1 //
    2 // Copyright (c) 2003, 2021, Oracle and/or its affiliates. All rights reserved.
    3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
    4 //
    5 // This code is free software; you can redistribute it and/or modify it
    6 // under the terms of the GNU General Public License version 2 only, as
    7 // published by the Free Software Foundation.
    8 //
    9 // This code is distributed in the hope that it will be useful, but WITHOUT
   10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
   11 // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
   12 // version 2 for more details (a copy is included in the LICENSE file that
   13 // accompanied this code).
   14 //
   15 // You should have received a copy of the GNU General Public License version
   16 // 2 along with this work; if not, write to the Free Software Foundation,
   17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
   18 //
   19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
   20 // or visit www.oracle.com if you need additional information or have any
   21 // questions.
   22 //
   23 //
   24 
   25 // AMD64 Architecture Description File
   26 
   27 //----------REGISTER DEFINITION BLOCK------------------------------------------
   28 // This information is used by the matcher and the register allocator to
   29 // describe individual registers and classes of registers within the target
   30 // archtecture.
   31 
   32 register %{
   33 //----------Architecture Description Register Definitions----------------------
   34 // General Registers
   35 // "reg_def"  name ( register save type, C convention save type,
   36 //                   ideal register type, encoding );
   37 // Register Save Types:
   38 //
   39 // NS  = No-Save:       The register allocator assumes that these registers
   40 //                      can be used without saving upon entry to the method, &
   41 //                      that they do not need to be saved at call sites.
   42 //
   43 // SOC = Save-On-Call:  The register allocator assumes that these registers
   44 //                      can be used without saving upon entry to the method,
   45 //                      but that they must be saved at call sites.
   46 //
   47 // SOE = Save-On-Entry: The register allocator assumes that these registers
   48 //                      must be saved before using them upon entry to the
   49 //                      method, but they do not need to be saved at call
   50 //                      sites.
   51 //
   52 // AS  = Always-Save:   The register allocator assumes that these registers
   53 //                      must be saved before using them upon entry to the
   54 //                      method, & that they must be saved at call sites.
   55 //
   56 // Ideal Register Type is used to determine how to save & restore a
   57 // register.  Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
   58 // spilled with LoadP/StoreP.  If the register supports both, use Op_RegI.
   59 //
   60 // The encoding number is the actual bit-pattern placed into the opcodes.
   61 
   62 // General Registers
   63 // R8-R15 must be encoded with REX.  (RSP, RBP, RSI, RDI need REX when
   64 // used as byte registers)
   65 
   66 // Previously set RBX, RSI, and RDI as save-on-entry for java code
   67 // Turn off SOE in java-code due to frequent use of uncommon-traps.
   68 // Now that allocator is better, turn on RSI and RDI as SOE registers.
   69 
   70 reg_def RAX  (SOC, SOC, Op_RegI,  0, rax->as_VMReg());
   71 reg_def RAX_H(SOC, SOC, Op_RegI,  0, rax->as_VMReg()->next());
   72 
   73 reg_def RCX  (SOC, SOC, Op_RegI,  1, rcx->as_VMReg());
   74 reg_def RCX_H(SOC, SOC, Op_RegI,  1, rcx->as_VMReg()->next());
   75 
   76 reg_def RDX  (SOC, SOC, Op_RegI,  2, rdx->as_VMReg());
   77 reg_def RDX_H(SOC, SOC, Op_RegI,  2, rdx->as_VMReg()->next());
   78 
   79 reg_def RBX  (SOC, SOE, Op_RegI,  3, rbx->as_VMReg());
   80 reg_def RBX_H(SOC, SOE, Op_RegI,  3, rbx->as_VMReg()->next());
   81 
   82 reg_def RSP  (NS,  NS,  Op_RegI,  4, rsp->as_VMReg());
   83 reg_def RSP_H(NS,  NS,  Op_RegI,  4, rsp->as_VMReg()->next());
   84 
   85 // now that adapter frames are gone RBP is always saved and restored by the prolog/epilog code
   86 reg_def RBP  (NS, SOE, Op_RegI,  5, rbp->as_VMReg());
   87 reg_def RBP_H(NS, SOE, Op_RegI,  5, rbp->as_VMReg()->next());
   88 
   89 #ifdef _WIN64
   90 
   91 reg_def RSI  (SOC, SOE, Op_RegI,  6, rsi->as_VMReg());
   92 reg_def RSI_H(SOC, SOE, Op_RegI,  6, rsi->as_VMReg()->next());
   93 
   94 reg_def RDI  (SOC, SOE, Op_RegI,  7, rdi->as_VMReg());
   95 reg_def RDI_H(SOC, SOE, Op_RegI,  7, rdi->as_VMReg()->next());
   96 
   97 #else
   98 
   99 reg_def RSI  (SOC, SOC, Op_RegI,  6, rsi->as_VMReg());
  100 reg_def RSI_H(SOC, SOC, Op_RegI,  6, rsi->as_VMReg()->next());
  101 
  102 reg_def RDI  (SOC, SOC, Op_RegI,  7, rdi->as_VMReg());
  103 reg_def RDI_H(SOC, SOC, Op_RegI,  7, rdi->as_VMReg()->next());
  104 
  105 #endif
  106 
  107 reg_def R8   (SOC, SOC, Op_RegI,  8, r8->as_VMReg());
  108 reg_def R8_H (SOC, SOC, Op_RegI,  8, r8->as_VMReg()->next());
  109 
  110 reg_def R9   (SOC, SOC, Op_RegI,  9, r9->as_VMReg());
  111 reg_def R9_H (SOC, SOC, Op_RegI,  9, r9->as_VMReg()->next());
  112 
  113 reg_def R10  (SOC, SOC, Op_RegI, 10, r10->as_VMReg());
  114 reg_def R10_H(SOC, SOC, Op_RegI, 10, r10->as_VMReg()->next());
  115 
  116 reg_def R11  (SOC, SOC, Op_RegI, 11, r11->as_VMReg());
  117 reg_def R11_H(SOC, SOC, Op_RegI, 11, r11->as_VMReg()->next());
  118 
  119 reg_def R12  (SOC, SOE, Op_RegI, 12, r12->as_VMReg());
  120 reg_def R12_H(SOC, SOE, Op_RegI, 12, r12->as_VMReg()->next());
  121 
  122 reg_def R13  (SOC, SOE, Op_RegI, 13, r13->as_VMReg());
  123 reg_def R13_H(SOC, SOE, Op_RegI, 13, r13->as_VMReg()->next());
  124 
  125 reg_def R14  (SOC, SOE, Op_RegI, 14, r14->as_VMReg());
  126 reg_def R14_H(SOC, SOE, Op_RegI, 14, r14->as_VMReg()->next());
  127 
  128 reg_def R15  (SOC, SOE, Op_RegI, 15, r15->as_VMReg());
  129 reg_def R15_H(SOC, SOE, Op_RegI, 15, r15->as_VMReg()->next());
  130 
  131 
  132 // Floating Point Registers
  133 
  134 // Specify priority of register selection within phases of register
  135 // allocation.  Highest priority is first.  A useful heuristic is to
  136 // give registers a low priority when they are required by machine
  137 // instructions, like EAX and EDX on I486, and choose no-save registers
  138 // before save-on-call, & save-on-call before save-on-entry.  Registers
  139 // which participate in fixed calling sequences should come last.
  140 // Registers which are used as pairs must fall on an even boundary.
  141 
  142 alloc_class chunk0(R10,         R10_H,
  143                    R11,         R11_H,
  144                    R8,          R8_H,
  145                    R9,          R9_H,
  146                    R12,         R12_H,
  147                    RCX,         RCX_H,
  148                    RBX,         RBX_H,
  149                    RDI,         RDI_H,
  150                    RDX,         RDX_H,
  151                    RSI,         RSI_H,
  152                    RAX,         RAX_H,
  153                    RBP,         RBP_H,
  154                    R13,         R13_H,
  155                    R14,         R14_H,
  156                    R15,         R15_H,
  157                    RSP,         RSP_H);
  158 
  159 
  160 //----------Architecture Description Register Classes--------------------------
  161 // Several register classes are automatically defined based upon information in
  162 // this architecture description.
  163 // 1) reg_class inline_cache_reg           ( /* as def'd in frame section */ )
  164 // 2) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
  165 //
  166 
  167 // Empty register class.
  168 reg_class no_reg();
  169 
  170 // Class for all pointer/long registers
  171 reg_class all_reg(RAX, RAX_H,
  172                   RDX, RDX_H,
  173                   RBP, RBP_H,
  174                   RDI, RDI_H,
  175                   RSI, RSI_H,
  176                   RCX, RCX_H,
  177                   RBX, RBX_H,
  178                   RSP, RSP_H,
  179                   R8,  R8_H,
  180                   R9,  R9_H,
  181                   R10, R10_H,
  182                   R11, R11_H,
  183                   R12, R12_H,
  184                   R13, R13_H,
  185                   R14, R14_H,
  186                   R15, R15_H);
  187 
  188 // Class for all int registers
  189 reg_class all_int_reg(RAX
  190                       RDX,
  191                       RBP,
  192                       RDI,
  193                       RSI,
  194                       RCX,
  195                       RBX,
  196                       R8,
  197                       R9,
  198                       R10,
  199                       R11,
  200                       R12,
  201                       R13,
  202                       R14);
  203 
  204 // Class for all pointer registers
  205 reg_class any_reg %{
  206   return _ANY_REG_mask;
  207 %}
  208 
  209 // Class for all pointer registers (excluding RSP)
  210 reg_class ptr_reg %{
  211   return _PTR_REG_mask;
  212 %}
  213 
  214 // Class for all pointer registers (excluding RSP and RBP)
  215 reg_class ptr_reg_no_rbp %{
  216   return _PTR_REG_NO_RBP_mask;
  217 %}
  218 
  219 // Class for all pointer registers (excluding RAX and RSP)
  220 reg_class ptr_no_rax_reg %{
  221   return _PTR_NO_RAX_REG_mask;
  222 %}
  223 
  224 // Class for all pointer registers (excluding RAX, RBX, and RSP)
  225 reg_class ptr_no_rax_rbx_reg %{
  226   return _PTR_NO_RAX_RBX_REG_mask;
  227 %}
  228 
  229 // Class for all long registers (excluding RSP)
  230 reg_class long_reg %{
  231   return _LONG_REG_mask;
  232 %}
  233 
  234 // Class for all long registers (excluding RAX, RDX and RSP)
  235 reg_class long_no_rax_rdx_reg %{
  236   return _LONG_NO_RAX_RDX_REG_mask;
  237 %}
  238 
  239 // Class for all long registers (excluding RCX and RSP)
  240 reg_class long_no_rcx_reg %{
  241   return _LONG_NO_RCX_REG_mask;
  242 %}
  243 
  244 // Class for all int registers (excluding RSP)
  245 reg_class int_reg %{
  246   return _INT_REG_mask;
  247 %}
  248 
  249 // Class for all int registers (excluding RAX, RDX, and RSP)
  250 reg_class int_no_rax_rdx_reg %{
  251   return _INT_NO_RAX_RDX_REG_mask;
  252 %}
  253 
  254 // Class for all int registers (excluding RCX and RSP)
  255 reg_class int_no_rcx_reg %{
  256   return _INT_NO_RCX_REG_mask;
  257 %}
  258 
  259 // Singleton class for RAX pointer register
  260 reg_class ptr_rax_reg(RAX, RAX_H);
  261 
  262 // Singleton class for RBX pointer register
  263 reg_class ptr_rbx_reg(RBX, RBX_H);
  264 
  265 // Singleton class for RSI pointer register
  266 reg_class ptr_rsi_reg(RSI, RSI_H);
  267 
  268 // Singleton class for RBP pointer register
  269 reg_class ptr_rbp_reg(RBP, RBP_H);
  270 
  271 // Singleton class for RDI pointer register
  272 reg_class ptr_rdi_reg(RDI, RDI_H);
  273 
  274 // Singleton class for stack pointer
  275 reg_class ptr_rsp_reg(RSP, RSP_H);
  276 
  277 // Singleton class for TLS pointer
  278 reg_class ptr_r15_reg(R15, R15_H);
  279 
  280 // Singleton class for RAX long register
  281 reg_class long_rax_reg(RAX, RAX_H);
  282 
  283 // Singleton class for RCX long register
  284 reg_class long_rcx_reg(RCX, RCX_H);
  285 
  286 // Singleton class for RDX long register
  287 reg_class long_rdx_reg(RDX, RDX_H);
  288 
  289 // Singleton class for RAX int register
  290 reg_class int_rax_reg(RAX);
  291 
  292 // Singleton class for RBX int register
  293 reg_class int_rbx_reg(RBX);
  294 
  295 // Singleton class for RCX int register
  296 reg_class int_rcx_reg(RCX);
  297 
  298 // Singleton class for RCX int register
  299 reg_class int_rdx_reg(RDX);
  300 
  301 // Singleton class for RCX int register
  302 reg_class int_rdi_reg(RDI);
  303 
  304 // Singleton class for instruction pointer
  305 // reg_class ip_reg(RIP);
  306 
  307 %}
  308 
  309 //----------SOURCE BLOCK-------------------------------------------------------
  310 // This is a block of C++ code which provides values, functions, and
  311 // definitions necessary in the rest of the architecture description
  312 source_hpp %{
  313 
  314 extern RegMask _ANY_REG_mask;
  315 extern RegMask _PTR_REG_mask;
  316 extern RegMask _PTR_REG_NO_RBP_mask;
  317 extern RegMask _PTR_NO_RAX_REG_mask;
  318 extern RegMask _PTR_NO_RAX_RBX_REG_mask;
  319 extern RegMask _LONG_REG_mask;
  320 extern RegMask _LONG_NO_RAX_RDX_REG_mask;
  321 extern RegMask _LONG_NO_RCX_REG_mask;
  322 extern RegMask _INT_REG_mask;
  323 extern RegMask _INT_NO_RAX_RDX_REG_mask;
  324 extern RegMask _INT_NO_RCX_REG_mask;
  325 
  326 extern RegMask _STACK_OR_PTR_REG_mask;
  327 extern RegMask _STACK_OR_LONG_REG_mask;
  328 extern RegMask _STACK_OR_INT_REG_mask;
  329 
  330 inline const RegMask& STACK_OR_PTR_REG_mask()  { return _STACK_OR_PTR_REG_mask;  }
  331 inline const RegMask& STACK_OR_LONG_REG_mask() { return _STACK_OR_LONG_REG_mask; }
  332 inline const RegMask& STACK_OR_INT_REG_mask()  { return _STACK_OR_INT_REG_mask;  }
  333 
  334 %}
  335 
  336 source %{
  337 #define   RELOC_IMM64    Assembler::imm_operand
  338 #define   RELOC_DISP32   Assembler::disp32_operand
  339 
  340 #define __ _masm.
  341 
  342 RegMask _ANY_REG_mask;
  343 RegMask _PTR_REG_mask;
  344 RegMask _PTR_REG_NO_RBP_mask;
  345 RegMask _PTR_NO_RAX_REG_mask;
  346 RegMask _PTR_NO_RAX_RBX_REG_mask;
  347 RegMask _LONG_REG_mask;
  348 RegMask _LONG_NO_RAX_RDX_REG_mask;
  349 RegMask _LONG_NO_RCX_REG_mask;
  350 RegMask _INT_REG_mask;
  351 RegMask _INT_NO_RAX_RDX_REG_mask;
  352 RegMask _INT_NO_RCX_REG_mask;
  353 RegMask _STACK_OR_PTR_REG_mask;
  354 RegMask _STACK_OR_LONG_REG_mask;
  355 RegMask _STACK_OR_INT_REG_mask;
  356 
  357 static bool need_r12_heapbase() {
  358   return UseCompressedOops;
  359 }
  360 
  361 void reg_mask_init() {
  362   // _ALL_REG_mask is generated by adlc from the all_reg register class below.
  363   // We derive a number of subsets from it.
  364   _ANY_REG_mask = _ALL_REG_mask;
  365 
  366   if (PreserveFramePointer) {
  367     _ANY_REG_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()));
  368     _ANY_REG_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()->next()));
  369   }
  370   if (need_r12_heapbase()) {
  371     _ANY_REG_mask.Remove(OptoReg::as_OptoReg(r12->as_VMReg()));
  372     _ANY_REG_mask.Remove(OptoReg::as_OptoReg(r12->as_VMReg()->next()));
  373   }
  374 
  375   _PTR_REG_mask = _ANY_REG_mask;
  376   _PTR_REG_mask.Remove(OptoReg::as_OptoReg(rsp->as_VMReg()));
  377   _PTR_REG_mask.Remove(OptoReg::as_OptoReg(rsp->as_VMReg()->next()));
  378   _PTR_REG_mask.Remove(OptoReg::as_OptoReg(r15->as_VMReg()));
  379   _PTR_REG_mask.Remove(OptoReg::as_OptoReg(r15->as_VMReg()->next()));
  380 
  381   _STACK_OR_PTR_REG_mask = _PTR_REG_mask;
  382   _STACK_OR_PTR_REG_mask.OR(STACK_OR_STACK_SLOTS_mask());
  383 
  384   _PTR_REG_NO_RBP_mask = _PTR_REG_mask;
  385   _PTR_REG_NO_RBP_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()));
  386   _PTR_REG_NO_RBP_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()->next()));
  387 
  388   _PTR_NO_RAX_REG_mask = _PTR_REG_mask;
  389   _PTR_NO_RAX_REG_mask.Remove(OptoReg::as_OptoReg(rax->as_VMReg()));
  390   _PTR_NO_RAX_REG_mask.Remove(OptoReg::as_OptoReg(rax->as_VMReg()->next()));
  391 
  392   _PTR_NO_RAX_RBX_REG_mask = _PTR_NO_RAX_REG_mask;
  393   _PTR_NO_RAX_RBX_REG_mask.Remove(OptoReg::as_OptoReg(rbx->as_VMReg()));
  394   _PTR_NO_RAX_RBX_REG_mask.Remove(OptoReg::as_OptoReg(rbx->as_VMReg()->next()));
  395 
  396   _LONG_REG_mask = _PTR_REG_mask;
  397   _STACK_OR_LONG_REG_mask = _LONG_REG_mask;
  398   _STACK_OR_LONG_REG_mask.OR(STACK_OR_STACK_SLOTS_mask());
  399 
  400   _LONG_NO_RAX_RDX_REG_mask = _LONG_REG_mask;
  401   _LONG_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rax->as_VMReg()));
  402   _LONG_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rax->as_VMReg()->next()));
  403   _LONG_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rdx->as_VMReg()));
  404   _LONG_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rdx->as_VMReg()->next()));
  405 
  406   _LONG_NO_RCX_REG_mask = _LONG_REG_mask;
  407   _LONG_NO_RCX_REG_mask.Remove(OptoReg::as_OptoReg(rcx->as_VMReg()));
  408   _LONG_NO_RCX_REG_mask.Remove(OptoReg::as_OptoReg(rcx->as_VMReg()->next()));
  409 
  410   _INT_REG_mask = _ALL_INT_REG_mask;
  411   if (PreserveFramePointer) {
  412     _INT_REG_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()));
  413   }
  414   if (need_r12_heapbase()) {
  415     _INT_REG_mask.Remove(OptoReg::as_OptoReg(r12->as_VMReg()));
  416   }
  417 
  418   _STACK_OR_INT_REG_mask = _INT_REG_mask;
  419   _STACK_OR_INT_REG_mask.OR(STACK_OR_STACK_SLOTS_mask());
  420 
  421   _INT_NO_RAX_RDX_REG_mask = _INT_REG_mask;
  422   _INT_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rax->as_VMReg()));
  423   _INT_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rdx->as_VMReg()));
  424 
  425   _INT_NO_RCX_REG_mask = _INT_REG_mask;
  426   _INT_NO_RCX_REG_mask.Remove(OptoReg::as_OptoReg(rcx->as_VMReg()));
  427 
  428   if (Matcher::has_predicated_vectors()) {
  429     // Post-loop multi-versioning expects mask to be present in K1 register, till the time
  430     // its fixed, RA should not be allocting K1 register, this shall prevent any accidental
  431     // curruption of value held in K1 register.
  432     if (PostLoopMultiversioning) {
  433       const_cast<RegMask*>(&_VECTMASK_REG_mask)->Remove(OptoReg::as_OptoReg(k1->as_VMReg()));
  434       const_cast<RegMask*>(&_VECTMASK_REG_mask)->Remove(OptoReg::as_OptoReg(k1->as_VMReg()->next()));
  435     }
  436   }
  437 }
  438 
  439 static bool generate_vzeroupper(Compile* C) {
  440   return (VM_Version::supports_vzeroupper() && (C->max_vector_size() > 16 || C->clear_upper_avx() == true)) ? true: false;  // Generate vzeroupper
  441 }
  442 
  443 static int clear_avx_size() {
  444   return generate_vzeroupper(Compile::current()) ? 3: 0;  // vzeroupper
  445 }
  446 
  447 // !!!!! Special hack to get all types of calls to specify the byte offset
  448 //       from the start of the call to the point where the return address
  449 //       will point.
  450 int MachCallStaticJavaNode::ret_addr_offset()
  451 {
  452   int offset = 5; // 5 bytes from start of call to where return address points
  453   offset += clear_avx_size();
  454   return offset;
  455 }
  456 
  457 int MachCallDynamicJavaNode::ret_addr_offset()
  458 {
  459   int offset = 15; // 15 bytes from start of call to where return address points
  460   offset += clear_avx_size();
  461   return offset;
  462 }
  463 
  464 int MachCallRuntimeNode::ret_addr_offset() {
  465   int offset = 13; // movq r10,#addr; callq (r10)
  466   if (this->ideal_Opcode() != Op_CallLeafVector) {
  467     offset += clear_avx_size();
  468   }
  469   return offset;
  470 }
  471 
  472 int MachCallNativeNode::ret_addr_offset() {
  473   int offset = 13; // movq r10,#addr; callq (r10)
  474   offset += clear_avx_size();
  475   return offset;
  476 }
  477 //
  478 // Compute padding required for nodes which need alignment
  479 //
  480 
  481 // The address of the call instruction needs to be 4-byte aligned to
  482 // ensure that it does not span a cache line so that it can be patched.
  483 int CallStaticJavaDirectNode::compute_padding(int current_offset) const
  484 {
  485   current_offset += clear_avx_size(); // skip vzeroupper
  486   current_offset += 1; // skip call opcode byte
  487   return align_up(current_offset, alignment_required()) - current_offset;
  488 }
  489 
  490 // The address of the call instruction needs to be 4-byte aligned to
  491 // ensure that it does not span a cache line so that it can be patched.
  492 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const
  493 {
  494   current_offset += clear_avx_size(); // skip vzeroupper
  495   current_offset += 11; // skip movq instruction + call opcode byte
  496   return align_up(current_offset, alignment_required()) - current_offset;
  497 }
  498 
  499 // EMIT_RM()
  500 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
  501   unsigned char c = (unsigned char) ((f1 << 6) | (f2 << 3) | f3);
  502   cbuf.insts()->emit_int8(c);
  503 }
  504 
  505 // EMIT_CC()
  506 void emit_cc(CodeBuffer &cbuf, int f1, int f2) {
  507   unsigned char c = (unsigned char) (f1 | f2);
  508   cbuf.insts()->emit_int8(c);
  509 }
  510 
  511 // EMIT_OPCODE()
  512 void emit_opcode(CodeBuffer &cbuf, int code) {
  513   cbuf.insts()->emit_int8((unsigned char) code);
  514 }
  515 
  516 // EMIT_OPCODE() w/ relocation information
  517 void emit_opcode(CodeBuffer &cbuf,
  518                  int code, relocInfo::relocType reloc, int offset, int format)
  519 {
  520   cbuf.relocate(cbuf.insts_mark() + offset, reloc, format);
  521   emit_opcode(cbuf, code);
  522 }
  523 
  524 // EMIT_D8()
  525 void emit_d8(CodeBuffer &cbuf, int d8) {
  526   cbuf.insts()->emit_int8((unsigned char) d8);
  527 }
  528 
  529 // EMIT_D16()
  530 void emit_d16(CodeBuffer &cbuf, int d16) {
  531   cbuf.insts()->emit_int16(d16);
  532 }
  533 
  534 // EMIT_D32()
  535 void emit_d32(CodeBuffer &cbuf, int d32) {
  536   cbuf.insts()->emit_int32(d32);
  537 }
  538 
  539 // EMIT_D64()
  540 void emit_d64(CodeBuffer &cbuf, int64_t d64) {
  541   cbuf.insts()->emit_int64(d64);
  542 }
  543 
  544 // emit 32 bit value and construct relocation entry from relocInfo::relocType
  545 void emit_d32_reloc(CodeBuffer& cbuf,
  546                     int d32,
  547                     relocInfo::relocType reloc,
  548                     int format)
  549 {
  550   assert(reloc != relocInfo::external_word_type, "use 2-arg emit_d32_reloc");
  551   cbuf.relocate(cbuf.insts_mark(), reloc, format);
  552   cbuf.insts()->emit_int32(d32);
  553 }
  554 
  555 // emit 32 bit value and construct relocation entry from RelocationHolder
  556 void emit_d32_reloc(CodeBuffer& cbuf, int d32, RelocationHolder const& rspec, int format) {
  557 #ifdef ASSERT
  558   if (rspec.reloc()->type() == relocInfo::oop_type &&
  559       d32 != 0 && d32 != (intptr_t) Universe::non_oop_word()) {
  560     assert(Universe::heap()->is_in((address)(intptr_t)d32), "should be real oop");
  561     assert(oopDesc::is_oop(cast_to_oop((intptr_t)d32)), "cannot embed broken oops in code");
  562   }
  563 #endif
  564   cbuf.relocate(cbuf.insts_mark(), rspec, format);
  565   cbuf.insts()->emit_int32(d32);
  566 }
  567 
  568 void emit_d32_reloc(CodeBuffer& cbuf, address addr) {
  569   address next_ip = cbuf.insts_end() + 4;
  570   emit_d32_reloc(cbuf, (int) (addr - next_ip),
  571                  external_word_Relocation::spec(addr),
  572                  RELOC_DISP32);
  573 }
  574 
  575 
  576 // emit 64 bit value and construct relocation entry from relocInfo::relocType
  577 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, relocInfo::relocType reloc, int format) {
  578   cbuf.relocate(cbuf.insts_mark(), reloc, format);
  579   cbuf.insts()->emit_int64(d64);
  580 }
  581 
  582 // emit 64 bit value and construct relocation entry from RelocationHolder
  583 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, RelocationHolder const& rspec, int format) {
  584 #ifdef ASSERT
  585   if (rspec.reloc()->type() == relocInfo::oop_type &&
  586       d64 != 0 && d64 != (int64_t) Universe::non_oop_word()) {
  587     assert(Universe::heap()->is_in((address)d64), "should be real oop");
  588     assert(oopDesc::is_oop(cast_to_oop(d64)), "cannot embed broken oops in code");
  589   }
  590 #endif
  591   cbuf.relocate(cbuf.insts_mark(), rspec, format);
  592   cbuf.insts()->emit_int64(d64);
  593 }
  594 
  595 // Access stack slot for load or store
  596 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp)
  597 {
  598   emit_opcode(cbuf, opcode);                  // (e.g., FILD   [RSP+src])
  599   if (-0x80 <= disp && disp < 0x80) {
  600     emit_rm(cbuf, 0x01, rm_field, RSP_enc);   // R/M byte
  601     emit_rm(cbuf, 0x00, RSP_enc, RSP_enc);    // SIB byte
  602     emit_d8(cbuf, disp);     // Displacement  // R/M byte
  603   } else {
  604     emit_rm(cbuf, 0x02, rm_field, RSP_enc);   // R/M byte
  605     emit_rm(cbuf, 0x00, RSP_enc, RSP_enc);    // SIB byte
  606     emit_d32(cbuf, disp);     // Displacement // R/M byte
  607   }
  608 }
  609 
  610    // rRegI ereg, memory mem) %{    // emit_reg_mem
  611 void encode_RegMem(CodeBuffer &cbuf,
  612                    int reg,
  613                    int base, int index, int scale, int disp, relocInfo::relocType disp_reloc)
  614 {
  615   assert(disp_reloc == relocInfo::none, "cannot have disp");
  616   int regenc = reg & 7;
  617   int baseenc = base & 7;
  618   int indexenc = index & 7;
  619 
  620   // There is no index & no scale, use form without SIB byte
  621   if (index == 0x4 && scale == 0 && base != RSP_enc && base != R12_enc) {
  622     // If no displacement, mode is 0x0; unless base is [RBP] or [R13]
  623     if (disp == 0 && base != RBP_enc && base != R13_enc) {
  624       emit_rm(cbuf, 0x0, regenc, baseenc); // *
  625     } else if (-0x80 <= disp && disp < 0x80 && disp_reloc == relocInfo::none) {
  626       // If 8-bit displacement, mode 0x1
  627       emit_rm(cbuf, 0x1, regenc, baseenc); // *
  628       emit_d8(cbuf, disp);
  629     } else {
  630       // If 32-bit displacement
  631       if (base == -1) { // Special flag for absolute address
  632         emit_rm(cbuf, 0x0, regenc, 0x5); // *
  633         if (disp_reloc != relocInfo::none) {
  634           emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
  635         } else {
  636           emit_d32(cbuf, disp);
  637         }
  638       } else {
  639         // Normal base + offset
  640         emit_rm(cbuf, 0x2, regenc, baseenc); // *
  641         if (disp_reloc != relocInfo::none) {
  642           emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
  643         } else {
  644           emit_d32(cbuf, disp);
  645         }
  646       }
  647     }
  648   } else {
  649     // Else, encode with the SIB byte
  650     // If no displacement, mode is 0x0; unless base is [RBP] or [R13]
  651     if (disp == 0 && base != RBP_enc && base != R13_enc) {
  652       // If no displacement
  653       emit_rm(cbuf, 0x0, regenc, 0x4); // *
  654       emit_rm(cbuf, scale, indexenc, baseenc);
  655     } else {
  656       if (-0x80 <= disp && disp < 0x80 && disp_reloc == relocInfo::none) {
  657         // If 8-bit displacement, mode 0x1
  658         emit_rm(cbuf, 0x1, regenc, 0x4); // *
  659         emit_rm(cbuf, scale, indexenc, baseenc);
  660         emit_d8(cbuf, disp);
  661       } else {
  662         // If 32-bit displacement
  663         if (base == 0x04 ) {
  664           emit_rm(cbuf, 0x2, regenc, 0x4);
  665           emit_rm(cbuf, scale, indexenc, 0x04); // XXX is this valid???
  666         } else {
  667           emit_rm(cbuf, 0x2, regenc, 0x4);
  668           emit_rm(cbuf, scale, indexenc, baseenc); // *
  669         }
  670         if (disp_reloc != relocInfo::none) {
  671           emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
  672         } else {
  673           emit_d32(cbuf, disp);
  674         }
  675       }
  676     }
  677   }
  678 }
  679 
  680 // This could be in MacroAssembler but it's fairly C2 specific
  681 void emit_cmpfp_fixup(MacroAssembler& _masm) {
  682   Label exit;
  683   __ jccb(Assembler::noParity, exit);
  684   __ pushf();
  685   //
  686   // comiss/ucomiss instructions set ZF,PF,CF flags and
  687   // zero OF,AF,SF for NaN values.
  688   // Fixup flags by zeroing ZF,PF so that compare of NaN
  689   // values returns 'less than' result (CF is set).
  690   // Leave the rest of flags unchanged.
  691   //
  692   //    7 6 5 4 3 2 1 0
  693   //   |S|Z|r|A|r|P|r|C|  (r - reserved bit)
  694   //    0 0 1 0 1 0 1 1   (0x2B)
  695   //
  696   __ andq(Address(rsp, 0), 0xffffff2b);
  697   __ popf();
  698   __ bind(exit);
  699 }
  700 
  701 void emit_cmpfp3(MacroAssembler& _masm, Register dst) {
  702   Label done;
  703   __ movl(dst, -1);
  704   __ jcc(Assembler::parity, done);
  705   __ jcc(Assembler::below, done);
  706   __ setb(Assembler::notEqual, dst);
  707   __ movzbl(dst, dst);
  708   __ bind(done);
  709 }
  710 
  711 // Math.min()    # Math.max()
  712 // --------------------------
  713 // ucomis[s/d]   #
  714 // ja   -> b     # a
  715 // jp   -> NaN   # NaN
  716 // jb   -> a     # b
  717 // je            #
  718 // |-jz -> a | b # a & b
  719 // |    -> a     #
  720 void emit_fp_min_max(MacroAssembler& _masm, XMMRegister dst,
  721                      XMMRegister a, XMMRegister b,
  722                      XMMRegister xmmt, Register rt,
  723                      bool min, bool single) {
  724 
  725   Label nan, zero, below, above, done;
  726 
  727   if (single)
  728     __ ucomiss(a, b);
  729   else
  730     __ ucomisd(a, b);
  731 
  732   if (dst->encoding() != (min ? b : a)->encoding())
  733     __ jccb(Assembler::above, above); // CF=0 & ZF=0
  734   else
  735     __ jccb(Assembler::above, done);
  736 
  737   __ jccb(Assembler::parity, nan);  // PF=1
  738   __ jccb(Assembler::below, below); // CF=1
  739 
  740   // equal
  741   __ vpxor(xmmt, xmmt, xmmt, Assembler::AVX_128bit);
  742   if (single) {
  743     __ ucomiss(a, xmmt);
  744     __ jccb(Assembler::equal, zero);
  745 
  746     __ movflt(dst, a);
  747     __ jmp(done);
  748   }
  749   else {
  750     __ ucomisd(a, xmmt);
  751     __ jccb(Assembler::equal, zero);
  752 
  753     __ movdbl(dst, a);
  754     __ jmp(done);
  755   }
  756 
  757   __ bind(zero);
  758   if (min)
  759     __ vpor(dst, a, b, Assembler::AVX_128bit);
  760   else
  761     __ vpand(dst, a, b, Assembler::AVX_128bit);
  762 
  763   __ jmp(done);
  764 
  765   __ bind(above);
  766   if (single)
  767     __ movflt(dst, min ? b : a);
  768   else
  769     __ movdbl(dst, min ? b : a);
  770 
  771   __ jmp(done);
  772 
  773   __ bind(nan);
  774   if (single) {
  775     __ movl(rt, 0x7fc00000); // Float.NaN
  776     __ movdl(dst, rt);
  777   }
  778   else {
  779     __ mov64(rt, 0x7ff8000000000000L); // Double.NaN
  780     __ movdq(dst, rt);
  781   }
  782   __ jmp(done);
  783 
  784   __ bind(below);
  785   if (single)
  786     __ movflt(dst, min ? a : b);
  787   else
  788     __ movdbl(dst, min ? a : b);
  789 
  790   __ bind(done);
  791 }
  792 
  793 //=============================================================================
  794 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;
  795 
  796 int ConstantTable::calculate_table_base_offset() const {
  797   return 0;  // absolute addressing, no offset
  798 }
  799 
  800 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
  801 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
  802   ShouldNotReachHere();
  803 }
  804 
  805 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
  806   // Empty encoding
  807 }
  808 
  809 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
  810   return 0;
  811 }
  812 
  813 #ifndef PRODUCT
  814 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
  815   st->print("# MachConstantBaseNode (empty encoding)");
  816 }
  817 #endif
  818 
  819 
  820 //=============================================================================
  821 #ifndef PRODUCT
  822 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
  823   Compile* C = ra_->C;
  824 
  825   int framesize = C->output()->frame_size_in_bytes();
  826   int bangsize = C->output()->bang_size_in_bytes();
  827   assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
  828   // Remove wordSize for return addr which is already pushed.
  829   framesize -= wordSize;
  830 
  831   if (C->output()->need_stack_bang(bangsize)) {
  832     framesize -= wordSize;
  833     st->print("# stack bang (%d bytes)", bangsize);
  834     st->print("\n\t");
  835     st->print("pushq   rbp\t# Save rbp");
  836     if (PreserveFramePointer) {
  837         st->print("\n\t");
  838         st->print("movq    rbp, rsp\t# Save the caller's SP into rbp");
  839     }
  840     if (framesize) {
  841       st->print("\n\t");
  842       st->print("subq    rsp, #%d\t# Create frame",framesize);
  843     }
  844   } else {
  845     st->print("subq    rsp, #%d\t# Create frame",framesize);
  846     st->print("\n\t");
  847     framesize -= wordSize;
  848     st->print("movq    [rsp + #%d], rbp\t# Save rbp",framesize);
  849     if (PreserveFramePointer) {
  850       st->print("\n\t");
  851       st->print("movq    rbp, rsp\t# Save the caller's SP into rbp");
  852       if (framesize > 0) {
  853         st->print("\n\t");
  854         st->print("addq    rbp, #%d", framesize);
  855       }
  856     }
  857   }
  858 
  859   if (VerifyStackAtCalls) {
  860     st->print("\n\t");
  861     framesize -= wordSize;
  862     st->print("movq    [rsp + #%d], 0xbadb100d\t# Majik cookie for stack depth check",framesize);
  863 #ifdef ASSERT
  864     st->print("\n\t");
  865     st->print("# stack alignment check");
  866 #endif
  867   }
  868   if (C->stub_function() != NULL && BarrierSet::barrier_set()->barrier_set_nmethod() != NULL) {
  869     st->print("\n\t");
  870     st->print("cmpl    [r15_thread + #disarmed_offset], #disarmed_value\t");
  871     st->print("\n\t");
  872     st->print("je      fast_entry\t");
  873     st->print("\n\t");
  874     st->print("call    #nmethod_entry_barrier_stub\t");
  875     st->print("\n\tfast_entry:");
  876   }
  877   st->cr();
  878 }
  879 #endif
  880 
  881 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
  882   Compile* C = ra_->C;
  883   MacroAssembler _masm(&cbuf);
  884 
  885   int framesize = C->output()->frame_size_in_bytes();
  886   int bangsize = C->output()->bang_size_in_bytes();
  887 
  888   if (C->clinit_barrier_on_entry()) {
  889     assert(VM_Version::supports_fast_class_init_checks(), "sanity");
  890     assert(!C->method()->holder()->is_not_initialized(), "initialization should have been started");
  891 
  892     Label L_skip_barrier;
  893     Register klass = rscratch1;
  894 
  895     __ mov_metadata(klass, C->method()->holder()->constant_encoding());
  896     __ clinit_barrier(klass, r15_thread, &L_skip_barrier /*L_fast_path*/);
  897 
  898     __ jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub())); // slow path
  899 
  900     __ bind(L_skip_barrier);
  901   }
  902 
  903   __ verified_entry(framesize, C->output()->need_stack_bang(bangsize)?bangsize:0, false, C->stub_function() != NULL);
  904 
  905   C->output()->set_frame_complete(cbuf.insts_size());
  906 
  907   if (C->has_mach_constant_base_node()) {
  908     // NOTE: We set the table base offset here because users might be
  909     // emitted before MachConstantBaseNode.
  910     ConstantTable& constant_table = C->output()->constant_table();
  911     constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
  912   }
  913 }
  914 
  915 uint MachPrologNode::size(PhaseRegAlloc* ra_) const
  916 {
  917   return MachNode::size(ra_); // too many variables; just compute it
  918                               // the hard way
  919 }
  920 
  921 int MachPrologNode::reloc() const
  922 {
  923   return 0; // a large enough number
  924 }
  925 
  926 //=============================================================================
  927 #ifndef PRODUCT
  928 void MachEpilogNode::format(PhaseRegAlloc* ra_, outputStream* st) const
  929 {
  930   Compile* C = ra_->C;
  931   if (generate_vzeroupper(C)) {
  932     st->print("vzeroupper");
  933     st->cr(); st->print("\t");
  934   }
  935 
  936   int framesize = C->output()->frame_size_in_bytes();
  937   assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
  938   // Remove word for return adr already pushed
  939   // and RBP
  940   framesize -= 2*wordSize;
  941 
  942   if (framesize) {
  943     st->print_cr("addq    rsp, %d\t# Destroy frame", framesize);
  944     st->print("\t");
  945   }
  946 
  947   st->print_cr("popq    rbp");
  948   if (do_polling() && C->is_method_compilation()) {
  949     st->print("\t");
  950     st->print_cr("cmpq     rsp, poll_offset[r15_thread] \n\t"
  951                  "ja       #safepoint_stub\t"
  952                  "# Safepoint: poll for GC");
  953   }
  954 }
  955 #endif
  956 
  957 void MachEpilogNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
  958 {
  959   Compile* C = ra_->C;
  960   MacroAssembler _masm(&cbuf);
  961 
  962   if (generate_vzeroupper(C)) {
  963     // Clear upper bits of YMM registers when current compiled code uses
  964     // wide vectors to avoid AVX <-> SSE transition penalty during call.
  965     __ vzeroupper();
  966   }
  967 
  968   int framesize = C->output()->frame_size_in_bytes();
  969   assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
  970   // Remove word for return adr already pushed
  971   // and RBP
  972   framesize -= 2*wordSize;
  973 
  974   // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here
  975 
  976   if (framesize) {
  977     emit_opcode(cbuf, Assembler::REX_W);
  978     if (framesize < 0x80) {
  979       emit_opcode(cbuf, 0x83); // addq rsp, #framesize
  980       emit_rm(cbuf, 0x3, 0x00, RSP_enc);
  981       emit_d8(cbuf, framesize);
  982     } else {
  983       emit_opcode(cbuf, 0x81); // addq rsp, #framesize
  984       emit_rm(cbuf, 0x3, 0x00, RSP_enc);
  985       emit_d32(cbuf, framesize);
  986     }
  987   }
  988 
  989   // popq rbp
  990   emit_opcode(cbuf, 0x58 | RBP_enc);
  991 
  992   if (StackReservedPages > 0 && C->has_reserved_stack_access()) {
  993     __ reserved_stack_check();
  994   }
  995 
  996   if (do_polling() && C->is_method_compilation()) {
  997     MacroAssembler _masm(&cbuf);
  998     Label dummy_label;
  999     Label* code_stub = &dummy_label;
 1000     if (!C->output()->in_scratch_emit_size()) {
 1001       code_stub = &C->output()->safepoint_poll_table()->add_safepoint(__ offset());
 1002     }
 1003     __ relocate(relocInfo::poll_return_type);
 1004     __ safepoint_poll(*code_stub, r15_thread, true /* at_return */, true /* in_nmethod */);
 1005   }
 1006 }
 1007 
 1008 uint MachEpilogNode::size(PhaseRegAlloc* ra_) const
 1009 {
 1010   return MachNode::size(ra_); // too many variables; just compute it
 1011                               // the hard way
 1012 }
 1013 
 1014 int MachEpilogNode::reloc() const
 1015 {
 1016   return 2; // a large enough number
 1017 }
 1018 
 1019 const Pipeline* MachEpilogNode::pipeline() const
 1020 {
 1021   return MachNode::pipeline_class();
 1022 }
 1023 
 1024 //=============================================================================
 1025 
 1026 enum RC {
 1027   rc_bad,
 1028   rc_int,
 1029   rc_kreg,
 1030   rc_float,
 1031   rc_stack
 1032 };
 1033 
 1034 static enum RC rc_class(OptoReg::Name reg)
 1035 {
 1036   if( !OptoReg::is_valid(reg)  ) return rc_bad;
 1037 
 1038   if (OptoReg::is_stack(reg)) return rc_stack;
 1039 
 1040   VMReg r = OptoReg::as_VMReg(reg);
 1041 
 1042   if (r->is_Register()) return rc_int;
 1043 
 1044   if (r->is_KRegister()) return rc_kreg;
 1045 
 1046   assert(r->is_XMMRegister(), "must be");
 1047   return rc_float;
 1048 }
 1049 
 1050 // Next two methods are shared by 32- and 64-bit VM. They are defined in x86.ad.
 1051 static void vec_mov_helper(CodeBuffer *cbuf, int src_lo, int dst_lo,
 1052                           int src_hi, int dst_hi, uint ireg, outputStream* st);
 1053 
 1054 void vec_spill_helper(CodeBuffer *cbuf, bool is_load,
 1055                      int stack_offset, int reg, uint ireg, outputStream* st);
 1056 
 1057 static void vec_stack_to_stack_helper(CodeBuffer *cbuf, int src_offset,
 1058                                       int dst_offset, uint ireg, outputStream* st) {
 1059   if (cbuf) {
 1060     MacroAssembler _masm(cbuf);
 1061     switch (ireg) {
 1062     case Op_VecS:
 1063       __ movq(Address(rsp, -8), rax);
 1064       __ movl(rax, Address(rsp, src_offset));
 1065       __ movl(Address(rsp, dst_offset), rax);
 1066       __ movq(rax, Address(rsp, -8));
 1067       break;
 1068     case Op_VecD:
 1069       __ pushq(Address(rsp, src_offset));
 1070       __ popq (Address(rsp, dst_offset));
 1071       break;
 1072     case Op_VecX:
 1073       __ pushq(Address(rsp, src_offset));
 1074       __ popq (Address(rsp, dst_offset));
 1075       __ pushq(Address(rsp, src_offset+8));
 1076       __ popq (Address(rsp, dst_offset+8));
 1077       break;
 1078     case Op_VecY:
 1079       __ vmovdqu(Address(rsp, -32), xmm0);
 1080       __ vmovdqu(xmm0, Address(rsp, src_offset));
 1081       __ vmovdqu(Address(rsp, dst_offset), xmm0);
 1082       __ vmovdqu(xmm0, Address(rsp, -32));
 1083       break;
 1084     case Op_VecZ:
 1085       __ evmovdquq(Address(rsp, -64), xmm0, 2);
 1086       __ evmovdquq(xmm0, Address(rsp, src_offset), 2);
 1087       __ evmovdquq(Address(rsp, dst_offset), xmm0, 2);
 1088       __ evmovdquq(xmm0, Address(rsp, -64), 2);
 1089       break;
 1090     default:
 1091       ShouldNotReachHere();
 1092     }
 1093 #ifndef PRODUCT
 1094   } else {
 1095     switch (ireg) {
 1096     case Op_VecS:
 1097       st->print("movq    [rsp - #8], rax\t# 32-bit mem-mem spill\n\t"
 1098                 "movl    rax, [rsp + #%d]\n\t"
 1099                 "movl    [rsp + #%d], rax\n\t"
 1100                 "movq    rax, [rsp - #8]",
 1101                 src_offset, dst_offset);
 1102       break;
 1103     case Op_VecD:
 1104       st->print("pushq   [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
 1105                 "popq    [rsp + #%d]",
 1106                 src_offset, dst_offset);
 1107       break;
 1108      case Op_VecX:
 1109       st->print("pushq   [rsp + #%d]\t# 128-bit mem-mem spill\n\t"
 1110                 "popq    [rsp + #%d]\n\t"
 1111                 "pushq   [rsp + #%d]\n\t"
 1112                 "popq    [rsp + #%d]",
 1113                 src_offset, dst_offset, src_offset+8, dst_offset+8);
 1114       break;
 1115     case Op_VecY:
 1116       st->print("vmovdqu [rsp - #32], xmm0\t# 256-bit mem-mem spill\n\t"
 1117                 "vmovdqu xmm0, [rsp + #%d]\n\t"
 1118                 "vmovdqu [rsp + #%d], xmm0\n\t"
 1119                 "vmovdqu xmm0, [rsp - #32]",
 1120                 src_offset, dst_offset);
 1121       break;
 1122     case Op_VecZ:
 1123       st->print("vmovdqu [rsp - #64], xmm0\t# 512-bit mem-mem spill\n\t"
 1124                 "vmovdqu xmm0, [rsp + #%d]\n\t"
 1125                 "vmovdqu [rsp + #%d], xmm0\n\t"
 1126                 "vmovdqu xmm0, [rsp - #64]",
 1127                 src_offset, dst_offset);
 1128       break;
 1129     default:
 1130       ShouldNotReachHere();
 1131     }
 1132 #endif
 1133   }
 1134 }
 1135 
 1136 uint MachSpillCopyNode::implementation(CodeBuffer* cbuf,
 1137                                        PhaseRegAlloc* ra_,
 1138                                        bool do_size,
 1139                                        outputStream* st) const {
 1140   assert(cbuf != NULL || st  != NULL, "sanity");
 1141   // Get registers to move
 1142   OptoReg::Name src_second = ra_->get_reg_second(in(1));
 1143   OptoReg::Name src_first = ra_->get_reg_first(in(1));
 1144   OptoReg::Name dst_second = ra_->get_reg_second(this);
 1145   OptoReg::Name dst_first = ra_->get_reg_first(this);
 1146 
 1147   enum RC src_second_rc = rc_class(src_second);
 1148   enum RC src_first_rc = rc_class(src_first);
 1149   enum RC dst_second_rc = rc_class(dst_second);
 1150   enum RC dst_first_rc = rc_class(dst_first);
 1151 
 1152   assert(OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first),
 1153          "must move at least 1 register" );
 1154 
 1155   if (src_first == dst_first && src_second == dst_second) {
 1156     // Self copy, no move
 1157     return 0;
 1158   }
 1159   if (bottom_type()->isa_vect() != NULL && bottom_type()->isa_vectmask() == NULL) {
 1160     uint ireg = ideal_reg();
 1161     assert((src_first_rc != rc_int && dst_first_rc != rc_int), "sanity");
 1162     assert((ireg == Op_VecS || ireg == Op_VecD || ireg == Op_VecX || ireg == Op_VecY || ireg == Op_VecZ ), "sanity");
 1163     if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
 1164       // mem -> mem
 1165       int src_offset = ra_->reg2offset(src_first);
 1166       int dst_offset = ra_->reg2offset(dst_first);
 1167       vec_stack_to_stack_helper(cbuf, src_offset, dst_offset, ireg, st);
 1168     } else if (src_first_rc == rc_float && dst_first_rc == rc_float ) {
 1169       vec_mov_helper(cbuf, src_first, dst_first, src_second, dst_second, ireg, st);
 1170     } else if (src_first_rc == rc_float && dst_first_rc == rc_stack ) {
 1171       int stack_offset = ra_->reg2offset(dst_first);
 1172       vec_spill_helper(cbuf, false, stack_offset, src_first, ireg, st);
 1173     } else if (src_first_rc == rc_stack && dst_first_rc == rc_float ) {
 1174       int stack_offset = ra_->reg2offset(src_first);
 1175       vec_spill_helper(cbuf, true,  stack_offset, dst_first, ireg, st);
 1176     } else {
 1177       ShouldNotReachHere();
 1178     }
 1179     return 0;
 1180   }
 1181   if (src_first_rc == rc_stack) {
 1182     // mem ->
 1183     if (dst_first_rc == rc_stack) {
 1184       // mem -> mem
 1185       assert(src_second != dst_first, "overlap");
 1186       if ((src_first & 1) == 0 && src_first + 1 == src_second &&
 1187           (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
 1188         // 64-bit
 1189         int src_offset = ra_->reg2offset(src_first);
 1190         int dst_offset = ra_->reg2offset(dst_first);
 1191         if (cbuf) {
 1192           MacroAssembler _masm(cbuf);
 1193           __ pushq(Address(rsp, src_offset));
 1194           __ popq (Address(rsp, dst_offset));
 1195 #ifndef PRODUCT
 1196         } else {
 1197           st->print("pushq   [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
 1198                     "popq    [rsp + #%d]",
 1199                      src_offset, dst_offset);
 1200 #endif
 1201         }
 1202       } else {
 1203         // 32-bit
 1204         assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
 1205         assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
 1206         // No pushl/popl, so:
 1207         int src_offset = ra_->reg2offset(src_first);
 1208         int dst_offset = ra_->reg2offset(dst_first);
 1209         if (cbuf) {
 1210           MacroAssembler _masm(cbuf);
 1211           __ movq(Address(rsp, -8), rax);
 1212           __ movl(rax, Address(rsp, src_offset));
 1213           __ movl(Address(rsp, dst_offset), rax);
 1214           __ movq(rax, Address(rsp, -8));
 1215 #ifndef PRODUCT
 1216         } else {
 1217           st->print("movq    [rsp - #8], rax\t# 32-bit mem-mem spill\n\t"
 1218                     "movl    rax, [rsp + #%d]\n\t"
 1219                     "movl    [rsp + #%d], rax\n\t"
 1220                     "movq    rax, [rsp - #8]",
 1221                      src_offset, dst_offset);
 1222 #endif
 1223         }
 1224       }
 1225       return 0;
 1226     } else if (dst_first_rc == rc_int) {
 1227       // mem -> gpr
 1228       if ((src_first & 1) == 0 && src_first + 1 == src_second &&
 1229           (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
 1230         // 64-bit
 1231         int offset = ra_->reg2offset(src_first);
 1232         if (cbuf) {
 1233           MacroAssembler _masm(cbuf);
 1234           __ movq(as_Register(Matcher::_regEncode[dst_first]), Address(rsp, offset));
 1235 #ifndef PRODUCT
 1236         } else {
 1237           st->print("movq    %s, [rsp + #%d]\t# spill",
 1238                      Matcher::regName[dst_first],
 1239                      offset);
 1240 #endif
 1241         }
 1242       } else {
 1243         // 32-bit
 1244         assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
 1245         assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
 1246         int offset = ra_->reg2offset(src_first);
 1247         if (cbuf) {
 1248           MacroAssembler _masm(cbuf);
 1249           __ movl(as_Register(Matcher::_regEncode[dst_first]), Address(rsp, offset));
 1250 #ifndef PRODUCT
 1251         } else {
 1252           st->print("movl    %s, [rsp + #%d]\t# spill",
 1253                      Matcher::regName[dst_first],
 1254                      offset);
 1255 #endif
 1256         }
 1257       }
 1258       return 0;
 1259     } else if (dst_first_rc == rc_float) {
 1260       // mem-> xmm
 1261       if ((src_first & 1) == 0 && src_first + 1 == src_second &&
 1262           (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
 1263         // 64-bit
 1264         int offset = ra_->reg2offset(src_first);
 1265         if (cbuf) {
 1266           MacroAssembler _masm(cbuf);
 1267           __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
 1268 #ifndef PRODUCT
 1269         } else {
 1270           st->print("%s  %s, [rsp + #%d]\t# spill",
 1271                      UseXmmLoadAndClearUpper ? "movsd " : "movlpd",
 1272                      Matcher::regName[dst_first],
 1273                      offset);
 1274 #endif
 1275         }
 1276       } else {
 1277         // 32-bit
 1278         assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
 1279         assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
 1280         int offset = ra_->reg2offset(src_first);
 1281         if (cbuf) {
 1282           MacroAssembler _masm(cbuf);
 1283           __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
 1284 #ifndef PRODUCT
 1285         } else {
 1286           st->print("movss   %s, [rsp + #%d]\t# spill",
 1287                      Matcher::regName[dst_first],
 1288                      offset);
 1289 #endif
 1290         }
 1291       }
 1292       return 0;
 1293     } else if (dst_first_rc == rc_kreg) {
 1294       // mem -> kreg
 1295       if ((src_first & 1) == 0 && src_first + 1 == src_second &&
 1296           (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
 1297         // 64-bit
 1298         int offset = ra_->reg2offset(src_first);
 1299         if (cbuf) {
 1300           MacroAssembler _masm(cbuf);
 1301           __ kmov(as_KRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
 1302 #ifndef PRODUCT
 1303         } else {
 1304           st->print("kmovq   %s, [rsp + #%d]\t# spill",
 1305                      Matcher::regName[dst_first],
 1306                      offset);
 1307 #endif
 1308         }
 1309       }
 1310       return 0;
 1311     }
 1312   } else if (src_first_rc == rc_int) {
 1313     // gpr ->
 1314     if (dst_first_rc == rc_stack) {
 1315       // gpr -> mem
 1316       if ((src_first & 1) == 0 && src_first + 1 == src_second &&
 1317           (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
 1318         // 64-bit
 1319         int offset = ra_->reg2offset(dst_first);
 1320         if (cbuf) {
 1321           MacroAssembler _masm(cbuf);
 1322           __ movq(Address(rsp, offset), as_Register(Matcher::_regEncode[src_first]));
 1323 #ifndef PRODUCT
 1324         } else {
 1325           st->print("movq    [rsp + #%d], %s\t# spill",
 1326                      offset,
 1327                      Matcher::regName[src_first]);
 1328 #endif
 1329         }
 1330       } else {
 1331         // 32-bit
 1332         assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
 1333         assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
 1334         int offset = ra_->reg2offset(dst_first);
 1335         if (cbuf) {
 1336           MacroAssembler _masm(cbuf);
 1337           __ movl(Address(rsp, offset), as_Register(Matcher::_regEncode[src_first]));
 1338 #ifndef PRODUCT
 1339         } else {
 1340           st->print("movl    [rsp + #%d], %s\t# spill",
 1341                      offset,
 1342                      Matcher::regName[src_first]);
 1343 #endif
 1344         }
 1345       }
 1346       return 0;
 1347     } else if (dst_first_rc == rc_int) {
 1348       // gpr -> gpr
 1349       if ((src_first & 1) == 0 && src_first + 1 == src_second &&
 1350           (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
 1351         // 64-bit
 1352         if (cbuf) {
 1353           MacroAssembler _masm(cbuf);
 1354           __ movq(as_Register(Matcher::_regEncode[dst_first]),
 1355                   as_Register(Matcher::_regEncode[src_first]));
 1356 #ifndef PRODUCT
 1357         } else {
 1358           st->print("movq    %s, %s\t# spill",
 1359                      Matcher::regName[dst_first],
 1360                      Matcher::regName[src_first]);
 1361 #endif
 1362         }
 1363         return 0;
 1364       } else {
 1365         // 32-bit
 1366         assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
 1367         assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
 1368         if (cbuf) {
 1369           MacroAssembler _masm(cbuf);
 1370           __ movl(as_Register(Matcher::_regEncode[dst_first]),
 1371                   as_Register(Matcher::_regEncode[src_first]));
 1372 #ifndef PRODUCT
 1373         } else {
 1374           st->print("movl    %s, %s\t# spill",
 1375                      Matcher::regName[dst_first],
 1376                      Matcher::regName[src_first]);
 1377 #endif
 1378         }
 1379         return 0;
 1380       }
 1381     } else if (dst_first_rc == rc_float) {
 1382       // gpr -> xmm
 1383       if ((src_first & 1) == 0 && src_first + 1 == src_second &&
 1384           (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
 1385         // 64-bit
 1386         if (cbuf) {
 1387           MacroAssembler _masm(cbuf);
 1388           __ movdq( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
 1389 #ifndef PRODUCT
 1390         } else {
 1391           st->print("movdq   %s, %s\t# spill",
 1392                      Matcher::regName[dst_first],
 1393                      Matcher::regName[src_first]);
 1394 #endif
 1395         }
 1396       } else {
 1397         // 32-bit
 1398         assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
 1399         assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
 1400         if (cbuf) {
 1401           MacroAssembler _masm(cbuf);
 1402           __ movdl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
 1403 #ifndef PRODUCT
 1404         } else {
 1405           st->print("movdl   %s, %s\t# spill",
 1406                      Matcher::regName[dst_first],
 1407                      Matcher::regName[src_first]);
 1408 #endif
 1409         }
 1410       }
 1411       return 0;
 1412     } else if (dst_first_rc == rc_kreg) {
 1413       if ((src_first & 1) == 0 && src_first + 1 == src_second &&
 1414           (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
 1415         // 64-bit
 1416         if (cbuf) {
 1417           MacroAssembler _masm(cbuf);
 1418           __ kmov(as_KRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
 1419   #ifndef PRODUCT
 1420         } else {
 1421            st->print("kmovq   %s, %s\t# spill",
 1422                        Matcher::regName[dst_first],
 1423                        Matcher::regName[src_first]);
 1424   #endif
 1425         }
 1426       }
 1427       Unimplemented();
 1428       return 0;
 1429     }
 1430   } else if (src_first_rc == rc_float) {
 1431     // xmm ->
 1432     if (dst_first_rc == rc_stack) {
 1433       // xmm -> mem
 1434       if ((src_first & 1) == 0 && src_first + 1 == src_second &&
 1435           (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
 1436         // 64-bit
 1437         int offset = ra_->reg2offset(dst_first);
 1438         if (cbuf) {
 1439           MacroAssembler _masm(cbuf);
 1440           __ movdbl( Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first]));
 1441 #ifndef PRODUCT
 1442         } else {
 1443           st->print("movsd   [rsp + #%d], %s\t# spill",
 1444                      offset,
 1445                      Matcher::regName[src_first]);
 1446 #endif
 1447         }
 1448       } else {
 1449         // 32-bit
 1450         assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
 1451         assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
 1452         int offset = ra_->reg2offset(dst_first);
 1453         if (cbuf) {
 1454           MacroAssembler _masm(cbuf);
 1455           __ movflt(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first]));
 1456 #ifndef PRODUCT
 1457         } else {
 1458           st->print("movss   [rsp + #%d], %s\t# spill",
 1459                      offset,
 1460                      Matcher::regName[src_first]);
 1461 #endif
 1462         }
 1463       }
 1464       return 0;
 1465     } else if (dst_first_rc == rc_int) {
 1466       // xmm -> gpr
 1467       if ((src_first & 1) == 0 && src_first + 1 == src_second &&
 1468           (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
 1469         // 64-bit
 1470         if (cbuf) {
 1471           MacroAssembler _masm(cbuf);
 1472           __ movdq( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
 1473 #ifndef PRODUCT
 1474         } else {
 1475           st->print("movdq   %s, %s\t# spill",
 1476                      Matcher::regName[dst_first],
 1477                      Matcher::regName[src_first]);
 1478 #endif
 1479         }
 1480       } else {
 1481         // 32-bit
 1482         assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
 1483         assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
 1484         if (cbuf) {
 1485           MacroAssembler _masm(cbuf);
 1486           __ movdl( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
 1487 #ifndef PRODUCT
 1488         } else {
 1489           st->print("movdl   %s, %s\t# spill",
 1490                      Matcher::regName[dst_first],
 1491                      Matcher::regName[src_first]);
 1492 #endif
 1493         }
 1494       }
 1495       return 0;
 1496     } else if (dst_first_rc == rc_float) {
 1497       // xmm -> xmm
 1498       if ((src_first & 1) == 0 && src_first + 1 == src_second &&
 1499           (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
 1500         // 64-bit
 1501         if (cbuf) {
 1502           MacroAssembler _masm(cbuf);
 1503           __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
 1504 #ifndef PRODUCT
 1505         } else {
 1506           st->print("%s  %s, %s\t# spill",
 1507                      UseXmmRegToRegMoveAll ? "movapd" : "movsd ",
 1508                      Matcher::regName[dst_first],
 1509                      Matcher::regName[src_first]);
 1510 #endif
 1511         }
 1512       } else {
 1513         // 32-bit
 1514         assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
 1515         assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
 1516         if (cbuf) {
 1517           MacroAssembler _masm(cbuf);
 1518           __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
 1519 #ifndef PRODUCT
 1520         } else {
 1521           st->print("%s  %s, %s\t# spill",
 1522                      UseXmmRegToRegMoveAll ? "movaps" : "movss ",
 1523                      Matcher::regName[dst_first],
 1524                      Matcher::regName[src_first]);
 1525 #endif
 1526         }
 1527       }
 1528       return 0;
 1529     } else if (dst_first_rc == rc_kreg) {
 1530       assert(false, "Illegal spilling");
 1531       return 0;
 1532     }
 1533   } else if (src_first_rc == rc_kreg) {
 1534     if (dst_first_rc == rc_stack) {
 1535       // mem -> kreg
 1536       if ((src_first & 1) == 0 && src_first + 1 == src_second &&
 1537           (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
 1538         // 64-bit
 1539         int offset = ra_->reg2offset(dst_first);
 1540         if (cbuf) {
 1541           MacroAssembler _masm(cbuf);
 1542           __ kmov(Address(rsp, offset), as_KRegister(Matcher::_regEncode[src_first]));
 1543 #ifndef PRODUCT
 1544         } else {
 1545           st->print("kmovq   [rsp + #%d] , %s\t# spill",
 1546                      offset,
 1547                      Matcher::regName[src_first]);
 1548 #endif
 1549         }
 1550       }
 1551       return 0;
 1552     } else if (dst_first_rc == rc_int) {
 1553       if ((src_first & 1) == 0 && src_first + 1 == src_second &&
 1554           (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
 1555         // 64-bit
 1556         if (cbuf) {
 1557           MacroAssembler _masm(cbuf);
 1558           __ kmov(as_Register(Matcher::_regEncode[dst_first]), as_KRegister(Matcher::_regEncode[src_first]));
 1559 #ifndef PRODUCT
 1560         } else {
 1561          st->print("kmovq   %s, %s\t# spill",
 1562                      Matcher::regName[dst_first],
 1563                      Matcher::regName[src_first]);
 1564 #endif
 1565         }
 1566       }
 1567       Unimplemented();
 1568       return 0;
 1569     } else if (dst_first_rc == rc_kreg) {
 1570       if ((src_first & 1) == 0 && src_first + 1 == src_second &&
 1571           (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
 1572         // 64-bit
 1573         if (cbuf) {
 1574           MacroAssembler _masm(cbuf);
 1575           __ kmov(as_KRegister(Matcher::_regEncode[dst_first]), as_KRegister(Matcher::_regEncode[src_first]));
 1576 #ifndef PRODUCT
 1577         } else {
 1578          st->print("kmovq   %s, %s\t# spill",
 1579                      Matcher::regName[dst_first],
 1580                      Matcher::regName[src_first]);
 1581 #endif
 1582         }
 1583       }
 1584       return 0;
 1585     } else if (dst_first_rc == rc_float) {
 1586       assert(false, "Illegal spill");
 1587       return 0;
 1588     }
 1589   }
 1590 
 1591   assert(0," foo ");
 1592   Unimplemented();
 1593   return 0;
 1594 }
 1595 
 1596 #ifndef PRODUCT
 1597 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const {
 1598   implementation(NULL, ra_, false, st);
 1599 }
 1600 #endif
 1601 
 1602 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
 1603   implementation(&cbuf, ra_, false, NULL);
 1604 }
 1605 
 1606 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
 1607   return MachNode::size(ra_);
 1608 }
 1609 
 1610 //=============================================================================
 1611 #ifndef PRODUCT
 1612 void BoxLockNode::format(PhaseRegAlloc* ra_, outputStream* st) const
 1613 {
 1614   int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
 1615   int reg = ra_->get_reg_first(this);
 1616   st->print("leaq    %s, [rsp + #%d]\t# box lock",
 1617             Matcher::regName[reg], offset);
 1618 }
 1619 #endif
 1620 
 1621 void BoxLockNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
 1622 {
 1623   int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
 1624   int reg = ra_->get_encode(this);
 1625   if (offset >= 0x80) {
 1626     emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
 1627     emit_opcode(cbuf, 0x8D); // LEA  reg,[SP+offset]
 1628     emit_rm(cbuf, 0x2, reg & 7, 0x04);
 1629     emit_rm(cbuf, 0x0, 0x04, RSP_enc);
 1630     emit_d32(cbuf, offset);
 1631   } else {
 1632     emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
 1633     emit_opcode(cbuf, 0x8D); // LEA  reg,[SP+offset]
 1634     emit_rm(cbuf, 0x1, reg & 7, 0x04);
 1635     emit_rm(cbuf, 0x0, 0x04, RSP_enc);
 1636     emit_d8(cbuf, offset);
 1637   }
 1638 }
 1639 
 1640 uint BoxLockNode::size(PhaseRegAlloc *ra_) const
 1641 {
 1642   int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
 1643   return (offset < 0x80) ? 5 : 8; // REX
 1644 }
 1645 
 1646 //=============================================================================
 1647 #ifndef PRODUCT
 1648 void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const
 1649 {
 1650   if (UseCompressedClassPointers) {
 1651     st->print_cr("movl    rscratch1, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass");
 1652     st->print_cr("\tdecode_klass_not_null rscratch1, rscratch1");
 1653     st->print_cr("\tcmpq    rax, rscratch1\t # Inline cache check");
 1654   } else {
 1655     st->print_cr("\tcmpq    rax, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t"
 1656                  "# Inline cache check");
 1657   }
 1658   st->print_cr("\tjne     SharedRuntime::_ic_miss_stub");
 1659   st->print_cr("\tnop\t# nops to align entry point");
 1660 }
 1661 #endif
 1662 
 1663 void MachUEPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
 1664 {
 1665   MacroAssembler masm(&cbuf);
 1666   uint insts_size = cbuf.insts_size();
 1667   if (UseCompressedClassPointers) {
 1668     masm.load_klass(rscratch1, j_rarg0, rscratch2);
 1669     masm.cmpptr(rax, rscratch1);
 1670   } else {
 1671     masm.cmpptr(rax, Address(j_rarg0, oopDesc::klass_offset_in_bytes()));
 1672   }
 1673 
 1674   masm.jump_cc(Assembler::notEqual, RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
 1675 
 1676   /* WARNING these NOPs are critical so that verified entry point is properly
 1677      4 bytes aligned for patching by NativeJump::patch_verified_entry() */
 1678   int nops_cnt = 4 - ((cbuf.insts_size() - insts_size) & 0x3);
 1679   if (OptoBreakpoint) {
 1680     // Leave space for int3
 1681     nops_cnt -= 1;
 1682   }
 1683   nops_cnt &= 0x3; // Do not add nops if code is aligned.
 1684   if (nops_cnt > 0)
 1685     masm.nop(nops_cnt);
 1686 }
 1687 
 1688 uint MachUEPNode::size(PhaseRegAlloc* ra_) const
 1689 {
 1690   return MachNode::size(ra_); // too many variables; just compute it
 1691                               // the hard way
 1692 }
 1693 
 1694 
 1695 //=============================================================================
 1696 
 1697 const bool Matcher::supports_vector_calling_convention(void) {
 1698   if (EnableVectorSupport && UseVectorStubs) {
 1699     return true;
 1700   }
 1701   return false;
 1702 }
 1703 
 1704 OptoRegPair Matcher::vector_return_value(uint ideal_reg) {
 1705   assert(EnableVectorSupport && UseVectorStubs, "sanity");
 1706   int lo = XMM0_num;
 1707   int hi = XMM0b_num;
 1708   if (ideal_reg == Op_VecX) hi = XMM0d_num;
 1709   else if (ideal_reg == Op_VecY) hi = XMM0h_num;
 1710   else if (ideal_reg == Op_VecZ) hi = XMM0p_num;
 1711   return OptoRegPair(hi, lo);
 1712 }
 1713 
 1714 // Is this branch offset short enough that a short branch can be used?
 1715 //
 1716 // NOTE: If the platform does not provide any short branch variants, then
 1717 //       this method should return false for offset 0.
 1718 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
 1719   // The passed offset is relative to address of the branch.
 1720   // On 86 a branch displacement is calculated relative to address
 1721   // of a next instruction.
 1722   offset -= br_size;
 1723 
 1724   // the short version of jmpConUCF2 contains multiple branches,
 1725   // making the reach slightly less
 1726   if (rule == jmpConUCF2_rule)
 1727     return (-126 <= offset && offset <= 125);
 1728   return (-128 <= offset && offset <= 127);
 1729 }
 1730 
 1731 // Return whether or not this register is ever used as an argument.
 1732 // This function is used on startup to build the trampoline stubs in
 1733 // generateOptoStub.  Registers not mentioned will be killed by the VM
 1734 // call in the trampoline, and arguments in those registers not be
 1735 // available to the callee.
 1736 bool Matcher::can_be_java_arg(int reg)
 1737 {
 1738   return
 1739     reg ==  RDI_num || reg == RDI_H_num ||
 1740     reg ==  RSI_num || reg == RSI_H_num ||
 1741     reg ==  RDX_num || reg == RDX_H_num ||
 1742     reg ==  RCX_num || reg == RCX_H_num ||
 1743     reg ==   R8_num || reg ==  R8_H_num ||
 1744     reg ==   R9_num || reg ==  R9_H_num ||
 1745     reg ==  R12_num || reg == R12_H_num ||
 1746     reg == XMM0_num || reg == XMM0b_num ||
 1747     reg == XMM1_num || reg == XMM1b_num ||
 1748     reg == XMM2_num || reg == XMM2b_num ||
 1749     reg == XMM3_num || reg == XMM3b_num ||
 1750     reg == XMM4_num || reg == XMM4b_num ||
 1751     reg == XMM5_num || reg == XMM5b_num ||
 1752     reg == XMM6_num || reg == XMM6b_num ||
 1753     reg == XMM7_num || reg == XMM7b_num;
 1754 }
 1755 
 1756 bool Matcher::is_spillable_arg(int reg)
 1757 {
 1758   return can_be_java_arg(reg);
 1759 }
 1760 
 1761 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
 1762   // In 64 bit mode a code which use multiply when
 1763   // devisor is constant is faster than hardware
 1764   // DIV instruction (it uses MulHiL).
 1765   return false;
 1766 }
 1767 
 1768 // Register for DIVI projection of divmodI
 1769 RegMask Matcher::divI_proj_mask() {
 1770   return INT_RAX_REG_mask();
 1771 }
 1772 
 1773 // Register for MODI projection of divmodI
 1774 RegMask Matcher::modI_proj_mask() {
 1775   return INT_RDX_REG_mask();
 1776 }
 1777 
 1778 // Register for DIVL projection of divmodL
 1779 RegMask Matcher::divL_proj_mask() {
 1780   return LONG_RAX_REG_mask();
 1781 }
 1782 
 1783 // Register for MODL projection of divmodL
 1784 RegMask Matcher::modL_proj_mask() {
 1785   return LONG_RDX_REG_mask();
 1786 }
 1787 
 1788 // Register for saving SP into on method handle invokes. Not used on x86_64.
 1789 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
 1790     return NO_REG_mask();
 1791 }
 1792 
 1793 %}
 1794 
 1795 //----------ENCODING BLOCK-----------------------------------------------------
 1796 // This block specifies the encoding classes used by the compiler to
 1797 // output byte streams.  Encoding classes are parameterized macros
 1798 // used by Machine Instruction Nodes in order to generate the bit
 1799 // encoding of the instruction.  Operands specify their base encoding
 1800 // interface with the interface keyword.  There are currently
 1801 // supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, &
 1802 // COND_INTER.  REG_INTER causes an operand to generate a function
 1803 // which returns its register number when queried.  CONST_INTER causes
 1804 // an operand to generate a function which returns the value of the
 1805 // constant when queried.  MEMORY_INTER causes an operand to generate
 1806 // four functions which return the Base Register, the Index Register,
 1807 // the Scale Value, and the Offset Value of the operand when queried.
 1808 // COND_INTER causes an operand to generate six functions which return
 1809 // the encoding code (ie - encoding bits for the instruction)
 1810 // associated with each basic boolean condition for a conditional
 1811 // instruction.
 1812 //
 1813 // Instructions specify two basic values for encoding.  Again, a
 1814 // function is available to check if the constant displacement is an
 1815 // oop. They use the ins_encode keyword to specify their encoding
 1816 // classes (which must be a sequence of enc_class names, and their
 1817 // parameters, specified in the encoding block), and they use the
 1818 // opcode keyword to specify, in order, their primary, secondary, and
 1819 // tertiary opcode.  Only the opcode sections which a particular
 1820 // instruction needs for encoding need to be specified.
 1821 encode %{
 1822   // Build emit functions for each basic byte or larger field in the
 1823   // intel encoding scheme (opcode, rm, sib, immediate), and call them
 1824   // from C++ code in the enc_class source block.  Emit functions will
 1825   // live in the main source block for now.  In future, we can
 1826   // generalize this by adding a syntax that specifies the sizes of
 1827   // fields in an order, so that the adlc can build the emit functions
 1828   // automagically
 1829 
 1830   // Emit primary opcode
 1831   enc_class OpcP
 1832   %{
 1833     emit_opcode(cbuf, $primary);
 1834   %}
 1835 
 1836   // Emit secondary opcode
 1837   enc_class OpcS
 1838   %{
 1839     emit_opcode(cbuf, $secondary);
 1840   %}
 1841 
 1842   // Emit tertiary opcode
 1843   enc_class OpcT
 1844   %{
 1845     emit_opcode(cbuf, $tertiary);
 1846   %}
 1847 
 1848   // Emit opcode directly
 1849   enc_class Opcode(immI d8)
 1850   %{
 1851     emit_opcode(cbuf, $d8$$constant);
 1852   %}
 1853 
 1854   // Emit size prefix
 1855   enc_class SizePrefix
 1856   %{
 1857     emit_opcode(cbuf, 0x66);
 1858   %}
 1859 
 1860   enc_class reg(rRegI reg)
 1861   %{
 1862     emit_rm(cbuf, 0x3, 0, $reg$$reg & 7);
 1863   %}
 1864 
 1865   enc_class reg_reg(rRegI dst, rRegI src)
 1866   %{
 1867     emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
 1868   %}
 1869 
 1870   enc_class opc_reg_reg(immI opcode, rRegI dst, rRegI src)
 1871   %{
 1872     emit_opcode(cbuf, $opcode$$constant);
 1873     emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
 1874   %}
 1875 
 1876   enc_class cdql_enc(no_rax_rdx_RegI div)
 1877   %{
 1878     // Full implementation of Java idiv and irem; checks for
 1879     // special case as described in JVM spec., p.243 & p.271.
 1880     //
 1881     //         normal case                           special case
 1882     //
 1883     // input : rax: dividend                         min_int
 1884     //         reg: divisor                          -1
 1885     //
 1886     // output: rax: quotient  (= rax idiv reg)       min_int
 1887     //         rdx: remainder (= rax irem reg)       0
 1888     //
 1889     //  Code sequnce:
 1890     //
 1891     //    0:   3d 00 00 00 80          cmp    $0x80000000,%eax
 1892     //    5:   75 07/08                jne    e <normal>
 1893     //    7:   33 d2                   xor    %edx,%edx
 1894     //  [div >= 8 -> offset + 1]
 1895     //  [REX_B]
 1896     //    9:   83 f9 ff                cmp    $0xffffffffffffffff,$div
 1897     //    c:   74 03/04                je     11 <done>
 1898     // 000000000000000e <normal>:
 1899     //    e:   99                      cltd
 1900     //  [div >= 8 -> offset + 1]
 1901     //  [REX_B]
 1902     //    f:   f7 f9                   idiv   $div
 1903     // 0000000000000011 <done>:
 1904     MacroAssembler _masm(&cbuf);
 1905     Label normal;
 1906     Label done;
 1907 
 1908     // cmp    $0x80000000,%eax
 1909     __ cmp(as_Register(RAX_enc), 0x80000000);
 1910 
 1911     // jne    e <normal>
 1912     __ jccb(Assembler::notEqual, normal);
 1913 
 1914     // xor    %edx,%edx
 1915     __ xorl(as_Register(RDX_enc), as_Register(RDX_enc));
 1916 
 1917     // cmp    $0xffffffffffffffff,%ecx
 1918     __ cmpl($div$$Register, -1);
 1919 
 1920     // je     11 <done>
 1921     __ jccb(Assembler::equal, done);
 1922 
 1923     // <normal>
 1924     // cltd
 1925     __ bind(normal);
 1926     __ cdql();
 1927 
 1928     // idivl
 1929     // <done>
 1930     __ idivl($div$$Register);
 1931     __ bind(done);
 1932   %}
 1933 
 1934   enc_class cdqq_enc(no_rax_rdx_RegL div)
 1935   %{
 1936     // Full implementation of Java ldiv and lrem; checks for
 1937     // special case as described in JVM spec., p.243 & p.271.
 1938     //
 1939     //         normal case                           special case
 1940     //
 1941     // input : rax: dividend                         min_long
 1942     //         reg: divisor                          -1
 1943     //
 1944     // output: rax: quotient  (= rax idiv reg)       min_long
 1945     //         rdx: remainder (= rax irem reg)       0
 1946     //
 1947     //  Code sequnce:
 1948     //
 1949     //    0:   48 ba 00 00 00 00 00    mov    $0x8000000000000000,%rdx
 1950     //    7:   00 00 80
 1951     //    a:   48 39 d0                cmp    %rdx,%rax
 1952     //    d:   75 08                   jne    17 <normal>
 1953     //    f:   33 d2                   xor    %edx,%edx
 1954     //   11:   48 83 f9 ff             cmp    $0xffffffffffffffff,$div
 1955     //   15:   74 05                   je     1c <done>
 1956     // 0000000000000017 <normal>:
 1957     //   17:   48 99                   cqto
 1958     //   19:   48 f7 f9                idiv   $div
 1959     // 000000000000001c <done>:
 1960     MacroAssembler _masm(&cbuf);
 1961     Label normal;
 1962     Label done;
 1963 
 1964     // mov    $0x8000000000000000,%rdx
 1965     __ mov64(as_Register(RDX_enc), 0x8000000000000000);
 1966 
 1967     // cmp    %rdx,%rax
 1968     __ cmpq(as_Register(RAX_enc), as_Register(RDX_enc));
 1969 
 1970     // jne    17 <normal>
 1971     __ jccb(Assembler::notEqual, normal);
 1972 
 1973     // xor    %edx,%edx
 1974     __ xorl(as_Register(RDX_enc), as_Register(RDX_enc));
 1975 
 1976     // cmp    $0xffffffffffffffff,$div
 1977     __ cmpq($div$$Register, -1);
 1978 
 1979     // je     1e <done>
 1980     __ jccb(Assembler::equal, done);
 1981 
 1982     // <normal>
 1983     // cqto
 1984     __ bind(normal);
 1985     __ cdqq();
 1986 
 1987     // idivq (note: must be emitted by the user of this rule)
 1988     // <done>
 1989     __ idivq($div$$Register);
 1990     __ bind(done);
 1991   %}
 1992 
 1993   // Opcde enc_class for 8/32 bit immediate instructions with sign-extension
 1994   enc_class OpcSE(immI imm)
 1995   %{
 1996     // Emit primary opcode and set sign-extend bit
 1997     // Check for 8-bit immediate, and set sign extend bit in opcode
 1998     if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
 1999       emit_opcode(cbuf, $primary | 0x02);
 2000     } else {
 2001       // 32-bit immediate
 2002       emit_opcode(cbuf, $primary);
 2003     }
 2004   %}
 2005 
 2006   enc_class OpcSErm(rRegI dst, immI imm)
 2007   %{
 2008     // OpcSEr/m
 2009     int dstenc = $dst$$reg;
 2010     if (dstenc >= 8) {
 2011       emit_opcode(cbuf, Assembler::REX_B);
 2012       dstenc -= 8;
 2013     }
 2014     // Emit primary opcode and set sign-extend bit
 2015     // Check for 8-bit immediate, and set sign extend bit in opcode
 2016     if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
 2017       emit_opcode(cbuf, $primary | 0x02);
 2018     } else {
 2019       // 32-bit immediate
 2020       emit_opcode(cbuf, $primary);
 2021     }
 2022     // Emit r/m byte with secondary opcode, after primary opcode.
 2023     emit_rm(cbuf, 0x3, $secondary, dstenc);
 2024   %}
 2025 
 2026   enc_class OpcSErm_wide(rRegL dst, immI imm)
 2027   %{
 2028     // OpcSEr/m
 2029     int dstenc = $dst$$reg;
 2030     if (dstenc < 8) {
 2031       emit_opcode(cbuf, Assembler::REX_W);
 2032     } else {
 2033       emit_opcode(cbuf, Assembler::REX_WB);
 2034       dstenc -= 8;
 2035     }
 2036     // Emit primary opcode and set sign-extend bit
 2037     // Check for 8-bit immediate, and set sign extend bit in opcode
 2038     if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
 2039       emit_opcode(cbuf, $primary | 0x02);
 2040     } else {
 2041       // 32-bit immediate
 2042       emit_opcode(cbuf, $primary);
 2043     }
 2044     // Emit r/m byte with secondary opcode, after primary opcode.
 2045     emit_rm(cbuf, 0x3, $secondary, dstenc);
 2046   %}
 2047 
 2048   enc_class Con8or32(immI imm)
 2049   %{
 2050     // Check for 8-bit immediate, and set sign extend bit in opcode
 2051     if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
 2052       $$$emit8$imm$$constant;
 2053     } else {
 2054       // 32-bit immediate
 2055       $$$emit32$imm$$constant;
 2056     }
 2057   %}
 2058 
 2059   enc_class opc2_reg(rRegI dst)
 2060   %{
 2061     // BSWAP
 2062     emit_cc(cbuf, $secondary, $dst$$reg);
 2063   %}
 2064 
 2065   enc_class opc3_reg(rRegI dst)
 2066   %{
 2067     // BSWAP
 2068     emit_cc(cbuf, $tertiary, $dst$$reg);
 2069   %}
 2070 
 2071   enc_class reg_opc(rRegI div)
 2072   %{
 2073     // INC, DEC, IDIV, IMOD, JMP indirect, ...
 2074     emit_rm(cbuf, 0x3, $secondary, $div$$reg & 7);
 2075   %}
 2076 
 2077   enc_class enc_cmov(cmpOp cop)
 2078   %{
 2079     // CMOV
 2080     $$$emit8$primary;
 2081     emit_cc(cbuf, $secondary, $cop$$cmpcode);
 2082   %}
 2083 
 2084   enc_class enc_PartialSubtypeCheck()
 2085   %{
 2086     Register Rrdi = as_Register(RDI_enc); // result register
 2087     Register Rrax = as_Register(RAX_enc); // super class
 2088     Register Rrcx = as_Register(RCX_enc); // killed
 2089     Register Rrsi = as_Register(RSI_enc); // sub class
 2090     Label miss;
 2091     const bool set_cond_codes = true;
 2092 
 2093     MacroAssembler _masm(&cbuf);
 2094     __ check_klass_subtype_slow_path(Rrsi, Rrax, Rrcx, Rrdi,
 2095                                      NULL, &miss,
 2096                                      /*set_cond_codes:*/ true);
 2097     if ($primary) {
 2098       __ xorptr(Rrdi, Rrdi);
 2099     }
 2100     __ bind(miss);
 2101   %}
 2102 
 2103   enc_class clear_avx %{
 2104     debug_only(int off0 = cbuf.insts_size());
 2105     if (generate_vzeroupper(Compile::current())) {
 2106       // Clear upper bits of YMM registers to avoid AVX <-> SSE transition penalty
 2107       // Clear upper bits of YMM registers when current compiled code uses
 2108       // wide vectors to avoid AVX <-> SSE transition penalty during call.
 2109       MacroAssembler _masm(&cbuf);
 2110       __ vzeroupper();
 2111     }
 2112     debug_only(int off1 = cbuf.insts_size());
 2113     assert(off1 - off0 == clear_avx_size(), "correct size prediction");
 2114   %}
 2115 
 2116   enc_class Java_To_Runtime(method meth) %{
 2117     // No relocation needed
 2118     MacroAssembler _masm(&cbuf);
 2119     __ mov64(r10, (int64_t) $meth$$method);
 2120     __ call(r10);
 2121   %}
 2122 
 2123   enc_class Java_To_Interpreter(method meth)
 2124   %{
 2125     // CALL Java_To_Interpreter
 2126     // This is the instruction starting address for relocation info.
 2127     cbuf.set_insts_mark();
 2128     $$$emit8$primary;
 2129     // CALL directly to the runtime
 2130     emit_d32_reloc(cbuf,
 2131                    (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
 2132                    runtime_call_Relocation::spec(),
 2133                    RELOC_DISP32);
 2134   %}
 2135 
 2136   enc_class Java_Static_Call(method meth)
 2137   %{
 2138     // JAVA STATIC CALL
 2139     // CALL to fixup routine.  Fixup routine uses ScopeDesc info to
 2140     // determine who we intended to call.
 2141     cbuf.set_insts_mark();
 2142     $$$emit8$primary;
 2143 
 2144     if (!_method) {
 2145       emit_d32_reloc(cbuf, (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
 2146                      runtime_call_Relocation::spec(),
 2147                      RELOC_DISP32);
 2148     } else {
 2149       int method_index = resolved_method_index(cbuf);
 2150       RelocationHolder rspec = _optimized_virtual ? opt_virtual_call_Relocation::spec(method_index)
 2151                                                   : static_call_Relocation::spec(method_index);
 2152       emit_d32_reloc(cbuf, (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
 2153                      rspec, RELOC_DISP32);
 2154       // Emit stubs for static call.
 2155       address mark = cbuf.insts_mark();
 2156       address stub = CompiledStaticCall::emit_to_interp_stub(cbuf, mark);
 2157       if (stub == NULL) {
 2158         ciEnv::current()->record_failure("CodeCache is full");
 2159         return;
 2160       }
 2161     }
 2162   %}
 2163 
 2164   enc_class Java_Dynamic_Call(method meth) %{
 2165     MacroAssembler _masm(&cbuf);
 2166     __ ic_call((address)$meth$$method, resolved_method_index(cbuf));
 2167   %}
 2168 
 2169   enc_class Java_Compiled_Call(method meth)
 2170   %{
 2171     // JAVA COMPILED CALL
 2172     int disp = in_bytes(Method:: from_compiled_offset());
 2173 
 2174     // XXX XXX offset is 128 is 1.5 NON-PRODUCT !!!
 2175     // assert(-0x80 <= disp && disp < 0x80, "compiled_code_offset isn't small");
 2176 
 2177     // callq *disp(%rax)
 2178     cbuf.set_insts_mark();
 2179     $$$emit8$primary;
 2180     if (disp < 0x80) {
 2181       emit_rm(cbuf, 0x01, $secondary, RAX_enc); // R/M byte
 2182       emit_d8(cbuf, disp); // Displacement
 2183     } else {
 2184       emit_rm(cbuf, 0x02, $secondary, RAX_enc); // R/M byte
 2185       emit_d32(cbuf, disp); // Displacement
 2186     }
 2187   %}
 2188 
 2189   enc_class reg_opc_imm(rRegI dst, immI8 shift)
 2190   %{
 2191     // SAL, SAR, SHR
 2192     int dstenc = $dst$$reg;
 2193     if (dstenc >= 8) {
 2194       emit_opcode(cbuf, Assembler::REX_B);
 2195       dstenc -= 8;
 2196     }
 2197     $$$emit8$primary;
 2198     emit_rm(cbuf, 0x3, $secondary, dstenc);
 2199     $$$emit8$shift$$constant;
 2200   %}
 2201 
 2202   enc_class reg_opc_imm_wide(rRegL dst, immI8 shift)
 2203   %{
 2204     // SAL, SAR, SHR
 2205     int dstenc = $dst$$reg;
 2206     if (dstenc < 8) {
 2207       emit_opcode(cbuf, Assembler::REX_W);
 2208     } else {
 2209       emit_opcode(cbuf, Assembler::REX_WB);
 2210       dstenc -= 8;
 2211     }
 2212     $$$emit8$primary;
 2213     emit_rm(cbuf, 0x3, $secondary, dstenc);
 2214     $$$emit8$shift$$constant;
 2215   %}
 2216 
 2217   enc_class load_immI(rRegI dst, immI src)
 2218   %{
 2219     int dstenc = $dst$$reg;
 2220     if (dstenc >= 8) {
 2221       emit_opcode(cbuf, Assembler::REX_B);
 2222       dstenc -= 8;
 2223     }
 2224     emit_opcode(cbuf, 0xB8 | dstenc);
 2225     $$$emit32$src$$constant;
 2226   %}
 2227 
 2228   enc_class load_immL(rRegL dst, immL src)
 2229   %{
 2230     int dstenc = $dst$$reg;
 2231     if (dstenc < 8) {
 2232       emit_opcode(cbuf, Assembler::REX_W);
 2233     } else {
 2234       emit_opcode(cbuf, Assembler::REX_WB);
 2235       dstenc -= 8;
 2236     }
 2237     emit_opcode(cbuf, 0xB8 | dstenc);
 2238     emit_d64(cbuf, $src$$constant);
 2239   %}
 2240 
 2241   enc_class load_immUL32(rRegL dst, immUL32 src)
 2242   %{
 2243     // same as load_immI, but this time we care about zeroes in the high word
 2244     int dstenc = $dst$$reg;
 2245     if (dstenc >= 8) {
 2246       emit_opcode(cbuf, Assembler::REX_B);
 2247       dstenc -= 8;
 2248     }
 2249     emit_opcode(cbuf, 0xB8 | dstenc);
 2250     $$$emit32$src$$constant;
 2251   %}
 2252 
 2253   enc_class load_immL32(rRegL dst, immL32 src)
 2254   %{
 2255     int dstenc = $dst$$reg;
 2256     if (dstenc < 8) {
 2257       emit_opcode(cbuf, Assembler::REX_W);
 2258     } else {
 2259       emit_opcode(cbuf, Assembler::REX_WB);
 2260       dstenc -= 8;
 2261     }
 2262     emit_opcode(cbuf, 0xC7);
 2263     emit_rm(cbuf, 0x03, 0x00, dstenc);
 2264     $$$emit32$src$$constant;
 2265   %}
 2266 
 2267   enc_class load_immP31(rRegP dst, immP32 src)
 2268   %{
 2269     // same as load_immI, but this time we care about zeroes in the high word
 2270     int dstenc = $dst$$reg;
 2271     if (dstenc >= 8) {
 2272       emit_opcode(cbuf, Assembler::REX_B);
 2273       dstenc -= 8;
 2274     }
 2275     emit_opcode(cbuf, 0xB8 | dstenc);
 2276     $$$emit32$src$$constant;
 2277   %}
 2278 
 2279   enc_class load_immP(rRegP dst, immP src)
 2280   %{
 2281     int dstenc = $dst$$reg;
 2282     if (dstenc < 8) {
 2283       emit_opcode(cbuf, Assembler::REX_W);
 2284     } else {
 2285       emit_opcode(cbuf, Assembler::REX_WB);
 2286       dstenc -= 8;
 2287     }
 2288     emit_opcode(cbuf, 0xB8 | dstenc);
 2289     // This next line should be generated from ADLC
 2290     if ($src->constant_reloc() != relocInfo::none) {
 2291       emit_d64_reloc(cbuf, $src$$constant, $src->constant_reloc(), RELOC_IMM64);
 2292     } else {
 2293       emit_d64(cbuf, $src$$constant);
 2294     }
 2295   %}
 2296 
 2297   enc_class Con32(immI src)
 2298   %{
 2299     // Output immediate
 2300     $$$emit32$src$$constant;
 2301   %}
 2302 
 2303   enc_class Con32F_as_bits(immF src)
 2304   %{
 2305     // Output Float immediate bits
 2306     jfloat jf = $src$$constant;
 2307     jint jf_as_bits = jint_cast(jf);
 2308     emit_d32(cbuf, jf_as_bits);
 2309   %}
 2310 
 2311   enc_class Con16(immI src)
 2312   %{
 2313     // Output immediate
 2314     $$$emit16$src$$constant;
 2315   %}
 2316 
 2317   // How is this different from Con32??? XXX
 2318   enc_class Con_d32(immI src)
 2319   %{
 2320     emit_d32(cbuf,$src$$constant);
 2321   %}
 2322 
 2323   enc_class conmemref (rRegP t1) %{    // Con32(storeImmI)
 2324     // Output immediate memory reference
 2325     emit_rm(cbuf, 0x00, $t1$$reg, 0x05 );
 2326     emit_d32(cbuf, 0x00);
 2327   %}
 2328 
 2329   enc_class lock_prefix()
 2330   %{
 2331     emit_opcode(cbuf, 0xF0); // lock
 2332   %}
 2333 
 2334   enc_class REX_mem(memory mem)
 2335   %{
 2336     if ($mem$$base >= 8) {
 2337       if ($mem$$index < 8) {
 2338         emit_opcode(cbuf, Assembler::REX_B);
 2339       } else {
 2340         emit_opcode(cbuf, Assembler::REX_XB);
 2341       }
 2342     } else {
 2343       if ($mem$$index >= 8) {
 2344         emit_opcode(cbuf, Assembler::REX_X);
 2345       }
 2346     }
 2347   %}
 2348 
 2349   enc_class REX_mem_wide(memory mem)
 2350   %{
 2351     if ($mem$$base >= 8) {
 2352       if ($mem$$index < 8) {
 2353         emit_opcode(cbuf, Assembler::REX_WB);
 2354       } else {
 2355         emit_opcode(cbuf, Assembler::REX_WXB);
 2356       }
 2357     } else {
 2358       if ($mem$$index < 8) {
 2359         emit_opcode(cbuf, Assembler::REX_W);
 2360       } else {
 2361         emit_opcode(cbuf, Assembler::REX_WX);
 2362       }
 2363     }
 2364   %}
 2365 
 2366   // for byte regs
 2367   enc_class REX_breg(rRegI reg)
 2368   %{
 2369     if ($reg$$reg >= 4) {
 2370       emit_opcode(cbuf, $reg$$reg < 8 ? Assembler::REX : Assembler::REX_B);
 2371     }
 2372   %}
 2373 
 2374   // for byte regs
 2375   enc_class REX_reg_breg(rRegI dst, rRegI src)
 2376   %{
 2377     if ($dst$$reg < 8) {
 2378       if ($src$$reg >= 4) {
 2379         emit_opcode(cbuf, $src$$reg < 8 ? Assembler::REX : Assembler::REX_B);
 2380       }
 2381     } else {
 2382       if ($src$$reg < 8) {
 2383         emit_opcode(cbuf, Assembler::REX_R);
 2384       } else {
 2385         emit_opcode(cbuf, Assembler::REX_RB);
 2386       }
 2387     }
 2388   %}
 2389 
 2390   // for byte regs
 2391   enc_class REX_breg_mem(rRegI reg, memory mem)
 2392   %{
 2393     if ($reg$$reg < 8) {
 2394       if ($mem$$base < 8) {
 2395         if ($mem$$index >= 8) {
 2396           emit_opcode(cbuf, Assembler::REX_X);
 2397         } else if ($reg$$reg >= 4) {
 2398           emit_opcode(cbuf, Assembler::REX);
 2399         }
 2400       } else {
 2401         if ($mem$$index < 8) {
 2402           emit_opcode(cbuf, Assembler::REX_B);
 2403         } else {
 2404           emit_opcode(cbuf, Assembler::REX_XB);
 2405         }
 2406       }
 2407     } else {
 2408       if ($mem$$base < 8) {
 2409         if ($mem$$index < 8) {
 2410           emit_opcode(cbuf, Assembler::REX_R);
 2411         } else {
 2412           emit_opcode(cbuf, Assembler::REX_RX);
 2413         }
 2414       } else {
 2415         if ($mem$$index < 8) {
 2416           emit_opcode(cbuf, Assembler::REX_RB);
 2417         } else {
 2418           emit_opcode(cbuf, Assembler::REX_RXB);
 2419         }
 2420       }
 2421     }
 2422   %}
 2423 
 2424   enc_class REX_reg(rRegI reg)
 2425   %{
 2426     if ($reg$$reg >= 8) {
 2427       emit_opcode(cbuf, Assembler::REX_B);
 2428     }
 2429   %}
 2430 
 2431   enc_class REX_reg_wide(rRegI reg)
 2432   %{
 2433     if ($reg$$reg < 8) {
 2434       emit_opcode(cbuf, Assembler::REX_W);
 2435     } else {
 2436       emit_opcode(cbuf, Assembler::REX_WB);
 2437     }
 2438   %}
 2439 
 2440   enc_class REX_reg_reg(rRegI dst, rRegI src)
 2441   %{
 2442     if ($dst$$reg < 8) {
 2443       if ($src$$reg >= 8) {
 2444         emit_opcode(cbuf, Assembler::REX_B);
 2445       }
 2446     } else {
 2447       if ($src$$reg < 8) {
 2448         emit_opcode(cbuf, Assembler::REX_R);
 2449       } else {
 2450         emit_opcode(cbuf, Assembler::REX_RB);
 2451       }
 2452     }
 2453   %}
 2454 
 2455   enc_class REX_reg_reg_wide(rRegI dst, rRegI src)
 2456   %{
 2457     if ($dst$$reg < 8) {
 2458       if ($src$$reg < 8) {
 2459         emit_opcode(cbuf, Assembler::REX_W);
 2460       } else {
 2461         emit_opcode(cbuf, Assembler::REX_WB);
 2462       }
 2463     } else {
 2464       if ($src$$reg < 8) {
 2465         emit_opcode(cbuf, Assembler::REX_WR);
 2466       } else {
 2467         emit_opcode(cbuf, Assembler::REX_WRB);
 2468       }
 2469     }
 2470   %}
 2471 
 2472   enc_class REX_reg_mem(rRegI reg, memory mem)
 2473   %{
 2474     if ($reg$$reg < 8) {
 2475       if ($mem$$base < 8) {
 2476         if ($mem$$index >= 8) {
 2477           emit_opcode(cbuf, Assembler::REX_X);
 2478         }
 2479       } else {
 2480         if ($mem$$index < 8) {
 2481           emit_opcode(cbuf, Assembler::REX_B);
 2482         } else {
 2483           emit_opcode(cbuf, Assembler::REX_XB);
 2484         }
 2485       }
 2486     } else {
 2487       if ($mem$$base < 8) {
 2488         if ($mem$$index < 8) {
 2489           emit_opcode(cbuf, Assembler::REX_R);
 2490         } else {
 2491           emit_opcode(cbuf, Assembler::REX_RX);
 2492         }
 2493       } else {
 2494         if ($mem$$index < 8) {
 2495           emit_opcode(cbuf, Assembler::REX_RB);
 2496         } else {
 2497           emit_opcode(cbuf, Assembler::REX_RXB);
 2498         }
 2499       }
 2500     }
 2501   %}
 2502 
 2503   enc_class REX_reg_mem_wide(rRegL reg, memory mem)
 2504   %{
 2505     if ($reg$$reg < 8) {
 2506       if ($mem$$base < 8) {
 2507         if ($mem$$index < 8) {
 2508           emit_opcode(cbuf, Assembler::REX_W);
 2509         } else {
 2510           emit_opcode(cbuf, Assembler::REX_WX);
 2511         }
 2512       } else {
 2513         if ($mem$$index < 8) {
 2514           emit_opcode(cbuf, Assembler::REX_WB);
 2515         } else {
 2516           emit_opcode(cbuf, Assembler::REX_WXB);
 2517         }
 2518       }
 2519     } else {
 2520       if ($mem$$base < 8) {
 2521         if ($mem$$index < 8) {
 2522           emit_opcode(cbuf, Assembler::REX_WR);
 2523         } else {
 2524           emit_opcode(cbuf, Assembler::REX_WRX);
 2525         }
 2526       } else {
 2527         if ($mem$$index < 8) {
 2528           emit_opcode(cbuf, Assembler::REX_WRB);
 2529         } else {
 2530           emit_opcode(cbuf, Assembler::REX_WRXB);
 2531         }
 2532       }
 2533     }
 2534   %}
 2535 
 2536   enc_class reg_mem(rRegI ereg, memory mem)
 2537   %{
 2538     // High registers handle in encode_RegMem
 2539     int reg = $ereg$$reg;
 2540     int base = $mem$$base;
 2541     int index = $mem$$index;
 2542     int scale = $mem$$scale;
 2543     int disp = $mem$$disp;
 2544     relocInfo::relocType disp_reloc = $mem->disp_reloc();
 2545 
 2546     encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
 2547   %}
 2548 
 2549   enc_class RM_opc_mem(immI rm_opcode, memory mem)
 2550   %{
 2551     int rm_byte_opcode = $rm_opcode$$constant;
 2552 
 2553     // High registers handle in encode_RegMem
 2554     int base = $mem$$base;
 2555     int index = $mem$$index;
 2556     int scale = $mem$$scale;
 2557     int displace = $mem$$disp;
 2558 
 2559     relocInfo::relocType disp_reloc = $mem->disp_reloc();       // disp-as-oop when
 2560                                             // working with static
 2561                                             // globals
 2562     encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace,
 2563                   disp_reloc);
 2564   %}
 2565 
 2566   enc_class reg_lea(rRegI dst, rRegI src0, immI src1)
 2567   %{
 2568     int reg_encoding = $dst$$reg;
 2569     int base         = $src0$$reg;      // 0xFFFFFFFF indicates no base
 2570     int index        = 0x04;            // 0x04 indicates no index
 2571     int scale        = 0x00;            // 0x00 indicates no scale
 2572     int displace     = $src1$$constant; // 0x00 indicates no displacement
 2573     relocInfo::relocType disp_reloc = relocInfo::none;
 2574     encode_RegMem(cbuf, reg_encoding, base, index, scale, displace,
 2575                   disp_reloc);
 2576   %}
 2577 
 2578   enc_class neg_reg(rRegI dst)
 2579   %{
 2580     int dstenc = $dst$$reg;
 2581     if (dstenc >= 8) {
 2582       emit_opcode(cbuf, Assembler::REX_B);
 2583       dstenc -= 8;
 2584     }
 2585     // NEG $dst
 2586     emit_opcode(cbuf, 0xF7);
 2587     emit_rm(cbuf, 0x3, 0x03, dstenc);
 2588   %}
 2589 
 2590   enc_class neg_reg_wide(rRegI dst)
 2591   %{
 2592     int dstenc = $dst$$reg;
 2593     if (dstenc < 8) {
 2594       emit_opcode(cbuf, Assembler::REX_W);
 2595     } else {
 2596       emit_opcode(cbuf, Assembler::REX_WB);
 2597       dstenc -= 8;
 2598     }
 2599     // NEG $dst
 2600     emit_opcode(cbuf, 0xF7);
 2601     emit_rm(cbuf, 0x3, 0x03, dstenc);
 2602   %}
 2603 
 2604   enc_class setLT_reg(rRegI dst)
 2605   %{
 2606     int dstenc = $dst$$reg;
 2607     if (dstenc >= 8) {
 2608       emit_opcode(cbuf, Assembler::REX_B);
 2609       dstenc -= 8;
 2610     } else if (dstenc >= 4) {
 2611       emit_opcode(cbuf, Assembler::REX);
 2612     }
 2613     // SETLT $dst
 2614     emit_opcode(cbuf, 0x0F);
 2615     emit_opcode(cbuf, 0x9C);
 2616     emit_rm(cbuf, 0x3, 0x0, dstenc);
 2617   %}
 2618 
 2619   enc_class setNZ_reg(rRegI dst)
 2620   %{
 2621     int dstenc = $dst$$reg;
 2622     if (dstenc >= 8) {
 2623       emit_opcode(cbuf, Assembler::REX_B);
 2624       dstenc -= 8;
 2625     } else if (dstenc >= 4) {
 2626       emit_opcode(cbuf, Assembler::REX);
 2627     }
 2628     // SETNZ $dst
 2629     emit_opcode(cbuf, 0x0F);
 2630     emit_opcode(cbuf, 0x95);
 2631     emit_rm(cbuf, 0x3, 0x0, dstenc);
 2632   %}
 2633 
 2634 
 2635   // Compare the lonogs and set -1, 0, or 1 into dst
 2636   enc_class cmpl3_flag(rRegL src1, rRegL src2, rRegI dst)
 2637   %{
 2638     int src1enc = $src1$$reg;
 2639     int src2enc = $src2$$reg;
 2640     int dstenc = $dst$$reg;
 2641 
 2642     // cmpq $src1, $src2
 2643     if (src1enc < 8) {
 2644       if (src2enc < 8) {
 2645         emit_opcode(cbuf, Assembler::REX_W);
 2646       } else {
 2647         emit_opcode(cbuf, Assembler::REX_WB);
 2648       }
 2649     } else {
 2650       if (src2enc < 8) {
 2651         emit_opcode(cbuf, Assembler::REX_WR);
 2652       } else {
 2653         emit_opcode(cbuf, Assembler::REX_WRB);
 2654       }
 2655     }
 2656     emit_opcode(cbuf, 0x3B);
 2657     emit_rm(cbuf, 0x3, src1enc & 7, src2enc & 7);
 2658 
 2659     // movl $dst, -1
 2660     if (dstenc >= 8) {
 2661       emit_opcode(cbuf, Assembler::REX_B);
 2662     }
 2663     emit_opcode(cbuf, 0xB8 | (dstenc & 7));
 2664     emit_d32(cbuf, -1);
 2665 
 2666     // jl,s done
 2667     emit_opcode(cbuf, 0x7C);
 2668     emit_d8(cbuf, dstenc < 4 ? 0x06 : 0x08);
 2669 
 2670     // setne $dst
 2671     if (dstenc >= 4) {
 2672       emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_B);
 2673     }
 2674     emit_opcode(cbuf, 0x0F);
 2675     emit_opcode(cbuf, 0x95);
 2676     emit_opcode(cbuf, 0xC0 | (dstenc & 7));
 2677 
 2678     // movzbl $dst, $dst
 2679     if (dstenc >= 4) {
 2680       emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_RB);
 2681     }
 2682     emit_opcode(cbuf, 0x0F);
 2683     emit_opcode(cbuf, 0xB6);
 2684     emit_rm(cbuf, 0x3, dstenc & 7, dstenc & 7);
 2685   %}
 2686 
 2687   enc_class Push_ResultXD(regD dst) %{
 2688     MacroAssembler _masm(&cbuf);
 2689     __ fstp_d(Address(rsp, 0));
 2690     __ movdbl($dst$$XMMRegister, Address(rsp, 0));
 2691     __ addptr(rsp, 8);
 2692   %}
 2693 
 2694   enc_class Push_SrcXD(regD src) %{
 2695     MacroAssembler _masm(&cbuf);
 2696     __ subptr(rsp, 8);
 2697     __ movdbl(Address(rsp, 0), $src$$XMMRegister);
 2698     __ fld_d(Address(rsp, 0));
 2699   %}
 2700 
 2701 
 2702   enc_class enc_rethrow()
 2703   %{
 2704     cbuf.set_insts_mark();
 2705     emit_opcode(cbuf, 0xE9); // jmp entry
 2706     emit_d32_reloc(cbuf,
 2707                    (int) (OptoRuntime::rethrow_stub() - cbuf.insts_end() - 4),
 2708                    runtime_call_Relocation::spec(),
 2709                    RELOC_DISP32);
 2710   %}
 2711 
 2712 %}
 2713 
 2714 
 2715 
 2716 //----------FRAME--------------------------------------------------------------
 2717 // Definition of frame structure and management information.
 2718 //
 2719 //  S T A C K   L A Y O U T    Allocators stack-slot number
 2720 //                             |   (to get allocators register number
 2721 //  G  Owned by    |        |  v    add OptoReg::stack0())
 2722 //  r   CALLER     |        |
 2723 //  o     |        +--------+      pad to even-align allocators stack-slot
 2724 //  w     V        |  pad0  |        numbers; owned by CALLER
 2725 //  t   -----------+--------+----> Matcher::_in_arg_limit, unaligned
 2726 //  h     ^        |   in   |  5
 2727 //        |        |  args  |  4   Holes in incoming args owned by SELF
 2728 //  |     |        |        |  3
 2729 //  |     |        +--------+
 2730 //  V     |        | old out|      Empty on Intel, window on Sparc
 2731 //        |    old |preserve|      Must be even aligned.
 2732 //        |     SP-+--------+----> Matcher::_old_SP, even aligned
 2733 //        |        |   in   |  3   area for Intel ret address
 2734 //     Owned by    |preserve|      Empty on Sparc.
 2735 //       SELF      +--------+
 2736 //        |        |  pad2  |  2   pad to align old SP
 2737 //        |        +--------+  1
 2738 //        |        | locks  |  0
 2739 //        |        +--------+----> OptoReg::stack0(), even aligned
 2740 //        |        |  pad1  | 11   pad to align new SP
 2741 //        |        +--------+
 2742 //        |        |        | 10
 2743 //        |        | spills |  9   spills
 2744 //        V        |        |  8   (pad0 slot for callee)
 2745 //      -----------+--------+----> Matcher::_out_arg_limit, unaligned
 2746 //        ^        |  out   |  7
 2747 //        |        |  args  |  6   Holes in outgoing args owned by CALLEE
 2748 //     Owned by    +--------+
 2749 //      CALLEE     | new out|  6   Empty on Intel, window on Sparc
 2750 //        |    new |preserve|      Must be even-aligned.
 2751 //        |     SP-+--------+----> Matcher::_new_SP, even aligned
 2752 //        |        |        |
 2753 //
 2754 // Note 1: Only region 8-11 is determined by the allocator.  Region 0-5 is
 2755 //         known from SELF's arguments and the Java calling convention.
 2756 //         Region 6-7 is determined per call site.
 2757 // Note 2: If the calling convention leaves holes in the incoming argument
 2758 //         area, those holes are owned by SELF.  Holes in the outgoing area
 2759 //         are owned by the CALLEE.  Holes should not be nessecary in the
 2760 //         incoming area, as the Java calling convention is completely under
 2761 //         the control of the AD file.  Doubles can be sorted and packed to
 2762 //         avoid holes.  Holes in the outgoing arguments may be nessecary for
 2763 //         varargs C calling conventions.
 2764 // Note 3: Region 0-3 is even aligned, with pad2 as needed.  Region 3-5 is
 2765 //         even aligned with pad0 as needed.
 2766 //         Region 6 is even aligned.  Region 6-7 is NOT even aligned;
 2767 //         region 6-11 is even aligned; it may be padded out more so that
 2768 //         the region from SP to FP meets the minimum stack alignment.
 2769 // Note 4: For I2C adapters, the incoming FP may not meet the minimum stack
 2770 //         alignment.  Region 11, pad1, may be dynamically extended so that
 2771 //         SP meets the minimum alignment.
 2772 
 2773 frame
 2774 %{
 2775   // These three registers define part of the calling convention
 2776   // between compiled code and the interpreter.
 2777   inline_cache_reg(RAX);                // Inline Cache Register
 2778 
 2779   // Optional: name the operand used by cisc-spilling to access
 2780   // [stack_pointer + offset]
 2781   cisc_spilling_operand_name(indOffset32);
 2782 
 2783   // Number of stack slots consumed by locking an object
 2784   sync_stack_slots(2);
 2785 
 2786   // Compiled code's Frame Pointer
 2787   frame_pointer(RSP);
 2788 
 2789   // Interpreter stores its frame pointer in a register which is
 2790   // stored to the stack by I2CAdaptors.
 2791   // I2CAdaptors convert from interpreted java to compiled java.
 2792   interpreter_frame_pointer(RBP);
 2793 
 2794   // Stack alignment requirement
 2795   stack_alignment(StackAlignmentInBytes); // Alignment size in bytes (128-bit -> 16 bytes)
 2796 
 2797   // Number of outgoing stack slots killed above the out_preserve_stack_slots
 2798   // for calls to C.  Supports the var-args backing area for register parms.
 2799   varargs_C_out_slots_killed(frame::arg_reg_save_area_bytes/BytesPerInt);
 2800 
 2801   // The after-PROLOG location of the return address.  Location of
 2802   // return address specifies a type (REG or STACK) and a number
 2803   // representing the register number (i.e. - use a register name) or
 2804   // stack slot.
 2805   // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
 2806   // Otherwise, it is above the locks and verification slot and alignment word
 2807   return_addr(STACK - 2 +
 2808               align_up((Compile::current()->in_preserve_stack_slots() +
 2809                         Compile::current()->fixed_slots()),
 2810                        stack_alignment_in_slots()));
 2811 
 2812   // Location of compiled Java return values.  Same as C for now.
 2813   return_value
 2814   %{
 2815     assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL,
 2816            "only return normal values");
 2817 
 2818     static const int lo[Op_RegL + 1] = {
 2819       0,
 2820       0,
 2821       RAX_num,  // Op_RegN
 2822       RAX_num,  // Op_RegI
 2823       RAX_num,  // Op_RegP
 2824       XMM0_num, // Op_RegF
 2825       XMM0_num, // Op_RegD
 2826       RAX_num   // Op_RegL
 2827     };
 2828     static const int hi[Op_RegL + 1] = {
 2829       0,
 2830       0,
 2831       OptoReg::Bad, // Op_RegN
 2832       OptoReg::Bad, // Op_RegI
 2833       RAX_H_num,    // Op_RegP
 2834       OptoReg::Bad, // Op_RegF
 2835       XMM0b_num,    // Op_RegD
 2836       RAX_H_num     // Op_RegL
 2837     };
 2838     // Excluded flags and vector registers.
 2839     assert(ARRAY_SIZE(hi) == _last_machine_leaf - 8, "missing type");
 2840     return OptoRegPair(hi[ideal_reg], lo[ideal_reg]);
 2841   %}
 2842 %}
 2843 
 2844 //----------ATTRIBUTES---------------------------------------------------------
 2845 //----------Operand Attributes-------------------------------------------------
 2846 op_attrib op_cost(0);        // Required cost attribute
 2847 
 2848 //----------Instruction Attributes---------------------------------------------
 2849 ins_attrib ins_cost(100);       // Required cost attribute
 2850 ins_attrib ins_size(8);         // Required size attribute (in bits)
 2851 ins_attrib ins_short_branch(0); // Required flag: is this instruction
 2852                                 // a non-matching short branch variant
 2853                                 // of some long branch?
 2854 ins_attrib ins_alignment(1);    // Required alignment attribute (must
 2855                                 // be a power of 2) specifies the
 2856                                 // alignment that some part of the
 2857                                 // instruction (not necessarily the
 2858                                 // start) requires.  If > 1, a
 2859                                 // compute_padding() function must be
 2860                                 // provided for the instruction
 2861 
 2862 //----------OPERANDS-----------------------------------------------------------
 2863 // Operand definitions must precede instruction definitions for correct parsing
 2864 // in the ADLC because operands constitute user defined types which are used in
 2865 // instruction definitions.
 2866 
 2867 //----------Simple Operands----------------------------------------------------
 2868 // Immediate Operands
 2869 // Integer Immediate
 2870 operand immI()
 2871 %{
 2872   match(ConI);
 2873 
 2874   op_cost(10);
 2875   format %{ %}
 2876   interface(CONST_INTER);
 2877 %}
 2878 
 2879 // Constant for test vs zero
 2880 operand immI_0()
 2881 %{
 2882   predicate(n->get_int() == 0);
 2883   match(ConI);
 2884 
 2885   op_cost(0);
 2886   format %{ %}
 2887   interface(CONST_INTER);
 2888 %}
 2889 
 2890 // Constant for increment
 2891 operand immI_1()
 2892 %{
 2893   predicate(n->get_int() == 1);
 2894   match(ConI);
 2895 
 2896   op_cost(0);
 2897   format %{ %}
 2898   interface(CONST_INTER);
 2899 %}
 2900 
 2901 // Constant for decrement
 2902 operand immI_M1()
 2903 %{
 2904   predicate(n->get_int() == -1);
 2905   match(ConI);
 2906 
 2907   op_cost(0);
 2908   format %{ %}
 2909   interface(CONST_INTER);
 2910 %}
 2911 
 2912 operand immI_2()
 2913 %{
 2914   predicate(n->get_int() == 2);
 2915   match(ConI);
 2916 
 2917   op_cost(0);
 2918   format %{ %}
 2919   interface(CONST_INTER);
 2920 %}
 2921 
 2922 operand immI_4()
 2923 %{
 2924   predicate(n->get_int() == 4);
 2925   match(ConI);
 2926 
 2927   op_cost(0);
 2928   format %{ %}
 2929   interface(CONST_INTER);
 2930 %}
 2931 
 2932 operand immI_8()
 2933 %{
 2934   predicate(n->get_int() == 8);
 2935   match(ConI);
 2936 
 2937   op_cost(0);
 2938   format %{ %}
 2939   interface(CONST_INTER);
 2940 %}
 2941 
 2942 // Valid scale values for addressing modes
 2943 operand immI2()
 2944 %{
 2945   predicate(0 <= n->get_int() && (n->get_int() <= 3));
 2946   match(ConI);
 2947 
 2948   format %{ %}
 2949   interface(CONST_INTER);
 2950 %}
 2951 
 2952 operand immU7()
 2953 %{
 2954   predicate((0 <= n->get_int()) && (n->get_int() <= 0x7F));
 2955   match(ConI);
 2956 
 2957   op_cost(5);
 2958   format %{ %}
 2959   interface(CONST_INTER);
 2960 %}
 2961 
 2962 operand immI8()
 2963 %{
 2964   predicate((-0x80 <= n->get_int()) && (n->get_int() < 0x80));
 2965   match(ConI);
 2966 
 2967   op_cost(5);
 2968   format %{ %}
 2969   interface(CONST_INTER);
 2970 %}
 2971 
 2972 operand immU8()
 2973 %{
 2974   predicate((0 <= n->get_int()) && (n->get_int() <= 255));
 2975   match(ConI);
 2976 
 2977   op_cost(5);
 2978   format %{ %}
 2979   interface(CONST_INTER);
 2980 %}
 2981 
 2982 operand immI16()
 2983 %{
 2984   predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
 2985   match(ConI);
 2986 
 2987   op_cost(10);
 2988   format %{ %}
 2989   interface(CONST_INTER);
 2990 %}
 2991 
 2992 // Int Immediate non-negative
 2993 operand immU31()
 2994 %{
 2995   predicate(n->get_int() >= 0);
 2996   match(ConI);
 2997 
 2998   op_cost(0);
 2999   format %{ %}
 3000   interface(CONST_INTER);
 3001 %}
 3002 
 3003 // Constant for long shifts
 3004 operand immI_32()
 3005 %{
 3006   predicate( n->get_int() == 32 );
 3007   match(ConI);
 3008 
 3009   op_cost(0);
 3010   format %{ %}
 3011   interface(CONST_INTER);
 3012 %}
 3013 
 3014 // Constant for long shifts
 3015 operand immI_64()
 3016 %{
 3017   predicate( n->get_int() == 64 );
 3018   match(ConI);
 3019 
 3020   op_cost(0);
 3021   format %{ %}
 3022   interface(CONST_INTER);
 3023 %}
 3024 
 3025 // Pointer Immediate
 3026 operand immP()
 3027 %{
 3028   match(ConP);
 3029 
 3030   op_cost(10);
 3031   format %{ %}
 3032   interface(CONST_INTER);
 3033 %}
 3034 
 3035 // NULL Pointer Immediate
 3036 operand immP0()
 3037 %{
 3038   predicate(n->get_ptr() == 0);
 3039   match(ConP);
 3040 
 3041   op_cost(5);
 3042   format %{ %}
 3043   interface(CONST_INTER);
 3044 %}
 3045 
 3046 // Pointer Immediate
 3047 operand immN() %{
 3048   match(ConN);
 3049 
 3050   op_cost(10);
 3051   format %{ %}
 3052   interface(CONST_INTER);
 3053 %}
 3054 
 3055 operand immNKlass() %{
 3056   match(ConNKlass);
 3057 
 3058   op_cost(10);
 3059   format %{ %}
 3060   interface(CONST_INTER);
 3061 %}
 3062 
 3063 // NULL Pointer Immediate
 3064 operand immN0() %{
 3065   predicate(n->get_narrowcon() == 0);
 3066   match(ConN);
 3067 
 3068   op_cost(5);
 3069   format %{ %}
 3070   interface(CONST_INTER);
 3071 %}
 3072 
 3073 operand immP31()
 3074 %{
 3075   predicate(n->as_Type()->type()->reloc() == relocInfo::none
 3076             && (n->get_ptr() >> 31) == 0);
 3077   match(ConP);
 3078 
 3079   op_cost(5);
 3080   format %{ %}
 3081   interface(CONST_INTER);
 3082 %}
 3083 
 3084 
 3085 // Long Immediate
 3086 operand immL()
 3087 %{
 3088   match(ConL);
 3089 
 3090   op_cost(20);
 3091   format %{ %}
 3092   interface(CONST_INTER);
 3093 %}
 3094 
 3095 // Long Immediate 8-bit
 3096 operand immL8()
 3097 %{
 3098   predicate(-0x80L <= n->get_long() && n->get_long() < 0x80L);
 3099   match(ConL);
 3100 
 3101   op_cost(5);
 3102   format %{ %}
 3103   interface(CONST_INTER);
 3104 %}
 3105 
 3106 // Long Immediate 32-bit unsigned
 3107 operand immUL32()
 3108 %{
 3109   predicate(n->get_long() == (unsigned int) (n->get_long()));
 3110   match(ConL);
 3111 
 3112   op_cost(10);
 3113   format %{ %}
 3114   interface(CONST_INTER);
 3115 %}
 3116 
 3117 // Long Immediate 32-bit signed
 3118 operand immL32()
 3119 %{
 3120   predicate(n->get_long() == (int) (n->get_long()));
 3121   match(ConL);
 3122 
 3123   op_cost(15);
 3124   format %{ %}
 3125   interface(CONST_INTER);
 3126 %}
 3127 
 3128 operand immL_Pow2()
 3129 %{
 3130   predicate(is_power_of_2((julong)n->get_long()));
 3131   match(ConL);
 3132 
 3133   op_cost(15);
 3134   format %{ %}
 3135   interface(CONST_INTER);
 3136 %}
 3137 
 3138 operand immL_NotPow2()
 3139 %{
 3140   predicate(is_power_of_2((julong)~n->get_long()));
 3141   match(ConL);
 3142 
 3143   op_cost(15);
 3144   format %{ %}
 3145   interface(CONST_INTER);
 3146 %}
 3147 
 3148 // Long Immediate zero
 3149 operand immL0()
 3150 %{
 3151   predicate(n->get_long() == 0L);
 3152   match(ConL);
 3153 
 3154   op_cost(10);
 3155   format %{ %}
 3156   interface(CONST_INTER);
 3157 %}
 3158 
 3159 // Constant for increment
 3160 operand immL1()
 3161 %{
 3162   predicate(n->get_long() == 1);
 3163   match(ConL);
 3164 
 3165   format %{ %}
 3166   interface(CONST_INTER);
 3167 %}
 3168 
 3169 // Constant for decrement
 3170 operand immL_M1()
 3171 %{
 3172   predicate(n->get_long() == -1);
 3173   match(ConL);
 3174 
 3175   format %{ %}
 3176   interface(CONST_INTER);
 3177 %}
 3178 
 3179 // Long Immediate: the value 10
 3180 operand immL10()
 3181 %{
 3182   predicate(n->get_long() == 10);
 3183   match(ConL);
 3184 
 3185   format %{ %}
 3186   interface(CONST_INTER);
 3187 %}
 3188 
 3189 // Long immediate from 0 to 127.
 3190 // Used for a shorter form of long mul by 10.
 3191 operand immL_127()
 3192 %{
 3193   predicate(0 <= n->get_long() && n->get_long() < 0x80);
 3194   match(ConL);
 3195 
 3196   op_cost(10);
 3197   format %{ %}
 3198   interface(CONST_INTER);
 3199 %}
 3200 
 3201 // Long Immediate: low 32-bit mask
 3202 operand immL_32bits()
 3203 %{
 3204   predicate(n->get_long() == 0xFFFFFFFFL);
 3205   match(ConL);
 3206   op_cost(20);
 3207 
 3208   format %{ %}
 3209   interface(CONST_INTER);
 3210 %}
 3211 
 3212 // Int Immediate: 2^n-1, postive
 3213 operand immI_Pow2M1()
 3214 %{
 3215   predicate((n->get_int() > 0)
 3216             && is_power_of_2(n->get_int() + 1));
 3217   match(ConI);
 3218 
 3219   op_cost(20);
 3220   format %{ %}
 3221   interface(CONST_INTER);
 3222 %}
 3223 
 3224 // Float Immediate zero
 3225 operand immF0()
 3226 %{
 3227   predicate(jint_cast(n->getf()) == 0);
 3228   match(ConF);
 3229 
 3230   op_cost(5);
 3231   format %{ %}
 3232   interface(CONST_INTER);
 3233 %}
 3234 
 3235 // Float Immediate
 3236 operand immF()
 3237 %{
 3238   match(ConF);
 3239 
 3240   op_cost(15);
 3241   format %{ %}
 3242   interface(CONST_INTER);
 3243 %}
 3244 
 3245 // Double Immediate zero
 3246 operand immD0()
 3247 %{
 3248   predicate(jlong_cast(n->getd()) == 0);
 3249   match(ConD);
 3250 
 3251   op_cost(5);
 3252   format %{ %}
 3253   interface(CONST_INTER);
 3254 %}
 3255 
 3256 // Double Immediate
 3257 operand immD()
 3258 %{
 3259   match(ConD);
 3260 
 3261   op_cost(15);
 3262   format %{ %}
 3263   interface(CONST_INTER);
 3264 %}
 3265 
 3266 // Immediates for special shifts (sign extend)
 3267 
 3268 // Constants for increment
 3269 operand immI_16()
 3270 %{
 3271   predicate(n->get_int() == 16);
 3272   match(ConI);
 3273 
 3274   format %{ %}
 3275   interface(CONST_INTER);
 3276 %}
 3277 
 3278 operand immI_24()
 3279 %{
 3280   predicate(n->get_int() == 24);
 3281   match(ConI);
 3282 
 3283   format %{ %}
 3284   interface(CONST_INTER);
 3285 %}
 3286 
 3287 // Constant for byte-wide masking
 3288 operand immI_255()
 3289 %{
 3290   predicate(n->get_int() == 255);
 3291   match(ConI);
 3292 
 3293   format %{ %}
 3294   interface(CONST_INTER);
 3295 %}
 3296 
 3297 // Constant for short-wide masking
 3298 operand immI_65535()
 3299 %{
 3300   predicate(n->get_int() == 65535);
 3301   match(ConI);
 3302 
 3303   format %{ %}
 3304   interface(CONST_INTER);
 3305 %}
 3306 
 3307 // Constant for byte-wide masking
 3308 operand immL_255()
 3309 %{
 3310   predicate(n->get_long() == 255);
 3311   match(ConL);
 3312 
 3313   format %{ %}
 3314   interface(CONST_INTER);
 3315 %}
 3316 
 3317 // Constant for short-wide masking
 3318 operand immL_65535()
 3319 %{
 3320   predicate(n->get_long() == 65535);
 3321   match(ConL);
 3322 
 3323   format %{ %}
 3324   interface(CONST_INTER);
 3325 %}
 3326 
 3327 operand kReg()
 3328 %{
 3329   constraint(ALLOC_IN_RC(vectmask_reg));
 3330   match(RegVectMask);
 3331   format %{%}
 3332   interface(REG_INTER);
 3333 %}
 3334 
 3335 operand kReg_K1()
 3336 %{
 3337   constraint(ALLOC_IN_RC(vectmask_reg_K1));
 3338   match(RegVectMask);
 3339   format %{%}
 3340   interface(REG_INTER);
 3341 %}
 3342 
 3343 operand kReg_K2()
 3344 %{
 3345   constraint(ALLOC_IN_RC(vectmask_reg_K2));
 3346   match(RegVectMask);
 3347   format %{%}
 3348   interface(REG_INTER);
 3349 %}
 3350 
 3351 // Special Registers
 3352 operand kReg_K3()
 3353 %{
 3354   constraint(ALLOC_IN_RC(vectmask_reg_K3));
 3355   match(RegVectMask);
 3356   format %{%}
 3357   interface(REG_INTER);
 3358 %}
 3359 
 3360 operand kReg_K4()
 3361 %{
 3362   constraint(ALLOC_IN_RC(vectmask_reg_K4));
 3363   match(RegVectMask);
 3364   format %{%}
 3365   interface(REG_INTER);
 3366 %}
 3367 
 3368 operand kReg_K5()
 3369 %{
 3370   constraint(ALLOC_IN_RC(vectmask_reg_K5));
 3371   match(RegVectMask);
 3372   format %{%}
 3373   interface(REG_INTER);
 3374 %}
 3375 
 3376 operand kReg_K6()
 3377 %{
 3378   constraint(ALLOC_IN_RC(vectmask_reg_K6));
 3379   match(RegVectMask);
 3380   format %{%}
 3381   interface(REG_INTER);
 3382 %}
 3383 
 3384 // Special Registers
 3385 operand kReg_K7()
 3386 %{
 3387   constraint(ALLOC_IN_RC(vectmask_reg_K7));
 3388   match(RegVectMask);
 3389   format %{%}
 3390   interface(REG_INTER);
 3391 %}
 3392 
 3393 // Register Operands
 3394 // Integer Register
 3395 operand rRegI()
 3396 %{
 3397   constraint(ALLOC_IN_RC(int_reg));
 3398   match(RegI);
 3399 
 3400   match(rax_RegI);
 3401   match(rbx_RegI);
 3402   match(rcx_RegI);
 3403   match(rdx_RegI);
 3404   match(rdi_RegI);
 3405 
 3406   format %{ %}
 3407   interface(REG_INTER);
 3408 %}
 3409 
 3410 // Special Registers
 3411 operand rax_RegI()
 3412 %{
 3413   constraint(ALLOC_IN_RC(int_rax_reg));
 3414   match(RegI);
 3415   match(rRegI);
 3416 
 3417   format %{ "RAX" %}
 3418   interface(REG_INTER);
 3419 %}
 3420 
 3421 // Special Registers
 3422 operand rbx_RegI()
 3423 %{
 3424   constraint(ALLOC_IN_RC(int_rbx_reg));
 3425   match(RegI);
 3426   match(rRegI);
 3427 
 3428   format %{ "RBX" %}
 3429   interface(REG_INTER);
 3430 %}
 3431 
 3432 operand rcx_RegI()
 3433 %{
 3434   constraint(ALLOC_IN_RC(int_rcx_reg));
 3435   match(RegI);
 3436   match(rRegI);
 3437 
 3438   format %{ "RCX" %}
 3439   interface(REG_INTER);
 3440 %}
 3441 
 3442 operand rdx_RegI()
 3443 %{
 3444   constraint(ALLOC_IN_RC(int_rdx_reg));
 3445   match(RegI);
 3446   match(rRegI);
 3447 
 3448   format %{ "RDX" %}
 3449   interface(REG_INTER);
 3450 %}
 3451 
 3452 operand rdi_RegI()
 3453 %{
 3454   constraint(ALLOC_IN_RC(int_rdi_reg));
 3455   match(RegI);
 3456   match(rRegI);
 3457 
 3458   format %{ "RDI" %}
 3459   interface(REG_INTER);
 3460 %}
 3461 
 3462 operand no_rax_rdx_RegI()
 3463 %{
 3464   constraint(ALLOC_IN_RC(int_no_rax_rdx_reg));
 3465   match(RegI);
 3466   match(rbx_RegI);
 3467   match(rcx_RegI);
 3468   match(rdi_RegI);
 3469 
 3470   format %{ %}
 3471   interface(REG_INTER);
 3472 %}
 3473 
 3474 // Pointer Register
 3475 operand any_RegP()
 3476 %{
 3477   constraint(ALLOC_IN_RC(any_reg));
 3478   match(RegP);
 3479   match(rax_RegP);
 3480   match(rbx_RegP);
 3481   match(rdi_RegP);
 3482   match(rsi_RegP);
 3483   match(rbp_RegP);
 3484   match(r15_RegP);
 3485   match(rRegP);
 3486 
 3487   format %{ %}
 3488   interface(REG_INTER);
 3489 %}
 3490 
 3491 operand rRegP()
 3492 %{
 3493   constraint(ALLOC_IN_RC(ptr_reg));
 3494   match(RegP);
 3495   match(rax_RegP);
 3496   match(rbx_RegP);
 3497   match(rdi_RegP);
 3498   match(rsi_RegP);
 3499   match(rbp_RegP);  // See Q&A below about
 3500   match(r15_RegP);  // r15_RegP and rbp_RegP.
 3501 
 3502   format %{ %}
 3503   interface(REG_INTER);
 3504 %}
 3505 
 3506 operand rRegN() %{
 3507   constraint(ALLOC_IN_RC(int_reg));
 3508   match(RegN);
 3509 
 3510   format %{ %}
 3511   interface(REG_INTER);
 3512 %}
 3513 
 3514 // Question: Why is r15_RegP (the read-only TLS register) a match for rRegP?
 3515 // Answer: Operand match rules govern the DFA as it processes instruction inputs.
 3516 // It's fine for an instruction input that expects rRegP to match a r15_RegP.
 3517 // The output of an instruction is controlled by the allocator, which respects
 3518 // register class masks, not match rules.  Unless an instruction mentions
 3519 // r15_RegP or any_RegP explicitly as its output, r15 will not be considered
 3520 // by the allocator as an input.
 3521 // The same logic applies to rbp_RegP being a match for rRegP: If PreserveFramePointer==true,
 3522 // the RBP is used as a proper frame pointer and is not included in ptr_reg. As a
 3523 // result, RBP is not included in the output of the instruction either.
 3524 
 3525 operand no_rax_RegP()
 3526 %{
 3527   constraint(ALLOC_IN_RC(ptr_no_rax_reg));
 3528   match(RegP);
 3529   match(rbx_RegP);
 3530   match(rsi_RegP);
 3531   match(rdi_RegP);
 3532 
 3533   format %{ %}
 3534   interface(REG_INTER);
 3535 %}
 3536 
 3537 // This operand is not allowed to use RBP even if
 3538 // RBP is not used to hold the frame pointer.
 3539 operand no_rbp_RegP()
 3540 %{
 3541   constraint(ALLOC_IN_RC(ptr_reg_no_rbp));
 3542   match(RegP);
 3543   match(rbx_RegP);
 3544   match(rsi_RegP);
 3545   match(rdi_RegP);
 3546 
 3547   format %{ %}
 3548   interface(REG_INTER);
 3549 %}
 3550 
 3551 operand no_rax_rbx_RegP()
 3552 %{
 3553   constraint(ALLOC_IN_RC(ptr_no_rax_rbx_reg));
 3554   match(RegP);
 3555   match(rsi_RegP);
 3556   match(rdi_RegP);
 3557 
 3558   format %{ %}
 3559   interface(REG_INTER);
 3560 %}
 3561 
 3562 // Special Registers
 3563 // Return a pointer value
 3564 operand rax_RegP()
 3565 %{
 3566   constraint(ALLOC_IN_RC(ptr_rax_reg));
 3567   match(RegP);
 3568   match(rRegP);
 3569 
 3570   format %{ %}
 3571   interface(REG_INTER);
 3572 %}
 3573 
 3574 // Special Registers
 3575 // Return a compressed pointer value
 3576 operand rax_RegN()
 3577 %{
 3578   constraint(ALLOC_IN_RC(int_rax_reg));
 3579   match(RegN);
 3580   match(rRegN);
 3581 
 3582   format %{ %}
 3583   interface(REG_INTER);
 3584 %}
 3585 
 3586 // Used in AtomicAdd
 3587 operand rbx_RegP()
 3588 %{
 3589   constraint(ALLOC_IN_RC(ptr_rbx_reg));
 3590   match(RegP);
 3591   match(rRegP);
 3592 
 3593   format %{ %}
 3594   interface(REG_INTER);
 3595 %}
 3596 
 3597 operand rsi_RegP()
 3598 %{
 3599   constraint(ALLOC_IN_RC(ptr_rsi_reg));
 3600   match(RegP);
 3601   match(rRegP);
 3602 
 3603   format %{ %}
 3604   interface(REG_INTER);
 3605 %}
 3606 
 3607 operand rbp_RegP()
 3608 %{
 3609   constraint(ALLOC_IN_RC(ptr_rbp_reg));
 3610   match(RegP);
 3611   match(rRegP);
 3612 
 3613   format %{ %}
 3614   interface(REG_INTER);
 3615 %}
 3616 
 3617 // Used in rep stosq
 3618 operand rdi_RegP()
 3619 %{
 3620   constraint(ALLOC_IN_RC(ptr_rdi_reg));
 3621   match(RegP);
 3622   match(rRegP);
 3623 
 3624   format %{ %}
 3625   interface(REG_INTER);
 3626 %}
 3627 
 3628 operand r15_RegP()
 3629 %{
 3630   constraint(ALLOC_IN_RC(ptr_r15_reg));
 3631   match(RegP);
 3632   match(rRegP);
 3633 
 3634   format %{ %}
 3635   interface(REG_INTER);
 3636 %}
 3637 
 3638 operand rRegL()
 3639 %{
 3640   constraint(ALLOC_IN_RC(long_reg));
 3641   match(RegL);
 3642   match(rax_RegL);
 3643   match(rdx_RegL);
 3644 
 3645   format %{ %}
 3646   interface(REG_INTER);
 3647 %}
 3648 
 3649 // Special Registers
 3650 operand no_rax_rdx_RegL()
 3651 %{
 3652   constraint(ALLOC_IN_RC(long_no_rax_rdx_reg));
 3653   match(RegL);
 3654   match(rRegL);
 3655 
 3656   format %{ %}
 3657   interface(REG_INTER);
 3658 %}
 3659 
 3660 operand no_rax_RegL()
 3661 %{
 3662   constraint(ALLOC_IN_RC(long_no_rax_rdx_reg));
 3663   match(RegL);
 3664   match(rRegL);
 3665   match(rdx_RegL);
 3666 
 3667   format %{ %}
 3668   interface(REG_INTER);
 3669 %}
 3670 
 3671 operand rax_RegL()
 3672 %{
 3673   constraint(ALLOC_IN_RC(long_rax_reg));
 3674   match(RegL);
 3675   match(rRegL);
 3676 
 3677   format %{ "RAX" %}
 3678   interface(REG_INTER);
 3679 %}
 3680 
 3681 operand rcx_RegL()
 3682 %{
 3683   constraint(ALLOC_IN_RC(long_rcx_reg));
 3684   match(RegL);
 3685   match(rRegL);
 3686 
 3687   format %{ %}
 3688   interface(REG_INTER);
 3689 %}
 3690 
 3691 operand rdx_RegL()
 3692 %{
 3693   constraint(ALLOC_IN_RC(long_rdx_reg));
 3694   match(RegL);
 3695   match(rRegL);
 3696 
 3697   format %{ %}
 3698   interface(REG_INTER);
 3699 %}
 3700 
 3701 // Flags register, used as output of compare instructions
 3702 operand rFlagsReg()
 3703 %{
 3704   constraint(ALLOC_IN_RC(int_flags));
 3705   match(RegFlags);
 3706 
 3707   format %{ "RFLAGS" %}
 3708   interface(REG_INTER);
 3709 %}
 3710 
 3711 // Flags register, used as output of FLOATING POINT compare instructions
 3712 operand rFlagsRegU()
 3713 %{
 3714   constraint(ALLOC_IN_RC(int_flags));
 3715   match(RegFlags);
 3716 
 3717   format %{ "RFLAGS_U" %}
 3718   interface(REG_INTER);
 3719 %}
 3720 
 3721 operand rFlagsRegUCF() %{
 3722   constraint(ALLOC_IN_RC(int_flags));
 3723   match(RegFlags);
 3724   predicate(false);
 3725 
 3726   format %{ "RFLAGS_U_CF" %}
 3727   interface(REG_INTER);
 3728 %}
 3729 
 3730 // Float register operands
 3731 operand regF() %{
 3732    constraint(ALLOC_IN_RC(float_reg));
 3733    match(RegF);
 3734 
 3735    format %{ %}
 3736    interface(REG_INTER);
 3737 %}
 3738 
 3739 // Float register operands
 3740 operand legRegF() %{
 3741    constraint(ALLOC_IN_RC(float_reg_legacy));
 3742    match(RegF);
 3743 
 3744    format %{ %}
 3745    interface(REG_INTER);
 3746 %}
 3747 
 3748 // Float register operands
 3749 operand vlRegF() %{
 3750    constraint(ALLOC_IN_RC(float_reg_vl));
 3751    match(RegF);
 3752 
 3753    format %{ %}
 3754    interface(REG_INTER);
 3755 %}
 3756 
 3757 // Double register operands
 3758 operand regD() %{
 3759    constraint(ALLOC_IN_RC(double_reg));
 3760    match(RegD);
 3761 
 3762    format %{ %}
 3763    interface(REG_INTER);
 3764 %}
 3765 
 3766 // Double register operands
 3767 operand legRegD() %{
 3768    constraint(ALLOC_IN_RC(double_reg_legacy));
 3769    match(RegD);
 3770 
 3771    format %{ %}
 3772    interface(REG_INTER);
 3773 %}
 3774 
 3775 // Double register operands
 3776 operand vlRegD() %{
 3777    constraint(ALLOC_IN_RC(double_reg_vl));
 3778    match(RegD);
 3779 
 3780    format %{ %}
 3781    interface(REG_INTER);
 3782 %}
 3783 
 3784 //----------Memory Operands----------------------------------------------------
 3785 // Direct Memory Operand
 3786 // operand direct(immP addr)
 3787 // %{
 3788 //   match(addr);
 3789 
 3790 //   format %{ "[$addr]" %}
 3791 //   interface(MEMORY_INTER) %{
 3792 //     base(0xFFFFFFFF);
 3793 //     index(0x4);
 3794 //     scale(0x0);
 3795 //     disp($addr);
 3796 //   %}
 3797 // %}
 3798 
 3799 // Indirect Memory Operand
 3800 operand indirect(any_RegP reg)
 3801 %{
 3802   constraint(ALLOC_IN_RC(ptr_reg));
 3803   match(reg);
 3804 
 3805   format %{ "[$reg]" %}
 3806   interface(MEMORY_INTER) %{
 3807     base($reg);
 3808     index(0x4);
 3809     scale(0x0);
 3810     disp(0x0);
 3811   %}
 3812 %}
 3813 
 3814 // Indirect Memory Plus Short Offset Operand
 3815 operand indOffset8(any_RegP reg, immL8 off)
 3816 %{
 3817   constraint(ALLOC_IN_RC(ptr_reg));
 3818   match(AddP reg off);
 3819 
 3820   format %{ "[$reg + $off (8-bit)]" %}
 3821   interface(MEMORY_INTER) %{
 3822     base($reg);
 3823     index(0x4);
 3824     scale(0x0);
 3825     disp($off);
 3826   %}
 3827 %}
 3828 
 3829 // Indirect Memory Plus Long Offset Operand
 3830 operand indOffset32(any_RegP reg, immL32 off)
 3831 %{
 3832   constraint(ALLOC_IN_RC(ptr_reg));
 3833   match(AddP reg off);
 3834 
 3835   format %{ "[$reg + $off (32-bit)]" %}
 3836   interface(MEMORY_INTER) %{
 3837     base($reg);
 3838     index(0x4);
 3839     scale(0x0);
 3840     disp($off);
 3841   %}
 3842 %}
 3843 
 3844 // Indirect Memory Plus Index Register Plus Offset Operand
 3845 operand indIndexOffset(any_RegP reg, rRegL lreg, immL32 off)
 3846 %{
 3847   constraint(ALLOC_IN_RC(ptr_reg));
 3848   match(AddP (AddP reg lreg) off);
 3849 
 3850   op_cost(10);
 3851   format %{"[$reg + $off + $lreg]" %}
 3852   interface(MEMORY_INTER) %{
 3853     base($reg);
 3854     index($lreg);
 3855     scale(0x0);
 3856     disp($off);
 3857   %}
 3858 %}
 3859 
 3860 // Indirect Memory Plus Index Register Plus Offset Operand
 3861 operand indIndex(any_RegP reg, rRegL lreg)
 3862 %{
 3863   constraint(ALLOC_IN_RC(ptr_reg));
 3864   match(AddP reg lreg);
 3865 
 3866   op_cost(10);
 3867   format %{"[$reg + $lreg]" %}
 3868   interface(MEMORY_INTER) %{
 3869     base($reg);
 3870     index($lreg);
 3871     scale(0x0);
 3872     disp(0x0);
 3873   %}
 3874 %}
 3875 
 3876 // Indirect Memory Times Scale Plus Index Register
 3877 operand indIndexScale(any_RegP reg, rRegL lreg, immI2 scale)
 3878 %{
 3879   constraint(ALLOC_IN_RC(ptr_reg));
 3880   match(AddP reg (LShiftL lreg scale));
 3881 
 3882   op_cost(10);
 3883   format %{"[$reg + $lreg << $scale]" %}
 3884   interface(MEMORY_INTER) %{
 3885     base($reg);
 3886     index($lreg);
 3887     scale($scale);
 3888     disp(0x0);
 3889   %}
 3890 %}
 3891 
 3892 operand indPosIndexScale(any_RegP reg, rRegI idx, immI2 scale)
 3893 %{
 3894   constraint(ALLOC_IN_RC(ptr_reg));
 3895   predicate(n->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
 3896   match(AddP reg (LShiftL (ConvI2L idx) scale));
 3897 
 3898   op_cost(10);
 3899   format %{"[$reg + pos $idx << $scale]" %}
 3900   interface(MEMORY_INTER) %{
 3901     base($reg);
 3902     index($idx);
 3903     scale($scale);
 3904     disp(0x0);
 3905   %}
 3906 %}
 3907 
 3908 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
 3909 operand indIndexScaleOffset(any_RegP reg, immL32 off, rRegL lreg, immI2 scale)
 3910 %{
 3911   constraint(ALLOC_IN_RC(ptr_reg));
 3912   match(AddP (AddP reg (LShiftL lreg scale)) off);
 3913 
 3914   op_cost(10);
 3915   format %{"[$reg + $off + $lreg << $scale]" %}
 3916   interface(MEMORY_INTER) %{
 3917     base($reg);
 3918     index($lreg);
 3919     scale($scale);
 3920     disp($off);
 3921   %}
 3922 %}
 3923 
 3924 // Indirect Memory Plus Positive Index Register Plus Offset Operand
 3925 operand indPosIndexOffset(any_RegP reg, immL32 off, rRegI idx)
 3926 %{
 3927   constraint(ALLOC_IN_RC(ptr_reg));
 3928   predicate(n->in(2)->in(3)->as_Type()->type()->is_long()->_lo >= 0);
 3929   match(AddP (AddP reg (ConvI2L idx)) off);
 3930 
 3931   op_cost(10);
 3932   format %{"[$reg + $off + $idx]" %}
 3933   interface(MEMORY_INTER) %{
 3934     base($reg);
 3935     index($idx);
 3936     scale(0x0);
 3937     disp($off);
 3938   %}
 3939 %}
 3940 
 3941 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand
 3942 operand indPosIndexScaleOffset(any_RegP reg, immL32 off, rRegI idx, immI2 scale)
 3943 %{
 3944   constraint(ALLOC_IN_RC(ptr_reg));
 3945   predicate(n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
 3946   match(AddP (AddP reg (LShiftL (ConvI2L idx) scale)) off);
 3947 
 3948   op_cost(10);
 3949   format %{"[$reg + $off + $idx << $scale]" %}
 3950   interface(MEMORY_INTER) %{
 3951     base($reg);
 3952     index($idx);
 3953     scale($scale);
 3954     disp($off);
 3955   %}
 3956 %}
 3957 
 3958 // Indirect Narrow Oop Plus Offset Operand
 3959 // Note: x86 architecture doesn't support "scale * index + offset" without a base
 3960 // we can't free r12 even with CompressedOops::base() == NULL.
 3961 operand indCompressedOopOffset(rRegN reg, immL32 off) %{
 3962   predicate(UseCompressedOops && (CompressedOops::shift() == Address::times_8));
 3963   constraint(ALLOC_IN_RC(ptr_reg));
 3964   match(AddP (DecodeN reg) off);
 3965 
 3966   op_cost(10);
 3967   format %{"[R12 + $reg << 3 + $off] (compressed oop addressing)" %}
 3968   interface(MEMORY_INTER) %{
 3969     base(0xc); // R12
 3970     index($reg);
 3971     scale(0x3);
 3972     disp($off);
 3973   %}
 3974 %}
 3975 
 3976 // Indirect Memory Operand
 3977 operand indirectNarrow(rRegN reg)
 3978 %{
 3979   predicate(CompressedOops::shift() == 0);
 3980   constraint(ALLOC_IN_RC(ptr_reg));
 3981   match(DecodeN reg);
 3982 
 3983   format %{ "[$reg]" %}
 3984   interface(MEMORY_INTER) %{
 3985     base($reg);
 3986     index(0x4);
 3987     scale(0x0);
 3988     disp(0x0);
 3989   %}
 3990 %}
 3991 
 3992 // Indirect Memory Plus Short Offset Operand
 3993 operand indOffset8Narrow(rRegN reg, immL8 off)
 3994 %{
 3995   predicate(CompressedOops::shift() == 0);
 3996   constraint(ALLOC_IN_RC(ptr_reg));
 3997   match(AddP (DecodeN reg) off);
 3998 
 3999   format %{ "[$reg + $off (8-bit)]" %}
 4000   interface(MEMORY_INTER) %{
 4001     base($reg);
 4002     index(0x4);
 4003     scale(0x0);
 4004     disp($off);
 4005   %}
 4006 %}
 4007 
 4008 // Indirect Memory Plus Long Offset Operand
 4009 operand indOffset32Narrow(rRegN reg, immL32 off)
 4010 %{
 4011   predicate(CompressedOops::shift() == 0);
 4012   constraint(ALLOC_IN_RC(ptr_reg));
 4013   match(AddP (DecodeN reg) off);
 4014 
 4015   format %{ "[$reg + $off (32-bit)]" %}
 4016   interface(MEMORY_INTER) %{
 4017     base($reg);
 4018     index(0x4);
 4019     scale(0x0);
 4020     disp($off);
 4021   %}
 4022 %}
 4023 
 4024 // Indirect Memory Plus Index Register Plus Offset Operand
 4025 operand indIndexOffsetNarrow(rRegN reg, rRegL lreg, immL32 off)
 4026 %{
 4027   predicate(CompressedOops::shift() == 0);
 4028   constraint(ALLOC_IN_RC(ptr_reg));
 4029   match(AddP (AddP (DecodeN reg) lreg) off);
 4030 
 4031   op_cost(10);
 4032   format %{"[$reg + $off + $lreg]" %}
 4033   interface(MEMORY_INTER) %{
 4034     base($reg);
 4035     index($lreg);
 4036     scale(0x0);
 4037     disp($off);
 4038   %}
 4039 %}
 4040 
 4041 // Indirect Memory Plus Index Register Plus Offset Operand
 4042 operand indIndexNarrow(rRegN reg, rRegL lreg)
 4043 %{
 4044   predicate(CompressedOops::shift() == 0);
 4045   constraint(ALLOC_IN_RC(ptr_reg));
 4046   match(AddP (DecodeN reg) lreg);
 4047 
 4048   op_cost(10);
 4049   format %{"[$reg + $lreg]" %}
 4050   interface(MEMORY_INTER) %{
 4051     base($reg);
 4052     index($lreg);
 4053     scale(0x0);
 4054     disp(0x0);
 4055   %}
 4056 %}
 4057 
 4058 // Indirect Memory Times Scale Plus Index Register
 4059 operand indIndexScaleNarrow(rRegN reg, rRegL lreg, immI2 scale)
 4060 %{
 4061   predicate(CompressedOops::shift() == 0);
 4062   constraint(ALLOC_IN_RC(ptr_reg));
 4063   match(AddP (DecodeN reg) (LShiftL lreg scale));
 4064 
 4065   op_cost(10);
 4066   format %{"[$reg + $lreg << $scale]" %}
 4067   interface(MEMORY_INTER) %{
 4068     base($reg);
 4069     index($lreg);
 4070     scale($scale);
 4071     disp(0x0);
 4072   %}
 4073 %}
 4074 
 4075 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
 4076 operand indIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegL lreg, immI2 scale)
 4077 %{
 4078   predicate(CompressedOops::shift() == 0);
 4079   constraint(ALLOC_IN_RC(ptr_reg));
 4080   match(AddP (AddP (DecodeN reg) (LShiftL lreg scale)) off);
 4081 
 4082   op_cost(10);
 4083   format %{"[$reg + $off + $lreg << $scale]" %}
 4084   interface(MEMORY_INTER) %{
 4085     base($reg);
 4086     index($lreg);
 4087     scale($scale);
 4088     disp($off);
 4089   %}
 4090 %}
 4091 
 4092 // Indirect Memory Times Plus Positive Index Register Plus Offset Operand
 4093 operand indPosIndexOffsetNarrow(rRegN reg, immL32 off, rRegI idx)
 4094 %{
 4095   constraint(ALLOC_IN_RC(ptr_reg));
 4096   predicate(CompressedOops::shift() == 0 && n->in(2)->in(3)->as_Type()->type()->is_long()->_lo >= 0);
 4097   match(AddP (AddP (DecodeN reg) (ConvI2L idx)) off);
 4098 
 4099   op_cost(10);
 4100   format %{"[$reg + $off + $idx]" %}
 4101   interface(MEMORY_INTER) %{
 4102     base($reg);
 4103     index($idx);
 4104     scale(0x0);
 4105     disp($off);
 4106   %}
 4107 %}
 4108 
 4109 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand
 4110 operand indPosIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegI idx, immI2 scale)
 4111 %{
 4112   constraint(ALLOC_IN_RC(ptr_reg));
 4113   predicate(CompressedOops::shift() == 0 && n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
 4114   match(AddP (AddP (DecodeN reg) (LShiftL (ConvI2L idx) scale)) off);
 4115 
 4116   op_cost(10);
 4117   format %{"[$reg + $off + $idx << $scale]" %}
 4118   interface(MEMORY_INTER) %{
 4119     base($reg);
 4120     index($idx);
 4121     scale($scale);
 4122     disp($off);
 4123   %}
 4124 %}
 4125 
 4126 //----------Special Memory Operands--------------------------------------------
 4127 // Stack Slot Operand - This operand is used for loading and storing temporary
 4128 //                      values on the stack where a match requires a value to
 4129 //                      flow through memory.
 4130 operand stackSlotP(sRegP reg)
 4131 %{
 4132   constraint(ALLOC_IN_RC(stack_slots));
 4133   // No match rule because this operand is only generated in matching
 4134 
 4135   format %{ "[$reg]" %}
 4136   interface(MEMORY_INTER) %{
 4137     base(0x4);   // RSP
 4138     index(0x4);  // No Index
 4139     scale(0x0);  // No Scale
 4140     disp($reg);  // Stack Offset
 4141   %}
 4142 %}
 4143 
 4144 operand stackSlotI(sRegI reg)
 4145 %{
 4146   constraint(ALLOC_IN_RC(stack_slots));
 4147   // No match rule because this operand is only generated in matching
 4148 
 4149   format %{ "[$reg]" %}
 4150   interface(MEMORY_INTER) %{
 4151     base(0x4);   // RSP
 4152     index(0x4);  // No Index
 4153     scale(0x0);  // No Scale
 4154     disp($reg);  // Stack Offset
 4155   %}
 4156 %}
 4157 
 4158 operand stackSlotF(sRegF reg)
 4159 %{
 4160   constraint(ALLOC_IN_RC(stack_slots));
 4161   // No match rule because this operand is only generated in matching
 4162 
 4163   format %{ "[$reg]" %}
 4164   interface(MEMORY_INTER) %{
 4165     base(0x4);   // RSP
 4166     index(0x4);  // No Index
 4167     scale(0x0);  // No Scale
 4168     disp($reg);  // Stack Offset
 4169   %}
 4170 %}
 4171 
 4172 operand stackSlotD(sRegD reg)
 4173 %{
 4174   constraint(ALLOC_IN_RC(stack_slots));
 4175   // No match rule because this operand is only generated in matching
 4176 
 4177   format %{ "[$reg]" %}
 4178   interface(MEMORY_INTER) %{
 4179     base(0x4);   // RSP
 4180     index(0x4);  // No Index
 4181     scale(0x0);  // No Scale
 4182     disp($reg);  // Stack Offset
 4183   %}
 4184 %}
 4185 operand stackSlotL(sRegL reg)
 4186 %{
 4187   constraint(ALLOC_IN_RC(stack_slots));
 4188   // No match rule because this operand is only generated in matching
 4189 
 4190   format %{ "[$reg]" %}
 4191   interface(MEMORY_INTER) %{
 4192     base(0x4);   // RSP
 4193     index(0x4);  // No Index
 4194     scale(0x0);  // No Scale
 4195     disp($reg);  // Stack Offset
 4196   %}
 4197 %}
 4198 
 4199 //----------Conditional Branch Operands----------------------------------------
 4200 // Comparison Op  - This is the operation of the comparison, and is limited to
 4201 //                  the following set of codes:
 4202 //                  L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
 4203 //
 4204 // Other attributes of the comparison, such as unsignedness, are specified
 4205 // by the comparison instruction that sets a condition code flags register.
 4206 // That result is represented by a flags operand whose subtype is appropriate
 4207 // to the unsignedness (etc.) of the comparison.
 4208 //
 4209 // Later, the instruction which matches both the Comparison Op (a Bool) and
 4210 // the flags (produced by the Cmp) specifies the coding of the comparison op
 4211 // by matching a specific subtype of Bool operand below, such as cmpOpU.
 4212 
 4213 // Comparision Code
 4214 operand cmpOp()
 4215 %{
 4216   match(Bool);
 4217 
 4218   format %{ "" %}
 4219   interface(COND_INTER) %{
 4220     equal(0x4, "e");
 4221     not_equal(0x5, "ne");
 4222     less(0xC, "l");
 4223     greater_equal(0xD, "ge");
 4224     less_equal(0xE, "le");
 4225     greater(0xF, "g");
 4226     overflow(0x0, "o");
 4227     no_overflow(0x1, "no");
 4228   %}
 4229 %}
 4230 
 4231 // Comparison Code, unsigned compare.  Used by FP also, with
 4232 // C2 (unordered) turned into GT or LT already.  The other bits
 4233 // C0 and C3 are turned into Carry & Zero flags.
 4234 operand cmpOpU()
 4235 %{
 4236   match(Bool);
 4237 
 4238   format %{ "" %}
 4239   interface(COND_INTER) %{
 4240     equal(0x4, "e");
 4241     not_equal(0x5, "ne");
 4242     less(0x2, "b");
 4243     greater_equal(0x3, "nb");
 4244     less_equal(0x6, "be");
 4245     greater(0x7, "nbe");
 4246     overflow(0x0, "o");
 4247     no_overflow(0x1, "no");
 4248   %}
 4249 %}
 4250 
 4251 
 4252 // Floating comparisons that don't require any fixup for the unordered case
 4253 operand cmpOpUCF() %{
 4254   match(Bool);
 4255   predicate(n->as_Bool()->_test._test == BoolTest::lt ||
 4256             n->as_Bool()->_test._test == BoolTest::ge ||
 4257             n->as_Bool()->_test._test == BoolTest::le ||
 4258             n->as_Bool()->_test._test == BoolTest::gt);
 4259   format %{ "" %}
 4260   interface(COND_INTER) %{
 4261     equal(0x4, "e");
 4262     not_equal(0x5, "ne");
 4263     less(0x2, "b");
 4264     greater_equal(0x3, "nb");
 4265     less_equal(0x6, "be");
 4266     greater(0x7, "nbe");
 4267     overflow(0x0, "o");
 4268     no_overflow(0x1, "no");
 4269   %}
 4270 %}
 4271 
 4272 
 4273 // Floating comparisons that can be fixed up with extra conditional jumps
 4274 operand cmpOpUCF2() %{
 4275   match(Bool);
 4276   predicate(n->as_Bool()->_test._test == BoolTest::ne ||
 4277             n->as_Bool()->_test._test == BoolTest::eq);
 4278   format %{ "" %}
 4279   interface(COND_INTER) %{
 4280     equal(0x4, "e");
 4281     not_equal(0x5, "ne");
 4282     less(0x2, "b");
 4283     greater_equal(0x3, "nb");
 4284     less_equal(0x6, "be");
 4285     greater(0x7, "nbe");
 4286     overflow(0x0, "o");
 4287     no_overflow(0x1, "no");
 4288   %}
 4289 %}
 4290 
 4291 //----------OPERAND CLASSES----------------------------------------------------
 4292 // Operand Classes are groups of operands that are used as to simplify
 4293 // instruction definitions by not requiring the AD writer to specify separate
 4294 // instructions for every form of operand when the instruction accepts
 4295 // multiple operand types with the same basic encoding and format.  The classic
 4296 // case of this is memory operands.
 4297 
 4298 opclass memory(indirect, indOffset8, indOffset32, indIndexOffset, indIndex,
 4299                indIndexScale, indPosIndexScale, indIndexScaleOffset, indPosIndexOffset, indPosIndexScaleOffset,
 4300                indCompressedOopOffset,
 4301                indirectNarrow, indOffset8Narrow, indOffset32Narrow,
 4302                indIndexOffsetNarrow, indIndexNarrow, indIndexScaleNarrow,
 4303                indIndexScaleOffsetNarrow, indPosIndexOffsetNarrow, indPosIndexScaleOffsetNarrow);
 4304 
 4305 //----------PIPELINE-----------------------------------------------------------
 4306 // Rules which define the behavior of the target architectures pipeline.
 4307 pipeline %{
 4308 
 4309 //----------ATTRIBUTES---------------------------------------------------------
 4310 attributes %{
 4311   variable_size_instructions;        // Fixed size instructions
 4312   max_instructions_per_bundle = 3;   // Up to 3 instructions per bundle
 4313   instruction_unit_size = 1;         // An instruction is 1 bytes long
 4314   instruction_fetch_unit_size = 16;  // The processor fetches one line
 4315   instruction_fetch_units = 1;       // of 16 bytes
 4316 
 4317   // List of nop instructions
 4318   nops( MachNop );
 4319 %}
 4320 
 4321 //----------RESOURCES----------------------------------------------------------
 4322 // Resources are the functional units available to the machine
 4323 
 4324 // Generic P2/P3 pipeline
 4325 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of
 4326 // 3 instructions decoded per cycle.
 4327 // 2 load/store ops per cycle, 1 branch, 1 FPU,
 4328 // 3 ALU op, only ALU0 handles mul instructions.
 4329 resources( D0, D1, D2, DECODE = D0 | D1 | D2,
 4330            MS0, MS1, MS2, MEM = MS0 | MS1 | MS2,
 4331            BR, FPU,
 4332            ALU0, ALU1, ALU2, ALU = ALU0 | ALU1 | ALU2);
 4333 
 4334 //----------PIPELINE DESCRIPTION-----------------------------------------------
 4335 // Pipeline Description specifies the stages in the machine's pipeline
 4336 
 4337 // Generic P2/P3 pipeline
 4338 pipe_desc(S0, S1, S2, S3, S4, S5);
 4339 
 4340 //----------PIPELINE CLASSES---------------------------------------------------
 4341 // Pipeline Classes describe the stages in which input and output are
 4342 // referenced by the hardware pipeline.
 4343 
 4344 // Naming convention: ialu or fpu
 4345 // Then: _reg
 4346 // Then: _reg if there is a 2nd register
 4347 // Then: _long if it's a pair of instructions implementing a long
 4348 // Then: _fat if it requires the big decoder
 4349 //   Or: _mem if it requires the big decoder and a memory unit.
 4350 
 4351 // Integer ALU reg operation
 4352 pipe_class ialu_reg(rRegI dst)
 4353 %{
 4354     single_instruction;
 4355     dst    : S4(write);
 4356     dst    : S3(read);
 4357     DECODE : S0;        // any decoder
 4358     ALU    : S3;        // any alu
 4359 %}
 4360 
 4361 // Long ALU reg operation
 4362 pipe_class ialu_reg_long(rRegL dst)
 4363 %{
 4364     instruction_count(2);
 4365     dst    : S4(write);
 4366     dst    : S3(read);
 4367     DECODE : S0(2);     // any 2 decoders
 4368     ALU    : S3(2);     // both alus
 4369 %}
 4370 
 4371 // Integer ALU reg operation using big decoder
 4372 pipe_class ialu_reg_fat(rRegI dst)
 4373 %{
 4374     single_instruction;
 4375     dst    : S4(write);
 4376     dst    : S3(read);
 4377     D0     : S0;        // big decoder only
 4378     ALU    : S3;        // any alu
 4379 %}
 4380 
 4381 // Integer ALU reg-reg operation
 4382 pipe_class ialu_reg_reg(rRegI dst, rRegI src)
 4383 %{
 4384     single_instruction;
 4385     dst    : S4(write);
 4386     src    : S3(read);
 4387     DECODE : S0;        // any decoder
 4388     ALU    : S3;        // any alu
 4389 %}
 4390 
 4391 // Integer ALU reg-reg operation
 4392 pipe_class ialu_reg_reg_fat(rRegI dst, memory src)
 4393 %{
 4394     single_instruction;
 4395     dst    : S4(write);
 4396     src    : S3(read);
 4397     D0     : S0;        // big decoder only
 4398     ALU    : S3;        // any alu
 4399 %}
 4400 
 4401 // Integer ALU reg-mem operation
 4402 pipe_class ialu_reg_mem(rRegI dst, memory mem)
 4403 %{
 4404     single_instruction;
 4405     dst    : S5(write);
 4406     mem    : S3(read);
 4407     D0     : S0;        // big decoder only
 4408     ALU    : S4;        // any alu
 4409     MEM    : S3;        // any mem
 4410 %}
 4411 
 4412 // Integer mem operation (prefetch)
 4413 pipe_class ialu_mem(memory mem)
 4414 %{
 4415     single_instruction;
 4416     mem    : S3(read);
 4417     D0     : S0;        // big decoder only
 4418     MEM    : S3;        // any mem
 4419 %}
 4420 
 4421 // Integer Store to Memory
 4422 pipe_class ialu_mem_reg(memory mem, rRegI src)
 4423 %{
 4424     single_instruction;
 4425     mem    : S3(read);
 4426     src    : S5(read);
 4427     D0     : S0;        // big decoder only
 4428     ALU    : S4;        // any alu
 4429     MEM    : S3;
 4430 %}
 4431 
 4432 // // Long Store to Memory
 4433 // pipe_class ialu_mem_long_reg(memory mem, rRegL src)
 4434 // %{
 4435 //     instruction_count(2);
 4436 //     mem    : S3(read);
 4437 //     src    : S5(read);
 4438 //     D0     : S0(2);          // big decoder only; twice
 4439 //     ALU    : S4(2);     // any 2 alus
 4440 //     MEM    : S3(2);  // Both mems
 4441 // %}
 4442 
 4443 // Integer Store to Memory
 4444 pipe_class ialu_mem_imm(memory mem)
 4445 %{
 4446     single_instruction;
 4447     mem    : S3(read);
 4448     D0     : S0;        // big decoder only
 4449     ALU    : S4;        // any alu
 4450     MEM    : S3;
 4451 %}
 4452 
 4453 // Integer ALU0 reg-reg operation
 4454 pipe_class ialu_reg_reg_alu0(rRegI dst, rRegI src)
 4455 %{
 4456     single_instruction;
 4457     dst    : S4(write);
 4458     src    : S3(read);
 4459     D0     : S0;        // Big decoder only
 4460     ALU0   : S3;        // only alu0
 4461 %}
 4462 
 4463 // Integer ALU0 reg-mem operation
 4464 pipe_class ialu_reg_mem_alu0(rRegI dst, memory mem)
 4465 %{
 4466     single_instruction;
 4467     dst    : S5(write);
 4468     mem    : S3(read);
 4469     D0     : S0;        // big decoder only
 4470     ALU0   : S4;        // ALU0 only
 4471     MEM    : S3;        // any mem
 4472 %}
 4473 
 4474 // Integer ALU reg-reg operation
 4475 pipe_class ialu_cr_reg_reg(rFlagsReg cr, rRegI src1, rRegI src2)
 4476 %{
 4477     single_instruction;
 4478     cr     : S4(write);
 4479     src1   : S3(read);
 4480     src2   : S3(read);
 4481     DECODE : S0;        // any decoder
 4482     ALU    : S3;        // any alu
 4483 %}
 4484 
 4485 // Integer ALU reg-imm operation
 4486 pipe_class ialu_cr_reg_imm(rFlagsReg cr, rRegI src1)
 4487 %{
 4488     single_instruction;
 4489     cr     : S4(write);
 4490     src1   : S3(read);
 4491     DECODE : S0;        // any decoder
 4492     ALU    : S3;        // any alu
 4493 %}
 4494 
 4495 // Integer ALU reg-mem operation
 4496 pipe_class ialu_cr_reg_mem(rFlagsReg cr, rRegI src1, memory src2)
 4497 %{
 4498     single_instruction;
 4499     cr     : S4(write);
 4500     src1   : S3(read);
 4501     src2   : S3(read);
 4502     D0     : S0;        // big decoder only
 4503     ALU    : S4;        // any alu
 4504     MEM    : S3;
 4505 %}
 4506 
 4507 // Conditional move reg-reg
 4508 pipe_class pipe_cmplt( rRegI p, rRegI q, rRegI y)
 4509 %{
 4510     instruction_count(4);
 4511     y      : S4(read);
 4512     q      : S3(read);
 4513     p      : S3(read);
 4514     DECODE : S0(4);     // any decoder
 4515 %}
 4516 
 4517 // Conditional move reg-reg
 4518 pipe_class pipe_cmov_reg( rRegI dst, rRegI src, rFlagsReg cr)
 4519 %{
 4520     single_instruction;
 4521     dst    : S4(write);
 4522     src    : S3(read);
 4523     cr     : S3(read);
 4524     DECODE : S0;        // any decoder
 4525 %}
 4526 
 4527 // Conditional move reg-mem
 4528 pipe_class pipe_cmov_mem( rFlagsReg cr, rRegI dst, memory src)
 4529 %{
 4530     single_instruction;
 4531     dst    : S4(write);
 4532     src    : S3(read);
 4533     cr     : S3(read);
 4534     DECODE : S0;        // any decoder
 4535     MEM    : S3;
 4536 %}
 4537 
 4538 // Conditional move reg-reg long
 4539 pipe_class pipe_cmov_reg_long( rFlagsReg cr, rRegL dst, rRegL src)
 4540 %{
 4541     single_instruction;
 4542     dst    : S4(write);
 4543     src    : S3(read);
 4544     cr     : S3(read);
 4545     DECODE : S0(2);     // any 2 decoders
 4546 %}
 4547 
 4548 // XXX
 4549 // // Conditional move double reg-reg
 4550 // pipe_class pipe_cmovD_reg( rFlagsReg cr, regDPR1 dst, regD src)
 4551 // %{
 4552 //     single_instruction;
 4553 //     dst    : S4(write);
 4554 //     src    : S3(read);
 4555 //     cr     : S3(read);
 4556 //     DECODE : S0;     // any decoder
 4557 // %}
 4558 
 4559 // Float reg-reg operation
 4560 pipe_class fpu_reg(regD dst)
 4561 %{
 4562     instruction_count(2);
 4563     dst    : S3(read);
 4564     DECODE : S0(2);     // any 2 decoders
 4565     FPU    : S3;
 4566 %}
 4567 
 4568 // Float reg-reg operation
 4569 pipe_class fpu_reg_reg(regD dst, regD src)
 4570 %{
 4571     instruction_count(2);
 4572     dst    : S4(write);
 4573     src    : S3(read);
 4574     DECODE : S0(2);     // any 2 decoders
 4575     FPU    : S3;
 4576 %}
 4577 
 4578 // Float reg-reg operation
 4579 pipe_class fpu_reg_reg_reg(regD dst, regD src1, regD src2)
 4580 %{
 4581     instruction_count(3);
 4582     dst    : S4(write);
 4583     src1   : S3(read);
 4584     src2   : S3(read);
 4585     DECODE : S0(3);     // any 3 decoders
 4586     FPU    : S3(2);
 4587 %}
 4588 
 4589 // Float reg-reg operation
 4590 pipe_class fpu_reg_reg_reg_reg(regD dst, regD src1, regD src2, regD src3)
 4591 %{
 4592     instruction_count(4);
 4593     dst    : S4(write);
 4594     src1   : S3(read);
 4595     src2   : S3(read);
 4596     src3   : S3(read);
 4597     DECODE : S0(4);     // any 3 decoders
 4598     FPU    : S3(2);
 4599 %}
 4600 
 4601 // Float reg-reg operation
 4602 pipe_class fpu_reg_mem_reg_reg(regD dst, memory src1, regD src2, regD src3)
 4603 %{
 4604     instruction_count(4);
 4605     dst    : S4(write);
 4606     src1   : S3(read);
 4607     src2   : S3(read);
 4608     src3   : S3(read);
 4609     DECODE : S1(3);     // any 3 decoders
 4610     D0     : S0;        // Big decoder only
 4611     FPU    : S3(2);
 4612     MEM    : S3;
 4613 %}
 4614 
 4615 // Float reg-mem operation
 4616 pipe_class fpu_reg_mem(regD dst, memory mem)
 4617 %{
 4618     instruction_count(2);
 4619     dst    : S5(write);
 4620     mem    : S3(read);
 4621     D0     : S0;        // big decoder only
 4622     DECODE : S1;        // any decoder for FPU POP
 4623     FPU    : S4;
 4624     MEM    : S3;        // any mem
 4625 %}
 4626 
 4627 // Float reg-mem operation
 4628 pipe_class fpu_reg_reg_mem(regD dst, regD src1, memory mem)
 4629 %{
 4630     instruction_count(3);
 4631     dst    : S5(write);
 4632     src1   : S3(read);
 4633     mem    : S3(read);
 4634     D0     : S0;        // big decoder only
 4635     DECODE : S1(2);     // any decoder for FPU POP
 4636     FPU    : S4;
 4637     MEM    : S3;        // any mem
 4638 %}
 4639 
 4640 // Float mem-reg operation
 4641 pipe_class fpu_mem_reg(memory mem, regD src)
 4642 %{
 4643     instruction_count(2);
 4644     src    : S5(read);
 4645     mem    : S3(read);
 4646     DECODE : S0;        // any decoder for FPU PUSH
 4647     D0     : S1;        // big decoder only
 4648     FPU    : S4;
 4649     MEM    : S3;        // any mem
 4650 %}
 4651 
 4652 pipe_class fpu_mem_reg_reg(memory mem, regD src1, regD src2)
 4653 %{
 4654     instruction_count(3);
 4655     src1   : S3(read);
 4656     src2   : S3(read);
 4657     mem    : S3(read);
 4658     DECODE : S0(2);     // any decoder for FPU PUSH
 4659     D0     : S1;        // big decoder only
 4660     FPU    : S4;
 4661     MEM    : S3;        // any mem
 4662 %}
 4663 
 4664 pipe_class fpu_mem_reg_mem(memory mem, regD src1, memory src2)
 4665 %{
 4666     instruction_count(3);
 4667     src1   : S3(read);
 4668     src2   : S3(read);
 4669     mem    : S4(read);
 4670     DECODE : S0;        // any decoder for FPU PUSH
 4671     D0     : S0(2);     // big decoder only
 4672     FPU    : S4;
 4673     MEM    : S3(2);     // any mem
 4674 %}
 4675 
 4676 pipe_class fpu_mem_mem(memory dst, memory src1)
 4677 %{
 4678     instruction_count(2);
 4679     src1   : S3(read);
 4680     dst    : S4(read);
 4681     D0     : S0(2);     // big decoder only
 4682     MEM    : S3(2);     // any mem
 4683 %}
 4684 
 4685 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2)
 4686 %{
 4687     instruction_count(3);
 4688     src1   : S3(read);
 4689     src2   : S3(read);
 4690     dst    : S4(read);
 4691     D0     : S0(3);     // big decoder only
 4692     FPU    : S4;
 4693     MEM    : S3(3);     // any mem
 4694 %}
 4695 
 4696 pipe_class fpu_mem_reg_con(memory mem, regD src1)
 4697 %{
 4698     instruction_count(3);
 4699     src1   : S4(read);
 4700     mem    : S4(read);
 4701     DECODE : S0;        // any decoder for FPU PUSH
 4702     D0     : S0(2);     // big decoder only
 4703     FPU    : S4;
 4704     MEM    : S3(2);     // any mem
 4705 %}
 4706 
 4707 // Float load constant
 4708 pipe_class fpu_reg_con(regD dst)
 4709 %{
 4710     instruction_count(2);
 4711     dst    : S5(write);
 4712     D0     : S0;        // big decoder only for the load
 4713     DECODE : S1;        // any decoder for FPU POP
 4714     FPU    : S4;
 4715     MEM    : S3;        // any mem
 4716 %}
 4717 
 4718 // Float load constant
 4719 pipe_class fpu_reg_reg_con(regD dst, regD src)
 4720 %{
 4721     instruction_count(3);
 4722     dst    : S5(write);
 4723     src    : S3(read);
 4724     D0     : S0;        // big decoder only for the load
 4725     DECODE : S1(2);     // any decoder for FPU POP
 4726     FPU    : S4;
 4727     MEM    : S3;        // any mem
 4728 %}
 4729 
 4730 // UnConditional branch
 4731 pipe_class pipe_jmp(label labl)
 4732 %{
 4733     single_instruction;
 4734     BR   : S3;
 4735 %}
 4736 
 4737 // Conditional branch
 4738 pipe_class pipe_jcc(cmpOp cmp, rFlagsReg cr, label labl)
 4739 %{
 4740     single_instruction;
 4741     cr    : S1(read);
 4742     BR    : S3;
 4743 %}
 4744 
 4745 // Allocation idiom
 4746 pipe_class pipe_cmpxchg(rRegP dst, rRegP heap_ptr)
 4747 %{
 4748     instruction_count(1); force_serialization;
 4749     fixed_latency(6);
 4750     heap_ptr : S3(read);
 4751     DECODE   : S0(3);
 4752     D0       : S2;
 4753     MEM      : S3;
 4754     ALU      : S3(2);
 4755     dst      : S5(write);
 4756     BR       : S5;
 4757 %}
 4758 
 4759 // Generic big/slow expanded idiom
 4760 pipe_class pipe_slow()
 4761 %{
 4762     instruction_count(10); multiple_bundles; force_serialization;
 4763     fixed_latency(100);
 4764     D0  : S0(2);
 4765     MEM : S3(2);
 4766 %}
 4767 
 4768 // The real do-nothing guy
 4769 pipe_class empty()
 4770 %{
 4771     instruction_count(0);
 4772 %}
 4773 
 4774 // Define the class for the Nop node
 4775 define
 4776 %{
 4777    MachNop = empty;
 4778 %}
 4779 
 4780 %}
 4781 
 4782 //----------INSTRUCTIONS-------------------------------------------------------
 4783 //
 4784 // match      -- States which machine-independent subtree may be replaced
 4785 //               by this instruction.
 4786 // ins_cost   -- The estimated cost of this instruction is used by instruction
 4787 //               selection to identify a minimum cost tree of machine
 4788 //               instructions that matches a tree of machine-independent
 4789 //               instructions.
 4790 // format     -- A string providing the disassembly for this instruction.
 4791 //               The value of an instruction's operand may be inserted
 4792 //               by referring to it with a '$' prefix.
 4793 // opcode     -- Three instruction opcodes may be provided.  These are referred
 4794 //               to within an encode class as $primary, $secondary, and $tertiary
 4795 //               rrspectively.  The primary opcode is commonly used to
 4796 //               indicate the type of machine instruction, while secondary
 4797 //               and tertiary are often used for prefix options or addressing
 4798 //               modes.
 4799 // ins_encode -- A list of encode classes with parameters. The encode class
 4800 //               name must have been defined in an 'enc_class' specification
 4801 //               in the encode section of the architecture description.
 4802 
 4803 //----------Load/Store/Move Instructions---------------------------------------
 4804 //----------Load Instructions--------------------------------------------------
 4805 
 4806 // Load Byte (8 bit signed)
 4807 instruct loadB(rRegI dst, memory mem)
 4808 %{
 4809   match(Set dst (LoadB mem));
 4810 
 4811   ins_cost(125);
 4812   format %{ "movsbl  $dst, $mem\t# byte" %}
 4813 
 4814   ins_encode %{
 4815     __ movsbl($dst$$Register, $mem$$Address);
 4816   %}
 4817 
 4818   ins_pipe(ialu_reg_mem);
 4819 %}
 4820 
 4821 // Load Byte (8 bit signed) into Long Register
 4822 instruct loadB2L(rRegL dst, memory mem)
 4823 %{
 4824   match(Set dst (ConvI2L (LoadB mem)));
 4825 
 4826   ins_cost(125);
 4827   format %{ "movsbq  $dst, $mem\t# byte -> long" %}
 4828 
 4829   ins_encode %{
 4830     __ movsbq($dst$$Register, $mem$$Address);
 4831   %}
 4832 
 4833   ins_pipe(ialu_reg_mem);
 4834 %}
 4835 
 4836 // Load Unsigned Byte (8 bit UNsigned)
 4837 instruct loadUB(rRegI dst, memory mem)
 4838 %{
 4839   match(Set dst (LoadUB mem));
 4840 
 4841   ins_cost(125);
 4842   format %{ "movzbl  $dst, $mem\t# ubyte" %}
 4843 
 4844   ins_encode %{
 4845     __ movzbl($dst$$Register, $mem$$Address);
 4846   %}
 4847 
 4848   ins_pipe(ialu_reg_mem);
 4849 %}
 4850 
 4851 // Load Unsigned Byte (8 bit UNsigned) into Long Register
 4852 instruct loadUB2L(rRegL dst, memory mem)
 4853 %{
 4854   match(Set dst (ConvI2L (LoadUB mem)));
 4855 
 4856   ins_cost(125);
 4857   format %{ "movzbq  $dst, $mem\t# ubyte -> long" %}
 4858 
 4859   ins_encode %{
 4860     __ movzbq($dst$$Register, $mem$$Address);
 4861   %}
 4862 
 4863   ins_pipe(ialu_reg_mem);
 4864 %}
 4865 
 4866 // Load Unsigned Byte (8 bit UNsigned) with 32-bit mask into Long Register
 4867 instruct loadUB2L_immI(rRegL dst, memory mem, immI mask, rFlagsReg cr) %{
 4868   match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
 4869   effect(KILL cr);
 4870 
 4871   format %{ "movzbq  $dst, $mem\t# ubyte & 32-bit mask -> long\n\t"
 4872             "andl    $dst, right_n_bits($mask, 8)" %}
 4873   ins_encode %{
 4874     Register Rdst = $dst$$Register;
 4875     __ movzbq(Rdst, $mem$$Address);
 4876     __ andl(Rdst, $mask$$constant & right_n_bits(8));
 4877   %}
 4878   ins_pipe(ialu_reg_mem);
 4879 %}
 4880 
 4881 // Load Short (16 bit signed)
 4882 instruct loadS(rRegI dst, memory mem)
 4883 %{
 4884   match(Set dst (LoadS mem));
 4885 
 4886   ins_cost(125);
 4887   format %{ "movswl $dst, $mem\t# short" %}
 4888 
 4889   ins_encode %{
 4890     __ movswl($dst$$Register, $mem$$Address);
 4891   %}
 4892 
 4893   ins_pipe(ialu_reg_mem);
 4894 %}
 4895 
 4896 // Load Short (16 bit signed) to Byte (8 bit signed)
 4897 instruct loadS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
 4898   match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
 4899 
 4900   ins_cost(125);
 4901   format %{ "movsbl $dst, $mem\t# short -> byte" %}
 4902   ins_encode %{
 4903     __ movsbl($dst$$Register, $mem$$Address);
 4904   %}
 4905   ins_pipe(ialu_reg_mem);
 4906 %}
 4907 
 4908 // Load Short (16 bit signed) into Long Register
 4909 instruct loadS2L(rRegL dst, memory mem)
 4910 %{
 4911   match(Set dst (ConvI2L (LoadS mem)));
 4912 
 4913   ins_cost(125);
 4914   format %{ "movswq $dst, $mem\t# short -> long" %}
 4915 
 4916   ins_encode %{
 4917     __ movswq($dst$$Register, $mem$$Address);
 4918   %}
 4919 
 4920   ins_pipe(ialu_reg_mem);
 4921 %}
 4922 
 4923 // Load Unsigned Short/Char (16 bit UNsigned)
 4924 instruct loadUS(rRegI dst, memory mem)
 4925 %{
 4926   match(Set dst (LoadUS mem));
 4927 
 4928   ins_cost(125);
 4929   format %{ "movzwl  $dst, $mem\t# ushort/char" %}
 4930 
 4931   ins_encode %{
 4932     __ movzwl($dst$$Register, $mem$$Address);
 4933   %}
 4934 
 4935   ins_pipe(ialu_reg_mem);
 4936 %}
 4937 
 4938 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
 4939 instruct loadUS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
 4940   match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
 4941 
 4942   ins_cost(125);
 4943   format %{ "movsbl $dst, $mem\t# ushort -> byte" %}
 4944   ins_encode %{
 4945     __ movsbl($dst$$Register, $mem$$Address);
 4946   %}
 4947   ins_pipe(ialu_reg_mem);
 4948 %}
 4949 
 4950 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register
 4951 instruct loadUS2L(rRegL dst, memory mem)
 4952 %{
 4953   match(Set dst (ConvI2L (LoadUS mem)));
 4954 
 4955   ins_cost(125);
 4956   format %{ "movzwq  $dst, $mem\t# ushort/char -> long" %}
 4957 
 4958   ins_encode %{
 4959     __ movzwq($dst$$Register, $mem$$Address);
 4960   %}
 4961 
 4962   ins_pipe(ialu_reg_mem);
 4963 %}
 4964 
 4965 // Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register
 4966 instruct loadUS2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{
 4967   match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
 4968 
 4969   format %{ "movzbq  $dst, $mem\t# ushort/char & 0xFF -> long" %}
 4970   ins_encode %{
 4971     __ movzbq($dst$$Register, $mem$$Address);
 4972   %}
 4973   ins_pipe(ialu_reg_mem);
 4974 %}
 4975 
 4976 // Load Unsigned Short/Char (16 bit UNsigned) with 32-bit mask into Long Register
 4977 instruct loadUS2L_immI(rRegL dst, memory mem, immI mask, rFlagsReg cr) %{
 4978   match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
 4979   effect(KILL cr);
 4980 
 4981   format %{ "movzwq  $dst, $mem\t# ushort/char & 32-bit mask -> long\n\t"
 4982             "andl    $dst, right_n_bits($mask, 16)" %}
 4983   ins_encode %{
 4984     Register Rdst = $dst$$Register;
 4985     __ movzwq(Rdst, $mem$$Address);
 4986     __ andl(Rdst, $mask$$constant & right_n_bits(16));
 4987   %}
 4988   ins_pipe(ialu_reg_mem);
 4989 %}
 4990 
 4991 // Load Integer
 4992 instruct loadI(rRegI dst, memory mem)
 4993 %{
 4994   match(Set dst (LoadI mem));
 4995 
 4996   ins_cost(125);
 4997   format %{ "movl    $dst, $mem\t# int" %}
 4998 
 4999   ins_encode %{
 5000     __ movl($dst$$Register, $mem$$Address);
 5001   %}
 5002 
 5003   ins_pipe(ialu_reg_mem);
 5004 %}
 5005 
 5006 // Load Integer (32 bit signed) to Byte (8 bit signed)
 5007 instruct loadI2B(rRegI dst, memory mem, immI_24 twentyfour) %{
 5008   match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
 5009 
 5010   ins_cost(125);
 5011   format %{ "movsbl  $dst, $mem\t# int -> byte" %}
 5012   ins_encode %{
 5013     __ movsbl($dst$$Register, $mem$$Address);
 5014   %}
 5015   ins_pipe(ialu_reg_mem);
 5016 %}
 5017 
 5018 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned)
 5019 instruct loadI2UB(rRegI dst, memory mem, immI_255 mask) %{
 5020   match(Set dst (AndI (LoadI mem) mask));
 5021 
 5022   ins_cost(125);
 5023   format %{ "movzbl  $dst, $mem\t# int -> ubyte" %}
 5024   ins_encode %{
 5025     __ movzbl($dst$$Register, $mem$$Address);
 5026   %}
 5027   ins_pipe(ialu_reg_mem);
 5028 %}
 5029 
 5030 // Load Integer (32 bit signed) to Short (16 bit signed)
 5031 instruct loadI2S(rRegI dst, memory mem, immI_16 sixteen) %{
 5032   match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
 5033 
 5034   ins_cost(125);
 5035   format %{ "movswl  $dst, $mem\t# int -> short" %}
 5036   ins_encode %{
 5037     __ movswl($dst$$Register, $mem$$Address);
 5038   %}
 5039   ins_pipe(ialu_reg_mem);
 5040 %}
 5041 
 5042 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned)
 5043 instruct loadI2US(rRegI dst, memory mem, immI_65535 mask) %{
 5044   match(Set dst (AndI (LoadI mem) mask));
 5045 
 5046   ins_cost(125);
 5047   format %{ "movzwl  $dst, $mem\t# int -> ushort/char" %}
 5048   ins_encode %{
 5049     __ movzwl($dst$$Register, $mem$$Address);
 5050   %}
 5051   ins_pipe(ialu_reg_mem);
 5052 %}
 5053 
 5054 // Load Integer into Long Register
 5055 instruct loadI2L(rRegL dst, memory mem)
 5056 %{
 5057   match(Set dst (ConvI2L (LoadI mem)));
 5058 
 5059   ins_cost(125);
 5060   format %{ "movslq  $dst, $mem\t# int -> long" %}
 5061 
 5062   ins_encode %{
 5063     __ movslq($dst$$Register, $mem$$Address);
 5064   %}
 5065 
 5066   ins_pipe(ialu_reg_mem);
 5067 %}
 5068 
 5069 // Load Integer with mask 0xFF into Long Register
 5070 instruct loadI2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{
 5071   match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
 5072 
 5073   format %{ "movzbq  $dst, $mem\t# int & 0xFF -> long" %}
 5074   ins_encode %{
 5075     __ movzbq($dst$$Register, $mem$$Address);
 5076   %}
 5077   ins_pipe(ialu_reg_mem);
 5078 %}
 5079 
 5080 // Load Integer with mask 0xFFFF into Long Register
 5081 instruct loadI2L_immI_65535(rRegL dst, memory mem, immI_65535 mask) %{
 5082   match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
 5083 
 5084   format %{ "movzwq  $dst, $mem\t# int & 0xFFFF -> long" %}
 5085   ins_encode %{
 5086     __ movzwq($dst$$Register, $mem$$Address);
 5087   %}
 5088   ins_pipe(ialu_reg_mem);
 5089 %}
 5090 
 5091 // Load Integer with a 31-bit mask into Long Register
 5092 instruct loadI2L_immU31(rRegL dst, memory mem, immU31 mask, rFlagsReg cr) %{
 5093   match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
 5094   effect(KILL cr);
 5095 
 5096   format %{ "movl    $dst, $mem\t# int & 31-bit mask -> long\n\t"
 5097             "andl    $dst, $mask" %}
 5098   ins_encode %{
 5099     Register Rdst = $dst$$Register;
 5100     __ movl(Rdst, $mem$$Address);
 5101     __ andl(Rdst, $mask$$constant);
 5102   %}
 5103   ins_pipe(ialu_reg_mem);
 5104 %}
 5105 
 5106 // Load Unsigned Integer into Long Register
 5107 instruct loadUI2L(rRegL dst, memory mem, immL_32bits mask)
 5108 %{
 5109   match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
 5110 
 5111   ins_cost(125);
 5112   format %{ "movl    $dst, $mem\t# uint -> long" %}
 5113 
 5114   ins_encode %{
 5115     __ movl($dst$$Register, $mem$$Address);
 5116   %}
 5117 
 5118   ins_pipe(ialu_reg_mem);
 5119 %}
 5120 
 5121 // Load Long
 5122 instruct loadL(rRegL dst, memory mem)
 5123 %{
 5124   match(Set dst (LoadL mem));
 5125 
 5126   ins_cost(125);
 5127   format %{ "movq    $dst, $mem\t# long" %}
 5128 
 5129   ins_encode %{
 5130     __ movq($dst$$Register, $mem$$Address);
 5131   %}
 5132 
 5133   ins_pipe(ialu_reg_mem); // XXX
 5134 %}
 5135 
 5136 // Load Range
 5137 instruct loadRange(rRegI dst, memory mem)
 5138 %{
 5139   match(Set dst (LoadRange mem));
 5140 
 5141   ins_cost(125); // XXX
 5142   format %{ "movl    $dst, $mem\t# range" %}
 5143   ins_encode %{
 5144     __ movl($dst$$Register, $mem$$Address);
 5145   %}
 5146   ins_pipe(ialu_reg_mem);
 5147 %}
 5148 
 5149 // Load Pointer
 5150 instruct loadP(rRegP dst, memory mem)
 5151 %{
 5152   match(Set dst (LoadP mem));
 5153   predicate(n->as_Load()->barrier_data() == 0);
 5154 
 5155   ins_cost(125); // XXX
 5156   format %{ "movq    $dst, $mem\t# ptr" %}
 5157   ins_encode %{
 5158     __ movq($dst$$Register, $mem$$Address);
 5159   %}
 5160   ins_pipe(ialu_reg_mem); // XXX
 5161 %}
 5162 
 5163 // Load Compressed Pointer
 5164 instruct loadN(rRegN dst, memory mem)
 5165 %{
 5166    match(Set dst (LoadN mem));
 5167 
 5168    ins_cost(125); // XXX
 5169    format %{ "movl    $dst, $mem\t# compressed ptr" %}
 5170    ins_encode %{
 5171      __ movl($dst$$Register, $mem$$Address);
 5172    %}
 5173    ins_pipe(ialu_reg_mem); // XXX
 5174 %}
 5175 
 5176 
 5177 // Load Klass Pointer
 5178 instruct loadKlass(rRegP dst, memory mem)
 5179 %{
 5180   match(Set dst (LoadKlass mem));
 5181 
 5182   ins_cost(125); // XXX
 5183   format %{ "movq    $dst, $mem\t# class" %}
 5184   ins_encode %{
 5185     __ movq($dst$$Register, $mem$$Address);
 5186   %}
 5187   ins_pipe(ialu_reg_mem); // XXX
 5188 %}
 5189 
 5190 // Load narrow Klass Pointer
 5191 instruct loadNKlass(rRegN dst, memory mem)
 5192 %{
 5193   match(Set dst (LoadNKlass mem));
 5194 
 5195   ins_cost(125); // XXX
 5196   format %{ "movl    $dst, $mem\t# compressed klass ptr" %}
 5197   ins_encode %{
 5198     __ movl($dst$$Register, $mem$$Address);
 5199   %}
 5200   ins_pipe(ialu_reg_mem); // XXX
 5201 %}
 5202 
 5203 // Load Float
 5204 instruct loadF(regF dst, memory mem)
 5205 %{
 5206   match(Set dst (LoadF mem));
 5207 
 5208   ins_cost(145); // XXX
 5209   format %{ "movss   $dst, $mem\t# float" %}
 5210   ins_encode %{
 5211     __ movflt($dst$$XMMRegister, $mem$$Address);
 5212   %}
 5213   ins_pipe(pipe_slow); // XXX
 5214 %}
 5215 
 5216 // Load Float
 5217 instruct MoveF2VL(vlRegF dst, regF src) %{
 5218   match(Set dst src);
 5219   format %{ "movss $dst,$src\t! load float (4 bytes)" %}
 5220   ins_encode %{
 5221     __ movflt($dst$$XMMRegister, $src$$XMMRegister);
 5222   %}
 5223   ins_pipe( fpu_reg_reg );
 5224 %}
 5225 
 5226 // Load Float
 5227 instruct MoveF2LEG(legRegF dst, regF src) %{
 5228   match(Set dst src);
 5229   format %{ "movss $dst,$src\t# if src != dst load float (4 bytes)" %}
 5230   ins_encode %{
 5231     __ movflt($dst$$XMMRegister, $src$$XMMRegister);
 5232   %}
 5233   ins_pipe( fpu_reg_reg );
 5234 %}
 5235 
 5236 // Load Float
 5237 instruct MoveVL2F(regF dst, vlRegF src) %{
 5238   match(Set dst src);
 5239   format %{ "movss $dst,$src\t! load float (4 bytes)" %}
 5240   ins_encode %{
 5241     __ movflt($dst$$XMMRegister, $src$$XMMRegister);
 5242   %}
 5243   ins_pipe( fpu_reg_reg );
 5244 %}
 5245 
 5246 // Load Float
 5247 instruct MoveLEG2F(regF dst, legRegF src) %{
 5248   match(Set dst src);
 5249   format %{ "movss $dst,$src\t# if src != dst load float (4 bytes)" %}
 5250   ins_encode %{
 5251     __ movflt($dst$$XMMRegister, $src$$XMMRegister);
 5252   %}
 5253   ins_pipe( fpu_reg_reg );
 5254 %}
 5255 
 5256 // Load Double
 5257 instruct loadD_partial(regD dst, memory mem)
 5258 %{
 5259   predicate(!UseXmmLoadAndClearUpper);
 5260   match(Set dst (LoadD mem));
 5261 
 5262   ins_cost(145); // XXX
 5263   format %{ "movlpd  $dst, $mem\t# double" %}
 5264   ins_encode %{
 5265     __ movdbl($dst$$XMMRegister, $mem$$Address);
 5266   %}
 5267   ins_pipe(pipe_slow); // XXX
 5268 %}
 5269 
 5270 instruct loadD(regD dst, memory mem)
 5271 %{
 5272   predicate(UseXmmLoadAndClearUpper);
 5273   match(Set dst (LoadD mem));
 5274 
 5275   ins_cost(145); // XXX
 5276   format %{ "movsd   $dst, $mem\t# double" %}
 5277   ins_encode %{
 5278     __ movdbl($dst$$XMMRegister, $mem$$Address);
 5279   %}
 5280   ins_pipe(pipe_slow); // XXX
 5281 %}
 5282 
 5283 // Load Double
 5284 instruct MoveD2VL(vlRegD dst, regD src) %{
 5285   match(Set dst src);
 5286   format %{ "movsd $dst,$src\t! load double (8 bytes)" %}
 5287   ins_encode %{
 5288     __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
 5289   %}
 5290   ins_pipe( fpu_reg_reg );
 5291 %}
 5292 
 5293 // Load Double
 5294 instruct MoveD2LEG(legRegD dst, regD src) %{
 5295   match(Set dst src);
 5296   format %{ "movsd $dst,$src\t# if src != dst load double (8 bytes)" %}
 5297   ins_encode %{
 5298     __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
 5299   %}
 5300   ins_pipe( fpu_reg_reg );
 5301 %}
 5302 
 5303 // Load Double
 5304 instruct MoveVL2D(regD dst, vlRegD src) %{
 5305   match(Set dst src);
 5306   format %{ "movsd $dst,$src\t! load double (8 bytes)" %}
 5307   ins_encode %{
 5308     __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
 5309   %}
 5310   ins_pipe( fpu_reg_reg );
 5311 %}
 5312 
 5313 // Load Double
 5314 instruct MoveLEG2D(regD dst, legRegD src) %{
 5315   match(Set dst src);
 5316   format %{ "movsd $dst,$src\t# if src != dst load double (8 bytes)" %}
 5317   ins_encode %{
 5318     __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
 5319   %}
 5320   ins_pipe( fpu_reg_reg );
 5321 %}
 5322 
 5323 // Following pseudo code describes the algorithm for max[FD]:
 5324 // Min algorithm is on similar lines
 5325 //  btmp = (b < +0.0) ? a : b
 5326 //  atmp = (b < +0.0) ? b : a
 5327 //  Tmp  = Max_Float(atmp , btmp)
 5328 //  Res  = (atmp == NaN) ? atmp : Tmp
 5329 
 5330 // max = java.lang.Math.max(float a, float b)
 5331 instruct maxF_reg(legRegF dst, legRegF a, legRegF b, legRegF tmp, legRegF atmp, legRegF btmp) %{
 5332   predicate(UseAVX > 0 && !n->is_reduction());
 5333   match(Set dst (MaxF a b));
 5334   effect(USE a, USE b, TEMP tmp, TEMP atmp, TEMP btmp);
 5335   format %{
 5336      "vblendvps        $btmp,$b,$a,$b           \n\t"
 5337      "vblendvps        $atmp,$a,$b,$b           \n\t"
 5338      "vmaxss           $tmp,$atmp,$btmp         \n\t"
 5339      "vcmpps.unordered $btmp,$atmp,$atmp        \n\t"
 5340      "vblendvps        $dst,$tmp,$atmp,$btmp    \n\t"
 5341   %}
 5342   ins_encode %{
 5343     int vector_len = Assembler::AVX_128bit;
 5344     __ vblendvps($btmp$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, vector_len);
 5345     __ vblendvps($atmp$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $b$$XMMRegister, vector_len);
 5346     __ vmaxss($tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister);
 5347     __ vcmpps($btmp$$XMMRegister, $atmp$$XMMRegister, $atmp$$XMMRegister, Assembler::_false, vector_len);
 5348     __ vblendvps($dst$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, vector_len);
 5349  %}
 5350   ins_pipe( pipe_slow );
 5351 %}
 5352 
 5353 instruct maxF_reduction_reg(legRegF dst, legRegF a, legRegF b, legRegF xmmt, rRegI tmp, rFlagsReg cr) %{
 5354   predicate(UseAVX > 0 && n->is_reduction());
 5355   match(Set dst (MaxF a b));
 5356   effect(USE a, USE b, TEMP xmmt, TEMP tmp, KILL cr);
 5357 
 5358   format %{ "$dst = max($a, $b)\t# intrinsic (float)" %}
 5359   ins_encode %{
 5360     emit_fp_min_max(_masm, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $xmmt$$XMMRegister, $tmp$$Register,
 5361                     false /*min*/, true /*single*/);
 5362   %}
 5363   ins_pipe( pipe_slow );
 5364 %}
 5365 
 5366 // max = java.lang.Math.max(double a, double b)
 5367 instruct maxD_reg(legRegD dst, legRegD a, legRegD b, legRegD tmp, legRegD atmp, legRegD btmp) %{
 5368   predicate(UseAVX > 0 && !n->is_reduction());
 5369   match(Set dst (MaxD a b));
 5370   effect(USE a, USE b, TEMP atmp, TEMP btmp, TEMP tmp);
 5371   format %{
 5372      "vblendvpd        $btmp,$b,$a,$b            \n\t"
 5373      "vblendvpd        $atmp,$a,$b,$b            \n\t"
 5374      "vmaxsd           $tmp,$atmp,$btmp          \n\t"
 5375      "vcmppd.unordered $btmp,$atmp,$atmp         \n\t"
 5376      "vblendvpd        $dst,$tmp,$atmp,$btmp     \n\t"
 5377   %}
 5378   ins_encode %{
 5379     int vector_len = Assembler::AVX_128bit;
 5380     __ vblendvpd($btmp$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, vector_len);
 5381     __ vblendvpd($atmp$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $b$$XMMRegister, vector_len);
 5382     __ vmaxsd($tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister);
 5383     __ vcmppd($btmp$$XMMRegister, $atmp$$XMMRegister, $atmp$$XMMRegister, Assembler::_false, vector_len);
 5384     __ vblendvpd($dst$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, vector_len);
 5385   %}
 5386   ins_pipe( pipe_slow );
 5387 %}
 5388 
 5389 instruct maxD_reduction_reg(legRegD dst, legRegD a, legRegD b, legRegD xmmt, rRegL tmp, rFlagsReg cr) %{
 5390   predicate(UseAVX > 0 && n->is_reduction());
 5391   match(Set dst (MaxD a b));
 5392   effect(USE a, USE b, TEMP xmmt, TEMP tmp, KILL cr);
 5393 
 5394   format %{ "$dst = max($a, $b)\t# intrinsic (double)" %}
 5395   ins_encode %{
 5396     emit_fp_min_max(_masm, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $xmmt$$XMMRegister, $tmp$$Register,
 5397                     false /*min*/, false /*single*/);
 5398   %}
 5399   ins_pipe( pipe_slow );
 5400 %}
 5401 
 5402 // min = java.lang.Math.min(float a, float b)
 5403 instruct minF_reg(legRegF dst, legRegF a, legRegF b, legRegF tmp, legRegF atmp, legRegF btmp) %{
 5404   predicate(UseAVX > 0 && !n->is_reduction());
 5405   match(Set dst (MinF a b));
 5406   effect(USE a, USE b, TEMP tmp, TEMP atmp, TEMP btmp);
 5407   format %{
 5408      "vblendvps        $atmp,$a,$b,$a             \n\t"
 5409      "vblendvps        $btmp,$b,$a,$a             \n\t"
 5410      "vminss           $tmp,$atmp,$btmp           \n\t"
 5411      "vcmpps.unordered $btmp,$atmp,$atmp          \n\t"
 5412      "vblendvps        $dst,$tmp,$atmp,$btmp      \n\t"
 5413   %}
 5414   ins_encode %{
 5415     int vector_len = Assembler::AVX_128bit;
 5416     __ vblendvps($atmp$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, vector_len);
 5417     __ vblendvps($btmp$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, $a$$XMMRegister, vector_len);
 5418     __ vminss($tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister);
 5419     __ vcmpps($btmp$$XMMRegister, $atmp$$XMMRegister, $atmp$$XMMRegister, Assembler::_false, vector_len);
 5420     __ vblendvps($dst$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, vector_len);
 5421   %}
 5422   ins_pipe( pipe_slow );
 5423 %}
 5424 
 5425 instruct minF_reduction_reg(legRegF dst, legRegF a, legRegF b, legRegF xmmt, rRegI tmp, rFlagsReg cr) %{
 5426   predicate(UseAVX > 0 && n->is_reduction());
 5427   match(Set dst (MinF a b));
 5428   effect(USE a, USE b, TEMP xmmt, TEMP tmp, KILL cr);
 5429 
 5430   format %{ "$dst = min($a, $b)\t# intrinsic (float)" %}
 5431   ins_encode %{
 5432     emit_fp_min_max(_masm, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $xmmt$$XMMRegister, $tmp$$Register,
 5433                     true /*min*/, true /*single*/);
 5434   %}
 5435   ins_pipe( pipe_slow );
 5436 %}
 5437 
 5438 // min = java.lang.Math.min(double a, double b)
 5439 instruct minD_reg(legRegD dst, legRegD a, legRegD b, legRegD tmp, legRegD atmp, legRegD btmp) %{
 5440   predicate(UseAVX > 0 && !n->is_reduction());
 5441   match(Set dst (MinD a b));
 5442   effect(USE a, USE b, TEMP tmp, TEMP atmp, TEMP btmp);
 5443   format %{
 5444      "vblendvpd        $atmp,$a,$b,$a           \n\t"
 5445      "vblendvpd        $btmp,$b,$a,$a           \n\t"
 5446      "vminsd           $tmp,$atmp,$btmp         \n\t"
 5447      "vcmppd.unordered $btmp,$atmp,$atmp        \n\t"
 5448      "vblendvpd        $dst,$tmp,$atmp,$btmp    \n\t"
 5449   %}
 5450   ins_encode %{
 5451     int vector_len = Assembler::AVX_128bit;
 5452     __ vblendvpd($atmp$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, vector_len);
 5453     __ vblendvpd($btmp$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, $a$$XMMRegister, vector_len);
 5454     __ vminsd($tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister);
 5455     __ vcmppd($btmp$$XMMRegister, $atmp$$XMMRegister, $atmp$$XMMRegister, Assembler::_false, vector_len);
 5456     __ vblendvpd($dst$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, vector_len);
 5457   %}
 5458   ins_pipe( pipe_slow );
 5459 %}
 5460 
 5461 instruct minD_reduction_reg(legRegD dst, legRegD a, legRegD b, legRegD xmmt, rRegL tmp, rFlagsReg cr) %{
 5462   predicate(UseAVX > 0 && n->is_reduction());
 5463   match(Set dst (MinD a b));
 5464   effect(USE a, USE b, TEMP xmmt, TEMP tmp, KILL cr);
 5465 
 5466   format %{ "$dst = min($a, $b)\t# intrinsic (double)" %}
 5467   ins_encode %{
 5468     emit_fp_min_max(_masm, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $xmmt$$XMMRegister, $tmp$$Register,
 5469                     true /*min*/, false /*single*/);
 5470   %}
 5471   ins_pipe( pipe_slow );
 5472 %}
 5473 
 5474 // Load Effective Address
 5475 instruct leaP8(rRegP dst, indOffset8 mem)
 5476 %{
 5477   match(Set dst mem);
 5478 
 5479   ins_cost(110); // XXX
 5480   format %{ "leaq    $dst, $mem\t# ptr 8" %}
 5481   ins_encode %{
 5482     __ leaq($dst$$Register, $mem$$Address);
 5483   %}
 5484   ins_pipe(ialu_reg_reg_fat);
 5485 %}
 5486 
 5487 instruct leaP32(rRegP dst, indOffset32 mem)
 5488 %{
 5489   match(Set dst mem);
 5490 
 5491   ins_cost(110);
 5492   format %{ "leaq    $dst, $mem\t# ptr 32" %}
 5493   ins_encode %{
 5494     __ leaq($dst$$Register, $mem$$Address);
 5495   %}
 5496   ins_pipe(ialu_reg_reg_fat);
 5497 %}
 5498 
 5499 instruct leaPIdxOff(rRegP dst, indIndexOffset mem)
 5500 %{
 5501   match(Set dst mem);
 5502 
 5503   ins_cost(110);
 5504   format %{ "leaq    $dst, $mem\t# ptr idxoff" %}
 5505   ins_encode %{
 5506     __ leaq($dst$$Register, $mem$$Address);
 5507   %}
 5508   ins_pipe(ialu_reg_reg_fat);
 5509 %}
 5510 
 5511 instruct leaPIdxScale(rRegP dst, indIndexScale mem)
 5512 %{
 5513   match(Set dst mem);
 5514 
 5515   ins_cost(110);
 5516   format %{ "leaq    $dst, $mem\t# ptr idxscale" %}
 5517   ins_encode %{
 5518     __ leaq($dst$$Register, $mem$$Address);
 5519   %}
 5520   ins_pipe(ialu_reg_reg_fat);
 5521 %}
 5522 
 5523 instruct leaPPosIdxScale(rRegP dst, indPosIndexScale mem)
 5524 %{
 5525   match(Set dst mem);
 5526 
 5527   ins_cost(110);
 5528   format %{ "leaq    $dst, $mem\t# ptr idxscale" %}
 5529   ins_encode %{
 5530     __ leaq($dst$$Register, $mem$$Address);
 5531   %}
 5532   ins_pipe(ialu_reg_reg_fat);
 5533 %}
 5534 
 5535 instruct leaPIdxScaleOff(rRegP dst, indIndexScaleOffset mem)
 5536 %{
 5537   match(Set dst mem);
 5538 
 5539   ins_cost(110);
 5540   format %{ "leaq    $dst, $mem\t# ptr idxscaleoff" %}
 5541   ins_encode %{
 5542     __ leaq($dst$$Register, $mem$$Address);
 5543   %}
 5544   ins_pipe(ialu_reg_reg_fat);
 5545 %}
 5546 
 5547 instruct leaPPosIdxOff(rRegP dst, indPosIndexOffset mem)
 5548 %{
 5549   match(Set dst mem);
 5550 
 5551   ins_cost(110);
 5552   format %{ "leaq    $dst, $mem\t# ptr posidxoff" %}
 5553   ins_encode %{
 5554     __ leaq($dst$$Register, $mem$$Address);
 5555   %}
 5556   ins_pipe(ialu_reg_reg_fat);
 5557 %}
 5558 
 5559 instruct leaPPosIdxScaleOff(rRegP dst, indPosIndexScaleOffset mem)
 5560 %{
 5561   match(Set dst mem);
 5562 
 5563   ins_cost(110);
 5564   format %{ "leaq    $dst, $mem\t# ptr posidxscaleoff" %}
 5565   ins_encode %{
 5566     __ leaq($dst$$Register, $mem$$Address);
 5567   %}
 5568   ins_pipe(ialu_reg_reg_fat);
 5569 %}
 5570 
 5571 // Load Effective Address which uses Narrow (32-bits) oop
 5572 instruct leaPCompressedOopOffset(rRegP dst, indCompressedOopOffset mem)
 5573 %{
 5574   predicate(UseCompressedOops && (CompressedOops::shift() != 0));
 5575   match(Set dst mem);
 5576 
 5577   ins_cost(110);
 5578   format %{ "leaq    $dst, $mem\t# ptr compressedoopoff32" %}
 5579   ins_encode %{
 5580     __ leaq($dst$$Register, $mem$$Address);
 5581   %}
 5582   ins_pipe(ialu_reg_reg_fat);
 5583 %}
 5584 
 5585 instruct leaP8Narrow(rRegP dst, indOffset8Narrow mem)
 5586 %{
 5587   predicate(CompressedOops::shift() == 0);
 5588   match(Set dst mem);
 5589 
 5590   ins_cost(110); // XXX
 5591   format %{ "leaq    $dst, $mem\t# ptr off8narrow" %}
 5592   ins_encode %{
 5593     __ leaq($dst$$Register, $mem$$Address);
 5594   %}
 5595   ins_pipe(ialu_reg_reg_fat);
 5596 %}
 5597 
 5598 instruct leaP32Narrow(rRegP dst, indOffset32Narrow mem)
 5599 %{
 5600   predicate(CompressedOops::shift() == 0);
 5601   match(Set dst mem);
 5602 
 5603   ins_cost(110);
 5604   format %{ "leaq    $dst, $mem\t# ptr off32narrow" %}
 5605   ins_encode %{
 5606     __ leaq($dst$$Register, $mem$$Address);
 5607   %}
 5608   ins_pipe(ialu_reg_reg_fat);
 5609 %}
 5610 
 5611 instruct leaPIdxOffNarrow(rRegP dst, indIndexOffsetNarrow mem)
 5612 %{
 5613   predicate(CompressedOops::shift() == 0);
 5614   match(Set dst mem);
 5615 
 5616   ins_cost(110);
 5617   format %{ "leaq    $dst, $mem\t# ptr idxoffnarrow" %}
 5618   ins_encode %{
 5619     __ leaq($dst$$Register, $mem$$Address);
 5620   %}
 5621   ins_pipe(ialu_reg_reg_fat);
 5622 %}
 5623 
 5624 instruct leaPIdxScaleNarrow(rRegP dst, indIndexScaleNarrow mem)
 5625 %{
 5626   predicate(CompressedOops::shift() == 0);
 5627   match(Set dst mem);
 5628 
 5629   ins_cost(110);
 5630   format %{ "leaq    $dst, $mem\t# ptr idxscalenarrow" %}
 5631   ins_encode %{
 5632     __ leaq($dst$$Register, $mem$$Address);
 5633   %}
 5634   ins_pipe(ialu_reg_reg_fat);
 5635 %}
 5636 
 5637 instruct leaPIdxScaleOffNarrow(rRegP dst, indIndexScaleOffsetNarrow mem)
 5638 %{
 5639   predicate(CompressedOops::shift() == 0);
 5640   match(Set dst mem);
 5641 
 5642   ins_cost(110);
 5643   format %{ "leaq    $dst, $mem\t# ptr idxscaleoffnarrow" %}
 5644   ins_encode %{
 5645     __ leaq($dst$$Register, $mem$$Address);
 5646   %}
 5647   ins_pipe(ialu_reg_reg_fat);
 5648 %}
 5649 
 5650 instruct leaPPosIdxOffNarrow(rRegP dst, indPosIndexOffsetNarrow mem)
 5651 %{
 5652   predicate(CompressedOops::shift() == 0);
 5653   match(Set dst mem);
 5654 
 5655   ins_cost(110);
 5656   format %{ "leaq    $dst, $mem\t# ptr posidxoffnarrow" %}
 5657   ins_encode %{
 5658     __ leaq($dst$$Register, $mem$$Address);
 5659   %}
 5660   ins_pipe(ialu_reg_reg_fat);
 5661 %}
 5662 
 5663 instruct leaPPosIdxScaleOffNarrow(rRegP dst, indPosIndexScaleOffsetNarrow mem)
 5664 %{
 5665   predicate(CompressedOops::shift() == 0);
 5666   match(Set dst mem);
 5667 
 5668   ins_cost(110);
 5669   format %{ "leaq    $dst, $mem\t# ptr posidxscaleoffnarrow" %}
 5670   ins_encode %{
 5671     __ leaq($dst$$Register, $mem$$Address);
 5672   %}
 5673   ins_pipe(ialu_reg_reg_fat);
 5674 %}
 5675 
 5676 instruct loadConI(rRegI dst, immI src)
 5677 %{
 5678   match(Set dst src);
 5679 
 5680   format %{ "movl    $dst, $src\t# int" %}
 5681   ins_encode %{
 5682     __ movl($dst$$Register, $src$$constant);
 5683   %}
 5684   ins_pipe(ialu_reg_fat); // XXX
 5685 %}
 5686 
 5687 instruct loadConI0(rRegI dst, immI_0 src, rFlagsReg cr)
 5688 %{
 5689   match(Set dst src);
 5690   effect(KILL cr);
 5691 
 5692   ins_cost(50);
 5693   format %{ "xorl    $dst, $dst\t# int" %}
 5694   ins_encode %{
 5695     __ xorl($dst$$Register, $dst$$Register);
 5696   %}
 5697   ins_pipe(ialu_reg);
 5698 %}
 5699 
 5700 instruct loadConL(rRegL dst, immL src)
 5701 %{
 5702   match(Set dst src);
 5703 
 5704   ins_cost(150);
 5705   format %{ "movq    $dst, $src\t# long" %}
 5706   ins_encode %{
 5707     __ mov64($dst$$Register, $src$$constant);
 5708   %}
 5709   ins_pipe(ialu_reg);
 5710 %}
 5711 
 5712 instruct loadConL0(rRegL dst, immL0 src, rFlagsReg cr)
 5713 %{
 5714   match(Set dst src);
 5715   effect(KILL cr);
 5716 
 5717   ins_cost(50);
 5718   format %{ "xorl    $dst, $dst\t# long" %}
 5719   ins_encode %{
 5720     __ xorl($dst$$Register, $dst$$Register);
 5721   %}
 5722   ins_pipe(ialu_reg); // XXX
 5723 %}
 5724 
 5725 instruct loadConUL32(rRegL dst, immUL32 src)
 5726 %{
 5727   match(Set dst src);
 5728 
 5729   ins_cost(60);
 5730   format %{ "movl    $dst, $src\t# long (unsigned 32-bit)" %}
 5731   ins_encode %{
 5732     __ movl($dst$$Register, $src$$constant);
 5733   %}
 5734   ins_pipe(ialu_reg);
 5735 %}
 5736 
 5737 instruct loadConL32(rRegL dst, immL32 src)
 5738 %{
 5739   match(Set dst src);
 5740 
 5741   ins_cost(70);
 5742   format %{ "movq    $dst, $src\t# long (32-bit)" %}
 5743   ins_encode %{
 5744     __ movq($dst$$Register, $src$$constant);
 5745   %}
 5746   ins_pipe(ialu_reg);
 5747 %}
 5748 
 5749 instruct loadConP(rRegP dst, immP con) %{
 5750   match(Set dst con);
 5751 
 5752   format %{ "movq    $dst, $con\t# ptr" %}
 5753   ins_encode %{
 5754     __ mov64($dst$$Register, $con$$constant, $con->constant_reloc(), RELOC_IMM64);
 5755   %}
 5756   ins_pipe(ialu_reg_fat); // XXX
 5757 %}
 5758 
 5759 instruct loadConP0(rRegP dst, immP0 src, rFlagsReg cr)
 5760 %{
 5761   match(Set dst src);
 5762   effect(KILL cr);
 5763 
 5764   ins_cost(50);
 5765   format %{ "xorl    $dst, $dst\t# ptr" %}
 5766   ins_encode %{
 5767     __ xorl($dst$$Register, $dst$$Register);
 5768   %}
 5769   ins_pipe(ialu_reg);
 5770 %}
 5771 
 5772 instruct loadConP31(rRegP dst, immP31 src, rFlagsReg cr)
 5773 %{
 5774   match(Set dst src);
 5775   effect(KILL cr);
 5776 
 5777   ins_cost(60);
 5778   format %{ "movl    $dst, $src\t# ptr (positive 32-bit)" %}
 5779   ins_encode %{
 5780     __ movl($dst$$Register, $src$$constant);
 5781   %}
 5782   ins_pipe(ialu_reg);
 5783 %}
 5784 
 5785 instruct loadConF(regF dst, immF con) %{
 5786   match(Set dst con);
 5787   ins_cost(125);
 5788   format %{ "movss   $dst, [$constantaddress]\t# load from constant table: float=$con" %}
 5789   ins_encode %{
 5790     __ movflt($dst$$XMMRegister, $constantaddress($con));
 5791   %}
 5792   ins_pipe(pipe_slow);
 5793 %}
 5794 
 5795 instruct loadConN0(rRegN dst, immN0 src, rFlagsReg cr) %{
 5796   match(Set dst src);
 5797   effect(KILL cr);
 5798   format %{ "xorq    $dst, $src\t# compressed NULL ptr" %}
 5799   ins_encode %{
 5800     __ xorq($dst$$Register, $dst$$Register);
 5801   %}
 5802   ins_pipe(ialu_reg);
 5803 %}
 5804 
 5805 instruct loadConN(rRegN dst, immN src) %{
 5806   match(Set dst src);
 5807 
 5808   ins_cost(125);
 5809   format %{ "movl    $dst, $src\t# compressed ptr" %}
 5810   ins_encode %{
 5811     address con = (address)$src$$constant;
 5812     if (con == NULL) {
 5813       ShouldNotReachHere();
 5814     } else {
 5815       __ set_narrow_oop($dst$$Register, (jobject)$src$$constant);
 5816     }
 5817   %}
 5818   ins_pipe(ialu_reg_fat); // XXX
 5819 %}
 5820 
 5821 instruct loadConNKlass(rRegN dst, immNKlass src) %{
 5822   match(Set dst src);
 5823 
 5824   ins_cost(125);
 5825   format %{ "movl    $dst, $src\t# compressed klass ptr" %}
 5826   ins_encode %{
 5827     address con = (address)$src$$constant;
 5828     if (con == NULL) {
 5829       ShouldNotReachHere();
 5830     } else {
 5831       __ set_narrow_klass($dst$$Register, (Klass*)$src$$constant);
 5832     }
 5833   %}
 5834   ins_pipe(ialu_reg_fat); // XXX
 5835 %}
 5836 
 5837 instruct loadConF0(regF dst, immF0 src)
 5838 %{
 5839   match(Set dst src);
 5840   ins_cost(100);
 5841 
 5842   format %{ "xorps   $dst, $dst\t# float 0.0" %}
 5843   ins_encode %{
 5844     __ xorps($dst$$XMMRegister, $dst$$XMMRegister);
 5845   %}
 5846   ins_pipe(pipe_slow);
 5847 %}
 5848 
 5849 // Use the same format since predicate() can not be used here.
 5850 instruct loadConD(regD dst, immD con) %{
 5851   match(Set dst con);
 5852   ins_cost(125);
 5853   format %{ "movsd   $dst, [$constantaddress]\t# load from constant table: double=$con" %}
 5854   ins_encode %{
 5855     __ movdbl($dst$$XMMRegister, $constantaddress($con));
 5856   %}
 5857   ins_pipe(pipe_slow);
 5858 %}
 5859 
 5860 instruct loadConD0(regD dst, immD0 src)
 5861 %{
 5862   match(Set dst src);
 5863   ins_cost(100);
 5864 
 5865   format %{ "xorpd   $dst, $dst\t# double 0.0" %}
 5866   ins_encode %{
 5867     __ xorpd ($dst$$XMMRegister, $dst$$XMMRegister);
 5868   %}
 5869   ins_pipe(pipe_slow);
 5870 %}
 5871 
 5872 instruct loadSSI(rRegI dst, stackSlotI src)
 5873 %{
 5874   match(Set dst src);
 5875 
 5876   ins_cost(125);
 5877   format %{ "movl    $dst, $src\t# int stk" %}
 5878   opcode(0x8B);
 5879   ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
 5880   ins_pipe(ialu_reg_mem);
 5881 %}
 5882 
 5883 instruct loadSSL(rRegL dst, stackSlotL src)
 5884 %{
 5885   match(Set dst src);
 5886 
 5887   ins_cost(125);
 5888   format %{ "movq    $dst, $src\t# long stk" %}
 5889   opcode(0x8B);
 5890   ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
 5891   ins_pipe(ialu_reg_mem);
 5892 %}
 5893 
 5894 instruct loadSSP(rRegP dst, stackSlotP src)
 5895 %{
 5896   match(Set dst src);
 5897 
 5898   ins_cost(125);
 5899   format %{ "movq    $dst, $src\t# ptr stk" %}
 5900   opcode(0x8B);
 5901   ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
 5902   ins_pipe(ialu_reg_mem);
 5903 %}
 5904 
 5905 instruct loadSSF(regF dst, stackSlotF src)
 5906 %{
 5907   match(Set dst src);
 5908 
 5909   ins_cost(125);
 5910   format %{ "movss   $dst, $src\t# float stk" %}
 5911   ins_encode %{
 5912     __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
 5913   %}
 5914   ins_pipe(pipe_slow); // XXX
 5915 %}
 5916 
 5917 // Use the same format since predicate() can not be used here.
 5918 instruct loadSSD(regD dst, stackSlotD src)
 5919 %{
 5920   match(Set dst src);
 5921 
 5922   ins_cost(125);
 5923   format %{ "movsd   $dst, $src\t# double stk" %}
 5924   ins_encode  %{
 5925     __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
 5926   %}
 5927   ins_pipe(pipe_slow); // XXX
 5928 %}
 5929 
 5930 // Prefetch instructions for allocation.
 5931 // Must be safe to execute with invalid address (cannot fault).
 5932 
 5933 instruct prefetchAlloc( memory mem ) %{
 5934   predicate(AllocatePrefetchInstr==3);
 5935   match(PrefetchAllocation mem);
 5936   ins_cost(125);
 5937 
 5938   format %{ "PREFETCHW $mem\t# Prefetch allocation into level 1 cache and mark modified" %}
 5939   ins_encode %{
 5940     __ prefetchw($mem$$Address);
 5941   %}
 5942   ins_pipe(ialu_mem);
 5943 %}
 5944 
 5945 instruct prefetchAllocNTA( memory mem ) %{
 5946   predicate(AllocatePrefetchInstr==0);
 5947   match(PrefetchAllocation mem);
 5948   ins_cost(125);
 5949 
 5950   format %{ "PREFETCHNTA $mem\t# Prefetch allocation to non-temporal cache for write" %}
 5951   ins_encode %{
 5952     __ prefetchnta($mem$$Address);
 5953   %}
 5954   ins_pipe(ialu_mem);
 5955 %}
 5956 
 5957 instruct prefetchAllocT0( memory mem ) %{
 5958   predicate(AllocatePrefetchInstr==1);
 5959   match(PrefetchAllocation mem);
 5960   ins_cost(125);
 5961 
 5962   format %{ "PREFETCHT0 $mem\t# Prefetch allocation to level 1 and 2 caches for write" %}
 5963   ins_encode %{
 5964     __ prefetcht0($mem$$Address);
 5965   %}
 5966   ins_pipe(ialu_mem);
 5967 %}
 5968 
 5969 instruct prefetchAllocT2( memory mem ) %{
 5970   predicate(AllocatePrefetchInstr==2);
 5971   match(PrefetchAllocation mem);
 5972   ins_cost(125);
 5973 
 5974   format %{ "PREFETCHT2 $mem\t# Prefetch allocation to level 2 cache for write" %}
 5975   ins_encode %{
 5976     __ prefetcht2($mem$$Address);
 5977   %}
 5978   ins_pipe(ialu_mem);
 5979 %}
 5980 
 5981 //----------Store Instructions-------------------------------------------------
 5982 
 5983 // Store Byte
 5984 instruct storeB(memory mem, rRegI src)
 5985 %{
 5986   match(Set mem (StoreB mem src));
 5987 
 5988   ins_cost(125); // XXX
 5989   format %{ "movb    $mem, $src\t# byte" %}
 5990   ins_encode %{
 5991     __ movb($mem$$Address, $src$$Register);
 5992   %}
 5993   ins_pipe(ialu_mem_reg);
 5994 %}
 5995 
 5996 // Store Char/Short
 5997 instruct storeC(memory mem, rRegI src)
 5998 %{
 5999   match(Set mem (StoreC mem src));
 6000 
 6001   ins_cost(125); // XXX
 6002   format %{ "movw    $mem, $src\t# char/short" %}
 6003   ins_encode %{
 6004     __ movw($mem$$Address, $src$$Register);
 6005   %}
 6006   ins_pipe(ialu_mem_reg);
 6007 %}
 6008 
 6009 // Store Integer
 6010 instruct storeI(memory mem, rRegI src)
 6011 %{
 6012   match(Set mem (StoreI mem src));
 6013 
 6014   ins_cost(125); // XXX
 6015   format %{ "movl    $mem, $src\t# int" %}
 6016   ins_encode %{
 6017     __ movl($mem$$Address, $src$$Register);
 6018   %}
 6019   ins_pipe(ialu_mem_reg);
 6020 %}
 6021 
 6022 // Store Long
 6023 instruct storeL(memory mem, rRegL src)
 6024 %{
 6025   match(Set mem (StoreL mem src));
 6026 
 6027   ins_cost(125); // XXX
 6028   format %{ "movq    $mem, $src\t# long" %}
 6029   ins_encode %{
 6030     __ movq($mem$$Address, $src$$Register);
 6031   %}
 6032   ins_pipe(ialu_mem_reg); // XXX
 6033 %}
 6034 
 6035 // Store Pointer
 6036 instruct storeP(memory mem, any_RegP src)
 6037 %{
 6038   match(Set mem (StoreP mem src));
 6039 
 6040   ins_cost(125); // XXX
 6041   format %{ "movq    $mem, $src\t# ptr" %}
 6042   ins_encode %{
 6043     __ movq($mem$$Address, $src$$Register);
 6044   %}
 6045   ins_pipe(ialu_mem_reg);
 6046 %}
 6047 
 6048 instruct storeImmP0(memory mem, immP0 zero)
 6049 %{
 6050   predicate(UseCompressedOops && (CompressedOops::base() == NULL));
 6051   match(Set mem (StoreP mem zero));
 6052 
 6053   ins_cost(125); // XXX
 6054   format %{ "movq    $mem, R12\t# ptr (R12_heapbase==0)" %}
 6055   ins_encode %{
 6056     __ movq($mem$$Address, r12);
 6057   %}
 6058   ins_pipe(ialu_mem_reg);
 6059 %}
 6060 
 6061 // Store NULL Pointer, mark word, or other simple pointer constant.
 6062 instruct storeImmP(memory mem, immP31 src)
 6063 %{
 6064   match(Set mem (StoreP mem src));
 6065 
 6066   ins_cost(150); // XXX
 6067   format %{ "movq    $mem, $src\t# ptr" %}
 6068   ins_encode %{
 6069     __ movq($mem$$Address, $src$$constant);
 6070   %}
 6071   ins_pipe(ialu_mem_imm);
 6072 %}
 6073 
 6074 // Store Compressed Pointer
 6075 instruct storeN(memory mem, rRegN src)
 6076 %{
 6077   match(Set mem (StoreN mem src));
 6078 
 6079   ins_cost(125); // XXX
 6080   format %{ "movl    $mem, $src\t# compressed ptr" %}
 6081   ins_encode %{
 6082     __ movl($mem$$Address, $src$$Register);
 6083   %}
 6084   ins_pipe(ialu_mem_reg);
 6085 %}
 6086 
 6087 instruct storeNKlass(memory mem, rRegN src)
 6088 %{
 6089   match(Set mem (StoreNKlass mem src));
 6090 
 6091   ins_cost(125); // XXX
 6092   format %{ "movl    $mem, $src\t# compressed klass ptr" %}
 6093   ins_encode %{
 6094     __ movl($mem$$Address, $src$$Register);
 6095   %}
 6096   ins_pipe(ialu_mem_reg);
 6097 %}
 6098 
 6099 instruct storeImmN0(memory mem, immN0 zero)
 6100 %{
 6101   predicate(CompressedOops::base() == NULL);
 6102   match(Set mem (StoreN mem zero));
 6103 
 6104   ins_cost(125); // XXX
 6105   format %{ "movl    $mem, R12\t# compressed ptr (R12_heapbase==0)" %}
 6106   ins_encode %{
 6107     __ movl($mem$$Address, r12);
 6108   %}
 6109   ins_pipe(ialu_mem_reg);
 6110 %}
 6111 
 6112 instruct storeImmN(memory mem, immN src)
 6113 %{
 6114   match(Set mem (StoreN mem src));
 6115 
 6116   ins_cost(150); // XXX
 6117   format %{ "movl    $mem, $src\t# compressed ptr" %}
 6118   ins_encode %{
 6119     address con = (address)$src$$constant;
 6120     if (con == NULL) {
 6121       __ movl($mem$$Address, (int32_t)0);
 6122     } else {
 6123       __ set_narrow_oop($mem$$Address, (jobject)$src$$constant);
 6124     }
 6125   %}
 6126   ins_pipe(ialu_mem_imm);
 6127 %}
 6128 
 6129 instruct storeImmNKlass(memory mem, immNKlass src)
 6130 %{
 6131   match(Set mem (StoreNKlass mem src));
 6132 
 6133   ins_cost(150); // XXX
 6134   format %{ "movl    $mem, $src\t# compressed klass ptr" %}
 6135   ins_encode %{
 6136     __ set_narrow_klass($mem$$Address, (Klass*)$src$$constant);
 6137   %}
 6138   ins_pipe(ialu_mem_imm);
 6139 %}
 6140 
 6141 // Store Integer Immediate
 6142 instruct storeImmI0(memory mem, immI_0 zero)
 6143 %{
 6144   predicate(UseCompressedOops && (CompressedOops::base() == NULL));
 6145   match(Set mem (StoreI mem zero));
 6146 
 6147   ins_cost(125); // XXX
 6148   format %{ "movl    $mem, R12\t# int (R12_heapbase==0)" %}
 6149   ins_encode %{
 6150     __ movl($mem$$Address, r12);
 6151   %}
 6152   ins_pipe(ialu_mem_reg);
 6153 %}
 6154 
 6155 instruct storeImmI(memory mem, immI src)
 6156 %{
 6157   match(Set mem (StoreI mem src));
 6158 
 6159   ins_cost(150);
 6160   format %{ "movl    $mem, $src\t# int" %}
 6161   ins_encode %{
 6162     __ movl($mem$$Address, $src$$constant);
 6163   %}
 6164   ins_pipe(ialu_mem_imm);
 6165 %}
 6166 
 6167 // Store Long Immediate
 6168 instruct storeImmL0(memory mem, immL0 zero)
 6169 %{
 6170   predicate(UseCompressedOops && (CompressedOops::base() == NULL));
 6171   match(Set mem (StoreL mem zero));
 6172 
 6173   ins_cost(125); // XXX
 6174   format %{ "movq    $mem, R12\t# long (R12_heapbase==0)" %}
 6175   ins_encode %{
 6176     __ movq($mem$$Address, r12);
 6177   %}
 6178   ins_pipe(ialu_mem_reg);
 6179 %}
 6180 
 6181 instruct storeImmL(memory mem, immL32 src)
 6182 %{
 6183   match(Set mem (StoreL mem src));
 6184 
 6185   ins_cost(150);
 6186   format %{ "movq    $mem, $src\t# long" %}
 6187   ins_encode %{
 6188     __ movq($mem$$Address, $src$$constant);
 6189   %}
 6190   ins_pipe(ialu_mem_imm);
 6191 %}
 6192 
 6193 // Store Short/Char Immediate
 6194 instruct storeImmC0(memory mem, immI_0 zero)
 6195 %{
 6196   predicate(UseCompressedOops && (CompressedOops::base() == NULL));
 6197   match(Set mem (StoreC mem zero));
 6198 
 6199   ins_cost(125); // XXX
 6200   format %{ "movw    $mem, R12\t# short/char (R12_heapbase==0)" %}
 6201   ins_encode %{
 6202     __ movw($mem$$Address, r12);
 6203   %}
 6204   ins_pipe(ialu_mem_reg);
 6205 %}
 6206 
 6207 instruct storeImmI16(memory mem, immI16 src)
 6208 %{
 6209   predicate(UseStoreImmI16);
 6210   match(Set mem (StoreC mem src));
 6211 
 6212   ins_cost(150);
 6213   format %{ "movw    $mem, $src\t# short/char" %}
 6214   ins_encode %{
 6215     __ movw($mem$$Address, $src$$constant);
 6216   %}
 6217   ins_pipe(ialu_mem_imm);
 6218 %}
 6219 
 6220 // Store Byte Immediate
 6221 instruct storeImmB0(memory mem, immI_0 zero)
 6222 %{
 6223   predicate(UseCompressedOops && (CompressedOops::base() == NULL));
 6224   match(Set mem (StoreB mem zero));
 6225 
 6226   ins_cost(125); // XXX
 6227   format %{ "movb    $mem, R12\t# short/char (R12_heapbase==0)" %}
 6228   ins_encode %{
 6229     __ movb($mem$$Address, r12);
 6230   %}
 6231   ins_pipe(ialu_mem_reg);
 6232 %}
 6233 
 6234 instruct storeImmB(memory mem, immI8 src)
 6235 %{
 6236   match(Set mem (StoreB mem src));
 6237 
 6238   ins_cost(150); // XXX
 6239   format %{ "movb    $mem, $src\t# byte" %}
 6240   ins_encode %{
 6241     __ movb($mem$$Address, $src$$constant);
 6242   %}
 6243   ins_pipe(ialu_mem_imm);
 6244 %}
 6245 
 6246 // Store CMS card-mark Immediate
 6247 instruct storeImmCM0_reg(memory mem, immI_0 zero)
 6248 %{
 6249   predicate(UseCompressedOops && (CompressedOops::base() == NULL));
 6250   match(Set mem (StoreCM mem zero));
 6251 
 6252   ins_cost(125); // XXX
 6253   format %{ "movb    $mem, R12\t# CMS card-mark byte 0 (R12_heapbase==0)" %}
 6254   ins_encode %{
 6255     __ movb($mem$$Address, r12);
 6256   %}
 6257   ins_pipe(ialu_mem_reg);
 6258 %}
 6259 
 6260 instruct storeImmCM0(memory mem, immI_0 src)
 6261 %{
 6262   match(Set mem (StoreCM mem src));
 6263 
 6264   ins_cost(150); // XXX
 6265   format %{ "movb    $mem, $src\t# CMS card-mark byte 0" %}
 6266   ins_encode %{
 6267     __ movb($mem$$Address, $src$$constant);
 6268   %}
 6269   ins_pipe(ialu_mem_imm);
 6270 %}
 6271 
 6272 // Store Float
 6273 instruct storeF(memory mem, regF src)
 6274 %{
 6275   match(Set mem (StoreF mem src));
 6276 
 6277   ins_cost(95); // XXX
 6278   format %{ "movss   $mem, $src\t# float" %}
 6279   ins_encode %{
 6280     __ movflt($mem$$Address, $src$$XMMRegister);
 6281   %}
 6282   ins_pipe(pipe_slow); // XXX
 6283 %}
 6284 
 6285 // Store immediate Float value (it is faster than store from XMM register)
 6286 instruct storeF0(memory mem, immF0 zero)
 6287 %{
 6288   predicate(UseCompressedOops && (CompressedOops::base() == NULL));
 6289   match(Set mem (StoreF mem zero));
 6290 
 6291   ins_cost(25); // XXX
 6292   format %{ "movl    $mem, R12\t# float 0. (R12_heapbase==0)" %}
 6293   ins_encode %{
 6294     __ movl($mem$$Address, r12);
 6295   %}
 6296   ins_pipe(ialu_mem_reg);
 6297 %}
 6298 
 6299 instruct storeF_imm(memory mem, immF src)
 6300 %{
 6301   match(Set mem (StoreF mem src));
 6302 
 6303   ins_cost(50);
 6304   format %{ "movl    $mem, $src\t# float" %}
 6305   ins_encode %{
 6306     __ movl($mem$$Address, jint_cast($src$$constant));
 6307   %}
 6308   ins_pipe(ialu_mem_imm);
 6309 %}
 6310 
 6311 // Store Double
 6312 instruct storeD(memory mem, regD src)
 6313 %{
 6314   match(Set mem (StoreD mem src));
 6315 
 6316   ins_cost(95); // XXX
 6317   format %{ "movsd   $mem, $src\t# double" %}
 6318   ins_encode %{
 6319     __ movdbl($mem$$Address, $src$$XMMRegister);
 6320   %}
 6321   ins_pipe(pipe_slow); // XXX
 6322 %}
 6323 
 6324 // Store immediate double 0.0 (it is faster than store from XMM register)
 6325 instruct storeD0_imm(memory mem, immD0 src)
 6326 %{
 6327   predicate(!UseCompressedOops || (CompressedOops::base() != NULL));
 6328   match(Set mem (StoreD mem src));
 6329 
 6330   ins_cost(50);
 6331   format %{ "movq    $mem, $src\t# double 0." %}
 6332   ins_encode %{
 6333     __ movq($mem$$Address, $src$$constant);
 6334   %}
 6335   ins_pipe(ialu_mem_imm);
 6336 %}
 6337 
 6338 instruct storeD0(memory mem, immD0 zero)
 6339 %{
 6340   predicate(UseCompressedOops && (CompressedOops::base() == NULL));
 6341   match(Set mem (StoreD mem zero));
 6342 
 6343   ins_cost(25); // XXX
 6344   format %{ "movq    $mem, R12\t# double 0. (R12_heapbase==0)" %}
 6345   ins_encode %{
 6346     __ movq($mem$$Address, r12);
 6347   %}
 6348   ins_pipe(ialu_mem_reg);
 6349 %}
 6350 
 6351 instruct storeSSI(stackSlotI dst, rRegI src)
 6352 %{
 6353   match(Set dst src);
 6354 
 6355   ins_cost(100);
 6356   format %{ "movl    $dst, $src\t# int stk" %}
 6357   opcode(0x89);
 6358   ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
 6359   ins_pipe( ialu_mem_reg );
 6360 %}
 6361 
 6362 instruct storeSSL(stackSlotL dst, rRegL src)
 6363 %{
 6364   match(Set dst src);
 6365 
 6366   ins_cost(100);
 6367   format %{ "movq    $dst, $src\t# long stk" %}
 6368   opcode(0x89);
 6369   ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
 6370   ins_pipe(ialu_mem_reg);
 6371 %}
 6372 
 6373 instruct storeSSP(stackSlotP dst, rRegP src)
 6374 %{
 6375   match(Set dst src);
 6376 
 6377   ins_cost(100);
 6378   format %{ "movq    $dst, $src\t# ptr stk" %}
 6379   opcode(0x89);
 6380   ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
 6381   ins_pipe(ialu_mem_reg);
 6382 %}
 6383 
 6384 instruct storeSSF(stackSlotF dst, regF src)
 6385 %{
 6386   match(Set dst src);
 6387 
 6388   ins_cost(95); // XXX
 6389   format %{ "movss   $dst, $src\t# float stk" %}
 6390   ins_encode %{
 6391     __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
 6392   %}
 6393   ins_pipe(pipe_slow); // XXX
 6394 %}
 6395 
 6396 instruct storeSSD(stackSlotD dst, regD src)
 6397 %{
 6398   match(Set dst src);
 6399 
 6400   ins_cost(95); // XXX
 6401   format %{ "movsd   $dst, $src\t# double stk" %}
 6402   ins_encode %{
 6403     __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
 6404   %}
 6405   ins_pipe(pipe_slow); // XXX
 6406 %}
 6407 
 6408 instruct cacheWB(indirect addr)
 6409 %{
 6410   predicate(VM_Version::supports_data_cache_line_flush());
 6411   match(CacheWB addr);
 6412 
 6413   ins_cost(100);
 6414   format %{"cache wb $addr" %}
 6415   ins_encode %{
 6416     assert($addr->index_position() < 0, "should be");
 6417     assert($addr$$disp == 0, "should be");
 6418     __ cache_wb(Address($addr$$base$$Register, 0));
 6419   %}
 6420   ins_pipe(pipe_slow); // XXX
 6421 %}
 6422 
 6423 instruct cacheWBPreSync()
 6424 %{
 6425   predicate(VM_Version::supports_data_cache_line_flush());
 6426   match(CacheWBPreSync);
 6427 
 6428   ins_cost(100);
 6429   format %{"cache wb presync" %}
 6430   ins_encode %{
 6431     __ cache_wbsync(true);
 6432   %}
 6433   ins_pipe(pipe_slow); // XXX
 6434 %}
 6435 
 6436 instruct cacheWBPostSync()
 6437 %{
 6438   predicate(VM_Version::supports_data_cache_line_flush());
 6439   match(CacheWBPostSync);
 6440 
 6441   ins_cost(100);
 6442   format %{"cache wb postsync" %}
 6443   ins_encode %{
 6444     __ cache_wbsync(false);
 6445   %}
 6446   ins_pipe(pipe_slow); // XXX
 6447 %}
 6448 
 6449 //----------BSWAP Instructions-------------------------------------------------
 6450 instruct bytes_reverse_int(rRegI dst) %{
 6451   match(Set dst (ReverseBytesI dst));
 6452 
 6453   format %{ "bswapl  $dst" %}
 6454   ins_encode %{
 6455     __ bswapl($dst$$Register);
 6456   %}
 6457   ins_pipe( ialu_reg );
 6458 %}
 6459 
 6460 instruct bytes_reverse_long(rRegL dst) %{
 6461   match(Set dst (ReverseBytesL dst));
 6462 
 6463   format %{ "bswapq  $dst" %}
 6464   ins_encode %{
 6465     __ bswapq($dst$$Register);
 6466   %}
 6467   ins_pipe( ialu_reg);
 6468 %}
 6469 
 6470 instruct bytes_reverse_unsigned_short(rRegI dst, rFlagsReg cr) %{
 6471   match(Set dst (ReverseBytesUS dst));
 6472   effect(KILL cr);
 6473 
 6474   format %{ "bswapl  $dst\n\t"
 6475             "shrl    $dst,16\n\t" %}
 6476   ins_encode %{
 6477     __ bswapl($dst$$Register);
 6478     __ shrl($dst$$Register, 16);
 6479   %}
 6480   ins_pipe( ialu_reg );
 6481 %}
 6482 
 6483 instruct bytes_reverse_short(rRegI dst, rFlagsReg cr) %{
 6484   match(Set dst (ReverseBytesS dst));
 6485   effect(KILL cr);
 6486 
 6487   format %{ "bswapl  $dst\n\t"
 6488             "sar     $dst,16\n\t" %}
 6489   ins_encode %{
 6490     __ bswapl($dst$$Register);
 6491     __ sarl($dst$$Register, 16);
 6492   %}
 6493   ins_pipe( ialu_reg );
 6494 %}
 6495 
 6496 //---------- Zeros Count Instructions ------------------------------------------
 6497 
 6498 instruct countLeadingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{
 6499   predicate(UseCountLeadingZerosInstruction);
 6500   match(Set dst (CountLeadingZerosI src));
 6501   effect(KILL cr);
 6502 
 6503   format %{ "lzcntl  $dst, $src\t# count leading zeros (int)" %}
 6504   ins_encode %{
 6505     __ lzcntl($dst$$Register, $src$$Register);
 6506   %}
 6507   ins_pipe(ialu_reg);
 6508 %}
 6509 
 6510 instruct countLeadingZerosI_bsr(rRegI dst, rRegI src, rFlagsReg cr) %{
 6511   predicate(!UseCountLeadingZerosInstruction);
 6512   match(Set dst (CountLeadingZerosI src));
 6513   effect(KILL cr);
 6514 
 6515   format %{ "bsrl    $dst, $src\t# count leading zeros (int)\n\t"
 6516             "jnz     skip\n\t"
 6517             "movl    $dst, -1\n"
 6518       "skip:\n\t"
 6519             "negl    $dst\n\t"
 6520             "addl    $dst, 31" %}
 6521   ins_encode %{
 6522     Register Rdst = $dst$$Register;
 6523     Register Rsrc = $src$$Register;
 6524     Label skip;
 6525     __ bsrl(Rdst, Rsrc);
 6526     __ jccb(Assembler::notZero, skip);
 6527     __ movl(Rdst, -1);
 6528     __ bind(skip);
 6529     __ negl(Rdst);
 6530     __ addl(Rdst, BitsPerInt - 1);
 6531   %}
 6532   ins_pipe(ialu_reg);
 6533 %}
 6534 
 6535 instruct countLeadingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{
 6536   predicate(UseCountLeadingZerosInstruction);
 6537   match(Set dst (CountLeadingZerosL src));
 6538   effect(KILL cr);
 6539 
 6540   format %{ "lzcntq  $dst, $src\t# count leading zeros (long)" %}
 6541   ins_encode %{
 6542     __ lzcntq($dst$$Register, $src$$Register);
 6543   %}
 6544   ins_pipe(ialu_reg);
 6545 %}
 6546 
 6547 instruct countLeadingZerosL_bsr(rRegI dst, rRegL src, rFlagsReg cr) %{
 6548   predicate(!UseCountLeadingZerosInstruction);
 6549   match(Set dst (CountLeadingZerosL src));
 6550   effect(KILL cr);
 6551 
 6552   format %{ "bsrq    $dst, $src\t# count leading zeros (long)\n\t"
 6553             "jnz     skip\n\t"
 6554             "movl    $dst, -1\n"
 6555       "skip:\n\t"
 6556             "negl    $dst\n\t"
 6557             "addl    $dst, 63" %}
 6558   ins_encode %{
 6559     Register Rdst = $dst$$Register;
 6560     Register Rsrc = $src$$Register;
 6561     Label skip;
 6562     __ bsrq(Rdst, Rsrc);
 6563     __ jccb(Assembler::notZero, skip);
 6564     __ movl(Rdst, -1);
 6565     __ bind(skip);
 6566     __ negl(Rdst);
 6567     __ addl(Rdst, BitsPerLong - 1);
 6568   %}
 6569   ins_pipe(ialu_reg);
 6570 %}
 6571 
 6572 instruct countTrailingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{
 6573   predicate(UseCountTrailingZerosInstruction);
 6574   match(Set dst (CountTrailingZerosI src));
 6575   effect(KILL cr);
 6576 
 6577   format %{ "tzcntl    $dst, $src\t# count trailing zeros (int)" %}
 6578   ins_encode %{
 6579     __ tzcntl($dst$$Register, $src$$Register);
 6580   %}
 6581   ins_pipe(ialu_reg);
 6582 %}
 6583 
 6584 instruct countTrailingZerosI_bsf(rRegI dst, rRegI src, rFlagsReg cr) %{
 6585   predicate(!UseCountTrailingZerosInstruction);
 6586   match(Set dst (CountTrailingZerosI src));
 6587   effect(KILL cr);
 6588 
 6589   format %{ "bsfl    $dst, $src\t# count trailing zeros (int)\n\t"
 6590             "jnz     done\n\t"
 6591             "movl    $dst, 32\n"
 6592       "done:" %}
 6593   ins_encode %{
 6594     Register Rdst = $dst$$Register;
 6595     Label done;
 6596     __ bsfl(Rdst, $src$$Register);
 6597     __ jccb(Assembler::notZero, done);
 6598     __ movl(Rdst, BitsPerInt);
 6599     __ bind(done);
 6600   %}
 6601   ins_pipe(ialu_reg);
 6602 %}
 6603 
 6604 instruct countTrailingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{
 6605   predicate(UseCountTrailingZerosInstruction);
 6606   match(Set dst (CountTrailingZerosL src));
 6607   effect(KILL cr);
 6608 
 6609   format %{ "tzcntq    $dst, $src\t# count trailing zeros (long)" %}
 6610   ins_encode %{
 6611     __ tzcntq($dst$$Register, $src$$Register);
 6612   %}
 6613   ins_pipe(ialu_reg);
 6614 %}
 6615 
 6616 instruct countTrailingZerosL_bsf(rRegI dst, rRegL src, rFlagsReg cr) %{
 6617   predicate(!UseCountTrailingZerosInstruction);
 6618   match(Set dst (CountTrailingZerosL src));
 6619   effect(KILL cr);
 6620 
 6621   format %{ "bsfq    $dst, $src\t# count trailing zeros (long)\n\t"
 6622             "jnz     done\n\t"
 6623             "movl    $dst, 64\n"
 6624       "done:" %}
 6625   ins_encode %{
 6626     Register Rdst = $dst$$Register;
 6627     Label done;
 6628     __ bsfq(Rdst, $src$$Register);
 6629     __ jccb(Assembler::notZero, done);
 6630     __ movl(Rdst, BitsPerLong);
 6631     __ bind(done);
 6632   %}
 6633   ins_pipe(ialu_reg);
 6634 %}
 6635 
 6636 
 6637 //---------- Population Count Instructions -------------------------------------
 6638 
 6639 instruct popCountI(rRegI dst, rRegI src, rFlagsReg cr) %{
 6640   predicate(UsePopCountInstruction);
 6641   match(Set dst (PopCountI src));
 6642   effect(KILL cr);
 6643 
 6644   format %{ "popcnt  $dst, $src" %}
 6645   ins_encode %{
 6646     __ popcntl($dst$$Register, $src$$Register);
 6647   %}
 6648   ins_pipe(ialu_reg);
 6649 %}
 6650 
 6651 instruct popCountI_mem(rRegI dst, memory mem, rFlagsReg cr) %{
 6652   predicate(UsePopCountInstruction);
 6653   match(Set dst (PopCountI (LoadI mem)));
 6654   effect(KILL cr);
 6655 
 6656   format %{ "popcnt  $dst, $mem" %}
 6657   ins_encode %{
 6658     __ popcntl($dst$$Register, $mem$$Address);
 6659   %}
 6660   ins_pipe(ialu_reg);
 6661 %}
 6662 
 6663 // Note: Long.bitCount(long) returns an int.
 6664 instruct popCountL(rRegI dst, rRegL src, rFlagsReg cr) %{
 6665   predicate(UsePopCountInstruction);
 6666   match(Set dst (PopCountL src));
 6667   effect(KILL cr);
 6668 
 6669   format %{ "popcnt  $dst, $src" %}
 6670   ins_encode %{
 6671     __ popcntq($dst$$Register, $src$$Register);
 6672   %}
 6673   ins_pipe(ialu_reg);
 6674 %}
 6675 
 6676 // Note: Long.bitCount(long) returns an int.
 6677 instruct popCountL_mem(rRegI dst, memory mem, rFlagsReg cr) %{
 6678   predicate(UsePopCountInstruction);
 6679   match(Set dst (PopCountL (LoadL mem)));
 6680   effect(KILL cr);
 6681 
 6682   format %{ "popcnt  $dst, $mem" %}
 6683   ins_encode %{
 6684     __ popcntq($dst$$Register, $mem$$Address);
 6685   %}
 6686   ins_pipe(ialu_reg);
 6687 %}
 6688 
 6689 
 6690 //----------MemBar Instructions-----------------------------------------------
 6691 // Memory barrier flavors
 6692 
 6693 instruct membar_acquire()
 6694 %{
 6695   match(MemBarAcquire);
 6696   match(LoadFence);
 6697   ins_cost(0);
 6698 
 6699   size(0);
 6700   format %{ "MEMBAR-acquire ! (empty encoding)" %}
 6701   ins_encode();
 6702   ins_pipe(empty);
 6703 %}
 6704 
 6705 instruct membar_acquire_lock()
 6706 %{
 6707   match(MemBarAcquireLock);
 6708   ins_cost(0);
 6709 
 6710   size(0);
 6711   format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %}
 6712   ins_encode();
 6713   ins_pipe(empty);
 6714 %}
 6715 
 6716 instruct membar_release()
 6717 %{
 6718   match(MemBarRelease);
 6719   match(StoreFence);
 6720   ins_cost(0);
 6721 
 6722   size(0);
 6723   format %{ "MEMBAR-release ! (empty encoding)" %}
 6724   ins_encode();
 6725   ins_pipe(empty);
 6726 %}
 6727 
 6728 instruct membar_release_lock()
 6729 %{
 6730   match(MemBarReleaseLock);
 6731   ins_cost(0);
 6732 
 6733   size(0);
 6734   format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %}
 6735   ins_encode();
 6736   ins_pipe(empty);
 6737 %}
 6738 
 6739 instruct membar_volatile(rFlagsReg cr) %{
 6740   match(MemBarVolatile);
 6741   effect(KILL cr);
 6742   ins_cost(400);
 6743 
 6744   format %{
 6745     $$template
 6746     $$emit$$"lock addl [rsp + #0], 0\t! membar_volatile"
 6747   %}
 6748   ins_encode %{
 6749     __ membar(Assembler::StoreLoad);
 6750   %}
 6751   ins_pipe(pipe_slow);
 6752 %}
 6753 
 6754 instruct unnecessary_membar_volatile()
 6755 %{
 6756   match(MemBarVolatile);
 6757   predicate(Matcher::post_store_load_barrier(n));
 6758   ins_cost(0);
 6759 
 6760   size(0);
 6761   format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %}
 6762   ins_encode();
 6763   ins_pipe(empty);
 6764 %}
 6765 
 6766 instruct membar_storestore() %{
 6767   match(MemBarStoreStore);
 6768   ins_cost(0);
 6769 
 6770   size(0);
 6771   format %{ "MEMBAR-storestore (empty encoding)" %}
 6772   ins_encode( );
 6773   ins_pipe(empty);
 6774 %}
 6775 
 6776 //----------Move Instructions--------------------------------------------------
 6777 
 6778 instruct castX2P(rRegP dst, rRegL src)
 6779 %{
 6780   match(Set dst (CastX2P src));
 6781 
 6782   format %{ "movq    $dst, $src\t# long->ptr" %}
 6783   ins_encode %{
 6784     if ($dst$$reg != $src$$reg) {
 6785       __ movptr($dst$$Register, $src$$Register);
 6786     }
 6787   %}
 6788   ins_pipe(ialu_reg_reg); // XXX
 6789 %}
 6790 
 6791 instruct castP2X(rRegL dst, rRegP src)
 6792 %{
 6793   match(Set dst (CastP2X src));
 6794 
 6795   format %{ "movq    $dst, $src\t# ptr -> long" %}
 6796   ins_encode %{
 6797     if ($dst$$reg != $src$$reg) {
 6798       __ movptr($dst$$Register, $src$$Register);
 6799     }
 6800   %}
 6801   ins_pipe(ialu_reg_reg); // XXX
 6802 %}
 6803 
 6804 // Convert oop into int for vectors alignment masking
 6805 instruct convP2I(rRegI dst, rRegP src)
 6806 %{
 6807   match(Set dst (ConvL2I (CastP2X src)));
 6808 
 6809   format %{ "movl    $dst, $src\t# ptr -> int" %}
 6810   ins_encode %{
 6811     __ movl($dst$$Register, $src$$Register);
 6812   %}
 6813   ins_pipe(ialu_reg_reg); // XXX
 6814 %}
 6815 
 6816 // Convert compressed oop into int for vectors alignment masking
 6817 // in case of 32bit oops (heap < 4Gb).
 6818 instruct convN2I(rRegI dst, rRegN src)
 6819 %{
 6820   predicate(CompressedOops::shift() == 0);
 6821   match(Set dst (ConvL2I (CastP2X (DecodeN src))));
 6822 
 6823   format %{ "movl    $dst, $src\t# compressed ptr -> int" %}
 6824   ins_encode %{
 6825     __ movl($dst$$Register, $src$$Register);
 6826   %}
 6827   ins_pipe(ialu_reg_reg); // XXX
 6828 %}
 6829 
 6830 // Convert oop pointer into compressed form
 6831 instruct encodeHeapOop(rRegN dst, rRegP src, rFlagsReg cr) %{
 6832   predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
 6833   match(Set dst (EncodeP src));
 6834   effect(KILL cr);
 6835   format %{ "encode_heap_oop $dst,$src" %}
 6836   ins_encode %{
 6837     Register s = $src$$Register;
 6838     Register d = $dst$$Register;
 6839     if (s != d) {
 6840       __ movq(d, s);
 6841     }
 6842     __ encode_heap_oop(d);
 6843   %}
 6844   ins_pipe(ialu_reg_long);
 6845 %}
 6846 
 6847 instruct encodeHeapOop_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{
 6848   predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
 6849   match(Set dst (EncodeP src));
 6850   effect(KILL cr);
 6851   format %{ "encode_heap_oop_not_null $dst,$src" %}
 6852   ins_encode %{
 6853     __ encode_heap_oop_not_null($dst$$Register, $src$$Register);
 6854   %}
 6855   ins_pipe(ialu_reg_long);
 6856 %}
 6857 
 6858 instruct decodeHeapOop(rRegP dst, rRegN src, rFlagsReg cr) %{
 6859   predicate(n->bottom_type()->is_ptr()->ptr() != TypePtr::NotNull &&
 6860             n->bottom_type()->is_ptr()->ptr() != TypePtr::Constant);
 6861   match(Set dst (DecodeN src));
 6862   effect(KILL cr);
 6863   format %{ "decode_heap_oop $dst,$src" %}
 6864   ins_encode %{
 6865     Register s = $src$$Register;
 6866     Register d = $dst$$Register;
 6867     if (s != d) {
 6868       __ movq(d, s);
 6869     }
 6870     __ decode_heap_oop(d);
 6871   %}
 6872   ins_pipe(ialu_reg_long);
 6873 %}
 6874 
 6875 instruct decodeHeapOop_not_null(rRegP dst, rRegN src, rFlagsReg cr) %{
 6876   predicate(n->bottom_type()->is_ptr()->ptr() == TypePtr::NotNull ||
 6877             n->bottom_type()->is_ptr()->ptr() == TypePtr::Constant);
 6878   match(Set dst (DecodeN src));
 6879   effect(KILL cr);
 6880   format %{ "decode_heap_oop_not_null $dst,$src" %}
 6881   ins_encode %{
 6882     Register s = $src$$Register;
 6883     Register d = $dst$$Register;
 6884     if (s != d) {
 6885       __ decode_heap_oop_not_null(d, s);
 6886     } else {
 6887       __ decode_heap_oop_not_null(d);
 6888     }
 6889   %}
 6890   ins_pipe(ialu_reg_long);
 6891 %}
 6892 
 6893 instruct encodeKlass_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{
 6894   match(Set dst (EncodePKlass src));
 6895   effect(TEMP dst, KILL cr);
 6896   format %{ "encode_and_move_klass_not_null $dst,$src" %}
 6897   ins_encode %{
 6898     __ encode_and_move_klass_not_null($dst$$Register, $src$$Register);
 6899   %}
 6900   ins_pipe(ialu_reg_long);
 6901 %}
 6902 
 6903 instruct decodeKlass_not_null(rRegP dst, rRegN src, rFlagsReg cr) %{
 6904   match(Set dst (DecodeNKlass src));
 6905   effect(TEMP dst, KILL cr);
 6906   format %{ "decode_and_move_klass_not_null $dst,$src" %}
 6907   ins_encode %{
 6908     __ decode_and_move_klass_not_null($dst$$Register, $src$$Register);
 6909   %}
 6910   ins_pipe(ialu_reg_long);
 6911 %}
 6912 
 6913 //----------Conditional Move---------------------------------------------------
 6914 // Jump
 6915 // dummy instruction for generating temp registers
 6916 instruct jumpXtnd_offset(rRegL switch_val, immI2 shift, rRegI dest) %{
 6917   match(Jump (LShiftL switch_val shift));
 6918   ins_cost(350);
 6919   predicate(false);
 6920   effect(TEMP dest);
 6921 
 6922   format %{ "leaq    $dest, [$constantaddress]\n\t"
 6923             "jmp     [$dest + $switch_val << $shift]\n\t" %}
 6924   ins_encode %{
 6925     // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
 6926     // to do that and the compiler is using that register as one it can allocate.
 6927     // So we build it all by hand.
 6928     // Address index(noreg, switch_reg, (Address::ScaleFactor)$shift$$constant);
 6929     // ArrayAddress dispatch(table, index);
 6930     Address dispatch($dest$$Register, $switch_val$$Register, (Address::ScaleFactor) $shift$$constant);
 6931     __ lea($dest$$Register, $constantaddress);
 6932     __ jmp(dispatch);
 6933   %}
 6934   ins_pipe(pipe_jmp);
 6935 %}
 6936 
 6937 instruct jumpXtnd_addr(rRegL switch_val, immI2 shift, immL32 offset, rRegI dest) %{
 6938   match(Jump (AddL (LShiftL switch_val shift) offset));
 6939   ins_cost(350);
 6940   effect(TEMP dest);
 6941 
 6942   format %{ "leaq    $dest, [$constantaddress]\n\t"
 6943             "jmp     [$dest + $switch_val << $shift + $offset]\n\t" %}
 6944   ins_encode %{
 6945     // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
 6946     // to do that and the compiler is using that register as one it can allocate.
 6947     // So we build it all by hand.
 6948     // Address index(noreg, switch_reg, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant);
 6949     // ArrayAddress dispatch(table, index);
 6950     Address dispatch($dest$$Register, $switch_val$$Register, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant);
 6951     __ lea($dest$$Register, $constantaddress);
 6952     __ jmp(dispatch);
 6953   %}
 6954   ins_pipe(pipe_jmp);
 6955 %}
 6956 
 6957 instruct jumpXtnd(rRegL switch_val, rRegI dest) %{
 6958   match(Jump switch_val);
 6959   ins_cost(350);
 6960   effect(TEMP dest);
 6961 
 6962   format %{ "leaq    $dest, [$constantaddress]\n\t"
 6963             "jmp     [$dest + $switch_val]\n\t" %}
 6964   ins_encode %{
 6965     // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
 6966     // to do that and the compiler is using that register as one it can allocate.
 6967     // So we build it all by hand.
 6968     // Address index(noreg, switch_reg, Address::times_1);
 6969     // ArrayAddress dispatch(table, index);
 6970     Address dispatch($dest$$Register, $switch_val$$Register, Address::times_1);
 6971     __ lea($dest$$Register, $constantaddress);
 6972     __ jmp(dispatch);
 6973   %}
 6974   ins_pipe(pipe_jmp);
 6975 %}
 6976 
 6977 // Conditional move
 6978 instruct cmovI_reg(rRegI dst, rRegI src, rFlagsReg cr, cmpOp cop)
 6979 %{
 6980   match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
 6981 
 6982   ins_cost(200); // XXX
 6983   format %{ "cmovl$cop $dst, $src\t# signed, int" %}
 6984   ins_encode %{
 6985     __ cmovl((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Register);
 6986   %}
 6987   ins_pipe(pipe_cmov_reg);
 6988 %}
 6989 
 6990 instruct cmovI_regU(cmpOpU cop, rFlagsRegU cr, rRegI dst, rRegI src) %{
 6991   match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
 6992 
 6993   ins_cost(200); // XXX
 6994   format %{ "cmovl$cop $dst, $src\t# unsigned, int" %}
 6995   ins_encode %{
 6996     __ cmovl((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Register);
 6997   %}
 6998   ins_pipe(pipe_cmov_reg);
 6999 %}
 7000 
 7001 instruct cmovI_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, rRegI src) %{
 7002   match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
 7003   ins_cost(200);
 7004   expand %{
 7005     cmovI_regU(cop, cr, dst, src);
 7006   %}
 7007 %}
 7008 
 7009 // Conditional move
 7010 instruct cmovI_mem(cmpOp cop, rFlagsReg cr, rRegI dst, memory src) %{
 7011   match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
 7012 
 7013   ins_cost(250); // XXX
 7014   format %{ "cmovl$cop $dst, $src\t# signed, int" %}
 7015   ins_encode %{
 7016     __ cmovl((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Address);
 7017   %}
 7018   ins_pipe(pipe_cmov_mem);
 7019 %}
 7020 
 7021 // Conditional move
 7022 instruct cmovI_memU(cmpOpU cop, rFlagsRegU cr, rRegI dst, memory src)
 7023 %{
 7024   match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
 7025 
 7026   ins_cost(250); // XXX
 7027   format %{ "cmovl$cop $dst, $src\t# unsigned, int" %}
 7028   ins_encode %{
 7029     __ cmovl((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Address);
 7030   %}
 7031   ins_pipe(pipe_cmov_mem);
 7032 %}
 7033 
 7034 instruct cmovI_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, memory src) %{
 7035   match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
 7036   ins_cost(250);
 7037   expand %{
 7038     cmovI_memU(cop, cr, dst, src);
 7039   %}
 7040 %}
 7041 
 7042 // Conditional move
 7043 instruct cmovN_reg(rRegN dst, rRegN src, rFlagsReg cr, cmpOp cop)
 7044 %{
 7045   match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
 7046 
 7047   ins_cost(200); // XXX
 7048   format %{ "cmovl$cop $dst, $src\t# signed, compressed ptr" %}
 7049   ins_encode %{
 7050     __ cmovl((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Register);
 7051   %}
 7052   ins_pipe(pipe_cmov_reg);
 7053 %}
 7054 
 7055 // Conditional move
 7056 instruct cmovN_regU(cmpOpU cop, rFlagsRegU cr, rRegN dst, rRegN src)
 7057 %{
 7058   match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
 7059 
 7060   ins_cost(200); // XXX
 7061   format %{ "cmovl$cop $dst, $src\t# unsigned, compressed ptr" %}
 7062   ins_encode %{
 7063     __ cmovl((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Register);
 7064   %}
 7065   ins_pipe(pipe_cmov_reg);
 7066 %}
 7067 
 7068 instruct cmovN_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegN dst, rRegN src) %{
 7069   match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
 7070   ins_cost(200);
 7071   expand %{
 7072     cmovN_regU(cop, cr, dst, src);
 7073   %}
 7074 %}
 7075 
 7076 // Conditional move
 7077 instruct cmovP_reg(rRegP dst, rRegP src, rFlagsReg cr, cmpOp cop)
 7078 %{
 7079   match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
 7080 
 7081   ins_cost(200); // XXX
 7082   format %{ "cmovq$cop $dst, $src\t# signed, ptr" %}
 7083   ins_encode %{
 7084     __ cmovq((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Register);
 7085   %}
 7086   ins_pipe(pipe_cmov_reg);  // XXX
 7087 %}
 7088 
 7089 // Conditional move
 7090 instruct cmovP_regU(cmpOpU cop, rFlagsRegU cr, rRegP dst, rRegP src)
 7091 %{
 7092   match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
 7093 
 7094   ins_cost(200); // XXX
 7095   format %{ "cmovq$cop $dst, $src\t# unsigned, ptr" %}
 7096   ins_encode %{
 7097     __ cmovq((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Register);
 7098   %}
 7099   ins_pipe(pipe_cmov_reg); // XXX
 7100 %}
 7101 
 7102 instruct cmovP_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegP dst, rRegP src) %{
 7103   match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
 7104   ins_cost(200);
 7105   expand %{
 7106     cmovP_regU(cop, cr, dst, src);
 7107   %}
 7108 %}
 7109 
 7110 // DISABLED: Requires the ADLC to emit a bottom_type call that
 7111 // correctly meets the two pointer arguments; one is an incoming
 7112 // register but the other is a memory operand.  ALSO appears to
 7113 // be buggy with implicit null checks.
 7114 //
 7115 //// Conditional move
 7116 //instruct cmovP_mem(cmpOp cop, rFlagsReg cr, rRegP dst, memory src)
 7117 //%{
 7118 //  match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
 7119 //  ins_cost(250);
 7120 //  format %{ "CMOV$cop $dst,$src\t# ptr" %}
 7121 //  opcode(0x0F,0x40);
 7122 //  ins_encode( enc_cmov(cop), reg_mem( dst, src ) );
 7123 //  ins_pipe( pipe_cmov_mem );
 7124 //%}
 7125 //
 7126 //// Conditional move
 7127 //instruct cmovP_memU(cmpOpU cop, rFlagsRegU cr, rRegP dst, memory src)
 7128 //%{
 7129 //  match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
 7130 //  ins_cost(250);
 7131 //  format %{ "CMOV$cop $dst,$src\t# ptr" %}
 7132 //  opcode(0x0F,0x40);
 7133 //  ins_encode( enc_cmov(cop), reg_mem( dst, src ) );
 7134 //  ins_pipe( pipe_cmov_mem );
 7135 //%}
 7136 
 7137 instruct cmovL_reg(cmpOp cop, rFlagsReg cr, rRegL dst, rRegL src)
 7138 %{
 7139   match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
 7140 
 7141   ins_cost(200); // XXX
 7142   format %{ "cmovq$cop $dst, $src\t# signed, long" %}
 7143   ins_encode %{
 7144     __ cmovq((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Register);
 7145   %}
 7146   ins_pipe(pipe_cmov_reg);  // XXX
 7147 %}
 7148 
 7149 instruct cmovL_mem(cmpOp cop, rFlagsReg cr, rRegL dst, memory src)
 7150 %{
 7151   match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
 7152 
 7153   ins_cost(200); // XXX
 7154   format %{ "cmovq$cop $dst, $src\t# signed, long" %}
 7155   ins_encode %{
 7156     __ cmovq((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Address);
 7157   %}
 7158   ins_pipe(pipe_cmov_mem);  // XXX
 7159 %}
 7160 
 7161 instruct cmovL_regU(cmpOpU cop, rFlagsRegU cr, rRegL dst, rRegL src)
 7162 %{
 7163   match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
 7164 
 7165   ins_cost(200); // XXX
 7166   format %{ "cmovq$cop $dst, $src\t# unsigned, long" %}
 7167   ins_encode %{
 7168     __ cmovq((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Register);
 7169   %}
 7170   ins_pipe(pipe_cmov_reg); // XXX
 7171 %}
 7172 
 7173 instruct cmovL_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, rRegL src) %{
 7174   match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
 7175   ins_cost(200);
 7176   expand %{
 7177     cmovL_regU(cop, cr, dst, src);
 7178   %}
 7179 %}
 7180 
 7181 instruct cmovL_memU(cmpOpU cop, rFlagsRegU cr, rRegL dst, memory src)
 7182 %{
 7183   match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
 7184 
 7185   ins_cost(200); // XXX
 7186   format %{ "cmovq$cop $dst, $src\t# unsigned, long" %}
 7187   ins_encode %{
 7188     __ cmovq((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Address);
 7189   %}
 7190   ins_pipe(pipe_cmov_mem); // XXX
 7191 %}
 7192 
 7193 instruct cmovL_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, memory src) %{
 7194   match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
 7195   ins_cost(200);
 7196   expand %{
 7197     cmovL_memU(cop, cr, dst, src);
 7198   %}
 7199 %}
 7200 
 7201 instruct cmovF_reg(cmpOp cop, rFlagsReg cr, regF dst, regF src)
 7202 %{
 7203   match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
 7204 
 7205   ins_cost(200); // XXX
 7206   format %{ "jn$cop    skip\t# signed cmove float\n\t"
 7207             "movss     $dst, $src\n"
 7208     "skip:" %}
 7209   ins_encode %{
 7210     Label Lskip;
 7211     // Invert sense of branch from sense of CMOV
 7212     __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
 7213     __ movflt($dst$$XMMRegister, $src$$XMMRegister);
 7214     __ bind(Lskip);
 7215   %}
 7216   ins_pipe(pipe_slow);
 7217 %}
 7218 
 7219 // instruct cmovF_mem(cmpOp cop, rFlagsReg cr, regF dst, memory src)
 7220 // %{
 7221 //   match(Set dst (CMoveF (Binary cop cr) (Binary dst (LoadL src))));
 7222 
 7223 //   ins_cost(200); // XXX
 7224 //   format %{ "jn$cop    skip\t# signed cmove float\n\t"
 7225 //             "movss     $dst, $src\n"
 7226 //     "skip:" %}
 7227 //   ins_encode(enc_cmovf_mem_branch(cop, dst, src));
 7228 //   ins_pipe(pipe_slow);
 7229 // %}
 7230 
 7231 instruct cmovF_regU(cmpOpU cop, rFlagsRegU cr, regF dst, regF src)
 7232 %{
 7233   match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
 7234 
 7235   ins_cost(200); // XXX
 7236   format %{ "jn$cop    skip\t# unsigned cmove float\n\t"
 7237             "movss     $dst, $src\n"
 7238     "skip:" %}
 7239   ins_encode %{
 7240     Label Lskip;
 7241     // Invert sense of branch from sense of CMOV
 7242     __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
 7243     __ movflt($dst$$XMMRegister, $src$$XMMRegister);
 7244     __ bind(Lskip);
 7245   %}
 7246   ins_pipe(pipe_slow);
 7247 %}
 7248 
 7249 instruct cmovF_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regF dst, regF src) %{
 7250   match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
 7251   ins_cost(200);
 7252   expand %{
 7253     cmovF_regU(cop, cr, dst, src);
 7254   %}
 7255 %}
 7256 
 7257 instruct cmovD_reg(cmpOp cop, rFlagsReg cr, regD dst, regD src)
 7258 %{
 7259   match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
 7260 
 7261   ins_cost(200); // XXX
 7262   format %{ "jn$cop    skip\t# signed cmove double\n\t"
 7263             "movsd     $dst, $src\n"
 7264     "skip:" %}
 7265   ins_encode %{
 7266     Label Lskip;
 7267     // Invert sense of branch from sense of CMOV
 7268     __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
 7269     __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
 7270     __ bind(Lskip);
 7271   %}
 7272   ins_pipe(pipe_slow);
 7273 %}
 7274 
 7275 instruct cmovD_regU(cmpOpU cop, rFlagsRegU cr, regD dst, regD src)
 7276 %{
 7277   match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
 7278 
 7279   ins_cost(200); // XXX
 7280   format %{ "jn$cop    skip\t# unsigned cmove double\n\t"
 7281             "movsd     $dst, $src\n"
 7282     "skip:" %}
 7283   ins_encode %{
 7284     Label Lskip;
 7285     // Invert sense of branch from sense of CMOV
 7286     __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
 7287     __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
 7288     __ bind(Lskip);
 7289   %}
 7290   ins_pipe(pipe_slow);
 7291 %}
 7292 
 7293 instruct cmovD_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regD dst, regD src) %{
 7294   match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
 7295   ins_cost(200);
 7296   expand %{
 7297     cmovD_regU(cop, cr, dst, src);
 7298   %}
 7299 %}
 7300 
 7301 //----------Arithmetic Instructions--------------------------------------------
 7302 //----------Addition Instructions----------------------------------------------
 7303 
 7304 instruct addI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
 7305 %{
 7306   match(Set dst (AddI dst src));
 7307   effect(KILL cr);
 7308 
 7309   format %{ "addl    $dst, $src\t# int" %}
 7310   ins_encode %{
 7311     __ addl($dst$$Register, $src$$Register);
 7312   %}
 7313   ins_pipe(ialu_reg_reg);
 7314 %}
 7315 
 7316 instruct addI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
 7317 %{
 7318   match(Set dst (AddI dst src));
 7319   effect(KILL cr);
 7320 
 7321   format %{ "addl    $dst, $src\t# int" %}
 7322   ins_encode %{
 7323     __ addl($dst$$Register, $src$$constant);
 7324   %}
 7325   ins_pipe( ialu_reg );
 7326 %}
 7327 
 7328 instruct addI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
 7329 %{
 7330   match(Set dst (AddI dst (LoadI src)));
 7331   effect(KILL cr);
 7332 
 7333   ins_cost(125); // XXX
 7334   format %{ "addl    $dst, $src\t# int" %}
 7335   ins_encode %{
 7336     __ addl($dst$$Register, $src$$Address);
 7337   %}
 7338   ins_pipe(ialu_reg_mem);
 7339 %}
 7340 
 7341 instruct addI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
 7342 %{
 7343   match(Set dst (StoreI dst (AddI (LoadI dst) src)));
 7344   effect(KILL cr);
 7345 
 7346   ins_cost(150); // XXX
 7347   format %{ "addl    $dst, $src\t# int" %}
 7348   ins_encode %{
 7349     __ addl($dst$$Address, $src$$Register);
 7350   %}
 7351   ins_pipe(ialu_mem_reg);
 7352 %}
 7353 
 7354 instruct addI_mem_imm(memory dst, immI src, rFlagsReg cr)
 7355 %{
 7356   match(Set dst (StoreI dst (AddI (LoadI dst) src)));
 7357   effect(KILL cr);
 7358 
 7359   ins_cost(125); // XXX
 7360   format %{ "addl    $dst, $src\t# int" %}
 7361   ins_encode %{
 7362     __ addl($dst$$Address, $src$$constant);
 7363   %}
 7364   ins_pipe(ialu_mem_imm);
 7365 %}
 7366 
 7367 instruct incI_rReg(rRegI dst, immI_1 src, rFlagsReg cr)
 7368 %{
 7369   predicate(UseIncDec);
 7370   match(Set dst (AddI dst src));
 7371   effect(KILL cr);
 7372 
 7373   format %{ "incl    $dst\t# int" %}
 7374   ins_encode %{
 7375     __ incrementl($dst$$Register);
 7376   %}
 7377   ins_pipe(ialu_reg);
 7378 %}
 7379 
 7380 instruct incI_mem(memory dst, immI_1 src, rFlagsReg cr)
 7381 %{
 7382   predicate(UseIncDec);
 7383   match(Set dst (StoreI dst (AddI (LoadI dst) src)));
 7384   effect(KILL cr);
 7385 
 7386   ins_cost(125); // XXX
 7387   format %{ "incl    $dst\t# int" %}
 7388   ins_encode %{
 7389     __ incrementl($dst$$Address);
 7390   %}
 7391   ins_pipe(ialu_mem_imm);
 7392 %}
 7393 
 7394 // XXX why does that use AddI
 7395 instruct decI_rReg(rRegI dst, immI_M1 src, rFlagsReg cr)
 7396 %{
 7397   predicate(UseIncDec);
 7398   match(Set dst (AddI dst src));
 7399   effect(KILL cr);
 7400 
 7401   format %{ "decl    $dst\t# int" %}
 7402   ins_encode %{
 7403     __ decrementl($dst$$Register);
 7404   %}
 7405   ins_pipe(ialu_reg);
 7406 %}
 7407 
 7408 // XXX why does that use AddI
 7409 instruct decI_mem(memory dst, immI_M1 src, rFlagsReg cr)
 7410 %{
 7411   predicate(UseIncDec);
 7412   match(Set dst (StoreI dst (AddI (LoadI dst) src)));
 7413   effect(KILL cr);
 7414 
 7415   ins_cost(125); // XXX
 7416   format %{ "decl    $dst\t# int" %}
 7417   ins_encode %{
 7418     __ decrementl($dst$$Address);
 7419   %}
 7420   ins_pipe(ialu_mem_imm);
 7421 %}
 7422 
 7423 instruct leaI_rReg_immI(rRegI dst, rRegI src0, immI src1)
 7424 %{
 7425   match(Set dst (AddI src0 src1));
 7426 
 7427   ins_cost(110);
 7428   format %{ "addr32 leal $dst, [$src0 + $src1]\t# int" %}
 7429   ins_encode %{
 7430     __ leal($dst$$Register, Address($src0$$Register, $src1$$constant));
 7431   %}
 7432   ins_pipe(ialu_reg_reg);
 7433 %}
 7434 
 7435 instruct addL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
 7436 %{
 7437   match(Set dst (AddL dst src));
 7438   effect(KILL cr);
 7439 
 7440   format %{ "addq    $dst, $src\t# long" %}
 7441   ins_encode %{
 7442     __ addq($dst$$Register, $src$$Register);
 7443   %}
 7444   ins_pipe(ialu_reg_reg);
 7445 %}
 7446 
 7447 instruct addL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
 7448 %{
 7449   match(Set dst (AddL dst src));
 7450   effect(KILL cr);
 7451 
 7452   format %{ "addq    $dst, $src\t# long" %}
 7453   ins_encode %{
 7454     __ addq($dst$$Register, $src$$constant);
 7455   %}
 7456   ins_pipe( ialu_reg );
 7457 %}
 7458 
 7459 instruct addL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
 7460 %{
 7461   match(Set dst (AddL dst (LoadL src)));
 7462   effect(KILL cr);
 7463 
 7464   ins_cost(125); // XXX
 7465   format %{ "addq    $dst, $src\t# long" %}
 7466   ins_encode %{
 7467     __ addq($dst$$Register, $src$$Address);
 7468   %}
 7469   ins_pipe(ialu_reg_mem);
 7470 %}
 7471 
 7472 instruct addL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
 7473 %{
 7474   match(Set dst (StoreL dst (AddL (LoadL dst) src)));
 7475   effect(KILL cr);
 7476 
 7477   ins_cost(150); // XXX
 7478   format %{ "addq    $dst, $src\t# long" %}
 7479   ins_encode %{
 7480     __ addq($dst$$Address, $src$$Register);
 7481   %}
 7482   ins_pipe(ialu_mem_reg);
 7483 %}
 7484 
 7485 instruct addL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
 7486 %{
 7487   match(Set dst (StoreL dst (AddL (LoadL dst) src)));
 7488   effect(KILL cr);
 7489 
 7490   ins_cost(125); // XXX
 7491   format %{ "addq    $dst, $src\t# long" %}
 7492   ins_encode %{
 7493     __ addq($dst$$Address, $src$$constant);
 7494   %}
 7495   ins_pipe(ialu_mem_imm);
 7496 %}
 7497 
 7498 instruct incL_rReg(rRegI dst, immL1 src, rFlagsReg cr)
 7499 %{
 7500   predicate(UseIncDec);
 7501   match(Set dst (AddL dst src));
 7502   effect(KILL cr);
 7503 
 7504   format %{ "incq    $dst\t# long" %}
 7505   ins_encode %{
 7506     __ incrementq($dst$$Register);
 7507   %}
 7508   ins_pipe(ialu_reg);
 7509 %}
 7510 
 7511 instruct incL_mem(memory dst, immL1 src, rFlagsReg cr)
 7512 %{
 7513   predicate(UseIncDec);
 7514   match(Set dst (StoreL dst (AddL (LoadL dst) src)));
 7515   effect(KILL cr);
 7516 
 7517   ins_cost(125); // XXX
 7518   format %{ "incq    $dst\t# long" %}
 7519   ins_encode %{
 7520     __ incrementq($dst$$Address);
 7521   %}
 7522   ins_pipe(ialu_mem_imm);
 7523 %}
 7524 
 7525 // XXX why does that use AddL
 7526 instruct decL_rReg(rRegL dst, immL_M1 src, rFlagsReg cr)
 7527 %{
 7528   predicate(UseIncDec);
 7529   match(Set dst (AddL dst src));
 7530   effect(KILL cr);
 7531 
 7532   format %{ "decq    $dst\t# long" %}
 7533   ins_encode %{
 7534     __ decrementq($dst$$Register);
 7535   %}
 7536   ins_pipe(ialu_reg);
 7537 %}
 7538 
 7539 // XXX why does that use AddL
 7540 instruct decL_mem(memory dst, immL_M1 src, rFlagsReg cr)
 7541 %{
 7542   predicate(UseIncDec);
 7543   match(Set dst (StoreL dst (AddL (LoadL dst) src)));
 7544   effect(KILL cr);
 7545 
 7546   ins_cost(125); // XXX
 7547   format %{ "decq    $dst\t# long" %}
 7548   ins_encode %{
 7549     __ decrementq($dst$$Address);
 7550   %}
 7551   ins_pipe(ialu_mem_imm);
 7552 %}
 7553 
 7554 instruct leaL_rReg_immL(rRegL dst, rRegL src0, immL32 src1)
 7555 %{
 7556   match(Set dst (AddL src0 src1));
 7557 
 7558   ins_cost(110);
 7559   format %{ "leaq    $dst, [$src0 + $src1]\t# long" %}
 7560   ins_encode %{
 7561     __ leaq($dst$$Register, Address($src0$$Register, $src1$$constant));
 7562   %}
 7563   ins_pipe(ialu_reg_reg);
 7564 %}
 7565 
 7566 instruct addP_rReg(rRegP dst, rRegL src, rFlagsReg cr)
 7567 %{
 7568   match(Set dst (AddP dst src));
 7569   effect(KILL cr);
 7570 
 7571   format %{ "addq    $dst, $src\t# ptr" %}
 7572   ins_encode %{
 7573     __ addq($dst$$Register, $src$$Register);
 7574   %}
 7575   ins_pipe(ialu_reg_reg);
 7576 %}
 7577 
 7578 instruct addP_rReg_imm(rRegP dst, immL32 src, rFlagsReg cr)
 7579 %{
 7580   match(Set dst (AddP dst src));
 7581   effect(KILL cr);
 7582 
 7583   format %{ "addq    $dst, $src\t# ptr" %}
 7584   ins_encode %{
 7585     __ addq($dst$$Register, $src$$constant);
 7586   %}
 7587   ins_pipe( ialu_reg );
 7588 %}
 7589 
 7590 // XXX addP mem ops ????
 7591 
 7592 instruct leaP_rReg_imm(rRegP dst, rRegP src0, immL32 src1)
 7593 %{
 7594   match(Set dst (AddP src0 src1));
 7595 
 7596   ins_cost(110);
 7597   format %{ "leaq    $dst, [$src0 + $src1]\t# ptr" %}
 7598   ins_encode %{
 7599     __ leaq($dst$$Register, Address($src0$$Register, $src1$$constant));
 7600   %}
 7601   ins_pipe(ialu_reg_reg);
 7602 %}
 7603 
 7604 instruct checkCastPP(rRegP dst)
 7605 %{
 7606   match(Set dst (CheckCastPP dst));
 7607 
 7608   size(0);
 7609   format %{ "# checkcastPP of $dst" %}
 7610   ins_encode(/* empty encoding */);
 7611   ins_pipe(empty);
 7612 %}
 7613 
 7614 instruct castPP(rRegP dst)
 7615 %{
 7616   match(Set dst (CastPP dst));
 7617 
 7618   size(0);
 7619   format %{ "# castPP of $dst" %}
 7620   ins_encode(/* empty encoding */);
 7621   ins_pipe(empty);
 7622 %}
 7623 
 7624 instruct castII(rRegI dst)
 7625 %{
 7626   match(Set dst (CastII dst));
 7627 
 7628   size(0);
 7629   format %{ "# castII of $dst" %}
 7630   ins_encode(/* empty encoding */);
 7631   ins_cost(0);
 7632   ins_pipe(empty);
 7633 %}
 7634 
 7635 instruct castLL(rRegL dst)
 7636 %{
 7637   match(Set dst (CastLL dst));
 7638 
 7639   size(0);
 7640   format %{ "# castLL of $dst" %}
 7641   ins_encode(/* empty encoding */);
 7642   ins_cost(0);
 7643   ins_pipe(empty);
 7644 %}
 7645 
 7646 instruct castFF(regF dst)
 7647 %{
 7648   match(Set dst (CastFF dst));
 7649 
 7650   size(0);
 7651   format %{ "# castFF of $dst" %}
 7652   ins_encode(/* empty encoding */);
 7653   ins_cost(0);
 7654   ins_pipe(empty);
 7655 %}
 7656 
 7657 instruct castDD(regD dst)
 7658 %{
 7659   match(Set dst (CastDD dst));
 7660 
 7661   size(0);
 7662   format %{ "# castDD of $dst" %}
 7663   ins_encode(/* empty encoding */);
 7664   ins_cost(0);
 7665   ins_pipe(empty);
 7666 %}
 7667 
 7668 // LoadP-locked same as a regular LoadP when used with compare-swap
 7669 instruct loadPLocked(rRegP dst, memory mem)
 7670 %{
 7671   match(Set dst (LoadPLocked mem));
 7672 
 7673   ins_cost(125); // XXX
 7674   format %{ "movq    $dst, $mem\t# ptr locked" %}
 7675   ins_encode %{
 7676     __ movq($dst$$Register, $mem$$Address);
 7677   %}
 7678   ins_pipe(ialu_reg_mem); // XXX
 7679 %}
 7680 
 7681 // Conditional-store of the updated heap-top.
 7682 // Used during allocation of the shared heap.
 7683 // Sets flags (EQ) on success.  Implemented with a CMPXCHG on Intel.
 7684 
 7685 instruct storePConditional(memory heap_top_ptr,
 7686                            rax_RegP oldval, rRegP newval,
 7687                            rFlagsReg cr)
 7688 %{
 7689   predicate(n->as_LoadStore()->barrier_data() == 0);
 7690   match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval)));
 7691 
 7692   format %{ "cmpxchgq $heap_top_ptr, $newval\t# (ptr) "
 7693             "If rax == $heap_top_ptr then store $newval into $heap_top_ptr" %}
 7694   ins_encode %{
 7695     __ lock();
 7696     __ cmpxchgq($newval$$Register, $heap_top_ptr$$Address);
 7697   %}
 7698   ins_pipe(pipe_cmpxchg);
 7699 %}
 7700 
 7701 // Conditional-store of an int value.
 7702 // ZF flag is set on success, reset otherwise.  Implemented with a CMPXCHG.
 7703 instruct storeIConditional(memory mem, rax_RegI oldval, rRegI newval, rFlagsReg cr)
 7704 %{
 7705   match(Set cr (StoreIConditional mem (Binary oldval newval)));
 7706   effect(KILL oldval);
 7707 
 7708   format %{ "cmpxchgl $mem, $newval\t# If rax == $mem then store $newval into $mem" %}
 7709   opcode(0x0F, 0xB1);
 7710   ins_encode(lock_prefix,
 7711              REX_reg_mem(newval, mem),
 7712              OpcP, OpcS,
 7713              reg_mem(newval, mem));
 7714   ins_pipe(pipe_cmpxchg);
 7715 %}
 7716 
 7717 // Conditional-store of a long value.
 7718 // ZF flag is set on success, reset otherwise.  Implemented with a CMPXCHG.
 7719 instruct storeLConditional(memory mem, rax_RegL oldval, rRegL newval, rFlagsReg cr)
 7720 %{
 7721   match(Set cr (StoreLConditional mem (Binary oldval newval)));
 7722   effect(KILL oldval);
 7723 
 7724   format %{ "cmpxchgq $mem, $newval\t# If rax == $mem then store $newval into $mem" %}
 7725   ins_encode %{
 7726     __ lock();
 7727     __ cmpxchgq($newval$$Register, $mem$$Address);
 7728   %}
 7729   ins_pipe(pipe_cmpxchg);
 7730 %}
 7731 
 7732 
 7733 // XXX No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
 7734 instruct compareAndSwapP(rRegI res,
 7735                          memory mem_ptr,
 7736                          rax_RegP oldval, rRegP newval,
 7737                          rFlagsReg cr)
 7738 %{
 7739   predicate(VM_Version::supports_cx8() && n->as_LoadStore()->barrier_data() == 0);
 7740   match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
 7741   match(Set res (WeakCompareAndSwapP mem_ptr (Binary oldval newval)));
 7742   effect(KILL cr, KILL oldval);
 7743 
 7744   format %{ "cmpxchgq $mem_ptr,$newval\t# "
 7745             "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
 7746             "sete    $res\n\t"
 7747             "movzbl  $res, $res" %}
 7748   ins_encode %{
 7749     __ lock();
 7750     __ cmpxchgq($newval$$Register, $mem_ptr$$Address);
 7751     __ sete($res$$Register);
 7752     __ movzbl($res$$Register, $res$$Register);
 7753   %}
 7754   ins_pipe( pipe_cmpxchg );
 7755 %}
 7756 
 7757 instruct compareAndSwapL(rRegI res,
 7758                          memory mem_ptr,
 7759                          rax_RegL oldval, rRegL newval,
 7760                          rFlagsReg cr)
 7761 %{
 7762   predicate(VM_Version::supports_cx8());
 7763   match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
 7764   match(Set res (WeakCompareAndSwapL mem_ptr (Binary oldval newval)));
 7765   effect(KILL cr, KILL oldval);
 7766 
 7767   format %{ "cmpxchgq $mem_ptr,$newval\t# "
 7768             "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
 7769             "sete    $res\n\t"
 7770             "movzbl  $res, $res" %}
 7771   ins_encode %{
 7772     __ lock();
 7773     __ cmpxchgq($newval$$Register, $mem_ptr$$Address);
 7774     __ sete($res$$Register);
 7775     __ movzbl($res$$Register, $res$$Register);
 7776   %}
 7777   ins_pipe( pipe_cmpxchg );
 7778 %}
 7779 
 7780 instruct compareAndSwapI(rRegI res,
 7781                          memory mem_ptr,
 7782                          rax_RegI oldval, rRegI newval,
 7783                          rFlagsReg cr)
 7784 %{
 7785   match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
 7786   match(Set res (WeakCompareAndSwapI mem_ptr (Binary oldval newval)));
 7787   effect(KILL cr, KILL oldval);
 7788 
 7789   format %{ "cmpxchgl $mem_ptr,$newval\t# "
 7790             "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
 7791             "sete    $res\n\t"
 7792             "movzbl  $res, $res" %}
 7793   ins_encode %{
 7794     __ lock();
 7795     __ cmpxchgl($newval$$Register, $mem_ptr$$Address);
 7796     __ sete($res$$Register);
 7797     __ movzbl($res$$Register, $res$$Register);
 7798   %}
 7799   ins_pipe( pipe_cmpxchg );
 7800 %}
 7801 
 7802 instruct compareAndSwapB(rRegI res,
 7803                          memory mem_ptr,
 7804                          rax_RegI oldval, rRegI newval,
 7805                          rFlagsReg cr)
 7806 %{
 7807   match(Set res (CompareAndSwapB mem_ptr (Binary oldval newval)));
 7808   match(Set res (WeakCompareAndSwapB mem_ptr (Binary oldval newval)));
 7809   effect(KILL cr, KILL oldval);
 7810 
 7811   format %{ "cmpxchgb $mem_ptr,$newval\t# "
 7812             "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
 7813             "sete    $res\n\t"
 7814             "movzbl  $res, $res" %}
 7815   ins_encode %{
 7816     __ lock();
 7817     __ cmpxchgb($newval$$Register, $mem_ptr$$Address);
 7818     __ sete($res$$Register);
 7819     __ movzbl($res$$Register, $res$$Register);
 7820   %}
 7821   ins_pipe( pipe_cmpxchg );
 7822 %}
 7823 
 7824 instruct compareAndSwapS(rRegI res,
 7825                          memory mem_ptr,
 7826                          rax_RegI oldval, rRegI newval,
 7827                          rFlagsReg cr)
 7828 %{
 7829   match(Set res (CompareAndSwapS mem_ptr (Binary oldval newval)));
 7830   match(Set res (WeakCompareAndSwapS mem_ptr (Binary oldval newval)));
 7831   effect(KILL cr, KILL oldval);
 7832 
 7833   format %{ "cmpxchgw $mem_ptr,$newval\t# "
 7834             "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
 7835             "sete    $res\n\t"
 7836             "movzbl  $res, $res" %}
 7837   ins_encode %{
 7838     __ lock();
 7839     __ cmpxchgw($newval$$Register, $mem_ptr$$Address);
 7840     __ sete($res$$Register);
 7841     __ movzbl($res$$Register, $res$$Register);
 7842   %}
 7843   ins_pipe( pipe_cmpxchg );
 7844 %}
 7845 
 7846 instruct compareAndSwapN(rRegI res,
 7847                           memory mem_ptr,
 7848                           rax_RegN oldval, rRegN newval,
 7849                           rFlagsReg cr) %{
 7850   match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
 7851   match(Set res (WeakCompareAndSwapN mem_ptr (Binary oldval newval)));
 7852   effect(KILL cr, KILL oldval);
 7853 
 7854   format %{ "cmpxchgl $mem_ptr,$newval\t# "
 7855             "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
 7856             "sete    $res\n\t"
 7857             "movzbl  $res, $res" %}
 7858   ins_encode %{
 7859     __ lock();
 7860     __ cmpxchgl($newval$$Register, $mem_ptr$$Address);
 7861     __ sete($res$$Register);
 7862     __ movzbl($res$$Register, $res$$Register);
 7863   %}
 7864   ins_pipe( pipe_cmpxchg );
 7865 %}
 7866 
 7867 instruct compareAndExchangeB(
 7868                          memory mem_ptr,
 7869                          rax_RegI oldval, rRegI newval,
 7870                          rFlagsReg cr)
 7871 %{
 7872   match(Set oldval (CompareAndExchangeB mem_ptr (Binary oldval newval)));
 7873   effect(KILL cr);
 7874 
 7875   format %{ "cmpxchgb $mem_ptr,$newval\t# "
 7876             "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"  %}
 7877   ins_encode %{
 7878     __ lock();
 7879     __ cmpxchgb($newval$$Register, $mem_ptr$$Address);
 7880   %}
 7881   ins_pipe( pipe_cmpxchg );
 7882 %}
 7883 
 7884 instruct compareAndExchangeS(
 7885                          memory mem_ptr,
 7886                          rax_RegI oldval, rRegI newval,
 7887                          rFlagsReg cr)
 7888 %{
 7889   match(Set oldval (CompareAndExchangeS mem_ptr (Binary oldval newval)));
 7890   effect(KILL cr);
 7891 
 7892   format %{ "cmpxchgw $mem_ptr,$newval\t# "
 7893             "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"  %}
 7894   ins_encode %{
 7895     __ lock();
 7896     __ cmpxchgw($newval$$Register, $mem_ptr$$Address);
 7897   %}
 7898   ins_pipe( pipe_cmpxchg );
 7899 %}
 7900 
 7901 instruct compareAndExchangeI(
 7902                          memory mem_ptr,
 7903                          rax_RegI oldval, rRegI newval,
 7904                          rFlagsReg cr)
 7905 %{
 7906   match(Set oldval (CompareAndExchangeI mem_ptr (Binary oldval newval)));
 7907   effect(KILL cr);
 7908 
 7909   format %{ "cmpxchgl $mem_ptr,$newval\t# "
 7910             "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"  %}
 7911   ins_encode %{
 7912     __ lock();
 7913     __ cmpxchgl($newval$$Register, $mem_ptr$$Address);
 7914   %}
 7915   ins_pipe( pipe_cmpxchg );
 7916 %}
 7917 
 7918 instruct compareAndExchangeL(
 7919                          memory mem_ptr,
 7920                          rax_RegL oldval, rRegL newval,
 7921                          rFlagsReg cr)
 7922 %{
 7923   predicate(VM_Version::supports_cx8());
 7924   match(Set oldval (CompareAndExchangeL mem_ptr (Binary oldval newval)));
 7925   effect(KILL cr);
 7926 
 7927   format %{ "cmpxchgq $mem_ptr,$newval\t# "
 7928             "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"  %}
 7929   ins_encode %{
 7930     __ lock();
 7931     __ cmpxchgq($newval$$Register, $mem_ptr$$Address);
 7932   %}
 7933   ins_pipe( pipe_cmpxchg );
 7934 %}
 7935 
 7936 instruct compareAndExchangeN(
 7937                           memory mem_ptr,
 7938                           rax_RegN oldval, rRegN newval,
 7939                           rFlagsReg cr) %{
 7940   match(Set oldval (CompareAndExchangeN mem_ptr (Binary oldval newval)));
 7941   effect(KILL cr);
 7942 
 7943   format %{ "cmpxchgl $mem_ptr,$newval\t# "
 7944             "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
 7945   ins_encode %{
 7946     __ lock();
 7947     __ cmpxchgl($newval$$Register, $mem_ptr$$Address);
 7948   %}
 7949   ins_pipe( pipe_cmpxchg );
 7950 %}
 7951 
 7952 instruct compareAndExchangeP(
 7953                          memory mem_ptr,
 7954                          rax_RegP oldval, rRegP newval,
 7955                          rFlagsReg cr)
 7956 %{
 7957   predicate(VM_Version::supports_cx8() && n->as_LoadStore()->barrier_data() == 0);
 7958   match(Set oldval (CompareAndExchangeP mem_ptr (Binary oldval newval)));
 7959   effect(KILL cr);
 7960 
 7961   format %{ "cmpxchgq $mem_ptr,$newval\t# "
 7962             "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
 7963   ins_encode %{
 7964     __ lock();
 7965     __ cmpxchgq($newval$$Register, $mem_ptr$$Address);
 7966   %}
 7967   ins_pipe( pipe_cmpxchg );
 7968 %}
 7969 
 7970 instruct xaddB_no_res( memory mem, Universe dummy, immI add, rFlagsReg cr) %{
 7971   predicate(n->as_LoadStore()->result_not_used());
 7972   match(Set dummy (GetAndAddB mem add));
 7973   effect(KILL cr);
 7974   format %{ "ADDB  [$mem],$add" %}
 7975   ins_encode %{
 7976     __ lock();
 7977     __ addb($mem$$Address, $add$$constant);
 7978   %}
 7979   ins_pipe( pipe_cmpxchg );
 7980 %}
 7981 
 7982 instruct xaddB( memory mem, rRegI newval, rFlagsReg cr) %{
 7983   match(Set newval (GetAndAddB mem newval));
 7984   effect(KILL cr);
 7985   format %{ "XADDB  [$mem],$newval" %}
 7986   ins_encode %{
 7987     __ lock();
 7988     __ xaddb($mem$$Address, $newval$$Register);
 7989   %}
 7990   ins_pipe( pipe_cmpxchg );
 7991 %}
 7992 
 7993 instruct xaddS_no_res( memory mem, Universe dummy, immI add, rFlagsReg cr) %{
 7994   predicate(n->as_LoadStore()->result_not_used());
 7995   match(Set dummy (GetAndAddS mem add));
 7996   effect(KILL cr);
 7997   format %{ "ADDW  [$mem],$add" %}
 7998   ins_encode %{
 7999     __ lock();
 8000     __ addw($mem$$Address, $add$$constant);
 8001   %}
 8002   ins_pipe( pipe_cmpxchg );
 8003 %}
 8004 
 8005 instruct xaddS( memory mem, rRegI newval, rFlagsReg cr) %{
 8006   match(Set newval (GetAndAddS mem newval));
 8007   effect(KILL cr);
 8008   format %{ "XADDW  [$mem],$newval" %}
 8009   ins_encode %{
 8010     __ lock();
 8011     __ xaddw($mem$$Address, $newval$$Register);
 8012   %}
 8013   ins_pipe( pipe_cmpxchg );
 8014 %}
 8015 
 8016 instruct xaddI_no_res( memory mem, Universe dummy, immI add, rFlagsReg cr) %{
 8017   predicate(n->as_LoadStore()->result_not_used());
 8018   match(Set dummy (GetAndAddI mem add));
 8019   effect(KILL cr);
 8020   format %{ "ADDL  [$mem],$add" %}
 8021   ins_encode %{
 8022     __ lock();
 8023     __ addl($mem$$Address, $add$$constant);
 8024   %}
 8025   ins_pipe( pipe_cmpxchg );
 8026 %}
 8027 
 8028 instruct xaddI( memory mem, rRegI newval, rFlagsReg cr) %{
 8029   match(Set newval (GetAndAddI mem newval));
 8030   effect(KILL cr);
 8031   format %{ "XADDL  [$mem],$newval" %}
 8032   ins_encode %{
 8033     __ lock();
 8034     __ xaddl($mem$$Address, $newval$$Register);
 8035   %}
 8036   ins_pipe( pipe_cmpxchg );
 8037 %}
 8038 
 8039 instruct xaddL_no_res( memory mem, Universe dummy, immL32 add, rFlagsReg cr) %{
 8040   predicate(n->as_LoadStore()->result_not_used());
 8041   match(Set dummy (GetAndAddL mem add));
 8042   effect(KILL cr);
 8043   format %{ "ADDQ  [$mem],$add" %}
 8044   ins_encode %{
 8045     __ lock();
 8046     __ addq($mem$$Address, $add$$constant);
 8047   %}
 8048   ins_pipe( pipe_cmpxchg );
 8049 %}
 8050 
 8051 instruct xaddL( memory mem, rRegL newval, rFlagsReg cr) %{
 8052   match(Set newval (GetAndAddL mem newval));
 8053   effect(KILL cr);
 8054   format %{ "XADDQ  [$mem],$newval" %}
 8055   ins_encode %{
 8056     __ lock();
 8057     __ xaddq($mem$$Address, $newval$$Register);
 8058   %}
 8059   ins_pipe( pipe_cmpxchg );
 8060 %}
 8061 
 8062 instruct xchgB( memory mem, rRegI newval) %{
 8063   match(Set newval (GetAndSetB mem newval));
 8064   format %{ "XCHGB  $newval,[$mem]" %}
 8065   ins_encode %{
 8066     __ xchgb($newval$$Register, $mem$$Address);
 8067   %}
 8068   ins_pipe( pipe_cmpxchg );
 8069 %}
 8070 
 8071 instruct xchgS( memory mem, rRegI newval) %{
 8072   match(Set newval (GetAndSetS mem newval));
 8073   format %{ "XCHGW  $newval,[$mem]" %}
 8074   ins_encode %{
 8075     __ xchgw($newval$$Register, $mem$$Address);
 8076   %}
 8077   ins_pipe( pipe_cmpxchg );
 8078 %}
 8079 
 8080 instruct xchgI( memory mem, rRegI newval) %{
 8081   match(Set newval (GetAndSetI mem newval));
 8082   format %{ "XCHGL  $newval,[$mem]" %}
 8083   ins_encode %{
 8084     __ xchgl($newval$$Register, $mem$$Address);
 8085   %}
 8086   ins_pipe( pipe_cmpxchg );
 8087 %}
 8088 
 8089 instruct xchgL( memory mem, rRegL newval) %{
 8090   match(Set newval (GetAndSetL mem newval));
 8091   format %{ "XCHGL  $newval,[$mem]" %}
 8092   ins_encode %{
 8093     __ xchgq($newval$$Register, $mem$$Address);
 8094   %}
 8095   ins_pipe( pipe_cmpxchg );
 8096 %}
 8097 
 8098 instruct xchgP( memory mem, rRegP newval) %{
 8099   match(Set newval (GetAndSetP mem newval));
 8100   predicate(n->as_LoadStore()->barrier_data() == 0);
 8101   format %{ "XCHGQ  $newval,[$mem]" %}
 8102   ins_encode %{
 8103     __ xchgq($newval$$Register, $mem$$Address);
 8104   %}
 8105   ins_pipe( pipe_cmpxchg );
 8106 %}
 8107 
 8108 instruct xchgN( memory mem, rRegN newval) %{
 8109   match(Set newval (GetAndSetN mem newval));
 8110   format %{ "XCHGL  $newval,$mem]" %}
 8111   ins_encode %{
 8112     __ xchgl($newval$$Register, $mem$$Address);
 8113   %}
 8114   ins_pipe( pipe_cmpxchg );
 8115 %}
 8116 
 8117 //----------Abs Instructions-------------------------------------------
 8118 
 8119 // Integer Absolute Instructions
 8120 instruct absI_rReg(rRegI dst, rRegI src, rRegI tmp, rFlagsReg cr)
 8121 %{
 8122   match(Set dst (AbsI src));
 8123   effect(TEMP dst, TEMP tmp, KILL cr);
 8124   format %{ "movl $tmp, $src\n\t"
 8125             "sarl $tmp, 31\n\t"
 8126             "movl $dst, $src\n\t"
 8127             "xorl $dst, $tmp\n\t"
 8128             "subl $dst, $tmp\n"
 8129           %}
 8130   ins_encode %{
 8131     __ movl($tmp$$Register, $src$$Register);
 8132     __ sarl($tmp$$Register, 31);
 8133     __ movl($dst$$Register, $src$$Register);
 8134     __ xorl($dst$$Register, $tmp$$Register);
 8135     __ subl($dst$$Register, $tmp$$Register);
 8136   %}
 8137 
 8138   ins_pipe(ialu_reg_reg);
 8139 %}
 8140 
 8141 // Long Absolute Instructions
 8142 instruct absL_rReg(rRegL dst, rRegL src, rRegL tmp, rFlagsReg cr)
 8143 %{
 8144   match(Set dst (AbsL src));
 8145   effect(TEMP dst, TEMP tmp, KILL cr);
 8146   format %{ "movq $tmp, $src\n\t"
 8147             "sarq $tmp, 63\n\t"
 8148             "movq $dst, $src\n\t"
 8149             "xorq $dst, $tmp\n\t"
 8150             "subq $dst, $tmp\n"
 8151           %}
 8152   ins_encode %{
 8153     __ movq($tmp$$Register, $src$$Register);
 8154     __ sarq($tmp$$Register, 63);
 8155     __ movq($dst$$Register, $src$$Register);
 8156     __ xorq($dst$$Register, $tmp$$Register);
 8157     __ subq($dst$$Register, $tmp$$Register);
 8158   %}
 8159 
 8160   ins_pipe(ialu_reg_reg);
 8161 %}
 8162 
 8163 //----------Subtraction Instructions-------------------------------------------
 8164 
 8165 // Integer Subtraction Instructions
 8166 instruct subI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
 8167 %{
 8168   match(Set dst (SubI dst src));
 8169   effect(KILL cr);
 8170 
 8171   format %{ "subl    $dst, $src\t# int" %}
 8172   ins_encode %{
 8173     __ subl($dst$$Register, $src$$Register);
 8174   %}
 8175   ins_pipe(ialu_reg_reg);
 8176 %}
 8177 
 8178 instruct subI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
 8179 %{
 8180   match(Set dst (SubI dst src));
 8181   effect(KILL cr);
 8182 
 8183   format %{ "subl    $dst, $src\t# int" %}
 8184   ins_encode %{
 8185     __ subl($dst$$Register, $src$$constant);
 8186   %}
 8187   ins_pipe(ialu_reg);
 8188 %}
 8189 
 8190 instruct subI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
 8191 %{
 8192   match(Set dst (SubI dst (LoadI src)));
 8193   effect(KILL cr);
 8194 
 8195   ins_cost(125);
 8196   format %{ "subl    $dst, $src\t# int" %}
 8197   ins_encode %{
 8198     __ subl($dst$$Register, $src$$Address);
 8199   %}
 8200   ins_pipe(ialu_reg_mem);
 8201 %}
 8202 
 8203 instruct subI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
 8204 %{
 8205   match(Set dst (StoreI dst (SubI (LoadI dst) src)));
 8206   effect(KILL cr);
 8207 
 8208   ins_cost(150);
 8209   format %{ "subl    $dst, $src\t# int" %}
 8210   ins_encode %{
 8211     __ subl($dst$$Address, $src$$Register);
 8212   %}
 8213   ins_pipe(ialu_mem_reg);
 8214 %}
 8215 
 8216 instruct subI_mem_imm(memory dst, immI src, rFlagsReg cr)
 8217 %{
 8218   match(Set dst (StoreI dst (SubI (LoadI dst) src)));
 8219   effect(KILL cr);
 8220 
 8221   ins_cost(125); // XXX
 8222   format %{ "subl    $dst, $src\t# int" %}
 8223   ins_encode %{
 8224     __ subl($dst$$Address, $src$$constant);
 8225   %}
 8226   ins_pipe(ialu_mem_imm);
 8227 %}
 8228 
 8229 instruct subL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
 8230 %{
 8231   match(Set dst (SubL dst src));
 8232   effect(KILL cr);
 8233 
 8234   format %{ "subq    $dst, $src\t# long" %}
 8235   ins_encode %{
 8236     __ subq($dst$$Register, $src$$Register);
 8237   %}
 8238   ins_pipe(ialu_reg_reg);
 8239 %}
 8240 
 8241 instruct subL_rReg_imm(rRegI dst, immL32 src, rFlagsReg cr)
 8242 %{
 8243   match(Set dst (SubL dst src));
 8244   effect(KILL cr);
 8245 
 8246   format %{ "subq    $dst, $src\t# long" %}
 8247   ins_encode %{
 8248     __ subq($dst$$Register, $src$$constant);
 8249   %}
 8250   ins_pipe(ialu_reg);
 8251 %}
 8252 
 8253 instruct subL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
 8254 %{
 8255   match(Set dst (SubL dst (LoadL src)));
 8256   effect(KILL cr);
 8257 
 8258   ins_cost(125);
 8259   format %{ "subq    $dst, $src\t# long" %}
 8260   ins_encode %{
 8261     __ subq($dst$$Register, $src$$Address);
 8262   %}
 8263   ins_pipe(ialu_reg_mem);
 8264 %}
 8265 
 8266 instruct subL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
 8267 %{
 8268   match(Set dst (StoreL dst (SubL (LoadL dst) src)));
 8269   effect(KILL cr);
 8270 
 8271   ins_cost(150);
 8272   format %{ "subq    $dst, $src\t# long" %}
 8273   ins_encode %{
 8274     __ subq($dst$$Address, $src$$Register);
 8275   %}
 8276   ins_pipe(ialu_mem_reg);
 8277 %}
 8278 
 8279 instruct subL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
 8280 %{
 8281   match(Set dst (StoreL dst (SubL (LoadL dst) src)));
 8282   effect(KILL cr);
 8283 
 8284   ins_cost(125); // XXX
 8285   format %{ "subq    $dst, $src\t# long" %}
 8286   ins_encode %{
 8287     __ subq($dst$$Address, $src$$constant);
 8288   %}
 8289   ins_pipe(ialu_mem_imm);
 8290 %}
 8291 
 8292 // Subtract from a pointer
 8293 // XXX hmpf???
 8294 instruct subP_rReg(rRegP dst, rRegI src, immI_0 zero, rFlagsReg cr)
 8295 %{
 8296   match(Set dst (AddP dst (SubI zero src)));
 8297   effect(KILL cr);
 8298 
 8299   format %{ "subq    $dst, $src\t# ptr - int" %}
 8300   opcode(0x2B);
 8301   ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
 8302   ins_pipe(ialu_reg_reg);
 8303 %}
 8304 
 8305 instruct negI_rReg(rRegI dst, immI_0 zero, rFlagsReg cr)
 8306 %{
 8307   match(Set dst (SubI zero dst));
 8308   effect(KILL cr);
 8309 
 8310   format %{ "negl    $dst\t# int" %}
 8311   ins_encode %{
 8312     __ negl($dst$$Register);
 8313   %}
 8314   ins_pipe(ialu_reg);
 8315 %}
 8316 
 8317 instruct negI_rReg_2(rRegI dst, rFlagsReg cr)
 8318 %{
 8319   match(Set dst (NegI dst));
 8320   effect(KILL cr);
 8321 
 8322   format %{ "negl    $dst\t# int" %}
 8323   ins_encode %{
 8324     __ negl($dst$$Register);
 8325   %}
 8326   ins_pipe(ialu_reg);
 8327 %}
 8328 
 8329 instruct negI_mem(memory dst, immI_0 zero, rFlagsReg cr)
 8330 %{
 8331   match(Set dst (StoreI dst (SubI zero (LoadI dst))));
 8332   effect(KILL cr);
 8333 
 8334   format %{ "negl    $dst\t# int" %}
 8335   ins_encode %{
 8336     __ negl($dst$$Address);
 8337   %}
 8338   ins_pipe(ialu_reg);
 8339 %}
 8340 
 8341 instruct negL_rReg(rRegL dst, immL0 zero, rFlagsReg cr)
 8342 %{
 8343   match(Set dst (SubL zero dst));
 8344   effect(KILL cr);
 8345 
 8346   format %{ "negq    $dst\t# long" %}
 8347   ins_encode %{
 8348     __ negq($dst$$Register);
 8349   %}
 8350   ins_pipe(ialu_reg);
 8351 %}
 8352 
 8353 instruct negL_rReg_2(rRegL dst, rFlagsReg cr)
 8354 %{
 8355   match(Set dst (NegL dst));
 8356   effect(KILL cr);
 8357 
 8358   format %{ "negq    $dst\t# int" %}
 8359   ins_encode %{
 8360     __ negq($dst$$Register);
 8361   %}
 8362   ins_pipe(ialu_reg);
 8363 %}
 8364 
 8365 instruct negL_mem(memory dst, immL0 zero, rFlagsReg cr)
 8366 %{
 8367   match(Set dst (StoreL dst (SubL zero (LoadL dst))));
 8368   effect(KILL cr);
 8369 
 8370   format %{ "negq    $dst\t# long" %}
 8371   ins_encode %{
 8372     __ negq($dst$$Address);
 8373   %}
 8374   ins_pipe(ialu_reg);
 8375 %}
 8376 
 8377 //----------Multiplication/Division Instructions-------------------------------
 8378 // Integer Multiplication Instructions
 8379 // Multiply Register
 8380 
 8381 instruct mulI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
 8382 %{
 8383   match(Set dst (MulI dst src));
 8384   effect(KILL cr);
 8385 
 8386   ins_cost(300);
 8387   format %{ "imull   $dst, $src\t# int" %}
 8388   ins_encode %{
 8389     __ imull($dst$$Register, $src$$Register);
 8390   %}
 8391   ins_pipe(ialu_reg_reg_alu0);
 8392 %}
 8393 
 8394 instruct mulI_rReg_imm(rRegI dst, rRegI src, immI imm, rFlagsReg cr)
 8395 %{
 8396   match(Set dst (MulI src imm));
 8397   effect(KILL cr);
 8398 
 8399   ins_cost(300);
 8400   format %{ "imull   $dst, $src, $imm\t# int" %}
 8401   ins_encode %{
 8402     __ imull($dst$$Register, $src$$Register, $imm$$constant);
 8403   %}
 8404   ins_pipe(ialu_reg_reg_alu0);
 8405 %}
 8406 
 8407 instruct mulI_mem(rRegI dst, memory src, rFlagsReg cr)
 8408 %{
 8409   match(Set dst (MulI dst (LoadI src)));
 8410   effect(KILL cr);
 8411 
 8412   ins_cost(350);
 8413   format %{ "imull   $dst, $src\t# int" %}
 8414   ins_encode %{
 8415     __ imull($dst$$Register, $src$$Address);
 8416   %}
 8417   ins_pipe(ialu_reg_mem_alu0);
 8418 %}
 8419 
 8420 instruct mulI_mem_imm(rRegI dst, memory src, immI imm, rFlagsReg cr)
 8421 %{
 8422   match(Set dst (MulI (LoadI src) imm));
 8423   effect(KILL cr);
 8424 
 8425   ins_cost(300);
 8426   format %{ "imull   $dst, $src, $imm\t# int" %}
 8427   ins_encode %{
 8428     __ imull($dst$$Register, $src$$Address, $imm$$constant);
 8429   %}
 8430   ins_pipe(ialu_reg_mem_alu0);
 8431 %}
 8432 
 8433 instruct mulAddS2I_rReg(rRegI dst, rRegI src1, rRegI src2, rRegI src3, rFlagsReg cr)
 8434 %{
 8435   match(Set dst (MulAddS2I (Binary dst src1) (Binary src2 src3)));
 8436   effect(KILL cr, KILL src2);
 8437 
 8438   expand %{ mulI_rReg(dst, src1, cr);
 8439            mulI_rReg(src2, src3, cr);
 8440            addI_rReg(dst, src2, cr); %}
 8441 %}
 8442 
 8443 instruct mulL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
 8444 %{
 8445   match(Set dst (MulL dst src));
 8446   effect(KILL cr);
 8447 
 8448   ins_cost(300);
 8449   format %{ "imulq   $dst, $src\t# long" %}
 8450   ins_encode %{
 8451     __ imulq($dst$$Register, $src$$Register);
 8452   %}
 8453   ins_pipe(ialu_reg_reg_alu0);
 8454 %}
 8455 
 8456 instruct mulL_rReg_imm(rRegL dst, rRegL src, immL32 imm, rFlagsReg cr)
 8457 %{
 8458   match(Set dst (MulL src imm));
 8459   effect(KILL cr);
 8460 
 8461   ins_cost(300);
 8462   format %{ "imulq   $dst, $src, $imm\t# long" %}
 8463   ins_encode %{
 8464     __ imulq($dst$$Register, $src$$Register, $imm$$constant);
 8465   %}
 8466   ins_pipe(ialu_reg_reg_alu0);
 8467 %}
 8468 
 8469 instruct mulL_mem(rRegL dst, memory src, rFlagsReg cr)
 8470 %{
 8471   match(Set dst (MulL dst (LoadL src)));
 8472   effect(KILL cr);
 8473 
 8474   ins_cost(350);
 8475   format %{ "imulq   $dst, $src\t# long" %}
 8476   ins_encode %{
 8477     __ imulq($dst$$Register, $src$$Address);
 8478   %}
 8479   ins_pipe(ialu_reg_mem_alu0);
 8480 %}
 8481 
 8482 instruct mulL_mem_imm(rRegL dst, memory src, immL32 imm, rFlagsReg cr)
 8483 %{
 8484   match(Set dst (MulL (LoadL src) imm));
 8485   effect(KILL cr);
 8486 
 8487   ins_cost(300);
 8488   format %{ "imulq   $dst, $src, $imm\t# long" %}
 8489   ins_encode %{
 8490     __ imulq($dst$$Register, $src$$Address, $imm$$constant);
 8491   %}
 8492   ins_pipe(ialu_reg_mem_alu0);
 8493 %}
 8494 
 8495 instruct mulHiL_rReg(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr)
 8496 %{
 8497   match(Set dst (MulHiL src rax));
 8498   effect(USE_KILL rax, KILL cr);
 8499 
 8500   ins_cost(300);
 8501   format %{ "imulq   RDX:RAX, RAX, $src\t# mulhi" %}
 8502   ins_encode %{
 8503     __ imulq($src$$Register);
 8504   %}
 8505   ins_pipe(ialu_reg_reg_alu0);
 8506 %}
 8507 
 8508 instruct divI_rReg(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
 8509                    rFlagsReg cr)
 8510 %{
 8511   match(Set rax (DivI rax div));
 8512   effect(KILL rdx, KILL cr);
 8513 
 8514   ins_cost(30*100+10*100); // XXX
 8515   format %{ "cmpl    rax, 0x80000000\t# idiv\n\t"
 8516             "jne,s   normal\n\t"
 8517             "xorl    rdx, rdx\n\t"
 8518             "cmpl    $div, -1\n\t"
 8519             "je,s    done\n"
 8520     "normal: cdql\n\t"
 8521             "idivl   $div\n"
 8522     "done:"        %}
 8523   ins_encode(cdql_enc(div));
 8524   ins_pipe(ialu_reg_reg_alu0);
 8525 %}
 8526 
 8527 instruct divL_rReg(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div,
 8528                    rFlagsReg cr)
 8529 %{
 8530   match(Set rax (DivL rax div));
 8531   effect(KILL rdx, KILL cr);
 8532 
 8533   ins_cost(30*100+10*100); // XXX
 8534   format %{ "movq    rdx, 0x8000000000000000\t# ldiv\n\t"
 8535             "cmpq    rax, rdx\n\t"
 8536             "jne,s   normal\n\t"
 8537             "xorl    rdx, rdx\n\t"
 8538             "cmpq    $div, -1\n\t"
 8539             "je,s    done\n"
 8540     "normal: cdqq\n\t"
 8541             "idivq   $div\n"
 8542     "done:"        %}
 8543   ins_encode(cdqq_enc(div));
 8544   ins_pipe(ialu_reg_reg_alu0);
 8545 %}
 8546 
 8547 // Integer DIVMOD with Register, both quotient and mod results
 8548 instruct divModI_rReg_divmod(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
 8549                              rFlagsReg cr)
 8550 %{
 8551   match(DivModI rax div);
 8552   effect(KILL cr);
 8553 
 8554   ins_cost(30*100+10*100); // XXX
 8555   format %{ "cmpl    rax, 0x80000000\t# idiv\n\t"
 8556             "jne,s   normal\n\t"
 8557             "xorl    rdx, rdx\n\t"
 8558             "cmpl    $div, -1\n\t"
 8559             "je,s    done\n"
 8560     "normal: cdql\n\t"
 8561             "idivl   $div\n"
 8562     "done:"        %}
 8563   ins_encode(cdql_enc(div));
 8564   ins_pipe(pipe_slow);
 8565 %}
 8566 
 8567 // Long DIVMOD with Register, both quotient and mod results
 8568 instruct divModL_rReg_divmod(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div,
 8569                              rFlagsReg cr)
 8570 %{
 8571   match(DivModL rax div);
 8572   effect(KILL cr);
 8573 
 8574   ins_cost(30*100+10*100); // XXX
 8575   format %{ "movq    rdx, 0x8000000000000000\t# ldiv\n\t"
 8576             "cmpq    rax, rdx\n\t"
 8577             "jne,s   normal\n\t"
 8578             "xorl    rdx, rdx\n\t"
 8579             "cmpq    $div, -1\n\t"
 8580             "je,s    done\n"
 8581     "normal: cdqq\n\t"
 8582             "idivq   $div\n"
 8583     "done:"        %}
 8584   ins_encode(cdqq_enc(div));
 8585   ins_pipe(pipe_slow);
 8586 %}
 8587 
 8588 //----------- DivL-By-Constant-Expansions--------------------------------------
 8589 // DivI cases are handled by the compiler
 8590 
 8591 // Magic constant, reciprocal of 10
 8592 instruct loadConL_0x6666666666666667(rRegL dst)
 8593 %{
 8594   effect(DEF dst);
 8595 
 8596   format %{ "movq    $dst, #0x666666666666667\t# Used in div-by-10" %}
 8597   ins_encode(load_immL(dst, 0x6666666666666667));
 8598   ins_pipe(ialu_reg);
 8599 %}
 8600 
 8601 instruct mul_hi(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr)
 8602 %{
 8603   effect(DEF dst, USE src, USE_KILL rax, KILL cr);
 8604 
 8605   format %{ "imulq   rdx:rax, rax, $src\t# Used in div-by-10" %}
 8606   ins_encode %{
 8607     __ imulq($src$$Register);
 8608   %}
 8609   ins_pipe(ialu_reg_reg_alu0);
 8610 %}
 8611 
 8612 instruct sarL_rReg_63(rRegL dst, rFlagsReg cr)
 8613 %{
 8614   effect(USE_DEF dst, KILL cr);
 8615 
 8616   format %{ "sarq    $dst, #63\t# Used in div-by-10" %}
 8617   ins_encode %{
 8618     __ sarq($dst$$Register, 63);
 8619   %}
 8620   ins_pipe(ialu_reg);
 8621 %}
 8622 
 8623 instruct sarL_rReg_2(rRegL dst, rFlagsReg cr)
 8624 %{
 8625   effect(USE_DEF dst, KILL cr);
 8626 
 8627   format %{ "sarq    $dst, #2\t# Used in div-by-10" %}
 8628   ins_encode %{
 8629     __ sarq($dst$$Register, 2);
 8630   %}
 8631   ins_pipe(ialu_reg);
 8632 %}
 8633 
 8634 instruct divL_10(rdx_RegL dst, no_rax_RegL src, immL10 div)
 8635 %{
 8636   match(Set dst (DivL src div));
 8637 
 8638   ins_cost((5+8)*100);
 8639   expand %{
 8640     rax_RegL rax;                     // Killed temp
 8641     rFlagsReg cr;                     // Killed
 8642     loadConL_0x6666666666666667(rax); // movq  rax, 0x6666666666666667
 8643     mul_hi(dst, src, rax, cr);        // mulq  rdx:rax <= rax * $src
 8644     sarL_rReg_63(src, cr);            // sarq  src, 63
 8645     sarL_rReg_2(dst, cr);             // sarq  rdx, 2
 8646     subL_rReg(dst, src, cr);          // subl  rdx, src
 8647   %}
 8648 %}
 8649 
 8650 //-----------------------------------------------------------------------------
 8651 
 8652 instruct modI_rReg(rdx_RegI rdx, rax_RegI rax, no_rax_rdx_RegI div,
 8653                    rFlagsReg cr)
 8654 %{
 8655   match(Set rdx (ModI rax div));
 8656   effect(KILL rax, KILL cr);
 8657 
 8658   ins_cost(300); // XXX
 8659   format %{ "cmpl    rax, 0x80000000\t# irem\n\t"
 8660             "jne,s   normal\n\t"
 8661             "xorl    rdx, rdx\n\t"
 8662             "cmpl    $div, -1\n\t"
 8663             "je,s    done\n"
 8664     "normal: cdql\n\t"
 8665             "idivl   $div\n"
 8666     "done:"        %}
 8667   ins_encode(cdql_enc(div));
 8668   ins_pipe(ialu_reg_reg_alu0);
 8669 %}
 8670 
 8671 instruct modL_rReg(rdx_RegL rdx, rax_RegL rax, no_rax_rdx_RegL div,
 8672                    rFlagsReg cr)
 8673 %{
 8674   match(Set rdx (ModL rax div));
 8675   effect(KILL rax, KILL cr);
 8676 
 8677   ins_cost(300); // XXX
 8678   format %{ "movq    rdx, 0x8000000000000000\t# lrem\n\t"
 8679             "cmpq    rax, rdx\n\t"
 8680             "jne,s   normal\n\t"
 8681             "xorl    rdx, rdx\n\t"
 8682             "cmpq    $div, -1\n\t"
 8683             "je,s    done\n"
 8684     "normal: cdqq\n\t"
 8685             "idivq   $div\n"
 8686     "done:"        %}
 8687   ins_encode(cdqq_enc(div));
 8688   ins_pipe(ialu_reg_reg_alu0);
 8689 %}
 8690 
 8691 // Integer Shift Instructions
 8692 // Shift Left by one
 8693 instruct salI_rReg_1(rRegI dst, immI_1 shift, rFlagsReg cr)
 8694 %{
 8695   match(Set dst (LShiftI dst shift));
 8696   effect(KILL cr);
 8697 
 8698   format %{ "sall    $dst, $shift" %}
 8699   ins_encode %{
 8700     __ sall($dst$$Register, $shift$$constant);
 8701   %}
 8702   ins_pipe(ialu_reg);
 8703 %}
 8704 
 8705 // Shift Left by one
 8706 instruct salI_mem_1(memory dst, immI_1 shift, rFlagsReg cr)
 8707 %{
 8708   match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
 8709   effect(KILL cr);
 8710 
 8711   format %{ "sall    $dst, $shift\t" %}
 8712   ins_encode %{
 8713     __ sall($dst$$Address, $shift$$constant);
 8714   %}
 8715   ins_pipe(ialu_mem_imm);
 8716 %}
 8717 
 8718 // Shift Left by 8-bit immediate
 8719 instruct salI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
 8720 %{
 8721   match(Set dst (LShiftI dst shift));
 8722   effect(KILL cr);
 8723 
 8724   format %{ "sall    $dst, $shift" %}
 8725   ins_encode %{
 8726     __ sall($dst$$Register, $shift$$constant);
 8727   %}
 8728   ins_pipe(ialu_reg);
 8729 %}
 8730 
 8731 // Shift Left by 8-bit immediate
 8732 instruct salI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
 8733 %{
 8734   match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
 8735   effect(KILL cr);
 8736 
 8737   format %{ "sall    $dst, $shift" %}
 8738   ins_encode %{
 8739     __ sall($dst$$Address, $shift$$constant);
 8740   %}
 8741   ins_pipe(ialu_mem_imm);
 8742 %}
 8743 
 8744 // Shift Left by variable
 8745 instruct salI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
 8746 %{
 8747   match(Set dst (LShiftI dst shift));
 8748   effect(KILL cr);
 8749 
 8750   format %{ "sall    $dst, $shift" %}
 8751   ins_encode %{
 8752     __ sall($dst$$Register);
 8753   %}
 8754   ins_pipe(ialu_reg_reg);
 8755 %}
 8756 
 8757 // Shift Left by variable
 8758 instruct salI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
 8759 %{
 8760   match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
 8761   effect(KILL cr);
 8762 
 8763   format %{ "sall    $dst, $shift" %}
 8764   ins_encode %{
 8765     __ sall($dst$$Address);
 8766   %}
 8767   ins_pipe(ialu_mem_reg);
 8768 %}
 8769 
 8770 // Arithmetic shift right by one
 8771 instruct sarI_rReg_1(rRegI dst, immI_1 shift, rFlagsReg cr)
 8772 %{
 8773   match(Set dst (RShiftI dst shift));
 8774   effect(KILL cr);
 8775 
 8776   format %{ "sarl    $dst, $shift" %}
 8777   ins_encode %{
 8778     __ sarl($dst$$Register, $shift$$constant);
 8779   %}
 8780   ins_pipe(ialu_reg);
 8781 %}
 8782 
 8783 // Arithmetic shift right by one
 8784 instruct sarI_mem_1(memory dst, immI_1 shift, rFlagsReg cr)
 8785 %{
 8786   match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
 8787   effect(KILL cr);
 8788 
 8789   format %{ "sarl    $dst, $shift" %}
 8790   ins_encode %{
 8791     __ sarl($dst$$Address, $shift$$constant);
 8792   %}
 8793   ins_pipe(ialu_mem_imm);
 8794 %}
 8795 
 8796 // Arithmetic Shift Right by 8-bit immediate
 8797 instruct sarI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
 8798 %{
 8799   match(Set dst (RShiftI dst shift));
 8800   effect(KILL cr);
 8801 
 8802   format %{ "sarl    $dst, $shift" %}
 8803   ins_encode %{
 8804     __ sarl($dst$$Register, $shift$$constant);
 8805   %}
 8806   ins_pipe(ialu_mem_imm);
 8807 %}
 8808 
 8809 // Arithmetic Shift Right by 8-bit immediate
 8810 instruct sarI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
 8811 %{
 8812   match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
 8813   effect(KILL cr);
 8814 
 8815   format %{ "sarl    $dst, $shift" %}
 8816   ins_encode %{
 8817     __ sarl($dst$$Address, $shift$$constant);
 8818   %}
 8819   ins_pipe(ialu_mem_imm);
 8820 %}
 8821 
 8822 // Arithmetic Shift Right by variable
 8823 instruct sarI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
 8824 %{
 8825   match(Set dst (RShiftI dst shift));
 8826   effect(KILL cr);
 8827   format %{ "sarl    $dst, $shift" %}
 8828   ins_encode %{
 8829     __ sarl($dst$$Register);
 8830   %}
 8831   ins_pipe(ialu_reg_reg);
 8832 %}
 8833 
 8834 // Arithmetic Shift Right by variable
 8835 instruct sarI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
 8836 %{
 8837   match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
 8838   effect(KILL cr);
 8839 
 8840   format %{ "sarl    $dst, $shift" %}
 8841   ins_encode %{
 8842     __ sarl($dst$$Address);
 8843   %}
 8844   ins_pipe(ialu_mem_reg);
 8845 %}
 8846 
 8847 // Logical shift right by one
 8848 instruct shrI_rReg_1(rRegI dst, immI_1 shift, rFlagsReg cr)
 8849 %{
 8850   match(Set dst (URShiftI dst shift));
 8851   effect(KILL cr);
 8852 
 8853   format %{ "shrl    $dst, $shift" %}
 8854   ins_encode %{
 8855     __ shrl($dst$$Register, $shift$$constant);
 8856   %}
 8857   ins_pipe(ialu_reg);
 8858 %}
 8859 
 8860 // Logical shift right by one
 8861 instruct shrI_mem_1(memory dst, immI_1 shift, rFlagsReg cr)
 8862 %{
 8863   match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
 8864   effect(KILL cr);
 8865 
 8866   format %{ "shrl    $dst, $shift" %}
 8867   ins_encode %{
 8868     __ shrl($dst$$Address, $shift$$constant);
 8869   %}
 8870   ins_pipe(ialu_mem_imm);
 8871 %}
 8872 
 8873 // Logical Shift Right by 8-bit immediate
 8874 instruct shrI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
 8875 %{
 8876   match(Set dst (URShiftI dst shift));
 8877   effect(KILL cr);
 8878 
 8879   format %{ "shrl    $dst, $shift" %}
 8880   ins_encode %{
 8881     __ shrl($dst$$Register, $shift$$constant);
 8882   %}
 8883   ins_pipe(ialu_reg);
 8884 %}
 8885 
 8886 // Logical Shift Right by 8-bit immediate
 8887 instruct shrI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
 8888 %{
 8889   match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
 8890   effect(KILL cr);
 8891 
 8892   format %{ "shrl    $dst, $shift" %}
 8893   ins_encode %{
 8894     __ shrl($dst$$Address, $shift$$constant);
 8895   %}
 8896   ins_pipe(ialu_mem_imm);
 8897 %}
 8898 
 8899 // Logical Shift Right by variable
 8900 instruct shrI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
 8901 %{
 8902   match(Set dst (URShiftI dst shift));
 8903   effect(KILL cr);
 8904 
 8905   format %{ "shrl    $dst, $shift" %}
 8906   ins_encode %{
 8907     __ shrl($dst$$Register);
 8908   %}
 8909   ins_pipe(ialu_reg_reg);
 8910 %}
 8911 
 8912 // Logical Shift Right by variable
 8913 instruct shrI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
 8914 %{
 8915   match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
 8916   effect(KILL cr);
 8917 
 8918   format %{ "shrl    $dst, $shift" %}
 8919   ins_encode %{
 8920     __ shrl($dst$$Address);
 8921   %}
 8922   ins_pipe(ialu_mem_reg);
 8923 %}
 8924 
 8925 // Long Shift Instructions
 8926 // Shift Left by one
 8927 instruct salL_rReg_1(rRegL dst, immI_1 shift, rFlagsReg cr)
 8928 %{
 8929   match(Set dst (LShiftL dst shift));
 8930   effect(KILL cr);
 8931 
 8932   format %{ "salq    $dst, $shift" %}
 8933   ins_encode %{
 8934     __ salq($dst$$Register, $shift$$constant);
 8935   %}
 8936   ins_pipe(ialu_reg);
 8937 %}
 8938 
 8939 // Shift Left by one
 8940 instruct salL_mem_1(memory dst, immI_1 shift, rFlagsReg cr)
 8941 %{
 8942   match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
 8943   effect(KILL cr);
 8944 
 8945   format %{ "salq    $dst, $shift" %}
 8946   ins_encode %{
 8947     __ salq($dst$$Address, $shift$$constant);
 8948   %}
 8949   ins_pipe(ialu_mem_imm);
 8950 %}
 8951 
 8952 // Shift Left by 8-bit immediate
 8953 instruct salL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
 8954 %{
 8955   match(Set dst (LShiftL dst shift));
 8956   effect(KILL cr);
 8957 
 8958   format %{ "salq    $dst, $shift" %}
 8959   ins_encode %{
 8960     __ salq($dst$$Register, $shift$$constant);
 8961   %}
 8962   ins_pipe(ialu_reg);
 8963 %}
 8964 
 8965 // Shift Left by 8-bit immediate
 8966 instruct salL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
 8967 %{
 8968   match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
 8969   effect(KILL cr);
 8970 
 8971   format %{ "salq    $dst, $shift" %}
 8972   ins_encode %{
 8973     __ salq($dst$$Address, $shift$$constant);
 8974   %}
 8975   ins_pipe(ialu_mem_imm);
 8976 %}
 8977 
 8978 // Shift Left by variable
 8979 instruct salL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
 8980 %{
 8981   match(Set dst (LShiftL dst shift));
 8982   effect(KILL cr);
 8983 
 8984   format %{ "salq    $dst, $shift" %}
 8985   ins_encode %{
 8986     __ salq($dst$$Register);
 8987   %}
 8988   ins_pipe(ialu_reg_reg);
 8989 %}
 8990 
 8991 // Shift Left by variable
 8992 instruct salL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
 8993 %{
 8994   match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
 8995   effect(KILL cr);
 8996 
 8997   format %{ "salq    $dst, $shift" %}
 8998   ins_encode %{
 8999     __ salq($dst$$Address);
 9000   %}
 9001   ins_pipe(ialu_mem_reg);
 9002 %}
 9003 
 9004 // Arithmetic shift right by one
 9005 instruct sarL_rReg_1(rRegL dst, immI_1 shift, rFlagsReg cr)
 9006 %{
 9007   match(Set dst (RShiftL dst shift));
 9008   effect(KILL cr);
 9009 
 9010   format %{ "sarq    $dst, $shift" %}
 9011   ins_encode %{
 9012     __ sarq($dst$$Register, $shift$$constant);
 9013   %}
 9014   ins_pipe(ialu_reg);
 9015 %}
 9016 
 9017 // Arithmetic shift right by one
 9018 instruct sarL_mem_1(memory dst, immI_1 shift, rFlagsReg cr)
 9019 %{
 9020   match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
 9021   effect(KILL cr);
 9022 
 9023   format %{ "sarq    $dst, $shift" %}
 9024   ins_encode %{
 9025     __ sarq($dst$$Address, $shift$$constant);
 9026   %}
 9027   ins_pipe(ialu_mem_imm);
 9028 %}
 9029 
 9030 // Arithmetic Shift Right by 8-bit immediate
 9031 instruct sarL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
 9032 %{
 9033   match(Set dst (RShiftL dst shift));
 9034   effect(KILL cr);
 9035 
 9036   format %{ "sarq    $dst, $shift" %}
 9037   ins_encode %{
 9038     __ sarq($dst$$Register, (unsigned char)($shift$$constant & 0x3F));
 9039   %}
 9040   ins_pipe(ialu_mem_imm);
 9041 %}
 9042 
 9043 // Arithmetic Shift Right by 8-bit immediate
 9044 instruct sarL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
 9045 %{
 9046   match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
 9047   effect(KILL cr);
 9048 
 9049   format %{ "sarq    $dst, $shift" %}
 9050   ins_encode %{
 9051     __ sarq($dst$$Address, (unsigned char)($shift$$constant & 0x3F));
 9052   %}
 9053   ins_pipe(ialu_mem_imm);
 9054 %}
 9055 
 9056 // Arithmetic Shift Right by variable
 9057 instruct sarL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
 9058 %{
 9059   match(Set dst (RShiftL dst shift));
 9060   effect(KILL cr);
 9061 
 9062   format %{ "sarq    $dst, $shift" %}
 9063   ins_encode %{
 9064     __ sarq($dst$$Register);
 9065   %}
 9066   ins_pipe(ialu_reg_reg);
 9067 %}
 9068 
 9069 // Arithmetic Shift Right by variable
 9070 instruct sarL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
 9071 %{
 9072   match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
 9073   effect(KILL cr);
 9074 
 9075   format %{ "sarq    $dst, $shift" %}
 9076   ins_encode %{
 9077     __ sarq($dst$$Address);
 9078   %}
 9079   ins_pipe(ialu_mem_reg);
 9080 %}
 9081 
 9082 // Logical shift right by one
 9083 instruct shrL_rReg_1(rRegL dst, immI_1 shift, rFlagsReg cr)
 9084 %{
 9085   match(Set dst (URShiftL dst shift));
 9086   effect(KILL cr);
 9087 
 9088   format %{ "shrq    $dst, $shift" %}
 9089   ins_encode %{
 9090     __ shrq($dst$$Register, $shift$$constant);
 9091   %}
 9092   ins_pipe(ialu_reg);
 9093 %}
 9094 
 9095 // Logical shift right by one
 9096 instruct shrL_mem_1(memory dst, immI_1 shift, rFlagsReg cr)
 9097 %{
 9098   match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
 9099   effect(KILL cr);
 9100 
 9101   format %{ "shrq    $dst, $shift" %}
 9102   ins_encode %{
 9103     __ shrq($dst$$Address, $shift$$constant);
 9104   %}
 9105   ins_pipe(ialu_mem_imm);
 9106 %}
 9107 
 9108 // Logical Shift Right by 8-bit immediate
 9109 instruct shrL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
 9110 %{
 9111   match(Set dst (URShiftL dst shift));
 9112   effect(KILL cr);
 9113 
 9114   format %{ "shrq    $dst, $shift" %}
 9115   ins_encode %{
 9116     __ shrq($dst$$Register, $shift$$constant);
 9117   %}
 9118   ins_pipe(ialu_reg);
 9119 %}
 9120 
 9121 // Logical Shift Right by 8-bit immediate
 9122 instruct shrL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
 9123 %{
 9124   match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
 9125   effect(KILL cr);
 9126 
 9127   format %{ "shrq    $dst, $shift" %}
 9128   ins_encode %{
 9129     __ shrq($dst$$Address, $shift$$constant);
 9130   %}
 9131   ins_pipe(ialu_mem_imm);
 9132 %}
 9133 
 9134 // Logical Shift Right by variable
 9135 instruct shrL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
 9136 %{
 9137   match(Set dst (URShiftL dst shift));
 9138   effect(KILL cr);
 9139 
 9140   format %{ "shrq    $dst, $shift" %}
 9141   ins_encode %{
 9142     __ shrq($dst$$Register);
 9143   %}
 9144   ins_pipe(ialu_reg_reg);
 9145 %}
 9146 
 9147 // Logical Shift Right by variable
 9148 instruct shrL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
 9149 %{
 9150   match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
 9151   effect(KILL cr);
 9152 
 9153   format %{ "shrq    $dst, $shift" %}
 9154   ins_encode %{
 9155     __ shrq($dst$$Address);
 9156   %}
 9157   ins_pipe(ialu_mem_reg);
 9158 %}
 9159 
 9160 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
 9161 // This idiom is used by the compiler for the i2b bytecode.
 9162 instruct i2b(rRegI dst, rRegI src, immI_24 twentyfour)
 9163 %{
 9164   match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour));
 9165 
 9166   format %{ "movsbl  $dst, $src\t# i2b" %}
 9167   ins_encode %{
 9168     __ movsbl($dst$$Register, $src$$Register);
 9169   %}
 9170   ins_pipe(ialu_reg_reg);
 9171 %}
 9172 
 9173 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16.
 9174 // This idiom is used by the compiler the i2s bytecode.
 9175 instruct i2s(rRegI dst, rRegI src, immI_16 sixteen)
 9176 %{
 9177   match(Set dst (RShiftI (LShiftI src sixteen) sixteen));
 9178 
 9179   format %{ "movswl  $dst, $src\t# i2s" %}
 9180   ins_encode %{
 9181     __ movswl($dst$$Register, $src$$Register);
 9182   %}
 9183   ins_pipe(ialu_reg_reg);
 9184 %}
 9185 
 9186 // ROL/ROR instructions
 9187 
 9188 // Rotate left by constant.
 9189 instruct rolI_imm(rRegI dst, immI8 shift, rFlagsReg cr)
 9190 %{
 9191   predicate(n->bottom_type()->basic_type() == T_INT);
 9192   match(Set dst (RotateLeft dst shift));
 9193   effect(KILL cr);
 9194   format %{ "roll    $dst, $shift" %}
 9195   ins_encode %{
 9196     __ roll($dst$$Register, $shift$$constant);
 9197   %}
 9198   ins_pipe(ialu_reg);
 9199 %}
 9200 
 9201 // Rotate Left by variable
 9202 instruct rolI_rReg_Var(rRegI dst, rcx_RegI shift, rFlagsReg cr)
 9203 %{
 9204   predicate(n->bottom_type()->basic_type() == T_INT);
 9205   match(Set dst (RotateLeft dst shift));
 9206   effect(KILL cr);
 9207   format %{ "roll    $dst, $shift" %}
 9208   ins_encode %{
 9209     __ roll($dst$$Register);
 9210   %}
 9211   ins_pipe(ialu_reg_reg);
 9212 %}
 9213 
 9214 // Rotate Right by constant.
 9215 instruct rorI_immI8_legacy(rRegI dst, immI8 shift, rFlagsReg cr)
 9216 %{
 9217   predicate(!VM_Version::supports_bmi2() && n->bottom_type()->basic_type() == T_INT);
 9218   match(Set dst (RotateRight dst shift));
 9219   effect(KILL cr);
 9220   format %{ "rorl    $dst, $shift" %}
 9221   ins_encode %{
 9222     __ rorl($dst$$Register, $shift$$constant);
 9223   %}
 9224   ins_pipe(ialu_reg);
 9225 %}
 9226 
 9227 // Rotate Right by constant.
 9228 instruct rorI_immI8(rRegI dst, immI8 shift)
 9229 %{
 9230   predicate(VM_Version::supports_bmi2() && n->bottom_type()->basic_type() == T_INT);
 9231   match(Set dst (RotateRight dst shift));
 9232   format %{ "rorxd     $dst, $shift" %}
 9233   ins_encode %{
 9234     __ rorxd($dst$$Register, $dst$$Register, $shift$$constant);
 9235   %}
 9236   ins_pipe(ialu_reg_reg);
 9237 %}
 9238 
 9239 // Rotate Right by variable
 9240 instruct rorI_rReg_Var(rRegI dst, rcx_RegI shift, rFlagsReg cr)
 9241 %{
 9242   predicate(n->bottom_type()->basic_type() == T_INT);
 9243   match(Set dst (RotateRight dst shift));
 9244   effect(KILL cr);
 9245   format %{ "rorl    $dst, $shift" %}
 9246   ins_encode %{
 9247     __ rorl($dst$$Register);
 9248   %}
 9249   ins_pipe(ialu_reg_reg);
 9250 %}
 9251 
 9252 
 9253 // Rotate Left by constant.
 9254 instruct rolL_immI8(rRegL dst, immI8 shift, rFlagsReg cr)
 9255 %{
 9256   predicate(n->bottom_type()->basic_type() == T_LONG);
 9257   match(Set dst (RotateLeft dst shift));
 9258   effect(KILL cr);
 9259   format %{ "rolq    $dst, $shift" %}
 9260   ins_encode %{
 9261     __ rolq($dst$$Register, $shift$$constant);
 9262   %}
 9263   ins_pipe(ialu_reg);
 9264 %}
 9265 
 9266 // Rotate Left by variable
 9267 instruct rolL_rReg_Var(rRegL dst, rcx_RegI shift, rFlagsReg cr)
 9268 %{
 9269   predicate(n->bottom_type()->basic_type() == T_LONG);
 9270   match(Set dst (RotateLeft dst shift));
 9271   effect(KILL cr);
 9272   format %{ "rolq    $dst, $shift" %}
 9273   ins_encode %{
 9274     __ rolq($dst$$Register);
 9275   %}
 9276   ins_pipe(ialu_reg_reg);
 9277 %}
 9278 
 9279 
 9280 // Rotate Right by constant.
 9281 instruct rorL_immI8_legacy(rRegL dst, immI8 shift, rFlagsReg cr)
 9282 %{
 9283   predicate(!VM_Version::supports_bmi2() && n->bottom_type()->basic_type() == T_LONG);
 9284   match(Set dst (RotateRight dst shift));
 9285   effect(KILL cr);
 9286   format %{ "rorq    $dst, $shift" %}
 9287   ins_encode %{
 9288     __ rorq($dst$$Register, $shift$$constant);
 9289   %}
 9290   ins_pipe(ialu_reg);
 9291 %}
 9292 
 9293 
 9294 // Rotate Right by constant
 9295 instruct rorL_immI8(rRegL dst, immI8 shift)
 9296 %{
 9297   predicate(VM_Version::supports_bmi2() && n->bottom_type()->basic_type() == T_LONG);
 9298   match(Set dst (RotateRight dst shift));
 9299   format %{ "rorxq    $dst, $shift" %}
 9300   ins_encode %{
 9301     __ rorxq($dst$$Register, $dst$$Register, $shift$$constant);
 9302   %}
 9303   ins_pipe(ialu_reg_reg);
 9304 %}
 9305 
 9306 // Rotate Right by variable
 9307 instruct rorL_rReg_Var(rRegL dst, rcx_RegI shift, rFlagsReg cr)
 9308 %{
 9309   predicate(n->bottom_type()->basic_type() == T_LONG);
 9310   match(Set dst (RotateRight dst shift));
 9311   effect(KILL cr);
 9312   format %{ "rorq    $dst, $shift" %}
 9313   ins_encode %{
 9314     __ rorq($dst$$Register);
 9315   %}
 9316   ins_pipe(ialu_reg_reg);
 9317 %}
 9318 
 9319 
 9320 // Logical Instructions
 9321 
 9322 // Integer Logical Instructions
 9323 
 9324 // And Instructions
 9325 // And Register with Register
 9326 instruct andI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
 9327 %{
 9328   match(Set dst (AndI dst src));
 9329   effect(KILL cr);
 9330 
 9331   format %{ "andl    $dst, $src\t# int" %}
 9332   ins_encode %{
 9333     __ andl($dst$$Register, $src$$Register);
 9334   %}
 9335   ins_pipe(ialu_reg_reg);
 9336 %}
 9337 
 9338 // And Register with Immediate 255
 9339 instruct andI_rReg_imm255(rRegI dst, immI_255 src)
 9340 %{
 9341   match(Set dst (AndI dst src));
 9342 
 9343   format %{ "movzbl  $dst, $dst\t# int & 0xFF" %}
 9344   ins_encode %{
 9345     __ movzbl($dst$$Register, $dst$$Register);
 9346   %}
 9347   ins_pipe(ialu_reg);
 9348 %}
 9349 
 9350 // And Register with Immediate 255 and promote to long
 9351 instruct andI2L_rReg_imm255(rRegL dst, rRegI src, immI_255 mask)
 9352 %{
 9353   match(Set dst (ConvI2L (AndI src mask)));
 9354 
 9355   format %{ "movzbl  $dst, $src\t# int & 0xFF -> long" %}
 9356   ins_encode %{
 9357     __ movzbl($dst$$Register, $src$$Register);
 9358   %}
 9359   ins_pipe(ialu_reg);
 9360 %}
 9361 
 9362 // And Register with Immediate 65535
 9363 instruct andI_rReg_imm65535(rRegI dst, immI_65535 src)
 9364 %{
 9365   match(Set dst (AndI dst src));
 9366 
 9367   format %{ "movzwl  $dst, $dst\t# int & 0xFFFF" %}
 9368   ins_encode %{
 9369     __ movzwl($dst$$Register, $dst$$Register);
 9370   %}
 9371   ins_pipe(ialu_reg);
 9372 %}
 9373 
 9374 // And Register with Immediate 65535 and promote to long
 9375 instruct andI2L_rReg_imm65535(rRegL dst, rRegI src, immI_65535 mask)
 9376 %{
 9377   match(Set dst (ConvI2L (AndI src mask)));
 9378 
 9379   format %{ "movzwl  $dst, $src\t# int & 0xFFFF -> long" %}
 9380   ins_encode %{
 9381     __ movzwl($dst$$Register, $src$$Register);
 9382   %}
 9383   ins_pipe(ialu_reg);
 9384 %}
 9385 
 9386 // Can skip int2long conversions after AND with small bitmask
 9387 instruct convI2LAndI_reg_immIbitmask(rRegL dst, rRegI src,  immI_Pow2M1 mask, rRegI tmp, rFlagsReg cr)
 9388 %{
 9389   predicate(VM_Version::supports_bmi2());
 9390   ins_cost(125);
 9391   effect(TEMP tmp, KILL cr);
 9392   match(Set dst (ConvI2L (AndI src mask)));
 9393   format %{ "bzhiq $dst, $src, $mask \t# using $tmp as TEMP, int &  immI_Pow2M1 -> long" %}
 9394   ins_encode %{
 9395     __ movl($tmp$$Register, exact_log2($mask$$constant + 1));
 9396     __ bzhiq($dst$$Register, $src$$Register, $tmp$$Register);
 9397   %}
 9398   ins_pipe(ialu_reg_reg);
 9399 %}
 9400 
 9401 // And Register with Immediate
 9402 instruct andI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
 9403 %{
 9404   match(Set dst (AndI dst src));
 9405   effect(KILL cr);
 9406 
 9407   format %{ "andl    $dst, $src\t# int" %}
 9408   ins_encode %{
 9409     __ andl($dst$$Register, $src$$constant);
 9410   %}
 9411   ins_pipe(ialu_reg);
 9412 %}
 9413 
 9414 // And Register with Memory
 9415 instruct andI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
 9416 %{
 9417   match(Set dst (AndI dst (LoadI src)));
 9418   effect(KILL cr);
 9419 
 9420   ins_cost(125);
 9421   format %{ "andl    $dst, $src\t# int" %}
 9422   ins_encode %{
 9423     __ andl($dst$$Register, $src$$Address);
 9424   %}
 9425   ins_pipe(ialu_reg_mem);
 9426 %}
 9427 
 9428 // And Memory with Register
 9429 instruct andB_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
 9430 %{
 9431   match(Set dst (StoreB dst (AndI (LoadB dst) src)));
 9432   effect(KILL cr);
 9433 
 9434   ins_cost(150);
 9435   format %{ "andb    $dst, $src\t# byte" %}
 9436   ins_encode %{
 9437     __ andb($dst$$Address, $src$$Register);
 9438   %}
 9439   ins_pipe(ialu_mem_reg);
 9440 %}
 9441 
 9442 instruct andI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
 9443 %{
 9444   match(Set dst (StoreI dst (AndI (LoadI dst) src)));
 9445   effect(KILL cr);
 9446 
 9447   ins_cost(150);
 9448   format %{ "andl    $dst, $src\t# int" %}
 9449   ins_encode %{
 9450     __ andl($dst$$Address, $src$$Register);
 9451   %}
 9452   ins_pipe(ialu_mem_reg);
 9453 %}
 9454 
 9455 // And Memory with Immediate
 9456 instruct andI_mem_imm(memory dst, immI src, rFlagsReg cr)
 9457 %{
 9458   match(Set dst (StoreI dst (AndI (LoadI dst) src)));
 9459   effect(KILL cr);
 9460 
 9461   ins_cost(125);
 9462   format %{ "andl    $dst, $src\t# int" %}
 9463   ins_encode %{
 9464     __ andl($dst$$Address, $src$$constant);
 9465   %}
 9466   ins_pipe(ialu_mem_imm);
 9467 %}
 9468 
 9469 // BMI1 instructions
 9470 instruct andnI_rReg_rReg_mem(rRegI dst, rRegI src1, memory src2, immI_M1 minus_1, rFlagsReg cr) %{
 9471   match(Set dst (AndI (XorI src1 minus_1) (LoadI src2)));
 9472   predicate(UseBMI1Instructions);
 9473   effect(KILL cr);
 9474 
 9475   ins_cost(125);
 9476   format %{ "andnl  $dst, $src1, $src2" %}
 9477 
 9478   ins_encode %{
 9479     __ andnl($dst$$Register, $src1$$Register, $src2$$Address);
 9480   %}
 9481   ins_pipe(ialu_reg_mem);
 9482 %}
 9483 
 9484 instruct andnI_rReg_rReg_rReg(rRegI dst, rRegI src1, rRegI src2, immI_M1 minus_1, rFlagsReg cr) %{
 9485   match(Set dst (AndI (XorI src1 minus_1) src2));
 9486   predicate(UseBMI1Instructions);
 9487   effect(KILL cr);
 9488 
 9489   format %{ "andnl  $dst, $src1, $src2" %}
 9490 
 9491   ins_encode %{
 9492     __ andnl($dst$$Register, $src1$$Register, $src2$$Register);
 9493   %}
 9494   ins_pipe(ialu_reg);
 9495 %}
 9496 
 9497 instruct blsiI_rReg_rReg(rRegI dst, rRegI src, immI_0 imm_zero, rFlagsReg cr) %{
 9498   match(Set dst (AndI (SubI imm_zero src) src));
 9499   predicate(UseBMI1Instructions);
 9500   effect(KILL cr);
 9501 
 9502   format %{ "blsil  $dst, $src" %}
 9503 
 9504   ins_encode %{
 9505     __ blsil($dst$$Register, $src$$Register);
 9506   %}
 9507   ins_pipe(ialu_reg);
 9508 %}
 9509 
 9510 instruct blsiI_rReg_mem(rRegI dst, memory src, immI_0 imm_zero, rFlagsReg cr) %{
 9511   match(Set dst (AndI (SubI imm_zero (LoadI src) ) (LoadI src) ));
 9512   predicate(UseBMI1Instructions);
 9513   effect(KILL cr);
 9514 
 9515   ins_cost(125);
 9516   format %{ "blsil  $dst, $src" %}
 9517 
 9518   ins_encode %{
 9519     __ blsil($dst$$Register, $src$$Address);
 9520   %}
 9521   ins_pipe(ialu_reg_mem);
 9522 %}
 9523 
 9524 instruct blsmskI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, rFlagsReg cr)
 9525 %{
 9526   match(Set dst (XorI (AddI (LoadI src) minus_1) (LoadI src) ) );
 9527   predicate(UseBMI1Instructions);
 9528   effect(KILL cr);
 9529 
 9530   ins_cost(125);
 9531   format %{ "blsmskl $dst, $src" %}
 9532 
 9533   ins_encode %{
 9534     __ blsmskl($dst$$Register, $src$$Address);
 9535   %}
 9536   ins_pipe(ialu_reg_mem);
 9537 %}
 9538 
 9539 instruct blsmskI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, rFlagsReg cr)
 9540 %{
 9541   match(Set dst (XorI (AddI src minus_1) src));
 9542   predicate(UseBMI1Instructions);
 9543   effect(KILL cr);
 9544 
 9545   format %{ "blsmskl $dst, $src" %}
 9546 
 9547   ins_encode %{
 9548     __ blsmskl($dst$$Register, $src$$Register);
 9549   %}
 9550 
 9551   ins_pipe(ialu_reg);
 9552 %}
 9553 
 9554 instruct blsrI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, rFlagsReg cr)
 9555 %{
 9556   match(Set dst (AndI (AddI src minus_1) src) );
 9557   predicate(UseBMI1Instructions);
 9558   effect(KILL cr);
 9559 
 9560   format %{ "blsrl  $dst, $src" %}
 9561 
 9562   ins_encode %{
 9563     __ blsrl($dst$$Register, $src$$Register);
 9564   %}
 9565 
 9566   ins_pipe(ialu_reg_mem);
 9567 %}
 9568 
 9569 instruct blsrI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, rFlagsReg cr)
 9570 %{
 9571   match(Set dst (AndI (AddI (LoadI src) minus_1) (LoadI src) ) );
 9572   predicate(UseBMI1Instructions);
 9573   effect(KILL cr);
 9574 
 9575   ins_cost(125);
 9576   format %{ "blsrl  $dst, $src" %}
 9577 
 9578   ins_encode %{
 9579     __ blsrl($dst$$Register, $src$$Address);
 9580   %}
 9581 
 9582   ins_pipe(ialu_reg);
 9583 %}
 9584 
 9585 // Or Instructions
 9586 // Or Register with Register
 9587 instruct orI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
 9588 %{
 9589   match(Set dst (OrI dst src));
 9590   effect(KILL cr);
 9591 
 9592   format %{ "orl     $dst, $src\t# int" %}
 9593   ins_encode %{
 9594     __ orl($dst$$Register, $src$$Register);
 9595   %}
 9596   ins_pipe(ialu_reg_reg);
 9597 %}
 9598 
 9599 // Or Register with Immediate
 9600 instruct orI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
 9601 %{
 9602   match(Set dst (OrI dst src));
 9603   effect(KILL cr);
 9604 
 9605   format %{ "orl     $dst, $src\t# int" %}
 9606   ins_encode %{
 9607     __ orl($dst$$Register, $src$$constant);
 9608   %}
 9609   ins_pipe(ialu_reg);
 9610 %}
 9611 
 9612 // Or Register with Memory
 9613 instruct orI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
 9614 %{
 9615   match(Set dst (OrI dst (LoadI src)));
 9616   effect(KILL cr);
 9617 
 9618   ins_cost(125);
 9619   format %{ "orl     $dst, $src\t# int" %}
 9620   ins_encode %{
 9621     __ orl($dst$$Register, $src$$Address);
 9622   %}
 9623   ins_pipe(ialu_reg_mem);
 9624 %}
 9625 
 9626 // Or Memory with Register
 9627 instruct orB_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
 9628 %{
 9629   match(Set dst (StoreB dst (OrI (LoadB dst) src)));
 9630   effect(KILL cr);
 9631 
 9632   ins_cost(150);
 9633   format %{ "orb    $dst, $src\t# byte" %}
 9634   ins_encode %{
 9635     __ orb($dst$$Address, $src$$Register);
 9636   %}
 9637   ins_pipe(ialu_mem_reg);
 9638 %}
 9639 
 9640 instruct orI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
 9641 %{
 9642   match(Set dst (StoreI dst (OrI (LoadI dst) src)));
 9643   effect(KILL cr);
 9644 
 9645   ins_cost(150);
 9646   format %{ "orl     $dst, $src\t# int" %}
 9647   ins_encode %{
 9648     __ orl($dst$$Address, $src$$Register);
 9649   %}
 9650   ins_pipe(ialu_mem_reg);
 9651 %}
 9652 
 9653 // Or Memory with Immediate
 9654 instruct orI_mem_imm(memory dst, immI src, rFlagsReg cr)
 9655 %{
 9656   match(Set dst (StoreI dst (OrI (LoadI dst) src)));
 9657   effect(KILL cr);
 9658 
 9659   ins_cost(125);
 9660   format %{ "orl     $dst, $src\t# int" %}
 9661   ins_encode %{
 9662     __ orl($dst$$Address, $src$$constant);
 9663   %}
 9664   ins_pipe(ialu_mem_imm);
 9665 %}
 9666 
 9667 // Xor Instructions
 9668 // Xor Register with Register
 9669 instruct xorI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
 9670 %{
 9671   match(Set dst (XorI dst src));
 9672   effect(KILL cr);
 9673 
 9674   format %{ "xorl    $dst, $src\t# int" %}
 9675   ins_encode %{
 9676     __ xorl($dst$$Register, $src$$Register);
 9677   %}
 9678   ins_pipe(ialu_reg_reg);
 9679 %}
 9680 
 9681 // Xor Register with Immediate -1
 9682 instruct xorI_rReg_im1(rRegI dst, immI_M1 imm) %{
 9683   match(Set dst (XorI dst imm));
 9684 
 9685   format %{ "not    $dst" %}
 9686   ins_encode %{
 9687      __ notl($dst$$Register);
 9688   %}
 9689   ins_pipe(ialu_reg);
 9690 %}
 9691 
 9692 // Xor Register with Immediate
 9693 instruct xorI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
 9694 %{
 9695   match(Set dst (XorI dst src));
 9696   effect(KILL cr);
 9697 
 9698   format %{ "xorl    $dst, $src\t# int" %}
 9699   ins_encode %{
 9700     __ xorl($dst$$Register, $src$$constant);
 9701   %}
 9702   ins_pipe(ialu_reg);
 9703 %}
 9704 
 9705 // Xor Register with Memory
 9706 instruct xorI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
 9707 %{
 9708   match(Set dst (XorI dst (LoadI src)));
 9709   effect(KILL cr);
 9710 
 9711   ins_cost(125);
 9712   format %{ "xorl    $dst, $src\t# int" %}
 9713   ins_encode %{
 9714     __ xorl($dst$$Register, $src$$Address);
 9715   %}
 9716   ins_pipe(ialu_reg_mem);
 9717 %}
 9718 
 9719 // Xor Memory with Register
 9720 instruct xorB_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
 9721 %{
 9722   match(Set dst (StoreB dst (XorI (LoadB dst) src)));
 9723   effect(KILL cr);
 9724 
 9725   ins_cost(150);
 9726   format %{ "xorb    $dst, $src\t# byte" %}
 9727   ins_encode %{
 9728     __ xorb($dst$$Address, $src$$Register);
 9729   %}
 9730   ins_pipe(ialu_mem_reg);
 9731 %}
 9732 
 9733 instruct xorI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
 9734 %{
 9735   match(Set dst (StoreI dst (XorI (LoadI dst) src)));
 9736   effect(KILL cr);
 9737 
 9738   ins_cost(150);
 9739   format %{ "xorl    $dst, $src\t# int" %}
 9740   ins_encode %{
 9741     __ xorl($dst$$Address, $src$$Register);
 9742   %}
 9743   ins_pipe(ialu_mem_reg);
 9744 %}
 9745 
 9746 // Xor Memory with Immediate
 9747 instruct xorI_mem_imm(memory dst, immI src, rFlagsReg cr)
 9748 %{
 9749   match(Set dst (StoreI dst (XorI (LoadI dst) src)));
 9750   effect(KILL cr);
 9751 
 9752   ins_cost(125);
 9753   format %{ "xorl    $dst, $src\t# int" %}
 9754   ins_encode %{
 9755     __ xorl($dst$$Address, $src$$constant);
 9756   %}
 9757   ins_pipe(ialu_mem_imm);
 9758 %}
 9759 
 9760 
 9761 // Long Logical Instructions
 9762 
 9763 // And Instructions
 9764 // And Register with Register
 9765 instruct andL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
 9766 %{
 9767   match(Set dst (AndL dst src));
 9768   effect(KILL cr);
 9769 
 9770   format %{ "andq    $dst, $src\t# long" %}
 9771   ins_encode %{
 9772     __ andq($dst$$Register, $src$$Register);
 9773   %}
 9774   ins_pipe(ialu_reg_reg);
 9775 %}
 9776 
 9777 // And Register with Immediate 255
 9778 instruct andL_rReg_imm255(rRegL dst, immL_255 src)
 9779 %{
 9780   match(Set dst (AndL dst src));
 9781 
 9782   format %{ "movzbq  $dst, $dst\t# long & 0xFF" %}
 9783   ins_encode %{
 9784     __ movzbq($dst$$Register, $dst$$Register);
 9785   %}
 9786   ins_pipe(ialu_reg);
 9787 %}
 9788 
 9789 // And Register with Immediate 65535
 9790 instruct andL_rReg_imm65535(rRegL dst, immL_65535 src)
 9791 %{
 9792   match(Set dst (AndL dst src));
 9793 
 9794   format %{ "movzwq  $dst, $dst\t# long & 0xFFFF" %}
 9795   ins_encode %{
 9796     __ movzwq($dst$$Register, $dst$$Register);
 9797   %}
 9798   ins_pipe(ialu_reg);
 9799 %}
 9800 
 9801 // And Register with Immediate
 9802 instruct andL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
 9803 %{
 9804   match(Set dst (AndL dst src));
 9805   effect(KILL cr);
 9806 
 9807   format %{ "andq    $dst, $src\t# long" %}
 9808   ins_encode %{
 9809     __ andq($dst$$Register, $src$$constant);
 9810   %}
 9811   ins_pipe(ialu_reg);
 9812 %}
 9813 
 9814 // And Register with Memory
 9815 instruct andL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
 9816 %{
 9817   match(Set dst (AndL dst (LoadL src)));
 9818   effect(KILL cr);
 9819 
 9820   ins_cost(125);
 9821   format %{ "andq    $dst, $src\t# long" %}
 9822   ins_encode %{
 9823     __ andq($dst$$Register, $src$$Address);
 9824   %}
 9825   ins_pipe(ialu_reg_mem);
 9826 %}
 9827 
 9828 // And Memory with Register
 9829 instruct andL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
 9830 %{
 9831   match(Set dst (StoreL dst (AndL (LoadL dst) src)));
 9832   effect(KILL cr);
 9833 
 9834   ins_cost(150);
 9835   format %{ "andq    $dst, $src\t# long" %}
 9836   ins_encode %{
 9837     __ andq($dst$$Address, $src$$Register);
 9838   %}
 9839   ins_pipe(ialu_mem_reg);
 9840 %}
 9841 
 9842 // And Memory with Immediate
 9843 instruct andL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
 9844 %{
 9845   match(Set dst (StoreL dst (AndL (LoadL dst) src)));
 9846   effect(KILL cr);
 9847 
 9848   ins_cost(125);
 9849   format %{ "andq    $dst, $src\t# long" %}
 9850   ins_encode %{
 9851     __ andq($dst$$Address, $src$$constant);
 9852   %}
 9853   ins_pipe(ialu_mem_imm);
 9854 %}
 9855 
 9856 instruct btrL_mem_imm(memory dst, immL_NotPow2 con, rFlagsReg cr)
 9857 %{
 9858   // con should be a pure 64-bit immediate given that not(con) is a power of 2
 9859   // because AND/OR works well enough for 8/32-bit values.
 9860   predicate(log2i_graceful(~n->in(3)->in(2)->get_long()) > 30);
 9861 
 9862   match(Set dst (StoreL dst (AndL (LoadL dst) con)));
 9863   effect(KILL cr);
 9864 
 9865   ins_cost(125);
 9866   format %{ "btrq    $dst, log2(not($con))\t# long" %}
 9867   ins_encode %{
 9868     __ btrq($dst$$Address, log2i_exact((julong)~$con$$constant));
 9869   %}
 9870   ins_pipe(ialu_mem_imm);
 9871 %}
 9872 
 9873 // BMI1 instructions
 9874 instruct andnL_rReg_rReg_mem(rRegL dst, rRegL src1, memory src2, immL_M1 minus_1, rFlagsReg cr) %{
 9875   match(Set dst (AndL (XorL src1 minus_1) (LoadL src2)));
 9876   predicate(UseBMI1Instructions);
 9877   effect(KILL cr);
 9878 
 9879   ins_cost(125);
 9880   format %{ "andnq  $dst, $src1, $src2" %}
 9881 
 9882   ins_encode %{
 9883     __ andnq($dst$$Register, $src1$$Register, $src2$$Address);
 9884   %}
 9885   ins_pipe(ialu_reg_mem);
 9886 %}
 9887 
 9888 instruct andnL_rReg_rReg_rReg(rRegL dst, rRegL src1, rRegL src2, immL_M1 minus_1, rFlagsReg cr) %{
 9889   match(Set dst (AndL (XorL src1 minus_1) src2));
 9890   predicate(UseBMI1Instructions);
 9891   effect(KILL cr);
 9892 
 9893   format %{ "andnq  $dst, $src1, $src2" %}
 9894 
 9895   ins_encode %{
 9896   __ andnq($dst$$Register, $src1$$Register, $src2$$Register);
 9897   %}
 9898   ins_pipe(ialu_reg_mem);
 9899 %}
 9900 
 9901 instruct blsiL_rReg_rReg(rRegL dst, rRegL src, immL0 imm_zero, rFlagsReg cr) %{
 9902   match(Set dst (AndL (SubL imm_zero src) src));
 9903   predicate(UseBMI1Instructions);
 9904   effect(KILL cr);
 9905 
 9906   format %{ "blsiq  $dst, $src" %}
 9907 
 9908   ins_encode %{
 9909     __ blsiq($dst$$Register, $src$$Register);
 9910   %}
 9911   ins_pipe(ialu_reg);
 9912 %}
 9913 
 9914 instruct blsiL_rReg_mem(rRegL dst, memory src, immL0 imm_zero, rFlagsReg cr) %{
 9915   match(Set dst (AndL (SubL imm_zero (LoadL src) ) (LoadL src) ));
 9916   predicate(UseBMI1Instructions);
 9917   effect(KILL cr);
 9918 
 9919   ins_cost(125);
 9920   format %{ "blsiq  $dst, $src" %}
 9921 
 9922   ins_encode %{
 9923     __ blsiq($dst$$Register, $src$$Address);
 9924   %}
 9925   ins_pipe(ialu_reg_mem);
 9926 %}
 9927 
 9928 instruct blsmskL_rReg_mem(rRegL dst, memory src, immL_M1 minus_1, rFlagsReg cr)
 9929 %{
 9930   match(Set dst (XorL (AddL (LoadL src) minus_1) (LoadL src) ) );
 9931   predicate(UseBMI1Instructions);
 9932   effect(KILL cr);
 9933 
 9934   ins_cost(125);
 9935   format %{ "blsmskq $dst, $src" %}
 9936 
 9937   ins_encode %{
 9938     __ blsmskq($dst$$Register, $src$$Address);
 9939   %}
 9940   ins_pipe(ialu_reg_mem);
 9941 %}
 9942 
 9943 instruct blsmskL_rReg_rReg(rRegL dst, rRegL src, immL_M1 minus_1, rFlagsReg cr)
 9944 %{
 9945   match(Set dst (XorL (AddL src minus_1) src));
 9946   predicate(UseBMI1Instructions);
 9947   effect(KILL cr);
 9948 
 9949   format %{ "blsmskq $dst, $src" %}
 9950 
 9951   ins_encode %{
 9952     __ blsmskq($dst$$Register, $src$$Register);
 9953   %}
 9954 
 9955   ins_pipe(ialu_reg);
 9956 %}
 9957 
 9958 instruct blsrL_rReg_rReg(rRegL dst, rRegL src, immL_M1 minus_1, rFlagsReg cr)
 9959 %{
 9960   match(Set dst (AndL (AddL src minus_1) src) );
 9961   predicate(UseBMI1Instructions);
 9962   effect(KILL cr);
 9963 
 9964   format %{ "blsrq  $dst, $src" %}
 9965 
 9966   ins_encode %{
 9967     __ blsrq($dst$$Register, $src$$Register);
 9968   %}
 9969 
 9970   ins_pipe(ialu_reg);
 9971 %}
 9972 
 9973 instruct blsrL_rReg_mem(rRegL dst, memory src, immL_M1 minus_1, rFlagsReg cr)
 9974 %{
 9975   match(Set dst (AndL (AddL (LoadL src) minus_1) (LoadL src)) );
 9976   predicate(UseBMI1Instructions);
 9977   effect(KILL cr);
 9978 
 9979   ins_cost(125);
 9980   format %{ "blsrq  $dst, $src" %}
 9981 
 9982   ins_encode %{
 9983     __ blsrq($dst$$Register, $src$$Address);
 9984   %}
 9985 
 9986   ins_pipe(ialu_reg);
 9987 %}
 9988 
 9989 // Or Instructions
 9990 // Or Register with Register
 9991 instruct orL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
 9992 %{
 9993   match(Set dst (OrL dst src));
 9994   effect(KILL cr);
 9995 
 9996   format %{ "orq     $dst, $src\t# long" %}
 9997   ins_encode %{
 9998     __ orq($dst$$Register, $src$$Register);
 9999   %}
10000   ins_pipe(ialu_reg_reg);
10001 %}
10002 
10003 // Use any_RegP to match R15 (TLS register) without spilling.
10004 instruct orL_rReg_castP2X(rRegL dst, any_RegP src, rFlagsReg cr) %{
10005   match(Set dst (OrL dst (CastP2X src)));
10006   effect(KILL cr);
10007 
10008   format %{ "orq     $dst, $src\t# long" %}
10009   ins_encode %{
10010     __ orq($dst$$Register, $src$$Register);
10011   %}
10012   ins_pipe(ialu_reg_reg);
10013 %}
10014 
10015 
10016 // Or Register with Immediate
10017 instruct orL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
10018 %{
10019   match(Set dst (OrL dst src));
10020   effect(KILL cr);
10021 
10022   format %{ "orq     $dst, $src\t# long" %}
10023   ins_encode %{
10024     __ orq($dst$$Register, $src$$constant);
10025   %}
10026   ins_pipe(ialu_reg);
10027 %}
10028 
10029 // Or Register with Memory
10030 instruct orL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
10031 %{
10032   match(Set dst (OrL dst (LoadL src)));
10033   effect(KILL cr);
10034 
10035   ins_cost(125);
10036   format %{ "orq     $dst, $src\t# long" %}
10037   ins_encode %{
10038     __ orq($dst$$Register, $src$$Address);
10039   %}
10040   ins_pipe(ialu_reg_mem);
10041 %}
10042 
10043 // Or Memory with Register
10044 instruct orL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
10045 %{
10046   match(Set dst (StoreL dst (OrL (LoadL dst) src)));
10047   effect(KILL cr);
10048 
10049   ins_cost(150);
10050   format %{ "orq     $dst, $src\t# long" %}
10051   ins_encode %{
10052     __ orq($dst$$Address, $src$$Register);
10053   %}
10054   ins_pipe(ialu_mem_reg);
10055 %}
10056 
10057 // Or Memory with Immediate
10058 instruct orL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
10059 %{
10060   match(Set dst (StoreL dst (OrL (LoadL dst) src)));
10061   effect(KILL cr);
10062 
10063   ins_cost(125);
10064   format %{ "orq     $dst, $src\t# long" %}
10065   ins_encode %{
10066     __ orq($dst$$Address, $src$$constant);
10067   %}
10068   ins_pipe(ialu_mem_imm);
10069 %}
10070 
10071 instruct btsL_mem_imm(memory dst, immL_Pow2 con, rFlagsReg cr)
10072 %{
10073   // con should be a pure 64-bit power of 2 immediate
10074   // because AND/OR works well enough for 8/32-bit values.
10075   predicate(log2i_graceful(n->in(3)->in(2)->get_long()) > 31);
10076 
10077   match(Set dst (StoreL dst (OrL (LoadL dst) con)));
10078   effect(KILL cr);
10079 
10080   ins_cost(125);
10081   format %{ "btsq    $dst, log2($con)\t# long" %}
10082   ins_encode %{
10083     __ btsq($dst$$Address, log2i_exact((julong)$con$$constant));
10084   %}
10085   ins_pipe(ialu_mem_imm);
10086 %}
10087 
10088 // Xor Instructions
10089 // Xor Register with Register
10090 instruct xorL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
10091 %{
10092   match(Set dst (XorL dst src));
10093   effect(KILL cr);
10094 
10095   format %{ "xorq    $dst, $src\t# long" %}
10096   ins_encode %{
10097     __ xorq($dst$$Register, $src$$Register);
10098   %}
10099   ins_pipe(ialu_reg_reg);
10100 %}
10101 
10102 // Xor Register with Immediate -1
10103 instruct xorL_rReg_im1(rRegL dst, immL_M1 imm) %{
10104   match(Set dst (XorL dst imm));
10105 
10106   format %{ "notq   $dst" %}
10107   ins_encode %{
10108      __ notq($dst$$Register);
10109   %}
10110   ins_pipe(ialu_reg);
10111 %}
10112 
10113 // Xor Register with Immediate
10114 instruct xorL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
10115 %{
10116   match(Set dst (XorL dst src));
10117   effect(KILL cr);
10118 
10119   format %{ "xorq    $dst, $src\t# long" %}
10120   ins_encode %{
10121     __ xorq($dst$$Register, $src$$constant);
10122   %}
10123   ins_pipe(ialu_reg);
10124 %}
10125 
10126 // Xor Register with Memory
10127 instruct xorL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
10128 %{
10129   match(Set dst (XorL dst (LoadL src)));
10130   effect(KILL cr);
10131 
10132   ins_cost(125);
10133   format %{ "xorq    $dst, $src\t# long" %}
10134   ins_encode %{
10135     __ xorq($dst$$Register, $src$$Address);
10136   %}
10137   ins_pipe(ialu_reg_mem);
10138 %}
10139 
10140 // Xor Memory with Register
10141 instruct xorL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
10142 %{
10143   match(Set dst (StoreL dst (XorL (LoadL dst) src)));
10144   effect(KILL cr);
10145 
10146   ins_cost(150);
10147   format %{ "xorq    $dst, $src\t# long" %}
10148   ins_encode %{
10149     __ xorq($dst$$Address, $src$$Register);
10150   %}
10151   ins_pipe(ialu_mem_reg);
10152 %}
10153 
10154 // Xor Memory with Immediate
10155 instruct xorL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
10156 %{
10157   match(Set dst (StoreL dst (XorL (LoadL dst) src)));
10158   effect(KILL cr);
10159 
10160   ins_cost(125);
10161   format %{ "xorq    $dst, $src\t# long" %}
10162   ins_encode %{
10163     __ xorq($dst$$Address, $src$$constant);
10164   %}
10165   ins_pipe(ialu_mem_imm);
10166 %}
10167 
10168 // Convert Int to Boolean
10169 instruct convI2B(rRegI dst, rRegI src, rFlagsReg cr)
10170 %{
10171   match(Set dst (Conv2B src));
10172   effect(KILL cr);
10173 
10174   format %{ "testl   $src, $src\t# ci2b\n\t"
10175             "setnz   $dst\n\t"
10176             "movzbl  $dst, $dst" %}
10177   ins_encode %{
10178     __ testl($src$$Register, $src$$Register);
10179     __ set_byte_if_not_zero($dst$$Register);
10180     __ movzbl($dst$$Register, $dst$$Register);
10181   %}
10182   ins_pipe(pipe_slow); // XXX
10183 %}
10184 
10185 // Convert Pointer to Boolean
10186 instruct convP2B(rRegI dst, rRegP src, rFlagsReg cr)
10187 %{
10188   match(Set dst (Conv2B src));
10189   effect(KILL cr);
10190 
10191   format %{ "testq   $src, $src\t# cp2b\n\t"
10192             "setnz   $dst\n\t"
10193             "movzbl  $dst, $dst" %}
10194   ins_encode %{
10195     __ testq($src$$Register, $src$$Register);
10196     __ set_byte_if_not_zero($dst$$Register);
10197     __ movzbl($dst$$Register, $dst$$Register);
10198   %}
10199   ins_pipe(pipe_slow); // XXX
10200 %}
10201 
10202 instruct cmpLTMask(rRegI dst, rRegI p, rRegI q, rFlagsReg cr)
10203 %{
10204   match(Set dst (CmpLTMask p q));
10205   effect(KILL cr);
10206 
10207   ins_cost(400);
10208   format %{ "cmpl    $p, $q\t# cmpLTMask\n\t"
10209             "setlt   $dst\n\t"
10210             "movzbl  $dst, $dst\n\t"
10211             "negl    $dst" %}
10212   ins_encode %{
10213     __ cmpl($p$$Register, $q$$Register);
10214     __ setl($dst$$Register);
10215     __ movzbl($dst$$Register, $dst$$Register);
10216     __ negl($dst$$Register);
10217   %}
10218   ins_pipe(pipe_slow);
10219 %}
10220 
10221 instruct cmpLTMask0(rRegI dst, immI_0 zero, rFlagsReg cr)
10222 %{
10223   match(Set dst (CmpLTMask dst zero));
10224   effect(KILL cr);
10225 
10226   ins_cost(100);
10227   format %{ "sarl    $dst, #31\t# cmpLTMask0" %}
10228   ins_encode %{
10229     __ sarl($dst$$Register, 31);
10230   %}
10231   ins_pipe(ialu_reg);
10232 %}
10233 
10234 /* Better to save a register than avoid a branch */
10235 instruct cadd_cmpLTMask(rRegI p, rRegI q, rRegI y, rFlagsReg cr)
10236 %{
10237   match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
10238   effect(KILL cr);
10239   ins_cost(300);
10240   format %{ "subl    $p,$q\t# cadd_cmpLTMask\n\t"
10241             "jge     done\n\t"
10242             "addl    $p,$y\n"
10243             "done:   " %}
10244   ins_encode %{
10245     Register Rp = $p$$Register;
10246     Register Rq = $q$$Register;
10247     Register Ry = $y$$Register;
10248     Label done;
10249     __ subl(Rp, Rq);
10250     __ jccb(Assembler::greaterEqual, done);
10251     __ addl(Rp, Ry);
10252     __ bind(done);
10253   %}
10254   ins_pipe(pipe_cmplt);
10255 %}
10256 
10257 /* Better to save a register than avoid a branch */
10258 instruct and_cmpLTMask(rRegI p, rRegI q, rRegI y, rFlagsReg cr)
10259 %{
10260   match(Set y (AndI (CmpLTMask p q) y));
10261   effect(KILL cr);
10262 
10263   ins_cost(300);
10264 
10265   format %{ "cmpl    $p, $q\t# and_cmpLTMask\n\t"
10266             "jlt     done\n\t"
10267             "xorl    $y, $y\n"
10268             "done:   " %}
10269   ins_encode %{
10270     Register Rp = $p$$Register;
10271     Register Rq = $q$$Register;
10272     Register Ry = $y$$Register;
10273     Label done;
10274     __ cmpl(Rp, Rq);
10275     __ jccb(Assembler::less, done);
10276     __ xorl(Ry, Ry);
10277     __ bind(done);
10278   %}
10279   ins_pipe(pipe_cmplt);
10280 %}
10281 
10282 
10283 //---------- FP Instructions------------------------------------------------
10284 
10285 instruct cmpF_cc_reg(rFlagsRegU cr, regF src1, regF src2)
10286 %{
10287   match(Set cr (CmpF src1 src2));
10288 
10289   ins_cost(145);
10290   format %{ "ucomiss $src1, $src2\n\t"
10291             "jnp,s   exit\n\t"
10292             "pushfq\t# saw NaN, set CF\n\t"
10293             "andq    [rsp], #0xffffff2b\n\t"
10294             "popfq\n"
10295     "exit:" %}
10296   ins_encode %{
10297     __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10298     emit_cmpfp_fixup(_masm);
10299   %}
10300   ins_pipe(pipe_slow);
10301 %}
10302 
10303 instruct cmpF_cc_reg_CF(rFlagsRegUCF cr, regF src1, regF src2) %{
10304   match(Set cr (CmpF src1 src2));
10305 
10306   ins_cost(100);
10307   format %{ "ucomiss $src1, $src2" %}
10308   ins_encode %{
10309     __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10310   %}
10311   ins_pipe(pipe_slow);
10312 %}
10313 
10314 instruct cmpF_cc_mem(rFlagsRegU cr, regF src1, memory src2)
10315 %{
10316   match(Set cr (CmpF src1 (LoadF src2)));
10317 
10318   ins_cost(145);
10319   format %{ "ucomiss $src1, $src2\n\t"
10320             "jnp,s   exit\n\t"
10321             "pushfq\t# saw NaN, set CF\n\t"
10322             "andq    [rsp], #0xffffff2b\n\t"
10323             "popfq\n"
10324     "exit:" %}
10325   ins_encode %{
10326     __ ucomiss($src1$$XMMRegister, $src2$$Address);
10327     emit_cmpfp_fixup(_masm);
10328   %}
10329   ins_pipe(pipe_slow);
10330 %}
10331 
10332 instruct cmpF_cc_memCF(rFlagsRegUCF cr, regF src1, memory src2) %{
10333   match(Set cr (CmpF src1 (LoadF src2)));
10334 
10335   ins_cost(100);
10336   format %{ "ucomiss $src1, $src2" %}
10337   ins_encode %{
10338     __ ucomiss($src1$$XMMRegister, $src2$$Address);
10339   %}
10340   ins_pipe(pipe_slow);
10341 %}
10342 
10343 instruct cmpF_cc_imm(rFlagsRegU cr, regF src, immF con) %{
10344   match(Set cr (CmpF src con));
10345 
10346   ins_cost(145);
10347   format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con\n\t"
10348             "jnp,s   exit\n\t"
10349             "pushfq\t# saw NaN, set CF\n\t"
10350             "andq    [rsp], #0xffffff2b\n\t"
10351             "popfq\n"
10352     "exit:" %}
10353   ins_encode %{
10354     __ ucomiss($src$$XMMRegister, $constantaddress($con));
10355     emit_cmpfp_fixup(_masm);
10356   %}
10357   ins_pipe(pipe_slow);
10358 %}
10359 
10360 instruct cmpF_cc_immCF(rFlagsRegUCF cr, regF src, immF con) %{
10361   match(Set cr (CmpF src con));
10362   ins_cost(100);
10363   format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con" %}
10364   ins_encode %{
10365     __ ucomiss($src$$XMMRegister, $constantaddress($con));
10366   %}
10367   ins_pipe(pipe_slow);
10368 %}
10369 
10370 instruct cmpD_cc_reg(rFlagsRegU cr, regD src1, regD src2)
10371 %{
10372   match(Set cr (CmpD src1 src2));
10373 
10374   ins_cost(145);
10375   format %{ "ucomisd $src1, $src2\n\t"
10376             "jnp,s   exit\n\t"
10377             "pushfq\t# saw NaN, set CF\n\t"
10378             "andq    [rsp], #0xffffff2b\n\t"
10379             "popfq\n"
10380     "exit:" %}
10381   ins_encode %{
10382     __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
10383     emit_cmpfp_fixup(_masm);
10384   %}
10385   ins_pipe(pipe_slow);
10386 %}
10387 
10388 instruct cmpD_cc_reg_CF(rFlagsRegUCF cr, regD src1, regD src2) %{
10389   match(Set cr (CmpD src1 src2));
10390 
10391   ins_cost(100);
10392   format %{ "ucomisd $src1, $src2 test" %}
10393   ins_encode %{
10394     __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
10395   %}
10396   ins_pipe(pipe_slow);
10397 %}
10398 
10399 instruct cmpD_cc_mem(rFlagsRegU cr, regD src1, memory src2)
10400 %{
10401   match(Set cr (CmpD src1 (LoadD src2)));
10402 
10403   ins_cost(145);
10404   format %{ "ucomisd $src1, $src2\n\t"
10405             "jnp,s   exit\n\t"
10406             "pushfq\t# saw NaN, set CF\n\t"
10407             "andq    [rsp], #0xffffff2b\n\t"
10408             "popfq\n"
10409     "exit:" %}
10410   ins_encode %{
10411     __ ucomisd($src1$$XMMRegister, $src2$$Address);
10412     emit_cmpfp_fixup(_masm);
10413   %}
10414   ins_pipe(pipe_slow);
10415 %}
10416 
10417 instruct cmpD_cc_memCF(rFlagsRegUCF cr, regD src1, memory src2) %{
10418   match(Set cr (CmpD src1 (LoadD src2)));
10419 
10420   ins_cost(100);
10421   format %{ "ucomisd $src1, $src2" %}
10422   ins_encode %{
10423     __ ucomisd($src1$$XMMRegister, $src2$$Address);
10424   %}
10425   ins_pipe(pipe_slow);
10426 %}
10427 
10428 instruct cmpD_cc_imm(rFlagsRegU cr, regD src, immD con) %{
10429   match(Set cr (CmpD src con));
10430 
10431   ins_cost(145);
10432   format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con\n\t"
10433             "jnp,s   exit\n\t"
10434             "pushfq\t# saw NaN, set CF\n\t"
10435             "andq    [rsp], #0xffffff2b\n\t"
10436             "popfq\n"
10437     "exit:" %}
10438   ins_encode %{
10439     __ ucomisd($src$$XMMRegister, $constantaddress($con));
10440     emit_cmpfp_fixup(_masm);
10441   %}
10442   ins_pipe(pipe_slow);
10443 %}
10444 
10445 instruct cmpD_cc_immCF(rFlagsRegUCF cr, regD src, immD con) %{
10446   match(Set cr (CmpD src con));
10447   ins_cost(100);
10448   format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con" %}
10449   ins_encode %{
10450     __ ucomisd($src$$XMMRegister, $constantaddress($con));
10451   %}
10452   ins_pipe(pipe_slow);
10453 %}
10454 
10455 // Compare into -1,0,1
10456 instruct cmpF_reg(rRegI dst, regF src1, regF src2, rFlagsReg cr)
10457 %{
10458   match(Set dst (CmpF3 src1 src2));
10459   effect(KILL cr);
10460 
10461   ins_cost(275);
10462   format %{ "ucomiss $src1, $src2\n\t"
10463             "movl    $dst, #-1\n\t"
10464             "jp,s    done\n\t"
10465             "jb,s    done\n\t"
10466             "setne   $dst\n\t"
10467             "movzbl  $dst, $dst\n"
10468     "done:" %}
10469   ins_encode %{
10470     __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10471     emit_cmpfp3(_masm, $dst$$Register);
10472   %}
10473   ins_pipe(pipe_slow);
10474 %}
10475 
10476 // Compare into -1,0,1
10477 instruct cmpF_mem(rRegI dst, regF src1, memory src2, rFlagsReg cr)
10478 %{
10479   match(Set dst (CmpF3 src1 (LoadF src2)));
10480   effect(KILL cr);
10481 
10482   ins_cost(275);
10483   format %{ "ucomiss $src1, $src2\n\t"
10484             "movl    $dst, #-1\n\t"
10485             "jp,s    done\n\t"
10486             "jb,s    done\n\t"
10487             "setne   $dst\n\t"
10488             "movzbl  $dst, $dst\n"
10489     "done:" %}
10490   ins_encode %{
10491     __ ucomiss($src1$$XMMRegister, $src2$$Address);
10492     emit_cmpfp3(_masm, $dst$$Register);
10493   %}
10494   ins_pipe(pipe_slow);
10495 %}
10496 
10497 // Compare into -1,0,1
10498 instruct cmpF_imm(rRegI dst, regF src, immF con, rFlagsReg cr) %{
10499   match(Set dst (CmpF3 src con));
10500   effect(KILL cr);
10501 
10502   ins_cost(275);
10503   format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con\n\t"
10504             "movl    $dst, #-1\n\t"
10505             "jp,s    done\n\t"
10506             "jb,s    done\n\t"
10507             "setne   $dst\n\t"
10508             "movzbl  $dst, $dst\n"
10509     "done:" %}
10510   ins_encode %{
10511     __ ucomiss($src$$XMMRegister, $constantaddress($con));
10512     emit_cmpfp3(_masm, $dst$$Register);
10513   %}
10514   ins_pipe(pipe_slow);
10515 %}
10516 
10517 // Compare into -1,0,1
10518 instruct cmpD_reg(rRegI dst, regD src1, regD src2, rFlagsReg cr)
10519 %{
10520   match(Set dst (CmpD3 src1 src2));
10521   effect(KILL cr);
10522 
10523   ins_cost(275);
10524   format %{ "ucomisd $src1, $src2\n\t"
10525             "movl    $dst, #-1\n\t"
10526             "jp,s    done\n\t"
10527             "jb,s    done\n\t"
10528             "setne   $dst\n\t"
10529             "movzbl  $dst, $dst\n"
10530     "done:" %}
10531   ins_encode %{
10532     __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
10533     emit_cmpfp3(_masm, $dst$$Register);
10534   %}
10535   ins_pipe(pipe_slow);
10536 %}
10537 
10538 // Compare into -1,0,1
10539 instruct cmpD_mem(rRegI dst, regD src1, memory src2, rFlagsReg cr)
10540 %{
10541   match(Set dst (CmpD3 src1 (LoadD src2)));
10542   effect(KILL cr);
10543 
10544   ins_cost(275);
10545   format %{ "ucomisd $src1, $src2\n\t"
10546             "movl    $dst, #-1\n\t"
10547             "jp,s    done\n\t"
10548             "jb,s    done\n\t"
10549             "setne   $dst\n\t"
10550             "movzbl  $dst, $dst\n"
10551     "done:" %}
10552   ins_encode %{
10553     __ ucomisd($src1$$XMMRegister, $src2$$Address);
10554     emit_cmpfp3(_masm, $dst$$Register);
10555   %}
10556   ins_pipe(pipe_slow);
10557 %}
10558 
10559 // Compare into -1,0,1
10560 instruct cmpD_imm(rRegI dst, regD src, immD con, rFlagsReg cr) %{
10561   match(Set dst (CmpD3 src con));
10562   effect(KILL cr);
10563 
10564   ins_cost(275);
10565   format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con\n\t"
10566             "movl    $dst, #-1\n\t"
10567             "jp,s    done\n\t"
10568             "jb,s    done\n\t"
10569             "setne   $dst\n\t"
10570             "movzbl  $dst, $dst\n"
10571     "done:" %}
10572   ins_encode %{
10573     __ ucomisd($src$$XMMRegister, $constantaddress($con));
10574     emit_cmpfp3(_masm, $dst$$Register);
10575   %}
10576   ins_pipe(pipe_slow);
10577 %}
10578 
10579 //----------Arithmetic Conversion Instructions---------------------------------
10580 
10581 instruct convF2D_reg_reg(regD dst, regF src)
10582 %{
10583   match(Set dst (ConvF2D src));
10584 
10585   format %{ "cvtss2sd $dst, $src" %}
10586   ins_encode %{
10587     __ cvtss2sd ($dst$$XMMRegister, $src$$XMMRegister);
10588   %}
10589   ins_pipe(pipe_slow); // XXX
10590 %}
10591 
10592 instruct convF2D_reg_mem(regD dst, memory src)
10593 %{
10594   match(Set dst (ConvF2D (LoadF src)));
10595 
10596   format %{ "cvtss2sd $dst, $src" %}
10597   ins_encode %{
10598     __ cvtss2sd ($dst$$XMMRegister, $src$$Address);
10599   %}
10600   ins_pipe(pipe_slow); // XXX
10601 %}
10602 
10603 instruct convD2F_reg_reg(regF dst, regD src)
10604 %{
10605   match(Set dst (ConvD2F src));
10606 
10607   format %{ "cvtsd2ss $dst, $src" %}
10608   ins_encode %{
10609     __ cvtsd2ss ($dst$$XMMRegister, $src$$XMMRegister);
10610   %}
10611   ins_pipe(pipe_slow); // XXX
10612 %}
10613 
10614 instruct convD2F_reg_mem(regF dst, memory src)
10615 %{
10616   match(Set dst (ConvD2F (LoadD src)));
10617 
10618   format %{ "cvtsd2ss $dst, $src" %}
10619   ins_encode %{
10620     __ cvtsd2ss ($dst$$XMMRegister, $src$$Address);
10621   %}
10622   ins_pipe(pipe_slow); // XXX
10623 %}
10624 
10625 // XXX do mem variants
10626 instruct convF2I_reg_reg(rRegI dst, regF src, rFlagsReg cr)
10627 %{
10628   match(Set dst (ConvF2I src));
10629   effect(KILL cr);
10630   format %{ "convert_f2i $dst,$src" %}
10631   ins_encode %{
10632     __ convert_f2i($dst$$Register, $src$$XMMRegister);
10633   %}
10634   ins_pipe(pipe_slow);
10635 %}
10636 
10637 instruct convF2L_reg_reg(rRegL dst, regF src, rFlagsReg cr)
10638 %{
10639   match(Set dst (ConvF2L src));
10640   effect(KILL cr);
10641   format %{ "convert_f2l $dst,$src"%}
10642   ins_encode %{
10643     __ convert_f2l($dst$$Register, $src$$XMMRegister);
10644   %}
10645   ins_pipe(pipe_slow);
10646 %}
10647 
10648 instruct convD2I_reg_reg(rRegI dst, regD src, rFlagsReg cr)
10649 %{
10650   match(Set dst (ConvD2I src));
10651   effect(KILL cr);
10652   format %{ "convert_d2i $dst,$src"%}
10653   ins_encode %{
10654     __ convert_d2i($dst$$Register, $src$$XMMRegister);
10655   %}
10656   ins_pipe(pipe_slow);
10657 %}
10658 
10659 instruct convD2L_reg_reg(rRegL dst, regD src, rFlagsReg cr)
10660 %{
10661   match(Set dst (ConvD2L src));
10662   effect(KILL cr);
10663   format %{ "convert_d2l $dst,$src"%}
10664   ins_encode %{
10665     __ convert_d2l($dst$$Register, $src$$XMMRegister);
10666   %}
10667   ins_pipe(pipe_slow);
10668 %}
10669 
10670 instruct convI2F_reg_reg(regF dst, rRegI src)
10671 %{
10672   predicate(!UseXmmI2F);
10673   match(Set dst (ConvI2F src));
10674 
10675   format %{ "cvtsi2ssl $dst, $src\t# i2f" %}
10676   ins_encode %{
10677     __ cvtsi2ssl ($dst$$XMMRegister, $src$$Register);
10678   %}
10679   ins_pipe(pipe_slow); // XXX
10680 %}
10681 
10682 instruct convI2F_reg_mem(regF dst, memory src)
10683 %{
10684   match(Set dst (ConvI2F (LoadI src)));
10685 
10686   format %{ "cvtsi2ssl $dst, $src\t# i2f" %}
10687   ins_encode %{
10688     __ cvtsi2ssl ($dst$$XMMRegister, $src$$Address);
10689   %}
10690   ins_pipe(pipe_slow); // XXX
10691 %}
10692 
10693 instruct convI2D_reg_reg(regD dst, rRegI src)
10694 %{
10695   predicate(!UseXmmI2D);
10696   match(Set dst (ConvI2D src));
10697 
10698   format %{ "cvtsi2sdl $dst, $src\t# i2d" %}
10699   ins_encode %{
10700     __ cvtsi2sdl ($dst$$XMMRegister, $src$$Register);
10701   %}
10702   ins_pipe(pipe_slow); // XXX
10703 %}
10704 
10705 instruct convI2D_reg_mem(regD dst, memory src)
10706 %{
10707   match(Set dst (ConvI2D (LoadI src)));
10708 
10709   format %{ "cvtsi2sdl $dst, $src\t# i2d" %}
10710   ins_encode %{
10711     __ cvtsi2sdl ($dst$$XMMRegister, $src$$Address);
10712   %}
10713   ins_pipe(pipe_slow); // XXX
10714 %}
10715 
10716 instruct convXI2F_reg(regF dst, rRegI src)
10717 %{
10718   predicate(UseXmmI2F);
10719   match(Set dst (ConvI2F src));
10720 
10721   format %{ "movdl $dst, $src\n\t"
10722             "cvtdq2psl $dst, $dst\t# i2f" %}
10723   ins_encode %{
10724     __ movdl($dst$$XMMRegister, $src$$Register);
10725     __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister);
10726   %}
10727   ins_pipe(pipe_slow); // XXX
10728 %}
10729 
10730 instruct convXI2D_reg(regD dst, rRegI src)
10731 %{
10732   predicate(UseXmmI2D);
10733   match(Set dst (ConvI2D src));
10734 
10735   format %{ "movdl $dst, $src\n\t"
10736             "cvtdq2pdl $dst, $dst\t# i2d" %}
10737   ins_encode %{
10738     __ movdl($dst$$XMMRegister, $src$$Register);
10739     __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister);
10740   %}
10741   ins_pipe(pipe_slow); // XXX
10742 %}
10743 
10744 instruct convL2F_reg_reg(regF dst, rRegL src)
10745 %{
10746   match(Set dst (ConvL2F src));
10747 
10748   format %{ "cvtsi2ssq $dst, $src\t# l2f" %}
10749   ins_encode %{
10750     __ cvtsi2ssq ($dst$$XMMRegister, $src$$Register);
10751   %}
10752   ins_pipe(pipe_slow); // XXX
10753 %}
10754 
10755 instruct convL2F_reg_mem(regF dst, memory src)
10756 %{
10757   match(Set dst (ConvL2F (LoadL src)));
10758 
10759   format %{ "cvtsi2ssq $dst, $src\t# l2f" %}
10760   ins_encode %{
10761     __ cvtsi2ssq ($dst$$XMMRegister, $src$$Address);
10762   %}
10763   ins_pipe(pipe_slow); // XXX
10764 %}
10765 
10766 instruct convL2D_reg_reg(regD dst, rRegL src)
10767 %{
10768   match(Set dst (ConvL2D src));
10769 
10770   format %{ "cvtsi2sdq $dst, $src\t# l2d" %}
10771   ins_encode %{
10772     __ cvtsi2sdq ($dst$$XMMRegister, $src$$Register);
10773   %}
10774   ins_pipe(pipe_slow); // XXX
10775 %}
10776 
10777 instruct convL2D_reg_mem(regD dst, memory src)
10778 %{
10779   match(Set dst (ConvL2D (LoadL src)));
10780 
10781   format %{ "cvtsi2sdq $dst, $src\t# l2d" %}
10782   ins_encode %{
10783     __ cvtsi2sdq ($dst$$XMMRegister, $src$$Address);
10784   %}
10785   ins_pipe(pipe_slow); // XXX
10786 %}
10787 
10788 instruct convI2L_reg_reg(rRegL dst, rRegI src)
10789 %{
10790   match(Set dst (ConvI2L src));
10791 
10792   ins_cost(125);
10793   format %{ "movslq  $dst, $src\t# i2l" %}
10794   ins_encode %{
10795     __ movslq($dst$$Register, $src$$Register);
10796   %}
10797   ins_pipe(ialu_reg_reg);
10798 %}
10799 
10800 // instruct convI2L_reg_reg_foo(rRegL dst, rRegI src)
10801 // %{
10802 //   match(Set dst (ConvI2L src));
10803 // //   predicate(_kids[0]->_leaf->as_Type()->type()->is_int()->_lo >= 0 &&
10804 // //             _kids[0]->_leaf->as_Type()->type()->is_int()->_hi >= 0);
10805 //   predicate(((const TypeNode*) n)->type()->is_long()->_hi ==
10806 //             (unsigned int) ((const TypeNode*) n)->type()->is_long()->_hi &&
10807 //             ((const TypeNode*) n)->type()->is_long()->_lo ==
10808 //             (unsigned int) ((const TypeNode*) n)->type()->is_long()->_lo);
10809 
10810 //   format %{ "movl    $dst, $src\t# unsigned i2l" %}
10811 //   ins_encode(enc_copy(dst, src));
10812 // //   opcode(0x63); // needs REX.W
10813 // //   ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst,src));
10814 //   ins_pipe(ialu_reg_reg);
10815 // %}
10816 
10817 // Zero-extend convert int to long
10818 instruct convI2L_reg_reg_zex(rRegL dst, rRegI src, immL_32bits mask)
10819 %{
10820   match(Set dst (AndL (ConvI2L src) mask));
10821 
10822   format %{ "movl    $dst, $src\t# i2l zero-extend\n\t" %}
10823   ins_encode %{
10824     if ($dst$$reg != $src$$reg) {
10825       __ movl($dst$$Register, $src$$Register);
10826     }
10827   %}
10828   ins_pipe(ialu_reg_reg);
10829 %}
10830 
10831 // Zero-extend convert int to long
10832 instruct convI2L_reg_mem_zex(rRegL dst, memory src, immL_32bits mask)
10833 %{
10834   match(Set dst (AndL (ConvI2L (LoadI src)) mask));
10835 
10836   format %{ "movl    $dst, $src\t# i2l zero-extend\n\t" %}
10837   ins_encode %{
10838     __ movl($dst$$Register, $src$$Address);
10839   %}
10840   ins_pipe(ialu_reg_mem);
10841 %}
10842 
10843 instruct zerox_long_reg_reg(rRegL dst, rRegL src, immL_32bits mask)
10844 %{
10845   match(Set dst (AndL src mask));
10846 
10847   format %{ "movl    $dst, $src\t# zero-extend long" %}
10848   ins_encode %{
10849     __ movl($dst$$Register, $src$$Register);
10850   %}
10851   ins_pipe(ialu_reg_reg);
10852 %}
10853 
10854 instruct convL2I_reg_reg(rRegI dst, rRegL src)
10855 %{
10856   match(Set dst (ConvL2I src));
10857 
10858   format %{ "movl    $dst, $src\t# l2i" %}
10859   ins_encode %{
10860     __ movl($dst$$Register, $src$$Register);
10861   %}
10862   ins_pipe(ialu_reg_reg);
10863 %}
10864 
10865 
10866 instruct MoveF2I_stack_reg(rRegI dst, stackSlotF src) %{
10867   match(Set dst (MoveF2I src));
10868   effect(DEF dst, USE src);
10869 
10870   ins_cost(125);
10871   format %{ "movl    $dst, $src\t# MoveF2I_stack_reg" %}
10872   ins_encode %{
10873     __ movl($dst$$Register, Address(rsp, $src$$disp));
10874   %}
10875   ins_pipe(ialu_reg_mem);
10876 %}
10877 
10878 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
10879   match(Set dst (MoveI2F src));
10880   effect(DEF dst, USE src);
10881 
10882   ins_cost(125);
10883   format %{ "movss   $dst, $src\t# MoveI2F_stack_reg" %}
10884   ins_encode %{
10885     __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
10886   %}
10887   ins_pipe(pipe_slow);
10888 %}
10889 
10890 instruct MoveD2L_stack_reg(rRegL dst, stackSlotD src) %{
10891   match(Set dst (MoveD2L src));
10892   effect(DEF dst, USE src);
10893 
10894   ins_cost(125);
10895   format %{ "movq    $dst, $src\t# MoveD2L_stack_reg" %}
10896   ins_encode %{
10897     __ movq($dst$$Register, Address(rsp, $src$$disp));
10898   %}
10899   ins_pipe(ialu_reg_mem);
10900 %}
10901 
10902 instruct MoveL2D_stack_reg_partial(regD dst, stackSlotL src) %{
10903   predicate(!UseXmmLoadAndClearUpper);
10904   match(Set dst (MoveL2D src));
10905   effect(DEF dst, USE src);
10906 
10907   ins_cost(125);
10908   format %{ "movlpd  $dst, $src\t# MoveL2D_stack_reg" %}
10909   ins_encode %{
10910     __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
10911   %}
10912   ins_pipe(pipe_slow);
10913 %}
10914 
10915 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
10916   predicate(UseXmmLoadAndClearUpper);
10917   match(Set dst (MoveL2D src));
10918   effect(DEF dst, USE src);
10919 
10920   ins_cost(125);
10921   format %{ "movsd   $dst, $src\t# MoveL2D_stack_reg" %}
10922   ins_encode %{
10923     __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
10924   %}
10925   ins_pipe(pipe_slow);
10926 %}
10927 
10928 
10929 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
10930   match(Set dst (MoveF2I src));
10931   effect(DEF dst, USE src);
10932 
10933   ins_cost(95); // XXX
10934   format %{ "movss   $dst, $src\t# MoveF2I_reg_stack" %}
10935   ins_encode %{
10936     __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
10937   %}
10938   ins_pipe(pipe_slow);
10939 %}
10940 
10941 instruct MoveI2F_reg_stack(stackSlotF dst, rRegI src) %{
10942   match(Set dst (MoveI2F src));
10943   effect(DEF dst, USE src);
10944 
10945   ins_cost(100);
10946   format %{ "movl    $dst, $src\t# MoveI2F_reg_stack" %}
10947   ins_encode %{
10948     __ movl(Address(rsp, $dst$$disp), $src$$Register);
10949   %}
10950   ins_pipe( ialu_mem_reg );
10951 %}
10952 
10953 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
10954   match(Set dst (MoveD2L src));
10955   effect(DEF dst, USE src);
10956 
10957   ins_cost(95); // XXX
10958   format %{ "movsd   $dst, $src\t# MoveL2D_reg_stack" %}
10959   ins_encode %{
10960     __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
10961   %}
10962   ins_pipe(pipe_slow);
10963 %}
10964 
10965 instruct MoveL2D_reg_stack(stackSlotD dst, rRegL src) %{
10966   match(Set dst (MoveL2D src));
10967   effect(DEF dst, USE src);
10968 
10969   ins_cost(100);
10970   format %{ "movq    $dst, $src\t# MoveL2D_reg_stack" %}
10971   ins_encode %{
10972     __ movq(Address(rsp, $dst$$disp), $src$$Register);
10973   %}
10974   ins_pipe(ialu_mem_reg);
10975 %}
10976 
10977 instruct MoveF2I_reg_reg(rRegI dst, regF src) %{
10978   match(Set dst (MoveF2I src));
10979   effect(DEF dst, USE src);
10980   ins_cost(85);
10981   format %{ "movd    $dst,$src\t# MoveF2I" %}
10982   ins_encode %{
10983     __ movdl($dst$$Register, $src$$XMMRegister);
10984   %}
10985   ins_pipe( pipe_slow );
10986 %}
10987 
10988 instruct MoveD2L_reg_reg(rRegL dst, regD src) %{
10989   match(Set dst (MoveD2L src));
10990   effect(DEF dst, USE src);
10991   ins_cost(85);
10992   format %{ "movd    $dst,$src\t# MoveD2L" %}
10993   ins_encode %{
10994     __ movdq($dst$$Register, $src$$XMMRegister);
10995   %}
10996   ins_pipe( pipe_slow );
10997 %}
10998 
10999 instruct MoveI2F_reg_reg(regF dst, rRegI src) %{
11000   match(Set dst (MoveI2F src));
11001   effect(DEF dst, USE src);
11002   ins_cost(100);
11003   format %{ "movd    $dst,$src\t# MoveI2F" %}
11004   ins_encode %{
11005     __ movdl($dst$$XMMRegister, $src$$Register);
11006   %}
11007   ins_pipe( pipe_slow );
11008 %}
11009 
11010 instruct MoveL2D_reg_reg(regD dst, rRegL src) %{
11011   match(Set dst (MoveL2D src));
11012   effect(DEF dst, USE src);
11013   ins_cost(100);
11014   format %{ "movd    $dst,$src\t# MoveL2D" %}
11015   ins_encode %{
11016      __ movdq($dst$$XMMRegister, $src$$Register);
11017   %}
11018   ins_pipe( pipe_slow );
11019 %}
11020 
11021 // Fast clearing of an array
11022 // Small ClearArray non-AVX512.
11023 instruct rep_stos(rcx_RegL cnt, rdi_RegP base, regD tmp, rax_RegI zero,
11024                   Universe dummy, rFlagsReg cr)
11025 %{
11026   predicate(!((ClearArrayNode*)n)->is_large() && (UseAVX <= 2));
11027   match(Set dummy (ClearArray cnt base));
11028   effect(USE_KILL cnt, USE_KILL base, TEMP tmp, KILL zero, KILL cr);
11029 
11030   format %{ $$template
11031     $$emit$$"xorq    rax, rax\t# ClearArray:\n\t"
11032     $$emit$$"cmp     InitArrayShortSize,rcx\n\t"
11033     $$emit$$"jg      LARGE\n\t"
11034     $$emit$$"dec     rcx\n\t"
11035     $$emit$$"js      DONE\t# Zero length\n\t"
11036     $$emit$$"mov     rax,(rdi,rcx,8)\t# LOOP\n\t"
11037     $$emit$$"dec     rcx\n\t"
11038     $$emit$$"jge     LOOP\n\t"
11039     $$emit$$"jmp     DONE\n\t"
11040     $$emit$$"# LARGE:\n\t"
11041     if (UseFastStosb) {
11042        $$emit$$"shlq    rcx,3\t# Convert doublewords to bytes\n\t"
11043        $$emit$$"rep     stosb\t# Store rax to *rdi++ while rcx--\n\t"
11044     } else if (UseXMMForObjInit) {
11045        $$emit$$"mov     rdi,rax\n\t"
11046        $$emit$$"vpxor   ymm0,ymm0,ymm0\n\t"
11047        $$emit$$"jmpq    L_zero_64_bytes\n\t"
11048        $$emit$$"# L_loop:\t# 64-byte LOOP\n\t"
11049        $$emit$$"vmovdqu ymm0,(rax)\n\t"
11050        $$emit$$"vmovdqu ymm0,0x20(rax)\n\t"
11051        $$emit$$"add     0x40,rax\n\t"
11052        $$emit$$"# L_zero_64_bytes:\n\t"
11053        $$emit$$"sub     0x8,rcx\n\t"
11054        $$emit$$"jge     L_loop\n\t"
11055        $$emit$$"add     0x4,rcx\n\t"
11056        $$emit$$"jl      L_tail\n\t"
11057        $$emit$$"vmovdqu ymm0,(rax)\n\t"
11058        $$emit$$"add     0x20,rax\n\t"
11059        $$emit$$"sub     0x4,rcx\n\t"
11060        $$emit$$"# L_tail:\t# Clearing tail bytes\n\t"
11061        $$emit$$"add     0x4,rcx\n\t"
11062        $$emit$$"jle     L_end\n\t"
11063        $$emit$$"dec     rcx\n\t"
11064        $$emit$$"# L_sloop:\t# 8-byte short loop\n\t"
11065        $$emit$$"vmovq   xmm0,(rax)\n\t"
11066        $$emit$$"add     0x8,rax\n\t"
11067        $$emit$$"dec     rcx\n\t"
11068        $$emit$$"jge     L_sloop\n\t"
11069        $$emit$$"# L_end:\n\t"
11070     } else {
11071        $$emit$$"rep     stosq\t# Store rax to *rdi++ while rcx--\n\t"
11072     }
11073     $$emit$$"# DONE"
11074   %}
11075   ins_encode %{
11076     __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register,
11077                  $tmp$$XMMRegister, false, knoreg);
11078   %}
11079   ins_pipe(pipe_slow);
11080 %}
11081 
11082 // Small ClearArray AVX512 non-constant length.
11083 instruct rep_stos_evex(rcx_RegL cnt, rdi_RegP base, legRegD tmp, kReg ktmp, rax_RegI zero,
11084                        Universe dummy, rFlagsReg cr)
11085 %{
11086   predicate(!((ClearArrayNode*)n)->is_large() && (UseAVX > 2));
11087   match(Set dummy (ClearArray cnt base));
11088   ins_cost(125);
11089   effect(USE_KILL cnt, USE_KILL base, TEMP tmp, TEMP ktmp, KILL zero, KILL cr);
11090 
11091   format %{ $$template
11092     $$emit$$"xorq    rax, rax\t# ClearArray:\n\t"
11093     $$emit$$"cmp     InitArrayShortSize,rcx\n\t"
11094     $$emit$$"jg      LARGE\n\t"
11095     $$emit$$"dec     rcx\n\t"
11096     $$emit$$"js      DONE\t# Zero length\n\t"
11097     $$emit$$"mov     rax,(rdi,rcx,8)\t# LOOP\n\t"
11098     $$emit$$"dec     rcx\n\t"
11099     $$emit$$"jge     LOOP\n\t"
11100     $$emit$$"jmp     DONE\n\t"
11101     $$emit$$"# LARGE:\n\t"
11102     if (UseFastStosb) {
11103        $$emit$$"shlq    rcx,3\t# Convert doublewords to bytes\n\t"
11104        $$emit$$"rep     stosb\t# Store rax to *rdi++ while rcx--\n\t"
11105     } else if (UseXMMForObjInit) {
11106        $$emit$$"mov     rdi,rax\n\t"
11107        $$emit$$"vpxor   ymm0,ymm0,ymm0\n\t"
11108        $$emit$$"jmpq    L_zero_64_bytes\n\t"
11109        $$emit$$"# L_loop:\t# 64-byte LOOP\n\t"
11110        $$emit$$"vmovdqu ymm0,(rax)\n\t"
11111        $$emit$$"vmovdqu ymm0,0x20(rax)\n\t"
11112        $$emit$$"add     0x40,rax\n\t"
11113        $$emit$$"# L_zero_64_bytes:\n\t"
11114        $$emit$$"sub     0x8,rcx\n\t"
11115        $$emit$$"jge     L_loop\n\t"
11116        $$emit$$"add     0x4,rcx\n\t"
11117        $$emit$$"jl      L_tail\n\t"
11118        $$emit$$"vmovdqu ymm0,(rax)\n\t"
11119        $$emit$$"add     0x20,rax\n\t"
11120        $$emit$$"sub     0x4,rcx\n\t"
11121        $$emit$$"# L_tail:\t# Clearing tail bytes\n\t"
11122        $$emit$$"add     0x4,rcx\n\t"
11123        $$emit$$"jle     L_end\n\t"
11124        $$emit$$"dec     rcx\n\t"
11125        $$emit$$"# L_sloop:\t# 8-byte short loop\n\t"
11126        $$emit$$"vmovq   xmm0,(rax)\n\t"
11127        $$emit$$"add     0x8,rax\n\t"
11128        $$emit$$"dec     rcx\n\t"
11129        $$emit$$"jge     L_sloop\n\t"
11130        $$emit$$"# L_end:\n\t"
11131     } else {
11132        $$emit$$"rep     stosq\t# Store rax to *rdi++ while rcx--\n\t"
11133     }
11134     $$emit$$"# DONE"
11135   %}
11136   ins_encode %{
11137     __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register,
11138                  $tmp$$XMMRegister, false, $ktmp$$KRegister);
11139   %}
11140   ins_pipe(pipe_slow);
11141 %}
11142 
11143 // Large ClearArray non-AVX512.
11144 instruct rep_stos_large(rcx_RegL cnt, rdi_RegP base, regD tmp, rax_RegI zero,
11145                         Universe dummy, rFlagsReg cr)
11146 %{
11147   predicate((UseAVX <=2) && ((ClearArrayNode*)n)->is_large());
11148   match(Set dummy (ClearArray cnt base));
11149   effect(USE_KILL cnt, USE_KILL base, TEMP tmp, KILL zero, KILL cr);
11150 
11151   format %{ $$template
11152     if (UseFastStosb) {
11153        $$emit$$"xorq    rax, rax\t# ClearArray:\n\t"
11154        $$emit$$"shlq    rcx,3\t# Convert doublewords to bytes\n\t"
11155        $$emit$$"rep     stosb\t# Store rax to *rdi++ while rcx--"
11156     } else if (UseXMMForObjInit) {
11157        $$emit$$"mov     rdi,rax\t# ClearArray:\n\t"
11158        $$emit$$"vpxor   ymm0,ymm0,ymm0\n\t"
11159        $$emit$$"jmpq    L_zero_64_bytes\n\t"
11160        $$emit$$"# L_loop:\t# 64-byte LOOP\n\t"
11161        $$emit$$"vmovdqu ymm0,(rax)\n\t"
11162        $$emit$$"vmovdqu ymm0,0x20(rax)\n\t"
11163        $$emit$$"add     0x40,rax\n\t"
11164        $$emit$$"# L_zero_64_bytes:\n\t"
11165        $$emit$$"sub     0x8,rcx\n\t"
11166        $$emit$$"jge     L_loop\n\t"
11167        $$emit$$"add     0x4,rcx\n\t"
11168        $$emit$$"jl      L_tail\n\t"
11169        $$emit$$"vmovdqu ymm0,(rax)\n\t"
11170        $$emit$$"add     0x20,rax\n\t"
11171        $$emit$$"sub     0x4,rcx\n\t"
11172        $$emit$$"# L_tail:\t# Clearing tail bytes\n\t"
11173        $$emit$$"add     0x4,rcx\n\t"
11174        $$emit$$"jle     L_end\n\t"
11175        $$emit$$"dec     rcx\n\t"
11176        $$emit$$"# L_sloop:\t# 8-byte short loop\n\t"
11177        $$emit$$"vmovq   xmm0,(rax)\n\t"
11178        $$emit$$"add     0x8,rax\n\t"
11179        $$emit$$"dec     rcx\n\t"
11180        $$emit$$"jge     L_sloop\n\t"
11181        $$emit$$"# L_end:\n\t"
11182     } else {
11183        $$emit$$"xorq    rax, rax\t# ClearArray:\n\t"
11184        $$emit$$"rep     stosq\t# Store rax to *rdi++ while rcx--"
11185     }
11186   %}
11187   ins_encode %{
11188     __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register,
11189                  $tmp$$XMMRegister, true, knoreg);
11190   %}
11191   ins_pipe(pipe_slow);
11192 %}
11193 
11194 // Large ClearArray AVX512.
11195 instruct rep_stos_large_evex(rcx_RegL cnt, rdi_RegP base, legRegD tmp, kReg ktmp, rax_RegI zero,
11196                              Universe dummy, rFlagsReg cr)
11197 %{
11198   predicate((UseAVX > 2) && ((ClearArrayNode*)n)->is_large());
11199   match(Set dummy (ClearArray cnt base));
11200   effect(USE_KILL cnt, USE_KILL base, TEMP tmp, TEMP ktmp, KILL zero, KILL cr);
11201 
11202   format %{ $$template
11203     if (UseFastStosb) {
11204        $$emit$$"xorq    rax, rax\t# ClearArray:\n\t"
11205        $$emit$$"shlq    rcx,3\t# Convert doublewords to bytes\n\t"
11206        $$emit$$"rep     stosb\t# Store rax to *rdi++ while rcx--"
11207     } else if (UseXMMForObjInit) {
11208        $$emit$$"mov     rdi,rax\t# ClearArray:\n\t"
11209        $$emit$$"vpxor   ymm0,ymm0,ymm0\n\t"
11210        $$emit$$"jmpq    L_zero_64_bytes\n\t"
11211        $$emit$$"# L_loop:\t# 64-byte LOOP\n\t"
11212        $$emit$$"vmovdqu ymm0,(rax)\n\t"
11213        $$emit$$"vmovdqu ymm0,0x20(rax)\n\t"
11214        $$emit$$"add     0x40,rax\n\t"
11215        $$emit$$"# L_zero_64_bytes:\n\t"
11216        $$emit$$"sub     0x8,rcx\n\t"
11217        $$emit$$"jge     L_loop\n\t"
11218        $$emit$$"add     0x4,rcx\n\t"
11219        $$emit$$"jl      L_tail\n\t"
11220        $$emit$$"vmovdqu ymm0,(rax)\n\t"
11221        $$emit$$"add     0x20,rax\n\t"
11222        $$emit$$"sub     0x4,rcx\n\t"
11223        $$emit$$"# L_tail:\t# Clearing tail bytes\n\t"
11224        $$emit$$"add     0x4,rcx\n\t"
11225        $$emit$$"jle     L_end\n\t"
11226        $$emit$$"dec     rcx\n\t"
11227        $$emit$$"# L_sloop:\t# 8-byte short loop\n\t"
11228        $$emit$$"vmovq   xmm0,(rax)\n\t"
11229        $$emit$$"add     0x8,rax\n\t"
11230        $$emit$$"dec     rcx\n\t"
11231        $$emit$$"jge     L_sloop\n\t"
11232        $$emit$$"# L_end:\n\t"
11233     } else {
11234        $$emit$$"xorq    rax, rax\t# ClearArray:\n\t"
11235        $$emit$$"rep     stosq\t# Store rax to *rdi++ while rcx--"
11236     }
11237   %}
11238   ins_encode %{
11239     __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register,
11240                  $tmp$$XMMRegister, true, $ktmp$$KRegister);
11241   %}
11242   ins_pipe(pipe_slow);
11243 %}
11244 
11245 // Small ClearArray AVX512 constant length.
11246 instruct rep_stos_im(immL cnt, rRegP base, regD tmp, rRegI zero, kReg ktmp, Universe dummy, rFlagsReg cr)
11247 %{
11248   predicate(!((ClearArrayNode*)n)->is_large() &&
11249               ((UseAVX > 2) && VM_Version::supports_avx512vlbw()));
11250   match(Set dummy (ClearArray cnt base));
11251   ins_cost(100);
11252   effect(TEMP tmp, TEMP zero, TEMP ktmp, KILL cr);
11253   format %{ "clear_mem_imm $base , $cnt  \n\t" %}
11254   ins_encode %{
11255    __ clear_mem($base$$Register, $cnt$$constant, $zero$$Register, $tmp$$XMMRegister, $ktmp$$KRegister);
11256   %}
11257   ins_pipe(pipe_slow);
11258 %}
11259 
11260 instruct string_compareL(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
11261                          rax_RegI result, legRegD tmp1, rFlagsReg cr)
11262 %{
11263   predicate(!VM_Version::supports_avx512vlbw() && ((StrCompNode*)n)->encoding() == StrIntrinsicNode::LL);
11264   match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11265   effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11266 
11267   format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result   // KILL $tmp1" %}
11268   ins_encode %{
11269     __ string_compare($str1$$Register, $str2$$Register,
11270                       $cnt1$$Register, $cnt2$$Register, $result$$Register,
11271                       $tmp1$$XMMRegister, StrIntrinsicNode::LL, knoreg);
11272   %}
11273   ins_pipe( pipe_slow );
11274 %}
11275 
11276 instruct string_compareL_evex(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
11277                               rax_RegI result, legRegD tmp1, kReg ktmp, rFlagsReg cr)
11278 %{
11279   predicate(VM_Version::supports_avx512vlbw() && ((StrCompNode*)n)->encoding() == StrIntrinsicNode::LL);
11280   match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11281   effect(TEMP tmp1, TEMP ktmp, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11282 
11283   format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result   // KILL $tmp1" %}
11284   ins_encode %{
11285     __ string_compare($str1$$Register, $str2$$Register,
11286                       $cnt1$$Register, $cnt2$$Register, $result$$Register,
11287                       $tmp1$$XMMRegister, StrIntrinsicNode::LL, $ktmp$$KRegister);
11288   %}
11289   ins_pipe( pipe_slow );
11290 %}
11291 
11292 instruct string_compareU(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
11293                          rax_RegI result, legRegD tmp1, rFlagsReg cr)
11294 %{
11295   predicate(!VM_Version::supports_avx512vlbw() && ((StrCompNode*)n)->encoding() == StrIntrinsicNode::UU);
11296   match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11297   effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11298 
11299   format %{ "String Compare char[] $str1,$cnt1,$str2,$cnt2 -> $result   // KILL $tmp1" %}
11300   ins_encode %{
11301     __ string_compare($str1$$Register, $str2$$Register,
11302                       $cnt1$$Register, $cnt2$$Register, $result$$Register,
11303                       $tmp1$$XMMRegister, StrIntrinsicNode::UU, knoreg);
11304   %}
11305   ins_pipe( pipe_slow );
11306 %}
11307 
11308 instruct string_compareU_evex(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
11309                               rax_RegI result, legRegD tmp1, kReg ktmp, rFlagsReg cr)
11310 %{
11311   predicate(VM_Version::supports_avx512vlbw() && ((StrCompNode*)n)->encoding() == StrIntrinsicNode::UU);
11312   match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11313   effect(TEMP tmp1, TEMP ktmp, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11314 
11315   format %{ "String Compare char[] $str1,$cnt1,$str2,$cnt2 -> $result   // KILL $tmp1" %}
11316   ins_encode %{
11317     __ string_compare($str1$$Register, $str2$$Register,
11318                       $cnt1$$Register, $cnt2$$Register, $result$$Register,
11319                       $tmp1$$XMMRegister, StrIntrinsicNode::UU, $ktmp$$KRegister);
11320   %}
11321   ins_pipe( pipe_slow );
11322 %}
11323 
11324 instruct string_compareLU(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
11325                           rax_RegI result, legRegD tmp1, rFlagsReg cr)
11326 %{
11327   predicate(!VM_Version::supports_avx512vlbw() && ((StrCompNode*)n)->encoding() == StrIntrinsicNode::LU);
11328   match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11329   effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11330 
11331   format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result   // KILL $tmp1" %}
11332   ins_encode %{
11333     __ string_compare($str1$$Register, $str2$$Register,
11334                       $cnt1$$Register, $cnt2$$Register, $result$$Register,
11335                       $tmp1$$XMMRegister, StrIntrinsicNode::LU, knoreg);
11336   %}
11337   ins_pipe( pipe_slow );
11338 %}
11339 
11340 instruct string_compareLU_evex(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
11341                                rax_RegI result, legRegD tmp1, kReg ktmp, rFlagsReg cr)
11342 %{
11343   predicate(VM_Version::supports_avx512vlbw() && ((StrCompNode*)n)->encoding() == StrIntrinsicNode::LU);
11344   match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11345   effect(TEMP tmp1, TEMP ktmp, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11346 
11347   format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result   // KILL $tmp1" %}
11348   ins_encode %{
11349     __ string_compare($str1$$Register, $str2$$Register,
11350                       $cnt1$$Register, $cnt2$$Register, $result$$Register,
11351                       $tmp1$$XMMRegister, StrIntrinsicNode::LU, $ktmp$$KRegister);
11352   %}
11353   ins_pipe( pipe_slow );
11354 %}
11355 
11356 instruct string_compareUL(rsi_RegP str1, rdx_RegI cnt1, rdi_RegP str2, rcx_RegI cnt2,
11357                           rax_RegI result, legRegD tmp1, rFlagsReg cr)
11358 %{
11359   predicate(!VM_Version::supports_avx512vlbw() && ((StrCompNode*)n)->encoding() == StrIntrinsicNode::UL);
11360   match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11361   effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11362 
11363   format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result   // KILL $tmp1" %}
11364   ins_encode %{
11365     __ string_compare($str2$$Register, $str1$$Register,
11366                       $cnt2$$Register, $cnt1$$Register, $result$$Register,
11367                       $tmp1$$XMMRegister, StrIntrinsicNode::UL, knoreg);
11368   %}
11369   ins_pipe( pipe_slow );
11370 %}
11371 
11372 instruct string_compareUL_evex(rsi_RegP str1, rdx_RegI cnt1, rdi_RegP str2, rcx_RegI cnt2,
11373                                rax_RegI result, legRegD tmp1, kReg ktmp, rFlagsReg cr)
11374 %{
11375   predicate(VM_Version::supports_avx512vlbw() && ((StrCompNode*)n)->encoding() == StrIntrinsicNode::UL);
11376   match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11377   effect(TEMP tmp1, TEMP ktmp, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11378 
11379   format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result   // KILL $tmp1" %}
11380   ins_encode %{
11381     __ string_compare($str2$$Register, $str1$$Register,
11382                       $cnt2$$Register, $cnt1$$Register, $result$$Register,
11383                       $tmp1$$XMMRegister, StrIntrinsicNode::UL, $ktmp$$KRegister);
11384   %}
11385   ins_pipe( pipe_slow );
11386 %}
11387 
11388 // fast search of substring with known size.
11389 instruct string_indexof_conL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2,
11390                              rbx_RegI result, legRegD tmp_vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr)
11391 %{
11392   predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL));
11393   match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
11394   effect(TEMP tmp_vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
11395 
11396   format %{ "String IndexOf byte[] $str1,$cnt1,$str2,$int_cnt2 -> $result   // KILL $tmp_vec, $cnt1, $cnt2, $tmp" %}
11397   ins_encode %{
11398     int icnt2 = (int)$int_cnt2$$constant;
11399     if (icnt2 >= 16) {
11400       // IndexOf for constant substrings with size >= 16 elements
11401       // which don't need to be loaded through stack.
11402       __ string_indexofC8($str1$$Register, $str2$$Register,
11403                           $cnt1$$Register, $cnt2$$Register,
11404                           icnt2, $result$$Register,
11405                           $tmp_vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::LL);
11406     } else {
11407       // Small strings are loaded through stack if they cross page boundary.
11408       __ string_indexof($str1$$Register, $str2$$Register,
11409                         $cnt1$$Register, $cnt2$$Register,
11410                         icnt2, $result$$Register,
11411                         $tmp_vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::LL);
11412     }
11413   %}
11414   ins_pipe( pipe_slow );
11415 %}
11416 
11417 // fast search of substring with known size.
11418 instruct string_indexof_conU(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2,
11419                              rbx_RegI result, legRegD tmp_vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr)
11420 %{
11421   predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU));
11422   match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
11423   effect(TEMP tmp_vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
11424 
11425   format %{ "String IndexOf char[] $str1,$cnt1,$str2,$int_cnt2 -> $result   // KILL $tmp_vec, $cnt1, $cnt2, $tmp" %}
11426   ins_encode %{
11427     int icnt2 = (int)$int_cnt2$$constant;
11428     if (icnt2 >= 8) {
11429       // IndexOf for constant substrings with size >= 8 elements
11430       // which don't need to be loaded through stack.
11431       __ string_indexofC8($str1$$Register, $str2$$Register,
11432                           $cnt1$$Register, $cnt2$$Register,
11433                           icnt2, $result$$Register,
11434                           $tmp_vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UU);
11435     } else {
11436       // Small strings are loaded through stack if they cross page boundary.
11437       __ string_indexof($str1$$Register, $str2$$Register,
11438                         $cnt1$$Register, $cnt2$$Register,
11439                         icnt2, $result$$Register,
11440                         $tmp_vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UU);
11441     }
11442   %}
11443   ins_pipe( pipe_slow );
11444 %}
11445 
11446 // fast search of substring with known size.
11447 instruct string_indexof_conUL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2,
11448                               rbx_RegI result, legRegD tmp_vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr)
11449 %{
11450   predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL));
11451   match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
11452   effect(TEMP tmp_vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
11453 
11454   format %{ "String IndexOf char[] $str1,$cnt1,$str2,$int_cnt2 -> $result   // KILL $tmp_vec, $cnt1, $cnt2, $tmp" %}
11455   ins_encode %{
11456     int icnt2 = (int)$int_cnt2$$constant;
11457     if (icnt2 >= 8) {
11458       // IndexOf for constant substrings with size >= 8 elements
11459       // which don't need to be loaded through stack.
11460       __ string_indexofC8($str1$$Register, $str2$$Register,
11461                           $cnt1$$Register, $cnt2$$Register,
11462                           icnt2, $result$$Register,
11463                           $tmp_vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UL);
11464     } else {
11465       // Small strings are loaded through stack if they cross page boundary.
11466       __ string_indexof($str1$$Register, $str2$$Register,
11467                         $cnt1$$Register, $cnt2$$Register,
11468                         icnt2, $result$$Register,
11469                         $tmp_vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UL);
11470     }
11471   %}
11472   ins_pipe( pipe_slow );
11473 %}
11474 
11475 instruct string_indexofL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2,
11476                          rbx_RegI result, legRegD tmp_vec, rcx_RegI tmp, rFlagsReg cr)
11477 %{
11478   predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL));
11479   match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
11480   effect(TEMP tmp_vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
11481 
11482   format %{ "String IndexOf byte[] $str1,$cnt1,$str2,$cnt2 -> $result   // KILL all" %}
11483   ins_encode %{
11484     __ string_indexof($str1$$Register, $str2$$Register,
11485                       $cnt1$$Register, $cnt2$$Register,
11486                       (-1), $result$$Register,
11487                       $tmp_vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::LL);
11488   %}
11489   ins_pipe( pipe_slow );
11490 %}
11491 
11492 instruct string_indexofU(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2,
11493                          rbx_RegI result, legRegD tmp_vec, rcx_RegI tmp, rFlagsReg cr)
11494 %{
11495   predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU));
11496   match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
11497   effect(TEMP tmp_vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
11498 
11499   format %{ "String IndexOf char[] $str1,$cnt1,$str2,$cnt2 -> $result   // KILL all" %}
11500   ins_encode %{
11501     __ string_indexof($str1$$Register, $str2$$Register,
11502                       $cnt1$$Register, $cnt2$$Register,
11503                       (-1), $result$$Register,
11504                       $tmp_vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UU);
11505   %}
11506   ins_pipe( pipe_slow );
11507 %}
11508 
11509 instruct string_indexofUL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2,
11510                           rbx_RegI result, legRegD tmp_vec, rcx_RegI tmp, rFlagsReg cr)
11511 %{
11512   predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL));
11513   match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
11514   effect(TEMP tmp_vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
11515 
11516   format %{ "String IndexOf char[] $str1,$cnt1,$str2,$cnt2 -> $result   // KILL all" %}
11517   ins_encode %{
11518     __ string_indexof($str1$$Register, $str2$$Register,
11519                       $cnt1$$Register, $cnt2$$Register,
11520                       (-1), $result$$Register,
11521                       $tmp_vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UL);
11522   %}
11523   ins_pipe( pipe_slow );
11524 %}
11525 
11526 instruct string_indexof_char(rdi_RegP str1, rdx_RegI cnt1, rax_RegI ch,
11527                               rbx_RegI result, legRegD tmp_vec1, legRegD tmp_vec2, legRegD tmp_vec3, rcx_RegI tmp, rFlagsReg cr)
11528 %{
11529   predicate(UseSSE42Intrinsics && (((StrIndexOfCharNode*)n)->encoding() == StrIntrinsicNode::U));
11530   match(Set result (StrIndexOfChar (Binary str1 cnt1) ch));
11531   effect(TEMP tmp_vec1, TEMP tmp_vec2, TEMP tmp_vec3, USE_KILL str1, USE_KILL cnt1, USE_KILL ch, TEMP tmp, KILL cr);
11532   format %{ "StringUTF16 IndexOf char[] $str1,$cnt1,$ch -> $result   // KILL all" %}
11533   ins_encode %{
11534     __ string_indexof_char($str1$$Register, $cnt1$$Register, $ch$$Register, $result$$Register,
11535                            $tmp_vec1$$XMMRegister, $tmp_vec2$$XMMRegister, $tmp_vec3$$XMMRegister, $tmp$$Register);
11536   %}
11537   ins_pipe( pipe_slow );
11538 %}
11539 
11540 instruct stringL_indexof_char(rdi_RegP str1, rdx_RegI cnt1, rax_RegI ch,
11541                               rbx_RegI result, legRegD tmp_vec1, legRegD tmp_vec2, legRegD tmp_vec3, rcx_RegI tmp, rFlagsReg cr)
11542 %{
11543   predicate(UseSSE42Intrinsics && (((StrIndexOfCharNode*)n)->encoding() == StrIntrinsicNode::L));
11544   match(Set result (StrIndexOfChar (Binary str1 cnt1) ch));
11545   effect(TEMP tmp_vec1, TEMP tmp_vec2, TEMP tmp_vec3, USE_KILL str1, USE_KILL cnt1, USE_KILL ch, TEMP tmp, KILL cr);
11546   format %{ "StringLatin1 IndexOf char[] $str1,$cnt1,$ch -> $result   // KILL all" %}
11547   ins_encode %{
11548     __ stringL_indexof_char($str1$$Register, $cnt1$$Register, $ch$$Register, $result$$Register,
11549                            $tmp_vec1$$XMMRegister, $tmp_vec2$$XMMRegister, $tmp_vec3$$XMMRegister, $tmp$$Register);
11550   %}
11551   ins_pipe( pipe_slow );
11552 %}
11553 
11554 // fast string equals
11555 instruct string_equals(rdi_RegP str1, rsi_RegP str2, rcx_RegI cnt, rax_RegI result,
11556                        legRegD tmp1, legRegD tmp2, rbx_RegI tmp3, rFlagsReg cr)
11557 %{
11558   predicate(!VM_Version::supports_avx512vlbw());
11559   match(Set result (StrEquals (Binary str1 str2) cnt));
11560   effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr);
11561 
11562   format %{ "String Equals $str1,$str2,$cnt -> $result    // KILL $tmp1, $tmp2, $tmp3" %}
11563   ins_encode %{
11564     __ arrays_equals(false, $str1$$Register, $str2$$Register,
11565                      $cnt$$Register, $result$$Register, $tmp3$$Register,
11566                      $tmp1$$XMMRegister, $tmp2$$XMMRegister, false /* char */, knoreg);
11567   %}
11568   ins_pipe( pipe_slow );
11569 %}
11570 
11571 instruct string_equals_evex(rdi_RegP str1, rsi_RegP str2, rcx_RegI cnt, rax_RegI result,
11572                            legRegD tmp1, legRegD tmp2, kReg ktmp, rbx_RegI tmp3, rFlagsReg cr)
11573 %{
11574   predicate(VM_Version::supports_avx512vlbw());
11575   match(Set result (StrEquals (Binary str1 str2) cnt));
11576   effect(TEMP tmp1, TEMP tmp2, TEMP ktmp, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr);
11577 
11578   format %{ "String Equals $str1,$str2,$cnt -> $result    // KILL $tmp1, $tmp2, $tmp3" %}
11579   ins_encode %{
11580     __ arrays_equals(false, $str1$$Register, $str2$$Register,
11581                      $cnt$$Register, $result$$Register, $tmp3$$Register,
11582                      $tmp1$$XMMRegister, $tmp2$$XMMRegister, false /* char */, $ktmp$$KRegister);
11583   %}
11584   ins_pipe( pipe_slow );
11585 %}
11586 
11587 // fast array equals
11588 instruct array_equalsB(rdi_RegP ary1, rsi_RegP ary2, rax_RegI result,
11589                        legRegD tmp1, legRegD tmp2, rcx_RegI tmp3, rbx_RegI tmp4, rFlagsReg cr)
11590 %{
11591   predicate(!VM_Version::supports_avx512vlbw() && ((AryEqNode*)n)->encoding() == StrIntrinsicNode::LL);
11592   match(Set result (AryEq ary1 ary2));
11593   effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
11594 
11595   format %{ "Array Equals byte[] $ary1,$ary2 -> $result   // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
11596   ins_encode %{
11597     __ arrays_equals(true, $ary1$$Register, $ary2$$Register,
11598                      $tmp3$$Register, $result$$Register, $tmp4$$Register,
11599                      $tmp1$$XMMRegister, $tmp2$$XMMRegister, false /* char */, knoreg);
11600   %}
11601   ins_pipe( pipe_slow );
11602 %}
11603 
11604 instruct array_equalsB_evex(rdi_RegP ary1, rsi_RegP ary2, rax_RegI result,
11605                             legRegD tmp1, legRegD tmp2, kReg ktmp, rcx_RegI tmp3, rbx_RegI tmp4, rFlagsReg cr)
11606 %{
11607   predicate(VM_Version::supports_avx512vlbw() && ((AryEqNode*)n)->encoding() == StrIntrinsicNode::LL);
11608   match(Set result (AryEq ary1 ary2));
11609   effect(TEMP tmp1, TEMP tmp2, TEMP ktmp, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
11610 
11611   format %{ "Array Equals byte[] $ary1,$ary2 -> $result   // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
11612   ins_encode %{
11613     __ arrays_equals(true, $ary1$$Register, $ary2$$Register,
11614                      $tmp3$$Register, $result$$Register, $tmp4$$Register,
11615                      $tmp1$$XMMRegister, $tmp2$$XMMRegister, false /* char */, $ktmp$$KRegister);
11616   %}
11617   ins_pipe( pipe_slow );
11618 %}
11619 
11620 instruct array_equalsC(rdi_RegP ary1, rsi_RegP ary2, rax_RegI result,
11621                        legRegD tmp1, legRegD tmp2, rcx_RegI tmp3, rbx_RegI tmp4, rFlagsReg cr)
11622 %{
11623   predicate(!VM_Version::supports_avx512vlbw() && ((AryEqNode*)n)->encoding() == StrIntrinsicNode::UU);
11624   match(Set result (AryEq ary1 ary2));
11625   effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
11626 
11627   format %{ "Array Equals char[] $ary1,$ary2 -> $result   // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
11628   ins_encode %{
11629     __ arrays_equals(true, $ary1$$Register, $ary2$$Register,
11630                      $tmp3$$Register, $result$$Register, $tmp4$$Register,
11631                      $tmp1$$XMMRegister, $tmp2$$XMMRegister, true /* char */, knoreg);
11632   %}
11633   ins_pipe( pipe_slow );
11634 %}
11635 
11636 instruct array_equalsC_evex(rdi_RegP ary1, rsi_RegP ary2, rax_RegI result,
11637                             legRegD tmp1, legRegD tmp2, kReg ktmp, rcx_RegI tmp3, rbx_RegI tmp4, rFlagsReg cr)
11638 %{
11639   predicate(VM_Version::supports_avx512vlbw() && ((AryEqNode*)n)->encoding() == StrIntrinsicNode::UU);
11640   match(Set result (AryEq ary1 ary2));
11641   effect(TEMP tmp1, TEMP tmp2, TEMP ktmp, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
11642 
11643   format %{ "Array Equals char[] $ary1,$ary2 -> $result   // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
11644   ins_encode %{
11645     __ arrays_equals(true, $ary1$$Register, $ary2$$Register,
11646                      $tmp3$$Register, $result$$Register, $tmp4$$Register,
11647                      $tmp1$$XMMRegister, $tmp2$$XMMRegister, true /* char */, $ktmp$$KRegister);
11648   %}
11649   ins_pipe( pipe_slow );
11650 %}
11651 
11652 instruct has_negatives(rsi_RegP ary1, rcx_RegI len, rax_RegI result,
11653                        legRegD tmp1, legRegD tmp2, rbx_RegI tmp3, rFlagsReg cr,)
11654 %{
11655   predicate(!VM_Version::supports_avx512vlbw() || !VM_Version::supports_bmi2());
11656   match(Set result (HasNegatives ary1 len));
11657   effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL len, KILL tmp3, KILL cr);
11658 
11659   format %{ "has negatives byte[] $ary1,$len -> $result   // KILL $tmp1, $tmp2, $tmp3" %}
11660   ins_encode %{
11661     __ has_negatives($ary1$$Register, $len$$Register,
11662                      $result$$Register, $tmp3$$Register,
11663                      $tmp1$$XMMRegister, $tmp2$$XMMRegister, knoreg, knoreg);
11664   %}
11665   ins_pipe( pipe_slow );
11666 %}
11667 
11668 instruct has_negatives_evex(rsi_RegP ary1, rcx_RegI len, rax_RegI result,
11669                             legRegD tmp1, legRegD tmp2, kReg ktmp1, kReg ktmp2, rbx_RegI tmp3, rFlagsReg cr,)
11670 %{
11671   predicate(VM_Version::supports_avx512vlbw() && VM_Version::supports_bmi2());
11672   match(Set result (HasNegatives ary1 len));
11673   effect(TEMP tmp1, TEMP tmp2, TEMP ktmp1, TEMP ktmp2, USE_KILL ary1, USE_KILL len, KILL tmp3, KILL cr);
11674 
11675   format %{ "has negatives byte[] $ary1,$len -> $result   // KILL $tmp1, $tmp2, $tmp3" %}
11676   ins_encode %{
11677     __ has_negatives($ary1$$Register, $len$$Register,
11678                      $result$$Register, $tmp3$$Register,
11679                      $tmp1$$XMMRegister, $tmp2$$XMMRegister, $ktmp1$$KRegister, $ktmp2$$KRegister);
11680   %}
11681   ins_pipe( pipe_slow );
11682 %}
11683 
11684 // fast char[] to byte[] compression
11685 instruct string_compress(rsi_RegP src, rdi_RegP dst, rdx_RegI len, legRegD tmp1, legRegD tmp2, legRegD tmp3,
11686                          legRegD tmp4, rcx_RegI tmp5, rax_RegI result, rFlagsReg cr) %{
11687   predicate(!VM_Version::supports_avx512vlbw() || !VM_Version::supports_bmi2());
11688   match(Set result (StrCompressedCopy src (Binary dst len)));
11689   effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst,
11690          USE_KILL len, KILL tmp5, KILL cr);
11691 
11692   format %{ "String Compress $src,$dst -> $result    // KILL RAX, RCX, RDX" %}
11693   ins_encode %{
11694     __ char_array_compress($src$$Register, $dst$$Register, $len$$Register,
11695                            $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
11696                            $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register,
11697                            knoreg, knoreg);
11698   %}
11699   ins_pipe( pipe_slow );
11700 %}
11701 
11702 instruct string_compress_evex(rsi_RegP src, rdi_RegP dst, rdx_RegI len, legRegD tmp1, legRegD tmp2, legRegD tmp3,
11703                               legRegD tmp4, kReg ktmp1, kReg ktmp2, rcx_RegI tmp5, rax_RegI result, rFlagsReg cr) %{
11704   predicate(VM_Version::supports_avx512vlbw() && VM_Version::supports_bmi2());
11705   match(Set result (StrCompressedCopy src (Binary dst len)));
11706   effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP ktmp1, TEMP ktmp2, USE_KILL src, USE_KILL dst,
11707          USE_KILL len, KILL tmp5, KILL cr);
11708 
11709   format %{ "String Compress $src,$dst -> $result    // KILL RAX, RCX, RDX" %}
11710   ins_encode %{
11711     __ char_array_compress($src$$Register, $dst$$Register, $len$$Register,
11712                            $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
11713                            $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register,
11714                            $ktmp1$$KRegister, $ktmp2$$KRegister);
11715   %}
11716   ins_pipe( pipe_slow );
11717 %}
11718 // fast byte[] to char[] inflation
11719 instruct string_inflate(Universe dummy, rsi_RegP src, rdi_RegP dst, rdx_RegI len,
11720                         legRegD tmp1, rcx_RegI tmp2, rFlagsReg cr) %{
11721   predicate(!VM_Version::supports_avx512vlbw() || !VM_Version::supports_bmi2());
11722   match(Set dummy (StrInflatedCopy src (Binary dst len)));
11723   effect(TEMP tmp1, TEMP tmp2, USE_KILL src, USE_KILL dst, USE_KILL len, KILL cr);
11724 
11725   format %{ "String Inflate $src,$dst    // KILL $tmp1, $tmp2" %}
11726   ins_encode %{
11727     __ byte_array_inflate($src$$Register, $dst$$Register, $len$$Register,
11728                           $tmp1$$XMMRegister, $tmp2$$Register, knoreg);
11729   %}
11730   ins_pipe( pipe_slow );
11731 %}
11732 
11733 instruct string_inflate_evex(Universe dummy, rsi_RegP src, rdi_RegP dst, rdx_RegI len,
11734                              legRegD tmp1, kReg ktmp, rcx_RegI tmp2, rFlagsReg cr) %{
11735   predicate(VM_Version::supports_avx512vlbw() && VM_Version::supports_bmi2());
11736   match(Set dummy (StrInflatedCopy src (Binary dst len)));
11737   effect(TEMP tmp1, TEMP tmp2, TEMP ktmp, USE_KILL src, USE_KILL dst, USE_KILL len, KILL cr);
11738 
11739   format %{ "String Inflate $src,$dst    // KILL $tmp1, $tmp2" %}
11740   ins_encode %{
11741     __ byte_array_inflate($src$$Register, $dst$$Register, $len$$Register,
11742                           $tmp1$$XMMRegister, $tmp2$$Register, $ktmp$$KRegister);
11743   %}
11744   ins_pipe( pipe_slow );
11745 %}
11746 
11747 // encode char[] to byte[] in ISO_8859_1
11748 instruct encode_iso_array(rsi_RegP src, rdi_RegP dst, rdx_RegI len,
11749                           legRegD tmp1, legRegD tmp2, legRegD tmp3, legRegD tmp4,
11750                           rcx_RegI tmp5, rax_RegI result, rFlagsReg cr) %{
11751   predicate(!((EncodeISOArrayNode*)n)->is_ascii());
11752   match(Set result (EncodeISOArray src (Binary dst len)));
11753   effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL tmp5, KILL cr);
11754 
11755   format %{ "Encode iso array $src,$dst,$len -> $result    // KILL RCX, RDX, $tmp1, $tmp2, $tmp3, $tmp4, RSI, RDI " %}
11756   ins_encode %{
11757     __ encode_iso_array($src$$Register, $dst$$Register, $len$$Register,
11758                         $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
11759                         $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register, false);
11760   %}
11761   ins_pipe( pipe_slow );
11762 %}
11763 
11764 // encode char[] to byte[] in ASCII
11765 instruct encode_ascii_array(rsi_RegP src, rdi_RegP dst, rdx_RegI len,
11766                             legRegD tmp1, legRegD tmp2, legRegD tmp3, legRegD tmp4,
11767                             rcx_RegI tmp5, rax_RegI result, rFlagsReg cr) %{
11768   predicate(((EncodeISOArrayNode*)n)->is_ascii());
11769   match(Set result (EncodeISOArray src (Binary dst len)));
11770   effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL tmp5, KILL cr);
11771 
11772   format %{ "Encode ascii array $src,$dst,$len -> $result    // KILL RCX, RDX, $tmp1, $tmp2, $tmp3, $tmp4, RSI, RDI " %}
11773   ins_encode %{
11774     __ encode_iso_array($src$$Register, $dst$$Register, $len$$Register,
11775                         $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
11776                         $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register, true);
11777   %}
11778   ins_pipe( pipe_slow );
11779 %}
11780 
11781 //----------Overflow Math Instructions-----------------------------------------
11782 
11783 instruct overflowAddI_rReg(rFlagsReg cr, rax_RegI op1, rRegI op2)
11784 %{
11785   match(Set cr (OverflowAddI op1 op2));
11786   effect(DEF cr, USE_KILL op1, USE op2);
11787 
11788   format %{ "addl    $op1, $op2\t# overflow check int" %}
11789 
11790   ins_encode %{
11791     __ addl($op1$$Register, $op2$$Register);
11792   %}
11793   ins_pipe(ialu_reg_reg);
11794 %}
11795 
11796 instruct overflowAddI_rReg_imm(rFlagsReg cr, rax_RegI op1, immI op2)
11797 %{
11798   match(Set cr (OverflowAddI op1 op2));
11799   effect(DEF cr, USE_KILL op1, USE op2);
11800 
11801   format %{ "addl    $op1, $op2\t# overflow check int" %}
11802 
11803   ins_encode %{
11804     __ addl($op1$$Register, $op2$$constant);
11805   %}
11806   ins_pipe(ialu_reg_reg);
11807 %}
11808 
11809 instruct overflowAddL_rReg(rFlagsReg cr, rax_RegL op1, rRegL op2)
11810 %{
11811   match(Set cr (OverflowAddL op1 op2));
11812   effect(DEF cr, USE_KILL op1, USE op2);
11813 
11814   format %{ "addq    $op1, $op2\t# overflow check long" %}
11815   ins_encode %{
11816     __ addq($op1$$Register, $op2$$Register);
11817   %}
11818   ins_pipe(ialu_reg_reg);
11819 %}
11820 
11821 instruct overflowAddL_rReg_imm(rFlagsReg cr, rax_RegL op1, immL32 op2)
11822 %{
11823   match(Set cr (OverflowAddL op1 op2));
11824   effect(DEF cr, USE_KILL op1, USE op2);
11825 
11826   format %{ "addq    $op1, $op2\t# overflow check long" %}
11827   ins_encode %{
11828     __ addq($op1$$Register, $op2$$constant);
11829   %}
11830   ins_pipe(ialu_reg_reg);
11831 %}
11832 
11833 instruct overflowSubI_rReg(rFlagsReg cr, rRegI op1, rRegI op2)
11834 %{
11835   match(Set cr (OverflowSubI op1 op2));
11836 
11837   format %{ "cmpl    $op1, $op2\t# overflow check int" %}
11838   ins_encode %{
11839     __ cmpl($op1$$Register, $op2$$Register);
11840   %}
11841   ins_pipe(ialu_reg_reg);
11842 %}
11843 
11844 instruct overflowSubI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2)
11845 %{
11846   match(Set cr (OverflowSubI op1 op2));
11847 
11848   format %{ "cmpl    $op1, $op2\t# overflow check int" %}
11849   ins_encode %{
11850     __ cmpl($op1$$Register, $op2$$constant);
11851   %}
11852   ins_pipe(ialu_reg_reg);
11853 %}
11854 
11855 instruct overflowSubL_rReg(rFlagsReg cr, rRegL op1, rRegL op2)
11856 %{
11857   match(Set cr (OverflowSubL op1 op2));
11858 
11859   format %{ "cmpq    $op1, $op2\t# overflow check long" %}
11860   ins_encode %{
11861     __ cmpq($op1$$Register, $op2$$Register);
11862   %}
11863   ins_pipe(ialu_reg_reg);
11864 %}
11865 
11866 instruct overflowSubL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2)
11867 %{
11868   match(Set cr (OverflowSubL op1 op2));
11869 
11870   format %{ "cmpq    $op1, $op2\t# overflow check long" %}
11871   ins_encode %{
11872     __ cmpq($op1$$Register, $op2$$constant);
11873   %}
11874   ins_pipe(ialu_reg_reg);
11875 %}
11876 
11877 instruct overflowNegI_rReg(rFlagsReg cr, immI_0 zero, rax_RegI op2)
11878 %{
11879   match(Set cr (OverflowSubI zero op2));
11880   effect(DEF cr, USE_KILL op2);
11881 
11882   format %{ "negl    $op2\t# overflow check int" %}
11883   ins_encode %{
11884     __ negl($op2$$Register);
11885   %}
11886   ins_pipe(ialu_reg_reg);
11887 %}
11888 
11889 instruct overflowNegL_rReg(rFlagsReg cr, immL0 zero, rax_RegL op2)
11890 %{
11891   match(Set cr (OverflowSubL zero op2));
11892   effect(DEF cr, USE_KILL op2);
11893 
11894   format %{ "negq    $op2\t# overflow check long" %}
11895   ins_encode %{
11896     __ negq($op2$$Register);
11897   %}
11898   ins_pipe(ialu_reg_reg);
11899 %}
11900 
11901 instruct overflowMulI_rReg(rFlagsReg cr, rax_RegI op1, rRegI op2)
11902 %{
11903   match(Set cr (OverflowMulI op1 op2));
11904   effect(DEF cr, USE_KILL op1, USE op2);
11905 
11906   format %{ "imull    $op1, $op2\t# overflow check int" %}
11907   ins_encode %{
11908     __ imull($op1$$Register, $op2$$Register);
11909   %}
11910   ins_pipe(ialu_reg_reg_alu0);
11911 %}
11912 
11913 instruct overflowMulI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2, rRegI tmp)
11914 %{
11915   match(Set cr (OverflowMulI op1 op2));
11916   effect(DEF cr, TEMP tmp, USE op1, USE op2);
11917 
11918   format %{ "imull    $tmp, $op1, $op2\t# overflow check int" %}
11919   ins_encode %{
11920     __ imull($tmp$$Register, $op1$$Register, $op2$$constant);
11921   %}
11922   ins_pipe(ialu_reg_reg_alu0);
11923 %}
11924 
11925 instruct overflowMulL_rReg(rFlagsReg cr, rax_RegL op1, rRegL op2)
11926 %{
11927   match(Set cr (OverflowMulL op1 op2));
11928   effect(DEF cr, USE_KILL op1, USE op2);
11929 
11930   format %{ "imulq    $op1, $op2\t# overflow check long" %}
11931   ins_encode %{
11932     __ imulq($op1$$Register, $op2$$Register);
11933   %}
11934   ins_pipe(ialu_reg_reg_alu0);
11935 %}
11936 
11937 instruct overflowMulL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2, rRegL tmp)
11938 %{
11939   match(Set cr (OverflowMulL op1 op2));
11940   effect(DEF cr, TEMP tmp, USE op1, USE op2);
11941 
11942   format %{ "imulq    $tmp, $op1, $op2\t# overflow check long" %}
11943   ins_encode %{
11944     __ imulq($tmp$$Register, $op1$$Register, $op2$$constant);
11945   %}
11946   ins_pipe(ialu_reg_reg_alu0);
11947 %}
11948 
11949 
11950 //----------Control Flow Instructions------------------------------------------
11951 // Signed compare Instructions
11952 
11953 // XXX more variants!!
11954 instruct compI_rReg(rFlagsReg cr, rRegI op1, rRegI op2)
11955 %{
11956   match(Set cr (CmpI op1 op2));
11957   effect(DEF cr, USE op1, USE op2);
11958 
11959   format %{ "cmpl    $op1, $op2" %}
11960   ins_encode %{
11961     __ cmpl($op1$$Register, $op2$$Register);
11962   %}
11963   ins_pipe(ialu_cr_reg_reg);
11964 %}
11965 
11966 instruct compI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2)
11967 %{
11968   match(Set cr (CmpI op1 op2));
11969 
11970   format %{ "cmpl    $op1, $op2" %}
11971   ins_encode %{
11972     __ cmpl($op1$$Register, $op2$$constant);
11973   %}
11974   ins_pipe(ialu_cr_reg_imm);
11975 %}
11976 
11977 instruct compI_rReg_mem(rFlagsReg cr, rRegI op1, memory op2)
11978 %{
11979   match(Set cr (CmpI op1 (LoadI op2)));
11980 
11981   ins_cost(500); // XXX
11982   format %{ "cmpl    $op1, $op2" %}
11983   ins_encode %{
11984     __ cmpl($op1$$Register, $op2$$Address);
11985   %}
11986   ins_pipe(ialu_cr_reg_mem);
11987 %}
11988 
11989 instruct testI_reg(rFlagsReg cr, rRegI src, immI_0 zero)
11990 %{
11991   match(Set cr (CmpI src zero));
11992 
11993   format %{ "testl   $src, $src" %}
11994   ins_encode %{
11995     __ testl($src$$Register, $src$$Register);
11996   %}
11997   ins_pipe(ialu_cr_reg_imm);
11998 %}
11999 
12000 instruct testI_reg_imm(rFlagsReg cr, rRegI src, immI con, immI_0 zero)
12001 %{
12002   match(Set cr (CmpI (AndI src con) zero));
12003 
12004   format %{ "testl   $src, $con" %}
12005   ins_encode %{
12006     __ testl($src$$Register, $con$$constant);
12007   %}
12008   ins_pipe(ialu_cr_reg_imm);
12009 %}
12010 
12011 instruct testI_reg_mem(rFlagsReg cr, rRegI src, memory mem, immI_0 zero)
12012 %{
12013   match(Set cr (CmpI (AndI src (LoadI mem)) zero));
12014 
12015   format %{ "testl   $src, $mem" %}
12016   ins_encode %{
12017     __ testl($src$$Register, $mem$$Address);
12018   %}
12019   ins_pipe(ialu_cr_reg_mem);
12020 %}
12021 
12022 // Unsigned compare Instructions; really, same as signed except they
12023 // produce an rFlagsRegU instead of rFlagsReg.
12024 instruct compU_rReg(rFlagsRegU cr, rRegI op1, rRegI op2)
12025 %{
12026   match(Set cr (CmpU op1 op2));
12027 
12028   format %{ "cmpl    $op1, $op2\t# unsigned" %}
12029   ins_encode %{
12030     __ cmpl($op1$$Register, $op2$$Register);
12031   %}
12032   ins_pipe(ialu_cr_reg_reg);
12033 %}
12034 
12035 instruct compU_rReg_imm(rFlagsRegU cr, rRegI op1, immI op2)
12036 %{
12037   match(Set cr (CmpU op1 op2));
12038 
12039   format %{ "cmpl    $op1, $op2\t# unsigned" %}
12040   ins_encode %{
12041     __ cmpl($op1$$Register, $op2$$constant);
12042   %}
12043   ins_pipe(ialu_cr_reg_imm);
12044 %}
12045 
12046 instruct compU_rReg_mem(rFlagsRegU cr, rRegI op1, memory op2)
12047 %{
12048   match(Set cr (CmpU op1 (LoadI op2)));
12049 
12050   ins_cost(500); // XXX
12051   format %{ "cmpl    $op1, $op2\t# unsigned" %}
12052   ins_encode %{
12053     __ cmpl($op1$$Register, $op2$$Address);
12054   %}
12055   ins_pipe(ialu_cr_reg_mem);
12056 %}
12057 
12058 // // // Cisc-spilled version of cmpU_rReg
12059 // //instruct compU_mem_rReg(rFlagsRegU cr, memory op1, rRegI op2)
12060 // //%{
12061 // //  match(Set cr (CmpU (LoadI op1) op2));
12062 // //
12063 // //  format %{ "CMPu   $op1,$op2" %}
12064 // //  ins_cost(500);
12065 // //  opcode(0x39);  /* Opcode 39 /r */
12066 // //  ins_encode( OpcP, reg_mem( op1, op2) );
12067 // //%}
12068 
12069 instruct testU_reg(rFlagsRegU cr, rRegI src, immI_0 zero)
12070 %{
12071   match(Set cr (CmpU src zero));
12072 
12073   format %{ "testl   $src, $src\t# unsigned" %}
12074   ins_encode %{
12075     __ testl($src$$Register, $src$$Register);
12076   %}
12077   ins_pipe(ialu_cr_reg_imm);
12078 %}
12079 
12080 instruct compP_rReg(rFlagsRegU cr, rRegP op1, rRegP op2)
12081 %{
12082   match(Set cr (CmpP op1 op2));
12083 
12084   format %{ "cmpq    $op1, $op2\t# ptr" %}
12085   ins_encode %{
12086     __ cmpq($op1$$Register, $op2$$Register);
12087   %}
12088   ins_pipe(ialu_cr_reg_reg);
12089 %}
12090 
12091 instruct compP_rReg_mem(rFlagsRegU cr, rRegP op1, memory op2)
12092 %{
12093   match(Set cr (CmpP op1 (LoadP op2)));
12094   predicate(n->in(2)->as_Load()->barrier_data() == 0);
12095 
12096   ins_cost(500); // XXX
12097   format %{ "cmpq    $op1, $op2\t# ptr" %}
12098   ins_encode %{
12099     __ cmpq($op1$$Register, $op2$$Address);
12100   %}
12101   ins_pipe(ialu_cr_reg_mem);
12102 %}
12103 
12104 // // // Cisc-spilled version of cmpP_rReg
12105 // //instruct compP_mem_rReg(rFlagsRegU cr, memory op1, rRegP op2)
12106 // //%{
12107 // //  match(Set cr (CmpP (LoadP op1) op2));
12108 // //
12109 // //  format %{ "CMPu   $op1,$op2" %}
12110 // //  ins_cost(500);
12111 // //  opcode(0x39);  /* Opcode 39 /r */
12112 // //  ins_encode( OpcP, reg_mem( op1, op2) );
12113 // //%}
12114 
12115 // XXX this is generalized by compP_rReg_mem???
12116 // Compare raw pointer (used in out-of-heap check).
12117 // Only works because non-oop pointers must be raw pointers
12118 // and raw pointers have no anti-dependencies.
12119 instruct compP_mem_rReg(rFlagsRegU cr, rRegP op1, memory op2)
12120 %{
12121   predicate(n->in(2)->in(2)->bottom_type()->reloc() == relocInfo::none &&
12122             n->in(2)->as_Load()->barrier_data() == 0);
12123   match(Set cr (CmpP op1 (LoadP op2)));
12124 
12125   format %{ "cmpq    $op1, $op2\t# raw ptr" %}
12126   ins_encode %{
12127     __ cmpq($op1$$Register, $op2$$Address);
12128   %}
12129   ins_pipe(ialu_cr_reg_mem);
12130 %}
12131 
12132 // This will generate a signed flags result. This should be OK since
12133 // any compare to a zero should be eq/neq.
12134 instruct testP_reg(rFlagsReg cr, rRegP src, immP0 zero)
12135 %{
12136   match(Set cr (CmpP src zero));
12137 
12138   format %{ "testq   $src, $src\t# ptr" %}
12139   ins_encode %{
12140     __ testq($src$$Register, $src$$Register);
12141   %}
12142   ins_pipe(ialu_cr_reg_imm);
12143 %}
12144 
12145 // This will generate a signed flags result. This should be OK since
12146 // any compare to a zero should be eq/neq.
12147 instruct testP_mem(rFlagsReg cr, memory op, immP0 zero)
12148 %{
12149   predicate((!UseCompressedOops || (CompressedOops::base() != NULL)) &&
12150             n->in(1)->as_Load()->barrier_data() == 0);
12151   match(Set cr (CmpP (LoadP op) zero));
12152 
12153   ins_cost(500); // XXX
12154   format %{ "testq   $op, 0xffffffffffffffff\t# ptr" %}
12155   ins_encode %{
12156     __ testq($op$$Address, 0xFFFFFFFF);
12157   %}
12158   ins_pipe(ialu_cr_reg_imm);
12159 %}
12160 
12161 instruct testP_mem_reg0(rFlagsReg cr, memory mem, immP0 zero)
12162 %{
12163   predicate(UseCompressedOops && (CompressedOops::base() == NULL) &&
12164             n->in(1)->as_Load()->barrier_data() == 0);
12165   match(Set cr (CmpP (LoadP mem) zero));
12166 
12167   format %{ "cmpq    R12, $mem\t# ptr (R12_heapbase==0)" %}
12168   ins_encode %{
12169     __ cmpq(r12, $mem$$Address);
12170   %}
12171   ins_pipe(ialu_cr_reg_mem);
12172 %}
12173 
12174 instruct compN_rReg(rFlagsRegU cr, rRegN op1, rRegN op2)
12175 %{
12176   match(Set cr (CmpN op1 op2));
12177 
12178   format %{ "cmpl    $op1, $op2\t# compressed ptr" %}
12179   ins_encode %{ __ cmpl($op1$$Register, $op2$$Register); %}
12180   ins_pipe(ialu_cr_reg_reg);
12181 %}
12182 
12183 instruct compN_rReg_mem(rFlagsRegU cr, rRegN src, memory mem)
12184 %{
12185   match(Set cr (CmpN src (LoadN mem)));
12186 
12187   format %{ "cmpl    $src, $mem\t# compressed ptr" %}
12188   ins_encode %{
12189     __ cmpl($src$$Register, $mem$$Address);
12190   %}
12191   ins_pipe(ialu_cr_reg_mem);
12192 %}
12193 
12194 instruct compN_rReg_imm(rFlagsRegU cr, rRegN op1, immN op2) %{
12195   match(Set cr (CmpN op1 op2));
12196 
12197   format %{ "cmpl    $op1, $op2\t# compressed ptr" %}
12198   ins_encode %{
12199     __ cmp_narrow_oop($op1$$Register, (jobject)$op2$$constant);
12200   %}
12201   ins_pipe(ialu_cr_reg_imm);
12202 %}
12203 
12204 instruct compN_mem_imm(rFlagsRegU cr, memory mem, immN src)
12205 %{
12206   match(Set cr (CmpN src (LoadN mem)));
12207 
12208   format %{ "cmpl    $mem, $src\t# compressed ptr" %}
12209   ins_encode %{
12210     __ cmp_narrow_oop($mem$$Address, (jobject)$src$$constant);
12211   %}
12212   ins_pipe(ialu_cr_reg_mem);
12213 %}
12214 
12215 instruct compN_rReg_imm_klass(rFlagsRegU cr, rRegN op1, immNKlass op2) %{
12216   match(Set cr (CmpN op1 op2));
12217 
12218   format %{ "cmpl    $op1, $op2\t# compressed klass ptr" %}
12219   ins_encode %{
12220     __ cmp_narrow_klass($op1$$Register, (Klass*)$op2$$constant);
12221   %}
12222   ins_pipe(ialu_cr_reg_imm);
12223 %}
12224 
12225 instruct compN_mem_imm_klass(rFlagsRegU cr, memory mem, immNKlass src)
12226 %{
12227   match(Set cr (CmpN src (LoadNKlass mem)));
12228 
12229   format %{ "cmpl    $mem, $src\t# compressed klass ptr" %}
12230   ins_encode %{
12231     __ cmp_narrow_klass($mem$$Address, (Klass*)$src$$constant);
12232   %}
12233   ins_pipe(ialu_cr_reg_mem);
12234 %}
12235 
12236 instruct testN_reg(rFlagsReg cr, rRegN src, immN0 zero) %{
12237   match(Set cr (CmpN src zero));
12238 
12239   format %{ "testl   $src, $src\t# compressed ptr" %}
12240   ins_encode %{ __ testl($src$$Register, $src$$Register); %}
12241   ins_pipe(ialu_cr_reg_imm);
12242 %}
12243 
12244 instruct testN_mem(rFlagsReg cr, memory mem, immN0 zero)
12245 %{
12246   predicate(CompressedOops::base() != NULL);
12247   match(Set cr (CmpN (LoadN mem) zero));
12248 
12249   ins_cost(500); // XXX
12250   format %{ "testl   $mem, 0xffffffff\t# compressed ptr" %}
12251   ins_encode %{
12252     __ cmpl($mem$$Address, (int)0xFFFFFFFF);
12253   %}
12254   ins_pipe(ialu_cr_reg_mem);
12255 %}
12256 
12257 instruct testN_mem_reg0(rFlagsReg cr, memory mem, immN0 zero)
12258 %{
12259   predicate(CompressedOops::base() == NULL);
12260   match(Set cr (CmpN (LoadN mem) zero));
12261 
12262   format %{ "cmpl    R12, $mem\t# compressed ptr (R12_heapbase==0)" %}
12263   ins_encode %{
12264     __ cmpl(r12, $mem$$Address);
12265   %}
12266   ins_pipe(ialu_cr_reg_mem);
12267 %}
12268 
12269 // Yanked all unsigned pointer compare operations.
12270 // Pointer compares are done with CmpP which is already unsigned.
12271 
12272 instruct compL_rReg(rFlagsReg cr, rRegL op1, rRegL op2)
12273 %{
12274   match(Set cr (CmpL op1 op2));
12275 
12276   format %{ "cmpq    $op1, $op2" %}
12277   ins_encode %{
12278     __ cmpq($op1$$Register, $op2$$Register);
12279   %}
12280   ins_pipe(ialu_cr_reg_reg);
12281 %}
12282 
12283 instruct compL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2)
12284 %{
12285   match(Set cr (CmpL op1 op2));
12286 
12287   format %{ "cmpq    $op1, $op2" %}
12288   ins_encode %{
12289     __ cmpq($op1$$Register, $op2$$constant);
12290   %}
12291   ins_pipe(ialu_cr_reg_imm);
12292 %}
12293 
12294 instruct compL_rReg_mem(rFlagsReg cr, rRegL op1, memory op2)
12295 %{
12296   match(Set cr (CmpL op1 (LoadL op2)));
12297 
12298   format %{ "cmpq    $op1, $op2" %}
12299   ins_encode %{
12300     __ cmpq($op1$$Register, $op2$$Address);
12301   %}
12302   ins_pipe(ialu_cr_reg_mem);
12303 %}
12304 
12305 instruct testL_reg(rFlagsReg cr, rRegL src, immL0 zero)
12306 %{
12307   match(Set cr (CmpL src zero));
12308 
12309   format %{ "testq   $src, $src" %}
12310   ins_encode %{
12311     __ testq($src$$Register, $src$$Register);
12312   %}
12313   ins_pipe(ialu_cr_reg_imm);
12314 %}
12315 
12316 instruct testL_reg_imm(rFlagsReg cr, rRegL src, immL32 con, immL0 zero)
12317 %{
12318   match(Set cr (CmpL (AndL src con) zero));
12319 
12320   format %{ "testq   $src, $con\t# long" %}
12321   ins_encode %{
12322     __ testq($src$$Register, $con$$constant);
12323   %}
12324   ins_pipe(ialu_cr_reg_imm);
12325 %}
12326 
12327 instruct testL_reg_mem(rFlagsReg cr, rRegL src, memory mem, immL0 zero)
12328 %{
12329   match(Set cr (CmpL (AndL src (LoadL mem)) zero));
12330 
12331   format %{ "testq   $src, $mem" %}
12332   ins_encode %{
12333     __ testq($src$$Register, $mem$$Address);
12334   %}
12335   ins_pipe(ialu_cr_reg_mem);
12336 %}
12337 
12338 instruct testL_reg_mem2(rFlagsReg cr, rRegP src, memory mem, immL0 zero)
12339 %{
12340   match(Set cr (CmpL (AndL (CastP2X src) (LoadL mem)) zero));
12341 
12342   format %{ "testq   $src, $mem" %}
12343   ins_encode %{
12344     __ testq($src$$Register, $mem$$Address);
12345   %}
12346   ins_pipe(ialu_cr_reg_mem);
12347 %}
12348 
12349 // Manifest a CmpL result in an integer register.  Very painful.
12350 // This is the test to avoid.
12351 instruct cmpL3_reg_reg(rRegI dst, rRegL src1, rRegL src2, rFlagsReg flags)
12352 %{
12353   match(Set dst (CmpL3 src1 src2));
12354   effect(KILL flags);
12355 
12356   ins_cost(275); // XXX
12357   format %{ "cmpq    $src1, $src2\t# CmpL3\n\t"
12358             "movl    $dst, -1\n\t"
12359             "jl,s    done\n\t"
12360             "setne   $dst\n\t"
12361             "movzbl  $dst, $dst\n\t"
12362     "done:" %}
12363   ins_encode %{
12364     Label done;
12365     __ cmpq($src1$$Register, $src2$$Register);
12366     __ movl($dst$$Register, -1);
12367     __ jccb(Assembler::less, done);
12368     __ setne($dst$$Register);
12369     __ movzbl($dst$$Register, $dst$$Register);
12370     __ bind(done);
12371   %}
12372   ins_pipe(pipe_slow);
12373 %}
12374 
12375 // Unsigned long compare Instructions; really, same as signed long except they
12376 // produce an rFlagsRegU instead of rFlagsReg.
12377 instruct compUL_rReg(rFlagsRegU cr, rRegL op1, rRegL op2)
12378 %{
12379   match(Set cr (CmpUL op1 op2));
12380 
12381   format %{ "cmpq    $op1, $op2\t# unsigned" %}
12382   ins_encode %{
12383     __ cmpq($op1$$Register, $op2$$Register);
12384   %}
12385   ins_pipe(ialu_cr_reg_reg);
12386 %}
12387 
12388 instruct compUL_rReg_imm(rFlagsRegU cr, rRegL op1, immL32 op2)
12389 %{
12390   match(Set cr (CmpUL op1 op2));
12391 
12392   format %{ "cmpq    $op1, $op2\t# unsigned" %}
12393   ins_encode %{
12394     __ cmpq($op1$$Register, $op2$$constant);
12395   %}
12396   ins_pipe(ialu_cr_reg_imm);
12397 %}
12398 
12399 instruct compUL_rReg_mem(rFlagsRegU cr, rRegL op1, memory op2)
12400 %{
12401   match(Set cr (CmpUL op1 (LoadL op2)));
12402 
12403   format %{ "cmpq    $op1, $op2\t# unsigned" %}
12404   ins_encode %{
12405     __ cmpq($op1$$Register, $op2$$Address);
12406   %}
12407   ins_pipe(ialu_cr_reg_mem);
12408 %}
12409 
12410 instruct testUL_reg(rFlagsRegU cr, rRegL src, immL0 zero)
12411 %{
12412   match(Set cr (CmpUL src zero));
12413 
12414   format %{ "testq   $src, $src\t# unsigned" %}
12415   ins_encode %{
12416     __ testq($src$$Register, $src$$Register);
12417   %}
12418   ins_pipe(ialu_cr_reg_imm);
12419 %}
12420 
12421 instruct compB_mem_imm(rFlagsReg cr, memory mem, immI8 imm)
12422 %{
12423   match(Set cr (CmpI (LoadB mem) imm));
12424 
12425   ins_cost(125);
12426   format %{ "cmpb    $mem, $imm" %}
12427   ins_encode %{ __ cmpb($mem$$Address, $imm$$constant); %}
12428   ins_pipe(ialu_cr_reg_mem);
12429 %}
12430 
12431 instruct testUB_mem_imm(rFlagsReg cr, memory mem, immU7 imm, immI_0 zero)
12432 %{
12433   match(Set cr (CmpI (AndI (LoadUB mem) imm) zero));
12434 
12435   ins_cost(125);
12436   format %{ "testb   $mem, $imm\t# ubyte" %}
12437   ins_encode %{ __ testb($mem$$Address, $imm$$constant); %}
12438   ins_pipe(ialu_cr_reg_mem);
12439 %}
12440 
12441 instruct testB_mem_imm(rFlagsReg cr, memory mem, immI8 imm, immI_0 zero)
12442 %{
12443   match(Set cr (CmpI (AndI (LoadB mem) imm) zero));
12444 
12445   ins_cost(125);
12446   format %{ "testb   $mem, $imm\t# byte" %}
12447   ins_encode %{ __ testb($mem$$Address, $imm$$constant); %}
12448   ins_pipe(ialu_cr_reg_mem);
12449 %}
12450 
12451 //----------Max and Min--------------------------------------------------------
12452 // Min Instructions
12453 
12454 instruct cmovI_reg_g(rRegI dst, rRegI src, rFlagsReg cr)
12455 %{
12456   effect(USE_DEF dst, USE src, USE cr);
12457 
12458   format %{ "cmovlgt $dst, $src\t# min" %}
12459   ins_encode %{
12460     __ cmovl(Assembler::greater, $dst$$Register, $src$$Register);
12461   %}
12462   ins_pipe(pipe_cmov_reg);
12463 %}
12464 
12465 
12466 instruct minI_rReg(rRegI dst, rRegI src)
12467 %{
12468   match(Set dst (MinI dst src));
12469 
12470   ins_cost(200);
12471   expand %{
12472     rFlagsReg cr;
12473     compI_rReg(cr, dst, src);
12474     cmovI_reg_g(dst, src, cr);
12475   %}
12476 %}
12477 
12478 instruct cmovI_reg_l(rRegI dst, rRegI src, rFlagsReg cr)
12479 %{
12480   effect(USE_DEF dst, USE src, USE cr);
12481 
12482   format %{ "cmovllt $dst, $src\t# max" %}
12483   ins_encode %{
12484     __ cmovl(Assembler::less, $dst$$Register, $src$$Register);
12485   %}
12486   ins_pipe(pipe_cmov_reg);
12487 %}
12488 
12489 
12490 instruct maxI_rReg(rRegI dst, rRegI src)
12491 %{
12492   match(Set dst (MaxI dst src));
12493 
12494   ins_cost(200);
12495   expand %{
12496     rFlagsReg cr;
12497     compI_rReg(cr, dst, src);
12498     cmovI_reg_l(dst, src, cr);
12499   %}
12500 %}
12501 
12502 // ============================================================================
12503 // Branch Instructions
12504 
12505 // Jump Direct - Label defines a relative address from JMP+1
12506 instruct jmpDir(label labl)
12507 %{
12508   match(Goto);
12509   effect(USE labl);
12510 
12511   ins_cost(300);
12512   format %{ "jmp     $labl" %}
12513   size(5);
12514   ins_encode %{
12515     Label* L = $labl$$label;
12516     __ jmp(*L, false); // Always long jump
12517   %}
12518   ins_pipe(pipe_jmp);
12519 %}
12520 
12521 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12522 instruct jmpCon(cmpOp cop, rFlagsReg cr, label labl)
12523 %{
12524   match(If cop cr);
12525   effect(USE labl);
12526 
12527   ins_cost(300);
12528   format %{ "j$cop     $labl" %}
12529   size(6);
12530   ins_encode %{
12531     Label* L = $labl$$label;
12532     __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12533   %}
12534   ins_pipe(pipe_jcc);
12535 %}
12536 
12537 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12538 instruct jmpLoopEnd(cmpOp cop, rFlagsReg cr, label labl)
12539 %{
12540   predicate(!n->has_vector_mask_set());
12541   match(CountedLoopEnd cop cr);
12542   effect(USE labl);
12543 
12544   ins_cost(300);
12545   format %{ "j$cop     $labl\t# loop end" %}
12546   size(6);
12547   ins_encode %{
12548     Label* L = $labl$$label;
12549     __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12550   %}
12551   ins_pipe(pipe_jcc);
12552 %}
12553 
12554 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12555 instruct jmpLoopEndU(cmpOpU cop, rFlagsRegU cmp, label labl) %{
12556   predicate(!n->has_vector_mask_set());
12557   match(CountedLoopEnd cop cmp);
12558   effect(USE labl);
12559 
12560   ins_cost(300);
12561   format %{ "j$cop,u   $labl\t# loop end" %}
12562   size(6);
12563   ins_encode %{
12564     Label* L = $labl$$label;
12565     __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12566   %}
12567   ins_pipe(pipe_jcc);
12568 %}
12569 
12570 instruct jmpLoopEndUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
12571   predicate(!n->has_vector_mask_set());
12572   match(CountedLoopEnd cop cmp);
12573   effect(USE labl);
12574 
12575   ins_cost(200);
12576   format %{ "j$cop,u   $labl\t# loop end" %}
12577   size(6);
12578   ins_encode %{
12579     Label* L = $labl$$label;
12580     __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12581   %}
12582   ins_pipe(pipe_jcc);
12583 %}
12584 
12585 // mask version
12586 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12587 // Bounded mask operand used in following patten is needed for
12588 // post-loop multiversioning.
12589 instruct jmpLoopEnd_and_restoreMask(cmpOp cop, kReg_K1 ktmp, rFlagsReg cr, label labl)
12590 %{
12591   predicate(PostLoopMultiversioning && n->has_vector_mask_set());
12592   match(CountedLoopEnd cop cr);
12593   effect(USE labl, TEMP ktmp);
12594 
12595   ins_cost(400);
12596   format %{ "j$cop     $labl\t# loop end\n\t"
12597             "restorevectmask \t# vector mask restore for loops" %}
12598   size(10);
12599   ins_encode %{
12600     Label* L = $labl$$label;
12601     __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12602     __ restorevectmask($ktmp$$KRegister);
12603   %}
12604   ins_pipe(pipe_jcc);
12605 %}
12606 
12607 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12608 // Bounded mask operand used in following patten is needed for
12609 // post-loop multiversioning.
12610 instruct jmpLoopEndU_and_restoreMask(cmpOpU cop, kReg_K1 ktmp, rFlagsRegU cmp, label labl) %{
12611   predicate(PostLoopMultiversioning && n->has_vector_mask_set());
12612   match(CountedLoopEnd cop cmp);
12613   effect(USE labl, TEMP ktmp);
12614 
12615   ins_cost(400);
12616   format %{ "j$cop,u   $labl\t# loop end\n\t"
12617             "restorevectmask \t# vector mask restore for loops" %}
12618   size(10);
12619   ins_encode %{
12620     Label* L = $labl$$label;
12621     __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12622     __ restorevectmask($ktmp$$KRegister);
12623   %}
12624   ins_pipe(pipe_jcc);
12625 %}
12626 
12627 // Bounded mask operand used in following patten is needed for
12628 // post-loop multiversioning.
12629 instruct jmpLoopEndUCF_and_restoreMask(cmpOpUCF cop, kReg_K1 ktmp, rFlagsRegUCF cmp, label labl) %{
12630   predicate(PostLoopMultiversioning && n->has_vector_mask_set());
12631   match(CountedLoopEnd cop cmp);
12632   effect(USE labl, TEMP ktmp);
12633 
12634   ins_cost(300);
12635   format %{ "j$cop,u   $labl\t# loop end\n\t"
12636             "restorevectmask \t# vector mask restore for loops" %}
12637   size(10);
12638   ins_encode %{
12639     Label* L = $labl$$label;
12640     __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12641     __ restorevectmask($ktmp$$KRegister);
12642   %}
12643   ins_pipe(pipe_jcc);
12644 %}
12645 
12646 // Jump Direct Conditional - using unsigned comparison
12647 instruct jmpConU(cmpOpU cop, rFlagsRegU cmp, label labl) %{
12648   match(If cop cmp);
12649   effect(USE labl);
12650 
12651   ins_cost(300);
12652   format %{ "j$cop,u   $labl" %}
12653   size(6);
12654   ins_encode %{
12655     Label* L = $labl$$label;
12656     __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12657   %}
12658   ins_pipe(pipe_jcc);
12659 %}
12660 
12661 instruct jmpConUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
12662   match(If cop cmp);
12663   effect(USE labl);
12664 
12665   ins_cost(200);
12666   format %{ "j$cop,u   $labl" %}
12667   size(6);
12668   ins_encode %{
12669     Label* L = $labl$$label;
12670     __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12671   %}
12672   ins_pipe(pipe_jcc);
12673 %}
12674 
12675 instruct jmpConUCF2(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{
12676   match(If cop cmp);
12677   effect(USE labl);
12678 
12679   ins_cost(200);
12680   format %{ $$template
12681     if ($cop$$cmpcode == Assembler::notEqual) {
12682       $$emit$$"jp,u    $labl\n\t"
12683       $$emit$$"j$cop,u   $labl"
12684     } else {
12685       $$emit$$"jp,u    done\n\t"
12686       $$emit$$"j$cop,u   $labl\n\t"
12687       $$emit$$"done:"
12688     }
12689   %}
12690   ins_encode %{
12691     Label* l = $labl$$label;
12692     if ($cop$$cmpcode == Assembler::notEqual) {
12693       __ jcc(Assembler::parity, *l, false);
12694       __ jcc(Assembler::notEqual, *l, false);
12695     } else if ($cop$$cmpcode == Assembler::equal) {
12696       Label done;
12697       __ jccb(Assembler::parity, done);
12698       __ jcc(Assembler::equal, *l, false);
12699       __ bind(done);
12700     } else {
12701        ShouldNotReachHere();
12702     }
12703   %}
12704   ins_pipe(pipe_jcc);
12705 %}
12706 
12707 // ============================================================================
12708 // The 2nd slow-half of a subtype check.  Scan the subklass's 2ndary
12709 // superklass array for an instance of the superklass.  Set a hidden
12710 // internal cache on a hit (cache is checked with exposed code in
12711 // gen_subtype_check()).  Return NZ for a miss or zero for a hit.  The
12712 // encoding ALSO sets flags.
12713 
12714 instruct partialSubtypeCheck(rdi_RegP result,
12715                              rsi_RegP sub, rax_RegP super, rcx_RegI rcx,
12716                              rFlagsReg cr)
12717 %{
12718   match(Set result (PartialSubtypeCheck sub super));
12719   effect(KILL rcx, KILL cr);
12720 
12721   ins_cost(1100);  // slightly larger than the next version
12722   format %{ "movq    rdi, [$sub + in_bytes(Klass::secondary_supers_offset())]\n\t"
12723             "movl    rcx, [rdi + Array<Klass*>::length_offset_in_bytes()]\t# length to scan\n\t"
12724             "addq    rdi, Array<Klass*>::base_offset_in_bytes()\t# Skip to start of data; set NZ in case count is zero\n\t"
12725             "repne   scasq\t# Scan *rdi++ for a match with rax while rcx--\n\t"
12726             "jne,s   miss\t\t# Missed: rdi not-zero\n\t"
12727             "movq    [$sub + in_bytes(Klass::secondary_super_cache_offset())], $super\t# Hit: update cache\n\t"
12728             "xorq    $result, $result\t\t Hit: rdi zero\n\t"
12729     "miss:\t" %}
12730 
12731   opcode(0x1); // Force a XOR of RDI
12732   ins_encode(enc_PartialSubtypeCheck());
12733   ins_pipe(pipe_slow);
12734 %}
12735 
12736 instruct partialSubtypeCheck_vs_Zero(rFlagsReg cr,
12737                                      rsi_RegP sub, rax_RegP super, rcx_RegI rcx,
12738                                      immP0 zero,
12739                                      rdi_RegP result)
12740 %{
12741   match(Set cr (CmpP (PartialSubtypeCheck sub super) zero));
12742   effect(KILL rcx, KILL result);
12743 
12744   ins_cost(1000);
12745   format %{ "movq    rdi, [$sub + in_bytes(Klass::secondary_supers_offset())]\n\t"
12746             "movl    rcx, [rdi + Array<Klass*>::length_offset_in_bytes()]\t# length to scan\n\t"
12747             "addq    rdi, Array<Klass*>::base_offset_in_bytes()\t# Skip to start of data; set NZ in case count is zero\n\t"
12748             "repne   scasq\t# Scan *rdi++ for a match with rax while cx-- != 0\n\t"
12749             "jne,s   miss\t\t# Missed: flags nz\n\t"
12750             "movq    [$sub + in_bytes(Klass::secondary_super_cache_offset())], $super\t# Hit: update cache\n\t"
12751     "miss:\t" %}
12752 
12753   opcode(0x0); // No need to XOR RDI
12754   ins_encode(enc_PartialSubtypeCheck());
12755   ins_pipe(pipe_slow);
12756 %}
12757 
12758 // ============================================================================
12759 // Branch Instructions -- short offset versions
12760 //
12761 // These instructions are used to replace jumps of a long offset (the default
12762 // match) with jumps of a shorter offset.  These instructions are all tagged
12763 // with the ins_short_branch attribute, which causes the ADLC to suppress the
12764 // match rules in general matching.  Instead, the ADLC generates a conversion
12765 // method in the MachNode which can be used to do in-place replacement of the
12766 // long variant with the shorter variant.  The compiler will determine if a
12767 // branch can be taken by the is_short_branch_offset() predicate in the machine
12768 // specific code section of the file.
12769 
12770 // Jump Direct - Label defines a relative address from JMP+1
12771 instruct jmpDir_short(label labl) %{
12772   match(Goto);
12773   effect(USE labl);
12774 
12775   ins_cost(300);
12776   format %{ "jmp,s   $labl" %}
12777   size(2);
12778   ins_encode %{
12779     Label* L = $labl$$label;
12780     __ jmpb(*L);
12781   %}
12782   ins_pipe(pipe_jmp);
12783   ins_short_branch(1);
12784 %}
12785 
12786 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12787 instruct jmpCon_short(cmpOp cop, rFlagsReg cr, label labl) %{
12788   match(If cop cr);
12789   effect(USE labl);
12790 
12791   ins_cost(300);
12792   format %{ "j$cop,s   $labl" %}
12793   size(2);
12794   ins_encode %{
12795     Label* L = $labl$$label;
12796     __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12797   %}
12798   ins_pipe(pipe_jcc);
12799   ins_short_branch(1);
12800 %}
12801 
12802 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12803 instruct jmpLoopEnd_short(cmpOp cop, rFlagsReg cr, label labl) %{
12804   match(CountedLoopEnd cop cr);
12805   effect(USE labl);
12806 
12807   ins_cost(300);
12808   format %{ "j$cop,s   $labl\t# loop end" %}
12809   size(2);
12810   ins_encode %{
12811     Label* L = $labl$$label;
12812     __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12813   %}
12814   ins_pipe(pipe_jcc);
12815   ins_short_branch(1);
12816 %}
12817 
12818 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12819 instruct jmpLoopEndU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{
12820   match(CountedLoopEnd cop cmp);
12821   effect(USE labl);
12822 
12823   ins_cost(300);
12824   format %{ "j$cop,us  $labl\t# loop end" %}
12825   size(2);
12826   ins_encode %{
12827     Label* L = $labl$$label;
12828     __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12829   %}
12830   ins_pipe(pipe_jcc);
12831   ins_short_branch(1);
12832 %}
12833 
12834 instruct jmpLoopEndUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
12835   match(CountedLoopEnd cop cmp);
12836   effect(USE labl);
12837 
12838   ins_cost(300);
12839   format %{ "j$cop,us  $labl\t# loop end" %}
12840   size(2);
12841   ins_encode %{
12842     Label* L = $labl$$label;
12843     __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12844   %}
12845   ins_pipe(pipe_jcc);
12846   ins_short_branch(1);
12847 %}
12848 
12849 // Jump Direct Conditional - using unsigned comparison
12850 instruct jmpConU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{
12851   match(If cop cmp);
12852   effect(USE labl);
12853 
12854   ins_cost(300);
12855   format %{ "j$cop,us  $labl" %}
12856   size(2);
12857   ins_encode %{
12858     Label* L = $labl$$label;
12859     __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12860   %}
12861   ins_pipe(pipe_jcc);
12862   ins_short_branch(1);
12863 %}
12864 
12865 instruct jmpConUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
12866   match(If cop cmp);
12867   effect(USE labl);
12868 
12869   ins_cost(300);
12870   format %{ "j$cop,us  $labl" %}
12871   size(2);
12872   ins_encode %{
12873     Label* L = $labl$$label;
12874     __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12875   %}
12876   ins_pipe(pipe_jcc);
12877   ins_short_branch(1);
12878 %}
12879 
12880 instruct jmpConUCF2_short(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{
12881   match(If cop cmp);
12882   effect(USE labl);
12883 
12884   ins_cost(300);
12885   format %{ $$template
12886     if ($cop$$cmpcode == Assembler::notEqual) {
12887       $$emit$$"jp,u,s  $labl\n\t"
12888       $$emit$$"j$cop,u,s  $labl"
12889     } else {
12890       $$emit$$"jp,u,s  done\n\t"
12891       $$emit$$"j$cop,u,s  $labl\n\t"
12892       $$emit$$"done:"
12893     }
12894   %}
12895   size(4);
12896   ins_encode %{
12897     Label* l = $labl$$label;
12898     if ($cop$$cmpcode == Assembler::notEqual) {
12899       __ jccb(Assembler::parity, *l);
12900       __ jccb(Assembler::notEqual, *l);
12901     } else if ($cop$$cmpcode == Assembler::equal) {
12902       Label done;
12903       __ jccb(Assembler::parity, done);
12904       __ jccb(Assembler::equal, *l);
12905       __ bind(done);
12906     } else {
12907        ShouldNotReachHere();
12908     }
12909   %}
12910   ins_pipe(pipe_jcc);
12911   ins_short_branch(1);
12912 %}
12913 
12914 // ============================================================================
12915 // inlined locking and unlocking
12916 
12917 instruct cmpFastLockRTM(rFlagsReg cr, rRegP object, rbx_RegP box, rax_RegI tmp, rdx_RegI scr, rRegI cx1, rRegI cx2) %{
12918   predicate(Compile::current()->use_rtm());
12919   match(Set cr (FastLock object box));
12920   effect(TEMP tmp, TEMP scr, TEMP cx1, TEMP cx2, USE_KILL box);
12921   ins_cost(300);
12922   format %{ "fastlock $object,$box\t! kills $box,$tmp,$scr,$cx1,$cx2" %}
12923   ins_encode %{
12924     __ fast_lock($object$$Register, $box$$Register, $tmp$$Register,
12925                  $scr$$Register, $cx1$$Register, $cx2$$Register,
12926                  _counters, _rtm_counters, _stack_rtm_counters,
12927                  ((Method*)(ra_->C->method()->constant_encoding()))->method_data(),
12928                  true, ra_->C->profile_rtm());
12929   %}
12930   ins_pipe(pipe_slow);
12931 %}
12932 
12933 instruct cmpFastLock(rFlagsReg cr, rRegP object, rbx_RegP box, rax_RegI tmp, rRegP scr, rRegP cx1) %{
12934   predicate(!Compile::current()->use_rtm());
12935   match(Set cr (FastLock object box));
12936   effect(TEMP tmp, TEMP scr, TEMP cx1, USE_KILL box);
12937   ins_cost(300);
12938   format %{ "fastlock $object,$box\t! kills $box,$tmp,$scr" %}
12939   ins_encode %{
12940     __ fast_lock($object$$Register, $box$$Register, $tmp$$Register,
12941                  $scr$$Register, $cx1$$Register, noreg, _counters, NULL, NULL, NULL, false, false);
12942   %}
12943   ins_pipe(pipe_slow);
12944 %}
12945 
12946 instruct cmpFastUnlock(rFlagsReg cr, rRegP object, rax_RegP box, rRegP tmp) %{
12947   match(Set cr (FastUnlock object box));
12948   effect(TEMP tmp, USE_KILL box);
12949   ins_cost(300);
12950   format %{ "fastunlock $object,$box\t! kills $box,$tmp" %}
12951   ins_encode %{
12952     __ fast_unlock($object$$Register, $box$$Register, $tmp$$Register, ra_->C->use_rtm());
12953   %}
12954   ins_pipe(pipe_slow);
12955 %}
12956 
12957 
12958 // ============================================================================
12959 // Safepoint Instructions
12960 instruct safePoint_poll_tls(rFlagsReg cr, rRegP poll)
12961 %{
12962   match(SafePoint poll);
12963   effect(KILL cr, USE poll);
12964 
12965   format %{ "testl   rax, [$poll]\t"
12966             "# Safepoint: poll for GC" %}
12967   ins_cost(125);
12968   size(4); /* setting an explicit size will cause debug builds to assert if size is incorrect */
12969   ins_encode %{
12970     __ relocate(relocInfo::poll_type);
12971     address pre_pc = __ pc();
12972     __ testl(rax, Address($poll$$Register, 0));
12973     assert(nativeInstruction_at(pre_pc)->is_safepoint_poll(), "must emit test %%eax [reg]");
12974   %}
12975   ins_pipe(ialu_reg_mem);
12976 %}
12977 
12978 // ============================================================================
12979 // Procedure Call/Return Instructions
12980 // Call Java Static Instruction
12981 // Note: If this code changes, the corresponding ret_addr_offset() and
12982 //       compute_padding() functions will have to be adjusted.
12983 instruct CallStaticJavaDirect(method meth) %{
12984   match(CallStaticJava);
12985   effect(USE meth);
12986 
12987   ins_cost(300);
12988   format %{ "call,static " %}
12989   opcode(0xE8); /* E8 cd */
12990   ins_encode(clear_avx, Java_Static_Call(meth), call_epilog);
12991   ins_pipe(pipe_slow);
12992   ins_alignment(4);
12993 %}
12994 
12995 // Call Java Dynamic Instruction
12996 // Note: If this code changes, the corresponding ret_addr_offset() and
12997 //       compute_padding() functions will have to be adjusted.
12998 instruct CallDynamicJavaDirect(method meth)
12999 %{
13000   match(CallDynamicJava);
13001   effect(USE meth);
13002 
13003   ins_cost(300);
13004   format %{ "movq    rax, #Universe::non_oop_word()\n\t"
13005             "call,dynamic " %}
13006   ins_encode(clear_avx, Java_Dynamic_Call(meth), call_epilog);
13007   ins_pipe(pipe_slow);
13008   ins_alignment(4);
13009 %}
13010 
13011 // Call Runtime Instruction
13012 instruct CallRuntimeDirect(method meth)
13013 %{
13014   match(CallRuntime);
13015   effect(USE meth);
13016 
13017   ins_cost(300);
13018   format %{ "call,runtime " %}
13019   ins_encode(clear_avx, Java_To_Runtime(meth));
13020   ins_pipe(pipe_slow);
13021 %}
13022 
13023 // Call runtime without safepoint
13024 instruct CallLeafDirect(method meth)
13025 %{
13026   match(CallLeaf);
13027   effect(USE meth);
13028 
13029   ins_cost(300);
13030   format %{ "call_leaf,runtime " %}
13031   ins_encode(clear_avx, Java_To_Runtime(meth));
13032   ins_pipe(pipe_slow);
13033 %}
13034 
13035 // Call runtime without safepoint and with vector arguments
13036 instruct CallLeafDirectVector(method meth)
13037 %{
13038   match(CallLeafVector);
13039   effect(USE meth);
13040 
13041   ins_cost(300);
13042   format %{ "call_leaf,vector " %}
13043   ins_encode(Java_To_Runtime(meth));
13044   ins_pipe(pipe_slow);
13045 %}
13046 
13047 //
13048 instruct CallNativeDirect(method meth)
13049 %{
13050   match(CallNative);
13051   effect(USE meth);
13052 
13053   ins_cost(300);
13054   format %{ "call_native " %}
13055   ins_encode(clear_avx, Java_To_Runtime(meth));
13056   ins_pipe(pipe_slow);
13057 %}
13058 
13059 // Call runtime without safepoint
13060 instruct CallLeafNoFPDirect(method meth)
13061 %{
13062   match(CallLeafNoFP);
13063   effect(USE meth);
13064 
13065   ins_cost(300);
13066   format %{ "call_leaf_nofp,runtime " %}
13067   ins_encode(clear_avx, Java_To_Runtime(meth));
13068   ins_pipe(pipe_slow);
13069 %}
13070 
13071 // Return Instruction
13072 // Remove the return address & jump to it.
13073 // Notice: We always emit a nop after a ret to make sure there is room
13074 // for safepoint patching
13075 instruct Ret()
13076 %{
13077   match(Return);
13078 
13079   format %{ "ret" %}
13080   ins_encode %{
13081     __ ret(0);
13082   %}
13083   ins_pipe(pipe_jmp);
13084 %}
13085 
13086 // Tail Call; Jump from runtime stub to Java code.
13087 // Also known as an 'interprocedural jump'.
13088 // Target of jump will eventually return to caller.
13089 // TailJump below removes the return address.
13090 instruct TailCalljmpInd(no_rbp_RegP jump_target, rbx_RegP method_ptr)
13091 %{
13092   match(TailCall jump_target method_ptr);
13093 
13094   ins_cost(300);
13095   format %{ "jmp     $jump_target\t# rbx holds method" %}
13096   ins_encode %{
13097     __ jmp($jump_target$$Register);
13098   %}
13099   ins_pipe(pipe_jmp);
13100 %}
13101 
13102 // Tail Jump; remove the return address; jump to target.
13103 // TailCall above leaves the return address around.
13104 instruct tailjmpInd(no_rbp_RegP jump_target, rax_RegP ex_oop)
13105 %{
13106   match(TailJump jump_target ex_oop);
13107 
13108   ins_cost(300);
13109   format %{ "popq    rdx\t# pop return address\n\t"
13110             "jmp     $jump_target" %}
13111   ins_encode %{
13112     __ popq(as_Register(RDX_enc));
13113     __ jmp($jump_target$$Register);
13114   %}
13115   ins_pipe(pipe_jmp);
13116 %}
13117 
13118 // Create exception oop: created by stack-crawling runtime code.
13119 // Created exception is now available to this handler, and is setup
13120 // just prior to jumping to this handler.  No code emitted.
13121 instruct CreateException(rax_RegP ex_oop)
13122 %{
13123   match(Set ex_oop (CreateEx));
13124 
13125   size(0);
13126   // use the following format syntax
13127   format %{ "# exception oop is in rax; no code emitted" %}
13128   ins_encode();
13129   ins_pipe(empty);
13130 %}
13131 
13132 // Rethrow exception:
13133 // The exception oop will come in the first argument position.
13134 // Then JUMP (not call) to the rethrow stub code.
13135 instruct RethrowException()
13136 %{
13137   match(Rethrow);
13138 
13139   // use the following format syntax
13140   format %{ "jmp     rethrow_stub" %}
13141   ins_encode(enc_rethrow);
13142   ins_pipe(pipe_jmp);
13143 %}
13144 
13145 // ============================================================================
13146 // This name is KNOWN by the ADLC and cannot be changed.
13147 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
13148 // for this guy.
13149 instruct tlsLoadP(r15_RegP dst) %{
13150   match(Set dst (ThreadLocal));
13151   effect(DEF dst);
13152 
13153   size(0);
13154   format %{ "# TLS is in R15" %}
13155   ins_encode( /*empty encoding*/ );
13156   ins_pipe(ialu_reg_reg);
13157 %}
13158 
13159 
13160 //----------PEEPHOLE RULES-----------------------------------------------------
13161 // These must follow all instruction definitions as they use the names
13162 // defined in the instructions definitions.
13163 //
13164 // peepmatch ( root_instr_name [preceding_instruction]* );
13165 //
13166 // peepconstraint %{
13167 // (instruction_number.operand_name relational_op instruction_number.operand_name
13168 //  [, ...] );
13169 // // instruction numbers are zero-based using left to right order in peepmatch
13170 //
13171 // peepreplace ( instr_name  ( [instruction_number.operand_name]* ) );
13172 // // provide an instruction_number.operand_name for each operand that appears
13173 // // in the replacement instruction's match rule
13174 //
13175 // ---------VM FLAGS---------------------------------------------------------
13176 //
13177 // All peephole optimizations can be turned off using -XX:-OptoPeephole
13178 //
13179 // Each peephole rule is given an identifying number starting with zero and
13180 // increasing by one in the order seen by the parser.  An individual peephole
13181 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
13182 // on the command-line.
13183 //
13184 // ---------CURRENT LIMITATIONS----------------------------------------------
13185 //
13186 // Only match adjacent instructions in same basic block
13187 // Only equality constraints
13188 // Only constraints between operands, not (0.dest_reg == RAX_enc)
13189 // Only one replacement instruction
13190 //
13191 // ---------EXAMPLE----------------------------------------------------------
13192 //
13193 // // pertinent parts of existing instructions in architecture description
13194 // instruct movI(rRegI dst, rRegI src)
13195 // %{
13196 //   match(Set dst (CopyI src));
13197 // %}
13198 //
13199 // instruct incI_rReg(rRegI dst, immI_1 src, rFlagsReg cr)
13200 // %{
13201 //   match(Set dst (AddI dst src));
13202 //   effect(KILL cr);
13203 // %}
13204 //
13205 // // Change (inc mov) to lea
13206 // peephole %{
13207 //   // increment preceeded by register-register move
13208 //   peepmatch ( incI_rReg movI );
13209 //   // require that the destination register of the increment
13210 //   // match the destination register of the move
13211 //   peepconstraint ( 0.dst == 1.dst );
13212 //   // construct a replacement instruction that sets
13213 //   // the destination to ( move's source register + one )
13214 //   peepreplace ( leaI_rReg_immI( 0.dst 1.src 0.src ) );
13215 // %}
13216 //
13217 
13218 // Implementation no longer uses movX instructions since
13219 // machine-independent system no longer uses CopyX nodes.
13220 //
13221 // peephole
13222 // %{
13223 //   peepmatch (incI_rReg movI);
13224 //   peepconstraint (0.dst == 1.dst);
13225 //   peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
13226 // %}
13227 
13228 // peephole
13229 // %{
13230 //   peepmatch (decI_rReg movI);
13231 //   peepconstraint (0.dst == 1.dst);
13232 //   peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
13233 // %}
13234 
13235 // peephole
13236 // %{
13237 //   peepmatch (addI_rReg_imm movI);
13238 //   peepconstraint (0.dst == 1.dst);
13239 //   peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
13240 // %}
13241 
13242 // peephole
13243 // %{
13244 //   peepmatch (incL_rReg movL);
13245 //   peepconstraint (0.dst == 1.dst);
13246 //   peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
13247 // %}
13248 
13249 // peephole
13250 // %{
13251 //   peepmatch (decL_rReg movL);
13252 //   peepconstraint (0.dst == 1.dst);
13253 //   peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
13254 // %}
13255 
13256 // peephole
13257 // %{
13258 //   peepmatch (addL_rReg_imm movL);
13259 //   peepconstraint (0.dst == 1.dst);
13260 //   peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
13261 // %}
13262 
13263 // peephole
13264 // %{
13265 //   peepmatch (addP_rReg_imm movP);
13266 //   peepconstraint (0.dst == 1.dst);
13267 //   peepreplace (leaP_rReg_imm(0.dst 1.src 0.src));
13268 // %}
13269 
13270 // // Change load of spilled value to only a spill
13271 // instruct storeI(memory mem, rRegI src)
13272 // %{
13273 //   match(Set mem (StoreI mem src));
13274 // %}
13275 //
13276 // instruct loadI(rRegI dst, memory mem)
13277 // %{
13278 //   match(Set dst (LoadI mem));
13279 // %}
13280 //
13281 
13282 peephole
13283 %{
13284   peepmatch (loadI storeI);
13285   peepconstraint (1.src == 0.dst, 1.mem == 0.mem);
13286   peepreplace (storeI(1.mem 1.mem 1.src));
13287 %}
13288 
13289 peephole
13290 %{
13291   peepmatch (loadL storeL);
13292   peepconstraint (1.src == 0.dst, 1.mem == 0.mem);
13293   peepreplace (storeL(1.mem 1.mem 1.src));
13294 %}
13295 
13296 //----------SMARTSPILL RULES---------------------------------------------------
13297 // These must follow all instruction definitions as they use the names
13298 // defined in the instructions definitions.