1 //
2 // Copyright (c) 2003, 2021, Oracle and/or its affiliates. All rights reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 // or visit www.oracle.com if you need additional information or have any
21 // questions.
22 //
23 //
24
25 // AMD64 Architecture Description File
26
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
31
32 register %{
33 //----------Architecture Description Register Definitions----------------------
34 // General Registers
35 // "reg_def" name ( register save type, C convention save type,
36 // ideal register type, encoding );
37 // Register Save Types:
38 //
39 // NS = No-Save: The register allocator assumes that these registers
40 // can be used without saving upon entry to the method, &
41 // that they do not need to be saved at call sites.
42 //
43 // SOC = Save-On-Call: The register allocator assumes that these registers
44 // can be used without saving upon entry to the method,
45 // but that they must be saved at call sites.
46 //
47 // SOE = Save-On-Entry: The register allocator assumes that these registers
48 // must be saved before using them upon entry to the
49 // method, but they do not need to be saved at call
50 // sites.
51 //
52 // AS = Always-Save: The register allocator assumes that these registers
53 // must be saved before using them upon entry to the
54 // method, & that they must be saved at call sites.
55 //
56 // Ideal Register Type is used to determine how to save & restore a
57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
59 //
60 // The encoding number is the actual bit-pattern placed into the opcodes.
61
62 // General Registers
63 // R8-R15 must be encoded with REX. (RSP, RBP, RSI, RDI need REX when
64 // used as byte registers)
65
66 // Previously set RBX, RSI, and RDI as save-on-entry for java code
67 // Turn off SOE in java-code due to frequent use of uncommon-traps.
68 // Now that allocator is better, turn on RSI and RDI as SOE registers.
69
70 reg_def RAX (SOC, SOC, Op_RegI, 0, rax->as_VMReg());
71 reg_def RAX_H(SOC, SOC, Op_RegI, 0, rax->as_VMReg()->next());
72
73 reg_def RCX (SOC, SOC, Op_RegI, 1, rcx->as_VMReg());
74 reg_def RCX_H(SOC, SOC, Op_RegI, 1, rcx->as_VMReg()->next());
75
76 reg_def RDX (SOC, SOC, Op_RegI, 2, rdx->as_VMReg());
77 reg_def RDX_H(SOC, SOC, Op_RegI, 2, rdx->as_VMReg()->next());
78
79 reg_def RBX (SOC, SOE, Op_RegI, 3, rbx->as_VMReg());
80 reg_def RBX_H(SOC, SOE, Op_RegI, 3, rbx->as_VMReg()->next());
81
82 reg_def RSP (NS, NS, Op_RegI, 4, rsp->as_VMReg());
83 reg_def RSP_H(NS, NS, Op_RegI, 4, rsp->as_VMReg()->next());
84
85 // now that adapter frames are gone RBP is always saved and restored by the prolog/epilog code
86 reg_def RBP (NS, SOE, Op_RegI, 5, rbp->as_VMReg());
87 reg_def RBP_H(NS, SOE, Op_RegI, 5, rbp->as_VMReg()->next());
88
89 #ifdef _WIN64
90
91 reg_def RSI (SOC, SOE, Op_RegI, 6, rsi->as_VMReg());
92 reg_def RSI_H(SOC, SOE, Op_RegI, 6, rsi->as_VMReg()->next());
93
94 reg_def RDI (SOC, SOE, Op_RegI, 7, rdi->as_VMReg());
95 reg_def RDI_H(SOC, SOE, Op_RegI, 7, rdi->as_VMReg()->next());
96
97 #else
98
99 reg_def RSI (SOC, SOC, Op_RegI, 6, rsi->as_VMReg());
100 reg_def RSI_H(SOC, SOC, Op_RegI, 6, rsi->as_VMReg()->next());
101
102 reg_def RDI (SOC, SOC, Op_RegI, 7, rdi->as_VMReg());
103 reg_def RDI_H(SOC, SOC, Op_RegI, 7, rdi->as_VMReg()->next());
104
105 #endif
106
107 reg_def R8 (SOC, SOC, Op_RegI, 8, r8->as_VMReg());
108 reg_def R8_H (SOC, SOC, Op_RegI, 8, r8->as_VMReg()->next());
109
110 reg_def R9 (SOC, SOC, Op_RegI, 9, r9->as_VMReg());
111 reg_def R9_H (SOC, SOC, Op_RegI, 9, r9->as_VMReg()->next());
112
113 reg_def R10 (SOC, SOC, Op_RegI, 10, r10->as_VMReg());
114 reg_def R10_H(SOC, SOC, Op_RegI, 10, r10->as_VMReg()->next());
115
116 reg_def R11 (SOC, SOC, Op_RegI, 11, r11->as_VMReg());
117 reg_def R11_H(SOC, SOC, Op_RegI, 11, r11->as_VMReg()->next());
118
119 reg_def R12 (SOC, SOE, Op_RegI, 12, r12->as_VMReg());
120 reg_def R12_H(SOC, SOE, Op_RegI, 12, r12->as_VMReg()->next());
121
122 reg_def R13 (SOC, SOE, Op_RegI, 13, r13->as_VMReg());
123 reg_def R13_H(SOC, SOE, Op_RegI, 13, r13->as_VMReg()->next());
124
125 reg_def R14 (SOC, SOE, Op_RegI, 14, r14->as_VMReg());
126 reg_def R14_H(SOC, SOE, Op_RegI, 14, r14->as_VMReg()->next());
127
128 reg_def R15 (SOC, SOE, Op_RegI, 15, r15->as_VMReg());
129 reg_def R15_H(SOC, SOE, Op_RegI, 15, r15->as_VMReg()->next());
130
131
132 // Floating Point Registers
133
134 // Specify priority of register selection within phases of register
135 // allocation. Highest priority is first. A useful heuristic is to
136 // give registers a low priority when they are required by machine
137 // instructions, like EAX and EDX on I486, and choose no-save registers
138 // before save-on-call, & save-on-call before save-on-entry. Registers
139 // which participate in fixed calling sequences should come last.
140 // Registers which are used as pairs must fall on an even boundary.
141
142 alloc_class chunk0(R10, R10_H,
143 R11, R11_H,
144 R8, R8_H,
145 R9, R9_H,
146 R12, R12_H,
147 RCX, RCX_H,
148 RBX, RBX_H,
149 RDI, RDI_H,
150 RDX, RDX_H,
151 RSI, RSI_H,
152 RAX, RAX_H,
153 RBP, RBP_H,
154 R13, R13_H,
155 R14, R14_H,
156 R15, R15_H,
157 RSP, RSP_H);
158
159
160 //----------Architecture Description Register Classes--------------------------
161 // Several register classes are automatically defined based upon information in
162 // this architecture description.
163 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
164 // 2) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
165 //
166
167 // Empty register class.
168 reg_class no_reg();
169
170 // Class for all pointer/long registers
171 reg_class all_reg(RAX, RAX_H,
172 RDX, RDX_H,
173 RBP, RBP_H,
174 RDI, RDI_H,
175 RSI, RSI_H,
176 RCX, RCX_H,
177 RBX, RBX_H,
178 RSP, RSP_H,
179 R8, R8_H,
180 R9, R9_H,
181 R10, R10_H,
182 R11, R11_H,
183 R12, R12_H,
184 R13, R13_H,
185 R14, R14_H,
186 R15, R15_H);
187
188 // Class for all int registers
189 reg_class all_int_reg(RAX
190 RDX,
191 RBP,
192 RDI,
193 RSI,
194 RCX,
195 RBX,
196 R8,
197 R9,
198 R10,
199 R11,
200 R12,
201 R13,
202 R14);
203
204 // Class for all pointer registers
205 reg_class any_reg %{
206 return _ANY_REG_mask;
207 %}
208
209 // Class for all pointer registers (excluding RSP)
210 reg_class ptr_reg %{
211 return _PTR_REG_mask;
212 %}
213
214 // Class for all pointer registers (excluding RSP and RBP)
215 reg_class ptr_reg_no_rbp %{
216 return _PTR_REG_NO_RBP_mask;
217 %}
218
219 // Class for all pointer registers (excluding RAX and RSP)
220 reg_class ptr_no_rax_reg %{
221 return _PTR_NO_RAX_REG_mask;
222 %}
223
224 // Class for all pointer registers (excluding RAX, RBX, and RSP)
225 reg_class ptr_no_rax_rbx_reg %{
226 return _PTR_NO_RAX_RBX_REG_mask;
227 %}
228
229 // Class for all long registers (excluding RSP)
230 reg_class long_reg %{
231 return _LONG_REG_mask;
232 %}
233
234 // Class for all long registers (excluding RAX, RDX and RSP)
235 reg_class long_no_rax_rdx_reg %{
236 return _LONG_NO_RAX_RDX_REG_mask;
237 %}
238
239 // Class for all long registers (excluding RCX and RSP)
240 reg_class long_no_rcx_reg %{
241 return _LONG_NO_RCX_REG_mask;
242 %}
243
244 // Class for all int registers (excluding RSP)
245 reg_class int_reg %{
246 return _INT_REG_mask;
247 %}
248
249 // Class for all int registers (excluding RAX, RDX, and RSP)
250 reg_class int_no_rax_rdx_reg %{
251 return _INT_NO_RAX_RDX_REG_mask;
252 %}
253
254 // Class for all int registers (excluding RCX and RSP)
255 reg_class int_no_rcx_reg %{
256 return _INT_NO_RCX_REG_mask;
257 %}
258
259 // Singleton class for RAX pointer register
260 reg_class ptr_rax_reg(RAX, RAX_H);
261
262 // Singleton class for RBX pointer register
263 reg_class ptr_rbx_reg(RBX, RBX_H);
264
265 // Singleton class for RSI pointer register
266 reg_class ptr_rsi_reg(RSI, RSI_H);
267
268 // Singleton class for RBP pointer register
269 reg_class ptr_rbp_reg(RBP, RBP_H);
270
271 // Singleton class for RDI pointer register
272 reg_class ptr_rdi_reg(RDI, RDI_H);
273
274 // Singleton class for stack pointer
275 reg_class ptr_rsp_reg(RSP, RSP_H);
276
277 // Singleton class for TLS pointer
278 reg_class ptr_r15_reg(R15, R15_H);
279
280 // Singleton class for RAX long register
281 reg_class long_rax_reg(RAX, RAX_H);
282
283 // Singleton class for RCX long register
284 reg_class long_rcx_reg(RCX, RCX_H);
285
286 // Singleton class for RDX long register
287 reg_class long_rdx_reg(RDX, RDX_H);
288
289 // Singleton class for RAX int register
290 reg_class int_rax_reg(RAX);
291
292 // Singleton class for RBX int register
293 reg_class int_rbx_reg(RBX);
294
295 // Singleton class for RCX int register
296 reg_class int_rcx_reg(RCX);
297
298 // Singleton class for RCX int register
299 reg_class int_rdx_reg(RDX);
300
301 // Singleton class for RCX int register
302 reg_class int_rdi_reg(RDI);
303
304 // Singleton class for instruction pointer
305 // reg_class ip_reg(RIP);
306
307 %}
308
309 //----------SOURCE BLOCK-------------------------------------------------------
310 // This is a block of C++ code which provides values, functions, and
311 // definitions necessary in the rest of the architecture description
312 source_hpp %{
313
314 extern RegMask _ANY_REG_mask;
315 extern RegMask _PTR_REG_mask;
316 extern RegMask _PTR_REG_NO_RBP_mask;
317 extern RegMask _PTR_NO_RAX_REG_mask;
318 extern RegMask _PTR_NO_RAX_RBX_REG_mask;
319 extern RegMask _LONG_REG_mask;
320 extern RegMask _LONG_NO_RAX_RDX_REG_mask;
321 extern RegMask _LONG_NO_RCX_REG_mask;
322 extern RegMask _INT_REG_mask;
323 extern RegMask _INT_NO_RAX_RDX_REG_mask;
324 extern RegMask _INT_NO_RCX_REG_mask;
325
326 extern RegMask _STACK_OR_PTR_REG_mask;
327 extern RegMask _STACK_OR_LONG_REG_mask;
328 extern RegMask _STACK_OR_INT_REG_mask;
329
330 inline const RegMask& STACK_OR_PTR_REG_mask() { return _STACK_OR_PTR_REG_mask; }
331 inline const RegMask& STACK_OR_LONG_REG_mask() { return _STACK_OR_LONG_REG_mask; }
332 inline const RegMask& STACK_OR_INT_REG_mask() { return _STACK_OR_INT_REG_mask; }
333
334 %}
335
336 source %{
337 #define RELOC_IMM64 Assembler::imm_operand
338 #define RELOC_DISP32 Assembler::disp32_operand
339
340 #define __ _masm.
341
342 RegMask _ANY_REG_mask;
343 RegMask _PTR_REG_mask;
344 RegMask _PTR_REG_NO_RBP_mask;
345 RegMask _PTR_NO_RAX_REG_mask;
346 RegMask _PTR_NO_RAX_RBX_REG_mask;
347 RegMask _LONG_REG_mask;
348 RegMask _LONG_NO_RAX_RDX_REG_mask;
349 RegMask _LONG_NO_RCX_REG_mask;
350 RegMask _INT_REG_mask;
351 RegMask _INT_NO_RAX_RDX_REG_mask;
352 RegMask _INT_NO_RCX_REG_mask;
353 RegMask _STACK_OR_PTR_REG_mask;
354 RegMask _STACK_OR_LONG_REG_mask;
355 RegMask _STACK_OR_INT_REG_mask;
356
357 static bool need_r12_heapbase() {
358 return UseCompressedOops;
359 }
360
361 void reg_mask_init() {
362 // _ALL_REG_mask is generated by adlc from the all_reg register class below.
363 // We derive a number of subsets from it.
364 _ANY_REG_mask = _ALL_REG_mask;
365
366 if (PreserveFramePointer) {
367 _ANY_REG_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()));
368 _ANY_REG_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()->next()));
369 }
370 if (need_r12_heapbase()) {
371 _ANY_REG_mask.Remove(OptoReg::as_OptoReg(r12->as_VMReg()));
372 _ANY_REG_mask.Remove(OptoReg::as_OptoReg(r12->as_VMReg()->next()));
373 }
374
375 _PTR_REG_mask = _ANY_REG_mask;
376 _PTR_REG_mask.Remove(OptoReg::as_OptoReg(rsp->as_VMReg()));
377 _PTR_REG_mask.Remove(OptoReg::as_OptoReg(rsp->as_VMReg()->next()));
378 _PTR_REG_mask.Remove(OptoReg::as_OptoReg(r15->as_VMReg()));
379 _PTR_REG_mask.Remove(OptoReg::as_OptoReg(r15->as_VMReg()->next()));
380
381 _STACK_OR_PTR_REG_mask = _PTR_REG_mask;
382 _STACK_OR_PTR_REG_mask.OR(STACK_OR_STACK_SLOTS_mask());
383
384 _PTR_REG_NO_RBP_mask = _PTR_REG_mask;
385 _PTR_REG_NO_RBP_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()));
386 _PTR_REG_NO_RBP_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()->next()));
387
388 _PTR_NO_RAX_REG_mask = _PTR_REG_mask;
389 _PTR_NO_RAX_REG_mask.Remove(OptoReg::as_OptoReg(rax->as_VMReg()));
390 _PTR_NO_RAX_REG_mask.Remove(OptoReg::as_OptoReg(rax->as_VMReg()->next()));
391
392 _PTR_NO_RAX_RBX_REG_mask = _PTR_NO_RAX_REG_mask;
393 _PTR_NO_RAX_RBX_REG_mask.Remove(OptoReg::as_OptoReg(rbx->as_VMReg()));
394 _PTR_NO_RAX_RBX_REG_mask.Remove(OptoReg::as_OptoReg(rbx->as_VMReg()->next()));
395
396 _LONG_REG_mask = _PTR_REG_mask;
397 _STACK_OR_LONG_REG_mask = _LONG_REG_mask;
398 _STACK_OR_LONG_REG_mask.OR(STACK_OR_STACK_SLOTS_mask());
399
400 _LONG_NO_RAX_RDX_REG_mask = _LONG_REG_mask;
401 _LONG_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rax->as_VMReg()));
402 _LONG_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rax->as_VMReg()->next()));
403 _LONG_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rdx->as_VMReg()));
404 _LONG_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rdx->as_VMReg()->next()));
405
406 _LONG_NO_RCX_REG_mask = _LONG_REG_mask;
407 _LONG_NO_RCX_REG_mask.Remove(OptoReg::as_OptoReg(rcx->as_VMReg()));
408 _LONG_NO_RCX_REG_mask.Remove(OptoReg::as_OptoReg(rcx->as_VMReg()->next()));
409
410 _INT_REG_mask = _ALL_INT_REG_mask;
411 if (PreserveFramePointer) {
412 _INT_REG_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()));
413 }
414 if (need_r12_heapbase()) {
415 _INT_REG_mask.Remove(OptoReg::as_OptoReg(r12->as_VMReg()));
416 }
417
418 _STACK_OR_INT_REG_mask = _INT_REG_mask;
419 _STACK_OR_INT_REG_mask.OR(STACK_OR_STACK_SLOTS_mask());
420
421 _INT_NO_RAX_RDX_REG_mask = _INT_REG_mask;
422 _INT_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rax->as_VMReg()));
423 _INT_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rdx->as_VMReg()));
424
425 _INT_NO_RCX_REG_mask = _INT_REG_mask;
426 _INT_NO_RCX_REG_mask.Remove(OptoReg::as_OptoReg(rcx->as_VMReg()));
427
428 if (Matcher::has_predicated_vectors()) {
429 // Post-loop multi-versioning expects mask to be present in K1 register, till the time
430 // its fixed, RA should not be allocting K1 register, this shall prevent any accidental
431 // curruption of value held in K1 register.
432 if (PostLoopMultiversioning) {
433 const_cast<RegMask*>(&_VECTMASK_REG_mask)->Remove(OptoReg::as_OptoReg(k1->as_VMReg()));
434 const_cast<RegMask*>(&_VECTMASK_REG_mask)->Remove(OptoReg::as_OptoReg(k1->as_VMReg()->next()));
435 }
436 }
437 }
438
439 static bool generate_vzeroupper(Compile* C) {
440 return (VM_Version::supports_vzeroupper() && (C->max_vector_size() > 16 || C->clear_upper_avx() == true)) ? true: false; // Generate vzeroupper
441 }
442
443 static int clear_avx_size() {
444 return generate_vzeroupper(Compile::current()) ? 3: 0; // vzeroupper
445 }
446
447 // !!!!! Special hack to get all types of calls to specify the byte offset
448 // from the start of the call to the point where the return address
449 // will point.
450 int MachCallStaticJavaNode::ret_addr_offset()
451 {
452 int offset = 5; // 5 bytes from start of call to where return address points
453 offset += clear_avx_size();
454 return offset;
455 }
456
457 int MachCallDynamicJavaNode::ret_addr_offset()
458 {
459 int offset = 15; // 15 bytes from start of call to where return address points
460 offset += clear_avx_size();
461 return offset;
462 }
463
464 int MachCallRuntimeNode::ret_addr_offset() {
465 int offset = 13; // movq r10,#addr; callq (r10)
466 if (this->ideal_Opcode() != Op_CallLeafVector) {
467 offset += clear_avx_size();
468 }
469 return offset;
470 }
471
472 int MachCallNativeNode::ret_addr_offset() {
473 int offset = 13; // movq r10,#addr; callq (r10)
474 offset += clear_avx_size();
475 return offset;
476 }
477 //
478 // Compute padding required for nodes which need alignment
479 //
480
481 // The address of the call instruction needs to be 4-byte aligned to
482 // ensure that it does not span a cache line so that it can be patched.
483 int CallStaticJavaDirectNode::compute_padding(int current_offset) const
484 {
485 current_offset += clear_avx_size(); // skip vzeroupper
486 current_offset += 1; // skip call opcode byte
487 return align_up(current_offset, alignment_required()) - current_offset;
488 }
489
490 // The address of the call instruction needs to be 4-byte aligned to
491 // ensure that it does not span a cache line so that it can be patched.
492 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const
493 {
494 current_offset += clear_avx_size(); // skip vzeroupper
495 current_offset += 11; // skip movq instruction + call opcode byte
496 return align_up(current_offset, alignment_required()) - current_offset;
497 }
498
499 // EMIT_RM()
500 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
501 unsigned char c = (unsigned char) ((f1 << 6) | (f2 << 3) | f3);
502 cbuf.insts()->emit_int8(c);
503 }
504
505 // EMIT_CC()
506 void emit_cc(CodeBuffer &cbuf, int f1, int f2) {
507 unsigned char c = (unsigned char) (f1 | f2);
508 cbuf.insts()->emit_int8(c);
509 }
510
511 // EMIT_OPCODE()
512 void emit_opcode(CodeBuffer &cbuf, int code) {
513 cbuf.insts()->emit_int8((unsigned char) code);
514 }
515
516 // EMIT_OPCODE() w/ relocation information
517 void emit_opcode(CodeBuffer &cbuf,
518 int code, relocInfo::relocType reloc, int offset, int format)
519 {
520 cbuf.relocate(cbuf.insts_mark() + offset, reloc, format);
521 emit_opcode(cbuf, code);
522 }
523
524 // EMIT_D8()
525 void emit_d8(CodeBuffer &cbuf, int d8) {
526 cbuf.insts()->emit_int8((unsigned char) d8);
527 }
528
529 // EMIT_D16()
530 void emit_d16(CodeBuffer &cbuf, int d16) {
531 cbuf.insts()->emit_int16(d16);
532 }
533
534 // EMIT_D32()
535 void emit_d32(CodeBuffer &cbuf, int d32) {
536 cbuf.insts()->emit_int32(d32);
537 }
538
539 // EMIT_D64()
540 void emit_d64(CodeBuffer &cbuf, int64_t d64) {
541 cbuf.insts()->emit_int64(d64);
542 }
543
544 // emit 32 bit value and construct relocation entry from relocInfo::relocType
545 void emit_d32_reloc(CodeBuffer& cbuf,
546 int d32,
547 relocInfo::relocType reloc,
548 int format)
549 {
550 assert(reloc != relocInfo::external_word_type, "use 2-arg emit_d32_reloc");
551 cbuf.relocate(cbuf.insts_mark(), reloc, format);
552 cbuf.insts()->emit_int32(d32);
553 }
554
555 // emit 32 bit value and construct relocation entry from RelocationHolder
556 void emit_d32_reloc(CodeBuffer& cbuf, int d32, RelocationHolder const& rspec, int format) {
557 #ifdef ASSERT
558 if (rspec.reloc()->type() == relocInfo::oop_type &&
559 d32 != 0 && d32 != (intptr_t) Universe::non_oop_word()) {
560 assert(Universe::heap()->is_in((address)(intptr_t)d32), "should be real oop");
561 assert(oopDesc::is_oop(cast_to_oop((intptr_t)d32)), "cannot embed broken oops in code");
562 }
563 #endif
564 cbuf.relocate(cbuf.insts_mark(), rspec, format);
565 cbuf.insts()->emit_int32(d32);
566 }
567
568 void emit_d32_reloc(CodeBuffer& cbuf, address addr) {
569 address next_ip = cbuf.insts_end() + 4;
570 emit_d32_reloc(cbuf, (int) (addr - next_ip),
571 external_word_Relocation::spec(addr),
572 RELOC_DISP32);
573 }
574
575
576 // emit 64 bit value and construct relocation entry from relocInfo::relocType
577 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, relocInfo::relocType reloc, int format) {
578 cbuf.relocate(cbuf.insts_mark(), reloc, format);
579 cbuf.insts()->emit_int64(d64);
580 }
581
582 // emit 64 bit value and construct relocation entry from RelocationHolder
583 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, RelocationHolder const& rspec, int format) {
584 #ifdef ASSERT
585 if (rspec.reloc()->type() == relocInfo::oop_type &&
586 d64 != 0 && d64 != (int64_t) Universe::non_oop_word()) {
587 assert(Universe::heap()->is_in((address)d64), "should be real oop");
588 assert(oopDesc::is_oop(cast_to_oop(d64)), "cannot embed broken oops in code");
589 }
590 #endif
591 cbuf.relocate(cbuf.insts_mark(), rspec, format);
592 cbuf.insts()->emit_int64(d64);
593 }
594
595 // Access stack slot for load or store
596 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp)
597 {
598 emit_opcode(cbuf, opcode); // (e.g., FILD [RSP+src])
599 if (-0x80 <= disp && disp < 0x80) {
600 emit_rm(cbuf, 0x01, rm_field, RSP_enc); // R/M byte
601 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte
602 emit_d8(cbuf, disp); // Displacement // R/M byte
603 } else {
604 emit_rm(cbuf, 0x02, rm_field, RSP_enc); // R/M byte
605 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte
606 emit_d32(cbuf, disp); // Displacement // R/M byte
607 }
608 }
609
610 // rRegI ereg, memory mem) %{ // emit_reg_mem
611 void encode_RegMem(CodeBuffer &cbuf,
612 int reg,
613 int base, int index, int scale, int disp, relocInfo::relocType disp_reloc)
614 {
615 assert(disp_reloc == relocInfo::none, "cannot have disp");
616 int regenc = reg & 7;
617 int baseenc = base & 7;
618 int indexenc = index & 7;
619
620 // There is no index & no scale, use form without SIB byte
621 if (index == 0x4 && scale == 0 && base != RSP_enc && base != R12_enc) {
622 // If no displacement, mode is 0x0; unless base is [RBP] or [R13]
623 if (disp == 0 && base != RBP_enc && base != R13_enc) {
624 emit_rm(cbuf, 0x0, regenc, baseenc); // *
625 } else if (-0x80 <= disp && disp < 0x80 && disp_reloc == relocInfo::none) {
626 // If 8-bit displacement, mode 0x1
627 emit_rm(cbuf, 0x1, regenc, baseenc); // *
628 emit_d8(cbuf, disp);
629 } else {
630 // If 32-bit displacement
631 if (base == -1) { // Special flag for absolute address
632 emit_rm(cbuf, 0x0, regenc, 0x5); // *
633 if (disp_reloc != relocInfo::none) {
634 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
635 } else {
636 emit_d32(cbuf, disp);
637 }
638 } else {
639 // Normal base + offset
640 emit_rm(cbuf, 0x2, regenc, baseenc); // *
641 if (disp_reloc != relocInfo::none) {
642 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
643 } else {
644 emit_d32(cbuf, disp);
645 }
646 }
647 }
648 } else {
649 // Else, encode with the SIB byte
650 // If no displacement, mode is 0x0; unless base is [RBP] or [R13]
651 if (disp == 0 && base != RBP_enc && base != R13_enc) {
652 // If no displacement
653 emit_rm(cbuf, 0x0, regenc, 0x4); // *
654 emit_rm(cbuf, scale, indexenc, baseenc);
655 } else {
656 if (-0x80 <= disp && disp < 0x80 && disp_reloc == relocInfo::none) {
657 // If 8-bit displacement, mode 0x1
658 emit_rm(cbuf, 0x1, regenc, 0x4); // *
659 emit_rm(cbuf, scale, indexenc, baseenc);
660 emit_d8(cbuf, disp);
661 } else {
662 // If 32-bit displacement
663 if (base == 0x04 ) {
664 emit_rm(cbuf, 0x2, regenc, 0x4);
665 emit_rm(cbuf, scale, indexenc, 0x04); // XXX is this valid???
666 } else {
667 emit_rm(cbuf, 0x2, regenc, 0x4);
668 emit_rm(cbuf, scale, indexenc, baseenc); // *
669 }
670 if (disp_reloc != relocInfo::none) {
671 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
672 } else {
673 emit_d32(cbuf, disp);
674 }
675 }
676 }
677 }
678 }
679
680 // This could be in MacroAssembler but it's fairly C2 specific
681 void emit_cmpfp_fixup(MacroAssembler& _masm) {
682 Label exit;
683 __ jccb(Assembler::noParity, exit);
684 __ pushf();
685 //
686 // comiss/ucomiss instructions set ZF,PF,CF flags and
687 // zero OF,AF,SF for NaN values.
688 // Fixup flags by zeroing ZF,PF so that compare of NaN
689 // values returns 'less than' result (CF is set).
690 // Leave the rest of flags unchanged.
691 //
692 // 7 6 5 4 3 2 1 0
693 // |S|Z|r|A|r|P|r|C| (r - reserved bit)
694 // 0 0 1 0 1 0 1 1 (0x2B)
695 //
696 __ andq(Address(rsp, 0), 0xffffff2b);
697 __ popf();
698 __ bind(exit);
699 }
700
701 void emit_cmpfp3(MacroAssembler& _masm, Register dst) {
702 Label done;
703 __ movl(dst, -1);
704 __ jcc(Assembler::parity, done);
705 __ jcc(Assembler::below, done);
706 __ setb(Assembler::notEqual, dst);
707 __ movzbl(dst, dst);
708 __ bind(done);
709 }
710
711 // Math.min() # Math.max()
712 // --------------------------
713 // ucomis[s/d] #
714 // ja -> b # a
715 // jp -> NaN # NaN
716 // jb -> a # b
717 // je #
718 // |-jz -> a | b # a & b
719 // | -> a #
720 void emit_fp_min_max(MacroAssembler& _masm, XMMRegister dst,
721 XMMRegister a, XMMRegister b,
722 XMMRegister xmmt, Register rt,
723 bool min, bool single) {
724
725 Label nan, zero, below, above, done;
726
727 if (single)
728 __ ucomiss(a, b);
729 else
730 __ ucomisd(a, b);
731
732 if (dst->encoding() != (min ? b : a)->encoding())
733 __ jccb(Assembler::above, above); // CF=0 & ZF=0
734 else
735 __ jccb(Assembler::above, done);
736
737 __ jccb(Assembler::parity, nan); // PF=1
738 __ jccb(Assembler::below, below); // CF=1
739
740 // equal
741 __ vpxor(xmmt, xmmt, xmmt, Assembler::AVX_128bit);
742 if (single) {
743 __ ucomiss(a, xmmt);
744 __ jccb(Assembler::equal, zero);
745
746 __ movflt(dst, a);
747 __ jmp(done);
748 }
749 else {
750 __ ucomisd(a, xmmt);
751 __ jccb(Assembler::equal, zero);
752
753 __ movdbl(dst, a);
754 __ jmp(done);
755 }
756
757 __ bind(zero);
758 if (min)
759 __ vpor(dst, a, b, Assembler::AVX_128bit);
760 else
761 __ vpand(dst, a, b, Assembler::AVX_128bit);
762
763 __ jmp(done);
764
765 __ bind(above);
766 if (single)
767 __ movflt(dst, min ? b : a);
768 else
769 __ movdbl(dst, min ? b : a);
770
771 __ jmp(done);
772
773 __ bind(nan);
774 if (single) {
775 __ movl(rt, 0x7fc00000); // Float.NaN
776 __ movdl(dst, rt);
777 }
778 else {
779 __ mov64(rt, 0x7ff8000000000000L); // Double.NaN
780 __ movdq(dst, rt);
781 }
782 __ jmp(done);
783
784 __ bind(below);
785 if (single)
786 __ movflt(dst, min ? a : b);
787 else
788 __ movdbl(dst, min ? a : b);
789
790 __ bind(done);
791 }
792
793 //=============================================================================
794 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;
795
796 int ConstantTable::calculate_table_base_offset() const {
797 return 0; // absolute addressing, no offset
798 }
799
800 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
801 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
802 ShouldNotReachHere();
803 }
804
805 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
806 // Empty encoding
807 }
808
809 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
810 return 0;
811 }
812
813 #ifndef PRODUCT
814 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
815 st->print("# MachConstantBaseNode (empty encoding)");
816 }
817 #endif
818
819
820 //=============================================================================
821 #ifndef PRODUCT
822 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
823 Compile* C = ra_->C;
824
825 int framesize = C->output()->frame_size_in_bytes();
826 int bangsize = C->output()->bang_size_in_bytes();
827 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
828 // Remove wordSize for return addr which is already pushed.
829 framesize -= wordSize;
830
831 if (C->output()->need_stack_bang(bangsize)) {
832 framesize -= wordSize;
833 st->print("# stack bang (%d bytes)", bangsize);
834 st->print("\n\t");
835 st->print("pushq rbp\t# Save rbp");
836 if (PreserveFramePointer) {
837 st->print("\n\t");
838 st->print("movq rbp, rsp\t# Save the caller's SP into rbp");
839 }
840 if (framesize) {
841 st->print("\n\t");
842 st->print("subq rsp, #%d\t# Create frame",framesize);
843 }
844 } else {
845 st->print("subq rsp, #%d\t# Create frame",framesize);
846 st->print("\n\t");
847 framesize -= wordSize;
848 st->print("movq [rsp + #%d], rbp\t# Save rbp",framesize);
849 if (PreserveFramePointer) {
850 st->print("\n\t");
851 st->print("movq rbp, rsp\t# Save the caller's SP into rbp");
852 if (framesize > 0) {
853 st->print("\n\t");
854 st->print("addq rbp, #%d", framesize);
855 }
856 }
857 }
858
859 if (VerifyStackAtCalls) {
860 st->print("\n\t");
861 framesize -= wordSize;
862 st->print("movq [rsp + #%d], 0xbadb100d\t# Majik cookie for stack depth check",framesize);
863 #ifdef ASSERT
864 st->print("\n\t");
865 st->print("# stack alignment check");
866 #endif
867 }
868 if (C->stub_function() != NULL && BarrierSet::barrier_set()->barrier_set_nmethod() != NULL) {
869 st->print("\n\t");
870 st->print("cmpl [r15_thread + #disarmed_offset], #disarmed_value\t");
871 st->print("\n\t");
872 st->print("je fast_entry\t");
873 st->print("\n\t");
874 st->print("call #nmethod_entry_barrier_stub\t");
875 st->print("\n\tfast_entry:");
876 }
877 st->cr();
878 }
879 #endif
880
881 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
882 Compile* C = ra_->C;
883 MacroAssembler _masm(&cbuf);
884
885 int framesize = C->output()->frame_size_in_bytes();
886 int bangsize = C->output()->bang_size_in_bytes();
887
888 if (C->clinit_barrier_on_entry()) {
889 assert(VM_Version::supports_fast_class_init_checks(), "sanity");
890 assert(!C->method()->holder()->is_not_initialized(), "initialization should have been started");
891
892 Label L_skip_barrier;
893 Register klass = rscratch1;
894
895 __ mov_metadata(klass, C->method()->holder()->constant_encoding());
896 __ clinit_barrier(klass, r15_thread, &L_skip_barrier /*L_fast_path*/);
897
898 __ jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub())); // slow path
899
900 __ bind(L_skip_barrier);
901 }
902
903 __ verified_entry(framesize, C->output()->need_stack_bang(bangsize)?bangsize:0, false, C->stub_function() != NULL);
904
905 C->output()->set_frame_complete(cbuf.insts_size());
906
907 if (C->has_mach_constant_base_node()) {
908 // NOTE: We set the table base offset here because users might be
909 // emitted before MachConstantBaseNode.
910 ConstantTable& constant_table = C->output()->constant_table();
911 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
912 }
913 }
914
915 uint MachPrologNode::size(PhaseRegAlloc* ra_) const
916 {
917 return MachNode::size(ra_); // too many variables; just compute it
918 // the hard way
919 }
920
921 int MachPrologNode::reloc() const
922 {
923 return 0; // a large enough number
924 }
925
926 //=============================================================================
927 #ifndef PRODUCT
928 void MachEpilogNode::format(PhaseRegAlloc* ra_, outputStream* st) const
929 {
930 Compile* C = ra_->C;
931 if (generate_vzeroupper(C)) {
932 st->print("vzeroupper");
933 st->cr(); st->print("\t");
934 }
935
936 int framesize = C->output()->frame_size_in_bytes();
937 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
938 // Remove word for return adr already pushed
939 // and RBP
940 framesize -= 2*wordSize;
941
942 if (framesize) {
943 st->print_cr("addq rsp, %d\t# Destroy frame", framesize);
944 st->print("\t");
945 }
946
947 st->print_cr("popq rbp");
948 if (do_polling() && C->is_method_compilation()) {
949 st->print("\t");
950 st->print_cr("cmpq rsp, poll_offset[r15_thread] \n\t"
951 "ja #safepoint_stub\t"
952 "# Safepoint: poll for GC");
953 }
954 }
955 #endif
956
957 void MachEpilogNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
958 {
959 Compile* C = ra_->C;
960 MacroAssembler _masm(&cbuf);
961
962 if (generate_vzeroupper(C)) {
963 // Clear upper bits of YMM registers when current compiled code uses
964 // wide vectors to avoid AVX <-> SSE transition penalty during call.
965 __ vzeroupper();
966 }
967
968 int framesize = C->output()->frame_size_in_bytes();
969 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
970 // Remove word for return adr already pushed
971 // and RBP
972 framesize -= 2*wordSize;
973
974 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here
975
976 if (framesize) {
977 emit_opcode(cbuf, Assembler::REX_W);
978 if (framesize < 0x80) {
979 emit_opcode(cbuf, 0x83); // addq rsp, #framesize
980 emit_rm(cbuf, 0x3, 0x00, RSP_enc);
981 emit_d8(cbuf, framesize);
982 } else {
983 emit_opcode(cbuf, 0x81); // addq rsp, #framesize
984 emit_rm(cbuf, 0x3, 0x00, RSP_enc);
985 emit_d32(cbuf, framesize);
986 }
987 }
988
989 // popq rbp
990 emit_opcode(cbuf, 0x58 | RBP_enc);
991
992 if (StackReservedPages > 0 && C->has_reserved_stack_access()) {
993 __ reserved_stack_check();
994 }
995
996 if (do_polling() && C->is_method_compilation()) {
997 MacroAssembler _masm(&cbuf);
998 Label dummy_label;
999 Label* code_stub = &dummy_label;
1000 if (!C->output()->in_scratch_emit_size()) {
1001 code_stub = &C->output()->safepoint_poll_table()->add_safepoint(__ offset());
1002 }
1003 __ relocate(relocInfo::poll_return_type);
1004 __ safepoint_poll(*code_stub, r15_thread, true /* at_return */, true /* in_nmethod */);
1005 }
1006 }
1007
1008 uint MachEpilogNode::size(PhaseRegAlloc* ra_) const
1009 {
1010 return MachNode::size(ra_); // too many variables; just compute it
1011 // the hard way
1012 }
1013
1014 int MachEpilogNode::reloc() const
1015 {
1016 return 2; // a large enough number
1017 }
1018
1019 const Pipeline* MachEpilogNode::pipeline() const
1020 {
1021 return MachNode::pipeline_class();
1022 }
1023
1024 //=============================================================================
1025
1026 enum RC {
1027 rc_bad,
1028 rc_int,
1029 rc_kreg,
1030 rc_float,
1031 rc_stack
1032 };
1033
1034 static enum RC rc_class(OptoReg::Name reg)
1035 {
1036 if( !OptoReg::is_valid(reg) ) return rc_bad;
1037
1038 if (OptoReg::is_stack(reg)) return rc_stack;
1039
1040 VMReg r = OptoReg::as_VMReg(reg);
1041
1042 if (r->is_Register()) return rc_int;
1043
1044 if (r->is_KRegister()) return rc_kreg;
1045
1046 assert(r->is_XMMRegister(), "must be");
1047 return rc_float;
1048 }
1049
1050 // Next two methods are shared by 32- and 64-bit VM. They are defined in x86.ad.
1051 static void vec_mov_helper(CodeBuffer *cbuf, int src_lo, int dst_lo,
1052 int src_hi, int dst_hi, uint ireg, outputStream* st);
1053
1054 void vec_spill_helper(CodeBuffer *cbuf, bool is_load,
1055 int stack_offset, int reg, uint ireg, outputStream* st);
1056
1057 static void vec_stack_to_stack_helper(CodeBuffer *cbuf, int src_offset,
1058 int dst_offset, uint ireg, outputStream* st) {
1059 if (cbuf) {
1060 MacroAssembler _masm(cbuf);
1061 switch (ireg) {
1062 case Op_VecS:
1063 __ movq(Address(rsp, -8), rax);
1064 __ movl(rax, Address(rsp, src_offset));
1065 __ movl(Address(rsp, dst_offset), rax);
1066 __ movq(rax, Address(rsp, -8));
1067 break;
1068 case Op_VecD:
1069 __ pushq(Address(rsp, src_offset));
1070 __ popq (Address(rsp, dst_offset));
1071 break;
1072 case Op_VecX:
1073 __ pushq(Address(rsp, src_offset));
1074 __ popq (Address(rsp, dst_offset));
1075 __ pushq(Address(rsp, src_offset+8));
1076 __ popq (Address(rsp, dst_offset+8));
1077 break;
1078 case Op_VecY:
1079 __ vmovdqu(Address(rsp, -32), xmm0);
1080 __ vmovdqu(xmm0, Address(rsp, src_offset));
1081 __ vmovdqu(Address(rsp, dst_offset), xmm0);
1082 __ vmovdqu(xmm0, Address(rsp, -32));
1083 break;
1084 case Op_VecZ:
1085 __ evmovdquq(Address(rsp, -64), xmm0, 2);
1086 __ evmovdquq(xmm0, Address(rsp, src_offset), 2);
1087 __ evmovdquq(Address(rsp, dst_offset), xmm0, 2);
1088 __ evmovdquq(xmm0, Address(rsp, -64), 2);
1089 break;
1090 default:
1091 ShouldNotReachHere();
1092 }
1093 #ifndef PRODUCT
1094 } else {
1095 switch (ireg) {
1096 case Op_VecS:
1097 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t"
1098 "movl rax, [rsp + #%d]\n\t"
1099 "movl [rsp + #%d], rax\n\t"
1100 "movq rax, [rsp - #8]",
1101 src_offset, dst_offset);
1102 break;
1103 case Op_VecD:
1104 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
1105 "popq [rsp + #%d]",
1106 src_offset, dst_offset);
1107 break;
1108 case Op_VecX:
1109 st->print("pushq [rsp + #%d]\t# 128-bit mem-mem spill\n\t"
1110 "popq [rsp + #%d]\n\t"
1111 "pushq [rsp + #%d]\n\t"
1112 "popq [rsp + #%d]",
1113 src_offset, dst_offset, src_offset+8, dst_offset+8);
1114 break;
1115 case Op_VecY:
1116 st->print("vmovdqu [rsp - #32], xmm0\t# 256-bit mem-mem spill\n\t"
1117 "vmovdqu xmm0, [rsp + #%d]\n\t"
1118 "vmovdqu [rsp + #%d], xmm0\n\t"
1119 "vmovdqu xmm0, [rsp - #32]",
1120 src_offset, dst_offset);
1121 break;
1122 case Op_VecZ:
1123 st->print("vmovdqu [rsp - #64], xmm0\t# 512-bit mem-mem spill\n\t"
1124 "vmovdqu xmm0, [rsp + #%d]\n\t"
1125 "vmovdqu [rsp + #%d], xmm0\n\t"
1126 "vmovdqu xmm0, [rsp - #64]",
1127 src_offset, dst_offset);
1128 break;
1129 default:
1130 ShouldNotReachHere();
1131 }
1132 #endif
1133 }
1134 }
1135
1136 uint MachSpillCopyNode::implementation(CodeBuffer* cbuf,
1137 PhaseRegAlloc* ra_,
1138 bool do_size,
1139 outputStream* st) const {
1140 assert(cbuf != NULL || st != NULL, "sanity");
1141 // Get registers to move
1142 OptoReg::Name src_second = ra_->get_reg_second(in(1));
1143 OptoReg::Name src_first = ra_->get_reg_first(in(1));
1144 OptoReg::Name dst_second = ra_->get_reg_second(this);
1145 OptoReg::Name dst_first = ra_->get_reg_first(this);
1146
1147 enum RC src_second_rc = rc_class(src_second);
1148 enum RC src_first_rc = rc_class(src_first);
1149 enum RC dst_second_rc = rc_class(dst_second);
1150 enum RC dst_first_rc = rc_class(dst_first);
1151
1152 assert(OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first),
1153 "must move at least 1 register" );
1154
1155 if (src_first == dst_first && src_second == dst_second) {
1156 // Self copy, no move
1157 return 0;
1158 }
1159 if (bottom_type()->isa_vect() != NULL && bottom_type()->isa_vectmask() == NULL) {
1160 uint ireg = ideal_reg();
1161 assert((src_first_rc != rc_int && dst_first_rc != rc_int), "sanity");
1162 assert((ireg == Op_VecS || ireg == Op_VecD || ireg == Op_VecX || ireg == Op_VecY || ireg == Op_VecZ ), "sanity");
1163 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1164 // mem -> mem
1165 int src_offset = ra_->reg2offset(src_first);
1166 int dst_offset = ra_->reg2offset(dst_first);
1167 vec_stack_to_stack_helper(cbuf, src_offset, dst_offset, ireg, st);
1168 } else if (src_first_rc == rc_float && dst_first_rc == rc_float ) {
1169 vec_mov_helper(cbuf, src_first, dst_first, src_second, dst_second, ireg, st);
1170 } else if (src_first_rc == rc_float && dst_first_rc == rc_stack ) {
1171 int stack_offset = ra_->reg2offset(dst_first);
1172 vec_spill_helper(cbuf, false, stack_offset, src_first, ireg, st);
1173 } else if (src_first_rc == rc_stack && dst_first_rc == rc_float ) {
1174 int stack_offset = ra_->reg2offset(src_first);
1175 vec_spill_helper(cbuf, true, stack_offset, dst_first, ireg, st);
1176 } else {
1177 ShouldNotReachHere();
1178 }
1179 return 0;
1180 }
1181 if (src_first_rc == rc_stack) {
1182 // mem ->
1183 if (dst_first_rc == rc_stack) {
1184 // mem -> mem
1185 assert(src_second != dst_first, "overlap");
1186 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1187 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1188 // 64-bit
1189 int src_offset = ra_->reg2offset(src_first);
1190 int dst_offset = ra_->reg2offset(dst_first);
1191 if (cbuf) {
1192 MacroAssembler _masm(cbuf);
1193 __ pushq(Address(rsp, src_offset));
1194 __ popq (Address(rsp, dst_offset));
1195 #ifndef PRODUCT
1196 } else {
1197 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
1198 "popq [rsp + #%d]",
1199 src_offset, dst_offset);
1200 #endif
1201 }
1202 } else {
1203 // 32-bit
1204 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1205 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1206 // No pushl/popl, so:
1207 int src_offset = ra_->reg2offset(src_first);
1208 int dst_offset = ra_->reg2offset(dst_first);
1209 if (cbuf) {
1210 MacroAssembler _masm(cbuf);
1211 __ movq(Address(rsp, -8), rax);
1212 __ movl(rax, Address(rsp, src_offset));
1213 __ movl(Address(rsp, dst_offset), rax);
1214 __ movq(rax, Address(rsp, -8));
1215 #ifndef PRODUCT
1216 } else {
1217 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t"
1218 "movl rax, [rsp + #%d]\n\t"
1219 "movl [rsp + #%d], rax\n\t"
1220 "movq rax, [rsp - #8]",
1221 src_offset, dst_offset);
1222 #endif
1223 }
1224 }
1225 return 0;
1226 } else if (dst_first_rc == rc_int) {
1227 // mem -> gpr
1228 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1229 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1230 // 64-bit
1231 int offset = ra_->reg2offset(src_first);
1232 if (cbuf) {
1233 MacroAssembler _masm(cbuf);
1234 __ movq(as_Register(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1235 #ifndef PRODUCT
1236 } else {
1237 st->print("movq %s, [rsp + #%d]\t# spill",
1238 Matcher::regName[dst_first],
1239 offset);
1240 #endif
1241 }
1242 } else {
1243 // 32-bit
1244 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1245 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1246 int offset = ra_->reg2offset(src_first);
1247 if (cbuf) {
1248 MacroAssembler _masm(cbuf);
1249 __ movl(as_Register(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1250 #ifndef PRODUCT
1251 } else {
1252 st->print("movl %s, [rsp + #%d]\t# spill",
1253 Matcher::regName[dst_first],
1254 offset);
1255 #endif
1256 }
1257 }
1258 return 0;
1259 } else if (dst_first_rc == rc_float) {
1260 // mem-> xmm
1261 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1262 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1263 // 64-bit
1264 int offset = ra_->reg2offset(src_first);
1265 if (cbuf) {
1266 MacroAssembler _masm(cbuf);
1267 __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1268 #ifndef PRODUCT
1269 } else {
1270 st->print("%s %s, [rsp + #%d]\t# spill",
1271 UseXmmLoadAndClearUpper ? "movsd " : "movlpd",
1272 Matcher::regName[dst_first],
1273 offset);
1274 #endif
1275 }
1276 } else {
1277 // 32-bit
1278 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1279 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1280 int offset = ra_->reg2offset(src_first);
1281 if (cbuf) {
1282 MacroAssembler _masm(cbuf);
1283 __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1284 #ifndef PRODUCT
1285 } else {
1286 st->print("movss %s, [rsp + #%d]\t# spill",
1287 Matcher::regName[dst_first],
1288 offset);
1289 #endif
1290 }
1291 }
1292 return 0;
1293 } else if (dst_first_rc == rc_kreg) {
1294 // mem -> kreg
1295 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1296 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1297 // 64-bit
1298 int offset = ra_->reg2offset(src_first);
1299 if (cbuf) {
1300 MacroAssembler _masm(cbuf);
1301 __ kmov(as_KRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1302 #ifndef PRODUCT
1303 } else {
1304 st->print("kmovq %s, [rsp + #%d]\t# spill",
1305 Matcher::regName[dst_first],
1306 offset);
1307 #endif
1308 }
1309 }
1310 return 0;
1311 }
1312 } else if (src_first_rc == rc_int) {
1313 // gpr ->
1314 if (dst_first_rc == rc_stack) {
1315 // gpr -> mem
1316 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1317 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1318 // 64-bit
1319 int offset = ra_->reg2offset(dst_first);
1320 if (cbuf) {
1321 MacroAssembler _masm(cbuf);
1322 __ movq(Address(rsp, offset), as_Register(Matcher::_regEncode[src_first]));
1323 #ifndef PRODUCT
1324 } else {
1325 st->print("movq [rsp + #%d], %s\t# spill",
1326 offset,
1327 Matcher::regName[src_first]);
1328 #endif
1329 }
1330 } else {
1331 // 32-bit
1332 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1333 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1334 int offset = ra_->reg2offset(dst_first);
1335 if (cbuf) {
1336 MacroAssembler _masm(cbuf);
1337 __ movl(Address(rsp, offset), as_Register(Matcher::_regEncode[src_first]));
1338 #ifndef PRODUCT
1339 } else {
1340 st->print("movl [rsp + #%d], %s\t# spill",
1341 offset,
1342 Matcher::regName[src_first]);
1343 #endif
1344 }
1345 }
1346 return 0;
1347 } else if (dst_first_rc == rc_int) {
1348 // gpr -> gpr
1349 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1350 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1351 // 64-bit
1352 if (cbuf) {
1353 MacroAssembler _masm(cbuf);
1354 __ movq(as_Register(Matcher::_regEncode[dst_first]),
1355 as_Register(Matcher::_regEncode[src_first]));
1356 #ifndef PRODUCT
1357 } else {
1358 st->print("movq %s, %s\t# spill",
1359 Matcher::regName[dst_first],
1360 Matcher::regName[src_first]);
1361 #endif
1362 }
1363 return 0;
1364 } else {
1365 // 32-bit
1366 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1367 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1368 if (cbuf) {
1369 MacroAssembler _masm(cbuf);
1370 __ movl(as_Register(Matcher::_regEncode[dst_first]),
1371 as_Register(Matcher::_regEncode[src_first]));
1372 #ifndef PRODUCT
1373 } else {
1374 st->print("movl %s, %s\t# spill",
1375 Matcher::regName[dst_first],
1376 Matcher::regName[src_first]);
1377 #endif
1378 }
1379 return 0;
1380 }
1381 } else if (dst_first_rc == rc_float) {
1382 // gpr -> xmm
1383 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1384 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1385 // 64-bit
1386 if (cbuf) {
1387 MacroAssembler _masm(cbuf);
1388 __ movdq( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
1389 #ifndef PRODUCT
1390 } else {
1391 st->print("movdq %s, %s\t# spill",
1392 Matcher::regName[dst_first],
1393 Matcher::regName[src_first]);
1394 #endif
1395 }
1396 } else {
1397 // 32-bit
1398 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1399 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1400 if (cbuf) {
1401 MacroAssembler _masm(cbuf);
1402 __ movdl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
1403 #ifndef PRODUCT
1404 } else {
1405 st->print("movdl %s, %s\t# spill",
1406 Matcher::regName[dst_first],
1407 Matcher::regName[src_first]);
1408 #endif
1409 }
1410 }
1411 return 0;
1412 } else if (dst_first_rc == rc_kreg) {
1413 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1414 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1415 // 64-bit
1416 if (cbuf) {
1417 MacroAssembler _masm(cbuf);
1418 __ kmov(as_KRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
1419 #ifndef PRODUCT
1420 } else {
1421 st->print("kmovq %s, %s\t# spill",
1422 Matcher::regName[dst_first],
1423 Matcher::regName[src_first]);
1424 #endif
1425 }
1426 }
1427 Unimplemented();
1428 return 0;
1429 }
1430 } else if (src_first_rc == rc_float) {
1431 // xmm ->
1432 if (dst_first_rc == rc_stack) {
1433 // xmm -> mem
1434 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1435 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1436 // 64-bit
1437 int offset = ra_->reg2offset(dst_first);
1438 if (cbuf) {
1439 MacroAssembler _masm(cbuf);
1440 __ movdbl( Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first]));
1441 #ifndef PRODUCT
1442 } else {
1443 st->print("movsd [rsp + #%d], %s\t# spill",
1444 offset,
1445 Matcher::regName[src_first]);
1446 #endif
1447 }
1448 } else {
1449 // 32-bit
1450 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1451 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1452 int offset = ra_->reg2offset(dst_first);
1453 if (cbuf) {
1454 MacroAssembler _masm(cbuf);
1455 __ movflt(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first]));
1456 #ifndef PRODUCT
1457 } else {
1458 st->print("movss [rsp + #%d], %s\t# spill",
1459 offset,
1460 Matcher::regName[src_first]);
1461 #endif
1462 }
1463 }
1464 return 0;
1465 } else if (dst_first_rc == rc_int) {
1466 // xmm -> gpr
1467 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1468 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1469 // 64-bit
1470 if (cbuf) {
1471 MacroAssembler _masm(cbuf);
1472 __ movdq( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1473 #ifndef PRODUCT
1474 } else {
1475 st->print("movdq %s, %s\t# spill",
1476 Matcher::regName[dst_first],
1477 Matcher::regName[src_first]);
1478 #endif
1479 }
1480 } else {
1481 // 32-bit
1482 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1483 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1484 if (cbuf) {
1485 MacroAssembler _masm(cbuf);
1486 __ movdl( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1487 #ifndef PRODUCT
1488 } else {
1489 st->print("movdl %s, %s\t# spill",
1490 Matcher::regName[dst_first],
1491 Matcher::regName[src_first]);
1492 #endif
1493 }
1494 }
1495 return 0;
1496 } else if (dst_first_rc == rc_float) {
1497 // xmm -> xmm
1498 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1499 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1500 // 64-bit
1501 if (cbuf) {
1502 MacroAssembler _masm(cbuf);
1503 __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1504 #ifndef PRODUCT
1505 } else {
1506 st->print("%s %s, %s\t# spill",
1507 UseXmmRegToRegMoveAll ? "movapd" : "movsd ",
1508 Matcher::regName[dst_first],
1509 Matcher::regName[src_first]);
1510 #endif
1511 }
1512 } else {
1513 // 32-bit
1514 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1515 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1516 if (cbuf) {
1517 MacroAssembler _masm(cbuf);
1518 __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1519 #ifndef PRODUCT
1520 } else {
1521 st->print("%s %s, %s\t# spill",
1522 UseXmmRegToRegMoveAll ? "movaps" : "movss ",
1523 Matcher::regName[dst_first],
1524 Matcher::regName[src_first]);
1525 #endif
1526 }
1527 }
1528 return 0;
1529 } else if (dst_first_rc == rc_kreg) {
1530 assert(false, "Illegal spilling");
1531 return 0;
1532 }
1533 } else if (src_first_rc == rc_kreg) {
1534 if (dst_first_rc == rc_stack) {
1535 // mem -> kreg
1536 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1537 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1538 // 64-bit
1539 int offset = ra_->reg2offset(dst_first);
1540 if (cbuf) {
1541 MacroAssembler _masm(cbuf);
1542 __ kmov(Address(rsp, offset), as_KRegister(Matcher::_regEncode[src_first]));
1543 #ifndef PRODUCT
1544 } else {
1545 st->print("kmovq [rsp + #%d] , %s\t# spill",
1546 offset,
1547 Matcher::regName[src_first]);
1548 #endif
1549 }
1550 }
1551 return 0;
1552 } else if (dst_first_rc == rc_int) {
1553 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1554 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1555 // 64-bit
1556 if (cbuf) {
1557 MacroAssembler _masm(cbuf);
1558 __ kmov(as_Register(Matcher::_regEncode[dst_first]), as_KRegister(Matcher::_regEncode[src_first]));
1559 #ifndef PRODUCT
1560 } else {
1561 st->print("kmovq %s, %s\t# spill",
1562 Matcher::regName[dst_first],
1563 Matcher::regName[src_first]);
1564 #endif
1565 }
1566 }
1567 Unimplemented();
1568 return 0;
1569 } else if (dst_first_rc == rc_kreg) {
1570 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1571 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1572 // 64-bit
1573 if (cbuf) {
1574 MacroAssembler _masm(cbuf);
1575 __ kmov(as_KRegister(Matcher::_regEncode[dst_first]), as_KRegister(Matcher::_regEncode[src_first]));
1576 #ifndef PRODUCT
1577 } else {
1578 st->print("kmovq %s, %s\t# spill",
1579 Matcher::regName[dst_first],
1580 Matcher::regName[src_first]);
1581 #endif
1582 }
1583 }
1584 return 0;
1585 } else if (dst_first_rc == rc_float) {
1586 assert(false, "Illegal spill");
1587 return 0;
1588 }
1589 }
1590
1591 assert(0," foo ");
1592 Unimplemented();
1593 return 0;
1594 }
1595
1596 #ifndef PRODUCT
1597 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const {
1598 implementation(NULL, ra_, false, st);
1599 }
1600 #endif
1601
1602 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1603 implementation(&cbuf, ra_, false, NULL);
1604 }
1605
1606 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1607 return MachNode::size(ra_);
1608 }
1609
1610 //=============================================================================
1611 #ifndef PRODUCT
1612 void BoxLockNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1613 {
1614 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1615 int reg = ra_->get_reg_first(this);
1616 st->print("leaq %s, [rsp + #%d]\t# box lock",
1617 Matcher::regName[reg], offset);
1618 }
1619 #endif
1620
1621 void BoxLockNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
1622 {
1623 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1624 int reg = ra_->get_encode(this);
1625 if (offset >= 0x80) {
1626 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
1627 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1628 emit_rm(cbuf, 0x2, reg & 7, 0x04);
1629 emit_rm(cbuf, 0x0, 0x04, RSP_enc);
1630 emit_d32(cbuf, offset);
1631 } else {
1632 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
1633 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1634 emit_rm(cbuf, 0x1, reg & 7, 0x04);
1635 emit_rm(cbuf, 0x0, 0x04, RSP_enc);
1636 emit_d8(cbuf, offset);
1637 }
1638 }
1639
1640 uint BoxLockNode::size(PhaseRegAlloc *ra_) const
1641 {
1642 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1643 return (offset < 0x80) ? 5 : 8; // REX
1644 }
1645
1646 //=============================================================================
1647 #ifndef PRODUCT
1648 void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1649 {
1650 if (UseCompressedClassPointers) {
1651 st->print_cr("movl rscratch1, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass");
1652 st->print_cr("\tdecode_klass_not_null rscratch1, rscratch1");
1653 st->print_cr("\tcmpq rax, rscratch1\t # Inline cache check");
1654 } else {
1655 st->print_cr("\tcmpq rax, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t"
1656 "# Inline cache check");
1657 }
1658 st->print_cr("\tjne SharedRuntime::_ic_miss_stub");
1659 st->print_cr("\tnop\t# nops to align entry point");
1660 }
1661 #endif
1662
1663 void MachUEPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
1664 {
1665 MacroAssembler masm(&cbuf);
1666 uint insts_size = cbuf.insts_size();
1667 if (UseCompressedClassPointers) {
1668 masm.load_klass(rscratch1, j_rarg0, rscratch2);
1669 masm.cmpptr(rax, rscratch1);
1670 } else {
1671 masm.cmpptr(rax, Address(j_rarg0, oopDesc::klass_offset_in_bytes()));
1672 }
1673
1674 masm.jump_cc(Assembler::notEqual, RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1675
1676 /* WARNING these NOPs are critical so that verified entry point is properly
1677 4 bytes aligned for patching by NativeJump::patch_verified_entry() */
1678 int nops_cnt = 4 - ((cbuf.insts_size() - insts_size) & 0x3);
1679 if (OptoBreakpoint) {
1680 // Leave space for int3
1681 nops_cnt -= 1;
1682 }
1683 nops_cnt &= 0x3; // Do not add nops if code is aligned.
1684 if (nops_cnt > 0)
1685 masm.nop(nops_cnt);
1686 }
1687
1688 uint MachUEPNode::size(PhaseRegAlloc* ra_) const
1689 {
1690 return MachNode::size(ra_); // too many variables; just compute it
1691 // the hard way
1692 }
1693
1694
1695 //=============================================================================
1696
1697 const bool Matcher::supports_vector_calling_convention(void) {
1698 if (EnableVectorSupport && UseVectorStubs) {
1699 return true;
1700 }
1701 return false;
1702 }
1703
1704 OptoRegPair Matcher::vector_return_value(uint ideal_reg) {
1705 assert(EnableVectorSupport && UseVectorStubs, "sanity");
1706 int lo = XMM0_num;
1707 int hi = XMM0b_num;
1708 if (ideal_reg == Op_VecX) hi = XMM0d_num;
1709 else if (ideal_reg == Op_VecY) hi = XMM0h_num;
1710 else if (ideal_reg == Op_VecZ) hi = XMM0p_num;
1711 return OptoRegPair(hi, lo);
1712 }
1713
1714 // Is this branch offset short enough that a short branch can be used?
1715 //
1716 // NOTE: If the platform does not provide any short branch variants, then
1717 // this method should return false for offset 0.
1718 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1719 // The passed offset is relative to address of the branch.
1720 // On 86 a branch displacement is calculated relative to address
1721 // of a next instruction.
1722 offset -= br_size;
1723
1724 // the short version of jmpConUCF2 contains multiple branches,
1725 // making the reach slightly less
1726 if (rule == jmpConUCF2_rule)
1727 return (-126 <= offset && offset <= 125);
1728 return (-128 <= offset && offset <= 127);
1729 }
1730
1731 // Return whether or not this register is ever used as an argument.
1732 // This function is used on startup to build the trampoline stubs in
1733 // generateOptoStub. Registers not mentioned will be killed by the VM
1734 // call in the trampoline, and arguments in those registers not be
1735 // available to the callee.
1736 bool Matcher::can_be_java_arg(int reg)
1737 {
1738 return
1739 reg == RDI_num || reg == RDI_H_num ||
1740 reg == RSI_num || reg == RSI_H_num ||
1741 reg == RDX_num || reg == RDX_H_num ||
1742 reg == RCX_num || reg == RCX_H_num ||
1743 reg == R8_num || reg == R8_H_num ||
1744 reg == R9_num || reg == R9_H_num ||
1745 reg == R12_num || reg == R12_H_num ||
1746 reg == XMM0_num || reg == XMM0b_num ||
1747 reg == XMM1_num || reg == XMM1b_num ||
1748 reg == XMM2_num || reg == XMM2b_num ||
1749 reg == XMM3_num || reg == XMM3b_num ||
1750 reg == XMM4_num || reg == XMM4b_num ||
1751 reg == XMM5_num || reg == XMM5b_num ||
1752 reg == XMM6_num || reg == XMM6b_num ||
1753 reg == XMM7_num || reg == XMM7b_num;
1754 }
1755
1756 bool Matcher::is_spillable_arg(int reg)
1757 {
1758 return can_be_java_arg(reg);
1759 }
1760
1761 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
1762 // In 64 bit mode a code which use multiply when
1763 // devisor is constant is faster than hardware
1764 // DIV instruction (it uses MulHiL).
1765 return false;
1766 }
1767
1768 // Register for DIVI projection of divmodI
1769 RegMask Matcher::divI_proj_mask() {
1770 return INT_RAX_REG_mask();
1771 }
1772
1773 // Register for MODI projection of divmodI
1774 RegMask Matcher::modI_proj_mask() {
1775 return INT_RDX_REG_mask();
1776 }
1777
1778 // Register for DIVL projection of divmodL
1779 RegMask Matcher::divL_proj_mask() {
1780 return LONG_RAX_REG_mask();
1781 }
1782
1783 // Register for MODL projection of divmodL
1784 RegMask Matcher::modL_proj_mask() {
1785 return LONG_RDX_REG_mask();
1786 }
1787
1788 // Register for saving SP into on method handle invokes. Not used on x86_64.
1789 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1790 return NO_REG_mask();
1791 }
1792
1793 %}
1794
1795 //----------ENCODING BLOCK-----------------------------------------------------
1796 // This block specifies the encoding classes used by the compiler to
1797 // output byte streams. Encoding classes are parameterized macros
1798 // used by Machine Instruction Nodes in order to generate the bit
1799 // encoding of the instruction. Operands specify their base encoding
1800 // interface with the interface keyword. There are currently
1801 // supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, &
1802 // COND_INTER. REG_INTER causes an operand to generate a function
1803 // which returns its register number when queried. CONST_INTER causes
1804 // an operand to generate a function which returns the value of the
1805 // constant when queried. MEMORY_INTER causes an operand to generate
1806 // four functions which return the Base Register, the Index Register,
1807 // the Scale Value, and the Offset Value of the operand when queried.
1808 // COND_INTER causes an operand to generate six functions which return
1809 // the encoding code (ie - encoding bits for the instruction)
1810 // associated with each basic boolean condition for a conditional
1811 // instruction.
1812 //
1813 // Instructions specify two basic values for encoding. Again, a
1814 // function is available to check if the constant displacement is an
1815 // oop. They use the ins_encode keyword to specify their encoding
1816 // classes (which must be a sequence of enc_class names, and their
1817 // parameters, specified in the encoding block), and they use the
1818 // opcode keyword to specify, in order, their primary, secondary, and
1819 // tertiary opcode. Only the opcode sections which a particular
1820 // instruction needs for encoding need to be specified.
1821 encode %{
1822 // Build emit functions for each basic byte or larger field in the
1823 // intel encoding scheme (opcode, rm, sib, immediate), and call them
1824 // from C++ code in the enc_class source block. Emit functions will
1825 // live in the main source block for now. In future, we can
1826 // generalize this by adding a syntax that specifies the sizes of
1827 // fields in an order, so that the adlc can build the emit functions
1828 // automagically
1829
1830 // Emit primary opcode
1831 enc_class OpcP
1832 %{
1833 emit_opcode(cbuf, $primary);
1834 %}
1835
1836 // Emit secondary opcode
1837 enc_class OpcS
1838 %{
1839 emit_opcode(cbuf, $secondary);
1840 %}
1841
1842 // Emit tertiary opcode
1843 enc_class OpcT
1844 %{
1845 emit_opcode(cbuf, $tertiary);
1846 %}
1847
1848 // Emit opcode directly
1849 enc_class Opcode(immI d8)
1850 %{
1851 emit_opcode(cbuf, $d8$$constant);
1852 %}
1853
1854 // Emit size prefix
1855 enc_class SizePrefix
1856 %{
1857 emit_opcode(cbuf, 0x66);
1858 %}
1859
1860 enc_class reg(rRegI reg)
1861 %{
1862 emit_rm(cbuf, 0x3, 0, $reg$$reg & 7);
1863 %}
1864
1865 enc_class reg_reg(rRegI dst, rRegI src)
1866 %{
1867 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
1868 %}
1869
1870 enc_class opc_reg_reg(immI opcode, rRegI dst, rRegI src)
1871 %{
1872 emit_opcode(cbuf, $opcode$$constant);
1873 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
1874 %}
1875
1876 enc_class cdql_enc(no_rax_rdx_RegI div)
1877 %{
1878 // Full implementation of Java idiv and irem; checks for
1879 // special case as described in JVM spec., p.243 & p.271.
1880 //
1881 // normal case special case
1882 //
1883 // input : rax: dividend min_int
1884 // reg: divisor -1
1885 //
1886 // output: rax: quotient (= rax idiv reg) min_int
1887 // rdx: remainder (= rax irem reg) 0
1888 //
1889 // Code sequnce:
1890 //
1891 // 0: 3d 00 00 00 80 cmp $0x80000000,%eax
1892 // 5: 75 07/08 jne e <normal>
1893 // 7: 33 d2 xor %edx,%edx
1894 // [div >= 8 -> offset + 1]
1895 // [REX_B]
1896 // 9: 83 f9 ff cmp $0xffffffffffffffff,$div
1897 // c: 74 03/04 je 11 <done>
1898 // 000000000000000e <normal>:
1899 // e: 99 cltd
1900 // [div >= 8 -> offset + 1]
1901 // [REX_B]
1902 // f: f7 f9 idiv $div
1903 // 0000000000000011 <done>:
1904 MacroAssembler _masm(&cbuf);
1905 Label normal;
1906 Label done;
1907
1908 // cmp $0x80000000,%eax
1909 __ cmp(as_Register(RAX_enc), 0x80000000);
1910
1911 // jne e <normal>
1912 __ jccb(Assembler::notEqual, normal);
1913
1914 // xor %edx,%edx
1915 __ xorl(as_Register(RDX_enc), as_Register(RDX_enc));
1916
1917 // cmp $0xffffffffffffffff,%ecx
1918 __ cmpl($div$$Register, -1);
1919
1920 // je 11 <done>
1921 __ jccb(Assembler::equal, done);
1922
1923 // <normal>
1924 // cltd
1925 __ bind(normal);
1926 __ cdql();
1927
1928 // idivl
1929 // <done>
1930 __ idivl($div$$Register);
1931 __ bind(done);
1932 %}
1933
1934 enc_class cdqq_enc(no_rax_rdx_RegL div)
1935 %{
1936 // Full implementation of Java ldiv and lrem; checks for
1937 // special case as described in JVM spec., p.243 & p.271.
1938 //
1939 // normal case special case
1940 //
1941 // input : rax: dividend min_long
1942 // reg: divisor -1
1943 //
1944 // output: rax: quotient (= rax idiv reg) min_long
1945 // rdx: remainder (= rax irem reg) 0
1946 //
1947 // Code sequnce:
1948 //
1949 // 0: 48 ba 00 00 00 00 00 mov $0x8000000000000000,%rdx
1950 // 7: 00 00 80
1951 // a: 48 39 d0 cmp %rdx,%rax
1952 // d: 75 08 jne 17 <normal>
1953 // f: 33 d2 xor %edx,%edx
1954 // 11: 48 83 f9 ff cmp $0xffffffffffffffff,$div
1955 // 15: 74 05 je 1c <done>
1956 // 0000000000000017 <normal>:
1957 // 17: 48 99 cqto
1958 // 19: 48 f7 f9 idiv $div
1959 // 000000000000001c <done>:
1960 MacroAssembler _masm(&cbuf);
1961 Label normal;
1962 Label done;
1963
1964 // mov $0x8000000000000000,%rdx
1965 __ mov64(as_Register(RDX_enc), 0x8000000000000000);
1966
1967 // cmp %rdx,%rax
1968 __ cmpq(as_Register(RAX_enc), as_Register(RDX_enc));
1969
1970 // jne 17 <normal>
1971 __ jccb(Assembler::notEqual, normal);
1972
1973 // xor %edx,%edx
1974 __ xorl(as_Register(RDX_enc), as_Register(RDX_enc));
1975
1976 // cmp $0xffffffffffffffff,$div
1977 __ cmpq($div$$Register, -1);
1978
1979 // je 1e <done>
1980 __ jccb(Assembler::equal, done);
1981
1982 // <normal>
1983 // cqto
1984 __ bind(normal);
1985 __ cdqq();
1986
1987 // idivq (note: must be emitted by the user of this rule)
1988 // <done>
1989 __ idivq($div$$Register);
1990 __ bind(done);
1991 %}
1992
1993 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension
1994 enc_class OpcSE(immI imm)
1995 %{
1996 // Emit primary opcode and set sign-extend bit
1997 // Check for 8-bit immediate, and set sign extend bit in opcode
1998 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
1999 emit_opcode(cbuf, $primary | 0x02);
2000 } else {
2001 // 32-bit immediate
2002 emit_opcode(cbuf, $primary);
2003 }
2004 %}
2005
2006 enc_class OpcSErm(rRegI dst, immI imm)
2007 %{
2008 // OpcSEr/m
2009 int dstenc = $dst$$reg;
2010 if (dstenc >= 8) {
2011 emit_opcode(cbuf, Assembler::REX_B);
2012 dstenc -= 8;
2013 }
2014 // Emit primary opcode and set sign-extend bit
2015 // Check for 8-bit immediate, and set sign extend bit in opcode
2016 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
2017 emit_opcode(cbuf, $primary | 0x02);
2018 } else {
2019 // 32-bit immediate
2020 emit_opcode(cbuf, $primary);
2021 }
2022 // Emit r/m byte with secondary opcode, after primary opcode.
2023 emit_rm(cbuf, 0x3, $secondary, dstenc);
2024 %}
2025
2026 enc_class OpcSErm_wide(rRegL dst, immI imm)
2027 %{
2028 // OpcSEr/m
2029 int dstenc = $dst$$reg;
2030 if (dstenc < 8) {
2031 emit_opcode(cbuf, Assembler::REX_W);
2032 } else {
2033 emit_opcode(cbuf, Assembler::REX_WB);
2034 dstenc -= 8;
2035 }
2036 // Emit primary opcode and set sign-extend bit
2037 // Check for 8-bit immediate, and set sign extend bit in opcode
2038 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
2039 emit_opcode(cbuf, $primary | 0x02);
2040 } else {
2041 // 32-bit immediate
2042 emit_opcode(cbuf, $primary);
2043 }
2044 // Emit r/m byte with secondary opcode, after primary opcode.
2045 emit_rm(cbuf, 0x3, $secondary, dstenc);
2046 %}
2047
2048 enc_class Con8or32(immI imm)
2049 %{
2050 // Check for 8-bit immediate, and set sign extend bit in opcode
2051 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
2052 $$$emit8$imm$$constant;
2053 } else {
2054 // 32-bit immediate
2055 $$$emit32$imm$$constant;
2056 }
2057 %}
2058
2059 enc_class opc2_reg(rRegI dst)
2060 %{
2061 // BSWAP
2062 emit_cc(cbuf, $secondary, $dst$$reg);
2063 %}
2064
2065 enc_class opc3_reg(rRegI dst)
2066 %{
2067 // BSWAP
2068 emit_cc(cbuf, $tertiary, $dst$$reg);
2069 %}
2070
2071 enc_class reg_opc(rRegI div)
2072 %{
2073 // INC, DEC, IDIV, IMOD, JMP indirect, ...
2074 emit_rm(cbuf, 0x3, $secondary, $div$$reg & 7);
2075 %}
2076
2077 enc_class enc_cmov(cmpOp cop)
2078 %{
2079 // CMOV
2080 $$$emit8$primary;
2081 emit_cc(cbuf, $secondary, $cop$$cmpcode);
2082 %}
2083
2084 enc_class enc_PartialSubtypeCheck()
2085 %{
2086 Register Rrdi = as_Register(RDI_enc); // result register
2087 Register Rrax = as_Register(RAX_enc); // super class
2088 Register Rrcx = as_Register(RCX_enc); // killed
2089 Register Rrsi = as_Register(RSI_enc); // sub class
2090 Label miss;
2091 const bool set_cond_codes = true;
2092
2093 MacroAssembler _masm(&cbuf);
2094 __ check_klass_subtype_slow_path(Rrsi, Rrax, Rrcx, Rrdi,
2095 NULL, &miss,
2096 /*set_cond_codes:*/ true);
2097 if ($primary) {
2098 __ xorptr(Rrdi, Rrdi);
2099 }
2100 __ bind(miss);
2101 %}
2102
2103 enc_class clear_avx %{
2104 debug_only(int off0 = cbuf.insts_size());
2105 if (generate_vzeroupper(Compile::current())) {
2106 // Clear upper bits of YMM registers to avoid AVX <-> SSE transition penalty
2107 // Clear upper bits of YMM registers when current compiled code uses
2108 // wide vectors to avoid AVX <-> SSE transition penalty during call.
2109 MacroAssembler _masm(&cbuf);
2110 __ vzeroupper();
2111 }
2112 debug_only(int off1 = cbuf.insts_size());
2113 assert(off1 - off0 == clear_avx_size(), "correct size prediction");
2114 %}
2115
2116 enc_class Java_To_Runtime(method meth) %{
2117 // No relocation needed
2118 MacroAssembler _masm(&cbuf);
2119 __ mov64(r10, (int64_t) $meth$$method);
2120 __ call(r10);
2121 %}
2122
2123 enc_class Java_To_Interpreter(method meth)
2124 %{
2125 // CALL Java_To_Interpreter
2126 // This is the instruction starting address for relocation info.
2127 cbuf.set_insts_mark();
2128 $$$emit8$primary;
2129 // CALL directly to the runtime
2130 emit_d32_reloc(cbuf,
2131 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2132 runtime_call_Relocation::spec(),
2133 RELOC_DISP32);
2134 %}
2135
2136 enc_class Java_Static_Call(method meth)
2137 %{
2138 // JAVA STATIC CALL
2139 // CALL to fixup routine. Fixup routine uses ScopeDesc info to
2140 // determine who we intended to call.
2141 cbuf.set_insts_mark();
2142 $$$emit8$primary;
2143
2144 if (!_method) {
2145 emit_d32_reloc(cbuf, (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2146 runtime_call_Relocation::spec(),
2147 RELOC_DISP32);
2148 } else {
2149 int method_index = resolved_method_index(cbuf);
2150 RelocationHolder rspec = _optimized_virtual ? opt_virtual_call_Relocation::spec(method_index)
2151 : static_call_Relocation::spec(method_index);
2152 emit_d32_reloc(cbuf, (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2153 rspec, RELOC_DISP32);
2154 // Emit stubs for static call.
2155 address mark = cbuf.insts_mark();
2156 address stub = CompiledStaticCall::emit_to_interp_stub(cbuf, mark);
2157 if (stub == NULL) {
2158 ciEnv::current()->record_failure("CodeCache is full");
2159 return;
2160 }
2161 }
2162 %}
2163
2164 enc_class Java_Dynamic_Call(method meth) %{
2165 MacroAssembler _masm(&cbuf);
2166 __ ic_call((address)$meth$$method, resolved_method_index(cbuf));
2167 %}
2168
2169 enc_class Java_Compiled_Call(method meth)
2170 %{
2171 // JAVA COMPILED CALL
2172 int disp = in_bytes(Method:: from_compiled_offset());
2173
2174 // XXX XXX offset is 128 is 1.5 NON-PRODUCT !!!
2175 // assert(-0x80 <= disp && disp < 0x80, "compiled_code_offset isn't small");
2176
2177 // callq *disp(%rax)
2178 cbuf.set_insts_mark();
2179 $$$emit8$primary;
2180 if (disp < 0x80) {
2181 emit_rm(cbuf, 0x01, $secondary, RAX_enc); // R/M byte
2182 emit_d8(cbuf, disp); // Displacement
2183 } else {
2184 emit_rm(cbuf, 0x02, $secondary, RAX_enc); // R/M byte
2185 emit_d32(cbuf, disp); // Displacement
2186 }
2187 %}
2188
2189 enc_class reg_opc_imm(rRegI dst, immI8 shift)
2190 %{
2191 // SAL, SAR, SHR
2192 int dstenc = $dst$$reg;
2193 if (dstenc >= 8) {
2194 emit_opcode(cbuf, Assembler::REX_B);
2195 dstenc -= 8;
2196 }
2197 $$$emit8$primary;
2198 emit_rm(cbuf, 0x3, $secondary, dstenc);
2199 $$$emit8$shift$$constant;
2200 %}
2201
2202 enc_class reg_opc_imm_wide(rRegL dst, immI8 shift)
2203 %{
2204 // SAL, SAR, SHR
2205 int dstenc = $dst$$reg;
2206 if (dstenc < 8) {
2207 emit_opcode(cbuf, Assembler::REX_W);
2208 } else {
2209 emit_opcode(cbuf, Assembler::REX_WB);
2210 dstenc -= 8;
2211 }
2212 $$$emit8$primary;
2213 emit_rm(cbuf, 0x3, $secondary, dstenc);
2214 $$$emit8$shift$$constant;
2215 %}
2216
2217 enc_class load_immI(rRegI dst, immI src)
2218 %{
2219 int dstenc = $dst$$reg;
2220 if (dstenc >= 8) {
2221 emit_opcode(cbuf, Assembler::REX_B);
2222 dstenc -= 8;
2223 }
2224 emit_opcode(cbuf, 0xB8 | dstenc);
2225 $$$emit32$src$$constant;
2226 %}
2227
2228 enc_class load_immL(rRegL dst, immL src)
2229 %{
2230 int dstenc = $dst$$reg;
2231 if (dstenc < 8) {
2232 emit_opcode(cbuf, Assembler::REX_W);
2233 } else {
2234 emit_opcode(cbuf, Assembler::REX_WB);
2235 dstenc -= 8;
2236 }
2237 emit_opcode(cbuf, 0xB8 | dstenc);
2238 emit_d64(cbuf, $src$$constant);
2239 %}
2240
2241 enc_class load_immUL32(rRegL dst, immUL32 src)
2242 %{
2243 // same as load_immI, but this time we care about zeroes in the high word
2244 int dstenc = $dst$$reg;
2245 if (dstenc >= 8) {
2246 emit_opcode(cbuf, Assembler::REX_B);
2247 dstenc -= 8;
2248 }
2249 emit_opcode(cbuf, 0xB8 | dstenc);
2250 $$$emit32$src$$constant;
2251 %}
2252
2253 enc_class load_immL32(rRegL dst, immL32 src)
2254 %{
2255 int dstenc = $dst$$reg;
2256 if (dstenc < 8) {
2257 emit_opcode(cbuf, Assembler::REX_W);
2258 } else {
2259 emit_opcode(cbuf, Assembler::REX_WB);
2260 dstenc -= 8;
2261 }
2262 emit_opcode(cbuf, 0xC7);
2263 emit_rm(cbuf, 0x03, 0x00, dstenc);
2264 $$$emit32$src$$constant;
2265 %}
2266
2267 enc_class load_immP31(rRegP dst, immP32 src)
2268 %{
2269 // same as load_immI, but this time we care about zeroes in the high word
2270 int dstenc = $dst$$reg;
2271 if (dstenc >= 8) {
2272 emit_opcode(cbuf, Assembler::REX_B);
2273 dstenc -= 8;
2274 }
2275 emit_opcode(cbuf, 0xB8 | dstenc);
2276 $$$emit32$src$$constant;
2277 %}
2278
2279 enc_class load_immP(rRegP dst, immP src)
2280 %{
2281 int dstenc = $dst$$reg;
2282 if (dstenc < 8) {
2283 emit_opcode(cbuf, Assembler::REX_W);
2284 } else {
2285 emit_opcode(cbuf, Assembler::REX_WB);
2286 dstenc -= 8;
2287 }
2288 emit_opcode(cbuf, 0xB8 | dstenc);
2289 // This next line should be generated from ADLC
2290 if ($src->constant_reloc() != relocInfo::none) {
2291 emit_d64_reloc(cbuf, $src$$constant, $src->constant_reloc(), RELOC_IMM64);
2292 } else {
2293 emit_d64(cbuf, $src$$constant);
2294 }
2295 %}
2296
2297 enc_class Con32(immI src)
2298 %{
2299 // Output immediate
2300 $$$emit32$src$$constant;
2301 %}
2302
2303 enc_class Con32F_as_bits(immF src)
2304 %{
2305 // Output Float immediate bits
2306 jfloat jf = $src$$constant;
2307 jint jf_as_bits = jint_cast(jf);
2308 emit_d32(cbuf, jf_as_bits);
2309 %}
2310
2311 enc_class Con16(immI src)
2312 %{
2313 // Output immediate
2314 $$$emit16$src$$constant;
2315 %}
2316
2317 // How is this different from Con32??? XXX
2318 enc_class Con_d32(immI src)
2319 %{
2320 emit_d32(cbuf,$src$$constant);
2321 %}
2322
2323 enc_class conmemref (rRegP t1) %{ // Con32(storeImmI)
2324 // Output immediate memory reference
2325 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 );
2326 emit_d32(cbuf, 0x00);
2327 %}
2328
2329 enc_class lock_prefix()
2330 %{
2331 emit_opcode(cbuf, 0xF0); // lock
2332 %}
2333
2334 enc_class REX_mem(memory mem)
2335 %{
2336 if ($mem$$base >= 8) {
2337 if ($mem$$index < 8) {
2338 emit_opcode(cbuf, Assembler::REX_B);
2339 } else {
2340 emit_opcode(cbuf, Assembler::REX_XB);
2341 }
2342 } else {
2343 if ($mem$$index >= 8) {
2344 emit_opcode(cbuf, Assembler::REX_X);
2345 }
2346 }
2347 %}
2348
2349 enc_class REX_mem_wide(memory mem)
2350 %{
2351 if ($mem$$base >= 8) {
2352 if ($mem$$index < 8) {
2353 emit_opcode(cbuf, Assembler::REX_WB);
2354 } else {
2355 emit_opcode(cbuf, Assembler::REX_WXB);
2356 }
2357 } else {
2358 if ($mem$$index < 8) {
2359 emit_opcode(cbuf, Assembler::REX_W);
2360 } else {
2361 emit_opcode(cbuf, Assembler::REX_WX);
2362 }
2363 }
2364 %}
2365
2366 // for byte regs
2367 enc_class REX_breg(rRegI reg)
2368 %{
2369 if ($reg$$reg >= 4) {
2370 emit_opcode(cbuf, $reg$$reg < 8 ? Assembler::REX : Assembler::REX_B);
2371 }
2372 %}
2373
2374 // for byte regs
2375 enc_class REX_reg_breg(rRegI dst, rRegI src)
2376 %{
2377 if ($dst$$reg < 8) {
2378 if ($src$$reg >= 4) {
2379 emit_opcode(cbuf, $src$$reg < 8 ? Assembler::REX : Assembler::REX_B);
2380 }
2381 } else {
2382 if ($src$$reg < 8) {
2383 emit_opcode(cbuf, Assembler::REX_R);
2384 } else {
2385 emit_opcode(cbuf, Assembler::REX_RB);
2386 }
2387 }
2388 %}
2389
2390 // for byte regs
2391 enc_class REX_breg_mem(rRegI reg, memory mem)
2392 %{
2393 if ($reg$$reg < 8) {
2394 if ($mem$$base < 8) {
2395 if ($mem$$index >= 8) {
2396 emit_opcode(cbuf, Assembler::REX_X);
2397 } else if ($reg$$reg >= 4) {
2398 emit_opcode(cbuf, Assembler::REX);
2399 }
2400 } else {
2401 if ($mem$$index < 8) {
2402 emit_opcode(cbuf, Assembler::REX_B);
2403 } else {
2404 emit_opcode(cbuf, Assembler::REX_XB);
2405 }
2406 }
2407 } else {
2408 if ($mem$$base < 8) {
2409 if ($mem$$index < 8) {
2410 emit_opcode(cbuf, Assembler::REX_R);
2411 } else {
2412 emit_opcode(cbuf, Assembler::REX_RX);
2413 }
2414 } else {
2415 if ($mem$$index < 8) {
2416 emit_opcode(cbuf, Assembler::REX_RB);
2417 } else {
2418 emit_opcode(cbuf, Assembler::REX_RXB);
2419 }
2420 }
2421 }
2422 %}
2423
2424 enc_class REX_reg(rRegI reg)
2425 %{
2426 if ($reg$$reg >= 8) {
2427 emit_opcode(cbuf, Assembler::REX_B);
2428 }
2429 %}
2430
2431 enc_class REX_reg_wide(rRegI reg)
2432 %{
2433 if ($reg$$reg < 8) {
2434 emit_opcode(cbuf, Assembler::REX_W);
2435 } else {
2436 emit_opcode(cbuf, Assembler::REX_WB);
2437 }
2438 %}
2439
2440 enc_class REX_reg_reg(rRegI dst, rRegI src)
2441 %{
2442 if ($dst$$reg < 8) {
2443 if ($src$$reg >= 8) {
2444 emit_opcode(cbuf, Assembler::REX_B);
2445 }
2446 } else {
2447 if ($src$$reg < 8) {
2448 emit_opcode(cbuf, Assembler::REX_R);
2449 } else {
2450 emit_opcode(cbuf, Assembler::REX_RB);
2451 }
2452 }
2453 %}
2454
2455 enc_class REX_reg_reg_wide(rRegI dst, rRegI src)
2456 %{
2457 if ($dst$$reg < 8) {
2458 if ($src$$reg < 8) {
2459 emit_opcode(cbuf, Assembler::REX_W);
2460 } else {
2461 emit_opcode(cbuf, Assembler::REX_WB);
2462 }
2463 } else {
2464 if ($src$$reg < 8) {
2465 emit_opcode(cbuf, Assembler::REX_WR);
2466 } else {
2467 emit_opcode(cbuf, Assembler::REX_WRB);
2468 }
2469 }
2470 %}
2471
2472 enc_class REX_reg_mem(rRegI reg, memory mem)
2473 %{
2474 if ($reg$$reg < 8) {
2475 if ($mem$$base < 8) {
2476 if ($mem$$index >= 8) {
2477 emit_opcode(cbuf, Assembler::REX_X);
2478 }
2479 } else {
2480 if ($mem$$index < 8) {
2481 emit_opcode(cbuf, Assembler::REX_B);
2482 } else {
2483 emit_opcode(cbuf, Assembler::REX_XB);
2484 }
2485 }
2486 } else {
2487 if ($mem$$base < 8) {
2488 if ($mem$$index < 8) {
2489 emit_opcode(cbuf, Assembler::REX_R);
2490 } else {
2491 emit_opcode(cbuf, Assembler::REX_RX);
2492 }
2493 } else {
2494 if ($mem$$index < 8) {
2495 emit_opcode(cbuf, Assembler::REX_RB);
2496 } else {
2497 emit_opcode(cbuf, Assembler::REX_RXB);
2498 }
2499 }
2500 }
2501 %}
2502
2503 enc_class REX_reg_mem_wide(rRegL reg, memory mem)
2504 %{
2505 if ($reg$$reg < 8) {
2506 if ($mem$$base < 8) {
2507 if ($mem$$index < 8) {
2508 emit_opcode(cbuf, Assembler::REX_W);
2509 } else {
2510 emit_opcode(cbuf, Assembler::REX_WX);
2511 }
2512 } else {
2513 if ($mem$$index < 8) {
2514 emit_opcode(cbuf, Assembler::REX_WB);
2515 } else {
2516 emit_opcode(cbuf, Assembler::REX_WXB);
2517 }
2518 }
2519 } else {
2520 if ($mem$$base < 8) {
2521 if ($mem$$index < 8) {
2522 emit_opcode(cbuf, Assembler::REX_WR);
2523 } else {
2524 emit_opcode(cbuf, Assembler::REX_WRX);
2525 }
2526 } else {
2527 if ($mem$$index < 8) {
2528 emit_opcode(cbuf, Assembler::REX_WRB);
2529 } else {
2530 emit_opcode(cbuf, Assembler::REX_WRXB);
2531 }
2532 }
2533 }
2534 %}
2535
2536 enc_class reg_mem(rRegI ereg, memory mem)
2537 %{
2538 // High registers handle in encode_RegMem
2539 int reg = $ereg$$reg;
2540 int base = $mem$$base;
2541 int index = $mem$$index;
2542 int scale = $mem$$scale;
2543 int disp = $mem$$disp;
2544 relocInfo::relocType disp_reloc = $mem->disp_reloc();
2545
2546 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
2547 %}
2548
2549 enc_class RM_opc_mem(immI rm_opcode, memory mem)
2550 %{
2551 int rm_byte_opcode = $rm_opcode$$constant;
2552
2553 // High registers handle in encode_RegMem
2554 int base = $mem$$base;
2555 int index = $mem$$index;
2556 int scale = $mem$$scale;
2557 int displace = $mem$$disp;
2558
2559 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when
2560 // working with static
2561 // globals
2562 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace,
2563 disp_reloc);
2564 %}
2565
2566 enc_class reg_lea(rRegI dst, rRegI src0, immI src1)
2567 %{
2568 int reg_encoding = $dst$$reg;
2569 int base = $src0$$reg; // 0xFFFFFFFF indicates no base
2570 int index = 0x04; // 0x04 indicates no index
2571 int scale = 0x00; // 0x00 indicates no scale
2572 int displace = $src1$$constant; // 0x00 indicates no displacement
2573 relocInfo::relocType disp_reloc = relocInfo::none;
2574 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace,
2575 disp_reloc);
2576 %}
2577
2578 enc_class neg_reg(rRegI dst)
2579 %{
2580 int dstenc = $dst$$reg;
2581 if (dstenc >= 8) {
2582 emit_opcode(cbuf, Assembler::REX_B);
2583 dstenc -= 8;
2584 }
2585 // NEG $dst
2586 emit_opcode(cbuf, 0xF7);
2587 emit_rm(cbuf, 0x3, 0x03, dstenc);
2588 %}
2589
2590 enc_class neg_reg_wide(rRegI dst)
2591 %{
2592 int dstenc = $dst$$reg;
2593 if (dstenc < 8) {
2594 emit_opcode(cbuf, Assembler::REX_W);
2595 } else {
2596 emit_opcode(cbuf, Assembler::REX_WB);
2597 dstenc -= 8;
2598 }
2599 // NEG $dst
2600 emit_opcode(cbuf, 0xF7);
2601 emit_rm(cbuf, 0x3, 0x03, dstenc);
2602 %}
2603
2604 enc_class setLT_reg(rRegI dst)
2605 %{
2606 int dstenc = $dst$$reg;
2607 if (dstenc >= 8) {
2608 emit_opcode(cbuf, Assembler::REX_B);
2609 dstenc -= 8;
2610 } else if (dstenc >= 4) {
2611 emit_opcode(cbuf, Assembler::REX);
2612 }
2613 // SETLT $dst
2614 emit_opcode(cbuf, 0x0F);
2615 emit_opcode(cbuf, 0x9C);
2616 emit_rm(cbuf, 0x3, 0x0, dstenc);
2617 %}
2618
2619 enc_class setNZ_reg(rRegI dst)
2620 %{
2621 int dstenc = $dst$$reg;
2622 if (dstenc >= 8) {
2623 emit_opcode(cbuf, Assembler::REX_B);
2624 dstenc -= 8;
2625 } else if (dstenc >= 4) {
2626 emit_opcode(cbuf, Assembler::REX);
2627 }
2628 // SETNZ $dst
2629 emit_opcode(cbuf, 0x0F);
2630 emit_opcode(cbuf, 0x95);
2631 emit_rm(cbuf, 0x3, 0x0, dstenc);
2632 %}
2633
2634
2635 // Compare the lonogs and set -1, 0, or 1 into dst
2636 enc_class cmpl3_flag(rRegL src1, rRegL src2, rRegI dst)
2637 %{
2638 int src1enc = $src1$$reg;
2639 int src2enc = $src2$$reg;
2640 int dstenc = $dst$$reg;
2641
2642 // cmpq $src1, $src2
2643 if (src1enc < 8) {
2644 if (src2enc < 8) {
2645 emit_opcode(cbuf, Assembler::REX_W);
2646 } else {
2647 emit_opcode(cbuf, Assembler::REX_WB);
2648 }
2649 } else {
2650 if (src2enc < 8) {
2651 emit_opcode(cbuf, Assembler::REX_WR);
2652 } else {
2653 emit_opcode(cbuf, Assembler::REX_WRB);
2654 }
2655 }
2656 emit_opcode(cbuf, 0x3B);
2657 emit_rm(cbuf, 0x3, src1enc & 7, src2enc & 7);
2658
2659 // movl $dst, -1
2660 if (dstenc >= 8) {
2661 emit_opcode(cbuf, Assembler::REX_B);
2662 }
2663 emit_opcode(cbuf, 0xB8 | (dstenc & 7));
2664 emit_d32(cbuf, -1);
2665
2666 // jl,s done
2667 emit_opcode(cbuf, 0x7C);
2668 emit_d8(cbuf, dstenc < 4 ? 0x06 : 0x08);
2669
2670 // setne $dst
2671 if (dstenc >= 4) {
2672 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_B);
2673 }
2674 emit_opcode(cbuf, 0x0F);
2675 emit_opcode(cbuf, 0x95);
2676 emit_opcode(cbuf, 0xC0 | (dstenc & 7));
2677
2678 // movzbl $dst, $dst
2679 if (dstenc >= 4) {
2680 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_RB);
2681 }
2682 emit_opcode(cbuf, 0x0F);
2683 emit_opcode(cbuf, 0xB6);
2684 emit_rm(cbuf, 0x3, dstenc & 7, dstenc & 7);
2685 %}
2686
2687 enc_class Push_ResultXD(regD dst) %{
2688 MacroAssembler _masm(&cbuf);
2689 __ fstp_d(Address(rsp, 0));
2690 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
2691 __ addptr(rsp, 8);
2692 %}
2693
2694 enc_class Push_SrcXD(regD src) %{
2695 MacroAssembler _masm(&cbuf);
2696 __ subptr(rsp, 8);
2697 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
2698 __ fld_d(Address(rsp, 0));
2699 %}
2700
2701
2702 enc_class enc_rethrow()
2703 %{
2704 cbuf.set_insts_mark();
2705 emit_opcode(cbuf, 0xE9); // jmp entry
2706 emit_d32_reloc(cbuf,
2707 (int) (OptoRuntime::rethrow_stub() - cbuf.insts_end() - 4),
2708 runtime_call_Relocation::spec(),
2709 RELOC_DISP32);
2710 %}
2711
2712 %}
2713
2714
2715
2716 //----------FRAME--------------------------------------------------------------
2717 // Definition of frame structure and management information.
2718 //
2719 // S T A C K L A Y O U T Allocators stack-slot number
2720 // | (to get allocators register number
2721 // G Owned by | | v add OptoReg::stack0())
2722 // r CALLER | |
2723 // o | +--------+ pad to even-align allocators stack-slot
2724 // w V | pad0 | numbers; owned by CALLER
2725 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
2726 // h ^ | in | 5
2727 // | | args | 4 Holes in incoming args owned by SELF
2728 // | | | | 3
2729 // | | +--------+
2730 // V | | old out| Empty on Intel, window on Sparc
2731 // | old |preserve| Must be even aligned.
2732 // | SP-+--------+----> Matcher::_old_SP, even aligned
2733 // | | in | 3 area for Intel ret address
2734 // Owned by |preserve| Empty on Sparc.
2735 // SELF +--------+
2736 // | | pad2 | 2 pad to align old SP
2737 // | +--------+ 1
2738 // | | locks | 0
2739 // | +--------+----> OptoReg::stack0(), even aligned
2740 // | | pad1 | 11 pad to align new SP
2741 // | +--------+
2742 // | | | 10
2743 // | | spills | 9 spills
2744 // V | | 8 (pad0 slot for callee)
2745 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
2746 // ^ | out | 7
2747 // | | args | 6 Holes in outgoing args owned by CALLEE
2748 // Owned by +--------+
2749 // CALLEE | new out| 6 Empty on Intel, window on Sparc
2750 // | new |preserve| Must be even-aligned.
2751 // | SP-+--------+----> Matcher::_new_SP, even aligned
2752 // | | |
2753 //
2754 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
2755 // known from SELF's arguments and the Java calling convention.
2756 // Region 6-7 is determined per call site.
2757 // Note 2: If the calling convention leaves holes in the incoming argument
2758 // area, those holes are owned by SELF. Holes in the outgoing area
2759 // are owned by the CALLEE. Holes should not be nessecary in the
2760 // incoming area, as the Java calling convention is completely under
2761 // the control of the AD file. Doubles can be sorted and packed to
2762 // avoid holes. Holes in the outgoing arguments may be nessecary for
2763 // varargs C calling conventions.
2764 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
2765 // even aligned with pad0 as needed.
2766 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
2767 // region 6-11 is even aligned; it may be padded out more so that
2768 // the region from SP to FP meets the minimum stack alignment.
2769 // Note 4: For I2C adapters, the incoming FP may not meet the minimum stack
2770 // alignment. Region 11, pad1, may be dynamically extended so that
2771 // SP meets the minimum alignment.
2772
2773 frame
2774 %{
2775 // These three registers define part of the calling convention
2776 // between compiled code and the interpreter.
2777 inline_cache_reg(RAX); // Inline Cache Register
2778
2779 // Optional: name the operand used by cisc-spilling to access
2780 // [stack_pointer + offset]
2781 cisc_spilling_operand_name(indOffset32);
2782
2783 // Number of stack slots consumed by locking an object
2784 sync_stack_slots(2);
2785
2786 // Compiled code's Frame Pointer
2787 frame_pointer(RSP);
2788
2789 // Interpreter stores its frame pointer in a register which is
2790 // stored to the stack by I2CAdaptors.
2791 // I2CAdaptors convert from interpreted java to compiled java.
2792 interpreter_frame_pointer(RBP);
2793
2794 // Stack alignment requirement
2795 stack_alignment(StackAlignmentInBytes); // Alignment size in bytes (128-bit -> 16 bytes)
2796
2797 // Number of outgoing stack slots killed above the out_preserve_stack_slots
2798 // for calls to C. Supports the var-args backing area for register parms.
2799 varargs_C_out_slots_killed(frame::arg_reg_save_area_bytes/BytesPerInt);
2800
2801 // The after-PROLOG location of the return address. Location of
2802 // return address specifies a type (REG or STACK) and a number
2803 // representing the register number (i.e. - use a register name) or
2804 // stack slot.
2805 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
2806 // Otherwise, it is above the locks and verification slot and alignment word
2807 return_addr(STACK - 2 +
2808 align_up((Compile::current()->in_preserve_stack_slots() +
2809 Compile::current()->fixed_slots()),
2810 stack_alignment_in_slots()));
2811
2812 // Location of compiled Java return values. Same as C for now.
2813 return_value
2814 %{
2815 assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL,
2816 "only return normal values");
2817
2818 static const int lo[Op_RegL + 1] = {
2819 0,
2820 0,
2821 RAX_num, // Op_RegN
2822 RAX_num, // Op_RegI
2823 RAX_num, // Op_RegP
2824 XMM0_num, // Op_RegF
2825 XMM0_num, // Op_RegD
2826 RAX_num // Op_RegL
2827 };
2828 static const int hi[Op_RegL + 1] = {
2829 0,
2830 0,
2831 OptoReg::Bad, // Op_RegN
2832 OptoReg::Bad, // Op_RegI
2833 RAX_H_num, // Op_RegP
2834 OptoReg::Bad, // Op_RegF
2835 XMM0b_num, // Op_RegD
2836 RAX_H_num // Op_RegL
2837 };
2838 // Excluded flags and vector registers.
2839 assert(ARRAY_SIZE(hi) == _last_machine_leaf - 8, "missing type");
2840 return OptoRegPair(hi[ideal_reg], lo[ideal_reg]);
2841 %}
2842 %}
2843
2844 //----------ATTRIBUTES---------------------------------------------------------
2845 //----------Operand Attributes-------------------------------------------------
2846 op_attrib op_cost(0); // Required cost attribute
2847
2848 //----------Instruction Attributes---------------------------------------------
2849 ins_attrib ins_cost(100); // Required cost attribute
2850 ins_attrib ins_size(8); // Required size attribute (in bits)
2851 ins_attrib ins_short_branch(0); // Required flag: is this instruction
2852 // a non-matching short branch variant
2853 // of some long branch?
2854 ins_attrib ins_alignment(1); // Required alignment attribute (must
2855 // be a power of 2) specifies the
2856 // alignment that some part of the
2857 // instruction (not necessarily the
2858 // start) requires. If > 1, a
2859 // compute_padding() function must be
2860 // provided for the instruction
2861
2862 //----------OPERANDS-----------------------------------------------------------
2863 // Operand definitions must precede instruction definitions for correct parsing
2864 // in the ADLC because operands constitute user defined types which are used in
2865 // instruction definitions.
2866
2867 //----------Simple Operands----------------------------------------------------
2868 // Immediate Operands
2869 // Integer Immediate
2870 operand immI()
2871 %{
2872 match(ConI);
2873
2874 op_cost(10);
2875 format %{ %}
2876 interface(CONST_INTER);
2877 %}
2878
2879 // Constant for test vs zero
2880 operand immI_0()
2881 %{
2882 predicate(n->get_int() == 0);
2883 match(ConI);
2884
2885 op_cost(0);
2886 format %{ %}
2887 interface(CONST_INTER);
2888 %}
2889
2890 // Constant for increment
2891 operand immI_1()
2892 %{
2893 predicate(n->get_int() == 1);
2894 match(ConI);
2895
2896 op_cost(0);
2897 format %{ %}
2898 interface(CONST_INTER);
2899 %}
2900
2901 // Constant for decrement
2902 operand immI_M1()
2903 %{
2904 predicate(n->get_int() == -1);
2905 match(ConI);
2906
2907 op_cost(0);
2908 format %{ %}
2909 interface(CONST_INTER);
2910 %}
2911
2912 operand immI_2()
2913 %{
2914 predicate(n->get_int() == 2);
2915 match(ConI);
2916
2917 op_cost(0);
2918 format %{ %}
2919 interface(CONST_INTER);
2920 %}
2921
2922 operand immI_4()
2923 %{
2924 predicate(n->get_int() == 4);
2925 match(ConI);
2926
2927 op_cost(0);
2928 format %{ %}
2929 interface(CONST_INTER);
2930 %}
2931
2932 operand immI_8()
2933 %{
2934 predicate(n->get_int() == 8);
2935 match(ConI);
2936
2937 op_cost(0);
2938 format %{ %}
2939 interface(CONST_INTER);
2940 %}
2941
2942 // Valid scale values for addressing modes
2943 operand immI2()
2944 %{
2945 predicate(0 <= n->get_int() && (n->get_int() <= 3));
2946 match(ConI);
2947
2948 format %{ %}
2949 interface(CONST_INTER);
2950 %}
2951
2952 operand immU7()
2953 %{
2954 predicate((0 <= n->get_int()) && (n->get_int() <= 0x7F));
2955 match(ConI);
2956
2957 op_cost(5);
2958 format %{ %}
2959 interface(CONST_INTER);
2960 %}
2961
2962 operand immI8()
2963 %{
2964 predicate((-0x80 <= n->get_int()) && (n->get_int() < 0x80));
2965 match(ConI);
2966
2967 op_cost(5);
2968 format %{ %}
2969 interface(CONST_INTER);
2970 %}
2971
2972 operand immU8()
2973 %{
2974 predicate((0 <= n->get_int()) && (n->get_int() <= 255));
2975 match(ConI);
2976
2977 op_cost(5);
2978 format %{ %}
2979 interface(CONST_INTER);
2980 %}
2981
2982 operand immI16()
2983 %{
2984 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
2985 match(ConI);
2986
2987 op_cost(10);
2988 format %{ %}
2989 interface(CONST_INTER);
2990 %}
2991
2992 // Int Immediate non-negative
2993 operand immU31()
2994 %{
2995 predicate(n->get_int() >= 0);
2996 match(ConI);
2997
2998 op_cost(0);
2999 format %{ %}
3000 interface(CONST_INTER);
3001 %}
3002
3003 // Constant for long shifts
3004 operand immI_32()
3005 %{
3006 predicate( n->get_int() == 32 );
3007 match(ConI);
3008
3009 op_cost(0);
3010 format %{ %}
3011 interface(CONST_INTER);
3012 %}
3013
3014 // Constant for long shifts
3015 operand immI_64()
3016 %{
3017 predicate( n->get_int() == 64 );
3018 match(ConI);
3019
3020 op_cost(0);
3021 format %{ %}
3022 interface(CONST_INTER);
3023 %}
3024
3025 // Pointer Immediate
3026 operand immP()
3027 %{
3028 match(ConP);
3029
3030 op_cost(10);
3031 format %{ %}
3032 interface(CONST_INTER);
3033 %}
3034
3035 // NULL Pointer Immediate
3036 operand immP0()
3037 %{
3038 predicate(n->get_ptr() == 0);
3039 match(ConP);
3040
3041 op_cost(5);
3042 format %{ %}
3043 interface(CONST_INTER);
3044 %}
3045
3046 // Pointer Immediate
3047 operand immN() %{
3048 match(ConN);
3049
3050 op_cost(10);
3051 format %{ %}
3052 interface(CONST_INTER);
3053 %}
3054
3055 operand immNKlass() %{
3056 match(ConNKlass);
3057
3058 op_cost(10);
3059 format %{ %}
3060 interface(CONST_INTER);
3061 %}
3062
3063 // NULL Pointer Immediate
3064 operand immN0() %{
3065 predicate(n->get_narrowcon() == 0);
3066 match(ConN);
3067
3068 op_cost(5);
3069 format %{ %}
3070 interface(CONST_INTER);
3071 %}
3072
3073 operand immP31()
3074 %{
3075 predicate(n->as_Type()->type()->reloc() == relocInfo::none
3076 && (n->get_ptr() >> 31) == 0);
3077 match(ConP);
3078
3079 op_cost(5);
3080 format %{ %}
3081 interface(CONST_INTER);
3082 %}
3083
3084
3085 // Long Immediate
3086 operand immL()
3087 %{
3088 match(ConL);
3089
3090 op_cost(20);
3091 format %{ %}
3092 interface(CONST_INTER);
3093 %}
3094
3095 // Long Immediate 8-bit
3096 operand immL8()
3097 %{
3098 predicate(-0x80L <= n->get_long() && n->get_long() < 0x80L);
3099 match(ConL);
3100
3101 op_cost(5);
3102 format %{ %}
3103 interface(CONST_INTER);
3104 %}
3105
3106 // Long Immediate 32-bit unsigned
3107 operand immUL32()
3108 %{
3109 predicate(n->get_long() == (unsigned int) (n->get_long()));
3110 match(ConL);
3111
3112 op_cost(10);
3113 format %{ %}
3114 interface(CONST_INTER);
3115 %}
3116
3117 // Long Immediate 32-bit signed
3118 operand immL32()
3119 %{
3120 predicate(n->get_long() == (int) (n->get_long()));
3121 match(ConL);
3122
3123 op_cost(15);
3124 format %{ %}
3125 interface(CONST_INTER);
3126 %}
3127
3128 operand immL_Pow2()
3129 %{
3130 predicate(is_power_of_2((julong)n->get_long()));
3131 match(ConL);
3132
3133 op_cost(15);
3134 format %{ %}
3135 interface(CONST_INTER);
3136 %}
3137
3138 operand immL_NotPow2()
3139 %{
3140 predicate(is_power_of_2((julong)~n->get_long()));
3141 match(ConL);
3142
3143 op_cost(15);
3144 format %{ %}
3145 interface(CONST_INTER);
3146 %}
3147
3148 // Long Immediate zero
3149 operand immL0()
3150 %{
3151 predicate(n->get_long() == 0L);
3152 match(ConL);
3153
3154 op_cost(10);
3155 format %{ %}
3156 interface(CONST_INTER);
3157 %}
3158
3159 // Constant for increment
3160 operand immL1()
3161 %{
3162 predicate(n->get_long() == 1);
3163 match(ConL);
3164
3165 format %{ %}
3166 interface(CONST_INTER);
3167 %}
3168
3169 // Constant for decrement
3170 operand immL_M1()
3171 %{
3172 predicate(n->get_long() == -1);
3173 match(ConL);
3174
3175 format %{ %}
3176 interface(CONST_INTER);
3177 %}
3178
3179 // Long Immediate: the value 10
3180 operand immL10()
3181 %{
3182 predicate(n->get_long() == 10);
3183 match(ConL);
3184
3185 format %{ %}
3186 interface(CONST_INTER);
3187 %}
3188
3189 // Long immediate from 0 to 127.
3190 // Used for a shorter form of long mul by 10.
3191 operand immL_127()
3192 %{
3193 predicate(0 <= n->get_long() && n->get_long() < 0x80);
3194 match(ConL);
3195
3196 op_cost(10);
3197 format %{ %}
3198 interface(CONST_INTER);
3199 %}
3200
3201 // Long Immediate: low 32-bit mask
3202 operand immL_32bits()
3203 %{
3204 predicate(n->get_long() == 0xFFFFFFFFL);
3205 match(ConL);
3206 op_cost(20);
3207
3208 format %{ %}
3209 interface(CONST_INTER);
3210 %}
3211
3212 // Int Immediate: 2^n-1, postive
3213 operand immI_Pow2M1()
3214 %{
3215 predicate((n->get_int() > 0)
3216 && is_power_of_2(n->get_int() + 1));
3217 match(ConI);
3218
3219 op_cost(20);
3220 format %{ %}
3221 interface(CONST_INTER);
3222 %}
3223
3224 // Float Immediate zero
3225 operand immF0()
3226 %{
3227 predicate(jint_cast(n->getf()) == 0);
3228 match(ConF);
3229
3230 op_cost(5);
3231 format %{ %}
3232 interface(CONST_INTER);
3233 %}
3234
3235 // Float Immediate
3236 operand immF()
3237 %{
3238 match(ConF);
3239
3240 op_cost(15);
3241 format %{ %}
3242 interface(CONST_INTER);
3243 %}
3244
3245 // Double Immediate zero
3246 operand immD0()
3247 %{
3248 predicate(jlong_cast(n->getd()) == 0);
3249 match(ConD);
3250
3251 op_cost(5);
3252 format %{ %}
3253 interface(CONST_INTER);
3254 %}
3255
3256 // Double Immediate
3257 operand immD()
3258 %{
3259 match(ConD);
3260
3261 op_cost(15);
3262 format %{ %}
3263 interface(CONST_INTER);
3264 %}
3265
3266 // Immediates for special shifts (sign extend)
3267
3268 // Constants for increment
3269 operand immI_16()
3270 %{
3271 predicate(n->get_int() == 16);
3272 match(ConI);
3273
3274 format %{ %}
3275 interface(CONST_INTER);
3276 %}
3277
3278 operand immI_24()
3279 %{
3280 predicate(n->get_int() == 24);
3281 match(ConI);
3282
3283 format %{ %}
3284 interface(CONST_INTER);
3285 %}
3286
3287 // Constant for byte-wide masking
3288 operand immI_255()
3289 %{
3290 predicate(n->get_int() == 255);
3291 match(ConI);
3292
3293 format %{ %}
3294 interface(CONST_INTER);
3295 %}
3296
3297 // Constant for short-wide masking
3298 operand immI_65535()
3299 %{
3300 predicate(n->get_int() == 65535);
3301 match(ConI);
3302
3303 format %{ %}
3304 interface(CONST_INTER);
3305 %}
3306
3307 // Constant for byte-wide masking
3308 operand immL_255()
3309 %{
3310 predicate(n->get_long() == 255);
3311 match(ConL);
3312
3313 format %{ %}
3314 interface(CONST_INTER);
3315 %}
3316
3317 // Constant for short-wide masking
3318 operand immL_65535()
3319 %{
3320 predicate(n->get_long() == 65535);
3321 match(ConL);
3322
3323 format %{ %}
3324 interface(CONST_INTER);
3325 %}
3326
3327 operand kReg()
3328 %{
3329 constraint(ALLOC_IN_RC(vectmask_reg));
3330 match(RegVectMask);
3331 format %{%}
3332 interface(REG_INTER);
3333 %}
3334
3335 operand kReg_K1()
3336 %{
3337 constraint(ALLOC_IN_RC(vectmask_reg_K1));
3338 match(RegVectMask);
3339 format %{%}
3340 interface(REG_INTER);
3341 %}
3342
3343 operand kReg_K2()
3344 %{
3345 constraint(ALLOC_IN_RC(vectmask_reg_K2));
3346 match(RegVectMask);
3347 format %{%}
3348 interface(REG_INTER);
3349 %}
3350
3351 // Special Registers
3352 operand kReg_K3()
3353 %{
3354 constraint(ALLOC_IN_RC(vectmask_reg_K3));
3355 match(RegVectMask);
3356 format %{%}
3357 interface(REG_INTER);
3358 %}
3359
3360 operand kReg_K4()
3361 %{
3362 constraint(ALLOC_IN_RC(vectmask_reg_K4));
3363 match(RegVectMask);
3364 format %{%}
3365 interface(REG_INTER);
3366 %}
3367
3368 operand kReg_K5()
3369 %{
3370 constraint(ALLOC_IN_RC(vectmask_reg_K5));
3371 match(RegVectMask);
3372 format %{%}
3373 interface(REG_INTER);
3374 %}
3375
3376 operand kReg_K6()
3377 %{
3378 constraint(ALLOC_IN_RC(vectmask_reg_K6));
3379 match(RegVectMask);
3380 format %{%}
3381 interface(REG_INTER);
3382 %}
3383
3384 // Special Registers
3385 operand kReg_K7()
3386 %{
3387 constraint(ALLOC_IN_RC(vectmask_reg_K7));
3388 match(RegVectMask);
3389 format %{%}
3390 interface(REG_INTER);
3391 %}
3392
3393 // Register Operands
3394 // Integer Register
3395 operand rRegI()
3396 %{
3397 constraint(ALLOC_IN_RC(int_reg));
3398 match(RegI);
3399
3400 match(rax_RegI);
3401 match(rbx_RegI);
3402 match(rcx_RegI);
3403 match(rdx_RegI);
3404 match(rdi_RegI);
3405
3406 format %{ %}
3407 interface(REG_INTER);
3408 %}
3409
3410 // Special Registers
3411 operand rax_RegI()
3412 %{
3413 constraint(ALLOC_IN_RC(int_rax_reg));
3414 match(RegI);
3415 match(rRegI);
3416
3417 format %{ "RAX" %}
3418 interface(REG_INTER);
3419 %}
3420
3421 // Special Registers
3422 operand rbx_RegI()
3423 %{
3424 constraint(ALLOC_IN_RC(int_rbx_reg));
3425 match(RegI);
3426 match(rRegI);
3427
3428 format %{ "RBX" %}
3429 interface(REG_INTER);
3430 %}
3431
3432 operand rcx_RegI()
3433 %{
3434 constraint(ALLOC_IN_RC(int_rcx_reg));
3435 match(RegI);
3436 match(rRegI);
3437
3438 format %{ "RCX" %}
3439 interface(REG_INTER);
3440 %}
3441
3442 operand rdx_RegI()
3443 %{
3444 constraint(ALLOC_IN_RC(int_rdx_reg));
3445 match(RegI);
3446 match(rRegI);
3447
3448 format %{ "RDX" %}
3449 interface(REG_INTER);
3450 %}
3451
3452 operand rdi_RegI()
3453 %{
3454 constraint(ALLOC_IN_RC(int_rdi_reg));
3455 match(RegI);
3456 match(rRegI);
3457
3458 format %{ "RDI" %}
3459 interface(REG_INTER);
3460 %}
3461
3462 operand no_rax_rdx_RegI()
3463 %{
3464 constraint(ALLOC_IN_RC(int_no_rax_rdx_reg));
3465 match(RegI);
3466 match(rbx_RegI);
3467 match(rcx_RegI);
3468 match(rdi_RegI);
3469
3470 format %{ %}
3471 interface(REG_INTER);
3472 %}
3473
3474 // Pointer Register
3475 operand any_RegP()
3476 %{
3477 constraint(ALLOC_IN_RC(any_reg));
3478 match(RegP);
3479 match(rax_RegP);
3480 match(rbx_RegP);
3481 match(rdi_RegP);
3482 match(rsi_RegP);
3483 match(rbp_RegP);
3484 match(r15_RegP);
3485 match(rRegP);
3486
3487 format %{ %}
3488 interface(REG_INTER);
3489 %}
3490
3491 operand rRegP()
3492 %{
3493 constraint(ALLOC_IN_RC(ptr_reg));
3494 match(RegP);
3495 match(rax_RegP);
3496 match(rbx_RegP);
3497 match(rdi_RegP);
3498 match(rsi_RegP);
3499 match(rbp_RegP); // See Q&A below about
3500 match(r15_RegP); // r15_RegP and rbp_RegP.
3501
3502 format %{ %}
3503 interface(REG_INTER);
3504 %}
3505
3506 operand rRegN() %{
3507 constraint(ALLOC_IN_RC(int_reg));
3508 match(RegN);
3509
3510 format %{ %}
3511 interface(REG_INTER);
3512 %}
3513
3514 // Question: Why is r15_RegP (the read-only TLS register) a match for rRegP?
3515 // Answer: Operand match rules govern the DFA as it processes instruction inputs.
3516 // It's fine for an instruction input that expects rRegP to match a r15_RegP.
3517 // The output of an instruction is controlled by the allocator, which respects
3518 // register class masks, not match rules. Unless an instruction mentions
3519 // r15_RegP or any_RegP explicitly as its output, r15 will not be considered
3520 // by the allocator as an input.
3521 // The same logic applies to rbp_RegP being a match for rRegP: If PreserveFramePointer==true,
3522 // the RBP is used as a proper frame pointer and is not included in ptr_reg. As a
3523 // result, RBP is not included in the output of the instruction either.
3524
3525 operand no_rax_RegP()
3526 %{
3527 constraint(ALLOC_IN_RC(ptr_no_rax_reg));
3528 match(RegP);
3529 match(rbx_RegP);
3530 match(rsi_RegP);
3531 match(rdi_RegP);
3532
3533 format %{ %}
3534 interface(REG_INTER);
3535 %}
3536
3537 // This operand is not allowed to use RBP even if
3538 // RBP is not used to hold the frame pointer.
3539 operand no_rbp_RegP()
3540 %{
3541 constraint(ALLOC_IN_RC(ptr_reg_no_rbp));
3542 match(RegP);
3543 match(rbx_RegP);
3544 match(rsi_RegP);
3545 match(rdi_RegP);
3546
3547 format %{ %}
3548 interface(REG_INTER);
3549 %}
3550
3551 operand no_rax_rbx_RegP()
3552 %{
3553 constraint(ALLOC_IN_RC(ptr_no_rax_rbx_reg));
3554 match(RegP);
3555 match(rsi_RegP);
3556 match(rdi_RegP);
3557
3558 format %{ %}
3559 interface(REG_INTER);
3560 %}
3561
3562 // Special Registers
3563 // Return a pointer value
3564 operand rax_RegP()
3565 %{
3566 constraint(ALLOC_IN_RC(ptr_rax_reg));
3567 match(RegP);
3568 match(rRegP);
3569
3570 format %{ %}
3571 interface(REG_INTER);
3572 %}
3573
3574 // Special Registers
3575 // Return a compressed pointer value
3576 operand rax_RegN()
3577 %{
3578 constraint(ALLOC_IN_RC(int_rax_reg));
3579 match(RegN);
3580 match(rRegN);
3581
3582 format %{ %}
3583 interface(REG_INTER);
3584 %}
3585
3586 // Used in AtomicAdd
3587 operand rbx_RegP()
3588 %{
3589 constraint(ALLOC_IN_RC(ptr_rbx_reg));
3590 match(RegP);
3591 match(rRegP);
3592
3593 format %{ %}
3594 interface(REG_INTER);
3595 %}
3596
3597 operand rsi_RegP()
3598 %{
3599 constraint(ALLOC_IN_RC(ptr_rsi_reg));
3600 match(RegP);
3601 match(rRegP);
3602
3603 format %{ %}
3604 interface(REG_INTER);
3605 %}
3606
3607 operand rbp_RegP()
3608 %{
3609 constraint(ALLOC_IN_RC(ptr_rbp_reg));
3610 match(RegP);
3611 match(rRegP);
3612
3613 format %{ %}
3614 interface(REG_INTER);
3615 %}
3616
3617 // Used in rep stosq
3618 operand rdi_RegP()
3619 %{
3620 constraint(ALLOC_IN_RC(ptr_rdi_reg));
3621 match(RegP);
3622 match(rRegP);
3623
3624 format %{ %}
3625 interface(REG_INTER);
3626 %}
3627
3628 operand r15_RegP()
3629 %{
3630 constraint(ALLOC_IN_RC(ptr_r15_reg));
3631 match(RegP);
3632 match(rRegP);
3633
3634 format %{ %}
3635 interface(REG_INTER);
3636 %}
3637
3638 operand rRegL()
3639 %{
3640 constraint(ALLOC_IN_RC(long_reg));
3641 match(RegL);
3642 match(rax_RegL);
3643 match(rdx_RegL);
3644
3645 format %{ %}
3646 interface(REG_INTER);
3647 %}
3648
3649 // Special Registers
3650 operand no_rax_rdx_RegL()
3651 %{
3652 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg));
3653 match(RegL);
3654 match(rRegL);
3655
3656 format %{ %}
3657 interface(REG_INTER);
3658 %}
3659
3660 operand no_rax_RegL()
3661 %{
3662 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg));
3663 match(RegL);
3664 match(rRegL);
3665 match(rdx_RegL);
3666
3667 format %{ %}
3668 interface(REG_INTER);
3669 %}
3670
3671 operand rax_RegL()
3672 %{
3673 constraint(ALLOC_IN_RC(long_rax_reg));
3674 match(RegL);
3675 match(rRegL);
3676
3677 format %{ "RAX" %}
3678 interface(REG_INTER);
3679 %}
3680
3681 operand rcx_RegL()
3682 %{
3683 constraint(ALLOC_IN_RC(long_rcx_reg));
3684 match(RegL);
3685 match(rRegL);
3686
3687 format %{ %}
3688 interface(REG_INTER);
3689 %}
3690
3691 operand rdx_RegL()
3692 %{
3693 constraint(ALLOC_IN_RC(long_rdx_reg));
3694 match(RegL);
3695 match(rRegL);
3696
3697 format %{ %}
3698 interface(REG_INTER);
3699 %}
3700
3701 // Flags register, used as output of compare instructions
3702 operand rFlagsReg()
3703 %{
3704 constraint(ALLOC_IN_RC(int_flags));
3705 match(RegFlags);
3706
3707 format %{ "RFLAGS" %}
3708 interface(REG_INTER);
3709 %}
3710
3711 // Flags register, used as output of FLOATING POINT compare instructions
3712 operand rFlagsRegU()
3713 %{
3714 constraint(ALLOC_IN_RC(int_flags));
3715 match(RegFlags);
3716
3717 format %{ "RFLAGS_U" %}
3718 interface(REG_INTER);
3719 %}
3720
3721 operand rFlagsRegUCF() %{
3722 constraint(ALLOC_IN_RC(int_flags));
3723 match(RegFlags);
3724 predicate(false);
3725
3726 format %{ "RFLAGS_U_CF" %}
3727 interface(REG_INTER);
3728 %}
3729
3730 // Float register operands
3731 operand regF() %{
3732 constraint(ALLOC_IN_RC(float_reg));
3733 match(RegF);
3734
3735 format %{ %}
3736 interface(REG_INTER);
3737 %}
3738
3739 // Float register operands
3740 operand legRegF() %{
3741 constraint(ALLOC_IN_RC(float_reg_legacy));
3742 match(RegF);
3743
3744 format %{ %}
3745 interface(REG_INTER);
3746 %}
3747
3748 // Float register operands
3749 operand vlRegF() %{
3750 constraint(ALLOC_IN_RC(float_reg_vl));
3751 match(RegF);
3752
3753 format %{ %}
3754 interface(REG_INTER);
3755 %}
3756
3757 // Double register operands
3758 operand regD() %{
3759 constraint(ALLOC_IN_RC(double_reg));
3760 match(RegD);
3761
3762 format %{ %}
3763 interface(REG_INTER);
3764 %}
3765
3766 // Double register operands
3767 operand legRegD() %{
3768 constraint(ALLOC_IN_RC(double_reg_legacy));
3769 match(RegD);
3770
3771 format %{ %}
3772 interface(REG_INTER);
3773 %}
3774
3775 // Double register operands
3776 operand vlRegD() %{
3777 constraint(ALLOC_IN_RC(double_reg_vl));
3778 match(RegD);
3779
3780 format %{ %}
3781 interface(REG_INTER);
3782 %}
3783
3784 //----------Memory Operands----------------------------------------------------
3785 // Direct Memory Operand
3786 // operand direct(immP addr)
3787 // %{
3788 // match(addr);
3789
3790 // format %{ "[$addr]" %}
3791 // interface(MEMORY_INTER) %{
3792 // base(0xFFFFFFFF);
3793 // index(0x4);
3794 // scale(0x0);
3795 // disp($addr);
3796 // %}
3797 // %}
3798
3799 // Indirect Memory Operand
3800 operand indirect(any_RegP reg)
3801 %{
3802 constraint(ALLOC_IN_RC(ptr_reg));
3803 match(reg);
3804
3805 format %{ "[$reg]" %}
3806 interface(MEMORY_INTER) %{
3807 base($reg);
3808 index(0x4);
3809 scale(0x0);
3810 disp(0x0);
3811 %}
3812 %}
3813
3814 // Indirect Memory Plus Short Offset Operand
3815 operand indOffset8(any_RegP reg, immL8 off)
3816 %{
3817 constraint(ALLOC_IN_RC(ptr_reg));
3818 match(AddP reg off);
3819
3820 format %{ "[$reg + $off (8-bit)]" %}
3821 interface(MEMORY_INTER) %{
3822 base($reg);
3823 index(0x4);
3824 scale(0x0);
3825 disp($off);
3826 %}
3827 %}
3828
3829 // Indirect Memory Plus Long Offset Operand
3830 operand indOffset32(any_RegP reg, immL32 off)
3831 %{
3832 constraint(ALLOC_IN_RC(ptr_reg));
3833 match(AddP reg off);
3834
3835 format %{ "[$reg + $off (32-bit)]" %}
3836 interface(MEMORY_INTER) %{
3837 base($reg);
3838 index(0x4);
3839 scale(0x0);
3840 disp($off);
3841 %}
3842 %}
3843
3844 // Indirect Memory Plus Index Register Plus Offset Operand
3845 operand indIndexOffset(any_RegP reg, rRegL lreg, immL32 off)
3846 %{
3847 constraint(ALLOC_IN_RC(ptr_reg));
3848 match(AddP (AddP reg lreg) off);
3849
3850 op_cost(10);
3851 format %{"[$reg + $off + $lreg]" %}
3852 interface(MEMORY_INTER) %{
3853 base($reg);
3854 index($lreg);
3855 scale(0x0);
3856 disp($off);
3857 %}
3858 %}
3859
3860 // Indirect Memory Plus Index Register Plus Offset Operand
3861 operand indIndex(any_RegP reg, rRegL lreg)
3862 %{
3863 constraint(ALLOC_IN_RC(ptr_reg));
3864 match(AddP reg lreg);
3865
3866 op_cost(10);
3867 format %{"[$reg + $lreg]" %}
3868 interface(MEMORY_INTER) %{
3869 base($reg);
3870 index($lreg);
3871 scale(0x0);
3872 disp(0x0);
3873 %}
3874 %}
3875
3876 // Indirect Memory Times Scale Plus Index Register
3877 operand indIndexScale(any_RegP reg, rRegL lreg, immI2 scale)
3878 %{
3879 constraint(ALLOC_IN_RC(ptr_reg));
3880 match(AddP reg (LShiftL lreg scale));
3881
3882 op_cost(10);
3883 format %{"[$reg + $lreg << $scale]" %}
3884 interface(MEMORY_INTER) %{
3885 base($reg);
3886 index($lreg);
3887 scale($scale);
3888 disp(0x0);
3889 %}
3890 %}
3891
3892 operand indPosIndexScale(any_RegP reg, rRegI idx, immI2 scale)
3893 %{
3894 constraint(ALLOC_IN_RC(ptr_reg));
3895 predicate(n->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
3896 match(AddP reg (LShiftL (ConvI2L idx) scale));
3897
3898 op_cost(10);
3899 format %{"[$reg + pos $idx << $scale]" %}
3900 interface(MEMORY_INTER) %{
3901 base($reg);
3902 index($idx);
3903 scale($scale);
3904 disp(0x0);
3905 %}
3906 %}
3907
3908 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
3909 operand indIndexScaleOffset(any_RegP reg, immL32 off, rRegL lreg, immI2 scale)
3910 %{
3911 constraint(ALLOC_IN_RC(ptr_reg));
3912 match(AddP (AddP reg (LShiftL lreg scale)) off);
3913
3914 op_cost(10);
3915 format %{"[$reg + $off + $lreg << $scale]" %}
3916 interface(MEMORY_INTER) %{
3917 base($reg);
3918 index($lreg);
3919 scale($scale);
3920 disp($off);
3921 %}
3922 %}
3923
3924 // Indirect Memory Plus Positive Index Register Plus Offset Operand
3925 operand indPosIndexOffset(any_RegP reg, immL32 off, rRegI idx)
3926 %{
3927 constraint(ALLOC_IN_RC(ptr_reg));
3928 predicate(n->in(2)->in(3)->as_Type()->type()->is_long()->_lo >= 0);
3929 match(AddP (AddP reg (ConvI2L idx)) off);
3930
3931 op_cost(10);
3932 format %{"[$reg + $off + $idx]" %}
3933 interface(MEMORY_INTER) %{
3934 base($reg);
3935 index($idx);
3936 scale(0x0);
3937 disp($off);
3938 %}
3939 %}
3940
3941 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand
3942 operand indPosIndexScaleOffset(any_RegP reg, immL32 off, rRegI idx, immI2 scale)
3943 %{
3944 constraint(ALLOC_IN_RC(ptr_reg));
3945 predicate(n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
3946 match(AddP (AddP reg (LShiftL (ConvI2L idx) scale)) off);
3947
3948 op_cost(10);
3949 format %{"[$reg + $off + $idx << $scale]" %}
3950 interface(MEMORY_INTER) %{
3951 base($reg);
3952 index($idx);
3953 scale($scale);
3954 disp($off);
3955 %}
3956 %}
3957
3958 // Indirect Narrow Oop Plus Offset Operand
3959 // Note: x86 architecture doesn't support "scale * index + offset" without a base
3960 // we can't free r12 even with CompressedOops::base() == NULL.
3961 operand indCompressedOopOffset(rRegN reg, immL32 off) %{
3962 predicate(UseCompressedOops && (CompressedOops::shift() == Address::times_8));
3963 constraint(ALLOC_IN_RC(ptr_reg));
3964 match(AddP (DecodeN reg) off);
3965
3966 op_cost(10);
3967 format %{"[R12 + $reg << 3 + $off] (compressed oop addressing)" %}
3968 interface(MEMORY_INTER) %{
3969 base(0xc); // R12
3970 index($reg);
3971 scale(0x3);
3972 disp($off);
3973 %}
3974 %}
3975
3976 // Indirect Memory Operand
3977 operand indirectNarrow(rRegN reg)
3978 %{
3979 predicate(CompressedOops::shift() == 0);
3980 constraint(ALLOC_IN_RC(ptr_reg));
3981 match(DecodeN reg);
3982
3983 format %{ "[$reg]" %}
3984 interface(MEMORY_INTER) %{
3985 base($reg);
3986 index(0x4);
3987 scale(0x0);
3988 disp(0x0);
3989 %}
3990 %}
3991
3992 // Indirect Memory Plus Short Offset Operand
3993 operand indOffset8Narrow(rRegN reg, immL8 off)
3994 %{
3995 predicate(CompressedOops::shift() == 0);
3996 constraint(ALLOC_IN_RC(ptr_reg));
3997 match(AddP (DecodeN reg) off);
3998
3999 format %{ "[$reg + $off (8-bit)]" %}
4000 interface(MEMORY_INTER) %{
4001 base($reg);
4002 index(0x4);
4003 scale(0x0);
4004 disp($off);
4005 %}
4006 %}
4007
4008 // Indirect Memory Plus Long Offset Operand
4009 operand indOffset32Narrow(rRegN reg, immL32 off)
4010 %{
4011 predicate(CompressedOops::shift() == 0);
4012 constraint(ALLOC_IN_RC(ptr_reg));
4013 match(AddP (DecodeN reg) off);
4014
4015 format %{ "[$reg + $off (32-bit)]" %}
4016 interface(MEMORY_INTER) %{
4017 base($reg);
4018 index(0x4);
4019 scale(0x0);
4020 disp($off);
4021 %}
4022 %}
4023
4024 // Indirect Memory Plus Index Register Plus Offset Operand
4025 operand indIndexOffsetNarrow(rRegN reg, rRegL lreg, immL32 off)
4026 %{
4027 predicate(CompressedOops::shift() == 0);
4028 constraint(ALLOC_IN_RC(ptr_reg));
4029 match(AddP (AddP (DecodeN reg) lreg) off);
4030
4031 op_cost(10);
4032 format %{"[$reg + $off + $lreg]" %}
4033 interface(MEMORY_INTER) %{
4034 base($reg);
4035 index($lreg);
4036 scale(0x0);
4037 disp($off);
4038 %}
4039 %}
4040
4041 // Indirect Memory Plus Index Register Plus Offset Operand
4042 operand indIndexNarrow(rRegN reg, rRegL lreg)
4043 %{
4044 predicate(CompressedOops::shift() == 0);
4045 constraint(ALLOC_IN_RC(ptr_reg));
4046 match(AddP (DecodeN reg) lreg);
4047
4048 op_cost(10);
4049 format %{"[$reg + $lreg]" %}
4050 interface(MEMORY_INTER) %{
4051 base($reg);
4052 index($lreg);
4053 scale(0x0);
4054 disp(0x0);
4055 %}
4056 %}
4057
4058 // Indirect Memory Times Scale Plus Index Register
4059 operand indIndexScaleNarrow(rRegN reg, rRegL lreg, immI2 scale)
4060 %{
4061 predicate(CompressedOops::shift() == 0);
4062 constraint(ALLOC_IN_RC(ptr_reg));
4063 match(AddP (DecodeN reg) (LShiftL lreg scale));
4064
4065 op_cost(10);
4066 format %{"[$reg + $lreg << $scale]" %}
4067 interface(MEMORY_INTER) %{
4068 base($reg);
4069 index($lreg);
4070 scale($scale);
4071 disp(0x0);
4072 %}
4073 %}
4074
4075 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
4076 operand indIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegL lreg, immI2 scale)
4077 %{
4078 predicate(CompressedOops::shift() == 0);
4079 constraint(ALLOC_IN_RC(ptr_reg));
4080 match(AddP (AddP (DecodeN reg) (LShiftL lreg scale)) off);
4081
4082 op_cost(10);
4083 format %{"[$reg + $off + $lreg << $scale]" %}
4084 interface(MEMORY_INTER) %{
4085 base($reg);
4086 index($lreg);
4087 scale($scale);
4088 disp($off);
4089 %}
4090 %}
4091
4092 // Indirect Memory Times Plus Positive Index Register Plus Offset Operand
4093 operand indPosIndexOffsetNarrow(rRegN reg, immL32 off, rRegI idx)
4094 %{
4095 constraint(ALLOC_IN_RC(ptr_reg));
4096 predicate(CompressedOops::shift() == 0 && n->in(2)->in(3)->as_Type()->type()->is_long()->_lo >= 0);
4097 match(AddP (AddP (DecodeN reg) (ConvI2L idx)) off);
4098
4099 op_cost(10);
4100 format %{"[$reg + $off + $idx]" %}
4101 interface(MEMORY_INTER) %{
4102 base($reg);
4103 index($idx);
4104 scale(0x0);
4105 disp($off);
4106 %}
4107 %}
4108
4109 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand
4110 operand indPosIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegI idx, immI2 scale)
4111 %{
4112 constraint(ALLOC_IN_RC(ptr_reg));
4113 predicate(CompressedOops::shift() == 0 && n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
4114 match(AddP (AddP (DecodeN reg) (LShiftL (ConvI2L idx) scale)) off);
4115
4116 op_cost(10);
4117 format %{"[$reg + $off + $idx << $scale]" %}
4118 interface(MEMORY_INTER) %{
4119 base($reg);
4120 index($idx);
4121 scale($scale);
4122 disp($off);
4123 %}
4124 %}
4125
4126 //----------Special Memory Operands--------------------------------------------
4127 // Stack Slot Operand - This operand is used for loading and storing temporary
4128 // values on the stack where a match requires a value to
4129 // flow through memory.
4130 operand stackSlotP(sRegP reg)
4131 %{
4132 constraint(ALLOC_IN_RC(stack_slots));
4133 // No match rule because this operand is only generated in matching
4134
4135 format %{ "[$reg]" %}
4136 interface(MEMORY_INTER) %{
4137 base(0x4); // RSP
4138 index(0x4); // No Index
4139 scale(0x0); // No Scale
4140 disp($reg); // Stack Offset
4141 %}
4142 %}
4143
4144 operand stackSlotI(sRegI reg)
4145 %{
4146 constraint(ALLOC_IN_RC(stack_slots));
4147 // No match rule because this operand is only generated in matching
4148
4149 format %{ "[$reg]" %}
4150 interface(MEMORY_INTER) %{
4151 base(0x4); // RSP
4152 index(0x4); // No Index
4153 scale(0x0); // No Scale
4154 disp($reg); // Stack Offset
4155 %}
4156 %}
4157
4158 operand stackSlotF(sRegF reg)
4159 %{
4160 constraint(ALLOC_IN_RC(stack_slots));
4161 // No match rule because this operand is only generated in matching
4162
4163 format %{ "[$reg]" %}
4164 interface(MEMORY_INTER) %{
4165 base(0x4); // RSP
4166 index(0x4); // No Index
4167 scale(0x0); // No Scale
4168 disp($reg); // Stack Offset
4169 %}
4170 %}
4171
4172 operand stackSlotD(sRegD reg)
4173 %{
4174 constraint(ALLOC_IN_RC(stack_slots));
4175 // No match rule because this operand is only generated in matching
4176
4177 format %{ "[$reg]" %}
4178 interface(MEMORY_INTER) %{
4179 base(0x4); // RSP
4180 index(0x4); // No Index
4181 scale(0x0); // No Scale
4182 disp($reg); // Stack Offset
4183 %}
4184 %}
4185 operand stackSlotL(sRegL reg)
4186 %{
4187 constraint(ALLOC_IN_RC(stack_slots));
4188 // No match rule because this operand is only generated in matching
4189
4190 format %{ "[$reg]" %}
4191 interface(MEMORY_INTER) %{
4192 base(0x4); // RSP
4193 index(0x4); // No Index
4194 scale(0x0); // No Scale
4195 disp($reg); // Stack Offset
4196 %}
4197 %}
4198
4199 //----------Conditional Branch Operands----------------------------------------
4200 // Comparison Op - This is the operation of the comparison, and is limited to
4201 // the following set of codes:
4202 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
4203 //
4204 // Other attributes of the comparison, such as unsignedness, are specified
4205 // by the comparison instruction that sets a condition code flags register.
4206 // That result is represented by a flags operand whose subtype is appropriate
4207 // to the unsignedness (etc.) of the comparison.
4208 //
4209 // Later, the instruction which matches both the Comparison Op (a Bool) and
4210 // the flags (produced by the Cmp) specifies the coding of the comparison op
4211 // by matching a specific subtype of Bool operand below, such as cmpOpU.
4212
4213 // Comparision Code
4214 operand cmpOp()
4215 %{
4216 match(Bool);
4217
4218 format %{ "" %}
4219 interface(COND_INTER) %{
4220 equal(0x4, "e");
4221 not_equal(0x5, "ne");
4222 less(0xC, "l");
4223 greater_equal(0xD, "ge");
4224 less_equal(0xE, "le");
4225 greater(0xF, "g");
4226 overflow(0x0, "o");
4227 no_overflow(0x1, "no");
4228 %}
4229 %}
4230
4231 // Comparison Code, unsigned compare. Used by FP also, with
4232 // C2 (unordered) turned into GT or LT already. The other bits
4233 // C0 and C3 are turned into Carry & Zero flags.
4234 operand cmpOpU()
4235 %{
4236 match(Bool);
4237
4238 format %{ "" %}
4239 interface(COND_INTER) %{
4240 equal(0x4, "e");
4241 not_equal(0x5, "ne");
4242 less(0x2, "b");
4243 greater_equal(0x3, "nb");
4244 less_equal(0x6, "be");
4245 greater(0x7, "nbe");
4246 overflow(0x0, "o");
4247 no_overflow(0x1, "no");
4248 %}
4249 %}
4250
4251
4252 // Floating comparisons that don't require any fixup for the unordered case
4253 operand cmpOpUCF() %{
4254 match(Bool);
4255 predicate(n->as_Bool()->_test._test == BoolTest::lt ||
4256 n->as_Bool()->_test._test == BoolTest::ge ||
4257 n->as_Bool()->_test._test == BoolTest::le ||
4258 n->as_Bool()->_test._test == BoolTest::gt);
4259 format %{ "" %}
4260 interface(COND_INTER) %{
4261 equal(0x4, "e");
4262 not_equal(0x5, "ne");
4263 less(0x2, "b");
4264 greater_equal(0x3, "nb");
4265 less_equal(0x6, "be");
4266 greater(0x7, "nbe");
4267 overflow(0x0, "o");
4268 no_overflow(0x1, "no");
4269 %}
4270 %}
4271
4272
4273 // Floating comparisons that can be fixed up with extra conditional jumps
4274 operand cmpOpUCF2() %{
4275 match(Bool);
4276 predicate(n->as_Bool()->_test._test == BoolTest::ne ||
4277 n->as_Bool()->_test._test == BoolTest::eq);
4278 format %{ "" %}
4279 interface(COND_INTER) %{
4280 equal(0x4, "e");
4281 not_equal(0x5, "ne");
4282 less(0x2, "b");
4283 greater_equal(0x3, "nb");
4284 less_equal(0x6, "be");
4285 greater(0x7, "nbe");
4286 overflow(0x0, "o");
4287 no_overflow(0x1, "no");
4288 %}
4289 %}
4290
4291 //----------OPERAND CLASSES----------------------------------------------------
4292 // Operand Classes are groups of operands that are used as to simplify
4293 // instruction definitions by not requiring the AD writer to specify separate
4294 // instructions for every form of operand when the instruction accepts
4295 // multiple operand types with the same basic encoding and format. The classic
4296 // case of this is memory operands.
4297
4298 opclass memory(indirect, indOffset8, indOffset32, indIndexOffset, indIndex,
4299 indIndexScale, indPosIndexScale, indIndexScaleOffset, indPosIndexOffset, indPosIndexScaleOffset,
4300 indCompressedOopOffset,
4301 indirectNarrow, indOffset8Narrow, indOffset32Narrow,
4302 indIndexOffsetNarrow, indIndexNarrow, indIndexScaleNarrow,
4303 indIndexScaleOffsetNarrow, indPosIndexOffsetNarrow, indPosIndexScaleOffsetNarrow);
4304
4305 //----------PIPELINE-----------------------------------------------------------
4306 // Rules which define the behavior of the target architectures pipeline.
4307 pipeline %{
4308
4309 //----------ATTRIBUTES---------------------------------------------------------
4310 attributes %{
4311 variable_size_instructions; // Fixed size instructions
4312 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle
4313 instruction_unit_size = 1; // An instruction is 1 bytes long
4314 instruction_fetch_unit_size = 16; // The processor fetches one line
4315 instruction_fetch_units = 1; // of 16 bytes
4316
4317 // List of nop instructions
4318 nops( MachNop );
4319 %}
4320
4321 //----------RESOURCES----------------------------------------------------------
4322 // Resources are the functional units available to the machine
4323
4324 // Generic P2/P3 pipeline
4325 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of
4326 // 3 instructions decoded per cycle.
4327 // 2 load/store ops per cycle, 1 branch, 1 FPU,
4328 // 3 ALU op, only ALU0 handles mul instructions.
4329 resources( D0, D1, D2, DECODE = D0 | D1 | D2,
4330 MS0, MS1, MS2, MEM = MS0 | MS1 | MS2,
4331 BR, FPU,
4332 ALU0, ALU1, ALU2, ALU = ALU0 | ALU1 | ALU2);
4333
4334 //----------PIPELINE DESCRIPTION-----------------------------------------------
4335 // Pipeline Description specifies the stages in the machine's pipeline
4336
4337 // Generic P2/P3 pipeline
4338 pipe_desc(S0, S1, S2, S3, S4, S5);
4339
4340 //----------PIPELINE CLASSES---------------------------------------------------
4341 // Pipeline Classes describe the stages in which input and output are
4342 // referenced by the hardware pipeline.
4343
4344 // Naming convention: ialu or fpu
4345 // Then: _reg
4346 // Then: _reg if there is a 2nd register
4347 // Then: _long if it's a pair of instructions implementing a long
4348 // Then: _fat if it requires the big decoder
4349 // Or: _mem if it requires the big decoder and a memory unit.
4350
4351 // Integer ALU reg operation
4352 pipe_class ialu_reg(rRegI dst)
4353 %{
4354 single_instruction;
4355 dst : S4(write);
4356 dst : S3(read);
4357 DECODE : S0; // any decoder
4358 ALU : S3; // any alu
4359 %}
4360
4361 // Long ALU reg operation
4362 pipe_class ialu_reg_long(rRegL dst)
4363 %{
4364 instruction_count(2);
4365 dst : S4(write);
4366 dst : S3(read);
4367 DECODE : S0(2); // any 2 decoders
4368 ALU : S3(2); // both alus
4369 %}
4370
4371 // Integer ALU reg operation using big decoder
4372 pipe_class ialu_reg_fat(rRegI dst)
4373 %{
4374 single_instruction;
4375 dst : S4(write);
4376 dst : S3(read);
4377 D0 : S0; // big decoder only
4378 ALU : S3; // any alu
4379 %}
4380
4381 // Integer ALU reg-reg operation
4382 pipe_class ialu_reg_reg(rRegI dst, rRegI src)
4383 %{
4384 single_instruction;
4385 dst : S4(write);
4386 src : S3(read);
4387 DECODE : S0; // any decoder
4388 ALU : S3; // any alu
4389 %}
4390
4391 // Integer ALU reg-reg operation
4392 pipe_class ialu_reg_reg_fat(rRegI dst, memory src)
4393 %{
4394 single_instruction;
4395 dst : S4(write);
4396 src : S3(read);
4397 D0 : S0; // big decoder only
4398 ALU : S3; // any alu
4399 %}
4400
4401 // Integer ALU reg-mem operation
4402 pipe_class ialu_reg_mem(rRegI dst, memory mem)
4403 %{
4404 single_instruction;
4405 dst : S5(write);
4406 mem : S3(read);
4407 D0 : S0; // big decoder only
4408 ALU : S4; // any alu
4409 MEM : S3; // any mem
4410 %}
4411
4412 // Integer mem operation (prefetch)
4413 pipe_class ialu_mem(memory mem)
4414 %{
4415 single_instruction;
4416 mem : S3(read);
4417 D0 : S0; // big decoder only
4418 MEM : S3; // any mem
4419 %}
4420
4421 // Integer Store to Memory
4422 pipe_class ialu_mem_reg(memory mem, rRegI src)
4423 %{
4424 single_instruction;
4425 mem : S3(read);
4426 src : S5(read);
4427 D0 : S0; // big decoder only
4428 ALU : S4; // any alu
4429 MEM : S3;
4430 %}
4431
4432 // // Long Store to Memory
4433 // pipe_class ialu_mem_long_reg(memory mem, rRegL src)
4434 // %{
4435 // instruction_count(2);
4436 // mem : S3(read);
4437 // src : S5(read);
4438 // D0 : S0(2); // big decoder only; twice
4439 // ALU : S4(2); // any 2 alus
4440 // MEM : S3(2); // Both mems
4441 // %}
4442
4443 // Integer Store to Memory
4444 pipe_class ialu_mem_imm(memory mem)
4445 %{
4446 single_instruction;
4447 mem : S3(read);
4448 D0 : S0; // big decoder only
4449 ALU : S4; // any alu
4450 MEM : S3;
4451 %}
4452
4453 // Integer ALU0 reg-reg operation
4454 pipe_class ialu_reg_reg_alu0(rRegI dst, rRegI src)
4455 %{
4456 single_instruction;
4457 dst : S4(write);
4458 src : S3(read);
4459 D0 : S0; // Big decoder only
4460 ALU0 : S3; // only alu0
4461 %}
4462
4463 // Integer ALU0 reg-mem operation
4464 pipe_class ialu_reg_mem_alu0(rRegI dst, memory mem)
4465 %{
4466 single_instruction;
4467 dst : S5(write);
4468 mem : S3(read);
4469 D0 : S0; // big decoder only
4470 ALU0 : S4; // ALU0 only
4471 MEM : S3; // any mem
4472 %}
4473
4474 // Integer ALU reg-reg operation
4475 pipe_class ialu_cr_reg_reg(rFlagsReg cr, rRegI src1, rRegI src2)
4476 %{
4477 single_instruction;
4478 cr : S4(write);
4479 src1 : S3(read);
4480 src2 : S3(read);
4481 DECODE : S0; // any decoder
4482 ALU : S3; // any alu
4483 %}
4484
4485 // Integer ALU reg-imm operation
4486 pipe_class ialu_cr_reg_imm(rFlagsReg cr, rRegI src1)
4487 %{
4488 single_instruction;
4489 cr : S4(write);
4490 src1 : S3(read);
4491 DECODE : S0; // any decoder
4492 ALU : S3; // any alu
4493 %}
4494
4495 // Integer ALU reg-mem operation
4496 pipe_class ialu_cr_reg_mem(rFlagsReg cr, rRegI src1, memory src2)
4497 %{
4498 single_instruction;
4499 cr : S4(write);
4500 src1 : S3(read);
4501 src2 : S3(read);
4502 D0 : S0; // big decoder only
4503 ALU : S4; // any alu
4504 MEM : S3;
4505 %}
4506
4507 // Conditional move reg-reg
4508 pipe_class pipe_cmplt( rRegI p, rRegI q, rRegI y)
4509 %{
4510 instruction_count(4);
4511 y : S4(read);
4512 q : S3(read);
4513 p : S3(read);
4514 DECODE : S0(4); // any decoder
4515 %}
4516
4517 // Conditional move reg-reg
4518 pipe_class pipe_cmov_reg( rRegI dst, rRegI src, rFlagsReg cr)
4519 %{
4520 single_instruction;
4521 dst : S4(write);
4522 src : S3(read);
4523 cr : S3(read);
4524 DECODE : S0; // any decoder
4525 %}
4526
4527 // Conditional move reg-mem
4528 pipe_class pipe_cmov_mem( rFlagsReg cr, rRegI dst, memory src)
4529 %{
4530 single_instruction;
4531 dst : S4(write);
4532 src : S3(read);
4533 cr : S3(read);
4534 DECODE : S0; // any decoder
4535 MEM : S3;
4536 %}
4537
4538 // Conditional move reg-reg long
4539 pipe_class pipe_cmov_reg_long( rFlagsReg cr, rRegL dst, rRegL src)
4540 %{
4541 single_instruction;
4542 dst : S4(write);
4543 src : S3(read);
4544 cr : S3(read);
4545 DECODE : S0(2); // any 2 decoders
4546 %}
4547
4548 // XXX
4549 // // Conditional move double reg-reg
4550 // pipe_class pipe_cmovD_reg( rFlagsReg cr, regDPR1 dst, regD src)
4551 // %{
4552 // single_instruction;
4553 // dst : S4(write);
4554 // src : S3(read);
4555 // cr : S3(read);
4556 // DECODE : S0; // any decoder
4557 // %}
4558
4559 // Float reg-reg operation
4560 pipe_class fpu_reg(regD dst)
4561 %{
4562 instruction_count(2);
4563 dst : S3(read);
4564 DECODE : S0(2); // any 2 decoders
4565 FPU : S3;
4566 %}
4567
4568 // Float reg-reg operation
4569 pipe_class fpu_reg_reg(regD dst, regD src)
4570 %{
4571 instruction_count(2);
4572 dst : S4(write);
4573 src : S3(read);
4574 DECODE : S0(2); // any 2 decoders
4575 FPU : S3;
4576 %}
4577
4578 // Float reg-reg operation
4579 pipe_class fpu_reg_reg_reg(regD dst, regD src1, regD src2)
4580 %{
4581 instruction_count(3);
4582 dst : S4(write);
4583 src1 : S3(read);
4584 src2 : S3(read);
4585 DECODE : S0(3); // any 3 decoders
4586 FPU : S3(2);
4587 %}
4588
4589 // Float reg-reg operation
4590 pipe_class fpu_reg_reg_reg_reg(regD dst, regD src1, regD src2, regD src3)
4591 %{
4592 instruction_count(4);
4593 dst : S4(write);
4594 src1 : S3(read);
4595 src2 : S3(read);
4596 src3 : S3(read);
4597 DECODE : S0(4); // any 3 decoders
4598 FPU : S3(2);
4599 %}
4600
4601 // Float reg-reg operation
4602 pipe_class fpu_reg_mem_reg_reg(regD dst, memory src1, regD src2, regD src3)
4603 %{
4604 instruction_count(4);
4605 dst : S4(write);
4606 src1 : S3(read);
4607 src2 : S3(read);
4608 src3 : S3(read);
4609 DECODE : S1(3); // any 3 decoders
4610 D0 : S0; // Big decoder only
4611 FPU : S3(2);
4612 MEM : S3;
4613 %}
4614
4615 // Float reg-mem operation
4616 pipe_class fpu_reg_mem(regD dst, memory mem)
4617 %{
4618 instruction_count(2);
4619 dst : S5(write);
4620 mem : S3(read);
4621 D0 : S0; // big decoder only
4622 DECODE : S1; // any decoder for FPU POP
4623 FPU : S4;
4624 MEM : S3; // any mem
4625 %}
4626
4627 // Float reg-mem operation
4628 pipe_class fpu_reg_reg_mem(regD dst, regD src1, memory mem)
4629 %{
4630 instruction_count(3);
4631 dst : S5(write);
4632 src1 : S3(read);
4633 mem : S3(read);
4634 D0 : S0; // big decoder only
4635 DECODE : S1(2); // any decoder for FPU POP
4636 FPU : S4;
4637 MEM : S3; // any mem
4638 %}
4639
4640 // Float mem-reg operation
4641 pipe_class fpu_mem_reg(memory mem, regD src)
4642 %{
4643 instruction_count(2);
4644 src : S5(read);
4645 mem : S3(read);
4646 DECODE : S0; // any decoder for FPU PUSH
4647 D0 : S1; // big decoder only
4648 FPU : S4;
4649 MEM : S3; // any mem
4650 %}
4651
4652 pipe_class fpu_mem_reg_reg(memory mem, regD src1, regD src2)
4653 %{
4654 instruction_count(3);
4655 src1 : S3(read);
4656 src2 : S3(read);
4657 mem : S3(read);
4658 DECODE : S0(2); // any decoder for FPU PUSH
4659 D0 : S1; // big decoder only
4660 FPU : S4;
4661 MEM : S3; // any mem
4662 %}
4663
4664 pipe_class fpu_mem_reg_mem(memory mem, regD src1, memory src2)
4665 %{
4666 instruction_count(3);
4667 src1 : S3(read);
4668 src2 : S3(read);
4669 mem : S4(read);
4670 DECODE : S0; // any decoder for FPU PUSH
4671 D0 : S0(2); // big decoder only
4672 FPU : S4;
4673 MEM : S3(2); // any mem
4674 %}
4675
4676 pipe_class fpu_mem_mem(memory dst, memory src1)
4677 %{
4678 instruction_count(2);
4679 src1 : S3(read);
4680 dst : S4(read);
4681 D0 : S0(2); // big decoder only
4682 MEM : S3(2); // any mem
4683 %}
4684
4685 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2)
4686 %{
4687 instruction_count(3);
4688 src1 : S3(read);
4689 src2 : S3(read);
4690 dst : S4(read);
4691 D0 : S0(3); // big decoder only
4692 FPU : S4;
4693 MEM : S3(3); // any mem
4694 %}
4695
4696 pipe_class fpu_mem_reg_con(memory mem, regD src1)
4697 %{
4698 instruction_count(3);
4699 src1 : S4(read);
4700 mem : S4(read);
4701 DECODE : S0; // any decoder for FPU PUSH
4702 D0 : S0(2); // big decoder only
4703 FPU : S4;
4704 MEM : S3(2); // any mem
4705 %}
4706
4707 // Float load constant
4708 pipe_class fpu_reg_con(regD dst)
4709 %{
4710 instruction_count(2);
4711 dst : S5(write);
4712 D0 : S0; // big decoder only for the load
4713 DECODE : S1; // any decoder for FPU POP
4714 FPU : S4;
4715 MEM : S3; // any mem
4716 %}
4717
4718 // Float load constant
4719 pipe_class fpu_reg_reg_con(regD dst, regD src)
4720 %{
4721 instruction_count(3);
4722 dst : S5(write);
4723 src : S3(read);
4724 D0 : S0; // big decoder only for the load
4725 DECODE : S1(2); // any decoder for FPU POP
4726 FPU : S4;
4727 MEM : S3; // any mem
4728 %}
4729
4730 // UnConditional branch
4731 pipe_class pipe_jmp(label labl)
4732 %{
4733 single_instruction;
4734 BR : S3;
4735 %}
4736
4737 // Conditional branch
4738 pipe_class pipe_jcc(cmpOp cmp, rFlagsReg cr, label labl)
4739 %{
4740 single_instruction;
4741 cr : S1(read);
4742 BR : S3;
4743 %}
4744
4745 // Allocation idiom
4746 pipe_class pipe_cmpxchg(rRegP dst, rRegP heap_ptr)
4747 %{
4748 instruction_count(1); force_serialization;
4749 fixed_latency(6);
4750 heap_ptr : S3(read);
4751 DECODE : S0(3);
4752 D0 : S2;
4753 MEM : S3;
4754 ALU : S3(2);
4755 dst : S5(write);
4756 BR : S5;
4757 %}
4758
4759 // Generic big/slow expanded idiom
4760 pipe_class pipe_slow()
4761 %{
4762 instruction_count(10); multiple_bundles; force_serialization;
4763 fixed_latency(100);
4764 D0 : S0(2);
4765 MEM : S3(2);
4766 %}
4767
4768 // The real do-nothing guy
4769 pipe_class empty()
4770 %{
4771 instruction_count(0);
4772 %}
4773
4774 // Define the class for the Nop node
4775 define
4776 %{
4777 MachNop = empty;
4778 %}
4779
4780 %}
4781
4782 //----------INSTRUCTIONS-------------------------------------------------------
4783 //
4784 // match -- States which machine-independent subtree may be replaced
4785 // by this instruction.
4786 // ins_cost -- The estimated cost of this instruction is used by instruction
4787 // selection to identify a minimum cost tree of machine
4788 // instructions that matches a tree of machine-independent
4789 // instructions.
4790 // format -- A string providing the disassembly for this instruction.
4791 // The value of an instruction's operand may be inserted
4792 // by referring to it with a '$' prefix.
4793 // opcode -- Three instruction opcodes may be provided. These are referred
4794 // to within an encode class as $primary, $secondary, and $tertiary
4795 // rrspectively. The primary opcode is commonly used to
4796 // indicate the type of machine instruction, while secondary
4797 // and tertiary are often used for prefix options or addressing
4798 // modes.
4799 // ins_encode -- A list of encode classes with parameters. The encode class
4800 // name must have been defined in an 'enc_class' specification
4801 // in the encode section of the architecture description.
4802
4803 //----------Load/Store/Move Instructions---------------------------------------
4804 //----------Load Instructions--------------------------------------------------
4805
4806 // Load Byte (8 bit signed)
4807 instruct loadB(rRegI dst, memory mem)
4808 %{
4809 match(Set dst (LoadB mem));
4810
4811 ins_cost(125);
4812 format %{ "movsbl $dst, $mem\t# byte" %}
4813
4814 ins_encode %{
4815 __ movsbl($dst$$Register, $mem$$Address);
4816 %}
4817
4818 ins_pipe(ialu_reg_mem);
4819 %}
4820
4821 // Load Byte (8 bit signed) into Long Register
4822 instruct loadB2L(rRegL dst, memory mem)
4823 %{
4824 match(Set dst (ConvI2L (LoadB mem)));
4825
4826 ins_cost(125);
4827 format %{ "movsbq $dst, $mem\t# byte -> long" %}
4828
4829 ins_encode %{
4830 __ movsbq($dst$$Register, $mem$$Address);
4831 %}
4832
4833 ins_pipe(ialu_reg_mem);
4834 %}
4835
4836 // Load Unsigned Byte (8 bit UNsigned)
4837 instruct loadUB(rRegI dst, memory mem)
4838 %{
4839 match(Set dst (LoadUB mem));
4840
4841 ins_cost(125);
4842 format %{ "movzbl $dst, $mem\t# ubyte" %}
4843
4844 ins_encode %{
4845 __ movzbl($dst$$Register, $mem$$Address);
4846 %}
4847
4848 ins_pipe(ialu_reg_mem);
4849 %}
4850
4851 // Load Unsigned Byte (8 bit UNsigned) into Long Register
4852 instruct loadUB2L(rRegL dst, memory mem)
4853 %{
4854 match(Set dst (ConvI2L (LoadUB mem)));
4855
4856 ins_cost(125);
4857 format %{ "movzbq $dst, $mem\t# ubyte -> long" %}
4858
4859 ins_encode %{
4860 __ movzbq($dst$$Register, $mem$$Address);
4861 %}
4862
4863 ins_pipe(ialu_reg_mem);
4864 %}
4865
4866 // Load Unsigned Byte (8 bit UNsigned) with 32-bit mask into Long Register
4867 instruct loadUB2L_immI(rRegL dst, memory mem, immI mask, rFlagsReg cr) %{
4868 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
4869 effect(KILL cr);
4870
4871 format %{ "movzbq $dst, $mem\t# ubyte & 32-bit mask -> long\n\t"
4872 "andl $dst, right_n_bits($mask, 8)" %}
4873 ins_encode %{
4874 Register Rdst = $dst$$Register;
4875 __ movzbq(Rdst, $mem$$Address);
4876 __ andl(Rdst, $mask$$constant & right_n_bits(8));
4877 %}
4878 ins_pipe(ialu_reg_mem);
4879 %}
4880
4881 // Load Short (16 bit signed)
4882 instruct loadS(rRegI dst, memory mem)
4883 %{
4884 match(Set dst (LoadS mem));
4885
4886 ins_cost(125);
4887 format %{ "movswl $dst, $mem\t# short" %}
4888
4889 ins_encode %{
4890 __ movswl($dst$$Register, $mem$$Address);
4891 %}
4892
4893 ins_pipe(ialu_reg_mem);
4894 %}
4895
4896 // Load Short (16 bit signed) to Byte (8 bit signed)
4897 instruct loadS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
4898 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
4899
4900 ins_cost(125);
4901 format %{ "movsbl $dst, $mem\t# short -> byte" %}
4902 ins_encode %{
4903 __ movsbl($dst$$Register, $mem$$Address);
4904 %}
4905 ins_pipe(ialu_reg_mem);
4906 %}
4907
4908 // Load Short (16 bit signed) into Long Register
4909 instruct loadS2L(rRegL dst, memory mem)
4910 %{
4911 match(Set dst (ConvI2L (LoadS mem)));
4912
4913 ins_cost(125);
4914 format %{ "movswq $dst, $mem\t# short -> long" %}
4915
4916 ins_encode %{
4917 __ movswq($dst$$Register, $mem$$Address);
4918 %}
4919
4920 ins_pipe(ialu_reg_mem);
4921 %}
4922
4923 // Load Unsigned Short/Char (16 bit UNsigned)
4924 instruct loadUS(rRegI dst, memory mem)
4925 %{
4926 match(Set dst (LoadUS mem));
4927
4928 ins_cost(125);
4929 format %{ "movzwl $dst, $mem\t# ushort/char" %}
4930
4931 ins_encode %{
4932 __ movzwl($dst$$Register, $mem$$Address);
4933 %}
4934
4935 ins_pipe(ialu_reg_mem);
4936 %}
4937
4938 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
4939 instruct loadUS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
4940 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
4941
4942 ins_cost(125);
4943 format %{ "movsbl $dst, $mem\t# ushort -> byte" %}
4944 ins_encode %{
4945 __ movsbl($dst$$Register, $mem$$Address);
4946 %}
4947 ins_pipe(ialu_reg_mem);
4948 %}
4949
4950 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register
4951 instruct loadUS2L(rRegL dst, memory mem)
4952 %{
4953 match(Set dst (ConvI2L (LoadUS mem)));
4954
4955 ins_cost(125);
4956 format %{ "movzwq $dst, $mem\t# ushort/char -> long" %}
4957
4958 ins_encode %{
4959 __ movzwq($dst$$Register, $mem$$Address);
4960 %}
4961
4962 ins_pipe(ialu_reg_mem);
4963 %}
4964
4965 // Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register
4966 instruct loadUS2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{
4967 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
4968
4969 format %{ "movzbq $dst, $mem\t# ushort/char & 0xFF -> long" %}
4970 ins_encode %{
4971 __ movzbq($dst$$Register, $mem$$Address);
4972 %}
4973 ins_pipe(ialu_reg_mem);
4974 %}
4975
4976 // Load Unsigned Short/Char (16 bit UNsigned) with 32-bit mask into Long Register
4977 instruct loadUS2L_immI(rRegL dst, memory mem, immI mask, rFlagsReg cr) %{
4978 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
4979 effect(KILL cr);
4980
4981 format %{ "movzwq $dst, $mem\t# ushort/char & 32-bit mask -> long\n\t"
4982 "andl $dst, right_n_bits($mask, 16)" %}
4983 ins_encode %{
4984 Register Rdst = $dst$$Register;
4985 __ movzwq(Rdst, $mem$$Address);
4986 __ andl(Rdst, $mask$$constant & right_n_bits(16));
4987 %}
4988 ins_pipe(ialu_reg_mem);
4989 %}
4990
4991 // Load Integer
4992 instruct loadI(rRegI dst, memory mem)
4993 %{
4994 match(Set dst (LoadI mem));
4995
4996 ins_cost(125);
4997 format %{ "movl $dst, $mem\t# int" %}
4998
4999 ins_encode %{
5000 __ movl($dst$$Register, $mem$$Address);
5001 %}
5002
5003 ins_pipe(ialu_reg_mem);
5004 %}
5005
5006 // Load Integer (32 bit signed) to Byte (8 bit signed)
5007 instruct loadI2B(rRegI dst, memory mem, immI_24 twentyfour) %{
5008 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
5009
5010 ins_cost(125);
5011 format %{ "movsbl $dst, $mem\t# int -> byte" %}
5012 ins_encode %{
5013 __ movsbl($dst$$Register, $mem$$Address);
5014 %}
5015 ins_pipe(ialu_reg_mem);
5016 %}
5017
5018 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned)
5019 instruct loadI2UB(rRegI dst, memory mem, immI_255 mask) %{
5020 match(Set dst (AndI (LoadI mem) mask));
5021
5022 ins_cost(125);
5023 format %{ "movzbl $dst, $mem\t# int -> ubyte" %}
5024 ins_encode %{
5025 __ movzbl($dst$$Register, $mem$$Address);
5026 %}
5027 ins_pipe(ialu_reg_mem);
5028 %}
5029
5030 // Load Integer (32 bit signed) to Short (16 bit signed)
5031 instruct loadI2S(rRegI dst, memory mem, immI_16 sixteen) %{
5032 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
5033
5034 ins_cost(125);
5035 format %{ "movswl $dst, $mem\t# int -> short" %}
5036 ins_encode %{
5037 __ movswl($dst$$Register, $mem$$Address);
5038 %}
5039 ins_pipe(ialu_reg_mem);
5040 %}
5041
5042 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned)
5043 instruct loadI2US(rRegI dst, memory mem, immI_65535 mask) %{
5044 match(Set dst (AndI (LoadI mem) mask));
5045
5046 ins_cost(125);
5047 format %{ "movzwl $dst, $mem\t# int -> ushort/char" %}
5048 ins_encode %{
5049 __ movzwl($dst$$Register, $mem$$Address);
5050 %}
5051 ins_pipe(ialu_reg_mem);
5052 %}
5053
5054 // Load Integer into Long Register
5055 instruct loadI2L(rRegL dst, memory mem)
5056 %{
5057 match(Set dst (ConvI2L (LoadI mem)));
5058
5059 ins_cost(125);
5060 format %{ "movslq $dst, $mem\t# int -> long" %}
5061
5062 ins_encode %{
5063 __ movslq($dst$$Register, $mem$$Address);
5064 %}
5065
5066 ins_pipe(ialu_reg_mem);
5067 %}
5068
5069 // Load Integer with mask 0xFF into Long Register
5070 instruct loadI2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{
5071 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5072
5073 format %{ "movzbq $dst, $mem\t# int & 0xFF -> long" %}
5074 ins_encode %{
5075 __ movzbq($dst$$Register, $mem$$Address);
5076 %}
5077 ins_pipe(ialu_reg_mem);
5078 %}
5079
5080 // Load Integer with mask 0xFFFF into Long Register
5081 instruct loadI2L_immI_65535(rRegL dst, memory mem, immI_65535 mask) %{
5082 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5083
5084 format %{ "movzwq $dst, $mem\t# int & 0xFFFF -> long" %}
5085 ins_encode %{
5086 __ movzwq($dst$$Register, $mem$$Address);
5087 %}
5088 ins_pipe(ialu_reg_mem);
5089 %}
5090
5091 // Load Integer with a 31-bit mask into Long Register
5092 instruct loadI2L_immU31(rRegL dst, memory mem, immU31 mask, rFlagsReg cr) %{
5093 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5094 effect(KILL cr);
5095
5096 format %{ "movl $dst, $mem\t# int & 31-bit mask -> long\n\t"
5097 "andl $dst, $mask" %}
5098 ins_encode %{
5099 Register Rdst = $dst$$Register;
5100 __ movl(Rdst, $mem$$Address);
5101 __ andl(Rdst, $mask$$constant);
5102 %}
5103 ins_pipe(ialu_reg_mem);
5104 %}
5105
5106 // Load Unsigned Integer into Long Register
5107 instruct loadUI2L(rRegL dst, memory mem, immL_32bits mask)
5108 %{
5109 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
5110
5111 ins_cost(125);
5112 format %{ "movl $dst, $mem\t# uint -> long" %}
5113
5114 ins_encode %{
5115 __ movl($dst$$Register, $mem$$Address);
5116 %}
5117
5118 ins_pipe(ialu_reg_mem);
5119 %}
5120
5121 // Load Long
5122 instruct loadL(rRegL dst, memory mem)
5123 %{
5124 match(Set dst (LoadL mem));
5125
5126 ins_cost(125);
5127 format %{ "movq $dst, $mem\t# long" %}
5128
5129 ins_encode %{
5130 __ movq($dst$$Register, $mem$$Address);
5131 %}
5132
5133 ins_pipe(ialu_reg_mem); // XXX
5134 %}
5135
5136 // Load Range
5137 instruct loadRange(rRegI dst, memory mem)
5138 %{
5139 match(Set dst (LoadRange mem));
5140
5141 ins_cost(125); // XXX
5142 format %{ "movl $dst, $mem\t# range" %}
5143 ins_encode %{
5144 __ movl($dst$$Register, $mem$$Address);
5145 %}
5146 ins_pipe(ialu_reg_mem);
5147 %}
5148
5149 // Load Pointer
5150 instruct loadP(rRegP dst, memory mem)
5151 %{
5152 match(Set dst (LoadP mem));
5153 predicate(n->as_Load()->barrier_data() == 0);
5154
5155 ins_cost(125); // XXX
5156 format %{ "movq $dst, $mem\t# ptr" %}
5157 ins_encode %{
5158 __ movq($dst$$Register, $mem$$Address);
5159 %}
5160 ins_pipe(ialu_reg_mem); // XXX
5161 %}
5162
5163 // Load Compressed Pointer
5164 instruct loadN(rRegN dst, memory mem)
5165 %{
5166 match(Set dst (LoadN mem));
5167
5168 ins_cost(125); // XXX
5169 format %{ "movl $dst, $mem\t# compressed ptr" %}
5170 ins_encode %{
5171 __ movl($dst$$Register, $mem$$Address);
5172 %}
5173 ins_pipe(ialu_reg_mem); // XXX
5174 %}
5175
5176
5177 // Load Klass Pointer
5178 instruct loadKlass(rRegP dst, memory mem)
5179 %{
5180 match(Set dst (LoadKlass mem));
5181
5182 ins_cost(125); // XXX
5183 format %{ "movq $dst, $mem\t# class" %}
5184 ins_encode %{
5185 __ movq($dst$$Register, $mem$$Address);
5186 %}
5187 ins_pipe(ialu_reg_mem); // XXX
5188 %}
5189
5190 // Load narrow Klass Pointer
5191 instruct loadNKlass(rRegN dst, memory mem)
5192 %{
5193 match(Set dst (LoadNKlass mem));
5194
5195 ins_cost(125); // XXX
5196 format %{ "movl $dst, $mem\t# compressed klass ptr" %}
5197 ins_encode %{
5198 __ movl($dst$$Register, $mem$$Address);
5199 %}
5200 ins_pipe(ialu_reg_mem); // XXX
5201 %}
5202
5203 // Load Float
5204 instruct loadF(regF dst, memory mem)
5205 %{
5206 match(Set dst (LoadF mem));
5207
5208 ins_cost(145); // XXX
5209 format %{ "movss $dst, $mem\t# float" %}
5210 ins_encode %{
5211 __ movflt($dst$$XMMRegister, $mem$$Address);
5212 %}
5213 ins_pipe(pipe_slow); // XXX
5214 %}
5215
5216 // Load Float
5217 instruct MoveF2VL(vlRegF dst, regF src) %{
5218 match(Set dst src);
5219 format %{ "movss $dst,$src\t! load float (4 bytes)" %}
5220 ins_encode %{
5221 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
5222 %}
5223 ins_pipe( fpu_reg_reg );
5224 %}
5225
5226 // Load Float
5227 instruct MoveF2LEG(legRegF dst, regF src) %{
5228 match(Set dst src);
5229 format %{ "movss $dst,$src\t# if src != dst load float (4 bytes)" %}
5230 ins_encode %{
5231 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
5232 %}
5233 ins_pipe( fpu_reg_reg );
5234 %}
5235
5236 // Load Float
5237 instruct MoveVL2F(regF dst, vlRegF src) %{
5238 match(Set dst src);
5239 format %{ "movss $dst,$src\t! load float (4 bytes)" %}
5240 ins_encode %{
5241 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
5242 %}
5243 ins_pipe( fpu_reg_reg );
5244 %}
5245
5246 // Load Float
5247 instruct MoveLEG2F(regF dst, legRegF src) %{
5248 match(Set dst src);
5249 format %{ "movss $dst,$src\t# if src != dst load float (4 bytes)" %}
5250 ins_encode %{
5251 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
5252 %}
5253 ins_pipe( fpu_reg_reg );
5254 %}
5255
5256 // Load Double
5257 instruct loadD_partial(regD dst, memory mem)
5258 %{
5259 predicate(!UseXmmLoadAndClearUpper);
5260 match(Set dst (LoadD mem));
5261
5262 ins_cost(145); // XXX
5263 format %{ "movlpd $dst, $mem\t# double" %}
5264 ins_encode %{
5265 __ movdbl($dst$$XMMRegister, $mem$$Address);
5266 %}
5267 ins_pipe(pipe_slow); // XXX
5268 %}
5269
5270 instruct loadD(regD dst, memory mem)
5271 %{
5272 predicate(UseXmmLoadAndClearUpper);
5273 match(Set dst (LoadD mem));
5274
5275 ins_cost(145); // XXX
5276 format %{ "movsd $dst, $mem\t# double" %}
5277 ins_encode %{
5278 __ movdbl($dst$$XMMRegister, $mem$$Address);
5279 %}
5280 ins_pipe(pipe_slow); // XXX
5281 %}
5282
5283 // Load Double
5284 instruct MoveD2VL(vlRegD dst, regD src) %{
5285 match(Set dst src);
5286 format %{ "movsd $dst,$src\t! load double (8 bytes)" %}
5287 ins_encode %{
5288 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
5289 %}
5290 ins_pipe( fpu_reg_reg );
5291 %}
5292
5293 // Load Double
5294 instruct MoveD2LEG(legRegD dst, regD src) %{
5295 match(Set dst src);
5296 format %{ "movsd $dst,$src\t# if src != dst load double (8 bytes)" %}
5297 ins_encode %{
5298 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
5299 %}
5300 ins_pipe( fpu_reg_reg );
5301 %}
5302
5303 // Load Double
5304 instruct MoveVL2D(regD dst, vlRegD src) %{
5305 match(Set dst src);
5306 format %{ "movsd $dst,$src\t! load double (8 bytes)" %}
5307 ins_encode %{
5308 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
5309 %}
5310 ins_pipe( fpu_reg_reg );
5311 %}
5312
5313 // Load Double
5314 instruct MoveLEG2D(regD dst, legRegD src) %{
5315 match(Set dst src);
5316 format %{ "movsd $dst,$src\t# if src != dst load double (8 bytes)" %}
5317 ins_encode %{
5318 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
5319 %}
5320 ins_pipe( fpu_reg_reg );
5321 %}
5322
5323 // Following pseudo code describes the algorithm for max[FD]:
5324 // Min algorithm is on similar lines
5325 // btmp = (b < +0.0) ? a : b
5326 // atmp = (b < +0.0) ? b : a
5327 // Tmp = Max_Float(atmp , btmp)
5328 // Res = (atmp == NaN) ? atmp : Tmp
5329
5330 // max = java.lang.Math.max(float a, float b)
5331 instruct maxF_reg(legRegF dst, legRegF a, legRegF b, legRegF tmp, legRegF atmp, legRegF btmp) %{
5332 predicate(UseAVX > 0 && !n->is_reduction());
5333 match(Set dst (MaxF a b));
5334 effect(USE a, USE b, TEMP tmp, TEMP atmp, TEMP btmp);
5335 format %{
5336 "vblendvps $btmp,$b,$a,$b \n\t"
5337 "vblendvps $atmp,$a,$b,$b \n\t"
5338 "vmaxss $tmp,$atmp,$btmp \n\t"
5339 "vcmpps.unordered $btmp,$atmp,$atmp \n\t"
5340 "vblendvps $dst,$tmp,$atmp,$btmp \n\t"
5341 %}
5342 ins_encode %{
5343 int vector_len = Assembler::AVX_128bit;
5344 __ vblendvps($btmp$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, vector_len);
5345 __ vblendvps($atmp$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $b$$XMMRegister, vector_len);
5346 __ vmaxss($tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister);
5347 __ vcmpps($btmp$$XMMRegister, $atmp$$XMMRegister, $atmp$$XMMRegister, Assembler::_false, vector_len);
5348 __ vblendvps($dst$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, vector_len);
5349 %}
5350 ins_pipe( pipe_slow );
5351 %}
5352
5353 instruct maxF_reduction_reg(legRegF dst, legRegF a, legRegF b, legRegF xmmt, rRegI tmp, rFlagsReg cr) %{
5354 predicate(UseAVX > 0 && n->is_reduction());
5355 match(Set dst (MaxF a b));
5356 effect(USE a, USE b, TEMP xmmt, TEMP tmp, KILL cr);
5357
5358 format %{ "$dst = max($a, $b)\t# intrinsic (float)" %}
5359 ins_encode %{
5360 emit_fp_min_max(_masm, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $xmmt$$XMMRegister, $tmp$$Register,
5361 false /*min*/, true /*single*/);
5362 %}
5363 ins_pipe( pipe_slow );
5364 %}
5365
5366 // max = java.lang.Math.max(double a, double b)
5367 instruct maxD_reg(legRegD dst, legRegD a, legRegD b, legRegD tmp, legRegD atmp, legRegD btmp) %{
5368 predicate(UseAVX > 0 && !n->is_reduction());
5369 match(Set dst (MaxD a b));
5370 effect(USE a, USE b, TEMP atmp, TEMP btmp, TEMP tmp);
5371 format %{
5372 "vblendvpd $btmp,$b,$a,$b \n\t"
5373 "vblendvpd $atmp,$a,$b,$b \n\t"
5374 "vmaxsd $tmp,$atmp,$btmp \n\t"
5375 "vcmppd.unordered $btmp,$atmp,$atmp \n\t"
5376 "vblendvpd $dst,$tmp,$atmp,$btmp \n\t"
5377 %}
5378 ins_encode %{
5379 int vector_len = Assembler::AVX_128bit;
5380 __ vblendvpd($btmp$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, vector_len);
5381 __ vblendvpd($atmp$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $b$$XMMRegister, vector_len);
5382 __ vmaxsd($tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister);
5383 __ vcmppd($btmp$$XMMRegister, $atmp$$XMMRegister, $atmp$$XMMRegister, Assembler::_false, vector_len);
5384 __ vblendvpd($dst$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, vector_len);
5385 %}
5386 ins_pipe( pipe_slow );
5387 %}
5388
5389 instruct maxD_reduction_reg(legRegD dst, legRegD a, legRegD b, legRegD xmmt, rRegL tmp, rFlagsReg cr) %{
5390 predicate(UseAVX > 0 && n->is_reduction());
5391 match(Set dst (MaxD a b));
5392 effect(USE a, USE b, TEMP xmmt, TEMP tmp, KILL cr);
5393
5394 format %{ "$dst = max($a, $b)\t# intrinsic (double)" %}
5395 ins_encode %{
5396 emit_fp_min_max(_masm, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $xmmt$$XMMRegister, $tmp$$Register,
5397 false /*min*/, false /*single*/);
5398 %}
5399 ins_pipe( pipe_slow );
5400 %}
5401
5402 // min = java.lang.Math.min(float a, float b)
5403 instruct minF_reg(legRegF dst, legRegF a, legRegF b, legRegF tmp, legRegF atmp, legRegF btmp) %{
5404 predicate(UseAVX > 0 && !n->is_reduction());
5405 match(Set dst (MinF a b));
5406 effect(USE a, USE b, TEMP tmp, TEMP atmp, TEMP btmp);
5407 format %{
5408 "vblendvps $atmp,$a,$b,$a \n\t"
5409 "vblendvps $btmp,$b,$a,$a \n\t"
5410 "vminss $tmp,$atmp,$btmp \n\t"
5411 "vcmpps.unordered $btmp,$atmp,$atmp \n\t"
5412 "vblendvps $dst,$tmp,$atmp,$btmp \n\t"
5413 %}
5414 ins_encode %{
5415 int vector_len = Assembler::AVX_128bit;
5416 __ vblendvps($atmp$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, vector_len);
5417 __ vblendvps($btmp$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, $a$$XMMRegister, vector_len);
5418 __ vminss($tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister);
5419 __ vcmpps($btmp$$XMMRegister, $atmp$$XMMRegister, $atmp$$XMMRegister, Assembler::_false, vector_len);
5420 __ vblendvps($dst$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, vector_len);
5421 %}
5422 ins_pipe( pipe_slow );
5423 %}
5424
5425 instruct minF_reduction_reg(legRegF dst, legRegF a, legRegF b, legRegF xmmt, rRegI tmp, rFlagsReg cr) %{
5426 predicate(UseAVX > 0 && n->is_reduction());
5427 match(Set dst (MinF a b));
5428 effect(USE a, USE b, TEMP xmmt, TEMP tmp, KILL cr);
5429
5430 format %{ "$dst = min($a, $b)\t# intrinsic (float)" %}
5431 ins_encode %{
5432 emit_fp_min_max(_masm, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $xmmt$$XMMRegister, $tmp$$Register,
5433 true /*min*/, true /*single*/);
5434 %}
5435 ins_pipe( pipe_slow );
5436 %}
5437
5438 // min = java.lang.Math.min(double a, double b)
5439 instruct minD_reg(legRegD dst, legRegD a, legRegD b, legRegD tmp, legRegD atmp, legRegD btmp) %{
5440 predicate(UseAVX > 0 && !n->is_reduction());
5441 match(Set dst (MinD a b));
5442 effect(USE a, USE b, TEMP tmp, TEMP atmp, TEMP btmp);
5443 format %{
5444 "vblendvpd $atmp,$a,$b,$a \n\t"
5445 "vblendvpd $btmp,$b,$a,$a \n\t"
5446 "vminsd $tmp,$atmp,$btmp \n\t"
5447 "vcmppd.unordered $btmp,$atmp,$atmp \n\t"
5448 "vblendvpd $dst,$tmp,$atmp,$btmp \n\t"
5449 %}
5450 ins_encode %{
5451 int vector_len = Assembler::AVX_128bit;
5452 __ vblendvpd($atmp$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, vector_len);
5453 __ vblendvpd($btmp$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, $a$$XMMRegister, vector_len);
5454 __ vminsd($tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister);
5455 __ vcmppd($btmp$$XMMRegister, $atmp$$XMMRegister, $atmp$$XMMRegister, Assembler::_false, vector_len);
5456 __ vblendvpd($dst$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, vector_len);
5457 %}
5458 ins_pipe( pipe_slow );
5459 %}
5460
5461 instruct minD_reduction_reg(legRegD dst, legRegD a, legRegD b, legRegD xmmt, rRegL tmp, rFlagsReg cr) %{
5462 predicate(UseAVX > 0 && n->is_reduction());
5463 match(Set dst (MinD a b));
5464 effect(USE a, USE b, TEMP xmmt, TEMP tmp, KILL cr);
5465
5466 format %{ "$dst = min($a, $b)\t# intrinsic (double)" %}
5467 ins_encode %{
5468 emit_fp_min_max(_masm, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $xmmt$$XMMRegister, $tmp$$Register,
5469 true /*min*/, false /*single*/);
5470 %}
5471 ins_pipe( pipe_slow );
5472 %}
5473
5474 // Load Effective Address
5475 instruct leaP8(rRegP dst, indOffset8 mem)
5476 %{
5477 match(Set dst mem);
5478
5479 ins_cost(110); // XXX
5480 format %{ "leaq $dst, $mem\t# ptr 8" %}
5481 ins_encode %{
5482 __ leaq($dst$$Register, $mem$$Address);
5483 %}
5484 ins_pipe(ialu_reg_reg_fat);
5485 %}
5486
5487 instruct leaP32(rRegP dst, indOffset32 mem)
5488 %{
5489 match(Set dst mem);
5490
5491 ins_cost(110);
5492 format %{ "leaq $dst, $mem\t# ptr 32" %}
5493 ins_encode %{
5494 __ leaq($dst$$Register, $mem$$Address);
5495 %}
5496 ins_pipe(ialu_reg_reg_fat);
5497 %}
5498
5499 instruct leaPIdxOff(rRegP dst, indIndexOffset mem)
5500 %{
5501 match(Set dst mem);
5502
5503 ins_cost(110);
5504 format %{ "leaq $dst, $mem\t# ptr idxoff" %}
5505 ins_encode %{
5506 __ leaq($dst$$Register, $mem$$Address);
5507 %}
5508 ins_pipe(ialu_reg_reg_fat);
5509 %}
5510
5511 instruct leaPIdxScale(rRegP dst, indIndexScale mem)
5512 %{
5513 match(Set dst mem);
5514
5515 ins_cost(110);
5516 format %{ "leaq $dst, $mem\t# ptr idxscale" %}
5517 ins_encode %{
5518 __ leaq($dst$$Register, $mem$$Address);
5519 %}
5520 ins_pipe(ialu_reg_reg_fat);
5521 %}
5522
5523 instruct leaPPosIdxScale(rRegP dst, indPosIndexScale mem)
5524 %{
5525 match(Set dst mem);
5526
5527 ins_cost(110);
5528 format %{ "leaq $dst, $mem\t# ptr idxscale" %}
5529 ins_encode %{
5530 __ leaq($dst$$Register, $mem$$Address);
5531 %}
5532 ins_pipe(ialu_reg_reg_fat);
5533 %}
5534
5535 instruct leaPIdxScaleOff(rRegP dst, indIndexScaleOffset mem)
5536 %{
5537 match(Set dst mem);
5538
5539 ins_cost(110);
5540 format %{ "leaq $dst, $mem\t# ptr idxscaleoff" %}
5541 ins_encode %{
5542 __ leaq($dst$$Register, $mem$$Address);
5543 %}
5544 ins_pipe(ialu_reg_reg_fat);
5545 %}
5546
5547 instruct leaPPosIdxOff(rRegP dst, indPosIndexOffset mem)
5548 %{
5549 match(Set dst mem);
5550
5551 ins_cost(110);
5552 format %{ "leaq $dst, $mem\t# ptr posidxoff" %}
5553 ins_encode %{
5554 __ leaq($dst$$Register, $mem$$Address);
5555 %}
5556 ins_pipe(ialu_reg_reg_fat);
5557 %}
5558
5559 instruct leaPPosIdxScaleOff(rRegP dst, indPosIndexScaleOffset mem)
5560 %{
5561 match(Set dst mem);
5562
5563 ins_cost(110);
5564 format %{ "leaq $dst, $mem\t# ptr posidxscaleoff" %}
5565 ins_encode %{
5566 __ leaq($dst$$Register, $mem$$Address);
5567 %}
5568 ins_pipe(ialu_reg_reg_fat);
5569 %}
5570
5571 // Load Effective Address which uses Narrow (32-bits) oop
5572 instruct leaPCompressedOopOffset(rRegP dst, indCompressedOopOffset mem)
5573 %{
5574 predicate(UseCompressedOops && (CompressedOops::shift() != 0));
5575 match(Set dst mem);
5576
5577 ins_cost(110);
5578 format %{ "leaq $dst, $mem\t# ptr compressedoopoff32" %}
5579 ins_encode %{
5580 __ leaq($dst$$Register, $mem$$Address);
5581 %}
5582 ins_pipe(ialu_reg_reg_fat);
5583 %}
5584
5585 instruct leaP8Narrow(rRegP dst, indOffset8Narrow mem)
5586 %{
5587 predicate(CompressedOops::shift() == 0);
5588 match(Set dst mem);
5589
5590 ins_cost(110); // XXX
5591 format %{ "leaq $dst, $mem\t# ptr off8narrow" %}
5592 ins_encode %{
5593 __ leaq($dst$$Register, $mem$$Address);
5594 %}
5595 ins_pipe(ialu_reg_reg_fat);
5596 %}
5597
5598 instruct leaP32Narrow(rRegP dst, indOffset32Narrow mem)
5599 %{
5600 predicate(CompressedOops::shift() == 0);
5601 match(Set dst mem);
5602
5603 ins_cost(110);
5604 format %{ "leaq $dst, $mem\t# ptr off32narrow" %}
5605 ins_encode %{
5606 __ leaq($dst$$Register, $mem$$Address);
5607 %}
5608 ins_pipe(ialu_reg_reg_fat);
5609 %}
5610
5611 instruct leaPIdxOffNarrow(rRegP dst, indIndexOffsetNarrow mem)
5612 %{
5613 predicate(CompressedOops::shift() == 0);
5614 match(Set dst mem);
5615
5616 ins_cost(110);
5617 format %{ "leaq $dst, $mem\t# ptr idxoffnarrow" %}
5618 ins_encode %{
5619 __ leaq($dst$$Register, $mem$$Address);
5620 %}
5621 ins_pipe(ialu_reg_reg_fat);
5622 %}
5623
5624 instruct leaPIdxScaleNarrow(rRegP dst, indIndexScaleNarrow mem)
5625 %{
5626 predicate(CompressedOops::shift() == 0);
5627 match(Set dst mem);
5628
5629 ins_cost(110);
5630 format %{ "leaq $dst, $mem\t# ptr idxscalenarrow" %}
5631 ins_encode %{
5632 __ leaq($dst$$Register, $mem$$Address);
5633 %}
5634 ins_pipe(ialu_reg_reg_fat);
5635 %}
5636
5637 instruct leaPIdxScaleOffNarrow(rRegP dst, indIndexScaleOffsetNarrow mem)
5638 %{
5639 predicate(CompressedOops::shift() == 0);
5640 match(Set dst mem);
5641
5642 ins_cost(110);
5643 format %{ "leaq $dst, $mem\t# ptr idxscaleoffnarrow" %}
5644 ins_encode %{
5645 __ leaq($dst$$Register, $mem$$Address);
5646 %}
5647 ins_pipe(ialu_reg_reg_fat);
5648 %}
5649
5650 instruct leaPPosIdxOffNarrow(rRegP dst, indPosIndexOffsetNarrow mem)
5651 %{
5652 predicate(CompressedOops::shift() == 0);
5653 match(Set dst mem);
5654
5655 ins_cost(110);
5656 format %{ "leaq $dst, $mem\t# ptr posidxoffnarrow" %}
5657 ins_encode %{
5658 __ leaq($dst$$Register, $mem$$Address);
5659 %}
5660 ins_pipe(ialu_reg_reg_fat);
5661 %}
5662
5663 instruct leaPPosIdxScaleOffNarrow(rRegP dst, indPosIndexScaleOffsetNarrow mem)
5664 %{
5665 predicate(CompressedOops::shift() == 0);
5666 match(Set dst mem);
5667
5668 ins_cost(110);
5669 format %{ "leaq $dst, $mem\t# ptr posidxscaleoffnarrow" %}
5670 ins_encode %{
5671 __ leaq($dst$$Register, $mem$$Address);
5672 %}
5673 ins_pipe(ialu_reg_reg_fat);
5674 %}
5675
5676 instruct loadConI(rRegI dst, immI src)
5677 %{
5678 match(Set dst src);
5679
5680 format %{ "movl $dst, $src\t# int" %}
5681 ins_encode %{
5682 __ movl($dst$$Register, $src$$constant);
5683 %}
5684 ins_pipe(ialu_reg_fat); // XXX
5685 %}
5686
5687 instruct loadConI0(rRegI dst, immI_0 src, rFlagsReg cr)
5688 %{
5689 match(Set dst src);
5690 effect(KILL cr);
5691
5692 ins_cost(50);
5693 format %{ "xorl $dst, $dst\t# int" %}
5694 ins_encode %{
5695 __ xorl($dst$$Register, $dst$$Register);
5696 %}
5697 ins_pipe(ialu_reg);
5698 %}
5699
5700 instruct loadConL(rRegL dst, immL src)
5701 %{
5702 match(Set dst src);
5703
5704 ins_cost(150);
5705 format %{ "movq $dst, $src\t# long" %}
5706 ins_encode %{
5707 __ mov64($dst$$Register, $src$$constant);
5708 %}
5709 ins_pipe(ialu_reg);
5710 %}
5711
5712 instruct loadConL0(rRegL dst, immL0 src, rFlagsReg cr)
5713 %{
5714 match(Set dst src);
5715 effect(KILL cr);
5716
5717 ins_cost(50);
5718 format %{ "xorl $dst, $dst\t# long" %}
5719 ins_encode %{
5720 __ xorl($dst$$Register, $dst$$Register);
5721 %}
5722 ins_pipe(ialu_reg); // XXX
5723 %}
5724
5725 instruct loadConUL32(rRegL dst, immUL32 src)
5726 %{
5727 match(Set dst src);
5728
5729 ins_cost(60);
5730 format %{ "movl $dst, $src\t# long (unsigned 32-bit)" %}
5731 ins_encode %{
5732 __ movl($dst$$Register, $src$$constant);
5733 %}
5734 ins_pipe(ialu_reg);
5735 %}
5736
5737 instruct loadConL32(rRegL dst, immL32 src)
5738 %{
5739 match(Set dst src);
5740
5741 ins_cost(70);
5742 format %{ "movq $dst, $src\t# long (32-bit)" %}
5743 ins_encode %{
5744 __ movq($dst$$Register, $src$$constant);
5745 %}
5746 ins_pipe(ialu_reg);
5747 %}
5748
5749 instruct loadConP(rRegP dst, immP con) %{
5750 match(Set dst con);
5751
5752 format %{ "movq $dst, $con\t# ptr" %}
5753 ins_encode %{
5754 __ mov64($dst$$Register, $con$$constant, $con->constant_reloc(), RELOC_IMM64);
5755 %}
5756 ins_pipe(ialu_reg_fat); // XXX
5757 %}
5758
5759 instruct loadConP0(rRegP dst, immP0 src, rFlagsReg cr)
5760 %{
5761 match(Set dst src);
5762 effect(KILL cr);
5763
5764 ins_cost(50);
5765 format %{ "xorl $dst, $dst\t# ptr" %}
5766 ins_encode %{
5767 __ xorl($dst$$Register, $dst$$Register);
5768 %}
5769 ins_pipe(ialu_reg);
5770 %}
5771
5772 instruct loadConP31(rRegP dst, immP31 src, rFlagsReg cr)
5773 %{
5774 match(Set dst src);
5775 effect(KILL cr);
5776
5777 ins_cost(60);
5778 format %{ "movl $dst, $src\t# ptr (positive 32-bit)" %}
5779 ins_encode %{
5780 __ movl($dst$$Register, $src$$constant);
5781 %}
5782 ins_pipe(ialu_reg);
5783 %}
5784
5785 instruct loadConF(regF dst, immF con) %{
5786 match(Set dst con);
5787 ins_cost(125);
5788 format %{ "movss $dst, [$constantaddress]\t# load from constant table: float=$con" %}
5789 ins_encode %{
5790 __ movflt($dst$$XMMRegister, $constantaddress($con));
5791 %}
5792 ins_pipe(pipe_slow);
5793 %}
5794
5795 instruct loadConN0(rRegN dst, immN0 src, rFlagsReg cr) %{
5796 match(Set dst src);
5797 effect(KILL cr);
5798 format %{ "xorq $dst, $src\t# compressed NULL ptr" %}
5799 ins_encode %{
5800 __ xorq($dst$$Register, $dst$$Register);
5801 %}
5802 ins_pipe(ialu_reg);
5803 %}
5804
5805 instruct loadConN(rRegN dst, immN src) %{
5806 match(Set dst src);
5807
5808 ins_cost(125);
5809 format %{ "movl $dst, $src\t# compressed ptr" %}
5810 ins_encode %{
5811 address con = (address)$src$$constant;
5812 if (con == NULL) {
5813 ShouldNotReachHere();
5814 } else {
5815 __ set_narrow_oop($dst$$Register, (jobject)$src$$constant);
5816 }
5817 %}
5818 ins_pipe(ialu_reg_fat); // XXX
5819 %}
5820
5821 instruct loadConNKlass(rRegN dst, immNKlass src) %{
5822 match(Set dst src);
5823
5824 ins_cost(125);
5825 format %{ "movl $dst, $src\t# compressed klass ptr" %}
5826 ins_encode %{
5827 address con = (address)$src$$constant;
5828 if (con == NULL) {
5829 ShouldNotReachHere();
5830 } else {
5831 __ set_narrow_klass($dst$$Register, (Klass*)$src$$constant);
5832 }
5833 %}
5834 ins_pipe(ialu_reg_fat); // XXX
5835 %}
5836
5837 instruct loadConF0(regF dst, immF0 src)
5838 %{
5839 match(Set dst src);
5840 ins_cost(100);
5841
5842 format %{ "xorps $dst, $dst\t# float 0.0" %}
5843 ins_encode %{
5844 __ xorps($dst$$XMMRegister, $dst$$XMMRegister);
5845 %}
5846 ins_pipe(pipe_slow);
5847 %}
5848
5849 // Use the same format since predicate() can not be used here.
5850 instruct loadConD(regD dst, immD con) %{
5851 match(Set dst con);
5852 ins_cost(125);
5853 format %{ "movsd $dst, [$constantaddress]\t# load from constant table: double=$con" %}
5854 ins_encode %{
5855 __ movdbl($dst$$XMMRegister, $constantaddress($con));
5856 %}
5857 ins_pipe(pipe_slow);
5858 %}
5859
5860 instruct loadConD0(regD dst, immD0 src)
5861 %{
5862 match(Set dst src);
5863 ins_cost(100);
5864
5865 format %{ "xorpd $dst, $dst\t# double 0.0" %}
5866 ins_encode %{
5867 __ xorpd ($dst$$XMMRegister, $dst$$XMMRegister);
5868 %}
5869 ins_pipe(pipe_slow);
5870 %}
5871
5872 instruct loadSSI(rRegI dst, stackSlotI src)
5873 %{
5874 match(Set dst src);
5875
5876 ins_cost(125);
5877 format %{ "movl $dst, $src\t# int stk" %}
5878 opcode(0x8B);
5879 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
5880 ins_pipe(ialu_reg_mem);
5881 %}
5882
5883 instruct loadSSL(rRegL dst, stackSlotL src)
5884 %{
5885 match(Set dst src);
5886
5887 ins_cost(125);
5888 format %{ "movq $dst, $src\t# long stk" %}
5889 opcode(0x8B);
5890 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
5891 ins_pipe(ialu_reg_mem);
5892 %}
5893
5894 instruct loadSSP(rRegP dst, stackSlotP src)
5895 %{
5896 match(Set dst src);
5897
5898 ins_cost(125);
5899 format %{ "movq $dst, $src\t# ptr stk" %}
5900 opcode(0x8B);
5901 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
5902 ins_pipe(ialu_reg_mem);
5903 %}
5904
5905 instruct loadSSF(regF dst, stackSlotF src)
5906 %{
5907 match(Set dst src);
5908
5909 ins_cost(125);
5910 format %{ "movss $dst, $src\t# float stk" %}
5911 ins_encode %{
5912 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
5913 %}
5914 ins_pipe(pipe_slow); // XXX
5915 %}
5916
5917 // Use the same format since predicate() can not be used here.
5918 instruct loadSSD(regD dst, stackSlotD src)
5919 %{
5920 match(Set dst src);
5921
5922 ins_cost(125);
5923 format %{ "movsd $dst, $src\t# double stk" %}
5924 ins_encode %{
5925 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
5926 %}
5927 ins_pipe(pipe_slow); // XXX
5928 %}
5929
5930 // Prefetch instructions for allocation.
5931 // Must be safe to execute with invalid address (cannot fault).
5932
5933 instruct prefetchAlloc( memory mem ) %{
5934 predicate(AllocatePrefetchInstr==3);
5935 match(PrefetchAllocation mem);
5936 ins_cost(125);
5937
5938 format %{ "PREFETCHW $mem\t# Prefetch allocation into level 1 cache and mark modified" %}
5939 ins_encode %{
5940 __ prefetchw($mem$$Address);
5941 %}
5942 ins_pipe(ialu_mem);
5943 %}
5944
5945 instruct prefetchAllocNTA( memory mem ) %{
5946 predicate(AllocatePrefetchInstr==0);
5947 match(PrefetchAllocation mem);
5948 ins_cost(125);
5949
5950 format %{ "PREFETCHNTA $mem\t# Prefetch allocation to non-temporal cache for write" %}
5951 ins_encode %{
5952 __ prefetchnta($mem$$Address);
5953 %}
5954 ins_pipe(ialu_mem);
5955 %}
5956
5957 instruct prefetchAllocT0( memory mem ) %{
5958 predicate(AllocatePrefetchInstr==1);
5959 match(PrefetchAllocation mem);
5960 ins_cost(125);
5961
5962 format %{ "PREFETCHT0 $mem\t# Prefetch allocation to level 1 and 2 caches for write" %}
5963 ins_encode %{
5964 __ prefetcht0($mem$$Address);
5965 %}
5966 ins_pipe(ialu_mem);
5967 %}
5968
5969 instruct prefetchAllocT2( memory mem ) %{
5970 predicate(AllocatePrefetchInstr==2);
5971 match(PrefetchAllocation mem);
5972 ins_cost(125);
5973
5974 format %{ "PREFETCHT2 $mem\t# Prefetch allocation to level 2 cache for write" %}
5975 ins_encode %{
5976 __ prefetcht2($mem$$Address);
5977 %}
5978 ins_pipe(ialu_mem);
5979 %}
5980
5981 //----------Store Instructions-------------------------------------------------
5982
5983 // Store Byte
5984 instruct storeB(memory mem, rRegI src)
5985 %{
5986 match(Set mem (StoreB mem src));
5987
5988 ins_cost(125); // XXX
5989 format %{ "movb $mem, $src\t# byte" %}
5990 ins_encode %{
5991 __ movb($mem$$Address, $src$$Register);
5992 %}
5993 ins_pipe(ialu_mem_reg);
5994 %}
5995
5996 // Store Char/Short
5997 instruct storeC(memory mem, rRegI src)
5998 %{
5999 match(Set mem (StoreC mem src));
6000
6001 ins_cost(125); // XXX
6002 format %{ "movw $mem, $src\t# char/short" %}
6003 ins_encode %{
6004 __ movw($mem$$Address, $src$$Register);
6005 %}
6006 ins_pipe(ialu_mem_reg);
6007 %}
6008
6009 // Store Integer
6010 instruct storeI(memory mem, rRegI src)
6011 %{
6012 match(Set mem (StoreI mem src));
6013
6014 ins_cost(125); // XXX
6015 format %{ "movl $mem, $src\t# int" %}
6016 ins_encode %{
6017 __ movl($mem$$Address, $src$$Register);
6018 %}
6019 ins_pipe(ialu_mem_reg);
6020 %}
6021
6022 // Store Long
6023 instruct storeL(memory mem, rRegL src)
6024 %{
6025 match(Set mem (StoreL mem src));
6026
6027 ins_cost(125); // XXX
6028 format %{ "movq $mem, $src\t# long" %}
6029 ins_encode %{
6030 __ movq($mem$$Address, $src$$Register);
6031 %}
6032 ins_pipe(ialu_mem_reg); // XXX
6033 %}
6034
6035 // Store Pointer
6036 instruct storeP(memory mem, any_RegP src)
6037 %{
6038 match(Set mem (StoreP mem src));
6039
6040 ins_cost(125); // XXX
6041 format %{ "movq $mem, $src\t# ptr" %}
6042 ins_encode %{
6043 __ movq($mem$$Address, $src$$Register);
6044 %}
6045 ins_pipe(ialu_mem_reg);
6046 %}
6047
6048 instruct storeImmP0(memory mem, immP0 zero)
6049 %{
6050 predicate(UseCompressedOops && (CompressedOops::base() == NULL));
6051 match(Set mem (StoreP mem zero));
6052
6053 ins_cost(125); // XXX
6054 format %{ "movq $mem, R12\t# ptr (R12_heapbase==0)" %}
6055 ins_encode %{
6056 __ movq($mem$$Address, r12);
6057 %}
6058 ins_pipe(ialu_mem_reg);
6059 %}
6060
6061 // Store NULL Pointer, mark word, or other simple pointer constant.
6062 instruct storeImmP(memory mem, immP31 src)
6063 %{
6064 match(Set mem (StoreP mem src));
6065
6066 ins_cost(150); // XXX
6067 format %{ "movq $mem, $src\t# ptr" %}
6068 ins_encode %{
6069 __ movq($mem$$Address, $src$$constant);
6070 %}
6071 ins_pipe(ialu_mem_imm);
6072 %}
6073
6074 // Store Compressed Pointer
6075 instruct storeN(memory mem, rRegN src)
6076 %{
6077 match(Set mem (StoreN mem src));
6078
6079 ins_cost(125); // XXX
6080 format %{ "movl $mem, $src\t# compressed ptr" %}
6081 ins_encode %{
6082 __ movl($mem$$Address, $src$$Register);
6083 %}
6084 ins_pipe(ialu_mem_reg);
6085 %}
6086
6087 instruct storeNKlass(memory mem, rRegN src)
6088 %{
6089 match(Set mem (StoreNKlass mem src));
6090
6091 ins_cost(125); // XXX
6092 format %{ "movl $mem, $src\t# compressed klass ptr" %}
6093 ins_encode %{
6094 __ movl($mem$$Address, $src$$Register);
6095 %}
6096 ins_pipe(ialu_mem_reg);
6097 %}
6098
6099 instruct storeImmN0(memory mem, immN0 zero)
6100 %{
6101 predicate(CompressedOops::base() == NULL);
6102 match(Set mem (StoreN mem zero));
6103
6104 ins_cost(125); // XXX
6105 format %{ "movl $mem, R12\t# compressed ptr (R12_heapbase==0)" %}
6106 ins_encode %{
6107 __ movl($mem$$Address, r12);
6108 %}
6109 ins_pipe(ialu_mem_reg);
6110 %}
6111
6112 instruct storeImmN(memory mem, immN src)
6113 %{
6114 match(Set mem (StoreN mem src));
6115
6116 ins_cost(150); // XXX
6117 format %{ "movl $mem, $src\t# compressed ptr" %}
6118 ins_encode %{
6119 address con = (address)$src$$constant;
6120 if (con == NULL) {
6121 __ movl($mem$$Address, (int32_t)0);
6122 } else {
6123 __ set_narrow_oop($mem$$Address, (jobject)$src$$constant);
6124 }
6125 %}
6126 ins_pipe(ialu_mem_imm);
6127 %}
6128
6129 instruct storeImmNKlass(memory mem, immNKlass src)
6130 %{
6131 match(Set mem (StoreNKlass mem src));
6132
6133 ins_cost(150); // XXX
6134 format %{ "movl $mem, $src\t# compressed klass ptr" %}
6135 ins_encode %{
6136 __ set_narrow_klass($mem$$Address, (Klass*)$src$$constant);
6137 %}
6138 ins_pipe(ialu_mem_imm);
6139 %}
6140
6141 // Store Integer Immediate
6142 instruct storeImmI0(memory mem, immI_0 zero)
6143 %{
6144 predicate(UseCompressedOops && (CompressedOops::base() == NULL));
6145 match(Set mem (StoreI mem zero));
6146
6147 ins_cost(125); // XXX
6148 format %{ "movl $mem, R12\t# int (R12_heapbase==0)" %}
6149 ins_encode %{
6150 __ movl($mem$$Address, r12);
6151 %}
6152 ins_pipe(ialu_mem_reg);
6153 %}
6154
6155 instruct storeImmI(memory mem, immI src)
6156 %{
6157 match(Set mem (StoreI mem src));
6158
6159 ins_cost(150);
6160 format %{ "movl $mem, $src\t# int" %}
6161 ins_encode %{
6162 __ movl($mem$$Address, $src$$constant);
6163 %}
6164 ins_pipe(ialu_mem_imm);
6165 %}
6166
6167 // Store Long Immediate
6168 instruct storeImmL0(memory mem, immL0 zero)
6169 %{
6170 predicate(UseCompressedOops && (CompressedOops::base() == NULL));
6171 match(Set mem (StoreL mem zero));
6172
6173 ins_cost(125); // XXX
6174 format %{ "movq $mem, R12\t# long (R12_heapbase==0)" %}
6175 ins_encode %{
6176 __ movq($mem$$Address, r12);
6177 %}
6178 ins_pipe(ialu_mem_reg);
6179 %}
6180
6181 instruct storeImmL(memory mem, immL32 src)
6182 %{
6183 match(Set mem (StoreL mem src));
6184
6185 ins_cost(150);
6186 format %{ "movq $mem, $src\t# long" %}
6187 ins_encode %{
6188 __ movq($mem$$Address, $src$$constant);
6189 %}
6190 ins_pipe(ialu_mem_imm);
6191 %}
6192
6193 // Store Short/Char Immediate
6194 instruct storeImmC0(memory mem, immI_0 zero)
6195 %{
6196 predicate(UseCompressedOops && (CompressedOops::base() == NULL));
6197 match(Set mem (StoreC mem zero));
6198
6199 ins_cost(125); // XXX
6200 format %{ "movw $mem, R12\t# short/char (R12_heapbase==0)" %}
6201 ins_encode %{
6202 __ movw($mem$$Address, r12);
6203 %}
6204 ins_pipe(ialu_mem_reg);
6205 %}
6206
6207 instruct storeImmI16(memory mem, immI16 src)
6208 %{
6209 predicate(UseStoreImmI16);
6210 match(Set mem (StoreC mem src));
6211
6212 ins_cost(150);
6213 format %{ "movw $mem, $src\t# short/char" %}
6214 ins_encode %{
6215 __ movw($mem$$Address, $src$$constant);
6216 %}
6217 ins_pipe(ialu_mem_imm);
6218 %}
6219
6220 // Store Byte Immediate
6221 instruct storeImmB0(memory mem, immI_0 zero)
6222 %{
6223 predicate(UseCompressedOops && (CompressedOops::base() == NULL));
6224 match(Set mem (StoreB mem zero));
6225
6226 ins_cost(125); // XXX
6227 format %{ "movb $mem, R12\t# short/char (R12_heapbase==0)" %}
6228 ins_encode %{
6229 __ movb($mem$$Address, r12);
6230 %}
6231 ins_pipe(ialu_mem_reg);
6232 %}
6233
6234 instruct storeImmB(memory mem, immI8 src)
6235 %{
6236 match(Set mem (StoreB mem src));
6237
6238 ins_cost(150); // XXX
6239 format %{ "movb $mem, $src\t# byte" %}
6240 ins_encode %{
6241 __ movb($mem$$Address, $src$$constant);
6242 %}
6243 ins_pipe(ialu_mem_imm);
6244 %}
6245
6246 // Store CMS card-mark Immediate
6247 instruct storeImmCM0_reg(memory mem, immI_0 zero)
6248 %{
6249 predicate(UseCompressedOops && (CompressedOops::base() == NULL));
6250 match(Set mem (StoreCM mem zero));
6251
6252 ins_cost(125); // XXX
6253 format %{ "movb $mem, R12\t# CMS card-mark byte 0 (R12_heapbase==0)" %}
6254 ins_encode %{
6255 __ movb($mem$$Address, r12);
6256 %}
6257 ins_pipe(ialu_mem_reg);
6258 %}
6259
6260 instruct storeImmCM0(memory mem, immI_0 src)
6261 %{
6262 match(Set mem (StoreCM mem src));
6263
6264 ins_cost(150); // XXX
6265 format %{ "movb $mem, $src\t# CMS card-mark byte 0" %}
6266 ins_encode %{
6267 __ movb($mem$$Address, $src$$constant);
6268 %}
6269 ins_pipe(ialu_mem_imm);
6270 %}
6271
6272 // Store Float
6273 instruct storeF(memory mem, regF src)
6274 %{
6275 match(Set mem (StoreF mem src));
6276
6277 ins_cost(95); // XXX
6278 format %{ "movss $mem, $src\t# float" %}
6279 ins_encode %{
6280 __ movflt($mem$$Address, $src$$XMMRegister);
6281 %}
6282 ins_pipe(pipe_slow); // XXX
6283 %}
6284
6285 // Store immediate Float value (it is faster than store from XMM register)
6286 instruct storeF0(memory mem, immF0 zero)
6287 %{
6288 predicate(UseCompressedOops && (CompressedOops::base() == NULL));
6289 match(Set mem (StoreF mem zero));
6290
6291 ins_cost(25); // XXX
6292 format %{ "movl $mem, R12\t# float 0. (R12_heapbase==0)" %}
6293 ins_encode %{
6294 __ movl($mem$$Address, r12);
6295 %}
6296 ins_pipe(ialu_mem_reg);
6297 %}
6298
6299 instruct storeF_imm(memory mem, immF src)
6300 %{
6301 match(Set mem (StoreF mem src));
6302
6303 ins_cost(50);
6304 format %{ "movl $mem, $src\t# float" %}
6305 ins_encode %{
6306 __ movl($mem$$Address, jint_cast($src$$constant));
6307 %}
6308 ins_pipe(ialu_mem_imm);
6309 %}
6310
6311 // Store Double
6312 instruct storeD(memory mem, regD src)
6313 %{
6314 match(Set mem (StoreD mem src));
6315
6316 ins_cost(95); // XXX
6317 format %{ "movsd $mem, $src\t# double" %}
6318 ins_encode %{
6319 __ movdbl($mem$$Address, $src$$XMMRegister);
6320 %}
6321 ins_pipe(pipe_slow); // XXX
6322 %}
6323
6324 // Store immediate double 0.0 (it is faster than store from XMM register)
6325 instruct storeD0_imm(memory mem, immD0 src)
6326 %{
6327 predicate(!UseCompressedOops || (CompressedOops::base() != NULL));
6328 match(Set mem (StoreD mem src));
6329
6330 ins_cost(50);
6331 format %{ "movq $mem, $src\t# double 0." %}
6332 ins_encode %{
6333 __ movq($mem$$Address, $src$$constant);
6334 %}
6335 ins_pipe(ialu_mem_imm);
6336 %}
6337
6338 instruct storeD0(memory mem, immD0 zero)
6339 %{
6340 predicate(UseCompressedOops && (CompressedOops::base() == NULL));
6341 match(Set mem (StoreD mem zero));
6342
6343 ins_cost(25); // XXX
6344 format %{ "movq $mem, R12\t# double 0. (R12_heapbase==0)" %}
6345 ins_encode %{
6346 __ movq($mem$$Address, r12);
6347 %}
6348 ins_pipe(ialu_mem_reg);
6349 %}
6350
6351 instruct storeSSI(stackSlotI dst, rRegI src)
6352 %{
6353 match(Set dst src);
6354
6355 ins_cost(100);
6356 format %{ "movl $dst, $src\t# int stk" %}
6357 opcode(0x89);
6358 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
6359 ins_pipe( ialu_mem_reg );
6360 %}
6361
6362 instruct storeSSL(stackSlotL dst, rRegL src)
6363 %{
6364 match(Set dst src);
6365
6366 ins_cost(100);
6367 format %{ "movq $dst, $src\t# long stk" %}
6368 opcode(0x89);
6369 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
6370 ins_pipe(ialu_mem_reg);
6371 %}
6372
6373 instruct storeSSP(stackSlotP dst, rRegP src)
6374 %{
6375 match(Set dst src);
6376
6377 ins_cost(100);
6378 format %{ "movq $dst, $src\t# ptr stk" %}
6379 opcode(0x89);
6380 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
6381 ins_pipe(ialu_mem_reg);
6382 %}
6383
6384 instruct storeSSF(stackSlotF dst, regF src)
6385 %{
6386 match(Set dst src);
6387
6388 ins_cost(95); // XXX
6389 format %{ "movss $dst, $src\t# float stk" %}
6390 ins_encode %{
6391 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
6392 %}
6393 ins_pipe(pipe_slow); // XXX
6394 %}
6395
6396 instruct storeSSD(stackSlotD dst, regD src)
6397 %{
6398 match(Set dst src);
6399
6400 ins_cost(95); // XXX
6401 format %{ "movsd $dst, $src\t# double stk" %}
6402 ins_encode %{
6403 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
6404 %}
6405 ins_pipe(pipe_slow); // XXX
6406 %}
6407
6408 instruct cacheWB(indirect addr)
6409 %{
6410 predicate(VM_Version::supports_data_cache_line_flush());
6411 match(CacheWB addr);
6412
6413 ins_cost(100);
6414 format %{"cache wb $addr" %}
6415 ins_encode %{
6416 assert($addr->index_position() < 0, "should be");
6417 assert($addr$$disp == 0, "should be");
6418 __ cache_wb(Address($addr$$base$$Register, 0));
6419 %}
6420 ins_pipe(pipe_slow); // XXX
6421 %}
6422
6423 instruct cacheWBPreSync()
6424 %{
6425 predicate(VM_Version::supports_data_cache_line_flush());
6426 match(CacheWBPreSync);
6427
6428 ins_cost(100);
6429 format %{"cache wb presync" %}
6430 ins_encode %{
6431 __ cache_wbsync(true);
6432 %}
6433 ins_pipe(pipe_slow); // XXX
6434 %}
6435
6436 instruct cacheWBPostSync()
6437 %{
6438 predicate(VM_Version::supports_data_cache_line_flush());
6439 match(CacheWBPostSync);
6440
6441 ins_cost(100);
6442 format %{"cache wb postsync" %}
6443 ins_encode %{
6444 __ cache_wbsync(false);
6445 %}
6446 ins_pipe(pipe_slow); // XXX
6447 %}
6448
6449 //----------BSWAP Instructions-------------------------------------------------
6450 instruct bytes_reverse_int(rRegI dst) %{
6451 match(Set dst (ReverseBytesI dst));
6452
6453 format %{ "bswapl $dst" %}
6454 ins_encode %{
6455 __ bswapl($dst$$Register);
6456 %}
6457 ins_pipe( ialu_reg );
6458 %}
6459
6460 instruct bytes_reverse_long(rRegL dst) %{
6461 match(Set dst (ReverseBytesL dst));
6462
6463 format %{ "bswapq $dst" %}
6464 ins_encode %{
6465 __ bswapq($dst$$Register);
6466 %}
6467 ins_pipe( ialu_reg);
6468 %}
6469
6470 instruct bytes_reverse_unsigned_short(rRegI dst, rFlagsReg cr) %{
6471 match(Set dst (ReverseBytesUS dst));
6472 effect(KILL cr);
6473
6474 format %{ "bswapl $dst\n\t"
6475 "shrl $dst,16\n\t" %}
6476 ins_encode %{
6477 __ bswapl($dst$$Register);
6478 __ shrl($dst$$Register, 16);
6479 %}
6480 ins_pipe( ialu_reg );
6481 %}
6482
6483 instruct bytes_reverse_short(rRegI dst, rFlagsReg cr) %{
6484 match(Set dst (ReverseBytesS dst));
6485 effect(KILL cr);
6486
6487 format %{ "bswapl $dst\n\t"
6488 "sar $dst,16\n\t" %}
6489 ins_encode %{
6490 __ bswapl($dst$$Register);
6491 __ sarl($dst$$Register, 16);
6492 %}
6493 ins_pipe( ialu_reg );
6494 %}
6495
6496 //---------- Zeros Count Instructions ------------------------------------------
6497
6498 instruct countLeadingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{
6499 predicate(UseCountLeadingZerosInstruction);
6500 match(Set dst (CountLeadingZerosI src));
6501 effect(KILL cr);
6502
6503 format %{ "lzcntl $dst, $src\t# count leading zeros (int)" %}
6504 ins_encode %{
6505 __ lzcntl($dst$$Register, $src$$Register);
6506 %}
6507 ins_pipe(ialu_reg);
6508 %}
6509
6510 instruct countLeadingZerosI_bsr(rRegI dst, rRegI src, rFlagsReg cr) %{
6511 predicate(!UseCountLeadingZerosInstruction);
6512 match(Set dst (CountLeadingZerosI src));
6513 effect(KILL cr);
6514
6515 format %{ "bsrl $dst, $src\t# count leading zeros (int)\n\t"
6516 "jnz skip\n\t"
6517 "movl $dst, -1\n"
6518 "skip:\n\t"
6519 "negl $dst\n\t"
6520 "addl $dst, 31" %}
6521 ins_encode %{
6522 Register Rdst = $dst$$Register;
6523 Register Rsrc = $src$$Register;
6524 Label skip;
6525 __ bsrl(Rdst, Rsrc);
6526 __ jccb(Assembler::notZero, skip);
6527 __ movl(Rdst, -1);
6528 __ bind(skip);
6529 __ negl(Rdst);
6530 __ addl(Rdst, BitsPerInt - 1);
6531 %}
6532 ins_pipe(ialu_reg);
6533 %}
6534
6535 instruct countLeadingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{
6536 predicate(UseCountLeadingZerosInstruction);
6537 match(Set dst (CountLeadingZerosL src));
6538 effect(KILL cr);
6539
6540 format %{ "lzcntq $dst, $src\t# count leading zeros (long)" %}
6541 ins_encode %{
6542 __ lzcntq($dst$$Register, $src$$Register);
6543 %}
6544 ins_pipe(ialu_reg);
6545 %}
6546
6547 instruct countLeadingZerosL_bsr(rRegI dst, rRegL src, rFlagsReg cr) %{
6548 predicate(!UseCountLeadingZerosInstruction);
6549 match(Set dst (CountLeadingZerosL src));
6550 effect(KILL cr);
6551
6552 format %{ "bsrq $dst, $src\t# count leading zeros (long)\n\t"
6553 "jnz skip\n\t"
6554 "movl $dst, -1\n"
6555 "skip:\n\t"
6556 "negl $dst\n\t"
6557 "addl $dst, 63" %}
6558 ins_encode %{
6559 Register Rdst = $dst$$Register;
6560 Register Rsrc = $src$$Register;
6561 Label skip;
6562 __ bsrq(Rdst, Rsrc);
6563 __ jccb(Assembler::notZero, skip);
6564 __ movl(Rdst, -1);
6565 __ bind(skip);
6566 __ negl(Rdst);
6567 __ addl(Rdst, BitsPerLong - 1);
6568 %}
6569 ins_pipe(ialu_reg);
6570 %}
6571
6572 instruct countTrailingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{
6573 predicate(UseCountTrailingZerosInstruction);
6574 match(Set dst (CountTrailingZerosI src));
6575 effect(KILL cr);
6576
6577 format %{ "tzcntl $dst, $src\t# count trailing zeros (int)" %}
6578 ins_encode %{
6579 __ tzcntl($dst$$Register, $src$$Register);
6580 %}
6581 ins_pipe(ialu_reg);
6582 %}
6583
6584 instruct countTrailingZerosI_bsf(rRegI dst, rRegI src, rFlagsReg cr) %{
6585 predicate(!UseCountTrailingZerosInstruction);
6586 match(Set dst (CountTrailingZerosI src));
6587 effect(KILL cr);
6588
6589 format %{ "bsfl $dst, $src\t# count trailing zeros (int)\n\t"
6590 "jnz done\n\t"
6591 "movl $dst, 32\n"
6592 "done:" %}
6593 ins_encode %{
6594 Register Rdst = $dst$$Register;
6595 Label done;
6596 __ bsfl(Rdst, $src$$Register);
6597 __ jccb(Assembler::notZero, done);
6598 __ movl(Rdst, BitsPerInt);
6599 __ bind(done);
6600 %}
6601 ins_pipe(ialu_reg);
6602 %}
6603
6604 instruct countTrailingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{
6605 predicate(UseCountTrailingZerosInstruction);
6606 match(Set dst (CountTrailingZerosL src));
6607 effect(KILL cr);
6608
6609 format %{ "tzcntq $dst, $src\t# count trailing zeros (long)" %}
6610 ins_encode %{
6611 __ tzcntq($dst$$Register, $src$$Register);
6612 %}
6613 ins_pipe(ialu_reg);
6614 %}
6615
6616 instruct countTrailingZerosL_bsf(rRegI dst, rRegL src, rFlagsReg cr) %{
6617 predicate(!UseCountTrailingZerosInstruction);
6618 match(Set dst (CountTrailingZerosL src));
6619 effect(KILL cr);
6620
6621 format %{ "bsfq $dst, $src\t# count trailing zeros (long)\n\t"
6622 "jnz done\n\t"
6623 "movl $dst, 64\n"
6624 "done:" %}
6625 ins_encode %{
6626 Register Rdst = $dst$$Register;
6627 Label done;
6628 __ bsfq(Rdst, $src$$Register);
6629 __ jccb(Assembler::notZero, done);
6630 __ movl(Rdst, BitsPerLong);
6631 __ bind(done);
6632 %}
6633 ins_pipe(ialu_reg);
6634 %}
6635
6636
6637 //---------- Population Count Instructions -------------------------------------
6638
6639 instruct popCountI(rRegI dst, rRegI src, rFlagsReg cr) %{
6640 predicate(UsePopCountInstruction);
6641 match(Set dst (PopCountI src));
6642 effect(KILL cr);
6643
6644 format %{ "popcnt $dst, $src" %}
6645 ins_encode %{
6646 __ popcntl($dst$$Register, $src$$Register);
6647 %}
6648 ins_pipe(ialu_reg);
6649 %}
6650
6651 instruct popCountI_mem(rRegI dst, memory mem, rFlagsReg cr) %{
6652 predicate(UsePopCountInstruction);
6653 match(Set dst (PopCountI (LoadI mem)));
6654 effect(KILL cr);
6655
6656 format %{ "popcnt $dst, $mem" %}
6657 ins_encode %{
6658 __ popcntl($dst$$Register, $mem$$Address);
6659 %}
6660 ins_pipe(ialu_reg);
6661 %}
6662
6663 // Note: Long.bitCount(long) returns an int.
6664 instruct popCountL(rRegI dst, rRegL src, rFlagsReg cr) %{
6665 predicate(UsePopCountInstruction);
6666 match(Set dst (PopCountL src));
6667 effect(KILL cr);
6668
6669 format %{ "popcnt $dst, $src" %}
6670 ins_encode %{
6671 __ popcntq($dst$$Register, $src$$Register);
6672 %}
6673 ins_pipe(ialu_reg);
6674 %}
6675
6676 // Note: Long.bitCount(long) returns an int.
6677 instruct popCountL_mem(rRegI dst, memory mem, rFlagsReg cr) %{
6678 predicate(UsePopCountInstruction);
6679 match(Set dst (PopCountL (LoadL mem)));
6680 effect(KILL cr);
6681
6682 format %{ "popcnt $dst, $mem" %}
6683 ins_encode %{
6684 __ popcntq($dst$$Register, $mem$$Address);
6685 %}
6686 ins_pipe(ialu_reg);
6687 %}
6688
6689
6690 //----------MemBar Instructions-----------------------------------------------
6691 // Memory barrier flavors
6692
6693 instruct membar_acquire()
6694 %{
6695 match(MemBarAcquire);
6696 match(LoadFence);
6697 ins_cost(0);
6698
6699 size(0);
6700 format %{ "MEMBAR-acquire ! (empty encoding)" %}
6701 ins_encode();
6702 ins_pipe(empty);
6703 %}
6704
6705 instruct membar_acquire_lock()
6706 %{
6707 match(MemBarAcquireLock);
6708 ins_cost(0);
6709
6710 size(0);
6711 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %}
6712 ins_encode();
6713 ins_pipe(empty);
6714 %}
6715
6716 instruct membar_release()
6717 %{
6718 match(MemBarRelease);
6719 match(StoreFence);
6720 ins_cost(0);
6721
6722 size(0);
6723 format %{ "MEMBAR-release ! (empty encoding)" %}
6724 ins_encode();
6725 ins_pipe(empty);
6726 %}
6727
6728 instruct membar_release_lock()
6729 %{
6730 match(MemBarReleaseLock);
6731 ins_cost(0);
6732
6733 size(0);
6734 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %}
6735 ins_encode();
6736 ins_pipe(empty);
6737 %}
6738
6739 instruct membar_volatile(rFlagsReg cr) %{
6740 match(MemBarVolatile);
6741 effect(KILL cr);
6742 ins_cost(400);
6743
6744 format %{
6745 $$template
6746 $$emit$$"lock addl [rsp + #0], 0\t! membar_volatile"
6747 %}
6748 ins_encode %{
6749 __ membar(Assembler::StoreLoad);
6750 %}
6751 ins_pipe(pipe_slow);
6752 %}
6753
6754 instruct unnecessary_membar_volatile()
6755 %{
6756 match(MemBarVolatile);
6757 predicate(Matcher::post_store_load_barrier(n));
6758 ins_cost(0);
6759
6760 size(0);
6761 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %}
6762 ins_encode();
6763 ins_pipe(empty);
6764 %}
6765
6766 instruct membar_storestore() %{
6767 match(MemBarStoreStore);
6768 match(StoreStoreFence);
6769 ins_cost(0);
6770
6771 size(0);
6772 format %{ "MEMBAR-storestore (empty encoding)" %}
6773 ins_encode( );
6774 ins_pipe(empty);
6775 %}
6776
6777 //----------Move Instructions--------------------------------------------------
6778
6779 instruct castX2P(rRegP dst, rRegL src)
6780 %{
6781 match(Set dst (CastX2P src));
6782
6783 format %{ "movq $dst, $src\t# long->ptr" %}
6784 ins_encode %{
6785 if ($dst$$reg != $src$$reg) {
6786 __ movptr($dst$$Register, $src$$Register);
6787 }
6788 %}
6789 ins_pipe(ialu_reg_reg); // XXX
6790 %}
6791
6792 instruct castP2X(rRegL dst, rRegP src)
6793 %{
6794 match(Set dst (CastP2X src));
6795
6796 format %{ "movq $dst, $src\t# ptr -> long" %}
6797 ins_encode %{
6798 if ($dst$$reg != $src$$reg) {
6799 __ movptr($dst$$Register, $src$$Register);
6800 }
6801 %}
6802 ins_pipe(ialu_reg_reg); // XXX
6803 %}
6804
6805 // Convert oop into int for vectors alignment masking
6806 instruct convP2I(rRegI dst, rRegP src)
6807 %{
6808 match(Set dst (ConvL2I (CastP2X src)));
6809
6810 format %{ "movl $dst, $src\t# ptr -> int" %}
6811 ins_encode %{
6812 __ movl($dst$$Register, $src$$Register);
6813 %}
6814 ins_pipe(ialu_reg_reg); // XXX
6815 %}
6816
6817 // Convert compressed oop into int for vectors alignment masking
6818 // in case of 32bit oops (heap < 4Gb).
6819 instruct convN2I(rRegI dst, rRegN src)
6820 %{
6821 predicate(CompressedOops::shift() == 0);
6822 match(Set dst (ConvL2I (CastP2X (DecodeN src))));
6823
6824 format %{ "movl $dst, $src\t# compressed ptr -> int" %}
6825 ins_encode %{
6826 __ movl($dst$$Register, $src$$Register);
6827 %}
6828 ins_pipe(ialu_reg_reg); // XXX
6829 %}
6830
6831 // Convert oop pointer into compressed form
6832 instruct encodeHeapOop(rRegN dst, rRegP src, rFlagsReg cr) %{
6833 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
6834 match(Set dst (EncodeP src));
6835 effect(KILL cr);
6836 format %{ "encode_heap_oop $dst,$src" %}
6837 ins_encode %{
6838 Register s = $src$$Register;
6839 Register d = $dst$$Register;
6840 if (s != d) {
6841 __ movq(d, s);
6842 }
6843 __ encode_heap_oop(d);
6844 %}
6845 ins_pipe(ialu_reg_long);
6846 %}
6847
6848 instruct encodeHeapOop_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{
6849 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
6850 match(Set dst (EncodeP src));
6851 effect(KILL cr);
6852 format %{ "encode_heap_oop_not_null $dst,$src" %}
6853 ins_encode %{
6854 __ encode_heap_oop_not_null($dst$$Register, $src$$Register);
6855 %}
6856 ins_pipe(ialu_reg_long);
6857 %}
6858
6859 instruct decodeHeapOop(rRegP dst, rRegN src, rFlagsReg cr) %{
6860 predicate(n->bottom_type()->is_ptr()->ptr() != TypePtr::NotNull &&
6861 n->bottom_type()->is_ptr()->ptr() != TypePtr::Constant);
6862 match(Set dst (DecodeN src));
6863 effect(KILL cr);
6864 format %{ "decode_heap_oop $dst,$src" %}
6865 ins_encode %{
6866 Register s = $src$$Register;
6867 Register d = $dst$$Register;
6868 if (s != d) {
6869 __ movq(d, s);
6870 }
6871 __ decode_heap_oop(d);
6872 %}
6873 ins_pipe(ialu_reg_long);
6874 %}
6875
6876 instruct decodeHeapOop_not_null(rRegP dst, rRegN src, rFlagsReg cr) %{
6877 predicate(n->bottom_type()->is_ptr()->ptr() == TypePtr::NotNull ||
6878 n->bottom_type()->is_ptr()->ptr() == TypePtr::Constant);
6879 match(Set dst (DecodeN src));
6880 effect(KILL cr);
6881 format %{ "decode_heap_oop_not_null $dst,$src" %}
6882 ins_encode %{
6883 Register s = $src$$Register;
6884 Register d = $dst$$Register;
6885 if (s != d) {
6886 __ decode_heap_oop_not_null(d, s);
6887 } else {
6888 __ decode_heap_oop_not_null(d);
6889 }
6890 %}
6891 ins_pipe(ialu_reg_long);
6892 %}
6893
6894 instruct encodeKlass_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{
6895 match(Set dst (EncodePKlass src));
6896 effect(TEMP dst, KILL cr);
6897 format %{ "encode_and_move_klass_not_null $dst,$src" %}
6898 ins_encode %{
6899 __ encode_and_move_klass_not_null($dst$$Register, $src$$Register);
6900 %}
6901 ins_pipe(ialu_reg_long);
6902 %}
6903
6904 instruct decodeKlass_not_null(rRegP dst, rRegN src, rFlagsReg cr) %{
6905 match(Set dst (DecodeNKlass src));
6906 effect(TEMP dst, KILL cr);
6907 format %{ "decode_and_move_klass_not_null $dst,$src" %}
6908 ins_encode %{
6909 __ decode_and_move_klass_not_null($dst$$Register, $src$$Register);
6910 %}
6911 ins_pipe(ialu_reg_long);
6912 %}
6913
6914 //----------Conditional Move---------------------------------------------------
6915 // Jump
6916 // dummy instruction for generating temp registers
6917 instruct jumpXtnd_offset(rRegL switch_val, immI2 shift, rRegI dest) %{
6918 match(Jump (LShiftL switch_val shift));
6919 ins_cost(350);
6920 predicate(false);
6921 effect(TEMP dest);
6922
6923 format %{ "leaq $dest, [$constantaddress]\n\t"
6924 "jmp [$dest + $switch_val << $shift]\n\t" %}
6925 ins_encode %{
6926 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
6927 // to do that and the compiler is using that register as one it can allocate.
6928 // So we build it all by hand.
6929 // Address index(noreg, switch_reg, (Address::ScaleFactor)$shift$$constant);
6930 // ArrayAddress dispatch(table, index);
6931 Address dispatch($dest$$Register, $switch_val$$Register, (Address::ScaleFactor) $shift$$constant);
6932 __ lea($dest$$Register, $constantaddress);
6933 __ jmp(dispatch);
6934 %}
6935 ins_pipe(pipe_jmp);
6936 %}
6937
6938 instruct jumpXtnd_addr(rRegL switch_val, immI2 shift, immL32 offset, rRegI dest) %{
6939 match(Jump (AddL (LShiftL switch_val shift) offset));
6940 ins_cost(350);
6941 effect(TEMP dest);
6942
6943 format %{ "leaq $dest, [$constantaddress]\n\t"
6944 "jmp [$dest + $switch_val << $shift + $offset]\n\t" %}
6945 ins_encode %{
6946 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
6947 // to do that and the compiler is using that register as one it can allocate.
6948 // So we build it all by hand.
6949 // Address index(noreg, switch_reg, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant);
6950 // ArrayAddress dispatch(table, index);
6951 Address dispatch($dest$$Register, $switch_val$$Register, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant);
6952 __ lea($dest$$Register, $constantaddress);
6953 __ jmp(dispatch);
6954 %}
6955 ins_pipe(pipe_jmp);
6956 %}
6957
6958 instruct jumpXtnd(rRegL switch_val, rRegI dest) %{
6959 match(Jump switch_val);
6960 ins_cost(350);
6961 effect(TEMP dest);
6962
6963 format %{ "leaq $dest, [$constantaddress]\n\t"
6964 "jmp [$dest + $switch_val]\n\t" %}
6965 ins_encode %{
6966 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
6967 // to do that and the compiler is using that register as one it can allocate.
6968 // So we build it all by hand.
6969 // Address index(noreg, switch_reg, Address::times_1);
6970 // ArrayAddress dispatch(table, index);
6971 Address dispatch($dest$$Register, $switch_val$$Register, Address::times_1);
6972 __ lea($dest$$Register, $constantaddress);
6973 __ jmp(dispatch);
6974 %}
6975 ins_pipe(pipe_jmp);
6976 %}
6977
6978 // Conditional move
6979 instruct cmovI_reg(rRegI dst, rRegI src, rFlagsReg cr, cmpOp cop)
6980 %{
6981 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6982
6983 ins_cost(200); // XXX
6984 format %{ "cmovl$cop $dst, $src\t# signed, int" %}
6985 ins_encode %{
6986 __ cmovl((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Register);
6987 %}
6988 ins_pipe(pipe_cmov_reg);
6989 %}
6990
6991 instruct cmovI_regU(cmpOpU cop, rFlagsRegU cr, rRegI dst, rRegI src) %{
6992 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6993
6994 ins_cost(200); // XXX
6995 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %}
6996 ins_encode %{
6997 __ cmovl((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Register);
6998 %}
6999 ins_pipe(pipe_cmov_reg);
7000 %}
7001
7002 instruct cmovI_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, rRegI src) %{
7003 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7004 ins_cost(200);
7005 expand %{
7006 cmovI_regU(cop, cr, dst, src);
7007 %}
7008 %}
7009
7010 // Conditional move
7011 instruct cmovI_mem(cmpOp cop, rFlagsReg cr, rRegI dst, memory src) %{
7012 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7013
7014 ins_cost(250); // XXX
7015 format %{ "cmovl$cop $dst, $src\t# signed, int" %}
7016 ins_encode %{
7017 __ cmovl((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Address);
7018 %}
7019 ins_pipe(pipe_cmov_mem);
7020 %}
7021
7022 // Conditional move
7023 instruct cmovI_memU(cmpOpU cop, rFlagsRegU cr, rRegI dst, memory src)
7024 %{
7025 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7026
7027 ins_cost(250); // XXX
7028 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %}
7029 ins_encode %{
7030 __ cmovl((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Address);
7031 %}
7032 ins_pipe(pipe_cmov_mem);
7033 %}
7034
7035 instruct cmovI_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, memory src) %{
7036 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7037 ins_cost(250);
7038 expand %{
7039 cmovI_memU(cop, cr, dst, src);
7040 %}
7041 %}
7042
7043 // Conditional move
7044 instruct cmovN_reg(rRegN dst, rRegN src, rFlagsReg cr, cmpOp cop)
7045 %{
7046 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
7047
7048 ins_cost(200); // XXX
7049 format %{ "cmovl$cop $dst, $src\t# signed, compressed ptr" %}
7050 ins_encode %{
7051 __ cmovl((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Register);
7052 %}
7053 ins_pipe(pipe_cmov_reg);
7054 %}
7055
7056 // Conditional move
7057 instruct cmovN_regU(cmpOpU cop, rFlagsRegU cr, rRegN dst, rRegN src)
7058 %{
7059 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
7060
7061 ins_cost(200); // XXX
7062 format %{ "cmovl$cop $dst, $src\t# unsigned, compressed ptr" %}
7063 ins_encode %{
7064 __ cmovl((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Register);
7065 %}
7066 ins_pipe(pipe_cmov_reg);
7067 %}
7068
7069 instruct cmovN_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegN dst, rRegN src) %{
7070 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
7071 ins_cost(200);
7072 expand %{
7073 cmovN_regU(cop, cr, dst, src);
7074 %}
7075 %}
7076
7077 // Conditional move
7078 instruct cmovP_reg(rRegP dst, rRegP src, rFlagsReg cr, cmpOp cop)
7079 %{
7080 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7081
7082 ins_cost(200); // XXX
7083 format %{ "cmovq$cop $dst, $src\t# signed, ptr" %}
7084 ins_encode %{
7085 __ cmovq((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Register);
7086 %}
7087 ins_pipe(pipe_cmov_reg); // XXX
7088 %}
7089
7090 // Conditional move
7091 instruct cmovP_regU(cmpOpU cop, rFlagsRegU cr, rRegP dst, rRegP src)
7092 %{
7093 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7094
7095 ins_cost(200); // XXX
7096 format %{ "cmovq$cop $dst, $src\t# unsigned, ptr" %}
7097 ins_encode %{
7098 __ cmovq((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Register);
7099 %}
7100 ins_pipe(pipe_cmov_reg); // XXX
7101 %}
7102
7103 instruct cmovP_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegP dst, rRegP src) %{
7104 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7105 ins_cost(200);
7106 expand %{
7107 cmovP_regU(cop, cr, dst, src);
7108 %}
7109 %}
7110
7111 // DISABLED: Requires the ADLC to emit a bottom_type call that
7112 // correctly meets the two pointer arguments; one is an incoming
7113 // register but the other is a memory operand. ALSO appears to
7114 // be buggy with implicit null checks.
7115 //
7116 //// Conditional move
7117 //instruct cmovP_mem(cmpOp cop, rFlagsReg cr, rRegP dst, memory src)
7118 //%{
7119 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
7120 // ins_cost(250);
7121 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
7122 // opcode(0x0F,0x40);
7123 // ins_encode( enc_cmov(cop), reg_mem( dst, src ) );
7124 // ins_pipe( pipe_cmov_mem );
7125 //%}
7126 //
7127 //// Conditional move
7128 //instruct cmovP_memU(cmpOpU cop, rFlagsRegU cr, rRegP dst, memory src)
7129 //%{
7130 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
7131 // ins_cost(250);
7132 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
7133 // opcode(0x0F,0x40);
7134 // ins_encode( enc_cmov(cop), reg_mem( dst, src ) );
7135 // ins_pipe( pipe_cmov_mem );
7136 //%}
7137
7138 instruct cmovL_reg(cmpOp cop, rFlagsReg cr, rRegL dst, rRegL src)
7139 %{
7140 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7141
7142 ins_cost(200); // XXX
7143 format %{ "cmovq$cop $dst, $src\t# signed, long" %}
7144 ins_encode %{
7145 __ cmovq((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Register);
7146 %}
7147 ins_pipe(pipe_cmov_reg); // XXX
7148 %}
7149
7150 instruct cmovL_mem(cmpOp cop, rFlagsReg cr, rRegL dst, memory src)
7151 %{
7152 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
7153
7154 ins_cost(200); // XXX
7155 format %{ "cmovq$cop $dst, $src\t# signed, long" %}
7156 ins_encode %{
7157 __ cmovq((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Address);
7158 %}
7159 ins_pipe(pipe_cmov_mem); // XXX
7160 %}
7161
7162 instruct cmovL_regU(cmpOpU cop, rFlagsRegU cr, rRegL dst, rRegL src)
7163 %{
7164 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7165
7166 ins_cost(200); // XXX
7167 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %}
7168 ins_encode %{
7169 __ cmovq((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Register);
7170 %}
7171 ins_pipe(pipe_cmov_reg); // XXX
7172 %}
7173
7174 instruct cmovL_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, rRegL src) %{
7175 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7176 ins_cost(200);
7177 expand %{
7178 cmovL_regU(cop, cr, dst, src);
7179 %}
7180 %}
7181
7182 instruct cmovL_memU(cmpOpU cop, rFlagsRegU cr, rRegL dst, memory src)
7183 %{
7184 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
7185
7186 ins_cost(200); // XXX
7187 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %}
7188 ins_encode %{
7189 __ cmovq((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Address);
7190 %}
7191 ins_pipe(pipe_cmov_mem); // XXX
7192 %}
7193
7194 instruct cmovL_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, memory src) %{
7195 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
7196 ins_cost(200);
7197 expand %{
7198 cmovL_memU(cop, cr, dst, src);
7199 %}
7200 %}
7201
7202 instruct cmovF_reg(cmpOp cop, rFlagsReg cr, regF dst, regF src)
7203 %{
7204 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7205
7206 ins_cost(200); // XXX
7207 format %{ "jn$cop skip\t# signed cmove float\n\t"
7208 "movss $dst, $src\n"
7209 "skip:" %}
7210 ins_encode %{
7211 Label Lskip;
7212 // Invert sense of branch from sense of CMOV
7213 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7214 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
7215 __ bind(Lskip);
7216 %}
7217 ins_pipe(pipe_slow);
7218 %}
7219
7220 // instruct cmovF_mem(cmpOp cop, rFlagsReg cr, regF dst, memory src)
7221 // %{
7222 // match(Set dst (CMoveF (Binary cop cr) (Binary dst (LoadL src))));
7223
7224 // ins_cost(200); // XXX
7225 // format %{ "jn$cop skip\t# signed cmove float\n\t"
7226 // "movss $dst, $src\n"
7227 // "skip:" %}
7228 // ins_encode(enc_cmovf_mem_branch(cop, dst, src));
7229 // ins_pipe(pipe_slow);
7230 // %}
7231
7232 instruct cmovF_regU(cmpOpU cop, rFlagsRegU cr, regF dst, regF src)
7233 %{
7234 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7235
7236 ins_cost(200); // XXX
7237 format %{ "jn$cop skip\t# unsigned cmove float\n\t"
7238 "movss $dst, $src\n"
7239 "skip:" %}
7240 ins_encode %{
7241 Label Lskip;
7242 // Invert sense of branch from sense of CMOV
7243 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7244 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
7245 __ bind(Lskip);
7246 %}
7247 ins_pipe(pipe_slow);
7248 %}
7249
7250 instruct cmovF_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regF dst, regF src) %{
7251 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7252 ins_cost(200);
7253 expand %{
7254 cmovF_regU(cop, cr, dst, src);
7255 %}
7256 %}
7257
7258 instruct cmovD_reg(cmpOp cop, rFlagsReg cr, regD dst, regD src)
7259 %{
7260 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7261
7262 ins_cost(200); // XXX
7263 format %{ "jn$cop skip\t# signed cmove double\n\t"
7264 "movsd $dst, $src\n"
7265 "skip:" %}
7266 ins_encode %{
7267 Label Lskip;
7268 // Invert sense of branch from sense of CMOV
7269 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7270 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
7271 __ bind(Lskip);
7272 %}
7273 ins_pipe(pipe_slow);
7274 %}
7275
7276 instruct cmovD_regU(cmpOpU cop, rFlagsRegU cr, regD dst, regD src)
7277 %{
7278 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7279
7280 ins_cost(200); // XXX
7281 format %{ "jn$cop skip\t# unsigned cmove double\n\t"
7282 "movsd $dst, $src\n"
7283 "skip:" %}
7284 ins_encode %{
7285 Label Lskip;
7286 // Invert sense of branch from sense of CMOV
7287 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7288 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
7289 __ bind(Lskip);
7290 %}
7291 ins_pipe(pipe_slow);
7292 %}
7293
7294 instruct cmovD_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regD dst, regD src) %{
7295 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7296 ins_cost(200);
7297 expand %{
7298 cmovD_regU(cop, cr, dst, src);
7299 %}
7300 %}
7301
7302 //----------Arithmetic Instructions--------------------------------------------
7303 //----------Addition Instructions----------------------------------------------
7304
7305 instruct addI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
7306 %{
7307 match(Set dst (AddI dst src));
7308 effect(KILL cr);
7309
7310 format %{ "addl $dst, $src\t# int" %}
7311 ins_encode %{
7312 __ addl($dst$$Register, $src$$Register);
7313 %}
7314 ins_pipe(ialu_reg_reg);
7315 %}
7316
7317 instruct addI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
7318 %{
7319 match(Set dst (AddI dst src));
7320 effect(KILL cr);
7321
7322 format %{ "addl $dst, $src\t# int" %}
7323 ins_encode %{
7324 __ addl($dst$$Register, $src$$constant);
7325 %}
7326 ins_pipe( ialu_reg );
7327 %}
7328
7329 instruct addI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
7330 %{
7331 match(Set dst (AddI dst (LoadI src)));
7332 effect(KILL cr);
7333
7334 ins_cost(125); // XXX
7335 format %{ "addl $dst, $src\t# int" %}
7336 ins_encode %{
7337 __ addl($dst$$Register, $src$$Address);
7338 %}
7339 ins_pipe(ialu_reg_mem);
7340 %}
7341
7342 instruct addI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
7343 %{
7344 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7345 effect(KILL cr);
7346
7347 ins_cost(150); // XXX
7348 format %{ "addl $dst, $src\t# int" %}
7349 ins_encode %{
7350 __ addl($dst$$Address, $src$$Register);
7351 %}
7352 ins_pipe(ialu_mem_reg);
7353 %}
7354
7355 instruct addI_mem_imm(memory dst, immI src, rFlagsReg cr)
7356 %{
7357 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7358 effect(KILL cr);
7359
7360 ins_cost(125); // XXX
7361 format %{ "addl $dst, $src\t# int" %}
7362 ins_encode %{
7363 __ addl($dst$$Address, $src$$constant);
7364 %}
7365 ins_pipe(ialu_mem_imm);
7366 %}
7367
7368 instruct incI_rReg(rRegI dst, immI_1 src, rFlagsReg cr)
7369 %{
7370 predicate(UseIncDec);
7371 match(Set dst (AddI dst src));
7372 effect(KILL cr);
7373
7374 format %{ "incl $dst\t# int" %}
7375 ins_encode %{
7376 __ incrementl($dst$$Register);
7377 %}
7378 ins_pipe(ialu_reg);
7379 %}
7380
7381 instruct incI_mem(memory dst, immI_1 src, rFlagsReg cr)
7382 %{
7383 predicate(UseIncDec);
7384 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7385 effect(KILL cr);
7386
7387 ins_cost(125); // XXX
7388 format %{ "incl $dst\t# int" %}
7389 ins_encode %{
7390 __ incrementl($dst$$Address);
7391 %}
7392 ins_pipe(ialu_mem_imm);
7393 %}
7394
7395 // XXX why does that use AddI
7396 instruct decI_rReg(rRegI dst, immI_M1 src, rFlagsReg cr)
7397 %{
7398 predicate(UseIncDec);
7399 match(Set dst (AddI dst src));
7400 effect(KILL cr);
7401
7402 format %{ "decl $dst\t# int" %}
7403 ins_encode %{
7404 __ decrementl($dst$$Register);
7405 %}
7406 ins_pipe(ialu_reg);
7407 %}
7408
7409 // XXX why does that use AddI
7410 instruct decI_mem(memory dst, immI_M1 src, rFlagsReg cr)
7411 %{
7412 predicate(UseIncDec);
7413 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7414 effect(KILL cr);
7415
7416 ins_cost(125); // XXX
7417 format %{ "decl $dst\t# int" %}
7418 ins_encode %{
7419 __ decrementl($dst$$Address);
7420 %}
7421 ins_pipe(ialu_mem_imm);
7422 %}
7423
7424 instruct leaI_rReg_immI(rRegI dst, rRegI src0, immI src1)
7425 %{
7426 match(Set dst (AddI src0 src1));
7427
7428 ins_cost(110);
7429 format %{ "addr32 leal $dst, [$src0 + $src1]\t# int" %}
7430 ins_encode %{
7431 __ leal($dst$$Register, Address($src0$$Register, $src1$$constant));
7432 %}
7433 ins_pipe(ialu_reg_reg);
7434 %}
7435
7436 instruct addL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
7437 %{
7438 match(Set dst (AddL dst src));
7439 effect(KILL cr);
7440
7441 format %{ "addq $dst, $src\t# long" %}
7442 ins_encode %{
7443 __ addq($dst$$Register, $src$$Register);
7444 %}
7445 ins_pipe(ialu_reg_reg);
7446 %}
7447
7448 instruct addL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
7449 %{
7450 match(Set dst (AddL dst src));
7451 effect(KILL cr);
7452
7453 format %{ "addq $dst, $src\t# long" %}
7454 ins_encode %{
7455 __ addq($dst$$Register, $src$$constant);
7456 %}
7457 ins_pipe( ialu_reg );
7458 %}
7459
7460 instruct addL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
7461 %{
7462 match(Set dst (AddL dst (LoadL src)));
7463 effect(KILL cr);
7464
7465 ins_cost(125); // XXX
7466 format %{ "addq $dst, $src\t# long" %}
7467 ins_encode %{
7468 __ addq($dst$$Register, $src$$Address);
7469 %}
7470 ins_pipe(ialu_reg_mem);
7471 %}
7472
7473 instruct addL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
7474 %{
7475 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7476 effect(KILL cr);
7477
7478 ins_cost(150); // XXX
7479 format %{ "addq $dst, $src\t# long" %}
7480 ins_encode %{
7481 __ addq($dst$$Address, $src$$Register);
7482 %}
7483 ins_pipe(ialu_mem_reg);
7484 %}
7485
7486 instruct addL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
7487 %{
7488 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7489 effect(KILL cr);
7490
7491 ins_cost(125); // XXX
7492 format %{ "addq $dst, $src\t# long" %}
7493 ins_encode %{
7494 __ addq($dst$$Address, $src$$constant);
7495 %}
7496 ins_pipe(ialu_mem_imm);
7497 %}
7498
7499 instruct incL_rReg(rRegI dst, immL1 src, rFlagsReg cr)
7500 %{
7501 predicate(UseIncDec);
7502 match(Set dst (AddL dst src));
7503 effect(KILL cr);
7504
7505 format %{ "incq $dst\t# long" %}
7506 ins_encode %{
7507 __ incrementq($dst$$Register);
7508 %}
7509 ins_pipe(ialu_reg);
7510 %}
7511
7512 instruct incL_mem(memory dst, immL1 src, rFlagsReg cr)
7513 %{
7514 predicate(UseIncDec);
7515 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7516 effect(KILL cr);
7517
7518 ins_cost(125); // XXX
7519 format %{ "incq $dst\t# long" %}
7520 ins_encode %{
7521 __ incrementq($dst$$Address);
7522 %}
7523 ins_pipe(ialu_mem_imm);
7524 %}
7525
7526 // XXX why does that use AddL
7527 instruct decL_rReg(rRegL dst, immL_M1 src, rFlagsReg cr)
7528 %{
7529 predicate(UseIncDec);
7530 match(Set dst (AddL dst src));
7531 effect(KILL cr);
7532
7533 format %{ "decq $dst\t# long" %}
7534 ins_encode %{
7535 __ decrementq($dst$$Register);
7536 %}
7537 ins_pipe(ialu_reg);
7538 %}
7539
7540 // XXX why does that use AddL
7541 instruct decL_mem(memory dst, immL_M1 src, rFlagsReg cr)
7542 %{
7543 predicate(UseIncDec);
7544 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7545 effect(KILL cr);
7546
7547 ins_cost(125); // XXX
7548 format %{ "decq $dst\t# long" %}
7549 ins_encode %{
7550 __ decrementq($dst$$Address);
7551 %}
7552 ins_pipe(ialu_mem_imm);
7553 %}
7554
7555 instruct leaL_rReg_immL(rRegL dst, rRegL src0, immL32 src1)
7556 %{
7557 match(Set dst (AddL src0 src1));
7558
7559 ins_cost(110);
7560 format %{ "leaq $dst, [$src0 + $src1]\t# long" %}
7561 ins_encode %{
7562 __ leaq($dst$$Register, Address($src0$$Register, $src1$$constant));
7563 %}
7564 ins_pipe(ialu_reg_reg);
7565 %}
7566
7567 instruct addP_rReg(rRegP dst, rRegL src, rFlagsReg cr)
7568 %{
7569 match(Set dst (AddP dst src));
7570 effect(KILL cr);
7571
7572 format %{ "addq $dst, $src\t# ptr" %}
7573 ins_encode %{
7574 __ addq($dst$$Register, $src$$Register);
7575 %}
7576 ins_pipe(ialu_reg_reg);
7577 %}
7578
7579 instruct addP_rReg_imm(rRegP dst, immL32 src, rFlagsReg cr)
7580 %{
7581 match(Set dst (AddP dst src));
7582 effect(KILL cr);
7583
7584 format %{ "addq $dst, $src\t# ptr" %}
7585 ins_encode %{
7586 __ addq($dst$$Register, $src$$constant);
7587 %}
7588 ins_pipe( ialu_reg );
7589 %}
7590
7591 // XXX addP mem ops ????
7592
7593 instruct leaP_rReg_imm(rRegP dst, rRegP src0, immL32 src1)
7594 %{
7595 match(Set dst (AddP src0 src1));
7596
7597 ins_cost(110);
7598 format %{ "leaq $dst, [$src0 + $src1]\t# ptr" %}
7599 ins_encode %{
7600 __ leaq($dst$$Register, Address($src0$$Register, $src1$$constant));
7601 %}
7602 ins_pipe(ialu_reg_reg);
7603 %}
7604
7605 instruct checkCastPP(rRegP dst)
7606 %{
7607 match(Set dst (CheckCastPP dst));
7608
7609 size(0);
7610 format %{ "# checkcastPP of $dst" %}
7611 ins_encode(/* empty encoding */);
7612 ins_pipe(empty);
7613 %}
7614
7615 instruct castPP(rRegP dst)
7616 %{
7617 match(Set dst (CastPP dst));
7618
7619 size(0);
7620 format %{ "# castPP of $dst" %}
7621 ins_encode(/* empty encoding */);
7622 ins_pipe(empty);
7623 %}
7624
7625 instruct castII(rRegI dst)
7626 %{
7627 match(Set dst (CastII dst));
7628
7629 size(0);
7630 format %{ "# castII of $dst" %}
7631 ins_encode(/* empty encoding */);
7632 ins_cost(0);
7633 ins_pipe(empty);
7634 %}
7635
7636 instruct castLL(rRegL dst)
7637 %{
7638 match(Set dst (CastLL dst));
7639
7640 size(0);
7641 format %{ "# castLL of $dst" %}
7642 ins_encode(/* empty encoding */);
7643 ins_cost(0);
7644 ins_pipe(empty);
7645 %}
7646
7647 instruct castFF(regF dst)
7648 %{
7649 match(Set dst (CastFF dst));
7650
7651 size(0);
7652 format %{ "# castFF of $dst" %}
7653 ins_encode(/* empty encoding */);
7654 ins_cost(0);
7655 ins_pipe(empty);
7656 %}
7657
7658 instruct castDD(regD dst)
7659 %{
7660 match(Set dst (CastDD dst));
7661
7662 size(0);
7663 format %{ "# castDD of $dst" %}
7664 ins_encode(/* empty encoding */);
7665 ins_cost(0);
7666 ins_pipe(empty);
7667 %}
7668
7669 // LoadP-locked same as a regular LoadP when used with compare-swap
7670 instruct loadPLocked(rRegP dst, memory mem)
7671 %{
7672 match(Set dst (LoadPLocked mem));
7673
7674 ins_cost(125); // XXX
7675 format %{ "movq $dst, $mem\t# ptr locked" %}
7676 ins_encode %{
7677 __ movq($dst$$Register, $mem$$Address);
7678 %}
7679 ins_pipe(ialu_reg_mem); // XXX
7680 %}
7681
7682 // Conditional-store of the updated heap-top.
7683 // Used during allocation of the shared heap.
7684 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel.
7685
7686 instruct storePConditional(memory heap_top_ptr,
7687 rax_RegP oldval, rRegP newval,
7688 rFlagsReg cr)
7689 %{
7690 predicate(n->as_LoadStore()->barrier_data() == 0);
7691 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval)));
7692
7693 format %{ "cmpxchgq $heap_top_ptr, $newval\t# (ptr) "
7694 "If rax == $heap_top_ptr then store $newval into $heap_top_ptr" %}
7695 ins_encode %{
7696 __ lock();
7697 __ cmpxchgq($newval$$Register, $heap_top_ptr$$Address);
7698 %}
7699 ins_pipe(pipe_cmpxchg);
7700 %}
7701
7702 // Conditional-store of an int value.
7703 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG.
7704 instruct storeIConditional(memory mem, rax_RegI oldval, rRegI newval, rFlagsReg cr)
7705 %{
7706 match(Set cr (StoreIConditional mem (Binary oldval newval)));
7707 effect(KILL oldval);
7708
7709 format %{ "cmpxchgl $mem, $newval\t# If rax == $mem then store $newval into $mem" %}
7710 opcode(0x0F, 0xB1);
7711 ins_encode(lock_prefix,
7712 REX_reg_mem(newval, mem),
7713 OpcP, OpcS,
7714 reg_mem(newval, mem));
7715 ins_pipe(pipe_cmpxchg);
7716 %}
7717
7718 // Conditional-store of a long value.
7719 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG.
7720 instruct storeLConditional(memory mem, rax_RegL oldval, rRegL newval, rFlagsReg cr)
7721 %{
7722 match(Set cr (StoreLConditional mem (Binary oldval newval)));
7723 effect(KILL oldval);
7724
7725 format %{ "cmpxchgq $mem, $newval\t# If rax == $mem then store $newval into $mem" %}
7726 ins_encode %{
7727 __ lock();
7728 __ cmpxchgq($newval$$Register, $mem$$Address);
7729 %}
7730 ins_pipe(pipe_cmpxchg);
7731 %}
7732
7733
7734 // XXX No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7735 instruct compareAndSwapP(rRegI res,
7736 memory mem_ptr,
7737 rax_RegP oldval, rRegP newval,
7738 rFlagsReg cr)
7739 %{
7740 predicate(VM_Version::supports_cx8() && n->as_LoadStore()->barrier_data() == 0);
7741 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7742 match(Set res (WeakCompareAndSwapP mem_ptr (Binary oldval newval)));
7743 effect(KILL cr, KILL oldval);
7744
7745 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7746 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7747 "sete $res\n\t"
7748 "movzbl $res, $res" %}
7749 ins_encode %{
7750 __ lock();
7751 __ cmpxchgq($newval$$Register, $mem_ptr$$Address);
7752 __ sete($res$$Register);
7753 __ movzbl($res$$Register, $res$$Register);
7754 %}
7755 ins_pipe( pipe_cmpxchg );
7756 %}
7757
7758 instruct compareAndSwapL(rRegI res,
7759 memory mem_ptr,
7760 rax_RegL oldval, rRegL newval,
7761 rFlagsReg cr)
7762 %{
7763 predicate(VM_Version::supports_cx8());
7764 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7765 match(Set res (WeakCompareAndSwapL mem_ptr (Binary oldval newval)));
7766 effect(KILL cr, KILL oldval);
7767
7768 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7769 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7770 "sete $res\n\t"
7771 "movzbl $res, $res" %}
7772 ins_encode %{
7773 __ lock();
7774 __ cmpxchgq($newval$$Register, $mem_ptr$$Address);
7775 __ sete($res$$Register);
7776 __ movzbl($res$$Register, $res$$Register);
7777 %}
7778 ins_pipe( pipe_cmpxchg );
7779 %}
7780
7781 instruct compareAndSwapI(rRegI res,
7782 memory mem_ptr,
7783 rax_RegI oldval, rRegI newval,
7784 rFlagsReg cr)
7785 %{
7786 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7787 match(Set res (WeakCompareAndSwapI mem_ptr (Binary oldval newval)));
7788 effect(KILL cr, KILL oldval);
7789
7790 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7791 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7792 "sete $res\n\t"
7793 "movzbl $res, $res" %}
7794 ins_encode %{
7795 __ lock();
7796 __ cmpxchgl($newval$$Register, $mem_ptr$$Address);
7797 __ sete($res$$Register);
7798 __ movzbl($res$$Register, $res$$Register);
7799 %}
7800 ins_pipe( pipe_cmpxchg );
7801 %}
7802
7803 instruct compareAndSwapB(rRegI res,
7804 memory mem_ptr,
7805 rax_RegI oldval, rRegI newval,
7806 rFlagsReg cr)
7807 %{
7808 match(Set res (CompareAndSwapB mem_ptr (Binary oldval newval)));
7809 match(Set res (WeakCompareAndSwapB mem_ptr (Binary oldval newval)));
7810 effect(KILL cr, KILL oldval);
7811
7812 format %{ "cmpxchgb $mem_ptr,$newval\t# "
7813 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7814 "sete $res\n\t"
7815 "movzbl $res, $res" %}
7816 ins_encode %{
7817 __ lock();
7818 __ cmpxchgb($newval$$Register, $mem_ptr$$Address);
7819 __ sete($res$$Register);
7820 __ movzbl($res$$Register, $res$$Register);
7821 %}
7822 ins_pipe( pipe_cmpxchg );
7823 %}
7824
7825 instruct compareAndSwapS(rRegI res,
7826 memory mem_ptr,
7827 rax_RegI oldval, rRegI newval,
7828 rFlagsReg cr)
7829 %{
7830 match(Set res (CompareAndSwapS mem_ptr (Binary oldval newval)));
7831 match(Set res (WeakCompareAndSwapS mem_ptr (Binary oldval newval)));
7832 effect(KILL cr, KILL oldval);
7833
7834 format %{ "cmpxchgw $mem_ptr,$newval\t# "
7835 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7836 "sete $res\n\t"
7837 "movzbl $res, $res" %}
7838 ins_encode %{
7839 __ lock();
7840 __ cmpxchgw($newval$$Register, $mem_ptr$$Address);
7841 __ sete($res$$Register);
7842 __ movzbl($res$$Register, $res$$Register);
7843 %}
7844 ins_pipe( pipe_cmpxchg );
7845 %}
7846
7847 instruct compareAndSwapN(rRegI res,
7848 memory mem_ptr,
7849 rax_RegN oldval, rRegN newval,
7850 rFlagsReg cr) %{
7851 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
7852 match(Set res (WeakCompareAndSwapN mem_ptr (Binary oldval newval)));
7853 effect(KILL cr, KILL oldval);
7854
7855 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7856 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7857 "sete $res\n\t"
7858 "movzbl $res, $res" %}
7859 ins_encode %{
7860 __ lock();
7861 __ cmpxchgl($newval$$Register, $mem_ptr$$Address);
7862 __ sete($res$$Register);
7863 __ movzbl($res$$Register, $res$$Register);
7864 %}
7865 ins_pipe( pipe_cmpxchg );
7866 %}
7867
7868 instruct compareAndExchangeB(
7869 memory mem_ptr,
7870 rax_RegI oldval, rRegI newval,
7871 rFlagsReg cr)
7872 %{
7873 match(Set oldval (CompareAndExchangeB mem_ptr (Binary oldval newval)));
7874 effect(KILL cr);
7875
7876 format %{ "cmpxchgb $mem_ptr,$newval\t# "
7877 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7878 ins_encode %{
7879 __ lock();
7880 __ cmpxchgb($newval$$Register, $mem_ptr$$Address);
7881 %}
7882 ins_pipe( pipe_cmpxchg );
7883 %}
7884
7885 instruct compareAndExchangeS(
7886 memory mem_ptr,
7887 rax_RegI oldval, rRegI newval,
7888 rFlagsReg cr)
7889 %{
7890 match(Set oldval (CompareAndExchangeS mem_ptr (Binary oldval newval)));
7891 effect(KILL cr);
7892
7893 format %{ "cmpxchgw $mem_ptr,$newval\t# "
7894 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7895 ins_encode %{
7896 __ lock();
7897 __ cmpxchgw($newval$$Register, $mem_ptr$$Address);
7898 %}
7899 ins_pipe( pipe_cmpxchg );
7900 %}
7901
7902 instruct compareAndExchangeI(
7903 memory mem_ptr,
7904 rax_RegI oldval, rRegI newval,
7905 rFlagsReg cr)
7906 %{
7907 match(Set oldval (CompareAndExchangeI mem_ptr (Binary oldval newval)));
7908 effect(KILL cr);
7909
7910 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7911 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7912 ins_encode %{
7913 __ lock();
7914 __ cmpxchgl($newval$$Register, $mem_ptr$$Address);
7915 %}
7916 ins_pipe( pipe_cmpxchg );
7917 %}
7918
7919 instruct compareAndExchangeL(
7920 memory mem_ptr,
7921 rax_RegL oldval, rRegL newval,
7922 rFlagsReg cr)
7923 %{
7924 predicate(VM_Version::supports_cx8());
7925 match(Set oldval (CompareAndExchangeL mem_ptr (Binary oldval newval)));
7926 effect(KILL cr);
7927
7928 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7929 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7930 ins_encode %{
7931 __ lock();
7932 __ cmpxchgq($newval$$Register, $mem_ptr$$Address);
7933 %}
7934 ins_pipe( pipe_cmpxchg );
7935 %}
7936
7937 instruct compareAndExchangeN(
7938 memory mem_ptr,
7939 rax_RegN oldval, rRegN newval,
7940 rFlagsReg cr) %{
7941 match(Set oldval (CompareAndExchangeN mem_ptr (Binary oldval newval)));
7942 effect(KILL cr);
7943
7944 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7945 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7946 ins_encode %{
7947 __ lock();
7948 __ cmpxchgl($newval$$Register, $mem_ptr$$Address);
7949 %}
7950 ins_pipe( pipe_cmpxchg );
7951 %}
7952
7953 instruct compareAndExchangeP(
7954 memory mem_ptr,
7955 rax_RegP oldval, rRegP newval,
7956 rFlagsReg cr)
7957 %{
7958 predicate(VM_Version::supports_cx8() && n->as_LoadStore()->barrier_data() == 0);
7959 match(Set oldval (CompareAndExchangeP mem_ptr (Binary oldval newval)));
7960 effect(KILL cr);
7961
7962 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7963 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7964 ins_encode %{
7965 __ lock();
7966 __ cmpxchgq($newval$$Register, $mem_ptr$$Address);
7967 %}
7968 ins_pipe( pipe_cmpxchg );
7969 %}
7970
7971 instruct xaddB_no_res( memory mem, Universe dummy, immI add, rFlagsReg cr) %{
7972 predicate(n->as_LoadStore()->result_not_used());
7973 match(Set dummy (GetAndAddB mem add));
7974 effect(KILL cr);
7975 format %{ "ADDB [$mem],$add" %}
7976 ins_encode %{
7977 __ lock();
7978 __ addb($mem$$Address, $add$$constant);
7979 %}
7980 ins_pipe( pipe_cmpxchg );
7981 %}
7982
7983 instruct xaddB( memory mem, rRegI newval, rFlagsReg cr) %{
7984 match(Set newval (GetAndAddB mem newval));
7985 effect(KILL cr);
7986 format %{ "XADDB [$mem],$newval" %}
7987 ins_encode %{
7988 __ lock();
7989 __ xaddb($mem$$Address, $newval$$Register);
7990 %}
7991 ins_pipe( pipe_cmpxchg );
7992 %}
7993
7994 instruct xaddS_no_res( memory mem, Universe dummy, immI add, rFlagsReg cr) %{
7995 predicate(n->as_LoadStore()->result_not_used());
7996 match(Set dummy (GetAndAddS mem add));
7997 effect(KILL cr);
7998 format %{ "ADDW [$mem],$add" %}
7999 ins_encode %{
8000 __ lock();
8001 __ addw($mem$$Address, $add$$constant);
8002 %}
8003 ins_pipe( pipe_cmpxchg );
8004 %}
8005
8006 instruct xaddS( memory mem, rRegI newval, rFlagsReg cr) %{
8007 match(Set newval (GetAndAddS mem newval));
8008 effect(KILL cr);
8009 format %{ "XADDW [$mem],$newval" %}
8010 ins_encode %{
8011 __ lock();
8012 __ xaddw($mem$$Address, $newval$$Register);
8013 %}
8014 ins_pipe( pipe_cmpxchg );
8015 %}
8016
8017 instruct xaddI_no_res( memory mem, Universe dummy, immI add, rFlagsReg cr) %{
8018 predicate(n->as_LoadStore()->result_not_used());
8019 match(Set dummy (GetAndAddI mem add));
8020 effect(KILL cr);
8021 format %{ "ADDL [$mem],$add" %}
8022 ins_encode %{
8023 __ lock();
8024 __ addl($mem$$Address, $add$$constant);
8025 %}
8026 ins_pipe( pipe_cmpxchg );
8027 %}
8028
8029 instruct xaddI( memory mem, rRegI newval, rFlagsReg cr) %{
8030 match(Set newval (GetAndAddI mem newval));
8031 effect(KILL cr);
8032 format %{ "XADDL [$mem],$newval" %}
8033 ins_encode %{
8034 __ lock();
8035 __ xaddl($mem$$Address, $newval$$Register);
8036 %}
8037 ins_pipe( pipe_cmpxchg );
8038 %}
8039
8040 instruct xaddL_no_res( memory mem, Universe dummy, immL32 add, rFlagsReg cr) %{
8041 predicate(n->as_LoadStore()->result_not_used());
8042 match(Set dummy (GetAndAddL mem add));
8043 effect(KILL cr);
8044 format %{ "ADDQ [$mem],$add" %}
8045 ins_encode %{
8046 __ lock();
8047 __ addq($mem$$Address, $add$$constant);
8048 %}
8049 ins_pipe( pipe_cmpxchg );
8050 %}
8051
8052 instruct xaddL( memory mem, rRegL newval, rFlagsReg cr) %{
8053 match(Set newval (GetAndAddL mem newval));
8054 effect(KILL cr);
8055 format %{ "XADDQ [$mem],$newval" %}
8056 ins_encode %{
8057 __ lock();
8058 __ xaddq($mem$$Address, $newval$$Register);
8059 %}
8060 ins_pipe( pipe_cmpxchg );
8061 %}
8062
8063 instruct xchgB( memory mem, rRegI newval) %{
8064 match(Set newval (GetAndSetB mem newval));
8065 format %{ "XCHGB $newval,[$mem]" %}
8066 ins_encode %{
8067 __ xchgb($newval$$Register, $mem$$Address);
8068 %}
8069 ins_pipe( pipe_cmpxchg );
8070 %}
8071
8072 instruct xchgS( memory mem, rRegI newval) %{
8073 match(Set newval (GetAndSetS mem newval));
8074 format %{ "XCHGW $newval,[$mem]" %}
8075 ins_encode %{
8076 __ xchgw($newval$$Register, $mem$$Address);
8077 %}
8078 ins_pipe( pipe_cmpxchg );
8079 %}
8080
8081 instruct xchgI( memory mem, rRegI newval) %{
8082 match(Set newval (GetAndSetI mem newval));
8083 format %{ "XCHGL $newval,[$mem]" %}
8084 ins_encode %{
8085 __ xchgl($newval$$Register, $mem$$Address);
8086 %}
8087 ins_pipe( pipe_cmpxchg );
8088 %}
8089
8090 instruct xchgL( memory mem, rRegL newval) %{
8091 match(Set newval (GetAndSetL mem newval));
8092 format %{ "XCHGL $newval,[$mem]" %}
8093 ins_encode %{
8094 __ xchgq($newval$$Register, $mem$$Address);
8095 %}
8096 ins_pipe( pipe_cmpxchg );
8097 %}
8098
8099 instruct xchgP( memory mem, rRegP newval) %{
8100 match(Set newval (GetAndSetP mem newval));
8101 predicate(n->as_LoadStore()->barrier_data() == 0);
8102 format %{ "XCHGQ $newval,[$mem]" %}
8103 ins_encode %{
8104 __ xchgq($newval$$Register, $mem$$Address);
8105 %}
8106 ins_pipe( pipe_cmpxchg );
8107 %}
8108
8109 instruct xchgN( memory mem, rRegN newval) %{
8110 match(Set newval (GetAndSetN mem newval));
8111 format %{ "XCHGL $newval,$mem]" %}
8112 ins_encode %{
8113 __ xchgl($newval$$Register, $mem$$Address);
8114 %}
8115 ins_pipe( pipe_cmpxchg );
8116 %}
8117
8118 //----------Abs Instructions-------------------------------------------
8119
8120 // Integer Absolute Instructions
8121 instruct absI_rReg(rRegI dst, rRegI src, rRegI tmp, rFlagsReg cr)
8122 %{
8123 match(Set dst (AbsI src));
8124 effect(TEMP dst, TEMP tmp, KILL cr);
8125 format %{ "movl $tmp, $src\n\t"
8126 "sarl $tmp, 31\n\t"
8127 "movl $dst, $src\n\t"
8128 "xorl $dst, $tmp\n\t"
8129 "subl $dst, $tmp\n"
8130 %}
8131 ins_encode %{
8132 __ movl($tmp$$Register, $src$$Register);
8133 __ sarl($tmp$$Register, 31);
8134 __ movl($dst$$Register, $src$$Register);
8135 __ xorl($dst$$Register, $tmp$$Register);
8136 __ subl($dst$$Register, $tmp$$Register);
8137 %}
8138
8139 ins_pipe(ialu_reg_reg);
8140 %}
8141
8142 // Long Absolute Instructions
8143 instruct absL_rReg(rRegL dst, rRegL src, rRegL tmp, rFlagsReg cr)
8144 %{
8145 match(Set dst (AbsL src));
8146 effect(TEMP dst, TEMP tmp, KILL cr);
8147 format %{ "movq $tmp, $src\n\t"
8148 "sarq $tmp, 63\n\t"
8149 "movq $dst, $src\n\t"
8150 "xorq $dst, $tmp\n\t"
8151 "subq $dst, $tmp\n"
8152 %}
8153 ins_encode %{
8154 __ movq($tmp$$Register, $src$$Register);
8155 __ sarq($tmp$$Register, 63);
8156 __ movq($dst$$Register, $src$$Register);
8157 __ xorq($dst$$Register, $tmp$$Register);
8158 __ subq($dst$$Register, $tmp$$Register);
8159 %}
8160
8161 ins_pipe(ialu_reg_reg);
8162 %}
8163
8164 //----------Subtraction Instructions-------------------------------------------
8165
8166 // Integer Subtraction Instructions
8167 instruct subI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
8168 %{
8169 match(Set dst (SubI dst src));
8170 effect(KILL cr);
8171
8172 format %{ "subl $dst, $src\t# int" %}
8173 ins_encode %{
8174 __ subl($dst$$Register, $src$$Register);
8175 %}
8176 ins_pipe(ialu_reg_reg);
8177 %}
8178
8179 instruct subI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
8180 %{
8181 match(Set dst (SubI dst src));
8182 effect(KILL cr);
8183
8184 format %{ "subl $dst, $src\t# int" %}
8185 ins_encode %{
8186 __ subl($dst$$Register, $src$$constant);
8187 %}
8188 ins_pipe(ialu_reg);
8189 %}
8190
8191 instruct subI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
8192 %{
8193 match(Set dst (SubI dst (LoadI src)));
8194 effect(KILL cr);
8195
8196 ins_cost(125);
8197 format %{ "subl $dst, $src\t# int" %}
8198 ins_encode %{
8199 __ subl($dst$$Register, $src$$Address);
8200 %}
8201 ins_pipe(ialu_reg_mem);
8202 %}
8203
8204 instruct subI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
8205 %{
8206 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
8207 effect(KILL cr);
8208
8209 ins_cost(150);
8210 format %{ "subl $dst, $src\t# int" %}
8211 ins_encode %{
8212 __ subl($dst$$Address, $src$$Register);
8213 %}
8214 ins_pipe(ialu_mem_reg);
8215 %}
8216
8217 instruct subI_mem_imm(memory dst, immI src, rFlagsReg cr)
8218 %{
8219 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
8220 effect(KILL cr);
8221
8222 ins_cost(125); // XXX
8223 format %{ "subl $dst, $src\t# int" %}
8224 ins_encode %{
8225 __ subl($dst$$Address, $src$$constant);
8226 %}
8227 ins_pipe(ialu_mem_imm);
8228 %}
8229
8230 instruct subL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
8231 %{
8232 match(Set dst (SubL dst src));
8233 effect(KILL cr);
8234
8235 format %{ "subq $dst, $src\t# long" %}
8236 ins_encode %{
8237 __ subq($dst$$Register, $src$$Register);
8238 %}
8239 ins_pipe(ialu_reg_reg);
8240 %}
8241
8242 instruct subL_rReg_imm(rRegI dst, immL32 src, rFlagsReg cr)
8243 %{
8244 match(Set dst (SubL dst src));
8245 effect(KILL cr);
8246
8247 format %{ "subq $dst, $src\t# long" %}
8248 ins_encode %{
8249 __ subq($dst$$Register, $src$$constant);
8250 %}
8251 ins_pipe(ialu_reg);
8252 %}
8253
8254 instruct subL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
8255 %{
8256 match(Set dst (SubL dst (LoadL src)));
8257 effect(KILL cr);
8258
8259 ins_cost(125);
8260 format %{ "subq $dst, $src\t# long" %}
8261 ins_encode %{
8262 __ subq($dst$$Register, $src$$Address);
8263 %}
8264 ins_pipe(ialu_reg_mem);
8265 %}
8266
8267 instruct subL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
8268 %{
8269 match(Set dst (StoreL dst (SubL (LoadL dst) src)));
8270 effect(KILL cr);
8271
8272 ins_cost(150);
8273 format %{ "subq $dst, $src\t# long" %}
8274 ins_encode %{
8275 __ subq($dst$$Address, $src$$Register);
8276 %}
8277 ins_pipe(ialu_mem_reg);
8278 %}
8279
8280 instruct subL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
8281 %{
8282 match(Set dst (StoreL dst (SubL (LoadL dst) src)));
8283 effect(KILL cr);
8284
8285 ins_cost(125); // XXX
8286 format %{ "subq $dst, $src\t# long" %}
8287 ins_encode %{
8288 __ subq($dst$$Address, $src$$constant);
8289 %}
8290 ins_pipe(ialu_mem_imm);
8291 %}
8292
8293 // Subtract from a pointer
8294 // XXX hmpf???
8295 instruct subP_rReg(rRegP dst, rRegI src, immI_0 zero, rFlagsReg cr)
8296 %{
8297 match(Set dst (AddP dst (SubI zero src)));
8298 effect(KILL cr);
8299
8300 format %{ "subq $dst, $src\t# ptr - int" %}
8301 opcode(0x2B);
8302 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
8303 ins_pipe(ialu_reg_reg);
8304 %}
8305
8306 instruct negI_rReg(rRegI dst, immI_0 zero, rFlagsReg cr)
8307 %{
8308 match(Set dst (SubI zero dst));
8309 effect(KILL cr);
8310
8311 format %{ "negl $dst\t# int" %}
8312 ins_encode %{
8313 __ negl($dst$$Register);
8314 %}
8315 ins_pipe(ialu_reg);
8316 %}
8317
8318 instruct negI_rReg_2(rRegI dst, rFlagsReg cr)
8319 %{
8320 match(Set dst (NegI dst));
8321 effect(KILL cr);
8322
8323 format %{ "negl $dst\t# int" %}
8324 ins_encode %{
8325 __ negl($dst$$Register);
8326 %}
8327 ins_pipe(ialu_reg);
8328 %}
8329
8330 instruct negI_mem(memory dst, immI_0 zero, rFlagsReg cr)
8331 %{
8332 match(Set dst (StoreI dst (SubI zero (LoadI dst))));
8333 effect(KILL cr);
8334
8335 format %{ "negl $dst\t# int" %}
8336 ins_encode %{
8337 __ negl($dst$$Address);
8338 %}
8339 ins_pipe(ialu_reg);
8340 %}
8341
8342 instruct negL_rReg(rRegL dst, immL0 zero, rFlagsReg cr)
8343 %{
8344 match(Set dst (SubL zero dst));
8345 effect(KILL cr);
8346
8347 format %{ "negq $dst\t# long" %}
8348 ins_encode %{
8349 __ negq($dst$$Register);
8350 %}
8351 ins_pipe(ialu_reg);
8352 %}
8353
8354 instruct negL_rReg_2(rRegL dst, rFlagsReg cr)
8355 %{
8356 match(Set dst (NegL dst));
8357 effect(KILL cr);
8358
8359 format %{ "negq $dst\t# int" %}
8360 ins_encode %{
8361 __ negq($dst$$Register);
8362 %}
8363 ins_pipe(ialu_reg);
8364 %}
8365
8366 instruct negL_mem(memory dst, immL0 zero, rFlagsReg cr)
8367 %{
8368 match(Set dst (StoreL dst (SubL zero (LoadL dst))));
8369 effect(KILL cr);
8370
8371 format %{ "negq $dst\t# long" %}
8372 ins_encode %{
8373 __ negq($dst$$Address);
8374 %}
8375 ins_pipe(ialu_reg);
8376 %}
8377
8378 //----------Multiplication/Division Instructions-------------------------------
8379 // Integer Multiplication Instructions
8380 // Multiply Register
8381
8382 instruct mulI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
8383 %{
8384 match(Set dst (MulI dst src));
8385 effect(KILL cr);
8386
8387 ins_cost(300);
8388 format %{ "imull $dst, $src\t# int" %}
8389 ins_encode %{
8390 __ imull($dst$$Register, $src$$Register);
8391 %}
8392 ins_pipe(ialu_reg_reg_alu0);
8393 %}
8394
8395 instruct mulI_rReg_imm(rRegI dst, rRegI src, immI imm, rFlagsReg cr)
8396 %{
8397 match(Set dst (MulI src imm));
8398 effect(KILL cr);
8399
8400 ins_cost(300);
8401 format %{ "imull $dst, $src, $imm\t# int" %}
8402 ins_encode %{
8403 __ imull($dst$$Register, $src$$Register, $imm$$constant);
8404 %}
8405 ins_pipe(ialu_reg_reg_alu0);
8406 %}
8407
8408 instruct mulI_mem(rRegI dst, memory src, rFlagsReg cr)
8409 %{
8410 match(Set dst (MulI dst (LoadI src)));
8411 effect(KILL cr);
8412
8413 ins_cost(350);
8414 format %{ "imull $dst, $src\t# int" %}
8415 ins_encode %{
8416 __ imull($dst$$Register, $src$$Address);
8417 %}
8418 ins_pipe(ialu_reg_mem_alu0);
8419 %}
8420
8421 instruct mulI_mem_imm(rRegI dst, memory src, immI imm, rFlagsReg cr)
8422 %{
8423 match(Set dst (MulI (LoadI src) imm));
8424 effect(KILL cr);
8425
8426 ins_cost(300);
8427 format %{ "imull $dst, $src, $imm\t# int" %}
8428 ins_encode %{
8429 __ imull($dst$$Register, $src$$Address, $imm$$constant);
8430 %}
8431 ins_pipe(ialu_reg_mem_alu0);
8432 %}
8433
8434 instruct mulAddS2I_rReg(rRegI dst, rRegI src1, rRegI src2, rRegI src3, rFlagsReg cr)
8435 %{
8436 match(Set dst (MulAddS2I (Binary dst src1) (Binary src2 src3)));
8437 effect(KILL cr, KILL src2);
8438
8439 expand %{ mulI_rReg(dst, src1, cr);
8440 mulI_rReg(src2, src3, cr);
8441 addI_rReg(dst, src2, cr); %}
8442 %}
8443
8444 instruct mulL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
8445 %{
8446 match(Set dst (MulL dst src));
8447 effect(KILL cr);
8448
8449 ins_cost(300);
8450 format %{ "imulq $dst, $src\t# long" %}
8451 ins_encode %{
8452 __ imulq($dst$$Register, $src$$Register);
8453 %}
8454 ins_pipe(ialu_reg_reg_alu0);
8455 %}
8456
8457 instruct mulL_rReg_imm(rRegL dst, rRegL src, immL32 imm, rFlagsReg cr)
8458 %{
8459 match(Set dst (MulL src imm));
8460 effect(KILL cr);
8461
8462 ins_cost(300);
8463 format %{ "imulq $dst, $src, $imm\t# long" %}
8464 ins_encode %{
8465 __ imulq($dst$$Register, $src$$Register, $imm$$constant);
8466 %}
8467 ins_pipe(ialu_reg_reg_alu0);
8468 %}
8469
8470 instruct mulL_mem(rRegL dst, memory src, rFlagsReg cr)
8471 %{
8472 match(Set dst (MulL dst (LoadL src)));
8473 effect(KILL cr);
8474
8475 ins_cost(350);
8476 format %{ "imulq $dst, $src\t# long" %}
8477 ins_encode %{
8478 __ imulq($dst$$Register, $src$$Address);
8479 %}
8480 ins_pipe(ialu_reg_mem_alu0);
8481 %}
8482
8483 instruct mulL_mem_imm(rRegL dst, memory src, immL32 imm, rFlagsReg cr)
8484 %{
8485 match(Set dst (MulL (LoadL src) imm));
8486 effect(KILL cr);
8487
8488 ins_cost(300);
8489 format %{ "imulq $dst, $src, $imm\t# long" %}
8490 ins_encode %{
8491 __ imulq($dst$$Register, $src$$Address, $imm$$constant);
8492 %}
8493 ins_pipe(ialu_reg_mem_alu0);
8494 %}
8495
8496 instruct mulHiL_rReg(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr)
8497 %{
8498 match(Set dst (MulHiL src rax));
8499 effect(USE_KILL rax, KILL cr);
8500
8501 ins_cost(300);
8502 format %{ "imulq RDX:RAX, RAX, $src\t# mulhi" %}
8503 ins_encode %{
8504 __ imulq($src$$Register);
8505 %}
8506 ins_pipe(ialu_reg_reg_alu0);
8507 %}
8508
8509 instruct divI_rReg(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
8510 rFlagsReg cr)
8511 %{
8512 match(Set rax (DivI rax div));
8513 effect(KILL rdx, KILL cr);
8514
8515 ins_cost(30*100+10*100); // XXX
8516 format %{ "cmpl rax, 0x80000000\t# idiv\n\t"
8517 "jne,s normal\n\t"
8518 "xorl rdx, rdx\n\t"
8519 "cmpl $div, -1\n\t"
8520 "je,s done\n"
8521 "normal: cdql\n\t"
8522 "idivl $div\n"
8523 "done:" %}
8524 ins_encode(cdql_enc(div));
8525 ins_pipe(ialu_reg_reg_alu0);
8526 %}
8527
8528 instruct divL_rReg(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div,
8529 rFlagsReg cr)
8530 %{
8531 match(Set rax (DivL rax div));
8532 effect(KILL rdx, KILL cr);
8533
8534 ins_cost(30*100+10*100); // XXX
8535 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t"
8536 "cmpq rax, rdx\n\t"
8537 "jne,s normal\n\t"
8538 "xorl rdx, rdx\n\t"
8539 "cmpq $div, -1\n\t"
8540 "je,s done\n"
8541 "normal: cdqq\n\t"
8542 "idivq $div\n"
8543 "done:" %}
8544 ins_encode(cdqq_enc(div));
8545 ins_pipe(ialu_reg_reg_alu0);
8546 %}
8547
8548 // Integer DIVMOD with Register, both quotient and mod results
8549 instruct divModI_rReg_divmod(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
8550 rFlagsReg cr)
8551 %{
8552 match(DivModI rax div);
8553 effect(KILL cr);
8554
8555 ins_cost(30*100+10*100); // XXX
8556 format %{ "cmpl rax, 0x80000000\t# idiv\n\t"
8557 "jne,s normal\n\t"
8558 "xorl rdx, rdx\n\t"
8559 "cmpl $div, -1\n\t"
8560 "je,s done\n"
8561 "normal: cdql\n\t"
8562 "idivl $div\n"
8563 "done:" %}
8564 ins_encode(cdql_enc(div));
8565 ins_pipe(pipe_slow);
8566 %}
8567
8568 // Long DIVMOD with Register, both quotient and mod results
8569 instruct divModL_rReg_divmod(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div,
8570 rFlagsReg cr)
8571 %{
8572 match(DivModL rax div);
8573 effect(KILL cr);
8574
8575 ins_cost(30*100+10*100); // XXX
8576 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t"
8577 "cmpq rax, rdx\n\t"
8578 "jne,s normal\n\t"
8579 "xorl rdx, rdx\n\t"
8580 "cmpq $div, -1\n\t"
8581 "je,s done\n"
8582 "normal: cdqq\n\t"
8583 "idivq $div\n"
8584 "done:" %}
8585 ins_encode(cdqq_enc(div));
8586 ins_pipe(pipe_slow);
8587 %}
8588
8589 //----------- DivL-By-Constant-Expansions--------------------------------------
8590 // DivI cases are handled by the compiler
8591
8592 // Magic constant, reciprocal of 10
8593 instruct loadConL_0x6666666666666667(rRegL dst)
8594 %{
8595 effect(DEF dst);
8596
8597 format %{ "movq $dst, #0x666666666666667\t# Used in div-by-10" %}
8598 ins_encode(load_immL(dst, 0x6666666666666667));
8599 ins_pipe(ialu_reg);
8600 %}
8601
8602 instruct mul_hi(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr)
8603 %{
8604 effect(DEF dst, USE src, USE_KILL rax, KILL cr);
8605
8606 format %{ "imulq rdx:rax, rax, $src\t# Used in div-by-10" %}
8607 ins_encode %{
8608 __ imulq($src$$Register);
8609 %}
8610 ins_pipe(ialu_reg_reg_alu0);
8611 %}
8612
8613 instruct sarL_rReg_63(rRegL dst, rFlagsReg cr)
8614 %{
8615 effect(USE_DEF dst, KILL cr);
8616
8617 format %{ "sarq $dst, #63\t# Used in div-by-10" %}
8618 ins_encode %{
8619 __ sarq($dst$$Register, 63);
8620 %}
8621 ins_pipe(ialu_reg);
8622 %}
8623
8624 instruct sarL_rReg_2(rRegL dst, rFlagsReg cr)
8625 %{
8626 effect(USE_DEF dst, KILL cr);
8627
8628 format %{ "sarq $dst, #2\t# Used in div-by-10" %}
8629 ins_encode %{
8630 __ sarq($dst$$Register, 2);
8631 %}
8632 ins_pipe(ialu_reg);
8633 %}
8634
8635 instruct divL_10(rdx_RegL dst, no_rax_RegL src, immL10 div)
8636 %{
8637 match(Set dst (DivL src div));
8638
8639 ins_cost((5+8)*100);
8640 expand %{
8641 rax_RegL rax; // Killed temp
8642 rFlagsReg cr; // Killed
8643 loadConL_0x6666666666666667(rax); // movq rax, 0x6666666666666667
8644 mul_hi(dst, src, rax, cr); // mulq rdx:rax <= rax * $src
8645 sarL_rReg_63(src, cr); // sarq src, 63
8646 sarL_rReg_2(dst, cr); // sarq rdx, 2
8647 subL_rReg(dst, src, cr); // subl rdx, src
8648 %}
8649 %}
8650
8651 //-----------------------------------------------------------------------------
8652
8653 instruct modI_rReg(rdx_RegI rdx, rax_RegI rax, no_rax_rdx_RegI div,
8654 rFlagsReg cr)
8655 %{
8656 match(Set rdx (ModI rax div));
8657 effect(KILL rax, KILL cr);
8658
8659 ins_cost(300); // XXX
8660 format %{ "cmpl rax, 0x80000000\t# irem\n\t"
8661 "jne,s normal\n\t"
8662 "xorl rdx, rdx\n\t"
8663 "cmpl $div, -1\n\t"
8664 "je,s done\n"
8665 "normal: cdql\n\t"
8666 "idivl $div\n"
8667 "done:" %}
8668 ins_encode(cdql_enc(div));
8669 ins_pipe(ialu_reg_reg_alu0);
8670 %}
8671
8672 instruct modL_rReg(rdx_RegL rdx, rax_RegL rax, no_rax_rdx_RegL div,
8673 rFlagsReg cr)
8674 %{
8675 match(Set rdx (ModL rax div));
8676 effect(KILL rax, KILL cr);
8677
8678 ins_cost(300); // XXX
8679 format %{ "movq rdx, 0x8000000000000000\t# lrem\n\t"
8680 "cmpq rax, rdx\n\t"
8681 "jne,s normal\n\t"
8682 "xorl rdx, rdx\n\t"
8683 "cmpq $div, -1\n\t"
8684 "je,s done\n"
8685 "normal: cdqq\n\t"
8686 "idivq $div\n"
8687 "done:" %}
8688 ins_encode(cdqq_enc(div));
8689 ins_pipe(ialu_reg_reg_alu0);
8690 %}
8691
8692 // Integer Shift Instructions
8693 // Shift Left by one
8694 instruct salI_rReg_1(rRegI dst, immI_1 shift, rFlagsReg cr)
8695 %{
8696 match(Set dst (LShiftI dst shift));
8697 effect(KILL cr);
8698
8699 format %{ "sall $dst, $shift" %}
8700 ins_encode %{
8701 __ sall($dst$$Register, $shift$$constant);
8702 %}
8703 ins_pipe(ialu_reg);
8704 %}
8705
8706 // Shift Left by one
8707 instruct salI_mem_1(memory dst, immI_1 shift, rFlagsReg cr)
8708 %{
8709 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
8710 effect(KILL cr);
8711
8712 format %{ "sall $dst, $shift\t" %}
8713 ins_encode %{
8714 __ sall($dst$$Address, $shift$$constant);
8715 %}
8716 ins_pipe(ialu_mem_imm);
8717 %}
8718
8719 // Shift Left by 8-bit immediate
8720 instruct salI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
8721 %{
8722 match(Set dst (LShiftI dst shift));
8723 effect(KILL cr);
8724
8725 format %{ "sall $dst, $shift" %}
8726 ins_encode %{
8727 __ sall($dst$$Register, $shift$$constant);
8728 %}
8729 ins_pipe(ialu_reg);
8730 %}
8731
8732 // Shift Left by 8-bit immediate
8733 instruct salI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8734 %{
8735 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
8736 effect(KILL cr);
8737
8738 format %{ "sall $dst, $shift" %}
8739 ins_encode %{
8740 __ sall($dst$$Address, $shift$$constant);
8741 %}
8742 ins_pipe(ialu_mem_imm);
8743 %}
8744
8745 // Shift Left by variable
8746 instruct salI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
8747 %{
8748 match(Set dst (LShiftI dst shift));
8749 effect(KILL cr);
8750
8751 format %{ "sall $dst, $shift" %}
8752 ins_encode %{
8753 __ sall($dst$$Register);
8754 %}
8755 ins_pipe(ialu_reg_reg);
8756 %}
8757
8758 // Shift Left by variable
8759 instruct salI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8760 %{
8761 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
8762 effect(KILL cr);
8763
8764 format %{ "sall $dst, $shift" %}
8765 ins_encode %{
8766 __ sall($dst$$Address);
8767 %}
8768 ins_pipe(ialu_mem_reg);
8769 %}
8770
8771 // Arithmetic shift right by one
8772 instruct sarI_rReg_1(rRegI dst, immI_1 shift, rFlagsReg cr)
8773 %{
8774 match(Set dst (RShiftI dst shift));
8775 effect(KILL cr);
8776
8777 format %{ "sarl $dst, $shift" %}
8778 ins_encode %{
8779 __ sarl($dst$$Register, $shift$$constant);
8780 %}
8781 ins_pipe(ialu_reg);
8782 %}
8783
8784 // Arithmetic shift right by one
8785 instruct sarI_mem_1(memory dst, immI_1 shift, rFlagsReg cr)
8786 %{
8787 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8788 effect(KILL cr);
8789
8790 format %{ "sarl $dst, $shift" %}
8791 ins_encode %{
8792 __ sarl($dst$$Address, $shift$$constant);
8793 %}
8794 ins_pipe(ialu_mem_imm);
8795 %}
8796
8797 // Arithmetic Shift Right by 8-bit immediate
8798 instruct sarI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
8799 %{
8800 match(Set dst (RShiftI dst shift));
8801 effect(KILL cr);
8802
8803 format %{ "sarl $dst, $shift" %}
8804 ins_encode %{
8805 __ sarl($dst$$Register, $shift$$constant);
8806 %}
8807 ins_pipe(ialu_mem_imm);
8808 %}
8809
8810 // Arithmetic Shift Right by 8-bit immediate
8811 instruct sarI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8812 %{
8813 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8814 effect(KILL cr);
8815
8816 format %{ "sarl $dst, $shift" %}
8817 ins_encode %{
8818 __ sarl($dst$$Address, $shift$$constant);
8819 %}
8820 ins_pipe(ialu_mem_imm);
8821 %}
8822
8823 // Arithmetic Shift Right by variable
8824 instruct sarI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
8825 %{
8826 match(Set dst (RShiftI dst shift));
8827 effect(KILL cr);
8828 format %{ "sarl $dst, $shift" %}
8829 ins_encode %{
8830 __ sarl($dst$$Register);
8831 %}
8832 ins_pipe(ialu_reg_reg);
8833 %}
8834
8835 // Arithmetic Shift Right by variable
8836 instruct sarI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8837 %{
8838 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8839 effect(KILL cr);
8840
8841 format %{ "sarl $dst, $shift" %}
8842 ins_encode %{
8843 __ sarl($dst$$Address);
8844 %}
8845 ins_pipe(ialu_mem_reg);
8846 %}
8847
8848 // Logical shift right by one
8849 instruct shrI_rReg_1(rRegI dst, immI_1 shift, rFlagsReg cr)
8850 %{
8851 match(Set dst (URShiftI dst shift));
8852 effect(KILL cr);
8853
8854 format %{ "shrl $dst, $shift" %}
8855 ins_encode %{
8856 __ shrl($dst$$Register, $shift$$constant);
8857 %}
8858 ins_pipe(ialu_reg);
8859 %}
8860
8861 // Logical shift right by one
8862 instruct shrI_mem_1(memory dst, immI_1 shift, rFlagsReg cr)
8863 %{
8864 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
8865 effect(KILL cr);
8866
8867 format %{ "shrl $dst, $shift" %}
8868 ins_encode %{
8869 __ shrl($dst$$Address, $shift$$constant);
8870 %}
8871 ins_pipe(ialu_mem_imm);
8872 %}
8873
8874 // Logical Shift Right by 8-bit immediate
8875 instruct shrI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
8876 %{
8877 match(Set dst (URShiftI dst shift));
8878 effect(KILL cr);
8879
8880 format %{ "shrl $dst, $shift" %}
8881 ins_encode %{
8882 __ shrl($dst$$Register, $shift$$constant);
8883 %}
8884 ins_pipe(ialu_reg);
8885 %}
8886
8887 // Logical Shift Right by 8-bit immediate
8888 instruct shrI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8889 %{
8890 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
8891 effect(KILL cr);
8892
8893 format %{ "shrl $dst, $shift" %}
8894 ins_encode %{
8895 __ shrl($dst$$Address, $shift$$constant);
8896 %}
8897 ins_pipe(ialu_mem_imm);
8898 %}
8899
8900 // Logical Shift Right by variable
8901 instruct shrI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
8902 %{
8903 match(Set dst (URShiftI dst shift));
8904 effect(KILL cr);
8905
8906 format %{ "shrl $dst, $shift" %}
8907 ins_encode %{
8908 __ shrl($dst$$Register);
8909 %}
8910 ins_pipe(ialu_reg_reg);
8911 %}
8912
8913 // Logical Shift Right by variable
8914 instruct shrI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8915 %{
8916 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
8917 effect(KILL cr);
8918
8919 format %{ "shrl $dst, $shift" %}
8920 ins_encode %{
8921 __ shrl($dst$$Address);
8922 %}
8923 ins_pipe(ialu_mem_reg);
8924 %}
8925
8926 // Long Shift Instructions
8927 // Shift Left by one
8928 instruct salL_rReg_1(rRegL dst, immI_1 shift, rFlagsReg cr)
8929 %{
8930 match(Set dst (LShiftL dst shift));
8931 effect(KILL cr);
8932
8933 format %{ "salq $dst, $shift" %}
8934 ins_encode %{
8935 __ salq($dst$$Register, $shift$$constant);
8936 %}
8937 ins_pipe(ialu_reg);
8938 %}
8939
8940 // Shift Left by one
8941 instruct salL_mem_1(memory dst, immI_1 shift, rFlagsReg cr)
8942 %{
8943 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
8944 effect(KILL cr);
8945
8946 format %{ "salq $dst, $shift" %}
8947 ins_encode %{
8948 __ salq($dst$$Address, $shift$$constant);
8949 %}
8950 ins_pipe(ialu_mem_imm);
8951 %}
8952
8953 // Shift Left by 8-bit immediate
8954 instruct salL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
8955 %{
8956 match(Set dst (LShiftL dst shift));
8957 effect(KILL cr);
8958
8959 format %{ "salq $dst, $shift" %}
8960 ins_encode %{
8961 __ salq($dst$$Register, $shift$$constant);
8962 %}
8963 ins_pipe(ialu_reg);
8964 %}
8965
8966 // Shift Left by 8-bit immediate
8967 instruct salL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8968 %{
8969 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
8970 effect(KILL cr);
8971
8972 format %{ "salq $dst, $shift" %}
8973 ins_encode %{
8974 __ salq($dst$$Address, $shift$$constant);
8975 %}
8976 ins_pipe(ialu_mem_imm);
8977 %}
8978
8979 // Shift Left by variable
8980 instruct salL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
8981 %{
8982 match(Set dst (LShiftL dst shift));
8983 effect(KILL cr);
8984
8985 format %{ "salq $dst, $shift" %}
8986 ins_encode %{
8987 __ salq($dst$$Register);
8988 %}
8989 ins_pipe(ialu_reg_reg);
8990 %}
8991
8992 // Shift Left by variable
8993 instruct salL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8994 %{
8995 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
8996 effect(KILL cr);
8997
8998 format %{ "salq $dst, $shift" %}
8999 ins_encode %{
9000 __ salq($dst$$Address);
9001 %}
9002 ins_pipe(ialu_mem_reg);
9003 %}
9004
9005 // Arithmetic shift right by one
9006 instruct sarL_rReg_1(rRegL dst, immI_1 shift, rFlagsReg cr)
9007 %{
9008 match(Set dst (RShiftL dst shift));
9009 effect(KILL cr);
9010
9011 format %{ "sarq $dst, $shift" %}
9012 ins_encode %{
9013 __ sarq($dst$$Register, $shift$$constant);
9014 %}
9015 ins_pipe(ialu_reg);
9016 %}
9017
9018 // Arithmetic shift right by one
9019 instruct sarL_mem_1(memory dst, immI_1 shift, rFlagsReg cr)
9020 %{
9021 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
9022 effect(KILL cr);
9023
9024 format %{ "sarq $dst, $shift" %}
9025 ins_encode %{
9026 __ sarq($dst$$Address, $shift$$constant);
9027 %}
9028 ins_pipe(ialu_mem_imm);
9029 %}
9030
9031 // Arithmetic Shift Right by 8-bit immediate
9032 instruct sarL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
9033 %{
9034 match(Set dst (RShiftL dst shift));
9035 effect(KILL cr);
9036
9037 format %{ "sarq $dst, $shift" %}
9038 ins_encode %{
9039 __ sarq($dst$$Register, (unsigned char)($shift$$constant & 0x3F));
9040 %}
9041 ins_pipe(ialu_mem_imm);
9042 %}
9043
9044 // Arithmetic Shift Right by 8-bit immediate
9045 instruct sarL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
9046 %{
9047 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
9048 effect(KILL cr);
9049
9050 format %{ "sarq $dst, $shift" %}
9051 ins_encode %{
9052 __ sarq($dst$$Address, (unsigned char)($shift$$constant & 0x3F));
9053 %}
9054 ins_pipe(ialu_mem_imm);
9055 %}
9056
9057 // Arithmetic Shift Right by variable
9058 instruct sarL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
9059 %{
9060 match(Set dst (RShiftL dst shift));
9061 effect(KILL cr);
9062
9063 format %{ "sarq $dst, $shift" %}
9064 ins_encode %{
9065 __ sarq($dst$$Register);
9066 %}
9067 ins_pipe(ialu_reg_reg);
9068 %}
9069
9070 // Arithmetic Shift Right by variable
9071 instruct sarL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
9072 %{
9073 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
9074 effect(KILL cr);
9075
9076 format %{ "sarq $dst, $shift" %}
9077 ins_encode %{
9078 __ sarq($dst$$Address);
9079 %}
9080 ins_pipe(ialu_mem_reg);
9081 %}
9082
9083 // Logical shift right by one
9084 instruct shrL_rReg_1(rRegL dst, immI_1 shift, rFlagsReg cr)
9085 %{
9086 match(Set dst (URShiftL dst shift));
9087 effect(KILL cr);
9088
9089 format %{ "shrq $dst, $shift" %}
9090 ins_encode %{
9091 __ shrq($dst$$Register, $shift$$constant);
9092 %}
9093 ins_pipe(ialu_reg);
9094 %}
9095
9096 // Logical shift right by one
9097 instruct shrL_mem_1(memory dst, immI_1 shift, rFlagsReg cr)
9098 %{
9099 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
9100 effect(KILL cr);
9101
9102 format %{ "shrq $dst, $shift" %}
9103 ins_encode %{
9104 __ shrq($dst$$Address, $shift$$constant);
9105 %}
9106 ins_pipe(ialu_mem_imm);
9107 %}
9108
9109 // Logical Shift Right by 8-bit immediate
9110 instruct shrL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
9111 %{
9112 match(Set dst (URShiftL dst shift));
9113 effect(KILL cr);
9114
9115 format %{ "shrq $dst, $shift" %}
9116 ins_encode %{
9117 __ shrq($dst$$Register, $shift$$constant);
9118 %}
9119 ins_pipe(ialu_reg);
9120 %}
9121
9122 // Logical Shift Right by 8-bit immediate
9123 instruct shrL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
9124 %{
9125 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
9126 effect(KILL cr);
9127
9128 format %{ "shrq $dst, $shift" %}
9129 ins_encode %{
9130 __ shrq($dst$$Address, $shift$$constant);
9131 %}
9132 ins_pipe(ialu_mem_imm);
9133 %}
9134
9135 // Logical Shift Right by variable
9136 instruct shrL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
9137 %{
9138 match(Set dst (URShiftL dst shift));
9139 effect(KILL cr);
9140
9141 format %{ "shrq $dst, $shift" %}
9142 ins_encode %{
9143 __ shrq($dst$$Register);
9144 %}
9145 ins_pipe(ialu_reg_reg);
9146 %}
9147
9148 // Logical Shift Right by variable
9149 instruct shrL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
9150 %{
9151 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
9152 effect(KILL cr);
9153
9154 format %{ "shrq $dst, $shift" %}
9155 ins_encode %{
9156 __ shrq($dst$$Address);
9157 %}
9158 ins_pipe(ialu_mem_reg);
9159 %}
9160
9161 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
9162 // This idiom is used by the compiler for the i2b bytecode.
9163 instruct i2b(rRegI dst, rRegI src, immI_24 twentyfour)
9164 %{
9165 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour));
9166
9167 format %{ "movsbl $dst, $src\t# i2b" %}
9168 ins_encode %{
9169 __ movsbl($dst$$Register, $src$$Register);
9170 %}
9171 ins_pipe(ialu_reg_reg);
9172 %}
9173
9174 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16.
9175 // This idiom is used by the compiler the i2s bytecode.
9176 instruct i2s(rRegI dst, rRegI src, immI_16 sixteen)
9177 %{
9178 match(Set dst (RShiftI (LShiftI src sixteen) sixteen));
9179
9180 format %{ "movswl $dst, $src\t# i2s" %}
9181 ins_encode %{
9182 __ movswl($dst$$Register, $src$$Register);
9183 %}
9184 ins_pipe(ialu_reg_reg);
9185 %}
9186
9187 // ROL/ROR instructions
9188
9189 // Rotate left by constant.
9190 instruct rolI_imm(rRegI dst, immI8 shift, rFlagsReg cr)
9191 %{
9192 predicate(n->bottom_type()->basic_type() == T_INT);
9193 match(Set dst (RotateLeft dst shift));
9194 effect(KILL cr);
9195 format %{ "roll $dst, $shift" %}
9196 ins_encode %{
9197 __ roll($dst$$Register, $shift$$constant);
9198 %}
9199 ins_pipe(ialu_reg);
9200 %}
9201
9202 // Rotate Left by variable
9203 instruct rolI_rReg_Var(rRegI dst, rcx_RegI shift, rFlagsReg cr)
9204 %{
9205 predicate(n->bottom_type()->basic_type() == T_INT);
9206 match(Set dst (RotateLeft dst shift));
9207 effect(KILL cr);
9208 format %{ "roll $dst, $shift" %}
9209 ins_encode %{
9210 __ roll($dst$$Register);
9211 %}
9212 ins_pipe(ialu_reg_reg);
9213 %}
9214
9215 // Rotate Right by constant.
9216 instruct rorI_immI8_legacy(rRegI dst, immI8 shift, rFlagsReg cr)
9217 %{
9218 predicate(!VM_Version::supports_bmi2() && n->bottom_type()->basic_type() == T_INT);
9219 match(Set dst (RotateRight dst shift));
9220 effect(KILL cr);
9221 format %{ "rorl $dst, $shift" %}
9222 ins_encode %{
9223 __ rorl($dst$$Register, $shift$$constant);
9224 %}
9225 ins_pipe(ialu_reg);
9226 %}
9227
9228 // Rotate Right by constant.
9229 instruct rorI_immI8(rRegI dst, immI8 shift)
9230 %{
9231 predicate(VM_Version::supports_bmi2() && n->bottom_type()->basic_type() == T_INT);
9232 match(Set dst (RotateRight dst shift));
9233 format %{ "rorxd $dst, $shift" %}
9234 ins_encode %{
9235 __ rorxd($dst$$Register, $dst$$Register, $shift$$constant);
9236 %}
9237 ins_pipe(ialu_reg_reg);
9238 %}
9239
9240 // Rotate Right by variable
9241 instruct rorI_rReg_Var(rRegI dst, rcx_RegI shift, rFlagsReg cr)
9242 %{
9243 predicate(n->bottom_type()->basic_type() == T_INT);
9244 match(Set dst (RotateRight dst shift));
9245 effect(KILL cr);
9246 format %{ "rorl $dst, $shift" %}
9247 ins_encode %{
9248 __ rorl($dst$$Register);
9249 %}
9250 ins_pipe(ialu_reg_reg);
9251 %}
9252
9253
9254 // Rotate Left by constant.
9255 instruct rolL_immI8(rRegL dst, immI8 shift, rFlagsReg cr)
9256 %{
9257 predicate(n->bottom_type()->basic_type() == T_LONG);
9258 match(Set dst (RotateLeft dst shift));
9259 effect(KILL cr);
9260 format %{ "rolq $dst, $shift" %}
9261 ins_encode %{
9262 __ rolq($dst$$Register, $shift$$constant);
9263 %}
9264 ins_pipe(ialu_reg);
9265 %}
9266
9267 // Rotate Left by variable
9268 instruct rolL_rReg_Var(rRegL dst, rcx_RegI shift, rFlagsReg cr)
9269 %{
9270 predicate(n->bottom_type()->basic_type() == T_LONG);
9271 match(Set dst (RotateLeft dst shift));
9272 effect(KILL cr);
9273 format %{ "rolq $dst, $shift" %}
9274 ins_encode %{
9275 __ rolq($dst$$Register);
9276 %}
9277 ins_pipe(ialu_reg_reg);
9278 %}
9279
9280
9281 // Rotate Right by constant.
9282 instruct rorL_immI8_legacy(rRegL dst, immI8 shift, rFlagsReg cr)
9283 %{
9284 predicate(!VM_Version::supports_bmi2() && n->bottom_type()->basic_type() == T_LONG);
9285 match(Set dst (RotateRight dst shift));
9286 effect(KILL cr);
9287 format %{ "rorq $dst, $shift" %}
9288 ins_encode %{
9289 __ rorq($dst$$Register, $shift$$constant);
9290 %}
9291 ins_pipe(ialu_reg);
9292 %}
9293
9294
9295 // Rotate Right by constant
9296 instruct rorL_immI8(rRegL dst, immI8 shift)
9297 %{
9298 predicate(VM_Version::supports_bmi2() && n->bottom_type()->basic_type() == T_LONG);
9299 match(Set dst (RotateRight dst shift));
9300 format %{ "rorxq $dst, $shift" %}
9301 ins_encode %{
9302 __ rorxq($dst$$Register, $dst$$Register, $shift$$constant);
9303 %}
9304 ins_pipe(ialu_reg_reg);
9305 %}
9306
9307 // Rotate Right by variable
9308 instruct rorL_rReg_Var(rRegL dst, rcx_RegI shift, rFlagsReg cr)
9309 %{
9310 predicate(n->bottom_type()->basic_type() == T_LONG);
9311 match(Set dst (RotateRight dst shift));
9312 effect(KILL cr);
9313 format %{ "rorq $dst, $shift" %}
9314 ins_encode %{
9315 __ rorq($dst$$Register);
9316 %}
9317 ins_pipe(ialu_reg_reg);
9318 %}
9319
9320
9321 // Logical Instructions
9322
9323 // Integer Logical Instructions
9324
9325 // And Instructions
9326 // And Register with Register
9327 instruct andI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
9328 %{
9329 match(Set dst (AndI dst src));
9330 effect(KILL cr);
9331
9332 format %{ "andl $dst, $src\t# int" %}
9333 ins_encode %{
9334 __ andl($dst$$Register, $src$$Register);
9335 %}
9336 ins_pipe(ialu_reg_reg);
9337 %}
9338
9339 // And Register with Immediate 255
9340 instruct andI_rReg_imm255(rRegI dst, immI_255 src)
9341 %{
9342 match(Set dst (AndI dst src));
9343
9344 format %{ "movzbl $dst, $dst\t# int & 0xFF" %}
9345 ins_encode %{
9346 __ movzbl($dst$$Register, $dst$$Register);
9347 %}
9348 ins_pipe(ialu_reg);
9349 %}
9350
9351 // And Register with Immediate 255 and promote to long
9352 instruct andI2L_rReg_imm255(rRegL dst, rRegI src, immI_255 mask)
9353 %{
9354 match(Set dst (ConvI2L (AndI src mask)));
9355
9356 format %{ "movzbl $dst, $src\t# int & 0xFF -> long" %}
9357 ins_encode %{
9358 __ movzbl($dst$$Register, $src$$Register);
9359 %}
9360 ins_pipe(ialu_reg);
9361 %}
9362
9363 // And Register with Immediate 65535
9364 instruct andI_rReg_imm65535(rRegI dst, immI_65535 src)
9365 %{
9366 match(Set dst (AndI dst src));
9367
9368 format %{ "movzwl $dst, $dst\t# int & 0xFFFF" %}
9369 ins_encode %{
9370 __ movzwl($dst$$Register, $dst$$Register);
9371 %}
9372 ins_pipe(ialu_reg);
9373 %}
9374
9375 // And Register with Immediate 65535 and promote to long
9376 instruct andI2L_rReg_imm65535(rRegL dst, rRegI src, immI_65535 mask)
9377 %{
9378 match(Set dst (ConvI2L (AndI src mask)));
9379
9380 format %{ "movzwl $dst, $src\t# int & 0xFFFF -> long" %}
9381 ins_encode %{
9382 __ movzwl($dst$$Register, $src$$Register);
9383 %}
9384 ins_pipe(ialu_reg);
9385 %}
9386
9387 // Can skip int2long conversions after AND with small bitmask
9388 instruct convI2LAndI_reg_immIbitmask(rRegL dst, rRegI src, immI_Pow2M1 mask, rRegI tmp, rFlagsReg cr)
9389 %{
9390 predicate(VM_Version::supports_bmi2());
9391 ins_cost(125);
9392 effect(TEMP tmp, KILL cr);
9393 match(Set dst (ConvI2L (AndI src mask)));
9394 format %{ "bzhiq $dst, $src, $mask \t# using $tmp as TEMP, int & immI_Pow2M1 -> long" %}
9395 ins_encode %{
9396 __ movl($tmp$$Register, exact_log2($mask$$constant + 1));
9397 __ bzhiq($dst$$Register, $src$$Register, $tmp$$Register);
9398 %}
9399 ins_pipe(ialu_reg_reg);
9400 %}
9401
9402 // And Register with Immediate
9403 instruct andI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
9404 %{
9405 match(Set dst (AndI dst src));
9406 effect(KILL cr);
9407
9408 format %{ "andl $dst, $src\t# int" %}
9409 ins_encode %{
9410 __ andl($dst$$Register, $src$$constant);
9411 %}
9412 ins_pipe(ialu_reg);
9413 %}
9414
9415 // And Register with Memory
9416 instruct andI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
9417 %{
9418 match(Set dst (AndI dst (LoadI src)));
9419 effect(KILL cr);
9420
9421 ins_cost(125);
9422 format %{ "andl $dst, $src\t# int" %}
9423 ins_encode %{
9424 __ andl($dst$$Register, $src$$Address);
9425 %}
9426 ins_pipe(ialu_reg_mem);
9427 %}
9428
9429 // And Memory with Register
9430 instruct andB_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9431 %{
9432 match(Set dst (StoreB dst (AndI (LoadB dst) src)));
9433 effect(KILL cr);
9434
9435 ins_cost(150);
9436 format %{ "andb $dst, $src\t# byte" %}
9437 ins_encode %{
9438 __ andb($dst$$Address, $src$$Register);
9439 %}
9440 ins_pipe(ialu_mem_reg);
9441 %}
9442
9443 instruct andI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9444 %{
9445 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
9446 effect(KILL cr);
9447
9448 ins_cost(150);
9449 format %{ "andl $dst, $src\t# int" %}
9450 ins_encode %{
9451 __ andl($dst$$Address, $src$$Register);
9452 %}
9453 ins_pipe(ialu_mem_reg);
9454 %}
9455
9456 // And Memory with Immediate
9457 instruct andI_mem_imm(memory dst, immI src, rFlagsReg cr)
9458 %{
9459 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
9460 effect(KILL cr);
9461
9462 ins_cost(125);
9463 format %{ "andl $dst, $src\t# int" %}
9464 ins_encode %{
9465 __ andl($dst$$Address, $src$$constant);
9466 %}
9467 ins_pipe(ialu_mem_imm);
9468 %}
9469
9470 // BMI1 instructions
9471 instruct andnI_rReg_rReg_mem(rRegI dst, rRegI src1, memory src2, immI_M1 minus_1, rFlagsReg cr) %{
9472 match(Set dst (AndI (XorI src1 minus_1) (LoadI src2)));
9473 predicate(UseBMI1Instructions);
9474 effect(KILL cr);
9475
9476 ins_cost(125);
9477 format %{ "andnl $dst, $src1, $src2" %}
9478
9479 ins_encode %{
9480 __ andnl($dst$$Register, $src1$$Register, $src2$$Address);
9481 %}
9482 ins_pipe(ialu_reg_mem);
9483 %}
9484
9485 instruct andnI_rReg_rReg_rReg(rRegI dst, rRegI src1, rRegI src2, immI_M1 minus_1, rFlagsReg cr) %{
9486 match(Set dst (AndI (XorI src1 minus_1) src2));
9487 predicate(UseBMI1Instructions);
9488 effect(KILL cr);
9489
9490 format %{ "andnl $dst, $src1, $src2" %}
9491
9492 ins_encode %{
9493 __ andnl($dst$$Register, $src1$$Register, $src2$$Register);
9494 %}
9495 ins_pipe(ialu_reg);
9496 %}
9497
9498 instruct blsiI_rReg_rReg(rRegI dst, rRegI src, immI_0 imm_zero, rFlagsReg cr) %{
9499 match(Set dst (AndI (SubI imm_zero src) src));
9500 predicate(UseBMI1Instructions);
9501 effect(KILL cr);
9502
9503 format %{ "blsil $dst, $src" %}
9504
9505 ins_encode %{
9506 __ blsil($dst$$Register, $src$$Register);
9507 %}
9508 ins_pipe(ialu_reg);
9509 %}
9510
9511 instruct blsiI_rReg_mem(rRegI dst, memory src, immI_0 imm_zero, rFlagsReg cr) %{
9512 match(Set dst (AndI (SubI imm_zero (LoadI src) ) (LoadI src) ));
9513 predicate(UseBMI1Instructions);
9514 effect(KILL cr);
9515
9516 ins_cost(125);
9517 format %{ "blsil $dst, $src" %}
9518
9519 ins_encode %{
9520 __ blsil($dst$$Register, $src$$Address);
9521 %}
9522 ins_pipe(ialu_reg_mem);
9523 %}
9524
9525 instruct blsmskI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, rFlagsReg cr)
9526 %{
9527 match(Set dst (XorI (AddI (LoadI src) minus_1) (LoadI src) ) );
9528 predicate(UseBMI1Instructions);
9529 effect(KILL cr);
9530
9531 ins_cost(125);
9532 format %{ "blsmskl $dst, $src" %}
9533
9534 ins_encode %{
9535 __ blsmskl($dst$$Register, $src$$Address);
9536 %}
9537 ins_pipe(ialu_reg_mem);
9538 %}
9539
9540 instruct blsmskI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, rFlagsReg cr)
9541 %{
9542 match(Set dst (XorI (AddI src minus_1) src));
9543 predicate(UseBMI1Instructions);
9544 effect(KILL cr);
9545
9546 format %{ "blsmskl $dst, $src" %}
9547
9548 ins_encode %{
9549 __ blsmskl($dst$$Register, $src$$Register);
9550 %}
9551
9552 ins_pipe(ialu_reg);
9553 %}
9554
9555 instruct blsrI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, rFlagsReg cr)
9556 %{
9557 match(Set dst (AndI (AddI src minus_1) src) );
9558 predicate(UseBMI1Instructions);
9559 effect(KILL cr);
9560
9561 format %{ "blsrl $dst, $src" %}
9562
9563 ins_encode %{
9564 __ blsrl($dst$$Register, $src$$Register);
9565 %}
9566
9567 ins_pipe(ialu_reg_mem);
9568 %}
9569
9570 instruct blsrI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, rFlagsReg cr)
9571 %{
9572 match(Set dst (AndI (AddI (LoadI src) minus_1) (LoadI src) ) );
9573 predicate(UseBMI1Instructions);
9574 effect(KILL cr);
9575
9576 ins_cost(125);
9577 format %{ "blsrl $dst, $src" %}
9578
9579 ins_encode %{
9580 __ blsrl($dst$$Register, $src$$Address);
9581 %}
9582
9583 ins_pipe(ialu_reg);
9584 %}
9585
9586 // Or Instructions
9587 // Or Register with Register
9588 instruct orI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
9589 %{
9590 match(Set dst (OrI dst src));
9591 effect(KILL cr);
9592
9593 format %{ "orl $dst, $src\t# int" %}
9594 ins_encode %{
9595 __ orl($dst$$Register, $src$$Register);
9596 %}
9597 ins_pipe(ialu_reg_reg);
9598 %}
9599
9600 // Or Register with Immediate
9601 instruct orI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
9602 %{
9603 match(Set dst (OrI dst src));
9604 effect(KILL cr);
9605
9606 format %{ "orl $dst, $src\t# int" %}
9607 ins_encode %{
9608 __ orl($dst$$Register, $src$$constant);
9609 %}
9610 ins_pipe(ialu_reg);
9611 %}
9612
9613 // Or Register with Memory
9614 instruct orI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
9615 %{
9616 match(Set dst (OrI dst (LoadI src)));
9617 effect(KILL cr);
9618
9619 ins_cost(125);
9620 format %{ "orl $dst, $src\t# int" %}
9621 ins_encode %{
9622 __ orl($dst$$Register, $src$$Address);
9623 %}
9624 ins_pipe(ialu_reg_mem);
9625 %}
9626
9627 // Or Memory with Register
9628 instruct orB_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9629 %{
9630 match(Set dst (StoreB dst (OrI (LoadB dst) src)));
9631 effect(KILL cr);
9632
9633 ins_cost(150);
9634 format %{ "orb $dst, $src\t# byte" %}
9635 ins_encode %{
9636 __ orb($dst$$Address, $src$$Register);
9637 %}
9638 ins_pipe(ialu_mem_reg);
9639 %}
9640
9641 instruct orI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9642 %{
9643 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
9644 effect(KILL cr);
9645
9646 ins_cost(150);
9647 format %{ "orl $dst, $src\t# int" %}
9648 ins_encode %{
9649 __ orl($dst$$Address, $src$$Register);
9650 %}
9651 ins_pipe(ialu_mem_reg);
9652 %}
9653
9654 // Or Memory with Immediate
9655 instruct orI_mem_imm(memory dst, immI src, rFlagsReg cr)
9656 %{
9657 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
9658 effect(KILL cr);
9659
9660 ins_cost(125);
9661 format %{ "orl $dst, $src\t# int" %}
9662 ins_encode %{
9663 __ orl($dst$$Address, $src$$constant);
9664 %}
9665 ins_pipe(ialu_mem_imm);
9666 %}
9667
9668 // Xor Instructions
9669 // Xor Register with Register
9670 instruct xorI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
9671 %{
9672 match(Set dst (XorI dst src));
9673 effect(KILL cr);
9674
9675 format %{ "xorl $dst, $src\t# int" %}
9676 ins_encode %{
9677 __ xorl($dst$$Register, $src$$Register);
9678 %}
9679 ins_pipe(ialu_reg_reg);
9680 %}
9681
9682 // Xor Register with Immediate -1
9683 instruct xorI_rReg_im1(rRegI dst, immI_M1 imm) %{
9684 match(Set dst (XorI dst imm));
9685
9686 format %{ "not $dst" %}
9687 ins_encode %{
9688 __ notl($dst$$Register);
9689 %}
9690 ins_pipe(ialu_reg);
9691 %}
9692
9693 // Xor Register with Immediate
9694 instruct xorI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
9695 %{
9696 match(Set dst (XorI dst src));
9697 effect(KILL cr);
9698
9699 format %{ "xorl $dst, $src\t# int" %}
9700 ins_encode %{
9701 __ xorl($dst$$Register, $src$$constant);
9702 %}
9703 ins_pipe(ialu_reg);
9704 %}
9705
9706 // Xor Register with Memory
9707 instruct xorI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
9708 %{
9709 match(Set dst (XorI dst (LoadI src)));
9710 effect(KILL cr);
9711
9712 ins_cost(125);
9713 format %{ "xorl $dst, $src\t# int" %}
9714 ins_encode %{
9715 __ xorl($dst$$Register, $src$$Address);
9716 %}
9717 ins_pipe(ialu_reg_mem);
9718 %}
9719
9720 // Xor Memory with Register
9721 instruct xorB_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9722 %{
9723 match(Set dst (StoreB dst (XorI (LoadB dst) src)));
9724 effect(KILL cr);
9725
9726 ins_cost(150);
9727 format %{ "xorb $dst, $src\t# byte" %}
9728 ins_encode %{
9729 __ xorb($dst$$Address, $src$$Register);
9730 %}
9731 ins_pipe(ialu_mem_reg);
9732 %}
9733
9734 instruct xorI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9735 %{
9736 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
9737 effect(KILL cr);
9738
9739 ins_cost(150);
9740 format %{ "xorl $dst, $src\t# int" %}
9741 ins_encode %{
9742 __ xorl($dst$$Address, $src$$Register);
9743 %}
9744 ins_pipe(ialu_mem_reg);
9745 %}
9746
9747 // Xor Memory with Immediate
9748 instruct xorI_mem_imm(memory dst, immI src, rFlagsReg cr)
9749 %{
9750 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
9751 effect(KILL cr);
9752
9753 ins_cost(125);
9754 format %{ "xorl $dst, $src\t# int" %}
9755 ins_encode %{
9756 __ xorl($dst$$Address, $src$$constant);
9757 %}
9758 ins_pipe(ialu_mem_imm);
9759 %}
9760
9761
9762 // Long Logical Instructions
9763
9764 // And Instructions
9765 // And Register with Register
9766 instruct andL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
9767 %{
9768 match(Set dst (AndL dst src));
9769 effect(KILL cr);
9770
9771 format %{ "andq $dst, $src\t# long" %}
9772 ins_encode %{
9773 __ andq($dst$$Register, $src$$Register);
9774 %}
9775 ins_pipe(ialu_reg_reg);
9776 %}
9777
9778 // And Register with Immediate 255
9779 instruct andL_rReg_imm255(rRegL dst, immL_255 src)
9780 %{
9781 match(Set dst (AndL dst src));
9782
9783 format %{ "movzbq $dst, $dst\t# long & 0xFF" %}
9784 ins_encode %{
9785 __ movzbq($dst$$Register, $dst$$Register);
9786 %}
9787 ins_pipe(ialu_reg);
9788 %}
9789
9790 // And Register with Immediate 65535
9791 instruct andL_rReg_imm65535(rRegL dst, immL_65535 src)
9792 %{
9793 match(Set dst (AndL dst src));
9794
9795 format %{ "movzwq $dst, $dst\t# long & 0xFFFF" %}
9796 ins_encode %{
9797 __ movzwq($dst$$Register, $dst$$Register);
9798 %}
9799 ins_pipe(ialu_reg);
9800 %}
9801
9802 // And Register with Immediate
9803 instruct andL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
9804 %{
9805 match(Set dst (AndL dst src));
9806 effect(KILL cr);
9807
9808 format %{ "andq $dst, $src\t# long" %}
9809 ins_encode %{
9810 __ andq($dst$$Register, $src$$constant);
9811 %}
9812 ins_pipe(ialu_reg);
9813 %}
9814
9815 // And Register with Memory
9816 instruct andL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
9817 %{
9818 match(Set dst (AndL dst (LoadL src)));
9819 effect(KILL cr);
9820
9821 ins_cost(125);
9822 format %{ "andq $dst, $src\t# long" %}
9823 ins_encode %{
9824 __ andq($dst$$Register, $src$$Address);
9825 %}
9826 ins_pipe(ialu_reg_mem);
9827 %}
9828
9829 // And Memory with Register
9830 instruct andL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
9831 %{
9832 match(Set dst (StoreL dst (AndL (LoadL dst) src)));
9833 effect(KILL cr);
9834
9835 ins_cost(150);
9836 format %{ "andq $dst, $src\t# long" %}
9837 ins_encode %{
9838 __ andq($dst$$Address, $src$$Register);
9839 %}
9840 ins_pipe(ialu_mem_reg);
9841 %}
9842
9843 // And Memory with Immediate
9844 instruct andL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
9845 %{
9846 match(Set dst (StoreL dst (AndL (LoadL dst) src)));
9847 effect(KILL cr);
9848
9849 ins_cost(125);
9850 format %{ "andq $dst, $src\t# long" %}
9851 ins_encode %{
9852 __ andq($dst$$Address, $src$$constant);
9853 %}
9854 ins_pipe(ialu_mem_imm);
9855 %}
9856
9857 instruct btrL_mem_imm(memory dst, immL_NotPow2 con, rFlagsReg cr)
9858 %{
9859 // con should be a pure 64-bit immediate given that not(con) is a power of 2
9860 // because AND/OR works well enough for 8/32-bit values.
9861 predicate(log2i_graceful(~n->in(3)->in(2)->get_long()) > 30);
9862
9863 match(Set dst (StoreL dst (AndL (LoadL dst) con)));
9864 effect(KILL cr);
9865
9866 ins_cost(125);
9867 format %{ "btrq $dst, log2(not($con))\t# long" %}
9868 ins_encode %{
9869 __ btrq($dst$$Address, log2i_exact((julong)~$con$$constant));
9870 %}
9871 ins_pipe(ialu_mem_imm);
9872 %}
9873
9874 // BMI1 instructions
9875 instruct andnL_rReg_rReg_mem(rRegL dst, rRegL src1, memory src2, immL_M1 minus_1, rFlagsReg cr) %{
9876 match(Set dst (AndL (XorL src1 minus_1) (LoadL src2)));
9877 predicate(UseBMI1Instructions);
9878 effect(KILL cr);
9879
9880 ins_cost(125);
9881 format %{ "andnq $dst, $src1, $src2" %}
9882
9883 ins_encode %{
9884 __ andnq($dst$$Register, $src1$$Register, $src2$$Address);
9885 %}
9886 ins_pipe(ialu_reg_mem);
9887 %}
9888
9889 instruct andnL_rReg_rReg_rReg(rRegL dst, rRegL src1, rRegL src2, immL_M1 minus_1, rFlagsReg cr) %{
9890 match(Set dst (AndL (XorL src1 minus_1) src2));
9891 predicate(UseBMI1Instructions);
9892 effect(KILL cr);
9893
9894 format %{ "andnq $dst, $src1, $src2" %}
9895
9896 ins_encode %{
9897 __ andnq($dst$$Register, $src1$$Register, $src2$$Register);
9898 %}
9899 ins_pipe(ialu_reg_mem);
9900 %}
9901
9902 instruct blsiL_rReg_rReg(rRegL dst, rRegL src, immL0 imm_zero, rFlagsReg cr) %{
9903 match(Set dst (AndL (SubL imm_zero src) src));
9904 predicate(UseBMI1Instructions);
9905 effect(KILL cr);
9906
9907 format %{ "blsiq $dst, $src" %}
9908
9909 ins_encode %{
9910 __ blsiq($dst$$Register, $src$$Register);
9911 %}
9912 ins_pipe(ialu_reg);
9913 %}
9914
9915 instruct blsiL_rReg_mem(rRegL dst, memory src, immL0 imm_zero, rFlagsReg cr) %{
9916 match(Set dst (AndL (SubL imm_zero (LoadL src) ) (LoadL src) ));
9917 predicate(UseBMI1Instructions);
9918 effect(KILL cr);
9919
9920 ins_cost(125);
9921 format %{ "blsiq $dst, $src" %}
9922
9923 ins_encode %{
9924 __ blsiq($dst$$Register, $src$$Address);
9925 %}
9926 ins_pipe(ialu_reg_mem);
9927 %}
9928
9929 instruct blsmskL_rReg_mem(rRegL dst, memory src, immL_M1 minus_1, rFlagsReg cr)
9930 %{
9931 match(Set dst (XorL (AddL (LoadL src) minus_1) (LoadL src) ) );
9932 predicate(UseBMI1Instructions);
9933 effect(KILL cr);
9934
9935 ins_cost(125);
9936 format %{ "blsmskq $dst, $src" %}
9937
9938 ins_encode %{
9939 __ blsmskq($dst$$Register, $src$$Address);
9940 %}
9941 ins_pipe(ialu_reg_mem);
9942 %}
9943
9944 instruct blsmskL_rReg_rReg(rRegL dst, rRegL src, immL_M1 minus_1, rFlagsReg cr)
9945 %{
9946 match(Set dst (XorL (AddL src minus_1) src));
9947 predicate(UseBMI1Instructions);
9948 effect(KILL cr);
9949
9950 format %{ "blsmskq $dst, $src" %}
9951
9952 ins_encode %{
9953 __ blsmskq($dst$$Register, $src$$Register);
9954 %}
9955
9956 ins_pipe(ialu_reg);
9957 %}
9958
9959 instruct blsrL_rReg_rReg(rRegL dst, rRegL src, immL_M1 minus_1, rFlagsReg cr)
9960 %{
9961 match(Set dst (AndL (AddL src minus_1) src) );
9962 predicate(UseBMI1Instructions);
9963 effect(KILL cr);
9964
9965 format %{ "blsrq $dst, $src" %}
9966
9967 ins_encode %{
9968 __ blsrq($dst$$Register, $src$$Register);
9969 %}
9970
9971 ins_pipe(ialu_reg);
9972 %}
9973
9974 instruct blsrL_rReg_mem(rRegL dst, memory src, immL_M1 minus_1, rFlagsReg cr)
9975 %{
9976 match(Set dst (AndL (AddL (LoadL src) minus_1) (LoadL src)) );
9977 predicate(UseBMI1Instructions);
9978 effect(KILL cr);
9979
9980 ins_cost(125);
9981 format %{ "blsrq $dst, $src" %}
9982
9983 ins_encode %{
9984 __ blsrq($dst$$Register, $src$$Address);
9985 %}
9986
9987 ins_pipe(ialu_reg);
9988 %}
9989
9990 // Or Instructions
9991 // Or Register with Register
9992 instruct orL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
9993 %{
9994 match(Set dst (OrL dst src));
9995 effect(KILL cr);
9996
9997 format %{ "orq $dst, $src\t# long" %}
9998 ins_encode %{
9999 __ orq($dst$$Register, $src$$Register);
10000 %}
10001 ins_pipe(ialu_reg_reg);
10002 %}
10003
10004 // Use any_RegP to match R15 (TLS register) without spilling.
10005 instruct orL_rReg_castP2X(rRegL dst, any_RegP src, rFlagsReg cr) %{
10006 match(Set dst (OrL dst (CastP2X src)));
10007 effect(KILL cr);
10008
10009 format %{ "orq $dst, $src\t# long" %}
10010 ins_encode %{
10011 __ orq($dst$$Register, $src$$Register);
10012 %}
10013 ins_pipe(ialu_reg_reg);
10014 %}
10015
10016
10017 // Or Register with Immediate
10018 instruct orL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
10019 %{
10020 match(Set dst (OrL dst src));
10021 effect(KILL cr);
10022
10023 format %{ "orq $dst, $src\t# long" %}
10024 ins_encode %{
10025 __ orq($dst$$Register, $src$$constant);
10026 %}
10027 ins_pipe(ialu_reg);
10028 %}
10029
10030 // Or Register with Memory
10031 instruct orL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
10032 %{
10033 match(Set dst (OrL dst (LoadL src)));
10034 effect(KILL cr);
10035
10036 ins_cost(125);
10037 format %{ "orq $dst, $src\t# long" %}
10038 ins_encode %{
10039 __ orq($dst$$Register, $src$$Address);
10040 %}
10041 ins_pipe(ialu_reg_mem);
10042 %}
10043
10044 // Or Memory with Register
10045 instruct orL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
10046 %{
10047 match(Set dst (StoreL dst (OrL (LoadL dst) src)));
10048 effect(KILL cr);
10049
10050 ins_cost(150);
10051 format %{ "orq $dst, $src\t# long" %}
10052 ins_encode %{
10053 __ orq($dst$$Address, $src$$Register);
10054 %}
10055 ins_pipe(ialu_mem_reg);
10056 %}
10057
10058 // Or Memory with Immediate
10059 instruct orL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
10060 %{
10061 match(Set dst (StoreL dst (OrL (LoadL dst) src)));
10062 effect(KILL cr);
10063
10064 ins_cost(125);
10065 format %{ "orq $dst, $src\t# long" %}
10066 ins_encode %{
10067 __ orq($dst$$Address, $src$$constant);
10068 %}
10069 ins_pipe(ialu_mem_imm);
10070 %}
10071
10072 instruct btsL_mem_imm(memory dst, immL_Pow2 con, rFlagsReg cr)
10073 %{
10074 // con should be a pure 64-bit power of 2 immediate
10075 // because AND/OR works well enough for 8/32-bit values.
10076 predicate(log2i_graceful(n->in(3)->in(2)->get_long()) > 31);
10077
10078 match(Set dst (StoreL dst (OrL (LoadL dst) con)));
10079 effect(KILL cr);
10080
10081 ins_cost(125);
10082 format %{ "btsq $dst, log2($con)\t# long" %}
10083 ins_encode %{
10084 __ btsq($dst$$Address, log2i_exact((julong)$con$$constant));
10085 %}
10086 ins_pipe(ialu_mem_imm);
10087 %}
10088
10089 // Xor Instructions
10090 // Xor Register with Register
10091 instruct xorL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
10092 %{
10093 match(Set dst (XorL dst src));
10094 effect(KILL cr);
10095
10096 format %{ "xorq $dst, $src\t# long" %}
10097 ins_encode %{
10098 __ xorq($dst$$Register, $src$$Register);
10099 %}
10100 ins_pipe(ialu_reg_reg);
10101 %}
10102
10103 // Xor Register with Immediate -1
10104 instruct xorL_rReg_im1(rRegL dst, immL_M1 imm) %{
10105 match(Set dst (XorL dst imm));
10106
10107 format %{ "notq $dst" %}
10108 ins_encode %{
10109 __ notq($dst$$Register);
10110 %}
10111 ins_pipe(ialu_reg);
10112 %}
10113
10114 // Xor Register with Immediate
10115 instruct xorL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
10116 %{
10117 match(Set dst (XorL dst src));
10118 effect(KILL cr);
10119
10120 format %{ "xorq $dst, $src\t# long" %}
10121 ins_encode %{
10122 __ xorq($dst$$Register, $src$$constant);
10123 %}
10124 ins_pipe(ialu_reg);
10125 %}
10126
10127 // Xor Register with Memory
10128 instruct xorL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
10129 %{
10130 match(Set dst (XorL dst (LoadL src)));
10131 effect(KILL cr);
10132
10133 ins_cost(125);
10134 format %{ "xorq $dst, $src\t# long" %}
10135 ins_encode %{
10136 __ xorq($dst$$Register, $src$$Address);
10137 %}
10138 ins_pipe(ialu_reg_mem);
10139 %}
10140
10141 // Xor Memory with Register
10142 instruct xorL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
10143 %{
10144 match(Set dst (StoreL dst (XorL (LoadL dst) src)));
10145 effect(KILL cr);
10146
10147 ins_cost(150);
10148 format %{ "xorq $dst, $src\t# long" %}
10149 ins_encode %{
10150 __ xorq($dst$$Address, $src$$Register);
10151 %}
10152 ins_pipe(ialu_mem_reg);
10153 %}
10154
10155 // Xor Memory with Immediate
10156 instruct xorL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
10157 %{
10158 match(Set dst (StoreL dst (XorL (LoadL dst) src)));
10159 effect(KILL cr);
10160
10161 ins_cost(125);
10162 format %{ "xorq $dst, $src\t# long" %}
10163 ins_encode %{
10164 __ xorq($dst$$Address, $src$$constant);
10165 %}
10166 ins_pipe(ialu_mem_imm);
10167 %}
10168
10169 // Convert Int to Boolean
10170 instruct convI2B(rRegI dst, rRegI src, rFlagsReg cr)
10171 %{
10172 match(Set dst (Conv2B src));
10173 effect(KILL cr);
10174
10175 format %{ "testl $src, $src\t# ci2b\n\t"
10176 "setnz $dst\n\t"
10177 "movzbl $dst, $dst" %}
10178 ins_encode %{
10179 __ testl($src$$Register, $src$$Register);
10180 __ set_byte_if_not_zero($dst$$Register);
10181 __ movzbl($dst$$Register, $dst$$Register);
10182 %}
10183 ins_pipe(pipe_slow); // XXX
10184 %}
10185
10186 // Convert Pointer to Boolean
10187 instruct convP2B(rRegI dst, rRegP src, rFlagsReg cr)
10188 %{
10189 match(Set dst (Conv2B src));
10190 effect(KILL cr);
10191
10192 format %{ "testq $src, $src\t# cp2b\n\t"
10193 "setnz $dst\n\t"
10194 "movzbl $dst, $dst" %}
10195 ins_encode %{
10196 __ testq($src$$Register, $src$$Register);
10197 __ set_byte_if_not_zero($dst$$Register);
10198 __ movzbl($dst$$Register, $dst$$Register);
10199 %}
10200 ins_pipe(pipe_slow); // XXX
10201 %}
10202
10203 instruct cmpLTMask(rRegI dst, rRegI p, rRegI q, rFlagsReg cr)
10204 %{
10205 match(Set dst (CmpLTMask p q));
10206 effect(KILL cr);
10207
10208 ins_cost(400);
10209 format %{ "cmpl $p, $q\t# cmpLTMask\n\t"
10210 "setlt $dst\n\t"
10211 "movzbl $dst, $dst\n\t"
10212 "negl $dst" %}
10213 ins_encode %{
10214 __ cmpl($p$$Register, $q$$Register);
10215 __ setl($dst$$Register);
10216 __ movzbl($dst$$Register, $dst$$Register);
10217 __ negl($dst$$Register);
10218 %}
10219 ins_pipe(pipe_slow);
10220 %}
10221
10222 instruct cmpLTMask0(rRegI dst, immI_0 zero, rFlagsReg cr)
10223 %{
10224 match(Set dst (CmpLTMask dst zero));
10225 effect(KILL cr);
10226
10227 ins_cost(100);
10228 format %{ "sarl $dst, #31\t# cmpLTMask0" %}
10229 ins_encode %{
10230 __ sarl($dst$$Register, 31);
10231 %}
10232 ins_pipe(ialu_reg);
10233 %}
10234
10235 /* Better to save a register than avoid a branch */
10236 instruct cadd_cmpLTMask(rRegI p, rRegI q, rRegI y, rFlagsReg cr)
10237 %{
10238 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
10239 effect(KILL cr);
10240 ins_cost(300);
10241 format %{ "subl $p,$q\t# cadd_cmpLTMask\n\t"
10242 "jge done\n\t"
10243 "addl $p,$y\n"
10244 "done: " %}
10245 ins_encode %{
10246 Register Rp = $p$$Register;
10247 Register Rq = $q$$Register;
10248 Register Ry = $y$$Register;
10249 Label done;
10250 __ subl(Rp, Rq);
10251 __ jccb(Assembler::greaterEqual, done);
10252 __ addl(Rp, Ry);
10253 __ bind(done);
10254 %}
10255 ins_pipe(pipe_cmplt);
10256 %}
10257
10258 /* Better to save a register than avoid a branch */
10259 instruct and_cmpLTMask(rRegI p, rRegI q, rRegI y, rFlagsReg cr)
10260 %{
10261 match(Set y (AndI (CmpLTMask p q) y));
10262 effect(KILL cr);
10263
10264 ins_cost(300);
10265
10266 format %{ "cmpl $p, $q\t# and_cmpLTMask\n\t"
10267 "jlt done\n\t"
10268 "xorl $y, $y\n"
10269 "done: " %}
10270 ins_encode %{
10271 Register Rp = $p$$Register;
10272 Register Rq = $q$$Register;
10273 Register Ry = $y$$Register;
10274 Label done;
10275 __ cmpl(Rp, Rq);
10276 __ jccb(Assembler::less, done);
10277 __ xorl(Ry, Ry);
10278 __ bind(done);
10279 %}
10280 ins_pipe(pipe_cmplt);
10281 %}
10282
10283
10284 //---------- FP Instructions------------------------------------------------
10285
10286 instruct cmpF_cc_reg(rFlagsRegU cr, regF src1, regF src2)
10287 %{
10288 match(Set cr (CmpF src1 src2));
10289
10290 ins_cost(145);
10291 format %{ "ucomiss $src1, $src2\n\t"
10292 "jnp,s exit\n\t"
10293 "pushfq\t# saw NaN, set CF\n\t"
10294 "andq [rsp], #0xffffff2b\n\t"
10295 "popfq\n"
10296 "exit:" %}
10297 ins_encode %{
10298 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10299 emit_cmpfp_fixup(_masm);
10300 %}
10301 ins_pipe(pipe_slow);
10302 %}
10303
10304 instruct cmpF_cc_reg_CF(rFlagsRegUCF cr, regF src1, regF src2) %{
10305 match(Set cr (CmpF src1 src2));
10306
10307 ins_cost(100);
10308 format %{ "ucomiss $src1, $src2" %}
10309 ins_encode %{
10310 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10311 %}
10312 ins_pipe(pipe_slow);
10313 %}
10314
10315 instruct cmpF_cc_mem(rFlagsRegU cr, regF src1, memory src2)
10316 %{
10317 match(Set cr (CmpF src1 (LoadF src2)));
10318
10319 ins_cost(145);
10320 format %{ "ucomiss $src1, $src2\n\t"
10321 "jnp,s exit\n\t"
10322 "pushfq\t# saw NaN, set CF\n\t"
10323 "andq [rsp], #0xffffff2b\n\t"
10324 "popfq\n"
10325 "exit:" %}
10326 ins_encode %{
10327 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10328 emit_cmpfp_fixup(_masm);
10329 %}
10330 ins_pipe(pipe_slow);
10331 %}
10332
10333 instruct cmpF_cc_memCF(rFlagsRegUCF cr, regF src1, memory src2) %{
10334 match(Set cr (CmpF src1 (LoadF src2)));
10335
10336 ins_cost(100);
10337 format %{ "ucomiss $src1, $src2" %}
10338 ins_encode %{
10339 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10340 %}
10341 ins_pipe(pipe_slow);
10342 %}
10343
10344 instruct cmpF_cc_imm(rFlagsRegU cr, regF src, immF con) %{
10345 match(Set cr (CmpF src con));
10346
10347 ins_cost(145);
10348 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con\n\t"
10349 "jnp,s exit\n\t"
10350 "pushfq\t# saw NaN, set CF\n\t"
10351 "andq [rsp], #0xffffff2b\n\t"
10352 "popfq\n"
10353 "exit:" %}
10354 ins_encode %{
10355 __ ucomiss($src$$XMMRegister, $constantaddress($con));
10356 emit_cmpfp_fixup(_masm);
10357 %}
10358 ins_pipe(pipe_slow);
10359 %}
10360
10361 instruct cmpF_cc_immCF(rFlagsRegUCF cr, regF src, immF con) %{
10362 match(Set cr (CmpF src con));
10363 ins_cost(100);
10364 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con" %}
10365 ins_encode %{
10366 __ ucomiss($src$$XMMRegister, $constantaddress($con));
10367 %}
10368 ins_pipe(pipe_slow);
10369 %}
10370
10371 instruct cmpD_cc_reg(rFlagsRegU cr, regD src1, regD src2)
10372 %{
10373 match(Set cr (CmpD src1 src2));
10374
10375 ins_cost(145);
10376 format %{ "ucomisd $src1, $src2\n\t"
10377 "jnp,s exit\n\t"
10378 "pushfq\t# saw NaN, set CF\n\t"
10379 "andq [rsp], #0xffffff2b\n\t"
10380 "popfq\n"
10381 "exit:" %}
10382 ins_encode %{
10383 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
10384 emit_cmpfp_fixup(_masm);
10385 %}
10386 ins_pipe(pipe_slow);
10387 %}
10388
10389 instruct cmpD_cc_reg_CF(rFlagsRegUCF cr, regD src1, regD src2) %{
10390 match(Set cr (CmpD src1 src2));
10391
10392 ins_cost(100);
10393 format %{ "ucomisd $src1, $src2 test" %}
10394 ins_encode %{
10395 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
10396 %}
10397 ins_pipe(pipe_slow);
10398 %}
10399
10400 instruct cmpD_cc_mem(rFlagsRegU cr, regD src1, memory src2)
10401 %{
10402 match(Set cr (CmpD src1 (LoadD src2)));
10403
10404 ins_cost(145);
10405 format %{ "ucomisd $src1, $src2\n\t"
10406 "jnp,s exit\n\t"
10407 "pushfq\t# saw NaN, set CF\n\t"
10408 "andq [rsp], #0xffffff2b\n\t"
10409 "popfq\n"
10410 "exit:" %}
10411 ins_encode %{
10412 __ ucomisd($src1$$XMMRegister, $src2$$Address);
10413 emit_cmpfp_fixup(_masm);
10414 %}
10415 ins_pipe(pipe_slow);
10416 %}
10417
10418 instruct cmpD_cc_memCF(rFlagsRegUCF cr, regD src1, memory src2) %{
10419 match(Set cr (CmpD src1 (LoadD src2)));
10420
10421 ins_cost(100);
10422 format %{ "ucomisd $src1, $src2" %}
10423 ins_encode %{
10424 __ ucomisd($src1$$XMMRegister, $src2$$Address);
10425 %}
10426 ins_pipe(pipe_slow);
10427 %}
10428
10429 instruct cmpD_cc_imm(rFlagsRegU cr, regD src, immD con) %{
10430 match(Set cr (CmpD src con));
10431
10432 ins_cost(145);
10433 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con\n\t"
10434 "jnp,s exit\n\t"
10435 "pushfq\t# saw NaN, set CF\n\t"
10436 "andq [rsp], #0xffffff2b\n\t"
10437 "popfq\n"
10438 "exit:" %}
10439 ins_encode %{
10440 __ ucomisd($src$$XMMRegister, $constantaddress($con));
10441 emit_cmpfp_fixup(_masm);
10442 %}
10443 ins_pipe(pipe_slow);
10444 %}
10445
10446 instruct cmpD_cc_immCF(rFlagsRegUCF cr, regD src, immD con) %{
10447 match(Set cr (CmpD src con));
10448 ins_cost(100);
10449 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con" %}
10450 ins_encode %{
10451 __ ucomisd($src$$XMMRegister, $constantaddress($con));
10452 %}
10453 ins_pipe(pipe_slow);
10454 %}
10455
10456 // Compare into -1,0,1
10457 instruct cmpF_reg(rRegI dst, regF src1, regF src2, rFlagsReg cr)
10458 %{
10459 match(Set dst (CmpF3 src1 src2));
10460 effect(KILL cr);
10461
10462 ins_cost(275);
10463 format %{ "ucomiss $src1, $src2\n\t"
10464 "movl $dst, #-1\n\t"
10465 "jp,s done\n\t"
10466 "jb,s done\n\t"
10467 "setne $dst\n\t"
10468 "movzbl $dst, $dst\n"
10469 "done:" %}
10470 ins_encode %{
10471 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10472 emit_cmpfp3(_masm, $dst$$Register);
10473 %}
10474 ins_pipe(pipe_slow);
10475 %}
10476
10477 // Compare into -1,0,1
10478 instruct cmpF_mem(rRegI dst, regF src1, memory src2, rFlagsReg cr)
10479 %{
10480 match(Set dst (CmpF3 src1 (LoadF src2)));
10481 effect(KILL cr);
10482
10483 ins_cost(275);
10484 format %{ "ucomiss $src1, $src2\n\t"
10485 "movl $dst, #-1\n\t"
10486 "jp,s done\n\t"
10487 "jb,s done\n\t"
10488 "setne $dst\n\t"
10489 "movzbl $dst, $dst\n"
10490 "done:" %}
10491 ins_encode %{
10492 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10493 emit_cmpfp3(_masm, $dst$$Register);
10494 %}
10495 ins_pipe(pipe_slow);
10496 %}
10497
10498 // Compare into -1,0,1
10499 instruct cmpF_imm(rRegI dst, regF src, immF con, rFlagsReg cr) %{
10500 match(Set dst (CmpF3 src con));
10501 effect(KILL cr);
10502
10503 ins_cost(275);
10504 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con\n\t"
10505 "movl $dst, #-1\n\t"
10506 "jp,s done\n\t"
10507 "jb,s done\n\t"
10508 "setne $dst\n\t"
10509 "movzbl $dst, $dst\n"
10510 "done:" %}
10511 ins_encode %{
10512 __ ucomiss($src$$XMMRegister, $constantaddress($con));
10513 emit_cmpfp3(_masm, $dst$$Register);
10514 %}
10515 ins_pipe(pipe_slow);
10516 %}
10517
10518 // Compare into -1,0,1
10519 instruct cmpD_reg(rRegI dst, regD src1, regD src2, rFlagsReg cr)
10520 %{
10521 match(Set dst (CmpD3 src1 src2));
10522 effect(KILL cr);
10523
10524 ins_cost(275);
10525 format %{ "ucomisd $src1, $src2\n\t"
10526 "movl $dst, #-1\n\t"
10527 "jp,s done\n\t"
10528 "jb,s done\n\t"
10529 "setne $dst\n\t"
10530 "movzbl $dst, $dst\n"
10531 "done:" %}
10532 ins_encode %{
10533 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
10534 emit_cmpfp3(_masm, $dst$$Register);
10535 %}
10536 ins_pipe(pipe_slow);
10537 %}
10538
10539 // Compare into -1,0,1
10540 instruct cmpD_mem(rRegI dst, regD src1, memory src2, rFlagsReg cr)
10541 %{
10542 match(Set dst (CmpD3 src1 (LoadD src2)));
10543 effect(KILL cr);
10544
10545 ins_cost(275);
10546 format %{ "ucomisd $src1, $src2\n\t"
10547 "movl $dst, #-1\n\t"
10548 "jp,s done\n\t"
10549 "jb,s done\n\t"
10550 "setne $dst\n\t"
10551 "movzbl $dst, $dst\n"
10552 "done:" %}
10553 ins_encode %{
10554 __ ucomisd($src1$$XMMRegister, $src2$$Address);
10555 emit_cmpfp3(_masm, $dst$$Register);
10556 %}
10557 ins_pipe(pipe_slow);
10558 %}
10559
10560 // Compare into -1,0,1
10561 instruct cmpD_imm(rRegI dst, regD src, immD con, rFlagsReg cr) %{
10562 match(Set dst (CmpD3 src con));
10563 effect(KILL cr);
10564
10565 ins_cost(275);
10566 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con\n\t"
10567 "movl $dst, #-1\n\t"
10568 "jp,s done\n\t"
10569 "jb,s done\n\t"
10570 "setne $dst\n\t"
10571 "movzbl $dst, $dst\n"
10572 "done:" %}
10573 ins_encode %{
10574 __ ucomisd($src$$XMMRegister, $constantaddress($con));
10575 emit_cmpfp3(_masm, $dst$$Register);
10576 %}
10577 ins_pipe(pipe_slow);
10578 %}
10579
10580 //----------Arithmetic Conversion Instructions---------------------------------
10581
10582 instruct convF2D_reg_reg(regD dst, regF src)
10583 %{
10584 match(Set dst (ConvF2D src));
10585
10586 format %{ "cvtss2sd $dst, $src" %}
10587 ins_encode %{
10588 __ cvtss2sd ($dst$$XMMRegister, $src$$XMMRegister);
10589 %}
10590 ins_pipe(pipe_slow); // XXX
10591 %}
10592
10593 instruct convF2D_reg_mem(regD dst, memory src)
10594 %{
10595 match(Set dst (ConvF2D (LoadF src)));
10596
10597 format %{ "cvtss2sd $dst, $src" %}
10598 ins_encode %{
10599 __ cvtss2sd ($dst$$XMMRegister, $src$$Address);
10600 %}
10601 ins_pipe(pipe_slow); // XXX
10602 %}
10603
10604 instruct convD2F_reg_reg(regF dst, regD src)
10605 %{
10606 match(Set dst (ConvD2F src));
10607
10608 format %{ "cvtsd2ss $dst, $src" %}
10609 ins_encode %{
10610 __ cvtsd2ss ($dst$$XMMRegister, $src$$XMMRegister);
10611 %}
10612 ins_pipe(pipe_slow); // XXX
10613 %}
10614
10615 instruct convD2F_reg_mem(regF dst, memory src)
10616 %{
10617 match(Set dst (ConvD2F (LoadD src)));
10618
10619 format %{ "cvtsd2ss $dst, $src" %}
10620 ins_encode %{
10621 __ cvtsd2ss ($dst$$XMMRegister, $src$$Address);
10622 %}
10623 ins_pipe(pipe_slow); // XXX
10624 %}
10625
10626 // XXX do mem variants
10627 instruct convF2I_reg_reg(rRegI dst, regF src, rFlagsReg cr)
10628 %{
10629 match(Set dst (ConvF2I src));
10630 effect(KILL cr);
10631 format %{ "convert_f2i $dst,$src" %}
10632 ins_encode %{
10633 __ convert_f2i($dst$$Register, $src$$XMMRegister);
10634 %}
10635 ins_pipe(pipe_slow);
10636 %}
10637
10638 instruct convF2L_reg_reg(rRegL dst, regF src, rFlagsReg cr)
10639 %{
10640 match(Set dst (ConvF2L src));
10641 effect(KILL cr);
10642 format %{ "convert_f2l $dst,$src"%}
10643 ins_encode %{
10644 __ convert_f2l($dst$$Register, $src$$XMMRegister);
10645 %}
10646 ins_pipe(pipe_slow);
10647 %}
10648
10649 instruct convD2I_reg_reg(rRegI dst, regD src, rFlagsReg cr)
10650 %{
10651 match(Set dst (ConvD2I src));
10652 effect(KILL cr);
10653 format %{ "convert_d2i $dst,$src"%}
10654 ins_encode %{
10655 __ convert_d2i($dst$$Register, $src$$XMMRegister);
10656 %}
10657 ins_pipe(pipe_slow);
10658 %}
10659
10660 instruct convD2L_reg_reg(rRegL dst, regD src, rFlagsReg cr)
10661 %{
10662 match(Set dst (ConvD2L src));
10663 effect(KILL cr);
10664 format %{ "convert_d2l $dst,$src"%}
10665 ins_encode %{
10666 __ convert_d2l($dst$$Register, $src$$XMMRegister);
10667 %}
10668 ins_pipe(pipe_slow);
10669 %}
10670
10671 instruct convI2F_reg_reg(regF dst, rRegI src)
10672 %{
10673 predicate(!UseXmmI2F);
10674 match(Set dst (ConvI2F src));
10675
10676 format %{ "cvtsi2ssl $dst, $src\t# i2f" %}
10677 ins_encode %{
10678 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Register);
10679 %}
10680 ins_pipe(pipe_slow); // XXX
10681 %}
10682
10683 instruct convI2F_reg_mem(regF dst, memory src)
10684 %{
10685 match(Set dst (ConvI2F (LoadI src)));
10686
10687 format %{ "cvtsi2ssl $dst, $src\t# i2f" %}
10688 ins_encode %{
10689 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Address);
10690 %}
10691 ins_pipe(pipe_slow); // XXX
10692 %}
10693
10694 instruct convI2D_reg_reg(regD dst, rRegI src)
10695 %{
10696 predicate(!UseXmmI2D);
10697 match(Set dst (ConvI2D src));
10698
10699 format %{ "cvtsi2sdl $dst, $src\t# i2d" %}
10700 ins_encode %{
10701 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Register);
10702 %}
10703 ins_pipe(pipe_slow); // XXX
10704 %}
10705
10706 instruct convI2D_reg_mem(regD dst, memory src)
10707 %{
10708 match(Set dst (ConvI2D (LoadI src)));
10709
10710 format %{ "cvtsi2sdl $dst, $src\t# i2d" %}
10711 ins_encode %{
10712 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Address);
10713 %}
10714 ins_pipe(pipe_slow); // XXX
10715 %}
10716
10717 instruct convXI2F_reg(regF dst, rRegI src)
10718 %{
10719 predicate(UseXmmI2F);
10720 match(Set dst (ConvI2F src));
10721
10722 format %{ "movdl $dst, $src\n\t"
10723 "cvtdq2psl $dst, $dst\t# i2f" %}
10724 ins_encode %{
10725 __ movdl($dst$$XMMRegister, $src$$Register);
10726 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister);
10727 %}
10728 ins_pipe(pipe_slow); // XXX
10729 %}
10730
10731 instruct convXI2D_reg(regD dst, rRegI src)
10732 %{
10733 predicate(UseXmmI2D);
10734 match(Set dst (ConvI2D src));
10735
10736 format %{ "movdl $dst, $src\n\t"
10737 "cvtdq2pdl $dst, $dst\t# i2d" %}
10738 ins_encode %{
10739 __ movdl($dst$$XMMRegister, $src$$Register);
10740 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister);
10741 %}
10742 ins_pipe(pipe_slow); // XXX
10743 %}
10744
10745 instruct convL2F_reg_reg(regF dst, rRegL src)
10746 %{
10747 match(Set dst (ConvL2F src));
10748
10749 format %{ "cvtsi2ssq $dst, $src\t# l2f" %}
10750 ins_encode %{
10751 __ cvtsi2ssq ($dst$$XMMRegister, $src$$Register);
10752 %}
10753 ins_pipe(pipe_slow); // XXX
10754 %}
10755
10756 instruct convL2F_reg_mem(regF dst, memory src)
10757 %{
10758 match(Set dst (ConvL2F (LoadL src)));
10759
10760 format %{ "cvtsi2ssq $dst, $src\t# l2f" %}
10761 ins_encode %{
10762 __ cvtsi2ssq ($dst$$XMMRegister, $src$$Address);
10763 %}
10764 ins_pipe(pipe_slow); // XXX
10765 %}
10766
10767 instruct convL2D_reg_reg(regD dst, rRegL src)
10768 %{
10769 match(Set dst (ConvL2D src));
10770
10771 format %{ "cvtsi2sdq $dst, $src\t# l2d" %}
10772 ins_encode %{
10773 __ cvtsi2sdq ($dst$$XMMRegister, $src$$Register);
10774 %}
10775 ins_pipe(pipe_slow); // XXX
10776 %}
10777
10778 instruct convL2D_reg_mem(regD dst, memory src)
10779 %{
10780 match(Set dst (ConvL2D (LoadL src)));
10781
10782 format %{ "cvtsi2sdq $dst, $src\t# l2d" %}
10783 ins_encode %{
10784 __ cvtsi2sdq ($dst$$XMMRegister, $src$$Address);
10785 %}
10786 ins_pipe(pipe_slow); // XXX
10787 %}
10788
10789 instruct convI2L_reg_reg(rRegL dst, rRegI src)
10790 %{
10791 match(Set dst (ConvI2L src));
10792
10793 ins_cost(125);
10794 format %{ "movslq $dst, $src\t# i2l" %}
10795 ins_encode %{
10796 __ movslq($dst$$Register, $src$$Register);
10797 %}
10798 ins_pipe(ialu_reg_reg);
10799 %}
10800
10801 // instruct convI2L_reg_reg_foo(rRegL dst, rRegI src)
10802 // %{
10803 // match(Set dst (ConvI2L src));
10804 // // predicate(_kids[0]->_leaf->as_Type()->type()->is_int()->_lo >= 0 &&
10805 // // _kids[0]->_leaf->as_Type()->type()->is_int()->_hi >= 0);
10806 // predicate(((const TypeNode*) n)->type()->is_long()->_hi ==
10807 // (unsigned int) ((const TypeNode*) n)->type()->is_long()->_hi &&
10808 // ((const TypeNode*) n)->type()->is_long()->_lo ==
10809 // (unsigned int) ((const TypeNode*) n)->type()->is_long()->_lo);
10810
10811 // format %{ "movl $dst, $src\t# unsigned i2l" %}
10812 // ins_encode(enc_copy(dst, src));
10813 // // opcode(0x63); // needs REX.W
10814 // // ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst,src));
10815 // ins_pipe(ialu_reg_reg);
10816 // %}
10817
10818 // Zero-extend convert int to long
10819 instruct convI2L_reg_reg_zex(rRegL dst, rRegI src, immL_32bits mask)
10820 %{
10821 match(Set dst (AndL (ConvI2L src) mask));
10822
10823 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %}
10824 ins_encode %{
10825 if ($dst$$reg != $src$$reg) {
10826 __ movl($dst$$Register, $src$$Register);
10827 }
10828 %}
10829 ins_pipe(ialu_reg_reg);
10830 %}
10831
10832 // Zero-extend convert int to long
10833 instruct convI2L_reg_mem_zex(rRegL dst, memory src, immL_32bits mask)
10834 %{
10835 match(Set dst (AndL (ConvI2L (LoadI src)) mask));
10836
10837 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %}
10838 ins_encode %{
10839 __ movl($dst$$Register, $src$$Address);
10840 %}
10841 ins_pipe(ialu_reg_mem);
10842 %}
10843
10844 instruct zerox_long_reg_reg(rRegL dst, rRegL src, immL_32bits mask)
10845 %{
10846 match(Set dst (AndL src mask));
10847
10848 format %{ "movl $dst, $src\t# zero-extend long" %}
10849 ins_encode %{
10850 __ movl($dst$$Register, $src$$Register);
10851 %}
10852 ins_pipe(ialu_reg_reg);
10853 %}
10854
10855 instruct convL2I_reg_reg(rRegI dst, rRegL src)
10856 %{
10857 match(Set dst (ConvL2I src));
10858
10859 format %{ "movl $dst, $src\t# l2i" %}
10860 ins_encode %{
10861 __ movl($dst$$Register, $src$$Register);
10862 %}
10863 ins_pipe(ialu_reg_reg);
10864 %}
10865
10866
10867 instruct MoveF2I_stack_reg(rRegI dst, stackSlotF src) %{
10868 match(Set dst (MoveF2I src));
10869 effect(DEF dst, USE src);
10870
10871 ins_cost(125);
10872 format %{ "movl $dst, $src\t# MoveF2I_stack_reg" %}
10873 ins_encode %{
10874 __ movl($dst$$Register, Address(rsp, $src$$disp));
10875 %}
10876 ins_pipe(ialu_reg_mem);
10877 %}
10878
10879 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
10880 match(Set dst (MoveI2F src));
10881 effect(DEF dst, USE src);
10882
10883 ins_cost(125);
10884 format %{ "movss $dst, $src\t# MoveI2F_stack_reg" %}
10885 ins_encode %{
10886 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
10887 %}
10888 ins_pipe(pipe_slow);
10889 %}
10890
10891 instruct MoveD2L_stack_reg(rRegL dst, stackSlotD src) %{
10892 match(Set dst (MoveD2L src));
10893 effect(DEF dst, USE src);
10894
10895 ins_cost(125);
10896 format %{ "movq $dst, $src\t# MoveD2L_stack_reg" %}
10897 ins_encode %{
10898 __ movq($dst$$Register, Address(rsp, $src$$disp));
10899 %}
10900 ins_pipe(ialu_reg_mem);
10901 %}
10902
10903 instruct MoveL2D_stack_reg_partial(regD dst, stackSlotL src) %{
10904 predicate(!UseXmmLoadAndClearUpper);
10905 match(Set dst (MoveL2D src));
10906 effect(DEF dst, USE src);
10907
10908 ins_cost(125);
10909 format %{ "movlpd $dst, $src\t# MoveL2D_stack_reg" %}
10910 ins_encode %{
10911 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
10912 %}
10913 ins_pipe(pipe_slow);
10914 %}
10915
10916 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
10917 predicate(UseXmmLoadAndClearUpper);
10918 match(Set dst (MoveL2D src));
10919 effect(DEF dst, USE src);
10920
10921 ins_cost(125);
10922 format %{ "movsd $dst, $src\t# MoveL2D_stack_reg" %}
10923 ins_encode %{
10924 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
10925 %}
10926 ins_pipe(pipe_slow);
10927 %}
10928
10929
10930 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
10931 match(Set dst (MoveF2I src));
10932 effect(DEF dst, USE src);
10933
10934 ins_cost(95); // XXX
10935 format %{ "movss $dst, $src\t# MoveF2I_reg_stack" %}
10936 ins_encode %{
10937 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
10938 %}
10939 ins_pipe(pipe_slow);
10940 %}
10941
10942 instruct MoveI2F_reg_stack(stackSlotF dst, rRegI src) %{
10943 match(Set dst (MoveI2F src));
10944 effect(DEF dst, USE src);
10945
10946 ins_cost(100);
10947 format %{ "movl $dst, $src\t# MoveI2F_reg_stack" %}
10948 ins_encode %{
10949 __ movl(Address(rsp, $dst$$disp), $src$$Register);
10950 %}
10951 ins_pipe( ialu_mem_reg );
10952 %}
10953
10954 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
10955 match(Set dst (MoveD2L src));
10956 effect(DEF dst, USE src);
10957
10958 ins_cost(95); // XXX
10959 format %{ "movsd $dst, $src\t# MoveL2D_reg_stack" %}
10960 ins_encode %{
10961 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
10962 %}
10963 ins_pipe(pipe_slow);
10964 %}
10965
10966 instruct MoveL2D_reg_stack(stackSlotD dst, rRegL src) %{
10967 match(Set dst (MoveL2D src));
10968 effect(DEF dst, USE src);
10969
10970 ins_cost(100);
10971 format %{ "movq $dst, $src\t# MoveL2D_reg_stack" %}
10972 ins_encode %{
10973 __ movq(Address(rsp, $dst$$disp), $src$$Register);
10974 %}
10975 ins_pipe(ialu_mem_reg);
10976 %}
10977
10978 instruct MoveF2I_reg_reg(rRegI dst, regF src) %{
10979 match(Set dst (MoveF2I src));
10980 effect(DEF dst, USE src);
10981 ins_cost(85);
10982 format %{ "movd $dst,$src\t# MoveF2I" %}
10983 ins_encode %{
10984 __ movdl($dst$$Register, $src$$XMMRegister);
10985 %}
10986 ins_pipe( pipe_slow );
10987 %}
10988
10989 instruct MoveD2L_reg_reg(rRegL dst, regD src) %{
10990 match(Set dst (MoveD2L src));
10991 effect(DEF dst, USE src);
10992 ins_cost(85);
10993 format %{ "movd $dst,$src\t# MoveD2L" %}
10994 ins_encode %{
10995 __ movdq($dst$$Register, $src$$XMMRegister);
10996 %}
10997 ins_pipe( pipe_slow );
10998 %}
10999
11000 instruct MoveI2F_reg_reg(regF dst, rRegI src) %{
11001 match(Set dst (MoveI2F src));
11002 effect(DEF dst, USE src);
11003 ins_cost(100);
11004 format %{ "movd $dst,$src\t# MoveI2F" %}
11005 ins_encode %{
11006 __ movdl($dst$$XMMRegister, $src$$Register);
11007 %}
11008 ins_pipe( pipe_slow );
11009 %}
11010
11011 instruct MoveL2D_reg_reg(regD dst, rRegL src) %{
11012 match(Set dst (MoveL2D src));
11013 effect(DEF dst, USE src);
11014 ins_cost(100);
11015 format %{ "movd $dst,$src\t# MoveL2D" %}
11016 ins_encode %{
11017 __ movdq($dst$$XMMRegister, $src$$Register);
11018 %}
11019 ins_pipe( pipe_slow );
11020 %}
11021
11022 // Fast clearing of an array
11023 // Small ClearArray non-AVX512.
11024 instruct rep_stos(rcx_RegL cnt, rdi_RegP base, regD tmp, rax_RegI zero,
11025 Universe dummy, rFlagsReg cr)
11026 %{
11027 predicate(!((ClearArrayNode*)n)->is_large() && (UseAVX <= 2));
11028 match(Set dummy (ClearArray cnt base));
11029 effect(USE_KILL cnt, USE_KILL base, TEMP tmp, KILL zero, KILL cr);
11030
11031 format %{ $$template
11032 $$emit$$"xorq rax, rax\t# ClearArray:\n\t"
11033 $$emit$$"cmp InitArrayShortSize,rcx\n\t"
11034 $$emit$$"jg LARGE\n\t"
11035 $$emit$$"dec rcx\n\t"
11036 $$emit$$"js DONE\t# Zero length\n\t"
11037 $$emit$$"mov rax,(rdi,rcx,8)\t# LOOP\n\t"
11038 $$emit$$"dec rcx\n\t"
11039 $$emit$$"jge LOOP\n\t"
11040 $$emit$$"jmp DONE\n\t"
11041 $$emit$$"# LARGE:\n\t"
11042 if (UseFastStosb) {
11043 $$emit$$"shlq rcx,3\t# Convert doublewords to bytes\n\t"
11044 $$emit$$"rep stosb\t# Store rax to *rdi++ while rcx--\n\t"
11045 } else if (UseXMMForObjInit) {
11046 $$emit$$"mov rdi,rax\n\t"
11047 $$emit$$"vpxor ymm0,ymm0,ymm0\n\t"
11048 $$emit$$"jmpq L_zero_64_bytes\n\t"
11049 $$emit$$"# L_loop:\t# 64-byte LOOP\n\t"
11050 $$emit$$"vmovdqu ymm0,(rax)\n\t"
11051 $$emit$$"vmovdqu ymm0,0x20(rax)\n\t"
11052 $$emit$$"add 0x40,rax\n\t"
11053 $$emit$$"# L_zero_64_bytes:\n\t"
11054 $$emit$$"sub 0x8,rcx\n\t"
11055 $$emit$$"jge L_loop\n\t"
11056 $$emit$$"add 0x4,rcx\n\t"
11057 $$emit$$"jl L_tail\n\t"
11058 $$emit$$"vmovdqu ymm0,(rax)\n\t"
11059 $$emit$$"add 0x20,rax\n\t"
11060 $$emit$$"sub 0x4,rcx\n\t"
11061 $$emit$$"# L_tail:\t# Clearing tail bytes\n\t"
11062 $$emit$$"add 0x4,rcx\n\t"
11063 $$emit$$"jle L_end\n\t"
11064 $$emit$$"dec rcx\n\t"
11065 $$emit$$"# L_sloop:\t# 8-byte short loop\n\t"
11066 $$emit$$"vmovq xmm0,(rax)\n\t"
11067 $$emit$$"add 0x8,rax\n\t"
11068 $$emit$$"dec rcx\n\t"
11069 $$emit$$"jge L_sloop\n\t"
11070 $$emit$$"# L_end:\n\t"
11071 } else {
11072 $$emit$$"rep stosq\t# Store rax to *rdi++ while rcx--\n\t"
11073 }
11074 $$emit$$"# DONE"
11075 %}
11076 ins_encode %{
11077 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register,
11078 $tmp$$XMMRegister, false, knoreg);
11079 %}
11080 ins_pipe(pipe_slow);
11081 %}
11082
11083 // Small ClearArray AVX512 non-constant length.
11084 instruct rep_stos_evex(rcx_RegL cnt, rdi_RegP base, legRegD tmp, kReg ktmp, rax_RegI zero,
11085 Universe dummy, rFlagsReg cr)
11086 %{
11087 predicate(!((ClearArrayNode*)n)->is_large() && (UseAVX > 2));
11088 match(Set dummy (ClearArray cnt base));
11089 ins_cost(125);
11090 effect(USE_KILL cnt, USE_KILL base, TEMP tmp, TEMP ktmp, KILL zero, KILL cr);
11091
11092 format %{ $$template
11093 $$emit$$"xorq rax, rax\t# ClearArray:\n\t"
11094 $$emit$$"cmp InitArrayShortSize,rcx\n\t"
11095 $$emit$$"jg LARGE\n\t"
11096 $$emit$$"dec rcx\n\t"
11097 $$emit$$"js DONE\t# Zero length\n\t"
11098 $$emit$$"mov rax,(rdi,rcx,8)\t# LOOP\n\t"
11099 $$emit$$"dec rcx\n\t"
11100 $$emit$$"jge LOOP\n\t"
11101 $$emit$$"jmp DONE\n\t"
11102 $$emit$$"# LARGE:\n\t"
11103 if (UseFastStosb) {
11104 $$emit$$"shlq rcx,3\t# Convert doublewords to bytes\n\t"
11105 $$emit$$"rep stosb\t# Store rax to *rdi++ while rcx--\n\t"
11106 } else if (UseXMMForObjInit) {
11107 $$emit$$"mov rdi,rax\n\t"
11108 $$emit$$"vpxor ymm0,ymm0,ymm0\n\t"
11109 $$emit$$"jmpq L_zero_64_bytes\n\t"
11110 $$emit$$"# L_loop:\t# 64-byte LOOP\n\t"
11111 $$emit$$"vmovdqu ymm0,(rax)\n\t"
11112 $$emit$$"vmovdqu ymm0,0x20(rax)\n\t"
11113 $$emit$$"add 0x40,rax\n\t"
11114 $$emit$$"# L_zero_64_bytes:\n\t"
11115 $$emit$$"sub 0x8,rcx\n\t"
11116 $$emit$$"jge L_loop\n\t"
11117 $$emit$$"add 0x4,rcx\n\t"
11118 $$emit$$"jl L_tail\n\t"
11119 $$emit$$"vmovdqu ymm0,(rax)\n\t"
11120 $$emit$$"add 0x20,rax\n\t"
11121 $$emit$$"sub 0x4,rcx\n\t"
11122 $$emit$$"# L_tail:\t# Clearing tail bytes\n\t"
11123 $$emit$$"add 0x4,rcx\n\t"
11124 $$emit$$"jle L_end\n\t"
11125 $$emit$$"dec rcx\n\t"
11126 $$emit$$"# L_sloop:\t# 8-byte short loop\n\t"
11127 $$emit$$"vmovq xmm0,(rax)\n\t"
11128 $$emit$$"add 0x8,rax\n\t"
11129 $$emit$$"dec rcx\n\t"
11130 $$emit$$"jge L_sloop\n\t"
11131 $$emit$$"# L_end:\n\t"
11132 } else {
11133 $$emit$$"rep stosq\t# Store rax to *rdi++ while rcx--\n\t"
11134 }
11135 $$emit$$"# DONE"
11136 %}
11137 ins_encode %{
11138 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register,
11139 $tmp$$XMMRegister, false, $ktmp$$KRegister);
11140 %}
11141 ins_pipe(pipe_slow);
11142 %}
11143
11144 // Large ClearArray non-AVX512.
11145 instruct rep_stos_large(rcx_RegL cnt, rdi_RegP base, regD tmp, rax_RegI zero,
11146 Universe dummy, rFlagsReg cr)
11147 %{
11148 predicate((UseAVX <=2) && ((ClearArrayNode*)n)->is_large());
11149 match(Set dummy (ClearArray cnt base));
11150 effect(USE_KILL cnt, USE_KILL base, TEMP tmp, KILL zero, KILL cr);
11151
11152 format %{ $$template
11153 if (UseFastStosb) {
11154 $$emit$$"xorq rax, rax\t# ClearArray:\n\t"
11155 $$emit$$"shlq rcx,3\t# Convert doublewords to bytes\n\t"
11156 $$emit$$"rep stosb\t# Store rax to *rdi++ while rcx--"
11157 } else if (UseXMMForObjInit) {
11158 $$emit$$"mov rdi,rax\t# ClearArray:\n\t"
11159 $$emit$$"vpxor ymm0,ymm0,ymm0\n\t"
11160 $$emit$$"jmpq L_zero_64_bytes\n\t"
11161 $$emit$$"# L_loop:\t# 64-byte LOOP\n\t"
11162 $$emit$$"vmovdqu ymm0,(rax)\n\t"
11163 $$emit$$"vmovdqu ymm0,0x20(rax)\n\t"
11164 $$emit$$"add 0x40,rax\n\t"
11165 $$emit$$"# L_zero_64_bytes:\n\t"
11166 $$emit$$"sub 0x8,rcx\n\t"
11167 $$emit$$"jge L_loop\n\t"
11168 $$emit$$"add 0x4,rcx\n\t"
11169 $$emit$$"jl L_tail\n\t"
11170 $$emit$$"vmovdqu ymm0,(rax)\n\t"
11171 $$emit$$"add 0x20,rax\n\t"
11172 $$emit$$"sub 0x4,rcx\n\t"
11173 $$emit$$"# L_tail:\t# Clearing tail bytes\n\t"
11174 $$emit$$"add 0x4,rcx\n\t"
11175 $$emit$$"jle L_end\n\t"
11176 $$emit$$"dec rcx\n\t"
11177 $$emit$$"# L_sloop:\t# 8-byte short loop\n\t"
11178 $$emit$$"vmovq xmm0,(rax)\n\t"
11179 $$emit$$"add 0x8,rax\n\t"
11180 $$emit$$"dec rcx\n\t"
11181 $$emit$$"jge L_sloop\n\t"
11182 $$emit$$"# L_end:\n\t"
11183 } else {
11184 $$emit$$"xorq rax, rax\t# ClearArray:\n\t"
11185 $$emit$$"rep stosq\t# Store rax to *rdi++ while rcx--"
11186 }
11187 %}
11188 ins_encode %{
11189 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register,
11190 $tmp$$XMMRegister, true, knoreg);
11191 %}
11192 ins_pipe(pipe_slow);
11193 %}
11194
11195 // Large ClearArray AVX512.
11196 instruct rep_stos_large_evex(rcx_RegL cnt, rdi_RegP base, legRegD tmp, kReg ktmp, rax_RegI zero,
11197 Universe dummy, rFlagsReg cr)
11198 %{
11199 predicate((UseAVX > 2) && ((ClearArrayNode*)n)->is_large());
11200 match(Set dummy (ClearArray cnt base));
11201 effect(USE_KILL cnt, USE_KILL base, TEMP tmp, TEMP ktmp, KILL zero, KILL cr);
11202
11203 format %{ $$template
11204 if (UseFastStosb) {
11205 $$emit$$"xorq rax, rax\t# ClearArray:\n\t"
11206 $$emit$$"shlq rcx,3\t# Convert doublewords to bytes\n\t"
11207 $$emit$$"rep stosb\t# Store rax to *rdi++ while rcx--"
11208 } else if (UseXMMForObjInit) {
11209 $$emit$$"mov rdi,rax\t# ClearArray:\n\t"
11210 $$emit$$"vpxor ymm0,ymm0,ymm0\n\t"
11211 $$emit$$"jmpq L_zero_64_bytes\n\t"
11212 $$emit$$"# L_loop:\t# 64-byte LOOP\n\t"
11213 $$emit$$"vmovdqu ymm0,(rax)\n\t"
11214 $$emit$$"vmovdqu ymm0,0x20(rax)\n\t"
11215 $$emit$$"add 0x40,rax\n\t"
11216 $$emit$$"# L_zero_64_bytes:\n\t"
11217 $$emit$$"sub 0x8,rcx\n\t"
11218 $$emit$$"jge L_loop\n\t"
11219 $$emit$$"add 0x4,rcx\n\t"
11220 $$emit$$"jl L_tail\n\t"
11221 $$emit$$"vmovdqu ymm0,(rax)\n\t"
11222 $$emit$$"add 0x20,rax\n\t"
11223 $$emit$$"sub 0x4,rcx\n\t"
11224 $$emit$$"# L_tail:\t# Clearing tail bytes\n\t"
11225 $$emit$$"add 0x4,rcx\n\t"
11226 $$emit$$"jle L_end\n\t"
11227 $$emit$$"dec rcx\n\t"
11228 $$emit$$"# L_sloop:\t# 8-byte short loop\n\t"
11229 $$emit$$"vmovq xmm0,(rax)\n\t"
11230 $$emit$$"add 0x8,rax\n\t"
11231 $$emit$$"dec rcx\n\t"
11232 $$emit$$"jge L_sloop\n\t"
11233 $$emit$$"# L_end:\n\t"
11234 } else {
11235 $$emit$$"xorq rax, rax\t# ClearArray:\n\t"
11236 $$emit$$"rep stosq\t# Store rax to *rdi++ while rcx--"
11237 }
11238 %}
11239 ins_encode %{
11240 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register,
11241 $tmp$$XMMRegister, true, $ktmp$$KRegister);
11242 %}
11243 ins_pipe(pipe_slow);
11244 %}
11245
11246 // Small ClearArray AVX512 constant length.
11247 instruct rep_stos_im(immL cnt, rRegP base, regD tmp, rRegI zero, kReg ktmp, Universe dummy, rFlagsReg cr)
11248 %{
11249 predicate(!((ClearArrayNode*)n)->is_large() &&
11250 ((UseAVX > 2) && VM_Version::supports_avx512vlbw()));
11251 match(Set dummy (ClearArray cnt base));
11252 ins_cost(100);
11253 effect(TEMP tmp, TEMP zero, TEMP ktmp, KILL cr);
11254 format %{ "clear_mem_imm $base , $cnt \n\t" %}
11255 ins_encode %{
11256 __ clear_mem($base$$Register, $cnt$$constant, $zero$$Register, $tmp$$XMMRegister, $ktmp$$KRegister);
11257 %}
11258 ins_pipe(pipe_slow);
11259 %}
11260
11261 instruct string_compareL(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
11262 rax_RegI result, legRegD tmp1, rFlagsReg cr)
11263 %{
11264 predicate(!VM_Version::supports_avx512vlbw() && ((StrCompNode*)n)->encoding() == StrIntrinsicNode::LL);
11265 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11266 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11267
11268 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
11269 ins_encode %{
11270 __ string_compare($str1$$Register, $str2$$Register,
11271 $cnt1$$Register, $cnt2$$Register, $result$$Register,
11272 $tmp1$$XMMRegister, StrIntrinsicNode::LL, knoreg);
11273 %}
11274 ins_pipe( pipe_slow );
11275 %}
11276
11277 instruct string_compareL_evex(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
11278 rax_RegI result, legRegD tmp1, kReg ktmp, rFlagsReg cr)
11279 %{
11280 predicate(VM_Version::supports_avx512vlbw() && ((StrCompNode*)n)->encoding() == StrIntrinsicNode::LL);
11281 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11282 effect(TEMP tmp1, TEMP ktmp, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11283
11284 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
11285 ins_encode %{
11286 __ string_compare($str1$$Register, $str2$$Register,
11287 $cnt1$$Register, $cnt2$$Register, $result$$Register,
11288 $tmp1$$XMMRegister, StrIntrinsicNode::LL, $ktmp$$KRegister);
11289 %}
11290 ins_pipe( pipe_slow );
11291 %}
11292
11293 instruct string_compareU(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
11294 rax_RegI result, legRegD tmp1, rFlagsReg cr)
11295 %{
11296 predicate(!VM_Version::supports_avx512vlbw() && ((StrCompNode*)n)->encoding() == StrIntrinsicNode::UU);
11297 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11298 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11299
11300 format %{ "String Compare char[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
11301 ins_encode %{
11302 __ string_compare($str1$$Register, $str2$$Register,
11303 $cnt1$$Register, $cnt2$$Register, $result$$Register,
11304 $tmp1$$XMMRegister, StrIntrinsicNode::UU, knoreg);
11305 %}
11306 ins_pipe( pipe_slow );
11307 %}
11308
11309 instruct string_compareU_evex(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
11310 rax_RegI result, legRegD tmp1, kReg ktmp, rFlagsReg cr)
11311 %{
11312 predicate(VM_Version::supports_avx512vlbw() && ((StrCompNode*)n)->encoding() == StrIntrinsicNode::UU);
11313 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11314 effect(TEMP tmp1, TEMP ktmp, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11315
11316 format %{ "String Compare char[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
11317 ins_encode %{
11318 __ string_compare($str1$$Register, $str2$$Register,
11319 $cnt1$$Register, $cnt2$$Register, $result$$Register,
11320 $tmp1$$XMMRegister, StrIntrinsicNode::UU, $ktmp$$KRegister);
11321 %}
11322 ins_pipe( pipe_slow );
11323 %}
11324
11325 instruct string_compareLU(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
11326 rax_RegI result, legRegD tmp1, rFlagsReg cr)
11327 %{
11328 predicate(!VM_Version::supports_avx512vlbw() && ((StrCompNode*)n)->encoding() == StrIntrinsicNode::LU);
11329 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11330 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11331
11332 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
11333 ins_encode %{
11334 __ string_compare($str1$$Register, $str2$$Register,
11335 $cnt1$$Register, $cnt2$$Register, $result$$Register,
11336 $tmp1$$XMMRegister, StrIntrinsicNode::LU, knoreg);
11337 %}
11338 ins_pipe( pipe_slow );
11339 %}
11340
11341 instruct string_compareLU_evex(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
11342 rax_RegI result, legRegD tmp1, kReg ktmp, rFlagsReg cr)
11343 %{
11344 predicate(VM_Version::supports_avx512vlbw() && ((StrCompNode*)n)->encoding() == StrIntrinsicNode::LU);
11345 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11346 effect(TEMP tmp1, TEMP ktmp, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11347
11348 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
11349 ins_encode %{
11350 __ string_compare($str1$$Register, $str2$$Register,
11351 $cnt1$$Register, $cnt2$$Register, $result$$Register,
11352 $tmp1$$XMMRegister, StrIntrinsicNode::LU, $ktmp$$KRegister);
11353 %}
11354 ins_pipe( pipe_slow );
11355 %}
11356
11357 instruct string_compareUL(rsi_RegP str1, rdx_RegI cnt1, rdi_RegP str2, rcx_RegI cnt2,
11358 rax_RegI result, legRegD tmp1, rFlagsReg cr)
11359 %{
11360 predicate(!VM_Version::supports_avx512vlbw() && ((StrCompNode*)n)->encoding() == StrIntrinsicNode::UL);
11361 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11362 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11363
11364 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
11365 ins_encode %{
11366 __ string_compare($str2$$Register, $str1$$Register,
11367 $cnt2$$Register, $cnt1$$Register, $result$$Register,
11368 $tmp1$$XMMRegister, StrIntrinsicNode::UL, knoreg);
11369 %}
11370 ins_pipe( pipe_slow );
11371 %}
11372
11373 instruct string_compareUL_evex(rsi_RegP str1, rdx_RegI cnt1, rdi_RegP str2, rcx_RegI cnt2,
11374 rax_RegI result, legRegD tmp1, kReg ktmp, rFlagsReg cr)
11375 %{
11376 predicate(VM_Version::supports_avx512vlbw() && ((StrCompNode*)n)->encoding() == StrIntrinsicNode::UL);
11377 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11378 effect(TEMP tmp1, TEMP ktmp, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11379
11380 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
11381 ins_encode %{
11382 __ string_compare($str2$$Register, $str1$$Register,
11383 $cnt2$$Register, $cnt1$$Register, $result$$Register,
11384 $tmp1$$XMMRegister, StrIntrinsicNode::UL, $ktmp$$KRegister);
11385 %}
11386 ins_pipe( pipe_slow );
11387 %}
11388
11389 // fast search of substring with known size.
11390 instruct string_indexof_conL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2,
11391 rbx_RegI result, legRegD tmp_vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr)
11392 %{
11393 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL));
11394 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
11395 effect(TEMP tmp_vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
11396
11397 format %{ "String IndexOf byte[] $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $tmp_vec, $cnt1, $cnt2, $tmp" %}
11398 ins_encode %{
11399 int icnt2 = (int)$int_cnt2$$constant;
11400 if (icnt2 >= 16) {
11401 // IndexOf for constant substrings with size >= 16 elements
11402 // which don't need to be loaded through stack.
11403 __ string_indexofC8($str1$$Register, $str2$$Register,
11404 $cnt1$$Register, $cnt2$$Register,
11405 icnt2, $result$$Register,
11406 $tmp_vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::LL);
11407 } else {
11408 // Small strings are loaded through stack if they cross page boundary.
11409 __ string_indexof($str1$$Register, $str2$$Register,
11410 $cnt1$$Register, $cnt2$$Register,
11411 icnt2, $result$$Register,
11412 $tmp_vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::LL);
11413 }
11414 %}
11415 ins_pipe( pipe_slow );
11416 %}
11417
11418 // fast search of substring with known size.
11419 instruct string_indexof_conU(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2,
11420 rbx_RegI result, legRegD tmp_vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr)
11421 %{
11422 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU));
11423 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
11424 effect(TEMP tmp_vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
11425
11426 format %{ "String IndexOf char[] $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $tmp_vec, $cnt1, $cnt2, $tmp" %}
11427 ins_encode %{
11428 int icnt2 = (int)$int_cnt2$$constant;
11429 if (icnt2 >= 8) {
11430 // IndexOf for constant substrings with size >= 8 elements
11431 // which don't need to be loaded through stack.
11432 __ string_indexofC8($str1$$Register, $str2$$Register,
11433 $cnt1$$Register, $cnt2$$Register,
11434 icnt2, $result$$Register,
11435 $tmp_vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UU);
11436 } else {
11437 // Small strings are loaded through stack if they cross page boundary.
11438 __ string_indexof($str1$$Register, $str2$$Register,
11439 $cnt1$$Register, $cnt2$$Register,
11440 icnt2, $result$$Register,
11441 $tmp_vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UU);
11442 }
11443 %}
11444 ins_pipe( pipe_slow );
11445 %}
11446
11447 // fast search of substring with known size.
11448 instruct string_indexof_conUL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2,
11449 rbx_RegI result, legRegD tmp_vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr)
11450 %{
11451 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL));
11452 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
11453 effect(TEMP tmp_vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
11454
11455 format %{ "String IndexOf char[] $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $tmp_vec, $cnt1, $cnt2, $tmp" %}
11456 ins_encode %{
11457 int icnt2 = (int)$int_cnt2$$constant;
11458 if (icnt2 >= 8) {
11459 // IndexOf for constant substrings with size >= 8 elements
11460 // which don't need to be loaded through stack.
11461 __ string_indexofC8($str1$$Register, $str2$$Register,
11462 $cnt1$$Register, $cnt2$$Register,
11463 icnt2, $result$$Register,
11464 $tmp_vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UL);
11465 } else {
11466 // Small strings are loaded through stack if they cross page boundary.
11467 __ string_indexof($str1$$Register, $str2$$Register,
11468 $cnt1$$Register, $cnt2$$Register,
11469 icnt2, $result$$Register,
11470 $tmp_vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UL);
11471 }
11472 %}
11473 ins_pipe( pipe_slow );
11474 %}
11475
11476 instruct string_indexofL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2,
11477 rbx_RegI result, legRegD tmp_vec, rcx_RegI tmp, rFlagsReg cr)
11478 %{
11479 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL));
11480 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
11481 effect(TEMP tmp_vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
11482
11483 format %{ "String IndexOf byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
11484 ins_encode %{
11485 __ string_indexof($str1$$Register, $str2$$Register,
11486 $cnt1$$Register, $cnt2$$Register,
11487 (-1), $result$$Register,
11488 $tmp_vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::LL);
11489 %}
11490 ins_pipe( pipe_slow );
11491 %}
11492
11493 instruct string_indexofU(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2,
11494 rbx_RegI result, legRegD tmp_vec, rcx_RegI tmp, rFlagsReg cr)
11495 %{
11496 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU));
11497 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
11498 effect(TEMP tmp_vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
11499
11500 format %{ "String IndexOf char[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
11501 ins_encode %{
11502 __ string_indexof($str1$$Register, $str2$$Register,
11503 $cnt1$$Register, $cnt2$$Register,
11504 (-1), $result$$Register,
11505 $tmp_vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UU);
11506 %}
11507 ins_pipe( pipe_slow );
11508 %}
11509
11510 instruct string_indexofUL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2,
11511 rbx_RegI result, legRegD tmp_vec, rcx_RegI tmp, rFlagsReg cr)
11512 %{
11513 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL));
11514 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
11515 effect(TEMP tmp_vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
11516
11517 format %{ "String IndexOf char[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
11518 ins_encode %{
11519 __ string_indexof($str1$$Register, $str2$$Register,
11520 $cnt1$$Register, $cnt2$$Register,
11521 (-1), $result$$Register,
11522 $tmp_vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UL);
11523 %}
11524 ins_pipe( pipe_slow );
11525 %}
11526
11527 instruct string_indexof_char(rdi_RegP str1, rdx_RegI cnt1, rax_RegI ch,
11528 rbx_RegI result, legRegD tmp_vec1, legRegD tmp_vec2, legRegD tmp_vec3, rcx_RegI tmp, rFlagsReg cr)
11529 %{
11530 predicate(UseSSE42Intrinsics && (((StrIndexOfCharNode*)n)->encoding() == StrIntrinsicNode::U));
11531 match(Set result (StrIndexOfChar (Binary str1 cnt1) ch));
11532 effect(TEMP tmp_vec1, TEMP tmp_vec2, TEMP tmp_vec3, USE_KILL str1, USE_KILL cnt1, USE_KILL ch, TEMP tmp, KILL cr);
11533 format %{ "StringUTF16 IndexOf char[] $str1,$cnt1,$ch -> $result // KILL all" %}
11534 ins_encode %{
11535 __ string_indexof_char($str1$$Register, $cnt1$$Register, $ch$$Register, $result$$Register,
11536 $tmp_vec1$$XMMRegister, $tmp_vec2$$XMMRegister, $tmp_vec3$$XMMRegister, $tmp$$Register);
11537 %}
11538 ins_pipe( pipe_slow );
11539 %}
11540
11541 instruct stringL_indexof_char(rdi_RegP str1, rdx_RegI cnt1, rax_RegI ch,
11542 rbx_RegI result, legRegD tmp_vec1, legRegD tmp_vec2, legRegD tmp_vec3, rcx_RegI tmp, rFlagsReg cr)
11543 %{
11544 predicate(UseSSE42Intrinsics && (((StrIndexOfCharNode*)n)->encoding() == StrIntrinsicNode::L));
11545 match(Set result (StrIndexOfChar (Binary str1 cnt1) ch));
11546 effect(TEMP tmp_vec1, TEMP tmp_vec2, TEMP tmp_vec3, USE_KILL str1, USE_KILL cnt1, USE_KILL ch, TEMP tmp, KILL cr);
11547 format %{ "StringLatin1 IndexOf char[] $str1,$cnt1,$ch -> $result // KILL all" %}
11548 ins_encode %{
11549 __ stringL_indexof_char($str1$$Register, $cnt1$$Register, $ch$$Register, $result$$Register,
11550 $tmp_vec1$$XMMRegister, $tmp_vec2$$XMMRegister, $tmp_vec3$$XMMRegister, $tmp$$Register);
11551 %}
11552 ins_pipe( pipe_slow );
11553 %}
11554
11555 // fast string equals
11556 instruct string_equals(rdi_RegP str1, rsi_RegP str2, rcx_RegI cnt, rax_RegI result,
11557 legRegD tmp1, legRegD tmp2, rbx_RegI tmp3, rFlagsReg cr)
11558 %{
11559 predicate(!VM_Version::supports_avx512vlbw());
11560 match(Set result (StrEquals (Binary str1 str2) cnt));
11561 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr);
11562
11563 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp1, $tmp2, $tmp3" %}
11564 ins_encode %{
11565 __ arrays_equals(false, $str1$$Register, $str2$$Register,
11566 $cnt$$Register, $result$$Register, $tmp3$$Register,
11567 $tmp1$$XMMRegister, $tmp2$$XMMRegister, false /* char */, knoreg);
11568 %}
11569 ins_pipe( pipe_slow );
11570 %}
11571
11572 instruct string_equals_evex(rdi_RegP str1, rsi_RegP str2, rcx_RegI cnt, rax_RegI result,
11573 legRegD tmp1, legRegD tmp2, kReg ktmp, rbx_RegI tmp3, rFlagsReg cr)
11574 %{
11575 predicate(VM_Version::supports_avx512vlbw());
11576 match(Set result (StrEquals (Binary str1 str2) cnt));
11577 effect(TEMP tmp1, TEMP tmp2, TEMP ktmp, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr);
11578
11579 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp1, $tmp2, $tmp3" %}
11580 ins_encode %{
11581 __ arrays_equals(false, $str1$$Register, $str2$$Register,
11582 $cnt$$Register, $result$$Register, $tmp3$$Register,
11583 $tmp1$$XMMRegister, $tmp2$$XMMRegister, false /* char */, $ktmp$$KRegister);
11584 %}
11585 ins_pipe( pipe_slow );
11586 %}
11587
11588 // fast array equals
11589 instruct array_equalsB(rdi_RegP ary1, rsi_RegP ary2, rax_RegI result,
11590 legRegD tmp1, legRegD tmp2, rcx_RegI tmp3, rbx_RegI tmp4, rFlagsReg cr)
11591 %{
11592 predicate(!VM_Version::supports_avx512vlbw() && ((AryEqNode*)n)->encoding() == StrIntrinsicNode::LL);
11593 match(Set result (AryEq ary1 ary2));
11594 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
11595
11596 format %{ "Array Equals byte[] $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
11597 ins_encode %{
11598 __ arrays_equals(true, $ary1$$Register, $ary2$$Register,
11599 $tmp3$$Register, $result$$Register, $tmp4$$Register,
11600 $tmp1$$XMMRegister, $tmp2$$XMMRegister, false /* char */, knoreg);
11601 %}
11602 ins_pipe( pipe_slow );
11603 %}
11604
11605 instruct array_equalsB_evex(rdi_RegP ary1, rsi_RegP ary2, rax_RegI result,
11606 legRegD tmp1, legRegD tmp2, kReg ktmp, rcx_RegI tmp3, rbx_RegI tmp4, rFlagsReg cr)
11607 %{
11608 predicate(VM_Version::supports_avx512vlbw() && ((AryEqNode*)n)->encoding() == StrIntrinsicNode::LL);
11609 match(Set result (AryEq ary1 ary2));
11610 effect(TEMP tmp1, TEMP tmp2, TEMP ktmp, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
11611
11612 format %{ "Array Equals byte[] $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
11613 ins_encode %{
11614 __ arrays_equals(true, $ary1$$Register, $ary2$$Register,
11615 $tmp3$$Register, $result$$Register, $tmp4$$Register,
11616 $tmp1$$XMMRegister, $tmp2$$XMMRegister, false /* char */, $ktmp$$KRegister);
11617 %}
11618 ins_pipe( pipe_slow );
11619 %}
11620
11621 instruct array_equalsC(rdi_RegP ary1, rsi_RegP ary2, rax_RegI result,
11622 legRegD tmp1, legRegD tmp2, rcx_RegI tmp3, rbx_RegI tmp4, rFlagsReg cr)
11623 %{
11624 predicate(!VM_Version::supports_avx512vlbw() && ((AryEqNode*)n)->encoding() == StrIntrinsicNode::UU);
11625 match(Set result (AryEq ary1 ary2));
11626 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
11627
11628 format %{ "Array Equals char[] $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
11629 ins_encode %{
11630 __ arrays_equals(true, $ary1$$Register, $ary2$$Register,
11631 $tmp3$$Register, $result$$Register, $tmp4$$Register,
11632 $tmp1$$XMMRegister, $tmp2$$XMMRegister, true /* char */, knoreg);
11633 %}
11634 ins_pipe( pipe_slow );
11635 %}
11636
11637 instruct array_equalsC_evex(rdi_RegP ary1, rsi_RegP ary2, rax_RegI result,
11638 legRegD tmp1, legRegD tmp2, kReg ktmp, rcx_RegI tmp3, rbx_RegI tmp4, rFlagsReg cr)
11639 %{
11640 predicate(VM_Version::supports_avx512vlbw() && ((AryEqNode*)n)->encoding() == StrIntrinsicNode::UU);
11641 match(Set result (AryEq ary1 ary2));
11642 effect(TEMP tmp1, TEMP tmp2, TEMP ktmp, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
11643
11644 format %{ "Array Equals char[] $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
11645 ins_encode %{
11646 __ arrays_equals(true, $ary1$$Register, $ary2$$Register,
11647 $tmp3$$Register, $result$$Register, $tmp4$$Register,
11648 $tmp1$$XMMRegister, $tmp2$$XMMRegister, true /* char */, $ktmp$$KRegister);
11649 %}
11650 ins_pipe( pipe_slow );
11651 %}
11652
11653 instruct has_negatives(rsi_RegP ary1, rcx_RegI len, rax_RegI result,
11654 legRegD tmp1, legRegD tmp2, rbx_RegI tmp3, rFlagsReg cr,)
11655 %{
11656 predicate(!VM_Version::supports_avx512vlbw() || !VM_Version::supports_bmi2());
11657 match(Set result (HasNegatives ary1 len));
11658 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL len, KILL tmp3, KILL cr);
11659
11660 format %{ "has negatives byte[] $ary1,$len -> $result // KILL $tmp1, $tmp2, $tmp3" %}
11661 ins_encode %{
11662 __ has_negatives($ary1$$Register, $len$$Register,
11663 $result$$Register, $tmp3$$Register,
11664 $tmp1$$XMMRegister, $tmp2$$XMMRegister, knoreg, knoreg);
11665 %}
11666 ins_pipe( pipe_slow );
11667 %}
11668
11669 instruct has_negatives_evex(rsi_RegP ary1, rcx_RegI len, rax_RegI result,
11670 legRegD tmp1, legRegD tmp2, kReg ktmp1, kReg ktmp2, rbx_RegI tmp3, rFlagsReg cr,)
11671 %{
11672 predicate(VM_Version::supports_avx512vlbw() && VM_Version::supports_bmi2());
11673 match(Set result (HasNegatives ary1 len));
11674 effect(TEMP tmp1, TEMP tmp2, TEMP ktmp1, TEMP ktmp2, USE_KILL ary1, USE_KILL len, KILL tmp3, KILL cr);
11675
11676 format %{ "has negatives byte[] $ary1,$len -> $result // KILL $tmp1, $tmp2, $tmp3" %}
11677 ins_encode %{
11678 __ has_negatives($ary1$$Register, $len$$Register,
11679 $result$$Register, $tmp3$$Register,
11680 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $ktmp1$$KRegister, $ktmp2$$KRegister);
11681 %}
11682 ins_pipe( pipe_slow );
11683 %}
11684
11685 // fast char[] to byte[] compression
11686 instruct string_compress(rsi_RegP src, rdi_RegP dst, rdx_RegI len, legRegD tmp1, legRegD tmp2, legRegD tmp3,
11687 legRegD tmp4, rcx_RegI tmp5, rax_RegI result, rFlagsReg cr) %{
11688 predicate(!VM_Version::supports_avx512vlbw() || !VM_Version::supports_bmi2());
11689 match(Set result (StrCompressedCopy src (Binary dst len)));
11690 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst,
11691 USE_KILL len, KILL tmp5, KILL cr);
11692
11693 format %{ "String Compress $src,$dst -> $result // KILL RAX, RCX, RDX" %}
11694 ins_encode %{
11695 __ char_array_compress($src$$Register, $dst$$Register, $len$$Register,
11696 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
11697 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register,
11698 knoreg, knoreg);
11699 %}
11700 ins_pipe( pipe_slow );
11701 %}
11702
11703 instruct string_compress_evex(rsi_RegP src, rdi_RegP dst, rdx_RegI len, legRegD tmp1, legRegD tmp2, legRegD tmp3,
11704 legRegD tmp4, kReg ktmp1, kReg ktmp2, rcx_RegI tmp5, rax_RegI result, rFlagsReg cr) %{
11705 predicate(VM_Version::supports_avx512vlbw() && VM_Version::supports_bmi2());
11706 match(Set result (StrCompressedCopy src (Binary dst len)));
11707 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP ktmp1, TEMP ktmp2, USE_KILL src, USE_KILL dst,
11708 USE_KILL len, KILL tmp5, KILL cr);
11709
11710 format %{ "String Compress $src,$dst -> $result // KILL RAX, RCX, RDX" %}
11711 ins_encode %{
11712 __ char_array_compress($src$$Register, $dst$$Register, $len$$Register,
11713 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
11714 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register,
11715 $ktmp1$$KRegister, $ktmp2$$KRegister);
11716 %}
11717 ins_pipe( pipe_slow );
11718 %}
11719 // fast byte[] to char[] inflation
11720 instruct string_inflate(Universe dummy, rsi_RegP src, rdi_RegP dst, rdx_RegI len,
11721 legRegD tmp1, rcx_RegI tmp2, rFlagsReg cr) %{
11722 predicate(!VM_Version::supports_avx512vlbw() || !VM_Version::supports_bmi2());
11723 match(Set dummy (StrInflatedCopy src (Binary dst len)));
11724 effect(TEMP tmp1, TEMP tmp2, USE_KILL src, USE_KILL dst, USE_KILL len, KILL cr);
11725
11726 format %{ "String Inflate $src,$dst // KILL $tmp1, $tmp2" %}
11727 ins_encode %{
11728 __ byte_array_inflate($src$$Register, $dst$$Register, $len$$Register,
11729 $tmp1$$XMMRegister, $tmp2$$Register, knoreg);
11730 %}
11731 ins_pipe( pipe_slow );
11732 %}
11733
11734 instruct string_inflate_evex(Universe dummy, rsi_RegP src, rdi_RegP dst, rdx_RegI len,
11735 legRegD tmp1, kReg ktmp, rcx_RegI tmp2, rFlagsReg cr) %{
11736 predicate(VM_Version::supports_avx512vlbw() && VM_Version::supports_bmi2());
11737 match(Set dummy (StrInflatedCopy src (Binary dst len)));
11738 effect(TEMP tmp1, TEMP tmp2, TEMP ktmp, USE_KILL src, USE_KILL dst, USE_KILL len, KILL cr);
11739
11740 format %{ "String Inflate $src,$dst // KILL $tmp1, $tmp2" %}
11741 ins_encode %{
11742 __ byte_array_inflate($src$$Register, $dst$$Register, $len$$Register,
11743 $tmp1$$XMMRegister, $tmp2$$Register, $ktmp$$KRegister);
11744 %}
11745 ins_pipe( pipe_slow );
11746 %}
11747
11748 // encode char[] to byte[] in ISO_8859_1
11749 instruct encode_iso_array(rsi_RegP src, rdi_RegP dst, rdx_RegI len,
11750 legRegD tmp1, legRegD tmp2, legRegD tmp3, legRegD tmp4,
11751 rcx_RegI tmp5, rax_RegI result, rFlagsReg cr) %{
11752 predicate(!((EncodeISOArrayNode*)n)->is_ascii());
11753 match(Set result (EncodeISOArray src (Binary dst len)));
11754 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL tmp5, KILL cr);
11755
11756 format %{ "Encode iso array $src,$dst,$len -> $result // KILL RCX, RDX, $tmp1, $tmp2, $tmp3, $tmp4, RSI, RDI " %}
11757 ins_encode %{
11758 __ encode_iso_array($src$$Register, $dst$$Register, $len$$Register,
11759 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
11760 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register, false);
11761 %}
11762 ins_pipe( pipe_slow );
11763 %}
11764
11765 // encode char[] to byte[] in ASCII
11766 instruct encode_ascii_array(rsi_RegP src, rdi_RegP dst, rdx_RegI len,
11767 legRegD tmp1, legRegD tmp2, legRegD tmp3, legRegD tmp4,
11768 rcx_RegI tmp5, rax_RegI result, rFlagsReg cr) %{
11769 predicate(((EncodeISOArrayNode*)n)->is_ascii());
11770 match(Set result (EncodeISOArray src (Binary dst len)));
11771 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL tmp5, KILL cr);
11772
11773 format %{ "Encode ascii array $src,$dst,$len -> $result // KILL RCX, RDX, $tmp1, $tmp2, $tmp3, $tmp4, RSI, RDI " %}
11774 ins_encode %{
11775 __ encode_iso_array($src$$Register, $dst$$Register, $len$$Register,
11776 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
11777 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register, true);
11778 %}
11779 ins_pipe( pipe_slow );
11780 %}
11781
11782 //----------Overflow Math Instructions-----------------------------------------
11783
11784 instruct overflowAddI_rReg(rFlagsReg cr, rax_RegI op1, rRegI op2)
11785 %{
11786 match(Set cr (OverflowAddI op1 op2));
11787 effect(DEF cr, USE_KILL op1, USE op2);
11788
11789 format %{ "addl $op1, $op2\t# overflow check int" %}
11790
11791 ins_encode %{
11792 __ addl($op1$$Register, $op2$$Register);
11793 %}
11794 ins_pipe(ialu_reg_reg);
11795 %}
11796
11797 instruct overflowAddI_rReg_imm(rFlagsReg cr, rax_RegI op1, immI op2)
11798 %{
11799 match(Set cr (OverflowAddI op1 op2));
11800 effect(DEF cr, USE_KILL op1, USE op2);
11801
11802 format %{ "addl $op1, $op2\t# overflow check int" %}
11803
11804 ins_encode %{
11805 __ addl($op1$$Register, $op2$$constant);
11806 %}
11807 ins_pipe(ialu_reg_reg);
11808 %}
11809
11810 instruct overflowAddL_rReg(rFlagsReg cr, rax_RegL op1, rRegL op2)
11811 %{
11812 match(Set cr (OverflowAddL op1 op2));
11813 effect(DEF cr, USE_KILL op1, USE op2);
11814
11815 format %{ "addq $op1, $op2\t# overflow check long" %}
11816 ins_encode %{
11817 __ addq($op1$$Register, $op2$$Register);
11818 %}
11819 ins_pipe(ialu_reg_reg);
11820 %}
11821
11822 instruct overflowAddL_rReg_imm(rFlagsReg cr, rax_RegL op1, immL32 op2)
11823 %{
11824 match(Set cr (OverflowAddL op1 op2));
11825 effect(DEF cr, USE_KILL op1, USE op2);
11826
11827 format %{ "addq $op1, $op2\t# overflow check long" %}
11828 ins_encode %{
11829 __ addq($op1$$Register, $op2$$constant);
11830 %}
11831 ins_pipe(ialu_reg_reg);
11832 %}
11833
11834 instruct overflowSubI_rReg(rFlagsReg cr, rRegI op1, rRegI op2)
11835 %{
11836 match(Set cr (OverflowSubI op1 op2));
11837
11838 format %{ "cmpl $op1, $op2\t# overflow check int" %}
11839 ins_encode %{
11840 __ cmpl($op1$$Register, $op2$$Register);
11841 %}
11842 ins_pipe(ialu_reg_reg);
11843 %}
11844
11845 instruct overflowSubI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2)
11846 %{
11847 match(Set cr (OverflowSubI op1 op2));
11848
11849 format %{ "cmpl $op1, $op2\t# overflow check int" %}
11850 ins_encode %{
11851 __ cmpl($op1$$Register, $op2$$constant);
11852 %}
11853 ins_pipe(ialu_reg_reg);
11854 %}
11855
11856 instruct overflowSubL_rReg(rFlagsReg cr, rRegL op1, rRegL op2)
11857 %{
11858 match(Set cr (OverflowSubL op1 op2));
11859
11860 format %{ "cmpq $op1, $op2\t# overflow check long" %}
11861 ins_encode %{
11862 __ cmpq($op1$$Register, $op2$$Register);
11863 %}
11864 ins_pipe(ialu_reg_reg);
11865 %}
11866
11867 instruct overflowSubL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2)
11868 %{
11869 match(Set cr (OverflowSubL op1 op2));
11870
11871 format %{ "cmpq $op1, $op2\t# overflow check long" %}
11872 ins_encode %{
11873 __ cmpq($op1$$Register, $op2$$constant);
11874 %}
11875 ins_pipe(ialu_reg_reg);
11876 %}
11877
11878 instruct overflowNegI_rReg(rFlagsReg cr, immI_0 zero, rax_RegI op2)
11879 %{
11880 match(Set cr (OverflowSubI zero op2));
11881 effect(DEF cr, USE_KILL op2);
11882
11883 format %{ "negl $op2\t# overflow check int" %}
11884 ins_encode %{
11885 __ negl($op2$$Register);
11886 %}
11887 ins_pipe(ialu_reg_reg);
11888 %}
11889
11890 instruct overflowNegL_rReg(rFlagsReg cr, immL0 zero, rax_RegL op2)
11891 %{
11892 match(Set cr (OverflowSubL zero op2));
11893 effect(DEF cr, USE_KILL op2);
11894
11895 format %{ "negq $op2\t# overflow check long" %}
11896 ins_encode %{
11897 __ negq($op2$$Register);
11898 %}
11899 ins_pipe(ialu_reg_reg);
11900 %}
11901
11902 instruct overflowMulI_rReg(rFlagsReg cr, rax_RegI op1, rRegI op2)
11903 %{
11904 match(Set cr (OverflowMulI op1 op2));
11905 effect(DEF cr, USE_KILL op1, USE op2);
11906
11907 format %{ "imull $op1, $op2\t# overflow check int" %}
11908 ins_encode %{
11909 __ imull($op1$$Register, $op2$$Register);
11910 %}
11911 ins_pipe(ialu_reg_reg_alu0);
11912 %}
11913
11914 instruct overflowMulI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2, rRegI tmp)
11915 %{
11916 match(Set cr (OverflowMulI op1 op2));
11917 effect(DEF cr, TEMP tmp, USE op1, USE op2);
11918
11919 format %{ "imull $tmp, $op1, $op2\t# overflow check int" %}
11920 ins_encode %{
11921 __ imull($tmp$$Register, $op1$$Register, $op2$$constant);
11922 %}
11923 ins_pipe(ialu_reg_reg_alu0);
11924 %}
11925
11926 instruct overflowMulL_rReg(rFlagsReg cr, rax_RegL op1, rRegL op2)
11927 %{
11928 match(Set cr (OverflowMulL op1 op2));
11929 effect(DEF cr, USE_KILL op1, USE op2);
11930
11931 format %{ "imulq $op1, $op2\t# overflow check long" %}
11932 ins_encode %{
11933 __ imulq($op1$$Register, $op2$$Register);
11934 %}
11935 ins_pipe(ialu_reg_reg_alu0);
11936 %}
11937
11938 instruct overflowMulL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2, rRegL tmp)
11939 %{
11940 match(Set cr (OverflowMulL op1 op2));
11941 effect(DEF cr, TEMP tmp, USE op1, USE op2);
11942
11943 format %{ "imulq $tmp, $op1, $op2\t# overflow check long" %}
11944 ins_encode %{
11945 __ imulq($tmp$$Register, $op1$$Register, $op2$$constant);
11946 %}
11947 ins_pipe(ialu_reg_reg_alu0);
11948 %}
11949
11950
11951 //----------Control Flow Instructions------------------------------------------
11952 // Signed compare Instructions
11953
11954 // XXX more variants!!
11955 instruct compI_rReg(rFlagsReg cr, rRegI op1, rRegI op2)
11956 %{
11957 match(Set cr (CmpI op1 op2));
11958 effect(DEF cr, USE op1, USE op2);
11959
11960 format %{ "cmpl $op1, $op2" %}
11961 ins_encode %{
11962 __ cmpl($op1$$Register, $op2$$Register);
11963 %}
11964 ins_pipe(ialu_cr_reg_reg);
11965 %}
11966
11967 instruct compI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2)
11968 %{
11969 match(Set cr (CmpI op1 op2));
11970
11971 format %{ "cmpl $op1, $op2" %}
11972 ins_encode %{
11973 __ cmpl($op1$$Register, $op2$$constant);
11974 %}
11975 ins_pipe(ialu_cr_reg_imm);
11976 %}
11977
11978 instruct compI_rReg_mem(rFlagsReg cr, rRegI op1, memory op2)
11979 %{
11980 match(Set cr (CmpI op1 (LoadI op2)));
11981
11982 ins_cost(500); // XXX
11983 format %{ "cmpl $op1, $op2" %}
11984 ins_encode %{
11985 __ cmpl($op1$$Register, $op2$$Address);
11986 %}
11987 ins_pipe(ialu_cr_reg_mem);
11988 %}
11989
11990 instruct testI_reg(rFlagsReg cr, rRegI src, immI_0 zero)
11991 %{
11992 match(Set cr (CmpI src zero));
11993
11994 format %{ "testl $src, $src" %}
11995 ins_encode %{
11996 __ testl($src$$Register, $src$$Register);
11997 %}
11998 ins_pipe(ialu_cr_reg_imm);
11999 %}
12000
12001 instruct testI_reg_imm(rFlagsReg cr, rRegI src, immI con, immI_0 zero)
12002 %{
12003 match(Set cr (CmpI (AndI src con) zero));
12004
12005 format %{ "testl $src, $con" %}
12006 ins_encode %{
12007 __ testl($src$$Register, $con$$constant);
12008 %}
12009 ins_pipe(ialu_cr_reg_imm);
12010 %}
12011
12012 instruct testI_reg_mem(rFlagsReg cr, rRegI src, memory mem, immI_0 zero)
12013 %{
12014 match(Set cr (CmpI (AndI src (LoadI mem)) zero));
12015
12016 format %{ "testl $src, $mem" %}
12017 ins_encode %{
12018 __ testl($src$$Register, $mem$$Address);
12019 %}
12020 ins_pipe(ialu_cr_reg_mem);
12021 %}
12022
12023 // Unsigned compare Instructions; really, same as signed except they
12024 // produce an rFlagsRegU instead of rFlagsReg.
12025 instruct compU_rReg(rFlagsRegU cr, rRegI op1, rRegI op2)
12026 %{
12027 match(Set cr (CmpU op1 op2));
12028
12029 format %{ "cmpl $op1, $op2\t# unsigned" %}
12030 ins_encode %{
12031 __ cmpl($op1$$Register, $op2$$Register);
12032 %}
12033 ins_pipe(ialu_cr_reg_reg);
12034 %}
12035
12036 instruct compU_rReg_imm(rFlagsRegU cr, rRegI op1, immI op2)
12037 %{
12038 match(Set cr (CmpU op1 op2));
12039
12040 format %{ "cmpl $op1, $op2\t# unsigned" %}
12041 ins_encode %{
12042 __ cmpl($op1$$Register, $op2$$constant);
12043 %}
12044 ins_pipe(ialu_cr_reg_imm);
12045 %}
12046
12047 instruct compU_rReg_mem(rFlagsRegU cr, rRegI op1, memory op2)
12048 %{
12049 match(Set cr (CmpU op1 (LoadI op2)));
12050
12051 ins_cost(500); // XXX
12052 format %{ "cmpl $op1, $op2\t# unsigned" %}
12053 ins_encode %{
12054 __ cmpl($op1$$Register, $op2$$Address);
12055 %}
12056 ins_pipe(ialu_cr_reg_mem);
12057 %}
12058
12059 // // // Cisc-spilled version of cmpU_rReg
12060 // //instruct compU_mem_rReg(rFlagsRegU cr, memory op1, rRegI op2)
12061 // //%{
12062 // // match(Set cr (CmpU (LoadI op1) op2));
12063 // //
12064 // // format %{ "CMPu $op1,$op2" %}
12065 // // ins_cost(500);
12066 // // opcode(0x39); /* Opcode 39 /r */
12067 // // ins_encode( OpcP, reg_mem( op1, op2) );
12068 // //%}
12069
12070 instruct testU_reg(rFlagsRegU cr, rRegI src, immI_0 zero)
12071 %{
12072 match(Set cr (CmpU src zero));
12073
12074 format %{ "testl $src, $src\t# unsigned" %}
12075 ins_encode %{
12076 __ testl($src$$Register, $src$$Register);
12077 %}
12078 ins_pipe(ialu_cr_reg_imm);
12079 %}
12080
12081 instruct compP_rReg(rFlagsRegU cr, rRegP op1, rRegP op2)
12082 %{
12083 match(Set cr (CmpP op1 op2));
12084
12085 format %{ "cmpq $op1, $op2\t# ptr" %}
12086 ins_encode %{
12087 __ cmpq($op1$$Register, $op2$$Register);
12088 %}
12089 ins_pipe(ialu_cr_reg_reg);
12090 %}
12091
12092 instruct compP_rReg_mem(rFlagsRegU cr, rRegP op1, memory op2)
12093 %{
12094 match(Set cr (CmpP op1 (LoadP op2)));
12095 predicate(n->in(2)->as_Load()->barrier_data() == 0);
12096
12097 ins_cost(500); // XXX
12098 format %{ "cmpq $op1, $op2\t# ptr" %}
12099 ins_encode %{
12100 __ cmpq($op1$$Register, $op2$$Address);
12101 %}
12102 ins_pipe(ialu_cr_reg_mem);
12103 %}
12104
12105 // // // Cisc-spilled version of cmpP_rReg
12106 // //instruct compP_mem_rReg(rFlagsRegU cr, memory op1, rRegP op2)
12107 // //%{
12108 // // match(Set cr (CmpP (LoadP op1) op2));
12109 // //
12110 // // format %{ "CMPu $op1,$op2" %}
12111 // // ins_cost(500);
12112 // // opcode(0x39); /* Opcode 39 /r */
12113 // // ins_encode( OpcP, reg_mem( op1, op2) );
12114 // //%}
12115
12116 // XXX this is generalized by compP_rReg_mem???
12117 // Compare raw pointer (used in out-of-heap check).
12118 // Only works because non-oop pointers must be raw pointers
12119 // and raw pointers have no anti-dependencies.
12120 instruct compP_mem_rReg(rFlagsRegU cr, rRegP op1, memory op2)
12121 %{
12122 predicate(n->in(2)->in(2)->bottom_type()->reloc() == relocInfo::none &&
12123 n->in(2)->as_Load()->barrier_data() == 0);
12124 match(Set cr (CmpP op1 (LoadP op2)));
12125
12126 format %{ "cmpq $op1, $op2\t# raw ptr" %}
12127 ins_encode %{
12128 __ cmpq($op1$$Register, $op2$$Address);
12129 %}
12130 ins_pipe(ialu_cr_reg_mem);
12131 %}
12132
12133 // This will generate a signed flags result. This should be OK since
12134 // any compare to a zero should be eq/neq.
12135 instruct testP_reg(rFlagsReg cr, rRegP src, immP0 zero)
12136 %{
12137 match(Set cr (CmpP src zero));
12138
12139 format %{ "testq $src, $src\t# ptr" %}
12140 ins_encode %{
12141 __ testq($src$$Register, $src$$Register);
12142 %}
12143 ins_pipe(ialu_cr_reg_imm);
12144 %}
12145
12146 // This will generate a signed flags result. This should be OK since
12147 // any compare to a zero should be eq/neq.
12148 instruct testP_mem(rFlagsReg cr, memory op, immP0 zero)
12149 %{
12150 predicate((!UseCompressedOops || (CompressedOops::base() != NULL)) &&
12151 n->in(1)->as_Load()->barrier_data() == 0);
12152 match(Set cr (CmpP (LoadP op) zero));
12153
12154 ins_cost(500); // XXX
12155 format %{ "testq $op, 0xffffffffffffffff\t# ptr" %}
12156 ins_encode %{
12157 __ testq($op$$Address, 0xFFFFFFFF);
12158 %}
12159 ins_pipe(ialu_cr_reg_imm);
12160 %}
12161
12162 instruct testP_mem_reg0(rFlagsReg cr, memory mem, immP0 zero)
12163 %{
12164 predicate(UseCompressedOops && (CompressedOops::base() == NULL) &&
12165 n->in(1)->as_Load()->barrier_data() == 0);
12166 match(Set cr (CmpP (LoadP mem) zero));
12167
12168 format %{ "cmpq R12, $mem\t# ptr (R12_heapbase==0)" %}
12169 ins_encode %{
12170 __ cmpq(r12, $mem$$Address);
12171 %}
12172 ins_pipe(ialu_cr_reg_mem);
12173 %}
12174
12175 instruct compN_rReg(rFlagsRegU cr, rRegN op1, rRegN op2)
12176 %{
12177 match(Set cr (CmpN op1 op2));
12178
12179 format %{ "cmpl $op1, $op2\t# compressed ptr" %}
12180 ins_encode %{ __ cmpl($op1$$Register, $op2$$Register); %}
12181 ins_pipe(ialu_cr_reg_reg);
12182 %}
12183
12184 instruct compN_rReg_mem(rFlagsRegU cr, rRegN src, memory mem)
12185 %{
12186 match(Set cr (CmpN src (LoadN mem)));
12187
12188 format %{ "cmpl $src, $mem\t# compressed ptr" %}
12189 ins_encode %{
12190 __ cmpl($src$$Register, $mem$$Address);
12191 %}
12192 ins_pipe(ialu_cr_reg_mem);
12193 %}
12194
12195 instruct compN_rReg_imm(rFlagsRegU cr, rRegN op1, immN op2) %{
12196 match(Set cr (CmpN op1 op2));
12197
12198 format %{ "cmpl $op1, $op2\t# compressed ptr" %}
12199 ins_encode %{
12200 __ cmp_narrow_oop($op1$$Register, (jobject)$op2$$constant);
12201 %}
12202 ins_pipe(ialu_cr_reg_imm);
12203 %}
12204
12205 instruct compN_mem_imm(rFlagsRegU cr, memory mem, immN src)
12206 %{
12207 match(Set cr (CmpN src (LoadN mem)));
12208
12209 format %{ "cmpl $mem, $src\t# compressed ptr" %}
12210 ins_encode %{
12211 __ cmp_narrow_oop($mem$$Address, (jobject)$src$$constant);
12212 %}
12213 ins_pipe(ialu_cr_reg_mem);
12214 %}
12215
12216 instruct compN_rReg_imm_klass(rFlagsRegU cr, rRegN op1, immNKlass op2) %{
12217 match(Set cr (CmpN op1 op2));
12218
12219 format %{ "cmpl $op1, $op2\t# compressed klass ptr" %}
12220 ins_encode %{
12221 __ cmp_narrow_klass($op1$$Register, (Klass*)$op2$$constant);
12222 %}
12223 ins_pipe(ialu_cr_reg_imm);
12224 %}
12225
12226 instruct compN_mem_imm_klass(rFlagsRegU cr, memory mem, immNKlass src)
12227 %{
12228 match(Set cr (CmpN src (LoadNKlass mem)));
12229
12230 format %{ "cmpl $mem, $src\t# compressed klass ptr" %}
12231 ins_encode %{
12232 __ cmp_narrow_klass($mem$$Address, (Klass*)$src$$constant);
12233 %}
12234 ins_pipe(ialu_cr_reg_mem);
12235 %}
12236
12237 instruct testN_reg(rFlagsReg cr, rRegN src, immN0 zero) %{
12238 match(Set cr (CmpN src zero));
12239
12240 format %{ "testl $src, $src\t# compressed ptr" %}
12241 ins_encode %{ __ testl($src$$Register, $src$$Register); %}
12242 ins_pipe(ialu_cr_reg_imm);
12243 %}
12244
12245 instruct testN_mem(rFlagsReg cr, memory mem, immN0 zero)
12246 %{
12247 predicate(CompressedOops::base() != NULL);
12248 match(Set cr (CmpN (LoadN mem) zero));
12249
12250 ins_cost(500); // XXX
12251 format %{ "testl $mem, 0xffffffff\t# compressed ptr" %}
12252 ins_encode %{
12253 __ cmpl($mem$$Address, (int)0xFFFFFFFF);
12254 %}
12255 ins_pipe(ialu_cr_reg_mem);
12256 %}
12257
12258 instruct testN_mem_reg0(rFlagsReg cr, memory mem, immN0 zero)
12259 %{
12260 predicate(CompressedOops::base() == NULL);
12261 match(Set cr (CmpN (LoadN mem) zero));
12262
12263 format %{ "cmpl R12, $mem\t# compressed ptr (R12_heapbase==0)" %}
12264 ins_encode %{
12265 __ cmpl(r12, $mem$$Address);
12266 %}
12267 ins_pipe(ialu_cr_reg_mem);
12268 %}
12269
12270 // Yanked all unsigned pointer compare operations.
12271 // Pointer compares are done with CmpP which is already unsigned.
12272
12273 instruct compL_rReg(rFlagsReg cr, rRegL op1, rRegL op2)
12274 %{
12275 match(Set cr (CmpL op1 op2));
12276
12277 format %{ "cmpq $op1, $op2" %}
12278 ins_encode %{
12279 __ cmpq($op1$$Register, $op2$$Register);
12280 %}
12281 ins_pipe(ialu_cr_reg_reg);
12282 %}
12283
12284 instruct compL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2)
12285 %{
12286 match(Set cr (CmpL op1 op2));
12287
12288 format %{ "cmpq $op1, $op2" %}
12289 ins_encode %{
12290 __ cmpq($op1$$Register, $op2$$constant);
12291 %}
12292 ins_pipe(ialu_cr_reg_imm);
12293 %}
12294
12295 instruct compL_rReg_mem(rFlagsReg cr, rRegL op1, memory op2)
12296 %{
12297 match(Set cr (CmpL op1 (LoadL op2)));
12298
12299 format %{ "cmpq $op1, $op2" %}
12300 ins_encode %{
12301 __ cmpq($op1$$Register, $op2$$Address);
12302 %}
12303 ins_pipe(ialu_cr_reg_mem);
12304 %}
12305
12306 instruct testL_reg(rFlagsReg cr, rRegL src, immL0 zero)
12307 %{
12308 match(Set cr (CmpL src zero));
12309
12310 format %{ "testq $src, $src" %}
12311 ins_encode %{
12312 __ testq($src$$Register, $src$$Register);
12313 %}
12314 ins_pipe(ialu_cr_reg_imm);
12315 %}
12316
12317 instruct testL_reg_imm(rFlagsReg cr, rRegL src, immL32 con, immL0 zero)
12318 %{
12319 match(Set cr (CmpL (AndL src con) zero));
12320
12321 format %{ "testq $src, $con\t# long" %}
12322 ins_encode %{
12323 __ testq($src$$Register, $con$$constant);
12324 %}
12325 ins_pipe(ialu_cr_reg_imm);
12326 %}
12327
12328 instruct testL_reg_mem(rFlagsReg cr, rRegL src, memory mem, immL0 zero)
12329 %{
12330 match(Set cr (CmpL (AndL src (LoadL mem)) zero));
12331
12332 format %{ "testq $src, $mem" %}
12333 ins_encode %{
12334 __ testq($src$$Register, $mem$$Address);
12335 %}
12336 ins_pipe(ialu_cr_reg_mem);
12337 %}
12338
12339 instruct testL_reg_mem2(rFlagsReg cr, rRegP src, memory mem, immL0 zero)
12340 %{
12341 match(Set cr (CmpL (AndL (CastP2X src) (LoadL mem)) zero));
12342
12343 format %{ "testq $src, $mem" %}
12344 ins_encode %{
12345 __ testq($src$$Register, $mem$$Address);
12346 %}
12347 ins_pipe(ialu_cr_reg_mem);
12348 %}
12349
12350 // Manifest a CmpL result in an integer register. Very painful.
12351 // This is the test to avoid.
12352 instruct cmpL3_reg_reg(rRegI dst, rRegL src1, rRegL src2, rFlagsReg flags)
12353 %{
12354 match(Set dst (CmpL3 src1 src2));
12355 effect(KILL flags);
12356
12357 ins_cost(275); // XXX
12358 format %{ "cmpq $src1, $src2\t# CmpL3\n\t"
12359 "movl $dst, -1\n\t"
12360 "jl,s done\n\t"
12361 "setne $dst\n\t"
12362 "movzbl $dst, $dst\n\t"
12363 "done:" %}
12364 ins_encode %{
12365 Label done;
12366 __ cmpq($src1$$Register, $src2$$Register);
12367 __ movl($dst$$Register, -1);
12368 __ jccb(Assembler::less, done);
12369 __ setne($dst$$Register);
12370 __ movzbl($dst$$Register, $dst$$Register);
12371 __ bind(done);
12372 %}
12373 ins_pipe(pipe_slow);
12374 %}
12375
12376 // Unsigned long compare Instructions; really, same as signed long except they
12377 // produce an rFlagsRegU instead of rFlagsReg.
12378 instruct compUL_rReg(rFlagsRegU cr, rRegL op1, rRegL op2)
12379 %{
12380 match(Set cr (CmpUL op1 op2));
12381
12382 format %{ "cmpq $op1, $op2\t# unsigned" %}
12383 ins_encode %{
12384 __ cmpq($op1$$Register, $op2$$Register);
12385 %}
12386 ins_pipe(ialu_cr_reg_reg);
12387 %}
12388
12389 instruct compUL_rReg_imm(rFlagsRegU cr, rRegL op1, immL32 op2)
12390 %{
12391 match(Set cr (CmpUL op1 op2));
12392
12393 format %{ "cmpq $op1, $op2\t# unsigned" %}
12394 ins_encode %{
12395 __ cmpq($op1$$Register, $op2$$constant);
12396 %}
12397 ins_pipe(ialu_cr_reg_imm);
12398 %}
12399
12400 instruct compUL_rReg_mem(rFlagsRegU cr, rRegL op1, memory op2)
12401 %{
12402 match(Set cr (CmpUL op1 (LoadL op2)));
12403
12404 format %{ "cmpq $op1, $op2\t# unsigned" %}
12405 ins_encode %{
12406 __ cmpq($op1$$Register, $op2$$Address);
12407 %}
12408 ins_pipe(ialu_cr_reg_mem);
12409 %}
12410
12411 instruct testUL_reg(rFlagsRegU cr, rRegL src, immL0 zero)
12412 %{
12413 match(Set cr (CmpUL src zero));
12414
12415 format %{ "testq $src, $src\t# unsigned" %}
12416 ins_encode %{
12417 __ testq($src$$Register, $src$$Register);
12418 %}
12419 ins_pipe(ialu_cr_reg_imm);
12420 %}
12421
12422 instruct compB_mem_imm(rFlagsReg cr, memory mem, immI8 imm)
12423 %{
12424 match(Set cr (CmpI (LoadB mem) imm));
12425
12426 ins_cost(125);
12427 format %{ "cmpb $mem, $imm" %}
12428 ins_encode %{ __ cmpb($mem$$Address, $imm$$constant); %}
12429 ins_pipe(ialu_cr_reg_mem);
12430 %}
12431
12432 instruct testUB_mem_imm(rFlagsReg cr, memory mem, immU7 imm, immI_0 zero)
12433 %{
12434 match(Set cr (CmpI (AndI (LoadUB mem) imm) zero));
12435
12436 ins_cost(125);
12437 format %{ "testb $mem, $imm\t# ubyte" %}
12438 ins_encode %{ __ testb($mem$$Address, $imm$$constant); %}
12439 ins_pipe(ialu_cr_reg_mem);
12440 %}
12441
12442 instruct testB_mem_imm(rFlagsReg cr, memory mem, immI8 imm, immI_0 zero)
12443 %{
12444 match(Set cr (CmpI (AndI (LoadB mem) imm) zero));
12445
12446 ins_cost(125);
12447 format %{ "testb $mem, $imm\t# byte" %}
12448 ins_encode %{ __ testb($mem$$Address, $imm$$constant); %}
12449 ins_pipe(ialu_cr_reg_mem);
12450 %}
12451
12452 //----------Max and Min--------------------------------------------------------
12453 // Min Instructions
12454
12455 instruct cmovI_reg_g(rRegI dst, rRegI src, rFlagsReg cr)
12456 %{
12457 effect(USE_DEF dst, USE src, USE cr);
12458
12459 format %{ "cmovlgt $dst, $src\t# min" %}
12460 ins_encode %{
12461 __ cmovl(Assembler::greater, $dst$$Register, $src$$Register);
12462 %}
12463 ins_pipe(pipe_cmov_reg);
12464 %}
12465
12466
12467 instruct minI_rReg(rRegI dst, rRegI src)
12468 %{
12469 match(Set dst (MinI dst src));
12470
12471 ins_cost(200);
12472 expand %{
12473 rFlagsReg cr;
12474 compI_rReg(cr, dst, src);
12475 cmovI_reg_g(dst, src, cr);
12476 %}
12477 %}
12478
12479 instruct cmovI_reg_l(rRegI dst, rRegI src, rFlagsReg cr)
12480 %{
12481 effect(USE_DEF dst, USE src, USE cr);
12482
12483 format %{ "cmovllt $dst, $src\t# max" %}
12484 ins_encode %{
12485 __ cmovl(Assembler::less, $dst$$Register, $src$$Register);
12486 %}
12487 ins_pipe(pipe_cmov_reg);
12488 %}
12489
12490
12491 instruct maxI_rReg(rRegI dst, rRegI src)
12492 %{
12493 match(Set dst (MaxI dst src));
12494
12495 ins_cost(200);
12496 expand %{
12497 rFlagsReg cr;
12498 compI_rReg(cr, dst, src);
12499 cmovI_reg_l(dst, src, cr);
12500 %}
12501 %}
12502
12503 // ============================================================================
12504 // Branch Instructions
12505
12506 // Jump Direct - Label defines a relative address from JMP+1
12507 instruct jmpDir(label labl)
12508 %{
12509 match(Goto);
12510 effect(USE labl);
12511
12512 ins_cost(300);
12513 format %{ "jmp $labl" %}
12514 size(5);
12515 ins_encode %{
12516 Label* L = $labl$$label;
12517 __ jmp(*L, false); // Always long jump
12518 %}
12519 ins_pipe(pipe_jmp);
12520 %}
12521
12522 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12523 instruct jmpCon(cmpOp cop, rFlagsReg cr, label labl)
12524 %{
12525 match(If cop cr);
12526 effect(USE labl);
12527
12528 ins_cost(300);
12529 format %{ "j$cop $labl" %}
12530 size(6);
12531 ins_encode %{
12532 Label* L = $labl$$label;
12533 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12534 %}
12535 ins_pipe(pipe_jcc);
12536 %}
12537
12538 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12539 instruct jmpLoopEnd(cmpOp cop, rFlagsReg cr, label labl)
12540 %{
12541 predicate(!n->has_vector_mask_set());
12542 match(CountedLoopEnd cop cr);
12543 effect(USE labl);
12544
12545 ins_cost(300);
12546 format %{ "j$cop $labl\t# loop end" %}
12547 size(6);
12548 ins_encode %{
12549 Label* L = $labl$$label;
12550 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12551 %}
12552 ins_pipe(pipe_jcc);
12553 %}
12554
12555 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12556 instruct jmpLoopEndU(cmpOpU cop, rFlagsRegU cmp, label labl) %{
12557 predicate(!n->has_vector_mask_set());
12558 match(CountedLoopEnd cop cmp);
12559 effect(USE labl);
12560
12561 ins_cost(300);
12562 format %{ "j$cop,u $labl\t# loop end" %}
12563 size(6);
12564 ins_encode %{
12565 Label* L = $labl$$label;
12566 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12567 %}
12568 ins_pipe(pipe_jcc);
12569 %}
12570
12571 instruct jmpLoopEndUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
12572 predicate(!n->has_vector_mask_set());
12573 match(CountedLoopEnd cop cmp);
12574 effect(USE labl);
12575
12576 ins_cost(200);
12577 format %{ "j$cop,u $labl\t# loop end" %}
12578 size(6);
12579 ins_encode %{
12580 Label* L = $labl$$label;
12581 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12582 %}
12583 ins_pipe(pipe_jcc);
12584 %}
12585
12586 // mask version
12587 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12588 // Bounded mask operand used in following patten is needed for
12589 // post-loop multiversioning.
12590 instruct jmpLoopEnd_and_restoreMask(cmpOp cop, kReg_K1 ktmp, rFlagsReg cr, label labl)
12591 %{
12592 predicate(PostLoopMultiversioning && n->has_vector_mask_set());
12593 match(CountedLoopEnd cop cr);
12594 effect(USE labl, TEMP ktmp);
12595
12596 ins_cost(400);
12597 format %{ "j$cop $labl\t# loop end\n\t"
12598 "restorevectmask \t# vector mask restore for loops" %}
12599 size(10);
12600 ins_encode %{
12601 Label* L = $labl$$label;
12602 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12603 __ restorevectmask($ktmp$$KRegister);
12604 %}
12605 ins_pipe(pipe_jcc);
12606 %}
12607
12608 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12609 // Bounded mask operand used in following patten is needed for
12610 // post-loop multiversioning.
12611 instruct jmpLoopEndU_and_restoreMask(cmpOpU cop, kReg_K1 ktmp, rFlagsRegU cmp, label labl) %{
12612 predicate(PostLoopMultiversioning && n->has_vector_mask_set());
12613 match(CountedLoopEnd cop cmp);
12614 effect(USE labl, TEMP ktmp);
12615
12616 ins_cost(400);
12617 format %{ "j$cop,u $labl\t# loop end\n\t"
12618 "restorevectmask \t# vector mask restore for loops" %}
12619 size(10);
12620 ins_encode %{
12621 Label* L = $labl$$label;
12622 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12623 __ restorevectmask($ktmp$$KRegister);
12624 %}
12625 ins_pipe(pipe_jcc);
12626 %}
12627
12628 // Bounded mask operand used in following patten is needed for
12629 // post-loop multiversioning.
12630 instruct jmpLoopEndUCF_and_restoreMask(cmpOpUCF cop, kReg_K1 ktmp, rFlagsRegUCF cmp, label labl) %{
12631 predicate(PostLoopMultiversioning && n->has_vector_mask_set());
12632 match(CountedLoopEnd cop cmp);
12633 effect(USE labl, TEMP ktmp);
12634
12635 ins_cost(300);
12636 format %{ "j$cop,u $labl\t# loop end\n\t"
12637 "restorevectmask \t# vector mask restore for loops" %}
12638 size(10);
12639 ins_encode %{
12640 Label* L = $labl$$label;
12641 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12642 __ restorevectmask($ktmp$$KRegister);
12643 %}
12644 ins_pipe(pipe_jcc);
12645 %}
12646
12647 // Jump Direct Conditional - using unsigned comparison
12648 instruct jmpConU(cmpOpU cop, rFlagsRegU cmp, label labl) %{
12649 match(If cop cmp);
12650 effect(USE labl);
12651
12652 ins_cost(300);
12653 format %{ "j$cop,u $labl" %}
12654 size(6);
12655 ins_encode %{
12656 Label* L = $labl$$label;
12657 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12658 %}
12659 ins_pipe(pipe_jcc);
12660 %}
12661
12662 instruct jmpConUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
12663 match(If cop cmp);
12664 effect(USE labl);
12665
12666 ins_cost(200);
12667 format %{ "j$cop,u $labl" %}
12668 size(6);
12669 ins_encode %{
12670 Label* L = $labl$$label;
12671 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12672 %}
12673 ins_pipe(pipe_jcc);
12674 %}
12675
12676 instruct jmpConUCF2(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{
12677 match(If cop cmp);
12678 effect(USE labl);
12679
12680 ins_cost(200);
12681 format %{ $$template
12682 if ($cop$$cmpcode == Assembler::notEqual) {
12683 $$emit$$"jp,u $labl\n\t"
12684 $$emit$$"j$cop,u $labl"
12685 } else {
12686 $$emit$$"jp,u done\n\t"
12687 $$emit$$"j$cop,u $labl\n\t"
12688 $$emit$$"done:"
12689 }
12690 %}
12691 ins_encode %{
12692 Label* l = $labl$$label;
12693 if ($cop$$cmpcode == Assembler::notEqual) {
12694 __ jcc(Assembler::parity, *l, false);
12695 __ jcc(Assembler::notEqual, *l, false);
12696 } else if ($cop$$cmpcode == Assembler::equal) {
12697 Label done;
12698 __ jccb(Assembler::parity, done);
12699 __ jcc(Assembler::equal, *l, false);
12700 __ bind(done);
12701 } else {
12702 ShouldNotReachHere();
12703 }
12704 %}
12705 ins_pipe(pipe_jcc);
12706 %}
12707
12708 // ============================================================================
12709 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary
12710 // superklass array for an instance of the superklass. Set a hidden
12711 // internal cache on a hit (cache is checked with exposed code in
12712 // gen_subtype_check()). Return NZ for a miss or zero for a hit. The
12713 // encoding ALSO sets flags.
12714
12715 instruct partialSubtypeCheck(rdi_RegP result,
12716 rsi_RegP sub, rax_RegP super, rcx_RegI rcx,
12717 rFlagsReg cr)
12718 %{
12719 match(Set result (PartialSubtypeCheck sub super));
12720 effect(KILL rcx, KILL cr);
12721
12722 ins_cost(1100); // slightly larger than the next version
12723 format %{ "movq rdi, [$sub + in_bytes(Klass::secondary_supers_offset())]\n\t"
12724 "movl rcx, [rdi + Array<Klass*>::length_offset_in_bytes()]\t# length to scan\n\t"
12725 "addq rdi, Array<Klass*>::base_offset_in_bytes()\t# Skip to start of data; set NZ in case count is zero\n\t"
12726 "repne scasq\t# Scan *rdi++ for a match with rax while rcx--\n\t"
12727 "jne,s miss\t\t# Missed: rdi not-zero\n\t"
12728 "movq [$sub + in_bytes(Klass::secondary_super_cache_offset())], $super\t# Hit: update cache\n\t"
12729 "xorq $result, $result\t\t Hit: rdi zero\n\t"
12730 "miss:\t" %}
12731
12732 opcode(0x1); // Force a XOR of RDI
12733 ins_encode(enc_PartialSubtypeCheck());
12734 ins_pipe(pipe_slow);
12735 %}
12736
12737 instruct partialSubtypeCheck_vs_Zero(rFlagsReg cr,
12738 rsi_RegP sub, rax_RegP super, rcx_RegI rcx,
12739 immP0 zero,
12740 rdi_RegP result)
12741 %{
12742 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero));
12743 effect(KILL rcx, KILL result);
12744
12745 ins_cost(1000);
12746 format %{ "movq rdi, [$sub + in_bytes(Klass::secondary_supers_offset())]\n\t"
12747 "movl rcx, [rdi + Array<Klass*>::length_offset_in_bytes()]\t# length to scan\n\t"
12748 "addq rdi, Array<Klass*>::base_offset_in_bytes()\t# Skip to start of data; set NZ in case count is zero\n\t"
12749 "repne scasq\t# Scan *rdi++ for a match with rax while cx-- != 0\n\t"
12750 "jne,s miss\t\t# Missed: flags nz\n\t"
12751 "movq [$sub + in_bytes(Klass::secondary_super_cache_offset())], $super\t# Hit: update cache\n\t"
12752 "miss:\t" %}
12753
12754 opcode(0x0); // No need to XOR RDI
12755 ins_encode(enc_PartialSubtypeCheck());
12756 ins_pipe(pipe_slow);
12757 %}
12758
12759 // ============================================================================
12760 // Branch Instructions -- short offset versions
12761 //
12762 // These instructions are used to replace jumps of a long offset (the default
12763 // match) with jumps of a shorter offset. These instructions are all tagged
12764 // with the ins_short_branch attribute, which causes the ADLC to suppress the
12765 // match rules in general matching. Instead, the ADLC generates a conversion
12766 // method in the MachNode which can be used to do in-place replacement of the
12767 // long variant with the shorter variant. The compiler will determine if a
12768 // branch can be taken by the is_short_branch_offset() predicate in the machine
12769 // specific code section of the file.
12770
12771 // Jump Direct - Label defines a relative address from JMP+1
12772 instruct jmpDir_short(label labl) %{
12773 match(Goto);
12774 effect(USE labl);
12775
12776 ins_cost(300);
12777 format %{ "jmp,s $labl" %}
12778 size(2);
12779 ins_encode %{
12780 Label* L = $labl$$label;
12781 __ jmpb(*L);
12782 %}
12783 ins_pipe(pipe_jmp);
12784 ins_short_branch(1);
12785 %}
12786
12787 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12788 instruct jmpCon_short(cmpOp cop, rFlagsReg cr, label labl) %{
12789 match(If cop cr);
12790 effect(USE labl);
12791
12792 ins_cost(300);
12793 format %{ "j$cop,s $labl" %}
12794 size(2);
12795 ins_encode %{
12796 Label* L = $labl$$label;
12797 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12798 %}
12799 ins_pipe(pipe_jcc);
12800 ins_short_branch(1);
12801 %}
12802
12803 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12804 instruct jmpLoopEnd_short(cmpOp cop, rFlagsReg cr, label labl) %{
12805 match(CountedLoopEnd cop cr);
12806 effect(USE labl);
12807
12808 ins_cost(300);
12809 format %{ "j$cop,s $labl\t# loop end" %}
12810 size(2);
12811 ins_encode %{
12812 Label* L = $labl$$label;
12813 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12814 %}
12815 ins_pipe(pipe_jcc);
12816 ins_short_branch(1);
12817 %}
12818
12819 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12820 instruct jmpLoopEndU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{
12821 match(CountedLoopEnd cop cmp);
12822 effect(USE labl);
12823
12824 ins_cost(300);
12825 format %{ "j$cop,us $labl\t# loop end" %}
12826 size(2);
12827 ins_encode %{
12828 Label* L = $labl$$label;
12829 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12830 %}
12831 ins_pipe(pipe_jcc);
12832 ins_short_branch(1);
12833 %}
12834
12835 instruct jmpLoopEndUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
12836 match(CountedLoopEnd cop cmp);
12837 effect(USE labl);
12838
12839 ins_cost(300);
12840 format %{ "j$cop,us $labl\t# loop end" %}
12841 size(2);
12842 ins_encode %{
12843 Label* L = $labl$$label;
12844 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12845 %}
12846 ins_pipe(pipe_jcc);
12847 ins_short_branch(1);
12848 %}
12849
12850 // Jump Direct Conditional - using unsigned comparison
12851 instruct jmpConU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{
12852 match(If cop cmp);
12853 effect(USE labl);
12854
12855 ins_cost(300);
12856 format %{ "j$cop,us $labl" %}
12857 size(2);
12858 ins_encode %{
12859 Label* L = $labl$$label;
12860 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12861 %}
12862 ins_pipe(pipe_jcc);
12863 ins_short_branch(1);
12864 %}
12865
12866 instruct jmpConUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
12867 match(If cop cmp);
12868 effect(USE labl);
12869
12870 ins_cost(300);
12871 format %{ "j$cop,us $labl" %}
12872 size(2);
12873 ins_encode %{
12874 Label* L = $labl$$label;
12875 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12876 %}
12877 ins_pipe(pipe_jcc);
12878 ins_short_branch(1);
12879 %}
12880
12881 instruct jmpConUCF2_short(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{
12882 match(If cop cmp);
12883 effect(USE labl);
12884
12885 ins_cost(300);
12886 format %{ $$template
12887 if ($cop$$cmpcode == Assembler::notEqual) {
12888 $$emit$$"jp,u,s $labl\n\t"
12889 $$emit$$"j$cop,u,s $labl"
12890 } else {
12891 $$emit$$"jp,u,s done\n\t"
12892 $$emit$$"j$cop,u,s $labl\n\t"
12893 $$emit$$"done:"
12894 }
12895 %}
12896 size(4);
12897 ins_encode %{
12898 Label* l = $labl$$label;
12899 if ($cop$$cmpcode == Assembler::notEqual) {
12900 __ jccb(Assembler::parity, *l);
12901 __ jccb(Assembler::notEqual, *l);
12902 } else if ($cop$$cmpcode == Assembler::equal) {
12903 Label done;
12904 __ jccb(Assembler::parity, done);
12905 __ jccb(Assembler::equal, *l);
12906 __ bind(done);
12907 } else {
12908 ShouldNotReachHere();
12909 }
12910 %}
12911 ins_pipe(pipe_jcc);
12912 ins_short_branch(1);
12913 %}
12914
12915 // ============================================================================
12916 // inlined locking and unlocking
12917
12918 instruct cmpFastLockRTM(rFlagsReg cr, rRegP object, rbx_RegP box, rax_RegI tmp, rdx_RegI scr, rRegI cx1, rRegI cx2) %{
12919 predicate(Compile::current()->use_rtm());
12920 match(Set cr (FastLock object box));
12921 effect(TEMP tmp, TEMP scr, TEMP cx1, TEMP cx2, USE_KILL box);
12922 ins_cost(300);
12923 format %{ "fastlock $object,$box\t! kills $box,$tmp,$scr,$cx1,$cx2" %}
12924 ins_encode %{
12925 __ fast_lock($object$$Register, $box$$Register, $tmp$$Register,
12926 $scr$$Register, $cx1$$Register, $cx2$$Register,
12927 _counters, _rtm_counters, _stack_rtm_counters,
12928 ((Method*)(ra_->C->method()->constant_encoding()))->method_data(),
12929 true, ra_->C->profile_rtm());
12930 %}
12931 ins_pipe(pipe_slow);
12932 %}
12933
12934 instruct cmpFastLock(rFlagsReg cr, rRegP object, rbx_RegP box, rax_RegI tmp, rRegP scr, rRegP cx1) %{
12935 predicate(!Compile::current()->use_rtm());
12936 match(Set cr (FastLock object box));
12937 effect(TEMP tmp, TEMP scr, TEMP cx1, USE_KILL box);
12938 ins_cost(300);
12939 format %{ "fastlock $object,$box\t! kills $box,$tmp,$scr" %}
12940 ins_encode %{
12941 __ fast_lock($object$$Register, $box$$Register, $tmp$$Register,
12942 $scr$$Register, $cx1$$Register, noreg, _counters, NULL, NULL, NULL, false, false);
12943 %}
12944 ins_pipe(pipe_slow);
12945 %}
12946
12947 instruct cmpFastUnlock(rFlagsReg cr, rRegP object, rax_RegP box, rRegP tmp) %{
12948 match(Set cr (FastUnlock object box));
12949 effect(TEMP tmp, USE_KILL box);
12950 ins_cost(300);
12951 format %{ "fastunlock $object,$box\t! kills $box,$tmp" %}
12952 ins_encode %{
12953 __ fast_unlock($object$$Register, $box$$Register, $tmp$$Register, ra_->C->use_rtm());
12954 %}
12955 ins_pipe(pipe_slow);
12956 %}
12957
12958
12959 // ============================================================================
12960 // Safepoint Instructions
12961 instruct safePoint_poll_tls(rFlagsReg cr, rRegP poll)
12962 %{
12963 match(SafePoint poll);
12964 effect(KILL cr, USE poll);
12965
12966 format %{ "testl rax, [$poll]\t"
12967 "# Safepoint: poll for GC" %}
12968 ins_cost(125);
12969 size(4); /* setting an explicit size will cause debug builds to assert if size is incorrect */
12970 ins_encode %{
12971 __ relocate(relocInfo::poll_type);
12972 address pre_pc = __ pc();
12973 __ testl(rax, Address($poll$$Register, 0));
12974 assert(nativeInstruction_at(pre_pc)->is_safepoint_poll(), "must emit test %%eax [reg]");
12975 %}
12976 ins_pipe(ialu_reg_mem);
12977 %}
12978
12979 // ============================================================================
12980 // Procedure Call/Return Instructions
12981 // Call Java Static Instruction
12982 // Note: If this code changes, the corresponding ret_addr_offset() and
12983 // compute_padding() functions will have to be adjusted.
12984 instruct CallStaticJavaDirect(method meth) %{
12985 match(CallStaticJava);
12986 effect(USE meth);
12987
12988 ins_cost(300);
12989 format %{ "call,static " %}
12990 opcode(0xE8); /* E8 cd */
12991 ins_encode(clear_avx, Java_Static_Call(meth), call_epilog);
12992 ins_pipe(pipe_slow);
12993 ins_alignment(4);
12994 %}
12995
12996 // Call Java Dynamic Instruction
12997 // Note: If this code changes, the corresponding ret_addr_offset() and
12998 // compute_padding() functions will have to be adjusted.
12999 instruct CallDynamicJavaDirect(method meth)
13000 %{
13001 match(CallDynamicJava);
13002 effect(USE meth);
13003
13004 ins_cost(300);
13005 format %{ "movq rax, #Universe::non_oop_word()\n\t"
13006 "call,dynamic " %}
13007 ins_encode(clear_avx, Java_Dynamic_Call(meth), call_epilog);
13008 ins_pipe(pipe_slow);
13009 ins_alignment(4);
13010 %}
13011
13012 // Call Runtime Instruction
13013 instruct CallRuntimeDirect(method meth)
13014 %{
13015 match(CallRuntime);
13016 effect(USE meth);
13017
13018 ins_cost(300);
13019 format %{ "call,runtime " %}
13020 ins_encode(clear_avx, Java_To_Runtime(meth));
13021 ins_pipe(pipe_slow);
13022 %}
13023
13024 // Call runtime without safepoint
13025 instruct CallLeafDirect(method meth)
13026 %{
13027 match(CallLeaf);
13028 effect(USE meth);
13029
13030 ins_cost(300);
13031 format %{ "call_leaf,runtime " %}
13032 ins_encode(clear_avx, Java_To_Runtime(meth));
13033 ins_pipe(pipe_slow);
13034 %}
13035
13036 // Call runtime without safepoint and with vector arguments
13037 instruct CallLeafDirectVector(method meth)
13038 %{
13039 match(CallLeafVector);
13040 effect(USE meth);
13041
13042 ins_cost(300);
13043 format %{ "call_leaf,vector " %}
13044 ins_encode(Java_To_Runtime(meth));
13045 ins_pipe(pipe_slow);
13046 %}
13047
13048 //
13049 instruct CallNativeDirect(method meth)
13050 %{
13051 match(CallNative);
13052 effect(USE meth);
13053
13054 ins_cost(300);
13055 format %{ "call_native " %}
13056 ins_encode(clear_avx, Java_To_Runtime(meth));
13057 ins_pipe(pipe_slow);
13058 %}
13059
13060 // Call runtime without safepoint
13061 instruct CallLeafNoFPDirect(method meth)
13062 %{
13063 match(CallLeafNoFP);
13064 effect(USE meth);
13065
13066 ins_cost(300);
13067 format %{ "call_leaf_nofp,runtime " %}
13068 ins_encode(clear_avx, Java_To_Runtime(meth));
13069 ins_pipe(pipe_slow);
13070 %}
13071
13072 // Return Instruction
13073 // Remove the return address & jump to it.
13074 // Notice: We always emit a nop after a ret to make sure there is room
13075 // for safepoint patching
13076 instruct Ret()
13077 %{
13078 match(Return);
13079
13080 format %{ "ret" %}
13081 ins_encode %{
13082 __ ret(0);
13083 %}
13084 ins_pipe(pipe_jmp);
13085 %}
13086
13087 // Tail Call; Jump from runtime stub to Java code.
13088 // Also known as an 'interprocedural jump'.
13089 // Target of jump will eventually return to caller.
13090 // TailJump below removes the return address.
13091 instruct TailCalljmpInd(no_rbp_RegP jump_target, rbx_RegP method_ptr)
13092 %{
13093 match(TailCall jump_target method_ptr);
13094
13095 ins_cost(300);
13096 format %{ "jmp $jump_target\t# rbx holds method" %}
13097 ins_encode %{
13098 __ jmp($jump_target$$Register);
13099 %}
13100 ins_pipe(pipe_jmp);
13101 %}
13102
13103 // Tail Jump; remove the return address; jump to target.
13104 // TailCall above leaves the return address around.
13105 instruct tailjmpInd(no_rbp_RegP jump_target, rax_RegP ex_oop)
13106 %{
13107 match(TailJump jump_target ex_oop);
13108
13109 ins_cost(300);
13110 format %{ "popq rdx\t# pop return address\n\t"
13111 "jmp $jump_target" %}
13112 ins_encode %{
13113 __ popq(as_Register(RDX_enc));
13114 __ jmp($jump_target$$Register);
13115 %}
13116 ins_pipe(pipe_jmp);
13117 %}
13118
13119 // Create exception oop: created by stack-crawling runtime code.
13120 // Created exception is now available to this handler, and is setup
13121 // just prior to jumping to this handler. No code emitted.
13122 instruct CreateException(rax_RegP ex_oop)
13123 %{
13124 match(Set ex_oop (CreateEx));
13125
13126 size(0);
13127 // use the following format syntax
13128 format %{ "# exception oop is in rax; no code emitted" %}
13129 ins_encode();
13130 ins_pipe(empty);
13131 %}
13132
13133 // Rethrow exception:
13134 // The exception oop will come in the first argument position.
13135 // Then JUMP (not call) to the rethrow stub code.
13136 instruct RethrowException()
13137 %{
13138 match(Rethrow);
13139
13140 // use the following format syntax
13141 format %{ "jmp rethrow_stub" %}
13142 ins_encode(enc_rethrow);
13143 ins_pipe(pipe_jmp);
13144 %}
13145
13146 // ============================================================================
13147 // This name is KNOWN by the ADLC and cannot be changed.
13148 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
13149 // for this guy.
13150 instruct tlsLoadP(r15_RegP dst) %{
13151 match(Set dst (ThreadLocal));
13152 effect(DEF dst);
13153
13154 size(0);
13155 format %{ "# TLS is in R15" %}
13156 ins_encode( /*empty encoding*/ );
13157 ins_pipe(ialu_reg_reg);
13158 %}
13159
13160
13161 //----------PEEPHOLE RULES-----------------------------------------------------
13162 // These must follow all instruction definitions as they use the names
13163 // defined in the instructions definitions.
13164 //
13165 // peepmatch ( root_instr_name [preceding_instruction]* );
13166 //
13167 // peepconstraint %{
13168 // (instruction_number.operand_name relational_op instruction_number.operand_name
13169 // [, ...] );
13170 // // instruction numbers are zero-based using left to right order in peepmatch
13171 //
13172 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
13173 // // provide an instruction_number.operand_name for each operand that appears
13174 // // in the replacement instruction's match rule
13175 //
13176 // ---------VM FLAGS---------------------------------------------------------
13177 //
13178 // All peephole optimizations can be turned off using -XX:-OptoPeephole
13179 //
13180 // Each peephole rule is given an identifying number starting with zero and
13181 // increasing by one in the order seen by the parser. An individual peephole
13182 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
13183 // on the command-line.
13184 //
13185 // ---------CURRENT LIMITATIONS----------------------------------------------
13186 //
13187 // Only match adjacent instructions in same basic block
13188 // Only equality constraints
13189 // Only constraints between operands, not (0.dest_reg == RAX_enc)
13190 // Only one replacement instruction
13191 //
13192 // ---------EXAMPLE----------------------------------------------------------
13193 //
13194 // // pertinent parts of existing instructions in architecture description
13195 // instruct movI(rRegI dst, rRegI src)
13196 // %{
13197 // match(Set dst (CopyI src));
13198 // %}
13199 //
13200 // instruct incI_rReg(rRegI dst, immI_1 src, rFlagsReg cr)
13201 // %{
13202 // match(Set dst (AddI dst src));
13203 // effect(KILL cr);
13204 // %}
13205 //
13206 // // Change (inc mov) to lea
13207 // peephole %{
13208 // // increment preceeded by register-register move
13209 // peepmatch ( incI_rReg movI );
13210 // // require that the destination register of the increment
13211 // // match the destination register of the move
13212 // peepconstraint ( 0.dst == 1.dst );
13213 // // construct a replacement instruction that sets
13214 // // the destination to ( move's source register + one )
13215 // peepreplace ( leaI_rReg_immI( 0.dst 1.src 0.src ) );
13216 // %}
13217 //
13218
13219 // Implementation no longer uses movX instructions since
13220 // machine-independent system no longer uses CopyX nodes.
13221 //
13222 // peephole
13223 // %{
13224 // peepmatch (incI_rReg movI);
13225 // peepconstraint (0.dst == 1.dst);
13226 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
13227 // %}
13228
13229 // peephole
13230 // %{
13231 // peepmatch (decI_rReg movI);
13232 // peepconstraint (0.dst == 1.dst);
13233 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
13234 // %}
13235
13236 // peephole
13237 // %{
13238 // peepmatch (addI_rReg_imm movI);
13239 // peepconstraint (0.dst == 1.dst);
13240 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
13241 // %}
13242
13243 // peephole
13244 // %{
13245 // peepmatch (incL_rReg movL);
13246 // peepconstraint (0.dst == 1.dst);
13247 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
13248 // %}
13249
13250 // peephole
13251 // %{
13252 // peepmatch (decL_rReg movL);
13253 // peepconstraint (0.dst == 1.dst);
13254 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
13255 // %}
13256
13257 // peephole
13258 // %{
13259 // peepmatch (addL_rReg_imm movL);
13260 // peepconstraint (0.dst == 1.dst);
13261 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
13262 // %}
13263
13264 // peephole
13265 // %{
13266 // peepmatch (addP_rReg_imm movP);
13267 // peepconstraint (0.dst == 1.dst);
13268 // peepreplace (leaP_rReg_imm(0.dst 1.src 0.src));
13269 // %}
13270
13271 // // Change load of spilled value to only a spill
13272 // instruct storeI(memory mem, rRegI src)
13273 // %{
13274 // match(Set mem (StoreI mem src));
13275 // %}
13276 //
13277 // instruct loadI(rRegI dst, memory mem)
13278 // %{
13279 // match(Set dst (LoadI mem));
13280 // %}
13281 //
13282
13283 peephole
13284 %{
13285 peepmatch (loadI storeI);
13286 peepconstraint (1.src == 0.dst, 1.mem == 0.mem);
13287 peepreplace (storeI(1.mem 1.mem 1.src));
13288 %}
13289
13290 peephole
13291 %{
13292 peepmatch (loadL storeL);
13293 peepconstraint (1.src == 0.dst, 1.mem == 0.mem);
13294 peepreplace (storeL(1.mem 1.mem 1.src));
13295 %}
13296
13297 //----------SMARTSPILL RULES---------------------------------------------------
13298 // These must follow all instruction definitions as they use the names
13299 // defined in the instructions definitions.