1 /*
2 * Copyright (c) 2000, 2022, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "c1/c1_CodeStubs.hpp"
27 #include "c1/c1_InstructionPrinter.hpp"
28 #include "c1/c1_LIR.hpp"
29 #include "c1/c1_LIRAssembler.hpp"
30 #include "c1/c1_ValueStack.hpp"
31 #include "ci/ciInstance.hpp"
32 #include "runtime/safepointMechanism.inline.hpp"
33 #include "runtime/sharedRuntime.hpp"
34 #include "runtime/vm_version.hpp"
35
36 Register LIR_OprDesc::as_register() const {
37 return FrameMap::cpu_rnr2reg(cpu_regnr());
38 }
39
40 Register LIR_OprDesc::as_register_lo() const {
41 return FrameMap::cpu_rnr2reg(cpu_regnrLo());
42 }
43
44 Register LIR_OprDesc::as_register_hi() const {
45 return FrameMap::cpu_rnr2reg(cpu_regnrHi());
46 }
47
48 LIR_Opr LIR_OprFact::illegalOpr = LIR_OprFact::illegal();
49
50 LIR_Opr LIR_OprFact::value_type(ValueType* type) {
51 ValueTag tag = type->tag();
52 switch (tag) {
53 case metaDataTag : {
54 ClassConstant* c = type->as_ClassConstant();
55 if (c != NULL && !c->value()->is_loaded()) {
56 return LIR_OprFact::metadataConst(NULL);
57 } else if (c != NULL) {
58 return LIR_OprFact::metadataConst(c->value()->constant_encoding());
59 } else {
60 MethodConstant* m = type->as_MethodConstant();
61 assert (m != NULL, "not a class or a method?");
62 return LIR_OprFact::metadataConst(m->value()->constant_encoding());
63 }
64 }
65 case objectTag : {
66 return LIR_OprFact::oopConst(type->as_ObjectType()->encoding());
67 }
68 case addressTag: return LIR_OprFact::addressConst(type->as_AddressConstant()->value());
69 case intTag : return LIR_OprFact::intConst(type->as_IntConstant()->value());
70 case floatTag : return LIR_OprFact::floatConst(type->as_FloatConstant()->value());
71 case longTag : return LIR_OprFact::longConst(type->as_LongConstant()->value());
72 case doubleTag : return LIR_OprFact::doubleConst(type->as_DoubleConstant()->value());
73 default: ShouldNotReachHere(); return LIR_OprFact::intConst(-1);
74 }
75 }
76
77
78 //---------------------------------------------------
79
80
81 LIR_Address::Scale LIR_Address::scale(BasicType type) {
82 int elem_size = type2aelembytes(type);
83 switch (elem_size) {
84 case 1: return LIR_Address::times_1;
85 case 2: return LIR_Address::times_2;
86 case 4: return LIR_Address::times_4;
87 case 8: return LIR_Address::times_8;
88 }
89 ShouldNotReachHere();
90 return LIR_Address::times_1;
91 }
92
93 //---------------------------------------------------
94
95 char LIR_OprDesc::type_char(BasicType t) {
96 switch (t) {
97 case T_ARRAY:
98 t = T_OBJECT;
99 case T_BOOLEAN:
100 case T_CHAR:
101 case T_FLOAT:
102 case T_DOUBLE:
103 case T_BYTE:
104 case T_SHORT:
105 case T_INT:
106 case T_LONG:
107 case T_OBJECT:
108 case T_ADDRESS:
109 case T_VOID:
110 return ::type2char(t);
111 case T_METADATA:
112 return 'M';
113 case T_ILLEGAL:
114 return '?';
115
116 default:
117 ShouldNotReachHere();
118 return '?';
119 }
120 }
121
122 #ifndef PRODUCT
123 void LIR_OprDesc::validate_type() const {
124
125 #ifdef ASSERT
126 if (!is_pointer() && !is_illegal()) {
127 OprKind kindfield = kind_field(); // Factored out because of compiler bug, see 8002160
128 switch (as_BasicType(type_field())) {
129 case T_LONG:
130 assert((kindfield == cpu_register || kindfield == stack_value) &&
131 size_field() == double_size, "must match");
132 break;
133 case T_FLOAT:
134 // FP return values can be also in CPU registers on ARM and PPC32 (softfp ABI)
135 assert((kindfield == fpu_register || kindfield == stack_value
136 ARM_ONLY(|| kindfield == cpu_register)
137 PPC32_ONLY(|| kindfield == cpu_register) ) &&
138 size_field() == single_size, "must match");
139 break;
140 case T_DOUBLE:
141 // FP return values can be also in CPU registers on ARM and PPC32 (softfp ABI)
142 assert((kindfield == fpu_register || kindfield == stack_value
143 ARM_ONLY(|| kindfield == cpu_register)
144 PPC32_ONLY(|| kindfield == cpu_register) ) &&
145 size_field() == double_size, "must match");
146 break;
147 case T_BOOLEAN:
148 case T_CHAR:
149 case T_BYTE:
150 case T_SHORT:
151 case T_INT:
152 case T_ADDRESS:
153 case T_OBJECT:
154 case T_METADATA:
155 case T_ARRAY:
156 assert((kindfield == cpu_register || kindfield == stack_value) &&
157 size_field() == single_size, "must match");
158 break;
159
160 case T_ILLEGAL:
161 // XXX TKR also means unknown right now
162 // assert(is_illegal(), "must match");
163 break;
164
165 default:
166 ShouldNotReachHere();
167 }
168 }
169 #endif
170
171 }
172 #endif // PRODUCT
173
174
175 bool LIR_OprDesc::is_oop() const {
176 if (is_pointer()) {
177 return pointer()->is_oop_pointer();
178 } else {
179 OprType t= type_field();
180 assert(t != unknown_type, "not set");
181 return t == object_type;
182 }
183 }
184
185
186
187 void LIR_Op2::verify() const {
188 #ifdef ASSERT
189 switch (code()) {
190 case lir_cmove:
191 #ifdef RISCV
192 assert(false, "lir_cmove is LIR_Op4 on RISCV");
193 #endif
194 case lir_xchg:
195 break;
196
197 default:
198 assert(!result_opr()->is_register() || !result_opr()->is_oop_register(),
199 "can't produce oops from arith");
200 }
201
202 if (TwoOperandLIRForm) {
203
204 #ifdef ASSERT
205 bool threeOperandForm = false;
206 #ifdef S390
207 // There are 3 operand shifts on S390 (see LIR_Assembler::shift_op()).
208 threeOperandForm =
209 code() == lir_shl ||
210 ((code() == lir_shr || code() == lir_ushr) && (result_opr()->is_double_cpu() || in_opr1()->type() == T_OBJECT));
211 #endif
212 #endif
213
214 switch (code()) {
215 case lir_add:
216 case lir_sub:
217 case lir_mul:
218 case lir_div:
219 case lir_rem:
220 case lir_logic_and:
221 case lir_logic_or:
222 case lir_logic_xor:
223 case lir_shl:
224 case lir_shr:
225 assert(in_opr1() == result_opr() || threeOperandForm, "opr1 and result must match");
226 assert(in_opr1()->is_valid() && in_opr2()->is_valid(), "must be valid");
227 break;
228
229 // special handling for lir_ushr because of write barriers
230 case lir_ushr:
231 assert(in_opr1() == result_opr() || in_opr2()->is_constant() || threeOperandForm, "opr1 and result must match or shift count is constant");
232 assert(in_opr1()->is_valid() && in_opr2()->is_valid(), "must be valid");
233 break;
234
235 default:
236 break;
237 }
238 }
239 #endif
240 }
241
242
243 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BlockBegin* block)
244 #ifdef RISCV
245 : LIR_Op2(lir_branch, cond, LIR_OprFact::illegalOpr, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)
246 #else
247 : LIR_Op(lir_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)
248 , _cond(cond)
249 #endif
250 , _label(block->label())
251 , _block(block)
252 , _ublock(NULL)
253 , _stub(NULL) {
254 }
255
256 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, CodeStub* stub) :
257 #ifdef RISCV
258 LIR_Op2(lir_branch, cond, LIR_OprFact::illegalOpr, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)
259 #else
260 LIR_Op(lir_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)
261 , _cond(cond)
262 #endif
263 , _label(stub->entry())
264 , _block(NULL)
265 , _ublock(NULL)
266 , _stub(stub) {
267 }
268
269 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BlockBegin* block, BlockBegin* ublock)
270 #ifdef RISCV
271 : LIR_Op2(lir_cond_float_branch, cond, LIR_OprFact::illegalOpr, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)
272 #else
273 : LIR_Op(lir_cond_float_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)
274 , _cond(cond)
275 #endif
276 , _label(block->label())
277 , _block(block)
278 , _ublock(ublock)
279 , _stub(NULL)
280 {
281 }
282
283 void LIR_OpBranch::change_block(BlockBegin* b) {
284 assert(_block != NULL, "must have old block");
285 assert(_block->label() == label(), "must be equal");
286
287 _block = b;
288 _label = b->label();
289 }
290
291 void LIR_OpBranch::change_ublock(BlockBegin* b) {
292 assert(_ublock != NULL, "must have old block");
293 _ublock = b;
294 }
295
296 void LIR_OpBranch::negate_cond() {
297 switch (cond()) {
298 case lir_cond_equal: set_cond(lir_cond_notEqual); break;
299 case lir_cond_notEqual: set_cond(lir_cond_equal); break;
300 case lir_cond_less: set_cond(lir_cond_greaterEqual); break;
301 case lir_cond_lessEqual: set_cond(lir_cond_greater); break;
302 case lir_cond_greaterEqual: set_cond(lir_cond_less); break;
303 case lir_cond_greater: set_cond(lir_cond_lessEqual); break;
304 default: ShouldNotReachHere();
305 }
306 }
307
308
309 LIR_OpTypeCheck::LIR_OpTypeCheck(LIR_Code code, LIR_Opr result, LIR_Opr object, ciKlass* klass,
310 LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3,
311 bool fast_check, CodeEmitInfo* info_for_exception, CodeEmitInfo* info_for_patch,
312 CodeStub* stub)
313
314 : LIR_Op(code, result, NULL)
315 , _object(object)
316 , _array(LIR_OprFact::illegalOpr)
317 , _klass(klass)
318 , _tmp1(tmp1)
319 , _tmp2(tmp2)
320 , _tmp3(tmp3)
321 , _fast_check(fast_check)
322 , _info_for_patch(info_for_patch)
323 , _info_for_exception(info_for_exception)
324 , _stub(stub)
325 , _profiled_method(NULL)
326 , _profiled_bci(-1)
327 , _should_profile(false)
328 {
329 if (code == lir_checkcast) {
330 assert(info_for_exception != NULL, "checkcast throws exceptions");
331 } else if (code == lir_instanceof) {
332 assert(info_for_exception == NULL, "instanceof throws no exceptions");
333 } else {
334 ShouldNotReachHere();
335 }
336 }
337
338
339
340 LIR_OpTypeCheck::LIR_OpTypeCheck(LIR_Code code, LIR_Opr object, LIR_Opr array, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, CodeEmitInfo* info_for_exception)
341 : LIR_Op(code, LIR_OprFact::illegalOpr, NULL)
342 , _object(object)
343 , _array(array)
344 , _klass(NULL)
345 , _tmp1(tmp1)
346 , _tmp2(tmp2)
347 , _tmp3(tmp3)
348 , _fast_check(false)
349 , _info_for_patch(NULL)
350 , _info_for_exception(info_for_exception)
351 , _stub(NULL)
352 , _profiled_method(NULL)
353 , _profiled_bci(-1)
354 , _should_profile(false)
355 {
356 if (code == lir_store_check) {
357 _stub = new ArrayStoreExceptionStub(object, info_for_exception);
358 assert(info_for_exception != NULL, "store_check throws exceptions");
359 } else {
360 ShouldNotReachHere();
361 }
362 }
363
364
365 LIR_OpArrayCopy::LIR_OpArrayCopy(LIR_Opr src, LIR_Opr src_pos, LIR_Opr dst, LIR_Opr dst_pos, LIR_Opr length,
366 LIR_Opr tmp, ciArrayKlass* expected_type, int flags, CodeEmitInfo* info)
367 : LIR_Op(lir_arraycopy, LIR_OprFact::illegalOpr, info)
368 , _src(src)
369 , _src_pos(src_pos)
370 , _dst(dst)
371 , _dst_pos(dst_pos)
372 , _length(length)
373 , _tmp(tmp)
374 , _expected_type(expected_type)
375 , _flags(flags) {
376 _stub = new ArrayCopyStub(this);
377 }
378
379 LIR_OpUpdateCRC32::LIR_OpUpdateCRC32(LIR_Opr crc, LIR_Opr val, LIR_Opr res)
380 : LIR_Op(lir_updatecrc32, res, NULL)
381 , _crc(crc)
382 , _val(val) {
383 }
384
385 //-------------------verify--------------------------
386
387 void LIR_Op1::verify() const {
388 switch(code()) {
389 case lir_move:
390 assert(in_opr()->is_valid() && result_opr()->is_valid(), "must be");
391 break;
392 case lir_null_check:
393 assert(in_opr()->is_register(), "must be");
394 break;
395 case lir_return:
396 assert(in_opr()->is_register() || in_opr()->is_illegal(), "must be");
397 break;
398 default:
399 break;
400 }
401 }
402
403 void LIR_OpRTCall::verify() const {
404 assert(strcmp(Runtime1::name_for_address(addr()), "<unknown function>") != 0, "unknown function");
405 }
406
407 //-------------------visits--------------------------
408
409 // complete rework of LIR instruction visitor.
410 // The virtual call for each instruction type is replaced by a big
411 // switch that adds the operands for each instruction
412
413 void LIR_OpVisitState::visit(LIR_Op* op) {
414 // copy information from the LIR_Op
415 reset();
416 set_op(op);
417
418 switch (op->code()) {
419
420 // LIR_Op0
421 case lir_backwardbranch_target: // result and info always invalid
422 case lir_fpop_raw: // result and info always invalid
423 case lir_breakpoint: // result and info always invalid
424 case lir_membar: // result and info always invalid
425 case lir_membar_acquire: // result and info always invalid
426 case lir_membar_release: // result and info always invalid
427 case lir_membar_loadload: // result and info always invalid
428 case lir_membar_storestore: // result and info always invalid
429 case lir_membar_loadstore: // result and info always invalid
430 case lir_membar_storeload: // result and info always invalid
431 case lir_on_spin_wait:
432 {
433 assert(op->as_Op0() != NULL, "must be");
434 assert(op->_info == NULL, "info not used by this instruction");
435 assert(op->_result->is_illegal(), "not used");
436 break;
437 }
438
439 case lir_nop: // may have info, result always invalid
440 case lir_std_entry: // may have result, info always invalid
441 case lir_osr_entry: // may have result, info always invalid
442 case lir_get_thread: // may have result, info always invalid
443 {
444 assert(op->as_Op0() != NULL, "must be");
445 if (op->_info != NULL) do_info(op->_info);
446 if (op->_result->is_valid()) do_output(op->_result);
447 break;
448 }
449
450
451 // LIR_OpLabel
452 case lir_label: // result and info always invalid
453 {
454 assert(op->as_OpLabel() != NULL, "must be");
455 assert(op->_info == NULL, "info not used by this instruction");
456 assert(op->_result->is_illegal(), "not used");
457 break;
458 }
459
460
461 // LIR_Op1
462 case lir_fxch: // input always valid, result and info always invalid
463 case lir_fld: // input always valid, result and info always invalid
464 case lir_push: // input always valid, result and info always invalid
465 case lir_pop: // input always valid, result and info always invalid
466 case lir_leal: // input and result always valid, info always invalid
467 case lir_monaddr: // input and result always valid, info always invalid
468 case lir_null_check: // input and info always valid, result always invalid
469 case lir_move: // input and result always valid, may have info
470 {
471 assert(op->as_Op1() != NULL, "must be");
472 LIR_Op1* op1 = (LIR_Op1*)op;
473
474 if (op1->_info) do_info(op1->_info);
475 if (op1->_opr->is_valid()) do_input(op1->_opr);
476 if (op1->_result->is_valid()) do_output(op1->_result);
477
478 break;
479 }
480
481 case lir_return:
482 {
483 assert(op->as_OpReturn() != NULL, "must be");
484 LIR_OpReturn* op_ret = (LIR_OpReturn*)op;
485
486 if (op_ret->_info) do_info(op_ret->_info);
487 if (op_ret->_opr->is_valid()) do_input(op_ret->_opr);
488 if (op_ret->_result->is_valid()) do_output(op_ret->_result);
489 if (op_ret->stub() != NULL) do_stub(op_ret->stub());
490
491 break;
492 }
493
494 case lir_safepoint:
495 {
496 assert(op->as_Op1() != NULL, "must be");
497 LIR_Op1* op1 = (LIR_Op1*)op;
498
499 assert(op1->_info != NULL, ""); do_info(op1->_info);
500 if (op1->_opr->is_valid()) do_temp(op1->_opr); // safepoints on SPARC need temporary register
501 assert(op1->_result->is_illegal(), "safepoint does not produce value");
502
503 break;
504 }
505
506 // LIR_OpConvert;
507 case lir_convert: // input and result always valid, info always invalid
508 {
509 assert(op->as_OpConvert() != NULL, "must be");
510 LIR_OpConvert* opConvert = (LIR_OpConvert*)op;
511
512 assert(opConvert->_info == NULL, "must be");
513 if (opConvert->_opr->is_valid()) do_input(opConvert->_opr);
514 if (opConvert->_result->is_valid()) do_output(opConvert->_result);
515 #ifdef PPC32
516 if (opConvert->_tmp1->is_valid()) do_temp(opConvert->_tmp1);
517 if (opConvert->_tmp2->is_valid()) do_temp(opConvert->_tmp2);
518 #endif
519 do_stub(opConvert->_stub);
520
521 break;
522 }
523
524 // LIR_OpBranch;
525 case lir_branch: // may have info, input and result register always invalid
526 case lir_cond_float_branch: // may have info, input and result register always invalid
527 {
528 assert(op->as_OpBranch() != NULL, "must be");
529 LIR_OpBranch* opBranch = (LIR_OpBranch*)op;
530
531 #ifdef RISCV
532 assert(opBranch->_tmp1->is_illegal() && opBranch->_tmp2->is_illegal() &&
533 opBranch->_tmp3->is_illegal() && opBranch->_tmp4->is_illegal() &&
534 opBranch->_tmp5->is_illegal(), "not used");
535
536 if (opBranch->_opr1->is_valid()) do_input(opBranch->_opr1);
537 if (opBranch->_opr2->is_valid()) do_input(opBranch->_opr2);
538 #endif
539
540 if (opBranch->_info != NULL) do_info(opBranch->_info);
541 assert(opBranch->_result->is_illegal(), "not used");
542 if (opBranch->_stub != NULL) opBranch->stub()->visit(this);
543
544 break;
545 }
546
547
548 // LIR_OpAllocObj
549 case lir_alloc_object:
550 {
551 assert(op->as_OpAllocObj() != NULL, "must be");
552 LIR_OpAllocObj* opAllocObj = (LIR_OpAllocObj*)op;
553
554 if (opAllocObj->_info) do_info(opAllocObj->_info);
555 if (opAllocObj->_opr->is_valid()) { do_input(opAllocObj->_opr);
556 do_temp(opAllocObj->_opr);
557 }
558 if (opAllocObj->_tmp1->is_valid()) do_temp(opAllocObj->_tmp1);
559 if (opAllocObj->_tmp2->is_valid()) do_temp(opAllocObj->_tmp2);
560 if (opAllocObj->_tmp3->is_valid()) do_temp(opAllocObj->_tmp3);
561 if (opAllocObj->_tmp4->is_valid()) do_temp(opAllocObj->_tmp4);
562 if (opAllocObj->_result->is_valid()) do_output(opAllocObj->_result);
563 do_stub(opAllocObj->_stub);
564 break;
565 }
566
567
568 // LIR_OpRoundFP;
569 case lir_roundfp: {
570 assert(op->as_OpRoundFP() != NULL, "must be");
571 LIR_OpRoundFP* opRoundFP = (LIR_OpRoundFP*)op;
572
573 assert(op->_info == NULL, "info not used by this instruction");
574 assert(opRoundFP->_tmp->is_illegal(), "not used");
575 do_input(opRoundFP->_opr);
576 do_output(opRoundFP->_result);
577
578 break;
579 }
580
581
582 // LIR_Op2
583 case lir_cmp:
584 case lir_cmp_l2i:
585 case lir_ucmp_fd2i:
586 case lir_cmp_fd2i:
587 case lir_add:
588 case lir_sub:
589 case lir_rem:
590 case lir_sqrt:
591 case lir_abs:
592 case lir_neg:
593 case lir_logic_and:
594 case lir_logic_or:
595 case lir_logic_xor:
596 case lir_shl:
597 case lir_shr:
598 case lir_ushr:
599 case lir_xadd:
600 case lir_xchg:
601 case lir_assert:
602 {
603 assert(op->as_Op2() != NULL, "must be");
604 LIR_Op2* op2 = (LIR_Op2*)op;
605 assert(op2->_tmp2->is_illegal() && op2->_tmp3->is_illegal() &&
606 op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used");
607
608 if (op2->_info) do_info(op2->_info);
609 if (op2->_opr1->is_valid()) do_input(op2->_opr1);
610 if (op2->_opr2->is_valid()) do_input(op2->_opr2);
611 if (op2->_tmp1->is_valid()) do_temp(op2->_tmp1);
612 if (op2->_result->is_valid()) do_output(op2->_result);
613 if (op->code() == lir_xchg || op->code() == lir_xadd) {
614 // on ARM and PPC, return value is loaded first so could
615 // destroy inputs. On other platforms that implement those
616 // (x86, sparc), the extra constrainsts are harmless.
617 if (op2->_opr1->is_valid()) do_temp(op2->_opr1);
618 if (op2->_opr2->is_valid()) do_temp(op2->_opr2);
619 }
620
621 break;
622 }
623
624 // special handling for cmove: right input operand must not be equal
625 // to the result operand, otherwise the backend fails
626 case lir_cmove:
627 {
628 #ifdef RISCV
629 assert(op->as_Op4() != NULL, "must be");
630 LIR_Op4* op4 = (LIR_Op4*)op;
631
632 assert(op4->_info == NULL && op4->_tmp1->is_illegal() && op4->_tmp2->is_illegal() &&
633 op4->_tmp3->is_illegal() && op4->_tmp4->is_illegal() && op4->_tmp5->is_illegal(), "not used");
634 assert(op4->_opr1->is_valid() && op4->_opr2->is_valid() && op4->_result->is_valid(), "used");
635
636 do_input(op4->_opr1);
637 do_input(op4->_opr2);
638 if (op4->_opr3->is_valid()) do_input(op4->_opr3);
639 if (op4->_opr4->is_valid()) do_input(op4->_opr4);
640 do_temp(op4->_opr2);
641 do_output(op4->_result);
642 #else
643 assert(op->as_Op2() != NULL, "must be");
644 LIR_Op2* op2 = (LIR_Op2*)op;
645
646 assert(op2->_info == NULL && op2->_tmp1->is_illegal() && op2->_tmp2->is_illegal() &&
647 op2->_tmp3->is_illegal() && op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used");
648 assert(op2->_opr1->is_valid() && op2->_opr2->is_valid() && op2->_result->is_valid(), "used");
649
650 do_input(op2->_opr1);
651 do_input(op2->_opr2);
652 do_temp(op2->_opr2);
653 do_output(op2->_result);
654 #endif
655
656 break;
657 }
658
659 // vspecial handling for strict operations: register input operands
660 // as temp to guarantee that they do not overlap with other
661 // registers
662 case lir_mul:
663 case lir_div:
664 {
665 assert(op->as_Op2() != NULL, "must be");
666 LIR_Op2* op2 = (LIR_Op2*)op;
667
668 assert(op2->_info == NULL, "not used");
669 assert(op2->_opr1->is_valid(), "used");
670 assert(op2->_opr2->is_valid(), "used");
671 assert(op2->_result->is_valid(), "used");
672 assert(op2->_tmp2->is_illegal() && op2->_tmp3->is_illegal() &&
673 op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used");
674
675 do_input(op2->_opr1); do_temp(op2->_opr1);
676 do_input(op2->_opr2); do_temp(op2->_opr2);
677 if (op2->_tmp1->is_valid()) do_temp(op2->_tmp1);
678 do_output(op2->_result);
679
680 break;
681 }
682
683 case lir_throw: {
684 assert(op->as_Op2() != NULL, "must be");
685 LIR_Op2* op2 = (LIR_Op2*)op;
686
687 if (op2->_info) do_info(op2->_info);
688 if (op2->_opr1->is_valid()) do_temp(op2->_opr1);
689 if (op2->_opr2->is_valid()) do_input(op2->_opr2); // exception object is input parameter
690 assert(op2->_result->is_illegal(), "no result");
691 assert(op2->_tmp2->is_illegal() && op2->_tmp3->is_illegal() &&
692 op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used");
693
694 break;
695 }
696
697 case lir_unwind: {
698 assert(op->as_Op1() != NULL, "must be");
699 LIR_Op1* op1 = (LIR_Op1*)op;
700
701 assert(op1->_info == NULL, "no info");
702 assert(op1->_opr->is_valid(), "exception oop"); do_input(op1->_opr);
703 assert(op1->_result->is_illegal(), "no result");
704
705 break;
706 }
707
708 // LIR_Op3
709 case lir_idiv:
710 case lir_irem: {
711 assert(op->as_Op3() != NULL, "must be");
712 LIR_Op3* op3= (LIR_Op3*)op;
713
714 if (op3->_info) do_info(op3->_info);
715 if (op3->_opr1->is_valid()) do_input(op3->_opr1);
716
717 // second operand is input and temp, so ensure that second operand
718 // and third operand get not the same register
719 if (op3->_opr2->is_valid()) do_input(op3->_opr2);
720 if (op3->_opr2->is_valid()) do_temp(op3->_opr2);
721 if (op3->_opr3->is_valid()) do_temp(op3->_opr3);
722
723 if (op3->_result->is_valid()) do_output(op3->_result);
724
725 break;
726 }
727
728 case lir_fmad:
729 case lir_fmaf: {
730 assert(op->as_Op3() != NULL, "must be");
731 LIR_Op3* op3= (LIR_Op3*)op;
732 assert(op3->_info == NULL, "no info");
733 do_input(op3->_opr1);
734 do_input(op3->_opr2);
735 do_input(op3->_opr3);
736 do_output(op3->_result);
737 break;
738 }
739
740 // LIR_OpJavaCall
741 case lir_static_call:
742 case lir_optvirtual_call:
743 case lir_icvirtual_call:
744 case lir_dynamic_call: {
745 LIR_OpJavaCall* opJavaCall = op->as_OpJavaCall();
746 assert(opJavaCall != NULL, "must be");
747
748 if (opJavaCall->_receiver->is_valid()) do_input(opJavaCall->_receiver);
749
750 // only visit register parameters
751 int n = opJavaCall->_arguments->length();
752 for (int i = opJavaCall->_receiver->is_valid() ? 1 : 0; i < n; i++) {
753 if (!opJavaCall->_arguments->at(i)->is_pointer()) {
754 do_input(*opJavaCall->_arguments->adr_at(i));
755 }
756 }
757
758 if (opJavaCall->_info) do_info(opJavaCall->_info);
759 if (FrameMap::method_handle_invoke_SP_save_opr() != LIR_OprFact::illegalOpr &&
760 opJavaCall->is_method_handle_invoke()) {
761 opJavaCall->_method_handle_invoke_SP_save_opr = FrameMap::method_handle_invoke_SP_save_opr();
762 do_temp(opJavaCall->_method_handle_invoke_SP_save_opr);
763 }
764 do_call();
765 if (opJavaCall->_result->is_valid()) do_output(opJavaCall->_result);
766
767 break;
768 }
769
770
771 // LIR_OpRTCall
772 case lir_rtcall: {
773 assert(op->as_OpRTCall() != NULL, "must be");
774 LIR_OpRTCall* opRTCall = (LIR_OpRTCall*)op;
775
776 // only visit register parameters
777 int n = opRTCall->_arguments->length();
778 for (int i = 0; i < n; i++) {
779 if (!opRTCall->_arguments->at(i)->is_pointer()) {
780 do_input(*opRTCall->_arguments->adr_at(i));
781 }
782 }
783 if (opRTCall->_info) do_info(opRTCall->_info);
784 if (opRTCall->_tmp->is_valid()) do_temp(opRTCall->_tmp);
785 do_call();
786 if (opRTCall->_result->is_valid()) do_output(opRTCall->_result);
787
788 break;
789 }
790
791
792 // LIR_OpArrayCopy
793 case lir_arraycopy: {
794 assert(op->as_OpArrayCopy() != NULL, "must be");
795 LIR_OpArrayCopy* opArrayCopy = (LIR_OpArrayCopy*)op;
796
797 assert(opArrayCopy->_result->is_illegal(), "unused");
798 assert(opArrayCopy->_src->is_valid(), "used"); do_input(opArrayCopy->_src); do_temp(opArrayCopy->_src);
799 assert(opArrayCopy->_src_pos->is_valid(), "used"); do_input(opArrayCopy->_src_pos); do_temp(opArrayCopy->_src_pos);
800 assert(opArrayCopy->_dst->is_valid(), "used"); do_input(opArrayCopy->_dst); do_temp(opArrayCopy->_dst);
801 assert(opArrayCopy->_dst_pos->is_valid(), "used"); do_input(opArrayCopy->_dst_pos); do_temp(opArrayCopy->_dst_pos);
802 assert(opArrayCopy->_length->is_valid(), "used"); do_input(opArrayCopy->_length); do_temp(opArrayCopy->_length);
803 assert(opArrayCopy->_tmp->is_valid(), "used"); do_temp(opArrayCopy->_tmp);
804 if (opArrayCopy->_info) do_info(opArrayCopy->_info);
805
806 // the implementation of arraycopy always has a call into the runtime
807 do_call();
808
809 break;
810 }
811
812
813 // LIR_OpUpdateCRC32
814 case lir_updatecrc32: {
815 assert(op->as_OpUpdateCRC32() != NULL, "must be");
816 LIR_OpUpdateCRC32* opUp = (LIR_OpUpdateCRC32*)op;
817
818 assert(opUp->_crc->is_valid(), "used"); do_input(opUp->_crc); do_temp(opUp->_crc);
819 assert(opUp->_val->is_valid(), "used"); do_input(opUp->_val); do_temp(opUp->_val);
820 assert(opUp->_result->is_valid(), "used"); do_output(opUp->_result);
821 assert(opUp->_info == NULL, "no info for LIR_OpUpdateCRC32");
822
823 break;
824 }
825
826
827 // LIR_OpLock
828 case lir_lock:
829 case lir_unlock: {
830 assert(op->as_OpLock() != NULL, "must be");
831 LIR_OpLock* opLock = (LIR_OpLock*)op;
832
833 if (opLock->_info) do_info(opLock->_info);
834
835 // TODO: check if these operands really have to be temp
836 // (or if input is sufficient). This may have influence on the oop map!
837 assert(opLock->_lock->is_valid(), "used"); do_temp(opLock->_lock);
838 assert(opLock->_hdr->is_valid(), "used"); do_temp(opLock->_hdr);
839 assert(opLock->_obj->is_valid(), "used"); do_temp(opLock->_obj);
840
841 if (opLock->_scratch->is_valid()) do_temp(opLock->_scratch);
842 assert(opLock->_result->is_illegal(), "unused");
843
844 do_stub(opLock->_stub);
845
846 break;
847 }
848
849
850 // LIR_OpDelay
851 case lir_delay_slot: {
852 assert(op->as_OpDelay() != NULL, "must be");
853 LIR_OpDelay* opDelay = (LIR_OpDelay*)op;
854
855 visit(opDelay->delay_op());
856 break;
857 }
858
859 // LIR_OpTypeCheck
860 case lir_instanceof:
861 case lir_checkcast:
862 case lir_store_check: {
863 assert(op->as_OpTypeCheck() != NULL, "must be");
864 LIR_OpTypeCheck* opTypeCheck = (LIR_OpTypeCheck*)op;
865
866 if (opTypeCheck->_info_for_exception) do_info(opTypeCheck->_info_for_exception);
867 if (opTypeCheck->_info_for_patch) do_info(opTypeCheck->_info_for_patch);
868 if (opTypeCheck->_object->is_valid()) do_input(opTypeCheck->_object);
869 if (op->code() == lir_store_check && opTypeCheck->_object->is_valid()) {
870 do_temp(opTypeCheck->_object);
871 }
872 if (opTypeCheck->_array->is_valid()) do_input(opTypeCheck->_array);
873 if (opTypeCheck->_tmp1->is_valid()) do_temp(opTypeCheck->_tmp1);
874 if (opTypeCheck->_tmp2->is_valid()) do_temp(opTypeCheck->_tmp2);
875 if (opTypeCheck->_tmp3->is_valid()) do_temp(opTypeCheck->_tmp3);
876 if (opTypeCheck->_result->is_valid()) do_output(opTypeCheck->_result);
877 do_stub(opTypeCheck->_stub);
878 break;
879 }
880
881 // LIR_OpCompareAndSwap
882 case lir_cas_long:
883 case lir_cas_obj:
884 case lir_cas_int: {
885 assert(op->as_OpCompareAndSwap() != NULL, "must be");
886 LIR_OpCompareAndSwap* opCompareAndSwap = (LIR_OpCompareAndSwap*)op;
887
888 assert(opCompareAndSwap->_addr->is_valid(), "used");
889 assert(opCompareAndSwap->_cmp_value->is_valid(), "used");
890 assert(opCompareAndSwap->_new_value->is_valid(), "used");
891 if (opCompareAndSwap->_info) do_info(opCompareAndSwap->_info);
892 do_input(opCompareAndSwap->_addr);
893 do_temp(opCompareAndSwap->_addr);
894 do_input(opCompareAndSwap->_cmp_value);
895 do_temp(opCompareAndSwap->_cmp_value);
896 do_input(opCompareAndSwap->_new_value);
897 do_temp(opCompareAndSwap->_new_value);
898 if (opCompareAndSwap->_tmp1->is_valid()) do_temp(opCompareAndSwap->_tmp1);
899 if (opCompareAndSwap->_tmp2->is_valid()) do_temp(opCompareAndSwap->_tmp2);
900 if (opCompareAndSwap->_result->is_valid()) do_output(opCompareAndSwap->_result);
901
902 break;
903 }
904
905
906 // LIR_OpAllocArray;
907 case lir_alloc_array: {
908 assert(op->as_OpAllocArray() != NULL, "must be");
909 LIR_OpAllocArray* opAllocArray = (LIR_OpAllocArray*)op;
910
911 if (opAllocArray->_info) do_info(opAllocArray->_info);
912 if (opAllocArray->_klass->is_valid()) do_input(opAllocArray->_klass); do_temp(opAllocArray->_klass);
913 if (opAllocArray->_len->is_valid()) do_input(opAllocArray->_len); do_temp(opAllocArray->_len);
914 if (opAllocArray->_tmp1->is_valid()) do_temp(opAllocArray->_tmp1);
915 if (opAllocArray->_tmp2->is_valid()) do_temp(opAllocArray->_tmp2);
916 if (opAllocArray->_tmp3->is_valid()) do_temp(opAllocArray->_tmp3);
917 if (opAllocArray->_tmp4->is_valid()) do_temp(opAllocArray->_tmp4);
918 if (opAllocArray->_result->is_valid()) do_output(opAllocArray->_result);
919 do_stub(opAllocArray->_stub);
920 break;
921 }
922
923 // LIR_OpLoadKlass
924 case lir_load_klass:
925 {
926 LIR_OpLoadKlass* opLoadKlass = op->as_OpLoadKlass();
927 assert(opLoadKlass != NULL, "must be");
928
929 do_input(opLoadKlass->_obj);
930 do_output(opLoadKlass->_result);
931 if (opLoadKlass->_info) do_info(opLoadKlass->_info);
932 break;
933 }
934
935
936 // LIR_OpProfileCall:
937 case lir_profile_call: {
938 assert(op->as_OpProfileCall() != NULL, "must be");
939 LIR_OpProfileCall* opProfileCall = (LIR_OpProfileCall*)op;
940
941 if (opProfileCall->_recv->is_valid()) do_temp(opProfileCall->_recv);
942 assert(opProfileCall->_mdo->is_valid(), "used"); do_temp(opProfileCall->_mdo);
943 assert(opProfileCall->_tmp1->is_valid(), "used"); do_temp(opProfileCall->_tmp1);
944 break;
945 }
946
947 // LIR_OpProfileType:
948 case lir_profile_type: {
949 assert(op->as_OpProfileType() != NULL, "must be");
950 LIR_OpProfileType* opProfileType = (LIR_OpProfileType*)op;
951
952 do_input(opProfileType->_mdp); do_temp(opProfileType->_mdp);
953 do_input(opProfileType->_obj);
954 do_temp(opProfileType->_tmp);
955 break;
956 }
957 default:
958 op->visit(this);
959 }
960 }
961
962 void LIR_Op::visit(LIR_OpVisitState* state) {
963 ShouldNotReachHere();
964 }
965
966 void LIR_OpVisitState::do_stub(CodeStub* stub) {
967 if (stub != NULL) {
968 stub->visit(this);
969 }
970 }
971
972 XHandlers* LIR_OpVisitState::all_xhandler() {
973 XHandlers* result = NULL;
974
975 int i;
976 for (i = 0; i < info_count(); i++) {
977 if (info_at(i)->exception_handlers() != NULL) {
978 result = info_at(i)->exception_handlers();
979 break;
980 }
981 }
982
983 #ifdef ASSERT
984 for (i = 0; i < info_count(); i++) {
985 assert(info_at(i)->exception_handlers() == NULL ||
986 info_at(i)->exception_handlers() == result,
987 "only one xhandler list allowed per LIR-operation");
988 }
989 #endif
990
991 if (result != NULL) {
992 return result;
993 } else {
994 return new XHandlers();
995 }
996
997 return result;
998 }
999
1000
1001 #ifdef ASSERT
1002 bool LIR_OpVisitState::no_operands(LIR_Op* op) {
1003 visit(op);
1004
1005 return opr_count(inputMode) == 0 &&
1006 opr_count(outputMode) == 0 &&
1007 opr_count(tempMode) == 0 &&
1008 info_count() == 0 &&
1009 !has_call() &&
1010 !has_slow_case();
1011 }
1012 #endif
1013
1014 // LIR_OpReturn
1015 LIR_OpReturn::LIR_OpReturn(LIR_Opr opr) :
1016 LIR_Op1(lir_return, opr, (CodeEmitInfo*)NULL /* info */),
1017 _stub(NULL) {
1018 if (VM_Version::supports_stack_watermark_barrier()) {
1019 _stub = new C1SafepointPollStub();
1020 }
1021 }
1022
1023 //---------------------------------------------------
1024
1025
1026 void LIR_OpJavaCall::emit_code(LIR_Assembler* masm) {
1027 masm->emit_call(this);
1028 }
1029
1030 void LIR_OpRTCall::emit_code(LIR_Assembler* masm) {
1031 masm->emit_rtcall(this);
1032 }
1033
1034 void LIR_OpLabel::emit_code(LIR_Assembler* masm) {
1035 masm->emit_opLabel(this);
1036 }
1037
1038 void LIR_OpArrayCopy::emit_code(LIR_Assembler* masm) {
1039 masm->emit_arraycopy(this);
1040 masm->append_code_stub(stub());
1041 }
1042
1043 void LIR_OpUpdateCRC32::emit_code(LIR_Assembler* masm) {
1044 masm->emit_updatecrc32(this);
1045 }
1046
1047 void LIR_Op0::emit_code(LIR_Assembler* masm) {
1048 masm->emit_op0(this);
1049 }
1050
1051 void LIR_Op1::emit_code(LIR_Assembler* masm) {
1052 masm->emit_op1(this);
1053 }
1054
1055 void LIR_OpAllocObj::emit_code(LIR_Assembler* masm) {
1056 masm->emit_alloc_obj(this);
1057 masm->append_code_stub(stub());
1058 }
1059
1060 void LIR_OpBranch::emit_code(LIR_Assembler* masm) {
1061 masm->emit_opBranch(this);
1062 if (stub()) {
1063 masm->append_code_stub(stub());
1064 }
1065 }
1066
1067 void LIR_OpConvert::emit_code(LIR_Assembler* masm) {
1068 masm->emit_opConvert(this);
1069 if (stub() != NULL) {
1070 masm->append_code_stub(stub());
1071 }
1072 }
1073
1074 void LIR_Op2::emit_code(LIR_Assembler* masm) {
1075 masm->emit_op2(this);
1076 }
1077
1078 void LIR_OpAllocArray::emit_code(LIR_Assembler* masm) {
1079 masm->emit_alloc_array(this);
1080 masm->append_code_stub(stub());
1081 }
1082
1083 void LIR_OpTypeCheck::emit_code(LIR_Assembler* masm) {
1084 masm->emit_opTypeCheck(this);
1085 if (stub()) {
1086 masm->append_code_stub(stub());
1087 }
1088 }
1089
1090 void LIR_OpCompareAndSwap::emit_code(LIR_Assembler* masm) {
1091 masm->emit_compare_and_swap(this);
1092 }
1093
1094 void LIR_Op3::emit_code(LIR_Assembler* masm) {
1095 masm->emit_op3(this);
1096 }
1097
1098 #ifdef RISCV
1099 void LIR_Op4::emit_code(LIR_Assembler* masm) {
1100 masm->emit_op4(this);
1101 }
1102 #endif
1103
1104 void LIR_OpLock::emit_code(LIR_Assembler* masm) {
1105 masm->emit_lock(this);
1106 if (stub()) {
1107 masm->append_code_stub(stub());
1108 }
1109 }
1110
1111 void LIR_OpLoadKlass::emit_code(LIR_Assembler* masm) {
1112 masm->emit_load_klass(this);
1113 }
1114
1115 #ifdef ASSERT
1116 void LIR_OpAssert::emit_code(LIR_Assembler* masm) {
1117 masm->emit_assert(this);
1118 }
1119 #endif
1120
1121 void LIR_OpDelay::emit_code(LIR_Assembler* masm) {
1122 masm->emit_delay(this);
1123 }
1124
1125 void LIR_OpProfileCall::emit_code(LIR_Assembler* masm) {
1126 masm->emit_profile_call(this);
1127 }
1128
1129 void LIR_OpProfileType::emit_code(LIR_Assembler* masm) {
1130 masm->emit_profile_type(this);
1131 }
1132
1133 // LIR_List
1134 LIR_List::LIR_List(Compilation* compilation, BlockBegin* block)
1135 : _operations(8)
1136 , _compilation(compilation)
1137 #ifndef PRODUCT
1138 , _block(block)
1139 #endif
1140 #ifdef ASSERT
1141 , _file(NULL)
1142 , _line(0)
1143 #endif
1144 #ifdef RISCV
1145 , _cmp_opr1(LIR_OprFact::illegalOpr)
1146 , _cmp_opr2(LIR_OprFact::illegalOpr)
1147 #endif
1148 { }
1149
1150
1151 #ifdef ASSERT
1152 void LIR_List::set_file_and_line(const char * file, int line) {
1153 const char * f = strrchr(file, '/');
1154 if (f == NULL) f = strrchr(file, '\\');
1155 if (f == NULL) {
1156 f = file;
1157 } else {
1158 f++;
1159 }
1160 _file = f;
1161 _line = line;
1162 }
1163 #endif
1164
1165 #ifdef RISCV
1166 void LIR_List::set_cmp_oprs(LIR_Op* op) {
1167 switch (op->code()) {
1168 case lir_cmp:
1169 _cmp_opr1 = op->as_Op2()->in_opr1();
1170 _cmp_opr2 = op->as_Op2()->in_opr2();
1171 break;
1172 case lir_branch: // fall through
1173 case lir_cond_float_branch:
1174 assert(op->as_OpBranch()->cond() == lir_cond_always ||
1175 (_cmp_opr1 != LIR_OprFact::illegalOpr && _cmp_opr2 != LIR_OprFact::illegalOpr),
1176 "conditional branches must have legal operands");
1177 if (op->as_OpBranch()->cond() != lir_cond_always) {
1178 op->as_Op2()->set_in_opr1(_cmp_opr1);
1179 op->as_Op2()->set_in_opr2(_cmp_opr2);
1180 }
1181 break;
1182 case lir_cmove:
1183 op->as_Op4()->set_in_opr3(_cmp_opr1);
1184 op->as_Op4()->set_in_opr4(_cmp_opr2);
1185 break;
1186 #if INCLUDE_ZGC
1187 case lir_zloadbarrier_test:
1188 _cmp_opr1 = FrameMap::as_opr(t1);
1189 _cmp_opr2 = LIR_OprFact::intConst(0);
1190 break;
1191 #endif
1192 default:
1193 break;
1194 }
1195 }
1196 #endif
1197
1198 void LIR_List::append(LIR_InsertionBuffer* buffer) {
1199 assert(this == buffer->lir_list(), "wrong lir list");
1200 const int n = _operations.length();
1201
1202 if (buffer->number_of_ops() > 0) {
1203 // increase size of instructions list
1204 _operations.at_grow(n + buffer->number_of_ops() - 1, NULL);
1205 // insert ops from buffer into instructions list
1206 int op_index = buffer->number_of_ops() - 1;
1207 int ip_index = buffer->number_of_insertion_points() - 1;
1208 int from_index = n - 1;
1209 int to_index = _operations.length() - 1;
1210 for (; ip_index >= 0; ip_index --) {
1211 int index = buffer->index_at(ip_index);
1212 // make room after insertion point
1213 while (index < from_index) {
1214 _operations.at_put(to_index --, _operations.at(from_index --));
1215 }
1216 // insert ops from buffer
1217 for (int i = buffer->count_at(ip_index); i > 0; i --) {
1218 _operations.at_put(to_index --, buffer->op_at(op_index --));
1219 }
1220 }
1221 }
1222
1223 buffer->finish();
1224 }
1225
1226
1227 void LIR_List::oop2reg_patch(jobject o, LIR_Opr reg, CodeEmitInfo* info) {
1228 assert(reg->type() == T_OBJECT, "bad reg");
1229 append(new LIR_Op1(lir_move, LIR_OprFact::oopConst(o), reg, T_OBJECT, lir_patch_normal, info));
1230 }
1231
1232 void LIR_List::klass2reg_patch(Metadata* o, LIR_Opr reg, CodeEmitInfo* info) {
1233 assert(reg->type() == T_METADATA, "bad reg");
1234 append(new LIR_Op1(lir_move, LIR_OprFact::metadataConst(o), reg, T_METADATA, lir_patch_normal, info));
1235 }
1236
1237 void LIR_List::load(LIR_Address* addr, LIR_Opr src, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1238 append(new LIR_Op1(
1239 lir_move,
1240 LIR_OprFact::address(addr),
1241 src,
1242 addr->type(),
1243 patch_code,
1244 info));
1245 }
1246
1247
1248 void LIR_List::volatile_load_mem_reg(LIR_Address* address, LIR_Opr dst, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1249 append(new LIR_Op1(
1250 lir_move,
1251 LIR_OprFact::address(address),
1252 dst,
1253 address->type(),
1254 patch_code,
1255 info, lir_move_volatile));
1256 }
1257
1258 void LIR_List::volatile_load_unsafe_reg(LIR_Opr base, LIR_Opr offset, LIR_Opr dst, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1259 append(new LIR_Op1(
1260 lir_move,
1261 LIR_OprFact::address(new LIR_Address(base, offset, type)),
1262 dst,
1263 type,
1264 patch_code,
1265 info, lir_move_volatile));
1266 }
1267
1268
1269 void LIR_List::store_mem_int(jint v, LIR_Opr base, int offset_in_bytes, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1270 append(new LIR_Op1(
1271 lir_move,
1272 LIR_OprFact::intConst(v),
1273 LIR_OprFact::address(new LIR_Address(base, offset_in_bytes, type)),
1274 type,
1275 patch_code,
1276 info));
1277 }
1278
1279
1280 void LIR_List::store_mem_oop(jobject o, LIR_Opr base, int offset_in_bytes, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1281 append(new LIR_Op1(
1282 lir_move,
1283 LIR_OprFact::oopConst(o),
1284 LIR_OprFact::address(new LIR_Address(base, offset_in_bytes, type)),
1285 type,
1286 patch_code,
1287 info));
1288 }
1289
1290
1291 void LIR_List::store(LIR_Opr src, LIR_Address* addr, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1292 append(new LIR_Op1(
1293 lir_move,
1294 src,
1295 LIR_OprFact::address(addr),
1296 addr->type(),
1297 patch_code,
1298 info));
1299 }
1300
1301
1302 void LIR_List::volatile_store_mem_reg(LIR_Opr src, LIR_Address* addr, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1303 append(new LIR_Op1(
1304 lir_move,
1305 src,
1306 LIR_OprFact::address(addr),
1307 addr->type(),
1308 patch_code,
1309 info,
1310 lir_move_volatile));
1311 }
1312
1313 void LIR_List::volatile_store_unsafe_reg(LIR_Opr src, LIR_Opr base, LIR_Opr offset, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1314 append(new LIR_Op1(
1315 lir_move,
1316 src,
1317 LIR_OprFact::address(new LIR_Address(base, offset, type)),
1318 type,
1319 patch_code,
1320 info, lir_move_volatile));
1321 }
1322
1323
1324 void LIR_List::idiv(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1325 append(new LIR_Op3(
1326 lir_idiv,
1327 left,
1328 right,
1329 tmp,
1330 res,
1331 info));
1332 }
1333
1334
1335 void LIR_List::idiv(LIR_Opr left, int right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1336 append(new LIR_Op3(
1337 lir_idiv,
1338 left,
1339 LIR_OprFact::intConst(right),
1340 tmp,
1341 res,
1342 info));
1343 }
1344
1345
1346 void LIR_List::irem(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1347 append(new LIR_Op3(
1348 lir_irem,
1349 left,
1350 right,
1351 tmp,
1352 res,
1353 info));
1354 }
1355
1356
1357 void LIR_List::irem(LIR_Opr left, int right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1358 append(new LIR_Op3(
1359 lir_irem,
1360 left,
1361 LIR_OprFact::intConst(right),
1362 tmp,
1363 res,
1364 info));
1365 }
1366
1367
1368 void LIR_List::cmp_mem_int(LIR_Condition condition, LIR_Opr base, int disp, int c, CodeEmitInfo* info) {
1369 append(new LIR_Op2(
1370 lir_cmp,
1371 condition,
1372 LIR_OprFact::address(new LIR_Address(base, disp, T_INT)),
1373 LIR_OprFact::intConst(c),
1374 info));
1375 }
1376
1377
1378 void LIR_List::cmp_reg_mem(LIR_Condition condition, LIR_Opr reg, LIR_Address* addr, CodeEmitInfo* info) {
1379 append(new LIR_Op2(
1380 lir_cmp,
1381 condition,
1382 reg,
1383 LIR_OprFact::address(addr),
1384 info));
1385 }
1386
1387 void LIR_List::allocate_object(LIR_Opr dst, LIR_Opr t1, LIR_Opr t2, LIR_Opr t3, LIR_Opr t4,
1388 int header_size, int object_size, LIR_Opr klass, bool init_check, CodeStub* stub) {
1389 append(new LIR_OpAllocObj(
1390 klass,
1391 dst,
1392 t1,
1393 t2,
1394 t3,
1395 t4,
1396 header_size,
1397 object_size,
1398 init_check,
1399 stub));
1400 }
1401
1402 void LIR_List::allocate_array(LIR_Opr dst, LIR_Opr len, LIR_Opr t1,LIR_Opr t2, LIR_Opr t3,LIR_Opr t4, BasicType type, LIR_Opr klass, CodeStub* stub) {
1403 append(new LIR_OpAllocArray(
1404 klass,
1405 len,
1406 dst,
1407 t1,
1408 t2,
1409 t3,
1410 t4,
1411 type,
1412 stub));
1413 }
1414
1415 void LIR_List::shift_left(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) {
1416 append(new LIR_Op2(
1417 lir_shl,
1418 value,
1419 count,
1420 dst,
1421 tmp));
1422 }
1423
1424 void LIR_List::shift_right(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) {
1425 append(new LIR_Op2(
1426 lir_shr,
1427 value,
1428 count,
1429 dst,
1430 tmp));
1431 }
1432
1433
1434 void LIR_List::unsigned_shift_right(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) {
1435 append(new LIR_Op2(
1436 lir_ushr,
1437 value,
1438 count,
1439 dst,
1440 tmp));
1441 }
1442
1443 void LIR_List::fcmp2int(LIR_Opr left, LIR_Opr right, LIR_Opr dst, bool is_unordered_less) {
1444 append(new LIR_Op2(is_unordered_less ? lir_ucmp_fd2i : lir_cmp_fd2i,
1445 left,
1446 right,
1447 dst));
1448 }
1449
1450 void LIR_List::lock_object(LIR_Opr hdr, LIR_Opr obj, LIR_Opr lock, LIR_Opr scratch, CodeStub* stub, CodeEmitInfo* info) {
1451 append(new LIR_OpLock(
1452 lir_lock,
1453 hdr,
1454 obj,
1455 lock,
1456 scratch,
1457 stub,
1458 info));
1459 }
1460
1461 void LIR_List::unlock_object(LIR_Opr hdr, LIR_Opr obj, LIR_Opr lock, LIR_Opr scratch, CodeStub* stub) {
1462 append(new LIR_OpLock(
1463 lir_unlock,
1464 hdr,
1465 obj,
1466 lock,
1467 scratch,
1468 stub,
1469 NULL));
1470 }
1471
1472
1473 void check_LIR() {
1474 // cannot do the proper checking as PRODUCT and other modes return different results
1475 // guarantee(sizeof(LIR_OprDesc) == wordSize, "may not have a v-table");
1476 }
1477
1478
1479
1480 void LIR_List::checkcast (LIR_Opr result, LIR_Opr object, ciKlass* klass,
1481 LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, bool fast_check,
1482 CodeEmitInfo* info_for_exception, CodeEmitInfo* info_for_patch, CodeStub* stub,
1483 ciMethod* profiled_method, int profiled_bci) {
1484 LIR_OpTypeCheck* c = new LIR_OpTypeCheck(lir_checkcast, result, object, klass,
1485 tmp1, tmp2, tmp3, fast_check, info_for_exception, info_for_patch, stub);
1486 if (profiled_method != NULL) {
1487 c->set_profiled_method(profiled_method);
1488 c->set_profiled_bci(profiled_bci);
1489 c->set_should_profile(true);
1490 }
1491 append(c);
1492 }
1493
1494 void LIR_List::instanceof(LIR_Opr result, LIR_Opr object, ciKlass* klass, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, bool fast_check, CodeEmitInfo* info_for_patch, ciMethod* profiled_method, int profiled_bci) {
1495 LIR_OpTypeCheck* c = new LIR_OpTypeCheck(lir_instanceof, result, object, klass, tmp1, tmp2, tmp3, fast_check, NULL, info_for_patch, NULL);
1496 if (profiled_method != NULL) {
1497 c->set_profiled_method(profiled_method);
1498 c->set_profiled_bci(profiled_bci);
1499 c->set_should_profile(true);
1500 }
1501 append(c);
1502 }
1503
1504
1505 void LIR_List::store_check(LIR_Opr object, LIR_Opr array, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3,
1506 CodeEmitInfo* info_for_exception, ciMethod* profiled_method, int profiled_bci) {
1507 LIR_OpTypeCheck* c = new LIR_OpTypeCheck(lir_store_check, object, array, tmp1, tmp2, tmp3, info_for_exception);
1508 if (profiled_method != NULL) {
1509 c->set_profiled_method(profiled_method);
1510 c->set_profiled_bci(profiled_bci);
1511 c->set_should_profile(true);
1512 }
1513 append(c);
1514 }
1515
1516 void LIR_List::null_check(LIR_Opr opr, CodeEmitInfo* info, bool deoptimize_on_null) {
1517 if (deoptimize_on_null) {
1518 // Emit an explicit null check and deoptimize if opr is null
1519 CodeStub* deopt = new DeoptimizeStub(info, Deoptimization::Reason_null_check, Deoptimization::Action_none);
1520 cmp(lir_cond_equal, opr, LIR_OprFact::oopConst(NULL));
1521 branch(lir_cond_equal, deopt);
1522 } else {
1523 // Emit an implicit null check
1524 append(new LIR_Op1(lir_null_check, opr, info));
1525 }
1526 }
1527
1528 void LIR_List::cas_long(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value,
1529 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
1530 append(new LIR_OpCompareAndSwap(lir_cas_long, addr, cmp_value, new_value, t1, t2, result));
1531 }
1532
1533 void LIR_List::cas_obj(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value,
1534 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
1535 append(new LIR_OpCompareAndSwap(lir_cas_obj, addr, cmp_value, new_value, t1, t2, result));
1536 }
1537
1538 void LIR_List::cas_int(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value,
1539 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
1540 append(new LIR_OpCompareAndSwap(lir_cas_int, addr, cmp_value, new_value, t1, t2, result));
1541 }
1542
1543
1544 #ifdef PRODUCT
1545
1546 void print_LIR(BlockList* blocks) {
1547 }
1548
1549 #else
1550 // LIR_OprDesc
1551 void LIR_OprDesc::print() const {
1552 print(tty);
1553 }
1554
1555 void LIR_OprDesc::print(outputStream* out) const {
1556 if (is_illegal()) {
1557 return;
1558 }
1559
1560 out->print("[");
1561 if (is_pointer()) {
1562 pointer()->print_value_on(out);
1563 } else if (is_single_stack()) {
1564 out->print("stack:%d", single_stack_ix());
1565 } else if (is_double_stack()) {
1566 out->print("dbl_stack:%d",double_stack_ix());
1567 } else if (is_virtual()) {
1568 out->print("R%d", vreg_number());
1569 } else if (is_single_cpu()) {
1570 out->print("%s", as_register()->name());
1571 } else if (is_double_cpu()) {
1572 out->print("%s", as_register_hi()->name());
1573 out->print("%s", as_register_lo()->name());
1574 #if defined(X86)
1575 } else if (is_single_xmm()) {
1576 out->print("%s", as_xmm_float_reg()->name());
1577 } else if (is_double_xmm()) {
1578 out->print("%s", as_xmm_double_reg()->name());
1579 } else if (is_single_fpu()) {
1580 out->print("fpu%d", fpu_regnr());
1581 } else if (is_double_fpu()) {
1582 out->print("fpu%d", fpu_regnrLo());
1583 #elif defined(AARCH64)
1584 } else if (is_single_fpu()) {
1585 out->print("fpu%d", fpu_regnr());
1586 } else if (is_double_fpu()) {
1587 out->print("fpu%d", fpu_regnrLo());
1588 #elif defined(ARM)
1589 } else if (is_single_fpu()) {
1590 out->print("s%d", fpu_regnr());
1591 } else if (is_double_fpu()) {
1592 out->print("d%d", fpu_regnrLo() >> 1);
1593 #else
1594 } else if (is_single_fpu()) {
1595 out->print("%s", as_float_reg()->name());
1596 } else if (is_double_fpu()) {
1597 out->print("%s", as_double_reg()->name());
1598 #endif
1599
1600 } else if (is_illegal()) {
1601 out->print("-");
1602 } else {
1603 out->print("Unknown Operand");
1604 }
1605 if (!is_illegal()) {
1606 out->print("|%c", type_char());
1607 }
1608 if (is_register() && is_last_use()) {
1609 out->print("(last_use)");
1610 }
1611 out->print("]");
1612 }
1613
1614
1615 // LIR_Address
1616 void LIR_Const::print_value_on(outputStream* out) const {
1617 switch (type()) {
1618 case T_ADDRESS:out->print("address:%d",as_jint()); break;
1619 case T_INT: out->print("int:%d", as_jint()); break;
1620 case T_LONG: out->print("lng:" JLONG_FORMAT, as_jlong()); break;
1621 case T_FLOAT: out->print("flt:%f", as_jfloat()); break;
1622 case T_DOUBLE: out->print("dbl:%f", as_jdouble()); break;
1623 case T_OBJECT: out->print("obj:" INTPTR_FORMAT, p2i(as_jobject())); break;
1624 case T_METADATA: out->print("metadata:" INTPTR_FORMAT, p2i(as_metadata()));break;
1625 default: out->print("%3d:0x" UINT64_FORMAT_X, type(), (uint64_t)as_jlong()); break;
1626 }
1627 }
1628
1629 // LIR_Address
1630 void LIR_Address::print_value_on(outputStream* out) const {
1631 out->print("Base:"); _base->print(out);
1632 if (!_index->is_illegal()) {
1633 out->print(" Index:"); _index->print(out);
1634 switch (scale()) {
1635 case times_1: break;
1636 case times_2: out->print(" * 2"); break;
1637 case times_4: out->print(" * 4"); break;
1638 case times_8: out->print(" * 8"); break;
1639 }
1640 }
1641 out->print(" Disp: " INTX_FORMAT, _disp);
1642 }
1643
1644 // debug output of block header without InstructionPrinter
1645 // (because phi functions are not necessary for LIR)
1646 static void print_block(BlockBegin* x) {
1647 // print block id
1648 BlockEnd* end = x->end();
1649 tty->print("B%d ", x->block_id());
1650
1651 // print flags
1652 if (x->is_set(BlockBegin::std_entry_flag)) tty->print("std ");
1653 if (x->is_set(BlockBegin::osr_entry_flag)) tty->print("osr ");
1654 if (x->is_set(BlockBegin::exception_entry_flag)) tty->print("ex ");
1655 if (x->is_set(BlockBegin::subroutine_entry_flag)) tty->print("jsr ");
1656 if (x->is_set(BlockBegin::backward_branch_target_flag)) tty->print("bb ");
1657 if (x->is_set(BlockBegin::linear_scan_loop_header_flag)) tty->print("lh ");
1658 if (x->is_set(BlockBegin::linear_scan_loop_end_flag)) tty->print("le ");
1659
1660 // print block bci range
1661 tty->print("[%d, %d] ", x->bci(), (end == NULL ? -1 : end->printable_bci()));
1662
1663 // print predecessors and successors
1664 if (x->number_of_preds() > 0) {
1665 tty->print("preds: ");
1666 for (int i = 0; i < x->number_of_preds(); i ++) {
1667 tty->print("B%d ", x->pred_at(i)->block_id());
1668 }
1669 }
1670
1671 if (x->number_of_sux() > 0) {
1672 tty->print("sux: ");
1673 for (int i = 0; i < x->number_of_sux(); i ++) {
1674 tty->print("B%d ", x->sux_at(i)->block_id());
1675 }
1676 }
1677
1678 // print exception handlers
1679 if (x->number_of_exception_handlers() > 0) {
1680 tty->print("xhandler: ");
1681 for (int i = 0; i < x->number_of_exception_handlers(); i++) {
1682 tty->print("B%d ", x->exception_handler_at(i)->block_id());
1683 }
1684 }
1685
1686 tty->cr();
1687 }
1688
1689 void print_LIR(BlockList* blocks) {
1690 tty->print_cr("LIR:");
1691 int i;
1692 for (i = 0; i < blocks->length(); i++) {
1693 BlockBegin* bb = blocks->at(i);
1694 print_block(bb);
1695 tty->print("__id_Instruction___________________________________________"); tty->cr();
1696 bb->lir()->print_instructions();
1697 }
1698 }
1699
1700 void LIR_List::print_instructions() {
1701 for (int i = 0; i < _operations.length(); i++) {
1702 _operations.at(i)->print(); tty->cr();
1703 }
1704 tty->cr();
1705 }
1706
1707 // LIR_Ops printing routines
1708 // LIR_Op
1709 void LIR_Op::print_on(outputStream* out) const {
1710 if (id() != -1 || PrintCFGToFile) {
1711 out->print("%4d ", id());
1712 } else {
1713 out->print(" ");
1714 }
1715 out->print("%s ", name());
1716 print_instr(out);
1717 if (info() != NULL) out->print(" [bci:%d]", info()->stack()->bci());
1718 #ifdef ASSERT
1719 if (Verbose && _file != NULL) {
1720 out->print(" (%s:%d)", _file, _line);
1721 }
1722 #endif
1723 }
1724
1725 const char * LIR_Op::name() const {
1726 const char* s = NULL;
1727 switch(code()) {
1728 // LIR_Op0
1729 case lir_membar: s = "membar"; break;
1730 case lir_membar_acquire: s = "membar_acquire"; break;
1731 case lir_membar_release: s = "membar_release"; break;
1732 case lir_membar_loadload: s = "membar_loadload"; break;
1733 case lir_membar_storestore: s = "membar_storestore"; break;
1734 case lir_membar_loadstore: s = "membar_loadstore"; break;
1735 case lir_membar_storeload: s = "membar_storeload"; break;
1736 case lir_label: s = "label"; break;
1737 case lir_nop: s = "nop"; break;
1738 case lir_on_spin_wait: s = "on_spin_wait"; break;
1739 case lir_backwardbranch_target: s = "backbranch"; break;
1740 case lir_std_entry: s = "std_entry"; break;
1741 case lir_osr_entry: s = "osr_entry"; break;
1742 case lir_fpop_raw: s = "fpop_raw"; break;
1743 case lir_breakpoint: s = "breakpoint"; break;
1744 case lir_get_thread: s = "get_thread"; break;
1745 // LIR_Op1
1746 case lir_fxch: s = "fxch"; break;
1747 case lir_fld: s = "fld"; break;
1748 case lir_push: s = "push"; break;
1749 case lir_pop: s = "pop"; break;
1750 case lir_null_check: s = "null_check"; break;
1751 case lir_return: s = "return"; break;
1752 case lir_safepoint: s = "safepoint"; break;
1753 case lir_leal: s = "leal"; break;
1754 case lir_branch: s = "branch"; break;
1755 case lir_cond_float_branch: s = "flt_cond_br"; break;
1756 case lir_move: s = "move"; break;
1757 case lir_roundfp: s = "roundfp"; break;
1758 case lir_rtcall: s = "rtcall"; break;
1759 case lir_throw: s = "throw"; break;
1760 case lir_unwind: s = "unwind"; break;
1761 case lir_convert: s = "convert"; break;
1762 case lir_alloc_object: s = "alloc_obj"; break;
1763 case lir_monaddr: s = "mon_addr"; break;
1764 // LIR_Op2
1765 case lir_cmp: s = "cmp"; break;
1766 case lir_cmp_l2i: s = "cmp_l2i"; break;
1767 case lir_ucmp_fd2i: s = "ucomp_fd2i"; break;
1768 case lir_cmp_fd2i: s = "comp_fd2i"; break;
1769 case lir_cmove: s = "cmove"; break;
1770 case lir_add: s = "add"; break;
1771 case lir_sub: s = "sub"; break;
1772 case lir_mul: s = "mul"; break;
1773 case lir_div: s = "div"; break;
1774 case lir_rem: s = "rem"; break;
1775 case lir_abs: s = "abs"; break;
1776 case lir_neg: s = "neg"; break;
1777 case lir_sqrt: s = "sqrt"; break;
1778 case lir_logic_and: s = "logic_and"; break;
1779 case lir_logic_or: s = "logic_or"; break;
1780 case lir_logic_xor: s = "logic_xor"; break;
1781 case lir_shl: s = "shift_left"; break;
1782 case lir_shr: s = "shift_right"; break;
1783 case lir_ushr: s = "ushift_right"; break;
1784 case lir_alloc_array: s = "alloc_array"; break;
1785 case lir_xadd: s = "xadd"; break;
1786 case lir_xchg: s = "xchg"; break;
1787 // LIR_Op3
1788 case lir_idiv: s = "idiv"; break;
1789 case lir_irem: s = "irem"; break;
1790 case lir_fmad: s = "fmad"; break;
1791 case lir_fmaf: s = "fmaf"; break;
1792 // LIR_OpJavaCall
1793 case lir_static_call: s = "static"; break;
1794 case lir_optvirtual_call: s = "optvirtual"; break;
1795 case lir_icvirtual_call: s = "icvirtual"; break;
1796 case lir_dynamic_call: s = "dynamic"; break;
1797 // LIR_OpArrayCopy
1798 case lir_arraycopy: s = "arraycopy"; break;
1799 // LIR_OpUpdateCRC32
1800 case lir_updatecrc32: s = "updatecrc32"; break;
1801 // LIR_OpLock
1802 case lir_lock: s = "lock"; break;
1803 case lir_unlock: s = "unlock"; break;
1804 // LIR_OpDelay
1805 case lir_delay_slot: s = "delay"; break;
1806 // LIR_OpTypeCheck
1807 case lir_instanceof: s = "instanceof"; break;
1808 case lir_checkcast: s = "checkcast"; break;
1809 case lir_store_check: s = "store_check"; break;
1810 // LIR_OpCompareAndSwap
1811 case lir_cas_long: s = "cas_long"; break;
1812 case lir_cas_obj: s = "cas_obj"; break;
1813 case lir_cas_int: s = "cas_int"; break;
1814 // LIR_OpProfileCall
1815 case lir_profile_call: s = "profile_call"; break;
1816 // LIR_OpProfileType
1817 case lir_profile_type: s = "profile_type"; break;
1818 // LIR_OpAssert
1819 #ifdef ASSERT
1820 case lir_assert: s = "assert"; break;
1821 #endif
1822 case lir_none: ShouldNotReachHere();break;
1823 default: s = "illegal_op"; break;
1824 }
1825 return s;
1826 }
1827
1828 // LIR_OpJavaCall
1829 void LIR_OpJavaCall::print_instr(outputStream* out) const {
1830 out->print("call: ");
1831 out->print("[addr: " INTPTR_FORMAT "]", p2i(address()));
1832 if (receiver()->is_valid()) {
1833 out->print(" [recv: "); receiver()->print(out); out->print("]");
1834 }
1835 if (result_opr()->is_valid()) {
1836 out->print(" [result: "); result_opr()->print(out); out->print("]");
1837 }
1838 }
1839
1840 // LIR_OpLabel
1841 void LIR_OpLabel::print_instr(outputStream* out) const {
1842 out->print("[label:" INTPTR_FORMAT "]", p2i(_label));
1843 }
1844
1845 // LIR_OpArrayCopy
1846 void LIR_OpArrayCopy::print_instr(outputStream* out) const {
1847 src()->print(out); out->print(" ");
1848 src_pos()->print(out); out->print(" ");
1849 dst()->print(out); out->print(" ");
1850 dst_pos()->print(out); out->print(" ");
1851 length()->print(out); out->print(" ");
1852 tmp()->print(out); out->print(" ");
1853 }
1854
1855 // LIR_OpUpdateCRC32
1856 void LIR_OpUpdateCRC32::print_instr(outputStream* out) const {
1857 crc()->print(out); out->print(" ");
1858 val()->print(out); out->print(" ");
1859 result_opr()->print(out); out->print(" ");
1860 }
1861
1862 // LIR_OpCompareAndSwap
1863 void LIR_OpCompareAndSwap::print_instr(outputStream* out) const {
1864 addr()->print(out); out->print(" ");
1865 cmp_value()->print(out); out->print(" ");
1866 new_value()->print(out); out->print(" ");
1867 tmp1()->print(out); out->print(" ");
1868 tmp2()->print(out); out->print(" ");
1869
1870 }
1871
1872 // LIR_Op0
1873 void LIR_Op0::print_instr(outputStream* out) const {
1874 result_opr()->print(out);
1875 }
1876
1877 // LIR_Op1
1878 const char * LIR_Op1::name() const {
1879 if (code() == lir_move) {
1880 switch (move_kind()) {
1881 case lir_move_normal:
1882 return "move";
1883 case lir_move_unaligned:
1884 return "unaligned move";
1885 case lir_move_volatile:
1886 return "volatile_move";
1887 case lir_move_wide:
1888 return "wide_move";
1889 default:
1890 ShouldNotReachHere();
1891 return "illegal_op";
1892 }
1893 } else {
1894 return LIR_Op::name();
1895 }
1896 }
1897
1898
1899 void LIR_Op1::print_instr(outputStream* out) const {
1900 _opr->print(out); out->print(" ");
1901 result_opr()->print(out); out->print(" ");
1902 print_patch_code(out, patch_code());
1903 }
1904
1905
1906 // LIR_Op1
1907 void LIR_OpRTCall::print_instr(outputStream* out) const {
1908 intx a = (intx)addr();
1909 out->print("%s", Runtime1::name_for_address(addr()));
1910 out->print(" ");
1911 tmp()->print(out);
1912 }
1913
1914 void LIR_Op1::print_patch_code(outputStream* out, LIR_PatchCode code) {
1915 switch(code) {
1916 case lir_patch_none: break;
1917 case lir_patch_low: out->print("[patch_low]"); break;
1918 case lir_patch_high: out->print("[patch_high]"); break;
1919 case lir_patch_normal: out->print("[patch_normal]"); break;
1920 default: ShouldNotReachHere();
1921 }
1922 }
1923
1924 // LIR_OpBranch
1925 void LIR_OpBranch::print_instr(outputStream* out) const {
1926 print_condition(out, cond()); out->print(" ");
1927 #ifdef RISCV
1928 in_opr1()->print(out); out->print(" ");
1929 in_opr2()->print(out); out->print(" ");
1930 #endif
1931 if (block() != NULL) {
1932 out->print("[B%d] ", block()->block_id());
1933 } else if (stub() != NULL) {
1934 out->print("[");
1935 stub()->print_name(out);
1936 out->print(": " INTPTR_FORMAT "]", p2i(stub()));
1937 if (stub()->info() != NULL) out->print(" [bci:%d]", stub()->info()->stack()->bci());
1938 } else {
1939 out->print("[label:" INTPTR_FORMAT "] ", p2i(label()));
1940 }
1941 if (ublock() != NULL) {
1942 out->print("unordered: [B%d] ", ublock()->block_id());
1943 }
1944 }
1945
1946 void LIR_Op::print_condition(outputStream* out, LIR_Condition cond) {
1947 switch(cond) {
1948 case lir_cond_equal: out->print("[EQ]"); break;
1949 case lir_cond_notEqual: out->print("[NE]"); break;
1950 case lir_cond_less: out->print("[LT]"); break;
1951 case lir_cond_lessEqual: out->print("[LE]"); break;
1952 case lir_cond_greaterEqual: out->print("[GE]"); break;
1953 case lir_cond_greater: out->print("[GT]"); break;
1954 case lir_cond_belowEqual: out->print("[BE]"); break;
1955 case lir_cond_aboveEqual: out->print("[AE]"); break;
1956 case lir_cond_always: out->print("[AL]"); break;
1957 default: out->print("[%d]",cond); break;
1958 }
1959 }
1960
1961 // LIR_OpConvert
1962 void LIR_OpConvert::print_instr(outputStream* out) const {
1963 print_bytecode(out, bytecode());
1964 in_opr()->print(out); out->print(" ");
1965 result_opr()->print(out); out->print(" ");
1966 #ifdef PPC32
1967 if(tmp1()->is_valid()) {
1968 tmp1()->print(out); out->print(" ");
1969 tmp2()->print(out); out->print(" ");
1970 }
1971 #endif
1972 }
1973
1974 void LIR_OpConvert::print_bytecode(outputStream* out, Bytecodes::Code code) {
1975 switch(code) {
1976 case Bytecodes::_d2f: out->print("[d2f] "); break;
1977 case Bytecodes::_d2i: out->print("[d2i] "); break;
1978 case Bytecodes::_d2l: out->print("[d2l] "); break;
1979 case Bytecodes::_f2d: out->print("[f2d] "); break;
1980 case Bytecodes::_f2i: out->print("[f2i] "); break;
1981 case Bytecodes::_f2l: out->print("[f2l] "); break;
1982 case Bytecodes::_i2b: out->print("[i2b] "); break;
1983 case Bytecodes::_i2c: out->print("[i2c] "); break;
1984 case Bytecodes::_i2d: out->print("[i2d] "); break;
1985 case Bytecodes::_i2f: out->print("[i2f] "); break;
1986 case Bytecodes::_i2l: out->print("[i2l] "); break;
1987 case Bytecodes::_i2s: out->print("[i2s] "); break;
1988 case Bytecodes::_l2i: out->print("[l2i] "); break;
1989 case Bytecodes::_l2f: out->print("[l2f] "); break;
1990 case Bytecodes::_l2d: out->print("[l2d] "); break;
1991 default:
1992 out->print("[?%d]",code);
1993 break;
1994 }
1995 }
1996
1997 void LIR_OpAllocObj::print_instr(outputStream* out) const {
1998 klass()->print(out); out->print(" ");
1999 obj()->print(out); out->print(" ");
2000 tmp1()->print(out); out->print(" ");
2001 tmp2()->print(out); out->print(" ");
2002 tmp3()->print(out); out->print(" ");
2003 tmp4()->print(out); out->print(" ");
2004 out->print("[hdr:%d]", header_size()); out->print(" ");
2005 out->print("[obj:%d]", object_size()); out->print(" ");
2006 out->print("[lbl:" INTPTR_FORMAT "]", p2i(stub()->entry()));
2007 }
2008
2009 void LIR_OpRoundFP::print_instr(outputStream* out) const {
2010 _opr->print(out); out->print(" ");
2011 tmp()->print(out); out->print(" ");
2012 result_opr()->print(out); out->print(" ");
2013 }
2014
2015 // LIR_Op2
2016 void LIR_Op2::print_instr(outputStream* out) const {
2017 #ifdef RISCV
2018 if (code() == lir_cmp || code() == lir_branch || code() == lir_cond_float_branch) {
2019 #else
2020 if (code() == lir_cmove || code() == lir_cmp) {
2021 #endif
2022 print_condition(out, condition()); out->print(" ");
2023 }
2024 in_opr1()->print(out); out->print(" ");
2025 in_opr2()->print(out); out->print(" ");
2026 if (tmp1_opr()->is_valid()) { tmp1_opr()->print(out); out->print(" "); }
2027 if (tmp2_opr()->is_valid()) { tmp2_opr()->print(out); out->print(" "); }
2028 if (tmp3_opr()->is_valid()) { tmp3_opr()->print(out); out->print(" "); }
2029 if (tmp4_opr()->is_valid()) { tmp4_opr()->print(out); out->print(" "); }
2030 if (tmp5_opr()->is_valid()) { tmp5_opr()->print(out); out->print(" "); }
2031 result_opr()->print(out);
2032 }
2033
2034 void LIR_OpAllocArray::print_instr(outputStream* out) const {
2035 klass()->print(out); out->print(" ");
2036 len()->print(out); out->print(" ");
2037 obj()->print(out); out->print(" ");
2038 tmp1()->print(out); out->print(" ");
2039 tmp2()->print(out); out->print(" ");
2040 tmp3()->print(out); out->print(" ");
2041 tmp4()->print(out); out->print(" ");
2042 out->print("[type:0x%x]", type()); out->print(" ");
2043 out->print("[label:" INTPTR_FORMAT "]", p2i(stub()->entry()));
2044 }
2045
2046
2047 void LIR_OpTypeCheck::print_instr(outputStream* out) const {
2048 object()->print(out); out->print(" ");
2049 if (code() == lir_store_check) {
2050 array()->print(out); out->print(" ");
2051 }
2052 if (code() != lir_store_check) {
2053 klass()->print_name_on(out); out->print(" ");
2054 if (fast_check()) out->print("fast_check ");
2055 }
2056 tmp1()->print(out); out->print(" ");
2057 tmp2()->print(out); out->print(" ");
2058 tmp3()->print(out); out->print(" ");
2059 result_opr()->print(out); out->print(" ");
2060 if (info_for_exception() != NULL) out->print(" [bci:%d]", info_for_exception()->stack()->bci());
2061 }
2062
2063
2064 // LIR_Op3
2065 void LIR_Op3::print_instr(outputStream* out) const {
2066 in_opr1()->print(out); out->print(" ");
2067 in_opr2()->print(out); out->print(" ");
2068 in_opr3()->print(out); out->print(" ");
2069 result_opr()->print(out);
2070 }
2071
2072 #ifdef RISCV
2073 // LIR_Op4
2074 void LIR_Op4::print_instr(outputStream* out) const {
2075 print_condition(out, condition()); out->print(" ");
2076 in_opr1()->print(out); out->print(" ");
2077 in_opr2()->print(out); out->print(" ");
2078 in_opr3()->print(out); out->print(" ");
2079 in_opr4()->print(out); out->print(" ");
2080 result_opr()->print(out);
2081 }
2082 #endif
2083
2084 void LIR_OpLock::print_instr(outputStream* out) const {
2085 hdr_opr()->print(out); out->print(" ");
2086 obj_opr()->print(out); out->print(" ");
2087 lock_opr()->print(out); out->print(" ");
2088 if (_scratch->is_valid()) {
2089 _scratch->print(out); out->print(" ");
2090 }
2091 out->print("[lbl:" INTPTR_FORMAT "]", p2i(stub()->entry()));
2092 }
2093
2094 void LIR_OpLoadKlass::print_instr(outputStream* out) const {
2095 obj()->print(out); out->print(" ");
2096 result_opr()->print(out); out->print(" ");
2097 }
2098
2099 #ifdef ASSERT
2100 void LIR_OpAssert::print_instr(outputStream* out) const {
2101 print_condition(out, condition()); out->print(" ");
2102 in_opr1()->print(out); out->print(" ");
2103 in_opr2()->print(out); out->print(", \"");
2104 out->print("%s", msg()); out->print("\"");
2105 }
2106 #endif
2107
2108
2109 void LIR_OpDelay::print_instr(outputStream* out) const {
2110 _op->print_on(out);
2111 }
2112
2113
2114 // LIR_OpProfileCall
2115 void LIR_OpProfileCall::print_instr(outputStream* out) const {
2116 profiled_method()->name()->print_symbol_on(out);
2117 out->print(".");
2118 profiled_method()->holder()->name()->print_symbol_on(out);
2119 out->print(" @ %d ", profiled_bci());
2120 mdo()->print(out); out->print(" ");
2121 recv()->print(out); out->print(" ");
2122 tmp1()->print(out); out->print(" ");
2123 }
2124
2125 // LIR_OpProfileType
2126 void LIR_OpProfileType::print_instr(outputStream* out) const {
2127 out->print("exact = ");
2128 if (exact_klass() == NULL) {
2129 out->print("unknown");
2130 } else {
2131 exact_klass()->print_name_on(out);
2132 }
2133 out->print(" current = "); ciTypeEntries::print_ciklass(out, current_klass());
2134 out->print(" ");
2135 mdp()->print(out); out->print(" ");
2136 obj()->print(out); out->print(" ");
2137 tmp()->print(out); out->print(" ");
2138 }
2139
2140 #endif // PRODUCT
2141
2142 // Implementation of LIR_InsertionBuffer
2143
2144 void LIR_InsertionBuffer::append(int index, LIR_Op* op) {
2145 assert(_index_and_count.length() % 2 == 0, "must have a count for each index");
2146
2147 int i = number_of_insertion_points() - 1;
2148 if (i < 0 || index_at(i) < index) {
2149 append_new(index, 1);
2150 } else {
2151 assert(index_at(i) == index, "can append LIR_Ops in ascending order only");
2152 assert(count_at(i) > 0, "check");
2153 set_count_at(i, count_at(i) + 1);
2154 }
2155 _ops.push(op);
2156
2157 DEBUG_ONLY(verify());
2158 }
2159
2160 #ifdef ASSERT
2161 void LIR_InsertionBuffer::verify() {
2162 int sum = 0;
2163 int prev_idx = -1;
2164
2165 for (int i = 0; i < number_of_insertion_points(); i++) {
2166 assert(prev_idx < index_at(i), "index must be ordered ascending");
2167 sum += count_at(i);
2168 }
2169 assert(sum == number_of_ops(), "wrong total sum");
2170 }
2171 #endif