1 /*
2 * Copyright (c) 2000, 2022, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "c1/c1_CodeStubs.hpp"
27 #include "c1/c1_InstructionPrinter.hpp"
28 #include "c1/c1_LIR.hpp"
29 #include "c1/c1_LIRAssembler.hpp"
30 #include "c1/c1_ValueStack.hpp"
31 #include "ci/ciInstance.hpp"
32 #include "runtime/safepointMechanism.inline.hpp"
33 #include "runtime/sharedRuntime.hpp"
34 #include "runtime/vm_version.hpp"
35
36 Register LIR_OprDesc::as_register() const {
37 return FrameMap::cpu_rnr2reg(cpu_regnr());
38 }
39
40 Register LIR_OprDesc::as_register_lo() const {
41 return FrameMap::cpu_rnr2reg(cpu_regnrLo());
42 }
43
44 Register LIR_OprDesc::as_register_hi() const {
45 return FrameMap::cpu_rnr2reg(cpu_regnrHi());
46 }
47
48 LIR_Opr LIR_OprFact::illegalOpr = LIR_OprFact::illegal();
49
50 LIR_Opr LIR_OprFact::value_type(ValueType* type) {
51 ValueTag tag = type->tag();
52 switch (tag) {
53 case metaDataTag : {
54 ClassConstant* c = type->as_ClassConstant();
55 if (c != NULL && !c->value()->is_loaded()) {
56 return LIR_OprFact::metadataConst(NULL);
57 } else if (c != NULL) {
58 return LIR_OprFact::metadataConst(c->value()->constant_encoding());
59 } else {
60 MethodConstant* m = type->as_MethodConstant();
61 assert (m != NULL, "not a class or a method?");
62 return LIR_OprFact::metadataConst(m->value()->constant_encoding());
63 }
64 }
65 case objectTag : {
66 return LIR_OprFact::oopConst(type->as_ObjectType()->encoding());
67 }
68 case addressTag: return LIR_OprFact::addressConst(type->as_AddressConstant()->value());
69 case intTag : return LIR_OprFact::intConst(type->as_IntConstant()->value());
70 case floatTag : return LIR_OprFact::floatConst(type->as_FloatConstant()->value());
71 case longTag : return LIR_OprFact::longConst(type->as_LongConstant()->value());
72 case doubleTag : return LIR_OprFact::doubleConst(type->as_DoubleConstant()->value());
73 default: ShouldNotReachHere(); return LIR_OprFact::intConst(-1);
74 }
75 }
76
77
78 //---------------------------------------------------
79
80
81 LIR_Address::Scale LIR_Address::scale(BasicType type) {
82 int elem_size = type2aelembytes(type);
83 switch (elem_size) {
84 case 1: return LIR_Address::times_1;
85 case 2: return LIR_Address::times_2;
86 case 4: return LIR_Address::times_4;
87 case 8: return LIR_Address::times_8;
88 }
89 ShouldNotReachHere();
90 return LIR_Address::times_1;
91 }
92
93 //---------------------------------------------------
94
95 char LIR_OprDesc::type_char(BasicType t) {
96 switch (t) {
97 case T_ARRAY:
98 t = T_OBJECT;
99 case T_BOOLEAN:
100 case T_CHAR:
101 case T_FLOAT:
102 case T_DOUBLE:
103 case T_BYTE:
104 case T_SHORT:
105 case T_INT:
106 case T_LONG:
107 case T_OBJECT:
108 case T_ADDRESS:
109 case T_VOID:
110 return ::type2char(t);
111 case T_METADATA:
112 return 'M';
113 case T_ILLEGAL:
114 return '?';
115
116 default:
117 ShouldNotReachHere();
118 return '?';
119 }
120 }
121
122 #ifndef PRODUCT
123 void LIR_OprDesc::validate_type() const {
124
125 #ifdef ASSERT
126 if (!is_pointer() && !is_illegal()) {
127 OprKind kindfield = kind_field(); // Factored out because of compiler bug, see 8002160
128 switch (as_BasicType(type_field())) {
129 case T_LONG:
130 assert((kindfield == cpu_register || kindfield == stack_value) &&
131 size_field() == double_size, "must match");
132 break;
133 case T_FLOAT:
134 // FP return values can be also in CPU registers on ARM and PPC32 (softfp ABI)
135 assert((kindfield == fpu_register || kindfield == stack_value
136 ARM_ONLY(|| kindfield == cpu_register)
137 PPC32_ONLY(|| kindfield == cpu_register) ) &&
138 size_field() == single_size, "must match");
139 break;
140 case T_DOUBLE:
141 // FP return values can be also in CPU registers on ARM and PPC32 (softfp ABI)
142 assert((kindfield == fpu_register || kindfield == stack_value
143 ARM_ONLY(|| kindfield == cpu_register)
144 PPC32_ONLY(|| kindfield == cpu_register) ) &&
145 size_field() == double_size, "must match");
146 break;
147 case T_BOOLEAN:
148 case T_CHAR:
149 case T_BYTE:
150 case T_SHORT:
151 case T_INT:
152 case T_ADDRESS:
153 case T_OBJECT:
154 case T_METADATA:
155 case T_ARRAY:
156 assert((kindfield == cpu_register || kindfield == stack_value) &&
157 size_field() == single_size, "must match");
158 break;
159
160 case T_ILLEGAL:
161 // XXX TKR also means unknown right now
162 // assert(is_illegal(), "must match");
163 break;
164
165 default:
166 ShouldNotReachHere();
167 }
168 }
169 #endif
170
171 }
172 #endif // PRODUCT
173
174
175 bool LIR_OprDesc::is_oop() const {
176 if (is_pointer()) {
177 return pointer()->is_oop_pointer();
178 } else {
179 OprType t= type_field();
180 assert(t != unknown_type, "not set");
181 return t == object_type;
182 }
183 }
184
185
186
187 void LIR_Op2::verify() const {
188 #ifdef ASSERT
189 switch (code()) {
190 case lir_cmove:
191 #ifdef RISCV
192 assert(false, "lir_cmove is LIR_Op4 on RISCV");
193 #endif
194 case lir_xchg:
195 break;
196
197 default:
198 assert(!result_opr()->is_register() || !result_opr()->is_oop_register(),
199 "can't produce oops from arith");
200 }
201
202 if (TwoOperandLIRForm) {
203
204 #ifdef ASSERT
205 bool threeOperandForm = false;
206 #ifdef S390
207 // There are 3 operand shifts on S390 (see LIR_Assembler::shift_op()).
208 threeOperandForm =
209 code() == lir_shl ||
210 ((code() == lir_shr || code() == lir_ushr) && (result_opr()->is_double_cpu() || in_opr1()->type() == T_OBJECT));
211 #endif
212 #endif
213
214 switch (code()) {
215 case lir_add:
216 case lir_sub:
217 case lir_mul:
218 case lir_div:
219 case lir_rem:
220 case lir_logic_and:
221 case lir_logic_or:
222 case lir_logic_xor:
223 case lir_shl:
224 case lir_shr:
225 assert(in_opr1() == result_opr() || threeOperandForm, "opr1 and result must match");
226 assert(in_opr1()->is_valid() && in_opr2()->is_valid(), "must be valid");
227 break;
228
229 // special handling for lir_ushr because of write barriers
230 case lir_ushr:
231 assert(in_opr1() == result_opr() || in_opr2()->is_constant() || threeOperandForm, "opr1 and result must match or shift count is constant");
232 assert(in_opr1()->is_valid() && in_opr2()->is_valid(), "must be valid");
233 break;
234
235 default:
236 break;
237 }
238 }
239 #endif
240 }
241
242
243 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BlockBegin* block)
244 #ifdef RISCV
245 : LIR_Op2(lir_branch, cond, LIR_OprFact::illegalOpr, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)
246 #else
247 : LIR_Op(lir_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)
248 , _cond(cond)
249 #endif
250 , _label(block->label())
251 , _block(block)
252 , _ublock(NULL)
253 , _stub(NULL) {
254 }
255
256 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, CodeStub* stub) :
257 #ifdef RISCV
258 LIR_Op2(lir_branch, cond, LIR_OprFact::illegalOpr, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)
259 #else
260 LIR_Op(lir_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)
261 , _cond(cond)
262 #endif
263 , _label(stub->entry())
264 , _block(NULL)
265 , _ublock(NULL)
266 , _stub(stub) {
267 }
268
269 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BlockBegin* block, BlockBegin* ublock)
270 #ifdef RISCV
271 : LIR_Op2(lir_cond_float_branch, cond, LIR_OprFact::illegalOpr, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)
272 #else
273 : LIR_Op(lir_cond_float_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)
274 , _cond(cond)
275 #endif
276 , _label(block->label())
277 , _block(block)
278 , _ublock(ublock)
279 , _stub(NULL)
280 {
281 }
282
283 void LIR_OpBranch::change_block(BlockBegin* b) {
284 assert(_block != NULL, "must have old block");
285 assert(_block->label() == label(), "must be equal");
286
287 _block = b;
288 _label = b->label();
289 }
290
291 void LIR_OpBranch::change_ublock(BlockBegin* b) {
292 assert(_ublock != NULL, "must have old block");
293 _ublock = b;
294 }
295
296 void LIR_OpBranch::negate_cond() {
297 switch (cond()) {
298 case lir_cond_equal: set_cond(lir_cond_notEqual); break;
299 case lir_cond_notEqual: set_cond(lir_cond_equal); break;
300 case lir_cond_less: set_cond(lir_cond_greaterEqual); break;
301 case lir_cond_lessEqual: set_cond(lir_cond_greater); break;
302 case lir_cond_greaterEqual: set_cond(lir_cond_less); break;
303 case lir_cond_greater: set_cond(lir_cond_lessEqual); break;
304 default: ShouldNotReachHere();
305 }
306 }
307
308
309 LIR_OpTypeCheck::LIR_OpTypeCheck(LIR_Code code, LIR_Opr result, LIR_Opr object, ciKlass* klass,
310 LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3,
311 bool fast_check, CodeEmitInfo* info_for_exception, CodeEmitInfo* info_for_patch,
312 CodeStub* stub)
313
314 : LIR_Op(code, result, NULL)
315 , _object(object)
316 , _array(LIR_OprFact::illegalOpr)
317 , _klass(klass)
318 , _tmp1(tmp1)
319 , _tmp2(tmp2)
320 , _tmp3(tmp3)
321 , _fast_check(fast_check)
322 , _info_for_patch(info_for_patch)
323 , _info_for_exception(info_for_exception)
324 , _stub(stub)
325 , _profiled_method(NULL)
326 , _profiled_bci(-1)
327 , _should_profile(false)
328 {
329 if (code == lir_checkcast) {
330 assert(info_for_exception != NULL, "checkcast throws exceptions");
331 } else if (code == lir_instanceof) {
332 assert(info_for_exception == NULL, "instanceof throws no exceptions");
333 } else {
334 ShouldNotReachHere();
335 }
336 }
337
338
339
340 LIR_OpTypeCheck::LIR_OpTypeCheck(LIR_Code code, LIR_Opr object, LIR_Opr array, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, CodeEmitInfo* info_for_exception)
341 : LIR_Op(code, LIR_OprFact::illegalOpr, NULL)
342 , _object(object)
343 , _array(array)
344 , _klass(NULL)
345 , _tmp1(tmp1)
346 , _tmp2(tmp2)
347 , _tmp3(tmp3)
348 , _fast_check(false)
349 , _info_for_patch(NULL)
350 , _info_for_exception(info_for_exception)
351 , _stub(NULL)
352 , _profiled_method(NULL)
353 , _profiled_bci(-1)
354 , _should_profile(false)
355 {
356 if (code == lir_store_check) {
357 _stub = new ArrayStoreExceptionStub(object, info_for_exception);
358 assert(info_for_exception != NULL, "store_check throws exceptions");
359 } else {
360 ShouldNotReachHere();
361 }
362 }
363
364
365 LIR_OpArrayCopy::LIR_OpArrayCopy(LIR_Opr src, LIR_Opr src_pos, LIR_Opr dst, LIR_Opr dst_pos, LIR_Opr length,
366 LIR_Opr tmp, ciArrayKlass* expected_type, int flags, CodeEmitInfo* info)
367 : LIR_Op(lir_arraycopy, LIR_OprFact::illegalOpr, info)
368 , _src(src)
369 , _src_pos(src_pos)
370 , _dst(dst)
371 , _dst_pos(dst_pos)
372 , _length(length)
373 , _tmp(tmp)
374 , _expected_type(expected_type)
375 , _flags(flags) {
376 _stub = new ArrayCopyStub(this);
377 }
378
379 LIR_OpUpdateCRC32::LIR_OpUpdateCRC32(LIR_Opr crc, LIR_Opr val, LIR_Opr res)
380 : LIR_Op(lir_updatecrc32, res, NULL)
381 , _crc(crc)
382 , _val(val) {
383 }
384
385 //-------------------verify--------------------------
386
387 void LIR_Op1::verify() const {
388 switch(code()) {
389 case lir_move:
390 assert(in_opr()->is_valid() && result_opr()->is_valid(), "must be");
391 break;
392 case lir_null_check:
393 assert(in_opr()->is_register(), "must be");
394 break;
395 case lir_return:
396 assert(in_opr()->is_register() || in_opr()->is_illegal(), "must be");
397 break;
398 default:
399 break;
400 }
401 }
402
403 void LIR_OpRTCall::verify() const {
404 assert(strcmp(Runtime1::name_for_address(addr()), "<unknown function>") != 0, "unknown function");
405 }
406
407 //-------------------visits--------------------------
408
409 // complete rework of LIR instruction visitor.
410 // The virtual call for each instruction type is replaced by a big
411 // switch that adds the operands for each instruction
412
413 void LIR_OpVisitState::visit(LIR_Op* op) {
414 // copy information from the LIR_Op
415 reset();
416 set_op(op);
417
418 switch (op->code()) {
419
420 // LIR_Op0
421 case lir_backwardbranch_target: // result and info always invalid
422 case lir_fpop_raw: // result and info always invalid
423 case lir_breakpoint: // result and info always invalid
424 case lir_membar: // result and info always invalid
425 case lir_membar_acquire: // result and info always invalid
426 case lir_membar_release: // result and info always invalid
427 case lir_membar_loadload: // result and info always invalid
428 case lir_membar_storestore: // result and info always invalid
429 case lir_membar_loadstore: // result and info always invalid
430 case lir_membar_storeload: // result and info always invalid
431 case lir_on_spin_wait:
432 {
433 assert(op->as_Op0() != NULL, "must be");
434 assert(op->_info == NULL, "info not used by this instruction");
435 assert(op->_result->is_illegal(), "not used");
436 break;
437 }
438
439 case lir_nop: // may have info, result always invalid
440 case lir_std_entry: // may have result, info always invalid
441 case lir_osr_entry: // may have result, info always invalid
442 case lir_get_thread: // may have result, info always invalid
443 {
444 assert(op->as_Op0() != NULL, "must be");
445 if (op->_info != NULL) do_info(op->_info);
446 if (op->_result->is_valid()) do_output(op->_result);
447 break;
448 }
449
450
451 // LIR_OpLabel
452 case lir_label: // result and info always invalid
453 {
454 assert(op->as_OpLabel() != NULL, "must be");
455 assert(op->_info == NULL, "info not used by this instruction");
456 assert(op->_result->is_illegal(), "not used");
457 break;
458 }
459
460
461 // LIR_Op1
462 case lir_fxch: // input always valid, result and info always invalid
463 case lir_fld: // input always valid, result and info always invalid
464 case lir_push: // input always valid, result and info always invalid
465 case lir_pop: // input always valid, result and info always invalid
466 case lir_leal: // input and result always valid, info always invalid
467 case lir_monaddr: // input and result always valid, info always invalid
468 case lir_null_check: // input and info always valid, result always invalid
469 case lir_move: // input and result always valid, may have info
470 {
471 assert(op->as_Op1() != NULL, "must be");
472 LIR_Op1* op1 = (LIR_Op1*)op;
473
474 if (op1->_info) do_info(op1->_info);
475 if (op1->_opr->is_valid()) do_input(op1->_opr);
476 if (op1->_result->is_valid()) do_output(op1->_result);
477
478 break;
479 }
480
481 case lir_return:
482 {
483 assert(op->as_OpReturn() != NULL, "must be");
484 LIR_OpReturn* op_ret = (LIR_OpReturn*)op;
485
486 if (op_ret->_info) do_info(op_ret->_info);
487 if (op_ret->_opr->is_valid()) do_input(op_ret->_opr);
488 if (op_ret->_result->is_valid()) do_output(op_ret->_result);
489 if (op_ret->stub() != NULL) do_stub(op_ret->stub());
490
491 break;
492 }
493
494 case lir_safepoint:
495 {
496 assert(op->as_Op1() != NULL, "must be");
497 LIR_Op1* op1 = (LIR_Op1*)op;
498
499 assert(op1->_info != NULL, ""); do_info(op1->_info);
500 if (op1->_opr->is_valid()) do_temp(op1->_opr); // safepoints on SPARC need temporary register
501 assert(op1->_result->is_illegal(), "safepoint does not produce value");
502
503 break;
504 }
505
506 // LIR_OpConvert;
507 case lir_convert: // input and result always valid, info always invalid
508 {
509 assert(op->as_OpConvert() != NULL, "must be");
510 LIR_OpConvert* opConvert = (LIR_OpConvert*)op;
511
512 assert(opConvert->_info == NULL, "must be");
513 if (opConvert->_opr->is_valid()) do_input(opConvert->_opr);
514 if (opConvert->_result->is_valid()) do_output(opConvert->_result);
515 #ifdef PPC32
516 if (opConvert->_tmp1->is_valid()) do_temp(opConvert->_tmp1);
517 if (opConvert->_tmp2->is_valid()) do_temp(opConvert->_tmp2);
518 #endif
519 do_stub(opConvert->_stub);
520
521 break;
522 }
523
524 // LIR_OpBranch;
525 case lir_branch: // may have info, input and result register always invalid
526 case lir_cond_float_branch: // may have info, input and result register always invalid
527 {
528 assert(op->as_OpBranch() != NULL, "must be");
529 LIR_OpBranch* opBranch = (LIR_OpBranch*)op;
530
531 #ifdef RISCV
532 assert(opBranch->_tmp1->is_illegal() && opBranch->_tmp2->is_illegal() &&
533 opBranch->_tmp3->is_illegal() && opBranch->_tmp4->is_illegal() &&
534 opBranch->_tmp5->is_illegal(), "not used");
535
536 if (opBranch->_opr1->is_valid()) do_input(opBranch->_opr1);
537 if (opBranch->_opr2->is_valid()) do_input(opBranch->_opr2);
538 #endif
539
540 if (opBranch->_info != NULL) do_info(opBranch->_info);
541 assert(opBranch->_result->is_illegal(), "not used");
542 if (opBranch->_stub != NULL) opBranch->stub()->visit(this);
543
544 break;
545 }
546
547
548 // LIR_OpAllocObj
549 case lir_alloc_object:
550 {
551 assert(op->as_OpAllocObj() != NULL, "must be");
552 LIR_OpAllocObj* opAllocObj = (LIR_OpAllocObj*)op;
553
554 if (opAllocObj->_info) do_info(opAllocObj->_info);
555 if (opAllocObj->_opr->is_valid()) { do_input(opAllocObj->_opr);
556 do_temp(opAllocObj->_opr);
557 }
558 if (opAllocObj->_tmp1->is_valid()) do_temp(opAllocObj->_tmp1);
559 if (opAllocObj->_tmp2->is_valid()) do_temp(opAllocObj->_tmp2);
560 if (opAllocObj->_tmp3->is_valid()) do_temp(opAllocObj->_tmp3);
561 if (opAllocObj->_tmp4->is_valid()) do_temp(opAllocObj->_tmp4);
562 if (opAllocObj->_result->is_valid()) do_output(opAllocObj->_result);
563 do_stub(opAllocObj->_stub);
564 break;
565 }
566
567
568 // LIR_OpRoundFP;
569 case lir_roundfp: {
570 assert(op->as_OpRoundFP() != NULL, "must be");
571 LIR_OpRoundFP* opRoundFP = (LIR_OpRoundFP*)op;
572
573 assert(op->_info == NULL, "info not used by this instruction");
574 assert(opRoundFP->_tmp->is_illegal(), "not used");
575 do_input(opRoundFP->_opr);
576 do_output(opRoundFP->_result);
577
578 break;
579 }
580
581
582 // LIR_Op2
583 case lir_cmp:
584 case lir_cmp_l2i:
585 case lir_ucmp_fd2i:
586 case lir_cmp_fd2i:
587 case lir_add:
588 case lir_sub:
589 case lir_rem:
590 case lir_sqrt:
591 case lir_abs:
592 case lir_neg:
593 case lir_logic_and:
594 case lir_logic_or:
595 case lir_logic_xor:
596 case lir_shl:
597 case lir_shr:
598 case lir_ushr:
599 case lir_xadd:
600 case lir_xchg:
601 case lir_assert:
602 {
603 assert(op->as_Op2() != NULL, "must be");
604 LIR_Op2* op2 = (LIR_Op2*)op;
605 assert(op2->_tmp2->is_illegal() && op2->_tmp3->is_illegal() &&
606 op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used");
607
608 if (op2->_info) do_info(op2->_info);
609 if (op2->_opr1->is_valid()) do_input(op2->_opr1);
610 if (op2->_opr2->is_valid()) do_input(op2->_opr2);
611 if (op2->_tmp1->is_valid()) do_temp(op2->_tmp1);
612 if (op2->_result->is_valid()) do_output(op2->_result);
613 if (op->code() == lir_xchg || op->code() == lir_xadd) {
614 // on ARM and PPC, return value is loaded first so could
615 // destroy inputs. On other platforms that implement those
616 // (x86, sparc), the extra constrainsts are harmless.
617 if (op2->_opr1->is_valid()) do_temp(op2->_opr1);
618 if (op2->_opr2->is_valid()) do_temp(op2->_opr2);
619 }
620
621 break;
622 }
623
624 // special handling for cmove: right input operand must not be equal
625 // to the result operand, otherwise the backend fails
626 case lir_cmove:
627 {
628 #ifdef RISCV
629 assert(op->as_Op4() != NULL, "must be");
630 LIR_Op4* op4 = (LIR_Op4*)op;
631
632 assert(op4->_info == NULL && op4->_tmp1->is_illegal() && op4->_tmp2->is_illegal() &&
633 op4->_tmp3->is_illegal() && op4->_tmp4->is_illegal() && op4->_tmp5->is_illegal(), "not used");
634 assert(op4->_opr1->is_valid() && op4->_opr2->is_valid() && op4->_result->is_valid(), "used");
635
636 do_input(op4->_opr1);
637 do_input(op4->_opr2);
638 if (op4->_opr3->is_valid()) do_input(op4->_opr3);
639 if (op4->_opr4->is_valid()) do_input(op4->_opr4);
640 do_temp(op4->_opr2);
641 do_output(op4->_result);
642 #else
643 assert(op->as_Op2() != NULL, "must be");
644 LIR_Op2* op2 = (LIR_Op2*)op;
645
646 assert(op2->_info == NULL && op2->_tmp1->is_illegal() && op2->_tmp2->is_illegal() &&
647 op2->_tmp3->is_illegal() && op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used");
648 assert(op2->_opr1->is_valid() && op2->_opr2->is_valid() && op2->_result->is_valid(), "used");
649
650 do_input(op2->_opr1);
651 do_input(op2->_opr2);
652 do_temp(op2->_opr2);
653 do_output(op2->_result);
654 #endif
655
656 break;
657 }
658
659 // vspecial handling for strict operations: register input operands
660 // as temp to guarantee that they do not overlap with other
661 // registers
662 case lir_mul:
663 case lir_div:
664 {
665 assert(op->as_Op2() != NULL, "must be");
666 LIR_Op2* op2 = (LIR_Op2*)op;
667
668 assert(op2->_info == NULL, "not used");
669 assert(op2->_opr1->is_valid(), "used");
670 assert(op2->_opr2->is_valid(), "used");
671 assert(op2->_result->is_valid(), "used");
672 assert(op2->_tmp2->is_illegal() && op2->_tmp3->is_illegal() &&
673 op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used");
674
675 do_input(op2->_opr1); do_temp(op2->_opr1);
676 do_input(op2->_opr2); do_temp(op2->_opr2);
677 if (op2->_tmp1->is_valid()) do_temp(op2->_tmp1);
678 do_output(op2->_result);
679
680 break;
681 }
682
683 case lir_throw: {
684 assert(op->as_Op2() != NULL, "must be");
685 LIR_Op2* op2 = (LIR_Op2*)op;
686
687 if (op2->_info) do_info(op2->_info);
688 if (op2->_opr1->is_valid()) do_temp(op2->_opr1);
689 if (op2->_opr2->is_valid()) do_input(op2->_opr2); // exception object is input parameter
690 assert(op2->_result->is_illegal(), "no result");
691 assert(op2->_tmp2->is_illegal() && op2->_tmp3->is_illegal() &&
692 op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used");
693
694 break;
695 }
696
697 case lir_unwind: {
698 assert(op->as_Op1() != NULL, "must be");
699 LIR_Op1* op1 = (LIR_Op1*)op;
700
701 assert(op1->_info == NULL, "no info");
702 assert(op1->_opr->is_valid(), "exception oop"); do_input(op1->_opr);
703 assert(op1->_result->is_illegal(), "no result");
704
705 break;
706 }
707
708 // LIR_Op3
709 case lir_idiv:
710 case lir_irem: {
711 assert(op->as_Op3() != NULL, "must be");
712 LIR_Op3* op3= (LIR_Op3*)op;
713
714 if (op3->_info) do_info(op3->_info);
715 if (op3->_opr1->is_valid()) do_input(op3->_opr1);
716
717 // second operand is input and temp, so ensure that second operand
718 // and third operand get not the same register
719 if (op3->_opr2->is_valid()) do_input(op3->_opr2);
720 if (op3->_opr2->is_valid()) do_temp(op3->_opr2);
721 if (op3->_opr3->is_valid()) do_temp(op3->_opr3);
722
723 if (op3->_result->is_valid()) do_output(op3->_result);
724
725 break;
726 }
727
728 case lir_fmad:
729 case lir_fmaf: {
730 assert(op->as_Op3() != NULL, "must be");
731 LIR_Op3* op3= (LIR_Op3*)op;
732 assert(op3->_info == NULL, "no info");
733 do_input(op3->_opr1);
734 do_input(op3->_opr2);
735 do_input(op3->_opr3);
736 do_output(op3->_result);
737 break;
738 }
739
740 // LIR_OpJavaCall
741 case lir_static_call:
742 case lir_optvirtual_call:
743 case lir_icvirtual_call:
744 case lir_dynamic_call: {
745 LIR_OpJavaCall* opJavaCall = op->as_OpJavaCall();
746 assert(opJavaCall != NULL, "must be");
747
748 if (opJavaCall->_receiver->is_valid()) do_input(opJavaCall->_receiver);
749
750 // only visit register parameters
751 int n = opJavaCall->_arguments->length();
752 for (int i = opJavaCall->_receiver->is_valid() ? 1 : 0; i < n; i++) {
753 if (!opJavaCall->_arguments->at(i)->is_pointer()) {
754 do_input(*opJavaCall->_arguments->adr_at(i));
755 }
756 }
757
758 if (opJavaCall->_info) do_info(opJavaCall->_info);
759 if (FrameMap::method_handle_invoke_SP_save_opr() != LIR_OprFact::illegalOpr &&
760 opJavaCall->is_method_handle_invoke()) {
761 opJavaCall->_method_handle_invoke_SP_save_opr = FrameMap::method_handle_invoke_SP_save_opr();
762 do_temp(opJavaCall->_method_handle_invoke_SP_save_opr);
763 }
764 do_call();
765 if (opJavaCall->_result->is_valid()) do_output(opJavaCall->_result);
766
767 break;
768 }
769
770
771 // LIR_OpRTCall
772 case lir_rtcall: {
773 assert(op->as_OpRTCall() != NULL, "must be");
774 LIR_OpRTCall* opRTCall = (LIR_OpRTCall*)op;
775
776 // only visit register parameters
777 int n = opRTCall->_arguments->length();
778 for (int i = 0; i < n; i++) {
779 if (!opRTCall->_arguments->at(i)->is_pointer()) {
780 do_input(*opRTCall->_arguments->adr_at(i));
781 }
782 }
783 if (opRTCall->_info) do_info(opRTCall->_info);
784 if (opRTCall->_tmp->is_valid()) do_temp(opRTCall->_tmp);
785 do_call();
786 if (opRTCall->_result->is_valid()) do_output(opRTCall->_result);
787
788 break;
789 }
790
791
792 // LIR_OpArrayCopy
793 case lir_arraycopy: {
794 assert(op->as_OpArrayCopy() != NULL, "must be");
795 LIR_OpArrayCopy* opArrayCopy = (LIR_OpArrayCopy*)op;
796
797 assert(opArrayCopy->_result->is_illegal(), "unused");
798 assert(opArrayCopy->_src->is_valid(), "used"); do_input(opArrayCopy->_src); do_temp(opArrayCopy->_src);
799 assert(opArrayCopy->_src_pos->is_valid(), "used"); do_input(opArrayCopy->_src_pos); do_temp(opArrayCopy->_src_pos);
800 assert(opArrayCopy->_dst->is_valid(), "used"); do_input(opArrayCopy->_dst); do_temp(opArrayCopy->_dst);
801 assert(opArrayCopy->_dst_pos->is_valid(), "used"); do_input(opArrayCopy->_dst_pos); do_temp(opArrayCopy->_dst_pos);
802 assert(opArrayCopy->_length->is_valid(), "used"); do_input(opArrayCopy->_length); do_temp(opArrayCopy->_length);
803 assert(opArrayCopy->_tmp->is_valid(), "used"); do_temp(opArrayCopy->_tmp);
804 if (opArrayCopy->_info) do_info(opArrayCopy->_info);
805
806 // the implementation of arraycopy always has a call into the runtime
807 do_call();
808
809 break;
810 }
811
812
813 // LIR_OpUpdateCRC32
814 case lir_updatecrc32: {
815 assert(op->as_OpUpdateCRC32() != NULL, "must be");
816 LIR_OpUpdateCRC32* opUp = (LIR_OpUpdateCRC32*)op;
817
818 assert(opUp->_crc->is_valid(), "used"); do_input(opUp->_crc); do_temp(opUp->_crc);
819 assert(opUp->_val->is_valid(), "used"); do_input(opUp->_val); do_temp(opUp->_val);
820 assert(opUp->_result->is_valid(), "used"); do_output(opUp->_result);
821 assert(opUp->_info == NULL, "no info for LIR_OpUpdateCRC32");
822
823 break;
824 }
825
826
827 // LIR_OpLock
828 case lir_lock:
829 case lir_unlock: {
830 assert(op->as_OpLock() != NULL, "must be");
831 LIR_OpLock* opLock = (LIR_OpLock*)op;
832
833 if (opLock->_info) do_info(opLock->_info);
834
835 // TODO: check if these operands really have to be temp
836 // (or if input is sufficient). This may have influence on the oop map!
837 assert(opLock->_lock->is_valid(), "used"); do_temp(opLock->_lock);
838 assert(opLock->_hdr->is_valid(), "used"); do_temp(opLock->_hdr);
839 assert(opLock->_obj->is_valid(), "used"); do_temp(opLock->_obj);
840
841 if (opLock->_scratch->is_valid()) do_temp(opLock->_scratch);
842 assert(opLock->_result->is_illegal(), "unused");
843
844 do_stub(opLock->_stub);
845
846 break;
847 }
848
849
850 // LIR_OpDelay
851 case lir_delay_slot: {
852 assert(op->as_OpDelay() != NULL, "must be");
853 LIR_OpDelay* opDelay = (LIR_OpDelay*)op;
854
855 visit(opDelay->delay_op());
856 break;
857 }
858
859 // LIR_OpTypeCheck
860 case lir_instanceof:
861 case lir_checkcast:
862 case lir_store_check: {
863 assert(op->as_OpTypeCheck() != NULL, "must be");
864 LIR_OpTypeCheck* opTypeCheck = (LIR_OpTypeCheck*)op;
865
866 if (opTypeCheck->_info_for_exception) do_info(opTypeCheck->_info_for_exception);
867 if (opTypeCheck->_info_for_patch) do_info(opTypeCheck->_info_for_patch);
868 if (opTypeCheck->_object->is_valid()) do_input(opTypeCheck->_object);
869 if (op->code() == lir_store_check && opTypeCheck->_object->is_valid()) {
870 do_temp(opTypeCheck->_object);
871 }
872 if (opTypeCheck->_array->is_valid()) do_input(opTypeCheck->_array);
873 if (opTypeCheck->_tmp1->is_valid()) do_temp(opTypeCheck->_tmp1);
874 if (opTypeCheck->_tmp2->is_valid()) do_temp(opTypeCheck->_tmp2);
875 if (opTypeCheck->_tmp3->is_valid()) do_temp(opTypeCheck->_tmp3);
876 if (opTypeCheck->_result->is_valid()) do_output(opTypeCheck->_result);
877 do_stub(opTypeCheck->_stub);
878 break;
879 }
880
881 // LIR_OpCompareAndSwap
882 case lir_cas_long:
883 case lir_cas_obj:
884 case lir_cas_int: {
885 assert(op->as_OpCompareAndSwap() != NULL, "must be");
886 LIR_OpCompareAndSwap* opCompareAndSwap = (LIR_OpCompareAndSwap*)op;
887
888 assert(opCompareAndSwap->_addr->is_valid(), "used");
889 assert(opCompareAndSwap->_cmp_value->is_valid(), "used");
890 assert(opCompareAndSwap->_new_value->is_valid(), "used");
891 if (opCompareAndSwap->_info) do_info(opCompareAndSwap->_info);
892 do_input(opCompareAndSwap->_addr);
893 do_temp(opCompareAndSwap->_addr);
894 do_input(opCompareAndSwap->_cmp_value);
895 do_temp(opCompareAndSwap->_cmp_value);
896 do_input(opCompareAndSwap->_new_value);
897 do_temp(opCompareAndSwap->_new_value);
898 if (opCompareAndSwap->_tmp1->is_valid()) do_temp(opCompareAndSwap->_tmp1);
899 if (opCompareAndSwap->_tmp2->is_valid()) do_temp(opCompareAndSwap->_tmp2);
900 if (opCompareAndSwap->_result->is_valid()) do_output(opCompareAndSwap->_result);
901
902 break;
903 }
904
905
906 // LIR_OpAllocArray;
907 case lir_alloc_array: {
908 assert(op->as_OpAllocArray() != NULL, "must be");
909 LIR_OpAllocArray* opAllocArray = (LIR_OpAllocArray*)op;
910
911 if (opAllocArray->_info) do_info(opAllocArray->_info);
912 if (opAllocArray->_klass->is_valid()) do_input(opAllocArray->_klass); do_temp(opAllocArray->_klass);
913 if (opAllocArray->_len->is_valid()) do_input(opAllocArray->_len); do_temp(opAllocArray->_len);
914 if (opAllocArray->_tmp1->is_valid()) do_temp(opAllocArray->_tmp1);
915 if (opAllocArray->_tmp2->is_valid()) do_temp(opAllocArray->_tmp2);
916 if (opAllocArray->_tmp3->is_valid()) do_temp(opAllocArray->_tmp3);
917 if (opAllocArray->_tmp4->is_valid()) do_temp(opAllocArray->_tmp4);
918 if (opAllocArray->_result->is_valid()) do_output(opAllocArray->_result);
919 do_stub(opAllocArray->_stub);
920 break;
921 }
922
923 // LIR_OpLoadKlass
924 case lir_load_klass:
925 {
926 LIR_OpLoadKlass* opLoadKlass = op->as_OpLoadKlass();
927 assert(opLoadKlass != NULL, "must be");
928
929 do_input(opLoadKlass->_obj);
930 do_output(opLoadKlass->_result);
931 if (opLoadKlass->_stub) do_stub(opLoadKlass->_stub);
932 if (opLoadKlass->_info) do_info(opLoadKlass->_info);
933 break;
934 }
935
936
937 // LIR_OpProfileCall:
938 case lir_profile_call: {
939 assert(op->as_OpProfileCall() != NULL, "must be");
940 LIR_OpProfileCall* opProfileCall = (LIR_OpProfileCall*)op;
941
942 if (opProfileCall->_recv->is_valid()) do_temp(opProfileCall->_recv);
943 assert(opProfileCall->_mdo->is_valid(), "used"); do_temp(opProfileCall->_mdo);
944 assert(opProfileCall->_tmp1->is_valid(), "used"); do_temp(opProfileCall->_tmp1);
945 break;
946 }
947
948 // LIR_OpProfileType:
949 case lir_profile_type: {
950 assert(op->as_OpProfileType() != NULL, "must be");
951 LIR_OpProfileType* opProfileType = (LIR_OpProfileType*)op;
952
953 do_input(opProfileType->_mdp); do_temp(opProfileType->_mdp);
954 do_input(opProfileType->_obj);
955 do_temp(opProfileType->_tmp);
956 break;
957 }
958 default:
959 op->visit(this);
960 }
961 }
962
963 void LIR_Op::visit(LIR_OpVisitState* state) {
964 ShouldNotReachHere();
965 }
966
967 void LIR_OpVisitState::do_stub(CodeStub* stub) {
968 if (stub != NULL) {
969 stub->visit(this);
970 }
971 }
972
973 XHandlers* LIR_OpVisitState::all_xhandler() {
974 XHandlers* result = NULL;
975
976 int i;
977 for (i = 0; i < info_count(); i++) {
978 if (info_at(i)->exception_handlers() != NULL) {
979 result = info_at(i)->exception_handlers();
980 break;
981 }
982 }
983
984 #ifdef ASSERT
985 for (i = 0; i < info_count(); i++) {
986 assert(info_at(i)->exception_handlers() == NULL ||
987 info_at(i)->exception_handlers() == result,
988 "only one xhandler list allowed per LIR-operation");
989 }
990 #endif
991
992 if (result != NULL) {
993 return result;
994 } else {
995 return new XHandlers();
996 }
997
998 return result;
999 }
1000
1001
1002 #ifdef ASSERT
1003 bool LIR_OpVisitState::no_operands(LIR_Op* op) {
1004 visit(op);
1005
1006 return opr_count(inputMode) == 0 &&
1007 opr_count(outputMode) == 0 &&
1008 opr_count(tempMode) == 0 &&
1009 info_count() == 0 &&
1010 !has_call() &&
1011 !has_slow_case();
1012 }
1013 #endif
1014
1015 // LIR_OpReturn
1016 LIR_OpReturn::LIR_OpReturn(LIR_Opr opr) :
1017 LIR_Op1(lir_return, opr, (CodeEmitInfo*)NULL /* info */),
1018 _stub(NULL) {
1019 if (VM_Version::supports_stack_watermark_barrier()) {
1020 _stub = new C1SafepointPollStub();
1021 }
1022 }
1023
1024 //---------------------------------------------------
1025
1026
1027 void LIR_OpJavaCall::emit_code(LIR_Assembler* masm) {
1028 masm->emit_call(this);
1029 }
1030
1031 void LIR_OpRTCall::emit_code(LIR_Assembler* masm) {
1032 masm->emit_rtcall(this);
1033 }
1034
1035 void LIR_OpLabel::emit_code(LIR_Assembler* masm) {
1036 masm->emit_opLabel(this);
1037 }
1038
1039 void LIR_OpArrayCopy::emit_code(LIR_Assembler* masm) {
1040 masm->emit_arraycopy(this);
1041 masm->append_code_stub(stub());
1042 }
1043
1044 void LIR_OpUpdateCRC32::emit_code(LIR_Assembler* masm) {
1045 masm->emit_updatecrc32(this);
1046 }
1047
1048 void LIR_Op0::emit_code(LIR_Assembler* masm) {
1049 masm->emit_op0(this);
1050 }
1051
1052 void LIR_Op1::emit_code(LIR_Assembler* masm) {
1053 masm->emit_op1(this);
1054 }
1055
1056 void LIR_OpAllocObj::emit_code(LIR_Assembler* masm) {
1057 masm->emit_alloc_obj(this);
1058 masm->append_code_stub(stub());
1059 }
1060
1061 void LIR_OpBranch::emit_code(LIR_Assembler* masm) {
1062 masm->emit_opBranch(this);
1063 if (stub()) {
1064 masm->append_code_stub(stub());
1065 }
1066 }
1067
1068 void LIR_OpConvert::emit_code(LIR_Assembler* masm) {
1069 masm->emit_opConvert(this);
1070 if (stub() != NULL) {
1071 masm->append_code_stub(stub());
1072 }
1073 }
1074
1075 void LIR_Op2::emit_code(LIR_Assembler* masm) {
1076 masm->emit_op2(this);
1077 }
1078
1079 void LIR_OpAllocArray::emit_code(LIR_Assembler* masm) {
1080 masm->emit_alloc_array(this);
1081 masm->append_code_stub(stub());
1082 }
1083
1084 void LIR_OpTypeCheck::emit_code(LIR_Assembler* masm) {
1085 masm->emit_opTypeCheck(this);
1086 if (stub()) {
1087 masm->append_code_stub(stub());
1088 }
1089 }
1090
1091 void LIR_OpCompareAndSwap::emit_code(LIR_Assembler* masm) {
1092 masm->emit_compare_and_swap(this);
1093 }
1094
1095 void LIR_Op3::emit_code(LIR_Assembler* masm) {
1096 masm->emit_op3(this);
1097 }
1098
1099 #ifdef RISCV
1100 void LIR_Op4::emit_code(LIR_Assembler* masm) {
1101 masm->emit_op4(this);
1102 }
1103 #endif
1104
1105 void LIR_OpLock::emit_code(LIR_Assembler* masm) {
1106 masm->emit_lock(this);
1107 if (stub()) {
1108 masm->append_code_stub(stub());
1109 }
1110 }
1111
1112 void LIR_OpLoadKlass::emit_code(LIR_Assembler* masm) {
1113 masm->emit_load_klass(this);
1114 if (stub()) {
1115 masm->append_code_stub(stub());
1116 }
1117 }
1118
1119 #ifdef ASSERT
1120 void LIR_OpAssert::emit_code(LIR_Assembler* masm) {
1121 masm->emit_assert(this);
1122 }
1123 #endif
1124
1125 void LIR_OpDelay::emit_code(LIR_Assembler* masm) {
1126 masm->emit_delay(this);
1127 }
1128
1129 void LIR_OpProfileCall::emit_code(LIR_Assembler* masm) {
1130 masm->emit_profile_call(this);
1131 }
1132
1133 void LIR_OpProfileType::emit_code(LIR_Assembler* masm) {
1134 masm->emit_profile_type(this);
1135 }
1136
1137 // LIR_List
1138 LIR_List::LIR_List(Compilation* compilation, BlockBegin* block)
1139 : _operations(8)
1140 , _compilation(compilation)
1141 #ifndef PRODUCT
1142 , _block(block)
1143 #endif
1144 #ifdef ASSERT
1145 , _file(NULL)
1146 , _line(0)
1147 #endif
1148 #ifdef RISCV
1149 , _cmp_opr1(LIR_OprFact::illegalOpr)
1150 , _cmp_opr2(LIR_OprFact::illegalOpr)
1151 #endif
1152 { }
1153
1154
1155 #ifdef ASSERT
1156 void LIR_List::set_file_and_line(const char * file, int line) {
1157 const char * f = strrchr(file, '/');
1158 if (f == NULL) f = strrchr(file, '\\');
1159 if (f == NULL) {
1160 f = file;
1161 } else {
1162 f++;
1163 }
1164 _file = f;
1165 _line = line;
1166 }
1167 #endif
1168
1169 #ifdef RISCV
1170 void LIR_List::set_cmp_oprs(LIR_Op* op) {
1171 switch (op->code()) {
1172 case lir_cmp:
1173 _cmp_opr1 = op->as_Op2()->in_opr1();
1174 _cmp_opr2 = op->as_Op2()->in_opr2();
1175 break;
1176 case lir_branch: // fall through
1177 case lir_cond_float_branch:
1178 assert(op->as_OpBranch()->cond() == lir_cond_always ||
1179 (_cmp_opr1 != LIR_OprFact::illegalOpr && _cmp_opr2 != LIR_OprFact::illegalOpr),
1180 "conditional branches must have legal operands");
1181 if (op->as_OpBranch()->cond() != lir_cond_always) {
1182 op->as_Op2()->set_in_opr1(_cmp_opr1);
1183 op->as_Op2()->set_in_opr2(_cmp_opr2);
1184 }
1185 break;
1186 case lir_cmove:
1187 op->as_Op4()->set_in_opr3(_cmp_opr1);
1188 op->as_Op4()->set_in_opr4(_cmp_opr2);
1189 break;
1190 #if INCLUDE_ZGC
1191 case lir_zloadbarrier_test:
1192 _cmp_opr1 = FrameMap::as_opr(t1);
1193 _cmp_opr2 = LIR_OprFact::intConst(0);
1194 break;
1195 #endif
1196 default:
1197 break;
1198 }
1199 }
1200 #endif
1201
1202 void LIR_List::append(LIR_InsertionBuffer* buffer) {
1203 assert(this == buffer->lir_list(), "wrong lir list");
1204 const int n = _operations.length();
1205
1206 if (buffer->number_of_ops() > 0) {
1207 // increase size of instructions list
1208 _operations.at_grow(n + buffer->number_of_ops() - 1, NULL);
1209 // insert ops from buffer into instructions list
1210 int op_index = buffer->number_of_ops() - 1;
1211 int ip_index = buffer->number_of_insertion_points() - 1;
1212 int from_index = n - 1;
1213 int to_index = _operations.length() - 1;
1214 for (; ip_index >= 0; ip_index --) {
1215 int index = buffer->index_at(ip_index);
1216 // make room after insertion point
1217 while (index < from_index) {
1218 _operations.at_put(to_index --, _operations.at(from_index --));
1219 }
1220 // insert ops from buffer
1221 for (int i = buffer->count_at(ip_index); i > 0; i --) {
1222 _operations.at_put(to_index --, buffer->op_at(op_index --));
1223 }
1224 }
1225 }
1226
1227 buffer->finish();
1228 }
1229
1230
1231 void LIR_List::oop2reg_patch(jobject o, LIR_Opr reg, CodeEmitInfo* info) {
1232 assert(reg->type() == T_OBJECT, "bad reg");
1233 append(new LIR_Op1(lir_move, LIR_OprFact::oopConst(o), reg, T_OBJECT, lir_patch_normal, info));
1234 }
1235
1236 void LIR_List::klass2reg_patch(Metadata* o, LIR_Opr reg, CodeEmitInfo* info) {
1237 assert(reg->type() == T_METADATA, "bad reg");
1238 append(new LIR_Op1(lir_move, LIR_OprFact::metadataConst(o), reg, T_METADATA, lir_patch_normal, info));
1239 }
1240
1241 void LIR_List::load(LIR_Address* addr, LIR_Opr src, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1242 append(new LIR_Op1(
1243 lir_move,
1244 LIR_OprFact::address(addr),
1245 src,
1246 addr->type(),
1247 patch_code,
1248 info));
1249 }
1250
1251
1252 void LIR_List::volatile_load_mem_reg(LIR_Address* address, LIR_Opr dst, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1253 append(new LIR_Op1(
1254 lir_move,
1255 LIR_OprFact::address(address),
1256 dst,
1257 address->type(),
1258 patch_code,
1259 info, lir_move_volatile));
1260 }
1261
1262 void LIR_List::volatile_load_unsafe_reg(LIR_Opr base, LIR_Opr offset, LIR_Opr dst, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1263 append(new LIR_Op1(
1264 lir_move,
1265 LIR_OprFact::address(new LIR_Address(base, offset, type)),
1266 dst,
1267 type,
1268 patch_code,
1269 info, lir_move_volatile));
1270 }
1271
1272
1273 void LIR_List::store_mem_int(jint v, LIR_Opr base, int offset_in_bytes, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1274 append(new LIR_Op1(
1275 lir_move,
1276 LIR_OprFact::intConst(v),
1277 LIR_OprFact::address(new LIR_Address(base, offset_in_bytes, type)),
1278 type,
1279 patch_code,
1280 info));
1281 }
1282
1283
1284 void LIR_List::store_mem_oop(jobject o, LIR_Opr base, int offset_in_bytes, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1285 append(new LIR_Op1(
1286 lir_move,
1287 LIR_OprFact::oopConst(o),
1288 LIR_OprFact::address(new LIR_Address(base, offset_in_bytes, type)),
1289 type,
1290 patch_code,
1291 info));
1292 }
1293
1294
1295 void LIR_List::store(LIR_Opr src, LIR_Address* addr, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1296 append(new LIR_Op1(
1297 lir_move,
1298 src,
1299 LIR_OprFact::address(addr),
1300 addr->type(),
1301 patch_code,
1302 info));
1303 }
1304
1305
1306 void LIR_List::volatile_store_mem_reg(LIR_Opr src, LIR_Address* addr, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1307 append(new LIR_Op1(
1308 lir_move,
1309 src,
1310 LIR_OprFact::address(addr),
1311 addr->type(),
1312 patch_code,
1313 info,
1314 lir_move_volatile));
1315 }
1316
1317 void LIR_List::volatile_store_unsafe_reg(LIR_Opr src, LIR_Opr base, LIR_Opr offset, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1318 append(new LIR_Op1(
1319 lir_move,
1320 src,
1321 LIR_OprFact::address(new LIR_Address(base, offset, type)),
1322 type,
1323 patch_code,
1324 info, lir_move_volatile));
1325 }
1326
1327
1328 void LIR_List::idiv(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1329 append(new LIR_Op3(
1330 lir_idiv,
1331 left,
1332 right,
1333 tmp,
1334 res,
1335 info));
1336 }
1337
1338
1339 void LIR_List::idiv(LIR_Opr left, int right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1340 append(new LIR_Op3(
1341 lir_idiv,
1342 left,
1343 LIR_OprFact::intConst(right),
1344 tmp,
1345 res,
1346 info));
1347 }
1348
1349
1350 void LIR_List::irem(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1351 append(new LIR_Op3(
1352 lir_irem,
1353 left,
1354 right,
1355 tmp,
1356 res,
1357 info));
1358 }
1359
1360
1361 void LIR_List::irem(LIR_Opr left, int right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1362 append(new LIR_Op3(
1363 lir_irem,
1364 left,
1365 LIR_OprFact::intConst(right),
1366 tmp,
1367 res,
1368 info));
1369 }
1370
1371
1372 void LIR_List::cmp_mem_int(LIR_Condition condition, LIR_Opr base, int disp, int c, CodeEmitInfo* info) {
1373 append(new LIR_Op2(
1374 lir_cmp,
1375 condition,
1376 LIR_OprFact::address(new LIR_Address(base, disp, T_INT)),
1377 LIR_OprFact::intConst(c),
1378 info));
1379 }
1380
1381
1382 void LIR_List::cmp_reg_mem(LIR_Condition condition, LIR_Opr reg, LIR_Address* addr, CodeEmitInfo* info) {
1383 append(new LIR_Op2(
1384 lir_cmp,
1385 condition,
1386 reg,
1387 LIR_OprFact::address(addr),
1388 info));
1389 }
1390
1391 void LIR_List::allocate_object(LIR_Opr dst, LIR_Opr t1, LIR_Opr t2, LIR_Opr t3, LIR_Opr t4,
1392 int header_size, int object_size, LIR_Opr klass, bool init_check, CodeStub* stub) {
1393 append(new LIR_OpAllocObj(
1394 klass,
1395 dst,
1396 t1,
1397 t2,
1398 t3,
1399 t4,
1400 header_size,
1401 object_size,
1402 init_check,
1403 stub));
1404 }
1405
1406 void LIR_List::allocate_array(LIR_Opr dst, LIR_Opr len, LIR_Opr t1,LIR_Opr t2, LIR_Opr t3,LIR_Opr t4, BasicType type, LIR_Opr klass, CodeStub* stub) {
1407 append(new LIR_OpAllocArray(
1408 klass,
1409 len,
1410 dst,
1411 t1,
1412 t2,
1413 t3,
1414 t4,
1415 type,
1416 stub));
1417 }
1418
1419 void LIR_List::shift_left(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) {
1420 append(new LIR_Op2(
1421 lir_shl,
1422 value,
1423 count,
1424 dst,
1425 tmp));
1426 }
1427
1428 void LIR_List::shift_right(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) {
1429 append(new LIR_Op2(
1430 lir_shr,
1431 value,
1432 count,
1433 dst,
1434 tmp));
1435 }
1436
1437
1438 void LIR_List::unsigned_shift_right(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) {
1439 append(new LIR_Op2(
1440 lir_ushr,
1441 value,
1442 count,
1443 dst,
1444 tmp));
1445 }
1446
1447 void LIR_List::fcmp2int(LIR_Opr left, LIR_Opr right, LIR_Opr dst, bool is_unordered_less) {
1448 append(new LIR_Op2(is_unordered_less ? lir_ucmp_fd2i : lir_cmp_fd2i,
1449 left,
1450 right,
1451 dst));
1452 }
1453
1454 void LIR_List::lock_object(LIR_Opr hdr, LIR_Opr obj, LIR_Opr lock, LIR_Opr scratch, CodeStub* stub, CodeEmitInfo* info) {
1455 append(new LIR_OpLock(
1456 lir_lock,
1457 hdr,
1458 obj,
1459 lock,
1460 scratch,
1461 stub,
1462 info));
1463 }
1464
1465 void LIR_List::unlock_object(LIR_Opr hdr, LIR_Opr obj, LIR_Opr lock, LIR_Opr scratch, CodeStub* stub) {
1466 append(new LIR_OpLock(
1467 lir_unlock,
1468 hdr,
1469 obj,
1470 lock,
1471 scratch,
1472 stub,
1473 NULL));
1474 }
1475
1476
1477 void check_LIR() {
1478 // cannot do the proper checking as PRODUCT and other modes return different results
1479 // guarantee(sizeof(LIR_OprDesc) == wordSize, "may not have a v-table");
1480 }
1481
1482
1483
1484 void LIR_List::checkcast (LIR_Opr result, LIR_Opr object, ciKlass* klass,
1485 LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, bool fast_check,
1486 CodeEmitInfo* info_for_exception, CodeEmitInfo* info_for_patch, CodeStub* stub,
1487 ciMethod* profiled_method, int profiled_bci) {
1488 LIR_OpTypeCheck* c = new LIR_OpTypeCheck(lir_checkcast, result, object, klass,
1489 tmp1, tmp2, tmp3, fast_check, info_for_exception, info_for_patch, stub);
1490 if (profiled_method != NULL) {
1491 c->set_profiled_method(profiled_method);
1492 c->set_profiled_bci(profiled_bci);
1493 c->set_should_profile(true);
1494 }
1495 append(c);
1496 }
1497
1498 void LIR_List::instanceof(LIR_Opr result, LIR_Opr object, ciKlass* klass, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, bool fast_check, CodeEmitInfo* info_for_patch, ciMethod* profiled_method, int profiled_bci) {
1499 LIR_OpTypeCheck* c = new LIR_OpTypeCheck(lir_instanceof, result, object, klass, tmp1, tmp2, tmp3, fast_check, NULL, info_for_patch, NULL);
1500 if (profiled_method != NULL) {
1501 c->set_profiled_method(profiled_method);
1502 c->set_profiled_bci(profiled_bci);
1503 c->set_should_profile(true);
1504 }
1505 append(c);
1506 }
1507
1508
1509 void LIR_List::store_check(LIR_Opr object, LIR_Opr array, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3,
1510 CodeEmitInfo* info_for_exception, ciMethod* profiled_method, int profiled_bci) {
1511 LIR_OpTypeCheck* c = new LIR_OpTypeCheck(lir_store_check, object, array, tmp1, tmp2, tmp3, info_for_exception);
1512 if (profiled_method != NULL) {
1513 c->set_profiled_method(profiled_method);
1514 c->set_profiled_bci(profiled_bci);
1515 c->set_should_profile(true);
1516 }
1517 append(c);
1518 }
1519
1520 void LIR_List::null_check(LIR_Opr opr, CodeEmitInfo* info, bool deoptimize_on_null) {
1521 if (deoptimize_on_null) {
1522 // Emit an explicit null check and deoptimize if opr is null
1523 CodeStub* deopt = new DeoptimizeStub(info, Deoptimization::Reason_null_check, Deoptimization::Action_none);
1524 cmp(lir_cond_equal, opr, LIR_OprFact::oopConst(NULL));
1525 branch(lir_cond_equal, deopt);
1526 } else {
1527 // Emit an implicit null check
1528 append(new LIR_Op1(lir_null_check, opr, info));
1529 }
1530 }
1531
1532 void LIR_List::cas_long(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value,
1533 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
1534 append(new LIR_OpCompareAndSwap(lir_cas_long, addr, cmp_value, new_value, t1, t2, result));
1535 }
1536
1537 void LIR_List::cas_obj(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value,
1538 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
1539 append(new LIR_OpCompareAndSwap(lir_cas_obj, addr, cmp_value, new_value, t1, t2, result));
1540 }
1541
1542 void LIR_List::cas_int(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value,
1543 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
1544 append(new LIR_OpCompareAndSwap(lir_cas_int, addr, cmp_value, new_value, t1, t2, result));
1545 }
1546
1547
1548 #ifdef PRODUCT
1549
1550 void print_LIR(BlockList* blocks) {
1551 }
1552
1553 #else
1554 // LIR_OprDesc
1555 void LIR_OprDesc::print() const {
1556 print(tty);
1557 }
1558
1559 void LIR_OprDesc::print(outputStream* out) const {
1560 if (is_illegal()) {
1561 return;
1562 }
1563
1564 out->print("[");
1565 if (is_pointer()) {
1566 pointer()->print_value_on(out);
1567 } else if (is_single_stack()) {
1568 out->print("stack:%d", single_stack_ix());
1569 } else if (is_double_stack()) {
1570 out->print("dbl_stack:%d",double_stack_ix());
1571 } else if (is_virtual()) {
1572 out->print("R%d", vreg_number());
1573 } else if (is_single_cpu()) {
1574 out->print("%s", as_register()->name());
1575 } else if (is_double_cpu()) {
1576 out->print("%s", as_register_hi()->name());
1577 out->print("%s", as_register_lo()->name());
1578 #if defined(X86)
1579 } else if (is_single_xmm()) {
1580 out->print("%s", as_xmm_float_reg()->name());
1581 } else if (is_double_xmm()) {
1582 out->print("%s", as_xmm_double_reg()->name());
1583 } else if (is_single_fpu()) {
1584 out->print("fpu%d", fpu_regnr());
1585 } else if (is_double_fpu()) {
1586 out->print("fpu%d", fpu_regnrLo());
1587 #elif defined(AARCH64)
1588 } else if (is_single_fpu()) {
1589 out->print("fpu%d", fpu_regnr());
1590 } else if (is_double_fpu()) {
1591 out->print("fpu%d", fpu_regnrLo());
1592 #elif defined(ARM)
1593 } else if (is_single_fpu()) {
1594 out->print("s%d", fpu_regnr());
1595 } else if (is_double_fpu()) {
1596 out->print("d%d", fpu_regnrLo() >> 1);
1597 #else
1598 } else if (is_single_fpu()) {
1599 out->print("%s", as_float_reg()->name());
1600 } else if (is_double_fpu()) {
1601 out->print("%s", as_double_reg()->name());
1602 #endif
1603
1604 } else if (is_illegal()) {
1605 out->print("-");
1606 } else {
1607 out->print("Unknown Operand");
1608 }
1609 if (!is_illegal()) {
1610 out->print("|%c", type_char());
1611 }
1612 if (is_register() && is_last_use()) {
1613 out->print("(last_use)");
1614 }
1615 out->print("]");
1616 }
1617
1618
1619 // LIR_Address
1620 void LIR_Const::print_value_on(outputStream* out) const {
1621 switch (type()) {
1622 case T_ADDRESS:out->print("address:%d",as_jint()); break;
1623 case T_INT: out->print("int:%d", as_jint()); break;
1624 case T_LONG: out->print("lng:" JLONG_FORMAT, as_jlong()); break;
1625 case T_FLOAT: out->print("flt:%f", as_jfloat()); break;
1626 case T_DOUBLE: out->print("dbl:%f", as_jdouble()); break;
1627 case T_OBJECT: out->print("obj:" INTPTR_FORMAT, p2i(as_jobject())); break;
1628 case T_METADATA: out->print("metadata:" INTPTR_FORMAT, p2i(as_metadata()));break;
1629 default: out->print("%3d:0x" UINT64_FORMAT_X, type(), (uint64_t)as_jlong()); break;
1630 }
1631 }
1632
1633 // LIR_Address
1634 void LIR_Address::print_value_on(outputStream* out) const {
1635 out->print("Base:"); _base->print(out);
1636 if (!_index->is_illegal()) {
1637 out->print(" Index:"); _index->print(out);
1638 switch (scale()) {
1639 case times_1: break;
1640 case times_2: out->print(" * 2"); break;
1641 case times_4: out->print(" * 4"); break;
1642 case times_8: out->print(" * 8"); break;
1643 }
1644 }
1645 out->print(" Disp: " INTX_FORMAT, _disp);
1646 }
1647
1648 // debug output of block header without InstructionPrinter
1649 // (because phi functions are not necessary for LIR)
1650 static void print_block(BlockBegin* x) {
1651 // print block id
1652 BlockEnd* end = x->end();
1653 tty->print("B%d ", x->block_id());
1654
1655 // print flags
1656 if (x->is_set(BlockBegin::std_entry_flag)) tty->print("std ");
1657 if (x->is_set(BlockBegin::osr_entry_flag)) tty->print("osr ");
1658 if (x->is_set(BlockBegin::exception_entry_flag)) tty->print("ex ");
1659 if (x->is_set(BlockBegin::subroutine_entry_flag)) tty->print("jsr ");
1660 if (x->is_set(BlockBegin::backward_branch_target_flag)) tty->print("bb ");
1661 if (x->is_set(BlockBegin::linear_scan_loop_header_flag)) tty->print("lh ");
1662 if (x->is_set(BlockBegin::linear_scan_loop_end_flag)) tty->print("le ");
1663
1664 // print block bci range
1665 tty->print("[%d, %d] ", x->bci(), (end == NULL ? -1 : end->printable_bci()));
1666
1667 // print predecessors and successors
1668 if (x->number_of_preds() > 0) {
1669 tty->print("preds: ");
1670 for (int i = 0; i < x->number_of_preds(); i ++) {
1671 tty->print("B%d ", x->pred_at(i)->block_id());
1672 }
1673 }
1674
1675 if (x->number_of_sux() > 0) {
1676 tty->print("sux: ");
1677 for (int i = 0; i < x->number_of_sux(); i ++) {
1678 tty->print("B%d ", x->sux_at(i)->block_id());
1679 }
1680 }
1681
1682 // print exception handlers
1683 if (x->number_of_exception_handlers() > 0) {
1684 tty->print("xhandler: ");
1685 for (int i = 0; i < x->number_of_exception_handlers(); i++) {
1686 tty->print("B%d ", x->exception_handler_at(i)->block_id());
1687 }
1688 }
1689
1690 tty->cr();
1691 }
1692
1693 void print_LIR(BlockList* blocks) {
1694 tty->print_cr("LIR:");
1695 int i;
1696 for (i = 0; i < blocks->length(); i++) {
1697 BlockBegin* bb = blocks->at(i);
1698 print_block(bb);
1699 tty->print("__id_Instruction___________________________________________"); tty->cr();
1700 bb->lir()->print_instructions();
1701 }
1702 }
1703
1704 void LIR_List::print_instructions() {
1705 for (int i = 0; i < _operations.length(); i++) {
1706 _operations.at(i)->print(); tty->cr();
1707 }
1708 tty->cr();
1709 }
1710
1711 // LIR_Ops printing routines
1712 // LIR_Op
1713 void LIR_Op::print_on(outputStream* out) const {
1714 if (id() != -1 || PrintCFGToFile) {
1715 out->print("%4d ", id());
1716 } else {
1717 out->print(" ");
1718 }
1719 out->print("%s ", name());
1720 print_instr(out);
1721 if (info() != NULL) out->print(" [bci:%d]", info()->stack()->bci());
1722 #ifdef ASSERT
1723 if (Verbose && _file != NULL) {
1724 out->print(" (%s:%d)", _file, _line);
1725 }
1726 #endif
1727 }
1728
1729 const char * LIR_Op::name() const {
1730 const char* s = NULL;
1731 switch(code()) {
1732 // LIR_Op0
1733 case lir_membar: s = "membar"; break;
1734 case lir_membar_acquire: s = "membar_acquire"; break;
1735 case lir_membar_release: s = "membar_release"; break;
1736 case lir_membar_loadload: s = "membar_loadload"; break;
1737 case lir_membar_storestore: s = "membar_storestore"; break;
1738 case lir_membar_loadstore: s = "membar_loadstore"; break;
1739 case lir_membar_storeload: s = "membar_storeload"; break;
1740 case lir_label: s = "label"; break;
1741 case lir_nop: s = "nop"; break;
1742 case lir_on_spin_wait: s = "on_spin_wait"; break;
1743 case lir_backwardbranch_target: s = "backbranch"; break;
1744 case lir_std_entry: s = "std_entry"; break;
1745 case lir_osr_entry: s = "osr_entry"; break;
1746 case lir_fpop_raw: s = "fpop_raw"; break;
1747 case lir_breakpoint: s = "breakpoint"; break;
1748 case lir_get_thread: s = "get_thread"; break;
1749 // LIR_Op1
1750 case lir_fxch: s = "fxch"; break;
1751 case lir_fld: s = "fld"; break;
1752 case lir_push: s = "push"; break;
1753 case lir_pop: s = "pop"; break;
1754 case lir_null_check: s = "null_check"; break;
1755 case lir_return: s = "return"; break;
1756 case lir_safepoint: s = "safepoint"; break;
1757 case lir_leal: s = "leal"; break;
1758 case lir_branch: s = "branch"; break;
1759 case lir_cond_float_branch: s = "flt_cond_br"; break;
1760 case lir_move: s = "move"; break;
1761 case lir_roundfp: s = "roundfp"; break;
1762 case lir_rtcall: s = "rtcall"; break;
1763 case lir_throw: s = "throw"; break;
1764 case lir_unwind: s = "unwind"; break;
1765 case lir_convert: s = "convert"; break;
1766 case lir_alloc_object: s = "alloc_obj"; break;
1767 case lir_monaddr: s = "mon_addr"; break;
1768 // LIR_Op2
1769 case lir_cmp: s = "cmp"; break;
1770 case lir_cmp_l2i: s = "cmp_l2i"; break;
1771 case lir_ucmp_fd2i: s = "ucomp_fd2i"; break;
1772 case lir_cmp_fd2i: s = "comp_fd2i"; break;
1773 case lir_cmove: s = "cmove"; break;
1774 case lir_add: s = "add"; break;
1775 case lir_sub: s = "sub"; break;
1776 case lir_mul: s = "mul"; break;
1777 case lir_div: s = "div"; break;
1778 case lir_rem: s = "rem"; break;
1779 case lir_abs: s = "abs"; break;
1780 case lir_neg: s = "neg"; break;
1781 case lir_sqrt: s = "sqrt"; break;
1782 case lir_logic_and: s = "logic_and"; break;
1783 case lir_logic_or: s = "logic_or"; break;
1784 case lir_logic_xor: s = "logic_xor"; break;
1785 case lir_shl: s = "shift_left"; break;
1786 case lir_shr: s = "shift_right"; break;
1787 case lir_ushr: s = "ushift_right"; break;
1788 case lir_alloc_array: s = "alloc_array"; break;
1789 case lir_xadd: s = "xadd"; break;
1790 case lir_xchg: s = "xchg"; break;
1791 // LIR_Op3
1792 case lir_idiv: s = "idiv"; break;
1793 case lir_irem: s = "irem"; break;
1794 case lir_fmad: s = "fmad"; break;
1795 case lir_fmaf: s = "fmaf"; break;
1796 // LIR_OpJavaCall
1797 case lir_static_call: s = "static"; break;
1798 case lir_optvirtual_call: s = "optvirtual"; break;
1799 case lir_icvirtual_call: s = "icvirtual"; break;
1800 case lir_dynamic_call: s = "dynamic"; break;
1801 // LIR_OpArrayCopy
1802 case lir_arraycopy: s = "arraycopy"; break;
1803 // LIR_OpUpdateCRC32
1804 case lir_updatecrc32: s = "updatecrc32"; break;
1805 // LIR_OpLock
1806 case lir_lock: s = "lock"; break;
1807 case lir_unlock: s = "unlock"; break;
1808 // LIR_OpDelay
1809 case lir_delay_slot: s = "delay"; break;
1810 // LIR_OpTypeCheck
1811 case lir_instanceof: s = "instanceof"; break;
1812 case lir_checkcast: s = "checkcast"; break;
1813 case lir_store_check: s = "store_check"; break;
1814 // LIR_OpCompareAndSwap
1815 case lir_cas_long: s = "cas_long"; break;
1816 case lir_cas_obj: s = "cas_obj"; break;
1817 case lir_cas_int: s = "cas_int"; break;
1818 // LIR_OpProfileCall
1819 case lir_profile_call: s = "profile_call"; break;
1820 // LIR_OpProfileType
1821 case lir_profile_type: s = "profile_type"; break;
1822 // LIR_OpAssert
1823 #ifdef ASSERT
1824 case lir_assert: s = "assert"; break;
1825 #endif
1826 case lir_none: ShouldNotReachHere();break;
1827 default: s = "illegal_op"; break;
1828 }
1829 return s;
1830 }
1831
1832 // LIR_OpJavaCall
1833 void LIR_OpJavaCall::print_instr(outputStream* out) const {
1834 out->print("call: ");
1835 out->print("[addr: " INTPTR_FORMAT "]", p2i(address()));
1836 if (receiver()->is_valid()) {
1837 out->print(" [recv: "); receiver()->print(out); out->print("]");
1838 }
1839 if (result_opr()->is_valid()) {
1840 out->print(" [result: "); result_opr()->print(out); out->print("]");
1841 }
1842 }
1843
1844 // LIR_OpLabel
1845 void LIR_OpLabel::print_instr(outputStream* out) const {
1846 out->print("[label:" INTPTR_FORMAT "]", p2i(_label));
1847 }
1848
1849 // LIR_OpArrayCopy
1850 void LIR_OpArrayCopy::print_instr(outputStream* out) const {
1851 src()->print(out); out->print(" ");
1852 src_pos()->print(out); out->print(" ");
1853 dst()->print(out); out->print(" ");
1854 dst_pos()->print(out); out->print(" ");
1855 length()->print(out); out->print(" ");
1856 tmp()->print(out); out->print(" ");
1857 }
1858
1859 // LIR_OpUpdateCRC32
1860 void LIR_OpUpdateCRC32::print_instr(outputStream* out) const {
1861 crc()->print(out); out->print(" ");
1862 val()->print(out); out->print(" ");
1863 result_opr()->print(out); out->print(" ");
1864 }
1865
1866 // LIR_OpCompareAndSwap
1867 void LIR_OpCompareAndSwap::print_instr(outputStream* out) const {
1868 addr()->print(out); out->print(" ");
1869 cmp_value()->print(out); out->print(" ");
1870 new_value()->print(out); out->print(" ");
1871 tmp1()->print(out); out->print(" ");
1872 tmp2()->print(out); out->print(" ");
1873
1874 }
1875
1876 // LIR_Op0
1877 void LIR_Op0::print_instr(outputStream* out) const {
1878 result_opr()->print(out);
1879 }
1880
1881 // LIR_Op1
1882 const char * LIR_Op1::name() const {
1883 if (code() == lir_move) {
1884 switch (move_kind()) {
1885 case lir_move_normal:
1886 return "move";
1887 case lir_move_unaligned:
1888 return "unaligned move";
1889 case lir_move_volatile:
1890 return "volatile_move";
1891 case lir_move_wide:
1892 return "wide_move";
1893 default:
1894 ShouldNotReachHere();
1895 return "illegal_op";
1896 }
1897 } else {
1898 return LIR_Op::name();
1899 }
1900 }
1901
1902
1903 void LIR_Op1::print_instr(outputStream* out) const {
1904 _opr->print(out); out->print(" ");
1905 result_opr()->print(out); out->print(" ");
1906 print_patch_code(out, patch_code());
1907 }
1908
1909
1910 // LIR_Op1
1911 void LIR_OpRTCall::print_instr(outputStream* out) const {
1912 intx a = (intx)addr();
1913 out->print("%s", Runtime1::name_for_address(addr()));
1914 out->print(" ");
1915 tmp()->print(out);
1916 }
1917
1918 void LIR_Op1::print_patch_code(outputStream* out, LIR_PatchCode code) {
1919 switch(code) {
1920 case lir_patch_none: break;
1921 case lir_patch_low: out->print("[patch_low]"); break;
1922 case lir_patch_high: out->print("[patch_high]"); break;
1923 case lir_patch_normal: out->print("[patch_normal]"); break;
1924 default: ShouldNotReachHere();
1925 }
1926 }
1927
1928 // LIR_OpBranch
1929 void LIR_OpBranch::print_instr(outputStream* out) const {
1930 print_condition(out, cond()); out->print(" ");
1931 #ifdef RISCV
1932 in_opr1()->print(out); out->print(" ");
1933 in_opr2()->print(out); out->print(" ");
1934 #endif
1935 if (block() != NULL) {
1936 out->print("[B%d] ", block()->block_id());
1937 } else if (stub() != NULL) {
1938 out->print("[");
1939 stub()->print_name(out);
1940 out->print(": " INTPTR_FORMAT "]", p2i(stub()));
1941 if (stub()->info() != NULL) out->print(" [bci:%d]", stub()->info()->stack()->bci());
1942 } else {
1943 out->print("[label:" INTPTR_FORMAT "] ", p2i(label()));
1944 }
1945 if (ublock() != NULL) {
1946 out->print("unordered: [B%d] ", ublock()->block_id());
1947 }
1948 }
1949
1950 void LIR_Op::print_condition(outputStream* out, LIR_Condition cond) {
1951 switch(cond) {
1952 case lir_cond_equal: out->print("[EQ]"); break;
1953 case lir_cond_notEqual: out->print("[NE]"); break;
1954 case lir_cond_less: out->print("[LT]"); break;
1955 case lir_cond_lessEqual: out->print("[LE]"); break;
1956 case lir_cond_greaterEqual: out->print("[GE]"); break;
1957 case lir_cond_greater: out->print("[GT]"); break;
1958 case lir_cond_belowEqual: out->print("[BE]"); break;
1959 case lir_cond_aboveEqual: out->print("[AE]"); break;
1960 case lir_cond_always: out->print("[AL]"); break;
1961 default: out->print("[%d]",cond); break;
1962 }
1963 }
1964
1965 // LIR_OpConvert
1966 void LIR_OpConvert::print_instr(outputStream* out) const {
1967 print_bytecode(out, bytecode());
1968 in_opr()->print(out); out->print(" ");
1969 result_opr()->print(out); out->print(" ");
1970 #ifdef PPC32
1971 if(tmp1()->is_valid()) {
1972 tmp1()->print(out); out->print(" ");
1973 tmp2()->print(out); out->print(" ");
1974 }
1975 #endif
1976 }
1977
1978 void LIR_OpConvert::print_bytecode(outputStream* out, Bytecodes::Code code) {
1979 switch(code) {
1980 case Bytecodes::_d2f: out->print("[d2f] "); break;
1981 case Bytecodes::_d2i: out->print("[d2i] "); break;
1982 case Bytecodes::_d2l: out->print("[d2l] "); break;
1983 case Bytecodes::_f2d: out->print("[f2d] "); break;
1984 case Bytecodes::_f2i: out->print("[f2i] "); break;
1985 case Bytecodes::_f2l: out->print("[f2l] "); break;
1986 case Bytecodes::_i2b: out->print("[i2b] "); break;
1987 case Bytecodes::_i2c: out->print("[i2c] "); break;
1988 case Bytecodes::_i2d: out->print("[i2d] "); break;
1989 case Bytecodes::_i2f: out->print("[i2f] "); break;
1990 case Bytecodes::_i2l: out->print("[i2l] "); break;
1991 case Bytecodes::_i2s: out->print("[i2s] "); break;
1992 case Bytecodes::_l2i: out->print("[l2i] "); break;
1993 case Bytecodes::_l2f: out->print("[l2f] "); break;
1994 case Bytecodes::_l2d: out->print("[l2d] "); break;
1995 default:
1996 out->print("[?%d]",code);
1997 break;
1998 }
1999 }
2000
2001 void LIR_OpAllocObj::print_instr(outputStream* out) const {
2002 klass()->print(out); out->print(" ");
2003 obj()->print(out); out->print(" ");
2004 tmp1()->print(out); out->print(" ");
2005 tmp2()->print(out); out->print(" ");
2006 tmp3()->print(out); out->print(" ");
2007 tmp4()->print(out); out->print(" ");
2008 out->print("[hdr:%d]", header_size()); out->print(" ");
2009 out->print("[obj:%d]", object_size()); out->print(" ");
2010 out->print("[lbl:" INTPTR_FORMAT "]", p2i(stub()->entry()));
2011 }
2012
2013 void LIR_OpRoundFP::print_instr(outputStream* out) const {
2014 _opr->print(out); out->print(" ");
2015 tmp()->print(out); out->print(" ");
2016 result_opr()->print(out); out->print(" ");
2017 }
2018
2019 // LIR_Op2
2020 void LIR_Op2::print_instr(outputStream* out) const {
2021 #ifdef RISCV
2022 if (code() == lir_cmp || code() == lir_branch || code() == lir_cond_float_branch) {
2023 #else
2024 if (code() == lir_cmove || code() == lir_cmp) {
2025 #endif
2026 print_condition(out, condition()); out->print(" ");
2027 }
2028 in_opr1()->print(out); out->print(" ");
2029 in_opr2()->print(out); out->print(" ");
2030 if (tmp1_opr()->is_valid()) { tmp1_opr()->print(out); out->print(" "); }
2031 if (tmp2_opr()->is_valid()) { tmp2_opr()->print(out); out->print(" "); }
2032 if (tmp3_opr()->is_valid()) { tmp3_opr()->print(out); out->print(" "); }
2033 if (tmp4_opr()->is_valid()) { tmp4_opr()->print(out); out->print(" "); }
2034 if (tmp5_opr()->is_valid()) { tmp5_opr()->print(out); out->print(" "); }
2035 result_opr()->print(out);
2036 }
2037
2038 void LIR_OpAllocArray::print_instr(outputStream* out) const {
2039 klass()->print(out); out->print(" ");
2040 len()->print(out); out->print(" ");
2041 obj()->print(out); out->print(" ");
2042 tmp1()->print(out); out->print(" ");
2043 tmp2()->print(out); out->print(" ");
2044 tmp3()->print(out); out->print(" ");
2045 tmp4()->print(out); out->print(" ");
2046 out->print("[type:0x%x]", type()); out->print(" ");
2047 out->print("[label:" INTPTR_FORMAT "]", p2i(stub()->entry()));
2048 }
2049
2050
2051 void LIR_OpTypeCheck::print_instr(outputStream* out) const {
2052 object()->print(out); out->print(" ");
2053 if (code() == lir_store_check) {
2054 array()->print(out); out->print(" ");
2055 }
2056 if (code() != lir_store_check) {
2057 klass()->print_name_on(out); out->print(" ");
2058 if (fast_check()) out->print("fast_check ");
2059 }
2060 tmp1()->print(out); out->print(" ");
2061 tmp2()->print(out); out->print(" ");
2062 tmp3()->print(out); out->print(" ");
2063 result_opr()->print(out); out->print(" ");
2064 if (info_for_exception() != NULL) out->print(" [bci:%d]", info_for_exception()->stack()->bci());
2065 }
2066
2067
2068 // LIR_Op3
2069 void LIR_Op3::print_instr(outputStream* out) const {
2070 in_opr1()->print(out); out->print(" ");
2071 in_opr2()->print(out); out->print(" ");
2072 in_opr3()->print(out); out->print(" ");
2073 result_opr()->print(out);
2074 }
2075
2076 #ifdef RISCV
2077 // LIR_Op4
2078 void LIR_Op4::print_instr(outputStream* out) const {
2079 print_condition(out, condition()); out->print(" ");
2080 in_opr1()->print(out); out->print(" ");
2081 in_opr2()->print(out); out->print(" ");
2082 in_opr3()->print(out); out->print(" ");
2083 in_opr4()->print(out); out->print(" ");
2084 result_opr()->print(out);
2085 }
2086 #endif
2087
2088 void LIR_OpLock::print_instr(outputStream* out) const {
2089 hdr_opr()->print(out); out->print(" ");
2090 obj_opr()->print(out); out->print(" ");
2091 lock_opr()->print(out); out->print(" ");
2092 if (_scratch->is_valid()) {
2093 _scratch->print(out); out->print(" ");
2094 }
2095 out->print("[lbl:" INTPTR_FORMAT "]", p2i(stub()->entry()));
2096 }
2097
2098 void LIR_OpLoadKlass::print_instr(outputStream* out) const {
2099 obj()->print(out); out->print(" ");
2100 result_opr()->print(out); out->print(" ");
2101 if (stub()) {
2102 out->print("[lbl:" INTPTR_FORMAT "]", p2i(stub()->entry()));
2103 }
2104 }
2105
2106 #ifdef ASSERT
2107 void LIR_OpAssert::print_instr(outputStream* out) const {
2108 print_condition(out, condition()); out->print(" ");
2109 in_opr1()->print(out); out->print(" ");
2110 in_opr2()->print(out); out->print(", \"");
2111 out->print("%s", msg()); out->print("\"");
2112 }
2113 #endif
2114
2115
2116 void LIR_OpDelay::print_instr(outputStream* out) const {
2117 _op->print_on(out);
2118 }
2119
2120
2121 // LIR_OpProfileCall
2122 void LIR_OpProfileCall::print_instr(outputStream* out) const {
2123 profiled_method()->name()->print_symbol_on(out);
2124 out->print(".");
2125 profiled_method()->holder()->name()->print_symbol_on(out);
2126 out->print(" @ %d ", profiled_bci());
2127 mdo()->print(out); out->print(" ");
2128 recv()->print(out); out->print(" ");
2129 tmp1()->print(out); out->print(" ");
2130 }
2131
2132 // LIR_OpProfileType
2133 void LIR_OpProfileType::print_instr(outputStream* out) const {
2134 out->print("exact = ");
2135 if (exact_klass() == NULL) {
2136 out->print("unknown");
2137 } else {
2138 exact_klass()->print_name_on(out);
2139 }
2140 out->print(" current = "); ciTypeEntries::print_ciklass(out, current_klass());
2141 out->print(" ");
2142 mdp()->print(out); out->print(" ");
2143 obj()->print(out); out->print(" ");
2144 tmp()->print(out); out->print(" ");
2145 }
2146
2147 #endif // PRODUCT
2148
2149 // Implementation of LIR_InsertionBuffer
2150
2151 void LIR_InsertionBuffer::append(int index, LIR_Op* op) {
2152 assert(_index_and_count.length() % 2 == 0, "must have a count for each index");
2153
2154 int i = number_of_insertion_points() - 1;
2155 if (i < 0 || index_at(i) < index) {
2156 append_new(index, 1);
2157 } else {
2158 assert(index_at(i) == index, "can append LIR_Ops in ascending order only");
2159 assert(count_at(i) > 0, "check");
2160 set_count_at(i, count_at(i) + 1);
2161 }
2162 _ops.push(op);
2163
2164 DEBUG_ONLY(verify());
2165 }
2166
2167 #ifdef ASSERT
2168 void LIR_InsertionBuffer::verify() {
2169 int sum = 0;
2170 int prev_idx = -1;
2171
2172 for (int i = 0; i < number_of_insertion_points(); i++) {
2173 assert(prev_idx < index_at(i), "index must be ordered ascending");
2174 sum += count_at(i);
2175 }
2176 assert(sum == number_of_ops(), "wrong total sum");
2177 }
2178 #endif