1 //
2 // Copyright (c) 2003, 2023, Oracle and/or its affiliates. All rights reserved.
3 // Copyright (c) 2014, 2021, Red Hat, Inc. All rights reserved.
4 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 //
6 // This code is free software; you can redistribute it and/or modify it
7 // under the terms of the GNU General Public License version 2 only, as
8 // published by the Free Software Foundation.
9 //
10 // This code is distributed in the hope that it will be useful, but WITHOUT
11 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 // version 2 for more details (a copy is included in the LICENSE file that
14 // accompanied this code).
15 //
16 // You should have received a copy of the GNU General Public License version
17 // 2 along with this work; if not, write to the Free Software Foundation,
18 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 //
20 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 // or visit www.oracle.com if you need additional information or have any
22 // questions.
23 //
24 //
25
26 // AArch64 Architecture Description File
27
28 //----------REGISTER DEFINITION BLOCK------------------------------------------
29 // This information is used by the matcher and the register allocator to
30 // describe individual registers and classes of registers within the target
31 // architecture.
32
33 register %{
34 //----------Architecture Description Register Definitions----------------------
35 // General Registers
36 // "reg_def" name ( register save type, C convention save type,
37 // ideal register type, encoding );
38 // Register Save Types:
39 //
40 // NS = No-Save: The register allocator assumes that these registers
41 // can be used without saving upon entry to the method, &
42 // that they do not need to be saved at call sites.
43 //
44 // SOC = Save-On-Call: The register allocator assumes that these registers
45 // can be used without saving upon entry to the method,
46 // but that they must be saved at call sites.
47 //
48 // SOE = Save-On-Entry: The register allocator assumes that these registers
49 // must be saved before using them upon entry to the
50 // method, but they do not need to be saved at call
51 // sites.
52 //
53 // AS = Always-Save: The register allocator assumes that these registers
54 // must be saved before using them upon entry to the
55 // method, & that they must be saved at call sites.
56 //
57 // Ideal Register Type is used to determine how to save & restore a
58 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
59 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
60 //
61 // The encoding number is the actual bit-pattern placed into the opcodes.
62
63 // We must define the 64 bit int registers in two 32 bit halves, the
64 // real lower register and a virtual upper half register. upper halves
65 // are used by the register allocator but are not actually supplied as
66 // operands to memory ops.
67 //
68 // follow the C1 compiler in making registers
69 //
70 // r0-r7,r10-r26 volatile (caller save)
71 // r27-r32 system (no save, no allocate)
72 // r8-r9 non-allocatable (so we can use them as scratch regs)
73 //
74 // as regards Java usage. we don't use any callee save registers
75 // because this makes it difficult to de-optimise a frame (see comment
76 // in x86 implementation of Deoptimization::unwind_callee_save_values)
77 //
78
79 // General Registers
80
81 reg_def R0 ( SOC, SOC, Op_RegI, 0, r0->as_VMReg() );
82 reg_def R0_H ( SOC, SOC, Op_RegI, 0, r0->as_VMReg()->next() );
83 reg_def R1 ( SOC, SOC, Op_RegI, 1, r1->as_VMReg() );
84 reg_def R1_H ( SOC, SOC, Op_RegI, 1, r1->as_VMReg()->next() );
85 reg_def R2 ( SOC, SOC, Op_RegI, 2, r2->as_VMReg() );
86 reg_def R2_H ( SOC, SOC, Op_RegI, 2, r2->as_VMReg()->next() );
87 reg_def R3 ( SOC, SOC, Op_RegI, 3, r3->as_VMReg() );
88 reg_def R3_H ( SOC, SOC, Op_RegI, 3, r3->as_VMReg()->next() );
89 reg_def R4 ( SOC, SOC, Op_RegI, 4, r4->as_VMReg() );
90 reg_def R4_H ( SOC, SOC, Op_RegI, 4, r4->as_VMReg()->next() );
91 reg_def R5 ( SOC, SOC, Op_RegI, 5, r5->as_VMReg() );
92 reg_def R5_H ( SOC, SOC, Op_RegI, 5, r5->as_VMReg()->next() );
93 reg_def R6 ( SOC, SOC, Op_RegI, 6, r6->as_VMReg() );
94 reg_def R6_H ( SOC, SOC, Op_RegI, 6, r6->as_VMReg()->next() );
95 reg_def R7 ( SOC, SOC, Op_RegI, 7, r7->as_VMReg() );
96 reg_def R7_H ( SOC, SOC, Op_RegI, 7, r7->as_VMReg()->next() );
97 reg_def R8 ( NS, SOC, Op_RegI, 8, r8->as_VMReg() ); // rscratch1, non-allocatable
98 reg_def R8_H ( NS, SOC, Op_RegI, 8, r8->as_VMReg()->next() );
99 reg_def R9 ( NS, SOC, Op_RegI, 9, r9->as_VMReg() ); // rscratch2, non-allocatable
100 reg_def R9_H ( NS, SOC, Op_RegI, 9, r9->as_VMReg()->next() );
101 reg_def R10 ( SOC, SOC, Op_RegI, 10, r10->as_VMReg() );
102 reg_def R10_H ( SOC, SOC, Op_RegI, 10, r10->as_VMReg()->next());
103 reg_def R11 ( SOC, SOC, Op_RegI, 11, r11->as_VMReg() );
104 reg_def R11_H ( SOC, SOC, Op_RegI, 11, r11->as_VMReg()->next());
105 reg_def R12 ( SOC, SOC, Op_RegI, 12, r12->as_VMReg() );
106 reg_def R12_H ( SOC, SOC, Op_RegI, 12, r12->as_VMReg()->next());
107 reg_def R13 ( SOC, SOC, Op_RegI, 13, r13->as_VMReg() );
108 reg_def R13_H ( SOC, SOC, Op_RegI, 13, r13->as_VMReg()->next());
109 reg_def R14 ( SOC, SOC, Op_RegI, 14, r14->as_VMReg() );
110 reg_def R14_H ( SOC, SOC, Op_RegI, 14, r14->as_VMReg()->next());
111 reg_def R15 ( SOC, SOC, Op_RegI, 15, r15->as_VMReg() );
112 reg_def R15_H ( SOC, SOC, Op_RegI, 15, r15->as_VMReg()->next());
113 reg_def R16 ( SOC, SOC, Op_RegI, 16, r16->as_VMReg() );
114 reg_def R16_H ( SOC, SOC, Op_RegI, 16, r16->as_VMReg()->next());
115 reg_def R17 ( SOC, SOC, Op_RegI, 17, r17->as_VMReg() );
116 reg_def R17_H ( SOC, SOC, Op_RegI, 17, r17->as_VMReg()->next());
117 reg_def R18 ( SOC, SOC, Op_RegI, 18, r18_tls->as_VMReg() );
118 reg_def R18_H ( SOC, SOC, Op_RegI, 18, r18_tls->as_VMReg()->next());
119 reg_def R19 ( SOC, SOE, Op_RegI, 19, r19->as_VMReg() );
120 reg_def R19_H ( SOC, SOE, Op_RegI, 19, r19->as_VMReg()->next());
121 reg_def R20 ( SOC, SOE, Op_RegI, 20, r20->as_VMReg() ); // caller esp
122 reg_def R20_H ( SOC, SOE, Op_RegI, 20, r20->as_VMReg()->next());
123 reg_def R21 ( SOC, SOE, Op_RegI, 21, r21->as_VMReg() );
124 reg_def R21_H ( SOC, SOE, Op_RegI, 21, r21->as_VMReg()->next());
125 reg_def R22 ( SOC, SOE, Op_RegI, 22, r22->as_VMReg() );
126 reg_def R22_H ( SOC, SOE, Op_RegI, 22, r22->as_VMReg()->next());
127 reg_def R23 ( SOC, SOE, Op_RegI, 23, r23->as_VMReg() );
128 reg_def R23_H ( SOC, SOE, Op_RegI, 23, r23->as_VMReg()->next());
129 reg_def R24 ( SOC, SOE, Op_RegI, 24, r24->as_VMReg() );
130 reg_def R24_H ( SOC, SOE, Op_RegI, 24, r24->as_VMReg()->next());
131 reg_def R25 ( SOC, SOE, Op_RegI, 25, r25->as_VMReg() );
132 reg_def R25_H ( SOC, SOE, Op_RegI, 25, r25->as_VMReg()->next());
133 reg_def R26 ( SOC, SOE, Op_RegI, 26, r26->as_VMReg() );
134 reg_def R26_H ( SOC, SOE, Op_RegI, 26, r26->as_VMReg()->next());
135 reg_def R27 ( SOC, SOE, Op_RegI, 27, r27->as_VMReg() ); // heapbase
136 reg_def R27_H ( SOC, SOE, Op_RegI, 27, r27->as_VMReg()->next());
137 reg_def R28 ( NS, SOE, Op_RegI, 28, r28->as_VMReg() ); // thread
138 reg_def R28_H ( NS, SOE, Op_RegI, 28, r28->as_VMReg()->next());
139 reg_def R29 ( NS, NS, Op_RegI, 29, r29->as_VMReg() ); // fp
140 reg_def R29_H ( NS, NS, Op_RegI, 29, r29->as_VMReg()->next());
141 reg_def R30 ( NS, NS, Op_RegI, 30, r30->as_VMReg() ); // lr
142 reg_def R30_H ( NS, NS, Op_RegI, 30, r30->as_VMReg()->next());
143 reg_def R31 ( NS, NS, Op_RegI, 31, r31_sp->as_VMReg() ); // sp
144 reg_def R31_H ( NS, NS, Op_RegI, 31, r31_sp->as_VMReg()->next());
145
146 // ----------------------------
147 // Float/Double/Vector Registers
148 // ----------------------------
149
150 // Double Registers
151
152 // The rules of ADL require that double registers be defined in pairs.
153 // Each pair must be two 32-bit values, but not necessarily a pair of
154 // single float registers. In each pair, ADLC-assigned register numbers
155 // must be adjacent, with the lower number even. Finally, when the
156 // CPU stores such a register pair to memory, the word associated with
157 // the lower ADLC-assigned number must be stored to the lower address.
158
159 // AArch64 has 32 floating-point registers. Each can store a vector of
160 // single or double precision floating-point values up to 8 * 32
161 // floats, 4 * 64 bit floats or 2 * 128 bit floats. We currently only
162 // use the first float or double element of the vector.
163
164 // for Java use float registers v0-v15 are always save on call whereas
165 // the platform ABI treats v8-v15 as callee save). float registers
166 // v16-v31 are SOC as per the platform spec
167
168 // For SVE vector registers, we simply extend vector register size to 8
169 // 'logical' slots. This is nominally 256 bits but it actually covers
170 // all possible 'physical' SVE vector register lengths from 128 ~ 2048
171 // bits. The 'physical' SVE vector register length is detected during
172 // startup, so the register allocator is able to identify the correct
173 // number of bytes needed for an SVE spill/unspill.
174 // Note that a vector register with 4 slots denotes a 128-bit NEON
175 // register allowing it to be distinguished from the corresponding SVE
176 // vector register when the SVE vector length is 128 bits.
177
178 reg_def V0 ( SOC, SOC, Op_RegF, 0, v0->as_VMReg() );
179 reg_def V0_H ( SOC, SOC, Op_RegF, 0, v0->as_VMReg()->next() );
180 reg_def V0_J ( SOC, SOC, Op_RegF, 0, v0->as_VMReg()->next(2) );
181 reg_def V0_K ( SOC, SOC, Op_RegF, 0, v0->as_VMReg()->next(3) );
182
183 reg_def V1 ( SOC, SOC, Op_RegF, 1, v1->as_VMReg() );
184 reg_def V1_H ( SOC, SOC, Op_RegF, 1, v1->as_VMReg()->next() );
185 reg_def V1_J ( SOC, SOC, Op_RegF, 1, v1->as_VMReg()->next(2) );
186 reg_def V1_K ( SOC, SOC, Op_RegF, 1, v1->as_VMReg()->next(3) );
187
188 reg_def V2 ( SOC, SOC, Op_RegF, 2, v2->as_VMReg() );
189 reg_def V2_H ( SOC, SOC, Op_RegF, 2, v2->as_VMReg()->next() );
190 reg_def V2_J ( SOC, SOC, Op_RegF, 2, v2->as_VMReg()->next(2) );
191 reg_def V2_K ( SOC, SOC, Op_RegF, 2, v2->as_VMReg()->next(3) );
192
193 reg_def V3 ( SOC, SOC, Op_RegF, 3, v3->as_VMReg() );
194 reg_def V3_H ( SOC, SOC, Op_RegF, 3, v3->as_VMReg()->next() );
195 reg_def V3_J ( SOC, SOC, Op_RegF, 3, v3->as_VMReg()->next(2) );
196 reg_def V3_K ( SOC, SOC, Op_RegF, 3, v3->as_VMReg()->next(3) );
197
198 reg_def V4 ( SOC, SOC, Op_RegF, 4, v4->as_VMReg() );
199 reg_def V4_H ( SOC, SOC, Op_RegF, 4, v4->as_VMReg()->next() );
200 reg_def V4_J ( SOC, SOC, Op_RegF, 4, v4->as_VMReg()->next(2) );
201 reg_def V4_K ( SOC, SOC, Op_RegF, 4, v4->as_VMReg()->next(3) );
202
203 reg_def V5 ( SOC, SOC, Op_RegF, 5, v5->as_VMReg() );
204 reg_def V5_H ( SOC, SOC, Op_RegF, 5, v5->as_VMReg()->next() );
205 reg_def V5_J ( SOC, SOC, Op_RegF, 5, v5->as_VMReg()->next(2) );
206 reg_def V5_K ( SOC, SOC, Op_RegF, 5, v5->as_VMReg()->next(3) );
207
208 reg_def V6 ( SOC, SOC, Op_RegF, 6, v6->as_VMReg() );
209 reg_def V6_H ( SOC, SOC, Op_RegF, 6, v6->as_VMReg()->next() );
210 reg_def V6_J ( SOC, SOC, Op_RegF, 6, v6->as_VMReg()->next(2) );
211 reg_def V6_K ( SOC, SOC, Op_RegF, 6, v6->as_VMReg()->next(3) );
212
213 reg_def V7 ( SOC, SOC, Op_RegF, 7, v7->as_VMReg() );
214 reg_def V7_H ( SOC, SOC, Op_RegF, 7, v7->as_VMReg()->next() );
215 reg_def V7_J ( SOC, SOC, Op_RegF, 7, v7->as_VMReg()->next(2) );
216 reg_def V7_K ( SOC, SOC, Op_RegF, 7, v7->as_VMReg()->next(3) );
217
218 reg_def V8 ( SOC, SOE, Op_RegF, 8, v8->as_VMReg() );
219 reg_def V8_H ( SOC, SOE, Op_RegF, 8, v8->as_VMReg()->next() );
220 reg_def V8_J ( SOC, SOC, Op_RegF, 8, v8->as_VMReg()->next(2) );
221 reg_def V8_K ( SOC, SOC, Op_RegF, 8, v8->as_VMReg()->next(3) );
222
223 reg_def V9 ( SOC, SOE, Op_RegF, 9, v9->as_VMReg() );
224 reg_def V9_H ( SOC, SOE, Op_RegF, 9, v9->as_VMReg()->next() );
225 reg_def V9_J ( SOC, SOC, Op_RegF, 9, v9->as_VMReg()->next(2) );
226 reg_def V9_K ( SOC, SOC, Op_RegF, 9, v9->as_VMReg()->next(3) );
227
228 reg_def V10 ( SOC, SOE, Op_RegF, 10, v10->as_VMReg() );
229 reg_def V10_H ( SOC, SOE, Op_RegF, 10, v10->as_VMReg()->next() );
230 reg_def V10_J ( SOC, SOC, Op_RegF, 10, v10->as_VMReg()->next(2) );
231 reg_def V10_K ( SOC, SOC, Op_RegF, 10, v10->as_VMReg()->next(3) );
232
233 reg_def V11 ( SOC, SOE, Op_RegF, 11, v11->as_VMReg() );
234 reg_def V11_H ( SOC, SOE, Op_RegF, 11, v11->as_VMReg()->next() );
235 reg_def V11_J ( SOC, SOC, Op_RegF, 11, v11->as_VMReg()->next(2) );
236 reg_def V11_K ( SOC, SOC, Op_RegF, 11, v11->as_VMReg()->next(3) );
237
238 reg_def V12 ( SOC, SOE, Op_RegF, 12, v12->as_VMReg() );
239 reg_def V12_H ( SOC, SOE, Op_RegF, 12, v12->as_VMReg()->next() );
240 reg_def V12_J ( SOC, SOC, Op_RegF, 12, v12->as_VMReg()->next(2) );
241 reg_def V12_K ( SOC, SOC, Op_RegF, 12, v12->as_VMReg()->next(3) );
242
243 reg_def V13 ( SOC, SOE, Op_RegF, 13, v13->as_VMReg() );
244 reg_def V13_H ( SOC, SOE, Op_RegF, 13, v13->as_VMReg()->next() );
245 reg_def V13_J ( SOC, SOC, Op_RegF, 13, v13->as_VMReg()->next(2) );
246 reg_def V13_K ( SOC, SOC, Op_RegF, 13, v13->as_VMReg()->next(3) );
247
248 reg_def V14 ( SOC, SOE, Op_RegF, 14, v14->as_VMReg() );
249 reg_def V14_H ( SOC, SOE, Op_RegF, 14, v14->as_VMReg()->next() );
250 reg_def V14_J ( SOC, SOC, Op_RegF, 14, v14->as_VMReg()->next(2) );
251 reg_def V14_K ( SOC, SOC, Op_RegF, 14, v14->as_VMReg()->next(3) );
252
253 reg_def V15 ( SOC, SOE, Op_RegF, 15, v15->as_VMReg() );
254 reg_def V15_H ( SOC, SOE, Op_RegF, 15, v15->as_VMReg()->next() );
255 reg_def V15_J ( SOC, SOC, Op_RegF, 15, v15->as_VMReg()->next(2) );
256 reg_def V15_K ( SOC, SOC, Op_RegF, 15, v15->as_VMReg()->next(3) );
257
258 reg_def V16 ( SOC, SOC, Op_RegF, 16, v16->as_VMReg() );
259 reg_def V16_H ( SOC, SOC, Op_RegF, 16, v16->as_VMReg()->next() );
260 reg_def V16_J ( SOC, SOC, Op_RegF, 16, v16->as_VMReg()->next(2) );
261 reg_def V16_K ( SOC, SOC, Op_RegF, 16, v16->as_VMReg()->next(3) );
262
263 reg_def V17 ( SOC, SOC, Op_RegF, 17, v17->as_VMReg() );
264 reg_def V17_H ( SOC, SOC, Op_RegF, 17, v17->as_VMReg()->next() );
265 reg_def V17_J ( SOC, SOC, Op_RegF, 17, v17->as_VMReg()->next(2) );
266 reg_def V17_K ( SOC, SOC, Op_RegF, 17, v17->as_VMReg()->next(3) );
267
268 reg_def V18 ( SOC, SOC, Op_RegF, 18, v18->as_VMReg() );
269 reg_def V18_H ( SOC, SOC, Op_RegF, 18, v18->as_VMReg()->next() );
270 reg_def V18_J ( SOC, SOC, Op_RegF, 18, v18->as_VMReg()->next(2) );
271 reg_def V18_K ( SOC, SOC, Op_RegF, 18, v18->as_VMReg()->next(3) );
272
273 reg_def V19 ( SOC, SOC, Op_RegF, 19, v19->as_VMReg() );
274 reg_def V19_H ( SOC, SOC, Op_RegF, 19, v19->as_VMReg()->next() );
275 reg_def V19_J ( SOC, SOC, Op_RegF, 19, v19->as_VMReg()->next(2) );
276 reg_def V19_K ( SOC, SOC, Op_RegF, 19, v19->as_VMReg()->next(3) );
277
278 reg_def V20 ( SOC, SOC, Op_RegF, 20, v20->as_VMReg() );
279 reg_def V20_H ( SOC, SOC, Op_RegF, 20, v20->as_VMReg()->next() );
280 reg_def V20_J ( SOC, SOC, Op_RegF, 20, v20->as_VMReg()->next(2) );
281 reg_def V20_K ( SOC, SOC, Op_RegF, 20, v20->as_VMReg()->next(3) );
282
283 reg_def V21 ( SOC, SOC, Op_RegF, 21, v21->as_VMReg() );
284 reg_def V21_H ( SOC, SOC, Op_RegF, 21, v21->as_VMReg()->next() );
285 reg_def V21_J ( SOC, SOC, Op_RegF, 21, v21->as_VMReg()->next(2) );
286 reg_def V21_K ( SOC, SOC, Op_RegF, 21, v21->as_VMReg()->next(3) );
287
288 reg_def V22 ( SOC, SOC, Op_RegF, 22, v22->as_VMReg() );
289 reg_def V22_H ( SOC, SOC, Op_RegF, 22, v22->as_VMReg()->next() );
290 reg_def V22_J ( SOC, SOC, Op_RegF, 22, v22->as_VMReg()->next(2) );
291 reg_def V22_K ( SOC, SOC, Op_RegF, 22, v22->as_VMReg()->next(3) );
292
293 reg_def V23 ( SOC, SOC, Op_RegF, 23, v23->as_VMReg() );
294 reg_def V23_H ( SOC, SOC, Op_RegF, 23, v23->as_VMReg()->next() );
295 reg_def V23_J ( SOC, SOC, Op_RegF, 23, v23->as_VMReg()->next(2) );
296 reg_def V23_K ( SOC, SOC, Op_RegF, 23, v23->as_VMReg()->next(3) );
297
298 reg_def V24 ( SOC, SOC, Op_RegF, 24, v24->as_VMReg() );
299 reg_def V24_H ( SOC, SOC, Op_RegF, 24, v24->as_VMReg()->next() );
300 reg_def V24_J ( SOC, SOC, Op_RegF, 24, v24->as_VMReg()->next(2) );
301 reg_def V24_K ( SOC, SOC, Op_RegF, 24, v24->as_VMReg()->next(3) );
302
303 reg_def V25 ( SOC, SOC, Op_RegF, 25, v25->as_VMReg() );
304 reg_def V25_H ( SOC, SOC, Op_RegF, 25, v25->as_VMReg()->next() );
305 reg_def V25_J ( SOC, SOC, Op_RegF, 25, v25->as_VMReg()->next(2) );
306 reg_def V25_K ( SOC, SOC, Op_RegF, 25, v25->as_VMReg()->next(3) );
307
308 reg_def V26 ( SOC, SOC, Op_RegF, 26, v26->as_VMReg() );
309 reg_def V26_H ( SOC, SOC, Op_RegF, 26, v26->as_VMReg()->next() );
310 reg_def V26_J ( SOC, SOC, Op_RegF, 26, v26->as_VMReg()->next(2) );
311 reg_def V26_K ( SOC, SOC, Op_RegF, 26, v26->as_VMReg()->next(3) );
312
313 reg_def V27 ( SOC, SOC, Op_RegF, 27, v27->as_VMReg() );
314 reg_def V27_H ( SOC, SOC, Op_RegF, 27, v27->as_VMReg()->next() );
315 reg_def V27_J ( SOC, SOC, Op_RegF, 27, v27->as_VMReg()->next(2) );
316 reg_def V27_K ( SOC, SOC, Op_RegF, 27, v27->as_VMReg()->next(3) );
317
318 reg_def V28 ( SOC, SOC, Op_RegF, 28, v28->as_VMReg() );
319 reg_def V28_H ( SOC, SOC, Op_RegF, 28, v28->as_VMReg()->next() );
320 reg_def V28_J ( SOC, SOC, Op_RegF, 28, v28->as_VMReg()->next(2) );
321 reg_def V28_K ( SOC, SOC, Op_RegF, 28, v28->as_VMReg()->next(3) );
322
323 reg_def V29 ( SOC, SOC, Op_RegF, 29, v29->as_VMReg() );
324 reg_def V29_H ( SOC, SOC, Op_RegF, 29, v29->as_VMReg()->next() );
325 reg_def V29_J ( SOC, SOC, Op_RegF, 29, v29->as_VMReg()->next(2) );
326 reg_def V29_K ( SOC, SOC, Op_RegF, 29, v29->as_VMReg()->next(3) );
327
328 reg_def V30 ( SOC, SOC, Op_RegF, 30, v30->as_VMReg() );
329 reg_def V30_H ( SOC, SOC, Op_RegF, 30, v30->as_VMReg()->next() );
330 reg_def V30_J ( SOC, SOC, Op_RegF, 30, v30->as_VMReg()->next(2) );
331 reg_def V30_K ( SOC, SOC, Op_RegF, 30, v30->as_VMReg()->next(3) );
332
333 reg_def V31 ( SOC, SOC, Op_RegF, 31, v31->as_VMReg() );
334 reg_def V31_H ( SOC, SOC, Op_RegF, 31, v31->as_VMReg()->next() );
335 reg_def V31_J ( SOC, SOC, Op_RegF, 31, v31->as_VMReg()->next(2) );
336 reg_def V31_K ( SOC, SOC, Op_RegF, 31, v31->as_VMReg()->next(3) );
337
338 // ----------------------------
339 // SVE Predicate Registers
340 // ----------------------------
341 reg_def P0 (SOC, SOC, Op_RegVectMask, 0, p0->as_VMReg());
342 reg_def P1 (SOC, SOC, Op_RegVectMask, 1, p1->as_VMReg());
343 reg_def P2 (SOC, SOC, Op_RegVectMask, 2, p2->as_VMReg());
344 reg_def P3 (SOC, SOC, Op_RegVectMask, 3, p3->as_VMReg());
345 reg_def P4 (SOC, SOC, Op_RegVectMask, 4, p4->as_VMReg());
346 reg_def P5 (SOC, SOC, Op_RegVectMask, 5, p5->as_VMReg());
347 reg_def P6 (SOC, SOC, Op_RegVectMask, 6, p6->as_VMReg());
348 reg_def P7 (SOC, SOC, Op_RegVectMask, 7, p7->as_VMReg());
349 reg_def P8 (SOC, SOC, Op_RegVectMask, 8, p8->as_VMReg());
350 reg_def P9 (SOC, SOC, Op_RegVectMask, 9, p9->as_VMReg());
351 reg_def P10 (SOC, SOC, Op_RegVectMask, 10, p10->as_VMReg());
352 reg_def P11 (SOC, SOC, Op_RegVectMask, 11, p11->as_VMReg());
353 reg_def P12 (SOC, SOC, Op_RegVectMask, 12, p12->as_VMReg());
354 reg_def P13 (SOC, SOC, Op_RegVectMask, 13, p13->as_VMReg());
355 reg_def P14 (SOC, SOC, Op_RegVectMask, 14, p14->as_VMReg());
356 reg_def P15 (SOC, SOC, Op_RegVectMask, 15, p15->as_VMReg());
357
358 // ----------------------------
359 // Special Registers
360 // ----------------------------
361
362 // the AArch64 CSPR status flag register is not directly accessible as
363 // instruction operand. the FPSR status flag register is a system
364 // register which can be written/read using MSR/MRS but again does not
365 // appear as an operand (a code identifying the FSPR occurs as an
366 // immediate value in the instruction).
367
368 reg_def RFLAGS(SOC, SOC, 0, 32, VMRegImpl::Bad());
369
370 // Specify priority of register selection within phases of register
371 // allocation. Highest priority is first. A useful heuristic is to
372 // give registers a low priority when they are required by machine
373 // instructions, like EAX and EDX on I486, and choose no-save registers
374 // before save-on-call, & save-on-call before save-on-entry. Registers
375 // which participate in fixed calling sequences should come last.
376 // Registers which are used as pairs must fall on an even boundary.
377
378 alloc_class chunk0(
379 // volatiles
380 R10, R10_H,
381 R11, R11_H,
382 R12, R12_H,
383 R13, R13_H,
384 R14, R14_H,
385 R15, R15_H,
386 R16, R16_H,
387 R17, R17_H,
388 R18, R18_H,
389
390 // arg registers
391 R0, R0_H,
392 R1, R1_H,
393 R2, R2_H,
394 R3, R3_H,
395 R4, R4_H,
396 R5, R5_H,
397 R6, R6_H,
398 R7, R7_H,
399
400 // non-volatiles
401 R19, R19_H,
402 R20, R20_H,
403 R21, R21_H,
404 R22, R22_H,
405 R23, R23_H,
406 R24, R24_H,
407 R25, R25_H,
408 R26, R26_H,
409
410 // non-allocatable registers
411
412 R27, R27_H, // heapbase
413 R28, R28_H, // thread
414 R29, R29_H, // fp
415 R30, R30_H, // lr
416 R31, R31_H, // sp
417 R8, R8_H, // rscratch1
418 R9, R9_H, // rscratch2
419 );
420
421 alloc_class chunk1(
422
423 // no save
424 V16, V16_H, V16_J, V16_K,
425 V17, V17_H, V17_J, V17_K,
426 V18, V18_H, V18_J, V18_K,
427 V19, V19_H, V19_J, V19_K,
428 V20, V20_H, V20_J, V20_K,
429 V21, V21_H, V21_J, V21_K,
430 V22, V22_H, V22_J, V22_K,
431 V23, V23_H, V23_J, V23_K,
432 V24, V24_H, V24_J, V24_K,
433 V25, V25_H, V25_J, V25_K,
434 V26, V26_H, V26_J, V26_K,
435 V27, V27_H, V27_J, V27_K,
436 V28, V28_H, V28_J, V28_K,
437 V29, V29_H, V29_J, V29_K,
438 V30, V30_H, V30_J, V30_K,
439 V31, V31_H, V31_J, V31_K,
440
441 // arg registers
442 V0, V0_H, V0_J, V0_K,
443 V1, V1_H, V1_J, V1_K,
444 V2, V2_H, V2_J, V2_K,
445 V3, V3_H, V3_J, V3_K,
446 V4, V4_H, V4_J, V4_K,
447 V5, V5_H, V5_J, V5_K,
448 V6, V6_H, V6_J, V6_K,
449 V7, V7_H, V7_J, V7_K,
450
451 // non-volatiles
452 V8, V8_H, V8_J, V8_K,
453 V9, V9_H, V9_J, V9_K,
454 V10, V10_H, V10_J, V10_K,
455 V11, V11_H, V11_J, V11_K,
456 V12, V12_H, V12_J, V12_K,
457 V13, V13_H, V13_J, V13_K,
458 V14, V14_H, V14_J, V14_K,
459 V15, V15_H, V15_J, V15_K,
460 );
461
462 alloc_class chunk2 (
463 // Governing predicates for load/store and arithmetic
464 P0,
465 P1,
466 P2,
467 P3,
468 P4,
469 P5,
470 P6,
471
472 // Extra predicates
473 P8,
474 P9,
475 P10,
476 P11,
477 P12,
478 P13,
479 P14,
480 P15,
481
482 // Preserved for all-true predicate
483 P7,
484 );
485
486 alloc_class chunk3(RFLAGS);
487
488 //----------Architecture Description Register Classes--------------------------
489 // Several register classes are automatically defined based upon information in
490 // this architecture description.
491 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
492 // 2) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
493 //
494
495 // Class for all 32 bit general purpose registers
496 reg_class all_reg32(
497 R0,
498 R1,
499 R2,
500 R3,
501 R4,
502 R5,
503 R6,
504 R7,
505 R10,
506 R11,
507 R12,
508 R13,
509 R14,
510 R15,
511 R16,
512 R17,
513 R18,
514 R19,
515 R20,
516 R21,
517 R22,
518 R23,
519 R24,
520 R25,
521 R26,
522 R27,
523 R28,
524 R29,
525 R30,
526 R31
527 );
528
529
530 // Class for all 32 bit integer registers (excluding SP which
531 // will never be used as an integer register)
532 reg_class any_reg32 %{
533 return _ANY_REG32_mask;
534 %}
535
536 // Singleton class for R0 int register
537 reg_class int_r0_reg(R0);
538
539 // Singleton class for R2 int register
540 reg_class int_r2_reg(R2);
541
542 // Singleton class for R3 int register
543 reg_class int_r3_reg(R3);
544
545 // Singleton class for R4 int register
546 reg_class int_r4_reg(R4);
547
548 // Singleton class for R31 int register
549 reg_class int_r31_reg(R31);
550
551 // Class for all 64 bit general purpose registers
552 reg_class all_reg(
553 R0, R0_H,
554 R1, R1_H,
555 R2, R2_H,
556 R3, R3_H,
557 R4, R4_H,
558 R5, R5_H,
559 R6, R6_H,
560 R7, R7_H,
561 R10, R10_H,
562 R11, R11_H,
563 R12, R12_H,
564 R13, R13_H,
565 R14, R14_H,
566 R15, R15_H,
567 R16, R16_H,
568 R17, R17_H,
569 R18, R18_H,
570 R19, R19_H,
571 R20, R20_H,
572 R21, R21_H,
573 R22, R22_H,
574 R23, R23_H,
575 R24, R24_H,
576 R25, R25_H,
577 R26, R26_H,
578 R27, R27_H,
579 R28, R28_H,
580 R29, R29_H,
581 R30, R30_H,
582 R31, R31_H
583 );
584
585 // Class for all long integer registers (including SP)
586 reg_class any_reg %{
587 return _ANY_REG_mask;
588 %}
589
590 // Class for non-allocatable 32 bit registers
591 reg_class non_allocatable_reg32(
592 #ifdef R18_RESERVED
593 // See comment in register_aarch64.hpp
594 R18, // tls on Windows
595 #endif
596 R28, // thread
597 R30, // lr
598 R31 // sp
599 );
600
601 // Class for non-allocatable 64 bit registers
602 reg_class non_allocatable_reg(
603 #ifdef R18_RESERVED
604 // See comment in register_aarch64.hpp
605 R18, R18_H, // tls on Windows, platform register on macOS
606 #endif
607 R28, R28_H, // thread
608 R30, R30_H, // lr
609 R31, R31_H // sp
610 );
611
612 // Class for all non-special integer registers
613 reg_class no_special_reg32 %{
614 return _NO_SPECIAL_REG32_mask;
615 %}
616
617 // Class for all non-special long integer registers
618 reg_class no_special_reg %{
619 return _NO_SPECIAL_REG_mask;
620 %}
621
622 // Class for 64 bit register r0
623 reg_class r0_reg(
624 R0, R0_H
625 );
626
627 // Class for 64 bit register r1
628 reg_class r1_reg(
629 R1, R1_H
630 );
631
632 // Class for 64 bit register r2
633 reg_class r2_reg(
634 R2, R2_H
635 );
636
637 // Class for 64 bit register r3
638 reg_class r3_reg(
639 R3, R3_H
640 );
641
642 // Class for 64 bit register r4
643 reg_class r4_reg(
644 R4, R4_H
645 );
646
647 // Class for 64 bit register r5
648 reg_class r5_reg(
649 R5, R5_H
650 );
651
652 // Class for 64 bit register r10
653 reg_class r10_reg(
654 R10, R10_H
655 );
656
657 // Class for 64 bit register r11
658 reg_class r11_reg(
659 R11, R11_H
660 );
661
662 // Class for method register
663 reg_class method_reg(
664 R12, R12_H
665 );
666
667 // Class for thread register
668 reg_class thread_reg(
669 R28, R28_H
670 );
671
672 // Class for frame pointer register
673 reg_class fp_reg(
674 R29, R29_H
675 );
676
677 // Class for link register
678 reg_class lr_reg(
679 R30, R30_H
680 );
681
682 // Class for long sp register
683 reg_class sp_reg(
684 R31, R31_H
685 );
686
687 // Class for all pointer registers
688 reg_class ptr_reg %{
689 return _PTR_REG_mask;
690 %}
691
692 // Class for all non_special pointer registers
693 reg_class no_special_ptr_reg %{
694 return _NO_SPECIAL_PTR_REG_mask;
695 %}
696
697 // Class for all float registers
698 reg_class float_reg(
699 V0,
700 V1,
701 V2,
702 V3,
703 V4,
704 V5,
705 V6,
706 V7,
707 V8,
708 V9,
709 V10,
710 V11,
711 V12,
712 V13,
713 V14,
714 V15,
715 V16,
716 V17,
717 V18,
718 V19,
719 V20,
720 V21,
721 V22,
722 V23,
723 V24,
724 V25,
725 V26,
726 V27,
727 V28,
728 V29,
729 V30,
730 V31
731 );
732
733 // Double precision float registers have virtual `high halves' that
734 // are needed by the allocator.
735 // Class for all double registers
736 reg_class double_reg(
737 V0, V0_H,
738 V1, V1_H,
739 V2, V2_H,
740 V3, V3_H,
741 V4, V4_H,
742 V5, V5_H,
743 V6, V6_H,
744 V7, V7_H,
745 V8, V8_H,
746 V9, V9_H,
747 V10, V10_H,
748 V11, V11_H,
749 V12, V12_H,
750 V13, V13_H,
751 V14, V14_H,
752 V15, V15_H,
753 V16, V16_H,
754 V17, V17_H,
755 V18, V18_H,
756 V19, V19_H,
757 V20, V20_H,
758 V21, V21_H,
759 V22, V22_H,
760 V23, V23_H,
761 V24, V24_H,
762 V25, V25_H,
763 V26, V26_H,
764 V27, V27_H,
765 V28, V28_H,
766 V29, V29_H,
767 V30, V30_H,
768 V31, V31_H
769 );
770
771 // Class for all SVE vector registers.
772 reg_class vectora_reg (
773 V0, V0_H, V0_J, V0_K,
774 V1, V1_H, V1_J, V1_K,
775 V2, V2_H, V2_J, V2_K,
776 V3, V3_H, V3_J, V3_K,
777 V4, V4_H, V4_J, V4_K,
778 V5, V5_H, V5_J, V5_K,
779 V6, V6_H, V6_J, V6_K,
780 V7, V7_H, V7_J, V7_K,
781 V8, V8_H, V8_J, V8_K,
782 V9, V9_H, V9_J, V9_K,
783 V10, V10_H, V10_J, V10_K,
784 V11, V11_H, V11_J, V11_K,
785 V12, V12_H, V12_J, V12_K,
786 V13, V13_H, V13_J, V13_K,
787 V14, V14_H, V14_J, V14_K,
788 V15, V15_H, V15_J, V15_K,
789 V16, V16_H, V16_J, V16_K,
790 V17, V17_H, V17_J, V17_K,
791 V18, V18_H, V18_J, V18_K,
792 V19, V19_H, V19_J, V19_K,
793 V20, V20_H, V20_J, V20_K,
794 V21, V21_H, V21_J, V21_K,
795 V22, V22_H, V22_J, V22_K,
796 V23, V23_H, V23_J, V23_K,
797 V24, V24_H, V24_J, V24_K,
798 V25, V25_H, V25_J, V25_K,
799 V26, V26_H, V26_J, V26_K,
800 V27, V27_H, V27_J, V27_K,
801 V28, V28_H, V28_J, V28_K,
802 V29, V29_H, V29_J, V29_K,
803 V30, V30_H, V30_J, V30_K,
804 V31, V31_H, V31_J, V31_K,
805 );
806
807 // Class for all 64bit vector registers
808 reg_class vectord_reg(
809 V0, V0_H,
810 V1, V1_H,
811 V2, V2_H,
812 V3, V3_H,
813 V4, V4_H,
814 V5, V5_H,
815 V6, V6_H,
816 V7, V7_H,
817 V8, V8_H,
818 V9, V9_H,
819 V10, V10_H,
820 V11, V11_H,
821 V12, V12_H,
822 V13, V13_H,
823 V14, V14_H,
824 V15, V15_H,
825 V16, V16_H,
826 V17, V17_H,
827 V18, V18_H,
828 V19, V19_H,
829 V20, V20_H,
830 V21, V21_H,
831 V22, V22_H,
832 V23, V23_H,
833 V24, V24_H,
834 V25, V25_H,
835 V26, V26_H,
836 V27, V27_H,
837 V28, V28_H,
838 V29, V29_H,
839 V30, V30_H,
840 V31, V31_H
841 );
842
843 // Class for all 128bit vector registers
844 reg_class vectorx_reg(
845 V0, V0_H, V0_J, V0_K,
846 V1, V1_H, V1_J, V1_K,
847 V2, V2_H, V2_J, V2_K,
848 V3, V3_H, V3_J, V3_K,
849 V4, V4_H, V4_J, V4_K,
850 V5, V5_H, V5_J, V5_K,
851 V6, V6_H, V6_J, V6_K,
852 V7, V7_H, V7_J, V7_K,
853 V8, V8_H, V8_J, V8_K,
854 V9, V9_H, V9_J, V9_K,
855 V10, V10_H, V10_J, V10_K,
856 V11, V11_H, V11_J, V11_K,
857 V12, V12_H, V12_J, V12_K,
858 V13, V13_H, V13_J, V13_K,
859 V14, V14_H, V14_J, V14_K,
860 V15, V15_H, V15_J, V15_K,
861 V16, V16_H, V16_J, V16_K,
862 V17, V17_H, V17_J, V17_K,
863 V18, V18_H, V18_J, V18_K,
864 V19, V19_H, V19_J, V19_K,
865 V20, V20_H, V20_J, V20_K,
866 V21, V21_H, V21_J, V21_K,
867 V22, V22_H, V22_J, V22_K,
868 V23, V23_H, V23_J, V23_K,
869 V24, V24_H, V24_J, V24_K,
870 V25, V25_H, V25_J, V25_K,
871 V26, V26_H, V26_J, V26_K,
872 V27, V27_H, V27_J, V27_K,
873 V28, V28_H, V28_J, V28_K,
874 V29, V29_H, V29_J, V29_K,
875 V30, V30_H, V30_J, V30_K,
876 V31, V31_H, V31_J, V31_K
877 );
878
879 // Class for 128 bit register v0
880 reg_class v0_reg(
881 V0, V0_H
882 );
883
884 // Class for 128 bit register v1
885 reg_class v1_reg(
886 V1, V1_H
887 );
888
889 // Class for 128 bit register v2
890 reg_class v2_reg(
891 V2, V2_H
892 );
893
894 // Class for 128 bit register v3
895 reg_class v3_reg(
896 V3, V3_H
897 );
898
899 // Class for 128 bit register v4
900 reg_class v4_reg(
901 V4, V4_H
902 );
903
904 // Class for 128 bit register v5
905 reg_class v5_reg(
906 V5, V5_H
907 );
908
909 // Class for 128 bit register v6
910 reg_class v6_reg(
911 V6, V6_H
912 );
913
914 // Class for 128 bit register v7
915 reg_class v7_reg(
916 V7, V7_H
917 );
918
919 // Class for 128 bit register v8
920 reg_class v8_reg(
921 V8, V8_H
922 );
923
924 // Class for 128 bit register v9
925 reg_class v9_reg(
926 V9, V9_H
927 );
928
929 // Class for 128 bit register v10
930 reg_class v10_reg(
931 V10, V10_H
932 );
933
934 // Class for 128 bit register v11
935 reg_class v11_reg(
936 V11, V11_H
937 );
938
939 // Class for 128 bit register v12
940 reg_class v12_reg(
941 V12, V12_H
942 );
943
944 // Class for 128 bit register v13
945 reg_class v13_reg(
946 V13, V13_H
947 );
948
949 // Class for 128 bit register v14
950 reg_class v14_reg(
951 V14, V14_H
952 );
953
954 // Class for 128 bit register v15
955 reg_class v15_reg(
956 V15, V15_H
957 );
958
959 // Class for 128 bit register v16
960 reg_class v16_reg(
961 V16, V16_H
962 );
963
964 // Class for 128 bit register v17
965 reg_class v17_reg(
966 V17, V17_H
967 );
968
969 // Class for 128 bit register v18
970 reg_class v18_reg(
971 V18, V18_H
972 );
973
974 // Class for 128 bit register v19
975 reg_class v19_reg(
976 V19, V19_H
977 );
978
979 // Class for 128 bit register v20
980 reg_class v20_reg(
981 V20, V20_H
982 );
983
984 // Class for 128 bit register v21
985 reg_class v21_reg(
986 V21, V21_H
987 );
988
989 // Class for 128 bit register v22
990 reg_class v22_reg(
991 V22, V22_H
992 );
993
994 // Class for 128 bit register v23
995 reg_class v23_reg(
996 V23, V23_H
997 );
998
999 // Class for 128 bit register v24
1000 reg_class v24_reg(
1001 V24, V24_H
1002 );
1003
1004 // Class for 128 bit register v25
1005 reg_class v25_reg(
1006 V25, V25_H
1007 );
1008
1009 // Class for 128 bit register v26
1010 reg_class v26_reg(
1011 V26, V26_H
1012 );
1013
1014 // Class for 128 bit register v27
1015 reg_class v27_reg(
1016 V27, V27_H
1017 );
1018
1019 // Class for 128 bit register v28
1020 reg_class v28_reg(
1021 V28, V28_H
1022 );
1023
1024 // Class for 128 bit register v29
1025 reg_class v29_reg(
1026 V29, V29_H
1027 );
1028
1029 // Class for 128 bit register v30
1030 reg_class v30_reg(
1031 V30, V30_H
1032 );
1033
1034 // Class for 128 bit register v31
1035 reg_class v31_reg(
1036 V31, V31_H
1037 );
1038
1039 // Class for all SVE predicate registers.
1040 reg_class pr_reg (
1041 P0,
1042 P1,
1043 P2,
1044 P3,
1045 P4,
1046 P5,
1047 P6,
1048 // P7, non-allocatable, preserved with all elements preset to TRUE.
1049 P8,
1050 P9,
1051 P10,
1052 P11,
1053 P12,
1054 P13,
1055 P14,
1056 P15
1057 );
1058
1059 // Class for SVE governing predicate registers, which are used
1060 // to determine the active elements of a predicated instruction.
1061 reg_class gov_pr (
1062 P0,
1063 P1,
1064 P2,
1065 P3,
1066 P4,
1067 P5,
1068 P6,
1069 // P7, non-allocatable, preserved with all elements preset to TRUE.
1070 );
1071
1072 reg_class p0_reg(P0);
1073 reg_class p1_reg(P1);
1074
1075 // Singleton class for condition codes
1076 reg_class int_flags(RFLAGS);
1077
1078 %}
1079
1080 //----------DEFINITION BLOCK---------------------------------------------------
1081 // Define name --> value mappings to inform the ADLC of an integer valued name
1082 // Current support includes integer values in the range [0, 0x7FFFFFFF]
1083 // Format:
1084 // int_def <name> ( <int_value>, <expression>);
1085 // Generated Code in ad_<arch>.hpp
1086 // #define <name> (<expression>)
1087 // // value == <int_value>
1088 // Generated code in ad_<arch>.cpp adlc_verification()
1089 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
1090 //
1091
1092 // we follow the ppc-aix port in using a simple cost model which ranks
1093 // register operations as cheap, memory ops as more expensive and
1094 // branches as most expensive. the first two have a low as well as a
1095 // normal cost. huge cost appears to be a way of saying don't do
1096 // something
1097
1098 definitions %{
1099 // The default cost (of a register move instruction).
1100 int_def INSN_COST ( 100, 100);
1101 int_def BRANCH_COST ( 200, 2 * INSN_COST);
1102 int_def CALL_COST ( 200, 2 * INSN_COST);
1103 int_def VOLATILE_REF_COST ( 1000, 10 * INSN_COST);
1104 %}
1105
1106
1107 //----------SOURCE BLOCK-------------------------------------------------------
1108 // This is a block of C++ code which provides values, functions, and
1109 // definitions necessary in the rest of the architecture description
1110
1111 source_hpp %{
1112
1113 #include "asm/macroAssembler.hpp"
1114 #include "gc/shared/barrierSetAssembler.hpp"
1115 #include "gc/shared/cardTable.hpp"
1116 #include "gc/shared/cardTableBarrierSet.hpp"
1117 #include "gc/shared/collectedHeap.hpp"
1118 #include "opto/addnode.hpp"
1119 #include "opto/convertnode.hpp"
1120 #include "runtime/objectMonitor.hpp"
1121
1122 extern RegMask _ANY_REG32_mask;
1123 extern RegMask _ANY_REG_mask;
1124 extern RegMask _PTR_REG_mask;
1125 extern RegMask _NO_SPECIAL_REG32_mask;
1126 extern RegMask _NO_SPECIAL_REG_mask;
1127 extern RegMask _NO_SPECIAL_PTR_REG_mask;
1128
1129 class CallStubImpl {
1130
1131 //--------------------------------------------------------------
1132 //---< Used for optimization in Compile::shorten_branches >---
1133 //--------------------------------------------------------------
1134
1135 public:
1136 // Size of call trampoline stub.
1137 static uint size_call_trampoline() {
1138 return 0; // no call trampolines on this platform
1139 }
1140
1141 // number of relocations needed by a call trampoline stub
1142 static uint reloc_call_trampoline() {
1143 return 0; // no call trampolines on this platform
1144 }
1145 };
1146
1147 class HandlerImpl {
1148
1149 public:
1150
1151 static int emit_exception_handler(CodeBuffer &cbuf);
1152 static int emit_deopt_handler(CodeBuffer& cbuf);
1153
1154 static uint size_exception_handler() {
1155 return MacroAssembler::far_codestub_branch_size();
1156 }
1157
1158 static uint size_deopt_handler() {
1159 // count one adr and one far branch instruction
1160 return NativeInstruction::instruction_size + MacroAssembler::far_codestub_branch_size();
1161 }
1162 };
1163
1164 class Node::PD {
1165 public:
1166 enum NodeFlags {
1167 _last_flag = Node::_last_flag
1168 };
1169 };
1170
1171 bool is_CAS(int opcode, bool maybe_volatile);
1172
1173 // predicates controlling emit of ldr<x>/ldar<x> and associated dmb
1174
1175 bool unnecessary_acquire(const Node *barrier);
1176 bool needs_acquiring_load(const Node *load);
1177
1178 // predicates controlling emit of str<x>/stlr<x> and associated dmbs
1179
1180 bool unnecessary_release(const Node *barrier);
1181 bool unnecessary_volatile(const Node *barrier);
1182 bool needs_releasing_store(const Node *store);
1183
1184 // predicate controlling translation of CompareAndSwapX
1185 bool needs_acquiring_load_exclusive(const Node *load);
1186
1187 // predicate controlling addressing modes
1188 bool size_fits_all_mem_uses(AddPNode* addp, int shift);
1189
1190 // Convert BootTest condition to Assembler condition.
1191 // Replicate the logic of cmpOpOper::ccode() and cmpOpUOper::ccode().
1192 Assembler::Condition to_assembler_cond(BoolTest::mask cond);
1193 %}
1194
1195 source %{
1196
1197 // Derived RegMask with conditionally allocatable registers
1198
1199 void PhaseOutput::pd_perform_mach_node_analysis() {
1200 }
1201
1202 int MachNode::pd_alignment_required() const {
1203 return 1;
1204 }
1205
1206 int MachNode::compute_padding(int current_offset) const {
1207 return 0;
1208 }
1209
1210 RegMask _ANY_REG32_mask;
1211 RegMask _ANY_REG_mask;
1212 RegMask _PTR_REG_mask;
1213 RegMask _NO_SPECIAL_REG32_mask;
1214 RegMask _NO_SPECIAL_REG_mask;
1215 RegMask _NO_SPECIAL_PTR_REG_mask;
1216
1217 void reg_mask_init() {
1218 // We derive below RegMask(s) from the ones which are auto-generated from
1219 // adlc register classes to make AArch64 rheapbase (r27) and rfp (r29)
1220 // registers conditionally reserved.
1221
1222 _ANY_REG32_mask = _ALL_REG32_mask;
1223 _ANY_REG32_mask.Remove(OptoReg::as_OptoReg(r31_sp->as_VMReg()));
1224
1225 _ANY_REG_mask = _ALL_REG_mask;
1226
1227 _PTR_REG_mask = _ALL_REG_mask;
1228
1229 _NO_SPECIAL_REG32_mask = _ALL_REG32_mask;
1230 _NO_SPECIAL_REG32_mask.SUBTRACT(_NON_ALLOCATABLE_REG32_mask);
1231
1232 _NO_SPECIAL_REG_mask = _ALL_REG_mask;
1233 _NO_SPECIAL_REG_mask.SUBTRACT(_NON_ALLOCATABLE_REG_mask);
1234
1235 _NO_SPECIAL_PTR_REG_mask = _ALL_REG_mask;
1236 _NO_SPECIAL_PTR_REG_mask.SUBTRACT(_NON_ALLOCATABLE_REG_mask);
1237
1238 // r27 is not allocatable when compressed oops is on and heapbase is not
1239 // zero, compressed klass pointers doesn't use r27 after JDK-8234794
1240 if (UseCompressedOops && (CompressedOops::ptrs_base() != NULL)) {
1241 _NO_SPECIAL_REG32_mask.Remove(OptoReg::as_OptoReg(r27->as_VMReg()));
1242 _NO_SPECIAL_REG_mask.Remove(OptoReg::as_OptoReg(r27->as_VMReg()));
1243 _NO_SPECIAL_PTR_REG_mask.Remove(OptoReg::as_OptoReg(r27->as_VMReg()));
1244 }
1245
1246 // r29 is not allocatable when PreserveFramePointer is on
1247 if (PreserveFramePointer) {
1248 _NO_SPECIAL_REG32_mask.Remove(OptoReg::as_OptoReg(r29->as_VMReg()));
1249 _NO_SPECIAL_REG_mask.Remove(OptoReg::as_OptoReg(r29->as_VMReg()));
1250 _NO_SPECIAL_PTR_REG_mask.Remove(OptoReg::as_OptoReg(r29->as_VMReg()));
1251 }
1252 }
1253
1254 // Optimizaton of volatile gets and puts
1255 // -------------------------------------
1256 //
1257 // AArch64 has ldar<x> and stlr<x> instructions which we can safely
1258 // use to implement volatile reads and writes. For a volatile read
1259 // we simply need
1260 //
1261 // ldar<x>
1262 //
1263 // and for a volatile write we need
1264 //
1265 // stlr<x>
1266 //
1267 // Alternatively, we can implement them by pairing a normal
1268 // load/store with a memory barrier. For a volatile read we need
1269 //
1270 // ldr<x>
1271 // dmb ishld
1272 //
1273 // for a volatile write
1274 //
1275 // dmb ish
1276 // str<x>
1277 // dmb ish
1278 //
1279 // We can also use ldaxr and stlxr to implement compare and swap CAS
1280 // sequences. These are normally translated to an instruction
1281 // sequence like the following
1282 //
1283 // dmb ish
1284 // retry:
1285 // ldxr<x> rval raddr
1286 // cmp rval rold
1287 // b.ne done
1288 // stlxr<x> rval, rnew, rold
1289 // cbnz rval retry
1290 // done:
1291 // cset r0, eq
1292 // dmb ishld
1293 //
1294 // Note that the exclusive store is already using an stlxr
1295 // instruction. That is required to ensure visibility to other
1296 // threads of the exclusive write (assuming it succeeds) before that
1297 // of any subsequent writes.
1298 //
1299 // The following instruction sequence is an improvement on the above
1300 //
1301 // retry:
1302 // ldaxr<x> rval raddr
1303 // cmp rval rold
1304 // b.ne done
1305 // stlxr<x> rval, rnew, rold
1306 // cbnz rval retry
1307 // done:
1308 // cset r0, eq
1309 //
1310 // We don't need the leading dmb ish since the stlxr guarantees
1311 // visibility of prior writes in the case that the swap is
1312 // successful. Crucially we don't have to worry about the case where
1313 // the swap is not successful since no valid program should be
1314 // relying on visibility of prior changes by the attempting thread
1315 // in the case where the CAS fails.
1316 //
1317 // Similarly, we don't need the trailing dmb ishld if we substitute
1318 // an ldaxr instruction since that will provide all the guarantees we
1319 // require regarding observation of changes made by other threads
1320 // before any change to the CAS address observed by the load.
1321 //
1322 // In order to generate the desired instruction sequence we need to
1323 // be able to identify specific 'signature' ideal graph node
1324 // sequences which i) occur as a translation of a volatile reads or
1325 // writes or CAS operations and ii) do not occur through any other
1326 // translation or graph transformation. We can then provide
1327 // alternative aldc matching rules which translate these node
1328 // sequences to the desired machine code sequences. Selection of the
1329 // alternative rules can be implemented by predicates which identify
1330 // the relevant node sequences.
1331 //
1332 // The ideal graph generator translates a volatile read to the node
1333 // sequence
1334 //
1335 // LoadX[mo_acquire]
1336 // MemBarAcquire
1337 //
1338 // As a special case when using the compressed oops optimization we
1339 // may also see this variant
1340 //
1341 // LoadN[mo_acquire]
1342 // DecodeN
1343 // MemBarAcquire
1344 //
1345 // A volatile write is translated to the node sequence
1346 //
1347 // MemBarRelease
1348 // StoreX[mo_release] {CardMark}-optional
1349 // MemBarVolatile
1350 //
1351 // n.b. the above node patterns are generated with a strict
1352 // 'signature' configuration of input and output dependencies (see
1353 // the predicates below for exact details). The card mark may be as
1354 // simple as a few extra nodes or, in a few GC configurations, may
1355 // include more complex control flow between the leading and
1356 // trailing memory barriers. However, whatever the card mark
1357 // configuration these signatures are unique to translated volatile
1358 // reads/stores -- they will not appear as a result of any other
1359 // bytecode translation or inlining nor as a consequence of
1360 // optimizing transforms.
1361 //
1362 // We also want to catch inlined unsafe volatile gets and puts and
1363 // be able to implement them using either ldar<x>/stlr<x> or some
1364 // combination of ldr<x>/stlr<x> and dmb instructions.
1365 //
1366 // Inlined unsafe volatiles puts manifest as a minor variant of the
1367 // normal volatile put node sequence containing an extra cpuorder
1368 // membar
1369 //
1370 // MemBarRelease
1371 // MemBarCPUOrder
1372 // StoreX[mo_release] {CardMark}-optional
1373 // MemBarCPUOrder
1374 // MemBarVolatile
1375 //
1376 // n.b. as an aside, a cpuorder membar is not itself subject to
1377 // matching and translation by adlc rules. However, the rule
1378 // predicates need to detect its presence in order to correctly
1379 // select the desired adlc rules.
1380 //
1381 // Inlined unsafe volatile gets manifest as a slightly different
1382 // node sequence to a normal volatile get because of the
1383 // introduction of some CPUOrder memory barriers to bracket the
1384 // Load. However, but the same basic skeleton of a LoadX feeding a
1385 // MemBarAcquire, possibly through an optional DecodeN, is still
1386 // present
1387 //
1388 // MemBarCPUOrder
1389 // || \\
1390 // MemBarCPUOrder LoadX[mo_acquire]
1391 // || |
1392 // || {DecodeN} optional
1393 // || /
1394 // MemBarAcquire
1395 //
1396 // In this case the acquire membar does not directly depend on the
1397 // load. However, we can be sure that the load is generated from an
1398 // inlined unsafe volatile get if we see it dependent on this unique
1399 // sequence of membar nodes. Similarly, given an acquire membar we
1400 // can know that it was added because of an inlined unsafe volatile
1401 // get if it is fed and feeds a cpuorder membar and if its feed
1402 // membar also feeds an acquiring load.
1403 //
1404 // Finally an inlined (Unsafe) CAS operation is translated to the
1405 // following ideal graph
1406 //
1407 // MemBarRelease
1408 // MemBarCPUOrder
1409 // CompareAndSwapX {CardMark}-optional
1410 // MemBarCPUOrder
1411 // MemBarAcquire
1412 //
1413 // So, where we can identify these volatile read and write
1414 // signatures we can choose to plant either of the above two code
1415 // sequences. For a volatile read we can simply plant a normal
1416 // ldr<x> and translate the MemBarAcquire to a dmb. However, we can
1417 // also choose to inhibit translation of the MemBarAcquire and
1418 // inhibit planting of the ldr<x>, instead planting an ldar<x>.
1419 //
1420 // When we recognise a volatile store signature we can choose to
1421 // plant at a dmb ish as a translation for the MemBarRelease, a
1422 // normal str<x> and then a dmb ish for the MemBarVolatile.
1423 // Alternatively, we can inhibit translation of the MemBarRelease
1424 // and MemBarVolatile and instead plant a simple stlr<x>
1425 // instruction.
1426 //
1427 // when we recognise a CAS signature we can choose to plant a dmb
1428 // ish as a translation for the MemBarRelease, the conventional
1429 // macro-instruction sequence for the CompareAndSwap node (which
1430 // uses ldxr<x>) and then a dmb ishld for the MemBarAcquire.
1431 // Alternatively, we can elide generation of the dmb instructions
1432 // and plant the alternative CompareAndSwap macro-instruction
1433 // sequence (which uses ldaxr<x>).
1434 //
1435 // Of course, the above only applies when we see these signature
1436 // configurations. We still want to plant dmb instructions in any
1437 // other cases where we may see a MemBarAcquire, MemBarRelease or
1438 // MemBarVolatile. For example, at the end of a constructor which
1439 // writes final/volatile fields we will see a MemBarRelease
1440 // instruction and this needs a 'dmb ish' lest we risk the
1441 // constructed object being visible without making the
1442 // final/volatile field writes visible.
1443 //
1444 // n.b. the translation rules below which rely on detection of the
1445 // volatile signatures and insert ldar<x> or stlr<x> are failsafe.
1446 // If we see anything other than the signature configurations we
1447 // always just translate the loads and stores to ldr<x> and str<x>
1448 // and translate acquire, release and volatile membars to the
1449 // relevant dmb instructions.
1450 //
1451
1452 // is_CAS(int opcode, bool maybe_volatile)
1453 //
1454 // return true if opcode is one of the possible CompareAndSwapX
1455 // values otherwise false.
1456
1457 bool is_CAS(int opcode, bool maybe_volatile)
1458 {
1459 switch(opcode) {
1460 // We handle these
1461 case Op_CompareAndSwapI:
1462 case Op_CompareAndSwapL:
1463 case Op_CompareAndSwapP:
1464 case Op_CompareAndSwapN:
1465 case Op_ShenandoahCompareAndSwapP:
1466 case Op_ShenandoahCompareAndSwapN:
1467 case Op_CompareAndSwapB:
1468 case Op_CompareAndSwapS:
1469 case Op_GetAndSetI:
1470 case Op_GetAndSetL:
1471 case Op_GetAndSetP:
1472 case Op_GetAndSetN:
1473 case Op_GetAndAddI:
1474 case Op_GetAndAddL:
1475 return true;
1476 case Op_CompareAndExchangeI:
1477 case Op_CompareAndExchangeN:
1478 case Op_CompareAndExchangeB:
1479 case Op_CompareAndExchangeS:
1480 case Op_CompareAndExchangeL:
1481 case Op_CompareAndExchangeP:
1482 case Op_WeakCompareAndSwapB:
1483 case Op_WeakCompareAndSwapS:
1484 case Op_WeakCompareAndSwapI:
1485 case Op_WeakCompareAndSwapL:
1486 case Op_WeakCompareAndSwapP:
1487 case Op_WeakCompareAndSwapN:
1488 case Op_ShenandoahWeakCompareAndSwapP:
1489 case Op_ShenandoahWeakCompareAndSwapN:
1490 case Op_ShenandoahCompareAndExchangeP:
1491 case Op_ShenandoahCompareAndExchangeN:
1492 return maybe_volatile;
1493 default:
1494 return false;
1495 }
1496 }
1497
1498 // helper to determine the maximum number of Phi nodes we may need to
1499 // traverse when searching from a card mark membar for the merge mem
1500 // feeding a trailing membar or vice versa
1501
1502 // predicates controlling emit of ldr<x>/ldar<x>
1503
1504 bool unnecessary_acquire(const Node *barrier)
1505 {
1506 assert(barrier->is_MemBar(), "expecting a membar");
1507
1508 MemBarNode* mb = barrier->as_MemBar();
1509
1510 if (mb->trailing_load()) {
1511 return true;
1512 }
1513
1514 if (mb->trailing_load_store()) {
1515 Node* load_store = mb->in(MemBarNode::Precedent);
1516 assert(load_store->is_LoadStore(), "unexpected graph shape");
1517 return is_CAS(load_store->Opcode(), true);
1518 }
1519
1520 return false;
1521 }
1522
1523 bool needs_acquiring_load(const Node *n)
1524 {
1525 assert(n->is_Load(), "expecting a load");
1526 LoadNode *ld = n->as_Load();
1527 return ld->is_acquire();
1528 }
1529
1530 bool unnecessary_release(const Node *n)
1531 {
1532 assert((n->is_MemBar() &&
1533 n->Opcode() == Op_MemBarRelease),
1534 "expecting a release membar");
1535
1536 MemBarNode *barrier = n->as_MemBar();
1537 if (!barrier->leading()) {
1538 return false;
1539 } else {
1540 Node* trailing = barrier->trailing_membar();
1541 MemBarNode* trailing_mb = trailing->as_MemBar();
1542 assert(trailing_mb->trailing(), "Not a trailing membar?");
1543 assert(trailing_mb->leading_membar() == n, "inconsistent leading/trailing membars");
1544
1545 Node* mem = trailing_mb->in(MemBarNode::Precedent);
1546 if (mem->is_Store()) {
1547 assert(mem->as_Store()->is_release(), "");
1548 assert(trailing_mb->Opcode() == Op_MemBarVolatile, "");
1549 return true;
1550 } else {
1551 assert(mem->is_LoadStore(), "");
1552 assert(trailing_mb->Opcode() == Op_MemBarAcquire, "");
1553 return is_CAS(mem->Opcode(), true);
1554 }
1555 }
1556 return false;
1557 }
1558
1559 bool unnecessary_volatile(const Node *n)
1560 {
1561 // assert n->is_MemBar();
1562 MemBarNode *mbvol = n->as_MemBar();
1563
1564 bool release = mbvol->trailing_store();
1565 assert(!release || (mbvol->in(MemBarNode::Precedent)->is_Store() && mbvol->in(MemBarNode::Precedent)->as_Store()->is_release()), "");
1566 #ifdef ASSERT
1567 if (release) {
1568 Node* leading = mbvol->leading_membar();
1569 assert(leading->Opcode() == Op_MemBarRelease, "");
1570 assert(leading->as_MemBar()->leading_store(), "");
1571 assert(leading->as_MemBar()->trailing_membar() == mbvol, "");
1572 }
1573 #endif
1574
1575 return release;
1576 }
1577
1578 // predicates controlling emit of str<x>/stlr<x>
1579
1580 bool needs_releasing_store(const Node *n)
1581 {
1582 // assert n->is_Store();
1583 StoreNode *st = n->as_Store();
1584 return st->trailing_membar() != NULL;
1585 }
1586
1587 // predicate controlling translation of CAS
1588 //
1589 // returns true if CAS needs to use an acquiring load otherwise false
1590
1591 bool needs_acquiring_load_exclusive(const Node *n)
1592 {
1593 assert(is_CAS(n->Opcode(), true), "expecting a compare and swap");
1594 LoadStoreNode* ldst = n->as_LoadStore();
1595 if (is_CAS(n->Opcode(), false)) {
1596 assert(ldst->trailing_membar() != NULL, "expected trailing membar");
1597 } else {
1598 return ldst->trailing_membar() != NULL;
1599 }
1600
1601 // so we can just return true here
1602 return true;
1603 }
1604
1605 #define __ _masm.
1606
1607 // advance declarations for helper functions to convert register
1608 // indices to register objects
1609
1610 // the ad file has to provide implementations of certain methods
1611 // expected by the generic code
1612 //
1613 // REQUIRED FUNCTIONALITY
1614
1615 //=============================================================================
1616
1617 // !!!!! Special hack to get all types of calls to specify the byte offset
1618 // from the start of the call to the point where the return address
1619 // will point.
1620
1621 int MachCallStaticJavaNode::ret_addr_offset()
1622 {
1623 // call should be a simple bl
1624 int off = 4;
1625 return off;
1626 }
1627
1628 int MachCallDynamicJavaNode::ret_addr_offset()
1629 {
1630 return 16; // movz, movk, movk, bl
1631 }
1632
1633 int MachCallRuntimeNode::ret_addr_offset() {
1634 // for generated stubs the call will be
1635 // bl(addr)
1636 // or with far branches
1637 // bl(trampoline_stub)
1638 // for real runtime callouts it will be six instructions
1639 // see aarch64_enc_java_to_runtime
1640 // adr(rscratch2, retaddr)
1641 // lea(rscratch1, RuntimeAddress(addr)
1642 // stp(zr, rscratch2, Address(__ pre(sp, -2 * wordSize)))
1643 // blr(rscratch1)
1644 CodeBlob *cb = CodeCache::find_blob(_entry_point);
1645 if (cb) {
1646 return 1 * NativeInstruction::instruction_size;
1647 } else {
1648 return 6 * NativeInstruction::instruction_size;
1649 }
1650 }
1651
1652 //=============================================================================
1653
1654 #ifndef PRODUCT
1655 void MachBreakpointNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1656 st->print("BREAKPOINT");
1657 }
1658 #endif
1659
1660 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1661 C2_MacroAssembler _masm(&cbuf);
1662 __ brk(0);
1663 }
1664
1665 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
1666 return MachNode::size(ra_);
1667 }
1668
1669 //=============================================================================
1670
1671 #ifndef PRODUCT
1672 void MachNopNode::format(PhaseRegAlloc*, outputStream* st) const {
1673 st->print("nop \t# %d bytes pad for loops and calls", _count);
1674 }
1675 #endif
1676
1677 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc*) const {
1678 C2_MacroAssembler _masm(&cbuf);
1679 for (int i = 0; i < _count; i++) {
1680 __ nop();
1681 }
1682 }
1683
1684 uint MachNopNode::size(PhaseRegAlloc*) const {
1685 return _count * NativeInstruction::instruction_size;
1686 }
1687
1688 //=============================================================================
1689 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;
1690
1691 int ConstantTable::calculate_table_base_offset() const {
1692 return 0; // absolute addressing, no offset
1693 }
1694
1695 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
1696 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
1697 ShouldNotReachHere();
1698 }
1699
1700 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
1701 // Empty encoding
1702 }
1703
1704 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
1705 return 0;
1706 }
1707
1708 #ifndef PRODUCT
1709 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1710 st->print("-- \t// MachConstantBaseNode (empty encoding)");
1711 }
1712 #endif
1713
1714 #ifndef PRODUCT
1715 void MachPrologNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1716 Compile* C = ra_->C;
1717
1718 int framesize = C->output()->frame_slots() << LogBytesPerInt;
1719
1720 if (C->output()->need_stack_bang(framesize))
1721 st->print("# stack bang size=%d\n\t", framesize);
1722
1723 if (VM_Version::use_rop_protection()) {
1724 st->print("ldr zr, [lr]\n\t");
1725 st->print("pacia lr, rfp\n\t");
1726 }
1727 if (framesize < ((1 << 9) + 2 * wordSize)) {
1728 st->print("sub sp, sp, #%d\n\t", framesize);
1729 st->print("stp rfp, lr, [sp, #%d]", framesize - 2 * wordSize);
1730 if (PreserveFramePointer) st->print("\n\tadd rfp, sp, #%d", framesize - 2 * wordSize);
1731 } else {
1732 st->print("stp lr, rfp, [sp, #%d]!\n\t", -(2 * wordSize));
1733 if (PreserveFramePointer) st->print("mov rfp, sp\n\t");
1734 st->print("mov rscratch1, #%d\n\t", framesize - 2 * wordSize);
1735 st->print("sub sp, sp, rscratch1");
1736 }
1737 if (C->stub_function() == NULL && BarrierSet::barrier_set()->barrier_set_nmethod() != NULL) {
1738 st->print("\n\t");
1739 st->print("ldr rscratch1, [guard]\n\t");
1740 st->print("dmb ishld\n\t");
1741 st->print("ldr rscratch2, [rthread, #thread_disarmed_guard_value_offset]\n\t");
1742 st->print("cmp rscratch1, rscratch2\n\t");
1743 st->print("b.eq skip");
1744 st->print("\n\t");
1745 st->print("blr #nmethod_entry_barrier_stub\n\t");
1746 st->print("b skip\n\t");
1747 st->print("guard: int\n\t");
1748 st->print("\n\t");
1749 st->print("skip:\n\t");
1750 }
1751 }
1752 #endif
1753
1754 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1755 Compile* C = ra_->C;
1756 C2_MacroAssembler _masm(&cbuf);
1757
1758 // n.b. frame size includes space for return pc and rfp
1759 const int framesize = C->output()->frame_size_in_bytes();
1760
1761 // insert a nop at the start of the prolog so we can patch in a
1762 // branch if we need to invalidate the method later
1763 __ nop();
1764
1765 if (C->clinit_barrier_on_entry()) {
1766 assert(!C->method()->holder()->is_not_initialized(), "initialization should have been started");
1767
1768 Label L_skip_barrier;
1769
1770 __ mov_metadata(rscratch2, C->method()->holder()->constant_encoding());
1771 __ clinit_barrier(rscratch2, rscratch1, &L_skip_barrier);
1772 __ far_jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub()));
1773 __ bind(L_skip_barrier);
1774 }
1775
1776 if (C->max_vector_size() > 0) {
1777 __ reinitialize_ptrue();
1778 }
1779
1780 int bangsize = C->output()->bang_size_in_bytes();
1781 if (C->output()->need_stack_bang(bangsize))
1782 __ generate_stack_overflow_check(bangsize);
1783
1784 __ build_frame(framesize);
1785
1786 if (C->stub_function() == NULL) {
1787 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
1788 if (BarrierSet::barrier_set()->barrier_set_nmethod() != NULL) {
1789 // Dummy labels for just measuring the code size
1790 Label dummy_slow_path;
1791 Label dummy_continuation;
1792 Label dummy_guard;
1793 Label* slow_path = &dummy_slow_path;
1794 Label* continuation = &dummy_continuation;
1795 Label* guard = &dummy_guard;
1796 if (!Compile::current()->output()->in_scratch_emit_size()) {
1797 // Use real labels from actual stub when not emitting code for the purpose of measuring its size
1798 C2EntryBarrierStub* stub = new (Compile::current()->comp_arena()) C2EntryBarrierStub();
1799 Compile::current()->output()->add_stub(stub);
1800 slow_path = &stub->entry();
1801 continuation = &stub->continuation();
1802 guard = &stub->guard();
1803 }
1804 // In the C2 code, we move the non-hot part of nmethod entry barriers out-of-line to a stub.
1805 bs->nmethod_entry_barrier(&_masm, slow_path, continuation, guard);
1806 }
1807 }
1808
1809 if (VerifyStackAtCalls) {
1810 Unimplemented();
1811 }
1812
1813 C->output()->set_frame_complete(cbuf.insts_size());
1814
1815 if (C->has_mach_constant_base_node()) {
1816 // NOTE: We set the table base offset here because users might be
1817 // emitted before MachConstantBaseNode.
1818 ConstantTable& constant_table = C->output()->constant_table();
1819 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
1820 }
1821 }
1822
1823 uint MachPrologNode::size(PhaseRegAlloc* ra_) const
1824 {
1825 return MachNode::size(ra_); // too many variables; just compute it
1826 // the hard way
1827 }
1828
1829 int MachPrologNode::reloc() const
1830 {
1831 return 0;
1832 }
1833
1834 //=============================================================================
1835
1836 #ifndef PRODUCT
1837 void MachEpilogNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1838 Compile* C = ra_->C;
1839 int framesize = C->output()->frame_slots() << LogBytesPerInt;
1840
1841 st->print("# pop frame %d\n\t",framesize);
1842
1843 if (framesize == 0) {
1844 st->print("ldp lr, rfp, [sp],#%d\n\t", (2 * wordSize));
1845 } else if (framesize < ((1 << 9) + 2 * wordSize)) {
1846 st->print("ldp lr, rfp, [sp,#%d]\n\t", framesize - 2 * wordSize);
1847 st->print("add sp, sp, #%d\n\t", framesize);
1848 } else {
1849 st->print("mov rscratch1, #%d\n\t", framesize - 2 * wordSize);
1850 st->print("add sp, sp, rscratch1\n\t");
1851 st->print("ldp lr, rfp, [sp],#%d\n\t", (2 * wordSize));
1852 }
1853 if (VM_Version::use_rop_protection()) {
1854 st->print("autia lr, rfp\n\t");
1855 st->print("ldr zr, [lr]\n\t");
1856 }
1857
1858 if (do_polling() && C->is_method_compilation()) {
1859 st->print("# test polling word\n\t");
1860 st->print("ldr rscratch1, [rthread],#%d\n\t", in_bytes(JavaThread::polling_word_offset()));
1861 st->print("cmp sp, rscratch1\n\t");
1862 st->print("bhi #slow_path");
1863 }
1864 }
1865 #endif
1866
1867 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1868 Compile* C = ra_->C;
1869 C2_MacroAssembler _masm(&cbuf);
1870 int framesize = C->output()->frame_slots() << LogBytesPerInt;
1871
1872 __ remove_frame(framesize);
1873
1874 if (StackReservedPages > 0 && C->has_reserved_stack_access()) {
1875 __ reserved_stack_check();
1876 }
1877
1878 if (do_polling() && C->is_method_compilation()) {
1879 Label dummy_label;
1880 Label* code_stub = &dummy_label;
1881 if (!C->output()->in_scratch_emit_size()) {
1882 C2SafepointPollStub* stub = new (C->comp_arena()) C2SafepointPollStub(__ offset());
1883 C->output()->add_stub(stub);
1884 code_stub = &stub->entry();
1885 }
1886 __ relocate(relocInfo::poll_return_type);
1887 __ safepoint_poll(*code_stub, true /* at_return */, false /* acquire */, true /* in_nmethod */);
1888 }
1889 }
1890
1891 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
1892 // Variable size. Determine dynamically.
1893 return MachNode::size(ra_);
1894 }
1895
1896 int MachEpilogNode::reloc() const {
1897 // Return number of relocatable values contained in this instruction.
1898 return 1; // 1 for polling page.
1899 }
1900
1901 const Pipeline * MachEpilogNode::pipeline() const {
1902 return MachNode::pipeline_class();
1903 }
1904
1905 //=============================================================================
1906
1907 // Figure out which register class each belongs in: rc_int, rc_float or
1908 // rc_stack.
1909 enum RC { rc_bad, rc_int, rc_float, rc_predicate, rc_stack };
1910
1911 static enum RC rc_class(OptoReg::Name reg) {
1912
1913 if (reg == OptoReg::Bad) {
1914 return rc_bad;
1915 }
1916
1917 // we have 32 int registers * 2 halves
1918 int slots_of_int_registers = Register::number_of_registers * Register::max_slots_per_register;
1919
1920 if (reg < slots_of_int_registers) {
1921 return rc_int;
1922 }
1923
1924 // we have 32 float register * 8 halves
1925 int slots_of_float_registers = FloatRegister::number_of_registers * FloatRegister::max_slots_per_register;
1926 if (reg < slots_of_int_registers + slots_of_float_registers) {
1927 return rc_float;
1928 }
1929
1930 int slots_of_predicate_registers = PRegister::number_of_registers * PRegister::max_slots_per_register;
1931 if (reg < slots_of_int_registers + slots_of_float_registers + slots_of_predicate_registers) {
1932 return rc_predicate;
1933 }
1934
1935 // Between predicate regs & stack is the flags.
1936 assert(OptoReg::is_stack(reg), "blow up if spilling flags");
1937
1938 return rc_stack;
1939 }
1940
1941 uint MachSpillCopyNode::implementation(CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream *st) const {
1942 Compile* C = ra_->C;
1943
1944 // Get registers to move.
1945 OptoReg::Name src_hi = ra_->get_reg_second(in(1));
1946 OptoReg::Name src_lo = ra_->get_reg_first(in(1));
1947 OptoReg::Name dst_hi = ra_->get_reg_second(this);
1948 OptoReg::Name dst_lo = ra_->get_reg_first(this);
1949
1950 enum RC src_hi_rc = rc_class(src_hi);
1951 enum RC src_lo_rc = rc_class(src_lo);
1952 enum RC dst_hi_rc = rc_class(dst_hi);
1953 enum RC dst_lo_rc = rc_class(dst_lo);
1954
1955 assert(src_lo != OptoReg::Bad && dst_lo != OptoReg::Bad, "must move at least 1 register");
1956
1957 if (src_hi != OptoReg::Bad && !bottom_type()->isa_vectmask()) {
1958 assert((src_lo&1)==0 && src_lo+1==src_hi &&
1959 (dst_lo&1)==0 && dst_lo+1==dst_hi,
1960 "expected aligned-adjacent pairs");
1961 }
1962
1963 if (src_lo == dst_lo && src_hi == dst_hi) {
1964 return 0; // Self copy, no move.
1965 }
1966
1967 bool is64 = (src_lo & 1) == 0 && src_lo + 1 == src_hi &&
1968 (dst_lo & 1) == 0 && dst_lo + 1 == dst_hi;
1969 int src_offset = ra_->reg2offset(src_lo);
1970 int dst_offset = ra_->reg2offset(dst_lo);
1971
1972 if (bottom_type()->isa_vect() && !bottom_type()->isa_vectmask()) {
1973 uint ireg = ideal_reg();
1974 if (ireg == Op_VecA && cbuf) {
1975 C2_MacroAssembler _masm(cbuf);
1976 int sve_vector_reg_size_in_bytes = Matcher::scalable_vector_reg_size(T_BYTE);
1977 if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
1978 // stack->stack
1979 __ spill_copy_sve_vector_stack_to_stack(src_offset, dst_offset,
1980 sve_vector_reg_size_in_bytes);
1981 } else if (src_lo_rc == rc_float && dst_lo_rc == rc_stack) {
1982 __ spill_sve_vector(as_FloatRegister(Matcher::_regEncode[src_lo]), ra_->reg2offset(dst_lo),
1983 sve_vector_reg_size_in_bytes);
1984 } else if (src_lo_rc == rc_stack && dst_lo_rc == rc_float) {
1985 __ unspill_sve_vector(as_FloatRegister(Matcher::_regEncode[dst_lo]), ra_->reg2offset(src_lo),
1986 sve_vector_reg_size_in_bytes);
1987 } else if (src_lo_rc == rc_float && dst_lo_rc == rc_float) {
1988 __ sve_orr(as_FloatRegister(Matcher::_regEncode[dst_lo]),
1989 as_FloatRegister(Matcher::_regEncode[src_lo]),
1990 as_FloatRegister(Matcher::_regEncode[src_lo]));
1991 } else {
1992 ShouldNotReachHere();
1993 }
1994 } else if (cbuf) {
1995 assert(ireg == Op_VecD || ireg == Op_VecX, "must be 64 bit or 128 bit vector");
1996 C2_MacroAssembler _masm(cbuf);
1997 assert((src_lo_rc != rc_int && dst_lo_rc != rc_int), "sanity");
1998 if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
1999 // stack->stack
2000 assert((src_offset & 7) == 0 && (dst_offset & 7) == 0, "unaligned stack offset");
2001 if (ireg == Op_VecD) {
2002 __ unspill(rscratch1, true, src_offset);
2003 __ spill(rscratch1, true, dst_offset);
2004 } else {
2005 __ spill_copy128(src_offset, dst_offset);
2006 }
2007 } else if (src_lo_rc == rc_float && dst_lo_rc == rc_float) {
2008 __ mov(as_FloatRegister(Matcher::_regEncode[dst_lo]),
2009 ireg == Op_VecD ? __ T8B : __ T16B,
2010 as_FloatRegister(Matcher::_regEncode[src_lo]));
2011 } else if (src_lo_rc == rc_float && dst_lo_rc == rc_stack) {
2012 __ spill(as_FloatRegister(Matcher::_regEncode[src_lo]),
2013 ireg == Op_VecD ? __ D : __ Q,
2014 ra_->reg2offset(dst_lo));
2015 } else if (src_lo_rc == rc_stack && dst_lo_rc == rc_float) {
2016 __ unspill(as_FloatRegister(Matcher::_regEncode[dst_lo]),
2017 ireg == Op_VecD ? __ D : __ Q,
2018 ra_->reg2offset(src_lo));
2019 } else {
2020 ShouldNotReachHere();
2021 }
2022 }
2023 } else if (cbuf) {
2024 C2_MacroAssembler _masm(cbuf);
2025 switch (src_lo_rc) {
2026 case rc_int:
2027 if (dst_lo_rc == rc_int) { // gpr --> gpr copy
2028 if (is64) {
2029 __ mov(as_Register(Matcher::_regEncode[dst_lo]),
2030 as_Register(Matcher::_regEncode[src_lo]));
2031 } else {
2032 C2_MacroAssembler _masm(cbuf);
2033 __ movw(as_Register(Matcher::_regEncode[dst_lo]),
2034 as_Register(Matcher::_regEncode[src_lo]));
2035 }
2036 } else if (dst_lo_rc == rc_float) { // gpr --> fpr copy
2037 if (is64) {
2038 __ fmovd(as_FloatRegister(Matcher::_regEncode[dst_lo]),
2039 as_Register(Matcher::_regEncode[src_lo]));
2040 } else {
2041 __ fmovs(as_FloatRegister(Matcher::_regEncode[dst_lo]),
2042 as_Register(Matcher::_regEncode[src_lo]));
2043 }
2044 } else { // gpr --> stack spill
2045 assert(dst_lo_rc == rc_stack, "spill to bad register class");
2046 __ spill(as_Register(Matcher::_regEncode[src_lo]), is64, dst_offset);
2047 }
2048 break;
2049 case rc_float:
2050 if (dst_lo_rc == rc_int) { // fpr --> gpr copy
2051 if (is64) {
2052 __ fmovd(as_Register(Matcher::_regEncode[dst_lo]),
2053 as_FloatRegister(Matcher::_regEncode[src_lo]));
2054 } else {
2055 __ fmovs(as_Register(Matcher::_regEncode[dst_lo]),
2056 as_FloatRegister(Matcher::_regEncode[src_lo]));
2057 }
2058 } else if (dst_lo_rc == rc_float) { // fpr --> fpr copy
2059 if (is64) {
2060 __ fmovd(as_FloatRegister(Matcher::_regEncode[dst_lo]),
2061 as_FloatRegister(Matcher::_regEncode[src_lo]));
2062 } else {
2063 __ fmovs(as_FloatRegister(Matcher::_regEncode[dst_lo]),
2064 as_FloatRegister(Matcher::_regEncode[src_lo]));
2065 }
2066 } else { // fpr --> stack spill
2067 assert(dst_lo_rc == rc_stack, "spill to bad register class");
2068 __ spill(as_FloatRegister(Matcher::_regEncode[src_lo]),
2069 is64 ? __ D : __ S, dst_offset);
2070 }
2071 break;
2072 case rc_stack:
2073 if (dst_lo_rc == rc_int) { // stack --> gpr load
2074 __ unspill(as_Register(Matcher::_regEncode[dst_lo]), is64, src_offset);
2075 } else if (dst_lo_rc == rc_float) { // stack --> fpr load
2076 __ unspill(as_FloatRegister(Matcher::_regEncode[dst_lo]),
2077 is64 ? __ D : __ S, src_offset);
2078 } else if (dst_lo_rc == rc_predicate) {
2079 __ unspill_sve_predicate(as_PRegister(Matcher::_regEncode[dst_lo]), ra_->reg2offset(src_lo),
2080 Matcher::scalable_vector_reg_size(T_BYTE) >> 3);
2081 } else { // stack --> stack copy
2082 assert(dst_lo_rc == rc_stack, "spill to bad register class");
2083 if (ideal_reg() == Op_RegVectMask) {
2084 __ spill_copy_sve_predicate_stack_to_stack(src_offset, dst_offset,
2085 Matcher::scalable_vector_reg_size(T_BYTE) >> 3);
2086 } else {
2087 __ unspill(rscratch1, is64, src_offset);
2088 __ spill(rscratch1, is64, dst_offset);
2089 }
2090 }
2091 break;
2092 case rc_predicate:
2093 if (dst_lo_rc == rc_predicate) {
2094 __ sve_mov(as_PRegister(Matcher::_regEncode[dst_lo]), as_PRegister(Matcher::_regEncode[src_lo]));
2095 } else if (dst_lo_rc == rc_stack) {
2096 __ spill_sve_predicate(as_PRegister(Matcher::_regEncode[src_lo]), ra_->reg2offset(dst_lo),
2097 Matcher::scalable_vector_reg_size(T_BYTE) >> 3);
2098 } else {
2099 assert(false, "bad src and dst rc_class combination.");
2100 ShouldNotReachHere();
2101 }
2102 break;
2103 default:
2104 assert(false, "bad rc_class for spill");
2105 ShouldNotReachHere();
2106 }
2107 }
2108
2109 if (st) {
2110 st->print("spill ");
2111 if (src_lo_rc == rc_stack) {
2112 st->print("[sp, #%d] -> ", ra_->reg2offset(src_lo));
2113 } else {
2114 st->print("%s -> ", Matcher::regName[src_lo]);
2115 }
2116 if (dst_lo_rc == rc_stack) {
2117 st->print("[sp, #%d]", ra_->reg2offset(dst_lo));
2118 } else {
2119 st->print("%s", Matcher::regName[dst_lo]);
2120 }
2121 if (bottom_type()->isa_vect() && !bottom_type()->isa_vectmask()) {
2122 int vsize = 0;
2123 switch (ideal_reg()) {
2124 case Op_VecD:
2125 vsize = 64;
2126 break;
2127 case Op_VecX:
2128 vsize = 128;
2129 break;
2130 case Op_VecA:
2131 vsize = Matcher::scalable_vector_reg_size(T_BYTE) * 8;
2132 break;
2133 default:
2134 assert(false, "bad register type for spill");
2135 ShouldNotReachHere();
2136 }
2137 st->print("\t# vector spill size = %d", vsize);
2138 } else if (ideal_reg() == Op_RegVectMask) {
2139 assert(Matcher::supports_scalable_vector(), "bad register type for spill");
2140 int vsize = Matcher::scalable_predicate_reg_slots() * 32;
2141 st->print("\t# predicate spill size = %d", vsize);
2142 } else {
2143 st->print("\t# spill size = %d", is64 ? 64 : 32);
2144 }
2145 }
2146
2147 return 0;
2148
2149 }
2150
2151 #ifndef PRODUCT
2152 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
2153 if (!ra_)
2154 st->print("N%d = SpillCopy(N%d)", _idx, in(1)->_idx);
2155 else
2156 implementation(NULL, ra_, false, st);
2157 }
2158 #endif
2159
2160 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
2161 implementation(&cbuf, ra_, false, NULL);
2162 }
2163
2164 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
2165 return MachNode::size(ra_);
2166 }
2167
2168 //=============================================================================
2169
2170 #ifndef PRODUCT
2171 void BoxLockNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
2172 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
2173 int reg = ra_->get_reg_first(this);
2174 st->print("add %s, rsp, #%d]\t# box lock",
2175 Matcher::regName[reg], offset);
2176 }
2177 #endif
2178
2179 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
2180 C2_MacroAssembler _masm(&cbuf);
2181
2182 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
2183 int reg = ra_->get_encode(this);
2184
2185 // This add will handle any 24-bit signed offset. 24 bits allows an
2186 // 8 megabyte stack frame.
2187 __ add(as_Register(reg), sp, offset);
2188 }
2189
2190 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
2191 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_).
2192 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
2193
2194 if (Assembler::operand_valid_for_add_sub_immediate(offset)) {
2195 return NativeInstruction::instruction_size;
2196 } else {
2197 return 2 * NativeInstruction::instruction_size;
2198 }
2199 }
2200
2201 //=============================================================================
2202
2203 #ifndef PRODUCT
2204 void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const
2205 {
2206 st->print_cr("# MachUEPNode");
2207 if (UseCompressedClassPointers) {
2208 st->print_cr("\tldrw rscratch1, j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass");
2209 if (CompressedKlassPointers::shift() != 0) {
2210 st->print_cr("\tdecode_klass_not_null rscratch1, rscratch1");
2211 }
2212 } else {
2213 st->print_cr("\tldr rscratch1, j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass");
2214 }
2215 st->print_cr("\tcmp r0, rscratch1\t # Inline cache check");
2216 st->print_cr("\tbne, SharedRuntime::_ic_miss_stub");
2217 }
2218 #endif
2219
2220 void MachUEPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
2221 {
2222 // This is the unverified entry point.
2223 C2_MacroAssembler _masm(&cbuf);
2224
2225 __ cmp_klass(j_rarg0, rscratch2, rscratch1);
2226 Label skip;
2227 // TODO
2228 // can we avoid this skip and still use a reloc?
2229 __ br(Assembler::EQ, skip);
2230 __ far_jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
2231 __ bind(skip);
2232 }
2233
2234 uint MachUEPNode::size(PhaseRegAlloc* ra_) const
2235 {
2236 return MachNode::size(ra_);
2237 }
2238
2239 // REQUIRED EMIT CODE
2240
2241 //=============================================================================
2242
2243 // Emit exception handler code.
2244 int HandlerImpl::emit_exception_handler(CodeBuffer& cbuf)
2245 {
2246 // mov rscratch1 #exception_blob_entry_point
2247 // br rscratch1
2248 // Note that the code buffer's insts_mark is always relative to insts.
2249 // That's why we must use the macroassembler to generate a handler.
2250 C2_MacroAssembler _masm(&cbuf);
2251 address base = __ start_a_stub(size_exception_handler());
2252 if (base == NULL) {
2253 ciEnv::current()->record_failure("CodeCache is full");
2254 return 0; // CodeBuffer::expand failed
2255 }
2256 int offset = __ offset();
2257 __ far_jump(RuntimeAddress(OptoRuntime::exception_blob()->entry_point()));
2258 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
2259 __ end_a_stub();
2260 return offset;
2261 }
2262
2263 // Emit deopt handler code.
2264 int HandlerImpl::emit_deopt_handler(CodeBuffer& cbuf)
2265 {
2266 // Note that the code buffer's insts_mark is always relative to insts.
2267 // That's why we must use the macroassembler to generate a handler.
2268 C2_MacroAssembler _masm(&cbuf);
2269 address base = __ start_a_stub(size_deopt_handler());
2270 if (base == NULL) {
2271 ciEnv::current()->record_failure("CodeCache is full");
2272 return 0; // CodeBuffer::expand failed
2273 }
2274 int offset = __ offset();
2275
2276 __ adr(lr, __ pc());
2277 __ far_jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
2278
2279 assert(__ offset() - offset == (int) size_deopt_handler(), "overflow");
2280 __ end_a_stub();
2281 return offset;
2282 }
2283
2284 // REQUIRED MATCHER CODE
2285
2286 //=============================================================================
2287
2288 const bool Matcher::match_rule_supported(int opcode) {
2289 if (!has_match_rule(opcode))
2290 return false;
2291
2292 bool ret_value = true;
2293 switch (opcode) {
2294 case Op_OnSpinWait:
2295 return VM_Version::supports_on_spin_wait();
2296 case Op_CacheWB:
2297 case Op_CacheWBPreSync:
2298 case Op_CacheWBPostSync:
2299 if (!VM_Version::supports_data_cache_line_flush()) {
2300 ret_value = false;
2301 }
2302 break;
2303 case Op_ExpandBits:
2304 case Op_CompressBits:
2305 if (!(UseSVE > 1 && VM_Version::supports_svebitperm())) {
2306 ret_value = false;
2307 }
2308 break;
2309 }
2310
2311 return ret_value; // Per default match rules are supported.
2312 }
2313
2314 const RegMask* Matcher::predicate_reg_mask(void) {
2315 return &_PR_REG_mask;
2316 }
2317
2318 const TypeVectMask* Matcher::predicate_reg_type(const Type* elemTy, int length) {
2319 return new TypeVectMask(elemTy, length);
2320 }
2321
2322 // Vector calling convention not yet implemented.
2323 const bool Matcher::supports_vector_calling_convention(void) {
2324 return false;
2325 }
2326
2327 OptoRegPair Matcher::vector_return_value(uint ideal_reg) {
2328 Unimplemented();
2329 return OptoRegPair(0, 0);
2330 }
2331
2332 // Is this branch offset short enough that a short branch can be used?
2333 //
2334 // NOTE: If the platform does not provide any short branch variants, then
2335 // this method should return false for offset 0.
2336 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
2337 // The passed offset is relative to address of the branch.
2338
2339 return (-32768 <= offset && offset < 32768);
2340 }
2341
2342 // Vector width in bytes.
2343 const int Matcher::vector_width_in_bytes(BasicType bt) {
2344 // The MaxVectorSize should have been set by detecting SVE max vector register size.
2345 int size = MIN2((UseSVE > 0) ? 256 : 16, (int)MaxVectorSize);
2346 // Minimum 2 values in vector
2347 if (size < 2*type2aelembytes(bt)) size = 0;
2348 // But never < 4
2349 if (size < 4) size = 0;
2350 return size;
2351 }
2352
2353 // Limits on vector size (number of elements) loaded into vector.
2354 const int Matcher::max_vector_size(const BasicType bt) {
2355 return vector_width_in_bytes(bt)/type2aelembytes(bt);
2356 }
2357
2358 const int Matcher::min_vector_size(const BasicType bt) {
2359 int max_size = max_vector_size(bt);
2360 // Limit the min vector size to 8 bytes.
2361 int size = 8 / type2aelembytes(bt);
2362 if (bt == T_BYTE) {
2363 // To support vector api shuffle/rearrange.
2364 size = 4;
2365 } else if (bt == T_BOOLEAN) {
2366 // To support vector api load/store mask.
2367 size = 2;
2368 }
2369 if (size < 2) size = 2;
2370 return MIN2(size, max_size);
2371 }
2372
2373 const int Matcher::superword_max_vector_size(const BasicType bt) {
2374 return Matcher::max_vector_size(bt);
2375 }
2376
2377 // Actual max scalable vector register length.
2378 const int Matcher::scalable_vector_reg_size(const BasicType bt) {
2379 return Matcher::max_vector_size(bt);
2380 }
2381
2382 // Vector ideal reg.
2383 const uint Matcher::vector_ideal_reg(int len) {
2384 if (UseSVE > 0 && 16 < len && len <= 256) {
2385 return Op_VecA;
2386 }
2387 switch(len) {
2388 // For 16-bit/32-bit mask vector, reuse VecD.
2389 case 2:
2390 case 4:
2391 case 8: return Op_VecD;
2392 case 16: return Op_VecX;
2393 }
2394 ShouldNotReachHere();
2395 return 0;
2396 }
2397
2398 MachOper* Matcher::pd_specialize_generic_vector_operand(MachOper* generic_opnd, uint ideal_reg, bool is_temp) {
2399 assert(Matcher::is_generic_vector(generic_opnd), "not generic");
2400 switch (ideal_reg) {
2401 case Op_VecA: return new vecAOper();
2402 case Op_VecD: return new vecDOper();
2403 case Op_VecX: return new vecXOper();
2404 }
2405 ShouldNotReachHere();
2406 return NULL;
2407 }
2408
2409 bool Matcher::is_reg2reg_move(MachNode* m) {
2410 return false;
2411 }
2412
2413 bool Matcher::is_generic_vector(MachOper* opnd) {
2414 return opnd->opcode() == VREG;
2415 }
2416
2417 // Return whether or not this register is ever used as an argument.
2418 // This function is used on startup to build the trampoline stubs in
2419 // generateOptoStub. Registers not mentioned will be killed by the VM
2420 // call in the trampoline, and arguments in those registers not be
2421 // available to the callee.
2422 bool Matcher::can_be_java_arg(int reg)
2423 {
2424 return
2425 reg == R0_num || reg == R0_H_num ||
2426 reg == R1_num || reg == R1_H_num ||
2427 reg == R2_num || reg == R2_H_num ||
2428 reg == R3_num || reg == R3_H_num ||
2429 reg == R4_num || reg == R4_H_num ||
2430 reg == R5_num || reg == R5_H_num ||
2431 reg == R6_num || reg == R6_H_num ||
2432 reg == R7_num || reg == R7_H_num ||
2433 reg == V0_num || reg == V0_H_num ||
2434 reg == V1_num || reg == V1_H_num ||
2435 reg == V2_num || reg == V2_H_num ||
2436 reg == V3_num || reg == V3_H_num ||
2437 reg == V4_num || reg == V4_H_num ||
2438 reg == V5_num || reg == V5_H_num ||
2439 reg == V6_num || reg == V6_H_num ||
2440 reg == V7_num || reg == V7_H_num;
2441 }
2442
2443 bool Matcher::is_spillable_arg(int reg)
2444 {
2445 return can_be_java_arg(reg);
2446 }
2447
2448 uint Matcher::int_pressure_limit()
2449 {
2450 // JDK-8183543: When taking the number of available registers as int
2451 // register pressure threshold, the jtreg test:
2452 // test/hotspot/jtreg/compiler/regalloc/TestC2IntPressure.java
2453 // failed due to C2 compilation failure with
2454 // "COMPILE SKIPPED: failed spill-split-recycle sanity check".
2455 //
2456 // A derived pointer is live at CallNode and then is flagged by RA
2457 // as a spilled LRG. Spilling heuristics(Spill-USE) explicitly skip
2458 // derived pointers and lastly fail to spill after reaching maximum
2459 // number of iterations. Lowering the default pressure threshold to
2460 // (_NO_SPECIAL_REG32_mask.Size() minus 1) forces CallNode to become
2461 // a high register pressure area of the code so that split_DEF can
2462 // generate DefinitionSpillCopy for the derived pointer.
2463 uint default_int_pressure_threshold = _NO_SPECIAL_REG32_mask.Size() - 1;
2464 if (!PreserveFramePointer) {
2465 // When PreserveFramePointer is off, frame pointer is allocatable,
2466 // but different from other SOC registers, it is excluded from
2467 // fatproj's mask because its save type is No-Save. Decrease 1 to
2468 // ensure high pressure at fatproj when PreserveFramePointer is off.
2469 // See check_pressure_at_fatproj().
2470 default_int_pressure_threshold--;
2471 }
2472 return (INTPRESSURE == -1) ? default_int_pressure_threshold : INTPRESSURE;
2473 }
2474
2475 uint Matcher::float_pressure_limit()
2476 {
2477 // _FLOAT_REG_mask is generated by adlc from the float_reg register class.
2478 return (FLOATPRESSURE == -1) ? _FLOAT_REG_mask.Size() : FLOATPRESSURE;
2479 }
2480
2481 bool Matcher::use_asm_for_ldiv_by_con(jlong divisor) {
2482 return false;
2483 }
2484
2485 RegMask Matcher::divI_proj_mask() {
2486 ShouldNotReachHere();
2487 return RegMask();
2488 }
2489
2490 // Register for MODI projection of divmodI.
2491 RegMask Matcher::modI_proj_mask() {
2492 ShouldNotReachHere();
2493 return RegMask();
2494 }
2495
2496 // Register for DIVL projection of divmodL.
2497 RegMask Matcher::divL_proj_mask() {
2498 ShouldNotReachHere();
2499 return RegMask();
2500 }
2501
2502 // Register for MODL projection of divmodL.
2503 RegMask Matcher::modL_proj_mask() {
2504 ShouldNotReachHere();
2505 return RegMask();
2506 }
2507
2508 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
2509 return FP_REG_mask();
2510 }
2511
2512 bool size_fits_all_mem_uses(AddPNode* addp, int shift) {
2513 for (DUIterator_Fast imax, i = addp->fast_outs(imax); i < imax; i++) {
2514 Node* u = addp->fast_out(i);
2515 if (u->is_LoadStore()) {
2516 // On AArch64, LoadStoreNodes (i.e. compare and swap
2517 // instructions) only take register indirect as an operand, so
2518 // any attempt to use an AddPNode as an input to a LoadStoreNode
2519 // must fail.
2520 return false;
2521 }
2522 if (u->is_Mem()) {
2523 int opsize = u->as_Mem()->memory_size();
2524 assert(opsize > 0, "unexpected memory operand size");
2525 if (u->as_Mem()->memory_size() != (1<<shift)) {
2526 return false;
2527 }
2528 }
2529 }
2530 return true;
2531 }
2532
2533 // Convert BootTest condition to Assembler condition.
2534 // Replicate the logic of cmpOpOper::ccode() and cmpOpUOper::ccode().
2535 Assembler::Condition to_assembler_cond(BoolTest::mask cond) {
2536 Assembler::Condition result;
2537 switch(cond) {
2538 case BoolTest::eq:
2539 result = Assembler::EQ; break;
2540 case BoolTest::ne:
2541 result = Assembler::NE; break;
2542 case BoolTest::le:
2543 result = Assembler::LE; break;
2544 case BoolTest::ge:
2545 result = Assembler::GE; break;
2546 case BoolTest::lt:
2547 result = Assembler::LT; break;
2548 case BoolTest::gt:
2549 result = Assembler::GT; break;
2550 case BoolTest::ule:
2551 result = Assembler::LS; break;
2552 case BoolTest::uge:
2553 result = Assembler::HS; break;
2554 case BoolTest::ult:
2555 result = Assembler::LO; break;
2556 case BoolTest::ugt:
2557 result = Assembler::HI; break;
2558 case BoolTest::overflow:
2559 result = Assembler::VS; break;
2560 case BoolTest::no_overflow:
2561 result = Assembler::VC; break;
2562 default:
2563 ShouldNotReachHere();
2564 return Assembler::Condition(-1);
2565 }
2566
2567 // Check conversion
2568 if (cond & BoolTest::unsigned_compare) {
2569 assert(cmpOpUOper((BoolTest::mask)((int)cond & ~(BoolTest::unsigned_compare))).ccode() == result, "Invalid conversion");
2570 } else {
2571 assert(cmpOpOper(cond).ccode() == result, "Invalid conversion");
2572 }
2573
2574 return result;
2575 }
2576
2577 // Binary src (Replicate con)
2578 bool is_valid_sve_arith_imm_pattern(Node* n, Node* m) {
2579 if (n == NULL || m == NULL) {
2580 return false;
2581 }
2582
2583 if (UseSVE == 0 || !VectorNode::is_invariant_vector(m)) {
2584 return false;
2585 }
2586
2587 Node* imm_node = m->in(1);
2588 if (!imm_node->is_Con()) {
2589 return false;
2590 }
2591
2592 const Type* t = imm_node->bottom_type();
2593 if (!(t->isa_int() || t->isa_long())) {
2594 return false;
2595 }
2596
2597 switch (n->Opcode()) {
2598 case Op_AndV:
2599 case Op_OrV:
2600 case Op_XorV: {
2601 Assembler::SIMD_RegVariant T = Assembler::elemType_to_regVariant(Matcher::vector_element_basic_type(n));
2602 uint64_t value = t->isa_long() ? (uint64_t)imm_node->get_long() : (uint64_t)imm_node->get_int();
2603 return Assembler::operand_valid_for_sve_logical_immediate(Assembler::regVariant_to_elemBits(T), value);
2604 }
2605 case Op_AddVB:
2606 return (imm_node->get_int() <= 255 && imm_node->get_int() >= -255);
2607 case Op_AddVS:
2608 case Op_AddVI:
2609 return Assembler::operand_valid_for_sve_add_sub_immediate((int64_t)imm_node->get_int());
2610 case Op_AddVL:
2611 return Assembler::operand_valid_for_sve_add_sub_immediate(imm_node->get_long());
2612 default:
2613 return false;
2614 }
2615 }
2616
2617 // (XorV src (Replicate m1))
2618 // (XorVMask src (MaskAll m1))
2619 bool is_vector_bitwise_not_pattern(Node* n, Node* m) {
2620 if (n != NULL && m != NULL) {
2621 return (n->Opcode() == Op_XorV || n->Opcode() == Op_XorVMask) &&
2622 VectorNode::is_all_ones_vector(m);
2623 }
2624 return false;
2625 }
2626
2627 // Should the matcher clone input 'm' of node 'n'?
2628 bool Matcher::pd_clone_node(Node* n, Node* m, Matcher::MStack& mstack) {
2629 if (is_vshift_con_pattern(n, m) ||
2630 is_vector_bitwise_not_pattern(n, m) ||
2631 is_valid_sve_arith_imm_pattern(n, m)) {
2632 mstack.push(m, Visit);
2633 return true;
2634 }
2635 return false;
2636 }
2637
2638 // Should the Matcher clone shifts on addressing modes, expecting them
2639 // to be subsumed into complex addressing expressions or compute them
2640 // into registers?
2641 bool Matcher::pd_clone_address_expressions(AddPNode* m, Matcher::MStack& mstack, VectorSet& address_visited) {
2642 if (clone_base_plus_offset_address(m, mstack, address_visited)) {
2643 return true;
2644 }
2645
2646 Node *off = m->in(AddPNode::Offset);
2647 if (off->Opcode() == Op_LShiftL && off->in(2)->is_Con() &&
2648 size_fits_all_mem_uses(m, off->in(2)->get_int()) &&
2649 // Are there other uses besides address expressions?
2650 !is_visited(off)) {
2651 address_visited.set(off->_idx); // Flag as address_visited
2652 mstack.push(off->in(2), Visit);
2653 Node *conv = off->in(1);
2654 if (conv->Opcode() == Op_ConvI2L &&
2655 // Are there other uses besides address expressions?
2656 !is_visited(conv)) {
2657 address_visited.set(conv->_idx); // Flag as address_visited
2658 mstack.push(conv->in(1), Pre_Visit);
2659 } else {
2660 mstack.push(conv, Pre_Visit);
2661 }
2662 address_visited.test_set(m->_idx); // Flag as address_visited
2663 mstack.push(m->in(AddPNode::Address), Pre_Visit);
2664 mstack.push(m->in(AddPNode::Base), Pre_Visit);
2665 return true;
2666 } else if (off->Opcode() == Op_ConvI2L &&
2667 // Are there other uses besides address expressions?
2668 !is_visited(off)) {
2669 address_visited.test_set(m->_idx); // Flag as address_visited
2670 address_visited.set(off->_idx); // Flag as address_visited
2671 mstack.push(off->in(1), Pre_Visit);
2672 mstack.push(m->in(AddPNode::Address), Pre_Visit);
2673 mstack.push(m->in(AddPNode::Base), Pre_Visit);
2674 return true;
2675 }
2676 return false;
2677 }
2678
2679 #define MOV_VOLATILE(REG, BASE, INDEX, SCALE, DISP, SCRATCH, INSN) \
2680 C2_MacroAssembler _masm(&cbuf); \
2681 { \
2682 guarantee(INDEX == -1, "mode not permitted for volatile"); \
2683 guarantee(DISP == 0, "mode not permitted for volatile"); \
2684 guarantee(SCALE == 0, "mode not permitted for volatile"); \
2685 __ INSN(REG, as_Register(BASE)); \
2686 }
2687
2688
2689 static Address mem2address(int opcode, Register base, int index, int size, int disp)
2690 {
2691 Address::extend scale;
2692
2693 // Hooboy, this is fugly. We need a way to communicate to the
2694 // encoder that the index needs to be sign extended, so we have to
2695 // enumerate all the cases.
2696 switch (opcode) {
2697 case INDINDEXSCALEDI2L:
2698 case INDINDEXSCALEDI2LN:
2699 case INDINDEXI2L:
2700 case INDINDEXI2LN:
2701 scale = Address::sxtw(size);
2702 break;
2703 default:
2704 scale = Address::lsl(size);
2705 }
2706
2707 if (index == -1) {
2708 return Address(base, disp);
2709 } else {
2710 assert(disp == 0, "unsupported address mode: disp = %d", disp);
2711 return Address(base, as_Register(index), scale);
2712 }
2713 }
2714
2715
2716 typedef void (MacroAssembler::* mem_insn)(Register Rt, const Address &adr);
2717 typedef void (MacroAssembler::* mem_insn2)(Register Rt, Register adr);
2718 typedef void (MacroAssembler::* mem_float_insn)(FloatRegister Rt, const Address &adr);
2719 typedef void (MacroAssembler::* mem_vector_insn)(FloatRegister Rt,
2720 MacroAssembler::SIMD_RegVariant T, const Address &adr);
2721
2722 // Used for all non-volatile memory accesses. The use of
2723 // $mem->opcode() to discover whether this pattern uses sign-extended
2724 // offsets is something of a kludge.
2725 static void loadStore(C2_MacroAssembler masm, mem_insn insn,
2726 Register reg, int opcode,
2727 Register base, int index, int scale, int disp,
2728 int size_in_memory)
2729 {
2730 Address addr = mem2address(opcode, base, index, scale, disp);
2731 if (addr.getMode() == Address::base_plus_offset) {
2732 /* If we get an out-of-range offset it is a bug in the compiler,
2733 so we assert here. */
2734 assert(Address::offset_ok_for_immed(addr.offset(), exact_log2(size_in_memory)),
2735 "c2 compiler bug");
2736 /* Fix up any out-of-range offsets. */
2737 assert_different_registers(rscratch1, base);
2738 assert_different_registers(rscratch1, reg);
2739 addr = masm.legitimize_address(addr, size_in_memory, rscratch1);
2740 }
2741 (masm.*insn)(reg, addr);
2742 }
2743
2744 static void loadStore(C2_MacroAssembler masm, mem_float_insn insn,
2745 FloatRegister reg, int opcode,
2746 Register base, int index, int size, int disp,
2747 int size_in_memory)
2748 {
2749 Address::extend scale;
2750
2751 switch (opcode) {
2752 case INDINDEXSCALEDI2L:
2753 case INDINDEXSCALEDI2LN:
2754 scale = Address::sxtw(size);
2755 break;
2756 default:
2757 scale = Address::lsl(size);
2758 }
2759
2760 if (index == -1) {
2761 /* If we get an out-of-range offset it is a bug in the compiler,
2762 so we assert here. */
2763 assert(Address::offset_ok_for_immed(disp, exact_log2(size_in_memory)), "c2 compiler bug");
2764 /* Fix up any out-of-range offsets. */
2765 assert_different_registers(rscratch1, base);
2766 Address addr = Address(base, disp);
2767 addr = masm.legitimize_address(addr, size_in_memory, rscratch1);
2768 (masm.*insn)(reg, addr);
2769 } else {
2770 assert(disp == 0, "unsupported address mode: disp = %d", disp);
2771 (masm.*insn)(reg, Address(base, as_Register(index), scale));
2772 }
2773 }
2774
2775 static void loadStore(C2_MacroAssembler masm, mem_vector_insn insn,
2776 FloatRegister reg, MacroAssembler::SIMD_RegVariant T,
2777 int opcode, Register base, int index, int size, int disp)
2778 {
2779 if (index == -1) {
2780 (masm.*insn)(reg, T, Address(base, disp));
2781 } else {
2782 assert(disp == 0, "unsupported address mode");
2783 (masm.*insn)(reg, T, Address(base, as_Register(index), Address::lsl(size)));
2784 }
2785 }
2786
2787 %}
2788
2789
2790
2791 //----------ENCODING BLOCK-----------------------------------------------------
2792 // This block specifies the encoding classes used by the compiler to
2793 // output byte streams. Encoding classes are parameterized macros
2794 // used by Machine Instruction Nodes in order to generate the bit
2795 // encoding of the instruction. Operands specify their base encoding
2796 // interface with the interface keyword. There are currently
2797 // supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, &
2798 // COND_INTER. REG_INTER causes an operand to generate a function
2799 // which returns its register number when queried. CONST_INTER causes
2800 // an operand to generate a function which returns the value of the
2801 // constant when queried. MEMORY_INTER causes an operand to generate
2802 // four functions which return the Base Register, the Index Register,
2803 // the Scale Value, and the Offset Value of the operand when queried.
2804 // COND_INTER causes an operand to generate six functions which return
2805 // the encoding code (ie - encoding bits for the instruction)
2806 // associated with each basic boolean condition for a conditional
2807 // instruction.
2808 //
2809 // Instructions specify two basic values for encoding. Again, a
2810 // function is available to check if the constant displacement is an
2811 // oop. They use the ins_encode keyword to specify their encoding
2812 // classes (which must be a sequence of enc_class names, and their
2813 // parameters, specified in the encoding block), and they use the
2814 // opcode keyword to specify, in order, their primary, secondary, and
2815 // tertiary opcode. Only the opcode sections which a particular
2816 // instruction needs for encoding need to be specified.
2817 encode %{
2818 // Build emit functions for each basic byte or larger field in the
2819 // intel encoding scheme (opcode, rm, sib, immediate), and call them
2820 // from C++ code in the enc_class source block. Emit functions will
2821 // live in the main source block for now. In future, we can
2822 // generalize this by adding a syntax that specifies the sizes of
2823 // fields in an order, so that the adlc can build the emit functions
2824 // automagically
2825
2826 // catch all for unimplemented encodings
2827 enc_class enc_unimplemented %{
2828 C2_MacroAssembler _masm(&cbuf);
2829 __ unimplemented("C2 catch all");
2830 %}
2831
2832 // BEGIN Non-volatile memory access
2833
2834 // This encoding class is generated automatically from ad_encode.m4.
2835 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
2836 enc_class aarch64_enc_ldrsbw(iRegI dst, memory1 mem) %{
2837 Register dst_reg = as_Register($dst$$reg);
2838 loadStore(C2_MacroAssembler(&cbuf), &MacroAssembler::ldrsbw, dst_reg, $mem->opcode(),
2839 as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp, 1);
2840 %}
2841
2842 // This encoding class is generated automatically from ad_encode.m4.
2843 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
2844 enc_class aarch64_enc_ldrsb(iRegI dst, memory1 mem) %{
2845 Register dst_reg = as_Register($dst$$reg);
2846 loadStore(C2_MacroAssembler(&cbuf), &MacroAssembler::ldrsb, dst_reg, $mem->opcode(),
2847 as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp, 1);
2848 %}
2849
2850 // This encoding class is generated automatically from ad_encode.m4.
2851 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
2852 enc_class aarch64_enc_ldrb(iRegI dst, memory1 mem) %{
2853 Register dst_reg = as_Register($dst$$reg);
2854 loadStore(C2_MacroAssembler(&cbuf), &MacroAssembler::ldrb, dst_reg, $mem->opcode(),
2855 as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp, 1);
2856 %}
2857
2858 // This encoding class is generated automatically from ad_encode.m4.
2859 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
2860 enc_class aarch64_enc_ldrb(iRegL dst, memory1 mem) %{
2861 Register dst_reg = as_Register($dst$$reg);
2862 loadStore(C2_MacroAssembler(&cbuf), &MacroAssembler::ldrb, dst_reg, $mem->opcode(),
2863 as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp, 1);
2864 %}
2865
2866 // This encoding class is generated automatically from ad_encode.m4.
2867 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
2868 enc_class aarch64_enc_ldrshw(iRegI dst, memory2 mem) %{
2869 Register dst_reg = as_Register($dst$$reg);
2870 loadStore(C2_MacroAssembler(&cbuf), &MacroAssembler::ldrshw, dst_reg, $mem->opcode(),
2871 as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp, 2);
2872 %}
2873
2874 // This encoding class is generated automatically from ad_encode.m4.
2875 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
2876 enc_class aarch64_enc_ldrsh(iRegI dst, memory2 mem) %{
2877 Register dst_reg = as_Register($dst$$reg);
2878 loadStore(C2_MacroAssembler(&cbuf), &MacroAssembler::ldrsh, dst_reg, $mem->opcode(),
2879 as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp, 2);
2880 %}
2881
2882 // This encoding class is generated automatically from ad_encode.m4.
2883 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
2884 enc_class aarch64_enc_ldrh(iRegI dst, memory2 mem) %{
2885 Register dst_reg = as_Register($dst$$reg);
2886 loadStore(C2_MacroAssembler(&cbuf), &MacroAssembler::ldrh, dst_reg, $mem->opcode(),
2887 as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp, 2);
2888 %}
2889
2890 // This encoding class is generated automatically from ad_encode.m4.
2891 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
2892 enc_class aarch64_enc_ldrh(iRegL dst, memory2 mem) %{
2893 Register dst_reg = as_Register($dst$$reg);
2894 loadStore(C2_MacroAssembler(&cbuf), &MacroAssembler::ldrh, dst_reg, $mem->opcode(),
2895 as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp, 2);
2896 %}
2897
2898 // This encoding class is generated automatically from ad_encode.m4.
2899 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
2900 enc_class aarch64_enc_ldrw(iRegI dst, memory4 mem) %{
2901 Register dst_reg = as_Register($dst$$reg);
2902 loadStore(C2_MacroAssembler(&cbuf), &MacroAssembler::ldrw, dst_reg, $mem->opcode(),
2903 as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp, 4);
2904 %}
2905
2906 // This encoding class is generated automatically from ad_encode.m4.
2907 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
2908 enc_class aarch64_enc_ldrw(iRegL dst, memory4 mem) %{
2909 Register dst_reg = as_Register($dst$$reg);
2910 loadStore(C2_MacroAssembler(&cbuf), &MacroAssembler::ldrw, dst_reg, $mem->opcode(),
2911 as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp, 4);
2912 %}
2913
2914 // This encoding class is generated automatically from ad_encode.m4.
2915 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
2916 enc_class aarch64_enc_ldrsw(iRegL dst, memory4 mem) %{
2917 Register dst_reg = as_Register($dst$$reg);
2918 loadStore(C2_MacroAssembler(&cbuf), &MacroAssembler::ldrsw, dst_reg, $mem->opcode(),
2919 as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp, 4);
2920 %}
2921
2922 // This encoding class is generated automatically from ad_encode.m4.
2923 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
2924 enc_class aarch64_enc_ldr(iRegL dst, memory8 mem) %{
2925 Register dst_reg = as_Register($dst$$reg);
2926 loadStore(C2_MacroAssembler(&cbuf), &MacroAssembler::ldr, dst_reg, $mem->opcode(),
2927 as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp, 8);
2928 %}
2929
2930 // This encoding class is generated automatically from ad_encode.m4.
2931 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
2932 enc_class aarch64_enc_ldrs(vRegF dst, memory4 mem) %{
2933 FloatRegister dst_reg = as_FloatRegister($dst$$reg);
2934 loadStore(C2_MacroAssembler(&cbuf), &MacroAssembler::ldrs, dst_reg, $mem->opcode(),
2935 as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp, 4);
2936 %}
2937
2938 // This encoding class is generated automatically from ad_encode.m4.
2939 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
2940 enc_class aarch64_enc_ldrd(vRegD dst, memory8 mem) %{
2941 FloatRegister dst_reg = as_FloatRegister($dst$$reg);
2942 loadStore(C2_MacroAssembler(&cbuf), &MacroAssembler::ldrd, dst_reg, $mem->opcode(),
2943 as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp, 8);
2944 %}
2945
2946 // This encoding class is generated automatically from ad_encode.m4.
2947 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
2948 enc_class aarch64_enc_strb(iRegI src, memory1 mem) %{
2949 Register src_reg = as_Register($src$$reg);
2950 loadStore(C2_MacroAssembler(&cbuf), &MacroAssembler::strb, src_reg, $mem->opcode(),
2951 as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp, 1);
2952 %}
2953
2954 // This encoding class is generated automatically from ad_encode.m4.
2955 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
2956 enc_class aarch64_enc_strb0(memory1 mem) %{
2957 C2_MacroAssembler _masm(&cbuf);
2958 loadStore(_masm, &MacroAssembler::strb, zr, $mem->opcode(),
2959 as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp, 1);
2960 %}
2961
2962 // This encoding class is generated automatically from ad_encode.m4.
2963 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
2964 enc_class aarch64_enc_strh(iRegI src, memory2 mem) %{
2965 Register src_reg = as_Register($src$$reg);
2966 loadStore(C2_MacroAssembler(&cbuf), &MacroAssembler::strh, src_reg, $mem->opcode(),
2967 as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp, 2);
2968 %}
2969
2970 // This encoding class is generated automatically from ad_encode.m4.
2971 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
2972 enc_class aarch64_enc_strh0(memory2 mem) %{
2973 C2_MacroAssembler _masm(&cbuf);
2974 loadStore(_masm, &MacroAssembler::strh, zr, $mem->opcode(),
2975 as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp, 2);
2976 %}
2977
2978 // This encoding class is generated automatically from ad_encode.m4.
2979 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
2980 enc_class aarch64_enc_strw(iRegI src, memory4 mem) %{
2981 Register src_reg = as_Register($src$$reg);
2982 loadStore(C2_MacroAssembler(&cbuf), &MacroAssembler::strw, src_reg, $mem->opcode(),
2983 as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp, 4);
2984 %}
2985
2986 // This encoding class is generated automatically from ad_encode.m4.
2987 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
2988 enc_class aarch64_enc_strw0(memory4 mem) %{
2989 C2_MacroAssembler _masm(&cbuf);
2990 loadStore(_masm, &MacroAssembler::strw, zr, $mem->opcode(),
2991 as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp, 4);
2992 %}
2993
2994 // This encoding class is generated automatically from ad_encode.m4.
2995 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
2996 enc_class aarch64_enc_str(iRegL src, memory8 mem) %{
2997 Register src_reg = as_Register($src$$reg);
2998 // we sometimes get asked to store the stack pointer into the
2999 // current thread -- we cannot do that directly on AArch64
3000 if (src_reg == r31_sp) {
3001 C2_MacroAssembler _masm(&cbuf);
3002 assert(as_Register($mem$$base) == rthread, "unexpected store for sp");
3003 __ mov(rscratch2, sp);
3004 src_reg = rscratch2;
3005 }
3006 loadStore(C2_MacroAssembler(&cbuf), &MacroAssembler::str, src_reg, $mem->opcode(),
3007 as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp, 8);
3008 %}
3009
3010 // This encoding class is generated automatically from ad_encode.m4.
3011 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
3012 enc_class aarch64_enc_str0(memory8 mem) %{
3013 C2_MacroAssembler _masm(&cbuf);
3014 loadStore(_masm, &MacroAssembler::str, zr, $mem->opcode(),
3015 as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp, 8);
3016 %}
3017
3018 // This encoding class is generated automatically from ad_encode.m4.
3019 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
3020 enc_class aarch64_enc_strs(vRegF src, memory4 mem) %{
3021 FloatRegister src_reg = as_FloatRegister($src$$reg);
3022 loadStore(C2_MacroAssembler(&cbuf), &MacroAssembler::strs, src_reg, $mem->opcode(),
3023 as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp, 4);
3024 %}
3025
3026 // This encoding class is generated automatically from ad_encode.m4.
3027 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
3028 enc_class aarch64_enc_strd(vRegD src, memory8 mem) %{
3029 FloatRegister src_reg = as_FloatRegister($src$$reg);
3030 loadStore(C2_MacroAssembler(&cbuf), &MacroAssembler::strd, src_reg, $mem->opcode(),
3031 as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp, 8);
3032 %}
3033
3034 // This encoding class is generated automatically from ad_encode.m4.
3035 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
3036 enc_class aarch64_enc_strb0_ordered(memory4 mem) %{
3037 C2_MacroAssembler _masm(&cbuf);
3038 __ membar(Assembler::StoreStore);
3039 loadStore(_masm, &MacroAssembler::strb, zr, $mem->opcode(),
3040 as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp, 1);
3041 %}
3042
3043 // END Non-volatile memory access
3044
3045 // Vector loads and stores
3046 enc_class aarch64_enc_ldrvH(vReg dst, memory mem) %{
3047 FloatRegister dst_reg = as_FloatRegister($dst$$reg);
3048 loadStore(C2_MacroAssembler(&cbuf), &MacroAssembler::ldr, dst_reg, MacroAssembler::H,
3049 $mem->opcode(), as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
3050 %}
3051
3052 enc_class aarch64_enc_ldrvS(vReg dst, memory mem) %{
3053 FloatRegister dst_reg = as_FloatRegister($dst$$reg);
3054 loadStore(C2_MacroAssembler(&cbuf), &MacroAssembler::ldr, dst_reg, MacroAssembler::S,
3055 $mem->opcode(), as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
3056 %}
3057
3058 enc_class aarch64_enc_ldrvD(vReg dst, memory mem) %{
3059 FloatRegister dst_reg = as_FloatRegister($dst$$reg);
3060 loadStore(C2_MacroAssembler(&cbuf), &MacroAssembler::ldr, dst_reg, MacroAssembler::D,
3061 $mem->opcode(), as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
3062 %}
3063
3064 enc_class aarch64_enc_ldrvQ(vReg dst, memory mem) %{
3065 FloatRegister dst_reg = as_FloatRegister($dst$$reg);
3066 loadStore(C2_MacroAssembler(&cbuf), &MacroAssembler::ldr, dst_reg, MacroAssembler::Q,
3067 $mem->opcode(), as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
3068 %}
3069
3070 enc_class aarch64_enc_strvH(vReg src, memory mem) %{
3071 FloatRegister src_reg = as_FloatRegister($src$$reg);
3072 loadStore(C2_MacroAssembler(&cbuf), &MacroAssembler::str, src_reg, MacroAssembler::H,
3073 $mem->opcode(), as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
3074 %}
3075
3076 enc_class aarch64_enc_strvS(vReg src, memory mem) %{
3077 FloatRegister src_reg = as_FloatRegister($src$$reg);
3078 loadStore(C2_MacroAssembler(&cbuf), &MacroAssembler::str, src_reg, MacroAssembler::S,
3079 $mem->opcode(), as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
3080 %}
3081
3082 enc_class aarch64_enc_strvD(vReg src, memory mem) %{
3083 FloatRegister src_reg = as_FloatRegister($src$$reg);
3084 loadStore(C2_MacroAssembler(&cbuf), &MacroAssembler::str, src_reg, MacroAssembler::D,
3085 $mem->opcode(), as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
3086 %}
3087
3088 enc_class aarch64_enc_strvQ(vReg src, memory mem) %{
3089 FloatRegister src_reg = as_FloatRegister($src$$reg);
3090 loadStore(C2_MacroAssembler(&cbuf), &MacroAssembler::str, src_reg, MacroAssembler::Q,
3091 $mem->opcode(), as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
3092 %}
3093
3094 // volatile loads and stores
3095
3096 enc_class aarch64_enc_stlrb(iRegI src, memory mem) %{
3097 MOV_VOLATILE(as_Register($src$$reg), $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
3098 rscratch1, stlrb);
3099 %}
3100
3101 enc_class aarch64_enc_stlrb0(memory mem) %{
3102 MOV_VOLATILE(zr, $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
3103 rscratch1, stlrb);
3104 %}
3105
3106 enc_class aarch64_enc_stlrh(iRegI src, memory mem) %{
3107 MOV_VOLATILE(as_Register($src$$reg), $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
3108 rscratch1, stlrh);
3109 %}
3110
3111 enc_class aarch64_enc_stlrh0(memory mem) %{
3112 MOV_VOLATILE(zr, $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
3113 rscratch1, stlrh);
3114 %}
3115
3116 enc_class aarch64_enc_stlrw(iRegI src, memory mem) %{
3117 MOV_VOLATILE(as_Register($src$$reg), $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
3118 rscratch1, stlrw);
3119 %}
3120
3121 enc_class aarch64_enc_stlrw0(memory mem) %{
3122 MOV_VOLATILE(zr, $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
3123 rscratch1, stlrw);
3124 %}
3125
3126 enc_class aarch64_enc_ldarsbw(iRegI dst, memory mem) %{
3127 Register dst_reg = as_Register($dst$$reg);
3128 MOV_VOLATILE(dst_reg, $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
3129 rscratch1, ldarb);
3130 __ sxtbw(dst_reg, dst_reg);
3131 %}
3132
3133 enc_class aarch64_enc_ldarsb(iRegL dst, memory mem) %{
3134 Register dst_reg = as_Register($dst$$reg);
3135 MOV_VOLATILE(dst_reg, $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
3136 rscratch1, ldarb);
3137 __ sxtb(dst_reg, dst_reg);
3138 %}
3139
3140 enc_class aarch64_enc_ldarbw(iRegI dst, memory mem) %{
3141 MOV_VOLATILE(as_Register($dst$$reg), $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
3142 rscratch1, ldarb);
3143 %}
3144
3145 enc_class aarch64_enc_ldarb(iRegL dst, memory mem) %{
3146 MOV_VOLATILE(as_Register($dst$$reg), $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
3147 rscratch1, ldarb);
3148 %}
3149
3150 enc_class aarch64_enc_ldarshw(iRegI dst, memory mem) %{
3151 Register dst_reg = as_Register($dst$$reg);
3152 MOV_VOLATILE(dst_reg, $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
3153 rscratch1, ldarh);
3154 __ sxthw(dst_reg, dst_reg);
3155 %}
3156
3157 enc_class aarch64_enc_ldarsh(iRegL dst, memory mem) %{
3158 Register dst_reg = as_Register($dst$$reg);
3159 MOV_VOLATILE(dst_reg, $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
3160 rscratch1, ldarh);
3161 __ sxth(dst_reg, dst_reg);
3162 %}
3163
3164 enc_class aarch64_enc_ldarhw(iRegI dst, memory mem) %{
3165 MOV_VOLATILE(as_Register($dst$$reg), $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
3166 rscratch1, ldarh);
3167 %}
3168
3169 enc_class aarch64_enc_ldarh(iRegL dst, memory mem) %{
3170 MOV_VOLATILE(as_Register($dst$$reg), $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
3171 rscratch1, ldarh);
3172 %}
3173
3174 enc_class aarch64_enc_ldarw(iRegI dst, memory mem) %{
3175 MOV_VOLATILE(as_Register($dst$$reg), $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
3176 rscratch1, ldarw);
3177 %}
3178
3179 enc_class aarch64_enc_ldarw(iRegL dst, memory mem) %{
3180 MOV_VOLATILE(as_Register($dst$$reg), $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
3181 rscratch1, ldarw);
3182 %}
3183
3184 enc_class aarch64_enc_ldar(iRegL dst, memory mem) %{
3185 MOV_VOLATILE(as_Register($dst$$reg), $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
3186 rscratch1, ldar);
3187 %}
3188
3189 enc_class aarch64_enc_fldars(vRegF dst, memory mem) %{
3190 MOV_VOLATILE(rscratch1, $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
3191 rscratch1, ldarw);
3192 __ fmovs(as_FloatRegister($dst$$reg), rscratch1);
3193 %}
3194
3195 enc_class aarch64_enc_fldard(vRegD dst, memory mem) %{
3196 MOV_VOLATILE(rscratch1, $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
3197 rscratch1, ldar);
3198 __ fmovd(as_FloatRegister($dst$$reg), rscratch1);
3199 %}
3200
3201 enc_class aarch64_enc_stlr(iRegL src, memory mem) %{
3202 Register src_reg = as_Register($src$$reg);
3203 // we sometimes get asked to store the stack pointer into the
3204 // current thread -- we cannot do that directly on AArch64
3205 if (src_reg == r31_sp) {
3206 C2_MacroAssembler _masm(&cbuf);
3207 assert(as_Register($mem$$base) == rthread, "unexpected store for sp");
3208 __ mov(rscratch2, sp);
3209 src_reg = rscratch2;
3210 }
3211 MOV_VOLATILE(src_reg, $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
3212 rscratch1, stlr);
3213 %}
3214
3215 enc_class aarch64_enc_stlr0(memory mem) %{
3216 MOV_VOLATILE(zr, $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
3217 rscratch1, stlr);
3218 %}
3219
3220 enc_class aarch64_enc_fstlrs(vRegF src, memory mem) %{
3221 {
3222 C2_MacroAssembler _masm(&cbuf);
3223 FloatRegister src_reg = as_FloatRegister($src$$reg);
3224 __ fmovs(rscratch2, src_reg);
3225 }
3226 MOV_VOLATILE(rscratch2, $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
3227 rscratch1, stlrw);
3228 %}
3229
3230 enc_class aarch64_enc_fstlrd(vRegD src, memory mem) %{
3231 {
3232 C2_MacroAssembler _masm(&cbuf);
3233 FloatRegister src_reg = as_FloatRegister($src$$reg);
3234 __ fmovd(rscratch2, src_reg);
3235 }
3236 MOV_VOLATILE(rscratch2, $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
3237 rscratch1, stlr);
3238 %}
3239
3240 // synchronized read/update encodings
3241
3242 enc_class aarch64_enc_ldaxr(iRegL dst, memory8 mem) %{
3243 C2_MacroAssembler _masm(&cbuf);
3244 Register dst_reg = as_Register($dst$$reg);
3245 Register base = as_Register($mem$$base);
3246 int index = $mem$$index;
3247 int scale = $mem$$scale;
3248 int disp = $mem$$disp;
3249 if (index == -1) {
3250 if (disp != 0) {
3251 __ lea(rscratch1, Address(base, disp));
3252 __ ldaxr(dst_reg, rscratch1);
3253 } else {
3254 // TODO
3255 // should we ever get anything other than this case?
3256 __ ldaxr(dst_reg, base);
3257 }
3258 } else {
3259 Register index_reg = as_Register(index);
3260 if (disp == 0) {
3261 __ lea(rscratch1, Address(base, index_reg, Address::lsl(scale)));
3262 __ ldaxr(dst_reg, rscratch1);
3263 } else {
3264 __ lea(rscratch1, Address(base, disp));
3265 __ lea(rscratch1, Address(rscratch1, index_reg, Address::lsl(scale)));
3266 __ ldaxr(dst_reg, rscratch1);
3267 }
3268 }
3269 %}
3270
3271 enc_class aarch64_enc_stlxr(iRegLNoSp src, memory8 mem) %{
3272 C2_MacroAssembler _masm(&cbuf);
3273 Register src_reg = as_Register($src$$reg);
3274 Register base = as_Register($mem$$base);
3275 int index = $mem$$index;
3276 int scale = $mem$$scale;
3277 int disp = $mem$$disp;
3278 if (index == -1) {
3279 if (disp != 0) {
3280 __ lea(rscratch2, Address(base, disp));
3281 __ stlxr(rscratch1, src_reg, rscratch2);
3282 } else {
3283 // TODO
3284 // should we ever get anything other than this case?
3285 __ stlxr(rscratch1, src_reg, base);
3286 }
3287 } else {
3288 Register index_reg = as_Register(index);
3289 if (disp == 0) {
3290 __ lea(rscratch2, Address(base, index_reg, Address::lsl(scale)));
3291 __ stlxr(rscratch1, src_reg, rscratch2);
3292 } else {
3293 __ lea(rscratch2, Address(base, disp));
3294 __ lea(rscratch2, Address(rscratch2, index_reg, Address::lsl(scale)));
3295 __ stlxr(rscratch1, src_reg, rscratch2);
3296 }
3297 }
3298 __ cmpw(rscratch1, zr);
3299 %}
3300
3301 enc_class aarch64_enc_cmpxchg(memory mem, iRegLNoSp oldval, iRegLNoSp newval) %{
3302 C2_MacroAssembler _masm(&cbuf);
3303 guarantee($mem$$index == -1 && $mem$$disp == 0, "impossible encoding");
3304 __ cmpxchg($mem$$base$$Register, $oldval$$Register, $newval$$Register,
3305 Assembler::xword, /*acquire*/ false, /*release*/ true,
3306 /*weak*/ false, noreg);
3307 %}
3308
3309 enc_class aarch64_enc_cmpxchgw(memory mem, iRegINoSp oldval, iRegINoSp newval) %{
3310 C2_MacroAssembler _masm(&cbuf);
3311 guarantee($mem$$index == -1 && $mem$$disp == 0, "impossible encoding");
3312 __ cmpxchg($mem$$base$$Register, $oldval$$Register, $newval$$Register,
3313 Assembler::word, /*acquire*/ false, /*release*/ true,
3314 /*weak*/ false, noreg);
3315 %}
3316
3317 enc_class aarch64_enc_cmpxchgs(memory mem, iRegINoSp oldval, iRegINoSp newval) %{
3318 C2_MacroAssembler _masm(&cbuf);
3319 guarantee($mem$$index == -1 && $mem$$disp == 0, "impossible encoding");
3320 __ cmpxchg($mem$$base$$Register, $oldval$$Register, $newval$$Register,
3321 Assembler::halfword, /*acquire*/ false, /*release*/ true,
3322 /*weak*/ false, noreg);
3323 %}
3324
3325 enc_class aarch64_enc_cmpxchgb(memory mem, iRegINoSp oldval, iRegINoSp newval) %{
3326 C2_MacroAssembler _masm(&cbuf);
3327 guarantee($mem$$index == -1 && $mem$$disp == 0, "impossible encoding");
3328 __ cmpxchg($mem$$base$$Register, $oldval$$Register, $newval$$Register,
3329 Assembler::byte, /*acquire*/ false, /*release*/ true,
3330 /*weak*/ false, noreg);
3331 %}
3332
3333
3334 // The only difference between aarch64_enc_cmpxchg and
3335 // aarch64_enc_cmpxchg_acq is that we use load-acquire in the
3336 // CompareAndSwap sequence to serve as a barrier on acquiring a
3337 // lock.
3338 enc_class aarch64_enc_cmpxchg_acq(memory mem, iRegLNoSp oldval, iRegLNoSp newval) %{
3339 C2_MacroAssembler _masm(&cbuf);
3340 guarantee($mem$$index == -1 && $mem$$disp == 0, "impossible encoding");
3341 __ cmpxchg($mem$$base$$Register, $oldval$$Register, $newval$$Register,
3342 Assembler::xword, /*acquire*/ true, /*release*/ true,
3343 /*weak*/ false, noreg);
3344 %}
3345
3346 enc_class aarch64_enc_cmpxchgw_acq(memory mem, iRegINoSp oldval, iRegINoSp newval) %{
3347 C2_MacroAssembler _masm(&cbuf);
3348 guarantee($mem$$index == -1 && $mem$$disp == 0, "impossible encoding");
3349 __ cmpxchg($mem$$base$$Register, $oldval$$Register, $newval$$Register,
3350 Assembler::word, /*acquire*/ true, /*release*/ true,
3351 /*weak*/ false, noreg);
3352 %}
3353
3354 enc_class aarch64_enc_cmpxchgs_acq(memory mem, iRegINoSp oldval, iRegINoSp newval) %{
3355 C2_MacroAssembler _masm(&cbuf);
3356 guarantee($mem$$index == -1 && $mem$$disp == 0, "impossible encoding");
3357 __ cmpxchg($mem$$base$$Register, $oldval$$Register, $newval$$Register,
3358 Assembler::halfword, /*acquire*/ true, /*release*/ true,
3359 /*weak*/ false, noreg);
3360 %}
3361
3362 enc_class aarch64_enc_cmpxchgb_acq(memory mem, iRegINoSp oldval, iRegINoSp newval) %{
3363 C2_MacroAssembler _masm(&cbuf);
3364 guarantee($mem$$index == -1 && $mem$$disp == 0, "impossible encoding");
3365 __ cmpxchg($mem$$base$$Register, $oldval$$Register, $newval$$Register,
3366 Assembler::byte, /*acquire*/ true, /*release*/ true,
3367 /*weak*/ false, noreg);
3368 %}
3369
3370 // auxiliary used for CompareAndSwapX to set result register
3371 enc_class aarch64_enc_cset_eq(iRegINoSp res) %{
3372 C2_MacroAssembler _masm(&cbuf);
3373 Register res_reg = as_Register($res$$reg);
3374 __ cset(res_reg, Assembler::EQ);
3375 %}
3376
3377 // prefetch encodings
3378
3379 enc_class aarch64_enc_prefetchw(memory mem) %{
3380 C2_MacroAssembler _masm(&cbuf);
3381 Register base = as_Register($mem$$base);
3382 int index = $mem$$index;
3383 int scale = $mem$$scale;
3384 int disp = $mem$$disp;
3385 if (index == -1) {
3386 __ prfm(Address(base, disp), PSTL1KEEP);
3387 } else {
3388 Register index_reg = as_Register(index);
3389 if (disp == 0) {
3390 __ prfm(Address(base, index_reg, Address::lsl(scale)), PSTL1KEEP);
3391 } else {
3392 __ lea(rscratch1, Address(base, disp));
3393 __ prfm(Address(rscratch1, index_reg, Address::lsl(scale)), PSTL1KEEP);
3394 }
3395 }
3396 %}
3397
3398 /// mov envcodings
3399
3400 enc_class aarch64_enc_movw_imm(iRegI dst, immI src) %{
3401 C2_MacroAssembler _masm(&cbuf);
3402 uint32_t con = (uint32_t)$src$$constant;
3403 Register dst_reg = as_Register($dst$$reg);
3404 if (con == 0) {
3405 __ movw(dst_reg, zr);
3406 } else {
3407 __ movw(dst_reg, con);
3408 }
3409 %}
3410
3411 enc_class aarch64_enc_mov_imm(iRegL dst, immL src) %{
3412 C2_MacroAssembler _masm(&cbuf);
3413 Register dst_reg = as_Register($dst$$reg);
3414 uint64_t con = (uint64_t)$src$$constant;
3415 if (con == 0) {
3416 __ mov(dst_reg, zr);
3417 } else {
3418 __ mov(dst_reg, con);
3419 }
3420 %}
3421
3422 enc_class aarch64_enc_mov_p(iRegP dst, immP src) %{
3423 C2_MacroAssembler _masm(&cbuf);
3424 Register dst_reg = as_Register($dst$$reg);
3425 address con = (address)$src$$constant;
3426 if (con == NULL || con == (address)1) {
3427 ShouldNotReachHere();
3428 } else {
3429 relocInfo::relocType rtype = $src->constant_reloc();
3430 if (rtype == relocInfo::oop_type) {
3431 __ movoop(dst_reg, (jobject)con);
3432 } else if (rtype == relocInfo::metadata_type) {
3433 __ mov_metadata(dst_reg, (Metadata*)con);
3434 } else {
3435 assert(rtype == relocInfo::none, "unexpected reloc type");
3436 if (! __ is_valid_AArch64_address(con) ||
3437 con < (address)(uintptr_t)os::vm_page_size()) {
3438 __ mov(dst_reg, con);
3439 } else {
3440 uint64_t offset;
3441 __ adrp(dst_reg, con, offset);
3442 __ add(dst_reg, dst_reg, offset);
3443 }
3444 }
3445 }
3446 %}
3447
3448 enc_class aarch64_enc_mov_p0(iRegP dst, immP0 src) %{
3449 C2_MacroAssembler _masm(&cbuf);
3450 Register dst_reg = as_Register($dst$$reg);
3451 __ mov(dst_reg, zr);
3452 %}
3453
3454 enc_class aarch64_enc_mov_p1(iRegP dst, immP_1 src) %{
3455 C2_MacroAssembler _masm(&cbuf);
3456 Register dst_reg = as_Register($dst$$reg);
3457 __ mov(dst_reg, (uint64_t)1);
3458 %}
3459
3460 enc_class aarch64_enc_mov_byte_map_base(iRegP dst, immByteMapBase src) %{
3461 C2_MacroAssembler _masm(&cbuf);
3462 __ load_byte_map_base($dst$$Register);
3463 %}
3464
3465 enc_class aarch64_enc_mov_n(iRegN dst, immN src) %{
3466 C2_MacroAssembler _masm(&cbuf);
3467 Register dst_reg = as_Register($dst$$reg);
3468 address con = (address)$src$$constant;
3469 if (con == NULL) {
3470 ShouldNotReachHere();
3471 } else {
3472 relocInfo::relocType rtype = $src->constant_reloc();
3473 assert(rtype == relocInfo::oop_type, "unexpected reloc type");
3474 __ set_narrow_oop(dst_reg, (jobject)con);
3475 }
3476 %}
3477
3478 enc_class aarch64_enc_mov_n0(iRegN dst, immN0 src) %{
3479 C2_MacroAssembler _masm(&cbuf);
3480 Register dst_reg = as_Register($dst$$reg);
3481 __ mov(dst_reg, zr);
3482 %}
3483
3484 enc_class aarch64_enc_mov_nk(iRegN dst, immNKlass src) %{
3485 C2_MacroAssembler _masm(&cbuf);
3486 Register dst_reg = as_Register($dst$$reg);
3487 address con = (address)$src$$constant;
3488 if (con == NULL) {
3489 ShouldNotReachHere();
3490 } else {
3491 relocInfo::relocType rtype = $src->constant_reloc();
3492 assert(rtype == relocInfo::metadata_type, "unexpected reloc type");
3493 __ set_narrow_klass(dst_reg, (Klass *)con);
3494 }
3495 %}
3496
3497 // arithmetic encodings
3498
3499 enc_class aarch64_enc_addsubw_imm(iRegI dst, iRegI src1, immIAddSub src2) %{
3500 C2_MacroAssembler _masm(&cbuf);
3501 Register dst_reg = as_Register($dst$$reg);
3502 Register src_reg = as_Register($src1$$reg);
3503 int32_t con = (int32_t)$src2$$constant;
3504 // add has primary == 0, subtract has primary == 1
3505 if ($primary) { con = -con; }
3506 if (con < 0) {
3507 __ subw(dst_reg, src_reg, -con);
3508 } else {
3509 __ addw(dst_reg, src_reg, con);
3510 }
3511 %}
3512
3513 enc_class aarch64_enc_addsub_imm(iRegL dst, iRegL src1, immLAddSub src2) %{
3514 C2_MacroAssembler _masm(&cbuf);
3515 Register dst_reg = as_Register($dst$$reg);
3516 Register src_reg = as_Register($src1$$reg);
3517 int32_t con = (int32_t)$src2$$constant;
3518 // add has primary == 0, subtract has primary == 1
3519 if ($primary) { con = -con; }
3520 if (con < 0) {
3521 __ sub(dst_reg, src_reg, -con);
3522 } else {
3523 __ add(dst_reg, src_reg, con);
3524 }
3525 %}
3526
3527 enc_class aarch64_enc_divw(iRegI dst, iRegI src1, iRegI src2) %{
3528 C2_MacroAssembler _masm(&cbuf);
3529 Register dst_reg = as_Register($dst$$reg);
3530 Register src1_reg = as_Register($src1$$reg);
3531 Register src2_reg = as_Register($src2$$reg);
3532 __ corrected_idivl(dst_reg, src1_reg, src2_reg, false, rscratch1);
3533 %}
3534
3535 enc_class aarch64_enc_div(iRegI dst, iRegI src1, iRegI src2) %{
3536 C2_MacroAssembler _masm(&cbuf);
3537 Register dst_reg = as_Register($dst$$reg);
3538 Register src1_reg = as_Register($src1$$reg);
3539 Register src2_reg = as_Register($src2$$reg);
3540 __ corrected_idivq(dst_reg, src1_reg, src2_reg, false, rscratch1);
3541 %}
3542
3543 enc_class aarch64_enc_modw(iRegI dst, iRegI src1, iRegI src2) %{
3544 C2_MacroAssembler _masm(&cbuf);
3545 Register dst_reg = as_Register($dst$$reg);
3546 Register src1_reg = as_Register($src1$$reg);
3547 Register src2_reg = as_Register($src2$$reg);
3548 __ corrected_idivl(dst_reg, src1_reg, src2_reg, true, rscratch1);
3549 %}
3550
3551 enc_class aarch64_enc_mod(iRegI dst, iRegI src1, iRegI src2) %{
3552 C2_MacroAssembler _masm(&cbuf);
3553 Register dst_reg = as_Register($dst$$reg);
3554 Register src1_reg = as_Register($src1$$reg);
3555 Register src2_reg = as_Register($src2$$reg);
3556 __ corrected_idivq(dst_reg, src1_reg, src2_reg, true, rscratch1);
3557 %}
3558
3559 // compare instruction encodings
3560
3561 enc_class aarch64_enc_cmpw(iRegI src1, iRegI src2) %{
3562 C2_MacroAssembler _masm(&cbuf);
3563 Register reg1 = as_Register($src1$$reg);
3564 Register reg2 = as_Register($src2$$reg);
3565 __ cmpw(reg1, reg2);
3566 %}
3567
3568 enc_class aarch64_enc_cmpw_imm_addsub(iRegI src1, immIAddSub src2) %{
3569 C2_MacroAssembler _masm(&cbuf);
3570 Register reg = as_Register($src1$$reg);
3571 int32_t val = $src2$$constant;
3572 if (val >= 0) {
3573 __ subsw(zr, reg, val);
3574 } else {
3575 __ addsw(zr, reg, -val);
3576 }
3577 %}
3578
3579 enc_class aarch64_enc_cmpw_imm(iRegI src1, immI src2) %{
3580 C2_MacroAssembler _masm(&cbuf);
3581 Register reg1 = as_Register($src1$$reg);
3582 uint32_t val = (uint32_t)$src2$$constant;
3583 __ movw(rscratch1, val);
3584 __ cmpw(reg1, rscratch1);
3585 %}
3586
3587 enc_class aarch64_enc_cmp(iRegL src1, iRegL src2) %{
3588 C2_MacroAssembler _masm(&cbuf);
3589 Register reg1 = as_Register($src1$$reg);
3590 Register reg2 = as_Register($src2$$reg);
3591 __ cmp(reg1, reg2);
3592 %}
3593
3594 enc_class aarch64_enc_cmp_imm_addsub(iRegL src1, immL12 src2) %{
3595 C2_MacroAssembler _masm(&cbuf);
3596 Register reg = as_Register($src1$$reg);
3597 int64_t val = $src2$$constant;
3598 if (val >= 0) {
3599 __ subs(zr, reg, val);
3600 } else if (val != -val) {
3601 __ adds(zr, reg, -val);
3602 } else {
3603 // aargh, Long.MIN_VALUE is a special case
3604 __ orr(rscratch1, zr, (uint64_t)val);
3605 __ subs(zr, reg, rscratch1);
3606 }
3607 %}
3608
3609 enc_class aarch64_enc_cmp_imm(iRegL src1, immL src2) %{
3610 C2_MacroAssembler _masm(&cbuf);
3611 Register reg1 = as_Register($src1$$reg);
3612 uint64_t val = (uint64_t)$src2$$constant;
3613 __ mov(rscratch1, val);
3614 __ cmp(reg1, rscratch1);
3615 %}
3616
3617 enc_class aarch64_enc_cmpp(iRegP src1, iRegP src2) %{
3618 C2_MacroAssembler _masm(&cbuf);
3619 Register reg1 = as_Register($src1$$reg);
3620 Register reg2 = as_Register($src2$$reg);
3621 __ cmp(reg1, reg2);
3622 %}
3623
3624 enc_class aarch64_enc_cmpn(iRegN src1, iRegN src2) %{
3625 C2_MacroAssembler _masm(&cbuf);
3626 Register reg1 = as_Register($src1$$reg);
3627 Register reg2 = as_Register($src2$$reg);
3628 __ cmpw(reg1, reg2);
3629 %}
3630
3631 enc_class aarch64_enc_testp(iRegP src) %{
3632 C2_MacroAssembler _masm(&cbuf);
3633 Register reg = as_Register($src$$reg);
3634 __ cmp(reg, zr);
3635 %}
3636
3637 enc_class aarch64_enc_testn(iRegN src) %{
3638 C2_MacroAssembler _masm(&cbuf);
3639 Register reg = as_Register($src$$reg);
3640 __ cmpw(reg, zr);
3641 %}
3642
3643 enc_class aarch64_enc_b(label lbl) %{
3644 C2_MacroAssembler _masm(&cbuf);
3645 Label *L = $lbl$$label;
3646 __ b(*L);
3647 %}
3648
3649 enc_class aarch64_enc_br_con(cmpOp cmp, label lbl) %{
3650 C2_MacroAssembler _masm(&cbuf);
3651 Label *L = $lbl$$label;
3652 __ br ((Assembler::Condition)$cmp$$cmpcode, *L);
3653 %}
3654
3655 enc_class aarch64_enc_br_conU(cmpOpU cmp, label lbl) %{
3656 C2_MacroAssembler _masm(&cbuf);
3657 Label *L = $lbl$$label;
3658 __ br ((Assembler::Condition)$cmp$$cmpcode, *L);
3659 %}
3660
3661 enc_class aarch64_enc_partial_subtype_check(iRegP sub, iRegP super, iRegP temp, iRegP result)
3662 %{
3663 Register sub_reg = as_Register($sub$$reg);
3664 Register super_reg = as_Register($super$$reg);
3665 Register temp_reg = as_Register($temp$$reg);
3666 Register result_reg = as_Register($result$$reg);
3667
3668 Label miss;
3669 C2_MacroAssembler _masm(&cbuf);
3670 __ check_klass_subtype_slow_path(sub_reg, super_reg, temp_reg, result_reg,
3671 NULL, &miss,
3672 /*set_cond_codes:*/ true);
3673 if ($primary) {
3674 __ mov(result_reg, zr);
3675 }
3676 __ bind(miss);
3677 %}
3678
3679 enc_class aarch64_enc_java_static_call(method meth) %{
3680 C2_MacroAssembler _masm(&cbuf);
3681
3682 address addr = (address)$meth$$method;
3683 address call;
3684 if (!_method) {
3685 // A call to a runtime wrapper, e.g. new, new_typeArray_Java, uncommon_trap.
3686 call = __ trampoline_call(Address(addr, relocInfo::runtime_call_type));
3687 if (call == NULL) {
3688 ciEnv::current()->record_failure("CodeCache is full");
3689 return;
3690 }
3691 } else if (_method->intrinsic_id() == vmIntrinsicID::_ensureMaterializedForStackWalk) {
3692 // The NOP here is purely to ensure that eliding a call to
3693 // JVM_EnsureMaterializedForStackWalk doesn't change the code size.
3694 __ nop();
3695 __ block_comment("call JVM_EnsureMaterializedForStackWalk (elided)");
3696 } else {
3697 int method_index = resolved_method_index(cbuf);
3698 RelocationHolder rspec = _optimized_virtual ? opt_virtual_call_Relocation::spec(method_index)
3699 : static_call_Relocation::spec(method_index);
3700 call = __ trampoline_call(Address(addr, rspec));
3701 if (call == NULL) {
3702 ciEnv::current()->record_failure("CodeCache is full");
3703 return;
3704 }
3705 if (CodeBuffer::supports_shared_stubs() && _method->can_be_statically_bound()) {
3706 // Calls of the same statically bound method can share
3707 // a stub to the interpreter.
3708 cbuf.shared_stub_to_interp_for(_method, call - cbuf.insts_begin());
3709 } else {
3710 // Emit stub for static call
3711 address stub = CompiledStaticCall::emit_to_interp_stub(cbuf, call);
3712 if (stub == NULL) {
3713 ciEnv::current()->record_failure("CodeCache is full");
3714 return;
3715 }
3716 }
3717 }
3718
3719 __ post_call_nop();
3720
3721 // Only non uncommon_trap calls need to reinitialize ptrue.
3722 if (Compile::current()->max_vector_size() > 0 && uncommon_trap_request() == 0) {
3723 __ reinitialize_ptrue();
3724 }
3725 %}
3726
3727 enc_class aarch64_enc_java_dynamic_call(method meth) %{
3728 C2_MacroAssembler _masm(&cbuf);
3729 int method_index = resolved_method_index(cbuf);
3730 address call = __ ic_call((address)$meth$$method, method_index);
3731 if (call == NULL) {
3732 ciEnv::current()->record_failure("CodeCache is full");
3733 return;
3734 }
3735 __ post_call_nop();
3736 if (Compile::current()->max_vector_size() > 0) {
3737 __ reinitialize_ptrue();
3738 }
3739 %}
3740
3741 enc_class aarch64_enc_call_epilog() %{
3742 C2_MacroAssembler _masm(&cbuf);
3743 if (VerifyStackAtCalls) {
3744 // Check that stack depth is unchanged: find majik cookie on stack
3745 __ call_Unimplemented();
3746 }
3747 %}
3748
3749 enc_class aarch64_enc_java_to_runtime(method meth) %{
3750 C2_MacroAssembler _masm(&cbuf);
3751
3752 // some calls to generated routines (arraycopy code) are scheduled
3753 // by C2 as runtime calls. if so we can call them using a br (they
3754 // will be in a reachable segment) otherwise we have to use a blr
3755 // which loads the absolute address into a register.
3756 address entry = (address)$meth$$method;
3757 CodeBlob *cb = CodeCache::find_blob(entry);
3758 if (cb) {
3759 address call = __ trampoline_call(Address(entry, relocInfo::runtime_call_type));
3760 if (call == NULL) {
3761 ciEnv::current()->record_failure("CodeCache is full");
3762 return;
3763 }
3764 __ post_call_nop();
3765 } else {
3766 Label retaddr;
3767 __ adr(rscratch2, retaddr);
3768 __ lea(rscratch1, RuntimeAddress(entry));
3769 // Leave a breadcrumb for JavaFrameAnchor::capture_last_Java_pc()
3770 __ stp(zr, rscratch2, Address(__ pre(sp, -2 * wordSize)));
3771 __ blr(rscratch1);
3772 __ bind(retaddr);
3773 __ post_call_nop();
3774 __ add(sp, sp, 2 * wordSize);
3775 }
3776 if (Compile::current()->max_vector_size() > 0) {
3777 __ reinitialize_ptrue();
3778 }
3779 %}
3780
3781 enc_class aarch64_enc_rethrow() %{
3782 C2_MacroAssembler _masm(&cbuf);
3783 __ far_jump(RuntimeAddress(OptoRuntime::rethrow_stub()));
3784 %}
3785
3786 enc_class aarch64_enc_ret() %{
3787 C2_MacroAssembler _masm(&cbuf);
3788 #ifdef ASSERT
3789 if (Compile::current()->max_vector_size() > 0) {
3790 __ verify_ptrue();
3791 }
3792 #endif
3793 __ ret(lr);
3794 %}
3795
3796 enc_class aarch64_enc_tail_call(iRegP jump_target) %{
3797 C2_MacroAssembler _masm(&cbuf);
3798 Register target_reg = as_Register($jump_target$$reg);
3799 __ br(target_reg);
3800 %}
3801
3802 enc_class aarch64_enc_tail_jmp(iRegP jump_target) %{
3803 C2_MacroAssembler _masm(&cbuf);
3804 Register target_reg = as_Register($jump_target$$reg);
3805 // exception oop should be in r0
3806 // ret addr has been popped into lr
3807 // callee expects it in r3
3808 __ mov(r3, lr);
3809 __ br(target_reg);
3810 %}
3811
3812 %}
3813
3814 //----------FRAME--------------------------------------------------------------
3815 // Definition of frame structure and management information.
3816 //
3817 // S T A C K L A Y O U T Allocators stack-slot number
3818 // | (to get allocators register number
3819 // G Owned by | | v add OptoReg::stack0())
3820 // r CALLER | |
3821 // o | +--------+ pad to even-align allocators stack-slot
3822 // w V | pad0 | numbers; owned by CALLER
3823 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
3824 // h ^ | in | 5
3825 // | | args | 4 Holes in incoming args owned by SELF
3826 // | | | | 3
3827 // | | +--------+
3828 // V | | old out| Empty on Intel, window on Sparc
3829 // | old |preserve| Must be even aligned.
3830 // | SP-+--------+----> Matcher::_old_SP, even aligned
3831 // | | in | 3 area for Intel ret address
3832 // Owned by |preserve| Empty on Sparc.
3833 // SELF +--------+
3834 // | | pad2 | 2 pad to align old SP
3835 // | +--------+ 1
3836 // | | locks | 0
3837 // | +--------+----> OptoReg::stack0(), even aligned
3838 // | | pad1 | 11 pad to align new SP
3839 // | +--------+
3840 // | | | 10
3841 // | | spills | 9 spills
3842 // V | | 8 (pad0 slot for callee)
3843 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
3844 // ^ | out | 7
3845 // | | args | 6 Holes in outgoing args owned by CALLEE
3846 // Owned by +--------+
3847 // CALLEE | new out| 6 Empty on Intel, window on Sparc
3848 // | new |preserve| Must be even-aligned.
3849 // | SP-+--------+----> Matcher::_new_SP, even aligned
3850 // | | |
3851 //
3852 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
3853 // known from SELF's arguments and the Java calling convention.
3854 // Region 6-7 is determined per call site.
3855 // Note 2: If the calling convention leaves holes in the incoming argument
3856 // area, those holes are owned by SELF. Holes in the outgoing area
3857 // are owned by the CALLEE. Holes should not be necessary in the
3858 // incoming area, as the Java calling convention is completely under
3859 // the control of the AD file. Doubles can be sorted and packed to
3860 // avoid holes. Holes in the outgoing arguments may be necessary for
3861 // varargs C calling conventions.
3862 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
3863 // even aligned with pad0 as needed.
3864 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
3865 // (the latter is true on Intel but is it false on AArch64?)
3866 // region 6-11 is even aligned; it may be padded out more so that
3867 // the region from SP to FP meets the minimum stack alignment.
3868 // Note 4: For I2C adapters, the incoming FP may not meet the minimum stack
3869 // alignment. Region 11, pad1, may be dynamically extended so that
3870 // SP meets the minimum alignment.
3871
3872 frame %{
3873 // These three registers define part of the calling convention
3874 // between compiled code and the interpreter.
3875
3876 // Inline Cache Register or Method for I2C.
3877 inline_cache_reg(R12);
3878
3879 // Number of stack slots consumed by locking an object
3880 sync_stack_slots(2);
3881
3882 // Compiled code's Frame Pointer
3883 frame_pointer(R31);
3884
3885 // Interpreter stores its frame pointer in a register which is
3886 // stored to the stack by I2CAdaptors.
3887 // I2CAdaptors convert from interpreted java to compiled java.
3888 interpreter_frame_pointer(R29);
3889
3890 // Stack alignment requirement
3891 stack_alignment(StackAlignmentInBytes); // Alignment size in bytes (128-bit -> 16 bytes)
3892
3893 // Number of outgoing stack slots killed above the out_preserve_stack_slots
3894 // for calls to C. Supports the var-args backing area for register parms.
3895 varargs_C_out_slots_killed(frame::arg_reg_save_area_bytes/BytesPerInt);
3896
3897 // The after-PROLOG location of the return address. Location of
3898 // return address specifies a type (REG or STACK) and a number
3899 // representing the register number (i.e. - use a register name) or
3900 // stack slot.
3901 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
3902 // Otherwise, it is above the locks and verification slot and alignment word
3903 // TODO this may well be correct but need to check why that - 2 is there
3904 // ppc port uses 0 but we definitely need to allow for fixed_slots
3905 // which folds in the space used for monitors
3906 return_addr(STACK - 2 +
3907 align_up((Compile::current()->in_preserve_stack_slots() +
3908 Compile::current()->fixed_slots()),
3909 stack_alignment_in_slots()));
3910
3911 // Location of compiled Java return values. Same as C for now.
3912 return_value
3913 %{
3914 // TODO do we allow ideal_reg == Op_RegN???
3915 assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL,
3916 "only return normal values");
3917
3918 static const int lo[Op_RegL + 1] = { // enum name
3919 0, // Op_Node
3920 0, // Op_Set
3921 R0_num, // Op_RegN
3922 R0_num, // Op_RegI
3923 R0_num, // Op_RegP
3924 V0_num, // Op_RegF
3925 V0_num, // Op_RegD
3926 R0_num // Op_RegL
3927 };
3928
3929 static const int hi[Op_RegL + 1] = { // enum name
3930 0, // Op_Node
3931 0, // Op_Set
3932 OptoReg::Bad, // Op_RegN
3933 OptoReg::Bad, // Op_RegI
3934 R0_H_num, // Op_RegP
3935 OptoReg::Bad, // Op_RegF
3936 V0_H_num, // Op_RegD
3937 R0_H_num // Op_RegL
3938 };
3939
3940 return OptoRegPair(hi[ideal_reg], lo[ideal_reg]);
3941 %}
3942 %}
3943
3944 //----------ATTRIBUTES---------------------------------------------------------
3945 //----------Operand Attributes-------------------------------------------------
3946 op_attrib op_cost(1); // Required cost attribute
3947
3948 //----------Instruction Attributes---------------------------------------------
3949 ins_attrib ins_cost(INSN_COST); // Required cost attribute
3950 ins_attrib ins_size(32); // Required size attribute (in bits)
3951 ins_attrib ins_short_branch(0); // Required flag: is this instruction
3952 // a non-matching short branch variant
3953 // of some long branch?
3954 ins_attrib ins_alignment(4); // Required alignment attribute (must
3955 // be a power of 2) specifies the
3956 // alignment that some part of the
3957 // instruction (not necessarily the
3958 // start) requires. If > 1, a
3959 // compute_padding() function must be
3960 // provided for the instruction
3961
3962 //----------OPERANDS-----------------------------------------------------------
3963 // Operand definitions must precede instruction definitions for correct parsing
3964 // in the ADLC because operands constitute user defined types which are used in
3965 // instruction definitions.
3966
3967 //----------Simple Operands----------------------------------------------------
3968
3969 // Integer operands 32 bit
3970 // 32 bit immediate
3971 operand immI()
3972 %{
3973 match(ConI);
3974
3975 op_cost(0);
3976 format %{ %}
3977 interface(CONST_INTER);
3978 %}
3979
3980 // 32 bit zero
3981 operand immI0()
3982 %{
3983 predicate(n->get_int() == 0);
3984 match(ConI);
3985
3986 op_cost(0);
3987 format %{ %}
3988 interface(CONST_INTER);
3989 %}
3990
3991 // 32 bit unit increment
3992 operand immI_1()
3993 %{
3994 predicate(n->get_int() == 1);
3995 match(ConI);
3996
3997 op_cost(0);
3998 format %{ %}
3999 interface(CONST_INTER);
4000 %}
4001
4002 // 32 bit unit decrement
4003 operand immI_M1()
4004 %{
4005 predicate(n->get_int() == -1);
4006 match(ConI);
4007
4008 op_cost(0);
4009 format %{ %}
4010 interface(CONST_INTER);
4011 %}
4012
4013 // Shift values for add/sub extension shift
4014 operand immIExt()
4015 %{
4016 predicate(0 <= n->get_int() && (n->get_int() <= 4));
4017 match(ConI);
4018
4019 op_cost(0);
4020 format %{ %}
4021 interface(CONST_INTER);
4022 %}
4023
4024 operand immI_gt_1()
4025 %{
4026 predicate(n->get_int() > 1);
4027 match(ConI);
4028
4029 op_cost(0);
4030 format %{ %}
4031 interface(CONST_INTER);
4032 %}
4033
4034 operand immI_le_4()
4035 %{
4036 predicate(n->get_int() <= 4);
4037 match(ConI);
4038
4039 op_cost(0);
4040 format %{ %}
4041 interface(CONST_INTER);
4042 %}
4043
4044 operand immI_16()
4045 %{
4046 predicate(n->get_int() == 16);
4047 match(ConI);
4048
4049 op_cost(0);
4050 format %{ %}
4051 interface(CONST_INTER);
4052 %}
4053
4054 operand immI_24()
4055 %{
4056 predicate(n->get_int() == 24);
4057 match(ConI);
4058
4059 op_cost(0);
4060 format %{ %}
4061 interface(CONST_INTER);
4062 %}
4063
4064 operand immI_32()
4065 %{
4066 predicate(n->get_int() == 32);
4067 match(ConI);
4068
4069 op_cost(0);
4070 format %{ %}
4071 interface(CONST_INTER);
4072 %}
4073
4074 operand immI_48()
4075 %{
4076 predicate(n->get_int() == 48);
4077 match(ConI);
4078
4079 op_cost(0);
4080 format %{ %}
4081 interface(CONST_INTER);
4082 %}
4083
4084 operand immI_56()
4085 %{
4086 predicate(n->get_int() == 56);
4087 match(ConI);
4088
4089 op_cost(0);
4090 format %{ %}
4091 interface(CONST_INTER);
4092 %}
4093
4094 operand immI_63()
4095 %{
4096 predicate(n->get_int() == 63);
4097 match(ConI);
4098
4099 op_cost(0);
4100 format %{ %}
4101 interface(CONST_INTER);
4102 %}
4103
4104 operand immI_64()
4105 %{
4106 predicate(n->get_int() == 64);
4107 match(ConI);
4108
4109 op_cost(0);
4110 format %{ %}
4111 interface(CONST_INTER);
4112 %}
4113
4114 operand immI_255()
4115 %{
4116 predicate(n->get_int() == 255);
4117 match(ConI);
4118
4119 op_cost(0);
4120 format %{ %}
4121 interface(CONST_INTER);
4122 %}
4123
4124 operand immI_65535()
4125 %{
4126 predicate(n->get_int() == 65535);
4127 match(ConI);
4128
4129 op_cost(0);
4130 format %{ %}
4131 interface(CONST_INTER);
4132 %}
4133
4134 operand immI_positive()
4135 %{
4136 predicate(n->get_int() > 0);
4137 match(ConI);
4138
4139 op_cost(0);
4140 format %{ %}
4141 interface(CONST_INTER);
4142 %}
4143
4144 // BoolTest condition for signed compare
4145 operand immI_cmp_cond()
4146 %{
4147 predicate(!Matcher::is_unsigned_booltest_pred(n->get_int()));
4148 match(ConI);
4149
4150 op_cost(0);
4151 format %{ %}
4152 interface(CONST_INTER);
4153 %}
4154
4155 // BoolTest condition for unsigned compare
4156 operand immI_cmpU_cond()
4157 %{
4158 predicate(Matcher::is_unsigned_booltest_pred(n->get_int()));
4159 match(ConI);
4160
4161 op_cost(0);
4162 format %{ %}
4163 interface(CONST_INTER);
4164 %}
4165
4166 operand immL_255()
4167 %{
4168 predicate(n->get_long() == 255L);
4169 match(ConL);
4170
4171 op_cost(0);
4172 format %{ %}
4173 interface(CONST_INTER);
4174 %}
4175
4176 operand immL_65535()
4177 %{
4178 predicate(n->get_long() == 65535L);
4179 match(ConL);
4180
4181 op_cost(0);
4182 format %{ %}
4183 interface(CONST_INTER);
4184 %}
4185
4186 operand immL_4294967295()
4187 %{
4188 predicate(n->get_long() == 4294967295L);
4189 match(ConL);
4190
4191 op_cost(0);
4192 format %{ %}
4193 interface(CONST_INTER);
4194 %}
4195
4196 operand immL_bitmask()
4197 %{
4198 predicate((n->get_long() != 0)
4199 && ((n->get_long() & 0xc000000000000000l) == 0)
4200 && is_power_of_2(n->get_long() + 1));
4201 match(ConL);
4202
4203 op_cost(0);
4204 format %{ %}
4205 interface(CONST_INTER);
4206 %}
4207
4208 operand immI_bitmask()
4209 %{
4210 predicate((n->get_int() != 0)
4211 && ((n->get_int() & 0xc0000000) == 0)
4212 && is_power_of_2(n->get_int() + 1));
4213 match(ConI);
4214
4215 op_cost(0);
4216 format %{ %}
4217 interface(CONST_INTER);
4218 %}
4219
4220 operand immL_positive_bitmaskI()
4221 %{
4222 predicate((n->get_long() != 0)
4223 && ((julong)n->get_long() < 0x80000000ULL)
4224 && is_power_of_2(n->get_long() + 1));
4225 match(ConL);
4226
4227 op_cost(0);
4228 format %{ %}
4229 interface(CONST_INTER);
4230 %}
4231
4232 // Scale values for scaled offset addressing modes (up to long but not quad)
4233 operand immIScale()
4234 %{
4235 predicate(0 <= n->get_int() && (n->get_int() <= 3));
4236 match(ConI);
4237
4238 op_cost(0);
4239 format %{ %}
4240 interface(CONST_INTER);
4241 %}
4242
4243 // 26 bit signed offset -- for pc-relative branches
4244 operand immI26()
4245 %{
4246 predicate(((-(1 << 25)) <= n->get_int()) && (n->get_int() < (1 << 25)));
4247 match(ConI);
4248
4249 op_cost(0);
4250 format %{ %}
4251 interface(CONST_INTER);
4252 %}
4253
4254 // 19 bit signed offset -- for pc-relative loads
4255 operand immI19()
4256 %{
4257 predicate(((-(1 << 18)) <= n->get_int()) && (n->get_int() < (1 << 18)));
4258 match(ConI);
4259
4260 op_cost(0);
4261 format %{ %}
4262 interface(CONST_INTER);
4263 %}
4264
4265 // 5 bit signed integer
4266 operand immI5()
4267 %{
4268 predicate(Assembler::is_simm(n->get_int(), 5));
4269 match(ConI);
4270
4271 op_cost(0);
4272 format %{ %}
4273 interface(CONST_INTER);
4274 %}
4275
4276 // 7 bit unsigned integer
4277 operand immIU7()
4278 %{
4279 predicate(Assembler::is_uimm(n->get_int(), 7));
4280 match(ConI);
4281
4282 op_cost(0);
4283 format %{ %}
4284 interface(CONST_INTER);
4285 %}
4286
4287 // 12 bit unsigned offset -- for base plus immediate loads
4288 operand immIU12()
4289 %{
4290 predicate((0 <= n->get_int()) && (n->get_int() < (1 << 12)));
4291 match(ConI);
4292
4293 op_cost(0);
4294 format %{ %}
4295 interface(CONST_INTER);
4296 %}
4297
4298 operand immLU12()
4299 %{
4300 predicate((0 <= n->get_long()) && (n->get_long() < (1 << 12)));
4301 match(ConL);
4302
4303 op_cost(0);
4304 format %{ %}
4305 interface(CONST_INTER);
4306 %}
4307
4308 // Offset for scaled or unscaled immediate loads and stores
4309 operand immIOffset()
4310 %{
4311 predicate(Address::offset_ok_for_immed(n->get_int(), 0));
4312 match(ConI);
4313
4314 op_cost(0);
4315 format %{ %}
4316 interface(CONST_INTER);
4317 %}
4318
4319 operand immIOffset1()
4320 %{
4321 predicate(Address::offset_ok_for_immed(n->get_int(), 0));
4322 match(ConI);
4323
4324 op_cost(0);
4325 format %{ %}
4326 interface(CONST_INTER);
4327 %}
4328
4329 operand immIOffset2()
4330 %{
4331 predicate(Address::offset_ok_for_immed(n->get_int(), 1));
4332 match(ConI);
4333
4334 op_cost(0);
4335 format %{ %}
4336 interface(CONST_INTER);
4337 %}
4338
4339 operand immIOffset4()
4340 %{
4341 predicate(Address::offset_ok_for_immed(n->get_int(), 2));
4342 match(ConI);
4343
4344 op_cost(0);
4345 format %{ %}
4346 interface(CONST_INTER);
4347 %}
4348
4349 operand immIOffset8()
4350 %{
4351 predicate(Address::offset_ok_for_immed(n->get_int(), 3));
4352 match(ConI);
4353
4354 op_cost(0);
4355 format %{ %}
4356 interface(CONST_INTER);
4357 %}
4358
4359 operand immIOffset16()
4360 %{
4361 predicate(Address::offset_ok_for_immed(n->get_int(), 4));
4362 match(ConI);
4363
4364 op_cost(0);
4365 format %{ %}
4366 interface(CONST_INTER);
4367 %}
4368
4369 operand immLoffset()
4370 %{
4371 predicate(Address::offset_ok_for_immed(n->get_long(), 0));
4372 match(ConL);
4373
4374 op_cost(0);
4375 format %{ %}
4376 interface(CONST_INTER);
4377 %}
4378
4379 operand immLoffset1()
4380 %{
4381 predicate(Address::offset_ok_for_immed(n->get_long(), 0));
4382 match(ConL);
4383
4384 op_cost(0);
4385 format %{ %}
4386 interface(CONST_INTER);
4387 %}
4388
4389 operand immLoffset2()
4390 %{
4391 predicate(Address::offset_ok_for_immed(n->get_long(), 1));
4392 match(ConL);
4393
4394 op_cost(0);
4395 format %{ %}
4396 interface(CONST_INTER);
4397 %}
4398
4399 operand immLoffset4()
4400 %{
4401 predicate(Address::offset_ok_for_immed(n->get_long(), 2));
4402 match(ConL);
4403
4404 op_cost(0);
4405 format %{ %}
4406 interface(CONST_INTER);
4407 %}
4408
4409 operand immLoffset8()
4410 %{
4411 predicate(Address::offset_ok_for_immed(n->get_long(), 3));
4412 match(ConL);
4413
4414 op_cost(0);
4415 format %{ %}
4416 interface(CONST_INTER);
4417 %}
4418
4419 operand immLoffset16()
4420 %{
4421 predicate(Address::offset_ok_for_immed(n->get_long(), 4));
4422 match(ConL);
4423
4424 op_cost(0);
4425 format %{ %}
4426 interface(CONST_INTER);
4427 %}
4428
4429 // 5 bit signed long integer
4430 operand immL5()
4431 %{
4432 predicate(Assembler::is_simm(n->get_long(), 5));
4433 match(ConL);
4434
4435 op_cost(0);
4436 format %{ %}
4437 interface(CONST_INTER);
4438 %}
4439
4440 // 7 bit unsigned long integer
4441 operand immLU7()
4442 %{
4443 predicate(Assembler::is_uimm(n->get_long(), 7));
4444 match(ConL);
4445
4446 op_cost(0);
4447 format %{ %}
4448 interface(CONST_INTER);
4449 %}
4450
4451 // 8 bit signed value.
4452 operand immI8()
4453 %{
4454 predicate(n->get_int() <= 127 && n->get_int() >= -128);
4455 match(ConI);
4456
4457 op_cost(0);
4458 format %{ %}
4459 interface(CONST_INTER);
4460 %}
4461
4462 // 8 bit signed value (simm8), or #simm8 LSL 8.
4463 operand immI8_shift8()
4464 %{
4465 predicate((n->get_int() <= 127 && n->get_int() >= -128) ||
4466 (n->get_int() <= 32512 && n->get_int() >= -32768 && (n->get_int() & 0xff) == 0));
4467 match(ConI);
4468
4469 op_cost(0);
4470 format %{ %}
4471 interface(CONST_INTER);
4472 %}
4473
4474 // 8 bit signed value (simm8), or #simm8 LSL 8.
4475 operand immL8_shift8()
4476 %{
4477 predicate((n->get_long() <= 127 && n->get_long() >= -128) ||
4478 (n->get_long() <= 32512 && n->get_long() >= -32768 && (n->get_long() & 0xff) == 0));
4479 match(ConL);
4480
4481 op_cost(0);
4482 format %{ %}
4483 interface(CONST_INTER);
4484 %}
4485
4486 // 8 bit integer valid for vector add sub immediate
4487 operand immBAddSubV()
4488 %{
4489 predicate(n->get_int() <= 255 && n->get_int() >= -255);
4490 match(ConI);
4491
4492 op_cost(0);
4493 format %{ %}
4494 interface(CONST_INTER);
4495 %}
4496
4497 // 32 bit integer valid for add sub immediate
4498 operand immIAddSub()
4499 %{
4500 predicate(Assembler::operand_valid_for_add_sub_immediate((int64_t)n->get_int()));
4501 match(ConI);
4502 op_cost(0);
4503 format %{ %}
4504 interface(CONST_INTER);
4505 %}
4506
4507 // 32 bit integer valid for vector add sub immediate
4508 operand immIAddSubV()
4509 %{
4510 predicate(Assembler::operand_valid_for_sve_add_sub_immediate((int64_t)n->get_int()));
4511 match(ConI);
4512
4513 op_cost(0);
4514 format %{ %}
4515 interface(CONST_INTER);
4516 %}
4517
4518 // 32 bit unsigned integer valid for logical immediate
4519
4520 operand immBLog()
4521 %{
4522 predicate(Assembler::operand_valid_for_sve_logical_immediate(BitsPerByte, (uint64_t)n->get_int()));
4523 match(ConI);
4524
4525 op_cost(0);
4526 format %{ %}
4527 interface(CONST_INTER);
4528 %}
4529
4530 operand immSLog()
4531 %{
4532 predicate(Assembler::operand_valid_for_sve_logical_immediate(BitsPerShort, (uint64_t)n->get_int()));
4533 match(ConI);
4534
4535 op_cost(0);
4536 format %{ %}
4537 interface(CONST_INTER);
4538 %}
4539
4540 operand immILog()
4541 %{
4542 predicate(Assembler::operand_valid_for_logical_immediate(/*is32*/true, (uint64_t)n->get_int()));
4543 match(ConI);
4544
4545 op_cost(0);
4546 format %{ %}
4547 interface(CONST_INTER);
4548 %}
4549
4550 // Integer operands 64 bit
4551 // 64 bit immediate
4552 operand immL()
4553 %{
4554 match(ConL);
4555
4556 op_cost(0);
4557 format %{ %}
4558 interface(CONST_INTER);
4559 %}
4560
4561 // 64 bit zero
4562 operand immL0()
4563 %{
4564 predicate(n->get_long() == 0);
4565 match(ConL);
4566
4567 op_cost(0);
4568 format %{ %}
4569 interface(CONST_INTER);
4570 %}
4571
4572 // 64 bit unit increment
4573 operand immL_1()
4574 %{
4575 predicate(n->get_long() == 1);
4576 match(ConL);
4577
4578 op_cost(0);
4579 format %{ %}
4580 interface(CONST_INTER);
4581 %}
4582
4583 // 64 bit unit decrement
4584 operand immL_M1()
4585 %{
4586 predicate(n->get_long() == -1);
4587 match(ConL);
4588
4589 op_cost(0);
4590 format %{ %}
4591 interface(CONST_INTER);
4592 %}
4593
4594 // 32 bit offset of pc in thread anchor
4595
4596 operand immL_pc_off()
4597 %{
4598 predicate(n->get_long() == in_bytes(JavaThread::frame_anchor_offset()) +
4599 in_bytes(JavaFrameAnchor::last_Java_pc_offset()));
4600 match(ConL);
4601
4602 op_cost(0);
4603 format %{ %}
4604 interface(CONST_INTER);
4605 %}
4606
4607 // 64 bit integer valid for add sub immediate
4608 operand immLAddSub()
4609 %{
4610 predicate(Assembler::operand_valid_for_add_sub_immediate(n->get_long()));
4611 match(ConL);
4612 op_cost(0);
4613 format %{ %}
4614 interface(CONST_INTER);
4615 %}
4616
4617 // 64 bit integer valid for addv subv immediate
4618 operand immLAddSubV()
4619 %{
4620 predicate(Assembler::operand_valid_for_sve_add_sub_immediate(n->get_long()));
4621 match(ConL);
4622
4623 op_cost(0);
4624 format %{ %}
4625 interface(CONST_INTER);
4626 %}
4627
4628 // 64 bit integer valid for logical immediate
4629 operand immLLog()
4630 %{
4631 predicate(Assembler::operand_valid_for_logical_immediate(/*is32*/false, (uint64_t)n->get_long()));
4632 match(ConL);
4633 op_cost(0);
4634 format %{ %}
4635 interface(CONST_INTER);
4636 %}
4637
4638 // Long Immediate: low 32-bit mask
4639 operand immL_32bits()
4640 %{
4641 predicate(n->get_long() == 0xFFFFFFFFL);
4642 match(ConL);
4643 op_cost(0);
4644 format %{ %}
4645 interface(CONST_INTER);
4646 %}
4647
4648 // Pointer operands
4649 // Pointer Immediate
4650 operand immP()
4651 %{
4652 match(ConP);
4653
4654 op_cost(0);
4655 format %{ %}
4656 interface(CONST_INTER);
4657 %}
4658
4659 // NULL Pointer Immediate
4660 operand immP0()
4661 %{
4662 predicate(n->get_ptr() == 0);
4663 match(ConP);
4664
4665 op_cost(0);
4666 format %{ %}
4667 interface(CONST_INTER);
4668 %}
4669
4670 // Pointer Immediate One
4671 // this is used in object initialization (initial object header)
4672 operand immP_1()
4673 %{
4674 predicate(n->get_ptr() == 1);
4675 match(ConP);
4676
4677 op_cost(0);
4678 format %{ %}
4679 interface(CONST_INTER);
4680 %}
4681
4682 // Card Table Byte Map Base
4683 operand immByteMapBase()
4684 %{
4685 // Get base of card map
4686 predicate(BarrierSet::barrier_set()->is_a(BarrierSet::CardTableBarrierSet) &&
4687 (CardTable::CardValue*)n->get_ptr() == ((CardTableBarrierSet*)(BarrierSet::barrier_set()))->card_table()->byte_map_base());
4688 match(ConP);
4689
4690 op_cost(0);
4691 format %{ %}
4692 interface(CONST_INTER);
4693 %}
4694
4695 // Pointer Immediate Minus One
4696 // this is used when we want to write the current PC to the thread anchor
4697 operand immP_M1()
4698 %{
4699 predicate(n->get_ptr() == -1);
4700 match(ConP);
4701
4702 op_cost(0);
4703 format %{ %}
4704 interface(CONST_INTER);
4705 %}
4706
4707 // Pointer Immediate Minus Two
4708 // this is used when we want to write the current PC to the thread anchor
4709 operand immP_M2()
4710 %{
4711 predicate(n->get_ptr() == -2);
4712 match(ConP);
4713
4714 op_cost(0);
4715 format %{ %}
4716 interface(CONST_INTER);
4717 %}
4718
4719 // Float and Double operands
4720 // Double Immediate
4721 operand immD()
4722 %{
4723 match(ConD);
4724 op_cost(0);
4725 format %{ %}
4726 interface(CONST_INTER);
4727 %}
4728
4729 // Double Immediate: +0.0d
4730 operand immD0()
4731 %{
4732 predicate(jlong_cast(n->getd()) == 0);
4733 match(ConD);
4734
4735 op_cost(0);
4736 format %{ %}
4737 interface(CONST_INTER);
4738 %}
4739
4740 // constant 'double +0.0'.
4741 operand immDPacked()
4742 %{
4743 predicate(Assembler::operand_valid_for_float_immediate(n->getd()));
4744 match(ConD);
4745 op_cost(0);
4746 format %{ %}
4747 interface(CONST_INTER);
4748 %}
4749
4750 // Float Immediate
4751 operand immF()
4752 %{
4753 match(ConF);
4754 op_cost(0);
4755 format %{ %}
4756 interface(CONST_INTER);
4757 %}
4758
4759 // Float Immediate: +0.0f.
4760 operand immF0()
4761 %{
4762 predicate(jint_cast(n->getf()) == 0);
4763 match(ConF);
4764
4765 op_cost(0);
4766 format %{ %}
4767 interface(CONST_INTER);
4768 %}
4769
4770 //
4771 operand immFPacked()
4772 %{
4773 predicate(Assembler::operand_valid_for_float_immediate((double)n->getf()));
4774 match(ConF);
4775 op_cost(0);
4776 format %{ %}
4777 interface(CONST_INTER);
4778 %}
4779
4780 // Narrow pointer operands
4781 // Narrow Pointer Immediate
4782 operand immN()
4783 %{
4784 match(ConN);
4785
4786 op_cost(0);
4787 format %{ %}
4788 interface(CONST_INTER);
4789 %}
4790
4791 // Narrow NULL Pointer Immediate
4792 operand immN0()
4793 %{
4794 predicate(n->get_narrowcon() == 0);
4795 match(ConN);
4796
4797 op_cost(0);
4798 format %{ %}
4799 interface(CONST_INTER);
4800 %}
4801
4802 operand immNKlass()
4803 %{
4804 match(ConNKlass);
4805
4806 op_cost(0);
4807 format %{ %}
4808 interface(CONST_INTER);
4809 %}
4810
4811 // Integer 32 bit Register Operands
4812 // Integer 32 bitRegister (excludes SP)
4813 operand iRegI()
4814 %{
4815 constraint(ALLOC_IN_RC(any_reg32));
4816 match(RegI);
4817 match(iRegINoSp);
4818 op_cost(0);
4819 format %{ %}
4820 interface(REG_INTER);
4821 %}
4822
4823 // Integer 32 bit Register not Special
4824 operand iRegINoSp()
4825 %{
4826 constraint(ALLOC_IN_RC(no_special_reg32));
4827 match(RegI);
4828 op_cost(0);
4829 format %{ %}
4830 interface(REG_INTER);
4831 %}
4832
4833 // Integer 64 bit Register Operands
4834 // Integer 64 bit Register (includes SP)
4835 operand iRegL()
4836 %{
4837 constraint(ALLOC_IN_RC(any_reg));
4838 match(RegL);
4839 match(iRegLNoSp);
4840 op_cost(0);
4841 format %{ %}
4842 interface(REG_INTER);
4843 %}
4844
4845 // Integer 64 bit Register not Special
4846 operand iRegLNoSp()
4847 %{
4848 constraint(ALLOC_IN_RC(no_special_reg));
4849 match(RegL);
4850 match(iRegL_R0);
4851 format %{ %}
4852 interface(REG_INTER);
4853 %}
4854
4855 // Pointer Register Operands
4856 // Pointer Register
4857 operand iRegP()
4858 %{
4859 constraint(ALLOC_IN_RC(ptr_reg));
4860 match(RegP);
4861 match(iRegPNoSp);
4862 match(iRegP_R0);
4863 //match(iRegP_R2);
4864 //match(iRegP_R4);
4865 match(iRegP_R5);
4866 match(thread_RegP);
4867 op_cost(0);
4868 format %{ %}
4869 interface(REG_INTER);
4870 %}
4871
4872 // Pointer 64 bit Register not Special
4873 operand iRegPNoSp()
4874 %{
4875 constraint(ALLOC_IN_RC(no_special_ptr_reg));
4876 match(RegP);
4877 // match(iRegP);
4878 // match(iRegP_R0);
4879 // match(iRegP_R2);
4880 // match(iRegP_R4);
4881 // match(iRegP_R5);
4882 // match(thread_RegP);
4883 op_cost(0);
4884 format %{ %}
4885 interface(REG_INTER);
4886 %}
4887
4888 // Pointer 64 bit Register R0 only
4889 operand iRegP_R0()
4890 %{
4891 constraint(ALLOC_IN_RC(r0_reg));
4892 match(RegP);
4893 // match(iRegP);
4894 match(iRegPNoSp);
4895 op_cost(0);
4896 format %{ %}
4897 interface(REG_INTER);
4898 %}
4899
4900 // Pointer 64 bit Register R1 only
4901 operand iRegP_R1()
4902 %{
4903 constraint(ALLOC_IN_RC(r1_reg));
4904 match(RegP);
4905 // match(iRegP);
4906 match(iRegPNoSp);
4907 op_cost(0);
4908 format %{ %}
4909 interface(REG_INTER);
4910 %}
4911
4912 // Pointer 64 bit Register R2 only
4913 operand iRegP_R2()
4914 %{
4915 constraint(ALLOC_IN_RC(r2_reg));
4916 match(RegP);
4917 // match(iRegP);
4918 match(iRegPNoSp);
4919 op_cost(0);
4920 format %{ %}
4921 interface(REG_INTER);
4922 %}
4923
4924 // Pointer 64 bit Register R3 only
4925 operand iRegP_R3()
4926 %{
4927 constraint(ALLOC_IN_RC(r3_reg));
4928 match(RegP);
4929 // match(iRegP);
4930 match(iRegPNoSp);
4931 op_cost(0);
4932 format %{ %}
4933 interface(REG_INTER);
4934 %}
4935
4936 // Pointer 64 bit Register R4 only
4937 operand iRegP_R4()
4938 %{
4939 constraint(ALLOC_IN_RC(r4_reg));
4940 match(RegP);
4941 // match(iRegP);
4942 match(iRegPNoSp);
4943 op_cost(0);
4944 format %{ %}
4945 interface(REG_INTER);
4946 %}
4947
4948 // Pointer 64 bit Register R5 only
4949 operand iRegP_R5()
4950 %{
4951 constraint(ALLOC_IN_RC(r5_reg));
4952 match(RegP);
4953 // match(iRegP);
4954 match(iRegPNoSp);
4955 op_cost(0);
4956 format %{ %}
4957 interface(REG_INTER);
4958 %}
4959
4960 // Pointer 64 bit Register R10 only
4961 operand iRegP_R10()
4962 %{
4963 constraint(ALLOC_IN_RC(r10_reg));
4964 match(RegP);
4965 // match(iRegP);
4966 match(iRegPNoSp);
4967 op_cost(0);
4968 format %{ %}
4969 interface(REG_INTER);
4970 %}
4971
4972 // Long 64 bit Register R0 only
4973 operand iRegL_R0()
4974 %{
4975 constraint(ALLOC_IN_RC(r0_reg));
4976 match(RegL);
4977 match(iRegLNoSp);
4978 op_cost(0);
4979 format %{ %}
4980 interface(REG_INTER);
4981 %}
4982
4983 // Long 64 bit Register R2 only
4984 operand iRegL_R2()
4985 %{
4986 constraint(ALLOC_IN_RC(r2_reg));
4987 match(RegL);
4988 match(iRegLNoSp);
4989 op_cost(0);
4990 format %{ %}
4991 interface(REG_INTER);
4992 %}
4993
4994 // Long 64 bit Register R3 only
4995 operand iRegL_R3()
4996 %{
4997 constraint(ALLOC_IN_RC(r3_reg));
4998 match(RegL);
4999 match(iRegLNoSp);
5000 op_cost(0);
5001 format %{ %}
5002 interface(REG_INTER);
5003 %}
5004
5005 // Long 64 bit Register R11 only
5006 operand iRegL_R11()
5007 %{
5008 constraint(ALLOC_IN_RC(r11_reg));
5009 match(RegL);
5010 match(iRegLNoSp);
5011 op_cost(0);
5012 format %{ %}
5013 interface(REG_INTER);
5014 %}
5015
5016 // Pointer 64 bit Register FP only
5017 operand iRegP_FP()
5018 %{
5019 constraint(ALLOC_IN_RC(fp_reg));
5020 match(RegP);
5021 // match(iRegP);
5022 op_cost(0);
5023 format %{ %}
5024 interface(REG_INTER);
5025 %}
5026
5027 // Register R0 only
5028 operand iRegI_R0()
5029 %{
5030 constraint(ALLOC_IN_RC(int_r0_reg));
5031 match(RegI);
5032 match(iRegINoSp);
5033 op_cost(0);
5034 format %{ %}
5035 interface(REG_INTER);
5036 %}
5037
5038 // Register R2 only
5039 operand iRegI_R2()
5040 %{
5041 constraint(ALLOC_IN_RC(int_r2_reg));
5042 match(RegI);
5043 match(iRegINoSp);
5044 op_cost(0);
5045 format %{ %}
5046 interface(REG_INTER);
5047 %}
5048
5049 // Register R3 only
5050 operand iRegI_R3()
5051 %{
5052 constraint(ALLOC_IN_RC(int_r3_reg));
5053 match(RegI);
5054 match(iRegINoSp);
5055 op_cost(0);
5056 format %{ %}
5057 interface(REG_INTER);
5058 %}
5059
5060
5061 // Register R4 only
5062 operand iRegI_R4()
5063 %{
5064 constraint(ALLOC_IN_RC(int_r4_reg));
5065 match(RegI);
5066 match(iRegINoSp);
5067 op_cost(0);
5068 format %{ %}
5069 interface(REG_INTER);
5070 %}
5071
5072
5073 // Pointer Register Operands
5074 // Narrow Pointer Register
5075 operand iRegN()
5076 %{
5077 constraint(ALLOC_IN_RC(any_reg32));
5078 match(RegN);
5079 match(iRegNNoSp);
5080 op_cost(0);
5081 format %{ %}
5082 interface(REG_INTER);
5083 %}
5084
5085 operand iRegN_R0()
5086 %{
5087 constraint(ALLOC_IN_RC(r0_reg));
5088 match(iRegN);
5089 op_cost(0);
5090 format %{ %}
5091 interface(REG_INTER);
5092 %}
5093
5094 operand iRegN_R2()
5095 %{
5096 constraint(ALLOC_IN_RC(r2_reg));
5097 match(iRegN);
5098 op_cost(0);
5099 format %{ %}
5100 interface(REG_INTER);
5101 %}
5102
5103 operand iRegN_R3()
5104 %{
5105 constraint(ALLOC_IN_RC(r3_reg));
5106 match(iRegN);
5107 op_cost(0);
5108 format %{ %}
5109 interface(REG_INTER);
5110 %}
5111
5112 // Integer 64 bit Register not Special
5113 operand iRegNNoSp()
5114 %{
5115 constraint(ALLOC_IN_RC(no_special_reg32));
5116 match(RegN);
5117 op_cost(0);
5118 format %{ %}
5119 interface(REG_INTER);
5120 %}
5121
5122 // Float Register
5123 // Float register operands
5124 operand vRegF()
5125 %{
5126 constraint(ALLOC_IN_RC(float_reg));
5127 match(RegF);
5128
5129 op_cost(0);
5130 format %{ %}
5131 interface(REG_INTER);
5132 %}
5133
5134 // Double Register
5135 // Double register operands
5136 operand vRegD()
5137 %{
5138 constraint(ALLOC_IN_RC(double_reg));
5139 match(RegD);
5140
5141 op_cost(0);
5142 format %{ %}
5143 interface(REG_INTER);
5144 %}
5145
5146 // Generic vector class. This will be used for
5147 // all vector operands, including NEON and SVE.
5148 operand vReg()
5149 %{
5150 constraint(ALLOC_IN_RC(dynamic));
5151 match(VecA);
5152 match(VecD);
5153 match(VecX);
5154
5155 op_cost(0);
5156 format %{ %}
5157 interface(REG_INTER);
5158 %}
5159
5160 operand vecA()
5161 %{
5162 constraint(ALLOC_IN_RC(vectora_reg));
5163 match(VecA);
5164
5165 op_cost(0);
5166 format %{ %}
5167 interface(REG_INTER);
5168 %}
5169
5170 operand vecD()
5171 %{
5172 constraint(ALLOC_IN_RC(vectord_reg));
5173 match(VecD);
5174
5175 op_cost(0);
5176 format %{ %}
5177 interface(REG_INTER);
5178 %}
5179
5180 operand vecX()
5181 %{
5182 constraint(ALLOC_IN_RC(vectorx_reg));
5183 match(VecX);
5184
5185 op_cost(0);
5186 format %{ %}
5187 interface(REG_INTER);
5188 %}
5189
5190 operand vRegD_V0()
5191 %{
5192 constraint(ALLOC_IN_RC(v0_reg));
5193 match(RegD);
5194 op_cost(0);
5195 format %{ %}
5196 interface(REG_INTER);
5197 %}
5198
5199 operand vRegD_V1()
5200 %{
5201 constraint(ALLOC_IN_RC(v1_reg));
5202 match(RegD);
5203 op_cost(0);
5204 format %{ %}
5205 interface(REG_INTER);
5206 %}
5207
5208 operand vRegD_V2()
5209 %{
5210 constraint(ALLOC_IN_RC(v2_reg));
5211 match(RegD);
5212 op_cost(0);
5213 format %{ %}
5214 interface(REG_INTER);
5215 %}
5216
5217 operand vRegD_V3()
5218 %{
5219 constraint(ALLOC_IN_RC(v3_reg));
5220 match(RegD);
5221 op_cost(0);
5222 format %{ %}
5223 interface(REG_INTER);
5224 %}
5225
5226 operand vRegD_V4()
5227 %{
5228 constraint(ALLOC_IN_RC(v4_reg));
5229 match(RegD);
5230 op_cost(0);
5231 format %{ %}
5232 interface(REG_INTER);
5233 %}
5234
5235 operand vRegD_V5()
5236 %{
5237 constraint(ALLOC_IN_RC(v5_reg));
5238 match(RegD);
5239 op_cost(0);
5240 format %{ %}
5241 interface(REG_INTER);
5242 %}
5243
5244 operand vRegD_V6()
5245 %{
5246 constraint(ALLOC_IN_RC(v6_reg));
5247 match(RegD);
5248 op_cost(0);
5249 format %{ %}
5250 interface(REG_INTER);
5251 %}
5252
5253 operand vRegD_V7()
5254 %{
5255 constraint(ALLOC_IN_RC(v7_reg));
5256 match(RegD);
5257 op_cost(0);
5258 format %{ %}
5259 interface(REG_INTER);
5260 %}
5261
5262 operand vRegD_V8()
5263 %{
5264 constraint(ALLOC_IN_RC(v8_reg));
5265 match(RegD);
5266 op_cost(0);
5267 format %{ %}
5268 interface(REG_INTER);
5269 %}
5270
5271 operand vRegD_V9()
5272 %{
5273 constraint(ALLOC_IN_RC(v9_reg));
5274 match(RegD);
5275 op_cost(0);
5276 format %{ %}
5277 interface(REG_INTER);
5278 %}
5279
5280 operand vRegD_V10()
5281 %{
5282 constraint(ALLOC_IN_RC(v10_reg));
5283 match(RegD);
5284 op_cost(0);
5285 format %{ %}
5286 interface(REG_INTER);
5287 %}
5288
5289 operand vRegD_V11()
5290 %{
5291 constraint(ALLOC_IN_RC(v11_reg));
5292 match(RegD);
5293 op_cost(0);
5294 format %{ %}
5295 interface(REG_INTER);
5296 %}
5297
5298 operand vRegD_V12()
5299 %{
5300 constraint(ALLOC_IN_RC(v12_reg));
5301 match(RegD);
5302 op_cost(0);
5303 format %{ %}
5304 interface(REG_INTER);
5305 %}
5306
5307 operand vRegD_V13()
5308 %{
5309 constraint(ALLOC_IN_RC(v13_reg));
5310 match(RegD);
5311 op_cost(0);
5312 format %{ %}
5313 interface(REG_INTER);
5314 %}
5315
5316 operand vRegD_V14()
5317 %{
5318 constraint(ALLOC_IN_RC(v14_reg));
5319 match(RegD);
5320 op_cost(0);
5321 format %{ %}
5322 interface(REG_INTER);
5323 %}
5324
5325 operand vRegD_V15()
5326 %{
5327 constraint(ALLOC_IN_RC(v15_reg));
5328 match(RegD);
5329 op_cost(0);
5330 format %{ %}
5331 interface(REG_INTER);
5332 %}
5333
5334 operand vRegD_V16()
5335 %{
5336 constraint(ALLOC_IN_RC(v16_reg));
5337 match(RegD);
5338 op_cost(0);
5339 format %{ %}
5340 interface(REG_INTER);
5341 %}
5342
5343 operand vRegD_V17()
5344 %{
5345 constraint(ALLOC_IN_RC(v17_reg));
5346 match(RegD);
5347 op_cost(0);
5348 format %{ %}
5349 interface(REG_INTER);
5350 %}
5351
5352 operand vRegD_V18()
5353 %{
5354 constraint(ALLOC_IN_RC(v18_reg));
5355 match(RegD);
5356 op_cost(0);
5357 format %{ %}
5358 interface(REG_INTER);
5359 %}
5360
5361 operand vRegD_V19()
5362 %{
5363 constraint(ALLOC_IN_RC(v19_reg));
5364 match(RegD);
5365 op_cost(0);
5366 format %{ %}
5367 interface(REG_INTER);
5368 %}
5369
5370 operand vRegD_V20()
5371 %{
5372 constraint(ALLOC_IN_RC(v20_reg));
5373 match(RegD);
5374 op_cost(0);
5375 format %{ %}
5376 interface(REG_INTER);
5377 %}
5378
5379 operand vRegD_V21()
5380 %{
5381 constraint(ALLOC_IN_RC(v21_reg));
5382 match(RegD);
5383 op_cost(0);
5384 format %{ %}
5385 interface(REG_INTER);
5386 %}
5387
5388 operand vRegD_V22()
5389 %{
5390 constraint(ALLOC_IN_RC(v22_reg));
5391 match(RegD);
5392 op_cost(0);
5393 format %{ %}
5394 interface(REG_INTER);
5395 %}
5396
5397 operand vRegD_V23()
5398 %{
5399 constraint(ALLOC_IN_RC(v23_reg));
5400 match(RegD);
5401 op_cost(0);
5402 format %{ %}
5403 interface(REG_INTER);
5404 %}
5405
5406 operand vRegD_V24()
5407 %{
5408 constraint(ALLOC_IN_RC(v24_reg));
5409 match(RegD);
5410 op_cost(0);
5411 format %{ %}
5412 interface(REG_INTER);
5413 %}
5414
5415 operand vRegD_V25()
5416 %{
5417 constraint(ALLOC_IN_RC(v25_reg));
5418 match(RegD);
5419 op_cost(0);
5420 format %{ %}
5421 interface(REG_INTER);
5422 %}
5423
5424 operand vRegD_V26()
5425 %{
5426 constraint(ALLOC_IN_RC(v26_reg));
5427 match(RegD);
5428 op_cost(0);
5429 format %{ %}
5430 interface(REG_INTER);
5431 %}
5432
5433 operand vRegD_V27()
5434 %{
5435 constraint(ALLOC_IN_RC(v27_reg));
5436 match(RegD);
5437 op_cost(0);
5438 format %{ %}
5439 interface(REG_INTER);
5440 %}
5441
5442 operand vRegD_V28()
5443 %{
5444 constraint(ALLOC_IN_RC(v28_reg));
5445 match(RegD);
5446 op_cost(0);
5447 format %{ %}
5448 interface(REG_INTER);
5449 %}
5450
5451 operand vRegD_V29()
5452 %{
5453 constraint(ALLOC_IN_RC(v29_reg));
5454 match(RegD);
5455 op_cost(0);
5456 format %{ %}
5457 interface(REG_INTER);
5458 %}
5459
5460 operand vRegD_V30()
5461 %{
5462 constraint(ALLOC_IN_RC(v30_reg));
5463 match(RegD);
5464 op_cost(0);
5465 format %{ %}
5466 interface(REG_INTER);
5467 %}
5468
5469 operand vRegD_V31()
5470 %{
5471 constraint(ALLOC_IN_RC(v31_reg));
5472 match(RegD);
5473 op_cost(0);
5474 format %{ %}
5475 interface(REG_INTER);
5476 %}
5477
5478 operand pReg()
5479 %{
5480 constraint(ALLOC_IN_RC(pr_reg));
5481 match(RegVectMask);
5482 match(pRegGov);
5483 op_cost(0);
5484 format %{ %}
5485 interface(REG_INTER);
5486 %}
5487
5488 operand pRegGov()
5489 %{
5490 constraint(ALLOC_IN_RC(gov_pr));
5491 match(RegVectMask);
5492 match(pReg);
5493 op_cost(0);
5494 format %{ %}
5495 interface(REG_INTER);
5496 %}
5497
5498 operand pRegGov_P0()
5499 %{
5500 constraint(ALLOC_IN_RC(p0_reg));
5501 match(RegVectMask);
5502 op_cost(0);
5503 format %{ %}
5504 interface(REG_INTER);
5505 %}
5506
5507 operand pRegGov_P1()
5508 %{
5509 constraint(ALLOC_IN_RC(p1_reg));
5510 match(RegVectMask);
5511 op_cost(0);
5512 format %{ %}
5513 interface(REG_INTER);
5514 %}
5515
5516 // Flags register, used as output of signed compare instructions
5517
5518 // note that on AArch64 we also use this register as the output for
5519 // for floating point compare instructions (CmpF CmpD). this ensures
5520 // that ordered inequality tests use GT, GE, LT or LE none of which
5521 // pass through cases where the result is unordered i.e. one or both
5522 // inputs to the compare is a NaN. this means that the ideal code can
5523 // replace e.g. a GT with an LE and not end up capturing the NaN case
5524 // (where the comparison should always fail). EQ and NE tests are
5525 // always generated in ideal code so that unordered folds into the NE
5526 // case, matching the behaviour of AArch64 NE.
5527 //
5528 // This differs from x86 where the outputs of FP compares use a
5529 // special FP flags registers and where compares based on this
5530 // register are distinguished into ordered inequalities (cmpOpUCF) and
5531 // EQ/NEQ tests (cmpOpUCF2). x86 has to special case the latter tests
5532 // to explicitly handle the unordered case in branches. x86 also has
5533 // to include extra CMoveX rules to accept a cmpOpUCF input.
5534
5535 operand rFlagsReg()
5536 %{
5537 constraint(ALLOC_IN_RC(int_flags));
5538 match(RegFlags);
5539
5540 op_cost(0);
5541 format %{ "RFLAGS" %}
5542 interface(REG_INTER);
5543 %}
5544
5545 // Flags register, used as output of unsigned compare instructions
5546 operand rFlagsRegU()
5547 %{
5548 constraint(ALLOC_IN_RC(int_flags));
5549 match(RegFlags);
5550
5551 op_cost(0);
5552 format %{ "RFLAGSU" %}
5553 interface(REG_INTER);
5554 %}
5555
5556 // Special Registers
5557
5558 // Method Register
5559 operand inline_cache_RegP(iRegP reg)
5560 %{
5561 constraint(ALLOC_IN_RC(method_reg)); // inline_cache_reg
5562 match(reg);
5563 match(iRegPNoSp);
5564 op_cost(0);
5565 format %{ %}
5566 interface(REG_INTER);
5567 %}
5568
5569 // Thread Register
5570 operand thread_RegP(iRegP reg)
5571 %{
5572 constraint(ALLOC_IN_RC(thread_reg)); // link_reg
5573 match(reg);
5574 op_cost(0);
5575 format %{ %}
5576 interface(REG_INTER);
5577 %}
5578
5579 operand lr_RegP(iRegP reg)
5580 %{
5581 constraint(ALLOC_IN_RC(lr_reg)); // link_reg
5582 match(reg);
5583 op_cost(0);
5584 format %{ %}
5585 interface(REG_INTER);
5586 %}
5587
5588 //----------Memory Operands----------------------------------------------------
5589
5590 operand indirect(iRegP reg)
5591 %{
5592 constraint(ALLOC_IN_RC(ptr_reg));
5593 match(reg);
5594 op_cost(0);
5595 format %{ "[$reg]" %}
5596 interface(MEMORY_INTER) %{
5597 base($reg);
5598 index(0xffffffff);
5599 scale(0x0);
5600 disp(0x0);
5601 %}
5602 %}
5603
5604 operand indIndexScaledI2L(iRegP reg, iRegI ireg, immIScale scale)
5605 %{
5606 constraint(ALLOC_IN_RC(ptr_reg));
5607 predicate(size_fits_all_mem_uses(n->as_AddP(), n->in(AddPNode::Offset)->in(2)->get_int()));
5608 match(AddP reg (LShiftL (ConvI2L ireg) scale));
5609 op_cost(0);
5610 format %{ "$reg, $ireg sxtw($scale), 0, I2L" %}
5611 interface(MEMORY_INTER) %{
5612 base($reg);
5613 index($ireg);
5614 scale($scale);
5615 disp(0x0);
5616 %}
5617 %}
5618
5619 operand indIndexScaled(iRegP reg, iRegL lreg, immIScale scale)
5620 %{
5621 constraint(ALLOC_IN_RC(ptr_reg));
5622 predicate(size_fits_all_mem_uses(n->as_AddP(), n->in(AddPNode::Offset)->in(2)->get_int()));
5623 match(AddP reg (LShiftL lreg scale));
5624 op_cost(0);
5625 format %{ "$reg, $lreg lsl($scale)" %}
5626 interface(MEMORY_INTER) %{
5627 base($reg);
5628 index($lreg);
5629 scale($scale);
5630 disp(0x0);
5631 %}
5632 %}
5633
5634 operand indIndexI2L(iRegP reg, iRegI ireg)
5635 %{
5636 constraint(ALLOC_IN_RC(ptr_reg));
5637 match(AddP reg (ConvI2L ireg));
5638 op_cost(0);
5639 format %{ "$reg, $ireg, 0, I2L" %}
5640 interface(MEMORY_INTER) %{
5641 base($reg);
5642 index($ireg);
5643 scale(0x0);
5644 disp(0x0);
5645 %}
5646 %}
5647
5648 operand indIndex(iRegP reg, iRegL lreg)
5649 %{
5650 constraint(ALLOC_IN_RC(ptr_reg));
5651 match(AddP reg lreg);
5652 op_cost(0);
5653 format %{ "$reg, $lreg" %}
5654 interface(MEMORY_INTER) %{
5655 base($reg);
5656 index($lreg);
5657 scale(0x0);
5658 disp(0x0);
5659 %}
5660 %}
5661
5662 operand indOffI(iRegP reg, immIOffset off)
5663 %{
5664 constraint(ALLOC_IN_RC(ptr_reg));
5665 match(AddP reg off);
5666 op_cost(0);
5667 format %{ "[$reg, $off]" %}
5668 interface(MEMORY_INTER) %{
5669 base($reg);
5670 index(0xffffffff);
5671 scale(0x0);
5672 disp($off);
5673 %}
5674 %}
5675
5676 operand indOffI1(iRegP reg, immIOffset1 off)
5677 %{
5678 constraint(ALLOC_IN_RC(ptr_reg));
5679 match(AddP reg off);
5680 op_cost(0);
5681 format %{ "[$reg, $off]" %}
5682 interface(MEMORY_INTER) %{
5683 base($reg);
5684 index(0xffffffff);
5685 scale(0x0);
5686 disp($off);
5687 %}
5688 %}
5689
5690 operand indOffI2(iRegP reg, immIOffset2 off)
5691 %{
5692 constraint(ALLOC_IN_RC(ptr_reg));
5693 match(AddP reg off);
5694 op_cost(0);
5695 format %{ "[$reg, $off]" %}
5696 interface(MEMORY_INTER) %{
5697 base($reg);
5698 index(0xffffffff);
5699 scale(0x0);
5700 disp($off);
5701 %}
5702 %}
5703
5704 operand indOffI4(iRegP reg, immIOffset4 off)
5705 %{
5706 constraint(ALLOC_IN_RC(ptr_reg));
5707 match(AddP reg off);
5708 op_cost(0);
5709 format %{ "[$reg, $off]" %}
5710 interface(MEMORY_INTER) %{
5711 base($reg);
5712 index(0xffffffff);
5713 scale(0x0);
5714 disp($off);
5715 %}
5716 %}
5717
5718 operand indOffI8(iRegP reg, immIOffset8 off)
5719 %{
5720 constraint(ALLOC_IN_RC(ptr_reg));
5721 match(AddP reg off);
5722 op_cost(0);
5723 format %{ "[$reg, $off]" %}
5724 interface(MEMORY_INTER) %{
5725 base($reg);
5726 index(0xffffffff);
5727 scale(0x0);
5728 disp($off);
5729 %}
5730 %}
5731
5732 operand indOffI16(iRegP reg, immIOffset16 off)
5733 %{
5734 constraint(ALLOC_IN_RC(ptr_reg));
5735 match(AddP reg off);
5736 op_cost(0);
5737 format %{ "[$reg, $off]" %}
5738 interface(MEMORY_INTER) %{
5739 base($reg);
5740 index(0xffffffff);
5741 scale(0x0);
5742 disp($off);
5743 %}
5744 %}
5745
5746 operand indOffL(iRegP reg, immLoffset off)
5747 %{
5748 constraint(ALLOC_IN_RC(ptr_reg));
5749 match(AddP reg off);
5750 op_cost(0);
5751 format %{ "[$reg, $off]" %}
5752 interface(MEMORY_INTER) %{
5753 base($reg);
5754 index(0xffffffff);
5755 scale(0x0);
5756 disp($off);
5757 %}
5758 %}
5759
5760 operand indOffL1(iRegP reg, immLoffset1 off)
5761 %{
5762 constraint(ALLOC_IN_RC(ptr_reg));
5763 match(AddP reg off);
5764 op_cost(0);
5765 format %{ "[$reg, $off]" %}
5766 interface(MEMORY_INTER) %{
5767 base($reg);
5768 index(0xffffffff);
5769 scale(0x0);
5770 disp($off);
5771 %}
5772 %}
5773
5774 operand indOffL2(iRegP reg, immLoffset2 off)
5775 %{
5776 constraint(ALLOC_IN_RC(ptr_reg));
5777 match(AddP reg off);
5778 op_cost(0);
5779 format %{ "[$reg, $off]" %}
5780 interface(MEMORY_INTER) %{
5781 base($reg);
5782 index(0xffffffff);
5783 scale(0x0);
5784 disp($off);
5785 %}
5786 %}
5787
5788 operand indOffL4(iRegP reg, immLoffset4 off)
5789 %{
5790 constraint(ALLOC_IN_RC(ptr_reg));
5791 match(AddP reg off);
5792 op_cost(0);
5793 format %{ "[$reg, $off]" %}
5794 interface(MEMORY_INTER) %{
5795 base($reg);
5796 index(0xffffffff);
5797 scale(0x0);
5798 disp($off);
5799 %}
5800 %}
5801
5802 operand indOffL8(iRegP reg, immLoffset8 off)
5803 %{
5804 constraint(ALLOC_IN_RC(ptr_reg));
5805 match(AddP reg off);
5806 op_cost(0);
5807 format %{ "[$reg, $off]" %}
5808 interface(MEMORY_INTER) %{
5809 base($reg);
5810 index(0xffffffff);
5811 scale(0x0);
5812 disp($off);
5813 %}
5814 %}
5815
5816 operand indOffL16(iRegP reg, immLoffset16 off)
5817 %{
5818 constraint(ALLOC_IN_RC(ptr_reg));
5819 match(AddP reg off);
5820 op_cost(0);
5821 format %{ "[$reg, $off]" %}
5822 interface(MEMORY_INTER) %{
5823 base($reg);
5824 index(0xffffffff);
5825 scale(0x0);
5826 disp($off);
5827 %}
5828 %}
5829
5830 operand indirectN(iRegN reg)
5831 %{
5832 predicate(CompressedOops::shift() == 0);
5833 constraint(ALLOC_IN_RC(ptr_reg));
5834 match(DecodeN reg);
5835 op_cost(0);
5836 format %{ "[$reg]\t# narrow" %}
5837 interface(MEMORY_INTER) %{
5838 base($reg);
5839 index(0xffffffff);
5840 scale(0x0);
5841 disp(0x0);
5842 %}
5843 %}
5844
5845 operand indIndexScaledI2LN(iRegN reg, iRegI ireg, immIScale scale)
5846 %{
5847 predicate(CompressedOops::shift() == 0 && size_fits_all_mem_uses(n->as_AddP(), n->in(AddPNode::Offset)->in(2)->get_int()));
5848 constraint(ALLOC_IN_RC(ptr_reg));
5849 match(AddP (DecodeN reg) (LShiftL (ConvI2L ireg) scale));
5850 op_cost(0);
5851 format %{ "$reg, $ireg sxtw($scale), 0, I2L\t# narrow" %}
5852 interface(MEMORY_INTER) %{
5853 base($reg);
5854 index($ireg);
5855 scale($scale);
5856 disp(0x0);
5857 %}
5858 %}
5859
5860 operand indIndexScaledN(iRegN reg, iRegL lreg, immIScale scale)
5861 %{
5862 predicate(CompressedOops::shift() == 0 && size_fits_all_mem_uses(n->as_AddP(), n->in(AddPNode::Offset)->in(2)->get_int()));
5863 constraint(ALLOC_IN_RC(ptr_reg));
5864 match(AddP (DecodeN reg) (LShiftL lreg scale));
5865 op_cost(0);
5866 format %{ "$reg, $lreg lsl($scale)\t# narrow" %}
5867 interface(MEMORY_INTER) %{
5868 base($reg);
5869 index($lreg);
5870 scale($scale);
5871 disp(0x0);
5872 %}
5873 %}
5874
5875 operand indIndexI2LN(iRegN reg, iRegI ireg)
5876 %{
5877 predicate(CompressedOops::shift() == 0);
5878 constraint(ALLOC_IN_RC(ptr_reg));
5879 match(AddP (DecodeN reg) (ConvI2L ireg));
5880 op_cost(0);
5881 format %{ "$reg, $ireg, 0, I2L\t# narrow" %}
5882 interface(MEMORY_INTER) %{
5883 base($reg);
5884 index($ireg);
5885 scale(0x0);
5886 disp(0x0);
5887 %}
5888 %}
5889
5890 operand indIndexN(iRegN reg, iRegL lreg)
5891 %{
5892 predicate(CompressedOops::shift() == 0);
5893 constraint(ALLOC_IN_RC(ptr_reg));
5894 match(AddP (DecodeN reg) lreg);
5895 op_cost(0);
5896 format %{ "$reg, $lreg\t# narrow" %}
5897 interface(MEMORY_INTER) %{
5898 base($reg);
5899 index($lreg);
5900 scale(0x0);
5901 disp(0x0);
5902 %}
5903 %}
5904
5905 operand indOffIN(iRegN reg, immIOffset off)
5906 %{
5907 predicate(CompressedOops::shift() == 0);
5908 constraint(ALLOC_IN_RC(ptr_reg));
5909 match(AddP (DecodeN reg) off);
5910 op_cost(0);
5911 format %{ "[$reg, $off]\t# narrow" %}
5912 interface(MEMORY_INTER) %{
5913 base($reg);
5914 index(0xffffffff);
5915 scale(0x0);
5916 disp($off);
5917 %}
5918 %}
5919
5920 operand indOffLN(iRegN reg, immLoffset off)
5921 %{
5922 predicate(CompressedOops::shift() == 0);
5923 constraint(ALLOC_IN_RC(ptr_reg));
5924 match(AddP (DecodeN reg) off);
5925 op_cost(0);
5926 format %{ "[$reg, $off]\t# narrow" %}
5927 interface(MEMORY_INTER) %{
5928 base($reg);
5929 index(0xffffffff);
5930 scale(0x0);
5931 disp($off);
5932 %}
5933 %}
5934
5935
5936
5937 // AArch64 opto stubs need to write to the pc slot in the thread anchor
5938 operand thread_anchor_pc(thread_RegP reg, immL_pc_off off)
5939 %{
5940 constraint(ALLOC_IN_RC(ptr_reg));
5941 match(AddP reg off);
5942 op_cost(0);
5943 format %{ "[$reg, $off]" %}
5944 interface(MEMORY_INTER) %{
5945 base($reg);
5946 index(0xffffffff);
5947 scale(0x0);
5948 disp($off);
5949 %}
5950 %}
5951
5952 //----------Special Memory Operands--------------------------------------------
5953 // Stack Slot Operand - This operand is used for loading and storing temporary
5954 // values on the stack where a match requires a value to
5955 // flow through memory.
5956 operand stackSlotP(sRegP reg)
5957 %{
5958 constraint(ALLOC_IN_RC(stack_slots));
5959 op_cost(100);
5960 // No match rule because this operand is only generated in matching
5961 // match(RegP);
5962 format %{ "[$reg]" %}
5963 interface(MEMORY_INTER) %{
5964 base(0x1e); // RSP
5965 index(0x0); // No Index
5966 scale(0x0); // No Scale
5967 disp($reg); // Stack Offset
5968 %}
5969 %}
5970
5971 operand stackSlotI(sRegI reg)
5972 %{
5973 constraint(ALLOC_IN_RC(stack_slots));
5974 // No match rule because this operand is only generated in matching
5975 // match(RegI);
5976 format %{ "[$reg]" %}
5977 interface(MEMORY_INTER) %{
5978 base(0x1e); // RSP
5979 index(0x0); // No Index
5980 scale(0x0); // No Scale
5981 disp($reg); // Stack Offset
5982 %}
5983 %}
5984
5985 operand stackSlotF(sRegF reg)
5986 %{
5987 constraint(ALLOC_IN_RC(stack_slots));
5988 // No match rule because this operand is only generated in matching
5989 // match(RegF);
5990 format %{ "[$reg]" %}
5991 interface(MEMORY_INTER) %{
5992 base(0x1e); // RSP
5993 index(0x0); // No Index
5994 scale(0x0); // No Scale
5995 disp($reg); // Stack Offset
5996 %}
5997 %}
5998
5999 operand stackSlotD(sRegD reg)
6000 %{
6001 constraint(ALLOC_IN_RC(stack_slots));
6002 // No match rule because this operand is only generated in matching
6003 // match(RegD);
6004 format %{ "[$reg]" %}
6005 interface(MEMORY_INTER) %{
6006 base(0x1e); // RSP
6007 index(0x0); // No Index
6008 scale(0x0); // No Scale
6009 disp($reg); // Stack Offset
6010 %}
6011 %}
6012
6013 operand stackSlotL(sRegL reg)
6014 %{
6015 constraint(ALLOC_IN_RC(stack_slots));
6016 // No match rule because this operand is only generated in matching
6017 // match(RegL);
6018 format %{ "[$reg]" %}
6019 interface(MEMORY_INTER) %{
6020 base(0x1e); // RSP
6021 index(0x0); // No Index
6022 scale(0x0); // No Scale
6023 disp($reg); // Stack Offset
6024 %}
6025 %}
6026
6027 // Operands for expressing Control Flow
6028 // NOTE: Label is a predefined operand which should not be redefined in
6029 // the AD file. It is generically handled within the ADLC.
6030
6031 //----------Conditional Branch Operands----------------------------------------
6032 // Comparison Op - This is the operation of the comparison, and is limited to
6033 // the following set of codes:
6034 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
6035 //
6036 // Other attributes of the comparison, such as unsignedness, are specified
6037 // by the comparison instruction that sets a condition code flags register.
6038 // That result is represented by a flags operand whose subtype is appropriate
6039 // to the unsignedness (etc.) of the comparison.
6040 //
6041 // Later, the instruction which matches both the Comparison Op (a Bool) and
6042 // the flags (produced by the Cmp) specifies the coding of the comparison op
6043 // by matching a specific subtype of Bool operand below, such as cmpOpU.
6044
6045 // used for signed integral comparisons and fp comparisons
6046
6047 operand cmpOp()
6048 %{
6049 match(Bool);
6050
6051 format %{ "" %}
6052 interface(COND_INTER) %{
6053 equal(0x0, "eq");
6054 not_equal(0x1, "ne");
6055 less(0xb, "lt");
6056 greater_equal(0xa, "ge");
6057 less_equal(0xd, "le");
6058 greater(0xc, "gt");
6059 overflow(0x6, "vs");
6060 no_overflow(0x7, "vc");
6061 %}
6062 %}
6063
6064 // used for unsigned integral comparisons
6065
6066 operand cmpOpU()
6067 %{
6068 match(Bool);
6069
6070 format %{ "" %}
6071 interface(COND_INTER) %{
6072 equal(0x0, "eq");
6073 not_equal(0x1, "ne");
6074 less(0x3, "lo");
6075 greater_equal(0x2, "hs");
6076 less_equal(0x9, "ls");
6077 greater(0x8, "hi");
6078 overflow(0x6, "vs");
6079 no_overflow(0x7, "vc");
6080 %}
6081 %}
6082
6083 // used for certain integral comparisons which can be
6084 // converted to cbxx or tbxx instructions
6085
6086 operand cmpOpEqNe()
6087 %{
6088 match(Bool);
6089 op_cost(0);
6090 predicate(n->as_Bool()->_test._test == BoolTest::ne
6091 || n->as_Bool()->_test._test == BoolTest::eq);
6092
6093 format %{ "" %}
6094 interface(COND_INTER) %{
6095 equal(0x0, "eq");
6096 not_equal(0x1, "ne");
6097 less(0xb, "lt");
6098 greater_equal(0xa, "ge");
6099 less_equal(0xd, "le");
6100 greater(0xc, "gt");
6101 overflow(0x6, "vs");
6102 no_overflow(0x7, "vc");
6103 %}
6104 %}
6105
6106 // used for certain integral comparisons which can be
6107 // converted to cbxx or tbxx instructions
6108
6109 operand cmpOpLtGe()
6110 %{
6111 match(Bool);
6112 op_cost(0);
6113
6114 predicate(n->as_Bool()->_test._test == BoolTest::lt
6115 || n->as_Bool()->_test._test == BoolTest::ge);
6116
6117 format %{ "" %}
6118 interface(COND_INTER) %{
6119 equal(0x0, "eq");
6120 not_equal(0x1, "ne");
6121 less(0xb, "lt");
6122 greater_equal(0xa, "ge");
6123 less_equal(0xd, "le");
6124 greater(0xc, "gt");
6125 overflow(0x6, "vs");
6126 no_overflow(0x7, "vc");
6127 %}
6128 %}
6129
6130 // used for certain unsigned integral comparisons which can be
6131 // converted to cbxx or tbxx instructions
6132
6133 operand cmpOpUEqNeLtGe()
6134 %{
6135 match(Bool);
6136 op_cost(0);
6137
6138 predicate(n->as_Bool()->_test._test == BoolTest::eq
6139 || n->as_Bool()->_test._test == BoolTest::ne
6140 || n->as_Bool()->_test._test == BoolTest::lt
6141 || n->as_Bool()->_test._test == BoolTest::ge);
6142
6143 format %{ "" %}
6144 interface(COND_INTER) %{
6145 equal(0x0, "eq");
6146 not_equal(0x1, "ne");
6147 less(0xb, "lt");
6148 greater_equal(0xa, "ge");
6149 less_equal(0xd, "le");
6150 greater(0xc, "gt");
6151 overflow(0x6, "vs");
6152 no_overflow(0x7, "vc");
6153 %}
6154 %}
6155
6156 // Special operand allowing long args to int ops to be truncated for free
6157
6158 operand iRegL2I(iRegL reg) %{
6159
6160 op_cost(0);
6161
6162 match(ConvL2I reg);
6163
6164 format %{ "l2i($reg)" %}
6165
6166 interface(REG_INTER)
6167 %}
6168
6169 opclass vmem2(indirect, indIndex, indOffI2, indOffL2);
6170 opclass vmem4(indirect, indIndex, indOffI4, indOffL4);
6171 opclass vmem8(indirect, indIndex, indOffI8, indOffL8);
6172 opclass vmem16(indirect, indIndex, indOffI16, indOffL16);
6173
6174 //----------OPERAND CLASSES----------------------------------------------------
6175 // Operand Classes are groups of operands that are used as to simplify
6176 // instruction definitions by not requiring the AD writer to specify
6177 // separate instructions for every form of operand when the
6178 // instruction accepts multiple operand types with the same basic
6179 // encoding and format. The classic case of this is memory operands.
6180
6181 // memory is used to define read/write location for load/store
6182 // instruction defs. we can turn a memory op into an Address
6183
6184 opclass memory1(indirect, indIndexScaled, indIndexScaledI2L, indIndexI2L, indIndex, indOffI1, indOffL1,
6185 indirectN, indIndexScaledN, indIndexScaledI2LN, indIndexI2LN, indIndexN);
6186
6187 opclass memory2(indirect, indIndexScaled, indIndexScaledI2L, indIndexI2L, indIndex, indOffI2, indOffL2,
6188 indirectN, indIndexScaledN, indIndexScaledI2LN, indIndexI2LN, indIndexN);
6189
6190 opclass memory4(indirect, indIndexScaled, indIndexScaledI2L, indIndexI2L, indIndex, indOffI4, indOffL4,
6191 indirectN, indIndexScaledN, indIndexScaledI2LN, indIndexI2LN, indIndexN, indOffIN, indOffLN);
6192
6193 opclass memory8(indirect, indIndexScaled, indIndexScaledI2L, indIndexI2L, indIndex, indOffI8, indOffL8,
6194 indirectN, indIndexScaledN, indIndexScaledI2LN, indIndexI2LN, indIndexN, indOffIN, indOffLN);
6195
6196 // All of the memory operands. For the pipeline description.
6197 opclass memory(indirect, indIndexScaled, indIndexScaledI2L, indIndexI2L, indIndex,
6198 indOffI1, indOffL1, indOffI2, indOffL2, indOffI4, indOffL4, indOffI8, indOffL8,
6199 indirectN, indIndexScaledN, indIndexScaledI2LN, indIndexI2LN, indIndexN, indOffIN, indOffLN);
6200
6201
6202 // iRegIorL2I is used for src inputs in rules for 32 bit int (I)
6203 // operations. it allows the src to be either an iRegI or a (ConvL2I
6204 // iRegL). in the latter case the l2i normally planted for a ConvL2I
6205 // can be elided because the 32-bit instruction will just employ the
6206 // lower 32 bits anyway.
6207 //
6208 // n.b. this does not elide all L2I conversions. if the truncated
6209 // value is consumed by more than one operation then the ConvL2I
6210 // cannot be bundled into the consuming nodes so an l2i gets planted
6211 // (actually a movw $dst $src) and the downstream instructions consume
6212 // the result of the l2i as an iRegI input. That's a shame since the
6213 // movw is actually redundant but its not too costly.
6214
6215 opclass iRegIorL2I(iRegI, iRegL2I);
6216
6217 //----------PIPELINE-----------------------------------------------------------
6218 // Rules which define the behavior of the target architectures pipeline.
6219
6220 // For specific pipelines, eg A53, define the stages of that pipeline
6221 //pipe_desc(ISS, EX1, EX2, WR);
6222 #define ISS S0
6223 #define EX1 S1
6224 #define EX2 S2
6225 #define WR S3
6226
6227 // Integer ALU reg operation
6228 pipeline %{
6229
6230 attributes %{
6231 // ARM instructions are of fixed length
6232 fixed_size_instructions; // Fixed size instructions TODO does
6233 max_instructions_per_bundle = 4; // A53 = 2, A57 = 4
6234 // ARM instructions come in 32-bit word units
6235 instruction_unit_size = 4; // An instruction is 4 bytes long
6236 instruction_fetch_unit_size = 64; // The processor fetches one line
6237 instruction_fetch_units = 1; // of 64 bytes
6238
6239 // List of nop instructions
6240 nops( MachNop );
6241 %}
6242
6243 // We don't use an actual pipeline model so don't care about resources
6244 // or description. we do use pipeline classes to introduce fixed
6245 // latencies
6246
6247 //----------RESOURCES----------------------------------------------------------
6248 // Resources are the functional units available to the machine
6249
6250 resources( INS0, INS1, INS01 = INS0 | INS1,
6251 ALU0, ALU1, ALU = ALU0 | ALU1,
6252 MAC,
6253 DIV,
6254 BRANCH,
6255 LDST,
6256 NEON_FP);
6257
6258 //----------PIPELINE DESCRIPTION-----------------------------------------------
6259 // Pipeline Description specifies the stages in the machine's pipeline
6260
6261 // Define the pipeline as a generic 6 stage pipeline
6262 pipe_desc(S0, S1, S2, S3, S4, S5);
6263
6264 //----------PIPELINE CLASSES---------------------------------------------------
6265 // Pipeline Classes describe the stages in which input and output are
6266 // referenced by the hardware pipeline.
6267
6268 pipe_class fp_dop_reg_reg_s(vRegF dst, vRegF src1, vRegF src2)
6269 %{
6270 single_instruction;
6271 src1 : S1(read);
6272 src2 : S2(read);
6273 dst : S5(write);
6274 INS01 : ISS;
6275 NEON_FP : S5;
6276 %}
6277
6278 pipe_class fp_dop_reg_reg_d(vRegD dst, vRegD src1, vRegD src2)
6279 %{
6280 single_instruction;
6281 src1 : S1(read);
6282 src2 : S2(read);
6283 dst : S5(write);
6284 INS01 : ISS;
6285 NEON_FP : S5;
6286 %}
6287
6288 pipe_class fp_uop_s(vRegF dst, vRegF src)
6289 %{
6290 single_instruction;
6291 src : S1(read);
6292 dst : S5(write);
6293 INS01 : ISS;
6294 NEON_FP : S5;
6295 %}
6296
6297 pipe_class fp_uop_d(vRegD dst, vRegD src)
6298 %{
6299 single_instruction;
6300 src : S1(read);
6301 dst : S5(write);
6302 INS01 : ISS;
6303 NEON_FP : S5;
6304 %}
6305
6306 pipe_class fp_d2f(vRegF dst, vRegD src)
6307 %{
6308 single_instruction;
6309 src : S1(read);
6310 dst : S5(write);
6311 INS01 : ISS;
6312 NEON_FP : S5;
6313 %}
6314
6315 pipe_class fp_f2d(vRegD dst, vRegF src)
6316 %{
6317 single_instruction;
6318 src : S1(read);
6319 dst : S5(write);
6320 INS01 : ISS;
6321 NEON_FP : S5;
6322 %}
6323
6324 pipe_class fp_f2i(iRegINoSp dst, vRegF src)
6325 %{
6326 single_instruction;
6327 src : S1(read);
6328 dst : S5(write);
6329 INS01 : ISS;
6330 NEON_FP : S5;
6331 %}
6332
6333 pipe_class fp_f2l(iRegLNoSp dst, vRegF src)
6334 %{
6335 single_instruction;
6336 src : S1(read);
6337 dst : S5(write);
6338 INS01 : ISS;
6339 NEON_FP : S5;
6340 %}
6341
6342 pipe_class fp_i2f(vRegF dst, iRegIorL2I src)
6343 %{
6344 single_instruction;
6345 src : S1(read);
6346 dst : S5(write);
6347 INS01 : ISS;
6348 NEON_FP : S5;
6349 %}
6350
6351 pipe_class fp_l2f(vRegF dst, iRegL src)
6352 %{
6353 single_instruction;
6354 src : S1(read);
6355 dst : S5(write);
6356 INS01 : ISS;
6357 NEON_FP : S5;
6358 %}
6359
6360 pipe_class fp_d2i(iRegINoSp dst, vRegD src)
6361 %{
6362 single_instruction;
6363 src : S1(read);
6364 dst : S5(write);
6365 INS01 : ISS;
6366 NEON_FP : S5;
6367 %}
6368
6369 pipe_class fp_d2l(iRegLNoSp dst, vRegD src)
6370 %{
6371 single_instruction;
6372 src : S1(read);
6373 dst : S5(write);
6374 INS01 : ISS;
6375 NEON_FP : S5;
6376 %}
6377
6378 pipe_class fp_i2d(vRegD dst, iRegIorL2I src)
6379 %{
6380 single_instruction;
6381 src : S1(read);
6382 dst : S5(write);
6383 INS01 : ISS;
6384 NEON_FP : S5;
6385 %}
6386
6387 pipe_class fp_l2d(vRegD dst, iRegIorL2I src)
6388 %{
6389 single_instruction;
6390 src : S1(read);
6391 dst : S5(write);
6392 INS01 : ISS;
6393 NEON_FP : S5;
6394 %}
6395
6396 pipe_class fp_div_s(vRegF dst, vRegF src1, vRegF src2)
6397 %{
6398 single_instruction;
6399 src1 : S1(read);
6400 src2 : S2(read);
6401 dst : S5(write);
6402 INS0 : ISS;
6403 NEON_FP : S5;
6404 %}
6405
6406 pipe_class fp_div_d(vRegD dst, vRegD src1, vRegD src2)
6407 %{
6408 single_instruction;
6409 src1 : S1(read);
6410 src2 : S2(read);
6411 dst : S5(write);
6412 INS0 : ISS;
6413 NEON_FP : S5;
6414 %}
6415
6416 pipe_class fp_cond_reg_reg_s(vRegF dst, vRegF src1, vRegF src2, rFlagsReg cr)
6417 %{
6418 single_instruction;
6419 cr : S1(read);
6420 src1 : S1(read);
6421 src2 : S1(read);
6422 dst : S3(write);
6423 INS01 : ISS;
6424 NEON_FP : S3;
6425 %}
6426
6427 pipe_class fp_cond_reg_reg_d(vRegD dst, vRegD src1, vRegD src2, rFlagsReg cr)
6428 %{
6429 single_instruction;
6430 cr : S1(read);
6431 src1 : S1(read);
6432 src2 : S1(read);
6433 dst : S3(write);
6434 INS01 : ISS;
6435 NEON_FP : S3;
6436 %}
6437
6438 pipe_class fp_imm_s(vRegF dst)
6439 %{
6440 single_instruction;
6441 dst : S3(write);
6442 INS01 : ISS;
6443 NEON_FP : S3;
6444 %}
6445
6446 pipe_class fp_imm_d(vRegD dst)
6447 %{
6448 single_instruction;
6449 dst : S3(write);
6450 INS01 : ISS;
6451 NEON_FP : S3;
6452 %}
6453
6454 pipe_class fp_load_constant_s(vRegF dst)
6455 %{
6456 single_instruction;
6457 dst : S4(write);
6458 INS01 : ISS;
6459 NEON_FP : S4;
6460 %}
6461
6462 pipe_class fp_load_constant_d(vRegD dst)
6463 %{
6464 single_instruction;
6465 dst : S4(write);
6466 INS01 : ISS;
6467 NEON_FP : S4;
6468 %}
6469
6470 //------- Integer ALU operations --------------------------
6471
6472 // Integer ALU reg-reg operation
6473 // Operands needed in EX1, result generated in EX2
6474 // Eg. ADD x0, x1, x2
6475 pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2)
6476 %{
6477 single_instruction;
6478 dst : EX2(write);
6479 src1 : EX1(read);
6480 src2 : EX1(read);
6481 INS01 : ISS; // Dual issue as instruction 0 or 1
6482 ALU : EX2;
6483 %}
6484
6485 // Integer ALU reg-reg operation with constant shift
6486 // Shifted register must be available in LATE_ISS instead of EX1
6487 // Eg. ADD x0, x1, x2, LSL #2
6488 pipe_class ialu_reg_reg_shift(iRegI dst, iRegI src1, iRegI src2, immI shift)
6489 %{
6490 single_instruction;
6491 dst : EX2(write);
6492 src1 : EX1(read);
6493 src2 : ISS(read);
6494 INS01 : ISS;
6495 ALU : EX2;
6496 %}
6497
6498 // Integer ALU reg operation with constant shift
6499 // Eg. LSL x0, x1, #shift
6500 pipe_class ialu_reg_shift(iRegI dst, iRegI src1)
6501 %{
6502 single_instruction;
6503 dst : EX2(write);
6504 src1 : ISS(read);
6505 INS01 : ISS;
6506 ALU : EX2;
6507 %}
6508
6509 // Integer ALU reg-reg operation with variable shift
6510 // Both operands must be available in LATE_ISS instead of EX1
6511 // Result is available in EX1 instead of EX2
6512 // Eg. LSLV x0, x1, x2
6513 pipe_class ialu_reg_reg_vshift(iRegI dst, iRegI src1, iRegI src2)
6514 %{
6515 single_instruction;
6516 dst : EX1(write);
6517 src1 : ISS(read);
6518 src2 : ISS(read);
6519 INS01 : ISS;
6520 ALU : EX1;
6521 %}
6522
6523 // Integer ALU reg-reg operation with extract
6524 // As for _vshift above, but result generated in EX2
6525 // Eg. EXTR x0, x1, x2, #N
6526 pipe_class ialu_reg_reg_extr(iRegI dst, iRegI src1, iRegI src2)
6527 %{
6528 single_instruction;
6529 dst : EX2(write);
6530 src1 : ISS(read);
6531 src2 : ISS(read);
6532 INS1 : ISS; // Can only dual issue as Instruction 1
6533 ALU : EX1;
6534 %}
6535
6536 // Integer ALU reg operation
6537 // Eg. NEG x0, x1
6538 pipe_class ialu_reg(iRegI dst, iRegI src)
6539 %{
6540 single_instruction;
6541 dst : EX2(write);
6542 src : EX1(read);
6543 INS01 : ISS;
6544 ALU : EX2;
6545 %}
6546
6547 // Integer ALU reg mmediate operation
6548 // Eg. ADD x0, x1, #N
6549 pipe_class ialu_reg_imm(iRegI dst, iRegI src1)
6550 %{
6551 single_instruction;
6552 dst : EX2(write);
6553 src1 : EX1(read);
6554 INS01 : ISS;
6555 ALU : EX2;
6556 %}
6557
6558 // Integer ALU immediate operation (no source operands)
6559 // Eg. MOV x0, #N
6560 pipe_class ialu_imm(iRegI dst)
6561 %{
6562 single_instruction;
6563 dst : EX1(write);
6564 INS01 : ISS;
6565 ALU : EX1;
6566 %}
6567
6568 //------- Compare operation -------------------------------
6569
6570 // Compare reg-reg
6571 // Eg. CMP x0, x1
6572 pipe_class icmp_reg_reg(rFlagsReg cr, iRegI op1, iRegI op2)
6573 %{
6574 single_instruction;
6575 // fixed_latency(16);
6576 cr : EX2(write);
6577 op1 : EX1(read);
6578 op2 : EX1(read);
6579 INS01 : ISS;
6580 ALU : EX2;
6581 %}
6582
6583 // Compare reg-reg
6584 // Eg. CMP x0, #N
6585 pipe_class icmp_reg_imm(rFlagsReg cr, iRegI op1)
6586 %{
6587 single_instruction;
6588 // fixed_latency(16);
6589 cr : EX2(write);
6590 op1 : EX1(read);
6591 INS01 : ISS;
6592 ALU : EX2;
6593 %}
6594
6595 //------- Conditional instructions ------------------------
6596
6597 // Conditional no operands
6598 // Eg. CSINC x0, zr, zr, <cond>
6599 pipe_class icond_none(iRegI dst, rFlagsReg cr)
6600 %{
6601 single_instruction;
6602 cr : EX1(read);
6603 dst : EX2(write);
6604 INS01 : ISS;
6605 ALU : EX2;
6606 %}
6607
6608 // Conditional 2 operand
6609 // EG. CSEL X0, X1, X2, <cond>
6610 pipe_class icond_reg_reg(iRegI dst, iRegI src1, iRegI src2, rFlagsReg cr)
6611 %{
6612 single_instruction;
6613 cr : EX1(read);
6614 src1 : EX1(read);
6615 src2 : EX1(read);
6616 dst : EX2(write);
6617 INS01 : ISS;
6618 ALU : EX2;
6619 %}
6620
6621 // Conditional 2 operand
6622 // EG. CSEL X0, X1, X2, <cond>
6623 pipe_class icond_reg(iRegI dst, iRegI src, rFlagsReg cr)
6624 %{
6625 single_instruction;
6626 cr : EX1(read);
6627 src : EX1(read);
6628 dst : EX2(write);
6629 INS01 : ISS;
6630 ALU : EX2;
6631 %}
6632
6633 //------- Multiply pipeline operations --------------------
6634
6635 // Multiply reg-reg
6636 // Eg. MUL w0, w1, w2
6637 pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2)
6638 %{
6639 single_instruction;
6640 dst : WR(write);
6641 src1 : ISS(read);
6642 src2 : ISS(read);
6643 INS01 : ISS;
6644 MAC : WR;
6645 %}
6646
6647 // Multiply accumulate
6648 // Eg. MADD w0, w1, w2, w3
6649 pipe_class imac_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI src3)
6650 %{
6651 single_instruction;
6652 dst : WR(write);
6653 src1 : ISS(read);
6654 src2 : ISS(read);
6655 src3 : ISS(read);
6656 INS01 : ISS;
6657 MAC : WR;
6658 %}
6659
6660 // Eg. MUL w0, w1, w2
6661 pipe_class lmul_reg_reg(iRegI dst, iRegI src1, iRegI src2)
6662 %{
6663 single_instruction;
6664 fixed_latency(3); // Maximum latency for 64 bit mul
6665 dst : WR(write);
6666 src1 : ISS(read);
6667 src2 : ISS(read);
6668 INS01 : ISS;
6669 MAC : WR;
6670 %}
6671
6672 // Multiply accumulate
6673 // Eg. MADD w0, w1, w2, w3
6674 pipe_class lmac_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI src3)
6675 %{
6676 single_instruction;
6677 fixed_latency(3); // Maximum latency for 64 bit mul
6678 dst : WR(write);
6679 src1 : ISS(read);
6680 src2 : ISS(read);
6681 src3 : ISS(read);
6682 INS01 : ISS;
6683 MAC : WR;
6684 %}
6685
6686 //------- Divide pipeline operations --------------------
6687
6688 // Eg. SDIV w0, w1, w2
6689 pipe_class idiv_reg_reg(iRegI dst, iRegI src1, iRegI src2)
6690 %{
6691 single_instruction;
6692 fixed_latency(8); // Maximum latency for 32 bit divide
6693 dst : WR(write);
6694 src1 : ISS(read);
6695 src2 : ISS(read);
6696 INS0 : ISS; // Can only dual issue as instruction 0
6697 DIV : WR;
6698 %}
6699
6700 // Eg. SDIV x0, x1, x2
6701 pipe_class ldiv_reg_reg(iRegI dst, iRegI src1, iRegI src2)
6702 %{
6703 single_instruction;
6704 fixed_latency(16); // Maximum latency for 64 bit divide
6705 dst : WR(write);
6706 src1 : ISS(read);
6707 src2 : ISS(read);
6708 INS0 : ISS; // Can only dual issue as instruction 0
6709 DIV : WR;
6710 %}
6711
6712 //------- Load pipeline operations ------------------------
6713
6714 // Load - prefetch
6715 // Eg. PFRM <mem>
6716 pipe_class iload_prefetch(memory mem)
6717 %{
6718 single_instruction;
6719 mem : ISS(read);
6720 INS01 : ISS;
6721 LDST : WR;
6722 %}
6723
6724 // Load - reg, mem
6725 // Eg. LDR x0, <mem>
6726 pipe_class iload_reg_mem(iRegI dst, memory mem)
6727 %{
6728 single_instruction;
6729 dst : WR(write);
6730 mem : ISS(read);
6731 INS01 : ISS;
6732 LDST : WR;
6733 %}
6734
6735 // Load - reg, reg
6736 // Eg. LDR x0, [sp, x1]
6737 pipe_class iload_reg_reg(iRegI dst, iRegI src)
6738 %{
6739 single_instruction;
6740 dst : WR(write);
6741 src : ISS(read);
6742 INS01 : ISS;
6743 LDST : WR;
6744 %}
6745
6746 //------- Store pipeline operations -----------------------
6747
6748 // Store - zr, mem
6749 // Eg. STR zr, <mem>
6750 pipe_class istore_mem(memory mem)
6751 %{
6752 single_instruction;
6753 mem : ISS(read);
6754 INS01 : ISS;
6755 LDST : WR;
6756 %}
6757
6758 // Store - reg, mem
6759 // Eg. STR x0, <mem>
6760 pipe_class istore_reg_mem(iRegI src, memory mem)
6761 %{
6762 single_instruction;
6763 mem : ISS(read);
6764 src : EX2(read);
6765 INS01 : ISS;
6766 LDST : WR;
6767 %}
6768
6769 // Store - reg, reg
6770 // Eg. STR x0, [sp, x1]
6771 pipe_class istore_reg_reg(iRegI dst, iRegI src)
6772 %{
6773 single_instruction;
6774 dst : ISS(read);
6775 src : EX2(read);
6776 INS01 : ISS;
6777 LDST : WR;
6778 %}
6779
6780 //------- Store pipeline operations -----------------------
6781
6782 // Branch
6783 pipe_class pipe_branch()
6784 %{
6785 single_instruction;
6786 INS01 : ISS;
6787 BRANCH : EX1;
6788 %}
6789
6790 // Conditional branch
6791 pipe_class pipe_branch_cond(rFlagsReg cr)
6792 %{
6793 single_instruction;
6794 cr : EX1(read);
6795 INS01 : ISS;
6796 BRANCH : EX1;
6797 %}
6798
6799 // Compare & Branch
6800 // EG. CBZ/CBNZ
6801 pipe_class pipe_cmp_branch(iRegI op1)
6802 %{
6803 single_instruction;
6804 op1 : EX1(read);
6805 INS01 : ISS;
6806 BRANCH : EX1;
6807 %}
6808
6809 //------- Synchronisation operations ----------------------
6810
6811 // Any operation requiring serialization.
6812 // EG. DMB/Atomic Ops/Load Acquire/Str Release
6813 pipe_class pipe_serial()
6814 %{
6815 single_instruction;
6816 force_serialization;
6817 fixed_latency(16);
6818 INS01 : ISS(2); // Cannot dual issue with any other instruction
6819 LDST : WR;
6820 %}
6821
6822 // Generic big/slow expanded idiom - also serialized
6823 pipe_class pipe_slow()
6824 %{
6825 instruction_count(10);
6826 multiple_bundles;
6827 force_serialization;
6828 fixed_latency(16);
6829 INS01 : ISS(2); // Cannot dual issue with any other instruction
6830 LDST : WR;
6831 %}
6832
6833 // Empty pipeline class
6834 pipe_class pipe_class_empty()
6835 %{
6836 single_instruction;
6837 fixed_latency(0);
6838 %}
6839
6840 // Default pipeline class.
6841 pipe_class pipe_class_default()
6842 %{
6843 single_instruction;
6844 fixed_latency(2);
6845 %}
6846
6847 // Pipeline class for compares.
6848 pipe_class pipe_class_compare()
6849 %{
6850 single_instruction;
6851 fixed_latency(16);
6852 %}
6853
6854 // Pipeline class for memory operations.
6855 pipe_class pipe_class_memory()
6856 %{
6857 single_instruction;
6858 fixed_latency(16);
6859 %}
6860
6861 // Pipeline class for call.
6862 pipe_class pipe_class_call()
6863 %{
6864 single_instruction;
6865 fixed_latency(100);
6866 %}
6867
6868 // Define the class for the Nop node.
6869 define %{
6870 MachNop = pipe_class_empty;
6871 %}
6872
6873 %}
6874 //----------INSTRUCTIONS-------------------------------------------------------
6875 //
6876 // match -- States which machine-independent subtree may be replaced
6877 // by this instruction.
6878 // ins_cost -- The estimated cost of this instruction is used by instruction
6879 // selection to identify a minimum cost tree of machine
6880 // instructions that matches a tree of machine-independent
6881 // instructions.
6882 // format -- A string providing the disassembly for this instruction.
6883 // The value of an instruction's operand may be inserted
6884 // by referring to it with a '$' prefix.
6885 // opcode -- Three instruction opcodes may be provided. These are referred
6886 // to within an encode class as $primary, $secondary, and $tertiary
6887 // rrspectively. The primary opcode is commonly used to
6888 // indicate the type of machine instruction, while secondary
6889 // and tertiary are often used for prefix options or addressing
6890 // modes.
6891 // ins_encode -- A list of encode classes with parameters. The encode class
6892 // name must have been defined in an 'enc_class' specification
6893 // in the encode section of the architecture description.
6894
6895 // ============================================================================
6896 // Memory (Load/Store) Instructions
6897
6898 // Load Instructions
6899
6900 // Load Byte (8 bit signed)
6901 instruct loadB(iRegINoSp dst, memory1 mem)
6902 %{
6903 match(Set dst (LoadB mem));
6904 predicate(!needs_acquiring_load(n));
6905
6906 ins_cost(4 * INSN_COST);
6907 format %{ "ldrsbw $dst, $mem\t# byte" %}
6908
6909 ins_encode(aarch64_enc_ldrsbw(dst, mem));
6910
6911 ins_pipe(iload_reg_mem);
6912 %}
6913
6914 // Load Byte (8 bit signed) into long
6915 instruct loadB2L(iRegLNoSp dst, memory1 mem)
6916 %{
6917 match(Set dst (ConvI2L (LoadB mem)));
6918 predicate(!needs_acquiring_load(n->in(1)));
6919
6920 ins_cost(4 * INSN_COST);
6921 format %{ "ldrsb $dst, $mem\t# byte" %}
6922
6923 ins_encode(aarch64_enc_ldrsb(dst, mem));
6924
6925 ins_pipe(iload_reg_mem);
6926 %}
6927
6928 // Load Byte (8 bit unsigned)
6929 instruct loadUB(iRegINoSp dst, memory1 mem)
6930 %{
6931 match(Set dst (LoadUB mem));
6932 predicate(!needs_acquiring_load(n));
6933
6934 ins_cost(4 * INSN_COST);
6935 format %{ "ldrbw $dst, $mem\t# byte" %}
6936
6937 ins_encode(aarch64_enc_ldrb(dst, mem));
6938
6939 ins_pipe(iload_reg_mem);
6940 %}
6941
6942 // Load Byte (8 bit unsigned) into long
6943 instruct loadUB2L(iRegLNoSp dst, memory1 mem)
6944 %{
6945 match(Set dst (ConvI2L (LoadUB mem)));
6946 predicate(!needs_acquiring_load(n->in(1)));
6947
6948 ins_cost(4 * INSN_COST);
6949 format %{ "ldrb $dst, $mem\t# byte" %}
6950
6951 ins_encode(aarch64_enc_ldrb(dst, mem));
6952
6953 ins_pipe(iload_reg_mem);
6954 %}
6955
6956 // Load Short (16 bit signed)
6957 instruct loadS(iRegINoSp dst, memory2 mem)
6958 %{
6959 match(Set dst (LoadS mem));
6960 predicate(!needs_acquiring_load(n));
6961
6962 ins_cost(4 * INSN_COST);
6963 format %{ "ldrshw $dst, $mem\t# short" %}
6964
6965 ins_encode(aarch64_enc_ldrshw(dst, mem));
6966
6967 ins_pipe(iload_reg_mem);
6968 %}
6969
6970 // Load Short (16 bit signed) into long
6971 instruct loadS2L(iRegLNoSp dst, memory2 mem)
6972 %{
6973 match(Set dst (ConvI2L (LoadS mem)));
6974 predicate(!needs_acquiring_load(n->in(1)));
6975
6976 ins_cost(4 * INSN_COST);
6977 format %{ "ldrsh $dst, $mem\t# short" %}
6978
6979 ins_encode(aarch64_enc_ldrsh(dst, mem));
6980
6981 ins_pipe(iload_reg_mem);
6982 %}
6983
6984 // Load Char (16 bit unsigned)
6985 instruct loadUS(iRegINoSp dst, memory2 mem)
6986 %{
6987 match(Set dst (LoadUS mem));
6988 predicate(!needs_acquiring_load(n));
6989
6990 ins_cost(4 * INSN_COST);
6991 format %{ "ldrh $dst, $mem\t# short" %}
6992
6993 ins_encode(aarch64_enc_ldrh(dst, mem));
6994
6995 ins_pipe(iload_reg_mem);
6996 %}
6997
6998 // Load Short/Char (16 bit unsigned) into long
6999 instruct loadUS2L(iRegLNoSp dst, memory2 mem)
7000 %{
7001 match(Set dst (ConvI2L (LoadUS mem)));
7002 predicate(!needs_acquiring_load(n->in(1)));
7003
7004 ins_cost(4 * INSN_COST);
7005 format %{ "ldrh $dst, $mem\t# short" %}
7006
7007 ins_encode(aarch64_enc_ldrh(dst, mem));
7008
7009 ins_pipe(iload_reg_mem);
7010 %}
7011
7012 // Load Integer (32 bit signed)
7013 instruct loadI(iRegINoSp dst, memory4 mem)
7014 %{
7015 match(Set dst (LoadI mem));
7016 predicate(!needs_acquiring_load(n));
7017
7018 ins_cost(4 * INSN_COST);
7019 format %{ "ldrw $dst, $mem\t# int" %}
7020
7021 ins_encode(aarch64_enc_ldrw(dst, mem));
7022
7023 ins_pipe(iload_reg_mem);
7024 %}
7025
7026 // Load Integer (32 bit signed) into long
7027 instruct loadI2L(iRegLNoSp dst, memory4 mem)
7028 %{
7029 match(Set dst (ConvI2L (LoadI mem)));
7030 predicate(!needs_acquiring_load(n->in(1)));
7031
7032 ins_cost(4 * INSN_COST);
7033 format %{ "ldrsw $dst, $mem\t# int" %}
7034
7035 ins_encode(aarch64_enc_ldrsw(dst, mem));
7036
7037 ins_pipe(iload_reg_mem);
7038 %}
7039
7040 // Load Integer (32 bit unsigned) into long
7041 instruct loadUI2L(iRegLNoSp dst, memory4 mem, immL_32bits mask)
7042 %{
7043 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
7044 predicate(!needs_acquiring_load(n->in(1)->in(1)->as_Load()));
7045
7046 ins_cost(4 * INSN_COST);
7047 format %{ "ldrw $dst, $mem\t# int" %}
7048
7049 ins_encode(aarch64_enc_ldrw(dst, mem));
7050
7051 ins_pipe(iload_reg_mem);
7052 %}
7053
7054 // Load Long (64 bit signed)
7055 instruct loadL(iRegLNoSp dst, memory8 mem)
7056 %{
7057 match(Set dst (LoadL mem));
7058 predicate(!needs_acquiring_load(n));
7059
7060 ins_cost(4 * INSN_COST);
7061 format %{ "ldr $dst, $mem\t# int" %}
7062
7063 ins_encode(aarch64_enc_ldr(dst, mem));
7064
7065 ins_pipe(iload_reg_mem);
7066 %}
7067
7068 // Load Range
7069 instruct loadRange(iRegINoSp dst, memory4 mem)
7070 %{
7071 match(Set dst (LoadRange mem));
7072
7073 ins_cost(4 * INSN_COST);
7074 format %{ "ldrw $dst, $mem\t# range" %}
7075
7076 ins_encode(aarch64_enc_ldrw(dst, mem));
7077
7078 ins_pipe(iload_reg_mem);
7079 %}
7080
7081 // Load Pointer
7082 instruct loadP(iRegPNoSp dst, memory8 mem)
7083 %{
7084 match(Set dst (LoadP mem));
7085 predicate(!needs_acquiring_load(n) && (n->as_Load()->barrier_data() == 0));
7086
7087 ins_cost(4 * INSN_COST);
7088 format %{ "ldr $dst, $mem\t# ptr" %}
7089
7090 ins_encode(aarch64_enc_ldr(dst, mem));
7091
7092 ins_pipe(iload_reg_mem);
7093 %}
7094
7095 // Load Compressed Pointer
7096 instruct loadN(iRegNNoSp dst, memory4 mem)
7097 %{
7098 match(Set dst (LoadN mem));
7099 predicate(!needs_acquiring_load(n));
7100
7101 ins_cost(4 * INSN_COST);
7102 format %{ "ldrw $dst, $mem\t# compressed ptr" %}
7103
7104 ins_encode(aarch64_enc_ldrw(dst, mem));
7105
7106 ins_pipe(iload_reg_mem);
7107 %}
7108
7109 // Load Klass Pointer
7110 instruct loadKlass(iRegPNoSp dst, memory8 mem)
7111 %{
7112 match(Set dst (LoadKlass mem));
7113 predicate(!needs_acquiring_load(n));
7114
7115 ins_cost(4 * INSN_COST);
7116 format %{ "ldr $dst, $mem\t# class" %}
7117
7118 ins_encode(aarch64_enc_ldr(dst, mem));
7119
7120 ins_pipe(iload_reg_mem);
7121 %}
7122
7123 // Load Narrow Klass Pointer
7124 instruct loadNKlass(iRegNNoSp dst, memory4 mem)
7125 %{
7126 match(Set dst (LoadNKlass mem));
7127 predicate(!needs_acquiring_load(n));
7128
7129 ins_cost(4 * INSN_COST);
7130 format %{ "ldrw $dst, $mem\t# compressed class ptr" %}
7131
7132 ins_encode(aarch64_enc_ldrw(dst, mem));
7133
7134 ins_pipe(iload_reg_mem);
7135 %}
7136
7137 // Load Float
7138 instruct loadF(vRegF dst, memory4 mem)
7139 %{
7140 match(Set dst (LoadF mem));
7141 predicate(!needs_acquiring_load(n));
7142
7143 ins_cost(4 * INSN_COST);
7144 format %{ "ldrs $dst, $mem\t# float" %}
7145
7146 ins_encode( aarch64_enc_ldrs(dst, mem) );
7147
7148 ins_pipe(pipe_class_memory);
7149 %}
7150
7151 // Load Double
7152 instruct loadD(vRegD dst, memory8 mem)
7153 %{
7154 match(Set dst (LoadD mem));
7155 predicate(!needs_acquiring_load(n));
7156
7157 ins_cost(4 * INSN_COST);
7158 format %{ "ldrd $dst, $mem\t# double" %}
7159
7160 ins_encode( aarch64_enc_ldrd(dst, mem) );
7161
7162 ins_pipe(pipe_class_memory);
7163 %}
7164
7165
7166 // Load Int Constant
7167 instruct loadConI(iRegINoSp dst, immI src)
7168 %{
7169 match(Set dst src);
7170
7171 ins_cost(INSN_COST);
7172 format %{ "mov $dst, $src\t# int" %}
7173
7174 ins_encode( aarch64_enc_movw_imm(dst, src) );
7175
7176 ins_pipe(ialu_imm);
7177 %}
7178
7179 // Load Long Constant
7180 instruct loadConL(iRegLNoSp dst, immL src)
7181 %{
7182 match(Set dst src);
7183
7184 ins_cost(INSN_COST);
7185 format %{ "mov $dst, $src\t# long" %}
7186
7187 ins_encode( aarch64_enc_mov_imm(dst, src) );
7188
7189 ins_pipe(ialu_imm);
7190 %}
7191
7192 // Load Pointer Constant
7193
7194 instruct loadConP(iRegPNoSp dst, immP con)
7195 %{
7196 match(Set dst con);
7197
7198 ins_cost(INSN_COST * 4);
7199 format %{
7200 "mov $dst, $con\t# ptr\n\t"
7201 %}
7202
7203 ins_encode(aarch64_enc_mov_p(dst, con));
7204
7205 ins_pipe(ialu_imm);
7206 %}
7207
7208 // Load Null Pointer Constant
7209
7210 instruct loadConP0(iRegPNoSp dst, immP0 con)
7211 %{
7212 match(Set dst con);
7213
7214 ins_cost(INSN_COST);
7215 format %{ "mov $dst, $con\t# NULL ptr" %}
7216
7217 ins_encode(aarch64_enc_mov_p0(dst, con));
7218
7219 ins_pipe(ialu_imm);
7220 %}
7221
7222 // Load Pointer Constant One
7223
7224 instruct loadConP1(iRegPNoSp dst, immP_1 con)
7225 %{
7226 match(Set dst con);
7227
7228 ins_cost(INSN_COST);
7229 format %{ "mov $dst, $con\t# NULL ptr" %}
7230
7231 ins_encode(aarch64_enc_mov_p1(dst, con));
7232
7233 ins_pipe(ialu_imm);
7234 %}
7235
7236 // Load Byte Map Base Constant
7237
7238 instruct loadByteMapBase(iRegPNoSp dst, immByteMapBase con)
7239 %{
7240 match(Set dst con);
7241
7242 ins_cost(INSN_COST);
7243 format %{ "adr $dst, $con\t# Byte Map Base" %}
7244
7245 ins_encode(aarch64_enc_mov_byte_map_base(dst, con));
7246
7247 ins_pipe(ialu_imm);
7248 %}
7249
7250 // Load Narrow Pointer Constant
7251
7252 instruct loadConN(iRegNNoSp dst, immN con)
7253 %{
7254 match(Set dst con);
7255
7256 ins_cost(INSN_COST * 4);
7257 format %{ "mov $dst, $con\t# compressed ptr" %}
7258
7259 ins_encode(aarch64_enc_mov_n(dst, con));
7260
7261 ins_pipe(ialu_imm);
7262 %}
7263
7264 // Load Narrow Null Pointer Constant
7265
7266 instruct loadConN0(iRegNNoSp dst, immN0 con)
7267 %{
7268 match(Set dst con);
7269
7270 ins_cost(INSN_COST);
7271 format %{ "mov $dst, $con\t# compressed NULL ptr" %}
7272
7273 ins_encode(aarch64_enc_mov_n0(dst, con));
7274
7275 ins_pipe(ialu_imm);
7276 %}
7277
7278 // Load Narrow Klass Constant
7279
7280 instruct loadConNKlass(iRegNNoSp dst, immNKlass con)
7281 %{
7282 match(Set dst con);
7283
7284 ins_cost(INSN_COST);
7285 format %{ "mov $dst, $con\t# compressed klass ptr" %}
7286
7287 ins_encode(aarch64_enc_mov_nk(dst, con));
7288
7289 ins_pipe(ialu_imm);
7290 %}
7291
7292 // Load Packed Float Constant
7293
7294 instruct loadConF_packed(vRegF dst, immFPacked con) %{
7295 match(Set dst con);
7296 ins_cost(INSN_COST * 4);
7297 format %{ "fmovs $dst, $con"%}
7298 ins_encode %{
7299 __ fmovs(as_FloatRegister($dst$$reg), (double)$con$$constant);
7300 %}
7301
7302 ins_pipe(fp_imm_s);
7303 %}
7304
7305 // Load Float Constant
7306
7307 instruct loadConF(vRegF dst, immF con) %{
7308 match(Set dst con);
7309
7310 ins_cost(INSN_COST * 4);
7311
7312 format %{
7313 "ldrs $dst, [$constantaddress]\t# load from constant table: float=$con\n\t"
7314 %}
7315
7316 ins_encode %{
7317 __ ldrs(as_FloatRegister($dst$$reg), $constantaddress($con));
7318 %}
7319
7320 ins_pipe(fp_load_constant_s);
7321 %}
7322
7323 // Load Packed Double Constant
7324
7325 instruct loadConD_packed(vRegD dst, immDPacked con) %{
7326 match(Set dst con);
7327 ins_cost(INSN_COST);
7328 format %{ "fmovd $dst, $con"%}
7329 ins_encode %{
7330 __ fmovd(as_FloatRegister($dst$$reg), $con$$constant);
7331 %}
7332
7333 ins_pipe(fp_imm_d);
7334 %}
7335
7336 // Load Double Constant
7337
7338 instruct loadConD(vRegD dst, immD con) %{
7339 match(Set dst con);
7340
7341 ins_cost(INSN_COST * 5);
7342 format %{
7343 "ldrd $dst, [$constantaddress]\t# load from constant table: float=$con\n\t"
7344 %}
7345
7346 ins_encode %{
7347 __ ldrd(as_FloatRegister($dst$$reg), $constantaddress($con));
7348 %}
7349
7350 ins_pipe(fp_load_constant_d);
7351 %}
7352
7353 // Store Instructions
7354
7355 // Store CMS card-mark Immediate
7356 instruct storeimmCM0(immI0 zero, memory1 mem)
7357 %{
7358 match(Set mem (StoreCM mem zero));
7359
7360 ins_cost(INSN_COST);
7361 format %{ "storestore (elided)\n\t"
7362 "strb zr, $mem\t# byte" %}
7363
7364 ins_encode(aarch64_enc_strb0(mem));
7365
7366 ins_pipe(istore_mem);
7367 %}
7368
7369 // Store CMS card-mark Immediate with intervening StoreStore
7370 // needed when using CMS with no conditional card marking
7371 instruct storeimmCM0_ordered(immI0 zero, memory1 mem)
7372 %{
7373 match(Set mem (StoreCM mem zero));
7374
7375 ins_cost(INSN_COST * 2);
7376 format %{ "storestore\n\t"
7377 "dmb ishst"
7378 "\n\tstrb zr, $mem\t# byte" %}
7379
7380 ins_encode(aarch64_enc_strb0_ordered(mem));
7381
7382 ins_pipe(istore_mem);
7383 %}
7384
7385 // Store Byte
7386 instruct storeB(iRegIorL2I src, memory1 mem)
7387 %{
7388 match(Set mem (StoreB mem src));
7389 predicate(!needs_releasing_store(n));
7390
7391 ins_cost(INSN_COST);
7392 format %{ "strb $src, $mem\t# byte" %}
7393
7394 ins_encode(aarch64_enc_strb(src, mem));
7395
7396 ins_pipe(istore_reg_mem);
7397 %}
7398
7399
7400 instruct storeimmB0(immI0 zero, memory1 mem)
7401 %{
7402 match(Set mem (StoreB mem zero));
7403 predicate(!needs_releasing_store(n));
7404
7405 ins_cost(INSN_COST);
7406 format %{ "strb rscractch2, $mem\t# byte" %}
7407
7408 ins_encode(aarch64_enc_strb0(mem));
7409
7410 ins_pipe(istore_mem);
7411 %}
7412
7413 // Store Char/Short
7414 instruct storeC(iRegIorL2I src, memory2 mem)
7415 %{
7416 match(Set mem (StoreC mem src));
7417 predicate(!needs_releasing_store(n));
7418
7419 ins_cost(INSN_COST);
7420 format %{ "strh $src, $mem\t# short" %}
7421
7422 ins_encode(aarch64_enc_strh(src, mem));
7423
7424 ins_pipe(istore_reg_mem);
7425 %}
7426
7427 instruct storeimmC0(immI0 zero, memory2 mem)
7428 %{
7429 match(Set mem (StoreC mem zero));
7430 predicate(!needs_releasing_store(n));
7431
7432 ins_cost(INSN_COST);
7433 format %{ "strh zr, $mem\t# short" %}
7434
7435 ins_encode(aarch64_enc_strh0(mem));
7436
7437 ins_pipe(istore_mem);
7438 %}
7439
7440 // Store Integer
7441
7442 instruct storeI(iRegIorL2I src, memory4 mem)
7443 %{
7444 match(Set mem(StoreI mem src));
7445 predicate(!needs_releasing_store(n));
7446
7447 ins_cost(INSN_COST);
7448 format %{ "strw $src, $mem\t# int" %}
7449
7450 ins_encode(aarch64_enc_strw(src, mem));
7451
7452 ins_pipe(istore_reg_mem);
7453 %}
7454
7455 instruct storeimmI0(immI0 zero, memory4 mem)
7456 %{
7457 match(Set mem(StoreI mem zero));
7458 predicate(!needs_releasing_store(n));
7459
7460 ins_cost(INSN_COST);
7461 format %{ "strw zr, $mem\t# int" %}
7462
7463 ins_encode(aarch64_enc_strw0(mem));
7464
7465 ins_pipe(istore_mem);
7466 %}
7467
7468 // Store Long (64 bit signed)
7469 instruct storeL(iRegL src, memory8 mem)
7470 %{
7471 match(Set mem (StoreL mem src));
7472 predicate(!needs_releasing_store(n));
7473
7474 ins_cost(INSN_COST);
7475 format %{ "str $src, $mem\t# int" %}
7476
7477 ins_encode(aarch64_enc_str(src, mem));
7478
7479 ins_pipe(istore_reg_mem);
7480 %}
7481
7482 // Store Long (64 bit signed)
7483 instruct storeimmL0(immL0 zero, memory8 mem)
7484 %{
7485 match(Set mem (StoreL mem zero));
7486 predicate(!needs_releasing_store(n));
7487
7488 ins_cost(INSN_COST);
7489 format %{ "str zr, $mem\t# int" %}
7490
7491 ins_encode(aarch64_enc_str0(mem));
7492
7493 ins_pipe(istore_mem);
7494 %}
7495
7496 // Store Pointer
7497 instruct storeP(iRegP src, memory8 mem)
7498 %{
7499 match(Set mem (StoreP mem src));
7500 predicate(!needs_releasing_store(n) && n->as_Store()->barrier_data() == 0);
7501
7502 ins_cost(INSN_COST);
7503 format %{ "str $src, $mem\t# ptr" %}
7504
7505 ins_encode(aarch64_enc_str(src, mem));
7506
7507 ins_pipe(istore_reg_mem);
7508 %}
7509
7510 // Store Pointer
7511 instruct storeimmP0(immP0 zero, memory8 mem)
7512 %{
7513 match(Set mem (StoreP mem zero));
7514 predicate(!needs_releasing_store(n) && n->as_Store()->barrier_data() == 0);
7515
7516 ins_cost(INSN_COST);
7517 format %{ "str zr, $mem\t# ptr" %}
7518
7519 ins_encode(aarch64_enc_str0(mem));
7520
7521 ins_pipe(istore_mem);
7522 %}
7523
7524 // Store Compressed Pointer
7525 instruct storeN(iRegN src, memory4 mem)
7526 %{
7527 match(Set mem (StoreN mem src));
7528 predicate(!needs_releasing_store(n));
7529
7530 ins_cost(INSN_COST);
7531 format %{ "strw $src, $mem\t# compressed ptr" %}
7532
7533 ins_encode(aarch64_enc_strw(src, mem));
7534
7535 ins_pipe(istore_reg_mem);
7536 %}
7537
7538 instruct storeImmN0(immN0 zero, memory4 mem)
7539 %{
7540 match(Set mem (StoreN mem zero));
7541 predicate(!needs_releasing_store(n));
7542
7543 ins_cost(INSN_COST);
7544 format %{ "strw zr, $mem\t# compressed ptr" %}
7545
7546 ins_encode(aarch64_enc_strw0(mem));
7547
7548 ins_pipe(istore_mem);
7549 %}
7550
7551 // Store Float
7552 instruct storeF(vRegF src, memory4 mem)
7553 %{
7554 match(Set mem (StoreF mem src));
7555 predicate(!needs_releasing_store(n));
7556
7557 ins_cost(INSN_COST);
7558 format %{ "strs $src, $mem\t# float" %}
7559
7560 ins_encode( aarch64_enc_strs(src, mem) );
7561
7562 ins_pipe(pipe_class_memory);
7563 %}
7564
7565 // TODO
7566 // implement storeImmF0 and storeFImmPacked
7567
7568 // Store Double
7569 instruct storeD(vRegD src, memory8 mem)
7570 %{
7571 match(Set mem (StoreD mem src));
7572 predicate(!needs_releasing_store(n));
7573
7574 ins_cost(INSN_COST);
7575 format %{ "strd $src, $mem\t# double" %}
7576
7577 ins_encode( aarch64_enc_strd(src, mem) );
7578
7579 ins_pipe(pipe_class_memory);
7580 %}
7581
7582 // Store Compressed Klass Pointer
7583 instruct storeNKlass(iRegN src, memory4 mem)
7584 %{
7585 predicate(!needs_releasing_store(n));
7586 match(Set mem (StoreNKlass mem src));
7587
7588 ins_cost(INSN_COST);
7589 format %{ "strw $src, $mem\t# compressed klass ptr" %}
7590
7591 ins_encode(aarch64_enc_strw(src, mem));
7592
7593 ins_pipe(istore_reg_mem);
7594 %}
7595
7596 // TODO
7597 // implement storeImmD0 and storeDImmPacked
7598
7599 // prefetch instructions
7600 // Must be safe to execute with invalid address (cannot fault).
7601
7602 instruct prefetchalloc( memory8 mem ) %{
7603 match(PrefetchAllocation mem);
7604
7605 ins_cost(INSN_COST);
7606 format %{ "prfm $mem, PSTL1KEEP\t# Prefetch into level 1 cache write keep" %}
7607
7608 ins_encode( aarch64_enc_prefetchw(mem) );
7609
7610 ins_pipe(iload_prefetch);
7611 %}
7612
7613 // ---------------- volatile loads and stores ----------------
7614
7615 // Load Byte (8 bit signed)
7616 instruct loadB_volatile(iRegINoSp dst, /* sync_memory*/indirect mem)
7617 %{
7618 match(Set dst (LoadB mem));
7619
7620 ins_cost(VOLATILE_REF_COST);
7621 format %{ "ldarsb $dst, $mem\t# byte" %}
7622
7623 ins_encode(aarch64_enc_ldarsb(dst, mem));
7624
7625 ins_pipe(pipe_serial);
7626 %}
7627
7628 // Load Byte (8 bit signed) into long
7629 instruct loadB2L_volatile(iRegLNoSp dst, /* sync_memory*/indirect mem)
7630 %{
7631 match(Set dst (ConvI2L (LoadB mem)));
7632
7633 ins_cost(VOLATILE_REF_COST);
7634 format %{ "ldarsb $dst, $mem\t# byte" %}
7635
7636 ins_encode(aarch64_enc_ldarsb(dst, mem));
7637
7638 ins_pipe(pipe_serial);
7639 %}
7640
7641 // Load Byte (8 bit unsigned)
7642 instruct loadUB_volatile(iRegINoSp dst, /* sync_memory*/indirect mem)
7643 %{
7644 match(Set dst (LoadUB mem));
7645
7646 ins_cost(VOLATILE_REF_COST);
7647 format %{ "ldarb $dst, $mem\t# byte" %}
7648
7649 ins_encode(aarch64_enc_ldarb(dst, mem));
7650
7651 ins_pipe(pipe_serial);
7652 %}
7653
7654 // Load Byte (8 bit unsigned) into long
7655 instruct loadUB2L_volatile(iRegLNoSp dst, /* sync_memory*/indirect mem)
7656 %{
7657 match(Set dst (ConvI2L (LoadUB mem)));
7658
7659 ins_cost(VOLATILE_REF_COST);
7660 format %{ "ldarb $dst, $mem\t# byte" %}
7661
7662 ins_encode(aarch64_enc_ldarb(dst, mem));
7663
7664 ins_pipe(pipe_serial);
7665 %}
7666
7667 // Load Short (16 bit signed)
7668 instruct loadS_volatile(iRegINoSp dst, /* sync_memory*/indirect mem)
7669 %{
7670 match(Set dst (LoadS mem));
7671
7672 ins_cost(VOLATILE_REF_COST);
7673 format %{ "ldarshw $dst, $mem\t# short" %}
7674
7675 ins_encode(aarch64_enc_ldarshw(dst, mem));
7676
7677 ins_pipe(pipe_serial);
7678 %}
7679
7680 instruct loadUS_volatile(iRegINoSp dst, /* sync_memory*/indirect mem)
7681 %{
7682 match(Set dst (LoadUS mem));
7683
7684 ins_cost(VOLATILE_REF_COST);
7685 format %{ "ldarhw $dst, $mem\t# short" %}
7686
7687 ins_encode(aarch64_enc_ldarhw(dst, mem));
7688
7689 ins_pipe(pipe_serial);
7690 %}
7691
7692 // Load Short/Char (16 bit unsigned) into long
7693 instruct loadUS2L_volatile(iRegLNoSp dst, /* sync_memory*/indirect mem)
7694 %{
7695 match(Set dst (ConvI2L (LoadUS mem)));
7696
7697 ins_cost(VOLATILE_REF_COST);
7698 format %{ "ldarh $dst, $mem\t# short" %}
7699
7700 ins_encode(aarch64_enc_ldarh(dst, mem));
7701
7702 ins_pipe(pipe_serial);
7703 %}
7704
7705 // Load Short/Char (16 bit signed) into long
7706 instruct loadS2L_volatile(iRegLNoSp dst, /* sync_memory*/indirect mem)
7707 %{
7708 match(Set dst (ConvI2L (LoadS mem)));
7709
7710 ins_cost(VOLATILE_REF_COST);
7711 format %{ "ldarh $dst, $mem\t# short" %}
7712
7713 ins_encode(aarch64_enc_ldarsh(dst, mem));
7714
7715 ins_pipe(pipe_serial);
7716 %}
7717
7718 // Load Integer (32 bit signed)
7719 instruct loadI_volatile(iRegINoSp dst, /* sync_memory*/indirect mem)
7720 %{
7721 match(Set dst (LoadI mem));
7722
7723 ins_cost(VOLATILE_REF_COST);
7724 format %{ "ldarw $dst, $mem\t# int" %}
7725
7726 ins_encode(aarch64_enc_ldarw(dst, mem));
7727
7728 ins_pipe(pipe_serial);
7729 %}
7730
7731 // Load Integer (32 bit unsigned) into long
7732 instruct loadUI2L_volatile(iRegLNoSp dst, /* sync_memory*/indirect mem, immL_32bits mask)
7733 %{
7734 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
7735
7736 ins_cost(VOLATILE_REF_COST);
7737 format %{ "ldarw $dst, $mem\t# int" %}
7738
7739 ins_encode(aarch64_enc_ldarw(dst, mem));
7740
7741 ins_pipe(pipe_serial);
7742 %}
7743
7744 // Load Long (64 bit signed)
7745 instruct loadL_volatile(iRegLNoSp dst, /* sync_memory*/indirect mem)
7746 %{
7747 match(Set dst (LoadL mem));
7748
7749 ins_cost(VOLATILE_REF_COST);
7750 format %{ "ldar $dst, $mem\t# int" %}
7751
7752 ins_encode(aarch64_enc_ldar(dst, mem));
7753
7754 ins_pipe(pipe_serial);
7755 %}
7756
7757 // Load Pointer
7758 instruct loadP_volatile(iRegPNoSp dst, /* sync_memory*/indirect mem)
7759 %{
7760 match(Set dst (LoadP mem));
7761 predicate(n->as_Load()->barrier_data() == 0);
7762
7763 ins_cost(VOLATILE_REF_COST);
7764 format %{ "ldar $dst, $mem\t# ptr" %}
7765
7766 ins_encode(aarch64_enc_ldar(dst, mem));
7767
7768 ins_pipe(pipe_serial);
7769 %}
7770
7771 // Load Compressed Pointer
7772 instruct loadN_volatile(iRegNNoSp dst, /* sync_memory*/indirect mem)
7773 %{
7774 match(Set dst (LoadN mem));
7775
7776 ins_cost(VOLATILE_REF_COST);
7777 format %{ "ldarw $dst, $mem\t# compressed ptr" %}
7778
7779 ins_encode(aarch64_enc_ldarw(dst, mem));
7780
7781 ins_pipe(pipe_serial);
7782 %}
7783
7784 // Load Float
7785 instruct loadF_volatile(vRegF dst, /* sync_memory*/indirect mem)
7786 %{
7787 match(Set dst (LoadF mem));
7788
7789 ins_cost(VOLATILE_REF_COST);
7790 format %{ "ldars $dst, $mem\t# float" %}
7791
7792 ins_encode( aarch64_enc_fldars(dst, mem) );
7793
7794 ins_pipe(pipe_serial);
7795 %}
7796
7797 // Load Double
7798 instruct loadD_volatile(vRegD dst, /* sync_memory*/indirect mem)
7799 %{
7800 match(Set dst (LoadD mem));
7801
7802 ins_cost(VOLATILE_REF_COST);
7803 format %{ "ldard $dst, $mem\t# double" %}
7804
7805 ins_encode( aarch64_enc_fldard(dst, mem) );
7806
7807 ins_pipe(pipe_serial);
7808 %}
7809
7810 // Store Byte
7811 instruct storeB_volatile(iRegIorL2I src, /* sync_memory*/indirect mem)
7812 %{
7813 match(Set mem (StoreB mem src));
7814
7815 ins_cost(VOLATILE_REF_COST);
7816 format %{ "stlrb $src, $mem\t# byte" %}
7817
7818 ins_encode(aarch64_enc_stlrb(src, mem));
7819
7820 ins_pipe(pipe_class_memory);
7821 %}
7822
7823 instruct storeimmB0_volatile(immI0 zero, /* sync_memory*/indirect mem)
7824 %{
7825 match(Set mem (StoreB mem zero));
7826
7827 ins_cost(VOLATILE_REF_COST);
7828 format %{ "stlrb zr, $mem\t# byte" %}
7829
7830 ins_encode(aarch64_enc_stlrb0(mem));
7831
7832 ins_pipe(pipe_class_memory);
7833 %}
7834
7835 // Store Char/Short
7836 instruct storeC_volatile(iRegIorL2I src, /* sync_memory*/indirect mem)
7837 %{
7838 match(Set mem (StoreC mem src));
7839
7840 ins_cost(VOLATILE_REF_COST);
7841 format %{ "stlrh $src, $mem\t# short" %}
7842
7843 ins_encode(aarch64_enc_stlrh(src, mem));
7844
7845 ins_pipe(pipe_class_memory);
7846 %}
7847
7848 instruct storeimmC0_volatile(immI0 zero, /* sync_memory*/indirect mem)
7849 %{
7850 match(Set mem (StoreC mem zero));
7851
7852 ins_cost(VOLATILE_REF_COST);
7853 format %{ "stlrh zr, $mem\t# short" %}
7854
7855 ins_encode(aarch64_enc_stlrh0(mem));
7856
7857 ins_pipe(pipe_class_memory);
7858 %}
7859
7860 // Store Integer
7861
7862 instruct storeI_volatile(iRegIorL2I src, /* sync_memory*/indirect mem)
7863 %{
7864 match(Set mem(StoreI mem src));
7865
7866 ins_cost(VOLATILE_REF_COST);
7867 format %{ "stlrw $src, $mem\t# int" %}
7868
7869 ins_encode(aarch64_enc_stlrw(src, mem));
7870
7871 ins_pipe(pipe_class_memory);
7872 %}
7873
7874 instruct storeimmI0_volatile(immI0 zero, /* sync_memory*/indirect mem)
7875 %{
7876 match(Set mem(StoreI mem zero));
7877
7878 ins_cost(VOLATILE_REF_COST);
7879 format %{ "stlrw zr, $mem\t# int" %}
7880
7881 ins_encode(aarch64_enc_stlrw0(mem));
7882
7883 ins_pipe(pipe_class_memory);
7884 %}
7885
7886 // Store Long (64 bit signed)
7887 instruct storeL_volatile(iRegL src, /* sync_memory*/indirect mem)
7888 %{
7889 match(Set mem (StoreL mem src));
7890
7891 ins_cost(VOLATILE_REF_COST);
7892 format %{ "stlr $src, $mem\t# int" %}
7893
7894 ins_encode(aarch64_enc_stlr(src, mem));
7895
7896 ins_pipe(pipe_class_memory);
7897 %}
7898
7899 instruct storeimmL0_volatile(immL0 zero, /* sync_memory*/indirect mem)
7900 %{
7901 match(Set mem (StoreL mem zero));
7902
7903 ins_cost(VOLATILE_REF_COST);
7904 format %{ "stlr zr, $mem\t# int" %}
7905
7906 ins_encode(aarch64_enc_stlr0(mem));
7907
7908 ins_pipe(pipe_class_memory);
7909 %}
7910
7911 // Store Pointer
7912 instruct storeP_volatile(iRegP src, /* sync_memory*/indirect mem)
7913 %{
7914 match(Set mem (StoreP mem src));
7915 predicate(n->as_Store()->barrier_data() == 0);
7916
7917 ins_cost(VOLATILE_REF_COST);
7918 format %{ "stlr $src, $mem\t# ptr" %}
7919
7920 ins_encode(aarch64_enc_stlr(src, mem));
7921
7922 ins_pipe(pipe_class_memory);
7923 %}
7924
7925 instruct storeimmP0_volatile(immP0 zero, /* sync_memory*/indirect mem)
7926 %{
7927 match(Set mem (StoreP mem zero));
7928 predicate(n->as_Store()->barrier_data() == 0);
7929
7930 ins_cost(VOLATILE_REF_COST);
7931 format %{ "stlr zr, $mem\t# ptr" %}
7932
7933 ins_encode(aarch64_enc_stlr0(mem));
7934
7935 ins_pipe(pipe_class_memory);
7936 %}
7937
7938 // Store Compressed Pointer
7939 instruct storeN_volatile(iRegN src, /* sync_memory*/indirect mem)
7940 %{
7941 match(Set mem (StoreN mem src));
7942
7943 ins_cost(VOLATILE_REF_COST);
7944 format %{ "stlrw $src, $mem\t# compressed ptr" %}
7945
7946 ins_encode(aarch64_enc_stlrw(src, mem));
7947
7948 ins_pipe(pipe_class_memory);
7949 %}
7950
7951 instruct storeimmN0_volatile(immN0 zero, /* sync_memory*/indirect mem)
7952 %{
7953 match(Set mem (StoreN mem zero));
7954
7955 ins_cost(VOLATILE_REF_COST);
7956 format %{ "stlrw zr, $mem\t# compressed ptr" %}
7957
7958 ins_encode(aarch64_enc_stlrw0(mem));
7959
7960 ins_pipe(pipe_class_memory);
7961 %}
7962
7963 // Store Float
7964 instruct storeF_volatile(vRegF src, /* sync_memory*/indirect mem)
7965 %{
7966 match(Set mem (StoreF mem src));
7967
7968 ins_cost(VOLATILE_REF_COST);
7969 format %{ "stlrs $src, $mem\t# float" %}
7970
7971 ins_encode( aarch64_enc_fstlrs(src, mem) );
7972
7973 ins_pipe(pipe_class_memory);
7974 %}
7975
7976 // TODO
7977 // implement storeImmF0 and storeFImmPacked
7978
7979 // Store Double
7980 instruct storeD_volatile(vRegD src, /* sync_memory*/indirect mem)
7981 %{
7982 match(Set mem (StoreD mem src));
7983
7984 ins_cost(VOLATILE_REF_COST);
7985 format %{ "stlrd $src, $mem\t# double" %}
7986
7987 ins_encode( aarch64_enc_fstlrd(src, mem) );
7988
7989 ins_pipe(pipe_class_memory);
7990 %}
7991
7992 // ---------------- end of volatile loads and stores ----------------
7993
7994 instruct cacheWB(indirect addr)
7995 %{
7996 predicate(VM_Version::supports_data_cache_line_flush());
7997 match(CacheWB addr);
7998
7999 ins_cost(100);
8000 format %{"cache wb $addr" %}
8001 ins_encode %{
8002 assert($addr->index_position() < 0, "should be");
8003 assert($addr$$disp == 0, "should be");
8004 __ cache_wb(Address($addr$$base$$Register, 0));
8005 %}
8006 ins_pipe(pipe_slow); // XXX
8007 %}
8008
8009 instruct cacheWBPreSync()
8010 %{
8011 predicate(VM_Version::supports_data_cache_line_flush());
8012 match(CacheWBPreSync);
8013
8014 ins_cost(100);
8015 format %{"cache wb presync" %}
8016 ins_encode %{
8017 __ cache_wbsync(true);
8018 %}
8019 ins_pipe(pipe_slow); // XXX
8020 %}
8021
8022 instruct cacheWBPostSync()
8023 %{
8024 predicate(VM_Version::supports_data_cache_line_flush());
8025 match(CacheWBPostSync);
8026
8027 ins_cost(100);
8028 format %{"cache wb postsync" %}
8029 ins_encode %{
8030 __ cache_wbsync(false);
8031 %}
8032 ins_pipe(pipe_slow); // XXX
8033 %}
8034
8035 // ============================================================================
8036 // BSWAP Instructions
8037
8038 instruct bytes_reverse_int(iRegINoSp dst, iRegIorL2I src) %{
8039 match(Set dst (ReverseBytesI src));
8040
8041 ins_cost(INSN_COST);
8042 format %{ "revw $dst, $src" %}
8043
8044 ins_encode %{
8045 __ revw(as_Register($dst$$reg), as_Register($src$$reg));
8046 %}
8047
8048 ins_pipe(ialu_reg);
8049 %}
8050
8051 instruct bytes_reverse_long(iRegLNoSp dst, iRegL src) %{
8052 match(Set dst (ReverseBytesL src));
8053
8054 ins_cost(INSN_COST);
8055 format %{ "rev $dst, $src" %}
8056
8057 ins_encode %{
8058 __ rev(as_Register($dst$$reg), as_Register($src$$reg));
8059 %}
8060
8061 ins_pipe(ialu_reg);
8062 %}
8063
8064 instruct bytes_reverse_unsigned_short(iRegINoSp dst, iRegIorL2I src) %{
8065 match(Set dst (ReverseBytesUS src));
8066
8067 ins_cost(INSN_COST);
8068 format %{ "rev16w $dst, $src" %}
8069
8070 ins_encode %{
8071 __ rev16w(as_Register($dst$$reg), as_Register($src$$reg));
8072 %}
8073
8074 ins_pipe(ialu_reg);
8075 %}
8076
8077 instruct bytes_reverse_short(iRegINoSp dst, iRegIorL2I src) %{
8078 match(Set dst (ReverseBytesS src));
8079
8080 ins_cost(INSN_COST);
8081 format %{ "rev16w $dst, $src\n\t"
8082 "sbfmw $dst, $dst, #0, #15" %}
8083
8084 ins_encode %{
8085 __ rev16w(as_Register($dst$$reg), as_Register($src$$reg));
8086 __ sbfmw(as_Register($dst$$reg), as_Register($dst$$reg), 0U, 15U);
8087 %}
8088
8089 ins_pipe(ialu_reg);
8090 %}
8091
8092 // ============================================================================
8093 // Zero Count Instructions
8094
8095 instruct countLeadingZerosI(iRegINoSp dst, iRegIorL2I src) %{
8096 match(Set dst (CountLeadingZerosI src));
8097
8098 ins_cost(INSN_COST);
8099 format %{ "clzw $dst, $src" %}
8100 ins_encode %{
8101 __ clzw(as_Register($dst$$reg), as_Register($src$$reg));
8102 %}
8103
8104 ins_pipe(ialu_reg);
8105 %}
8106
8107 instruct countLeadingZerosL(iRegINoSp dst, iRegL src) %{
8108 match(Set dst (CountLeadingZerosL src));
8109
8110 ins_cost(INSN_COST);
8111 format %{ "clz $dst, $src" %}
8112 ins_encode %{
8113 __ clz(as_Register($dst$$reg), as_Register($src$$reg));
8114 %}
8115
8116 ins_pipe(ialu_reg);
8117 %}
8118
8119 instruct countTrailingZerosI(iRegINoSp dst, iRegIorL2I src) %{
8120 match(Set dst (CountTrailingZerosI src));
8121
8122 ins_cost(INSN_COST * 2);
8123 format %{ "rbitw $dst, $src\n\t"
8124 "clzw $dst, $dst" %}
8125 ins_encode %{
8126 __ rbitw(as_Register($dst$$reg), as_Register($src$$reg));
8127 __ clzw(as_Register($dst$$reg), as_Register($dst$$reg));
8128 %}
8129
8130 ins_pipe(ialu_reg);
8131 %}
8132
8133 instruct countTrailingZerosL(iRegINoSp dst, iRegL src) %{
8134 match(Set dst (CountTrailingZerosL src));
8135
8136 ins_cost(INSN_COST * 2);
8137 format %{ "rbit $dst, $src\n\t"
8138 "clz $dst, $dst" %}
8139 ins_encode %{
8140 __ rbit(as_Register($dst$$reg), as_Register($src$$reg));
8141 __ clz(as_Register($dst$$reg), as_Register($dst$$reg));
8142 %}
8143
8144 ins_pipe(ialu_reg);
8145 %}
8146
8147 //---------- Population Count Instructions -------------------------------------
8148 //
8149
8150 instruct popCountI(iRegINoSp dst, iRegIorL2I src, vRegF tmp) %{
8151 match(Set dst (PopCountI src));
8152 effect(TEMP tmp);
8153 ins_cost(INSN_COST * 13);
8154
8155 format %{ "movw $src, $src\n\t"
8156 "mov $tmp, $src\t# vector (1D)\n\t"
8157 "cnt $tmp, $tmp\t# vector (8B)\n\t"
8158 "addv $tmp, $tmp\t# vector (8B)\n\t"
8159 "mov $dst, $tmp\t# vector (1D)" %}
8160 ins_encode %{
8161 __ movw($src$$Register, $src$$Register); // ensure top 32 bits 0
8162 __ mov($tmp$$FloatRegister, __ D, 0, $src$$Register);
8163 __ cnt($tmp$$FloatRegister, __ T8B, $tmp$$FloatRegister);
8164 __ addv($tmp$$FloatRegister, __ T8B, $tmp$$FloatRegister);
8165 __ mov($dst$$Register, $tmp$$FloatRegister, __ D, 0);
8166 %}
8167
8168 ins_pipe(pipe_class_default);
8169 %}
8170
8171 instruct popCountI_mem(iRegINoSp dst, memory4 mem, vRegF tmp) %{
8172 match(Set dst (PopCountI (LoadI mem)));
8173 effect(TEMP tmp);
8174 ins_cost(INSN_COST * 13);
8175
8176 format %{ "ldrs $tmp, $mem\n\t"
8177 "cnt $tmp, $tmp\t# vector (8B)\n\t"
8178 "addv $tmp, $tmp\t# vector (8B)\n\t"
8179 "mov $dst, $tmp\t# vector (1D)" %}
8180 ins_encode %{
8181 FloatRegister tmp_reg = as_FloatRegister($tmp$$reg);
8182 loadStore(C2_MacroAssembler(&cbuf), &MacroAssembler::ldrs, tmp_reg, $mem->opcode(),
8183 as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp, 4);
8184 __ cnt($tmp$$FloatRegister, __ T8B, $tmp$$FloatRegister);
8185 __ addv($tmp$$FloatRegister, __ T8B, $tmp$$FloatRegister);
8186 __ mov($dst$$Register, $tmp$$FloatRegister, __ D, 0);
8187 %}
8188
8189 ins_pipe(pipe_class_default);
8190 %}
8191
8192 // Note: Long.bitCount(long) returns an int.
8193 instruct popCountL(iRegINoSp dst, iRegL src, vRegD tmp) %{
8194 match(Set dst (PopCountL src));
8195 effect(TEMP tmp);
8196 ins_cost(INSN_COST * 13);
8197
8198 format %{ "mov $tmp, $src\t# vector (1D)\n\t"
8199 "cnt $tmp, $tmp\t# vector (8B)\n\t"
8200 "addv $tmp, $tmp\t# vector (8B)\n\t"
8201 "mov $dst, $tmp\t# vector (1D)" %}
8202 ins_encode %{
8203 __ mov($tmp$$FloatRegister, __ D, 0, $src$$Register);
8204 __ cnt($tmp$$FloatRegister, __ T8B, $tmp$$FloatRegister);
8205 __ addv($tmp$$FloatRegister, __ T8B, $tmp$$FloatRegister);
8206 __ mov($dst$$Register, $tmp$$FloatRegister, __ D, 0);
8207 %}
8208
8209 ins_pipe(pipe_class_default);
8210 %}
8211
8212 instruct popCountL_mem(iRegINoSp dst, memory8 mem, vRegD tmp) %{
8213 match(Set dst (PopCountL (LoadL mem)));
8214 effect(TEMP tmp);
8215 ins_cost(INSN_COST * 13);
8216
8217 format %{ "ldrd $tmp, $mem\n\t"
8218 "cnt $tmp, $tmp\t# vector (8B)\n\t"
8219 "addv $tmp, $tmp\t# vector (8B)\n\t"
8220 "mov $dst, $tmp\t# vector (1D)" %}
8221 ins_encode %{
8222 FloatRegister tmp_reg = as_FloatRegister($tmp$$reg);
8223 loadStore(C2_MacroAssembler(&cbuf), &MacroAssembler::ldrd, tmp_reg, $mem->opcode(),
8224 as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp, 8);
8225 __ cnt($tmp$$FloatRegister, __ T8B, $tmp$$FloatRegister);
8226 __ addv($tmp$$FloatRegister, __ T8B, $tmp$$FloatRegister);
8227 __ mov($dst$$Register, $tmp$$FloatRegister, __ D, 0);
8228 %}
8229
8230 ins_pipe(pipe_class_default);
8231 %}
8232
8233 // ============================================================================
8234 // MemBar Instruction
8235
8236 instruct load_fence() %{
8237 match(LoadFence);
8238 ins_cost(VOLATILE_REF_COST);
8239
8240 format %{ "load_fence" %}
8241
8242 ins_encode %{
8243 __ membar(Assembler::LoadLoad|Assembler::LoadStore);
8244 %}
8245 ins_pipe(pipe_serial);
8246 %}
8247
8248 instruct unnecessary_membar_acquire() %{
8249 predicate(unnecessary_acquire(n));
8250 match(MemBarAcquire);
8251 ins_cost(0);
8252
8253 format %{ "membar_acquire (elided)" %}
8254
8255 ins_encode %{
8256 __ block_comment("membar_acquire (elided)");
8257 %}
8258
8259 ins_pipe(pipe_class_empty);
8260 %}
8261
8262 instruct membar_acquire() %{
8263 match(MemBarAcquire);
8264 ins_cost(VOLATILE_REF_COST);
8265
8266 format %{ "membar_acquire\n\t"
8267 "dmb ish" %}
8268
8269 ins_encode %{
8270 __ block_comment("membar_acquire");
8271 __ membar(Assembler::LoadLoad|Assembler::LoadStore);
8272 %}
8273
8274 ins_pipe(pipe_serial);
8275 %}
8276
8277
8278 instruct membar_acquire_lock() %{
8279 match(MemBarAcquireLock);
8280 ins_cost(VOLATILE_REF_COST);
8281
8282 format %{ "membar_acquire_lock (elided)" %}
8283
8284 ins_encode %{
8285 __ block_comment("membar_acquire_lock (elided)");
8286 %}
8287
8288 ins_pipe(pipe_serial);
8289 %}
8290
8291 instruct store_fence() %{
8292 match(StoreFence);
8293 ins_cost(VOLATILE_REF_COST);
8294
8295 format %{ "store_fence" %}
8296
8297 ins_encode %{
8298 __ membar(Assembler::LoadStore|Assembler::StoreStore);
8299 %}
8300 ins_pipe(pipe_serial);
8301 %}
8302
8303 instruct unnecessary_membar_release() %{
8304 predicate(unnecessary_release(n));
8305 match(MemBarRelease);
8306 ins_cost(0);
8307
8308 format %{ "membar_release (elided)" %}
8309
8310 ins_encode %{
8311 __ block_comment("membar_release (elided)");
8312 %}
8313 ins_pipe(pipe_serial);
8314 %}
8315
8316 instruct membar_release() %{
8317 match(MemBarRelease);
8318 ins_cost(VOLATILE_REF_COST);
8319
8320 format %{ "membar_release\n\t"
8321 "dmb ish" %}
8322
8323 ins_encode %{
8324 __ block_comment("membar_release");
8325 __ membar(Assembler::LoadStore|Assembler::StoreStore);
8326 %}
8327 ins_pipe(pipe_serial);
8328 %}
8329
8330 instruct membar_storestore() %{
8331 match(MemBarStoreStore);
8332 match(StoreStoreFence);
8333 ins_cost(VOLATILE_REF_COST);
8334
8335 format %{ "MEMBAR-store-store" %}
8336
8337 ins_encode %{
8338 __ membar(Assembler::StoreStore);
8339 %}
8340 ins_pipe(pipe_serial);
8341 %}
8342
8343 instruct membar_release_lock() %{
8344 match(MemBarReleaseLock);
8345 ins_cost(VOLATILE_REF_COST);
8346
8347 format %{ "membar_release_lock (elided)" %}
8348
8349 ins_encode %{
8350 __ block_comment("membar_release_lock (elided)");
8351 %}
8352
8353 ins_pipe(pipe_serial);
8354 %}
8355
8356 instruct unnecessary_membar_volatile() %{
8357 predicate(unnecessary_volatile(n));
8358 match(MemBarVolatile);
8359 ins_cost(0);
8360
8361 format %{ "membar_volatile (elided)" %}
8362
8363 ins_encode %{
8364 __ block_comment("membar_volatile (elided)");
8365 %}
8366
8367 ins_pipe(pipe_serial);
8368 %}
8369
8370 instruct membar_volatile() %{
8371 match(MemBarVolatile);
8372 ins_cost(VOLATILE_REF_COST*100);
8373
8374 format %{ "membar_volatile\n\t"
8375 "dmb ish"%}
8376
8377 ins_encode %{
8378 __ block_comment("membar_volatile");
8379 __ membar(Assembler::StoreLoad);
8380 %}
8381
8382 ins_pipe(pipe_serial);
8383 %}
8384
8385 // ============================================================================
8386 // Cast/Convert Instructions
8387
8388 instruct castX2P(iRegPNoSp dst, iRegL src) %{
8389 match(Set dst (CastX2P src));
8390
8391 ins_cost(INSN_COST);
8392 format %{ "mov $dst, $src\t# long -> ptr" %}
8393
8394 ins_encode %{
8395 if ($dst$$reg != $src$$reg) {
8396 __ mov(as_Register($dst$$reg), as_Register($src$$reg));
8397 }
8398 %}
8399
8400 ins_pipe(ialu_reg);
8401 %}
8402
8403 instruct castP2X(iRegLNoSp dst, iRegP src) %{
8404 match(Set dst (CastP2X src));
8405
8406 ins_cost(INSN_COST);
8407 format %{ "mov $dst, $src\t# ptr -> long" %}
8408
8409 ins_encode %{
8410 if ($dst$$reg != $src$$reg) {
8411 __ mov(as_Register($dst$$reg), as_Register($src$$reg));
8412 }
8413 %}
8414
8415 ins_pipe(ialu_reg);
8416 %}
8417
8418 // Convert oop into int for vectors alignment masking
8419 instruct convP2I(iRegINoSp dst, iRegP src) %{
8420 match(Set dst (ConvL2I (CastP2X src)));
8421
8422 ins_cost(INSN_COST);
8423 format %{ "movw $dst, $src\t# ptr -> int" %}
8424 ins_encode %{
8425 __ movw($dst$$Register, $src$$Register);
8426 %}
8427
8428 ins_pipe(ialu_reg);
8429 %}
8430
8431 // Convert compressed oop into int for vectors alignment masking
8432 // in case of 32bit oops (heap < 4Gb).
8433 instruct convN2I(iRegINoSp dst, iRegN src)
8434 %{
8435 predicate(CompressedOops::shift() == 0);
8436 match(Set dst (ConvL2I (CastP2X (DecodeN src))));
8437
8438 ins_cost(INSN_COST);
8439 format %{ "mov dst, $src\t# compressed ptr -> int" %}
8440 ins_encode %{
8441 __ movw($dst$$Register, $src$$Register);
8442 %}
8443
8444 ins_pipe(ialu_reg);
8445 %}
8446
8447
8448 // Convert oop pointer into compressed form
8449 instruct encodeHeapOop(iRegNNoSp dst, iRegP src, rFlagsReg cr) %{
8450 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
8451 match(Set dst (EncodeP src));
8452 effect(KILL cr);
8453 ins_cost(INSN_COST * 3);
8454 format %{ "encode_heap_oop $dst, $src" %}
8455 ins_encode %{
8456 Register s = $src$$Register;
8457 Register d = $dst$$Register;
8458 __ encode_heap_oop(d, s);
8459 %}
8460 ins_pipe(ialu_reg);
8461 %}
8462
8463 instruct encodeHeapOop_not_null(iRegNNoSp dst, iRegP src, rFlagsReg cr) %{
8464 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
8465 match(Set dst (EncodeP src));
8466 ins_cost(INSN_COST * 3);
8467 format %{ "encode_heap_oop_not_null $dst, $src" %}
8468 ins_encode %{
8469 __ encode_heap_oop_not_null($dst$$Register, $src$$Register);
8470 %}
8471 ins_pipe(ialu_reg);
8472 %}
8473
8474 instruct decodeHeapOop(iRegPNoSp dst, iRegN src, rFlagsReg cr) %{
8475 predicate(n->bottom_type()->is_ptr()->ptr() != TypePtr::NotNull &&
8476 n->bottom_type()->is_ptr()->ptr() != TypePtr::Constant);
8477 match(Set dst (DecodeN src));
8478 ins_cost(INSN_COST * 3);
8479 format %{ "decode_heap_oop $dst, $src" %}
8480 ins_encode %{
8481 Register s = $src$$Register;
8482 Register d = $dst$$Register;
8483 __ decode_heap_oop(d, s);
8484 %}
8485 ins_pipe(ialu_reg);
8486 %}
8487
8488 instruct decodeHeapOop_not_null(iRegPNoSp dst, iRegN src, rFlagsReg cr) %{
8489 predicate(n->bottom_type()->is_ptr()->ptr() == TypePtr::NotNull ||
8490 n->bottom_type()->is_ptr()->ptr() == TypePtr::Constant);
8491 match(Set dst (DecodeN src));
8492 ins_cost(INSN_COST * 3);
8493 format %{ "decode_heap_oop_not_null $dst, $src" %}
8494 ins_encode %{
8495 Register s = $src$$Register;
8496 Register d = $dst$$Register;
8497 __ decode_heap_oop_not_null(d, s);
8498 %}
8499 ins_pipe(ialu_reg);
8500 %}
8501
8502 // n.b. AArch64 implementations of encode_klass_not_null and
8503 // decode_klass_not_null do not modify the flags register so, unlike
8504 // Intel, we don't kill CR as a side effect here
8505
8506 instruct encodeKlass_not_null(iRegNNoSp dst, iRegP src) %{
8507 match(Set dst (EncodePKlass src));
8508
8509 ins_cost(INSN_COST * 3);
8510 format %{ "encode_klass_not_null $dst,$src" %}
8511
8512 ins_encode %{
8513 Register src_reg = as_Register($src$$reg);
8514 Register dst_reg = as_Register($dst$$reg);
8515 __ encode_klass_not_null(dst_reg, src_reg);
8516 %}
8517
8518 ins_pipe(ialu_reg);
8519 %}
8520
8521 instruct decodeKlass_not_null(iRegPNoSp dst, iRegN src) %{
8522 match(Set dst (DecodeNKlass src));
8523
8524 ins_cost(INSN_COST * 3);
8525 format %{ "decode_klass_not_null $dst,$src" %}
8526
8527 ins_encode %{
8528 Register src_reg = as_Register($src$$reg);
8529 Register dst_reg = as_Register($dst$$reg);
8530 if (dst_reg != src_reg) {
8531 __ decode_klass_not_null(dst_reg, src_reg);
8532 } else {
8533 __ decode_klass_not_null(dst_reg);
8534 }
8535 %}
8536
8537 ins_pipe(ialu_reg);
8538 %}
8539
8540 instruct checkCastPP(iRegPNoSp dst)
8541 %{
8542 match(Set dst (CheckCastPP dst));
8543
8544 size(0);
8545 format %{ "# checkcastPP of $dst" %}
8546 ins_encode(/* empty encoding */);
8547 ins_pipe(pipe_class_empty);
8548 %}
8549
8550 instruct castPP(iRegPNoSp dst)
8551 %{
8552 match(Set dst (CastPP dst));
8553
8554 size(0);
8555 format %{ "# castPP of $dst" %}
8556 ins_encode(/* empty encoding */);
8557 ins_pipe(pipe_class_empty);
8558 %}
8559
8560 instruct castII(iRegI dst)
8561 %{
8562 match(Set dst (CastII dst));
8563
8564 size(0);
8565 format %{ "# castII of $dst" %}
8566 ins_encode(/* empty encoding */);
8567 ins_cost(0);
8568 ins_pipe(pipe_class_empty);
8569 %}
8570
8571 instruct castLL(iRegL dst)
8572 %{
8573 match(Set dst (CastLL dst));
8574
8575 size(0);
8576 format %{ "# castLL of $dst" %}
8577 ins_encode(/* empty encoding */);
8578 ins_cost(0);
8579 ins_pipe(pipe_class_empty);
8580 %}
8581
8582 instruct castFF(vRegF dst)
8583 %{
8584 match(Set dst (CastFF dst));
8585
8586 size(0);
8587 format %{ "# castFF of $dst" %}
8588 ins_encode(/* empty encoding */);
8589 ins_cost(0);
8590 ins_pipe(pipe_class_empty);
8591 %}
8592
8593 instruct castDD(vRegD dst)
8594 %{
8595 match(Set dst (CastDD dst));
8596
8597 size(0);
8598 format %{ "# castDD of $dst" %}
8599 ins_encode(/* empty encoding */);
8600 ins_cost(0);
8601 ins_pipe(pipe_class_empty);
8602 %}
8603
8604 instruct castVV(vReg dst)
8605 %{
8606 match(Set dst (CastVV dst));
8607
8608 size(0);
8609 format %{ "# castVV of $dst" %}
8610 ins_encode(/* empty encoding */);
8611 ins_cost(0);
8612 ins_pipe(pipe_class_empty);
8613 %}
8614
8615 instruct castVVMask(pRegGov dst)
8616 %{
8617 match(Set dst (CastVV dst));
8618
8619 size(0);
8620 format %{ "# castVV of $dst" %}
8621 ins_encode(/* empty encoding */);
8622 ins_cost(0);
8623 ins_pipe(pipe_class_empty);
8624 %}
8625
8626 // ============================================================================
8627 // Atomic operation instructions
8628 //
8629
8630 // standard CompareAndSwapX when we are using barriers
8631 // these have higher priority than the rules selected by a predicate
8632
8633 // XXX No flag versions for CompareAndSwap{I,L,P,N} because matcher
8634 // can't match them
8635
8636 instruct compareAndSwapB(iRegINoSp res, indirect mem, iRegINoSp oldval, iRegINoSp newval, rFlagsReg cr) %{
8637
8638 match(Set res (CompareAndSwapB mem (Binary oldval newval)));
8639 ins_cost(2 * VOLATILE_REF_COST);
8640
8641 effect(KILL cr);
8642
8643 format %{
8644 "cmpxchgb $mem, $oldval, $newval\t# (int) if $mem == $oldval then $mem <-- $newval"
8645 "cset $res, EQ\t# $res <-- (EQ ? 1 : 0)"
8646 %}
8647
8648 ins_encode(aarch64_enc_cmpxchgb(mem, oldval, newval),
8649 aarch64_enc_cset_eq(res));
8650
8651 ins_pipe(pipe_slow);
8652 %}
8653
8654 instruct compareAndSwapS(iRegINoSp res, indirect mem, iRegINoSp oldval, iRegINoSp newval, rFlagsReg cr) %{
8655
8656 match(Set res (CompareAndSwapS mem (Binary oldval newval)));
8657 ins_cost(2 * VOLATILE_REF_COST);
8658
8659 effect(KILL cr);
8660
8661 format %{
8662 "cmpxchgs $mem, $oldval, $newval\t# (int) if $mem == $oldval then $mem <-- $newval"
8663 "cset $res, EQ\t# $res <-- (EQ ? 1 : 0)"
8664 %}
8665
8666 ins_encode(aarch64_enc_cmpxchgs(mem, oldval, newval),
8667 aarch64_enc_cset_eq(res));
8668
8669 ins_pipe(pipe_slow);
8670 %}
8671
8672 instruct compareAndSwapI(iRegINoSp res, indirect mem, iRegINoSp oldval, iRegINoSp newval, rFlagsReg cr) %{
8673
8674 match(Set res (CompareAndSwapI mem (Binary oldval newval)));
8675 ins_cost(2 * VOLATILE_REF_COST);
8676
8677 effect(KILL cr);
8678
8679 format %{
8680 "cmpxchgw $mem, $oldval, $newval\t# (int) if $mem == $oldval then $mem <-- $newval"
8681 "cset $res, EQ\t# $res <-- (EQ ? 1 : 0)"
8682 %}
8683
8684 ins_encode(aarch64_enc_cmpxchgw(mem, oldval, newval),
8685 aarch64_enc_cset_eq(res));
8686
8687 ins_pipe(pipe_slow);
8688 %}
8689
8690 instruct compareAndSwapL(iRegINoSp res, indirect mem, iRegLNoSp oldval, iRegLNoSp newval, rFlagsReg cr) %{
8691
8692 match(Set res (CompareAndSwapL mem (Binary oldval newval)));
8693 ins_cost(2 * VOLATILE_REF_COST);
8694
8695 effect(KILL cr);
8696
8697 format %{
8698 "cmpxchg $mem, $oldval, $newval\t# (long) if $mem == $oldval then $mem <-- $newval"
8699 "cset $res, EQ\t# $res <-- (EQ ? 1 : 0)"
8700 %}
8701
8702 ins_encode(aarch64_enc_cmpxchg(mem, oldval, newval),
8703 aarch64_enc_cset_eq(res));
8704
8705 ins_pipe(pipe_slow);
8706 %}
8707
8708 instruct compareAndSwapP(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval, rFlagsReg cr) %{
8709
8710 match(Set res (CompareAndSwapP mem (Binary oldval newval)));
8711 predicate(n->as_LoadStore()->barrier_data() == 0);
8712 ins_cost(2 * VOLATILE_REF_COST);
8713
8714 effect(KILL cr);
8715
8716 format %{
8717 "cmpxchg $mem, $oldval, $newval\t# (ptr) if $mem == $oldval then $mem <-- $newval"
8718 "cset $res, EQ\t# $res <-- (EQ ? 1 : 0)"
8719 %}
8720
8721 ins_encode(aarch64_enc_cmpxchg(mem, oldval, newval),
8722 aarch64_enc_cset_eq(res));
8723
8724 ins_pipe(pipe_slow);
8725 %}
8726
8727 instruct compareAndSwapN(iRegINoSp res, indirect mem, iRegNNoSp oldval, iRegNNoSp newval, rFlagsReg cr) %{
8728
8729 match(Set res (CompareAndSwapN mem (Binary oldval newval)));
8730 ins_cost(2 * VOLATILE_REF_COST);
8731
8732 effect(KILL cr);
8733
8734 format %{
8735 "cmpxchgw $mem, $oldval, $newval\t# (narrow oop) if $mem == $oldval then $mem <-- $newval"
8736 "cset $res, EQ\t# $res <-- (EQ ? 1 : 0)"
8737 %}
8738
8739 ins_encode(aarch64_enc_cmpxchgw(mem, oldval, newval),
8740 aarch64_enc_cset_eq(res));
8741
8742 ins_pipe(pipe_slow);
8743 %}
8744
8745 // alternative CompareAndSwapX when we are eliding barriers
8746
8747 instruct compareAndSwapBAcq(iRegINoSp res, indirect mem, iRegINoSp oldval, iRegINoSp newval, rFlagsReg cr) %{
8748
8749 predicate(needs_acquiring_load_exclusive(n));
8750 match(Set res (CompareAndSwapB mem (Binary oldval newval)));
8751 ins_cost(VOLATILE_REF_COST);
8752
8753 effect(KILL cr);
8754
8755 format %{
8756 "cmpxchgb_acq $mem, $oldval, $newval\t# (int) if $mem == $oldval then $mem <-- $newval"
8757 "cset $res, EQ\t# $res <-- (EQ ? 1 : 0)"
8758 %}
8759
8760 ins_encode(aarch64_enc_cmpxchgb_acq(mem, oldval, newval),
8761 aarch64_enc_cset_eq(res));
8762
8763 ins_pipe(pipe_slow);
8764 %}
8765
8766 instruct compareAndSwapSAcq(iRegINoSp res, indirect mem, iRegINoSp oldval, iRegINoSp newval, rFlagsReg cr) %{
8767
8768 predicate(needs_acquiring_load_exclusive(n));
8769 match(Set res (CompareAndSwapS mem (Binary oldval newval)));
8770 ins_cost(VOLATILE_REF_COST);
8771
8772 effect(KILL cr);
8773
8774 format %{
8775 "cmpxchgs_acq $mem, $oldval, $newval\t# (int) if $mem == $oldval then $mem <-- $newval"
8776 "cset $res, EQ\t# $res <-- (EQ ? 1 : 0)"
8777 %}
8778
8779 ins_encode(aarch64_enc_cmpxchgs_acq(mem, oldval, newval),
8780 aarch64_enc_cset_eq(res));
8781
8782 ins_pipe(pipe_slow);
8783 %}
8784
8785 instruct compareAndSwapIAcq(iRegINoSp res, indirect mem, iRegINoSp oldval, iRegINoSp newval, rFlagsReg cr) %{
8786
8787 predicate(needs_acquiring_load_exclusive(n));
8788 match(Set res (CompareAndSwapI mem (Binary oldval newval)));
8789 ins_cost(VOLATILE_REF_COST);
8790
8791 effect(KILL cr);
8792
8793 format %{
8794 "cmpxchgw_acq $mem, $oldval, $newval\t# (int) if $mem == $oldval then $mem <-- $newval"
8795 "cset $res, EQ\t# $res <-- (EQ ? 1 : 0)"
8796 %}
8797
8798 ins_encode(aarch64_enc_cmpxchgw_acq(mem, oldval, newval),
8799 aarch64_enc_cset_eq(res));
8800
8801 ins_pipe(pipe_slow);
8802 %}
8803
8804 instruct compareAndSwapLAcq(iRegINoSp res, indirect mem, iRegLNoSp oldval, iRegLNoSp newval, rFlagsReg cr) %{
8805
8806 predicate(needs_acquiring_load_exclusive(n));
8807 match(Set res (CompareAndSwapL mem (Binary oldval newval)));
8808 ins_cost(VOLATILE_REF_COST);
8809
8810 effect(KILL cr);
8811
8812 format %{
8813 "cmpxchg_acq $mem, $oldval, $newval\t# (long) if $mem == $oldval then $mem <-- $newval"
8814 "cset $res, EQ\t# $res <-- (EQ ? 1 : 0)"
8815 %}
8816
8817 ins_encode(aarch64_enc_cmpxchg_acq(mem, oldval, newval),
8818 aarch64_enc_cset_eq(res));
8819
8820 ins_pipe(pipe_slow);
8821 %}
8822
8823 instruct compareAndSwapPAcq(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval, rFlagsReg cr) %{
8824
8825 predicate(needs_acquiring_load_exclusive(n) && (n->as_LoadStore()->barrier_data() == 0));
8826 match(Set res (CompareAndSwapP mem (Binary oldval newval)));
8827 ins_cost(VOLATILE_REF_COST);
8828
8829 effect(KILL cr);
8830
8831 format %{
8832 "cmpxchg_acq $mem, $oldval, $newval\t# (ptr) if $mem == $oldval then $mem <-- $newval"
8833 "cset $res, EQ\t# $res <-- (EQ ? 1 : 0)"
8834 %}
8835
8836 ins_encode(aarch64_enc_cmpxchg_acq(mem, oldval, newval),
8837 aarch64_enc_cset_eq(res));
8838
8839 ins_pipe(pipe_slow);
8840 %}
8841
8842 instruct compareAndSwapNAcq(iRegINoSp res, indirect mem, iRegNNoSp oldval, iRegNNoSp newval, rFlagsReg cr) %{
8843
8844 predicate(needs_acquiring_load_exclusive(n));
8845 match(Set res (CompareAndSwapN mem (Binary oldval newval)));
8846 ins_cost(VOLATILE_REF_COST);
8847
8848 effect(KILL cr);
8849
8850 format %{
8851 "cmpxchgw_acq $mem, $oldval, $newval\t# (narrow oop) if $mem == $oldval then $mem <-- $newval"
8852 "cset $res, EQ\t# $res <-- (EQ ? 1 : 0)"
8853 %}
8854
8855 ins_encode(aarch64_enc_cmpxchgw_acq(mem, oldval, newval),
8856 aarch64_enc_cset_eq(res));
8857
8858 ins_pipe(pipe_slow);
8859 %}
8860
8861
8862 // ---------------------------------------------------------------------
8863
8864 // BEGIN This section of the file is automatically generated. Do not edit --------------
8865
8866 // Sundry CAS operations. Note that release is always true,
8867 // regardless of the memory ordering of the CAS. This is because we
8868 // need the volatile case to be sequentially consistent but there is
8869 // no trailing StoreLoad barrier emitted by C2. Unfortunately we
8870 // can't check the type of memory ordering here, so we always emit a
8871 // STLXR.
8872
8873 // This section is generated from cas.m4
8874
8875
8876 // This pattern is generated automatically from cas.m4.
8877 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
8878 instruct compareAndExchangeB(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval, rFlagsReg cr) %{
8879 match(Set res (CompareAndExchangeB mem (Binary oldval newval)));
8880 ins_cost(2 * VOLATILE_REF_COST);
8881 effect(TEMP_DEF res, KILL cr);
8882 format %{
8883 "cmpxchgb $res = $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval"
8884 %}
8885 ins_encode %{
8886 __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register,
8887 Assembler::byte, /*acquire*/ false, /*release*/ true,
8888 /*weak*/ false, $res$$Register);
8889 __ sxtbw($res$$Register, $res$$Register);
8890 %}
8891 ins_pipe(pipe_slow);
8892 %}
8893
8894 // This pattern is generated automatically from cas.m4.
8895 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
8896 instruct compareAndExchangeS(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval, rFlagsReg cr) %{
8897 match(Set res (CompareAndExchangeS mem (Binary oldval newval)));
8898 ins_cost(2 * VOLATILE_REF_COST);
8899 effect(TEMP_DEF res, KILL cr);
8900 format %{
8901 "cmpxchgs $res = $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval"
8902 %}
8903 ins_encode %{
8904 __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register,
8905 Assembler::halfword, /*acquire*/ false, /*release*/ true,
8906 /*weak*/ false, $res$$Register);
8907 __ sxthw($res$$Register, $res$$Register);
8908 %}
8909 ins_pipe(pipe_slow);
8910 %}
8911
8912 // This pattern is generated automatically from cas.m4.
8913 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
8914 instruct compareAndExchangeI(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval, rFlagsReg cr) %{
8915 match(Set res (CompareAndExchangeI mem (Binary oldval newval)));
8916 ins_cost(2 * VOLATILE_REF_COST);
8917 effect(TEMP_DEF res, KILL cr);
8918 format %{
8919 "cmpxchgw $res = $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval"
8920 %}
8921 ins_encode %{
8922 __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register,
8923 Assembler::word, /*acquire*/ false, /*release*/ true,
8924 /*weak*/ false, $res$$Register);
8925 %}
8926 ins_pipe(pipe_slow);
8927 %}
8928
8929 // This pattern is generated automatically from cas.m4.
8930 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
8931 instruct compareAndExchangeL(iRegLNoSp res, indirect mem, iRegL oldval, iRegL newval, rFlagsReg cr) %{
8932 match(Set res (CompareAndExchangeL mem (Binary oldval newval)));
8933 ins_cost(2 * VOLATILE_REF_COST);
8934 effect(TEMP_DEF res, KILL cr);
8935 format %{
8936 "cmpxchg $res = $mem, $oldval, $newval\t# (long, weak) if $mem == $oldval then $mem <-- $newval"
8937 %}
8938 ins_encode %{
8939 __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register,
8940 Assembler::xword, /*acquire*/ false, /*release*/ true,
8941 /*weak*/ false, $res$$Register);
8942 %}
8943 ins_pipe(pipe_slow);
8944 %}
8945
8946 // This pattern is generated automatically from cas.m4.
8947 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
8948 instruct compareAndExchangeN(iRegNNoSp res, indirect mem, iRegN oldval, iRegN newval, rFlagsReg cr) %{
8949 match(Set res (CompareAndExchangeN mem (Binary oldval newval)));
8950 ins_cost(2 * VOLATILE_REF_COST);
8951 effect(TEMP_DEF res, KILL cr);
8952 format %{
8953 "cmpxchgw $res = $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval"
8954 %}
8955 ins_encode %{
8956 __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register,
8957 Assembler::word, /*acquire*/ false, /*release*/ true,
8958 /*weak*/ false, $res$$Register);
8959 %}
8960 ins_pipe(pipe_slow);
8961 %}
8962
8963 // This pattern is generated automatically from cas.m4.
8964 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
8965 instruct compareAndExchangeP(iRegPNoSp res, indirect mem, iRegP oldval, iRegP newval, rFlagsReg cr) %{
8966 predicate(n->as_LoadStore()->barrier_data() == 0);
8967 match(Set res (CompareAndExchangeP mem (Binary oldval newval)));
8968 ins_cost(2 * VOLATILE_REF_COST);
8969 effect(TEMP_DEF res, KILL cr);
8970 format %{
8971 "cmpxchg $res = $mem, $oldval, $newval\t# (ptr, weak) if $mem == $oldval then $mem <-- $newval"
8972 %}
8973 ins_encode %{
8974 __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register,
8975 Assembler::xword, /*acquire*/ false, /*release*/ true,
8976 /*weak*/ false, $res$$Register);
8977 %}
8978 ins_pipe(pipe_slow);
8979 %}
8980
8981 // This pattern is generated automatically from cas.m4.
8982 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
8983 instruct compareAndExchangeBAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval, rFlagsReg cr) %{
8984 predicate(needs_acquiring_load_exclusive(n));
8985 match(Set res (CompareAndExchangeB mem (Binary oldval newval)));
8986 ins_cost(VOLATILE_REF_COST);
8987 effect(TEMP_DEF res, KILL cr);
8988 format %{
8989 "cmpxchgb_acq $res = $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval"
8990 %}
8991 ins_encode %{
8992 __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register,
8993 Assembler::byte, /*acquire*/ true, /*release*/ true,
8994 /*weak*/ false, $res$$Register);
8995 __ sxtbw($res$$Register, $res$$Register);
8996 %}
8997 ins_pipe(pipe_slow);
8998 %}
8999
9000 // This pattern is generated automatically from cas.m4.
9001 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
9002 instruct compareAndExchangeSAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval, rFlagsReg cr) %{
9003 predicate(needs_acquiring_load_exclusive(n));
9004 match(Set res (CompareAndExchangeS mem (Binary oldval newval)));
9005 ins_cost(VOLATILE_REF_COST);
9006 effect(TEMP_DEF res, KILL cr);
9007 format %{
9008 "cmpxchgs_acq $res = $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval"
9009 %}
9010 ins_encode %{
9011 __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register,
9012 Assembler::halfword, /*acquire*/ true, /*release*/ true,
9013 /*weak*/ false, $res$$Register);
9014 __ sxthw($res$$Register, $res$$Register);
9015 %}
9016 ins_pipe(pipe_slow);
9017 %}
9018
9019 // This pattern is generated automatically from cas.m4.
9020 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
9021 instruct compareAndExchangeIAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval, rFlagsReg cr) %{
9022 predicate(needs_acquiring_load_exclusive(n));
9023 match(Set res (CompareAndExchangeI mem (Binary oldval newval)));
9024 ins_cost(VOLATILE_REF_COST);
9025 effect(TEMP_DEF res, KILL cr);
9026 format %{
9027 "cmpxchgw_acq $res = $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval"
9028 %}
9029 ins_encode %{
9030 __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register,
9031 Assembler::word, /*acquire*/ true, /*release*/ true,
9032 /*weak*/ false, $res$$Register);
9033 %}
9034 ins_pipe(pipe_slow);
9035 %}
9036
9037 // This pattern is generated automatically from cas.m4.
9038 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
9039 instruct compareAndExchangeLAcq(iRegLNoSp res, indirect mem, iRegL oldval, iRegL newval, rFlagsReg cr) %{
9040 predicate(needs_acquiring_load_exclusive(n));
9041 match(Set res (CompareAndExchangeL mem (Binary oldval newval)));
9042 ins_cost(VOLATILE_REF_COST);
9043 effect(TEMP_DEF res, KILL cr);
9044 format %{
9045 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (long, weak) if $mem == $oldval then $mem <-- $newval"
9046 %}
9047 ins_encode %{
9048 __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register,
9049 Assembler::xword, /*acquire*/ true, /*release*/ true,
9050 /*weak*/ false, $res$$Register);
9051 %}
9052 ins_pipe(pipe_slow);
9053 %}
9054
9055 // This pattern is generated automatically from cas.m4.
9056 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
9057 instruct compareAndExchangeNAcq(iRegNNoSp res, indirect mem, iRegN oldval, iRegN newval, rFlagsReg cr) %{
9058 predicate(needs_acquiring_load_exclusive(n));
9059 match(Set res (CompareAndExchangeN mem (Binary oldval newval)));
9060 ins_cost(VOLATILE_REF_COST);
9061 effect(TEMP_DEF res, KILL cr);
9062 format %{
9063 "cmpxchgw_acq $res = $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval"
9064 %}
9065 ins_encode %{
9066 __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register,
9067 Assembler::word, /*acquire*/ true, /*release*/ true,
9068 /*weak*/ false, $res$$Register);
9069 %}
9070 ins_pipe(pipe_slow);
9071 %}
9072
9073 // This pattern is generated automatically from cas.m4.
9074 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
9075 instruct compareAndExchangePAcq(iRegPNoSp res, indirect mem, iRegP oldval, iRegP newval, rFlagsReg cr) %{
9076 predicate(needs_acquiring_load_exclusive(n) && (n->as_LoadStore()->barrier_data() == 0));
9077 match(Set res (CompareAndExchangeP mem (Binary oldval newval)));
9078 ins_cost(VOLATILE_REF_COST);
9079 effect(TEMP_DEF res, KILL cr);
9080 format %{
9081 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (ptr, weak) if $mem == $oldval then $mem <-- $newval"
9082 %}
9083 ins_encode %{
9084 __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register,
9085 Assembler::xword, /*acquire*/ true, /*release*/ true,
9086 /*weak*/ false, $res$$Register);
9087 %}
9088 ins_pipe(pipe_slow);
9089 %}
9090
9091 // This pattern is generated automatically from cas.m4.
9092 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
9093 instruct weakCompareAndSwapB(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval, rFlagsReg cr) %{
9094 match(Set res (WeakCompareAndSwapB mem (Binary oldval newval)));
9095 ins_cost(2 * VOLATILE_REF_COST);
9096 effect(KILL cr);
9097 format %{
9098 "cmpxchgb $res = $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval"
9099 "csetw $res, EQ\t# $res <-- (EQ ? 1 : 0)"
9100 %}
9101 ins_encode %{
9102 __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register,
9103 Assembler::byte, /*acquire*/ false, /*release*/ true,
9104 /*weak*/ true, noreg);
9105 __ csetw($res$$Register, Assembler::EQ);
9106 %}
9107 ins_pipe(pipe_slow);
9108 %}
9109
9110 // This pattern is generated automatically from cas.m4.
9111 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
9112 instruct weakCompareAndSwapS(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval, rFlagsReg cr) %{
9113 match(Set res (WeakCompareAndSwapS mem (Binary oldval newval)));
9114 ins_cost(2 * VOLATILE_REF_COST);
9115 effect(KILL cr);
9116 format %{
9117 "cmpxchgs $res = $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval"
9118 "csetw $res, EQ\t# $res <-- (EQ ? 1 : 0)"
9119 %}
9120 ins_encode %{
9121 __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register,
9122 Assembler::halfword, /*acquire*/ false, /*release*/ true,
9123 /*weak*/ true, noreg);
9124 __ csetw($res$$Register, Assembler::EQ);
9125 %}
9126 ins_pipe(pipe_slow);
9127 %}
9128
9129 // This pattern is generated automatically from cas.m4.
9130 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
9131 instruct weakCompareAndSwapI(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval, rFlagsReg cr) %{
9132 match(Set res (WeakCompareAndSwapI mem (Binary oldval newval)));
9133 ins_cost(2 * VOLATILE_REF_COST);
9134 effect(KILL cr);
9135 format %{
9136 "cmpxchgw $res = $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval"
9137 "csetw $res, EQ\t# $res <-- (EQ ? 1 : 0)"
9138 %}
9139 ins_encode %{
9140 __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register,
9141 Assembler::word, /*acquire*/ false, /*release*/ true,
9142 /*weak*/ true, noreg);
9143 __ csetw($res$$Register, Assembler::EQ);
9144 %}
9145 ins_pipe(pipe_slow);
9146 %}
9147
9148 // This pattern is generated automatically from cas.m4.
9149 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
9150 instruct weakCompareAndSwapL(iRegINoSp res, indirect mem, iRegL oldval, iRegL newval, rFlagsReg cr) %{
9151 match(Set res (WeakCompareAndSwapL mem (Binary oldval newval)));
9152 ins_cost(2 * VOLATILE_REF_COST);
9153 effect(KILL cr);
9154 format %{
9155 "cmpxchg $res = $mem, $oldval, $newval\t# (long, weak) if $mem == $oldval then $mem <-- $newval"
9156 "csetw $res, EQ\t# $res <-- (EQ ? 1 : 0)"
9157 %}
9158 ins_encode %{
9159 __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register,
9160 Assembler::xword, /*acquire*/ false, /*release*/ true,
9161 /*weak*/ true, noreg);
9162 __ csetw($res$$Register, Assembler::EQ);
9163 %}
9164 ins_pipe(pipe_slow);
9165 %}
9166
9167 // This pattern is generated automatically from cas.m4.
9168 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
9169 instruct weakCompareAndSwapN(iRegINoSp res, indirect mem, iRegN oldval, iRegN newval, rFlagsReg cr) %{
9170 match(Set res (WeakCompareAndSwapN mem (Binary oldval newval)));
9171 ins_cost(2 * VOLATILE_REF_COST);
9172 effect(KILL cr);
9173 format %{
9174 "cmpxchgw $res = $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval"
9175 "csetw $res, EQ\t# $res <-- (EQ ? 1 : 0)"
9176 %}
9177 ins_encode %{
9178 __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register,
9179 Assembler::word, /*acquire*/ false, /*release*/ true,
9180 /*weak*/ true, noreg);
9181 __ csetw($res$$Register, Assembler::EQ);
9182 %}
9183 ins_pipe(pipe_slow);
9184 %}
9185
9186 // This pattern is generated automatically from cas.m4.
9187 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
9188 instruct weakCompareAndSwapP(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval, rFlagsReg cr) %{
9189 predicate(n->as_LoadStore()->barrier_data() == 0);
9190 match(Set res (WeakCompareAndSwapP mem (Binary oldval newval)));
9191 ins_cost(2 * VOLATILE_REF_COST);
9192 effect(KILL cr);
9193 format %{
9194 "cmpxchg $res = $mem, $oldval, $newval\t# (ptr, weak) if $mem == $oldval then $mem <-- $newval"
9195 "csetw $res, EQ\t# $res <-- (EQ ? 1 : 0)"
9196 %}
9197 ins_encode %{
9198 __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register,
9199 Assembler::xword, /*acquire*/ false, /*release*/ true,
9200 /*weak*/ true, noreg);
9201 __ csetw($res$$Register, Assembler::EQ);
9202 %}
9203 ins_pipe(pipe_slow);
9204 %}
9205
9206 // This pattern is generated automatically from cas.m4.
9207 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
9208 instruct weakCompareAndSwapBAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval, rFlagsReg cr) %{
9209 predicate(needs_acquiring_load_exclusive(n));
9210 match(Set res (WeakCompareAndSwapB mem (Binary oldval newval)));
9211 ins_cost(VOLATILE_REF_COST);
9212 effect(KILL cr);
9213 format %{
9214 "cmpxchgb_acq $res = $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval"
9215 "csetw $res, EQ\t# $res <-- (EQ ? 1 : 0)"
9216 %}
9217 ins_encode %{
9218 __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register,
9219 Assembler::byte, /*acquire*/ true, /*release*/ true,
9220 /*weak*/ true, noreg);
9221 __ csetw($res$$Register, Assembler::EQ);
9222 %}
9223 ins_pipe(pipe_slow);
9224 %}
9225
9226 // This pattern is generated automatically from cas.m4.
9227 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
9228 instruct weakCompareAndSwapSAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval, rFlagsReg cr) %{
9229 predicate(needs_acquiring_load_exclusive(n));
9230 match(Set res (WeakCompareAndSwapS mem (Binary oldval newval)));
9231 ins_cost(VOLATILE_REF_COST);
9232 effect(KILL cr);
9233 format %{
9234 "cmpxchgs_acq $res = $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval"
9235 "csetw $res, EQ\t# $res <-- (EQ ? 1 : 0)"
9236 %}
9237 ins_encode %{
9238 __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register,
9239 Assembler::halfword, /*acquire*/ true, /*release*/ true,
9240 /*weak*/ true, noreg);
9241 __ csetw($res$$Register, Assembler::EQ);
9242 %}
9243 ins_pipe(pipe_slow);
9244 %}
9245
9246 // This pattern is generated automatically from cas.m4.
9247 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
9248 instruct weakCompareAndSwapIAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval, rFlagsReg cr) %{
9249 predicate(needs_acquiring_load_exclusive(n));
9250 match(Set res (WeakCompareAndSwapI mem (Binary oldval newval)));
9251 ins_cost(VOLATILE_REF_COST);
9252 effect(KILL cr);
9253 format %{
9254 "cmpxchgw_acq $res = $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval"
9255 "csetw $res, EQ\t# $res <-- (EQ ? 1 : 0)"
9256 %}
9257 ins_encode %{
9258 __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register,
9259 Assembler::word, /*acquire*/ true, /*release*/ true,
9260 /*weak*/ true, noreg);
9261 __ csetw($res$$Register, Assembler::EQ);
9262 %}
9263 ins_pipe(pipe_slow);
9264 %}
9265
9266 // This pattern is generated automatically from cas.m4.
9267 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
9268 instruct weakCompareAndSwapLAcq(iRegINoSp res, indirect mem, iRegL oldval, iRegL newval, rFlagsReg cr) %{
9269 predicate(needs_acquiring_load_exclusive(n));
9270 match(Set res (WeakCompareAndSwapL mem (Binary oldval newval)));
9271 ins_cost(VOLATILE_REF_COST);
9272 effect(KILL cr);
9273 format %{
9274 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (long, weak) if $mem == $oldval then $mem <-- $newval"
9275 "csetw $res, EQ\t# $res <-- (EQ ? 1 : 0)"
9276 %}
9277 ins_encode %{
9278 __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register,
9279 Assembler::xword, /*acquire*/ true, /*release*/ true,
9280 /*weak*/ true, noreg);
9281 __ csetw($res$$Register, Assembler::EQ);
9282 %}
9283 ins_pipe(pipe_slow);
9284 %}
9285
9286 // This pattern is generated automatically from cas.m4.
9287 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
9288 instruct weakCompareAndSwapNAcq(iRegINoSp res, indirect mem, iRegN oldval, iRegN newval, rFlagsReg cr) %{
9289 predicate(needs_acquiring_load_exclusive(n));
9290 match(Set res (WeakCompareAndSwapN mem (Binary oldval newval)));
9291 ins_cost(VOLATILE_REF_COST);
9292 effect(KILL cr);
9293 format %{
9294 "cmpxchgw_acq $res = $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval"
9295 "csetw $res, EQ\t# $res <-- (EQ ? 1 : 0)"
9296 %}
9297 ins_encode %{
9298 __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register,
9299 Assembler::word, /*acquire*/ true, /*release*/ true,
9300 /*weak*/ true, noreg);
9301 __ csetw($res$$Register, Assembler::EQ);
9302 %}
9303 ins_pipe(pipe_slow);
9304 %}
9305
9306 // This pattern is generated automatically from cas.m4.
9307 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
9308 instruct weakCompareAndSwapPAcq(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval, rFlagsReg cr) %{
9309 predicate(needs_acquiring_load_exclusive(n) && (n->as_LoadStore()->barrier_data() == 0));
9310 match(Set res (WeakCompareAndSwapP mem (Binary oldval newval)));
9311 ins_cost(VOLATILE_REF_COST);
9312 effect(KILL cr);
9313 format %{
9314 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (ptr, weak) if $mem == $oldval then $mem <-- $newval"
9315 "csetw $res, EQ\t# $res <-- (EQ ? 1 : 0)"
9316 %}
9317 ins_encode %{
9318 __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register,
9319 Assembler::xword, /*acquire*/ true, /*release*/ true,
9320 /*weak*/ true, noreg);
9321 __ csetw($res$$Register, Assembler::EQ);
9322 %}
9323 ins_pipe(pipe_slow);
9324 %}
9325
9326 // END This section of the file is automatically generated. Do not edit --------------
9327 // ---------------------------------------------------------------------
9328
9329 instruct get_and_setI(indirect mem, iRegI newv, iRegINoSp prev) %{
9330 match(Set prev (GetAndSetI mem newv));
9331 ins_cost(2 * VOLATILE_REF_COST);
9332 format %{ "atomic_xchgw $prev, $newv, [$mem]" %}
9333 ins_encode %{
9334 __ atomic_xchgw($prev$$Register, $newv$$Register, as_Register($mem$$base));
9335 %}
9336 ins_pipe(pipe_serial);
9337 %}
9338
9339 instruct get_and_setL(indirect mem, iRegL newv, iRegLNoSp prev) %{
9340 match(Set prev (GetAndSetL mem newv));
9341 ins_cost(2 * VOLATILE_REF_COST);
9342 format %{ "atomic_xchg $prev, $newv, [$mem]" %}
9343 ins_encode %{
9344 __ atomic_xchg($prev$$Register, $newv$$Register, as_Register($mem$$base));
9345 %}
9346 ins_pipe(pipe_serial);
9347 %}
9348
9349 instruct get_and_setN(indirect mem, iRegN newv, iRegINoSp prev) %{
9350 match(Set prev (GetAndSetN mem newv));
9351 ins_cost(2 * VOLATILE_REF_COST);
9352 format %{ "atomic_xchgw $prev, $newv, [$mem]" %}
9353 ins_encode %{
9354 __ atomic_xchgw($prev$$Register, $newv$$Register, as_Register($mem$$base));
9355 %}
9356 ins_pipe(pipe_serial);
9357 %}
9358
9359 instruct get_and_setP(indirect mem, iRegP newv, iRegPNoSp prev) %{
9360 predicate(n->as_LoadStore()->barrier_data() == 0);
9361 match(Set prev (GetAndSetP mem newv));
9362 ins_cost(2 * VOLATILE_REF_COST);
9363 format %{ "atomic_xchg $prev, $newv, [$mem]" %}
9364 ins_encode %{
9365 __ atomic_xchg($prev$$Register, $newv$$Register, as_Register($mem$$base));
9366 %}
9367 ins_pipe(pipe_serial);
9368 %}
9369
9370 instruct get_and_setIAcq(indirect mem, iRegI newv, iRegINoSp prev) %{
9371 predicate(needs_acquiring_load_exclusive(n));
9372 match(Set prev (GetAndSetI mem newv));
9373 ins_cost(VOLATILE_REF_COST);
9374 format %{ "atomic_xchgw_acq $prev, $newv, [$mem]" %}
9375 ins_encode %{
9376 __ atomic_xchgalw($prev$$Register, $newv$$Register, as_Register($mem$$base));
9377 %}
9378 ins_pipe(pipe_serial);
9379 %}
9380
9381 instruct get_and_setLAcq(indirect mem, iRegL newv, iRegLNoSp prev) %{
9382 predicate(needs_acquiring_load_exclusive(n));
9383 match(Set prev (GetAndSetL mem newv));
9384 ins_cost(VOLATILE_REF_COST);
9385 format %{ "atomic_xchg_acq $prev, $newv, [$mem]" %}
9386 ins_encode %{
9387 __ atomic_xchgal($prev$$Register, $newv$$Register, as_Register($mem$$base));
9388 %}
9389 ins_pipe(pipe_serial);
9390 %}
9391
9392 instruct get_and_setNAcq(indirect mem, iRegN newv, iRegINoSp prev) %{
9393 predicate(needs_acquiring_load_exclusive(n));
9394 match(Set prev (GetAndSetN mem newv));
9395 ins_cost(VOLATILE_REF_COST);
9396 format %{ "atomic_xchgw_acq $prev, $newv, [$mem]" %}
9397 ins_encode %{
9398 __ atomic_xchgalw($prev$$Register, $newv$$Register, as_Register($mem$$base));
9399 %}
9400 ins_pipe(pipe_serial);
9401 %}
9402
9403 instruct get_and_setPAcq(indirect mem, iRegP newv, iRegPNoSp prev) %{
9404 predicate(needs_acquiring_load_exclusive(n) && (n->as_LoadStore()->barrier_data() == 0));
9405 match(Set prev (GetAndSetP mem newv));
9406 ins_cost(VOLATILE_REF_COST);
9407 format %{ "atomic_xchg_acq $prev, $newv, [$mem]" %}
9408 ins_encode %{
9409 __ atomic_xchgal($prev$$Register, $newv$$Register, as_Register($mem$$base));
9410 %}
9411 ins_pipe(pipe_serial);
9412 %}
9413
9414
9415 instruct get_and_addL(indirect mem, iRegLNoSp newval, iRegL incr) %{
9416 match(Set newval (GetAndAddL mem incr));
9417 ins_cost(2 * VOLATILE_REF_COST + 1);
9418 format %{ "get_and_addL $newval, [$mem], $incr" %}
9419 ins_encode %{
9420 __ atomic_add($newval$$Register, $incr$$Register, as_Register($mem$$base));
9421 %}
9422 ins_pipe(pipe_serial);
9423 %}
9424
9425 instruct get_and_addL_no_res(indirect mem, Universe dummy, iRegL incr) %{
9426 predicate(n->as_LoadStore()->result_not_used());
9427 match(Set dummy (GetAndAddL mem incr));
9428 ins_cost(2 * VOLATILE_REF_COST);
9429 format %{ "get_and_addL [$mem], $incr" %}
9430 ins_encode %{
9431 __ atomic_add(noreg, $incr$$Register, as_Register($mem$$base));
9432 %}
9433 ins_pipe(pipe_serial);
9434 %}
9435
9436 instruct get_and_addLi(indirect mem, iRegLNoSp newval, immLAddSub incr) %{
9437 match(Set newval (GetAndAddL mem incr));
9438 ins_cost(2 * VOLATILE_REF_COST + 1);
9439 format %{ "get_and_addL $newval, [$mem], $incr" %}
9440 ins_encode %{
9441 __ atomic_add($newval$$Register, $incr$$constant, as_Register($mem$$base));
9442 %}
9443 ins_pipe(pipe_serial);
9444 %}
9445
9446 instruct get_and_addLi_no_res(indirect mem, Universe dummy, immLAddSub incr) %{
9447 predicate(n->as_LoadStore()->result_not_used());
9448 match(Set dummy (GetAndAddL mem incr));
9449 ins_cost(2 * VOLATILE_REF_COST);
9450 format %{ "get_and_addL [$mem], $incr" %}
9451 ins_encode %{
9452 __ atomic_add(noreg, $incr$$constant, as_Register($mem$$base));
9453 %}
9454 ins_pipe(pipe_serial);
9455 %}
9456
9457 instruct get_and_addI(indirect mem, iRegINoSp newval, iRegIorL2I incr) %{
9458 match(Set newval (GetAndAddI mem incr));
9459 ins_cost(2 * VOLATILE_REF_COST + 1);
9460 format %{ "get_and_addI $newval, [$mem], $incr" %}
9461 ins_encode %{
9462 __ atomic_addw($newval$$Register, $incr$$Register, as_Register($mem$$base));
9463 %}
9464 ins_pipe(pipe_serial);
9465 %}
9466
9467 instruct get_and_addI_no_res(indirect mem, Universe dummy, iRegIorL2I incr) %{
9468 predicate(n->as_LoadStore()->result_not_used());
9469 match(Set dummy (GetAndAddI mem incr));
9470 ins_cost(2 * VOLATILE_REF_COST);
9471 format %{ "get_and_addI [$mem], $incr" %}
9472 ins_encode %{
9473 __ atomic_addw(noreg, $incr$$Register, as_Register($mem$$base));
9474 %}
9475 ins_pipe(pipe_serial);
9476 %}
9477
9478 instruct get_and_addIi(indirect mem, iRegINoSp newval, immIAddSub incr) %{
9479 match(Set newval (GetAndAddI mem incr));
9480 ins_cost(2 * VOLATILE_REF_COST + 1);
9481 format %{ "get_and_addI $newval, [$mem], $incr" %}
9482 ins_encode %{
9483 __ atomic_addw($newval$$Register, $incr$$constant, as_Register($mem$$base));
9484 %}
9485 ins_pipe(pipe_serial);
9486 %}
9487
9488 instruct get_and_addIi_no_res(indirect mem, Universe dummy, immIAddSub incr) %{
9489 predicate(n->as_LoadStore()->result_not_used());
9490 match(Set dummy (GetAndAddI mem incr));
9491 ins_cost(2 * VOLATILE_REF_COST);
9492 format %{ "get_and_addI [$mem], $incr" %}
9493 ins_encode %{
9494 __ atomic_addw(noreg, $incr$$constant, as_Register($mem$$base));
9495 %}
9496 ins_pipe(pipe_serial);
9497 %}
9498
9499 instruct get_and_addLAcq(indirect mem, iRegLNoSp newval, iRegL incr) %{
9500 predicate(needs_acquiring_load_exclusive(n));
9501 match(Set newval (GetAndAddL mem incr));
9502 ins_cost(VOLATILE_REF_COST + 1);
9503 format %{ "get_and_addL_acq $newval, [$mem], $incr" %}
9504 ins_encode %{
9505 __ atomic_addal($newval$$Register, $incr$$Register, as_Register($mem$$base));
9506 %}
9507 ins_pipe(pipe_serial);
9508 %}
9509
9510 instruct get_and_addL_no_resAcq(indirect mem, Universe dummy, iRegL incr) %{
9511 predicate(n->as_LoadStore()->result_not_used() && needs_acquiring_load_exclusive(n));
9512 match(Set dummy (GetAndAddL mem incr));
9513 ins_cost(VOLATILE_REF_COST);
9514 format %{ "get_and_addL_acq [$mem], $incr" %}
9515 ins_encode %{
9516 __ atomic_addal(noreg, $incr$$Register, as_Register($mem$$base));
9517 %}
9518 ins_pipe(pipe_serial);
9519 %}
9520
9521 instruct get_and_addLiAcq(indirect mem, iRegLNoSp newval, immLAddSub incr) %{
9522 predicate(needs_acquiring_load_exclusive(n));
9523 match(Set newval (GetAndAddL mem incr));
9524 ins_cost(VOLATILE_REF_COST + 1);
9525 format %{ "get_and_addL_acq $newval, [$mem], $incr" %}
9526 ins_encode %{
9527 __ atomic_addal($newval$$Register, $incr$$constant, as_Register($mem$$base));
9528 %}
9529 ins_pipe(pipe_serial);
9530 %}
9531
9532 instruct get_and_addLi_no_resAcq(indirect mem, Universe dummy, immLAddSub incr) %{
9533 predicate(n->as_LoadStore()->result_not_used() && needs_acquiring_load_exclusive(n));
9534 match(Set dummy (GetAndAddL mem incr));
9535 ins_cost(VOLATILE_REF_COST);
9536 format %{ "get_and_addL_acq [$mem], $incr" %}
9537 ins_encode %{
9538 __ atomic_addal(noreg, $incr$$constant, as_Register($mem$$base));
9539 %}
9540 ins_pipe(pipe_serial);
9541 %}
9542
9543 instruct get_and_addIAcq(indirect mem, iRegINoSp newval, iRegIorL2I incr) %{
9544 predicate(needs_acquiring_load_exclusive(n));
9545 match(Set newval (GetAndAddI mem incr));
9546 ins_cost(VOLATILE_REF_COST + 1);
9547 format %{ "get_and_addI_acq $newval, [$mem], $incr" %}
9548 ins_encode %{
9549 __ atomic_addalw($newval$$Register, $incr$$Register, as_Register($mem$$base));
9550 %}
9551 ins_pipe(pipe_serial);
9552 %}
9553
9554 instruct get_and_addI_no_resAcq(indirect mem, Universe dummy, iRegIorL2I incr) %{
9555 predicate(n->as_LoadStore()->result_not_used() && needs_acquiring_load_exclusive(n));
9556 match(Set dummy (GetAndAddI mem incr));
9557 ins_cost(VOLATILE_REF_COST);
9558 format %{ "get_and_addI_acq [$mem], $incr" %}
9559 ins_encode %{
9560 __ atomic_addalw(noreg, $incr$$Register, as_Register($mem$$base));
9561 %}
9562 ins_pipe(pipe_serial);
9563 %}
9564
9565 instruct get_and_addIiAcq(indirect mem, iRegINoSp newval, immIAddSub incr) %{
9566 predicate(needs_acquiring_load_exclusive(n));
9567 match(Set newval (GetAndAddI mem incr));
9568 ins_cost(VOLATILE_REF_COST + 1);
9569 format %{ "get_and_addI_acq $newval, [$mem], $incr" %}
9570 ins_encode %{
9571 __ atomic_addalw($newval$$Register, $incr$$constant, as_Register($mem$$base));
9572 %}
9573 ins_pipe(pipe_serial);
9574 %}
9575
9576 instruct get_and_addIi_no_resAcq(indirect mem, Universe dummy, immIAddSub incr) %{
9577 predicate(n->as_LoadStore()->result_not_used() && needs_acquiring_load_exclusive(n));
9578 match(Set dummy (GetAndAddI mem incr));
9579 ins_cost(VOLATILE_REF_COST);
9580 format %{ "get_and_addI_acq [$mem], $incr" %}
9581 ins_encode %{
9582 __ atomic_addalw(noreg, $incr$$constant, as_Register($mem$$base));
9583 %}
9584 ins_pipe(pipe_serial);
9585 %}
9586
9587 // Manifest a CmpU result in an integer register.
9588 // (src1 < src2) ? -1 : ((src1 > src2) ? 1 : 0)
9589 instruct cmpU3_reg_reg(iRegINoSp dst, iRegI src1, iRegI src2, rFlagsReg flags)
9590 %{
9591 match(Set dst (CmpU3 src1 src2));
9592 effect(KILL flags);
9593
9594 ins_cost(INSN_COST * 3);
9595 format %{
9596 "cmpw $src1, $src2\n\t"
9597 "csetw $dst, ne\n\t"
9598 "cnegw $dst, lo\t# CmpU3(reg)"
9599 %}
9600 ins_encode %{
9601 __ cmpw($src1$$Register, $src2$$Register);
9602 __ csetw($dst$$Register, Assembler::NE);
9603 __ cnegw($dst$$Register, $dst$$Register, Assembler::LO);
9604 %}
9605
9606 ins_pipe(pipe_class_default);
9607 %}
9608
9609 instruct cmpU3_reg_imm(iRegINoSp dst, iRegI src1, immIAddSub src2, rFlagsReg flags)
9610 %{
9611 match(Set dst (CmpU3 src1 src2));
9612 effect(KILL flags);
9613
9614 ins_cost(INSN_COST * 3);
9615 format %{
9616 "subsw zr, $src1, $src2\n\t"
9617 "csetw $dst, ne\n\t"
9618 "cnegw $dst, lo\t# CmpU3(imm)"
9619 %}
9620 ins_encode %{
9621 __ subsw(zr, $src1$$Register, (int32_t)$src2$$constant);
9622 __ csetw($dst$$Register, Assembler::NE);
9623 __ cnegw($dst$$Register, $dst$$Register, Assembler::LO);
9624 %}
9625
9626 ins_pipe(pipe_class_default);
9627 %}
9628
9629 // Manifest a CmpUL result in an integer register.
9630 // (src1 < src2) ? -1 : ((src1 > src2) ? 1 : 0)
9631 instruct cmpUL3_reg_reg(iRegINoSp dst, iRegL src1, iRegL src2, rFlagsReg flags)
9632 %{
9633 match(Set dst (CmpUL3 src1 src2));
9634 effect(KILL flags);
9635
9636 ins_cost(INSN_COST * 3);
9637 format %{
9638 "cmp $src1, $src2\n\t"
9639 "csetw $dst, ne\n\t"
9640 "cnegw $dst, lo\t# CmpUL3(reg)"
9641 %}
9642 ins_encode %{
9643 __ cmp($src1$$Register, $src2$$Register);
9644 __ csetw($dst$$Register, Assembler::NE);
9645 __ cnegw($dst$$Register, $dst$$Register, Assembler::LO);
9646 %}
9647
9648 ins_pipe(pipe_class_default);
9649 %}
9650
9651 instruct cmpUL3_reg_imm(iRegINoSp dst, iRegL src1, immLAddSub src2, rFlagsReg flags)
9652 %{
9653 match(Set dst (CmpUL3 src1 src2));
9654 effect(KILL flags);
9655
9656 ins_cost(INSN_COST * 3);
9657 format %{
9658 "subs zr, $src1, $src2\n\t"
9659 "csetw $dst, ne\n\t"
9660 "cnegw $dst, lo\t# CmpUL3(imm)"
9661 %}
9662 ins_encode %{
9663 __ subs(zr, $src1$$Register, (int32_t)$src2$$constant);
9664 __ csetw($dst$$Register, Assembler::NE);
9665 __ cnegw($dst$$Register, $dst$$Register, Assembler::LO);
9666 %}
9667
9668 ins_pipe(pipe_class_default);
9669 %}
9670
9671 // Manifest a CmpL result in an integer register.
9672 // (src1 < src2) ? -1 : ((src1 > src2) ? 1 : 0)
9673 instruct cmpL3_reg_reg(iRegINoSp dst, iRegL src1, iRegL src2, rFlagsReg flags)
9674 %{
9675 match(Set dst (CmpL3 src1 src2));
9676 effect(KILL flags);
9677
9678 ins_cost(INSN_COST * 3);
9679 format %{
9680 "cmp $src1, $src2\n\t"
9681 "csetw $dst, ne\n\t"
9682 "cnegw $dst, lt\t# CmpL3(reg)"
9683 %}
9684 ins_encode %{
9685 __ cmp($src1$$Register, $src2$$Register);
9686 __ csetw($dst$$Register, Assembler::NE);
9687 __ cnegw($dst$$Register, $dst$$Register, Assembler::LT);
9688 %}
9689
9690 ins_pipe(pipe_class_default);
9691 %}
9692
9693 instruct cmpL3_reg_imm(iRegINoSp dst, iRegL src1, immLAddSub src2, rFlagsReg flags)
9694 %{
9695 match(Set dst (CmpL3 src1 src2));
9696 effect(KILL flags);
9697
9698 ins_cost(INSN_COST * 3);
9699 format %{
9700 "subs zr, $src1, $src2\n\t"
9701 "csetw $dst, ne\n\t"
9702 "cnegw $dst, lt\t# CmpL3(imm)"
9703 %}
9704 ins_encode %{
9705 __ subs(zr, $src1$$Register, (int32_t)$src2$$constant);
9706 __ csetw($dst$$Register, Assembler::NE);
9707 __ cnegw($dst$$Register, $dst$$Register, Assembler::LT);
9708 %}
9709
9710 ins_pipe(pipe_class_default);
9711 %}
9712
9713 // ============================================================================
9714 // Conditional Move Instructions
9715
9716 // n.b. we have identical rules for both a signed compare op (cmpOp)
9717 // and an unsigned compare op (cmpOpU). it would be nice if we could
9718 // define an op class which merged both inputs and use it to type the
9719 // argument to a single rule. unfortunatelyt his fails because the
9720 // opclass does not live up to the COND_INTER interface of its
9721 // component operands. When the generic code tries to negate the
9722 // operand it ends up running the generci Machoper::negate method
9723 // which throws a ShouldNotHappen. So, we have to provide two flavours
9724 // of each rule, one for a cmpOp and a second for a cmpOpU (sigh).
9725
9726 instruct cmovI_reg_reg(cmpOp cmp, rFlagsReg cr, iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
9727 match(Set dst (CMoveI (Binary cmp cr) (Binary src1 src2)));
9728
9729 ins_cost(INSN_COST * 2);
9730 format %{ "cselw $dst, $src2, $src1 $cmp\t# signed, int" %}
9731
9732 ins_encode %{
9733 __ cselw(as_Register($dst$$reg),
9734 as_Register($src2$$reg),
9735 as_Register($src1$$reg),
9736 (Assembler::Condition)$cmp$$cmpcode);
9737 %}
9738
9739 ins_pipe(icond_reg_reg);
9740 %}
9741
9742 instruct cmovUI_reg_reg(cmpOpU cmp, rFlagsRegU cr, iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
9743 match(Set dst (CMoveI (Binary cmp cr) (Binary src1 src2)));
9744
9745 ins_cost(INSN_COST * 2);
9746 format %{ "cselw $dst, $src2, $src1 $cmp\t# unsigned, int" %}
9747
9748 ins_encode %{
9749 __ cselw(as_Register($dst$$reg),
9750 as_Register($src2$$reg),
9751 as_Register($src1$$reg),
9752 (Assembler::Condition)$cmp$$cmpcode);
9753 %}
9754
9755 ins_pipe(icond_reg_reg);
9756 %}
9757
9758 // special cases where one arg is zero
9759
9760 // n.b. this is selected in preference to the rule above because it
9761 // avoids loading constant 0 into a source register
9762
9763 // TODO
9764 // we ought only to be able to cull one of these variants as the ideal
9765 // transforms ought always to order the zero consistently (to left/right?)
9766
9767 instruct cmovI_zero_reg(cmpOp cmp, rFlagsReg cr, iRegINoSp dst, immI0 zero, iRegIorL2I src) %{
9768 match(Set dst (CMoveI (Binary cmp cr) (Binary zero src)));
9769
9770 ins_cost(INSN_COST * 2);
9771 format %{ "cselw $dst, $src, zr $cmp\t# signed, int" %}
9772
9773 ins_encode %{
9774 __ cselw(as_Register($dst$$reg),
9775 as_Register($src$$reg),
9776 zr,
9777 (Assembler::Condition)$cmp$$cmpcode);
9778 %}
9779
9780 ins_pipe(icond_reg);
9781 %}
9782
9783 instruct cmovUI_zero_reg(cmpOpU cmp, rFlagsRegU cr, iRegINoSp dst, immI0 zero, iRegIorL2I src) %{
9784 match(Set dst (CMoveI (Binary cmp cr) (Binary zero src)));
9785
9786 ins_cost(INSN_COST * 2);
9787 format %{ "cselw $dst, $src, zr $cmp\t# unsigned, int" %}
9788
9789 ins_encode %{
9790 __ cselw(as_Register($dst$$reg),
9791 as_Register($src$$reg),
9792 zr,
9793 (Assembler::Condition)$cmp$$cmpcode);
9794 %}
9795
9796 ins_pipe(icond_reg);
9797 %}
9798
9799 instruct cmovI_reg_zero(cmpOp cmp, rFlagsReg cr, iRegINoSp dst, iRegIorL2I src, immI0 zero) %{
9800 match(Set dst (CMoveI (Binary cmp cr) (Binary src zero)));
9801
9802 ins_cost(INSN_COST * 2);
9803 format %{ "cselw $dst, zr, $src $cmp\t# signed, int" %}
9804
9805 ins_encode %{
9806 __ cselw(as_Register($dst$$reg),
9807 zr,
9808 as_Register($src$$reg),
9809 (Assembler::Condition)$cmp$$cmpcode);
9810 %}
9811
9812 ins_pipe(icond_reg);
9813 %}
9814
9815 instruct cmovUI_reg_zero(cmpOpU cmp, rFlagsRegU cr, iRegINoSp dst, iRegIorL2I src, immI0 zero) %{
9816 match(Set dst (CMoveI (Binary cmp cr) (Binary src zero)));
9817
9818 ins_cost(INSN_COST * 2);
9819 format %{ "cselw $dst, zr, $src $cmp\t# unsigned, int" %}
9820
9821 ins_encode %{
9822 __ cselw(as_Register($dst$$reg),
9823 zr,
9824 as_Register($src$$reg),
9825 (Assembler::Condition)$cmp$$cmpcode);
9826 %}
9827
9828 ins_pipe(icond_reg);
9829 %}
9830
9831 // special case for creating a boolean 0 or 1
9832
9833 // n.b. this is selected in preference to the rule above because it
9834 // avoids loading constants 0 and 1 into a source register
9835
9836 instruct cmovI_reg_zero_one(cmpOp cmp, rFlagsReg cr, iRegINoSp dst, immI0 zero, immI_1 one) %{
9837 match(Set dst (CMoveI (Binary cmp cr) (Binary one zero)));
9838
9839 ins_cost(INSN_COST * 2);
9840 format %{ "csincw $dst, zr, zr $cmp\t# signed, int" %}
9841
9842 ins_encode %{
9843 // equivalently
9844 // cset(as_Register($dst$$reg),
9845 // negate_condition((Assembler::Condition)$cmp$$cmpcode));
9846 __ csincw(as_Register($dst$$reg),
9847 zr,
9848 zr,
9849 (Assembler::Condition)$cmp$$cmpcode);
9850 %}
9851
9852 ins_pipe(icond_none);
9853 %}
9854
9855 instruct cmovUI_reg_zero_one(cmpOpU cmp, rFlagsRegU cr, iRegINoSp dst, immI0 zero, immI_1 one) %{
9856 match(Set dst (CMoveI (Binary cmp cr) (Binary one zero)));
9857
9858 ins_cost(INSN_COST * 2);
9859 format %{ "csincw $dst, zr, zr $cmp\t# unsigned, int" %}
9860
9861 ins_encode %{
9862 // equivalently
9863 // cset(as_Register($dst$$reg),
9864 // negate_condition((Assembler::Condition)$cmp$$cmpcode));
9865 __ csincw(as_Register($dst$$reg),
9866 zr,
9867 zr,
9868 (Assembler::Condition)$cmp$$cmpcode);
9869 %}
9870
9871 ins_pipe(icond_none);
9872 %}
9873
9874 instruct cmovL_reg_reg(cmpOp cmp, rFlagsReg cr, iRegLNoSp dst, iRegL src1, iRegL src2) %{
9875 match(Set dst (CMoveL (Binary cmp cr) (Binary src1 src2)));
9876
9877 ins_cost(INSN_COST * 2);
9878 format %{ "csel $dst, $src2, $src1 $cmp\t# signed, long" %}
9879
9880 ins_encode %{
9881 __ csel(as_Register($dst$$reg),
9882 as_Register($src2$$reg),
9883 as_Register($src1$$reg),
9884 (Assembler::Condition)$cmp$$cmpcode);
9885 %}
9886
9887 ins_pipe(icond_reg_reg);
9888 %}
9889
9890 instruct cmovUL_reg_reg(cmpOpU cmp, rFlagsRegU cr, iRegLNoSp dst, iRegL src1, iRegL src2) %{
9891 match(Set dst (CMoveL (Binary cmp cr) (Binary src1 src2)));
9892
9893 ins_cost(INSN_COST * 2);
9894 format %{ "csel $dst, $src2, $src1 $cmp\t# unsigned, long" %}
9895
9896 ins_encode %{
9897 __ csel(as_Register($dst$$reg),
9898 as_Register($src2$$reg),
9899 as_Register($src1$$reg),
9900 (Assembler::Condition)$cmp$$cmpcode);
9901 %}
9902
9903 ins_pipe(icond_reg_reg);
9904 %}
9905
9906 // special cases where one arg is zero
9907
9908 instruct cmovL_reg_zero(cmpOp cmp, rFlagsReg cr, iRegLNoSp dst, iRegL src, immL0 zero) %{
9909 match(Set dst (CMoveL (Binary cmp cr) (Binary src zero)));
9910
9911 ins_cost(INSN_COST * 2);
9912 format %{ "csel $dst, zr, $src $cmp\t# signed, long" %}
9913
9914 ins_encode %{
9915 __ csel(as_Register($dst$$reg),
9916 zr,
9917 as_Register($src$$reg),
9918 (Assembler::Condition)$cmp$$cmpcode);
9919 %}
9920
9921 ins_pipe(icond_reg);
9922 %}
9923
9924 instruct cmovUL_reg_zero(cmpOpU cmp, rFlagsRegU cr, iRegLNoSp dst, iRegL src, immL0 zero) %{
9925 match(Set dst (CMoveL (Binary cmp cr) (Binary src zero)));
9926
9927 ins_cost(INSN_COST * 2);
9928 format %{ "csel $dst, zr, $src $cmp\t# unsigned, long" %}
9929
9930 ins_encode %{
9931 __ csel(as_Register($dst$$reg),
9932 zr,
9933 as_Register($src$$reg),
9934 (Assembler::Condition)$cmp$$cmpcode);
9935 %}
9936
9937 ins_pipe(icond_reg);
9938 %}
9939
9940 instruct cmovL_zero_reg(cmpOp cmp, rFlagsReg cr, iRegLNoSp dst, immL0 zero, iRegL src) %{
9941 match(Set dst (CMoveL (Binary cmp cr) (Binary zero src)));
9942
9943 ins_cost(INSN_COST * 2);
9944 format %{ "csel $dst, $src, zr $cmp\t# signed, long" %}
9945
9946 ins_encode %{
9947 __ csel(as_Register($dst$$reg),
9948 as_Register($src$$reg),
9949 zr,
9950 (Assembler::Condition)$cmp$$cmpcode);
9951 %}
9952
9953 ins_pipe(icond_reg);
9954 %}
9955
9956 instruct cmovUL_zero_reg(cmpOpU cmp, rFlagsRegU cr, iRegLNoSp dst, immL0 zero, iRegL src) %{
9957 match(Set dst (CMoveL (Binary cmp cr) (Binary zero src)));
9958
9959 ins_cost(INSN_COST * 2);
9960 format %{ "csel $dst, $src, zr $cmp\t# unsigned, long" %}
9961
9962 ins_encode %{
9963 __ csel(as_Register($dst$$reg),
9964 as_Register($src$$reg),
9965 zr,
9966 (Assembler::Condition)$cmp$$cmpcode);
9967 %}
9968
9969 ins_pipe(icond_reg);
9970 %}
9971
9972 instruct cmovP_reg_reg(cmpOp cmp, rFlagsReg cr, iRegPNoSp dst, iRegP src1, iRegP src2) %{
9973 match(Set dst (CMoveP (Binary cmp cr) (Binary src1 src2)));
9974
9975 ins_cost(INSN_COST * 2);
9976 format %{ "csel $dst, $src2, $src1 $cmp\t# signed, ptr" %}
9977
9978 ins_encode %{
9979 __ csel(as_Register($dst$$reg),
9980 as_Register($src2$$reg),
9981 as_Register($src1$$reg),
9982 (Assembler::Condition)$cmp$$cmpcode);
9983 %}
9984
9985 ins_pipe(icond_reg_reg);
9986 %}
9987
9988 instruct cmovUP_reg_reg(cmpOpU cmp, rFlagsRegU cr, iRegPNoSp dst, iRegP src1, iRegP src2) %{
9989 match(Set dst (CMoveP (Binary cmp cr) (Binary src1 src2)));
9990
9991 ins_cost(INSN_COST * 2);
9992 format %{ "csel $dst, $src2, $src1 $cmp\t# unsigned, ptr" %}
9993
9994 ins_encode %{
9995 __ csel(as_Register($dst$$reg),
9996 as_Register($src2$$reg),
9997 as_Register($src1$$reg),
9998 (Assembler::Condition)$cmp$$cmpcode);
9999 %}
10000
10001 ins_pipe(icond_reg_reg);
10002 %}
10003
10004 // special cases where one arg is zero
10005
10006 instruct cmovP_reg_zero(cmpOp cmp, rFlagsReg cr, iRegPNoSp dst, iRegP src, immP0 zero) %{
10007 match(Set dst (CMoveP (Binary cmp cr) (Binary src zero)));
10008
10009 ins_cost(INSN_COST * 2);
10010 format %{ "csel $dst, zr, $src $cmp\t# signed, ptr" %}
10011
10012 ins_encode %{
10013 __ csel(as_Register($dst$$reg),
10014 zr,
10015 as_Register($src$$reg),
10016 (Assembler::Condition)$cmp$$cmpcode);
10017 %}
10018
10019 ins_pipe(icond_reg);
10020 %}
10021
10022 instruct cmovUP_reg_zero(cmpOpU cmp, rFlagsRegU cr, iRegPNoSp dst, iRegP src, immP0 zero) %{
10023 match(Set dst (CMoveP (Binary cmp cr) (Binary src zero)));
10024
10025 ins_cost(INSN_COST * 2);
10026 format %{ "csel $dst, zr, $src $cmp\t# unsigned, ptr" %}
10027
10028 ins_encode %{
10029 __ csel(as_Register($dst$$reg),
10030 zr,
10031 as_Register($src$$reg),
10032 (Assembler::Condition)$cmp$$cmpcode);
10033 %}
10034
10035 ins_pipe(icond_reg);
10036 %}
10037
10038 instruct cmovP_zero_reg(cmpOp cmp, rFlagsReg cr, iRegPNoSp dst, immP0 zero, iRegP src) %{
10039 match(Set dst (CMoveP (Binary cmp cr) (Binary zero src)));
10040
10041 ins_cost(INSN_COST * 2);
10042 format %{ "csel $dst, $src, zr $cmp\t# signed, ptr" %}
10043
10044 ins_encode %{
10045 __ csel(as_Register($dst$$reg),
10046 as_Register($src$$reg),
10047 zr,
10048 (Assembler::Condition)$cmp$$cmpcode);
10049 %}
10050
10051 ins_pipe(icond_reg);
10052 %}
10053
10054 instruct cmovUP_zero_reg(cmpOpU cmp, rFlagsRegU cr, iRegPNoSp dst, immP0 zero, iRegP src) %{
10055 match(Set dst (CMoveP (Binary cmp cr) (Binary zero src)));
10056
10057 ins_cost(INSN_COST * 2);
10058 format %{ "csel $dst, $src, zr $cmp\t# unsigned, ptr" %}
10059
10060 ins_encode %{
10061 __ csel(as_Register($dst$$reg),
10062 as_Register($src$$reg),
10063 zr,
10064 (Assembler::Condition)$cmp$$cmpcode);
10065 %}
10066
10067 ins_pipe(icond_reg);
10068 %}
10069
10070 instruct cmovN_reg_reg(cmpOp cmp, rFlagsReg cr, iRegNNoSp dst, iRegN src1, iRegN src2) %{
10071 match(Set dst (CMoveN (Binary cmp cr) (Binary src1 src2)));
10072
10073 ins_cost(INSN_COST * 2);
10074 format %{ "cselw $dst, $src2, $src1 $cmp\t# signed, compressed ptr" %}
10075
10076 ins_encode %{
10077 __ cselw(as_Register($dst$$reg),
10078 as_Register($src2$$reg),
10079 as_Register($src1$$reg),
10080 (Assembler::Condition)$cmp$$cmpcode);
10081 %}
10082
10083 ins_pipe(icond_reg_reg);
10084 %}
10085
10086 instruct cmovUN_reg_reg(cmpOpU cmp, rFlagsRegU cr, iRegNNoSp dst, iRegN src1, iRegN src2) %{
10087 match(Set dst (CMoveN (Binary cmp cr) (Binary src1 src2)));
10088
10089 ins_cost(INSN_COST * 2);
10090 format %{ "cselw $dst, $src2, $src1 $cmp\t# signed, compressed ptr" %}
10091
10092 ins_encode %{
10093 __ cselw(as_Register($dst$$reg),
10094 as_Register($src2$$reg),
10095 as_Register($src1$$reg),
10096 (Assembler::Condition)$cmp$$cmpcode);
10097 %}
10098
10099 ins_pipe(icond_reg_reg);
10100 %}
10101
10102 // special cases where one arg is zero
10103
10104 instruct cmovN_reg_zero(cmpOp cmp, rFlagsReg cr, iRegNNoSp dst, iRegN src, immN0 zero) %{
10105 match(Set dst (CMoveN (Binary cmp cr) (Binary src zero)));
10106
10107 ins_cost(INSN_COST * 2);
10108 format %{ "cselw $dst, zr, $src $cmp\t# signed, compressed ptr" %}
10109
10110 ins_encode %{
10111 __ cselw(as_Register($dst$$reg),
10112 zr,
10113 as_Register($src$$reg),
10114 (Assembler::Condition)$cmp$$cmpcode);
10115 %}
10116
10117 ins_pipe(icond_reg);
10118 %}
10119
10120 instruct cmovUN_reg_zero(cmpOpU cmp, rFlagsRegU cr, iRegNNoSp dst, iRegN src, immN0 zero) %{
10121 match(Set dst (CMoveN (Binary cmp cr) (Binary src zero)));
10122
10123 ins_cost(INSN_COST * 2);
10124 format %{ "cselw $dst, zr, $src $cmp\t# unsigned, compressed ptr" %}
10125
10126 ins_encode %{
10127 __ cselw(as_Register($dst$$reg),
10128 zr,
10129 as_Register($src$$reg),
10130 (Assembler::Condition)$cmp$$cmpcode);
10131 %}
10132
10133 ins_pipe(icond_reg);
10134 %}
10135
10136 instruct cmovN_zero_reg(cmpOp cmp, rFlagsReg cr, iRegNNoSp dst, immN0 zero, iRegN src) %{
10137 match(Set dst (CMoveN (Binary cmp cr) (Binary zero src)));
10138
10139 ins_cost(INSN_COST * 2);
10140 format %{ "cselw $dst, $src, zr $cmp\t# signed, compressed ptr" %}
10141
10142 ins_encode %{
10143 __ cselw(as_Register($dst$$reg),
10144 as_Register($src$$reg),
10145 zr,
10146 (Assembler::Condition)$cmp$$cmpcode);
10147 %}
10148
10149 ins_pipe(icond_reg);
10150 %}
10151
10152 instruct cmovUN_zero_reg(cmpOpU cmp, rFlagsRegU cr, iRegNNoSp dst, immN0 zero, iRegN src) %{
10153 match(Set dst (CMoveN (Binary cmp cr) (Binary zero src)));
10154
10155 ins_cost(INSN_COST * 2);
10156 format %{ "cselw $dst, $src, zr $cmp\t# unsigned, compressed ptr" %}
10157
10158 ins_encode %{
10159 __ cselw(as_Register($dst$$reg),
10160 as_Register($src$$reg),
10161 zr,
10162 (Assembler::Condition)$cmp$$cmpcode);
10163 %}
10164
10165 ins_pipe(icond_reg);
10166 %}
10167
10168 instruct cmovF_reg(cmpOp cmp, rFlagsReg cr, vRegF dst, vRegF src1, vRegF src2)
10169 %{
10170 match(Set dst (CMoveF (Binary cmp cr) (Binary src1 src2)));
10171
10172 ins_cost(INSN_COST * 3);
10173
10174 format %{ "fcsels $dst, $src1, $src2, $cmp\t# signed cmove float\n\t" %}
10175 ins_encode %{
10176 Assembler::Condition cond = (Assembler::Condition)$cmp$$cmpcode;
10177 __ fcsels(as_FloatRegister($dst$$reg),
10178 as_FloatRegister($src2$$reg),
10179 as_FloatRegister($src1$$reg),
10180 cond);
10181 %}
10182
10183 ins_pipe(fp_cond_reg_reg_s);
10184 %}
10185
10186 instruct cmovUF_reg(cmpOpU cmp, rFlagsRegU cr, vRegF dst, vRegF src1, vRegF src2)
10187 %{
10188 match(Set dst (CMoveF (Binary cmp cr) (Binary src1 src2)));
10189
10190 ins_cost(INSN_COST * 3);
10191
10192 format %{ "fcsels $dst, $src1, $src2, $cmp\t# unsigned cmove float\n\t" %}
10193 ins_encode %{
10194 Assembler::Condition cond = (Assembler::Condition)$cmp$$cmpcode;
10195 __ fcsels(as_FloatRegister($dst$$reg),
10196 as_FloatRegister($src2$$reg),
10197 as_FloatRegister($src1$$reg),
10198 cond);
10199 %}
10200
10201 ins_pipe(fp_cond_reg_reg_s);
10202 %}
10203
10204 instruct cmovD_reg(cmpOp cmp, rFlagsReg cr, vRegD dst, vRegD src1, vRegD src2)
10205 %{
10206 match(Set dst (CMoveD (Binary cmp cr) (Binary src1 src2)));
10207
10208 ins_cost(INSN_COST * 3);
10209
10210 format %{ "fcseld $dst, $src1, $src2, $cmp\t# signed cmove float\n\t" %}
10211 ins_encode %{
10212 Assembler::Condition cond = (Assembler::Condition)$cmp$$cmpcode;
10213 __ fcseld(as_FloatRegister($dst$$reg),
10214 as_FloatRegister($src2$$reg),
10215 as_FloatRegister($src1$$reg),
10216 cond);
10217 %}
10218
10219 ins_pipe(fp_cond_reg_reg_d);
10220 %}
10221
10222 instruct cmovUD_reg(cmpOpU cmp, rFlagsRegU cr, vRegD dst, vRegD src1, vRegD src2)
10223 %{
10224 match(Set dst (CMoveD (Binary cmp cr) (Binary src1 src2)));
10225
10226 ins_cost(INSN_COST * 3);
10227
10228 format %{ "fcseld $dst, $src1, $src2, $cmp\t# unsigned cmove float\n\t" %}
10229 ins_encode %{
10230 Assembler::Condition cond = (Assembler::Condition)$cmp$$cmpcode;
10231 __ fcseld(as_FloatRegister($dst$$reg),
10232 as_FloatRegister($src2$$reg),
10233 as_FloatRegister($src1$$reg),
10234 cond);
10235 %}
10236
10237 ins_pipe(fp_cond_reg_reg_d);
10238 %}
10239
10240 // ============================================================================
10241 // Arithmetic Instructions
10242 //
10243
10244 // Integer Addition
10245
10246 // TODO
10247 // these currently employ operations which do not set CR and hence are
10248 // not flagged as killing CR but we would like to isolate the cases
10249 // where we want to set flags from those where we don't. need to work
10250 // out how to do that.
10251
10252 instruct addI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
10253 match(Set dst (AddI src1 src2));
10254
10255 ins_cost(INSN_COST);
10256 format %{ "addw $dst, $src1, $src2" %}
10257
10258 ins_encode %{
10259 __ addw(as_Register($dst$$reg),
10260 as_Register($src1$$reg),
10261 as_Register($src2$$reg));
10262 %}
10263
10264 ins_pipe(ialu_reg_reg);
10265 %}
10266
10267 instruct addI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immIAddSub src2) %{
10268 match(Set dst (AddI src1 src2));
10269
10270 ins_cost(INSN_COST);
10271 format %{ "addw $dst, $src1, $src2" %}
10272
10273 // use opcode to indicate that this is an add not a sub
10274 opcode(0x0);
10275
10276 ins_encode(aarch64_enc_addsubw_imm(dst, src1, src2));
10277
10278 ins_pipe(ialu_reg_imm);
10279 %}
10280
10281 instruct addI_reg_imm_i2l(iRegINoSp dst, iRegL src1, immIAddSub src2) %{
10282 match(Set dst (AddI (ConvL2I src1) src2));
10283
10284 ins_cost(INSN_COST);
10285 format %{ "addw $dst, $src1, $src2" %}
10286
10287 // use opcode to indicate that this is an add not a sub
10288 opcode(0x0);
10289
10290 ins_encode(aarch64_enc_addsubw_imm(dst, src1, src2));
10291
10292 ins_pipe(ialu_reg_imm);
10293 %}
10294
10295 // Pointer Addition
10296 instruct addP_reg_reg(iRegPNoSp dst, iRegP src1, iRegL src2) %{
10297 match(Set dst (AddP src1 src2));
10298
10299 ins_cost(INSN_COST);
10300 format %{ "add $dst, $src1, $src2\t# ptr" %}
10301
10302 ins_encode %{
10303 __ add(as_Register($dst$$reg),
10304 as_Register($src1$$reg),
10305 as_Register($src2$$reg));
10306 %}
10307
10308 ins_pipe(ialu_reg_reg);
10309 %}
10310
10311 instruct addP_reg_reg_ext(iRegPNoSp dst, iRegP src1, iRegIorL2I src2) %{
10312 match(Set dst (AddP src1 (ConvI2L src2)));
10313
10314 ins_cost(1.9 * INSN_COST);
10315 format %{ "add $dst, $src1, $src2, sxtw\t# ptr" %}
10316
10317 ins_encode %{
10318 __ add(as_Register($dst$$reg),
10319 as_Register($src1$$reg),
10320 as_Register($src2$$reg), ext::sxtw);
10321 %}
10322
10323 ins_pipe(ialu_reg_reg);
10324 %}
10325
10326 instruct addP_reg_reg_lsl(iRegPNoSp dst, iRegP src1, iRegL src2, immIScale scale) %{
10327 match(Set dst (AddP src1 (LShiftL src2 scale)));
10328
10329 ins_cost(1.9 * INSN_COST);
10330 format %{ "add $dst, $src1, $src2, LShiftL $scale\t# ptr" %}
10331
10332 ins_encode %{
10333 __ lea(as_Register($dst$$reg),
10334 Address(as_Register($src1$$reg), as_Register($src2$$reg),
10335 Address::lsl($scale$$constant)));
10336 %}
10337
10338 ins_pipe(ialu_reg_reg_shift);
10339 %}
10340
10341 instruct addP_reg_reg_ext_shift(iRegPNoSp dst, iRegP src1, iRegIorL2I src2, immIScale scale) %{
10342 match(Set dst (AddP src1 (LShiftL (ConvI2L src2) scale)));
10343
10344 ins_cost(1.9 * INSN_COST);
10345 format %{ "add $dst, $src1, $src2, I2L $scale\t# ptr" %}
10346
10347 ins_encode %{
10348 __ lea(as_Register($dst$$reg),
10349 Address(as_Register($src1$$reg), as_Register($src2$$reg),
10350 Address::sxtw($scale$$constant)));
10351 %}
10352
10353 ins_pipe(ialu_reg_reg_shift);
10354 %}
10355
10356 instruct lshift_ext(iRegLNoSp dst, iRegIorL2I src, immI scale, rFlagsReg cr) %{
10357 match(Set dst (LShiftL (ConvI2L src) scale));
10358
10359 ins_cost(INSN_COST);
10360 format %{ "sbfiz $dst, $src, $scale & 63, -$scale & 63\t" %}
10361
10362 ins_encode %{
10363 __ sbfiz(as_Register($dst$$reg),
10364 as_Register($src$$reg),
10365 $scale$$constant & 63, MIN2(32, (int)((-$scale$$constant) & 63)));
10366 %}
10367
10368 ins_pipe(ialu_reg_shift);
10369 %}
10370
10371 // Pointer Immediate Addition
10372 // n.b. this needs to be more expensive than using an indirect memory
10373 // operand
10374 instruct addP_reg_imm(iRegPNoSp dst, iRegP src1, immLAddSub src2) %{
10375 match(Set dst (AddP src1 src2));
10376
10377 ins_cost(INSN_COST);
10378 format %{ "add $dst, $src1, $src2\t# ptr" %}
10379
10380 // use opcode to indicate that this is an add not a sub
10381 opcode(0x0);
10382
10383 ins_encode( aarch64_enc_addsub_imm(dst, src1, src2) );
10384
10385 ins_pipe(ialu_reg_imm);
10386 %}
10387
10388 // Long Addition
10389 instruct addL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
10390
10391 match(Set dst (AddL src1 src2));
10392
10393 ins_cost(INSN_COST);
10394 format %{ "add $dst, $src1, $src2" %}
10395
10396 ins_encode %{
10397 __ add(as_Register($dst$$reg),
10398 as_Register($src1$$reg),
10399 as_Register($src2$$reg));
10400 %}
10401
10402 ins_pipe(ialu_reg_reg);
10403 %}
10404
10405 // No constant pool entries requiredLong Immediate Addition.
10406 instruct addL_reg_imm(iRegLNoSp dst, iRegL src1, immLAddSub src2) %{
10407 match(Set dst (AddL src1 src2));
10408
10409 ins_cost(INSN_COST);
10410 format %{ "add $dst, $src1, $src2" %}
10411
10412 // use opcode to indicate that this is an add not a sub
10413 opcode(0x0);
10414
10415 ins_encode( aarch64_enc_addsub_imm(dst, src1, src2) );
10416
10417 ins_pipe(ialu_reg_imm);
10418 %}
10419
10420 // Integer Subtraction
10421 instruct subI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
10422 match(Set dst (SubI src1 src2));
10423
10424 ins_cost(INSN_COST);
10425 format %{ "subw $dst, $src1, $src2" %}
10426
10427 ins_encode %{
10428 __ subw(as_Register($dst$$reg),
10429 as_Register($src1$$reg),
10430 as_Register($src2$$reg));
10431 %}
10432
10433 ins_pipe(ialu_reg_reg);
10434 %}
10435
10436 // Immediate Subtraction
10437 instruct subI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immIAddSub src2) %{
10438 match(Set dst (SubI src1 src2));
10439
10440 ins_cost(INSN_COST);
10441 format %{ "subw $dst, $src1, $src2" %}
10442
10443 // use opcode to indicate that this is a sub not an add
10444 opcode(0x1);
10445
10446 ins_encode(aarch64_enc_addsubw_imm(dst, src1, src2));
10447
10448 ins_pipe(ialu_reg_imm);
10449 %}
10450
10451 // Long Subtraction
10452 instruct subL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
10453
10454 match(Set dst (SubL src1 src2));
10455
10456 ins_cost(INSN_COST);
10457 format %{ "sub $dst, $src1, $src2" %}
10458
10459 ins_encode %{
10460 __ sub(as_Register($dst$$reg),
10461 as_Register($src1$$reg),
10462 as_Register($src2$$reg));
10463 %}
10464
10465 ins_pipe(ialu_reg_reg);
10466 %}
10467
10468 // No constant pool entries requiredLong Immediate Subtraction.
10469 instruct subL_reg_imm(iRegLNoSp dst, iRegL src1, immLAddSub src2) %{
10470 match(Set dst (SubL src1 src2));
10471
10472 ins_cost(INSN_COST);
10473 format %{ "sub$dst, $src1, $src2" %}
10474
10475 // use opcode to indicate that this is a sub not an add
10476 opcode(0x1);
10477
10478 ins_encode( aarch64_enc_addsub_imm(dst, src1, src2) );
10479
10480 ins_pipe(ialu_reg_imm);
10481 %}
10482
10483 // Integer Negation (special case for sub)
10484
10485 instruct negI_reg(iRegINoSp dst, iRegIorL2I src, immI0 zero, rFlagsReg cr) %{
10486 match(Set dst (SubI zero src));
10487
10488 ins_cost(INSN_COST);
10489 format %{ "negw $dst, $src\t# int" %}
10490
10491 ins_encode %{
10492 __ negw(as_Register($dst$$reg),
10493 as_Register($src$$reg));
10494 %}
10495
10496 ins_pipe(ialu_reg);
10497 %}
10498
10499 // Long Negation
10500
10501 instruct negL_reg(iRegLNoSp dst, iRegL src, immL0 zero, rFlagsReg cr) %{
10502 match(Set dst (SubL zero src));
10503
10504 ins_cost(INSN_COST);
10505 format %{ "neg $dst, $src\t# long" %}
10506
10507 ins_encode %{
10508 __ neg(as_Register($dst$$reg),
10509 as_Register($src$$reg));
10510 %}
10511
10512 ins_pipe(ialu_reg);
10513 %}
10514
10515 // Integer Multiply
10516
10517 instruct mulI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
10518 match(Set dst (MulI src1 src2));
10519
10520 ins_cost(INSN_COST * 3);
10521 format %{ "mulw $dst, $src1, $src2" %}
10522
10523 ins_encode %{
10524 __ mulw(as_Register($dst$$reg),
10525 as_Register($src1$$reg),
10526 as_Register($src2$$reg));
10527 %}
10528
10529 ins_pipe(imul_reg_reg);
10530 %}
10531
10532 instruct smulI(iRegLNoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
10533 match(Set dst (MulL (ConvI2L src1) (ConvI2L src2)));
10534
10535 ins_cost(INSN_COST * 3);
10536 format %{ "smull $dst, $src1, $src2" %}
10537
10538 ins_encode %{
10539 __ smull(as_Register($dst$$reg),
10540 as_Register($src1$$reg),
10541 as_Register($src2$$reg));
10542 %}
10543
10544 ins_pipe(imul_reg_reg);
10545 %}
10546
10547 // Long Multiply
10548
10549 instruct mulL(iRegLNoSp dst, iRegL src1, iRegL src2) %{
10550 match(Set dst (MulL src1 src2));
10551
10552 ins_cost(INSN_COST * 5);
10553 format %{ "mul $dst, $src1, $src2" %}
10554
10555 ins_encode %{
10556 __ mul(as_Register($dst$$reg),
10557 as_Register($src1$$reg),
10558 as_Register($src2$$reg));
10559 %}
10560
10561 ins_pipe(lmul_reg_reg);
10562 %}
10563
10564 instruct mulHiL_rReg(iRegLNoSp dst, iRegL src1, iRegL src2, rFlagsReg cr)
10565 %{
10566 match(Set dst (MulHiL src1 src2));
10567
10568 ins_cost(INSN_COST * 7);
10569 format %{ "smulh $dst, $src1, $src2\t# mulhi" %}
10570
10571 ins_encode %{
10572 __ smulh(as_Register($dst$$reg),
10573 as_Register($src1$$reg),
10574 as_Register($src2$$reg));
10575 %}
10576
10577 ins_pipe(lmul_reg_reg);
10578 %}
10579
10580 instruct umulHiL_rReg(iRegLNoSp dst, iRegL src1, iRegL src2, rFlagsReg cr)
10581 %{
10582 match(Set dst (UMulHiL src1 src2));
10583
10584 ins_cost(INSN_COST * 7);
10585 format %{ "umulh $dst, $src1, $src2\t# umulhi" %}
10586
10587 ins_encode %{
10588 __ umulh(as_Register($dst$$reg),
10589 as_Register($src1$$reg),
10590 as_Register($src2$$reg));
10591 %}
10592
10593 ins_pipe(lmul_reg_reg);
10594 %}
10595
10596 // Combined Integer Multiply & Add/Sub
10597
10598 instruct maddI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, iRegIorL2I src3) %{
10599 match(Set dst (AddI src3 (MulI src1 src2)));
10600
10601 ins_cost(INSN_COST * 3);
10602 format %{ "madd $dst, $src1, $src2, $src3" %}
10603
10604 ins_encode %{
10605 __ maddw(as_Register($dst$$reg),
10606 as_Register($src1$$reg),
10607 as_Register($src2$$reg),
10608 as_Register($src3$$reg));
10609 %}
10610
10611 ins_pipe(imac_reg_reg);
10612 %}
10613
10614 instruct msubI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, iRegIorL2I src3) %{
10615 match(Set dst (SubI src3 (MulI src1 src2)));
10616
10617 ins_cost(INSN_COST * 3);
10618 format %{ "msub $dst, $src1, $src2, $src3" %}
10619
10620 ins_encode %{
10621 __ msubw(as_Register($dst$$reg),
10622 as_Register($src1$$reg),
10623 as_Register($src2$$reg),
10624 as_Register($src3$$reg));
10625 %}
10626
10627 ins_pipe(imac_reg_reg);
10628 %}
10629
10630 // Combined Integer Multiply & Neg
10631
10632 instruct mnegI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI0 zero) %{
10633 match(Set dst (MulI (SubI zero src1) src2));
10634
10635 ins_cost(INSN_COST * 3);
10636 format %{ "mneg $dst, $src1, $src2" %}
10637
10638 ins_encode %{
10639 __ mnegw(as_Register($dst$$reg),
10640 as_Register($src1$$reg),
10641 as_Register($src2$$reg));
10642 %}
10643
10644 ins_pipe(imac_reg_reg);
10645 %}
10646
10647 // Combined Long Multiply & Add/Sub
10648
10649 instruct maddL(iRegLNoSp dst, iRegL src1, iRegL src2, iRegL src3) %{
10650 match(Set dst (AddL src3 (MulL src1 src2)));
10651
10652 ins_cost(INSN_COST * 5);
10653 format %{ "madd $dst, $src1, $src2, $src3" %}
10654
10655 ins_encode %{
10656 __ madd(as_Register($dst$$reg),
10657 as_Register($src1$$reg),
10658 as_Register($src2$$reg),
10659 as_Register($src3$$reg));
10660 %}
10661
10662 ins_pipe(lmac_reg_reg);
10663 %}
10664
10665 instruct msubL(iRegLNoSp dst, iRegL src1, iRegL src2, iRegL src3) %{
10666 match(Set dst (SubL src3 (MulL src1 src2)));
10667
10668 ins_cost(INSN_COST * 5);
10669 format %{ "msub $dst, $src1, $src2, $src3" %}
10670
10671 ins_encode %{
10672 __ msub(as_Register($dst$$reg),
10673 as_Register($src1$$reg),
10674 as_Register($src2$$reg),
10675 as_Register($src3$$reg));
10676 %}
10677
10678 ins_pipe(lmac_reg_reg);
10679 %}
10680
10681 // Combined Long Multiply & Neg
10682
10683 instruct mnegL(iRegLNoSp dst, iRegL src1, iRegL src2, immL0 zero) %{
10684 match(Set dst (MulL (SubL zero src1) src2));
10685
10686 ins_cost(INSN_COST * 5);
10687 format %{ "mneg $dst, $src1, $src2" %}
10688
10689 ins_encode %{
10690 __ mneg(as_Register($dst$$reg),
10691 as_Register($src1$$reg),
10692 as_Register($src2$$reg));
10693 %}
10694
10695 ins_pipe(lmac_reg_reg);
10696 %}
10697
10698 // Combine Integer Signed Multiply & Add/Sub/Neg Long
10699
10700 instruct smaddL(iRegLNoSp dst, iRegIorL2I src1, iRegIorL2I src2, iRegLNoSp src3) %{
10701 match(Set dst (AddL src3 (MulL (ConvI2L src1) (ConvI2L src2))));
10702
10703 ins_cost(INSN_COST * 3);
10704 format %{ "smaddl $dst, $src1, $src2, $src3" %}
10705
10706 ins_encode %{
10707 __ smaddl(as_Register($dst$$reg),
10708 as_Register($src1$$reg),
10709 as_Register($src2$$reg),
10710 as_Register($src3$$reg));
10711 %}
10712
10713 ins_pipe(imac_reg_reg);
10714 %}
10715
10716 instruct smsubL(iRegLNoSp dst, iRegIorL2I src1, iRegIorL2I src2, iRegLNoSp src3) %{
10717 match(Set dst (SubL src3 (MulL (ConvI2L src1) (ConvI2L src2))));
10718
10719 ins_cost(INSN_COST * 3);
10720 format %{ "smsubl $dst, $src1, $src2, $src3" %}
10721
10722 ins_encode %{
10723 __ smsubl(as_Register($dst$$reg),
10724 as_Register($src1$$reg),
10725 as_Register($src2$$reg),
10726 as_Register($src3$$reg));
10727 %}
10728
10729 ins_pipe(imac_reg_reg);
10730 %}
10731
10732 instruct smnegL(iRegLNoSp dst, iRegIorL2I src1, iRegIorL2I src2, immL0 zero) %{
10733 match(Set dst (MulL (SubL zero (ConvI2L src1)) (ConvI2L src2)));
10734
10735 ins_cost(INSN_COST * 3);
10736 format %{ "smnegl $dst, $src1, $src2" %}
10737
10738 ins_encode %{
10739 __ smnegl(as_Register($dst$$reg),
10740 as_Register($src1$$reg),
10741 as_Register($src2$$reg));
10742 %}
10743
10744 ins_pipe(imac_reg_reg);
10745 %}
10746
10747 // Combined Multiply-Add Shorts into Integer (dst = src1 * src2 + src3 * src4)
10748
10749 instruct muladdS2I(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, iRegIorL2I src3, iRegIorL2I src4) %{
10750 match(Set dst (MulAddS2I (Binary src1 src2) (Binary src3 src4)));
10751
10752 ins_cost(INSN_COST * 5);
10753 format %{ "mulw rscratch1, $src1, $src2\n\t"
10754 "maddw $dst, $src3, $src4, rscratch1" %}
10755
10756 ins_encode %{
10757 __ mulw(rscratch1, as_Register($src1$$reg), as_Register($src2$$reg));
10758 __ maddw(as_Register($dst$$reg), as_Register($src3$$reg), as_Register($src4$$reg), rscratch1); %}
10759
10760 ins_pipe(imac_reg_reg);
10761 %}
10762
10763 // Integer Divide
10764
10765 instruct divI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
10766 match(Set dst (DivI src1 src2));
10767
10768 ins_cost(INSN_COST * 19);
10769 format %{ "sdivw $dst, $src1, $src2" %}
10770
10771 ins_encode(aarch64_enc_divw(dst, src1, src2));
10772 ins_pipe(idiv_reg_reg);
10773 %}
10774
10775 // Long Divide
10776
10777 instruct divL(iRegLNoSp dst, iRegL src1, iRegL src2) %{
10778 match(Set dst (DivL src1 src2));
10779
10780 ins_cost(INSN_COST * 35);
10781 format %{ "sdiv $dst, $src1, $src2" %}
10782
10783 ins_encode(aarch64_enc_div(dst, src1, src2));
10784 ins_pipe(ldiv_reg_reg);
10785 %}
10786
10787 // Integer Remainder
10788
10789 instruct modI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
10790 match(Set dst (ModI src1 src2));
10791
10792 ins_cost(INSN_COST * 22);
10793 format %{ "sdivw rscratch1, $src1, $src2\n\t"
10794 "msubw $dst, rscratch1, $src2, $src1" %}
10795
10796 ins_encode(aarch64_enc_modw(dst, src1, src2));
10797 ins_pipe(idiv_reg_reg);
10798 %}
10799
10800 // Long Remainder
10801
10802 instruct modL(iRegLNoSp dst, iRegL src1, iRegL src2) %{
10803 match(Set dst (ModL src1 src2));
10804
10805 ins_cost(INSN_COST * 38);
10806 format %{ "sdiv rscratch1, $src1, $src2\n"
10807 "msub $dst, rscratch1, $src2, $src1" %}
10808
10809 ins_encode(aarch64_enc_mod(dst, src1, src2));
10810 ins_pipe(ldiv_reg_reg);
10811 %}
10812
10813 // Unsigned Integer Divide
10814
10815 instruct UdivI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
10816 match(Set dst (UDivI src1 src2));
10817
10818 ins_cost(INSN_COST * 19);
10819 format %{ "udivw $dst, $src1, $src2" %}
10820
10821 ins_encode %{
10822 __ udivw($dst$$Register, $src1$$Register, $src2$$Register);
10823 %}
10824
10825 ins_pipe(idiv_reg_reg);
10826 %}
10827
10828 // Unsigned Long Divide
10829
10830 instruct UdivL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
10831 match(Set dst (UDivL src1 src2));
10832
10833 ins_cost(INSN_COST * 35);
10834 format %{ "udiv $dst, $src1, $src2" %}
10835
10836 ins_encode %{
10837 __ udiv($dst$$Register, $src1$$Register, $src2$$Register);
10838 %}
10839
10840 ins_pipe(ldiv_reg_reg);
10841 %}
10842
10843 // Unsigned Integer Remainder
10844
10845 instruct UmodI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
10846 match(Set dst (UModI src1 src2));
10847
10848 ins_cost(INSN_COST * 22);
10849 format %{ "udivw rscratch1, $src1, $src2\n\t"
10850 "msubw $dst, rscratch1, $src2, $src1" %}
10851
10852 ins_encode %{
10853 __ udivw(rscratch1, $src1$$Register, $src2$$Register);
10854 __ msubw($dst$$Register, rscratch1, $src2$$Register, $src1$$Register);
10855 %}
10856
10857 ins_pipe(idiv_reg_reg);
10858 %}
10859
10860 // Unsigned Long Remainder
10861
10862 instruct UModL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
10863 match(Set dst (UModL src1 src2));
10864
10865 ins_cost(INSN_COST * 38);
10866 format %{ "udiv rscratch1, $src1, $src2\n"
10867 "msub $dst, rscratch1, $src2, $src1" %}
10868
10869 ins_encode %{
10870 __ udiv(rscratch1, $src1$$Register, $src2$$Register);
10871 __ msub($dst$$Register, rscratch1, $src2$$Register, $src1$$Register);
10872 %}
10873
10874 ins_pipe(ldiv_reg_reg);
10875 %}
10876
10877 // Integer Shifts
10878
10879 // Shift Left Register
10880 instruct lShiftI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
10881 match(Set dst (LShiftI src1 src2));
10882
10883 ins_cost(INSN_COST * 2);
10884 format %{ "lslvw $dst, $src1, $src2" %}
10885
10886 ins_encode %{
10887 __ lslvw(as_Register($dst$$reg),
10888 as_Register($src1$$reg),
10889 as_Register($src2$$reg));
10890 %}
10891
10892 ins_pipe(ialu_reg_reg_vshift);
10893 %}
10894
10895 // Shift Left Immediate
10896 instruct lShiftI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immI src2) %{
10897 match(Set dst (LShiftI src1 src2));
10898
10899 ins_cost(INSN_COST);
10900 format %{ "lslw $dst, $src1, ($src2 & 0x1f)" %}
10901
10902 ins_encode %{
10903 __ lslw(as_Register($dst$$reg),
10904 as_Register($src1$$reg),
10905 $src2$$constant & 0x1f);
10906 %}
10907
10908 ins_pipe(ialu_reg_shift);
10909 %}
10910
10911 // Shift Right Logical Register
10912 instruct urShiftI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
10913 match(Set dst (URShiftI src1 src2));
10914
10915 ins_cost(INSN_COST * 2);
10916 format %{ "lsrvw $dst, $src1, $src2" %}
10917
10918 ins_encode %{
10919 __ lsrvw(as_Register($dst$$reg),
10920 as_Register($src1$$reg),
10921 as_Register($src2$$reg));
10922 %}
10923
10924 ins_pipe(ialu_reg_reg_vshift);
10925 %}
10926
10927 // Shift Right Logical Immediate
10928 instruct urShiftI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immI src2) %{
10929 match(Set dst (URShiftI src1 src2));
10930
10931 ins_cost(INSN_COST);
10932 format %{ "lsrw $dst, $src1, ($src2 & 0x1f)" %}
10933
10934 ins_encode %{
10935 __ lsrw(as_Register($dst$$reg),
10936 as_Register($src1$$reg),
10937 $src2$$constant & 0x1f);
10938 %}
10939
10940 ins_pipe(ialu_reg_shift);
10941 %}
10942
10943 // Shift Right Arithmetic Register
10944 instruct rShiftI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
10945 match(Set dst (RShiftI src1 src2));
10946
10947 ins_cost(INSN_COST * 2);
10948 format %{ "asrvw $dst, $src1, $src2" %}
10949
10950 ins_encode %{
10951 __ asrvw(as_Register($dst$$reg),
10952 as_Register($src1$$reg),
10953 as_Register($src2$$reg));
10954 %}
10955
10956 ins_pipe(ialu_reg_reg_vshift);
10957 %}
10958
10959 // Shift Right Arithmetic Immediate
10960 instruct rShiftI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immI src2) %{
10961 match(Set dst (RShiftI src1 src2));
10962
10963 ins_cost(INSN_COST);
10964 format %{ "asrw $dst, $src1, ($src2 & 0x1f)" %}
10965
10966 ins_encode %{
10967 __ asrw(as_Register($dst$$reg),
10968 as_Register($src1$$reg),
10969 $src2$$constant & 0x1f);
10970 %}
10971
10972 ins_pipe(ialu_reg_shift);
10973 %}
10974
10975 // Combined Int Mask and Right Shift (using UBFM)
10976 // TODO
10977
10978 // Long Shifts
10979
10980 // Shift Left Register
10981 instruct lShiftL_reg_reg(iRegLNoSp dst, iRegL src1, iRegIorL2I src2) %{
10982 match(Set dst (LShiftL src1 src2));
10983
10984 ins_cost(INSN_COST * 2);
10985 format %{ "lslv $dst, $src1, $src2" %}
10986
10987 ins_encode %{
10988 __ lslv(as_Register($dst$$reg),
10989 as_Register($src1$$reg),
10990 as_Register($src2$$reg));
10991 %}
10992
10993 ins_pipe(ialu_reg_reg_vshift);
10994 %}
10995
10996 // Shift Left Immediate
10997 instruct lShiftL_reg_imm(iRegLNoSp dst, iRegL src1, immI src2) %{
10998 match(Set dst (LShiftL src1 src2));
10999
11000 ins_cost(INSN_COST);
11001 format %{ "lsl $dst, $src1, ($src2 & 0x3f)" %}
11002
11003 ins_encode %{
11004 __ lsl(as_Register($dst$$reg),
11005 as_Register($src1$$reg),
11006 $src2$$constant & 0x3f);
11007 %}
11008
11009 ins_pipe(ialu_reg_shift);
11010 %}
11011
11012 // Shift Right Logical Register
11013 instruct urShiftL_reg_reg(iRegLNoSp dst, iRegL src1, iRegIorL2I src2) %{
11014 match(Set dst (URShiftL src1 src2));
11015
11016 ins_cost(INSN_COST * 2);
11017 format %{ "lsrv $dst, $src1, $src2" %}
11018
11019 ins_encode %{
11020 __ lsrv(as_Register($dst$$reg),
11021 as_Register($src1$$reg),
11022 as_Register($src2$$reg));
11023 %}
11024
11025 ins_pipe(ialu_reg_reg_vshift);
11026 %}
11027
11028 // Shift Right Logical Immediate
11029 instruct urShiftL_reg_imm(iRegLNoSp dst, iRegL src1, immI src2) %{
11030 match(Set dst (URShiftL src1 src2));
11031
11032 ins_cost(INSN_COST);
11033 format %{ "lsr $dst, $src1, ($src2 & 0x3f)" %}
11034
11035 ins_encode %{
11036 __ lsr(as_Register($dst$$reg),
11037 as_Register($src1$$reg),
11038 $src2$$constant & 0x3f);
11039 %}
11040
11041 ins_pipe(ialu_reg_shift);
11042 %}
11043
11044 // A special-case pattern for card table stores.
11045 instruct urShiftP_reg_imm(iRegLNoSp dst, iRegP src1, immI src2) %{
11046 match(Set dst (URShiftL (CastP2X src1) src2));
11047
11048 ins_cost(INSN_COST);
11049 format %{ "lsr $dst, p2x($src1), ($src2 & 0x3f)" %}
11050
11051 ins_encode %{
11052 __ lsr(as_Register($dst$$reg),
11053 as_Register($src1$$reg),
11054 $src2$$constant & 0x3f);
11055 %}
11056
11057 ins_pipe(ialu_reg_shift);
11058 %}
11059
11060 // Shift Right Arithmetic Register
11061 instruct rShiftL_reg_reg(iRegLNoSp dst, iRegL src1, iRegIorL2I src2) %{
11062 match(Set dst (RShiftL src1 src2));
11063
11064 ins_cost(INSN_COST * 2);
11065 format %{ "asrv $dst, $src1, $src2" %}
11066
11067 ins_encode %{
11068 __ asrv(as_Register($dst$$reg),
11069 as_Register($src1$$reg),
11070 as_Register($src2$$reg));
11071 %}
11072
11073 ins_pipe(ialu_reg_reg_vshift);
11074 %}
11075
11076 // Shift Right Arithmetic Immediate
11077 instruct rShiftL_reg_imm(iRegLNoSp dst, iRegL src1, immI src2) %{
11078 match(Set dst (RShiftL src1 src2));
11079
11080 ins_cost(INSN_COST);
11081 format %{ "asr $dst, $src1, ($src2 & 0x3f)" %}
11082
11083 ins_encode %{
11084 __ asr(as_Register($dst$$reg),
11085 as_Register($src1$$reg),
11086 $src2$$constant & 0x3f);
11087 %}
11088
11089 ins_pipe(ialu_reg_shift);
11090 %}
11091
11092 // BEGIN This section of the file is automatically generated. Do not edit --------------
11093 // This section is generated from aarch64_ad.m4
11094
11095 // This pattern is automatically generated from aarch64_ad.m4
11096 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
11097 instruct regL_not_reg(iRegLNoSp dst,
11098 iRegL src1, immL_M1 m1,
11099 rFlagsReg cr) %{
11100 match(Set dst (XorL src1 m1));
11101 ins_cost(INSN_COST);
11102 format %{ "eon $dst, $src1, zr" %}
11103
11104 ins_encode %{
11105 __ eon(as_Register($dst$$reg),
11106 as_Register($src1$$reg),
11107 zr,
11108 Assembler::LSL, 0);
11109 %}
11110
11111 ins_pipe(ialu_reg);
11112 %}
11113
11114 // This pattern is automatically generated from aarch64_ad.m4
11115 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
11116 instruct regI_not_reg(iRegINoSp dst,
11117 iRegIorL2I src1, immI_M1 m1,
11118 rFlagsReg cr) %{
11119 match(Set dst (XorI src1 m1));
11120 ins_cost(INSN_COST);
11121 format %{ "eonw $dst, $src1, zr" %}
11122
11123 ins_encode %{
11124 __ eonw(as_Register($dst$$reg),
11125 as_Register($src1$$reg),
11126 zr,
11127 Assembler::LSL, 0);
11128 %}
11129
11130 ins_pipe(ialu_reg);
11131 %}
11132
11133 // This pattern is automatically generated from aarch64_ad.m4
11134 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
11135 instruct NegI_reg_URShift_reg(iRegINoSp dst,
11136 immI0 zero, iRegIorL2I src1, immI src2) %{
11137 match(Set dst (SubI zero (URShiftI src1 src2)));
11138
11139 ins_cost(1.9 * INSN_COST);
11140 format %{ "negw $dst, $src1, LSR $src2" %}
11141
11142 ins_encode %{
11143 __ negw(as_Register($dst$$reg), as_Register($src1$$reg),
11144 Assembler::LSR, $src2$$constant & 0x1f);
11145 %}
11146
11147 ins_pipe(ialu_reg_shift);
11148 %}
11149
11150 // This pattern is automatically generated from aarch64_ad.m4
11151 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
11152 instruct NegI_reg_RShift_reg(iRegINoSp dst,
11153 immI0 zero, iRegIorL2I src1, immI src2) %{
11154 match(Set dst (SubI zero (RShiftI src1 src2)));
11155
11156 ins_cost(1.9 * INSN_COST);
11157 format %{ "negw $dst, $src1, ASR $src2" %}
11158
11159 ins_encode %{
11160 __ negw(as_Register($dst$$reg), as_Register($src1$$reg),
11161 Assembler::ASR, $src2$$constant & 0x1f);
11162 %}
11163
11164 ins_pipe(ialu_reg_shift);
11165 %}
11166
11167 // This pattern is automatically generated from aarch64_ad.m4
11168 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
11169 instruct NegI_reg_LShift_reg(iRegINoSp dst,
11170 immI0 zero, iRegIorL2I src1, immI src2) %{
11171 match(Set dst (SubI zero (LShiftI src1 src2)));
11172
11173 ins_cost(1.9 * INSN_COST);
11174 format %{ "negw $dst, $src1, LSL $src2" %}
11175
11176 ins_encode %{
11177 __ negw(as_Register($dst$$reg), as_Register($src1$$reg),
11178 Assembler::LSL, $src2$$constant & 0x1f);
11179 %}
11180
11181 ins_pipe(ialu_reg_shift);
11182 %}
11183
11184 // This pattern is automatically generated from aarch64_ad.m4
11185 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
11186 instruct NegL_reg_URShift_reg(iRegLNoSp dst,
11187 immL0 zero, iRegL src1, immI src2) %{
11188 match(Set dst (SubL zero (URShiftL src1 src2)));
11189
11190 ins_cost(1.9 * INSN_COST);
11191 format %{ "neg $dst, $src1, LSR $src2" %}
11192
11193 ins_encode %{
11194 __ neg(as_Register($dst$$reg), as_Register($src1$$reg),
11195 Assembler::LSR, $src2$$constant & 0x3f);
11196 %}
11197
11198 ins_pipe(ialu_reg_shift);
11199 %}
11200
11201 // This pattern is automatically generated from aarch64_ad.m4
11202 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
11203 instruct NegL_reg_RShift_reg(iRegLNoSp dst,
11204 immL0 zero, iRegL src1, immI src2) %{
11205 match(Set dst (SubL zero (RShiftL src1 src2)));
11206
11207 ins_cost(1.9 * INSN_COST);
11208 format %{ "neg $dst, $src1, ASR $src2" %}
11209
11210 ins_encode %{
11211 __ neg(as_Register($dst$$reg), as_Register($src1$$reg),
11212 Assembler::ASR, $src2$$constant & 0x3f);
11213 %}
11214
11215 ins_pipe(ialu_reg_shift);
11216 %}
11217
11218 // This pattern is automatically generated from aarch64_ad.m4
11219 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
11220 instruct NegL_reg_LShift_reg(iRegLNoSp dst,
11221 immL0 zero, iRegL src1, immI src2) %{
11222 match(Set dst (SubL zero (LShiftL src1 src2)));
11223
11224 ins_cost(1.9 * INSN_COST);
11225 format %{ "neg $dst, $src1, LSL $src2" %}
11226
11227 ins_encode %{
11228 __ neg(as_Register($dst$$reg), as_Register($src1$$reg),
11229 Assembler::LSL, $src2$$constant & 0x3f);
11230 %}
11231
11232 ins_pipe(ialu_reg_shift);
11233 %}
11234
11235 // This pattern is automatically generated from aarch64_ad.m4
11236 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
11237 instruct AndI_reg_not_reg(iRegINoSp dst,
11238 iRegIorL2I src1, iRegIorL2I src2, immI_M1 m1) %{
11239 match(Set dst (AndI src1 (XorI src2 m1)));
11240 ins_cost(INSN_COST);
11241 format %{ "bicw $dst, $src1, $src2" %}
11242
11243 ins_encode %{
11244 __ bicw(as_Register($dst$$reg),
11245 as_Register($src1$$reg),
11246 as_Register($src2$$reg),
11247 Assembler::LSL, 0);
11248 %}
11249
11250 ins_pipe(ialu_reg_reg);
11251 %}
11252
11253 // This pattern is automatically generated from aarch64_ad.m4
11254 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
11255 instruct AndL_reg_not_reg(iRegLNoSp dst,
11256 iRegL src1, iRegL src2, immL_M1 m1) %{
11257 match(Set dst (AndL src1 (XorL src2 m1)));
11258 ins_cost(INSN_COST);
11259 format %{ "bic $dst, $src1, $src2" %}
11260
11261 ins_encode %{
11262 __ bic(as_Register($dst$$reg),
11263 as_Register($src1$$reg),
11264 as_Register($src2$$reg),
11265 Assembler::LSL, 0);
11266 %}
11267
11268 ins_pipe(ialu_reg_reg);
11269 %}
11270
11271 // This pattern is automatically generated from aarch64_ad.m4
11272 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
11273 instruct OrI_reg_not_reg(iRegINoSp dst,
11274 iRegIorL2I src1, iRegIorL2I src2, immI_M1 m1) %{
11275 match(Set dst (OrI src1 (XorI src2 m1)));
11276 ins_cost(INSN_COST);
11277 format %{ "ornw $dst, $src1, $src2" %}
11278
11279 ins_encode %{
11280 __ ornw(as_Register($dst$$reg),
11281 as_Register($src1$$reg),
11282 as_Register($src2$$reg),
11283 Assembler::LSL, 0);
11284 %}
11285
11286 ins_pipe(ialu_reg_reg);
11287 %}
11288
11289 // This pattern is automatically generated from aarch64_ad.m4
11290 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
11291 instruct OrL_reg_not_reg(iRegLNoSp dst,
11292 iRegL src1, iRegL src2, immL_M1 m1) %{
11293 match(Set dst (OrL src1 (XorL src2 m1)));
11294 ins_cost(INSN_COST);
11295 format %{ "orn $dst, $src1, $src2" %}
11296
11297 ins_encode %{
11298 __ orn(as_Register($dst$$reg),
11299 as_Register($src1$$reg),
11300 as_Register($src2$$reg),
11301 Assembler::LSL, 0);
11302 %}
11303
11304 ins_pipe(ialu_reg_reg);
11305 %}
11306
11307 // This pattern is automatically generated from aarch64_ad.m4
11308 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
11309 instruct XorI_reg_not_reg(iRegINoSp dst,
11310 iRegIorL2I src1, iRegIorL2I src2, immI_M1 m1) %{
11311 match(Set dst (XorI m1 (XorI src2 src1)));
11312 ins_cost(INSN_COST);
11313 format %{ "eonw $dst, $src1, $src2" %}
11314
11315 ins_encode %{
11316 __ eonw(as_Register($dst$$reg),
11317 as_Register($src1$$reg),
11318 as_Register($src2$$reg),
11319 Assembler::LSL, 0);
11320 %}
11321
11322 ins_pipe(ialu_reg_reg);
11323 %}
11324
11325 // This pattern is automatically generated from aarch64_ad.m4
11326 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
11327 instruct XorL_reg_not_reg(iRegLNoSp dst,
11328 iRegL src1, iRegL src2, immL_M1 m1) %{
11329 match(Set dst (XorL m1 (XorL src2 src1)));
11330 ins_cost(INSN_COST);
11331 format %{ "eon $dst, $src1, $src2" %}
11332
11333 ins_encode %{
11334 __ eon(as_Register($dst$$reg),
11335 as_Register($src1$$reg),
11336 as_Register($src2$$reg),
11337 Assembler::LSL, 0);
11338 %}
11339
11340 ins_pipe(ialu_reg_reg);
11341 %}
11342
11343 // This pattern is automatically generated from aarch64_ad.m4
11344 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
11345 // val & (-1 ^ (val >>> shift)) ==> bicw
11346 instruct AndI_reg_URShift_not_reg(iRegINoSp dst,
11347 iRegIorL2I src1, iRegIorL2I src2,
11348 immI src3, immI_M1 src4) %{
11349 match(Set dst (AndI src1 (XorI(URShiftI src2 src3) src4)));
11350 ins_cost(1.9 * INSN_COST);
11351 format %{ "bicw $dst, $src1, $src2, LSR $src3" %}
11352
11353 ins_encode %{
11354 __ bicw(as_Register($dst$$reg),
11355 as_Register($src1$$reg),
11356 as_Register($src2$$reg),
11357 Assembler::LSR,
11358 $src3$$constant & 0x1f);
11359 %}
11360
11361 ins_pipe(ialu_reg_reg_shift);
11362 %}
11363
11364 // This pattern is automatically generated from aarch64_ad.m4
11365 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
11366 // val & (-1 ^ (val >>> shift)) ==> bic
11367 instruct AndL_reg_URShift_not_reg(iRegLNoSp dst,
11368 iRegL src1, iRegL src2,
11369 immI src3, immL_M1 src4) %{
11370 match(Set dst (AndL src1 (XorL(URShiftL src2 src3) src4)));
11371 ins_cost(1.9 * INSN_COST);
11372 format %{ "bic $dst, $src1, $src2, LSR $src3" %}
11373
11374 ins_encode %{
11375 __ bic(as_Register($dst$$reg),
11376 as_Register($src1$$reg),
11377 as_Register($src2$$reg),
11378 Assembler::LSR,
11379 $src3$$constant & 0x3f);
11380 %}
11381
11382 ins_pipe(ialu_reg_reg_shift);
11383 %}
11384
11385 // This pattern is automatically generated from aarch64_ad.m4
11386 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
11387 // val & (-1 ^ (val >> shift)) ==> bicw
11388 instruct AndI_reg_RShift_not_reg(iRegINoSp dst,
11389 iRegIorL2I src1, iRegIorL2I src2,
11390 immI src3, immI_M1 src4) %{
11391 match(Set dst (AndI src1 (XorI(RShiftI src2 src3) src4)));
11392 ins_cost(1.9 * INSN_COST);
11393 format %{ "bicw $dst, $src1, $src2, ASR $src3" %}
11394
11395 ins_encode %{
11396 __ bicw(as_Register($dst$$reg),
11397 as_Register($src1$$reg),
11398 as_Register($src2$$reg),
11399 Assembler::ASR,
11400 $src3$$constant & 0x1f);
11401 %}
11402
11403 ins_pipe(ialu_reg_reg_shift);
11404 %}
11405
11406 // This pattern is automatically generated from aarch64_ad.m4
11407 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
11408 // val & (-1 ^ (val >> shift)) ==> bic
11409 instruct AndL_reg_RShift_not_reg(iRegLNoSp dst,
11410 iRegL src1, iRegL src2,
11411 immI src3, immL_M1 src4) %{
11412 match(Set dst (AndL src1 (XorL(RShiftL src2 src3) src4)));
11413 ins_cost(1.9 * INSN_COST);
11414 format %{ "bic $dst, $src1, $src2, ASR $src3" %}
11415
11416 ins_encode %{
11417 __ bic(as_Register($dst$$reg),
11418 as_Register($src1$$reg),
11419 as_Register($src2$$reg),
11420 Assembler::ASR,
11421 $src3$$constant & 0x3f);
11422 %}
11423
11424 ins_pipe(ialu_reg_reg_shift);
11425 %}
11426
11427 // This pattern is automatically generated from aarch64_ad.m4
11428 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
11429 // val & (-1 ^ (val ror shift)) ==> bicw
11430 instruct AndI_reg_RotateRight_not_reg(iRegINoSp dst,
11431 iRegIorL2I src1, iRegIorL2I src2,
11432 immI src3, immI_M1 src4) %{
11433 match(Set dst (AndI src1 (XorI(RotateRight src2 src3) src4)));
11434 ins_cost(1.9 * INSN_COST);
11435 format %{ "bicw $dst, $src1, $src2, ROR $src3" %}
11436
11437 ins_encode %{
11438 __ bicw(as_Register($dst$$reg),
11439 as_Register($src1$$reg),
11440 as_Register($src2$$reg),
11441 Assembler::ROR,
11442 $src3$$constant & 0x1f);
11443 %}
11444
11445 ins_pipe(ialu_reg_reg_shift);
11446 %}
11447
11448 // This pattern is automatically generated from aarch64_ad.m4
11449 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
11450 // val & (-1 ^ (val ror shift)) ==> bic
11451 instruct AndL_reg_RotateRight_not_reg(iRegLNoSp dst,
11452 iRegL src1, iRegL src2,
11453 immI src3, immL_M1 src4) %{
11454 match(Set dst (AndL src1 (XorL(RotateRight src2 src3) src4)));
11455 ins_cost(1.9 * INSN_COST);
11456 format %{ "bic $dst, $src1, $src2, ROR $src3" %}
11457
11458 ins_encode %{
11459 __ bic(as_Register($dst$$reg),
11460 as_Register($src1$$reg),
11461 as_Register($src2$$reg),
11462 Assembler::ROR,
11463 $src3$$constant & 0x3f);
11464 %}
11465
11466 ins_pipe(ialu_reg_reg_shift);
11467 %}
11468
11469 // This pattern is automatically generated from aarch64_ad.m4
11470 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
11471 // val & (-1 ^ (val << shift)) ==> bicw
11472 instruct AndI_reg_LShift_not_reg(iRegINoSp dst,
11473 iRegIorL2I src1, iRegIorL2I src2,
11474 immI src3, immI_M1 src4) %{
11475 match(Set dst (AndI src1 (XorI(LShiftI src2 src3) src4)));
11476 ins_cost(1.9 * INSN_COST);
11477 format %{ "bicw $dst, $src1, $src2, LSL $src3" %}
11478
11479 ins_encode %{
11480 __ bicw(as_Register($dst$$reg),
11481 as_Register($src1$$reg),
11482 as_Register($src2$$reg),
11483 Assembler::LSL,
11484 $src3$$constant & 0x1f);
11485 %}
11486
11487 ins_pipe(ialu_reg_reg_shift);
11488 %}
11489
11490 // This pattern is automatically generated from aarch64_ad.m4
11491 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
11492 // val & (-1 ^ (val << shift)) ==> bic
11493 instruct AndL_reg_LShift_not_reg(iRegLNoSp dst,
11494 iRegL src1, iRegL src2,
11495 immI src3, immL_M1 src4) %{
11496 match(Set dst (AndL src1 (XorL(LShiftL src2 src3) src4)));
11497 ins_cost(1.9 * INSN_COST);
11498 format %{ "bic $dst, $src1, $src2, LSL $src3" %}
11499
11500 ins_encode %{
11501 __ bic(as_Register($dst$$reg),
11502 as_Register($src1$$reg),
11503 as_Register($src2$$reg),
11504 Assembler::LSL,
11505 $src3$$constant & 0x3f);
11506 %}
11507
11508 ins_pipe(ialu_reg_reg_shift);
11509 %}
11510
11511 // This pattern is automatically generated from aarch64_ad.m4
11512 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
11513 // val ^ (-1 ^ (val >>> shift)) ==> eonw
11514 instruct XorI_reg_URShift_not_reg(iRegINoSp dst,
11515 iRegIorL2I src1, iRegIorL2I src2,
11516 immI src3, immI_M1 src4) %{
11517 match(Set dst (XorI src4 (XorI(URShiftI src2 src3) src1)));
11518 ins_cost(1.9 * INSN_COST);
11519 format %{ "eonw $dst, $src1, $src2, LSR $src3" %}
11520
11521 ins_encode %{
11522 __ eonw(as_Register($dst$$reg),
11523 as_Register($src1$$reg),
11524 as_Register($src2$$reg),
11525 Assembler::LSR,
11526 $src3$$constant & 0x1f);
11527 %}
11528
11529 ins_pipe(ialu_reg_reg_shift);
11530 %}
11531
11532 // This pattern is automatically generated from aarch64_ad.m4
11533 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
11534 // val ^ (-1 ^ (val >>> shift)) ==> eon
11535 instruct XorL_reg_URShift_not_reg(iRegLNoSp dst,
11536 iRegL src1, iRegL src2,
11537 immI src3, immL_M1 src4) %{
11538 match(Set dst (XorL src4 (XorL(URShiftL src2 src3) src1)));
11539 ins_cost(1.9 * INSN_COST);
11540 format %{ "eon $dst, $src1, $src2, LSR $src3" %}
11541
11542 ins_encode %{
11543 __ eon(as_Register($dst$$reg),
11544 as_Register($src1$$reg),
11545 as_Register($src2$$reg),
11546 Assembler::LSR,
11547 $src3$$constant & 0x3f);
11548 %}
11549
11550 ins_pipe(ialu_reg_reg_shift);
11551 %}
11552
11553 // This pattern is automatically generated from aarch64_ad.m4
11554 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
11555 // val ^ (-1 ^ (val >> shift)) ==> eonw
11556 instruct XorI_reg_RShift_not_reg(iRegINoSp dst,
11557 iRegIorL2I src1, iRegIorL2I src2,
11558 immI src3, immI_M1 src4) %{
11559 match(Set dst (XorI src4 (XorI(RShiftI src2 src3) src1)));
11560 ins_cost(1.9 * INSN_COST);
11561 format %{ "eonw $dst, $src1, $src2, ASR $src3" %}
11562
11563 ins_encode %{
11564 __ eonw(as_Register($dst$$reg),
11565 as_Register($src1$$reg),
11566 as_Register($src2$$reg),
11567 Assembler::ASR,
11568 $src3$$constant & 0x1f);
11569 %}
11570
11571 ins_pipe(ialu_reg_reg_shift);
11572 %}
11573
11574 // This pattern is automatically generated from aarch64_ad.m4
11575 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
11576 // val ^ (-1 ^ (val >> shift)) ==> eon
11577 instruct XorL_reg_RShift_not_reg(iRegLNoSp dst,
11578 iRegL src1, iRegL src2,
11579 immI src3, immL_M1 src4) %{
11580 match(Set dst (XorL src4 (XorL(RShiftL src2 src3) src1)));
11581 ins_cost(1.9 * INSN_COST);
11582 format %{ "eon $dst, $src1, $src2, ASR $src3" %}
11583
11584 ins_encode %{
11585 __ eon(as_Register($dst$$reg),
11586 as_Register($src1$$reg),
11587 as_Register($src2$$reg),
11588 Assembler::ASR,
11589 $src3$$constant & 0x3f);
11590 %}
11591
11592 ins_pipe(ialu_reg_reg_shift);
11593 %}
11594
11595 // This pattern is automatically generated from aarch64_ad.m4
11596 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
11597 // val ^ (-1 ^ (val ror shift)) ==> eonw
11598 instruct XorI_reg_RotateRight_not_reg(iRegINoSp dst,
11599 iRegIorL2I src1, iRegIorL2I src2,
11600 immI src3, immI_M1 src4) %{
11601 match(Set dst (XorI src4 (XorI(RotateRight src2 src3) src1)));
11602 ins_cost(1.9 * INSN_COST);
11603 format %{ "eonw $dst, $src1, $src2, ROR $src3" %}
11604
11605 ins_encode %{
11606 __ eonw(as_Register($dst$$reg),
11607 as_Register($src1$$reg),
11608 as_Register($src2$$reg),
11609 Assembler::ROR,
11610 $src3$$constant & 0x1f);
11611 %}
11612
11613 ins_pipe(ialu_reg_reg_shift);
11614 %}
11615
11616 // This pattern is automatically generated from aarch64_ad.m4
11617 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
11618 // val ^ (-1 ^ (val ror shift)) ==> eon
11619 instruct XorL_reg_RotateRight_not_reg(iRegLNoSp dst,
11620 iRegL src1, iRegL src2,
11621 immI src3, immL_M1 src4) %{
11622 match(Set dst (XorL src4 (XorL(RotateRight src2 src3) src1)));
11623 ins_cost(1.9 * INSN_COST);
11624 format %{ "eon $dst, $src1, $src2, ROR $src3" %}
11625
11626 ins_encode %{
11627 __ eon(as_Register($dst$$reg),
11628 as_Register($src1$$reg),
11629 as_Register($src2$$reg),
11630 Assembler::ROR,
11631 $src3$$constant & 0x3f);
11632 %}
11633
11634 ins_pipe(ialu_reg_reg_shift);
11635 %}
11636
11637 // This pattern is automatically generated from aarch64_ad.m4
11638 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
11639 // val ^ (-1 ^ (val << shift)) ==> eonw
11640 instruct XorI_reg_LShift_not_reg(iRegINoSp dst,
11641 iRegIorL2I src1, iRegIorL2I src2,
11642 immI src3, immI_M1 src4) %{
11643 match(Set dst (XorI src4 (XorI(LShiftI src2 src3) src1)));
11644 ins_cost(1.9 * INSN_COST);
11645 format %{ "eonw $dst, $src1, $src2, LSL $src3" %}
11646
11647 ins_encode %{
11648 __ eonw(as_Register($dst$$reg),
11649 as_Register($src1$$reg),
11650 as_Register($src2$$reg),
11651 Assembler::LSL,
11652 $src3$$constant & 0x1f);
11653 %}
11654
11655 ins_pipe(ialu_reg_reg_shift);
11656 %}
11657
11658 // This pattern is automatically generated from aarch64_ad.m4
11659 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
11660 // val ^ (-1 ^ (val << shift)) ==> eon
11661 instruct XorL_reg_LShift_not_reg(iRegLNoSp dst,
11662 iRegL src1, iRegL src2,
11663 immI src3, immL_M1 src4) %{
11664 match(Set dst (XorL src4 (XorL(LShiftL src2 src3) src1)));
11665 ins_cost(1.9 * INSN_COST);
11666 format %{ "eon $dst, $src1, $src2, LSL $src3" %}
11667
11668 ins_encode %{
11669 __ eon(as_Register($dst$$reg),
11670 as_Register($src1$$reg),
11671 as_Register($src2$$reg),
11672 Assembler::LSL,
11673 $src3$$constant & 0x3f);
11674 %}
11675
11676 ins_pipe(ialu_reg_reg_shift);
11677 %}
11678
11679 // This pattern is automatically generated from aarch64_ad.m4
11680 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
11681 // val | (-1 ^ (val >>> shift)) ==> ornw
11682 instruct OrI_reg_URShift_not_reg(iRegINoSp dst,
11683 iRegIorL2I src1, iRegIorL2I src2,
11684 immI src3, immI_M1 src4) %{
11685 match(Set dst (OrI src1 (XorI(URShiftI src2 src3) src4)));
11686 ins_cost(1.9 * INSN_COST);
11687 format %{ "ornw $dst, $src1, $src2, LSR $src3" %}
11688
11689 ins_encode %{
11690 __ ornw(as_Register($dst$$reg),
11691 as_Register($src1$$reg),
11692 as_Register($src2$$reg),
11693 Assembler::LSR,
11694 $src3$$constant & 0x1f);
11695 %}
11696
11697 ins_pipe(ialu_reg_reg_shift);
11698 %}
11699
11700 // This pattern is automatically generated from aarch64_ad.m4
11701 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
11702 // val | (-1 ^ (val >>> shift)) ==> orn
11703 instruct OrL_reg_URShift_not_reg(iRegLNoSp dst,
11704 iRegL src1, iRegL src2,
11705 immI src3, immL_M1 src4) %{
11706 match(Set dst (OrL src1 (XorL(URShiftL src2 src3) src4)));
11707 ins_cost(1.9 * INSN_COST);
11708 format %{ "orn $dst, $src1, $src2, LSR $src3" %}
11709
11710 ins_encode %{
11711 __ orn(as_Register($dst$$reg),
11712 as_Register($src1$$reg),
11713 as_Register($src2$$reg),
11714 Assembler::LSR,
11715 $src3$$constant & 0x3f);
11716 %}
11717
11718 ins_pipe(ialu_reg_reg_shift);
11719 %}
11720
11721 // This pattern is automatically generated from aarch64_ad.m4
11722 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
11723 // val | (-1 ^ (val >> shift)) ==> ornw
11724 instruct OrI_reg_RShift_not_reg(iRegINoSp dst,
11725 iRegIorL2I src1, iRegIorL2I src2,
11726 immI src3, immI_M1 src4) %{
11727 match(Set dst (OrI src1 (XorI(RShiftI src2 src3) src4)));
11728 ins_cost(1.9 * INSN_COST);
11729 format %{ "ornw $dst, $src1, $src2, ASR $src3" %}
11730
11731 ins_encode %{
11732 __ ornw(as_Register($dst$$reg),
11733 as_Register($src1$$reg),
11734 as_Register($src2$$reg),
11735 Assembler::ASR,
11736 $src3$$constant & 0x1f);
11737 %}
11738
11739 ins_pipe(ialu_reg_reg_shift);
11740 %}
11741
11742 // This pattern is automatically generated from aarch64_ad.m4
11743 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
11744 // val | (-1 ^ (val >> shift)) ==> orn
11745 instruct OrL_reg_RShift_not_reg(iRegLNoSp dst,
11746 iRegL src1, iRegL src2,
11747 immI src3, immL_M1 src4) %{
11748 match(Set dst (OrL src1 (XorL(RShiftL src2 src3) src4)));
11749 ins_cost(1.9 * INSN_COST);
11750 format %{ "orn $dst, $src1, $src2, ASR $src3" %}
11751
11752 ins_encode %{
11753 __ orn(as_Register($dst$$reg),
11754 as_Register($src1$$reg),
11755 as_Register($src2$$reg),
11756 Assembler::ASR,
11757 $src3$$constant & 0x3f);
11758 %}
11759
11760 ins_pipe(ialu_reg_reg_shift);
11761 %}
11762
11763 // This pattern is automatically generated from aarch64_ad.m4
11764 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
11765 // val | (-1 ^ (val ror shift)) ==> ornw
11766 instruct OrI_reg_RotateRight_not_reg(iRegINoSp dst,
11767 iRegIorL2I src1, iRegIorL2I src2,
11768 immI src3, immI_M1 src4) %{
11769 match(Set dst (OrI src1 (XorI(RotateRight src2 src3) src4)));
11770 ins_cost(1.9 * INSN_COST);
11771 format %{ "ornw $dst, $src1, $src2, ROR $src3" %}
11772
11773 ins_encode %{
11774 __ ornw(as_Register($dst$$reg),
11775 as_Register($src1$$reg),
11776 as_Register($src2$$reg),
11777 Assembler::ROR,
11778 $src3$$constant & 0x1f);
11779 %}
11780
11781 ins_pipe(ialu_reg_reg_shift);
11782 %}
11783
11784 // This pattern is automatically generated from aarch64_ad.m4
11785 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
11786 // val | (-1 ^ (val ror shift)) ==> orn
11787 instruct OrL_reg_RotateRight_not_reg(iRegLNoSp dst,
11788 iRegL src1, iRegL src2,
11789 immI src3, immL_M1 src4) %{
11790 match(Set dst (OrL src1 (XorL(RotateRight src2 src3) src4)));
11791 ins_cost(1.9 * INSN_COST);
11792 format %{ "orn $dst, $src1, $src2, ROR $src3" %}
11793
11794 ins_encode %{
11795 __ orn(as_Register($dst$$reg),
11796 as_Register($src1$$reg),
11797 as_Register($src2$$reg),
11798 Assembler::ROR,
11799 $src3$$constant & 0x3f);
11800 %}
11801
11802 ins_pipe(ialu_reg_reg_shift);
11803 %}
11804
11805 // This pattern is automatically generated from aarch64_ad.m4
11806 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
11807 // val | (-1 ^ (val << shift)) ==> ornw
11808 instruct OrI_reg_LShift_not_reg(iRegINoSp dst,
11809 iRegIorL2I src1, iRegIorL2I src2,
11810 immI src3, immI_M1 src4) %{
11811 match(Set dst (OrI src1 (XorI(LShiftI src2 src3) src4)));
11812 ins_cost(1.9 * INSN_COST);
11813 format %{ "ornw $dst, $src1, $src2, LSL $src3" %}
11814
11815 ins_encode %{
11816 __ ornw(as_Register($dst$$reg),
11817 as_Register($src1$$reg),
11818 as_Register($src2$$reg),
11819 Assembler::LSL,
11820 $src3$$constant & 0x1f);
11821 %}
11822
11823 ins_pipe(ialu_reg_reg_shift);
11824 %}
11825
11826 // This pattern is automatically generated from aarch64_ad.m4
11827 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
11828 // val | (-1 ^ (val << shift)) ==> orn
11829 instruct OrL_reg_LShift_not_reg(iRegLNoSp dst,
11830 iRegL src1, iRegL src2,
11831 immI src3, immL_M1 src4) %{
11832 match(Set dst (OrL src1 (XorL(LShiftL src2 src3) src4)));
11833 ins_cost(1.9 * INSN_COST);
11834 format %{ "orn $dst, $src1, $src2, LSL $src3" %}
11835
11836 ins_encode %{
11837 __ orn(as_Register($dst$$reg),
11838 as_Register($src1$$reg),
11839 as_Register($src2$$reg),
11840 Assembler::LSL,
11841 $src3$$constant & 0x3f);
11842 %}
11843
11844 ins_pipe(ialu_reg_reg_shift);
11845 %}
11846
11847 // This pattern is automatically generated from aarch64_ad.m4
11848 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
11849 instruct AndI_reg_URShift_reg(iRegINoSp dst,
11850 iRegIorL2I src1, iRegIorL2I src2,
11851 immI src3) %{
11852 match(Set dst (AndI src1 (URShiftI src2 src3)));
11853
11854 ins_cost(1.9 * INSN_COST);
11855 format %{ "andw $dst, $src1, $src2, LSR $src3" %}
11856
11857 ins_encode %{
11858 __ andw(as_Register($dst$$reg),
11859 as_Register($src1$$reg),
11860 as_Register($src2$$reg),
11861 Assembler::LSR,
11862 $src3$$constant & 0x1f);
11863 %}
11864
11865 ins_pipe(ialu_reg_reg_shift);
11866 %}
11867
11868 // This pattern is automatically generated from aarch64_ad.m4
11869 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
11870 instruct AndL_reg_URShift_reg(iRegLNoSp dst,
11871 iRegL src1, iRegL src2,
11872 immI src3) %{
11873 match(Set dst (AndL src1 (URShiftL src2 src3)));
11874
11875 ins_cost(1.9 * INSN_COST);
11876 format %{ "andr $dst, $src1, $src2, LSR $src3" %}
11877
11878 ins_encode %{
11879 __ andr(as_Register($dst$$reg),
11880 as_Register($src1$$reg),
11881 as_Register($src2$$reg),
11882 Assembler::LSR,
11883 $src3$$constant & 0x3f);
11884 %}
11885
11886 ins_pipe(ialu_reg_reg_shift);
11887 %}
11888
11889 // This pattern is automatically generated from aarch64_ad.m4
11890 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
11891 instruct AndI_reg_RShift_reg(iRegINoSp dst,
11892 iRegIorL2I src1, iRegIorL2I src2,
11893 immI src3) %{
11894 match(Set dst (AndI src1 (RShiftI src2 src3)));
11895
11896 ins_cost(1.9 * INSN_COST);
11897 format %{ "andw $dst, $src1, $src2, ASR $src3" %}
11898
11899 ins_encode %{
11900 __ andw(as_Register($dst$$reg),
11901 as_Register($src1$$reg),
11902 as_Register($src2$$reg),
11903 Assembler::ASR,
11904 $src3$$constant & 0x1f);
11905 %}
11906
11907 ins_pipe(ialu_reg_reg_shift);
11908 %}
11909
11910 // This pattern is automatically generated from aarch64_ad.m4
11911 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
11912 instruct AndL_reg_RShift_reg(iRegLNoSp dst,
11913 iRegL src1, iRegL src2,
11914 immI src3) %{
11915 match(Set dst (AndL src1 (RShiftL src2 src3)));
11916
11917 ins_cost(1.9 * INSN_COST);
11918 format %{ "andr $dst, $src1, $src2, ASR $src3" %}
11919
11920 ins_encode %{
11921 __ andr(as_Register($dst$$reg),
11922 as_Register($src1$$reg),
11923 as_Register($src2$$reg),
11924 Assembler::ASR,
11925 $src3$$constant & 0x3f);
11926 %}
11927
11928 ins_pipe(ialu_reg_reg_shift);
11929 %}
11930
11931 // This pattern is automatically generated from aarch64_ad.m4
11932 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
11933 instruct AndI_reg_LShift_reg(iRegINoSp dst,
11934 iRegIorL2I src1, iRegIorL2I src2,
11935 immI src3) %{
11936 match(Set dst (AndI src1 (LShiftI src2 src3)));
11937
11938 ins_cost(1.9 * INSN_COST);
11939 format %{ "andw $dst, $src1, $src2, LSL $src3" %}
11940
11941 ins_encode %{
11942 __ andw(as_Register($dst$$reg),
11943 as_Register($src1$$reg),
11944 as_Register($src2$$reg),
11945 Assembler::LSL,
11946 $src3$$constant & 0x1f);
11947 %}
11948
11949 ins_pipe(ialu_reg_reg_shift);
11950 %}
11951
11952 // This pattern is automatically generated from aarch64_ad.m4
11953 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
11954 instruct AndL_reg_LShift_reg(iRegLNoSp dst,
11955 iRegL src1, iRegL src2,
11956 immI src3) %{
11957 match(Set dst (AndL src1 (LShiftL src2 src3)));
11958
11959 ins_cost(1.9 * INSN_COST);
11960 format %{ "andr $dst, $src1, $src2, LSL $src3" %}
11961
11962 ins_encode %{
11963 __ andr(as_Register($dst$$reg),
11964 as_Register($src1$$reg),
11965 as_Register($src2$$reg),
11966 Assembler::LSL,
11967 $src3$$constant & 0x3f);
11968 %}
11969
11970 ins_pipe(ialu_reg_reg_shift);
11971 %}
11972
11973 // This pattern is automatically generated from aarch64_ad.m4
11974 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
11975 instruct AndI_reg_RotateRight_reg(iRegINoSp dst,
11976 iRegIorL2I src1, iRegIorL2I src2,
11977 immI src3) %{
11978 match(Set dst (AndI src1 (RotateRight src2 src3)));
11979
11980 ins_cost(1.9 * INSN_COST);
11981 format %{ "andw $dst, $src1, $src2, ROR $src3" %}
11982
11983 ins_encode %{
11984 __ andw(as_Register($dst$$reg),
11985 as_Register($src1$$reg),
11986 as_Register($src2$$reg),
11987 Assembler::ROR,
11988 $src3$$constant & 0x1f);
11989 %}
11990
11991 ins_pipe(ialu_reg_reg_shift);
11992 %}
11993
11994 // This pattern is automatically generated from aarch64_ad.m4
11995 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
11996 instruct AndL_reg_RotateRight_reg(iRegLNoSp dst,
11997 iRegL src1, iRegL src2,
11998 immI src3) %{
11999 match(Set dst (AndL src1 (RotateRight src2 src3)));
12000
12001 ins_cost(1.9 * INSN_COST);
12002 format %{ "andr $dst, $src1, $src2, ROR $src3" %}
12003
12004 ins_encode %{
12005 __ andr(as_Register($dst$$reg),
12006 as_Register($src1$$reg),
12007 as_Register($src2$$reg),
12008 Assembler::ROR,
12009 $src3$$constant & 0x3f);
12010 %}
12011
12012 ins_pipe(ialu_reg_reg_shift);
12013 %}
12014
12015 // This pattern is automatically generated from aarch64_ad.m4
12016 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
12017 instruct XorI_reg_URShift_reg(iRegINoSp dst,
12018 iRegIorL2I src1, iRegIorL2I src2,
12019 immI src3) %{
12020 match(Set dst (XorI src1 (URShiftI src2 src3)));
12021
12022 ins_cost(1.9 * INSN_COST);
12023 format %{ "eorw $dst, $src1, $src2, LSR $src3" %}
12024
12025 ins_encode %{
12026 __ eorw(as_Register($dst$$reg),
12027 as_Register($src1$$reg),
12028 as_Register($src2$$reg),
12029 Assembler::LSR,
12030 $src3$$constant & 0x1f);
12031 %}
12032
12033 ins_pipe(ialu_reg_reg_shift);
12034 %}
12035
12036 // This pattern is automatically generated from aarch64_ad.m4
12037 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
12038 instruct XorL_reg_URShift_reg(iRegLNoSp dst,
12039 iRegL src1, iRegL src2,
12040 immI src3) %{
12041 match(Set dst (XorL src1 (URShiftL src2 src3)));
12042
12043 ins_cost(1.9 * INSN_COST);
12044 format %{ "eor $dst, $src1, $src2, LSR $src3" %}
12045
12046 ins_encode %{
12047 __ eor(as_Register($dst$$reg),
12048 as_Register($src1$$reg),
12049 as_Register($src2$$reg),
12050 Assembler::LSR,
12051 $src3$$constant & 0x3f);
12052 %}
12053
12054 ins_pipe(ialu_reg_reg_shift);
12055 %}
12056
12057 // This pattern is automatically generated from aarch64_ad.m4
12058 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
12059 instruct XorI_reg_RShift_reg(iRegINoSp dst,
12060 iRegIorL2I src1, iRegIorL2I src2,
12061 immI src3) %{
12062 match(Set dst (XorI src1 (RShiftI src2 src3)));
12063
12064 ins_cost(1.9 * INSN_COST);
12065 format %{ "eorw $dst, $src1, $src2, ASR $src3" %}
12066
12067 ins_encode %{
12068 __ eorw(as_Register($dst$$reg),
12069 as_Register($src1$$reg),
12070 as_Register($src2$$reg),
12071 Assembler::ASR,
12072 $src3$$constant & 0x1f);
12073 %}
12074
12075 ins_pipe(ialu_reg_reg_shift);
12076 %}
12077
12078 // This pattern is automatically generated from aarch64_ad.m4
12079 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
12080 instruct XorL_reg_RShift_reg(iRegLNoSp dst,
12081 iRegL src1, iRegL src2,
12082 immI src3) %{
12083 match(Set dst (XorL src1 (RShiftL src2 src3)));
12084
12085 ins_cost(1.9 * INSN_COST);
12086 format %{ "eor $dst, $src1, $src2, ASR $src3" %}
12087
12088 ins_encode %{
12089 __ eor(as_Register($dst$$reg),
12090 as_Register($src1$$reg),
12091 as_Register($src2$$reg),
12092 Assembler::ASR,
12093 $src3$$constant & 0x3f);
12094 %}
12095
12096 ins_pipe(ialu_reg_reg_shift);
12097 %}
12098
12099 // This pattern is automatically generated from aarch64_ad.m4
12100 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
12101 instruct XorI_reg_LShift_reg(iRegINoSp dst,
12102 iRegIorL2I src1, iRegIorL2I src2,
12103 immI src3) %{
12104 match(Set dst (XorI src1 (LShiftI src2 src3)));
12105
12106 ins_cost(1.9 * INSN_COST);
12107 format %{ "eorw $dst, $src1, $src2, LSL $src3" %}
12108
12109 ins_encode %{
12110 __ eorw(as_Register($dst$$reg),
12111 as_Register($src1$$reg),
12112 as_Register($src2$$reg),
12113 Assembler::LSL,
12114 $src3$$constant & 0x1f);
12115 %}
12116
12117 ins_pipe(ialu_reg_reg_shift);
12118 %}
12119
12120 // This pattern is automatically generated from aarch64_ad.m4
12121 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
12122 instruct XorL_reg_LShift_reg(iRegLNoSp dst,
12123 iRegL src1, iRegL src2,
12124 immI src3) %{
12125 match(Set dst (XorL src1 (LShiftL src2 src3)));
12126
12127 ins_cost(1.9 * INSN_COST);
12128 format %{ "eor $dst, $src1, $src2, LSL $src3" %}
12129
12130 ins_encode %{
12131 __ eor(as_Register($dst$$reg),
12132 as_Register($src1$$reg),
12133 as_Register($src2$$reg),
12134 Assembler::LSL,
12135 $src3$$constant & 0x3f);
12136 %}
12137
12138 ins_pipe(ialu_reg_reg_shift);
12139 %}
12140
12141 // This pattern is automatically generated from aarch64_ad.m4
12142 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
12143 instruct XorI_reg_RotateRight_reg(iRegINoSp dst,
12144 iRegIorL2I src1, iRegIorL2I src2,
12145 immI src3) %{
12146 match(Set dst (XorI src1 (RotateRight src2 src3)));
12147
12148 ins_cost(1.9 * INSN_COST);
12149 format %{ "eorw $dst, $src1, $src2, ROR $src3" %}
12150
12151 ins_encode %{
12152 __ eorw(as_Register($dst$$reg),
12153 as_Register($src1$$reg),
12154 as_Register($src2$$reg),
12155 Assembler::ROR,
12156 $src3$$constant & 0x1f);
12157 %}
12158
12159 ins_pipe(ialu_reg_reg_shift);
12160 %}
12161
12162 // This pattern is automatically generated from aarch64_ad.m4
12163 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
12164 instruct XorL_reg_RotateRight_reg(iRegLNoSp dst,
12165 iRegL src1, iRegL src2,
12166 immI src3) %{
12167 match(Set dst (XorL src1 (RotateRight src2 src3)));
12168
12169 ins_cost(1.9 * INSN_COST);
12170 format %{ "eor $dst, $src1, $src2, ROR $src3" %}
12171
12172 ins_encode %{
12173 __ eor(as_Register($dst$$reg),
12174 as_Register($src1$$reg),
12175 as_Register($src2$$reg),
12176 Assembler::ROR,
12177 $src3$$constant & 0x3f);
12178 %}
12179
12180 ins_pipe(ialu_reg_reg_shift);
12181 %}
12182
12183 // This pattern is automatically generated from aarch64_ad.m4
12184 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
12185 instruct OrI_reg_URShift_reg(iRegINoSp dst,
12186 iRegIorL2I src1, iRegIorL2I src2,
12187 immI src3) %{
12188 match(Set dst (OrI src1 (URShiftI src2 src3)));
12189
12190 ins_cost(1.9 * INSN_COST);
12191 format %{ "orrw $dst, $src1, $src2, LSR $src3" %}
12192
12193 ins_encode %{
12194 __ orrw(as_Register($dst$$reg),
12195 as_Register($src1$$reg),
12196 as_Register($src2$$reg),
12197 Assembler::LSR,
12198 $src3$$constant & 0x1f);
12199 %}
12200
12201 ins_pipe(ialu_reg_reg_shift);
12202 %}
12203
12204 // This pattern is automatically generated from aarch64_ad.m4
12205 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
12206 instruct OrL_reg_URShift_reg(iRegLNoSp dst,
12207 iRegL src1, iRegL src2,
12208 immI src3) %{
12209 match(Set dst (OrL src1 (URShiftL src2 src3)));
12210
12211 ins_cost(1.9 * INSN_COST);
12212 format %{ "orr $dst, $src1, $src2, LSR $src3" %}
12213
12214 ins_encode %{
12215 __ orr(as_Register($dst$$reg),
12216 as_Register($src1$$reg),
12217 as_Register($src2$$reg),
12218 Assembler::LSR,
12219 $src3$$constant & 0x3f);
12220 %}
12221
12222 ins_pipe(ialu_reg_reg_shift);
12223 %}
12224
12225 // This pattern is automatically generated from aarch64_ad.m4
12226 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
12227 instruct OrI_reg_RShift_reg(iRegINoSp dst,
12228 iRegIorL2I src1, iRegIorL2I src2,
12229 immI src3) %{
12230 match(Set dst (OrI src1 (RShiftI src2 src3)));
12231
12232 ins_cost(1.9 * INSN_COST);
12233 format %{ "orrw $dst, $src1, $src2, ASR $src3" %}
12234
12235 ins_encode %{
12236 __ orrw(as_Register($dst$$reg),
12237 as_Register($src1$$reg),
12238 as_Register($src2$$reg),
12239 Assembler::ASR,
12240 $src3$$constant & 0x1f);
12241 %}
12242
12243 ins_pipe(ialu_reg_reg_shift);
12244 %}
12245
12246 // This pattern is automatically generated from aarch64_ad.m4
12247 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
12248 instruct OrL_reg_RShift_reg(iRegLNoSp dst,
12249 iRegL src1, iRegL src2,
12250 immI src3) %{
12251 match(Set dst (OrL src1 (RShiftL src2 src3)));
12252
12253 ins_cost(1.9 * INSN_COST);
12254 format %{ "orr $dst, $src1, $src2, ASR $src3" %}
12255
12256 ins_encode %{
12257 __ orr(as_Register($dst$$reg),
12258 as_Register($src1$$reg),
12259 as_Register($src2$$reg),
12260 Assembler::ASR,
12261 $src3$$constant & 0x3f);
12262 %}
12263
12264 ins_pipe(ialu_reg_reg_shift);
12265 %}
12266
12267 // This pattern is automatically generated from aarch64_ad.m4
12268 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
12269 instruct OrI_reg_LShift_reg(iRegINoSp dst,
12270 iRegIorL2I src1, iRegIorL2I src2,
12271 immI src3) %{
12272 match(Set dst (OrI src1 (LShiftI src2 src3)));
12273
12274 ins_cost(1.9 * INSN_COST);
12275 format %{ "orrw $dst, $src1, $src2, LSL $src3" %}
12276
12277 ins_encode %{
12278 __ orrw(as_Register($dst$$reg),
12279 as_Register($src1$$reg),
12280 as_Register($src2$$reg),
12281 Assembler::LSL,
12282 $src3$$constant & 0x1f);
12283 %}
12284
12285 ins_pipe(ialu_reg_reg_shift);
12286 %}
12287
12288 // This pattern is automatically generated from aarch64_ad.m4
12289 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
12290 instruct OrL_reg_LShift_reg(iRegLNoSp dst,
12291 iRegL src1, iRegL src2,
12292 immI src3) %{
12293 match(Set dst (OrL src1 (LShiftL src2 src3)));
12294
12295 ins_cost(1.9 * INSN_COST);
12296 format %{ "orr $dst, $src1, $src2, LSL $src3" %}
12297
12298 ins_encode %{
12299 __ orr(as_Register($dst$$reg),
12300 as_Register($src1$$reg),
12301 as_Register($src2$$reg),
12302 Assembler::LSL,
12303 $src3$$constant & 0x3f);
12304 %}
12305
12306 ins_pipe(ialu_reg_reg_shift);
12307 %}
12308
12309 // This pattern is automatically generated from aarch64_ad.m4
12310 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
12311 instruct OrI_reg_RotateRight_reg(iRegINoSp dst,
12312 iRegIorL2I src1, iRegIorL2I src2,
12313 immI src3) %{
12314 match(Set dst (OrI src1 (RotateRight src2 src3)));
12315
12316 ins_cost(1.9 * INSN_COST);
12317 format %{ "orrw $dst, $src1, $src2, ROR $src3" %}
12318
12319 ins_encode %{
12320 __ orrw(as_Register($dst$$reg),
12321 as_Register($src1$$reg),
12322 as_Register($src2$$reg),
12323 Assembler::ROR,
12324 $src3$$constant & 0x1f);
12325 %}
12326
12327 ins_pipe(ialu_reg_reg_shift);
12328 %}
12329
12330 // This pattern is automatically generated from aarch64_ad.m4
12331 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
12332 instruct OrL_reg_RotateRight_reg(iRegLNoSp dst,
12333 iRegL src1, iRegL src2,
12334 immI src3) %{
12335 match(Set dst (OrL src1 (RotateRight src2 src3)));
12336
12337 ins_cost(1.9 * INSN_COST);
12338 format %{ "orr $dst, $src1, $src2, ROR $src3" %}
12339
12340 ins_encode %{
12341 __ orr(as_Register($dst$$reg),
12342 as_Register($src1$$reg),
12343 as_Register($src2$$reg),
12344 Assembler::ROR,
12345 $src3$$constant & 0x3f);
12346 %}
12347
12348 ins_pipe(ialu_reg_reg_shift);
12349 %}
12350
12351 // This pattern is automatically generated from aarch64_ad.m4
12352 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
12353 instruct AddI_reg_URShift_reg(iRegINoSp dst,
12354 iRegIorL2I src1, iRegIorL2I src2,
12355 immI src3) %{
12356 match(Set dst (AddI src1 (URShiftI src2 src3)));
12357
12358 ins_cost(1.9 * INSN_COST);
12359 format %{ "addw $dst, $src1, $src2, LSR $src3" %}
12360
12361 ins_encode %{
12362 __ addw(as_Register($dst$$reg),
12363 as_Register($src1$$reg),
12364 as_Register($src2$$reg),
12365 Assembler::LSR,
12366 $src3$$constant & 0x1f);
12367 %}
12368
12369 ins_pipe(ialu_reg_reg_shift);
12370 %}
12371
12372 // This pattern is automatically generated from aarch64_ad.m4
12373 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
12374 instruct AddL_reg_URShift_reg(iRegLNoSp dst,
12375 iRegL src1, iRegL src2,
12376 immI src3) %{
12377 match(Set dst (AddL src1 (URShiftL src2 src3)));
12378
12379 ins_cost(1.9 * INSN_COST);
12380 format %{ "add $dst, $src1, $src2, LSR $src3" %}
12381
12382 ins_encode %{
12383 __ add(as_Register($dst$$reg),
12384 as_Register($src1$$reg),
12385 as_Register($src2$$reg),
12386 Assembler::LSR,
12387 $src3$$constant & 0x3f);
12388 %}
12389
12390 ins_pipe(ialu_reg_reg_shift);
12391 %}
12392
12393 // This pattern is automatically generated from aarch64_ad.m4
12394 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
12395 instruct AddI_reg_RShift_reg(iRegINoSp dst,
12396 iRegIorL2I src1, iRegIorL2I src2,
12397 immI src3) %{
12398 match(Set dst (AddI src1 (RShiftI src2 src3)));
12399
12400 ins_cost(1.9 * INSN_COST);
12401 format %{ "addw $dst, $src1, $src2, ASR $src3" %}
12402
12403 ins_encode %{
12404 __ addw(as_Register($dst$$reg),
12405 as_Register($src1$$reg),
12406 as_Register($src2$$reg),
12407 Assembler::ASR,
12408 $src3$$constant & 0x1f);
12409 %}
12410
12411 ins_pipe(ialu_reg_reg_shift);
12412 %}
12413
12414 // This pattern is automatically generated from aarch64_ad.m4
12415 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
12416 instruct AddL_reg_RShift_reg(iRegLNoSp dst,
12417 iRegL src1, iRegL src2,
12418 immI src3) %{
12419 match(Set dst (AddL src1 (RShiftL src2 src3)));
12420
12421 ins_cost(1.9 * INSN_COST);
12422 format %{ "add $dst, $src1, $src2, ASR $src3" %}
12423
12424 ins_encode %{
12425 __ add(as_Register($dst$$reg),
12426 as_Register($src1$$reg),
12427 as_Register($src2$$reg),
12428 Assembler::ASR,
12429 $src3$$constant & 0x3f);
12430 %}
12431
12432 ins_pipe(ialu_reg_reg_shift);
12433 %}
12434
12435 // This pattern is automatically generated from aarch64_ad.m4
12436 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
12437 instruct AddI_reg_LShift_reg(iRegINoSp dst,
12438 iRegIorL2I src1, iRegIorL2I src2,
12439 immI src3) %{
12440 match(Set dst (AddI src1 (LShiftI src2 src3)));
12441
12442 ins_cost(1.9 * INSN_COST);
12443 format %{ "addw $dst, $src1, $src2, LSL $src3" %}
12444
12445 ins_encode %{
12446 __ addw(as_Register($dst$$reg),
12447 as_Register($src1$$reg),
12448 as_Register($src2$$reg),
12449 Assembler::LSL,
12450 $src3$$constant & 0x1f);
12451 %}
12452
12453 ins_pipe(ialu_reg_reg_shift);
12454 %}
12455
12456 // This pattern is automatically generated from aarch64_ad.m4
12457 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
12458 instruct AddL_reg_LShift_reg(iRegLNoSp dst,
12459 iRegL src1, iRegL src2,
12460 immI src3) %{
12461 match(Set dst (AddL src1 (LShiftL src2 src3)));
12462
12463 ins_cost(1.9 * INSN_COST);
12464 format %{ "add $dst, $src1, $src2, LSL $src3" %}
12465
12466 ins_encode %{
12467 __ add(as_Register($dst$$reg),
12468 as_Register($src1$$reg),
12469 as_Register($src2$$reg),
12470 Assembler::LSL,
12471 $src3$$constant & 0x3f);
12472 %}
12473
12474 ins_pipe(ialu_reg_reg_shift);
12475 %}
12476
12477 // This pattern is automatically generated from aarch64_ad.m4
12478 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
12479 instruct SubI_reg_URShift_reg(iRegINoSp dst,
12480 iRegIorL2I src1, iRegIorL2I src2,
12481 immI src3) %{
12482 match(Set dst (SubI src1 (URShiftI src2 src3)));
12483
12484 ins_cost(1.9 * INSN_COST);
12485 format %{ "subw $dst, $src1, $src2, LSR $src3" %}
12486
12487 ins_encode %{
12488 __ subw(as_Register($dst$$reg),
12489 as_Register($src1$$reg),
12490 as_Register($src2$$reg),
12491 Assembler::LSR,
12492 $src3$$constant & 0x1f);
12493 %}
12494
12495 ins_pipe(ialu_reg_reg_shift);
12496 %}
12497
12498 // This pattern is automatically generated from aarch64_ad.m4
12499 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
12500 instruct SubL_reg_URShift_reg(iRegLNoSp dst,
12501 iRegL src1, iRegL src2,
12502 immI src3) %{
12503 match(Set dst (SubL src1 (URShiftL src2 src3)));
12504
12505 ins_cost(1.9 * INSN_COST);
12506 format %{ "sub $dst, $src1, $src2, LSR $src3" %}
12507
12508 ins_encode %{
12509 __ sub(as_Register($dst$$reg),
12510 as_Register($src1$$reg),
12511 as_Register($src2$$reg),
12512 Assembler::LSR,
12513 $src3$$constant & 0x3f);
12514 %}
12515
12516 ins_pipe(ialu_reg_reg_shift);
12517 %}
12518
12519 // This pattern is automatically generated from aarch64_ad.m4
12520 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
12521 instruct SubI_reg_RShift_reg(iRegINoSp dst,
12522 iRegIorL2I src1, iRegIorL2I src2,
12523 immI src3) %{
12524 match(Set dst (SubI src1 (RShiftI src2 src3)));
12525
12526 ins_cost(1.9 * INSN_COST);
12527 format %{ "subw $dst, $src1, $src2, ASR $src3" %}
12528
12529 ins_encode %{
12530 __ subw(as_Register($dst$$reg),
12531 as_Register($src1$$reg),
12532 as_Register($src2$$reg),
12533 Assembler::ASR,
12534 $src3$$constant & 0x1f);
12535 %}
12536
12537 ins_pipe(ialu_reg_reg_shift);
12538 %}
12539
12540 // This pattern is automatically generated from aarch64_ad.m4
12541 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
12542 instruct SubL_reg_RShift_reg(iRegLNoSp dst,
12543 iRegL src1, iRegL src2,
12544 immI src3) %{
12545 match(Set dst (SubL src1 (RShiftL src2 src3)));
12546
12547 ins_cost(1.9 * INSN_COST);
12548 format %{ "sub $dst, $src1, $src2, ASR $src3" %}
12549
12550 ins_encode %{
12551 __ sub(as_Register($dst$$reg),
12552 as_Register($src1$$reg),
12553 as_Register($src2$$reg),
12554 Assembler::ASR,
12555 $src3$$constant & 0x3f);
12556 %}
12557
12558 ins_pipe(ialu_reg_reg_shift);
12559 %}
12560
12561 // This pattern is automatically generated from aarch64_ad.m4
12562 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
12563 instruct SubI_reg_LShift_reg(iRegINoSp dst,
12564 iRegIorL2I src1, iRegIorL2I src2,
12565 immI src3) %{
12566 match(Set dst (SubI src1 (LShiftI src2 src3)));
12567
12568 ins_cost(1.9 * INSN_COST);
12569 format %{ "subw $dst, $src1, $src2, LSL $src3" %}
12570
12571 ins_encode %{
12572 __ subw(as_Register($dst$$reg),
12573 as_Register($src1$$reg),
12574 as_Register($src2$$reg),
12575 Assembler::LSL,
12576 $src3$$constant & 0x1f);
12577 %}
12578
12579 ins_pipe(ialu_reg_reg_shift);
12580 %}
12581
12582 // This pattern is automatically generated from aarch64_ad.m4
12583 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
12584 instruct SubL_reg_LShift_reg(iRegLNoSp dst,
12585 iRegL src1, iRegL src2,
12586 immI src3) %{
12587 match(Set dst (SubL src1 (LShiftL src2 src3)));
12588
12589 ins_cost(1.9 * INSN_COST);
12590 format %{ "sub $dst, $src1, $src2, LSL $src3" %}
12591
12592 ins_encode %{
12593 __ sub(as_Register($dst$$reg),
12594 as_Register($src1$$reg),
12595 as_Register($src2$$reg),
12596 Assembler::LSL,
12597 $src3$$constant & 0x3f);
12598 %}
12599
12600 ins_pipe(ialu_reg_reg_shift);
12601 %}
12602
12603 // This pattern is automatically generated from aarch64_ad.m4
12604 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
12605
12606 // Shift Left followed by Shift Right.
12607 // This idiom is used by the compiler for the i2b bytecode etc.
12608 instruct sbfmL(iRegLNoSp dst, iRegL src, immI lshift_count, immI rshift_count)
12609 %{
12610 match(Set dst (RShiftL (LShiftL src lshift_count) rshift_count));
12611 ins_cost(INSN_COST * 2);
12612 format %{ "sbfm $dst, $src, $rshift_count - $lshift_count, #63 - $lshift_count" %}
12613 ins_encode %{
12614 int lshift = $lshift_count$$constant & 63;
12615 int rshift = $rshift_count$$constant & 63;
12616 int s = 63 - lshift;
12617 int r = (rshift - lshift) & 63;
12618 __ sbfm(as_Register($dst$$reg),
12619 as_Register($src$$reg),
12620 r, s);
12621 %}
12622
12623 ins_pipe(ialu_reg_shift);
12624 %}
12625
12626 // This pattern is automatically generated from aarch64_ad.m4
12627 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
12628
12629 // Shift Left followed by Shift Right.
12630 // This idiom is used by the compiler for the i2b bytecode etc.
12631 instruct sbfmwI(iRegINoSp dst, iRegIorL2I src, immI lshift_count, immI rshift_count)
12632 %{
12633 match(Set dst (RShiftI (LShiftI src lshift_count) rshift_count));
12634 ins_cost(INSN_COST * 2);
12635 format %{ "sbfmw $dst, $src, $rshift_count - $lshift_count, #31 - $lshift_count" %}
12636 ins_encode %{
12637 int lshift = $lshift_count$$constant & 31;
12638 int rshift = $rshift_count$$constant & 31;
12639 int s = 31 - lshift;
12640 int r = (rshift - lshift) & 31;
12641 __ sbfmw(as_Register($dst$$reg),
12642 as_Register($src$$reg),
12643 r, s);
12644 %}
12645
12646 ins_pipe(ialu_reg_shift);
12647 %}
12648
12649 // This pattern is automatically generated from aarch64_ad.m4
12650 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
12651
12652 // Shift Left followed by Shift Right.
12653 // This idiom is used by the compiler for the i2b bytecode etc.
12654 instruct ubfmL(iRegLNoSp dst, iRegL src, immI lshift_count, immI rshift_count)
12655 %{
12656 match(Set dst (URShiftL (LShiftL src lshift_count) rshift_count));
12657 ins_cost(INSN_COST * 2);
12658 format %{ "ubfm $dst, $src, $rshift_count - $lshift_count, #63 - $lshift_count" %}
12659 ins_encode %{
12660 int lshift = $lshift_count$$constant & 63;
12661 int rshift = $rshift_count$$constant & 63;
12662 int s = 63 - lshift;
12663 int r = (rshift - lshift) & 63;
12664 __ ubfm(as_Register($dst$$reg),
12665 as_Register($src$$reg),
12666 r, s);
12667 %}
12668
12669 ins_pipe(ialu_reg_shift);
12670 %}
12671
12672 // This pattern is automatically generated from aarch64_ad.m4
12673 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
12674
12675 // Shift Left followed by Shift Right.
12676 // This idiom is used by the compiler for the i2b bytecode etc.
12677 instruct ubfmwI(iRegINoSp dst, iRegIorL2I src, immI lshift_count, immI rshift_count)
12678 %{
12679 match(Set dst (URShiftI (LShiftI src lshift_count) rshift_count));
12680 ins_cost(INSN_COST * 2);
12681 format %{ "ubfmw $dst, $src, $rshift_count - $lshift_count, #31 - $lshift_count" %}
12682 ins_encode %{
12683 int lshift = $lshift_count$$constant & 31;
12684 int rshift = $rshift_count$$constant & 31;
12685 int s = 31 - lshift;
12686 int r = (rshift - lshift) & 31;
12687 __ ubfmw(as_Register($dst$$reg),
12688 as_Register($src$$reg),
12689 r, s);
12690 %}
12691
12692 ins_pipe(ialu_reg_shift);
12693 %}
12694
12695 // Bitfield extract with shift & mask
12696
12697 // This pattern is automatically generated from aarch64_ad.m4
12698 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
12699 instruct ubfxwI(iRegINoSp dst, iRegIorL2I src, immI rshift, immI_bitmask mask)
12700 %{
12701 match(Set dst (AndI (URShiftI src rshift) mask));
12702 // Make sure we are not going to exceed what ubfxw can do.
12703 predicate((exact_log2(n->in(2)->get_int() + 1) + (n->in(1)->in(2)->get_int() & 31)) <= (31 + 1));
12704
12705 ins_cost(INSN_COST);
12706 format %{ "ubfxw $dst, $src, $rshift, $mask" %}
12707 ins_encode %{
12708 int rshift = $rshift$$constant & 31;
12709 intptr_t mask = $mask$$constant;
12710 int width = exact_log2(mask+1);
12711 __ ubfxw(as_Register($dst$$reg),
12712 as_Register($src$$reg), rshift, width);
12713 %}
12714 ins_pipe(ialu_reg_shift);
12715 %}
12716
12717 // This pattern is automatically generated from aarch64_ad.m4
12718 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
12719 instruct ubfxL(iRegLNoSp dst, iRegL src, immI rshift, immL_bitmask mask)
12720 %{
12721 match(Set dst (AndL (URShiftL src rshift) mask));
12722 // Make sure we are not going to exceed what ubfx can do.
12723 predicate((exact_log2_long(n->in(2)->get_long() + 1) + (n->in(1)->in(2)->get_int() & 63)) <= (63 + 1));
12724
12725 ins_cost(INSN_COST);
12726 format %{ "ubfx $dst, $src, $rshift, $mask" %}
12727 ins_encode %{
12728 int rshift = $rshift$$constant & 63;
12729 intptr_t mask = $mask$$constant;
12730 int width = exact_log2_long(mask+1);
12731 __ ubfx(as_Register($dst$$reg),
12732 as_Register($src$$reg), rshift, width);
12733 %}
12734 ins_pipe(ialu_reg_shift);
12735 %}
12736
12737
12738 // This pattern is automatically generated from aarch64_ad.m4
12739 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
12740
12741 // We can use ubfx when extending an And with a mask when we know mask
12742 // is positive. We know that because immI_bitmask guarantees it.
12743 instruct ubfxIConvI2L(iRegLNoSp dst, iRegIorL2I src, immI rshift, immI_bitmask mask)
12744 %{
12745 match(Set dst (ConvI2L (AndI (URShiftI src rshift) mask)));
12746 // Make sure we are not going to exceed what ubfxw can do.
12747 predicate((exact_log2(n->in(1)->in(2)->get_int() + 1) + (n->in(1)->in(1)->in(2)->get_int() & 31)) <= (31 + 1));
12748
12749 ins_cost(INSN_COST * 2);
12750 format %{ "ubfx $dst, $src, $rshift, $mask" %}
12751 ins_encode %{
12752 int rshift = $rshift$$constant & 31;
12753 intptr_t mask = $mask$$constant;
12754 int width = exact_log2(mask+1);
12755 __ ubfx(as_Register($dst$$reg),
12756 as_Register($src$$reg), rshift, width);
12757 %}
12758 ins_pipe(ialu_reg_shift);
12759 %}
12760
12761
12762 // This pattern is automatically generated from aarch64_ad.m4
12763 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
12764
12765 // We can use ubfiz when masking by a positive number and then left shifting the result.
12766 // We know that the mask is positive because immI_bitmask guarantees it.
12767 instruct ubfizwI(iRegINoSp dst, iRegIorL2I src, immI lshift, immI_bitmask mask)
12768 %{
12769 match(Set dst (LShiftI (AndI src mask) lshift));
12770 predicate((exact_log2(n->in(1)->in(2)->get_int() + 1) + (n->in(2)->get_int() & 31)) <= (31 + 1));
12771
12772 ins_cost(INSN_COST);
12773 format %{ "ubfizw $dst, $src, $lshift, $mask" %}
12774 ins_encode %{
12775 int lshift = $lshift$$constant & 31;
12776 intptr_t mask = $mask$$constant;
12777 int width = exact_log2(mask+1);
12778 __ ubfizw(as_Register($dst$$reg),
12779 as_Register($src$$reg), lshift, width);
12780 %}
12781 ins_pipe(ialu_reg_shift);
12782 %}
12783
12784 // This pattern is automatically generated from aarch64_ad.m4
12785 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
12786
12787 // We can use ubfiz when masking by a positive number and then left shifting the result.
12788 // We know that the mask is positive because immL_bitmask guarantees it.
12789 instruct ubfizL(iRegLNoSp dst, iRegL src, immI lshift, immL_bitmask mask)
12790 %{
12791 match(Set dst (LShiftL (AndL src mask) lshift));
12792 predicate((exact_log2_long(n->in(1)->in(2)->get_long() + 1) + (n->in(2)->get_int() & 63)) <= (63 + 1));
12793
12794 ins_cost(INSN_COST);
12795 format %{ "ubfiz $dst, $src, $lshift, $mask" %}
12796 ins_encode %{
12797 int lshift = $lshift$$constant & 63;
12798 intptr_t mask = $mask$$constant;
12799 int width = exact_log2_long(mask+1);
12800 __ ubfiz(as_Register($dst$$reg),
12801 as_Register($src$$reg), lshift, width);
12802 %}
12803 ins_pipe(ialu_reg_shift);
12804 %}
12805
12806 // This pattern is automatically generated from aarch64_ad.m4
12807 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
12808
12809 // We can use ubfiz when masking by a positive number and then left shifting the result.
12810 // We know that the mask is positive because immI_bitmask guarantees it.
12811 instruct ubfizwIConvI2L(iRegLNoSp dst, iRegIorL2I src, immI lshift, immI_bitmask mask)
12812 %{
12813 match(Set dst (ConvI2L (LShiftI (AndI src mask) lshift)));
12814 predicate((exact_log2(n->in(1)->in(1)->in(2)->get_int() + 1) + (n->in(1)->in(2)->get_int() & 31)) <= 31);
12815
12816 ins_cost(INSN_COST);
12817 format %{ "ubfizw $dst, $src, $lshift, $mask" %}
12818 ins_encode %{
12819 int lshift = $lshift$$constant & 31;
12820 intptr_t mask = $mask$$constant;
12821 int width = exact_log2(mask+1);
12822 __ ubfizw(as_Register($dst$$reg),
12823 as_Register($src$$reg), lshift, width);
12824 %}
12825 ins_pipe(ialu_reg_shift);
12826 %}
12827
12828 // This pattern is automatically generated from aarch64_ad.m4
12829 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
12830
12831 // We can use ubfiz when masking by a positive number and then left shifting the result.
12832 // We know that the mask is positive because immL_bitmask guarantees it.
12833 instruct ubfizLConvL2I(iRegINoSp dst, iRegL src, immI lshift, immL_positive_bitmaskI mask)
12834 %{
12835 match(Set dst (ConvL2I (LShiftL (AndL src mask) lshift)));
12836 predicate((exact_log2_long(n->in(1)->in(1)->in(2)->get_long() + 1) + (n->in(1)->in(2)->get_int() & 63)) <= 31);
12837
12838 ins_cost(INSN_COST);
12839 format %{ "ubfiz $dst, $src, $lshift, $mask" %}
12840 ins_encode %{
12841 int lshift = $lshift$$constant & 63;
12842 intptr_t mask = $mask$$constant;
12843 int width = exact_log2_long(mask+1);
12844 __ ubfiz(as_Register($dst$$reg),
12845 as_Register($src$$reg), lshift, width);
12846 %}
12847 ins_pipe(ialu_reg_shift);
12848 %}
12849
12850
12851 // This pattern is automatically generated from aarch64_ad.m4
12852 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
12853
12854 // If there is a convert I to L block between and AndI and a LShiftL, we can also match ubfiz
12855 instruct ubfizIConvI2L(iRegLNoSp dst, iRegIorL2I src, immI lshift, immI_bitmask mask)
12856 %{
12857 match(Set dst (LShiftL (ConvI2L (AndI src mask)) lshift));
12858 predicate((exact_log2(n->in(1)->in(1)->in(2)->get_int() + 1) + (n->in(2)->get_int() & 63)) <= (63 + 1));
12859
12860 ins_cost(INSN_COST);
12861 format %{ "ubfiz $dst, $src, $lshift, $mask" %}
12862 ins_encode %{
12863 int lshift = $lshift$$constant & 63;
12864 intptr_t mask = $mask$$constant;
12865 int width = exact_log2(mask+1);
12866 __ ubfiz(as_Register($dst$$reg),
12867 as_Register($src$$reg), lshift, width);
12868 %}
12869 ins_pipe(ialu_reg_shift);
12870 %}
12871
12872 // This pattern is automatically generated from aarch64_ad.m4
12873 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
12874
12875 // If there is a convert L to I block between and AndL and a LShiftI, we can also match ubfiz
12876 instruct ubfizLConvL2Ix(iRegINoSp dst, iRegL src, immI lshift, immL_positive_bitmaskI mask)
12877 %{
12878 match(Set dst (LShiftI (ConvL2I (AndL src mask)) lshift));
12879 predicate((exact_log2_long(n->in(1)->in(1)->in(2)->get_long() + 1) + (n->in(2)->get_int() & 31)) <= 31);
12880
12881 ins_cost(INSN_COST);
12882 format %{ "ubfiz $dst, $src, $lshift, $mask" %}
12883 ins_encode %{
12884 int lshift = $lshift$$constant & 31;
12885 intptr_t mask = $mask$$constant;
12886 int width = exact_log2(mask+1);
12887 __ ubfiz(as_Register($dst$$reg),
12888 as_Register($src$$reg), lshift, width);
12889 %}
12890 ins_pipe(ialu_reg_shift);
12891 %}
12892
12893 // This pattern is automatically generated from aarch64_ad.m4
12894 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
12895
12896 // Can skip int2long conversions after AND with small bitmask
12897 instruct ubfizIConvI2LAndI(iRegLNoSp dst, iRegI src, immI_bitmask msk)
12898 %{
12899 match(Set dst (ConvI2L (AndI src msk)));
12900 ins_cost(INSN_COST);
12901 format %{ "ubfiz $dst, $src, 0, exact_log2($msk + 1) " %}
12902 ins_encode %{
12903 __ ubfiz(as_Register($dst$$reg), as_Register($src$$reg), 0, exact_log2($msk$$constant + 1));
12904 %}
12905 ins_pipe(ialu_reg_shift);
12906 %}
12907
12908
12909 // Rotations
12910
12911 // This pattern is automatically generated from aarch64_ad.m4
12912 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
12913 instruct extrOrL(iRegLNoSp dst, iRegL src1, iRegL src2, immI lshift, immI rshift, rFlagsReg cr)
12914 %{
12915 match(Set dst (OrL (LShiftL src1 lshift) (URShiftL src2 rshift)));
12916 predicate(0 == (((n->in(1)->in(2)->get_int() & 63) + (n->in(2)->in(2)->get_int() & 63)) & 63));
12917
12918 ins_cost(INSN_COST);
12919 format %{ "extr $dst, $src1, $src2, #$rshift" %}
12920
12921 ins_encode %{
12922 __ extr(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg),
12923 $rshift$$constant & 63);
12924 %}
12925 ins_pipe(ialu_reg_reg_extr);
12926 %}
12927
12928
12929 // This pattern is automatically generated from aarch64_ad.m4
12930 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
12931 instruct extrOrI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI lshift, immI rshift, rFlagsReg cr)
12932 %{
12933 match(Set dst (OrI (LShiftI src1 lshift) (URShiftI src2 rshift)));
12934 predicate(0 == (((n->in(1)->in(2)->get_int() & 31) + (n->in(2)->in(2)->get_int() & 31)) & 31));
12935
12936 ins_cost(INSN_COST);
12937 format %{ "extr $dst, $src1, $src2, #$rshift" %}
12938
12939 ins_encode %{
12940 __ extrw(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg),
12941 $rshift$$constant & 31);
12942 %}
12943 ins_pipe(ialu_reg_reg_extr);
12944 %}
12945
12946
12947 // This pattern is automatically generated from aarch64_ad.m4
12948 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
12949 instruct extrAddL(iRegLNoSp dst, iRegL src1, iRegL src2, immI lshift, immI rshift, rFlagsReg cr)
12950 %{
12951 match(Set dst (AddL (LShiftL src1 lshift) (URShiftL src2 rshift)));
12952 predicate(0 == (((n->in(1)->in(2)->get_int() & 63) + (n->in(2)->in(2)->get_int() & 63)) & 63));
12953
12954 ins_cost(INSN_COST);
12955 format %{ "extr $dst, $src1, $src2, #$rshift" %}
12956
12957 ins_encode %{
12958 __ extr(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg),
12959 $rshift$$constant & 63);
12960 %}
12961 ins_pipe(ialu_reg_reg_extr);
12962 %}
12963
12964
12965 // This pattern is automatically generated from aarch64_ad.m4
12966 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
12967 instruct extrAddI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI lshift, immI rshift, rFlagsReg cr)
12968 %{
12969 match(Set dst (AddI (LShiftI src1 lshift) (URShiftI src2 rshift)));
12970 predicate(0 == (((n->in(1)->in(2)->get_int() & 31) + (n->in(2)->in(2)->get_int() & 31)) & 31));
12971
12972 ins_cost(INSN_COST);
12973 format %{ "extr $dst, $src1, $src2, #$rshift" %}
12974
12975 ins_encode %{
12976 __ extrw(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg),
12977 $rshift$$constant & 31);
12978 %}
12979 ins_pipe(ialu_reg_reg_extr);
12980 %}
12981
12982 // This pattern is automatically generated from aarch64_ad.m4
12983 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
12984 instruct rorI_imm(iRegINoSp dst, iRegI src, immI shift)
12985 %{
12986 match(Set dst (RotateRight src shift));
12987
12988 ins_cost(INSN_COST);
12989 format %{ "ror $dst, $src, $shift" %}
12990
12991 ins_encode %{
12992 __ extrw(as_Register($dst$$reg), as_Register($src$$reg), as_Register($src$$reg),
12993 $shift$$constant & 0x1f);
12994 %}
12995 ins_pipe(ialu_reg_reg_vshift);
12996 %}
12997
12998 // This pattern is automatically generated from aarch64_ad.m4
12999 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
13000 instruct rorL_imm(iRegLNoSp dst, iRegL src, immI shift)
13001 %{
13002 match(Set dst (RotateRight src shift));
13003
13004 ins_cost(INSN_COST);
13005 format %{ "ror $dst, $src, $shift" %}
13006
13007 ins_encode %{
13008 __ extr(as_Register($dst$$reg), as_Register($src$$reg), as_Register($src$$reg),
13009 $shift$$constant & 0x3f);
13010 %}
13011 ins_pipe(ialu_reg_reg_vshift);
13012 %}
13013
13014 // This pattern is automatically generated from aarch64_ad.m4
13015 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
13016 instruct rorI_reg(iRegINoSp dst, iRegI src, iRegI shift)
13017 %{
13018 match(Set dst (RotateRight src shift));
13019
13020 ins_cost(INSN_COST);
13021 format %{ "ror $dst, $src, $shift" %}
13022
13023 ins_encode %{
13024 __ rorvw(as_Register($dst$$reg), as_Register($src$$reg), as_Register($shift$$reg));
13025 %}
13026 ins_pipe(ialu_reg_reg_vshift);
13027 %}
13028
13029 // This pattern is automatically generated from aarch64_ad.m4
13030 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
13031 instruct rorL_reg(iRegLNoSp dst, iRegL src, iRegI shift)
13032 %{
13033 match(Set dst (RotateRight src shift));
13034
13035 ins_cost(INSN_COST);
13036 format %{ "ror $dst, $src, $shift" %}
13037
13038 ins_encode %{
13039 __ rorv(as_Register($dst$$reg), as_Register($src$$reg), as_Register($shift$$reg));
13040 %}
13041 ins_pipe(ialu_reg_reg_vshift);
13042 %}
13043
13044 // This pattern is automatically generated from aarch64_ad.m4
13045 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
13046 instruct rolI_reg(iRegINoSp dst, iRegI src, iRegI shift)
13047 %{
13048 match(Set dst (RotateLeft src shift));
13049
13050 ins_cost(INSN_COST);
13051 format %{ "rol $dst, $src, $shift" %}
13052
13053 ins_encode %{
13054 __ subw(rscratch1, zr, as_Register($shift$$reg));
13055 __ rorvw(as_Register($dst$$reg), as_Register($src$$reg), rscratch1);
13056 %}
13057 ins_pipe(ialu_reg_reg_vshift);
13058 %}
13059
13060 // This pattern is automatically generated from aarch64_ad.m4
13061 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
13062 instruct rolL_reg(iRegLNoSp dst, iRegL src, iRegI shift)
13063 %{
13064 match(Set dst (RotateLeft src shift));
13065
13066 ins_cost(INSN_COST);
13067 format %{ "rol $dst, $src, $shift" %}
13068
13069 ins_encode %{
13070 __ subw(rscratch1, zr, as_Register($shift$$reg));
13071 __ rorv(as_Register($dst$$reg), as_Register($src$$reg), rscratch1);
13072 %}
13073 ins_pipe(ialu_reg_reg_vshift);
13074 %}
13075
13076
13077 // Add/subtract (extended)
13078
13079 // This pattern is automatically generated from aarch64_ad.m4
13080 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
13081 instruct AddExtI(iRegLNoSp dst, iRegL src1, iRegIorL2I src2, rFlagsReg cr)
13082 %{
13083 match(Set dst (AddL src1 (ConvI2L src2)));
13084 ins_cost(INSN_COST);
13085 format %{ "add $dst, $src1, $src2, sxtw" %}
13086
13087 ins_encode %{
13088 __ add(as_Register($dst$$reg), as_Register($src1$$reg),
13089 as_Register($src2$$reg), ext::sxtw);
13090 %}
13091 ins_pipe(ialu_reg_reg);
13092 %}
13093
13094 // This pattern is automatically generated from aarch64_ad.m4
13095 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
13096 instruct SubExtI(iRegLNoSp dst, iRegL src1, iRegIorL2I src2, rFlagsReg cr)
13097 %{
13098 match(Set dst (SubL src1 (ConvI2L src2)));
13099 ins_cost(INSN_COST);
13100 format %{ "sub $dst, $src1, $src2, sxtw" %}
13101
13102 ins_encode %{
13103 __ sub(as_Register($dst$$reg), as_Register($src1$$reg),
13104 as_Register($src2$$reg), ext::sxtw);
13105 %}
13106 ins_pipe(ialu_reg_reg);
13107 %}
13108
13109 // This pattern is automatically generated from aarch64_ad.m4
13110 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
13111 instruct AddExtI_sxth(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI_16 lshift, immI_16 rshift, rFlagsReg cr)
13112 %{
13113 match(Set dst (AddI src1 (RShiftI (LShiftI src2 lshift) rshift)));
13114 ins_cost(INSN_COST);
13115 format %{ "add $dst, $src1, $src2, sxth" %}
13116
13117 ins_encode %{
13118 __ add(as_Register($dst$$reg), as_Register($src1$$reg),
13119 as_Register($src2$$reg), ext::sxth);
13120 %}
13121 ins_pipe(ialu_reg_reg);
13122 %}
13123
13124 // This pattern is automatically generated from aarch64_ad.m4
13125 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
13126 instruct AddExtI_sxtb(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI_24 lshift, immI_24 rshift, rFlagsReg cr)
13127 %{
13128 match(Set dst (AddI src1 (RShiftI (LShiftI src2 lshift) rshift)));
13129 ins_cost(INSN_COST);
13130 format %{ "add $dst, $src1, $src2, sxtb" %}
13131
13132 ins_encode %{
13133 __ add(as_Register($dst$$reg), as_Register($src1$$reg),
13134 as_Register($src2$$reg), ext::sxtb);
13135 %}
13136 ins_pipe(ialu_reg_reg);
13137 %}
13138
13139 // This pattern is automatically generated from aarch64_ad.m4
13140 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
13141 instruct AddExtI_uxtb(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI_24 lshift, immI_24 rshift, rFlagsReg cr)
13142 %{
13143 match(Set dst (AddI src1 (URShiftI (LShiftI src2 lshift) rshift)));
13144 ins_cost(INSN_COST);
13145 format %{ "add $dst, $src1, $src2, uxtb" %}
13146
13147 ins_encode %{
13148 __ add(as_Register($dst$$reg), as_Register($src1$$reg),
13149 as_Register($src2$$reg), ext::uxtb);
13150 %}
13151 ins_pipe(ialu_reg_reg);
13152 %}
13153
13154 // This pattern is automatically generated from aarch64_ad.m4
13155 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
13156 instruct AddExtL_sxth(iRegLNoSp dst, iRegL src1, iRegL src2, immI_48 lshift, immI_48 rshift, rFlagsReg cr)
13157 %{
13158 match(Set dst (AddL src1 (RShiftL (LShiftL src2 lshift) rshift)));
13159 ins_cost(INSN_COST);
13160 format %{ "add $dst, $src1, $src2, sxth" %}
13161
13162 ins_encode %{
13163 __ add(as_Register($dst$$reg), as_Register($src1$$reg),
13164 as_Register($src2$$reg), ext::sxth);
13165 %}
13166 ins_pipe(ialu_reg_reg);
13167 %}
13168
13169 // This pattern is automatically generated from aarch64_ad.m4
13170 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
13171 instruct AddExtL_sxtw(iRegLNoSp dst, iRegL src1, iRegL src2, immI_32 lshift, immI_32 rshift, rFlagsReg cr)
13172 %{
13173 match(Set dst (AddL src1 (RShiftL (LShiftL src2 lshift) rshift)));
13174 ins_cost(INSN_COST);
13175 format %{ "add $dst, $src1, $src2, sxtw" %}
13176
13177 ins_encode %{
13178 __ add(as_Register($dst$$reg), as_Register($src1$$reg),
13179 as_Register($src2$$reg), ext::sxtw);
13180 %}
13181 ins_pipe(ialu_reg_reg);
13182 %}
13183
13184 // This pattern is automatically generated from aarch64_ad.m4
13185 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
13186 instruct AddExtL_sxtb(iRegLNoSp dst, iRegL src1, iRegL src2, immI_56 lshift, immI_56 rshift, rFlagsReg cr)
13187 %{
13188 match(Set dst (AddL src1 (RShiftL (LShiftL src2 lshift) rshift)));
13189 ins_cost(INSN_COST);
13190 format %{ "add $dst, $src1, $src2, sxtb" %}
13191
13192 ins_encode %{
13193 __ add(as_Register($dst$$reg), as_Register($src1$$reg),
13194 as_Register($src2$$reg), ext::sxtb);
13195 %}
13196 ins_pipe(ialu_reg_reg);
13197 %}
13198
13199 // This pattern is automatically generated from aarch64_ad.m4
13200 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
13201 instruct AddExtL_uxtb(iRegLNoSp dst, iRegL src1, iRegL src2, immI_56 lshift, immI_56 rshift, rFlagsReg cr)
13202 %{
13203 match(Set dst (AddL src1 (URShiftL (LShiftL src2 lshift) rshift)));
13204 ins_cost(INSN_COST);
13205 format %{ "add $dst, $src1, $src2, uxtb" %}
13206
13207 ins_encode %{
13208 __ add(as_Register($dst$$reg), as_Register($src1$$reg),
13209 as_Register($src2$$reg), ext::uxtb);
13210 %}
13211 ins_pipe(ialu_reg_reg);
13212 %}
13213
13214 // This pattern is automatically generated from aarch64_ad.m4
13215 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
13216 instruct AddExtI_uxtb_and(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI_255 mask, rFlagsReg cr)
13217 %{
13218 match(Set dst (AddI src1 (AndI src2 mask)));
13219 ins_cost(INSN_COST);
13220 format %{ "addw $dst, $src1, $src2, uxtb" %}
13221
13222 ins_encode %{
13223 __ addw(as_Register($dst$$reg), as_Register($src1$$reg),
13224 as_Register($src2$$reg), ext::uxtb);
13225 %}
13226 ins_pipe(ialu_reg_reg);
13227 %}
13228
13229 // This pattern is automatically generated from aarch64_ad.m4
13230 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
13231 instruct AddExtI_uxth_and(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI_65535 mask, rFlagsReg cr)
13232 %{
13233 match(Set dst (AddI src1 (AndI src2 mask)));
13234 ins_cost(INSN_COST);
13235 format %{ "addw $dst, $src1, $src2, uxth" %}
13236
13237 ins_encode %{
13238 __ addw(as_Register($dst$$reg), as_Register($src1$$reg),
13239 as_Register($src2$$reg), ext::uxth);
13240 %}
13241 ins_pipe(ialu_reg_reg);
13242 %}
13243
13244 // This pattern is automatically generated from aarch64_ad.m4
13245 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
13246 instruct AddExtL_uxtb_and(iRegLNoSp dst, iRegL src1, iRegL src2, immL_255 mask, rFlagsReg cr)
13247 %{
13248 match(Set dst (AddL src1 (AndL src2 mask)));
13249 ins_cost(INSN_COST);
13250 format %{ "add $dst, $src1, $src2, uxtb" %}
13251
13252 ins_encode %{
13253 __ add(as_Register($dst$$reg), as_Register($src1$$reg),
13254 as_Register($src2$$reg), ext::uxtb);
13255 %}
13256 ins_pipe(ialu_reg_reg);
13257 %}
13258
13259 // This pattern is automatically generated from aarch64_ad.m4
13260 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
13261 instruct AddExtL_uxth_and(iRegLNoSp dst, iRegL src1, iRegL src2, immL_65535 mask, rFlagsReg cr)
13262 %{
13263 match(Set dst (AddL src1 (AndL src2 mask)));
13264 ins_cost(INSN_COST);
13265 format %{ "add $dst, $src1, $src2, uxth" %}
13266
13267 ins_encode %{
13268 __ add(as_Register($dst$$reg), as_Register($src1$$reg),
13269 as_Register($src2$$reg), ext::uxth);
13270 %}
13271 ins_pipe(ialu_reg_reg);
13272 %}
13273
13274 // This pattern is automatically generated from aarch64_ad.m4
13275 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
13276 instruct AddExtL_uxtw_and(iRegLNoSp dst, iRegL src1, iRegL src2, immL_4294967295 mask, rFlagsReg cr)
13277 %{
13278 match(Set dst (AddL src1 (AndL src2 mask)));
13279 ins_cost(INSN_COST);
13280 format %{ "add $dst, $src1, $src2, uxtw" %}
13281
13282 ins_encode %{
13283 __ add(as_Register($dst$$reg), as_Register($src1$$reg),
13284 as_Register($src2$$reg), ext::uxtw);
13285 %}
13286 ins_pipe(ialu_reg_reg);
13287 %}
13288
13289 // This pattern is automatically generated from aarch64_ad.m4
13290 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
13291 instruct SubExtI_uxtb_and(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI_255 mask, rFlagsReg cr)
13292 %{
13293 match(Set dst (SubI src1 (AndI src2 mask)));
13294 ins_cost(INSN_COST);
13295 format %{ "subw $dst, $src1, $src2, uxtb" %}
13296
13297 ins_encode %{
13298 __ subw(as_Register($dst$$reg), as_Register($src1$$reg),
13299 as_Register($src2$$reg), ext::uxtb);
13300 %}
13301 ins_pipe(ialu_reg_reg);
13302 %}
13303
13304 // This pattern is automatically generated from aarch64_ad.m4
13305 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
13306 instruct SubExtI_uxth_and(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI_65535 mask, rFlagsReg cr)
13307 %{
13308 match(Set dst (SubI src1 (AndI src2 mask)));
13309 ins_cost(INSN_COST);
13310 format %{ "subw $dst, $src1, $src2, uxth" %}
13311
13312 ins_encode %{
13313 __ subw(as_Register($dst$$reg), as_Register($src1$$reg),
13314 as_Register($src2$$reg), ext::uxth);
13315 %}
13316 ins_pipe(ialu_reg_reg);
13317 %}
13318
13319 // This pattern is automatically generated from aarch64_ad.m4
13320 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
13321 instruct SubExtL_uxtb_and(iRegLNoSp dst, iRegL src1, iRegL src2, immL_255 mask, rFlagsReg cr)
13322 %{
13323 match(Set dst (SubL src1 (AndL src2 mask)));
13324 ins_cost(INSN_COST);
13325 format %{ "sub $dst, $src1, $src2, uxtb" %}
13326
13327 ins_encode %{
13328 __ sub(as_Register($dst$$reg), as_Register($src1$$reg),
13329 as_Register($src2$$reg), ext::uxtb);
13330 %}
13331 ins_pipe(ialu_reg_reg);
13332 %}
13333
13334 // This pattern is automatically generated from aarch64_ad.m4
13335 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
13336 instruct SubExtL_uxth_and(iRegLNoSp dst, iRegL src1, iRegL src2, immL_65535 mask, rFlagsReg cr)
13337 %{
13338 match(Set dst (SubL src1 (AndL src2 mask)));
13339 ins_cost(INSN_COST);
13340 format %{ "sub $dst, $src1, $src2, uxth" %}
13341
13342 ins_encode %{
13343 __ sub(as_Register($dst$$reg), as_Register($src1$$reg),
13344 as_Register($src2$$reg), ext::uxth);
13345 %}
13346 ins_pipe(ialu_reg_reg);
13347 %}
13348
13349 // This pattern is automatically generated from aarch64_ad.m4
13350 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
13351 instruct SubExtL_uxtw_and(iRegLNoSp dst, iRegL src1, iRegL src2, immL_4294967295 mask, rFlagsReg cr)
13352 %{
13353 match(Set dst (SubL src1 (AndL src2 mask)));
13354 ins_cost(INSN_COST);
13355 format %{ "sub $dst, $src1, $src2, uxtw" %}
13356
13357 ins_encode %{
13358 __ sub(as_Register($dst$$reg), as_Register($src1$$reg),
13359 as_Register($src2$$reg), ext::uxtw);
13360 %}
13361 ins_pipe(ialu_reg_reg);
13362 %}
13363
13364
13365 // This pattern is automatically generated from aarch64_ad.m4
13366 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
13367 instruct AddExtL_sxtb_shift(iRegLNoSp dst, iRegL src1, iRegL src2, immIExt lshift2, immI_56 lshift1, immI_56 rshift1, rFlagsReg cr)
13368 %{
13369 match(Set dst (AddL src1 (LShiftL (RShiftL (LShiftL src2 lshift1) rshift1) lshift2)));
13370 ins_cost(1.9 * INSN_COST);
13371 format %{ "add $dst, $src1, $src2, sxtb #lshift2" %}
13372
13373 ins_encode %{
13374 __ add(as_Register($dst$$reg), as_Register($src1$$reg),
13375 as_Register($src2$$reg), ext::sxtb, ($lshift2$$constant));
13376 %}
13377 ins_pipe(ialu_reg_reg_shift);
13378 %}
13379
13380 // This pattern is automatically generated from aarch64_ad.m4
13381 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
13382 instruct AddExtL_sxth_shift(iRegLNoSp dst, iRegL src1, iRegL src2, immIExt lshift2, immI_48 lshift1, immI_48 rshift1, rFlagsReg cr)
13383 %{
13384 match(Set dst (AddL src1 (LShiftL (RShiftL (LShiftL src2 lshift1) rshift1) lshift2)));
13385 ins_cost(1.9 * INSN_COST);
13386 format %{ "add $dst, $src1, $src2, sxth #lshift2" %}
13387
13388 ins_encode %{
13389 __ add(as_Register($dst$$reg), as_Register($src1$$reg),
13390 as_Register($src2$$reg), ext::sxth, ($lshift2$$constant));
13391 %}
13392 ins_pipe(ialu_reg_reg_shift);
13393 %}
13394
13395 // This pattern is automatically generated from aarch64_ad.m4
13396 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
13397 instruct AddExtL_sxtw_shift(iRegLNoSp dst, iRegL src1, iRegL src2, immIExt lshift2, immI_32 lshift1, immI_32 rshift1, rFlagsReg cr)
13398 %{
13399 match(Set dst (AddL src1 (LShiftL (RShiftL (LShiftL src2 lshift1) rshift1) lshift2)));
13400 ins_cost(1.9 * INSN_COST);
13401 format %{ "add $dst, $src1, $src2, sxtw #lshift2" %}
13402
13403 ins_encode %{
13404 __ add(as_Register($dst$$reg), as_Register($src1$$reg),
13405 as_Register($src2$$reg), ext::sxtw, ($lshift2$$constant));
13406 %}
13407 ins_pipe(ialu_reg_reg_shift);
13408 %}
13409
13410 // This pattern is automatically generated from aarch64_ad.m4
13411 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
13412 instruct SubExtL_sxtb_shift(iRegLNoSp dst, iRegL src1, iRegL src2, immIExt lshift2, immI_56 lshift1, immI_56 rshift1, rFlagsReg cr)
13413 %{
13414 match(Set dst (SubL src1 (LShiftL (RShiftL (LShiftL src2 lshift1) rshift1) lshift2)));
13415 ins_cost(1.9 * INSN_COST);
13416 format %{ "sub $dst, $src1, $src2, sxtb #lshift2" %}
13417
13418 ins_encode %{
13419 __ sub(as_Register($dst$$reg), as_Register($src1$$reg),
13420 as_Register($src2$$reg), ext::sxtb, ($lshift2$$constant));
13421 %}
13422 ins_pipe(ialu_reg_reg_shift);
13423 %}
13424
13425 // This pattern is automatically generated from aarch64_ad.m4
13426 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
13427 instruct SubExtL_sxth_shift(iRegLNoSp dst, iRegL src1, iRegL src2, immIExt lshift2, immI_48 lshift1, immI_48 rshift1, rFlagsReg cr)
13428 %{
13429 match(Set dst (SubL src1 (LShiftL (RShiftL (LShiftL src2 lshift1) rshift1) lshift2)));
13430 ins_cost(1.9 * INSN_COST);
13431 format %{ "sub $dst, $src1, $src2, sxth #lshift2" %}
13432
13433 ins_encode %{
13434 __ sub(as_Register($dst$$reg), as_Register($src1$$reg),
13435 as_Register($src2$$reg), ext::sxth, ($lshift2$$constant));
13436 %}
13437 ins_pipe(ialu_reg_reg_shift);
13438 %}
13439
13440 // This pattern is automatically generated from aarch64_ad.m4
13441 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
13442 instruct SubExtL_sxtw_shift(iRegLNoSp dst, iRegL src1, iRegL src2, immIExt lshift2, immI_32 lshift1, immI_32 rshift1, rFlagsReg cr)
13443 %{
13444 match(Set dst (SubL src1 (LShiftL (RShiftL (LShiftL src2 lshift1) rshift1) lshift2)));
13445 ins_cost(1.9 * INSN_COST);
13446 format %{ "sub $dst, $src1, $src2, sxtw #lshift2" %}
13447
13448 ins_encode %{
13449 __ sub(as_Register($dst$$reg), as_Register($src1$$reg),
13450 as_Register($src2$$reg), ext::sxtw, ($lshift2$$constant));
13451 %}
13452 ins_pipe(ialu_reg_reg_shift);
13453 %}
13454
13455 // This pattern is automatically generated from aarch64_ad.m4
13456 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
13457 instruct AddExtI_sxtb_shift(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immIExt lshift2, immI_24 lshift1, immI_24 rshift1, rFlagsReg cr)
13458 %{
13459 match(Set dst (AddI src1 (LShiftI (RShiftI (LShiftI src2 lshift1) rshift1) lshift2)));
13460 ins_cost(1.9 * INSN_COST);
13461 format %{ "addw $dst, $src1, $src2, sxtb #lshift2" %}
13462
13463 ins_encode %{
13464 __ addw(as_Register($dst$$reg), as_Register($src1$$reg),
13465 as_Register($src2$$reg), ext::sxtb, ($lshift2$$constant));
13466 %}
13467 ins_pipe(ialu_reg_reg_shift);
13468 %}
13469
13470 // This pattern is automatically generated from aarch64_ad.m4
13471 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
13472 instruct AddExtI_sxth_shift(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immIExt lshift2, immI_16 lshift1, immI_16 rshift1, rFlagsReg cr)
13473 %{
13474 match(Set dst (AddI src1 (LShiftI (RShiftI (LShiftI src2 lshift1) rshift1) lshift2)));
13475 ins_cost(1.9 * INSN_COST);
13476 format %{ "addw $dst, $src1, $src2, sxth #lshift2" %}
13477
13478 ins_encode %{
13479 __ addw(as_Register($dst$$reg), as_Register($src1$$reg),
13480 as_Register($src2$$reg), ext::sxth, ($lshift2$$constant));
13481 %}
13482 ins_pipe(ialu_reg_reg_shift);
13483 %}
13484
13485 // This pattern is automatically generated from aarch64_ad.m4
13486 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
13487 instruct SubExtI_sxtb_shift(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immIExt lshift2, immI_24 lshift1, immI_24 rshift1, rFlagsReg cr)
13488 %{
13489 match(Set dst (SubI src1 (LShiftI (RShiftI (LShiftI src2 lshift1) rshift1) lshift2)));
13490 ins_cost(1.9 * INSN_COST);
13491 format %{ "subw $dst, $src1, $src2, sxtb #lshift2" %}
13492
13493 ins_encode %{
13494 __ subw(as_Register($dst$$reg), as_Register($src1$$reg),
13495 as_Register($src2$$reg), ext::sxtb, ($lshift2$$constant));
13496 %}
13497 ins_pipe(ialu_reg_reg_shift);
13498 %}
13499
13500 // This pattern is automatically generated from aarch64_ad.m4
13501 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
13502 instruct SubExtI_sxth_shift(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immIExt lshift2, immI_16 lshift1, immI_16 rshift1, rFlagsReg cr)
13503 %{
13504 match(Set dst (SubI src1 (LShiftI (RShiftI (LShiftI src2 lshift1) rshift1) lshift2)));
13505 ins_cost(1.9 * INSN_COST);
13506 format %{ "subw $dst, $src1, $src2, sxth #lshift2" %}
13507
13508 ins_encode %{
13509 __ subw(as_Register($dst$$reg), as_Register($src1$$reg),
13510 as_Register($src2$$reg), ext::sxth, ($lshift2$$constant));
13511 %}
13512 ins_pipe(ialu_reg_reg_shift);
13513 %}
13514
13515 // This pattern is automatically generated from aarch64_ad.m4
13516 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
13517 instruct AddExtI_shift(iRegLNoSp dst, iRegL src1, iRegIorL2I src2, immIExt lshift, rFlagsReg cr)
13518 %{
13519 match(Set dst (AddL src1 (LShiftL (ConvI2L src2) lshift)));
13520 ins_cost(1.9 * INSN_COST);
13521 format %{ "add $dst, $src1, $src2, sxtw #lshift" %}
13522
13523 ins_encode %{
13524 __ add(as_Register($dst$$reg), as_Register($src1$$reg),
13525 as_Register($src2$$reg), ext::sxtw, ($lshift$$constant));
13526 %}
13527 ins_pipe(ialu_reg_reg_shift);
13528 %}
13529
13530 // This pattern is automatically generated from aarch64_ad.m4
13531 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
13532 instruct SubExtI_shift(iRegLNoSp dst, iRegL src1, iRegIorL2I src2, immIExt lshift, rFlagsReg cr)
13533 %{
13534 match(Set dst (SubL src1 (LShiftL (ConvI2L src2) lshift)));
13535 ins_cost(1.9 * INSN_COST);
13536 format %{ "sub $dst, $src1, $src2, sxtw #lshift" %}
13537
13538 ins_encode %{
13539 __ sub(as_Register($dst$$reg), as_Register($src1$$reg),
13540 as_Register($src2$$reg), ext::sxtw, ($lshift$$constant));
13541 %}
13542 ins_pipe(ialu_reg_reg_shift);
13543 %}
13544
13545 // This pattern is automatically generated from aarch64_ad.m4
13546 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
13547 instruct AddExtL_uxtb_and_shift(iRegLNoSp dst, iRegL src1, iRegL src2, immL_255 mask, immIExt lshift, rFlagsReg cr)
13548 %{
13549 match(Set dst (AddL src1 (LShiftL (AndL src2 mask) lshift)));
13550 ins_cost(1.9 * INSN_COST);
13551 format %{ "add $dst, $src1, $src2, uxtb #lshift" %}
13552
13553 ins_encode %{
13554 __ add(as_Register($dst$$reg), as_Register($src1$$reg),
13555 as_Register($src2$$reg), ext::uxtb, ($lshift$$constant));
13556 %}
13557 ins_pipe(ialu_reg_reg_shift);
13558 %}
13559
13560 // This pattern is automatically generated from aarch64_ad.m4
13561 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
13562 instruct AddExtL_uxth_and_shift(iRegLNoSp dst, iRegL src1, iRegL src2, immL_65535 mask, immIExt lshift, rFlagsReg cr)
13563 %{
13564 match(Set dst (AddL src1 (LShiftL (AndL src2 mask) lshift)));
13565 ins_cost(1.9 * INSN_COST);
13566 format %{ "add $dst, $src1, $src2, uxth #lshift" %}
13567
13568 ins_encode %{
13569 __ add(as_Register($dst$$reg), as_Register($src1$$reg),
13570 as_Register($src2$$reg), ext::uxth, ($lshift$$constant));
13571 %}
13572 ins_pipe(ialu_reg_reg_shift);
13573 %}
13574
13575 // This pattern is automatically generated from aarch64_ad.m4
13576 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
13577 instruct AddExtL_uxtw_and_shift(iRegLNoSp dst, iRegL src1, iRegL src2, immL_4294967295 mask, immIExt lshift, rFlagsReg cr)
13578 %{
13579 match(Set dst (AddL src1 (LShiftL (AndL src2 mask) lshift)));
13580 ins_cost(1.9 * INSN_COST);
13581 format %{ "add $dst, $src1, $src2, uxtw #lshift" %}
13582
13583 ins_encode %{
13584 __ add(as_Register($dst$$reg), as_Register($src1$$reg),
13585 as_Register($src2$$reg), ext::uxtw, ($lshift$$constant));
13586 %}
13587 ins_pipe(ialu_reg_reg_shift);
13588 %}
13589
13590 // This pattern is automatically generated from aarch64_ad.m4
13591 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
13592 instruct SubExtL_uxtb_and_shift(iRegLNoSp dst, iRegL src1, iRegL src2, immL_255 mask, immIExt lshift, rFlagsReg cr)
13593 %{
13594 match(Set dst (SubL src1 (LShiftL (AndL src2 mask) lshift)));
13595 ins_cost(1.9 * INSN_COST);
13596 format %{ "sub $dst, $src1, $src2, uxtb #lshift" %}
13597
13598 ins_encode %{
13599 __ sub(as_Register($dst$$reg), as_Register($src1$$reg),
13600 as_Register($src2$$reg), ext::uxtb, ($lshift$$constant));
13601 %}
13602 ins_pipe(ialu_reg_reg_shift);
13603 %}
13604
13605 // This pattern is automatically generated from aarch64_ad.m4
13606 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
13607 instruct SubExtL_uxth_and_shift(iRegLNoSp dst, iRegL src1, iRegL src2, immL_65535 mask, immIExt lshift, rFlagsReg cr)
13608 %{
13609 match(Set dst (SubL src1 (LShiftL (AndL src2 mask) lshift)));
13610 ins_cost(1.9 * INSN_COST);
13611 format %{ "sub $dst, $src1, $src2, uxth #lshift" %}
13612
13613 ins_encode %{
13614 __ sub(as_Register($dst$$reg), as_Register($src1$$reg),
13615 as_Register($src2$$reg), ext::uxth, ($lshift$$constant));
13616 %}
13617 ins_pipe(ialu_reg_reg_shift);
13618 %}
13619
13620 // This pattern is automatically generated from aarch64_ad.m4
13621 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
13622 instruct SubExtL_uxtw_and_shift(iRegLNoSp dst, iRegL src1, iRegL src2, immL_4294967295 mask, immIExt lshift, rFlagsReg cr)
13623 %{
13624 match(Set dst (SubL src1 (LShiftL (AndL src2 mask) lshift)));
13625 ins_cost(1.9 * INSN_COST);
13626 format %{ "sub $dst, $src1, $src2, uxtw #lshift" %}
13627
13628 ins_encode %{
13629 __ sub(as_Register($dst$$reg), as_Register($src1$$reg),
13630 as_Register($src2$$reg), ext::uxtw, ($lshift$$constant));
13631 %}
13632 ins_pipe(ialu_reg_reg_shift);
13633 %}
13634
13635 // This pattern is automatically generated from aarch64_ad.m4
13636 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
13637 instruct AddExtI_uxtb_and_shift(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI_255 mask, immIExt lshift, rFlagsReg cr)
13638 %{
13639 match(Set dst (AddI src1 (LShiftI (AndI src2 mask) lshift)));
13640 ins_cost(1.9 * INSN_COST);
13641 format %{ "addw $dst, $src1, $src2, uxtb #lshift" %}
13642
13643 ins_encode %{
13644 __ addw(as_Register($dst$$reg), as_Register($src1$$reg),
13645 as_Register($src2$$reg), ext::uxtb, ($lshift$$constant));
13646 %}
13647 ins_pipe(ialu_reg_reg_shift);
13648 %}
13649
13650 // This pattern is automatically generated from aarch64_ad.m4
13651 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
13652 instruct AddExtI_uxth_and_shift(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI_65535 mask, immIExt lshift, rFlagsReg cr)
13653 %{
13654 match(Set dst (AddI src1 (LShiftI (AndI src2 mask) lshift)));
13655 ins_cost(1.9 * INSN_COST);
13656 format %{ "addw $dst, $src1, $src2, uxth #lshift" %}
13657
13658 ins_encode %{
13659 __ addw(as_Register($dst$$reg), as_Register($src1$$reg),
13660 as_Register($src2$$reg), ext::uxth, ($lshift$$constant));
13661 %}
13662 ins_pipe(ialu_reg_reg_shift);
13663 %}
13664
13665 // This pattern is automatically generated from aarch64_ad.m4
13666 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
13667 instruct SubExtI_uxtb_and_shift(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI_255 mask, immIExt lshift, rFlagsReg cr)
13668 %{
13669 match(Set dst (SubI src1 (LShiftI (AndI src2 mask) lshift)));
13670 ins_cost(1.9 * INSN_COST);
13671 format %{ "subw $dst, $src1, $src2, uxtb #lshift" %}
13672
13673 ins_encode %{
13674 __ subw(as_Register($dst$$reg), as_Register($src1$$reg),
13675 as_Register($src2$$reg), ext::uxtb, ($lshift$$constant));
13676 %}
13677 ins_pipe(ialu_reg_reg_shift);
13678 %}
13679
13680 // This pattern is automatically generated from aarch64_ad.m4
13681 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
13682 instruct SubExtI_uxth_and_shift(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI_65535 mask, immIExt lshift, rFlagsReg cr)
13683 %{
13684 match(Set dst (SubI src1 (LShiftI (AndI src2 mask) lshift)));
13685 ins_cost(1.9 * INSN_COST);
13686 format %{ "subw $dst, $src1, $src2, uxth #lshift" %}
13687
13688 ins_encode %{
13689 __ subw(as_Register($dst$$reg), as_Register($src1$$reg),
13690 as_Register($src2$$reg), ext::uxth, ($lshift$$constant));
13691 %}
13692 ins_pipe(ialu_reg_reg_shift);
13693 %}
13694
13695 // This pattern is automatically generated from aarch64_ad.m4
13696 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
13697 instruct cmovI_reg_reg_lt(iRegINoSp dst, iRegI src1, iRegI src2, rFlagsReg cr)
13698 %{
13699 effect(DEF dst, USE src1, USE src2, USE cr);
13700 ins_cost(INSN_COST * 2);
13701 format %{ "cselw $dst, $src1, $src2 lt\t" %}
13702
13703 ins_encode %{
13704 __ cselw($dst$$Register,
13705 $src1$$Register,
13706 $src2$$Register,
13707 Assembler::LT);
13708 %}
13709 ins_pipe(icond_reg_reg);
13710 %}
13711
13712 // This pattern is automatically generated from aarch64_ad.m4
13713 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
13714 instruct cmovI_reg_reg_gt(iRegINoSp dst, iRegI src1, iRegI src2, rFlagsReg cr)
13715 %{
13716 effect(DEF dst, USE src1, USE src2, USE cr);
13717 ins_cost(INSN_COST * 2);
13718 format %{ "cselw $dst, $src1, $src2 gt\t" %}
13719
13720 ins_encode %{
13721 __ cselw($dst$$Register,
13722 $src1$$Register,
13723 $src2$$Register,
13724 Assembler::GT);
13725 %}
13726 ins_pipe(icond_reg_reg);
13727 %}
13728
13729 // This pattern is automatically generated from aarch64_ad.m4
13730 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
13731 instruct cmovI_reg_imm0_lt(iRegINoSp dst, iRegI src1, rFlagsReg cr)
13732 %{
13733 effect(DEF dst, USE src1, USE cr);
13734 ins_cost(INSN_COST * 2);
13735 format %{ "cselw $dst, $src1, zr lt\t" %}
13736
13737 ins_encode %{
13738 __ cselw($dst$$Register,
13739 $src1$$Register,
13740 zr,
13741 Assembler::LT);
13742 %}
13743 ins_pipe(icond_reg);
13744 %}
13745
13746 // This pattern is automatically generated from aarch64_ad.m4
13747 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
13748 instruct cmovI_reg_imm0_gt(iRegINoSp dst, iRegI src1, rFlagsReg cr)
13749 %{
13750 effect(DEF dst, USE src1, USE cr);
13751 ins_cost(INSN_COST * 2);
13752 format %{ "cselw $dst, $src1, zr gt\t" %}
13753
13754 ins_encode %{
13755 __ cselw($dst$$Register,
13756 $src1$$Register,
13757 zr,
13758 Assembler::GT);
13759 %}
13760 ins_pipe(icond_reg);
13761 %}
13762
13763 // This pattern is automatically generated from aarch64_ad.m4
13764 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
13765 instruct cmovI_reg_imm1_le(iRegINoSp dst, iRegI src1, rFlagsReg cr)
13766 %{
13767 effect(DEF dst, USE src1, USE cr);
13768 ins_cost(INSN_COST * 2);
13769 format %{ "csincw $dst, $src1, zr le\t" %}
13770
13771 ins_encode %{
13772 __ csincw($dst$$Register,
13773 $src1$$Register,
13774 zr,
13775 Assembler::LE);
13776 %}
13777 ins_pipe(icond_reg);
13778 %}
13779
13780 // This pattern is automatically generated from aarch64_ad.m4
13781 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
13782 instruct cmovI_reg_imm1_gt(iRegINoSp dst, iRegI src1, rFlagsReg cr)
13783 %{
13784 effect(DEF dst, USE src1, USE cr);
13785 ins_cost(INSN_COST * 2);
13786 format %{ "csincw $dst, $src1, zr gt\t" %}
13787
13788 ins_encode %{
13789 __ csincw($dst$$Register,
13790 $src1$$Register,
13791 zr,
13792 Assembler::GT);
13793 %}
13794 ins_pipe(icond_reg);
13795 %}
13796
13797 // This pattern is automatically generated from aarch64_ad.m4
13798 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
13799 instruct cmovI_reg_immM1_lt(iRegINoSp dst, iRegI src1, rFlagsReg cr)
13800 %{
13801 effect(DEF dst, USE src1, USE cr);
13802 ins_cost(INSN_COST * 2);
13803 format %{ "csinvw $dst, $src1, zr lt\t" %}
13804
13805 ins_encode %{
13806 __ csinvw($dst$$Register,
13807 $src1$$Register,
13808 zr,
13809 Assembler::LT);
13810 %}
13811 ins_pipe(icond_reg);
13812 %}
13813
13814 // This pattern is automatically generated from aarch64_ad.m4
13815 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
13816 instruct cmovI_reg_immM1_ge(iRegINoSp dst, iRegI src1, rFlagsReg cr)
13817 %{
13818 effect(DEF dst, USE src1, USE cr);
13819 ins_cost(INSN_COST * 2);
13820 format %{ "csinvw $dst, $src1, zr ge\t" %}
13821
13822 ins_encode %{
13823 __ csinvw($dst$$Register,
13824 $src1$$Register,
13825 zr,
13826 Assembler::GE);
13827 %}
13828 ins_pipe(icond_reg);
13829 %}
13830
13831 // This pattern is automatically generated from aarch64_ad.m4
13832 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
13833 instruct minI_reg_imm0(iRegINoSp dst, iRegIorL2I src, immI0 imm)
13834 %{
13835 match(Set dst (MinI src imm));
13836 ins_cost(INSN_COST * 3);
13837 expand %{
13838 rFlagsReg cr;
13839 compI_reg_imm0(cr, src);
13840 cmovI_reg_imm0_lt(dst, src, cr);
13841 %}
13842 %}
13843
13844 // This pattern is automatically generated from aarch64_ad.m4
13845 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
13846 instruct minI_imm0_reg(iRegINoSp dst, immI0 imm, iRegIorL2I src)
13847 %{
13848 match(Set dst (MinI imm src));
13849 ins_cost(INSN_COST * 3);
13850 expand %{
13851 rFlagsReg cr;
13852 compI_reg_imm0(cr, src);
13853 cmovI_reg_imm0_lt(dst, src, cr);
13854 %}
13855 %}
13856
13857 // This pattern is automatically generated from aarch64_ad.m4
13858 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
13859 instruct minI_reg_imm1(iRegINoSp dst, iRegIorL2I src, immI_1 imm)
13860 %{
13861 match(Set dst (MinI src imm));
13862 ins_cost(INSN_COST * 3);
13863 expand %{
13864 rFlagsReg cr;
13865 compI_reg_imm0(cr, src);
13866 cmovI_reg_imm1_le(dst, src, cr);
13867 %}
13868 %}
13869
13870 // This pattern is automatically generated from aarch64_ad.m4
13871 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
13872 instruct minI_imm1_reg(iRegINoSp dst, immI_1 imm, iRegIorL2I src)
13873 %{
13874 match(Set dst (MinI imm src));
13875 ins_cost(INSN_COST * 3);
13876 expand %{
13877 rFlagsReg cr;
13878 compI_reg_imm0(cr, src);
13879 cmovI_reg_imm1_le(dst, src, cr);
13880 %}
13881 %}
13882
13883 // This pattern is automatically generated from aarch64_ad.m4
13884 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
13885 instruct minI_reg_immM1(iRegINoSp dst, iRegIorL2I src, immI_M1 imm)
13886 %{
13887 match(Set dst (MinI src imm));
13888 ins_cost(INSN_COST * 3);
13889 expand %{
13890 rFlagsReg cr;
13891 compI_reg_imm0(cr, src);
13892 cmovI_reg_immM1_lt(dst, src, cr);
13893 %}
13894 %}
13895
13896 // This pattern is automatically generated from aarch64_ad.m4
13897 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
13898 instruct minI_immM1_reg(iRegINoSp dst, immI_M1 imm, iRegIorL2I src)
13899 %{
13900 match(Set dst (MinI imm src));
13901 ins_cost(INSN_COST * 3);
13902 expand %{
13903 rFlagsReg cr;
13904 compI_reg_imm0(cr, src);
13905 cmovI_reg_immM1_lt(dst, src, cr);
13906 %}
13907 %}
13908
13909 // This pattern is automatically generated from aarch64_ad.m4
13910 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
13911 instruct maxI_reg_imm0(iRegINoSp dst, iRegIorL2I src, immI0 imm)
13912 %{
13913 match(Set dst (MaxI src imm));
13914 ins_cost(INSN_COST * 3);
13915 expand %{
13916 rFlagsReg cr;
13917 compI_reg_imm0(cr, src);
13918 cmovI_reg_imm0_gt(dst, src, cr);
13919 %}
13920 %}
13921
13922 // This pattern is automatically generated from aarch64_ad.m4
13923 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
13924 instruct maxI_imm0_reg(iRegINoSp dst, immI0 imm, iRegIorL2I src)
13925 %{
13926 match(Set dst (MaxI imm src));
13927 ins_cost(INSN_COST * 3);
13928 expand %{
13929 rFlagsReg cr;
13930 compI_reg_imm0(cr, src);
13931 cmovI_reg_imm0_gt(dst, src, cr);
13932 %}
13933 %}
13934
13935 // This pattern is automatically generated from aarch64_ad.m4
13936 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
13937 instruct maxI_reg_imm1(iRegINoSp dst, iRegIorL2I src, immI_1 imm)
13938 %{
13939 match(Set dst (MaxI src imm));
13940 ins_cost(INSN_COST * 3);
13941 expand %{
13942 rFlagsReg cr;
13943 compI_reg_imm0(cr, src);
13944 cmovI_reg_imm1_gt(dst, src, cr);
13945 %}
13946 %}
13947
13948 // This pattern is automatically generated from aarch64_ad.m4
13949 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
13950 instruct maxI_imm1_reg(iRegINoSp dst, immI_1 imm, iRegIorL2I src)
13951 %{
13952 match(Set dst (MaxI imm src));
13953 ins_cost(INSN_COST * 3);
13954 expand %{
13955 rFlagsReg cr;
13956 compI_reg_imm0(cr, src);
13957 cmovI_reg_imm1_gt(dst, src, cr);
13958 %}
13959 %}
13960
13961 // This pattern is automatically generated from aarch64_ad.m4
13962 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
13963 instruct maxI_reg_immM1(iRegINoSp dst, iRegIorL2I src, immI_M1 imm)
13964 %{
13965 match(Set dst (MaxI src imm));
13966 ins_cost(INSN_COST * 3);
13967 expand %{
13968 rFlagsReg cr;
13969 compI_reg_imm0(cr, src);
13970 cmovI_reg_immM1_ge(dst, src, cr);
13971 %}
13972 %}
13973
13974 // This pattern is automatically generated from aarch64_ad.m4
13975 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
13976 instruct maxI_immM1_reg(iRegINoSp dst, immI_M1 imm, iRegIorL2I src)
13977 %{
13978 match(Set dst (MaxI imm src));
13979 ins_cost(INSN_COST * 3);
13980 expand %{
13981 rFlagsReg cr;
13982 compI_reg_imm0(cr, src);
13983 cmovI_reg_immM1_ge(dst, src, cr);
13984 %}
13985 %}
13986
13987 // This pattern is automatically generated from aarch64_ad.m4
13988 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
13989 instruct bits_reverse_I(iRegINoSp dst, iRegIorL2I src)
13990 %{
13991 match(Set dst (ReverseI src));
13992 ins_cost(INSN_COST);
13993 format %{ "rbitw $dst, $src" %}
13994 ins_encode %{
13995 __ rbitw($dst$$Register, $src$$Register);
13996 %}
13997 ins_pipe(ialu_reg);
13998 %}
13999
14000 // This pattern is automatically generated from aarch64_ad.m4
14001 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
14002 instruct bits_reverse_L(iRegLNoSp dst, iRegL src)
14003 %{
14004 match(Set dst (ReverseL src));
14005 ins_cost(INSN_COST);
14006 format %{ "rbit $dst, $src" %}
14007 ins_encode %{
14008 __ rbit($dst$$Register, $src$$Register);
14009 %}
14010 ins_pipe(ialu_reg);
14011 %}
14012
14013
14014 // END This section of the file is automatically generated. Do not edit --------------
14015
14016
14017 // ============================================================================
14018 // Floating Point Arithmetic Instructions
14019
14020 instruct addF_reg_reg(vRegF dst, vRegF src1, vRegF src2) %{
14021 match(Set dst (AddF src1 src2));
14022
14023 ins_cost(INSN_COST * 5);
14024 format %{ "fadds $dst, $src1, $src2" %}
14025
14026 ins_encode %{
14027 __ fadds(as_FloatRegister($dst$$reg),
14028 as_FloatRegister($src1$$reg),
14029 as_FloatRegister($src2$$reg));
14030 %}
14031
14032 ins_pipe(fp_dop_reg_reg_s);
14033 %}
14034
14035 instruct addD_reg_reg(vRegD dst, vRegD src1, vRegD src2) %{
14036 match(Set dst (AddD src1 src2));
14037
14038 ins_cost(INSN_COST * 5);
14039 format %{ "faddd $dst, $src1, $src2" %}
14040
14041 ins_encode %{
14042 __ faddd(as_FloatRegister($dst$$reg),
14043 as_FloatRegister($src1$$reg),
14044 as_FloatRegister($src2$$reg));
14045 %}
14046
14047 ins_pipe(fp_dop_reg_reg_d);
14048 %}
14049
14050 instruct subF_reg_reg(vRegF dst, vRegF src1, vRegF src2) %{
14051 match(Set dst (SubF src1 src2));
14052
14053 ins_cost(INSN_COST * 5);
14054 format %{ "fsubs $dst, $src1, $src2" %}
14055
14056 ins_encode %{
14057 __ fsubs(as_FloatRegister($dst$$reg),
14058 as_FloatRegister($src1$$reg),
14059 as_FloatRegister($src2$$reg));
14060 %}
14061
14062 ins_pipe(fp_dop_reg_reg_s);
14063 %}
14064
14065 instruct subD_reg_reg(vRegD dst, vRegD src1, vRegD src2) %{
14066 match(Set dst (SubD src1 src2));
14067
14068 ins_cost(INSN_COST * 5);
14069 format %{ "fsubd $dst, $src1, $src2" %}
14070
14071 ins_encode %{
14072 __ fsubd(as_FloatRegister($dst$$reg),
14073 as_FloatRegister($src1$$reg),
14074 as_FloatRegister($src2$$reg));
14075 %}
14076
14077 ins_pipe(fp_dop_reg_reg_d);
14078 %}
14079
14080 instruct mulF_reg_reg(vRegF dst, vRegF src1, vRegF src2) %{
14081 match(Set dst (MulF src1 src2));
14082
14083 ins_cost(INSN_COST * 6);
14084 format %{ "fmuls $dst, $src1, $src2" %}
14085
14086 ins_encode %{
14087 __ fmuls(as_FloatRegister($dst$$reg),
14088 as_FloatRegister($src1$$reg),
14089 as_FloatRegister($src2$$reg));
14090 %}
14091
14092 ins_pipe(fp_dop_reg_reg_s);
14093 %}
14094
14095 instruct mulD_reg_reg(vRegD dst, vRegD src1, vRegD src2) %{
14096 match(Set dst (MulD src1 src2));
14097
14098 ins_cost(INSN_COST * 6);
14099 format %{ "fmuld $dst, $src1, $src2" %}
14100
14101 ins_encode %{
14102 __ fmuld(as_FloatRegister($dst$$reg),
14103 as_FloatRegister($src1$$reg),
14104 as_FloatRegister($src2$$reg));
14105 %}
14106
14107 ins_pipe(fp_dop_reg_reg_d);
14108 %}
14109
14110 // src1 * src2 + src3
14111 instruct maddF_reg_reg(vRegF dst, vRegF src1, vRegF src2, vRegF src3) %{
14112 predicate(UseFMA);
14113 match(Set dst (FmaF src3 (Binary src1 src2)));
14114
14115 format %{ "fmadds $dst, $src1, $src2, $src3" %}
14116
14117 ins_encode %{
14118 __ fmadds(as_FloatRegister($dst$$reg),
14119 as_FloatRegister($src1$$reg),
14120 as_FloatRegister($src2$$reg),
14121 as_FloatRegister($src3$$reg));
14122 %}
14123
14124 ins_pipe(pipe_class_default);
14125 %}
14126
14127 // src1 * src2 + src3
14128 instruct maddD_reg_reg(vRegD dst, vRegD src1, vRegD src2, vRegD src3) %{
14129 predicate(UseFMA);
14130 match(Set dst (FmaD src3 (Binary src1 src2)));
14131
14132 format %{ "fmaddd $dst, $src1, $src2, $src3" %}
14133
14134 ins_encode %{
14135 __ fmaddd(as_FloatRegister($dst$$reg),
14136 as_FloatRegister($src1$$reg),
14137 as_FloatRegister($src2$$reg),
14138 as_FloatRegister($src3$$reg));
14139 %}
14140
14141 ins_pipe(pipe_class_default);
14142 %}
14143
14144 // -src1 * src2 + src3
14145 instruct msubF_reg_reg(vRegF dst, vRegF src1, vRegF src2, vRegF src3) %{
14146 predicate(UseFMA);
14147 match(Set dst (FmaF src3 (Binary (NegF src1) src2)));
14148 match(Set dst (FmaF src3 (Binary src1 (NegF src2))));
14149
14150 format %{ "fmsubs $dst, $src1, $src2, $src3" %}
14151
14152 ins_encode %{
14153 __ fmsubs(as_FloatRegister($dst$$reg),
14154 as_FloatRegister($src1$$reg),
14155 as_FloatRegister($src2$$reg),
14156 as_FloatRegister($src3$$reg));
14157 %}
14158
14159 ins_pipe(pipe_class_default);
14160 %}
14161
14162 // -src1 * src2 + src3
14163 instruct msubD_reg_reg(vRegD dst, vRegD src1, vRegD src2, vRegD src3) %{
14164 predicate(UseFMA);
14165 match(Set dst (FmaD src3 (Binary (NegD src1) src2)));
14166 match(Set dst (FmaD src3 (Binary src1 (NegD src2))));
14167
14168 format %{ "fmsubd $dst, $src1, $src2, $src3" %}
14169
14170 ins_encode %{
14171 __ fmsubd(as_FloatRegister($dst$$reg),
14172 as_FloatRegister($src1$$reg),
14173 as_FloatRegister($src2$$reg),
14174 as_FloatRegister($src3$$reg));
14175 %}
14176
14177 ins_pipe(pipe_class_default);
14178 %}
14179
14180 // -src1 * src2 - src3
14181 instruct mnaddF_reg_reg(vRegF dst, vRegF src1, vRegF src2, vRegF src3) %{
14182 predicate(UseFMA);
14183 match(Set dst (FmaF (NegF src3) (Binary (NegF src1) src2)));
14184 match(Set dst (FmaF (NegF src3) (Binary src1 (NegF src2))));
14185
14186 format %{ "fnmadds $dst, $src1, $src2, $src3" %}
14187
14188 ins_encode %{
14189 __ fnmadds(as_FloatRegister($dst$$reg),
14190 as_FloatRegister($src1$$reg),
14191 as_FloatRegister($src2$$reg),
14192 as_FloatRegister($src3$$reg));
14193 %}
14194
14195 ins_pipe(pipe_class_default);
14196 %}
14197
14198 // -src1 * src2 - src3
14199 instruct mnaddD_reg_reg(vRegD dst, vRegD src1, vRegD src2, vRegD src3) %{
14200 predicate(UseFMA);
14201 match(Set dst (FmaD (NegD src3) (Binary (NegD src1) src2)));
14202 match(Set dst (FmaD (NegD src3) (Binary src1 (NegD src2))));
14203
14204 format %{ "fnmaddd $dst, $src1, $src2, $src3" %}
14205
14206 ins_encode %{
14207 __ fnmaddd(as_FloatRegister($dst$$reg),
14208 as_FloatRegister($src1$$reg),
14209 as_FloatRegister($src2$$reg),
14210 as_FloatRegister($src3$$reg));
14211 %}
14212
14213 ins_pipe(pipe_class_default);
14214 %}
14215
14216 // src1 * src2 - src3
14217 instruct mnsubF_reg_reg(vRegF dst, vRegF src1, vRegF src2, vRegF src3, immF0 zero) %{
14218 predicate(UseFMA);
14219 match(Set dst (FmaF (NegF src3) (Binary src1 src2)));
14220
14221 format %{ "fnmsubs $dst, $src1, $src2, $src3" %}
14222
14223 ins_encode %{
14224 __ fnmsubs(as_FloatRegister($dst$$reg),
14225 as_FloatRegister($src1$$reg),
14226 as_FloatRegister($src2$$reg),
14227 as_FloatRegister($src3$$reg));
14228 %}
14229
14230 ins_pipe(pipe_class_default);
14231 %}
14232
14233 // src1 * src2 - src3
14234 instruct mnsubD_reg_reg(vRegD dst, vRegD src1, vRegD src2, vRegD src3, immD0 zero) %{
14235 predicate(UseFMA);
14236 match(Set dst (FmaD (NegD src3) (Binary src1 src2)));
14237
14238 format %{ "fnmsubd $dst, $src1, $src2, $src3" %}
14239
14240 ins_encode %{
14241 // n.b. insn name should be fnmsubd
14242 __ fnmsub(as_FloatRegister($dst$$reg),
14243 as_FloatRegister($src1$$reg),
14244 as_FloatRegister($src2$$reg),
14245 as_FloatRegister($src3$$reg));
14246 %}
14247
14248 ins_pipe(pipe_class_default);
14249 %}
14250
14251
14252 // Math.max(FF)F
14253 instruct maxF_reg_reg(vRegF dst, vRegF src1, vRegF src2) %{
14254 match(Set dst (MaxF src1 src2));
14255
14256 format %{ "fmaxs $dst, $src1, $src2" %}
14257 ins_encode %{
14258 __ fmaxs(as_FloatRegister($dst$$reg),
14259 as_FloatRegister($src1$$reg),
14260 as_FloatRegister($src2$$reg));
14261 %}
14262
14263 ins_pipe(fp_dop_reg_reg_s);
14264 %}
14265
14266 // Math.min(FF)F
14267 instruct minF_reg_reg(vRegF dst, vRegF src1, vRegF src2) %{
14268 match(Set dst (MinF src1 src2));
14269
14270 format %{ "fmins $dst, $src1, $src2" %}
14271 ins_encode %{
14272 __ fmins(as_FloatRegister($dst$$reg),
14273 as_FloatRegister($src1$$reg),
14274 as_FloatRegister($src2$$reg));
14275 %}
14276
14277 ins_pipe(fp_dop_reg_reg_s);
14278 %}
14279
14280 // Math.max(DD)D
14281 instruct maxD_reg_reg(vRegD dst, vRegD src1, vRegD src2) %{
14282 match(Set dst (MaxD src1 src2));
14283
14284 format %{ "fmaxd $dst, $src1, $src2" %}
14285 ins_encode %{
14286 __ fmaxd(as_FloatRegister($dst$$reg),
14287 as_FloatRegister($src1$$reg),
14288 as_FloatRegister($src2$$reg));
14289 %}
14290
14291 ins_pipe(fp_dop_reg_reg_d);
14292 %}
14293
14294 // Math.min(DD)D
14295 instruct minD_reg_reg(vRegD dst, vRegD src1, vRegD src2) %{
14296 match(Set dst (MinD src1 src2));
14297
14298 format %{ "fmind $dst, $src1, $src2" %}
14299 ins_encode %{
14300 __ fmind(as_FloatRegister($dst$$reg),
14301 as_FloatRegister($src1$$reg),
14302 as_FloatRegister($src2$$reg));
14303 %}
14304
14305 ins_pipe(fp_dop_reg_reg_d);
14306 %}
14307
14308
14309 instruct divF_reg_reg(vRegF dst, vRegF src1, vRegF src2) %{
14310 match(Set dst (DivF src1 src2));
14311
14312 ins_cost(INSN_COST * 18);
14313 format %{ "fdivs $dst, $src1, $src2" %}
14314
14315 ins_encode %{
14316 __ fdivs(as_FloatRegister($dst$$reg),
14317 as_FloatRegister($src1$$reg),
14318 as_FloatRegister($src2$$reg));
14319 %}
14320
14321 ins_pipe(fp_div_s);
14322 %}
14323
14324 instruct divD_reg_reg(vRegD dst, vRegD src1, vRegD src2) %{
14325 match(Set dst (DivD src1 src2));
14326
14327 ins_cost(INSN_COST * 32);
14328 format %{ "fdivd $dst, $src1, $src2" %}
14329
14330 ins_encode %{
14331 __ fdivd(as_FloatRegister($dst$$reg),
14332 as_FloatRegister($src1$$reg),
14333 as_FloatRegister($src2$$reg));
14334 %}
14335
14336 ins_pipe(fp_div_d);
14337 %}
14338
14339 instruct negF_reg_reg(vRegF dst, vRegF src) %{
14340 match(Set dst (NegF src));
14341
14342 ins_cost(INSN_COST * 3);
14343 format %{ "fneg $dst, $src" %}
14344
14345 ins_encode %{
14346 __ fnegs(as_FloatRegister($dst$$reg),
14347 as_FloatRegister($src$$reg));
14348 %}
14349
14350 ins_pipe(fp_uop_s);
14351 %}
14352
14353 instruct negD_reg_reg(vRegD dst, vRegD src) %{
14354 match(Set dst (NegD src));
14355
14356 ins_cost(INSN_COST * 3);
14357 format %{ "fnegd $dst, $src" %}
14358
14359 ins_encode %{
14360 __ fnegd(as_FloatRegister($dst$$reg),
14361 as_FloatRegister($src$$reg));
14362 %}
14363
14364 ins_pipe(fp_uop_d);
14365 %}
14366
14367 instruct absI_reg(iRegINoSp dst, iRegIorL2I src, rFlagsReg cr)
14368 %{
14369 match(Set dst (AbsI src));
14370
14371 effect(KILL cr);
14372 ins_cost(INSN_COST * 2);
14373 format %{ "cmpw $src, zr\n\t"
14374 "cnegw $dst, $src, Assembler::LT\t# int abs"
14375 %}
14376
14377 ins_encode %{
14378 __ cmpw(as_Register($src$$reg), zr);
14379 __ cnegw(as_Register($dst$$reg), as_Register($src$$reg), Assembler::LT);
14380 %}
14381 ins_pipe(pipe_class_default);
14382 %}
14383
14384 instruct absL_reg(iRegLNoSp dst, iRegL src, rFlagsReg cr)
14385 %{
14386 match(Set dst (AbsL src));
14387
14388 effect(KILL cr);
14389 ins_cost(INSN_COST * 2);
14390 format %{ "cmp $src, zr\n\t"
14391 "cneg $dst, $src, Assembler::LT\t# long abs"
14392 %}
14393
14394 ins_encode %{
14395 __ cmp(as_Register($src$$reg), zr);
14396 __ cneg(as_Register($dst$$reg), as_Register($src$$reg), Assembler::LT);
14397 %}
14398 ins_pipe(pipe_class_default);
14399 %}
14400
14401 instruct absF_reg(vRegF dst, vRegF src) %{
14402 match(Set dst (AbsF src));
14403
14404 ins_cost(INSN_COST * 3);
14405 format %{ "fabss $dst, $src" %}
14406 ins_encode %{
14407 __ fabss(as_FloatRegister($dst$$reg),
14408 as_FloatRegister($src$$reg));
14409 %}
14410
14411 ins_pipe(fp_uop_s);
14412 %}
14413
14414 instruct absD_reg(vRegD dst, vRegD src) %{
14415 match(Set dst (AbsD src));
14416
14417 ins_cost(INSN_COST * 3);
14418 format %{ "fabsd $dst, $src" %}
14419 ins_encode %{
14420 __ fabsd(as_FloatRegister($dst$$reg),
14421 as_FloatRegister($src$$reg));
14422 %}
14423
14424 ins_pipe(fp_uop_d);
14425 %}
14426
14427 instruct absdF_reg(vRegF dst, vRegF src1, vRegF src2) %{
14428 match(Set dst (AbsF (SubF src1 src2)));
14429
14430 ins_cost(INSN_COST * 3);
14431 format %{ "fabds $dst, $src1, $src2" %}
14432 ins_encode %{
14433 __ fabds(as_FloatRegister($dst$$reg),
14434 as_FloatRegister($src1$$reg),
14435 as_FloatRegister($src2$$reg));
14436 %}
14437
14438 ins_pipe(fp_uop_s);
14439 %}
14440
14441 instruct absdD_reg(vRegD dst, vRegD src1, vRegD src2) %{
14442 match(Set dst (AbsD (SubD src1 src2)));
14443
14444 ins_cost(INSN_COST * 3);
14445 format %{ "fabdd $dst, $src1, $src2" %}
14446 ins_encode %{
14447 __ fabdd(as_FloatRegister($dst$$reg),
14448 as_FloatRegister($src1$$reg),
14449 as_FloatRegister($src2$$reg));
14450 %}
14451
14452 ins_pipe(fp_uop_d);
14453 %}
14454
14455 instruct sqrtD_reg(vRegD dst, vRegD src) %{
14456 match(Set dst (SqrtD src));
14457
14458 ins_cost(INSN_COST * 50);
14459 format %{ "fsqrtd $dst, $src" %}
14460 ins_encode %{
14461 __ fsqrtd(as_FloatRegister($dst$$reg),
14462 as_FloatRegister($src$$reg));
14463 %}
14464
14465 ins_pipe(fp_div_s);
14466 %}
14467
14468 instruct sqrtF_reg(vRegF dst, vRegF src) %{
14469 match(Set dst (SqrtF src));
14470
14471 ins_cost(INSN_COST * 50);
14472 format %{ "fsqrts $dst, $src" %}
14473 ins_encode %{
14474 __ fsqrts(as_FloatRegister($dst$$reg),
14475 as_FloatRegister($src$$reg));
14476 %}
14477
14478 ins_pipe(fp_div_d);
14479 %}
14480
14481 // Math.rint, floor, ceil
14482 instruct roundD_reg(vRegD dst, vRegD src, immI rmode) %{
14483 match(Set dst (RoundDoubleMode src rmode));
14484 format %{ "frint $dst, $src, $rmode" %}
14485 ins_encode %{
14486 switch ($rmode$$constant) {
14487 case RoundDoubleModeNode::rmode_rint:
14488 __ frintnd(as_FloatRegister($dst$$reg),
14489 as_FloatRegister($src$$reg));
14490 break;
14491 case RoundDoubleModeNode::rmode_floor:
14492 __ frintmd(as_FloatRegister($dst$$reg),
14493 as_FloatRegister($src$$reg));
14494 break;
14495 case RoundDoubleModeNode::rmode_ceil:
14496 __ frintpd(as_FloatRegister($dst$$reg),
14497 as_FloatRegister($src$$reg));
14498 break;
14499 }
14500 %}
14501 ins_pipe(fp_uop_d);
14502 %}
14503
14504 instruct copySignD_reg(vRegD dst, vRegD src1, vRegD src2, vRegD zero) %{
14505 match(Set dst (CopySignD src1 (Binary src2 zero)));
14506 effect(TEMP_DEF dst, USE src1, USE src2, USE zero);
14507 format %{ "CopySignD $dst $src1 $src2" %}
14508 ins_encode %{
14509 FloatRegister dst = as_FloatRegister($dst$$reg),
14510 src1 = as_FloatRegister($src1$$reg),
14511 src2 = as_FloatRegister($src2$$reg),
14512 zero = as_FloatRegister($zero$$reg);
14513 __ fnegd(dst, zero);
14514 __ bsl(dst, __ T8B, src2, src1);
14515 %}
14516 ins_pipe(fp_uop_d);
14517 %}
14518
14519 instruct copySignF_reg(vRegF dst, vRegF src1, vRegF src2) %{
14520 match(Set dst (CopySignF src1 src2));
14521 effect(TEMP_DEF dst, USE src1, USE src2);
14522 format %{ "CopySignF $dst $src1 $src2" %}
14523 ins_encode %{
14524 FloatRegister dst = as_FloatRegister($dst$$reg),
14525 src1 = as_FloatRegister($src1$$reg),
14526 src2 = as_FloatRegister($src2$$reg);
14527 __ movi(dst, __ T2S, 0x80, 24);
14528 __ bsl(dst, __ T8B, src2, src1);
14529 %}
14530 ins_pipe(fp_uop_d);
14531 %}
14532
14533 instruct signumD_reg(vRegD dst, vRegD src, vRegD zero, vRegD one) %{
14534 match(Set dst (SignumD src (Binary zero one)));
14535 effect(TEMP_DEF dst, USE src, USE zero, USE one);
14536 format %{ "signumD $dst, $src" %}
14537 ins_encode %{
14538 FloatRegister src = as_FloatRegister($src$$reg),
14539 dst = as_FloatRegister($dst$$reg),
14540 zero = as_FloatRegister($zero$$reg),
14541 one = as_FloatRegister($one$$reg);
14542 __ facgtd(dst, src, zero); // dst=0 for +-0.0 and NaN. 0xFFF..F otherwise
14543 __ ushrd(dst, dst, 1); // dst=0 for +-0.0 and NaN. 0x7FF..F otherwise
14544 // Bit selection instruction gets bit from "one" for each enabled bit in
14545 // "dst", otherwise gets a bit from "src". For "src" that contains +-0.0 or
14546 // NaN the whole "src" will be copied because "dst" is zero. For all other
14547 // "src" values dst is 0x7FF..F, which means only the sign bit is copied
14548 // from "src", and all other bits are copied from 1.0.
14549 __ bsl(dst, __ T8B, one, src);
14550 %}
14551 ins_pipe(fp_uop_d);
14552 %}
14553
14554 instruct signumF_reg(vRegF dst, vRegF src, vRegF zero, vRegF one) %{
14555 match(Set dst (SignumF src (Binary zero one)));
14556 effect(TEMP_DEF dst, USE src, USE zero, USE one);
14557 format %{ "signumF $dst, $src" %}
14558 ins_encode %{
14559 FloatRegister src = as_FloatRegister($src$$reg),
14560 dst = as_FloatRegister($dst$$reg),
14561 zero = as_FloatRegister($zero$$reg),
14562 one = as_FloatRegister($one$$reg);
14563 __ facgts(dst, src, zero); // dst=0 for +-0.0 and NaN. 0xFFF..F otherwise
14564 __ ushr(dst, __ T2S, dst, 1); // dst=0 for +-0.0 and NaN. 0x7FF..F otherwise
14565 // Bit selection instruction gets bit from "one" for each enabled bit in
14566 // "dst", otherwise gets a bit from "src". For "src" that contains +-0.0 or
14567 // NaN the whole "src" will be copied because "dst" is zero. For all other
14568 // "src" values dst is 0x7FF..F, which means only the sign bit is copied
14569 // from "src", and all other bits are copied from 1.0.
14570 __ bsl(dst, __ T8B, one, src);
14571 %}
14572 ins_pipe(fp_uop_d);
14573 %}
14574
14575 instruct onspinwait() %{
14576 match(OnSpinWait);
14577 ins_cost(INSN_COST);
14578
14579 format %{ "onspinwait" %}
14580
14581 ins_encode %{
14582 __ spin_wait();
14583 %}
14584 ins_pipe(pipe_class_empty);
14585 %}
14586
14587 // ============================================================================
14588 // Logical Instructions
14589
14590 // Integer Logical Instructions
14591
14592 // And Instructions
14593
14594
14595 instruct andI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, rFlagsReg cr) %{
14596 match(Set dst (AndI src1 src2));
14597
14598 format %{ "andw $dst, $src1, $src2\t# int" %}
14599
14600 ins_cost(INSN_COST);
14601 ins_encode %{
14602 __ andw(as_Register($dst$$reg),
14603 as_Register($src1$$reg),
14604 as_Register($src2$$reg));
14605 %}
14606
14607 ins_pipe(ialu_reg_reg);
14608 %}
14609
14610 instruct andI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immILog src2, rFlagsReg cr) %{
14611 match(Set dst (AndI src1 src2));
14612
14613 format %{ "andsw $dst, $src1, $src2\t# int" %}
14614
14615 ins_cost(INSN_COST);
14616 ins_encode %{
14617 __ andw(as_Register($dst$$reg),
14618 as_Register($src1$$reg),
14619 (uint64_t)($src2$$constant));
14620 %}
14621
14622 ins_pipe(ialu_reg_imm);
14623 %}
14624
14625 // Or Instructions
14626
14627 instruct orI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
14628 match(Set dst (OrI src1 src2));
14629
14630 format %{ "orrw $dst, $src1, $src2\t# int" %}
14631
14632 ins_cost(INSN_COST);
14633 ins_encode %{
14634 __ orrw(as_Register($dst$$reg),
14635 as_Register($src1$$reg),
14636 as_Register($src2$$reg));
14637 %}
14638
14639 ins_pipe(ialu_reg_reg);
14640 %}
14641
14642 instruct orI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immILog src2) %{
14643 match(Set dst (OrI src1 src2));
14644
14645 format %{ "orrw $dst, $src1, $src2\t# int" %}
14646
14647 ins_cost(INSN_COST);
14648 ins_encode %{
14649 __ orrw(as_Register($dst$$reg),
14650 as_Register($src1$$reg),
14651 (uint64_t)($src2$$constant));
14652 %}
14653
14654 ins_pipe(ialu_reg_imm);
14655 %}
14656
14657 // Xor Instructions
14658
14659 instruct xorI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
14660 match(Set dst (XorI src1 src2));
14661
14662 format %{ "eorw $dst, $src1, $src2\t# int" %}
14663
14664 ins_cost(INSN_COST);
14665 ins_encode %{
14666 __ eorw(as_Register($dst$$reg),
14667 as_Register($src1$$reg),
14668 as_Register($src2$$reg));
14669 %}
14670
14671 ins_pipe(ialu_reg_reg);
14672 %}
14673
14674 instruct xorI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immILog src2) %{
14675 match(Set dst (XorI src1 src2));
14676
14677 format %{ "eorw $dst, $src1, $src2\t# int" %}
14678
14679 ins_cost(INSN_COST);
14680 ins_encode %{
14681 __ eorw(as_Register($dst$$reg),
14682 as_Register($src1$$reg),
14683 (uint64_t)($src2$$constant));
14684 %}
14685
14686 ins_pipe(ialu_reg_imm);
14687 %}
14688
14689 // Long Logical Instructions
14690 // TODO
14691
14692 instruct andL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2, rFlagsReg cr) %{
14693 match(Set dst (AndL src1 src2));
14694
14695 format %{ "and $dst, $src1, $src2\t# int" %}
14696
14697 ins_cost(INSN_COST);
14698 ins_encode %{
14699 __ andr(as_Register($dst$$reg),
14700 as_Register($src1$$reg),
14701 as_Register($src2$$reg));
14702 %}
14703
14704 ins_pipe(ialu_reg_reg);
14705 %}
14706
14707 instruct andL_reg_imm(iRegLNoSp dst, iRegL src1, immLLog src2, rFlagsReg cr) %{
14708 match(Set dst (AndL src1 src2));
14709
14710 format %{ "and $dst, $src1, $src2\t# int" %}
14711
14712 ins_cost(INSN_COST);
14713 ins_encode %{
14714 __ andr(as_Register($dst$$reg),
14715 as_Register($src1$$reg),
14716 (uint64_t)($src2$$constant));
14717 %}
14718
14719 ins_pipe(ialu_reg_imm);
14720 %}
14721
14722 // Or Instructions
14723
14724 instruct orL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
14725 match(Set dst (OrL src1 src2));
14726
14727 format %{ "orr $dst, $src1, $src2\t# int" %}
14728
14729 ins_cost(INSN_COST);
14730 ins_encode %{
14731 __ orr(as_Register($dst$$reg),
14732 as_Register($src1$$reg),
14733 as_Register($src2$$reg));
14734 %}
14735
14736 ins_pipe(ialu_reg_reg);
14737 %}
14738
14739 instruct orL_reg_imm(iRegLNoSp dst, iRegL src1, immLLog src2) %{
14740 match(Set dst (OrL src1 src2));
14741
14742 format %{ "orr $dst, $src1, $src2\t# int" %}
14743
14744 ins_cost(INSN_COST);
14745 ins_encode %{
14746 __ orr(as_Register($dst$$reg),
14747 as_Register($src1$$reg),
14748 (uint64_t)($src2$$constant));
14749 %}
14750
14751 ins_pipe(ialu_reg_imm);
14752 %}
14753
14754 // Xor Instructions
14755
14756 instruct xorL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
14757 match(Set dst (XorL src1 src2));
14758
14759 format %{ "eor $dst, $src1, $src2\t# int" %}
14760
14761 ins_cost(INSN_COST);
14762 ins_encode %{
14763 __ eor(as_Register($dst$$reg),
14764 as_Register($src1$$reg),
14765 as_Register($src2$$reg));
14766 %}
14767
14768 ins_pipe(ialu_reg_reg);
14769 %}
14770
14771 instruct xorL_reg_imm(iRegLNoSp dst, iRegL src1, immLLog src2) %{
14772 match(Set dst (XorL src1 src2));
14773
14774 ins_cost(INSN_COST);
14775 format %{ "eor $dst, $src1, $src2\t# int" %}
14776
14777 ins_encode %{
14778 __ eor(as_Register($dst$$reg),
14779 as_Register($src1$$reg),
14780 (uint64_t)($src2$$constant));
14781 %}
14782
14783 ins_pipe(ialu_reg_imm);
14784 %}
14785
14786 instruct convI2L_reg_reg(iRegLNoSp dst, iRegIorL2I src)
14787 %{
14788 match(Set dst (ConvI2L src));
14789
14790 ins_cost(INSN_COST);
14791 format %{ "sxtw $dst, $src\t# i2l" %}
14792 ins_encode %{
14793 __ sbfm($dst$$Register, $src$$Register, 0, 31);
14794 %}
14795 ins_pipe(ialu_reg_shift);
14796 %}
14797
14798 // this pattern occurs in bigmath arithmetic
14799 instruct convUI2L_reg_reg(iRegLNoSp dst, iRegIorL2I src, immL_32bits mask)
14800 %{
14801 match(Set dst (AndL (ConvI2L src) mask));
14802
14803 ins_cost(INSN_COST);
14804 format %{ "ubfm $dst, $src, 0, 31\t# ui2l" %}
14805 ins_encode %{
14806 __ ubfm($dst$$Register, $src$$Register, 0, 31);
14807 %}
14808
14809 ins_pipe(ialu_reg_shift);
14810 %}
14811
14812 instruct convL2I_reg(iRegINoSp dst, iRegL src) %{
14813 match(Set dst (ConvL2I src));
14814
14815 ins_cost(INSN_COST);
14816 format %{ "movw $dst, $src \t// l2i" %}
14817
14818 ins_encode %{
14819 __ movw(as_Register($dst$$reg), as_Register($src$$reg));
14820 %}
14821
14822 ins_pipe(ialu_reg);
14823 %}
14824
14825 instruct convD2F_reg(vRegF dst, vRegD src) %{
14826 match(Set dst (ConvD2F src));
14827
14828 ins_cost(INSN_COST * 5);
14829 format %{ "fcvtd $dst, $src \t// d2f" %}
14830
14831 ins_encode %{
14832 __ fcvtd(as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg));
14833 %}
14834
14835 ins_pipe(fp_d2f);
14836 %}
14837
14838 instruct convF2D_reg(vRegD dst, vRegF src) %{
14839 match(Set dst (ConvF2D src));
14840
14841 ins_cost(INSN_COST * 5);
14842 format %{ "fcvts $dst, $src \t// f2d" %}
14843
14844 ins_encode %{
14845 __ fcvts(as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg));
14846 %}
14847
14848 ins_pipe(fp_f2d);
14849 %}
14850
14851 instruct convF2I_reg_reg(iRegINoSp dst, vRegF src) %{
14852 match(Set dst (ConvF2I src));
14853
14854 ins_cost(INSN_COST * 5);
14855 format %{ "fcvtzsw $dst, $src \t// f2i" %}
14856
14857 ins_encode %{
14858 __ fcvtzsw(as_Register($dst$$reg), as_FloatRegister($src$$reg));
14859 %}
14860
14861 ins_pipe(fp_f2i);
14862 %}
14863
14864 instruct convF2L_reg_reg(iRegLNoSp dst, vRegF src) %{
14865 match(Set dst (ConvF2L src));
14866
14867 ins_cost(INSN_COST * 5);
14868 format %{ "fcvtzs $dst, $src \t// f2l" %}
14869
14870 ins_encode %{
14871 __ fcvtzs(as_Register($dst$$reg), as_FloatRegister($src$$reg));
14872 %}
14873
14874 ins_pipe(fp_f2l);
14875 %}
14876
14877 instruct convF2HF_reg_reg(iRegINoSp dst, vRegF src, vRegF tmp) %{
14878 match(Set dst (ConvF2HF src));
14879 format %{ "fcvt $tmp, $src\t# convert single to half precision\n\t"
14880 "smov $dst, $tmp\t# move result from $tmp to $dst"
14881 %}
14882 effect(TEMP tmp);
14883 ins_encode %{
14884 __ flt_to_flt16($dst$$Register, $src$$FloatRegister, $tmp$$FloatRegister);
14885 %}
14886 ins_pipe(pipe_slow);
14887 %}
14888
14889 instruct convHF2F_reg_reg(vRegF dst, iRegINoSp src, vRegF tmp) %{
14890 match(Set dst (ConvHF2F src));
14891 format %{ "mov $tmp, $src\t# move source from $src to $tmp\n\t"
14892 "fcvt $dst, $tmp\t# convert half to single precision"
14893 %}
14894 effect(TEMP tmp);
14895 ins_encode %{
14896 __ flt16_to_flt($dst$$FloatRegister, $src$$Register, $tmp$$FloatRegister);
14897 %}
14898 ins_pipe(pipe_slow);
14899 %}
14900
14901 instruct convI2F_reg_reg(vRegF dst, iRegIorL2I src) %{
14902 match(Set dst (ConvI2F src));
14903
14904 ins_cost(INSN_COST * 5);
14905 format %{ "scvtfws $dst, $src \t// i2f" %}
14906
14907 ins_encode %{
14908 __ scvtfws(as_FloatRegister($dst$$reg), as_Register($src$$reg));
14909 %}
14910
14911 ins_pipe(fp_i2f);
14912 %}
14913
14914 instruct convL2F_reg_reg(vRegF dst, iRegL src) %{
14915 match(Set dst (ConvL2F src));
14916
14917 ins_cost(INSN_COST * 5);
14918 format %{ "scvtfs $dst, $src \t// l2f" %}
14919
14920 ins_encode %{
14921 __ scvtfs(as_FloatRegister($dst$$reg), as_Register($src$$reg));
14922 %}
14923
14924 ins_pipe(fp_l2f);
14925 %}
14926
14927 instruct convD2I_reg_reg(iRegINoSp dst, vRegD src) %{
14928 match(Set dst (ConvD2I src));
14929
14930 ins_cost(INSN_COST * 5);
14931 format %{ "fcvtzdw $dst, $src \t// d2i" %}
14932
14933 ins_encode %{
14934 __ fcvtzdw(as_Register($dst$$reg), as_FloatRegister($src$$reg));
14935 %}
14936
14937 ins_pipe(fp_d2i);
14938 %}
14939
14940 instruct convD2L_reg_reg(iRegLNoSp dst, vRegD src) %{
14941 match(Set dst (ConvD2L src));
14942
14943 ins_cost(INSN_COST * 5);
14944 format %{ "fcvtzd $dst, $src \t// d2l" %}
14945
14946 ins_encode %{
14947 __ fcvtzd(as_Register($dst$$reg), as_FloatRegister($src$$reg));
14948 %}
14949
14950 ins_pipe(fp_d2l);
14951 %}
14952
14953 instruct convI2D_reg_reg(vRegD dst, iRegIorL2I src) %{
14954 match(Set dst (ConvI2D src));
14955
14956 ins_cost(INSN_COST * 5);
14957 format %{ "scvtfwd $dst, $src \t// i2d" %}
14958
14959 ins_encode %{
14960 __ scvtfwd(as_FloatRegister($dst$$reg), as_Register($src$$reg));
14961 %}
14962
14963 ins_pipe(fp_i2d);
14964 %}
14965
14966 instruct convL2D_reg_reg(vRegD dst, iRegL src) %{
14967 match(Set dst (ConvL2D src));
14968
14969 ins_cost(INSN_COST * 5);
14970 format %{ "scvtfd $dst, $src \t// l2d" %}
14971
14972 ins_encode %{
14973 __ scvtfd(as_FloatRegister($dst$$reg), as_Register($src$$reg));
14974 %}
14975
14976 ins_pipe(fp_l2d);
14977 %}
14978
14979 instruct round_double_reg(iRegLNoSp dst, vRegD src, vRegD ftmp, rFlagsReg cr)
14980 %{
14981 match(Set dst (RoundD src));
14982 effect(TEMP_DEF dst, TEMP ftmp, KILL cr);
14983 format %{ "java_round_double $dst,$src"%}
14984 ins_encode %{
14985 __ java_round_double($dst$$Register, as_FloatRegister($src$$reg),
14986 as_FloatRegister($ftmp$$reg));
14987 %}
14988 ins_pipe(pipe_slow);
14989 %}
14990
14991 instruct round_float_reg(iRegINoSp dst, vRegF src, vRegF ftmp, rFlagsReg cr)
14992 %{
14993 match(Set dst (RoundF src));
14994 effect(TEMP_DEF dst, TEMP ftmp, KILL cr);
14995 format %{ "java_round_float $dst,$src"%}
14996 ins_encode %{
14997 __ java_round_float($dst$$Register, as_FloatRegister($src$$reg),
14998 as_FloatRegister($ftmp$$reg));
14999 %}
15000 ins_pipe(pipe_slow);
15001 %}
15002
15003 // stack <-> reg and reg <-> reg shuffles with no conversion
15004
15005 instruct MoveF2I_stack_reg(iRegINoSp dst, stackSlotF src) %{
15006
15007 match(Set dst (MoveF2I src));
15008
15009 effect(DEF dst, USE src);
15010
15011 ins_cost(4 * INSN_COST);
15012
15013 format %{ "ldrw $dst, $src\t# MoveF2I_stack_reg" %}
15014
15015 ins_encode %{
15016 __ ldrw($dst$$Register, Address(sp, $src$$disp));
15017 %}
15018
15019 ins_pipe(iload_reg_reg);
15020
15021 %}
15022
15023 instruct MoveI2F_stack_reg(vRegF dst, stackSlotI src) %{
15024
15025 match(Set dst (MoveI2F src));
15026
15027 effect(DEF dst, USE src);
15028
15029 ins_cost(4 * INSN_COST);
15030
15031 format %{ "ldrs $dst, $src\t# MoveI2F_stack_reg" %}
15032
15033 ins_encode %{
15034 __ ldrs(as_FloatRegister($dst$$reg), Address(sp, $src$$disp));
15035 %}
15036
15037 ins_pipe(pipe_class_memory);
15038
15039 %}
15040
15041 instruct MoveD2L_stack_reg(iRegLNoSp dst, stackSlotD src) %{
15042
15043 match(Set dst (MoveD2L src));
15044
15045 effect(DEF dst, USE src);
15046
15047 ins_cost(4 * INSN_COST);
15048
15049 format %{ "ldr $dst, $src\t# MoveD2L_stack_reg" %}
15050
15051 ins_encode %{
15052 __ ldr($dst$$Register, Address(sp, $src$$disp));
15053 %}
15054
15055 ins_pipe(iload_reg_reg);
15056
15057 %}
15058
15059 instruct MoveL2D_stack_reg(vRegD dst, stackSlotL src) %{
15060
15061 match(Set dst (MoveL2D src));
15062
15063 effect(DEF dst, USE src);
15064
15065 ins_cost(4 * INSN_COST);
15066
15067 format %{ "ldrd $dst, $src\t# MoveL2D_stack_reg" %}
15068
15069 ins_encode %{
15070 __ ldrd(as_FloatRegister($dst$$reg), Address(sp, $src$$disp));
15071 %}
15072
15073 ins_pipe(pipe_class_memory);
15074
15075 %}
15076
15077 instruct MoveF2I_reg_stack(stackSlotI dst, vRegF src) %{
15078
15079 match(Set dst (MoveF2I src));
15080
15081 effect(DEF dst, USE src);
15082
15083 ins_cost(INSN_COST);
15084
15085 format %{ "strs $src, $dst\t# MoveF2I_reg_stack" %}
15086
15087 ins_encode %{
15088 __ strs(as_FloatRegister($src$$reg), Address(sp, $dst$$disp));
15089 %}
15090
15091 ins_pipe(pipe_class_memory);
15092
15093 %}
15094
15095 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{
15096
15097 match(Set dst (MoveI2F src));
15098
15099 effect(DEF dst, USE src);
15100
15101 ins_cost(INSN_COST);
15102
15103 format %{ "strw $src, $dst\t# MoveI2F_reg_stack" %}
15104
15105 ins_encode %{
15106 __ strw($src$$Register, Address(sp, $dst$$disp));
15107 %}
15108
15109 ins_pipe(istore_reg_reg);
15110
15111 %}
15112
15113 instruct MoveD2L_reg_stack(stackSlotL dst, vRegD src) %{
15114
15115 match(Set dst (MoveD2L src));
15116
15117 effect(DEF dst, USE src);
15118
15119 ins_cost(INSN_COST);
15120
15121 format %{ "strd $dst, $src\t# MoveD2L_reg_stack" %}
15122
15123 ins_encode %{
15124 __ strd(as_FloatRegister($src$$reg), Address(sp, $dst$$disp));
15125 %}
15126
15127 ins_pipe(pipe_class_memory);
15128
15129 %}
15130
15131 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{
15132
15133 match(Set dst (MoveL2D src));
15134
15135 effect(DEF dst, USE src);
15136
15137 ins_cost(INSN_COST);
15138
15139 format %{ "str $src, $dst\t# MoveL2D_reg_stack" %}
15140
15141 ins_encode %{
15142 __ str($src$$Register, Address(sp, $dst$$disp));
15143 %}
15144
15145 ins_pipe(istore_reg_reg);
15146
15147 %}
15148
15149 instruct MoveF2I_reg_reg(iRegINoSp dst, vRegF src) %{
15150
15151 match(Set dst (MoveF2I src));
15152
15153 effect(DEF dst, USE src);
15154
15155 ins_cost(INSN_COST);
15156
15157 format %{ "fmovs $dst, $src\t# MoveF2I_reg_reg" %}
15158
15159 ins_encode %{
15160 __ fmovs($dst$$Register, as_FloatRegister($src$$reg));
15161 %}
15162
15163 ins_pipe(fp_f2i);
15164
15165 %}
15166
15167 instruct MoveI2F_reg_reg(vRegF dst, iRegI src) %{
15168
15169 match(Set dst (MoveI2F src));
15170
15171 effect(DEF dst, USE src);
15172
15173 ins_cost(INSN_COST);
15174
15175 format %{ "fmovs $dst, $src\t# MoveI2F_reg_reg" %}
15176
15177 ins_encode %{
15178 __ fmovs(as_FloatRegister($dst$$reg), $src$$Register);
15179 %}
15180
15181 ins_pipe(fp_i2f);
15182
15183 %}
15184
15185 instruct MoveD2L_reg_reg(iRegLNoSp dst, vRegD src) %{
15186
15187 match(Set dst (MoveD2L src));
15188
15189 effect(DEF dst, USE src);
15190
15191 ins_cost(INSN_COST);
15192
15193 format %{ "fmovd $dst, $src\t# MoveD2L_reg_reg" %}
15194
15195 ins_encode %{
15196 __ fmovd($dst$$Register, as_FloatRegister($src$$reg));
15197 %}
15198
15199 ins_pipe(fp_d2l);
15200
15201 %}
15202
15203 instruct MoveL2D_reg_reg(vRegD dst, iRegL src) %{
15204
15205 match(Set dst (MoveL2D src));
15206
15207 effect(DEF dst, USE src);
15208
15209 ins_cost(INSN_COST);
15210
15211 format %{ "fmovd $dst, $src\t# MoveL2D_reg_reg" %}
15212
15213 ins_encode %{
15214 __ fmovd(as_FloatRegister($dst$$reg), $src$$Register);
15215 %}
15216
15217 ins_pipe(fp_l2d);
15218
15219 %}
15220
15221 // ============================================================================
15222 // clearing of an array
15223
15224 instruct clearArray_reg_reg(iRegL_R11 cnt, iRegP_R10 base, Universe dummy, rFlagsReg cr)
15225 %{
15226 match(Set dummy (ClearArray cnt base));
15227 effect(USE_KILL cnt, USE_KILL base, KILL cr);
15228
15229 ins_cost(4 * INSN_COST);
15230 format %{ "ClearArray $cnt, $base" %}
15231
15232 ins_encode %{
15233 address tpc = __ zero_words($base$$Register, $cnt$$Register);
15234 if (tpc == NULL) {
15235 ciEnv::current()->record_failure("CodeCache is full");
15236 return;
15237 }
15238 %}
15239
15240 ins_pipe(pipe_class_memory);
15241 %}
15242
15243 instruct clearArray_imm_reg(immL cnt, iRegP_R10 base, iRegL_R11 temp, Universe dummy, rFlagsReg cr)
15244 %{
15245 predicate((uint64_t)n->in(2)->get_long()
15246 < (uint64_t)(BlockZeroingLowLimit >> LogBytesPerWord));
15247 match(Set dummy (ClearArray cnt base));
15248 effect(TEMP temp, USE_KILL base, KILL cr);
15249
15250 ins_cost(4 * INSN_COST);
15251 format %{ "ClearArray $cnt, $base" %}
15252
15253 ins_encode %{
15254 address tpc = __ zero_words($base$$Register, (uint64_t)$cnt$$constant);
15255 if (tpc == NULL) {
15256 ciEnv::current()->record_failure("CodeCache is full");
15257 return;
15258 }
15259 %}
15260
15261 ins_pipe(pipe_class_memory);
15262 %}
15263
15264 // ============================================================================
15265 // Overflow Math Instructions
15266
15267 instruct overflowAddI_reg_reg(rFlagsReg cr, iRegIorL2I op1, iRegIorL2I op2)
15268 %{
15269 match(Set cr (OverflowAddI op1 op2));
15270
15271 format %{ "cmnw $op1, $op2\t# overflow check int" %}
15272 ins_cost(INSN_COST);
15273 ins_encode %{
15274 __ cmnw($op1$$Register, $op2$$Register);
15275 %}
15276
15277 ins_pipe(icmp_reg_reg);
15278 %}
15279
15280 instruct overflowAddI_reg_imm(rFlagsReg cr, iRegIorL2I op1, immIAddSub op2)
15281 %{
15282 match(Set cr (OverflowAddI op1 op2));
15283
15284 format %{ "cmnw $op1, $op2\t# overflow check int" %}
15285 ins_cost(INSN_COST);
15286 ins_encode %{
15287 __ cmnw($op1$$Register, $op2$$constant);
15288 %}
15289
15290 ins_pipe(icmp_reg_imm);
15291 %}
15292
15293 instruct overflowAddL_reg_reg(rFlagsReg cr, iRegL op1, iRegL op2)
15294 %{
15295 match(Set cr (OverflowAddL op1 op2));
15296
15297 format %{ "cmn $op1, $op2\t# overflow check long" %}
15298 ins_cost(INSN_COST);
15299 ins_encode %{
15300 __ cmn($op1$$Register, $op2$$Register);
15301 %}
15302
15303 ins_pipe(icmp_reg_reg);
15304 %}
15305
15306 instruct overflowAddL_reg_imm(rFlagsReg cr, iRegL op1, immLAddSub op2)
15307 %{
15308 match(Set cr (OverflowAddL op1 op2));
15309
15310 format %{ "adds zr, $op1, $op2\t# overflow check long" %}
15311 ins_cost(INSN_COST);
15312 ins_encode %{
15313 __ adds(zr, $op1$$Register, $op2$$constant);
15314 %}
15315
15316 ins_pipe(icmp_reg_imm);
15317 %}
15318
15319 instruct overflowSubI_reg_reg(rFlagsReg cr, iRegIorL2I op1, iRegIorL2I op2)
15320 %{
15321 match(Set cr (OverflowSubI op1 op2));
15322
15323 format %{ "cmpw $op1, $op2\t# overflow check int" %}
15324 ins_cost(INSN_COST);
15325 ins_encode %{
15326 __ cmpw($op1$$Register, $op2$$Register);
15327 %}
15328
15329 ins_pipe(icmp_reg_reg);
15330 %}
15331
15332 instruct overflowSubI_reg_imm(rFlagsReg cr, iRegIorL2I op1, immIAddSub op2)
15333 %{
15334 match(Set cr (OverflowSubI op1 op2));
15335
15336 format %{ "cmpw $op1, $op2\t# overflow check int" %}
15337 ins_cost(INSN_COST);
15338 ins_encode %{
15339 __ cmpw($op1$$Register, $op2$$constant);
15340 %}
15341
15342 ins_pipe(icmp_reg_imm);
15343 %}
15344
15345 instruct overflowSubL_reg_reg(rFlagsReg cr, iRegL op1, iRegL op2)
15346 %{
15347 match(Set cr (OverflowSubL op1 op2));
15348
15349 format %{ "cmp $op1, $op2\t# overflow check long" %}
15350 ins_cost(INSN_COST);
15351 ins_encode %{
15352 __ cmp($op1$$Register, $op2$$Register);
15353 %}
15354
15355 ins_pipe(icmp_reg_reg);
15356 %}
15357
15358 instruct overflowSubL_reg_imm(rFlagsReg cr, iRegL op1, immLAddSub op2)
15359 %{
15360 match(Set cr (OverflowSubL op1 op2));
15361
15362 format %{ "cmp $op1, $op2\t# overflow check long" %}
15363 ins_cost(INSN_COST);
15364 ins_encode %{
15365 __ subs(zr, $op1$$Register, $op2$$constant);
15366 %}
15367
15368 ins_pipe(icmp_reg_imm);
15369 %}
15370
15371 instruct overflowNegI_reg(rFlagsReg cr, immI0 zero, iRegIorL2I op1)
15372 %{
15373 match(Set cr (OverflowSubI zero op1));
15374
15375 format %{ "cmpw zr, $op1\t# overflow check int" %}
15376 ins_cost(INSN_COST);
15377 ins_encode %{
15378 __ cmpw(zr, $op1$$Register);
15379 %}
15380
15381 ins_pipe(icmp_reg_imm);
15382 %}
15383
15384 instruct overflowNegL_reg(rFlagsReg cr, immI0 zero, iRegL op1)
15385 %{
15386 match(Set cr (OverflowSubL zero op1));
15387
15388 format %{ "cmp zr, $op1\t# overflow check long" %}
15389 ins_cost(INSN_COST);
15390 ins_encode %{
15391 __ cmp(zr, $op1$$Register);
15392 %}
15393
15394 ins_pipe(icmp_reg_imm);
15395 %}
15396
15397 instruct overflowMulI_reg(rFlagsReg cr, iRegIorL2I op1, iRegIorL2I op2)
15398 %{
15399 match(Set cr (OverflowMulI op1 op2));
15400
15401 format %{ "smull rscratch1, $op1, $op2\t# overflow check int\n\t"
15402 "cmp rscratch1, rscratch1, sxtw\n\t"
15403 "movw rscratch1, #0x80000000\n\t"
15404 "cselw rscratch1, rscratch1, zr, NE\n\t"
15405 "cmpw rscratch1, #1" %}
15406 ins_cost(5 * INSN_COST);
15407 ins_encode %{
15408 __ smull(rscratch1, $op1$$Register, $op2$$Register);
15409 __ subs(zr, rscratch1, rscratch1, ext::sxtw); // NE => overflow
15410 __ movw(rscratch1, 0x80000000); // Develop 0 (EQ),
15411 __ cselw(rscratch1, rscratch1, zr, Assembler::NE); // or 0x80000000 (NE)
15412 __ cmpw(rscratch1, 1); // 0x80000000 - 1 => VS
15413 %}
15414
15415 ins_pipe(pipe_slow);
15416 %}
15417
15418 instruct overflowMulI_reg_branch(cmpOp cmp, iRegIorL2I op1, iRegIorL2I op2, label labl, rFlagsReg cr)
15419 %{
15420 match(If cmp (OverflowMulI op1 op2));
15421 predicate(n->in(1)->as_Bool()->_test._test == BoolTest::overflow
15422 || n->in(1)->as_Bool()->_test._test == BoolTest::no_overflow);
15423 effect(USE labl, KILL cr);
15424
15425 format %{ "smull rscratch1, $op1, $op2\t# overflow check int\n\t"
15426 "cmp rscratch1, rscratch1, sxtw\n\t"
15427 "b$cmp $labl" %}
15428 ins_cost(3 * INSN_COST); // Branch is rare so treat as INSN_COST
15429 ins_encode %{
15430 Label* L = $labl$$label;
15431 Assembler::Condition cond = (Assembler::Condition)$cmp$$cmpcode;
15432 __ smull(rscratch1, $op1$$Register, $op2$$Register);
15433 __ subs(zr, rscratch1, rscratch1, ext::sxtw); // NE => overflow
15434 __ br(cond == Assembler::VS ? Assembler::NE : Assembler::EQ, *L);
15435 %}
15436
15437 ins_pipe(pipe_serial);
15438 %}
15439
15440 instruct overflowMulL_reg(rFlagsReg cr, iRegL op1, iRegL op2)
15441 %{
15442 match(Set cr (OverflowMulL op1 op2));
15443
15444 format %{ "mul rscratch1, $op1, $op2\t#overflow check long\n\t"
15445 "smulh rscratch2, $op1, $op2\n\t"
15446 "cmp rscratch2, rscratch1, ASR #63\n\t"
15447 "movw rscratch1, #0x80000000\n\t"
15448 "cselw rscratch1, rscratch1, zr, NE\n\t"
15449 "cmpw rscratch1, #1" %}
15450 ins_cost(6 * INSN_COST);
15451 ins_encode %{
15452 __ mul(rscratch1, $op1$$Register, $op2$$Register); // Result bits 0..63
15453 __ smulh(rscratch2, $op1$$Register, $op2$$Register); // Result bits 64..127
15454 __ cmp(rscratch2, rscratch1, Assembler::ASR, 63); // Top is pure sign ext
15455 __ movw(rscratch1, 0x80000000); // Develop 0 (EQ),
15456 __ cselw(rscratch1, rscratch1, zr, Assembler::NE); // or 0x80000000 (NE)
15457 __ cmpw(rscratch1, 1); // 0x80000000 - 1 => VS
15458 %}
15459
15460 ins_pipe(pipe_slow);
15461 %}
15462
15463 instruct overflowMulL_reg_branch(cmpOp cmp, iRegL op1, iRegL op2, label labl, rFlagsReg cr)
15464 %{
15465 match(If cmp (OverflowMulL op1 op2));
15466 predicate(n->in(1)->as_Bool()->_test._test == BoolTest::overflow
15467 || n->in(1)->as_Bool()->_test._test == BoolTest::no_overflow);
15468 effect(USE labl, KILL cr);
15469
15470 format %{ "mul rscratch1, $op1, $op2\t#overflow check long\n\t"
15471 "smulh rscratch2, $op1, $op2\n\t"
15472 "cmp rscratch2, rscratch1, ASR #63\n\t"
15473 "b$cmp $labl" %}
15474 ins_cost(4 * INSN_COST); // Branch is rare so treat as INSN_COST
15475 ins_encode %{
15476 Label* L = $labl$$label;
15477 Assembler::Condition cond = (Assembler::Condition)$cmp$$cmpcode;
15478 __ mul(rscratch1, $op1$$Register, $op2$$Register); // Result bits 0..63
15479 __ smulh(rscratch2, $op1$$Register, $op2$$Register); // Result bits 64..127
15480 __ cmp(rscratch2, rscratch1, Assembler::ASR, 63); // Top is pure sign ext
15481 __ br(cond == Assembler::VS ? Assembler::NE : Assembler::EQ, *L);
15482 %}
15483
15484 ins_pipe(pipe_serial);
15485 %}
15486
15487 // ============================================================================
15488 // Compare Instructions
15489
15490 instruct compI_reg_reg(rFlagsReg cr, iRegI op1, iRegI op2)
15491 %{
15492 match(Set cr (CmpI op1 op2));
15493
15494 effect(DEF cr, USE op1, USE op2);
15495
15496 ins_cost(INSN_COST);
15497 format %{ "cmpw $op1, $op2" %}
15498
15499 ins_encode(aarch64_enc_cmpw(op1, op2));
15500
15501 ins_pipe(icmp_reg_reg);
15502 %}
15503
15504 instruct compI_reg_immI0(rFlagsReg cr, iRegI op1, immI0 zero)
15505 %{
15506 match(Set cr (CmpI op1 zero));
15507
15508 effect(DEF cr, USE op1);
15509
15510 ins_cost(INSN_COST);
15511 format %{ "cmpw $op1, 0" %}
15512
15513 ins_encode(aarch64_enc_cmpw_imm_addsub(op1, zero));
15514
15515 ins_pipe(icmp_reg_imm);
15516 %}
15517
15518 instruct compI_reg_immIAddSub(rFlagsReg cr, iRegI op1, immIAddSub op2)
15519 %{
15520 match(Set cr (CmpI op1 op2));
15521
15522 effect(DEF cr, USE op1);
15523
15524 ins_cost(INSN_COST);
15525 format %{ "cmpw $op1, $op2" %}
15526
15527 ins_encode(aarch64_enc_cmpw_imm_addsub(op1, op2));
15528
15529 ins_pipe(icmp_reg_imm);
15530 %}
15531
15532 instruct compI_reg_immI(rFlagsReg cr, iRegI op1, immI op2)
15533 %{
15534 match(Set cr (CmpI op1 op2));
15535
15536 effect(DEF cr, USE op1);
15537
15538 ins_cost(INSN_COST * 2);
15539 format %{ "cmpw $op1, $op2" %}
15540
15541 ins_encode(aarch64_enc_cmpw_imm(op1, op2));
15542
15543 ins_pipe(icmp_reg_imm);
15544 %}
15545
15546 // Unsigned compare Instructions; really, same as signed compare
15547 // except it should only be used to feed an If or a CMovI which takes a
15548 // cmpOpU.
15549
15550 instruct compU_reg_reg(rFlagsRegU cr, iRegI op1, iRegI op2)
15551 %{
15552 match(Set cr (CmpU op1 op2));
15553
15554 effect(DEF cr, USE op1, USE op2);
15555
15556 ins_cost(INSN_COST);
15557 format %{ "cmpw $op1, $op2\t# unsigned" %}
15558
15559 ins_encode(aarch64_enc_cmpw(op1, op2));
15560
15561 ins_pipe(icmp_reg_reg);
15562 %}
15563
15564 instruct compU_reg_immI0(rFlagsRegU cr, iRegI op1, immI0 zero)
15565 %{
15566 match(Set cr (CmpU op1 zero));
15567
15568 effect(DEF cr, USE op1);
15569
15570 ins_cost(INSN_COST);
15571 format %{ "cmpw $op1, #0\t# unsigned" %}
15572
15573 ins_encode(aarch64_enc_cmpw_imm_addsub(op1, zero));
15574
15575 ins_pipe(icmp_reg_imm);
15576 %}
15577
15578 instruct compU_reg_immIAddSub(rFlagsRegU cr, iRegI op1, immIAddSub op2)
15579 %{
15580 match(Set cr (CmpU op1 op2));
15581
15582 effect(DEF cr, USE op1);
15583
15584 ins_cost(INSN_COST);
15585 format %{ "cmpw $op1, $op2\t# unsigned" %}
15586
15587 ins_encode(aarch64_enc_cmpw_imm_addsub(op1, op2));
15588
15589 ins_pipe(icmp_reg_imm);
15590 %}
15591
15592 instruct compU_reg_immI(rFlagsRegU cr, iRegI op1, immI op2)
15593 %{
15594 match(Set cr (CmpU op1 op2));
15595
15596 effect(DEF cr, USE op1);
15597
15598 ins_cost(INSN_COST * 2);
15599 format %{ "cmpw $op1, $op2\t# unsigned" %}
15600
15601 ins_encode(aarch64_enc_cmpw_imm(op1, op2));
15602
15603 ins_pipe(icmp_reg_imm);
15604 %}
15605
15606 instruct compL_reg_reg(rFlagsReg cr, iRegL op1, iRegL op2)
15607 %{
15608 match(Set cr (CmpL op1 op2));
15609
15610 effect(DEF cr, USE op1, USE op2);
15611
15612 ins_cost(INSN_COST);
15613 format %{ "cmp $op1, $op2" %}
15614
15615 ins_encode(aarch64_enc_cmp(op1, op2));
15616
15617 ins_pipe(icmp_reg_reg);
15618 %}
15619
15620 instruct compL_reg_immL0(rFlagsReg cr, iRegL op1, immL0 zero)
15621 %{
15622 match(Set cr (CmpL op1 zero));
15623
15624 effect(DEF cr, USE op1);
15625
15626 ins_cost(INSN_COST);
15627 format %{ "tst $op1" %}
15628
15629 ins_encode(aarch64_enc_cmp_imm_addsub(op1, zero));
15630
15631 ins_pipe(icmp_reg_imm);
15632 %}
15633
15634 instruct compL_reg_immLAddSub(rFlagsReg cr, iRegL op1, immLAddSub op2)
15635 %{
15636 match(Set cr (CmpL op1 op2));
15637
15638 effect(DEF cr, USE op1);
15639
15640 ins_cost(INSN_COST);
15641 format %{ "cmp $op1, $op2" %}
15642
15643 ins_encode(aarch64_enc_cmp_imm_addsub(op1, op2));
15644
15645 ins_pipe(icmp_reg_imm);
15646 %}
15647
15648 instruct compL_reg_immL(rFlagsReg cr, iRegL op1, immL op2)
15649 %{
15650 match(Set cr (CmpL op1 op2));
15651
15652 effect(DEF cr, USE op1);
15653
15654 ins_cost(INSN_COST * 2);
15655 format %{ "cmp $op1, $op2" %}
15656
15657 ins_encode(aarch64_enc_cmp_imm(op1, op2));
15658
15659 ins_pipe(icmp_reg_imm);
15660 %}
15661
15662 instruct compUL_reg_reg(rFlagsRegU cr, iRegL op1, iRegL op2)
15663 %{
15664 match(Set cr (CmpUL op1 op2));
15665
15666 effect(DEF cr, USE op1, USE op2);
15667
15668 ins_cost(INSN_COST);
15669 format %{ "cmp $op1, $op2" %}
15670
15671 ins_encode(aarch64_enc_cmp(op1, op2));
15672
15673 ins_pipe(icmp_reg_reg);
15674 %}
15675
15676 instruct compUL_reg_immL0(rFlagsRegU cr, iRegL op1, immL0 zero)
15677 %{
15678 match(Set cr (CmpUL op1 zero));
15679
15680 effect(DEF cr, USE op1);
15681
15682 ins_cost(INSN_COST);
15683 format %{ "tst $op1" %}
15684
15685 ins_encode(aarch64_enc_cmp_imm_addsub(op1, zero));
15686
15687 ins_pipe(icmp_reg_imm);
15688 %}
15689
15690 instruct compUL_reg_immLAddSub(rFlagsRegU cr, iRegL op1, immLAddSub op2)
15691 %{
15692 match(Set cr (CmpUL op1 op2));
15693
15694 effect(DEF cr, USE op1);
15695
15696 ins_cost(INSN_COST);
15697 format %{ "cmp $op1, $op2" %}
15698
15699 ins_encode(aarch64_enc_cmp_imm_addsub(op1, op2));
15700
15701 ins_pipe(icmp_reg_imm);
15702 %}
15703
15704 instruct compUL_reg_immL(rFlagsRegU cr, iRegL op1, immL op2)
15705 %{
15706 match(Set cr (CmpUL op1 op2));
15707
15708 effect(DEF cr, USE op1);
15709
15710 ins_cost(INSN_COST * 2);
15711 format %{ "cmp $op1, $op2" %}
15712
15713 ins_encode(aarch64_enc_cmp_imm(op1, op2));
15714
15715 ins_pipe(icmp_reg_imm);
15716 %}
15717
15718 instruct compP_reg_reg(rFlagsRegU cr, iRegP op1, iRegP op2)
15719 %{
15720 match(Set cr (CmpP op1 op2));
15721
15722 effect(DEF cr, USE op1, USE op2);
15723
15724 ins_cost(INSN_COST);
15725 format %{ "cmp $op1, $op2\t // ptr" %}
15726
15727 ins_encode(aarch64_enc_cmpp(op1, op2));
15728
15729 ins_pipe(icmp_reg_reg);
15730 %}
15731
15732 instruct compN_reg_reg(rFlagsRegU cr, iRegN op1, iRegN op2)
15733 %{
15734 match(Set cr (CmpN op1 op2));
15735
15736 effect(DEF cr, USE op1, USE op2);
15737
15738 ins_cost(INSN_COST);
15739 format %{ "cmp $op1, $op2\t // compressed ptr" %}
15740
15741 ins_encode(aarch64_enc_cmpn(op1, op2));
15742
15743 ins_pipe(icmp_reg_reg);
15744 %}
15745
15746 instruct testP_reg(rFlagsRegU cr, iRegP op1, immP0 zero)
15747 %{
15748 match(Set cr (CmpP op1 zero));
15749
15750 effect(DEF cr, USE op1, USE zero);
15751
15752 ins_cost(INSN_COST);
15753 format %{ "cmp $op1, 0\t // ptr" %}
15754
15755 ins_encode(aarch64_enc_testp(op1));
15756
15757 ins_pipe(icmp_reg_imm);
15758 %}
15759
15760 instruct testN_reg(rFlagsRegU cr, iRegN op1, immN0 zero)
15761 %{
15762 match(Set cr (CmpN op1 zero));
15763
15764 effect(DEF cr, USE op1, USE zero);
15765
15766 ins_cost(INSN_COST);
15767 format %{ "cmp $op1, 0\t // compressed ptr" %}
15768
15769 ins_encode(aarch64_enc_testn(op1));
15770
15771 ins_pipe(icmp_reg_imm);
15772 %}
15773
15774 // FP comparisons
15775 //
15776 // n.b. CmpF/CmpD set a normal flags reg which then gets compared
15777 // using normal cmpOp. See declaration of rFlagsReg for details.
15778
15779 instruct compF_reg_reg(rFlagsReg cr, vRegF src1, vRegF src2)
15780 %{
15781 match(Set cr (CmpF src1 src2));
15782
15783 ins_cost(3 * INSN_COST);
15784 format %{ "fcmps $src1, $src2" %}
15785
15786 ins_encode %{
15787 __ fcmps(as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
15788 %}
15789
15790 ins_pipe(pipe_class_compare);
15791 %}
15792
15793 instruct compF_reg_zero(rFlagsReg cr, vRegF src1, immF0 src2)
15794 %{
15795 match(Set cr (CmpF src1 src2));
15796
15797 ins_cost(3 * INSN_COST);
15798 format %{ "fcmps $src1, 0.0" %}
15799
15800 ins_encode %{
15801 __ fcmps(as_FloatRegister($src1$$reg), 0.0);
15802 %}
15803
15804 ins_pipe(pipe_class_compare);
15805 %}
15806 // FROM HERE
15807
15808 instruct compD_reg_reg(rFlagsReg cr, vRegD src1, vRegD src2)
15809 %{
15810 match(Set cr (CmpD src1 src2));
15811
15812 ins_cost(3 * INSN_COST);
15813 format %{ "fcmpd $src1, $src2" %}
15814
15815 ins_encode %{
15816 __ fcmpd(as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
15817 %}
15818
15819 ins_pipe(pipe_class_compare);
15820 %}
15821
15822 instruct compD_reg_zero(rFlagsReg cr, vRegD src1, immD0 src2)
15823 %{
15824 match(Set cr (CmpD src1 src2));
15825
15826 ins_cost(3 * INSN_COST);
15827 format %{ "fcmpd $src1, 0.0" %}
15828
15829 ins_encode %{
15830 __ fcmpd(as_FloatRegister($src1$$reg), 0.0);
15831 %}
15832
15833 ins_pipe(pipe_class_compare);
15834 %}
15835
15836 instruct compF3_reg_reg(iRegINoSp dst, vRegF src1, vRegF src2, rFlagsReg cr)
15837 %{
15838 match(Set dst (CmpF3 src1 src2));
15839 effect(KILL cr);
15840
15841 ins_cost(5 * INSN_COST);
15842 format %{ "fcmps $src1, $src2\n\t"
15843 "csinvw($dst, zr, zr, eq\n\t"
15844 "csnegw($dst, $dst, $dst, lt)"
15845 %}
15846
15847 ins_encode %{
15848 Label done;
15849 FloatRegister s1 = as_FloatRegister($src1$$reg);
15850 FloatRegister s2 = as_FloatRegister($src2$$reg);
15851 Register d = as_Register($dst$$reg);
15852 __ fcmps(s1, s2);
15853 // installs 0 if EQ else -1
15854 __ csinvw(d, zr, zr, Assembler::EQ);
15855 // keeps -1 if less or unordered else installs 1
15856 __ csnegw(d, d, d, Assembler::LT);
15857 __ bind(done);
15858 %}
15859
15860 ins_pipe(pipe_class_default);
15861
15862 %}
15863
15864 instruct compD3_reg_reg(iRegINoSp dst, vRegD src1, vRegD src2, rFlagsReg cr)
15865 %{
15866 match(Set dst (CmpD3 src1 src2));
15867 effect(KILL cr);
15868
15869 ins_cost(5 * INSN_COST);
15870 format %{ "fcmpd $src1, $src2\n\t"
15871 "csinvw($dst, zr, zr, eq\n\t"
15872 "csnegw($dst, $dst, $dst, lt)"
15873 %}
15874
15875 ins_encode %{
15876 Label done;
15877 FloatRegister s1 = as_FloatRegister($src1$$reg);
15878 FloatRegister s2 = as_FloatRegister($src2$$reg);
15879 Register d = as_Register($dst$$reg);
15880 __ fcmpd(s1, s2);
15881 // installs 0 if EQ else -1
15882 __ csinvw(d, zr, zr, Assembler::EQ);
15883 // keeps -1 if less or unordered else installs 1
15884 __ csnegw(d, d, d, Assembler::LT);
15885 __ bind(done);
15886 %}
15887 ins_pipe(pipe_class_default);
15888
15889 %}
15890
15891 instruct compF3_reg_immF0(iRegINoSp dst, vRegF src1, immF0 zero, rFlagsReg cr)
15892 %{
15893 match(Set dst (CmpF3 src1 zero));
15894 effect(KILL cr);
15895
15896 ins_cost(5 * INSN_COST);
15897 format %{ "fcmps $src1, 0.0\n\t"
15898 "csinvw($dst, zr, zr, eq\n\t"
15899 "csnegw($dst, $dst, $dst, lt)"
15900 %}
15901
15902 ins_encode %{
15903 Label done;
15904 FloatRegister s1 = as_FloatRegister($src1$$reg);
15905 Register d = as_Register($dst$$reg);
15906 __ fcmps(s1, 0.0);
15907 // installs 0 if EQ else -1
15908 __ csinvw(d, zr, zr, Assembler::EQ);
15909 // keeps -1 if less or unordered else installs 1
15910 __ csnegw(d, d, d, Assembler::LT);
15911 __ bind(done);
15912 %}
15913
15914 ins_pipe(pipe_class_default);
15915
15916 %}
15917
15918 instruct compD3_reg_immD0(iRegINoSp dst, vRegD src1, immD0 zero, rFlagsReg cr)
15919 %{
15920 match(Set dst (CmpD3 src1 zero));
15921 effect(KILL cr);
15922
15923 ins_cost(5 * INSN_COST);
15924 format %{ "fcmpd $src1, 0.0\n\t"
15925 "csinvw($dst, zr, zr, eq\n\t"
15926 "csnegw($dst, $dst, $dst, lt)"
15927 %}
15928
15929 ins_encode %{
15930 Label done;
15931 FloatRegister s1 = as_FloatRegister($src1$$reg);
15932 Register d = as_Register($dst$$reg);
15933 __ fcmpd(s1, 0.0);
15934 // installs 0 if EQ else -1
15935 __ csinvw(d, zr, zr, Assembler::EQ);
15936 // keeps -1 if less or unordered else installs 1
15937 __ csnegw(d, d, d, Assembler::LT);
15938 __ bind(done);
15939 %}
15940 ins_pipe(pipe_class_default);
15941
15942 %}
15943
15944 instruct cmpLTMask_reg_reg(iRegINoSp dst, iRegIorL2I p, iRegIorL2I q, rFlagsReg cr)
15945 %{
15946 match(Set dst (CmpLTMask p q));
15947 effect(KILL cr);
15948
15949 ins_cost(3 * INSN_COST);
15950
15951 format %{ "cmpw $p, $q\t# cmpLTMask\n\t"
15952 "csetw $dst, lt\n\t"
15953 "subw $dst, zr, $dst"
15954 %}
15955
15956 ins_encode %{
15957 __ cmpw(as_Register($p$$reg), as_Register($q$$reg));
15958 __ csetw(as_Register($dst$$reg), Assembler::LT);
15959 __ subw(as_Register($dst$$reg), zr, as_Register($dst$$reg));
15960 %}
15961
15962 ins_pipe(ialu_reg_reg);
15963 %}
15964
15965 instruct cmpLTMask_reg_zero(iRegINoSp dst, iRegIorL2I src, immI0 zero, rFlagsReg cr)
15966 %{
15967 match(Set dst (CmpLTMask src zero));
15968 effect(KILL cr);
15969
15970 ins_cost(INSN_COST);
15971
15972 format %{ "asrw $dst, $src, #31\t# cmpLTMask0" %}
15973
15974 ins_encode %{
15975 __ asrw(as_Register($dst$$reg), as_Register($src$$reg), 31);
15976 %}
15977
15978 ins_pipe(ialu_reg_shift);
15979 %}
15980
15981 // ============================================================================
15982 // Max and Min
15983
15984 // Like compI_reg_reg or compI_reg_immI0 but without match rule and second zero parameter.
15985
15986 instruct compI_reg_imm0(rFlagsReg cr, iRegI src)
15987 %{
15988 effect(DEF cr, USE src);
15989 ins_cost(INSN_COST);
15990 format %{ "cmpw $src, 0" %}
15991
15992 ins_encode %{
15993 __ cmpw($src$$Register, 0);
15994 %}
15995 ins_pipe(icmp_reg_imm);
15996 %}
15997
15998 instruct minI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2)
15999 %{
16000 match(Set dst (MinI src1 src2));
16001 ins_cost(INSN_COST * 3);
16002
16003 expand %{
16004 rFlagsReg cr;
16005 compI_reg_reg(cr, src1, src2);
16006 cmovI_reg_reg_lt(dst, src1, src2, cr);
16007 %}
16008 %}
16009
16010 instruct maxI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2)
16011 %{
16012 match(Set dst (MaxI src1 src2));
16013 ins_cost(INSN_COST * 3);
16014
16015 expand %{
16016 rFlagsReg cr;
16017 compI_reg_reg(cr, src1, src2);
16018 cmovI_reg_reg_gt(dst, src1, src2, cr);
16019 %}
16020 %}
16021
16022
16023 // ============================================================================
16024 // Branch Instructions
16025
16026 // Direct Branch.
16027 instruct branch(label lbl)
16028 %{
16029 match(Goto);
16030
16031 effect(USE lbl);
16032
16033 ins_cost(BRANCH_COST);
16034 format %{ "b $lbl" %}
16035
16036 ins_encode(aarch64_enc_b(lbl));
16037
16038 ins_pipe(pipe_branch);
16039 %}
16040
16041 // Conditional Near Branch
16042 instruct branchCon(cmpOp cmp, rFlagsReg cr, label lbl)
16043 %{
16044 // Same match rule as `branchConFar'.
16045 match(If cmp cr);
16046
16047 effect(USE lbl);
16048
16049 ins_cost(BRANCH_COST);
16050 // If set to 1 this indicates that the current instruction is a
16051 // short variant of a long branch. This avoids using this
16052 // instruction in first-pass matching. It will then only be used in
16053 // the `Shorten_branches' pass.
16054 // ins_short_branch(1);
16055 format %{ "b$cmp $lbl" %}
16056
16057 ins_encode(aarch64_enc_br_con(cmp, lbl));
16058
16059 ins_pipe(pipe_branch_cond);
16060 %}
16061
16062 // Conditional Near Branch Unsigned
16063 instruct branchConU(cmpOpU cmp, rFlagsRegU cr, label lbl)
16064 %{
16065 // Same match rule as `branchConFar'.
16066 match(If cmp cr);
16067
16068 effect(USE lbl);
16069
16070 ins_cost(BRANCH_COST);
16071 // If set to 1 this indicates that the current instruction is a
16072 // short variant of a long branch. This avoids using this
16073 // instruction in first-pass matching. It will then only be used in
16074 // the `Shorten_branches' pass.
16075 // ins_short_branch(1);
16076 format %{ "b$cmp $lbl\t# unsigned" %}
16077
16078 ins_encode(aarch64_enc_br_conU(cmp, lbl));
16079
16080 ins_pipe(pipe_branch_cond);
16081 %}
16082
16083 // Make use of CBZ and CBNZ. These instructions, as well as being
16084 // shorter than (cmp; branch), have the additional benefit of not
16085 // killing the flags.
16086
16087 instruct cmpI_imm0_branch(cmpOpEqNe cmp, iRegIorL2I op1, immI0 op2, label labl, rFlagsReg cr) %{
16088 match(If cmp (CmpI op1 op2));
16089 effect(USE labl);
16090
16091 ins_cost(BRANCH_COST);
16092 format %{ "cbw$cmp $op1, $labl" %}
16093 ins_encode %{
16094 Label* L = $labl$$label;
16095 Assembler::Condition cond = (Assembler::Condition)$cmp$$cmpcode;
16096 if (cond == Assembler::EQ)
16097 __ cbzw($op1$$Register, *L);
16098 else
16099 __ cbnzw($op1$$Register, *L);
16100 %}
16101 ins_pipe(pipe_cmp_branch);
16102 %}
16103
16104 instruct cmpL_imm0_branch(cmpOpEqNe cmp, iRegL op1, immL0 op2, label labl, rFlagsReg cr) %{
16105 match(If cmp (CmpL op1 op2));
16106 effect(USE labl);
16107
16108 ins_cost(BRANCH_COST);
16109 format %{ "cb$cmp $op1, $labl" %}
16110 ins_encode %{
16111 Label* L = $labl$$label;
16112 Assembler::Condition cond = (Assembler::Condition)$cmp$$cmpcode;
16113 if (cond == Assembler::EQ)
16114 __ cbz($op1$$Register, *L);
16115 else
16116 __ cbnz($op1$$Register, *L);
16117 %}
16118 ins_pipe(pipe_cmp_branch);
16119 %}
16120
16121 instruct cmpP_imm0_branch(cmpOpEqNe cmp, iRegP op1, immP0 op2, label labl, rFlagsReg cr) %{
16122 match(If cmp (CmpP op1 op2));
16123 effect(USE labl);
16124
16125 ins_cost(BRANCH_COST);
16126 format %{ "cb$cmp $op1, $labl" %}
16127 ins_encode %{
16128 Label* L = $labl$$label;
16129 Assembler::Condition cond = (Assembler::Condition)$cmp$$cmpcode;
16130 if (cond == Assembler::EQ)
16131 __ cbz($op1$$Register, *L);
16132 else
16133 __ cbnz($op1$$Register, *L);
16134 %}
16135 ins_pipe(pipe_cmp_branch);
16136 %}
16137
16138 instruct cmpN_imm0_branch(cmpOpEqNe cmp, iRegN op1, immN0 op2, label labl, rFlagsReg cr) %{
16139 match(If cmp (CmpN op1 op2));
16140 effect(USE labl);
16141
16142 ins_cost(BRANCH_COST);
16143 format %{ "cbw$cmp $op1, $labl" %}
16144 ins_encode %{
16145 Label* L = $labl$$label;
16146 Assembler::Condition cond = (Assembler::Condition)$cmp$$cmpcode;
16147 if (cond == Assembler::EQ)
16148 __ cbzw($op1$$Register, *L);
16149 else
16150 __ cbnzw($op1$$Register, *L);
16151 %}
16152 ins_pipe(pipe_cmp_branch);
16153 %}
16154
16155 instruct cmpP_narrowOop_imm0_branch(cmpOpEqNe cmp, iRegN oop, immP0 zero, label labl, rFlagsReg cr) %{
16156 match(If cmp (CmpP (DecodeN oop) zero));
16157 effect(USE labl);
16158
16159 ins_cost(BRANCH_COST);
16160 format %{ "cb$cmp $oop, $labl" %}
16161 ins_encode %{
16162 Label* L = $labl$$label;
16163 Assembler::Condition cond = (Assembler::Condition)$cmp$$cmpcode;
16164 if (cond == Assembler::EQ)
16165 __ cbzw($oop$$Register, *L);
16166 else
16167 __ cbnzw($oop$$Register, *L);
16168 %}
16169 ins_pipe(pipe_cmp_branch);
16170 %}
16171
16172 instruct cmpUI_imm0_branch(cmpOpUEqNeLtGe cmp, iRegIorL2I op1, immI0 op2, label labl, rFlagsRegU cr) %{
16173 match(If cmp (CmpU op1 op2));
16174 effect(USE labl);
16175
16176 ins_cost(BRANCH_COST);
16177 format %{ "cbw$cmp $op1, $labl" %}
16178 ins_encode %{
16179 Label* L = $labl$$label;
16180 Assembler::Condition cond = (Assembler::Condition)$cmp$$cmpcode;
16181 if (cond == Assembler::EQ || cond == Assembler::LS)
16182 __ cbzw($op1$$Register, *L);
16183 else
16184 __ cbnzw($op1$$Register, *L);
16185 %}
16186 ins_pipe(pipe_cmp_branch);
16187 %}
16188
16189 instruct cmpUL_imm0_branch(cmpOpUEqNeLtGe cmp, iRegL op1, immL0 op2, label labl, rFlagsRegU cr) %{
16190 match(If cmp (CmpUL op1 op2));
16191 effect(USE labl);
16192
16193 ins_cost(BRANCH_COST);
16194 format %{ "cb$cmp $op1, $labl" %}
16195 ins_encode %{
16196 Label* L = $labl$$label;
16197 Assembler::Condition cond = (Assembler::Condition)$cmp$$cmpcode;
16198 if (cond == Assembler::EQ || cond == Assembler::LS)
16199 __ cbz($op1$$Register, *L);
16200 else
16201 __ cbnz($op1$$Register, *L);
16202 %}
16203 ins_pipe(pipe_cmp_branch);
16204 %}
16205
16206 // Test bit and Branch
16207
16208 // Patterns for short (< 32KiB) variants
16209 instruct cmpL_branch_sign(cmpOpLtGe cmp, iRegL op1, immL0 op2, label labl) %{
16210 match(If cmp (CmpL op1 op2));
16211 effect(USE labl);
16212
16213 ins_cost(BRANCH_COST);
16214 format %{ "cb$cmp $op1, $labl # long" %}
16215 ins_encode %{
16216 Label* L = $labl$$label;
16217 Assembler::Condition cond =
16218 ((Assembler::Condition)$cmp$$cmpcode == Assembler::LT) ? Assembler::NE : Assembler::EQ;
16219 __ tbr(cond, $op1$$Register, 63, *L);
16220 %}
16221 ins_pipe(pipe_cmp_branch);
16222 ins_short_branch(1);
16223 %}
16224
16225 instruct cmpI_branch_sign(cmpOpLtGe cmp, iRegIorL2I op1, immI0 op2, label labl) %{
16226 match(If cmp (CmpI op1 op2));
16227 effect(USE labl);
16228
16229 ins_cost(BRANCH_COST);
16230 format %{ "cb$cmp $op1, $labl # int" %}
16231 ins_encode %{
16232 Label* L = $labl$$label;
16233 Assembler::Condition cond =
16234 ((Assembler::Condition)$cmp$$cmpcode == Assembler::LT) ? Assembler::NE : Assembler::EQ;
16235 __ tbr(cond, $op1$$Register, 31, *L);
16236 %}
16237 ins_pipe(pipe_cmp_branch);
16238 ins_short_branch(1);
16239 %}
16240
16241 instruct cmpL_branch_bit(cmpOpEqNe cmp, iRegL op1, immL op2, immL0 op3, label labl) %{
16242 match(If cmp (CmpL (AndL op1 op2) op3));
16243 predicate(is_power_of_2((julong)n->in(2)->in(1)->in(2)->get_long()));
16244 effect(USE labl);
16245
16246 ins_cost(BRANCH_COST);
16247 format %{ "tb$cmp $op1, $op2, $labl" %}
16248 ins_encode %{
16249 Label* L = $labl$$label;
16250 Assembler::Condition cond = (Assembler::Condition)$cmp$$cmpcode;
16251 int bit = exact_log2_long($op2$$constant);
16252 __ tbr(cond, $op1$$Register, bit, *L);
16253 %}
16254 ins_pipe(pipe_cmp_branch);
16255 ins_short_branch(1);
16256 %}
16257
16258 instruct cmpI_branch_bit(cmpOpEqNe cmp, iRegIorL2I op1, immI op2, immI0 op3, label labl) %{
16259 match(If cmp (CmpI (AndI op1 op2) op3));
16260 predicate(is_power_of_2((juint)n->in(2)->in(1)->in(2)->get_int()));
16261 effect(USE labl);
16262
16263 ins_cost(BRANCH_COST);
16264 format %{ "tb$cmp $op1, $op2, $labl" %}
16265 ins_encode %{
16266 Label* L = $labl$$label;
16267 Assembler::Condition cond = (Assembler::Condition)$cmp$$cmpcode;
16268 int bit = exact_log2((juint)$op2$$constant);
16269 __ tbr(cond, $op1$$Register, bit, *L);
16270 %}
16271 ins_pipe(pipe_cmp_branch);
16272 ins_short_branch(1);
16273 %}
16274
16275 // And far variants
16276 instruct far_cmpL_branch_sign(cmpOpLtGe cmp, iRegL op1, immL0 op2, label labl) %{
16277 match(If cmp (CmpL op1 op2));
16278 effect(USE labl);
16279
16280 ins_cost(BRANCH_COST);
16281 format %{ "cb$cmp $op1, $labl # long" %}
16282 ins_encode %{
16283 Label* L = $labl$$label;
16284 Assembler::Condition cond =
16285 ((Assembler::Condition)$cmp$$cmpcode == Assembler::LT) ? Assembler::NE : Assembler::EQ;
16286 __ tbr(cond, $op1$$Register, 63, *L, /*far*/true);
16287 %}
16288 ins_pipe(pipe_cmp_branch);
16289 %}
16290
16291 instruct far_cmpI_branch_sign(cmpOpLtGe cmp, iRegIorL2I op1, immI0 op2, label labl) %{
16292 match(If cmp (CmpI op1 op2));
16293 effect(USE labl);
16294
16295 ins_cost(BRANCH_COST);
16296 format %{ "cb$cmp $op1, $labl # int" %}
16297 ins_encode %{
16298 Label* L = $labl$$label;
16299 Assembler::Condition cond =
16300 ((Assembler::Condition)$cmp$$cmpcode == Assembler::LT) ? Assembler::NE : Assembler::EQ;
16301 __ tbr(cond, $op1$$Register, 31, *L, /*far*/true);
16302 %}
16303 ins_pipe(pipe_cmp_branch);
16304 %}
16305
16306 instruct far_cmpL_branch_bit(cmpOpEqNe cmp, iRegL op1, immL op2, immL0 op3, label labl) %{
16307 match(If cmp (CmpL (AndL op1 op2) op3));
16308 predicate(is_power_of_2((julong)n->in(2)->in(1)->in(2)->get_long()));
16309 effect(USE labl);
16310
16311 ins_cost(BRANCH_COST);
16312 format %{ "tb$cmp $op1, $op2, $labl" %}
16313 ins_encode %{
16314 Label* L = $labl$$label;
16315 Assembler::Condition cond = (Assembler::Condition)$cmp$$cmpcode;
16316 int bit = exact_log2_long($op2$$constant);
16317 __ tbr(cond, $op1$$Register, bit, *L, /*far*/true);
16318 %}
16319 ins_pipe(pipe_cmp_branch);
16320 %}
16321
16322 instruct far_cmpI_branch_bit(cmpOpEqNe cmp, iRegIorL2I op1, immI op2, immI0 op3, label labl) %{
16323 match(If cmp (CmpI (AndI op1 op2) op3));
16324 predicate(is_power_of_2((juint)n->in(2)->in(1)->in(2)->get_int()));
16325 effect(USE labl);
16326
16327 ins_cost(BRANCH_COST);
16328 format %{ "tb$cmp $op1, $op2, $labl" %}
16329 ins_encode %{
16330 Label* L = $labl$$label;
16331 Assembler::Condition cond = (Assembler::Condition)$cmp$$cmpcode;
16332 int bit = exact_log2((juint)$op2$$constant);
16333 __ tbr(cond, $op1$$Register, bit, *L, /*far*/true);
16334 %}
16335 ins_pipe(pipe_cmp_branch);
16336 %}
16337
16338 // Test bits
16339
16340 instruct cmpL_and(cmpOp cmp, iRegL op1, immL op2, immL0 op3, rFlagsReg cr) %{
16341 match(Set cr (CmpL (AndL op1 op2) op3));
16342 predicate(Assembler::operand_valid_for_logical_immediate
16343 (/*is_32*/false, n->in(1)->in(2)->get_long()));
16344
16345 ins_cost(INSN_COST);
16346 format %{ "tst $op1, $op2 # long" %}
16347 ins_encode %{
16348 __ tst($op1$$Register, $op2$$constant);
16349 %}
16350 ins_pipe(ialu_reg_reg);
16351 %}
16352
16353 instruct cmpI_and(cmpOp cmp, iRegIorL2I op1, immI op2, immI0 op3, rFlagsReg cr) %{
16354 match(Set cr (CmpI (AndI op1 op2) op3));
16355 predicate(Assembler::operand_valid_for_logical_immediate
16356 (/*is_32*/true, n->in(1)->in(2)->get_int()));
16357
16358 ins_cost(INSN_COST);
16359 format %{ "tst $op1, $op2 # int" %}
16360 ins_encode %{
16361 __ tstw($op1$$Register, $op2$$constant);
16362 %}
16363 ins_pipe(ialu_reg_reg);
16364 %}
16365
16366 instruct cmpL_and_reg(cmpOp cmp, iRegL op1, iRegL op2, immL0 op3, rFlagsReg cr) %{
16367 match(Set cr (CmpL (AndL op1 op2) op3));
16368
16369 ins_cost(INSN_COST);
16370 format %{ "tst $op1, $op2 # long" %}
16371 ins_encode %{
16372 __ tst($op1$$Register, $op2$$Register);
16373 %}
16374 ins_pipe(ialu_reg_reg);
16375 %}
16376
16377 instruct cmpI_and_reg(cmpOp cmp, iRegIorL2I op1, iRegIorL2I op2, immI0 op3, rFlagsReg cr) %{
16378 match(Set cr (CmpI (AndI op1 op2) op3));
16379
16380 ins_cost(INSN_COST);
16381 format %{ "tstw $op1, $op2 # int" %}
16382 ins_encode %{
16383 __ tstw($op1$$Register, $op2$$Register);
16384 %}
16385 ins_pipe(ialu_reg_reg);
16386 %}
16387
16388
16389 // Conditional Far Branch
16390 // Conditional Far Branch Unsigned
16391 // TODO: fixme
16392
16393 // counted loop end branch near
16394 instruct branchLoopEnd(cmpOp cmp, rFlagsReg cr, label lbl)
16395 %{
16396 match(CountedLoopEnd cmp cr);
16397
16398 effect(USE lbl);
16399
16400 ins_cost(BRANCH_COST);
16401 // short variant.
16402 // ins_short_branch(1);
16403 format %{ "b$cmp $lbl \t// counted loop end" %}
16404
16405 ins_encode(aarch64_enc_br_con(cmp, lbl));
16406
16407 ins_pipe(pipe_branch);
16408 %}
16409
16410 // counted loop end branch far
16411 // TODO: fixme
16412
16413 // ============================================================================
16414 // inlined locking and unlocking
16415
16416 instruct cmpFastLock(rFlagsReg cr, iRegP object, iRegP box, iRegPNoSp tmp, iRegPNoSp tmp2, iRegPNoSp tmp3)
16417 %{
16418 match(Set cr (FastLock object box));
16419 effect(TEMP tmp, TEMP tmp2, TEMP tmp3);
16420
16421 // TODO
16422 // identify correct cost
16423 ins_cost(5 * INSN_COST);
16424 format %{ "fastlock $object,$box\t! kills $tmp,$tmp2" %}
16425
16426 ins_encode %{
16427 __ fast_lock($object$$Register, $box$$Register, $tmp$$Register, $tmp2$$Register, $tmp3$$Register);
16428 %}
16429
16430 ins_pipe(pipe_serial);
16431 %}
16432
16433 instruct cmpFastUnlock(rFlagsReg cr, iRegP object, iRegP box, iRegPNoSp tmp, iRegPNoSp tmp2)
16434 %{
16435 match(Set cr (FastUnlock object box));
16436 effect(TEMP tmp, TEMP tmp2);
16437
16438 ins_cost(5 * INSN_COST);
16439 format %{ "fastunlock $object,$box\t! kills $tmp, $tmp2" %}
16440
16441 ins_encode %{
16442 __ fast_unlock($object$$Register, $box$$Register, $tmp$$Register, $tmp2$$Register);
16443 %}
16444
16445 ins_pipe(pipe_serial);
16446 %}
16447
16448
16449 // ============================================================================
16450 // Safepoint Instructions
16451
16452 // TODO
16453 // provide a near and far version of this code
16454
16455 instruct safePoint(rFlagsReg cr, iRegP poll)
16456 %{
16457 match(SafePoint poll);
16458 effect(KILL cr);
16459
16460 format %{
16461 "ldrw zr, [$poll]\t# Safepoint: poll for GC"
16462 %}
16463 ins_encode %{
16464 __ read_polling_page(as_Register($poll$$reg), relocInfo::poll_type);
16465 %}
16466 ins_pipe(pipe_serial); // ins_pipe(iload_reg_mem);
16467 %}
16468
16469
16470 // ============================================================================
16471 // Procedure Call/Return Instructions
16472
16473 // Call Java Static Instruction
16474
16475 instruct CallStaticJavaDirect(method meth)
16476 %{
16477 match(CallStaticJava);
16478
16479 effect(USE meth);
16480
16481 ins_cost(CALL_COST);
16482
16483 format %{ "call,static $meth \t// ==> " %}
16484
16485 ins_encode(aarch64_enc_java_static_call(meth),
16486 aarch64_enc_call_epilog);
16487
16488 ins_pipe(pipe_class_call);
16489 %}
16490
16491 // TO HERE
16492
16493 // Call Java Dynamic Instruction
16494 instruct CallDynamicJavaDirect(method meth)
16495 %{
16496 match(CallDynamicJava);
16497
16498 effect(USE meth);
16499
16500 ins_cost(CALL_COST);
16501
16502 format %{ "CALL,dynamic $meth \t// ==> " %}
16503
16504 ins_encode(aarch64_enc_java_dynamic_call(meth),
16505 aarch64_enc_call_epilog);
16506
16507 ins_pipe(pipe_class_call);
16508 %}
16509
16510 // Call Runtime Instruction
16511
16512 instruct CallRuntimeDirect(method meth)
16513 %{
16514 match(CallRuntime);
16515
16516 effect(USE meth);
16517
16518 ins_cost(CALL_COST);
16519
16520 format %{ "CALL, runtime $meth" %}
16521
16522 ins_encode( aarch64_enc_java_to_runtime(meth) );
16523
16524 ins_pipe(pipe_class_call);
16525 %}
16526
16527 // Call Runtime Instruction
16528
16529 instruct CallLeafDirect(method meth)
16530 %{
16531 match(CallLeaf);
16532
16533 effect(USE meth);
16534
16535 ins_cost(CALL_COST);
16536
16537 format %{ "CALL, runtime leaf $meth" %}
16538
16539 ins_encode( aarch64_enc_java_to_runtime(meth) );
16540
16541 ins_pipe(pipe_class_call);
16542 %}
16543
16544 // Call Runtime Instruction
16545
16546 instruct CallLeafNoFPDirect(method meth)
16547 %{
16548 match(CallLeafNoFP);
16549
16550 effect(USE meth);
16551
16552 ins_cost(CALL_COST);
16553
16554 format %{ "CALL, runtime leaf nofp $meth" %}
16555
16556 ins_encode( aarch64_enc_java_to_runtime(meth) );
16557
16558 ins_pipe(pipe_class_call);
16559 %}
16560
16561 // Tail Call; Jump from runtime stub to Java code.
16562 // Also known as an 'interprocedural jump'.
16563 // Target of jump will eventually return to caller.
16564 // TailJump below removes the return address.
16565 instruct TailCalljmpInd(iRegPNoSp jump_target, inline_cache_RegP method_ptr)
16566 %{
16567 match(TailCall jump_target method_ptr);
16568
16569 ins_cost(CALL_COST);
16570
16571 format %{ "br $jump_target\t# $method_ptr holds method" %}
16572
16573 ins_encode(aarch64_enc_tail_call(jump_target));
16574
16575 ins_pipe(pipe_class_call);
16576 %}
16577
16578 instruct TailjmpInd(iRegPNoSp jump_target, iRegP_R0 ex_oop)
16579 %{
16580 match(TailJump jump_target ex_oop);
16581
16582 ins_cost(CALL_COST);
16583
16584 format %{ "br $jump_target\t# $ex_oop holds exception oop" %}
16585
16586 ins_encode(aarch64_enc_tail_jmp(jump_target));
16587
16588 ins_pipe(pipe_class_call);
16589 %}
16590
16591 // Create exception oop: created by stack-crawling runtime code.
16592 // Created exception is now available to this handler, and is setup
16593 // just prior to jumping to this handler. No code emitted.
16594 // TODO check
16595 // should ex_oop be in r0? intel uses rax, ppc cannot use r0 so uses rarg1
16596 instruct CreateException(iRegP_R0 ex_oop)
16597 %{
16598 match(Set ex_oop (CreateEx));
16599
16600 format %{ " -- \t// exception oop; no code emitted" %}
16601
16602 size(0);
16603
16604 ins_encode( /*empty*/ );
16605
16606 ins_pipe(pipe_class_empty);
16607 %}
16608
16609 // Rethrow exception: The exception oop will come in the first
16610 // argument position. Then JUMP (not call) to the rethrow stub code.
16611 instruct RethrowException() %{
16612 match(Rethrow);
16613 ins_cost(CALL_COST);
16614
16615 format %{ "b rethrow_stub" %}
16616
16617 ins_encode( aarch64_enc_rethrow() );
16618
16619 ins_pipe(pipe_class_call);
16620 %}
16621
16622
16623 // Return Instruction
16624 // epilog node loads ret address into lr as part of frame pop
16625 instruct Ret()
16626 %{
16627 match(Return);
16628
16629 format %{ "ret\t// return register" %}
16630
16631 ins_encode( aarch64_enc_ret() );
16632
16633 ins_pipe(pipe_branch);
16634 %}
16635
16636 // Die now.
16637 instruct ShouldNotReachHere() %{
16638 match(Halt);
16639
16640 ins_cost(CALL_COST);
16641 format %{ "ShouldNotReachHere" %}
16642
16643 ins_encode %{
16644 if (is_reachable()) {
16645 __ stop(_halt_reason);
16646 }
16647 %}
16648
16649 ins_pipe(pipe_class_default);
16650 %}
16651
16652 // ============================================================================
16653 // Partial Subtype Check
16654 //
16655 // superklass array for an instance of the superklass. Set a hidden
16656 // internal cache on a hit (cache is checked with exposed code in
16657 // gen_subtype_check()). Return NZ for a miss or zero for a hit. The
16658 // encoding ALSO sets flags.
16659
16660 instruct partialSubtypeCheck(iRegP_R4 sub, iRegP_R0 super, iRegP_R2 temp, iRegP_R5 result, rFlagsReg cr)
16661 %{
16662 match(Set result (PartialSubtypeCheck sub super));
16663 effect(KILL cr, KILL temp);
16664
16665 ins_cost(1100); // slightly larger than the next version
16666 format %{ "partialSubtypeCheck $result, $sub, $super" %}
16667
16668 ins_encode(aarch64_enc_partial_subtype_check(sub, super, temp, result));
16669
16670 opcode(0x1); // Force zero of result reg on hit
16671
16672 ins_pipe(pipe_class_memory);
16673 %}
16674
16675 instruct partialSubtypeCheckVsZero(iRegP_R4 sub, iRegP_R0 super, iRegP_R2 temp, iRegP_R5 result, immP0 zero, rFlagsReg cr)
16676 %{
16677 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero));
16678 effect(KILL temp, KILL result);
16679
16680 ins_cost(1100); // slightly larger than the next version
16681 format %{ "partialSubtypeCheck $result, $sub, $super == 0" %}
16682
16683 ins_encode(aarch64_enc_partial_subtype_check(sub, super, temp, result));
16684
16685 opcode(0x0); // Don't zero result reg on hit
16686
16687 ins_pipe(pipe_class_memory);
16688 %}
16689
16690 // Intrisics for String.compareTo()
16691
16692 instruct string_compareU(iRegP_R1 str1, iRegI_R2 cnt1, iRegP_R3 str2, iRegI_R4 cnt2,
16693 iRegI_R0 result, iRegP_R10 tmp1, iRegL_R11 tmp2, rFlagsReg cr)
16694 %{
16695 predicate((UseSVE == 0) && (((StrCompNode*)n)->encoding() == StrIntrinsicNode::UU));
16696 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
16697 effect(KILL tmp1, KILL tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
16698
16699 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result # KILL $tmp1" %}
16700 ins_encode %{
16701 // Count is in 8-bit bytes; non-Compact chars are 16 bits.
16702 __ string_compare($str1$$Register, $str2$$Register,
16703 $cnt1$$Register, $cnt2$$Register, $result$$Register,
16704 $tmp1$$Register, $tmp2$$Register,
16705 fnoreg, fnoreg, fnoreg, pnoreg, pnoreg, StrIntrinsicNode::UU);
16706 %}
16707 ins_pipe(pipe_class_memory);
16708 %}
16709
16710 instruct string_compareL(iRegP_R1 str1, iRegI_R2 cnt1, iRegP_R3 str2, iRegI_R4 cnt2,
16711 iRegI_R0 result, iRegP_R10 tmp1, iRegL_R11 tmp2, rFlagsReg cr)
16712 %{
16713 predicate((UseSVE == 0) && (((StrCompNode*)n)->encoding() == StrIntrinsicNode::LL));
16714 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
16715 effect(KILL tmp1, KILL tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
16716
16717 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result # KILL $tmp1" %}
16718 ins_encode %{
16719 __ string_compare($str1$$Register, $str2$$Register,
16720 $cnt1$$Register, $cnt2$$Register, $result$$Register,
16721 $tmp1$$Register, $tmp2$$Register,
16722 fnoreg, fnoreg, fnoreg, pnoreg, pnoreg, StrIntrinsicNode::LL);
16723 %}
16724 ins_pipe(pipe_class_memory);
16725 %}
16726
16727 instruct string_compareUL(iRegP_R1 str1, iRegI_R2 cnt1, iRegP_R3 str2, iRegI_R4 cnt2,
16728 iRegI_R0 result, iRegP_R10 tmp1, iRegL_R11 tmp2,
16729 vRegD_V0 vtmp1, vRegD_V1 vtmp2, vRegD_V2 vtmp3, rFlagsReg cr)
16730 %{
16731 predicate((UseSVE == 0) && (((StrCompNode*)n)->encoding() == StrIntrinsicNode::UL));
16732 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
16733 effect(KILL tmp1, KILL tmp2, KILL vtmp1, KILL vtmp2, KILL vtmp3,
16734 USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
16735
16736 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result # KILL $tmp1, $tmp2, $vtmp1, $vtmp2, $vtmp3" %}
16737 ins_encode %{
16738 __ string_compare($str1$$Register, $str2$$Register,
16739 $cnt1$$Register, $cnt2$$Register, $result$$Register,
16740 $tmp1$$Register, $tmp2$$Register,
16741 $vtmp1$$FloatRegister, $vtmp2$$FloatRegister,
16742 $vtmp3$$FloatRegister, pnoreg, pnoreg, StrIntrinsicNode::UL);
16743 %}
16744 ins_pipe(pipe_class_memory);
16745 %}
16746
16747 instruct string_compareLU(iRegP_R1 str1, iRegI_R2 cnt1, iRegP_R3 str2, iRegI_R4 cnt2,
16748 iRegI_R0 result, iRegP_R10 tmp1, iRegL_R11 tmp2,
16749 vRegD_V0 vtmp1, vRegD_V1 vtmp2, vRegD_V2 vtmp3, rFlagsReg cr)
16750 %{
16751 predicate((UseSVE == 0) && (((StrCompNode*)n)->encoding() == StrIntrinsicNode::LU));
16752 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
16753 effect(KILL tmp1, KILL tmp2, KILL vtmp1, KILL vtmp2, KILL vtmp3,
16754 USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
16755
16756 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result # KILL $tmp1, $tmp2, $vtmp1, $vtmp2, $vtmp3" %}
16757 ins_encode %{
16758 __ string_compare($str1$$Register, $str2$$Register,
16759 $cnt1$$Register, $cnt2$$Register, $result$$Register,
16760 $tmp1$$Register, $tmp2$$Register,
16761 $vtmp1$$FloatRegister, $vtmp2$$FloatRegister,
16762 $vtmp3$$FloatRegister, pnoreg, pnoreg, StrIntrinsicNode::LU);
16763 %}
16764 ins_pipe(pipe_class_memory);
16765 %}
16766
16767 // Note that Z registers alias the corresponding NEON registers, we declare the vector operands of
16768 // these string_compare variants as NEON register type for convenience so that the prototype of
16769 // string_compare can be shared with all variants.
16770
16771 instruct string_compareLL_sve(iRegP_R1 str1, iRegI_R2 cnt1, iRegP_R3 str2, iRegI_R4 cnt2,
16772 iRegI_R0 result, iRegP_R10 tmp1, iRegL_R11 tmp2,
16773 vRegD_V0 vtmp1, vRegD_V1 vtmp2, pRegGov_P0 pgtmp1,
16774 pRegGov_P1 pgtmp2, rFlagsReg cr)
16775 %{
16776 predicate((UseSVE > 0) && (((StrCompNode*)n)->encoding() == StrIntrinsicNode::LL));
16777 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
16778 effect(TEMP tmp1, TEMP tmp2, TEMP vtmp1, TEMP vtmp2, TEMP pgtmp1, TEMP pgtmp2,
16779 USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
16780
16781 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result # USE sve" %}
16782 ins_encode %{
16783 // Count is in 8-bit bytes; non-Compact chars are 16 bits.
16784 __ string_compare($str1$$Register, $str2$$Register,
16785 $cnt1$$Register, $cnt2$$Register, $result$$Register,
16786 $tmp1$$Register, $tmp2$$Register,
16787 $vtmp1$$FloatRegister, $vtmp2$$FloatRegister, fnoreg,
16788 as_PRegister($pgtmp1$$reg), as_PRegister($pgtmp2$$reg),
16789 StrIntrinsicNode::LL);
16790 %}
16791 ins_pipe(pipe_class_memory);
16792 %}
16793
16794 instruct string_compareLU_sve(iRegP_R1 str1, iRegI_R2 cnt1, iRegP_R3 str2, iRegI_R4 cnt2,
16795 iRegI_R0 result, iRegP_R10 tmp1, iRegL_R11 tmp2,
16796 vRegD_V0 vtmp1, vRegD_V1 vtmp2, pRegGov_P0 pgtmp1,
16797 pRegGov_P1 pgtmp2, rFlagsReg cr)
16798 %{
16799 predicate((UseSVE > 0) && (((StrCompNode*)n)->encoding() == StrIntrinsicNode::LU));
16800 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
16801 effect(TEMP tmp1, TEMP tmp2, TEMP vtmp1, TEMP vtmp2, TEMP pgtmp1, TEMP pgtmp2,
16802 USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
16803
16804 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result # USE sve" %}
16805 ins_encode %{
16806 // Count is in 8-bit bytes; non-Compact chars are 16 bits.
16807 __ string_compare($str1$$Register, $str2$$Register,
16808 $cnt1$$Register, $cnt2$$Register, $result$$Register,
16809 $tmp1$$Register, $tmp2$$Register,
16810 $vtmp1$$FloatRegister, $vtmp2$$FloatRegister, fnoreg,
16811 as_PRegister($pgtmp1$$reg), as_PRegister($pgtmp2$$reg),
16812 StrIntrinsicNode::LU);
16813 %}
16814 ins_pipe(pipe_class_memory);
16815 %}
16816
16817 instruct string_compareUL_sve(iRegP_R1 str1, iRegI_R2 cnt1, iRegP_R3 str2, iRegI_R4 cnt2,
16818 iRegI_R0 result, iRegP_R10 tmp1, iRegL_R11 tmp2,
16819 vRegD_V0 vtmp1, vRegD_V1 vtmp2, pRegGov_P0 pgtmp1,
16820 pRegGov_P1 pgtmp2, rFlagsReg cr)
16821 %{
16822 predicate((UseSVE > 0) && (((StrCompNode*)n)->encoding() == StrIntrinsicNode::UL));
16823 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
16824 effect(TEMP tmp1, TEMP tmp2, TEMP vtmp1, TEMP vtmp2, TEMP pgtmp1, TEMP pgtmp2,
16825 USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
16826
16827 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result # USE sve" %}
16828 ins_encode %{
16829 // Count is in 8-bit bytes; non-Compact chars are 16 bits.
16830 __ string_compare($str1$$Register, $str2$$Register,
16831 $cnt1$$Register, $cnt2$$Register, $result$$Register,
16832 $tmp1$$Register, $tmp2$$Register,
16833 $vtmp1$$FloatRegister, $vtmp2$$FloatRegister, fnoreg,
16834 as_PRegister($pgtmp1$$reg), as_PRegister($pgtmp2$$reg),
16835 StrIntrinsicNode::UL);
16836 %}
16837 ins_pipe(pipe_class_memory);
16838 %}
16839
16840 instruct string_compareUU_sve(iRegP_R1 str1, iRegI_R2 cnt1, iRegP_R3 str2, iRegI_R4 cnt2,
16841 iRegI_R0 result, iRegP_R10 tmp1, iRegL_R11 tmp2,
16842 vRegD_V0 vtmp1, vRegD_V1 vtmp2, pRegGov_P0 pgtmp1,
16843 pRegGov_P1 pgtmp2, rFlagsReg cr)
16844 %{
16845 predicate((UseSVE > 0) && (((StrCompNode*)n)->encoding() == StrIntrinsicNode::UU));
16846 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
16847 effect(TEMP tmp1, TEMP tmp2, TEMP vtmp1, TEMP vtmp2, TEMP pgtmp1, TEMP pgtmp2,
16848 USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
16849
16850 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result # USE sve" %}
16851 ins_encode %{
16852 // Count is in 8-bit bytes; non-Compact chars are 16 bits.
16853 __ string_compare($str1$$Register, $str2$$Register,
16854 $cnt1$$Register, $cnt2$$Register, $result$$Register,
16855 $tmp1$$Register, $tmp2$$Register,
16856 $vtmp1$$FloatRegister, $vtmp2$$FloatRegister, fnoreg,
16857 as_PRegister($pgtmp1$$reg), as_PRegister($pgtmp2$$reg),
16858 StrIntrinsicNode::UU);
16859 %}
16860 ins_pipe(pipe_class_memory);
16861 %}
16862
16863 instruct string_indexofUU(iRegP_R1 str1, iRegI_R4 cnt1, iRegP_R3 str2, iRegI_R2 cnt2,
16864 iRegI_R0 result, iRegINoSp tmp1, iRegINoSp tmp2,
16865 iRegINoSp tmp3, iRegINoSp tmp4, iRegINoSp tmp5, iRegINoSp tmp6,
16866 vRegD_V0 vtmp0, vRegD_V1 vtmp1, rFlagsReg cr)
16867 %{
16868 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU);
16869 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
16870 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2,
16871 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, TEMP tmp6,
16872 TEMP vtmp0, TEMP vtmp1, KILL cr);
16873 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result (UU) "
16874 "# KILL $str1 $cnt1 $str2 $cnt2 $tmp1 $tmp2 $tmp3 $tmp4 $tmp5 $tmp6 V0-V1 cr" %}
16875
16876 ins_encode %{
16877 __ string_indexof($str1$$Register, $str2$$Register,
16878 $cnt1$$Register, $cnt2$$Register,
16879 $tmp1$$Register, $tmp2$$Register,
16880 $tmp3$$Register, $tmp4$$Register,
16881 $tmp5$$Register, $tmp6$$Register,
16882 -1, $result$$Register, StrIntrinsicNode::UU);
16883 %}
16884 ins_pipe(pipe_class_memory);
16885 %}
16886
16887 instruct string_indexofLL(iRegP_R1 str1, iRegI_R4 cnt1, iRegP_R3 str2, iRegI_R2 cnt2,
16888 iRegI_R0 result, iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3,
16889 iRegINoSp tmp4, iRegINoSp tmp5, iRegINoSp tmp6,
16890 vRegD_V0 vtmp0, vRegD_V1 vtmp1, rFlagsReg cr)
16891 %{
16892 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL);
16893 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
16894 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2,
16895 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, TEMP tmp6,
16896 TEMP vtmp0, TEMP vtmp1, KILL cr);
16897 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result (LL) "
16898 "# KILL $str1 $cnt1 $str2 $cnt2 $tmp1 $tmp2 $tmp3 $tmp4 $tmp5 $tmp6 V0-V1 cr" %}
16899
16900 ins_encode %{
16901 __ string_indexof($str1$$Register, $str2$$Register,
16902 $cnt1$$Register, $cnt2$$Register,
16903 $tmp1$$Register, $tmp2$$Register,
16904 $tmp3$$Register, $tmp4$$Register,
16905 $tmp5$$Register, $tmp6$$Register,
16906 -1, $result$$Register, StrIntrinsicNode::LL);
16907 %}
16908 ins_pipe(pipe_class_memory);
16909 %}
16910
16911 instruct string_indexofUL(iRegP_R1 str1, iRegI_R4 cnt1, iRegP_R3 str2, iRegI_R2 cnt2,
16912 iRegI_R0 result, iRegINoSp tmp1, iRegINoSp tmp2,iRegINoSp tmp3,
16913 iRegINoSp tmp4, iRegINoSp tmp5, iRegINoSp tmp6,
16914 vRegD_V0 vtmp0, vRegD_V1 vtmp1, rFlagsReg cr)
16915 %{
16916 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL);
16917 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
16918 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2,
16919 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5,
16920 TEMP tmp6, TEMP vtmp0, TEMP vtmp1, KILL cr);
16921 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result (UL) "
16922 "# KILL $str1 cnt1 $str2 $cnt2 $tmp1 $tmp2 $tmp3 $tmp4 $tmp5 $tmp6 V0-V1 cr" %}
16923
16924 ins_encode %{
16925 __ string_indexof($str1$$Register, $str2$$Register,
16926 $cnt1$$Register, $cnt2$$Register,
16927 $tmp1$$Register, $tmp2$$Register,
16928 $tmp3$$Register, $tmp4$$Register,
16929 $tmp5$$Register, $tmp6$$Register,
16930 -1, $result$$Register, StrIntrinsicNode::UL);
16931 %}
16932 ins_pipe(pipe_class_memory);
16933 %}
16934
16935 instruct string_indexof_conUU(iRegP_R1 str1, iRegI_R4 cnt1, iRegP_R3 str2,
16936 immI_le_4 int_cnt2, iRegI_R0 result, iRegINoSp tmp1,
16937 iRegINoSp tmp2, iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
16938 %{
16939 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU);
16940 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
16941 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1,
16942 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
16943 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result (UU) "
16944 "# KILL $str1 $cnt1 $str2 $tmp1 $tmp2 $tmp3 $tmp4 cr" %}
16945
16946 ins_encode %{
16947 int icnt2 = (int)$int_cnt2$$constant;
16948 __ string_indexof($str1$$Register, $str2$$Register,
16949 $cnt1$$Register, zr,
16950 $tmp1$$Register, $tmp2$$Register,
16951 $tmp3$$Register, $tmp4$$Register, zr, zr,
16952 icnt2, $result$$Register, StrIntrinsicNode::UU);
16953 %}
16954 ins_pipe(pipe_class_memory);
16955 %}
16956
16957 instruct string_indexof_conLL(iRegP_R1 str1, iRegI_R4 cnt1, iRegP_R3 str2,
16958 immI_le_4 int_cnt2, iRegI_R0 result, iRegINoSp tmp1,
16959 iRegINoSp tmp2, iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
16960 %{
16961 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL);
16962 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
16963 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1,
16964 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
16965 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result (LL) "
16966 "# KILL $str1 $cnt1 $str2 $tmp1 $tmp2 $tmp3 $tmp4 cr" %}
16967
16968 ins_encode %{
16969 int icnt2 = (int)$int_cnt2$$constant;
16970 __ string_indexof($str1$$Register, $str2$$Register,
16971 $cnt1$$Register, zr,
16972 $tmp1$$Register, $tmp2$$Register,
16973 $tmp3$$Register, $tmp4$$Register, zr, zr,
16974 icnt2, $result$$Register, StrIntrinsicNode::LL);
16975 %}
16976 ins_pipe(pipe_class_memory);
16977 %}
16978
16979 instruct string_indexof_conUL(iRegP_R1 str1, iRegI_R4 cnt1, iRegP_R3 str2,
16980 immI_1 int_cnt2, iRegI_R0 result, iRegINoSp tmp1,
16981 iRegINoSp tmp2, iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
16982 %{
16983 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL);
16984 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
16985 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1,
16986 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
16987 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result (UL) "
16988 "# KILL $str1 $cnt1 $str2 $tmp1 $tmp2 $tmp3 $tmp4 cr" %}
16989
16990 ins_encode %{
16991 int icnt2 = (int)$int_cnt2$$constant;
16992 __ string_indexof($str1$$Register, $str2$$Register,
16993 $cnt1$$Register, zr,
16994 $tmp1$$Register, $tmp2$$Register,
16995 $tmp3$$Register, $tmp4$$Register, zr, zr,
16996 icnt2, $result$$Register, StrIntrinsicNode::UL);
16997 %}
16998 ins_pipe(pipe_class_memory);
16999 %}
17000
17001 instruct string_indexof_char(iRegP_R1 str1, iRegI_R2 cnt1, iRegI_R3 ch,
17002 iRegI_R0 result, iRegINoSp tmp1, iRegINoSp tmp2,
17003 iRegINoSp tmp3, rFlagsReg cr)
17004 %{
17005 match(Set result (StrIndexOfChar (Binary str1 cnt1) ch));
17006 predicate((UseSVE == 0) && (((StrIndexOfCharNode*)n)->encoding() == StrIntrinsicNode::U));
17007 effect(USE_KILL str1, USE_KILL cnt1, USE_KILL ch,
17008 TEMP tmp1, TEMP tmp2, TEMP tmp3, KILL cr);
17009
17010 format %{ "StringUTF16 IndexOf char[] $str1,$cnt1,$ch -> $result" %}
17011
17012 ins_encode %{
17013 __ string_indexof_char($str1$$Register, $cnt1$$Register, $ch$$Register,
17014 $result$$Register, $tmp1$$Register, $tmp2$$Register,
17015 $tmp3$$Register);
17016 %}
17017 ins_pipe(pipe_class_memory);
17018 %}
17019
17020 instruct stringL_indexof_char(iRegP_R1 str1, iRegI_R2 cnt1, iRegI_R3 ch,
17021 iRegI_R0 result, iRegINoSp tmp1, iRegINoSp tmp2,
17022 iRegINoSp tmp3, rFlagsReg cr)
17023 %{
17024 match(Set result (StrIndexOfChar (Binary str1 cnt1) ch));
17025 predicate((UseSVE == 0) && (((StrIndexOfCharNode*)n)->encoding() == StrIntrinsicNode::L));
17026 effect(USE_KILL str1, USE_KILL cnt1, USE_KILL ch,
17027 TEMP tmp1, TEMP tmp2, TEMP tmp3, KILL cr);
17028
17029 format %{ "StringLatin1 IndexOf char[] $str1,$cnt1,$ch -> $result" %}
17030
17031 ins_encode %{
17032 __ stringL_indexof_char($str1$$Register, $cnt1$$Register, $ch$$Register,
17033 $result$$Register, $tmp1$$Register, $tmp2$$Register,
17034 $tmp3$$Register);
17035 %}
17036 ins_pipe(pipe_class_memory);
17037 %}
17038
17039 instruct stringL_indexof_char_sve(iRegP_R1 str1, iRegI_R2 cnt1, iRegI_R3 ch,
17040 iRegI_R0 result, vecA ztmp1, vecA ztmp2,
17041 pRegGov pgtmp, pReg ptmp, rFlagsReg cr) %{
17042 predicate(UseSVE > 0 && ((StrIndexOfCharNode*)n)->encoding() == StrIntrinsicNode::L);
17043 match(Set result (StrIndexOfChar (Binary str1 cnt1) ch));
17044 effect(TEMP ztmp1, TEMP ztmp2, TEMP pgtmp, TEMP ptmp, KILL cr);
17045 format %{ "StringLatin1 IndexOf char[] $str1,$cnt1,$ch -> $result # use sve" %}
17046 ins_encode %{
17047 __ string_indexof_char_sve($str1$$Register, $cnt1$$Register, $ch$$Register,
17048 $result$$Register, $ztmp1$$FloatRegister,
17049 $ztmp2$$FloatRegister, $pgtmp$$PRegister,
17050 $ptmp$$PRegister, true /* isL */);
17051 %}
17052 ins_pipe(pipe_class_memory);
17053 %}
17054
17055 instruct stringU_indexof_char_sve(iRegP_R1 str1, iRegI_R2 cnt1, iRegI_R3 ch,
17056 iRegI_R0 result, vecA ztmp1, vecA ztmp2,
17057 pRegGov pgtmp, pReg ptmp, rFlagsReg cr) %{
17058 predicate(UseSVE > 0 && ((StrIndexOfCharNode*)n)->encoding() == StrIntrinsicNode::U);
17059 match(Set result (StrIndexOfChar (Binary str1 cnt1) ch));
17060 effect(TEMP ztmp1, TEMP ztmp2, TEMP pgtmp, TEMP ptmp, KILL cr);
17061 format %{ "StringUTF16 IndexOf char[] $str1,$cnt1,$ch -> $result # use sve" %}
17062 ins_encode %{
17063 __ string_indexof_char_sve($str1$$Register, $cnt1$$Register, $ch$$Register,
17064 $result$$Register, $ztmp1$$FloatRegister,
17065 $ztmp2$$FloatRegister, $pgtmp$$PRegister,
17066 $ptmp$$PRegister, false /* isL */);
17067 %}
17068 ins_pipe(pipe_class_memory);
17069 %}
17070
17071 instruct string_equalsL(iRegP_R1 str1, iRegP_R3 str2, iRegI_R4 cnt,
17072 iRegI_R0 result, rFlagsReg cr)
17073 %{
17074 predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::LL);
17075 match(Set result (StrEquals (Binary str1 str2) cnt));
17076 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL cr);
17077
17078 format %{ "String Equals $str1,$str2,$cnt -> $result" %}
17079 ins_encode %{
17080 // Count is in 8-bit bytes; non-Compact chars are 16 bits.
17081 __ string_equals($str1$$Register, $str2$$Register,
17082 $result$$Register, $cnt$$Register, 1);
17083 %}
17084 ins_pipe(pipe_class_memory);
17085 %}
17086
17087 instruct string_equalsU(iRegP_R1 str1, iRegP_R3 str2, iRegI_R4 cnt,
17088 iRegI_R0 result, rFlagsReg cr)
17089 %{
17090 predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::UU);
17091 match(Set result (StrEquals (Binary str1 str2) cnt));
17092 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL cr);
17093
17094 format %{ "String Equals $str1,$str2,$cnt -> $result" %}
17095 ins_encode %{
17096 // Count is in 8-bit bytes; non-Compact chars are 16 bits.
17097 __ string_equals($str1$$Register, $str2$$Register,
17098 $result$$Register, $cnt$$Register, 2);
17099 %}
17100 ins_pipe(pipe_class_memory);
17101 %}
17102
17103 instruct array_equalsB(iRegP_R1 ary1, iRegP_R2 ary2, iRegI_R0 result,
17104 iRegP_R3 tmp1, iRegP_R4 tmp2, iRegP_R5 tmp3,
17105 vRegD_V0 vtmp0, vRegD_V1 vtmp1, vRegD_V2 vtmp2, vRegD_V3 vtmp3,
17106 vRegD_V4 vtmp4, vRegD_V5 vtmp5, vRegD_V6 vtmp6, vRegD_V7 vtmp7,
17107 iRegP_R10 tmp, rFlagsReg cr)
17108 %{
17109 predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::LL);
17110 match(Set result (AryEq ary1 ary2));
17111 effect(KILL tmp, USE_KILL ary1, USE_KILL ary2, TEMP tmp1, TEMP tmp2, TEMP tmp3,
17112 TEMP vtmp0, TEMP vtmp1, TEMP vtmp2, TEMP vtmp3, TEMP vtmp4, TEMP vtmp5,
17113 TEMP vtmp6, TEMP vtmp7, KILL cr);
17114
17115 format %{ "Array Equals $ary1,ary2 -> $result # KILL $ary1 $ary2 $tmp $tmp1 $tmp2 $tmp3 V0-V7 cr" %}
17116 ins_encode %{
17117 address tpc = __ arrays_equals($ary1$$Register, $ary2$$Register,
17118 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
17119 $result$$Register, $tmp$$Register, 1);
17120 if (tpc == NULL) {
17121 ciEnv::current()->record_failure("CodeCache is full");
17122 return;
17123 }
17124 %}
17125 ins_pipe(pipe_class_memory);
17126 %}
17127
17128 instruct array_equalsC(iRegP_R1 ary1, iRegP_R2 ary2, iRegI_R0 result,
17129 iRegP_R3 tmp1, iRegP_R4 tmp2, iRegP_R5 tmp3,
17130 vRegD_V0 vtmp0, vRegD_V1 vtmp1, vRegD_V2 vtmp2, vRegD_V3 vtmp3,
17131 vRegD_V4 vtmp4, vRegD_V5 vtmp5, vRegD_V6 vtmp6, vRegD_V7 vtmp7,
17132 iRegP_R10 tmp, rFlagsReg cr)
17133 %{
17134 predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::UU);
17135 match(Set result (AryEq ary1 ary2));
17136 effect(KILL tmp, USE_KILL ary1, USE_KILL ary2, TEMP tmp1, TEMP tmp2, TEMP tmp3,
17137 TEMP vtmp0, TEMP vtmp1, TEMP vtmp2, TEMP vtmp3, TEMP vtmp4, TEMP vtmp5,
17138 TEMP vtmp6, TEMP vtmp7, KILL cr);
17139
17140 format %{ "Array Equals $ary1,ary2 -> $result # KILL $ary1 $ary2 $tmp $tmp1 $tmp2 $tmp3 V0-V7 cr" %}
17141 ins_encode %{
17142 address tpc = __ arrays_equals($ary1$$Register, $ary2$$Register,
17143 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
17144 $result$$Register, $tmp$$Register, 2);
17145 if (tpc == NULL) {
17146 ciEnv::current()->record_failure("CodeCache is full");
17147 return;
17148 }
17149 %}
17150 ins_pipe(pipe_class_memory);
17151 %}
17152
17153 instruct count_positives(iRegP_R1 ary1, iRegI_R2 len, iRegI_R0 result, rFlagsReg cr)
17154 %{
17155 match(Set result (CountPositives ary1 len));
17156 effect(USE_KILL ary1, USE_KILL len, KILL cr);
17157 format %{ "count positives byte[] $ary1,$len -> $result" %}
17158 ins_encode %{
17159 address tpc = __ count_positives($ary1$$Register, $len$$Register, $result$$Register);
17160 if (tpc == NULL) {
17161 ciEnv::current()->record_failure("CodeCache is full");
17162 return;
17163 }
17164 %}
17165 ins_pipe( pipe_slow );
17166 %}
17167
17168 // fast char[] to byte[] compression
17169 instruct string_compress(iRegP_R2 src, iRegP_R1 dst, iRegI_R3 len,
17170 vRegD_V0 vtmp0, vRegD_V1 vtmp1, vRegD_V2 vtmp2,
17171 vRegD_V3 vtmp3, vRegD_V4 vtmp4, vRegD_V5 vtmp5,
17172 iRegI_R0 result, rFlagsReg cr)
17173 %{
17174 match(Set result (StrCompressedCopy src (Binary dst len)));
17175 effect(TEMP vtmp0, TEMP vtmp1, TEMP vtmp2, TEMP vtmp3, TEMP vtmp4, TEMP vtmp5,
17176 USE_KILL src, USE_KILL dst, USE len, KILL cr);
17177
17178 format %{ "String Compress $src,$dst,$len -> $result # KILL $src $dst V0-V5 cr" %}
17179 ins_encode %{
17180 __ char_array_compress($src$$Register, $dst$$Register, $len$$Register,
17181 $result$$Register, $vtmp0$$FloatRegister, $vtmp1$$FloatRegister,
17182 $vtmp2$$FloatRegister, $vtmp3$$FloatRegister,
17183 $vtmp4$$FloatRegister, $vtmp5$$FloatRegister);
17184 %}
17185 ins_pipe(pipe_slow);
17186 %}
17187
17188 // fast byte[] to char[] inflation
17189 instruct string_inflate(Universe dummy, iRegP_R0 src, iRegP_R1 dst, iRegI_R2 len, iRegP_R3 tmp,
17190 vRegD_V0 vtmp0, vRegD_V1 vtmp1, vRegD_V2 vtmp2, vRegD_V3 vtmp3,
17191 vRegD_V4 vtmp4, vRegD_V5 vtmp5, vRegD_V6 vtmp6, rFlagsReg cr)
17192 %{
17193 match(Set dummy (StrInflatedCopy src (Binary dst len)));
17194 effect(TEMP vtmp0, TEMP vtmp1, TEMP vtmp2, TEMP vtmp3,
17195 TEMP vtmp4, TEMP vtmp5, TEMP vtmp6, TEMP tmp,
17196 USE_KILL src, USE_KILL dst, USE_KILL len, KILL cr);
17197
17198 format %{ "String Inflate $src,$dst # KILL $tmp $src $dst $len V0-V6 cr" %}
17199 ins_encode %{
17200 address tpc = __ byte_array_inflate($src$$Register, $dst$$Register, $len$$Register,
17201 $vtmp0$$FloatRegister, $vtmp1$$FloatRegister,
17202 $vtmp2$$FloatRegister, $tmp$$Register);
17203 if (tpc == NULL) {
17204 ciEnv::current()->record_failure("CodeCache is full");
17205 return;
17206 }
17207 %}
17208 ins_pipe(pipe_class_memory);
17209 %}
17210
17211 // encode char[] to byte[] in ISO_8859_1
17212 instruct encode_iso_array(iRegP_R2 src, iRegP_R1 dst, iRegI_R3 len,
17213 vRegD_V0 vtmp0, vRegD_V1 vtmp1, vRegD_V2 vtmp2,
17214 vRegD_V3 vtmp3, vRegD_V4 vtmp4, vRegD_V5 vtmp5,
17215 iRegI_R0 result, rFlagsReg cr)
17216 %{
17217 predicate(!((EncodeISOArrayNode*)n)->is_ascii());
17218 match(Set result (EncodeISOArray src (Binary dst len)));
17219 effect(USE_KILL src, USE_KILL dst, USE len, KILL vtmp0, KILL vtmp1,
17220 KILL vtmp2, KILL vtmp3, KILL vtmp4, KILL vtmp5, KILL cr);
17221
17222 format %{ "Encode ISO array $src,$dst,$len -> $result # KILL $src $dst V0-V5 cr" %}
17223 ins_encode %{
17224 __ encode_iso_array($src$$Register, $dst$$Register, $len$$Register,
17225 $result$$Register, false,
17226 $vtmp0$$FloatRegister, $vtmp1$$FloatRegister,
17227 $vtmp2$$FloatRegister, $vtmp3$$FloatRegister,
17228 $vtmp4$$FloatRegister, $vtmp5$$FloatRegister);
17229 %}
17230 ins_pipe(pipe_class_memory);
17231 %}
17232
17233 instruct encode_ascii_array(iRegP_R2 src, iRegP_R1 dst, iRegI_R3 len,
17234 vRegD_V0 vtmp0, vRegD_V1 vtmp1, vRegD_V2 vtmp2,
17235 vRegD_V3 vtmp3, vRegD_V4 vtmp4, vRegD_V5 vtmp5,
17236 iRegI_R0 result, rFlagsReg cr)
17237 %{
17238 predicate(((EncodeISOArrayNode*)n)->is_ascii());
17239 match(Set result (EncodeISOArray src (Binary dst len)));
17240 effect(USE_KILL src, USE_KILL dst, USE len, KILL vtmp0, KILL vtmp1,
17241 KILL vtmp2, KILL vtmp3, KILL vtmp4, KILL vtmp5, KILL cr);
17242
17243 format %{ "Encode ASCII array $src,$dst,$len -> $result # KILL $src $dst V0-V5 cr" %}
17244 ins_encode %{
17245 __ encode_iso_array($src$$Register, $dst$$Register, $len$$Register,
17246 $result$$Register, true,
17247 $vtmp0$$FloatRegister, $vtmp1$$FloatRegister,
17248 $vtmp2$$FloatRegister, $vtmp3$$FloatRegister,
17249 $vtmp4$$FloatRegister, $vtmp5$$FloatRegister);
17250 %}
17251 ins_pipe(pipe_class_memory);
17252 %}
17253
17254 //----------------------------- CompressBits/ExpandBits ------------------------
17255
17256 instruct compressBitsI_reg(iRegINoSp dst, iRegIorL2I src, iRegIorL2I mask,
17257 vRegF tdst, vRegF tsrc, vRegF tmask) %{
17258 match(Set dst (CompressBits src mask));
17259 effect(TEMP tdst, TEMP tsrc, TEMP tmask);
17260 format %{ "mov $tsrc, $src\n\t"
17261 "mov $tmask, $mask\n\t"
17262 "bext $tdst, $tsrc, $tmask\n\t"
17263 "mov $dst, $tdst"
17264 %}
17265 ins_encode %{
17266 __ mov($tsrc$$FloatRegister, __ S, 0, $src$$Register);
17267 __ mov($tmask$$FloatRegister, __ S, 0, $mask$$Register);
17268 __ sve_bext($tdst$$FloatRegister, __ S, $tsrc$$FloatRegister, $tmask$$FloatRegister);
17269 __ mov($dst$$Register, $tdst$$FloatRegister, __ S, 0);
17270 %}
17271 ins_pipe(pipe_slow);
17272 %}
17273
17274 instruct compressBitsI_memcon(iRegINoSp dst, memory4 mem, immI mask,
17275 vRegF tdst, vRegF tsrc, vRegF tmask) %{
17276 match(Set dst (CompressBits (LoadI mem) mask));
17277 effect(TEMP tdst, TEMP tsrc, TEMP tmask);
17278 format %{ "ldrs $tsrc, $mem\n\t"
17279 "ldrs $tmask, $mask\n\t"
17280 "bext $tdst, $tsrc, $tmask\n\t"
17281 "mov $dst, $tdst"
17282 %}
17283 ins_encode %{
17284 loadStore(C2_MacroAssembler(&cbuf), &MacroAssembler::ldrs, $tsrc$$FloatRegister, $mem->opcode(),
17285 as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp, 4);
17286 __ ldrs($tmask$$FloatRegister, $constantaddress($mask));
17287 __ sve_bext($tdst$$FloatRegister, __ S, $tsrc$$FloatRegister, $tmask$$FloatRegister);
17288 __ mov($dst$$Register, $tdst$$FloatRegister, __ S, 0);
17289 %}
17290 ins_pipe(pipe_slow);
17291 %}
17292
17293 instruct compressBitsL_reg(iRegLNoSp dst, iRegL src, iRegL mask,
17294 vRegD tdst, vRegD tsrc, vRegD tmask) %{
17295 match(Set dst (CompressBits src mask));
17296 effect(TEMP tdst, TEMP tsrc, TEMP tmask);
17297 format %{ "mov $tsrc, $src\n\t"
17298 "mov $tmask, $mask\n\t"
17299 "bext $tdst, $tsrc, $tmask\n\t"
17300 "mov $dst, $tdst"
17301 %}
17302 ins_encode %{
17303 __ mov($tsrc$$FloatRegister, __ D, 0, $src$$Register);
17304 __ mov($tmask$$FloatRegister, __ D, 0, $mask$$Register);
17305 __ sve_bext($tdst$$FloatRegister, __ D, $tsrc$$FloatRegister, $tmask$$FloatRegister);
17306 __ mov($dst$$Register, $tdst$$FloatRegister, __ D, 0);
17307 %}
17308 ins_pipe(pipe_slow);
17309 %}
17310
17311 instruct compressBitsL_memcon(iRegLNoSp dst, memory8 mem, immL mask,
17312 vRegF tdst, vRegF tsrc, vRegF tmask) %{
17313 match(Set dst (CompressBits (LoadL mem) mask));
17314 effect(TEMP tdst, TEMP tsrc, TEMP tmask);
17315 format %{ "ldrd $tsrc, $mem\n\t"
17316 "ldrd $tmask, $mask\n\t"
17317 "bext $tdst, $tsrc, $tmask\n\t"
17318 "mov $dst, $tdst"
17319 %}
17320 ins_encode %{
17321 loadStore(C2_MacroAssembler(&cbuf), &MacroAssembler::ldrd, $tsrc$$FloatRegister, $mem->opcode(),
17322 as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp, 8);
17323 __ ldrd($tmask$$FloatRegister, $constantaddress($mask));
17324 __ sve_bext($tdst$$FloatRegister, __ D, $tsrc$$FloatRegister, $tmask$$FloatRegister);
17325 __ mov($dst$$Register, $tdst$$FloatRegister, __ D, 0);
17326 %}
17327 ins_pipe(pipe_slow);
17328 %}
17329
17330 instruct expandBitsI_reg(iRegINoSp dst, iRegIorL2I src, iRegIorL2I mask,
17331 vRegF tdst, vRegF tsrc, vRegF tmask) %{
17332 match(Set dst (ExpandBits src mask));
17333 effect(TEMP tdst, TEMP tsrc, TEMP tmask);
17334 format %{ "mov $tsrc, $src\n\t"
17335 "mov $tmask, $mask\n\t"
17336 "bdep $tdst, $tsrc, $tmask\n\t"
17337 "mov $dst, $tdst"
17338 %}
17339 ins_encode %{
17340 __ mov($tsrc$$FloatRegister, __ S, 0, $src$$Register);
17341 __ mov($tmask$$FloatRegister, __ S, 0, $mask$$Register);
17342 __ sve_bdep($tdst$$FloatRegister, __ S, $tsrc$$FloatRegister, $tmask$$FloatRegister);
17343 __ mov($dst$$Register, $tdst$$FloatRegister, __ S, 0);
17344 %}
17345 ins_pipe(pipe_slow);
17346 %}
17347
17348 instruct expandBitsI_memcon(iRegINoSp dst, memory4 mem, immI mask,
17349 vRegF tdst, vRegF tsrc, vRegF tmask) %{
17350 match(Set dst (ExpandBits (LoadI mem) mask));
17351 effect(TEMP tdst, TEMP tsrc, TEMP tmask);
17352 format %{ "ldrs $tsrc, $mem\n\t"
17353 "ldrs $tmask, $mask\n\t"
17354 "bdep $tdst, $tsrc, $tmask\n\t"
17355 "mov $dst, $tdst"
17356 %}
17357 ins_encode %{
17358 loadStore(C2_MacroAssembler(&cbuf), &MacroAssembler::ldrs, $tsrc$$FloatRegister, $mem->opcode(),
17359 as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp, 4);
17360 __ ldrs($tmask$$FloatRegister, $constantaddress($mask));
17361 __ sve_bdep($tdst$$FloatRegister, __ S, $tsrc$$FloatRegister, $tmask$$FloatRegister);
17362 __ mov($dst$$Register, $tdst$$FloatRegister, __ S, 0);
17363 %}
17364 ins_pipe(pipe_slow);
17365 %}
17366
17367 instruct expandBitsL_reg(iRegLNoSp dst, iRegL src, iRegL mask,
17368 vRegD tdst, vRegD tsrc, vRegD tmask) %{
17369 match(Set dst (ExpandBits src mask));
17370 effect(TEMP tdst, TEMP tsrc, TEMP tmask);
17371 format %{ "mov $tsrc, $src\n\t"
17372 "mov $tmask, $mask\n\t"
17373 "bdep $tdst, $tsrc, $tmask\n\t"
17374 "mov $dst, $tdst"
17375 %}
17376 ins_encode %{
17377 __ mov($tsrc$$FloatRegister, __ D, 0, $src$$Register);
17378 __ mov($tmask$$FloatRegister, __ D, 0, $mask$$Register);
17379 __ sve_bdep($tdst$$FloatRegister, __ D, $tsrc$$FloatRegister, $tmask$$FloatRegister);
17380 __ mov($dst$$Register, $tdst$$FloatRegister, __ D, 0);
17381 %}
17382 ins_pipe(pipe_slow);
17383 %}
17384
17385
17386 instruct expandBitsL_memcon(iRegINoSp dst, memory8 mem, immL mask,
17387 vRegF tdst, vRegF tsrc, vRegF tmask) %{
17388 match(Set dst (ExpandBits (LoadL mem) mask));
17389 effect(TEMP tdst, TEMP tsrc, TEMP tmask);
17390 format %{ "ldrd $tsrc, $mem\n\t"
17391 "ldrd $tmask, $mask\n\t"
17392 "bdep $tdst, $tsrc, $tmask\n\t"
17393 "mov $dst, $tdst"
17394 %}
17395 ins_encode %{
17396 loadStore(C2_MacroAssembler(&cbuf), &MacroAssembler::ldrd, $tsrc$$FloatRegister, $mem->opcode(),
17397 as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp, 8);
17398 __ ldrd($tmask$$FloatRegister, $constantaddress($mask));
17399 __ sve_bdep($tdst$$FloatRegister, __ D, $tsrc$$FloatRegister, $tmask$$FloatRegister);
17400 __ mov($dst$$Register, $tdst$$FloatRegister, __ D, 0);
17401 %}
17402 ins_pipe(pipe_slow);
17403 %}
17404
17405 // ============================================================================
17406 // This name is KNOWN by the ADLC and cannot be changed.
17407 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
17408 // for this guy.
17409 instruct tlsLoadP(thread_RegP dst)
17410 %{
17411 match(Set dst (ThreadLocal));
17412
17413 ins_cost(0);
17414
17415 format %{ " -- \t// $dst=Thread::current(), empty" %}
17416
17417 size(0);
17418
17419 ins_encode( /*empty*/ );
17420
17421 ins_pipe(pipe_class_empty);
17422 %}
17423
17424 //----------PEEPHOLE RULES-----------------------------------------------------
17425 // These must follow all instruction definitions as they use the names
17426 // defined in the instructions definitions.
17427 //
17428 // peepmatch ( root_instr_name [preceding_instruction]* );
17429 //
17430 // peepconstraint %{
17431 // (instruction_number.operand_name relational_op instruction_number.operand_name
17432 // [, ...] );
17433 // // instruction numbers are zero-based using left to right order in peepmatch
17434 //
17435 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
17436 // // provide an instruction_number.operand_name for each operand that appears
17437 // // in the replacement instruction's match rule
17438 //
17439 // ---------VM FLAGS---------------------------------------------------------
17440 //
17441 // All peephole optimizations can be turned off using -XX:-OptoPeephole
17442 //
17443 // Each peephole rule is given an identifying number starting with zero and
17444 // increasing by one in the order seen by the parser. An individual peephole
17445 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
17446 // on the command-line.
17447 //
17448 // ---------CURRENT LIMITATIONS----------------------------------------------
17449 //
17450 // Only match adjacent instructions in same basic block
17451 // Only equality constraints
17452 // Only constraints between operands, not (0.dest_reg == RAX_enc)
17453 // Only one replacement instruction
17454 //
17455 // ---------EXAMPLE----------------------------------------------------------
17456 //
17457 // // pertinent parts of existing instructions in architecture description
17458 // instruct movI(iRegINoSp dst, iRegI src)
17459 // %{
17460 // match(Set dst (CopyI src));
17461 // %}
17462 //
17463 // instruct incI_iReg(iRegINoSp dst, immI1 src, rFlagsReg cr)
17464 // %{
17465 // match(Set dst (AddI dst src));
17466 // effect(KILL cr);
17467 // %}
17468 //
17469 // // Change (inc mov) to lea
17470 // peephole %{
17471 // // increment preceded by register-register move
17472 // peepmatch ( incI_iReg movI );
17473 // // require that the destination register of the increment
17474 // // match the destination register of the move
17475 // peepconstraint ( 0.dst == 1.dst );
17476 // // construct a replacement instruction that sets
17477 // // the destination to ( move's source register + one )
17478 // peepreplace ( leaI_iReg_immI( 0.dst 1.src 0.src ) );
17479 // %}
17480 //
17481
17482 // Implementation no longer uses movX instructions since
17483 // machine-independent system no longer uses CopyX nodes.
17484 //
17485 // peephole
17486 // %{
17487 // peepmatch (incI_iReg movI);
17488 // peepconstraint (0.dst == 1.dst);
17489 // peepreplace (leaI_iReg_immI(0.dst 1.src 0.src));
17490 // %}
17491
17492 // peephole
17493 // %{
17494 // peepmatch (decI_iReg movI);
17495 // peepconstraint (0.dst == 1.dst);
17496 // peepreplace (leaI_iReg_immI(0.dst 1.src 0.src));
17497 // %}
17498
17499 // peephole
17500 // %{
17501 // peepmatch (addI_iReg_imm movI);
17502 // peepconstraint (0.dst == 1.dst);
17503 // peepreplace (leaI_iReg_immI(0.dst 1.src 0.src));
17504 // %}
17505
17506 // peephole
17507 // %{
17508 // peepmatch (incL_iReg movL);
17509 // peepconstraint (0.dst == 1.dst);
17510 // peepreplace (leaL_iReg_immL(0.dst 1.src 0.src));
17511 // %}
17512
17513 // peephole
17514 // %{
17515 // peepmatch (decL_iReg movL);
17516 // peepconstraint (0.dst == 1.dst);
17517 // peepreplace (leaL_iReg_immL(0.dst 1.src 0.src));
17518 // %}
17519
17520 // peephole
17521 // %{
17522 // peepmatch (addL_iReg_imm movL);
17523 // peepconstraint (0.dst == 1.dst);
17524 // peepreplace (leaL_iReg_immL(0.dst 1.src 0.src));
17525 // %}
17526
17527 // peephole
17528 // %{
17529 // peepmatch (addP_iReg_imm movP);
17530 // peepconstraint (0.dst == 1.dst);
17531 // peepreplace (leaP_iReg_imm(0.dst 1.src 0.src));
17532 // %}
17533
17534 // // Change load of spilled value to only a spill
17535 // instruct storeI(memory mem, iRegI src)
17536 // %{
17537 // match(Set mem (StoreI mem src));
17538 // %}
17539 //
17540 // instruct loadI(iRegINoSp dst, memory mem)
17541 // %{
17542 // match(Set dst (LoadI mem));
17543 // %}
17544 //
17545
17546 //----------SMARTSPILL RULES---------------------------------------------------
17547 // These must follow all instruction definitions as they use the names
17548 // defined in the instructions definitions.
17549
17550 // Local Variables:
17551 // mode: c++
17552 // End: