1 /*
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  3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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  6  * under the terms of the GNU General Public License version 2 only, as
  7  * published by the Free Software Foundation.
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  9  * This code is distributed in the hope that it will be useful, but WITHOUT
 10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 12  * version 2 for more details (a copy is included in the LICENSE file that
 13  * accompanied this code).
 14  *
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 24 
 25 #ifndef CPU_AARCH64_C2_MACROASSEMBLER_AARCH64_HPP
 26 #define CPU_AARCH64_C2_MACROASSEMBLER_AARCH64_HPP
 27 
 28 // C2_MacroAssembler contains high-level macros for C2
 29 
 30  private:
 31   // Return true if the phase output is in the scratch emit size mode.
 32   virtual bool in_scratch_emit_size() override;
 33 
 34   void neon_reduce_logical_helper(int opc, bool sf, Register Rd, Register Rn, Register Rm,
 35                                   enum shift_kind kind = Assembler::LSL, unsigned shift = 0);
 36 
 37  public:
 38   void string_compare(Register str1, Register str2,
 39                       Register cnt1, Register cnt2, Register result,
 40                       Register tmp1, Register tmp2, FloatRegister vtmp1,
 41                       FloatRegister vtmp2, FloatRegister vtmp3,
 42                       PRegister pgtmp1, PRegister pgtmp2, int ae);
 43 
 44   void string_indexof(Register str1, Register str2,
 45                       Register cnt1, Register cnt2,
 46                       Register tmp1, Register tmp2,
 47                       Register tmp3, Register tmp4,
 48                       Register tmp5, Register tmp6,
 49                       int int_cnt1, Register result, int ae);
 50 
 51   void string_indexof_char(Register str1, Register cnt1,
 52                            Register ch, Register result,
 53                            Register tmp1, Register tmp2, Register tmp3);
 54 
 55   void stringL_indexof_char(Register str1, Register cnt1,
 56                             Register ch, Register result,
 57                             Register tmp1, Register tmp2, Register tmp3);
 58 
 59   void string_indexof_char_sve(Register str1, Register cnt1,
 60                                Register ch, Register result,
 61                                FloatRegister ztmp1, FloatRegister ztmp2,
 62                                PRegister pgtmp, PRegister ptmp, bool isL);
 63 
 64   // Compress the least significant bit of each byte to the rightmost and clear
 65   // the higher garbage bits.
 66   void bytemask_compress(Register dst);
 67 
 68   // Pack the lowest-numbered bit of each mask element in src into a long value
 69   // in dst, at most the first 64 lane elements.
 70   void sve_vmask_tolong(Register dst, PRegister src, BasicType bt, int lane_cnt,
 71                         FloatRegister vtmp1, FloatRegister vtmp2);
 72 
 73   // Unpack the mask, a long value in src, into predicate register dst based on the
 74   // corresponding data type. Note that dst can support at most 64 lanes.
 75   void sve_vmask_fromlong(PRegister dst, Register src, BasicType bt, int lane_cnt,
 76                           FloatRegister vtmp1, FloatRegister vtmp2);
 77 
 78   // SIMD&FP comparison
 79   void neon_compare(FloatRegister dst, BasicType bt, FloatRegister src1,
 80                     FloatRegister src2, Condition cond, bool isQ);
 81 
 82   void neon_compare_zero(FloatRegister dst, BasicType bt, FloatRegister src,
 83                          Condition cond, bool isQ);
 84 
 85   void sve_compare(PRegister pd, BasicType bt, PRegister pg,
 86                    FloatRegister zn, FloatRegister zm, Condition cond);
 87 
 88   void sve_vmask_lasttrue(Register dst, BasicType bt, PRegister src, PRegister ptmp);
 89 
 90   // Vector cast
 91   void neon_vector_extend(FloatRegister dst, BasicType dst_bt, unsigned dst_vlen_in_bytes,
 92                           FloatRegister src, BasicType src_bt);
 93 
 94   void neon_vector_narrow(FloatRegister dst, BasicType dst_bt,
 95                           FloatRegister src, BasicType src_bt, unsigned src_vlen_in_bytes);
 96 
 97   void sve_vector_extend(FloatRegister dst, SIMD_RegVariant dst_size,
 98                          FloatRegister src, SIMD_RegVariant src_size);
 99 
100   void sve_vector_narrow(FloatRegister dst, SIMD_RegVariant dst_size,
101                          FloatRegister src, SIMD_RegVariant src_size, FloatRegister tmp);
102 
103   void sve_vmaskcast_extend(PRegister dst, PRegister src,
104                             uint dst_element_length_in_bytes, uint src_element_lenght_in_bytes);
105 
106   void sve_vmaskcast_narrow(PRegister dst, PRegister src, PRegister ptmp,
107                             uint dst_element_length_in_bytes, uint src_element_lenght_in_bytes);
108 
109   // Vector reduction
110   void neon_reduce_add_integral(Register dst, BasicType bt,
111                                 Register isrc, FloatRegister vsrc,
112                                 unsigned vector_length_in_bytes, FloatRegister vtmp);
113 
114   void neon_reduce_mul_integral(Register dst, BasicType bt,
115                                 Register isrc, FloatRegister vsrc,
116                                 unsigned vector_length_in_bytes,
117                                 FloatRegister vtmp1, FloatRegister vtmp2);
118 
119   void neon_reduce_mul_fp(FloatRegister dst, BasicType bt,
120                           FloatRegister fsrc, FloatRegister vsrc,
121                           unsigned vector_length_in_bytes, FloatRegister vtmp);
122 
123   void neon_reduce_logical(int opc, Register dst, BasicType bt, Register isrc,
124                            FloatRegister vsrc, unsigned vector_length_in_bytes);
125 
126   void neon_reduce_minmax_integral(int opc, Register dst, BasicType bt,
127                                    Register isrc, FloatRegister vsrc,
128                                    unsigned vector_length_in_bytes, FloatRegister vtmp);
129 
130   void sve_reduce_integral(int opc, Register dst, BasicType bt, Register src1,
131                            FloatRegister src2, PRegister pg, FloatRegister tmp);
132 
133   // Set elements of the dst predicate to true for lanes in the range of
134   // [0, lane_cnt), or to false otherwise. The input "lane_cnt" should be
135   // smaller than or equal to the supported max vector length of the basic
136   // type. Clobbers: rscratch1 and the rFlagsReg.
137   void sve_gen_mask_imm(PRegister dst, BasicType bt, uint32_t lane_cnt);
138 
139   // Extract a scalar element from an sve vector at position 'idx'.
140   // The input elements in src are expected to be of integral type.
141   void sve_extract_integral(Register dst, BasicType bt, FloatRegister src,
142                             int idx, FloatRegister vtmp);
143 
144   // java.lang.Math::round intrinsics
145   void vector_round_neon(FloatRegister dst, FloatRegister src, FloatRegister tmp1,
146                          FloatRegister tmp2, FloatRegister tmp3,
147                          SIMD_Arrangement T);
148   void vector_round_sve(FloatRegister dst, FloatRegister src, FloatRegister tmp1,
149                         FloatRegister tmp2, PRegister pgtmp,
150                         SIMD_RegVariant T);
151 
152   // Pack active elements of src, under the control of mask, into the
153   // lowest-numbered elements of dst. Any remaining elements of dst will
154   // be filled with zero.
155   void sve_compress_byte(FloatRegister dst, FloatRegister src, PRegister mask,
156                          FloatRegister vtmp1, FloatRegister vtmp2,
157                          FloatRegister vtmp3, FloatRegister vtmp4,
158                          PRegister ptmp, PRegister pgtmp);
159 
160   void sve_compress_short(FloatRegister dst, FloatRegister src, PRegister mask,
161                           FloatRegister vtmp1, FloatRegister vtmp2,
162                           PRegister pgtmp);
163 
164   void neon_reverse_bits(FloatRegister dst, FloatRegister src, BasicType bt, bool isQ);
165 
166   void neon_reverse_bytes(FloatRegister dst, FloatRegister src, BasicType bt, bool isQ);
167 
168   // java.lang.Math::signum intrinsics
169   void vector_signum_neon(FloatRegister dst, FloatRegister src, FloatRegister zero,
170                           FloatRegister one, SIMD_Arrangement T);
171 
172   void vector_signum_sve(FloatRegister dst, FloatRegister src, FloatRegister zero,
173                          FloatRegister one, FloatRegister vtmp, PRegister pgtmp, SIMD_RegVariant T);
174 
175   void load_nklass_compact(Register dst, Register obj, Register index, int scale, int disp);
176 
177 #endif // CPU_AARCH64_C2_MACROASSEMBLER_AARCH64_HPP