155 void sve_compress_byte(FloatRegister dst, FloatRegister src, PRegister mask,
156 FloatRegister vtmp1, FloatRegister vtmp2,
157 FloatRegister vtmp3, FloatRegister vtmp4,
158 PRegister ptmp, PRegister pgtmp);
159
160 void sve_compress_short(FloatRegister dst, FloatRegister src, PRegister mask,
161 FloatRegister vtmp1, FloatRegister vtmp2,
162 PRegister pgtmp);
163
164 void neon_reverse_bits(FloatRegister dst, FloatRegister src, BasicType bt, bool isQ);
165
166 void neon_reverse_bytes(FloatRegister dst, FloatRegister src, BasicType bt, bool isQ);
167
168 // java.lang.Math::signum intrinsics
169 void vector_signum_neon(FloatRegister dst, FloatRegister src, FloatRegister zero,
170 FloatRegister one, SIMD_Arrangement T);
171
172 void vector_signum_sve(FloatRegister dst, FloatRegister src, FloatRegister zero,
173 FloatRegister one, FloatRegister vtmp, PRegister pgtmp, SIMD_RegVariant T);
174
175 #endif // CPU_AARCH64_C2_MACROASSEMBLER_AARCH64_HPP
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155 void sve_compress_byte(FloatRegister dst, FloatRegister src, PRegister mask,
156 FloatRegister vtmp1, FloatRegister vtmp2,
157 FloatRegister vtmp3, FloatRegister vtmp4,
158 PRegister ptmp, PRegister pgtmp);
159
160 void sve_compress_short(FloatRegister dst, FloatRegister src, PRegister mask,
161 FloatRegister vtmp1, FloatRegister vtmp2,
162 PRegister pgtmp);
163
164 void neon_reverse_bits(FloatRegister dst, FloatRegister src, BasicType bt, bool isQ);
165
166 void neon_reverse_bytes(FloatRegister dst, FloatRegister src, BasicType bt, bool isQ);
167
168 // java.lang.Math::signum intrinsics
169 void vector_signum_neon(FloatRegister dst, FloatRegister src, FloatRegister zero,
170 FloatRegister one, SIMD_Arrangement T);
171
172 void vector_signum_sve(FloatRegister dst, FloatRegister src, FloatRegister zero,
173 FloatRegister one, FloatRegister vtmp, PRegister pgtmp, SIMD_RegVariant T);
174
175 void load_nklass_compact(Register dst, Register obj);
176
177 #endif // CPU_AARCH64_C2_MACROASSEMBLER_AARCH64_HPP
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