< prev index next >

src/hotspot/cpu/aarch64/c2_MacroAssembler_aarch64.hpp

Print this page

  1 /*
  2  * Copyright (c) 2020, 2023, Oracle and/or its affiliates. All rights reserved.
  3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  4  *
  5  * This code is free software; you can redistribute it and/or modify it
  6  * under the terms of the GNU General Public License version 2 only, as
  7  * published by the Free Software Foundation.
  8  *
  9  * This code is distributed in the hope that it will be useful, but WITHOUT
 10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 12  * version 2 for more details (a copy is included in the LICENSE file that
 13  * accompanied this code).
 14  *
 15  * You should have received a copy of the GNU General Public License version
 16  * 2 along with this work; if not, write to the Free Software Foundation,
 17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
 18  *
 19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
 20  * or visit www.oracle.com if you need additional information or have any
 21  * questions.
 22  *
 23  */
 24 
 25 #ifndef CPU_AARCH64_C2_MACROASSEMBLER_AARCH64_HPP
 26 #define CPU_AARCH64_C2_MACROASSEMBLER_AARCH64_HPP
 27 
 28 // C2_MacroAssembler contains high-level macros for C2
 29 
 30  private:
 31   // Return true if the phase output is in the scratch emit size mode.
 32   virtual bool in_scratch_emit_size() override;
 33 
 34   void neon_reduce_logical_helper(int opc, bool sf, Register Rd, Register Rn, Register Rm,
 35                                   enum shift_kind kind = Assembler::LSL, unsigned shift = 0);
 36 
 37  public:
 38   // Code used by cmpFastLock and cmpFastUnlock mach instructions in .ad file.
 39   // See full description in macroAssembler_aarch64.cpp.
 40   void fast_lock(Register object, Register box, Register tmp, Register tmp2, Register tmp3);
 41   void fast_unlock(Register object, Register box, Register tmp, Register tmp2);



 42 
 43   void string_compare(Register str1, Register str2,
 44                       Register cnt1, Register cnt2, Register result,
 45                       Register tmp1, Register tmp2, FloatRegister vtmp1,
 46                       FloatRegister vtmp2, FloatRegister vtmp3,
 47                       PRegister pgtmp1, PRegister pgtmp2, int ae);
 48 
 49   void string_indexof(Register str1, Register str2,
 50                       Register cnt1, Register cnt2,
 51                       Register tmp1, Register tmp2,
 52                       Register tmp3, Register tmp4,
 53                       Register tmp5, Register tmp6,
 54                       int int_cnt1, Register result, int ae);
 55 
 56   void string_indexof_char(Register str1, Register cnt1,
 57                            Register ch, Register result,
 58                            Register tmp1, Register tmp2, Register tmp3);
 59 
 60   void stringL_indexof_char(Register str1, Register cnt1,
 61                             Register ch, Register result,

160   void sve_compress_byte(FloatRegister dst, FloatRegister src, PRegister mask,
161                          FloatRegister vtmp1, FloatRegister vtmp2,
162                          FloatRegister vtmp3, FloatRegister vtmp4,
163                          PRegister ptmp, PRegister pgtmp);
164 
165   void sve_compress_short(FloatRegister dst, FloatRegister src, PRegister mask,
166                           FloatRegister vtmp1, FloatRegister vtmp2,
167                           PRegister pgtmp);
168 
169   void neon_reverse_bits(FloatRegister dst, FloatRegister src, BasicType bt, bool isQ);
170 
171   void neon_reverse_bytes(FloatRegister dst, FloatRegister src, BasicType bt, bool isQ);
172 
173   // java.lang.Math::signum intrinsics
174   void vector_signum_neon(FloatRegister dst, FloatRegister src, FloatRegister zero,
175                           FloatRegister one, SIMD_Arrangement T);
176 
177   void vector_signum_sve(FloatRegister dst, FloatRegister src, FloatRegister zero,
178                          FloatRegister one, FloatRegister vtmp, PRegister pgtmp, SIMD_RegVariant T);
179 


180 #endif // CPU_AARCH64_C2_MACROASSEMBLER_AARCH64_HPP

  1 /*
  2  * Copyright (c) 2020, 2024, Oracle and/or its affiliates. All rights reserved.
  3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  4  *
  5  * This code is free software; you can redistribute it and/or modify it
  6  * under the terms of the GNU General Public License version 2 only, as
  7  * published by the Free Software Foundation.
  8  *
  9  * This code is distributed in the hope that it will be useful, but WITHOUT
 10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 12  * version 2 for more details (a copy is included in the LICENSE file that
 13  * accompanied this code).
 14  *
 15  * You should have received a copy of the GNU General Public License version
 16  * 2 along with this work; if not, write to the Free Software Foundation,
 17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
 18  *
 19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
 20  * or visit www.oracle.com if you need additional information or have any
 21  * questions.
 22  *
 23  */
 24 
 25 #ifndef CPU_AARCH64_C2_MACROASSEMBLER_AARCH64_HPP
 26 #define CPU_AARCH64_C2_MACROASSEMBLER_AARCH64_HPP
 27 
 28 // C2_MacroAssembler contains high-level macros for C2
 29 
 30  private:
 31   // Return true if the phase output is in the scratch emit size mode.
 32   virtual bool in_scratch_emit_size() override;
 33 
 34   void neon_reduce_logical_helper(int opc, bool sf, Register Rd, Register Rn, Register Rm,
 35                                   enum shift_kind kind = Assembler::LSL, unsigned shift = 0);
 36 
 37  public:
 38   // Code used by cmpFastLock and cmpFastUnlock mach instructions in .ad file.

 39   void fast_lock(Register object, Register box, Register tmp, Register tmp2, Register tmp3);
 40   void fast_unlock(Register object, Register box, Register tmp, Register tmp2);
 41   // Code used by cmpFastLockLightweight and cmpFastUnlockLightweight mach instructions in .ad file.
 42   void fast_lock_lightweight(Register object, Register t1, Register t2, Register t3);
 43   void fast_unlock_lightweight(Register object, Register t1, Register t2, Register t3);
 44 
 45   void string_compare(Register str1, Register str2,
 46                       Register cnt1, Register cnt2, Register result,
 47                       Register tmp1, Register tmp2, FloatRegister vtmp1,
 48                       FloatRegister vtmp2, FloatRegister vtmp3,
 49                       PRegister pgtmp1, PRegister pgtmp2, int ae);
 50 
 51   void string_indexof(Register str1, Register str2,
 52                       Register cnt1, Register cnt2,
 53                       Register tmp1, Register tmp2,
 54                       Register tmp3, Register tmp4,
 55                       Register tmp5, Register tmp6,
 56                       int int_cnt1, Register result, int ae);
 57 
 58   void string_indexof_char(Register str1, Register cnt1,
 59                            Register ch, Register result,
 60                            Register tmp1, Register tmp2, Register tmp3);
 61 
 62   void stringL_indexof_char(Register str1, Register cnt1,
 63                             Register ch, Register result,

162   void sve_compress_byte(FloatRegister dst, FloatRegister src, PRegister mask,
163                          FloatRegister vtmp1, FloatRegister vtmp2,
164                          FloatRegister vtmp3, FloatRegister vtmp4,
165                          PRegister ptmp, PRegister pgtmp);
166 
167   void sve_compress_short(FloatRegister dst, FloatRegister src, PRegister mask,
168                           FloatRegister vtmp1, FloatRegister vtmp2,
169                           PRegister pgtmp);
170 
171   void neon_reverse_bits(FloatRegister dst, FloatRegister src, BasicType bt, bool isQ);
172 
173   void neon_reverse_bytes(FloatRegister dst, FloatRegister src, BasicType bt, bool isQ);
174 
175   // java.lang.Math::signum intrinsics
176   void vector_signum_neon(FloatRegister dst, FloatRegister src, FloatRegister zero,
177                           FloatRegister one, SIMD_Arrangement T);
178 
179   void vector_signum_sve(FloatRegister dst, FloatRegister src, FloatRegister zero,
180                          FloatRegister one, FloatRegister vtmp, PRegister pgtmp, SIMD_RegVariant T);
181 
182   void load_nklass_compact(Register dst, Register obj, Register index, int scale, int disp);
183 
184 #endif // CPU_AARCH64_C2_MACROASSEMBLER_AARCH64_HPP
< prev index next >