src/hotspot/cpu/aarch64/c2_MacroAssembler_aarch64.hpp

@@ -1,7 +1,7 @@
  /*
-  * Copyright (c) 2020, 2023, Oracle and/or its affiliates. All rights reserved.
+  * Copyright (c) 2020, 2024, Oracle and/or its affiliates. All rights reserved.
   * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   *
   * This code is free software; you can redistribute it and/or modify it
   * under the terms of the GNU General Public License version 2 only, as
   * published by the Free Software Foundation.

@@ -34,13 +34,15 @@
    void neon_reduce_logical_helper(int opc, bool sf, Register Rd, Register Rn, Register Rm,
                                    enum shift_kind kind = Assembler::LSL, unsigned shift = 0);
  
   public:
    // Code used by cmpFastLock and cmpFastUnlock mach instructions in .ad file.
-   // See full description in macroAssembler_aarch64.cpp.
    void fast_lock(Register object, Register box, Register tmp, Register tmp2, Register tmp3);
    void fast_unlock(Register object, Register box, Register tmp, Register tmp2);
+   // Code used by cmpFastLockLightweight and cmpFastUnlockLightweight mach instructions in .ad file.
+   void fast_lock_lightweight(Register object, Register t1, Register t2, Register t3);
+   void fast_unlock_lightweight(Register object, Register t1, Register t2, Register t3);
  
    void string_compare(Register str1, Register str2,
                        Register cnt1, Register cnt2, Register result,
                        Register tmp1, Register tmp2, FloatRegister vtmp1,
                        FloatRegister vtmp2, FloatRegister vtmp3,

@@ -175,6 +177,8 @@
                            FloatRegister one, SIMD_Arrangement T);
  
    void vector_signum_sve(FloatRegister dst, FloatRegister src, FloatRegister zero,
                           FloatRegister one, FloatRegister vtmp, PRegister pgtmp, SIMD_RegVariant T);
  
+   void load_nklass_compact(Register dst, Register obj, Register index, int scale, int disp);
+ 
  #endif // CPU_AARCH64_C2_MACROASSEMBLER_AARCH64_HPP