1 /*
2 * Copyright (c) 1997, 2024, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2014, 2021, Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "precompiled.hpp"
27 #include "asm/assembler.hpp"
28 #include "asm/assembler.inline.hpp"
29 #include "ci/ciEnv.hpp"
30 #include "compiler/compileTask.hpp"
31 #include "compiler/disassembler.hpp"
32 #include "compiler/oopMap.hpp"
33 #include "gc/shared/barrierSet.hpp"
34 #include "gc/shared/barrierSetAssembler.hpp"
35 #include "gc/shared/cardTableBarrierSet.hpp"
36 #include "gc/shared/cardTable.hpp"
37 #include "gc/shared/collectedHeap.hpp"
38 #include "gc/shared/tlab_globals.hpp"
39 #include "interpreter/bytecodeHistogram.hpp"
40 #include "interpreter/interpreter.hpp"
41 #include "jvm.h"
42 #include "memory/resourceArea.hpp"
43 #include "memory/universe.hpp"
44 #include "nativeInst_aarch64.hpp"
45 #include "oops/accessDecorators.hpp"
46 #include "oops/compressedOops.inline.hpp"
47 #include "oops/klass.inline.hpp"
48 #include "runtime/continuation.hpp"
49 #include "runtime/icache.hpp"
50 #include "runtime/interfaceSupport.inline.hpp"
51 #include "runtime/javaThread.hpp"
52 #include "runtime/jniHandles.inline.hpp"
53 #include "runtime/sharedRuntime.hpp"
54 #include "runtime/stubRoutines.hpp"
55 #include "utilities/globalDefinitions.hpp"
56 #include "utilities/powerOfTwo.hpp"
57 #ifdef COMPILER1
58 #include "c1/c1_LIRAssembler.hpp"
59 #endif
60 #ifdef COMPILER2
61 #include "oops/oop.hpp"
62 #include "opto/compile.hpp"
63 #include "opto/node.hpp"
64 #include "opto/output.hpp"
65 #endif
66
67 #include <sys/types.h>
68
69 #ifdef PRODUCT
70 #define BLOCK_COMMENT(str) /* nothing */
71 #else
72 #define BLOCK_COMMENT(str) block_comment(str)
73 #endif
74 #define STOP(str) stop(str);
75 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
76
77 #ifdef ASSERT
78 extern "C" void disnm(intptr_t p);
79 #endif
80 // Target-dependent relocation processing
81 //
82 // Instruction sequences whose target may need to be retrieved or
83 // patched are distinguished by their leading instruction, sorting
84 // them into three main instruction groups and related subgroups.
85 //
86 // 1) Branch, Exception and System (insn count = 1)
87 // 1a) Unconditional branch (immediate):
88 // b/bl imm19
89 // 1b) Compare & branch (immediate):
90 // cbz/cbnz Rt imm19
91 // 1c) Test & branch (immediate):
92 // tbz/tbnz Rt imm14
93 // 1d) Conditional branch (immediate):
94 // b.cond imm19
95 //
96 // 2) Loads and Stores (insn count = 1)
97 // 2a) Load register literal:
98 // ldr Rt imm19
99 //
100 // 3) Data Processing Immediate (insn count = 2 or 3)
101 // 3a) PC-rel. addressing
102 // adr/adrp Rx imm21; ldr/str Ry Rx #imm12
103 // adr/adrp Rx imm21; add Ry Rx #imm12
104 // adr/adrp Rx imm21; movk Rx #imm16<<32; ldr/str Ry, [Rx, #offset_in_page]
105 // adr/adrp Rx imm21
106 // adr/adrp Rx imm21; movk Rx #imm16<<32
107 // adr/adrp Rx imm21; movk Rx #imm16<<32; add Ry, Rx, #offset_in_page
108 // The latter form can only happen when the target is an
109 // ExternalAddress, and (by definition) ExternalAddresses don't
110 // move. Because of that property, there is never any need to
111 // patch the last of the three instructions. However,
112 // MacroAssembler::target_addr_for_insn takes all three
113 // instructions into account and returns the correct address.
114 // 3b) Move wide (immediate)
115 // movz Rx #imm16; movk Rx #imm16 << 16; movk Rx #imm16 << 32;
116 //
117 // A switch on a subset of the instruction's bits provides an
118 // efficient dispatch to these subcases.
119 //
120 // insn[28:26] -> main group ('x' == don't care)
121 // 00x -> UNALLOCATED
122 // 100 -> Data Processing Immediate
123 // 101 -> Branch, Exception and System
124 // x1x -> Loads and Stores
125 //
126 // insn[30:25] -> subgroup ('_' == group, 'x' == don't care).
127 // n.b. in some cases extra bits need to be checked to verify the
128 // instruction is as expected
129 //
130 // 1) ... xx101x Branch, Exception and System
131 // 1a) 00___x Unconditional branch (immediate)
132 // 1b) 01___0 Compare & branch (immediate)
133 // 1c) 01___1 Test & branch (immediate)
134 // 1d) 10___0 Conditional branch (immediate)
135 // other Should not happen
136 //
137 // 2) ... xxx1x0 Loads and Stores
138 // 2a) xx1__00 Load/Store register (insn[28] == 1 && insn[24] == 0)
139 // 2aa) x01__00 Load register literal (i.e. requires insn[29] == 0)
140 // strictly should be 64 bit non-FP/SIMD i.e.
141 // 0101_000 (i.e. requires insn[31:24] == 01011000)
142 //
143 // 3) ... xx100x Data Processing Immediate
144 // 3a) xx___00 PC-rel. addressing (n.b. requires insn[24] == 0)
145 // 3b) xx___101 Move wide (immediate) (n.b. requires insn[24:23] == 01)
146 // strictly should be 64 bit movz #imm16<<0
147 // 110___10100 (i.e. requires insn[31:21] == 11010010100)
148 //
149 class RelocActions {
150 protected:
151 typedef int (*reloc_insn)(address insn_addr, address &target);
152
153 virtual reloc_insn adrpMem() = 0;
154 virtual reloc_insn adrpAdd() = 0;
155 virtual reloc_insn adrpMovk() = 0;
156
157 const address _insn_addr;
158 const uint32_t _insn;
159
160 static uint32_t insn_at(address insn_addr, int n) {
161 return ((uint32_t*)insn_addr)[n];
162 }
163 uint32_t insn_at(int n) const {
164 return insn_at(_insn_addr, n);
165 }
166
167 public:
168
169 RelocActions(address insn_addr) : _insn_addr(insn_addr), _insn(insn_at(insn_addr, 0)) {}
170 RelocActions(address insn_addr, uint32_t insn)
171 : _insn_addr(insn_addr), _insn(insn) {}
172
173 virtual int unconditionalBranch(address insn_addr, address &target) = 0;
174 virtual int conditionalBranch(address insn_addr, address &target) = 0;
175 virtual int testAndBranch(address insn_addr, address &target) = 0;
176 virtual int loadStore(address insn_addr, address &target) = 0;
177 virtual int adr(address insn_addr, address &target) = 0;
178 virtual int adrp(address insn_addr, address &target, reloc_insn inner) = 0;
179 virtual int immediate(address insn_addr, address &target) = 0;
180 virtual void verify(address insn_addr, address &target) = 0;
181
182 int ALWAYSINLINE run(address insn_addr, address &target) {
183 int instructions = 1;
184
185 uint32_t dispatch = Instruction_aarch64::extract(_insn, 30, 25);
186 switch(dispatch) {
187 case 0b001010:
188 case 0b001011: {
189 instructions = unconditionalBranch(insn_addr, target);
190 break;
191 }
192 case 0b101010: // Conditional branch (immediate)
193 case 0b011010: { // Compare & branch (immediate)
194 instructions = conditionalBranch(insn_addr, target);
195 break;
196 }
197 case 0b011011: {
198 instructions = testAndBranch(insn_addr, target);
199 break;
200 }
201 case 0b001100:
202 case 0b001110:
203 case 0b011100:
204 case 0b011110:
205 case 0b101100:
206 case 0b101110:
207 case 0b111100:
208 case 0b111110: {
209 // load/store
210 if ((Instruction_aarch64::extract(_insn, 29, 24) & 0b111011) == 0b011000) {
211 // Load register (literal)
212 instructions = loadStore(insn_addr, target);
213 break;
214 } else {
215 // nothing to do
216 assert(target == 0, "did not expect to relocate target for polling page load");
217 }
218 break;
219 }
220 case 0b001000:
221 case 0b011000:
222 case 0b101000:
223 case 0b111000: {
224 // adr/adrp
225 assert(Instruction_aarch64::extract(_insn, 28, 24) == 0b10000, "must be");
226 int shift = Instruction_aarch64::extract(_insn, 31, 31);
227 if (shift) {
228 uint32_t insn2 = insn_at(1);
229 if (Instruction_aarch64::extract(insn2, 29, 24) == 0b111001 &&
230 Instruction_aarch64::extract(_insn, 4, 0) ==
231 Instruction_aarch64::extract(insn2, 9, 5)) {
232 instructions = adrp(insn_addr, target, adrpMem());
233 } else if (Instruction_aarch64::extract(insn2, 31, 22) == 0b1001000100 &&
234 Instruction_aarch64::extract(_insn, 4, 0) ==
235 Instruction_aarch64::extract(insn2, 4, 0)) {
236 instructions = adrp(insn_addr, target, adrpAdd());
237 } else if (Instruction_aarch64::extract(insn2, 31, 21) == 0b11110010110 &&
238 Instruction_aarch64::extract(_insn, 4, 0) ==
239 Instruction_aarch64::extract(insn2, 4, 0)) {
240 instructions = adrp(insn_addr, target, adrpMovk());
241 } else {
242 ShouldNotReachHere();
243 }
244 } else {
245 instructions = adr(insn_addr, target);
246 }
247 break;
248 }
249 case 0b001001:
250 case 0b011001:
251 case 0b101001:
252 case 0b111001: {
253 instructions = immediate(insn_addr, target);
254 break;
255 }
256 default: {
257 ShouldNotReachHere();
258 }
259 }
260
261 verify(insn_addr, target);
262 return instructions * NativeInstruction::instruction_size;
263 }
264 };
265
266 class Patcher : public RelocActions {
267 virtual reloc_insn adrpMem() { return &Patcher::adrpMem_impl; }
268 virtual reloc_insn adrpAdd() { return &Patcher::adrpAdd_impl; }
269 virtual reloc_insn adrpMovk() { return &Patcher::adrpMovk_impl; }
270
271 public:
272 Patcher(address insn_addr) : RelocActions(insn_addr) {}
273
274 virtual int unconditionalBranch(address insn_addr, address &target) {
275 intptr_t offset = (target - insn_addr) >> 2;
276 Instruction_aarch64::spatch(insn_addr, 25, 0, offset);
277 return 1;
278 }
279 virtual int conditionalBranch(address insn_addr, address &target) {
280 intptr_t offset = (target - insn_addr) >> 2;
281 Instruction_aarch64::spatch(insn_addr, 23, 5, offset);
282 return 1;
283 }
284 virtual int testAndBranch(address insn_addr, address &target) {
285 intptr_t offset = (target - insn_addr) >> 2;
286 Instruction_aarch64::spatch(insn_addr, 18, 5, offset);
287 return 1;
288 }
289 virtual int loadStore(address insn_addr, address &target) {
290 intptr_t offset = (target - insn_addr) >> 2;
291 Instruction_aarch64::spatch(insn_addr, 23, 5, offset);
292 return 1;
293 }
294 virtual int adr(address insn_addr, address &target) {
295 #ifdef ASSERT
296 assert(Instruction_aarch64::extract(_insn, 28, 24) == 0b10000, "must be");
297 #endif
298 // PC-rel. addressing
299 ptrdiff_t offset = target - insn_addr;
300 int offset_lo = offset & 3;
301 offset >>= 2;
302 Instruction_aarch64::spatch(insn_addr, 23, 5, offset);
303 Instruction_aarch64::patch(insn_addr, 30, 29, offset_lo);
304 return 1;
305 }
306 virtual int adrp(address insn_addr, address &target, reloc_insn inner) {
307 int instructions = 1;
308 #ifdef ASSERT
309 assert(Instruction_aarch64::extract(_insn, 28, 24) == 0b10000, "must be");
310 #endif
311 ptrdiff_t offset = target - insn_addr;
312 instructions = 2;
313 precond(inner != nullptr);
314 // Give the inner reloc a chance to modify the target.
315 address adjusted_target = target;
316 instructions = (*inner)(insn_addr, adjusted_target);
317 uintptr_t pc_page = (uintptr_t)insn_addr >> 12;
318 uintptr_t adr_page = (uintptr_t)adjusted_target >> 12;
319 offset = adr_page - pc_page;
320 int offset_lo = offset & 3;
321 offset >>= 2;
322 Instruction_aarch64::spatch(insn_addr, 23, 5, offset);
323 Instruction_aarch64::patch(insn_addr, 30, 29, offset_lo);
324 return instructions;
325 }
326 static int adrpMem_impl(address insn_addr, address &target) {
327 uintptr_t dest = (uintptr_t)target;
328 int offset_lo = dest & 0xfff;
329 uint32_t insn2 = insn_at(insn_addr, 1);
330 uint32_t size = Instruction_aarch64::extract(insn2, 31, 30);
331 Instruction_aarch64::patch(insn_addr + sizeof (uint32_t), 21, 10, offset_lo >> size);
332 guarantee(((dest >> size) << size) == dest, "misaligned target");
333 return 2;
334 }
335 static int adrpAdd_impl(address insn_addr, address &target) {
336 uintptr_t dest = (uintptr_t)target;
337 int offset_lo = dest & 0xfff;
338 Instruction_aarch64::patch(insn_addr + sizeof (uint32_t), 21, 10, offset_lo);
339 return 2;
340 }
341 static int adrpMovk_impl(address insn_addr, address &target) {
342 uintptr_t dest = uintptr_t(target);
343 Instruction_aarch64::patch(insn_addr + sizeof (uint32_t), 20, 5, (uintptr_t)target >> 32);
344 dest = (dest & 0xffffffffULL) | (uintptr_t(insn_addr) & 0xffff00000000ULL);
345 target = address(dest);
346 return 2;
347 }
348 virtual int immediate(address insn_addr, address &target) {
349 assert(Instruction_aarch64::extract(_insn, 31, 21) == 0b11010010100, "must be");
350 uint64_t dest = (uint64_t)target;
351 // Move wide constant
352 assert(nativeInstruction_at(insn_addr+4)->is_movk(), "wrong insns in patch");
353 assert(nativeInstruction_at(insn_addr+8)->is_movk(), "wrong insns in patch");
354 Instruction_aarch64::patch(insn_addr, 20, 5, dest & 0xffff);
355 Instruction_aarch64::patch(insn_addr+4, 20, 5, (dest >>= 16) & 0xffff);
356 Instruction_aarch64::patch(insn_addr+8, 20, 5, (dest >>= 16) & 0xffff);
357 return 3;
358 }
359 virtual void verify(address insn_addr, address &target) {
360 #ifdef ASSERT
361 address address_is = MacroAssembler::target_addr_for_insn(insn_addr);
362 if (!(address_is == target)) {
363 tty->print_cr("%p at %p should be %p", address_is, insn_addr, target);
364 disnm((intptr_t)insn_addr);
365 assert(address_is == target, "should be");
366 }
367 #endif
368 }
369 };
370
371 // If insn1 and insn2 use the same register to form an address, either
372 // by an offsetted LDR or a simple ADD, return the offset. If the
373 // second instruction is an LDR, the offset may be scaled.
374 static bool offset_for(uint32_t insn1, uint32_t insn2, ptrdiff_t &byte_offset) {
375 if (Instruction_aarch64::extract(insn2, 29, 24) == 0b111001 &&
376 Instruction_aarch64::extract(insn1, 4, 0) ==
377 Instruction_aarch64::extract(insn2, 9, 5)) {
378 // Load/store register (unsigned immediate)
379 byte_offset = Instruction_aarch64::extract(insn2, 21, 10);
380 uint32_t size = Instruction_aarch64::extract(insn2, 31, 30);
381 byte_offset <<= size;
382 return true;
383 } else if (Instruction_aarch64::extract(insn2, 31, 22) == 0b1001000100 &&
384 Instruction_aarch64::extract(insn1, 4, 0) ==
385 Instruction_aarch64::extract(insn2, 4, 0)) {
386 // add (immediate)
387 byte_offset = Instruction_aarch64::extract(insn2, 21, 10);
388 return true;
389 }
390 return false;
391 }
392
393 class AArch64Decoder : public RelocActions {
394 virtual reloc_insn adrpMem() { return &AArch64Decoder::adrpMem_impl; }
395 virtual reloc_insn adrpAdd() { return &AArch64Decoder::adrpAdd_impl; }
396 virtual reloc_insn adrpMovk() { return &AArch64Decoder::adrpMovk_impl; }
397
398 public:
399 AArch64Decoder(address insn_addr, uint32_t insn) : RelocActions(insn_addr, insn) {}
400
401 virtual int loadStore(address insn_addr, address &target) {
402 intptr_t offset = Instruction_aarch64::sextract(_insn, 23, 5);
403 target = insn_addr + (offset << 2);
404 return 1;
405 }
406 virtual int unconditionalBranch(address insn_addr, address &target) {
407 intptr_t offset = Instruction_aarch64::sextract(_insn, 25, 0);
408 target = insn_addr + (offset << 2);
409 return 1;
410 }
411 virtual int conditionalBranch(address insn_addr, address &target) {
412 intptr_t offset = Instruction_aarch64::sextract(_insn, 23, 5);
413 target = address(((uint64_t)insn_addr + (offset << 2)));
414 return 1;
415 }
416 virtual int testAndBranch(address insn_addr, address &target) {
417 intptr_t offset = Instruction_aarch64::sextract(_insn, 18, 5);
418 target = address(((uint64_t)insn_addr + (offset << 2)));
419 return 1;
420 }
421 virtual int adr(address insn_addr, address &target) {
422 // PC-rel. addressing
423 intptr_t offset = Instruction_aarch64::extract(_insn, 30, 29);
424 offset |= Instruction_aarch64::sextract(_insn, 23, 5) << 2;
425 target = address((uint64_t)insn_addr + offset);
426 return 1;
427 }
428 virtual int adrp(address insn_addr, address &target, reloc_insn inner) {
429 assert(Instruction_aarch64::extract(_insn, 28, 24) == 0b10000, "must be");
430 intptr_t offset = Instruction_aarch64::extract(_insn, 30, 29);
431 offset |= Instruction_aarch64::sextract(_insn, 23, 5) << 2;
432 int shift = 12;
433 offset <<= shift;
434 uint64_t target_page = ((uint64_t)insn_addr) + offset;
435 target_page &= ((uint64_t)-1) << shift;
436 uint32_t insn2 = insn_at(1);
437 target = address(target_page);
438 precond(inner != nullptr);
439 (*inner)(insn_addr, target);
440 return 2;
441 }
442 static int adrpMem_impl(address insn_addr, address &target) {
443 uint32_t insn2 = insn_at(insn_addr, 1);
444 // Load/store register (unsigned immediate)
445 ptrdiff_t byte_offset = Instruction_aarch64::extract(insn2, 21, 10);
446 uint32_t size = Instruction_aarch64::extract(insn2, 31, 30);
447 byte_offset <<= size;
448 target += byte_offset;
449 return 2;
450 }
451 static int adrpAdd_impl(address insn_addr, address &target) {
452 uint32_t insn2 = insn_at(insn_addr, 1);
453 // add (immediate)
454 ptrdiff_t byte_offset = Instruction_aarch64::extract(insn2, 21, 10);
455 target += byte_offset;
456 return 2;
457 }
458 static int adrpMovk_impl(address insn_addr, address &target) {
459 uint32_t insn2 = insn_at(insn_addr, 1);
460 uint64_t dest = uint64_t(target);
461 dest = (dest & 0xffff0000ffffffff) |
462 ((uint64_t)Instruction_aarch64::extract(insn2, 20, 5) << 32);
463 target = address(dest);
464
465 // We know the destination 4k page. Maybe we have a third
466 // instruction.
467 uint32_t insn = insn_at(insn_addr, 0);
468 uint32_t insn3 = insn_at(insn_addr, 2);
469 ptrdiff_t byte_offset;
470 if (offset_for(insn, insn3, byte_offset)) {
471 target += byte_offset;
472 return 3;
473 } else {
474 return 2;
475 }
476 }
477 virtual int immediate(address insn_addr, address &target) {
478 uint32_t *insns = (uint32_t *)insn_addr;
479 assert(Instruction_aarch64::extract(_insn, 31, 21) == 0b11010010100, "must be");
480 // Move wide constant: movz, movk, movk. See movptr().
481 assert(nativeInstruction_at(insns+1)->is_movk(), "wrong insns in patch");
482 assert(nativeInstruction_at(insns+2)->is_movk(), "wrong insns in patch");
483 target = address(uint64_t(Instruction_aarch64::extract(_insn, 20, 5))
484 + (uint64_t(Instruction_aarch64::extract(insns[1], 20, 5)) << 16)
485 + (uint64_t(Instruction_aarch64::extract(insns[2], 20, 5)) << 32));
486 assert(nativeInstruction_at(insn_addr+4)->is_movk(), "wrong insns in patch");
487 assert(nativeInstruction_at(insn_addr+8)->is_movk(), "wrong insns in patch");
488 return 3;
489 }
490 virtual void verify(address insn_addr, address &target) {
491 }
492 };
493
494 address MacroAssembler::target_addr_for_insn(address insn_addr, uint32_t insn) {
495 AArch64Decoder decoder(insn_addr, insn);
496 address target;
497 decoder.run(insn_addr, target);
498 return target;
499 }
500
501 // Patch any kind of instruction; there may be several instructions.
502 // Return the total length (in bytes) of the instructions.
503 int MacroAssembler::pd_patch_instruction_size(address insn_addr, address target) {
504 Patcher patcher(insn_addr);
505 return patcher.run(insn_addr, target);
506 }
507
508 int MacroAssembler::patch_oop(address insn_addr, address o) {
509 int instructions;
510 unsigned insn = *(unsigned*)insn_addr;
511 assert(nativeInstruction_at(insn_addr+4)->is_movk(), "wrong insns in patch");
512
513 // OOPs are either narrow (32 bits) or wide (48 bits). We encode
514 // narrow OOPs by setting the upper 16 bits in the first
515 // instruction.
516 if (Instruction_aarch64::extract(insn, 31, 21) == 0b11010010101) {
517 // Move narrow OOP
518 uint32_t n = CompressedOops::narrow_oop_value(cast_to_oop(o));
519 Instruction_aarch64::patch(insn_addr, 20, 5, n >> 16);
520 Instruction_aarch64::patch(insn_addr+4, 20, 5, n & 0xffff);
521 instructions = 2;
522 } else {
523 // Move wide OOP
524 assert(nativeInstruction_at(insn_addr+8)->is_movk(), "wrong insns in patch");
525 uintptr_t dest = (uintptr_t)o;
526 Instruction_aarch64::patch(insn_addr, 20, 5, dest & 0xffff);
527 Instruction_aarch64::patch(insn_addr+4, 20, 5, (dest >>= 16) & 0xffff);
528 Instruction_aarch64::patch(insn_addr+8, 20, 5, (dest >>= 16) & 0xffff);
529 instructions = 3;
530 }
531 return instructions * NativeInstruction::instruction_size;
532 }
533
534 int MacroAssembler::patch_narrow_klass(address insn_addr, narrowKlass n) {
535 // Metadata pointers are either narrow (32 bits) or wide (48 bits).
536 // We encode narrow ones by setting the upper 16 bits in the first
537 // instruction.
538 NativeInstruction *insn = nativeInstruction_at(insn_addr);
539 assert(Instruction_aarch64::extract(insn->encoding(), 31, 21) == 0b11010010101 &&
540 nativeInstruction_at(insn_addr+4)->is_movk(), "wrong insns in patch");
541
542 Instruction_aarch64::patch(insn_addr, 20, 5, n >> 16);
543 Instruction_aarch64::patch(insn_addr+4, 20, 5, n & 0xffff);
544 return 2 * NativeInstruction::instruction_size;
545 }
546
547 address MacroAssembler::target_addr_for_insn_or_null(address insn_addr, unsigned insn) {
548 if (NativeInstruction::is_ldrw_to_zr(address(&insn))) {
549 return nullptr;
550 }
551 return MacroAssembler::target_addr_for_insn(insn_addr, insn);
552 }
553
554 void MacroAssembler::safepoint_poll(Label& slow_path, bool at_return, bool acquire, bool in_nmethod, Register tmp) {
555 if (acquire) {
556 lea(tmp, Address(rthread, JavaThread::polling_word_offset()));
557 ldar(tmp, tmp);
558 } else {
559 ldr(tmp, Address(rthread, JavaThread::polling_word_offset()));
560 }
561 if (at_return) {
562 // Note that when in_nmethod is set, the stack pointer is incremented before the poll. Therefore,
563 // we may safely use the sp instead to perform the stack watermark check.
564 cmp(in_nmethod ? sp : rfp, tmp);
565 br(Assembler::HI, slow_path);
566 } else {
567 tbnz(tmp, log2i_exact(SafepointMechanism::poll_bit()), slow_path);
568 }
569 }
570
571 void MacroAssembler::rt_call(address dest, Register tmp) {
572 CodeBlob *cb = CodeCache::find_blob(dest);
573 if (cb) {
574 far_call(RuntimeAddress(dest));
575 } else {
576 lea(tmp, RuntimeAddress(dest));
577 blr(tmp);
578 }
579 }
580
581 void MacroAssembler::push_cont_fastpath(Register java_thread) {
582 if (!Continuations::enabled()) return;
583 Label done;
584 ldr(rscratch1, Address(java_thread, JavaThread::cont_fastpath_offset()));
585 cmp(sp, rscratch1);
586 br(Assembler::LS, done);
587 mov(rscratch1, sp); // we can't use sp as the source in str
588 str(rscratch1, Address(java_thread, JavaThread::cont_fastpath_offset()));
589 bind(done);
590 }
591
592 void MacroAssembler::pop_cont_fastpath(Register java_thread) {
593 if (!Continuations::enabled()) return;
594 Label done;
595 ldr(rscratch1, Address(java_thread, JavaThread::cont_fastpath_offset()));
596 cmp(sp, rscratch1);
597 br(Assembler::LO, done);
598 str(zr, Address(java_thread, JavaThread::cont_fastpath_offset()));
599 bind(done);
600 }
601
602 void MacroAssembler::reset_last_Java_frame(bool clear_fp) {
603 // we must set sp to zero to clear frame
604 str(zr, Address(rthread, JavaThread::last_Java_sp_offset()));
605
606 // must clear fp, so that compiled frames are not confused; it is
607 // possible that we need it only for debugging
608 if (clear_fp) {
609 str(zr, Address(rthread, JavaThread::last_Java_fp_offset()));
610 }
611
612 // Always clear the pc because it could have been set by make_walkable()
613 str(zr, Address(rthread, JavaThread::last_Java_pc_offset()));
614 }
615
616 // Calls to C land
617 //
618 // When entering C land, the rfp, & resp of the last Java frame have to be recorded
619 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp
620 // has to be reset to 0. This is required to allow proper stack traversal.
621 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
622 Register last_java_fp,
623 Register last_java_pc,
624 Register scratch) {
625
626 if (last_java_pc->is_valid()) {
627 str(last_java_pc, Address(rthread,
628 JavaThread::frame_anchor_offset()
629 + JavaFrameAnchor::last_Java_pc_offset()));
630 }
631
632 // determine last_java_sp register
633 if (last_java_sp == sp) {
634 mov(scratch, sp);
635 last_java_sp = scratch;
636 } else if (!last_java_sp->is_valid()) {
637 last_java_sp = esp;
638 }
639
640 str(last_java_sp, Address(rthread, JavaThread::last_Java_sp_offset()));
641
642 // last_java_fp is optional
643 if (last_java_fp->is_valid()) {
644 str(last_java_fp, Address(rthread, JavaThread::last_Java_fp_offset()));
645 }
646 }
647
648 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
649 Register last_java_fp,
650 address last_java_pc,
651 Register scratch) {
652 assert(last_java_pc != nullptr, "must provide a valid PC");
653
654 adr(scratch, last_java_pc);
655 str(scratch, Address(rthread,
656 JavaThread::frame_anchor_offset()
657 + JavaFrameAnchor::last_Java_pc_offset()));
658
659 set_last_Java_frame(last_java_sp, last_java_fp, noreg, scratch);
660 }
661
662 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
663 Register last_java_fp,
664 Label &L,
665 Register scratch) {
666 if (L.is_bound()) {
667 set_last_Java_frame(last_java_sp, last_java_fp, target(L), scratch);
668 } else {
669 InstructionMark im(this);
670 L.add_patch_at(code(), locator());
671 set_last_Java_frame(last_java_sp, last_java_fp, pc() /* Patched later */, scratch);
672 }
673 }
674
675 static inline bool target_needs_far_branch(address addr) {
676 // codecache size <= 128M
677 if (!MacroAssembler::far_branches()) {
678 return false;
679 }
680 // codecache size > 240M
681 if (MacroAssembler::codestub_branch_needs_far_jump()) {
682 return true;
683 }
684 // codecache size: 128M..240M
685 return !CodeCache::is_non_nmethod(addr);
686 }
687
688 void MacroAssembler::far_call(Address entry, Register tmp) {
689 assert(ReservedCodeCacheSize < 4*G, "branch out of range");
690 assert(CodeCache::find_blob(entry.target()) != nullptr,
691 "destination of far call not found in code cache");
692 assert(entry.rspec().type() == relocInfo::external_word_type
693 || entry.rspec().type() == relocInfo::runtime_call_type
694 || entry.rspec().type() == relocInfo::none, "wrong entry relocInfo type");
695 if (target_needs_far_branch(entry.target())) {
696 uint64_t offset;
697 // We can use ADRP here because we know that the total size of
698 // the code cache cannot exceed 2Gb (ADRP limit is 4GB).
699 adrp(tmp, entry, offset);
700 add(tmp, tmp, offset);
701 blr(tmp);
702 } else {
703 bl(entry);
704 }
705 }
706
707 int MacroAssembler::far_jump(Address entry, Register tmp) {
708 assert(ReservedCodeCacheSize < 4*G, "branch out of range");
709 assert(CodeCache::find_blob(entry.target()) != nullptr,
710 "destination of far call not found in code cache");
711 assert(entry.rspec().type() == relocInfo::external_word_type
712 || entry.rspec().type() == relocInfo::runtime_call_type
713 || entry.rspec().type() == relocInfo::none, "wrong entry relocInfo type");
714 address start = pc();
715 if (target_needs_far_branch(entry.target())) {
716 uint64_t offset;
717 // We can use ADRP here because we know that the total size of
718 // the code cache cannot exceed 2Gb (ADRP limit is 4GB).
719 adrp(tmp, entry, offset);
720 add(tmp, tmp, offset);
721 br(tmp);
722 } else {
723 b(entry);
724 }
725 return pc() - start;
726 }
727
728 void MacroAssembler::reserved_stack_check() {
729 // testing if reserved zone needs to be enabled
730 Label no_reserved_zone_enabling;
731
732 ldr(rscratch1, Address(rthread, JavaThread::reserved_stack_activation_offset()));
733 cmp(sp, rscratch1);
734 br(Assembler::LO, no_reserved_zone_enabling);
735
736 enter(); // LR and FP are live.
737 lea(rscratch1, CAST_FROM_FN_PTR(address, SharedRuntime::enable_stack_reserved_zone));
738 mov(c_rarg0, rthread);
739 blr(rscratch1);
740 leave();
741
742 // We have already removed our own frame.
743 // throw_delayed_StackOverflowError will think that it's been
744 // called by our caller.
745 lea(rscratch1, RuntimeAddress(StubRoutines::throw_delayed_StackOverflowError_entry()));
746 br(rscratch1);
747 should_not_reach_here();
748
749 bind(no_reserved_zone_enabling);
750 }
751
752 static void pass_arg0(MacroAssembler* masm, Register arg) {
753 if (c_rarg0 != arg ) {
754 masm->mov(c_rarg0, arg);
755 }
756 }
757
758 static void pass_arg1(MacroAssembler* masm, Register arg) {
759 if (c_rarg1 != arg ) {
760 masm->mov(c_rarg1, arg);
761 }
762 }
763
764 static void pass_arg2(MacroAssembler* masm, Register arg) {
765 if (c_rarg2 != arg ) {
766 masm->mov(c_rarg2, arg);
767 }
768 }
769
770 static void pass_arg3(MacroAssembler* masm, Register arg) {
771 if (c_rarg3 != arg ) {
772 masm->mov(c_rarg3, arg);
773 }
774 }
775
776 void MacroAssembler::call_VM_base(Register oop_result,
777 Register java_thread,
778 Register last_java_sp,
779 address entry_point,
780 int number_of_arguments,
781 bool check_exceptions) {
782 // determine java_thread register
783 if (!java_thread->is_valid()) {
784 java_thread = rthread;
785 }
786
787 // determine last_java_sp register
788 if (!last_java_sp->is_valid()) {
789 last_java_sp = esp;
790 }
791
792 // debugging support
793 assert(number_of_arguments >= 0 , "cannot have negative number of arguments");
794 assert(java_thread == rthread, "unexpected register");
795 #ifdef ASSERT
796 // TraceBytecodes does not use r12 but saves it over the call, so don't verify
797 // if ((UseCompressedOops || UseCompressedClassPointers) && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?");
798 #endif // ASSERT
799
800 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result");
801 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp");
802
803 // push java thread (becomes first argument of C function)
804
805 mov(c_rarg0, java_thread);
806
807 // set last Java frame before call
808 assert(last_java_sp != rfp, "can't use rfp");
809
810 Label l;
811 set_last_Java_frame(last_java_sp, rfp, l, rscratch1);
812
813 // do the call, remove parameters
814 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments, &l);
815
816 // lr could be poisoned with PAC signature during throw_pending_exception
817 // if it was tail-call optimized by compiler, since lr is not callee-saved
818 // reload it with proper value
819 adr(lr, l);
820
821 // reset last Java frame
822 // Only interpreter should have to clear fp
823 reset_last_Java_frame(true);
824
825 // C++ interp handles this in the interpreter
826 check_and_handle_popframe(java_thread);
827 check_and_handle_earlyret(java_thread);
828
829 if (check_exceptions) {
830 // check for pending exceptions (java_thread is set upon return)
831 ldr(rscratch1, Address(java_thread, in_bytes(Thread::pending_exception_offset())));
832 Label ok;
833 cbz(rscratch1, ok);
834 lea(rscratch1, RuntimeAddress(StubRoutines::forward_exception_entry()));
835 br(rscratch1);
836 bind(ok);
837 }
838
839 // get oop result if there is one and reset the value in the thread
840 if (oop_result->is_valid()) {
841 get_vm_result(oop_result, java_thread);
842 }
843 }
844
845 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
846 call_VM_base(oop_result, noreg, noreg, entry_point, number_of_arguments, check_exceptions);
847 }
848
849 // Check the entry target is always reachable from any branch.
850 static bool is_always_within_branch_range(Address entry) {
851 const address target = entry.target();
852
853 if (!CodeCache::contains(target)) {
854 // We always use trampolines for callees outside CodeCache.
855 assert(entry.rspec().type() == relocInfo::runtime_call_type, "non-runtime call of an external target");
856 return false;
857 }
858
859 if (!MacroAssembler::far_branches()) {
860 return true;
861 }
862
863 if (entry.rspec().type() == relocInfo::runtime_call_type) {
864 // Runtime calls are calls of a non-compiled method (stubs, adapters).
865 // Non-compiled methods stay forever in CodeCache.
866 // We check whether the longest possible branch is within the branch range.
867 assert(CodeCache::find_blob(target) != nullptr &&
868 !CodeCache::find_blob(target)->is_compiled(),
869 "runtime call of compiled method");
870 const address right_longest_branch_start = CodeCache::high_bound() - NativeInstruction::instruction_size;
871 const address left_longest_branch_start = CodeCache::low_bound();
872 const bool is_reachable = Assembler::reachable_from_branch_at(left_longest_branch_start, target) &&
873 Assembler::reachable_from_branch_at(right_longest_branch_start, target);
874 return is_reachable;
875 }
876
877 return false;
878 }
879
880 // Maybe emit a call via a trampoline. If the code cache is small
881 // trampolines won't be emitted.
882 address MacroAssembler::trampoline_call(Address entry) {
883 assert(entry.rspec().type() == relocInfo::runtime_call_type
884 || entry.rspec().type() == relocInfo::opt_virtual_call_type
885 || entry.rspec().type() == relocInfo::static_call_type
886 || entry.rspec().type() == relocInfo::virtual_call_type, "wrong reloc type");
887
888 address target = entry.target();
889
890 if (!is_always_within_branch_range(entry)) {
891 if (!in_scratch_emit_size()) {
892 // We don't want to emit a trampoline if C2 is generating dummy
893 // code during its branch shortening phase.
894 if (entry.rspec().type() == relocInfo::runtime_call_type) {
895 assert(CodeBuffer::supports_shared_stubs(), "must support shared stubs");
896 code()->share_trampoline_for(entry.target(), offset());
897 } else {
898 address stub = emit_trampoline_stub(offset(), target);
899 if (stub == nullptr) {
900 postcond(pc() == badAddress);
901 return nullptr; // CodeCache is full
902 }
903 }
904 }
905 target = pc();
906 }
907
908 address call_pc = pc();
909 relocate(entry.rspec());
910 bl(target);
911
912 postcond(pc() != badAddress);
913 return call_pc;
914 }
915
916 // Emit a trampoline stub for a call to a target which is too far away.
917 //
918 // code sequences:
919 //
920 // call-site:
921 // branch-and-link to <destination> or <trampoline stub>
922 //
923 // Related trampoline stub for this call site in the stub section:
924 // load the call target from the constant pool
925 // branch (LR still points to the call site above)
926
927 address MacroAssembler::emit_trampoline_stub(int insts_call_instruction_offset,
928 address dest) {
929 // Max stub size: alignment nop, TrampolineStub.
930 address stub = start_a_stub(max_trampoline_stub_size());
931 if (stub == nullptr) {
932 return nullptr; // CodeBuffer::expand failed
933 }
934
935 // Create a trampoline stub relocation which relates this trampoline stub
936 // with the call instruction at insts_call_instruction_offset in the
937 // instructions code-section.
938 align(wordSize);
939 relocate(trampoline_stub_Relocation::spec(code()->insts()->start()
940 + insts_call_instruction_offset));
941 const int stub_start_offset = offset();
942
943 // Now, create the trampoline stub's code:
944 // - load the call
945 // - call
946 Label target;
947 ldr(rscratch1, target);
948 br(rscratch1);
949 bind(target);
950 assert(offset() - stub_start_offset == NativeCallTrampolineStub::data_offset,
951 "should be");
952 emit_int64((int64_t)dest);
953
954 const address stub_start_addr = addr_at(stub_start_offset);
955
956 assert(is_NativeCallTrampolineStub_at(stub_start_addr), "doesn't look like a trampoline");
957
958 end_a_stub();
959 return stub_start_addr;
960 }
961
962 int MacroAssembler::max_trampoline_stub_size() {
963 // Max stub size: alignment nop, TrampolineStub.
964 return NativeInstruction::instruction_size + NativeCallTrampolineStub::instruction_size;
965 }
966
967 void MacroAssembler::emit_static_call_stub() {
968 // CompiledDirectStaticCall::set_to_interpreted knows the
969 // exact layout of this stub.
970
971 isb();
972 mov_metadata(rmethod, nullptr);
973
974 // Jump to the entry point of the c2i stub.
975 movptr(rscratch1, 0);
976 br(rscratch1);
977 }
978
979 int MacroAssembler::static_call_stub_size() {
980 // isb; movk; movz; movz; movk; movz; movz; br
981 return 8 * NativeInstruction::instruction_size;
982 }
983
984 void MacroAssembler::c2bool(Register x) {
985 // implements x == 0 ? 0 : 1
986 // note: must only look at least-significant byte of x
987 // since C-style booleans are stored in one byte
988 // only! (was bug)
989 tst(x, 0xff);
990 cset(x, Assembler::NE);
991 }
992
993 address MacroAssembler::ic_call(address entry, jint method_index) {
994 RelocationHolder rh = virtual_call_Relocation::spec(pc(), method_index);
995 // address const_ptr = long_constant((jlong)Universe::non_oop_word());
996 // uintptr_t offset;
997 // ldr_constant(rscratch2, const_ptr);
998 movptr(rscratch2, (uintptr_t)Universe::non_oop_word());
999 return trampoline_call(Address(entry, rh));
1000 }
1001
1002 // Implementation of call_VM versions
1003
1004 void MacroAssembler::call_VM(Register oop_result,
1005 address entry_point,
1006 bool check_exceptions) {
1007 call_VM_helper(oop_result, entry_point, 0, check_exceptions);
1008 }
1009
1010 void MacroAssembler::call_VM(Register oop_result,
1011 address entry_point,
1012 Register arg_1,
1013 bool check_exceptions) {
1014 pass_arg1(this, arg_1);
1015 call_VM_helper(oop_result, entry_point, 1, check_exceptions);
1016 }
1017
1018 void MacroAssembler::call_VM(Register oop_result,
1019 address entry_point,
1020 Register arg_1,
1021 Register arg_2,
1022 bool check_exceptions) {
1023 assert(arg_1 != c_rarg2, "smashed arg");
1024 pass_arg2(this, arg_2);
1025 pass_arg1(this, arg_1);
1026 call_VM_helper(oop_result, entry_point, 2, check_exceptions);
1027 }
1028
1029 void MacroAssembler::call_VM(Register oop_result,
1030 address entry_point,
1031 Register arg_1,
1032 Register arg_2,
1033 Register arg_3,
1034 bool check_exceptions) {
1035 assert(arg_1 != c_rarg3, "smashed arg");
1036 assert(arg_2 != c_rarg3, "smashed arg");
1037 pass_arg3(this, arg_3);
1038
1039 assert(arg_1 != c_rarg2, "smashed arg");
1040 pass_arg2(this, arg_2);
1041
1042 pass_arg1(this, arg_1);
1043 call_VM_helper(oop_result, entry_point, 3, check_exceptions);
1044 }
1045
1046 void MacroAssembler::call_VM(Register oop_result,
1047 Register last_java_sp,
1048 address entry_point,
1049 int number_of_arguments,
1050 bool check_exceptions) {
1051 call_VM_base(oop_result, rthread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
1052 }
1053
1054 void MacroAssembler::call_VM(Register oop_result,
1055 Register last_java_sp,
1056 address entry_point,
1057 Register arg_1,
1058 bool check_exceptions) {
1059 pass_arg1(this, arg_1);
1060 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
1061 }
1062
1063 void MacroAssembler::call_VM(Register oop_result,
1064 Register last_java_sp,
1065 address entry_point,
1066 Register arg_1,
1067 Register arg_2,
1068 bool check_exceptions) {
1069
1070 assert(arg_1 != c_rarg2, "smashed arg");
1071 pass_arg2(this, arg_2);
1072 pass_arg1(this, arg_1);
1073 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
1074 }
1075
1076 void MacroAssembler::call_VM(Register oop_result,
1077 Register last_java_sp,
1078 address entry_point,
1079 Register arg_1,
1080 Register arg_2,
1081 Register arg_3,
1082 bool check_exceptions) {
1083 assert(arg_1 != c_rarg3, "smashed arg");
1084 assert(arg_2 != c_rarg3, "smashed arg");
1085 pass_arg3(this, arg_3);
1086 assert(arg_1 != c_rarg2, "smashed arg");
1087 pass_arg2(this, arg_2);
1088 pass_arg1(this, arg_1);
1089 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
1090 }
1091
1092
1093 void MacroAssembler::get_vm_result(Register oop_result, Register java_thread) {
1094 ldr(oop_result, Address(java_thread, JavaThread::vm_result_offset()));
1095 str(zr, Address(java_thread, JavaThread::vm_result_offset()));
1096 verify_oop_msg(oop_result, "broken oop in call_VM_base");
1097 }
1098
1099 void MacroAssembler::get_vm_result_2(Register metadata_result, Register java_thread) {
1100 ldr(metadata_result, Address(java_thread, JavaThread::vm_result_2_offset()));
1101 str(zr, Address(java_thread, JavaThread::vm_result_2_offset()));
1102 }
1103
1104 void MacroAssembler::align(int modulus) {
1105 while (offset() % modulus != 0) nop();
1106 }
1107
1108 void MacroAssembler::post_call_nop() {
1109 if (!Continuations::enabled()) {
1110 return;
1111 }
1112 InstructionMark im(this);
1113 relocate(post_call_nop_Relocation::spec());
1114 InlineSkippedInstructionsCounter skipCounter(this);
1115 nop();
1116 movk(zr, 0);
1117 movk(zr, 0);
1118 }
1119
1120 // these are no-ops overridden by InterpreterMacroAssembler
1121
1122 void MacroAssembler::check_and_handle_earlyret(Register java_thread) { }
1123
1124 void MacroAssembler::check_and_handle_popframe(Register java_thread) { }
1125
1126 // Look up the method for a megamorphic invokeinterface call.
1127 // The target method is determined by <intf_klass, itable_index>.
1128 // The receiver klass is in recv_klass.
1129 // On success, the result will be in method_result, and execution falls through.
1130 // On failure, execution transfers to the given label.
1131 void MacroAssembler::lookup_interface_method(Register recv_klass,
1132 Register intf_klass,
1133 RegisterOrConstant itable_index,
1134 Register method_result,
1135 Register scan_temp,
1136 Label& L_no_such_interface,
1137 bool return_method) {
1138 assert_different_registers(recv_klass, intf_klass, scan_temp);
1139 assert_different_registers(method_result, intf_klass, scan_temp);
1140 assert(recv_klass != method_result || !return_method,
1141 "recv_klass can be destroyed when method isn't needed");
1142 assert(itable_index.is_constant() || itable_index.as_register() == method_result,
1143 "caller must use same register for non-constant itable index as for method");
1144
1145 // Compute start of first itableOffsetEntry (which is at the end of the vtable)
1146 int vtable_base = in_bytes(Klass::vtable_start_offset());
1147 int itentry_off = in_bytes(itableMethodEntry::method_offset());
1148 int scan_step = itableOffsetEntry::size() * wordSize;
1149 int vte_size = vtableEntry::size_in_bytes();
1150 assert(vte_size == wordSize, "else adjust times_vte_scale");
1151
1152 ldrw(scan_temp, Address(recv_klass, Klass::vtable_length_offset()));
1153
1154 // %%% Could store the aligned, prescaled offset in the klassoop.
1155 // lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base));
1156 lea(scan_temp, Address(recv_klass, scan_temp, Address::lsl(3)));
1157 add(scan_temp, scan_temp, vtable_base);
1158
1159 if (return_method) {
1160 // Adjust recv_klass by scaled itable_index, so we can free itable_index.
1161 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
1162 // lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off));
1163 lea(recv_klass, Address(recv_klass, itable_index, Address::lsl(3)));
1164 if (itentry_off)
1165 add(recv_klass, recv_klass, itentry_off);
1166 }
1167
1168 // for (scan = klass->itable(); scan->interface() != nullptr; scan += scan_step) {
1169 // if (scan->interface() == intf) {
1170 // result = (klass + scan->offset() + itable_index);
1171 // }
1172 // }
1173 Label search, found_method;
1174
1175 ldr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset()));
1176 cmp(intf_klass, method_result);
1177 br(Assembler::EQ, found_method);
1178 bind(search);
1179 // Check that the previous entry is non-null. A null entry means that
1180 // the receiver class doesn't implement the interface, and wasn't the
1181 // same as when the caller was compiled.
1182 cbz(method_result, L_no_such_interface);
1183 if (itableOffsetEntry::interface_offset() != 0) {
1184 add(scan_temp, scan_temp, scan_step);
1185 ldr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset()));
1186 } else {
1187 ldr(method_result, Address(pre(scan_temp, scan_step)));
1188 }
1189 cmp(intf_klass, method_result);
1190 br(Assembler::NE, search);
1191
1192 bind(found_method);
1193
1194 // Got a hit.
1195 if (return_method) {
1196 ldrw(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset()));
1197 ldr(method_result, Address(recv_klass, scan_temp, Address::uxtw(0)));
1198 }
1199 }
1200
1201 // Look up the method for a megamorphic invokeinterface call in a single pass over itable:
1202 // - check recv_klass (actual object class) is a subtype of resolved_klass from CompiledICHolder
1203 // - find a holder_klass (class that implements the method) vtable offset and get the method from vtable by index
1204 // The target method is determined by <holder_klass, itable_index>.
1205 // The receiver klass is in recv_klass.
1206 // On success, the result will be in method_result, and execution falls through.
1207 // On failure, execution transfers to the given label.
1208 void MacroAssembler::lookup_interface_method_stub(Register recv_klass,
1209 Register holder_klass,
1210 Register resolved_klass,
1211 Register method_result,
1212 Register temp_itbl_klass,
1213 Register scan_temp,
1214 int itable_index,
1215 Label& L_no_such_interface) {
1216 // 'method_result' is only used as output register at the very end of this method.
1217 // Until then we can reuse it as 'holder_offset'.
1218 Register holder_offset = method_result;
1219 assert_different_registers(resolved_klass, recv_klass, holder_klass, temp_itbl_klass, scan_temp, holder_offset);
1220
1221 int vtable_start_offset = in_bytes(Klass::vtable_start_offset());
1222 int itable_offset_entry_size = itableOffsetEntry::size() * wordSize;
1223 int ioffset = in_bytes(itableOffsetEntry::interface_offset());
1224 int ooffset = in_bytes(itableOffsetEntry::offset_offset());
1225
1226 Label L_loop_search_resolved_entry, L_resolved_found, L_holder_found;
1227
1228 ldrw(scan_temp, Address(recv_klass, Klass::vtable_length_offset()));
1229 add(recv_klass, recv_klass, vtable_start_offset + ioffset);
1230 // itableOffsetEntry[] itable = recv_klass + Klass::vtable_start_offset() + sizeof(vtableEntry) * recv_klass->_vtable_len;
1231 // temp_itbl_klass = itable[0]._interface;
1232 int vtblEntrySize = vtableEntry::size_in_bytes();
1233 assert(vtblEntrySize == wordSize, "ldr lsl shift amount must be 3");
1234 ldr(temp_itbl_klass, Address(recv_klass, scan_temp, Address::lsl(exact_log2(vtblEntrySize))));
1235 mov(holder_offset, zr);
1236 // scan_temp = &(itable[0]._interface)
1237 lea(scan_temp, Address(recv_klass, scan_temp, Address::lsl(exact_log2(vtblEntrySize))));
1238
1239 // Initial checks:
1240 // - if (holder_klass != resolved_klass), go to "scan for resolved"
1241 // - if (itable[0] == holder_klass), shortcut to "holder found"
1242 // - if (itable[0] == 0), no such interface
1243 cmp(resolved_klass, holder_klass);
1244 br(Assembler::NE, L_loop_search_resolved_entry);
1245 cmp(holder_klass, temp_itbl_klass);
1246 br(Assembler::EQ, L_holder_found);
1247 cbz(temp_itbl_klass, L_no_such_interface);
1248
1249 // Loop: Look for holder_klass record in itable
1250 // do {
1251 // temp_itbl_klass = *(scan_temp += itable_offset_entry_size);
1252 // if (temp_itbl_klass == holder_klass) {
1253 // goto L_holder_found; // Found!
1254 // }
1255 // } while (temp_itbl_klass != 0);
1256 // goto L_no_such_interface // Not found.
1257 Label L_search_holder;
1258 bind(L_search_holder);
1259 ldr(temp_itbl_klass, Address(pre(scan_temp, itable_offset_entry_size)));
1260 cmp(holder_klass, temp_itbl_klass);
1261 br(Assembler::EQ, L_holder_found);
1262 cbnz(temp_itbl_klass, L_search_holder);
1263
1264 b(L_no_such_interface);
1265
1266 // Loop: Look for resolved_class record in itable
1267 // while (true) {
1268 // temp_itbl_klass = *(scan_temp += itable_offset_entry_size);
1269 // if (temp_itbl_klass == 0) {
1270 // goto L_no_such_interface;
1271 // }
1272 // if (temp_itbl_klass == resolved_klass) {
1273 // goto L_resolved_found; // Found!
1274 // }
1275 // if (temp_itbl_klass == holder_klass) {
1276 // holder_offset = scan_temp;
1277 // }
1278 // }
1279 //
1280 Label L_loop_search_resolved;
1281 bind(L_loop_search_resolved);
1282 ldr(temp_itbl_klass, Address(pre(scan_temp, itable_offset_entry_size)));
1283 bind(L_loop_search_resolved_entry);
1284 cbz(temp_itbl_klass, L_no_such_interface);
1285 cmp(resolved_klass, temp_itbl_klass);
1286 br(Assembler::EQ, L_resolved_found);
1287 cmp(holder_klass, temp_itbl_klass);
1288 br(Assembler::NE, L_loop_search_resolved);
1289 mov(holder_offset, scan_temp);
1290 b(L_loop_search_resolved);
1291
1292 // See if we already have a holder klass. If not, go and scan for it.
1293 bind(L_resolved_found);
1294 cbz(holder_offset, L_search_holder);
1295 mov(scan_temp, holder_offset);
1296
1297 // Finally, scan_temp contains holder_klass vtable offset
1298 bind(L_holder_found);
1299 ldrw(method_result, Address(scan_temp, ooffset - ioffset));
1300 add(recv_klass, recv_klass, itable_index * wordSize + in_bytes(itableMethodEntry::method_offset())
1301 - vtable_start_offset - ioffset); // substract offsets to restore the original value of recv_klass
1302 ldr(method_result, Address(recv_klass, method_result, Address::uxtw(0)));
1303 }
1304
1305 // virtual method calling
1306 void MacroAssembler::lookup_virtual_method(Register recv_klass,
1307 RegisterOrConstant vtable_index,
1308 Register method_result) {
1309 assert(vtableEntry::size() * wordSize == 8,
1310 "adjust the scaling in the code below");
1311 int64_t vtable_offset_in_bytes = in_bytes(Klass::vtable_start_offset() + vtableEntry::method_offset());
1312
1313 if (vtable_index.is_register()) {
1314 lea(method_result, Address(recv_klass,
1315 vtable_index.as_register(),
1316 Address::lsl(LogBytesPerWord)));
1317 ldr(method_result, Address(method_result, vtable_offset_in_bytes));
1318 } else {
1319 vtable_offset_in_bytes += vtable_index.as_constant() * wordSize;
1320 ldr(method_result,
1321 form_address(rscratch1, recv_klass, vtable_offset_in_bytes, 0));
1322 }
1323 }
1324
1325 void MacroAssembler::check_klass_subtype(Register sub_klass,
1326 Register super_klass,
1327 Register temp_reg,
1328 Label& L_success) {
1329 Label L_failure;
1330 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, nullptr);
1331 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, nullptr);
1332 bind(L_failure);
1333 }
1334
1335
1336 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
1337 Register super_klass,
1338 Register temp_reg,
1339 Label* L_success,
1340 Label* L_failure,
1341 Label* L_slow_path,
1342 RegisterOrConstant super_check_offset) {
1343 assert_different_registers(sub_klass, super_klass, temp_reg);
1344 bool must_load_sco = (super_check_offset.constant_or_zero() == -1);
1345 if (super_check_offset.is_register()) {
1346 assert_different_registers(sub_klass, super_klass,
1347 super_check_offset.as_register());
1348 } else if (must_load_sco) {
1349 assert(temp_reg != noreg, "supply either a temp or a register offset");
1350 }
1351
1352 Label L_fallthrough;
1353 int label_nulls = 0;
1354 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
1355 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
1356 if (L_slow_path == nullptr) { L_slow_path = &L_fallthrough; label_nulls++; }
1357 assert(label_nulls <= 1, "at most one null in the batch");
1358
1359 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
1360 int sco_offset = in_bytes(Klass::super_check_offset_offset());
1361 Address super_check_offset_addr(super_klass, sco_offset);
1362
1363 // Hacked jmp, which may only be used just before L_fallthrough.
1364 #define final_jmp(label) \
1365 if (&(label) == &L_fallthrough) { /*do nothing*/ } \
1366 else b(label) /*omit semi*/
1367
1368 // If the pointers are equal, we are done (e.g., String[] elements).
1369 // This self-check enables sharing of secondary supertype arrays among
1370 // non-primary types such as array-of-interface. Otherwise, each such
1371 // type would need its own customized SSA.
1372 // We move this check to the front of the fast path because many
1373 // type checks are in fact trivially successful in this manner,
1374 // so we get a nicely predicted branch right at the start of the check.
1375 cmp(sub_klass, super_klass);
1376 br(Assembler::EQ, *L_success);
1377
1378 // Check the supertype display:
1379 if (must_load_sco) {
1380 ldrw(temp_reg, super_check_offset_addr);
1381 super_check_offset = RegisterOrConstant(temp_reg);
1382 }
1383 Address super_check_addr(sub_klass, super_check_offset);
1384 ldr(rscratch1, super_check_addr);
1385 cmp(super_klass, rscratch1); // load displayed supertype
1386
1387 // This check has worked decisively for primary supers.
1388 // Secondary supers are sought in the super_cache ('super_cache_addr').
1389 // (Secondary supers are interfaces and very deeply nested subtypes.)
1390 // This works in the same check above because of a tricky aliasing
1391 // between the super_cache and the primary super display elements.
1392 // (The 'super_check_addr' can address either, as the case requires.)
1393 // Note that the cache is updated below if it does not help us find
1394 // what we need immediately.
1395 // So if it was a primary super, we can just fail immediately.
1396 // Otherwise, it's the slow path for us (no success at this point).
1397
1398 if (super_check_offset.is_register()) {
1399 br(Assembler::EQ, *L_success);
1400 subs(zr, super_check_offset.as_register(), sc_offset);
1401 if (L_failure == &L_fallthrough) {
1402 br(Assembler::EQ, *L_slow_path);
1403 } else {
1404 br(Assembler::NE, *L_failure);
1405 final_jmp(*L_slow_path);
1406 }
1407 } else if (super_check_offset.as_constant() == sc_offset) {
1408 // Need a slow path; fast failure is impossible.
1409 if (L_slow_path == &L_fallthrough) {
1410 br(Assembler::EQ, *L_success);
1411 } else {
1412 br(Assembler::NE, *L_slow_path);
1413 final_jmp(*L_success);
1414 }
1415 } else {
1416 // No slow path; it's a fast decision.
1417 if (L_failure == &L_fallthrough) {
1418 br(Assembler::EQ, *L_success);
1419 } else {
1420 br(Assembler::NE, *L_failure);
1421 final_jmp(*L_success);
1422 }
1423 }
1424
1425 bind(L_fallthrough);
1426
1427 #undef final_jmp
1428 }
1429
1430 // These two are taken from x86, but they look generally useful
1431
1432 // scans count pointer sized words at [addr] for occurrence of value,
1433 // generic
1434 void MacroAssembler::repne_scan(Register addr, Register value, Register count,
1435 Register scratch) {
1436 Label Lloop, Lexit;
1437 cbz(count, Lexit);
1438 bind(Lloop);
1439 ldr(scratch, post(addr, wordSize));
1440 cmp(value, scratch);
1441 br(EQ, Lexit);
1442 sub(count, count, 1);
1443 cbnz(count, Lloop);
1444 bind(Lexit);
1445 }
1446
1447 // scans count 4 byte words at [addr] for occurrence of value,
1448 // generic
1449 void MacroAssembler::repne_scanw(Register addr, Register value, Register count,
1450 Register scratch) {
1451 Label Lloop, Lexit;
1452 cbz(count, Lexit);
1453 bind(Lloop);
1454 ldrw(scratch, post(addr, wordSize));
1455 cmpw(value, scratch);
1456 br(EQ, Lexit);
1457 sub(count, count, 1);
1458 cbnz(count, Lloop);
1459 bind(Lexit);
1460 }
1461
1462 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
1463 Register super_klass,
1464 Register temp_reg,
1465 Register temp2_reg,
1466 Label* L_success,
1467 Label* L_failure,
1468 bool set_cond_codes) {
1469 assert_different_registers(sub_klass, super_klass, temp_reg);
1470 if (temp2_reg != noreg)
1471 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg, rscratch1);
1472 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg)
1473
1474 Label L_fallthrough;
1475 int label_nulls = 0;
1476 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
1477 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
1478 assert(label_nulls <= 1, "at most one null in the batch");
1479
1480 // a couple of useful fields in sub_klass:
1481 int ss_offset = in_bytes(Klass::secondary_supers_offset());
1482 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
1483 Address secondary_supers_addr(sub_klass, ss_offset);
1484 Address super_cache_addr( sub_klass, sc_offset);
1485
1486 BLOCK_COMMENT("check_klass_subtype_slow_path");
1487
1488 // Do a linear scan of the secondary super-klass chain.
1489 // This code is rarely used, so simplicity is a virtue here.
1490 // The repne_scan instruction uses fixed registers, which we must spill.
1491 // Don't worry too much about pre-existing connections with the input regs.
1492
1493 assert(sub_klass != r0, "killed reg"); // killed by mov(r0, super)
1494 assert(sub_klass != r2, "killed reg"); // killed by lea(r2, &pst_counter)
1495
1496 RegSet pushed_registers;
1497 if (!IS_A_TEMP(r2)) pushed_registers += r2;
1498 if (!IS_A_TEMP(r5)) pushed_registers += r5;
1499
1500 if (super_klass != r0) {
1501 if (!IS_A_TEMP(r0)) pushed_registers += r0;
1502 }
1503
1504 push(pushed_registers, sp);
1505
1506 // Get super_klass value into r0 (even if it was in r5 or r2).
1507 if (super_klass != r0) {
1508 mov(r0, super_klass);
1509 }
1510
1511 #ifndef PRODUCT
1512 mov(rscratch2, (address)&SharedRuntime::_partial_subtype_ctr);
1513 Address pst_counter_addr(rscratch2);
1514 ldr(rscratch1, pst_counter_addr);
1515 add(rscratch1, rscratch1, 1);
1516 str(rscratch1, pst_counter_addr);
1517 #endif //PRODUCT
1518
1519 // We will consult the secondary-super array.
1520 ldr(r5, secondary_supers_addr);
1521 // Load the array length.
1522 ldrw(r2, Address(r5, Array<Klass*>::length_offset_in_bytes()));
1523 // Skip to start of data.
1524 add(r5, r5, Array<Klass*>::base_offset_in_bytes());
1525
1526 cmp(sp, zr); // Clear Z flag; SP is never zero
1527 // Scan R2 words at [R5] for an occurrence of R0.
1528 // Set NZ/Z based on last compare.
1529 repne_scan(r5, r0, r2, rscratch1);
1530
1531 // Unspill the temp. registers:
1532 pop(pushed_registers, sp);
1533
1534 br(Assembler::NE, *L_failure);
1535
1536 // Success. Cache the super we found and proceed in triumph.
1537 str(super_klass, super_cache_addr);
1538
1539 if (L_success != &L_fallthrough) {
1540 b(*L_success);
1541 }
1542
1543 #undef IS_A_TEMP
1544
1545 bind(L_fallthrough);
1546 }
1547
1548 void MacroAssembler::clinit_barrier(Register klass, Register scratch, Label* L_fast_path, Label* L_slow_path) {
1549 assert(L_fast_path != nullptr || L_slow_path != nullptr, "at least one is required");
1550 assert_different_registers(klass, rthread, scratch);
1551
1552 Label L_fallthrough, L_tmp;
1553 if (L_fast_path == nullptr) {
1554 L_fast_path = &L_fallthrough;
1555 } else if (L_slow_path == nullptr) {
1556 L_slow_path = &L_fallthrough;
1557 }
1558 // Fast path check: class is fully initialized
1559 ldrb(scratch, Address(klass, InstanceKlass::init_state_offset()));
1560 subs(zr, scratch, InstanceKlass::fully_initialized);
1561 br(Assembler::EQ, *L_fast_path);
1562
1563 // Fast path check: current thread is initializer thread
1564 ldr(scratch, Address(klass, InstanceKlass::init_thread_offset()));
1565 cmp(rthread, scratch);
1566
1567 if (L_slow_path == &L_fallthrough) {
1568 br(Assembler::EQ, *L_fast_path);
1569 bind(*L_slow_path);
1570 } else if (L_fast_path == &L_fallthrough) {
1571 br(Assembler::NE, *L_slow_path);
1572 bind(*L_fast_path);
1573 } else {
1574 Unimplemented();
1575 }
1576 }
1577
1578 void MacroAssembler::_verify_oop(Register reg, const char* s, const char* file, int line) {
1579 if (!VerifyOops) return;
1580
1581 // Pass register number to verify_oop_subroutine
1582 const char* b = nullptr;
1583 {
1584 ResourceMark rm;
1585 stringStream ss;
1586 ss.print("verify_oop: %s: %s (%s:%d)", reg->name(), s, file, line);
1587 b = code_string(ss.as_string());
1588 }
1589 BLOCK_COMMENT("verify_oop {");
1590
1591 strip_return_address(); // This might happen within a stack frame.
1592 protect_return_address();
1593 stp(r0, rscratch1, Address(pre(sp, -2 * wordSize)));
1594 stp(rscratch2, lr, Address(pre(sp, -2 * wordSize)));
1595
1596 mov(r0, reg);
1597 movptr(rscratch1, (uintptr_t)(address)b);
1598
1599 // call indirectly to solve generation ordering problem
1600 lea(rscratch2, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
1601 ldr(rscratch2, Address(rscratch2));
1602 blr(rscratch2);
1603
1604 ldp(rscratch2, lr, Address(post(sp, 2 * wordSize)));
1605 ldp(r0, rscratch1, Address(post(sp, 2 * wordSize)));
1606 authenticate_return_address();
1607
1608 BLOCK_COMMENT("} verify_oop");
1609 }
1610
1611 void MacroAssembler::_verify_oop_addr(Address addr, const char* s, const char* file, int line) {
1612 if (!VerifyOops) return;
1613
1614 const char* b = nullptr;
1615 {
1616 ResourceMark rm;
1617 stringStream ss;
1618 ss.print("verify_oop_addr: %s (%s:%d)", s, file, line);
1619 b = code_string(ss.as_string());
1620 }
1621 BLOCK_COMMENT("verify_oop_addr {");
1622
1623 strip_return_address(); // This might happen within a stack frame.
1624 protect_return_address();
1625 stp(r0, rscratch1, Address(pre(sp, -2 * wordSize)));
1626 stp(rscratch2, lr, Address(pre(sp, -2 * wordSize)));
1627
1628 // addr may contain sp so we will have to adjust it based on the
1629 // pushes that we just did.
1630 if (addr.uses(sp)) {
1631 lea(r0, addr);
1632 ldr(r0, Address(r0, 4 * wordSize));
1633 } else {
1634 ldr(r0, addr);
1635 }
1636 movptr(rscratch1, (uintptr_t)(address)b);
1637
1638 // call indirectly to solve generation ordering problem
1639 lea(rscratch2, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
1640 ldr(rscratch2, Address(rscratch2));
1641 blr(rscratch2);
1642
1643 ldp(rscratch2, lr, Address(post(sp, 2 * wordSize)));
1644 ldp(r0, rscratch1, Address(post(sp, 2 * wordSize)));
1645 authenticate_return_address();
1646
1647 BLOCK_COMMENT("} verify_oop_addr");
1648 }
1649
1650 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot,
1651 int extra_slot_offset) {
1652 // cf. TemplateTable::prepare_invoke(), if (load_receiver).
1653 int stackElementSize = Interpreter::stackElementSize;
1654 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0);
1655 #ifdef ASSERT
1656 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1);
1657 assert(offset1 - offset == stackElementSize, "correct arithmetic");
1658 #endif
1659 if (arg_slot.is_constant()) {
1660 return Address(esp, arg_slot.as_constant() * stackElementSize
1661 + offset);
1662 } else {
1663 add(rscratch1, esp, arg_slot.as_register(),
1664 ext::uxtx, exact_log2(stackElementSize));
1665 return Address(rscratch1, offset);
1666 }
1667 }
1668
1669 void MacroAssembler::call_VM_leaf_base(address entry_point,
1670 int number_of_arguments,
1671 Label *retaddr) {
1672 Label E, L;
1673
1674 stp(rscratch1, rmethod, Address(pre(sp, -2 * wordSize)));
1675
1676 mov(rscratch1, entry_point);
1677 blr(rscratch1);
1678 if (retaddr)
1679 bind(*retaddr);
1680
1681 ldp(rscratch1, rmethod, Address(post(sp, 2 * wordSize)));
1682 }
1683
1684 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) {
1685 call_VM_leaf_base(entry_point, number_of_arguments);
1686 }
1687
1688 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) {
1689 pass_arg0(this, arg_0);
1690 call_VM_leaf_base(entry_point, 1);
1691 }
1692
1693 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
1694 pass_arg0(this, arg_0);
1695 pass_arg1(this, arg_1);
1696 call_VM_leaf_base(entry_point, 2);
1697 }
1698
1699 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0,
1700 Register arg_1, Register arg_2) {
1701 pass_arg0(this, arg_0);
1702 pass_arg1(this, arg_1);
1703 pass_arg2(this, arg_2);
1704 call_VM_leaf_base(entry_point, 3);
1705 }
1706
1707 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) {
1708 pass_arg0(this, arg_0);
1709 MacroAssembler::call_VM_leaf_base(entry_point, 1);
1710 }
1711
1712 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
1713
1714 assert(arg_0 != c_rarg1, "smashed arg");
1715 pass_arg1(this, arg_1);
1716 pass_arg0(this, arg_0);
1717 MacroAssembler::call_VM_leaf_base(entry_point, 2);
1718 }
1719
1720 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
1721 assert(arg_0 != c_rarg2, "smashed arg");
1722 assert(arg_1 != c_rarg2, "smashed arg");
1723 pass_arg2(this, arg_2);
1724 assert(arg_0 != c_rarg1, "smashed arg");
1725 pass_arg1(this, arg_1);
1726 pass_arg0(this, arg_0);
1727 MacroAssembler::call_VM_leaf_base(entry_point, 3);
1728 }
1729
1730 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
1731 assert(arg_0 != c_rarg3, "smashed arg");
1732 assert(arg_1 != c_rarg3, "smashed arg");
1733 assert(arg_2 != c_rarg3, "smashed arg");
1734 pass_arg3(this, arg_3);
1735 assert(arg_0 != c_rarg2, "smashed arg");
1736 assert(arg_1 != c_rarg2, "smashed arg");
1737 pass_arg2(this, arg_2);
1738 assert(arg_0 != c_rarg1, "smashed arg");
1739 pass_arg1(this, arg_1);
1740 pass_arg0(this, arg_0);
1741 MacroAssembler::call_VM_leaf_base(entry_point, 4);
1742 }
1743
1744 void MacroAssembler::null_check(Register reg, int offset) {
1745 if (needs_explicit_null_check(offset)) {
1746 // provoke OS null exception if reg is null by
1747 // accessing M[reg] w/o changing any registers
1748 // NOTE: this is plenty to provoke a segv
1749 ldr(zr, Address(reg));
1750 } else {
1751 // nothing to do, (later) access of M[reg + offset]
1752 // will provoke OS null exception if reg is null
1753 }
1754 }
1755
1756 // MacroAssembler protected routines needed to implement
1757 // public methods
1758
1759 void MacroAssembler::mov(Register r, Address dest) {
1760 code_section()->relocate(pc(), dest.rspec());
1761 uint64_t imm64 = (uint64_t)dest.target();
1762 movptr(r, imm64);
1763 }
1764
1765 // Move a constant pointer into r. In AArch64 mode the virtual
1766 // address space is 48 bits in size, so we only need three
1767 // instructions to create a patchable instruction sequence that can
1768 // reach anywhere.
1769 void MacroAssembler::movptr(Register r, uintptr_t imm64) {
1770 #ifndef PRODUCT
1771 {
1772 char buffer[64];
1773 snprintf(buffer, sizeof(buffer), "0x%" PRIX64, (uint64_t)imm64);
1774 block_comment(buffer);
1775 }
1776 #endif
1777 assert(imm64 < (1ull << 48), "48-bit overflow in address constant");
1778 movz(r, imm64 & 0xffff);
1779 imm64 >>= 16;
1780 movk(r, imm64 & 0xffff, 16);
1781 imm64 >>= 16;
1782 movk(r, imm64 & 0xffff, 32);
1783 }
1784
1785 // Macro to mov replicated immediate to vector register.
1786 // imm64: only the lower 8/16/32 bits are considered for B/H/S type. That is,
1787 // the upper 56/48/32 bits must be zeros for B/H/S type.
1788 // Vd will get the following values for different arrangements in T
1789 // imm64 == hex 000000gh T8B: Vd = ghghghghghghghgh
1790 // imm64 == hex 000000gh T16B: Vd = ghghghghghghghghghghghghghghghgh
1791 // imm64 == hex 0000efgh T4H: Vd = efghefghefghefgh
1792 // imm64 == hex 0000efgh T8H: Vd = efghefghefghefghefghefghefghefgh
1793 // imm64 == hex abcdefgh T2S: Vd = abcdefghabcdefgh
1794 // imm64 == hex abcdefgh T4S: Vd = abcdefghabcdefghabcdefghabcdefgh
1795 // imm64 == hex abcdefgh T1D: Vd = 00000000abcdefgh
1796 // imm64 == hex abcdefgh T2D: Vd = 00000000abcdefgh00000000abcdefgh
1797 // Clobbers rscratch1
1798 void MacroAssembler::mov(FloatRegister Vd, SIMD_Arrangement T, uint64_t imm64) {
1799 assert(T != T1Q, "unsupported");
1800 if (T == T1D || T == T2D) {
1801 int imm = operand_valid_for_movi_immediate(imm64, T);
1802 if (-1 != imm) {
1803 movi(Vd, T, imm);
1804 } else {
1805 mov(rscratch1, imm64);
1806 dup(Vd, T, rscratch1);
1807 }
1808 return;
1809 }
1810
1811 #ifdef ASSERT
1812 if (T == T8B || T == T16B) assert((imm64 & ~0xff) == 0, "extraneous bits (T8B/T16B)");
1813 if (T == T4H || T == T8H) assert((imm64 & ~0xffff) == 0, "extraneous bits (T4H/T8H)");
1814 if (T == T2S || T == T4S) assert((imm64 & ~0xffffffff) == 0, "extraneous bits (T2S/T4S)");
1815 #endif
1816 int shift = operand_valid_for_movi_immediate(imm64, T);
1817 uint32_t imm32 = imm64 & 0xffffffffULL;
1818 if (shift >= 0) {
1819 movi(Vd, T, (imm32 >> shift) & 0xff, shift);
1820 } else {
1821 movw(rscratch1, imm32);
1822 dup(Vd, T, rscratch1);
1823 }
1824 }
1825
1826 void MacroAssembler::mov_immediate64(Register dst, uint64_t imm64)
1827 {
1828 #ifndef PRODUCT
1829 {
1830 char buffer[64];
1831 snprintf(buffer, sizeof(buffer), "0x%" PRIX64, imm64);
1832 block_comment(buffer);
1833 }
1834 #endif
1835 if (operand_valid_for_logical_immediate(false, imm64)) {
1836 orr(dst, zr, imm64);
1837 } else {
1838 // we can use a combination of MOVZ or MOVN with
1839 // MOVK to build up the constant
1840 uint64_t imm_h[4];
1841 int zero_count = 0;
1842 int neg_count = 0;
1843 int i;
1844 for (i = 0; i < 4; i++) {
1845 imm_h[i] = ((imm64 >> (i * 16)) & 0xffffL);
1846 if (imm_h[i] == 0) {
1847 zero_count++;
1848 } else if (imm_h[i] == 0xffffL) {
1849 neg_count++;
1850 }
1851 }
1852 if (zero_count == 4) {
1853 // one MOVZ will do
1854 movz(dst, 0);
1855 } else if (neg_count == 4) {
1856 // one MOVN will do
1857 movn(dst, 0);
1858 } else if (zero_count == 3) {
1859 for (i = 0; i < 4; i++) {
1860 if (imm_h[i] != 0L) {
1861 movz(dst, (uint32_t)imm_h[i], (i << 4));
1862 break;
1863 }
1864 }
1865 } else if (neg_count == 3) {
1866 // one MOVN will do
1867 for (int i = 0; i < 4; i++) {
1868 if (imm_h[i] != 0xffffL) {
1869 movn(dst, (uint32_t)imm_h[i] ^ 0xffffL, (i << 4));
1870 break;
1871 }
1872 }
1873 } else if (zero_count == 2) {
1874 // one MOVZ and one MOVK will do
1875 for (i = 0; i < 3; i++) {
1876 if (imm_h[i] != 0L) {
1877 movz(dst, (uint32_t)imm_h[i], (i << 4));
1878 i++;
1879 break;
1880 }
1881 }
1882 for (;i < 4; i++) {
1883 if (imm_h[i] != 0L) {
1884 movk(dst, (uint32_t)imm_h[i], (i << 4));
1885 }
1886 }
1887 } else if (neg_count == 2) {
1888 // one MOVN and one MOVK will do
1889 for (i = 0; i < 4; i++) {
1890 if (imm_h[i] != 0xffffL) {
1891 movn(dst, (uint32_t)imm_h[i] ^ 0xffffL, (i << 4));
1892 i++;
1893 break;
1894 }
1895 }
1896 for (;i < 4; i++) {
1897 if (imm_h[i] != 0xffffL) {
1898 movk(dst, (uint32_t)imm_h[i], (i << 4));
1899 }
1900 }
1901 } else if (zero_count == 1) {
1902 // one MOVZ and two MOVKs will do
1903 for (i = 0; i < 4; i++) {
1904 if (imm_h[i] != 0L) {
1905 movz(dst, (uint32_t)imm_h[i], (i << 4));
1906 i++;
1907 break;
1908 }
1909 }
1910 for (;i < 4; i++) {
1911 if (imm_h[i] != 0x0L) {
1912 movk(dst, (uint32_t)imm_h[i], (i << 4));
1913 }
1914 }
1915 } else if (neg_count == 1) {
1916 // one MOVN and two MOVKs will do
1917 for (i = 0; i < 4; i++) {
1918 if (imm_h[i] != 0xffffL) {
1919 movn(dst, (uint32_t)imm_h[i] ^ 0xffffL, (i << 4));
1920 i++;
1921 break;
1922 }
1923 }
1924 for (;i < 4; i++) {
1925 if (imm_h[i] != 0xffffL) {
1926 movk(dst, (uint32_t)imm_h[i], (i << 4));
1927 }
1928 }
1929 } else {
1930 // use a MOVZ and 3 MOVKs (makes it easier to debug)
1931 movz(dst, (uint32_t)imm_h[0], 0);
1932 for (i = 1; i < 4; i++) {
1933 movk(dst, (uint32_t)imm_h[i], (i << 4));
1934 }
1935 }
1936 }
1937 }
1938
1939 void MacroAssembler::mov_immediate32(Register dst, uint32_t imm32)
1940 {
1941 #ifndef PRODUCT
1942 {
1943 char buffer[64];
1944 snprintf(buffer, sizeof(buffer), "0x%" PRIX32, imm32);
1945 block_comment(buffer);
1946 }
1947 #endif
1948 if (operand_valid_for_logical_immediate(true, imm32)) {
1949 orrw(dst, zr, imm32);
1950 } else {
1951 // we can use MOVZ, MOVN or two calls to MOVK to build up the
1952 // constant
1953 uint32_t imm_h[2];
1954 imm_h[0] = imm32 & 0xffff;
1955 imm_h[1] = ((imm32 >> 16) & 0xffff);
1956 if (imm_h[0] == 0) {
1957 movzw(dst, imm_h[1], 16);
1958 } else if (imm_h[0] == 0xffff) {
1959 movnw(dst, imm_h[1] ^ 0xffff, 16);
1960 } else if (imm_h[1] == 0) {
1961 movzw(dst, imm_h[0], 0);
1962 } else if (imm_h[1] == 0xffff) {
1963 movnw(dst, imm_h[0] ^ 0xffff, 0);
1964 } else {
1965 // use a MOVZ and MOVK (makes it easier to debug)
1966 movzw(dst, imm_h[0], 0);
1967 movkw(dst, imm_h[1], 16);
1968 }
1969 }
1970 }
1971
1972 // Form an address from base + offset in Rd. Rd may or may
1973 // not actually be used: you must use the Address that is returned.
1974 // It is up to you to ensure that the shift provided matches the size
1975 // of your data.
1976 Address MacroAssembler::form_address(Register Rd, Register base, int64_t byte_offset, int shift) {
1977 if (Address::offset_ok_for_immed(byte_offset, shift))
1978 // It fits; no need for any heroics
1979 return Address(base, byte_offset);
1980
1981 // Don't do anything clever with negative or misaligned offsets
1982 unsigned mask = (1 << shift) - 1;
1983 if (byte_offset < 0 || byte_offset & mask) {
1984 mov(Rd, byte_offset);
1985 add(Rd, base, Rd);
1986 return Address(Rd);
1987 }
1988
1989 // See if we can do this with two 12-bit offsets
1990 {
1991 uint64_t word_offset = byte_offset >> shift;
1992 uint64_t masked_offset = word_offset & 0xfff000;
1993 if (Address::offset_ok_for_immed(word_offset - masked_offset, 0)
1994 && Assembler::operand_valid_for_add_sub_immediate(masked_offset << shift)) {
1995 add(Rd, base, masked_offset << shift);
1996 word_offset -= masked_offset;
1997 return Address(Rd, word_offset << shift);
1998 }
1999 }
2000
2001 // Do it the hard way
2002 mov(Rd, byte_offset);
2003 add(Rd, base, Rd);
2004 return Address(Rd);
2005 }
2006
2007 int MacroAssembler::corrected_idivl(Register result, Register ra, Register rb,
2008 bool want_remainder, Register scratch)
2009 {
2010 // Full implementation of Java idiv and irem. The function
2011 // returns the (pc) offset of the div instruction - may be needed
2012 // for implicit exceptions.
2013 //
2014 // constraint : ra/rb =/= scratch
2015 // normal case
2016 //
2017 // input : ra: dividend
2018 // rb: divisor
2019 //
2020 // result: either
2021 // quotient (= ra idiv rb)
2022 // remainder (= ra irem rb)
2023
2024 assert(ra != scratch && rb != scratch, "reg cannot be scratch");
2025
2026 int idivl_offset = offset();
2027 if (! want_remainder) {
2028 sdivw(result, ra, rb);
2029 } else {
2030 sdivw(scratch, ra, rb);
2031 Assembler::msubw(result, scratch, rb, ra);
2032 }
2033
2034 return idivl_offset;
2035 }
2036
2037 int MacroAssembler::corrected_idivq(Register result, Register ra, Register rb,
2038 bool want_remainder, Register scratch)
2039 {
2040 // Full implementation of Java ldiv and lrem. The function
2041 // returns the (pc) offset of the div instruction - may be needed
2042 // for implicit exceptions.
2043 //
2044 // constraint : ra/rb =/= scratch
2045 // normal case
2046 //
2047 // input : ra: dividend
2048 // rb: divisor
2049 //
2050 // result: either
2051 // quotient (= ra idiv rb)
2052 // remainder (= ra irem rb)
2053
2054 assert(ra != scratch && rb != scratch, "reg cannot be scratch");
2055
2056 int idivq_offset = offset();
2057 if (! want_remainder) {
2058 sdiv(result, ra, rb);
2059 } else {
2060 sdiv(scratch, ra, rb);
2061 Assembler::msub(result, scratch, rb, ra);
2062 }
2063
2064 return idivq_offset;
2065 }
2066
2067 void MacroAssembler::membar(Membar_mask_bits order_constraint) {
2068 address prev = pc() - NativeMembar::instruction_size;
2069 address last = code()->last_insn();
2070 if (last != nullptr && nativeInstruction_at(last)->is_Membar() && prev == last) {
2071 NativeMembar *bar = NativeMembar_at(prev);
2072 // We are merging two memory barrier instructions. On AArch64 we
2073 // can do this simply by ORing them together.
2074 bar->set_kind(bar->get_kind() | order_constraint);
2075 BLOCK_COMMENT("merged membar");
2076 } else {
2077 code()->set_last_insn(pc());
2078 dmb(Assembler::barrier(order_constraint));
2079 }
2080 }
2081
2082 bool MacroAssembler::try_merge_ldst(Register rt, const Address &adr, size_t size_in_bytes, bool is_store) {
2083 if (ldst_can_merge(rt, adr, size_in_bytes, is_store)) {
2084 merge_ldst(rt, adr, size_in_bytes, is_store);
2085 code()->clear_last_insn();
2086 return true;
2087 } else {
2088 assert(size_in_bytes == 8 || size_in_bytes == 4, "only 8 bytes or 4 bytes load/store is supported.");
2089 const uint64_t mask = size_in_bytes - 1;
2090 if (adr.getMode() == Address::base_plus_offset &&
2091 (adr.offset() & mask) == 0) { // only supports base_plus_offset.
2092 code()->set_last_insn(pc());
2093 }
2094 return false;
2095 }
2096 }
2097
2098 void MacroAssembler::ldr(Register Rx, const Address &adr) {
2099 // We always try to merge two adjacent loads into one ldp.
2100 if (!try_merge_ldst(Rx, adr, 8, false)) {
2101 Assembler::ldr(Rx, adr);
2102 }
2103 }
2104
2105 void MacroAssembler::ldrw(Register Rw, const Address &adr) {
2106 // We always try to merge two adjacent loads into one ldp.
2107 if (!try_merge_ldst(Rw, adr, 4, false)) {
2108 Assembler::ldrw(Rw, adr);
2109 }
2110 }
2111
2112 void MacroAssembler::str(Register Rx, const Address &adr) {
2113 // We always try to merge two adjacent stores into one stp.
2114 if (!try_merge_ldst(Rx, adr, 8, true)) {
2115 Assembler::str(Rx, adr);
2116 }
2117 }
2118
2119 void MacroAssembler::strw(Register Rw, const Address &adr) {
2120 // We always try to merge two adjacent stores into one stp.
2121 if (!try_merge_ldst(Rw, adr, 4, true)) {
2122 Assembler::strw(Rw, adr);
2123 }
2124 }
2125
2126 // MacroAssembler routines found actually to be needed
2127
2128 void MacroAssembler::push(Register src)
2129 {
2130 str(src, Address(pre(esp, -1 * wordSize)));
2131 }
2132
2133 void MacroAssembler::pop(Register dst)
2134 {
2135 ldr(dst, Address(post(esp, 1 * wordSize)));
2136 }
2137
2138 // Note: load_unsigned_short used to be called load_unsigned_word.
2139 int MacroAssembler::load_unsigned_short(Register dst, Address src) {
2140 int off = offset();
2141 ldrh(dst, src);
2142 return off;
2143 }
2144
2145 int MacroAssembler::load_unsigned_byte(Register dst, Address src) {
2146 int off = offset();
2147 ldrb(dst, src);
2148 return off;
2149 }
2150
2151 int MacroAssembler::load_signed_short(Register dst, Address src) {
2152 int off = offset();
2153 ldrsh(dst, src);
2154 return off;
2155 }
2156
2157 int MacroAssembler::load_signed_byte(Register dst, Address src) {
2158 int off = offset();
2159 ldrsb(dst, src);
2160 return off;
2161 }
2162
2163 int MacroAssembler::load_signed_short32(Register dst, Address src) {
2164 int off = offset();
2165 ldrshw(dst, src);
2166 return off;
2167 }
2168
2169 int MacroAssembler::load_signed_byte32(Register dst, Address src) {
2170 int off = offset();
2171 ldrsbw(dst, src);
2172 return off;
2173 }
2174
2175 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed) {
2176 switch (size_in_bytes) {
2177 case 8: ldr(dst, src); break;
2178 case 4: ldrw(dst, src); break;
2179 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break;
2180 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break;
2181 default: ShouldNotReachHere();
2182 }
2183 }
2184
2185 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes) {
2186 switch (size_in_bytes) {
2187 case 8: str(src, dst); break;
2188 case 4: strw(src, dst); break;
2189 case 2: strh(src, dst); break;
2190 case 1: strb(src, dst); break;
2191 default: ShouldNotReachHere();
2192 }
2193 }
2194
2195 void MacroAssembler::decrementw(Register reg, int value)
2196 {
2197 if (value < 0) { incrementw(reg, -value); return; }
2198 if (value == 0) { return; }
2199 if (value < (1 << 12)) { subw(reg, reg, value); return; }
2200 /* else */ {
2201 guarantee(reg != rscratch2, "invalid dst for register decrement");
2202 movw(rscratch2, (unsigned)value);
2203 subw(reg, reg, rscratch2);
2204 }
2205 }
2206
2207 void MacroAssembler::decrement(Register reg, int value)
2208 {
2209 if (value < 0) { increment(reg, -value); return; }
2210 if (value == 0) { return; }
2211 if (value < (1 << 12)) { sub(reg, reg, value); return; }
2212 /* else */ {
2213 assert(reg != rscratch2, "invalid dst for register decrement");
2214 mov(rscratch2, (uint64_t)value);
2215 sub(reg, reg, rscratch2);
2216 }
2217 }
2218
2219 void MacroAssembler::decrementw(Address dst, int value)
2220 {
2221 assert(!dst.uses(rscratch1), "invalid dst for address decrement");
2222 if (dst.getMode() == Address::literal) {
2223 assert(abs(value) < (1 << 12), "invalid value and address mode combination");
2224 lea(rscratch2, dst);
2225 dst = Address(rscratch2);
2226 }
2227 ldrw(rscratch1, dst);
2228 decrementw(rscratch1, value);
2229 strw(rscratch1, dst);
2230 }
2231
2232 void MacroAssembler::decrement(Address dst, int value)
2233 {
2234 assert(!dst.uses(rscratch1), "invalid address for decrement");
2235 if (dst.getMode() == Address::literal) {
2236 assert(abs(value) < (1 << 12), "invalid value and address mode combination");
2237 lea(rscratch2, dst);
2238 dst = Address(rscratch2);
2239 }
2240 ldr(rscratch1, dst);
2241 decrement(rscratch1, value);
2242 str(rscratch1, dst);
2243 }
2244
2245 void MacroAssembler::incrementw(Register reg, int value)
2246 {
2247 if (value < 0) { decrementw(reg, -value); return; }
2248 if (value == 0) { return; }
2249 if (value < (1 << 12)) { addw(reg, reg, value); return; }
2250 /* else */ {
2251 assert(reg != rscratch2, "invalid dst for register increment");
2252 movw(rscratch2, (unsigned)value);
2253 addw(reg, reg, rscratch2);
2254 }
2255 }
2256
2257 void MacroAssembler::increment(Register reg, int value)
2258 {
2259 if (value < 0) { decrement(reg, -value); return; }
2260 if (value == 0) { return; }
2261 if (value < (1 << 12)) { add(reg, reg, value); return; }
2262 /* else */ {
2263 assert(reg != rscratch2, "invalid dst for register increment");
2264 movw(rscratch2, (unsigned)value);
2265 add(reg, reg, rscratch2);
2266 }
2267 }
2268
2269 void MacroAssembler::incrementw(Address dst, int value)
2270 {
2271 assert(!dst.uses(rscratch1), "invalid dst for address increment");
2272 if (dst.getMode() == Address::literal) {
2273 assert(abs(value) < (1 << 12), "invalid value and address mode combination");
2274 lea(rscratch2, dst);
2275 dst = Address(rscratch2);
2276 }
2277 ldrw(rscratch1, dst);
2278 incrementw(rscratch1, value);
2279 strw(rscratch1, dst);
2280 }
2281
2282 void MacroAssembler::increment(Address dst, int value)
2283 {
2284 assert(!dst.uses(rscratch1), "invalid dst for address increment");
2285 if (dst.getMode() == Address::literal) {
2286 assert(abs(value) < (1 << 12), "invalid value and address mode combination");
2287 lea(rscratch2, dst);
2288 dst = Address(rscratch2);
2289 }
2290 ldr(rscratch1, dst);
2291 increment(rscratch1, value);
2292 str(rscratch1, dst);
2293 }
2294
2295 // Push lots of registers in the bit set supplied. Don't push sp.
2296 // Return the number of words pushed
2297 int MacroAssembler::push(unsigned int bitset, Register stack) {
2298 int words_pushed = 0;
2299
2300 // Scan bitset to accumulate register pairs
2301 unsigned char regs[32];
2302 int count = 0;
2303 for (int reg = 0; reg <= 30; reg++) {
2304 if (1 & bitset)
2305 regs[count++] = reg;
2306 bitset >>= 1;
2307 }
2308 regs[count++] = zr->raw_encoding();
2309 count &= ~1; // Only push an even number of regs
2310
2311 if (count) {
2312 stp(as_Register(regs[0]), as_Register(regs[1]),
2313 Address(pre(stack, -count * wordSize)));
2314 words_pushed += 2;
2315 }
2316 for (int i = 2; i < count; i += 2) {
2317 stp(as_Register(regs[i]), as_Register(regs[i+1]),
2318 Address(stack, i * wordSize));
2319 words_pushed += 2;
2320 }
2321
2322 assert(words_pushed == count, "oops, pushed != count");
2323
2324 return count;
2325 }
2326
2327 int MacroAssembler::pop(unsigned int bitset, Register stack) {
2328 int words_pushed = 0;
2329
2330 // Scan bitset to accumulate register pairs
2331 unsigned char regs[32];
2332 int count = 0;
2333 for (int reg = 0; reg <= 30; reg++) {
2334 if (1 & bitset)
2335 regs[count++] = reg;
2336 bitset >>= 1;
2337 }
2338 regs[count++] = zr->raw_encoding();
2339 count &= ~1;
2340
2341 for (int i = 2; i < count; i += 2) {
2342 ldp(as_Register(regs[i]), as_Register(regs[i+1]),
2343 Address(stack, i * wordSize));
2344 words_pushed += 2;
2345 }
2346 if (count) {
2347 ldp(as_Register(regs[0]), as_Register(regs[1]),
2348 Address(post(stack, count * wordSize)));
2349 words_pushed += 2;
2350 }
2351
2352 assert(words_pushed == count, "oops, pushed != count");
2353
2354 return count;
2355 }
2356
2357 // Push lots of registers in the bit set supplied. Don't push sp.
2358 // Return the number of dwords pushed
2359 int MacroAssembler::push_fp(unsigned int bitset, Register stack) {
2360 int words_pushed = 0;
2361 bool use_sve = false;
2362 int sve_vector_size_in_bytes = 0;
2363
2364 #ifdef COMPILER2
2365 use_sve = Matcher::supports_scalable_vector();
2366 sve_vector_size_in_bytes = Matcher::scalable_vector_reg_size(T_BYTE);
2367 #endif
2368
2369 // Scan bitset to accumulate register pairs
2370 unsigned char regs[32];
2371 int count = 0;
2372 for (int reg = 0; reg <= 31; reg++) {
2373 if (1 & bitset)
2374 regs[count++] = reg;
2375 bitset >>= 1;
2376 }
2377
2378 if (count == 0) {
2379 return 0;
2380 }
2381
2382 // SVE
2383 if (use_sve && sve_vector_size_in_bytes > 16) {
2384 sub(stack, stack, sve_vector_size_in_bytes * count);
2385 for (int i = 0; i < count; i++) {
2386 sve_str(as_FloatRegister(regs[i]), Address(stack, i));
2387 }
2388 return count * sve_vector_size_in_bytes / 8;
2389 }
2390
2391 // NEON
2392 if (count == 1) {
2393 strq(as_FloatRegister(regs[0]), Address(pre(stack, -wordSize * 2)));
2394 return 2;
2395 }
2396
2397 bool odd = (count & 1) == 1;
2398 int push_slots = count + (odd ? 1 : 0);
2399
2400 // Always pushing full 128 bit registers.
2401 stpq(as_FloatRegister(regs[0]), as_FloatRegister(regs[1]), Address(pre(stack, -push_slots * wordSize * 2)));
2402 words_pushed += 2;
2403
2404 for (int i = 2; i + 1 < count; i += 2) {
2405 stpq(as_FloatRegister(regs[i]), as_FloatRegister(regs[i+1]), Address(stack, i * wordSize * 2));
2406 words_pushed += 2;
2407 }
2408
2409 if (odd) {
2410 strq(as_FloatRegister(regs[count - 1]), Address(stack, (count - 1) * wordSize * 2));
2411 words_pushed++;
2412 }
2413
2414 assert(words_pushed == count, "oops, pushed(%d) != count(%d)", words_pushed, count);
2415 return count * 2;
2416 }
2417
2418 // Return the number of dwords popped
2419 int MacroAssembler::pop_fp(unsigned int bitset, Register stack) {
2420 int words_pushed = 0;
2421 bool use_sve = false;
2422 int sve_vector_size_in_bytes = 0;
2423
2424 #ifdef COMPILER2
2425 use_sve = Matcher::supports_scalable_vector();
2426 sve_vector_size_in_bytes = Matcher::scalable_vector_reg_size(T_BYTE);
2427 #endif
2428 // Scan bitset to accumulate register pairs
2429 unsigned char regs[32];
2430 int count = 0;
2431 for (int reg = 0; reg <= 31; reg++) {
2432 if (1 & bitset)
2433 regs[count++] = reg;
2434 bitset >>= 1;
2435 }
2436
2437 if (count == 0) {
2438 return 0;
2439 }
2440
2441 // SVE
2442 if (use_sve && sve_vector_size_in_bytes > 16) {
2443 for (int i = count - 1; i >= 0; i--) {
2444 sve_ldr(as_FloatRegister(regs[i]), Address(stack, i));
2445 }
2446 add(stack, stack, sve_vector_size_in_bytes * count);
2447 return count * sve_vector_size_in_bytes / 8;
2448 }
2449
2450 // NEON
2451 if (count == 1) {
2452 ldrq(as_FloatRegister(regs[0]), Address(post(stack, wordSize * 2)));
2453 return 2;
2454 }
2455
2456 bool odd = (count & 1) == 1;
2457 int push_slots = count + (odd ? 1 : 0);
2458
2459 if (odd) {
2460 ldrq(as_FloatRegister(regs[count - 1]), Address(stack, (count - 1) * wordSize * 2));
2461 words_pushed++;
2462 }
2463
2464 for (int i = 2; i + 1 < count; i += 2) {
2465 ldpq(as_FloatRegister(regs[i]), as_FloatRegister(regs[i+1]), Address(stack, i * wordSize * 2));
2466 words_pushed += 2;
2467 }
2468
2469 ldpq(as_FloatRegister(regs[0]), as_FloatRegister(regs[1]), Address(post(stack, push_slots * wordSize * 2)));
2470 words_pushed += 2;
2471
2472 assert(words_pushed == count, "oops, pushed(%d) != count(%d)", words_pushed, count);
2473
2474 return count * 2;
2475 }
2476
2477 // Return the number of dwords pushed
2478 int MacroAssembler::push_p(unsigned int bitset, Register stack) {
2479 bool use_sve = false;
2480 int sve_predicate_size_in_slots = 0;
2481
2482 #ifdef COMPILER2
2483 use_sve = Matcher::supports_scalable_vector();
2484 if (use_sve) {
2485 sve_predicate_size_in_slots = Matcher::scalable_predicate_reg_slots();
2486 }
2487 #endif
2488
2489 if (!use_sve) {
2490 return 0;
2491 }
2492
2493 unsigned char regs[PRegister::number_of_registers];
2494 int count = 0;
2495 for (int reg = 0; reg < PRegister::number_of_registers; reg++) {
2496 if (1 & bitset)
2497 regs[count++] = reg;
2498 bitset >>= 1;
2499 }
2500
2501 if (count == 0) {
2502 return 0;
2503 }
2504
2505 int total_push_bytes = align_up(sve_predicate_size_in_slots *
2506 VMRegImpl::stack_slot_size * count, 16);
2507 sub(stack, stack, total_push_bytes);
2508 for (int i = 0; i < count; i++) {
2509 sve_str(as_PRegister(regs[i]), Address(stack, i));
2510 }
2511 return total_push_bytes / 8;
2512 }
2513
2514 // Return the number of dwords popped
2515 int MacroAssembler::pop_p(unsigned int bitset, Register stack) {
2516 bool use_sve = false;
2517 int sve_predicate_size_in_slots = 0;
2518
2519 #ifdef COMPILER2
2520 use_sve = Matcher::supports_scalable_vector();
2521 if (use_sve) {
2522 sve_predicate_size_in_slots = Matcher::scalable_predicate_reg_slots();
2523 }
2524 #endif
2525
2526 if (!use_sve) {
2527 return 0;
2528 }
2529
2530 unsigned char regs[PRegister::number_of_registers];
2531 int count = 0;
2532 for (int reg = 0; reg < PRegister::number_of_registers; reg++) {
2533 if (1 & bitset)
2534 regs[count++] = reg;
2535 bitset >>= 1;
2536 }
2537
2538 if (count == 0) {
2539 return 0;
2540 }
2541
2542 int total_pop_bytes = align_up(sve_predicate_size_in_slots *
2543 VMRegImpl::stack_slot_size * count, 16);
2544 for (int i = count - 1; i >= 0; i--) {
2545 sve_ldr(as_PRegister(regs[i]), Address(stack, i));
2546 }
2547 add(stack, stack, total_pop_bytes);
2548 return total_pop_bytes / 8;
2549 }
2550
2551 #ifdef ASSERT
2552 void MacroAssembler::verify_heapbase(const char* msg) {
2553 #if 0
2554 assert (UseCompressedOops || UseCompressedClassPointers, "should be compressed");
2555 assert (Universe::heap() != nullptr, "java heap should be initialized");
2556 if (!UseCompressedOops || Universe::ptr_base() == nullptr) {
2557 // rheapbase is allocated as general register
2558 return;
2559 }
2560 if (CheckCompressedOops) {
2561 Label ok;
2562 push(1 << rscratch1->encoding(), sp); // cmpptr trashes rscratch1
2563 cmpptr(rheapbase, ExternalAddress(CompressedOops::ptrs_base_addr()));
2564 br(Assembler::EQ, ok);
2565 stop(msg);
2566 bind(ok);
2567 pop(1 << rscratch1->encoding(), sp);
2568 }
2569 #endif
2570 }
2571 #endif
2572
2573 void MacroAssembler::resolve_jobject(Register value, Register tmp1, Register tmp2) {
2574 assert_different_registers(value, tmp1, tmp2);
2575 Label done, tagged, weak_tagged;
2576
2577 cbz(value, done); // Use null as-is.
2578 tst(value, JNIHandles::tag_mask); // Test for tag.
2579 br(Assembler::NE, tagged);
2580
2581 // Resolve local handle
2582 access_load_at(T_OBJECT, IN_NATIVE | AS_RAW, value, Address(value, 0), tmp1, tmp2);
2583 verify_oop(value);
2584 b(done);
2585
2586 bind(tagged);
2587 STATIC_ASSERT(JNIHandles::TypeTag::weak_global == 0b1);
2588 tbnz(value, 0, weak_tagged); // Test for weak tag.
2589
2590 // Resolve global handle
2591 access_load_at(T_OBJECT, IN_NATIVE, value, Address(value, -JNIHandles::TypeTag::global), tmp1, tmp2);
2592 verify_oop(value);
2593 b(done);
2594
2595 bind(weak_tagged);
2596 // Resolve jweak.
2597 access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF,
2598 value, Address(value, -JNIHandles::TypeTag::weak_global), tmp1, tmp2);
2599 verify_oop(value);
2600
2601 bind(done);
2602 }
2603
2604 void MacroAssembler::resolve_global_jobject(Register value, Register tmp1, Register tmp2) {
2605 assert_different_registers(value, tmp1, tmp2);
2606 Label done;
2607
2608 cbz(value, done); // Use null as-is.
2609
2610 #ifdef ASSERT
2611 {
2612 STATIC_ASSERT(JNIHandles::TypeTag::global == 0b10);
2613 Label valid_global_tag;
2614 tbnz(value, 1, valid_global_tag); // Test for global tag
2615 stop("non global jobject using resolve_global_jobject");
2616 bind(valid_global_tag);
2617 }
2618 #endif
2619
2620 // Resolve global handle
2621 access_load_at(T_OBJECT, IN_NATIVE, value, Address(value, -JNIHandles::TypeTag::global), tmp1, tmp2);
2622 verify_oop(value);
2623
2624 bind(done);
2625 }
2626
2627 void MacroAssembler::stop(const char* msg) {
2628 BLOCK_COMMENT(msg);
2629 dcps1(0xdeae);
2630 emit_int64((uintptr_t)msg);
2631 }
2632
2633 void MacroAssembler::unimplemented(const char* what) {
2634 const char* buf = nullptr;
2635 {
2636 ResourceMark rm;
2637 stringStream ss;
2638 ss.print("unimplemented: %s", what);
2639 buf = code_string(ss.as_string());
2640 }
2641 stop(buf);
2642 }
2643
2644 void MacroAssembler::_assert_asm(Assembler::Condition cc, const char* msg) {
2645 #ifdef ASSERT
2646 Label OK;
2647 br(cc, OK);
2648 stop(msg);
2649 bind(OK);
2650 #endif
2651 }
2652
2653 // If a constant does not fit in an immediate field, generate some
2654 // number of MOV instructions and then perform the operation.
2655 void MacroAssembler::wrap_add_sub_imm_insn(Register Rd, Register Rn, uint64_t imm,
2656 add_sub_imm_insn insn1,
2657 add_sub_reg_insn insn2,
2658 bool is32) {
2659 assert(Rd != zr, "Rd = zr and not setting flags?");
2660 bool fits = operand_valid_for_add_sub_immediate(is32 ? (int32_t)imm : imm);
2661 if (fits) {
2662 (this->*insn1)(Rd, Rn, imm);
2663 } else {
2664 if (uabs(imm) < (1 << 24)) {
2665 (this->*insn1)(Rd, Rn, imm & -(1 << 12));
2666 (this->*insn1)(Rd, Rd, imm & ((1 << 12)-1));
2667 } else {
2668 assert_different_registers(Rd, Rn);
2669 mov(Rd, imm);
2670 (this->*insn2)(Rd, Rn, Rd, LSL, 0);
2671 }
2672 }
2673 }
2674
2675 // Separate vsn which sets the flags. Optimisations are more restricted
2676 // because we must set the flags correctly.
2677 void MacroAssembler::wrap_adds_subs_imm_insn(Register Rd, Register Rn, uint64_t imm,
2678 add_sub_imm_insn insn1,
2679 add_sub_reg_insn insn2,
2680 bool is32) {
2681 bool fits = operand_valid_for_add_sub_immediate(is32 ? (int32_t)imm : imm);
2682 if (fits) {
2683 (this->*insn1)(Rd, Rn, imm);
2684 } else {
2685 assert_different_registers(Rd, Rn);
2686 assert(Rd != zr, "overflow in immediate operand");
2687 mov(Rd, imm);
2688 (this->*insn2)(Rd, Rn, Rd, LSL, 0);
2689 }
2690 }
2691
2692
2693 void MacroAssembler::add(Register Rd, Register Rn, RegisterOrConstant increment) {
2694 if (increment.is_register()) {
2695 add(Rd, Rn, increment.as_register());
2696 } else {
2697 add(Rd, Rn, increment.as_constant());
2698 }
2699 }
2700
2701 void MacroAssembler::addw(Register Rd, Register Rn, RegisterOrConstant increment) {
2702 if (increment.is_register()) {
2703 addw(Rd, Rn, increment.as_register());
2704 } else {
2705 addw(Rd, Rn, increment.as_constant());
2706 }
2707 }
2708
2709 void MacroAssembler::sub(Register Rd, Register Rn, RegisterOrConstant decrement) {
2710 if (decrement.is_register()) {
2711 sub(Rd, Rn, decrement.as_register());
2712 } else {
2713 sub(Rd, Rn, decrement.as_constant());
2714 }
2715 }
2716
2717 void MacroAssembler::subw(Register Rd, Register Rn, RegisterOrConstant decrement) {
2718 if (decrement.is_register()) {
2719 subw(Rd, Rn, decrement.as_register());
2720 } else {
2721 subw(Rd, Rn, decrement.as_constant());
2722 }
2723 }
2724
2725 void MacroAssembler::reinit_heapbase()
2726 {
2727 if (UseCompressedOops) {
2728 if (Universe::is_fully_initialized()) {
2729 mov(rheapbase, CompressedOops::ptrs_base());
2730 } else {
2731 lea(rheapbase, ExternalAddress(CompressedOops::ptrs_base_addr()));
2732 ldr(rheapbase, Address(rheapbase));
2733 }
2734 }
2735 }
2736
2737 // this simulates the behaviour of the x86 cmpxchg instruction using a
2738 // load linked/store conditional pair. we use the acquire/release
2739 // versions of these instructions so that we flush pending writes as
2740 // per Java semantics.
2741
2742 // n.b the x86 version assumes the old value to be compared against is
2743 // in rax and updates rax with the value located in memory if the
2744 // cmpxchg fails. we supply a register for the old value explicitly
2745
2746 // the aarch64 load linked/store conditional instructions do not
2747 // accept an offset. so, unlike x86, we must provide a plain register
2748 // to identify the memory word to be compared/exchanged rather than a
2749 // register+offset Address.
2750
2751 void MacroAssembler::cmpxchgptr(Register oldv, Register newv, Register addr, Register tmp,
2752 Label &succeed, Label *fail) {
2753 // oldv holds comparison value
2754 // newv holds value to write in exchange
2755 // addr identifies memory word to compare against/update
2756 if (UseLSE) {
2757 mov(tmp, oldv);
2758 casal(Assembler::xword, oldv, newv, addr);
2759 cmp(tmp, oldv);
2760 br(Assembler::EQ, succeed);
2761 membar(AnyAny);
2762 } else {
2763 Label retry_load, nope;
2764 prfm(Address(addr), PSTL1STRM);
2765 bind(retry_load);
2766 // flush and load exclusive from the memory location
2767 // and fail if it is not what we expect
2768 ldaxr(tmp, addr);
2769 cmp(tmp, oldv);
2770 br(Assembler::NE, nope);
2771 // if we store+flush with no intervening write tmp will be zero
2772 stlxr(tmp, newv, addr);
2773 cbzw(tmp, succeed);
2774 // retry so we only ever return after a load fails to compare
2775 // ensures we don't return a stale value after a failed write.
2776 b(retry_load);
2777 // if the memory word differs we return it in oldv and signal a fail
2778 bind(nope);
2779 membar(AnyAny);
2780 mov(oldv, tmp);
2781 }
2782 if (fail)
2783 b(*fail);
2784 }
2785
2786 void MacroAssembler::cmpxchg_obj_header(Register oldv, Register newv, Register obj, Register tmp,
2787 Label &succeed, Label *fail) {
2788 assert(oopDesc::mark_offset_in_bytes() == 0, "assumption");
2789 cmpxchgptr(oldv, newv, obj, tmp, succeed, fail);
2790 }
2791
2792 void MacroAssembler::cmpxchgw(Register oldv, Register newv, Register addr, Register tmp,
2793 Label &succeed, Label *fail) {
2794 // oldv holds comparison value
2795 // newv holds value to write in exchange
2796 // addr identifies memory word to compare against/update
2797 // tmp returns 0/1 for success/failure
2798 if (UseLSE) {
2799 mov(tmp, oldv);
2800 casal(Assembler::word, oldv, newv, addr);
2801 cmp(tmp, oldv);
2802 br(Assembler::EQ, succeed);
2803 membar(AnyAny);
2804 } else {
2805 Label retry_load, nope;
2806 prfm(Address(addr), PSTL1STRM);
2807 bind(retry_load);
2808 // flush and load exclusive from the memory location
2809 // and fail if it is not what we expect
2810 ldaxrw(tmp, addr);
2811 cmp(tmp, oldv);
2812 br(Assembler::NE, nope);
2813 // if we store+flush with no intervening write tmp will be zero
2814 stlxrw(tmp, newv, addr);
2815 cbzw(tmp, succeed);
2816 // retry so we only ever return after a load fails to compare
2817 // ensures we don't return a stale value after a failed write.
2818 b(retry_load);
2819 // if the memory word differs we return it in oldv and signal a fail
2820 bind(nope);
2821 membar(AnyAny);
2822 mov(oldv, tmp);
2823 }
2824 if (fail)
2825 b(*fail);
2826 }
2827
2828 // A generic CAS; success or failure is in the EQ flag. A weak CAS
2829 // doesn't retry and may fail spuriously. If the oldval is wanted,
2830 // Pass a register for the result, otherwise pass noreg.
2831
2832 // Clobbers rscratch1
2833 void MacroAssembler::cmpxchg(Register addr, Register expected,
2834 Register new_val,
2835 enum operand_size size,
2836 bool acquire, bool release,
2837 bool weak,
2838 Register result) {
2839 if (result == noreg) result = rscratch1;
2840 BLOCK_COMMENT("cmpxchg {");
2841 if (UseLSE) {
2842 mov(result, expected);
2843 lse_cas(result, new_val, addr, size, acquire, release, /*not_pair*/ true);
2844 compare_eq(result, expected, size);
2845 #ifdef ASSERT
2846 // Poison rscratch1 which is written on !UseLSE branch
2847 mov(rscratch1, 0x1f1f1f1f1f1f1f1f);
2848 #endif
2849 } else {
2850 Label retry_load, done;
2851 prfm(Address(addr), PSTL1STRM);
2852 bind(retry_load);
2853 load_exclusive(result, addr, size, acquire);
2854 compare_eq(result, expected, size);
2855 br(Assembler::NE, done);
2856 store_exclusive(rscratch1, new_val, addr, size, release);
2857 if (weak) {
2858 cmpw(rscratch1, 0u); // If the store fails, return NE to our caller.
2859 } else {
2860 cbnzw(rscratch1, retry_load);
2861 }
2862 bind(done);
2863 }
2864 BLOCK_COMMENT("} cmpxchg");
2865 }
2866
2867 // A generic comparison. Only compares for equality, clobbers rscratch1.
2868 void MacroAssembler::compare_eq(Register rm, Register rn, enum operand_size size) {
2869 if (size == xword) {
2870 cmp(rm, rn);
2871 } else if (size == word) {
2872 cmpw(rm, rn);
2873 } else if (size == halfword) {
2874 eorw(rscratch1, rm, rn);
2875 ands(zr, rscratch1, 0xffff);
2876 } else if (size == byte) {
2877 eorw(rscratch1, rm, rn);
2878 ands(zr, rscratch1, 0xff);
2879 } else {
2880 ShouldNotReachHere();
2881 }
2882 }
2883
2884
2885 static bool different(Register a, RegisterOrConstant b, Register c) {
2886 if (b.is_constant())
2887 return a != c;
2888 else
2889 return a != b.as_register() && a != c && b.as_register() != c;
2890 }
2891
2892 #define ATOMIC_OP(NAME, LDXR, OP, IOP, AOP, STXR, sz) \
2893 void MacroAssembler::atomic_##NAME(Register prev, RegisterOrConstant incr, Register addr) { \
2894 if (UseLSE) { \
2895 prev = prev->is_valid() ? prev : zr; \
2896 if (incr.is_register()) { \
2897 AOP(sz, incr.as_register(), prev, addr); \
2898 } else { \
2899 mov(rscratch2, incr.as_constant()); \
2900 AOP(sz, rscratch2, prev, addr); \
2901 } \
2902 return; \
2903 } \
2904 Register result = rscratch2; \
2905 if (prev->is_valid()) \
2906 result = different(prev, incr, addr) ? prev : rscratch2; \
2907 \
2908 Label retry_load; \
2909 prfm(Address(addr), PSTL1STRM); \
2910 bind(retry_load); \
2911 LDXR(result, addr); \
2912 OP(rscratch1, result, incr); \
2913 STXR(rscratch2, rscratch1, addr); \
2914 cbnzw(rscratch2, retry_load); \
2915 if (prev->is_valid() && prev != result) { \
2916 IOP(prev, rscratch1, incr); \
2917 } \
2918 }
2919
2920 ATOMIC_OP(add, ldxr, add, sub, ldadd, stxr, Assembler::xword)
2921 ATOMIC_OP(addw, ldxrw, addw, subw, ldadd, stxrw, Assembler::word)
2922 ATOMIC_OP(addal, ldaxr, add, sub, ldaddal, stlxr, Assembler::xword)
2923 ATOMIC_OP(addalw, ldaxrw, addw, subw, ldaddal, stlxrw, Assembler::word)
2924
2925 #undef ATOMIC_OP
2926
2927 #define ATOMIC_XCHG(OP, AOP, LDXR, STXR, sz) \
2928 void MacroAssembler::atomic_##OP(Register prev, Register newv, Register addr) { \
2929 if (UseLSE) { \
2930 prev = prev->is_valid() ? prev : zr; \
2931 AOP(sz, newv, prev, addr); \
2932 return; \
2933 } \
2934 Register result = rscratch2; \
2935 if (prev->is_valid()) \
2936 result = different(prev, newv, addr) ? prev : rscratch2; \
2937 \
2938 Label retry_load; \
2939 prfm(Address(addr), PSTL1STRM); \
2940 bind(retry_load); \
2941 LDXR(result, addr); \
2942 STXR(rscratch1, newv, addr); \
2943 cbnzw(rscratch1, retry_load); \
2944 if (prev->is_valid() && prev != result) \
2945 mov(prev, result); \
2946 }
2947
2948 ATOMIC_XCHG(xchg, swp, ldxr, stxr, Assembler::xword)
2949 ATOMIC_XCHG(xchgw, swp, ldxrw, stxrw, Assembler::word)
2950 ATOMIC_XCHG(xchgl, swpl, ldxr, stlxr, Assembler::xword)
2951 ATOMIC_XCHG(xchglw, swpl, ldxrw, stlxrw, Assembler::word)
2952 ATOMIC_XCHG(xchgal, swpal, ldaxr, stlxr, Assembler::xword)
2953 ATOMIC_XCHG(xchgalw, swpal, ldaxrw, stlxrw, Assembler::word)
2954
2955 #undef ATOMIC_XCHG
2956
2957 #ifndef PRODUCT
2958 extern "C" void findpc(intptr_t x);
2959 #endif
2960
2961 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[])
2962 {
2963 // In order to get locks to work, we need to fake a in_VM state
2964 if (ShowMessageBoxOnError ) {
2965 JavaThread* thread = JavaThread::current();
2966 JavaThreadState saved_state = thread->thread_state();
2967 thread->set_thread_state(_thread_in_vm);
2968 #ifndef PRODUCT
2969 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
2970 ttyLocker ttyl;
2971 BytecodeCounter::print();
2972 }
2973 #endif
2974 if (os::message_box(msg, "Execution stopped, print registers?")) {
2975 ttyLocker ttyl;
2976 tty->print_cr(" pc = 0x%016" PRIx64, pc);
2977 #ifndef PRODUCT
2978 tty->cr();
2979 findpc(pc);
2980 tty->cr();
2981 #endif
2982 tty->print_cr(" r0 = 0x%016" PRIx64, regs[0]);
2983 tty->print_cr(" r1 = 0x%016" PRIx64, regs[1]);
2984 tty->print_cr(" r2 = 0x%016" PRIx64, regs[2]);
2985 tty->print_cr(" r3 = 0x%016" PRIx64, regs[3]);
2986 tty->print_cr(" r4 = 0x%016" PRIx64, regs[4]);
2987 tty->print_cr(" r5 = 0x%016" PRIx64, regs[5]);
2988 tty->print_cr(" r6 = 0x%016" PRIx64, regs[6]);
2989 tty->print_cr(" r7 = 0x%016" PRIx64, regs[7]);
2990 tty->print_cr(" r8 = 0x%016" PRIx64, regs[8]);
2991 tty->print_cr(" r9 = 0x%016" PRIx64, regs[9]);
2992 tty->print_cr("r10 = 0x%016" PRIx64, regs[10]);
2993 tty->print_cr("r11 = 0x%016" PRIx64, regs[11]);
2994 tty->print_cr("r12 = 0x%016" PRIx64, regs[12]);
2995 tty->print_cr("r13 = 0x%016" PRIx64, regs[13]);
2996 tty->print_cr("r14 = 0x%016" PRIx64, regs[14]);
2997 tty->print_cr("r15 = 0x%016" PRIx64, regs[15]);
2998 tty->print_cr("r16 = 0x%016" PRIx64, regs[16]);
2999 tty->print_cr("r17 = 0x%016" PRIx64, regs[17]);
3000 tty->print_cr("r18 = 0x%016" PRIx64, regs[18]);
3001 tty->print_cr("r19 = 0x%016" PRIx64, regs[19]);
3002 tty->print_cr("r20 = 0x%016" PRIx64, regs[20]);
3003 tty->print_cr("r21 = 0x%016" PRIx64, regs[21]);
3004 tty->print_cr("r22 = 0x%016" PRIx64, regs[22]);
3005 tty->print_cr("r23 = 0x%016" PRIx64, regs[23]);
3006 tty->print_cr("r24 = 0x%016" PRIx64, regs[24]);
3007 tty->print_cr("r25 = 0x%016" PRIx64, regs[25]);
3008 tty->print_cr("r26 = 0x%016" PRIx64, regs[26]);
3009 tty->print_cr("r27 = 0x%016" PRIx64, regs[27]);
3010 tty->print_cr("r28 = 0x%016" PRIx64, regs[28]);
3011 tty->print_cr("r30 = 0x%016" PRIx64, regs[30]);
3012 tty->print_cr("r31 = 0x%016" PRIx64, regs[31]);
3013 BREAKPOINT;
3014 }
3015 }
3016 fatal("DEBUG MESSAGE: %s", msg);
3017 }
3018
3019 RegSet MacroAssembler::call_clobbered_gp_registers() {
3020 RegSet regs = RegSet::range(r0, r17) - RegSet::of(rscratch1, rscratch2);
3021 #ifndef R18_RESERVED
3022 regs += r18_tls;
3023 #endif
3024 return regs;
3025 }
3026
3027 void MacroAssembler::push_call_clobbered_registers_except(RegSet exclude) {
3028 int step = 4 * wordSize;
3029 push(call_clobbered_gp_registers() - exclude, sp);
3030 sub(sp, sp, step);
3031 mov(rscratch1, -step);
3032 // Push v0-v7, v16-v31.
3033 for (int i = 31; i>= 4; i -= 4) {
3034 if (i <= v7->encoding() || i >= v16->encoding())
3035 st1(as_FloatRegister(i-3), as_FloatRegister(i-2), as_FloatRegister(i-1),
3036 as_FloatRegister(i), T1D, Address(post(sp, rscratch1)));
3037 }
3038 st1(as_FloatRegister(0), as_FloatRegister(1), as_FloatRegister(2),
3039 as_FloatRegister(3), T1D, Address(sp));
3040 }
3041
3042 void MacroAssembler::pop_call_clobbered_registers_except(RegSet exclude) {
3043 for (int i = 0; i < 32; i += 4) {
3044 if (i <= v7->encoding() || i >= v16->encoding())
3045 ld1(as_FloatRegister(i), as_FloatRegister(i+1), as_FloatRegister(i+2),
3046 as_FloatRegister(i+3), T1D, Address(post(sp, 4 * wordSize)));
3047 }
3048
3049 reinitialize_ptrue();
3050
3051 pop(call_clobbered_gp_registers() - exclude, sp);
3052 }
3053
3054 void MacroAssembler::push_CPU_state(bool save_vectors, bool use_sve,
3055 int sve_vector_size_in_bytes, int total_predicate_in_bytes) {
3056 push(RegSet::range(r0, r29), sp); // integer registers except lr & sp
3057 if (save_vectors && use_sve && sve_vector_size_in_bytes > 16) {
3058 sub(sp, sp, sve_vector_size_in_bytes * FloatRegister::number_of_registers);
3059 for (int i = 0; i < FloatRegister::number_of_registers; i++) {
3060 sve_str(as_FloatRegister(i), Address(sp, i));
3061 }
3062 } else {
3063 int step = (save_vectors ? 8 : 4) * wordSize;
3064 mov(rscratch1, -step);
3065 sub(sp, sp, step);
3066 for (int i = 28; i >= 4; i -= 4) {
3067 st1(as_FloatRegister(i), as_FloatRegister(i+1), as_FloatRegister(i+2),
3068 as_FloatRegister(i+3), save_vectors ? T2D : T1D, Address(post(sp, rscratch1)));
3069 }
3070 st1(v0, v1, v2, v3, save_vectors ? T2D : T1D, sp);
3071 }
3072 if (save_vectors && use_sve && total_predicate_in_bytes > 0) {
3073 sub(sp, sp, total_predicate_in_bytes);
3074 for (int i = 0; i < PRegister::number_of_registers; i++) {
3075 sve_str(as_PRegister(i), Address(sp, i));
3076 }
3077 }
3078 }
3079
3080 void MacroAssembler::pop_CPU_state(bool restore_vectors, bool use_sve,
3081 int sve_vector_size_in_bytes, int total_predicate_in_bytes) {
3082 if (restore_vectors && use_sve && total_predicate_in_bytes > 0) {
3083 for (int i = PRegister::number_of_registers - 1; i >= 0; i--) {
3084 sve_ldr(as_PRegister(i), Address(sp, i));
3085 }
3086 add(sp, sp, total_predicate_in_bytes);
3087 }
3088 if (restore_vectors && use_sve && sve_vector_size_in_bytes > 16) {
3089 for (int i = FloatRegister::number_of_registers - 1; i >= 0; i--) {
3090 sve_ldr(as_FloatRegister(i), Address(sp, i));
3091 }
3092 add(sp, sp, sve_vector_size_in_bytes * FloatRegister::number_of_registers);
3093 } else {
3094 int step = (restore_vectors ? 8 : 4) * wordSize;
3095 for (int i = 0; i <= 28; i += 4)
3096 ld1(as_FloatRegister(i), as_FloatRegister(i+1), as_FloatRegister(i+2),
3097 as_FloatRegister(i+3), restore_vectors ? T2D : T1D, Address(post(sp, step)));
3098 }
3099
3100 // We may use predicate registers and rely on ptrue with SVE,
3101 // regardless of wide vector (> 8 bytes) used or not.
3102 if (use_sve) {
3103 reinitialize_ptrue();
3104 }
3105
3106 // integer registers except lr & sp
3107 pop(RegSet::range(r0, r17), sp);
3108 #ifdef R18_RESERVED
3109 ldp(zr, r19, Address(post(sp, 2 * wordSize)));
3110 pop(RegSet::range(r20, r29), sp);
3111 #else
3112 pop(RegSet::range(r18_tls, r29), sp);
3113 #endif
3114 }
3115
3116 /**
3117 * Helpers for multiply_to_len().
3118 */
3119 void MacroAssembler::add2_with_carry(Register final_dest_hi, Register dest_hi, Register dest_lo,
3120 Register src1, Register src2) {
3121 adds(dest_lo, dest_lo, src1);
3122 adc(dest_hi, dest_hi, zr);
3123 adds(dest_lo, dest_lo, src2);
3124 adc(final_dest_hi, dest_hi, zr);
3125 }
3126
3127 // Generate an address from (r + r1 extend offset). "size" is the
3128 // size of the operand. The result may be in rscratch2.
3129 Address MacroAssembler::offsetted_address(Register r, Register r1,
3130 Address::extend ext, int offset, int size) {
3131 if (offset || (ext.shift() % size != 0)) {
3132 lea(rscratch2, Address(r, r1, ext));
3133 return Address(rscratch2, offset);
3134 } else {
3135 return Address(r, r1, ext);
3136 }
3137 }
3138
3139 Address MacroAssembler::spill_address(int size, int offset, Register tmp)
3140 {
3141 assert(offset >= 0, "spill to negative address?");
3142 // Offset reachable ?
3143 // Not aligned - 9 bits signed offset
3144 // Aligned - 12 bits unsigned offset shifted
3145 Register base = sp;
3146 if ((offset & (size-1)) && offset >= (1<<8)) {
3147 add(tmp, base, offset & ((1<<12)-1));
3148 base = tmp;
3149 offset &= -1u<<12;
3150 }
3151
3152 if (offset >= (1<<12) * size) {
3153 add(tmp, base, offset & (((1<<12)-1)<<12));
3154 base = tmp;
3155 offset &= ~(((1<<12)-1)<<12);
3156 }
3157
3158 return Address(base, offset);
3159 }
3160
3161 Address MacroAssembler::sve_spill_address(int sve_reg_size_in_bytes, int offset, Register tmp) {
3162 assert(offset >= 0, "spill to negative address?");
3163
3164 Register base = sp;
3165
3166 // An immediate offset in the range 0 to 255 which is multiplied
3167 // by the current vector or predicate register size in bytes.
3168 if (offset % sve_reg_size_in_bytes == 0 && offset < ((1<<8)*sve_reg_size_in_bytes)) {
3169 return Address(base, offset / sve_reg_size_in_bytes);
3170 }
3171
3172 add(tmp, base, offset);
3173 return Address(tmp);
3174 }
3175
3176 // Checks whether offset is aligned.
3177 // Returns true if it is, else false.
3178 bool MacroAssembler::merge_alignment_check(Register base,
3179 size_t size,
3180 int64_t cur_offset,
3181 int64_t prev_offset) const {
3182 if (AvoidUnalignedAccesses) {
3183 if (base == sp) {
3184 // Checks whether low offset if aligned to pair of registers.
3185 int64_t pair_mask = size * 2 - 1;
3186 int64_t offset = prev_offset > cur_offset ? cur_offset : prev_offset;
3187 return (offset & pair_mask) == 0;
3188 } else { // If base is not sp, we can't guarantee the access is aligned.
3189 return false;
3190 }
3191 } else {
3192 int64_t mask = size - 1;
3193 // Load/store pair instruction only supports element size aligned offset.
3194 return (cur_offset & mask) == 0 && (prev_offset & mask) == 0;
3195 }
3196 }
3197
3198 // Checks whether current and previous loads/stores can be merged.
3199 // Returns true if it can be merged, else false.
3200 bool MacroAssembler::ldst_can_merge(Register rt,
3201 const Address &adr,
3202 size_t cur_size_in_bytes,
3203 bool is_store) const {
3204 address prev = pc() - NativeInstruction::instruction_size;
3205 address last = code()->last_insn();
3206
3207 if (last == nullptr || !nativeInstruction_at(last)->is_Imm_LdSt()) {
3208 return false;
3209 }
3210
3211 if (adr.getMode() != Address::base_plus_offset || prev != last) {
3212 return false;
3213 }
3214
3215 NativeLdSt* prev_ldst = NativeLdSt_at(prev);
3216 size_t prev_size_in_bytes = prev_ldst->size_in_bytes();
3217
3218 assert(prev_size_in_bytes == 4 || prev_size_in_bytes == 8, "only supports 64/32bit merging.");
3219 assert(cur_size_in_bytes == 4 || cur_size_in_bytes == 8, "only supports 64/32bit merging.");
3220
3221 if (cur_size_in_bytes != prev_size_in_bytes || is_store != prev_ldst->is_store()) {
3222 return false;
3223 }
3224
3225 int64_t max_offset = 63 * prev_size_in_bytes;
3226 int64_t min_offset = -64 * prev_size_in_bytes;
3227
3228 assert(prev_ldst->is_not_pre_post_index(), "pre-index or post-index is not supported to be merged.");
3229
3230 // Only same base can be merged.
3231 if (adr.base() != prev_ldst->base()) {
3232 return false;
3233 }
3234
3235 int64_t cur_offset = adr.offset();
3236 int64_t prev_offset = prev_ldst->offset();
3237 size_t diff = abs(cur_offset - prev_offset);
3238 if (diff != prev_size_in_bytes) {
3239 return false;
3240 }
3241
3242 // Following cases can not be merged:
3243 // ldr x2, [x2, #8]
3244 // ldr x3, [x2, #16]
3245 // or:
3246 // ldr x2, [x3, #8]
3247 // ldr x2, [x3, #16]
3248 // If t1 and t2 is the same in "ldp t1, t2, [xn, #imm]", we'll get SIGILL.
3249 if (!is_store && (adr.base() == prev_ldst->target() || rt == prev_ldst->target())) {
3250 return false;
3251 }
3252
3253 int64_t low_offset = prev_offset > cur_offset ? cur_offset : prev_offset;
3254 // Offset range must be in ldp/stp instruction's range.
3255 if (low_offset > max_offset || low_offset < min_offset) {
3256 return false;
3257 }
3258
3259 if (merge_alignment_check(adr.base(), prev_size_in_bytes, cur_offset, prev_offset)) {
3260 return true;
3261 }
3262
3263 return false;
3264 }
3265
3266 // Merge current load/store with previous load/store into ldp/stp.
3267 void MacroAssembler::merge_ldst(Register rt,
3268 const Address &adr,
3269 size_t cur_size_in_bytes,
3270 bool is_store) {
3271
3272 assert(ldst_can_merge(rt, adr, cur_size_in_bytes, is_store) == true, "cur and prev must be able to be merged.");
3273
3274 Register rt_low, rt_high;
3275 address prev = pc() - NativeInstruction::instruction_size;
3276 NativeLdSt* prev_ldst = NativeLdSt_at(prev);
3277
3278 int64_t offset;
3279
3280 if (adr.offset() < prev_ldst->offset()) {
3281 offset = adr.offset();
3282 rt_low = rt;
3283 rt_high = prev_ldst->target();
3284 } else {
3285 offset = prev_ldst->offset();
3286 rt_low = prev_ldst->target();
3287 rt_high = rt;
3288 }
3289
3290 Address adr_p = Address(prev_ldst->base(), offset);
3291 // Overwrite previous generated binary.
3292 code_section()->set_end(prev);
3293
3294 const size_t sz = prev_ldst->size_in_bytes();
3295 assert(sz == 8 || sz == 4, "only supports 64/32bit merging.");
3296 if (!is_store) {
3297 BLOCK_COMMENT("merged ldr pair");
3298 if (sz == 8) {
3299 ldp(rt_low, rt_high, adr_p);
3300 } else {
3301 ldpw(rt_low, rt_high, adr_p);
3302 }
3303 } else {
3304 BLOCK_COMMENT("merged str pair");
3305 if (sz == 8) {
3306 stp(rt_low, rt_high, adr_p);
3307 } else {
3308 stpw(rt_low, rt_high, adr_p);
3309 }
3310 }
3311 }
3312
3313 /**
3314 * Multiply 64 bit by 64 bit first loop.
3315 */
3316 void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
3317 Register y, Register y_idx, Register z,
3318 Register carry, Register product,
3319 Register idx, Register kdx) {
3320 //
3321 // jlong carry, x[], y[], z[];
3322 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
3323 // huge_128 product = y[idx] * x[xstart] + carry;
3324 // z[kdx] = (jlong)product;
3325 // carry = (jlong)(product >>> 64);
3326 // }
3327 // z[xstart] = carry;
3328 //
3329
3330 Label L_first_loop, L_first_loop_exit;
3331 Label L_one_x, L_one_y, L_multiply;
3332
3333 subsw(xstart, xstart, 1);
3334 br(Assembler::MI, L_one_x);
3335
3336 lea(rscratch1, Address(x, xstart, Address::lsl(LogBytesPerInt)));
3337 ldr(x_xstart, Address(rscratch1));
3338 ror(x_xstart, x_xstart, 32); // convert big-endian to little-endian
3339
3340 bind(L_first_loop);
3341 subsw(idx, idx, 1);
3342 br(Assembler::MI, L_first_loop_exit);
3343 subsw(idx, idx, 1);
3344 br(Assembler::MI, L_one_y);
3345 lea(rscratch1, Address(y, idx, Address::uxtw(LogBytesPerInt)));
3346 ldr(y_idx, Address(rscratch1));
3347 ror(y_idx, y_idx, 32); // convert big-endian to little-endian
3348 bind(L_multiply);
3349
3350 // AArch64 has a multiply-accumulate instruction that we can't use
3351 // here because it has no way to process carries, so we have to use
3352 // separate add and adc instructions. Bah.
3353 umulh(rscratch1, x_xstart, y_idx); // x_xstart * y_idx -> rscratch1:product
3354 mul(product, x_xstart, y_idx);
3355 adds(product, product, carry);
3356 adc(carry, rscratch1, zr); // x_xstart * y_idx + carry -> carry:product
3357
3358 subw(kdx, kdx, 2);
3359 ror(product, product, 32); // back to big-endian
3360 str(product, offsetted_address(z, kdx, Address::uxtw(LogBytesPerInt), 0, BytesPerLong));
3361
3362 b(L_first_loop);
3363
3364 bind(L_one_y);
3365 ldrw(y_idx, Address(y, 0));
3366 b(L_multiply);
3367
3368 bind(L_one_x);
3369 ldrw(x_xstart, Address(x, 0));
3370 b(L_first_loop);
3371
3372 bind(L_first_loop_exit);
3373 }
3374
3375 /**
3376 * Multiply 128 bit by 128. Unrolled inner loop.
3377 *
3378 */
3379 void MacroAssembler::multiply_128_x_128_loop(Register y, Register z,
3380 Register carry, Register carry2,
3381 Register idx, Register jdx,
3382 Register yz_idx1, Register yz_idx2,
3383 Register tmp, Register tmp3, Register tmp4,
3384 Register tmp6, Register product_hi) {
3385
3386 // jlong carry, x[], y[], z[];
3387 // int kdx = ystart+1;
3388 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
3389 // huge_128 tmp3 = (y[idx+1] * product_hi) + z[kdx+idx+1] + carry;
3390 // jlong carry2 = (jlong)(tmp3 >>> 64);
3391 // huge_128 tmp4 = (y[idx] * product_hi) + z[kdx+idx] + carry2;
3392 // carry = (jlong)(tmp4 >>> 64);
3393 // z[kdx+idx+1] = (jlong)tmp3;
3394 // z[kdx+idx] = (jlong)tmp4;
3395 // }
3396 // idx += 2;
3397 // if (idx > 0) {
3398 // yz_idx1 = (y[idx] * product_hi) + z[kdx+idx] + carry;
3399 // z[kdx+idx] = (jlong)yz_idx1;
3400 // carry = (jlong)(yz_idx1 >>> 64);
3401 // }
3402 //
3403
3404 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
3405
3406 lsrw(jdx, idx, 2);
3407
3408 bind(L_third_loop);
3409
3410 subsw(jdx, jdx, 1);
3411 br(Assembler::MI, L_third_loop_exit);
3412 subw(idx, idx, 4);
3413
3414 lea(rscratch1, Address(y, idx, Address::uxtw(LogBytesPerInt)));
3415
3416 ldp(yz_idx2, yz_idx1, Address(rscratch1, 0));
3417
3418 lea(tmp6, Address(z, idx, Address::uxtw(LogBytesPerInt)));
3419
3420 ror(yz_idx1, yz_idx1, 32); // convert big-endian to little-endian
3421 ror(yz_idx2, yz_idx2, 32);
3422
3423 ldp(rscratch2, rscratch1, Address(tmp6, 0));
3424
3425 mul(tmp3, product_hi, yz_idx1); // yz_idx1 * product_hi -> tmp4:tmp3
3426 umulh(tmp4, product_hi, yz_idx1);
3427
3428 ror(rscratch1, rscratch1, 32); // convert big-endian to little-endian
3429 ror(rscratch2, rscratch2, 32);
3430
3431 mul(tmp, product_hi, yz_idx2); // yz_idx2 * product_hi -> carry2:tmp
3432 umulh(carry2, product_hi, yz_idx2);
3433
3434 // propagate sum of both multiplications into carry:tmp4:tmp3
3435 adds(tmp3, tmp3, carry);
3436 adc(tmp4, tmp4, zr);
3437 adds(tmp3, tmp3, rscratch1);
3438 adcs(tmp4, tmp4, tmp);
3439 adc(carry, carry2, zr);
3440 adds(tmp4, tmp4, rscratch2);
3441 adc(carry, carry, zr);
3442
3443 ror(tmp3, tmp3, 32); // convert little-endian to big-endian
3444 ror(tmp4, tmp4, 32);
3445 stp(tmp4, tmp3, Address(tmp6, 0));
3446
3447 b(L_third_loop);
3448 bind (L_third_loop_exit);
3449
3450 andw (idx, idx, 0x3);
3451 cbz(idx, L_post_third_loop_done);
3452
3453 Label L_check_1;
3454 subsw(idx, idx, 2);
3455 br(Assembler::MI, L_check_1);
3456
3457 lea(rscratch1, Address(y, idx, Address::uxtw(LogBytesPerInt)));
3458 ldr(yz_idx1, Address(rscratch1, 0));
3459 ror(yz_idx1, yz_idx1, 32);
3460 mul(tmp3, product_hi, yz_idx1); // yz_idx1 * product_hi -> tmp4:tmp3
3461 umulh(tmp4, product_hi, yz_idx1);
3462 lea(rscratch1, Address(z, idx, Address::uxtw(LogBytesPerInt)));
3463 ldr(yz_idx2, Address(rscratch1, 0));
3464 ror(yz_idx2, yz_idx2, 32);
3465
3466 add2_with_carry(carry, tmp4, tmp3, carry, yz_idx2);
3467
3468 ror(tmp3, tmp3, 32);
3469 str(tmp3, Address(rscratch1, 0));
3470
3471 bind (L_check_1);
3472
3473 andw (idx, idx, 0x1);
3474 subsw(idx, idx, 1);
3475 br(Assembler::MI, L_post_third_loop_done);
3476 ldrw(tmp4, Address(y, idx, Address::uxtw(LogBytesPerInt)));
3477 mul(tmp3, tmp4, product_hi); // tmp4 * product_hi -> carry2:tmp3
3478 umulh(carry2, tmp4, product_hi);
3479 ldrw(tmp4, Address(z, idx, Address::uxtw(LogBytesPerInt)));
3480
3481 add2_with_carry(carry2, tmp3, tmp4, carry);
3482
3483 strw(tmp3, Address(z, idx, Address::uxtw(LogBytesPerInt)));
3484 extr(carry, carry2, tmp3, 32);
3485
3486 bind(L_post_third_loop_done);
3487 }
3488
3489 /**
3490 * Code for BigInteger::multiplyToLen() intrinsic.
3491 *
3492 * r0: x
3493 * r1: xlen
3494 * r2: y
3495 * r3: ylen
3496 * r4: z
3497 * r5: zlen
3498 * r10: tmp1
3499 * r11: tmp2
3500 * r12: tmp3
3501 * r13: tmp4
3502 * r14: tmp5
3503 * r15: tmp6
3504 * r16: tmp7
3505 *
3506 */
3507 void MacroAssembler::multiply_to_len(Register x, Register xlen, Register y, Register ylen,
3508 Register z, Register zlen,
3509 Register tmp1, Register tmp2, Register tmp3, Register tmp4,
3510 Register tmp5, Register tmp6, Register product_hi) {
3511
3512 assert_different_registers(x, xlen, y, ylen, z, zlen, tmp1, tmp2, tmp3, tmp4, tmp5, tmp6);
3513
3514 const Register idx = tmp1;
3515 const Register kdx = tmp2;
3516 const Register xstart = tmp3;
3517
3518 const Register y_idx = tmp4;
3519 const Register carry = tmp5;
3520 const Register product = xlen;
3521 const Register x_xstart = zlen; // reuse register
3522
3523 // First Loop.
3524 //
3525 // final static long LONG_MASK = 0xffffffffL;
3526 // int xstart = xlen - 1;
3527 // int ystart = ylen - 1;
3528 // long carry = 0;
3529 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
3530 // long product = (y[idx] & LONG_MASK) * (x[xstart] & LONG_MASK) + carry;
3531 // z[kdx] = (int)product;
3532 // carry = product >>> 32;
3533 // }
3534 // z[xstart] = (int)carry;
3535 //
3536
3537 movw(idx, ylen); // idx = ylen;
3538 movw(kdx, zlen); // kdx = xlen+ylen;
3539 mov(carry, zr); // carry = 0;
3540
3541 Label L_done;
3542
3543 movw(xstart, xlen);
3544 subsw(xstart, xstart, 1);
3545 br(Assembler::MI, L_done);
3546
3547 multiply_64_x_64_loop(x, xstart, x_xstart, y, y_idx, z, carry, product, idx, kdx);
3548
3549 Label L_second_loop;
3550 cbzw(kdx, L_second_loop);
3551
3552 Label L_carry;
3553 subw(kdx, kdx, 1);
3554 cbzw(kdx, L_carry);
3555
3556 strw(carry, Address(z, kdx, Address::uxtw(LogBytesPerInt)));
3557 lsr(carry, carry, 32);
3558 subw(kdx, kdx, 1);
3559
3560 bind(L_carry);
3561 strw(carry, Address(z, kdx, Address::uxtw(LogBytesPerInt)));
3562
3563 // Second and third (nested) loops.
3564 //
3565 // for (int i = xstart-1; i >= 0; i--) { // Second loop
3566 // carry = 0;
3567 // for (int jdx=ystart, k=ystart+1+i; jdx >= 0; jdx--, k--) { // Third loop
3568 // long product = (y[jdx] & LONG_MASK) * (x[i] & LONG_MASK) +
3569 // (z[k] & LONG_MASK) + carry;
3570 // z[k] = (int)product;
3571 // carry = product >>> 32;
3572 // }
3573 // z[i] = (int)carry;
3574 // }
3575 //
3576 // i = xlen, j = tmp1, k = tmp2, carry = tmp5, x[i] = product_hi
3577
3578 const Register jdx = tmp1;
3579
3580 bind(L_second_loop);
3581 mov(carry, zr); // carry = 0;
3582 movw(jdx, ylen); // j = ystart+1
3583
3584 subsw(xstart, xstart, 1); // i = xstart-1;
3585 br(Assembler::MI, L_done);
3586
3587 str(z, Address(pre(sp, -4 * wordSize)));
3588
3589 Label L_last_x;
3590 lea(z, offsetted_address(z, xstart, Address::uxtw(LogBytesPerInt), 4, BytesPerInt)); // z = z + k - j
3591 subsw(xstart, xstart, 1); // i = xstart-1;
3592 br(Assembler::MI, L_last_x);
3593
3594 lea(rscratch1, Address(x, xstart, Address::uxtw(LogBytesPerInt)));
3595 ldr(product_hi, Address(rscratch1));
3596 ror(product_hi, product_hi, 32); // convert big-endian to little-endian
3597
3598 Label L_third_loop_prologue;
3599 bind(L_third_loop_prologue);
3600
3601 str(ylen, Address(sp, wordSize));
3602 stp(x, xstart, Address(sp, 2 * wordSize));
3603 multiply_128_x_128_loop(y, z, carry, x, jdx, ylen, product,
3604 tmp2, x_xstart, tmp3, tmp4, tmp6, product_hi);
3605 ldp(z, ylen, Address(post(sp, 2 * wordSize)));
3606 ldp(x, xlen, Address(post(sp, 2 * wordSize))); // copy old xstart -> xlen
3607
3608 addw(tmp3, xlen, 1);
3609 strw(carry, Address(z, tmp3, Address::uxtw(LogBytesPerInt)));
3610 subsw(tmp3, tmp3, 1);
3611 br(Assembler::MI, L_done);
3612
3613 lsr(carry, carry, 32);
3614 strw(carry, Address(z, tmp3, Address::uxtw(LogBytesPerInt)));
3615 b(L_second_loop);
3616
3617 // Next infrequent code is moved outside loops.
3618 bind(L_last_x);
3619 ldrw(product_hi, Address(x, 0));
3620 b(L_third_loop_prologue);
3621
3622 bind(L_done);
3623 }
3624
3625 // Code for BigInteger::mulAdd intrinsic
3626 // out = r0
3627 // in = r1
3628 // offset = r2 (already out.length-offset)
3629 // len = r3
3630 // k = r4
3631 //
3632 // pseudo code from java implementation:
3633 // carry = 0;
3634 // offset = out.length-offset - 1;
3635 // for (int j=len-1; j >= 0; j--) {
3636 // product = (in[j] & LONG_MASK) * kLong + (out[offset] & LONG_MASK) + carry;
3637 // out[offset--] = (int)product;
3638 // carry = product >>> 32;
3639 // }
3640 // return (int)carry;
3641 void MacroAssembler::mul_add(Register out, Register in, Register offset,
3642 Register len, Register k) {
3643 Label LOOP, END;
3644 // pre-loop
3645 cmp(len, zr); // cmp, not cbz/cbnz: to use condition twice => less branches
3646 csel(out, zr, out, Assembler::EQ);
3647 br(Assembler::EQ, END);
3648 add(in, in, len, LSL, 2); // in[j+1] address
3649 add(offset, out, offset, LSL, 2); // out[offset + 1] address
3650 mov(out, zr); // used to keep carry now
3651 BIND(LOOP);
3652 ldrw(rscratch1, Address(pre(in, -4)));
3653 madd(rscratch1, rscratch1, k, out);
3654 ldrw(rscratch2, Address(pre(offset, -4)));
3655 add(rscratch1, rscratch1, rscratch2);
3656 strw(rscratch1, Address(offset));
3657 lsr(out, rscratch1, 32);
3658 subs(len, len, 1);
3659 br(Assembler::NE, LOOP);
3660 BIND(END);
3661 }
3662
3663 /**
3664 * Emits code to update CRC-32 with a byte value according to constants in table
3665 *
3666 * @param [in,out]crc Register containing the crc.
3667 * @param [in]val Register containing the byte to fold into the CRC.
3668 * @param [in]table Register containing the table of crc constants.
3669 *
3670 * uint32_t crc;
3671 * val = crc_table[(val ^ crc) & 0xFF];
3672 * crc = val ^ (crc >> 8);
3673 *
3674 */
3675 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) {
3676 eor(val, val, crc);
3677 andr(val, val, 0xff);
3678 ldrw(val, Address(table, val, Address::lsl(2)));
3679 eor(crc, val, crc, Assembler::LSR, 8);
3680 }
3681
3682 /**
3683 * Emits code to update CRC-32 with a 32-bit value according to tables 0 to 3
3684 *
3685 * @param [in,out]crc Register containing the crc.
3686 * @param [in]v Register containing the 32-bit to fold into the CRC.
3687 * @param [in]table0 Register containing table 0 of crc constants.
3688 * @param [in]table1 Register containing table 1 of crc constants.
3689 * @param [in]table2 Register containing table 2 of crc constants.
3690 * @param [in]table3 Register containing table 3 of crc constants.
3691 *
3692 * uint32_t crc;
3693 * v = crc ^ v
3694 * crc = table3[v&0xff]^table2[(v>>8)&0xff]^table1[(v>>16)&0xff]^table0[v>>24]
3695 *
3696 */
3697 void MacroAssembler::update_word_crc32(Register crc, Register v, Register tmp,
3698 Register table0, Register table1, Register table2, Register table3,
3699 bool upper) {
3700 eor(v, crc, v, upper ? LSR:LSL, upper ? 32:0);
3701 uxtb(tmp, v);
3702 ldrw(crc, Address(table3, tmp, Address::lsl(2)));
3703 ubfx(tmp, v, 8, 8);
3704 ldrw(tmp, Address(table2, tmp, Address::lsl(2)));
3705 eor(crc, crc, tmp);
3706 ubfx(tmp, v, 16, 8);
3707 ldrw(tmp, Address(table1, tmp, Address::lsl(2)));
3708 eor(crc, crc, tmp);
3709 ubfx(tmp, v, 24, 8);
3710 ldrw(tmp, Address(table0, tmp, Address::lsl(2)));
3711 eor(crc, crc, tmp);
3712 }
3713
3714 void MacroAssembler::kernel_crc32_using_crypto_pmull(Register crc, Register buf,
3715 Register len, Register tmp0, Register tmp1, Register tmp2, Register tmp3) {
3716 Label CRC_by4_loop, CRC_by1_loop, CRC_less128, CRC_by128_pre, CRC_by32_loop, CRC_less32, L_exit;
3717 assert_different_registers(crc, buf, len, tmp0, tmp1, tmp2);
3718
3719 subs(tmp0, len, 384);
3720 mvnw(crc, crc);
3721 br(Assembler::GE, CRC_by128_pre);
3722 BIND(CRC_less128);
3723 subs(len, len, 32);
3724 br(Assembler::GE, CRC_by32_loop);
3725 BIND(CRC_less32);
3726 adds(len, len, 32 - 4);
3727 br(Assembler::GE, CRC_by4_loop);
3728 adds(len, len, 4);
3729 br(Assembler::GT, CRC_by1_loop);
3730 b(L_exit);
3731
3732 BIND(CRC_by32_loop);
3733 ldp(tmp0, tmp1, Address(buf));
3734 crc32x(crc, crc, tmp0);
3735 ldp(tmp2, tmp3, Address(buf, 16));
3736 crc32x(crc, crc, tmp1);
3737 add(buf, buf, 32);
3738 crc32x(crc, crc, tmp2);
3739 subs(len, len, 32);
3740 crc32x(crc, crc, tmp3);
3741 br(Assembler::GE, CRC_by32_loop);
3742 cmn(len, (u1)32);
3743 br(Assembler::NE, CRC_less32);
3744 b(L_exit);
3745
3746 BIND(CRC_by4_loop);
3747 ldrw(tmp0, Address(post(buf, 4)));
3748 subs(len, len, 4);
3749 crc32w(crc, crc, tmp0);
3750 br(Assembler::GE, CRC_by4_loop);
3751 adds(len, len, 4);
3752 br(Assembler::LE, L_exit);
3753 BIND(CRC_by1_loop);
3754 ldrb(tmp0, Address(post(buf, 1)));
3755 subs(len, len, 1);
3756 crc32b(crc, crc, tmp0);
3757 br(Assembler::GT, CRC_by1_loop);
3758 b(L_exit);
3759
3760 BIND(CRC_by128_pre);
3761 kernel_crc32_common_fold_using_crypto_pmull(crc, buf, len, tmp0, tmp1, tmp2,
3762 4*256*sizeof(juint) + 8*sizeof(juint));
3763 mov(crc, 0);
3764 crc32x(crc, crc, tmp0);
3765 crc32x(crc, crc, tmp1);
3766
3767 cbnz(len, CRC_less128);
3768
3769 BIND(L_exit);
3770 mvnw(crc, crc);
3771 }
3772
3773 void MacroAssembler::kernel_crc32_using_crc32(Register crc, Register buf,
3774 Register len, Register tmp0, Register tmp1, Register tmp2,
3775 Register tmp3) {
3776 Label CRC_by64_loop, CRC_by4_loop, CRC_by1_loop, CRC_less64, CRC_by64_pre, CRC_by32_loop, CRC_less32, L_exit;
3777 assert_different_registers(crc, buf, len, tmp0, tmp1, tmp2, tmp3);
3778
3779 mvnw(crc, crc);
3780
3781 subs(len, len, 128);
3782 br(Assembler::GE, CRC_by64_pre);
3783 BIND(CRC_less64);
3784 adds(len, len, 128-32);
3785 br(Assembler::GE, CRC_by32_loop);
3786 BIND(CRC_less32);
3787 adds(len, len, 32-4);
3788 br(Assembler::GE, CRC_by4_loop);
3789 adds(len, len, 4);
3790 br(Assembler::GT, CRC_by1_loop);
3791 b(L_exit);
3792
3793 BIND(CRC_by32_loop);
3794 ldp(tmp0, tmp1, Address(post(buf, 16)));
3795 subs(len, len, 32);
3796 crc32x(crc, crc, tmp0);
3797 ldr(tmp2, Address(post(buf, 8)));
3798 crc32x(crc, crc, tmp1);
3799 ldr(tmp3, Address(post(buf, 8)));
3800 crc32x(crc, crc, tmp2);
3801 crc32x(crc, crc, tmp3);
3802 br(Assembler::GE, CRC_by32_loop);
3803 cmn(len, (u1)32);
3804 br(Assembler::NE, CRC_less32);
3805 b(L_exit);
3806
3807 BIND(CRC_by4_loop);
3808 ldrw(tmp0, Address(post(buf, 4)));
3809 subs(len, len, 4);
3810 crc32w(crc, crc, tmp0);
3811 br(Assembler::GE, CRC_by4_loop);
3812 adds(len, len, 4);
3813 br(Assembler::LE, L_exit);
3814 BIND(CRC_by1_loop);
3815 ldrb(tmp0, Address(post(buf, 1)));
3816 subs(len, len, 1);
3817 crc32b(crc, crc, tmp0);
3818 br(Assembler::GT, CRC_by1_loop);
3819 b(L_exit);
3820
3821 BIND(CRC_by64_pre);
3822 sub(buf, buf, 8);
3823 ldp(tmp0, tmp1, Address(buf, 8));
3824 crc32x(crc, crc, tmp0);
3825 ldr(tmp2, Address(buf, 24));
3826 crc32x(crc, crc, tmp1);
3827 ldr(tmp3, Address(buf, 32));
3828 crc32x(crc, crc, tmp2);
3829 ldr(tmp0, Address(buf, 40));
3830 crc32x(crc, crc, tmp3);
3831 ldr(tmp1, Address(buf, 48));
3832 crc32x(crc, crc, tmp0);
3833 ldr(tmp2, Address(buf, 56));
3834 crc32x(crc, crc, tmp1);
3835 ldr(tmp3, Address(pre(buf, 64)));
3836
3837 b(CRC_by64_loop);
3838
3839 align(CodeEntryAlignment);
3840 BIND(CRC_by64_loop);
3841 subs(len, len, 64);
3842 crc32x(crc, crc, tmp2);
3843 ldr(tmp0, Address(buf, 8));
3844 crc32x(crc, crc, tmp3);
3845 ldr(tmp1, Address(buf, 16));
3846 crc32x(crc, crc, tmp0);
3847 ldr(tmp2, Address(buf, 24));
3848 crc32x(crc, crc, tmp1);
3849 ldr(tmp3, Address(buf, 32));
3850 crc32x(crc, crc, tmp2);
3851 ldr(tmp0, Address(buf, 40));
3852 crc32x(crc, crc, tmp3);
3853 ldr(tmp1, Address(buf, 48));
3854 crc32x(crc, crc, tmp0);
3855 ldr(tmp2, Address(buf, 56));
3856 crc32x(crc, crc, tmp1);
3857 ldr(tmp3, Address(pre(buf, 64)));
3858 br(Assembler::GE, CRC_by64_loop);
3859
3860 // post-loop
3861 crc32x(crc, crc, tmp2);
3862 crc32x(crc, crc, tmp3);
3863
3864 sub(len, len, 64);
3865 add(buf, buf, 8);
3866 cmn(len, (u1)128);
3867 br(Assembler::NE, CRC_less64);
3868 BIND(L_exit);
3869 mvnw(crc, crc);
3870 }
3871
3872 /**
3873 * @param crc register containing existing CRC (32-bit)
3874 * @param buf register pointing to input byte buffer (byte*)
3875 * @param len register containing number of bytes
3876 * @param table register that will contain address of CRC table
3877 * @param tmp scratch register
3878 */
3879 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len,
3880 Register table0, Register table1, Register table2, Register table3,
3881 Register tmp, Register tmp2, Register tmp3) {
3882 Label L_by16, L_by16_loop, L_by4, L_by4_loop, L_by1, L_by1_loop, L_exit;
3883
3884 if (UseCryptoPmullForCRC32) {
3885 kernel_crc32_using_crypto_pmull(crc, buf, len, table0, table1, table2, table3);
3886 return;
3887 }
3888
3889 if (UseCRC32) {
3890 kernel_crc32_using_crc32(crc, buf, len, table0, table1, table2, table3);
3891 return;
3892 }
3893
3894 mvnw(crc, crc);
3895
3896 {
3897 uint64_t offset;
3898 adrp(table0, ExternalAddress(StubRoutines::crc_table_addr()), offset);
3899 add(table0, table0, offset);
3900 }
3901 add(table1, table0, 1*256*sizeof(juint));
3902 add(table2, table0, 2*256*sizeof(juint));
3903 add(table3, table0, 3*256*sizeof(juint));
3904
3905 if (UseNeon) {
3906 cmp(len, (u1)64);
3907 br(Assembler::LT, L_by16);
3908 eor(v16, T16B, v16, v16);
3909
3910 Label L_fold;
3911
3912 add(tmp, table0, 4*256*sizeof(juint)); // Point at the Neon constants
3913
3914 ld1(v0, v1, T2D, post(buf, 32));
3915 ld1r(v4, T2D, post(tmp, 8));
3916 ld1r(v5, T2D, post(tmp, 8));
3917 ld1r(v6, T2D, post(tmp, 8));
3918 ld1r(v7, T2D, post(tmp, 8));
3919 mov(v16, S, 0, crc);
3920
3921 eor(v0, T16B, v0, v16);
3922 sub(len, len, 64);
3923
3924 BIND(L_fold);
3925 pmull(v22, T8H, v0, v5, T8B);
3926 pmull(v20, T8H, v0, v7, T8B);
3927 pmull(v23, T8H, v0, v4, T8B);
3928 pmull(v21, T8H, v0, v6, T8B);
3929
3930 pmull2(v18, T8H, v0, v5, T16B);
3931 pmull2(v16, T8H, v0, v7, T16B);
3932 pmull2(v19, T8H, v0, v4, T16B);
3933 pmull2(v17, T8H, v0, v6, T16B);
3934
3935 uzp1(v24, T8H, v20, v22);
3936 uzp2(v25, T8H, v20, v22);
3937 eor(v20, T16B, v24, v25);
3938
3939 uzp1(v26, T8H, v16, v18);
3940 uzp2(v27, T8H, v16, v18);
3941 eor(v16, T16B, v26, v27);
3942
3943 ushll2(v22, T4S, v20, T8H, 8);
3944 ushll(v20, T4S, v20, T4H, 8);
3945
3946 ushll2(v18, T4S, v16, T8H, 8);
3947 ushll(v16, T4S, v16, T4H, 8);
3948
3949 eor(v22, T16B, v23, v22);
3950 eor(v18, T16B, v19, v18);
3951 eor(v20, T16B, v21, v20);
3952 eor(v16, T16B, v17, v16);
3953
3954 uzp1(v17, T2D, v16, v20);
3955 uzp2(v21, T2D, v16, v20);
3956 eor(v17, T16B, v17, v21);
3957
3958 ushll2(v20, T2D, v17, T4S, 16);
3959 ushll(v16, T2D, v17, T2S, 16);
3960
3961 eor(v20, T16B, v20, v22);
3962 eor(v16, T16B, v16, v18);
3963
3964 uzp1(v17, T2D, v20, v16);
3965 uzp2(v21, T2D, v20, v16);
3966 eor(v28, T16B, v17, v21);
3967
3968 pmull(v22, T8H, v1, v5, T8B);
3969 pmull(v20, T8H, v1, v7, T8B);
3970 pmull(v23, T8H, v1, v4, T8B);
3971 pmull(v21, T8H, v1, v6, T8B);
3972
3973 pmull2(v18, T8H, v1, v5, T16B);
3974 pmull2(v16, T8H, v1, v7, T16B);
3975 pmull2(v19, T8H, v1, v4, T16B);
3976 pmull2(v17, T8H, v1, v6, T16B);
3977
3978 ld1(v0, v1, T2D, post(buf, 32));
3979
3980 uzp1(v24, T8H, v20, v22);
3981 uzp2(v25, T8H, v20, v22);
3982 eor(v20, T16B, v24, v25);
3983
3984 uzp1(v26, T8H, v16, v18);
3985 uzp2(v27, T8H, v16, v18);
3986 eor(v16, T16B, v26, v27);
3987
3988 ushll2(v22, T4S, v20, T8H, 8);
3989 ushll(v20, T4S, v20, T4H, 8);
3990
3991 ushll2(v18, T4S, v16, T8H, 8);
3992 ushll(v16, T4S, v16, T4H, 8);
3993
3994 eor(v22, T16B, v23, v22);
3995 eor(v18, T16B, v19, v18);
3996 eor(v20, T16B, v21, v20);
3997 eor(v16, T16B, v17, v16);
3998
3999 uzp1(v17, T2D, v16, v20);
4000 uzp2(v21, T2D, v16, v20);
4001 eor(v16, T16B, v17, v21);
4002
4003 ushll2(v20, T2D, v16, T4S, 16);
4004 ushll(v16, T2D, v16, T2S, 16);
4005
4006 eor(v20, T16B, v22, v20);
4007 eor(v16, T16B, v16, v18);
4008
4009 uzp1(v17, T2D, v20, v16);
4010 uzp2(v21, T2D, v20, v16);
4011 eor(v20, T16B, v17, v21);
4012
4013 shl(v16, T2D, v28, 1);
4014 shl(v17, T2D, v20, 1);
4015
4016 eor(v0, T16B, v0, v16);
4017 eor(v1, T16B, v1, v17);
4018
4019 subs(len, len, 32);
4020 br(Assembler::GE, L_fold);
4021
4022 mov(crc, 0);
4023 mov(tmp, v0, D, 0);
4024 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false);
4025 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true);
4026 mov(tmp, v0, D, 1);
4027 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false);
4028 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true);
4029 mov(tmp, v1, D, 0);
4030 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false);
4031 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true);
4032 mov(tmp, v1, D, 1);
4033 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false);
4034 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true);
4035
4036 add(len, len, 32);
4037 }
4038
4039 BIND(L_by16);
4040 subs(len, len, 16);
4041 br(Assembler::GE, L_by16_loop);
4042 adds(len, len, 16-4);
4043 br(Assembler::GE, L_by4_loop);
4044 adds(len, len, 4);
4045 br(Assembler::GT, L_by1_loop);
4046 b(L_exit);
4047
4048 BIND(L_by4_loop);
4049 ldrw(tmp, Address(post(buf, 4)));
4050 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3);
4051 subs(len, len, 4);
4052 br(Assembler::GE, L_by4_loop);
4053 adds(len, len, 4);
4054 br(Assembler::LE, L_exit);
4055 BIND(L_by1_loop);
4056 subs(len, len, 1);
4057 ldrb(tmp, Address(post(buf, 1)));
4058 update_byte_crc32(crc, tmp, table0);
4059 br(Assembler::GT, L_by1_loop);
4060 b(L_exit);
4061
4062 align(CodeEntryAlignment);
4063 BIND(L_by16_loop);
4064 subs(len, len, 16);
4065 ldp(tmp, tmp3, Address(post(buf, 16)));
4066 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false);
4067 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true);
4068 update_word_crc32(crc, tmp3, tmp2, table0, table1, table2, table3, false);
4069 update_word_crc32(crc, tmp3, tmp2, table0, table1, table2, table3, true);
4070 br(Assembler::GE, L_by16_loop);
4071 adds(len, len, 16-4);
4072 br(Assembler::GE, L_by4_loop);
4073 adds(len, len, 4);
4074 br(Assembler::GT, L_by1_loop);
4075 BIND(L_exit);
4076 mvnw(crc, crc);
4077 }
4078
4079 void MacroAssembler::kernel_crc32c_using_crypto_pmull(Register crc, Register buf,
4080 Register len, Register tmp0, Register tmp1, Register tmp2, Register tmp3) {
4081 Label CRC_by4_loop, CRC_by1_loop, CRC_less128, CRC_by128_pre, CRC_by32_loop, CRC_less32, L_exit;
4082 assert_different_registers(crc, buf, len, tmp0, tmp1, tmp2);
4083
4084 subs(tmp0, len, 384);
4085 br(Assembler::GE, CRC_by128_pre);
4086 BIND(CRC_less128);
4087 subs(len, len, 32);
4088 br(Assembler::GE, CRC_by32_loop);
4089 BIND(CRC_less32);
4090 adds(len, len, 32 - 4);
4091 br(Assembler::GE, CRC_by4_loop);
4092 adds(len, len, 4);
4093 br(Assembler::GT, CRC_by1_loop);
4094 b(L_exit);
4095
4096 BIND(CRC_by32_loop);
4097 ldp(tmp0, tmp1, Address(buf));
4098 crc32cx(crc, crc, tmp0);
4099 ldr(tmp2, Address(buf, 16));
4100 crc32cx(crc, crc, tmp1);
4101 ldr(tmp3, Address(buf, 24));
4102 crc32cx(crc, crc, tmp2);
4103 add(buf, buf, 32);
4104 subs(len, len, 32);
4105 crc32cx(crc, crc, tmp3);
4106 br(Assembler::GE, CRC_by32_loop);
4107 cmn(len, (u1)32);
4108 br(Assembler::NE, CRC_less32);
4109 b(L_exit);
4110
4111 BIND(CRC_by4_loop);
4112 ldrw(tmp0, Address(post(buf, 4)));
4113 subs(len, len, 4);
4114 crc32cw(crc, crc, tmp0);
4115 br(Assembler::GE, CRC_by4_loop);
4116 adds(len, len, 4);
4117 br(Assembler::LE, L_exit);
4118 BIND(CRC_by1_loop);
4119 ldrb(tmp0, Address(post(buf, 1)));
4120 subs(len, len, 1);
4121 crc32cb(crc, crc, tmp0);
4122 br(Assembler::GT, CRC_by1_loop);
4123 b(L_exit);
4124
4125 BIND(CRC_by128_pre);
4126 kernel_crc32_common_fold_using_crypto_pmull(crc, buf, len, tmp0, tmp1, tmp2,
4127 4*256*sizeof(juint) + 8*sizeof(juint) + 0x50);
4128 mov(crc, 0);
4129 crc32cx(crc, crc, tmp0);
4130 crc32cx(crc, crc, tmp1);
4131
4132 cbnz(len, CRC_less128);
4133
4134 BIND(L_exit);
4135 }
4136
4137 void MacroAssembler::kernel_crc32c_using_crc32c(Register crc, Register buf,
4138 Register len, Register tmp0, Register tmp1, Register tmp2,
4139 Register tmp3) {
4140 Label CRC_by64_loop, CRC_by4_loop, CRC_by1_loop, CRC_less64, CRC_by64_pre, CRC_by32_loop, CRC_less32, L_exit;
4141 assert_different_registers(crc, buf, len, tmp0, tmp1, tmp2, tmp3);
4142
4143 subs(len, len, 128);
4144 br(Assembler::GE, CRC_by64_pre);
4145 BIND(CRC_less64);
4146 adds(len, len, 128-32);
4147 br(Assembler::GE, CRC_by32_loop);
4148 BIND(CRC_less32);
4149 adds(len, len, 32-4);
4150 br(Assembler::GE, CRC_by4_loop);
4151 adds(len, len, 4);
4152 br(Assembler::GT, CRC_by1_loop);
4153 b(L_exit);
4154
4155 BIND(CRC_by32_loop);
4156 ldp(tmp0, tmp1, Address(post(buf, 16)));
4157 subs(len, len, 32);
4158 crc32cx(crc, crc, tmp0);
4159 ldr(tmp2, Address(post(buf, 8)));
4160 crc32cx(crc, crc, tmp1);
4161 ldr(tmp3, Address(post(buf, 8)));
4162 crc32cx(crc, crc, tmp2);
4163 crc32cx(crc, crc, tmp3);
4164 br(Assembler::GE, CRC_by32_loop);
4165 cmn(len, (u1)32);
4166 br(Assembler::NE, CRC_less32);
4167 b(L_exit);
4168
4169 BIND(CRC_by4_loop);
4170 ldrw(tmp0, Address(post(buf, 4)));
4171 subs(len, len, 4);
4172 crc32cw(crc, crc, tmp0);
4173 br(Assembler::GE, CRC_by4_loop);
4174 adds(len, len, 4);
4175 br(Assembler::LE, L_exit);
4176 BIND(CRC_by1_loop);
4177 ldrb(tmp0, Address(post(buf, 1)));
4178 subs(len, len, 1);
4179 crc32cb(crc, crc, tmp0);
4180 br(Assembler::GT, CRC_by1_loop);
4181 b(L_exit);
4182
4183 BIND(CRC_by64_pre);
4184 sub(buf, buf, 8);
4185 ldp(tmp0, tmp1, Address(buf, 8));
4186 crc32cx(crc, crc, tmp0);
4187 ldr(tmp2, Address(buf, 24));
4188 crc32cx(crc, crc, tmp1);
4189 ldr(tmp3, Address(buf, 32));
4190 crc32cx(crc, crc, tmp2);
4191 ldr(tmp0, Address(buf, 40));
4192 crc32cx(crc, crc, tmp3);
4193 ldr(tmp1, Address(buf, 48));
4194 crc32cx(crc, crc, tmp0);
4195 ldr(tmp2, Address(buf, 56));
4196 crc32cx(crc, crc, tmp1);
4197 ldr(tmp3, Address(pre(buf, 64)));
4198
4199 b(CRC_by64_loop);
4200
4201 align(CodeEntryAlignment);
4202 BIND(CRC_by64_loop);
4203 subs(len, len, 64);
4204 crc32cx(crc, crc, tmp2);
4205 ldr(tmp0, Address(buf, 8));
4206 crc32cx(crc, crc, tmp3);
4207 ldr(tmp1, Address(buf, 16));
4208 crc32cx(crc, crc, tmp0);
4209 ldr(tmp2, Address(buf, 24));
4210 crc32cx(crc, crc, tmp1);
4211 ldr(tmp3, Address(buf, 32));
4212 crc32cx(crc, crc, tmp2);
4213 ldr(tmp0, Address(buf, 40));
4214 crc32cx(crc, crc, tmp3);
4215 ldr(tmp1, Address(buf, 48));
4216 crc32cx(crc, crc, tmp0);
4217 ldr(tmp2, Address(buf, 56));
4218 crc32cx(crc, crc, tmp1);
4219 ldr(tmp3, Address(pre(buf, 64)));
4220 br(Assembler::GE, CRC_by64_loop);
4221
4222 // post-loop
4223 crc32cx(crc, crc, tmp2);
4224 crc32cx(crc, crc, tmp3);
4225
4226 sub(len, len, 64);
4227 add(buf, buf, 8);
4228 cmn(len, (u1)128);
4229 br(Assembler::NE, CRC_less64);
4230 BIND(L_exit);
4231 }
4232
4233 /**
4234 * @param crc register containing existing CRC (32-bit)
4235 * @param buf register pointing to input byte buffer (byte*)
4236 * @param len register containing number of bytes
4237 * @param table register that will contain address of CRC table
4238 * @param tmp scratch register
4239 */
4240 void MacroAssembler::kernel_crc32c(Register crc, Register buf, Register len,
4241 Register table0, Register table1, Register table2, Register table3,
4242 Register tmp, Register tmp2, Register tmp3) {
4243 if (UseCryptoPmullForCRC32) {
4244 kernel_crc32c_using_crypto_pmull(crc, buf, len, table0, table1, table2, table3);
4245 } else {
4246 kernel_crc32c_using_crc32c(crc, buf, len, table0, table1, table2, table3);
4247 }
4248 }
4249
4250 void MacroAssembler::kernel_crc32_common_fold_using_crypto_pmull(Register crc, Register buf,
4251 Register len, Register tmp0, Register tmp1, Register tmp2, size_t table_offset) {
4252 Label CRC_by128_loop;
4253 assert_different_registers(crc, buf, len, tmp0, tmp1, tmp2);
4254
4255 sub(len, len, 256);
4256 Register table = tmp0;
4257 {
4258 uint64_t offset;
4259 adrp(table, ExternalAddress(StubRoutines::crc_table_addr()), offset);
4260 add(table, table, offset);
4261 }
4262 add(table, table, table_offset);
4263
4264 // Registers v0..v7 are used as data registers.
4265 // Registers v16..v31 are used as tmp registers.
4266 sub(buf, buf, 0x10);
4267 ldrq(v0, Address(buf, 0x10));
4268 ldrq(v1, Address(buf, 0x20));
4269 ldrq(v2, Address(buf, 0x30));
4270 ldrq(v3, Address(buf, 0x40));
4271 ldrq(v4, Address(buf, 0x50));
4272 ldrq(v5, Address(buf, 0x60));
4273 ldrq(v6, Address(buf, 0x70));
4274 ldrq(v7, Address(pre(buf, 0x80)));
4275
4276 movi(v31, T4S, 0);
4277 mov(v31, S, 0, crc);
4278 eor(v0, T16B, v0, v31);
4279
4280 // Register v16 contains constants from the crc table.
4281 ldrq(v16, Address(table));
4282 b(CRC_by128_loop);
4283
4284 align(OptoLoopAlignment);
4285 BIND(CRC_by128_loop);
4286 pmull (v17, T1Q, v0, v16, T1D);
4287 pmull2(v18, T1Q, v0, v16, T2D);
4288 ldrq(v0, Address(buf, 0x10));
4289 eor3(v0, T16B, v17, v18, v0);
4290
4291 pmull (v19, T1Q, v1, v16, T1D);
4292 pmull2(v20, T1Q, v1, v16, T2D);
4293 ldrq(v1, Address(buf, 0x20));
4294 eor3(v1, T16B, v19, v20, v1);
4295
4296 pmull (v21, T1Q, v2, v16, T1D);
4297 pmull2(v22, T1Q, v2, v16, T2D);
4298 ldrq(v2, Address(buf, 0x30));
4299 eor3(v2, T16B, v21, v22, v2);
4300
4301 pmull (v23, T1Q, v3, v16, T1D);
4302 pmull2(v24, T1Q, v3, v16, T2D);
4303 ldrq(v3, Address(buf, 0x40));
4304 eor3(v3, T16B, v23, v24, v3);
4305
4306 pmull (v25, T1Q, v4, v16, T1D);
4307 pmull2(v26, T1Q, v4, v16, T2D);
4308 ldrq(v4, Address(buf, 0x50));
4309 eor3(v4, T16B, v25, v26, v4);
4310
4311 pmull (v27, T1Q, v5, v16, T1D);
4312 pmull2(v28, T1Q, v5, v16, T2D);
4313 ldrq(v5, Address(buf, 0x60));
4314 eor3(v5, T16B, v27, v28, v5);
4315
4316 pmull (v29, T1Q, v6, v16, T1D);
4317 pmull2(v30, T1Q, v6, v16, T2D);
4318 ldrq(v6, Address(buf, 0x70));
4319 eor3(v6, T16B, v29, v30, v6);
4320
4321 // Reuse registers v23, v24.
4322 // Using them won't block the first instruction of the next iteration.
4323 pmull (v23, T1Q, v7, v16, T1D);
4324 pmull2(v24, T1Q, v7, v16, T2D);
4325 ldrq(v7, Address(pre(buf, 0x80)));
4326 eor3(v7, T16B, v23, v24, v7);
4327
4328 subs(len, len, 0x80);
4329 br(Assembler::GE, CRC_by128_loop);
4330
4331 // fold into 512 bits
4332 // Use v31 for constants because v16 can be still in use.
4333 ldrq(v31, Address(table, 0x10));
4334
4335 pmull (v17, T1Q, v0, v31, T1D);
4336 pmull2(v18, T1Q, v0, v31, T2D);
4337 eor3(v0, T16B, v17, v18, v4);
4338
4339 pmull (v19, T1Q, v1, v31, T1D);
4340 pmull2(v20, T1Q, v1, v31, T2D);
4341 eor3(v1, T16B, v19, v20, v5);
4342
4343 pmull (v21, T1Q, v2, v31, T1D);
4344 pmull2(v22, T1Q, v2, v31, T2D);
4345 eor3(v2, T16B, v21, v22, v6);
4346
4347 pmull (v23, T1Q, v3, v31, T1D);
4348 pmull2(v24, T1Q, v3, v31, T2D);
4349 eor3(v3, T16B, v23, v24, v7);
4350
4351 // fold into 128 bits
4352 // Use v17 for constants because v31 can be still in use.
4353 ldrq(v17, Address(table, 0x20));
4354 pmull (v25, T1Q, v0, v17, T1D);
4355 pmull2(v26, T1Q, v0, v17, T2D);
4356 eor3(v3, T16B, v3, v25, v26);
4357
4358 // Use v18 for constants because v17 can be still in use.
4359 ldrq(v18, Address(table, 0x30));
4360 pmull (v27, T1Q, v1, v18, T1D);
4361 pmull2(v28, T1Q, v1, v18, T2D);
4362 eor3(v3, T16B, v3, v27, v28);
4363
4364 // Use v19 for constants because v18 can be still in use.
4365 ldrq(v19, Address(table, 0x40));
4366 pmull (v29, T1Q, v2, v19, T1D);
4367 pmull2(v30, T1Q, v2, v19, T2D);
4368 eor3(v0, T16B, v3, v29, v30);
4369
4370 add(len, len, 0x80);
4371 add(buf, buf, 0x10);
4372
4373 mov(tmp0, v0, D, 0);
4374 mov(tmp1, v0, D, 1);
4375 }
4376
4377 SkipIfEqual::SkipIfEqual(
4378 MacroAssembler* masm, const bool* flag_addr, bool value) {
4379 _masm = masm;
4380 uint64_t offset;
4381 _masm->adrp(rscratch1, ExternalAddress((address)flag_addr), offset);
4382 _masm->ldrb(rscratch1, Address(rscratch1, offset));
4383 if (value) {
4384 _masm->cbnzw(rscratch1, _label);
4385 } else {
4386 _masm->cbzw(rscratch1, _label);
4387 }
4388 }
4389
4390 SkipIfEqual::~SkipIfEqual() {
4391 _masm->bind(_label);
4392 }
4393
4394 void MacroAssembler::addptr(const Address &dst, int32_t src) {
4395 Address adr;
4396 switch(dst.getMode()) {
4397 case Address::base_plus_offset:
4398 // This is the expected mode, although we allow all the other
4399 // forms below.
4400 adr = form_address(rscratch2, dst.base(), dst.offset(), LogBytesPerWord);
4401 break;
4402 default:
4403 lea(rscratch2, dst);
4404 adr = Address(rscratch2);
4405 break;
4406 }
4407 ldr(rscratch1, adr);
4408 add(rscratch1, rscratch1, src);
4409 str(rscratch1, adr);
4410 }
4411
4412 void MacroAssembler::cmpptr(Register src1, Address src2) {
4413 uint64_t offset;
4414 adrp(rscratch1, src2, offset);
4415 ldr(rscratch1, Address(rscratch1, offset));
4416 cmp(src1, rscratch1);
4417 }
4418
4419 void MacroAssembler::cmpoop(Register obj1, Register obj2) {
4420 cmp(obj1, obj2);
4421 }
4422
4423 void MacroAssembler::load_method_holder_cld(Register rresult, Register rmethod) {
4424 load_method_holder(rresult, rmethod);
4425 ldr(rresult, Address(rresult, InstanceKlass::class_loader_data_offset()));
4426 }
4427
4428 void MacroAssembler::load_method_holder(Register holder, Register method) {
4429 ldr(holder, Address(method, Method::const_offset())); // ConstMethod*
4430 ldr(holder, Address(holder, ConstMethod::constants_offset())); // ConstantPool*
4431 ldr(holder, Address(holder, ConstantPool::pool_holder_offset())); // InstanceKlass*
4432 }
4433
4434 // Loads the obj's Klass* into dst.
4435 // Preserves all registers (incl src, rscratch1 and rscratch2).
4436 void MacroAssembler::load_nklass_compact(Register dst, Register src) {
4437 assert(UseCompactObjectHeaders, "expects UseCompactObjectHeaders");
4438
4439 Label fast;
4440
4441 // Check if we can take the (common) fast path, if obj is unlocked.
4442 ldr(dst, Address(src, oopDesc::mark_offset_in_bytes()));
4443 tbz(dst, exact_log2(markWord::monitor_value), fast);
4444
4445 // Fetch displaced header
4446 ldr(dst, Address(dst, OM_OFFSET_NO_MONITOR_VALUE_TAG(header)));
4447
4448 // Fast-path: shift to get narrowKlass.
4449 bind(fast);
4450 lsr(dst, dst, markWord::klass_shift);
4451 }
4452
4453 void MacroAssembler::load_klass(Register dst, Register src) {
4454 if (UseCompactObjectHeaders) {
4455 load_nklass_compact(dst, src);
4456 decode_klass_not_null(dst);
4457 } else if (UseCompressedClassPointers) {
4458 ldrw(dst, Address(src, oopDesc::klass_offset_in_bytes()));
4459 decode_klass_not_null(dst);
4460 } else {
4461 ldr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
4462 }
4463 }
4464
4465 // ((OopHandle)result).resolve();
4466 void MacroAssembler::resolve_oop_handle(Register result, Register tmp1, Register tmp2) {
4467 // OopHandle::resolve is an indirection.
4468 access_load_at(T_OBJECT, IN_NATIVE, result, Address(result, 0), tmp1, tmp2);
4469 }
4470
4471 // ((WeakHandle)result).resolve();
4472 void MacroAssembler::resolve_weak_handle(Register result, Register tmp1, Register tmp2) {
4473 assert_different_registers(result, tmp1, tmp2);
4474 Label resolved;
4475
4476 // A null weak handle resolves to null.
4477 cbz(result, resolved);
4478
4479 // Only 64 bit platforms support GCs that require a tmp register
4480 // WeakHandle::resolve is an indirection like jweak.
4481 access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF,
4482 result, Address(result), tmp1, tmp2);
4483 bind(resolved);
4484 }
4485
4486 void MacroAssembler::load_mirror(Register dst, Register method, Register tmp1, Register tmp2) {
4487 const int mirror_offset = in_bytes(Klass::java_mirror_offset());
4488 ldr(dst, Address(rmethod, Method::const_offset()));
4489 ldr(dst, Address(dst, ConstMethod::constants_offset()));
4490 ldr(dst, Address(dst, ConstantPool::pool_holder_offset()));
4491 ldr(dst, Address(dst, mirror_offset));
4492 resolve_oop_handle(dst, tmp1, tmp2);
4493 }
4494
4495 void MacroAssembler::cmp_klass(Register oop, Register trial_klass, Register tmp) {
4496 assert_different_registers(oop, trial_klass, tmp);
4497 if (UseCompressedClassPointers) {
4498 if (UseCompactObjectHeaders) {
4499 load_nklass_compact(tmp, oop);
4500 } else {
4501 ldrw(tmp, Address(oop, oopDesc::klass_offset_in_bytes()));
4502 }
4503 if (CompressedKlassPointers::base() == nullptr) {
4504 cmp(trial_klass, tmp, LSL, CompressedKlassPointers::shift());
4505 return;
4506 } else if (((uint64_t)CompressedKlassPointers::base() & 0xffffffff) == 0
4507 && CompressedKlassPointers::shift() == 0) {
4508 // Only the bottom 32 bits matter
4509 cmpw(trial_klass, tmp);
4510 return;
4511 }
4512 decode_klass_not_null(tmp);
4513 } else {
4514 ldr(tmp, Address(oop, oopDesc::klass_offset_in_bytes()));
4515 }
4516 cmp(trial_klass, tmp);
4517 }
4518
4519 void MacroAssembler::cmp_klass(Register src, Register dst, Register tmp1, Register tmp2) {
4520 if (UseCompactObjectHeaders) {
4521 load_nklass_compact(tmp1, src);
4522 load_nklass_compact(tmp2, dst);
4523 cmpw(tmp1, tmp2);
4524 } else if (UseCompressedClassPointers) {
4525 ldrw(tmp1, Address(src, oopDesc::klass_offset_in_bytes()));
4526 ldrw(tmp2, Address(dst, oopDesc::klass_offset_in_bytes()));
4527 cmpw(tmp1, tmp2);
4528 } else {
4529 ldr(tmp1, Address(src, oopDesc::klass_offset_in_bytes()));
4530 ldr(tmp2, Address(dst, oopDesc::klass_offset_in_bytes()));
4531 cmp(tmp1, tmp2);
4532 }
4533 }
4534
4535 void MacroAssembler::store_klass(Register dst, Register src) {
4536 // FIXME: Should this be a store release? concurrent gcs assumes
4537 // klass length is valid if klass field is not null.
4538 assert(!UseCompactObjectHeaders, "not with compact headers");
4539 if (UseCompressedClassPointers) {
4540 encode_klass_not_null(src);
4541 strw(src, Address(dst, oopDesc::klass_offset_in_bytes()));
4542 } else {
4543 str(src, Address(dst, oopDesc::klass_offset_in_bytes()));
4544 }
4545 }
4546
4547 void MacroAssembler::store_klass_gap(Register dst, Register src) {
4548 assert(!UseCompactObjectHeaders, "not with compact headers");
4549 if (UseCompressedClassPointers) {
4550 // Store to klass gap in destination
4551 strw(src, Address(dst, oopDesc::klass_gap_offset_in_bytes()));
4552 }
4553 }
4554
4555 // Algorithm must match CompressedOops::encode.
4556 void MacroAssembler::encode_heap_oop(Register d, Register s) {
4557 #ifdef ASSERT
4558 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?");
4559 #endif
4560 verify_oop_msg(s, "broken oop in encode_heap_oop");
4561 if (CompressedOops::base() == nullptr) {
4562 if (CompressedOops::shift() != 0) {
4563 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
4564 lsr(d, s, LogMinObjAlignmentInBytes);
4565 } else {
4566 mov(d, s);
4567 }
4568 } else {
4569 subs(d, s, rheapbase);
4570 csel(d, d, zr, Assembler::HS);
4571 lsr(d, d, LogMinObjAlignmentInBytes);
4572
4573 /* Old algorithm: is this any worse?
4574 Label nonnull;
4575 cbnz(r, nonnull);
4576 sub(r, r, rheapbase);
4577 bind(nonnull);
4578 lsr(r, r, LogMinObjAlignmentInBytes);
4579 */
4580 }
4581 }
4582
4583 void MacroAssembler::encode_heap_oop_not_null(Register r) {
4584 #ifdef ASSERT
4585 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?");
4586 if (CheckCompressedOops) {
4587 Label ok;
4588 cbnz(r, ok);
4589 stop("null oop passed to encode_heap_oop_not_null");
4590 bind(ok);
4591 }
4592 #endif
4593 verify_oop_msg(r, "broken oop in encode_heap_oop_not_null");
4594 if (CompressedOops::base() != nullptr) {
4595 sub(r, r, rheapbase);
4596 }
4597 if (CompressedOops::shift() != 0) {
4598 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
4599 lsr(r, r, LogMinObjAlignmentInBytes);
4600 }
4601 }
4602
4603 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) {
4604 #ifdef ASSERT
4605 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?");
4606 if (CheckCompressedOops) {
4607 Label ok;
4608 cbnz(src, ok);
4609 stop("null oop passed to encode_heap_oop_not_null2");
4610 bind(ok);
4611 }
4612 #endif
4613 verify_oop_msg(src, "broken oop in encode_heap_oop_not_null2");
4614
4615 Register data = src;
4616 if (CompressedOops::base() != nullptr) {
4617 sub(dst, src, rheapbase);
4618 data = dst;
4619 }
4620 if (CompressedOops::shift() != 0) {
4621 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
4622 lsr(dst, data, LogMinObjAlignmentInBytes);
4623 data = dst;
4624 }
4625 if (data == src)
4626 mov(dst, src);
4627 }
4628
4629 void MacroAssembler::decode_heap_oop(Register d, Register s) {
4630 #ifdef ASSERT
4631 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?");
4632 #endif
4633 if (CompressedOops::base() == nullptr) {
4634 if (CompressedOops::shift() != 0 || d != s) {
4635 lsl(d, s, CompressedOops::shift());
4636 }
4637 } else {
4638 Label done;
4639 if (d != s)
4640 mov(d, s);
4641 cbz(s, done);
4642 add(d, rheapbase, s, Assembler::LSL, LogMinObjAlignmentInBytes);
4643 bind(done);
4644 }
4645 verify_oop_msg(d, "broken oop in decode_heap_oop");
4646 }
4647
4648 void MacroAssembler::decode_heap_oop_not_null(Register r) {
4649 assert (UseCompressedOops, "should only be used for compressed headers");
4650 assert (Universe::heap() != nullptr, "java heap should be initialized");
4651 // Cannot assert, unverified entry point counts instructions (see .ad file)
4652 // vtableStubs also counts instructions in pd_code_size_limit.
4653 // Also do not verify_oop as this is called by verify_oop.
4654 if (CompressedOops::shift() != 0) {
4655 assert(LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
4656 if (CompressedOops::base() != nullptr) {
4657 add(r, rheapbase, r, Assembler::LSL, LogMinObjAlignmentInBytes);
4658 } else {
4659 add(r, zr, r, Assembler::LSL, LogMinObjAlignmentInBytes);
4660 }
4661 } else {
4662 assert (CompressedOops::base() == nullptr, "sanity");
4663 }
4664 }
4665
4666 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) {
4667 assert (UseCompressedOops, "should only be used for compressed headers");
4668 assert (Universe::heap() != nullptr, "java heap should be initialized");
4669 // Cannot assert, unverified entry point counts instructions (see .ad file)
4670 // vtableStubs also counts instructions in pd_code_size_limit.
4671 // Also do not verify_oop as this is called by verify_oop.
4672 if (CompressedOops::shift() != 0) {
4673 assert(LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
4674 if (CompressedOops::base() != nullptr) {
4675 add(dst, rheapbase, src, Assembler::LSL, LogMinObjAlignmentInBytes);
4676 } else {
4677 add(dst, zr, src, Assembler::LSL, LogMinObjAlignmentInBytes);
4678 }
4679 } else {
4680 assert (CompressedOops::base() == nullptr, "sanity");
4681 if (dst != src) {
4682 mov(dst, src);
4683 }
4684 }
4685 }
4686
4687 MacroAssembler::KlassDecodeMode MacroAssembler::_klass_decode_mode(KlassDecodeNone);
4688
4689 MacroAssembler::KlassDecodeMode MacroAssembler::klass_decode_mode() {
4690 assert(UseCompressedClassPointers, "not using compressed class pointers");
4691 assert(Metaspace::initialized(), "metaspace not initialized yet");
4692
4693 if (_klass_decode_mode != KlassDecodeNone) {
4694 return _klass_decode_mode;
4695 }
4696
4697 assert(LogKlassAlignmentInBytes == CompressedKlassPointers::shift()
4698 || 0 == CompressedKlassPointers::shift(), "decode alg wrong");
4699
4700 if (CompressedKlassPointers::base() == nullptr) {
4701 return (_klass_decode_mode = KlassDecodeZero);
4702 }
4703
4704 if (operand_valid_for_logical_immediate(
4705 /*is32*/false, (uint64_t)CompressedKlassPointers::base())) {
4706 const uint64_t range_mask =
4707 (1ULL << log2i(CompressedKlassPointers::range())) - 1;
4708 if (((uint64_t)CompressedKlassPointers::base() & range_mask) == 0) {
4709 return (_klass_decode_mode = KlassDecodeXor);
4710 }
4711 }
4712
4713 const uint64_t shifted_base =
4714 (uint64_t)CompressedKlassPointers::base() >> CompressedKlassPointers::shift();
4715 guarantee((shifted_base & 0xffff0000ffffffff) == 0,
4716 "compressed class base bad alignment");
4717
4718 return (_klass_decode_mode = KlassDecodeMovk);
4719 }
4720
4721 void MacroAssembler::encode_klass_not_null(Register dst, Register src) {
4722 switch (klass_decode_mode()) {
4723 case KlassDecodeZero:
4724 if (CompressedKlassPointers::shift() != 0) {
4725 lsr(dst, src, LogKlassAlignmentInBytes);
4726 } else {
4727 if (dst != src) mov(dst, src);
4728 }
4729 break;
4730
4731 case KlassDecodeXor:
4732 if (CompressedKlassPointers::shift() != 0) {
4733 eor(dst, src, (uint64_t)CompressedKlassPointers::base());
4734 lsr(dst, dst, LogKlassAlignmentInBytes);
4735 } else {
4736 eor(dst, src, (uint64_t)CompressedKlassPointers::base());
4737 }
4738 break;
4739
4740 case KlassDecodeMovk:
4741 if (CompressedKlassPointers::shift() != 0) {
4742 ubfx(dst, src, LogKlassAlignmentInBytes, 32);
4743 } else {
4744 movw(dst, src);
4745 }
4746 break;
4747
4748 case KlassDecodeNone:
4749 ShouldNotReachHere();
4750 break;
4751 }
4752 }
4753
4754 void MacroAssembler::encode_klass_not_null(Register r) {
4755 encode_klass_not_null(r, r);
4756 }
4757
4758 void MacroAssembler::decode_klass_not_null(Register dst, Register src) {
4759 assert (UseCompressedClassPointers, "should only be used for compressed headers");
4760
4761 switch (klass_decode_mode()) {
4762 case KlassDecodeZero:
4763 if (CompressedKlassPointers::shift() != 0) {
4764 lsl(dst, src, LogKlassAlignmentInBytes);
4765 } else {
4766 if (dst != src) mov(dst, src);
4767 }
4768 break;
4769
4770 case KlassDecodeXor:
4771 if (CompressedKlassPointers::shift() != 0) {
4772 lsl(dst, src, LogKlassAlignmentInBytes);
4773 eor(dst, dst, (uint64_t)CompressedKlassPointers::base());
4774 } else {
4775 eor(dst, src, (uint64_t)CompressedKlassPointers::base());
4776 }
4777 break;
4778
4779 case KlassDecodeMovk: {
4780 const uint64_t shifted_base =
4781 (uint64_t)CompressedKlassPointers::base() >> CompressedKlassPointers::shift();
4782
4783 if (dst != src) movw(dst, src);
4784 movk(dst, shifted_base >> 32, 32);
4785
4786 if (CompressedKlassPointers::shift() != 0) {
4787 lsl(dst, dst, LogKlassAlignmentInBytes);
4788 }
4789
4790 break;
4791 }
4792
4793 case KlassDecodeNone:
4794 ShouldNotReachHere();
4795 break;
4796 }
4797 }
4798
4799 void MacroAssembler::decode_klass_not_null(Register r) {
4800 decode_klass_not_null(r, r);
4801 }
4802
4803 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) {
4804 #ifdef ASSERT
4805 {
4806 ThreadInVMfromUnknown tiv;
4807 assert (UseCompressedOops, "should only be used for compressed oops");
4808 assert (Universe::heap() != nullptr, "java heap should be initialized");
4809 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
4810 assert(Universe::heap()->is_in(JNIHandles::resolve(obj)), "should be real oop");
4811 }
4812 #endif
4813 int oop_index = oop_recorder()->find_index(obj);
4814 InstructionMark im(this);
4815 RelocationHolder rspec = oop_Relocation::spec(oop_index);
4816 code_section()->relocate(inst_mark(), rspec);
4817 movz(dst, 0xDEAD, 16);
4818 movk(dst, 0xBEEF);
4819 }
4820
4821 void MacroAssembler::set_narrow_klass(Register dst, Klass* k) {
4822 assert (UseCompressedClassPointers, "should only be used for compressed headers");
4823 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
4824 int index = oop_recorder()->find_index(k);
4825 assert(! Universe::heap()->is_in(k), "should not be an oop");
4826
4827 InstructionMark im(this);
4828 RelocationHolder rspec = metadata_Relocation::spec(index);
4829 code_section()->relocate(inst_mark(), rspec);
4830 narrowKlass nk = CompressedKlassPointers::encode(k);
4831 movz(dst, (nk >> 16), 16);
4832 movk(dst, nk & 0xffff);
4833 }
4834
4835 void MacroAssembler::access_load_at(BasicType type, DecoratorSet decorators,
4836 Register dst, Address src,
4837 Register tmp1, Register tmp2) {
4838 BarrierSetAssembler *bs = BarrierSet::barrier_set()->barrier_set_assembler();
4839 decorators = AccessInternal::decorator_fixup(decorators, type);
4840 bool as_raw = (decorators & AS_RAW) != 0;
4841 if (as_raw) {
4842 bs->BarrierSetAssembler::load_at(this, decorators, type, dst, src, tmp1, tmp2);
4843 } else {
4844 bs->load_at(this, decorators, type, dst, src, tmp1, tmp2);
4845 }
4846 }
4847
4848 void MacroAssembler::access_store_at(BasicType type, DecoratorSet decorators,
4849 Address dst, Register val,
4850 Register tmp1, Register tmp2, Register tmp3) {
4851 BarrierSetAssembler *bs = BarrierSet::barrier_set()->barrier_set_assembler();
4852 decorators = AccessInternal::decorator_fixup(decorators, type);
4853 bool as_raw = (decorators & AS_RAW) != 0;
4854 if (as_raw) {
4855 bs->BarrierSetAssembler::store_at(this, decorators, type, dst, val, tmp1, tmp2, tmp3);
4856 } else {
4857 bs->store_at(this, decorators, type, dst, val, tmp1, tmp2, tmp3);
4858 }
4859 }
4860
4861 void MacroAssembler::load_heap_oop(Register dst, Address src, Register tmp1,
4862 Register tmp2, DecoratorSet decorators) {
4863 access_load_at(T_OBJECT, IN_HEAP | decorators, dst, src, tmp1, tmp2);
4864 }
4865
4866 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src, Register tmp1,
4867 Register tmp2, DecoratorSet decorators) {
4868 access_load_at(T_OBJECT, IN_HEAP | IS_NOT_NULL | decorators, dst, src, tmp1, tmp2);
4869 }
4870
4871 void MacroAssembler::store_heap_oop(Address dst, Register val, Register tmp1,
4872 Register tmp2, Register tmp3, DecoratorSet decorators) {
4873 access_store_at(T_OBJECT, IN_HEAP | decorators, dst, val, tmp1, tmp2, tmp3);
4874 }
4875
4876 // Used for storing nulls.
4877 void MacroAssembler::store_heap_oop_null(Address dst) {
4878 access_store_at(T_OBJECT, IN_HEAP, dst, noreg, noreg, noreg, noreg);
4879 }
4880
4881 Address MacroAssembler::allocate_metadata_address(Metadata* obj) {
4882 assert(oop_recorder() != nullptr, "this assembler needs a Recorder");
4883 int index = oop_recorder()->allocate_metadata_index(obj);
4884 RelocationHolder rspec = metadata_Relocation::spec(index);
4885 return Address((address)obj, rspec);
4886 }
4887
4888 // Move an oop into a register.
4889 void MacroAssembler::movoop(Register dst, jobject obj) {
4890 int oop_index;
4891 if (obj == nullptr) {
4892 oop_index = oop_recorder()->allocate_oop_index(obj);
4893 } else {
4894 #ifdef ASSERT
4895 {
4896 ThreadInVMfromUnknown tiv;
4897 assert(Universe::heap()->is_in(JNIHandles::resolve(obj)), "should be real oop");
4898 }
4899 #endif
4900 oop_index = oop_recorder()->find_index(obj);
4901 }
4902 RelocationHolder rspec = oop_Relocation::spec(oop_index);
4903
4904 if (BarrierSet::barrier_set()->barrier_set_assembler()->supports_instruction_patching()) {
4905 mov(dst, Address((address)obj, rspec));
4906 } else {
4907 address dummy = address(uintptr_t(pc()) & -wordSize); // A nearby aligned address
4908 ldr_constant(dst, Address(dummy, rspec));
4909 }
4910
4911 }
4912
4913 // Move a metadata address into a register.
4914 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
4915 int oop_index;
4916 if (obj == nullptr) {
4917 oop_index = oop_recorder()->allocate_metadata_index(obj);
4918 } else {
4919 oop_index = oop_recorder()->find_index(obj);
4920 }
4921 RelocationHolder rspec = metadata_Relocation::spec(oop_index);
4922 mov(dst, Address((address)obj, rspec));
4923 }
4924
4925 Address MacroAssembler::constant_oop_address(jobject obj) {
4926 #ifdef ASSERT
4927 {
4928 ThreadInVMfromUnknown tiv;
4929 assert(oop_recorder() != nullptr, "this assembler needs an OopRecorder");
4930 assert(Universe::heap()->is_in(JNIHandles::resolve(obj)), "not an oop");
4931 }
4932 #endif
4933 int oop_index = oop_recorder()->find_index(obj);
4934 return Address((address)obj, oop_Relocation::spec(oop_index));
4935 }
4936
4937 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
4938 void MacroAssembler::tlab_allocate(Register obj,
4939 Register var_size_in_bytes,
4940 int con_size_in_bytes,
4941 Register t1,
4942 Register t2,
4943 Label& slow_case) {
4944 BarrierSetAssembler *bs = BarrierSet::barrier_set()->barrier_set_assembler();
4945 bs->tlab_allocate(this, obj, var_size_in_bytes, con_size_in_bytes, t1, t2, slow_case);
4946 }
4947
4948 void MacroAssembler::verify_tlab() {
4949 #ifdef ASSERT
4950 if (UseTLAB && VerifyOops) {
4951 Label next, ok;
4952
4953 stp(rscratch2, rscratch1, Address(pre(sp, -16)));
4954
4955 ldr(rscratch2, Address(rthread, in_bytes(JavaThread::tlab_top_offset())));
4956 ldr(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_start_offset())));
4957 cmp(rscratch2, rscratch1);
4958 br(Assembler::HS, next);
4959 STOP("assert(top >= start)");
4960 should_not_reach_here();
4961
4962 bind(next);
4963 ldr(rscratch2, Address(rthread, in_bytes(JavaThread::tlab_end_offset())));
4964 ldr(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_top_offset())));
4965 cmp(rscratch2, rscratch1);
4966 br(Assembler::HS, ok);
4967 STOP("assert(top <= end)");
4968 should_not_reach_here();
4969
4970 bind(ok);
4971 ldp(rscratch2, rscratch1, Address(post(sp, 16)));
4972 }
4973 #endif
4974 }
4975
4976 // Writes to stack successive pages until offset reached to check for
4977 // stack overflow + shadow pages. This clobbers tmp.
4978 void MacroAssembler::bang_stack_size(Register size, Register tmp) {
4979 assert_different_registers(tmp, size, rscratch1);
4980 mov(tmp, sp);
4981 // Bang stack for total size given plus shadow page size.
4982 // Bang one page at a time because large size can bang beyond yellow and
4983 // red zones.
4984 Label loop;
4985 mov(rscratch1, (int)os::vm_page_size());
4986 bind(loop);
4987 lea(tmp, Address(tmp, -(int)os::vm_page_size()));
4988 subsw(size, size, rscratch1);
4989 str(size, Address(tmp));
4990 br(Assembler::GT, loop);
4991
4992 // Bang down shadow pages too.
4993 // At this point, (tmp-0) is the last address touched, so don't
4994 // touch it again. (It was touched as (tmp-pagesize) but then tmp
4995 // was post-decremented.) Skip this address by starting at i=1, and
4996 // touch a few more pages below. N.B. It is important to touch all
4997 // the way down to and including i=StackShadowPages.
4998 for (int i = 0; i < (int)(StackOverflow::stack_shadow_zone_size() / (int)os::vm_page_size()) - 1; i++) {
4999 // this could be any sized move but this is can be a debugging crumb
5000 // so the bigger the better.
5001 lea(tmp, Address(tmp, -(int)os::vm_page_size()));
5002 str(size, Address(tmp));
5003 }
5004 }
5005
5006 // Move the address of the polling page into dest.
5007 void MacroAssembler::get_polling_page(Register dest, relocInfo::relocType rtype) {
5008 ldr(dest, Address(rthread, JavaThread::polling_page_offset()));
5009 }
5010
5011 // Read the polling page. The address of the polling page must
5012 // already be in r.
5013 address MacroAssembler::read_polling_page(Register r, relocInfo::relocType rtype) {
5014 address mark;
5015 {
5016 InstructionMark im(this);
5017 code_section()->relocate(inst_mark(), rtype);
5018 ldrw(zr, Address(r, 0));
5019 mark = inst_mark();
5020 }
5021 verify_cross_modify_fence_not_required();
5022 return mark;
5023 }
5024
5025 void MacroAssembler::adrp(Register reg1, const Address &dest, uint64_t &byte_offset) {
5026 relocInfo::relocType rtype = dest.rspec().reloc()->type();
5027 uint64_t low_page = (uint64_t)CodeCache::low_bound() >> 12;
5028 uint64_t high_page = (uint64_t)(CodeCache::high_bound()-1) >> 12;
5029 uint64_t dest_page = (uint64_t)dest.target() >> 12;
5030 int64_t offset_low = dest_page - low_page;
5031 int64_t offset_high = dest_page - high_page;
5032
5033 assert(is_valid_AArch64_address(dest.target()), "bad address");
5034 assert(dest.getMode() == Address::literal, "ADRP must be applied to a literal address");
5035
5036 InstructionMark im(this);
5037 code_section()->relocate(inst_mark(), dest.rspec());
5038 // 8143067: Ensure that the adrp can reach the dest from anywhere within
5039 // the code cache so that if it is relocated we know it will still reach
5040 if (offset_high >= -(1<<20) && offset_low < (1<<20)) {
5041 _adrp(reg1, dest.target());
5042 } else {
5043 uint64_t target = (uint64_t)dest.target();
5044 uint64_t adrp_target
5045 = (target & 0xffffffffULL) | ((uint64_t)pc() & 0xffff00000000ULL);
5046
5047 _adrp(reg1, (address)adrp_target);
5048 movk(reg1, target >> 32, 32);
5049 }
5050 byte_offset = (uint64_t)dest.target() & 0xfff;
5051 }
5052
5053 void MacroAssembler::load_byte_map_base(Register reg) {
5054 CardTable::CardValue* byte_map_base =
5055 ((CardTableBarrierSet*)(BarrierSet::barrier_set()))->card_table()->byte_map_base();
5056
5057 // Strictly speaking the byte_map_base isn't an address at all, and it might
5058 // even be negative. It is thus materialised as a constant.
5059 mov(reg, (uint64_t)byte_map_base);
5060 }
5061
5062 void MacroAssembler::build_frame(int framesize) {
5063 assert(framesize >= 2 * wordSize, "framesize must include space for FP/LR");
5064 assert(framesize % (2*wordSize) == 0, "must preserve 2*wordSize alignment");
5065 protect_return_address();
5066 if (framesize < ((1 << 9) + 2 * wordSize)) {
5067 sub(sp, sp, framesize);
5068 stp(rfp, lr, Address(sp, framesize - 2 * wordSize));
5069 if (PreserveFramePointer) add(rfp, sp, framesize - 2 * wordSize);
5070 } else {
5071 stp(rfp, lr, Address(pre(sp, -2 * wordSize)));
5072 if (PreserveFramePointer) mov(rfp, sp);
5073 if (framesize < ((1 << 12) + 2 * wordSize))
5074 sub(sp, sp, framesize - 2 * wordSize);
5075 else {
5076 mov(rscratch1, framesize - 2 * wordSize);
5077 sub(sp, sp, rscratch1);
5078 }
5079 }
5080 verify_cross_modify_fence_not_required();
5081 }
5082
5083 void MacroAssembler::remove_frame(int framesize) {
5084 assert(framesize >= 2 * wordSize, "framesize must include space for FP/LR");
5085 assert(framesize % (2*wordSize) == 0, "must preserve 2*wordSize alignment");
5086 if (framesize < ((1 << 9) + 2 * wordSize)) {
5087 ldp(rfp, lr, Address(sp, framesize - 2 * wordSize));
5088 add(sp, sp, framesize);
5089 } else {
5090 if (framesize < ((1 << 12) + 2 * wordSize))
5091 add(sp, sp, framesize - 2 * wordSize);
5092 else {
5093 mov(rscratch1, framesize - 2 * wordSize);
5094 add(sp, sp, rscratch1);
5095 }
5096 ldp(rfp, lr, Address(post(sp, 2 * wordSize)));
5097 }
5098 authenticate_return_address();
5099 }
5100
5101
5102 // This method counts leading positive bytes (highest bit not set) in provided byte array
5103 address MacroAssembler::count_positives(Register ary1, Register len, Register result) {
5104 // Simple and most common case of aligned small array which is not at the
5105 // end of memory page is placed here. All other cases are in stub.
5106 Label LOOP, END, STUB, STUB_LONG, SET_RESULT, DONE;
5107 const uint64_t UPPER_BIT_MASK=0x8080808080808080;
5108 assert_different_registers(ary1, len, result);
5109
5110 mov(result, len);
5111 cmpw(len, 0);
5112 br(LE, DONE);
5113 cmpw(len, 4 * wordSize);
5114 br(GE, STUB_LONG); // size > 32 then go to stub
5115
5116 int shift = 64 - exact_log2(os::vm_page_size());
5117 lsl(rscratch1, ary1, shift);
5118 mov(rscratch2, (size_t)(4 * wordSize) << shift);
5119 adds(rscratch2, rscratch1, rscratch2); // At end of page?
5120 br(CS, STUB); // at the end of page then go to stub
5121 subs(len, len, wordSize);
5122 br(LT, END);
5123
5124 BIND(LOOP);
5125 ldr(rscratch1, Address(post(ary1, wordSize)));
5126 tst(rscratch1, UPPER_BIT_MASK);
5127 br(NE, SET_RESULT);
5128 subs(len, len, wordSize);
5129 br(GE, LOOP);
5130 cmpw(len, -wordSize);
5131 br(EQ, DONE);
5132
5133 BIND(END);
5134 ldr(rscratch1, Address(ary1));
5135 sub(rscratch2, zr, len, LSL, 3); // LSL 3 is to get bits from bytes
5136 lslv(rscratch1, rscratch1, rscratch2);
5137 tst(rscratch1, UPPER_BIT_MASK);
5138 br(NE, SET_RESULT);
5139 b(DONE);
5140
5141 BIND(STUB);
5142 RuntimeAddress count_pos = RuntimeAddress(StubRoutines::aarch64::count_positives());
5143 assert(count_pos.target() != nullptr, "count_positives stub has not been generated");
5144 address tpc1 = trampoline_call(count_pos);
5145 if (tpc1 == nullptr) {
5146 DEBUG_ONLY(reset_labels(STUB_LONG, SET_RESULT, DONE));
5147 postcond(pc() == badAddress);
5148 return nullptr;
5149 }
5150 b(DONE);
5151
5152 BIND(STUB_LONG);
5153 RuntimeAddress count_pos_long = RuntimeAddress(StubRoutines::aarch64::count_positives_long());
5154 assert(count_pos_long.target() != nullptr, "count_positives_long stub has not been generated");
5155 address tpc2 = trampoline_call(count_pos_long);
5156 if (tpc2 == nullptr) {
5157 DEBUG_ONLY(reset_labels(SET_RESULT, DONE));
5158 postcond(pc() == badAddress);
5159 return nullptr;
5160 }
5161 b(DONE);
5162
5163 BIND(SET_RESULT);
5164
5165 add(len, len, wordSize);
5166 sub(result, result, len);
5167
5168 BIND(DONE);
5169 postcond(pc() != badAddress);
5170 return pc();
5171 }
5172
5173 // Clobbers: rscratch1, rscratch2, rflags
5174 // May also clobber v0-v7 when (!UseSimpleArrayEquals && UseSIMDForArrayEquals)
5175 address MacroAssembler::arrays_equals(Register a1, Register a2, Register tmp3,
5176 Register tmp4, Register tmp5, Register result,
5177 Register cnt1, int elem_size) {
5178 Label DONE, SAME;
5179 Register tmp1 = rscratch1;
5180 Register tmp2 = rscratch2;
5181 Register cnt2 = tmp2; // cnt2 only used in array length compare
5182 int elem_per_word = wordSize/elem_size;
5183 int log_elem_size = exact_log2(elem_size);
5184 int length_offset = arrayOopDesc::length_offset_in_bytes();
5185 int base_offset
5186 = arrayOopDesc::base_offset_in_bytes(elem_size == 2 ? T_CHAR : T_BYTE);
5187 int stubBytesThreshold = 3 * 64 + (UseSIMDForArrayEquals ? 0 : 16);
5188
5189 assert(elem_size == 1 || elem_size == 2, "must be char or byte");
5190 assert_different_registers(a1, a2, result, cnt1, rscratch1, rscratch2);
5191
5192 #ifndef PRODUCT
5193 {
5194 const char kind = (elem_size == 2) ? 'U' : 'L';
5195 char comment[64];
5196 snprintf(comment, sizeof comment, "array_equals%c{", kind);
5197 BLOCK_COMMENT(comment);
5198 }
5199 #endif
5200
5201 // if (a1 == a2)
5202 // return true;
5203 cmpoop(a1, a2); // May have read barriers for a1 and a2.
5204 br(EQ, SAME);
5205
5206 if (UseSimpleArrayEquals) {
5207 Label NEXT_WORD, SHORT, TAIL03, TAIL01, A_MIGHT_BE_NULL, A_IS_NOT_NULL;
5208 // if (a1 == nullptr || a2 == nullptr)
5209 // return false;
5210 // a1 & a2 == 0 means (some-pointer is null) or
5211 // (very-rare-or-even-probably-impossible-pointer-values)
5212 // so, we can save one branch in most cases
5213 tst(a1, a2);
5214 mov(result, false);
5215 br(EQ, A_MIGHT_BE_NULL);
5216 // if (a1.length != a2.length)
5217 // return false;
5218 bind(A_IS_NOT_NULL);
5219 ldrw(cnt1, Address(a1, length_offset));
5220 ldrw(cnt2, Address(a2, length_offset));
5221 eorw(tmp5, cnt1, cnt2);
5222 cbnzw(tmp5, DONE);
5223 lea(a1, Address(a1, base_offset));
5224 lea(a2, Address(a2, base_offset));
5225 // Check for short strings, i.e. smaller than wordSize.
5226 subs(cnt1, cnt1, elem_per_word);
5227 br(Assembler::LT, SHORT);
5228 // Main 8 byte comparison loop.
5229 bind(NEXT_WORD); {
5230 ldr(tmp1, Address(post(a1, wordSize)));
5231 ldr(tmp2, Address(post(a2, wordSize)));
5232 subs(cnt1, cnt1, elem_per_word);
5233 eor(tmp5, tmp1, tmp2);
5234 cbnz(tmp5, DONE);
5235 } br(GT, NEXT_WORD);
5236 // Last longword. In the case where length == 4 we compare the
5237 // same longword twice, but that's still faster than another
5238 // conditional branch.
5239 // cnt1 could be 0, -1, -2, -3, -4 for chars; -4 only happens when
5240 // length == 4.
5241 if (log_elem_size > 0)
5242 lsl(cnt1, cnt1, log_elem_size);
5243 ldr(tmp3, Address(a1, cnt1));
5244 ldr(tmp4, Address(a2, cnt1));
5245 eor(tmp5, tmp3, tmp4);
5246 cbnz(tmp5, DONE);
5247 b(SAME);
5248 bind(A_MIGHT_BE_NULL);
5249 // in case both a1 and a2 are not-null, proceed with loads
5250 cbz(a1, DONE);
5251 cbz(a2, DONE);
5252 b(A_IS_NOT_NULL);
5253 bind(SHORT);
5254
5255 tbz(cnt1, 2 - log_elem_size, TAIL03); // 0-7 bytes left.
5256 {
5257 ldrw(tmp1, Address(post(a1, 4)));
5258 ldrw(tmp2, Address(post(a2, 4)));
5259 eorw(tmp5, tmp1, tmp2);
5260 cbnzw(tmp5, DONE);
5261 }
5262 bind(TAIL03);
5263 tbz(cnt1, 1 - log_elem_size, TAIL01); // 0-3 bytes left.
5264 {
5265 ldrh(tmp3, Address(post(a1, 2)));
5266 ldrh(tmp4, Address(post(a2, 2)));
5267 eorw(tmp5, tmp3, tmp4);
5268 cbnzw(tmp5, DONE);
5269 }
5270 bind(TAIL01);
5271 if (elem_size == 1) { // Only needed when comparing byte arrays.
5272 tbz(cnt1, 0, SAME); // 0-1 bytes left.
5273 {
5274 ldrb(tmp1, a1);
5275 ldrb(tmp2, a2);
5276 eorw(tmp5, tmp1, tmp2);
5277 cbnzw(tmp5, DONE);
5278 }
5279 }
5280 } else {
5281 Label NEXT_DWORD, SHORT, TAIL, TAIL2, STUB,
5282 CSET_EQ, LAST_CHECK;
5283 mov(result, false);
5284 cbz(a1, DONE);
5285 ldrw(cnt1, Address(a1, length_offset));
5286 cbz(a2, DONE);
5287 ldrw(cnt2, Address(a2, length_offset));
5288 // on most CPUs a2 is still "locked"(surprisingly) in ldrw and it's
5289 // faster to perform another branch before comparing a1 and a2
5290 cmp(cnt1, (u1)elem_per_word);
5291 br(LE, SHORT); // short or same
5292 ldr(tmp3, Address(pre(a1, base_offset)));
5293 subs(zr, cnt1, stubBytesThreshold);
5294 br(GE, STUB);
5295 ldr(tmp4, Address(pre(a2, base_offset)));
5296 sub(tmp5, zr, cnt1, LSL, 3 + log_elem_size);
5297 cmp(cnt2, cnt1);
5298 br(NE, DONE);
5299
5300 // Main 16 byte comparison loop with 2 exits
5301 bind(NEXT_DWORD); {
5302 ldr(tmp1, Address(pre(a1, wordSize)));
5303 ldr(tmp2, Address(pre(a2, wordSize)));
5304 subs(cnt1, cnt1, 2 * elem_per_word);
5305 br(LE, TAIL);
5306 eor(tmp4, tmp3, tmp4);
5307 cbnz(tmp4, DONE);
5308 ldr(tmp3, Address(pre(a1, wordSize)));
5309 ldr(tmp4, Address(pre(a2, wordSize)));
5310 cmp(cnt1, (u1)elem_per_word);
5311 br(LE, TAIL2);
5312 cmp(tmp1, tmp2);
5313 } br(EQ, NEXT_DWORD);
5314 b(DONE);
5315
5316 bind(TAIL);
5317 eor(tmp4, tmp3, tmp4);
5318 eor(tmp2, tmp1, tmp2);
5319 lslv(tmp2, tmp2, tmp5);
5320 orr(tmp5, tmp4, tmp2);
5321 cmp(tmp5, zr);
5322 b(CSET_EQ);
5323
5324 bind(TAIL2);
5325 eor(tmp2, tmp1, tmp2);
5326 cbnz(tmp2, DONE);
5327 b(LAST_CHECK);
5328
5329 bind(STUB);
5330 ldr(tmp4, Address(pre(a2, base_offset)));
5331 cmp(cnt2, cnt1);
5332 br(NE, DONE);
5333 if (elem_size == 2) { // convert to byte counter
5334 lsl(cnt1, cnt1, 1);
5335 }
5336 eor(tmp5, tmp3, tmp4);
5337 cbnz(tmp5, DONE);
5338 RuntimeAddress stub = RuntimeAddress(StubRoutines::aarch64::large_array_equals());
5339 assert(stub.target() != nullptr, "array_equals_long stub has not been generated");
5340 address tpc = trampoline_call(stub);
5341 if (tpc == nullptr) {
5342 DEBUG_ONLY(reset_labels(SHORT, LAST_CHECK, CSET_EQ, SAME, DONE));
5343 postcond(pc() == badAddress);
5344 return nullptr;
5345 }
5346 b(DONE);
5347
5348 // (a1 != null && a2 == null) || (a1 != null && a2 != null && a1 == a2)
5349 // so, if a2 == null => return false(0), else return true, so we can return a2
5350 mov(result, a2);
5351 b(DONE);
5352 bind(SHORT);
5353 cmp(cnt2, cnt1);
5354 br(NE, DONE);
5355 cbz(cnt1, SAME);
5356 sub(tmp5, zr, cnt1, LSL, 3 + log_elem_size);
5357 ldr(tmp3, Address(a1, base_offset));
5358 ldr(tmp4, Address(a2, base_offset));
5359 bind(LAST_CHECK);
5360 eor(tmp4, tmp3, tmp4);
5361 lslv(tmp5, tmp4, tmp5);
5362 cmp(tmp5, zr);
5363 bind(CSET_EQ);
5364 cset(result, EQ);
5365 b(DONE);
5366 }
5367
5368 bind(SAME);
5369 mov(result, true);
5370 // That's it.
5371 bind(DONE);
5372
5373 BLOCK_COMMENT("} array_equals");
5374 postcond(pc() != badAddress);
5375 return pc();
5376 }
5377
5378 // Compare Strings
5379
5380 // For Strings we're passed the address of the first characters in a1
5381 // and a2 and the length in cnt1.
5382 // elem_size is the element size in bytes: either 1 or 2.
5383 // There are two implementations. For arrays >= 8 bytes, all
5384 // comparisons (including the final one, which may overlap) are
5385 // performed 8 bytes at a time. For strings < 8 bytes, we compare a
5386 // halfword, then a short, and then a byte.
5387
5388 void MacroAssembler::string_equals(Register a1, Register a2,
5389 Register result, Register cnt1, int elem_size)
5390 {
5391 Label SAME, DONE, SHORT, NEXT_WORD;
5392 Register tmp1 = rscratch1;
5393 Register tmp2 = rscratch2;
5394 Register cnt2 = tmp2; // cnt2 only used in array length compare
5395
5396 assert(elem_size == 1 || elem_size == 2, "must be 2 or 1 byte");
5397 assert_different_registers(a1, a2, result, cnt1, rscratch1, rscratch2);
5398
5399 #ifndef PRODUCT
5400 {
5401 const char kind = (elem_size == 2) ? 'U' : 'L';
5402 char comment[64];
5403 snprintf(comment, sizeof comment, "{string_equals%c", kind);
5404 BLOCK_COMMENT(comment);
5405 }
5406 #endif
5407
5408 mov(result, false);
5409
5410 // Check for short strings, i.e. smaller than wordSize.
5411 subs(cnt1, cnt1, wordSize);
5412 br(Assembler::LT, SHORT);
5413 // Main 8 byte comparison loop.
5414 bind(NEXT_WORD); {
5415 ldr(tmp1, Address(post(a1, wordSize)));
5416 ldr(tmp2, Address(post(a2, wordSize)));
5417 subs(cnt1, cnt1, wordSize);
5418 eor(tmp1, tmp1, tmp2);
5419 cbnz(tmp1, DONE);
5420 } br(GT, NEXT_WORD);
5421 // Last longword. In the case where length == 4 we compare the
5422 // same longword twice, but that's still faster than another
5423 // conditional branch.
5424 // cnt1 could be 0, -1, -2, -3, -4 for chars; -4 only happens when
5425 // length == 4.
5426 ldr(tmp1, Address(a1, cnt1));
5427 ldr(tmp2, Address(a2, cnt1));
5428 eor(tmp2, tmp1, tmp2);
5429 cbnz(tmp2, DONE);
5430 b(SAME);
5431
5432 bind(SHORT);
5433 Label TAIL03, TAIL01;
5434
5435 tbz(cnt1, 2, TAIL03); // 0-7 bytes left.
5436 {
5437 ldrw(tmp1, Address(post(a1, 4)));
5438 ldrw(tmp2, Address(post(a2, 4)));
5439 eorw(tmp1, tmp1, tmp2);
5440 cbnzw(tmp1, DONE);
5441 }
5442 bind(TAIL03);
5443 tbz(cnt1, 1, TAIL01); // 0-3 bytes left.
5444 {
5445 ldrh(tmp1, Address(post(a1, 2)));
5446 ldrh(tmp2, Address(post(a2, 2)));
5447 eorw(tmp1, tmp1, tmp2);
5448 cbnzw(tmp1, DONE);
5449 }
5450 bind(TAIL01);
5451 if (elem_size == 1) { // Only needed when comparing 1-byte elements
5452 tbz(cnt1, 0, SAME); // 0-1 bytes left.
5453 {
5454 ldrb(tmp1, a1);
5455 ldrb(tmp2, a2);
5456 eorw(tmp1, tmp1, tmp2);
5457 cbnzw(tmp1, DONE);
5458 }
5459 }
5460 // Arrays are equal.
5461 bind(SAME);
5462 mov(result, true);
5463
5464 // That's it.
5465 bind(DONE);
5466 BLOCK_COMMENT("} string_equals");
5467 }
5468
5469
5470 // The size of the blocks erased by the zero_blocks stub. We must
5471 // handle anything smaller than this ourselves in zero_words().
5472 const int MacroAssembler::zero_words_block_size = 8;
5473
5474 // zero_words() is used by C2 ClearArray patterns and by
5475 // C1_MacroAssembler. It is as small as possible, handling small word
5476 // counts locally and delegating anything larger to the zero_blocks
5477 // stub. It is expanded many times in compiled code, so it is
5478 // important to keep it short.
5479
5480 // ptr: Address of a buffer to be zeroed.
5481 // cnt: Count in HeapWords.
5482 //
5483 // ptr, cnt, rscratch1, and rscratch2 are clobbered.
5484 address MacroAssembler::zero_words(Register ptr, Register cnt)
5485 {
5486 assert(is_power_of_2(zero_words_block_size), "adjust this");
5487
5488 BLOCK_COMMENT("zero_words {");
5489 assert(ptr == r10 && cnt == r11, "mismatch in register usage");
5490 RuntimeAddress zero_blocks = RuntimeAddress(StubRoutines::aarch64::zero_blocks());
5491 assert(zero_blocks.target() != nullptr, "zero_blocks stub has not been generated");
5492
5493 subs(rscratch1, cnt, zero_words_block_size);
5494 Label around;
5495 br(LO, around);
5496 {
5497 RuntimeAddress zero_blocks = RuntimeAddress(StubRoutines::aarch64::zero_blocks());
5498 assert(zero_blocks.target() != nullptr, "zero_blocks stub has not been generated");
5499 // Make sure this is a C2 compilation. C1 allocates space only for
5500 // trampoline stubs generated by Call LIR ops, and in any case it
5501 // makes sense for a C1 compilation task to proceed as quickly as
5502 // possible.
5503 CompileTask* task;
5504 if (StubRoutines::aarch64::complete()
5505 && Thread::current()->is_Compiler_thread()
5506 && (task = ciEnv::current()->task())
5507 && is_c2_compile(task->comp_level())) {
5508 address tpc = trampoline_call(zero_blocks);
5509 if (tpc == nullptr) {
5510 DEBUG_ONLY(reset_labels(around));
5511 return nullptr;
5512 }
5513 } else {
5514 far_call(zero_blocks);
5515 }
5516 }
5517 bind(around);
5518
5519 // We have a few words left to do. zero_blocks has adjusted r10 and r11
5520 // for us.
5521 for (int i = zero_words_block_size >> 1; i > 1; i >>= 1) {
5522 Label l;
5523 tbz(cnt, exact_log2(i), l);
5524 for (int j = 0; j < i; j += 2) {
5525 stp(zr, zr, post(ptr, 2 * BytesPerWord));
5526 }
5527 bind(l);
5528 }
5529 {
5530 Label l;
5531 tbz(cnt, 0, l);
5532 str(zr, Address(ptr));
5533 bind(l);
5534 }
5535
5536 BLOCK_COMMENT("} zero_words");
5537 return pc();
5538 }
5539
5540 // base: Address of a buffer to be zeroed, 8 bytes aligned.
5541 // cnt: Immediate count in HeapWords.
5542 //
5543 // r10, r11, rscratch1, and rscratch2 are clobbered.
5544 address MacroAssembler::zero_words(Register base, uint64_t cnt)
5545 {
5546 assert(wordSize <= BlockZeroingLowLimit,
5547 "increase BlockZeroingLowLimit");
5548 address result = nullptr;
5549 if (cnt <= (uint64_t)BlockZeroingLowLimit / BytesPerWord) {
5550 #ifndef PRODUCT
5551 {
5552 char buf[64];
5553 snprintf(buf, sizeof buf, "zero_words (count = %" PRIu64 ") {", cnt);
5554 BLOCK_COMMENT(buf);
5555 }
5556 #endif
5557 if (cnt >= 16) {
5558 uint64_t loops = cnt/16;
5559 if (loops > 1) {
5560 mov(rscratch2, loops - 1);
5561 }
5562 {
5563 Label loop;
5564 bind(loop);
5565 for (int i = 0; i < 16; i += 2) {
5566 stp(zr, zr, Address(base, i * BytesPerWord));
5567 }
5568 add(base, base, 16 * BytesPerWord);
5569 if (loops > 1) {
5570 subs(rscratch2, rscratch2, 1);
5571 br(GE, loop);
5572 }
5573 }
5574 }
5575 cnt %= 16;
5576 int i = cnt & 1; // store any odd word to start
5577 if (i) str(zr, Address(base));
5578 for (; i < (int)cnt; i += 2) {
5579 stp(zr, zr, Address(base, i * wordSize));
5580 }
5581 BLOCK_COMMENT("} zero_words");
5582 result = pc();
5583 } else {
5584 mov(r10, base); mov(r11, cnt);
5585 result = zero_words(r10, r11);
5586 }
5587 return result;
5588 }
5589
5590 // Zero blocks of memory by using DC ZVA.
5591 //
5592 // Aligns the base address first sufficiently for DC ZVA, then uses
5593 // DC ZVA repeatedly for every full block. cnt is the size to be
5594 // zeroed in HeapWords. Returns the count of words left to be zeroed
5595 // in cnt.
5596 //
5597 // NOTE: This is intended to be used in the zero_blocks() stub. If
5598 // you want to use it elsewhere, note that cnt must be >= 2*zva_length.
5599 void MacroAssembler::zero_dcache_blocks(Register base, Register cnt) {
5600 Register tmp = rscratch1;
5601 Register tmp2 = rscratch2;
5602 int zva_length = VM_Version::zva_length();
5603 Label initial_table_end, loop_zva;
5604 Label fini;
5605
5606 // Base must be 16 byte aligned. If not just return and let caller handle it
5607 tst(base, 0x0f);
5608 br(Assembler::NE, fini);
5609 // Align base with ZVA length.
5610 neg(tmp, base);
5611 andr(tmp, tmp, zva_length - 1);
5612
5613 // tmp: the number of bytes to be filled to align the base with ZVA length.
5614 add(base, base, tmp);
5615 sub(cnt, cnt, tmp, Assembler::ASR, 3);
5616 adr(tmp2, initial_table_end);
5617 sub(tmp2, tmp2, tmp, Assembler::LSR, 2);
5618 br(tmp2);
5619
5620 for (int i = -zva_length + 16; i < 0; i += 16)
5621 stp(zr, zr, Address(base, i));
5622 bind(initial_table_end);
5623
5624 sub(cnt, cnt, zva_length >> 3);
5625 bind(loop_zva);
5626 dc(Assembler::ZVA, base);
5627 subs(cnt, cnt, zva_length >> 3);
5628 add(base, base, zva_length);
5629 br(Assembler::GE, loop_zva);
5630 add(cnt, cnt, zva_length >> 3); // count not zeroed by DC ZVA
5631 bind(fini);
5632 }
5633
5634 // base: Address of a buffer to be filled, 8 bytes aligned.
5635 // cnt: Count in 8-byte unit.
5636 // value: Value to be filled with.
5637 // base will point to the end of the buffer after filling.
5638 void MacroAssembler::fill_words(Register base, Register cnt, Register value)
5639 {
5640 // Algorithm:
5641 //
5642 // if (cnt == 0) {
5643 // return;
5644 // }
5645 // if ((p & 8) != 0) {
5646 // *p++ = v;
5647 // }
5648 //
5649 // scratch1 = cnt & 14;
5650 // cnt -= scratch1;
5651 // p += scratch1;
5652 // switch (scratch1 / 2) {
5653 // do {
5654 // cnt -= 16;
5655 // p[-16] = v;
5656 // p[-15] = v;
5657 // case 7:
5658 // p[-14] = v;
5659 // p[-13] = v;
5660 // case 6:
5661 // p[-12] = v;
5662 // p[-11] = v;
5663 // // ...
5664 // case 1:
5665 // p[-2] = v;
5666 // p[-1] = v;
5667 // case 0:
5668 // p += 16;
5669 // } while (cnt);
5670 // }
5671 // if ((cnt & 1) == 1) {
5672 // *p++ = v;
5673 // }
5674
5675 assert_different_registers(base, cnt, value, rscratch1, rscratch2);
5676
5677 Label fini, skip, entry, loop;
5678 const int unroll = 8; // Number of stp instructions we'll unroll
5679
5680 cbz(cnt, fini);
5681 tbz(base, 3, skip);
5682 str(value, Address(post(base, 8)));
5683 sub(cnt, cnt, 1);
5684 bind(skip);
5685
5686 andr(rscratch1, cnt, (unroll-1) * 2);
5687 sub(cnt, cnt, rscratch1);
5688 add(base, base, rscratch1, Assembler::LSL, 3);
5689 adr(rscratch2, entry);
5690 sub(rscratch2, rscratch2, rscratch1, Assembler::LSL, 1);
5691 br(rscratch2);
5692
5693 bind(loop);
5694 add(base, base, unroll * 16);
5695 for (int i = -unroll; i < 0; i++)
5696 stp(value, value, Address(base, i * 16));
5697 bind(entry);
5698 subs(cnt, cnt, unroll * 2);
5699 br(Assembler::GE, loop);
5700
5701 tbz(cnt, 0, fini);
5702 str(value, Address(post(base, 8)));
5703 bind(fini);
5704 }
5705
5706 // Intrinsic for
5707 //
5708 // - sun/nio/cs/ISO_8859_1$Encoder.implEncodeISOArray
5709 // return the number of characters copied.
5710 // - java/lang/StringUTF16.compress
5711 // return zero (0) if copy fails, otherwise 'len'.
5712 //
5713 // This version always returns the number of characters copied, and does not
5714 // clobber the 'len' register. A successful copy will complete with the post-
5715 // condition: 'res' == 'len', while an unsuccessful copy will exit with the
5716 // post-condition: 0 <= 'res' < 'len'.
5717 //
5718 // NOTE: Attempts to use 'ld2' (and 'umaxv' in the ISO part) has proven to
5719 // degrade performance (on Ampere Altra - Neoverse N1), to an extent
5720 // beyond the acceptable, even though the footprint would be smaller.
5721 // Using 'umaxv' in the ASCII-case comes with a small penalty but does
5722 // avoid additional bloat.
5723 //
5724 // Clobbers: src, dst, res, rscratch1, rscratch2, rflags
5725 void MacroAssembler::encode_iso_array(Register src, Register dst,
5726 Register len, Register res, bool ascii,
5727 FloatRegister vtmp0, FloatRegister vtmp1,
5728 FloatRegister vtmp2, FloatRegister vtmp3,
5729 FloatRegister vtmp4, FloatRegister vtmp5)
5730 {
5731 Register cnt = res;
5732 Register max = rscratch1;
5733 Register chk = rscratch2;
5734
5735 prfm(Address(src), PLDL1STRM);
5736 movw(cnt, len);
5737
5738 #define ASCII(insn) do { if (ascii) { insn; } } while (0)
5739
5740 Label LOOP_32, DONE_32, FAIL_32;
5741
5742 BIND(LOOP_32);
5743 {
5744 cmpw(cnt, 32);
5745 br(LT, DONE_32);
5746 ld1(vtmp0, vtmp1, vtmp2, vtmp3, T8H, Address(post(src, 64)));
5747 // Extract lower bytes.
5748 FloatRegister vlo0 = vtmp4;
5749 FloatRegister vlo1 = vtmp5;
5750 uzp1(vlo0, T16B, vtmp0, vtmp1);
5751 uzp1(vlo1, T16B, vtmp2, vtmp3);
5752 // Merge bits...
5753 orr(vtmp0, T16B, vtmp0, vtmp1);
5754 orr(vtmp2, T16B, vtmp2, vtmp3);
5755 // Extract merged upper bytes.
5756 FloatRegister vhix = vtmp0;
5757 uzp2(vhix, T16B, vtmp0, vtmp2);
5758 // ISO-check on hi-parts (all zero).
5759 // ASCII-check on lo-parts (no sign).
5760 FloatRegister vlox = vtmp1; // Merge lower bytes.
5761 ASCII(orr(vlox, T16B, vlo0, vlo1));
5762 umov(chk, vhix, D, 1); ASCII(cm(LT, vlox, T16B, vlox));
5763 fmovd(max, vhix); ASCII(umaxv(vlox, T16B, vlox));
5764 orr(chk, chk, max); ASCII(umov(max, vlox, B, 0));
5765 ASCII(orr(chk, chk, max));
5766 cbnz(chk, FAIL_32);
5767 subw(cnt, cnt, 32);
5768 st1(vlo0, vlo1, T16B, Address(post(dst, 32)));
5769 b(LOOP_32);
5770 }
5771 BIND(FAIL_32);
5772 sub(src, src, 64);
5773 BIND(DONE_32);
5774
5775 Label LOOP_8, SKIP_8;
5776
5777 BIND(LOOP_8);
5778 {
5779 cmpw(cnt, 8);
5780 br(LT, SKIP_8);
5781 FloatRegister vhi = vtmp0;
5782 FloatRegister vlo = vtmp1;
5783 ld1(vtmp3, T8H, src);
5784 uzp1(vlo, T16B, vtmp3, vtmp3);
5785 uzp2(vhi, T16B, vtmp3, vtmp3);
5786 // ISO-check on hi-parts (all zero).
5787 // ASCII-check on lo-parts (no sign).
5788 ASCII(cm(LT, vtmp2, T16B, vlo));
5789 fmovd(chk, vhi); ASCII(umaxv(vtmp2, T16B, vtmp2));
5790 ASCII(umov(max, vtmp2, B, 0));
5791 ASCII(orr(chk, chk, max));
5792 cbnz(chk, SKIP_8);
5793
5794 strd(vlo, Address(post(dst, 8)));
5795 subw(cnt, cnt, 8);
5796 add(src, src, 16);
5797 b(LOOP_8);
5798 }
5799 BIND(SKIP_8);
5800
5801 #undef ASCII
5802
5803 Label LOOP, DONE;
5804
5805 cbz(cnt, DONE);
5806 BIND(LOOP);
5807 {
5808 Register chr = rscratch1;
5809 ldrh(chr, Address(post(src, 2)));
5810 tst(chr, ascii ? 0xff80 : 0xff00);
5811 br(NE, DONE);
5812 strb(chr, Address(post(dst, 1)));
5813 subs(cnt, cnt, 1);
5814 br(GT, LOOP);
5815 }
5816 BIND(DONE);
5817 // Return index where we stopped.
5818 subw(res, len, cnt);
5819 }
5820
5821 // Inflate byte[] array to char[].
5822 // Clobbers: src, dst, len, rflags, rscratch1, v0-v6
5823 address MacroAssembler::byte_array_inflate(Register src, Register dst, Register len,
5824 FloatRegister vtmp1, FloatRegister vtmp2,
5825 FloatRegister vtmp3, Register tmp4) {
5826 Label big, done, after_init, to_stub;
5827
5828 assert_different_registers(src, dst, len, tmp4, rscratch1);
5829
5830 fmovd(vtmp1, 0.0);
5831 lsrw(tmp4, len, 3);
5832 bind(after_init);
5833 cbnzw(tmp4, big);
5834 // Short string: less than 8 bytes.
5835 {
5836 Label loop, tiny;
5837
5838 cmpw(len, 4);
5839 br(LT, tiny);
5840 // Use SIMD to do 4 bytes.
5841 ldrs(vtmp2, post(src, 4));
5842 zip1(vtmp3, T8B, vtmp2, vtmp1);
5843 subw(len, len, 4);
5844 strd(vtmp3, post(dst, 8));
5845
5846 cbzw(len, done);
5847
5848 // Do the remaining bytes by steam.
5849 bind(loop);
5850 ldrb(tmp4, post(src, 1));
5851 strh(tmp4, post(dst, 2));
5852 subw(len, len, 1);
5853
5854 bind(tiny);
5855 cbnz(len, loop);
5856
5857 b(done);
5858 }
5859
5860 if (SoftwarePrefetchHintDistance >= 0) {
5861 bind(to_stub);
5862 RuntimeAddress stub = RuntimeAddress(StubRoutines::aarch64::large_byte_array_inflate());
5863 assert(stub.target() != nullptr, "large_byte_array_inflate stub has not been generated");
5864 address tpc = trampoline_call(stub);
5865 if (tpc == nullptr) {
5866 DEBUG_ONLY(reset_labels(big, done));
5867 postcond(pc() == badAddress);
5868 return nullptr;
5869 }
5870 b(after_init);
5871 }
5872
5873 // Unpack the bytes 8 at a time.
5874 bind(big);
5875 {
5876 Label loop, around, loop_last, loop_start;
5877
5878 if (SoftwarePrefetchHintDistance >= 0) {
5879 const int large_loop_threshold = (64 + 16)/8;
5880 ldrd(vtmp2, post(src, 8));
5881 andw(len, len, 7);
5882 cmp(tmp4, (u1)large_loop_threshold);
5883 br(GE, to_stub);
5884 b(loop_start);
5885
5886 bind(loop);
5887 ldrd(vtmp2, post(src, 8));
5888 bind(loop_start);
5889 subs(tmp4, tmp4, 1);
5890 br(EQ, loop_last);
5891 zip1(vtmp2, T16B, vtmp2, vtmp1);
5892 ldrd(vtmp3, post(src, 8));
5893 st1(vtmp2, T8H, post(dst, 16));
5894 subs(tmp4, tmp4, 1);
5895 zip1(vtmp3, T16B, vtmp3, vtmp1);
5896 st1(vtmp3, T8H, post(dst, 16));
5897 br(NE, loop);
5898 b(around);
5899 bind(loop_last);
5900 zip1(vtmp2, T16B, vtmp2, vtmp1);
5901 st1(vtmp2, T8H, post(dst, 16));
5902 bind(around);
5903 cbz(len, done);
5904 } else {
5905 andw(len, len, 7);
5906 bind(loop);
5907 ldrd(vtmp2, post(src, 8));
5908 sub(tmp4, tmp4, 1);
5909 zip1(vtmp3, T16B, vtmp2, vtmp1);
5910 st1(vtmp3, T8H, post(dst, 16));
5911 cbnz(tmp4, loop);
5912 }
5913 }
5914
5915 // Do the tail of up to 8 bytes.
5916 add(src, src, len);
5917 ldrd(vtmp3, Address(src, -8));
5918 add(dst, dst, len, ext::uxtw, 1);
5919 zip1(vtmp3, T16B, vtmp3, vtmp1);
5920 strq(vtmp3, Address(dst, -16));
5921
5922 bind(done);
5923 postcond(pc() != badAddress);
5924 return pc();
5925 }
5926
5927 // Compress char[] array to byte[].
5928 void MacroAssembler::char_array_compress(Register src, Register dst, Register len,
5929 Register res,
5930 FloatRegister tmp0, FloatRegister tmp1,
5931 FloatRegister tmp2, FloatRegister tmp3,
5932 FloatRegister tmp4, FloatRegister tmp5) {
5933 encode_iso_array(src, dst, len, res, false, tmp0, tmp1, tmp2, tmp3, tmp4, tmp5);
5934 // Adjust result: res == len ? len : 0
5935 cmp(len, res);
5936 csel(res, res, zr, EQ);
5937 }
5938
5939 // java.math.round(double a)
5940 // Returns the closest long to the argument, with ties rounding to
5941 // positive infinity. This requires some fiddling for corner
5942 // cases. We take care to avoid double rounding in e.g. (jlong)(a + 0.5).
5943 void MacroAssembler::java_round_double(Register dst, FloatRegister src,
5944 FloatRegister ftmp) {
5945 Label DONE;
5946 BLOCK_COMMENT("java_round_double: { ");
5947 fmovd(rscratch1, src);
5948 // Use RoundToNearestTiesAway unless src small and -ve.
5949 fcvtasd(dst, src);
5950 // Test if src >= 0 || abs(src) >= 0x1.0p52
5951 eor(rscratch1, rscratch1, UCONST64(1) << 63); // flip sign bit
5952 mov(rscratch2, julong_cast(0x1.0p52));
5953 cmp(rscratch1, rscratch2);
5954 br(HS, DONE); {
5955 // src < 0 && abs(src) < 0x1.0p52
5956 // src may have a fractional part, so add 0.5
5957 fmovd(ftmp, 0.5);
5958 faddd(ftmp, src, ftmp);
5959 // Convert double to jlong, use RoundTowardsNegative
5960 fcvtmsd(dst, ftmp);
5961 }
5962 bind(DONE);
5963 BLOCK_COMMENT("} java_round_double");
5964 }
5965
5966 void MacroAssembler::java_round_float(Register dst, FloatRegister src,
5967 FloatRegister ftmp) {
5968 Label DONE;
5969 BLOCK_COMMENT("java_round_float: { ");
5970 fmovs(rscratch1, src);
5971 // Use RoundToNearestTiesAway unless src small and -ve.
5972 fcvtassw(dst, src);
5973 // Test if src >= 0 || abs(src) >= 0x1.0p23
5974 eor(rscratch1, rscratch1, 0x80000000); // flip sign bit
5975 mov(rscratch2, jint_cast(0x1.0p23f));
5976 cmp(rscratch1, rscratch2);
5977 br(HS, DONE); {
5978 // src < 0 && |src| < 0x1.0p23
5979 // src may have a fractional part, so add 0.5
5980 fmovs(ftmp, 0.5f);
5981 fadds(ftmp, src, ftmp);
5982 // Convert float to jint, use RoundTowardsNegative
5983 fcvtmssw(dst, ftmp);
5984 }
5985 bind(DONE);
5986 BLOCK_COMMENT("} java_round_float");
5987 }
5988
5989 // get_thread() can be called anywhere inside generated code so we
5990 // need to save whatever non-callee save context might get clobbered
5991 // by the call to JavaThread::aarch64_get_thread_helper() or, indeed,
5992 // the call setup code.
5993 //
5994 // On Linux, aarch64_get_thread_helper() clobbers only r0, r1, and flags.
5995 // On other systems, the helper is a usual C function.
5996 //
5997 void MacroAssembler::get_thread(Register dst) {
5998 RegSet saved_regs =
5999 LINUX_ONLY(RegSet::range(r0, r1) + lr - dst)
6000 NOT_LINUX (RegSet::range(r0, r17) + lr - dst);
6001
6002 protect_return_address();
6003 push(saved_regs, sp);
6004
6005 mov(lr, CAST_FROM_FN_PTR(address, JavaThread::aarch64_get_thread_helper));
6006 blr(lr);
6007 if (dst != c_rarg0) {
6008 mov(dst, c_rarg0);
6009 }
6010
6011 pop(saved_regs, sp);
6012 authenticate_return_address();
6013 }
6014
6015 void MacroAssembler::cache_wb(Address line) {
6016 assert(line.getMode() == Address::base_plus_offset, "mode should be base_plus_offset");
6017 assert(line.index() == noreg, "index should be noreg");
6018 assert(line.offset() == 0, "offset should be 0");
6019 // would like to assert this
6020 // assert(line._ext.shift == 0, "shift should be zero");
6021 if (VM_Version::supports_dcpop()) {
6022 // writeback using clear virtual address to point of persistence
6023 dc(Assembler::CVAP, line.base());
6024 } else {
6025 // no need to generate anything as Unsafe.writebackMemory should
6026 // never invoke this stub
6027 }
6028 }
6029
6030 void MacroAssembler::cache_wbsync(bool is_pre) {
6031 // we only need a barrier post sync
6032 if (!is_pre) {
6033 membar(Assembler::AnyAny);
6034 }
6035 }
6036
6037 void MacroAssembler::verify_sve_vector_length(Register tmp) {
6038 // Make sure that native code does not change SVE vector length.
6039 if (!UseSVE) return;
6040 Label verify_ok;
6041 movw(tmp, zr);
6042 sve_inc(tmp, B);
6043 subsw(zr, tmp, VM_Version::get_initial_sve_vector_length());
6044 br(EQ, verify_ok);
6045 stop("Error: SVE vector length has changed since jvm startup");
6046 bind(verify_ok);
6047 }
6048
6049 void MacroAssembler::verify_ptrue() {
6050 Label verify_ok;
6051 if (!UseSVE) {
6052 return;
6053 }
6054 sve_cntp(rscratch1, B, ptrue, ptrue); // get true elements count.
6055 sve_dec(rscratch1, B);
6056 cbz(rscratch1, verify_ok);
6057 stop("Error: the preserved predicate register (p7) elements are not all true");
6058 bind(verify_ok);
6059 }
6060
6061 void MacroAssembler::safepoint_isb() {
6062 isb();
6063 #ifndef PRODUCT
6064 if (VerifyCrossModifyFence) {
6065 // Clear the thread state.
6066 strb(zr, Address(rthread, in_bytes(JavaThread::requires_cross_modify_fence_offset())));
6067 }
6068 #endif
6069 }
6070
6071 #ifndef PRODUCT
6072 void MacroAssembler::verify_cross_modify_fence_not_required() {
6073 if (VerifyCrossModifyFence) {
6074 // Check if thread needs a cross modify fence.
6075 ldrb(rscratch1, Address(rthread, in_bytes(JavaThread::requires_cross_modify_fence_offset())));
6076 Label fence_not_required;
6077 cbz(rscratch1, fence_not_required);
6078 // If it does then fail.
6079 lea(rscratch1, CAST_FROM_FN_PTR(address, JavaThread::verify_cross_modify_fence_failure));
6080 mov(c_rarg0, rthread);
6081 blr(rscratch1);
6082 bind(fence_not_required);
6083 }
6084 }
6085 #endif
6086
6087 void MacroAssembler::spin_wait() {
6088 for (int i = 0; i < VM_Version::spin_wait_desc().inst_count(); ++i) {
6089 switch (VM_Version::spin_wait_desc().inst()) {
6090 case SpinWait::NOP:
6091 nop();
6092 break;
6093 case SpinWait::ISB:
6094 isb();
6095 break;
6096 case SpinWait::YIELD:
6097 yield();
6098 break;
6099 default:
6100 ShouldNotReachHere();
6101 }
6102 }
6103 }
6104
6105 // Stack frame creation/removal
6106
6107 void MacroAssembler::enter(bool strip_ret_addr) {
6108 if (strip_ret_addr) {
6109 // Addresses can only be signed once. If there are multiple nested frames being created
6110 // in the same function, then the return address needs stripping first.
6111 strip_return_address();
6112 }
6113 protect_return_address();
6114 stp(rfp, lr, Address(pre(sp, -2 * wordSize)));
6115 mov(rfp, sp);
6116 }
6117
6118 void MacroAssembler::leave() {
6119 mov(sp, rfp);
6120 ldp(rfp, lr, Address(post(sp, 2 * wordSize)));
6121 authenticate_return_address();
6122 }
6123
6124 // ROP Protection
6125 // Use the AArch64 PAC feature to add ROP protection for generated code. Use whenever creating/
6126 // destroying stack frames or whenever directly loading/storing the LR to memory.
6127 // If ROP protection is not set then these functions are no-ops.
6128 // For more details on PAC see pauth_aarch64.hpp.
6129
6130 // Sign the LR. Use during construction of a stack frame, before storing the LR to memory.
6131 // Uses value zero as the modifier.
6132 //
6133 void MacroAssembler::protect_return_address() {
6134 if (VM_Version::use_rop_protection()) {
6135 check_return_address();
6136 paciaz();
6137 }
6138 }
6139
6140 // Sign the return value in the given register. Use before updating the LR in the existing stack
6141 // frame for the current function.
6142 // Uses value zero as the modifier.
6143 //
6144 void MacroAssembler::protect_return_address(Register return_reg) {
6145 if (VM_Version::use_rop_protection()) {
6146 check_return_address(return_reg);
6147 paciza(return_reg);
6148 }
6149 }
6150
6151 // Authenticate the LR. Use before function return, after restoring FP and loading LR from memory.
6152 // Uses value zero as the modifier.
6153 //
6154 void MacroAssembler::authenticate_return_address() {
6155 if (VM_Version::use_rop_protection()) {
6156 autiaz();
6157 check_return_address();
6158 }
6159 }
6160
6161 // Authenticate the return value in the given register. Use before updating the LR in the existing
6162 // stack frame for the current function.
6163 // Uses value zero as the modifier.
6164 //
6165 void MacroAssembler::authenticate_return_address(Register return_reg) {
6166 if (VM_Version::use_rop_protection()) {
6167 autiza(return_reg);
6168 check_return_address(return_reg);
6169 }
6170 }
6171
6172 // Strip any PAC data from LR without performing any authentication. Use with caution - only if
6173 // there is no guaranteed way of authenticating the LR.
6174 //
6175 void MacroAssembler::strip_return_address() {
6176 if (VM_Version::use_rop_protection()) {
6177 xpaclri();
6178 }
6179 }
6180
6181 #ifndef PRODUCT
6182 // PAC failures can be difficult to debug. After an authentication failure, a segfault will only
6183 // occur when the pointer is used - ie when the program returns to the invalid LR. At this point
6184 // it is difficult to debug back to the callee function.
6185 // This function simply loads from the address in the given register.
6186 // Use directly after authentication to catch authentication failures.
6187 // Also use before signing to check that the pointer is valid and hasn't already been signed.
6188 //
6189 void MacroAssembler::check_return_address(Register return_reg) {
6190 if (VM_Version::use_rop_protection()) {
6191 ldr(zr, Address(return_reg));
6192 }
6193 }
6194 #endif
6195
6196 // The java_calling_convention describes stack locations as ideal slots on
6197 // a frame with no abi restrictions. Since we must observe abi restrictions
6198 // (like the placement of the register window) the slots must be biased by
6199 // the following value.
6200 static int reg2offset_in(VMReg r) {
6201 // Account for saved rfp and lr
6202 // This should really be in_preserve_stack_slots
6203 return (r->reg2stack() + 4) * VMRegImpl::stack_slot_size;
6204 }
6205
6206 static int reg2offset_out(VMReg r) {
6207 return (r->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size;
6208 }
6209
6210 // On 64bit we will store integer like items to the stack as
6211 // 64bits items (AArch64 ABI) even though java would only store
6212 // 32bits for a parameter. On 32bit it will simply be 32bits
6213 // So this routine will do 32->32 on 32bit and 32->64 on 64bit
6214 void MacroAssembler::move32_64(VMRegPair src, VMRegPair dst, Register tmp) {
6215 if (src.first()->is_stack()) {
6216 if (dst.first()->is_stack()) {
6217 // stack to stack
6218 ldr(tmp, Address(rfp, reg2offset_in(src.first())));
6219 str(tmp, Address(sp, reg2offset_out(dst.first())));
6220 } else {
6221 // stack to reg
6222 ldrsw(dst.first()->as_Register(), Address(rfp, reg2offset_in(src.first())));
6223 }
6224 } else if (dst.first()->is_stack()) {
6225 // reg to stack
6226 str(src.first()->as_Register(), Address(sp, reg2offset_out(dst.first())));
6227 } else {
6228 if (dst.first() != src.first()) {
6229 sxtw(dst.first()->as_Register(), src.first()->as_Register());
6230 }
6231 }
6232 }
6233
6234 // An oop arg. Must pass a handle not the oop itself
6235 void MacroAssembler::object_move(
6236 OopMap* map,
6237 int oop_handle_offset,
6238 int framesize_in_slots,
6239 VMRegPair src,
6240 VMRegPair dst,
6241 bool is_receiver,
6242 int* receiver_offset) {
6243
6244 // must pass a handle. First figure out the location we use as a handle
6245
6246 Register rHandle = dst.first()->is_stack() ? rscratch2 : dst.first()->as_Register();
6247
6248 // See if oop is null if it is we need no handle
6249
6250 if (src.first()->is_stack()) {
6251
6252 // Oop is already on the stack as an argument
6253 int offset_in_older_frame = src.first()->reg2stack() + SharedRuntime::out_preserve_stack_slots();
6254 map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + framesize_in_slots));
6255 if (is_receiver) {
6256 *receiver_offset = (offset_in_older_frame + framesize_in_slots) * VMRegImpl::stack_slot_size;
6257 }
6258
6259 ldr(rscratch1, Address(rfp, reg2offset_in(src.first())));
6260 lea(rHandle, Address(rfp, reg2offset_in(src.first())));
6261 // conditionally move a null
6262 cmp(rscratch1, zr);
6263 csel(rHandle, zr, rHandle, Assembler::EQ);
6264 } else {
6265
6266 // Oop is in an a register we must store it to the space we reserve
6267 // on the stack for oop_handles and pass a handle if oop is non-null
6268
6269 const Register rOop = src.first()->as_Register();
6270 int oop_slot;
6271 if (rOop == j_rarg0)
6272 oop_slot = 0;
6273 else if (rOop == j_rarg1)
6274 oop_slot = 1;
6275 else if (rOop == j_rarg2)
6276 oop_slot = 2;
6277 else if (rOop == j_rarg3)
6278 oop_slot = 3;
6279 else if (rOop == j_rarg4)
6280 oop_slot = 4;
6281 else if (rOop == j_rarg5)
6282 oop_slot = 5;
6283 else if (rOop == j_rarg6)
6284 oop_slot = 6;
6285 else {
6286 assert(rOop == j_rarg7, "wrong register");
6287 oop_slot = 7;
6288 }
6289
6290 oop_slot = oop_slot * VMRegImpl::slots_per_word + oop_handle_offset;
6291 int offset = oop_slot*VMRegImpl::stack_slot_size;
6292
6293 map->set_oop(VMRegImpl::stack2reg(oop_slot));
6294 // Store oop in handle area, may be null
6295 str(rOop, Address(sp, offset));
6296 if (is_receiver) {
6297 *receiver_offset = offset;
6298 }
6299
6300 cmp(rOop, zr);
6301 lea(rHandle, Address(sp, offset));
6302 // conditionally move a null
6303 csel(rHandle, zr, rHandle, Assembler::EQ);
6304 }
6305
6306 // If arg is on the stack then place it otherwise it is already in correct reg.
6307 if (dst.first()->is_stack()) {
6308 str(rHandle, Address(sp, reg2offset_out(dst.first())));
6309 }
6310 }
6311
6312 // A float arg may have to do float reg int reg conversion
6313 void MacroAssembler::float_move(VMRegPair src, VMRegPair dst, Register tmp) {
6314 if (src.first()->is_stack()) {
6315 if (dst.first()->is_stack()) {
6316 ldrw(tmp, Address(rfp, reg2offset_in(src.first())));
6317 strw(tmp, Address(sp, reg2offset_out(dst.first())));
6318 } else {
6319 ldrs(dst.first()->as_FloatRegister(), Address(rfp, reg2offset_in(src.first())));
6320 }
6321 } else if (src.first() != dst.first()) {
6322 if (src.is_single_phys_reg() && dst.is_single_phys_reg())
6323 fmovs(dst.first()->as_FloatRegister(), src.first()->as_FloatRegister());
6324 else
6325 strs(src.first()->as_FloatRegister(), Address(sp, reg2offset_out(dst.first())));
6326 }
6327 }
6328
6329 // A long move
6330 void MacroAssembler::long_move(VMRegPair src, VMRegPair dst, Register tmp) {
6331 if (src.first()->is_stack()) {
6332 if (dst.first()->is_stack()) {
6333 // stack to stack
6334 ldr(tmp, Address(rfp, reg2offset_in(src.first())));
6335 str(tmp, Address(sp, reg2offset_out(dst.first())));
6336 } else {
6337 // stack to reg
6338 ldr(dst.first()->as_Register(), Address(rfp, reg2offset_in(src.first())));
6339 }
6340 } else if (dst.first()->is_stack()) {
6341 // reg to stack
6342 // Do we really have to sign extend???
6343 // __ movslq(src.first()->as_Register(), src.first()->as_Register());
6344 str(src.first()->as_Register(), Address(sp, reg2offset_out(dst.first())));
6345 } else {
6346 if (dst.first() != src.first()) {
6347 mov(dst.first()->as_Register(), src.first()->as_Register());
6348 }
6349 }
6350 }
6351
6352
6353 // A double move
6354 void MacroAssembler::double_move(VMRegPair src, VMRegPair dst, Register tmp) {
6355 if (src.first()->is_stack()) {
6356 if (dst.first()->is_stack()) {
6357 ldr(tmp, Address(rfp, reg2offset_in(src.first())));
6358 str(tmp, Address(sp, reg2offset_out(dst.first())));
6359 } else {
6360 ldrd(dst.first()->as_FloatRegister(), Address(rfp, reg2offset_in(src.first())));
6361 }
6362 } else if (src.first() != dst.first()) {
6363 if (src.is_single_phys_reg() && dst.is_single_phys_reg())
6364 fmovd(dst.first()->as_FloatRegister(), src.first()->as_FloatRegister());
6365 else
6366 strd(src.first()->as_FloatRegister(), Address(sp, reg2offset_out(dst.first())));
6367 }
6368 }
6369
6370 // Implements lightweight-locking.
6371 //
6372 // - obj: the object to be locked
6373 // - t1, t2, t3: temporary registers, will be destroyed
6374 // - slow: branched to if locking fails, absolute offset may larger than 32KB (imm14 encoding).
6375 void MacroAssembler::lightweight_lock(Register obj, Register t1, Register t2, Register t3, Label& slow) {
6376 assert(LockingMode == LM_LIGHTWEIGHT, "only used with new lightweight locking");
6377 assert_different_registers(obj, t1, t2, t3, rscratch1);
6378
6379 Label push;
6380 const Register top = t1;
6381 const Register mark = t2;
6382 const Register t = t3;
6383
6384 // Preload the markWord. It is important that this is the first
6385 // instruction emitted as it is part of C1's null check semantics.
6386 ldr(mark, Address(obj, oopDesc::mark_offset_in_bytes()));
6387
6388 // Check if the lock-stack is full.
6389 ldrw(top, Address(rthread, JavaThread::lock_stack_top_offset()));
6390 cmpw(top, (unsigned)LockStack::end_offset());
6391 br(Assembler::GE, slow);
6392
6393 // Check for recursion.
6394 subw(t, top, oopSize);
6395 ldr(t, Address(rthread, t));
6396 cmp(obj, t);
6397 br(Assembler::EQ, push);
6398
6399 // Check header for monitor (0b10).
6400 tst(mark, markWord::monitor_value);
6401 br(Assembler::NE, slow);
6402
6403 // Try to lock. Transition lock bits 0b01 => 0b00
6404 assert(oopDesc::mark_offset_in_bytes() == 0, "required to avoid lea");
6405 orr(mark, mark, markWord::unlocked_value);
6406 eor(t, mark, markWord::unlocked_value);
6407 cmpxchg(/*addr*/ obj, /*expected*/ mark, /*new*/ t, Assembler::xword,
6408 /*acquire*/ true, /*release*/ false, /*weak*/ false, noreg);
6409 br(Assembler::NE, slow);
6410
6411 bind(push);
6412 // After successful lock, push object on lock-stack.
6413 str(obj, Address(rthread, top));
6414 addw(top, top, oopSize);
6415 strw(top, Address(rthread, JavaThread::lock_stack_top_offset()));
6416 }
6417
6418 // Implements lightweight-unlocking.
6419 //
6420 // - obj: the object to be unlocked
6421 // - t1, t2, t3: temporary registers
6422 // - slow: branched to if unlocking fails, absolute offset may larger than 32KB (imm14 encoding).
6423 void MacroAssembler::lightweight_unlock(Register obj, Register t1, Register t2, Register t3, Label& slow) {
6424 assert(LockingMode == LM_LIGHTWEIGHT, "only used with new lightweight locking");
6425 // cmpxchg clobbers rscratch1.
6426 assert_different_registers(obj, t1, t2, t3, rscratch1);
6427
6428 #ifdef ASSERT
6429 {
6430 // Check for lock-stack underflow.
6431 Label stack_ok;
6432 ldrw(t1, Address(rthread, JavaThread::lock_stack_top_offset()));
6433 cmpw(t1, (unsigned)LockStack::start_offset());
6434 br(Assembler::GE, stack_ok);
6435 STOP("Lock-stack underflow");
6436 bind(stack_ok);
6437 }
6438 #endif
6439
6440 Label unlocked, push_and_slow;
6441 const Register top = t1;
6442 const Register mark = t2;
6443 const Register t = t3;
6444
6445 // Check if obj is top of lock-stack.
6446 ldrw(top, Address(rthread, JavaThread::lock_stack_top_offset()));
6447 subw(top, top, oopSize);
6448 ldr(t, Address(rthread, top));
6449 cmp(obj, t);
6450 br(Assembler::NE, slow);
6451
6452 // Pop lock-stack.
6453 DEBUG_ONLY(str(zr, Address(rthread, top));)
6454 strw(top, Address(rthread, JavaThread::lock_stack_top_offset()));
6455
6456 // Check if recursive.
6457 subw(t, top, oopSize);
6458 ldr(t, Address(rthread, t));
6459 cmp(obj, t);
6460 br(Assembler::EQ, unlocked);
6461
6462 // Not recursive. Check header for monitor (0b10).
6463 ldr(mark, Address(obj, oopDesc::mark_offset_in_bytes()));
6464 tbnz(mark, log2i_exact(markWord::monitor_value), push_and_slow);
6465
6466 #ifdef ASSERT
6467 // Check header not unlocked (0b01).
6468 Label not_unlocked;
6469 tbz(mark, log2i_exact(markWord::unlocked_value), not_unlocked);
6470 stop("lightweight_unlock already unlocked");
6471 bind(not_unlocked);
6472 #endif
6473
6474 // Try to unlock. Transition lock bits 0b00 => 0b01
6475 assert(oopDesc::mark_offset_in_bytes() == 0, "required to avoid lea");
6476 orr(t, mark, markWord::unlocked_value);
6477 cmpxchg(obj, mark, t, Assembler::xword,
6478 /*acquire*/ false, /*release*/ true, /*weak*/ false, noreg);
6479 br(Assembler::EQ, unlocked);
6480
6481 bind(push_and_slow);
6482 // Restore lock-stack and handle the unlock in runtime.
6483 DEBUG_ONLY(str(obj, Address(rthread, top));)
6484 addw(top, top, oopSize);
6485 strw(top, Address(rthread, JavaThread::lock_stack_top_offset()));
6486 b(slow);
6487
6488 bind(unlocked);
6489 }