1 /*
2 * Copyright (c) 1997, 2023, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2014, 2021, Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #ifndef CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
27 #define CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
28
29 #include "asm/assembler.inline.hpp"
30 #include "code/vmreg.hpp"
31 #include "metaprogramming/enableIf.hpp"
32 #include "oops/compressedOops.hpp"
33 #include "runtime/vm_version.hpp"
34 #include "utilities/powerOfTwo.hpp"
35
36 class OopMap;
37
38 // MacroAssembler extends Assembler by frequently used macros.
39 //
40 // Instructions for which a 'better' code sequence exists depending
41 // on arguments should also go in here.
42
43 class MacroAssembler: public Assembler {
44 friend class LIR_Assembler;
45
46 public:
47 using Assembler::mov;
48 using Assembler::movi;
49
50 protected:
51
52 // Support for VM calls
53 //
54 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
55 // may customize this version by overriding it for its purposes (e.g., to save/restore
56 // additional registers when doing a VM call).
57 virtual void call_VM_leaf_base(
58 address entry_point, // the entry point
59 int number_of_arguments, // the number of arguments to pop after the call
60 Label *retaddr = nullptr
61 );
62
63 virtual void call_VM_leaf_base(
64 address entry_point, // the entry point
65 int number_of_arguments, // the number of arguments to pop after the call
66 Label &retaddr) {
67 call_VM_leaf_base(entry_point, number_of_arguments, &retaddr);
68 }
69
70 // This is the base routine called by the different versions of call_VM. The interpreter
71 // may customize this version by overriding it for its purposes (e.g., to save/restore
72 // additional registers when doing a VM call).
73 //
74 // If no java_thread register is specified (noreg) than rthread will be used instead. call_VM_base
75 // returns the register which contains the thread upon return. If a thread register has been
76 // specified, the return value will correspond to that register. If no last_java_sp is specified
77 // (noreg) than rsp will be used instead.
78 virtual void call_VM_base( // returns the register containing the thread upon return
79 Register oop_result, // where an oop-result ends up if any; use noreg otherwise
80 Register java_thread, // the thread if computed before ; use noreg otherwise
81 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise
82 address entry_point, // the entry point
83 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call
84 bool check_exceptions // whether to check for pending exceptions after return
85 );
86
87 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
88
89 enum KlassDecodeMode {
90 KlassDecodeNone,
91 KlassDecodeZero,
92 KlassDecodeXor,
93 KlassDecodeMovk
94 };
95
96 KlassDecodeMode klass_decode_mode();
97
98 private:
99 static KlassDecodeMode _klass_decode_mode;
100
101 public:
102 MacroAssembler(CodeBuffer* code) : Assembler(code) {}
103
104 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
105 // The implementation is only non-empty for the InterpreterMacroAssembler,
106 // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
107 virtual void check_and_handle_popframe(Register java_thread);
108 virtual void check_and_handle_earlyret(Register java_thread);
109
110 void safepoint_poll(Label& slow_path, bool at_return, bool acquire, bool in_nmethod, Register tmp = rscratch1);
111 void rt_call(address dest, Register tmp = rscratch1);
112
113 // Load Effective Address
114 void lea(Register r, const Address &a) {
115 InstructionMark im(this);
116 a.lea(this, r);
117 }
118
119 /* Sometimes we get misaligned loads and stores, usually from Unsafe
120 accesses, and these can exceed the offset range. */
121 Address legitimize_address(const Address &a, int size, Register scratch) {
122 if (a.getMode() == Address::base_plus_offset) {
123 if (! Address::offset_ok_for_immed(a.offset(), exact_log2(size))) {
124 block_comment("legitimize_address {");
125 lea(scratch, a);
126 block_comment("} legitimize_address");
127 return Address(scratch);
128 }
129 }
130 return a;
131 }
132
133 void addmw(Address a, Register incr, Register scratch) {
134 ldrw(scratch, a);
135 addw(scratch, scratch, incr);
136 strw(scratch, a);
137 }
138
139 // Add constant to memory word
140 void addmw(Address a, int imm, Register scratch) {
141 ldrw(scratch, a);
142 if (imm > 0)
143 addw(scratch, scratch, (unsigned)imm);
144 else
145 subw(scratch, scratch, (unsigned)-imm);
146 strw(scratch, a);
147 }
148
149 void bind(Label& L) {
150 Assembler::bind(L);
151 code()->clear_last_insn();
152 }
153
154 void membar(Membar_mask_bits order_constraint);
155
156 using Assembler::ldr;
157 using Assembler::str;
158 using Assembler::ldrw;
159 using Assembler::strw;
160
161 void ldr(Register Rx, const Address &adr);
162 void ldrw(Register Rw, const Address &adr);
163 void str(Register Rx, const Address &adr);
164 void strw(Register Rx, const Address &adr);
165
166 // Frame creation and destruction shared between JITs.
167 void build_frame(int framesize);
168 void remove_frame(int framesize);
169
170 virtual void _call_Unimplemented(address call_site) {
171 mov(rscratch2, call_site);
172 }
173
174 // Microsoft's MSVC team thinks that the __FUNCSIG__ is approximately (sympathy for calling conventions) equivalent to __PRETTY_FUNCTION__
175 // Also, from Clang patch: "It is very similar to GCC's PRETTY_FUNCTION, except it prints the calling convention."
176 // https://reviews.llvm.org/D3311
177
178 #ifdef _WIN64
179 #define call_Unimplemented() _call_Unimplemented((address)__FUNCSIG__)
180 #else
181 #define call_Unimplemented() _call_Unimplemented((address)__PRETTY_FUNCTION__)
182 #endif
183
184 // aliases defined in AARCH64 spec
185
186 template<class T>
187 inline void cmpw(Register Rd, T imm) { subsw(zr, Rd, imm); }
188
189 inline void cmp(Register Rd, unsigned char imm8) { subs(zr, Rd, imm8); }
190 inline void cmp(Register Rd, unsigned imm) = delete;
191
192 template<class T>
193 inline void cmnw(Register Rd, T imm) { addsw(zr, Rd, imm); }
194
195 inline void cmn(Register Rd, unsigned char imm8) { adds(zr, Rd, imm8); }
196 inline void cmn(Register Rd, unsigned imm) = delete;
197
198 void cset(Register Rd, Assembler::Condition cond) {
199 csinc(Rd, zr, zr, ~cond);
200 }
201 void csetw(Register Rd, Assembler::Condition cond) {
202 csincw(Rd, zr, zr, ~cond);
203 }
204
205 void cneg(Register Rd, Register Rn, Assembler::Condition cond) {
206 csneg(Rd, Rn, Rn, ~cond);
207 }
208 void cnegw(Register Rd, Register Rn, Assembler::Condition cond) {
209 csnegw(Rd, Rn, Rn, ~cond);
210 }
211
212 inline void movw(Register Rd, Register Rn) {
213 if (Rd == sp || Rn == sp) {
214 Assembler::addw(Rd, Rn, 0U);
215 } else {
216 orrw(Rd, zr, Rn);
217 }
218 }
219 inline void mov(Register Rd, Register Rn) {
220 assert(Rd != r31_sp && Rn != r31_sp, "should be");
221 if (Rd == Rn) {
222 } else if (Rd == sp || Rn == sp) {
223 Assembler::add(Rd, Rn, 0U);
224 } else {
225 orr(Rd, zr, Rn);
226 }
227 }
228
229 inline void moviw(Register Rd, unsigned imm) { orrw(Rd, zr, imm); }
230 inline void movi(Register Rd, unsigned imm) { orr(Rd, zr, imm); }
231
232 inline void tstw(Register Rd, Register Rn) { andsw(zr, Rd, Rn); }
233 inline void tst(Register Rd, Register Rn) { ands(zr, Rd, Rn); }
234
235 inline void tstw(Register Rd, uint64_t imm) { andsw(zr, Rd, imm); }
236 inline void tst(Register Rd, uint64_t imm) { ands(zr, Rd, imm); }
237
238 inline void bfiw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
239 bfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
240 }
241 inline void bfi(Register Rd, Register Rn, unsigned lsb, unsigned width) {
242 bfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
243 }
244
245 inline void bfxilw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
246 bfmw(Rd, Rn, lsb, (lsb + width - 1));
247 }
248 inline void bfxil(Register Rd, Register Rn, unsigned lsb, unsigned width) {
249 bfm(Rd, Rn, lsb , (lsb + width - 1));
250 }
251
252 inline void sbfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
253 sbfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
254 }
255 inline void sbfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) {
256 sbfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
257 }
258
259 inline void sbfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
260 sbfmw(Rd, Rn, lsb, (lsb + width - 1));
261 }
262 inline void sbfx(Register Rd, Register Rn, unsigned lsb, unsigned width) {
263 sbfm(Rd, Rn, lsb , (lsb + width - 1));
264 }
265
266 inline void ubfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
267 ubfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
268 }
269 inline void ubfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) {
270 ubfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
271 }
272
273 inline void ubfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
274 ubfmw(Rd, Rn, lsb, (lsb + width - 1));
275 }
276 inline void ubfx(Register Rd, Register Rn, unsigned lsb, unsigned width) {
277 ubfm(Rd, Rn, lsb , (lsb + width - 1));
278 }
279
280 inline void asrw(Register Rd, Register Rn, unsigned imm) {
281 sbfmw(Rd, Rn, imm, 31);
282 }
283
284 inline void asr(Register Rd, Register Rn, unsigned imm) {
285 sbfm(Rd, Rn, imm, 63);
286 }
287
288 inline void lslw(Register Rd, Register Rn, unsigned imm) {
289 ubfmw(Rd, Rn, ((32 - imm) & 31), (31 - imm));
290 }
291
292 inline void lsl(Register Rd, Register Rn, unsigned imm) {
293 ubfm(Rd, Rn, ((64 - imm) & 63), (63 - imm));
294 }
295
296 inline void lsrw(Register Rd, Register Rn, unsigned imm) {
297 ubfmw(Rd, Rn, imm, 31);
298 }
299
300 inline void lsr(Register Rd, Register Rn, unsigned imm) {
301 ubfm(Rd, Rn, imm, 63);
302 }
303
304 inline void rorw(Register Rd, Register Rn, unsigned imm) {
305 extrw(Rd, Rn, Rn, imm);
306 }
307
308 inline void ror(Register Rd, Register Rn, unsigned imm) {
309 extr(Rd, Rn, Rn, imm);
310 }
311
312 inline void sxtbw(Register Rd, Register Rn) {
313 sbfmw(Rd, Rn, 0, 7);
314 }
315 inline void sxthw(Register Rd, Register Rn) {
316 sbfmw(Rd, Rn, 0, 15);
317 }
318 inline void sxtb(Register Rd, Register Rn) {
319 sbfm(Rd, Rn, 0, 7);
320 }
321 inline void sxth(Register Rd, Register Rn) {
322 sbfm(Rd, Rn, 0, 15);
323 }
324 inline void sxtw(Register Rd, Register Rn) {
325 sbfm(Rd, Rn, 0, 31);
326 }
327
328 inline void uxtbw(Register Rd, Register Rn) {
329 ubfmw(Rd, Rn, 0, 7);
330 }
331 inline void uxthw(Register Rd, Register Rn) {
332 ubfmw(Rd, Rn, 0, 15);
333 }
334 inline void uxtb(Register Rd, Register Rn) {
335 ubfm(Rd, Rn, 0, 7);
336 }
337 inline void uxth(Register Rd, Register Rn) {
338 ubfm(Rd, Rn, 0, 15);
339 }
340 inline void uxtw(Register Rd, Register Rn) {
341 ubfm(Rd, Rn, 0, 31);
342 }
343
344 inline void cmnw(Register Rn, Register Rm) {
345 addsw(zr, Rn, Rm);
346 }
347 inline void cmn(Register Rn, Register Rm) {
348 adds(zr, Rn, Rm);
349 }
350
351 inline void cmpw(Register Rn, Register Rm) {
352 subsw(zr, Rn, Rm);
353 }
354 inline void cmp(Register Rn, Register Rm) {
355 subs(zr, Rn, Rm);
356 }
357
358 inline void negw(Register Rd, Register Rn) {
359 subw(Rd, zr, Rn);
360 }
361
362 inline void neg(Register Rd, Register Rn) {
363 sub(Rd, zr, Rn);
364 }
365
366 inline void negsw(Register Rd, Register Rn) {
367 subsw(Rd, zr, Rn);
368 }
369
370 inline void negs(Register Rd, Register Rn) {
371 subs(Rd, zr, Rn);
372 }
373
374 inline void cmnw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
375 addsw(zr, Rn, Rm, kind, shift);
376 }
377 inline void cmn(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
378 adds(zr, Rn, Rm, kind, shift);
379 }
380
381 inline void cmpw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
382 subsw(zr, Rn, Rm, kind, shift);
383 }
384 inline void cmp(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
385 subs(zr, Rn, Rm, kind, shift);
386 }
387
388 inline void negw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
389 subw(Rd, zr, Rn, kind, shift);
390 }
391
392 inline void neg(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
393 sub(Rd, zr, Rn, kind, shift);
394 }
395
396 inline void negsw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
397 subsw(Rd, zr, Rn, kind, shift);
398 }
399
400 inline void negs(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
401 subs(Rd, zr, Rn, kind, shift);
402 }
403
404 inline void mnegw(Register Rd, Register Rn, Register Rm) {
405 msubw(Rd, Rn, Rm, zr);
406 }
407 inline void mneg(Register Rd, Register Rn, Register Rm) {
408 msub(Rd, Rn, Rm, zr);
409 }
410
411 inline void mulw(Register Rd, Register Rn, Register Rm) {
412 maddw(Rd, Rn, Rm, zr);
413 }
414 inline void mul(Register Rd, Register Rn, Register Rm) {
415 madd(Rd, Rn, Rm, zr);
416 }
417
418 inline void smnegl(Register Rd, Register Rn, Register Rm) {
419 smsubl(Rd, Rn, Rm, zr);
420 }
421 inline void smull(Register Rd, Register Rn, Register Rm) {
422 smaddl(Rd, Rn, Rm, zr);
423 }
424
425 inline void umnegl(Register Rd, Register Rn, Register Rm) {
426 umsubl(Rd, Rn, Rm, zr);
427 }
428 inline void umull(Register Rd, Register Rn, Register Rm) {
429 umaddl(Rd, Rn, Rm, zr);
430 }
431
432 #define WRAP(INSN) \
433 void INSN(Register Rd, Register Rn, Register Rm, Register Ra) { \
434 if (VM_Version::supports_a53mac() && Ra != zr) \
435 nop(); \
436 Assembler::INSN(Rd, Rn, Rm, Ra); \
437 }
438
439 WRAP(madd) WRAP(msub) WRAP(maddw) WRAP(msubw)
440 WRAP(smaddl) WRAP(smsubl) WRAP(umaddl) WRAP(umsubl)
441 #undef WRAP
442
443
444 // macro assembly operations needed for aarch64
445
446 // first two private routines for loading 32 bit or 64 bit constants
447 private:
448
449 void mov_immediate64(Register dst, uint64_t imm64);
450 void mov_immediate32(Register dst, uint32_t imm32);
451
452 int push(unsigned int bitset, Register stack);
453 int pop(unsigned int bitset, Register stack);
454
455 int push_fp(unsigned int bitset, Register stack);
456 int pop_fp(unsigned int bitset, Register stack);
457
458 int push_p(unsigned int bitset, Register stack);
459 int pop_p(unsigned int bitset, Register stack);
460
461 void mov(Register dst, Address a);
462
463 public:
464 void push(RegSet regs, Register stack) { if (regs.bits()) push(regs.bits(), stack); }
465 void pop(RegSet regs, Register stack) { if (regs.bits()) pop(regs.bits(), stack); }
466
467 void push_fp(FloatRegSet regs, Register stack) { if (regs.bits()) push_fp(regs.bits(), stack); }
468 void pop_fp(FloatRegSet regs, Register stack) { if (regs.bits()) pop_fp(regs.bits(), stack); }
469
470 static RegSet call_clobbered_gp_registers();
471
472 void push_p(PRegSet regs, Register stack) { if (regs.bits()) push_p(regs.bits(), stack); }
473 void pop_p(PRegSet regs, Register stack) { if (regs.bits()) pop_p(regs.bits(), stack); }
474
475 // Push and pop everything that might be clobbered by a native
476 // runtime call except rscratch1 and rscratch2. (They are always
477 // scratch, so we don't have to protect them.) Only save the lower
478 // 64 bits of each vector register. Additional registers can be excluded
479 // in a passed RegSet.
480 void push_call_clobbered_registers_except(RegSet exclude);
481 void pop_call_clobbered_registers_except(RegSet exclude);
482
483 void push_call_clobbered_registers() {
484 push_call_clobbered_registers_except(RegSet());
485 }
486 void pop_call_clobbered_registers() {
487 pop_call_clobbered_registers_except(RegSet());
488 }
489
490
491 // now mov instructions for loading absolute addresses and 32 or
492 // 64 bit integers
493
494 inline void mov(Register dst, address addr) { mov_immediate64(dst, (uint64_t)addr); }
495
496 template<typename T, ENABLE_IF(std::is_integral<T>::value)>
497 inline void mov(Register dst, T o) { mov_immediate64(dst, (uint64_t)o); }
498
499 inline void movw(Register dst, uint32_t imm32) { mov_immediate32(dst, imm32); }
500
501 void mov(Register dst, RegisterOrConstant src) {
502 if (src.is_register())
503 mov(dst, src.as_register());
504 else
505 mov(dst, src.as_constant());
506 }
507
508 void movptr(Register r, uintptr_t imm64);
509
510 void mov(FloatRegister Vd, SIMD_Arrangement T, uint64_t imm64);
511
512 void mov(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) {
513 orr(Vd, T, Vn, Vn);
514 }
515
516 void flt_to_flt16(Register dst, FloatRegister src, FloatRegister tmp) {
517 fcvtsh(tmp, src);
518 smov(dst, tmp, H, 0);
519 }
520
521 void flt16_to_flt(FloatRegister dst, Register src, FloatRegister tmp) {
522 mov(tmp, H, 0, src);
523 fcvths(dst, tmp);
524 }
525
526 // Generalized Test Bit And Branch, including a "far" variety which
527 // spans more than 32KiB.
528 void tbr(Condition cond, Register Rt, int bitpos, Label &dest, bool isfar = false) {
529 assert(cond == EQ || cond == NE, "must be");
530
531 if (isfar)
532 cond = ~cond;
533
534 void (Assembler::* branch)(Register Rt, int bitpos, Label &L);
535 if (cond == Assembler::EQ)
536 branch = &Assembler::tbz;
537 else
538 branch = &Assembler::tbnz;
539
540 if (isfar) {
541 Label L;
542 (this->*branch)(Rt, bitpos, L);
543 b(dest);
544 bind(L);
545 } else {
546 (this->*branch)(Rt, bitpos, dest);
547 }
548 }
549
550 // macro instructions for accessing and updating floating point
551 // status register
552 //
553 // FPSR : op1 == 011
554 // CRn == 0100
555 // CRm == 0100
556 // op2 == 001
557
558 inline void get_fpsr(Register reg)
559 {
560 mrs(0b11, 0b0100, 0b0100, 0b001, reg);
561 }
562
563 inline void set_fpsr(Register reg)
564 {
565 msr(0b011, 0b0100, 0b0100, 0b001, reg);
566 }
567
568 inline void clear_fpsr()
569 {
570 msr(0b011, 0b0100, 0b0100, 0b001, zr);
571 }
572
573 // DCZID_EL0: op1 == 011
574 // CRn == 0000
575 // CRm == 0000
576 // op2 == 111
577 inline void get_dczid_el0(Register reg)
578 {
579 mrs(0b011, 0b0000, 0b0000, 0b111, reg);
580 }
581
582 // CTR_EL0: op1 == 011
583 // CRn == 0000
584 // CRm == 0000
585 // op2 == 001
586 inline void get_ctr_el0(Register reg)
587 {
588 mrs(0b011, 0b0000, 0b0000, 0b001, reg);
589 }
590
591 inline void get_nzcv(Register reg) {
592 mrs(0b011, 0b0100, 0b0010, 0b000, reg);
593 }
594
595 inline void set_nzcv(Register reg) {
596 msr(0b011, 0b0100, 0b0010, 0b000, reg);
597 }
598
599 // idiv variant which deals with MINLONG as dividend and -1 as divisor
600 int corrected_idivl(Register result, Register ra, Register rb,
601 bool want_remainder, Register tmp = rscratch1);
602 int corrected_idivq(Register result, Register ra, Register rb,
603 bool want_remainder, Register tmp = rscratch1);
604
605 // Support for null-checks
606 //
607 // Generates code that causes a null OS exception if the content of reg is null.
608 // If the accessed location is M[reg + offset] and the offset is known, provide the
609 // offset. No explicit code generation is needed if the offset is within a certain
610 // range (0 <= offset <= page_size).
611
612 virtual void null_check(Register reg, int offset = -1);
613 static bool needs_explicit_null_check(intptr_t offset);
614 static bool uses_implicit_null_check(void* address);
615
616 static address target_addr_for_insn(address insn_addr, unsigned insn);
617 static address target_addr_for_insn_or_null(address insn_addr, unsigned insn);
618 static address target_addr_for_insn(address insn_addr) {
619 unsigned insn = *(unsigned*)insn_addr;
620 return target_addr_for_insn(insn_addr, insn);
621 }
622 static address target_addr_for_insn_or_null(address insn_addr) {
623 unsigned insn = *(unsigned*)insn_addr;
624 return target_addr_for_insn_or_null(insn_addr, insn);
625 }
626
627 // Required platform-specific helpers for Label::patch_instructions.
628 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
629 static int pd_patch_instruction_size(address branch, address target);
630 static void pd_patch_instruction(address branch, address target, const char* file = nullptr, int line = 0) {
631 pd_patch_instruction_size(branch, target);
632 }
633 static address pd_call_destination(address branch) {
634 return target_addr_for_insn(branch);
635 }
636 #ifndef PRODUCT
637 static void pd_print_patched_instruction(address branch);
638 #endif
639
640 static int patch_oop(address insn_addr, address o);
641 static int patch_narrow_klass(address insn_addr, narrowKlass n);
642
643 // Return whether code is emitted to a scratch blob.
644 virtual bool in_scratch_emit_size() {
645 return false;
646 }
647 address emit_trampoline_stub(int insts_call_instruction_offset, address target);
648 static int max_trampoline_stub_size();
649 void emit_static_call_stub();
650 static int static_call_stub_size();
651
652 // The following 4 methods return the offset of the appropriate move instruction
653
654 // Support for fast byte/short loading with zero extension (depending on particular CPU)
655 int load_unsigned_byte(Register dst, Address src);
656 int load_unsigned_short(Register dst, Address src);
657
658 // Support for fast byte/short loading with sign extension (depending on particular CPU)
659 int load_signed_byte(Register dst, Address src);
660 int load_signed_short(Register dst, Address src);
661
662 int load_signed_byte32(Register dst, Address src);
663 int load_signed_short32(Register dst, Address src);
664
665 // Support for sign-extension (hi:lo = extend_sign(lo))
666 void extend_sign(Register hi, Register lo);
667
668 // Load and store values by size and signed-ness
669 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed);
670 void store_sized_value(Address dst, Register src, size_t size_in_bytes);
671
672 // Support for inc/dec with optimal instruction selection depending on value
673
674 // x86_64 aliases an unqualified register/address increment and
675 // decrement to call incrementq and decrementq but also supports
676 // explicitly sized calls to incrementq/decrementq or
677 // incrementl/decrementl
678
679 // for aarch64 the proper convention would be to use
680 // increment/decrement for 64 bit operations and
681 // incrementw/decrementw for 32 bit operations. so when porting
682 // x86_64 code we can leave calls to increment/decrement as is,
683 // replace incrementq/decrementq with increment/decrement and
684 // replace incrementl/decrementl with incrementw/decrementw.
685
686 // n.b. increment/decrement calls with an Address destination will
687 // need to use a scratch register to load the value to be
688 // incremented. increment/decrement calls which add or subtract a
689 // constant value greater than 2^12 will need to use a 2nd scratch
690 // register to hold the constant. so, a register increment/decrement
691 // may trash rscratch2 and an address increment/decrement trash
692 // rscratch and rscratch2
693
694 void decrementw(Address dst, int value = 1);
695 void decrementw(Register reg, int value = 1);
696
697 void decrement(Register reg, int value = 1);
698 void decrement(Address dst, int value = 1);
699
700 void incrementw(Address dst, int value = 1);
701 void incrementw(Register reg, int value = 1);
702
703 void increment(Register reg, int value = 1);
704 void increment(Address dst, int value = 1);
705
706
707 // Alignment
708 void align(int modulus);
709
710 // nop
711 void post_call_nop();
712
713 // Stack frame creation/removal
714 void enter(bool strip_ret_addr = false);
715 void leave();
716
717 // ROP Protection
718 void protect_return_address();
719 void protect_return_address(Register return_reg);
720 void authenticate_return_address();
721 void authenticate_return_address(Register return_reg);
722 void strip_return_address();
723 void check_return_address(Register return_reg=lr) PRODUCT_RETURN;
724
725 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
726 // The pointer will be loaded into the thread register.
727 void get_thread(Register thread);
728
729 // support for argument shuffling
730 void move32_64(VMRegPair src, VMRegPair dst, Register tmp = rscratch1);
731 void float_move(VMRegPair src, VMRegPair dst, Register tmp = rscratch1);
732 void long_move(VMRegPair src, VMRegPair dst, Register tmp = rscratch1);
733 void double_move(VMRegPair src, VMRegPair dst, Register tmp = rscratch1);
734 void object_move(
735 OopMap* map,
736 int oop_handle_offset,
737 int framesize_in_slots,
738 VMRegPair src,
739 VMRegPair dst,
740 bool is_receiver,
741 int* receiver_offset);
742
743
744 // Support for VM calls
745 //
746 // It is imperative that all calls into the VM are handled via the call_VM macros.
747 // They make sure that the stack linkage is setup correctly. call_VM's correspond
748 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
749
750
751 void call_VM(Register oop_result,
752 address entry_point,
753 bool check_exceptions = true);
754 void call_VM(Register oop_result,
755 address entry_point,
756 Register arg_1,
757 bool check_exceptions = true);
758 void call_VM(Register oop_result,
759 address entry_point,
760 Register arg_1, Register arg_2,
761 bool check_exceptions = true);
762 void call_VM(Register oop_result,
763 address entry_point,
764 Register arg_1, Register arg_2, Register arg_3,
765 bool check_exceptions = true);
766
767 // Overloadings with last_Java_sp
768 void call_VM(Register oop_result,
769 Register last_java_sp,
770 address entry_point,
771 int number_of_arguments = 0,
772 bool check_exceptions = true);
773 void call_VM(Register oop_result,
774 Register last_java_sp,
775 address entry_point,
776 Register arg_1, bool
777 check_exceptions = true);
778 void call_VM(Register oop_result,
779 Register last_java_sp,
780 address entry_point,
781 Register arg_1, Register arg_2,
782 bool check_exceptions = true);
783 void call_VM(Register oop_result,
784 Register last_java_sp,
785 address entry_point,
786 Register arg_1, Register arg_2, Register arg_3,
787 bool check_exceptions = true);
788
789 void get_vm_result (Register oop_result, Register thread);
790 void get_vm_result_2(Register metadata_result, Register thread);
791
792 // These always tightly bind to MacroAssembler::call_VM_base
793 // bypassing the virtual implementation
794 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
795 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
796 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
797 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
798 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
799
800 void call_VM_leaf(address entry_point,
801 int number_of_arguments = 0);
802 void call_VM_leaf(address entry_point,
803 Register arg_1);
804 void call_VM_leaf(address entry_point,
805 Register arg_1, Register arg_2);
806 void call_VM_leaf(address entry_point,
807 Register arg_1, Register arg_2, Register arg_3);
808
809 // These always tightly bind to MacroAssembler::call_VM_leaf_base
810 // bypassing the virtual implementation
811 void super_call_VM_leaf(address entry_point);
812 void super_call_VM_leaf(address entry_point, Register arg_1);
813 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
814 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
815 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
816
817 // last Java Frame (fills frame anchor)
818 void set_last_Java_frame(Register last_java_sp,
819 Register last_java_fp,
820 address last_java_pc,
821 Register scratch);
822
823 void set_last_Java_frame(Register last_java_sp,
824 Register last_java_fp,
825 Label &last_java_pc,
826 Register scratch);
827
828 void set_last_Java_frame(Register last_java_sp,
829 Register last_java_fp,
830 Register last_java_pc,
831 Register scratch);
832
833 void reset_last_Java_frame(Register thread);
834
835 // thread in the default location (rthread)
836 void reset_last_Java_frame(bool clear_fp);
837
838 // Stores
839 void store_check(Register obj); // store check for obj - register is destroyed afterwards
840 void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed)
841
842 void resolve_jobject(Register value, Register tmp1, Register tmp2);
843 void resolve_global_jobject(Register value, Register tmp1, Register tmp2);
844
845 // C 'boolean' to Java boolean: x == 0 ? 0 : 1
846 void c2bool(Register x);
847
848 void load_method_holder_cld(Register rresult, Register rmethod);
849 void load_method_holder(Register holder, Register method);
850
851 // oop manipulations
852 void load_klass(Register dst, Register src);
853 void store_klass(Register dst, Register src);
854 void cmp_klass(Register oop, Register trial_klass, Register tmp);
855
856 void resolve_weak_handle(Register result, Register tmp1, Register tmp2);
857 void resolve_oop_handle(Register result, Register tmp1, Register tmp2);
858 void load_mirror(Register dst, Register method, Register tmp1, Register tmp2);
859
860 void access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
861 Register tmp1, Register tmp2);
862
863 void access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register val,
864 Register tmp1, Register tmp2, Register tmp3);
865
866 void load_heap_oop(Register dst, Address src, Register tmp1,
867 Register tmp2, DecoratorSet decorators = 0);
868
869 void load_heap_oop_not_null(Register dst, Address src, Register tmp1,
870 Register tmp2, DecoratorSet decorators = 0);
871 void store_heap_oop(Address dst, Register val, Register tmp1,
872 Register tmp2, Register tmp3, DecoratorSet decorators = 0);
873
874 // currently unimplemented
875 // Used for storing null. All other oop constants should be
876 // stored using routines that take a jobject.
877 void store_heap_oop_null(Address dst);
878
879 void store_klass_gap(Register dst, Register src);
880
881 // This dummy is to prevent a call to store_heap_oop from
882 // converting a zero (like null) into a Register by giving
883 // the compiler two choices it can't resolve
884
885 void store_heap_oop(Address dst, void* dummy);
886
887 void encode_heap_oop(Register d, Register s);
888 void encode_heap_oop(Register r) { encode_heap_oop(r, r); }
889 void decode_heap_oop(Register d, Register s);
890 void decode_heap_oop(Register r) { decode_heap_oop(r, r); }
891 void encode_heap_oop_not_null(Register r);
892 void decode_heap_oop_not_null(Register r);
893 void encode_heap_oop_not_null(Register dst, Register src);
894 void decode_heap_oop_not_null(Register dst, Register src);
895
896 void set_narrow_oop(Register dst, jobject obj);
897
898 void encode_klass_not_null(Register r);
899 void decode_klass_not_null(Register r);
900 void encode_klass_not_null(Register dst, Register src);
901 void decode_klass_not_null(Register dst, Register src);
902
903 void set_narrow_klass(Register dst, Klass* k);
904
905 // if heap base register is used - reinit it with the correct value
906 void reinit_heapbase();
907
908 DEBUG_ONLY(void verify_heapbase(const char* msg);)
909
910 void push_CPU_state(bool save_vectors = false, bool use_sve = false,
911 int sve_vector_size_in_bytes = 0, int total_predicate_in_bytes = 0);
912 void pop_CPU_state(bool restore_vectors = false, bool use_sve = false,
913 int sve_vector_size_in_bytes = 0, int total_predicate_in_bytes = 0);
914
915 void push_cont_fastpath(Register java_thread);
916 void pop_cont_fastpath(Register java_thread);
917
918 // Round up to a power of two
919 void round_to(Register reg, int modulus);
920
921 // java.lang.Math::round intrinsics
922 void java_round_double(Register dst, FloatRegister src, FloatRegister ftmp);
923 void java_round_float(Register dst, FloatRegister src, FloatRegister ftmp);
924
925 // allocation
926 void tlab_allocate(
927 Register obj, // result: pointer to object after successful allocation
928 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
929 int con_size_in_bytes, // object size in bytes if known at compile time
930 Register t1, // temp register
931 Register t2, // temp register
932 Label& slow_case // continuation point if fast allocation fails
933 );
934 void verify_tlab();
935
936 // interface method calling
937 void lookup_interface_method(Register recv_klass,
938 Register intf_klass,
939 RegisterOrConstant itable_index,
940 Register method_result,
941 Register scan_temp,
942 Label& no_such_interface,
943 bool return_method = true);
944
945 void lookup_interface_method_stub(Register recv_klass,
946 Register holder_klass,
947 Register resolved_klass,
948 Register method_result,
949 Register temp_reg,
950 Register temp_reg2,
951 int itable_index,
952 Label& L_no_such_interface);
953
954 // virtual method calling
955 // n.b. x86 allows RegisterOrConstant for vtable_index
956 void lookup_virtual_method(Register recv_klass,
957 RegisterOrConstant vtable_index,
958 Register method_result);
959
960 // Test sub_klass against super_klass, with fast and slow paths.
961
962 // The fast path produces a tri-state answer: yes / no / maybe-slow.
963 // One of the three labels can be null, meaning take the fall-through.
964 // If super_check_offset is -1, the value is loaded up from super_klass.
965 // No registers are killed, except temp_reg.
966 void check_klass_subtype_fast_path(Register sub_klass,
967 Register super_klass,
968 Register temp_reg,
969 Label* L_success,
970 Label* L_failure,
971 Label* L_slow_path,
972 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
973
974 // The rest of the type check; must be wired to a corresponding fast path.
975 // It does not repeat the fast path logic, so don't use it standalone.
976 // The temp_reg and temp2_reg can be noreg, if no temps are available.
977 // Updates the sub's secondary super cache as necessary.
978 // If set_cond_codes, condition codes will be Z on success, NZ on failure.
979 void check_klass_subtype_slow_path(Register sub_klass,
980 Register super_klass,
981 Register temp_reg,
982 Register temp2_reg,
983 Label* L_success,
984 Label* L_failure,
985 bool set_cond_codes = false);
986
987 // Simplified, combined version, good for typical uses.
988 // Falls through on failure.
989 void check_klass_subtype(Register sub_klass,
990 Register super_klass,
991 Register temp_reg,
992 Label& L_success);
993
994 void clinit_barrier(Register klass,
995 Register thread,
996 Label* L_fast_path = nullptr,
997 Label* L_slow_path = nullptr);
998
999 Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
1000
1001 void verify_sve_vector_length(Register tmp = rscratch1);
1002 void reinitialize_ptrue() {
1003 if (UseSVE > 0) {
1004 sve_ptrue(ptrue, B);
1005 }
1006 }
1007 void verify_ptrue();
1008
1009 // Debugging
1010
1011 // only if +VerifyOops
1012 void _verify_oop(Register reg, const char* s, const char* file, int line);
1013 void _verify_oop_addr(Address addr, const char * s, const char* file, int line);
1014
1015 void _verify_oop_checked(Register reg, const char* s, const char* file, int line) {
1016 if (VerifyOops) {
1017 _verify_oop(reg, s, file, line);
1018 }
1019 }
1020 void _verify_oop_addr_checked(Address reg, const char* s, const char* file, int line) {
1021 if (VerifyOops) {
1022 _verify_oop_addr(reg, s, file, line);
1023 }
1024 }
1025
1026 // TODO: verify method and klass metadata (compare against vptr?)
1027 void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
1028 void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
1029
1030 #define verify_oop(reg) _verify_oop_checked(reg, "broken oop " #reg, __FILE__, __LINE__)
1031 #define verify_oop_msg(reg, msg) _verify_oop_checked(reg, "broken oop " #reg ", " #msg, __FILE__, __LINE__)
1032 #define verify_oop_addr(addr) _verify_oop_addr_checked(addr, "broken oop addr " #addr, __FILE__, __LINE__)
1033 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
1034 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
1035
1036 // only if +VerifyFPU
1037 void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
1038
1039 // prints msg, dumps registers and stops execution
1040 void stop(const char* msg);
1041
1042 static void debug64(char* msg, int64_t pc, int64_t regs[]);
1043
1044 void untested() { stop("untested"); }
1045
1046 void unimplemented(const char* what = "");
1047
1048 void should_not_reach_here() { stop("should not reach here"); }
1049
1050 void _assert_asm(Condition cc, const char* msg);
1051 #define assert_asm0(cc, msg) _assert_asm(cc, FILE_AND_LINE ": " msg)
1052 #define assert_asm(masm, command, cc, msg) DEBUG_ONLY(command; (masm)->_assert_asm(cc, FILE_AND_LINE ": " #command " " #cc ": " msg))
1053
1054 // Stack overflow checking
1055 void bang_stack_with_offset(int offset) {
1056 // stack grows down, caller passes positive offset
1057 assert(offset > 0, "must bang with negative offset");
1058 sub(rscratch2, sp, offset);
1059 str(zr, Address(rscratch2));
1060 }
1061
1062 // Writes to stack successive pages until offset reached to check for
1063 // stack overflow + shadow pages. Also, clobbers tmp
1064 void bang_stack_size(Register size, Register tmp);
1065
1066 // Check for reserved stack access in method being exited (for JIT)
1067 void reserved_stack_check();
1068
1069 // Arithmetics
1070
1071 void addptr(const Address &dst, int32_t src);
1072 void cmpptr(Register src1, Address src2);
1073
1074 void cmpoop(Register obj1, Register obj2);
1075
1076 // Various forms of CAS
1077
1078 void cmpxchg_obj_header(Register oldv, Register newv, Register obj, Register tmp,
1079 Label &succeed, Label *fail);
1080 void cmpxchgptr(Register oldv, Register newv, Register addr, Register tmp,
1081 Label &succeed, Label *fail);
1082
1083 void cmpxchgw(Register oldv, Register newv, Register addr, Register tmp,
1084 Label &succeed, Label *fail);
1085
1086 void atomic_add(Register prev, RegisterOrConstant incr, Register addr);
1087 void atomic_addw(Register prev, RegisterOrConstant incr, Register addr);
1088 void atomic_addal(Register prev, RegisterOrConstant incr, Register addr);
1089 void atomic_addalw(Register prev, RegisterOrConstant incr, Register addr);
1090
1091 void atomic_xchg(Register prev, Register newv, Register addr);
1092 void atomic_xchgw(Register prev, Register newv, Register addr);
1093 void atomic_xchgl(Register prev, Register newv, Register addr);
1094 void atomic_xchglw(Register prev, Register newv, Register addr);
1095 void atomic_xchgal(Register prev, Register newv, Register addr);
1096 void atomic_xchgalw(Register prev, Register newv, Register addr);
1097
1098 void orptr(Address adr, RegisterOrConstant src) {
1099 ldr(rscratch1, adr);
1100 if (src.is_register())
1101 orr(rscratch1, rscratch1, src.as_register());
1102 else
1103 orr(rscratch1, rscratch1, src.as_constant());
1104 str(rscratch1, adr);
1105 }
1106
1107 // A generic CAS; success or failure is in the EQ flag.
1108 // Clobbers rscratch1
1109 void cmpxchg(Register addr, Register expected, Register new_val,
1110 enum operand_size size,
1111 bool acquire, bool release, bool weak,
1112 Register result);
1113
1114 #ifdef ASSERT
1115 // Template short-hand support to clean-up after a failed call to trampoline
1116 // call generation (see trampoline_call() below), when a set of Labels must
1117 // be reset (before returning).
1118 template<typename Label, typename... More>
1119 void reset_labels(Label &lbl, More&... more) {
1120 lbl.reset(); reset_labels(more...);
1121 }
1122 template<typename Label>
1123 void reset_labels(Label &lbl) {
1124 lbl.reset();
1125 }
1126 #endif
1127
1128 private:
1129 void compare_eq(Register rn, Register rm, enum operand_size size);
1130
1131 public:
1132 // AArch64 OpenJDK uses four different types of calls:
1133 // - direct call: bl pc_relative_offset
1134 // This is the shortest and the fastest, but the offset has the range:
1135 // +/-128MB for the release build, +/-2MB for the debug build.
1136 //
1137 // - far call: adrp reg, pc_relative_offset; add; bl reg
1138 // This is longer than a direct call. The offset has
1139 // the range +/-4GB. As the code cache size is limited to 4GB,
1140 // far calls can reach anywhere in the code cache. If a jump is
1141 // needed rather than a call, a far jump 'b reg' can be used instead.
1142 // All instructions are embedded at a call site.
1143 //
1144 // - trampoline call:
1145 // This is only available in C1/C2-generated code (nmethod). It is a combination
1146 // of a direct call, which is used if the destination of a call is in range,
1147 // and a register-indirect call. It has the advantages of reaching anywhere in
1148 // the AArch64 address space and being patchable at runtime when the generated
1149 // code is being executed by other threads.
1150 //
1151 // [Main code section]
1152 // bl trampoline
1153 // [Stub code section]
1154 // trampoline:
1155 // ldr reg, pc + 8
1156 // br reg
1157 // <64-bit destination address>
1158 //
1159 // If the destination is in range when the generated code is moved to the code
1160 // cache, 'bl trampoline' is replaced with 'bl destination' and the trampoline
1161 // is not used.
1162 // The optimization does not remove the trampoline from the stub section.
1163 // This is necessary because the trampoline may well be redirected later when
1164 // code is patched, and the new destination may not be reachable by a simple BR
1165 // instruction.
1166 //
1167 // - indirect call: move reg, address; blr reg
1168 // This too can reach anywhere in the address space, but it cannot be
1169 // patched while code is running, so it must only be modified at a safepoint.
1170 // This form of call is most suitable for targets at fixed addresses, which
1171 // will never be patched.
1172 //
1173 // The patching we do conforms to the "Concurrent modification and
1174 // execution of instructions" section of the Arm Architectural
1175 // Reference Manual, which only allows B, BL, BRK, HVC, ISB, NOP, SMC,
1176 // or SVC instructions to be modified while another thread is
1177 // executing them.
1178 //
1179 // To patch a trampoline call when the BL can't reach, we first modify
1180 // the 64-bit destination address in the trampoline, then modify the
1181 // BL to point to the trampoline, then flush the instruction cache to
1182 // broadcast the change to all executing threads. See
1183 // NativeCall::set_destination_mt_safe for the details.
1184 //
1185 // There is a benign race in that the other thread might observe the
1186 // modified BL before it observes the modified 64-bit destination
1187 // address. That does not matter because the destination method has been
1188 // invalidated, so there will be a trap at its start.
1189 // For this to work, the destination address in the trampoline is
1190 // always updated, even if we're not using the trampoline.
1191
1192 // Emit a direct call if the entry address will always be in range,
1193 // otherwise a trampoline call.
1194 // Supported entry.rspec():
1195 // - relocInfo::runtime_call_type
1196 // - relocInfo::opt_virtual_call_type
1197 // - relocInfo::static_call_type
1198 // - relocInfo::virtual_call_type
1199 //
1200 // Return: the call PC or null if CodeCache is full.
1201 address trampoline_call(Address entry);
1202
1203 static bool far_branches() {
1204 return ReservedCodeCacheSize > branch_range;
1205 }
1206
1207 // Check if branches to the non nmethod section require a far jump
1208 static bool codestub_branch_needs_far_jump() {
1209 return CodeCache::max_distance_to_non_nmethod() > branch_range;
1210 }
1211
1212 // Emit a direct call/jump if the entry address will always be in range,
1213 // otherwise a far call/jump.
1214 // The address must be inside the code cache.
1215 // Supported entry.rspec():
1216 // - relocInfo::external_word_type
1217 // - relocInfo::runtime_call_type
1218 // - relocInfo::none
1219 // In the case of a far call/jump, the entry address is put in the tmp register.
1220 // The tmp register is invalidated.
1221 //
1222 // Far_jump returns the amount of the emitted code.
1223 void far_call(Address entry, Register tmp = rscratch1);
1224 int far_jump(Address entry, Register tmp = rscratch1);
1225
1226 static int far_codestub_branch_size() {
1227 if (codestub_branch_needs_far_jump()) {
1228 return 3 * 4; // adrp, add, br
1229 } else {
1230 return 4;
1231 }
1232 }
1233
1234 // Emit the CompiledIC call idiom
1235 address ic_call(address entry, jint method_index = 0);
1236
1237 public:
1238
1239 // Data
1240
1241 void mov_metadata(Register dst, Metadata* obj);
1242 Address allocate_metadata_address(Metadata* obj);
1243 Address constant_oop_address(jobject obj);
1244
1245 void movoop(Register dst, jobject obj);
1246
1247 // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
1248 void kernel_crc32(Register crc, Register buf, Register len,
1249 Register table0, Register table1, Register table2, Register table3,
1250 Register tmp, Register tmp2, Register tmp3);
1251 // CRC32 code for java.util.zip.CRC32C::updateBytes() intrinsic.
1252 void kernel_crc32c(Register crc, Register buf, Register len,
1253 Register table0, Register table1, Register table2, Register table3,
1254 Register tmp, Register tmp2, Register tmp3);
1255
1256 // Stack push and pop individual 64 bit registers
1257 void push(Register src);
1258 void pop(Register dst);
1259
1260 void repne_scan(Register addr, Register value, Register count,
1261 Register scratch);
1262 void repne_scanw(Register addr, Register value, Register count,
1263 Register scratch);
1264
1265 typedef void (MacroAssembler::* add_sub_imm_insn)(Register Rd, Register Rn, unsigned imm);
1266 typedef void (MacroAssembler::* add_sub_reg_insn)(Register Rd, Register Rn, Register Rm, enum shift_kind kind, unsigned shift);
1267
1268 // If a constant does not fit in an immediate field, generate some
1269 // number of MOV instructions and then perform the operation
1270 void wrap_add_sub_imm_insn(Register Rd, Register Rn, uint64_t imm,
1271 add_sub_imm_insn insn1,
1272 add_sub_reg_insn insn2, bool is32);
1273 // Separate vsn which sets the flags
1274 void wrap_adds_subs_imm_insn(Register Rd, Register Rn, uint64_t imm,
1275 add_sub_imm_insn insn1,
1276 add_sub_reg_insn insn2, bool is32);
1277
1278 #define WRAP(INSN, is32) \
1279 void INSN(Register Rd, Register Rn, uint64_t imm) { \
1280 wrap_add_sub_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN, is32); \
1281 } \
1282 \
1283 void INSN(Register Rd, Register Rn, Register Rm, \
1284 enum shift_kind kind, unsigned shift = 0) { \
1285 Assembler::INSN(Rd, Rn, Rm, kind, shift); \
1286 } \
1287 \
1288 void INSN(Register Rd, Register Rn, Register Rm) { \
1289 Assembler::INSN(Rd, Rn, Rm); \
1290 } \
1291 \
1292 void INSN(Register Rd, Register Rn, Register Rm, \
1293 ext::operation option, int amount = 0) { \
1294 Assembler::INSN(Rd, Rn, Rm, option, amount); \
1295 }
1296
1297 WRAP(add, false) WRAP(addw, true) WRAP(sub, false) WRAP(subw, true)
1298
1299 #undef WRAP
1300 #define WRAP(INSN, is32) \
1301 void INSN(Register Rd, Register Rn, uint64_t imm) { \
1302 wrap_adds_subs_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN, is32); \
1303 } \
1304 \
1305 void INSN(Register Rd, Register Rn, Register Rm, \
1306 enum shift_kind kind, unsigned shift = 0) { \
1307 Assembler::INSN(Rd, Rn, Rm, kind, shift); \
1308 } \
1309 \
1310 void INSN(Register Rd, Register Rn, Register Rm) { \
1311 Assembler::INSN(Rd, Rn, Rm); \
1312 } \
1313 \
1314 void INSN(Register Rd, Register Rn, Register Rm, \
1315 ext::operation option, int amount = 0) { \
1316 Assembler::INSN(Rd, Rn, Rm, option, amount); \
1317 }
1318
1319 WRAP(adds, false) WRAP(addsw, true) WRAP(subs, false) WRAP(subsw, true)
1320
1321 void add(Register Rd, Register Rn, RegisterOrConstant increment);
1322 void addw(Register Rd, Register Rn, RegisterOrConstant increment);
1323 void sub(Register Rd, Register Rn, RegisterOrConstant decrement);
1324 void subw(Register Rd, Register Rn, RegisterOrConstant decrement);
1325
1326 void adrp(Register reg1, const Address &dest, uint64_t &byte_offset);
1327
1328 void tableswitch(Register index, jint lowbound, jint highbound,
1329 Label &jumptable, Label &jumptable_end, int stride = 1) {
1330 adr(rscratch1, jumptable);
1331 subsw(rscratch2, index, lowbound);
1332 subsw(zr, rscratch2, highbound - lowbound);
1333 br(Assembler::HS, jumptable_end);
1334 add(rscratch1, rscratch1, rscratch2,
1335 ext::sxtw, exact_log2(stride * Assembler::instruction_size));
1336 br(rscratch1);
1337 }
1338
1339 // Form an address from base + offset in Rd. Rd may or may not
1340 // actually be used: you must use the Address that is returned. It
1341 // is up to you to ensure that the shift provided matches the size
1342 // of your data.
1343 Address form_address(Register Rd, Register base, int64_t byte_offset, int shift);
1344
1345 // Return true iff an address is within the 48-bit AArch64 address
1346 // space.
1347 bool is_valid_AArch64_address(address a) {
1348 return ((uint64_t)a >> 48) == 0;
1349 }
1350
1351 // Load the base of the cardtable byte map into reg.
1352 void load_byte_map_base(Register reg);
1353
1354 // Prolog generator routines to support switch between x86 code and
1355 // generated ARM code
1356
1357 // routine to generate an x86 prolog for a stub function which
1358 // bootstraps into the generated ARM code which directly follows the
1359 // stub
1360 //
1361
1362 public:
1363
1364 void ldr_constant(Register dest, const Address &const_addr) {
1365 if (NearCpool) {
1366 ldr(dest, const_addr);
1367 } else {
1368 uint64_t offset;
1369 adrp(dest, InternalAddress(const_addr.target()), offset);
1370 ldr(dest, Address(dest, offset));
1371 }
1372 }
1373
1374 address read_polling_page(Register r, relocInfo::relocType rtype);
1375 void get_polling_page(Register dest, relocInfo::relocType rtype);
1376
1377 // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
1378 void update_byte_crc32(Register crc, Register val, Register table);
1379 void update_word_crc32(Register crc, Register v, Register tmp,
1380 Register table0, Register table1, Register table2, Register table3,
1381 bool upper = false);
1382
1383 address count_positives(Register ary1, Register len, Register result);
1384
1385 address arrays_equals(Register a1, Register a2, Register result, Register cnt1,
1386 Register tmp1, Register tmp2, Register tmp3, int elem_size);
1387
1388 void string_equals(Register a1, Register a2, Register result, Register cnt1,
1389 int elem_size);
1390
1391 void fill_words(Register base, Register cnt, Register value);
1392 address zero_words(Register base, uint64_t cnt);
1393 address zero_words(Register ptr, Register cnt);
1394 void zero_dcache_blocks(Register base, Register cnt);
1395
1396 static const int zero_words_block_size;
1397
1398 address byte_array_inflate(Register src, Register dst, Register len,
1399 FloatRegister vtmp1, FloatRegister vtmp2,
1400 FloatRegister vtmp3, Register tmp4);
1401
1402 void char_array_compress(Register src, Register dst, Register len,
1403 Register res,
1404 FloatRegister vtmp0, FloatRegister vtmp1,
1405 FloatRegister vtmp2, FloatRegister vtmp3,
1406 FloatRegister vtmp4, FloatRegister vtmp5);
1407
1408 void encode_iso_array(Register src, Register dst,
1409 Register len, Register res, bool ascii,
1410 FloatRegister vtmp0, FloatRegister vtmp1,
1411 FloatRegister vtmp2, FloatRegister vtmp3,
1412 FloatRegister vtmp4, FloatRegister vtmp5);
1413
1414 void fast_log(FloatRegister vtmp0, FloatRegister vtmp1, FloatRegister vtmp2,
1415 FloatRegister vtmp3, FloatRegister vtmp4, FloatRegister vtmp5,
1416 FloatRegister tmpC1, FloatRegister tmpC2, FloatRegister tmpC3,
1417 FloatRegister tmpC4, Register tmp1, Register tmp2,
1418 Register tmp3, Register tmp4, Register tmp5);
1419 void generate_dsin_dcos(bool isCos, address npio2_hw, address two_over_pi,
1420 address pio2, address dsin_coef, address dcos_coef);
1421 private:
1422 // begin trigonometric functions support block
1423 void generate__ieee754_rem_pio2(address npio2_hw, address two_over_pi, address pio2);
1424 void generate__kernel_rem_pio2(address two_over_pi, address pio2);
1425 void generate_kernel_sin(FloatRegister x, bool iyIsOne, address dsin_coef);
1426 void generate_kernel_cos(FloatRegister x, address dcos_coef);
1427 // end trigonometric functions support block
1428 void add2_with_carry(Register final_dest_hi, Register dest_hi, Register dest_lo,
1429 Register src1, Register src2);
1430 void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
1431 add2_with_carry(dest_hi, dest_hi, dest_lo, src1, src2);
1432 }
1433 void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
1434 Register y, Register y_idx, Register z,
1435 Register carry, Register product,
1436 Register idx, Register kdx);
1437 void multiply_128_x_128_loop(Register y, Register z,
1438 Register carry, Register carry2,
1439 Register idx, Register jdx,
1440 Register yz_idx1, Register yz_idx2,
1441 Register tmp, Register tmp3, Register tmp4,
1442 Register tmp7, Register product_hi);
1443 void kernel_crc32_using_crypto_pmull(Register crc, Register buf,
1444 Register len, Register tmp0, Register tmp1, Register tmp2,
1445 Register tmp3);
1446 void kernel_crc32_using_crc32(Register crc, Register buf,
1447 Register len, Register tmp0, Register tmp1, Register tmp2,
1448 Register tmp3);
1449 void kernel_crc32c_using_crypto_pmull(Register crc, Register buf,
1450 Register len, Register tmp0, Register tmp1, Register tmp2,
1451 Register tmp3);
1452 void kernel_crc32c_using_crc32c(Register crc, Register buf,
1453 Register len, Register tmp0, Register tmp1, Register tmp2,
1454 Register tmp3);
1455 void kernel_crc32_common_fold_using_crypto_pmull(Register crc, Register buf,
1456 Register len, Register tmp0, Register tmp1, Register tmp2,
1457 size_t table_offset);
1458
1459 void ghash_modmul (FloatRegister result,
1460 FloatRegister result_lo, FloatRegister result_hi, FloatRegister b,
1461 FloatRegister a, FloatRegister vzr, FloatRegister a1_xor_a0, FloatRegister p,
1462 FloatRegister t1, FloatRegister t2, FloatRegister t3);
1463 void ghash_load_wide(int index, Register data, FloatRegister result, FloatRegister state);
1464 public:
1465 void multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z,
1466 Register zlen, Register tmp1, Register tmp2, Register tmp3,
1467 Register tmp4, Register tmp5, Register tmp6, Register tmp7);
1468 void mul_add(Register out, Register in, Register offs, Register len, Register k);
1469 void ghash_multiply(FloatRegister result_lo, FloatRegister result_hi,
1470 FloatRegister a, FloatRegister b, FloatRegister a1_xor_a0,
1471 FloatRegister tmp1, FloatRegister tmp2, FloatRegister tmp3);
1472 void ghash_multiply_wide(int index,
1473 FloatRegister result_lo, FloatRegister result_hi,
1474 FloatRegister a, FloatRegister b, FloatRegister a1_xor_a0,
1475 FloatRegister tmp1, FloatRegister tmp2, FloatRegister tmp3);
1476 void ghash_reduce(FloatRegister result, FloatRegister lo, FloatRegister hi,
1477 FloatRegister p, FloatRegister z, FloatRegister t1);
1478 void ghash_reduce_wide(int index, FloatRegister result, FloatRegister lo, FloatRegister hi,
1479 FloatRegister p, FloatRegister z, FloatRegister t1);
1480 void ghash_processBlocks_wide(address p, Register state, Register subkeyH,
1481 Register data, Register blocks, int unrolls);
1482
1483
1484 void aesenc_loadkeys(Register key, Register keylen);
1485 void aesecb_encrypt(Register from, Register to, Register keylen,
1486 FloatRegister data = v0, int unrolls = 1);
1487 void aesecb_decrypt(Register from, Register to, Register key, Register keylen);
1488 void aes_round(FloatRegister input, FloatRegister subkey);
1489
1490 // ChaCha20 functions support block
1491 void cc20_quarter_round(FloatRegister aVec, FloatRegister bVec,
1492 FloatRegister cVec, FloatRegister dVec, FloatRegister scratch,
1493 FloatRegister tbl);
1494 void cc20_shift_lane_org(FloatRegister bVec, FloatRegister cVec,
1495 FloatRegister dVec, bool colToDiag);
1496
1497 // Place an ISB after code may have been modified due to a safepoint.
1498 void safepoint_isb();
1499
1500 private:
1501 // Return the effective address r + (r1 << ext) + offset.
1502 // Uses rscratch2.
1503 Address offsetted_address(Register r, Register r1, Address::extend ext,
1504 int offset, int size);
1505
1506 private:
1507 // Returns an address on the stack which is reachable with a ldr/str of size
1508 // Uses rscratch2 if the address is not directly reachable
1509 Address spill_address(int size, int offset, Register tmp=rscratch2);
1510 Address sve_spill_address(int sve_reg_size_in_bytes, int offset, Register tmp=rscratch2);
1511
1512 bool merge_alignment_check(Register base, size_t size, int64_t cur_offset, int64_t prev_offset) const;
1513
1514 // Check whether two loads/stores can be merged into ldp/stp.
1515 bool ldst_can_merge(Register rx, const Address &adr, size_t cur_size_in_bytes, bool is_store) const;
1516
1517 // Merge current load/store with previous load/store into ldp/stp.
1518 void merge_ldst(Register rx, const Address &adr, size_t cur_size_in_bytes, bool is_store);
1519
1520 // Try to merge two loads/stores into ldp/stp. If success, returns true else false.
1521 bool try_merge_ldst(Register rt, const Address &adr, size_t cur_size_in_bytes, bool is_store);
1522
1523 public:
1524 void spill(Register Rx, bool is64, int offset) {
1525 if (is64) {
1526 str(Rx, spill_address(8, offset));
1527 } else {
1528 strw(Rx, spill_address(4, offset));
1529 }
1530 }
1531 void spill(FloatRegister Vx, SIMD_RegVariant T, int offset) {
1532 str(Vx, T, spill_address(1 << (int)T, offset));
1533 }
1534
1535 void spill_sve_vector(FloatRegister Zx, int offset, int vector_reg_size_in_bytes) {
1536 sve_str(Zx, sve_spill_address(vector_reg_size_in_bytes, offset));
1537 }
1538 void spill_sve_predicate(PRegister pr, int offset, int predicate_reg_size_in_bytes) {
1539 sve_str(pr, sve_spill_address(predicate_reg_size_in_bytes, offset));
1540 }
1541
1542 void unspill(Register Rx, bool is64, int offset) {
1543 if (is64) {
1544 ldr(Rx, spill_address(8, offset));
1545 } else {
1546 ldrw(Rx, spill_address(4, offset));
1547 }
1548 }
1549 void unspill(FloatRegister Vx, SIMD_RegVariant T, int offset) {
1550 ldr(Vx, T, spill_address(1 << (int)T, offset));
1551 }
1552
1553 void unspill_sve_vector(FloatRegister Zx, int offset, int vector_reg_size_in_bytes) {
1554 sve_ldr(Zx, sve_spill_address(vector_reg_size_in_bytes, offset));
1555 }
1556 void unspill_sve_predicate(PRegister pr, int offset, int predicate_reg_size_in_bytes) {
1557 sve_ldr(pr, sve_spill_address(predicate_reg_size_in_bytes, offset));
1558 }
1559
1560 void spill_copy128(int src_offset, int dst_offset,
1561 Register tmp1=rscratch1, Register tmp2=rscratch2) {
1562 if (src_offset < 512 && (src_offset & 7) == 0 &&
1563 dst_offset < 512 && (dst_offset & 7) == 0) {
1564 ldp(tmp1, tmp2, Address(sp, src_offset));
1565 stp(tmp1, tmp2, Address(sp, dst_offset));
1566 } else {
1567 unspill(tmp1, true, src_offset);
1568 spill(tmp1, true, dst_offset);
1569 unspill(tmp1, true, src_offset+8);
1570 spill(tmp1, true, dst_offset+8);
1571 }
1572 }
1573 void spill_copy_sve_vector_stack_to_stack(int src_offset, int dst_offset,
1574 int sve_vec_reg_size_in_bytes) {
1575 assert(sve_vec_reg_size_in_bytes % 16 == 0, "unexpected sve vector reg size");
1576 for (int i = 0; i < sve_vec_reg_size_in_bytes / 16; i++) {
1577 spill_copy128(src_offset, dst_offset);
1578 src_offset += 16;
1579 dst_offset += 16;
1580 }
1581 }
1582 void spill_copy_sve_predicate_stack_to_stack(int src_offset, int dst_offset,
1583 int sve_predicate_reg_size_in_bytes) {
1584 sve_ldr(ptrue, sve_spill_address(sve_predicate_reg_size_in_bytes, src_offset));
1585 sve_str(ptrue, sve_spill_address(sve_predicate_reg_size_in_bytes, dst_offset));
1586 reinitialize_ptrue();
1587 }
1588 void cache_wb(Address line);
1589 void cache_wbsync(bool is_pre);
1590
1591 // Code for java.lang.Thread::onSpinWait() intrinsic.
1592 void spin_wait();
1593
1594 void lightweight_lock(Register obj, Register hdr, Register t1, Register t2, Label& slow);
1595 void lightweight_unlock(Register obj, Register hdr, Register t1, Register t2, Label& slow);
1596
1597 private:
1598 // Check the current thread doesn't need a cross modify fence.
1599 void verify_cross_modify_fence_not_required() PRODUCT_RETURN;
1600
1601 };
1602
1603 #ifdef ASSERT
1604 inline bool AbstractAssembler::pd_check_instruction_mark() { return false; }
1605 #endif
1606
1607 /**
1608 * class SkipIfEqual:
1609 *
1610 * Instantiating this class will result in assembly code being output that will
1611 * jump around any code emitted between the creation of the instance and it's
1612 * automatic destruction at the end of a scope block, depending on the value of
1613 * the flag passed to the constructor, which will be checked at run-time.
1614 */
1615 class SkipIfEqual {
1616 private:
1617 MacroAssembler* _masm;
1618 Label _label;
1619
1620 public:
1621 SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
1622 ~SkipIfEqual();
1623 };
1624
1625 struct tableswitch {
1626 Register _reg;
1627 int _insn_index; jint _first_key; jint _last_key;
1628 Label _after;
1629 Label _branches;
1630 };
1631
1632 #endif // CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP