1 /* 2 * Copyright (c) 2002, 2023, Oracle and/or its affiliates. All rights reserved. 3 * Copyright (c) 2012, 2023 SAP SE. All rights reserved. 4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 5 * 6 * This code is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 only, as 8 * published by the Free Software Foundation. 9 * 10 * This code is distributed in the hope that it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 13 * version 2 for more details (a copy is included in the LICENSE file that 14 * accompanied this code). 15 * 16 * You should have received a copy of the GNU General Public License version 17 * 2 along with this work; if not, write to the Free Software Foundation, 18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 19 * 20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 21 * or visit www.oracle.com if you need additional information or have any 22 * questions. 23 * 24 */ 25 26 #ifndef CPU_PPC_ASSEMBLER_PPC_HPP 27 #define CPU_PPC_ASSEMBLER_PPC_HPP 28 29 #include "asm/assembler.hpp" 30 #include "asm/register.hpp" 31 32 // Address is an abstraction used to represent a memory location 33 // as used in assembler instructions. 34 // PPC instructions grok either baseReg + indexReg or baseReg + disp. 35 class Address { 36 private: 37 Register _base; // Base register. 38 Register _index; // Index register. 39 intptr_t _disp; // Displacement. 40 41 public: 42 Address(Register b, Register i, address d = 0) 43 : _base(b), _index(i), _disp((intptr_t)d) { 44 assert(i == noreg || d == 0, "can't have both"); 45 } 46 47 Address(Register b, address d = 0) 48 : _base(b), _index(noreg), _disp((intptr_t)d) {} 49 50 Address(Register b, ByteSize d) 51 : _base(b), _index(noreg), _disp((intptr_t)d) {} 52 53 Address(Register b, intptr_t d) 54 : _base(b), _index(noreg), _disp(d) {} 55 56 Address(Register b, RegisterOrConstant roc) 57 : _base(b), _index(noreg), _disp(0) { 58 if (roc.is_constant()) _disp = roc.as_constant(); else _index = roc.as_register(); 59 } 60 61 Address() 62 : _base(noreg), _index(noreg), _disp(0) {} 63 64 // accessors 65 Register base() const { return _base; } 66 Register index() const { return _index; } 67 int disp() const { return (int)_disp; } 68 bool is_const() const { return _base == noreg && _index == noreg; } 69 }; 70 71 class AddressLiteral { 72 private: 73 address _address; 74 RelocationHolder _rspec; 75 76 RelocationHolder rspec_from_rtype(relocInfo::relocType rtype, address addr) { 77 switch (rtype) { 78 case relocInfo::external_word_type: 79 return external_word_Relocation::spec(addr); 80 case relocInfo::internal_word_type: 81 return internal_word_Relocation::spec(addr); 82 case relocInfo::opt_virtual_call_type: 83 return opt_virtual_call_Relocation::spec(); 84 case relocInfo::static_call_type: 85 return static_call_Relocation::spec(); 86 case relocInfo::runtime_call_type: 87 return runtime_call_Relocation::spec(); 88 case relocInfo::none: 89 return RelocationHolder(); 90 default: 91 ShouldNotReachHere(); 92 return RelocationHolder(); 93 } 94 } 95 96 protected: 97 // creation 98 AddressLiteral() : _address(nullptr), _rspec() {} 99 100 public: 101 AddressLiteral(address addr, RelocationHolder const& rspec) 102 : _address(addr), 103 _rspec(rspec) {} 104 105 AddressLiteral(address addr, relocInfo::relocType rtype = relocInfo::none) 106 : _address((address) addr), 107 _rspec(rspec_from_rtype(rtype, (address) addr)) {} 108 109 AddressLiteral(oop* addr, relocInfo::relocType rtype = relocInfo::none) 110 : _address((address) addr), 111 _rspec(rspec_from_rtype(rtype, (address) addr)) {} 112 113 intptr_t value() const { return (intptr_t) _address; } 114 115 const RelocationHolder& rspec() const { return _rspec; } 116 }; 117 118 // Argument is an abstraction used to represent an outgoing 119 // actual argument or an incoming formal parameter, whether 120 // it resides in memory or in a register, in a manner consistent 121 // with the PPC Application Binary Interface, or ABI. This is 122 // often referred to as the native or C calling convention. 123 124 class Argument { 125 private: 126 int _number; // The number of the argument. 127 public: 128 enum { 129 // Only 8 registers may contain integer parameters. 130 n_register_parameters = 8, 131 // Can have up to 8 floating registers. 132 n_float_register_parameters = 8, 133 134 // PPC C calling conventions. 135 // The first eight arguments are passed in int regs if they are int. 136 n_int_register_parameters_c = 8, 137 // The first thirteen float arguments are passed in float regs. 138 n_float_register_parameters_c = 13, 139 // Only the first 8 parameters are not placed on the stack. Aix disassembly 140 // shows that xlC places all float args after argument 8 on the stack AND 141 // in a register. This is not documented, but we follow this convention, too. 142 n_regs_not_on_stack_c = 8, 143 144 n_int_register_parameters_j = 8, // duplicates num_java_iarg_registers 145 n_float_register_parameters_j = 13, // num_java_farg_registers 146 }; 147 // creation 148 Argument(int number) : _number(number) {} 149 150 int number() const { return _number; } 151 152 // Locating register-based arguments: 153 bool is_register() const { return _number < n_register_parameters; } 154 155 Register as_register() const { 156 assert(is_register(), "must be a register argument"); 157 return as_Register(number() + R3_ARG1->encoding()); 158 } 159 }; 160 161 #if !defined(ABI_ELFv2) 162 // A ppc64 function descriptor. 163 struct FunctionDescriptor { 164 private: 165 address _entry; 166 address _toc; 167 address _env; 168 169 public: 170 inline address entry() const { return _entry; } 171 inline address toc() const { return _toc; } 172 inline address env() const { return _env; } 173 174 inline void set_entry(address entry) { _entry = entry; } 175 inline void set_toc( address toc) { _toc = toc; } 176 inline void set_env( address env) { _env = env; } 177 178 inline static ByteSize entry_offset() { return byte_offset_of(FunctionDescriptor, _entry); } 179 inline static ByteSize toc_offset() { return byte_offset_of(FunctionDescriptor, _toc); } 180 inline static ByteSize env_offset() { return byte_offset_of(FunctionDescriptor, _env); } 181 182 // Friend functions can be called without loading toc and env. 183 enum { 184 friend_toc = 0xcafe, 185 friend_env = 0xc0de 186 }; 187 188 inline bool is_friend_function() const { 189 return (toc() == (address) friend_toc) && (env() == (address) friend_env); 190 } 191 192 // Constructor for stack-allocated instances. 193 FunctionDescriptor() { 194 _entry = (address) 0xbad; 195 _toc = (address) 0xbad; 196 _env = (address) 0xbad; 197 } 198 }; 199 #endif 200 201 202 // The PPC Assembler: Pure assembler doing NO optimizations on the 203 // instruction level; i.e., what you write is what you get. The 204 // Assembler is generating code into a CodeBuffer. 205 206 class Assembler : public AbstractAssembler { 207 protected: 208 // Displacement routines 209 static int patched_branch(int dest_pos, int inst, int inst_pos); 210 static int branch_destination(int inst, int pos); 211 212 friend class AbstractAssembler; 213 214 // Code patchers need various routines like inv_wdisp() 215 friend class NativeInstruction; 216 friend class NativeGeneralJump; 217 friend class Relocation; 218 219 public: 220 221 enum shifts { 222 XO_21_29_SHIFT = 2, 223 XO_21_30_SHIFT = 1, 224 XO_27_29_SHIFT = 2, 225 XO_30_31_SHIFT = 0, 226 SPR_5_9_SHIFT = 11u, // SPR_5_9 field in bits 11 -- 15 227 SPR_0_4_SHIFT = 16u, // SPR_0_4 field in bits 16 -- 20 228 RS_SHIFT = 21u, // RS field in bits 21 -- 25 229 OPCODE_SHIFT = 26u, // opcode in bits 26 -- 31 230 231 // Shift counts in prefix word 232 PRE_TYPE_SHIFT = 24u, // Prefix type in bits 24 -- 25 233 PRE_ST1_SHIFT = 23u, // ST1 field in bits 23 -- 23 234 PRE_R_SHIFT = 20u, // R-bit in bits 20 -- 20 235 PRE_ST4_SHIFT = 20u, // ST4 field in bits 23 -- 20 236 }; 237 238 enum opcdxos_masks { 239 XL_FORM_OPCODE_MASK = (63u << OPCODE_SHIFT) | (1023u << 1), 240 ANDI_OPCODE_MASK = (63u << OPCODE_SHIFT), 241 ADDI_OPCODE_MASK = (63u << OPCODE_SHIFT), 242 ADDIS_OPCODE_MASK = (63u << OPCODE_SHIFT), 243 BXX_OPCODE_MASK = (63u << OPCODE_SHIFT), 244 BCXX_OPCODE_MASK = (63u << OPCODE_SHIFT), 245 CMPLI_OPCODE_MASK = (63u << OPCODE_SHIFT), 246 // trap instructions 247 TDI_OPCODE_MASK = (63u << OPCODE_SHIFT), 248 TWI_OPCODE_MASK = (63u << OPCODE_SHIFT), 249 TD_OPCODE_MASK = (63u << OPCODE_SHIFT) | (1023u << 1), 250 TW_OPCODE_MASK = (63u << OPCODE_SHIFT) | (1023u << 1), 251 LD_OPCODE_MASK = (63u << OPCODE_SHIFT) | (3u << XO_30_31_SHIFT), // DS-FORM 252 STD_OPCODE_MASK = LD_OPCODE_MASK, 253 STDU_OPCODE_MASK = STD_OPCODE_MASK, 254 STDX_OPCODE_MASK = (63u << OPCODE_SHIFT) | (1023u << 1), 255 STDUX_OPCODE_MASK = STDX_OPCODE_MASK, 256 STW_OPCODE_MASK = (63u << OPCODE_SHIFT), 257 STWU_OPCODE_MASK = STW_OPCODE_MASK, 258 STWX_OPCODE_MASK = (63u << OPCODE_SHIFT) | (1023u << 1), 259 STWUX_OPCODE_MASK = STWX_OPCODE_MASK, 260 MTCTR_OPCODE_MASK = ~(31u << RS_SHIFT), 261 ORI_OPCODE_MASK = (63u << OPCODE_SHIFT), 262 ORIS_OPCODE_MASK = (63u << OPCODE_SHIFT), 263 RLDICR_OPCODE_MASK = (63u << OPCODE_SHIFT) | (7u << XO_27_29_SHIFT) 264 }; 265 266 enum opcdxos { 267 ADD_OPCODE = (31u << OPCODE_SHIFT | 266u << 1), 268 ADDC_OPCODE = (31u << OPCODE_SHIFT | 10u << 1), 269 ADDI_OPCODE = (14u << OPCODE_SHIFT), 270 ADDIS_OPCODE = (15u << OPCODE_SHIFT), 271 ADDIC__OPCODE = (13u << OPCODE_SHIFT), 272 ADDE_OPCODE = (31u << OPCODE_SHIFT | 138u << 1), 273 ADDME_OPCODE = (31u << OPCODE_SHIFT | 234u << 1), 274 ADDZE_OPCODE = (31u << OPCODE_SHIFT | 202u << 1), 275 SUBF_OPCODE = (31u << OPCODE_SHIFT | 40u << 1), 276 SUBFC_OPCODE = (31u << OPCODE_SHIFT | 8u << 1), 277 SUBFE_OPCODE = (31u << OPCODE_SHIFT | 136u << 1), 278 SUBFIC_OPCODE = (8u << OPCODE_SHIFT), 279 SUBFME_OPCODE = (31u << OPCODE_SHIFT | 232u << 1), 280 SUBFZE_OPCODE = (31u << OPCODE_SHIFT | 200u << 1), 281 DIVW_OPCODE = (31u << OPCODE_SHIFT | 491u << 1), 282 DIVWU_OPCODE = (31u << OPCODE_SHIFT | 459u << 1), 283 MULLW_OPCODE = (31u << OPCODE_SHIFT | 235u << 1), 284 MULHW_OPCODE = (31u << OPCODE_SHIFT | 75u << 1), 285 MULHWU_OPCODE = (31u << OPCODE_SHIFT | 11u << 1), 286 MULLI_OPCODE = (7u << OPCODE_SHIFT), 287 AND_OPCODE = (31u << OPCODE_SHIFT | 28u << 1), 288 ANDI_OPCODE = (28u << OPCODE_SHIFT), 289 ANDIS_OPCODE = (29u << OPCODE_SHIFT), 290 ANDC_OPCODE = (31u << OPCODE_SHIFT | 60u << 1), 291 ORC_OPCODE = (31u << OPCODE_SHIFT | 412u << 1), 292 OR_OPCODE = (31u << OPCODE_SHIFT | 444u << 1), 293 ORI_OPCODE = (24u << OPCODE_SHIFT), 294 ORIS_OPCODE = (25u << OPCODE_SHIFT), 295 XOR_OPCODE = (31u << OPCODE_SHIFT | 316u << 1), 296 XORI_OPCODE = (26u << OPCODE_SHIFT), 297 XORIS_OPCODE = (27u << OPCODE_SHIFT), 298 299 NEG_OPCODE = (31u << OPCODE_SHIFT | 104u << 1), 300 301 RLWINM_OPCODE = (21u << OPCODE_SHIFT), 302 CLRRWI_OPCODE = RLWINM_OPCODE, 303 CLRLWI_OPCODE = RLWINM_OPCODE, 304 305 RLWIMI_OPCODE = (20u << OPCODE_SHIFT), 306 307 SLW_OPCODE = (31u << OPCODE_SHIFT | 24u << 1), 308 SLWI_OPCODE = RLWINM_OPCODE, 309 SRW_OPCODE = (31u << OPCODE_SHIFT | 536u << 1), 310 SRWI_OPCODE = RLWINM_OPCODE, 311 SRAW_OPCODE = (31u << OPCODE_SHIFT | 792u << 1), 312 SRAWI_OPCODE = (31u << OPCODE_SHIFT | 824u << 1), 313 314 CMP_OPCODE = (31u << OPCODE_SHIFT | 0u << 1), 315 CMPI_OPCODE = (11u << OPCODE_SHIFT), 316 CMPL_OPCODE = (31u << OPCODE_SHIFT | 32u << 1), 317 CMPLI_OPCODE = (10u << OPCODE_SHIFT), 318 CMPRB_OPCODE = (31u << OPCODE_SHIFT | 192u << 1), 319 CMPEQB_OPCODE = (31u << OPCODE_SHIFT | 224u << 1), 320 321 ISEL_OPCODE = (31u << OPCODE_SHIFT | 15u << 1), 322 323 // Special purpose registers 324 MTSPR_OPCODE = (31u << OPCODE_SHIFT | 467u << 1), 325 MFSPR_OPCODE = (31u << OPCODE_SHIFT | 339u << 1), 326 327 MTXER_OPCODE = (MTSPR_OPCODE | 1 << SPR_0_4_SHIFT), 328 MFXER_OPCODE = (MFSPR_OPCODE | 1 << SPR_0_4_SHIFT), 329 330 MTDSCR_OPCODE = (MTSPR_OPCODE | 3 << SPR_0_4_SHIFT), 331 MFDSCR_OPCODE = (MFSPR_OPCODE | 3 << SPR_0_4_SHIFT), 332 333 MTLR_OPCODE = (MTSPR_OPCODE | 8 << SPR_0_4_SHIFT), 334 MFLR_OPCODE = (MFSPR_OPCODE | 8 << SPR_0_4_SHIFT), 335 336 MTCTR_OPCODE = (MTSPR_OPCODE | 9 << SPR_0_4_SHIFT), 337 MFCTR_OPCODE = (MFSPR_OPCODE | 9 << SPR_0_4_SHIFT), 338 339 // Attention: Higher and lower half are inserted in reversed order. 340 MTTFHAR_OPCODE = (MTSPR_OPCODE | 4 << SPR_5_9_SHIFT | 0 << SPR_0_4_SHIFT), 341 MFTFHAR_OPCODE = (MFSPR_OPCODE | 4 << SPR_5_9_SHIFT | 0 << SPR_0_4_SHIFT), 342 MTTFIAR_OPCODE = (MTSPR_OPCODE | 4 << SPR_5_9_SHIFT | 1 << SPR_0_4_SHIFT), 343 MFTFIAR_OPCODE = (MFSPR_OPCODE | 4 << SPR_5_9_SHIFT | 1 << SPR_0_4_SHIFT), 344 MTTEXASR_OPCODE = (MTSPR_OPCODE | 4 << SPR_5_9_SHIFT | 2 << SPR_0_4_SHIFT), 345 MFTEXASR_OPCODE = (MFSPR_OPCODE | 4 << SPR_5_9_SHIFT | 2 << SPR_0_4_SHIFT), 346 MTTEXASRU_OPCODE = (MTSPR_OPCODE | 4 << SPR_5_9_SHIFT | 3 << SPR_0_4_SHIFT), 347 MFTEXASRU_OPCODE = (MFSPR_OPCODE | 4 << SPR_5_9_SHIFT | 3 << SPR_0_4_SHIFT), 348 349 MTVRSAVE_OPCODE = (MTSPR_OPCODE | 8 << SPR_5_9_SHIFT | 0 << SPR_0_4_SHIFT), 350 MFVRSAVE_OPCODE = (MFSPR_OPCODE | 8 << SPR_5_9_SHIFT | 0 << SPR_0_4_SHIFT), 351 352 MFTB_OPCODE = (MFSPR_OPCODE | 8 << SPR_5_9_SHIFT | 12 << SPR_0_4_SHIFT), 353 354 MTCRF_OPCODE = (31u << OPCODE_SHIFT | 144u << 1), 355 MFCR_OPCODE = (31u << OPCODE_SHIFT | 19u << 1), 356 MCRF_OPCODE = (19u << OPCODE_SHIFT | 0u << 1), 357 MCRXRX_OPCODE = (31u << OPCODE_SHIFT | 576u << 1), 358 SETB_OPCODE = (31u << OPCODE_SHIFT | 128u << 1), 359 360 SETBC_OPCODE = (31u << OPCODE_SHIFT | 384u << 1), 361 SETNBC_OPCODE = (31u << OPCODE_SHIFT | 448u << 1), 362 363 // condition register logic instructions 364 CRAND_OPCODE = (19u << OPCODE_SHIFT | 257u << 1), 365 CRNAND_OPCODE = (19u << OPCODE_SHIFT | 225u << 1), 366 CROR_OPCODE = (19u << OPCODE_SHIFT | 449u << 1), 367 CRXOR_OPCODE = (19u << OPCODE_SHIFT | 193u << 1), 368 CRNOR_OPCODE = (19u << OPCODE_SHIFT | 33u << 1), 369 CREQV_OPCODE = (19u << OPCODE_SHIFT | 289u << 1), 370 CRANDC_OPCODE = (19u << OPCODE_SHIFT | 129u << 1), 371 CRORC_OPCODE = (19u << OPCODE_SHIFT | 417u << 1), 372 373 BCLR_OPCODE = (19u << OPCODE_SHIFT | 16u << 1), 374 BXX_OPCODE = (18u << OPCODE_SHIFT), 375 BCXX_OPCODE = (16u << OPCODE_SHIFT), 376 377 // CTR-related opcodes 378 BCCTR_OPCODE = (19u << OPCODE_SHIFT | 528u << 1), 379 380 LWZ_OPCODE = (32u << OPCODE_SHIFT), 381 LWZX_OPCODE = (31u << OPCODE_SHIFT | 23u << 1), 382 LWZU_OPCODE = (33u << OPCODE_SHIFT), 383 LWBRX_OPCODE = (31u << OPCODE_SHIFT | 534 << 1), 384 385 LHA_OPCODE = (42u << OPCODE_SHIFT), 386 LHAX_OPCODE = (31u << OPCODE_SHIFT | 343u << 1), 387 LHAU_OPCODE = (43u << OPCODE_SHIFT), 388 389 LHZ_OPCODE = (40u << OPCODE_SHIFT), 390 LHZX_OPCODE = (31u << OPCODE_SHIFT | 279u << 1), 391 LHZU_OPCODE = (41u << OPCODE_SHIFT), 392 LHBRX_OPCODE = (31u << OPCODE_SHIFT | 790 << 1), 393 394 LBZ_OPCODE = (34u << OPCODE_SHIFT), 395 LBZX_OPCODE = (31u << OPCODE_SHIFT | 87u << 1), 396 LBZU_OPCODE = (35u << OPCODE_SHIFT), 397 398 STW_OPCODE = (36u << OPCODE_SHIFT), 399 STWX_OPCODE = (31u << OPCODE_SHIFT | 151u << 1), 400 STWU_OPCODE = (37u << OPCODE_SHIFT), 401 STWUX_OPCODE = (31u << OPCODE_SHIFT | 183u << 1), 402 STWBRX_OPCODE = (31u << OPCODE_SHIFT | 662u << 1), 403 404 STH_OPCODE = (44u << OPCODE_SHIFT), 405 STHX_OPCODE = (31u << OPCODE_SHIFT | 407u << 1), 406 STHU_OPCODE = (45u << OPCODE_SHIFT), 407 STHBRX_OPCODE = (31u << OPCODE_SHIFT | 918u << 1), 408 409 STB_OPCODE = (38u << OPCODE_SHIFT), 410 STBX_OPCODE = (31u << OPCODE_SHIFT | 215u << 1), 411 STBU_OPCODE = (39u << OPCODE_SHIFT), 412 413 EXTSB_OPCODE = (31u << OPCODE_SHIFT | 954u << 1), 414 EXTSH_OPCODE = (31u << OPCODE_SHIFT | 922u << 1), 415 EXTSW_OPCODE = (31u << OPCODE_SHIFT | 986u << 1), // X-FORM 416 417 // 32 bit opcode encodings 418 419 LWA_OPCODE = (58u << OPCODE_SHIFT | 2u << XO_30_31_SHIFT), // DS-FORM 420 LWAX_OPCODE = (31u << OPCODE_SHIFT | 341u << XO_21_30_SHIFT), // X-FORM 421 422 CNTLZW_OPCODE = (31u << OPCODE_SHIFT | 26u << XO_21_30_SHIFT), // X-FORM 423 CNTTZW_OPCODE = (31u << OPCODE_SHIFT | 538u << XO_21_30_SHIFT), // X-FORM 424 425 // 64 bit opcode encodings 426 427 LD_OPCODE = (58u << OPCODE_SHIFT | 0u << XO_30_31_SHIFT), // DS-FORM 428 LDU_OPCODE = (58u << OPCODE_SHIFT | 1u << XO_30_31_SHIFT), // DS-FORM 429 LDX_OPCODE = (31u << OPCODE_SHIFT | 21u << XO_21_30_SHIFT), // X-FORM 430 LDBRX_OPCODE = (31u << OPCODE_SHIFT | 532u << 1), // X-FORM 431 432 STD_OPCODE = (62u << OPCODE_SHIFT | 0u << XO_30_31_SHIFT), // DS-FORM 433 STDU_OPCODE = (62u << OPCODE_SHIFT | 1u << XO_30_31_SHIFT), // DS-FORM 434 STDUX_OPCODE = (31u << OPCODE_SHIFT | 181u << 1), // X-FORM 435 STDX_OPCODE = (31u << OPCODE_SHIFT | 149u << XO_21_30_SHIFT), // X-FORM 436 STDBRX_OPCODE = (31u << OPCODE_SHIFT | 660u << 1), // X-FORM 437 438 RLDICR_OPCODE = (30u << OPCODE_SHIFT | 1u << XO_27_29_SHIFT), // MD-FORM 439 RLDICL_OPCODE = (30u << OPCODE_SHIFT | 0u << XO_27_29_SHIFT), // MD-FORM 440 RLDIC_OPCODE = (30u << OPCODE_SHIFT | 2u << XO_27_29_SHIFT), // MD-FORM 441 RLDIMI_OPCODE = (30u << OPCODE_SHIFT | 3u << XO_27_29_SHIFT), // MD-FORM 442 443 SRADI_OPCODE = (31u << OPCODE_SHIFT | 413u << XO_21_29_SHIFT), // XS-FORM 444 445 SLD_OPCODE = (31u << OPCODE_SHIFT | 27u << 1), // X-FORM 446 SRD_OPCODE = (31u << OPCODE_SHIFT | 539u << 1), // X-FORM 447 SRAD_OPCODE = (31u << OPCODE_SHIFT | 794u << 1), // X-FORM 448 449 MULLD_OPCODE = (31u << OPCODE_SHIFT | 233u << 1), // XO-FORM 450 MULHD_OPCODE = (31u << OPCODE_SHIFT | 73u << 1), // XO-FORM 451 MULHDU_OPCODE = (31u << OPCODE_SHIFT | 9u << 1), // XO-FORM 452 DIVD_OPCODE = (31u << OPCODE_SHIFT | 489u << 1), // XO-FORM 453 DIVDU_OPCODE = (31u << OPCODE_SHIFT | 457u << 1), // XO-FORM 454 455 CNTLZD_OPCODE = (31u << OPCODE_SHIFT | 58u << XO_21_30_SHIFT), // X-FORM 456 CNTTZD_OPCODE = (31u << OPCODE_SHIFT | 570u << XO_21_30_SHIFT), // X-FORM 457 NAND_OPCODE = (31u << OPCODE_SHIFT | 476u << XO_21_30_SHIFT), // X-FORM 458 NOR_OPCODE = (31u << OPCODE_SHIFT | 124u << XO_21_30_SHIFT), // X-FORM 459 460 // Byte reverse opcodes (introduced with Power10) 461 BRH_OPCODE = (31u << OPCODE_SHIFT | 219u << 1), // X-FORM 462 BRW_OPCODE = (31u << OPCODE_SHIFT | 155u << 1), // X-FORM 463 BRD_OPCODE = (31u << OPCODE_SHIFT | 187u << 1), // X-FORM 464 465 // opcodes only used for floating arithmetic 466 FADD_OPCODE = (63u << OPCODE_SHIFT | 21u << 1), 467 FADDS_OPCODE = (59u << OPCODE_SHIFT | 21u << 1), 468 FCMPU_OPCODE = (63u << OPCODE_SHIFT | 00u << 1), 469 FDIV_OPCODE = (63u << OPCODE_SHIFT | 18u << 1), 470 FDIVS_OPCODE = (59u << OPCODE_SHIFT | 18u << 1), 471 FMR_OPCODE = (63u << OPCODE_SHIFT | 72u << 1), 472 FRIN_OPCODE = (63u << OPCODE_SHIFT | 392u << 1), 473 FRIP_OPCODE = (63u << OPCODE_SHIFT | 456u << 1), 474 FRIM_OPCODE = (63u << OPCODE_SHIFT | 488u << 1), 475 // These are special Power6 opcodes, reused for "lfdepx" and "stfdepx" 476 // on Power7. Do not use. 477 // MFFGPR_OPCODE = (31u << OPCODE_SHIFT | 607u << 1), 478 // MFTGPR_OPCODE = (31u << OPCODE_SHIFT | 735u << 1), 479 CMPB_OPCODE = (31u << OPCODE_SHIFT | 508 << 1), 480 POPCNTB_OPCODE = (31u << OPCODE_SHIFT | 122 << 1), 481 POPCNTW_OPCODE = (31u << OPCODE_SHIFT | 378 << 1), 482 POPCNTD_OPCODE = (31u << OPCODE_SHIFT | 506 << 1), 483 FABS_OPCODE = (63u << OPCODE_SHIFT | 264u << 1), 484 FNABS_OPCODE = (63u << OPCODE_SHIFT | 136u << 1), 485 FMUL_OPCODE = (63u << OPCODE_SHIFT | 25u << 1), 486 FMULS_OPCODE = (59u << OPCODE_SHIFT | 25u << 1), 487 FNEG_OPCODE = (63u << OPCODE_SHIFT | 40u << 1), 488 FSUB_OPCODE = (63u << OPCODE_SHIFT | 20u << 1), 489 FSUBS_OPCODE = (59u << OPCODE_SHIFT | 20u << 1), 490 491 // PPC64-internal FPU conversion opcodes 492 FCFID_OPCODE = (63u << OPCODE_SHIFT | 846u << 1), 493 FCFIDS_OPCODE = (59u << OPCODE_SHIFT | 846u << 1), 494 FCTID_OPCODE = (63u << OPCODE_SHIFT | 814u << 1), 495 FCTIDZ_OPCODE = (63u << OPCODE_SHIFT | 815u << 1), 496 FCTIW_OPCODE = (63u << OPCODE_SHIFT | 14u << 1), 497 FCTIWZ_OPCODE = (63u << OPCODE_SHIFT | 15u << 1), 498 FRSP_OPCODE = (63u << OPCODE_SHIFT | 12u << 1), 499 500 // Fused multiply-accumulate instructions. 501 FMADD_OPCODE = (63u << OPCODE_SHIFT | 29u << 1), 502 FMADDS_OPCODE = (59u << OPCODE_SHIFT | 29u << 1), 503 FMSUB_OPCODE = (63u << OPCODE_SHIFT | 28u << 1), 504 FMSUBS_OPCODE = (59u << OPCODE_SHIFT | 28u << 1), 505 FNMADD_OPCODE = (63u << OPCODE_SHIFT | 31u << 1), 506 FNMADDS_OPCODE = (59u << OPCODE_SHIFT | 31u << 1), 507 FNMSUB_OPCODE = (63u << OPCODE_SHIFT | 30u << 1), 508 FNMSUBS_OPCODE = (59u << OPCODE_SHIFT | 30u << 1), 509 510 LFD_OPCODE = (50u << OPCODE_SHIFT | 00u << 1), 511 LFDU_OPCODE = (51u << OPCODE_SHIFT | 00u << 1), 512 LFDX_OPCODE = (31u << OPCODE_SHIFT | 599u << 1), 513 LFS_OPCODE = (48u << OPCODE_SHIFT | 00u << 1), 514 LFSU_OPCODE = (49u << OPCODE_SHIFT | 00u << 1), 515 LFSX_OPCODE = (31u << OPCODE_SHIFT | 535u << 1), 516 517 STFD_OPCODE = (54u << OPCODE_SHIFT | 00u << 1), 518 STFDU_OPCODE = (55u << OPCODE_SHIFT | 00u << 1), 519 STFDX_OPCODE = (31u << OPCODE_SHIFT | 727u << 1), 520 STFS_OPCODE = (52u << OPCODE_SHIFT | 00u << 1), 521 STFSU_OPCODE = (53u << OPCODE_SHIFT | 00u << 1), 522 STFSX_OPCODE = (31u << OPCODE_SHIFT | 663u << 1), 523 524 FSQRT_OPCODE = (63u << OPCODE_SHIFT | 22u << 1), // A-FORM 525 FSQRTS_OPCODE = (59u << OPCODE_SHIFT | 22u << 1), // A-FORM 526 527 // Vector instruction support for >= Power6 528 // Vector Storage Access 529 LVEBX_OPCODE = (31u << OPCODE_SHIFT | 7u << 1), 530 LVEHX_OPCODE = (31u << OPCODE_SHIFT | 39u << 1), 531 LVEWX_OPCODE = (31u << OPCODE_SHIFT | 71u << 1), 532 LVX_OPCODE = (31u << OPCODE_SHIFT | 103u << 1), 533 LVXL_OPCODE = (31u << OPCODE_SHIFT | 359u << 1), 534 STVEBX_OPCODE = (31u << OPCODE_SHIFT | 135u << 1), 535 STVEHX_OPCODE = (31u << OPCODE_SHIFT | 167u << 1), 536 STVEWX_OPCODE = (31u << OPCODE_SHIFT | 199u << 1), 537 STVX_OPCODE = (31u << OPCODE_SHIFT | 231u << 1), 538 STVXL_OPCODE = (31u << OPCODE_SHIFT | 487u << 1), 539 LVSL_OPCODE = (31u << OPCODE_SHIFT | 6u << 1), 540 LVSR_OPCODE = (31u << OPCODE_SHIFT | 38u << 1), 541 542 // Vector-Scalar (VSX) instruction support. 543 LXV_OPCODE = (61u << OPCODE_SHIFT | 1u ), 544 LXVL_OPCODE = (31u << OPCODE_SHIFT | 269u << 1), 545 STXV_OPCODE = (61u << OPCODE_SHIFT | 5u ), 546 STXVL_OPCODE = (31u << OPCODE_SHIFT | 397u << 1), 547 LXVD2X_OPCODE = (31u << OPCODE_SHIFT | 844u << 1), 548 STXVD2X_OPCODE = (31u << OPCODE_SHIFT | 972u << 1), 549 MTVSRD_OPCODE = (31u << OPCODE_SHIFT | 179u << 1), 550 MTVSRDD_OPCODE = (31u << OPCODE_SHIFT | 435u << 1), 551 MTVSRWZ_OPCODE = (31u << OPCODE_SHIFT | 243u << 1), 552 MFVSRD_OPCODE = (31u << OPCODE_SHIFT | 51u << 1), 553 MTVSRWA_OPCODE = (31u << OPCODE_SHIFT | 211u << 1), 554 MFVSRWZ_OPCODE = (31u << OPCODE_SHIFT | 115u << 1), 555 XXPERMDI_OPCODE= (60u << OPCODE_SHIFT | 10u << 3), 556 XXMRGHW_OPCODE = (60u << OPCODE_SHIFT | 18u << 3), 557 XXMRGLW_OPCODE = (60u << OPCODE_SHIFT | 50u << 3), 558 XXSPLTW_OPCODE = (60u << OPCODE_SHIFT | 164u << 2), 559 XXLAND_OPCODE = (60u << OPCODE_SHIFT | 130u << 3), 560 XXLOR_OPCODE = (60u << OPCODE_SHIFT | 146u << 3), 561 XXLXOR_OPCODE = (60u << OPCODE_SHIFT | 154u << 3), 562 XXLEQV_OPCODE = (60u << OPCODE_SHIFT | 186u << 3), 563 XVDIVSP_OPCODE = (60u << OPCODE_SHIFT | 88u << 3), 564 XXBRD_OPCODE = (60u << OPCODE_SHIFT | 475u << 2 | 23u << 16), // XX2-FORM 565 XXBRW_OPCODE = (60u << OPCODE_SHIFT | 475u << 2 | 15u << 16), // XX2-FORM 566 XXPERM_OPCODE = (60u << OPCODE_SHIFT | 26u << 3), 567 XXSEL_OPCODE = (60u << OPCODE_SHIFT | 3u << 4), 568 XXSPLTIB_OPCODE= (60u << OPCODE_SHIFT | 360u << 1), 569 XVDIVDP_OPCODE = (60u << OPCODE_SHIFT | 120u << 3), 570 XVABSSP_OPCODE = (60u << OPCODE_SHIFT | 409u << 2), 571 XVABSDP_OPCODE = (60u << OPCODE_SHIFT | 473u << 2), 572 XVNEGSP_OPCODE = (60u << OPCODE_SHIFT | 441u << 2), 573 XVNEGDP_OPCODE = (60u << OPCODE_SHIFT | 505u << 2), 574 XVSQRTSP_OPCODE= (60u << OPCODE_SHIFT | 139u << 2), 575 XVSQRTDP_OPCODE= (60u << OPCODE_SHIFT | 203u << 2), 576 XSCVDPSPN_OPCODE=(60u << OPCODE_SHIFT | 267u << 2), 577 XVADDDP_OPCODE = (60u << OPCODE_SHIFT | 96u << 3), 578 XVSUBDP_OPCODE = (60u << OPCODE_SHIFT | 104u << 3), 579 XVMULSP_OPCODE = (60u << OPCODE_SHIFT | 80u << 3), 580 XVMULDP_OPCODE = (60u << OPCODE_SHIFT | 112u << 3), 581 XVMADDASP_OPCODE=(60u << OPCODE_SHIFT | 65u << 3), 582 XVMADDADP_OPCODE=(60u << OPCODE_SHIFT | 97u << 3), 583 XVMSUBASP_OPCODE=(60u << OPCODE_SHIFT | 81u << 3), 584 XVMSUBADP_OPCODE=(60u << OPCODE_SHIFT | 113u << 3), 585 XVNMSUBASP_OPCODE=(60u<< OPCODE_SHIFT | 209u << 3), 586 XVNMSUBADP_OPCODE=(60u<< OPCODE_SHIFT | 241u << 3), 587 XVRDPI_OPCODE = (60u << OPCODE_SHIFT | 201u << 2), 588 XVRDPIC_OPCODE = (60u << OPCODE_SHIFT | 235u << 2), 589 XVRDPIM_OPCODE = (60u << OPCODE_SHIFT | 249u << 2), 590 XVRDPIP_OPCODE = (60u << OPCODE_SHIFT | 233u << 2), 591 592 // Deliver A Random Number (introduced with POWER9) 593 DARN_OPCODE = (31u << OPCODE_SHIFT | 755u << 1), 594 595 // Vector Permute and Formatting 596 VPKPX_OPCODE = (4u << OPCODE_SHIFT | 782u ), 597 VPKSHSS_OPCODE = (4u << OPCODE_SHIFT | 398u ), 598 VPKSWSS_OPCODE = (4u << OPCODE_SHIFT | 462u ), 599 VPKSHUS_OPCODE = (4u << OPCODE_SHIFT | 270u ), 600 VPKSWUS_OPCODE = (4u << OPCODE_SHIFT | 334u ), 601 VPKUHUM_OPCODE = (4u << OPCODE_SHIFT | 14u ), 602 VPKUWUM_OPCODE = (4u << OPCODE_SHIFT | 78u ), 603 VPKUHUS_OPCODE = (4u << OPCODE_SHIFT | 142u ), 604 VPKUWUS_OPCODE = (4u << OPCODE_SHIFT | 206u ), 605 VUPKHPX_OPCODE = (4u << OPCODE_SHIFT | 846u ), 606 VUPKHSB_OPCODE = (4u << OPCODE_SHIFT | 526u ), 607 VUPKHSH_OPCODE = (4u << OPCODE_SHIFT | 590u ), 608 VUPKLPX_OPCODE = (4u << OPCODE_SHIFT | 974u ), 609 VUPKLSB_OPCODE = (4u << OPCODE_SHIFT | 654u ), 610 VUPKLSH_OPCODE = (4u << OPCODE_SHIFT | 718u ), 611 612 VMRGHB_OPCODE = (4u << OPCODE_SHIFT | 12u ), 613 VMRGHW_OPCODE = (4u << OPCODE_SHIFT | 140u ), 614 VMRGHH_OPCODE = (4u << OPCODE_SHIFT | 76u ), 615 VMRGLB_OPCODE = (4u << OPCODE_SHIFT | 268u ), 616 VMRGLW_OPCODE = (4u << OPCODE_SHIFT | 396u ), 617 VMRGLH_OPCODE = (4u << OPCODE_SHIFT | 332u ), 618 619 VSPLT_OPCODE = (4u << OPCODE_SHIFT | 524u ), 620 VSPLTH_OPCODE = (4u << OPCODE_SHIFT | 588u ), 621 VSPLTW_OPCODE = (4u << OPCODE_SHIFT | 652u ), 622 VSPLTISB_OPCODE= (4u << OPCODE_SHIFT | 780u ), 623 VSPLTISH_OPCODE= (4u << OPCODE_SHIFT | 844u ), 624 VSPLTISW_OPCODE= (4u << OPCODE_SHIFT | 908u ), 625 626 VPEXTD_OPCODE = (4u << OPCODE_SHIFT | 1421u ), 627 VPERM_OPCODE = (4u << OPCODE_SHIFT | 43u ), 628 VSEL_OPCODE = (4u << OPCODE_SHIFT | 42u ), 629 630 VSL_OPCODE = (4u << OPCODE_SHIFT | 452u ), 631 VSLDOI_OPCODE = (4u << OPCODE_SHIFT | 44u ), 632 VSLO_OPCODE = (4u << OPCODE_SHIFT | 1036u ), 633 VSR_OPCODE = (4u << OPCODE_SHIFT | 708u ), 634 VSRO_OPCODE = (4u << OPCODE_SHIFT | 1100u ), 635 636 // Vector Integer 637 VADDCUW_OPCODE = (4u << OPCODE_SHIFT | 384u ), 638 VADDSHS_OPCODE = (4u << OPCODE_SHIFT | 832u ), 639 VADDSBS_OPCODE = (4u << OPCODE_SHIFT | 768u ), 640 VADDSWS_OPCODE = (4u << OPCODE_SHIFT | 896u ), 641 VADDUBM_OPCODE = (4u << OPCODE_SHIFT | 0u ), 642 VADDUWM_OPCODE = (4u << OPCODE_SHIFT | 128u ), 643 VADDUHM_OPCODE = (4u << OPCODE_SHIFT | 64u ), 644 VADDUDM_OPCODE = (4u << OPCODE_SHIFT | 192u ), 645 VADDUBS_OPCODE = (4u << OPCODE_SHIFT | 512u ), 646 VADDUWS_OPCODE = (4u << OPCODE_SHIFT | 640u ), 647 VADDUHS_OPCODE = (4u << OPCODE_SHIFT | 576u ), 648 VADDFP_OPCODE = (4u << OPCODE_SHIFT | 10u ), 649 VSUBCUW_OPCODE = (4u << OPCODE_SHIFT | 1408u ), 650 VSUBSHS_OPCODE = (4u << OPCODE_SHIFT | 1856u ), 651 VSUBSBS_OPCODE = (4u << OPCODE_SHIFT | 1792u ), 652 VSUBSWS_OPCODE = (4u << OPCODE_SHIFT | 1920u ), 653 VSUBUBM_OPCODE = (4u << OPCODE_SHIFT | 1024u ), 654 VSUBUWM_OPCODE = (4u << OPCODE_SHIFT | 1152u ), 655 VSUBUHM_OPCODE = (4u << OPCODE_SHIFT | 1088u ), 656 VSUBUDM_OPCODE = (4u << OPCODE_SHIFT | 1216u ), 657 VSUBUBS_OPCODE = (4u << OPCODE_SHIFT | 1536u ), 658 VSUBUWS_OPCODE = (4u << OPCODE_SHIFT | 1664u ), 659 VSUBUHS_OPCODE = (4u << OPCODE_SHIFT | 1600u ), 660 VSUBFP_OPCODE = (4u << OPCODE_SHIFT | 74u ), 661 662 VMULESB_OPCODE = (4u << OPCODE_SHIFT | 776u ), 663 VMULEUB_OPCODE = (4u << OPCODE_SHIFT | 520u ), 664 VMULESH_OPCODE = (4u << OPCODE_SHIFT | 840u ), 665 VMULEUH_OPCODE = (4u << OPCODE_SHIFT | 584u ), 666 VMULOSB_OPCODE = (4u << OPCODE_SHIFT | 264u ), 667 VMULOUB_OPCODE = (4u << OPCODE_SHIFT | 8u ), 668 VMULOSH_OPCODE = (4u << OPCODE_SHIFT | 328u ), 669 VMULOSW_OPCODE = (4u << OPCODE_SHIFT | 392u ), 670 VMULOUH_OPCODE = (4u << OPCODE_SHIFT | 72u ), 671 VMULUWM_OPCODE = (4u << OPCODE_SHIFT | 137u ), 672 VMHADDSHS_OPCODE=(4u << OPCODE_SHIFT | 32u ), 673 VMHRADDSHS_OPCODE=(4u << OPCODE_SHIFT | 33u ), 674 VMLADDUHM_OPCODE=(4u << OPCODE_SHIFT | 34u ), 675 VMSUBUHM_OPCODE= (4u << OPCODE_SHIFT | 36u ), 676 VMSUMMBM_OPCODE= (4u << OPCODE_SHIFT | 37u ), 677 VMSUMSHM_OPCODE= (4u << OPCODE_SHIFT | 40u ), 678 VMSUMSHS_OPCODE= (4u << OPCODE_SHIFT | 41u ), 679 VMSUMUHM_OPCODE= (4u << OPCODE_SHIFT | 38u ), 680 VMSUMUHS_OPCODE= (4u << OPCODE_SHIFT | 39u ), 681 VMADDFP_OPCODE = (4u << OPCODE_SHIFT | 46u ), 682 683 VSUMSWS_OPCODE = (4u << OPCODE_SHIFT | 1928u ), 684 VSUM2SWS_OPCODE= (4u << OPCODE_SHIFT | 1672u ), 685 VSUM4SBS_OPCODE= (4u << OPCODE_SHIFT | 1800u ), 686 VSUM4UBS_OPCODE= (4u << OPCODE_SHIFT | 1544u ), 687 VSUM4SHS_OPCODE= (4u << OPCODE_SHIFT | 1608u ), 688 689 VAVGSB_OPCODE = (4u << OPCODE_SHIFT | 1282u ), 690 VAVGSW_OPCODE = (4u << OPCODE_SHIFT | 1410u ), 691 VAVGSH_OPCODE = (4u << OPCODE_SHIFT | 1346u ), 692 VAVGUB_OPCODE = (4u << OPCODE_SHIFT | 1026u ), 693 VAVGUW_OPCODE = (4u << OPCODE_SHIFT | 1154u ), 694 VAVGUH_OPCODE = (4u << OPCODE_SHIFT | 1090u ), 695 696 VMAXSB_OPCODE = (4u << OPCODE_SHIFT | 258u ), 697 VMAXSW_OPCODE = (4u << OPCODE_SHIFT | 386u ), 698 VMAXSH_OPCODE = (4u << OPCODE_SHIFT | 322u ), 699 VMAXUB_OPCODE = (4u << OPCODE_SHIFT | 2u ), 700 VMAXUW_OPCODE = (4u << OPCODE_SHIFT | 130u ), 701 VMAXUH_OPCODE = (4u << OPCODE_SHIFT | 66u ), 702 VMINSB_OPCODE = (4u << OPCODE_SHIFT | 770u ), 703 VMINSW_OPCODE = (4u << OPCODE_SHIFT | 898u ), 704 VMINSH_OPCODE = (4u << OPCODE_SHIFT | 834u ), 705 VMINUB_OPCODE = (4u << OPCODE_SHIFT | 514u ), 706 VMINUW_OPCODE = (4u << OPCODE_SHIFT | 642u ), 707 VMINUH_OPCODE = (4u << OPCODE_SHIFT | 578u ), 708 709 VCMPEQUB_OPCODE= (4u << OPCODE_SHIFT | 6u ), 710 VCMPEQUH_OPCODE= (4u << OPCODE_SHIFT | 70u ), 711 VCMPEQUW_OPCODE= (4u << OPCODE_SHIFT | 134u ), 712 VCMPGTSH_OPCODE= (4u << OPCODE_SHIFT | 838u ), 713 VCMPGTSB_OPCODE= (4u << OPCODE_SHIFT | 774u ), 714 VCMPGTSW_OPCODE= (4u << OPCODE_SHIFT | 902u ), 715 VCMPGTUB_OPCODE= (4u << OPCODE_SHIFT | 518u ), 716 VCMPGTUH_OPCODE= (4u << OPCODE_SHIFT | 582u ), 717 VCMPGTUW_OPCODE= (4u << OPCODE_SHIFT | 646u ), 718 719 VAND_OPCODE = (4u << OPCODE_SHIFT | 1028u ), 720 VANDC_OPCODE = (4u << OPCODE_SHIFT | 1092u ), 721 VNOR_OPCODE = (4u << OPCODE_SHIFT | 1284u ), 722 VOR_OPCODE = (4u << OPCODE_SHIFT | 1156u ), 723 VXOR_OPCODE = (4u << OPCODE_SHIFT | 1220u ), 724 VRLD_OPCODE = (4u << OPCODE_SHIFT | 196u ), 725 VRLB_OPCODE = (4u << OPCODE_SHIFT | 4u ), 726 VRLW_OPCODE = (4u << OPCODE_SHIFT | 132u ), 727 VRLH_OPCODE = (4u << OPCODE_SHIFT | 68u ), 728 VSLB_OPCODE = (4u << OPCODE_SHIFT | 260u ), 729 VSKW_OPCODE = (4u << OPCODE_SHIFT | 388u ), 730 VSLH_OPCODE = (4u << OPCODE_SHIFT | 324u ), 731 VSRB_OPCODE = (4u << OPCODE_SHIFT | 516u ), 732 VSRW_OPCODE = (4u << OPCODE_SHIFT | 644u ), 733 VSRH_OPCODE = (4u << OPCODE_SHIFT | 580u ), 734 VSRAB_OPCODE = (4u << OPCODE_SHIFT | 772u ), 735 VSRAW_OPCODE = (4u << OPCODE_SHIFT | 900u ), 736 VSRAH_OPCODE = (4u << OPCODE_SHIFT | 836u ), 737 VPOPCNTB_OPCODE= (4u << OPCODE_SHIFT | 1795u ), 738 VPOPCNTH_OPCODE= (4u << OPCODE_SHIFT | 1859u ), 739 VPOPCNTW_OPCODE= (4u << OPCODE_SHIFT | 1923u ), 740 VPOPCNTD_OPCODE= (4u << OPCODE_SHIFT | 1987u ), 741 742 // Vector Floating-Point 743 // not implemented yet 744 745 // Vector Status and Control 746 MTVSCR_OPCODE = (4u << OPCODE_SHIFT | 1604u ), 747 MFVSCR_OPCODE = (4u << OPCODE_SHIFT | 1540u ), 748 749 // AES (introduced with Power 8) 750 VCIPHER_OPCODE = (4u << OPCODE_SHIFT | 1288u), 751 VCIPHERLAST_OPCODE = (4u << OPCODE_SHIFT | 1289u), 752 VNCIPHER_OPCODE = (4u << OPCODE_SHIFT | 1352u), 753 VNCIPHERLAST_OPCODE = (4u << OPCODE_SHIFT | 1353u), 754 VSBOX_OPCODE = (4u << OPCODE_SHIFT | 1480u), 755 756 // SHA (introduced with Power 8) 757 VSHASIGMAD_OPCODE = (4u << OPCODE_SHIFT | 1730u), 758 VSHASIGMAW_OPCODE = (4u << OPCODE_SHIFT | 1666u), 759 760 // Vector Binary Polynomial Multiplication (introduced with Power 8) 761 VPMSUMB_OPCODE = (4u << OPCODE_SHIFT | 1032u), 762 VPMSUMD_OPCODE = (4u << OPCODE_SHIFT | 1224u), 763 VPMSUMH_OPCODE = (4u << OPCODE_SHIFT | 1096u), 764 VPMSUMW_OPCODE = (4u << OPCODE_SHIFT | 1160u), 765 766 // Vector Permute and Xor (introduced with Power 8) 767 VPERMXOR_OPCODE = (4u << OPCODE_SHIFT | 45u), 768 769 // Transactional Memory instructions (introduced with Power 8) 770 TBEGIN_OPCODE = (31u << OPCODE_SHIFT | 654u << 1), 771 TEND_OPCODE = (31u << OPCODE_SHIFT | 686u << 1), 772 TABORT_OPCODE = (31u << OPCODE_SHIFT | 910u << 1), 773 TABORTWC_OPCODE = (31u << OPCODE_SHIFT | 782u << 1), 774 TABORTWCI_OPCODE = (31u << OPCODE_SHIFT | 846u << 1), 775 TABORTDC_OPCODE = (31u << OPCODE_SHIFT | 814u << 1), 776 TABORTDCI_OPCODE = (31u << OPCODE_SHIFT | 878u << 1), 777 TSR_OPCODE = (31u << OPCODE_SHIFT | 750u << 1), 778 TCHECK_OPCODE = (31u << OPCODE_SHIFT | 718u << 1), 779 780 // Icache and dcache related instructions 781 DCBA_OPCODE = (31u << OPCODE_SHIFT | 758u << 1), 782 DCBZ_OPCODE = (31u << OPCODE_SHIFT | 1014u << 1), 783 DCBST_OPCODE = (31u << OPCODE_SHIFT | 54u << 1), 784 DCBF_OPCODE = (31u << OPCODE_SHIFT | 86u << 1), 785 786 DCBT_OPCODE = (31u << OPCODE_SHIFT | 278u << 1), 787 DCBTST_OPCODE = (31u << OPCODE_SHIFT | 246u << 1), 788 ICBI_OPCODE = (31u << OPCODE_SHIFT | 982u << 1), 789 790 // Instruction synchronization 791 ISYNC_OPCODE = (19u << OPCODE_SHIFT | 150u << 1), 792 // Memory barriers 793 SYNC_OPCODE = (31u << OPCODE_SHIFT | 598u << 1), 794 EIEIO_OPCODE = (31u << OPCODE_SHIFT | 854u << 1), 795 796 // Wait instructions for polling. 797 WAIT_OPCODE = (31u << OPCODE_SHIFT | 62u << 1), 798 799 // Trap instructions 800 TDI_OPCODE = (2u << OPCODE_SHIFT), 801 TWI_OPCODE = (3u << OPCODE_SHIFT), 802 TD_OPCODE = (31u << OPCODE_SHIFT | 68u << 1), 803 TW_OPCODE = (31u << OPCODE_SHIFT | 4u << 1), 804 805 // Atomics. 806 LBARX_OPCODE = (31u << OPCODE_SHIFT | 52u << 1), 807 LHARX_OPCODE = (31u << OPCODE_SHIFT | 116u << 1), 808 LWARX_OPCODE = (31u << OPCODE_SHIFT | 20u << 1), 809 LDARX_OPCODE = (31u << OPCODE_SHIFT | 84u << 1), 810 LQARX_OPCODE = (31u << OPCODE_SHIFT | 276u << 1), 811 STBCX_OPCODE = (31u << OPCODE_SHIFT | 694u << 1), 812 STHCX_OPCODE = (31u << OPCODE_SHIFT | 726u << 1), 813 STWCX_OPCODE = (31u << OPCODE_SHIFT | 150u << 1), 814 STDCX_OPCODE = (31u << OPCODE_SHIFT | 214u << 1), 815 STQCX_OPCODE = (31u << OPCODE_SHIFT | 182u << 1) 816 817 }; 818 819 enum opcdeos_mask { 820 // Mask for prefix primary opcode field 821 PREFIX_OPCODE_MASK = (63u << OPCODE_SHIFT), 822 // Mask for prefix opcode and type fields 823 PREFIX_OPCODE_TYPE_MASK = (63u << OPCODE_SHIFT) | (3u << PRE_TYPE_SHIFT), 824 // Masks for type 00/10 and type 01/11, including opcode, type, and st fieds 825 PREFIX_OPCODE_TYPEx0_MASK = PREFIX_OPCODE_TYPE_MASK | ( 1u << PRE_ST1_SHIFT), 826 PREFIX_OPCODE_TYPEx1_MASK = PREFIX_OPCODE_TYPE_MASK | (15u << PRE_ST4_SHIFT), 827 828 // Masks for each instructions 829 PADDI_PREFIX_OPCODE_MASK = PREFIX_OPCODE_TYPEx0_MASK, 830 PADDI_SUFFIX_OPCODE_MASK = ADDI_OPCODE_MASK, 831 }; 832 833 enum opcdeos { 834 PREFIX_PRIMARY_OPCODE = (1u << OPCODE_SHIFT), 835 836 // Prefixed addi/li 837 PADDI_PREFIX_OPCODE = PREFIX_PRIMARY_OPCODE | (2u << PRE_TYPE_SHIFT), 838 PADDI_SUFFIX_OPCODE = ADDI_OPCODE, 839 840 // xxpermx 841 XXPERMX_PREFIX_OPCODE = PREFIX_PRIMARY_OPCODE | (1u << PRE_TYPE_SHIFT), 842 XXPERMX_SUFFIX_OPCODE = (34u << OPCODE_SHIFT), 843 }; 844 845 // Trap instructions TO bits 846 enum trap_to_bits { 847 // single bits 848 traptoLessThanSigned = 1 << 4, // 0, left end 849 traptoGreaterThanSigned = 1 << 3, 850 traptoEqual = 1 << 2, 851 traptoLessThanUnsigned = 1 << 1, 852 traptoGreaterThanUnsigned = 1 << 0, // 4, right end 853 854 // compound ones 855 traptoUnconditional = (traptoLessThanSigned | 856 traptoGreaterThanSigned | 857 traptoEqual | 858 traptoLessThanUnsigned | 859 traptoGreaterThanUnsigned) 860 }; 861 862 // Branch hints BH field 863 enum branch_hint_bh { 864 // bclr cases: 865 bhintbhBCLRisReturn = 0, 866 bhintbhBCLRisNotReturnButSame = 1, 867 bhintbhBCLRisNotPredictable = 3, 868 869 // bcctr cases: 870 bhintbhBCCTRisNotReturnButSame = 0, 871 bhintbhBCCTRisNotPredictable = 3 872 }; 873 874 // Branch prediction hints AT field 875 enum branch_hint_at { 876 bhintatNoHint = 0, // at=00 877 bhintatIsNotTaken = 2, // at=10 878 bhintatIsTaken = 3 // at=11 879 }; 880 881 // Branch prediction hints 882 enum branch_hint_concept { 883 // Use the same encoding as branch_hint_at to simply code. 884 bhintNoHint = bhintatNoHint, 885 bhintIsNotTaken = bhintatIsNotTaken, 886 bhintIsTaken = bhintatIsTaken 887 }; 888 889 // Used in BO field of branch instruction. 890 enum branch_condition { 891 bcondCRbiIs0 = 4, // bo=001at 892 bcondCRbiIs1 = 12, // bo=011at 893 bcondAlways = 20 // bo=10100 894 }; 895 896 // Branch condition with combined prediction hints. 897 enum branch_condition_with_hint { 898 bcondCRbiIs0_bhintNoHint = bcondCRbiIs0 | bhintatNoHint, 899 bcondCRbiIs0_bhintIsNotTaken = bcondCRbiIs0 | bhintatIsNotTaken, 900 bcondCRbiIs0_bhintIsTaken = bcondCRbiIs0 | bhintatIsTaken, 901 bcondCRbiIs1_bhintNoHint = bcondCRbiIs1 | bhintatNoHint, 902 bcondCRbiIs1_bhintIsNotTaken = bcondCRbiIs1 | bhintatIsNotTaken, 903 bcondCRbiIs1_bhintIsTaken = bcondCRbiIs1 | bhintatIsTaken, 904 }; 905 906 // Elemental Memory Barriers (>=Power 8) 907 enum Elemental_Membar_mask_bits { 908 StoreStore = 1 << 0, 909 StoreLoad = 1 << 1, 910 LoadStore = 1 << 2, 911 LoadLoad = 1 << 3 912 }; 913 914 // Branch prediction hints. 915 inline static int add_bhint_to_boint(const int bhint, const int boint) { 916 switch (boint) { 917 case bcondCRbiIs0: 918 case bcondCRbiIs1: 919 // branch_hint and branch_hint_at have same encodings 920 assert( (int)bhintNoHint == (int)bhintatNoHint 921 && (int)bhintIsNotTaken == (int)bhintatIsNotTaken 922 && (int)bhintIsTaken == (int)bhintatIsTaken, 923 "wrong encodings"); 924 assert((bhint & 0x03) == bhint, "wrong encodings"); 925 return (boint & ~0x03) | bhint; 926 case bcondAlways: 927 // no branch_hint 928 return boint; 929 default: 930 ShouldNotReachHere(); 931 return 0; 932 } 933 } 934 935 // Extract bcond from boint. 936 inline static int inv_boint_bcond(const int boint) { 937 int r_bcond = boint & ~0x03; 938 assert(r_bcond == bcondCRbiIs0 || 939 r_bcond == bcondCRbiIs1 || 940 r_bcond == bcondAlways, 941 "bad branch condition"); 942 return r_bcond; 943 } 944 945 // Extract bhint from boint. 946 inline static int inv_boint_bhint(const int boint) { 947 int r_bhint = boint & 0x03; 948 assert(r_bhint == bhintatNoHint || 949 r_bhint == bhintatIsNotTaken || 950 r_bhint == bhintatIsTaken, 951 "bad branch hint"); 952 return r_bhint; 953 } 954 955 // Calculate opposite of given bcond. 956 inline static int opposite_bcond(const int bcond) { 957 switch (bcond) { 958 case bcondCRbiIs0: 959 return bcondCRbiIs1; 960 case bcondCRbiIs1: 961 return bcondCRbiIs0; 962 default: 963 ShouldNotReachHere(); 964 return 0; 965 } 966 } 967 968 // Calculate opposite of given bhint. 969 inline static int opposite_bhint(const int bhint) { 970 switch (bhint) { 971 case bhintatNoHint: 972 return bhintatNoHint; 973 case bhintatIsNotTaken: 974 return bhintatIsTaken; 975 case bhintatIsTaken: 976 return bhintatIsNotTaken; 977 default: 978 ShouldNotReachHere(); 979 return 0; 980 } 981 } 982 983 // PPC branch instructions 984 enum ppcops { 985 b_op = 18, 986 bc_op = 16, 987 bcr_op = 19 988 }; 989 990 enum Condition { 991 negative = 0, 992 less = 0, 993 positive = 1, 994 greater = 1, 995 zero = 2, 996 equal = 2, 997 summary_overflow = 3, 998 }; 999 1000 public: 1001 // Helper functions for groups of instructions 1002 1003 enum Predict { pt = 1, pn = 0 }; // pt = predict taken 1004 1005 //---< calculate length of instruction >--- 1006 // With PPC64 being a RISC architecture, this always is BytesPerInstWord 1007 // instruction must start at passed address 1008 static unsigned int instr_len(unsigned char *instr) { return BytesPerInstWord; } 1009 1010 //---< longest instructions >--- 1011 static unsigned int instr_maxlen() { return BytesPerInstWord; } 1012 1013 // Test if x is within signed immediate range for nbits. 1014 static bool is_simm(int x, unsigned int nbits) { 1015 assert(0 < nbits && nbits < 32, "out of bounds"); 1016 const int min = -(((int)1) << (nbits-1)); 1017 const int maxplus1 = (((int)1) << (nbits-1)); 1018 return min <= x && x < maxplus1; 1019 } 1020 1021 static bool is_simm(jlong x, unsigned int nbits) { 1022 assert(0 < nbits && nbits < 64, "out of bounds"); 1023 const jlong min = -(((jlong)1) << (nbits-1)); 1024 const jlong maxplus1 = (((jlong)1) << (nbits-1)); 1025 return min <= x && x < maxplus1; 1026 } 1027 1028 // Test if x is within unsigned immediate range for nbits. 1029 static bool is_uimm(int x, unsigned int nbits) { 1030 assert(0 < nbits && nbits < 32, "out of bounds"); 1031 const unsigned int maxplus1 = (((unsigned int)1) << nbits); 1032 return (unsigned int)x < maxplus1; 1033 } 1034 1035 static bool is_uimm(jlong x, unsigned int nbits) { 1036 assert(0 < nbits && nbits < 64, "out of bounds"); 1037 const julong maxplus1 = (((julong)1) << nbits); 1038 return (julong)x < maxplus1; 1039 } 1040 1041 protected: 1042 // helpers 1043 1044 // X is supposed to fit in a field "nbits" wide 1045 // and be sign-extended. Check the range. 1046 static void assert_signed_range(intptr_t x, int nbits) { 1047 assert(nbits == 32 || (-(1 << (nbits-1)) <= x && x < (1 << (nbits-1))), 1048 "value out of range"); 1049 } 1050 1051 static void assert_signed_word_disp_range(intptr_t x, int nbits) { 1052 assert((x & 3) == 0, "not word aligned"); 1053 assert_signed_range(x, nbits + 2); 1054 } 1055 1056 static void assert_unsigned_const(int x, int nbits) { 1057 assert(juint(x) < juint(1 << nbits), "unsigned constant out of range"); 1058 } 1059 1060 static int fmask(juint hi_bit, juint lo_bit) { 1061 assert(hi_bit >= lo_bit && hi_bit < 32, "bad bits"); 1062 return (1 << ( hi_bit-lo_bit + 1 )) - 1; 1063 } 1064 1065 // inverse of u_field 1066 static int inv_u_field(int x, int hi_bit, int lo_bit) { 1067 juint r = juint(x) >> lo_bit; 1068 r &= fmask(hi_bit, lo_bit); 1069 return int(r); 1070 } 1071 1072 // signed version: extract from field and sign-extend 1073 static int inv_s_field_ppc(int x, int hi_bit, int lo_bit) { 1074 x = x << (31-hi_bit); 1075 x = x >> (31-hi_bit+lo_bit); 1076 return x; 1077 } 1078 1079 static int u_field(int x, int hi_bit, int lo_bit) { 1080 assert((x & ~fmask(hi_bit, lo_bit)) == 0, "value out of range"); 1081 int r = x << lo_bit; 1082 assert(inv_u_field(r, hi_bit, lo_bit) == x, "just checking"); 1083 return r; 1084 } 1085 1086 // Same as u_field for signed values 1087 static int s_field(int x, int hi_bit, int lo_bit) { 1088 int nbits = hi_bit - lo_bit + 1; 1089 assert(nbits == 32 || (-(1 << (nbits-1)) <= x && x < (1 << (nbits-1))), 1090 "value out of range"); 1091 x &= fmask(hi_bit, lo_bit); 1092 int r = x << lo_bit; 1093 return r; 1094 } 1095 1096 // inv_op for ppc instructions 1097 static int inv_op_ppc(int x) { return inv_u_field(x, 31, 26); } 1098 1099 // Determine target address from li, bd field of branch instruction. 1100 static intptr_t inv_li_field(int x) { 1101 intptr_t r = inv_s_field_ppc(x, 25, 2); 1102 r = (r << 2); 1103 return r; 1104 } 1105 static intptr_t inv_bd_field(int x, intptr_t pos) { 1106 intptr_t r = inv_s_field_ppc(x, 15, 2); 1107 r = (r << 2) + pos; 1108 return r; 1109 } 1110 1111 #define inv_opp_u_field(x, hi_bit, lo_bit) inv_u_field(x, 31-(lo_bit), 31-(hi_bit)) 1112 #define inv_opp_s_field(x, hi_bit, lo_bit) inv_s_field_ppc(x, 31-(lo_bit), 31-(hi_bit)) 1113 // Extract instruction fields from instruction words. 1114 public: 1115 static int inv_ra_field(int x) { return inv_opp_u_field(x, 15, 11); } 1116 static int inv_rb_field(int x) { return inv_opp_u_field(x, 20, 16); } 1117 static int inv_rt_field(int x) { return inv_opp_u_field(x, 10, 6); } 1118 static int inv_rta_field(int x) { return inv_opp_u_field(x, 15, 11); } 1119 static int inv_rs_field(int x) { return inv_opp_u_field(x, 10, 6); } 1120 // Ds uses opp_s_field(x, 31, 16), but lowest 2 bits must be 0. 1121 // Inv_ds_field uses range (x, 29, 16) but shifts by 2 to ensure that lowest bits are 0. 1122 static int inv_ds_field(int x) { return inv_opp_s_field(x, 29, 16) << 2; } 1123 static int inv_d1_field(int x) { return inv_opp_s_field(x, 31, 16); } 1124 static int inv_si_field(int x) { return inv_opp_s_field(x, 31, 16); } 1125 static int inv_to_field(int x) { return inv_opp_u_field(x, 10, 6); } 1126 static int inv_lk_field(int x) { return inv_opp_u_field(x, 31, 31); } 1127 static int inv_bo_field(int x) { return inv_opp_u_field(x, 10, 6); } 1128 static int inv_bi_field(int x) { return inv_opp_u_field(x, 15, 11); } 1129 1130 // For extended opcodes (prefixed instructions) introduced with Power 10 1131 static long inv_r_eo( int x) { return inv_opp_u_field(x, 11, 11); } 1132 static long inv_type( int x) { return inv_opp_u_field(x, 7, 6); } 1133 static long inv_st_x0( int x) { return inv_opp_u_field(x, 8, 8); } 1134 static long inv_st_x1( int x) { return inv_opp_u_field(x, 11, 8); } 1135 1136 // - 8LS:D/MLS:D Formats 1137 static long inv_d0_eo( long x) { return inv_opp_u_field(x, 31, 14); } 1138 1139 // - 8RR:XX4/8RR:D Formats 1140 static long inv_imm0_eo(int x) { return inv_opp_u_field(x, 31, 16); } 1141 static long inv_uimm_eo(int x) { return inv_opp_u_field(x, 31, 29); } 1142 static long inv_imm_eo( int x) { return inv_opp_u_field(x, 31, 24); } 1143 1144 #define opp_u_field(x, hi_bit, lo_bit) u_field(x, 31-(lo_bit), 31-(hi_bit)) 1145 #define opp_s_field(x, hi_bit, lo_bit) s_field(x, 31-(lo_bit), 31-(hi_bit)) 1146 1147 // instruction fields 1148 static int aa( int x) { return opp_u_field(x, 30, 30); } 1149 static int ba( int x) { return opp_u_field(x, 15, 11); } 1150 static int bb( int x) { return opp_u_field(x, 20, 16); } 1151 static int bc( int x) { return opp_u_field(x, 25, 21); } 1152 static int bd( int x) { return opp_s_field(x, 29, 16); } 1153 static int bf( ConditionRegister cr) { return bf(cr->encoding()); } 1154 static int bf( int x) { return opp_u_field(x, 8, 6); } 1155 static int bfa(ConditionRegister cr) { return bfa(cr->encoding()); } 1156 static int bfa( int x) { return opp_u_field(x, 13, 11); } 1157 static int bh( int x) { return opp_u_field(x, 20, 19); } 1158 static int bi( int x) { return opp_u_field(x, 15, 11); } 1159 static int bi0(ConditionRegister cr, Condition c) { return (cr->encoding() << 2) | c; } 1160 static int bo( int x) { return opp_u_field(x, 10, 6); } 1161 static int bt( int x) { return opp_u_field(x, 10, 6); } 1162 static int d1( int x) { return opp_s_field(x, 31, 16); } 1163 static int ds( int x) { assert((x & 0x3) == 0, "unaligned offset"); return opp_s_field(x, 31, 16); } 1164 static int eh( int x) { return opp_u_field(x, 31, 31); } 1165 static int flm( int x) { return opp_u_field(x, 14, 7); } 1166 static int fra( FloatRegister r) { return fra(r->encoding());} 1167 static int frb( FloatRegister r) { return frb(r->encoding());} 1168 static int frc( FloatRegister r) { return frc(r->encoding());} 1169 static int frs( FloatRegister r) { return frs(r->encoding());} 1170 static int frt( FloatRegister r) { return frt(r->encoding());} 1171 static int fra( int x) { return opp_u_field(x, 15, 11); } 1172 static int frb( int x) { return opp_u_field(x, 20, 16); } 1173 static int frc( int x) { return opp_u_field(x, 25, 21); } 1174 static int frs( int x) { return opp_u_field(x, 10, 6); } 1175 static int frt( int x) { return opp_u_field(x, 10, 6); } 1176 static int fxm( int x) { return opp_u_field(x, 19, 12); } 1177 static int imm8( int x) { return opp_u_field(uimm(x, 8), 20, 13); } 1178 static int l10( int x) { assert(x == 0 || x == 1, "must be 0 or 1"); return opp_u_field(x, 10, 10); } 1179 static int l14( int x) { return opp_u_field(x, 15, 14); } 1180 static int l15( int x) { return opp_u_field(x, 15, 15); } 1181 static int l910( int x) { return opp_u_field(x, 10, 9); } 1182 static int e1215( int x) { return opp_u_field(x, 15, 12); } 1183 static int lev( int x) { return opp_u_field(x, 26, 20); } 1184 static int li( int x) { return opp_s_field(x, 29, 6); } 1185 static int lk( int x) { return opp_u_field(x, 31, 31); } 1186 static int mb2125( int x) { return opp_u_field(x, 25, 21); } 1187 static int me2630( int x) { return opp_u_field(x, 30, 26); } 1188 static int mb2126( int x) { return opp_u_field(((x & 0x1f) << 1) | ((x & 0x20) >> 5), 26, 21); } 1189 static int me2126( int x) { return mb2126(x); } 1190 static int nb( int x) { return opp_u_field(x, 20, 16); } 1191 //static int opcd( int x) { return opp_u_field(x, 5, 0); } // is contained in our opcodes 1192 static int oe( int x) { return opp_u_field(x, 21, 21); } 1193 static int ra( Register r) { return ra(r->encoding()); } 1194 static int ra( int x) { return opp_u_field(x, 15, 11); } 1195 static int rb( Register r) { return rb(r->encoding()); } 1196 static int rb( int x) { return opp_u_field(x, 20, 16); } 1197 static int rc( int x) { return opp_u_field(x, 31, 31); } 1198 static int rs( Register r) { return rs(r->encoding()); } 1199 static int rs( int x) { return opp_u_field(x, 10, 6); } 1200 // we don't want to use R0 in memory accesses, because it has value `0' then 1201 static int ra0mem( Register r) { assert(r != R0, "cannot use register R0 in memory access"); return ra(r); } 1202 static int ra0mem( int x) { assert(x != 0, "cannot use register 0 in memory access"); return ra(x); } 1203 1204 // register r is target 1205 static int rt( Register r) { return rs(r); } 1206 static int rt( int x) { return rs(x); } 1207 static int rta( Register r) { return ra(r); } 1208 static int rta0mem( Register r) { rta(r); return ra0mem(r); } 1209 1210 static int sh1620( int x) { return opp_u_field(x, 20, 16); } 1211 static int sh30( int x) { return opp_u_field(x, 30, 30); } 1212 static int sh162030( int x) { return sh1620(x & 0x1f) | sh30((x & 0x20) >> 5); } 1213 static int si( int x) { return opp_s_field(x, 31, 16); } 1214 static int spr( int x) { return opp_u_field(x, 20, 11); } 1215 static int sr( int x) { return opp_u_field(x, 15, 12); } 1216 static int tbr( int x) { return opp_u_field(x, 20, 11); } 1217 static int th( int x) { return opp_u_field(x, 10, 7); } 1218 static int thct( int x) { assert((x&8) == 0, "must be valid cache specification"); return th(x); } 1219 static int thds( int x) { assert((x&8) == 8, "must be valid stream specification"); return th(x); } 1220 static int to( int x) { return opp_u_field(x, 10, 6); } 1221 static int u( int x) { return opp_u_field(x, 19, 16); } 1222 static int ui( int x) { return opp_u_field(x, 31, 16); } 1223 1224 // Support vector instructions for >= Power6. 1225 static int vra( int x) { return opp_u_field(x, 15, 11); } 1226 static int vrb( int x) { return opp_u_field(x, 20, 16); } 1227 static int vrc( int x) { return opp_u_field(x, 25, 21); } 1228 static int vrs( int x) { return opp_u_field(x, 10, 6); } 1229 static int vrt( int x) { return opp_u_field(x, 10, 6); } 1230 1231 static int vra( VectorRegister r) { return vra(r->encoding());} 1232 static int vrb( VectorRegister r) { return vrb(r->encoding());} 1233 static int vrc( VectorRegister r) { return vrc(r->encoding());} 1234 static int vrs( VectorRegister r) { return vrs(r->encoding());} 1235 static int vrt( VectorRegister r) { return vrt(r->encoding());} 1236 1237 // Only used on SHA sigma instructions (VX-form) 1238 static int vst( int x) { return opp_u_field(x, 16, 16); } 1239 static int vsix( int x) { return opp_u_field(x, 20, 17); } 1240 1241 // Support Vector-Scalar (VSX) instructions. 1242 static int vsra( int x) { return opp_u_field(x & 0x1F, 15, 11) | opp_u_field((x & 0x20) >> 5, 29, 29); } 1243 static int vsrb( int x) { return opp_u_field(x & 0x1F, 20, 16) | opp_u_field((x & 0x20) >> 5, 30, 30); } 1244 static int vsrc( int x) { return opp_u_field(x & 0x1F, 25, 21) | opp_u_field((x & 0x20) >> 5, 28, 28); } 1245 static int vsrs( int x) { return opp_u_field(x & 0x1F, 10, 6) | opp_u_field((x & 0x20) >> 5, 31, 31); } 1246 static int vsrt( int x) { return vsrs(x); } 1247 static int vsdm( int x) { return opp_u_field(x, 23, 22); } 1248 static int vsrs_dq( int x) { return opp_u_field(x & 0x1F, 10, 6) | opp_u_field((x & 0x20) >> 5, 28, 28); } 1249 static int vsrt_dq( int x) { return vsrs_dq(x); } 1250 1251 static int vsra( VectorSRegister r) { return vsra(r->encoding());} 1252 static int vsrb( VectorSRegister r) { return vsrb(r->encoding());} 1253 static int vsrc( VectorSRegister r) { return vsrc(r->encoding());} 1254 static int vsrs( VectorSRegister r) { return vsrs(r->encoding());} 1255 static int vsrt( VectorSRegister r) { return vsrt(r->encoding());} 1256 static int vsrs_dq(VectorSRegister r) { return vsrs_dq(r->encoding());} 1257 static int vsrt_dq(VectorSRegister r) { return vsrt_dq(r->encoding());} 1258 1259 static int vsplt_uim( int x) { return opp_u_field(x, 15, 12); } // for vsplt* instructions 1260 static int vsplti_sim(int x) { return opp_u_field(x, 15, 11); } // for vsplti* instructions 1261 static int vsldoi_shb(int x) { return opp_u_field(x, 25, 22); } // for vsldoi instruction 1262 static int vcmp_rc( int x) { return opp_u_field(x, 21, 21); } // for vcmp* instructions 1263 static int xxsplt_uim(int x) { return opp_u_field(x, 15, 14); } // for xxsplt* instructions 1264 1265 // For extended opcodes (prefixed instructions) introduced with Power 10 1266 static long r_eo( int x) { return opp_u_field(x, 11, 11); } 1267 static long type( int x) { return opp_u_field(x, 7, 6); } 1268 static long st_x0( int x) { return opp_u_field(x, 8, 8); } 1269 static long st_x1( int x) { return opp_u_field(x, 11, 8); } 1270 1271 // - 8LS:D/MLS:D Formats 1272 static long d0_eo( long x) { return opp_u_field((x >> 16) & 0x3FFFF, 31, 14); } 1273 static long d1_eo( long x) { return opp_u_field(x & 0xFFFF, 31, 16); } 1274 static long s0_eo( long x) { return d0_eo(x); } 1275 static long s1_eo( long x) { return d1_eo(x); } 1276 1277 // - 8RR:XX4/8RR:D Formats 1278 static long imm0_eo( int x) { return opp_u_field(x >> 16, 31, 16); } 1279 static long imm1_eo( int x) { return opp_u_field(x & 0xFFFF, 31, 16); } 1280 static long uimm_eo( int x) { return opp_u_field(x, 31, 29); } 1281 static long imm_eo( int x) { return opp_u_field(x, 31, 24); } 1282 1283 //static int xo1( int x) { return opp_u_field(x, 29, 21); }// is contained in our opcodes 1284 //static int xo2( int x) { return opp_u_field(x, 30, 21); }// is contained in our opcodes 1285 //static int xo3( int x) { return opp_u_field(x, 30, 22); }// is contained in our opcodes 1286 //static int xo4( int x) { return opp_u_field(x, 30, 26); }// is contained in our opcodes 1287 //static int xo5( int x) { return opp_u_field(x, 29, 27); }// is contained in our opcodes 1288 //static int xo6( int x) { return opp_u_field(x, 30, 27); }// is contained in our opcodes 1289 //static int xo7( int x) { return opp_u_field(x, 31, 30); }// is contained in our opcodes 1290 1291 protected: 1292 // Compute relative address for branch. 1293 static intptr_t disp(intptr_t x, intptr_t off) { 1294 int xx = x - off; 1295 xx = xx >> 2; 1296 return xx; 1297 } 1298 1299 public: 1300 // signed immediate, in low bits, nbits long 1301 static int simm(int x, int nbits) { 1302 assert_signed_range(x, nbits); 1303 return x & ((1 << nbits) - 1); 1304 } 1305 1306 // unsigned immediate, in low bits, nbits long 1307 static int uimm(int x, int nbits) { 1308 assert_unsigned_const(x, nbits); 1309 return x & ((1 << nbits) - 1); 1310 } 1311 1312 static void set_imm(int* instr, short s) { 1313 // imm is always in the lower 16 bits of the instruction, 1314 // so this is endian-neutral. Same for the get_imm below. 1315 uint32_t w = *(uint32_t *)instr; 1316 *instr = (int)((w & ~0x0000FFFF) | (s & 0x0000FFFF)); 1317 } 1318 1319 static int get_imm(address a, int instruction_number) { 1320 return (short)((int *)a)[instruction_number]; 1321 } 1322 1323 static inline int hi16_signed( int x) { return (int)(int16_t)(x >> 16); } 1324 static inline int lo16_unsigned(int x) { return x & 0xffff; } 1325 1326 protected: 1327 1328 // Extract the top 32 bits in a 64 bit word. 1329 static int32_t hi32(int64_t x) { 1330 int32_t r = int32_t((uint64_t)x >> 32); 1331 return r; 1332 } 1333 1334 public: 1335 1336 static inline unsigned int align_addr(unsigned int addr, unsigned int a) { 1337 return ((addr + (a - 1)) & ~(a - 1)); 1338 } 1339 1340 static inline bool is_aligned(unsigned int addr, unsigned int a) { 1341 return (0 == addr % a); 1342 } 1343 1344 void flush() { 1345 AbstractAssembler::flush(); 1346 } 1347 1348 inline void emit_int32(int); // shadows AbstractAssembler::emit_int32 1349 inline void emit_data(int); 1350 inline void emit_data(int, RelocationHolder const&); 1351 inline void emit_data(int, relocInfo::relocType rtype); 1352 1353 // Emit an address. 1354 inline address emit_addr(const address addr = nullptr); 1355 1356 #if !defined(ABI_ELFv2) 1357 // Emit a function descriptor with the specified entry point, TOC, 1358 // and ENV. If the entry point is null, the descriptor will point 1359 // just past the descriptor. 1360 // Use values from friend functions as defaults. 1361 inline address emit_fd(address entry = nullptr, 1362 address toc = (address) FunctionDescriptor::friend_toc, 1363 address env = (address) FunctionDescriptor::friend_env); 1364 #endif 1365 1366 ///////////////////////////////////////////////////////////////////////////////////// 1367 // PPC instructions 1368 ///////////////////////////////////////////////////////////////////////////////////// 1369 1370 // Memory instructions use r0 as hard coded 0, e.g. to simulate loading 1371 // immediates. The normal instruction encoders enforce that r0 is not 1372 // passed to them. Use either extended mnemonics encoders or the special ra0 1373 // versions. 1374 1375 // Issue an illegal instruction. 1376 inline void illtrap(); 1377 static inline bool is_illtrap(address instr_addr); 1378 1379 // PPC 1, section 3.3.8, Fixed-Point Arithmetic Instructions 1380 inline void addi( Register d, Register a, int si16); 1381 inline void addis(Register d, Register a, int si16); 1382 1383 // Prefixed add immediate, introduced by POWER10 1384 inline void paddi(Register d, Register a, long si34, bool r); 1385 inline void pli( Register d, long si34); 1386 1387 private: 1388 inline void addi_r0ok( Register d, Register a, int si16); 1389 inline void addis_r0ok(Register d, Register a, int si16); 1390 inline void paddi_r0ok(Register d, Register a, long si34, bool r); 1391 public: 1392 inline void addic_( Register d, Register a, int si16); 1393 inline void subfic( Register d, Register a, int si16); 1394 inline void add( Register d, Register a, Register b); 1395 inline void add_( Register d, Register a, Register b); 1396 inline void subf( Register d, Register a, Register b); // d = b - a "Sub_from", as in ppc spec. 1397 inline void sub( Register d, Register a, Register b); // d = a - b Swap operands of subf for readability. 1398 inline void subf_( Register d, Register a, Register b); 1399 inline void addc( Register d, Register a, Register b); 1400 inline void addc_( Register d, Register a, Register b); 1401 inline void subfc( Register d, Register a, Register b); 1402 inline void subfc_( Register d, Register a, Register b); 1403 inline void adde( Register d, Register a, Register b); 1404 inline void adde_( Register d, Register a, Register b); 1405 inline void subfe( Register d, Register a, Register b); 1406 inline void subfe_( Register d, Register a, Register b); 1407 inline void addme( Register d, Register a); 1408 inline void addme_( Register d, Register a); 1409 inline void subfme( Register d, Register a); 1410 inline void subfme_(Register d, Register a); 1411 inline void addze( Register d, Register a); 1412 inline void addze_( Register d, Register a); 1413 inline void subfze( Register d, Register a); 1414 inline void subfze_(Register d, Register a); 1415 inline void neg( Register d, Register a); 1416 inline void neg_( Register d, Register a); 1417 inline void mulli( Register d, Register a, int si16); 1418 inline void mulld( Register d, Register a, Register b); 1419 inline void mulld_( Register d, Register a, Register b); 1420 inline void mullw( Register d, Register a, Register b); 1421 inline void mullw_( Register d, Register a, Register b); 1422 inline void mulhw( Register d, Register a, Register b); 1423 inline void mulhw_( Register d, Register a, Register b); 1424 inline void mulhwu( Register d, Register a, Register b); 1425 inline void mulhwu_(Register d, Register a, Register b); 1426 inline void mulhd( Register d, Register a, Register b); 1427 inline void mulhd_( Register d, Register a, Register b); 1428 inline void mulhdu( Register d, Register a, Register b); 1429 inline void mulhdu_(Register d, Register a, Register b); 1430 inline void divd( Register d, Register a, Register b); 1431 inline void divd_( Register d, Register a, Register b); 1432 inline void divw( Register d, Register a, Register b); 1433 inline void divw_( Register d, Register a, Register b); 1434 inline void divdu( Register d, Register a, Register b); 1435 inline void divdu_( Register d, Register a, Register b); 1436 inline void divwu( Register d, Register a, Register b); 1437 inline void divwu_( Register d, Register a, Register b); 1438 1439 // Fixed-Point Arithmetic Instructions with Overflow detection 1440 inline void addo( Register d, Register a, Register b); 1441 inline void addo_( Register d, Register a, Register b); 1442 inline void subfo( Register d, Register a, Register b); 1443 inline void subfo_( Register d, Register a, Register b); 1444 inline void addco( Register d, Register a, Register b); 1445 inline void addco_( Register d, Register a, Register b); 1446 inline void subfco( Register d, Register a, Register b); 1447 inline void subfco_( Register d, Register a, Register b); 1448 inline void addeo( Register d, Register a, Register b); 1449 inline void addeo_( Register d, Register a, Register b); 1450 inline void subfeo( Register d, Register a, Register b); 1451 inline void subfeo_( Register d, Register a, Register b); 1452 inline void addmeo( Register d, Register a); 1453 inline void addmeo_( Register d, Register a); 1454 inline void subfmeo( Register d, Register a); 1455 inline void subfmeo_(Register d, Register a); 1456 inline void addzeo( Register d, Register a); 1457 inline void addzeo_( Register d, Register a); 1458 inline void subfzeo( Register d, Register a); 1459 inline void subfzeo_(Register d, Register a); 1460 inline void nego( Register d, Register a); 1461 inline void nego_( Register d, Register a); 1462 inline void mulldo( Register d, Register a, Register b); 1463 inline void mulldo_( Register d, Register a, Register b); 1464 inline void mullwo( Register d, Register a, Register b); 1465 inline void mullwo_( Register d, Register a, Register b); 1466 inline void divdo( Register d, Register a, Register b); 1467 inline void divdo_( Register d, Register a, Register b); 1468 inline void divwo( Register d, Register a, Register b); 1469 inline void divwo_( Register d, Register a, Register b); 1470 1471 // extended mnemonics 1472 inline void li( Register d, int si16); 1473 inline void lis( Register d, int si16); 1474 inline void addir(Register d, int si16, Register a); 1475 inline void subi( Register d, Register a, int si16); 1476 1477 static bool is_addi(int x) { 1478 return ADDI_OPCODE == (x & ADDI_OPCODE_MASK); 1479 } 1480 static bool is_addis(int x) { 1481 return ADDIS_OPCODE == (x & ADDIS_OPCODE_MASK); 1482 } 1483 static bool is_andi(int x) { 1484 return ANDI_OPCODE == (x & ANDI_OPCODE_MASK); 1485 } 1486 static bool is_bxx(int x) { 1487 return BXX_OPCODE == (x & BXX_OPCODE_MASK); 1488 } 1489 static bool is_b(int x) { 1490 return BXX_OPCODE == (x & BXX_OPCODE_MASK) && inv_lk_field(x) == 0; 1491 } 1492 static bool is_bl(int x) { 1493 return BXX_OPCODE == (x & BXX_OPCODE_MASK) && inv_lk_field(x) == 1; 1494 } 1495 static bool is_bcxx(int x) { 1496 return BCXX_OPCODE == (x & BCXX_OPCODE_MASK); 1497 } 1498 static bool is_bxx_or_bcxx(int x) { 1499 return is_bxx(x) || is_bcxx(x); 1500 } 1501 static bool is_bctrl(int x) { 1502 return x == 0x4e800421; 1503 } 1504 static bool is_bctr(int x) { 1505 return x == 0x4e800420; 1506 } 1507 static bool is_bclr(int x) { 1508 return BCLR_OPCODE == (x & XL_FORM_OPCODE_MASK); 1509 } 1510 static bool is_cmpli(int x) { 1511 return CMPLI_OPCODE == (x & CMPLI_OPCODE_MASK); 1512 } 1513 static bool is_li(int x) { 1514 return is_addi(x) && inv_ra_field(x)==0; 1515 } 1516 static bool is_lis(int x) { 1517 return is_addis(x) && inv_ra_field(x)==0; 1518 } 1519 static bool is_mtctr(int x) { 1520 return MTCTR_OPCODE == (x & MTCTR_OPCODE_MASK); 1521 } 1522 static bool is_ld(int x) { 1523 return LD_OPCODE == (x & LD_OPCODE_MASK); 1524 } 1525 static bool is_std(int x) { 1526 return STD_OPCODE == (x & STD_OPCODE_MASK); 1527 } 1528 static bool is_stdu(int x) { 1529 return STDU_OPCODE == (x & STDU_OPCODE_MASK); 1530 } 1531 static bool is_stdx(int x) { 1532 return STDX_OPCODE == (x & STDX_OPCODE_MASK); 1533 } 1534 static bool is_stdux(int x) { 1535 return STDUX_OPCODE == (x & STDUX_OPCODE_MASK); 1536 } 1537 static bool is_stwx(int x) { 1538 return STWX_OPCODE == (x & STWX_OPCODE_MASK); 1539 } 1540 static bool is_stwux(int x) { 1541 return STWUX_OPCODE == (x & STWUX_OPCODE_MASK); 1542 } 1543 static bool is_stw(int x) { 1544 return STW_OPCODE == (x & STW_OPCODE_MASK); 1545 } 1546 static bool is_stwu(int x) { 1547 return STWU_OPCODE == (x & STWU_OPCODE_MASK); 1548 } 1549 static bool is_ori(int x) { 1550 return ORI_OPCODE == (x & ORI_OPCODE_MASK); 1551 }; 1552 static bool is_oris(int x) { 1553 return ORIS_OPCODE == (x & ORIS_OPCODE_MASK); 1554 }; 1555 static bool is_rldicr(int x) { 1556 return (RLDICR_OPCODE == (x & RLDICR_OPCODE_MASK)); 1557 }; 1558 static bool is_nop(int x) { 1559 return x == 0x60000000; 1560 } 1561 // endgroup opcode for Power6 1562 static bool is_endgroup(int x) { 1563 return is_ori(x) && inv_ra_field(x) == 1 && inv_rs_field(x) == 1 && inv_d1_field(x) == 0; 1564 } 1565 1566 1567 private: 1568 // PPC 1, section 3.3.9, Fixed-Point Compare Instructions 1569 inline void cmpi( ConditionRegister bf, int l, Register a, int si16); 1570 inline void cmp( ConditionRegister bf, int l, Register a, Register b); 1571 inline void cmpli(ConditionRegister bf, int l, Register a, int ui16); 1572 inline void cmpl( ConditionRegister bf, int l, Register a, Register b); 1573 1574 public: 1575 // extended mnemonics of Compare Instructions 1576 inline void cmpwi( ConditionRegister crx, Register a, int si16); 1577 inline void cmpdi( ConditionRegister crx, Register a, int si16); 1578 inline void cmpw( ConditionRegister crx, Register a, Register b); 1579 inline void cmpd( ConditionRegister crx, Register a, Register b); 1580 inline void cmplwi(ConditionRegister crx, Register a, int ui16); 1581 inline void cmpldi(ConditionRegister crx, Register a, int ui16); 1582 inline void cmplw( ConditionRegister crx, Register a, Register b); 1583 inline void cmpld( ConditionRegister crx, Register a, Register b); 1584 1585 // >= Power9 1586 inline void cmprb( ConditionRegister bf, int l, Register a, Register b); 1587 inline void cmpeqb(ConditionRegister bf, Register a, Register b); 1588 1589 inline void isel( Register d, Register a, Register b, int bc); 1590 // Convenient version which takes: Condition register, Condition code and invert flag. Omit b to keep old value. 1591 inline void isel( Register d, ConditionRegister cr, Condition cc, bool inv, Register a, Register b = noreg); 1592 // Set d = 0 if (cr.cc) equals 1, otherwise b. 1593 inline void isel_0( Register d, ConditionRegister cr, Condition cc, Register b = noreg); 1594 1595 // PPC 1, section 3.3.11, Fixed-Point Logical Instructions 1596 void andi( Register a, Register s, long ui16); // optimized version 1597 inline void andi_( Register a, Register s, int ui16); 1598 inline void andis_( Register a, Register s, int ui16); 1599 inline void ori( Register a, Register s, int ui16); 1600 inline void oris( Register a, Register s, int ui16); 1601 inline void xori( Register a, Register s, int ui16); 1602 inline void xoris( Register a, Register s, int ui16); 1603 inline void andr( Register a, Register s, Register b); // suffixed by 'r' as 'and' is C++ keyword 1604 inline void and_( Register a, Register s, Register b); 1605 // Turn or0(rx,rx,rx) into a nop and avoid that we accidentally emit a 1606 // SMT-priority change instruction (see SMT instructions below). 1607 inline void or_unchecked(Register a, Register s, Register b); 1608 inline void orr( Register a, Register s, Register b); // suffixed by 'r' as 'or' is C++ keyword 1609 inline void or_( Register a, Register s, Register b); 1610 inline void xorr( Register a, Register s, Register b); // suffixed by 'r' as 'xor' is C++ keyword 1611 inline void xor_( Register a, Register s, Register b); 1612 inline void nand( Register a, Register s, Register b); 1613 inline void nand_( Register a, Register s, Register b); 1614 inline void nor( Register a, Register s, Register b); 1615 inline void nor_( Register a, Register s, Register b); 1616 inline void andc( Register a, Register s, Register b); 1617 inline void andc_( Register a, Register s, Register b); 1618 inline void orc( Register a, Register s, Register b); 1619 inline void orc_( Register a, Register s, Register b); 1620 inline void extsb( Register a, Register s); 1621 inline void extsb_( Register a, Register s); 1622 inline void extsh( Register a, Register s); 1623 inline void extsh_( Register a, Register s); 1624 inline void extsw( Register a, Register s); 1625 inline void extsw_( Register a, Register s); 1626 1627 // extended mnemonics 1628 inline void nop(); 1629 // NOP for FP and BR units (different versions to allow them to be in one group) 1630 inline void fpnop0(); 1631 inline void fpnop1(); 1632 inline void brnop0(); 1633 inline void brnop1(); 1634 inline void brnop2(); 1635 1636 inline void mr( Register d, Register s); 1637 inline void ori_opt( Register d, int ui16); 1638 inline void oris_opt(Register d, int ui16); 1639 1640 // endgroup opcode for Power6 1641 inline void endgroup(); 1642 1643 // count instructions 1644 inline void cntlzw( Register a, Register s); 1645 inline void cntlzw_( Register a, Register s); 1646 inline void cntlzd( Register a, Register s); 1647 inline void cntlzd_( Register a, Register s); 1648 inline void cnttzw( Register a, Register s); 1649 inline void cnttzw_( Register a, Register s); 1650 inline void cnttzd( Register a, Register s); 1651 inline void cnttzd_( Register a, Register s); 1652 1653 // PPC 1, section 3.3.12, Fixed-Point Rotate and Shift Instructions 1654 inline void sld( Register a, Register s, Register b); 1655 inline void sld_( Register a, Register s, Register b); 1656 inline void slw( Register a, Register s, Register b); 1657 inline void slw_( Register a, Register s, Register b); 1658 inline void srd( Register a, Register s, Register b); 1659 inline void srd_( Register a, Register s, Register b); 1660 inline void srw( Register a, Register s, Register b); 1661 inline void srw_( Register a, Register s, Register b); 1662 inline void srad( Register a, Register s, Register b); 1663 inline void srad_( Register a, Register s, Register b); 1664 inline void sraw( Register a, Register s, Register b); 1665 inline void sraw_( Register a, Register s, Register b); 1666 inline void sradi( Register a, Register s, int sh6); 1667 inline void sradi_( Register a, Register s, int sh6); 1668 inline void srawi( Register a, Register s, int sh5); 1669 inline void srawi_( Register a, Register s, int sh5); 1670 1671 // extended mnemonics for Shift Instructions 1672 inline void sldi( Register a, Register s, int sh6); 1673 inline void sldi_( Register a, Register s, int sh6); 1674 inline void slwi( Register a, Register s, int sh5); 1675 inline void slwi_( Register a, Register s, int sh5); 1676 inline void srdi( Register a, Register s, int sh6); 1677 inline void srdi_( Register a, Register s, int sh6); 1678 inline void srwi( Register a, Register s, int sh5); 1679 inline void srwi_( Register a, Register s, int sh5); 1680 1681 inline void clrrdi( Register a, Register s, int ui6); 1682 inline void clrrdi_( Register a, Register s, int ui6); 1683 inline void clrldi( Register a, Register s, int ui6); 1684 inline void clrldi_( Register a, Register s, int ui6); 1685 inline void clrlsldi(Register a, Register s, int clrl6, int shl6); 1686 inline void clrlsldi_(Register a, Register s, int clrl6, int shl6); 1687 inline void extrdi( Register a, Register s, int n, int b); 1688 // testbit with condition register 1689 inline void testbitdi(ConditionRegister cr, Register a, Register s, int ui6); 1690 1691 // Byte reverse instructions (introduced with Power10) 1692 inline void brh( Register a, Register s); 1693 inline void brw( Register a, Register s); 1694 inline void brd( Register a, Register s); 1695 1696 // rotate instructions 1697 inline void rotldi( Register a, Register s, int n); 1698 inline void rotrdi( Register a, Register s, int n); 1699 inline void rotlwi( Register a, Register s, int n); 1700 inline void rotrwi( Register a, Register s, int n); 1701 1702 // Rotate Instructions 1703 inline void rldic( Register a, Register s, int sh6, int mb6); 1704 inline void rldic_( Register a, Register s, int sh6, int mb6); 1705 inline void rldicr( Register a, Register s, int sh6, int mb6); 1706 inline void rldicr_( Register a, Register s, int sh6, int mb6); 1707 inline void rldicl( Register a, Register s, int sh6, int mb6); 1708 inline void rldicl_( Register a, Register s, int sh6, int mb6); 1709 inline void rlwinm( Register a, Register s, int sh5, int mb5, int me5); 1710 inline void rlwinm_( Register a, Register s, int sh5, int mb5, int me5); 1711 inline void rldimi( Register a, Register s, int sh6, int mb6); 1712 inline void rldimi_( Register a, Register s, int sh6, int mb6); 1713 inline void rlwimi( Register a, Register s, int sh5, int mb5, int me5); 1714 inline void insrdi( Register a, Register s, int n, int b); 1715 inline void insrwi( Register a, Register s, int n, int b); 1716 1717 // PPC 1, section 3.3.2 Fixed-Point Load Instructions 1718 // 4 bytes 1719 inline void lwzx( Register d, Register s1, Register s2); 1720 inline void lwz( Register d, int si16, Register s1); 1721 inline void lwzu( Register d, int si16, Register s1); 1722 1723 // 4 bytes 1724 inline void lwax( Register d, Register s1, Register s2); 1725 inline void lwa( Register d, int si16, Register s1); 1726 1727 // 4 bytes reversed 1728 inline void lwbrx( Register d, Register s1, Register s2); 1729 1730 // 2 bytes 1731 inline void lhzx( Register d, Register s1, Register s2); 1732 inline void lhz( Register d, int si16, Register s1); 1733 inline void lhzu( Register d, int si16, Register s1); 1734 1735 // 2 bytes reversed 1736 inline void lhbrx( Register d, Register s1, Register s2); 1737 1738 // 2 bytes 1739 inline void lhax( Register d, Register s1, Register s2); 1740 inline void lha( Register d, int si16, Register s1); 1741 inline void lhau( Register d, int si16, Register s1); 1742 1743 // 1 byte 1744 inline void lbzx( Register d, Register s1, Register s2); 1745 inline void lbz( Register d, int si16, Register s1); 1746 inline void lbzu( Register d, int si16, Register s1); 1747 1748 // 8 bytes 1749 inline void ldx( Register d, Register s1, Register s2); 1750 inline void ld( Register d, int si16, Register s1); 1751 inline void ld( Register d, ByteSize si16, Register s1); 1752 inline void ldu( Register d, int si16, Register s1); 1753 1754 // 8 bytes reversed 1755 inline void ldbrx( Register d, Register s1, Register s2); 1756 1757 // For convenience. Load pointer into d from b+s1. 1758 inline void ld_ptr(Register d, int b, Register s1); 1759 inline void ld_ptr(Register d, ByteSize b, Register s1); 1760 1761 // PPC 1, section 3.3.3 Fixed-Point Store Instructions 1762 inline void stwx( Register d, Register s1, Register s2); 1763 inline void stw( Register d, int si16, Register s1); 1764 inline void stwu( Register d, int si16, Register s1); 1765 inline void stwbrx( Register d, Register s1, Register s2); 1766 1767 inline void sthx( Register d, Register s1, Register s2); 1768 inline void sth( Register d, int si16, Register s1); 1769 inline void sthu( Register d, int si16, Register s1); 1770 inline void sthbrx( Register d, Register s1, Register s2); 1771 1772 inline void stbx( Register d, Register s1, Register s2); 1773 inline void stb( Register d, int si16, Register s1); 1774 inline void stbu( Register d, int si16, Register s1); 1775 1776 inline void stdx( Register d, Register s1, Register s2); 1777 inline void std( Register d, int si16, Register s1); 1778 inline void stdu( Register d, int si16, Register s1); 1779 inline void stdux(Register s, Register a, Register b); 1780 inline void stdbrx( Register d, Register s1, Register s2); 1781 1782 inline void st_ptr(Register d, int si16, Register s1); 1783 inline void st_ptr(Register d, ByteSize b, Register s1); 1784 1785 // PPC 1, section 3.3.13 Move To/From System Register Instructions 1786 inline void mtlr( Register s1); 1787 inline void mflr( Register d); 1788 inline void mtctr(Register s1); 1789 inline void mfctr(Register d); 1790 inline void mtcrf(int fxm, Register s); 1791 inline void mfcr( Register d); 1792 inline void mcrf( ConditionRegister crd, ConditionRegister cra); 1793 inline void mtcr( Register s); 1794 // >= Power9 1795 inline void mcrxrx(ConditionRegister cra); 1796 inline void setb( Register d, ConditionRegister cra); 1797 1798 // >= Power10 1799 inline void setbc( Register d, int biint); 1800 inline void setbc( Register d, ConditionRegister cr, Condition cc); 1801 inline void setnbc(Register d, int biint); 1802 inline void setnbc(Register d, ConditionRegister cr, Condition cc); 1803 1804 // Special purpose registers 1805 // Exception Register 1806 inline void mtxer(Register s1); 1807 inline void mfxer(Register d); 1808 // Vector Register Save Register 1809 inline void mtvrsave(Register s1); 1810 inline void mfvrsave(Register d); 1811 // Timebase 1812 inline void mftb(Register d); 1813 // Introduced with Power 8: 1814 // Data Stream Control Register 1815 inline void mtdscr(Register s1); 1816 inline void mfdscr(Register d ); 1817 // Transactional Memory Registers 1818 inline void mftfhar(Register d); 1819 inline void mftfiar(Register d); 1820 inline void mftexasr(Register d); 1821 inline void mftexasru(Register d); 1822 1823 // TEXASR bit description 1824 enum transaction_failure_reason { 1825 // Upper half (TEXASRU): 1826 tm_failure_code = 0, // The Failure Code is copied from tabort or treclaim operand. 1827 tm_failure_persistent = 7, // The failure is likely to recur on each execution. 1828 tm_disallowed = 8, // The instruction is not permitted. 1829 tm_nesting_of = 9, // The maximum transaction level was exceeded. 1830 tm_footprint_of = 10, // The tracking limit for transactional storage accesses was exceeded. 1831 tm_self_induced_cf = 11, // A self-induced conflict occurred in Suspended state. 1832 tm_non_trans_cf = 12, // A conflict occurred with a non-transactional access by another processor. 1833 tm_trans_cf = 13, // A conflict occurred with another transaction. 1834 tm_translation_cf = 14, // A conflict occurred with a TLB invalidation. 1835 tm_inst_fetch_cf = 16, // An instruction fetch was performed from a block that was previously written transactionally. 1836 tm_tabort = 31, // Termination was caused by the execution of an abort instruction. 1837 // Lower half: 1838 tm_suspended = 32, // Failure was recorded in Suspended state. 1839 tm_failure_summary = 36, // Failure has been detected and recorded. 1840 tm_tfiar_exact = 37, // Value in the TFIAR is exact. 1841 tm_rot = 38, // Rollback-only transaction. 1842 tm_transaction_level = 52, // Transaction level (nesting depth + 1). 1843 }; 1844 1845 // PPC 1, section 2.4.1 Branch Instructions 1846 inline void b( address a, relocInfo::relocType rt = relocInfo::none); 1847 inline void b( Label& L); 1848 inline void bl( address a, relocInfo::relocType rt = relocInfo::none); 1849 inline void bl( Label& L); 1850 inline void bc( int boint, int biint, address a, relocInfo::relocType rt = relocInfo::none); 1851 inline void bc( int boint, int biint, Label& L); 1852 inline void bcl(int boint, int biint, address a, relocInfo::relocType rt = relocInfo::none); 1853 inline void bcl(int boint, int biint, Label& L); 1854 1855 inline void bclr( int boint, int biint, int bhint, relocInfo::relocType rt = relocInfo::none); 1856 inline void bclrl( int boint, int biint, int bhint, relocInfo::relocType rt = relocInfo::none); 1857 inline void bcctr( int boint, int biint, int bhint = bhintbhBCCTRisNotReturnButSame, 1858 relocInfo::relocType rt = relocInfo::none); 1859 inline void bcctrl(int boint, int biint, int bhint = bhintbhBCLRisReturn, 1860 relocInfo::relocType rt = relocInfo::none); 1861 1862 // helper function for b, bcxx 1863 inline bool is_within_range_of_b(address a, address pc); 1864 inline bool is_within_range_of_bcxx(address a, address pc); 1865 1866 // get the destination of a bxx branch (b, bl, ba, bla) 1867 static inline address bxx_destination(address baddr); 1868 static inline address bxx_destination(int instr, address pc); 1869 static inline intptr_t bxx_destination_offset(int instr, intptr_t bxx_pos); 1870 1871 // extended mnemonics for branch instructions 1872 inline void blt(ConditionRegister crx, Label& L); 1873 inline void bgt(ConditionRegister crx, Label& L); 1874 inline void beq(ConditionRegister crx, Label& L); 1875 inline void bso(ConditionRegister crx, Label& L); 1876 inline void bge(ConditionRegister crx, Label& L); 1877 inline void ble(ConditionRegister crx, Label& L); 1878 inline void bne(ConditionRegister crx, Label& L); 1879 inline void bns(ConditionRegister crx, Label& L); 1880 1881 // Branch instructions with static prediction hints. 1882 inline void blt_predict_taken( ConditionRegister crx, Label& L); 1883 inline void bgt_predict_taken( ConditionRegister crx, Label& L); 1884 inline void beq_predict_taken( ConditionRegister crx, Label& L); 1885 inline void bso_predict_taken( ConditionRegister crx, Label& L); 1886 inline void bge_predict_taken( ConditionRegister crx, Label& L); 1887 inline void ble_predict_taken( ConditionRegister crx, Label& L); 1888 inline void bne_predict_taken( ConditionRegister crx, Label& L); 1889 inline void bns_predict_taken( ConditionRegister crx, Label& L); 1890 inline void blt_predict_not_taken(ConditionRegister crx, Label& L); 1891 inline void bgt_predict_not_taken(ConditionRegister crx, Label& L); 1892 inline void beq_predict_not_taken(ConditionRegister crx, Label& L); 1893 inline void bso_predict_not_taken(ConditionRegister crx, Label& L); 1894 inline void bge_predict_not_taken(ConditionRegister crx, Label& L); 1895 inline void ble_predict_not_taken(ConditionRegister crx, Label& L); 1896 inline void bne_predict_not_taken(ConditionRegister crx, Label& L); 1897 inline void bns_predict_not_taken(ConditionRegister crx, Label& L); 1898 1899 // for use in conjunction with testbitdi: 1900 inline void btrue( ConditionRegister crx, Label& L); 1901 inline void bfalse(ConditionRegister crx, Label& L); 1902 1903 inline void bltl(ConditionRegister crx, Label& L); 1904 inline void bgtl(ConditionRegister crx, Label& L); 1905 inline void beql(ConditionRegister crx, Label& L); 1906 inline void bsol(ConditionRegister crx, Label& L); 1907 inline void bgel(ConditionRegister crx, Label& L); 1908 inline void blel(ConditionRegister crx, Label& L); 1909 inline void bnel(ConditionRegister crx, Label& L); 1910 inline void bnsl(ConditionRegister crx, Label& L); 1911 1912 // extended mnemonics for Branch Instructions via LR 1913 // We use `blr' for returns. 1914 inline void blr(relocInfo::relocType rt = relocInfo::none); 1915 1916 // extended mnemonics for Branch Instructions with CTR 1917 // bdnz means `decrement CTR and jump to L if CTR is not zero' 1918 inline void bdnz(Label& L); 1919 // Decrement and branch if result is zero. 1920 inline void bdz(Label& L); 1921 // we use `bctr[l]' for jumps/calls in function descriptor glue 1922 // code, e.g. calls to runtime functions 1923 inline void bctr( relocInfo::relocType rt = relocInfo::none); 1924 inline void bctrl(relocInfo::relocType rt = relocInfo::none); 1925 // conditional jumps/branches via CTR 1926 inline void beqctr( ConditionRegister crx, relocInfo::relocType rt = relocInfo::none); 1927 inline void beqctrl(ConditionRegister crx, relocInfo::relocType rt = relocInfo::none); 1928 inline void bnectr( ConditionRegister crx, relocInfo::relocType rt = relocInfo::none); 1929 inline void bnectrl(ConditionRegister crx, relocInfo::relocType rt = relocInfo::none); 1930 1931 // condition register logic instructions 1932 // NOTE: There's a preferred form: d and s2 should point into the same condition register. 1933 inline void crand( int d, int s1, int s2); 1934 inline void crnand(int d, int s1, int s2); 1935 inline void cror( int d, int s1, int s2); 1936 inline void crxor( int d, int s1, int s2); 1937 inline void crnor( int d, int s1, int s2); 1938 inline void creqv( int d, int s1, int s2); 1939 inline void crandc(int d, int s1, int s2); 1940 inline void crorc( int d, int s1, int s2); 1941 1942 // More convenient version. 1943 int condition_register_bit(ConditionRegister cr, Condition c) { 1944 return 4 * cr.encoding() + c; 1945 } 1946 void crand( ConditionRegister crdst, Condition cdst, ConditionRegister crsrc, Condition csrc); 1947 void crnand(ConditionRegister crdst, Condition cdst, ConditionRegister crsrc, Condition csrc); 1948 void cror( ConditionRegister crdst, Condition cdst, ConditionRegister crsrc, Condition csrc); 1949 void crxor( ConditionRegister crdst, Condition cdst, ConditionRegister crsrc, Condition csrc); 1950 void crnor( ConditionRegister crdst, Condition cdst, ConditionRegister crsrc, Condition csrc); 1951 void creqv( ConditionRegister crdst, Condition cdst, ConditionRegister crsrc, Condition csrc); 1952 void crandc(ConditionRegister crdst, Condition cdst, ConditionRegister crsrc, Condition csrc); 1953 void crorc( ConditionRegister crdst, Condition cdst, ConditionRegister crsrc, Condition csrc); 1954 1955 // icache and dcache related instructions 1956 inline void icbi( Register s1, Register s2); 1957 //inline void dcba(Register s1, Register s2); // Instruction for embedded processor only. 1958 inline void dcbz( Register s1, Register s2); 1959 inline void dcbst( Register s1, Register s2); 1960 inline void dcbf( Register s1, Register s2); 1961 1962 enum ct_cache_specification { 1963 ct_primary_cache = 0, 1964 ct_secondary_cache = 2 1965 }; 1966 // dcache read hint 1967 inline void dcbt( Register s1, Register s2); 1968 inline void dcbtct( Register s1, Register s2, int ct); 1969 inline void dcbtds( Register s1, Register s2, int ds); 1970 // dcache write hint 1971 inline void dcbtst( Register s1, Register s2); 1972 inline void dcbtstct(Register s1, Register s2, int ct); 1973 1974 // machine barrier instructions: 1975 // 1976 // - sync two-way memory barrier, aka fence 1977 // - lwsync orders Store|Store, 1978 // Load|Store, 1979 // Load|Load, 1980 // but not Store|Load 1981 // - eieio orders memory accesses for device memory (only) 1982 // - isync invalidates speculatively executed instructions 1983 // From the Power ISA 2.06 documentation: 1984 // "[...] an isync instruction prevents the execution of 1985 // instructions following the isync until instructions 1986 // preceding the isync have completed, [...]" 1987 // From IBM's AIX assembler reference: 1988 // "The isync [...] instructions causes the processor to 1989 // refetch any instructions that might have been fetched 1990 // prior to the isync instruction. The instruction isync 1991 // causes the processor to wait for all previous instructions 1992 // to complete. Then any instructions already fetched are 1993 // discarded and instruction processing continues in the 1994 // environment established by the previous instructions." 1995 // 1996 // semantic barrier instructions: 1997 // (as defined in orderAccess.hpp) 1998 // 1999 // - release orders Store|Store, (maps to lwsync) 2000 // Load|Store 2001 // - acquire orders Load|Store, (maps to lwsync) 2002 // Load|Load 2003 // - fence orders Store|Store, (maps to sync) 2004 // Load|Store, 2005 // Load|Load, 2006 // Store|Load 2007 // 2008 private: 2009 inline void sync(int l); 2010 public: 2011 inline void sync(); 2012 inline void lwsync(); 2013 inline void ptesync(); 2014 inline void eieio(); 2015 inline void isync(); 2016 inline void elemental_membar(int e); // Elemental Memory Barriers (>=Power 8) 2017 2018 // Wait instructions for polling. Attention: May result in SIGILL. 2019 inline void wait(); 2020 inline void waitrsv(); // >=Power7 2021 2022 // atomics 2023 inline void lbarx_unchecked(Register d, Register a, Register b, int eh1 = 0); // >=Power 8 2024 inline void lharx_unchecked(Register d, Register a, Register b, int eh1 = 0); // >=Power 8 2025 inline void lwarx_unchecked(Register d, Register a, Register b, int eh1 = 0); 2026 inline void ldarx_unchecked(Register d, Register a, Register b, int eh1 = 0); 2027 inline void lqarx_unchecked(Register d, Register a, Register b, int eh1 = 0); // >=Power 8 2028 inline bool lxarx_hint_exclusive_access(); 2029 inline void lbarx( Register d, Register a, Register b, bool hint_exclusive_access = false); 2030 inline void lharx( Register d, Register a, Register b, bool hint_exclusive_access = false); 2031 inline void lwarx( Register d, Register a, Register b, bool hint_exclusive_access = false); 2032 inline void ldarx( Register d, Register a, Register b, bool hint_exclusive_access = false); 2033 inline void lqarx( Register d, Register a, Register b, bool hint_exclusive_access = false); 2034 inline void stbcx_( Register s, Register a, Register b); 2035 inline void sthcx_( Register s, Register a, Register b); 2036 inline void stwcx_( Register s, Register a, Register b); 2037 inline void stdcx_( Register s, Register a, Register b); 2038 inline void stqcx_( Register s, Register a, Register b); 2039 2040 // Instructions for adjusting thread priority for simultaneous 2041 // multithreading (SMT) on Power5. 2042 private: 2043 inline void smt_prio_very_low(); 2044 inline void smt_prio_medium_high(); 2045 inline void smt_prio_high(); 2046 2047 public: 2048 inline void smt_prio_low(); 2049 inline void smt_prio_medium_low(); 2050 inline void smt_prio_medium(); 2051 // >= Power7 2052 inline void smt_yield(); 2053 inline void smt_mdoio(); 2054 inline void smt_mdoom(); 2055 // >= Power8 2056 inline void smt_miso(); 2057 2058 // trap instructions 2059 inline void twi_0(Register a); // for load with acquire semantics use load+twi_0+isync (trap can't occur) 2060 // NOT FOR DIRECT USE!! 2061 protected: 2062 inline void tdi_unchecked(int tobits, Register a, int si16); 2063 inline void twi_unchecked(int tobits, Register a, int si16); 2064 inline void tdi( int tobits, Register a, int si16); // asserts UseSIGTRAP 2065 inline void twi( int tobits, Register a, int si16); // asserts UseSIGTRAP 2066 inline void td( int tobits, Register a, Register b); // asserts UseSIGTRAP 2067 inline void tw( int tobits, Register a, Register b); // asserts UseSIGTRAP 2068 2069 public: 2070 static bool is_tdi(int x, int tobits, int ra, int si16) { 2071 return (TDI_OPCODE == (x & TDI_OPCODE_MASK)) 2072 && (tobits == inv_to_field(x)) 2073 && (ra == -1/*any reg*/ || ra == inv_ra_field(x)) 2074 && (si16 == inv_si_field(x)); 2075 } 2076 2077 static int tdi_get_si16(int x, int tobits, int ra) { 2078 if (TDI_OPCODE == (x & TDI_OPCODE_MASK) 2079 && (tobits == inv_to_field(x)) 2080 && (ra == -1/*any reg*/ || ra == inv_ra_field(x))) { 2081 return inv_si_field(x); 2082 } 2083 return -1; // No valid tdi instruction. 2084 } 2085 2086 static bool is_twi(int x, int tobits, int ra, int si16) { 2087 return (TWI_OPCODE == (x & TWI_OPCODE_MASK)) 2088 && (tobits == inv_to_field(x)) 2089 && (ra == -1/*any reg*/ || ra == inv_ra_field(x)) 2090 && (si16 == inv_si_field(x)); 2091 } 2092 2093 static bool is_twi(int x, int tobits, int ra) { 2094 return (TWI_OPCODE == (x & TWI_OPCODE_MASK)) 2095 && (tobits == inv_to_field(x)) 2096 && (ra == -1/*any reg*/ || ra == inv_ra_field(x)); 2097 } 2098 2099 static bool is_td(int x, int tobits, int ra, int rb) { 2100 return (TD_OPCODE == (x & TD_OPCODE_MASK)) 2101 && (tobits == inv_to_field(x)) 2102 && (ra == -1/*any reg*/ || ra == inv_ra_field(x)) 2103 && (rb == -1/*any reg*/ || rb == inv_rb_field(x)); 2104 } 2105 2106 static bool is_tw(int x, int tobits, int ra, int rb) { 2107 return (TW_OPCODE == (x & TW_OPCODE_MASK)) 2108 && (tobits == inv_to_field(x)) 2109 && (ra == -1/*any reg*/ || ra == inv_ra_field(x)) 2110 && (rb == -1/*any reg*/ || rb == inv_rb_field(x)); 2111 } 2112 2113 // PPC floating point instructions 2114 // PPC 1, section 4.6.2 Floating-Point Load Instructions 2115 inline void lfs( FloatRegister d, int si16, Register a); 2116 inline void lfsu( FloatRegister d, int si16, Register a); 2117 inline void lfsx( FloatRegister d, Register a, Register b); 2118 inline void lfd( FloatRegister d, int si16, Register a); 2119 inline void lfdu( FloatRegister d, int si16, Register a); 2120 inline void lfdx( FloatRegister d, Register a, Register b); 2121 2122 // PPC 1, section 4.6.3 Floating-Point Store Instructions 2123 inline void stfs( FloatRegister s, int si16, Register a); 2124 inline void stfsu( FloatRegister s, int si16, Register a); 2125 inline void stfsx( FloatRegister s, Register a, Register b); 2126 inline void stfd( FloatRegister s, int si16, Register a); 2127 inline void stfdu( FloatRegister s, int si16, Register a); 2128 inline void stfdx( FloatRegister s, Register a, Register b); 2129 2130 // PPC 1, section 4.6.4 Floating-Point Move Instructions 2131 inline void fmr( FloatRegister d, FloatRegister b); 2132 inline void fmr_( FloatRegister d, FloatRegister b); 2133 2134 inline void frin( FloatRegister d, FloatRegister b); 2135 inline void frip( FloatRegister d, FloatRegister b); 2136 inline void frim( FloatRegister d, FloatRegister b); 2137 2138 // inline void mffgpr( FloatRegister d, Register b); 2139 // inline void mftgpr( Register d, FloatRegister b); 2140 inline void cmpb( Register a, Register s, Register b); 2141 inline void popcntb(Register a, Register s); 2142 inline void popcntw(Register a, Register s); 2143 inline void popcntd(Register a, Register s); 2144 2145 inline void fneg( FloatRegister d, FloatRegister b); 2146 inline void fneg_( FloatRegister d, FloatRegister b); 2147 inline void fabs( FloatRegister d, FloatRegister b); 2148 inline void fabs_( FloatRegister d, FloatRegister b); 2149 inline void fnabs( FloatRegister d, FloatRegister b); 2150 inline void fnabs_(FloatRegister d, FloatRegister b); 2151 2152 // PPC 1, section 4.6.5.1 Floating-Point Elementary Arithmetic Instructions 2153 inline void fadd( FloatRegister d, FloatRegister a, FloatRegister b); 2154 inline void fadd_( FloatRegister d, FloatRegister a, FloatRegister b); 2155 inline void fadds( FloatRegister d, FloatRegister a, FloatRegister b); 2156 inline void fadds_(FloatRegister d, FloatRegister a, FloatRegister b); 2157 inline void fsub( FloatRegister d, FloatRegister a, FloatRegister b); 2158 inline void fsub_( FloatRegister d, FloatRegister a, FloatRegister b); 2159 inline void fsubs( FloatRegister d, FloatRegister a, FloatRegister b); 2160 inline void fsubs_(FloatRegister d, FloatRegister a, FloatRegister b); 2161 inline void fmul( FloatRegister d, FloatRegister a, FloatRegister c); 2162 inline void fmul_( FloatRegister d, FloatRegister a, FloatRegister c); 2163 inline void fmuls( FloatRegister d, FloatRegister a, FloatRegister c); 2164 inline void fmuls_(FloatRegister d, FloatRegister a, FloatRegister c); 2165 inline void fdiv( FloatRegister d, FloatRegister a, FloatRegister b); 2166 inline void fdiv_( FloatRegister d, FloatRegister a, FloatRegister b); 2167 inline void fdivs( FloatRegister d, FloatRegister a, FloatRegister b); 2168 inline void fdivs_(FloatRegister d, FloatRegister a, FloatRegister b); 2169 2170 // Fused multiply-accumulate instructions. 2171 // WARNING: Use only when rounding between the 2 parts is not desired. 2172 // Some floating point tck tests will fail if used incorrectly. 2173 inline void fmadd( FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b); 2174 inline void fmadd_( FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b); 2175 inline void fmadds( FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b); 2176 inline void fmadds_( FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b); 2177 inline void fmsub( FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b); 2178 inline void fmsub_( FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b); 2179 inline void fmsubs( FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b); 2180 inline void fmsubs_( FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b); 2181 inline void fnmadd( FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b); 2182 inline void fnmadd_( FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b); 2183 inline void fnmadds( FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b); 2184 inline void fnmadds_(FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b); 2185 inline void fnmsub( FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b); 2186 inline void fnmsub_( FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b); 2187 inline void fnmsubs( FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b); 2188 inline void fnmsubs_(FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b); 2189 2190 // PPC 1, section 4.6.6 Floating-Point Rounding and Conversion Instructions 2191 inline void frsp( FloatRegister d, FloatRegister b); 2192 inline void fctid( FloatRegister d, FloatRegister b); 2193 inline void fctidz(FloatRegister d, FloatRegister b); 2194 inline void fctiw( FloatRegister d, FloatRegister b); 2195 inline void fctiwz(FloatRegister d, FloatRegister b); 2196 inline void fcfid( FloatRegister d, FloatRegister b); 2197 inline void fcfids(FloatRegister d, FloatRegister b); 2198 2199 // PPC 1, section 4.6.7 Floating-Point Compare Instructions 2200 inline void fcmpu( ConditionRegister crx, FloatRegister a, FloatRegister b); 2201 2202 inline void fsqrt( FloatRegister d, FloatRegister b); 2203 inline void fsqrts(FloatRegister d, FloatRegister b); 2204 2205 // Vector instructions for >= Power6. 2206 inline void lvebx( VectorRegister d, Register s1, Register s2); 2207 inline void lvehx( VectorRegister d, Register s1, Register s2); 2208 inline void lvewx( VectorRegister d, Register s1, Register s2); 2209 inline void lvx( VectorRegister d, Register s1, Register s2); 2210 inline void lvxl( VectorRegister d, Register s1, Register s2); 2211 inline void stvebx( VectorRegister d, Register s1, Register s2); 2212 inline void stvehx( VectorRegister d, Register s1, Register s2); 2213 inline void stvewx( VectorRegister d, Register s1, Register s2); 2214 inline void stvx( VectorRegister d, Register s1, Register s2); 2215 inline void stvxl( VectorRegister d, Register s1, Register s2); 2216 inline void lvsl( VectorRegister d, Register s1, Register s2); 2217 inline void lvsr( VectorRegister d, Register s1, Register s2); 2218 inline void vpkpx( VectorRegister d, VectorRegister a, VectorRegister b); 2219 inline void vpkshss( VectorRegister d, VectorRegister a, VectorRegister b); 2220 inline void vpkswss( VectorRegister d, VectorRegister a, VectorRegister b); 2221 inline void vpkshus( VectorRegister d, VectorRegister a, VectorRegister b); 2222 inline void vpkswus( VectorRegister d, VectorRegister a, VectorRegister b); 2223 inline void vpkuhum( VectorRegister d, VectorRegister a, VectorRegister b); 2224 inline void vpkuwum( VectorRegister d, VectorRegister a, VectorRegister b); 2225 inline void vpkuhus( VectorRegister d, VectorRegister a, VectorRegister b); 2226 inline void vpkuwus( VectorRegister d, VectorRegister a, VectorRegister b); 2227 inline void vupkhpx( VectorRegister d, VectorRegister b); 2228 inline void vupkhsb( VectorRegister d, VectorRegister b); 2229 inline void vupkhsh( VectorRegister d, VectorRegister b); 2230 inline void vupklpx( VectorRegister d, VectorRegister b); 2231 inline void vupklsb( VectorRegister d, VectorRegister b); 2232 inline void vupklsh( VectorRegister d, VectorRegister b); 2233 inline void vmrghb( VectorRegister d, VectorRegister a, VectorRegister b); 2234 inline void vmrghw( VectorRegister d, VectorRegister a, VectorRegister b); 2235 inline void vmrghh( VectorRegister d, VectorRegister a, VectorRegister b); 2236 inline void vmrglb( VectorRegister d, VectorRegister a, VectorRegister b); 2237 inline void vmrglw( VectorRegister d, VectorRegister a, VectorRegister b); 2238 inline void vmrglh( VectorRegister d, VectorRegister a, VectorRegister b); 2239 inline void vsplt( VectorRegister d, int ui4, VectorRegister b); 2240 inline void vsplth( VectorRegister d, int ui3, VectorRegister b); 2241 inline void vspltw( VectorRegister d, int ui2, VectorRegister b); 2242 inline void vspltisb( VectorRegister d, int si5); 2243 inline void vspltish( VectorRegister d, int si5); 2244 inline void vspltisw( VectorRegister d, int si5); 2245 inline void vperm( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c); 2246 inline void vpextd( VectorRegister d, VectorRegister a, VectorRegister b); 2247 inline void vsel( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c); 2248 inline void vsl( VectorRegister d, VectorRegister a, VectorRegister b); 2249 inline void vsldoi( VectorRegister d, VectorRegister a, VectorRegister b, int ui4); 2250 inline void vslo( VectorRegister d, VectorRegister a, VectorRegister b); 2251 inline void vsr( VectorRegister d, VectorRegister a, VectorRegister b); 2252 inline void vsro( VectorRegister d, VectorRegister a, VectorRegister b); 2253 inline void vaddcuw( VectorRegister d, VectorRegister a, VectorRegister b); 2254 inline void vaddshs( VectorRegister d, VectorRegister a, VectorRegister b); 2255 inline void vaddsbs( VectorRegister d, VectorRegister a, VectorRegister b); 2256 inline void vaddsws( VectorRegister d, VectorRegister a, VectorRegister b); 2257 inline void vaddubm( VectorRegister d, VectorRegister a, VectorRegister b); 2258 inline void vadduwm( VectorRegister d, VectorRegister a, VectorRegister b); 2259 inline void vadduhm( VectorRegister d, VectorRegister a, VectorRegister b); 2260 inline void vaddudm( VectorRegister d, VectorRegister a, VectorRegister b); 2261 inline void vaddubs( VectorRegister d, VectorRegister a, VectorRegister b); 2262 inline void vadduws( VectorRegister d, VectorRegister a, VectorRegister b); 2263 inline void vadduhs( VectorRegister d, VectorRegister a, VectorRegister b); 2264 inline void vaddfp( VectorRegister d, VectorRegister a, VectorRegister b); 2265 inline void vsubcuw( VectorRegister d, VectorRegister a, VectorRegister b); 2266 inline void vsubshs( VectorRegister d, VectorRegister a, VectorRegister b); 2267 inline void vsubsbs( VectorRegister d, VectorRegister a, VectorRegister b); 2268 inline void vsubsws( VectorRegister d, VectorRegister a, VectorRegister b); 2269 inline void vsububm( VectorRegister d, VectorRegister a, VectorRegister b); 2270 inline void vsubuwm( VectorRegister d, VectorRegister a, VectorRegister b); 2271 inline void vsubuhm( VectorRegister d, VectorRegister a, VectorRegister b); 2272 inline void vsubudm( VectorRegister d, VectorRegister a, VectorRegister b); 2273 inline void vsububs( VectorRegister d, VectorRegister a, VectorRegister b); 2274 inline void vsubuws( VectorRegister d, VectorRegister a, VectorRegister b); 2275 inline void vsubuhs( VectorRegister d, VectorRegister a, VectorRegister b); 2276 inline void vsubfp( VectorRegister d, VectorRegister a, VectorRegister b); 2277 inline void vmulesb( VectorRegister d, VectorRegister a, VectorRegister b); 2278 inline void vmuleub( VectorRegister d, VectorRegister a, VectorRegister b); 2279 inline void vmulesh( VectorRegister d, VectorRegister a, VectorRegister b); 2280 inline void vmuleuh( VectorRegister d, VectorRegister a, VectorRegister b); 2281 inline void vmulosb( VectorRegister d, VectorRegister a, VectorRegister b); 2282 inline void vmuloub( VectorRegister d, VectorRegister a, VectorRegister b); 2283 inline void vmulosh( VectorRegister d, VectorRegister a, VectorRegister b); 2284 inline void vmulosw( VectorRegister d, VectorRegister a, VectorRegister b); 2285 inline void vmulouh( VectorRegister d, VectorRegister a, VectorRegister b); 2286 inline void vmuluwm( VectorRegister d, VectorRegister a, VectorRegister b); 2287 inline void vmhaddshs(VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c); 2288 inline void vmhraddshs(VectorRegister d,VectorRegister a, VectorRegister b, VectorRegister c); 2289 inline void vmladduhm(VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c); 2290 inline void vmsubuhm( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c); 2291 inline void vmsummbm( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c); 2292 inline void vmsumshm( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c); 2293 inline void vmsumshs( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c); 2294 inline void vmsumuhm( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c); 2295 inline void vmsumuhs( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c); 2296 inline void vmaddfp( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c); 2297 inline void vsumsws( VectorRegister d, VectorRegister a, VectorRegister b); 2298 inline void vsum2sws( VectorRegister d, VectorRegister a, VectorRegister b); 2299 inline void vsum4sbs( VectorRegister d, VectorRegister a, VectorRegister b); 2300 inline void vsum4ubs( VectorRegister d, VectorRegister a, VectorRegister b); 2301 inline void vsum4shs( VectorRegister d, VectorRegister a, VectorRegister b); 2302 inline void vavgsb( VectorRegister d, VectorRegister a, VectorRegister b); 2303 inline void vavgsw( VectorRegister d, VectorRegister a, VectorRegister b); 2304 inline void vavgsh( VectorRegister d, VectorRegister a, VectorRegister b); 2305 inline void vavgub( VectorRegister d, VectorRegister a, VectorRegister b); 2306 inline void vavguw( VectorRegister d, VectorRegister a, VectorRegister b); 2307 inline void vavguh( VectorRegister d, VectorRegister a, VectorRegister b); 2308 inline void vmaxsb( VectorRegister d, VectorRegister a, VectorRegister b); 2309 inline void vmaxsw( VectorRegister d, VectorRegister a, VectorRegister b); 2310 inline void vmaxsh( VectorRegister d, VectorRegister a, VectorRegister b); 2311 inline void vmaxub( VectorRegister d, VectorRegister a, VectorRegister b); 2312 inline void vmaxuw( VectorRegister d, VectorRegister a, VectorRegister b); 2313 inline void vmaxuh( VectorRegister d, VectorRegister a, VectorRegister b); 2314 inline void vminsb( VectorRegister d, VectorRegister a, VectorRegister b); 2315 inline void vminsw( VectorRegister d, VectorRegister a, VectorRegister b); 2316 inline void vminsh( VectorRegister d, VectorRegister a, VectorRegister b); 2317 inline void vminub( VectorRegister d, VectorRegister a, VectorRegister b); 2318 inline void vminuw( VectorRegister d, VectorRegister a, VectorRegister b); 2319 inline void vminuh( VectorRegister d, VectorRegister a, VectorRegister b); 2320 inline void vcmpequb( VectorRegister d, VectorRegister a, VectorRegister b); 2321 inline void vcmpequh( VectorRegister d, VectorRegister a, VectorRegister b); 2322 inline void vcmpequw( VectorRegister d, VectorRegister a, VectorRegister b); 2323 inline void vcmpgtsh( VectorRegister d, VectorRegister a, VectorRegister b); 2324 inline void vcmpgtsb( VectorRegister d, VectorRegister a, VectorRegister b); 2325 inline void vcmpgtsw( VectorRegister d, VectorRegister a, VectorRegister b); 2326 inline void vcmpgtub( VectorRegister d, VectorRegister a, VectorRegister b); 2327 inline void vcmpgtuh( VectorRegister d, VectorRegister a, VectorRegister b); 2328 inline void vcmpgtuw( VectorRegister d, VectorRegister a, VectorRegister b); 2329 inline void vcmpequb_(VectorRegister d, VectorRegister a, VectorRegister b); 2330 inline void vcmpequh_(VectorRegister d, VectorRegister a, VectorRegister b); 2331 inline void vcmpequw_(VectorRegister d, VectorRegister a, VectorRegister b); 2332 inline void vcmpgtsh_(VectorRegister d, VectorRegister a, VectorRegister b); 2333 inline void vcmpgtsb_(VectorRegister d, VectorRegister a, VectorRegister b); 2334 inline void vcmpgtsw_(VectorRegister d, VectorRegister a, VectorRegister b); 2335 inline void vcmpgtub_(VectorRegister d, VectorRegister a, VectorRegister b); 2336 inline void vcmpgtuh_(VectorRegister d, VectorRegister a, VectorRegister b); 2337 inline void vcmpgtuw_(VectorRegister d, VectorRegister a, VectorRegister b); 2338 inline void vand( VectorRegister d, VectorRegister a, VectorRegister b); 2339 inline void vandc( VectorRegister d, VectorRegister a, VectorRegister b); 2340 inline void vnor( VectorRegister d, VectorRegister a, VectorRegister b); 2341 inline void vor( VectorRegister d, VectorRegister a, VectorRegister b); 2342 inline void vmr( VectorRegister d, VectorRegister a); 2343 inline void vxor( VectorRegister d, VectorRegister a, VectorRegister b); 2344 inline void vrld( VectorRegister d, VectorRegister a, VectorRegister b); 2345 inline void vrlb( VectorRegister d, VectorRegister a, VectorRegister b); 2346 inline void vrlw( VectorRegister d, VectorRegister a, VectorRegister b); 2347 inline void vrlh( VectorRegister d, VectorRegister a, VectorRegister b); 2348 inline void vslb( VectorRegister d, VectorRegister a, VectorRegister b); 2349 inline void vskw( VectorRegister d, VectorRegister a, VectorRegister b); 2350 inline void vslh( VectorRegister d, VectorRegister a, VectorRegister b); 2351 inline void vsrb( VectorRegister d, VectorRegister a, VectorRegister b); 2352 inline void vsrw( VectorRegister d, VectorRegister a, VectorRegister b); 2353 inline void vsrh( VectorRegister d, VectorRegister a, VectorRegister b); 2354 inline void vsrab( VectorRegister d, VectorRegister a, VectorRegister b); 2355 inline void vsraw( VectorRegister d, VectorRegister a, VectorRegister b); 2356 inline void vsrah( VectorRegister d, VectorRegister a, VectorRegister b); 2357 inline void vpopcntb( VectorRegister d, VectorRegister b); 2358 inline void vpopcnth( VectorRegister d, VectorRegister b); 2359 inline void vpopcntw( VectorRegister d, VectorRegister b); 2360 inline void vpopcntd( VectorRegister d, VectorRegister b); 2361 // Vector Floating-Point not implemented yet 2362 inline void mtvscr( VectorRegister b); 2363 inline void mfvscr( VectorRegister d); 2364 2365 // Vector-Scalar (VSX) instructions. 2366 inline void lxv( VectorSRegister d, int si16, Register a); 2367 inline void stxv( VectorSRegister d, int si16, Register a); 2368 inline void lxvl( VectorSRegister d, Register a, Register b); 2369 inline void stxvl( VectorSRegister d, Register a, Register b); 2370 inline void lxvd2x( VectorSRegister d, Register a); 2371 inline void lxvd2x( VectorSRegister d, Register a, Register b); 2372 inline void stxvd2x( VectorSRegister d, Register a); 2373 inline void stxvd2x( VectorSRegister d, Register a, Register b); 2374 inline void mtvrwz( VectorRegister d, Register a); 2375 inline void mfvrwz( Register a, VectorRegister d); 2376 inline void mtvrd( VectorRegister d, Register a); 2377 inline void mfvrd( Register a, VectorRegister d); 2378 inline void xxperm( VectorSRegister d, VectorSRegister a, VectorSRegister b); 2379 inline void xxpermx( VectorSRegister d, VectorSRegister a, VectorSRegister b, VectorSRegister c, int ui3); 2380 inline void xxpermdi( VectorSRegister d, VectorSRegister a, VectorSRegister b, int dm); 2381 inline void xxmrghw( VectorSRegister d, VectorSRegister a, VectorSRegister b); 2382 inline void xxmrglw( VectorSRegister d, VectorSRegister a, VectorSRegister b); 2383 inline void mtvsrd( VectorSRegister d, Register a); 2384 inline void mfvsrd( Register d, VectorSRegister a); 2385 inline void mtvsrdd( VectorSRegister d, Register a, Register b); 2386 inline void mtvsrwz( VectorSRegister d, Register a); 2387 inline void mfvsrwz( Register d, VectorSRegister a); 2388 inline void xxspltw( VectorSRegister d, VectorSRegister b, int ui2); 2389 inline void xxlor( VectorSRegister d, VectorSRegister a, VectorSRegister b); 2390 inline void xxlxor( VectorSRegister d, VectorSRegister a, VectorSRegister b); 2391 inline void xxleqv( VectorSRegister d, VectorSRegister a, VectorSRegister b); 2392 inline void xxbrd( VectorSRegister d, VectorSRegister b); 2393 inline void xxbrw( VectorSRegister d, VectorSRegister b); 2394 inline void xxland( VectorSRegister d, VectorSRegister a, VectorSRegister b); 2395 inline void xxsel( VectorSRegister d, VectorSRegister a, VectorSRegister b, VectorSRegister c); 2396 inline void xxspltib( VectorSRegister d, int ui8); 2397 inline void xvdivsp( VectorSRegister d, VectorSRegister a, VectorSRegister b); 2398 inline void xvdivdp( VectorSRegister d, VectorSRegister a, VectorSRegister b); 2399 inline void xvabssp( VectorSRegister d, VectorSRegister b); 2400 inline void xvabsdp( VectorSRegister d, VectorSRegister b); 2401 inline void xvnegsp( VectorSRegister d, VectorSRegister b); 2402 inline void xvnegdp( VectorSRegister d, VectorSRegister b); 2403 inline void xvsqrtsp( VectorSRegister d, VectorSRegister b); 2404 inline void xvsqrtdp( VectorSRegister d, VectorSRegister b); 2405 inline void xscvdpspn(VectorSRegister d, VectorSRegister b); 2406 inline void xvadddp( VectorSRegister d, VectorSRegister a, VectorSRegister b); 2407 inline void xvsubdp( VectorSRegister d, VectorSRegister a, VectorSRegister b); 2408 inline void xvmulsp( VectorSRegister d, VectorSRegister a, VectorSRegister b); 2409 inline void xvmuldp( VectorSRegister d, VectorSRegister a, VectorSRegister b); 2410 inline void xvmaddasp(VectorSRegister d, VectorSRegister a, VectorSRegister b); 2411 inline void xvmaddadp(VectorSRegister d, VectorSRegister a, VectorSRegister b); 2412 inline void xvmsubasp(VectorSRegister d, VectorSRegister a, VectorSRegister b); 2413 inline void xvmsubadp(VectorSRegister d, VectorSRegister a, VectorSRegister b); 2414 inline void xvnmsubasp(VectorSRegister d, VectorSRegister a, VectorSRegister b); 2415 inline void xvnmsubadp(VectorSRegister d, VectorSRegister a, VectorSRegister b); 2416 inline void xvrdpi( VectorSRegister d, VectorSRegister b); 2417 inline void xvrdpic( VectorSRegister d, VectorSRegister b); 2418 inline void xvrdpim( VectorSRegister d, VectorSRegister b); 2419 inline void xvrdpip( VectorSRegister d, VectorSRegister b); 2420 2421 // VSX Extended Mnemonics 2422 inline void xxspltd( VectorSRegister d, VectorSRegister a, int x); 2423 inline void xxmrghd( VectorSRegister d, VectorSRegister a, VectorSRegister b); 2424 inline void xxmrgld( VectorSRegister d, VectorSRegister a, VectorSRegister b); 2425 inline void xxswapd( VectorSRegister d, VectorSRegister a); 2426 2427 // Vector-Scalar (VSX) instructions. 2428 inline void mtfprd( FloatRegister d, Register a); 2429 inline void mtfprwa( FloatRegister d, Register a); 2430 inline void mffprd( Register a, FloatRegister d); 2431 2432 // Deliver A Random Number (introduced with POWER9) 2433 inline void darn( Register d, int l = 1 /*L=CRN*/); 2434 2435 // AES (introduced with Power 8) 2436 inline void vcipher( VectorRegister d, VectorRegister a, VectorRegister b); 2437 inline void vcipherlast( VectorRegister d, VectorRegister a, VectorRegister b); 2438 inline void vncipher( VectorRegister d, VectorRegister a, VectorRegister b); 2439 inline void vncipherlast(VectorRegister d, VectorRegister a, VectorRegister b); 2440 inline void vsbox( VectorRegister d, VectorRegister a); 2441 2442 // SHA (introduced with Power 8) 2443 inline void vshasigmad(VectorRegister d, VectorRegister a, bool st, int six); 2444 inline void vshasigmaw(VectorRegister d, VectorRegister a, bool st, int six); 2445 2446 // Vector Binary Polynomial Multiplication (introduced with Power 8) 2447 inline void vpmsumb( VectorRegister d, VectorRegister a, VectorRegister b); 2448 inline void vpmsumd( VectorRegister d, VectorRegister a, VectorRegister b); 2449 inline void vpmsumh( VectorRegister d, VectorRegister a, VectorRegister b); 2450 inline void vpmsumw( VectorRegister d, VectorRegister a, VectorRegister b); 2451 2452 // Vector Permute and Xor (introduced with Power 8) 2453 inline void vpermxor( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c); 2454 2455 // Transactional Memory instructions (introduced with Power 8) 2456 inline void tbegin_(); // R=0 2457 inline void tbeginrot_(); // R=1 Rollback-Only Transaction 2458 inline void tend_(); // A=0 2459 inline void tendall_(); // A=1 2460 inline void tabort_(); 2461 inline void tabort_(Register a); 2462 inline void tabortwc_(int t, Register a, Register b); 2463 inline void tabortwci_(int t, Register a, int si); 2464 inline void tabortdc_(int t, Register a, Register b); 2465 inline void tabortdci_(int t, Register a, int si); 2466 inline void tsuspend_(); // tsr with L=0 2467 inline void tresume_(); // tsr with L=1 2468 inline void tcheck(int f); 2469 2470 static bool is_tbegin(int x) { 2471 return TBEGIN_OPCODE == (x & (0x3f << OPCODE_SHIFT | 0x3ff << 1)); 2472 } 2473 2474 // The following encoders use r0 as second operand. These instructions 2475 // read r0 as '0'. 2476 inline void lwzx( Register d, Register s2); 2477 inline void lwz( Register d, int si16); 2478 inline void lwax( Register d, Register s2); 2479 inline void lwa( Register d, int si16); 2480 inline void lwbrx(Register d, Register s2); 2481 inline void lhzx( Register d, Register s2); 2482 inline void lhz( Register d, int si16); 2483 inline void lhax( Register d, Register s2); 2484 inline void lha( Register d, int si16); 2485 inline void lhbrx(Register d, Register s2); 2486 inline void lbzx( Register d, Register s2); 2487 inline void lbz( Register d, int si16); 2488 inline void ldx( Register d, Register s2); 2489 inline void ld( Register d, int si16); 2490 inline void ld( Register d, ByteSize si16); 2491 inline void ldbrx(Register d, Register s2); 2492 inline void stwx( Register d, Register s2); 2493 inline void stw( Register d, int si16); 2494 inline void stwbrx( Register d, Register s2); 2495 inline void sthx( Register d, Register s2); 2496 inline void sth( Register d, int si16); 2497 inline void sthbrx( Register d, Register s2); 2498 inline void stbx( Register d, Register s2); 2499 inline void stb( Register d, int si16); 2500 inline void stdx( Register d, Register s2); 2501 inline void std( Register d, int si16); 2502 inline void stdbrx( Register d, Register s2); 2503 2504 // PPC 2, section 3.2.1 Instruction Cache Instructions 2505 inline void icbi( Register s2); 2506 // PPC 2, section 3.2.2 Data Cache Instructions 2507 //inlinevoid dcba( Register s2); // Instruction for embedded processor only. 2508 inline void dcbz( Register s2); 2509 inline void dcbst( Register s2); 2510 inline void dcbf( Register s2); 2511 // dcache read hint 2512 inline void dcbt( Register s2); 2513 inline void dcbtct( Register s2, int ct); 2514 inline void dcbtds( Register s2, int ds); 2515 // dcache write hint 2516 inline void dcbtst( Register s2); 2517 inline void dcbtstct(Register s2, int ct); 2518 2519 // Atomics: use ra0mem to disallow R0 as base. 2520 inline void lbarx_unchecked(Register d, Register b, int eh1); 2521 inline void lharx_unchecked(Register d, Register b, int eh1); 2522 inline void lwarx_unchecked(Register d, Register b, int eh1); 2523 inline void ldarx_unchecked(Register d, Register b, int eh1); 2524 inline void lqarx_unchecked(Register d, Register b, int eh1); 2525 inline void lbarx( Register d, Register b, bool hint_exclusive_access); 2526 inline void lharx( Register d, Register b, bool hint_exclusive_access); 2527 inline void lwarx( Register d, Register b, bool hint_exclusive_access); 2528 inline void ldarx( Register d, Register b, bool hint_exclusive_access); 2529 inline void lqarx( Register d, Register b, bool hint_exclusive_access); 2530 inline void stbcx_(Register s, Register b); 2531 inline void sthcx_(Register s, Register b); 2532 inline void stwcx_(Register s, Register b); 2533 inline void stdcx_(Register s, Register b); 2534 inline void stqcx_(Register s, Register b); 2535 inline void lfs( FloatRegister d, int si16); 2536 inline void lfsx( FloatRegister d, Register b); 2537 inline void lfd( FloatRegister d, int si16); 2538 inline void lfdx( FloatRegister d, Register b); 2539 inline void stfs( FloatRegister s, int si16); 2540 inline void stfsx( FloatRegister s, Register b); 2541 inline void stfd( FloatRegister s, int si16); 2542 inline void stfdx( FloatRegister s, Register b); 2543 inline void lvebx( VectorRegister d, Register s2); 2544 inline void lvehx( VectorRegister d, Register s2); 2545 inline void lvewx( VectorRegister d, Register s2); 2546 inline void lvx( VectorRegister d, Register s2); 2547 inline void lvxl( VectorRegister d, Register s2); 2548 inline void stvebx(VectorRegister d, Register s2); 2549 inline void stvehx(VectorRegister d, Register s2); 2550 inline void stvewx(VectorRegister d, Register s2); 2551 inline void stvx( VectorRegister d, Register s2); 2552 inline void stvxl( VectorRegister d, Register s2); 2553 inline void lvsl( VectorRegister d, Register s2); 2554 inline void lvsr( VectorRegister d, Register s2); 2555 2556 // Endianness specific concatenation of 2 loaded vectors. 2557 inline void load_perm(VectorRegister perm, Register addr); 2558 inline void vec_perm(VectorRegister first_dest, VectorRegister second, VectorRegister perm); 2559 inline void vec_perm(VectorRegister dest, VectorRegister first, VectorRegister second, VectorRegister perm); 2560 2561 // RegisterOrConstant versions. 2562 // These emitters choose between the versions using two registers and 2563 // those with register and immediate, depending on the content of roc. 2564 // If the constant is not encodable as immediate, instructions to 2565 // load the constant are emitted beforehand. Store instructions need a 2566 // tmp reg if the constant is not encodable as immediate. 2567 // Size unpredictable. 2568 void ld( Register d, RegisterOrConstant roc, Register s1 = noreg); 2569 void lwa( Register d, RegisterOrConstant roc, Register s1 = noreg); 2570 void lwz( Register d, RegisterOrConstant roc, Register s1 = noreg); 2571 void lha( Register d, RegisterOrConstant roc, Register s1 = noreg); 2572 void lhz( Register d, RegisterOrConstant roc, Register s1 = noreg); 2573 void lbz( Register d, RegisterOrConstant roc, Register s1 = noreg); 2574 void std( Register d, RegisterOrConstant roc, Register s1 = noreg, Register tmp = noreg); 2575 void stw( Register d, RegisterOrConstant roc, Register s1 = noreg, Register tmp = noreg); 2576 void sth( Register d, RegisterOrConstant roc, Register s1 = noreg, Register tmp = noreg); 2577 void stb( Register d, RegisterOrConstant roc, Register s1 = noreg, Register tmp = noreg); 2578 void add( Register d, RegisterOrConstant roc, Register s1); 2579 void subf(Register d, RegisterOrConstant roc, Register s1); 2580 void cmpd(ConditionRegister d, RegisterOrConstant roc, Register s1); 2581 // Load pointer d from s1+roc. 2582 void ld_ptr(Register d, RegisterOrConstant roc, Register s1 = noreg) { ld(d, roc, s1); } 2583 2584 // Emit several instructions to load a 64 bit constant. This issues a fixed 2585 // instruction pattern so that the constant can be patched later on. 2586 enum { 2587 load_const_size = 5 * BytesPerInstWord 2588 }; 2589 void load_const(Register d, long a, Register tmp = noreg); 2590 inline void load_const(Register d, void* a, Register tmp = noreg); 2591 inline void load_const(Register d, Label& L, Register tmp = noreg); 2592 inline void load_const(Register d, AddressLiteral& a, Register tmp = noreg); 2593 inline void load_const32(Register d, int i); // load signed int (patchable) 2594 2595 // Load a 64 bit constant, optimized, not identifiable. 2596 // Tmp can be used to increase ILP. Set return_simm16_rest = true to get a 2597 // 16 bit immediate offset. This is useful if the offset can be encoded in 2598 // a succeeding instruction. 2599 int load_const_optimized(Register d, long a, Register tmp = noreg, bool return_simm16_rest = false); 2600 inline int load_const_optimized(Register d, void* a, Register tmp = noreg, bool return_simm16_rest = false) { 2601 return load_const_optimized(d, (long)(unsigned long)a, tmp, return_simm16_rest); 2602 } 2603 2604 // If return_simm16_rest, the return value needs to get added afterwards. 2605 int add_const_optimized(Register d, Register s, long x, Register tmp = R0, bool return_simm16_rest = false); 2606 inline int add_const_optimized(Register d, Register s, void* a, Register tmp = R0, bool return_simm16_rest = false) { 2607 return add_const_optimized(d, s, (long)(unsigned long)a, tmp, return_simm16_rest); 2608 } 2609 2610 // If return_simm16_rest, the return value needs to get added afterwards. 2611 inline int sub_const_optimized(Register d, Register s, long x, Register tmp = R0, bool return_simm16_rest = false) { 2612 return add_const_optimized(d, s, -x, tmp, return_simm16_rest); 2613 } 2614 inline int sub_const_optimized(Register d, Register s, void* a, Register tmp = R0, bool return_simm16_rest = false) { 2615 return sub_const_optimized(d, s, (long)(unsigned long)a, tmp, return_simm16_rest); 2616 } 2617 2618 // Creation 2619 Assembler(CodeBuffer* code) : AbstractAssembler(code) { 2620 #ifdef CHECK_DELAY 2621 delay_state = no_delay; 2622 #endif 2623 } 2624 2625 // Testing 2626 #ifndef PRODUCT 2627 void test_asm(); 2628 #endif 2629 }; 2630 2631 2632 #endif // CPU_PPC_ASSEMBLER_PPC_HPP --- EOF ---