1 /*
2 * Copyright (c) 2002, 2023, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2012, 2023 SAP SE. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #ifndef CPU_PPC_ASSEMBLER_PPC_HPP
27 #define CPU_PPC_ASSEMBLER_PPC_HPP
28
29 #include "asm/assembler.hpp"
30 #include "asm/register.hpp"
31
32 // Address is an abstraction used to represent a memory location
33 // as used in assembler instructions.
34 // PPC instructions grok either baseReg + indexReg or baseReg + disp.
35 class Address {
36 private:
37 Register _base; // Base register.
38 Register _index; // Index register.
39 intptr_t _disp; // Displacement.
40
41 public:
42 Address(Register b, Register i, address d = 0)
43 : _base(b), _index(i), _disp((intptr_t)d) {
44 assert(i == noreg || d == 0, "can't have both");
45 }
46
47 Address(Register b, address d = 0)
48 : _base(b), _index(noreg), _disp((intptr_t)d) {}
49
50 Address(Register b, ByteSize d)
51 : _base(b), _index(noreg), _disp((intptr_t)d) {}
52
53 Address(Register b, intptr_t d)
54 : _base(b), _index(noreg), _disp(d) {}
55
56 Address(Register b, RegisterOrConstant roc)
57 : _base(b), _index(noreg), _disp(0) {
58 if (roc.is_constant()) _disp = roc.as_constant(); else _index = roc.as_register();
59 }
60
61 Address()
62 : _base(noreg), _index(noreg), _disp(0) {}
63
64 // accessors
65 Register base() const { return _base; }
66 Register index() const { return _index; }
67 int disp() const { return (int)_disp; }
68 bool is_const() const { return _base == noreg && _index == noreg; }
69 };
70
71 class AddressLiteral {
72 private:
73 address _address;
74 RelocationHolder _rspec;
75
76 RelocationHolder rspec_from_rtype(relocInfo::relocType rtype, address addr) {
77 switch (rtype) {
78 case relocInfo::external_word_type:
79 return external_word_Relocation::spec(addr);
80 case relocInfo::internal_word_type:
81 return internal_word_Relocation::spec(addr);
82 case relocInfo::opt_virtual_call_type:
83 return opt_virtual_call_Relocation::spec();
84 case relocInfo::static_call_type:
85 return static_call_Relocation::spec();
86 case relocInfo::runtime_call_type:
87 return runtime_call_Relocation::spec();
88 case relocInfo::none:
89 return RelocationHolder();
90 default:
91 ShouldNotReachHere();
92 return RelocationHolder();
93 }
94 }
95
96 protected:
97 // creation
98 AddressLiteral() : _address(nullptr), _rspec() {}
99
100 public:
101 AddressLiteral(address addr, RelocationHolder const& rspec)
102 : _address(addr),
103 _rspec(rspec) {}
104
105 AddressLiteral(address addr, relocInfo::relocType rtype = relocInfo::none)
106 : _address((address) addr),
107 _rspec(rspec_from_rtype(rtype, (address) addr)) {}
108
109 AddressLiteral(oop* addr, relocInfo::relocType rtype = relocInfo::none)
110 : _address((address) addr),
111 _rspec(rspec_from_rtype(rtype, (address) addr)) {}
112
113 intptr_t value() const { return (intptr_t) _address; }
114
115 const RelocationHolder& rspec() const { return _rspec; }
116 };
117
118 // Argument is an abstraction used to represent an outgoing
119 // actual argument or an incoming formal parameter, whether
120 // it resides in memory or in a register, in a manner consistent
121 // with the PPC Application Binary Interface, or ABI. This is
122 // often referred to as the native or C calling convention.
123
124 class Argument {
125 private:
126 int _number; // The number of the argument.
127 public:
128 enum {
129 // Only 8 registers may contain integer parameters.
130 n_register_parameters = 8,
131 // Can have up to 8 floating registers.
132 n_float_register_parameters = 8,
133
134 // PPC C calling conventions.
135 // The first eight arguments are passed in int regs if they are int.
136 n_int_register_parameters_c = 8,
137 // The first thirteen float arguments are passed in float regs.
138 n_float_register_parameters_c = 13,
139 // Only the first 8 parameters are not placed on the stack. Aix disassembly
140 // shows that xlC places all float args after argument 8 on the stack AND
141 // in a register. This is not documented, but we follow this convention, too.
142 n_regs_not_on_stack_c = 8,
143
144 n_int_register_parameters_j = 8, // duplicates num_java_iarg_registers
145 n_float_register_parameters_j = 13, // num_java_farg_registers
146 };
147 // creation
148 Argument(int number) : _number(number) {}
149
150 int number() const { return _number; }
151
152 // Locating register-based arguments:
153 bool is_register() const { return _number < n_register_parameters; }
154
155 Register as_register() const {
156 assert(is_register(), "must be a register argument");
157 return as_Register(number() + R3_ARG1->encoding());
158 }
159 };
160
161 #if !defined(ABI_ELFv2)
162 // A ppc64 function descriptor.
163 struct FunctionDescriptor {
164 private:
165 address _entry;
166 address _toc;
167 address _env;
168
169 public:
170 inline address entry() const { return _entry; }
171 inline address toc() const { return _toc; }
172 inline address env() const { return _env; }
173
174 inline void set_entry(address entry) { _entry = entry; }
175 inline void set_toc( address toc) { _toc = toc; }
176 inline void set_env( address env) { _env = env; }
177
178 inline static ByteSize entry_offset() { return byte_offset_of(FunctionDescriptor, _entry); }
179 inline static ByteSize toc_offset() { return byte_offset_of(FunctionDescriptor, _toc); }
180 inline static ByteSize env_offset() { return byte_offset_of(FunctionDescriptor, _env); }
181
182 // Friend functions can be called without loading toc and env.
183 enum {
184 friend_toc = 0xcafe,
185 friend_env = 0xc0de
186 };
187
188 inline bool is_friend_function() const {
189 return (toc() == (address) friend_toc) && (env() == (address) friend_env);
190 }
191
192 // Constructor for stack-allocated instances.
193 FunctionDescriptor() {
194 _entry = (address) 0xbad;
195 _toc = (address) 0xbad;
196 _env = (address) 0xbad;
197 }
198 };
199 #endif
200
201
202 // The PPC Assembler: Pure assembler doing NO optimizations on the
203 // instruction level; i.e., what you write is what you get. The
204 // Assembler is generating code into a CodeBuffer.
205
206 class Assembler : public AbstractAssembler {
207 protected:
208 // Displacement routines
209 static int patched_branch(int dest_pos, int inst, int inst_pos);
210 static int branch_destination(int inst, int pos);
211
212 friend class AbstractAssembler;
213
214 // Code patchers need various routines like inv_wdisp()
215 friend class NativeInstruction;
216 friend class NativeGeneralJump;
217 friend class Relocation;
218
219 public:
220
221 enum shifts {
222 XO_21_29_SHIFT = 2,
223 XO_21_30_SHIFT = 1,
224 XO_27_29_SHIFT = 2,
225 XO_30_31_SHIFT = 0,
226 SPR_5_9_SHIFT = 11u, // SPR_5_9 field in bits 11 -- 15
227 SPR_0_4_SHIFT = 16u, // SPR_0_4 field in bits 16 -- 20
228 RS_SHIFT = 21u, // RS field in bits 21 -- 25
229 OPCODE_SHIFT = 26u, // opcode in bits 26 -- 31
230
231 // Shift counts in prefix word
232 PRE_TYPE_SHIFT = 24u, // Prefix type in bits 24 -- 25
233 PRE_ST1_SHIFT = 23u, // ST1 field in bits 23 -- 23
234 PRE_R_SHIFT = 20u, // R-bit in bits 20 -- 20
235 PRE_ST4_SHIFT = 20u, // ST4 field in bits 23 -- 20
236 };
237
238 enum opcdxos_masks {
239 XL_FORM_OPCODE_MASK = (63u << OPCODE_SHIFT) | (1023u << 1),
240 ANDI_OPCODE_MASK = (63u << OPCODE_SHIFT),
241 ADDI_OPCODE_MASK = (63u << OPCODE_SHIFT),
242 ADDIS_OPCODE_MASK = (63u << OPCODE_SHIFT),
243 BXX_OPCODE_MASK = (63u << OPCODE_SHIFT),
244 BCXX_OPCODE_MASK = (63u << OPCODE_SHIFT),
245 CMPLI_OPCODE_MASK = (63u << OPCODE_SHIFT),
246 // trap instructions
247 TDI_OPCODE_MASK = (63u << OPCODE_SHIFT),
248 TWI_OPCODE_MASK = (63u << OPCODE_SHIFT),
249 TD_OPCODE_MASK = (63u << OPCODE_SHIFT) | (1023u << 1),
250 TW_OPCODE_MASK = (63u << OPCODE_SHIFT) | (1023u << 1),
251 LD_OPCODE_MASK = (63u << OPCODE_SHIFT) | (3u << XO_30_31_SHIFT), // DS-FORM
252 STD_OPCODE_MASK = LD_OPCODE_MASK,
253 STDU_OPCODE_MASK = STD_OPCODE_MASK,
254 STDX_OPCODE_MASK = (63u << OPCODE_SHIFT) | (1023u << 1),
255 STDUX_OPCODE_MASK = STDX_OPCODE_MASK,
256 STW_OPCODE_MASK = (63u << OPCODE_SHIFT),
257 STWU_OPCODE_MASK = STW_OPCODE_MASK,
258 STWX_OPCODE_MASK = (63u << OPCODE_SHIFT) | (1023u << 1),
259 STWUX_OPCODE_MASK = STWX_OPCODE_MASK,
260 MTCTR_OPCODE_MASK = ~(31u << RS_SHIFT),
261 ORI_OPCODE_MASK = (63u << OPCODE_SHIFT),
262 ORIS_OPCODE_MASK = (63u << OPCODE_SHIFT),
263 RLDICR_OPCODE_MASK = (63u << OPCODE_SHIFT) | (7u << XO_27_29_SHIFT)
264 };
265
266 enum opcdxos {
267 ADD_OPCODE = (31u << OPCODE_SHIFT | 266u << 1),
268 ADDC_OPCODE = (31u << OPCODE_SHIFT | 10u << 1),
269 ADDI_OPCODE = (14u << OPCODE_SHIFT),
270 ADDIS_OPCODE = (15u << OPCODE_SHIFT),
271 ADDIC__OPCODE = (13u << OPCODE_SHIFT),
272 ADDE_OPCODE = (31u << OPCODE_SHIFT | 138u << 1),
273 ADDME_OPCODE = (31u << OPCODE_SHIFT | 234u << 1),
274 ADDZE_OPCODE = (31u << OPCODE_SHIFT | 202u << 1),
275 SUBF_OPCODE = (31u << OPCODE_SHIFT | 40u << 1),
276 SUBFC_OPCODE = (31u << OPCODE_SHIFT | 8u << 1),
277 SUBFE_OPCODE = (31u << OPCODE_SHIFT | 136u << 1),
278 SUBFIC_OPCODE = (8u << OPCODE_SHIFT),
279 SUBFME_OPCODE = (31u << OPCODE_SHIFT | 232u << 1),
280 SUBFZE_OPCODE = (31u << OPCODE_SHIFT | 200u << 1),
281 DIVW_OPCODE = (31u << OPCODE_SHIFT | 491u << 1),
282 DIVWU_OPCODE = (31u << OPCODE_SHIFT | 459u << 1),
283 MULLW_OPCODE = (31u << OPCODE_SHIFT | 235u << 1),
284 MULHW_OPCODE = (31u << OPCODE_SHIFT | 75u << 1),
285 MULHWU_OPCODE = (31u << OPCODE_SHIFT | 11u << 1),
286 MULLI_OPCODE = (7u << OPCODE_SHIFT),
287 AND_OPCODE = (31u << OPCODE_SHIFT | 28u << 1),
288 ANDI_OPCODE = (28u << OPCODE_SHIFT),
289 ANDIS_OPCODE = (29u << OPCODE_SHIFT),
290 ANDC_OPCODE = (31u << OPCODE_SHIFT | 60u << 1),
291 ORC_OPCODE = (31u << OPCODE_SHIFT | 412u << 1),
292 OR_OPCODE = (31u << OPCODE_SHIFT | 444u << 1),
293 ORI_OPCODE = (24u << OPCODE_SHIFT),
294 ORIS_OPCODE = (25u << OPCODE_SHIFT),
295 XOR_OPCODE = (31u << OPCODE_SHIFT | 316u << 1),
296 XORI_OPCODE = (26u << OPCODE_SHIFT),
297 XORIS_OPCODE = (27u << OPCODE_SHIFT),
298
299 NEG_OPCODE = (31u << OPCODE_SHIFT | 104u << 1),
300
301 RLWINM_OPCODE = (21u << OPCODE_SHIFT),
302 CLRRWI_OPCODE = RLWINM_OPCODE,
303 CLRLWI_OPCODE = RLWINM_OPCODE,
304
305 RLWIMI_OPCODE = (20u << OPCODE_SHIFT),
306
307 SLW_OPCODE = (31u << OPCODE_SHIFT | 24u << 1),
308 SLWI_OPCODE = RLWINM_OPCODE,
309 SRW_OPCODE = (31u << OPCODE_SHIFT | 536u << 1),
310 SRWI_OPCODE = RLWINM_OPCODE,
311 SRAW_OPCODE = (31u << OPCODE_SHIFT | 792u << 1),
312 SRAWI_OPCODE = (31u << OPCODE_SHIFT | 824u << 1),
313
314 CMP_OPCODE = (31u << OPCODE_SHIFT | 0u << 1),
315 CMPI_OPCODE = (11u << OPCODE_SHIFT),
316 CMPL_OPCODE = (31u << OPCODE_SHIFT | 32u << 1),
317 CMPLI_OPCODE = (10u << OPCODE_SHIFT),
318 CMPRB_OPCODE = (31u << OPCODE_SHIFT | 192u << 1),
319 CMPEQB_OPCODE = (31u << OPCODE_SHIFT | 224u << 1),
320
321 ISEL_OPCODE = (31u << OPCODE_SHIFT | 15u << 1),
322
323 // Special purpose registers
324 MTSPR_OPCODE = (31u << OPCODE_SHIFT | 467u << 1),
325 MFSPR_OPCODE = (31u << OPCODE_SHIFT | 339u << 1),
326
327 MTXER_OPCODE = (MTSPR_OPCODE | 1 << SPR_0_4_SHIFT),
328 MFXER_OPCODE = (MFSPR_OPCODE | 1 << SPR_0_4_SHIFT),
329
330 MTDSCR_OPCODE = (MTSPR_OPCODE | 3 << SPR_0_4_SHIFT),
331 MFDSCR_OPCODE = (MFSPR_OPCODE | 3 << SPR_0_4_SHIFT),
332
333 MTLR_OPCODE = (MTSPR_OPCODE | 8 << SPR_0_4_SHIFT),
334 MFLR_OPCODE = (MFSPR_OPCODE | 8 << SPR_0_4_SHIFT),
335
336 MTCTR_OPCODE = (MTSPR_OPCODE | 9 << SPR_0_4_SHIFT),
337 MFCTR_OPCODE = (MFSPR_OPCODE | 9 << SPR_0_4_SHIFT),
338
339 // Attention: Higher and lower half are inserted in reversed order.
340 MTVRSAVE_OPCODE = (MTSPR_OPCODE | 8 << SPR_5_9_SHIFT | 0 << SPR_0_4_SHIFT),
341 MFVRSAVE_OPCODE = (MFSPR_OPCODE | 8 << SPR_5_9_SHIFT | 0 << SPR_0_4_SHIFT),
342
343 MFTB_OPCODE = (MFSPR_OPCODE | 8 << SPR_5_9_SHIFT | 12 << SPR_0_4_SHIFT),
344
345 MTCRF_OPCODE = (31u << OPCODE_SHIFT | 144u << 1),
346 MFCR_OPCODE = (31u << OPCODE_SHIFT | 19u << 1),
347 MCRF_OPCODE = (19u << OPCODE_SHIFT | 0u << 1),
348 MCRXRX_OPCODE = (31u << OPCODE_SHIFT | 576u << 1),
349 SETB_OPCODE = (31u << OPCODE_SHIFT | 128u << 1),
350
351 SETBC_OPCODE = (31u << OPCODE_SHIFT | 384u << 1),
352 SETNBC_OPCODE = (31u << OPCODE_SHIFT | 448u << 1),
353
354 // condition register logic instructions
355 CRAND_OPCODE = (19u << OPCODE_SHIFT | 257u << 1),
356 CRNAND_OPCODE = (19u << OPCODE_SHIFT | 225u << 1),
357 CROR_OPCODE = (19u << OPCODE_SHIFT | 449u << 1),
358 CRXOR_OPCODE = (19u << OPCODE_SHIFT | 193u << 1),
359 CRNOR_OPCODE = (19u << OPCODE_SHIFT | 33u << 1),
360 CREQV_OPCODE = (19u << OPCODE_SHIFT | 289u << 1),
361 CRANDC_OPCODE = (19u << OPCODE_SHIFT | 129u << 1),
362 CRORC_OPCODE = (19u << OPCODE_SHIFT | 417u << 1),
363
364 BCLR_OPCODE = (19u << OPCODE_SHIFT | 16u << 1),
365 BXX_OPCODE = (18u << OPCODE_SHIFT),
366 BCXX_OPCODE = (16u << OPCODE_SHIFT),
367
368 // CTR-related opcodes
369 BCCTR_OPCODE = (19u << OPCODE_SHIFT | 528u << 1),
370
371 LWZ_OPCODE = (32u << OPCODE_SHIFT),
372 LWZX_OPCODE = (31u << OPCODE_SHIFT | 23u << 1),
373 LWZU_OPCODE = (33u << OPCODE_SHIFT),
374 LWBRX_OPCODE = (31u << OPCODE_SHIFT | 534 << 1),
375
376 LHA_OPCODE = (42u << OPCODE_SHIFT),
377 LHAX_OPCODE = (31u << OPCODE_SHIFT | 343u << 1),
378 LHAU_OPCODE = (43u << OPCODE_SHIFT),
379
380 LHZ_OPCODE = (40u << OPCODE_SHIFT),
381 LHZX_OPCODE = (31u << OPCODE_SHIFT | 279u << 1),
382 LHZU_OPCODE = (41u << OPCODE_SHIFT),
383 LHBRX_OPCODE = (31u << OPCODE_SHIFT | 790 << 1),
384
385 LBZ_OPCODE = (34u << OPCODE_SHIFT),
386 LBZX_OPCODE = (31u << OPCODE_SHIFT | 87u << 1),
387 LBZU_OPCODE = (35u << OPCODE_SHIFT),
388
389 STW_OPCODE = (36u << OPCODE_SHIFT),
390 STWX_OPCODE = (31u << OPCODE_SHIFT | 151u << 1),
391 STWU_OPCODE = (37u << OPCODE_SHIFT),
392 STWUX_OPCODE = (31u << OPCODE_SHIFT | 183u << 1),
393 STWBRX_OPCODE = (31u << OPCODE_SHIFT | 662u << 1),
394
395 STH_OPCODE = (44u << OPCODE_SHIFT),
396 STHX_OPCODE = (31u << OPCODE_SHIFT | 407u << 1),
397 STHU_OPCODE = (45u << OPCODE_SHIFT),
398 STHBRX_OPCODE = (31u << OPCODE_SHIFT | 918u << 1),
399
400 STB_OPCODE = (38u << OPCODE_SHIFT),
401 STBX_OPCODE = (31u << OPCODE_SHIFT | 215u << 1),
402 STBU_OPCODE = (39u << OPCODE_SHIFT),
403
404 EXTSB_OPCODE = (31u << OPCODE_SHIFT | 954u << 1),
405 EXTSH_OPCODE = (31u << OPCODE_SHIFT | 922u << 1),
406 EXTSW_OPCODE = (31u << OPCODE_SHIFT | 986u << 1), // X-FORM
407
408 // 32 bit opcode encodings
409
410 LWA_OPCODE = (58u << OPCODE_SHIFT | 2u << XO_30_31_SHIFT), // DS-FORM
411 LWAX_OPCODE = (31u << OPCODE_SHIFT | 341u << XO_21_30_SHIFT), // X-FORM
412
413 CNTLZW_OPCODE = (31u << OPCODE_SHIFT | 26u << XO_21_30_SHIFT), // X-FORM
414 CNTTZW_OPCODE = (31u << OPCODE_SHIFT | 538u << XO_21_30_SHIFT), // X-FORM
415
416 // 64 bit opcode encodings
417
418 LD_OPCODE = (58u << OPCODE_SHIFT | 0u << XO_30_31_SHIFT), // DS-FORM
419 LDU_OPCODE = (58u << OPCODE_SHIFT | 1u << XO_30_31_SHIFT), // DS-FORM
420 LDX_OPCODE = (31u << OPCODE_SHIFT | 21u << XO_21_30_SHIFT), // X-FORM
421 LDBRX_OPCODE = (31u << OPCODE_SHIFT | 532u << 1), // X-FORM
422
423 STD_OPCODE = (62u << OPCODE_SHIFT | 0u << XO_30_31_SHIFT), // DS-FORM
424 STDU_OPCODE = (62u << OPCODE_SHIFT | 1u << XO_30_31_SHIFT), // DS-FORM
425 STDUX_OPCODE = (31u << OPCODE_SHIFT | 181u << 1), // X-FORM
426 STDX_OPCODE = (31u << OPCODE_SHIFT | 149u << XO_21_30_SHIFT), // X-FORM
427 STDBRX_OPCODE = (31u << OPCODE_SHIFT | 660u << 1), // X-FORM
428
429 RLDICR_OPCODE = (30u << OPCODE_SHIFT | 1u << XO_27_29_SHIFT), // MD-FORM
430 RLDICL_OPCODE = (30u << OPCODE_SHIFT | 0u << XO_27_29_SHIFT), // MD-FORM
431 RLDIC_OPCODE = (30u << OPCODE_SHIFT | 2u << XO_27_29_SHIFT), // MD-FORM
432 RLDIMI_OPCODE = (30u << OPCODE_SHIFT | 3u << XO_27_29_SHIFT), // MD-FORM
433
434 SRADI_OPCODE = (31u << OPCODE_SHIFT | 413u << XO_21_29_SHIFT), // XS-FORM
435
436 SLD_OPCODE = (31u << OPCODE_SHIFT | 27u << 1), // X-FORM
437 SRD_OPCODE = (31u << OPCODE_SHIFT | 539u << 1), // X-FORM
438 SRAD_OPCODE = (31u << OPCODE_SHIFT | 794u << 1), // X-FORM
439
440 MULLD_OPCODE = (31u << OPCODE_SHIFT | 233u << 1), // XO-FORM
441 MULHD_OPCODE = (31u << OPCODE_SHIFT | 73u << 1), // XO-FORM
442 MULHDU_OPCODE = (31u << OPCODE_SHIFT | 9u << 1), // XO-FORM
443 DIVD_OPCODE = (31u << OPCODE_SHIFT | 489u << 1), // XO-FORM
444 DIVDU_OPCODE = (31u << OPCODE_SHIFT | 457u << 1), // XO-FORM
445
446 CNTLZD_OPCODE = (31u << OPCODE_SHIFT | 58u << XO_21_30_SHIFT), // X-FORM
447 CNTTZD_OPCODE = (31u << OPCODE_SHIFT | 570u << XO_21_30_SHIFT), // X-FORM
448 NAND_OPCODE = (31u << OPCODE_SHIFT | 476u << XO_21_30_SHIFT), // X-FORM
449 NOR_OPCODE = (31u << OPCODE_SHIFT | 124u << XO_21_30_SHIFT), // X-FORM
450
451 // Byte reverse opcodes (introduced with Power10)
452 BRH_OPCODE = (31u << OPCODE_SHIFT | 219u << 1), // X-FORM
453 BRW_OPCODE = (31u << OPCODE_SHIFT | 155u << 1), // X-FORM
454 BRD_OPCODE = (31u << OPCODE_SHIFT | 187u << 1), // X-FORM
455
456 // opcodes only used for floating arithmetic
457 FADD_OPCODE = (63u << OPCODE_SHIFT | 21u << 1),
458 FADDS_OPCODE = (59u << OPCODE_SHIFT | 21u << 1),
459 FCMPU_OPCODE = (63u << OPCODE_SHIFT | 00u << 1),
460 FDIV_OPCODE = (63u << OPCODE_SHIFT | 18u << 1),
461 FDIVS_OPCODE = (59u << OPCODE_SHIFT | 18u << 1),
462 FMR_OPCODE = (63u << OPCODE_SHIFT | 72u << 1),
463 FRIN_OPCODE = (63u << OPCODE_SHIFT | 392u << 1),
464 FRIP_OPCODE = (63u << OPCODE_SHIFT | 456u << 1),
465 FRIM_OPCODE = (63u << OPCODE_SHIFT | 488u << 1),
466 // These are special Power6 opcodes, reused for "lfdepx" and "stfdepx"
467 // on Power7. Do not use.
468 // MFFGPR_OPCODE = (31u << OPCODE_SHIFT | 607u << 1),
469 // MFTGPR_OPCODE = (31u << OPCODE_SHIFT | 735u << 1),
470 CMPB_OPCODE = (31u << OPCODE_SHIFT | 508 << 1),
471 POPCNTB_OPCODE = (31u << OPCODE_SHIFT | 122 << 1),
472 POPCNTW_OPCODE = (31u << OPCODE_SHIFT | 378 << 1),
473 POPCNTD_OPCODE = (31u << OPCODE_SHIFT | 506 << 1),
474 FABS_OPCODE = (63u << OPCODE_SHIFT | 264u << 1),
475 FNABS_OPCODE = (63u << OPCODE_SHIFT | 136u << 1),
476 FMUL_OPCODE = (63u << OPCODE_SHIFT | 25u << 1),
477 FMULS_OPCODE = (59u << OPCODE_SHIFT | 25u << 1),
478 FNEG_OPCODE = (63u << OPCODE_SHIFT | 40u << 1),
479 FSUB_OPCODE = (63u << OPCODE_SHIFT | 20u << 1),
480 FSUBS_OPCODE = (59u << OPCODE_SHIFT | 20u << 1),
481
482 // PPC64-internal FPU conversion opcodes
483 FCFID_OPCODE = (63u << OPCODE_SHIFT | 846u << 1),
484 FCFIDS_OPCODE = (59u << OPCODE_SHIFT | 846u << 1),
485 FCTID_OPCODE = (63u << OPCODE_SHIFT | 814u << 1),
486 FCTIDZ_OPCODE = (63u << OPCODE_SHIFT | 815u << 1),
487 FCTIW_OPCODE = (63u << OPCODE_SHIFT | 14u << 1),
488 FCTIWZ_OPCODE = (63u << OPCODE_SHIFT | 15u << 1),
489 FRSP_OPCODE = (63u << OPCODE_SHIFT | 12u << 1),
490
491 // Fused multiply-accumulate instructions.
492 FMADD_OPCODE = (63u << OPCODE_SHIFT | 29u << 1),
493 FMADDS_OPCODE = (59u << OPCODE_SHIFT | 29u << 1),
494 FMSUB_OPCODE = (63u << OPCODE_SHIFT | 28u << 1),
495 FMSUBS_OPCODE = (59u << OPCODE_SHIFT | 28u << 1),
496 FNMADD_OPCODE = (63u << OPCODE_SHIFT | 31u << 1),
497 FNMADDS_OPCODE = (59u << OPCODE_SHIFT | 31u << 1),
498 FNMSUB_OPCODE = (63u << OPCODE_SHIFT | 30u << 1),
499 FNMSUBS_OPCODE = (59u << OPCODE_SHIFT | 30u << 1),
500
501 LFD_OPCODE = (50u << OPCODE_SHIFT | 00u << 1),
502 LFDU_OPCODE = (51u << OPCODE_SHIFT | 00u << 1),
503 LFDX_OPCODE = (31u << OPCODE_SHIFT | 599u << 1),
504 LFS_OPCODE = (48u << OPCODE_SHIFT | 00u << 1),
505 LFSU_OPCODE = (49u << OPCODE_SHIFT | 00u << 1),
506 LFSX_OPCODE = (31u << OPCODE_SHIFT | 535u << 1),
507
508 STFD_OPCODE = (54u << OPCODE_SHIFT | 00u << 1),
509 STFDU_OPCODE = (55u << OPCODE_SHIFT | 00u << 1),
510 STFDX_OPCODE = (31u << OPCODE_SHIFT | 727u << 1),
511 STFS_OPCODE = (52u << OPCODE_SHIFT | 00u << 1),
512 STFSU_OPCODE = (53u << OPCODE_SHIFT | 00u << 1),
513 STFSX_OPCODE = (31u << OPCODE_SHIFT | 663u << 1),
514
515 FSQRT_OPCODE = (63u << OPCODE_SHIFT | 22u << 1), // A-FORM
516 FSQRTS_OPCODE = (59u << OPCODE_SHIFT | 22u << 1), // A-FORM
517
518 // Vector instruction support for >= Power6
519 // Vector Storage Access
520 LVEBX_OPCODE = (31u << OPCODE_SHIFT | 7u << 1),
521 LVEHX_OPCODE = (31u << OPCODE_SHIFT | 39u << 1),
522 LVEWX_OPCODE = (31u << OPCODE_SHIFT | 71u << 1),
523 LVX_OPCODE = (31u << OPCODE_SHIFT | 103u << 1),
524 LVXL_OPCODE = (31u << OPCODE_SHIFT | 359u << 1),
525 STVEBX_OPCODE = (31u << OPCODE_SHIFT | 135u << 1),
526 STVEHX_OPCODE = (31u << OPCODE_SHIFT | 167u << 1),
527 STVEWX_OPCODE = (31u << OPCODE_SHIFT | 199u << 1),
528 STVX_OPCODE = (31u << OPCODE_SHIFT | 231u << 1),
529 STVXL_OPCODE = (31u << OPCODE_SHIFT | 487u << 1),
530 LVSL_OPCODE = (31u << OPCODE_SHIFT | 6u << 1),
531 LVSR_OPCODE = (31u << OPCODE_SHIFT | 38u << 1),
532
533 // Vector-Scalar (VSX) instruction support.
534 LXV_OPCODE = (61u << OPCODE_SHIFT | 1u ),
535 LXVL_OPCODE = (31u << OPCODE_SHIFT | 269u << 1),
536 STXV_OPCODE = (61u << OPCODE_SHIFT | 5u ),
537 STXVL_OPCODE = (31u << OPCODE_SHIFT | 397u << 1),
538 LXVD2X_OPCODE = (31u << OPCODE_SHIFT | 844u << 1),
539 STXVD2X_OPCODE = (31u << OPCODE_SHIFT | 972u << 1),
540 MTVSRD_OPCODE = (31u << OPCODE_SHIFT | 179u << 1),
541 MTVSRDD_OPCODE = (31u << OPCODE_SHIFT | 435u << 1),
542 MTVSRWZ_OPCODE = (31u << OPCODE_SHIFT | 243u << 1),
543 MFVSRD_OPCODE = (31u << OPCODE_SHIFT | 51u << 1),
544 MTVSRWA_OPCODE = (31u << OPCODE_SHIFT | 211u << 1),
545 MFVSRWZ_OPCODE = (31u << OPCODE_SHIFT | 115u << 1),
546 XXPERMDI_OPCODE= (60u << OPCODE_SHIFT | 10u << 3),
547 XXMRGHW_OPCODE = (60u << OPCODE_SHIFT | 18u << 3),
548 XXMRGLW_OPCODE = (60u << OPCODE_SHIFT | 50u << 3),
549 XXSPLTW_OPCODE = (60u << OPCODE_SHIFT | 164u << 2),
550 XXLAND_OPCODE = (60u << OPCODE_SHIFT | 130u << 3),
551 XXLOR_OPCODE = (60u << OPCODE_SHIFT | 146u << 3),
552 XXLXOR_OPCODE = (60u << OPCODE_SHIFT | 154u << 3),
553 XXLEQV_OPCODE = (60u << OPCODE_SHIFT | 186u << 3),
554 XVDIVSP_OPCODE = (60u << OPCODE_SHIFT | 88u << 3),
555 XXBRD_OPCODE = (60u << OPCODE_SHIFT | 475u << 2 | 23u << 16), // XX2-FORM
556 XXBRW_OPCODE = (60u << OPCODE_SHIFT | 475u << 2 | 15u << 16), // XX2-FORM
557 XXPERM_OPCODE = (60u << OPCODE_SHIFT | 26u << 3),
558 XXSEL_OPCODE = (60u << OPCODE_SHIFT | 3u << 4),
559 XXSPLTIB_OPCODE= (60u << OPCODE_SHIFT | 360u << 1),
560 XVDIVDP_OPCODE = (60u << OPCODE_SHIFT | 120u << 3),
561 XVABSSP_OPCODE = (60u << OPCODE_SHIFT | 409u << 2),
562 XVABSDP_OPCODE = (60u << OPCODE_SHIFT | 473u << 2),
563 XVNEGSP_OPCODE = (60u << OPCODE_SHIFT | 441u << 2),
564 XVNEGDP_OPCODE = (60u << OPCODE_SHIFT | 505u << 2),
565 XVSQRTSP_OPCODE= (60u << OPCODE_SHIFT | 139u << 2),
566 XVSQRTDP_OPCODE= (60u << OPCODE_SHIFT | 203u << 2),
567 XSCVDPSPN_OPCODE=(60u << OPCODE_SHIFT | 267u << 2),
568 XVADDDP_OPCODE = (60u << OPCODE_SHIFT | 96u << 3),
569 XVSUBDP_OPCODE = (60u << OPCODE_SHIFT | 104u << 3),
570 XVMULSP_OPCODE = (60u << OPCODE_SHIFT | 80u << 3),
571 XVMULDP_OPCODE = (60u << OPCODE_SHIFT | 112u << 3),
572 XVMADDASP_OPCODE=(60u << OPCODE_SHIFT | 65u << 3),
573 XVMADDADP_OPCODE=(60u << OPCODE_SHIFT | 97u << 3),
574 XVMSUBASP_OPCODE=(60u << OPCODE_SHIFT | 81u << 3),
575 XVMSUBADP_OPCODE=(60u << OPCODE_SHIFT | 113u << 3),
576 XVNMSUBASP_OPCODE=(60u<< OPCODE_SHIFT | 209u << 3),
577 XVNMSUBADP_OPCODE=(60u<< OPCODE_SHIFT | 241u << 3),
578 XVRDPI_OPCODE = (60u << OPCODE_SHIFT | 201u << 2),
579 XVRDPIC_OPCODE = (60u << OPCODE_SHIFT | 235u << 2),
580 XVRDPIM_OPCODE = (60u << OPCODE_SHIFT | 249u << 2),
581 XVRDPIP_OPCODE = (60u << OPCODE_SHIFT | 233u << 2),
582
583 // Deliver A Random Number (introduced with POWER9)
584 DARN_OPCODE = (31u << OPCODE_SHIFT | 755u << 1),
585
586 // Vector Permute and Formatting
587 VPKPX_OPCODE = (4u << OPCODE_SHIFT | 782u ),
588 VPKSHSS_OPCODE = (4u << OPCODE_SHIFT | 398u ),
589 VPKSWSS_OPCODE = (4u << OPCODE_SHIFT | 462u ),
590 VPKSHUS_OPCODE = (4u << OPCODE_SHIFT | 270u ),
591 VPKSWUS_OPCODE = (4u << OPCODE_SHIFT | 334u ),
592 VPKUHUM_OPCODE = (4u << OPCODE_SHIFT | 14u ),
593 VPKUWUM_OPCODE = (4u << OPCODE_SHIFT | 78u ),
594 VPKUHUS_OPCODE = (4u << OPCODE_SHIFT | 142u ),
595 VPKUWUS_OPCODE = (4u << OPCODE_SHIFT | 206u ),
596 VUPKHPX_OPCODE = (4u << OPCODE_SHIFT | 846u ),
597 VUPKHSB_OPCODE = (4u << OPCODE_SHIFT | 526u ),
598 VUPKHSH_OPCODE = (4u << OPCODE_SHIFT | 590u ),
599 VUPKLPX_OPCODE = (4u << OPCODE_SHIFT | 974u ),
600 VUPKLSB_OPCODE = (4u << OPCODE_SHIFT | 654u ),
601 VUPKLSH_OPCODE = (4u << OPCODE_SHIFT | 718u ),
602
603 VMRGHB_OPCODE = (4u << OPCODE_SHIFT | 12u ),
604 VMRGHW_OPCODE = (4u << OPCODE_SHIFT | 140u ),
605 VMRGHH_OPCODE = (4u << OPCODE_SHIFT | 76u ),
606 VMRGLB_OPCODE = (4u << OPCODE_SHIFT | 268u ),
607 VMRGLW_OPCODE = (4u << OPCODE_SHIFT | 396u ),
608 VMRGLH_OPCODE = (4u << OPCODE_SHIFT | 332u ),
609
610 VSPLT_OPCODE = (4u << OPCODE_SHIFT | 524u ),
611 VSPLTH_OPCODE = (4u << OPCODE_SHIFT | 588u ),
612 VSPLTW_OPCODE = (4u << OPCODE_SHIFT | 652u ),
613 VSPLTISB_OPCODE= (4u << OPCODE_SHIFT | 780u ),
614 VSPLTISH_OPCODE= (4u << OPCODE_SHIFT | 844u ),
615 VSPLTISW_OPCODE= (4u << OPCODE_SHIFT | 908u ),
616
617 VPEXTD_OPCODE = (4u << OPCODE_SHIFT | 1421u ),
618 VPERM_OPCODE = (4u << OPCODE_SHIFT | 43u ),
619 VSEL_OPCODE = (4u << OPCODE_SHIFT | 42u ),
620
621 VSL_OPCODE = (4u << OPCODE_SHIFT | 452u ),
622 VSLDOI_OPCODE = (4u << OPCODE_SHIFT | 44u ),
623 VSLO_OPCODE = (4u << OPCODE_SHIFT | 1036u ),
624 VSR_OPCODE = (4u << OPCODE_SHIFT | 708u ),
625 VSRO_OPCODE = (4u << OPCODE_SHIFT | 1100u ),
626
627 // Vector Integer
628 VADDCUW_OPCODE = (4u << OPCODE_SHIFT | 384u ),
629 VADDSHS_OPCODE = (4u << OPCODE_SHIFT | 832u ),
630 VADDSBS_OPCODE = (4u << OPCODE_SHIFT | 768u ),
631 VADDSWS_OPCODE = (4u << OPCODE_SHIFT | 896u ),
632 VADDUBM_OPCODE = (4u << OPCODE_SHIFT | 0u ),
633 VADDUWM_OPCODE = (4u << OPCODE_SHIFT | 128u ),
634 VADDUHM_OPCODE = (4u << OPCODE_SHIFT | 64u ),
635 VADDUDM_OPCODE = (4u << OPCODE_SHIFT | 192u ),
636 VADDUBS_OPCODE = (4u << OPCODE_SHIFT | 512u ),
637 VADDUWS_OPCODE = (4u << OPCODE_SHIFT | 640u ),
638 VADDUHS_OPCODE = (4u << OPCODE_SHIFT | 576u ),
639 VADDFP_OPCODE = (4u << OPCODE_SHIFT | 10u ),
640 VSUBCUW_OPCODE = (4u << OPCODE_SHIFT | 1408u ),
641 VSUBSHS_OPCODE = (4u << OPCODE_SHIFT | 1856u ),
642 VSUBSBS_OPCODE = (4u << OPCODE_SHIFT | 1792u ),
643 VSUBSWS_OPCODE = (4u << OPCODE_SHIFT | 1920u ),
644 VSUBUBM_OPCODE = (4u << OPCODE_SHIFT | 1024u ),
645 VSUBUWM_OPCODE = (4u << OPCODE_SHIFT | 1152u ),
646 VSUBUHM_OPCODE = (4u << OPCODE_SHIFT | 1088u ),
647 VSUBUDM_OPCODE = (4u << OPCODE_SHIFT | 1216u ),
648 VSUBUBS_OPCODE = (4u << OPCODE_SHIFT | 1536u ),
649 VSUBUWS_OPCODE = (4u << OPCODE_SHIFT | 1664u ),
650 VSUBUHS_OPCODE = (4u << OPCODE_SHIFT | 1600u ),
651 VSUBFP_OPCODE = (4u << OPCODE_SHIFT | 74u ),
652
653 VMULESB_OPCODE = (4u << OPCODE_SHIFT | 776u ),
654 VMULEUB_OPCODE = (4u << OPCODE_SHIFT | 520u ),
655 VMULESH_OPCODE = (4u << OPCODE_SHIFT | 840u ),
656 VMULEUH_OPCODE = (4u << OPCODE_SHIFT | 584u ),
657 VMULOSB_OPCODE = (4u << OPCODE_SHIFT | 264u ),
658 VMULOUB_OPCODE = (4u << OPCODE_SHIFT | 8u ),
659 VMULOSH_OPCODE = (4u << OPCODE_SHIFT | 328u ),
660 VMULOSW_OPCODE = (4u << OPCODE_SHIFT | 392u ),
661 VMULOUH_OPCODE = (4u << OPCODE_SHIFT | 72u ),
662 VMULUWM_OPCODE = (4u << OPCODE_SHIFT | 137u ),
663 VMHADDSHS_OPCODE=(4u << OPCODE_SHIFT | 32u ),
664 VMHRADDSHS_OPCODE=(4u << OPCODE_SHIFT | 33u ),
665 VMLADDUHM_OPCODE=(4u << OPCODE_SHIFT | 34u ),
666 VMSUBUHM_OPCODE= (4u << OPCODE_SHIFT | 36u ),
667 VMSUMMBM_OPCODE= (4u << OPCODE_SHIFT | 37u ),
668 VMSUMSHM_OPCODE= (4u << OPCODE_SHIFT | 40u ),
669 VMSUMSHS_OPCODE= (4u << OPCODE_SHIFT | 41u ),
670 VMSUMUHM_OPCODE= (4u << OPCODE_SHIFT | 38u ),
671 VMSUMUHS_OPCODE= (4u << OPCODE_SHIFT | 39u ),
672 VMADDFP_OPCODE = (4u << OPCODE_SHIFT | 46u ),
673
674 VSUMSWS_OPCODE = (4u << OPCODE_SHIFT | 1928u ),
675 VSUM2SWS_OPCODE= (4u << OPCODE_SHIFT | 1672u ),
676 VSUM4SBS_OPCODE= (4u << OPCODE_SHIFT | 1800u ),
677 VSUM4UBS_OPCODE= (4u << OPCODE_SHIFT | 1544u ),
678 VSUM4SHS_OPCODE= (4u << OPCODE_SHIFT | 1608u ),
679
680 VAVGSB_OPCODE = (4u << OPCODE_SHIFT | 1282u ),
681 VAVGSW_OPCODE = (4u << OPCODE_SHIFT | 1410u ),
682 VAVGSH_OPCODE = (4u << OPCODE_SHIFT | 1346u ),
683 VAVGUB_OPCODE = (4u << OPCODE_SHIFT | 1026u ),
684 VAVGUW_OPCODE = (4u << OPCODE_SHIFT | 1154u ),
685 VAVGUH_OPCODE = (4u << OPCODE_SHIFT | 1090u ),
686
687 VMAXSB_OPCODE = (4u << OPCODE_SHIFT | 258u ),
688 VMAXSW_OPCODE = (4u << OPCODE_SHIFT | 386u ),
689 VMAXSH_OPCODE = (4u << OPCODE_SHIFT | 322u ),
690 VMAXUB_OPCODE = (4u << OPCODE_SHIFT | 2u ),
691 VMAXUW_OPCODE = (4u << OPCODE_SHIFT | 130u ),
692 VMAXUH_OPCODE = (4u << OPCODE_SHIFT | 66u ),
693 VMINSB_OPCODE = (4u << OPCODE_SHIFT | 770u ),
694 VMINSW_OPCODE = (4u << OPCODE_SHIFT | 898u ),
695 VMINSH_OPCODE = (4u << OPCODE_SHIFT | 834u ),
696 VMINUB_OPCODE = (4u << OPCODE_SHIFT | 514u ),
697 VMINUW_OPCODE = (4u << OPCODE_SHIFT | 642u ),
698 VMINUH_OPCODE = (4u << OPCODE_SHIFT | 578u ),
699
700 VCMPEQUB_OPCODE= (4u << OPCODE_SHIFT | 6u ),
701 VCMPEQUH_OPCODE= (4u << OPCODE_SHIFT | 70u ),
702 VCMPEQUW_OPCODE= (4u << OPCODE_SHIFT | 134u ),
703 VCMPGTSH_OPCODE= (4u << OPCODE_SHIFT | 838u ),
704 VCMPGTSB_OPCODE= (4u << OPCODE_SHIFT | 774u ),
705 VCMPGTSW_OPCODE= (4u << OPCODE_SHIFT | 902u ),
706 VCMPGTUB_OPCODE= (4u << OPCODE_SHIFT | 518u ),
707 VCMPGTUH_OPCODE= (4u << OPCODE_SHIFT | 582u ),
708 VCMPGTUW_OPCODE= (4u << OPCODE_SHIFT | 646u ),
709
710 VAND_OPCODE = (4u << OPCODE_SHIFT | 1028u ),
711 VANDC_OPCODE = (4u << OPCODE_SHIFT | 1092u ),
712 VNOR_OPCODE = (4u << OPCODE_SHIFT | 1284u ),
713 VOR_OPCODE = (4u << OPCODE_SHIFT | 1156u ),
714 VXOR_OPCODE = (4u << OPCODE_SHIFT | 1220u ),
715 VRLD_OPCODE = (4u << OPCODE_SHIFT | 196u ),
716 VRLB_OPCODE = (4u << OPCODE_SHIFT | 4u ),
717 VRLW_OPCODE = (4u << OPCODE_SHIFT | 132u ),
718 VRLH_OPCODE = (4u << OPCODE_SHIFT | 68u ),
719 VSLB_OPCODE = (4u << OPCODE_SHIFT | 260u ),
720 VSKW_OPCODE = (4u << OPCODE_SHIFT | 388u ),
721 VSLH_OPCODE = (4u << OPCODE_SHIFT | 324u ),
722 VSRB_OPCODE = (4u << OPCODE_SHIFT | 516u ),
723 VSRW_OPCODE = (4u << OPCODE_SHIFT | 644u ),
724 VSRH_OPCODE = (4u << OPCODE_SHIFT | 580u ),
725 VSRAB_OPCODE = (4u << OPCODE_SHIFT | 772u ),
726 VSRAW_OPCODE = (4u << OPCODE_SHIFT | 900u ),
727 VSRAH_OPCODE = (4u << OPCODE_SHIFT | 836u ),
728 VPOPCNTB_OPCODE= (4u << OPCODE_SHIFT | 1795u ),
729 VPOPCNTH_OPCODE= (4u << OPCODE_SHIFT | 1859u ),
730 VPOPCNTW_OPCODE= (4u << OPCODE_SHIFT | 1923u ),
731 VPOPCNTD_OPCODE= (4u << OPCODE_SHIFT | 1987u ),
732
733 // Vector Floating-Point
734 // not implemented yet
735
736 // Vector Status and Control
737 MTVSCR_OPCODE = (4u << OPCODE_SHIFT | 1604u ),
738 MFVSCR_OPCODE = (4u << OPCODE_SHIFT | 1540u ),
739
740 // AES (introduced with Power 8)
741 VCIPHER_OPCODE = (4u << OPCODE_SHIFT | 1288u),
742 VCIPHERLAST_OPCODE = (4u << OPCODE_SHIFT | 1289u),
743 VNCIPHER_OPCODE = (4u << OPCODE_SHIFT | 1352u),
744 VNCIPHERLAST_OPCODE = (4u << OPCODE_SHIFT | 1353u),
745 VSBOX_OPCODE = (4u << OPCODE_SHIFT | 1480u),
746
747 // SHA (introduced with Power 8)
748 VSHASIGMAD_OPCODE = (4u << OPCODE_SHIFT | 1730u),
749 VSHASIGMAW_OPCODE = (4u << OPCODE_SHIFT | 1666u),
750
751 // Vector Binary Polynomial Multiplication (introduced with Power 8)
752 VPMSUMB_OPCODE = (4u << OPCODE_SHIFT | 1032u),
753 VPMSUMD_OPCODE = (4u << OPCODE_SHIFT | 1224u),
754 VPMSUMH_OPCODE = (4u << OPCODE_SHIFT | 1096u),
755 VPMSUMW_OPCODE = (4u << OPCODE_SHIFT | 1160u),
756
757 // Vector Permute and Xor (introduced with Power 8)
758 VPERMXOR_OPCODE = (4u << OPCODE_SHIFT | 45u),
759
760 // Icache and dcache related instructions
761 DCBA_OPCODE = (31u << OPCODE_SHIFT | 758u << 1),
762 DCBZ_OPCODE = (31u << OPCODE_SHIFT | 1014u << 1),
763 DCBST_OPCODE = (31u << OPCODE_SHIFT | 54u << 1),
764 DCBF_OPCODE = (31u << OPCODE_SHIFT | 86u << 1),
765
766 DCBT_OPCODE = (31u << OPCODE_SHIFT | 278u << 1),
767 DCBTST_OPCODE = (31u << OPCODE_SHIFT | 246u << 1),
768 ICBI_OPCODE = (31u << OPCODE_SHIFT | 982u << 1),
769
770 // Instruction synchronization
771 ISYNC_OPCODE = (19u << OPCODE_SHIFT | 150u << 1),
772 // Memory barriers
773 SYNC_OPCODE = (31u << OPCODE_SHIFT | 598u << 1),
774 EIEIO_OPCODE = (31u << OPCODE_SHIFT | 854u << 1),
775
776 // Wait instructions for polling.
777 WAIT_OPCODE = (31u << OPCODE_SHIFT | 62u << 1),
778
779 // Trap instructions
780 TDI_OPCODE = (2u << OPCODE_SHIFT),
781 TWI_OPCODE = (3u << OPCODE_SHIFT),
782 TD_OPCODE = (31u << OPCODE_SHIFT | 68u << 1),
783 TW_OPCODE = (31u << OPCODE_SHIFT | 4u << 1),
784
785 // Atomics.
786 LBARX_OPCODE = (31u << OPCODE_SHIFT | 52u << 1),
787 LHARX_OPCODE = (31u << OPCODE_SHIFT | 116u << 1),
788 LWARX_OPCODE = (31u << OPCODE_SHIFT | 20u << 1),
789 LDARX_OPCODE = (31u << OPCODE_SHIFT | 84u << 1),
790 LQARX_OPCODE = (31u << OPCODE_SHIFT | 276u << 1),
791 STBCX_OPCODE = (31u << OPCODE_SHIFT | 694u << 1),
792 STHCX_OPCODE = (31u << OPCODE_SHIFT | 726u << 1),
793 STWCX_OPCODE = (31u << OPCODE_SHIFT | 150u << 1),
794 STDCX_OPCODE = (31u << OPCODE_SHIFT | 214u << 1),
795 STQCX_OPCODE = (31u << OPCODE_SHIFT | 182u << 1)
796
797 };
798
799 enum opcdeos_mask {
800 // Mask for prefix primary opcode field
801 PREFIX_OPCODE_MASK = (63u << OPCODE_SHIFT),
802 // Mask for prefix opcode and type fields
803 PREFIX_OPCODE_TYPE_MASK = (63u << OPCODE_SHIFT) | (3u << PRE_TYPE_SHIFT),
804 // Masks for type 00/10 and type 01/11, including opcode, type, and st fieds
805 PREFIX_OPCODE_TYPEx0_MASK = PREFIX_OPCODE_TYPE_MASK | ( 1u << PRE_ST1_SHIFT),
806 PREFIX_OPCODE_TYPEx1_MASK = PREFIX_OPCODE_TYPE_MASK | (15u << PRE_ST4_SHIFT),
807
808 // Masks for each instructions
809 PADDI_PREFIX_OPCODE_MASK = PREFIX_OPCODE_TYPEx0_MASK,
810 PADDI_SUFFIX_OPCODE_MASK = ADDI_OPCODE_MASK,
811 };
812
813 enum opcdeos {
814 PREFIX_PRIMARY_OPCODE = (1u << OPCODE_SHIFT),
815
816 // Prefixed addi/li
817 PADDI_PREFIX_OPCODE = PREFIX_PRIMARY_OPCODE | (2u << PRE_TYPE_SHIFT),
818 PADDI_SUFFIX_OPCODE = ADDI_OPCODE,
819
820 // xxpermx
821 XXPERMX_PREFIX_OPCODE = PREFIX_PRIMARY_OPCODE | (1u << PRE_TYPE_SHIFT),
822 XXPERMX_SUFFIX_OPCODE = (34u << OPCODE_SHIFT),
823 };
824
825 // Trap instructions TO bits
826 enum trap_to_bits {
827 // single bits
828 traptoLessThanSigned = 1 << 4, // 0, left end
829 traptoGreaterThanSigned = 1 << 3,
830 traptoEqual = 1 << 2,
831 traptoLessThanUnsigned = 1 << 1,
832 traptoGreaterThanUnsigned = 1 << 0, // 4, right end
833
834 // compound ones
835 traptoUnconditional = (traptoLessThanSigned |
836 traptoGreaterThanSigned |
837 traptoEqual |
838 traptoLessThanUnsigned |
839 traptoGreaterThanUnsigned)
840 };
841
842 // Branch hints BH field
843 enum branch_hint_bh {
844 // bclr cases:
845 bhintbhBCLRisReturn = 0,
846 bhintbhBCLRisNotReturnButSame = 1,
847 bhintbhBCLRisNotPredictable = 3,
848
849 // bcctr cases:
850 bhintbhBCCTRisNotReturnButSame = 0,
851 bhintbhBCCTRisNotPredictable = 3
852 };
853
854 // Branch prediction hints AT field
855 enum branch_hint_at {
856 bhintatNoHint = 0, // at=00
857 bhintatIsNotTaken = 2, // at=10
858 bhintatIsTaken = 3 // at=11
859 };
860
861 // Branch prediction hints
862 enum branch_hint_concept {
863 // Use the same encoding as branch_hint_at to simply code.
864 bhintNoHint = bhintatNoHint,
865 bhintIsNotTaken = bhintatIsNotTaken,
866 bhintIsTaken = bhintatIsTaken
867 };
868
869 // Used in BO field of branch instruction.
870 enum branch_condition {
871 bcondCRbiIs0 = 4, // bo=001at
872 bcondCRbiIs1 = 12, // bo=011at
873 bcondAlways = 20 // bo=10100
874 };
875
876 // Branch condition with combined prediction hints.
877 enum branch_condition_with_hint {
878 bcondCRbiIs0_bhintNoHint = bcondCRbiIs0 | bhintatNoHint,
879 bcondCRbiIs0_bhintIsNotTaken = bcondCRbiIs0 | bhintatIsNotTaken,
880 bcondCRbiIs0_bhintIsTaken = bcondCRbiIs0 | bhintatIsTaken,
881 bcondCRbiIs1_bhintNoHint = bcondCRbiIs1 | bhintatNoHint,
882 bcondCRbiIs1_bhintIsNotTaken = bcondCRbiIs1 | bhintatIsNotTaken,
883 bcondCRbiIs1_bhintIsTaken = bcondCRbiIs1 | bhintatIsTaken,
884 };
885
886 // Elemental Memory Barriers (>=Power 8)
887 enum Elemental_Membar_mask_bits {
888 StoreStore = 1 << 0,
889 StoreLoad = 1 << 1,
890 LoadStore = 1 << 2,
891 LoadLoad = 1 << 3
892 };
893
894 // Branch prediction hints.
895 inline static int add_bhint_to_boint(const int bhint, const int boint) {
896 switch (boint) {
897 case bcondCRbiIs0:
898 case bcondCRbiIs1:
899 // branch_hint and branch_hint_at have same encodings
900 assert( (int)bhintNoHint == (int)bhintatNoHint
901 && (int)bhintIsNotTaken == (int)bhintatIsNotTaken
902 && (int)bhintIsTaken == (int)bhintatIsTaken,
903 "wrong encodings");
904 assert((bhint & 0x03) == bhint, "wrong encodings");
905 return (boint & ~0x03) | bhint;
906 case bcondAlways:
907 // no branch_hint
908 return boint;
909 default:
910 ShouldNotReachHere();
911 return 0;
912 }
913 }
914
915 // Extract bcond from boint.
916 inline static int inv_boint_bcond(const int boint) {
917 int r_bcond = boint & ~0x03;
918 assert(r_bcond == bcondCRbiIs0 ||
919 r_bcond == bcondCRbiIs1 ||
920 r_bcond == bcondAlways,
921 "bad branch condition");
922 return r_bcond;
923 }
924
925 // Extract bhint from boint.
926 inline static int inv_boint_bhint(const int boint) {
927 int r_bhint = boint & 0x03;
928 assert(r_bhint == bhintatNoHint ||
929 r_bhint == bhintatIsNotTaken ||
930 r_bhint == bhintatIsTaken,
931 "bad branch hint");
932 return r_bhint;
933 }
934
935 // Calculate opposite of given bcond.
936 inline static int opposite_bcond(const int bcond) {
937 switch (bcond) {
938 case bcondCRbiIs0:
939 return bcondCRbiIs1;
940 case bcondCRbiIs1:
941 return bcondCRbiIs0;
942 default:
943 ShouldNotReachHere();
944 return 0;
945 }
946 }
947
948 // Calculate opposite of given bhint.
949 inline static int opposite_bhint(const int bhint) {
950 switch (bhint) {
951 case bhintatNoHint:
952 return bhintatNoHint;
953 case bhintatIsNotTaken:
954 return bhintatIsTaken;
955 case bhintatIsTaken:
956 return bhintatIsNotTaken;
957 default:
958 ShouldNotReachHere();
959 return 0;
960 }
961 }
962
963 // PPC branch instructions
964 enum ppcops {
965 b_op = 18,
966 bc_op = 16,
967 bcr_op = 19
968 };
969
970 enum Condition {
971 negative = 0,
972 less = 0,
973 positive = 1,
974 greater = 1,
975 zero = 2,
976 equal = 2,
977 summary_overflow = 3,
978 };
979
980 public:
981 // Helper functions for groups of instructions
982
983 enum Predict { pt = 1, pn = 0 }; // pt = predict taken
984
985 //---< calculate length of instruction >---
986 // With PPC64 being a RISC architecture, this always is BytesPerInstWord
987 // instruction must start at passed address
988 static unsigned int instr_len(unsigned char *instr) { return BytesPerInstWord; }
989
990 //---< longest instructions >---
991 static unsigned int instr_maxlen() { return BytesPerInstWord; }
992
993 // Test if x is within signed immediate range for nbits.
994 static bool is_simm(int x, unsigned int nbits) {
995 assert(0 < nbits && nbits < 32, "out of bounds");
996 const int min = -(((int)1) << (nbits-1));
997 const int maxplus1 = (((int)1) << (nbits-1));
998 return min <= x && x < maxplus1;
999 }
1000
1001 static bool is_simm(jlong x, unsigned int nbits) {
1002 assert(0 < nbits && nbits < 64, "out of bounds");
1003 const jlong min = -(((jlong)1) << (nbits-1));
1004 const jlong maxplus1 = (((jlong)1) << (nbits-1));
1005 return min <= x && x < maxplus1;
1006 }
1007
1008 // Test if x is within unsigned immediate range for nbits.
1009 static bool is_uimm(int x, unsigned int nbits) {
1010 assert(0 < nbits && nbits < 32, "out of bounds");
1011 const unsigned int maxplus1 = (((unsigned int)1) << nbits);
1012 return (unsigned int)x < maxplus1;
1013 }
1014
1015 static bool is_uimm(jlong x, unsigned int nbits) {
1016 assert(0 < nbits && nbits < 64, "out of bounds");
1017 const julong maxplus1 = (((julong)1) << nbits);
1018 return (julong)x < maxplus1;
1019 }
1020
1021 protected:
1022 // helpers
1023
1024 // X is supposed to fit in a field "nbits" wide
1025 // and be sign-extended. Check the range.
1026 static void assert_signed_range(intptr_t x, int nbits) {
1027 assert(nbits == 32 || (-(1 << (nbits-1)) <= x && x < (1 << (nbits-1))),
1028 "value out of range");
1029 }
1030
1031 static void assert_signed_word_disp_range(intptr_t x, int nbits) {
1032 assert((x & 3) == 0, "not word aligned");
1033 assert_signed_range(x, nbits + 2);
1034 }
1035
1036 static void assert_unsigned_const(int x, int nbits) {
1037 assert(juint(x) < juint(1 << nbits), "unsigned constant out of range");
1038 }
1039
1040 static int fmask(juint hi_bit, juint lo_bit) {
1041 assert(hi_bit >= lo_bit && hi_bit < 32, "bad bits");
1042 return (1 << ( hi_bit-lo_bit + 1 )) - 1;
1043 }
1044
1045 // inverse of u_field
1046 static int inv_u_field(int x, int hi_bit, int lo_bit) {
1047 juint r = juint(x) >> lo_bit;
1048 r &= fmask(hi_bit, lo_bit);
1049 return int(r);
1050 }
1051
1052 // signed version: extract from field and sign-extend
1053 static int inv_s_field_ppc(int x, int hi_bit, int lo_bit) {
1054 x = x << (31-hi_bit);
1055 x = x >> (31-hi_bit+lo_bit);
1056 return x;
1057 }
1058
1059 static int u_field(int x, int hi_bit, int lo_bit) {
1060 assert((x & ~fmask(hi_bit, lo_bit)) == 0, "value out of range");
1061 int r = x << lo_bit;
1062 assert(inv_u_field(r, hi_bit, lo_bit) == x, "just checking");
1063 return r;
1064 }
1065
1066 // Same as u_field for signed values
1067 static int s_field(int x, int hi_bit, int lo_bit) {
1068 int nbits = hi_bit - lo_bit + 1;
1069 assert(nbits == 32 || (-(1 << (nbits-1)) <= x && x < (1 << (nbits-1))),
1070 "value out of range");
1071 x &= fmask(hi_bit, lo_bit);
1072 int r = x << lo_bit;
1073 return r;
1074 }
1075
1076 // inv_op for ppc instructions
1077 static int inv_op_ppc(int x) { return inv_u_field(x, 31, 26); }
1078
1079 // Determine target address from li, bd field of branch instruction.
1080 static intptr_t inv_li_field(int x) {
1081 intptr_t r = inv_s_field_ppc(x, 25, 2);
1082 r = (r << 2);
1083 return r;
1084 }
1085 static intptr_t inv_bd_field(int x, intptr_t pos) {
1086 intptr_t r = inv_s_field_ppc(x, 15, 2);
1087 r = (r << 2) + pos;
1088 return r;
1089 }
1090
1091 #define inv_opp_u_field(x, hi_bit, lo_bit) inv_u_field(x, 31-(lo_bit), 31-(hi_bit))
1092 #define inv_opp_s_field(x, hi_bit, lo_bit) inv_s_field_ppc(x, 31-(lo_bit), 31-(hi_bit))
1093 // Extract instruction fields from instruction words.
1094 public:
1095 static int inv_ra_field(int x) { return inv_opp_u_field(x, 15, 11); }
1096 static int inv_rb_field(int x) { return inv_opp_u_field(x, 20, 16); }
1097 static int inv_rt_field(int x) { return inv_opp_u_field(x, 10, 6); }
1098 static int inv_rta_field(int x) { return inv_opp_u_field(x, 15, 11); }
1099 static int inv_rs_field(int x) { return inv_opp_u_field(x, 10, 6); }
1100 // Ds uses opp_s_field(x, 31, 16), but lowest 2 bits must be 0.
1101 // Inv_ds_field uses range (x, 29, 16) but shifts by 2 to ensure that lowest bits are 0.
1102 static int inv_ds_field(int x) { return inv_opp_s_field(x, 29, 16) << 2; }
1103 static int inv_d1_field(int x) { return inv_opp_s_field(x, 31, 16); }
1104 static int inv_si_field(int x) { return inv_opp_s_field(x, 31, 16); }
1105 static int inv_to_field(int x) { return inv_opp_u_field(x, 10, 6); }
1106 static int inv_lk_field(int x) { return inv_opp_u_field(x, 31, 31); }
1107 static int inv_bo_field(int x) { return inv_opp_u_field(x, 10, 6); }
1108 static int inv_bi_field(int x) { return inv_opp_u_field(x, 15, 11); }
1109
1110 // For extended opcodes (prefixed instructions) introduced with Power 10
1111 static long inv_r_eo( int x) { return inv_opp_u_field(x, 11, 11); }
1112 static long inv_type( int x) { return inv_opp_u_field(x, 7, 6); }
1113 static long inv_st_x0( int x) { return inv_opp_u_field(x, 8, 8); }
1114 static long inv_st_x1( int x) { return inv_opp_u_field(x, 11, 8); }
1115
1116 // - 8LS:D/MLS:D Formats
1117 static long inv_d0_eo( long x) { return inv_opp_u_field(x, 31, 14); }
1118
1119 // - 8RR:XX4/8RR:D Formats
1120 static long inv_imm0_eo(int x) { return inv_opp_u_field(x, 31, 16); }
1121 static long inv_uimm_eo(int x) { return inv_opp_u_field(x, 31, 29); }
1122 static long inv_imm_eo( int x) { return inv_opp_u_field(x, 31, 24); }
1123
1124 #define opp_u_field(x, hi_bit, lo_bit) u_field(x, 31-(lo_bit), 31-(hi_bit))
1125 #define opp_s_field(x, hi_bit, lo_bit) s_field(x, 31-(lo_bit), 31-(hi_bit))
1126
1127 // instruction fields
1128 static int aa( int x) { return opp_u_field(x, 30, 30); }
1129 static int ba( int x) { return opp_u_field(x, 15, 11); }
1130 static int bb( int x) { return opp_u_field(x, 20, 16); }
1131 static int bc( int x) { return opp_u_field(x, 25, 21); }
1132 static int bd( int x) { return opp_s_field(x, 29, 16); }
1133 static int bf( ConditionRegister cr) { return bf(cr->encoding()); }
1134 static int bf( int x) { return opp_u_field(x, 8, 6); }
1135 static int bfa(ConditionRegister cr) { return bfa(cr->encoding()); }
1136 static int bfa( int x) { return opp_u_field(x, 13, 11); }
1137 static int bh( int x) { return opp_u_field(x, 20, 19); }
1138 static int bi( int x) { return opp_u_field(x, 15, 11); }
1139 static int bi0(ConditionRegister cr, Condition c) { return (cr->encoding() << 2) | c; }
1140 static int bo( int x) { return opp_u_field(x, 10, 6); }
1141 static int bt( int x) { return opp_u_field(x, 10, 6); }
1142 static int d1( int x) { return opp_s_field(x, 31, 16); }
1143 static int ds( int x) { assert((x & 0x3) == 0, "unaligned offset"); return opp_s_field(x, 31, 16); }
1144 static int eh( int x) { return opp_u_field(x, 31, 31); }
1145 static int flm( int x) { return opp_u_field(x, 14, 7); }
1146 static int fra( FloatRegister r) { return fra(r->encoding());}
1147 static int frb( FloatRegister r) { return frb(r->encoding());}
1148 static int frc( FloatRegister r) { return frc(r->encoding());}
1149 static int frs( FloatRegister r) { return frs(r->encoding());}
1150 static int frt( FloatRegister r) { return frt(r->encoding());}
1151 static int fra( int x) { return opp_u_field(x, 15, 11); }
1152 static int frb( int x) { return opp_u_field(x, 20, 16); }
1153 static int frc( int x) { return opp_u_field(x, 25, 21); }
1154 static int frs( int x) { return opp_u_field(x, 10, 6); }
1155 static int frt( int x) { return opp_u_field(x, 10, 6); }
1156 static int fxm( int x) { return opp_u_field(x, 19, 12); }
1157 static int imm8( int x) { return opp_u_field(uimm(x, 8), 20, 13); }
1158 static int l10( int x) { assert(x == 0 || x == 1, "must be 0 or 1"); return opp_u_field(x, 10, 10); }
1159 static int l14( int x) { return opp_u_field(x, 15, 14); }
1160 static int l15( int x) { return opp_u_field(x, 15, 15); }
1161 static int l910( int x) { return opp_u_field(x, 10, 9); }
1162 static int e1215( int x) { return opp_u_field(x, 15, 12); }
1163 static int lev( int x) { return opp_u_field(x, 26, 20); }
1164 static int li( int x) { return opp_s_field(x, 29, 6); }
1165 static int lk( int x) { return opp_u_field(x, 31, 31); }
1166 static int mb2125( int x) { return opp_u_field(x, 25, 21); }
1167 static int me2630( int x) { return opp_u_field(x, 30, 26); }
1168 static int mb2126( int x) { return opp_u_field(((x & 0x1f) << 1) | ((x & 0x20) >> 5), 26, 21); }
1169 static int me2126( int x) { return mb2126(x); }
1170 static int nb( int x) { return opp_u_field(x, 20, 16); }
1171 //static int opcd( int x) { return opp_u_field(x, 5, 0); } // is contained in our opcodes
1172 static int oe( int x) { return opp_u_field(x, 21, 21); }
1173 static int ra( Register r) { return ra(r->encoding()); }
1174 static int ra( int x) { return opp_u_field(x, 15, 11); }
1175 static int rb( Register r) { return rb(r->encoding()); }
1176 static int rb( int x) { return opp_u_field(x, 20, 16); }
1177 static int rc( int x) { return opp_u_field(x, 31, 31); }
1178 static int rs( Register r) { return rs(r->encoding()); }
1179 static int rs( int x) { return opp_u_field(x, 10, 6); }
1180 // we don't want to use R0 in memory accesses, because it has value `0' then
1181 static int ra0mem( Register r) { assert(r != R0, "cannot use register R0 in memory access"); return ra(r); }
1182 static int ra0mem( int x) { assert(x != 0, "cannot use register 0 in memory access"); return ra(x); }
1183
1184 // register r is target
1185 static int rt( Register r) { return rs(r); }
1186 static int rt( int x) { return rs(x); }
1187 static int rta( Register r) { return ra(r); }
1188 static int rta0mem( Register r) { rta(r); return ra0mem(r); }
1189
1190 static int sh1620( int x) { return opp_u_field(x, 20, 16); }
1191 static int sh30( int x) { return opp_u_field(x, 30, 30); }
1192 static int sh162030( int x) { return sh1620(x & 0x1f) | sh30((x & 0x20) >> 5); }
1193 static int si( int x) { return opp_s_field(x, 31, 16); }
1194 static int spr( int x) { return opp_u_field(x, 20, 11); }
1195 static int sr( int x) { return opp_u_field(x, 15, 12); }
1196 static int tbr( int x) { return opp_u_field(x, 20, 11); }
1197 static int th( int x) { return opp_u_field(x, 10, 7); }
1198 static int thct( int x) { assert((x&8) == 0, "must be valid cache specification"); return th(x); }
1199 static int thds( int x) { assert((x&8) == 8, "must be valid stream specification"); return th(x); }
1200 static int to( int x) { return opp_u_field(x, 10, 6); }
1201 static int u( int x) { return opp_u_field(x, 19, 16); }
1202 static int ui( int x) { return opp_u_field(x, 31, 16); }
1203
1204 // Support vector instructions for >= Power6.
1205 static int vra( int x) { return opp_u_field(x, 15, 11); }
1206 static int vrb( int x) { return opp_u_field(x, 20, 16); }
1207 static int vrc( int x) { return opp_u_field(x, 25, 21); }
1208 static int vrs( int x) { return opp_u_field(x, 10, 6); }
1209 static int vrt( int x) { return opp_u_field(x, 10, 6); }
1210
1211 static int vra( VectorRegister r) { return vra(r->encoding());}
1212 static int vrb( VectorRegister r) { return vrb(r->encoding());}
1213 static int vrc( VectorRegister r) { return vrc(r->encoding());}
1214 static int vrs( VectorRegister r) { return vrs(r->encoding());}
1215 static int vrt( VectorRegister r) { return vrt(r->encoding());}
1216
1217 // Only used on SHA sigma instructions (VX-form)
1218 static int vst( int x) { return opp_u_field(x, 16, 16); }
1219 static int vsix( int x) { return opp_u_field(x, 20, 17); }
1220
1221 // Support Vector-Scalar (VSX) instructions.
1222 static int vsra( int x) { return opp_u_field(x & 0x1F, 15, 11) | opp_u_field((x & 0x20) >> 5, 29, 29); }
1223 static int vsrb( int x) { return opp_u_field(x & 0x1F, 20, 16) | opp_u_field((x & 0x20) >> 5, 30, 30); }
1224 static int vsrc( int x) { return opp_u_field(x & 0x1F, 25, 21) | opp_u_field((x & 0x20) >> 5, 28, 28); }
1225 static int vsrs( int x) { return opp_u_field(x & 0x1F, 10, 6) | opp_u_field((x & 0x20) >> 5, 31, 31); }
1226 static int vsrt( int x) { return vsrs(x); }
1227 static int vsdm( int x) { return opp_u_field(x, 23, 22); }
1228 static int vsrs_dq( int x) { return opp_u_field(x & 0x1F, 10, 6) | opp_u_field((x & 0x20) >> 5, 28, 28); }
1229 static int vsrt_dq( int x) { return vsrs_dq(x); }
1230
1231 static int vsra( VectorSRegister r) { return vsra(r->encoding());}
1232 static int vsrb( VectorSRegister r) { return vsrb(r->encoding());}
1233 static int vsrc( VectorSRegister r) { return vsrc(r->encoding());}
1234 static int vsrs( VectorSRegister r) { return vsrs(r->encoding());}
1235 static int vsrt( VectorSRegister r) { return vsrt(r->encoding());}
1236 static int vsrs_dq(VectorSRegister r) { return vsrs_dq(r->encoding());}
1237 static int vsrt_dq(VectorSRegister r) { return vsrt_dq(r->encoding());}
1238
1239 static int vsplt_uim( int x) { return opp_u_field(x, 15, 12); } // for vsplt* instructions
1240 static int vsplti_sim(int x) { return opp_u_field(x, 15, 11); } // for vsplti* instructions
1241 static int vsldoi_shb(int x) { return opp_u_field(x, 25, 22); } // for vsldoi instruction
1242 static int vcmp_rc( int x) { return opp_u_field(x, 21, 21); } // for vcmp* instructions
1243 static int xxsplt_uim(int x) { return opp_u_field(x, 15, 14); } // for xxsplt* instructions
1244
1245 // For extended opcodes (prefixed instructions) introduced with Power 10
1246 static long r_eo( int x) { return opp_u_field(x, 11, 11); }
1247 static long type( int x) { return opp_u_field(x, 7, 6); }
1248 static long st_x0( int x) { return opp_u_field(x, 8, 8); }
1249 static long st_x1( int x) { return opp_u_field(x, 11, 8); }
1250
1251 // - 8LS:D/MLS:D Formats
1252 static long d0_eo( long x) { return opp_u_field((x >> 16) & 0x3FFFF, 31, 14); }
1253 static long d1_eo( long x) { return opp_u_field(x & 0xFFFF, 31, 16); }
1254 static long s0_eo( long x) { return d0_eo(x); }
1255 static long s1_eo( long x) { return d1_eo(x); }
1256
1257 // - 8RR:XX4/8RR:D Formats
1258 static long imm0_eo( int x) { return opp_u_field(x >> 16, 31, 16); }
1259 static long imm1_eo( int x) { return opp_u_field(x & 0xFFFF, 31, 16); }
1260 static long uimm_eo( int x) { return opp_u_field(x, 31, 29); }
1261 static long imm_eo( int x) { return opp_u_field(x, 31, 24); }
1262
1263 //static int xo1( int x) { return opp_u_field(x, 29, 21); }// is contained in our opcodes
1264 //static int xo2( int x) { return opp_u_field(x, 30, 21); }// is contained in our opcodes
1265 //static int xo3( int x) { return opp_u_field(x, 30, 22); }// is contained in our opcodes
1266 //static int xo4( int x) { return opp_u_field(x, 30, 26); }// is contained in our opcodes
1267 //static int xo5( int x) { return opp_u_field(x, 29, 27); }// is contained in our opcodes
1268 //static int xo6( int x) { return opp_u_field(x, 30, 27); }// is contained in our opcodes
1269 //static int xo7( int x) { return opp_u_field(x, 31, 30); }// is contained in our opcodes
1270
1271 protected:
1272 // Compute relative address for branch.
1273 static intptr_t disp(intptr_t x, intptr_t off) {
1274 int xx = x - off;
1275 xx = xx >> 2;
1276 return xx;
1277 }
1278
1279 public:
1280 // signed immediate, in low bits, nbits long
1281 static int simm(int x, int nbits) {
1282 assert_signed_range(x, nbits);
1283 return x & ((1 << nbits) - 1);
1284 }
1285
1286 // unsigned immediate, in low bits, nbits long
1287 static int uimm(int x, int nbits) {
1288 assert_unsigned_const(x, nbits);
1289 return x & ((1 << nbits) - 1);
1290 }
1291
1292 static void set_imm(int* instr, short s) {
1293 // imm is always in the lower 16 bits of the instruction,
1294 // so this is endian-neutral. Same for the get_imm below.
1295 uint32_t w = *(uint32_t *)instr;
1296 *instr = (int)((w & ~0x0000FFFF) | (s & 0x0000FFFF));
1297 }
1298
1299 static int get_imm(address a, int instruction_number) {
1300 return (short)((int *)a)[instruction_number];
1301 }
1302
1303 static inline int hi16_signed( int x) { return (int)(int16_t)(x >> 16); }
1304 static inline int lo16_unsigned(int x) { return x & 0xffff; }
1305
1306 protected:
1307
1308 // Extract the top 32 bits in a 64 bit word.
1309 static int32_t hi32(int64_t x) {
1310 int32_t r = int32_t((uint64_t)x >> 32);
1311 return r;
1312 }
1313
1314 public:
1315
1316 static inline unsigned int align_addr(unsigned int addr, unsigned int a) {
1317 return ((addr + (a - 1)) & ~(a - 1));
1318 }
1319
1320 static inline bool is_aligned(unsigned int addr, unsigned int a) {
1321 return (0 == addr % a);
1322 }
1323
1324 void flush() {
1325 AbstractAssembler::flush();
1326 }
1327
1328 inline void emit_int32(int); // shadows AbstractAssembler::emit_int32
1329 inline void emit_data(int);
1330 inline void emit_data(int, RelocationHolder const&);
1331 inline void emit_data(int, relocInfo::relocType rtype);
1332
1333 // Emit an address.
1334 inline address emit_addr(const address addr = nullptr);
1335
1336 #if !defined(ABI_ELFv2)
1337 // Emit a function descriptor with the specified entry point, TOC,
1338 // and ENV. If the entry point is null, the descriptor will point
1339 // just past the descriptor.
1340 // Use values from friend functions as defaults.
1341 inline address emit_fd(address entry = nullptr,
1342 address toc = (address) FunctionDescriptor::friend_toc,
1343 address env = (address) FunctionDescriptor::friend_env);
1344 #endif
1345
1346 /////////////////////////////////////////////////////////////////////////////////////
1347 // PPC instructions
1348 /////////////////////////////////////////////////////////////////////////////////////
1349
1350 // Memory instructions use r0 as hard coded 0, e.g. to simulate loading
1351 // immediates. The normal instruction encoders enforce that r0 is not
1352 // passed to them. Use either extended mnemonics encoders or the special ra0
1353 // versions.
1354
1355 // Issue an illegal instruction.
1356 inline void illtrap();
1357 static inline bool is_illtrap(address instr_addr);
1358
1359 // PPC 1, section 3.3.8, Fixed-Point Arithmetic Instructions
1360 inline void addi( Register d, Register a, int si16);
1361 inline void addis(Register d, Register a, int si16);
1362
1363 // Prefixed add immediate, introduced by POWER10
1364 inline void paddi(Register d, Register a, long si34, bool r);
1365 inline void pli( Register d, long si34);
1366
1367 private:
1368 inline void addi_r0ok( Register d, Register a, int si16);
1369 inline void addis_r0ok(Register d, Register a, int si16);
1370 inline void paddi_r0ok(Register d, Register a, long si34, bool r);
1371 public:
1372 inline void addic_( Register d, Register a, int si16);
1373 inline void subfic( Register d, Register a, int si16);
1374 inline void add( Register d, Register a, Register b);
1375 inline void add_( Register d, Register a, Register b);
1376 inline void subf( Register d, Register a, Register b); // d = b - a "Sub_from", as in ppc spec.
1377 inline void sub( Register d, Register a, Register b); // d = a - b Swap operands of subf for readability.
1378 inline void subf_( Register d, Register a, Register b);
1379 inline void addc( Register d, Register a, Register b);
1380 inline void addc_( Register d, Register a, Register b);
1381 inline void subfc( Register d, Register a, Register b);
1382 inline void subfc_( Register d, Register a, Register b);
1383 inline void adde( Register d, Register a, Register b);
1384 inline void adde_( Register d, Register a, Register b);
1385 inline void subfe( Register d, Register a, Register b);
1386 inline void subfe_( Register d, Register a, Register b);
1387 inline void addme( Register d, Register a);
1388 inline void addme_( Register d, Register a);
1389 inline void subfme( Register d, Register a);
1390 inline void subfme_(Register d, Register a);
1391 inline void addze( Register d, Register a);
1392 inline void addze_( Register d, Register a);
1393 inline void subfze( Register d, Register a);
1394 inline void subfze_(Register d, Register a);
1395 inline void neg( Register d, Register a);
1396 inline void neg_( Register d, Register a);
1397 inline void mulli( Register d, Register a, int si16);
1398 inline void mulld( Register d, Register a, Register b);
1399 inline void mulld_( Register d, Register a, Register b);
1400 inline void mullw( Register d, Register a, Register b);
1401 inline void mullw_( Register d, Register a, Register b);
1402 inline void mulhw( Register d, Register a, Register b);
1403 inline void mulhw_( Register d, Register a, Register b);
1404 inline void mulhwu( Register d, Register a, Register b);
1405 inline void mulhwu_(Register d, Register a, Register b);
1406 inline void mulhd( Register d, Register a, Register b);
1407 inline void mulhd_( Register d, Register a, Register b);
1408 inline void mulhdu( Register d, Register a, Register b);
1409 inline void mulhdu_(Register d, Register a, Register b);
1410 inline void divd( Register d, Register a, Register b);
1411 inline void divd_( Register d, Register a, Register b);
1412 inline void divw( Register d, Register a, Register b);
1413 inline void divw_( Register d, Register a, Register b);
1414 inline void divdu( Register d, Register a, Register b);
1415 inline void divdu_( Register d, Register a, Register b);
1416 inline void divwu( Register d, Register a, Register b);
1417 inline void divwu_( Register d, Register a, Register b);
1418
1419 // Fixed-Point Arithmetic Instructions with Overflow detection
1420 inline void addo( Register d, Register a, Register b);
1421 inline void addo_( Register d, Register a, Register b);
1422 inline void subfo( Register d, Register a, Register b);
1423 inline void subfo_( Register d, Register a, Register b);
1424 inline void addco( Register d, Register a, Register b);
1425 inline void addco_( Register d, Register a, Register b);
1426 inline void subfco( Register d, Register a, Register b);
1427 inline void subfco_( Register d, Register a, Register b);
1428 inline void addeo( Register d, Register a, Register b);
1429 inline void addeo_( Register d, Register a, Register b);
1430 inline void subfeo( Register d, Register a, Register b);
1431 inline void subfeo_( Register d, Register a, Register b);
1432 inline void addmeo( Register d, Register a);
1433 inline void addmeo_( Register d, Register a);
1434 inline void subfmeo( Register d, Register a);
1435 inline void subfmeo_(Register d, Register a);
1436 inline void addzeo( Register d, Register a);
1437 inline void addzeo_( Register d, Register a);
1438 inline void subfzeo( Register d, Register a);
1439 inline void subfzeo_(Register d, Register a);
1440 inline void nego( Register d, Register a);
1441 inline void nego_( Register d, Register a);
1442 inline void mulldo( Register d, Register a, Register b);
1443 inline void mulldo_( Register d, Register a, Register b);
1444 inline void mullwo( Register d, Register a, Register b);
1445 inline void mullwo_( Register d, Register a, Register b);
1446 inline void divdo( Register d, Register a, Register b);
1447 inline void divdo_( Register d, Register a, Register b);
1448 inline void divwo( Register d, Register a, Register b);
1449 inline void divwo_( Register d, Register a, Register b);
1450
1451 // extended mnemonics
1452 inline void li( Register d, int si16);
1453 inline void lis( Register d, int si16);
1454 inline void addir(Register d, int si16, Register a);
1455 inline void subi( Register d, Register a, int si16);
1456
1457 static bool is_addi(int x) {
1458 return ADDI_OPCODE == (x & ADDI_OPCODE_MASK);
1459 }
1460 static bool is_addis(int x) {
1461 return ADDIS_OPCODE == (x & ADDIS_OPCODE_MASK);
1462 }
1463 static bool is_andi(int x) {
1464 return ANDI_OPCODE == (x & ANDI_OPCODE_MASK);
1465 }
1466 static bool is_bxx(int x) {
1467 return BXX_OPCODE == (x & BXX_OPCODE_MASK);
1468 }
1469 static bool is_b(int x) {
1470 return BXX_OPCODE == (x & BXX_OPCODE_MASK) && inv_lk_field(x) == 0;
1471 }
1472 static bool is_bl(int x) {
1473 return BXX_OPCODE == (x & BXX_OPCODE_MASK) && inv_lk_field(x) == 1;
1474 }
1475 static bool is_bcxx(int x) {
1476 return BCXX_OPCODE == (x & BCXX_OPCODE_MASK);
1477 }
1478 static bool is_bxx_or_bcxx(int x) {
1479 return is_bxx(x) || is_bcxx(x);
1480 }
1481 static bool is_bctrl(int x) {
1482 return x == 0x4e800421;
1483 }
1484 static bool is_bctr(int x) {
1485 return x == 0x4e800420;
1486 }
1487 static bool is_bclr(int x) {
1488 return BCLR_OPCODE == (x & XL_FORM_OPCODE_MASK);
1489 }
1490 static bool is_cmpli(int x) {
1491 return CMPLI_OPCODE == (x & CMPLI_OPCODE_MASK);
1492 }
1493 static bool is_li(int x) {
1494 return is_addi(x) && inv_ra_field(x)==0;
1495 }
1496 static bool is_lis(int x) {
1497 return is_addis(x) && inv_ra_field(x)==0;
1498 }
1499 static bool is_mtctr(int x) {
1500 return MTCTR_OPCODE == (x & MTCTR_OPCODE_MASK);
1501 }
1502 static bool is_ld(int x) {
1503 return LD_OPCODE == (x & LD_OPCODE_MASK);
1504 }
1505 static bool is_std(int x) {
1506 return STD_OPCODE == (x & STD_OPCODE_MASK);
1507 }
1508 static bool is_stdu(int x) {
1509 return STDU_OPCODE == (x & STDU_OPCODE_MASK);
1510 }
1511 static bool is_stdx(int x) {
1512 return STDX_OPCODE == (x & STDX_OPCODE_MASK);
1513 }
1514 static bool is_stdux(int x) {
1515 return STDUX_OPCODE == (x & STDUX_OPCODE_MASK);
1516 }
1517 static bool is_stwx(int x) {
1518 return STWX_OPCODE == (x & STWX_OPCODE_MASK);
1519 }
1520 static bool is_stwux(int x) {
1521 return STWUX_OPCODE == (x & STWUX_OPCODE_MASK);
1522 }
1523 static bool is_stw(int x) {
1524 return STW_OPCODE == (x & STW_OPCODE_MASK);
1525 }
1526 static bool is_stwu(int x) {
1527 return STWU_OPCODE == (x & STWU_OPCODE_MASK);
1528 }
1529 static bool is_ori(int x) {
1530 return ORI_OPCODE == (x & ORI_OPCODE_MASK);
1531 };
1532 static bool is_oris(int x) {
1533 return ORIS_OPCODE == (x & ORIS_OPCODE_MASK);
1534 };
1535 static bool is_rldicr(int x) {
1536 return (RLDICR_OPCODE == (x & RLDICR_OPCODE_MASK));
1537 };
1538 static bool is_nop(int x) {
1539 return x == 0x60000000;
1540 }
1541 // endgroup opcode for Power6
1542 static bool is_endgroup(int x) {
1543 return is_ori(x) && inv_ra_field(x) == 1 && inv_rs_field(x) == 1 && inv_d1_field(x) == 0;
1544 }
1545
1546
1547 private:
1548 // PPC 1, section 3.3.9, Fixed-Point Compare Instructions
1549 inline void cmpi( ConditionRegister bf, int l, Register a, int si16);
1550 inline void cmp( ConditionRegister bf, int l, Register a, Register b);
1551 inline void cmpli(ConditionRegister bf, int l, Register a, int ui16);
1552 inline void cmpl( ConditionRegister bf, int l, Register a, Register b);
1553
1554 public:
1555 // extended mnemonics of Compare Instructions
1556 inline void cmpwi( ConditionRegister crx, Register a, int si16);
1557 inline void cmpdi( ConditionRegister crx, Register a, int si16);
1558 inline void cmpw( ConditionRegister crx, Register a, Register b);
1559 inline void cmpd( ConditionRegister crx, Register a, Register b);
1560 inline void cmplwi(ConditionRegister crx, Register a, int ui16);
1561 inline void cmpldi(ConditionRegister crx, Register a, int ui16);
1562 inline void cmplw( ConditionRegister crx, Register a, Register b);
1563 inline void cmpld( ConditionRegister crx, Register a, Register b);
1564
1565 // >= Power9
1566 inline void cmprb( ConditionRegister bf, int l, Register a, Register b);
1567 inline void cmpeqb(ConditionRegister bf, Register a, Register b);
1568
1569 inline void isel( Register d, Register a, Register b, int bc);
1570 // Convenient version which takes: Condition register, Condition code and invert flag. Omit b to keep old value.
1571 inline void isel( Register d, ConditionRegister cr, Condition cc, bool inv, Register a, Register b = noreg);
1572 // Set d = 0 if (cr.cc) equals 1, otherwise b.
1573 inline void isel_0( Register d, ConditionRegister cr, Condition cc, Register b = noreg);
1574
1575 // PPC 1, section 3.3.11, Fixed-Point Logical Instructions
1576 void andi( Register a, Register s, long ui16); // optimized version
1577 inline void andi_( Register a, Register s, int ui16);
1578 inline void andis_( Register a, Register s, int ui16);
1579 inline void ori( Register a, Register s, int ui16);
1580 inline void oris( Register a, Register s, int ui16);
1581 inline void xori( Register a, Register s, int ui16);
1582 inline void xoris( Register a, Register s, int ui16);
1583 inline void andr( Register a, Register s, Register b); // suffixed by 'r' as 'and' is C++ keyword
1584 inline void and_( Register a, Register s, Register b);
1585 // Turn or0(rx,rx,rx) into a nop and avoid that we accidentally emit a
1586 // SMT-priority change instruction (see SMT instructions below).
1587 inline void or_unchecked(Register a, Register s, Register b);
1588 inline void orr( Register a, Register s, Register b); // suffixed by 'r' as 'or' is C++ keyword
1589 inline void or_( Register a, Register s, Register b);
1590 inline void xorr( Register a, Register s, Register b); // suffixed by 'r' as 'xor' is C++ keyword
1591 inline void xor_( Register a, Register s, Register b);
1592 inline void nand( Register a, Register s, Register b);
1593 inline void nand_( Register a, Register s, Register b);
1594 inline void nor( Register a, Register s, Register b);
1595 inline void nor_( Register a, Register s, Register b);
1596 inline void andc( Register a, Register s, Register b);
1597 inline void andc_( Register a, Register s, Register b);
1598 inline void orc( Register a, Register s, Register b);
1599 inline void orc_( Register a, Register s, Register b);
1600 inline void extsb( Register a, Register s);
1601 inline void extsb_( Register a, Register s);
1602 inline void extsh( Register a, Register s);
1603 inline void extsh_( Register a, Register s);
1604 inline void extsw( Register a, Register s);
1605 inline void extsw_( Register a, Register s);
1606
1607 // extended mnemonics
1608 inline void nop();
1609 // NOP for FP and BR units (different versions to allow them to be in one group)
1610 inline void fpnop0();
1611 inline void fpnop1();
1612 inline void brnop0();
1613 inline void brnop1();
1614 inline void brnop2();
1615
1616 inline void mr( Register d, Register s);
1617 inline void ori_opt( Register d, int ui16);
1618 inline void oris_opt(Register d, int ui16);
1619
1620 // endgroup opcode for Power6
1621 inline void endgroup();
1622
1623 // count instructions
1624 inline void cntlzw( Register a, Register s);
1625 inline void cntlzw_( Register a, Register s);
1626 inline void cntlzd( Register a, Register s);
1627 inline void cntlzd_( Register a, Register s);
1628 inline void cnttzw( Register a, Register s);
1629 inline void cnttzw_( Register a, Register s);
1630 inline void cnttzd( Register a, Register s);
1631 inline void cnttzd_( Register a, Register s);
1632
1633 // PPC 1, section 3.3.12, Fixed-Point Rotate and Shift Instructions
1634 inline void sld( Register a, Register s, Register b);
1635 inline void sld_( Register a, Register s, Register b);
1636 inline void slw( Register a, Register s, Register b);
1637 inline void slw_( Register a, Register s, Register b);
1638 inline void srd( Register a, Register s, Register b);
1639 inline void srd_( Register a, Register s, Register b);
1640 inline void srw( Register a, Register s, Register b);
1641 inline void srw_( Register a, Register s, Register b);
1642 inline void srad( Register a, Register s, Register b);
1643 inline void srad_( Register a, Register s, Register b);
1644 inline void sraw( Register a, Register s, Register b);
1645 inline void sraw_( Register a, Register s, Register b);
1646 inline void sradi( Register a, Register s, int sh6);
1647 inline void sradi_( Register a, Register s, int sh6);
1648 inline void srawi( Register a, Register s, int sh5);
1649 inline void srawi_( Register a, Register s, int sh5);
1650
1651 // extended mnemonics for Shift Instructions
1652 inline void sldi( Register a, Register s, int sh6);
1653 inline void sldi_( Register a, Register s, int sh6);
1654 inline void slwi( Register a, Register s, int sh5);
1655 inline void slwi_( Register a, Register s, int sh5);
1656 inline void srdi( Register a, Register s, int sh6);
1657 inline void srdi_( Register a, Register s, int sh6);
1658 inline void srwi( Register a, Register s, int sh5);
1659 inline void srwi_( Register a, Register s, int sh5);
1660
1661 inline void clrrdi( Register a, Register s, int ui6);
1662 inline void clrrdi_( Register a, Register s, int ui6);
1663 inline void clrldi( Register a, Register s, int ui6);
1664 inline void clrldi_( Register a, Register s, int ui6);
1665 inline void clrlsldi(Register a, Register s, int clrl6, int shl6);
1666 inline void clrlsldi_(Register a, Register s, int clrl6, int shl6);
1667 inline void extrdi( Register a, Register s, int n, int b);
1668 // testbit with condition register
1669 inline void testbitdi(ConditionRegister cr, Register a, Register s, int ui6);
1670
1671 // Byte reverse instructions (introduced with Power10)
1672 inline void brh( Register a, Register s);
1673 inline void brw( Register a, Register s);
1674 inline void brd( Register a, Register s);
1675
1676 // rotate instructions
1677 inline void rotldi( Register a, Register s, int n);
1678 inline void rotrdi( Register a, Register s, int n);
1679 inline void rotlwi( Register a, Register s, int n);
1680 inline void rotrwi( Register a, Register s, int n);
1681
1682 // Rotate Instructions
1683 inline void rldic( Register a, Register s, int sh6, int mb6);
1684 inline void rldic_( Register a, Register s, int sh6, int mb6);
1685 inline void rldicr( Register a, Register s, int sh6, int mb6);
1686 inline void rldicr_( Register a, Register s, int sh6, int mb6);
1687 inline void rldicl( Register a, Register s, int sh6, int mb6);
1688 inline void rldicl_( Register a, Register s, int sh6, int mb6);
1689 inline void rlwinm( Register a, Register s, int sh5, int mb5, int me5);
1690 inline void rlwinm_( Register a, Register s, int sh5, int mb5, int me5);
1691 inline void rldimi( Register a, Register s, int sh6, int mb6);
1692 inline void rldimi_( Register a, Register s, int sh6, int mb6);
1693 inline void rlwimi( Register a, Register s, int sh5, int mb5, int me5);
1694 inline void insrdi( Register a, Register s, int n, int b);
1695 inline void insrwi( Register a, Register s, int n, int b);
1696
1697 // PPC 1, section 3.3.2 Fixed-Point Load Instructions
1698 // 4 bytes
1699 inline void lwzx( Register d, Register s1, Register s2);
1700 inline void lwz( Register d, int si16, Register s1);
1701 inline void lwzu( Register d, int si16, Register s1);
1702
1703 // 4 bytes
1704 inline void lwax( Register d, Register s1, Register s2);
1705 inline void lwa( Register d, int si16, Register s1);
1706
1707 // 4 bytes reversed
1708 inline void lwbrx( Register d, Register s1, Register s2);
1709
1710 // 2 bytes
1711 inline void lhzx( Register d, Register s1, Register s2);
1712 inline void lhz( Register d, int si16, Register s1);
1713 inline void lhzu( Register d, int si16, Register s1);
1714
1715 // 2 bytes reversed
1716 inline void lhbrx( Register d, Register s1, Register s2);
1717
1718 // 2 bytes
1719 inline void lhax( Register d, Register s1, Register s2);
1720 inline void lha( Register d, int si16, Register s1);
1721 inline void lhau( Register d, int si16, Register s1);
1722
1723 // 1 byte
1724 inline void lbzx( Register d, Register s1, Register s2);
1725 inline void lbz( Register d, int si16, Register s1);
1726 inline void lbzu( Register d, int si16, Register s1);
1727
1728 // 8 bytes
1729 inline void ldx( Register d, Register s1, Register s2);
1730 inline void ld( Register d, int si16, Register s1);
1731 inline void ld( Register d, ByteSize si16, Register s1);
1732 inline void ldu( Register d, int si16, Register s1);
1733
1734 // 8 bytes reversed
1735 inline void ldbrx( Register d, Register s1, Register s2);
1736
1737 // For convenience. Load pointer into d from b+s1.
1738 inline void ld_ptr(Register d, int b, Register s1);
1739 inline void ld_ptr(Register d, ByteSize b, Register s1);
1740
1741 // PPC 1, section 3.3.3 Fixed-Point Store Instructions
1742 inline void stwx( Register d, Register s1, Register s2);
1743 inline void stw( Register d, int si16, Register s1);
1744 inline void stwu( Register d, int si16, Register s1);
1745 inline void stwbrx( Register d, Register s1, Register s2);
1746
1747 inline void sthx( Register d, Register s1, Register s2);
1748 inline void sth( Register d, int si16, Register s1);
1749 inline void sthu( Register d, int si16, Register s1);
1750 inline void sthbrx( Register d, Register s1, Register s2);
1751
1752 inline void stbx( Register d, Register s1, Register s2);
1753 inline void stb( Register d, int si16, Register s1);
1754 inline void stbu( Register d, int si16, Register s1);
1755
1756 inline void stdx( Register d, Register s1, Register s2);
1757 inline void std( Register d, int si16, Register s1);
1758 inline void stdu( Register d, int si16, Register s1);
1759 inline void stdux(Register s, Register a, Register b);
1760 inline void stdbrx( Register d, Register s1, Register s2);
1761
1762 inline void st_ptr(Register d, int si16, Register s1);
1763 inline void st_ptr(Register d, ByteSize b, Register s1);
1764
1765 // PPC 1, section 3.3.13 Move To/From System Register Instructions
1766 inline void mtlr( Register s1);
1767 inline void mflr( Register d);
1768 inline void mtctr(Register s1);
1769 inline void mfctr(Register d);
1770 inline void mtcrf(int fxm, Register s);
1771 inline void mfcr( Register d);
1772 inline void mcrf( ConditionRegister crd, ConditionRegister cra);
1773 inline void mtcr( Register s);
1774 // >= Power9
1775 inline void mcrxrx(ConditionRegister cra);
1776 inline void setb( Register d, ConditionRegister cra);
1777
1778 // >= Power10
1779 inline void setbc( Register d, int biint);
1780 inline void setbc( Register d, ConditionRegister cr, Condition cc);
1781 inline void setnbc(Register d, int biint);
1782 inline void setnbc(Register d, ConditionRegister cr, Condition cc);
1783
1784 // Special purpose registers
1785 // Exception Register
1786 inline void mtxer(Register s1);
1787 inline void mfxer(Register d);
1788 // Vector Register Save Register
1789 inline void mtvrsave(Register s1);
1790 inline void mfvrsave(Register d);
1791 // Timebase
1792 inline void mftb(Register d);
1793 // Introduced with Power 8:
1794 // Data Stream Control Register
1795 inline void mtdscr(Register s1);
1796 inline void mfdscr(Register d );
1797
1798 // PPC 1, section 2.4.1 Branch Instructions
1799 inline void b( address a, relocInfo::relocType rt = relocInfo::none);
1800 inline void b( Label& L);
1801 inline void bl( address a, relocInfo::relocType rt = relocInfo::none);
1802 inline void bl( Label& L);
1803 inline void bc( int boint, int biint, address a, relocInfo::relocType rt = relocInfo::none);
1804 inline void bc( int boint, int biint, Label& L);
1805 inline void bcl(int boint, int biint, address a, relocInfo::relocType rt = relocInfo::none);
1806 inline void bcl(int boint, int biint, Label& L);
1807
1808 inline void bclr( int boint, int biint, int bhint, relocInfo::relocType rt = relocInfo::none);
1809 inline void bclrl( int boint, int biint, int bhint, relocInfo::relocType rt = relocInfo::none);
1810 inline void bcctr( int boint, int biint, int bhint = bhintbhBCCTRisNotReturnButSame,
1811 relocInfo::relocType rt = relocInfo::none);
1812 inline void bcctrl(int boint, int biint, int bhint = bhintbhBCLRisReturn,
1813 relocInfo::relocType rt = relocInfo::none);
1814
1815 // helper function for b, bcxx
1816 inline bool is_within_range_of_b(address a, address pc);
1817 inline bool is_within_range_of_bcxx(address a, address pc);
1818
1819 // get the destination of a bxx branch (b, bl, ba, bla)
1820 static inline address bxx_destination(address baddr);
1821 static inline address bxx_destination(int instr, address pc);
1822 static inline intptr_t bxx_destination_offset(int instr, intptr_t bxx_pos);
1823
1824 // extended mnemonics for branch instructions
1825 inline void blt(ConditionRegister crx, Label& L);
1826 inline void bgt(ConditionRegister crx, Label& L);
1827 inline void beq(ConditionRegister crx, Label& L);
1828 inline void bso(ConditionRegister crx, Label& L);
1829 inline void bge(ConditionRegister crx, Label& L);
1830 inline void ble(ConditionRegister crx, Label& L);
1831 inline void bne(ConditionRegister crx, Label& L);
1832 inline void bns(ConditionRegister crx, Label& L);
1833
1834 // Branch instructions with static prediction hints.
1835 inline void blt_predict_taken( ConditionRegister crx, Label& L);
1836 inline void bgt_predict_taken( ConditionRegister crx, Label& L);
1837 inline void beq_predict_taken( ConditionRegister crx, Label& L);
1838 inline void bso_predict_taken( ConditionRegister crx, Label& L);
1839 inline void bge_predict_taken( ConditionRegister crx, Label& L);
1840 inline void ble_predict_taken( ConditionRegister crx, Label& L);
1841 inline void bne_predict_taken( ConditionRegister crx, Label& L);
1842 inline void bns_predict_taken( ConditionRegister crx, Label& L);
1843 inline void blt_predict_not_taken(ConditionRegister crx, Label& L);
1844 inline void bgt_predict_not_taken(ConditionRegister crx, Label& L);
1845 inline void beq_predict_not_taken(ConditionRegister crx, Label& L);
1846 inline void bso_predict_not_taken(ConditionRegister crx, Label& L);
1847 inline void bge_predict_not_taken(ConditionRegister crx, Label& L);
1848 inline void ble_predict_not_taken(ConditionRegister crx, Label& L);
1849 inline void bne_predict_not_taken(ConditionRegister crx, Label& L);
1850 inline void bns_predict_not_taken(ConditionRegister crx, Label& L);
1851
1852 // for use in conjunction with testbitdi:
1853 inline void btrue( ConditionRegister crx, Label& L);
1854 inline void bfalse(ConditionRegister crx, Label& L);
1855
1856 inline void bltl(ConditionRegister crx, Label& L);
1857 inline void bgtl(ConditionRegister crx, Label& L);
1858 inline void beql(ConditionRegister crx, Label& L);
1859 inline void bsol(ConditionRegister crx, Label& L);
1860 inline void bgel(ConditionRegister crx, Label& L);
1861 inline void blel(ConditionRegister crx, Label& L);
1862 inline void bnel(ConditionRegister crx, Label& L);
1863 inline void bnsl(ConditionRegister crx, Label& L);
1864
1865 // extended mnemonics for Branch Instructions via LR
1866 // We use `blr' for returns.
1867 inline void blr(relocInfo::relocType rt = relocInfo::none);
1868
1869 // extended mnemonics for Branch Instructions with CTR
1870 // bdnz means `decrement CTR and jump to L if CTR is not zero'
1871 inline void bdnz(Label& L);
1872 // Decrement and branch if result is zero.
1873 inline void bdz(Label& L);
1874 // we use `bctr[l]' for jumps/calls in function descriptor glue
1875 // code, e.g. calls to runtime functions
1876 inline void bctr( relocInfo::relocType rt = relocInfo::none);
1877 inline void bctrl(relocInfo::relocType rt = relocInfo::none);
1878 // conditional jumps/branches via CTR
1879 inline void beqctr( ConditionRegister crx, relocInfo::relocType rt = relocInfo::none);
1880 inline void beqctrl(ConditionRegister crx, relocInfo::relocType rt = relocInfo::none);
1881 inline void bnectr( ConditionRegister crx, relocInfo::relocType rt = relocInfo::none);
1882 inline void bnectrl(ConditionRegister crx, relocInfo::relocType rt = relocInfo::none);
1883
1884 // condition register logic instructions
1885 // NOTE: There's a preferred form: d and s2 should point into the same condition register.
1886 inline void crand( int d, int s1, int s2);
1887 inline void crnand(int d, int s1, int s2);
1888 inline void cror( int d, int s1, int s2);
1889 inline void crxor( int d, int s1, int s2);
1890 inline void crnor( int d, int s1, int s2);
1891 inline void creqv( int d, int s1, int s2);
1892 inline void crandc(int d, int s1, int s2);
1893 inline void crorc( int d, int s1, int s2);
1894
1895 // More convenient version.
1896 int condition_register_bit(ConditionRegister cr, Condition c) {
1897 return 4 * cr.encoding() + c;
1898 }
1899 void crand( ConditionRegister crdst, Condition cdst, ConditionRegister crsrc, Condition csrc);
1900 void crnand(ConditionRegister crdst, Condition cdst, ConditionRegister crsrc, Condition csrc);
1901 void cror( ConditionRegister crdst, Condition cdst, ConditionRegister crsrc, Condition csrc);
1902 void crxor( ConditionRegister crdst, Condition cdst, ConditionRegister crsrc, Condition csrc);
1903 void crnor( ConditionRegister crdst, Condition cdst, ConditionRegister crsrc, Condition csrc);
1904 void creqv( ConditionRegister crdst, Condition cdst, ConditionRegister crsrc, Condition csrc);
1905 void crandc(ConditionRegister crdst, Condition cdst, ConditionRegister crsrc, Condition csrc);
1906 void crorc( ConditionRegister crdst, Condition cdst, ConditionRegister crsrc, Condition csrc);
1907
1908 // icache and dcache related instructions
1909 inline void icbi( Register s1, Register s2);
1910 //inline void dcba(Register s1, Register s2); // Instruction for embedded processor only.
1911 inline void dcbz( Register s1, Register s2);
1912 inline void dcbst( Register s1, Register s2);
1913 inline void dcbf( Register s1, Register s2);
1914
1915 enum ct_cache_specification {
1916 ct_primary_cache = 0,
1917 ct_secondary_cache = 2
1918 };
1919 // dcache read hint
1920 inline void dcbt( Register s1, Register s2);
1921 inline void dcbtct( Register s1, Register s2, int ct);
1922 inline void dcbtds( Register s1, Register s2, int ds);
1923 // dcache write hint
1924 inline void dcbtst( Register s1, Register s2);
1925 inline void dcbtstct(Register s1, Register s2, int ct);
1926
1927 // machine barrier instructions:
1928 //
1929 // - sync two-way memory barrier, aka fence
1930 // - lwsync orders Store|Store,
1931 // Load|Store,
1932 // Load|Load,
1933 // but not Store|Load
1934 // - eieio orders memory accesses for device memory (only)
1935 // - isync invalidates speculatively executed instructions
1936 // From the Power ISA 2.06 documentation:
1937 // "[...] an isync instruction prevents the execution of
1938 // instructions following the isync until instructions
1939 // preceding the isync have completed, [...]"
1940 // From IBM's AIX assembler reference:
1941 // "The isync [...] instructions causes the processor to
1942 // refetch any instructions that might have been fetched
1943 // prior to the isync instruction. The instruction isync
1944 // causes the processor to wait for all previous instructions
1945 // to complete. Then any instructions already fetched are
1946 // discarded and instruction processing continues in the
1947 // environment established by the previous instructions."
1948 //
1949 // semantic barrier instructions:
1950 // (as defined in orderAccess.hpp)
1951 //
1952 // - release orders Store|Store, (maps to lwsync)
1953 // Load|Store
1954 // - acquire orders Load|Store, (maps to lwsync)
1955 // Load|Load
1956 // - fence orders Store|Store, (maps to sync)
1957 // Load|Store,
1958 // Load|Load,
1959 // Store|Load
1960 //
1961 private:
1962 inline void sync(int l);
1963 public:
1964 inline void sync();
1965 inline void lwsync();
1966 inline void ptesync();
1967 inline void eieio();
1968 inline void isync();
1969 inline void elemental_membar(int e); // Elemental Memory Barriers (>=Power 8)
1970
1971 // Wait instructions for polling. Attention: May result in SIGILL.
1972 inline void wait();
1973 inline void waitrsv(); // >=Power7
1974
1975 // atomics
1976 inline void lbarx_unchecked(Register d, Register a, Register b, int eh1 = 0); // >=Power 8
1977 inline void lharx_unchecked(Register d, Register a, Register b, int eh1 = 0); // >=Power 8
1978 inline void lwarx_unchecked(Register d, Register a, Register b, int eh1 = 0);
1979 inline void ldarx_unchecked(Register d, Register a, Register b, int eh1 = 0);
1980 inline void lqarx_unchecked(Register d, Register a, Register b, int eh1 = 0); // >=Power 8
1981 inline bool lxarx_hint_exclusive_access();
1982 inline void lbarx( Register d, Register a, Register b, bool hint_exclusive_access = false);
1983 inline void lharx( Register d, Register a, Register b, bool hint_exclusive_access = false);
1984 inline void lwarx( Register d, Register a, Register b, bool hint_exclusive_access = false);
1985 inline void ldarx( Register d, Register a, Register b, bool hint_exclusive_access = false);
1986 inline void lqarx( Register d, Register a, Register b, bool hint_exclusive_access = false);
1987 inline void stbcx_( Register s, Register a, Register b);
1988 inline void sthcx_( Register s, Register a, Register b);
1989 inline void stwcx_( Register s, Register a, Register b);
1990 inline void stdcx_( Register s, Register a, Register b);
1991 inline void stqcx_( Register s, Register a, Register b);
1992
1993 // Instructions for adjusting thread priority for simultaneous
1994 // multithreading (SMT) on Power5.
1995 private:
1996 inline void smt_prio_very_low();
1997 inline void smt_prio_medium_high();
1998 inline void smt_prio_high();
1999
2000 public:
2001 inline void smt_prio_low();
2002 inline void smt_prio_medium_low();
2003 inline void smt_prio_medium();
2004 // >= Power7
2005 inline void smt_yield();
2006 inline void smt_mdoio();
2007 inline void smt_mdoom();
2008 // >= Power8
2009 inline void smt_miso();
2010
2011 // trap instructions
2012 inline void twi_0(Register a); // for load with acquire semantics use load+twi_0+isync (trap can't occur)
2013 // NOT FOR DIRECT USE!!
2014 protected:
2015 inline void tdi_unchecked(int tobits, Register a, int si16);
2016 inline void twi_unchecked(int tobits, Register a, int si16);
2017 inline void tdi( int tobits, Register a, int si16); // asserts UseSIGTRAP
2018 inline void twi( int tobits, Register a, int si16); // asserts UseSIGTRAP
2019 inline void td( int tobits, Register a, Register b); // asserts UseSIGTRAP
2020 inline void tw( int tobits, Register a, Register b); // asserts UseSIGTRAP
2021
2022 public:
2023 static bool is_tdi(int x, int tobits, int ra, int si16) {
2024 return (TDI_OPCODE == (x & TDI_OPCODE_MASK))
2025 && (tobits == inv_to_field(x))
2026 && (ra == -1/*any reg*/ || ra == inv_ra_field(x))
2027 && (si16 == inv_si_field(x));
2028 }
2029
2030 static int tdi_get_si16(int x, int tobits, int ra) {
2031 if (TDI_OPCODE == (x & TDI_OPCODE_MASK)
2032 && (tobits == inv_to_field(x))
2033 && (ra == -1/*any reg*/ || ra == inv_ra_field(x))) {
2034 return inv_si_field(x);
2035 }
2036 return -1; // No valid tdi instruction.
2037 }
2038
2039 static bool is_twi(int x, int tobits, int ra, int si16) {
2040 return (TWI_OPCODE == (x & TWI_OPCODE_MASK))
2041 && (tobits == inv_to_field(x))
2042 && (ra == -1/*any reg*/ || ra == inv_ra_field(x))
2043 && (si16 == inv_si_field(x));
2044 }
2045
2046 static bool is_twi(int x, int tobits, int ra) {
2047 return (TWI_OPCODE == (x & TWI_OPCODE_MASK))
2048 && (tobits == inv_to_field(x))
2049 && (ra == -1/*any reg*/ || ra == inv_ra_field(x));
2050 }
2051
2052 static bool is_td(int x, int tobits, int ra, int rb) {
2053 return (TD_OPCODE == (x & TD_OPCODE_MASK))
2054 && (tobits == inv_to_field(x))
2055 && (ra == -1/*any reg*/ || ra == inv_ra_field(x))
2056 && (rb == -1/*any reg*/ || rb == inv_rb_field(x));
2057 }
2058
2059 static bool is_tw(int x, int tobits, int ra, int rb) {
2060 return (TW_OPCODE == (x & TW_OPCODE_MASK))
2061 && (tobits == inv_to_field(x))
2062 && (ra == -1/*any reg*/ || ra == inv_ra_field(x))
2063 && (rb == -1/*any reg*/ || rb == inv_rb_field(x));
2064 }
2065
2066 // PPC floating point instructions
2067 // PPC 1, section 4.6.2 Floating-Point Load Instructions
2068 inline void lfs( FloatRegister d, int si16, Register a);
2069 inline void lfsu( FloatRegister d, int si16, Register a);
2070 inline void lfsx( FloatRegister d, Register a, Register b);
2071 inline void lfd( FloatRegister d, int si16, Register a);
2072 inline void lfdu( FloatRegister d, int si16, Register a);
2073 inline void lfdx( FloatRegister d, Register a, Register b);
2074
2075 // PPC 1, section 4.6.3 Floating-Point Store Instructions
2076 inline void stfs( FloatRegister s, int si16, Register a);
2077 inline void stfsu( FloatRegister s, int si16, Register a);
2078 inline void stfsx( FloatRegister s, Register a, Register b);
2079 inline void stfd( FloatRegister s, int si16, Register a);
2080 inline void stfdu( FloatRegister s, int si16, Register a);
2081 inline void stfdx( FloatRegister s, Register a, Register b);
2082
2083 // PPC 1, section 4.6.4 Floating-Point Move Instructions
2084 inline void fmr( FloatRegister d, FloatRegister b);
2085 inline void fmr_( FloatRegister d, FloatRegister b);
2086
2087 inline void frin( FloatRegister d, FloatRegister b);
2088 inline void frip( FloatRegister d, FloatRegister b);
2089 inline void frim( FloatRegister d, FloatRegister b);
2090
2091 // inline void mffgpr( FloatRegister d, Register b);
2092 // inline void mftgpr( Register d, FloatRegister b);
2093 inline void cmpb( Register a, Register s, Register b);
2094 inline void popcntb(Register a, Register s);
2095 inline void popcntw(Register a, Register s);
2096 inline void popcntd(Register a, Register s);
2097
2098 inline void fneg( FloatRegister d, FloatRegister b);
2099 inline void fneg_( FloatRegister d, FloatRegister b);
2100 inline void fabs( FloatRegister d, FloatRegister b);
2101 inline void fabs_( FloatRegister d, FloatRegister b);
2102 inline void fnabs( FloatRegister d, FloatRegister b);
2103 inline void fnabs_(FloatRegister d, FloatRegister b);
2104
2105 // PPC 1, section 4.6.5.1 Floating-Point Elementary Arithmetic Instructions
2106 inline void fadd( FloatRegister d, FloatRegister a, FloatRegister b);
2107 inline void fadd_( FloatRegister d, FloatRegister a, FloatRegister b);
2108 inline void fadds( FloatRegister d, FloatRegister a, FloatRegister b);
2109 inline void fadds_(FloatRegister d, FloatRegister a, FloatRegister b);
2110 inline void fsub( FloatRegister d, FloatRegister a, FloatRegister b);
2111 inline void fsub_( FloatRegister d, FloatRegister a, FloatRegister b);
2112 inline void fsubs( FloatRegister d, FloatRegister a, FloatRegister b);
2113 inline void fsubs_(FloatRegister d, FloatRegister a, FloatRegister b);
2114 inline void fmul( FloatRegister d, FloatRegister a, FloatRegister c);
2115 inline void fmul_( FloatRegister d, FloatRegister a, FloatRegister c);
2116 inline void fmuls( FloatRegister d, FloatRegister a, FloatRegister c);
2117 inline void fmuls_(FloatRegister d, FloatRegister a, FloatRegister c);
2118 inline void fdiv( FloatRegister d, FloatRegister a, FloatRegister b);
2119 inline void fdiv_( FloatRegister d, FloatRegister a, FloatRegister b);
2120 inline void fdivs( FloatRegister d, FloatRegister a, FloatRegister b);
2121 inline void fdivs_(FloatRegister d, FloatRegister a, FloatRegister b);
2122
2123 // Fused multiply-accumulate instructions.
2124 // WARNING: Use only when rounding between the 2 parts is not desired.
2125 // Some floating point tck tests will fail if used incorrectly.
2126 inline void fmadd( FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b);
2127 inline void fmadd_( FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b);
2128 inline void fmadds( FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b);
2129 inline void fmadds_( FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b);
2130 inline void fmsub( FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b);
2131 inline void fmsub_( FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b);
2132 inline void fmsubs( FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b);
2133 inline void fmsubs_( FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b);
2134 inline void fnmadd( FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b);
2135 inline void fnmadd_( FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b);
2136 inline void fnmadds( FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b);
2137 inline void fnmadds_(FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b);
2138 inline void fnmsub( FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b);
2139 inline void fnmsub_( FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b);
2140 inline void fnmsubs( FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b);
2141 inline void fnmsubs_(FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b);
2142
2143 // PPC 1, section 4.6.6 Floating-Point Rounding and Conversion Instructions
2144 inline void frsp( FloatRegister d, FloatRegister b);
2145 inline void fctid( FloatRegister d, FloatRegister b);
2146 inline void fctidz(FloatRegister d, FloatRegister b);
2147 inline void fctiw( FloatRegister d, FloatRegister b);
2148 inline void fctiwz(FloatRegister d, FloatRegister b);
2149 inline void fcfid( FloatRegister d, FloatRegister b);
2150 inline void fcfids(FloatRegister d, FloatRegister b);
2151
2152 // PPC 1, section 4.6.7 Floating-Point Compare Instructions
2153 inline void fcmpu( ConditionRegister crx, FloatRegister a, FloatRegister b);
2154
2155 inline void fsqrt( FloatRegister d, FloatRegister b);
2156 inline void fsqrts(FloatRegister d, FloatRegister b);
2157
2158 // Vector instructions for >= Power6.
2159 inline void lvebx( VectorRegister d, Register s1, Register s2);
2160 inline void lvehx( VectorRegister d, Register s1, Register s2);
2161 inline void lvewx( VectorRegister d, Register s1, Register s2);
2162 inline void lvx( VectorRegister d, Register s1, Register s2);
2163 inline void lvxl( VectorRegister d, Register s1, Register s2);
2164 inline void stvebx( VectorRegister d, Register s1, Register s2);
2165 inline void stvehx( VectorRegister d, Register s1, Register s2);
2166 inline void stvewx( VectorRegister d, Register s1, Register s2);
2167 inline void stvx( VectorRegister d, Register s1, Register s2);
2168 inline void stvxl( VectorRegister d, Register s1, Register s2);
2169 inline void lvsl( VectorRegister d, Register s1, Register s2);
2170 inline void lvsr( VectorRegister d, Register s1, Register s2);
2171 inline void vpkpx( VectorRegister d, VectorRegister a, VectorRegister b);
2172 inline void vpkshss( VectorRegister d, VectorRegister a, VectorRegister b);
2173 inline void vpkswss( VectorRegister d, VectorRegister a, VectorRegister b);
2174 inline void vpkshus( VectorRegister d, VectorRegister a, VectorRegister b);
2175 inline void vpkswus( VectorRegister d, VectorRegister a, VectorRegister b);
2176 inline void vpkuhum( VectorRegister d, VectorRegister a, VectorRegister b);
2177 inline void vpkuwum( VectorRegister d, VectorRegister a, VectorRegister b);
2178 inline void vpkuhus( VectorRegister d, VectorRegister a, VectorRegister b);
2179 inline void vpkuwus( VectorRegister d, VectorRegister a, VectorRegister b);
2180 inline void vupkhpx( VectorRegister d, VectorRegister b);
2181 inline void vupkhsb( VectorRegister d, VectorRegister b);
2182 inline void vupkhsh( VectorRegister d, VectorRegister b);
2183 inline void vupklpx( VectorRegister d, VectorRegister b);
2184 inline void vupklsb( VectorRegister d, VectorRegister b);
2185 inline void vupklsh( VectorRegister d, VectorRegister b);
2186 inline void vmrghb( VectorRegister d, VectorRegister a, VectorRegister b);
2187 inline void vmrghw( VectorRegister d, VectorRegister a, VectorRegister b);
2188 inline void vmrghh( VectorRegister d, VectorRegister a, VectorRegister b);
2189 inline void vmrglb( VectorRegister d, VectorRegister a, VectorRegister b);
2190 inline void vmrglw( VectorRegister d, VectorRegister a, VectorRegister b);
2191 inline void vmrglh( VectorRegister d, VectorRegister a, VectorRegister b);
2192 inline void vsplt( VectorRegister d, int ui4, VectorRegister b);
2193 inline void vsplth( VectorRegister d, int ui3, VectorRegister b);
2194 inline void vspltw( VectorRegister d, int ui2, VectorRegister b);
2195 inline void vspltisb( VectorRegister d, int si5);
2196 inline void vspltish( VectorRegister d, int si5);
2197 inline void vspltisw( VectorRegister d, int si5);
2198 inline void vperm( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
2199 inline void vpextd( VectorRegister d, VectorRegister a, VectorRegister b);
2200 inline void vsel( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
2201 inline void vsl( VectorRegister d, VectorRegister a, VectorRegister b);
2202 inline void vsldoi( VectorRegister d, VectorRegister a, VectorRegister b, int ui4);
2203 inline void vslo( VectorRegister d, VectorRegister a, VectorRegister b);
2204 inline void vsr( VectorRegister d, VectorRegister a, VectorRegister b);
2205 inline void vsro( VectorRegister d, VectorRegister a, VectorRegister b);
2206 inline void vaddcuw( VectorRegister d, VectorRegister a, VectorRegister b);
2207 inline void vaddshs( VectorRegister d, VectorRegister a, VectorRegister b);
2208 inline void vaddsbs( VectorRegister d, VectorRegister a, VectorRegister b);
2209 inline void vaddsws( VectorRegister d, VectorRegister a, VectorRegister b);
2210 inline void vaddubm( VectorRegister d, VectorRegister a, VectorRegister b);
2211 inline void vadduwm( VectorRegister d, VectorRegister a, VectorRegister b);
2212 inline void vadduhm( VectorRegister d, VectorRegister a, VectorRegister b);
2213 inline void vaddudm( VectorRegister d, VectorRegister a, VectorRegister b);
2214 inline void vaddubs( VectorRegister d, VectorRegister a, VectorRegister b);
2215 inline void vadduws( VectorRegister d, VectorRegister a, VectorRegister b);
2216 inline void vadduhs( VectorRegister d, VectorRegister a, VectorRegister b);
2217 inline void vaddfp( VectorRegister d, VectorRegister a, VectorRegister b);
2218 inline void vsubcuw( VectorRegister d, VectorRegister a, VectorRegister b);
2219 inline void vsubshs( VectorRegister d, VectorRegister a, VectorRegister b);
2220 inline void vsubsbs( VectorRegister d, VectorRegister a, VectorRegister b);
2221 inline void vsubsws( VectorRegister d, VectorRegister a, VectorRegister b);
2222 inline void vsububm( VectorRegister d, VectorRegister a, VectorRegister b);
2223 inline void vsubuwm( VectorRegister d, VectorRegister a, VectorRegister b);
2224 inline void vsubuhm( VectorRegister d, VectorRegister a, VectorRegister b);
2225 inline void vsubudm( VectorRegister d, VectorRegister a, VectorRegister b);
2226 inline void vsububs( VectorRegister d, VectorRegister a, VectorRegister b);
2227 inline void vsubuws( VectorRegister d, VectorRegister a, VectorRegister b);
2228 inline void vsubuhs( VectorRegister d, VectorRegister a, VectorRegister b);
2229 inline void vsubfp( VectorRegister d, VectorRegister a, VectorRegister b);
2230 inline void vmulesb( VectorRegister d, VectorRegister a, VectorRegister b);
2231 inline void vmuleub( VectorRegister d, VectorRegister a, VectorRegister b);
2232 inline void vmulesh( VectorRegister d, VectorRegister a, VectorRegister b);
2233 inline void vmuleuh( VectorRegister d, VectorRegister a, VectorRegister b);
2234 inline void vmulosb( VectorRegister d, VectorRegister a, VectorRegister b);
2235 inline void vmuloub( VectorRegister d, VectorRegister a, VectorRegister b);
2236 inline void vmulosh( VectorRegister d, VectorRegister a, VectorRegister b);
2237 inline void vmulosw( VectorRegister d, VectorRegister a, VectorRegister b);
2238 inline void vmulouh( VectorRegister d, VectorRegister a, VectorRegister b);
2239 inline void vmuluwm( VectorRegister d, VectorRegister a, VectorRegister b);
2240 inline void vmhaddshs(VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
2241 inline void vmhraddshs(VectorRegister d,VectorRegister a, VectorRegister b, VectorRegister c);
2242 inline void vmladduhm(VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
2243 inline void vmsubuhm( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
2244 inline void vmsummbm( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
2245 inline void vmsumshm( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
2246 inline void vmsumshs( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
2247 inline void vmsumuhm( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
2248 inline void vmsumuhs( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
2249 inline void vmaddfp( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
2250 inline void vsumsws( VectorRegister d, VectorRegister a, VectorRegister b);
2251 inline void vsum2sws( VectorRegister d, VectorRegister a, VectorRegister b);
2252 inline void vsum4sbs( VectorRegister d, VectorRegister a, VectorRegister b);
2253 inline void vsum4ubs( VectorRegister d, VectorRegister a, VectorRegister b);
2254 inline void vsum4shs( VectorRegister d, VectorRegister a, VectorRegister b);
2255 inline void vavgsb( VectorRegister d, VectorRegister a, VectorRegister b);
2256 inline void vavgsw( VectorRegister d, VectorRegister a, VectorRegister b);
2257 inline void vavgsh( VectorRegister d, VectorRegister a, VectorRegister b);
2258 inline void vavgub( VectorRegister d, VectorRegister a, VectorRegister b);
2259 inline void vavguw( VectorRegister d, VectorRegister a, VectorRegister b);
2260 inline void vavguh( VectorRegister d, VectorRegister a, VectorRegister b);
2261 inline void vmaxsb( VectorRegister d, VectorRegister a, VectorRegister b);
2262 inline void vmaxsw( VectorRegister d, VectorRegister a, VectorRegister b);
2263 inline void vmaxsh( VectorRegister d, VectorRegister a, VectorRegister b);
2264 inline void vmaxub( VectorRegister d, VectorRegister a, VectorRegister b);
2265 inline void vmaxuw( VectorRegister d, VectorRegister a, VectorRegister b);
2266 inline void vmaxuh( VectorRegister d, VectorRegister a, VectorRegister b);
2267 inline void vminsb( VectorRegister d, VectorRegister a, VectorRegister b);
2268 inline void vminsw( VectorRegister d, VectorRegister a, VectorRegister b);
2269 inline void vminsh( VectorRegister d, VectorRegister a, VectorRegister b);
2270 inline void vminub( VectorRegister d, VectorRegister a, VectorRegister b);
2271 inline void vminuw( VectorRegister d, VectorRegister a, VectorRegister b);
2272 inline void vminuh( VectorRegister d, VectorRegister a, VectorRegister b);
2273 inline void vcmpequb( VectorRegister d, VectorRegister a, VectorRegister b);
2274 inline void vcmpequh( VectorRegister d, VectorRegister a, VectorRegister b);
2275 inline void vcmpequw( VectorRegister d, VectorRegister a, VectorRegister b);
2276 inline void vcmpgtsh( VectorRegister d, VectorRegister a, VectorRegister b);
2277 inline void vcmpgtsb( VectorRegister d, VectorRegister a, VectorRegister b);
2278 inline void vcmpgtsw( VectorRegister d, VectorRegister a, VectorRegister b);
2279 inline void vcmpgtub( VectorRegister d, VectorRegister a, VectorRegister b);
2280 inline void vcmpgtuh( VectorRegister d, VectorRegister a, VectorRegister b);
2281 inline void vcmpgtuw( VectorRegister d, VectorRegister a, VectorRegister b);
2282 inline void vcmpequb_(VectorRegister d, VectorRegister a, VectorRegister b);
2283 inline void vcmpequh_(VectorRegister d, VectorRegister a, VectorRegister b);
2284 inline void vcmpequw_(VectorRegister d, VectorRegister a, VectorRegister b);
2285 inline void vcmpgtsh_(VectorRegister d, VectorRegister a, VectorRegister b);
2286 inline void vcmpgtsb_(VectorRegister d, VectorRegister a, VectorRegister b);
2287 inline void vcmpgtsw_(VectorRegister d, VectorRegister a, VectorRegister b);
2288 inline void vcmpgtub_(VectorRegister d, VectorRegister a, VectorRegister b);
2289 inline void vcmpgtuh_(VectorRegister d, VectorRegister a, VectorRegister b);
2290 inline void vcmpgtuw_(VectorRegister d, VectorRegister a, VectorRegister b);
2291 inline void vand( VectorRegister d, VectorRegister a, VectorRegister b);
2292 inline void vandc( VectorRegister d, VectorRegister a, VectorRegister b);
2293 inline void vnor( VectorRegister d, VectorRegister a, VectorRegister b);
2294 inline void vor( VectorRegister d, VectorRegister a, VectorRegister b);
2295 inline void vmr( VectorRegister d, VectorRegister a);
2296 inline void vxor( VectorRegister d, VectorRegister a, VectorRegister b);
2297 inline void vrld( VectorRegister d, VectorRegister a, VectorRegister b);
2298 inline void vrlb( VectorRegister d, VectorRegister a, VectorRegister b);
2299 inline void vrlw( VectorRegister d, VectorRegister a, VectorRegister b);
2300 inline void vrlh( VectorRegister d, VectorRegister a, VectorRegister b);
2301 inline void vslb( VectorRegister d, VectorRegister a, VectorRegister b);
2302 inline void vskw( VectorRegister d, VectorRegister a, VectorRegister b);
2303 inline void vslh( VectorRegister d, VectorRegister a, VectorRegister b);
2304 inline void vsrb( VectorRegister d, VectorRegister a, VectorRegister b);
2305 inline void vsrw( VectorRegister d, VectorRegister a, VectorRegister b);
2306 inline void vsrh( VectorRegister d, VectorRegister a, VectorRegister b);
2307 inline void vsrab( VectorRegister d, VectorRegister a, VectorRegister b);
2308 inline void vsraw( VectorRegister d, VectorRegister a, VectorRegister b);
2309 inline void vsrah( VectorRegister d, VectorRegister a, VectorRegister b);
2310 inline void vpopcntb( VectorRegister d, VectorRegister b);
2311 inline void vpopcnth( VectorRegister d, VectorRegister b);
2312 inline void vpopcntw( VectorRegister d, VectorRegister b);
2313 inline void vpopcntd( VectorRegister d, VectorRegister b);
2314 // Vector Floating-Point not implemented yet
2315 inline void mtvscr( VectorRegister b);
2316 inline void mfvscr( VectorRegister d);
2317
2318 // Vector-Scalar (VSX) instructions.
2319 inline void lxv( VectorSRegister d, int si16, Register a);
2320 inline void stxv( VectorSRegister d, int si16, Register a);
2321 inline void lxvl( VectorSRegister d, Register a, Register b);
2322 inline void stxvl( VectorSRegister d, Register a, Register b);
2323 inline void lxvd2x( VectorSRegister d, Register a);
2324 inline void lxvd2x( VectorSRegister d, Register a, Register b);
2325 inline void stxvd2x( VectorSRegister d, Register a);
2326 inline void stxvd2x( VectorSRegister d, Register a, Register b);
2327 inline void mtvrwz( VectorRegister d, Register a);
2328 inline void mfvrwz( Register a, VectorRegister d);
2329 inline void mtvrd( VectorRegister d, Register a);
2330 inline void mfvrd( Register a, VectorRegister d);
2331 inline void xxperm( VectorSRegister d, VectorSRegister a, VectorSRegister b);
2332 inline void xxpermx( VectorSRegister d, VectorSRegister a, VectorSRegister b, VectorSRegister c, int ui3);
2333 inline void xxpermdi( VectorSRegister d, VectorSRegister a, VectorSRegister b, int dm);
2334 inline void xxmrghw( VectorSRegister d, VectorSRegister a, VectorSRegister b);
2335 inline void xxmrglw( VectorSRegister d, VectorSRegister a, VectorSRegister b);
2336 inline void mtvsrd( VectorSRegister d, Register a);
2337 inline void mfvsrd( Register d, VectorSRegister a);
2338 inline void mtvsrdd( VectorSRegister d, Register a, Register b);
2339 inline void mtvsrwz( VectorSRegister d, Register a);
2340 inline void mfvsrwz( Register d, VectorSRegister a);
2341 inline void xxspltw( VectorSRegister d, VectorSRegister b, int ui2);
2342 inline void xxlor( VectorSRegister d, VectorSRegister a, VectorSRegister b);
2343 inline void xxlxor( VectorSRegister d, VectorSRegister a, VectorSRegister b);
2344 inline void xxleqv( VectorSRegister d, VectorSRegister a, VectorSRegister b);
2345 inline void xxbrd( VectorSRegister d, VectorSRegister b);
2346 inline void xxbrw( VectorSRegister d, VectorSRegister b);
2347 inline void xxland( VectorSRegister d, VectorSRegister a, VectorSRegister b);
2348 inline void xxsel( VectorSRegister d, VectorSRegister a, VectorSRegister b, VectorSRegister c);
2349 inline void xxspltib( VectorSRegister d, int ui8);
2350 inline void xvdivsp( VectorSRegister d, VectorSRegister a, VectorSRegister b);
2351 inline void xvdivdp( VectorSRegister d, VectorSRegister a, VectorSRegister b);
2352 inline void xvabssp( VectorSRegister d, VectorSRegister b);
2353 inline void xvabsdp( VectorSRegister d, VectorSRegister b);
2354 inline void xvnegsp( VectorSRegister d, VectorSRegister b);
2355 inline void xvnegdp( VectorSRegister d, VectorSRegister b);
2356 inline void xvsqrtsp( VectorSRegister d, VectorSRegister b);
2357 inline void xvsqrtdp( VectorSRegister d, VectorSRegister b);
2358 inline void xscvdpspn(VectorSRegister d, VectorSRegister b);
2359 inline void xvadddp( VectorSRegister d, VectorSRegister a, VectorSRegister b);
2360 inline void xvsubdp( VectorSRegister d, VectorSRegister a, VectorSRegister b);
2361 inline void xvmulsp( VectorSRegister d, VectorSRegister a, VectorSRegister b);
2362 inline void xvmuldp( VectorSRegister d, VectorSRegister a, VectorSRegister b);
2363 inline void xvmaddasp(VectorSRegister d, VectorSRegister a, VectorSRegister b);
2364 inline void xvmaddadp(VectorSRegister d, VectorSRegister a, VectorSRegister b);
2365 inline void xvmsubasp(VectorSRegister d, VectorSRegister a, VectorSRegister b);
2366 inline void xvmsubadp(VectorSRegister d, VectorSRegister a, VectorSRegister b);
2367 inline void xvnmsubasp(VectorSRegister d, VectorSRegister a, VectorSRegister b);
2368 inline void xvnmsubadp(VectorSRegister d, VectorSRegister a, VectorSRegister b);
2369 inline void xvrdpi( VectorSRegister d, VectorSRegister b);
2370 inline void xvrdpic( VectorSRegister d, VectorSRegister b);
2371 inline void xvrdpim( VectorSRegister d, VectorSRegister b);
2372 inline void xvrdpip( VectorSRegister d, VectorSRegister b);
2373
2374 // VSX Extended Mnemonics
2375 inline void xxspltd( VectorSRegister d, VectorSRegister a, int x);
2376 inline void xxmrghd( VectorSRegister d, VectorSRegister a, VectorSRegister b);
2377 inline void xxmrgld( VectorSRegister d, VectorSRegister a, VectorSRegister b);
2378 inline void xxswapd( VectorSRegister d, VectorSRegister a);
2379
2380 // Vector-Scalar (VSX) instructions.
2381 inline void mtfprd( FloatRegister d, Register a);
2382 inline void mtfprwa( FloatRegister d, Register a);
2383 inline void mffprd( Register a, FloatRegister d);
2384
2385 // Deliver A Random Number (introduced with POWER9)
2386 inline void darn( Register d, int l = 1 /*L=CRN*/);
2387
2388 // AES (introduced with Power 8)
2389 inline void vcipher( VectorRegister d, VectorRegister a, VectorRegister b);
2390 inline void vcipherlast( VectorRegister d, VectorRegister a, VectorRegister b);
2391 inline void vncipher( VectorRegister d, VectorRegister a, VectorRegister b);
2392 inline void vncipherlast(VectorRegister d, VectorRegister a, VectorRegister b);
2393 inline void vsbox( VectorRegister d, VectorRegister a);
2394
2395 // SHA (introduced with Power 8)
2396 inline void vshasigmad(VectorRegister d, VectorRegister a, bool st, int six);
2397 inline void vshasigmaw(VectorRegister d, VectorRegister a, bool st, int six);
2398
2399 // Vector Binary Polynomial Multiplication (introduced with Power 8)
2400 inline void vpmsumb( VectorRegister d, VectorRegister a, VectorRegister b);
2401 inline void vpmsumd( VectorRegister d, VectorRegister a, VectorRegister b);
2402 inline void vpmsumh( VectorRegister d, VectorRegister a, VectorRegister b);
2403 inline void vpmsumw( VectorRegister d, VectorRegister a, VectorRegister b);
2404
2405 // Vector Permute and Xor (introduced with Power 8)
2406 inline void vpermxor( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
2407
2408 // The following encoders use r0 as second operand. These instructions
2409 // read r0 as '0'.
2410 inline void lwzx( Register d, Register s2);
2411 inline void lwz( Register d, int si16);
2412 inline void lwax( Register d, Register s2);
2413 inline void lwa( Register d, int si16);
2414 inline void lwbrx(Register d, Register s2);
2415 inline void lhzx( Register d, Register s2);
2416 inline void lhz( Register d, int si16);
2417 inline void lhax( Register d, Register s2);
2418 inline void lha( Register d, int si16);
2419 inline void lhbrx(Register d, Register s2);
2420 inline void lbzx( Register d, Register s2);
2421 inline void lbz( Register d, int si16);
2422 inline void ldx( Register d, Register s2);
2423 inline void ld( Register d, int si16);
2424 inline void ld( Register d, ByteSize si16);
2425 inline void ldbrx(Register d, Register s2);
2426 inline void stwx( Register d, Register s2);
2427 inline void stw( Register d, int si16);
2428 inline void stwbrx( Register d, Register s2);
2429 inline void sthx( Register d, Register s2);
2430 inline void sth( Register d, int si16);
2431 inline void sthbrx( Register d, Register s2);
2432 inline void stbx( Register d, Register s2);
2433 inline void stb( Register d, int si16);
2434 inline void stdx( Register d, Register s2);
2435 inline void std( Register d, int si16);
2436 inline void stdbrx( Register d, Register s2);
2437
2438 // PPC 2, section 3.2.1 Instruction Cache Instructions
2439 inline void icbi( Register s2);
2440 // PPC 2, section 3.2.2 Data Cache Instructions
2441 //inlinevoid dcba( Register s2); // Instruction for embedded processor only.
2442 inline void dcbz( Register s2);
2443 inline void dcbst( Register s2);
2444 inline void dcbf( Register s2);
2445 // dcache read hint
2446 inline void dcbt( Register s2);
2447 inline void dcbtct( Register s2, int ct);
2448 inline void dcbtds( Register s2, int ds);
2449 // dcache write hint
2450 inline void dcbtst( Register s2);
2451 inline void dcbtstct(Register s2, int ct);
2452
2453 // Atomics: use ra0mem to disallow R0 as base.
2454 inline void lbarx_unchecked(Register d, Register b, int eh1);
2455 inline void lharx_unchecked(Register d, Register b, int eh1);
2456 inline void lwarx_unchecked(Register d, Register b, int eh1);
2457 inline void ldarx_unchecked(Register d, Register b, int eh1);
2458 inline void lqarx_unchecked(Register d, Register b, int eh1);
2459 inline void lbarx( Register d, Register b, bool hint_exclusive_access);
2460 inline void lharx( Register d, Register b, bool hint_exclusive_access);
2461 inline void lwarx( Register d, Register b, bool hint_exclusive_access);
2462 inline void ldarx( Register d, Register b, bool hint_exclusive_access);
2463 inline void lqarx( Register d, Register b, bool hint_exclusive_access);
2464 inline void stbcx_(Register s, Register b);
2465 inline void sthcx_(Register s, Register b);
2466 inline void stwcx_(Register s, Register b);
2467 inline void stdcx_(Register s, Register b);
2468 inline void stqcx_(Register s, Register b);
2469 inline void lfs( FloatRegister d, int si16);
2470 inline void lfsx( FloatRegister d, Register b);
2471 inline void lfd( FloatRegister d, int si16);
2472 inline void lfdx( FloatRegister d, Register b);
2473 inline void stfs( FloatRegister s, int si16);
2474 inline void stfsx( FloatRegister s, Register b);
2475 inline void stfd( FloatRegister s, int si16);
2476 inline void stfdx( FloatRegister s, Register b);
2477 inline void lvebx( VectorRegister d, Register s2);
2478 inline void lvehx( VectorRegister d, Register s2);
2479 inline void lvewx( VectorRegister d, Register s2);
2480 inline void lvx( VectorRegister d, Register s2);
2481 inline void lvxl( VectorRegister d, Register s2);
2482 inline void stvebx(VectorRegister d, Register s2);
2483 inline void stvehx(VectorRegister d, Register s2);
2484 inline void stvewx(VectorRegister d, Register s2);
2485 inline void stvx( VectorRegister d, Register s2);
2486 inline void stvxl( VectorRegister d, Register s2);
2487 inline void lvsl( VectorRegister d, Register s2);
2488 inline void lvsr( VectorRegister d, Register s2);
2489
2490 // Endianness specific concatenation of 2 loaded vectors.
2491 inline void load_perm(VectorRegister perm, Register addr);
2492 inline void vec_perm(VectorRegister first_dest, VectorRegister second, VectorRegister perm);
2493 inline void vec_perm(VectorRegister dest, VectorRegister first, VectorRegister second, VectorRegister perm);
2494
2495 // RegisterOrConstant versions.
2496 // These emitters choose between the versions using two registers and
2497 // those with register and immediate, depending on the content of roc.
2498 // If the constant is not encodable as immediate, instructions to
2499 // load the constant are emitted beforehand. Store instructions need a
2500 // tmp reg if the constant is not encodable as immediate.
2501 // Size unpredictable.
2502 void ld( Register d, RegisterOrConstant roc, Register s1 = noreg);
2503 void lwa( Register d, RegisterOrConstant roc, Register s1 = noreg);
2504 void lwz( Register d, RegisterOrConstant roc, Register s1 = noreg);
2505 void lha( Register d, RegisterOrConstant roc, Register s1 = noreg);
2506 void lhz( Register d, RegisterOrConstant roc, Register s1 = noreg);
2507 void lbz( Register d, RegisterOrConstant roc, Register s1 = noreg);
2508 void std( Register d, RegisterOrConstant roc, Register s1 = noreg, Register tmp = noreg);
2509 void stw( Register d, RegisterOrConstant roc, Register s1 = noreg, Register tmp = noreg);
2510 void sth( Register d, RegisterOrConstant roc, Register s1 = noreg, Register tmp = noreg);
2511 void stb( Register d, RegisterOrConstant roc, Register s1 = noreg, Register tmp = noreg);
2512 void add( Register d, RegisterOrConstant roc, Register s1);
2513 void subf(Register d, RegisterOrConstant roc, Register s1);
2514 void cmpd(ConditionRegister d, RegisterOrConstant roc, Register s1);
2515 // Load pointer d from s1+roc.
2516 void ld_ptr(Register d, RegisterOrConstant roc, Register s1 = noreg) { ld(d, roc, s1); }
2517
2518 // Emit several instructions to load a 64 bit constant. This issues a fixed
2519 // instruction pattern so that the constant can be patched later on.
2520 enum {
2521 load_const_size = 5 * BytesPerInstWord
2522 };
2523 void load_const(Register d, long a, Register tmp = noreg);
2524 inline void load_const(Register d, void* a, Register tmp = noreg);
2525 inline void load_const(Register d, Label& L, Register tmp = noreg);
2526 inline void load_const(Register d, AddressLiteral& a, Register tmp = noreg);
2527 inline void load_const32(Register d, int i); // load signed int (patchable)
2528
2529 // Load a 64 bit constant, optimized, not identifiable.
2530 // Tmp can be used to increase ILP. Set return_simm16_rest = true to get a
2531 // 16 bit immediate offset. This is useful if the offset can be encoded in
2532 // a succeeding instruction.
2533 int load_const_optimized(Register d, long a, Register tmp = noreg, bool return_simm16_rest = false);
2534 inline int load_const_optimized(Register d, void* a, Register tmp = noreg, bool return_simm16_rest = false) {
2535 return load_const_optimized(d, (long)(unsigned long)a, tmp, return_simm16_rest);
2536 }
2537
2538 // If return_simm16_rest, the return value needs to get added afterwards.
2539 int add_const_optimized(Register d, Register s, long x, Register tmp = R0, bool return_simm16_rest = false);
2540 inline int add_const_optimized(Register d, Register s, void* a, Register tmp = R0, bool return_simm16_rest = false) {
2541 return add_const_optimized(d, s, (long)(unsigned long)a, tmp, return_simm16_rest);
2542 }
2543
2544 // If return_simm16_rest, the return value needs to get added afterwards.
2545 inline int sub_const_optimized(Register d, Register s, long x, Register tmp = R0, bool return_simm16_rest = false) {
2546 return add_const_optimized(d, s, -x, tmp, return_simm16_rest);
2547 }
2548 inline int sub_const_optimized(Register d, Register s, void* a, Register tmp = R0, bool return_simm16_rest = false) {
2549 return sub_const_optimized(d, s, (long)(unsigned long)a, tmp, return_simm16_rest);
2550 }
2551
2552 // Creation
2553 Assembler(CodeBuffer* code) : AbstractAssembler(code) {
2554 #ifdef CHECK_DELAY
2555 delay_state = no_delay;
2556 #endif
2557 }
2558
2559 // Testing
2560 #ifndef PRODUCT
2561 void test_asm();
2562 #endif
2563 };
2564
2565
2566 #endif // CPU_PPC_ASSEMBLER_PPC_HPP
--- EOF ---