320
321 ISEL_OPCODE = (31u << OPCODE_SHIFT | 15u << 1),
322
323 // Special purpose registers
324 MTSPR_OPCODE = (31u << OPCODE_SHIFT | 467u << 1),
325 MFSPR_OPCODE = (31u << OPCODE_SHIFT | 339u << 1),
326
327 MTXER_OPCODE = (MTSPR_OPCODE | 1 << SPR_0_4_SHIFT),
328 MFXER_OPCODE = (MFSPR_OPCODE | 1 << SPR_0_4_SHIFT),
329
330 MTDSCR_OPCODE = (MTSPR_OPCODE | 3 << SPR_0_4_SHIFT),
331 MFDSCR_OPCODE = (MFSPR_OPCODE | 3 << SPR_0_4_SHIFT),
332
333 MTLR_OPCODE = (MTSPR_OPCODE | 8 << SPR_0_4_SHIFT),
334 MFLR_OPCODE = (MFSPR_OPCODE | 8 << SPR_0_4_SHIFT),
335
336 MTCTR_OPCODE = (MTSPR_OPCODE | 9 << SPR_0_4_SHIFT),
337 MFCTR_OPCODE = (MFSPR_OPCODE | 9 << SPR_0_4_SHIFT),
338
339 // Attention: Higher and lower half are inserted in reversed order.
340 MTTFHAR_OPCODE = (MTSPR_OPCODE | 4 << SPR_5_9_SHIFT | 0 << SPR_0_4_SHIFT),
341 MFTFHAR_OPCODE = (MFSPR_OPCODE | 4 << SPR_5_9_SHIFT | 0 << SPR_0_4_SHIFT),
342 MTTFIAR_OPCODE = (MTSPR_OPCODE | 4 << SPR_5_9_SHIFT | 1 << SPR_0_4_SHIFT),
343 MFTFIAR_OPCODE = (MFSPR_OPCODE | 4 << SPR_5_9_SHIFT | 1 << SPR_0_4_SHIFT),
344 MTTEXASR_OPCODE = (MTSPR_OPCODE | 4 << SPR_5_9_SHIFT | 2 << SPR_0_4_SHIFT),
345 MFTEXASR_OPCODE = (MFSPR_OPCODE | 4 << SPR_5_9_SHIFT | 2 << SPR_0_4_SHIFT),
346 MTTEXASRU_OPCODE = (MTSPR_OPCODE | 4 << SPR_5_9_SHIFT | 3 << SPR_0_4_SHIFT),
347 MFTEXASRU_OPCODE = (MFSPR_OPCODE | 4 << SPR_5_9_SHIFT | 3 << SPR_0_4_SHIFT),
348
349 MTVRSAVE_OPCODE = (MTSPR_OPCODE | 8 << SPR_5_9_SHIFT | 0 << SPR_0_4_SHIFT),
350 MFVRSAVE_OPCODE = (MFSPR_OPCODE | 8 << SPR_5_9_SHIFT | 0 << SPR_0_4_SHIFT),
351
352 MFTB_OPCODE = (MFSPR_OPCODE | 8 << SPR_5_9_SHIFT | 12 << SPR_0_4_SHIFT),
353
354 MTCRF_OPCODE = (31u << OPCODE_SHIFT | 144u << 1),
355 MFCR_OPCODE = (31u << OPCODE_SHIFT | 19u << 1),
356 MCRF_OPCODE = (19u << OPCODE_SHIFT | 0u << 1),
357 MCRXRX_OPCODE = (31u << OPCODE_SHIFT | 576u << 1),
358 SETB_OPCODE = (31u << OPCODE_SHIFT | 128u << 1),
359
360 SETBC_OPCODE = (31u << OPCODE_SHIFT | 384u << 1),
361 SETNBC_OPCODE = (31u << OPCODE_SHIFT | 448u << 1),
362
363 // condition register logic instructions
364 CRAND_OPCODE = (19u << OPCODE_SHIFT | 257u << 1),
365 CRNAND_OPCODE = (19u << OPCODE_SHIFT | 225u << 1),
366 CROR_OPCODE = (19u << OPCODE_SHIFT | 449u << 1),
367 CRXOR_OPCODE = (19u << OPCODE_SHIFT | 193u << 1),
368 CRNOR_OPCODE = (19u << OPCODE_SHIFT | 33u << 1),
749 // AES (introduced with Power 8)
750 VCIPHER_OPCODE = (4u << OPCODE_SHIFT | 1288u),
751 VCIPHERLAST_OPCODE = (4u << OPCODE_SHIFT | 1289u),
752 VNCIPHER_OPCODE = (4u << OPCODE_SHIFT | 1352u),
753 VNCIPHERLAST_OPCODE = (4u << OPCODE_SHIFT | 1353u),
754 VSBOX_OPCODE = (4u << OPCODE_SHIFT | 1480u),
755
756 // SHA (introduced with Power 8)
757 VSHASIGMAD_OPCODE = (4u << OPCODE_SHIFT | 1730u),
758 VSHASIGMAW_OPCODE = (4u << OPCODE_SHIFT | 1666u),
759
760 // Vector Binary Polynomial Multiplication (introduced with Power 8)
761 VPMSUMB_OPCODE = (4u << OPCODE_SHIFT | 1032u),
762 VPMSUMD_OPCODE = (4u << OPCODE_SHIFT | 1224u),
763 VPMSUMH_OPCODE = (4u << OPCODE_SHIFT | 1096u),
764 VPMSUMW_OPCODE = (4u << OPCODE_SHIFT | 1160u),
765
766 // Vector Permute and Xor (introduced with Power 8)
767 VPERMXOR_OPCODE = (4u << OPCODE_SHIFT | 45u),
768
769 // Transactional Memory instructions (introduced with Power 8)
770 TBEGIN_OPCODE = (31u << OPCODE_SHIFT | 654u << 1),
771 TEND_OPCODE = (31u << OPCODE_SHIFT | 686u << 1),
772 TABORT_OPCODE = (31u << OPCODE_SHIFT | 910u << 1),
773 TABORTWC_OPCODE = (31u << OPCODE_SHIFT | 782u << 1),
774 TABORTWCI_OPCODE = (31u << OPCODE_SHIFT | 846u << 1),
775 TABORTDC_OPCODE = (31u << OPCODE_SHIFT | 814u << 1),
776 TABORTDCI_OPCODE = (31u << OPCODE_SHIFT | 878u << 1),
777 TSR_OPCODE = (31u << OPCODE_SHIFT | 750u << 1),
778 TCHECK_OPCODE = (31u << OPCODE_SHIFT | 718u << 1),
779
780 // Icache and dcache related instructions
781 DCBA_OPCODE = (31u << OPCODE_SHIFT | 758u << 1),
782 DCBZ_OPCODE = (31u << OPCODE_SHIFT | 1014u << 1),
783 DCBST_OPCODE = (31u << OPCODE_SHIFT | 54u << 1),
784 DCBF_OPCODE = (31u << OPCODE_SHIFT | 86u << 1),
785
786 DCBT_OPCODE = (31u << OPCODE_SHIFT | 278u << 1),
787 DCBTST_OPCODE = (31u << OPCODE_SHIFT | 246u << 1),
788 ICBI_OPCODE = (31u << OPCODE_SHIFT | 982u << 1),
789
790 // Instruction synchronization
791 ISYNC_OPCODE = (19u << OPCODE_SHIFT | 150u << 1),
792 // Memory barriers
793 SYNC_OPCODE = (31u << OPCODE_SHIFT | 598u << 1),
794 EIEIO_OPCODE = (31u << OPCODE_SHIFT | 854u << 1),
795
796 // Wait instructions for polling.
797 WAIT_OPCODE = (31u << OPCODE_SHIFT | 62u << 1),
798
799 // Trap instructions
1797
1798 // >= Power10
1799 inline void setbc( Register d, int biint);
1800 inline void setbc( Register d, ConditionRegister cr, Condition cc);
1801 inline void setnbc(Register d, int biint);
1802 inline void setnbc(Register d, ConditionRegister cr, Condition cc);
1803
1804 // Special purpose registers
1805 // Exception Register
1806 inline void mtxer(Register s1);
1807 inline void mfxer(Register d);
1808 // Vector Register Save Register
1809 inline void mtvrsave(Register s1);
1810 inline void mfvrsave(Register d);
1811 // Timebase
1812 inline void mftb(Register d);
1813 // Introduced with Power 8:
1814 // Data Stream Control Register
1815 inline void mtdscr(Register s1);
1816 inline void mfdscr(Register d );
1817 // Transactional Memory Registers
1818 inline void mftfhar(Register d);
1819 inline void mftfiar(Register d);
1820 inline void mftexasr(Register d);
1821 inline void mftexasru(Register d);
1822
1823 // TEXASR bit description
1824 enum transaction_failure_reason {
1825 // Upper half (TEXASRU):
1826 tm_failure_code = 0, // The Failure Code is copied from tabort or treclaim operand.
1827 tm_failure_persistent = 7, // The failure is likely to recur on each execution.
1828 tm_disallowed = 8, // The instruction is not permitted.
1829 tm_nesting_of = 9, // The maximum transaction level was exceeded.
1830 tm_footprint_of = 10, // The tracking limit for transactional storage accesses was exceeded.
1831 tm_self_induced_cf = 11, // A self-induced conflict occurred in Suspended state.
1832 tm_non_trans_cf = 12, // A conflict occurred with a non-transactional access by another processor.
1833 tm_trans_cf = 13, // A conflict occurred with another transaction.
1834 tm_translation_cf = 14, // A conflict occurred with a TLB invalidation.
1835 tm_inst_fetch_cf = 16, // An instruction fetch was performed from a block that was previously written transactionally.
1836 tm_tabort = 31, // Termination was caused by the execution of an abort instruction.
1837 // Lower half:
1838 tm_suspended = 32, // Failure was recorded in Suspended state.
1839 tm_failure_summary = 36, // Failure has been detected and recorded.
1840 tm_tfiar_exact = 37, // Value in the TFIAR is exact.
1841 tm_rot = 38, // Rollback-only transaction.
1842 tm_transaction_level = 52, // Transaction level (nesting depth + 1).
1843 };
1844
1845 // PPC 1, section 2.4.1 Branch Instructions
1846 inline void b( address a, relocInfo::relocType rt = relocInfo::none);
1847 inline void b( Label& L);
1848 inline void bl( address a, relocInfo::relocType rt = relocInfo::none);
1849 inline void bl( Label& L);
1850 inline void bc( int boint, int biint, address a, relocInfo::relocType rt = relocInfo::none);
1851 inline void bc( int boint, int biint, Label& L);
1852 inline void bcl(int boint, int biint, address a, relocInfo::relocType rt = relocInfo::none);
1853 inline void bcl(int boint, int biint, Label& L);
1854
1855 inline void bclr( int boint, int biint, int bhint, relocInfo::relocType rt = relocInfo::none);
1856 inline void bclrl( int boint, int biint, int bhint, relocInfo::relocType rt = relocInfo::none);
1857 inline void bcctr( int boint, int biint, int bhint = bhintbhBCCTRisNotReturnButSame,
1858 relocInfo::relocType rt = relocInfo::none);
1859 inline void bcctrl(int boint, int biint, int bhint = bhintbhBCLRisReturn,
1860 relocInfo::relocType rt = relocInfo::none);
1861
1862 // helper function for b, bcxx
1863 inline bool is_within_range_of_b(address a, address pc);
2435 // AES (introduced with Power 8)
2436 inline void vcipher( VectorRegister d, VectorRegister a, VectorRegister b);
2437 inline void vcipherlast( VectorRegister d, VectorRegister a, VectorRegister b);
2438 inline void vncipher( VectorRegister d, VectorRegister a, VectorRegister b);
2439 inline void vncipherlast(VectorRegister d, VectorRegister a, VectorRegister b);
2440 inline void vsbox( VectorRegister d, VectorRegister a);
2441
2442 // SHA (introduced with Power 8)
2443 inline void vshasigmad(VectorRegister d, VectorRegister a, bool st, int six);
2444 inline void vshasigmaw(VectorRegister d, VectorRegister a, bool st, int six);
2445
2446 // Vector Binary Polynomial Multiplication (introduced with Power 8)
2447 inline void vpmsumb( VectorRegister d, VectorRegister a, VectorRegister b);
2448 inline void vpmsumd( VectorRegister d, VectorRegister a, VectorRegister b);
2449 inline void vpmsumh( VectorRegister d, VectorRegister a, VectorRegister b);
2450 inline void vpmsumw( VectorRegister d, VectorRegister a, VectorRegister b);
2451
2452 // Vector Permute and Xor (introduced with Power 8)
2453 inline void vpermxor( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
2454
2455 // Transactional Memory instructions (introduced with Power 8)
2456 inline void tbegin_(); // R=0
2457 inline void tbeginrot_(); // R=1 Rollback-Only Transaction
2458 inline void tend_(); // A=0
2459 inline void tendall_(); // A=1
2460 inline void tabort_();
2461 inline void tabort_(Register a);
2462 inline void tabortwc_(int t, Register a, Register b);
2463 inline void tabortwci_(int t, Register a, int si);
2464 inline void tabortdc_(int t, Register a, Register b);
2465 inline void tabortdci_(int t, Register a, int si);
2466 inline void tsuspend_(); // tsr with L=0
2467 inline void tresume_(); // tsr with L=1
2468 inline void tcheck(int f);
2469
2470 static bool is_tbegin(int x) {
2471 return TBEGIN_OPCODE == (x & (0x3f << OPCODE_SHIFT | 0x3ff << 1));
2472 }
2473
2474 // The following encoders use r0 as second operand. These instructions
2475 // read r0 as '0'.
2476 inline void lwzx( Register d, Register s2);
2477 inline void lwz( Register d, int si16);
2478 inline void lwax( Register d, Register s2);
2479 inline void lwa( Register d, int si16);
2480 inline void lwbrx(Register d, Register s2);
2481 inline void lhzx( Register d, Register s2);
2482 inline void lhz( Register d, int si16);
2483 inline void lhax( Register d, Register s2);
2484 inline void lha( Register d, int si16);
2485 inline void lhbrx(Register d, Register s2);
2486 inline void lbzx( Register d, Register s2);
2487 inline void lbz( Register d, int si16);
2488 inline void ldx( Register d, Register s2);
2489 inline void ld( Register d, int si16);
2490 inline void ld( Register d, ByteSize si16);
2491 inline void ldbrx(Register d, Register s2);
2492 inline void stwx( Register d, Register s2);
2493 inline void stw( Register d, int si16);
|
320
321 ISEL_OPCODE = (31u << OPCODE_SHIFT | 15u << 1),
322
323 // Special purpose registers
324 MTSPR_OPCODE = (31u << OPCODE_SHIFT | 467u << 1),
325 MFSPR_OPCODE = (31u << OPCODE_SHIFT | 339u << 1),
326
327 MTXER_OPCODE = (MTSPR_OPCODE | 1 << SPR_0_4_SHIFT),
328 MFXER_OPCODE = (MFSPR_OPCODE | 1 << SPR_0_4_SHIFT),
329
330 MTDSCR_OPCODE = (MTSPR_OPCODE | 3 << SPR_0_4_SHIFT),
331 MFDSCR_OPCODE = (MFSPR_OPCODE | 3 << SPR_0_4_SHIFT),
332
333 MTLR_OPCODE = (MTSPR_OPCODE | 8 << SPR_0_4_SHIFT),
334 MFLR_OPCODE = (MFSPR_OPCODE | 8 << SPR_0_4_SHIFT),
335
336 MTCTR_OPCODE = (MTSPR_OPCODE | 9 << SPR_0_4_SHIFT),
337 MFCTR_OPCODE = (MFSPR_OPCODE | 9 << SPR_0_4_SHIFT),
338
339 // Attention: Higher and lower half are inserted in reversed order.
340 MTVRSAVE_OPCODE = (MTSPR_OPCODE | 8 << SPR_5_9_SHIFT | 0 << SPR_0_4_SHIFT),
341 MFVRSAVE_OPCODE = (MFSPR_OPCODE | 8 << SPR_5_9_SHIFT | 0 << SPR_0_4_SHIFT),
342
343 MFTB_OPCODE = (MFSPR_OPCODE | 8 << SPR_5_9_SHIFT | 12 << SPR_0_4_SHIFT),
344
345 MTCRF_OPCODE = (31u << OPCODE_SHIFT | 144u << 1),
346 MFCR_OPCODE = (31u << OPCODE_SHIFT | 19u << 1),
347 MCRF_OPCODE = (19u << OPCODE_SHIFT | 0u << 1),
348 MCRXRX_OPCODE = (31u << OPCODE_SHIFT | 576u << 1),
349 SETB_OPCODE = (31u << OPCODE_SHIFT | 128u << 1),
350
351 SETBC_OPCODE = (31u << OPCODE_SHIFT | 384u << 1),
352 SETNBC_OPCODE = (31u << OPCODE_SHIFT | 448u << 1),
353
354 // condition register logic instructions
355 CRAND_OPCODE = (19u << OPCODE_SHIFT | 257u << 1),
356 CRNAND_OPCODE = (19u << OPCODE_SHIFT | 225u << 1),
357 CROR_OPCODE = (19u << OPCODE_SHIFT | 449u << 1),
358 CRXOR_OPCODE = (19u << OPCODE_SHIFT | 193u << 1),
359 CRNOR_OPCODE = (19u << OPCODE_SHIFT | 33u << 1),
740 // AES (introduced with Power 8)
741 VCIPHER_OPCODE = (4u << OPCODE_SHIFT | 1288u),
742 VCIPHERLAST_OPCODE = (4u << OPCODE_SHIFT | 1289u),
743 VNCIPHER_OPCODE = (4u << OPCODE_SHIFT | 1352u),
744 VNCIPHERLAST_OPCODE = (4u << OPCODE_SHIFT | 1353u),
745 VSBOX_OPCODE = (4u << OPCODE_SHIFT | 1480u),
746
747 // SHA (introduced with Power 8)
748 VSHASIGMAD_OPCODE = (4u << OPCODE_SHIFT | 1730u),
749 VSHASIGMAW_OPCODE = (4u << OPCODE_SHIFT | 1666u),
750
751 // Vector Binary Polynomial Multiplication (introduced with Power 8)
752 VPMSUMB_OPCODE = (4u << OPCODE_SHIFT | 1032u),
753 VPMSUMD_OPCODE = (4u << OPCODE_SHIFT | 1224u),
754 VPMSUMH_OPCODE = (4u << OPCODE_SHIFT | 1096u),
755 VPMSUMW_OPCODE = (4u << OPCODE_SHIFT | 1160u),
756
757 // Vector Permute and Xor (introduced with Power 8)
758 VPERMXOR_OPCODE = (4u << OPCODE_SHIFT | 45u),
759
760 // Icache and dcache related instructions
761 DCBA_OPCODE = (31u << OPCODE_SHIFT | 758u << 1),
762 DCBZ_OPCODE = (31u << OPCODE_SHIFT | 1014u << 1),
763 DCBST_OPCODE = (31u << OPCODE_SHIFT | 54u << 1),
764 DCBF_OPCODE = (31u << OPCODE_SHIFT | 86u << 1),
765
766 DCBT_OPCODE = (31u << OPCODE_SHIFT | 278u << 1),
767 DCBTST_OPCODE = (31u << OPCODE_SHIFT | 246u << 1),
768 ICBI_OPCODE = (31u << OPCODE_SHIFT | 982u << 1),
769
770 // Instruction synchronization
771 ISYNC_OPCODE = (19u << OPCODE_SHIFT | 150u << 1),
772 // Memory barriers
773 SYNC_OPCODE = (31u << OPCODE_SHIFT | 598u << 1),
774 EIEIO_OPCODE = (31u << OPCODE_SHIFT | 854u << 1),
775
776 // Wait instructions for polling.
777 WAIT_OPCODE = (31u << OPCODE_SHIFT | 62u << 1),
778
779 // Trap instructions
1777
1778 // >= Power10
1779 inline void setbc( Register d, int biint);
1780 inline void setbc( Register d, ConditionRegister cr, Condition cc);
1781 inline void setnbc(Register d, int biint);
1782 inline void setnbc(Register d, ConditionRegister cr, Condition cc);
1783
1784 // Special purpose registers
1785 // Exception Register
1786 inline void mtxer(Register s1);
1787 inline void mfxer(Register d);
1788 // Vector Register Save Register
1789 inline void mtvrsave(Register s1);
1790 inline void mfvrsave(Register d);
1791 // Timebase
1792 inline void mftb(Register d);
1793 // Introduced with Power 8:
1794 // Data Stream Control Register
1795 inline void mtdscr(Register s1);
1796 inline void mfdscr(Register d );
1797
1798 // PPC 1, section 2.4.1 Branch Instructions
1799 inline void b( address a, relocInfo::relocType rt = relocInfo::none);
1800 inline void b( Label& L);
1801 inline void bl( address a, relocInfo::relocType rt = relocInfo::none);
1802 inline void bl( Label& L);
1803 inline void bc( int boint, int biint, address a, relocInfo::relocType rt = relocInfo::none);
1804 inline void bc( int boint, int biint, Label& L);
1805 inline void bcl(int boint, int biint, address a, relocInfo::relocType rt = relocInfo::none);
1806 inline void bcl(int boint, int biint, Label& L);
1807
1808 inline void bclr( int boint, int biint, int bhint, relocInfo::relocType rt = relocInfo::none);
1809 inline void bclrl( int boint, int biint, int bhint, relocInfo::relocType rt = relocInfo::none);
1810 inline void bcctr( int boint, int biint, int bhint = bhintbhBCCTRisNotReturnButSame,
1811 relocInfo::relocType rt = relocInfo::none);
1812 inline void bcctrl(int boint, int biint, int bhint = bhintbhBCLRisReturn,
1813 relocInfo::relocType rt = relocInfo::none);
1814
1815 // helper function for b, bcxx
1816 inline bool is_within_range_of_b(address a, address pc);
2388 // AES (introduced with Power 8)
2389 inline void vcipher( VectorRegister d, VectorRegister a, VectorRegister b);
2390 inline void vcipherlast( VectorRegister d, VectorRegister a, VectorRegister b);
2391 inline void vncipher( VectorRegister d, VectorRegister a, VectorRegister b);
2392 inline void vncipherlast(VectorRegister d, VectorRegister a, VectorRegister b);
2393 inline void vsbox( VectorRegister d, VectorRegister a);
2394
2395 // SHA (introduced with Power 8)
2396 inline void vshasigmad(VectorRegister d, VectorRegister a, bool st, int six);
2397 inline void vshasigmaw(VectorRegister d, VectorRegister a, bool st, int six);
2398
2399 // Vector Binary Polynomial Multiplication (introduced with Power 8)
2400 inline void vpmsumb( VectorRegister d, VectorRegister a, VectorRegister b);
2401 inline void vpmsumd( VectorRegister d, VectorRegister a, VectorRegister b);
2402 inline void vpmsumh( VectorRegister d, VectorRegister a, VectorRegister b);
2403 inline void vpmsumw( VectorRegister d, VectorRegister a, VectorRegister b);
2404
2405 // Vector Permute and Xor (introduced with Power 8)
2406 inline void vpermxor( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
2407
2408 // The following encoders use r0 as second operand. These instructions
2409 // read r0 as '0'.
2410 inline void lwzx( Register d, Register s2);
2411 inline void lwz( Register d, int si16);
2412 inline void lwax( Register d, Register s2);
2413 inline void lwa( Register d, int si16);
2414 inline void lwbrx(Register d, Register s2);
2415 inline void lhzx( Register d, Register s2);
2416 inline void lhz( Register d, int si16);
2417 inline void lhax( Register d, Register s2);
2418 inline void lha( Register d, int si16);
2419 inline void lhbrx(Register d, Register s2);
2420 inline void lbzx( Register d, Register s2);
2421 inline void lbz( Register d, int si16);
2422 inline void ldx( Register d, Register s2);
2423 inline void ld( Register d, int si16);
2424 inline void ld( Register d, ByteSize si16);
2425 inline void ldbrx(Register d, Register s2);
2426 inline void stwx( Register d, Register s2);
2427 inline void stw( Register d, int si16);
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