1 /*
2 * Copyright (c) 2000, 2023, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2012, 2023 SAP SE. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "precompiled.hpp"
27 #include "asm/macroAssembler.inline.hpp"
28 #include "c1/c1_Compilation.hpp"
29 #include "c1/c1_LIRAssembler.hpp"
30 #include "c1/c1_MacroAssembler.hpp"
31 #include "c1/c1_Runtime1.hpp"
32 #include "c1/c1_ValueStack.hpp"
33 #include "ci/ciArrayKlass.hpp"
34 #include "ci/ciInstance.hpp"
35 #include "gc/shared/collectedHeap.hpp"
36 #include "memory/universe.hpp"
37 #include "nativeInst_ppc.hpp"
38 #include "oops/compressedOops.hpp"
39 #include "oops/objArrayKlass.hpp"
40 #include "runtime/frame.inline.hpp"
41 #include "runtime/os.inline.hpp"
42 #include "runtime/safepointMechanism.inline.hpp"
43 #include "runtime/sharedRuntime.hpp"
44 #include "runtime/stubRoutines.hpp"
45 #include "runtime/vm_version.hpp"
46 #include "utilities/macros.hpp"
47 #include "utilities/powerOfTwo.hpp"
48
49 #define __ _masm->
50
51
52 const ConditionRegister LIR_Assembler::BOOL_RESULT = CCR5;
53
54
55 bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
56 Unimplemented(); return false; // Currently not used on this platform.
57 }
58
59
60 LIR_Opr LIR_Assembler::receiverOpr() {
61 return FrameMap::R3_oop_opr;
62 }
63
64
65 LIR_Opr LIR_Assembler::osrBufferPointer() {
66 return FrameMap::R3_opr;
67 }
68
69
70 // This specifies the stack pointer decrement needed to build the frame.
71 int LIR_Assembler::initial_frame_size_in_bytes() const {
72 return in_bytes(frame_map()->framesize_in_bytes());
73 }
74
75
76 // Inline cache check: the inline cached class is in inline_cache_reg;
77 // we fetch the class of the receiver and compare it with the cached class.
78 // If they do not match we jump to slow case.
79 int LIR_Assembler::check_icache() {
80 int offset = __ offset();
81 __ inline_cache_check(R3_ARG1, R19_inline_cache_reg);
82 return offset;
83 }
84
85 void LIR_Assembler::clinit_barrier(ciMethod* method) {
86 assert(!method->holder()->is_not_initialized(), "initialization should have been started");
87
88 Label L_skip_barrier;
89 Register klass = R20;
90
91 metadata2reg(method->holder()->constant_encoding(), klass);
92 __ clinit_barrier(klass, R16_thread, &L_skip_barrier /*L_fast_path*/);
93
94 __ load_const_optimized(klass, SharedRuntime::get_handle_wrong_method_stub(), R0);
95 __ mtctr(klass);
96 __ bctr();
97
98 __ bind(L_skip_barrier);
99 }
100
101 void LIR_Assembler::osr_entry() {
102 // On-stack-replacement entry sequence:
103 //
104 // 1. Create a new compiled activation.
105 // 2. Initialize local variables in the compiled activation. The expression
106 // stack must be empty at the osr_bci; it is not initialized.
107 // 3. Jump to the continuation address in compiled code to resume execution.
108
109 // OSR entry point
110 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
111 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
112 ValueStack* entry_state = osr_entry->end()->state();
113 int number_of_locks = entry_state->locks_size();
114
115 // Create a frame for the compiled activation.
116 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
117
118 // OSR buffer is
119 //
120 // locals[nlocals-1..0]
121 // monitors[number_of_locks-1..0]
122 //
123 // Locals is a direct copy of the interpreter frame so in the osr buffer
124 // the first slot in the local array is the last local from the interpreter
125 // and the last slot is local[0] (receiver) from the interpreter.
126 //
127 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
128 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
129 // in the interpreter frame (the method lock if a sync method).
130
131 // Initialize monitors in the compiled activation.
132 // R3: pointer to osr buffer
133 //
134 // All other registers are dead at this point and the locals will be
135 // copied into place by code emitted in the IR.
136
137 Register OSR_buf = osrBufferPointer()->as_register();
138 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
139 int monitor_offset = BytesPerWord * method()->max_locals() +
140 (2 * BytesPerWord) * (number_of_locks - 1);
141 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
142 // the OSR buffer using 2 word entries: first the lock and then
143 // the oop.
144 for (int i = 0; i < number_of_locks; i++) {
145 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
146 #ifdef ASSERT
147 // Verify the interpreter's monitor has a non-null object.
148 {
149 Label L;
150 __ ld(R0, slot_offset + 1*BytesPerWord, OSR_buf);
151 __ cmpdi(CCR0, R0, 0);
152 __ bne(CCR0, L);
153 __ stop("locked object is null");
154 __ bind(L);
155 }
156 #endif // ASSERT
157 // Copy the lock field into the compiled activation.
158 Address ml = frame_map()->address_for_monitor_lock(i),
159 mo = frame_map()->address_for_monitor_object(i);
160 assert(ml.index() == noreg && mo.index() == noreg, "sanity");
161 __ ld(R0, slot_offset + 0, OSR_buf);
162 __ std(R0, ml.disp(), ml.base());
163 __ ld(R0, slot_offset + 1*BytesPerWord, OSR_buf);
164 __ std(R0, mo.disp(), mo.base());
165 }
166 }
167 }
168
169
170 int LIR_Assembler::emit_exception_handler() {
171 // Generate code for the exception handler.
172 address handler_base = __ start_a_stub(exception_handler_size());
173
174 if (handler_base == nullptr) {
175 // Not enough space left for the handler.
176 bailout("exception handler overflow");
177 return -1;
178 }
179
180 int offset = code_offset();
181 address entry_point = CAST_FROM_FN_PTR(address, Runtime1::entry_for(Runtime1::handle_exception_from_callee_id));
182 //__ load_const_optimized(R0, entry_point);
183 __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(entry_point));
184 __ mtctr(R0);
185 __ bctr();
186
187 guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
188 __ end_a_stub();
189
190 return offset;
191 }
192
193
194 // Emit the code to remove the frame from the stack in the exception
195 // unwind path.
196 int LIR_Assembler::emit_unwind_handler() {
197 _masm->block_comment("Unwind handler");
198
199 int offset = code_offset();
200 bool preserve_exception = method()->is_synchronized() || compilation()->env()->dtrace_method_probes();
201 const Register Rexception = R3 /*LIRGenerator::exceptionOopOpr()*/, Rexception_save = R31;
202
203 // Fetch the exception from TLS and clear out exception related thread state.
204 __ ld(Rexception, in_bytes(JavaThread::exception_oop_offset()), R16_thread);
205 __ li(R0, 0);
206 __ std(R0, in_bytes(JavaThread::exception_oop_offset()), R16_thread);
207 __ std(R0, in_bytes(JavaThread::exception_pc_offset()), R16_thread);
208
209 __ bind(_unwind_handler_entry);
210 __ verify_not_null_oop(Rexception);
211 if (preserve_exception) { __ mr(Rexception_save, Rexception); }
212
213 // Perform needed unlocking
214 MonitorExitStub* stub = nullptr;
215 if (method()->is_synchronized()) {
216 monitor_address(0, FrameMap::R4_opr);
217 stub = new MonitorExitStub(FrameMap::R4_opr, true, 0);
218 __ unlock_object(R5, R6, R4, *stub->entry());
219 __ bind(*stub->continuation());
220 }
221
222 if (compilation()->env()->dtrace_method_probes()) {
223 Unimplemented();
224 }
225
226 // Dispatch to the unwind logic.
227 address unwind_stub = Runtime1::entry_for(Runtime1::unwind_exception_id);
228 //__ load_const_optimized(R0, unwind_stub);
229 __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(unwind_stub));
230 if (preserve_exception) { __ mr(Rexception, Rexception_save); }
231 __ mtctr(R0);
232 __ bctr();
233
234 // Emit the slow path assembly.
235 if (stub != nullptr) {
236 stub->emit_code(this);
237 }
238
239 return offset;
240 }
241
242
243 int LIR_Assembler::emit_deopt_handler() {
244 // Generate code for deopt handler.
245 address handler_base = __ start_a_stub(deopt_handler_size());
246
247 if (handler_base == nullptr) {
248 // Not enough space left for the handler.
249 bailout("deopt handler overflow");
250 return -1;
251 }
252
253 int offset = code_offset();
254 __ bl64_patchable(SharedRuntime::deopt_blob()->unpack(), relocInfo::runtime_call_type);
255
256 guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
257 __ end_a_stub();
258
259 return offset;
260 }
261
262
263 void LIR_Assembler::jobject2reg(jobject o, Register reg) {
264 if (o == nullptr) {
265 __ li(reg, 0);
266 } else {
267 AddressLiteral addrlit = __ constant_oop_address(o);
268 __ load_const(reg, addrlit, (reg != R0) ? R0 : noreg);
269 }
270 }
271
272
273 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) {
274 // Allocate a new index in table to hold the object once it's been patched.
275 int oop_index = __ oop_recorder()->allocate_oop_index(nullptr);
276 PatchingStub* patch = new PatchingStub(_masm, patching_id(info), oop_index);
277
278 AddressLiteral addrlit((address)nullptr, oop_Relocation::spec(oop_index));
279 __ load_const(reg, addrlit, R0);
280
281 patching_epilog(patch, lir_patch_normal, reg, info);
282 }
283
284
285 void LIR_Assembler::metadata2reg(Metadata* o, Register reg) {
286 AddressLiteral md = __ constant_metadata_address(o); // Notify OOP recorder (don't need the relocation)
287 __ load_const_optimized(reg, md.value(), (reg != R0) ? R0 : noreg);
288 }
289
290
291 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo *info) {
292 // Allocate a new index in table to hold the klass once it's been patched.
293 int index = __ oop_recorder()->allocate_metadata_index(nullptr);
294 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id, index);
295
296 AddressLiteral addrlit((address)nullptr, metadata_Relocation::spec(index));
297 assert(addrlit.rspec().type() == relocInfo::metadata_type, "must be an metadata reloc");
298 __ load_const(reg, addrlit, R0);
299
300 patching_epilog(patch, lir_patch_normal, reg, info);
301 }
302
303
304 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) {
305 const bool is_int = result->is_single_cpu();
306 Register Rdividend = is_int ? left->as_register() : left->as_register_lo();
307 Register Rdivisor = noreg;
308 Register Rscratch = temp->as_register();
309 Register Rresult = is_int ? result->as_register() : result->as_register_lo();
310 long divisor = -1;
311
312 if (right->is_register()) {
313 Rdivisor = is_int ? right->as_register() : right->as_register_lo();
314 } else {
315 divisor = is_int ? right->as_constant_ptr()->as_jint()
316 : right->as_constant_ptr()->as_jlong();
317 }
318
319 assert(Rdividend != Rscratch, "");
320 assert(Rdivisor != Rscratch, "");
321 assert(code == lir_idiv || code == lir_irem, "Must be irem or idiv");
322
323 if (Rdivisor == noreg) {
324 if (divisor == 1) { // stupid, but can happen
325 if (code == lir_idiv) {
326 __ mr_if_needed(Rresult, Rdividend);
327 } else {
328 __ li(Rresult, 0);
329 }
330
331 } else if (is_power_of_2(divisor)) {
332 // Convert division by a power of two into some shifts and logical operations.
333 int log2 = log2i_exact(divisor);
334
335 // Round towards 0.
336 if (divisor == 2) {
337 if (is_int) {
338 __ srwi(Rscratch, Rdividend, 31);
339 } else {
340 __ srdi(Rscratch, Rdividend, 63);
341 }
342 } else {
343 if (is_int) {
344 __ srawi(Rscratch, Rdividend, 31);
345 } else {
346 __ sradi(Rscratch, Rdividend, 63);
347 }
348 __ clrldi(Rscratch, Rscratch, 64-log2);
349 }
350 __ add(Rscratch, Rdividend, Rscratch);
351
352 if (code == lir_idiv) {
353 if (is_int) {
354 __ srawi(Rresult, Rscratch, log2);
355 } else {
356 __ sradi(Rresult, Rscratch, log2);
357 }
358 } else { // lir_irem
359 __ clrrdi(Rscratch, Rscratch, log2);
360 __ sub(Rresult, Rdividend, Rscratch);
361 }
362
363 } else if (divisor == -1) {
364 if (code == lir_idiv) {
365 __ neg(Rresult, Rdividend);
366 } else {
367 __ li(Rresult, 0);
368 }
369
370 } else {
371 __ load_const_optimized(Rscratch, divisor);
372 if (code == lir_idiv) {
373 if (is_int) {
374 __ divw(Rresult, Rdividend, Rscratch); // Can't divide minint/-1.
375 } else {
376 __ divd(Rresult, Rdividend, Rscratch); // Can't divide minint/-1.
377 }
378 } else {
379 assert(Rscratch != R0, "need both");
380 if (is_int) {
381 __ divw(R0, Rdividend, Rscratch); // Can't divide minint/-1.
382 __ mullw(Rscratch, R0, Rscratch);
383 } else {
384 __ divd(R0, Rdividend, Rscratch); // Can't divide minint/-1.
385 __ mulld(Rscratch, R0, Rscratch);
386 }
387 __ sub(Rresult, Rdividend, Rscratch);
388 }
389
390 }
391 return;
392 }
393
394 Label regular, done;
395 if (is_int) {
396 __ cmpwi(CCR0, Rdivisor, -1);
397 } else {
398 __ cmpdi(CCR0, Rdivisor, -1);
399 }
400 __ bne(CCR0, regular);
401 if (code == lir_idiv) {
402 __ neg(Rresult, Rdividend);
403 __ b(done);
404 __ bind(regular);
405 if (is_int) {
406 __ divw(Rresult, Rdividend, Rdivisor); // Can't divide minint/-1.
407 } else {
408 __ divd(Rresult, Rdividend, Rdivisor); // Can't divide minint/-1.
409 }
410 } else { // lir_irem
411 __ li(Rresult, 0);
412 __ b(done);
413 __ bind(regular);
414 if (is_int) {
415 __ divw(Rscratch, Rdividend, Rdivisor); // Can't divide minint/-1.
416 __ mullw(Rscratch, Rscratch, Rdivisor);
417 } else {
418 __ divd(Rscratch, Rdividend, Rdivisor); // Can't divide minint/-1.
419 __ mulld(Rscratch, Rscratch, Rdivisor);
420 }
421 __ sub(Rresult, Rdividend, Rscratch);
422 }
423 __ bind(done);
424 }
425
426
427 void LIR_Assembler::emit_op3(LIR_Op3* op) {
428 switch (op->code()) {
429 case lir_idiv:
430 case lir_irem:
431 arithmetic_idiv(op->code(), op->in_opr1(), op->in_opr2(), op->in_opr3(),
432 op->result_opr(), op->info());
433 break;
434 case lir_fmad:
435 __ fmadd(op->result_opr()->as_double_reg(), op->in_opr1()->as_double_reg(),
436 op->in_opr2()->as_double_reg(), op->in_opr3()->as_double_reg());
437 break;
438 case lir_fmaf:
439 __ fmadds(op->result_opr()->as_float_reg(), op->in_opr1()->as_float_reg(),
440 op->in_opr2()->as_float_reg(), op->in_opr3()->as_float_reg());
441 break;
442 default: ShouldNotReachHere(); break;
443 }
444 }
445
446
447 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
448 #ifdef ASSERT
449 assert(op->block() == nullptr || op->block()->label() == op->label(), "wrong label");
450 if (op->block() != nullptr) _branch_target_blocks.append(op->block());
451 if (op->ublock() != nullptr) _branch_target_blocks.append(op->ublock());
452 assert(op->info() == nullptr, "shouldn't have CodeEmitInfo");
453 #endif
454
455 Label *L = op->label();
456 if (op->cond() == lir_cond_always) {
457 __ b(*L);
458 } else {
459 Label done;
460 bool is_unordered = false;
461 if (op->code() == lir_cond_float_branch) {
462 assert(op->ublock() != nullptr, "must have unordered successor");
463 is_unordered = true;
464 } else {
465 assert(op->code() == lir_branch, "just checking");
466 }
467
468 bool positive = false;
469 Assembler::Condition cond = Assembler::equal;
470 switch (op->cond()) {
471 case lir_cond_equal: positive = true ; cond = Assembler::equal ; is_unordered = false; break;
472 case lir_cond_notEqual: positive = false; cond = Assembler::equal ; is_unordered = false; break;
473 case lir_cond_less: positive = true ; cond = Assembler::less ; break;
474 case lir_cond_belowEqual: assert(op->code() != lir_cond_float_branch, ""); // fallthru
475 case lir_cond_lessEqual: positive = false; cond = Assembler::greater; break;
476 case lir_cond_greater: positive = true ; cond = Assembler::greater; break;
477 case lir_cond_aboveEqual: assert(op->code() != lir_cond_float_branch, ""); // fallthru
478 case lir_cond_greaterEqual: positive = false; cond = Assembler::less ; break;
479 default: ShouldNotReachHere();
480 }
481 int bo = positive ? Assembler::bcondCRbiIs1 : Assembler::bcondCRbiIs0;
482 int bi = Assembler::bi0(BOOL_RESULT, cond);
483 if (is_unordered) {
484 if (positive) {
485 if (op->ublock() == op->block()) {
486 __ bc_far_optimized(Assembler::bcondCRbiIs1, __ bi0(BOOL_RESULT, Assembler::summary_overflow), *L);
487 }
488 } else {
489 if (op->ublock() != op->block()) { __ bso(BOOL_RESULT, done); }
490 }
491 }
492 __ bc_far_optimized(bo, bi, *L);
493 __ bind(done);
494 }
495 }
496
497
498 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
499 Bytecodes::Code code = op->bytecode();
500 LIR_Opr src = op->in_opr(),
501 dst = op->result_opr();
502
503 switch(code) {
504 case Bytecodes::_i2l: {
505 __ extsw(dst->as_register_lo(), src->as_register());
506 break;
507 }
508 case Bytecodes::_l2i: {
509 __ mr_if_needed(dst->as_register(), src->as_register_lo()); // high bits are garbage
510 break;
511 }
512 case Bytecodes::_i2b: {
513 __ extsb(dst->as_register(), src->as_register());
514 break;
515 }
516 case Bytecodes::_i2c: {
517 __ clrldi(dst->as_register(), src->as_register(), 64-16);
518 break;
519 }
520 case Bytecodes::_i2s: {
521 __ extsh(dst->as_register(), src->as_register());
522 break;
523 }
524 case Bytecodes::_i2d:
525 case Bytecodes::_l2d: {
526 bool src_in_memory = !VM_Version::has_mtfprd();
527 FloatRegister rdst = dst->as_double_reg();
528 FloatRegister rsrc;
529 if (src_in_memory) {
530 rsrc = src->as_double_reg(); // via mem
531 } else {
532 // move src to dst register
533 if (code == Bytecodes::_i2d) {
534 __ mtfprwa(rdst, src->as_register());
535 } else {
536 __ mtfprd(rdst, src->as_register_lo());
537 }
538 rsrc = rdst;
539 }
540 __ fcfid(rdst, rsrc);
541 break;
542 }
543 case Bytecodes::_i2f:
544 case Bytecodes::_l2f: {
545 bool src_in_memory = !VM_Version::has_mtfprd();
546 FloatRegister rdst = dst->as_float_reg();
547 FloatRegister rsrc;
548 if (src_in_memory) {
549 rsrc = src->as_double_reg(); // via mem
550 } else {
551 // move src to dst register
552 if (code == Bytecodes::_i2f) {
553 __ mtfprwa(rdst, src->as_register());
554 } else {
555 __ mtfprd(rdst, src->as_register_lo());
556 }
557 rsrc = rdst;
558 }
559 if (VM_Version::has_fcfids()) {
560 __ fcfids(rdst, rsrc);
561 } else {
562 assert(code == Bytecodes::_i2f, "fcfid+frsp needs fixup code to avoid rounding incompatibility");
563 __ fcfid(rdst, rsrc);
564 __ frsp(rdst, rdst);
565 }
566 break;
567 }
568 case Bytecodes::_f2d: {
569 __ fmr_if_needed(dst->as_double_reg(), src->as_float_reg());
570 break;
571 }
572 case Bytecodes::_d2f: {
573 __ frsp(dst->as_float_reg(), src->as_double_reg());
574 break;
575 }
576 case Bytecodes::_d2i:
577 case Bytecodes::_f2i: {
578 bool dst_in_memory = !VM_Version::has_mtfprd();
579 FloatRegister rsrc = (code == Bytecodes::_d2i) ? src->as_double_reg() : src->as_float_reg();
580 Address addr = dst_in_memory ? frame_map()->address_for_slot(dst->double_stack_ix()) : Address();
581 Label L;
582 // Result must be 0 if value is NaN; test by comparing value to itself.
583 __ fcmpu(CCR0, rsrc, rsrc);
584 if (dst_in_memory) {
585 __ li(R0, 0); // 0 in case of NAN
586 __ std(R0, addr.disp(), addr.base());
587 } else {
588 __ li(dst->as_register(), 0);
589 }
590 __ bso(CCR0, L);
591 __ fctiwz(rsrc, rsrc); // USE_KILL
592 if (dst_in_memory) {
593 __ stfd(rsrc, addr.disp(), addr.base());
594 } else {
595 __ mffprd(dst->as_register(), rsrc);
596 }
597 __ bind(L);
598 break;
599 }
600 case Bytecodes::_d2l:
601 case Bytecodes::_f2l: {
602 bool dst_in_memory = !VM_Version::has_mtfprd();
603 FloatRegister rsrc = (code == Bytecodes::_d2l) ? src->as_double_reg() : src->as_float_reg();
604 Address addr = dst_in_memory ? frame_map()->address_for_slot(dst->double_stack_ix()) : Address();
605 Label L;
606 // Result must be 0 if value is NaN; test by comparing value to itself.
607 __ fcmpu(CCR0, rsrc, rsrc);
608 if (dst_in_memory) {
609 __ li(R0, 0); // 0 in case of NAN
610 __ std(R0, addr.disp(), addr.base());
611 } else {
612 __ li(dst->as_register_lo(), 0);
613 }
614 __ bso(CCR0, L);
615 __ fctidz(rsrc, rsrc); // USE_KILL
616 if (dst_in_memory) {
617 __ stfd(rsrc, addr.disp(), addr.base());
618 } else {
619 __ mffprd(dst->as_register_lo(), rsrc);
620 }
621 __ bind(L);
622 break;
623 }
624
625 default: ShouldNotReachHere();
626 }
627 }
628
629
630 void LIR_Assembler::align_call(LIR_Code) {
631 // do nothing since all instructions are word aligned on ppc
632 }
633
634
635 bool LIR_Assembler::emit_trampoline_stub_for_call(address target, Register Rtoc) {
636 int start_offset = __ offset();
637 // Put the entry point as a constant into the constant pool.
638 const address entry_point_toc_addr = __ address_constant(target, RelocationHolder::none);
639 if (entry_point_toc_addr == nullptr) {
640 bailout("const section overflow");
641 return false;
642 }
643 const int entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr);
644
645 // Emit the trampoline stub which will be related to the branch-and-link below.
646 address stub = __ emit_trampoline_stub(entry_point_toc_offset, start_offset, Rtoc);
647 if (!stub) {
648 bailout("no space for trampoline stub");
649 return false;
650 }
651 return true;
652 }
653
654
655 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
656 assert(rtype==relocInfo::opt_virtual_call_type || rtype==relocInfo::static_call_type, "unexpected rtype");
657
658 bool success = emit_trampoline_stub_for_call(op->addr());
659 if (!success) { return; }
660
661 __ relocate(rtype);
662 // Note: At this point we do not have the address of the trampoline
663 // stub, and the entry point might be too far away for bl, so __ pc()
664 // serves as dummy and the bl will be patched later.
665 __ code()->set_insts_mark();
666 __ bl(__ pc());
667 add_call_info(code_offset(), op->info());
668 __ post_call_nop();
669 }
670
671
672 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
673 __ calculate_address_from_global_toc(R2_TOC, __ method_toc());
674
675 // Virtual call relocation will point to ic load.
676 address virtual_call_meta_addr = __ pc();
677 // Load a clear inline cache.
678 AddressLiteral empty_ic((address) Universe::non_oop_word());
679 bool success = __ load_const_from_method_toc(R19_inline_cache_reg, empty_ic, R2_TOC);
680 if (!success) {
681 bailout("const section overflow");
682 return;
683 }
684 // Call to fixup routine. Fixup routine uses ScopeDesc info
685 // to determine who we intended to call.
686 __ relocate(virtual_call_Relocation::spec(virtual_call_meta_addr));
687
688 success = emit_trampoline_stub_for_call(op->addr(), R2_TOC);
689 if (!success) { return; }
690
691 // Note: At this point we do not have the address of the trampoline
692 // stub, and the entry point might be too far away for bl, so __ pc()
693 // serves as dummy and the bl will be patched later.
694 __ bl(__ pc());
695 add_call_info(code_offset(), op->info());
696 __ post_call_nop();
697 }
698
699 void LIR_Assembler::explicit_null_check(Register addr, CodeEmitInfo* info) {
700 ImplicitNullCheckStub* stub = new ImplicitNullCheckStub(code_offset(), info);
701 __ null_check(addr, stub->entry());
702 append_code_stub(stub);
703 }
704
705
706 // Attention: caller must encode oop if needed
707 int LIR_Assembler::store(LIR_Opr from_reg, Register base, int offset, BasicType type, bool wide) {
708 int store_offset;
709 if (!Assembler::is_simm16(offset)) {
710 // For offsets larger than a simm16 we setup the offset.
711 assert(wide && !from_reg->is_same_register(FrameMap::R0_opr), "large offset only supported in special case");
712 __ load_const_optimized(R0, offset);
713 store_offset = store(from_reg, base, R0, type, wide);
714 } else {
715 store_offset = code_offset();
716 switch (type) {
717 case T_BOOLEAN: // fall through
718 case T_BYTE : __ stb(from_reg->as_register(), offset, base); break;
719 case T_CHAR :
720 case T_SHORT : __ sth(from_reg->as_register(), offset, base); break;
721 case T_INT : __ stw(from_reg->as_register(), offset, base); break;
722 case T_LONG : __ std(from_reg->as_register_lo(), offset, base); break;
723 case T_ADDRESS:
724 case T_METADATA: __ std(from_reg->as_register(), offset, base); break;
725 case T_ARRAY : // fall through
726 case T_OBJECT:
727 {
728 if (UseCompressedOops && !wide) {
729 // Encoding done in caller
730 __ stw(from_reg->as_register(), offset, base);
731 __ verify_coop(from_reg->as_register(), FILE_AND_LINE);
732 } else {
733 __ std(from_reg->as_register(), offset, base);
734 if (VerifyOops) {
735 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
736 bs->check_oop(_masm, from_reg->as_register(), FILE_AND_LINE); // kills R0
737 }
738 }
739 break;
740 }
741 case T_FLOAT : __ stfs(from_reg->as_float_reg(), offset, base); break;
742 case T_DOUBLE: __ stfd(from_reg->as_double_reg(), offset, base); break;
743 default : ShouldNotReachHere();
744 }
745 }
746 return store_offset;
747 }
748
749
750 // Attention: caller must encode oop if needed
751 int LIR_Assembler::store(LIR_Opr from_reg, Register base, Register disp, BasicType type, bool wide) {
752 int store_offset = code_offset();
753 switch (type) {
754 case T_BOOLEAN: // fall through
755 case T_BYTE : __ stbx(from_reg->as_register(), base, disp); break;
756 case T_CHAR :
757 case T_SHORT : __ sthx(from_reg->as_register(), base, disp); break;
758 case T_INT : __ stwx(from_reg->as_register(), base, disp); break;
759 case T_LONG :
760 #ifdef _LP64
761 __ stdx(from_reg->as_register_lo(), base, disp);
762 #else
763 Unimplemented();
764 #endif
765 break;
766 case T_ADDRESS:
767 __ stdx(from_reg->as_register(), base, disp);
768 break;
769 case T_ARRAY : // fall through
770 case T_OBJECT:
771 {
772 if (UseCompressedOops && !wide) {
773 // Encoding done in caller.
774 __ stwx(from_reg->as_register(), base, disp);
775 __ verify_coop(from_reg->as_register(), FILE_AND_LINE); // kills R0
776 } else {
777 __ stdx(from_reg->as_register(), base, disp);
778 if (VerifyOops) {
779 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
780 bs->check_oop(_masm, from_reg->as_register(), FILE_AND_LINE); // kills R0
781 }
782 }
783 break;
784 }
785 case T_FLOAT : __ stfsx(from_reg->as_float_reg(), base, disp); break;
786 case T_DOUBLE: __ stfdx(from_reg->as_double_reg(), base, disp); break;
787 default : ShouldNotReachHere();
788 }
789 return store_offset;
790 }
791
792
793 int LIR_Assembler::load(Register base, int offset, LIR_Opr to_reg, BasicType type, bool wide) {
794 int load_offset;
795 if (!Assembler::is_simm16(offset)) {
796 // For offsets larger than a simm16 we setup the offset.
797 __ load_const_optimized(R0, offset);
798 load_offset = load(base, R0, to_reg, type, wide);
799 } else {
800 load_offset = code_offset();
801 switch(type) {
802 case T_BOOLEAN: // fall through
803 case T_BYTE : __ lbz(to_reg->as_register(), offset, base);
804 __ extsb(to_reg->as_register(), to_reg->as_register()); break;
805 case T_CHAR : __ lhz(to_reg->as_register(), offset, base); break;
806 case T_SHORT : __ lha(to_reg->as_register(), offset, base); break;
807 case T_INT : __ lwa(to_reg->as_register(), offset, base); break;
808 case T_LONG : __ ld(to_reg->as_register_lo(), offset, base); break;
809 case T_METADATA: __ ld(to_reg->as_register(), offset, base); break;
810 case T_ADDRESS:
811 __ ld(to_reg->as_register(), offset, base);
812 break;
813 case T_ARRAY : // fall through
814 case T_OBJECT:
815 {
816 if (UseCompressedOops && !wide) {
817 __ lwz(to_reg->as_register(), offset, base);
818 __ decode_heap_oop(to_reg->as_register());
819 } else {
820 __ ld(to_reg->as_register(), offset, base);
821 }
822 break;
823 }
824 case T_FLOAT: __ lfs(to_reg->as_float_reg(), offset, base); break;
825 case T_DOUBLE: __ lfd(to_reg->as_double_reg(), offset, base); break;
826 default : ShouldNotReachHere();
827 }
828 }
829 return load_offset;
830 }
831
832
833 int LIR_Assembler::load(Register base, Register disp, LIR_Opr to_reg, BasicType type, bool wide) {
834 int load_offset = code_offset();
835 switch(type) {
836 case T_BOOLEAN: // fall through
837 case T_BYTE : __ lbzx(to_reg->as_register(), base, disp);
838 __ extsb(to_reg->as_register(), to_reg->as_register()); break;
839 case T_CHAR : __ lhzx(to_reg->as_register(), base, disp); break;
840 case T_SHORT : __ lhax(to_reg->as_register(), base, disp); break;
841 case T_INT : __ lwax(to_reg->as_register(), base, disp); break;
842 case T_ADDRESS: __ ldx(to_reg->as_register(), base, disp); break;
843 case T_ARRAY : // fall through
844 case T_OBJECT:
845 {
846 if (UseCompressedOops && !wide) {
847 __ lwzx(to_reg->as_register(), base, disp);
848 __ decode_heap_oop(to_reg->as_register());
849 } else {
850 __ ldx(to_reg->as_register(), base, disp);
851 }
852 break;
853 }
854 case T_FLOAT: __ lfsx(to_reg->as_float_reg() , base, disp); break;
855 case T_DOUBLE: __ lfdx(to_reg->as_double_reg(), base, disp); break;
856 case T_LONG :
857 #ifdef _LP64
858 __ ldx(to_reg->as_register_lo(), base, disp);
859 #else
860 Unimplemented();
861 #endif
862 break;
863 default : ShouldNotReachHere();
864 }
865 return load_offset;
866 }
867
868
869 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
870 LIR_Const* c = src->as_constant_ptr();
871 Register src_reg = R0;
872 switch (c->type()) {
873 case T_INT:
874 case T_FLOAT: {
875 int value = c->as_jint_bits();
876 __ load_const_optimized(src_reg, value);
877 Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
878 __ stw(src_reg, addr.disp(), addr.base());
879 break;
880 }
881 case T_ADDRESS: {
882 int value = c->as_jint_bits();
883 __ load_const_optimized(src_reg, value);
884 Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
885 __ std(src_reg, addr.disp(), addr.base());
886 break;
887 }
888 case T_OBJECT: {
889 jobject2reg(c->as_jobject(), src_reg);
890 Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
891 __ std(src_reg, addr.disp(), addr.base());
892 break;
893 }
894 case T_LONG:
895 case T_DOUBLE: {
896 int value = c->as_jlong_bits();
897 __ load_const_optimized(src_reg, value);
898 Address addr = frame_map()->address_for_double_slot(dest->double_stack_ix());
899 __ std(src_reg, addr.disp(), addr.base());
900 break;
901 }
902 default:
903 Unimplemented();
904 }
905 }
906
907
908 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
909 LIR_Const* c = src->as_constant_ptr();
910 LIR_Address* addr = dest->as_address_ptr();
911 Register base = addr->base()->as_pointer_register();
912 LIR_Opr tmp = LIR_OprFact::illegalOpr;
913 int offset = -1;
914 // Null check for large offsets in LIRGenerator::do_StoreField.
915 bool needs_explicit_null_check = !ImplicitNullChecks;
916
917 if (info != nullptr && needs_explicit_null_check) {
918 explicit_null_check(base, info);
919 }
920
921 switch (c->type()) {
922 case T_FLOAT: type = T_INT;
923 case T_INT:
924 case T_ADDRESS: {
925 tmp = FrameMap::R0_opr;
926 __ load_const_optimized(tmp->as_register(), c->as_jint_bits());
927 break;
928 }
929 case T_DOUBLE: type = T_LONG;
930 case T_LONG: {
931 tmp = FrameMap::R0_long_opr;
932 __ load_const_optimized(tmp->as_register_lo(), c->as_jlong_bits());
933 break;
934 }
935 case T_OBJECT: {
936 tmp = FrameMap::R0_opr;
937 if (UseCompressedOops && !wide && c->as_jobject() != nullptr) {
938 AddressLiteral oop_addr = __ constant_oop_address(c->as_jobject());
939 // Don't care about sign extend (will use stw).
940 __ lis(R0, 0); // Will get patched.
941 __ relocate(oop_addr.rspec(), /*compressed format*/ 1);
942 __ ori(R0, R0, 0); // Will get patched.
943 } else {
944 jobject2reg(c->as_jobject(), R0);
945 }
946 break;
947 }
948 default:
949 Unimplemented();
950 }
951
952 // Handle either reg+reg or reg+disp address.
953 if (addr->index()->is_valid()) {
954 assert(addr->disp() == 0, "must be zero");
955 offset = store(tmp, base, addr->index()->as_pointer_register(), type, wide);
956 } else {
957 assert(Assembler::is_simm16(addr->disp()), "can't handle larger addresses");
958 offset = store(tmp, base, addr->disp(), type, wide);
959 }
960
961 if (info != nullptr) {
962 assert(offset != -1, "offset should've been set");
963 if (!needs_explicit_null_check) {
964 add_debug_info_for_null_check(offset, info);
965 }
966 }
967 }
968
969
970 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
971 LIR_Const* c = src->as_constant_ptr();
972 LIR_Opr to_reg = dest;
973
974 switch (c->type()) {
975 case T_INT: {
976 assert(patch_code == lir_patch_none, "no patching handled here");
977 __ load_const_optimized(dest->as_register(), c->as_jint(), R0);
978 break;
979 }
980 case T_ADDRESS: {
981 assert(patch_code == lir_patch_none, "no patching handled here");
982 __ load_const_optimized(dest->as_register(), c->as_jint(), R0); // Yes, as_jint ...
983 break;
984 }
985 case T_LONG: {
986 assert(patch_code == lir_patch_none, "no patching handled here");
987 __ load_const_optimized(dest->as_register_lo(), c->as_jlong(), R0);
988 break;
989 }
990
991 case T_OBJECT: {
992 if (patch_code == lir_patch_none) {
993 jobject2reg(c->as_jobject(), to_reg->as_register());
994 } else {
995 jobject2reg_with_patching(to_reg->as_register(), info);
996 }
997 break;
998 }
999
1000 case T_METADATA:
1001 {
1002 if (patch_code == lir_patch_none) {
1003 metadata2reg(c->as_metadata(), to_reg->as_register());
1004 } else {
1005 klass2reg_with_patching(to_reg->as_register(), info);
1006 }
1007 }
1008 break;
1009
1010 case T_FLOAT:
1011 {
1012 if (to_reg->is_single_fpu()) {
1013 address const_addr = __ float_constant(c->as_jfloat());
1014 if (const_addr == nullptr) {
1015 bailout("const section overflow");
1016 break;
1017 }
1018 RelocationHolder rspec = internal_word_Relocation::spec(const_addr);
1019 __ relocate(rspec);
1020 __ load_const(R0, const_addr);
1021 __ lfsx(to_reg->as_float_reg(), R0);
1022 } else {
1023 assert(to_reg->is_single_cpu(), "Must be a cpu register.");
1024 __ load_const_optimized(to_reg->as_register(), jint_cast(c->as_jfloat()), R0);
1025 }
1026 }
1027 break;
1028
1029 case T_DOUBLE:
1030 {
1031 if (to_reg->is_double_fpu()) {
1032 address const_addr = __ double_constant(c->as_jdouble());
1033 if (const_addr == nullptr) {
1034 bailout("const section overflow");
1035 break;
1036 }
1037 RelocationHolder rspec = internal_word_Relocation::spec(const_addr);
1038 __ relocate(rspec);
1039 __ load_const(R0, const_addr);
1040 __ lfdx(to_reg->as_double_reg(), R0);
1041 } else {
1042 assert(to_reg->is_double_cpu(), "Must be a long register.");
1043 __ load_const_optimized(to_reg->as_register_lo(), jlong_cast(c->as_jdouble()), R0);
1044 }
1045 }
1046 break;
1047
1048 default:
1049 ShouldNotReachHere();
1050 }
1051 }
1052
1053
1054 Address LIR_Assembler::as_Address(LIR_Address* addr) {
1055 Unimplemented(); return Address();
1056 }
1057
1058
1059 inline RegisterOrConstant index_or_disp(LIR_Address* addr) {
1060 if (addr->index()->is_illegal()) {
1061 return (RegisterOrConstant)(addr->disp());
1062 } else {
1063 return (RegisterOrConstant)(addr->index()->as_pointer_register());
1064 }
1065 }
1066
1067
1068 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
1069 const Register tmp = R0;
1070 switch (type) {
1071 case T_INT:
1072 case T_FLOAT: {
1073 Address from = frame_map()->address_for_slot(src->single_stack_ix());
1074 Address to = frame_map()->address_for_slot(dest->single_stack_ix());
1075 __ lwz(tmp, from.disp(), from.base());
1076 __ stw(tmp, to.disp(), to.base());
1077 break;
1078 }
1079 case T_ADDRESS:
1080 case T_OBJECT: {
1081 Address from = frame_map()->address_for_slot(src->single_stack_ix());
1082 Address to = frame_map()->address_for_slot(dest->single_stack_ix());
1083 __ ld(tmp, from.disp(), from.base());
1084 __ std(tmp, to.disp(), to.base());
1085 break;
1086 }
1087 case T_LONG:
1088 case T_DOUBLE: {
1089 Address from = frame_map()->address_for_double_slot(src->double_stack_ix());
1090 Address to = frame_map()->address_for_double_slot(dest->double_stack_ix());
1091 __ ld(tmp, from.disp(), from.base());
1092 __ std(tmp, to.disp(), to.base());
1093 break;
1094 }
1095
1096 default:
1097 ShouldNotReachHere();
1098 }
1099 }
1100
1101
1102 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
1103 Unimplemented(); return Address();
1104 }
1105
1106
1107 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
1108 Unimplemented(); return Address();
1109 }
1110
1111
1112 void LIR_Assembler::mem2reg(LIR_Opr src_opr, LIR_Opr dest, BasicType type,
1113 LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide) {
1114
1115 assert(type != T_METADATA, "load of metadata ptr not supported");
1116 LIR_Address* addr = src_opr->as_address_ptr();
1117 LIR_Opr to_reg = dest;
1118
1119 Register src = addr->base()->as_pointer_register();
1120 Register disp_reg = noreg;
1121 int disp_value = addr->disp();
1122 bool needs_patching = (patch_code != lir_patch_none);
1123 // null check for large offsets in LIRGenerator::do_LoadField
1124 bool needs_explicit_null_check = !os::zero_page_read_protected() || !ImplicitNullChecks;
1125
1126 if (info != nullptr && needs_explicit_null_check) {
1127 explicit_null_check(src, info);
1128 }
1129
1130 if (addr->base()->type() == T_OBJECT) {
1131 __ verify_oop(src, FILE_AND_LINE);
1132 }
1133
1134 PatchingStub* patch = nullptr;
1135 if (needs_patching) {
1136 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1137 assert(!to_reg->is_double_cpu() ||
1138 patch_code == lir_patch_none ||
1139 patch_code == lir_patch_normal, "patching doesn't match register");
1140 }
1141
1142 if (addr->index()->is_illegal()) {
1143 if (!Assembler::is_simm16(disp_value)) {
1144 if (needs_patching) {
1145 __ load_const32(R0, 0); // patchable int
1146 } else {
1147 __ load_const_optimized(R0, disp_value);
1148 }
1149 disp_reg = R0;
1150 }
1151 } else {
1152 disp_reg = addr->index()->as_pointer_register();
1153 assert(disp_value == 0, "can't handle 3 operand addresses");
1154 }
1155
1156 // Remember the offset of the load. The patching_epilog must be done
1157 // before the call to add_debug_info, otherwise the PcDescs don't get
1158 // entered in increasing order.
1159 int offset;
1160
1161 if (disp_reg == noreg) {
1162 assert(Assembler::is_simm16(disp_value), "should have set this up");
1163 offset = load(src, disp_value, to_reg, type, wide);
1164 } else {
1165 offset = load(src, disp_reg, to_reg, type, wide);
1166 }
1167
1168 if (patch != nullptr) {
1169 patching_epilog(patch, patch_code, src, info);
1170 }
1171 if (info != nullptr && !needs_explicit_null_check) {
1172 add_debug_info_for_null_check(offset, info);
1173 }
1174 }
1175
1176
1177 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
1178 Address addr;
1179 if (src->is_single_word()) {
1180 addr = frame_map()->address_for_slot(src->single_stack_ix());
1181 } else if (src->is_double_word()) {
1182 addr = frame_map()->address_for_double_slot(src->double_stack_ix());
1183 }
1184
1185 load(addr.base(), addr.disp(), dest, dest->type(), true /*wide*/);
1186 }
1187
1188
1189 void LIR_Assembler::reg2stack(LIR_Opr from_reg, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
1190 Address addr;
1191 if (dest->is_single_word()) {
1192 addr = frame_map()->address_for_slot(dest->single_stack_ix());
1193 } else if (dest->is_double_word()) {
1194 addr = frame_map()->address_for_slot(dest->double_stack_ix());
1195 }
1196
1197 store(from_reg, addr.base(), addr.disp(), from_reg->type(), true /*wide*/);
1198 }
1199
1200
1201 void LIR_Assembler::reg2reg(LIR_Opr from_reg, LIR_Opr to_reg) {
1202 if (from_reg->is_float_kind() && to_reg->is_float_kind()) {
1203 if (from_reg->is_double_fpu()) {
1204 // double to double moves
1205 assert(to_reg->is_double_fpu(), "should match");
1206 __ fmr_if_needed(to_reg->as_double_reg(), from_reg->as_double_reg());
1207 } else {
1208 // float to float moves
1209 assert(to_reg->is_single_fpu(), "should match");
1210 __ fmr_if_needed(to_reg->as_float_reg(), from_reg->as_float_reg());
1211 }
1212 } else if (!from_reg->is_float_kind() && !to_reg->is_float_kind()) {
1213 if (from_reg->is_double_cpu()) {
1214 __ mr_if_needed(to_reg->as_pointer_register(), from_reg->as_pointer_register());
1215 } else if (to_reg->is_double_cpu()) {
1216 // int to int moves
1217 __ mr_if_needed(to_reg->as_register_lo(), from_reg->as_register());
1218 } else {
1219 // int to int moves
1220 __ mr_if_needed(to_reg->as_register(), from_reg->as_register());
1221 }
1222 } else {
1223 ShouldNotReachHere();
1224 }
1225 if (is_reference_type(to_reg->type())) {
1226 __ verify_oop(to_reg->as_register(), FILE_AND_LINE);
1227 }
1228 }
1229
1230
1231 void LIR_Assembler::reg2mem(LIR_Opr from_reg, LIR_Opr dest, BasicType type,
1232 LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack,
1233 bool wide) {
1234 assert(type != T_METADATA, "store of metadata ptr not supported");
1235 LIR_Address* addr = dest->as_address_ptr();
1236
1237 Register src = addr->base()->as_pointer_register();
1238 Register disp_reg = noreg;
1239 int disp_value = addr->disp();
1240 bool needs_patching = (patch_code != lir_patch_none);
1241 bool compress_oop = (is_reference_type(type)) && UseCompressedOops && !wide &&
1242 CompressedOops::mode() != CompressedOops::UnscaledNarrowOop;
1243 bool load_disp = addr->index()->is_illegal() && !Assembler::is_simm16(disp_value);
1244 bool use_R29 = compress_oop && load_disp; // Avoid register conflict, also do null check before killing R29.
1245 // Null check for large offsets in LIRGenerator::do_StoreField.
1246 bool needs_explicit_null_check = !ImplicitNullChecks || use_R29;
1247
1248 if (info != nullptr && needs_explicit_null_check) {
1249 explicit_null_check(src, info);
1250 }
1251
1252 if (addr->base()->is_oop_register()) {
1253 __ verify_oop(src, FILE_AND_LINE);
1254 }
1255
1256 PatchingStub* patch = nullptr;
1257 if (needs_patching) {
1258 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1259 assert(!from_reg->is_double_cpu() ||
1260 patch_code == lir_patch_none ||
1261 patch_code == lir_patch_normal, "patching doesn't match register");
1262 }
1263
1264 if (addr->index()->is_illegal()) {
1265 if (load_disp) {
1266 disp_reg = use_R29 ? R29_TOC : R0;
1267 if (needs_patching) {
1268 __ load_const32(disp_reg, 0); // patchable int
1269 } else {
1270 __ load_const_optimized(disp_reg, disp_value);
1271 }
1272 }
1273 } else {
1274 disp_reg = addr->index()->as_pointer_register();
1275 assert(disp_value == 0, "can't handle 3 operand addresses");
1276 }
1277
1278 // remember the offset of the store. The patching_epilog must be done
1279 // before the call to add_debug_info_for_null_check, otherwise the PcDescs don't get
1280 // entered in increasing order.
1281 int offset;
1282
1283 if (compress_oop) {
1284 Register co = __ encode_heap_oop(R0, from_reg->as_register());
1285 from_reg = FrameMap::as_opr(co);
1286 }
1287
1288 if (disp_reg == noreg) {
1289 assert(Assembler::is_simm16(disp_value), "should have set this up");
1290 offset = store(from_reg, src, disp_value, type, wide);
1291 } else {
1292 offset = store(from_reg, src, disp_reg, type, wide);
1293 }
1294
1295 if (use_R29) {
1296 __ load_const_optimized(R29_TOC, MacroAssembler::global_toc(), R0); // reinit
1297 }
1298
1299 if (patch != nullptr) {
1300 patching_epilog(patch, patch_code, src, info);
1301 }
1302
1303 if (info != nullptr && !needs_explicit_null_check) {
1304 add_debug_info_for_null_check(offset, info);
1305 }
1306 }
1307
1308
1309 void LIR_Assembler::return_op(LIR_Opr result, C1SafepointPollStub* code_stub) {
1310 const Register return_pc = R31; // Must survive C-call to enable_stack_reserved_zone().
1311 const Register temp = R12;
1312
1313 // Pop the stack before the safepoint code.
1314 int frame_size = initial_frame_size_in_bytes();
1315 if (Assembler::is_simm(frame_size, 16)) {
1316 __ addi(R1_SP, R1_SP, frame_size);
1317 } else {
1318 __ pop_frame();
1319 }
1320
1321 // Restore return pc relative to callers' sp.
1322 __ ld(return_pc, _abi0(lr), R1_SP);
1323 // Move return pc to LR.
1324 __ mtlr(return_pc);
1325
1326 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
1327 __ reserved_stack_check(return_pc);
1328 }
1329
1330 // We need to mark the code position where the load from the safepoint
1331 // polling page was emitted as relocInfo::poll_return_type here.
1332 if (!UseSIGTRAP) {
1333 code_stub->set_safepoint_offset(__ offset());
1334 __ relocate(relocInfo::poll_return_type);
1335 }
1336 __ safepoint_poll(*code_stub->entry(), temp, true /* at_return */, true /* in_nmethod */);
1337
1338 // Return.
1339 __ blr();
1340 }
1341
1342
1343 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
1344 const Register poll_addr = tmp->as_register();
1345 __ ld(poll_addr, in_bytes(JavaThread::polling_page_offset()), R16_thread);
1346 if (info != nullptr) {
1347 add_debug_info_for_branch(info);
1348 }
1349 int offset = __ offset();
1350 __ relocate(relocInfo::poll_type);
1351 __ load_from_polling_page(poll_addr);
1352
1353 return offset;
1354 }
1355
1356
1357 void LIR_Assembler::emit_static_call_stub() {
1358 address call_pc = __ pc();
1359 address stub = __ start_a_stub(static_call_stub_size());
1360 if (stub == nullptr) {
1361 bailout("static call stub overflow");
1362 return;
1363 }
1364
1365 // For java_to_interp stubs we use R11_scratch1 as scratch register
1366 // and in call trampoline stubs we use R12_scratch2. This way we
1367 // can distinguish them (see is_NativeCallTrampolineStub_at()).
1368 const Register reg_scratch = R11_scratch1;
1369
1370 // Create a static stub relocation which relates this stub
1371 // with the call instruction at insts_call_instruction_offset in the
1372 // instructions code-section.
1373 int start = __ offset();
1374 __ relocate(static_stub_Relocation::spec(call_pc));
1375
1376 // Now, create the stub's code:
1377 // - load the TOC
1378 // - load the inline cache oop from the constant pool
1379 // - load the call target from the constant pool
1380 // - call
1381 __ calculate_address_from_global_toc(reg_scratch, __ method_toc());
1382 AddressLiteral ic = __ allocate_metadata_address((Metadata *)nullptr);
1383 bool success = __ load_const_from_method_toc(R19_inline_cache_reg, ic, reg_scratch, /*fixed_size*/ true);
1384
1385 if (ReoptimizeCallSequences) {
1386 __ b64_patchable((address)-1, relocInfo::none);
1387 } else {
1388 AddressLiteral a((address)-1);
1389 success = success && __ load_const_from_method_toc(reg_scratch, a, reg_scratch, /*fixed_size*/ true);
1390 __ mtctr(reg_scratch);
1391 __ bctr();
1392 }
1393 if (!success) {
1394 bailout("const section overflow");
1395 return;
1396 }
1397
1398 assert(__ offset() - start <= static_call_stub_size(), "stub too big");
1399 __ end_a_stub();
1400 }
1401
1402
1403 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
1404 bool unsigned_comp = (condition == lir_cond_belowEqual || condition == lir_cond_aboveEqual);
1405 if (opr1->is_single_fpu()) {
1406 __ fcmpu(BOOL_RESULT, opr1->as_float_reg(), opr2->as_float_reg());
1407 } else if (opr1->is_double_fpu()) {
1408 __ fcmpu(BOOL_RESULT, opr1->as_double_reg(), opr2->as_double_reg());
1409 } else if (opr1->is_single_cpu()) {
1410 if (opr2->is_constant()) {
1411 switch (opr2->as_constant_ptr()->type()) {
1412 case T_INT:
1413 {
1414 jint con = opr2->as_constant_ptr()->as_jint();
1415 if (unsigned_comp) {
1416 if (Assembler::is_uimm(con, 16)) {
1417 __ cmplwi(BOOL_RESULT, opr1->as_register(), con);
1418 } else {
1419 __ load_const_optimized(R0, con);
1420 __ cmplw(BOOL_RESULT, opr1->as_register(), R0);
1421 }
1422 } else {
1423 if (Assembler::is_simm(con, 16)) {
1424 __ cmpwi(BOOL_RESULT, opr1->as_register(), con);
1425 } else {
1426 __ load_const_optimized(R0, con);
1427 __ cmpw(BOOL_RESULT, opr1->as_register(), R0);
1428 }
1429 }
1430 }
1431 break;
1432
1433 case T_OBJECT:
1434 // There are only equal/notequal comparisons on objects.
1435 {
1436 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "oops");
1437 jobject con = opr2->as_constant_ptr()->as_jobject();
1438 if (con == nullptr) {
1439 __ cmpdi(BOOL_RESULT, opr1->as_register(), 0);
1440 } else {
1441 jobject2reg(con, R0);
1442 __ cmpd(BOOL_RESULT, opr1->as_register(), R0);
1443 }
1444 }
1445 break;
1446
1447 case T_METADATA:
1448 // We only need, for now, comparison with null for metadata.
1449 {
1450 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "oops");
1451 Metadata* p = opr2->as_constant_ptr()->as_metadata();
1452 if (p == nullptr) {
1453 __ cmpdi(BOOL_RESULT, opr1->as_register(), 0);
1454 } else {
1455 ShouldNotReachHere();
1456 }
1457 }
1458 break;
1459
1460 default:
1461 ShouldNotReachHere();
1462 break;
1463 }
1464 } else {
1465 assert(opr1->type() != T_ADDRESS && opr2->type() != T_ADDRESS, "currently unsupported");
1466 if (is_reference_type(opr1->type())) {
1467 // There are only equal/notequal comparisons on objects.
1468 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "oops");
1469 __ cmpd(BOOL_RESULT, opr1->as_register(), opr2->as_register());
1470 } else {
1471 if (unsigned_comp) {
1472 __ cmplw(BOOL_RESULT, opr1->as_register(), opr2->as_register());
1473 } else {
1474 __ cmpw(BOOL_RESULT, opr1->as_register(), opr2->as_register());
1475 }
1476 }
1477 }
1478 } else if (opr1->is_double_cpu()) {
1479 if (opr2->is_constant()) {
1480 jlong con = opr2->as_constant_ptr()->as_jlong();
1481 if (unsigned_comp) {
1482 if (Assembler::is_uimm(con, 16)) {
1483 __ cmpldi(BOOL_RESULT, opr1->as_register_lo(), con);
1484 } else {
1485 __ load_const_optimized(R0, con);
1486 __ cmpld(BOOL_RESULT, opr1->as_register_lo(), R0);
1487 }
1488 } else {
1489 if (Assembler::is_simm(con, 16)) {
1490 __ cmpdi(BOOL_RESULT, opr1->as_register_lo(), con);
1491 } else {
1492 __ load_const_optimized(R0, con);
1493 __ cmpd(BOOL_RESULT, opr1->as_register_lo(), R0);
1494 }
1495 }
1496 } else if (opr2->is_register()) {
1497 if (unsigned_comp) {
1498 __ cmpld(BOOL_RESULT, opr1->as_register_lo(), opr2->as_register_lo());
1499 } else {
1500 __ cmpd(BOOL_RESULT, opr1->as_register_lo(), opr2->as_register_lo());
1501 }
1502 } else {
1503 ShouldNotReachHere();
1504 }
1505 } else {
1506 ShouldNotReachHere();
1507 }
1508 }
1509
1510
1511 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op){
1512 const Register Rdst = dst->as_register();
1513 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
1514 bool is_unordered_less = (code == lir_ucmp_fd2i);
1515 if (left->is_single_fpu()) {
1516 __ fcmpu(CCR0, left->as_float_reg(), right->as_float_reg());
1517 } else if (left->is_double_fpu()) {
1518 __ fcmpu(CCR0, left->as_double_reg(), right->as_double_reg());
1519 } else {
1520 ShouldNotReachHere();
1521 }
1522 __ set_cmpu3(Rdst, is_unordered_less); // is_unordered_less ? -1 : 1
1523 } else if (code == lir_cmp_l2i) {
1524 __ cmpd(CCR0, left->as_register_lo(), right->as_register_lo());
1525 __ set_cmp3(Rdst); // set result as follows: <: -1, =: 0, >: 1
1526 } else {
1527 ShouldNotReachHere();
1528 }
1529 }
1530
1531
1532 inline void load_to_reg(LIR_Assembler *lasm, LIR_Opr src, LIR_Opr dst) {
1533 if (src->is_constant()) {
1534 lasm->const2reg(src, dst, lir_patch_none, nullptr);
1535 } else if (src->is_register()) {
1536 lasm->reg2reg(src, dst);
1537 } else if (src->is_stack()) {
1538 lasm->stack2reg(src, dst, dst->type());
1539 } else {
1540 ShouldNotReachHere();
1541 }
1542 }
1543
1544 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type,
1545 LIR_Opr cmp_opr1, LIR_Opr cmp_opr2) {
1546 assert(cmp_opr1 == LIR_OprFact::illegalOpr && cmp_opr2 == LIR_OprFact::illegalOpr, "unnecessary cmp oprs on ppc");
1547
1548 if (opr1->is_equal(opr2) || opr1->is_same_register(opr2)) {
1549 load_to_reg(this, opr1, result); // Condition doesn't matter.
1550 return;
1551 }
1552
1553 bool positive = false;
1554 Assembler::Condition cond = Assembler::equal;
1555 switch (condition) {
1556 case lir_cond_equal: positive = true ; cond = Assembler::equal ; break;
1557 case lir_cond_notEqual: positive = false; cond = Assembler::equal ; break;
1558 case lir_cond_less: positive = true ; cond = Assembler::less ; break;
1559 case lir_cond_belowEqual:
1560 case lir_cond_lessEqual: positive = false; cond = Assembler::greater; break;
1561 case lir_cond_greater: positive = true ; cond = Assembler::greater; break;
1562 case lir_cond_aboveEqual:
1563 case lir_cond_greaterEqual: positive = false; cond = Assembler::less ; break;
1564 default: ShouldNotReachHere();
1565 }
1566
1567 // Try to use isel on >=Power7.
1568 if (VM_Version::has_isel() && result->is_cpu_register()) {
1569 bool o1_is_reg = opr1->is_cpu_register(), o2_is_reg = opr2->is_cpu_register();
1570 const Register result_reg = result->is_single_cpu() ? result->as_register() : result->as_register_lo();
1571
1572 // We can use result_reg to load one operand if not already in register.
1573 Register first = o1_is_reg ? (opr1->is_single_cpu() ? opr1->as_register() : opr1->as_register_lo()) : result_reg,
1574 second = o2_is_reg ? (opr2->is_single_cpu() ? opr2->as_register() : opr2->as_register_lo()) : result_reg;
1575
1576 if (first != second) {
1577 if (!o1_is_reg) {
1578 load_to_reg(this, opr1, result);
1579 }
1580
1581 if (!o2_is_reg) {
1582 load_to_reg(this, opr2, result);
1583 }
1584
1585 __ isel(result_reg, BOOL_RESULT, cond, !positive, first, second);
1586 return;
1587 }
1588 } // isel
1589
1590 load_to_reg(this, opr1, result);
1591
1592 Label skip;
1593 int bo = positive ? Assembler::bcondCRbiIs1 : Assembler::bcondCRbiIs0;
1594 int bi = Assembler::bi0(BOOL_RESULT, cond);
1595 __ bc(bo, bi, skip);
1596
1597 load_to_reg(this, opr2, result);
1598 __ bind(skip);
1599 }
1600
1601
1602 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest,
1603 CodeEmitInfo* info, bool pop_fpu_stack) {
1604 assert(info == nullptr, "unused on this code path");
1605 assert(left->is_register(), "wrong items state");
1606 assert(dest->is_register(), "wrong items state");
1607
1608 if (right->is_register()) {
1609 if (dest->is_float_kind()) {
1610
1611 FloatRegister lreg, rreg, res;
1612 if (right->is_single_fpu()) {
1613 lreg = left->as_float_reg();
1614 rreg = right->as_float_reg();
1615 res = dest->as_float_reg();
1616 switch (code) {
1617 case lir_add: __ fadds(res, lreg, rreg); break;
1618 case lir_sub: __ fsubs(res, lreg, rreg); break;
1619 case lir_mul: __ fmuls(res, lreg, rreg); break;
1620 case lir_div: __ fdivs(res, lreg, rreg); break;
1621 default: ShouldNotReachHere();
1622 }
1623 } else {
1624 lreg = left->as_double_reg();
1625 rreg = right->as_double_reg();
1626 res = dest->as_double_reg();
1627 switch (code) {
1628 case lir_add: __ fadd(res, lreg, rreg); break;
1629 case lir_sub: __ fsub(res, lreg, rreg); break;
1630 case lir_mul: __ fmul(res, lreg, rreg); break;
1631 case lir_div: __ fdiv(res, lreg, rreg); break;
1632 default: ShouldNotReachHere();
1633 }
1634 }
1635
1636 } else if (dest->is_double_cpu()) {
1637
1638 Register dst_lo = dest->as_register_lo();
1639 Register op1_lo = left->as_pointer_register();
1640 Register op2_lo = right->as_pointer_register();
1641
1642 switch (code) {
1643 case lir_add: __ add(dst_lo, op1_lo, op2_lo); break;
1644 case lir_sub: __ sub(dst_lo, op1_lo, op2_lo); break;
1645 case lir_mul: __ mulld(dst_lo, op1_lo, op2_lo); break;
1646 default: ShouldNotReachHere();
1647 }
1648 } else {
1649 assert (right->is_single_cpu(), "Just Checking");
1650
1651 Register lreg = left->as_register();
1652 Register res = dest->as_register();
1653 Register rreg = right->as_register();
1654 switch (code) {
1655 case lir_add: __ add (res, lreg, rreg); break;
1656 case lir_sub: __ sub (res, lreg, rreg); break;
1657 case lir_mul: __ mullw(res, lreg, rreg); break;
1658 default: ShouldNotReachHere();
1659 }
1660 }
1661 } else {
1662 assert (right->is_constant(), "must be constant");
1663
1664 if (dest->is_single_cpu()) {
1665 Register lreg = left->as_register();
1666 Register res = dest->as_register();
1667 int simm16 = right->as_constant_ptr()->as_jint();
1668
1669 switch (code) {
1670 case lir_sub: assert(Assembler::is_simm16(-simm16), "cannot encode"); // see do_ArithmeticOp_Int
1671 simm16 = -simm16;
1672 case lir_add: if (res == lreg && simm16 == 0) break;
1673 __ addi(res, lreg, simm16); break;
1674 case lir_mul: if (res == lreg && simm16 == 1) break;
1675 __ mulli(res, lreg, simm16); break;
1676 default: ShouldNotReachHere();
1677 }
1678 } else {
1679 Register lreg = left->as_pointer_register();
1680 Register res = dest->as_register_lo();
1681 long con = right->as_constant_ptr()->as_jlong();
1682 assert(Assembler::is_simm16(con), "must be simm16");
1683
1684 switch (code) {
1685 case lir_sub: assert(Assembler::is_simm16(-con), "cannot encode"); // see do_ArithmeticOp_Long
1686 con = -con;
1687 case lir_add: if (res == lreg && con == 0) break;
1688 __ addi(res, lreg, (int)con); break;
1689 case lir_mul: if (res == lreg && con == 1) break;
1690 __ mulli(res, lreg, (int)con); break;
1691 default: ShouldNotReachHere();
1692 }
1693 }
1694 }
1695 }
1696
1697
1698 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr thread, LIR_Opr dest, LIR_Op* op) {
1699 switch (code) {
1700 case lir_sqrt: {
1701 __ fsqrt(dest->as_double_reg(), value->as_double_reg());
1702 break;
1703 }
1704 case lir_abs: {
1705 __ fabs(dest->as_double_reg(), value->as_double_reg());
1706 break;
1707 }
1708 default: {
1709 ShouldNotReachHere();
1710 break;
1711 }
1712 }
1713 }
1714
1715
1716 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest) {
1717 if (right->is_constant()) { // see do_LogicOp
1718 long uimm;
1719 Register d, l;
1720 if (dest->is_single_cpu()) {
1721 uimm = right->as_constant_ptr()->as_jint();
1722 d = dest->as_register();
1723 l = left->as_register();
1724 } else {
1725 uimm = right->as_constant_ptr()->as_jlong();
1726 d = dest->as_register_lo();
1727 l = left->as_register_lo();
1728 }
1729 long uimms = (unsigned long)uimm >> 16,
1730 uimmss = (unsigned long)uimm >> 32;
1731
1732 switch (code) {
1733 case lir_logic_and:
1734 if (uimmss != 0 || (uimms != 0 && (uimm & 0xFFFF) != 0) || is_power_of_2(uimm)) {
1735 __ andi(d, l, uimm); // special cases
1736 } else if (uimms != 0) { __ andis_(d, l, uimms); }
1737 else { __ andi_(d, l, uimm); }
1738 break;
1739
1740 case lir_logic_or:
1741 if (uimms != 0) { assert((uimm & 0xFFFF) == 0, "sanity"); __ oris(d, l, uimms); }
1742 else { __ ori(d, l, uimm); }
1743 break;
1744
1745 case lir_logic_xor:
1746 if (uimm == -1) { __ nand(d, l, l); } // special case
1747 else if (uimms != 0) { assert((uimm & 0xFFFF) == 0, "sanity"); __ xoris(d, l, uimms); }
1748 else { __ xori(d, l, uimm); }
1749 break;
1750
1751 default: ShouldNotReachHere();
1752 }
1753 } else {
1754 assert(right->is_register(), "right should be in register");
1755
1756 if (dest->is_single_cpu()) {
1757 switch (code) {
1758 case lir_logic_and: __ andr(dest->as_register(), left->as_register(), right->as_register()); break;
1759 case lir_logic_or: __ orr (dest->as_register(), left->as_register(), right->as_register()); break;
1760 case lir_logic_xor: __ xorr(dest->as_register(), left->as_register(), right->as_register()); break;
1761 default: ShouldNotReachHere();
1762 }
1763 } else {
1764 Register l = (left->is_single_cpu() && left->is_oop_register()) ? left->as_register() :
1765 left->as_register_lo();
1766 Register r = (right->is_single_cpu() && right->is_oop_register()) ? right->as_register() :
1767 right->as_register_lo();
1768
1769 switch (code) {
1770 case lir_logic_and: __ andr(dest->as_register_lo(), l, r); break;
1771 case lir_logic_or: __ orr (dest->as_register_lo(), l, r); break;
1772 case lir_logic_xor: __ xorr(dest->as_register_lo(), l, r); break;
1773 default: ShouldNotReachHere();
1774 }
1775 }
1776 }
1777 }
1778
1779
1780 int LIR_Assembler::shift_amount(BasicType t) {
1781 int elem_size = type2aelembytes(t);
1782 switch (elem_size) {
1783 case 1 : return 0;
1784 case 2 : return 1;
1785 case 4 : return 2;
1786 case 8 : return 3;
1787 }
1788 ShouldNotReachHere();
1789 return -1;
1790 }
1791
1792
1793 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
1794 info->add_register_oop(exceptionOop);
1795
1796 // Reuse the debug info from the safepoint poll for the throw op itself.
1797 address pc_for_athrow = __ pc();
1798 int pc_for_athrow_offset = __ offset();
1799 //RelocationHolder rspec = internal_word_Relocation::spec(pc_for_athrow);
1800 //__ relocate(rspec);
1801 //__ load_const(exceptionPC->as_register(), pc_for_athrow, R0);
1802 __ calculate_address_from_global_toc(exceptionPC->as_register(), pc_for_athrow, true, true, /*add_relocation*/ true);
1803 add_call_info(pc_for_athrow_offset, info); // for exception handler
1804
1805 address stub = Runtime1::entry_for(compilation()->has_fpu_code() ? Runtime1::handle_exception_id
1806 : Runtime1::handle_exception_nofpu_id);
1807 //__ load_const_optimized(R0, stub);
1808 __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(stub));
1809 __ mtctr(R0);
1810 __ bctr();
1811 }
1812
1813
1814 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
1815 // Note: Not used with EnableDebuggingOnDemand.
1816 assert(exceptionOop->as_register() == R3, "should match");
1817 __ b(_unwind_handler_entry);
1818 }
1819
1820
1821 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
1822 Register src = op->src()->as_register();
1823 Register dst = op->dst()->as_register();
1824 Register src_pos = op->src_pos()->as_register();
1825 Register dst_pos = op->dst_pos()->as_register();
1826 Register length = op->length()->as_register();
1827 Register tmp = op->tmp()->as_register();
1828 Register tmp2 = R0;
1829
1830 int flags = op->flags();
1831 ciArrayKlass* default_type = op->expected_type();
1832 BasicType basic_type = default_type != nullptr ? default_type->element_type()->basic_type() : T_ILLEGAL;
1833 if (basic_type == T_ARRAY) basic_type = T_OBJECT;
1834
1835 // Set up the arraycopy stub information.
1836 ArrayCopyStub* stub = op->stub();
1837 const int frame_resize = frame::native_abi_reg_args_size - sizeof(frame::java_abi); // C calls need larger frame.
1838
1839 // Always do stub if no type information is available. It's ok if
1840 // the known type isn't loaded since the code sanity checks
1841 // in debug mode and the type isn't required when we know the exact type
1842 // also check that the type is an array type.
1843 if (op->expected_type() == nullptr) {
1844 assert(src->is_nonvolatile() && src_pos->is_nonvolatile() && dst->is_nonvolatile() && dst_pos->is_nonvolatile() &&
1845 length->is_nonvolatile(), "must preserve");
1846 address copyfunc_addr = StubRoutines::generic_arraycopy();
1847 assert(copyfunc_addr != nullptr, "generic arraycopy stub required");
1848
1849 // 3 parms are int. Convert to long.
1850 __ mr(R3_ARG1, src);
1851 __ extsw(R4_ARG2, src_pos);
1852 __ mr(R5_ARG3, dst);
1853 __ extsw(R6_ARG4, dst_pos);
1854 __ extsw(R7_ARG5, length);
1855
1856 #ifndef PRODUCT
1857 if (PrintC1Statistics) {
1858 address counter = (address)&Runtime1::_generic_arraycopystub_cnt;
1859 int simm16_offs = __ load_const_optimized(tmp, counter, tmp2, true);
1860 __ lwz(R11_scratch1, simm16_offs, tmp);
1861 __ addi(R11_scratch1, R11_scratch1, 1);
1862 __ stw(R11_scratch1, simm16_offs, tmp);
1863 }
1864 #endif
1865 __ call_c_with_frame_resize(copyfunc_addr, /*stub does not need resized frame*/ 0);
1866
1867 __ nand(tmp, R3_RET, R3_RET);
1868 __ subf(length, tmp, length);
1869 __ add(src_pos, tmp, src_pos);
1870 __ add(dst_pos, tmp, dst_pos);
1871
1872 __ cmpwi(CCR0, R3_RET, 0);
1873 __ bc_far_optimized(Assembler::bcondCRbiIs1, __ bi0(CCR0, Assembler::less), *stub->entry());
1874 __ bind(*stub->continuation());
1875 return;
1876 }
1877
1878 assert(default_type != nullptr && default_type->is_array_klass(), "must be true at this point");
1879 Label cont, slow, copyfunc;
1880
1881 bool simple_check_flag_set = flags & (LIR_OpArrayCopy::src_null_check |
1882 LIR_OpArrayCopy::dst_null_check |
1883 LIR_OpArrayCopy::src_pos_positive_check |
1884 LIR_OpArrayCopy::dst_pos_positive_check |
1885 LIR_OpArrayCopy::length_positive_check);
1886
1887 // Use only one conditional branch for simple checks.
1888 if (simple_check_flag_set) {
1889 ConditionRegister combined_check = CCR1, tmp_check = CCR1;
1890
1891 // Make sure src and dst are non-null.
1892 if (flags & LIR_OpArrayCopy::src_null_check) {
1893 __ cmpdi(combined_check, src, 0);
1894 tmp_check = CCR0;
1895 }
1896
1897 if (flags & LIR_OpArrayCopy::dst_null_check) {
1898 __ cmpdi(tmp_check, dst, 0);
1899 if (tmp_check != combined_check) {
1900 __ cror(combined_check, Assembler::equal, tmp_check, Assembler::equal);
1901 }
1902 tmp_check = CCR0;
1903 }
1904
1905 // Clear combined_check.eq if not already used.
1906 if (tmp_check == combined_check) {
1907 __ crandc(combined_check, Assembler::equal, combined_check, Assembler::equal);
1908 tmp_check = CCR0;
1909 }
1910
1911 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
1912 // Test src_pos register.
1913 __ cmpwi(tmp_check, src_pos, 0);
1914 __ cror(combined_check, Assembler::equal, tmp_check, Assembler::less);
1915 }
1916
1917 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
1918 // Test dst_pos register.
1919 __ cmpwi(tmp_check, dst_pos, 0);
1920 __ cror(combined_check, Assembler::equal, tmp_check, Assembler::less);
1921 }
1922
1923 if (flags & LIR_OpArrayCopy::length_positive_check) {
1924 // Make sure length isn't negative.
1925 __ cmpwi(tmp_check, length, 0);
1926 __ cror(combined_check, Assembler::equal, tmp_check, Assembler::less);
1927 }
1928
1929 __ beq(combined_check, slow);
1930 }
1931
1932 // If the compiler was not able to prove that exact type of the source or the destination
1933 // of the arraycopy is an array type, check at runtime if the source or the destination is
1934 // an instance type.
1935 if (flags & LIR_OpArrayCopy::type_check) {
1936 if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
1937 __ load_klass(tmp, dst);
1938 __ lwz(tmp2, in_bytes(Klass::layout_helper_offset()), tmp);
1939 __ cmpwi(CCR0, tmp2, Klass::_lh_neutral_value);
1940 __ bge(CCR0, slow);
1941 }
1942
1943 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
1944 __ load_klass(tmp, src);
1945 __ lwz(tmp2, in_bytes(Klass::layout_helper_offset()), tmp);
1946 __ cmpwi(CCR0, tmp2, Klass::_lh_neutral_value);
1947 __ bge(CCR0, slow);
1948 }
1949 }
1950
1951 // Higher 32bits must be null.
1952 __ extsw(length, length);
1953
1954 __ extsw(src_pos, src_pos);
1955 if (flags & LIR_OpArrayCopy::src_range_check) {
1956 __ lwz(tmp2, arrayOopDesc::length_offset_in_bytes(), src);
1957 __ add(tmp, length, src_pos);
1958 __ cmpld(CCR0, tmp2, tmp);
1959 __ ble(CCR0, slow);
1960 }
1961
1962 __ extsw(dst_pos, dst_pos);
1963 if (flags & LIR_OpArrayCopy::dst_range_check) {
1964 __ lwz(tmp2, arrayOopDesc::length_offset_in_bytes(), dst);
1965 __ add(tmp, length, dst_pos);
1966 __ cmpld(CCR0, tmp2, tmp);
1967 __ ble(CCR0, slow);
1968 }
1969
1970 int shift = shift_amount(basic_type);
1971
1972 if (!(flags & LIR_OpArrayCopy::type_check)) {
1973 __ b(cont);
1974 } else {
1975 // We don't know the array types are compatible.
1976 if (basic_type != T_OBJECT) {
1977 // Simple test for basic type arrays.
1978 if (UseCompressedClassPointers) {
1979 // We don't need decode because we just need to compare.
1980 __ lwz(tmp, oopDesc::klass_offset_in_bytes(), src);
1981 __ lwz(tmp2, oopDesc::klass_offset_in_bytes(), dst);
1982 __ cmpw(CCR0, tmp, tmp2);
1983 } else {
1984 __ ld(tmp, oopDesc::klass_offset_in_bytes(), src);
1985 __ ld(tmp2, oopDesc::klass_offset_in_bytes(), dst);
1986 __ cmpd(CCR0, tmp, tmp2);
1987 }
1988 __ beq(CCR0, cont);
1989 } else {
1990 // For object arrays, if src is a sub class of dst then we can
1991 // safely do the copy.
1992 address copyfunc_addr = StubRoutines::checkcast_arraycopy();
1993
1994 const Register sub_klass = R5, super_klass = R4; // like CheckCast/InstanceOf
1995 assert_different_registers(tmp, tmp2, sub_klass, super_klass);
1996
1997 __ load_klass(sub_klass, src);
1998 __ load_klass(super_klass, dst);
1999
2000 __ check_klass_subtype_fast_path(sub_klass, super_klass, tmp, tmp2,
2001 &cont, copyfunc_addr != nullptr ? ©func : &slow, nullptr);
2002
2003 address slow_stc = Runtime1::entry_for(Runtime1::slow_subtype_check_id);
2004 //__ load_const_optimized(tmp, slow_stc, tmp2);
2005 __ calculate_address_from_global_toc(tmp, slow_stc, true, true, false);
2006 __ mtctr(tmp);
2007 __ bctrl(); // sets CR0
2008 __ beq(CCR0, cont);
2009
2010 if (copyfunc_addr != nullptr) { // Use stub if available.
2011 __ bind(copyfunc);
2012 // Src is not a sub class of dst so we have to do a
2013 // per-element check.
2014 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
2015 if ((flags & mask) != mask) {
2016 assert(flags & mask, "one of the two should be known to be an object array");
2017
2018 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
2019 __ load_klass(tmp, src);
2020 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
2021 __ load_klass(tmp, dst);
2022 }
2023
2024 __ lwz(tmp2, in_bytes(Klass::layout_helper_offset()), tmp);
2025
2026 jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
2027 __ load_const_optimized(tmp, objArray_lh);
2028 __ cmpw(CCR0, tmp, tmp2);
2029 __ bne(CCR0, slow);
2030 }
2031
2032 Register src_ptr = R3_ARG1;
2033 Register dst_ptr = R4_ARG2;
2034 Register len = R5_ARG3;
2035 Register chk_off = R6_ARG4;
2036 Register super_k = R7_ARG5;
2037
2038 __ addi(src_ptr, src, arrayOopDesc::base_offset_in_bytes(basic_type));
2039 __ addi(dst_ptr, dst, arrayOopDesc::base_offset_in_bytes(basic_type));
2040 if (shift == 0) {
2041 __ add(src_ptr, src_pos, src_ptr);
2042 __ add(dst_ptr, dst_pos, dst_ptr);
2043 } else {
2044 __ sldi(tmp, src_pos, shift);
2045 __ sldi(tmp2, dst_pos, shift);
2046 __ add(src_ptr, tmp, src_ptr);
2047 __ add(dst_ptr, tmp2, dst_ptr);
2048 }
2049
2050 __ load_klass(tmp, dst);
2051 __ mr(len, length);
2052
2053 int ek_offset = in_bytes(ObjArrayKlass::element_klass_offset());
2054 __ ld(super_k, ek_offset, tmp);
2055
2056 int sco_offset = in_bytes(Klass::super_check_offset_offset());
2057 __ lwz(chk_off, sco_offset, super_k);
2058
2059 __ call_c_with_frame_resize(copyfunc_addr, /*stub does not need resized frame*/ 0);
2060
2061 #ifndef PRODUCT
2062 if (PrintC1Statistics) {
2063 Label failed;
2064 __ cmpwi(CCR0, R3_RET, 0);
2065 __ bne(CCR0, failed);
2066 address counter = (address)&Runtime1::_arraycopy_checkcast_cnt;
2067 int simm16_offs = __ load_const_optimized(tmp, counter, tmp2, true);
2068 __ lwz(R11_scratch1, simm16_offs, tmp);
2069 __ addi(R11_scratch1, R11_scratch1, 1);
2070 __ stw(R11_scratch1, simm16_offs, tmp);
2071 __ bind(failed);
2072 }
2073 #endif
2074
2075 __ nand(tmp, R3_RET, R3_RET);
2076 __ cmpwi(CCR0, R3_RET, 0);
2077 __ beq(CCR0, *stub->continuation());
2078
2079 #ifndef PRODUCT
2080 if (PrintC1Statistics) {
2081 address counter = (address)&Runtime1::_arraycopy_checkcast_attempt_cnt;
2082 int simm16_offs = __ load_const_optimized(tmp, counter, tmp2, true);
2083 __ lwz(R11_scratch1, simm16_offs, tmp);
2084 __ addi(R11_scratch1, R11_scratch1, 1);
2085 __ stw(R11_scratch1, simm16_offs, tmp);
2086 }
2087 #endif
2088
2089 __ subf(length, tmp, length);
2090 __ add(src_pos, tmp, src_pos);
2091 __ add(dst_pos, tmp, dst_pos);
2092 }
2093 }
2094 }
2095 __ bind(slow);
2096 __ b(*stub->entry());
2097 __ bind(cont);
2098
2099 #ifdef ASSERT
2100 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
2101 // Sanity check the known type with the incoming class. For the
2102 // primitive case the types must match exactly with src.klass and
2103 // dst.klass each exactly matching the default type. For the
2104 // object array case, if no type check is needed then either the
2105 // dst type is exactly the expected type and the src type is a
2106 // subtype which we can't check or src is the same array as dst
2107 // but not necessarily exactly of type default_type.
2108 Label known_ok, halt;
2109 metadata2reg(op->expected_type()->constant_encoding(), tmp);
2110 if (UseCompressedClassPointers) {
2111 // Tmp holds the default type. It currently comes uncompressed after the
2112 // load of a constant, so encode it.
2113 __ encode_klass_not_null(tmp);
2114 // Load the raw value of the dst klass, since we will be comparing
2115 // uncompressed values directly.
2116 __ lwz(tmp2, oopDesc::klass_offset_in_bytes(), dst);
2117 __ cmpw(CCR0, tmp, tmp2);
2118 if (basic_type != T_OBJECT) {
2119 __ bne(CCR0, halt);
2120 // Load the raw value of the src klass.
2121 __ lwz(tmp2, oopDesc::klass_offset_in_bytes(), src);
2122 __ cmpw(CCR0, tmp, tmp2);
2123 __ beq(CCR0, known_ok);
2124 } else {
2125 __ beq(CCR0, known_ok);
2126 __ cmpw(CCR0, src, dst);
2127 __ beq(CCR0, known_ok);
2128 }
2129 } else {
2130 __ ld(tmp2, oopDesc::klass_offset_in_bytes(), dst);
2131 __ cmpd(CCR0, tmp, tmp2);
2132 if (basic_type != T_OBJECT) {
2133 __ bne(CCR0, halt);
2134 // Load the raw value of the src klass.
2135 __ ld(tmp2, oopDesc::klass_offset_in_bytes(), src);
2136 __ cmpd(CCR0, tmp, tmp2);
2137 __ beq(CCR0, known_ok);
2138 } else {
2139 __ beq(CCR0, known_ok);
2140 __ cmpd(CCR0, src, dst);
2141 __ beq(CCR0, known_ok);
2142 }
2143 }
2144 __ bind(halt);
2145 __ stop("incorrect type information in arraycopy");
2146 __ bind(known_ok);
2147 }
2148 #endif
2149
2150 #ifndef PRODUCT
2151 if (PrintC1Statistics) {
2152 address counter = Runtime1::arraycopy_count_address(basic_type);
2153 int simm16_offs = __ load_const_optimized(tmp, counter, tmp2, true);
2154 __ lwz(R11_scratch1, simm16_offs, tmp);
2155 __ addi(R11_scratch1, R11_scratch1, 1);
2156 __ stw(R11_scratch1, simm16_offs, tmp);
2157 }
2158 #endif
2159
2160 Register src_ptr = R3_ARG1;
2161 Register dst_ptr = R4_ARG2;
2162 Register len = R5_ARG3;
2163
2164 __ addi(src_ptr, src, arrayOopDesc::base_offset_in_bytes(basic_type));
2165 __ addi(dst_ptr, dst, arrayOopDesc::base_offset_in_bytes(basic_type));
2166 if (shift == 0) {
2167 __ add(src_ptr, src_pos, src_ptr);
2168 __ add(dst_ptr, dst_pos, dst_ptr);
2169 } else {
2170 __ sldi(tmp, src_pos, shift);
2171 __ sldi(tmp2, dst_pos, shift);
2172 __ add(src_ptr, tmp, src_ptr);
2173 __ add(dst_ptr, tmp2, dst_ptr);
2174 }
2175
2176 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
2177 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
2178 const char *name;
2179 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
2180
2181 // Arraycopy stubs takes a length in number of elements, so don't scale it.
2182 __ mr(len, length);
2183 __ call_c_with_frame_resize(entry, /*stub does not need resized frame*/ 0);
2184
2185 __ bind(*stub->continuation());
2186 }
2187
2188
2189 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2190 if (dest->is_single_cpu()) {
2191 __ rldicl(tmp->as_register(), count->as_register(), 0, 64-5);
2192 #ifdef _LP64
2193 if (left->type() == T_OBJECT) {
2194 switch (code) {
2195 case lir_shl: __ sld(dest->as_register(), left->as_register(), tmp->as_register()); break;
2196 case lir_shr: __ srad(dest->as_register(), left->as_register(), tmp->as_register()); break;
2197 case lir_ushr: __ srd(dest->as_register(), left->as_register(), tmp->as_register()); break;
2198 default: ShouldNotReachHere();
2199 }
2200 } else
2201 #endif
2202 switch (code) {
2203 case lir_shl: __ slw(dest->as_register(), left->as_register(), tmp->as_register()); break;
2204 case lir_shr: __ sraw(dest->as_register(), left->as_register(), tmp->as_register()); break;
2205 case lir_ushr: __ srw(dest->as_register(), left->as_register(), tmp->as_register()); break;
2206 default: ShouldNotReachHere();
2207 }
2208 } else {
2209 __ rldicl(tmp->as_register(), count->as_register(), 0, 64-6);
2210 switch (code) {
2211 case lir_shl: __ sld(dest->as_register_lo(), left->as_register_lo(), tmp->as_register()); break;
2212 case lir_shr: __ srad(dest->as_register_lo(), left->as_register_lo(), tmp->as_register()); break;
2213 case lir_ushr: __ srd(dest->as_register_lo(), left->as_register_lo(), tmp->as_register()); break;
2214 default: ShouldNotReachHere();
2215 }
2216 }
2217 }
2218
2219
2220 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2221 #ifdef _LP64
2222 if (left->type() == T_OBJECT) {
2223 count = count & 63; // Shouldn't shift by more than sizeof(intptr_t).
2224 if (count == 0) { __ mr_if_needed(dest->as_register_lo(), left->as_register()); }
2225 else {
2226 switch (code) {
2227 case lir_shl: __ sldi(dest->as_register_lo(), left->as_register(), count); break;
2228 case lir_shr: __ sradi(dest->as_register_lo(), left->as_register(), count); break;
2229 case lir_ushr: __ srdi(dest->as_register_lo(), left->as_register(), count); break;
2230 default: ShouldNotReachHere();
2231 }
2232 }
2233 return;
2234 }
2235 #endif
2236
2237 if (dest->is_single_cpu()) {
2238 count = count & 0x1F; // Java spec
2239 if (count == 0) { __ mr_if_needed(dest->as_register(), left->as_register()); }
2240 else {
2241 switch (code) {
2242 case lir_shl: __ slwi(dest->as_register(), left->as_register(), count); break;
2243 case lir_shr: __ srawi(dest->as_register(), left->as_register(), count); break;
2244 case lir_ushr: __ srwi(dest->as_register(), left->as_register(), count); break;
2245 default: ShouldNotReachHere();
2246 }
2247 }
2248 } else if (dest->is_double_cpu()) {
2249 count = count & 63; // Java spec
2250 if (count == 0) { __ mr_if_needed(dest->as_pointer_register(), left->as_pointer_register()); }
2251 else {
2252 switch (code) {
2253 case lir_shl: __ sldi(dest->as_pointer_register(), left->as_pointer_register(), count); break;
2254 case lir_shr: __ sradi(dest->as_pointer_register(), left->as_pointer_register(), count); break;
2255 case lir_ushr: __ srdi(dest->as_pointer_register(), left->as_pointer_register(), count); break;
2256 default: ShouldNotReachHere();
2257 }
2258 }
2259 } else {
2260 ShouldNotReachHere();
2261 }
2262 }
2263
2264
2265 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
2266 if (op->init_check()) {
2267 if (!os::zero_page_read_protected() || !ImplicitNullChecks) {
2268 explicit_null_check(op->klass()->as_register(), op->stub()->info());
2269 } else {
2270 add_debug_info_for_null_check_here(op->stub()->info());
2271 }
2272 __ lbz(op->tmp1()->as_register(),
2273 in_bytes(InstanceKlass::init_state_offset()), op->klass()->as_register());
2274 __ cmpwi(CCR0, op->tmp1()->as_register(), InstanceKlass::fully_initialized);
2275 __ bc_far_optimized(Assembler::bcondCRbiIs0, __ bi0(CCR0, Assembler::equal), *op->stub()->entry());
2276 }
2277 __ allocate_object(op->obj()->as_register(),
2278 op->tmp1()->as_register(),
2279 op->tmp2()->as_register(),
2280 op->tmp3()->as_register(),
2281 op->header_size(),
2282 op->object_size(),
2283 op->klass()->as_register(),
2284 *op->stub()->entry());
2285
2286 __ bind(*op->stub()->continuation());
2287 __ verify_oop(op->obj()->as_register(), FILE_AND_LINE);
2288 }
2289
2290
2291 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
2292 LP64_ONLY( __ extsw(op->len()->as_register(), op->len()->as_register()); )
2293 if (UseSlowPath ||
2294 (!UseFastNewObjectArray && (is_reference_type(op->type()))) ||
2295 (!UseFastNewTypeArray && (!is_reference_type(op->type())))) {
2296 __ b(*op->stub()->entry());
2297 } else {
2298 __ allocate_array(op->obj()->as_register(),
2299 op->len()->as_register(),
2300 op->tmp1()->as_register(),
2301 op->tmp2()->as_register(),
2302 op->tmp3()->as_register(),
2303 arrayOopDesc::header_size(op->type()),
2304 type2aelembytes(op->type()),
2305 op->klass()->as_register(),
2306 *op->stub()->entry());
2307 }
2308 __ bind(*op->stub()->continuation());
2309 }
2310
2311
2312 void LIR_Assembler::type_profile_helper(Register mdo, int mdo_offset_bias,
2313 ciMethodData *md, ciProfileData *data,
2314 Register recv, Register tmp1, Label* update_done) {
2315 uint i;
2316 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2317 Label next_test;
2318 // See if the receiver is receiver[n].
2319 __ ld(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) - mdo_offset_bias, mdo);
2320 __ verify_klass_ptr(tmp1);
2321 __ cmpd(CCR0, recv, tmp1);
2322 __ bne(CCR0, next_test);
2323
2324 __ ld(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2325 __ addi(tmp1, tmp1, DataLayout::counter_increment);
2326 __ std(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2327 __ b(*update_done);
2328
2329 __ bind(next_test);
2330 }
2331
2332 // Didn't find receiver; find next empty slot and fill it in.
2333 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2334 Label next_test;
2335 __ ld(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) - mdo_offset_bias, mdo);
2336 __ cmpdi(CCR0, tmp1, 0);
2337 __ bne(CCR0, next_test);
2338 __ li(tmp1, DataLayout::counter_increment);
2339 __ std(recv, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) - mdo_offset_bias, mdo);
2340 __ std(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2341 __ b(*update_done);
2342
2343 __ bind(next_test);
2344 }
2345 }
2346
2347
2348 void LIR_Assembler::setup_md_access(ciMethod* method, int bci,
2349 ciMethodData*& md, ciProfileData*& data, int& mdo_offset_bias) {
2350 md = method->method_data_or_null();
2351 assert(md != nullptr, "Sanity");
2352 data = md->bci_to_data(bci);
2353 assert(data != nullptr, "need data for checkcast");
2354 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
2355 if (!Assembler::is_simm16(md->byte_offset_of_slot(data, DataLayout::header_offset()) + data->size_in_bytes())) {
2356 // The offset is large so bias the mdo by the base of the slot so
2357 // that the ld can use simm16s to reference the slots of the data.
2358 mdo_offset_bias = md->byte_offset_of_slot(data, DataLayout::header_offset());
2359 }
2360 }
2361
2362
2363 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
2364 const Register obj = op->object()->as_register(); // Needs to live in this register at safepoint (patching stub).
2365 Register k_RInfo = op->tmp1()->as_register();
2366 Register klass_RInfo = op->tmp2()->as_register();
2367 Register Rtmp1 = op->tmp3()->as_register();
2368 Register dst = op->result_opr()->as_register();
2369 ciKlass* k = op->klass();
2370 bool should_profile = op->should_profile();
2371 // Attention: do_temp(opTypeCheck->_object) is not used, i.e. obj may be same as one of the temps.
2372 bool reg_conflict = false;
2373 if (obj == k_RInfo) {
2374 k_RInfo = dst;
2375 reg_conflict = true;
2376 } else if (obj == klass_RInfo) {
2377 klass_RInfo = dst;
2378 reg_conflict = true;
2379 } else if (obj == Rtmp1) {
2380 Rtmp1 = dst;
2381 reg_conflict = true;
2382 }
2383 assert_different_registers(obj, k_RInfo, klass_RInfo, Rtmp1);
2384
2385 __ cmpdi(CCR0, obj, 0);
2386
2387 ciMethodData* md = nullptr;
2388 ciProfileData* data = nullptr;
2389 int mdo_offset_bias = 0;
2390 if (should_profile) {
2391 ciMethod* method = op->profiled_method();
2392 assert(method != nullptr, "Should have method");
2393 setup_md_access(method, op->profiled_bci(), md, data, mdo_offset_bias);
2394
2395 Register mdo = k_RInfo;
2396 Register data_val = Rtmp1;
2397 Label not_null;
2398 __ bne(CCR0, not_null);
2399 metadata2reg(md->constant_encoding(), mdo);
2400 __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2401 __ lbz(data_val, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias, mdo);
2402 __ ori(data_val, data_val, BitData::null_seen_byte_constant());
2403 __ stb(data_val, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias, mdo);
2404 __ b(*obj_is_null);
2405 __ bind(not_null);
2406 } else {
2407 __ beq(CCR0, *obj_is_null);
2408 }
2409
2410 // get object class
2411 __ load_klass(klass_RInfo, obj);
2412
2413 if (k->is_loaded()) {
2414 metadata2reg(k->constant_encoding(), k_RInfo);
2415 } else {
2416 klass2reg_with_patching(k_RInfo, op->info_for_patch());
2417 }
2418
2419 Label profile_cast_failure, failure_restore_obj, profile_cast_success;
2420 Label *failure_target = should_profile ? &profile_cast_failure : failure;
2421 Label *success_target = should_profile ? &profile_cast_success : success;
2422
2423 if (op->fast_check()) {
2424 assert_different_registers(klass_RInfo, k_RInfo);
2425 __ cmpd(CCR0, k_RInfo, klass_RInfo);
2426 if (should_profile) {
2427 __ bne(CCR0, *failure_target);
2428 // Fall through to success case.
2429 } else {
2430 __ beq(CCR0, *success);
2431 // Fall through to failure case.
2432 }
2433 } else {
2434 bool need_slow_path = true;
2435 if (k->is_loaded()) {
2436 if ((int) k->super_check_offset() != in_bytes(Klass::secondary_super_cache_offset())) {
2437 need_slow_path = false;
2438 }
2439 // Perform the fast part of the checking logic.
2440 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, R0, (need_slow_path ? success_target : nullptr),
2441 failure_target, nullptr, RegisterOrConstant(k->super_check_offset()));
2442 } else {
2443 // Perform the fast part of the checking logic.
2444 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, R0, success_target, failure_target);
2445 }
2446 if (!need_slow_path) {
2447 if (!should_profile) { __ b(*success); }
2448 } else {
2449 // Call out-of-line instance of __ check_klass_subtype_slow_path(...):
2450 address entry = Runtime1::entry_for(Runtime1::slow_subtype_check_id);
2451 // Stub needs fixed registers (tmp1-3).
2452 Register original_k_RInfo = op->tmp1()->as_register();
2453 Register original_klass_RInfo = op->tmp2()->as_register();
2454 Register original_Rtmp1 = op->tmp3()->as_register();
2455 bool keep_obj_alive = reg_conflict && (op->code() == lir_checkcast);
2456 bool keep_klass_RInfo_alive = (obj == original_klass_RInfo) && should_profile;
2457 if (keep_obj_alive && (obj != original_Rtmp1)) { __ mr(R0, obj); }
2458 __ mr_if_needed(original_k_RInfo, k_RInfo);
2459 __ mr_if_needed(original_klass_RInfo, klass_RInfo);
2460 if (keep_obj_alive) { __ mr(dst, (obj == original_Rtmp1) ? obj : R0); }
2461 //__ load_const_optimized(original_Rtmp1, entry, R0);
2462 __ calculate_address_from_global_toc(original_Rtmp1, entry, true, true, false);
2463 __ mtctr(original_Rtmp1);
2464 __ bctrl(); // sets CR0
2465 if (keep_obj_alive) {
2466 if (keep_klass_RInfo_alive) { __ mr(R0, obj); }
2467 __ mr(obj, dst);
2468 }
2469 if (should_profile) {
2470 __ bne(CCR0, *failure_target);
2471 if (keep_klass_RInfo_alive) { __ mr(klass_RInfo, keep_obj_alive ? R0 : obj); }
2472 // Fall through to success case.
2473 } else {
2474 __ beq(CCR0, *success);
2475 // Fall through to failure case.
2476 }
2477 }
2478 }
2479
2480 if (should_profile) {
2481 Register mdo = k_RInfo, recv = klass_RInfo;
2482 assert_different_registers(mdo, recv, Rtmp1);
2483 __ bind(profile_cast_success);
2484 metadata2reg(md->constant_encoding(), mdo);
2485 __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2486 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, Rtmp1, success);
2487 __ b(*success);
2488
2489 // Cast failure case.
2490 __ bind(profile_cast_failure);
2491 metadata2reg(md->constant_encoding(), mdo);
2492 __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2493 __ ld(Rtmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2494 __ addi(Rtmp1, Rtmp1, -DataLayout::counter_increment);
2495 __ std(Rtmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2496 }
2497
2498 __ bind(*failure);
2499 }
2500
2501
2502 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
2503 LIR_Code code = op->code();
2504 if (code == lir_store_check) {
2505 Register value = op->object()->as_register();
2506 Register array = op->array()->as_register();
2507 Register k_RInfo = op->tmp1()->as_register();
2508 Register klass_RInfo = op->tmp2()->as_register();
2509 Register Rtmp1 = op->tmp3()->as_register();
2510 bool should_profile = op->should_profile();
2511
2512 __ verify_oop(value, FILE_AND_LINE);
2513 CodeStub* stub = op->stub();
2514 // Check if it needs to be profiled.
2515 ciMethodData* md = nullptr;
2516 ciProfileData* data = nullptr;
2517 int mdo_offset_bias = 0;
2518 if (should_profile) {
2519 ciMethod* method = op->profiled_method();
2520 assert(method != nullptr, "Should have method");
2521 setup_md_access(method, op->profiled_bci(), md, data, mdo_offset_bias);
2522 }
2523 Label profile_cast_success, failure, done;
2524 Label *success_target = should_profile ? &profile_cast_success : &done;
2525
2526 __ cmpdi(CCR0, value, 0);
2527 if (should_profile) {
2528 Label not_null;
2529 __ bne(CCR0, not_null);
2530 Register mdo = k_RInfo;
2531 Register data_val = Rtmp1;
2532 metadata2reg(md->constant_encoding(), mdo);
2533 __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2534 __ lbz(data_val, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias, mdo);
2535 __ ori(data_val, data_val, BitData::null_seen_byte_constant());
2536 __ stb(data_val, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias, mdo);
2537 __ b(done);
2538 __ bind(not_null);
2539 } else {
2540 __ beq(CCR0, done);
2541 }
2542 if (!os::zero_page_read_protected() || !ImplicitNullChecks) {
2543 explicit_null_check(array, op->info_for_exception());
2544 } else {
2545 add_debug_info_for_null_check_here(op->info_for_exception());
2546 }
2547 __ load_klass(k_RInfo, array);
2548 __ load_klass(klass_RInfo, value);
2549
2550 // Get instance klass.
2551 __ ld(k_RInfo, in_bytes(ObjArrayKlass::element_klass_offset()), k_RInfo);
2552 // Perform the fast part of the checking logic.
2553 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, R0, success_target, &failure, nullptr);
2554
2555 // Call out-of-line instance of __ check_klass_subtype_slow_path(...):
2556 const address slow_path = Runtime1::entry_for(Runtime1::slow_subtype_check_id);
2557 //__ load_const_optimized(R0, slow_path);
2558 __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(slow_path));
2559 __ mtctr(R0);
2560 __ bctrl(); // sets CR0
2561 if (!should_profile) {
2562 __ beq(CCR0, done);
2563 __ bind(failure);
2564 } else {
2565 __ bne(CCR0, failure);
2566 // Fall through to the success case.
2567
2568 Register mdo = klass_RInfo, recv = k_RInfo, tmp1 = Rtmp1;
2569 assert_different_registers(value, mdo, recv, tmp1);
2570 __ bind(profile_cast_success);
2571 metadata2reg(md->constant_encoding(), mdo);
2572 __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2573 __ load_klass(recv, value);
2574 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, &done);
2575 __ b(done);
2576
2577 // Cast failure case.
2578 __ bind(failure);
2579 metadata2reg(md->constant_encoding(), mdo);
2580 __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2581 Address data_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias);
2582 __ ld(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2583 __ addi(tmp1, tmp1, -DataLayout::counter_increment);
2584 __ std(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2585 }
2586 __ b(*stub->entry());
2587 __ bind(done);
2588
2589 } else if (code == lir_checkcast) {
2590 Label success, failure;
2591 emit_typecheck_helper(op, &success, /*fallthru*/&failure, &success);
2592 __ b(*op->stub()->entry());
2593 __ align(32, 12);
2594 __ bind(success);
2595 __ mr_if_needed(op->result_opr()->as_register(), op->object()->as_register());
2596 } else if (code == lir_instanceof) {
2597 Register dst = op->result_opr()->as_register();
2598 Label success, failure, done;
2599 emit_typecheck_helper(op, &success, /*fallthru*/&failure, &failure);
2600 __ li(dst, 0);
2601 __ b(done);
2602 __ align(32, 12);
2603 __ bind(success);
2604 __ li(dst, 1);
2605 __ bind(done);
2606 } else {
2607 ShouldNotReachHere();
2608 }
2609 }
2610
2611
2612 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
2613 Register addr = op->addr()->as_pointer_register();
2614 Register cmp_value = noreg, new_value = noreg;
2615 bool is_64bit = false;
2616
2617 if (op->code() == lir_cas_long) {
2618 cmp_value = op->cmp_value()->as_register_lo();
2619 new_value = op->new_value()->as_register_lo();
2620 is_64bit = true;
2621 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj) {
2622 cmp_value = op->cmp_value()->as_register();
2623 new_value = op->new_value()->as_register();
2624 if (op->code() == lir_cas_obj) {
2625 if (UseCompressedOops) {
2626 Register t1 = op->tmp1()->as_register();
2627 Register t2 = op->tmp2()->as_register();
2628 cmp_value = __ encode_heap_oop(t1, cmp_value);
2629 new_value = __ encode_heap_oop(t2, new_value);
2630 } else {
2631 is_64bit = true;
2632 }
2633 }
2634 } else {
2635 Unimplemented();
2636 }
2637
2638 // There might be a volatile load before this Unsafe CAS.
2639 if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
2640 __ sync();
2641 } else {
2642 __ lwsync();
2643 }
2644
2645 if (is_64bit) {
2646 __ cmpxchgd(BOOL_RESULT, /*current_value=*/R0, cmp_value, new_value, addr,
2647 MacroAssembler::MemBarNone,
2648 MacroAssembler::cmpxchgx_hint_atomic_update(),
2649 noreg, nullptr, /*check without ldarx first*/true);
2650 } else {
2651 __ cmpxchgw(BOOL_RESULT, /*current_value=*/R0, cmp_value, new_value, addr,
2652 MacroAssembler::MemBarNone,
2653 MacroAssembler::cmpxchgx_hint_atomic_update(),
2654 noreg, /*check without ldarx first*/true);
2655 }
2656
2657 if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
2658 __ isync();
2659 } else {
2660 __ sync();
2661 }
2662 }
2663
2664 void LIR_Assembler::breakpoint() {
2665 __ illtrap();
2666 }
2667
2668
2669 void LIR_Assembler::push(LIR_Opr opr) {
2670 Unimplemented();
2671 }
2672
2673 void LIR_Assembler::pop(LIR_Opr opr) {
2674 Unimplemented();
2675 }
2676
2677
2678 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst_opr) {
2679 Address mon_addr = frame_map()->address_for_monitor_lock(monitor_no);
2680 Register dst = dst_opr->as_register();
2681 Register reg = mon_addr.base();
2682 int offset = mon_addr.disp();
2683 // Compute pointer to BasicLock.
2684 __ add_const_optimized(dst, reg, offset);
2685 }
2686
2687
2688 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
2689 Register obj = op->obj_opr()->as_register();
2690 Register hdr = op->hdr_opr()->as_register();
2691 Register lock = op->lock_opr()->as_register();
2692
2693 // Obj may not be an oop.
2694 if (op->code() == lir_lock) {
2695 MonitorEnterStub* stub = (MonitorEnterStub*)op->stub();
2696 if (LockingMode != LM_MONITOR) {
2697 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2698 // Add debug info for NullPointerException only if one is possible.
2699 if (op->info() != nullptr) {
2700 if (!os::zero_page_read_protected() || !ImplicitNullChecks) {
2701 explicit_null_check(obj, op->info());
2702 } else {
2703 add_debug_info_for_null_check_here(op->info());
2704 }
2705 }
2706 __ lock_object(hdr, obj, lock, op->scratch_opr()->as_register(), *op->stub()->entry());
2707 } else {
2708 // always do slow locking
2709 // note: The slow locking code could be inlined here, however if we use
2710 // slow locking, speed doesn't matter anyway and this solution is
2711 // simpler and requires less duplicated code - additionally, the
2712 // slow locking code is the same in either case which simplifies
2713 // debugging.
2714 if (op->info() != nullptr) {
2715 add_debug_info_for_null_check_here(op->info());
2716 __ null_check(obj);
2717 }
2718 __ b(*op->stub()->entry());
2719 }
2720 } else {
2721 assert (op->code() == lir_unlock, "Invalid code, expected lir_unlock");
2722 if (LockingMode != LM_MONITOR) {
2723 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2724 __ unlock_object(hdr, obj, lock, *op->stub()->entry());
2725 } else {
2726 // always do slow unlocking
2727 // note: The slow unlocking code could be inlined here, however if we use
2728 // slow unlocking, speed doesn't matter anyway and this solution is
2729 // simpler and requires less duplicated code - additionally, the
2730 // slow unlocking code is the same in either case which simplifies
2731 // debugging.
2732 __ b(*op->stub()->entry());
2733 }
2734 }
2735 __ bind(*op->stub()->continuation());
2736 }
2737
2738 void LIR_Assembler::emit_load_klass(LIR_OpLoadKlass* op) {
2739 Register obj = op->obj()->as_pointer_register();
2740 Register result = op->result_opr()->as_pointer_register();
2741
2742 CodeEmitInfo* info = op->info();
2743 if (info != nullptr) {
2744 if (!os::zero_page_read_protected() || !ImplicitNullChecks) {
2745 explicit_null_check(obj, info);
2746 } else {
2747 add_debug_info_for_null_check_here(info);
2748 }
2749 }
2750
2751 if (UseCompressedClassPointers) {
2752 __ lwz(result, oopDesc::klass_offset_in_bytes(), obj);
2753 __ decode_klass_not_null(result);
2754 } else {
2755 __ ld(result, oopDesc::klass_offset_in_bytes(), obj);
2756 }
2757 }
2758
2759 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
2760 ciMethod* method = op->profiled_method();
2761 int bci = op->profiled_bci();
2762 ciMethod* callee = op->profiled_callee();
2763
2764 // Update counter for all call types.
2765 ciMethodData* md = method->method_data_or_null();
2766 assert(md != nullptr, "Sanity");
2767 ciProfileData* data = md->bci_to_data(bci);
2768 assert(data != nullptr && data->is_CounterData(), "need CounterData for calls");
2769 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
2770 Register mdo = op->mdo()->as_register();
2771 #ifdef _LP64
2772 assert(op->tmp1()->is_double_cpu(), "tmp1 must be allocated");
2773 Register tmp1 = op->tmp1()->as_register_lo();
2774 #else
2775 assert(op->tmp1()->is_single_cpu(), "tmp1 must be allocated");
2776 Register tmp1 = op->tmp1()->as_register();
2777 #endif
2778 metadata2reg(md->constant_encoding(), mdo);
2779 int mdo_offset_bias = 0;
2780 if (!Assembler::is_simm16(md->byte_offset_of_slot(data, CounterData::count_offset()) +
2781 data->size_in_bytes())) {
2782 // The offset is large so bias the mdo by the base of the slot so
2783 // that the ld can use simm16s to reference the slots of the data.
2784 mdo_offset_bias = md->byte_offset_of_slot(data, CounterData::count_offset());
2785 __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2786 }
2787
2788 // Perform additional virtual call profiling for invokevirtual and
2789 // invokeinterface bytecodes
2790 if (op->should_profile_receiver_type()) {
2791 assert(op->recv()->is_single_cpu(), "recv must be allocated");
2792 Register recv = op->recv()->as_register();
2793 assert_different_registers(mdo, tmp1, recv);
2794 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
2795 ciKlass* known_klass = op->known_holder();
2796 if (C1OptimizeVirtualCallProfiling && known_klass != nullptr) {
2797 // We know the type that will be seen at this call site; we can
2798 // statically update the MethodData* rather than needing to do
2799 // dynamic tests on the receiver type.
2800
2801 // NOTE: we should probably put a lock around this search to
2802 // avoid collisions by concurrent compilations.
2803 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
2804 uint i;
2805 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2806 ciKlass* receiver = vc_data->receiver(i);
2807 if (known_klass->equals(receiver)) {
2808 __ ld(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2809 __ addi(tmp1, tmp1, DataLayout::counter_increment);
2810 __ std(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2811 return;
2812 }
2813 }
2814
2815 // Receiver type not found in profile data; select an empty slot.
2816
2817 // Note that this is less efficient than it should be because it
2818 // always does a write to the receiver part of the
2819 // VirtualCallData rather than just the first time.
2820 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2821 ciKlass* receiver = vc_data->receiver(i);
2822 if (receiver == nullptr) {
2823 metadata2reg(known_klass->constant_encoding(), tmp1);
2824 __ std(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)) - mdo_offset_bias, mdo);
2825
2826 __ ld(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2827 __ addi(tmp1, tmp1, DataLayout::counter_increment);
2828 __ std(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2829 return;
2830 }
2831 }
2832 } else {
2833 __ load_klass(recv, recv);
2834 Label update_done;
2835 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, &update_done);
2836 // Receiver did not match any saved receiver and there is no empty row for it.
2837 // Increment total counter to indicate polymorphic case.
2838 __ ld(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2839 __ addi(tmp1, tmp1, DataLayout::counter_increment);
2840 __ std(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2841
2842 __ bind(update_done);
2843 }
2844 } else {
2845 // Static call
2846 __ ld(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2847 __ addi(tmp1, tmp1, DataLayout::counter_increment);
2848 __ std(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2849 }
2850 }
2851
2852
2853 void LIR_Assembler::align_backward_branch_target() {
2854 __ align(32, 12); // Insert up to 3 nops to align with 32 byte boundary.
2855 }
2856
2857
2858 void LIR_Assembler::emit_delay(LIR_OpDelay* op) {
2859 Unimplemented();
2860 }
2861
2862
2863 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) {
2864 // tmp must be unused
2865 assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2866 assert(left->is_register(), "can only handle registers");
2867
2868 if (left->is_single_cpu()) {
2869 __ neg(dest->as_register(), left->as_register());
2870 } else if (left->is_single_fpu()) {
2871 __ fneg(dest->as_float_reg(), left->as_float_reg());
2872 } else if (left->is_double_fpu()) {
2873 __ fneg(dest->as_double_reg(), left->as_double_reg());
2874 } else {
2875 assert (left->is_double_cpu(), "Must be a long");
2876 __ neg(dest->as_register_lo(), left->as_register_lo());
2877 }
2878 }
2879
2880
2881 void LIR_Assembler::rt_call(LIR_Opr result, address dest,
2882 const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
2883 // Stubs: Called via rt_call, but dest is a stub address (no function descriptor).
2884 if (dest == Runtime1::entry_for(Runtime1::register_finalizer_id) ||
2885 dest == Runtime1::entry_for(Runtime1::new_multi_array_id )) {
2886 //__ load_const_optimized(R0, dest);
2887 __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(dest));
2888 __ mtctr(R0);
2889 __ bctrl();
2890 assert(info != nullptr, "sanity");
2891 add_call_info_here(info);
2892 __ post_call_nop();
2893 return;
2894 }
2895
2896 __ call_c_with_frame_resize(dest, /*no resizing*/ 0);
2897 if (info != nullptr) {
2898 add_call_info_here(info);
2899 }
2900 __ post_call_nop();
2901 }
2902
2903
2904 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
2905 ShouldNotReachHere(); // Not needed on _LP64.
2906 }
2907
2908 void LIR_Assembler::membar() {
2909 __ fence();
2910 }
2911
2912 void LIR_Assembler::membar_acquire() {
2913 __ acquire();
2914 }
2915
2916 void LIR_Assembler::membar_release() {
2917 __ release();
2918 }
2919
2920 void LIR_Assembler::membar_loadload() {
2921 __ membar(Assembler::LoadLoad);
2922 }
2923
2924 void LIR_Assembler::membar_storestore() {
2925 __ membar(Assembler::StoreStore);
2926 }
2927
2928 void LIR_Assembler::membar_loadstore() {
2929 __ membar(Assembler::LoadStore);
2930 }
2931
2932 void LIR_Assembler::membar_storeload() {
2933 __ membar(Assembler::StoreLoad);
2934 }
2935
2936 void LIR_Assembler::on_spin_wait() {
2937 Unimplemented();
2938 }
2939
2940 void LIR_Assembler::leal(LIR_Opr addr_opr, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
2941 LIR_Address* addr = addr_opr->as_address_ptr();
2942 assert(addr->scale() == LIR_Address::times_1, "no scaling on this platform");
2943
2944 if (addr->index()->is_illegal()) {
2945 if (patch_code != lir_patch_none) {
2946 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::access_field_id);
2947 __ load_const32(R0, 0); // patchable int
2948 __ add(dest->as_pointer_register(), addr->base()->as_pointer_register(), R0);
2949 patching_epilog(patch, patch_code, addr->base()->as_register(), info);
2950 } else {
2951 __ add_const_optimized(dest->as_pointer_register(), addr->base()->as_pointer_register(), addr->disp());
2952 }
2953 } else {
2954 assert(patch_code == lir_patch_none, "Patch code not supported");
2955 assert(addr->disp() == 0, "can't have both: index and disp");
2956 __ add(dest->as_pointer_register(), addr->index()->as_pointer_register(), addr->base()->as_pointer_register());
2957 }
2958 }
2959
2960
2961 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
2962 ShouldNotReachHere();
2963 }
2964
2965
2966 #ifdef ASSERT
2967 // Emit run-time assertion.
2968 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
2969 Unimplemented();
2970 }
2971 #endif
2972
2973
2974 void LIR_Assembler::peephole(LIR_List* lir) {
2975 // Optimize instruction pairs before emitting.
2976 LIR_OpList* inst = lir->instructions_list();
2977 for (int i = 1; i < inst->length(); i++) {
2978 LIR_Op* op = inst->at(i);
2979
2980 // 2 register-register-moves
2981 if (op->code() == lir_move) {
2982 LIR_Opr in2 = ((LIR_Op1*)op)->in_opr(),
2983 res2 = ((LIR_Op1*)op)->result_opr();
2984 if (in2->is_register() && res2->is_register()) {
2985 LIR_Op* prev = inst->at(i - 1);
2986 if (prev && prev->code() == lir_move) {
2987 LIR_Opr in1 = ((LIR_Op1*)prev)->in_opr(),
2988 res1 = ((LIR_Op1*)prev)->result_opr();
2989 if (in1->is_same_register(res2) && in2->is_same_register(res1)) {
2990 inst->remove_at(i);
2991 }
2992 }
2993 }
2994 }
2995
2996 }
2997 return;
2998 }
2999
3000
3001 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) {
3002 const LIR_Address *addr = src->as_address_ptr();
3003 assert(addr->disp() == 0 && addr->index()->is_illegal(), "use leal!");
3004 const Register Rptr = addr->base()->as_pointer_register(),
3005 Rtmp = tmp->as_register();
3006 Register Robj = noreg;
3007 if (data->is_oop()) {
3008 if (UseCompressedOops) {
3009 Robj = __ encode_heap_oop(Rtmp, data->as_register());
3010 } else {
3011 Robj = data->as_register();
3012 if (Robj == dest->as_register()) { // May happen with ZGC.
3013 __ mr(Rtmp, Robj);
3014 Robj = Rtmp;
3015 }
3016 }
3017 }
3018
3019 // There might be a volatile load before this Unsafe OP.
3020 if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
3021 __ sync();
3022 } else {
3023 __ lwsync();
3024 }
3025
3026 Label Lretry;
3027 __ bind(Lretry);
3028
3029 if (data->type() == T_INT) {
3030 const Register Rold = dest->as_register(),
3031 Rsrc = data->as_register();
3032 assert_different_registers(Rptr, Rtmp, Rold, Rsrc);
3033 __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3034 if (code == lir_xadd) {
3035 __ add(Rtmp, Rsrc, Rold);
3036 __ stwcx_(Rtmp, Rptr);
3037 } else {
3038 __ stwcx_(Rsrc, Rptr);
3039 }
3040 } else if (data->is_oop()) {
3041 assert(code == lir_xchg, "xadd for oops");
3042 const Register Rold = dest->as_register();
3043 assert_different_registers(Rptr, Rold, Robj);
3044 if (UseCompressedOops) {
3045 __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3046 __ stwcx_(Robj, Rptr);
3047 } else {
3048 __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3049 __ stdcx_(Robj, Rptr);
3050 }
3051 } else if (data->type() == T_LONG) {
3052 const Register Rold = dest->as_register_lo(),
3053 Rsrc = data->as_register_lo();
3054 assert_different_registers(Rptr, Rtmp, Rold, Rsrc);
3055 __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3056 if (code == lir_xadd) {
3057 __ add(Rtmp, Rsrc, Rold);
3058 __ stdcx_(Rtmp, Rptr);
3059 } else {
3060 __ stdcx_(Rsrc, Rptr);
3061 }
3062 } else {
3063 ShouldNotReachHere();
3064 }
3065
3066 if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
3067 __ bne_predict_not_taken(CCR0, Lretry);
3068 } else {
3069 __ bne( CCR0, Lretry);
3070 }
3071
3072 if (UseCompressedOops && data->is_oop()) {
3073 __ decode_heap_oop(dest->as_register());
3074 }
3075
3076 if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
3077 __ isync();
3078 } else {
3079 __ sync();
3080 }
3081 }
3082
3083
3084 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
3085 Register obj = op->obj()->as_register();
3086 Register tmp = op->tmp()->as_pointer_register();
3087 LIR_Address* mdo_addr = op->mdp()->as_address_ptr();
3088 ciKlass* exact_klass = op->exact_klass();
3089 intptr_t current_klass = op->current_klass();
3090 bool not_null = op->not_null();
3091 bool no_conflict = op->no_conflict();
3092
3093 Label Lupdate, Ldo_update, Ldone;
3094
3095 bool do_null = !not_null;
3096 bool exact_klass_set = exact_klass != nullptr && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
3097 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
3098
3099 assert(do_null || do_update, "why are we here?");
3100 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
3101
3102 __ verify_oop(obj, FILE_AND_LINE);
3103
3104 if (do_null) {
3105 if (!TypeEntries::was_null_seen(current_klass)) {
3106 __ cmpdi(CCR0, obj, 0);
3107 __ bne(CCR0, Lupdate);
3108 __ ld(R0, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3109 __ ori(R0, R0, TypeEntries::null_seen);
3110 if (do_update) {
3111 __ b(Ldo_update);
3112 } else {
3113 __ std(R0, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3114 }
3115 } else {
3116 if (do_update) {
3117 __ cmpdi(CCR0, obj, 0);
3118 __ beq(CCR0, Ldone);
3119 }
3120 }
3121 #ifdef ASSERT
3122 } else {
3123 __ cmpdi(CCR0, obj, 0);
3124 __ bne(CCR0, Lupdate);
3125 __ stop("unexpected null obj");
3126 #endif
3127 }
3128
3129 __ bind(Lupdate);
3130 if (do_update) {
3131 Label Lnext;
3132 const Register klass = R29_TOC; // kill and reload
3133 bool klass_reg_used = false;
3134 #ifdef ASSERT
3135 if (exact_klass != nullptr) {
3136 Label ok;
3137 klass_reg_used = true;
3138 __ load_klass(klass, obj);
3139 metadata2reg(exact_klass->constant_encoding(), R0);
3140 __ cmpd(CCR0, klass, R0);
3141 __ beq(CCR0, ok);
3142 __ stop("exact klass and actual klass differ");
3143 __ bind(ok);
3144 }
3145 #endif
3146
3147 if (!no_conflict) {
3148 if (exact_klass == nullptr || TypeEntries::is_type_none(current_klass)) {
3149 klass_reg_used = true;
3150 if (exact_klass != nullptr) {
3151 __ ld(tmp, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3152 metadata2reg(exact_klass->constant_encoding(), klass);
3153 } else {
3154 __ load_klass(klass, obj);
3155 __ ld(tmp, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register()); // may kill obj
3156 }
3157
3158 // Like InterpreterMacroAssembler::profile_obj_type
3159 __ clrrdi(R0, tmp, exact_log2(-TypeEntries::type_klass_mask));
3160 // Basically same as andi(R0, tmp, TypeEntries::type_klass_mask);
3161 __ cmpd(CCR1, R0, klass);
3162 // Klass seen before, nothing to do (regardless of unknown bit).
3163 //beq(CCR1, do_nothing);
3164
3165 __ andi_(R0, tmp, TypeEntries::type_unknown);
3166 // Already unknown. Nothing to do anymore.
3167 //bne(CCR0, do_nothing);
3168 __ crorc(CCR0, Assembler::equal, CCR1, Assembler::equal); // cr0 eq = cr1 eq or cr0 ne
3169 __ beq(CCR0, Lnext);
3170
3171 if (TypeEntries::is_type_none(current_klass)) {
3172 __ clrrdi_(R0, tmp, exact_log2(-TypeEntries::type_mask));
3173 __ orr(R0, klass, tmp); // Combine klass and null_seen bit (only used if (tmp & type_mask)==0).
3174 __ beq(CCR0, Ldo_update); // First time here. Set profile type.
3175 }
3176
3177 } else {
3178 assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
3179 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
3180
3181 __ ld(tmp, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3182 __ andi_(R0, tmp, TypeEntries::type_unknown);
3183 // Already unknown. Nothing to do anymore.
3184 __ bne(CCR0, Lnext);
3185 }
3186
3187 // Different than before. Cannot keep accurate profile.
3188 __ ori(R0, tmp, TypeEntries::type_unknown);
3189 } else {
3190 // There's a single possible klass at this profile point
3191 assert(exact_klass != nullptr, "should be");
3192 __ ld(tmp, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3193
3194 if (TypeEntries::is_type_none(current_klass)) {
3195 klass_reg_used = true;
3196 metadata2reg(exact_klass->constant_encoding(), klass);
3197
3198 __ clrrdi(R0, tmp, exact_log2(-TypeEntries::type_klass_mask));
3199 // Basically same as andi(R0, tmp, TypeEntries::type_klass_mask);
3200 __ cmpd(CCR1, R0, klass);
3201 // Klass seen before, nothing to do (regardless of unknown bit).
3202 __ beq(CCR1, Lnext);
3203 #ifdef ASSERT
3204 {
3205 Label ok;
3206 __ clrrdi_(R0, tmp, exact_log2(-TypeEntries::type_mask));
3207 __ beq(CCR0, ok); // First time here.
3208
3209 __ stop("unexpected profiling mismatch");
3210 __ bind(ok);
3211 }
3212 #endif
3213 // First time here. Set profile type.
3214 __ orr(R0, klass, tmp); // Combine klass and null_seen bit (only used if (tmp & type_mask)==0).
3215 } else {
3216 assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
3217 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
3218
3219 // Already unknown. Nothing to do anymore.
3220 __ andi_(R0, tmp, TypeEntries::type_unknown);
3221 __ bne(CCR0, Lnext);
3222
3223 // Different than before. Cannot keep accurate profile.
3224 __ ori(R0, tmp, TypeEntries::type_unknown);
3225 }
3226 }
3227
3228 __ bind(Ldo_update);
3229 __ std(R0, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3230
3231 __ bind(Lnext);
3232 if (klass_reg_used) { __ load_const_optimized(R29_TOC, MacroAssembler::global_toc(), R0); } // reinit
3233 }
3234 __ bind(Ldone);
3235 }
3236
3237
3238 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
3239 assert(op->crc()->is_single_cpu(), "crc must be register");
3240 assert(op->val()->is_single_cpu(), "byte value must be register");
3241 assert(op->result_opr()->is_single_cpu(), "result must be register");
3242 Register crc = op->crc()->as_register();
3243 Register val = op->val()->as_register();
3244 Register res = op->result_opr()->as_register();
3245
3246 assert_different_registers(val, crc, res);
3247
3248 __ load_const_optimized(res, StubRoutines::crc_table_addr(), R0);
3249 __ kernel_crc32_singleByteReg(crc, val, res, true);
3250 __ mr(res, crc);
3251 }
3252
3253 #undef __