134 product(bool, UseExtendedLoadAndReserveInstructionsPPC64, false, DIAGNOSTIC,\
135 "Use extended versions of load-and-reserve instructions.") \
136 \
137 product(bool, UseRotateAndMaskInstructionsPPC64, true, DIAGNOSTIC, \
138 "Use rotate and mask instructions.") \
139 \
140 /* Trap based checks. */ \
141 /* Trap based checks use the ppc trap instructions to check certain */ \
142 /* conditions. This instruction raises a SIGTRAP caught by the */ \
143 /* exception handler of the VM. */ \
144 product(bool, UseSIGTRAP, true, \
145 "Allow trap instructions that make use of SIGTRAP. Use this to " \
146 "switch off all optimizations requiring SIGTRAP.") \
147 product(bool, TrapBasedICMissChecks, true, DIAGNOSTIC, \
148 "Raise and handle SIGTRAP if inline cache miss detected.") \
149 \
150 product(bool, TraceTraps, false, DIAGNOSTIC, \
151 "Trace all traps the signal handler handles.") \
152 \
153 develop(bool, ZapMemory, false, \
154 "Write 0x0101... to empty memory. Use this to ease debugging.") \
155 \
156 /* Use Restricted Transactional Memory for lock elision */ \
157 product(bool, UseRTMLocking, false, \
158 "Enable RTM lock eliding for inflated locks in compiled code") \
159 \
160 product(bool, UseRTMForStackLocks, false, EXPERIMENTAL, \
161 "Enable RTM lock eliding for stack locks in compiled code") \
162 \
163 product(bool, UseRTMDeopt, false, \
164 "Perform deopt and recompilation based on RTM abort ratio") \
165 \
166 product(int, RTMRetryCount, 5, \
167 "Number of RTM retries on lock abort or busy") \
168 range(0, max_jint) \
169 \
170 product(int, RTMSpinLoopCount, 100, EXPERIMENTAL, \
171 "Spin count for lock to become free before RTM retry") \
172 range(0, 32767) /* immediate operand limit on ppc */ \
173 \
174 product(int, RTMAbortThreshold, 1000, EXPERIMENTAL, \
175 "Calculate abort ratio after this number of aborts") \
176 range(0, max_jint) \
177 \
178 product(int, RTMLockingThreshold, 10000, EXPERIMENTAL, \
179 "Lock count at which to do RTM lock eliding without " \
180 "abort ratio calculation") \
181 range(0, max_jint) \
182 \
183 product(int, RTMAbortRatio, 50, EXPERIMENTAL, \
184 "Lock abort ratio at which to stop use RTM lock eliding") \
185 range(0, 100) /* natural range */ \
186 \
187 product(int, RTMTotalCountIncrRate, 64, EXPERIMENTAL, \
188 "Increment total RTM attempted lock count once every n times") \
189 range(1, 32767) /* immediate operand limit on ppc */ \
190 constraint(RTMTotalCountIncrRateConstraintFunc,AfterErgo) \
191 \
192 product(intx, RTMLockingCalculationDelay, 0, EXPERIMENTAL, \
193 "Number of milliseconds to wait before start calculating aborts " \
194 "for RTM locking") \
195 \
196 product(bool, UseRTMXendForLockBusy, true, EXPERIMENTAL, \
197 "Use RTM Xend instead of Xabort when lock busy")
198
199 // end of ARCH_FLAGS
200
201 #endif // CPU_PPC_GLOBALS_PPC_HPP
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134 product(bool, UseExtendedLoadAndReserveInstructionsPPC64, false, DIAGNOSTIC,\
135 "Use extended versions of load-and-reserve instructions.") \
136 \
137 product(bool, UseRotateAndMaskInstructionsPPC64, true, DIAGNOSTIC, \
138 "Use rotate and mask instructions.") \
139 \
140 /* Trap based checks. */ \
141 /* Trap based checks use the ppc trap instructions to check certain */ \
142 /* conditions. This instruction raises a SIGTRAP caught by the */ \
143 /* exception handler of the VM. */ \
144 product(bool, UseSIGTRAP, true, \
145 "Allow trap instructions that make use of SIGTRAP. Use this to " \
146 "switch off all optimizations requiring SIGTRAP.") \
147 product(bool, TrapBasedICMissChecks, true, DIAGNOSTIC, \
148 "Raise and handle SIGTRAP if inline cache miss detected.") \
149 \
150 product(bool, TraceTraps, false, DIAGNOSTIC, \
151 "Trace all traps the signal handler handles.") \
152 \
153 develop(bool, ZapMemory, false, \
154 "Write 0x0101... to empty memory. Use this to ease debugging.")
155
156 // end of ARCH_FLAGS
157
158 #endif // CPU_PPC_GLOBALS_PPC_HPP
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