1 /*
2 * Copyright (c) 1997, 2023, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2012, 2023 SAP SE. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "precompiled.hpp"
27 #include "asm/assembler.inline.hpp"
28 #include "asm/macroAssembler.inline.hpp"
29 #include "compiler/disassembler.hpp"
30 #include "jvm.h"
31 #include "memory/resourceArea.hpp"
32 #include "runtime/globals_extension.hpp"
33 #include "runtime/java.hpp"
34 #include "runtime/os.hpp"
35 #include "runtime/stubCodeGenerator.hpp"
36 #include "runtime/vm_version.hpp"
37 #include "utilities/align.hpp"
38 #include "utilities/defaultStream.hpp"
39 #include "utilities/globalDefinitions.hpp"
40 #include "utilities/powerOfTwo.hpp"
41
42 #include <sys/sysinfo.h>
43 #if defined(_AIX)
44 #include "os_aix.hpp"
45 #include <libperfstat.h>
46 #endif
47
48 #if defined(LINUX) && defined(VM_LITTLE_ENDIAN)
49 #include <sys/auxv.h>
50
51 #ifndef PPC_FEATURE2_HTM_NOSC
52 #define PPC_FEATURE2_HTM_NOSC (1 << 24)
53 #endif
54 #endif
55
56 bool VM_Version::_is_determine_features_test_running = false;
57 uint64_t VM_Version::_dscr_val = 0;
58
59 #define MSG(flag) \
60 if (flag && !FLAG_IS_DEFAULT(flag)) \
61 jio_fprintf(defaultStream::error_stream(), \
62 "warning: -XX:+" #flag " requires -XX:+UseSIGTRAP\n" \
63 " -XX:+" #flag " will be disabled!\n");
64
65 void VM_Version::initialize() {
66
67 // Test which instructions are supported and measure cache line size.
68 determine_features();
69
70 // If PowerArchitecturePPC64 hasn't been specified explicitly determine from features.
71 if (FLAG_IS_DEFAULT(PowerArchitecturePPC64)) {
72 if (VM_Version::has_brw()) {
73 FLAG_SET_ERGO(PowerArchitecturePPC64, 10);
74 } else if (VM_Version::has_darn()) {
75 FLAG_SET_ERGO(PowerArchitecturePPC64, 9);
76 } else if (VM_Version::has_lqarx()) {
77 FLAG_SET_ERGO(PowerArchitecturePPC64, 8);
78 } else if (VM_Version::has_popcntw()) {
79 FLAG_SET_ERGO(PowerArchitecturePPC64, 7);
80 } else if (VM_Version::has_cmpb()) {
81 FLAG_SET_ERGO(PowerArchitecturePPC64, 6);
82 } else if (VM_Version::has_popcntb()) {
83 FLAG_SET_ERGO(PowerArchitecturePPC64, 5);
84 } else {
85 FLAG_SET_ERGO(PowerArchitecturePPC64, 0);
86 }
87 }
88
89 bool PowerArchitecturePPC64_ok = false;
90 switch (PowerArchitecturePPC64) {
91 case 10: if (!VM_Version::has_brw() ) break;
92 case 9: if (!VM_Version::has_darn() ) break;
93 case 8: if (!VM_Version::has_lqarx() ) break;
94 case 7: if (!VM_Version::has_popcntw()) break;
95 case 6: if (!VM_Version::has_cmpb() ) break;
96 case 5: if (!VM_Version::has_popcntb()) break;
97 case 0: PowerArchitecturePPC64_ok = true; break;
98 default: break;
99 }
100 guarantee(PowerArchitecturePPC64_ok, "PowerArchitecturePPC64 cannot be set to "
101 UINTX_FORMAT " on this machine", PowerArchitecturePPC64);
102
103 // Power 8: Configure Data Stream Control Register.
104 if (PowerArchitecturePPC64 >= 8 && has_mfdscr()) {
105 config_dscr();
106 }
107
108 if (!UseSIGTRAP) {
109 MSG(TrapBasedICMissChecks);
110 MSG(TrapBasedNullChecks);
111 FLAG_SET_ERGO(TrapBasedNullChecks, false);
112 FLAG_SET_ERGO(TrapBasedICMissChecks, false);
113 }
114
115 #ifdef COMPILER2
116 if (!UseSIGTRAP) {
117 MSG(TrapBasedRangeChecks);
118 FLAG_SET_ERGO(TrapBasedRangeChecks, false);
119 }
120
121 if (PowerArchitecturePPC64 >= 8) {
122 if (FLAG_IS_DEFAULT(SuperwordUseVSX)) {
123 FLAG_SET_ERGO(SuperwordUseVSX, true);
124 }
125 } else {
126 if (SuperwordUseVSX) {
127 warning("SuperwordUseVSX specified, but needs at least Power8.");
128 FLAG_SET_DEFAULT(SuperwordUseVSX, false);
129 }
130 }
131 MaxVectorSize = SuperwordUseVSX ? 16 : 8;
132
133 if (PowerArchitecturePPC64 >= 9) {
134 if (FLAG_IS_DEFAULT(UseCountTrailingZerosInstructionsPPC64)) {
135 FLAG_SET_ERGO(UseCountTrailingZerosInstructionsPPC64, true);
136 }
137 if (FLAG_IS_DEFAULT(UseCharacterCompareIntrinsics)) {
138 FLAG_SET_ERGO(UseCharacterCompareIntrinsics, true);
139 }
140 if (SuperwordUseVSX) {
141 if (FLAG_IS_DEFAULT(UseVectorByteReverseInstructionsPPC64)) {
142 FLAG_SET_ERGO(UseVectorByteReverseInstructionsPPC64, true);
143 }
144 } else if (UseVectorByteReverseInstructionsPPC64) {
145 warning("UseVectorByteReverseInstructionsPPC64 specified, but needs SuperwordUseVSX.");
146 FLAG_SET_DEFAULT(UseVectorByteReverseInstructionsPPC64, false);
147 }
148 if (FLAG_IS_DEFAULT(UseBASE64Intrinsics)) {
149 FLAG_SET_ERGO(UseBASE64Intrinsics, true);
150 }
151 } else {
152 if (UseCountTrailingZerosInstructionsPPC64) {
153 warning("UseCountTrailingZerosInstructionsPPC64 specified, but needs at least Power9.");
154 FLAG_SET_DEFAULT(UseCountTrailingZerosInstructionsPPC64, false);
155 }
156 if (UseCharacterCompareIntrinsics) {
157 warning("UseCharacterCompareIntrinsics specified, but needs at least Power9.");
158 FLAG_SET_DEFAULT(UseCharacterCompareIntrinsics, false);
159 }
160 if (UseVectorByteReverseInstructionsPPC64) {
161 warning("UseVectorByteReverseInstructionsPPC64 specified, but needs at least Power9.");
162 FLAG_SET_DEFAULT(UseVectorByteReverseInstructionsPPC64, false);
163 }
164 if (UseBASE64Intrinsics) {
165 warning("UseBASE64Intrinsics specified, but needs at least Power9.");
166 FLAG_SET_DEFAULT(UseBASE64Intrinsics, false);
167 }
168 }
169
170 if (PowerArchitecturePPC64 >= 10) {
171 if (FLAG_IS_DEFAULT(UseByteReverseInstructions)) {
172 FLAG_SET_ERGO(UseByteReverseInstructions, true);
173 }
174 } else {
175 if (UseByteReverseInstructions) {
176 warning("UseByteReverseInstructions specified, but needs at least Power10.");
177 FLAG_SET_DEFAULT(UseByteReverseInstructions, false);
178 }
179 }
180 #endif
181
182 // Create and print feature-string.
183 char buf[(num_features+1) * 16]; // Max 16 chars per feature.
184 jio_snprintf(buf, sizeof(buf),
185 "ppc64%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
186 (has_fsqrt() ? " fsqrt" : ""),
187 (has_isel() ? " isel" : ""),
188 (has_lxarxeh() ? " lxarxeh" : ""),
189 (has_cmpb() ? " cmpb" : ""),
190 (has_popcntb() ? " popcntb" : ""),
191 (has_popcntw() ? " popcntw" : ""),
192 (has_fcfids() ? " fcfids" : ""),
193 (has_vand() ? " vand" : ""),
194 (has_lqarx() ? " lqarx" : ""),
195 (has_vcipher() ? " aes" : ""),
196 (has_vpmsumb() ? " vpmsumb" : ""),
197 (has_mfdscr() ? " mfdscr" : ""),
198 (has_vsx() ? " vsx" : ""),
199 (has_ldbrx() ? " ldbrx" : ""),
200 (has_stdbrx() ? " stdbrx" : ""),
201 (has_vshasig() ? " sha" : ""),
202 (has_tm() ? " rtm" : ""),
203 (has_darn() ? " darn" : ""),
204 (has_brw() ? " brw" : "")
205 // Make sure number of %s matches num_features!
206 );
207 _features_string = os::strdup(buf);
208 if (Verbose) {
209 print_features();
210 }
211
212 // PPC64 supports 8-byte compare-exchange operations (see Atomic::cmpxchg)
213 // and 'atomic long memory ops' (see Unsafe_GetLongVolatile).
214 _supports_cx8 = true;
215
216 // Used by C1.
217 _supports_atomic_getset4 = true;
218 _supports_atomic_getadd4 = true;
219 _supports_atomic_getset8 = true;
220 _supports_atomic_getadd8 = true;
221
222 intx cache_line_size = L1_data_cache_line_size();
223
224 if (PowerArchitecturePPC64 >= 9) {
225 if (os::supports_map_sync() == true) {
226 _data_cache_line_flush_size = cache_line_size;
227 }
228 }
229
230 if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) AllocatePrefetchStyle = 1;
231
232 if (cache_line_size > AllocatePrefetchStepSize) AllocatePrefetchStepSize = cache_line_size;
233 // PPC processors have an automatic prefetch engine.
234 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) AllocatePrefetchLines = 1;
235 if (AllocatePrefetchDistance < 0) AllocatePrefetchDistance = 3 * cache_line_size;
236
237 assert(AllocatePrefetchLines > 0, "invalid value");
238 if (AllocatePrefetchLines < 1) { // Set valid value in product VM.
239 AllocatePrefetchLines = 1; // Conservative value.
240 }
241
242 if (AllocatePrefetchStyle == 3 && AllocatePrefetchDistance < cache_line_size) {
243 AllocatePrefetchStyle = 1; // Fall back if inappropriate.
244 }
245
246 assert(AllocatePrefetchStyle >= 0, "AllocatePrefetchStyle should be positive");
247
248 if (FLAG_IS_DEFAULT(ContendedPaddingWidth) && (cache_line_size > ContendedPaddingWidth)) {
249 ContendedPaddingWidth = cache_line_size;
250 }
251
252 // If running on Power8 or newer hardware, the implementation uses the available vector instructions.
253 // In all other cases, the implementation uses only generally available instructions.
254 if (!UseCRC32Intrinsics) {
255 if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
256 FLAG_SET_DEFAULT(UseCRC32Intrinsics, true);
257 }
258 }
259
260 // Implementation does not use any of the vector instructions available with Power8.
261 // Their exploitation is still pending (aka "work in progress").
262 if (!UseCRC32CIntrinsics) {
263 if (FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) {
264 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, true);
265 }
266 }
267
268 // TODO: Provide implementation.
269 if (UseAdler32Intrinsics) {
270 warning("Adler32Intrinsics not available on this CPU.");
271 FLAG_SET_DEFAULT(UseAdler32Intrinsics, false);
272 }
273
274 // The AES intrinsic stubs require AES instruction support.
275 if (has_vcipher()) {
276 if (FLAG_IS_DEFAULT(UseAES)) {
277 UseAES = true;
278 }
279 } else if (UseAES) {
280 if (!FLAG_IS_DEFAULT(UseAES))
281 warning("AES instructions are not available on this CPU");
282 FLAG_SET_DEFAULT(UseAES, false);
283 }
284
285 if (UseAES && has_vcipher()) {
286 if (FLAG_IS_DEFAULT(UseAESIntrinsics)) {
287 UseAESIntrinsics = true;
288 }
289 } else if (UseAESIntrinsics) {
290 if (!FLAG_IS_DEFAULT(UseAESIntrinsics))
291 warning("AES intrinsics are not available on this CPU");
292 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
293 }
294
295 if (UseAESCTRIntrinsics) {
296 warning("AES/CTR intrinsics are not available on this CPU");
297 FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
298 }
299
300 if (UseGHASHIntrinsics) {
301 warning("GHASH intrinsics are not available on this CPU");
302 FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
303 }
304
305 if (FLAG_IS_DEFAULT(UseFMA)) {
306 FLAG_SET_DEFAULT(UseFMA, true);
307 }
308
309 if (UseMD5Intrinsics) {
310 warning("MD5 intrinsics are not available on this CPU");
311 FLAG_SET_DEFAULT(UseMD5Intrinsics, false);
312 }
313
314 if (has_vshasig()) {
315 if (FLAG_IS_DEFAULT(UseSHA)) {
316 UseSHA = true;
317 }
318 } else if (UseSHA) {
319 if (!FLAG_IS_DEFAULT(UseSHA))
320 warning("SHA instructions are not available on this CPU");
321 FLAG_SET_DEFAULT(UseSHA, false);
322 }
323
324 if (UseSHA1Intrinsics) {
325 warning("Intrinsics for SHA-1 crypto hash functions not available on this CPU.");
326 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
327 }
328
329 if (UseSHA && has_vshasig()) {
330 if (FLAG_IS_DEFAULT(UseSHA256Intrinsics)) {
331 FLAG_SET_DEFAULT(UseSHA256Intrinsics, true);
332 }
333 } else if (UseSHA256Intrinsics) {
334 warning("Intrinsics for SHA-224 and SHA-256 crypto hash functions not available on this CPU.");
335 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
336 }
337
338 if (UseSHA && has_vshasig()) {
339 if (FLAG_IS_DEFAULT(UseSHA512Intrinsics)) {
340 FLAG_SET_DEFAULT(UseSHA512Intrinsics, true);
341 }
342 } else if (UseSHA512Intrinsics) {
343 warning("Intrinsics for SHA-384 and SHA-512 crypto hash functions not available on this CPU.");
344 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
345 }
346
347 if (UseSHA3Intrinsics) {
348 warning("Intrinsics for SHA3-224, SHA3-256, SHA3-384 and SHA3-512 crypto hash functions not available on this CPU.");
349 FLAG_SET_DEFAULT(UseSHA3Intrinsics, false);
350 }
351
352 if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics)) {
353 FLAG_SET_DEFAULT(UseSHA, false);
354 }
355
356 #ifdef COMPILER2
357 if (FLAG_IS_DEFAULT(UseSquareToLenIntrinsic)) {
358 UseSquareToLenIntrinsic = true;
359 }
360 if (FLAG_IS_DEFAULT(UseMulAddIntrinsic)) {
361 UseMulAddIntrinsic = true;
362 }
363 if (FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) {
364 UseMultiplyToLenIntrinsic = true;
365 }
366 if (FLAG_IS_DEFAULT(UseMontgomeryMultiplyIntrinsic)) {
367 UseMontgomeryMultiplyIntrinsic = true;
368 }
369 if (FLAG_IS_DEFAULT(UseMontgomerySquareIntrinsic)) {
370 UseMontgomerySquareIntrinsic = true;
371 }
372 #endif
373
374 if (UseVectorizedMismatchIntrinsic) {
375 warning("UseVectorizedMismatchIntrinsic specified, but not available on this CPU.");
376 FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false);
377 }
378
379
380 // Adjust RTM (Restricted Transactional Memory) flags.
381 if (UseRTMLocking) {
382 // If CPU or OS do not support RTM:
383 if (PowerArchitecturePPC64 < 8 || PowerArchitecturePPC64 > 9) {
384 vm_exit_during_initialization("RTM instructions are not available on this CPU.");
385 }
386
387 if (!has_tm()) {
388 vm_exit_during_initialization("RTM is not supported on this OS version.");
389 }
390
391 #if INCLUDE_RTM_OPT
392 if (!FLAG_IS_CMDLINE(UseRTMLocking)) {
393 // RTM locking should be used only for applications with
394 // high lock contention. For now we do not use it by default.
395 vm_exit_during_initialization("UseRTMLocking flag should be only set on command line");
396 }
397 if (LockingMode != LM_LEGACY) {
398 warning("UseRTMLocking requires LockingMode = 1");
399 FLAG_SET_DEFAULT(UseRTMLocking, false);
400 }
401 #else
402 // Only C2 does RTM locking optimization.
403 vm_exit_during_initialization("RTM locking optimization is not supported in this VM");
404 #endif
405 } else { // !UseRTMLocking
406 if (UseRTMForStackLocks) {
407 if (!FLAG_IS_DEFAULT(UseRTMForStackLocks)) {
408 warning("UseRTMForStackLocks flag should be off when UseRTMLocking flag is off");
409 }
410 FLAG_SET_DEFAULT(UseRTMForStackLocks, false);
411 }
412 if (UseRTMDeopt) {
413 FLAG_SET_DEFAULT(UseRTMDeopt, false);
414 }
415 #ifdef COMPILER2
416 if (PrintPreciseRTMLockingStatistics) {
417 FLAG_SET_DEFAULT(PrintPreciseRTMLockingStatistics, false);
418 }
419 #endif
420 }
421
422 // This machine allows unaligned memory accesses
423 if (FLAG_IS_DEFAULT(UseUnalignedAccesses)) {
424 FLAG_SET_DEFAULT(UseUnalignedAccesses, true);
425 }
426
427 check_virtualizations();
428 }
429
430 void VM_Version::check_virtualizations() {
431 #if defined(_AIX)
432 int rc = 0;
433 perfstat_partition_total_t pinfo;
434 rc = perfstat_partition_total(nullptr, &pinfo, sizeof(perfstat_partition_total_t), 1);
435 if (rc == 1) {
436 Abstract_VM_Version::_detected_virtualization = PowerVM;
437 }
438 #else
439 const char* info_file = "/proc/ppc64/lparcfg";
440 // system_type=...qemu indicates PowerKVM
441 // e.g. system_type=IBM pSeries (emulated by qemu)
442 char line[500];
443 FILE* fp = os::fopen(info_file, "r");
444 if (fp == nullptr) {
445 return;
446 }
447 const char* system_type="system_type="; // in case this line contains qemu, it is KVM
448 const char* num_lpars="NumLpars="; // in case of non-KVM : if this line is found it is PowerVM
449 bool num_lpars_found = false;
450
451 while (fgets(line, sizeof(line), fp) != nullptr) {
452 if (strncmp(line, system_type, strlen(system_type)) == 0) {
453 if (strstr(line, "qemu") != 0) {
454 Abstract_VM_Version::_detected_virtualization = PowerKVM;
455 fclose(fp);
456 return;
457 }
458 }
459 if (strncmp(line, num_lpars, strlen(num_lpars)) == 0) {
460 num_lpars_found = true;
461 }
462 }
463 if (num_lpars_found) {
464 Abstract_VM_Version::_detected_virtualization = PowerVM;
465 } else {
466 Abstract_VM_Version::_detected_virtualization = PowerFullPartitionMode;
467 }
468 fclose(fp);
469 #endif
470 }
471
472 void VM_Version::print_platform_virtualization_info(outputStream* st) {
473 #if defined(_AIX)
474 // more info about perfstat API see
475 // https://www.ibm.com/support/knowledgecenter/en/ssw_aix_72/com.ibm.aix.prftools/idprftools_perfstat_glob_partition.htm
476 int rc = 0;
477 perfstat_partition_total_t pinfo;
478 memset(&pinfo, 0, sizeof(perfstat_partition_total_t));
479 rc = perfstat_partition_total(nullptr, &pinfo, sizeof(perfstat_partition_total_t), 1);
480 if (rc != 1) {
481 return;
482 } else {
483 st->print_cr("Virtualization type : PowerVM");
484 }
485 // CPU information
486 perfstat_cpu_total_t cpuinfo;
487 memset(&cpuinfo, 0, sizeof(perfstat_cpu_total_t));
488 rc = perfstat_cpu_total(nullptr, &cpuinfo, sizeof(perfstat_cpu_total_t), 1);
489 if (rc != 1) {
490 return;
491 }
492
493 st->print_cr("Processor description : %s", cpuinfo.description);
494 st->print_cr("Processor speed : %llu Hz", cpuinfo.processorHZ);
495
496 st->print_cr("LPAR partition name : %s", pinfo.name);
497 st->print_cr("LPAR partition number : %u", pinfo.lpar_id);
498 st->print_cr("LPAR partition type : %s", pinfo.type.b.shared_enabled ? "shared" : "dedicated");
499 st->print_cr("LPAR mode : %s", pinfo.type.b.donate_enabled ? "donating" : pinfo.type.b.capped ? "capped" : "uncapped");
500 st->print_cr("LPAR partition group ID : %u", pinfo.group_id);
501 st->print_cr("LPAR shared pool ID : %u", pinfo.pool_id);
502
503 st->print_cr("AMS (active memory sharing) : %s", pinfo.type.b.ams_capable ? "capable" : "not capable");
504 st->print_cr("AMS (active memory sharing) : %s", pinfo.type.b.ams_enabled ? "on" : "off");
505 st->print_cr("AME (active memory expansion) : %s", pinfo.type.b.ame_enabled ? "on" : "off");
506
507 if (pinfo.type.b.ame_enabled) {
508 st->print_cr("AME true memory in bytes : %llu", pinfo.true_memory);
509 st->print_cr("AME expanded memory in bytes : %llu", pinfo.expanded_memory);
510 }
511
512 st->print_cr("SMT : %s", pinfo.type.b.smt_capable ? "capable" : "not capable");
513 st->print_cr("SMT : %s", pinfo.type.b.smt_enabled ? "on" : "off");
514 int ocpus = pinfo.online_cpus > 0 ? pinfo.online_cpus : 1;
515 st->print_cr("LPAR threads : %d", cpuinfo.ncpus/ocpus);
516 st->print_cr("LPAR online virtual cpus : %d", pinfo.online_cpus);
517 st->print_cr("LPAR logical cpus : %d", cpuinfo.ncpus);
518 st->print_cr("LPAR maximum virtual cpus : %u", pinfo.max_cpus);
519 st->print_cr("LPAR minimum virtual cpus : %u", pinfo.min_cpus);
520 st->print_cr("LPAR entitled capacity : %4.2f", (double) (pinfo.entitled_proc_capacity/100.0));
521 st->print_cr("LPAR online memory : %llu MB", pinfo.online_memory);
522 st->print_cr("LPAR maximum memory : %llu MB", pinfo.max_memory);
523 st->print_cr("LPAR minimum memory : %llu MB", pinfo.min_memory);
524 #else
525 const char* info_file = "/proc/ppc64/lparcfg";
526 const char* kw[] = { "system_type=", // qemu indicates PowerKVM
527 "partition_entitled_capacity=", // entitled processor capacity percentage
528 "partition_max_entitled_capacity=",
529 "capacity_weight=", // partition CPU weight
530 "partition_active_processors=",
531 "partition_potential_processors=",
532 "entitled_proc_capacity_available=",
533 "capped=", // 0 - uncapped, 1 - vcpus capped at entitled processor capacity percentage
534 "shared_processor_mode=", // (non)dedicated partition
535 "system_potential_processors=",
536 "pool=", // CPU-pool number
537 "pool_capacity=",
538 "NumLpars=", // on non-KVM machines, NumLpars is not found for full partition mode machines
539 nullptr };
540 if (!print_matching_lines_from_file(info_file, st, kw)) {
541 st->print_cr(" <%s Not Available>", info_file);
542 }
543 #endif
544 }
545
546 void VM_Version::print_features() {
547 tty->print_cr("Version: %s L1_data_cache_line_size=%d", features_string(), L1_data_cache_line_size());
548
549 if (Verbose) {
550 if (ContendedPaddingWidth > 0) {
551 tty->cr();
552 tty->print_cr("ContendedPaddingWidth " INTX_FORMAT, ContendedPaddingWidth);
553 }
554 }
555 }
556
557 void VM_Version::determine_features() {
558 #if defined(ABI_ELFv2)
559 // 1 InstWord per call for the blr instruction.
560 const int code_size = (num_features+1+2*1)*BytesPerInstWord;
561 #else
562 // 7 InstWords for each call (function descriptor + blr instruction).
563 const int code_size = (num_features+1+2*7)*BytesPerInstWord;
564 #endif
565 int features = 0;
566
567 // create test area
568 enum { BUFFER_SIZE = 2*4*K }; // Needs to be >=2* max cache line size (cache line size can't exceed min page size).
569 char test_area[BUFFER_SIZE];
570 char *mid_of_test_area = &test_area[BUFFER_SIZE>>1];
571
572 // Allocate space for the code.
573 ResourceMark rm;
574 CodeBuffer cb("detect_cpu_features", code_size, 0);
575 MacroAssembler* a = new MacroAssembler(&cb);
576
577 // Must be set to true so we can generate the test code.
578 _features = VM_Version::all_features_m;
579
580 // Emit code.
581 void (*test)(address addr, uint64_t offset)=(void(*)(address addr, uint64_t offset))(void *)a->function_entry();
582 uint32_t *code = (uint32_t *)a->pc();
583 // Don't use R0 in ldarx.
584 // Keep R3_ARG1 unmodified, it contains &field (see below).
585 // Keep R4_ARG2 unmodified, it contains offset = 0 (see below).
586 a->fsqrt(F3, F4); // code[0] -> fsqrt_m
587 a->fsqrts(F3, F4); // code[1] -> fsqrts_m
588 a->isel(R7, R5, R6, 0); // code[2] -> isel_m
589 a->ldarx_unchecked(R7, R3_ARG1, R4_ARG2, 1); // code[3] -> lxarx_m
590 a->cmpb(R7, R5, R6); // code[4] -> cmpb
591 a->popcntb(R7, R5); // code[5] -> popcntb
592 a->popcntw(R7, R5); // code[6] -> popcntw
593 a->fcfids(F3, F4); // code[7] -> fcfids
594 a->vand(VR0, VR0, VR0); // code[8] -> vand
595 // arg0 of lqarx must be an even register, (arg1 + arg2) must be a multiple of 16
596 a->lqarx_unchecked(R6, R3_ARG1, R4_ARG2, 1); // code[9] -> lqarx_m
597 a->vcipher(VR0, VR1, VR2); // code[10] -> vcipher
598 a->vpmsumb(VR0, VR1, VR2); // code[11] -> vpmsumb
599 a->mfdscr(R0); // code[12] -> mfdscr
600 a->lxvd2x(VSR0, R3_ARG1); // code[13] -> vsx
601 a->ldbrx(R7, R3_ARG1, R4_ARG2); // code[14] -> ldbrx
602 a->stdbrx(R7, R3_ARG1, R4_ARG2); // code[15] -> stdbrx
603 a->vshasigmaw(VR0, VR1, 1, 0xF); // code[16] -> vshasig
604 // rtm is determined by OS
605 a->darn(R7); // code[17] -> darn
606 a->brw(R5, R6); // code[18] -> brw
607 a->blr();
608
609 // Emit function to set one cache line to zero. Emit function descriptor and get pointer to it.
610 void (*zero_cacheline_func_ptr)(char*) = (void(*)(char*))(void *)a->function_entry();
611 a->dcbz(R3_ARG1); // R3_ARG1 = addr
612 a->blr();
613
614 uint32_t *code_end = (uint32_t *)a->pc();
615 a->flush();
616 _features = VM_Version::unknown_m;
617
618 // Print the detection code.
619 if (PrintAssembly) {
620 ttyLocker ttyl;
621 tty->print_cr("Decoding cpu-feature detection stub at " INTPTR_FORMAT " before execution:", p2i(code));
622 Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
623 }
624
625 // Measure cache line size.
626 memset(test_area, 0xFF, BUFFER_SIZE); // Fill test area with 0xFF.
627 (*zero_cacheline_func_ptr)(mid_of_test_area); // Call function which executes dcbz to the middle.
628 int count = 0; // count zeroed bytes
629 for (int i = 0; i < BUFFER_SIZE; i++) if (test_area[i] == 0) count++;
630 guarantee(is_power_of_2(count), "cache line size needs to be a power of 2");
631 _L1_data_cache_line_size = count;
632
633 // Execute code. Illegal instructions will be replaced by 0 in the signal handler.
634 VM_Version::_is_determine_features_test_running = true;
635 // We must align the first argument to 16 bytes because of the lqarx check.
636 (*test)(align_up((address)mid_of_test_area, 16), 0);
637 VM_Version::_is_determine_features_test_running = false;
638
639 // determine which instructions are legal.
640 int feature_cntr = 0;
641 if (code[feature_cntr++]) features |= fsqrt_m;
642 if (code[feature_cntr++]) features |= fsqrts_m;
643 if (code[feature_cntr++]) features |= isel_m;
644 if (code[feature_cntr++]) features |= lxarxeh_m;
645 if (code[feature_cntr++]) features |= cmpb_m;
646 if (code[feature_cntr++]) features |= popcntb_m;
647 if (code[feature_cntr++]) features |= popcntw_m;
648 if (code[feature_cntr++]) features |= fcfids_m;
649 if (code[feature_cntr++]) features |= vand_m;
650 if (code[feature_cntr++]) features |= lqarx_m;
651 if (code[feature_cntr++]) features |= vcipher_m;
652 if (code[feature_cntr++]) features |= vpmsumb_m;
653 if (code[feature_cntr++]) features |= mfdscr_m;
654 if (code[feature_cntr++]) features |= vsx_m;
655 if (code[feature_cntr++]) features |= ldbrx_m;
656 if (code[feature_cntr++]) features |= stdbrx_m;
657 if (code[feature_cntr++]) features |= vshasig_m;
658 // feature rtm_m is determined by OS
659 if (code[feature_cntr++]) features |= darn_m;
660 if (code[feature_cntr++]) features |= brw_m;
661
662 // Print the detection code.
663 if (PrintAssembly) {
664 ttyLocker ttyl;
665 tty->print_cr("Decoding cpu-feature detection stub at " INTPTR_FORMAT " after execution:", p2i(code));
666 Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
667 }
668
669 _features = features;
670
671 #ifdef AIX
672 // To enable it on AIX it's necessary POWER8 or above and at least AIX 7.2.
673 // Actually, this is supported since AIX 7.1.. Unfortunately, this first
674 // contained bugs, so that it can only be enabled after AIX 7.1.3.30.
675 // The Java property os.version, which is used in RTM tests to decide
676 // whether the feature is available, only knows major and minor versions.
677 // We don't want to change this property, as user code might depend on it.
678 // So the tests can not check on subversion 3.30, and we only enable RTM
679 // with AIX 7.2.
680 if (has_lqarx() && !has_brw()) { // POWER8 or POWER9
681 if (os::Aix::os_version() >= 0x07020000) { // At least AIX 7.2.
682 _features |= rtm_m;
683 }
684 }
685 #endif
686 #if defined(LINUX) && defined(VM_LITTLE_ENDIAN)
687 unsigned long auxv = getauxval(AT_HWCAP2);
688
689 if (auxv & PPC_FEATURE2_HTM_NOSC) {
690 if (auxv & PPC_FEATURE2_HAS_HTM) {
691 // TM on POWER8 and POWER9 in compat mode (VM) is supported by the JVM.
692 // TM on POWER9 DD2.1 NV (baremetal) is not supported by the JVM (TM on
693 // POWER9 DD2.1 NV has a few issues that need a couple of firmware
694 // and kernel workarounds, so there is a new mode only supported
695 // on non-virtualized P9 machines called HTM with no Suspend Mode).
696 // TM on POWER9 D2.2+ NV is not supported at all by Linux.
697 _features |= rtm_m;
698 }
699 }
700 #endif
701 }
702
703 // Power 8: Configure Data Stream Control Register.
704 void VM_Version::config_dscr() {
705 // 7 InstWords for each call (function descriptor + blr instruction).
706 const int code_size = (2+2*7)*BytesPerInstWord;
707
708 // Allocate space for the code.
709 ResourceMark rm;
710 CodeBuffer cb("config_dscr", code_size, 0);
711 MacroAssembler* a = new MacroAssembler(&cb);
712
713 // Emit code.
714 uint64_t (*get_dscr)() = (uint64_t(*)())(void *)a->function_entry();
715 uint32_t *code = (uint32_t *)a->pc();
716 a->mfdscr(R3);
717 a->blr();
718
719 void (*set_dscr)(long) = (void(*)(long))(void *)a->function_entry();
720 a->mtdscr(R3);
721 a->blr();
722
723 uint32_t *code_end = (uint32_t *)a->pc();
724 a->flush();
725
726 // Print the detection code.
727 if (PrintAssembly) {
728 ttyLocker ttyl;
729 tty->print_cr("Decoding dscr configuration stub at " INTPTR_FORMAT " before execution:", p2i(code));
730 Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
731 }
732
733 // Apply the configuration if needed.
734 _dscr_val = (*get_dscr)();
735 if (Verbose) {
736 tty->print_cr("dscr value was 0x%lx" , _dscr_val);
737 }
738 bool change_requested = false;
739 if (DSCR_PPC64 != (uintx)-1) {
740 _dscr_val = DSCR_PPC64;
741 change_requested = true;
742 }
743 if (DSCR_DPFD_PPC64 <= 7) {
744 uint64_t mask = 0x7;
745 if ((_dscr_val & mask) != DSCR_DPFD_PPC64) {
746 _dscr_val = (_dscr_val & ~mask) | (DSCR_DPFD_PPC64);
747 change_requested = true;
748 }
749 }
750 if (DSCR_URG_PPC64 <= 7) {
751 uint64_t mask = 0x7 << 6;
752 if ((_dscr_val & mask) != DSCR_DPFD_PPC64 << 6) {
753 _dscr_val = (_dscr_val & ~mask) | (DSCR_URG_PPC64 << 6);
754 change_requested = true;
755 }
756 }
757 if (change_requested) {
758 (*set_dscr)(_dscr_val);
759 if (Verbose) {
760 tty->print_cr("dscr was set to 0x%lx" , (*get_dscr)());
761 }
762 }
763 }
764
765 static uint64_t saved_features = 0;
766
767 void VM_Version::allow_all() {
768 saved_features = _features;
769 _features = all_features_m;
770 }
771
772 void VM_Version::revert() {
773 _features = saved_features;
774 }
775
776 // get cpu information.
777 void VM_Version::initialize_cpu_information(void) {
778 // do nothing if cpu info has been initialized
779 if (_initialized) {
780 return;
781 }
782
783 _no_of_cores = os::processor_count();
784 _no_of_threads = _no_of_cores;
785 _no_of_sockets = _no_of_cores;
786 snprintf(_cpu_name, CPU_TYPE_DESC_BUF_SIZE, "PowerPC POWER%lu", PowerArchitecturePPC64);
787 snprintf(_cpu_desc, CPU_DETAILED_DESC_BUF_SIZE, "PPC %s", features_string());
788 _initialized = true;
789 }