28 #include "asm/macroAssembler.inline.hpp"
29 #include "compiler/disassembler.hpp"
30 #include "jvm.h"
31 #include "memory/resourceArea.hpp"
32 #include "runtime/globals_extension.hpp"
33 #include "runtime/java.hpp"
34 #include "runtime/os.hpp"
35 #include "runtime/stubCodeGenerator.hpp"
36 #include "runtime/vm_version.hpp"
37 #include "utilities/align.hpp"
38 #include "utilities/defaultStream.hpp"
39 #include "utilities/globalDefinitions.hpp"
40 #include "utilities/powerOfTwo.hpp"
41
42 #include <sys/sysinfo.h>
43 #if defined(_AIX)
44 #include "os_aix.hpp"
45 #include <libperfstat.h>
46 #endif
47
48 #if defined(LINUX) && defined(VM_LITTLE_ENDIAN)
49 #include <sys/auxv.h>
50
51 #ifndef PPC_FEATURE2_HTM_NOSC
52 #define PPC_FEATURE2_HTM_NOSC (1 << 24)
53 #endif
54 #endif
55
56 bool VM_Version::_is_determine_features_test_running = false;
57 uint64_t VM_Version::_dscr_val = 0;
58
59 #define MSG(flag) \
60 if (flag && !FLAG_IS_DEFAULT(flag)) \
61 jio_fprintf(defaultStream::error_stream(), \
62 "warning: -XX:+" #flag " requires -XX:+UseSIGTRAP\n" \
63 " -XX:+" #flag " will be disabled!\n");
64
65 void VM_Version::initialize() {
66
67 // Test which instructions are supported and measure cache line size.
68 determine_features();
69
70 // If PowerArchitecturePPC64 hasn't been specified explicitly determine from features.
71 if (FLAG_IS_DEFAULT(PowerArchitecturePPC64)) {
72 if (VM_Version::has_brw()) {
73 FLAG_SET_ERGO(PowerArchitecturePPC64, 10);
74 } else if (VM_Version::has_darn()) {
75 FLAG_SET_ERGO(PowerArchitecturePPC64, 9);
165 warning("UseBASE64Intrinsics specified, but needs at least Power9.");
166 FLAG_SET_DEFAULT(UseBASE64Intrinsics, false);
167 }
168 }
169
170 if (PowerArchitecturePPC64 >= 10) {
171 if (FLAG_IS_DEFAULT(UseByteReverseInstructions)) {
172 FLAG_SET_ERGO(UseByteReverseInstructions, true);
173 }
174 } else {
175 if (UseByteReverseInstructions) {
176 warning("UseByteReverseInstructions specified, but needs at least Power10.");
177 FLAG_SET_DEFAULT(UseByteReverseInstructions, false);
178 }
179 }
180 #endif
181
182 // Create and print feature-string.
183 char buf[(num_features+1) * 16]; // Max 16 chars per feature.
184 jio_snprintf(buf, sizeof(buf),
185 "ppc64%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
186 (has_fsqrt() ? " fsqrt" : ""),
187 (has_isel() ? " isel" : ""),
188 (has_lxarxeh() ? " lxarxeh" : ""),
189 (has_cmpb() ? " cmpb" : ""),
190 (has_popcntb() ? " popcntb" : ""),
191 (has_popcntw() ? " popcntw" : ""),
192 (has_fcfids() ? " fcfids" : ""),
193 (has_vand() ? " vand" : ""),
194 (has_lqarx() ? " lqarx" : ""),
195 (has_vcipher() ? " aes" : ""),
196 (has_vpmsumb() ? " vpmsumb" : ""),
197 (has_mfdscr() ? " mfdscr" : ""),
198 (has_vsx() ? " vsx" : ""),
199 (has_ldbrx() ? " ldbrx" : ""),
200 (has_stdbrx() ? " stdbrx" : ""),
201 (has_vshasig() ? " sha" : ""),
202 (has_tm() ? " rtm" : ""),
203 (has_darn() ? " darn" : ""),
204 (has_brw() ? " brw" : "")
205 // Make sure number of %s matches num_features!
206 );
207 _features_string = os::strdup(buf);
208 if (Verbose) {
209 print_features();
210 }
211
212 // PPC64 supports 8-byte compare-exchange operations (see Atomic::cmpxchg)
213 // and 'atomic long memory ops' (see Unsafe_GetLongVolatile).
214 _supports_cx8 = true;
215
216 // Used by C1.
217 _supports_atomic_getset4 = true;
218 _supports_atomic_getadd4 = true;
219 _supports_atomic_getset8 = true;
220 _supports_atomic_getadd8 = true;
221
222 intx cache_line_size = L1_data_cache_line_size();
359 }
360 if (FLAG_IS_DEFAULT(UseMulAddIntrinsic)) {
361 UseMulAddIntrinsic = true;
362 }
363 if (FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) {
364 UseMultiplyToLenIntrinsic = true;
365 }
366 if (FLAG_IS_DEFAULT(UseMontgomeryMultiplyIntrinsic)) {
367 UseMontgomeryMultiplyIntrinsic = true;
368 }
369 if (FLAG_IS_DEFAULT(UseMontgomerySquareIntrinsic)) {
370 UseMontgomerySquareIntrinsic = true;
371 }
372 #endif
373
374 if (UseVectorizedMismatchIntrinsic) {
375 warning("UseVectorizedMismatchIntrinsic specified, but not available on this CPU.");
376 FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false);
377 }
378
379
380 // Adjust RTM (Restricted Transactional Memory) flags.
381 if (UseRTMLocking) {
382 // If CPU or OS do not support RTM:
383 if (PowerArchitecturePPC64 < 8 || PowerArchitecturePPC64 > 9) {
384 vm_exit_during_initialization("RTM instructions are not available on this CPU.");
385 }
386
387 if (!has_tm()) {
388 vm_exit_during_initialization("RTM is not supported on this OS version.");
389 }
390
391 #if INCLUDE_RTM_OPT
392 if (!FLAG_IS_CMDLINE(UseRTMLocking)) {
393 // RTM locking should be used only for applications with
394 // high lock contention. For now we do not use it by default.
395 vm_exit_during_initialization("UseRTMLocking flag should be only set on command line");
396 }
397 if (LockingMode != LM_LEGACY) {
398 warning("UseRTMLocking requires LockingMode = 1");
399 FLAG_SET_DEFAULT(UseRTMLocking, false);
400 }
401 #else
402 // Only C2 does RTM locking optimization.
403 vm_exit_during_initialization("RTM locking optimization is not supported in this VM");
404 #endif
405 } else { // !UseRTMLocking
406 if (UseRTMForStackLocks) {
407 if (!FLAG_IS_DEFAULT(UseRTMForStackLocks)) {
408 warning("UseRTMForStackLocks flag should be off when UseRTMLocking flag is off");
409 }
410 FLAG_SET_DEFAULT(UseRTMForStackLocks, false);
411 }
412 if (UseRTMDeopt) {
413 FLAG_SET_DEFAULT(UseRTMDeopt, false);
414 }
415 #ifdef COMPILER2
416 if (PrintPreciseRTMLockingStatistics) {
417 FLAG_SET_DEFAULT(PrintPreciseRTMLockingStatistics, false);
418 }
419 #endif
420 }
421
422 // This machine allows unaligned memory accesses
423 if (FLAG_IS_DEFAULT(UseUnalignedAccesses)) {
424 FLAG_SET_DEFAULT(UseUnalignedAccesses, true);
425 }
426
427 check_virtualizations();
428 }
429
430 void VM_Version::check_virtualizations() {
431 #if defined(_AIX)
432 int rc = 0;
433 perfstat_partition_total_t pinfo;
434 rc = perfstat_partition_total(nullptr, &pinfo, sizeof(perfstat_partition_total_t), 1);
435 if (rc == 1) {
436 Abstract_VM_Version::_detected_virtualization = PowerVM;
437 }
438 #else
439 const char* info_file = "/proc/ppc64/lparcfg";
440 // system_type=...qemu indicates PowerKVM
441 // e.g. system_type=IBM pSeries (emulated by qemu)
584 // Keep R3_ARG1 unmodified, it contains &field (see below).
585 // Keep R4_ARG2 unmodified, it contains offset = 0 (see below).
586 a->fsqrt(F3, F4); // code[0] -> fsqrt_m
587 a->fsqrts(F3, F4); // code[1] -> fsqrts_m
588 a->isel(R7, R5, R6, 0); // code[2] -> isel_m
589 a->ldarx_unchecked(R7, R3_ARG1, R4_ARG2, 1); // code[3] -> lxarx_m
590 a->cmpb(R7, R5, R6); // code[4] -> cmpb
591 a->popcntb(R7, R5); // code[5] -> popcntb
592 a->popcntw(R7, R5); // code[6] -> popcntw
593 a->fcfids(F3, F4); // code[7] -> fcfids
594 a->vand(VR0, VR0, VR0); // code[8] -> vand
595 // arg0 of lqarx must be an even register, (arg1 + arg2) must be a multiple of 16
596 a->lqarx_unchecked(R6, R3_ARG1, R4_ARG2, 1); // code[9] -> lqarx_m
597 a->vcipher(VR0, VR1, VR2); // code[10] -> vcipher
598 a->vpmsumb(VR0, VR1, VR2); // code[11] -> vpmsumb
599 a->mfdscr(R0); // code[12] -> mfdscr
600 a->lxvd2x(VSR0, R3_ARG1); // code[13] -> vsx
601 a->ldbrx(R7, R3_ARG1, R4_ARG2); // code[14] -> ldbrx
602 a->stdbrx(R7, R3_ARG1, R4_ARG2); // code[15] -> stdbrx
603 a->vshasigmaw(VR0, VR1, 1, 0xF); // code[16] -> vshasig
604 // rtm is determined by OS
605 a->darn(R7); // code[17] -> darn
606 a->brw(R5, R6); // code[18] -> brw
607 a->blr();
608
609 // Emit function to set one cache line to zero. Emit function descriptor and get pointer to it.
610 void (*zero_cacheline_func_ptr)(char*) = (void(*)(char*))(void *)a->function_entry();
611 a->dcbz(R3_ARG1); // R3_ARG1 = addr
612 a->blr();
613
614 uint32_t *code_end = (uint32_t *)a->pc();
615 a->flush();
616 _features = VM_Version::unknown_m;
617
618 // Print the detection code.
619 if (PrintAssembly) {
620 ttyLocker ttyl;
621 tty->print_cr("Decoding cpu-feature detection stub at " INTPTR_FORMAT " before execution:", p2i(code));
622 Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
623 }
624
638
639 // determine which instructions are legal.
640 int feature_cntr = 0;
641 if (code[feature_cntr++]) features |= fsqrt_m;
642 if (code[feature_cntr++]) features |= fsqrts_m;
643 if (code[feature_cntr++]) features |= isel_m;
644 if (code[feature_cntr++]) features |= lxarxeh_m;
645 if (code[feature_cntr++]) features |= cmpb_m;
646 if (code[feature_cntr++]) features |= popcntb_m;
647 if (code[feature_cntr++]) features |= popcntw_m;
648 if (code[feature_cntr++]) features |= fcfids_m;
649 if (code[feature_cntr++]) features |= vand_m;
650 if (code[feature_cntr++]) features |= lqarx_m;
651 if (code[feature_cntr++]) features |= vcipher_m;
652 if (code[feature_cntr++]) features |= vpmsumb_m;
653 if (code[feature_cntr++]) features |= mfdscr_m;
654 if (code[feature_cntr++]) features |= vsx_m;
655 if (code[feature_cntr++]) features |= ldbrx_m;
656 if (code[feature_cntr++]) features |= stdbrx_m;
657 if (code[feature_cntr++]) features |= vshasig_m;
658 // feature rtm_m is determined by OS
659 if (code[feature_cntr++]) features |= darn_m;
660 if (code[feature_cntr++]) features |= brw_m;
661
662 // Print the detection code.
663 if (PrintAssembly) {
664 ttyLocker ttyl;
665 tty->print_cr("Decoding cpu-feature detection stub at " INTPTR_FORMAT " after execution:", p2i(code));
666 Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
667 }
668
669 _features = features;
670
671 #ifdef AIX
672 // To enable it on AIX it's necessary POWER8 or above and at least AIX 7.2.
673 // Actually, this is supported since AIX 7.1.. Unfortunately, this first
674 // contained bugs, so that it can only be enabled after AIX 7.1.3.30.
675 // The Java property os.version, which is used in RTM tests to decide
676 // whether the feature is available, only knows major and minor versions.
677 // We don't want to change this property, as user code might depend on it.
678 // So the tests can not check on subversion 3.30, and we only enable RTM
679 // with AIX 7.2.
680 if (has_lqarx() && !has_brw()) { // POWER8 or POWER9
681 if (os::Aix::os_version() >= 0x07020000) { // At least AIX 7.2.
682 _features |= rtm_m;
683 }
684 }
685 #endif
686 #if defined(LINUX) && defined(VM_LITTLE_ENDIAN)
687 unsigned long auxv = getauxval(AT_HWCAP2);
688
689 if (auxv & PPC_FEATURE2_HTM_NOSC) {
690 if (auxv & PPC_FEATURE2_HAS_HTM) {
691 // TM on POWER8 and POWER9 in compat mode (VM) is supported by the JVM.
692 // TM on POWER9 DD2.1 NV (baremetal) is not supported by the JVM (TM on
693 // POWER9 DD2.1 NV has a few issues that need a couple of firmware
694 // and kernel workarounds, so there is a new mode only supported
695 // on non-virtualized P9 machines called HTM with no Suspend Mode).
696 // TM on POWER9 D2.2+ NV is not supported at all by Linux.
697 _features |= rtm_m;
698 }
699 }
700 #endif
701 }
702
703 // Power 8: Configure Data Stream Control Register.
704 void VM_Version::config_dscr() {
705 // 7 InstWords for each call (function descriptor + blr instruction).
706 const int code_size = (2+2*7)*BytesPerInstWord;
707
708 // Allocate space for the code.
709 ResourceMark rm;
710 CodeBuffer cb("config_dscr", code_size, 0);
711 MacroAssembler* a = new MacroAssembler(&cb);
712
713 // Emit code.
714 uint64_t (*get_dscr)() = (uint64_t(*)())(void *)a->function_entry();
715 uint32_t *code = (uint32_t *)a->pc();
716 a->mfdscr(R3);
717 a->blr();
718
719 void (*set_dscr)(long) = (void(*)(long))(void *)a->function_entry();
720 a->mtdscr(R3);
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28 #include "asm/macroAssembler.inline.hpp"
29 #include "compiler/disassembler.hpp"
30 #include "jvm.h"
31 #include "memory/resourceArea.hpp"
32 #include "runtime/globals_extension.hpp"
33 #include "runtime/java.hpp"
34 #include "runtime/os.hpp"
35 #include "runtime/stubCodeGenerator.hpp"
36 #include "runtime/vm_version.hpp"
37 #include "utilities/align.hpp"
38 #include "utilities/defaultStream.hpp"
39 #include "utilities/globalDefinitions.hpp"
40 #include "utilities/powerOfTwo.hpp"
41
42 #include <sys/sysinfo.h>
43 #if defined(_AIX)
44 #include "os_aix.hpp"
45 #include <libperfstat.h>
46 #endif
47
48 bool VM_Version::_is_determine_features_test_running = false;
49 uint64_t VM_Version::_dscr_val = 0;
50
51 #define MSG(flag) \
52 if (flag && !FLAG_IS_DEFAULT(flag)) \
53 jio_fprintf(defaultStream::error_stream(), \
54 "warning: -XX:+" #flag " requires -XX:+UseSIGTRAP\n" \
55 " -XX:+" #flag " will be disabled!\n");
56
57 void VM_Version::initialize() {
58
59 // Test which instructions are supported and measure cache line size.
60 determine_features();
61
62 // If PowerArchitecturePPC64 hasn't been specified explicitly determine from features.
63 if (FLAG_IS_DEFAULT(PowerArchitecturePPC64)) {
64 if (VM_Version::has_brw()) {
65 FLAG_SET_ERGO(PowerArchitecturePPC64, 10);
66 } else if (VM_Version::has_darn()) {
67 FLAG_SET_ERGO(PowerArchitecturePPC64, 9);
157 warning("UseBASE64Intrinsics specified, but needs at least Power9.");
158 FLAG_SET_DEFAULT(UseBASE64Intrinsics, false);
159 }
160 }
161
162 if (PowerArchitecturePPC64 >= 10) {
163 if (FLAG_IS_DEFAULT(UseByteReverseInstructions)) {
164 FLAG_SET_ERGO(UseByteReverseInstructions, true);
165 }
166 } else {
167 if (UseByteReverseInstructions) {
168 warning("UseByteReverseInstructions specified, but needs at least Power10.");
169 FLAG_SET_DEFAULT(UseByteReverseInstructions, false);
170 }
171 }
172 #endif
173
174 // Create and print feature-string.
175 char buf[(num_features+1) * 16]; // Max 16 chars per feature.
176 jio_snprintf(buf, sizeof(buf),
177 "ppc64%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
178 (has_fsqrt() ? " fsqrt" : ""),
179 (has_isel() ? " isel" : ""),
180 (has_lxarxeh() ? " lxarxeh" : ""),
181 (has_cmpb() ? " cmpb" : ""),
182 (has_popcntb() ? " popcntb" : ""),
183 (has_popcntw() ? " popcntw" : ""),
184 (has_fcfids() ? " fcfids" : ""),
185 (has_vand() ? " vand" : ""),
186 (has_lqarx() ? " lqarx" : ""),
187 (has_vcipher() ? " aes" : ""),
188 (has_vpmsumb() ? " vpmsumb" : ""),
189 (has_mfdscr() ? " mfdscr" : ""),
190 (has_vsx() ? " vsx" : ""),
191 (has_ldbrx() ? " ldbrx" : ""),
192 (has_stdbrx() ? " stdbrx" : ""),
193 (has_vshasig() ? " sha" : ""),
194 (has_darn() ? " darn" : ""),
195 (has_brw() ? " brw" : "")
196 // Make sure number of %s matches num_features!
197 );
198 _features_string = os::strdup(buf);
199 if (Verbose) {
200 print_features();
201 }
202
203 // PPC64 supports 8-byte compare-exchange operations (see Atomic::cmpxchg)
204 // and 'atomic long memory ops' (see Unsafe_GetLongVolatile).
205 _supports_cx8 = true;
206
207 // Used by C1.
208 _supports_atomic_getset4 = true;
209 _supports_atomic_getadd4 = true;
210 _supports_atomic_getset8 = true;
211 _supports_atomic_getadd8 = true;
212
213 intx cache_line_size = L1_data_cache_line_size();
350 }
351 if (FLAG_IS_DEFAULT(UseMulAddIntrinsic)) {
352 UseMulAddIntrinsic = true;
353 }
354 if (FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) {
355 UseMultiplyToLenIntrinsic = true;
356 }
357 if (FLAG_IS_DEFAULT(UseMontgomeryMultiplyIntrinsic)) {
358 UseMontgomeryMultiplyIntrinsic = true;
359 }
360 if (FLAG_IS_DEFAULT(UseMontgomerySquareIntrinsic)) {
361 UseMontgomerySquareIntrinsic = true;
362 }
363 #endif
364
365 if (UseVectorizedMismatchIntrinsic) {
366 warning("UseVectorizedMismatchIntrinsic specified, but not available on this CPU.");
367 FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false);
368 }
369
370 // This machine allows unaligned memory accesses
371 if (FLAG_IS_DEFAULT(UseUnalignedAccesses)) {
372 FLAG_SET_DEFAULT(UseUnalignedAccesses, true);
373 }
374
375 check_virtualizations();
376 }
377
378 void VM_Version::check_virtualizations() {
379 #if defined(_AIX)
380 int rc = 0;
381 perfstat_partition_total_t pinfo;
382 rc = perfstat_partition_total(nullptr, &pinfo, sizeof(perfstat_partition_total_t), 1);
383 if (rc == 1) {
384 Abstract_VM_Version::_detected_virtualization = PowerVM;
385 }
386 #else
387 const char* info_file = "/proc/ppc64/lparcfg";
388 // system_type=...qemu indicates PowerKVM
389 // e.g. system_type=IBM pSeries (emulated by qemu)
532 // Keep R3_ARG1 unmodified, it contains &field (see below).
533 // Keep R4_ARG2 unmodified, it contains offset = 0 (see below).
534 a->fsqrt(F3, F4); // code[0] -> fsqrt_m
535 a->fsqrts(F3, F4); // code[1] -> fsqrts_m
536 a->isel(R7, R5, R6, 0); // code[2] -> isel_m
537 a->ldarx_unchecked(R7, R3_ARG1, R4_ARG2, 1); // code[3] -> lxarx_m
538 a->cmpb(R7, R5, R6); // code[4] -> cmpb
539 a->popcntb(R7, R5); // code[5] -> popcntb
540 a->popcntw(R7, R5); // code[6] -> popcntw
541 a->fcfids(F3, F4); // code[7] -> fcfids
542 a->vand(VR0, VR0, VR0); // code[8] -> vand
543 // arg0 of lqarx must be an even register, (arg1 + arg2) must be a multiple of 16
544 a->lqarx_unchecked(R6, R3_ARG1, R4_ARG2, 1); // code[9] -> lqarx_m
545 a->vcipher(VR0, VR1, VR2); // code[10] -> vcipher
546 a->vpmsumb(VR0, VR1, VR2); // code[11] -> vpmsumb
547 a->mfdscr(R0); // code[12] -> mfdscr
548 a->lxvd2x(VSR0, R3_ARG1); // code[13] -> vsx
549 a->ldbrx(R7, R3_ARG1, R4_ARG2); // code[14] -> ldbrx
550 a->stdbrx(R7, R3_ARG1, R4_ARG2); // code[15] -> stdbrx
551 a->vshasigmaw(VR0, VR1, 1, 0xF); // code[16] -> vshasig
552 a->darn(R7); // code[17] -> darn
553 a->brw(R5, R6); // code[18] -> brw
554 a->blr();
555
556 // Emit function to set one cache line to zero. Emit function descriptor and get pointer to it.
557 void (*zero_cacheline_func_ptr)(char*) = (void(*)(char*))(void *)a->function_entry();
558 a->dcbz(R3_ARG1); // R3_ARG1 = addr
559 a->blr();
560
561 uint32_t *code_end = (uint32_t *)a->pc();
562 a->flush();
563 _features = VM_Version::unknown_m;
564
565 // Print the detection code.
566 if (PrintAssembly) {
567 ttyLocker ttyl;
568 tty->print_cr("Decoding cpu-feature detection stub at " INTPTR_FORMAT " before execution:", p2i(code));
569 Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
570 }
571
585
586 // determine which instructions are legal.
587 int feature_cntr = 0;
588 if (code[feature_cntr++]) features |= fsqrt_m;
589 if (code[feature_cntr++]) features |= fsqrts_m;
590 if (code[feature_cntr++]) features |= isel_m;
591 if (code[feature_cntr++]) features |= lxarxeh_m;
592 if (code[feature_cntr++]) features |= cmpb_m;
593 if (code[feature_cntr++]) features |= popcntb_m;
594 if (code[feature_cntr++]) features |= popcntw_m;
595 if (code[feature_cntr++]) features |= fcfids_m;
596 if (code[feature_cntr++]) features |= vand_m;
597 if (code[feature_cntr++]) features |= lqarx_m;
598 if (code[feature_cntr++]) features |= vcipher_m;
599 if (code[feature_cntr++]) features |= vpmsumb_m;
600 if (code[feature_cntr++]) features |= mfdscr_m;
601 if (code[feature_cntr++]) features |= vsx_m;
602 if (code[feature_cntr++]) features |= ldbrx_m;
603 if (code[feature_cntr++]) features |= stdbrx_m;
604 if (code[feature_cntr++]) features |= vshasig_m;
605 if (code[feature_cntr++]) features |= darn_m;
606 if (code[feature_cntr++]) features |= brw_m;
607
608 // Print the detection code.
609 if (PrintAssembly) {
610 ttyLocker ttyl;
611 tty->print_cr("Decoding cpu-feature detection stub at " INTPTR_FORMAT " after execution:", p2i(code));
612 Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
613 }
614
615 _features = features;
616 }
617
618 // Power 8: Configure Data Stream Control Register.
619 void VM_Version::config_dscr() {
620 // 7 InstWords for each call (function descriptor + blr instruction).
621 const int code_size = (2+2*7)*BytesPerInstWord;
622
623 // Allocate space for the code.
624 ResourceMark rm;
625 CodeBuffer cb("config_dscr", code_size, 0);
626 MacroAssembler* a = new MacroAssembler(&cb);
627
628 // Emit code.
629 uint64_t (*get_dscr)() = (uint64_t(*)())(void *)a->function_entry();
630 uint32_t *code = (uint32_t *)a->pc();
631 a->mfdscr(R3);
632 a->blr();
633
634 void (*set_dscr)(long) = (void(*)(long))(void *)a->function_entry();
635 a->mtdscr(R3);
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