1 /* 2 * Copyright (c) 2000, 2023, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #include "precompiled.hpp" 26 #include "asm/macroAssembler.hpp" 27 #include "asm/macroAssembler.inline.hpp" 28 #include "c1/c1_CodeStubs.hpp" 29 #include "c1/c1_Compilation.hpp" 30 #include "c1/c1_LIRAssembler.hpp" 31 #include "c1/c1_MacroAssembler.hpp" 32 #include "c1/c1_Runtime1.hpp" 33 #include "c1/c1_ValueStack.hpp" 34 #include "ci/ciArrayKlass.hpp" 35 #include "ci/ciInstance.hpp" 36 #include "compiler/oopMap.hpp" 37 #include "gc/shared/collectedHeap.hpp" 38 #include "gc/shared/gc_globals.hpp" 39 #include "nativeInst_x86.hpp" 40 #include "oops/objArrayKlass.hpp" 41 #include "runtime/frame.inline.hpp" 42 #include "runtime/safepointMechanism.hpp" 43 #include "runtime/sharedRuntime.hpp" 44 #include "runtime/stubRoutines.hpp" 45 #include "utilities/powerOfTwo.hpp" 46 #include "vmreg_x86.inline.hpp" 47 48 49 // These masks are used to provide 128-bit aligned bitmasks to the XMM 50 // instructions, to allow sign-masking or sign-bit flipping. They allow 51 // fast versions of NegF/NegD and AbsF/AbsD. 52 53 // Note: 'double' and 'long long' have 32-bits alignment on x86. 54 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) { 55 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address 56 // of 128-bits operands for SSE instructions. 57 jlong *operand = (jlong*)(((intptr_t)adr) & ((intptr_t)(~0xF))); 58 // Store the value to a 128-bits operand. 59 operand[0] = lo; 60 operand[1] = hi; 61 return operand; 62 } 63 64 // Buffer for 128-bits masks used by SSE instructions. 65 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment) 66 67 // Static initialization during VM startup. 68 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF)); 69 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF)); 70 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], (jlong)UCONST64(0x8000000080000000), (jlong)UCONST64(0x8000000080000000)); 71 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], (jlong)UCONST64(0x8000000000000000), (jlong)UCONST64(0x8000000000000000)); 72 73 74 NEEDS_CLEANUP // remove this definitions ? 75 const Register IC_Klass = rax; // where the IC klass is cached 76 const Register SYNC_header = rax; // synchronization header 77 const Register SHIFT_count = rcx; // where count for shift operations must be 78 79 #define __ _masm-> 80 81 82 static void select_different_registers(Register preserve, 83 Register extra, 84 Register &tmp1, 85 Register &tmp2) { 86 if (tmp1 == preserve) { 87 assert_different_registers(tmp1, tmp2, extra); 88 tmp1 = extra; 89 } else if (tmp2 == preserve) { 90 assert_different_registers(tmp1, tmp2, extra); 91 tmp2 = extra; 92 } 93 assert_different_registers(preserve, tmp1, tmp2); 94 } 95 96 97 98 static void select_different_registers(Register preserve, 99 Register extra, 100 Register &tmp1, 101 Register &tmp2, 102 Register &tmp3) { 103 if (tmp1 == preserve) { 104 assert_different_registers(tmp1, tmp2, tmp3, extra); 105 tmp1 = extra; 106 } else if (tmp2 == preserve) { 107 assert_different_registers(tmp1, tmp2, tmp3, extra); 108 tmp2 = extra; 109 } else if (tmp3 == preserve) { 110 assert_different_registers(tmp1, tmp2, tmp3, extra); 111 tmp3 = extra; 112 } 113 assert_different_registers(preserve, tmp1, tmp2, tmp3); 114 } 115 116 117 118 bool LIR_Assembler::is_small_constant(LIR_Opr opr) { 119 if (opr->is_constant()) { 120 LIR_Const* constant = opr->as_constant_ptr(); 121 switch (constant->type()) { 122 case T_INT: { 123 return true; 124 } 125 126 default: 127 return false; 128 } 129 } 130 return false; 131 } 132 133 134 LIR_Opr LIR_Assembler::receiverOpr() { 135 return FrameMap::receiver_opr; 136 } 137 138 LIR_Opr LIR_Assembler::osrBufferPointer() { 139 return FrameMap::as_pointer_opr(receiverOpr()->as_register()); 140 } 141 142 //--------------fpu register translations----------------------- 143 144 145 address LIR_Assembler::float_constant(float f) { 146 address const_addr = __ float_constant(f); 147 if (const_addr == nullptr) { 148 bailout("const section overflow"); 149 return __ code()->consts()->start(); 150 } else { 151 return const_addr; 152 } 153 } 154 155 156 address LIR_Assembler::double_constant(double d) { 157 address const_addr = __ double_constant(d); 158 if (const_addr == nullptr) { 159 bailout("const section overflow"); 160 return __ code()->consts()->start(); 161 } else { 162 return const_addr; 163 } 164 } 165 166 #ifndef _LP64 167 void LIR_Assembler::fpop() { 168 __ fpop(); 169 } 170 171 void LIR_Assembler::fxch(int i) { 172 __ fxch(i); 173 } 174 175 void LIR_Assembler::fld(int i) { 176 __ fld_s(i); 177 } 178 179 void LIR_Assembler::ffree(int i) { 180 __ ffree(i); 181 } 182 #endif // !_LP64 183 184 void LIR_Assembler::breakpoint() { 185 __ int3(); 186 } 187 188 void LIR_Assembler::push(LIR_Opr opr) { 189 if (opr->is_single_cpu()) { 190 __ push_reg(opr->as_register()); 191 } else if (opr->is_double_cpu()) { 192 NOT_LP64(__ push_reg(opr->as_register_hi())); 193 __ push_reg(opr->as_register_lo()); 194 } else if (opr->is_stack()) { 195 __ push_addr(frame_map()->address_for_slot(opr->single_stack_ix())); 196 } else if (opr->is_constant()) { 197 LIR_Const* const_opr = opr->as_constant_ptr(); 198 if (const_opr->type() == T_OBJECT) { 199 __ push_oop(const_opr->as_jobject(), rscratch1); 200 } else if (const_opr->type() == T_INT) { 201 __ push_jint(const_opr->as_jint()); 202 } else { 203 ShouldNotReachHere(); 204 } 205 206 } else { 207 ShouldNotReachHere(); 208 } 209 } 210 211 void LIR_Assembler::pop(LIR_Opr opr) { 212 if (opr->is_single_cpu()) { 213 __ pop_reg(opr->as_register()); 214 } else { 215 ShouldNotReachHere(); 216 } 217 } 218 219 bool LIR_Assembler::is_literal_address(LIR_Address* addr) { 220 return addr->base()->is_illegal() && addr->index()->is_illegal(); 221 } 222 223 //------------------------------------------- 224 225 Address LIR_Assembler::as_Address(LIR_Address* addr) { 226 return as_Address(addr, rscratch1); 227 } 228 229 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) { 230 if (addr->base()->is_illegal()) { 231 assert(addr->index()->is_illegal(), "must be illegal too"); 232 AddressLiteral laddr((address)addr->disp(), relocInfo::none); 233 if (! __ reachable(laddr)) { 234 __ movptr(tmp, laddr.addr()); 235 Address res(tmp, 0); 236 return res; 237 } else { 238 return __ as_Address(laddr); 239 } 240 } 241 242 Register base = addr->base()->as_pointer_register(); 243 244 if (addr->index()->is_illegal()) { 245 return Address( base, addr->disp()); 246 } else if (addr->index()->is_cpu_register()) { 247 Register index = addr->index()->as_pointer_register(); 248 return Address(base, index, (Address::ScaleFactor) addr->scale(), addr->disp()); 249 } else if (addr->index()->is_constant()) { 250 intptr_t addr_offset = (addr->index()->as_constant_ptr()->as_jint() << addr->scale()) + addr->disp(); 251 assert(Assembler::is_simm32(addr_offset), "must be"); 252 253 return Address(base, addr_offset); 254 } else { 255 Unimplemented(); 256 return Address(); 257 } 258 } 259 260 261 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) { 262 Address base = as_Address(addr); 263 return Address(base._base, base._index, base._scale, base._disp + BytesPerWord); 264 } 265 266 267 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) { 268 return as_Address(addr); 269 } 270 271 272 void LIR_Assembler::osr_entry() { 273 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset()); 274 BlockBegin* osr_entry = compilation()->hir()->osr_entry(); 275 ValueStack* entry_state = osr_entry->state(); 276 int number_of_locks = entry_state->locks_size(); 277 278 // we jump here if osr happens with the interpreter 279 // state set up to continue at the beginning of the 280 // loop that triggered osr - in particular, we have 281 // the following registers setup: 282 // 283 // rcx: osr buffer 284 // 285 286 // build frame 287 ciMethod* m = compilation()->method(); 288 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes()); 289 290 // OSR buffer is 291 // 292 // locals[nlocals-1..0] 293 // monitors[0..number_of_locks] 294 // 295 // locals is a direct copy of the interpreter frame so in the osr buffer 296 // so first slot in the local array is the last local from the interpreter 297 // and last slot is local[0] (receiver) from the interpreter 298 // 299 // Similarly with locks. The first lock slot in the osr buffer is the nth lock 300 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock 301 // in the interpreter frame (the method lock if a sync method) 302 303 // Initialize monitors in the compiled activation. 304 // rcx: pointer to osr buffer 305 // 306 // All other registers are dead at this point and the locals will be 307 // copied into place by code emitted in the IR. 308 309 Register OSR_buf = osrBufferPointer()->as_pointer_register(); 310 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below"); 311 int monitor_offset = BytesPerWord * method()->max_locals() + 312 (BasicObjectLock::size() * BytesPerWord) * (number_of_locks - 1); 313 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in 314 // the OSR buffer using 2 word entries: first the lock and then 315 // the oop. 316 for (int i = 0; i < number_of_locks; i++) { 317 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord); 318 #ifdef ASSERT 319 // verify the interpreter's monitor has a non-null object 320 { 321 Label L; 322 __ cmpptr(Address(OSR_buf, slot_offset + 1*BytesPerWord), NULL_WORD); 323 __ jcc(Assembler::notZero, L); 324 __ stop("locked object is null"); 325 __ bind(L); 326 } 327 #endif 328 __ movptr(rbx, Address(OSR_buf, slot_offset + 0)); 329 __ movptr(frame_map()->address_for_monitor_lock(i), rbx); 330 __ movptr(rbx, Address(OSR_buf, slot_offset + 1*BytesPerWord)); 331 __ movptr(frame_map()->address_for_monitor_object(i), rbx); 332 } 333 } 334 } 335 336 337 // inline cache check; done before the frame is built. 338 int LIR_Assembler::check_icache() { 339 Register receiver = FrameMap::receiver_opr->as_register(); 340 Register ic_klass = IC_Klass; 341 const int ic_cmp_size = LP64_ONLY(10) NOT_LP64(9); 342 const bool do_post_padding = VerifyOops || UseCompressedClassPointers; 343 if (!do_post_padding) { 344 // insert some nops so that the verified entry point is aligned on CodeEntryAlignment 345 __ align(CodeEntryAlignment, __ offset() + ic_cmp_size); 346 } 347 int offset = __ offset(); 348 __ inline_cache_check(receiver, IC_Klass); 349 assert(__ offset() % CodeEntryAlignment == 0 || do_post_padding, "alignment must be correct"); 350 if (do_post_padding) { 351 // force alignment after the cache check. 352 // It's been verified to be aligned if !VerifyOops 353 __ align(CodeEntryAlignment); 354 } 355 return offset; 356 } 357 358 void LIR_Assembler::clinit_barrier(ciMethod* method) { 359 assert(VM_Version::supports_fast_class_init_checks(), "sanity"); 360 assert(!method->holder()->is_not_initialized(), "initialization should have been started"); 361 362 Label L_skip_barrier; 363 Register klass = rscratch1; 364 Register thread = LP64_ONLY( r15_thread ) NOT_LP64( noreg ); 365 assert(thread != noreg, "x86_32 not implemented"); 366 367 __ mov_metadata(klass, method->holder()->constant_encoding()); 368 __ clinit_barrier(klass, thread, &L_skip_barrier /*L_fast_path*/); 369 370 __ jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub())); 371 372 __ bind(L_skip_barrier); 373 } 374 375 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo* info) { 376 jobject o = nullptr; 377 PatchingStub* patch = new PatchingStub(_masm, patching_id(info)); 378 __ movoop(reg, o); 379 patching_epilog(patch, lir_patch_normal, reg, info); 380 } 381 382 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) { 383 Metadata* o = nullptr; 384 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id); 385 __ mov_metadata(reg, o); 386 patching_epilog(patch, lir_patch_normal, reg, info); 387 } 388 389 // This specifies the rsp decrement needed to build the frame 390 int LIR_Assembler::initial_frame_size_in_bytes() const { 391 // if rounding, must let FrameMap know! 392 393 // The frame_map records size in slots (32bit word) 394 395 // subtract two words to account for return address and link 396 return (frame_map()->framesize() - (2*VMRegImpl::slots_per_word)) * VMRegImpl::stack_slot_size; 397 } 398 399 400 int LIR_Assembler::emit_exception_handler() { 401 // generate code for exception handler 402 address handler_base = __ start_a_stub(exception_handler_size()); 403 if (handler_base == nullptr) { 404 // not enough space left for the handler 405 bailout("exception handler overflow"); 406 return -1; 407 } 408 409 int offset = code_offset(); 410 411 // the exception oop and pc are in rax, and rdx 412 // no other registers need to be preserved, so invalidate them 413 __ invalidate_registers(false, true, true, false, true, true); 414 415 // check that there is really an exception 416 __ verify_not_null_oop(rax); 417 418 // search an exception handler (rax: exception oop, rdx: throwing pc) 419 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::handle_exception_from_callee_id))); 420 __ should_not_reach_here(); 421 guarantee(code_offset() - offset <= exception_handler_size(), "overflow"); 422 __ end_a_stub(); 423 424 return offset; 425 } 426 427 428 // Emit the code to remove the frame from the stack in the exception 429 // unwind path. 430 int LIR_Assembler::emit_unwind_handler() { 431 #ifndef PRODUCT 432 if (CommentedAssembly) { 433 _masm->block_comment("Unwind handler"); 434 } 435 #endif 436 437 int offset = code_offset(); 438 439 // Fetch the exception from TLS and clear out exception related thread state 440 Register thread = NOT_LP64(rsi) LP64_ONLY(r15_thread); 441 NOT_LP64(__ get_thread(thread)); 442 __ movptr(rax, Address(thread, JavaThread::exception_oop_offset())); 443 __ movptr(Address(thread, JavaThread::exception_oop_offset()), NULL_WORD); 444 __ movptr(Address(thread, JavaThread::exception_pc_offset()), NULL_WORD); 445 446 __ bind(_unwind_handler_entry); 447 __ verify_not_null_oop(rax); 448 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) { 449 __ mov(rbx, rax); // Preserve the exception (rbx is always callee-saved) 450 } 451 452 // Perform needed unlocking 453 MonitorExitStub* stub = nullptr; 454 if (method()->is_synchronized()) { 455 monitor_address(0, FrameMap::rax_opr); 456 stub = new MonitorExitStub(FrameMap::rax_opr, true, 0); 457 if (LockingMode == LM_MONITOR) { 458 __ jmp(*stub->entry()); 459 } else { 460 __ unlock_object(rdi, rsi, rax, *stub->entry()); 461 } 462 __ bind(*stub->continuation()); 463 } 464 465 if (compilation()->env()->dtrace_method_probes()) { 466 #ifdef _LP64 467 __ mov(rdi, r15_thread); 468 __ mov_metadata(rsi, method()->constant_encoding()); 469 #else 470 __ get_thread(rax); 471 __ movptr(Address(rsp, 0), rax); 472 __ mov_metadata(Address(rsp, sizeof(void*)), method()->constant_encoding(), noreg); 473 #endif 474 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit))); 475 } 476 477 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) { 478 __ mov(rax, rbx); // Restore the exception 479 } 480 481 // remove the activation and dispatch to the unwind handler 482 __ remove_frame(initial_frame_size_in_bytes()); 483 __ jump(RuntimeAddress(Runtime1::entry_for(Runtime1::unwind_exception_id))); 484 485 // Emit the slow path assembly 486 if (stub != nullptr) { 487 stub->emit_code(this); 488 } 489 490 return offset; 491 } 492 493 494 int LIR_Assembler::emit_deopt_handler() { 495 // generate code for exception handler 496 address handler_base = __ start_a_stub(deopt_handler_size()); 497 if (handler_base == nullptr) { 498 // not enough space left for the handler 499 bailout("deopt handler overflow"); 500 return -1; 501 } 502 503 int offset = code_offset(); 504 InternalAddress here(__ pc()); 505 506 __ pushptr(here.addr(), rscratch1); 507 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack())); 508 guarantee(code_offset() - offset <= deopt_handler_size(), "overflow"); 509 __ end_a_stub(); 510 511 return offset; 512 } 513 514 void LIR_Assembler::return_op(LIR_Opr result, C1SafepointPollStub* code_stub) { 515 assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == rax, "word returns are in rax,"); 516 if (!result->is_illegal() && result->is_float_kind() && !result->is_xmm_register()) { 517 assert(result->fpu() == 0, "result must already be on TOS"); 518 } 519 520 // Pop the stack before the safepoint code 521 __ remove_frame(initial_frame_size_in_bytes()); 522 523 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) { 524 __ reserved_stack_check(); 525 } 526 527 // Note: we do not need to round double result; float result has the right precision 528 // the poll sets the condition code, but no data registers 529 530 #ifdef _LP64 531 const Register thread = r15_thread; 532 #else 533 const Register thread = rbx; 534 __ get_thread(thread); 535 #endif 536 code_stub->set_safepoint_offset(__ offset()); 537 __ relocate(relocInfo::poll_return_type); 538 __ safepoint_poll(*code_stub->entry(), thread, true /* at_return */, true /* in_nmethod */); 539 __ ret(0); 540 } 541 542 543 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) { 544 guarantee(info != nullptr, "Shouldn't be null"); 545 int offset = __ offset(); 546 #ifdef _LP64 547 const Register poll_addr = rscratch1; 548 __ movptr(poll_addr, Address(r15_thread, JavaThread::polling_page_offset())); 549 #else 550 assert(tmp->is_cpu_register(), "needed"); 551 const Register poll_addr = tmp->as_register(); 552 __ get_thread(poll_addr); 553 __ movptr(poll_addr, Address(poll_addr, in_bytes(JavaThread::polling_page_offset()))); 554 #endif 555 add_debug_info_for_branch(info); 556 __ relocate(relocInfo::poll_type); 557 address pre_pc = __ pc(); 558 __ testl(rax, Address(poll_addr, 0)); 559 address post_pc = __ pc(); 560 guarantee(pointer_delta(post_pc, pre_pc, 1) == 2 LP64_ONLY(+1), "must be exact length"); 561 return offset; 562 } 563 564 565 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) { 566 if (from_reg != to_reg) __ mov(to_reg, from_reg); 567 } 568 569 void LIR_Assembler::swap_reg(Register a, Register b) { 570 __ xchgptr(a, b); 571 } 572 573 574 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) { 575 assert(src->is_constant(), "should not call otherwise"); 576 assert(dest->is_register(), "should not call otherwise"); 577 LIR_Const* c = src->as_constant_ptr(); 578 579 switch (c->type()) { 580 case T_INT: { 581 assert(patch_code == lir_patch_none, "no patching handled here"); 582 __ movl(dest->as_register(), c->as_jint()); 583 break; 584 } 585 586 case T_ADDRESS: { 587 assert(patch_code == lir_patch_none, "no patching handled here"); 588 __ movptr(dest->as_register(), c->as_jint()); 589 break; 590 } 591 592 case T_LONG: { 593 assert(patch_code == lir_patch_none, "no patching handled here"); 594 #ifdef _LP64 595 __ movptr(dest->as_register_lo(), (intptr_t)c->as_jlong()); 596 #else 597 __ movptr(dest->as_register_lo(), c->as_jint_lo()); 598 __ movptr(dest->as_register_hi(), c->as_jint_hi()); 599 #endif // _LP64 600 break; 601 } 602 603 case T_OBJECT: { 604 if (patch_code != lir_patch_none) { 605 jobject2reg_with_patching(dest->as_register(), info); 606 } else { 607 __ movoop(dest->as_register(), c->as_jobject()); 608 } 609 break; 610 } 611 612 case T_METADATA: { 613 if (patch_code != lir_patch_none) { 614 klass2reg_with_patching(dest->as_register(), info); 615 } else { 616 __ mov_metadata(dest->as_register(), c->as_metadata()); 617 } 618 break; 619 } 620 621 case T_FLOAT: { 622 if (dest->is_single_xmm()) { 623 if (LP64_ONLY(UseAVX <= 2 &&) c->is_zero_float()) { 624 __ xorps(dest->as_xmm_float_reg(), dest->as_xmm_float_reg()); 625 } else { 626 __ movflt(dest->as_xmm_float_reg(), 627 InternalAddress(float_constant(c->as_jfloat()))); 628 } 629 } else { 630 #ifndef _LP64 631 assert(dest->is_single_fpu(), "must be"); 632 assert(dest->fpu_regnr() == 0, "dest must be TOS"); 633 if (c->is_zero_float()) { 634 __ fldz(); 635 } else if (c->is_one_float()) { 636 __ fld1(); 637 } else { 638 __ fld_s (InternalAddress(float_constant(c->as_jfloat()))); 639 } 640 #else 641 ShouldNotReachHere(); 642 #endif // !_LP64 643 } 644 break; 645 } 646 647 case T_DOUBLE: { 648 if (dest->is_double_xmm()) { 649 if (LP64_ONLY(UseAVX <= 2 &&) c->is_zero_double()) { 650 __ xorpd(dest->as_xmm_double_reg(), dest->as_xmm_double_reg()); 651 } else { 652 __ movdbl(dest->as_xmm_double_reg(), 653 InternalAddress(double_constant(c->as_jdouble()))); 654 } 655 } else { 656 #ifndef _LP64 657 assert(dest->is_double_fpu(), "must be"); 658 assert(dest->fpu_regnrLo() == 0, "dest must be TOS"); 659 if (c->is_zero_double()) { 660 __ fldz(); 661 } else if (c->is_one_double()) { 662 __ fld1(); 663 } else { 664 __ fld_d (InternalAddress(double_constant(c->as_jdouble()))); 665 } 666 #else 667 ShouldNotReachHere(); 668 #endif // !_LP64 669 } 670 break; 671 } 672 673 default: 674 ShouldNotReachHere(); 675 } 676 } 677 678 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) { 679 assert(src->is_constant(), "should not call otherwise"); 680 assert(dest->is_stack(), "should not call otherwise"); 681 LIR_Const* c = src->as_constant_ptr(); 682 683 switch (c->type()) { 684 case T_INT: // fall through 685 case T_FLOAT: 686 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits()); 687 break; 688 689 case T_ADDRESS: 690 __ movptr(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits()); 691 break; 692 693 case T_OBJECT: 694 __ movoop(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jobject(), rscratch1); 695 break; 696 697 case T_LONG: // fall through 698 case T_DOUBLE: 699 #ifdef _LP64 700 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(), 701 lo_word_offset_in_bytes), 702 (intptr_t)c->as_jlong_bits(), 703 rscratch1); 704 #else 705 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(), 706 lo_word_offset_in_bytes), c->as_jint_lo_bits()); 707 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(), 708 hi_word_offset_in_bytes), c->as_jint_hi_bits()); 709 #endif // _LP64 710 break; 711 712 default: 713 ShouldNotReachHere(); 714 } 715 } 716 717 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) { 718 assert(src->is_constant(), "should not call otherwise"); 719 assert(dest->is_address(), "should not call otherwise"); 720 LIR_Const* c = src->as_constant_ptr(); 721 LIR_Address* addr = dest->as_address_ptr(); 722 723 int null_check_here = code_offset(); 724 switch (type) { 725 case T_INT: // fall through 726 case T_FLOAT: 727 __ movl(as_Address(addr), c->as_jint_bits()); 728 break; 729 730 case T_ADDRESS: 731 __ movptr(as_Address(addr), c->as_jint_bits()); 732 break; 733 734 case T_OBJECT: // fall through 735 case T_ARRAY: 736 if (c->as_jobject() == nullptr) { 737 if (UseCompressedOops && !wide) { 738 __ movl(as_Address(addr), NULL_WORD); 739 } else { 740 #ifdef _LP64 741 __ xorptr(rscratch1, rscratch1); 742 null_check_here = code_offset(); 743 __ movptr(as_Address(addr), rscratch1); 744 #else 745 __ movptr(as_Address(addr), NULL_WORD); 746 #endif 747 } 748 } else { 749 if (is_literal_address(addr)) { 750 ShouldNotReachHere(); 751 __ movoop(as_Address(addr, noreg), c->as_jobject(), rscratch1); 752 } else { 753 #ifdef _LP64 754 __ movoop(rscratch1, c->as_jobject()); 755 if (UseCompressedOops && !wide) { 756 __ encode_heap_oop(rscratch1); 757 null_check_here = code_offset(); 758 __ movl(as_Address_lo(addr), rscratch1); 759 } else { 760 null_check_here = code_offset(); 761 __ movptr(as_Address_lo(addr), rscratch1); 762 } 763 #else 764 __ movoop(as_Address(addr), c->as_jobject(), noreg); 765 #endif 766 } 767 } 768 break; 769 770 case T_LONG: // fall through 771 case T_DOUBLE: 772 #ifdef _LP64 773 if (is_literal_address(addr)) { 774 ShouldNotReachHere(); 775 __ movptr(as_Address(addr, r15_thread), (intptr_t)c->as_jlong_bits()); 776 } else { 777 __ movptr(r10, (intptr_t)c->as_jlong_bits()); 778 null_check_here = code_offset(); 779 __ movptr(as_Address_lo(addr), r10); 780 } 781 #else 782 // Always reachable in 32bit so this doesn't produce useless move literal 783 __ movptr(as_Address_hi(addr), c->as_jint_hi_bits()); 784 __ movptr(as_Address_lo(addr), c->as_jint_lo_bits()); 785 #endif // _LP64 786 break; 787 788 case T_BOOLEAN: // fall through 789 case T_BYTE: 790 __ movb(as_Address(addr), c->as_jint() & 0xFF); 791 break; 792 793 case T_CHAR: // fall through 794 case T_SHORT: 795 __ movw(as_Address(addr), c->as_jint() & 0xFFFF); 796 break; 797 798 default: 799 ShouldNotReachHere(); 800 }; 801 802 if (info != nullptr) { 803 add_debug_info_for_null_check(null_check_here, info); 804 } 805 } 806 807 808 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) { 809 assert(src->is_register(), "should not call otherwise"); 810 assert(dest->is_register(), "should not call otherwise"); 811 812 // move between cpu-registers 813 if (dest->is_single_cpu()) { 814 #ifdef _LP64 815 if (src->type() == T_LONG) { 816 // Can do LONG -> OBJECT 817 move_regs(src->as_register_lo(), dest->as_register()); 818 return; 819 } 820 #endif 821 assert(src->is_single_cpu(), "must match"); 822 if (src->type() == T_OBJECT) { 823 __ verify_oop(src->as_register()); 824 } 825 move_regs(src->as_register(), dest->as_register()); 826 827 } else if (dest->is_double_cpu()) { 828 #ifdef _LP64 829 if (is_reference_type(src->type())) { 830 // Surprising to me but we can see move of a long to t_object 831 __ verify_oop(src->as_register()); 832 move_regs(src->as_register(), dest->as_register_lo()); 833 return; 834 } 835 #endif 836 assert(src->is_double_cpu(), "must match"); 837 Register f_lo = src->as_register_lo(); 838 Register f_hi = src->as_register_hi(); 839 Register t_lo = dest->as_register_lo(); 840 Register t_hi = dest->as_register_hi(); 841 #ifdef _LP64 842 assert(f_hi == f_lo, "must be same"); 843 assert(t_hi == t_lo, "must be same"); 844 move_regs(f_lo, t_lo); 845 #else 846 assert(f_lo != f_hi && t_lo != t_hi, "invalid register allocation"); 847 848 849 if (f_lo == t_hi && f_hi == t_lo) { 850 swap_reg(f_lo, f_hi); 851 } else if (f_hi == t_lo) { 852 assert(f_lo != t_hi, "overwriting register"); 853 move_regs(f_hi, t_hi); 854 move_regs(f_lo, t_lo); 855 } else { 856 assert(f_hi != t_lo, "overwriting register"); 857 move_regs(f_lo, t_lo); 858 move_regs(f_hi, t_hi); 859 } 860 #endif // LP64 861 862 #ifndef _LP64 863 // special moves from fpu-register to xmm-register 864 // necessary for method results 865 } else if (src->is_single_xmm() && !dest->is_single_xmm()) { 866 __ movflt(Address(rsp, 0), src->as_xmm_float_reg()); 867 __ fld_s(Address(rsp, 0)); 868 } else if (src->is_double_xmm() && !dest->is_double_xmm()) { 869 __ movdbl(Address(rsp, 0), src->as_xmm_double_reg()); 870 __ fld_d(Address(rsp, 0)); 871 } else if (dest->is_single_xmm() && !src->is_single_xmm()) { 872 __ fstp_s(Address(rsp, 0)); 873 __ movflt(dest->as_xmm_float_reg(), Address(rsp, 0)); 874 } else if (dest->is_double_xmm() && !src->is_double_xmm()) { 875 __ fstp_d(Address(rsp, 0)); 876 __ movdbl(dest->as_xmm_double_reg(), Address(rsp, 0)); 877 #endif // !_LP64 878 879 // move between xmm-registers 880 } else if (dest->is_single_xmm()) { 881 assert(src->is_single_xmm(), "must match"); 882 __ movflt(dest->as_xmm_float_reg(), src->as_xmm_float_reg()); 883 } else if (dest->is_double_xmm()) { 884 assert(src->is_double_xmm(), "must match"); 885 __ movdbl(dest->as_xmm_double_reg(), src->as_xmm_double_reg()); 886 887 #ifndef _LP64 888 // move between fpu-registers (no instruction necessary because of fpu-stack) 889 } else if (dest->is_single_fpu() || dest->is_double_fpu()) { 890 assert(src->is_single_fpu() || src->is_double_fpu(), "must match"); 891 assert(src->fpu() == dest->fpu(), "currently should be nothing to do"); 892 #endif // !_LP64 893 894 } else { 895 ShouldNotReachHere(); 896 } 897 } 898 899 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) { 900 assert(src->is_register(), "should not call otherwise"); 901 assert(dest->is_stack(), "should not call otherwise"); 902 903 if (src->is_single_cpu()) { 904 Address dst = frame_map()->address_for_slot(dest->single_stack_ix()); 905 if (is_reference_type(type)) { 906 __ verify_oop(src->as_register()); 907 __ movptr (dst, src->as_register()); 908 } else if (type == T_METADATA || type == T_ADDRESS) { 909 __ movptr (dst, src->as_register()); 910 } else { 911 __ movl (dst, src->as_register()); 912 } 913 914 } else if (src->is_double_cpu()) { 915 Address dstLO = frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes); 916 Address dstHI = frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes); 917 __ movptr (dstLO, src->as_register_lo()); 918 NOT_LP64(__ movptr (dstHI, src->as_register_hi())); 919 920 } else if (src->is_single_xmm()) { 921 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix()); 922 __ movflt(dst_addr, src->as_xmm_float_reg()); 923 924 } else if (src->is_double_xmm()) { 925 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix()); 926 __ movdbl(dst_addr, src->as_xmm_double_reg()); 927 928 #ifndef _LP64 929 } else if (src->is_single_fpu()) { 930 assert(src->fpu_regnr() == 0, "argument must be on TOS"); 931 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix()); 932 if (pop_fpu_stack) __ fstp_s (dst_addr); 933 else __ fst_s (dst_addr); 934 935 } else if (src->is_double_fpu()) { 936 assert(src->fpu_regnrLo() == 0, "argument must be on TOS"); 937 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix()); 938 if (pop_fpu_stack) __ fstp_d (dst_addr); 939 else __ fst_d (dst_addr); 940 #endif // !_LP64 941 942 } else { 943 ShouldNotReachHere(); 944 } 945 } 946 947 948 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool wide) { 949 LIR_Address* to_addr = dest->as_address_ptr(); 950 PatchingStub* patch = nullptr; 951 Register compressed_src = rscratch1; 952 953 if (is_reference_type(type)) { 954 __ verify_oop(src->as_register()); 955 #ifdef _LP64 956 if (UseCompressedOops && !wide) { 957 __ movptr(compressed_src, src->as_register()); 958 __ encode_heap_oop(compressed_src); 959 if (patch_code != lir_patch_none) { 960 info->oop_map()->set_narrowoop(compressed_src->as_VMReg()); 961 } 962 } 963 #endif 964 } 965 966 if (patch_code != lir_patch_none) { 967 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 968 Address toa = as_Address(to_addr); 969 assert(toa.disp() != 0, "must have"); 970 } 971 972 int null_check_here = code_offset(); 973 switch (type) { 974 case T_FLOAT: { 975 #ifdef _LP64 976 assert(src->is_single_xmm(), "not a float"); 977 __ movflt(as_Address(to_addr), src->as_xmm_float_reg()); 978 #else 979 if (src->is_single_xmm()) { 980 __ movflt(as_Address(to_addr), src->as_xmm_float_reg()); 981 } else { 982 assert(src->is_single_fpu(), "must be"); 983 assert(src->fpu_regnr() == 0, "argument must be on TOS"); 984 if (pop_fpu_stack) __ fstp_s(as_Address(to_addr)); 985 else __ fst_s (as_Address(to_addr)); 986 } 987 #endif // _LP64 988 break; 989 } 990 991 case T_DOUBLE: { 992 #ifdef _LP64 993 assert(src->is_double_xmm(), "not a double"); 994 __ movdbl(as_Address(to_addr), src->as_xmm_double_reg()); 995 #else 996 if (src->is_double_xmm()) { 997 __ movdbl(as_Address(to_addr), src->as_xmm_double_reg()); 998 } else { 999 assert(src->is_double_fpu(), "must be"); 1000 assert(src->fpu_regnrLo() == 0, "argument must be on TOS"); 1001 if (pop_fpu_stack) __ fstp_d(as_Address(to_addr)); 1002 else __ fst_d (as_Address(to_addr)); 1003 } 1004 #endif // _LP64 1005 break; 1006 } 1007 1008 case T_ARRAY: // fall through 1009 case T_OBJECT: // fall through 1010 if (UseCompressedOops && !wide) { 1011 __ movl(as_Address(to_addr), compressed_src); 1012 } else { 1013 __ movptr(as_Address(to_addr), src->as_register()); 1014 } 1015 break; 1016 case T_METADATA: 1017 // We get here to store a method pointer to the stack to pass to 1018 // a dtrace runtime call. This can't work on 64 bit with 1019 // compressed klass ptrs: T_METADATA can be a compressed klass 1020 // ptr or a 64 bit method pointer. 1021 LP64_ONLY(ShouldNotReachHere()); 1022 __ movptr(as_Address(to_addr), src->as_register()); 1023 break; 1024 case T_ADDRESS: 1025 __ movptr(as_Address(to_addr), src->as_register()); 1026 break; 1027 case T_INT: 1028 __ movl(as_Address(to_addr), src->as_register()); 1029 break; 1030 1031 case T_LONG: { 1032 Register from_lo = src->as_register_lo(); 1033 Register from_hi = src->as_register_hi(); 1034 #ifdef _LP64 1035 __ movptr(as_Address_lo(to_addr), from_lo); 1036 #else 1037 Register base = to_addr->base()->as_register(); 1038 Register index = noreg; 1039 if (to_addr->index()->is_register()) { 1040 index = to_addr->index()->as_register(); 1041 } 1042 if (base == from_lo || index == from_lo) { 1043 assert(base != from_hi, "can't be"); 1044 assert(index == noreg || (index != base && index != from_hi), "can't handle this"); 1045 __ movl(as_Address_hi(to_addr), from_hi); 1046 if (patch != nullptr) { 1047 patching_epilog(patch, lir_patch_high, base, info); 1048 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1049 patch_code = lir_patch_low; 1050 } 1051 __ movl(as_Address_lo(to_addr), from_lo); 1052 } else { 1053 assert(index == noreg || (index != base && index != from_lo), "can't handle this"); 1054 __ movl(as_Address_lo(to_addr), from_lo); 1055 if (patch != nullptr) { 1056 patching_epilog(patch, lir_patch_low, base, info); 1057 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1058 patch_code = lir_patch_high; 1059 } 1060 __ movl(as_Address_hi(to_addr), from_hi); 1061 } 1062 #endif // _LP64 1063 break; 1064 } 1065 1066 case T_BYTE: // fall through 1067 case T_BOOLEAN: { 1068 Register src_reg = src->as_register(); 1069 Address dst_addr = as_Address(to_addr); 1070 assert(VM_Version::is_P6() || src_reg->has_byte_register(), "must use byte registers if not P6"); 1071 __ movb(dst_addr, src_reg); 1072 break; 1073 } 1074 1075 case T_CHAR: // fall through 1076 case T_SHORT: 1077 __ movw(as_Address(to_addr), src->as_register()); 1078 break; 1079 1080 default: 1081 ShouldNotReachHere(); 1082 } 1083 if (info != nullptr) { 1084 add_debug_info_for_null_check(null_check_here, info); 1085 } 1086 1087 if (patch_code != lir_patch_none) { 1088 patching_epilog(patch, patch_code, to_addr->base()->as_register(), info); 1089 } 1090 } 1091 1092 1093 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) { 1094 assert(src->is_stack(), "should not call otherwise"); 1095 assert(dest->is_register(), "should not call otherwise"); 1096 1097 if (dest->is_single_cpu()) { 1098 if (is_reference_type(type)) { 1099 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix())); 1100 __ verify_oop(dest->as_register()); 1101 } else if (type == T_METADATA || type == T_ADDRESS) { 1102 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix())); 1103 } else { 1104 __ movl(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix())); 1105 } 1106 1107 } else if (dest->is_double_cpu()) { 1108 Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix(), lo_word_offset_in_bytes); 1109 Address src_addr_HI = frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes); 1110 __ movptr(dest->as_register_lo(), src_addr_LO); 1111 NOT_LP64(__ movptr(dest->as_register_hi(), src_addr_HI)); 1112 1113 } else if (dest->is_single_xmm()) { 1114 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix()); 1115 __ movflt(dest->as_xmm_float_reg(), src_addr); 1116 1117 } else if (dest->is_double_xmm()) { 1118 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix()); 1119 __ movdbl(dest->as_xmm_double_reg(), src_addr); 1120 1121 #ifndef _LP64 1122 } else if (dest->is_single_fpu()) { 1123 assert(dest->fpu_regnr() == 0, "dest must be TOS"); 1124 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix()); 1125 __ fld_s(src_addr); 1126 1127 } else if (dest->is_double_fpu()) { 1128 assert(dest->fpu_regnrLo() == 0, "dest must be TOS"); 1129 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix()); 1130 __ fld_d(src_addr); 1131 #endif // _LP64 1132 1133 } else { 1134 ShouldNotReachHere(); 1135 } 1136 } 1137 1138 1139 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) { 1140 if (src->is_single_stack()) { 1141 if (is_reference_type(type)) { 1142 __ pushptr(frame_map()->address_for_slot(src ->single_stack_ix())); 1143 __ popptr (frame_map()->address_for_slot(dest->single_stack_ix())); 1144 } else { 1145 #ifndef _LP64 1146 __ pushl(frame_map()->address_for_slot(src ->single_stack_ix())); 1147 __ popl (frame_map()->address_for_slot(dest->single_stack_ix())); 1148 #else 1149 //no pushl on 64bits 1150 __ movl(rscratch1, frame_map()->address_for_slot(src ->single_stack_ix())); 1151 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), rscratch1); 1152 #endif 1153 } 1154 1155 } else if (src->is_double_stack()) { 1156 #ifdef _LP64 1157 __ pushptr(frame_map()->address_for_slot(src ->double_stack_ix())); 1158 __ popptr (frame_map()->address_for_slot(dest->double_stack_ix())); 1159 #else 1160 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 0)); 1161 // push and pop the part at src + wordSize, adding wordSize for the previous push 1162 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 2 * wordSize)); 1163 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 2 * wordSize)); 1164 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 0)); 1165 #endif // _LP64 1166 1167 } else { 1168 ShouldNotReachHere(); 1169 } 1170 } 1171 1172 1173 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide) { 1174 assert(src->is_address(), "should not call otherwise"); 1175 assert(dest->is_register(), "should not call otherwise"); 1176 1177 LIR_Address* addr = src->as_address_ptr(); 1178 Address from_addr = as_Address(addr); 1179 1180 if (addr->base()->type() == T_OBJECT) { 1181 __ verify_oop(addr->base()->as_pointer_register()); 1182 } 1183 1184 switch (type) { 1185 case T_BOOLEAN: // fall through 1186 case T_BYTE: // fall through 1187 case T_CHAR: // fall through 1188 case T_SHORT: 1189 if (!VM_Version::is_P6() && !from_addr.uses(dest->as_register())) { 1190 // on pre P6 processors we may get partial register stalls 1191 // so blow away the value of to_rinfo before loading a 1192 // partial word into it. Do it here so that it precedes 1193 // the potential patch point below. 1194 __ xorptr(dest->as_register(), dest->as_register()); 1195 } 1196 break; 1197 default: 1198 break; 1199 } 1200 1201 PatchingStub* patch = nullptr; 1202 if (patch_code != lir_patch_none) { 1203 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1204 assert(from_addr.disp() != 0, "must have"); 1205 } 1206 if (info != nullptr) { 1207 add_debug_info_for_null_check_here(info); 1208 } 1209 1210 switch (type) { 1211 case T_FLOAT: { 1212 if (dest->is_single_xmm()) { 1213 __ movflt(dest->as_xmm_float_reg(), from_addr); 1214 } else { 1215 #ifndef _LP64 1216 assert(dest->is_single_fpu(), "must be"); 1217 assert(dest->fpu_regnr() == 0, "dest must be TOS"); 1218 __ fld_s(from_addr); 1219 #else 1220 ShouldNotReachHere(); 1221 #endif // !LP64 1222 } 1223 break; 1224 } 1225 1226 case T_DOUBLE: { 1227 if (dest->is_double_xmm()) { 1228 __ movdbl(dest->as_xmm_double_reg(), from_addr); 1229 } else { 1230 #ifndef _LP64 1231 assert(dest->is_double_fpu(), "must be"); 1232 assert(dest->fpu_regnrLo() == 0, "dest must be TOS"); 1233 __ fld_d(from_addr); 1234 #else 1235 ShouldNotReachHere(); 1236 #endif // !LP64 1237 } 1238 break; 1239 } 1240 1241 case T_OBJECT: // fall through 1242 case T_ARRAY: // fall through 1243 if (UseCompressedOops && !wide) { 1244 __ movl(dest->as_register(), from_addr); 1245 } else { 1246 __ movptr(dest->as_register(), from_addr); 1247 } 1248 break; 1249 1250 case T_ADDRESS: 1251 __ movptr(dest->as_register(), from_addr); 1252 break; 1253 case T_INT: 1254 __ movl(dest->as_register(), from_addr); 1255 break; 1256 1257 case T_LONG: { 1258 Register to_lo = dest->as_register_lo(); 1259 Register to_hi = dest->as_register_hi(); 1260 #ifdef _LP64 1261 __ movptr(to_lo, as_Address_lo(addr)); 1262 #else 1263 Register base = addr->base()->as_register(); 1264 Register index = noreg; 1265 if (addr->index()->is_register()) { 1266 index = addr->index()->as_register(); 1267 } 1268 if ((base == to_lo && index == to_hi) || 1269 (base == to_hi && index == to_lo)) { 1270 // addresses with 2 registers are only formed as a result of 1271 // array access so this code will never have to deal with 1272 // patches or null checks. 1273 assert(info == nullptr && patch == nullptr, "must be"); 1274 __ lea(to_hi, as_Address(addr)); 1275 __ movl(to_lo, Address(to_hi, 0)); 1276 __ movl(to_hi, Address(to_hi, BytesPerWord)); 1277 } else if (base == to_lo || index == to_lo) { 1278 assert(base != to_hi, "can't be"); 1279 assert(index == noreg || (index != base && index != to_hi), "can't handle this"); 1280 __ movl(to_hi, as_Address_hi(addr)); 1281 if (patch != nullptr) { 1282 patching_epilog(patch, lir_patch_high, base, info); 1283 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1284 patch_code = lir_patch_low; 1285 } 1286 __ movl(to_lo, as_Address_lo(addr)); 1287 } else { 1288 assert(index == noreg || (index != base && index != to_lo), "can't handle this"); 1289 __ movl(to_lo, as_Address_lo(addr)); 1290 if (patch != nullptr) { 1291 patching_epilog(patch, lir_patch_low, base, info); 1292 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1293 patch_code = lir_patch_high; 1294 } 1295 __ movl(to_hi, as_Address_hi(addr)); 1296 } 1297 #endif // _LP64 1298 break; 1299 } 1300 1301 case T_BOOLEAN: // fall through 1302 case T_BYTE: { 1303 Register dest_reg = dest->as_register(); 1304 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6"); 1305 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) { 1306 __ movsbl(dest_reg, from_addr); 1307 } else { 1308 __ movb(dest_reg, from_addr); 1309 __ shll(dest_reg, 24); 1310 __ sarl(dest_reg, 24); 1311 } 1312 break; 1313 } 1314 1315 case T_CHAR: { 1316 Register dest_reg = dest->as_register(); 1317 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6"); 1318 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) { 1319 __ movzwl(dest_reg, from_addr); 1320 } else { 1321 __ movw(dest_reg, from_addr); 1322 } 1323 break; 1324 } 1325 1326 case T_SHORT: { 1327 Register dest_reg = dest->as_register(); 1328 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) { 1329 __ movswl(dest_reg, from_addr); 1330 } else { 1331 __ movw(dest_reg, from_addr); 1332 __ shll(dest_reg, 16); 1333 __ sarl(dest_reg, 16); 1334 } 1335 break; 1336 } 1337 1338 default: 1339 ShouldNotReachHere(); 1340 } 1341 1342 if (patch != nullptr) { 1343 patching_epilog(patch, patch_code, addr->base()->as_register(), info); 1344 } 1345 1346 if (is_reference_type(type)) { 1347 #ifdef _LP64 1348 if (UseCompressedOops && !wide) { 1349 __ decode_heap_oop(dest->as_register()); 1350 } 1351 #endif 1352 1353 if (!(UseZGC && !ZGenerational)) { 1354 // Load barrier has not yet been applied, so ZGC can't verify the oop here 1355 __ verify_oop(dest->as_register()); 1356 } 1357 } 1358 } 1359 1360 1361 NEEDS_CLEANUP; // This could be static? 1362 Address::ScaleFactor LIR_Assembler::array_element_size(BasicType type) const { 1363 int elem_size = type2aelembytes(type); 1364 switch (elem_size) { 1365 case 1: return Address::times_1; 1366 case 2: return Address::times_2; 1367 case 4: return Address::times_4; 1368 case 8: return Address::times_8; 1369 } 1370 ShouldNotReachHere(); 1371 return Address::no_scale; 1372 } 1373 1374 1375 void LIR_Assembler::emit_op3(LIR_Op3* op) { 1376 switch (op->code()) { 1377 case lir_idiv: 1378 case lir_irem: 1379 arithmetic_idiv(op->code(), 1380 op->in_opr1(), 1381 op->in_opr2(), 1382 op->in_opr3(), 1383 op->result_opr(), 1384 op->info()); 1385 break; 1386 case lir_fmad: 1387 __ fmad(op->result_opr()->as_xmm_double_reg(), 1388 op->in_opr1()->as_xmm_double_reg(), 1389 op->in_opr2()->as_xmm_double_reg(), 1390 op->in_opr3()->as_xmm_double_reg()); 1391 break; 1392 case lir_fmaf: 1393 __ fmaf(op->result_opr()->as_xmm_float_reg(), 1394 op->in_opr1()->as_xmm_float_reg(), 1395 op->in_opr2()->as_xmm_float_reg(), 1396 op->in_opr3()->as_xmm_float_reg()); 1397 break; 1398 default: ShouldNotReachHere(); break; 1399 } 1400 } 1401 1402 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) { 1403 #ifdef ASSERT 1404 assert(op->block() == nullptr || op->block()->label() == op->label(), "wrong label"); 1405 if (op->block() != nullptr) _branch_target_blocks.append(op->block()); 1406 if (op->ublock() != nullptr) _branch_target_blocks.append(op->ublock()); 1407 #endif 1408 1409 if (op->cond() == lir_cond_always) { 1410 if (op->info() != nullptr) add_debug_info_for_branch(op->info()); 1411 __ jmp (*(op->label())); 1412 } else { 1413 Assembler::Condition acond = Assembler::zero; 1414 if (op->code() == lir_cond_float_branch) { 1415 assert(op->ublock() != nullptr, "must have unordered successor"); 1416 __ jcc(Assembler::parity, *(op->ublock()->label())); 1417 switch(op->cond()) { 1418 case lir_cond_equal: acond = Assembler::equal; break; 1419 case lir_cond_notEqual: acond = Assembler::notEqual; break; 1420 case lir_cond_less: acond = Assembler::below; break; 1421 case lir_cond_lessEqual: acond = Assembler::belowEqual; break; 1422 case lir_cond_greaterEqual: acond = Assembler::aboveEqual; break; 1423 case lir_cond_greater: acond = Assembler::above; break; 1424 default: ShouldNotReachHere(); 1425 } 1426 } else { 1427 switch (op->cond()) { 1428 case lir_cond_equal: acond = Assembler::equal; break; 1429 case lir_cond_notEqual: acond = Assembler::notEqual; break; 1430 case lir_cond_less: acond = Assembler::less; break; 1431 case lir_cond_lessEqual: acond = Assembler::lessEqual; break; 1432 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break; 1433 case lir_cond_greater: acond = Assembler::greater; break; 1434 case lir_cond_belowEqual: acond = Assembler::belowEqual; break; 1435 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break; 1436 default: ShouldNotReachHere(); 1437 } 1438 } 1439 __ jcc(acond,*(op->label())); 1440 } 1441 } 1442 1443 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) { 1444 LIR_Opr src = op->in_opr(); 1445 LIR_Opr dest = op->result_opr(); 1446 1447 switch (op->bytecode()) { 1448 case Bytecodes::_i2l: 1449 #ifdef _LP64 1450 __ movl2ptr(dest->as_register_lo(), src->as_register()); 1451 #else 1452 move_regs(src->as_register(), dest->as_register_lo()); 1453 move_regs(src->as_register(), dest->as_register_hi()); 1454 __ sarl(dest->as_register_hi(), 31); 1455 #endif // LP64 1456 break; 1457 1458 case Bytecodes::_l2i: 1459 #ifdef _LP64 1460 __ movl(dest->as_register(), src->as_register_lo()); 1461 #else 1462 move_regs(src->as_register_lo(), dest->as_register()); 1463 #endif 1464 break; 1465 1466 case Bytecodes::_i2b: 1467 move_regs(src->as_register(), dest->as_register()); 1468 __ sign_extend_byte(dest->as_register()); 1469 break; 1470 1471 case Bytecodes::_i2c: 1472 move_regs(src->as_register(), dest->as_register()); 1473 __ andl(dest->as_register(), 0xFFFF); 1474 break; 1475 1476 case Bytecodes::_i2s: 1477 move_regs(src->as_register(), dest->as_register()); 1478 __ sign_extend_short(dest->as_register()); 1479 break; 1480 1481 1482 #ifdef _LP64 1483 case Bytecodes::_f2d: 1484 __ cvtss2sd(dest->as_xmm_double_reg(), src->as_xmm_float_reg()); 1485 break; 1486 1487 case Bytecodes::_d2f: 1488 __ cvtsd2ss(dest->as_xmm_float_reg(), src->as_xmm_double_reg()); 1489 break; 1490 1491 case Bytecodes::_i2f: 1492 __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register()); 1493 break; 1494 1495 case Bytecodes::_i2d: 1496 __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register()); 1497 break; 1498 1499 case Bytecodes::_l2f: 1500 __ cvtsi2ssq(dest->as_xmm_float_reg(), src->as_register_lo()); 1501 break; 1502 1503 case Bytecodes::_l2d: 1504 __ cvtsi2sdq(dest->as_xmm_double_reg(), src->as_register_lo()); 1505 break; 1506 1507 case Bytecodes::_f2i: 1508 __ convert_f2i(dest->as_register(), src->as_xmm_float_reg()); 1509 break; 1510 1511 case Bytecodes::_d2i: 1512 __ convert_d2i(dest->as_register(), src->as_xmm_double_reg()); 1513 break; 1514 1515 case Bytecodes::_f2l: 1516 __ convert_f2l(dest->as_register_lo(), src->as_xmm_float_reg()); 1517 break; 1518 1519 case Bytecodes::_d2l: 1520 __ convert_d2l(dest->as_register_lo(), src->as_xmm_double_reg()); 1521 break; 1522 #else 1523 case Bytecodes::_f2d: 1524 case Bytecodes::_d2f: 1525 if (dest->is_single_xmm()) { 1526 __ cvtsd2ss(dest->as_xmm_float_reg(), src->as_xmm_double_reg()); 1527 } else if (dest->is_double_xmm()) { 1528 __ cvtss2sd(dest->as_xmm_double_reg(), src->as_xmm_float_reg()); 1529 } else { 1530 assert(src->fpu() == dest->fpu(), "register must be equal"); 1531 // do nothing (float result is rounded later through spilling) 1532 } 1533 break; 1534 1535 case Bytecodes::_i2f: 1536 case Bytecodes::_i2d: 1537 if (dest->is_single_xmm()) { 1538 __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register()); 1539 } else if (dest->is_double_xmm()) { 1540 __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register()); 1541 } else { 1542 assert(dest->fpu() == 0, "result must be on TOS"); 1543 __ movl(Address(rsp, 0), src->as_register()); 1544 __ fild_s(Address(rsp, 0)); 1545 } 1546 break; 1547 1548 case Bytecodes::_l2f: 1549 case Bytecodes::_l2d: 1550 assert(!dest->is_xmm_register(), "result in xmm register not supported (no SSE instruction present)"); 1551 assert(dest->fpu() == 0, "result must be on TOS"); 1552 __ movptr(Address(rsp, 0), src->as_register_lo()); 1553 __ movl(Address(rsp, BytesPerWord), src->as_register_hi()); 1554 __ fild_d(Address(rsp, 0)); 1555 // float result is rounded later through spilling 1556 break; 1557 1558 case Bytecodes::_f2i: 1559 case Bytecodes::_d2i: 1560 if (src->is_single_xmm()) { 1561 __ cvttss2sil(dest->as_register(), src->as_xmm_float_reg()); 1562 } else if (src->is_double_xmm()) { 1563 __ cvttsd2sil(dest->as_register(), src->as_xmm_double_reg()); 1564 } else { 1565 assert(src->fpu() == 0, "input must be on TOS"); 1566 __ fldcw(ExternalAddress(StubRoutines::x86::addr_fpu_cntrl_wrd_trunc())); 1567 __ fist_s(Address(rsp, 0)); 1568 __ movl(dest->as_register(), Address(rsp, 0)); 1569 __ fldcw(ExternalAddress(StubRoutines::x86::addr_fpu_cntrl_wrd_std())); 1570 } 1571 // IA32 conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub 1572 assert(op->stub() != nullptr, "stub required"); 1573 __ cmpl(dest->as_register(), 0x80000000); 1574 __ jcc(Assembler::equal, *op->stub()->entry()); 1575 __ bind(*op->stub()->continuation()); 1576 break; 1577 1578 case Bytecodes::_f2l: 1579 case Bytecodes::_d2l: 1580 assert(!src->is_xmm_register(), "input in xmm register not supported (no SSE instruction present)"); 1581 assert(src->fpu() == 0, "input must be on TOS"); 1582 assert(dest == FrameMap::long0_opr, "runtime stub places result in these registers"); 1583 1584 // instruction sequence too long to inline it here 1585 { 1586 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::fpu2long_stub_id))); 1587 } 1588 break; 1589 #endif // _LP64 1590 1591 default: ShouldNotReachHere(); 1592 } 1593 } 1594 1595 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) { 1596 if (op->init_check()) { 1597 add_debug_info_for_null_check_here(op->stub()->info()); 1598 __ cmpb(Address(op->klass()->as_register(), 1599 InstanceKlass::init_state_offset()), 1600 InstanceKlass::fully_initialized); 1601 __ jcc(Assembler::notEqual, *op->stub()->entry()); 1602 } 1603 __ allocate_object(op->obj()->as_register(), 1604 op->tmp1()->as_register(), 1605 op->tmp2()->as_register(), 1606 op->header_size(), 1607 op->object_size(), 1608 op->klass()->as_register(), 1609 *op->stub()->entry()); 1610 __ bind(*op->stub()->continuation()); 1611 } 1612 1613 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) { 1614 Register len = op->len()->as_register(); 1615 LP64_ONLY( __ movslq(len, len); ) 1616 1617 if (UseSlowPath || 1618 (!UseFastNewObjectArray && is_reference_type(op->type())) || 1619 (!UseFastNewTypeArray && !is_reference_type(op->type()))) { 1620 __ jmp(*op->stub()->entry()); 1621 } else { 1622 Register tmp1 = op->tmp1()->as_register(); 1623 Register tmp2 = op->tmp2()->as_register(); 1624 Register tmp3 = op->tmp3()->as_register(); 1625 if (len == tmp1) { 1626 tmp1 = tmp3; 1627 } else if (len == tmp2) { 1628 tmp2 = tmp3; 1629 } else if (len == tmp3) { 1630 // everything is ok 1631 } else { 1632 __ mov(tmp3, len); 1633 } 1634 __ allocate_array(op->obj()->as_register(), 1635 len, 1636 tmp1, 1637 tmp2, 1638 arrayOopDesc::base_offset_in_bytes(op->type()), 1639 array_element_size(op->type()), 1640 op->klass()->as_register(), 1641 *op->stub()->entry()); 1642 } 1643 __ bind(*op->stub()->continuation()); 1644 } 1645 1646 void LIR_Assembler::type_profile_helper(Register mdo, 1647 ciMethodData *md, ciProfileData *data, 1648 Register recv, Label* update_done) { 1649 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) { 1650 Label next_test; 1651 // See if the receiver is receiver[n]. 1652 __ cmpptr(recv, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)))); 1653 __ jccb(Assembler::notEqual, next_test); 1654 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))); 1655 __ addptr(data_addr, DataLayout::counter_increment); 1656 __ jmp(*update_done); 1657 __ bind(next_test); 1658 } 1659 1660 // Didn't find receiver; find next empty slot and fill it in 1661 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) { 1662 Label next_test; 1663 Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))); 1664 __ cmpptr(recv_addr, NULL_WORD); 1665 __ jccb(Assembler::notEqual, next_test); 1666 __ movptr(recv_addr, recv); 1667 __ movptr(Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))), DataLayout::counter_increment); 1668 __ jmp(*update_done); 1669 __ bind(next_test); 1670 } 1671 } 1672 1673 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) { 1674 // we always need a stub for the failure case. 1675 CodeStub* stub = op->stub(); 1676 Register obj = op->object()->as_register(); 1677 Register k_RInfo = op->tmp1()->as_register(); 1678 Register klass_RInfo = op->tmp2()->as_register(); 1679 Register dst = op->result_opr()->as_register(); 1680 ciKlass* k = op->klass(); 1681 Register Rtmp1 = noreg; 1682 Register tmp_load_klass = LP64_ONLY(rscratch1) NOT_LP64(noreg); 1683 1684 // check if it needs to be profiled 1685 ciMethodData* md = nullptr; 1686 ciProfileData* data = nullptr; 1687 1688 if (op->should_profile()) { 1689 ciMethod* method = op->profiled_method(); 1690 assert(method != nullptr, "Should have method"); 1691 int bci = op->profiled_bci(); 1692 md = method->method_data_or_null(); 1693 assert(md != nullptr, "Sanity"); 1694 data = md->bci_to_data(bci); 1695 assert(data != nullptr, "need data for type check"); 1696 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check"); 1697 } 1698 Label profile_cast_success, profile_cast_failure; 1699 Label *success_target = op->should_profile() ? &profile_cast_success : success; 1700 Label *failure_target = op->should_profile() ? &profile_cast_failure : failure; 1701 1702 if (obj == k_RInfo) { 1703 k_RInfo = dst; 1704 } else if (obj == klass_RInfo) { 1705 klass_RInfo = dst; 1706 } 1707 if (k->is_loaded() && !UseCompressedClassPointers) { 1708 select_different_registers(obj, dst, k_RInfo, klass_RInfo); 1709 } else { 1710 Rtmp1 = op->tmp3()->as_register(); 1711 select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1); 1712 } 1713 1714 assert_different_registers(obj, k_RInfo, klass_RInfo); 1715 1716 __ cmpptr(obj, NULL_WORD); 1717 if (op->should_profile()) { 1718 Label not_null; 1719 __ jccb(Assembler::notEqual, not_null); 1720 // Object is null; update MDO and exit 1721 Register mdo = klass_RInfo; 1722 __ mov_metadata(mdo, md->constant_encoding()); 1723 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset())); 1724 int header_bits = BitData::null_seen_byte_constant(); 1725 __ orb(data_addr, header_bits); 1726 __ jmp(*obj_is_null); 1727 __ bind(not_null); 1728 } else { 1729 __ jcc(Assembler::equal, *obj_is_null); 1730 } 1731 1732 if (!k->is_loaded()) { 1733 klass2reg_with_patching(k_RInfo, op->info_for_patch()); 1734 } else { 1735 #ifdef _LP64 1736 __ mov_metadata(k_RInfo, k->constant_encoding()); 1737 #endif // _LP64 1738 } 1739 __ verify_oop(obj); 1740 1741 if (op->fast_check()) { 1742 // get object class 1743 // not a safepoint as obj null check happens earlier 1744 #ifdef _LP64 1745 if (UseCompressedClassPointers) { 1746 __ load_klass(Rtmp1, obj, tmp_load_klass); 1747 __ cmpptr(k_RInfo, Rtmp1); 1748 } else { 1749 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes())); 1750 } 1751 #else 1752 if (k->is_loaded()) { 1753 __ cmpklass(Address(obj, oopDesc::klass_offset_in_bytes()), k->constant_encoding()); 1754 } else { 1755 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes())); 1756 } 1757 #endif 1758 __ jcc(Assembler::notEqual, *failure_target); 1759 // successful cast, fall through to profile or jump 1760 } else { 1761 // get object class 1762 // not a safepoint as obj null check happens earlier 1763 __ load_klass(klass_RInfo, obj, tmp_load_klass); 1764 if (k->is_loaded()) { 1765 // See if we get an immediate positive hit 1766 #ifdef _LP64 1767 __ cmpptr(k_RInfo, Address(klass_RInfo, k->super_check_offset())); 1768 #else 1769 __ cmpklass(Address(klass_RInfo, k->super_check_offset()), k->constant_encoding()); 1770 #endif // _LP64 1771 if ((juint)in_bytes(Klass::secondary_super_cache_offset()) != k->super_check_offset()) { 1772 __ jcc(Assembler::notEqual, *failure_target); 1773 // successful cast, fall through to profile or jump 1774 } else { 1775 // See if we get an immediate positive hit 1776 __ jcc(Assembler::equal, *success_target); 1777 // check for self 1778 #ifdef _LP64 1779 __ cmpptr(klass_RInfo, k_RInfo); 1780 #else 1781 __ cmpklass(klass_RInfo, k->constant_encoding()); 1782 #endif // _LP64 1783 __ jcc(Assembler::equal, *success_target); 1784 1785 __ push(klass_RInfo); 1786 #ifdef _LP64 1787 __ push(k_RInfo); 1788 #else 1789 __ pushklass(k->constant_encoding(), noreg); 1790 #endif // _LP64 1791 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); 1792 __ pop(klass_RInfo); 1793 __ pop(klass_RInfo); 1794 // result is a boolean 1795 __ cmpl(klass_RInfo, 0); 1796 __ jcc(Assembler::equal, *failure_target); 1797 // successful cast, fall through to profile or jump 1798 } 1799 } else { 1800 // perform the fast part of the checking logic 1801 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, nullptr); 1802 // call out-of-line instance of __ check_klass_subtype_slow_path(...): 1803 __ push(klass_RInfo); 1804 __ push(k_RInfo); 1805 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); 1806 __ pop(klass_RInfo); 1807 __ pop(k_RInfo); 1808 // result is a boolean 1809 __ cmpl(k_RInfo, 0); 1810 __ jcc(Assembler::equal, *failure_target); 1811 // successful cast, fall through to profile or jump 1812 } 1813 } 1814 if (op->should_profile()) { 1815 Register mdo = klass_RInfo, recv = k_RInfo; 1816 __ bind(profile_cast_success); 1817 __ mov_metadata(mdo, md->constant_encoding()); 1818 __ load_klass(recv, obj, tmp_load_klass); 1819 type_profile_helper(mdo, md, data, recv, success); 1820 __ jmp(*success); 1821 1822 __ bind(profile_cast_failure); 1823 __ mov_metadata(mdo, md->constant_encoding()); 1824 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset())); 1825 __ subptr(counter_addr, DataLayout::counter_increment); 1826 __ jmp(*failure); 1827 } 1828 __ jmp(*success); 1829 } 1830 1831 1832 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) { 1833 Register tmp_load_klass = LP64_ONLY(rscratch1) NOT_LP64(noreg); 1834 LIR_Code code = op->code(); 1835 if (code == lir_store_check) { 1836 Register value = op->object()->as_register(); 1837 Register array = op->array()->as_register(); 1838 Register k_RInfo = op->tmp1()->as_register(); 1839 Register klass_RInfo = op->tmp2()->as_register(); 1840 Register Rtmp1 = op->tmp3()->as_register(); 1841 1842 CodeStub* stub = op->stub(); 1843 1844 // check if it needs to be profiled 1845 ciMethodData* md = nullptr; 1846 ciProfileData* data = nullptr; 1847 1848 if (op->should_profile()) { 1849 ciMethod* method = op->profiled_method(); 1850 assert(method != nullptr, "Should have method"); 1851 int bci = op->profiled_bci(); 1852 md = method->method_data_or_null(); 1853 assert(md != nullptr, "Sanity"); 1854 data = md->bci_to_data(bci); 1855 assert(data != nullptr, "need data for type check"); 1856 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check"); 1857 } 1858 Label profile_cast_success, profile_cast_failure, done; 1859 Label *success_target = op->should_profile() ? &profile_cast_success : &done; 1860 Label *failure_target = op->should_profile() ? &profile_cast_failure : stub->entry(); 1861 1862 __ cmpptr(value, NULL_WORD); 1863 if (op->should_profile()) { 1864 Label not_null; 1865 __ jccb(Assembler::notEqual, not_null); 1866 // Object is null; update MDO and exit 1867 Register mdo = klass_RInfo; 1868 __ mov_metadata(mdo, md->constant_encoding()); 1869 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset())); 1870 int header_bits = BitData::null_seen_byte_constant(); 1871 __ orb(data_addr, header_bits); 1872 __ jmp(done); 1873 __ bind(not_null); 1874 } else { 1875 __ jcc(Assembler::equal, done); 1876 } 1877 1878 add_debug_info_for_null_check_here(op->info_for_exception()); 1879 __ load_klass(k_RInfo, array, tmp_load_klass); 1880 __ load_klass(klass_RInfo, value, tmp_load_klass); 1881 1882 // get instance klass (it's already uncompressed) 1883 __ movptr(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset())); 1884 // perform the fast part of the checking logic 1885 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, nullptr); 1886 // call out-of-line instance of __ check_klass_subtype_slow_path(...): 1887 __ push(klass_RInfo); 1888 __ push(k_RInfo); 1889 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); 1890 __ pop(klass_RInfo); 1891 __ pop(k_RInfo); 1892 // result is a boolean 1893 __ cmpl(k_RInfo, 0); 1894 __ jcc(Assembler::equal, *failure_target); 1895 // fall through to the success case 1896 1897 if (op->should_profile()) { 1898 Register mdo = klass_RInfo, recv = k_RInfo; 1899 __ bind(profile_cast_success); 1900 __ mov_metadata(mdo, md->constant_encoding()); 1901 __ load_klass(recv, value, tmp_load_klass); 1902 type_profile_helper(mdo, md, data, recv, &done); 1903 __ jmpb(done); 1904 1905 __ bind(profile_cast_failure); 1906 __ mov_metadata(mdo, md->constant_encoding()); 1907 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset())); 1908 __ subptr(counter_addr, DataLayout::counter_increment); 1909 __ jmp(*stub->entry()); 1910 } 1911 1912 __ bind(done); 1913 } else 1914 if (code == lir_checkcast) { 1915 Register obj = op->object()->as_register(); 1916 Register dst = op->result_opr()->as_register(); 1917 Label success; 1918 emit_typecheck_helper(op, &success, op->stub()->entry(), &success); 1919 __ bind(success); 1920 if (dst != obj) { 1921 __ mov(dst, obj); 1922 } 1923 } else 1924 if (code == lir_instanceof) { 1925 Register obj = op->object()->as_register(); 1926 Register dst = op->result_opr()->as_register(); 1927 Label success, failure, done; 1928 emit_typecheck_helper(op, &success, &failure, &failure); 1929 __ bind(failure); 1930 __ xorptr(dst, dst); 1931 __ jmpb(done); 1932 __ bind(success); 1933 __ movptr(dst, 1); 1934 __ bind(done); 1935 } else { 1936 ShouldNotReachHere(); 1937 } 1938 1939 } 1940 1941 1942 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) { 1943 if (LP64_ONLY(false &&) op->code() == lir_cas_long && VM_Version::supports_cx8()) { 1944 assert(op->cmp_value()->as_register_lo() == rax, "wrong register"); 1945 assert(op->cmp_value()->as_register_hi() == rdx, "wrong register"); 1946 assert(op->new_value()->as_register_lo() == rbx, "wrong register"); 1947 assert(op->new_value()->as_register_hi() == rcx, "wrong register"); 1948 Register addr = op->addr()->as_register(); 1949 __ lock(); 1950 NOT_LP64(__ cmpxchg8(Address(addr, 0))); 1951 1952 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj ) { 1953 NOT_LP64(assert(op->addr()->is_single_cpu(), "must be single");) 1954 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo()); 1955 Register newval = op->new_value()->as_register(); 1956 Register cmpval = op->cmp_value()->as_register(); 1957 assert(cmpval == rax, "wrong register"); 1958 assert(newval != noreg, "new val must be register"); 1959 assert(cmpval != newval, "cmp and new values must be in different registers"); 1960 assert(cmpval != addr, "cmp and addr must be in different registers"); 1961 assert(newval != addr, "new value and addr must be in different registers"); 1962 1963 if ( op->code() == lir_cas_obj) { 1964 #ifdef _LP64 1965 if (UseCompressedOops) { 1966 __ encode_heap_oop(cmpval); 1967 __ mov(rscratch1, newval); 1968 __ encode_heap_oop(rscratch1); 1969 __ lock(); 1970 // cmpval (rax) is implicitly used by this instruction 1971 __ cmpxchgl(rscratch1, Address(addr, 0)); 1972 } else 1973 #endif 1974 { 1975 __ lock(); 1976 __ cmpxchgptr(newval, Address(addr, 0)); 1977 } 1978 } else { 1979 assert(op->code() == lir_cas_int, "lir_cas_int expected"); 1980 __ lock(); 1981 __ cmpxchgl(newval, Address(addr, 0)); 1982 } 1983 #ifdef _LP64 1984 } else if (op->code() == lir_cas_long) { 1985 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo()); 1986 Register newval = op->new_value()->as_register_lo(); 1987 Register cmpval = op->cmp_value()->as_register_lo(); 1988 assert(cmpval == rax, "wrong register"); 1989 assert(newval != noreg, "new val must be register"); 1990 assert(cmpval != newval, "cmp and new values must be in different registers"); 1991 assert(cmpval != addr, "cmp and addr must be in different registers"); 1992 assert(newval != addr, "new value and addr must be in different registers"); 1993 __ lock(); 1994 __ cmpxchgq(newval, Address(addr, 0)); 1995 #endif // _LP64 1996 } else { 1997 Unimplemented(); 1998 } 1999 } 2000 2001 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type, 2002 LIR_Opr cmp_opr1, LIR_Opr cmp_opr2) { 2003 assert(cmp_opr1 == LIR_OprFact::illegalOpr && cmp_opr2 == LIR_OprFact::illegalOpr, "unnecessary cmp oprs on x86"); 2004 2005 Assembler::Condition acond, ncond; 2006 switch (condition) { 2007 case lir_cond_equal: acond = Assembler::equal; ncond = Assembler::notEqual; break; 2008 case lir_cond_notEqual: acond = Assembler::notEqual; ncond = Assembler::equal; break; 2009 case lir_cond_less: acond = Assembler::less; ncond = Assembler::greaterEqual; break; 2010 case lir_cond_lessEqual: acond = Assembler::lessEqual; ncond = Assembler::greater; break; 2011 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; ncond = Assembler::less; break; 2012 case lir_cond_greater: acond = Assembler::greater; ncond = Assembler::lessEqual; break; 2013 case lir_cond_belowEqual: acond = Assembler::belowEqual; ncond = Assembler::above; break; 2014 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; ncond = Assembler::below; break; 2015 default: acond = Assembler::equal; ncond = Assembler::notEqual; 2016 ShouldNotReachHere(); 2017 } 2018 2019 if (opr1->is_cpu_register()) { 2020 reg2reg(opr1, result); 2021 } else if (opr1->is_stack()) { 2022 stack2reg(opr1, result, result->type()); 2023 } else if (opr1->is_constant()) { 2024 const2reg(opr1, result, lir_patch_none, nullptr); 2025 } else { 2026 ShouldNotReachHere(); 2027 } 2028 2029 if (VM_Version::supports_cmov() && !opr2->is_constant()) { 2030 // optimized version that does not require a branch 2031 if (opr2->is_single_cpu()) { 2032 assert(opr2->cpu_regnr() != result->cpu_regnr(), "opr2 already overwritten by previous move"); 2033 __ cmov(ncond, result->as_register(), opr2->as_register()); 2034 } else if (opr2->is_double_cpu()) { 2035 assert(opr2->cpu_regnrLo() != result->cpu_regnrLo() && opr2->cpu_regnrLo() != result->cpu_regnrHi(), "opr2 already overwritten by previous move"); 2036 assert(opr2->cpu_regnrHi() != result->cpu_regnrLo() && opr2->cpu_regnrHi() != result->cpu_regnrHi(), "opr2 already overwritten by previous move"); 2037 __ cmovptr(ncond, result->as_register_lo(), opr2->as_register_lo()); 2038 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), opr2->as_register_hi());) 2039 } else if (opr2->is_single_stack()) { 2040 __ cmovl(ncond, result->as_register(), frame_map()->address_for_slot(opr2->single_stack_ix())); 2041 } else if (opr2->is_double_stack()) { 2042 __ cmovptr(ncond, result->as_register_lo(), frame_map()->address_for_slot(opr2->double_stack_ix(), lo_word_offset_in_bytes)); 2043 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), frame_map()->address_for_slot(opr2->double_stack_ix(), hi_word_offset_in_bytes));) 2044 } else { 2045 ShouldNotReachHere(); 2046 } 2047 2048 } else { 2049 Label skip; 2050 __ jcc (acond, skip); 2051 if (opr2->is_cpu_register()) { 2052 reg2reg(opr2, result); 2053 } else if (opr2->is_stack()) { 2054 stack2reg(opr2, result, result->type()); 2055 } else if (opr2->is_constant()) { 2056 const2reg(opr2, result, lir_patch_none, nullptr); 2057 } else { 2058 ShouldNotReachHere(); 2059 } 2060 __ bind(skip); 2061 } 2062 } 2063 2064 2065 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) { 2066 assert(info == nullptr, "should never be used, idiv/irem and ldiv/lrem not handled by this method"); 2067 2068 if (left->is_single_cpu()) { 2069 assert(left == dest, "left and dest must be equal"); 2070 Register lreg = left->as_register(); 2071 2072 if (right->is_single_cpu()) { 2073 // cpu register - cpu register 2074 Register rreg = right->as_register(); 2075 switch (code) { 2076 case lir_add: __ addl (lreg, rreg); break; 2077 case lir_sub: __ subl (lreg, rreg); break; 2078 case lir_mul: __ imull(lreg, rreg); break; 2079 default: ShouldNotReachHere(); 2080 } 2081 2082 } else if (right->is_stack()) { 2083 // cpu register - stack 2084 Address raddr = frame_map()->address_for_slot(right->single_stack_ix()); 2085 switch (code) { 2086 case lir_add: __ addl(lreg, raddr); break; 2087 case lir_sub: __ subl(lreg, raddr); break; 2088 default: ShouldNotReachHere(); 2089 } 2090 2091 } else if (right->is_constant()) { 2092 // cpu register - constant 2093 jint c = right->as_constant_ptr()->as_jint(); 2094 switch (code) { 2095 case lir_add: { 2096 __ incrementl(lreg, c); 2097 break; 2098 } 2099 case lir_sub: { 2100 __ decrementl(lreg, c); 2101 break; 2102 } 2103 default: ShouldNotReachHere(); 2104 } 2105 2106 } else { 2107 ShouldNotReachHere(); 2108 } 2109 2110 } else if (left->is_double_cpu()) { 2111 assert(left == dest, "left and dest must be equal"); 2112 Register lreg_lo = left->as_register_lo(); 2113 Register lreg_hi = left->as_register_hi(); 2114 2115 if (right->is_double_cpu()) { 2116 // cpu register - cpu register 2117 Register rreg_lo = right->as_register_lo(); 2118 Register rreg_hi = right->as_register_hi(); 2119 NOT_LP64(assert_different_registers(lreg_lo, lreg_hi, rreg_lo, rreg_hi)); 2120 LP64_ONLY(assert_different_registers(lreg_lo, rreg_lo)); 2121 switch (code) { 2122 case lir_add: 2123 __ addptr(lreg_lo, rreg_lo); 2124 NOT_LP64(__ adcl(lreg_hi, rreg_hi)); 2125 break; 2126 case lir_sub: 2127 __ subptr(lreg_lo, rreg_lo); 2128 NOT_LP64(__ sbbl(lreg_hi, rreg_hi)); 2129 break; 2130 case lir_mul: 2131 #ifdef _LP64 2132 __ imulq(lreg_lo, rreg_lo); 2133 #else 2134 assert(lreg_lo == rax && lreg_hi == rdx, "must be"); 2135 __ imull(lreg_hi, rreg_lo); 2136 __ imull(rreg_hi, lreg_lo); 2137 __ addl (rreg_hi, lreg_hi); 2138 __ mull (rreg_lo); 2139 __ addl (lreg_hi, rreg_hi); 2140 #endif // _LP64 2141 break; 2142 default: 2143 ShouldNotReachHere(); 2144 } 2145 2146 } else if (right->is_constant()) { 2147 // cpu register - constant 2148 #ifdef _LP64 2149 jlong c = right->as_constant_ptr()->as_jlong_bits(); 2150 __ movptr(r10, (intptr_t) c); 2151 switch (code) { 2152 case lir_add: 2153 __ addptr(lreg_lo, r10); 2154 break; 2155 case lir_sub: 2156 __ subptr(lreg_lo, r10); 2157 break; 2158 default: 2159 ShouldNotReachHere(); 2160 } 2161 #else 2162 jint c_lo = right->as_constant_ptr()->as_jint_lo(); 2163 jint c_hi = right->as_constant_ptr()->as_jint_hi(); 2164 switch (code) { 2165 case lir_add: 2166 __ addptr(lreg_lo, c_lo); 2167 __ adcl(lreg_hi, c_hi); 2168 break; 2169 case lir_sub: 2170 __ subptr(lreg_lo, c_lo); 2171 __ sbbl(lreg_hi, c_hi); 2172 break; 2173 default: 2174 ShouldNotReachHere(); 2175 } 2176 #endif // _LP64 2177 2178 } else { 2179 ShouldNotReachHere(); 2180 } 2181 2182 } else if (left->is_single_xmm()) { 2183 assert(left == dest, "left and dest must be equal"); 2184 XMMRegister lreg = left->as_xmm_float_reg(); 2185 2186 if (right->is_single_xmm()) { 2187 XMMRegister rreg = right->as_xmm_float_reg(); 2188 switch (code) { 2189 case lir_add: __ addss(lreg, rreg); break; 2190 case lir_sub: __ subss(lreg, rreg); break; 2191 case lir_mul: __ mulss(lreg, rreg); break; 2192 case lir_div: __ divss(lreg, rreg); break; 2193 default: ShouldNotReachHere(); 2194 } 2195 } else { 2196 Address raddr; 2197 if (right->is_single_stack()) { 2198 raddr = frame_map()->address_for_slot(right->single_stack_ix()); 2199 } else if (right->is_constant()) { 2200 // hack for now 2201 raddr = __ as_Address(InternalAddress(float_constant(right->as_jfloat()))); 2202 } else { 2203 ShouldNotReachHere(); 2204 } 2205 switch (code) { 2206 case lir_add: __ addss(lreg, raddr); break; 2207 case lir_sub: __ subss(lreg, raddr); break; 2208 case lir_mul: __ mulss(lreg, raddr); break; 2209 case lir_div: __ divss(lreg, raddr); break; 2210 default: ShouldNotReachHere(); 2211 } 2212 } 2213 2214 } else if (left->is_double_xmm()) { 2215 assert(left == dest, "left and dest must be equal"); 2216 2217 XMMRegister lreg = left->as_xmm_double_reg(); 2218 if (right->is_double_xmm()) { 2219 XMMRegister rreg = right->as_xmm_double_reg(); 2220 switch (code) { 2221 case lir_add: __ addsd(lreg, rreg); break; 2222 case lir_sub: __ subsd(lreg, rreg); break; 2223 case lir_mul: __ mulsd(lreg, rreg); break; 2224 case lir_div: __ divsd(lreg, rreg); break; 2225 default: ShouldNotReachHere(); 2226 } 2227 } else { 2228 Address raddr; 2229 if (right->is_double_stack()) { 2230 raddr = frame_map()->address_for_slot(right->double_stack_ix()); 2231 } else if (right->is_constant()) { 2232 // hack for now 2233 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble()))); 2234 } else { 2235 ShouldNotReachHere(); 2236 } 2237 switch (code) { 2238 case lir_add: __ addsd(lreg, raddr); break; 2239 case lir_sub: __ subsd(lreg, raddr); break; 2240 case lir_mul: __ mulsd(lreg, raddr); break; 2241 case lir_div: __ divsd(lreg, raddr); break; 2242 default: ShouldNotReachHere(); 2243 } 2244 } 2245 2246 #ifndef _LP64 2247 } else if (left->is_single_fpu()) { 2248 assert(dest->is_single_fpu(), "fpu stack allocation required"); 2249 2250 if (right->is_single_fpu()) { 2251 arith_fpu_implementation(code, left->fpu_regnr(), right->fpu_regnr(), dest->fpu_regnr(), pop_fpu_stack); 2252 2253 } else { 2254 assert(left->fpu_regnr() == 0, "left must be on TOS"); 2255 assert(dest->fpu_regnr() == 0, "dest must be on TOS"); 2256 2257 Address raddr; 2258 if (right->is_single_stack()) { 2259 raddr = frame_map()->address_for_slot(right->single_stack_ix()); 2260 } else if (right->is_constant()) { 2261 address const_addr = float_constant(right->as_jfloat()); 2262 assert(const_addr != nullptr, "incorrect float/double constant maintenance"); 2263 // hack for now 2264 raddr = __ as_Address(InternalAddress(const_addr)); 2265 } else { 2266 ShouldNotReachHere(); 2267 } 2268 2269 switch (code) { 2270 case lir_add: __ fadd_s(raddr); break; 2271 case lir_sub: __ fsub_s(raddr); break; 2272 case lir_mul: __ fmul_s(raddr); break; 2273 case lir_div: __ fdiv_s(raddr); break; 2274 default: ShouldNotReachHere(); 2275 } 2276 } 2277 2278 } else if (left->is_double_fpu()) { 2279 assert(dest->is_double_fpu(), "fpu stack allocation required"); 2280 2281 if (code == lir_mul || code == lir_div) { 2282 // Double values require special handling for strictfp mul/div on x86 2283 __ fld_x(ExternalAddress(StubRoutines::x86::addr_fpu_subnormal_bias1())); 2284 __ fmulp(left->fpu_regnrLo() + 1); 2285 } 2286 2287 if (right->is_double_fpu()) { 2288 arith_fpu_implementation(code, left->fpu_regnrLo(), right->fpu_regnrLo(), dest->fpu_regnrLo(), pop_fpu_stack); 2289 2290 } else { 2291 assert(left->fpu_regnrLo() == 0, "left must be on TOS"); 2292 assert(dest->fpu_regnrLo() == 0, "dest must be on TOS"); 2293 2294 Address raddr; 2295 if (right->is_double_stack()) { 2296 raddr = frame_map()->address_for_slot(right->double_stack_ix()); 2297 } else if (right->is_constant()) { 2298 // hack for now 2299 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble()))); 2300 } else { 2301 ShouldNotReachHere(); 2302 } 2303 2304 switch (code) { 2305 case lir_add: __ fadd_d(raddr); break; 2306 case lir_sub: __ fsub_d(raddr); break; 2307 case lir_mul: __ fmul_d(raddr); break; 2308 case lir_div: __ fdiv_d(raddr); break; 2309 default: ShouldNotReachHere(); 2310 } 2311 } 2312 2313 if (code == lir_mul || code == lir_div) { 2314 // Double values require special handling for strictfp mul/div on x86 2315 __ fld_x(ExternalAddress(StubRoutines::x86::addr_fpu_subnormal_bias2())); 2316 __ fmulp(dest->fpu_regnrLo() + 1); 2317 } 2318 #endif // !_LP64 2319 2320 } else if (left->is_single_stack() || left->is_address()) { 2321 assert(left == dest, "left and dest must be equal"); 2322 2323 Address laddr; 2324 if (left->is_single_stack()) { 2325 laddr = frame_map()->address_for_slot(left->single_stack_ix()); 2326 } else if (left->is_address()) { 2327 laddr = as_Address(left->as_address_ptr()); 2328 } else { 2329 ShouldNotReachHere(); 2330 } 2331 2332 if (right->is_single_cpu()) { 2333 Register rreg = right->as_register(); 2334 switch (code) { 2335 case lir_add: __ addl(laddr, rreg); break; 2336 case lir_sub: __ subl(laddr, rreg); break; 2337 default: ShouldNotReachHere(); 2338 } 2339 } else if (right->is_constant()) { 2340 jint c = right->as_constant_ptr()->as_jint(); 2341 switch (code) { 2342 case lir_add: { 2343 __ incrementl(laddr, c); 2344 break; 2345 } 2346 case lir_sub: { 2347 __ decrementl(laddr, c); 2348 break; 2349 } 2350 default: ShouldNotReachHere(); 2351 } 2352 } else { 2353 ShouldNotReachHere(); 2354 } 2355 2356 } else { 2357 ShouldNotReachHere(); 2358 } 2359 } 2360 2361 #ifndef _LP64 2362 void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) { 2363 assert(pop_fpu_stack || (left_index == dest_index || right_index == dest_index), "invalid LIR"); 2364 assert(!pop_fpu_stack || (left_index - 1 == dest_index || right_index - 1 == dest_index), "invalid LIR"); 2365 assert(left_index == 0 || right_index == 0, "either must be on top of stack"); 2366 2367 bool left_is_tos = (left_index == 0); 2368 bool dest_is_tos = (dest_index == 0); 2369 int non_tos_index = (left_is_tos ? right_index : left_index); 2370 2371 switch (code) { 2372 case lir_add: 2373 if (pop_fpu_stack) __ faddp(non_tos_index); 2374 else if (dest_is_tos) __ fadd (non_tos_index); 2375 else __ fadda(non_tos_index); 2376 break; 2377 2378 case lir_sub: 2379 if (left_is_tos) { 2380 if (pop_fpu_stack) __ fsubrp(non_tos_index); 2381 else if (dest_is_tos) __ fsub (non_tos_index); 2382 else __ fsubra(non_tos_index); 2383 } else { 2384 if (pop_fpu_stack) __ fsubp (non_tos_index); 2385 else if (dest_is_tos) __ fsubr (non_tos_index); 2386 else __ fsuba (non_tos_index); 2387 } 2388 break; 2389 2390 case lir_mul: 2391 if (pop_fpu_stack) __ fmulp(non_tos_index); 2392 else if (dest_is_tos) __ fmul (non_tos_index); 2393 else __ fmula(non_tos_index); 2394 break; 2395 2396 case lir_div: 2397 if (left_is_tos) { 2398 if (pop_fpu_stack) __ fdivrp(non_tos_index); 2399 else if (dest_is_tos) __ fdiv (non_tos_index); 2400 else __ fdivra(non_tos_index); 2401 } else { 2402 if (pop_fpu_stack) __ fdivp (non_tos_index); 2403 else if (dest_is_tos) __ fdivr (non_tos_index); 2404 else __ fdiva (non_tos_index); 2405 } 2406 break; 2407 2408 case lir_rem: 2409 assert(left_is_tos && dest_is_tos && right_index == 1, "must be guaranteed by FPU stack allocation"); 2410 __ fremr(noreg); 2411 break; 2412 2413 default: 2414 ShouldNotReachHere(); 2415 } 2416 } 2417 #endif // _LP64 2418 2419 2420 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr tmp, LIR_Opr dest, LIR_Op* op) { 2421 if (value->is_double_xmm()) { 2422 switch(code) { 2423 case lir_abs : 2424 { 2425 #ifdef _LP64 2426 if (UseAVX > 2 && !VM_Version::supports_avx512vl()) { 2427 assert(tmp->is_valid(), "need temporary"); 2428 __ vpandn(dest->as_xmm_double_reg(), tmp->as_xmm_double_reg(), value->as_xmm_double_reg(), 2); 2429 } else 2430 #endif 2431 { 2432 if (dest->as_xmm_double_reg() != value->as_xmm_double_reg()) { 2433 __ movdbl(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); 2434 } 2435 assert(!tmp->is_valid(), "do not need temporary"); 2436 __ andpd(dest->as_xmm_double_reg(), 2437 ExternalAddress((address)double_signmask_pool), 2438 rscratch1); 2439 } 2440 } 2441 break; 2442 2443 case lir_sqrt: __ sqrtsd(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); break; 2444 // all other intrinsics are not available in the SSE instruction set, so FPU is used 2445 default : ShouldNotReachHere(); 2446 } 2447 2448 #ifndef _LP64 2449 } else if (value->is_double_fpu()) { 2450 assert(value->fpu_regnrLo() == 0 && dest->fpu_regnrLo() == 0, "both must be on TOS"); 2451 switch(code) { 2452 case lir_abs : __ fabs() ; break; 2453 case lir_sqrt : __ fsqrt(); break; 2454 default : ShouldNotReachHere(); 2455 } 2456 #endif // !_LP64 2457 } else if (code == lir_f2hf) { 2458 __ flt_to_flt16(dest->as_register(), value->as_xmm_float_reg(), tmp->as_xmm_float_reg()); 2459 } else if (code == lir_hf2f) { 2460 __ flt16_to_flt(dest->as_xmm_float_reg(), value->as_register()); 2461 } else { 2462 Unimplemented(); 2463 } 2464 } 2465 2466 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) { 2467 // assert(left->destroys_register(), "check"); 2468 if (left->is_single_cpu()) { 2469 Register reg = left->as_register(); 2470 if (right->is_constant()) { 2471 int val = right->as_constant_ptr()->as_jint(); 2472 switch (code) { 2473 case lir_logic_and: __ andl (reg, val); break; 2474 case lir_logic_or: __ orl (reg, val); break; 2475 case lir_logic_xor: __ xorl (reg, val); break; 2476 default: ShouldNotReachHere(); 2477 } 2478 } else if (right->is_stack()) { 2479 // added support for stack operands 2480 Address raddr = frame_map()->address_for_slot(right->single_stack_ix()); 2481 switch (code) { 2482 case lir_logic_and: __ andl (reg, raddr); break; 2483 case lir_logic_or: __ orl (reg, raddr); break; 2484 case lir_logic_xor: __ xorl (reg, raddr); break; 2485 default: ShouldNotReachHere(); 2486 } 2487 } else { 2488 Register rright = right->as_register(); 2489 switch (code) { 2490 case lir_logic_and: __ andptr (reg, rright); break; 2491 case lir_logic_or : __ orptr (reg, rright); break; 2492 case lir_logic_xor: __ xorptr (reg, rright); break; 2493 default: ShouldNotReachHere(); 2494 } 2495 } 2496 move_regs(reg, dst->as_register()); 2497 } else { 2498 Register l_lo = left->as_register_lo(); 2499 Register l_hi = left->as_register_hi(); 2500 if (right->is_constant()) { 2501 #ifdef _LP64 2502 __ mov64(rscratch1, right->as_constant_ptr()->as_jlong()); 2503 switch (code) { 2504 case lir_logic_and: 2505 __ andq(l_lo, rscratch1); 2506 break; 2507 case lir_logic_or: 2508 __ orq(l_lo, rscratch1); 2509 break; 2510 case lir_logic_xor: 2511 __ xorq(l_lo, rscratch1); 2512 break; 2513 default: ShouldNotReachHere(); 2514 } 2515 #else 2516 int r_lo = right->as_constant_ptr()->as_jint_lo(); 2517 int r_hi = right->as_constant_ptr()->as_jint_hi(); 2518 switch (code) { 2519 case lir_logic_and: 2520 __ andl(l_lo, r_lo); 2521 __ andl(l_hi, r_hi); 2522 break; 2523 case lir_logic_or: 2524 __ orl(l_lo, r_lo); 2525 __ orl(l_hi, r_hi); 2526 break; 2527 case lir_logic_xor: 2528 __ xorl(l_lo, r_lo); 2529 __ xorl(l_hi, r_hi); 2530 break; 2531 default: ShouldNotReachHere(); 2532 } 2533 #endif // _LP64 2534 } else { 2535 #ifdef _LP64 2536 Register r_lo; 2537 if (is_reference_type(right->type())) { 2538 r_lo = right->as_register(); 2539 } else { 2540 r_lo = right->as_register_lo(); 2541 } 2542 #else 2543 Register r_lo = right->as_register_lo(); 2544 Register r_hi = right->as_register_hi(); 2545 assert(l_lo != r_hi, "overwriting registers"); 2546 #endif 2547 switch (code) { 2548 case lir_logic_and: 2549 __ andptr(l_lo, r_lo); 2550 NOT_LP64(__ andptr(l_hi, r_hi);) 2551 break; 2552 case lir_logic_or: 2553 __ orptr(l_lo, r_lo); 2554 NOT_LP64(__ orptr(l_hi, r_hi);) 2555 break; 2556 case lir_logic_xor: 2557 __ xorptr(l_lo, r_lo); 2558 NOT_LP64(__ xorptr(l_hi, r_hi);) 2559 break; 2560 default: ShouldNotReachHere(); 2561 } 2562 } 2563 2564 Register dst_lo = dst->as_register_lo(); 2565 Register dst_hi = dst->as_register_hi(); 2566 2567 #ifdef _LP64 2568 move_regs(l_lo, dst_lo); 2569 #else 2570 if (dst_lo == l_hi) { 2571 assert(dst_hi != l_lo, "overwriting registers"); 2572 move_regs(l_hi, dst_hi); 2573 move_regs(l_lo, dst_lo); 2574 } else { 2575 assert(dst_lo != l_hi, "overwriting registers"); 2576 move_regs(l_lo, dst_lo); 2577 move_regs(l_hi, dst_hi); 2578 } 2579 #endif // _LP64 2580 } 2581 } 2582 2583 2584 // we assume that rax, and rdx can be overwritten 2585 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) { 2586 2587 assert(left->is_single_cpu(), "left must be register"); 2588 assert(right->is_single_cpu() || right->is_constant(), "right must be register or constant"); 2589 assert(result->is_single_cpu(), "result must be register"); 2590 2591 // assert(left->destroys_register(), "check"); 2592 // assert(right->destroys_register(), "check"); 2593 2594 Register lreg = left->as_register(); 2595 Register dreg = result->as_register(); 2596 2597 if (right->is_constant()) { 2598 jint divisor = right->as_constant_ptr()->as_jint(); 2599 assert(divisor > 0 && is_power_of_2(divisor), "must be"); 2600 if (code == lir_idiv) { 2601 assert(lreg == rax, "must be rax,"); 2602 assert(temp->as_register() == rdx, "tmp register must be rdx"); 2603 __ cdql(); // sign extend into rdx:rax 2604 if (divisor == 2) { 2605 __ subl(lreg, rdx); 2606 } else { 2607 __ andl(rdx, divisor - 1); 2608 __ addl(lreg, rdx); 2609 } 2610 __ sarl(lreg, log2i_exact(divisor)); 2611 move_regs(lreg, dreg); 2612 } else if (code == lir_irem) { 2613 Label done; 2614 __ mov(dreg, lreg); 2615 __ andl(dreg, 0x80000000 | (divisor - 1)); 2616 __ jcc(Assembler::positive, done); 2617 __ decrement(dreg); 2618 __ orl(dreg, ~(divisor - 1)); 2619 __ increment(dreg); 2620 __ bind(done); 2621 } else { 2622 ShouldNotReachHere(); 2623 } 2624 } else { 2625 Register rreg = right->as_register(); 2626 assert(lreg == rax, "left register must be rax,"); 2627 assert(rreg != rdx, "right register must not be rdx"); 2628 assert(temp->as_register() == rdx, "tmp register must be rdx"); 2629 2630 move_regs(lreg, rax); 2631 2632 int idivl_offset = __ corrected_idivl(rreg); 2633 if (ImplicitDiv0Checks) { 2634 add_debug_info_for_div0(idivl_offset, info); 2635 } 2636 if (code == lir_irem) { 2637 move_regs(rdx, dreg); // result is in rdx 2638 } else { 2639 move_regs(rax, dreg); 2640 } 2641 } 2642 } 2643 2644 2645 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) { 2646 if (opr1->is_single_cpu()) { 2647 Register reg1 = opr1->as_register(); 2648 if (opr2->is_single_cpu()) { 2649 // cpu register - cpu register 2650 if (is_reference_type(opr1->type())) { 2651 __ cmpoop(reg1, opr2->as_register()); 2652 } else { 2653 assert(!is_reference_type(opr2->type()), "cmp int, oop?"); 2654 __ cmpl(reg1, opr2->as_register()); 2655 } 2656 } else if (opr2->is_stack()) { 2657 // cpu register - stack 2658 if (is_reference_type(opr1->type())) { 2659 __ cmpoop(reg1, frame_map()->address_for_slot(opr2->single_stack_ix())); 2660 } else { 2661 __ cmpl(reg1, frame_map()->address_for_slot(opr2->single_stack_ix())); 2662 } 2663 } else if (opr2->is_constant()) { 2664 // cpu register - constant 2665 LIR_Const* c = opr2->as_constant_ptr(); 2666 if (c->type() == T_INT) { 2667 __ cmpl(reg1, c->as_jint()); 2668 } else if (c->type() == T_METADATA) { 2669 // All we need for now is a comparison with null for equality. 2670 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "oops"); 2671 Metadata* m = c->as_metadata(); 2672 if (m == nullptr) { 2673 __ cmpptr(reg1, NULL_WORD); 2674 } else { 2675 ShouldNotReachHere(); 2676 } 2677 } else if (is_reference_type(c->type())) { 2678 // In 64bit oops are single register 2679 jobject o = c->as_jobject(); 2680 if (o == nullptr) { 2681 __ cmpptr(reg1, NULL_WORD); 2682 } else { 2683 __ cmpoop(reg1, o, rscratch1); 2684 } 2685 } else { 2686 fatal("unexpected type: %s", basictype_to_str(c->type())); 2687 } 2688 // cpu register - address 2689 } else if (opr2->is_address()) { 2690 if (op->info() != nullptr) { 2691 add_debug_info_for_null_check_here(op->info()); 2692 } 2693 __ cmpl(reg1, as_Address(opr2->as_address_ptr())); 2694 } else { 2695 ShouldNotReachHere(); 2696 } 2697 2698 } else if(opr1->is_double_cpu()) { 2699 Register xlo = opr1->as_register_lo(); 2700 Register xhi = opr1->as_register_hi(); 2701 if (opr2->is_double_cpu()) { 2702 #ifdef _LP64 2703 __ cmpptr(xlo, opr2->as_register_lo()); 2704 #else 2705 // cpu register - cpu register 2706 Register ylo = opr2->as_register_lo(); 2707 Register yhi = opr2->as_register_hi(); 2708 __ subl(xlo, ylo); 2709 __ sbbl(xhi, yhi); 2710 if (condition == lir_cond_equal || condition == lir_cond_notEqual) { 2711 __ orl(xhi, xlo); 2712 } 2713 #endif // _LP64 2714 } else if (opr2->is_constant()) { 2715 // cpu register - constant 0 2716 assert(opr2->as_jlong() == (jlong)0, "only handles zero"); 2717 #ifdef _LP64 2718 __ cmpptr(xlo, (int32_t)opr2->as_jlong()); 2719 #else 2720 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles equals case"); 2721 __ orl(xhi, xlo); 2722 #endif // _LP64 2723 } else { 2724 ShouldNotReachHere(); 2725 } 2726 2727 } else if (opr1->is_single_xmm()) { 2728 XMMRegister reg1 = opr1->as_xmm_float_reg(); 2729 if (opr2->is_single_xmm()) { 2730 // xmm register - xmm register 2731 __ ucomiss(reg1, opr2->as_xmm_float_reg()); 2732 } else if (opr2->is_stack()) { 2733 // xmm register - stack 2734 __ ucomiss(reg1, frame_map()->address_for_slot(opr2->single_stack_ix())); 2735 } else if (opr2->is_constant()) { 2736 // xmm register - constant 2737 __ ucomiss(reg1, InternalAddress(float_constant(opr2->as_jfloat()))); 2738 } else if (opr2->is_address()) { 2739 // xmm register - address 2740 if (op->info() != nullptr) { 2741 add_debug_info_for_null_check_here(op->info()); 2742 } 2743 __ ucomiss(reg1, as_Address(opr2->as_address_ptr())); 2744 } else { 2745 ShouldNotReachHere(); 2746 } 2747 2748 } else if (opr1->is_double_xmm()) { 2749 XMMRegister reg1 = opr1->as_xmm_double_reg(); 2750 if (opr2->is_double_xmm()) { 2751 // xmm register - xmm register 2752 __ ucomisd(reg1, opr2->as_xmm_double_reg()); 2753 } else if (opr2->is_stack()) { 2754 // xmm register - stack 2755 __ ucomisd(reg1, frame_map()->address_for_slot(opr2->double_stack_ix())); 2756 } else if (opr2->is_constant()) { 2757 // xmm register - constant 2758 __ ucomisd(reg1, InternalAddress(double_constant(opr2->as_jdouble()))); 2759 } else if (opr2->is_address()) { 2760 // xmm register - address 2761 if (op->info() != nullptr) { 2762 add_debug_info_for_null_check_here(op->info()); 2763 } 2764 __ ucomisd(reg1, as_Address(opr2->pointer()->as_address())); 2765 } else { 2766 ShouldNotReachHere(); 2767 } 2768 2769 #ifndef _LP64 2770 } else if(opr1->is_single_fpu() || opr1->is_double_fpu()) { 2771 assert(opr1->is_fpu_register() && opr1->fpu() == 0, "currently left-hand side must be on TOS (relax this restriction)"); 2772 assert(opr2->is_fpu_register(), "both must be registers"); 2773 __ fcmp(noreg, opr2->fpu(), op->fpu_pop_count() > 0, op->fpu_pop_count() > 1); 2774 #endif // LP64 2775 2776 } else if (opr1->is_address() && opr2->is_constant()) { 2777 LIR_Const* c = opr2->as_constant_ptr(); 2778 #ifdef _LP64 2779 if (is_reference_type(c->type())) { 2780 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "need to reverse"); 2781 __ movoop(rscratch1, c->as_jobject()); 2782 } 2783 #endif // LP64 2784 if (op->info() != nullptr) { 2785 add_debug_info_for_null_check_here(op->info()); 2786 } 2787 // special case: address - constant 2788 LIR_Address* addr = opr1->as_address_ptr(); 2789 if (c->type() == T_INT) { 2790 __ cmpl(as_Address(addr), c->as_jint()); 2791 } else if (is_reference_type(c->type())) { 2792 #ifdef _LP64 2793 // %%% Make this explode if addr isn't reachable until we figure out a 2794 // better strategy by giving noreg as the temp for as_Address 2795 __ cmpoop(rscratch1, as_Address(addr, noreg)); 2796 #else 2797 __ cmpoop(as_Address(addr), c->as_jobject()); 2798 #endif // _LP64 2799 } else { 2800 ShouldNotReachHere(); 2801 } 2802 2803 } else { 2804 ShouldNotReachHere(); 2805 } 2806 } 2807 2808 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op) { 2809 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) { 2810 if (left->is_single_xmm()) { 2811 assert(right->is_single_xmm(), "must match"); 2812 __ cmpss2int(left->as_xmm_float_reg(), right->as_xmm_float_reg(), dst->as_register(), code == lir_ucmp_fd2i); 2813 } else if (left->is_double_xmm()) { 2814 assert(right->is_double_xmm(), "must match"); 2815 __ cmpsd2int(left->as_xmm_double_reg(), right->as_xmm_double_reg(), dst->as_register(), code == lir_ucmp_fd2i); 2816 2817 } else { 2818 #ifdef _LP64 2819 ShouldNotReachHere(); 2820 #else 2821 assert(left->is_single_fpu() || left->is_double_fpu(), "must be"); 2822 assert(right->is_single_fpu() || right->is_double_fpu(), "must match"); 2823 2824 assert(left->fpu() == 0, "left must be on TOS"); 2825 __ fcmp2int(dst->as_register(), code == lir_ucmp_fd2i, right->fpu(), 2826 op->fpu_pop_count() > 0, op->fpu_pop_count() > 1); 2827 #endif // LP64 2828 } 2829 } else { 2830 assert(code == lir_cmp_l2i, "check"); 2831 #ifdef _LP64 2832 Label done; 2833 Register dest = dst->as_register(); 2834 __ cmpptr(left->as_register_lo(), right->as_register_lo()); 2835 __ movl(dest, -1); 2836 __ jccb(Assembler::less, done); 2837 __ setb(Assembler::notZero, dest); 2838 __ movzbl(dest, dest); 2839 __ bind(done); 2840 #else 2841 __ lcmp2int(left->as_register_hi(), 2842 left->as_register_lo(), 2843 right->as_register_hi(), 2844 right->as_register_lo()); 2845 move_regs(left->as_register_hi(), dst->as_register()); 2846 #endif // _LP64 2847 } 2848 } 2849 2850 2851 void LIR_Assembler::align_call(LIR_Code code) { 2852 // make sure that the displacement word of the call ends up word aligned 2853 int offset = __ offset(); 2854 switch (code) { 2855 case lir_static_call: 2856 case lir_optvirtual_call: 2857 case lir_dynamic_call: 2858 offset += NativeCall::displacement_offset; 2859 break; 2860 case lir_icvirtual_call: 2861 offset += NativeCall::displacement_offset + NativeMovConstReg::instruction_size; 2862 break; 2863 default: ShouldNotReachHere(); 2864 } 2865 __ align(BytesPerWord, offset); 2866 } 2867 2868 2869 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) { 2870 assert((__ offset() + NativeCall::displacement_offset) % BytesPerWord == 0, 2871 "must be aligned"); 2872 __ call(AddressLiteral(op->addr(), rtype)); 2873 add_call_info(code_offset(), op->info()); 2874 __ post_call_nop(); 2875 } 2876 2877 2878 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) { 2879 __ ic_call(op->addr()); 2880 add_call_info(code_offset(), op->info()); 2881 assert((__ offset() - NativeCall::instruction_size + NativeCall::displacement_offset) % BytesPerWord == 0, 2882 "must be aligned"); 2883 __ post_call_nop(); 2884 } 2885 2886 2887 void LIR_Assembler::emit_static_call_stub() { 2888 address call_pc = __ pc(); 2889 address stub = __ start_a_stub(call_stub_size()); 2890 if (stub == nullptr) { 2891 bailout("static call stub overflow"); 2892 return; 2893 } 2894 2895 int start = __ offset(); 2896 2897 // make sure that the displacement word of the call ends up word aligned 2898 __ align(BytesPerWord, __ offset() + NativeMovConstReg::instruction_size + NativeCall::displacement_offset); 2899 __ relocate(static_stub_Relocation::spec(call_pc)); 2900 __ mov_metadata(rbx, (Metadata*)nullptr); 2901 // must be set to -1 at code generation time 2902 assert(((__ offset() + 1) % BytesPerWord) == 0, "must be aligned"); 2903 // On 64bit this will die since it will take a movq & jmp, must be only a jmp 2904 __ jump(RuntimeAddress(__ pc())); 2905 2906 assert(__ offset() - start <= call_stub_size(), "stub too big"); 2907 __ end_a_stub(); 2908 } 2909 2910 2911 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) { 2912 assert(exceptionOop->as_register() == rax, "must match"); 2913 assert(exceptionPC->as_register() == rdx, "must match"); 2914 2915 // exception object is not added to oop map by LinearScan 2916 // (LinearScan assumes that no oops are in fixed registers) 2917 info->add_register_oop(exceptionOop); 2918 Runtime1::StubID unwind_id; 2919 2920 // get current pc information 2921 // pc is only needed if the method has an exception handler, the unwind code does not need it. 2922 int pc_for_athrow_offset = __ offset(); 2923 InternalAddress pc_for_athrow(__ pc()); 2924 __ lea(exceptionPC->as_register(), pc_for_athrow); 2925 add_call_info(pc_for_athrow_offset, info); // for exception handler 2926 2927 __ verify_not_null_oop(rax); 2928 // search an exception handler (rax: exception oop, rdx: throwing pc) 2929 if (compilation()->has_fpu_code()) { 2930 unwind_id = Runtime1::handle_exception_id; 2931 } else { 2932 unwind_id = Runtime1::handle_exception_nofpu_id; 2933 } 2934 __ call(RuntimeAddress(Runtime1::entry_for(unwind_id))); 2935 2936 // enough room for two byte trap 2937 __ nop(); 2938 } 2939 2940 2941 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) { 2942 assert(exceptionOop->as_register() == rax, "must match"); 2943 2944 __ jmp(_unwind_handler_entry); 2945 } 2946 2947 2948 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) { 2949 2950 // optimized version for linear scan: 2951 // * count must be already in ECX (guaranteed by LinearScan) 2952 // * left and dest must be equal 2953 // * tmp must be unused 2954 assert(count->as_register() == SHIFT_count, "count must be in ECX"); 2955 assert(left == dest, "left and dest must be equal"); 2956 assert(tmp->is_illegal(), "wasting a register if tmp is allocated"); 2957 2958 if (left->is_single_cpu()) { 2959 Register value = left->as_register(); 2960 assert(value != SHIFT_count, "left cannot be ECX"); 2961 2962 switch (code) { 2963 case lir_shl: __ shll(value); break; 2964 case lir_shr: __ sarl(value); break; 2965 case lir_ushr: __ shrl(value); break; 2966 default: ShouldNotReachHere(); 2967 } 2968 } else if (left->is_double_cpu()) { 2969 Register lo = left->as_register_lo(); 2970 Register hi = left->as_register_hi(); 2971 assert(lo != SHIFT_count && hi != SHIFT_count, "left cannot be ECX"); 2972 #ifdef _LP64 2973 switch (code) { 2974 case lir_shl: __ shlptr(lo); break; 2975 case lir_shr: __ sarptr(lo); break; 2976 case lir_ushr: __ shrptr(lo); break; 2977 default: ShouldNotReachHere(); 2978 } 2979 #else 2980 2981 switch (code) { 2982 case lir_shl: __ lshl(hi, lo); break; 2983 case lir_shr: __ lshr(hi, lo, true); break; 2984 case lir_ushr: __ lshr(hi, lo, false); break; 2985 default: ShouldNotReachHere(); 2986 } 2987 #endif // LP64 2988 } else { 2989 ShouldNotReachHere(); 2990 } 2991 } 2992 2993 2994 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) { 2995 if (dest->is_single_cpu()) { 2996 // first move left into dest so that left is not destroyed by the shift 2997 Register value = dest->as_register(); 2998 count = count & 0x1F; // Java spec 2999 3000 move_regs(left->as_register(), value); 3001 switch (code) { 3002 case lir_shl: __ shll(value, count); break; 3003 case lir_shr: __ sarl(value, count); break; 3004 case lir_ushr: __ shrl(value, count); break; 3005 default: ShouldNotReachHere(); 3006 } 3007 } else if (dest->is_double_cpu()) { 3008 #ifndef _LP64 3009 Unimplemented(); 3010 #else 3011 // first move left into dest so that left is not destroyed by the shift 3012 Register value = dest->as_register_lo(); 3013 count = count & 0x1F; // Java spec 3014 3015 move_regs(left->as_register_lo(), value); 3016 switch (code) { 3017 case lir_shl: __ shlptr(value, count); break; 3018 case lir_shr: __ sarptr(value, count); break; 3019 case lir_ushr: __ shrptr(value, count); break; 3020 default: ShouldNotReachHere(); 3021 } 3022 #endif // _LP64 3023 } else { 3024 ShouldNotReachHere(); 3025 } 3026 } 3027 3028 3029 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) { 3030 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); 3031 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; 3032 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); 3033 __ movptr (Address(rsp, offset_from_rsp_in_bytes), r); 3034 } 3035 3036 3037 void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) { 3038 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); 3039 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; 3040 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); 3041 __ movptr (Address(rsp, offset_from_rsp_in_bytes), c); 3042 } 3043 3044 3045 void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) { 3046 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); 3047 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; 3048 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); 3049 __ movoop(Address(rsp, offset_from_rsp_in_bytes), o, rscratch1); 3050 } 3051 3052 3053 void LIR_Assembler::store_parameter(Metadata* m, int offset_from_rsp_in_words) { 3054 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); 3055 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; 3056 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); 3057 __ mov_metadata(Address(rsp, offset_from_rsp_in_bytes), m, rscratch1); 3058 } 3059 3060 3061 // This code replaces a call to arraycopy; no exception may 3062 // be thrown in this code, they must be thrown in the System.arraycopy 3063 // activation frame; we could save some checks if this would not be the case 3064 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) { 3065 ciArrayKlass* default_type = op->expected_type(); 3066 Register src = op->src()->as_register(); 3067 Register dst = op->dst()->as_register(); 3068 Register src_pos = op->src_pos()->as_register(); 3069 Register dst_pos = op->dst_pos()->as_register(); 3070 Register length = op->length()->as_register(); 3071 Register tmp = op->tmp()->as_register(); 3072 Register tmp_load_klass = LP64_ONLY(rscratch1) NOT_LP64(noreg); 3073 Register tmp2 = UseCompactObjectHeaders ? rscratch2 : noreg; 3074 3075 CodeStub* stub = op->stub(); 3076 int flags = op->flags(); 3077 BasicType basic_type = default_type != nullptr ? default_type->element_type()->basic_type() : T_ILLEGAL; 3078 if (is_reference_type(basic_type)) basic_type = T_OBJECT; 3079 3080 // if we don't know anything, just go through the generic arraycopy 3081 if (default_type == nullptr) { 3082 // save outgoing arguments on stack in case call to System.arraycopy is needed 3083 // HACK ALERT. This code used to push the parameters in a hardwired fashion 3084 // for interpreter calling conventions. Now we have to do it in new style conventions. 3085 // For the moment until C1 gets the new register allocator I just force all the 3086 // args to the right place (except the register args) and then on the back side 3087 // reload the register args properly if we go slow path. Yuck 3088 3089 // These are proper for the calling convention 3090 store_parameter(length, 2); 3091 store_parameter(dst_pos, 1); 3092 store_parameter(dst, 0); 3093 3094 // these are just temporary placements until we need to reload 3095 store_parameter(src_pos, 3); 3096 store_parameter(src, 4); 3097 NOT_LP64(assert(src == rcx && src_pos == rdx, "mismatch in calling convention");) 3098 3099 address copyfunc_addr = StubRoutines::generic_arraycopy(); 3100 assert(copyfunc_addr != nullptr, "generic arraycopy stub required"); 3101 3102 // pass arguments: may push as this is not a safepoint; SP must be fix at each safepoint 3103 #ifdef _LP64 3104 // The arguments are in java calling convention so we can trivially shift them to C 3105 // convention 3106 assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4); 3107 __ mov(c_rarg0, j_rarg0); 3108 assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4); 3109 __ mov(c_rarg1, j_rarg1); 3110 assert_different_registers(c_rarg2, j_rarg3, j_rarg4); 3111 __ mov(c_rarg2, j_rarg2); 3112 assert_different_registers(c_rarg3, j_rarg4); 3113 __ mov(c_rarg3, j_rarg3); 3114 #ifdef _WIN64 3115 // Allocate abi space for args but be sure to keep stack aligned 3116 __ subptr(rsp, 6*wordSize); 3117 store_parameter(j_rarg4, 4); 3118 #ifndef PRODUCT 3119 if (PrintC1Statistics) { 3120 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt), rscratch1); 3121 } 3122 #endif 3123 __ call(RuntimeAddress(copyfunc_addr)); 3124 __ addptr(rsp, 6*wordSize); 3125 #else 3126 __ mov(c_rarg4, j_rarg4); 3127 #ifndef PRODUCT 3128 if (PrintC1Statistics) { 3129 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt), rscratch1); 3130 } 3131 #endif 3132 __ call(RuntimeAddress(copyfunc_addr)); 3133 #endif // _WIN64 3134 #else 3135 __ push(length); 3136 __ push(dst_pos); 3137 __ push(dst); 3138 __ push(src_pos); 3139 __ push(src); 3140 3141 #ifndef PRODUCT 3142 if (PrintC1Statistics) { 3143 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt), rscratch1); 3144 } 3145 #endif 3146 __ call_VM_leaf(copyfunc_addr, 5); // removes pushed parameter from the stack 3147 3148 #endif // _LP64 3149 3150 __ cmpl(rax, 0); 3151 __ jcc(Assembler::equal, *stub->continuation()); 3152 3153 __ mov(tmp, rax); 3154 __ xorl(tmp, -1); 3155 3156 // Reload values from the stack so they are where the stub 3157 // expects them. 3158 __ movptr (dst, Address(rsp, 0*BytesPerWord)); 3159 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord)); 3160 __ movptr (length, Address(rsp, 2*BytesPerWord)); 3161 __ movptr (src_pos, Address(rsp, 3*BytesPerWord)); 3162 __ movptr (src, Address(rsp, 4*BytesPerWord)); 3163 3164 __ subl(length, tmp); 3165 __ addl(src_pos, tmp); 3166 __ addl(dst_pos, tmp); 3167 __ jmp(*stub->entry()); 3168 3169 __ bind(*stub->continuation()); 3170 return; 3171 } 3172 3173 assert(default_type != nullptr && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point"); 3174 3175 int elem_size = type2aelembytes(basic_type); 3176 Address::ScaleFactor scale; 3177 3178 switch (elem_size) { 3179 case 1 : 3180 scale = Address::times_1; 3181 break; 3182 case 2 : 3183 scale = Address::times_2; 3184 break; 3185 case 4 : 3186 scale = Address::times_4; 3187 break; 3188 case 8 : 3189 scale = Address::times_8; 3190 break; 3191 default: 3192 scale = Address::no_scale; 3193 ShouldNotReachHere(); 3194 } 3195 3196 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes()); 3197 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes()); 3198 3199 // length and pos's are all sign extended at this point on 64bit 3200 3201 // test for null 3202 if (flags & LIR_OpArrayCopy::src_null_check) { 3203 __ testptr(src, src); 3204 __ jcc(Assembler::zero, *stub->entry()); 3205 } 3206 if (flags & LIR_OpArrayCopy::dst_null_check) { 3207 __ testptr(dst, dst); 3208 __ jcc(Assembler::zero, *stub->entry()); 3209 } 3210 3211 // If the compiler was not able to prove that exact type of the source or the destination 3212 // of the arraycopy is an array type, check at runtime if the source or the destination is 3213 // an instance type. 3214 if (flags & LIR_OpArrayCopy::type_check) { 3215 if (!(flags & LIR_OpArrayCopy::dst_objarray)) { 3216 __ load_klass(tmp, dst, tmp_load_klass); 3217 __ cmpl(Address(tmp, in_bytes(Klass::layout_helper_offset())), Klass::_lh_neutral_value); 3218 __ jcc(Assembler::greaterEqual, *stub->entry()); 3219 } 3220 3221 if (!(flags & LIR_OpArrayCopy::src_objarray)) { 3222 __ load_klass(tmp, src, tmp_load_klass); 3223 __ cmpl(Address(tmp, in_bytes(Klass::layout_helper_offset())), Klass::_lh_neutral_value); 3224 __ jcc(Assembler::greaterEqual, *stub->entry()); 3225 } 3226 } 3227 3228 // check if negative 3229 if (flags & LIR_OpArrayCopy::src_pos_positive_check) { 3230 __ testl(src_pos, src_pos); 3231 __ jcc(Assembler::less, *stub->entry()); 3232 } 3233 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) { 3234 __ testl(dst_pos, dst_pos); 3235 __ jcc(Assembler::less, *stub->entry()); 3236 } 3237 3238 if (flags & LIR_OpArrayCopy::src_range_check) { 3239 __ lea(tmp, Address(src_pos, length, Address::times_1, 0)); 3240 __ cmpl(tmp, src_length_addr); 3241 __ jcc(Assembler::above, *stub->entry()); 3242 } 3243 if (flags & LIR_OpArrayCopy::dst_range_check) { 3244 __ lea(tmp, Address(dst_pos, length, Address::times_1, 0)); 3245 __ cmpl(tmp, dst_length_addr); 3246 __ jcc(Assembler::above, *stub->entry()); 3247 } 3248 3249 if (flags & LIR_OpArrayCopy::length_positive_check) { 3250 __ testl(length, length); 3251 __ jcc(Assembler::less, *stub->entry()); 3252 } 3253 3254 #ifdef _LP64 3255 __ movl2ptr(src_pos, src_pos); //higher 32bits must be null 3256 __ movl2ptr(dst_pos, dst_pos); //higher 32bits must be null 3257 #endif 3258 3259 if (flags & LIR_OpArrayCopy::type_check) { 3260 // We don't know the array types are compatible 3261 if (basic_type != T_OBJECT) { 3262 // Simple test for basic type arrays 3263 __ cmp_klass(src, dst, tmp, tmp2); 3264 __ jcc(Assembler::notEqual, *stub->entry()); 3265 } else { 3266 // For object arrays, if src is a sub class of dst then we can 3267 // safely do the copy. 3268 Label cont, slow; 3269 3270 __ push(src); 3271 __ push(dst); 3272 3273 __ load_klass(src, src, tmp_load_klass); 3274 __ load_klass(dst, dst, tmp_load_klass); 3275 3276 __ check_klass_subtype_fast_path(src, dst, tmp, &cont, &slow, nullptr); 3277 3278 __ push(src); 3279 __ push(dst); 3280 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); 3281 __ pop(dst); 3282 __ pop(src); 3283 3284 __ cmpl(src, 0); 3285 __ jcc(Assembler::notEqual, cont); 3286 3287 __ bind(slow); 3288 __ pop(dst); 3289 __ pop(src); 3290 3291 address copyfunc_addr = StubRoutines::checkcast_arraycopy(); 3292 if (copyfunc_addr != nullptr) { // use stub if available 3293 // src is not a sub class of dst so we have to do a 3294 // per-element check. 3295 3296 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray; 3297 if ((flags & mask) != mask) { 3298 // Check that at least both of them object arrays. 3299 assert(flags & mask, "one of the two should be known to be an object array"); 3300 3301 if (!(flags & LIR_OpArrayCopy::src_objarray)) { 3302 __ load_klass(tmp, src, tmp_load_klass); 3303 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) { 3304 __ load_klass(tmp, dst, tmp_load_klass); 3305 } 3306 int lh_offset = in_bytes(Klass::layout_helper_offset()); 3307 Address klass_lh_addr(tmp, lh_offset); 3308 jint objArray_lh = Klass::array_layout_helper(T_OBJECT); 3309 __ cmpl(klass_lh_addr, objArray_lh); 3310 __ jcc(Assembler::notEqual, *stub->entry()); 3311 } 3312 3313 // Spill because stubs can use any register they like and it's 3314 // easier to restore just those that we care about. 3315 store_parameter(dst, 0); 3316 store_parameter(dst_pos, 1); 3317 store_parameter(length, 2); 3318 store_parameter(src_pos, 3); 3319 store_parameter(src, 4); 3320 3321 #ifndef _LP64 3322 Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes()); 3323 __ movptr(tmp, dst_klass_addr); 3324 __ movptr(tmp, Address(tmp, ObjArrayKlass::element_klass_offset())); 3325 __ push(tmp); 3326 __ movl(tmp, Address(tmp, Klass::super_check_offset_offset())); 3327 __ push(tmp); 3328 __ push(length); 3329 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3330 __ push(tmp); 3331 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3332 __ push(tmp); 3333 3334 __ call_VM_leaf(copyfunc_addr, 5); 3335 #else 3336 __ movl2ptr(length, length); //higher 32bits must be null 3337 3338 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3339 assert_different_registers(c_rarg0, dst, dst_pos, length); 3340 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3341 assert_different_registers(c_rarg1, dst, length); 3342 3343 __ mov(c_rarg2, length); 3344 assert_different_registers(c_rarg2, dst); 3345 3346 #ifdef _WIN64 3347 // Allocate abi space for args but be sure to keep stack aligned 3348 __ subptr(rsp, 6*wordSize); 3349 __ load_klass(c_rarg3, dst, tmp_load_klass); 3350 __ movptr(c_rarg3, Address(c_rarg3, ObjArrayKlass::element_klass_offset())); 3351 store_parameter(c_rarg3, 4); 3352 __ movl(c_rarg3, Address(c_rarg3, Klass::super_check_offset_offset())); 3353 __ call(RuntimeAddress(copyfunc_addr)); 3354 __ addptr(rsp, 6*wordSize); 3355 #else 3356 __ load_klass(c_rarg4, dst, tmp_load_klass); 3357 __ movptr(c_rarg4, Address(c_rarg4, ObjArrayKlass::element_klass_offset())); 3358 __ movl(c_rarg3, Address(c_rarg4, Klass::super_check_offset_offset())); 3359 __ call(RuntimeAddress(copyfunc_addr)); 3360 #endif 3361 3362 #endif 3363 3364 #ifndef PRODUCT 3365 if (PrintC1Statistics) { 3366 Label failed; 3367 __ testl(rax, rax); 3368 __ jcc(Assembler::notZero, failed); 3369 __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt), rscratch1); 3370 __ bind(failed); 3371 } 3372 #endif 3373 3374 __ testl(rax, rax); 3375 __ jcc(Assembler::zero, *stub->continuation()); 3376 3377 #ifndef PRODUCT 3378 if (PrintC1Statistics) { 3379 __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt), rscratch1); 3380 } 3381 #endif 3382 3383 __ mov(tmp, rax); 3384 3385 __ xorl(tmp, -1); 3386 3387 // Restore previously spilled arguments 3388 __ movptr (dst, Address(rsp, 0*BytesPerWord)); 3389 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord)); 3390 __ movptr (length, Address(rsp, 2*BytesPerWord)); 3391 __ movptr (src_pos, Address(rsp, 3*BytesPerWord)); 3392 __ movptr (src, Address(rsp, 4*BytesPerWord)); 3393 3394 3395 __ subl(length, tmp); 3396 __ addl(src_pos, tmp); 3397 __ addl(dst_pos, tmp); 3398 } 3399 3400 __ jmp(*stub->entry()); 3401 3402 __ bind(cont); 3403 __ pop(dst); 3404 __ pop(src); 3405 } 3406 } 3407 3408 #ifdef ASSERT 3409 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) { 3410 // Sanity check the known type with the incoming class. For the 3411 // primitive case the types must match exactly with src.klass and 3412 // dst.klass each exactly matching the default type. For the 3413 // object array case, if no type check is needed then either the 3414 // dst type is exactly the expected type and the src type is a 3415 // subtype which we can't check or src is the same array as dst 3416 // but not necessarily exactly of type default_type. 3417 Label known_ok, halt; 3418 __ mov_metadata(tmp, default_type->constant_encoding()); 3419 #ifdef _LP64 3420 if (UseCompressedClassPointers) { 3421 __ encode_klass_not_null(tmp, rscratch1); 3422 } 3423 #endif 3424 3425 if (basic_type != T_OBJECT) { 3426 __ cmp_klass(tmp, dst, tmp2); 3427 __ jcc(Assembler::notEqual, halt); 3428 __ cmp_klass(tmp, src, tmp2); 3429 __ jcc(Assembler::equal, known_ok); 3430 } else { 3431 __ cmp_klass(tmp, dst, tmp2); 3432 __ jcc(Assembler::equal, known_ok); 3433 __ cmpptr(src, dst); 3434 __ jcc(Assembler::equal, known_ok); 3435 } 3436 __ bind(halt); 3437 __ stop("incorrect type information in arraycopy"); 3438 __ bind(known_ok); 3439 } 3440 #endif 3441 3442 #ifndef PRODUCT 3443 if (PrintC1Statistics) { 3444 __ incrementl(ExternalAddress(Runtime1::arraycopy_count_address(basic_type)), rscratch1); 3445 } 3446 #endif 3447 3448 #ifdef _LP64 3449 assert_different_registers(c_rarg0, dst, dst_pos, length); 3450 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3451 assert_different_registers(c_rarg1, length); 3452 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3453 __ mov(c_rarg2, length); 3454 3455 #else 3456 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3457 store_parameter(tmp, 0); 3458 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3459 store_parameter(tmp, 1); 3460 store_parameter(length, 2); 3461 #endif // _LP64 3462 3463 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0; 3464 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0; 3465 const char *name; 3466 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false); 3467 __ call_VM_leaf(entry, 0); 3468 3469 __ bind(*stub->continuation()); 3470 } 3471 3472 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) { 3473 assert(op->crc()->is_single_cpu(), "crc must be register"); 3474 assert(op->val()->is_single_cpu(), "byte value must be register"); 3475 assert(op->result_opr()->is_single_cpu(), "result must be register"); 3476 Register crc = op->crc()->as_register(); 3477 Register val = op->val()->as_register(); 3478 Register res = op->result_opr()->as_register(); 3479 3480 assert_different_registers(val, crc, res); 3481 3482 __ lea(res, ExternalAddress(StubRoutines::crc_table_addr())); 3483 __ notl(crc); // ~crc 3484 __ update_byte_crc32(crc, val, res); 3485 __ notl(crc); // ~crc 3486 __ mov(res, crc); 3487 } 3488 3489 void LIR_Assembler::emit_lock(LIR_OpLock* op) { 3490 Register obj = op->obj_opr()->as_register(); // may not be an oop 3491 Register hdr = op->hdr_opr()->as_register(); 3492 Register lock = op->lock_opr()->as_register(); 3493 if (LockingMode == LM_MONITOR) { 3494 if (op->info() != nullptr) { 3495 add_debug_info_for_null_check_here(op->info()); 3496 __ null_check(obj); 3497 } 3498 __ jmp(*op->stub()->entry()); 3499 } else if (op->code() == lir_lock) { 3500 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); 3501 Register tmp = LockingMode == LM_LIGHTWEIGHT ? op->scratch_opr()->as_register() : noreg; 3502 // add debug info for NullPointerException only if one is possible 3503 int null_check_offset = __ lock_object(hdr, obj, lock, tmp, *op->stub()->entry()); 3504 if (op->info() != nullptr) { 3505 add_debug_info_for_null_check(null_check_offset, op->info()); 3506 } 3507 // done 3508 } else if (op->code() == lir_unlock) { 3509 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); 3510 __ unlock_object(hdr, obj, lock, *op->stub()->entry()); 3511 } else { 3512 Unimplemented(); 3513 } 3514 __ bind(*op->stub()->continuation()); 3515 } 3516 3517 void LIR_Assembler::emit_load_klass(LIR_OpLoadKlass* op) { 3518 Register obj = op->obj()->as_pointer_register(); 3519 Register result = op->result_opr()->as_pointer_register(); 3520 3521 CodeEmitInfo* info = op->info(); 3522 if (info != nullptr) { 3523 add_debug_info_for_null_check_here(info); 3524 } 3525 3526 #ifdef _LP64 3527 if (UseCompactObjectHeaders) { 3528 Register tmp = rscratch1; 3529 assert_different_registers(tmp, obj); 3530 assert_different_registers(tmp, result); 3531 3532 // Check if we can take the (common) fast path, if obj is unlocked. 3533 __ movq(result, Address(obj, oopDesc::mark_offset_in_bytes())); 3534 __ testb(result, markWord::monitor_value); 3535 __ jcc(Assembler::notZero, *op->stub()->entry()); 3536 __ bind(*op->stub()->continuation()); 3537 // Fast-path: shift and decode Klass*. 3538 __ shrq(result, markWord::klass_shift); 3539 __ decode_klass_not_null(result, tmp); 3540 } else if (UseCompressedClassPointers) { 3541 __ movl(result, Address(obj, oopDesc::klass_offset_in_bytes())); 3542 __ decode_klass_not_null(result, rscratch1); 3543 } else 3544 #endif 3545 { 3546 __ movptr(result, Address(obj, oopDesc::klass_offset_in_bytes())); 3547 } 3548 } 3549 3550 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) { 3551 ciMethod* method = op->profiled_method(); 3552 int bci = op->profiled_bci(); 3553 ciMethod* callee = op->profiled_callee(); 3554 Register tmp_load_klass = LP64_ONLY(rscratch1) NOT_LP64(noreg); 3555 3556 // Update counter for all call types 3557 ciMethodData* md = method->method_data_or_null(); 3558 assert(md != nullptr, "Sanity"); 3559 ciProfileData* data = md->bci_to_data(bci); 3560 assert(data != nullptr && data->is_CounterData(), "need CounterData for calls"); 3561 assert(op->mdo()->is_single_cpu(), "mdo must be allocated"); 3562 Register mdo = op->mdo()->as_register(); 3563 __ mov_metadata(mdo, md->constant_encoding()); 3564 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset())); 3565 // Perform additional virtual call profiling for invokevirtual and 3566 // invokeinterface bytecodes 3567 if (op->should_profile_receiver_type()) { 3568 assert(op->recv()->is_single_cpu(), "recv must be allocated"); 3569 Register recv = op->recv()->as_register(); 3570 assert_different_registers(mdo, recv); 3571 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls"); 3572 ciKlass* known_klass = op->known_holder(); 3573 if (C1OptimizeVirtualCallProfiling && known_klass != nullptr) { 3574 // We know the type that will be seen at this call site; we can 3575 // statically update the MethodData* rather than needing to do 3576 // dynamic tests on the receiver type 3577 3578 // NOTE: we should probably put a lock around this search to 3579 // avoid collisions by concurrent compilations 3580 ciVirtualCallData* vc_data = (ciVirtualCallData*) data; 3581 uint i; 3582 for (i = 0; i < VirtualCallData::row_limit(); i++) { 3583 ciKlass* receiver = vc_data->receiver(i); 3584 if (known_klass->equals(receiver)) { 3585 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i))); 3586 __ addptr(data_addr, DataLayout::counter_increment); 3587 return; 3588 } 3589 } 3590 3591 // Receiver type not found in profile data; select an empty slot 3592 3593 // Note that this is less efficient than it should be because it 3594 // always does a write to the receiver part of the 3595 // VirtualCallData rather than just the first time 3596 for (i = 0; i < VirtualCallData::row_limit(); i++) { 3597 ciKlass* receiver = vc_data->receiver(i); 3598 if (receiver == nullptr) { 3599 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i))); 3600 __ mov_metadata(recv_addr, known_klass->constant_encoding(), rscratch1); 3601 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i))); 3602 __ addptr(data_addr, DataLayout::counter_increment); 3603 return; 3604 } 3605 } 3606 } else { 3607 __ load_klass(recv, recv, tmp_load_klass); 3608 Label update_done; 3609 type_profile_helper(mdo, md, data, recv, &update_done); 3610 // Receiver did not match any saved receiver and there is no empty row for it. 3611 // Increment total counter to indicate polymorphic case. 3612 __ addptr(counter_addr, DataLayout::counter_increment); 3613 3614 __ bind(update_done); 3615 } 3616 } else { 3617 // Static call 3618 __ addptr(counter_addr, DataLayout::counter_increment); 3619 } 3620 } 3621 3622 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) { 3623 Register obj = op->obj()->as_register(); 3624 Register tmp = op->tmp()->as_pointer_register(); 3625 Register tmp_load_klass = LP64_ONLY(rscratch1) NOT_LP64(noreg); 3626 Address mdo_addr = as_Address(op->mdp()->as_address_ptr()); 3627 ciKlass* exact_klass = op->exact_klass(); 3628 intptr_t current_klass = op->current_klass(); 3629 bool not_null = op->not_null(); 3630 bool no_conflict = op->no_conflict(); 3631 3632 Label update, next, none; 3633 3634 bool do_null = !not_null; 3635 bool exact_klass_set = exact_klass != nullptr && ciTypeEntries::valid_ciklass(current_klass) == exact_klass; 3636 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set; 3637 3638 assert(do_null || do_update, "why are we here?"); 3639 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?"); 3640 3641 __ verify_oop(obj); 3642 3643 if (tmp != obj) { 3644 __ mov(tmp, obj); 3645 } 3646 if (do_null) { 3647 __ testptr(tmp, tmp); 3648 __ jccb(Assembler::notZero, update); 3649 if (!TypeEntries::was_null_seen(current_klass)) { 3650 __ orptr(mdo_addr, TypeEntries::null_seen); 3651 } 3652 if (do_update) { 3653 #ifndef ASSERT 3654 __ jmpb(next); 3655 } 3656 #else 3657 __ jmp(next); 3658 } 3659 } else { 3660 __ testptr(tmp, tmp); 3661 __ jcc(Assembler::notZero, update); 3662 __ stop("unexpected null obj"); 3663 #endif 3664 } 3665 3666 __ bind(update); 3667 3668 if (do_update) { 3669 #ifdef ASSERT 3670 if (exact_klass != nullptr) { 3671 Label ok; 3672 __ load_klass(tmp, tmp, tmp_load_klass); 3673 __ push(tmp); 3674 __ mov_metadata(tmp, exact_klass->constant_encoding()); 3675 __ cmpptr(tmp, Address(rsp, 0)); 3676 __ jcc(Assembler::equal, ok); 3677 __ stop("exact klass and actual klass differ"); 3678 __ bind(ok); 3679 __ pop(tmp); 3680 } 3681 #endif 3682 if (!no_conflict) { 3683 if (exact_klass == nullptr || TypeEntries::is_type_none(current_klass)) { 3684 if (exact_klass != nullptr) { 3685 __ mov_metadata(tmp, exact_klass->constant_encoding()); 3686 } else { 3687 __ load_klass(tmp, tmp, tmp_load_klass); 3688 } 3689 3690 __ xorptr(tmp, mdo_addr); 3691 __ testptr(tmp, TypeEntries::type_klass_mask); 3692 // klass seen before, nothing to do. The unknown bit may have been 3693 // set already but no need to check. 3694 __ jccb(Assembler::zero, next); 3695 3696 __ testptr(tmp, TypeEntries::type_unknown); 3697 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore. 3698 3699 if (TypeEntries::is_type_none(current_klass)) { 3700 __ cmpptr(mdo_addr, 0); 3701 __ jccb(Assembler::equal, none); 3702 __ cmpptr(mdo_addr, TypeEntries::null_seen); 3703 __ jccb(Assembler::equal, none); 3704 // There is a chance that the checks above (re-reading profiling 3705 // data from memory) fail if another thread has just set the 3706 // profiling to this obj's klass 3707 __ xorptr(tmp, mdo_addr); 3708 __ testptr(tmp, TypeEntries::type_klass_mask); 3709 __ jccb(Assembler::zero, next); 3710 } 3711 } else { 3712 assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr && 3713 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only"); 3714 3715 __ movptr(tmp, mdo_addr); 3716 __ testptr(tmp, TypeEntries::type_unknown); 3717 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore. 3718 } 3719 3720 // different than before. Cannot keep accurate profile. 3721 __ orptr(mdo_addr, TypeEntries::type_unknown); 3722 3723 if (TypeEntries::is_type_none(current_klass)) { 3724 __ jmpb(next); 3725 3726 __ bind(none); 3727 // first time here. Set profile type. 3728 __ movptr(mdo_addr, tmp); 3729 } 3730 } else { 3731 // There's a single possible klass at this profile point 3732 assert(exact_klass != nullptr, "should be"); 3733 if (TypeEntries::is_type_none(current_klass)) { 3734 __ mov_metadata(tmp, exact_klass->constant_encoding()); 3735 __ xorptr(tmp, mdo_addr); 3736 __ testptr(tmp, TypeEntries::type_klass_mask); 3737 #ifdef ASSERT 3738 __ jcc(Assembler::zero, next); 3739 3740 { 3741 Label ok; 3742 __ push(tmp); 3743 __ cmpptr(mdo_addr, 0); 3744 __ jcc(Assembler::equal, ok); 3745 __ cmpptr(mdo_addr, TypeEntries::null_seen); 3746 __ jcc(Assembler::equal, ok); 3747 // may have been set by another thread 3748 __ mov_metadata(tmp, exact_klass->constant_encoding()); 3749 __ xorptr(tmp, mdo_addr); 3750 __ testptr(tmp, TypeEntries::type_mask); 3751 __ jcc(Assembler::zero, ok); 3752 3753 __ stop("unexpected profiling mismatch"); 3754 __ bind(ok); 3755 __ pop(tmp); 3756 } 3757 #else 3758 __ jccb(Assembler::zero, next); 3759 #endif 3760 // first time here. Set profile type. 3761 __ movptr(mdo_addr, tmp); 3762 } else { 3763 assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr && 3764 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent"); 3765 3766 __ movptr(tmp, mdo_addr); 3767 __ testptr(tmp, TypeEntries::type_unknown); 3768 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore. 3769 3770 __ orptr(mdo_addr, TypeEntries::type_unknown); 3771 } 3772 } 3773 3774 __ bind(next); 3775 } 3776 } 3777 3778 void LIR_Assembler::emit_delay(LIR_OpDelay*) { 3779 Unimplemented(); 3780 } 3781 3782 3783 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) { 3784 __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no)); 3785 } 3786 3787 3788 void LIR_Assembler::align_backward_branch_target() { 3789 __ align(BytesPerWord); 3790 } 3791 3792 3793 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) { 3794 if (left->is_single_cpu()) { 3795 __ negl(left->as_register()); 3796 move_regs(left->as_register(), dest->as_register()); 3797 3798 } else if (left->is_double_cpu()) { 3799 Register lo = left->as_register_lo(); 3800 #ifdef _LP64 3801 Register dst = dest->as_register_lo(); 3802 __ movptr(dst, lo); 3803 __ negptr(dst); 3804 #else 3805 Register hi = left->as_register_hi(); 3806 __ lneg(hi, lo); 3807 if (dest->as_register_lo() == hi) { 3808 assert(dest->as_register_hi() != lo, "destroying register"); 3809 move_regs(hi, dest->as_register_hi()); 3810 move_regs(lo, dest->as_register_lo()); 3811 } else { 3812 move_regs(lo, dest->as_register_lo()); 3813 move_regs(hi, dest->as_register_hi()); 3814 } 3815 #endif // _LP64 3816 3817 } else if (dest->is_single_xmm()) { 3818 #ifdef _LP64 3819 if (UseAVX > 2 && !VM_Version::supports_avx512vl()) { 3820 assert(tmp->is_valid(), "need temporary"); 3821 assert_different_registers(left->as_xmm_float_reg(), tmp->as_xmm_float_reg()); 3822 __ vpxor(dest->as_xmm_float_reg(), tmp->as_xmm_float_reg(), left->as_xmm_float_reg(), 2); 3823 } 3824 else 3825 #endif 3826 { 3827 assert(!tmp->is_valid(), "do not need temporary"); 3828 if (left->as_xmm_float_reg() != dest->as_xmm_float_reg()) { 3829 __ movflt(dest->as_xmm_float_reg(), left->as_xmm_float_reg()); 3830 } 3831 __ xorps(dest->as_xmm_float_reg(), 3832 ExternalAddress((address)float_signflip_pool), 3833 rscratch1); 3834 } 3835 } else if (dest->is_double_xmm()) { 3836 #ifdef _LP64 3837 if (UseAVX > 2 && !VM_Version::supports_avx512vl()) { 3838 assert(tmp->is_valid(), "need temporary"); 3839 assert_different_registers(left->as_xmm_double_reg(), tmp->as_xmm_double_reg()); 3840 __ vpxor(dest->as_xmm_double_reg(), tmp->as_xmm_double_reg(), left->as_xmm_double_reg(), 2); 3841 } 3842 else 3843 #endif 3844 { 3845 assert(!tmp->is_valid(), "do not need temporary"); 3846 if (left->as_xmm_double_reg() != dest->as_xmm_double_reg()) { 3847 __ movdbl(dest->as_xmm_double_reg(), left->as_xmm_double_reg()); 3848 } 3849 __ xorpd(dest->as_xmm_double_reg(), 3850 ExternalAddress((address)double_signflip_pool), 3851 rscratch1); 3852 } 3853 #ifndef _LP64 3854 } else if (left->is_single_fpu() || left->is_double_fpu()) { 3855 assert(left->fpu() == 0, "arg must be on TOS"); 3856 assert(dest->fpu() == 0, "dest must be TOS"); 3857 __ fchs(); 3858 #endif // !_LP64 3859 3860 } else { 3861 ShouldNotReachHere(); 3862 } 3863 } 3864 3865 3866 void LIR_Assembler::leal(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) { 3867 assert(src->is_address(), "must be an address"); 3868 assert(dest->is_register(), "must be a register"); 3869 3870 PatchingStub* patch = nullptr; 3871 if (patch_code != lir_patch_none) { 3872 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 3873 } 3874 3875 Register reg = dest->as_pointer_register(); 3876 LIR_Address* addr = src->as_address_ptr(); 3877 __ lea(reg, as_Address(addr)); 3878 3879 if (patch != nullptr) { 3880 patching_epilog(patch, patch_code, addr->base()->as_register(), info); 3881 } 3882 } 3883 3884 3885 3886 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) { 3887 assert(!tmp->is_valid(), "don't need temporary"); 3888 __ call(RuntimeAddress(dest)); 3889 if (info != nullptr) { 3890 add_call_info_here(info); 3891 } 3892 __ post_call_nop(); 3893 } 3894 3895 3896 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) { 3897 assert(type == T_LONG, "only for volatile long fields"); 3898 3899 if (info != nullptr) { 3900 add_debug_info_for_null_check_here(info); 3901 } 3902 3903 if (src->is_double_xmm()) { 3904 if (dest->is_double_cpu()) { 3905 #ifdef _LP64 3906 __ movdq(dest->as_register_lo(), src->as_xmm_double_reg()); 3907 #else 3908 __ movdl(dest->as_register_lo(), src->as_xmm_double_reg()); 3909 __ psrlq(src->as_xmm_double_reg(), 32); 3910 __ movdl(dest->as_register_hi(), src->as_xmm_double_reg()); 3911 #endif // _LP64 3912 } else if (dest->is_double_stack()) { 3913 __ movdbl(frame_map()->address_for_slot(dest->double_stack_ix()), src->as_xmm_double_reg()); 3914 } else if (dest->is_address()) { 3915 __ movdbl(as_Address(dest->as_address_ptr()), src->as_xmm_double_reg()); 3916 } else { 3917 ShouldNotReachHere(); 3918 } 3919 3920 } else if (dest->is_double_xmm()) { 3921 if (src->is_double_stack()) { 3922 __ movdbl(dest->as_xmm_double_reg(), frame_map()->address_for_slot(src->double_stack_ix())); 3923 } else if (src->is_address()) { 3924 __ movdbl(dest->as_xmm_double_reg(), as_Address(src->as_address_ptr())); 3925 } else { 3926 ShouldNotReachHere(); 3927 } 3928 3929 #ifndef _LP64 3930 } else if (src->is_double_fpu()) { 3931 assert(src->fpu_regnrLo() == 0, "must be TOS"); 3932 if (dest->is_double_stack()) { 3933 __ fistp_d(frame_map()->address_for_slot(dest->double_stack_ix())); 3934 } else if (dest->is_address()) { 3935 __ fistp_d(as_Address(dest->as_address_ptr())); 3936 } else { 3937 ShouldNotReachHere(); 3938 } 3939 3940 } else if (dest->is_double_fpu()) { 3941 assert(dest->fpu_regnrLo() == 0, "must be TOS"); 3942 if (src->is_double_stack()) { 3943 __ fild_d(frame_map()->address_for_slot(src->double_stack_ix())); 3944 } else if (src->is_address()) { 3945 __ fild_d(as_Address(src->as_address_ptr())); 3946 } else { 3947 ShouldNotReachHere(); 3948 } 3949 #endif // !_LP64 3950 3951 } else { 3952 ShouldNotReachHere(); 3953 } 3954 } 3955 3956 #ifdef ASSERT 3957 // emit run-time assertion 3958 void LIR_Assembler::emit_assert(LIR_OpAssert* op) { 3959 assert(op->code() == lir_assert, "must be"); 3960 3961 if (op->in_opr1()->is_valid()) { 3962 assert(op->in_opr2()->is_valid(), "both operands must be valid"); 3963 comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op); 3964 } else { 3965 assert(op->in_opr2()->is_illegal(), "both operands must be illegal"); 3966 assert(op->condition() == lir_cond_always, "no other conditions allowed"); 3967 } 3968 3969 Label ok; 3970 if (op->condition() != lir_cond_always) { 3971 Assembler::Condition acond = Assembler::zero; 3972 switch (op->condition()) { 3973 case lir_cond_equal: acond = Assembler::equal; break; 3974 case lir_cond_notEqual: acond = Assembler::notEqual; break; 3975 case lir_cond_less: acond = Assembler::less; break; 3976 case lir_cond_lessEqual: acond = Assembler::lessEqual; break; 3977 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break; 3978 case lir_cond_greater: acond = Assembler::greater; break; 3979 case lir_cond_belowEqual: acond = Assembler::belowEqual; break; 3980 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break; 3981 default: ShouldNotReachHere(); 3982 } 3983 __ jcc(acond, ok); 3984 } 3985 if (op->halt()) { 3986 const char* str = __ code_string(op->msg()); 3987 __ stop(str); 3988 } else { 3989 breakpoint(); 3990 } 3991 __ bind(ok); 3992 } 3993 #endif 3994 3995 void LIR_Assembler::membar() { 3996 // QQQ sparc TSO uses this, 3997 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad)); 3998 } 3999 4000 void LIR_Assembler::membar_acquire() { 4001 // No x86 machines currently require load fences 4002 } 4003 4004 void LIR_Assembler::membar_release() { 4005 // No x86 machines currently require store fences 4006 } 4007 4008 void LIR_Assembler::membar_loadload() { 4009 // no-op 4010 //__ membar(Assembler::Membar_mask_bits(Assembler::loadload)); 4011 } 4012 4013 void LIR_Assembler::membar_storestore() { 4014 // no-op 4015 //__ membar(Assembler::Membar_mask_bits(Assembler::storestore)); 4016 } 4017 4018 void LIR_Assembler::membar_loadstore() { 4019 // no-op 4020 //__ membar(Assembler::Membar_mask_bits(Assembler::loadstore)); 4021 } 4022 4023 void LIR_Assembler::membar_storeload() { 4024 __ membar(Assembler::Membar_mask_bits(Assembler::StoreLoad)); 4025 } 4026 4027 void LIR_Assembler::on_spin_wait() { 4028 __ pause (); 4029 } 4030 4031 void LIR_Assembler::get_thread(LIR_Opr result_reg) { 4032 assert(result_reg->is_register(), "check"); 4033 #ifdef _LP64 4034 // __ get_thread(result_reg->as_register_lo()); 4035 __ mov(result_reg->as_register(), r15_thread); 4036 #else 4037 __ get_thread(result_reg->as_register()); 4038 #endif // _LP64 4039 } 4040 4041 4042 void LIR_Assembler::peephole(LIR_List*) { 4043 // do nothing for now 4044 } 4045 4046 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) { 4047 assert(data == dest, "xchg/xadd uses only 2 operands"); 4048 4049 if (data->type() == T_INT) { 4050 if (code == lir_xadd) { 4051 __ lock(); 4052 __ xaddl(as_Address(src->as_address_ptr()), data->as_register()); 4053 } else { 4054 __ xchgl(data->as_register(), as_Address(src->as_address_ptr())); 4055 } 4056 } else if (data->is_oop()) { 4057 assert (code == lir_xchg, "xadd for oops"); 4058 Register obj = data->as_register(); 4059 #ifdef _LP64 4060 if (UseCompressedOops) { 4061 __ encode_heap_oop(obj); 4062 __ xchgl(obj, as_Address(src->as_address_ptr())); 4063 __ decode_heap_oop(obj); 4064 } else { 4065 __ xchgptr(obj, as_Address(src->as_address_ptr())); 4066 } 4067 #else 4068 __ xchgl(obj, as_Address(src->as_address_ptr())); 4069 #endif 4070 } else if (data->type() == T_LONG) { 4071 #ifdef _LP64 4072 assert(data->as_register_lo() == data->as_register_hi(), "should be a single register"); 4073 if (code == lir_xadd) { 4074 __ lock(); 4075 __ xaddq(as_Address(src->as_address_ptr()), data->as_register_lo()); 4076 } else { 4077 __ xchgq(data->as_register_lo(), as_Address(src->as_address_ptr())); 4078 } 4079 #else 4080 ShouldNotReachHere(); 4081 #endif 4082 } else { 4083 ShouldNotReachHere(); 4084 } 4085 } 4086 4087 #undef __