1 /* 2 * Copyright (c) 1997, 2023, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #include "precompiled.hpp" 26 #include "asm/assembler.hpp" 27 #include "asm/assembler.inline.hpp" 28 #include "compiler/compiler_globals.hpp" 29 #include "compiler/disassembler.hpp" 30 #include "crc32c.h" 31 #include "gc/shared/barrierSet.hpp" 32 #include "gc/shared/barrierSetAssembler.hpp" 33 #include "gc/shared/collectedHeap.inline.hpp" 34 #include "gc/shared/tlab_globals.hpp" 35 #include "interpreter/bytecodeHistogram.hpp" 36 #include "interpreter/interpreter.hpp" 37 #include "jvm.h" 38 #include "memory/resourceArea.hpp" 39 #include "memory/universe.hpp" 40 #include "oops/accessDecorators.hpp" 41 #include "oops/compressedOops.inline.hpp" 42 #include "oops/klass.inline.hpp" 43 #include "prims/methodHandles.hpp" 44 #include "runtime/continuation.hpp" 45 #include "runtime/interfaceSupport.inline.hpp" 46 #include "runtime/javaThread.hpp" 47 #include "runtime/jniHandles.hpp" 48 #include "runtime/objectMonitor.hpp" 49 #include "runtime/os.hpp" 50 #include "runtime/safepoint.hpp" 51 #include "runtime/safepointMechanism.hpp" 52 #include "runtime/sharedRuntime.hpp" 53 #include "runtime/stubRoutines.hpp" 54 #include "utilities/macros.hpp" 55 56 #ifdef PRODUCT 57 #define BLOCK_COMMENT(str) /* nothing */ 58 #define STOP(error) stop(error) 59 #else 60 #define BLOCK_COMMENT(str) block_comment(str) 61 #define STOP(error) block_comment(error); stop(error) 62 #endif 63 64 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":") 65 66 #ifdef ASSERT 67 bool AbstractAssembler::pd_check_instruction_mark() { return true; } 68 #endif 69 70 static const Assembler::Condition reverse[] = { 71 Assembler::noOverflow /* overflow = 0x0 */ , 72 Assembler::overflow /* noOverflow = 0x1 */ , 73 Assembler::aboveEqual /* carrySet = 0x2, below = 0x2 */ , 74 Assembler::below /* aboveEqual = 0x3, carryClear = 0x3 */ , 75 Assembler::notZero /* zero = 0x4, equal = 0x4 */ , 76 Assembler::zero /* notZero = 0x5, notEqual = 0x5 */ , 77 Assembler::above /* belowEqual = 0x6 */ , 78 Assembler::belowEqual /* above = 0x7 */ , 79 Assembler::positive /* negative = 0x8 */ , 80 Assembler::negative /* positive = 0x9 */ , 81 Assembler::noParity /* parity = 0xa */ , 82 Assembler::parity /* noParity = 0xb */ , 83 Assembler::greaterEqual /* less = 0xc */ , 84 Assembler::less /* greaterEqual = 0xd */ , 85 Assembler::greater /* lessEqual = 0xe */ , 86 Assembler::lessEqual /* greater = 0xf, */ 87 88 }; 89 90 91 // Implementation of MacroAssembler 92 93 // First all the versions that have distinct versions depending on 32/64 bit 94 // Unless the difference is trivial (1 line or so). 95 96 #ifndef _LP64 97 98 // 32bit versions 99 100 Address MacroAssembler::as_Address(AddressLiteral adr) { 101 return Address(adr.target(), adr.rspec()); 102 } 103 104 Address MacroAssembler::as_Address(ArrayAddress adr, Register rscratch) { 105 assert(rscratch == noreg, ""); 106 return Address::make_array(adr); 107 } 108 109 void MacroAssembler::call_VM_leaf_base(address entry_point, 110 int number_of_arguments) { 111 call(RuntimeAddress(entry_point)); 112 increment(rsp, number_of_arguments * wordSize); 113 } 114 115 void MacroAssembler::cmpklass(Address src1, Metadata* obj) { 116 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate()); 117 } 118 119 120 void MacroAssembler::cmpklass(Register src1, Metadata* obj) { 121 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate()); 122 } 123 124 void MacroAssembler::cmpoop(Address src1, jobject obj) { 125 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate()); 126 } 127 128 void MacroAssembler::cmpoop(Register src1, jobject obj, Register rscratch) { 129 assert(rscratch == noreg, "redundant"); 130 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate()); 131 } 132 133 void MacroAssembler::extend_sign(Register hi, Register lo) { 134 // According to Intel Doc. AP-526, "Integer Divide", p.18. 135 if (VM_Version::is_P6() && hi == rdx && lo == rax) { 136 cdql(); 137 } else { 138 movl(hi, lo); 139 sarl(hi, 31); 140 } 141 } 142 143 void MacroAssembler::jC2(Register tmp, Label& L) { 144 // set parity bit if FPU flag C2 is set (via rax) 145 save_rax(tmp); 146 fwait(); fnstsw_ax(); 147 sahf(); 148 restore_rax(tmp); 149 // branch 150 jcc(Assembler::parity, L); 151 } 152 153 void MacroAssembler::jnC2(Register tmp, Label& L) { 154 // set parity bit if FPU flag C2 is set (via rax) 155 save_rax(tmp); 156 fwait(); fnstsw_ax(); 157 sahf(); 158 restore_rax(tmp); 159 // branch 160 jcc(Assembler::noParity, L); 161 } 162 163 // 32bit can do a case table jump in one instruction but we no longer allow the base 164 // to be installed in the Address class 165 void MacroAssembler::jump(ArrayAddress entry, Register rscratch) { 166 assert(rscratch == noreg, "not needed"); 167 jmp(as_Address(entry, noreg)); 168 } 169 170 // Note: y_lo will be destroyed 171 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) { 172 // Long compare for Java (semantics as described in JVM spec.) 173 Label high, low, done; 174 175 cmpl(x_hi, y_hi); 176 jcc(Assembler::less, low); 177 jcc(Assembler::greater, high); 178 // x_hi is the return register 179 xorl(x_hi, x_hi); 180 cmpl(x_lo, y_lo); 181 jcc(Assembler::below, low); 182 jcc(Assembler::equal, done); 183 184 bind(high); 185 xorl(x_hi, x_hi); 186 increment(x_hi); 187 jmp(done); 188 189 bind(low); 190 xorl(x_hi, x_hi); 191 decrementl(x_hi); 192 193 bind(done); 194 } 195 196 void MacroAssembler::lea(Register dst, AddressLiteral src) { 197 mov_literal32(dst, (int32_t)src.target(), src.rspec()); 198 } 199 200 void MacroAssembler::lea(Address dst, AddressLiteral adr, Register rscratch) { 201 assert(rscratch == noreg, "not needed"); 202 203 // leal(dst, as_Address(adr)); 204 // see note in movl as to why we must use a move 205 mov_literal32(dst, (int32_t)adr.target(), adr.rspec()); 206 } 207 208 void MacroAssembler::leave() { 209 mov(rsp, rbp); 210 pop(rbp); 211 } 212 213 void MacroAssembler::lmul(int x_rsp_offset, int y_rsp_offset) { 214 // Multiplication of two Java long values stored on the stack 215 // as illustrated below. Result is in rdx:rax. 216 // 217 // rsp ---> [ ?? ] \ \ 218 // .... | y_rsp_offset | 219 // [ y_lo ] / (in bytes) | x_rsp_offset 220 // [ y_hi ] | (in bytes) 221 // .... | 222 // [ x_lo ] / 223 // [ x_hi ] 224 // .... 225 // 226 // Basic idea: lo(result) = lo(x_lo * y_lo) 227 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi) 228 Address x_hi(rsp, x_rsp_offset + wordSize); Address x_lo(rsp, x_rsp_offset); 229 Address y_hi(rsp, y_rsp_offset + wordSize); Address y_lo(rsp, y_rsp_offset); 230 Label quick; 231 // load x_hi, y_hi and check if quick 232 // multiplication is possible 233 movl(rbx, x_hi); 234 movl(rcx, y_hi); 235 movl(rax, rbx); 236 orl(rbx, rcx); // rbx, = 0 <=> x_hi = 0 and y_hi = 0 237 jcc(Assembler::zero, quick); // if rbx, = 0 do quick multiply 238 // do full multiplication 239 // 1st step 240 mull(y_lo); // x_hi * y_lo 241 movl(rbx, rax); // save lo(x_hi * y_lo) in rbx, 242 // 2nd step 243 movl(rax, x_lo); 244 mull(rcx); // x_lo * y_hi 245 addl(rbx, rax); // add lo(x_lo * y_hi) to rbx, 246 // 3rd step 247 bind(quick); // note: rbx, = 0 if quick multiply! 248 movl(rax, x_lo); 249 mull(y_lo); // x_lo * y_lo 250 addl(rdx, rbx); // correct hi(x_lo * y_lo) 251 } 252 253 void MacroAssembler::lneg(Register hi, Register lo) { 254 negl(lo); 255 adcl(hi, 0); 256 negl(hi); 257 } 258 259 void MacroAssembler::lshl(Register hi, Register lo) { 260 // Java shift left long support (semantics as described in JVM spec., p.305) 261 // (basic idea for shift counts s >= n: x << s == (x << n) << (s - n)) 262 // shift value is in rcx ! 263 assert(hi != rcx, "must not use rcx"); 264 assert(lo != rcx, "must not use rcx"); 265 const Register s = rcx; // shift count 266 const int n = BitsPerWord; 267 Label L; 268 andl(s, 0x3f); // s := s & 0x3f (s < 0x40) 269 cmpl(s, n); // if (s < n) 270 jcc(Assembler::less, L); // else (s >= n) 271 movl(hi, lo); // x := x << n 272 xorl(lo, lo); 273 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n! 274 bind(L); // s (mod n) < n 275 shldl(hi, lo); // x := x << s 276 shll(lo); 277 } 278 279 280 void MacroAssembler::lshr(Register hi, Register lo, bool sign_extension) { 281 // Java shift right long support (semantics as described in JVM spec., p.306 & p.310) 282 // (basic idea for shift counts s >= n: x >> s == (x >> n) >> (s - n)) 283 assert(hi != rcx, "must not use rcx"); 284 assert(lo != rcx, "must not use rcx"); 285 const Register s = rcx; // shift count 286 const int n = BitsPerWord; 287 Label L; 288 andl(s, 0x3f); // s := s & 0x3f (s < 0x40) 289 cmpl(s, n); // if (s < n) 290 jcc(Assembler::less, L); // else (s >= n) 291 movl(lo, hi); // x := x >> n 292 if (sign_extension) sarl(hi, 31); 293 else xorl(hi, hi); 294 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n! 295 bind(L); // s (mod n) < n 296 shrdl(lo, hi); // x := x >> s 297 if (sign_extension) sarl(hi); 298 else shrl(hi); 299 } 300 301 void MacroAssembler::movoop(Register dst, jobject obj) { 302 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate()); 303 } 304 305 void MacroAssembler::movoop(Address dst, jobject obj, Register rscratch) { 306 assert(rscratch == noreg, "redundant"); 307 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate()); 308 } 309 310 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) { 311 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate()); 312 } 313 314 void MacroAssembler::mov_metadata(Address dst, Metadata* obj, Register rscratch) { 315 assert(rscratch == noreg, "redundant"); 316 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate()); 317 } 318 319 void MacroAssembler::movptr(Register dst, AddressLiteral src) { 320 if (src.is_lval()) { 321 mov_literal32(dst, (intptr_t)src.target(), src.rspec()); 322 } else { 323 movl(dst, as_Address(src)); 324 } 325 } 326 327 void MacroAssembler::movptr(ArrayAddress dst, Register src, Register rscratch) { 328 assert(rscratch == noreg, "redundant"); 329 movl(as_Address(dst, noreg), src); 330 } 331 332 void MacroAssembler::movptr(Register dst, ArrayAddress src) { 333 movl(dst, as_Address(src, noreg)); 334 } 335 336 void MacroAssembler::movptr(Address dst, intptr_t src, Register rscratch) { 337 assert(rscratch == noreg, "redundant"); 338 movl(dst, src); 339 } 340 341 void MacroAssembler::pushoop(jobject obj, Register rscratch) { 342 assert(rscratch == noreg, "redundant"); 343 push_literal32((int32_t)obj, oop_Relocation::spec_for_immediate()); 344 } 345 346 void MacroAssembler::pushklass(Metadata* obj, Register rscratch) { 347 assert(rscratch == noreg, "redundant"); 348 push_literal32((int32_t)obj, metadata_Relocation::spec_for_immediate()); 349 } 350 351 void MacroAssembler::pushptr(AddressLiteral src, Register rscratch) { 352 assert(rscratch == noreg, "redundant"); 353 if (src.is_lval()) { 354 push_literal32((int32_t)src.target(), src.rspec()); 355 } else { 356 pushl(as_Address(src)); 357 } 358 } 359 360 static void pass_arg0(MacroAssembler* masm, Register arg) { 361 masm->push(arg); 362 } 363 364 static void pass_arg1(MacroAssembler* masm, Register arg) { 365 masm->push(arg); 366 } 367 368 static void pass_arg2(MacroAssembler* masm, Register arg) { 369 masm->push(arg); 370 } 371 372 static void pass_arg3(MacroAssembler* masm, Register arg) { 373 masm->push(arg); 374 } 375 376 #ifndef PRODUCT 377 extern "C" void findpc(intptr_t x); 378 #endif 379 380 void MacroAssembler::debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg) { 381 // In order to get locks to work, we need to fake a in_VM state 382 JavaThread* thread = JavaThread::current(); 383 JavaThreadState saved_state = thread->thread_state(); 384 thread->set_thread_state(_thread_in_vm); 385 if (ShowMessageBoxOnError) { 386 JavaThread* thread = JavaThread::current(); 387 JavaThreadState saved_state = thread->thread_state(); 388 thread->set_thread_state(_thread_in_vm); 389 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) { 390 ttyLocker ttyl; 391 BytecodeCounter::print(); 392 } 393 // To see where a verify_oop failed, get $ebx+40/X for this frame. 394 // This is the value of eip which points to where verify_oop will return. 395 if (os::message_box(msg, "Execution stopped, print registers?")) { 396 print_state32(rdi, rsi, rbp, rsp, rbx, rdx, rcx, rax, eip); 397 BREAKPOINT; 398 } 399 } 400 fatal("DEBUG MESSAGE: %s", msg); 401 } 402 403 void MacroAssembler::print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip) { 404 ttyLocker ttyl; 405 DebuggingContext debugging{}; 406 tty->print_cr("eip = 0x%08x", eip); 407 #ifndef PRODUCT 408 if ((WizardMode || Verbose) && PrintMiscellaneous) { 409 tty->cr(); 410 findpc(eip); 411 tty->cr(); 412 } 413 #endif 414 #define PRINT_REG(rax) \ 415 { tty->print("%s = ", #rax); os::print_location(tty, rax); } 416 PRINT_REG(rax); 417 PRINT_REG(rbx); 418 PRINT_REG(rcx); 419 PRINT_REG(rdx); 420 PRINT_REG(rdi); 421 PRINT_REG(rsi); 422 PRINT_REG(rbp); 423 PRINT_REG(rsp); 424 #undef PRINT_REG 425 // Print some words near top of staack. 426 int* dump_sp = (int*) rsp; 427 for (int col1 = 0; col1 < 8; col1++) { 428 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp); 429 os::print_location(tty, *dump_sp++); 430 } 431 for (int row = 0; row < 16; row++) { 432 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp); 433 for (int col = 0; col < 8; col++) { 434 tty->print(" 0x%08x", *dump_sp++); 435 } 436 tty->cr(); 437 } 438 // Print some instructions around pc: 439 Disassembler::decode((address)eip-64, (address)eip); 440 tty->print_cr("--------"); 441 Disassembler::decode((address)eip, (address)eip+32); 442 } 443 444 void MacroAssembler::stop(const char* msg) { 445 // push address of message 446 ExternalAddress message((address)msg); 447 pushptr(message.addr(), noreg); 448 { Label L; call(L, relocInfo::none); bind(L); } // push eip 449 pusha(); // push registers 450 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug32))); 451 hlt(); 452 } 453 454 void MacroAssembler::warn(const char* msg) { 455 push_CPU_state(); 456 457 // push address of message 458 ExternalAddress message((address)msg); 459 pushptr(message.addr(), noreg); 460 461 call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning))); 462 addl(rsp, wordSize); // discard argument 463 pop_CPU_state(); 464 } 465 466 void MacroAssembler::print_state() { 467 { Label L; call(L, relocInfo::none); bind(L); } // push eip 468 pusha(); // push registers 469 470 push_CPU_state(); 471 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::print_state32))); 472 pop_CPU_state(); 473 474 popa(); 475 addl(rsp, wordSize); 476 } 477 478 #else // _LP64 479 480 // 64 bit versions 481 482 Address MacroAssembler::as_Address(AddressLiteral adr) { 483 // amd64 always does this as a pc-rel 484 // we can be absolute or disp based on the instruction type 485 // jmp/call are displacements others are absolute 486 assert(!adr.is_lval(), "must be rval"); 487 assert(reachable(adr), "must be"); 488 return Address(checked_cast<int32_t>(adr.target() - pc()), adr.target(), adr.reloc()); 489 490 } 491 492 Address MacroAssembler::as_Address(ArrayAddress adr, Register rscratch) { 493 AddressLiteral base = adr.base(); 494 lea(rscratch, base); 495 Address index = adr.index(); 496 assert(index._disp == 0, "must not have disp"); // maybe it can? 497 Address array(rscratch, index._index, index._scale, index._disp); 498 return array; 499 } 500 501 void MacroAssembler::call_VM_leaf_base(address entry_point, int num_args) { 502 Label L, E; 503 504 #ifdef _WIN64 505 // Windows always allocates space for it's register args 506 assert(num_args <= 4, "only register arguments supported"); 507 subq(rsp, frame::arg_reg_save_area_bytes); 508 #endif 509 510 // Align stack if necessary 511 testl(rsp, 15); 512 jcc(Assembler::zero, L); 513 514 subq(rsp, 8); 515 call(RuntimeAddress(entry_point)); 516 addq(rsp, 8); 517 jmp(E); 518 519 bind(L); 520 call(RuntimeAddress(entry_point)); 521 522 bind(E); 523 524 #ifdef _WIN64 525 // restore stack pointer 526 addq(rsp, frame::arg_reg_save_area_bytes); 527 #endif 528 529 } 530 531 void MacroAssembler::cmp64(Register src1, AddressLiteral src2, Register rscratch) { 532 assert(!src2.is_lval(), "should use cmpptr"); 533 assert(rscratch != noreg || always_reachable(src2), "missing"); 534 535 if (reachable(src2)) { 536 cmpq(src1, as_Address(src2)); 537 } else { 538 lea(rscratch, src2); 539 Assembler::cmpq(src1, Address(rscratch, 0)); 540 } 541 } 542 543 int MacroAssembler::corrected_idivq(Register reg) { 544 // Full implementation of Java ldiv and lrem; checks for special 545 // case as described in JVM spec., p.243 & p.271. The function 546 // returns the (pc) offset of the idivl instruction - may be needed 547 // for implicit exceptions. 548 // 549 // normal case special case 550 // 551 // input : rax: dividend min_long 552 // reg: divisor (may not be eax/edx) -1 553 // 554 // output: rax: quotient (= rax idiv reg) min_long 555 // rdx: remainder (= rax irem reg) 0 556 assert(reg != rax && reg != rdx, "reg cannot be rax or rdx register"); 557 static const int64_t min_long = 0x8000000000000000; 558 Label normal_case, special_case; 559 560 // check for special case 561 cmp64(rax, ExternalAddress((address) &min_long), rdx /*rscratch*/); 562 jcc(Assembler::notEqual, normal_case); 563 xorl(rdx, rdx); // prepare rdx for possible special case (where 564 // remainder = 0) 565 cmpq(reg, -1); 566 jcc(Assembler::equal, special_case); 567 568 // handle normal case 569 bind(normal_case); 570 cdqq(); 571 int idivq_offset = offset(); 572 idivq(reg); 573 574 // normal and special case exit 575 bind(special_case); 576 577 return idivq_offset; 578 } 579 580 void MacroAssembler::decrementq(Register reg, int value) { 581 if (value == min_jint) { subq(reg, value); return; } 582 if (value < 0) { incrementq(reg, -value); return; } 583 if (value == 0) { ; return; } 584 if (value == 1 && UseIncDec) { decq(reg) ; return; } 585 /* else */ { subq(reg, value) ; return; } 586 } 587 588 void MacroAssembler::decrementq(Address dst, int value) { 589 if (value == min_jint) { subq(dst, value); return; } 590 if (value < 0) { incrementq(dst, -value); return; } 591 if (value == 0) { ; return; } 592 if (value == 1 && UseIncDec) { decq(dst) ; return; } 593 /* else */ { subq(dst, value) ; return; } 594 } 595 596 void MacroAssembler::incrementq(AddressLiteral dst, Register rscratch) { 597 assert(rscratch != noreg || always_reachable(dst), "missing"); 598 599 if (reachable(dst)) { 600 incrementq(as_Address(dst)); 601 } else { 602 lea(rscratch, dst); 603 incrementq(Address(rscratch, 0)); 604 } 605 } 606 607 void MacroAssembler::incrementq(Register reg, int value) { 608 if (value == min_jint) { addq(reg, value); return; } 609 if (value < 0) { decrementq(reg, -value); return; } 610 if (value == 0) { ; return; } 611 if (value == 1 && UseIncDec) { incq(reg) ; return; } 612 /* else */ { addq(reg, value) ; return; } 613 } 614 615 void MacroAssembler::incrementq(Address dst, int value) { 616 if (value == min_jint) { addq(dst, value); return; } 617 if (value < 0) { decrementq(dst, -value); return; } 618 if (value == 0) { ; return; } 619 if (value == 1 && UseIncDec) { incq(dst) ; return; } 620 /* else */ { addq(dst, value) ; return; } 621 } 622 623 // 32bit can do a case table jump in one instruction but we no longer allow the base 624 // to be installed in the Address class 625 void MacroAssembler::jump(ArrayAddress entry, Register rscratch) { 626 lea(rscratch, entry.base()); 627 Address dispatch = entry.index(); 628 assert(dispatch._base == noreg, "must be"); 629 dispatch._base = rscratch; 630 jmp(dispatch); 631 } 632 633 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) { 634 ShouldNotReachHere(); // 64bit doesn't use two regs 635 cmpq(x_lo, y_lo); 636 } 637 638 void MacroAssembler::lea(Register dst, AddressLiteral src) { 639 mov_literal64(dst, (intptr_t)src.target(), src.rspec()); 640 } 641 642 void MacroAssembler::lea(Address dst, AddressLiteral adr, Register rscratch) { 643 lea(rscratch, adr); 644 movptr(dst, rscratch); 645 } 646 647 void MacroAssembler::leave() { 648 // %%% is this really better? Why not on 32bit too? 649 emit_int8((unsigned char)0xC9); // LEAVE 650 } 651 652 void MacroAssembler::lneg(Register hi, Register lo) { 653 ShouldNotReachHere(); // 64bit doesn't use two regs 654 negq(lo); 655 } 656 657 void MacroAssembler::movoop(Register dst, jobject obj) { 658 mov_literal64(dst, (intptr_t)obj, oop_Relocation::spec_for_immediate()); 659 } 660 661 void MacroAssembler::movoop(Address dst, jobject obj, Register rscratch) { 662 mov_literal64(rscratch, (intptr_t)obj, oop_Relocation::spec_for_immediate()); 663 movq(dst, rscratch); 664 } 665 666 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) { 667 mov_literal64(dst, (intptr_t)obj, metadata_Relocation::spec_for_immediate()); 668 } 669 670 void MacroAssembler::mov_metadata(Address dst, Metadata* obj, Register rscratch) { 671 mov_literal64(rscratch, (intptr_t)obj, metadata_Relocation::spec_for_immediate()); 672 movq(dst, rscratch); 673 } 674 675 void MacroAssembler::movptr(Register dst, AddressLiteral src) { 676 if (src.is_lval()) { 677 mov_literal64(dst, (intptr_t)src.target(), src.rspec()); 678 } else { 679 if (reachable(src)) { 680 movq(dst, as_Address(src)); 681 } else { 682 lea(dst, src); 683 movq(dst, Address(dst, 0)); 684 } 685 } 686 } 687 688 void MacroAssembler::movptr(ArrayAddress dst, Register src, Register rscratch) { 689 movq(as_Address(dst, rscratch), src); 690 } 691 692 void MacroAssembler::movptr(Register dst, ArrayAddress src) { 693 movq(dst, as_Address(src, dst /*rscratch*/)); 694 } 695 696 // src should NEVER be a real pointer. Use AddressLiteral for true pointers 697 void MacroAssembler::movptr(Address dst, intptr_t src, Register rscratch) { 698 if (is_simm32(src)) { 699 movptr(dst, checked_cast<int32_t>(src)); 700 } else { 701 mov64(rscratch, src); 702 movq(dst, rscratch); 703 } 704 } 705 706 void MacroAssembler::pushoop(jobject obj, Register rscratch) { 707 movoop(rscratch, obj); 708 push(rscratch); 709 } 710 711 void MacroAssembler::pushklass(Metadata* obj, Register rscratch) { 712 mov_metadata(rscratch, obj); 713 push(rscratch); 714 } 715 716 void MacroAssembler::pushptr(AddressLiteral src, Register rscratch) { 717 lea(rscratch, src); 718 if (src.is_lval()) { 719 push(rscratch); 720 } else { 721 pushq(Address(rscratch, 0)); 722 } 723 } 724 725 void MacroAssembler::reset_last_Java_frame(bool clear_fp) { 726 reset_last_Java_frame(r15_thread, clear_fp); 727 } 728 729 void MacroAssembler::set_last_Java_frame(Register last_java_sp, 730 Register last_java_fp, 731 address last_java_pc, 732 Register rscratch) { 733 set_last_Java_frame(r15_thread, last_java_sp, last_java_fp, last_java_pc, rscratch); 734 } 735 736 static void pass_arg0(MacroAssembler* masm, Register arg) { 737 if (c_rarg0 != arg ) { 738 masm->mov(c_rarg0, arg); 739 } 740 } 741 742 static void pass_arg1(MacroAssembler* masm, Register arg) { 743 if (c_rarg1 != arg ) { 744 masm->mov(c_rarg1, arg); 745 } 746 } 747 748 static void pass_arg2(MacroAssembler* masm, Register arg) { 749 if (c_rarg2 != arg ) { 750 masm->mov(c_rarg2, arg); 751 } 752 } 753 754 static void pass_arg3(MacroAssembler* masm, Register arg) { 755 if (c_rarg3 != arg ) { 756 masm->mov(c_rarg3, arg); 757 } 758 } 759 760 void MacroAssembler::stop(const char* msg) { 761 if (ShowMessageBoxOnError) { 762 address rip = pc(); 763 pusha(); // get regs on stack 764 lea(c_rarg1, InternalAddress(rip)); 765 movq(c_rarg2, rsp); // pass pointer to regs array 766 } 767 lea(c_rarg0, ExternalAddress((address) msg)); 768 andq(rsp, -16); // align stack as required by ABI 769 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug64))); 770 hlt(); 771 } 772 773 void MacroAssembler::warn(const char* msg) { 774 push(rbp); 775 movq(rbp, rsp); 776 andq(rsp, -16); // align stack as required by push_CPU_state and call 777 push_CPU_state(); // keeps alignment at 16 bytes 778 779 lea(c_rarg0, ExternalAddress((address) msg)); 780 call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning))); 781 782 pop_CPU_state(); 783 mov(rsp, rbp); 784 pop(rbp); 785 } 786 787 void MacroAssembler::print_state() { 788 address rip = pc(); 789 pusha(); // get regs on stack 790 push(rbp); 791 movq(rbp, rsp); 792 andq(rsp, -16); // align stack as required by push_CPU_state and call 793 push_CPU_state(); // keeps alignment at 16 bytes 794 795 lea(c_rarg0, InternalAddress(rip)); 796 lea(c_rarg1, Address(rbp, wordSize)); // pass pointer to regs array 797 call_VM_leaf(CAST_FROM_FN_PTR(address, MacroAssembler::print_state64), c_rarg0, c_rarg1); 798 799 pop_CPU_state(); 800 mov(rsp, rbp); 801 pop(rbp); 802 popa(); 803 } 804 805 #ifndef PRODUCT 806 extern "C" void findpc(intptr_t x); 807 #endif 808 809 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) { 810 // In order to get locks to work, we need to fake a in_VM state 811 if (ShowMessageBoxOnError) { 812 JavaThread* thread = JavaThread::current(); 813 JavaThreadState saved_state = thread->thread_state(); 814 thread->set_thread_state(_thread_in_vm); 815 #ifndef PRODUCT 816 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) { 817 ttyLocker ttyl; 818 BytecodeCounter::print(); 819 } 820 #endif 821 // To see where a verify_oop failed, get $ebx+40/X for this frame. 822 // XXX correct this offset for amd64 823 // This is the value of eip which points to where verify_oop will return. 824 if (os::message_box(msg, "Execution stopped, print registers?")) { 825 print_state64(pc, regs); 826 BREAKPOINT; 827 } 828 } 829 fatal("DEBUG MESSAGE: %s", msg); 830 } 831 832 void MacroAssembler::print_state64(int64_t pc, int64_t regs[]) { 833 ttyLocker ttyl; 834 DebuggingContext debugging{}; 835 tty->print_cr("rip = 0x%016lx", (intptr_t)pc); 836 #ifndef PRODUCT 837 tty->cr(); 838 findpc(pc); 839 tty->cr(); 840 #endif 841 #define PRINT_REG(rax, value) \ 842 { tty->print("%s = ", #rax); os::print_location(tty, value); } 843 PRINT_REG(rax, regs[15]); 844 PRINT_REG(rbx, regs[12]); 845 PRINT_REG(rcx, regs[14]); 846 PRINT_REG(rdx, regs[13]); 847 PRINT_REG(rdi, regs[8]); 848 PRINT_REG(rsi, regs[9]); 849 PRINT_REG(rbp, regs[10]); 850 // rsp is actually not stored by pusha(), compute the old rsp from regs (rsp after pusha): regs + 16 = old rsp 851 PRINT_REG(rsp, (intptr_t)(®s[16])); 852 PRINT_REG(r8 , regs[7]); 853 PRINT_REG(r9 , regs[6]); 854 PRINT_REG(r10, regs[5]); 855 PRINT_REG(r11, regs[4]); 856 PRINT_REG(r12, regs[3]); 857 PRINT_REG(r13, regs[2]); 858 PRINT_REG(r14, regs[1]); 859 PRINT_REG(r15, regs[0]); 860 #undef PRINT_REG 861 // Print some words near the top of the stack. 862 int64_t* rsp = ®s[16]; 863 int64_t* dump_sp = rsp; 864 for (int col1 = 0; col1 < 8; col1++) { 865 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp); 866 os::print_location(tty, *dump_sp++); 867 } 868 for (int row = 0; row < 25; row++) { 869 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp); 870 for (int col = 0; col < 4; col++) { 871 tty->print(" 0x%016lx", (intptr_t)*dump_sp++); 872 } 873 tty->cr(); 874 } 875 // Print some instructions around pc: 876 Disassembler::decode((address)pc-64, (address)pc); 877 tty->print_cr("--------"); 878 Disassembler::decode((address)pc, (address)pc+32); 879 } 880 881 // The java_calling_convention describes stack locations as ideal slots on 882 // a frame with no abi restrictions. Since we must observe abi restrictions 883 // (like the placement of the register window) the slots must be biased by 884 // the following value. 885 static int reg2offset_in(VMReg r) { 886 // Account for saved rbp and return address 887 // This should really be in_preserve_stack_slots 888 return (r->reg2stack() + 4) * VMRegImpl::stack_slot_size; 889 } 890 891 static int reg2offset_out(VMReg r) { 892 return (r->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size; 893 } 894 895 // A long move 896 void MacroAssembler::long_move(VMRegPair src, VMRegPair dst, Register tmp, int in_stk_bias, int out_stk_bias) { 897 898 // The calling conventions assures us that each VMregpair is either 899 // all really one physical register or adjacent stack slots. 900 901 if (src.is_single_phys_reg() ) { 902 if (dst.is_single_phys_reg()) { 903 if (dst.first() != src.first()) { 904 mov(dst.first()->as_Register(), src.first()->as_Register()); 905 } 906 } else { 907 assert(dst.is_single_reg(), "not a stack pair: (%s, %s), (%s, %s)", 908 src.first()->name(), src.second()->name(), dst.first()->name(), dst.second()->name()); 909 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), src.first()->as_Register()); 910 } 911 } else if (dst.is_single_phys_reg()) { 912 assert(src.is_single_reg(), "not a stack pair"); 913 movq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first()) + in_stk_bias)); 914 } else { 915 assert(src.is_single_reg() && dst.is_single_reg(), "not stack pairs"); 916 movq(tmp, Address(rbp, reg2offset_in(src.first()) + in_stk_bias)); 917 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), tmp); 918 } 919 } 920 921 // A double move 922 void MacroAssembler::double_move(VMRegPair src, VMRegPair dst, Register tmp, int in_stk_bias, int out_stk_bias) { 923 924 // The calling conventions assures us that each VMregpair is either 925 // all really one physical register or adjacent stack slots. 926 927 if (src.is_single_phys_reg() ) { 928 if (dst.is_single_phys_reg()) { 929 // In theory these overlap but the ordering is such that this is likely a nop 930 if ( src.first() != dst.first()) { 931 movdbl(dst.first()->as_XMMRegister(), src.first()->as_XMMRegister()); 932 } 933 } else { 934 assert(dst.is_single_reg(), "not a stack pair"); 935 movdbl(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), src.first()->as_XMMRegister()); 936 } 937 } else if (dst.is_single_phys_reg()) { 938 assert(src.is_single_reg(), "not a stack pair"); 939 movdbl(dst.first()->as_XMMRegister(), Address(rbp, reg2offset_in(src.first()) + in_stk_bias)); 940 } else { 941 assert(src.is_single_reg() && dst.is_single_reg(), "not stack pairs"); 942 movq(tmp, Address(rbp, reg2offset_in(src.first()) + in_stk_bias)); 943 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), tmp); 944 } 945 } 946 947 948 // A float arg may have to do float reg int reg conversion 949 void MacroAssembler::float_move(VMRegPair src, VMRegPair dst, Register tmp, int in_stk_bias, int out_stk_bias) { 950 assert(!src.second()->is_valid() && !dst.second()->is_valid(), "bad float_move"); 951 952 // The calling conventions assures us that each VMregpair is either 953 // all really one physical register or adjacent stack slots. 954 955 if (src.first()->is_stack()) { 956 if (dst.first()->is_stack()) { 957 movl(tmp, Address(rbp, reg2offset_in(src.first()) + in_stk_bias)); 958 movptr(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), tmp); 959 } else { 960 // stack to reg 961 assert(dst.first()->is_XMMRegister(), "only expect xmm registers as parameters"); 962 movflt(dst.first()->as_XMMRegister(), Address(rbp, reg2offset_in(src.first()) + in_stk_bias)); 963 } 964 } else if (dst.first()->is_stack()) { 965 // reg to stack 966 assert(src.first()->is_XMMRegister(), "only expect xmm registers as parameters"); 967 movflt(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), src.first()->as_XMMRegister()); 968 } else { 969 // reg to reg 970 // In theory these overlap but the ordering is such that this is likely a nop 971 if ( src.first() != dst.first()) { 972 movdbl(dst.first()->as_XMMRegister(), src.first()->as_XMMRegister()); 973 } 974 } 975 } 976 977 // On 64 bit we will store integer like items to the stack as 978 // 64 bits items (x86_32/64 abi) even though java would only store 979 // 32bits for a parameter. On 32bit it will simply be 32 bits 980 // So this routine will do 32->32 on 32bit and 32->64 on 64bit 981 void MacroAssembler::move32_64(VMRegPair src, VMRegPair dst, Register tmp, int in_stk_bias, int out_stk_bias) { 982 if (src.first()->is_stack()) { 983 if (dst.first()->is_stack()) { 984 // stack to stack 985 movslq(tmp, Address(rbp, reg2offset_in(src.first()) + in_stk_bias)); 986 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), tmp); 987 } else { 988 // stack to reg 989 movslq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first()) + in_stk_bias)); 990 } 991 } else if (dst.first()->is_stack()) { 992 // reg to stack 993 // Do we really have to sign extend??? 994 // __ movslq(src.first()->as_Register(), src.first()->as_Register()); 995 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), src.first()->as_Register()); 996 } else { 997 // Do we really have to sign extend??? 998 // __ movslq(dst.first()->as_Register(), src.first()->as_Register()); 999 if (dst.first() != src.first()) { 1000 movq(dst.first()->as_Register(), src.first()->as_Register()); 1001 } 1002 } 1003 } 1004 1005 void MacroAssembler::move_ptr(VMRegPair src, VMRegPair dst) { 1006 if (src.first()->is_stack()) { 1007 if (dst.first()->is_stack()) { 1008 // stack to stack 1009 movq(rax, Address(rbp, reg2offset_in(src.first()))); 1010 movq(Address(rsp, reg2offset_out(dst.first())), rax); 1011 } else { 1012 // stack to reg 1013 movq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first()))); 1014 } 1015 } else if (dst.first()->is_stack()) { 1016 // reg to stack 1017 movq(Address(rsp, reg2offset_out(dst.first())), src.first()->as_Register()); 1018 } else { 1019 if (dst.first() != src.first()) { 1020 movq(dst.first()->as_Register(), src.first()->as_Register()); 1021 } 1022 } 1023 } 1024 1025 // An oop arg. Must pass a handle not the oop itself 1026 void MacroAssembler::object_move(OopMap* map, 1027 int oop_handle_offset, 1028 int framesize_in_slots, 1029 VMRegPair src, 1030 VMRegPair dst, 1031 bool is_receiver, 1032 int* receiver_offset) { 1033 1034 // must pass a handle. First figure out the location we use as a handle 1035 1036 Register rHandle = dst.first()->is_stack() ? rax : dst.first()->as_Register(); 1037 1038 // See if oop is null if it is we need no handle 1039 1040 if (src.first()->is_stack()) { 1041 1042 // Oop is already on the stack as an argument 1043 int offset_in_older_frame = src.first()->reg2stack() + SharedRuntime::out_preserve_stack_slots(); 1044 map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + framesize_in_slots)); 1045 if (is_receiver) { 1046 *receiver_offset = (offset_in_older_frame + framesize_in_slots) * VMRegImpl::stack_slot_size; 1047 } 1048 1049 cmpptr(Address(rbp, reg2offset_in(src.first())), NULL_WORD); 1050 lea(rHandle, Address(rbp, reg2offset_in(src.first()))); 1051 // conditionally move a null 1052 cmovptr(Assembler::equal, rHandle, Address(rbp, reg2offset_in(src.first()))); 1053 } else { 1054 1055 // Oop is in a register we must store it to the space we reserve 1056 // on the stack for oop_handles and pass a handle if oop is non-null 1057 1058 const Register rOop = src.first()->as_Register(); 1059 int oop_slot; 1060 if (rOop == j_rarg0) 1061 oop_slot = 0; 1062 else if (rOop == j_rarg1) 1063 oop_slot = 1; 1064 else if (rOop == j_rarg2) 1065 oop_slot = 2; 1066 else if (rOop == j_rarg3) 1067 oop_slot = 3; 1068 else if (rOop == j_rarg4) 1069 oop_slot = 4; 1070 else { 1071 assert(rOop == j_rarg5, "wrong register"); 1072 oop_slot = 5; 1073 } 1074 1075 oop_slot = oop_slot * VMRegImpl::slots_per_word + oop_handle_offset; 1076 int offset = oop_slot*VMRegImpl::stack_slot_size; 1077 1078 map->set_oop(VMRegImpl::stack2reg(oop_slot)); 1079 // Store oop in handle area, may be null 1080 movptr(Address(rsp, offset), rOop); 1081 if (is_receiver) { 1082 *receiver_offset = offset; 1083 } 1084 1085 cmpptr(rOop, NULL_WORD); 1086 lea(rHandle, Address(rsp, offset)); 1087 // conditionally move a null from the handle area where it was just stored 1088 cmovptr(Assembler::equal, rHandle, Address(rsp, offset)); 1089 } 1090 1091 // If arg is on the stack then place it otherwise it is already in correct reg. 1092 if (dst.first()->is_stack()) { 1093 movptr(Address(rsp, reg2offset_out(dst.first())), rHandle); 1094 } 1095 } 1096 1097 #endif // _LP64 1098 1099 // Now versions that are common to 32/64 bit 1100 1101 void MacroAssembler::addptr(Register dst, int32_t imm32) { 1102 LP64_ONLY(addq(dst, imm32)) NOT_LP64(addl(dst, imm32)); 1103 } 1104 1105 void MacroAssembler::addptr(Register dst, Register src) { 1106 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); 1107 } 1108 1109 void MacroAssembler::addptr(Address dst, Register src) { 1110 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); 1111 } 1112 1113 void MacroAssembler::addsd(XMMRegister dst, AddressLiteral src, Register rscratch) { 1114 assert(rscratch != noreg || always_reachable(src), "missing"); 1115 1116 if (reachable(src)) { 1117 Assembler::addsd(dst, as_Address(src)); 1118 } else { 1119 lea(rscratch, src); 1120 Assembler::addsd(dst, Address(rscratch, 0)); 1121 } 1122 } 1123 1124 void MacroAssembler::addss(XMMRegister dst, AddressLiteral src, Register rscratch) { 1125 assert(rscratch != noreg || always_reachable(src), "missing"); 1126 1127 if (reachable(src)) { 1128 addss(dst, as_Address(src)); 1129 } else { 1130 lea(rscratch, src); 1131 addss(dst, Address(rscratch, 0)); 1132 } 1133 } 1134 1135 void MacroAssembler::addpd(XMMRegister dst, AddressLiteral src, Register rscratch) { 1136 assert(rscratch != noreg || always_reachable(src), "missing"); 1137 1138 if (reachable(src)) { 1139 Assembler::addpd(dst, as_Address(src)); 1140 } else { 1141 lea(rscratch, src); 1142 Assembler::addpd(dst, Address(rscratch, 0)); 1143 } 1144 } 1145 1146 // See 8273459. Function for ensuring 64-byte alignment, intended for stubs only. 1147 // Stub code is generated once and never copied. 1148 // NMethods can't use this because they get copied and we can't force alignment > 32 bytes. 1149 void MacroAssembler::align64() { 1150 align(64, (unsigned long long) pc()); 1151 } 1152 1153 void MacroAssembler::align32() { 1154 align(32, (unsigned long long) pc()); 1155 } 1156 1157 void MacroAssembler::align(int modulus) { 1158 // 8273459: Ensure alignment is possible with current segment alignment 1159 assert(modulus <= CodeEntryAlignment, "Alignment must be <= CodeEntryAlignment"); 1160 align(modulus, offset()); 1161 } 1162 1163 void MacroAssembler::align(int modulus, int target) { 1164 if (target % modulus != 0) { 1165 nop(modulus - (target % modulus)); 1166 } 1167 } 1168 1169 void MacroAssembler::push_f(XMMRegister r) { 1170 subptr(rsp, wordSize); 1171 movflt(Address(rsp, 0), r); 1172 } 1173 1174 void MacroAssembler::pop_f(XMMRegister r) { 1175 movflt(r, Address(rsp, 0)); 1176 addptr(rsp, wordSize); 1177 } 1178 1179 void MacroAssembler::push_d(XMMRegister r) { 1180 subptr(rsp, 2 * wordSize); 1181 movdbl(Address(rsp, 0), r); 1182 } 1183 1184 void MacroAssembler::pop_d(XMMRegister r) { 1185 movdbl(r, Address(rsp, 0)); 1186 addptr(rsp, 2 * Interpreter::stackElementSize); 1187 } 1188 1189 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src, Register rscratch) { 1190 // Used in sign-masking with aligned address. 1191 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes"); 1192 assert(rscratch != noreg || always_reachable(src), "missing"); 1193 1194 if (reachable(src)) { 1195 Assembler::andpd(dst, as_Address(src)); 1196 } else { 1197 lea(rscratch, src); 1198 Assembler::andpd(dst, Address(rscratch, 0)); 1199 } 1200 } 1201 1202 void MacroAssembler::andps(XMMRegister dst, AddressLiteral src, Register rscratch) { 1203 // Used in sign-masking with aligned address. 1204 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes"); 1205 assert(rscratch != noreg || always_reachable(src), "missing"); 1206 1207 if (reachable(src)) { 1208 Assembler::andps(dst, as_Address(src)); 1209 } else { 1210 lea(rscratch, src); 1211 Assembler::andps(dst, Address(rscratch, 0)); 1212 } 1213 } 1214 1215 void MacroAssembler::andptr(Register dst, int32_t imm32) { 1216 LP64_ONLY(andq(dst, imm32)) NOT_LP64(andl(dst, imm32)); 1217 } 1218 1219 #ifdef _LP64 1220 void MacroAssembler::andq(Register dst, AddressLiteral src, Register rscratch) { 1221 assert(rscratch != noreg || always_reachable(src), "missing"); 1222 1223 if (reachable(src)) { 1224 andq(dst, as_Address(src)); 1225 } else { 1226 lea(rscratch, src); 1227 andq(dst, Address(rscratch, 0)); 1228 } 1229 } 1230 #endif 1231 1232 void MacroAssembler::atomic_incl(Address counter_addr) { 1233 lock(); 1234 incrementl(counter_addr); 1235 } 1236 1237 void MacroAssembler::atomic_incl(AddressLiteral counter_addr, Register rscratch) { 1238 assert(rscratch != noreg || always_reachable(counter_addr), "missing"); 1239 1240 if (reachable(counter_addr)) { 1241 atomic_incl(as_Address(counter_addr)); 1242 } else { 1243 lea(rscratch, counter_addr); 1244 atomic_incl(Address(rscratch, 0)); 1245 } 1246 } 1247 1248 #ifdef _LP64 1249 void MacroAssembler::atomic_incq(Address counter_addr) { 1250 lock(); 1251 incrementq(counter_addr); 1252 } 1253 1254 void MacroAssembler::atomic_incq(AddressLiteral counter_addr, Register rscratch) { 1255 assert(rscratch != noreg || always_reachable(counter_addr), "missing"); 1256 1257 if (reachable(counter_addr)) { 1258 atomic_incq(as_Address(counter_addr)); 1259 } else { 1260 lea(rscratch, counter_addr); 1261 atomic_incq(Address(rscratch, 0)); 1262 } 1263 } 1264 #endif 1265 1266 // Writes to stack successive pages until offset reached to check for 1267 // stack overflow + shadow pages. This clobbers tmp. 1268 void MacroAssembler::bang_stack_size(Register size, Register tmp) { 1269 movptr(tmp, rsp); 1270 // Bang stack for total size given plus shadow page size. 1271 // Bang one page at a time because large size can bang beyond yellow and 1272 // red zones. 1273 Label loop; 1274 bind(loop); 1275 movl(Address(tmp, (-(int)os::vm_page_size())), size ); 1276 subptr(tmp, (int)os::vm_page_size()); 1277 subl(size, (int)os::vm_page_size()); 1278 jcc(Assembler::greater, loop); 1279 1280 // Bang down shadow pages too. 1281 // At this point, (tmp-0) is the last address touched, so don't 1282 // touch it again. (It was touched as (tmp-pagesize) but then tmp 1283 // was post-decremented.) Skip this address by starting at i=1, and 1284 // touch a few more pages below. N.B. It is important to touch all 1285 // the way down including all pages in the shadow zone. 1286 for (int i = 1; i < ((int)StackOverflow::stack_shadow_zone_size() / (int)os::vm_page_size()); i++) { 1287 // this could be any sized move but this is can be a debugging crumb 1288 // so the bigger the better. 1289 movptr(Address(tmp, (-i*(int)os::vm_page_size())), size ); 1290 } 1291 } 1292 1293 void MacroAssembler::reserved_stack_check() { 1294 // testing if reserved zone needs to be enabled 1295 Label no_reserved_zone_enabling; 1296 Register thread = NOT_LP64(rsi) LP64_ONLY(r15_thread); 1297 NOT_LP64(get_thread(rsi);) 1298 1299 cmpptr(rsp, Address(thread, JavaThread::reserved_stack_activation_offset())); 1300 jcc(Assembler::below, no_reserved_zone_enabling); 1301 1302 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::enable_stack_reserved_zone), thread); 1303 jump(RuntimeAddress(StubRoutines::throw_delayed_StackOverflowError_entry())); 1304 should_not_reach_here(); 1305 1306 bind(no_reserved_zone_enabling); 1307 } 1308 1309 void MacroAssembler::c2bool(Register x) { 1310 // implements x == 0 ? 0 : 1 1311 // note: must only look at least-significant byte of x 1312 // since C-style booleans are stored in one byte 1313 // only! (was bug) 1314 andl(x, 0xFF); 1315 setb(Assembler::notZero, x); 1316 } 1317 1318 // Wouldn't need if AddressLiteral version had new name 1319 void MacroAssembler::call(Label& L, relocInfo::relocType rtype) { 1320 Assembler::call(L, rtype); 1321 } 1322 1323 void MacroAssembler::call(Register entry) { 1324 Assembler::call(entry); 1325 } 1326 1327 void MacroAssembler::call(AddressLiteral entry, Register rscratch) { 1328 assert(rscratch != noreg || always_reachable(entry), "missing"); 1329 1330 if (reachable(entry)) { 1331 Assembler::call_literal(entry.target(), entry.rspec()); 1332 } else { 1333 lea(rscratch, entry); 1334 Assembler::call(rscratch); 1335 } 1336 } 1337 1338 void MacroAssembler::ic_call(address entry, jint method_index) { 1339 RelocationHolder rh = virtual_call_Relocation::spec(pc(), method_index); 1340 movptr(rax, (intptr_t)Universe::non_oop_word()); 1341 call(AddressLiteral(entry, rh)); 1342 } 1343 1344 void MacroAssembler::emit_static_call_stub() { 1345 // Static stub relocation also tags the Method* in the code-stream. 1346 mov_metadata(rbx, (Metadata*) nullptr); // Method is zapped till fixup time. 1347 // This is recognized as unresolved by relocs/nativeinst/ic code. 1348 jump(RuntimeAddress(pc())); 1349 } 1350 1351 // Implementation of call_VM versions 1352 1353 void MacroAssembler::call_VM(Register oop_result, 1354 address entry_point, 1355 bool check_exceptions) { 1356 Label C, E; 1357 call(C, relocInfo::none); 1358 jmp(E); 1359 1360 bind(C); 1361 call_VM_helper(oop_result, entry_point, 0, check_exceptions); 1362 ret(0); 1363 1364 bind(E); 1365 } 1366 1367 void MacroAssembler::call_VM(Register oop_result, 1368 address entry_point, 1369 Register arg_1, 1370 bool check_exceptions) { 1371 Label C, E; 1372 call(C, relocInfo::none); 1373 jmp(E); 1374 1375 bind(C); 1376 pass_arg1(this, arg_1); 1377 call_VM_helper(oop_result, entry_point, 1, check_exceptions); 1378 ret(0); 1379 1380 bind(E); 1381 } 1382 1383 void MacroAssembler::call_VM(Register oop_result, 1384 address entry_point, 1385 Register arg_1, 1386 Register arg_2, 1387 bool check_exceptions) { 1388 Label C, E; 1389 call(C, relocInfo::none); 1390 jmp(E); 1391 1392 bind(C); 1393 1394 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 1395 1396 pass_arg2(this, arg_2); 1397 pass_arg1(this, arg_1); 1398 call_VM_helper(oop_result, entry_point, 2, check_exceptions); 1399 ret(0); 1400 1401 bind(E); 1402 } 1403 1404 void MacroAssembler::call_VM(Register oop_result, 1405 address entry_point, 1406 Register arg_1, 1407 Register arg_2, 1408 Register arg_3, 1409 bool check_exceptions) { 1410 Label C, E; 1411 call(C, relocInfo::none); 1412 jmp(E); 1413 1414 bind(C); 1415 1416 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg")); 1417 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg")); 1418 pass_arg3(this, arg_3); 1419 1420 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 1421 pass_arg2(this, arg_2); 1422 1423 pass_arg1(this, arg_1); 1424 call_VM_helper(oop_result, entry_point, 3, check_exceptions); 1425 ret(0); 1426 1427 bind(E); 1428 } 1429 1430 void MacroAssembler::call_VM(Register oop_result, 1431 Register last_java_sp, 1432 address entry_point, 1433 int number_of_arguments, 1434 bool check_exceptions) { 1435 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg); 1436 call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions); 1437 } 1438 1439 void MacroAssembler::call_VM(Register oop_result, 1440 Register last_java_sp, 1441 address entry_point, 1442 Register arg_1, 1443 bool check_exceptions) { 1444 pass_arg1(this, arg_1); 1445 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions); 1446 } 1447 1448 void MacroAssembler::call_VM(Register oop_result, 1449 Register last_java_sp, 1450 address entry_point, 1451 Register arg_1, 1452 Register arg_2, 1453 bool check_exceptions) { 1454 1455 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 1456 pass_arg2(this, arg_2); 1457 pass_arg1(this, arg_1); 1458 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions); 1459 } 1460 1461 void MacroAssembler::call_VM(Register oop_result, 1462 Register last_java_sp, 1463 address entry_point, 1464 Register arg_1, 1465 Register arg_2, 1466 Register arg_3, 1467 bool check_exceptions) { 1468 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg")); 1469 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg")); 1470 pass_arg3(this, arg_3); 1471 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 1472 pass_arg2(this, arg_2); 1473 pass_arg1(this, arg_1); 1474 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions); 1475 } 1476 1477 void MacroAssembler::super_call_VM(Register oop_result, 1478 Register last_java_sp, 1479 address entry_point, 1480 int number_of_arguments, 1481 bool check_exceptions) { 1482 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg); 1483 MacroAssembler::call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions); 1484 } 1485 1486 void MacroAssembler::super_call_VM(Register oop_result, 1487 Register last_java_sp, 1488 address entry_point, 1489 Register arg_1, 1490 bool check_exceptions) { 1491 pass_arg1(this, arg_1); 1492 super_call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions); 1493 } 1494 1495 void MacroAssembler::super_call_VM(Register oop_result, 1496 Register last_java_sp, 1497 address entry_point, 1498 Register arg_1, 1499 Register arg_2, 1500 bool check_exceptions) { 1501 1502 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 1503 pass_arg2(this, arg_2); 1504 pass_arg1(this, arg_1); 1505 super_call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions); 1506 } 1507 1508 void MacroAssembler::super_call_VM(Register oop_result, 1509 Register last_java_sp, 1510 address entry_point, 1511 Register arg_1, 1512 Register arg_2, 1513 Register arg_3, 1514 bool check_exceptions) { 1515 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg")); 1516 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg")); 1517 pass_arg3(this, arg_3); 1518 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 1519 pass_arg2(this, arg_2); 1520 pass_arg1(this, arg_1); 1521 super_call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions); 1522 } 1523 1524 void MacroAssembler::call_VM_base(Register oop_result, 1525 Register java_thread, 1526 Register last_java_sp, 1527 address entry_point, 1528 int number_of_arguments, 1529 bool check_exceptions) { 1530 // determine java_thread register 1531 if (!java_thread->is_valid()) { 1532 #ifdef _LP64 1533 java_thread = r15_thread; 1534 #else 1535 java_thread = rdi; 1536 get_thread(java_thread); 1537 #endif // LP64 1538 } 1539 // determine last_java_sp register 1540 if (!last_java_sp->is_valid()) { 1541 last_java_sp = rsp; 1542 } 1543 // debugging support 1544 assert(number_of_arguments >= 0 , "cannot have negative number of arguments"); 1545 LP64_ONLY(assert(java_thread == r15_thread, "unexpected register")); 1546 #ifdef ASSERT 1547 // TraceBytecodes does not use r12 but saves it over the call, so don't verify 1548 // r12 is the heapbase. 1549 LP64_ONLY(if (UseCompressedOops && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?");) 1550 #endif // ASSERT 1551 1552 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result"); 1553 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp"); 1554 1555 // push java thread (becomes first argument of C function) 1556 1557 NOT_LP64(push(java_thread); number_of_arguments++); 1558 LP64_ONLY(mov(c_rarg0, r15_thread)); 1559 1560 // set last Java frame before call 1561 assert(last_java_sp != rbp, "can't use ebp/rbp"); 1562 1563 // Only interpreter should have to set fp 1564 set_last_Java_frame(java_thread, last_java_sp, rbp, nullptr, rscratch1); 1565 1566 // do the call, remove parameters 1567 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments); 1568 1569 // restore the thread (cannot use the pushed argument since arguments 1570 // may be overwritten by C code generated by an optimizing compiler); 1571 // however can use the register value directly if it is callee saved. 1572 if (LP64_ONLY(true ||) java_thread == rdi || java_thread == rsi) { 1573 // rdi & rsi (also r15) are callee saved -> nothing to do 1574 #ifdef ASSERT 1575 guarantee(java_thread != rax, "change this code"); 1576 push(rax); 1577 { Label L; 1578 get_thread(rax); 1579 cmpptr(java_thread, rax); 1580 jcc(Assembler::equal, L); 1581 STOP("MacroAssembler::call_VM_base: rdi not callee saved?"); 1582 bind(L); 1583 } 1584 pop(rax); 1585 #endif 1586 } else { 1587 get_thread(java_thread); 1588 } 1589 // reset last Java frame 1590 // Only interpreter should have to clear fp 1591 reset_last_Java_frame(java_thread, true); 1592 1593 // C++ interp handles this in the interpreter 1594 check_and_handle_popframe(java_thread); 1595 check_and_handle_earlyret(java_thread); 1596 1597 if (check_exceptions) { 1598 // check for pending exceptions (java_thread is set upon return) 1599 cmpptr(Address(java_thread, Thread::pending_exception_offset()), NULL_WORD); 1600 #ifndef _LP64 1601 jump_cc(Assembler::notEqual, 1602 RuntimeAddress(StubRoutines::forward_exception_entry())); 1603 #else 1604 // This used to conditionally jump to forward_exception however it is 1605 // possible if we relocate that the branch will not reach. So we must jump 1606 // around so we can always reach 1607 1608 Label ok; 1609 jcc(Assembler::equal, ok); 1610 jump(RuntimeAddress(StubRoutines::forward_exception_entry())); 1611 bind(ok); 1612 #endif // LP64 1613 } 1614 1615 // get oop result if there is one and reset the value in the thread 1616 if (oop_result->is_valid()) { 1617 get_vm_result(oop_result, java_thread); 1618 } 1619 } 1620 1621 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) { 1622 1623 // Calculate the value for last_Java_sp 1624 // somewhat subtle. call_VM does an intermediate call 1625 // which places a return address on the stack just under the 1626 // stack pointer as the user finished with it. This allows 1627 // use to retrieve last_Java_pc from last_Java_sp[-1]. 1628 // On 32bit we then have to push additional args on the stack to accomplish 1629 // the actual requested call. On 64bit call_VM only can use register args 1630 // so the only extra space is the return address that call_VM created. 1631 // This hopefully explains the calculations here. 1632 1633 #ifdef _LP64 1634 // We've pushed one address, correct last_Java_sp 1635 lea(rax, Address(rsp, wordSize)); 1636 #else 1637 lea(rax, Address(rsp, (1 + number_of_arguments) * wordSize)); 1638 #endif // LP64 1639 1640 call_VM_base(oop_result, noreg, rax, entry_point, number_of_arguments, check_exceptions); 1641 1642 } 1643 1644 // Use this method when MacroAssembler version of call_VM_leaf_base() should be called from Interpreter. 1645 void MacroAssembler::call_VM_leaf0(address entry_point) { 1646 MacroAssembler::call_VM_leaf_base(entry_point, 0); 1647 } 1648 1649 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) { 1650 call_VM_leaf_base(entry_point, number_of_arguments); 1651 } 1652 1653 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) { 1654 pass_arg0(this, arg_0); 1655 call_VM_leaf(entry_point, 1); 1656 } 1657 1658 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) { 1659 1660 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); 1661 pass_arg1(this, arg_1); 1662 pass_arg0(this, arg_0); 1663 call_VM_leaf(entry_point, 2); 1664 } 1665 1666 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) { 1667 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg")); 1668 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 1669 pass_arg2(this, arg_2); 1670 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); 1671 pass_arg1(this, arg_1); 1672 pass_arg0(this, arg_0); 1673 call_VM_leaf(entry_point, 3); 1674 } 1675 1676 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) { 1677 LP64_ONLY(assert(arg_0 != c_rarg3, "smashed arg")); 1678 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg")); 1679 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg")); 1680 pass_arg3(this, arg_3); 1681 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg")); 1682 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 1683 pass_arg2(this, arg_2); 1684 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); 1685 pass_arg1(this, arg_1); 1686 pass_arg0(this, arg_0); 1687 call_VM_leaf(entry_point, 3); 1688 } 1689 1690 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) { 1691 pass_arg0(this, arg_0); 1692 MacroAssembler::call_VM_leaf_base(entry_point, 1); 1693 } 1694 1695 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) { 1696 1697 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); 1698 pass_arg1(this, arg_1); 1699 pass_arg0(this, arg_0); 1700 MacroAssembler::call_VM_leaf_base(entry_point, 2); 1701 } 1702 1703 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) { 1704 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg")); 1705 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 1706 pass_arg2(this, arg_2); 1707 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); 1708 pass_arg1(this, arg_1); 1709 pass_arg0(this, arg_0); 1710 MacroAssembler::call_VM_leaf_base(entry_point, 3); 1711 } 1712 1713 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) { 1714 LP64_ONLY(assert(arg_0 != c_rarg3, "smashed arg")); 1715 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg")); 1716 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg")); 1717 pass_arg3(this, arg_3); 1718 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg")); 1719 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 1720 pass_arg2(this, arg_2); 1721 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); 1722 pass_arg1(this, arg_1); 1723 pass_arg0(this, arg_0); 1724 MacroAssembler::call_VM_leaf_base(entry_point, 4); 1725 } 1726 1727 void MacroAssembler::get_vm_result(Register oop_result, Register java_thread) { 1728 movptr(oop_result, Address(java_thread, JavaThread::vm_result_offset())); 1729 movptr(Address(java_thread, JavaThread::vm_result_offset()), NULL_WORD); 1730 verify_oop_msg(oop_result, "broken oop in call_VM_base"); 1731 } 1732 1733 void MacroAssembler::get_vm_result_2(Register metadata_result, Register java_thread) { 1734 movptr(metadata_result, Address(java_thread, JavaThread::vm_result_2_offset())); 1735 movptr(Address(java_thread, JavaThread::vm_result_2_offset()), NULL_WORD); 1736 } 1737 1738 void MacroAssembler::check_and_handle_earlyret(Register java_thread) { 1739 } 1740 1741 void MacroAssembler::check_and_handle_popframe(Register java_thread) { 1742 } 1743 1744 void MacroAssembler::cmp32(AddressLiteral src1, int32_t imm, Register rscratch) { 1745 assert(rscratch != noreg || always_reachable(src1), "missing"); 1746 1747 if (reachable(src1)) { 1748 cmpl(as_Address(src1), imm); 1749 } else { 1750 lea(rscratch, src1); 1751 cmpl(Address(rscratch, 0), imm); 1752 } 1753 } 1754 1755 void MacroAssembler::cmp32(Register src1, AddressLiteral src2, Register rscratch) { 1756 assert(!src2.is_lval(), "use cmpptr"); 1757 assert(rscratch != noreg || always_reachable(src2), "missing"); 1758 1759 if (reachable(src2)) { 1760 cmpl(src1, as_Address(src2)); 1761 } else { 1762 lea(rscratch, src2); 1763 cmpl(src1, Address(rscratch, 0)); 1764 } 1765 } 1766 1767 void MacroAssembler::cmp32(Register src1, int32_t imm) { 1768 Assembler::cmpl(src1, imm); 1769 } 1770 1771 void MacroAssembler::cmp32(Register src1, Address src2) { 1772 Assembler::cmpl(src1, src2); 1773 } 1774 1775 void MacroAssembler::cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) { 1776 ucomisd(opr1, opr2); 1777 1778 Label L; 1779 if (unordered_is_less) { 1780 movl(dst, -1); 1781 jcc(Assembler::parity, L); 1782 jcc(Assembler::below , L); 1783 movl(dst, 0); 1784 jcc(Assembler::equal , L); 1785 increment(dst); 1786 } else { // unordered is greater 1787 movl(dst, 1); 1788 jcc(Assembler::parity, L); 1789 jcc(Assembler::above , L); 1790 movl(dst, 0); 1791 jcc(Assembler::equal , L); 1792 decrementl(dst); 1793 } 1794 bind(L); 1795 } 1796 1797 void MacroAssembler::cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) { 1798 ucomiss(opr1, opr2); 1799 1800 Label L; 1801 if (unordered_is_less) { 1802 movl(dst, -1); 1803 jcc(Assembler::parity, L); 1804 jcc(Assembler::below , L); 1805 movl(dst, 0); 1806 jcc(Assembler::equal , L); 1807 increment(dst); 1808 } else { // unordered is greater 1809 movl(dst, 1); 1810 jcc(Assembler::parity, L); 1811 jcc(Assembler::above , L); 1812 movl(dst, 0); 1813 jcc(Assembler::equal , L); 1814 decrementl(dst); 1815 } 1816 bind(L); 1817 } 1818 1819 1820 void MacroAssembler::cmp8(AddressLiteral src1, int imm, Register rscratch) { 1821 assert(rscratch != noreg || always_reachable(src1), "missing"); 1822 1823 if (reachable(src1)) { 1824 cmpb(as_Address(src1), imm); 1825 } else { 1826 lea(rscratch, src1); 1827 cmpb(Address(rscratch, 0), imm); 1828 } 1829 } 1830 1831 void MacroAssembler::cmpptr(Register src1, AddressLiteral src2, Register rscratch) { 1832 #ifdef _LP64 1833 assert(rscratch != noreg || always_reachable(src2), "missing"); 1834 1835 if (src2.is_lval()) { 1836 movptr(rscratch, src2); 1837 Assembler::cmpq(src1, rscratch); 1838 } else if (reachable(src2)) { 1839 cmpq(src1, as_Address(src2)); 1840 } else { 1841 lea(rscratch, src2); 1842 Assembler::cmpq(src1, Address(rscratch, 0)); 1843 } 1844 #else 1845 assert(rscratch == noreg, "not needed"); 1846 if (src2.is_lval()) { 1847 cmp_literal32(src1, (int32_t)src2.target(), src2.rspec()); 1848 } else { 1849 cmpl(src1, as_Address(src2)); 1850 } 1851 #endif // _LP64 1852 } 1853 1854 void MacroAssembler::cmpptr(Address src1, AddressLiteral src2, Register rscratch) { 1855 assert(src2.is_lval(), "not a mem-mem compare"); 1856 #ifdef _LP64 1857 // moves src2's literal address 1858 movptr(rscratch, src2); 1859 Assembler::cmpq(src1, rscratch); 1860 #else 1861 assert(rscratch == noreg, "not needed"); 1862 cmp_literal32(src1, (int32_t)src2.target(), src2.rspec()); 1863 #endif // _LP64 1864 } 1865 1866 void MacroAssembler::cmpoop(Register src1, Register src2) { 1867 cmpptr(src1, src2); 1868 } 1869 1870 void MacroAssembler::cmpoop(Register src1, Address src2) { 1871 cmpptr(src1, src2); 1872 } 1873 1874 #ifdef _LP64 1875 void MacroAssembler::cmpoop(Register src1, jobject src2, Register rscratch) { 1876 movoop(rscratch, src2); 1877 cmpptr(src1, rscratch); 1878 } 1879 #endif 1880 1881 void MacroAssembler::locked_cmpxchgptr(Register reg, AddressLiteral adr, Register rscratch) { 1882 assert(rscratch != noreg || always_reachable(adr), "missing"); 1883 1884 if (reachable(adr)) { 1885 lock(); 1886 cmpxchgptr(reg, as_Address(adr)); 1887 } else { 1888 lea(rscratch, adr); 1889 lock(); 1890 cmpxchgptr(reg, Address(rscratch, 0)); 1891 } 1892 } 1893 1894 void MacroAssembler::cmpxchgptr(Register reg, Address adr) { 1895 LP64_ONLY(cmpxchgq(reg, adr)) NOT_LP64(cmpxchgl(reg, adr)); 1896 } 1897 1898 void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src, Register rscratch) { 1899 assert(rscratch != noreg || always_reachable(src), "missing"); 1900 1901 if (reachable(src)) { 1902 Assembler::comisd(dst, as_Address(src)); 1903 } else { 1904 lea(rscratch, src); 1905 Assembler::comisd(dst, Address(rscratch, 0)); 1906 } 1907 } 1908 1909 void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src, Register rscratch) { 1910 assert(rscratch != noreg || always_reachable(src), "missing"); 1911 1912 if (reachable(src)) { 1913 Assembler::comiss(dst, as_Address(src)); 1914 } else { 1915 lea(rscratch, src); 1916 Assembler::comiss(dst, Address(rscratch, 0)); 1917 } 1918 } 1919 1920 1921 void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr, Register rscratch) { 1922 assert(rscratch != noreg || always_reachable(counter_addr), "missing"); 1923 1924 Condition negated_cond = negate_condition(cond); 1925 Label L; 1926 jcc(negated_cond, L); 1927 pushf(); // Preserve flags 1928 atomic_incl(counter_addr, rscratch); 1929 popf(); 1930 bind(L); 1931 } 1932 1933 int MacroAssembler::corrected_idivl(Register reg) { 1934 // Full implementation of Java idiv and irem; checks for 1935 // special case as described in JVM spec., p.243 & p.271. 1936 // The function returns the (pc) offset of the idivl 1937 // instruction - may be needed for implicit exceptions. 1938 // 1939 // normal case special case 1940 // 1941 // input : rax,: dividend min_int 1942 // reg: divisor (may not be rax,/rdx) -1 1943 // 1944 // output: rax,: quotient (= rax, idiv reg) min_int 1945 // rdx: remainder (= rax, irem reg) 0 1946 assert(reg != rax && reg != rdx, "reg cannot be rax, or rdx register"); 1947 const int min_int = 0x80000000; 1948 Label normal_case, special_case; 1949 1950 // check for special case 1951 cmpl(rax, min_int); 1952 jcc(Assembler::notEqual, normal_case); 1953 xorl(rdx, rdx); // prepare rdx for possible special case (where remainder = 0) 1954 cmpl(reg, -1); 1955 jcc(Assembler::equal, special_case); 1956 1957 // handle normal case 1958 bind(normal_case); 1959 cdql(); 1960 int idivl_offset = offset(); 1961 idivl(reg); 1962 1963 // normal and special case exit 1964 bind(special_case); 1965 1966 return idivl_offset; 1967 } 1968 1969 1970 1971 void MacroAssembler::decrementl(Register reg, int value) { 1972 if (value == min_jint) {subl(reg, value) ; return; } 1973 if (value < 0) { incrementl(reg, -value); return; } 1974 if (value == 0) { ; return; } 1975 if (value == 1 && UseIncDec) { decl(reg) ; return; } 1976 /* else */ { subl(reg, value) ; return; } 1977 } 1978 1979 void MacroAssembler::decrementl(Address dst, int value) { 1980 if (value == min_jint) {subl(dst, value) ; return; } 1981 if (value < 0) { incrementl(dst, -value); return; } 1982 if (value == 0) { ; return; } 1983 if (value == 1 && UseIncDec) { decl(dst) ; return; } 1984 /* else */ { subl(dst, value) ; return; } 1985 } 1986 1987 void MacroAssembler::division_with_shift (Register reg, int shift_value) { 1988 assert(shift_value > 0, "illegal shift value"); 1989 Label _is_positive; 1990 testl (reg, reg); 1991 jcc (Assembler::positive, _is_positive); 1992 int offset = (1 << shift_value) - 1 ; 1993 1994 if (offset == 1) { 1995 incrementl(reg); 1996 } else { 1997 addl(reg, offset); 1998 } 1999 2000 bind (_is_positive); 2001 sarl(reg, shift_value); 2002 } 2003 2004 void MacroAssembler::divsd(XMMRegister dst, AddressLiteral src, Register rscratch) { 2005 assert(rscratch != noreg || always_reachable(src), "missing"); 2006 2007 if (reachable(src)) { 2008 Assembler::divsd(dst, as_Address(src)); 2009 } else { 2010 lea(rscratch, src); 2011 Assembler::divsd(dst, Address(rscratch, 0)); 2012 } 2013 } 2014 2015 void MacroAssembler::divss(XMMRegister dst, AddressLiteral src, Register rscratch) { 2016 assert(rscratch != noreg || always_reachable(src), "missing"); 2017 2018 if (reachable(src)) { 2019 Assembler::divss(dst, as_Address(src)); 2020 } else { 2021 lea(rscratch, src); 2022 Assembler::divss(dst, Address(rscratch, 0)); 2023 } 2024 } 2025 2026 void MacroAssembler::enter() { 2027 push(rbp); 2028 mov(rbp, rsp); 2029 } 2030 2031 void MacroAssembler::post_call_nop() { 2032 if (!Continuations::enabled()) { 2033 return; 2034 } 2035 InstructionMark im(this); 2036 relocate(post_call_nop_Relocation::spec()); 2037 InlineSkippedInstructionsCounter skipCounter(this); 2038 emit_int8((int8_t)0x0f); 2039 emit_int8((int8_t)0x1f); 2040 emit_int8((int8_t)0x84); 2041 emit_int8((int8_t)0x00); 2042 emit_int32(0x00); 2043 } 2044 2045 // A 5 byte nop that is safe for patching (see patch_verified_entry) 2046 void MacroAssembler::fat_nop() { 2047 if (UseAddressNop) { 2048 addr_nop_5(); 2049 } else { 2050 emit_int8((int8_t)0x26); // es: 2051 emit_int8((int8_t)0x2e); // cs: 2052 emit_int8((int8_t)0x64); // fs: 2053 emit_int8((int8_t)0x65); // gs: 2054 emit_int8((int8_t)0x90); 2055 } 2056 } 2057 2058 #ifndef _LP64 2059 void MacroAssembler::fcmp(Register tmp) { 2060 fcmp(tmp, 1, true, true); 2061 } 2062 2063 void MacroAssembler::fcmp(Register tmp, int index, bool pop_left, bool pop_right) { 2064 assert(!pop_right || pop_left, "usage error"); 2065 if (VM_Version::supports_cmov()) { 2066 assert(tmp == noreg, "unneeded temp"); 2067 if (pop_left) { 2068 fucomip(index); 2069 } else { 2070 fucomi(index); 2071 } 2072 if (pop_right) { 2073 fpop(); 2074 } 2075 } else { 2076 assert(tmp != noreg, "need temp"); 2077 if (pop_left) { 2078 if (pop_right) { 2079 fcompp(); 2080 } else { 2081 fcomp(index); 2082 } 2083 } else { 2084 fcom(index); 2085 } 2086 // convert FPU condition into eflags condition via rax, 2087 save_rax(tmp); 2088 fwait(); fnstsw_ax(); 2089 sahf(); 2090 restore_rax(tmp); 2091 } 2092 // condition codes set as follows: 2093 // 2094 // CF (corresponds to C0) if x < y 2095 // PF (corresponds to C2) if unordered 2096 // ZF (corresponds to C3) if x = y 2097 } 2098 2099 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less) { 2100 fcmp2int(dst, unordered_is_less, 1, true, true); 2101 } 2102 2103 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right) { 2104 fcmp(VM_Version::supports_cmov() ? noreg : dst, index, pop_left, pop_right); 2105 Label L; 2106 if (unordered_is_less) { 2107 movl(dst, -1); 2108 jcc(Assembler::parity, L); 2109 jcc(Assembler::below , L); 2110 movl(dst, 0); 2111 jcc(Assembler::equal , L); 2112 increment(dst); 2113 } else { // unordered is greater 2114 movl(dst, 1); 2115 jcc(Assembler::parity, L); 2116 jcc(Assembler::above , L); 2117 movl(dst, 0); 2118 jcc(Assembler::equal , L); 2119 decrementl(dst); 2120 } 2121 bind(L); 2122 } 2123 2124 void MacroAssembler::fld_d(AddressLiteral src) { 2125 fld_d(as_Address(src)); 2126 } 2127 2128 void MacroAssembler::fld_s(AddressLiteral src) { 2129 fld_s(as_Address(src)); 2130 } 2131 2132 void MacroAssembler::fldcw(AddressLiteral src) { 2133 fldcw(as_Address(src)); 2134 } 2135 2136 void MacroAssembler::fpop() { 2137 ffree(); 2138 fincstp(); 2139 } 2140 2141 void MacroAssembler::fremr(Register tmp) { 2142 save_rax(tmp); 2143 { Label L; 2144 bind(L); 2145 fprem(); 2146 fwait(); fnstsw_ax(); 2147 sahf(); 2148 jcc(Assembler::parity, L); 2149 } 2150 restore_rax(tmp); 2151 // Result is in ST0. 2152 // Note: fxch & fpop to get rid of ST1 2153 // (otherwise FPU stack could overflow eventually) 2154 fxch(1); 2155 fpop(); 2156 } 2157 2158 void MacroAssembler::empty_FPU_stack() { 2159 if (VM_Version::supports_mmx()) { 2160 emms(); 2161 } else { 2162 for (int i = 8; i-- > 0; ) ffree(i); 2163 } 2164 } 2165 #endif // !LP64 2166 2167 void MacroAssembler::mulpd(XMMRegister dst, AddressLiteral src, Register rscratch) { 2168 assert(rscratch != noreg || always_reachable(src), "missing"); 2169 if (reachable(src)) { 2170 Assembler::mulpd(dst, as_Address(src)); 2171 } else { 2172 lea(rscratch, src); 2173 Assembler::mulpd(dst, Address(rscratch, 0)); 2174 } 2175 } 2176 2177 void MacroAssembler::load_float(Address src) { 2178 #ifdef _LP64 2179 movflt(xmm0, src); 2180 #else 2181 if (UseSSE >= 1) { 2182 movflt(xmm0, src); 2183 } else { 2184 fld_s(src); 2185 } 2186 #endif // LP64 2187 } 2188 2189 void MacroAssembler::store_float(Address dst) { 2190 #ifdef _LP64 2191 movflt(dst, xmm0); 2192 #else 2193 if (UseSSE >= 1) { 2194 movflt(dst, xmm0); 2195 } else { 2196 fstp_s(dst); 2197 } 2198 #endif // LP64 2199 } 2200 2201 void MacroAssembler::load_double(Address src) { 2202 #ifdef _LP64 2203 movdbl(xmm0, src); 2204 #else 2205 if (UseSSE >= 2) { 2206 movdbl(xmm0, src); 2207 } else { 2208 fld_d(src); 2209 } 2210 #endif // LP64 2211 } 2212 2213 void MacroAssembler::store_double(Address dst) { 2214 #ifdef _LP64 2215 movdbl(dst, xmm0); 2216 #else 2217 if (UseSSE >= 2) { 2218 movdbl(dst, xmm0); 2219 } else { 2220 fstp_d(dst); 2221 } 2222 #endif // LP64 2223 } 2224 2225 // dst = c = a * b + c 2226 void MacroAssembler::fmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) { 2227 Assembler::vfmadd231sd(c, a, b); 2228 if (dst != c) { 2229 movdbl(dst, c); 2230 } 2231 } 2232 2233 // dst = c = a * b + c 2234 void MacroAssembler::fmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) { 2235 Assembler::vfmadd231ss(c, a, b); 2236 if (dst != c) { 2237 movflt(dst, c); 2238 } 2239 } 2240 2241 // dst = c = a * b + c 2242 void MacroAssembler::vfmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len) { 2243 Assembler::vfmadd231pd(c, a, b, vector_len); 2244 if (dst != c) { 2245 vmovdqu(dst, c); 2246 } 2247 } 2248 2249 // dst = c = a * b + c 2250 void MacroAssembler::vfmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len) { 2251 Assembler::vfmadd231ps(c, a, b, vector_len); 2252 if (dst != c) { 2253 vmovdqu(dst, c); 2254 } 2255 } 2256 2257 // dst = c = a * b + c 2258 void MacroAssembler::vfmad(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len) { 2259 Assembler::vfmadd231pd(c, a, b, vector_len); 2260 if (dst != c) { 2261 vmovdqu(dst, c); 2262 } 2263 } 2264 2265 // dst = c = a * b + c 2266 void MacroAssembler::vfmaf(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len) { 2267 Assembler::vfmadd231ps(c, a, b, vector_len); 2268 if (dst != c) { 2269 vmovdqu(dst, c); 2270 } 2271 } 2272 2273 void MacroAssembler::incrementl(AddressLiteral dst, Register rscratch) { 2274 assert(rscratch != noreg || always_reachable(dst), "missing"); 2275 2276 if (reachable(dst)) { 2277 incrementl(as_Address(dst)); 2278 } else { 2279 lea(rscratch, dst); 2280 incrementl(Address(rscratch, 0)); 2281 } 2282 } 2283 2284 void MacroAssembler::incrementl(ArrayAddress dst, Register rscratch) { 2285 incrementl(as_Address(dst, rscratch)); 2286 } 2287 2288 void MacroAssembler::incrementl(Register reg, int value) { 2289 if (value == min_jint) {addl(reg, value) ; return; } 2290 if (value < 0) { decrementl(reg, -value); return; } 2291 if (value == 0) { ; return; } 2292 if (value == 1 && UseIncDec) { incl(reg) ; return; } 2293 /* else */ { addl(reg, value) ; return; } 2294 } 2295 2296 void MacroAssembler::incrementl(Address dst, int value) { 2297 if (value == min_jint) {addl(dst, value) ; return; } 2298 if (value < 0) { decrementl(dst, -value); return; } 2299 if (value == 0) { ; return; } 2300 if (value == 1 && UseIncDec) { incl(dst) ; return; } 2301 /* else */ { addl(dst, value) ; return; } 2302 } 2303 2304 void MacroAssembler::jump(AddressLiteral dst, Register rscratch) { 2305 assert(rscratch != noreg || always_reachable(dst), "missing"); 2306 2307 if (reachable(dst)) { 2308 jmp_literal(dst.target(), dst.rspec()); 2309 } else { 2310 lea(rscratch, dst); 2311 jmp(rscratch); 2312 } 2313 } 2314 2315 void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst, Register rscratch) { 2316 assert(rscratch != noreg || always_reachable(dst), "missing"); 2317 2318 if (reachable(dst)) { 2319 InstructionMark im(this); 2320 relocate(dst.reloc()); 2321 const int short_size = 2; 2322 const int long_size = 6; 2323 int offs = (intptr_t)dst.target() - ((intptr_t)pc()); 2324 if (dst.reloc() == relocInfo::none && is8bit(offs - short_size)) { 2325 // 0111 tttn #8-bit disp 2326 emit_int8(0x70 | cc); 2327 emit_int8((offs - short_size) & 0xFF); 2328 } else { 2329 // 0000 1111 1000 tttn #32-bit disp 2330 emit_int8(0x0F); 2331 emit_int8((unsigned char)(0x80 | cc)); 2332 emit_int32(offs - long_size); 2333 } 2334 } else { 2335 #ifdef ASSERT 2336 warning("reversing conditional branch"); 2337 #endif /* ASSERT */ 2338 Label skip; 2339 jccb(reverse[cc], skip); 2340 lea(rscratch, dst); 2341 Assembler::jmp(rscratch); 2342 bind(skip); 2343 } 2344 } 2345 2346 void MacroAssembler::ldmxcsr(AddressLiteral src, Register rscratch) { 2347 assert(rscratch != noreg || always_reachable(src), "missing"); 2348 2349 if (reachable(src)) { 2350 Assembler::ldmxcsr(as_Address(src)); 2351 } else { 2352 lea(rscratch, src); 2353 Assembler::ldmxcsr(Address(rscratch, 0)); 2354 } 2355 } 2356 2357 int MacroAssembler::load_signed_byte(Register dst, Address src) { 2358 int off; 2359 if (LP64_ONLY(true ||) VM_Version::is_P6()) { 2360 off = offset(); 2361 movsbl(dst, src); // movsxb 2362 } else { 2363 off = load_unsigned_byte(dst, src); 2364 shll(dst, 24); 2365 sarl(dst, 24); 2366 } 2367 return off; 2368 } 2369 2370 // Note: load_signed_short used to be called load_signed_word. 2371 // Although the 'w' in x86 opcodes refers to the term "word" in the assembler 2372 // manual, which means 16 bits, that usage is found nowhere in HotSpot code. 2373 // The term "word" in HotSpot means a 32- or 64-bit machine word. 2374 int MacroAssembler::load_signed_short(Register dst, Address src) { 2375 int off; 2376 if (LP64_ONLY(true ||) VM_Version::is_P6()) { 2377 // This is dubious to me since it seems safe to do a signed 16 => 64 bit 2378 // version but this is what 64bit has always done. This seems to imply 2379 // that users are only using 32bits worth. 2380 off = offset(); 2381 movswl(dst, src); // movsxw 2382 } else { 2383 off = load_unsigned_short(dst, src); 2384 shll(dst, 16); 2385 sarl(dst, 16); 2386 } 2387 return off; 2388 } 2389 2390 int MacroAssembler::load_unsigned_byte(Register dst, Address src) { 2391 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16, 2392 // and "3.9 Partial Register Penalties", p. 22). 2393 int off; 2394 if (LP64_ONLY(true || ) VM_Version::is_P6() || src.uses(dst)) { 2395 off = offset(); 2396 movzbl(dst, src); // movzxb 2397 } else { 2398 xorl(dst, dst); 2399 off = offset(); 2400 movb(dst, src); 2401 } 2402 return off; 2403 } 2404 2405 // Note: load_unsigned_short used to be called load_unsigned_word. 2406 int MacroAssembler::load_unsigned_short(Register dst, Address src) { 2407 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16, 2408 // and "3.9 Partial Register Penalties", p. 22). 2409 int off; 2410 if (LP64_ONLY(true ||) VM_Version::is_P6() || src.uses(dst)) { 2411 off = offset(); 2412 movzwl(dst, src); // movzxw 2413 } else { 2414 xorl(dst, dst); 2415 off = offset(); 2416 movw(dst, src); 2417 } 2418 return off; 2419 } 2420 2421 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2) { 2422 switch (size_in_bytes) { 2423 #ifndef _LP64 2424 case 8: 2425 assert(dst2 != noreg, "second dest register required"); 2426 movl(dst, src); 2427 movl(dst2, src.plus_disp(BytesPerInt)); 2428 break; 2429 #else 2430 case 8: movq(dst, src); break; 2431 #endif 2432 case 4: movl(dst, src); break; 2433 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break; 2434 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break; 2435 default: ShouldNotReachHere(); 2436 } 2437 } 2438 2439 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) { 2440 switch (size_in_bytes) { 2441 #ifndef _LP64 2442 case 8: 2443 assert(src2 != noreg, "second source register required"); 2444 movl(dst, src); 2445 movl(dst.plus_disp(BytesPerInt), src2); 2446 break; 2447 #else 2448 case 8: movq(dst, src); break; 2449 #endif 2450 case 4: movl(dst, src); break; 2451 case 2: movw(dst, src); break; 2452 case 1: movb(dst, src); break; 2453 default: ShouldNotReachHere(); 2454 } 2455 } 2456 2457 void MacroAssembler::mov32(AddressLiteral dst, Register src, Register rscratch) { 2458 assert(rscratch != noreg || always_reachable(dst), "missing"); 2459 2460 if (reachable(dst)) { 2461 movl(as_Address(dst), src); 2462 } else { 2463 lea(rscratch, dst); 2464 movl(Address(rscratch, 0), src); 2465 } 2466 } 2467 2468 void MacroAssembler::mov32(Register dst, AddressLiteral src) { 2469 if (reachable(src)) { 2470 movl(dst, as_Address(src)); 2471 } else { 2472 lea(dst, src); 2473 movl(dst, Address(dst, 0)); 2474 } 2475 } 2476 2477 // C++ bool manipulation 2478 2479 void MacroAssembler::movbool(Register dst, Address src) { 2480 if(sizeof(bool) == 1) 2481 movb(dst, src); 2482 else if(sizeof(bool) == 2) 2483 movw(dst, src); 2484 else if(sizeof(bool) == 4) 2485 movl(dst, src); 2486 else 2487 // unsupported 2488 ShouldNotReachHere(); 2489 } 2490 2491 void MacroAssembler::movbool(Address dst, bool boolconst) { 2492 if(sizeof(bool) == 1) 2493 movb(dst, (int) boolconst); 2494 else if(sizeof(bool) == 2) 2495 movw(dst, (int) boolconst); 2496 else if(sizeof(bool) == 4) 2497 movl(dst, (int) boolconst); 2498 else 2499 // unsupported 2500 ShouldNotReachHere(); 2501 } 2502 2503 void MacroAssembler::movbool(Address dst, Register src) { 2504 if(sizeof(bool) == 1) 2505 movb(dst, src); 2506 else if(sizeof(bool) == 2) 2507 movw(dst, src); 2508 else if(sizeof(bool) == 4) 2509 movl(dst, src); 2510 else 2511 // unsupported 2512 ShouldNotReachHere(); 2513 } 2514 2515 void MacroAssembler::movdl(XMMRegister dst, AddressLiteral src, Register rscratch) { 2516 assert(rscratch != noreg || always_reachable(src), "missing"); 2517 2518 if (reachable(src)) { 2519 movdl(dst, as_Address(src)); 2520 } else { 2521 lea(rscratch, src); 2522 movdl(dst, Address(rscratch, 0)); 2523 } 2524 } 2525 2526 void MacroAssembler::movq(XMMRegister dst, AddressLiteral src, Register rscratch) { 2527 assert(rscratch != noreg || always_reachable(src), "missing"); 2528 2529 if (reachable(src)) { 2530 movq(dst, as_Address(src)); 2531 } else { 2532 lea(rscratch, src); 2533 movq(dst, Address(rscratch, 0)); 2534 } 2535 } 2536 2537 void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src, Register rscratch) { 2538 assert(rscratch != noreg || always_reachable(src), "missing"); 2539 2540 if (reachable(src)) { 2541 if (UseXmmLoadAndClearUpper) { 2542 movsd (dst, as_Address(src)); 2543 } else { 2544 movlpd(dst, as_Address(src)); 2545 } 2546 } else { 2547 lea(rscratch, src); 2548 if (UseXmmLoadAndClearUpper) { 2549 movsd (dst, Address(rscratch, 0)); 2550 } else { 2551 movlpd(dst, Address(rscratch, 0)); 2552 } 2553 } 2554 } 2555 2556 void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src, Register rscratch) { 2557 assert(rscratch != noreg || always_reachable(src), "missing"); 2558 2559 if (reachable(src)) { 2560 movss(dst, as_Address(src)); 2561 } else { 2562 lea(rscratch, src); 2563 movss(dst, Address(rscratch, 0)); 2564 } 2565 } 2566 2567 void MacroAssembler::movptr(Register dst, Register src) { 2568 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); 2569 } 2570 2571 void MacroAssembler::movptr(Register dst, Address src) { 2572 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); 2573 } 2574 2575 // src should NEVER be a real pointer. Use AddressLiteral for true pointers 2576 void MacroAssembler::movptr(Register dst, intptr_t src) { 2577 LP64_ONLY(mov64(dst, src)) NOT_LP64(movl(dst, src)); 2578 } 2579 2580 void MacroAssembler::movptr(Address dst, Register src) { 2581 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); 2582 } 2583 2584 void MacroAssembler::movptr(Address dst, int32_t src) { 2585 LP64_ONLY(movslq(dst, src)) NOT_LP64(movl(dst, src)); 2586 } 2587 2588 void MacroAssembler::movdqu(Address dst, XMMRegister src) { 2589 assert(((src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15"); 2590 Assembler::movdqu(dst, src); 2591 } 2592 2593 void MacroAssembler::movdqu(XMMRegister dst, Address src) { 2594 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15"); 2595 Assembler::movdqu(dst, src); 2596 } 2597 2598 void MacroAssembler::movdqu(XMMRegister dst, XMMRegister src) { 2599 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15"); 2600 Assembler::movdqu(dst, src); 2601 } 2602 2603 void MacroAssembler::movdqu(XMMRegister dst, AddressLiteral src, Register rscratch) { 2604 assert(rscratch != noreg || always_reachable(src), "missing"); 2605 2606 if (reachable(src)) { 2607 movdqu(dst, as_Address(src)); 2608 } else { 2609 lea(rscratch, src); 2610 movdqu(dst, Address(rscratch, 0)); 2611 } 2612 } 2613 2614 void MacroAssembler::vmovdqu(Address dst, XMMRegister src) { 2615 assert(((src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15"); 2616 Assembler::vmovdqu(dst, src); 2617 } 2618 2619 void MacroAssembler::vmovdqu(XMMRegister dst, Address src) { 2620 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15"); 2621 Assembler::vmovdqu(dst, src); 2622 } 2623 2624 void MacroAssembler::vmovdqu(XMMRegister dst, XMMRegister src) { 2625 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15"); 2626 Assembler::vmovdqu(dst, src); 2627 } 2628 2629 void MacroAssembler::vmovdqu(XMMRegister dst, AddressLiteral src, Register rscratch) { 2630 assert(rscratch != noreg || always_reachable(src), "missing"); 2631 2632 if (reachable(src)) { 2633 vmovdqu(dst, as_Address(src)); 2634 } 2635 else { 2636 lea(rscratch, src); 2637 vmovdqu(dst, Address(rscratch, 0)); 2638 } 2639 } 2640 2641 void MacroAssembler::vmovdqu(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) { 2642 assert(rscratch != noreg || always_reachable(src), "missing"); 2643 2644 if (vector_len == AVX_512bit) { 2645 evmovdquq(dst, src, AVX_512bit, rscratch); 2646 } else if (vector_len == AVX_256bit) { 2647 vmovdqu(dst, src, rscratch); 2648 } else { 2649 movdqu(dst, src, rscratch); 2650 } 2651 } 2652 2653 void MacroAssembler::kmov(KRegister dst, Address src) { 2654 if (VM_Version::supports_avx512bw()) { 2655 kmovql(dst, src); 2656 } else { 2657 assert(VM_Version::supports_evex(), ""); 2658 kmovwl(dst, src); 2659 } 2660 } 2661 2662 void MacroAssembler::kmov(Address dst, KRegister src) { 2663 if (VM_Version::supports_avx512bw()) { 2664 kmovql(dst, src); 2665 } else { 2666 assert(VM_Version::supports_evex(), ""); 2667 kmovwl(dst, src); 2668 } 2669 } 2670 2671 void MacroAssembler::kmov(KRegister dst, KRegister src) { 2672 if (VM_Version::supports_avx512bw()) { 2673 kmovql(dst, src); 2674 } else { 2675 assert(VM_Version::supports_evex(), ""); 2676 kmovwl(dst, src); 2677 } 2678 } 2679 2680 void MacroAssembler::kmov(Register dst, KRegister src) { 2681 if (VM_Version::supports_avx512bw()) { 2682 kmovql(dst, src); 2683 } else { 2684 assert(VM_Version::supports_evex(), ""); 2685 kmovwl(dst, src); 2686 } 2687 } 2688 2689 void MacroAssembler::kmov(KRegister dst, Register src) { 2690 if (VM_Version::supports_avx512bw()) { 2691 kmovql(dst, src); 2692 } else { 2693 assert(VM_Version::supports_evex(), ""); 2694 kmovwl(dst, src); 2695 } 2696 } 2697 2698 void MacroAssembler::kmovql(KRegister dst, AddressLiteral src, Register rscratch) { 2699 assert(rscratch != noreg || always_reachable(src), "missing"); 2700 2701 if (reachable(src)) { 2702 kmovql(dst, as_Address(src)); 2703 } else { 2704 lea(rscratch, src); 2705 kmovql(dst, Address(rscratch, 0)); 2706 } 2707 } 2708 2709 void MacroAssembler::kmovwl(KRegister dst, AddressLiteral src, Register rscratch) { 2710 assert(rscratch != noreg || always_reachable(src), "missing"); 2711 2712 if (reachable(src)) { 2713 kmovwl(dst, as_Address(src)); 2714 } else { 2715 lea(rscratch, src); 2716 kmovwl(dst, Address(rscratch, 0)); 2717 } 2718 } 2719 2720 void MacroAssembler::evmovdqub(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, 2721 int vector_len, Register rscratch) { 2722 assert(rscratch != noreg || always_reachable(src), "missing"); 2723 2724 if (reachable(src)) { 2725 Assembler::evmovdqub(dst, mask, as_Address(src), merge, vector_len); 2726 } else { 2727 lea(rscratch, src); 2728 Assembler::evmovdqub(dst, mask, Address(rscratch, 0), merge, vector_len); 2729 } 2730 } 2731 2732 void MacroAssembler::evmovdquw(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, 2733 int vector_len, Register rscratch) { 2734 assert(rscratch != noreg || always_reachable(src), "missing"); 2735 2736 if (reachable(src)) { 2737 Assembler::evmovdquw(dst, mask, as_Address(src), merge, vector_len); 2738 } else { 2739 lea(rscratch, src); 2740 Assembler::evmovdquw(dst, mask, Address(rscratch, 0), merge, vector_len); 2741 } 2742 } 2743 2744 void MacroAssembler::evmovdqul(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register rscratch) { 2745 assert(rscratch != noreg || always_reachable(src), "missing"); 2746 2747 if (reachable(src)) { 2748 Assembler::evmovdqul(dst, mask, as_Address(src), merge, vector_len); 2749 } else { 2750 lea(rscratch, src); 2751 Assembler::evmovdqul(dst, mask, Address(rscratch, 0), merge, vector_len); 2752 } 2753 } 2754 2755 void MacroAssembler::evmovdquq(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register rscratch) { 2756 assert(rscratch != noreg || always_reachable(src), "missing"); 2757 2758 if (reachable(src)) { 2759 Assembler::evmovdquq(dst, mask, as_Address(src), merge, vector_len); 2760 } else { 2761 lea(rscratch, src); 2762 Assembler::evmovdquq(dst, mask, Address(rscratch, 0), merge, vector_len); 2763 } 2764 } 2765 2766 void MacroAssembler::evmovdquq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) { 2767 assert(rscratch != noreg || always_reachable(src), "missing"); 2768 2769 if (reachable(src)) { 2770 Assembler::evmovdquq(dst, as_Address(src), vector_len); 2771 } else { 2772 lea(rscratch, src); 2773 Assembler::evmovdquq(dst, Address(rscratch, 0), vector_len); 2774 } 2775 } 2776 2777 void MacroAssembler::movdqa(XMMRegister dst, AddressLiteral src, Register rscratch) { 2778 assert(rscratch != noreg || always_reachable(src), "missing"); 2779 2780 if (reachable(src)) { 2781 Assembler::movdqa(dst, as_Address(src)); 2782 } else { 2783 lea(rscratch, src); 2784 Assembler::movdqa(dst, Address(rscratch, 0)); 2785 } 2786 } 2787 2788 void MacroAssembler::movsd(XMMRegister dst, AddressLiteral src, Register rscratch) { 2789 assert(rscratch != noreg || always_reachable(src), "missing"); 2790 2791 if (reachable(src)) { 2792 Assembler::movsd(dst, as_Address(src)); 2793 } else { 2794 lea(rscratch, src); 2795 Assembler::movsd(dst, Address(rscratch, 0)); 2796 } 2797 } 2798 2799 void MacroAssembler::movss(XMMRegister dst, AddressLiteral src, Register rscratch) { 2800 assert(rscratch != noreg || always_reachable(src), "missing"); 2801 2802 if (reachable(src)) { 2803 Assembler::movss(dst, as_Address(src)); 2804 } else { 2805 lea(rscratch, src); 2806 Assembler::movss(dst, Address(rscratch, 0)); 2807 } 2808 } 2809 2810 void MacroAssembler::movddup(XMMRegister dst, AddressLiteral src, Register rscratch) { 2811 assert(rscratch != noreg || always_reachable(src), "missing"); 2812 2813 if (reachable(src)) { 2814 Assembler::movddup(dst, as_Address(src)); 2815 } else { 2816 lea(rscratch, src); 2817 Assembler::movddup(dst, Address(rscratch, 0)); 2818 } 2819 } 2820 2821 void MacroAssembler::vmovddup(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) { 2822 assert(rscratch != noreg || always_reachable(src), "missing"); 2823 2824 if (reachable(src)) { 2825 Assembler::vmovddup(dst, as_Address(src), vector_len); 2826 } else { 2827 lea(rscratch, src); 2828 Assembler::vmovddup(dst, Address(rscratch, 0), vector_len); 2829 } 2830 } 2831 2832 void MacroAssembler::mulsd(XMMRegister dst, AddressLiteral src, Register rscratch) { 2833 assert(rscratch != noreg || always_reachable(src), "missing"); 2834 2835 if (reachable(src)) { 2836 Assembler::mulsd(dst, as_Address(src)); 2837 } else { 2838 lea(rscratch, src); 2839 Assembler::mulsd(dst, Address(rscratch, 0)); 2840 } 2841 } 2842 2843 void MacroAssembler::mulss(XMMRegister dst, AddressLiteral src, Register rscratch) { 2844 assert(rscratch != noreg || always_reachable(src), "missing"); 2845 2846 if (reachable(src)) { 2847 Assembler::mulss(dst, as_Address(src)); 2848 } else { 2849 lea(rscratch, src); 2850 Assembler::mulss(dst, Address(rscratch, 0)); 2851 } 2852 } 2853 2854 void MacroAssembler::null_check(Register reg, int offset) { 2855 if (needs_explicit_null_check(offset)) { 2856 // provoke OS null exception if reg is null by 2857 // accessing M[reg] w/o changing any (non-CC) registers 2858 // NOTE: cmpl is plenty here to provoke a segv 2859 cmpptr(rax, Address(reg, 0)); 2860 // Note: should probably use testl(rax, Address(reg, 0)); 2861 // may be shorter code (however, this version of 2862 // testl needs to be implemented first) 2863 } else { 2864 // nothing to do, (later) access of M[reg + offset] 2865 // will provoke OS null exception if reg is null 2866 } 2867 } 2868 2869 void MacroAssembler::os_breakpoint() { 2870 // instead of directly emitting a breakpoint, call os:breakpoint for better debugability 2871 // (e.g., MSVC can't call ps() otherwise) 2872 call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint))); 2873 } 2874 2875 void MacroAssembler::unimplemented(const char* what) { 2876 const char* buf = nullptr; 2877 { 2878 ResourceMark rm; 2879 stringStream ss; 2880 ss.print("unimplemented: %s", what); 2881 buf = code_string(ss.as_string()); 2882 } 2883 stop(buf); 2884 } 2885 2886 #ifdef _LP64 2887 #define XSTATE_BV 0x200 2888 #endif 2889 2890 void MacroAssembler::pop_CPU_state() { 2891 pop_FPU_state(); 2892 pop_IU_state(); 2893 } 2894 2895 void MacroAssembler::pop_FPU_state() { 2896 #ifndef _LP64 2897 frstor(Address(rsp, 0)); 2898 #else 2899 fxrstor(Address(rsp, 0)); 2900 #endif 2901 addptr(rsp, FPUStateSizeInWords * wordSize); 2902 } 2903 2904 void MacroAssembler::pop_IU_state() { 2905 popa(); 2906 LP64_ONLY(addq(rsp, 8)); 2907 popf(); 2908 } 2909 2910 // Save Integer and Float state 2911 // Warning: Stack must be 16 byte aligned (64bit) 2912 void MacroAssembler::push_CPU_state() { 2913 push_IU_state(); 2914 push_FPU_state(); 2915 } 2916 2917 void MacroAssembler::push_FPU_state() { 2918 subptr(rsp, FPUStateSizeInWords * wordSize); 2919 #ifndef _LP64 2920 fnsave(Address(rsp, 0)); 2921 fwait(); 2922 #else 2923 fxsave(Address(rsp, 0)); 2924 #endif // LP64 2925 } 2926 2927 void MacroAssembler::push_IU_state() { 2928 // Push flags first because pusha kills them 2929 pushf(); 2930 // Make sure rsp stays 16-byte aligned 2931 LP64_ONLY(subq(rsp, 8)); 2932 pusha(); 2933 } 2934 2935 void MacroAssembler::push_cont_fastpath() { 2936 if (!Continuations::enabled()) return; 2937 2938 #ifndef _LP64 2939 Register rthread = rax; 2940 Register rrealsp = rbx; 2941 push(rthread); 2942 push(rrealsp); 2943 2944 get_thread(rthread); 2945 2946 // The code below wants the original RSP. 2947 // Move it back after the pushes above. 2948 movptr(rrealsp, rsp); 2949 addptr(rrealsp, 2*wordSize); 2950 #else 2951 Register rthread = r15_thread; 2952 Register rrealsp = rsp; 2953 #endif 2954 2955 Label done; 2956 cmpptr(rrealsp, Address(rthread, JavaThread::cont_fastpath_offset())); 2957 jccb(Assembler::belowEqual, done); 2958 movptr(Address(rthread, JavaThread::cont_fastpath_offset()), rrealsp); 2959 bind(done); 2960 2961 #ifndef _LP64 2962 pop(rrealsp); 2963 pop(rthread); 2964 #endif 2965 } 2966 2967 void MacroAssembler::pop_cont_fastpath() { 2968 if (!Continuations::enabled()) return; 2969 2970 #ifndef _LP64 2971 Register rthread = rax; 2972 Register rrealsp = rbx; 2973 push(rthread); 2974 push(rrealsp); 2975 2976 get_thread(rthread); 2977 2978 // The code below wants the original RSP. 2979 // Move it back after the pushes above. 2980 movptr(rrealsp, rsp); 2981 addptr(rrealsp, 2*wordSize); 2982 #else 2983 Register rthread = r15_thread; 2984 Register rrealsp = rsp; 2985 #endif 2986 2987 Label done; 2988 cmpptr(rrealsp, Address(rthread, JavaThread::cont_fastpath_offset())); 2989 jccb(Assembler::below, done); 2990 movptr(Address(rthread, JavaThread::cont_fastpath_offset()), 0); 2991 bind(done); 2992 2993 #ifndef _LP64 2994 pop(rrealsp); 2995 pop(rthread); 2996 #endif 2997 } 2998 2999 void MacroAssembler::inc_held_monitor_count() { 3000 #ifndef _LP64 3001 Register thread = rax; 3002 push(thread); 3003 get_thread(thread); 3004 incrementl(Address(thread, JavaThread::held_monitor_count_offset())); 3005 pop(thread); 3006 #else // LP64 3007 incrementq(Address(r15_thread, JavaThread::held_monitor_count_offset())); 3008 #endif 3009 } 3010 3011 void MacroAssembler::dec_held_monitor_count() { 3012 #ifndef _LP64 3013 Register thread = rax; 3014 push(thread); 3015 get_thread(thread); 3016 decrementl(Address(thread, JavaThread::held_monitor_count_offset())); 3017 pop(thread); 3018 #else // LP64 3019 decrementq(Address(r15_thread, JavaThread::held_monitor_count_offset())); 3020 #endif 3021 } 3022 3023 #ifdef ASSERT 3024 void MacroAssembler::stop_if_in_cont(Register cont, const char* name) { 3025 #ifdef _LP64 3026 Label no_cont; 3027 movptr(cont, Address(r15_thread, JavaThread::cont_entry_offset())); 3028 testl(cont, cont); 3029 jcc(Assembler::zero, no_cont); 3030 stop(name); 3031 bind(no_cont); 3032 #else 3033 Unimplemented(); 3034 #endif 3035 } 3036 #endif 3037 3038 void MacroAssembler::reset_last_Java_frame(Register java_thread, bool clear_fp) { // determine java_thread register 3039 if (!java_thread->is_valid()) { 3040 java_thread = rdi; 3041 get_thread(java_thread); 3042 } 3043 // we must set sp to zero to clear frame 3044 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), NULL_WORD); 3045 // must clear fp, so that compiled frames are not confused; it is 3046 // possible that we need it only for debugging 3047 if (clear_fp) { 3048 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), NULL_WORD); 3049 } 3050 // Always clear the pc because it could have been set by make_walkable() 3051 movptr(Address(java_thread, JavaThread::last_Java_pc_offset()), NULL_WORD); 3052 vzeroupper(); 3053 } 3054 3055 void MacroAssembler::restore_rax(Register tmp) { 3056 if (tmp == noreg) pop(rax); 3057 else if (tmp != rax) mov(rax, tmp); 3058 } 3059 3060 void MacroAssembler::round_to(Register reg, int modulus) { 3061 addptr(reg, modulus - 1); 3062 andptr(reg, -modulus); 3063 } 3064 3065 void MacroAssembler::save_rax(Register tmp) { 3066 if (tmp == noreg) push(rax); 3067 else if (tmp != rax) mov(tmp, rax); 3068 } 3069 3070 void MacroAssembler::safepoint_poll(Label& slow_path, Register thread_reg, bool at_return, bool in_nmethod) { 3071 if (at_return) { 3072 // Note that when in_nmethod is set, the stack pointer is incremented before the poll. Therefore, 3073 // we may safely use rsp instead to perform the stack watermark check. 3074 cmpptr(in_nmethod ? rsp : rbp, Address(thread_reg, JavaThread::polling_word_offset())); 3075 jcc(Assembler::above, slow_path); 3076 return; 3077 } 3078 testb(Address(thread_reg, JavaThread::polling_word_offset()), SafepointMechanism::poll_bit()); 3079 jcc(Assembler::notZero, slow_path); // handshake bit set implies poll 3080 } 3081 3082 // Calls to C land 3083 // 3084 // When entering C land, the rbp, & rsp of the last Java frame have to be recorded 3085 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp 3086 // has to be reset to 0. This is required to allow proper stack traversal. 3087 void MacroAssembler::set_last_Java_frame(Register java_thread, 3088 Register last_java_sp, 3089 Register last_java_fp, 3090 address last_java_pc, 3091 Register rscratch) { 3092 vzeroupper(); 3093 // determine java_thread register 3094 if (!java_thread->is_valid()) { 3095 java_thread = rdi; 3096 get_thread(java_thread); 3097 } 3098 // determine last_java_sp register 3099 if (!last_java_sp->is_valid()) { 3100 last_java_sp = rsp; 3101 } 3102 // last_java_fp is optional 3103 if (last_java_fp->is_valid()) { 3104 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), last_java_fp); 3105 } 3106 // last_java_pc is optional 3107 if (last_java_pc != nullptr) { 3108 Address java_pc(java_thread, 3109 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()); 3110 lea(java_pc, InternalAddress(last_java_pc), rscratch); 3111 } 3112 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), last_java_sp); 3113 } 3114 3115 void MacroAssembler::shlptr(Register dst, int imm8) { 3116 LP64_ONLY(shlq(dst, imm8)) NOT_LP64(shll(dst, imm8)); 3117 } 3118 3119 void MacroAssembler::shrptr(Register dst, int imm8) { 3120 LP64_ONLY(shrq(dst, imm8)) NOT_LP64(shrl(dst, imm8)); 3121 } 3122 3123 void MacroAssembler::sign_extend_byte(Register reg) { 3124 if (LP64_ONLY(true ||) (VM_Version::is_P6() && reg->has_byte_register())) { 3125 movsbl(reg, reg); // movsxb 3126 } else { 3127 shll(reg, 24); 3128 sarl(reg, 24); 3129 } 3130 } 3131 3132 void MacroAssembler::sign_extend_short(Register reg) { 3133 if (LP64_ONLY(true ||) VM_Version::is_P6()) { 3134 movswl(reg, reg); // movsxw 3135 } else { 3136 shll(reg, 16); 3137 sarl(reg, 16); 3138 } 3139 } 3140 3141 void MacroAssembler::testl(Address dst, int32_t imm32) { 3142 if (imm32 >= 0 && is8bit(imm32)) { 3143 testb(dst, imm32); 3144 } else { 3145 Assembler::testl(dst, imm32); 3146 } 3147 } 3148 3149 void MacroAssembler::testl(Register dst, int32_t imm32) { 3150 if (imm32 >= 0 && is8bit(imm32) && dst->has_byte_register()) { 3151 testb(dst, imm32); 3152 } else { 3153 Assembler::testl(dst, imm32); 3154 } 3155 } 3156 3157 void MacroAssembler::testl(Register dst, AddressLiteral src) { 3158 assert(always_reachable(src), "Address should be reachable"); 3159 testl(dst, as_Address(src)); 3160 } 3161 3162 #ifdef _LP64 3163 3164 void MacroAssembler::testq(Address dst, int32_t imm32) { 3165 if (imm32 >= 0) { 3166 testl(dst, imm32); 3167 } else { 3168 Assembler::testq(dst, imm32); 3169 } 3170 } 3171 3172 void MacroAssembler::testq(Register dst, int32_t imm32) { 3173 if (imm32 >= 0) { 3174 testl(dst, imm32); 3175 } else { 3176 Assembler::testq(dst, imm32); 3177 } 3178 } 3179 3180 #endif 3181 3182 void MacroAssembler::pcmpeqb(XMMRegister dst, XMMRegister src) { 3183 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15"); 3184 Assembler::pcmpeqb(dst, src); 3185 } 3186 3187 void MacroAssembler::pcmpeqw(XMMRegister dst, XMMRegister src) { 3188 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15"); 3189 Assembler::pcmpeqw(dst, src); 3190 } 3191 3192 void MacroAssembler::pcmpestri(XMMRegister dst, Address src, int imm8) { 3193 assert((dst->encoding() < 16),"XMM register should be 0-15"); 3194 Assembler::pcmpestri(dst, src, imm8); 3195 } 3196 3197 void MacroAssembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) { 3198 assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15"); 3199 Assembler::pcmpestri(dst, src, imm8); 3200 } 3201 3202 void MacroAssembler::pmovzxbw(XMMRegister dst, XMMRegister src) { 3203 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15"); 3204 Assembler::pmovzxbw(dst, src); 3205 } 3206 3207 void MacroAssembler::pmovzxbw(XMMRegister dst, Address src) { 3208 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15"); 3209 Assembler::pmovzxbw(dst, src); 3210 } 3211 3212 void MacroAssembler::pmovmskb(Register dst, XMMRegister src) { 3213 assert((src->encoding() < 16),"XMM register should be 0-15"); 3214 Assembler::pmovmskb(dst, src); 3215 } 3216 3217 void MacroAssembler::ptest(XMMRegister dst, XMMRegister src) { 3218 assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15"); 3219 Assembler::ptest(dst, src); 3220 } 3221 3222 void MacroAssembler::sqrtss(XMMRegister dst, AddressLiteral src, Register rscratch) { 3223 assert(rscratch != noreg || always_reachable(src), "missing"); 3224 3225 if (reachable(src)) { 3226 Assembler::sqrtss(dst, as_Address(src)); 3227 } else { 3228 lea(rscratch, src); 3229 Assembler::sqrtss(dst, Address(rscratch, 0)); 3230 } 3231 } 3232 3233 void MacroAssembler::subsd(XMMRegister dst, AddressLiteral src, Register rscratch) { 3234 assert(rscratch != noreg || always_reachable(src), "missing"); 3235 3236 if (reachable(src)) { 3237 Assembler::subsd(dst, as_Address(src)); 3238 } else { 3239 lea(rscratch, src); 3240 Assembler::subsd(dst, Address(rscratch, 0)); 3241 } 3242 } 3243 3244 void MacroAssembler::roundsd(XMMRegister dst, AddressLiteral src, int32_t rmode, Register rscratch) { 3245 assert(rscratch != noreg || always_reachable(src), "missing"); 3246 3247 if (reachable(src)) { 3248 Assembler::roundsd(dst, as_Address(src), rmode); 3249 } else { 3250 lea(rscratch, src); 3251 Assembler::roundsd(dst, Address(rscratch, 0), rmode); 3252 } 3253 } 3254 3255 void MacroAssembler::subss(XMMRegister dst, AddressLiteral src, Register rscratch) { 3256 assert(rscratch != noreg || always_reachable(src), "missing"); 3257 3258 if (reachable(src)) { 3259 Assembler::subss(dst, as_Address(src)); 3260 } else { 3261 lea(rscratch, src); 3262 Assembler::subss(dst, Address(rscratch, 0)); 3263 } 3264 } 3265 3266 void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src, Register rscratch) { 3267 assert(rscratch != noreg || always_reachable(src), "missing"); 3268 3269 if (reachable(src)) { 3270 Assembler::ucomisd(dst, as_Address(src)); 3271 } else { 3272 lea(rscratch, src); 3273 Assembler::ucomisd(dst, Address(rscratch, 0)); 3274 } 3275 } 3276 3277 void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src, Register rscratch) { 3278 assert(rscratch != noreg || always_reachable(src), "missing"); 3279 3280 if (reachable(src)) { 3281 Assembler::ucomiss(dst, as_Address(src)); 3282 } else { 3283 lea(rscratch, src); 3284 Assembler::ucomiss(dst, Address(rscratch, 0)); 3285 } 3286 } 3287 3288 void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src, Register rscratch) { 3289 assert(rscratch != noreg || always_reachable(src), "missing"); 3290 3291 // Used in sign-bit flipping with aligned address. 3292 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes"); 3293 if (reachable(src)) { 3294 Assembler::xorpd(dst, as_Address(src)); 3295 } else { 3296 lea(rscratch, src); 3297 Assembler::xorpd(dst, Address(rscratch, 0)); 3298 } 3299 } 3300 3301 void MacroAssembler::xorpd(XMMRegister dst, XMMRegister src) { 3302 if (UseAVX > 2 && !VM_Version::supports_avx512dq() && (dst->encoding() == src->encoding())) { 3303 Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit); 3304 } 3305 else { 3306 Assembler::xorpd(dst, src); 3307 } 3308 } 3309 3310 void MacroAssembler::xorps(XMMRegister dst, XMMRegister src) { 3311 if (UseAVX > 2 && !VM_Version::supports_avx512dq() && (dst->encoding() == src->encoding())) { 3312 Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit); 3313 } else { 3314 Assembler::xorps(dst, src); 3315 } 3316 } 3317 3318 void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src, Register rscratch) { 3319 assert(rscratch != noreg || always_reachable(src), "missing"); 3320 3321 // Used in sign-bit flipping with aligned address. 3322 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes"); 3323 if (reachable(src)) { 3324 Assembler::xorps(dst, as_Address(src)); 3325 } else { 3326 lea(rscratch, src); 3327 Assembler::xorps(dst, Address(rscratch, 0)); 3328 } 3329 } 3330 3331 void MacroAssembler::pshufb(XMMRegister dst, AddressLiteral src, Register rscratch) { 3332 assert(rscratch != noreg || always_reachable(src), "missing"); 3333 3334 // Used in sign-bit flipping with aligned address. 3335 bool aligned_adr = (((intptr_t)src.target() & 15) == 0); 3336 assert((UseAVX > 0) || aligned_adr, "SSE mode requires address alignment 16 bytes"); 3337 if (reachable(src)) { 3338 Assembler::pshufb(dst, as_Address(src)); 3339 } else { 3340 lea(rscratch, src); 3341 Assembler::pshufb(dst, Address(rscratch, 0)); 3342 } 3343 } 3344 3345 // AVX 3-operands instructions 3346 3347 void MacroAssembler::vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) { 3348 assert(rscratch != noreg || always_reachable(src), "missing"); 3349 3350 if (reachable(src)) { 3351 vaddsd(dst, nds, as_Address(src)); 3352 } else { 3353 lea(rscratch, src); 3354 vaddsd(dst, nds, Address(rscratch, 0)); 3355 } 3356 } 3357 3358 void MacroAssembler::vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) { 3359 assert(rscratch != noreg || always_reachable(src), "missing"); 3360 3361 if (reachable(src)) { 3362 vaddss(dst, nds, as_Address(src)); 3363 } else { 3364 lea(rscratch, src); 3365 vaddss(dst, nds, Address(rscratch, 0)); 3366 } 3367 } 3368 3369 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) { 3370 assert(UseAVX > 0, "requires some form of AVX"); 3371 assert(rscratch != noreg || always_reachable(src), "missing"); 3372 3373 if (reachable(src)) { 3374 Assembler::vpaddb(dst, nds, as_Address(src), vector_len); 3375 } else { 3376 lea(rscratch, src); 3377 Assembler::vpaddb(dst, nds, Address(rscratch, 0), vector_len); 3378 } 3379 } 3380 3381 void MacroAssembler::vpaddd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) { 3382 assert(UseAVX > 0, "requires some form of AVX"); 3383 assert(rscratch != noreg || always_reachable(src), "missing"); 3384 3385 if (reachable(src)) { 3386 Assembler::vpaddd(dst, nds, as_Address(src), vector_len); 3387 } else { 3388 lea(rscratch, src); 3389 Assembler::vpaddd(dst, nds, Address(rscratch, 0), vector_len); 3390 } 3391 } 3392 3393 void MacroAssembler::vabsss(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len, Register rscratch) { 3394 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15"); 3395 assert(rscratch != noreg || always_reachable(negate_field), "missing"); 3396 3397 vandps(dst, nds, negate_field, vector_len, rscratch); 3398 } 3399 3400 void MacroAssembler::vabssd(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len, Register rscratch) { 3401 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15"); 3402 assert(rscratch != noreg || always_reachable(negate_field), "missing"); 3403 3404 vandpd(dst, nds, negate_field, vector_len, rscratch); 3405 } 3406 3407 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 3408 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15"); 3409 Assembler::vpaddb(dst, nds, src, vector_len); 3410 } 3411 3412 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 3413 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15"); 3414 Assembler::vpaddb(dst, nds, src, vector_len); 3415 } 3416 3417 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 3418 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15"); 3419 Assembler::vpaddw(dst, nds, src, vector_len); 3420 } 3421 3422 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 3423 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15"); 3424 Assembler::vpaddw(dst, nds, src, vector_len); 3425 } 3426 3427 void MacroAssembler::vpand(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) { 3428 assert(rscratch != noreg || always_reachable(src), "missing"); 3429 3430 if (reachable(src)) { 3431 Assembler::vpand(dst, nds, as_Address(src), vector_len); 3432 } else { 3433 lea(rscratch, src); 3434 Assembler::vpand(dst, nds, Address(rscratch, 0), vector_len); 3435 } 3436 } 3437 3438 void MacroAssembler::vpbroadcastd(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) { 3439 assert(rscratch != noreg || always_reachable(src), "missing"); 3440 3441 if (reachable(src)) { 3442 Assembler::vpbroadcastd(dst, as_Address(src), vector_len); 3443 } else { 3444 lea(rscratch, src); 3445 Assembler::vpbroadcastd(dst, Address(rscratch, 0), vector_len); 3446 } 3447 } 3448 3449 void MacroAssembler::vpbroadcastq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) { 3450 assert(rscratch != noreg || always_reachable(src), "missing"); 3451 3452 if (reachable(src)) { 3453 Assembler::vpbroadcastq(dst, as_Address(src), vector_len); 3454 } else { 3455 lea(rscratch, src); 3456 Assembler::vpbroadcastq(dst, Address(rscratch, 0), vector_len); 3457 } 3458 } 3459 3460 void MacroAssembler::vbroadcastsd(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) { 3461 assert(rscratch != noreg || always_reachable(src), "missing"); 3462 3463 if (reachable(src)) { 3464 Assembler::vbroadcastsd(dst, as_Address(src), vector_len); 3465 } else { 3466 lea(rscratch, src); 3467 Assembler::vbroadcastsd(dst, Address(rscratch, 0), vector_len); 3468 } 3469 } 3470 3471 void MacroAssembler::vbroadcastss(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) { 3472 assert(rscratch != noreg || always_reachable(src), "missing"); 3473 3474 if (reachable(src)) { 3475 Assembler::vbroadcastss(dst, as_Address(src), vector_len); 3476 } else { 3477 lea(rscratch, src); 3478 Assembler::vbroadcastss(dst, Address(rscratch, 0), vector_len); 3479 } 3480 } 3481 3482 void MacroAssembler::vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 3483 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15"); 3484 Assembler::vpcmpeqb(dst, nds, src, vector_len); 3485 } 3486 3487 void MacroAssembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 3488 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15"); 3489 Assembler::vpcmpeqw(dst, nds, src, vector_len); 3490 } 3491 3492 void MacroAssembler::evpcmpeqd(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) { 3493 assert(rscratch != noreg || always_reachable(src), "missing"); 3494 3495 if (reachable(src)) { 3496 Assembler::evpcmpeqd(kdst, mask, nds, as_Address(src), vector_len); 3497 } else { 3498 lea(rscratch, src); 3499 Assembler::evpcmpeqd(kdst, mask, nds, Address(rscratch, 0), vector_len); 3500 } 3501 } 3502 3503 void MacroAssembler::evpcmpd(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src, 3504 int comparison, bool is_signed, int vector_len, Register rscratch) { 3505 assert(rscratch != noreg || always_reachable(src), "missing"); 3506 3507 if (reachable(src)) { 3508 Assembler::evpcmpd(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len); 3509 } else { 3510 lea(rscratch, src); 3511 Assembler::evpcmpd(kdst, mask, nds, Address(rscratch, 0), comparison, is_signed, vector_len); 3512 } 3513 } 3514 3515 void MacroAssembler::evpcmpq(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src, 3516 int comparison, bool is_signed, int vector_len, Register rscratch) { 3517 assert(rscratch != noreg || always_reachable(src), "missing"); 3518 3519 if (reachable(src)) { 3520 Assembler::evpcmpq(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len); 3521 } else { 3522 lea(rscratch, src); 3523 Assembler::evpcmpq(kdst, mask, nds, Address(rscratch, 0), comparison, is_signed, vector_len); 3524 } 3525 } 3526 3527 void MacroAssembler::evpcmpb(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src, 3528 int comparison, bool is_signed, int vector_len, Register rscratch) { 3529 assert(rscratch != noreg || always_reachable(src), "missing"); 3530 3531 if (reachable(src)) { 3532 Assembler::evpcmpb(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len); 3533 } else { 3534 lea(rscratch, src); 3535 Assembler::evpcmpb(kdst, mask, nds, Address(rscratch, 0), comparison, is_signed, vector_len); 3536 } 3537 } 3538 3539 void MacroAssembler::evpcmpw(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src, 3540 int comparison, bool is_signed, int vector_len, Register rscratch) { 3541 assert(rscratch != noreg || always_reachable(src), "missing"); 3542 3543 if (reachable(src)) { 3544 Assembler::evpcmpw(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len); 3545 } else { 3546 lea(rscratch, src); 3547 Assembler::evpcmpw(kdst, mask, nds, Address(rscratch, 0), comparison, is_signed, vector_len); 3548 } 3549 } 3550 3551 void MacroAssembler::vpcmpCC(XMMRegister dst, XMMRegister nds, XMMRegister src, int cond_encoding, Width width, int vector_len) { 3552 if (width == Assembler::Q) { 3553 Assembler::vpcmpCCq(dst, nds, src, cond_encoding, vector_len); 3554 } else { 3555 Assembler::vpcmpCCbwd(dst, nds, src, cond_encoding, vector_len); 3556 } 3557 } 3558 3559 void MacroAssembler::vpcmpCCW(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister xtmp, ComparisonPredicate cond, Width width, int vector_len) { 3560 int eq_cond_enc = 0x29; 3561 int gt_cond_enc = 0x37; 3562 if (width != Assembler::Q) { 3563 eq_cond_enc = 0x74 + width; 3564 gt_cond_enc = 0x64 + width; 3565 } 3566 switch (cond) { 3567 case eq: 3568 vpcmpCC(dst, nds, src, eq_cond_enc, width, vector_len); 3569 break; 3570 case neq: 3571 vpcmpCC(dst, nds, src, eq_cond_enc, width, vector_len); 3572 vallones(xtmp, vector_len); 3573 vpxor(dst, xtmp, dst, vector_len); 3574 break; 3575 case le: 3576 vpcmpCC(dst, nds, src, gt_cond_enc, width, vector_len); 3577 vallones(xtmp, vector_len); 3578 vpxor(dst, xtmp, dst, vector_len); 3579 break; 3580 case nlt: 3581 vpcmpCC(dst, src, nds, gt_cond_enc, width, vector_len); 3582 vallones(xtmp, vector_len); 3583 vpxor(dst, xtmp, dst, vector_len); 3584 break; 3585 case lt: 3586 vpcmpCC(dst, src, nds, gt_cond_enc, width, vector_len); 3587 break; 3588 case nle: 3589 vpcmpCC(dst, nds, src, gt_cond_enc, width, vector_len); 3590 break; 3591 default: 3592 assert(false, "Should not reach here"); 3593 } 3594 } 3595 3596 void MacroAssembler::vpmovzxbw(XMMRegister dst, Address src, int vector_len) { 3597 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15"); 3598 Assembler::vpmovzxbw(dst, src, vector_len); 3599 } 3600 3601 void MacroAssembler::vpmovmskb(Register dst, XMMRegister src, int vector_len) { 3602 assert((src->encoding() < 16),"XMM register should be 0-15"); 3603 Assembler::vpmovmskb(dst, src, vector_len); 3604 } 3605 3606 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 3607 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15"); 3608 Assembler::vpmullw(dst, nds, src, vector_len); 3609 } 3610 3611 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 3612 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15"); 3613 Assembler::vpmullw(dst, nds, src, vector_len); 3614 } 3615 3616 void MacroAssembler::vpmulld(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) { 3617 assert((UseAVX > 0), "AVX support is needed"); 3618 assert(rscratch != noreg || always_reachable(src), "missing"); 3619 3620 if (reachable(src)) { 3621 Assembler::vpmulld(dst, nds, as_Address(src), vector_len); 3622 } else { 3623 lea(rscratch, src); 3624 Assembler::vpmulld(dst, nds, Address(rscratch, 0), vector_len); 3625 } 3626 } 3627 3628 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 3629 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15"); 3630 Assembler::vpsubb(dst, nds, src, vector_len); 3631 } 3632 3633 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 3634 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15"); 3635 Assembler::vpsubb(dst, nds, src, vector_len); 3636 } 3637 3638 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 3639 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15"); 3640 Assembler::vpsubw(dst, nds, src, vector_len); 3641 } 3642 3643 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 3644 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15"); 3645 Assembler::vpsubw(dst, nds, src, vector_len); 3646 } 3647 3648 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) { 3649 assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15"); 3650 Assembler::vpsraw(dst, nds, shift, vector_len); 3651 } 3652 3653 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) { 3654 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15"); 3655 Assembler::vpsraw(dst, nds, shift, vector_len); 3656 } 3657 3658 void MacroAssembler::evpsraq(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) { 3659 assert(UseAVX > 2,""); 3660 if (!VM_Version::supports_avx512vl() && vector_len < 2) { 3661 vector_len = 2; 3662 } 3663 Assembler::evpsraq(dst, nds, shift, vector_len); 3664 } 3665 3666 void MacroAssembler::evpsraq(XMMRegister dst, XMMRegister nds, int shift, int vector_len) { 3667 assert(UseAVX > 2,""); 3668 if (!VM_Version::supports_avx512vl() && vector_len < 2) { 3669 vector_len = 2; 3670 } 3671 Assembler::evpsraq(dst, nds, shift, vector_len); 3672 } 3673 3674 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) { 3675 assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15"); 3676 Assembler::vpsrlw(dst, nds, shift, vector_len); 3677 } 3678 3679 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) { 3680 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15"); 3681 Assembler::vpsrlw(dst, nds, shift, vector_len); 3682 } 3683 3684 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) { 3685 assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15"); 3686 Assembler::vpsllw(dst, nds, shift, vector_len); 3687 } 3688 3689 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) { 3690 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15"); 3691 Assembler::vpsllw(dst, nds, shift, vector_len); 3692 } 3693 3694 void MacroAssembler::vptest(XMMRegister dst, XMMRegister src) { 3695 assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15"); 3696 Assembler::vptest(dst, src); 3697 } 3698 3699 void MacroAssembler::punpcklbw(XMMRegister dst, XMMRegister src) { 3700 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15"); 3701 Assembler::punpcklbw(dst, src); 3702 } 3703 3704 void MacroAssembler::pshufd(XMMRegister dst, Address src, int mode) { 3705 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15"); 3706 Assembler::pshufd(dst, src, mode); 3707 } 3708 3709 void MacroAssembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) { 3710 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15"); 3711 Assembler::pshuflw(dst, src, mode); 3712 } 3713 3714 void MacroAssembler::vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) { 3715 assert(rscratch != noreg || always_reachable(src), "missing"); 3716 3717 if (reachable(src)) { 3718 vandpd(dst, nds, as_Address(src), vector_len); 3719 } else { 3720 lea(rscratch, src); 3721 vandpd(dst, nds, Address(rscratch, 0), vector_len); 3722 } 3723 } 3724 3725 void MacroAssembler::vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) { 3726 assert(rscratch != noreg || always_reachable(src), "missing"); 3727 3728 if (reachable(src)) { 3729 vandps(dst, nds, as_Address(src), vector_len); 3730 } else { 3731 lea(rscratch, src); 3732 vandps(dst, nds, Address(rscratch, 0), vector_len); 3733 } 3734 } 3735 3736 void MacroAssembler::evpord(XMMRegister dst, KRegister mask, XMMRegister nds, AddressLiteral src, 3737 bool merge, int vector_len, Register rscratch) { 3738 assert(rscratch != noreg || always_reachable(src), "missing"); 3739 3740 if (reachable(src)) { 3741 Assembler::evpord(dst, mask, nds, as_Address(src), merge, vector_len); 3742 } else { 3743 lea(rscratch, src); 3744 Assembler::evpord(dst, mask, nds, Address(rscratch, 0), merge, vector_len); 3745 } 3746 } 3747 3748 void MacroAssembler::vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) { 3749 assert(rscratch != noreg || always_reachable(src), "missing"); 3750 3751 if (reachable(src)) { 3752 vdivsd(dst, nds, as_Address(src)); 3753 } else { 3754 lea(rscratch, src); 3755 vdivsd(dst, nds, Address(rscratch, 0)); 3756 } 3757 } 3758 3759 void MacroAssembler::vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) { 3760 assert(rscratch != noreg || always_reachable(src), "missing"); 3761 3762 if (reachable(src)) { 3763 vdivss(dst, nds, as_Address(src)); 3764 } else { 3765 lea(rscratch, src); 3766 vdivss(dst, nds, Address(rscratch, 0)); 3767 } 3768 } 3769 3770 void MacroAssembler::vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) { 3771 assert(rscratch != noreg || always_reachable(src), "missing"); 3772 3773 if (reachable(src)) { 3774 vmulsd(dst, nds, as_Address(src)); 3775 } else { 3776 lea(rscratch, src); 3777 vmulsd(dst, nds, Address(rscratch, 0)); 3778 } 3779 } 3780 3781 void MacroAssembler::vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) { 3782 assert(rscratch != noreg || always_reachable(src), "missing"); 3783 3784 if (reachable(src)) { 3785 vmulss(dst, nds, as_Address(src)); 3786 } else { 3787 lea(rscratch, src); 3788 vmulss(dst, nds, Address(rscratch, 0)); 3789 } 3790 } 3791 3792 void MacroAssembler::vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) { 3793 assert(rscratch != noreg || always_reachable(src), "missing"); 3794 3795 if (reachable(src)) { 3796 vsubsd(dst, nds, as_Address(src)); 3797 } else { 3798 lea(rscratch, src); 3799 vsubsd(dst, nds, Address(rscratch, 0)); 3800 } 3801 } 3802 3803 void MacroAssembler::vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) { 3804 assert(rscratch != noreg || always_reachable(src), "missing"); 3805 3806 if (reachable(src)) { 3807 vsubss(dst, nds, as_Address(src)); 3808 } else { 3809 lea(rscratch, src); 3810 vsubss(dst, nds, Address(rscratch, 0)); 3811 } 3812 } 3813 3814 void MacroAssembler::vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) { 3815 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15"); 3816 assert(rscratch != noreg || always_reachable(src), "missing"); 3817 3818 vxorps(dst, nds, src, Assembler::AVX_128bit, rscratch); 3819 } 3820 3821 void MacroAssembler::vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) { 3822 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15"); 3823 assert(rscratch != noreg || always_reachable(src), "missing"); 3824 3825 vxorpd(dst, nds, src, Assembler::AVX_128bit, rscratch); 3826 } 3827 3828 void MacroAssembler::vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) { 3829 assert(rscratch != noreg || always_reachable(src), "missing"); 3830 3831 if (reachable(src)) { 3832 vxorpd(dst, nds, as_Address(src), vector_len); 3833 } else { 3834 lea(rscratch, src); 3835 vxorpd(dst, nds, Address(rscratch, 0), vector_len); 3836 } 3837 } 3838 3839 void MacroAssembler::vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) { 3840 assert(rscratch != noreg || always_reachable(src), "missing"); 3841 3842 if (reachable(src)) { 3843 vxorps(dst, nds, as_Address(src), vector_len); 3844 } else { 3845 lea(rscratch, src); 3846 vxorps(dst, nds, Address(rscratch, 0), vector_len); 3847 } 3848 } 3849 3850 void MacroAssembler::vpxor(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) { 3851 assert(rscratch != noreg || always_reachable(src), "missing"); 3852 3853 if (UseAVX > 1 || (vector_len < 1)) { 3854 if (reachable(src)) { 3855 Assembler::vpxor(dst, nds, as_Address(src), vector_len); 3856 } else { 3857 lea(rscratch, src); 3858 Assembler::vpxor(dst, nds, Address(rscratch, 0), vector_len); 3859 } 3860 } else { 3861 MacroAssembler::vxorpd(dst, nds, src, vector_len, rscratch); 3862 } 3863 } 3864 3865 void MacroAssembler::vpermd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) { 3866 assert(rscratch != noreg || always_reachable(src), "missing"); 3867 3868 if (reachable(src)) { 3869 Assembler::vpermd(dst, nds, as_Address(src), vector_len); 3870 } else { 3871 lea(rscratch, src); 3872 Assembler::vpermd(dst, nds, Address(rscratch, 0), vector_len); 3873 } 3874 } 3875 3876 void MacroAssembler::clear_jobject_tag(Register possibly_non_local) { 3877 const int32_t inverted_mask = ~static_cast<int32_t>(JNIHandles::tag_mask); 3878 STATIC_ASSERT(inverted_mask == -4); // otherwise check this code 3879 // The inverted mask is sign-extended 3880 andptr(possibly_non_local, inverted_mask); 3881 } 3882 3883 void MacroAssembler::resolve_jobject(Register value, 3884 Register thread, 3885 Register tmp) { 3886 assert_different_registers(value, thread, tmp); 3887 Label done, tagged, weak_tagged; 3888 testptr(value, value); 3889 jcc(Assembler::zero, done); // Use null as-is. 3890 testptr(value, JNIHandles::tag_mask); // Test for tag. 3891 jcc(Assembler::notZero, tagged); 3892 3893 // Resolve local handle 3894 access_load_at(T_OBJECT, IN_NATIVE | AS_RAW, value, Address(value, 0), tmp, thread); 3895 verify_oop(value); 3896 jmp(done); 3897 3898 bind(tagged); 3899 testptr(value, JNIHandles::TypeTag::weak_global); // Test for weak tag. 3900 jcc(Assembler::notZero, weak_tagged); 3901 3902 // Resolve global handle 3903 access_load_at(T_OBJECT, IN_NATIVE, value, Address(value, -JNIHandles::TypeTag::global), tmp, thread); 3904 verify_oop(value); 3905 jmp(done); 3906 3907 bind(weak_tagged); 3908 // Resolve jweak. 3909 access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF, 3910 value, Address(value, -JNIHandles::TypeTag::weak_global), tmp, thread); 3911 verify_oop(value); 3912 3913 bind(done); 3914 } 3915 3916 void MacroAssembler::resolve_global_jobject(Register value, 3917 Register thread, 3918 Register tmp) { 3919 assert_different_registers(value, thread, tmp); 3920 Label done; 3921 3922 testptr(value, value); 3923 jcc(Assembler::zero, done); // Use null as-is. 3924 3925 #ifdef ASSERT 3926 { 3927 Label valid_global_tag; 3928 testptr(value, JNIHandles::TypeTag::global); // Test for global tag. 3929 jcc(Assembler::notZero, valid_global_tag); 3930 stop("non global jobject using resolve_global_jobject"); 3931 bind(valid_global_tag); 3932 } 3933 #endif 3934 3935 // Resolve global handle 3936 access_load_at(T_OBJECT, IN_NATIVE, value, Address(value, -JNIHandles::TypeTag::global), tmp, thread); 3937 verify_oop(value); 3938 3939 bind(done); 3940 } 3941 3942 void MacroAssembler::subptr(Register dst, int32_t imm32) { 3943 LP64_ONLY(subq(dst, imm32)) NOT_LP64(subl(dst, imm32)); 3944 } 3945 3946 // Force generation of a 4 byte immediate value even if it fits into 8bit 3947 void MacroAssembler::subptr_imm32(Register dst, int32_t imm32) { 3948 LP64_ONLY(subq_imm32(dst, imm32)) NOT_LP64(subl_imm32(dst, imm32)); 3949 } 3950 3951 void MacroAssembler::subptr(Register dst, Register src) { 3952 LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); 3953 } 3954 3955 // C++ bool manipulation 3956 void MacroAssembler::testbool(Register dst) { 3957 if(sizeof(bool) == 1) 3958 testb(dst, 0xff); 3959 else if(sizeof(bool) == 2) { 3960 // testw implementation needed for two byte bools 3961 ShouldNotReachHere(); 3962 } else if(sizeof(bool) == 4) 3963 testl(dst, dst); 3964 else 3965 // unsupported 3966 ShouldNotReachHere(); 3967 } 3968 3969 void MacroAssembler::testptr(Register dst, Register src) { 3970 LP64_ONLY(testq(dst, src)) NOT_LP64(testl(dst, src)); 3971 } 3972 3973 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes. 3974 void MacroAssembler::tlab_allocate(Register thread, Register obj, 3975 Register var_size_in_bytes, 3976 int con_size_in_bytes, 3977 Register t1, 3978 Register t2, 3979 Label& slow_case) { 3980 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler(); 3981 bs->tlab_allocate(this, thread, obj, var_size_in_bytes, con_size_in_bytes, t1, t2, slow_case); 3982 } 3983 3984 RegSet MacroAssembler::call_clobbered_gp_registers() { 3985 RegSet regs; 3986 #ifdef _LP64 3987 regs += RegSet::of(rax, rcx, rdx); 3988 #ifndef WINDOWS 3989 regs += RegSet::of(rsi, rdi); 3990 #endif 3991 regs += RegSet::range(r8, r11); 3992 #else 3993 regs += RegSet::of(rax, rcx, rdx); 3994 #endif 3995 return regs; 3996 } 3997 3998 XMMRegSet MacroAssembler::call_clobbered_xmm_registers() { 3999 int num_xmm_registers = XMMRegister::available_xmm_registers(); 4000 #if defined(WINDOWS) && defined(_LP64) 4001 XMMRegSet result = XMMRegSet::range(xmm0, xmm5); 4002 if (num_xmm_registers > 16) { 4003 result += XMMRegSet::range(xmm16, as_XMMRegister(num_xmm_registers - 1)); 4004 } 4005 return result; 4006 #else 4007 return XMMRegSet::range(xmm0, as_XMMRegister(num_xmm_registers - 1)); 4008 #endif 4009 } 4010 4011 static int FPUSaveAreaSize = align_up(108, StackAlignmentInBytes); // 108 bytes needed for FPU state by fsave/frstor 4012 4013 #ifndef _LP64 4014 static bool use_x87_registers() { return UseSSE < 2; } 4015 #endif 4016 static bool use_xmm_registers() { return UseSSE >= 1; } 4017 4018 // C1 only ever uses the first double/float of the XMM register. 4019 static int xmm_save_size() { return UseSSE >= 2 ? sizeof(double) : sizeof(float); } 4020 4021 static void save_xmm_register(MacroAssembler* masm, int offset, XMMRegister reg) { 4022 if (UseSSE == 1) { 4023 masm->movflt(Address(rsp, offset), reg); 4024 } else { 4025 masm->movdbl(Address(rsp, offset), reg); 4026 } 4027 } 4028 4029 static void restore_xmm_register(MacroAssembler* masm, int offset, XMMRegister reg) { 4030 if (UseSSE == 1) { 4031 masm->movflt(reg, Address(rsp, offset)); 4032 } else { 4033 masm->movdbl(reg, Address(rsp, offset)); 4034 } 4035 } 4036 4037 int register_section_sizes(RegSet gp_registers, XMMRegSet xmm_registers, bool save_fpu, 4038 int& gp_area_size, int& fp_area_size, int& xmm_area_size) { 4039 4040 gp_area_size = align_up(gp_registers.size() * Register::max_slots_per_register * VMRegImpl::stack_slot_size, 4041 StackAlignmentInBytes); 4042 #ifdef _LP64 4043 fp_area_size = 0; 4044 #else 4045 fp_area_size = (save_fpu && use_x87_registers()) ? FPUSaveAreaSize : 0; 4046 #endif 4047 xmm_area_size = (save_fpu && use_xmm_registers()) ? xmm_registers.size() * xmm_save_size() : 0; 4048 4049 return gp_area_size + fp_area_size + xmm_area_size; 4050 } 4051 4052 void MacroAssembler::push_call_clobbered_registers_except(RegSet exclude, bool save_fpu) { 4053 block_comment("push_call_clobbered_registers start"); 4054 // Regular registers 4055 RegSet gp_registers_to_push = call_clobbered_gp_registers() - exclude; 4056 4057 int gp_area_size; 4058 int fp_area_size; 4059 int xmm_area_size; 4060 int total_save_size = register_section_sizes(gp_registers_to_push, call_clobbered_xmm_registers(), save_fpu, 4061 gp_area_size, fp_area_size, xmm_area_size); 4062 subptr(rsp, total_save_size); 4063 4064 push_set(gp_registers_to_push, 0); 4065 4066 #ifndef _LP64 4067 if (save_fpu && use_x87_registers()) { 4068 fnsave(Address(rsp, gp_area_size)); 4069 fwait(); 4070 } 4071 #endif 4072 if (save_fpu && use_xmm_registers()) { 4073 push_set(call_clobbered_xmm_registers(), gp_area_size + fp_area_size); 4074 } 4075 4076 block_comment("push_call_clobbered_registers end"); 4077 } 4078 4079 void MacroAssembler::pop_call_clobbered_registers_except(RegSet exclude, bool restore_fpu) { 4080 block_comment("pop_call_clobbered_registers start"); 4081 4082 RegSet gp_registers_to_pop = call_clobbered_gp_registers() - exclude; 4083 4084 int gp_area_size; 4085 int fp_area_size; 4086 int xmm_area_size; 4087 int total_save_size = register_section_sizes(gp_registers_to_pop, call_clobbered_xmm_registers(), restore_fpu, 4088 gp_area_size, fp_area_size, xmm_area_size); 4089 4090 if (restore_fpu && use_xmm_registers()) { 4091 pop_set(call_clobbered_xmm_registers(), gp_area_size + fp_area_size); 4092 } 4093 #ifndef _LP64 4094 if (restore_fpu && use_x87_registers()) { 4095 frstor(Address(rsp, gp_area_size)); 4096 } 4097 #endif 4098 4099 pop_set(gp_registers_to_pop, 0); 4100 4101 addptr(rsp, total_save_size); 4102 4103 vzeroupper(); 4104 4105 block_comment("pop_call_clobbered_registers end"); 4106 } 4107 4108 void MacroAssembler::push_set(XMMRegSet set, int offset) { 4109 assert(is_aligned(set.size() * xmm_save_size(), StackAlignmentInBytes), "must be"); 4110 int spill_offset = offset; 4111 4112 for (RegSetIterator<XMMRegister> it = set.begin(); *it != xnoreg; ++it) { 4113 save_xmm_register(this, spill_offset, *it); 4114 spill_offset += xmm_save_size(); 4115 } 4116 } 4117 4118 void MacroAssembler::pop_set(XMMRegSet set, int offset) { 4119 int restore_size = set.size() * xmm_save_size(); 4120 assert(is_aligned(restore_size, StackAlignmentInBytes), "must be"); 4121 4122 int restore_offset = offset + restore_size - xmm_save_size(); 4123 4124 for (ReverseRegSetIterator<XMMRegister> it = set.rbegin(); *it != xnoreg; ++it) { 4125 restore_xmm_register(this, restore_offset, *it); 4126 restore_offset -= xmm_save_size(); 4127 } 4128 } 4129 4130 void MacroAssembler::push_set(RegSet set, int offset) { 4131 int spill_offset; 4132 if (offset == -1) { 4133 int register_push_size = set.size() * Register::max_slots_per_register * VMRegImpl::stack_slot_size; 4134 int aligned_size = align_up(register_push_size, StackAlignmentInBytes); 4135 subptr(rsp, aligned_size); 4136 spill_offset = 0; 4137 } else { 4138 spill_offset = offset; 4139 } 4140 4141 for (RegSetIterator<Register> it = set.begin(); *it != noreg; ++it) { 4142 movptr(Address(rsp, spill_offset), *it); 4143 spill_offset += Register::max_slots_per_register * VMRegImpl::stack_slot_size; 4144 } 4145 } 4146 4147 void MacroAssembler::pop_set(RegSet set, int offset) { 4148 4149 int gp_reg_size = Register::max_slots_per_register * VMRegImpl::stack_slot_size; 4150 int restore_size = set.size() * gp_reg_size; 4151 int aligned_size = align_up(restore_size, StackAlignmentInBytes); 4152 4153 int restore_offset; 4154 if (offset == -1) { 4155 restore_offset = restore_size - gp_reg_size; 4156 } else { 4157 restore_offset = offset + restore_size - gp_reg_size; 4158 } 4159 for (ReverseRegSetIterator<Register> it = set.rbegin(); *it != noreg; ++it) { 4160 movptr(*it, Address(rsp, restore_offset)); 4161 restore_offset -= gp_reg_size; 4162 } 4163 4164 if (offset == -1) { 4165 addptr(rsp, aligned_size); 4166 } 4167 } 4168 4169 // Preserves the contents of address, destroys the contents length_in_bytes and temp. 4170 void MacroAssembler::zero_memory(Register address, Register length_in_bytes, int offset_in_bytes, Register temp) { 4171 assert(address != length_in_bytes && address != temp && temp != length_in_bytes, "registers must be different"); 4172 assert((offset_in_bytes & (BytesPerWord - 1)) == 0, "offset must be a multiple of BytesPerWord"); 4173 Label done; 4174 4175 testptr(length_in_bytes, length_in_bytes); 4176 jcc(Assembler::zero, done); 4177 4178 // initialize topmost word, divide index by 2, check if odd and test if zero 4179 // note: for the remaining code to work, index must be a multiple of BytesPerWord 4180 #ifdef ASSERT 4181 { 4182 Label L; 4183 testptr(length_in_bytes, BytesPerWord - 1); 4184 jcc(Assembler::zero, L); 4185 stop("length must be a multiple of BytesPerWord"); 4186 bind(L); 4187 } 4188 #endif 4189 Register index = length_in_bytes; 4190 xorptr(temp, temp); // use _zero reg to clear memory (shorter code) 4191 if (UseIncDec) { 4192 shrptr(index, 3); // divide by 8/16 and set carry flag if bit 2 was set 4193 } else { 4194 shrptr(index, 2); // use 2 instructions to avoid partial flag stall 4195 shrptr(index, 1); 4196 } 4197 #ifndef _LP64 4198 // index could have not been a multiple of 8 (i.e., bit 2 was set) 4199 { 4200 Label even; 4201 // note: if index was a multiple of 8, then it cannot 4202 // be 0 now otherwise it must have been 0 before 4203 // => if it is even, we don't need to check for 0 again 4204 jcc(Assembler::carryClear, even); 4205 // clear topmost word (no jump would be needed if conditional assignment worked here) 4206 movptr(Address(address, index, Address::times_8, offset_in_bytes - 0*BytesPerWord), temp); 4207 // index could be 0 now, must check again 4208 jcc(Assembler::zero, done); 4209 bind(even); 4210 } 4211 #endif // !_LP64 4212 // initialize remaining object fields: index is a multiple of 2 now 4213 { 4214 Label loop; 4215 bind(loop); 4216 movptr(Address(address, index, Address::times_8, offset_in_bytes - 1*BytesPerWord), temp); 4217 NOT_LP64(movptr(Address(address, index, Address::times_8, offset_in_bytes - 2*BytesPerWord), temp);) 4218 decrement(index); 4219 jcc(Assembler::notZero, loop); 4220 } 4221 4222 bind(done); 4223 } 4224 4225 // Look up the method for a megamorphic invokeinterface call. 4226 // The target method is determined by <intf_klass, itable_index>. 4227 // The receiver klass is in recv_klass. 4228 // On success, the result will be in method_result, and execution falls through. 4229 // On failure, execution transfers to the given label. 4230 void MacroAssembler::lookup_interface_method(Register recv_klass, 4231 Register intf_klass, 4232 RegisterOrConstant itable_index, 4233 Register method_result, 4234 Register scan_temp, 4235 Label& L_no_such_interface, 4236 bool return_method) { 4237 assert_different_registers(recv_klass, intf_klass, scan_temp); 4238 assert_different_registers(method_result, intf_klass, scan_temp); 4239 assert(recv_klass != method_result || !return_method, 4240 "recv_klass can be destroyed when method isn't needed"); 4241 4242 assert(itable_index.is_constant() || itable_index.as_register() == method_result, 4243 "caller must use same register for non-constant itable index as for method"); 4244 4245 // Compute start of first itableOffsetEntry (which is at the end of the vtable) 4246 int vtable_base = in_bytes(Klass::vtable_start_offset()); 4247 int itentry_off = in_bytes(itableMethodEntry::method_offset()); 4248 int scan_step = itableOffsetEntry::size() * wordSize; 4249 int vte_size = vtableEntry::size_in_bytes(); 4250 Address::ScaleFactor times_vte_scale = Address::times_ptr; 4251 assert(vte_size == wordSize, "else adjust times_vte_scale"); 4252 4253 movl(scan_temp, Address(recv_klass, Klass::vtable_length_offset())); 4254 4255 // %%% Could store the aligned, prescaled offset in the klassoop. 4256 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base)); 4257 4258 if (return_method) { 4259 // Adjust recv_klass by scaled itable_index, so we can free itable_index. 4260 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below"); 4261 lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off)); 4262 } 4263 4264 // for (scan = klass->itable(); scan->interface() != nullptr; scan += scan_step) { 4265 // if (scan->interface() == intf) { 4266 // result = (klass + scan->offset() + itable_index); 4267 // } 4268 // } 4269 Label search, found_method; 4270 4271 for (int peel = 1; peel >= 0; peel--) { 4272 movptr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset())); 4273 cmpptr(intf_klass, method_result); 4274 4275 if (peel) { 4276 jccb(Assembler::equal, found_method); 4277 } else { 4278 jccb(Assembler::notEqual, search); 4279 // (invert the test to fall through to found_method...) 4280 } 4281 4282 if (!peel) break; 4283 4284 bind(search); 4285 4286 // Check that the previous entry is non-null. A null entry means that 4287 // the receiver class doesn't implement the interface, and wasn't the 4288 // same as when the caller was compiled. 4289 testptr(method_result, method_result); 4290 jcc(Assembler::zero, L_no_such_interface); 4291 addptr(scan_temp, scan_step); 4292 } 4293 4294 bind(found_method); 4295 4296 if (return_method) { 4297 // Got a hit. 4298 movl(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset())); 4299 movptr(method_result, Address(recv_klass, scan_temp, Address::times_1)); 4300 } 4301 } 4302 4303 // Look up the method for a megamorphic invokeinterface call in a single pass over itable: 4304 // - check recv_klass (actual object class) is a subtype of resolved_klass from CompiledICHolder 4305 // - find a holder_klass (class that implements the method) vtable offset and get the method from vtable by index 4306 // The target method is determined by <holder_klass, itable_index>. 4307 // The receiver klass is in recv_klass. 4308 // On success, the result will be in method_result, and execution falls through. 4309 // On failure, execution transfers to the given label. 4310 void MacroAssembler::lookup_interface_method_stub(Register recv_klass, 4311 Register holder_klass, 4312 Register resolved_klass, 4313 Register method_result, 4314 Register scan_temp, 4315 Register temp_reg2, 4316 Register receiver, 4317 int itable_index, 4318 Label& L_no_such_interface) { 4319 assert_different_registers(recv_klass, method_result, holder_klass, resolved_klass, scan_temp, temp_reg2, receiver); 4320 Register temp_itbl_klass = method_result; 4321 Register temp_reg = (temp_reg2 == noreg ? recv_klass : temp_reg2); // reuse recv_klass register on 32-bit x86 impl 4322 4323 int vtable_base = in_bytes(Klass::vtable_start_offset()); 4324 int itentry_off = in_bytes(itableMethodEntry::method_offset()); 4325 int scan_step = itableOffsetEntry::size() * wordSize; 4326 int vte_size = vtableEntry::size_in_bytes(); 4327 int ioffset = in_bytes(itableOffsetEntry::interface_offset()); 4328 int ooffset = in_bytes(itableOffsetEntry::offset_offset()); 4329 Address::ScaleFactor times_vte_scale = Address::times_ptr; 4330 assert(vte_size == wordSize, "adjust times_vte_scale"); 4331 4332 Label L_loop_scan_resolved_entry, L_resolved_found, L_holder_found; 4333 4334 // temp_itbl_klass = recv_klass.itable[0] 4335 // scan_temp = &recv_klass.itable[0] + step 4336 movl(scan_temp, Address(recv_klass, Klass::vtable_length_offset())); 4337 movptr(temp_itbl_klass, Address(recv_klass, scan_temp, times_vte_scale, vtable_base + ioffset)); 4338 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base + ioffset + scan_step)); 4339 xorptr(temp_reg, temp_reg); 4340 4341 // Initial checks: 4342 // - if (holder_klass != resolved_klass), go to "scan for resolved" 4343 // - if (itable[0] == 0), no such interface 4344 // - if (itable[0] == holder_klass), shortcut to "holder found" 4345 cmpptr(holder_klass, resolved_klass); 4346 jccb(Assembler::notEqual, L_loop_scan_resolved_entry); 4347 testptr(temp_itbl_klass, temp_itbl_klass); 4348 jccb(Assembler::zero, L_no_such_interface); 4349 cmpptr(holder_klass, temp_itbl_klass); 4350 jccb(Assembler::equal, L_holder_found); 4351 4352 // Loop: Look for holder_klass record in itable 4353 // do { 4354 // tmp = itable[index]; 4355 // index += step; 4356 // if (tmp == holder_klass) { 4357 // goto L_holder_found; // Found! 4358 // } 4359 // } while (tmp != 0); 4360 // goto L_no_such_interface // Not found. 4361 Label L_scan_holder; 4362 bind(L_scan_holder); 4363 movptr(temp_itbl_klass, Address(scan_temp, 0)); 4364 addptr(scan_temp, scan_step); 4365 cmpptr(holder_klass, temp_itbl_klass); 4366 jccb(Assembler::equal, L_holder_found); 4367 testptr(temp_itbl_klass, temp_itbl_klass); 4368 jccb(Assembler::notZero, L_scan_holder); 4369 4370 jmpb(L_no_such_interface); 4371 4372 // Loop: Look for resolved_class record in itable 4373 // do { 4374 // tmp = itable[index]; 4375 // index += step; 4376 // if (tmp == holder_klass) { 4377 // // Also check if we have met a holder klass 4378 // holder_tmp = itable[index-step-ioffset]; 4379 // } 4380 // if (tmp == resolved_klass) { 4381 // goto L_resolved_found; // Found! 4382 // } 4383 // } while (tmp != 0); 4384 // goto L_no_such_interface // Not found. 4385 // 4386 Label L_loop_scan_resolved; 4387 bind(L_loop_scan_resolved); 4388 movptr(temp_itbl_klass, Address(scan_temp, 0)); 4389 addptr(scan_temp, scan_step); 4390 bind(L_loop_scan_resolved_entry); 4391 cmpptr(holder_klass, temp_itbl_klass); 4392 cmovl(Assembler::equal, temp_reg, Address(scan_temp, ooffset - ioffset - scan_step)); 4393 cmpptr(resolved_klass, temp_itbl_klass); 4394 jccb(Assembler::equal, L_resolved_found); 4395 testptr(temp_itbl_klass, temp_itbl_klass); 4396 jccb(Assembler::notZero, L_loop_scan_resolved); 4397 4398 jmpb(L_no_such_interface); 4399 4400 Label L_ready; 4401 4402 // See if we already have a holder klass. If not, go and scan for it. 4403 bind(L_resolved_found); 4404 testptr(temp_reg, temp_reg); 4405 jccb(Assembler::zero, L_scan_holder); 4406 jmpb(L_ready); 4407 4408 bind(L_holder_found); 4409 movl(temp_reg, Address(scan_temp, ooffset - ioffset - scan_step)); 4410 4411 // Finally, temp_reg contains holder_klass vtable offset 4412 bind(L_ready); 4413 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below"); 4414 if (temp_reg2 == noreg) { // recv_klass register is clobbered for 32-bit x86 impl 4415 load_klass(scan_temp, receiver, noreg); 4416 movptr(method_result, Address(scan_temp, temp_reg, Address::times_1, itable_index * wordSize + itentry_off)); 4417 } else { 4418 movptr(method_result, Address(recv_klass, temp_reg, Address::times_1, itable_index * wordSize + itentry_off)); 4419 } 4420 } 4421 4422 4423 // virtual method calling 4424 void MacroAssembler::lookup_virtual_method(Register recv_klass, 4425 RegisterOrConstant vtable_index, 4426 Register method_result) { 4427 const ByteSize base = Klass::vtable_start_offset(); 4428 assert(vtableEntry::size() * wordSize == wordSize, "else adjust the scaling in the code below"); 4429 Address vtable_entry_addr(recv_klass, 4430 vtable_index, Address::times_ptr, 4431 base + vtableEntry::method_offset()); 4432 movptr(method_result, vtable_entry_addr); 4433 } 4434 4435 4436 void MacroAssembler::check_klass_subtype(Register sub_klass, 4437 Register super_klass, 4438 Register temp_reg, 4439 Label& L_success) { 4440 Label L_failure; 4441 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, nullptr); 4442 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, nullptr); 4443 bind(L_failure); 4444 } 4445 4446 4447 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass, 4448 Register super_klass, 4449 Register temp_reg, 4450 Label* L_success, 4451 Label* L_failure, 4452 Label* L_slow_path, 4453 RegisterOrConstant super_check_offset) { 4454 assert_different_registers(sub_klass, super_klass, temp_reg); 4455 bool must_load_sco = (super_check_offset.constant_or_zero() == -1); 4456 if (super_check_offset.is_register()) { 4457 assert_different_registers(sub_klass, super_klass, 4458 super_check_offset.as_register()); 4459 } else if (must_load_sco) { 4460 assert(temp_reg != noreg, "supply either a temp or a register offset"); 4461 } 4462 4463 Label L_fallthrough; 4464 int label_nulls = 0; 4465 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; } 4466 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; } 4467 if (L_slow_path == nullptr) { L_slow_path = &L_fallthrough; label_nulls++; } 4468 assert(label_nulls <= 1, "at most one null in the batch"); 4469 4470 int sc_offset = in_bytes(Klass::secondary_super_cache_offset()); 4471 int sco_offset = in_bytes(Klass::super_check_offset_offset()); 4472 Address super_check_offset_addr(super_klass, sco_offset); 4473 4474 // Hacked jcc, which "knows" that L_fallthrough, at least, is in 4475 // range of a jccb. If this routine grows larger, reconsider at 4476 // least some of these. 4477 #define local_jcc(assembler_cond, label) \ 4478 if (&(label) == &L_fallthrough) jccb(assembler_cond, label); \ 4479 else jcc( assembler_cond, label) /*omit semi*/ 4480 4481 // Hacked jmp, which may only be used just before L_fallthrough. 4482 #define final_jmp(label) \ 4483 if (&(label) == &L_fallthrough) { /*do nothing*/ } \ 4484 else jmp(label) /*omit semi*/ 4485 4486 // If the pointers are equal, we are done (e.g., String[] elements). 4487 // This self-check enables sharing of secondary supertype arrays among 4488 // non-primary types such as array-of-interface. Otherwise, each such 4489 // type would need its own customized SSA. 4490 // We move this check to the front of the fast path because many 4491 // type checks are in fact trivially successful in this manner, 4492 // so we get a nicely predicted branch right at the start of the check. 4493 cmpptr(sub_klass, super_klass); 4494 local_jcc(Assembler::equal, *L_success); 4495 4496 // Check the supertype display: 4497 if (must_load_sco) { 4498 // Positive movl does right thing on LP64. 4499 movl(temp_reg, super_check_offset_addr); 4500 super_check_offset = RegisterOrConstant(temp_reg); 4501 } 4502 Address super_check_addr(sub_klass, super_check_offset, Address::times_1, 0); 4503 cmpptr(super_klass, super_check_addr); // load displayed supertype 4504 4505 // This check has worked decisively for primary supers. 4506 // Secondary supers are sought in the super_cache ('super_cache_addr'). 4507 // (Secondary supers are interfaces and very deeply nested subtypes.) 4508 // This works in the same check above because of a tricky aliasing 4509 // between the super_cache and the primary super display elements. 4510 // (The 'super_check_addr' can address either, as the case requires.) 4511 // Note that the cache is updated below if it does not help us find 4512 // what we need immediately. 4513 // So if it was a primary super, we can just fail immediately. 4514 // Otherwise, it's the slow path for us (no success at this point). 4515 4516 if (super_check_offset.is_register()) { 4517 local_jcc(Assembler::equal, *L_success); 4518 cmpl(super_check_offset.as_register(), sc_offset); 4519 if (L_failure == &L_fallthrough) { 4520 local_jcc(Assembler::equal, *L_slow_path); 4521 } else { 4522 local_jcc(Assembler::notEqual, *L_failure); 4523 final_jmp(*L_slow_path); 4524 } 4525 } else if (super_check_offset.as_constant() == sc_offset) { 4526 // Need a slow path; fast failure is impossible. 4527 if (L_slow_path == &L_fallthrough) { 4528 local_jcc(Assembler::equal, *L_success); 4529 } else { 4530 local_jcc(Assembler::notEqual, *L_slow_path); 4531 final_jmp(*L_success); 4532 } 4533 } else { 4534 // No slow path; it's a fast decision. 4535 if (L_failure == &L_fallthrough) { 4536 local_jcc(Assembler::equal, *L_success); 4537 } else { 4538 local_jcc(Assembler::notEqual, *L_failure); 4539 final_jmp(*L_success); 4540 } 4541 } 4542 4543 bind(L_fallthrough); 4544 4545 #undef local_jcc 4546 #undef final_jmp 4547 } 4548 4549 4550 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass, 4551 Register super_klass, 4552 Register temp_reg, 4553 Register temp2_reg, 4554 Label* L_success, 4555 Label* L_failure, 4556 bool set_cond_codes) { 4557 assert_different_registers(sub_klass, super_klass, temp_reg); 4558 if (temp2_reg != noreg) 4559 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg); 4560 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg) 4561 4562 Label L_fallthrough; 4563 int label_nulls = 0; 4564 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; } 4565 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; } 4566 assert(label_nulls <= 1, "at most one null in the batch"); 4567 4568 // a couple of useful fields in sub_klass: 4569 int ss_offset = in_bytes(Klass::secondary_supers_offset()); 4570 int sc_offset = in_bytes(Klass::secondary_super_cache_offset()); 4571 Address secondary_supers_addr(sub_klass, ss_offset); 4572 Address super_cache_addr( sub_klass, sc_offset); 4573 4574 // Do a linear scan of the secondary super-klass chain. 4575 // This code is rarely used, so simplicity is a virtue here. 4576 // The repne_scan instruction uses fixed registers, which we must spill. 4577 // Don't worry too much about pre-existing connections with the input regs. 4578 4579 assert(sub_klass != rax, "killed reg"); // killed by mov(rax, super) 4580 assert(sub_klass != rcx, "killed reg"); // killed by lea(rcx, &pst_counter) 4581 4582 // Get super_klass value into rax (even if it was in rdi or rcx). 4583 bool pushed_rax = false, pushed_rcx = false, pushed_rdi = false; 4584 if (super_klass != rax) { 4585 if (!IS_A_TEMP(rax)) { push(rax); pushed_rax = true; } 4586 mov(rax, super_klass); 4587 } 4588 if (!IS_A_TEMP(rcx)) { push(rcx); pushed_rcx = true; } 4589 if (!IS_A_TEMP(rdi)) { push(rdi); pushed_rdi = true; } 4590 4591 #ifndef PRODUCT 4592 int* pst_counter = &SharedRuntime::_partial_subtype_ctr; 4593 ExternalAddress pst_counter_addr((address) pst_counter); 4594 NOT_LP64( incrementl(pst_counter_addr) ); 4595 LP64_ONLY( lea(rcx, pst_counter_addr) ); 4596 LP64_ONLY( incrementl(Address(rcx, 0)) ); 4597 #endif //PRODUCT 4598 4599 // We will consult the secondary-super array. 4600 movptr(rdi, secondary_supers_addr); 4601 // Load the array length. (Positive movl does right thing on LP64.) 4602 movl(rcx, Address(rdi, Array<Klass*>::length_offset_in_bytes())); 4603 // Skip to start of data. 4604 addptr(rdi, Array<Klass*>::base_offset_in_bytes()); 4605 4606 // Scan RCX words at [RDI] for an occurrence of RAX. 4607 // Set NZ/Z based on last compare. 4608 // Z flag value will not be set by 'repne' if RCX == 0 since 'repne' does 4609 // not change flags (only scas instruction which is repeated sets flags). 4610 // Set Z = 0 (not equal) before 'repne' to indicate that class was not found. 4611 4612 testptr(rax,rax); // Set Z = 0 4613 repne_scan(); 4614 4615 // Unspill the temp. registers: 4616 if (pushed_rdi) pop(rdi); 4617 if (pushed_rcx) pop(rcx); 4618 if (pushed_rax) pop(rax); 4619 4620 if (set_cond_codes) { 4621 // Special hack for the AD files: rdi is guaranteed non-zero. 4622 assert(!pushed_rdi, "rdi must be left non-null"); 4623 // Also, the condition codes are properly set Z/NZ on succeed/failure. 4624 } 4625 4626 if (L_failure == &L_fallthrough) 4627 jccb(Assembler::notEqual, *L_failure); 4628 else jcc(Assembler::notEqual, *L_failure); 4629 4630 // Success. Cache the super we found and proceed in triumph. 4631 movptr(super_cache_addr, super_klass); 4632 4633 if (L_success != &L_fallthrough) { 4634 jmp(*L_success); 4635 } 4636 4637 #undef IS_A_TEMP 4638 4639 bind(L_fallthrough); 4640 } 4641 4642 void MacroAssembler::clinit_barrier(Register klass, Register thread, Label* L_fast_path, Label* L_slow_path) { 4643 assert(L_fast_path != nullptr || L_slow_path != nullptr, "at least one is required"); 4644 4645 Label L_fallthrough; 4646 if (L_fast_path == nullptr) { 4647 L_fast_path = &L_fallthrough; 4648 } else if (L_slow_path == nullptr) { 4649 L_slow_path = &L_fallthrough; 4650 } 4651 4652 // Fast path check: class is fully initialized 4653 cmpb(Address(klass, InstanceKlass::init_state_offset()), InstanceKlass::fully_initialized); 4654 jcc(Assembler::equal, *L_fast_path); 4655 4656 // Fast path check: current thread is initializer thread 4657 cmpptr(thread, Address(klass, InstanceKlass::init_thread_offset())); 4658 if (L_slow_path == &L_fallthrough) { 4659 jcc(Assembler::equal, *L_fast_path); 4660 bind(*L_slow_path); 4661 } else if (L_fast_path == &L_fallthrough) { 4662 jcc(Assembler::notEqual, *L_slow_path); 4663 bind(*L_fast_path); 4664 } else { 4665 Unimplemented(); 4666 } 4667 } 4668 4669 void MacroAssembler::cmov32(Condition cc, Register dst, Address src) { 4670 if (VM_Version::supports_cmov()) { 4671 cmovl(cc, dst, src); 4672 } else { 4673 Label L; 4674 jccb(negate_condition(cc), L); 4675 movl(dst, src); 4676 bind(L); 4677 } 4678 } 4679 4680 void MacroAssembler::cmov32(Condition cc, Register dst, Register src) { 4681 if (VM_Version::supports_cmov()) { 4682 cmovl(cc, dst, src); 4683 } else { 4684 Label L; 4685 jccb(negate_condition(cc), L); 4686 movl(dst, src); 4687 bind(L); 4688 } 4689 } 4690 4691 void MacroAssembler::_verify_oop(Register reg, const char* s, const char* file, int line) { 4692 if (!VerifyOops) return; 4693 4694 BLOCK_COMMENT("verify_oop {"); 4695 #ifdef _LP64 4696 push(rscratch1); 4697 #endif 4698 push(rax); // save rax 4699 push(reg); // pass register argument 4700 4701 // Pass register number to verify_oop_subroutine 4702 const char* b = nullptr; 4703 { 4704 ResourceMark rm; 4705 stringStream ss; 4706 ss.print("verify_oop: %s: %s (%s:%d)", reg->name(), s, file, line); 4707 b = code_string(ss.as_string()); 4708 } 4709 ExternalAddress buffer((address) b); 4710 pushptr(buffer.addr(), rscratch1); 4711 4712 // call indirectly to solve generation ordering problem 4713 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address())); 4714 call(rax); 4715 // Caller pops the arguments (oop, message) and restores rax, r10 4716 BLOCK_COMMENT("} verify_oop"); 4717 } 4718 4719 void MacroAssembler::vallones(XMMRegister dst, int vector_len) { 4720 if (UseAVX > 2 && (vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl())) { 4721 // Only pcmpeq has dependency breaking treatment (i.e the execution can begin without 4722 // waiting for the previous result on dst), not vpcmpeqd, so just use vpternlog 4723 vpternlogd(dst, 0xFF, dst, dst, vector_len); 4724 } else if (VM_Version::supports_avx()) { 4725 vpcmpeqd(dst, dst, dst, vector_len); 4726 } else { 4727 assert(VM_Version::supports_sse2(), ""); 4728 pcmpeqd(dst, dst); 4729 } 4730 } 4731 4732 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot, 4733 int extra_slot_offset) { 4734 // cf. TemplateTable::prepare_invoke(), if (load_receiver). 4735 int stackElementSize = Interpreter::stackElementSize; 4736 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0); 4737 #ifdef ASSERT 4738 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1); 4739 assert(offset1 - offset == stackElementSize, "correct arithmetic"); 4740 #endif 4741 Register scale_reg = noreg; 4742 Address::ScaleFactor scale_factor = Address::no_scale; 4743 if (arg_slot.is_constant()) { 4744 offset += arg_slot.as_constant() * stackElementSize; 4745 } else { 4746 scale_reg = arg_slot.as_register(); 4747 scale_factor = Address::times(stackElementSize); 4748 } 4749 offset += wordSize; // return PC is on stack 4750 return Address(rsp, scale_reg, scale_factor, offset); 4751 } 4752 4753 void MacroAssembler::_verify_oop_addr(Address addr, const char* s, const char* file, int line) { 4754 if (!VerifyOops) return; 4755 4756 #ifdef _LP64 4757 push(rscratch1); 4758 #endif 4759 push(rax); // save rax, 4760 // addr may contain rsp so we will have to adjust it based on the push 4761 // we just did (and on 64 bit we do two pushes) 4762 // NOTE: 64bit seemed to have had a bug in that it did movq(addr, rax); which 4763 // stores rax into addr which is backwards of what was intended. 4764 if (addr.uses(rsp)) { 4765 lea(rax, addr); 4766 pushptr(Address(rax, LP64_ONLY(2 *) BytesPerWord)); 4767 } else { 4768 pushptr(addr); 4769 } 4770 4771 // Pass register number to verify_oop_subroutine 4772 const char* b = nullptr; 4773 { 4774 ResourceMark rm; 4775 stringStream ss; 4776 ss.print("verify_oop_addr: %s (%s:%d)", s, file, line); 4777 b = code_string(ss.as_string()); 4778 } 4779 ExternalAddress buffer((address) b); 4780 pushptr(buffer.addr(), rscratch1); 4781 4782 // call indirectly to solve generation ordering problem 4783 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address())); 4784 call(rax); 4785 // Caller pops the arguments (addr, message) and restores rax, r10. 4786 } 4787 4788 void MacroAssembler::verify_tlab() { 4789 #ifdef ASSERT 4790 if (UseTLAB && VerifyOops) { 4791 Label next, ok; 4792 Register t1 = rsi; 4793 Register thread_reg = NOT_LP64(rbx) LP64_ONLY(r15_thread); 4794 4795 push(t1); 4796 NOT_LP64(push(thread_reg)); 4797 NOT_LP64(get_thread(thread_reg)); 4798 4799 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset()))); 4800 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset()))); 4801 jcc(Assembler::aboveEqual, next); 4802 STOP("assert(top >= start)"); 4803 should_not_reach_here(); 4804 4805 bind(next); 4806 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset()))); 4807 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset()))); 4808 jcc(Assembler::aboveEqual, ok); 4809 STOP("assert(top <= end)"); 4810 should_not_reach_here(); 4811 4812 bind(ok); 4813 NOT_LP64(pop(thread_reg)); 4814 pop(t1); 4815 } 4816 #endif 4817 } 4818 4819 class ControlWord { 4820 public: 4821 int32_t _value; 4822 4823 int rounding_control() const { return (_value >> 10) & 3 ; } 4824 int precision_control() const { return (_value >> 8) & 3 ; } 4825 bool precision() const { return ((_value >> 5) & 1) != 0; } 4826 bool underflow() const { return ((_value >> 4) & 1) != 0; } 4827 bool overflow() const { return ((_value >> 3) & 1) != 0; } 4828 bool zero_divide() const { return ((_value >> 2) & 1) != 0; } 4829 bool denormalized() const { return ((_value >> 1) & 1) != 0; } 4830 bool invalid() const { return ((_value >> 0) & 1) != 0; } 4831 4832 void print() const { 4833 // rounding control 4834 const char* rc; 4835 switch (rounding_control()) { 4836 case 0: rc = "round near"; break; 4837 case 1: rc = "round down"; break; 4838 case 2: rc = "round up "; break; 4839 case 3: rc = "chop "; break; 4840 default: 4841 rc = nullptr; // silence compiler warnings 4842 fatal("Unknown rounding control: %d", rounding_control()); 4843 }; 4844 // precision control 4845 const char* pc; 4846 switch (precision_control()) { 4847 case 0: pc = "24 bits "; break; 4848 case 1: pc = "reserved"; break; 4849 case 2: pc = "53 bits "; break; 4850 case 3: pc = "64 bits "; break; 4851 default: 4852 pc = nullptr; // silence compiler warnings 4853 fatal("Unknown precision control: %d", precision_control()); 4854 }; 4855 // flags 4856 char f[9]; 4857 f[0] = ' '; 4858 f[1] = ' '; 4859 f[2] = (precision ()) ? 'P' : 'p'; 4860 f[3] = (underflow ()) ? 'U' : 'u'; 4861 f[4] = (overflow ()) ? 'O' : 'o'; 4862 f[5] = (zero_divide ()) ? 'Z' : 'z'; 4863 f[6] = (denormalized()) ? 'D' : 'd'; 4864 f[7] = (invalid ()) ? 'I' : 'i'; 4865 f[8] = '\x0'; 4866 // output 4867 printf("%04x masks = %s, %s, %s", _value & 0xFFFF, f, rc, pc); 4868 } 4869 4870 }; 4871 4872 class StatusWord { 4873 public: 4874 int32_t _value; 4875 4876 bool busy() const { return ((_value >> 15) & 1) != 0; } 4877 bool C3() const { return ((_value >> 14) & 1) != 0; } 4878 bool C2() const { return ((_value >> 10) & 1) != 0; } 4879 bool C1() const { return ((_value >> 9) & 1) != 0; } 4880 bool C0() const { return ((_value >> 8) & 1) != 0; } 4881 int top() const { return (_value >> 11) & 7 ; } 4882 bool error_status() const { return ((_value >> 7) & 1) != 0; } 4883 bool stack_fault() const { return ((_value >> 6) & 1) != 0; } 4884 bool precision() const { return ((_value >> 5) & 1) != 0; } 4885 bool underflow() const { return ((_value >> 4) & 1) != 0; } 4886 bool overflow() const { return ((_value >> 3) & 1) != 0; } 4887 bool zero_divide() const { return ((_value >> 2) & 1) != 0; } 4888 bool denormalized() const { return ((_value >> 1) & 1) != 0; } 4889 bool invalid() const { return ((_value >> 0) & 1) != 0; } 4890 4891 void print() const { 4892 // condition codes 4893 char c[5]; 4894 c[0] = (C3()) ? '3' : '-'; 4895 c[1] = (C2()) ? '2' : '-'; 4896 c[2] = (C1()) ? '1' : '-'; 4897 c[3] = (C0()) ? '0' : '-'; 4898 c[4] = '\x0'; 4899 // flags 4900 char f[9]; 4901 f[0] = (error_status()) ? 'E' : '-'; 4902 f[1] = (stack_fault ()) ? 'S' : '-'; 4903 f[2] = (precision ()) ? 'P' : '-'; 4904 f[3] = (underflow ()) ? 'U' : '-'; 4905 f[4] = (overflow ()) ? 'O' : '-'; 4906 f[5] = (zero_divide ()) ? 'Z' : '-'; 4907 f[6] = (denormalized()) ? 'D' : '-'; 4908 f[7] = (invalid ()) ? 'I' : '-'; 4909 f[8] = '\x0'; 4910 // output 4911 printf("%04x flags = %s, cc = %s, top = %d", _value & 0xFFFF, f, c, top()); 4912 } 4913 4914 }; 4915 4916 class TagWord { 4917 public: 4918 int32_t _value; 4919 4920 int tag_at(int i) const { return (_value >> (i*2)) & 3; } 4921 4922 void print() const { 4923 printf("%04x", _value & 0xFFFF); 4924 } 4925 4926 }; 4927 4928 class FPU_Register { 4929 public: 4930 int32_t _m0; 4931 int32_t _m1; 4932 int16_t _ex; 4933 4934 bool is_indefinite() const { 4935 return _ex == -1 && _m1 == (int32_t)0xC0000000 && _m0 == 0; 4936 } 4937 4938 void print() const { 4939 char sign = (_ex < 0) ? '-' : '+'; 4940 const char* kind = (_ex == 0x7FFF || _ex == (int16_t)-1) ? "NaN" : " "; 4941 printf("%c%04hx.%08x%08x %s", sign, _ex, _m1, _m0, kind); 4942 }; 4943 4944 }; 4945 4946 class FPU_State { 4947 public: 4948 enum { 4949 register_size = 10, 4950 number_of_registers = 8, 4951 register_mask = 7 4952 }; 4953 4954 ControlWord _control_word; 4955 StatusWord _status_word; 4956 TagWord _tag_word; 4957 int32_t _error_offset; 4958 int32_t _error_selector; 4959 int32_t _data_offset; 4960 int32_t _data_selector; 4961 int8_t _register[register_size * number_of_registers]; 4962 4963 int tag_for_st(int i) const { return _tag_word.tag_at((_status_word.top() + i) & register_mask); } 4964 FPU_Register* st(int i) const { return (FPU_Register*)&_register[register_size * i]; } 4965 4966 const char* tag_as_string(int tag) const { 4967 switch (tag) { 4968 case 0: return "valid"; 4969 case 1: return "zero"; 4970 case 2: return "special"; 4971 case 3: return "empty"; 4972 } 4973 ShouldNotReachHere(); 4974 return nullptr; 4975 } 4976 4977 void print() const { 4978 // print computation registers 4979 { int t = _status_word.top(); 4980 for (int i = 0; i < number_of_registers; i++) { 4981 int j = (i - t) & register_mask; 4982 printf("%c r%d = ST%d = ", (j == 0 ? '*' : ' '), i, j); 4983 st(j)->print(); 4984 printf(" %s\n", tag_as_string(_tag_word.tag_at(i))); 4985 } 4986 } 4987 printf("\n"); 4988 // print control registers 4989 printf("ctrl = "); _control_word.print(); printf("\n"); 4990 printf("stat = "); _status_word .print(); printf("\n"); 4991 printf("tags = "); _tag_word .print(); printf("\n"); 4992 } 4993 4994 }; 4995 4996 class Flag_Register { 4997 public: 4998 int32_t _value; 4999 5000 bool overflow() const { return ((_value >> 11) & 1) != 0; } 5001 bool direction() const { return ((_value >> 10) & 1) != 0; } 5002 bool sign() const { return ((_value >> 7) & 1) != 0; } 5003 bool zero() const { return ((_value >> 6) & 1) != 0; } 5004 bool auxiliary_carry() const { return ((_value >> 4) & 1) != 0; } 5005 bool parity() const { return ((_value >> 2) & 1) != 0; } 5006 bool carry() const { return ((_value >> 0) & 1) != 0; } 5007 5008 void print() const { 5009 // flags 5010 char f[8]; 5011 f[0] = (overflow ()) ? 'O' : '-'; 5012 f[1] = (direction ()) ? 'D' : '-'; 5013 f[2] = (sign ()) ? 'S' : '-'; 5014 f[3] = (zero ()) ? 'Z' : '-'; 5015 f[4] = (auxiliary_carry()) ? 'A' : '-'; 5016 f[5] = (parity ()) ? 'P' : '-'; 5017 f[6] = (carry ()) ? 'C' : '-'; 5018 f[7] = '\x0'; 5019 // output 5020 printf("%08x flags = %s", _value, f); 5021 } 5022 5023 }; 5024 5025 class IU_Register { 5026 public: 5027 int32_t _value; 5028 5029 void print() const { 5030 printf("%08x %11d", _value, _value); 5031 } 5032 5033 }; 5034 5035 class IU_State { 5036 public: 5037 Flag_Register _eflags; 5038 IU_Register _rdi; 5039 IU_Register _rsi; 5040 IU_Register _rbp; 5041 IU_Register _rsp; 5042 IU_Register _rbx; 5043 IU_Register _rdx; 5044 IU_Register _rcx; 5045 IU_Register _rax; 5046 5047 void print() const { 5048 // computation registers 5049 printf("rax, = "); _rax.print(); printf("\n"); 5050 printf("rbx, = "); _rbx.print(); printf("\n"); 5051 printf("rcx = "); _rcx.print(); printf("\n"); 5052 printf("rdx = "); _rdx.print(); printf("\n"); 5053 printf("rdi = "); _rdi.print(); printf("\n"); 5054 printf("rsi = "); _rsi.print(); printf("\n"); 5055 printf("rbp, = "); _rbp.print(); printf("\n"); 5056 printf("rsp = "); _rsp.print(); printf("\n"); 5057 printf("\n"); 5058 // control registers 5059 printf("flgs = "); _eflags.print(); printf("\n"); 5060 } 5061 }; 5062 5063 5064 class CPU_State { 5065 public: 5066 FPU_State _fpu_state; 5067 IU_State _iu_state; 5068 5069 void print() const { 5070 printf("--------------------------------------------------\n"); 5071 _iu_state .print(); 5072 printf("\n"); 5073 _fpu_state.print(); 5074 printf("--------------------------------------------------\n"); 5075 } 5076 5077 }; 5078 5079 5080 static void _print_CPU_state(CPU_State* state) { 5081 state->print(); 5082 }; 5083 5084 5085 void MacroAssembler::print_CPU_state() { 5086 push_CPU_state(); 5087 push(rsp); // pass CPU state 5088 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _print_CPU_state))); 5089 addptr(rsp, wordSize); // discard argument 5090 pop_CPU_state(); 5091 } 5092 5093 5094 #ifndef _LP64 5095 static bool _verify_FPU(int stack_depth, char* s, CPU_State* state) { 5096 static int counter = 0; 5097 FPU_State* fs = &state->_fpu_state; 5098 counter++; 5099 // For leaf calls, only verify that the top few elements remain empty. 5100 // We only need 1 empty at the top for C2 code. 5101 if( stack_depth < 0 ) { 5102 if( fs->tag_for_st(7) != 3 ) { 5103 printf("FPR7 not empty\n"); 5104 state->print(); 5105 assert(false, "error"); 5106 return false; 5107 } 5108 return true; // All other stack states do not matter 5109 } 5110 5111 assert((fs->_control_word._value & 0xffff) == StubRoutines::x86::fpu_cntrl_wrd_std(), 5112 "bad FPU control word"); 5113 5114 // compute stack depth 5115 int i = 0; 5116 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) < 3) i++; 5117 int d = i; 5118 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) == 3) i++; 5119 // verify findings 5120 if (i != FPU_State::number_of_registers) { 5121 // stack not contiguous 5122 printf("%s: stack not contiguous at ST%d\n", s, i); 5123 state->print(); 5124 assert(false, "error"); 5125 return false; 5126 } 5127 // check if computed stack depth corresponds to expected stack depth 5128 if (stack_depth < 0) { 5129 // expected stack depth is -stack_depth or less 5130 if (d > -stack_depth) { 5131 // too many elements on the stack 5132 printf("%s: <= %d stack elements expected but found %d\n", s, -stack_depth, d); 5133 state->print(); 5134 assert(false, "error"); 5135 return false; 5136 } 5137 } else { 5138 // expected stack depth is stack_depth 5139 if (d != stack_depth) { 5140 // wrong stack depth 5141 printf("%s: %d stack elements expected but found %d\n", s, stack_depth, d); 5142 state->print(); 5143 assert(false, "error"); 5144 return false; 5145 } 5146 } 5147 // everything is cool 5148 return true; 5149 } 5150 5151 void MacroAssembler::verify_FPU(int stack_depth, const char* s) { 5152 if (!VerifyFPU) return; 5153 push_CPU_state(); 5154 push(rsp); // pass CPU state 5155 ExternalAddress msg((address) s); 5156 // pass message string s 5157 pushptr(msg.addr(), noreg); 5158 push(stack_depth); // pass stack depth 5159 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _verify_FPU))); 5160 addptr(rsp, 3 * wordSize); // discard arguments 5161 // check for error 5162 { Label L; 5163 testl(rax, rax); 5164 jcc(Assembler::notZero, L); 5165 int3(); // break if error condition 5166 bind(L); 5167 } 5168 pop_CPU_state(); 5169 } 5170 #endif // _LP64 5171 5172 void MacroAssembler::restore_cpu_control_state_after_jni(Register rscratch) { 5173 // Either restore the MXCSR register after returning from the JNI Call 5174 // or verify that it wasn't changed (with -Xcheck:jni flag). 5175 if (VM_Version::supports_sse()) { 5176 if (RestoreMXCSROnJNICalls) { 5177 ldmxcsr(ExternalAddress(StubRoutines::x86::addr_mxcsr_std()), rscratch); 5178 } else if (CheckJNICalls) { 5179 call(RuntimeAddress(StubRoutines::x86::verify_mxcsr_entry())); 5180 } 5181 } 5182 // Clear upper bits of YMM registers to avoid SSE <-> AVX transition penalty. 5183 vzeroupper(); 5184 5185 #ifndef _LP64 5186 // Either restore the x87 floating pointer control word after returning 5187 // from the JNI call or verify that it wasn't changed. 5188 if (CheckJNICalls) { 5189 call(RuntimeAddress(StubRoutines::x86::verify_fpu_cntrl_wrd_entry())); 5190 } 5191 #endif // _LP64 5192 } 5193 5194 // ((OopHandle)result).resolve(); 5195 void MacroAssembler::resolve_oop_handle(Register result, Register tmp) { 5196 assert_different_registers(result, tmp); 5197 5198 // Only 64 bit platforms support GCs that require a tmp register 5199 // Only IN_HEAP loads require a thread_tmp register 5200 // OopHandle::resolve is an indirection like jobject. 5201 access_load_at(T_OBJECT, IN_NATIVE, 5202 result, Address(result, 0), tmp, /*tmp_thread*/noreg); 5203 } 5204 5205 // ((WeakHandle)result).resolve(); 5206 void MacroAssembler::resolve_weak_handle(Register rresult, Register rtmp) { 5207 assert_different_registers(rresult, rtmp); 5208 Label resolved; 5209 5210 // A null weak handle resolves to null. 5211 cmpptr(rresult, 0); 5212 jcc(Assembler::equal, resolved); 5213 5214 // Only 64 bit platforms support GCs that require a tmp register 5215 // Only IN_HEAP loads require a thread_tmp register 5216 // WeakHandle::resolve is an indirection like jweak. 5217 access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF, 5218 rresult, Address(rresult, 0), rtmp, /*tmp_thread*/noreg); 5219 bind(resolved); 5220 } 5221 5222 void MacroAssembler::load_mirror(Register mirror, Register method, Register tmp) { 5223 // get mirror 5224 const int mirror_offset = in_bytes(Klass::java_mirror_offset()); 5225 load_method_holder(mirror, method); 5226 movptr(mirror, Address(mirror, mirror_offset)); 5227 resolve_oop_handle(mirror, tmp); 5228 } 5229 5230 void MacroAssembler::load_method_holder_cld(Register rresult, Register rmethod) { 5231 load_method_holder(rresult, rmethod); 5232 movptr(rresult, Address(rresult, InstanceKlass::class_loader_data_offset())); 5233 } 5234 5235 void MacroAssembler::load_method_holder(Register holder, Register method) { 5236 movptr(holder, Address(method, Method::const_offset())); // ConstMethod* 5237 movptr(holder, Address(holder, ConstMethod::constants_offset())); // ConstantPool* 5238 movptr(holder, Address(holder, ConstantPool::pool_holder_offset())); // InstanceKlass* 5239 } 5240 5241 void MacroAssembler::load_klass(Register dst, Register src, Register tmp) { 5242 assert_different_registers(src, tmp); 5243 assert_different_registers(dst, tmp); 5244 #ifdef _LP64 5245 if (UseCompressedClassPointers) { 5246 movl(dst, Address(src, oopDesc::klass_offset_in_bytes())); 5247 decode_klass_not_null(dst, tmp); 5248 } else 5249 #endif 5250 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes())); 5251 } 5252 5253 void MacroAssembler::store_klass(Register dst, Register src, Register tmp) { 5254 assert_different_registers(src, tmp); 5255 assert_different_registers(dst, tmp); 5256 #ifdef _LP64 5257 if (UseCompressedClassPointers) { 5258 encode_klass_not_null(src, tmp); 5259 movl(Address(dst, oopDesc::klass_offset_in_bytes()), src); 5260 } else 5261 #endif 5262 movptr(Address(dst, oopDesc::klass_offset_in_bytes()), src); 5263 } 5264 5265 void MacroAssembler::access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src, 5266 Register tmp1, Register thread_tmp) { 5267 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler(); 5268 decorators = AccessInternal::decorator_fixup(decorators, type); 5269 bool as_raw = (decorators & AS_RAW) != 0; 5270 if (as_raw) { 5271 bs->BarrierSetAssembler::load_at(this, decorators, type, dst, src, tmp1, thread_tmp); 5272 } else { 5273 bs->load_at(this, decorators, type, dst, src, tmp1, thread_tmp); 5274 } 5275 } 5276 5277 void MacroAssembler::access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register val, 5278 Register tmp1, Register tmp2, Register tmp3) { 5279 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler(); 5280 decorators = AccessInternal::decorator_fixup(decorators, type); 5281 bool as_raw = (decorators & AS_RAW) != 0; 5282 if (as_raw) { 5283 bs->BarrierSetAssembler::store_at(this, decorators, type, dst, val, tmp1, tmp2, tmp3); 5284 } else { 5285 bs->store_at(this, decorators, type, dst, val, tmp1, tmp2, tmp3); 5286 } 5287 } 5288 5289 void MacroAssembler::load_heap_oop(Register dst, Address src, Register tmp1, 5290 Register thread_tmp, DecoratorSet decorators) { 5291 access_load_at(T_OBJECT, IN_HEAP | decorators, dst, src, tmp1, thread_tmp); 5292 } 5293 5294 // Doesn't do verification, generates fixed size code 5295 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src, Register tmp1, 5296 Register thread_tmp, DecoratorSet decorators) { 5297 access_load_at(T_OBJECT, IN_HEAP | IS_NOT_NULL | decorators, dst, src, tmp1, thread_tmp); 5298 } 5299 5300 void MacroAssembler::store_heap_oop(Address dst, Register val, Register tmp1, 5301 Register tmp2, Register tmp3, DecoratorSet decorators) { 5302 access_store_at(T_OBJECT, IN_HEAP | decorators, dst, val, tmp1, tmp2, tmp3); 5303 } 5304 5305 // Used for storing nulls. 5306 void MacroAssembler::store_heap_oop_null(Address dst) { 5307 access_store_at(T_OBJECT, IN_HEAP, dst, noreg, noreg, noreg, noreg); 5308 } 5309 5310 #ifdef _LP64 5311 void MacroAssembler::store_klass_gap(Register dst, Register src) { 5312 if (UseCompressedClassPointers) { 5313 // Store to klass gap in destination 5314 movl(Address(dst, oopDesc::klass_gap_offset_in_bytes()), src); 5315 } 5316 } 5317 5318 #ifdef ASSERT 5319 void MacroAssembler::verify_heapbase(const char* msg) { 5320 assert (UseCompressedOops, "should be compressed"); 5321 assert (Universe::heap() != nullptr, "java heap should be initialized"); 5322 if (CheckCompressedOops) { 5323 Label ok; 5324 ExternalAddress src2(CompressedOops::ptrs_base_addr()); 5325 const bool is_src2_reachable = reachable(src2); 5326 if (!is_src2_reachable) { 5327 push(rscratch1); // cmpptr trashes rscratch1 5328 } 5329 cmpptr(r12_heapbase, src2, rscratch1); 5330 jcc(Assembler::equal, ok); 5331 STOP(msg); 5332 bind(ok); 5333 if (!is_src2_reachable) { 5334 pop(rscratch1); 5335 } 5336 } 5337 } 5338 #endif 5339 5340 // Algorithm must match oop.inline.hpp encode_heap_oop. 5341 void MacroAssembler::encode_heap_oop(Register r) { 5342 #ifdef ASSERT 5343 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?"); 5344 #endif 5345 verify_oop_msg(r, "broken oop in encode_heap_oop"); 5346 if (CompressedOops::base() == nullptr) { 5347 if (CompressedOops::shift() != 0) { 5348 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong"); 5349 shrq(r, LogMinObjAlignmentInBytes); 5350 } 5351 return; 5352 } 5353 testq(r, r); 5354 cmovq(Assembler::equal, r, r12_heapbase); 5355 subq(r, r12_heapbase); 5356 shrq(r, LogMinObjAlignmentInBytes); 5357 } 5358 5359 void MacroAssembler::encode_heap_oop_not_null(Register r) { 5360 #ifdef ASSERT 5361 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?"); 5362 if (CheckCompressedOops) { 5363 Label ok; 5364 testq(r, r); 5365 jcc(Assembler::notEqual, ok); 5366 STOP("null oop passed to encode_heap_oop_not_null"); 5367 bind(ok); 5368 } 5369 #endif 5370 verify_oop_msg(r, "broken oop in encode_heap_oop_not_null"); 5371 if (CompressedOops::base() != nullptr) { 5372 subq(r, r12_heapbase); 5373 } 5374 if (CompressedOops::shift() != 0) { 5375 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong"); 5376 shrq(r, LogMinObjAlignmentInBytes); 5377 } 5378 } 5379 5380 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) { 5381 #ifdef ASSERT 5382 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?"); 5383 if (CheckCompressedOops) { 5384 Label ok; 5385 testq(src, src); 5386 jcc(Assembler::notEqual, ok); 5387 STOP("null oop passed to encode_heap_oop_not_null2"); 5388 bind(ok); 5389 } 5390 #endif 5391 verify_oop_msg(src, "broken oop in encode_heap_oop_not_null2"); 5392 if (dst != src) { 5393 movq(dst, src); 5394 } 5395 if (CompressedOops::base() != nullptr) { 5396 subq(dst, r12_heapbase); 5397 } 5398 if (CompressedOops::shift() != 0) { 5399 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong"); 5400 shrq(dst, LogMinObjAlignmentInBytes); 5401 } 5402 } 5403 5404 void MacroAssembler::decode_heap_oop(Register r) { 5405 #ifdef ASSERT 5406 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?"); 5407 #endif 5408 if (CompressedOops::base() == nullptr) { 5409 if (CompressedOops::shift() != 0) { 5410 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong"); 5411 shlq(r, LogMinObjAlignmentInBytes); 5412 } 5413 } else { 5414 Label done; 5415 shlq(r, LogMinObjAlignmentInBytes); 5416 jccb(Assembler::equal, done); 5417 addq(r, r12_heapbase); 5418 bind(done); 5419 } 5420 verify_oop_msg(r, "broken oop in decode_heap_oop"); 5421 } 5422 5423 void MacroAssembler::decode_heap_oop_not_null(Register r) { 5424 // Note: it will change flags 5425 assert (UseCompressedOops, "should only be used for compressed headers"); 5426 assert (Universe::heap() != nullptr, "java heap should be initialized"); 5427 // Cannot assert, unverified entry point counts instructions (see .ad file) 5428 // vtableStubs also counts instructions in pd_code_size_limit. 5429 // Also do not verify_oop as this is called by verify_oop. 5430 if (CompressedOops::shift() != 0) { 5431 assert(LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong"); 5432 shlq(r, LogMinObjAlignmentInBytes); 5433 if (CompressedOops::base() != nullptr) { 5434 addq(r, r12_heapbase); 5435 } 5436 } else { 5437 assert (CompressedOops::base() == nullptr, "sanity"); 5438 } 5439 } 5440 5441 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) { 5442 // Note: it will change flags 5443 assert (UseCompressedOops, "should only be used for compressed headers"); 5444 assert (Universe::heap() != nullptr, "java heap should be initialized"); 5445 // Cannot assert, unverified entry point counts instructions (see .ad file) 5446 // vtableStubs also counts instructions in pd_code_size_limit. 5447 // Also do not verify_oop as this is called by verify_oop. 5448 if (CompressedOops::shift() != 0) { 5449 assert(LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong"); 5450 if (LogMinObjAlignmentInBytes == Address::times_8) { 5451 leaq(dst, Address(r12_heapbase, src, Address::times_8, 0)); 5452 } else { 5453 if (dst != src) { 5454 movq(dst, src); 5455 } 5456 shlq(dst, LogMinObjAlignmentInBytes); 5457 if (CompressedOops::base() != nullptr) { 5458 addq(dst, r12_heapbase); 5459 } 5460 } 5461 } else { 5462 assert (CompressedOops::base() == nullptr, "sanity"); 5463 if (dst != src) { 5464 movq(dst, src); 5465 } 5466 } 5467 } 5468 5469 void MacroAssembler::encode_klass_not_null(Register r, Register tmp) { 5470 assert_different_registers(r, tmp); 5471 if (CompressedKlassPointers::base() != nullptr) { 5472 mov64(tmp, (int64_t)CompressedKlassPointers::base()); 5473 subq(r, tmp); 5474 } 5475 if (CompressedKlassPointers::shift() != 0) { 5476 assert (LogKlassAlignmentInBytes == CompressedKlassPointers::shift(), "decode alg wrong"); 5477 shrq(r, LogKlassAlignmentInBytes); 5478 } 5479 } 5480 5481 void MacroAssembler::encode_and_move_klass_not_null(Register dst, Register src) { 5482 assert_different_registers(src, dst); 5483 if (CompressedKlassPointers::base() != nullptr) { 5484 mov64(dst, -(int64_t)CompressedKlassPointers::base()); 5485 addq(dst, src); 5486 } else { 5487 movptr(dst, src); 5488 } 5489 if (CompressedKlassPointers::shift() != 0) { 5490 assert (LogKlassAlignmentInBytes == CompressedKlassPointers::shift(), "decode alg wrong"); 5491 shrq(dst, LogKlassAlignmentInBytes); 5492 } 5493 } 5494 5495 void MacroAssembler::decode_klass_not_null(Register r, Register tmp) { 5496 assert_different_registers(r, tmp); 5497 // Note: it will change flags 5498 assert(UseCompressedClassPointers, "should only be used for compressed headers"); 5499 // Cannot assert, unverified entry point counts instructions (see .ad file) 5500 // vtableStubs also counts instructions in pd_code_size_limit. 5501 // Also do not verify_oop as this is called by verify_oop. 5502 if (CompressedKlassPointers::shift() != 0) { 5503 assert(LogKlassAlignmentInBytes == CompressedKlassPointers::shift(), "decode alg wrong"); 5504 shlq(r, LogKlassAlignmentInBytes); 5505 } 5506 if (CompressedKlassPointers::base() != nullptr) { 5507 mov64(tmp, (int64_t)CompressedKlassPointers::base()); 5508 addq(r, tmp); 5509 } 5510 } 5511 5512 void MacroAssembler::decode_and_move_klass_not_null(Register dst, Register src) { 5513 assert_different_registers(src, dst); 5514 // Note: it will change flags 5515 assert (UseCompressedClassPointers, "should only be used for compressed headers"); 5516 // Cannot assert, unverified entry point counts instructions (see .ad file) 5517 // vtableStubs also counts instructions in pd_code_size_limit. 5518 // Also do not verify_oop as this is called by verify_oop. 5519 5520 if (CompressedKlassPointers::base() == nullptr && 5521 CompressedKlassPointers::shift() == 0) { 5522 // The best case scenario is that there is no base or shift. Then it is already 5523 // a pointer that needs nothing but a register rename. 5524 movl(dst, src); 5525 } else { 5526 if (CompressedKlassPointers::base() != nullptr) { 5527 mov64(dst, (int64_t)CompressedKlassPointers::base()); 5528 } else { 5529 xorq(dst, dst); 5530 } 5531 if (CompressedKlassPointers::shift() != 0) { 5532 assert(LogKlassAlignmentInBytes == CompressedKlassPointers::shift(), "decode alg wrong"); 5533 assert(LogKlassAlignmentInBytes == Address::times_8, "klass not aligned on 64bits?"); 5534 leaq(dst, Address(dst, src, Address::times_8, 0)); 5535 } else { 5536 addq(dst, src); 5537 } 5538 } 5539 } 5540 5541 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) { 5542 assert (UseCompressedOops, "should only be used for compressed headers"); 5543 assert (Universe::heap() != nullptr, "java heap should be initialized"); 5544 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder"); 5545 int oop_index = oop_recorder()->find_index(obj); 5546 RelocationHolder rspec = oop_Relocation::spec(oop_index); 5547 mov_narrow_oop(dst, oop_index, rspec); 5548 } 5549 5550 void MacroAssembler::set_narrow_oop(Address dst, jobject obj) { 5551 assert (UseCompressedOops, "should only be used for compressed headers"); 5552 assert (Universe::heap() != nullptr, "java heap should be initialized"); 5553 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder"); 5554 int oop_index = oop_recorder()->find_index(obj); 5555 RelocationHolder rspec = oop_Relocation::spec(oop_index); 5556 mov_narrow_oop(dst, oop_index, rspec); 5557 } 5558 5559 void MacroAssembler::set_narrow_klass(Register dst, Klass* k) { 5560 assert (UseCompressedClassPointers, "should only be used for compressed headers"); 5561 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder"); 5562 int klass_index = oop_recorder()->find_index(k); 5563 RelocationHolder rspec = metadata_Relocation::spec(klass_index); 5564 mov_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec); 5565 } 5566 5567 void MacroAssembler::set_narrow_klass(Address dst, Klass* k) { 5568 assert (UseCompressedClassPointers, "should only be used for compressed headers"); 5569 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder"); 5570 int klass_index = oop_recorder()->find_index(k); 5571 RelocationHolder rspec = metadata_Relocation::spec(klass_index); 5572 mov_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec); 5573 } 5574 5575 void MacroAssembler::cmp_narrow_oop(Register dst, jobject obj) { 5576 assert (UseCompressedOops, "should only be used for compressed headers"); 5577 assert (Universe::heap() != nullptr, "java heap should be initialized"); 5578 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder"); 5579 int oop_index = oop_recorder()->find_index(obj); 5580 RelocationHolder rspec = oop_Relocation::spec(oop_index); 5581 Assembler::cmp_narrow_oop(dst, oop_index, rspec); 5582 } 5583 5584 void MacroAssembler::cmp_narrow_oop(Address dst, jobject obj) { 5585 assert (UseCompressedOops, "should only be used for compressed headers"); 5586 assert (Universe::heap() != nullptr, "java heap should be initialized"); 5587 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder"); 5588 int oop_index = oop_recorder()->find_index(obj); 5589 RelocationHolder rspec = oop_Relocation::spec(oop_index); 5590 Assembler::cmp_narrow_oop(dst, oop_index, rspec); 5591 } 5592 5593 void MacroAssembler::cmp_narrow_klass(Register dst, Klass* k) { 5594 assert (UseCompressedClassPointers, "should only be used for compressed headers"); 5595 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder"); 5596 int klass_index = oop_recorder()->find_index(k); 5597 RelocationHolder rspec = metadata_Relocation::spec(klass_index); 5598 Assembler::cmp_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec); 5599 } 5600 5601 void MacroAssembler::cmp_narrow_klass(Address dst, Klass* k) { 5602 assert (UseCompressedClassPointers, "should only be used for compressed headers"); 5603 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder"); 5604 int klass_index = oop_recorder()->find_index(k); 5605 RelocationHolder rspec = metadata_Relocation::spec(klass_index); 5606 Assembler::cmp_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec); 5607 } 5608 5609 void MacroAssembler::reinit_heapbase() { 5610 if (UseCompressedOops) { 5611 if (Universe::heap() != nullptr) { 5612 if (CompressedOops::base() == nullptr) { 5613 MacroAssembler::xorptr(r12_heapbase, r12_heapbase); 5614 } else { 5615 mov64(r12_heapbase, (int64_t)CompressedOops::ptrs_base()); 5616 } 5617 } else { 5618 movptr(r12_heapbase, ExternalAddress(CompressedOops::ptrs_base_addr())); 5619 } 5620 } 5621 } 5622 5623 #endif // _LP64 5624 5625 #if COMPILER2_OR_JVMCI 5626 5627 // clear memory of size 'cnt' qwords, starting at 'base' using XMM/YMM/ZMM registers 5628 void MacroAssembler::xmm_clear_mem(Register base, Register cnt, Register rtmp, XMMRegister xtmp, KRegister mask) { 5629 // cnt - number of qwords (8-byte words). 5630 // base - start address, qword aligned. 5631 Label L_zero_64_bytes, L_loop, L_sloop, L_tail, L_end; 5632 bool use64byteVector = (MaxVectorSize == 64) && (VM_Version::avx3_threshold() == 0); 5633 if (use64byteVector) { 5634 vpxor(xtmp, xtmp, xtmp, AVX_512bit); 5635 } else if (MaxVectorSize >= 32) { 5636 vpxor(xtmp, xtmp, xtmp, AVX_256bit); 5637 } else { 5638 pxor(xtmp, xtmp); 5639 } 5640 jmp(L_zero_64_bytes); 5641 5642 BIND(L_loop); 5643 if (MaxVectorSize >= 32) { 5644 fill64(base, 0, xtmp, use64byteVector); 5645 } else { 5646 movdqu(Address(base, 0), xtmp); 5647 movdqu(Address(base, 16), xtmp); 5648 movdqu(Address(base, 32), xtmp); 5649 movdqu(Address(base, 48), xtmp); 5650 } 5651 addptr(base, 64); 5652 5653 BIND(L_zero_64_bytes); 5654 subptr(cnt, 8); 5655 jccb(Assembler::greaterEqual, L_loop); 5656 5657 // Copy trailing 64 bytes 5658 if (use64byteVector) { 5659 addptr(cnt, 8); 5660 jccb(Assembler::equal, L_end); 5661 fill64_masked(3, base, 0, xtmp, mask, cnt, rtmp, true); 5662 jmp(L_end); 5663 } else { 5664 addptr(cnt, 4); 5665 jccb(Assembler::less, L_tail); 5666 if (MaxVectorSize >= 32) { 5667 vmovdqu(Address(base, 0), xtmp); 5668 } else { 5669 movdqu(Address(base, 0), xtmp); 5670 movdqu(Address(base, 16), xtmp); 5671 } 5672 } 5673 addptr(base, 32); 5674 subptr(cnt, 4); 5675 5676 BIND(L_tail); 5677 addptr(cnt, 4); 5678 jccb(Assembler::lessEqual, L_end); 5679 if (UseAVX > 2 && MaxVectorSize >= 32 && VM_Version::supports_avx512vl()) { 5680 fill32_masked(3, base, 0, xtmp, mask, cnt, rtmp); 5681 } else { 5682 decrement(cnt); 5683 5684 BIND(L_sloop); 5685 movq(Address(base, 0), xtmp); 5686 addptr(base, 8); 5687 decrement(cnt); 5688 jccb(Assembler::greaterEqual, L_sloop); 5689 } 5690 BIND(L_end); 5691 } 5692 5693 // Clearing constant sized memory using YMM/ZMM registers. 5694 void MacroAssembler::clear_mem(Register base, int cnt, Register rtmp, XMMRegister xtmp, KRegister mask) { 5695 assert(UseAVX > 2 && VM_Version::supports_avx512vlbw(), ""); 5696 bool use64byteVector = (MaxVectorSize > 32) && (VM_Version::avx3_threshold() == 0); 5697 5698 int vector64_count = (cnt & (~0x7)) >> 3; 5699 cnt = cnt & 0x7; 5700 const int fill64_per_loop = 4; 5701 const int max_unrolled_fill64 = 8; 5702 5703 // 64 byte initialization loop. 5704 vpxor(xtmp, xtmp, xtmp, use64byteVector ? AVX_512bit : AVX_256bit); 5705 int start64 = 0; 5706 if (vector64_count > max_unrolled_fill64) { 5707 Label LOOP; 5708 Register index = rtmp; 5709 5710 start64 = vector64_count - (vector64_count % fill64_per_loop); 5711 5712 movl(index, 0); 5713 BIND(LOOP); 5714 for (int i = 0; i < fill64_per_loop; i++) { 5715 fill64(Address(base, index, Address::times_1, i * 64), xtmp, use64byteVector); 5716 } 5717 addl(index, fill64_per_loop * 64); 5718 cmpl(index, start64 * 64); 5719 jccb(Assembler::less, LOOP); 5720 } 5721 for (int i = start64; i < vector64_count; i++) { 5722 fill64(base, i * 64, xtmp, use64byteVector); 5723 } 5724 5725 // Clear remaining 64 byte tail. 5726 int disp = vector64_count * 64; 5727 if (cnt) { 5728 switch (cnt) { 5729 case 1: 5730 movq(Address(base, disp), xtmp); 5731 break; 5732 case 2: 5733 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_128bit); 5734 break; 5735 case 3: 5736 movl(rtmp, 0x7); 5737 kmovwl(mask, rtmp); 5738 evmovdqu(T_LONG, mask, Address(base, disp), xtmp, true, Assembler::AVX_256bit); 5739 break; 5740 case 4: 5741 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_256bit); 5742 break; 5743 case 5: 5744 if (use64byteVector) { 5745 movl(rtmp, 0x1F); 5746 kmovwl(mask, rtmp); 5747 evmovdqu(T_LONG, mask, Address(base, disp), xtmp, true, Assembler::AVX_512bit); 5748 } else { 5749 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_256bit); 5750 movq(Address(base, disp + 32), xtmp); 5751 } 5752 break; 5753 case 6: 5754 if (use64byteVector) { 5755 movl(rtmp, 0x3F); 5756 kmovwl(mask, rtmp); 5757 evmovdqu(T_LONG, mask, Address(base, disp), xtmp, true, Assembler::AVX_512bit); 5758 } else { 5759 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_256bit); 5760 evmovdqu(T_LONG, k0, Address(base, disp + 32), xtmp, false, Assembler::AVX_128bit); 5761 } 5762 break; 5763 case 7: 5764 if (use64byteVector) { 5765 movl(rtmp, 0x7F); 5766 kmovwl(mask, rtmp); 5767 evmovdqu(T_LONG, mask, Address(base, disp), xtmp, true, Assembler::AVX_512bit); 5768 } else { 5769 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_256bit); 5770 movl(rtmp, 0x7); 5771 kmovwl(mask, rtmp); 5772 evmovdqu(T_LONG, mask, Address(base, disp + 32), xtmp, true, Assembler::AVX_256bit); 5773 } 5774 break; 5775 default: 5776 fatal("Unexpected length : %d\n",cnt); 5777 break; 5778 } 5779 } 5780 } 5781 5782 void MacroAssembler::clear_mem(Register base, Register cnt, Register tmp, XMMRegister xtmp, 5783 bool is_large, KRegister mask) { 5784 // cnt - number of qwords (8-byte words). 5785 // base - start address, qword aligned. 5786 // is_large - if optimizers know cnt is larger than InitArrayShortSize 5787 assert(base==rdi, "base register must be edi for rep stos"); 5788 assert(tmp==rax, "tmp register must be eax for rep stos"); 5789 assert(cnt==rcx, "cnt register must be ecx for rep stos"); 5790 assert(InitArrayShortSize % BytesPerLong == 0, 5791 "InitArrayShortSize should be the multiple of BytesPerLong"); 5792 5793 Label DONE; 5794 if (!is_large || !UseXMMForObjInit) { 5795 xorptr(tmp, tmp); 5796 } 5797 5798 if (!is_large) { 5799 Label LOOP, LONG; 5800 cmpptr(cnt, InitArrayShortSize/BytesPerLong); 5801 jccb(Assembler::greater, LONG); 5802 5803 NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM 5804 5805 decrement(cnt); 5806 jccb(Assembler::negative, DONE); // Zero length 5807 5808 // Use individual pointer-sized stores for small counts: 5809 BIND(LOOP); 5810 movptr(Address(base, cnt, Address::times_ptr), tmp); 5811 decrement(cnt); 5812 jccb(Assembler::greaterEqual, LOOP); 5813 jmpb(DONE); 5814 5815 BIND(LONG); 5816 } 5817 5818 // Use longer rep-prefixed ops for non-small counts: 5819 if (UseFastStosb) { 5820 shlptr(cnt, 3); // convert to number of bytes 5821 rep_stosb(); 5822 } else if (UseXMMForObjInit) { 5823 xmm_clear_mem(base, cnt, tmp, xtmp, mask); 5824 } else { 5825 NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM 5826 rep_stos(); 5827 } 5828 5829 BIND(DONE); 5830 } 5831 5832 #endif //COMPILER2_OR_JVMCI 5833 5834 5835 void MacroAssembler::generate_fill(BasicType t, bool aligned, 5836 Register to, Register value, Register count, 5837 Register rtmp, XMMRegister xtmp) { 5838 ShortBranchVerifier sbv(this); 5839 assert_different_registers(to, value, count, rtmp); 5840 Label L_exit; 5841 Label L_fill_2_bytes, L_fill_4_bytes; 5842 5843 #if defined(COMPILER2) && defined(_LP64) 5844 if(MaxVectorSize >=32 && 5845 VM_Version::supports_avx512vlbw() && 5846 VM_Version::supports_bmi2()) { 5847 generate_fill_avx3(t, to, value, count, rtmp, xtmp); 5848 return; 5849 } 5850 #endif 5851 5852 int shift = -1; 5853 switch (t) { 5854 case T_BYTE: 5855 shift = 2; 5856 break; 5857 case T_SHORT: 5858 shift = 1; 5859 break; 5860 case T_INT: 5861 shift = 0; 5862 break; 5863 default: ShouldNotReachHere(); 5864 } 5865 5866 if (t == T_BYTE) { 5867 andl(value, 0xff); 5868 movl(rtmp, value); 5869 shll(rtmp, 8); 5870 orl(value, rtmp); 5871 } 5872 if (t == T_SHORT) { 5873 andl(value, 0xffff); 5874 } 5875 if (t == T_BYTE || t == T_SHORT) { 5876 movl(rtmp, value); 5877 shll(rtmp, 16); 5878 orl(value, rtmp); 5879 } 5880 5881 cmpl(count, 2<<shift); // Short arrays (< 8 bytes) fill by element 5882 jcc(Assembler::below, L_fill_4_bytes); // use unsigned cmp 5883 if (!UseUnalignedLoadStores && !aligned && (t == T_BYTE || t == T_SHORT)) { 5884 Label L_skip_align2; 5885 // align source address at 4 bytes address boundary 5886 if (t == T_BYTE) { 5887 Label L_skip_align1; 5888 // One byte misalignment happens only for byte arrays 5889 testptr(to, 1); 5890 jccb(Assembler::zero, L_skip_align1); 5891 movb(Address(to, 0), value); 5892 increment(to); 5893 decrement(count); 5894 BIND(L_skip_align1); 5895 } 5896 // Two bytes misalignment happens only for byte and short (char) arrays 5897 testptr(to, 2); 5898 jccb(Assembler::zero, L_skip_align2); 5899 movw(Address(to, 0), value); 5900 addptr(to, 2); 5901 subl(count, 1<<(shift-1)); 5902 BIND(L_skip_align2); 5903 } 5904 if (UseSSE < 2) { 5905 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes; 5906 // Fill 32-byte chunks 5907 subl(count, 8 << shift); 5908 jcc(Assembler::less, L_check_fill_8_bytes); 5909 align(16); 5910 5911 BIND(L_fill_32_bytes_loop); 5912 5913 for (int i = 0; i < 32; i += 4) { 5914 movl(Address(to, i), value); 5915 } 5916 5917 addptr(to, 32); 5918 subl(count, 8 << shift); 5919 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop); 5920 BIND(L_check_fill_8_bytes); 5921 addl(count, 8 << shift); 5922 jccb(Assembler::zero, L_exit); 5923 jmpb(L_fill_8_bytes); 5924 5925 // 5926 // length is too short, just fill qwords 5927 // 5928 BIND(L_fill_8_bytes_loop); 5929 movl(Address(to, 0), value); 5930 movl(Address(to, 4), value); 5931 addptr(to, 8); 5932 BIND(L_fill_8_bytes); 5933 subl(count, 1 << (shift + 1)); 5934 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop); 5935 // fall through to fill 4 bytes 5936 } else { 5937 Label L_fill_32_bytes; 5938 if (!UseUnalignedLoadStores) { 5939 // align to 8 bytes, we know we are 4 byte aligned to start 5940 testptr(to, 4); 5941 jccb(Assembler::zero, L_fill_32_bytes); 5942 movl(Address(to, 0), value); 5943 addptr(to, 4); 5944 subl(count, 1<<shift); 5945 } 5946 BIND(L_fill_32_bytes); 5947 { 5948 assert( UseSSE >= 2, "supported cpu only" ); 5949 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes; 5950 movdl(xtmp, value); 5951 if (UseAVX >= 2 && UseUnalignedLoadStores) { 5952 Label L_check_fill_32_bytes; 5953 if (UseAVX > 2) { 5954 // Fill 64-byte chunks 5955 Label L_fill_64_bytes_loop_avx3, L_check_fill_64_bytes_avx2; 5956 5957 // If number of bytes to fill < VM_Version::avx3_threshold(), perform fill using AVX2 5958 cmpl(count, VM_Version::avx3_threshold()); 5959 jccb(Assembler::below, L_check_fill_64_bytes_avx2); 5960 5961 vpbroadcastd(xtmp, xtmp, Assembler::AVX_512bit); 5962 5963 subl(count, 16 << shift); 5964 jccb(Assembler::less, L_check_fill_32_bytes); 5965 align(16); 5966 5967 BIND(L_fill_64_bytes_loop_avx3); 5968 evmovdqul(Address(to, 0), xtmp, Assembler::AVX_512bit); 5969 addptr(to, 64); 5970 subl(count, 16 << shift); 5971 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop_avx3); 5972 jmpb(L_check_fill_32_bytes); 5973 5974 BIND(L_check_fill_64_bytes_avx2); 5975 } 5976 // Fill 64-byte chunks 5977 Label L_fill_64_bytes_loop; 5978 vpbroadcastd(xtmp, xtmp, Assembler::AVX_256bit); 5979 5980 subl(count, 16 << shift); 5981 jcc(Assembler::less, L_check_fill_32_bytes); 5982 align(16); 5983 5984 BIND(L_fill_64_bytes_loop); 5985 vmovdqu(Address(to, 0), xtmp); 5986 vmovdqu(Address(to, 32), xtmp); 5987 addptr(to, 64); 5988 subl(count, 16 << shift); 5989 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop); 5990 5991 BIND(L_check_fill_32_bytes); 5992 addl(count, 8 << shift); 5993 jccb(Assembler::less, L_check_fill_8_bytes); 5994 vmovdqu(Address(to, 0), xtmp); 5995 addptr(to, 32); 5996 subl(count, 8 << shift); 5997 5998 BIND(L_check_fill_8_bytes); 5999 // clean upper bits of YMM registers 6000 movdl(xtmp, value); 6001 pshufd(xtmp, xtmp, 0); 6002 } else { 6003 // Fill 32-byte chunks 6004 pshufd(xtmp, xtmp, 0); 6005 6006 subl(count, 8 << shift); 6007 jcc(Assembler::less, L_check_fill_8_bytes); 6008 align(16); 6009 6010 BIND(L_fill_32_bytes_loop); 6011 6012 if (UseUnalignedLoadStores) { 6013 movdqu(Address(to, 0), xtmp); 6014 movdqu(Address(to, 16), xtmp); 6015 } else { 6016 movq(Address(to, 0), xtmp); 6017 movq(Address(to, 8), xtmp); 6018 movq(Address(to, 16), xtmp); 6019 movq(Address(to, 24), xtmp); 6020 } 6021 6022 addptr(to, 32); 6023 subl(count, 8 << shift); 6024 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop); 6025 6026 BIND(L_check_fill_8_bytes); 6027 } 6028 addl(count, 8 << shift); 6029 jccb(Assembler::zero, L_exit); 6030 jmpb(L_fill_8_bytes); 6031 6032 // 6033 // length is too short, just fill qwords 6034 // 6035 BIND(L_fill_8_bytes_loop); 6036 movq(Address(to, 0), xtmp); 6037 addptr(to, 8); 6038 BIND(L_fill_8_bytes); 6039 subl(count, 1 << (shift + 1)); 6040 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop); 6041 } 6042 } 6043 // fill trailing 4 bytes 6044 BIND(L_fill_4_bytes); 6045 testl(count, 1<<shift); 6046 jccb(Assembler::zero, L_fill_2_bytes); 6047 movl(Address(to, 0), value); 6048 if (t == T_BYTE || t == T_SHORT) { 6049 Label L_fill_byte; 6050 addptr(to, 4); 6051 BIND(L_fill_2_bytes); 6052 // fill trailing 2 bytes 6053 testl(count, 1<<(shift-1)); 6054 jccb(Assembler::zero, L_fill_byte); 6055 movw(Address(to, 0), value); 6056 if (t == T_BYTE) { 6057 addptr(to, 2); 6058 BIND(L_fill_byte); 6059 // fill trailing byte 6060 testl(count, 1); 6061 jccb(Assembler::zero, L_exit); 6062 movb(Address(to, 0), value); 6063 } else { 6064 BIND(L_fill_byte); 6065 } 6066 } else { 6067 BIND(L_fill_2_bytes); 6068 } 6069 BIND(L_exit); 6070 } 6071 6072 void MacroAssembler::evpbroadcast(BasicType type, XMMRegister dst, Register src, int vector_len) { 6073 switch(type) { 6074 case T_BYTE: 6075 case T_BOOLEAN: 6076 evpbroadcastb(dst, src, vector_len); 6077 break; 6078 case T_SHORT: 6079 case T_CHAR: 6080 evpbroadcastw(dst, src, vector_len); 6081 break; 6082 case T_INT: 6083 case T_FLOAT: 6084 evpbroadcastd(dst, src, vector_len); 6085 break; 6086 case T_LONG: 6087 case T_DOUBLE: 6088 evpbroadcastq(dst, src, vector_len); 6089 break; 6090 default: 6091 fatal("Unhandled type : %s", type2name(type)); 6092 break; 6093 } 6094 } 6095 6096 // encode char[] to byte[] in ISO_8859_1 or ASCII 6097 //@IntrinsicCandidate 6098 //private static int implEncodeISOArray(byte[] sa, int sp, 6099 //byte[] da, int dp, int len) { 6100 // int i = 0; 6101 // for (; i < len; i++) { 6102 // char c = StringUTF16.getChar(sa, sp++); 6103 // if (c > '\u00FF') 6104 // break; 6105 // da[dp++] = (byte)c; 6106 // } 6107 // return i; 6108 //} 6109 // 6110 //@IntrinsicCandidate 6111 //private static int implEncodeAsciiArray(char[] sa, int sp, 6112 // byte[] da, int dp, int len) { 6113 // int i = 0; 6114 // for (; i < len; i++) { 6115 // char c = sa[sp++]; 6116 // if (c >= '\u0080') 6117 // break; 6118 // da[dp++] = (byte)c; 6119 // } 6120 // return i; 6121 //} 6122 void MacroAssembler::encode_iso_array(Register src, Register dst, Register len, 6123 XMMRegister tmp1Reg, XMMRegister tmp2Reg, 6124 XMMRegister tmp3Reg, XMMRegister tmp4Reg, 6125 Register tmp5, Register result, bool ascii) { 6126 6127 // rsi: src 6128 // rdi: dst 6129 // rdx: len 6130 // rcx: tmp5 6131 // rax: result 6132 ShortBranchVerifier sbv(this); 6133 assert_different_registers(src, dst, len, tmp5, result); 6134 Label L_done, L_copy_1_char, L_copy_1_char_exit; 6135 6136 int mask = ascii ? 0xff80ff80 : 0xff00ff00; 6137 int short_mask = ascii ? 0xff80 : 0xff00; 6138 6139 // set result 6140 xorl(result, result); 6141 // check for zero length 6142 testl(len, len); 6143 jcc(Assembler::zero, L_done); 6144 6145 movl(result, len); 6146 6147 // Setup pointers 6148 lea(src, Address(src, len, Address::times_2)); // char[] 6149 lea(dst, Address(dst, len, Address::times_1)); // byte[] 6150 negptr(len); 6151 6152 if (UseSSE42Intrinsics || UseAVX >= 2) { 6153 Label L_copy_8_chars, L_copy_8_chars_exit; 6154 Label L_chars_16_check, L_copy_16_chars, L_copy_16_chars_exit; 6155 6156 if (UseAVX >= 2) { 6157 Label L_chars_32_check, L_copy_32_chars, L_copy_32_chars_exit; 6158 movl(tmp5, mask); // create mask to test for Unicode or non-ASCII chars in vector 6159 movdl(tmp1Reg, tmp5); 6160 vpbroadcastd(tmp1Reg, tmp1Reg, Assembler::AVX_256bit); 6161 jmp(L_chars_32_check); 6162 6163 bind(L_copy_32_chars); 6164 vmovdqu(tmp3Reg, Address(src, len, Address::times_2, -64)); 6165 vmovdqu(tmp4Reg, Address(src, len, Address::times_2, -32)); 6166 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1); 6167 vptest(tmp2Reg, tmp1Reg); // check for Unicode or non-ASCII chars in vector 6168 jccb(Assembler::notZero, L_copy_32_chars_exit); 6169 vpackuswb(tmp3Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1); 6170 vpermq(tmp4Reg, tmp3Reg, 0xD8, /* vector_len */ 1); 6171 vmovdqu(Address(dst, len, Address::times_1, -32), tmp4Reg); 6172 6173 bind(L_chars_32_check); 6174 addptr(len, 32); 6175 jcc(Assembler::lessEqual, L_copy_32_chars); 6176 6177 bind(L_copy_32_chars_exit); 6178 subptr(len, 16); 6179 jccb(Assembler::greater, L_copy_16_chars_exit); 6180 6181 } else if (UseSSE42Intrinsics) { 6182 movl(tmp5, mask); // create mask to test for Unicode or non-ASCII chars in vector 6183 movdl(tmp1Reg, tmp5); 6184 pshufd(tmp1Reg, tmp1Reg, 0); 6185 jmpb(L_chars_16_check); 6186 } 6187 6188 bind(L_copy_16_chars); 6189 if (UseAVX >= 2) { 6190 vmovdqu(tmp2Reg, Address(src, len, Address::times_2, -32)); 6191 vptest(tmp2Reg, tmp1Reg); 6192 jcc(Assembler::notZero, L_copy_16_chars_exit); 6193 vpackuswb(tmp2Reg, tmp2Reg, tmp1Reg, /* vector_len */ 1); 6194 vpermq(tmp3Reg, tmp2Reg, 0xD8, /* vector_len */ 1); 6195 } else { 6196 if (UseAVX > 0) { 6197 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32)); 6198 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16)); 6199 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 0); 6200 } else { 6201 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32)); 6202 por(tmp2Reg, tmp3Reg); 6203 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16)); 6204 por(tmp2Reg, tmp4Reg); 6205 } 6206 ptest(tmp2Reg, tmp1Reg); // check for Unicode or non-ASCII chars in vector 6207 jccb(Assembler::notZero, L_copy_16_chars_exit); 6208 packuswb(tmp3Reg, tmp4Reg); 6209 } 6210 movdqu(Address(dst, len, Address::times_1, -16), tmp3Reg); 6211 6212 bind(L_chars_16_check); 6213 addptr(len, 16); 6214 jcc(Assembler::lessEqual, L_copy_16_chars); 6215 6216 bind(L_copy_16_chars_exit); 6217 if (UseAVX >= 2) { 6218 // clean upper bits of YMM registers 6219 vpxor(tmp2Reg, tmp2Reg); 6220 vpxor(tmp3Reg, tmp3Reg); 6221 vpxor(tmp4Reg, tmp4Reg); 6222 movdl(tmp1Reg, tmp5); 6223 pshufd(tmp1Reg, tmp1Reg, 0); 6224 } 6225 subptr(len, 8); 6226 jccb(Assembler::greater, L_copy_8_chars_exit); 6227 6228 bind(L_copy_8_chars); 6229 movdqu(tmp3Reg, Address(src, len, Address::times_2, -16)); 6230 ptest(tmp3Reg, tmp1Reg); 6231 jccb(Assembler::notZero, L_copy_8_chars_exit); 6232 packuswb(tmp3Reg, tmp1Reg); 6233 movq(Address(dst, len, Address::times_1, -8), tmp3Reg); 6234 addptr(len, 8); 6235 jccb(Assembler::lessEqual, L_copy_8_chars); 6236 6237 bind(L_copy_8_chars_exit); 6238 subptr(len, 8); 6239 jccb(Assembler::zero, L_done); 6240 } 6241 6242 bind(L_copy_1_char); 6243 load_unsigned_short(tmp5, Address(src, len, Address::times_2, 0)); 6244 testl(tmp5, short_mask); // check if Unicode or non-ASCII char 6245 jccb(Assembler::notZero, L_copy_1_char_exit); 6246 movb(Address(dst, len, Address::times_1, 0), tmp5); 6247 addptr(len, 1); 6248 jccb(Assembler::less, L_copy_1_char); 6249 6250 bind(L_copy_1_char_exit); 6251 addptr(result, len); // len is negative count of not processed elements 6252 6253 bind(L_done); 6254 } 6255 6256 #ifdef _LP64 6257 /** 6258 * Helper for multiply_to_len(). 6259 */ 6260 void MacroAssembler::add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) { 6261 addq(dest_lo, src1); 6262 adcq(dest_hi, 0); 6263 addq(dest_lo, src2); 6264 adcq(dest_hi, 0); 6265 } 6266 6267 /** 6268 * Multiply 64 bit by 64 bit first loop. 6269 */ 6270 void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart, 6271 Register y, Register y_idx, Register z, 6272 Register carry, Register product, 6273 Register idx, Register kdx) { 6274 // 6275 // jlong carry, x[], y[], z[]; 6276 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) { 6277 // huge_128 product = y[idx] * x[xstart] + carry; 6278 // z[kdx] = (jlong)product; 6279 // carry = (jlong)(product >>> 64); 6280 // } 6281 // z[xstart] = carry; 6282 // 6283 6284 Label L_first_loop, L_first_loop_exit; 6285 Label L_one_x, L_one_y, L_multiply; 6286 6287 decrementl(xstart); 6288 jcc(Assembler::negative, L_one_x); 6289 6290 movq(x_xstart, Address(x, xstart, Address::times_4, 0)); 6291 rorq(x_xstart, 32); // convert big-endian to little-endian 6292 6293 bind(L_first_loop); 6294 decrementl(idx); 6295 jcc(Assembler::negative, L_first_loop_exit); 6296 decrementl(idx); 6297 jcc(Assembler::negative, L_one_y); 6298 movq(y_idx, Address(y, idx, Address::times_4, 0)); 6299 rorq(y_idx, 32); // convert big-endian to little-endian 6300 bind(L_multiply); 6301 movq(product, x_xstart); 6302 mulq(y_idx); // product(rax) * y_idx -> rdx:rax 6303 addq(product, carry); 6304 adcq(rdx, 0); 6305 subl(kdx, 2); 6306 movl(Address(z, kdx, Address::times_4, 4), product); 6307 shrq(product, 32); 6308 movl(Address(z, kdx, Address::times_4, 0), product); 6309 movq(carry, rdx); 6310 jmp(L_first_loop); 6311 6312 bind(L_one_y); 6313 movl(y_idx, Address(y, 0)); 6314 jmp(L_multiply); 6315 6316 bind(L_one_x); 6317 movl(x_xstart, Address(x, 0)); 6318 jmp(L_first_loop); 6319 6320 bind(L_first_loop_exit); 6321 } 6322 6323 /** 6324 * Multiply 64 bit by 64 bit and add 128 bit. 6325 */ 6326 void MacroAssembler::multiply_add_128_x_128(Register x_xstart, Register y, Register z, 6327 Register yz_idx, Register idx, 6328 Register carry, Register product, int offset) { 6329 // huge_128 product = (y[idx] * x_xstart) + z[kdx] + carry; 6330 // z[kdx] = (jlong)product; 6331 6332 movq(yz_idx, Address(y, idx, Address::times_4, offset)); 6333 rorq(yz_idx, 32); // convert big-endian to little-endian 6334 movq(product, x_xstart); 6335 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax) 6336 movq(yz_idx, Address(z, idx, Address::times_4, offset)); 6337 rorq(yz_idx, 32); // convert big-endian to little-endian 6338 6339 add2_with_carry(rdx, product, carry, yz_idx); 6340 6341 movl(Address(z, idx, Address::times_4, offset+4), product); 6342 shrq(product, 32); 6343 movl(Address(z, idx, Address::times_4, offset), product); 6344 6345 } 6346 6347 /** 6348 * Multiply 128 bit by 128 bit. Unrolled inner loop. 6349 */ 6350 void MacroAssembler::multiply_128_x_128_loop(Register x_xstart, Register y, Register z, 6351 Register yz_idx, Register idx, Register jdx, 6352 Register carry, Register product, 6353 Register carry2) { 6354 // jlong carry, x[], y[], z[]; 6355 // int kdx = ystart+1; 6356 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop 6357 // huge_128 product = (y[idx+1] * x_xstart) + z[kdx+idx+1] + carry; 6358 // z[kdx+idx+1] = (jlong)product; 6359 // jlong carry2 = (jlong)(product >>> 64); 6360 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry2; 6361 // z[kdx+idx] = (jlong)product; 6362 // carry = (jlong)(product >>> 64); 6363 // } 6364 // idx += 2; 6365 // if (idx > 0) { 6366 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry; 6367 // z[kdx+idx] = (jlong)product; 6368 // carry = (jlong)(product >>> 64); 6369 // } 6370 // 6371 6372 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done; 6373 6374 movl(jdx, idx); 6375 andl(jdx, 0xFFFFFFFC); 6376 shrl(jdx, 2); 6377 6378 bind(L_third_loop); 6379 subl(jdx, 1); 6380 jcc(Assembler::negative, L_third_loop_exit); 6381 subl(idx, 4); 6382 6383 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 8); 6384 movq(carry2, rdx); 6385 6386 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry2, product, 0); 6387 movq(carry, rdx); 6388 jmp(L_third_loop); 6389 6390 bind (L_third_loop_exit); 6391 6392 andl (idx, 0x3); 6393 jcc(Assembler::zero, L_post_third_loop_done); 6394 6395 Label L_check_1; 6396 subl(idx, 2); 6397 jcc(Assembler::negative, L_check_1); 6398 6399 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 0); 6400 movq(carry, rdx); 6401 6402 bind (L_check_1); 6403 addl (idx, 0x2); 6404 andl (idx, 0x1); 6405 subl(idx, 1); 6406 jcc(Assembler::negative, L_post_third_loop_done); 6407 6408 movl(yz_idx, Address(y, idx, Address::times_4, 0)); 6409 movq(product, x_xstart); 6410 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax) 6411 movl(yz_idx, Address(z, idx, Address::times_4, 0)); 6412 6413 add2_with_carry(rdx, product, yz_idx, carry); 6414 6415 movl(Address(z, idx, Address::times_4, 0), product); 6416 shrq(product, 32); 6417 6418 shlq(rdx, 32); 6419 orq(product, rdx); 6420 movq(carry, product); 6421 6422 bind(L_post_third_loop_done); 6423 } 6424 6425 /** 6426 * Multiply 128 bit by 128 bit using BMI2. Unrolled inner loop. 6427 * 6428 */ 6429 void MacroAssembler::multiply_128_x_128_bmi2_loop(Register y, Register z, 6430 Register carry, Register carry2, 6431 Register idx, Register jdx, 6432 Register yz_idx1, Register yz_idx2, 6433 Register tmp, Register tmp3, Register tmp4) { 6434 assert(UseBMI2Instructions, "should be used only when BMI2 is available"); 6435 6436 // jlong carry, x[], y[], z[]; 6437 // int kdx = ystart+1; 6438 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop 6439 // huge_128 tmp3 = (y[idx+1] * rdx) + z[kdx+idx+1] + carry; 6440 // jlong carry2 = (jlong)(tmp3 >>> 64); 6441 // huge_128 tmp4 = (y[idx] * rdx) + z[kdx+idx] + carry2; 6442 // carry = (jlong)(tmp4 >>> 64); 6443 // z[kdx+idx+1] = (jlong)tmp3; 6444 // z[kdx+idx] = (jlong)tmp4; 6445 // } 6446 // idx += 2; 6447 // if (idx > 0) { 6448 // yz_idx1 = (y[idx] * rdx) + z[kdx+idx] + carry; 6449 // z[kdx+idx] = (jlong)yz_idx1; 6450 // carry = (jlong)(yz_idx1 >>> 64); 6451 // } 6452 // 6453 6454 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done; 6455 6456 movl(jdx, idx); 6457 andl(jdx, 0xFFFFFFFC); 6458 shrl(jdx, 2); 6459 6460 bind(L_third_loop); 6461 subl(jdx, 1); 6462 jcc(Assembler::negative, L_third_loop_exit); 6463 subl(idx, 4); 6464 6465 movq(yz_idx1, Address(y, idx, Address::times_4, 8)); 6466 rorxq(yz_idx1, yz_idx1, 32); // convert big-endian to little-endian 6467 movq(yz_idx2, Address(y, idx, Address::times_4, 0)); 6468 rorxq(yz_idx2, yz_idx2, 32); 6469 6470 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3 6471 mulxq(carry2, tmp, yz_idx2); // yz_idx2 * rdx -> carry2:tmp 6472 6473 movq(yz_idx1, Address(z, idx, Address::times_4, 8)); 6474 rorxq(yz_idx1, yz_idx1, 32); 6475 movq(yz_idx2, Address(z, idx, Address::times_4, 0)); 6476 rorxq(yz_idx2, yz_idx2, 32); 6477 6478 if (VM_Version::supports_adx()) { 6479 adcxq(tmp3, carry); 6480 adoxq(tmp3, yz_idx1); 6481 6482 adcxq(tmp4, tmp); 6483 adoxq(tmp4, yz_idx2); 6484 6485 movl(carry, 0); // does not affect flags 6486 adcxq(carry2, carry); 6487 adoxq(carry2, carry); 6488 } else { 6489 add2_with_carry(tmp4, tmp3, carry, yz_idx1); 6490 add2_with_carry(carry2, tmp4, tmp, yz_idx2); 6491 } 6492 movq(carry, carry2); 6493 6494 movl(Address(z, idx, Address::times_4, 12), tmp3); 6495 shrq(tmp3, 32); 6496 movl(Address(z, idx, Address::times_4, 8), tmp3); 6497 6498 movl(Address(z, idx, Address::times_4, 4), tmp4); 6499 shrq(tmp4, 32); 6500 movl(Address(z, idx, Address::times_4, 0), tmp4); 6501 6502 jmp(L_third_loop); 6503 6504 bind (L_third_loop_exit); 6505 6506 andl (idx, 0x3); 6507 jcc(Assembler::zero, L_post_third_loop_done); 6508 6509 Label L_check_1; 6510 subl(idx, 2); 6511 jcc(Assembler::negative, L_check_1); 6512 6513 movq(yz_idx1, Address(y, idx, Address::times_4, 0)); 6514 rorxq(yz_idx1, yz_idx1, 32); 6515 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3 6516 movq(yz_idx2, Address(z, idx, Address::times_4, 0)); 6517 rorxq(yz_idx2, yz_idx2, 32); 6518 6519 add2_with_carry(tmp4, tmp3, carry, yz_idx2); 6520 6521 movl(Address(z, idx, Address::times_4, 4), tmp3); 6522 shrq(tmp3, 32); 6523 movl(Address(z, idx, Address::times_4, 0), tmp3); 6524 movq(carry, tmp4); 6525 6526 bind (L_check_1); 6527 addl (idx, 0x2); 6528 andl (idx, 0x1); 6529 subl(idx, 1); 6530 jcc(Assembler::negative, L_post_third_loop_done); 6531 movl(tmp4, Address(y, idx, Address::times_4, 0)); 6532 mulxq(carry2, tmp3, tmp4); // tmp4 * rdx -> carry2:tmp3 6533 movl(tmp4, Address(z, idx, Address::times_4, 0)); 6534 6535 add2_with_carry(carry2, tmp3, tmp4, carry); 6536 6537 movl(Address(z, idx, Address::times_4, 0), tmp3); 6538 shrq(tmp3, 32); 6539 6540 shlq(carry2, 32); 6541 orq(tmp3, carry2); 6542 movq(carry, tmp3); 6543 6544 bind(L_post_third_loop_done); 6545 } 6546 6547 /** 6548 * Code for BigInteger::multiplyToLen() intrinsic. 6549 * 6550 * rdi: x 6551 * rax: xlen 6552 * rsi: y 6553 * rcx: ylen 6554 * r8: z 6555 * r11: zlen 6556 * r12: tmp1 6557 * r13: tmp2 6558 * r14: tmp3 6559 * r15: tmp4 6560 * rbx: tmp5 6561 * 6562 */ 6563 void MacroAssembler::multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register zlen, 6564 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5) { 6565 ShortBranchVerifier sbv(this); 6566 assert_different_registers(x, xlen, y, ylen, z, zlen, tmp1, tmp2, tmp3, tmp4, tmp5, rdx); 6567 6568 push(tmp1); 6569 push(tmp2); 6570 push(tmp3); 6571 push(tmp4); 6572 push(tmp5); 6573 6574 push(xlen); 6575 push(zlen); 6576 6577 const Register idx = tmp1; 6578 const Register kdx = tmp2; 6579 const Register xstart = tmp3; 6580 6581 const Register y_idx = tmp4; 6582 const Register carry = tmp5; 6583 const Register product = xlen; 6584 const Register x_xstart = zlen; // reuse register 6585 6586 // First Loop. 6587 // 6588 // final static long LONG_MASK = 0xffffffffL; 6589 // int xstart = xlen - 1; 6590 // int ystart = ylen - 1; 6591 // long carry = 0; 6592 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) { 6593 // long product = (y[idx] & LONG_MASK) * (x[xstart] & LONG_MASK) + carry; 6594 // z[kdx] = (int)product; 6595 // carry = product >>> 32; 6596 // } 6597 // z[xstart] = (int)carry; 6598 // 6599 6600 movl(idx, ylen); // idx = ylen; 6601 movl(kdx, zlen); // kdx = xlen+ylen; 6602 xorq(carry, carry); // carry = 0; 6603 6604 Label L_done; 6605 6606 movl(xstart, xlen); 6607 decrementl(xstart); 6608 jcc(Assembler::negative, L_done); 6609 6610 multiply_64_x_64_loop(x, xstart, x_xstart, y, y_idx, z, carry, product, idx, kdx); 6611 6612 Label L_second_loop; 6613 testl(kdx, kdx); 6614 jcc(Assembler::zero, L_second_loop); 6615 6616 Label L_carry; 6617 subl(kdx, 1); 6618 jcc(Assembler::zero, L_carry); 6619 6620 movl(Address(z, kdx, Address::times_4, 0), carry); 6621 shrq(carry, 32); 6622 subl(kdx, 1); 6623 6624 bind(L_carry); 6625 movl(Address(z, kdx, Address::times_4, 0), carry); 6626 6627 // Second and third (nested) loops. 6628 // 6629 // for (int i = xstart-1; i >= 0; i--) { // Second loop 6630 // carry = 0; 6631 // for (int jdx=ystart, k=ystart+1+i; jdx >= 0; jdx--, k--) { // Third loop 6632 // long product = (y[jdx] & LONG_MASK) * (x[i] & LONG_MASK) + 6633 // (z[k] & LONG_MASK) + carry; 6634 // z[k] = (int)product; 6635 // carry = product >>> 32; 6636 // } 6637 // z[i] = (int)carry; 6638 // } 6639 // 6640 // i = xlen, j = tmp1, k = tmp2, carry = tmp5, x[i] = rdx 6641 6642 const Register jdx = tmp1; 6643 6644 bind(L_second_loop); 6645 xorl(carry, carry); // carry = 0; 6646 movl(jdx, ylen); // j = ystart+1 6647 6648 subl(xstart, 1); // i = xstart-1; 6649 jcc(Assembler::negative, L_done); 6650 6651 push (z); 6652 6653 Label L_last_x; 6654 lea(z, Address(z, xstart, Address::times_4, 4)); // z = z + k - j 6655 subl(xstart, 1); // i = xstart-1; 6656 jcc(Assembler::negative, L_last_x); 6657 6658 if (UseBMI2Instructions) { 6659 movq(rdx, Address(x, xstart, Address::times_4, 0)); 6660 rorxq(rdx, rdx, 32); // convert big-endian to little-endian 6661 } else { 6662 movq(x_xstart, Address(x, xstart, Address::times_4, 0)); 6663 rorq(x_xstart, 32); // convert big-endian to little-endian 6664 } 6665 6666 Label L_third_loop_prologue; 6667 bind(L_third_loop_prologue); 6668 6669 push (x); 6670 push (xstart); 6671 push (ylen); 6672 6673 6674 if (UseBMI2Instructions) { 6675 multiply_128_x_128_bmi2_loop(y, z, carry, x, jdx, ylen, product, tmp2, x_xstart, tmp3, tmp4); 6676 } else { // !UseBMI2Instructions 6677 multiply_128_x_128_loop(x_xstart, y, z, y_idx, jdx, ylen, carry, product, x); 6678 } 6679 6680 pop(ylen); 6681 pop(xlen); 6682 pop(x); 6683 pop(z); 6684 6685 movl(tmp3, xlen); 6686 addl(tmp3, 1); 6687 movl(Address(z, tmp3, Address::times_4, 0), carry); 6688 subl(tmp3, 1); 6689 jccb(Assembler::negative, L_done); 6690 6691 shrq(carry, 32); 6692 movl(Address(z, tmp3, Address::times_4, 0), carry); 6693 jmp(L_second_loop); 6694 6695 // Next infrequent code is moved outside loops. 6696 bind(L_last_x); 6697 if (UseBMI2Instructions) { 6698 movl(rdx, Address(x, 0)); 6699 } else { 6700 movl(x_xstart, Address(x, 0)); 6701 } 6702 jmp(L_third_loop_prologue); 6703 6704 bind(L_done); 6705 6706 pop(zlen); 6707 pop(xlen); 6708 6709 pop(tmp5); 6710 pop(tmp4); 6711 pop(tmp3); 6712 pop(tmp2); 6713 pop(tmp1); 6714 } 6715 6716 void MacroAssembler::vectorized_mismatch(Register obja, Register objb, Register length, Register log2_array_indxscale, 6717 Register result, Register tmp1, Register tmp2, XMMRegister rymm0, XMMRegister rymm1, XMMRegister rymm2){ 6718 assert(UseSSE42Intrinsics, "SSE4.2 must be enabled."); 6719 Label VECTOR16_LOOP, VECTOR8_LOOP, VECTOR4_LOOP; 6720 Label VECTOR8_TAIL, VECTOR4_TAIL; 6721 Label VECTOR32_NOT_EQUAL, VECTOR16_NOT_EQUAL, VECTOR8_NOT_EQUAL, VECTOR4_NOT_EQUAL; 6722 Label SAME_TILL_END, DONE; 6723 Label BYTES_LOOP, BYTES_TAIL, BYTES_NOT_EQUAL; 6724 6725 //scale is in rcx in both Win64 and Unix 6726 ShortBranchVerifier sbv(this); 6727 6728 shlq(length); 6729 xorq(result, result); 6730 6731 if ((AVX3Threshold == 0) && (UseAVX > 2) && 6732 VM_Version::supports_avx512vlbw()) { 6733 Label VECTOR64_LOOP, VECTOR64_NOT_EQUAL, VECTOR32_TAIL; 6734 6735 cmpq(length, 64); 6736 jcc(Assembler::less, VECTOR32_TAIL); 6737 6738 movq(tmp1, length); 6739 andq(tmp1, 0x3F); // tail count 6740 andq(length, ~(0x3F)); //vector count 6741 6742 bind(VECTOR64_LOOP); 6743 // AVX512 code to compare 64 byte vectors. 6744 evmovdqub(rymm0, Address(obja, result), Assembler::AVX_512bit); 6745 evpcmpeqb(k7, rymm0, Address(objb, result), Assembler::AVX_512bit); 6746 kortestql(k7, k7); 6747 jcc(Assembler::aboveEqual, VECTOR64_NOT_EQUAL); // mismatch 6748 addq(result, 64); 6749 subq(length, 64); 6750 jccb(Assembler::notZero, VECTOR64_LOOP); 6751 6752 //bind(VECTOR64_TAIL); 6753 testq(tmp1, tmp1); 6754 jcc(Assembler::zero, SAME_TILL_END); 6755 6756 //bind(VECTOR64_TAIL); 6757 // AVX512 code to compare up to 63 byte vectors. 6758 mov64(tmp2, 0xFFFFFFFFFFFFFFFF); 6759 shlxq(tmp2, tmp2, tmp1); 6760 notq(tmp2); 6761 kmovql(k3, tmp2); 6762 6763 evmovdqub(rymm0, k3, Address(obja, result), false, Assembler::AVX_512bit); 6764 evpcmpeqb(k7, k3, rymm0, Address(objb, result), Assembler::AVX_512bit); 6765 6766 ktestql(k7, k3); 6767 jcc(Assembler::below, SAME_TILL_END); // not mismatch 6768 6769 bind(VECTOR64_NOT_EQUAL); 6770 kmovql(tmp1, k7); 6771 notq(tmp1); 6772 tzcntq(tmp1, tmp1); 6773 addq(result, tmp1); 6774 shrq(result); 6775 jmp(DONE); 6776 bind(VECTOR32_TAIL); 6777 } 6778 6779 cmpq(length, 8); 6780 jcc(Assembler::equal, VECTOR8_LOOP); 6781 jcc(Assembler::less, VECTOR4_TAIL); 6782 6783 if (UseAVX >= 2) { 6784 Label VECTOR16_TAIL, VECTOR32_LOOP; 6785 6786 cmpq(length, 16); 6787 jcc(Assembler::equal, VECTOR16_LOOP); 6788 jcc(Assembler::less, VECTOR8_LOOP); 6789 6790 cmpq(length, 32); 6791 jccb(Assembler::less, VECTOR16_TAIL); 6792 6793 subq(length, 32); 6794 bind(VECTOR32_LOOP); 6795 vmovdqu(rymm0, Address(obja, result)); 6796 vmovdqu(rymm1, Address(objb, result)); 6797 vpxor(rymm2, rymm0, rymm1, Assembler::AVX_256bit); 6798 vptest(rymm2, rymm2); 6799 jcc(Assembler::notZero, VECTOR32_NOT_EQUAL);//mismatch found 6800 addq(result, 32); 6801 subq(length, 32); 6802 jcc(Assembler::greaterEqual, VECTOR32_LOOP); 6803 addq(length, 32); 6804 jcc(Assembler::equal, SAME_TILL_END); 6805 //falling through if less than 32 bytes left //close the branch here. 6806 6807 bind(VECTOR16_TAIL); 6808 cmpq(length, 16); 6809 jccb(Assembler::less, VECTOR8_TAIL); 6810 bind(VECTOR16_LOOP); 6811 movdqu(rymm0, Address(obja, result)); 6812 movdqu(rymm1, Address(objb, result)); 6813 vpxor(rymm2, rymm0, rymm1, Assembler::AVX_128bit); 6814 ptest(rymm2, rymm2); 6815 jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found 6816 addq(result, 16); 6817 subq(length, 16); 6818 jcc(Assembler::equal, SAME_TILL_END); 6819 //falling through if less than 16 bytes left 6820 } else {//regular intrinsics 6821 6822 cmpq(length, 16); 6823 jccb(Assembler::less, VECTOR8_TAIL); 6824 6825 subq(length, 16); 6826 bind(VECTOR16_LOOP); 6827 movdqu(rymm0, Address(obja, result)); 6828 movdqu(rymm1, Address(objb, result)); 6829 pxor(rymm0, rymm1); 6830 ptest(rymm0, rymm0); 6831 jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found 6832 addq(result, 16); 6833 subq(length, 16); 6834 jccb(Assembler::greaterEqual, VECTOR16_LOOP); 6835 addq(length, 16); 6836 jcc(Assembler::equal, SAME_TILL_END); 6837 //falling through if less than 16 bytes left 6838 } 6839 6840 bind(VECTOR8_TAIL); 6841 cmpq(length, 8); 6842 jccb(Assembler::less, VECTOR4_TAIL); 6843 bind(VECTOR8_LOOP); 6844 movq(tmp1, Address(obja, result)); 6845 movq(tmp2, Address(objb, result)); 6846 xorq(tmp1, tmp2); 6847 testq(tmp1, tmp1); 6848 jcc(Assembler::notZero, VECTOR8_NOT_EQUAL);//mismatch found 6849 addq(result, 8); 6850 subq(length, 8); 6851 jcc(Assembler::equal, SAME_TILL_END); 6852 //falling through if less than 8 bytes left 6853 6854 bind(VECTOR4_TAIL); 6855 cmpq(length, 4); 6856 jccb(Assembler::less, BYTES_TAIL); 6857 bind(VECTOR4_LOOP); 6858 movl(tmp1, Address(obja, result)); 6859 xorl(tmp1, Address(objb, result)); 6860 testl(tmp1, tmp1); 6861 jcc(Assembler::notZero, VECTOR4_NOT_EQUAL);//mismatch found 6862 addq(result, 4); 6863 subq(length, 4); 6864 jcc(Assembler::equal, SAME_TILL_END); 6865 //falling through if less than 4 bytes left 6866 6867 bind(BYTES_TAIL); 6868 bind(BYTES_LOOP); 6869 load_unsigned_byte(tmp1, Address(obja, result)); 6870 load_unsigned_byte(tmp2, Address(objb, result)); 6871 xorl(tmp1, tmp2); 6872 testl(tmp1, tmp1); 6873 jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found 6874 decq(length); 6875 jcc(Assembler::zero, SAME_TILL_END); 6876 incq(result); 6877 load_unsigned_byte(tmp1, Address(obja, result)); 6878 load_unsigned_byte(tmp2, Address(objb, result)); 6879 xorl(tmp1, tmp2); 6880 testl(tmp1, tmp1); 6881 jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found 6882 decq(length); 6883 jcc(Assembler::zero, SAME_TILL_END); 6884 incq(result); 6885 load_unsigned_byte(tmp1, Address(obja, result)); 6886 load_unsigned_byte(tmp2, Address(objb, result)); 6887 xorl(tmp1, tmp2); 6888 testl(tmp1, tmp1); 6889 jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found 6890 jmp(SAME_TILL_END); 6891 6892 if (UseAVX >= 2) { 6893 bind(VECTOR32_NOT_EQUAL); 6894 vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_256bit); 6895 vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_256bit); 6896 vpxor(rymm0, rymm0, rymm2, Assembler::AVX_256bit); 6897 vpmovmskb(tmp1, rymm0); 6898 bsfq(tmp1, tmp1); 6899 addq(result, tmp1); 6900 shrq(result); 6901 jmp(DONE); 6902 } 6903 6904 bind(VECTOR16_NOT_EQUAL); 6905 if (UseAVX >= 2) { 6906 vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_128bit); 6907 vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_128bit); 6908 pxor(rymm0, rymm2); 6909 } else { 6910 pcmpeqb(rymm2, rymm2); 6911 pxor(rymm0, rymm1); 6912 pcmpeqb(rymm0, rymm1); 6913 pxor(rymm0, rymm2); 6914 } 6915 pmovmskb(tmp1, rymm0); 6916 bsfq(tmp1, tmp1); 6917 addq(result, tmp1); 6918 shrq(result); 6919 jmpb(DONE); 6920 6921 bind(VECTOR8_NOT_EQUAL); 6922 bind(VECTOR4_NOT_EQUAL); 6923 bsfq(tmp1, tmp1); 6924 shrq(tmp1, 3); 6925 addq(result, tmp1); 6926 bind(BYTES_NOT_EQUAL); 6927 shrq(result); 6928 jmpb(DONE); 6929 6930 bind(SAME_TILL_END); 6931 mov64(result, -1); 6932 6933 bind(DONE); 6934 } 6935 6936 //Helper functions for square_to_len() 6937 6938 /** 6939 * Store the squares of x[], right shifted one bit (divided by 2) into z[] 6940 * Preserves x and z and modifies rest of the registers. 6941 */ 6942 void MacroAssembler::square_rshift(Register x, Register xlen, Register z, Register tmp1, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) { 6943 // Perform square and right shift by 1 6944 // Handle odd xlen case first, then for even xlen do the following 6945 // jlong carry = 0; 6946 // for (int j=0, i=0; j < xlen; j+=2, i+=4) { 6947 // huge_128 product = x[j:j+1] * x[j:j+1]; 6948 // z[i:i+1] = (carry << 63) | (jlong)(product >>> 65); 6949 // z[i+2:i+3] = (jlong)(product >>> 1); 6950 // carry = (jlong)product; 6951 // } 6952 6953 xorq(tmp5, tmp5); // carry 6954 xorq(rdxReg, rdxReg); 6955 xorl(tmp1, tmp1); // index for x 6956 xorl(tmp4, tmp4); // index for z 6957 6958 Label L_first_loop, L_first_loop_exit; 6959 6960 testl(xlen, 1); 6961 jccb(Assembler::zero, L_first_loop); //jump if xlen is even 6962 6963 // Square and right shift by 1 the odd element using 32 bit multiply 6964 movl(raxReg, Address(x, tmp1, Address::times_4, 0)); 6965 imulq(raxReg, raxReg); 6966 shrq(raxReg, 1); 6967 adcq(tmp5, 0); 6968 movq(Address(z, tmp4, Address::times_4, 0), raxReg); 6969 incrementl(tmp1); 6970 addl(tmp4, 2); 6971 6972 // Square and right shift by 1 the rest using 64 bit multiply 6973 bind(L_first_loop); 6974 cmpptr(tmp1, xlen); 6975 jccb(Assembler::equal, L_first_loop_exit); 6976 6977 // Square 6978 movq(raxReg, Address(x, tmp1, Address::times_4, 0)); 6979 rorq(raxReg, 32); // convert big-endian to little-endian 6980 mulq(raxReg); // 64-bit multiply rax * rax -> rdx:rax 6981 6982 // Right shift by 1 and save carry 6983 shrq(tmp5, 1); // rdx:rax:tmp5 = (tmp5:rdx:rax) >>> 1 6984 rcrq(rdxReg, 1); 6985 rcrq(raxReg, 1); 6986 adcq(tmp5, 0); 6987 6988 // Store result in z 6989 movq(Address(z, tmp4, Address::times_4, 0), rdxReg); 6990 movq(Address(z, tmp4, Address::times_4, 8), raxReg); 6991 6992 // Update indices for x and z 6993 addl(tmp1, 2); 6994 addl(tmp4, 4); 6995 jmp(L_first_loop); 6996 6997 bind(L_first_loop_exit); 6998 } 6999 7000 7001 /** 7002 * Perform the following multiply add operation using BMI2 instructions 7003 * carry:sum = sum + op1*op2 + carry 7004 * op2 should be in rdx 7005 * op2 is preserved, all other registers are modified 7006 */ 7007 void MacroAssembler::multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry, Register tmp2) { 7008 // assert op2 is rdx 7009 mulxq(tmp2, op1, op1); // op1 * op2 -> tmp2:op1 7010 addq(sum, carry); 7011 adcq(tmp2, 0); 7012 addq(sum, op1); 7013 adcq(tmp2, 0); 7014 movq(carry, tmp2); 7015 } 7016 7017 /** 7018 * Perform the following multiply add operation: 7019 * carry:sum = sum + op1*op2 + carry 7020 * Preserves op1, op2 and modifies rest of registers 7021 */ 7022 void MacroAssembler::multiply_add_64(Register sum, Register op1, Register op2, Register carry, Register rdxReg, Register raxReg) { 7023 // rdx:rax = op1 * op2 7024 movq(raxReg, op2); 7025 mulq(op1); 7026 7027 // rdx:rax = sum + carry + rdx:rax 7028 addq(sum, carry); 7029 adcq(rdxReg, 0); 7030 addq(sum, raxReg); 7031 adcq(rdxReg, 0); 7032 7033 // carry:sum = rdx:sum 7034 movq(carry, rdxReg); 7035 } 7036 7037 /** 7038 * Add 64 bit long carry into z[] with carry propagation. 7039 * Preserves z and carry register values and modifies rest of registers. 7040 * 7041 */ 7042 void MacroAssembler::add_one_64(Register z, Register zlen, Register carry, Register tmp1) { 7043 Label L_fourth_loop, L_fourth_loop_exit; 7044 7045 movl(tmp1, 1); 7046 subl(zlen, 2); 7047 addq(Address(z, zlen, Address::times_4, 0), carry); 7048 7049 bind(L_fourth_loop); 7050 jccb(Assembler::carryClear, L_fourth_loop_exit); 7051 subl(zlen, 2); 7052 jccb(Assembler::negative, L_fourth_loop_exit); 7053 addq(Address(z, zlen, Address::times_4, 0), tmp1); 7054 jmp(L_fourth_loop); 7055 bind(L_fourth_loop_exit); 7056 } 7057 7058 /** 7059 * Shift z[] left by 1 bit. 7060 * Preserves x, len, z and zlen registers and modifies rest of the registers. 7061 * 7062 */ 7063 void MacroAssembler::lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4) { 7064 7065 Label L_fifth_loop, L_fifth_loop_exit; 7066 7067 // Fifth loop 7068 // Perform primitiveLeftShift(z, zlen, 1) 7069 7070 const Register prev_carry = tmp1; 7071 const Register new_carry = tmp4; 7072 const Register value = tmp2; 7073 const Register zidx = tmp3; 7074 7075 // int zidx, carry; 7076 // long value; 7077 // carry = 0; 7078 // for (zidx = zlen-2; zidx >=0; zidx -= 2) { 7079 // (carry:value) = (z[i] << 1) | carry ; 7080 // z[i] = value; 7081 // } 7082 7083 movl(zidx, zlen); 7084 xorl(prev_carry, prev_carry); // clear carry flag and prev_carry register 7085 7086 bind(L_fifth_loop); 7087 decl(zidx); // Use decl to preserve carry flag 7088 decl(zidx); 7089 jccb(Assembler::negative, L_fifth_loop_exit); 7090 7091 if (UseBMI2Instructions) { 7092 movq(value, Address(z, zidx, Address::times_4, 0)); 7093 rclq(value, 1); 7094 rorxq(value, value, 32); 7095 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form 7096 } 7097 else { 7098 // clear new_carry 7099 xorl(new_carry, new_carry); 7100 7101 // Shift z[i] by 1, or in previous carry and save new carry 7102 movq(value, Address(z, zidx, Address::times_4, 0)); 7103 shlq(value, 1); 7104 adcl(new_carry, 0); 7105 7106 orq(value, prev_carry); 7107 rorq(value, 0x20); 7108 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form 7109 7110 // Set previous carry = new carry 7111 movl(prev_carry, new_carry); 7112 } 7113 jmp(L_fifth_loop); 7114 7115 bind(L_fifth_loop_exit); 7116 } 7117 7118 7119 /** 7120 * Code for BigInteger::squareToLen() intrinsic 7121 * 7122 * rdi: x 7123 * rsi: len 7124 * r8: z 7125 * rcx: zlen 7126 * r12: tmp1 7127 * r13: tmp2 7128 * r14: tmp3 7129 * r15: tmp4 7130 * rbx: tmp5 7131 * 7132 */ 7133 void MacroAssembler::square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) { 7134 7135 Label L_second_loop, L_second_loop_exit, L_third_loop, L_third_loop_exit, L_last_x, L_multiply; 7136 push(tmp1); 7137 push(tmp2); 7138 push(tmp3); 7139 push(tmp4); 7140 push(tmp5); 7141 7142 // First loop 7143 // Store the squares, right shifted one bit (i.e., divided by 2). 7144 square_rshift(x, len, z, tmp1, tmp3, tmp4, tmp5, rdxReg, raxReg); 7145 7146 // Add in off-diagonal sums. 7147 // 7148 // Second, third (nested) and fourth loops. 7149 // zlen +=2; 7150 // for (int xidx=len-2,zidx=zlen-4; xidx > 0; xidx-=2,zidx-=4) { 7151 // carry = 0; 7152 // long op2 = x[xidx:xidx+1]; 7153 // for (int j=xidx-2,k=zidx; j >= 0; j-=2) { 7154 // k -= 2; 7155 // long op1 = x[j:j+1]; 7156 // long sum = z[k:k+1]; 7157 // carry:sum = multiply_add_64(sum, op1, op2, carry, tmp_regs); 7158 // z[k:k+1] = sum; 7159 // } 7160 // add_one_64(z, k, carry, tmp_regs); 7161 // } 7162 7163 const Register carry = tmp5; 7164 const Register sum = tmp3; 7165 const Register op1 = tmp4; 7166 Register op2 = tmp2; 7167 7168 push(zlen); 7169 push(len); 7170 addl(zlen,2); 7171 bind(L_second_loop); 7172 xorq(carry, carry); 7173 subl(zlen, 4); 7174 subl(len, 2); 7175 push(zlen); 7176 push(len); 7177 cmpl(len, 0); 7178 jccb(Assembler::lessEqual, L_second_loop_exit); 7179 7180 // Multiply an array by one 64 bit long. 7181 if (UseBMI2Instructions) { 7182 op2 = rdxReg; 7183 movq(op2, Address(x, len, Address::times_4, 0)); 7184 rorxq(op2, op2, 32); 7185 } 7186 else { 7187 movq(op2, Address(x, len, Address::times_4, 0)); 7188 rorq(op2, 32); 7189 } 7190 7191 bind(L_third_loop); 7192 decrementl(len); 7193 jccb(Assembler::negative, L_third_loop_exit); 7194 decrementl(len); 7195 jccb(Assembler::negative, L_last_x); 7196 7197 movq(op1, Address(x, len, Address::times_4, 0)); 7198 rorq(op1, 32); 7199 7200 bind(L_multiply); 7201 subl(zlen, 2); 7202 movq(sum, Address(z, zlen, Address::times_4, 0)); 7203 7204 // Multiply 64 bit by 64 bit and add 64 bits lower half and upper 64 bits as carry. 7205 if (UseBMI2Instructions) { 7206 multiply_add_64_bmi2(sum, op1, op2, carry, tmp2); 7207 } 7208 else { 7209 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg); 7210 } 7211 7212 movq(Address(z, zlen, Address::times_4, 0), sum); 7213 7214 jmp(L_third_loop); 7215 bind(L_third_loop_exit); 7216 7217 // Fourth loop 7218 // Add 64 bit long carry into z with carry propagation. 7219 // Uses offsetted zlen. 7220 add_one_64(z, zlen, carry, tmp1); 7221 7222 pop(len); 7223 pop(zlen); 7224 jmp(L_second_loop); 7225 7226 // Next infrequent code is moved outside loops. 7227 bind(L_last_x); 7228 movl(op1, Address(x, 0)); 7229 jmp(L_multiply); 7230 7231 bind(L_second_loop_exit); 7232 pop(len); 7233 pop(zlen); 7234 pop(len); 7235 pop(zlen); 7236 7237 // Fifth loop 7238 // Shift z left 1 bit. 7239 lshift_by_1(x, len, z, zlen, tmp1, tmp2, tmp3, tmp4); 7240 7241 // z[zlen-1] |= x[len-1] & 1; 7242 movl(tmp3, Address(x, len, Address::times_4, -4)); 7243 andl(tmp3, 1); 7244 orl(Address(z, zlen, Address::times_4, -4), tmp3); 7245 7246 pop(tmp5); 7247 pop(tmp4); 7248 pop(tmp3); 7249 pop(tmp2); 7250 pop(tmp1); 7251 } 7252 7253 /** 7254 * Helper function for mul_add() 7255 * Multiply the in[] by int k and add to out[] starting at offset offs using 7256 * 128 bit by 32 bit multiply and return the carry in tmp5. 7257 * Only quad int aligned length of in[] is operated on in this function. 7258 * k is in rdxReg for BMI2Instructions, for others it is in tmp2. 7259 * This function preserves out, in and k registers. 7260 * len and offset point to the appropriate index in "in" & "out" correspondingly 7261 * tmp5 has the carry. 7262 * other registers are temporary and are modified. 7263 * 7264 */ 7265 void MacroAssembler::mul_add_128_x_32_loop(Register out, Register in, 7266 Register offset, Register len, Register tmp1, Register tmp2, Register tmp3, 7267 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) { 7268 7269 Label L_first_loop, L_first_loop_exit; 7270 7271 movl(tmp1, len); 7272 shrl(tmp1, 2); 7273 7274 bind(L_first_loop); 7275 subl(tmp1, 1); 7276 jccb(Assembler::negative, L_first_loop_exit); 7277 7278 subl(len, 4); 7279 subl(offset, 4); 7280 7281 Register op2 = tmp2; 7282 const Register sum = tmp3; 7283 const Register op1 = tmp4; 7284 const Register carry = tmp5; 7285 7286 if (UseBMI2Instructions) { 7287 op2 = rdxReg; 7288 } 7289 7290 movq(op1, Address(in, len, Address::times_4, 8)); 7291 rorq(op1, 32); 7292 movq(sum, Address(out, offset, Address::times_4, 8)); 7293 rorq(sum, 32); 7294 if (UseBMI2Instructions) { 7295 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg); 7296 } 7297 else { 7298 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg); 7299 } 7300 // Store back in big endian from little endian 7301 rorq(sum, 0x20); 7302 movq(Address(out, offset, Address::times_4, 8), sum); 7303 7304 movq(op1, Address(in, len, Address::times_4, 0)); 7305 rorq(op1, 32); 7306 movq(sum, Address(out, offset, Address::times_4, 0)); 7307 rorq(sum, 32); 7308 if (UseBMI2Instructions) { 7309 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg); 7310 } 7311 else { 7312 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg); 7313 } 7314 // Store back in big endian from little endian 7315 rorq(sum, 0x20); 7316 movq(Address(out, offset, Address::times_4, 0), sum); 7317 7318 jmp(L_first_loop); 7319 bind(L_first_loop_exit); 7320 } 7321 7322 /** 7323 * Code for BigInteger::mulAdd() intrinsic 7324 * 7325 * rdi: out 7326 * rsi: in 7327 * r11: offs (out.length - offset) 7328 * rcx: len 7329 * r8: k 7330 * r12: tmp1 7331 * r13: tmp2 7332 * r14: tmp3 7333 * r15: tmp4 7334 * rbx: tmp5 7335 * Multiply the in[] by word k and add to out[], return the carry in rax 7336 */ 7337 void MacroAssembler::mul_add(Register out, Register in, Register offs, 7338 Register len, Register k, Register tmp1, Register tmp2, Register tmp3, 7339 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) { 7340 7341 Label L_carry, L_last_in, L_done; 7342 7343 // carry = 0; 7344 // for (int j=len-1; j >= 0; j--) { 7345 // long product = (in[j] & LONG_MASK) * kLong + 7346 // (out[offs] & LONG_MASK) + carry; 7347 // out[offs--] = (int)product; 7348 // carry = product >>> 32; 7349 // } 7350 // 7351 push(tmp1); 7352 push(tmp2); 7353 push(tmp3); 7354 push(tmp4); 7355 push(tmp5); 7356 7357 Register op2 = tmp2; 7358 const Register sum = tmp3; 7359 const Register op1 = tmp4; 7360 const Register carry = tmp5; 7361 7362 if (UseBMI2Instructions) { 7363 op2 = rdxReg; 7364 movl(op2, k); 7365 } 7366 else { 7367 movl(op2, k); 7368 } 7369 7370 xorq(carry, carry); 7371 7372 //First loop 7373 7374 //Multiply in[] by k in a 4 way unrolled loop using 128 bit by 32 bit multiply 7375 //The carry is in tmp5 7376 mul_add_128_x_32_loop(out, in, offs, len, tmp1, tmp2, tmp3, tmp4, tmp5, rdxReg, raxReg); 7377 7378 //Multiply the trailing in[] entry using 64 bit by 32 bit, if any 7379 decrementl(len); 7380 jccb(Assembler::negative, L_carry); 7381 decrementl(len); 7382 jccb(Assembler::negative, L_last_in); 7383 7384 movq(op1, Address(in, len, Address::times_4, 0)); 7385 rorq(op1, 32); 7386 7387 subl(offs, 2); 7388 movq(sum, Address(out, offs, Address::times_4, 0)); 7389 rorq(sum, 32); 7390 7391 if (UseBMI2Instructions) { 7392 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg); 7393 } 7394 else { 7395 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg); 7396 } 7397 7398 // Store back in big endian from little endian 7399 rorq(sum, 0x20); 7400 movq(Address(out, offs, Address::times_4, 0), sum); 7401 7402 testl(len, len); 7403 jccb(Assembler::zero, L_carry); 7404 7405 //Multiply the last in[] entry, if any 7406 bind(L_last_in); 7407 movl(op1, Address(in, 0)); 7408 movl(sum, Address(out, offs, Address::times_4, -4)); 7409 7410 movl(raxReg, k); 7411 mull(op1); //tmp4 * eax -> edx:eax 7412 addl(sum, carry); 7413 adcl(rdxReg, 0); 7414 addl(sum, raxReg); 7415 adcl(rdxReg, 0); 7416 movl(carry, rdxReg); 7417 7418 movl(Address(out, offs, Address::times_4, -4), sum); 7419 7420 bind(L_carry); 7421 //return tmp5/carry as carry in rax 7422 movl(rax, carry); 7423 7424 bind(L_done); 7425 pop(tmp5); 7426 pop(tmp4); 7427 pop(tmp3); 7428 pop(tmp2); 7429 pop(tmp1); 7430 } 7431 #endif 7432 7433 /** 7434 * Emits code to update CRC-32 with a byte value according to constants in table 7435 * 7436 * @param [in,out]crc Register containing the crc. 7437 * @param [in]val Register containing the byte to fold into the CRC. 7438 * @param [in]table Register containing the table of crc constants. 7439 * 7440 * uint32_t crc; 7441 * val = crc_table[(val ^ crc) & 0xFF]; 7442 * crc = val ^ (crc >> 8); 7443 * 7444 */ 7445 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) { 7446 xorl(val, crc); 7447 andl(val, 0xFF); 7448 shrl(crc, 8); // unsigned shift 7449 xorl(crc, Address(table, val, Address::times_4, 0)); 7450 } 7451 7452 /** 7453 * Fold 128-bit data chunk 7454 */ 7455 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset) { 7456 if (UseAVX > 0) { 7457 vpclmulhdq(xtmp, xK, xcrc); // [123:64] 7458 vpclmulldq(xcrc, xK, xcrc); // [63:0] 7459 vpxor(xcrc, xcrc, Address(buf, offset), 0 /* vector_len */); 7460 pxor(xcrc, xtmp); 7461 } else { 7462 movdqa(xtmp, xcrc); 7463 pclmulhdq(xtmp, xK); // [123:64] 7464 pclmulldq(xcrc, xK); // [63:0] 7465 pxor(xcrc, xtmp); 7466 movdqu(xtmp, Address(buf, offset)); 7467 pxor(xcrc, xtmp); 7468 } 7469 } 7470 7471 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf) { 7472 if (UseAVX > 0) { 7473 vpclmulhdq(xtmp, xK, xcrc); 7474 vpclmulldq(xcrc, xK, xcrc); 7475 pxor(xcrc, xbuf); 7476 pxor(xcrc, xtmp); 7477 } else { 7478 movdqa(xtmp, xcrc); 7479 pclmulhdq(xtmp, xK); 7480 pclmulldq(xcrc, xK); 7481 pxor(xcrc, xbuf); 7482 pxor(xcrc, xtmp); 7483 } 7484 } 7485 7486 /** 7487 * 8-bit folds to compute 32-bit CRC 7488 * 7489 * uint64_t xcrc; 7490 * timesXtoThe32[xcrc & 0xFF] ^ (xcrc >> 8); 7491 */ 7492 void MacroAssembler::fold_8bit_crc32(XMMRegister xcrc, Register table, XMMRegister xtmp, Register tmp) { 7493 movdl(tmp, xcrc); 7494 andl(tmp, 0xFF); 7495 movdl(xtmp, Address(table, tmp, Address::times_4, 0)); 7496 psrldq(xcrc, 1); // unsigned shift one byte 7497 pxor(xcrc, xtmp); 7498 } 7499 7500 /** 7501 * uint32_t crc; 7502 * timesXtoThe32[crc & 0xFF] ^ (crc >> 8); 7503 */ 7504 void MacroAssembler::fold_8bit_crc32(Register crc, Register table, Register tmp) { 7505 movl(tmp, crc); 7506 andl(tmp, 0xFF); 7507 shrl(crc, 8); 7508 xorl(crc, Address(table, tmp, Address::times_4, 0)); 7509 } 7510 7511 /** 7512 * @param crc register containing existing CRC (32-bit) 7513 * @param buf register pointing to input byte buffer (byte*) 7514 * @param len register containing number of bytes 7515 * @param table register that will contain address of CRC table 7516 * @param tmp scratch register 7517 */ 7518 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp) { 7519 assert_different_registers(crc, buf, len, table, tmp, rax); 7520 7521 Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned; 7522 Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop; 7523 7524 // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge 7525 // context for the registers used, where all instructions below are using 128-bit mode 7526 // On EVEX without VL and BW, these instructions will all be AVX. 7527 lea(table, ExternalAddress(StubRoutines::crc_table_addr())); 7528 notl(crc); // ~crc 7529 cmpl(len, 16); 7530 jcc(Assembler::less, L_tail); 7531 7532 // Align buffer to 16 bytes 7533 movl(tmp, buf); 7534 andl(tmp, 0xF); 7535 jccb(Assembler::zero, L_aligned); 7536 subl(tmp, 16); 7537 addl(len, tmp); 7538 7539 align(4); 7540 BIND(L_align_loop); 7541 movsbl(rax, Address(buf, 0)); // load byte with sign extension 7542 update_byte_crc32(crc, rax, table); 7543 increment(buf); 7544 incrementl(tmp); 7545 jccb(Assembler::less, L_align_loop); 7546 7547 BIND(L_aligned); 7548 movl(tmp, len); // save 7549 shrl(len, 4); 7550 jcc(Assembler::zero, L_tail_restore); 7551 7552 // Fold crc into first bytes of vector 7553 movdqa(xmm1, Address(buf, 0)); 7554 movdl(rax, xmm1); 7555 xorl(crc, rax); 7556 if (VM_Version::supports_sse4_1()) { 7557 pinsrd(xmm1, crc, 0); 7558 } else { 7559 pinsrw(xmm1, crc, 0); 7560 shrl(crc, 16); 7561 pinsrw(xmm1, crc, 1); 7562 } 7563 addptr(buf, 16); 7564 subl(len, 4); // len > 0 7565 jcc(Assembler::less, L_fold_tail); 7566 7567 movdqa(xmm2, Address(buf, 0)); 7568 movdqa(xmm3, Address(buf, 16)); 7569 movdqa(xmm4, Address(buf, 32)); 7570 addptr(buf, 48); 7571 subl(len, 3); 7572 jcc(Assembler::lessEqual, L_fold_512b); 7573 7574 // Fold total 512 bits of polynomial on each iteration, 7575 // 128 bits per each of 4 parallel streams. 7576 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 32), rscratch1); 7577 7578 align32(); 7579 BIND(L_fold_512b_loop); 7580 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0); 7581 fold_128bit_crc32(xmm2, xmm0, xmm5, buf, 16); 7582 fold_128bit_crc32(xmm3, xmm0, xmm5, buf, 32); 7583 fold_128bit_crc32(xmm4, xmm0, xmm5, buf, 48); 7584 addptr(buf, 64); 7585 subl(len, 4); 7586 jcc(Assembler::greater, L_fold_512b_loop); 7587 7588 // Fold 512 bits to 128 bits. 7589 BIND(L_fold_512b); 7590 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16), rscratch1); 7591 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm2); 7592 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm3); 7593 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm4); 7594 7595 // Fold the rest of 128 bits data chunks 7596 BIND(L_fold_tail); 7597 addl(len, 3); 7598 jccb(Assembler::lessEqual, L_fold_128b); 7599 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16), rscratch1); 7600 7601 BIND(L_fold_tail_loop); 7602 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0); 7603 addptr(buf, 16); 7604 decrementl(len); 7605 jccb(Assembler::greater, L_fold_tail_loop); 7606 7607 // Fold 128 bits in xmm1 down into 32 bits in crc register. 7608 BIND(L_fold_128b); 7609 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr()), rscratch1); 7610 if (UseAVX > 0) { 7611 vpclmulqdq(xmm2, xmm0, xmm1, 0x1); 7612 vpand(xmm3, xmm0, xmm2, 0 /* vector_len */); 7613 vpclmulqdq(xmm0, xmm0, xmm3, 0x1); 7614 } else { 7615 movdqa(xmm2, xmm0); 7616 pclmulqdq(xmm2, xmm1, 0x1); 7617 movdqa(xmm3, xmm0); 7618 pand(xmm3, xmm2); 7619 pclmulqdq(xmm0, xmm3, 0x1); 7620 } 7621 psrldq(xmm1, 8); 7622 psrldq(xmm2, 4); 7623 pxor(xmm0, xmm1); 7624 pxor(xmm0, xmm2); 7625 7626 // 8 8-bit folds to compute 32-bit CRC. 7627 for (int j = 0; j < 4; j++) { 7628 fold_8bit_crc32(xmm0, table, xmm1, rax); 7629 } 7630 movdl(crc, xmm0); // mov 32 bits to general register 7631 for (int j = 0; j < 4; j++) { 7632 fold_8bit_crc32(crc, table, rax); 7633 } 7634 7635 BIND(L_tail_restore); 7636 movl(len, tmp); // restore 7637 BIND(L_tail); 7638 andl(len, 0xf); 7639 jccb(Assembler::zero, L_exit); 7640 7641 // Fold the rest of bytes 7642 align(4); 7643 BIND(L_tail_loop); 7644 movsbl(rax, Address(buf, 0)); // load byte with sign extension 7645 update_byte_crc32(crc, rax, table); 7646 increment(buf); 7647 decrementl(len); 7648 jccb(Assembler::greater, L_tail_loop); 7649 7650 BIND(L_exit); 7651 notl(crc); // ~c 7652 } 7653 7654 #ifdef _LP64 7655 // Helper function for AVX 512 CRC32 7656 // Fold 512-bit data chunks 7657 void MacroAssembler::fold512bit_crc32_avx512(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, 7658 Register pos, int offset) { 7659 evmovdquq(xmm3, Address(buf, pos, Address::times_1, offset), Assembler::AVX_512bit); 7660 evpclmulqdq(xtmp, xcrc, xK, 0x10, Assembler::AVX_512bit); // [123:64] 7661 evpclmulqdq(xmm2, xcrc, xK, 0x01, Assembler::AVX_512bit); // [63:0] 7662 evpxorq(xcrc, xtmp, xmm2, Assembler::AVX_512bit /* vector_len */); 7663 evpxorq(xcrc, xcrc, xmm3, Assembler::AVX_512bit /* vector_len */); 7664 } 7665 7666 // Helper function for AVX 512 CRC32 7667 // Compute CRC32 for < 256B buffers 7668 void MacroAssembler::kernel_crc32_avx512_256B(Register crc, Register buf, Register len, Register table, Register pos, 7669 Register tmp1, Register tmp2, Label& L_barrett, Label& L_16B_reduction_loop, 7670 Label& L_get_last_two_xmms, Label& L_128_done, Label& L_cleanup) { 7671 7672 Label L_less_than_32, L_exact_16_left, L_less_than_16_left; 7673 Label L_less_than_8_left, L_less_than_4_left, L_less_than_2_left, L_zero_left; 7674 Label L_only_less_than_4, L_only_less_than_3, L_only_less_than_2; 7675 7676 // check if there is enough buffer to be able to fold 16B at a time 7677 cmpl(len, 32); 7678 jcc(Assembler::less, L_less_than_32); 7679 7680 // if there is, load the constants 7681 movdqu(xmm10, Address(table, 1 * 16)); //rk1 and rk2 in xmm10 7682 movdl(xmm0, crc); // get the initial crc value 7683 movdqu(xmm7, Address(buf, pos, Address::times_1, 0 * 16)); //load the plaintext 7684 pxor(xmm7, xmm0); 7685 7686 // update the buffer pointer 7687 addl(pos, 16); 7688 //update the counter.subtract 32 instead of 16 to save one instruction from the loop 7689 subl(len, 32); 7690 jmp(L_16B_reduction_loop); 7691 7692 bind(L_less_than_32); 7693 //mov initial crc to the return value. this is necessary for zero - length buffers. 7694 movl(rax, crc); 7695 testl(len, len); 7696 jcc(Assembler::equal, L_cleanup); 7697 7698 movdl(xmm0, crc); //get the initial crc value 7699 7700 cmpl(len, 16); 7701 jcc(Assembler::equal, L_exact_16_left); 7702 jcc(Assembler::less, L_less_than_16_left); 7703 7704 movdqu(xmm7, Address(buf, pos, Address::times_1, 0 * 16)); //load the plaintext 7705 pxor(xmm7, xmm0); //xor the initial crc value 7706 addl(pos, 16); 7707 subl(len, 16); 7708 movdqu(xmm10, Address(table, 1 * 16)); // rk1 and rk2 in xmm10 7709 jmp(L_get_last_two_xmms); 7710 7711 bind(L_less_than_16_left); 7712 //use stack space to load data less than 16 bytes, zero - out the 16B in memory first. 7713 pxor(xmm1, xmm1); 7714 movptr(tmp1, rsp); 7715 movdqu(Address(tmp1, 0 * 16), xmm1); 7716 7717 cmpl(len, 4); 7718 jcc(Assembler::less, L_only_less_than_4); 7719 7720 //backup the counter value 7721 movl(tmp2, len); 7722 cmpl(len, 8); 7723 jcc(Assembler::less, L_less_than_8_left); 7724 7725 //load 8 Bytes 7726 movq(rax, Address(buf, pos, Address::times_1, 0 * 16)); 7727 movq(Address(tmp1, 0 * 16), rax); 7728 addptr(tmp1, 8); 7729 subl(len, 8); 7730 addl(pos, 8); 7731 7732 bind(L_less_than_8_left); 7733 cmpl(len, 4); 7734 jcc(Assembler::less, L_less_than_4_left); 7735 7736 //load 4 Bytes 7737 movl(rax, Address(buf, pos, Address::times_1, 0)); 7738 movl(Address(tmp1, 0 * 16), rax); 7739 addptr(tmp1, 4); 7740 subl(len, 4); 7741 addl(pos, 4); 7742 7743 bind(L_less_than_4_left); 7744 cmpl(len, 2); 7745 jcc(Assembler::less, L_less_than_2_left); 7746 7747 // load 2 Bytes 7748 movw(rax, Address(buf, pos, Address::times_1, 0)); 7749 movl(Address(tmp1, 0 * 16), rax); 7750 addptr(tmp1, 2); 7751 subl(len, 2); 7752 addl(pos, 2); 7753 7754 bind(L_less_than_2_left); 7755 cmpl(len, 1); 7756 jcc(Assembler::less, L_zero_left); 7757 7758 // load 1 Byte 7759 movb(rax, Address(buf, pos, Address::times_1, 0)); 7760 movb(Address(tmp1, 0 * 16), rax); 7761 7762 bind(L_zero_left); 7763 movdqu(xmm7, Address(rsp, 0)); 7764 pxor(xmm7, xmm0); //xor the initial crc value 7765 7766 lea(rax, ExternalAddress(StubRoutines::x86::shuf_table_crc32_avx512_addr())); 7767 movdqu(xmm0, Address(rax, tmp2)); 7768 pshufb(xmm7, xmm0); 7769 jmp(L_128_done); 7770 7771 bind(L_exact_16_left); 7772 movdqu(xmm7, Address(buf, pos, Address::times_1, 0)); 7773 pxor(xmm7, xmm0); //xor the initial crc value 7774 jmp(L_128_done); 7775 7776 bind(L_only_less_than_4); 7777 cmpl(len, 3); 7778 jcc(Assembler::less, L_only_less_than_3); 7779 7780 // load 3 Bytes 7781 movb(rax, Address(buf, pos, Address::times_1, 0)); 7782 movb(Address(tmp1, 0), rax); 7783 7784 movb(rax, Address(buf, pos, Address::times_1, 1)); 7785 movb(Address(tmp1, 1), rax); 7786 7787 movb(rax, Address(buf, pos, Address::times_1, 2)); 7788 movb(Address(tmp1, 2), rax); 7789 7790 movdqu(xmm7, Address(rsp, 0)); 7791 pxor(xmm7, xmm0); //xor the initial crc value 7792 7793 pslldq(xmm7, 0x5); 7794 jmp(L_barrett); 7795 bind(L_only_less_than_3); 7796 cmpl(len, 2); 7797 jcc(Assembler::less, L_only_less_than_2); 7798 7799 // load 2 Bytes 7800 movb(rax, Address(buf, pos, Address::times_1, 0)); 7801 movb(Address(tmp1, 0), rax); 7802 7803 movb(rax, Address(buf, pos, Address::times_1, 1)); 7804 movb(Address(tmp1, 1), rax); 7805 7806 movdqu(xmm7, Address(rsp, 0)); 7807 pxor(xmm7, xmm0); //xor the initial crc value 7808 7809 pslldq(xmm7, 0x6); 7810 jmp(L_barrett); 7811 7812 bind(L_only_less_than_2); 7813 //load 1 Byte 7814 movb(rax, Address(buf, pos, Address::times_1, 0)); 7815 movb(Address(tmp1, 0), rax); 7816 7817 movdqu(xmm7, Address(rsp, 0)); 7818 pxor(xmm7, xmm0); //xor the initial crc value 7819 7820 pslldq(xmm7, 0x7); 7821 } 7822 7823 /** 7824 * Compute CRC32 using AVX512 instructions 7825 * param crc register containing existing CRC (32-bit) 7826 * param buf register pointing to input byte buffer (byte*) 7827 * param len register containing number of bytes 7828 * param table address of crc or crc32c table 7829 * param tmp1 scratch register 7830 * param tmp2 scratch register 7831 * return rax result register 7832 * 7833 * This routine is identical for crc32c with the exception of the precomputed constant 7834 * table which will be passed as the table argument. The calculation steps are 7835 * the same for both variants. 7836 */ 7837 void MacroAssembler::kernel_crc32_avx512(Register crc, Register buf, Register len, Register table, Register tmp1, Register tmp2) { 7838 assert_different_registers(crc, buf, len, table, tmp1, tmp2, rax, r12); 7839 7840 Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned; 7841 Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop; 7842 Label L_less_than_256, L_fold_128_B_loop, L_fold_256_B_loop; 7843 Label L_fold_128_B_register, L_final_reduction_for_128, L_16B_reduction_loop; 7844 Label L_128_done, L_get_last_two_xmms, L_barrett, L_cleanup; 7845 7846 const Register pos = r12; 7847 push(r12); 7848 subptr(rsp, 16 * 2 + 8); 7849 7850 // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge 7851 // context for the registers used, where all instructions below are using 128-bit mode 7852 // On EVEX without VL and BW, these instructions will all be AVX. 7853 movl(pos, 0); 7854 7855 // check if smaller than 256B 7856 cmpl(len, 256); 7857 jcc(Assembler::less, L_less_than_256); 7858 7859 // load the initial crc value 7860 movdl(xmm10, crc); 7861 7862 // receive the initial 64B data, xor the initial crc value 7863 evmovdquq(xmm0, Address(buf, pos, Address::times_1, 0 * 64), Assembler::AVX_512bit); 7864 evmovdquq(xmm4, Address(buf, pos, Address::times_1, 1 * 64), Assembler::AVX_512bit); 7865 evpxorq(xmm0, xmm0, xmm10, Assembler::AVX_512bit); 7866 evbroadcasti32x4(xmm10, Address(table, 2 * 16), Assembler::AVX_512bit); //zmm10 has rk3 and rk4 7867 7868 subl(len, 256); 7869 cmpl(len, 256); 7870 jcc(Assembler::less, L_fold_128_B_loop); 7871 7872 evmovdquq(xmm7, Address(buf, pos, Address::times_1, 2 * 64), Assembler::AVX_512bit); 7873 evmovdquq(xmm8, Address(buf, pos, Address::times_1, 3 * 64), Assembler::AVX_512bit); 7874 evbroadcasti32x4(xmm16, Address(table, 0 * 16), Assembler::AVX_512bit); //zmm16 has rk-1 and rk-2 7875 subl(len, 256); 7876 7877 bind(L_fold_256_B_loop); 7878 addl(pos, 256); 7879 fold512bit_crc32_avx512(xmm0, xmm16, xmm1, buf, pos, 0 * 64); 7880 fold512bit_crc32_avx512(xmm4, xmm16, xmm1, buf, pos, 1 * 64); 7881 fold512bit_crc32_avx512(xmm7, xmm16, xmm1, buf, pos, 2 * 64); 7882 fold512bit_crc32_avx512(xmm8, xmm16, xmm1, buf, pos, 3 * 64); 7883 7884 subl(len, 256); 7885 jcc(Assembler::greaterEqual, L_fold_256_B_loop); 7886 7887 // Fold 256 into 128 7888 addl(pos, 256); 7889 evpclmulqdq(xmm1, xmm0, xmm10, 0x01, Assembler::AVX_512bit); 7890 evpclmulqdq(xmm2, xmm0, xmm10, 0x10, Assembler::AVX_512bit); 7891 vpternlogq(xmm7, 0x96, xmm1, xmm2, Assembler::AVX_512bit); // xor ABC 7892 7893 evpclmulqdq(xmm5, xmm4, xmm10, 0x01, Assembler::AVX_512bit); 7894 evpclmulqdq(xmm6, xmm4, xmm10, 0x10, Assembler::AVX_512bit); 7895 vpternlogq(xmm8, 0x96, xmm5, xmm6, Assembler::AVX_512bit); // xor ABC 7896 7897 evmovdquq(xmm0, xmm7, Assembler::AVX_512bit); 7898 evmovdquq(xmm4, xmm8, Assembler::AVX_512bit); 7899 7900 addl(len, 128); 7901 jmp(L_fold_128_B_register); 7902 7903 // at this section of the code, there is 128 * x + y(0 <= y<128) bytes of buffer.The fold_128_B_loop 7904 // loop will fold 128B at a time until we have 128 + y Bytes of buffer 7905 7906 // fold 128B at a time.This section of the code folds 8 xmm registers in parallel 7907 bind(L_fold_128_B_loop); 7908 addl(pos, 128); 7909 fold512bit_crc32_avx512(xmm0, xmm10, xmm1, buf, pos, 0 * 64); 7910 fold512bit_crc32_avx512(xmm4, xmm10, xmm1, buf, pos, 1 * 64); 7911 7912 subl(len, 128); 7913 jcc(Assembler::greaterEqual, L_fold_128_B_loop); 7914 7915 addl(pos, 128); 7916 7917 // at this point, the buffer pointer is pointing at the last y Bytes of the buffer, where 0 <= y < 128 7918 // the 128B of folded data is in 8 of the xmm registers : xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7 7919 bind(L_fold_128_B_register); 7920 evmovdquq(xmm16, Address(table, 5 * 16), Assembler::AVX_512bit); // multiply by rk9-rk16 7921 evmovdquq(xmm11, Address(table, 9 * 16), Assembler::AVX_512bit); // multiply by rk17-rk20, rk1,rk2, 0,0 7922 evpclmulqdq(xmm1, xmm0, xmm16, 0x01, Assembler::AVX_512bit); 7923 evpclmulqdq(xmm2, xmm0, xmm16, 0x10, Assembler::AVX_512bit); 7924 // save last that has no multiplicand 7925 vextracti64x2(xmm7, xmm4, 3); 7926 7927 evpclmulqdq(xmm5, xmm4, xmm11, 0x01, Assembler::AVX_512bit); 7928 evpclmulqdq(xmm6, xmm4, xmm11, 0x10, Assembler::AVX_512bit); 7929 // Needed later in reduction loop 7930 movdqu(xmm10, Address(table, 1 * 16)); 7931 vpternlogq(xmm1, 0x96, xmm2, xmm5, Assembler::AVX_512bit); // xor ABC 7932 vpternlogq(xmm1, 0x96, xmm6, xmm7, Assembler::AVX_512bit); // xor ABC 7933 7934 // Swap 1,0,3,2 - 01 00 11 10 7935 evshufi64x2(xmm8, xmm1, xmm1, 0x4e, Assembler::AVX_512bit); 7936 evpxorq(xmm8, xmm8, xmm1, Assembler::AVX_256bit); 7937 vextracti128(xmm5, xmm8, 1); 7938 evpxorq(xmm7, xmm5, xmm8, Assembler::AVX_128bit); 7939 7940 // instead of 128, we add 128 - 16 to the loop counter to save 1 instruction from the loop 7941 // instead of a cmp instruction, we use the negative flag with the jl instruction 7942 addl(len, 128 - 16); 7943 jcc(Assembler::less, L_final_reduction_for_128); 7944 7945 bind(L_16B_reduction_loop); 7946 vpclmulqdq(xmm8, xmm7, xmm10, 0x01); 7947 vpclmulqdq(xmm7, xmm7, xmm10, 0x10); 7948 vpxor(xmm7, xmm7, xmm8, Assembler::AVX_128bit); 7949 movdqu(xmm0, Address(buf, pos, Address::times_1, 0 * 16)); 7950 vpxor(xmm7, xmm7, xmm0, Assembler::AVX_128bit); 7951 addl(pos, 16); 7952 subl(len, 16); 7953 jcc(Assembler::greaterEqual, L_16B_reduction_loop); 7954 7955 bind(L_final_reduction_for_128); 7956 addl(len, 16); 7957 jcc(Assembler::equal, L_128_done); 7958 7959 bind(L_get_last_two_xmms); 7960 movdqu(xmm2, xmm7); 7961 addl(pos, len); 7962 movdqu(xmm1, Address(buf, pos, Address::times_1, -16)); 7963 subl(pos, len); 7964 7965 // get rid of the extra data that was loaded before 7966 // load the shift constant 7967 lea(rax, ExternalAddress(StubRoutines::x86::shuf_table_crc32_avx512_addr())); 7968 movdqu(xmm0, Address(rax, len)); 7969 addl(rax, len); 7970 7971 vpshufb(xmm7, xmm7, xmm0, Assembler::AVX_128bit); 7972 //Change mask to 512 7973 vpxor(xmm0, xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_avx512_addr() + 2 * 16), Assembler::AVX_128bit, tmp2); 7974 vpshufb(xmm2, xmm2, xmm0, Assembler::AVX_128bit); 7975 7976 blendvpb(xmm2, xmm2, xmm1, xmm0, Assembler::AVX_128bit); 7977 vpclmulqdq(xmm8, xmm7, xmm10, 0x01); 7978 vpclmulqdq(xmm7, xmm7, xmm10, 0x10); 7979 vpxor(xmm7, xmm7, xmm8, Assembler::AVX_128bit); 7980 vpxor(xmm7, xmm7, xmm2, Assembler::AVX_128bit); 7981 7982 bind(L_128_done); 7983 // compute crc of a 128-bit value 7984 movdqu(xmm10, Address(table, 3 * 16)); 7985 movdqu(xmm0, xmm7); 7986 7987 // 64b fold 7988 vpclmulqdq(xmm7, xmm7, xmm10, 0x0); 7989 vpsrldq(xmm0, xmm0, 0x8, Assembler::AVX_128bit); 7990 vpxor(xmm7, xmm7, xmm0, Assembler::AVX_128bit); 7991 7992 // 32b fold 7993 movdqu(xmm0, xmm7); 7994 vpslldq(xmm7, xmm7, 0x4, Assembler::AVX_128bit); 7995 vpclmulqdq(xmm7, xmm7, xmm10, 0x10); 7996 vpxor(xmm7, xmm7, xmm0, Assembler::AVX_128bit); 7997 jmp(L_barrett); 7998 7999 bind(L_less_than_256); 8000 kernel_crc32_avx512_256B(crc, buf, len, table, pos, tmp1, tmp2, L_barrett, L_16B_reduction_loop, L_get_last_two_xmms, L_128_done, L_cleanup); 8001 8002 //barrett reduction 8003 bind(L_barrett); 8004 vpand(xmm7, xmm7, ExternalAddress(StubRoutines::x86::crc_by128_masks_avx512_addr() + 1 * 16), Assembler::AVX_128bit, tmp2); 8005 movdqu(xmm1, xmm7); 8006 movdqu(xmm2, xmm7); 8007 movdqu(xmm10, Address(table, 4 * 16)); 8008 8009 pclmulqdq(xmm7, xmm10, 0x0); 8010 pxor(xmm7, xmm2); 8011 vpand(xmm7, xmm7, ExternalAddress(StubRoutines::x86::crc_by128_masks_avx512_addr()), Assembler::AVX_128bit, tmp2); 8012 movdqu(xmm2, xmm7); 8013 pclmulqdq(xmm7, xmm10, 0x10); 8014 pxor(xmm7, xmm2); 8015 pxor(xmm7, xmm1); 8016 pextrd(crc, xmm7, 2); 8017 8018 bind(L_cleanup); 8019 addptr(rsp, 16 * 2 + 8); 8020 pop(r12); 8021 } 8022 8023 // S. Gueron / Information Processing Letters 112 (2012) 184 8024 // Algorithm 4: Computing carry-less multiplication using a precomputed lookup table. 8025 // Input: A 32 bit value B = [byte3, byte2, byte1, byte0]. 8026 // Output: the 64-bit carry-less product of B * CONST 8027 void MacroAssembler::crc32c_ipl_alg4(Register in, uint32_t n, 8028 Register tmp1, Register tmp2, Register tmp3) { 8029 lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr())); 8030 if (n > 0) { 8031 addq(tmp3, n * 256 * 8); 8032 } 8033 // Q1 = TABLEExt[n][B & 0xFF]; 8034 movl(tmp1, in); 8035 andl(tmp1, 0x000000FF); 8036 shll(tmp1, 3); 8037 addq(tmp1, tmp3); 8038 movq(tmp1, Address(tmp1, 0)); 8039 8040 // Q2 = TABLEExt[n][B >> 8 & 0xFF]; 8041 movl(tmp2, in); 8042 shrl(tmp2, 8); 8043 andl(tmp2, 0x000000FF); 8044 shll(tmp2, 3); 8045 addq(tmp2, tmp3); 8046 movq(tmp2, Address(tmp2, 0)); 8047 8048 shlq(tmp2, 8); 8049 xorq(tmp1, tmp2); 8050 8051 // Q3 = TABLEExt[n][B >> 16 & 0xFF]; 8052 movl(tmp2, in); 8053 shrl(tmp2, 16); 8054 andl(tmp2, 0x000000FF); 8055 shll(tmp2, 3); 8056 addq(tmp2, tmp3); 8057 movq(tmp2, Address(tmp2, 0)); 8058 8059 shlq(tmp2, 16); 8060 xorq(tmp1, tmp2); 8061 8062 // Q4 = TABLEExt[n][B >> 24 & 0xFF]; 8063 shrl(in, 24); 8064 andl(in, 0x000000FF); 8065 shll(in, 3); 8066 addq(in, tmp3); 8067 movq(in, Address(in, 0)); 8068 8069 shlq(in, 24); 8070 xorq(in, tmp1); 8071 // return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24; 8072 } 8073 8074 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1, 8075 Register in_out, 8076 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported, 8077 XMMRegister w_xtmp2, 8078 Register tmp1, 8079 Register n_tmp2, Register n_tmp3) { 8080 if (is_pclmulqdq_supported) { 8081 movdl(w_xtmp1, in_out); // modified blindly 8082 8083 movl(tmp1, const_or_pre_comp_const_index); 8084 movdl(w_xtmp2, tmp1); 8085 pclmulqdq(w_xtmp1, w_xtmp2, 0); 8086 8087 movdq(in_out, w_xtmp1); 8088 } else { 8089 crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3); 8090 } 8091 } 8092 8093 // Recombination Alternative 2: No bit-reflections 8094 // T1 = (CRC_A * U1) << 1 8095 // T2 = (CRC_B * U2) << 1 8096 // C1 = T1 >> 32 8097 // C2 = T2 >> 32 8098 // T1 = T1 & 0xFFFFFFFF 8099 // T2 = T2 & 0xFFFFFFFF 8100 // T1 = CRC32(0, T1) 8101 // T2 = CRC32(0, T2) 8102 // C1 = C1 ^ T1 8103 // C2 = C2 ^ T2 8104 // CRC = C1 ^ C2 ^ CRC_C 8105 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2, 8106 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3, 8107 Register tmp1, Register tmp2, 8108 Register n_tmp3) { 8109 crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3); 8110 crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3); 8111 shlq(in_out, 1); 8112 movl(tmp1, in_out); 8113 shrq(in_out, 32); 8114 xorl(tmp2, tmp2); 8115 crc32(tmp2, tmp1, 4); 8116 xorl(in_out, tmp2); // we don't care about upper 32 bit contents here 8117 shlq(in1, 1); 8118 movl(tmp1, in1); 8119 shrq(in1, 32); 8120 xorl(tmp2, tmp2); 8121 crc32(tmp2, tmp1, 4); 8122 xorl(in1, tmp2); 8123 xorl(in_out, in1); 8124 xorl(in_out, in2); 8125 } 8126 8127 // Set N to predefined value 8128 // Subtract from a length of a buffer 8129 // execute in a loop: 8130 // CRC_A = 0xFFFFFFFF, CRC_B = 0, CRC_C = 0 8131 // for i = 1 to N do 8132 // CRC_A = CRC32(CRC_A, A[i]) 8133 // CRC_B = CRC32(CRC_B, B[i]) 8134 // CRC_C = CRC32(CRC_C, C[i]) 8135 // end for 8136 // Recombine 8137 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, 8138 Register in_out1, Register in_out2, Register in_out3, 8139 Register tmp1, Register tmp2, Register tmp3, 8140 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3, 8141 Register tmp4, Register tmp5, 8142 Register n_tmp6) { 8143 Label L_processPartitions; 8144 Label L_processPartition; 8145 Label L_exit; 8146 8147 bind(L_processPartitions); 8148 cmpl(in_out1, 3 * size); 8149 jcc(Assembler::less, L_exit); 8150 xorl(tmp1, tmp1); 8151 xorl(tmp2, tmp2); 8152 movq(tmp3, in_out2); 8153 addq(tmp3, size); 8154 8155 bind(L_processPartition); 8156 crc32(in_out3, Address(in_out2, 0), 8); 8157 crc32(tmp1, Address(in_out2, size), 8); 8158 crc32(tmp2, Address(in_out2, size * 2), 8); 8159 addq(in_out2, 8); 8160 cmpq(in_out2, tmp3); 8161 jcc(Assembler::less, L_processPartition); 8162 crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2, 8163 w_xtmp1, w_xtmp2, w_xtmp3, 8164 tmp4, tmp5, 8165 n_tmp6); 8166 addq(in_out2, 2 * size); 8167 subl(in_out1, 3 * size); 8168 jmp(L_processPartitions); 8169 8170 bind(L_exit); 8171 } 8172 #else 8173 void MacroAssembler::crc32c_ipl_alg4(Register in_out, uint32_t n, 8174 Register tmp1, Register tmp2, Register tmp3, 8175 XMMRegister xtmp1, XMMRegister xtmp2) { 8176 lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr())); 8177 if (n > 0) { 8178 addl(tmp3, n * 256 * 8); 8179 } 8180 // Q1 = TABLEExt[n][B & 0xFF]; 8181 movl(tmp1, in_out); 8182 andl(tmp1, 0x000000FF); 8183 shll(tmp1, 3); 8184 addl(tmp1, tmp3); 8185 movq(xtmp1, Address(tmp1, 0)); 8186 8187 // Q2 = TABLEExt[n][B >> 8 & 0xFF]; 8188 movl(tmp2, in_out); 8189 shrl(tmp2, 8); 8190 andl(tmp2, 0x000000FF); 8191 shll(tmp2, 3); 8192 addl(tmp2, tmp3); 8193 movq(xtmp2, Address(tmp2, 0)); 8194 8195 psllq(xtmp2, 8); 8196 pxor(xtmp1, xtmp2); 8197 8198 // Q3 = TABLEExt[n][B >> 16 & 0xFF]; 8199 movl(tmp2, in_out); 8200 shrl(tmp2, 16); 8201 andl(tmp2, 0x000000FF); 8202 shll(tmp2, 3); 8203 addl(tmp2, tmp3); 8204 movq(xtmp2, Address(tmp2, 0)); 8205 8206 psllq(xtmp2, 16); 8207 pxor(xtmp1, xtmp2); 8208 8209 // Q4 = TABLEExt[n][B >> 24 & 0xFF]; 8210 shrl(in_out, 24); 8211 andl(in_out, 0x000000FF); 8212 shll(in_out, 3); 8213 addl(in_out, tmp3); 8214 movq(xtmp2, Address(in_out, 0)); 8215 8216 psllq(xtmp2, 24); 8217 pxor(xtmp1, xtmp2); // Result in CXMM 8218 // return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24; 8219 } 8220 8221 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1, 8222 Register in_out, 8223 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported, 8224 XMMRegister w_xtmp2, 8225 Register tmp1, 8226 Register n_tmp2, Register n_tmp3) { 8227 if (is_pclmulqdq_supported) { 8228 movdl(w_xtmp1, in_out); 8229 8230 movl(tmp1, const_or_pre_comp_const_index); 8231 movdl(w_xtmp2, tmp1); 8232 pclmulqdq(w_xtmp1, w_xtmp2, 0); 8233 // Keep result in XMM since GPR is 32 bit in length 8234 } else { 8235 crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3, w_xtmp1, w_xtmp2); 8236 } 8237 } 8238 8239 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2, 8240 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3, 8241 Register tmp1, Register tmp2, 8242 Register n_tmp3) { 8243 crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3); 8244 crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3); 8245 8246 psllq(w_xtmp1, 1); 8247 movdl(tmp1, w_xtmp1); 8248 psrlq(w_xtmp1, 32); 8249 movdl(in_out, w_xtmp1); 8250 8251 xorl(tmp2, tmp2); 8252 crc32(tmp2, tmp1, 4); 8253 xorl(in_out, tmp2); 8254 8255 psllq(w_xtmp2, 1); 8256 movdl(tmp1, w_xtmp2); 8257 psrlq(w_xtmp2, 32); 8258 movdl(in1, w_xtmp2); 8259 8260 xorl(tmp2, tmp2); 8261 crc32(tmp2, tmp1, 4); 8262 xorl(in1, tmp2); 8263 xorl(in_out, in1); 8264 xorl(in_out, in2); 8265 } 8266 8267 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, 8268 Register in_out1, Register in_out2, Register in_out3, 8269 Register tmp1, Register tmp2, Register tmp3, 8270 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3, 8271 Register tmp4, Register tmp5, 8272 Register n_tmp6) { 8273 Label L_processPartitions; 8274 Label L_processPartition; 8275 Label L_exit; 8276 8277 bind(L_processPartitions); 8278 cmpl(in_out1, 3 * size); 8279 jcc(Assembler::less, L_exit); 8280 xorl(tmp1, tmp1); 8281 xorl(tmp2, tmp2); 8282 movl(tmp3, in_out2); 8283 addl(tmp3, size); 8284 8285 bind(L_processPartition); 8286 crc32(in_out3, Address(in_out2, 0), 4); 8287 crc32(tmp1, Address(in_out2, size), 4); 8288 crc32(tmp2, Address(in_out2, size*2), 4); 8289 crc32(in_out3, Address(in_out2, 0+4), 4); 8290 crc32(tmp1, Address(in_out2, size+4), 4); 8291 crc32(tmp2, Address(in_out2, size*2+4), 4); 8292 addl(in_out2, 8); 8293 cmpl(in_out2, tmp3); 8294 jcc(Assembler::less, L_processPartition); 8295 8296 push(tmp3); 8297 push(in_out1); 8298 push(in_out2); 8299 tmp4 = tmp3; 8300 tmp5 = in_out1; 8301 n_tmp6 = in_out2; 8302 8303 crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2, 8304 w_xtmp1, w_xtmp2, w_xtmp3, 8305 tmp4, tmp5, 8306 n_tmp6); 8307 8308 pop(in_out2); 8309 pop(in_out1); 8310 pop(tmp3); 8311 8312 addl(in_out2, 2 * size); 8313 subl(in_out1, 3 * size); 8314 jmp(L_processPartitions); 8315 8316 bind(L_exit); 8317 } 8318 #endif //LP64 8319 8320 #ifdef _LP64 8321 // Algorithm 2: Pipelined usage of the CRC32 instruction. 8322 // Input: A buffer I of L bytes. 8323 // Output: the CRC32C value of the buffer. 8324 // Notations: 8325 // Write L = 24N + r, with N = floor (L/24). 8326 // r = L mod 24 (0 <= r < 24). 8327 // Consider I as the concatenation of A|B|C|R, where A, B, C, each, 8328 // N quadwords, and R consists of r bytes. 8329 // A[j] = I [8j+7:8j], j= 0, 1, ..., N-1 8330 // B[j] = I [N + 8j+7:N + 8j], j= 0, 1, ..., N-1 8331 // C[j] = I [2N + 8j+7:2N + 8j], j= 0, 1, ..., N-1 8332 // if r > 0 R[j] = I [3N +j], j= 0, 1, ...,r-1 8333 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2, 8334 Register tmp1, Register tmp2, Register tmp3, 8335 Register tmp4, Register tmp5, Register tmp6, 8336 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3, 8337 bool is_pclmulqdq_supported) { 8338 uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS]; 8339 Label L_wordByWord; 8340 Label L_byteByByteProlog; 8341 Label L_byteByByte; 8342 Label L_exit; 8343 8344 if (is_pclmulqdq_supported ) { 8345 const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::_crc32c_table_addr; 8346 const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::_crc32c_table_addr+1); 8347 8348 const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 2); 8349 const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 3); 8350 8351 const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 4); 8352 const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 5); 8353 assert((CRC32C_NUM_PRECOMPUTED_CONSTANTS - 1 ) == 5, "Checking whether you declared all of the constants based on the number of \"chunks\""); 8354 } else { 8355 const_or_pre_comp_const_index[0] = 1; 8356 const_or_pre_comp_const_index[1] = 0; 8357 8358 const_or_pre_comp_const_index[2] = 3; 8359 const_or_pre_comp_const_index[3] = 2; 8360 8361 const_or_pre_comp_const_index[4] = 5; 8362 const_or_pre_comp_const_index[5] = 4; 8363 } 8364 crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported, 8365 in2, in1, in_out, 8366 tmp1, tmp2, tmp3, 8367 w_xtmp1, w_xtmp2, w_xtmp3, 8368 tmp4, tmp5, 8369 tmp6); 8370 crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported, 8371 in2, in1, in_out, 8372 tmp1, tmp2, tmp3, 8373 w_xtmp1, w_xtmp2, w_xtmp3, 8374 tmp4, tmp5, 8375 tmp6); 8376 crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported, 8377 in2, in1, in_out, 8378 tmp1, tmp2, tmp3, 8379 w_xtmp1, w_xtmp2, w_xtmp3, 8380 tmp4, tmp5, 8381 tmp6); 8382 movl(tmp1, in2); 8383 andl(tmp1, 0x00000007); 8384 negl(tmp1); 8385 addl(tmp1, in2); 8386 addq(tmp1, in1); 8387 8388 cmpq(in1, tmp1); 8389 jccb(Assembler::greaterEqual, L_byteByByteProlog); 8390 align(16); 8391 BIND(L_wordByWord); 8392 crc32(in_out, Address(in1, 0), 8); 8393 addq(in1, 8); 8394 cmpq(in1, tmp1); 8395 jcc(Assembler::less, L_wordByWord); 8396 8397 BIND(L_byteByByteProlog); 8398 andl(in2, 0x00000007); 8399 movl(tmp2, 1); 8400 8401 cmpl(tmp2, in2); 8402 jccb(Assembler::greater, L_exit); 8403 BIND(L_byteByByte); 8404 crc32(in_out, Address(in1, 0), 1); 8405 incq(in1); 8406 incl(tmp2); 8407 cmpl(tmp2, in2); 8408 jcc(Assembler::lessEqual, L_byteByByte); 8409 8410 BIND(L_exit); 8411 } 8412 #else 8413 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2, 8414 Register tmp1, Register tmp2, Register tmp3, 8415 Register tmp4, Register tmp5, Register tmp6, 8416 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3, 8417 bool is_pclmulqdq_supported) { 8418 uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS]; 8419 Label L_wordByWord; 8420 Label L_byteByByteProlog; 8421 Label L_byteByByte; 8422 Label L_exit; 8423 8424 if (is_pclmulqdq_supported) { 8425 const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::_crc32c_table_addr; 8426 const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 1); 8427 8428 const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 2); 8429 const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 3); 8430 8431 const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 4); 8432 const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 5); 8433 } else { 8434 const_or_pre_comp_const_index[0] = 1; 8435 const_or_pre_comp_const_index[1] = 0; 8436 8437 const_or_pre_comp_const_index[2] = 3; 8438 const_or_pre_comp_const_index[3] = 2; 8439 8440 const_or_pre_comp_const_index[4] = 5; 8441 const_or_pre_comp_const_index[5] = 4; 8442 } 8443 crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported, 8444 in2, in1, in_out, 8445 tmp1, tmp2, tmp3, 8446 w_xtmp1, w_xtmp2, w_xtmp3, 8447 tmp4, tmp5, 8448 tmp6); 8449 crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported, 8450 in2, in1, in_out, 8451 tmp1, tmp2, tmp3, 8452 w_xtmp1, w_xtmp2, w_xtmp3, 8453 tmp4, tmp5, 8454 tmp6); 8455 crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported, 8456 in2, in1, in_out, 8457 tmp1, tmp2, tmp3, 8458 w_xtmp1, w_xtmp2, w_xtmp3, 8459 tmp4, tmp5, 8460 tmp6); 8461 movl(tmp1, in2); 8462 andl(tmp1, 0x00000007); 8463 negl(tmp1); 8464 addl(tmp1, in2); 8465 addl(tmp1, in1); 8466 8467 BIND(L_wordByWord); 8468 cmpl(in1, tmp1); 8469 jcc(Assembler::greaterEqual, L_byteByByteProlog); 8470 crc32(in_out, Address(in1,0), 4); 8471 addl(in1, 4); 8472 jmp(L_wordByWord); 8473 8474 BIND(L_byteByByteProlog); 8475 andl(in2, 0x00000007); 8476 movl(tmp2, 1); 8477 8478 BIND(L_byteByByte); 8479 cmpl(tmp2, in2); 8480 jccb(Assembler::greater, L_exit); 8481 movb(tmp1, Address(in1, 0)); 8482 crc32(in_out, tmp1, 1); 8483 incl(in1); 8484 incl(tmp2); 8485 jmp(L_byteByByte); 8486 8487 BIND(L_exit); 8488 } 8489 #endif // LP64 8490 #undef BIND 8491 #undef BLOCK_COMMENT 8492 8493 // Compress char[] array to byte[]. 8494 // ..\jdk\src\java.base\share\classes\java\lang\StringUTF16.java 8495 // @IntrinsicCandidate 8496 // private static int compress(char[] src, int srcOff, byte[] dst, int dstOff, int len) { 8497 // for (int i = 0; i < len; i++) { 8498 // int c = src[srcOff++]; 8499 // if (c >>> 8 != 0) { 8500 // return 0; 8501 // } 8502 // dst[dstOff++] = (byte)c; 8503 // } 8504 // return len; 8505 // } 8506 void MacroAssembler::char_array_compress(Register src, Register dst, Register len, 8507 XMMRegister tmp1Reg, XMMRegister tmp2Reg, 8508 XMMRegister tmp3Reg, XMMRegister tmp4Reg, 8509 Register tmp5, Register result, KRegister mask1, KRegister mask2) { 8510 Label copy_chars_loop, return_length, return_zero, done; 8511 8512 // rsi: src 8513 // rdi: dst 8514 // rdx: len 8515 // rcx: tmp5 8516 // rax: result 8517 8518 // rsi holds start addr of source char[] to be compressed 8519 // rdi holds start addr of destination byte[] 8520 // rdx holds length 8521 8522 assert(len != result, ""); 8523 8524 // save length for return 8525 push(len); 8526 8527 if ((AVX3Threshold == 0) && (UseAVX > 2) && // AVX512 8528 VM_Version::supports_avx512vlbw() && 8529 VM_Version::supports_bmi2()) { 8530 8531 Label copy_32_loop, copy_loop_tail, below_threshold; 8532 8533 // alignment 8534 Label post_alignment; 8535 8536 // if length of the string is less than 16, handle it in an old fashioned way 8537 testl(len, -32); 8538 jcc(Assembler::zero, below_threshold); 8539 8540 // First check whether a character is compressible ( <= 0xFF). 8541 // Create mask to test for Unicode chars inside zmm vector 8542 movl(result, 0x00FF); 8543 evpbroadcastw(tmp2Reg, result, Assembler::AVX_512bit); 8544 8545 testl(len, -64); 8546 jcc(Assembler::zero, post_alignment); 8547 8548 movl(tmp5, dst); 8549 andl(tmp5, (32 - 1)); 8550 negl(tmp5); 8551 andl(tmp5, (32 - 1)); 8552 8553 // bail out when there is nothing to be done 8554 testl(tmp5, 0xFFFFFFFF); 8555 jcc(Assembler::zero, post_alignment); 8556 8557 // ~(~0 << len), where len is the # of remaining elements to process 8558 movl(result, 0xFFFFFFFF); 8559 shlxl(result, result, tmp5); 8560 notl(result); 8561 kmovdl(mask2, result); 8562 8563 evmovdquw(tmp1Reg, mask2, Address(src, 0), /*merge*/ false, Assembler::AVX_512bit); 8564 evpcmpw(mask1, mask2, tmp1Reg, tmp2Reg, Assembler::le, /*signed*/ false, Assembler::AVX_512bit); 8565 ktestd(mask1, mask2); 8566 jcc(Assembler::carryClear, return_zero); 8567 8568 evpmovwb(Address(dst, 0), mask2, tmp1Reg, Assembler::AVX_512bit); 8569 8570 addptr(src, tmp5); 8571 addptr(src, tmp5); 8572 addptr(dst, tmp5); 8573 subl(len, tmp5); 8574 8575 bind(post_alignment); 8576 // end of alignment 8577 8578 movl(tmp5, len); 8579 andl(tmp5, (32 - 1)); // tail count (in chars) 8580 andl(len, ~(32 - 1)); // vector count (in chars) 8581 jcc(Assembler::zero, copy_loop_tail); 8582 8583 lea(src, Address(src, len, Address::times_2)); 8584 lea(dst, Address(dst, len, Address::times_1)); 8585 negptr(len); 8586 8587 bind(copy_32_loop); 8588 evmovdquw(tmp1Reg, Address(src, len, Address::times_2), Assembler::AVX_512bit); 8589 evpcmpuw(mask1, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit); 8590 kortestdl(mask1, mask1); 8591 jcc(Assembler::carryClear, return_zero); 8592 8593 // All elements in current processed chunk are valid candidates for 8594 // compression. Write a truncated byte elements to the memory. 8595 evpmovwb(Address(dst, len, Address::times_1), tmp1Reg, Assembler::AVX_512bit); 8596 addptr(len, 32); 8597 jcc(Assembler::notZero, copy_32_loop); 8598 8599 bind(copy_loop_tail); 8600 // bail out when there is nothing to be done 8601 testl(tmp5, 0xFFFFFFFF); 8602 jcc(Assembler::zero, return_length); 8603 8604 movl(len, tmp5); 8605 8606 // ~(~0 << len), where len is the # of remaining elements to process 8607 movl(result, 0xFFFFFFFF); 8608 shlxl(result, result, len); 8609 notl(result); 8610 8611 kmovdl(mask2, result); 8612 8613 evmovdquw(tmp1Reg, mask2, Address(src, 0), /*merge*/ false, Assembler::AVX_512bit); 8614 evpcmpw(mask1, mask2, tmp1Reg, tmp2Reg, Assembler::le, /*signed*/ false, Assembler::AVX_512bit); 8615 ktestd(mask1, mask2); 8616 jcc(Assembler::carryClear, return_zero); 8617 8618 evpmovwb(Address(dst, 0), mask2, tmp1Reg, Assembler::AVX_512bit); 8619 jmp(return_length); 8620 8621 bind(below_threshold); 8622 } 8623 8624 if (UseSSE42Intrinsics) { 8625 Label copy_32_loop, copy_16, copy_tail; 8626 8627 movl(result, len); 8628 8629 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vectors 8630 8631 // vectored compression 8632 andl(len, 0xfffffff0); // vector count (in chars) 8633 andl(result, 0x0000000f); // tail count (in chars) 8634 testl(len, len); 8635 jcc(Assembler::zero, copy_16); 8636 8637 // compress 16 chars per iter 8638 movdl(tmp1Reg, tmp5); 8639 pshufd(tmp1Reg, tmp1Reg, 0); // store Unicode mask in tmp1Reg 8640 pxor(tmp4Reg, tmp4Reg); 8641 8642 lea(src, Address(src, len, Address::times_2)); 8643 lea(dst, Address(dst, len, Address::times_1)); 8644 negptr(len); 8645 8646 bind(copy_32_loop); 8647 movdqu(tmp2Reg, Address(src, len, Address::times_2)); // load 1st 8 characters 8648 por(tmp4Reg, tmp2Reg); 8649 movdqu(tmp3Reg, Address(src, len, Address::times_2, 16)); // load next 8 characters 8650 por(tmp4Reg, tmp3Reg); 8651 ptest(tmp4Reg, tmp1Reg); // check for Unicode chars in next vector 8652 jcc(Assembler::notZero, return_zero); 8653 packuswb(tmp2Reg, tmp3Reg); // only ASCII chars; compress each to 1 byte 8654 movdqu(Address(dst, len, Address::times_1), tmp2Reg); 8655 addptr(len, 16); 8656 jcc(Assembler::notZero, copy_32_loop); 8657 8658 // compress next vector of 8 chars (if any) 8659 bind(copy_16); 8660 movl(len, result); 8661 andl(len, 0xfffffff8); // vector count (in chars) 8662 andl(result, 0x00000007); // tail count (in chars) 8663 testl(len, len); 8664 jccb(Assembler::zero, copy_tail); 8665 8666 movdl(tmp1Reg, tmp5); 8667 pshufd(tmp1Reg, tmp1Reg, 0); // store Unicode mask in tmp1Reg 8668 pxor(tmp3Reg, tmp3Reg); 8669 8670 movdqu(tmp2Reg, Address(src, 0)); 8671 ptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector 8672 jccb(Assembler::notZero, return_zero); 8673 packuswb(tmp2Reg, tmp3Reg); // only LATIN1 chars; compress each to 1 byte 8674 movq(Address(dst, 0), tmp2Reg); 8675 addptr(src, 16); 8676 addptr(dst, 8); 8677 8678 bind(copy_tail); 8679 movl(len, result); 8680 } 8681 // compress 1 char per iter 8682 testl(len, len); 8683 jccb(Assembler::zero, return_length); 8684 lea(src, Address(src, len, Address::times_2)); 8685 lea(dst, Address(dst, len, Address::times_1)); 8686 negptr(len); 8687 8688 bind(copy_chars_loop); 8689 load_unsigned_short(result, Address(src, len, Address::times_2)); 8690 testl(result, 0xff00); // check if Unicode char 8691 jccb(Assembler::notZero, return_zero); 8692 movb(Address(dst, len, Address::times_1), result); // ASCII char; compress to 1 byte 8693 increment(len); 8694 jcc(Assembler::notZero, copy_chars_loop); 8695 8696 // if compression succeeded, return length 8697 bind(return_length); 8698 pop(result); 8699 jmpb(done); 8700 8701 // if compression failed, return 0 8702 bind(return_zero); 8703 xorl(result, result); 8704 addptr(rsp, wordSize); 8705 8706 bind(done); 8707 } 8708 8709 // Inflate byte[] array to char[]. 8710 // ..\jdk\src\java.base\share\classes\java\lang\StringLatin1.java 8711 // @IntrinsicCandidate 8712 // private static void inflate(byte[] src, int srcOff, char[] dst, int dstOff, int len) { 8713 // for (int i = 0; i < len; i++) { 8714 // dst[dstOff++] = (char)(src[srcOff++] & 0xff); 8715 // } 8716 // } 8717 void MacroAssembler::byte_array_inflate(Register src, Register dst, Register len, 8718 XMMRegister tmp1, Register tmp2, KRegister mask) { 8719 Label copy_chars_loop, done, below_threshold, avx3_threshold; 8720 // rsi: src 8721 // rdi: dst 8722 // rdx: len 8723 // rcx: tmp2 8724 8725 // rsi holds start addr of source byte[] to be inflated 8726 // rdi holds start addr of destination char[] 8727 // rdx holds length 8728 assert_different_registers(src, dst, len, tmp2); 8729 movl(tmp2, len); 8730 if ((UseAVX > 2) && // AVX512 8731 VM_Version::supports_avx512vlbw() && 8732 VM_Version::supports_bmi2()) { 8733 8734 Label copy_32_loop, copy_tail; 8735 Register tmp3_aliased = len; 8736 8737 // if length of the string is less than 16, handle it in an old fashioned way 8738 testl(len, -16); 8739 jcc(Assembler::zero, below_threshold); 8740 8741 testl(len, -1 * AVX3Threshold); 8742 jcc(Assembler::zero, avx3_threshold); 8743 8744 // In order to use only one arithmetic operation for the main loop we use 8745 // this pre-calculation 8746 andl(tmp2, (32 - 1)); // tail count (in chars), 32 element wide loop 8747 andl(len, -32); // vector count 8748 jccb(Assembler::zero, copy_tail); 8749 8750 lea(src, Address(src, len, Address::times_1)); 8751 lea(dst, Address(dst, len, Address::times_2)); 8752 negptr(len); 8753 8754 8755 // inflate 32 chars per iter 8756 bind(copy_32_loop); 8757 vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_512bit); 8758 evmovdquw(Address(dst, len, Address::times_2), tmp1, Assembler::AVX_512bit); 8759 addptr(len, 32); 8760 jcc(Assembler::notZero, copy_32_loop); 8761 8762 bind(copy_tail); 8763 // bail out when there is nothing to be done 8764 testl(tmp2, -1); // we don't destroy the contents of tmp2 here 8765 jcc(Assembler::zero, done); 8766 8767 // ~(~0 << length), where length is the # of remaining elements to process 8768 movl(tmp3_aliased, -1); 8769 shlxl(tmp3_aliased, tmp3_aliased, tmp2); 8770 notl(tmp3_aliased); 8771 kmovdl(mask, tmp3_aliased); 8772 evpmovzxbw(tmp1, mask, Address(src, 0), Assembler::AVX_512bit); 8773 evmovdquw(Address(dst, 0), mask, tmp1, /*merge*/ true, Assembler::AVX_512bit); 8774 8775 jmp(done); 8776 bind(avx3_threshold); 8777 } 8778 if (UseSSE42Intrinsics) { 8779 Label copy_16_loop, copy_8_loop, copy_bytes, copy_new_tail, copy_tail; 8780 8781 if (UseAVX > 1) { 8782 andl(tmp2, (16 - 1)); 8783 andl(len, -16); 8784 jccb(Assembler::zero, copy_new_tail); 8785 } else { 8786 andl(tmp2, 0x00000007); // tail count (in chars) 8787 andl(len, 0xfffffff8); // vector count (in chars) 8788 jccb(Assembler::zero, copy_tail); 8789 } 8790 8791 // vectored inflation 8792 lea(src, Address(src, len, Address::times_1)); 8793 lea(dst, Address(dst, len, Address::times_2)); 8794 negptr(len); 8795 8796 if (UseAVX > 1) { 8797 bind(copy_16_loop); 8798 vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_256bit); 8799 vmovdqu(Address(dst, len, Address::times_2), tmp1); 8800 addptr(len, 16); 8801 jcc(Assembler::notZero, copy_16_loop); 8802 8803 bind(below_threshold); 8804 bind(copy_new_tail); 8805 movl(len, tmp2); 8806 andl(tmp2, 0x00000007); 8807 andl(len, 0xFFFFFFF8); 8808 jccb(Assembler::zero, copy_tail); 8809 8810 pmovzxbw(tmp1, Address(src, 0)); 8811 movdqu(Address(dst, 0), tmp1); 8812 addptr(src, 8); 8813 addptr(dst, 2 * 8); 8814 8815 jmp(copy_tail, true); 8816 } 8817 8818 // inflate 8 chars per iter 8819 bind(copy_8_loop); 8820 pmovzxbw(tmp1, Address(src, len, Address::times_1)); // unpack to 8 words 8821 movdqu(Address(dst, len, Address::times_2), tmp1); 8822 addptr(len, 8); 8823 jcc(Assembler::notZero, copy_8_loop); 8824 8825 bind(copy_tail); 8826 movl(len, tmp2); 8827 8828 cmpl(len, 4); 8829 jccb(Assembler::less, copy_bytes); 8830 8831 movdl(tmp1, Address(src, 0)); // load 4 byte chars 8832 pmovzxbw(tmp1, tmp1); 8833 movq(Address(dst, 0), tmp1); 8834 subptr(len, 4); 8835 addptr(src, 4); 8836 addptr(dst, 8); 8837 8838 bind(copy_bytes); 8839 } else { 8840 bind(below_threshold); 8841 } 8842 8843 testl(len, len); 8844 jccb(Assembler::zero, done); 8845 lea(src, Address(src, len, Address::times_1)); 8846 lea(dst, Address(dst, len, Address::times_2)); 8847 negptr(len); 8848 8849 // inflate 1 char per iter 8850 bind(copy_chars_loop); 8851 load_unsigned_byte(tmp2, Address(src, len, Address::times_1)); // load byte char 8852 movw(Address(dst, len, Address::times_2), tmp2); // inflate byte char to word 8853 increment(len); 8854 jcc(Assembler::notZero, copy_chars_loop); 8855 8856 bind(done); 8857 } 8858 8859 8860 void MacroAssembler::evmovdqu(BasicType type, KRegister kmask, XMMRegister dst, Address src, bool merge, int vector_len) { 8861 switch(type) { 8862 case T_BYTE: 8863 case T_BOOLEAN: 8864 evmovdqub(dst, kmask, src, merge, vector_len); 8865 break; 8866 case T_CHAR: 8867 case T_SHORT: 8868 evmovdquw(dst, kmask, src, merge, vector_len); 8869 break; 8870 case T_INT: 8871 case T_FLOAT: 8872 evmovdqul(dst, kmask, src, merge, vector_len); 8873 break; 8874 case T_LONG: 8875 case T_DOUBLE: 8876 evmovdquq(dst, kmask, src, merge, vector_len); 8877 break; 8878 default: 8879 fatal("Unexpected type argument %s", type2name(type)); 8880 break; 8881 } 8882 } 8883 8884 void MacroAssembler::evmovdqu(BasicType type, KRegister kmask, Address dst, XMMRegister src, bool merge, int vector_len) { 8885 switch(type) { 8886 case T_BYTE: 8887 case T_BOOLEAN: 8888 evmovdqub(dst, kmask, src, merge, vector_len); 8889 break; 8890 case T_CHAR: 8891 case T_SHORT: 8892 evmovdquw(dst, kmask, src, merge, vector_len); 8893 break; 8894 case T_INT: 8895 case T_FLOAT: 8896 evmovdqul(dst, kmask, src, merge, vector_len); 8897 break; 8898 case T_LONG: 8899 case T_DOUBLE: 8900 evmovdquq(dst, kmask, src, merge, vector_len); 8901 break; 8902 default: 8903 fatal("Unexpected type argument %s", type2name(type)); 8904 break; 8905 } 8906 } 8907 8908 void MacroAssembler::knot(uint masklen, KRegister dst, KRegister src, KRegister ktmp, Register rtmp) { 8909 switch(masklen) { 8910 case 2: 8911 knotbl(dst, src); 8912 movl(rtmp, 3); 8913 kmovbl(ktmp, rtmp); 8914 kandbl(dst, ktmp, dst); 8915 break; 8916 case 4: 8917 knotbl(dst, src); 8918 movl(rtmp, 15); 8919 kmovbl(ktmp, rtmp); 8920 kandbl(dst, ktmp, dst); 8921 break; 8922 case 8: 8923 knotbl(dst, src); 8924 break; 8925 case 16: 8926 knotwl(dst, src); 8927 break; 8928 case 32: 8929 knotdl(dst, src); 8930 break; 8931 case 64: 8932 knotql(dst, src); 8933 break; 8934 default: 8935 fatal("Unexpected vector length %d", masklen); 8936 break; 8937 } 8938 } 8939 8940 void MacroAssembler::kand(BasicType type, KRegister dst, KRegister src1, KRegister src2) { 8941 switch(type) { 8942 case T_BOOLEAN: 8943 case T_BYTE: 8944 kandbl(dst, src1, src2); 8945 break; 8946 case T_CHAR: 8947 case T_SHORT: 8948 kandwl(dst, src1, src2); 8949 break; 8950 case T_INT: 8951 case T_FLOAT: 8952 kanddl(dst, src1, src2); 8953 break; 8954 case T_LONG: 8955 case T_DOUBLE: 8956 kandql(dst, src1, src2); 8957 break; 8958 default: 8959 fatal("Unexpected type argument %s", type2name(type)); 8960 break; 8961 } 8962 } 8963 8964 void MacroAssembler::kor(BasicType type, KRegister dst, KRegister src1, KRegister src2) { 8965 switch(type) { 8966 case T_BOOLEAN: 8967 case T_BYTE: 8968 korbl(dst, src1, src2); 8969 break; 8970 case T_CHAR: 8971 case T_SHORT: 8972 korwl(dst, src1, src2); 8973 break; 8974 case T_INT: 8975 case T_FLOAT: 8976 kordl(dst, src1, src2); 8977 break; 8978 case T_LONG: 8979 case T_DOUBLE: 8980 korql(dst, src1, src2); 8981 break; 8982 default: 8983 fatal("Unexpected type argument %s", type2name(type)); 8984 break; 8985 } 8986 } 8987 8988 void MacroAssembler::kxor(BasicType type, KRegister dst, KRegister src1, KRegister src2) { 8989 switch(type) { 8990 case T_BOOLEAN: 8991 case T_BYTE: 8992 kxorbl(dst, src1, src2); 8993 break; 8994 case T_CHAR: 8995 case T_SHORT: 8996 kxorwl(dst, src1, src2); 8997 break; 8998 case T_INT: 8999 case T_FLOAT: 9000 kxordl(dst, src1, src2); 9001 break; 9002 case T_LONG: 9003 case T_DOUBLE: 9004 kxorql(dst, src1, src2); 9005 break; 9006 default: 9007 fatal("Unexpected type argument %s", type2name(type)); 9008 break; 9009 } 9010 } 9011 9012 void MacroAssembler::evperm(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) { 9013 switch(type) { 9014 case T_BOOLEAN: 9015 case T_BYTE: 9016 evpermb(dst, mask, nds, src, merge, vector_len); break; 9017 case T_CHAR: 9018 case T_SHORT: 9019 evpermw(dst, mask, nds, src, merge, vector_len); break; 9020 case T_INT: 9021 case T_FLOAT: 9022 evpermd(dst, mask, nds, src, merge, vector_len); break; 9023 case T_LONG: 9024 case T_DOUBLE: 9025 evpermq(dst, mask, nds, src, merge, vector_len); break; 9026 default: 9027 fatal("Unexpected type argument %s", type2name(type)); break; 9028 } 9029 } 9030 9031 void MacroAssembler::evperm(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) { 9032 switch(type) { 9033 case T_BOOLEAN: 9034 case T_BYTE: 9035 evpermb(dst, mask, nds, src, merge, vector_len); break; 9036 case T_CHAR: 9037 case T_SHORT: 9038 evpermw(dst, mask, nds, src, merge, vector_len); break; 9039 case T_INT: 9040 case T_FLOAT: 9041 evpermd(dst, mask, nds, src, merge, vector_len); break; 9042 case T_LONG: 9043 case T_DOUBLE: 9044 evpermq(dst, mask, nds, src, merge, vector_len); break; 9045 default: 9046 fatal("Unexpected type argument %s", type2name(type)); break; 9047 } 9048 } 9049 9050 void MacroAssembler::evpmins(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) { 9051 switch(type) { 9052 case T_BYTE: 9053 evpminsb(dst, mask, nds, src, merge, vector_len); break; 9054 case T_SHORT: 9055 evpminsw(dst, mask, nds, src, merge, vector_len); break; 9056 case T_INT: 9057 evpminsd(dst, mask, nds, src, merge, vector_len); break; 9058 case T_LONG: 9059 evpminsq(dst, mask, nds, src, merge, vector_len); break; 9060 default: 9061 fatal("Unexpected type argument %s", type2name(type)); break; 9062 } 9063 } 9064 9065 void MacroAssembler::evpmaxs(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) { 9066 switch(type) { 9067 case T_BYTE: 9068 evpmaxsb(dst, mask, nds, src, merge, vector_len); break; 9069 case T_SHORT: 9070 evpmaxsw(dst, mask, nds, src, merge, vector_len); break; 9071 case T_INT: 9072 evpmaxsd(dst, mask, nds, src, merge, vector_len); break; 9073 case T_LONG: 9074 evpmaxsq(dst, mask, nds, src, merge, vector_len); break; 9075 default: 9076 fatal("Unexpected type argument %s", type2name(type)); break; 9077 } 9078 } 9079 9080 void MacroAssembler::evpmins(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) { 9081 switch(type) { 9082 case T_BYTE: 9083 evpminsb(dst, mask, nds, src, merge, vector_len); break; 9084 case T_SHORT: 9085 evpminsw(dst, mask, nds, src, merge, vector_len); break; 9086 case T_INT: 9087 evpminsd(dst, mask, nds, src, merge, vector_len); break; 9088 case T_LONG: 9089 evpminsq(dst, mask, nds, src, merge, vector_len); break; 9090 default: 9091 fatal("Unexpected type argument %s", type2name(type)); break; 9092 } 9093 } 9094 9095 void MacroAssembler::evpmaxs(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) { 9096 switch(type) { 9097 case T_BYTE: 9098 evpmaxsb(dst, mask, nds, src, merge, vector_len); break; 9099 case T_SHORT: 9100 evpmaxsw(dst, mask, nds, src, merge, vector_len); break; 9101 case T_INT: 9102 evpmaxsd(dst, mask, nds, src, merge, vector_len); break; 9103 case T_LONG: 9104 evpmaxsq(dst, mask, nds, src, merge, vector_len); break; 9105 default: 9106 fatal("Unexpected type argument %s", type2name(type)); break; 9107 } 9108 } 9109 9110 void MacroAssembler::evxor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) { 9111 switch(type) { 9112 case T_INT: 9113 evpxord(dst, mask, nds, src, merge, vector_len); break; 9114 case T_LONG: 9115 evpxorq(dst, mask, nds, src, merge, vector_len); break; 9116 default: 9117 fatal("Unexpected type argument %s", type2name(type)); break; 9118 } 9119 } 9120 9121 void MacroAssembler::evxor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) { 9122 switch(type) { 9123 case T_INT: 9124 evpxord(dst, mask, nds, src, merge, vector_len); break; 9125 case T_LONG: 9126 evpxorq(dst, mask, nds, src, merge, vector_len); break; 9127 default: 9128 fatal("Unexpected type argument %s", type2name(type)); break; 9129 } 9130 } 9131 9132 void MacroAssembler::evor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) { 9133 switch(type) { 9134 case T_INT: 9135 Assembler::evpord(dst, mask, nds, src, merge, vector_len); break; 9136 case T_LONG: 9137 evporq(dst, mask, nds, src, merge, vector_len); break; 9138 default: 9139 fatal("Unexpected type argument %s", type2name(type)); break; 9140 } 9141 } 9142 9143 void MacroAssembler::evor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) { 9144 switch(type) { 9145 case T_INT: 9146 Assembler::evpord(dst, mask, nds, src, merge, vector_len); break; 9147 case T_LONG: 9148 evporq(dst, mask, nds, src, merge, vector_len); break; 9149 default: 9150 fatal("Unexpected type argument %s", type2name(type)); break; 9151 } 9152 } 9153 9154 void MacroAssembler::evand(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) { 9155 switch(type) { 9156 case T_INT: 9157 evpandd(dst, mask, nds, src, merge, vector_len); break; 9158 case T_LONG: 9159 evpandq(dst, mask, nds, src, merge, vector_len); break; 9160 default: 9161 fatal("Unexpected type argument %s", type2name(type)); break; 9162 } 9163 } 9164 9165 void MacroAssembler::evand(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) { 9166 switch(type) { 9167 case T_INT: 9168 evpandd(dst, mask, nds, src, merge, vector_len); break; 9169 case T_LONG: 9170 evpandq(dst, mask, nds, src, merge, vector_len); break; 9171 default: 9172 fatal("Unexpected type argument %s", type2name(type)); break; 9173 } 9174 } 9175 9176 void MacroAssembler::kortest(uint masklen, KRegister src1, KRegister src2) { 9177 switch(masklen) { 9178 case 8: 9179 kortestbl(src1, src2); 9180 break; 9181 case 16: 9182 kortestwl(src1, src2); 9183 break; 9184 case 32: 9185 kortestdl(src1, src2); 9186 break; 9187 case 64: 9188 kortestql(src1, src2); 9189 break; 9190 default: 9191 fatal("Unexpected mask length %d", masklen); 9192 break; 9193 } 9194 } 9195 9196 9197 void MacroAssembler::ktest(uint masklen, KRegister src1, KRegister src2) { 9198 switch(masklen) { 9199 case 8: 9200 ktestbl(src1, src2); 9201 break; 9202 case 16: 9203 ktestwl(src1, src2); 9204 break; 9205 case 32: 9206 ktestdl(src1, src2); 9207 break; 9208 case 64: 9209 ktestql(src1, src2); 9210 break; 9211 default: 9212 fatal("Unexpected mask length %d", masklen); 9213 break; 9214 } 9215 } 9216 9217 void MacroAssembler::evrold(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vlen_enc) { 9218 switch(type) { 9219 case T_INT: 9220 evprold(dst, mask, src, shift, merge, vlen_enc); break; 9221 case T_LONG: 9222 evprolq(dst, mask, src, shift, merge, vlen_enc); break; 9223 default: 9224 fatal("Unexpected type argument %s", type2name(type)); break; 9225 break; 9226 } 9227 } 9228 9229 void MacroAssembler::evrord(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vlen_enc) { 9230 switch(type) { 9231 case T_INT: 9232 evprord(dst, mask, src, shift, merge, vlen_enc); break; 9233 case T_LONG: 9234 evprorq(dst, mask, src, shift, merge, vlen_enc); break; 9235 default: 9236 fatal("Unexpected type argument %s", type2name(type)); break; 9237 } 9238 } 9239 9240 void MacroAssembler::evrold(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src1, XMMRegister src2, bool merge, int vlen_enc) { 9241 switch(type) { 9242 case T_INT: 9243 evprolvd(dst, mask, src1, src2, merge, vlen_enc); break; 9244 case T_LONG: 9245 evprolvq(dst, mask, src1, src2, merge, vlen_enc); break; 9246 default: 9247 fatal("Unexpected type argument %s", type2name(type)); break; 9248 } 9249 } 9250 9251 void MacroAssembler::evrord(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src1, XMMRegister src2, bool merge, int vlen_enc) { 9252 switch(type) { 9253 case T_INT: 9254 evprorvd(dst, mask, src1, src2, merge, vlen_enc); break; 9255 case T_LONG: 9256 evprorvq(dst, mask, src1, src2, merge, vlen_enc); break; 9257 default: 9258 fatal("Unexpected type argument %s", type2name(type)); break; 9259 } 9260 } 9261 9262 void MacroAssembler::evpandq(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) { 9263 assert(rscratch != noreg || always_reachable(src), "missing"); 9264 9265 if (reachable(src)) { 9266 evpandq(dst, nds, as_Address(src), vector_len); 9267 } else { 9268 lea(rscratch, src); 9269 evpandq(dst, nds, Address(rscratch, 0), vector_len); 9270 } 9271 } 9272 9273 void MacroAssembler::evpaddq(XMMRegister dst, KRegister mask, XMMRegister nds, AddressLiteral src, bool merge, int vector_len, Register rscratch) { 9274 assert(rscratch != noreg || always_reachable(src), "missing"); 9275 9276 if (reachable(src)) { 9277 Assembler::evpaddq(dst, mask, nds, as_Address(src), merge, vector_len); 9278 } else { 9279 lea(rscratch, src); 9280 Assembler::evpaddq(dst, mask, nds, Address(rscratch, 0), merge, vector_len); 9281 } 9282 } 9283 9284 void MacroAssembler::evporq(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) { 9285 assert(rscratch != noreg || always_reachable(src), "missing"); 9286 9287 if (reachable(src)) { 9288 evporq(dst, nds, as_Address(src), vector_len); 9289 } else { 9290 lea(rscratch, src); 9291 evporq(dst, nds, Address(rscratch, 0), vector_len); 9292 } 9293 } 9294 9295 void MacroAssembler::vpternlogq(XMMRegister dst, int imm8, XMMRegister src2, AddressLiteral src3, int vector_len, Register rscratch) { 9296 assert(rscratch != noreg || always_reachable(src3), "missing"); 9297 9298 if (reachable(src3)) { 9299 vpternlogq(dst, imm8, src2, as_Address(src3), vector_len); 9300 } else { 9301 lea(rscratch, src3); 9302 vpternlogq(dst, imm8, src2, Address(rscratch, 0), vector_len); 9303 } 9304 } 9305 9306 #if COMPILER2_OR_JVMCI 9307 9308 void MacroAssembler::fill_masked(BasicType bt, Address dst, XMMRegister xmm, KRegister mask, 9309 Register length, Register temp, int vec_enc) { 9310 // Computing mask for predicated vector store. 9311 movptr(temp, -1); 9312 bzhiq(temp, temp, length); 9313 kmov(mask, temp); 9314 evmovdqu(bt, mask, dst, xmm, true, vec_enc); 9315 } 9316 9317 // Set memory operation for length "less than" 64 bytes. 9318 void MacroAssembler::fill64_masked(uint shift, Register dst, int disp, 9319 XMMRegister xmm, KRegister mask, Register length, 9320 Register temp, bool use64byteVector) { 9321 assert(MaxVectorSize >= 32, "vector length should be >= 32"); 9322 const BasicType type[] = { T_BYTE, T_SHORT, T_INT, T_LONG}; 9323 if (!use64byteVector) { 9324 fill32(dst, disp, xmm); 9325 subptr(length, 32 >> shift); 9326 fill32_masked(shift, dst, disp + 32, xmm, mask, length, temp); 9327 } else { 9328 assert(MaxVectorSize == 64, "vector length != 64"); 9329 fill_masked(type[shift], Address(dst, disp), xmm, mask, length, temp, Assembler::AVX_512bit); 9330 } 9331 } 9332 9333 9334 void MacroAssembler::fill32_masked(uint shift, Register dst, int disp, 9335 XMMRegister xmm, KRegister mask, Register length, 9336 Register temp) { 9337 assert(MaxVectorSize >= 32, "vector length should be >= 32"); 9338 const BasicType type[] = { T_BYTE, T_SHORT, T_INT, T_LONG}; 9339 fill_masked(type[shift], Address(dst, disp), xmm, mask, length, temp, Assembler::AVX_256bit); 9340 } 9341 9342 9343 void MacroAssembler::fill32(Address dst, XMMRegister xmm) { 9344 assert(MaxVectorSize >= 32, "vector length should be >= 32"); 9345 vmovdqu(dst, xmm); 9346 } 9347 9348 void MacroAssembler::fill32(Register dst, int disp, XMMRegister xmm) { 9349 fill32(Address(dst, disp), xmm); 9350 } 9351 9352 void MacroAssembler::fill64(Address dst, XMMRegister xmm, bool use64byteVector) { 9353 assert(MaxVectorSize >= 32, "vector length should be >= 32"); 9354 if (!use64byteVector) { 9355 fill32(dst, xmm); 9356 fill32(dst.plus_disp(32), xmm); 9357 } else { 9358 evmovdquq(dst, xmm, Assembler::AVX_512bit); 9359 } 9360 } 9361 9362 void MacroAssembler::fill64(Register dst, int disp, XMMRegister xmm, bool use64byteVector) { 9363 fill64(Address(dst, disp), xmm, use64byteVector); 9364 } 9365 9366 #ifdef _LP64 9367 void MacroAssembler::generate_fill_avx3(BasicType type, Register to, Register value, 9368 Register count, Register rtmp, XMMRegister xtmp) { 9369 Label L_exit; 9370 Label L_fill_start; 9371 Label L_fill_64_bytes; 9372 Label L_fill_96_bytes; 9373 Label L_fill_128_bytes; 9374 Label L_fill_128_bytes_loop; 9375 Label L_fill_128_loop_header; 9376 Label L_fill_128_bytes_loop_header; 9377 Label L_fill_128_bytes_loop_pre_header; 9378 Label L_fill_zmm_sequence; 9379 9380 int shift = -1; 9381 int avx3threshold = VM_Version::avx3_threshold(); 9382 switch(type) { 9383 case T_BYTE: shift = 0; 9384 break; 9385 case T_SHORT: shift = 1; 9386 break; 9387 case T_INT: shift = 2; 9388 break; 9389 /* Uncomment when LONG fill stubs are supported. 9390 case T_LONG: shift = 3; 9391 break; 9392 */ 9393 default: 9394 fatal("Unhandled type: %s\n", type2name(type)); 9395 } 9396 9397 if ((avx3threshold != 0) || (MaxVectorSize == 32)) { 9398 9399 if (MaxVectorSize == 64) { 9400 cmpq(count, avx3threshold >> shift); 9401 jcc(Assembler::greater, L_fill_zmm_sequence); 9402 } 9403 9404 evpbroadcast(type, xtmp, value, Assembler::AVX_256bit); 9405 9406 bind(L_fill_start); 9407 9408 cmpq(count, 32 >> shift); 9409 jccb(Assembler::greater, L_fill_64_bytes); 9410 fill32_masked(shift, to, 0, xtmp, k2, count, rtmp); 9411 jmp(L_exit); 9412 9413 bind(L_fill_64_bytes); 9414 cmpq(count, 64 >> shift); 9415 jccb(Assembler::greater, L_fill_96_bytes); 9416 fill64_masked(shift, to, 0, xtmp, k2, count, rtmp); 9417 jmp(L_exit); 9418 9419 bind(L_fill_96_bytes); 9420 cmpq(count, 96 >> shift); 9421 jccb(Assembler::greater, L_fill_128_bytes); 9422 fill64(to, 0, xtmp); 9423 subq(count, 64 >> shift); 9424 fill32_masked(shift, to, 64, xtmp, k2, count, rtmp); 9425 jmp(L_exit); 9426 9427 bind(L_fill_128_bytes); 9428 cmpq(count, 128 >> shift); 9429 jccb(Assembler::greater, L_fill_128_bytes_loop_pre_header); 9430 fill64(to, 0, xtmp); 9431 fill32(to, 64, xtmp); 9432 subq(count, 96 >> shift); 9433 fill32_masked(shift, to, 96, xtmp, k2, count, rtmp); 9434 jmp(L_exit); 9435 9436 bind(L_fill_128_bytes_loop_pre_header); 9437 { 9438 mov(rtmp, to); 9439 andq(rtmp, 31); 9440 jccb(Assembler::zero, L_fill_128_bytes_loop_header); 9441 negq(rtmp); 9442 addq(rtmp, 32); 9443 mov64(r8, -1L); 9444 bzhiq(r8, r8, rtmp); 9445 kmovql(k2, r8); 9446 evmovdqu(T_BYTE, k2, Address(to, 0), xtmp, true, Assembler::AVX_256bit); 9447 addq(to, rtmp); 9448 shrq(rtmp, shift); 9449 subq(count, rtmp); 9450 } 9451 9452 cmpq(count, 128 >> shift); 9453 jcc(Assembler::less, L_fill_start); 9454 9455 bind(L_fill_128_bytes_loop_header); 9456 subq(count, 128 >> shift); 9457 9458 align32(); 9459 bind(L_fill_128_bytes_loop); 9460 fill64(to, 0, xtmp); 9461 fill64(to, 64, xtmp); 9462 addq(to, 128); 9463 subq(count, 128 >> shift); 9464 jccb(Assembler::greaterEqual, L_fill_128_bytes_loop); 9465 9466 addq(count, 128 >> shift); 9467 jcc(Assembler::zero, L_exit); 9468 jmp(L_fill_start); 9469 } 9470 9471 if (MaxVectorSize == 64) { 9472 // Sequence using 64 byte ZMM register. 9473 Label L_fill_128_bytes_zmm; 9474 Label L_fill_192_bytes_zmm; 9475 Label L_fill_192_bytes_loop_zmm; 9476 Label L_fill_192_bytes_loop_header_zmm; 9477 Label L_fill_192_bytes_loop_pre_header_zmm; 9478 Label L_fill_start_zmm_sequence; 9479 9480 bind(L_fill_zmm_sequence); 9481 evpbroadcast(type, xtmp, value, Assembler::AVX_512bit); 9482 9483 bind(L_fill_start_zmm_sequence); 9484 cmpq(count, 64 >> shift); 9485 jccb(Assembler::greater, L_fill_128_bytes_zmm); 9486 fill64_masked(shift, to, 0, xtmp, k2, count, rtmp, true); 9487 jmp(L_exit); 9488 9489 bind(L_fill_128_bytes_zmm); 9490 cmpq(count, 128 >> shift); 9491 jccb(Assembler::greater, L_fill_192_bytes_zmm); 9492 fill64(to, 0, xtmp, true); 9493 subq(count, 64 >> shift); 9494 fill64_masked(shift, to, 64, xtmp, k2, count, rtmp, true); 9495 jmp(L_exit); 9496 9497 bind(L_fill_192_bytes_zmm); 9498 cmpq(count, 192 >> shift); 9499 jccb(Assembler::greater, L_fill_192_bytes_loop_pre_header_zmm); 9500 fill64(to, 0, xtmp, true); 9501 fill64(to, 64, xtmp, true); 9502 subq(count, 128 >> shift); 9503 fill64_masked(shift, to, 128, xtmp, k2, count, rtmp, true); 9504 jmp(L_exit); 9505 9506 bind(L_fill_192_bytes_loop_pre_header_zmm); 9507 { 9508 movq(rtmp, to); 9509 andq(rtmp, 63); 9510 jccb(Assembler::zero, L_fill_192_bytes_loop_header_zmm); 9511 negq(rtmp); 9512 addq(rtmp, 64); 9513 mov64(r8, -1L); 9514 bzhiq(r8, r8, rtmp); 9515 kmovql(k2, r8); 9516 evmovdqu(T_BYTE, k2, Address(to, 0), xtmp, true, Assembler::AVX_512bit); 9517 addq(to, rtmp); 9518 shrq(rtmp, shift); 9519 subq(count, rtmp); 9520 } 9521 9522 cmpq(count, 192 >> shift); 9523 jcc(Assembler::less, L_fill_start_zmm_sequence); 9524 9525 bind(L_fill_192_bytes_loop_header_zmm); 9526 subq(count, 192 >> shift); 9527 9528 align32(); 9529 bind(L_fill_192_bytes_loop_zmm); 9530 fill64(to, 0, xtmp, true); 9531 fill64(to, 64, xtmp, true); 9532 fill64(to, 128, xtmp, true); 9533 addq(to, 192); 9534 subq(count, 192 >> shift); 9535 jccb(Assembler::greaterEqual, L_fill_192_bytes_loop_zmm); 9536 9537 addq(count, 192 >> shift); 9538 jcc(Assembler::zero, L_exit); 9539 jmp(L_fill_start_zmm_sequence); 9540 } 9541 bind(L_exit); 9542 } 9543 #endif 9544 #endif //COMPILER2_OR_JVMCI 9545 9546 9547 #ifdef _LP64 9548 void MacroAssembler::convert_f2i(Register dst, XMMRegister src) { 9549 Label done; 9550 cvttss2sil(dst, src); 9551 // Conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub 9552 cmpl(dst, 0x80000000); // float_sign_flip 9553 jccb(Assembler::notEqual, done); 9554 subptr(rsp, 8); 9555 movflt(Address(rsp, 0), src); 9556 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2i_fixup()))); 9557 pop(dst); 9558 bind(done); 9559 } 9560 9561 void MacroAssembler::convert_d2i(Register dst, XMMRegister src) { 9562 Label done; 9563 cvttsd2sil(dst, src); 9564 // Conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub 9565 cmpl(dst, 0x80000000); // float_sign_flip 9566 jccb(Assembler::notEqual, done); 9567 subptr(rsp, 8); 9568 movdbl(Address(rsp, 0), src); 9569 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2i_fixup()))); 9570 pop(dst); 9571 bind(done); 9572 } 9573 9574 void MacroAssembler::convert_f2l(Register dst, XMMRegister src) { 9575 Label done; 9576 cvttss2siq(dst, src); 9577 cmp64(dst, ExternalAddress((address) StubRoutines::x86::double_sign_flip())); 9578 jccb(Assembler::notEqual, done); 9579 subptr(rsp, 8); 9580 movflt(Address(rsp, 0), src); 9581 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2l_fixup()))); 9582 pop(dst); 9583 bind(done); 9584 } 9585 9586 void MacroAssembler::round_float(Register dst, XMMRegister src, Register rtmp, Register rcx) { 9587 // Following code is line by line assembly translation rounding algorithm. 9588 // Please refer to java.lang.Math.round(float) algorithm for details. 9589 const int32_t FloatConsts_EXP_BIT_MASK = 0x7F800000; 9590 const int32_t FloatConsts_SIGNIFICAND_WIDTH = 24; 9591 const int32_t FloatConsts_EXP_BIAS = 127; 9592 const int32_t FloatConsts_SIGNIF_BIT_MASK = 0x007FFFFF; 9593 const int32_t MINUS_32 = 0xFFFFFFE0; 9594 Label L_special_case, L_block1, L_exit; 9595 movl(rtmp, FloatConsts_EXP_BIT_MASK); 9596 movdl(dst, src); 9597 andl(dst, rtmp); 9598 sarl(dst, FloatConsts_SIGNIFICAND_WIDTH - 1); 9599 movl(rtmp, FloatConsts_SIGNIFICAND_WIDTH - 2 + FloatConsts_EXP_BIAS); 9600 subl(rtmp, dst); 9601 movl(rcx, rtmp); 9602 movl(dst, MINUS_32); 9603 testl(rtmp, dst); 9604 jccb(Assembler::notEqual, L_special_case); 9605 movdl(dst, src); 9606 andl(dst, FloatConsts_SIGNIF_BIT_MASK); 9607 orl(dst, FloatConsts_SIGNIF_BIT_MASK + 1); 9608 movdl(rtmp, src); 9609 testl(rtmp, rtmp); 9610 jccb(Assembler::greaterEqual, L_block1); 9611 negl(dst); 9612 bind(L_block1); 9613 sarl(dst); 9614 addl(dst, 0x1); 9615 sarl(dst, 0x1); 9616 jmp(L_exit); 9617 bind(L_special_case); 9618 convert_f2i(dst, src); 9619 bind(L_exit); 9620 } 9621 9622 void MacroAssembler::round_double(Register dst, XMMRegister src, Register rtmp, Register rcx) { 9623 // Following code is line by line assembly translation rounding algorithm. 9624 // Please refer to java.lang.Math.round(double) algorithm for details. 9625 const int64_t DoubleConsts_EXP_BIT_MASK = 0x7FF0000000000000L; 9626 const int64_t DoubleConsts_SIGNIFICAND_WIDTH = 53; 9627 const int64_t DoubleConsts_EXP_BIAS = 1023; 9628 const int64_t DoubleConsts_SIGNIF_BIT_MASK = 0x000FFFFFFFFFFFFFL; 9629 const int64_t MINUS_64 = 0xFFFFFFFFFFFFFFC0L; 9630 Label L_special_case, L_block1, L_exit; 9631 mov64(rtmp, DoubleConsts_EXP_BIT_MASK); 9632 movq(dst, src); 9633 andq(dst, rtmp); 9634 sarq(dst, DoubleConsts_SIGNIFICAND_WIDTH - 1); 9635 mov64(rtmp, DoubleConsts_SIGNIFICAND_WIDTH - 2 + DoubleConsts_EXP_BIAS); 9636 subq(rtmp, dst); 9637 movq(rcx, rtmp); 9638 mov64(dst, MINUS_64); 9639 testq(rtmp, dst); 9640 jccb(Assembler::notEqual, L_special_case); 9641 movq(dst, src); 9642 mov64(rtmp, DoubleConsts_SIGNIF_BIT_MASK); 9643 andq(dst, rtmp); 9644 mov64(rtmp, DoubleConsts_SIGNIF_BIT_MASK + 1); 9645 orq(dst, rtmp); 9646 movq(rtmp, src); 9647 testq(rtmp, rtmp); 9648 jccb(Assembler::greaterEqual, L_block1); 9649 negq(dst); 9650 bind(L_block1); 9651 sarq(dst); 9652 addq(dst, 0x1); 9653 sarq(dst, 0x1); 9654 jmp(L_exit); 9655 bind(L_special_case); 9656 convert_d2l(dst, src); 9657 bind(L_exit); 9658 } 9659 9660 void MacroAssembler::convert_d2l(Register dst, XMMRegister src) { 9661 Label done; 9662 cvttsd2siq(dst, src); 9663 cmp64(dst, ExternalAddress((address) StubRoutines::x86::double_sign_flip())); 9664 jccb(Assembler::notEqual, done); 9665 subptr(rsp, 8); 9666 movdbl(Address(rsp, 0), src); 9667 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2l_fixup()))); 9668 pop(dst); 9669 bind(done); 9670 } 9671 9672 void MacroAssembler::cache_wb(Address line) 9673 { 9674 // 64 bit cpus always support clflush 9675 assert(VM_Version::supports_clflush(), "clflush should be available"); 9676 bool optimized = VM_Version::supports_clflushopt(); 9677 bool no_evict = VM_Version::supports_clwb(); 9678 9679 // prefer clwb (writeback without evict) otherwise 9680 // prefer clflushopt (potentially parallel writeback with evict) 9681 // otherwise fallback on clflush (serial writeback with evict) 9682 9683 if (optimized) { 9684 if (no_evict) { 9685 clwb(line); 9686 } else { 9687 clflushopt(line); 9688 } 9689 } else { 9690 // no need for fence when using CLFLUSH 9691 clflush(line); 9692 } 9693 } 9694 9695 void MacroAssembler::cache_wbsync(bool is_pre) 9696 { 9697 assert(VM_Version::supports_clflush(), "clflush should be available"); 9698 bool optimized = VM_Version::supports_clflushopt(); 9699 bool no_evict = VM_Version::supports_clwb(); 9700 9701 // pick the correct implementation 9702 9703 if (!is_pre && (optimized || no_evict)) { 9704 // need an sfence for post flush when using clflushopt or clwb 9705 // otherwise no no need for any synchroniaztion 9706 9707 sfence(); 9708 } 9709 } 9710 9711 #endif // _LP64 9712 9713 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) { 9714 switch (cond) { 9715 // Note some conditions are synonyms for others 9716 case Assembler::zero: return Assembler::notZero; 9717 case Assembler::notZero: return Assembler::zero; 9718 case Assembler::less: return Assembler::greaterEqual; 9719 case Assembler::lessEqual: return Assembler::greater; 9720 case Assembler::greater: return Assembler::lessEqual; 9721 case Assembler::greaterEqual: return Assembler::less; 9722 case Assembler::below: return Assembler::aboveEqual; 9723 case Assembler::belowEqual: return Assembler::above; 9724 case Assembler::above: return Assembler::belowEqual; 9725 case Assembler::aboveEqual: return Assembler::below; 9726 case Assembler::overflow: return Assembler::noOverflow; 9727 case Assembler::noOverflow: return Assembler::overflow; 9728 case Assembler::negative: return Assembler::positive; 9729 case Assembler::positive: return Assembler::negative; 9730 case Assembler::parity: return Assembler::noParity; 9731 case Assembler::noParity: return Assembler::parity; 9732 } 9733 ShouldNotReachHere(); return Assembler::overflow; 9734 } 9735 9736 SkipIfEqual::SkipIfEqual( 9737 MacroAssembler* masm, const bool* flag_addr, bool value, Register rscratch) { 9738 _masm = masm; 9739 _masm->cmp8(ExternalAddress((address)flag_addr), value, rscratch); 9740 _masm->jcc(Assembler::equal, _label); 9741 } 9742 9743 SkipIfEqual::~SkipIfEqual() { 9744 _masm->bind(_label); 9745 } 9746 9747 // 32-bit Windows has its own fast-path implementation 9748 // of get_thread 9749 #if !defined(WIN32) || defined(_LP64) 9750 9751 // This is simply a call to Thread::current() 9752 void MacroAssembler::get_thread(Register thread) { 9753 if (thread != rax) { 9754 push(rax); 9755 } 9756 LP64_ONLY(push(rdi);) 9757 LP64_ONLY(push(rsi);) 9758 push(rdx); 9759 push(rcx); 9760 #ifdef _LP64 9761 push(r8); 9762 push(r9); 9763 push(r10); 9764 push(r11); 9765 #endif 9766 9767 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, Thread::current), 0); 9768 9769 #ifdef _LP64 9770 pop(r11); 9771 pop(r10); 9772 pop(r9); 9773 pop(r8); 9774 #endif 9775 pop(rcx); 9776 pop(rdx); 9777 LP64_ONLY(pop(rsi);) 9778 LP64_ONLY(pop(rdi);) 9779 if (thread != rax) { 9780 mov(thread, rax); 9781 pop(rax); 9782 } 9783 } 9784 9785 9786 #endif // !WIN32 || _LP64 9787 9788 void MacroAssembler::check_stack_alignment(Register sp, const char* msg, unsigned bias, Register tmp) { 9789 Label L_stack_ok; 9790 if (bias == 0) { 9791 testptr(sp, 2 * wordSize - 1); 9792 } else { 9793 // lea(tmp, Address(rsp, bias); 9794 mov(tmp, sp); 9795 addptr(tmp, bias); 9796 testptr(tmp, 2 * wordSize - 1); 9797 } 9798 jcc(Assembler::equal, L_stack_ok); 9799 block_comment(msg); 9800 stop(msg); 9801 bind(L_stack_ok); 9802 } 9803 9804 // Implements fast-locking. 9805 // Branches to slow upon failure to lock the object, with ZF cleared. 9806 // Falls through upon success with unspecified ZF. 9807 // 9808 // obj: the object to be locked 9809 // hdr: the (pre-loaded) header of the object, must be rax 9810 // thread: the thread which attempts to lock obj 9811 // tmp: a temporary register 9812 void MacroAssembler::fast_lock_impl(Register obj, Register hdr, Register thread, Register tmp, Label& slow) { 9813 assert(hdr == rax, "header must be in rax for cmpxchg"); 9814 assert_different_registers(obj, hdr, thread, tmp); 9815 9816 // First we need to check if the lock-stack has room for pushing the object reference. 9817 // Note: we subtract 1 from the end-offset so that we can do a 'greater' comparison, instead 9818 // of 'greaterEqual' below, which readily clears the ZF. This makes C2 code a little simpler and 9819 // avoids one branch. 9820 cmpl(Address(thread, JavaThread::lock_stack_top_offset()), LockStack::end_offset() - 1); 9821 jcc(Assembler::greater, slow); 9822 9823 // Now we attempt to take the fast-lock. 9824 // Clear lock_mask bits (locked state). 9825 andptr(hdr, ~(int32_t)markWord::lock_mask_in_place); 9826 movptr(tmp, hdr); 9827 // Set unlocked_value bit. 9828 orptr(hdr, markWord::unlocked_value); 9829 lock(); 9830 cmpxchgptr(tmp, Address(obj, oopDesc::mark_offset_in_bytes())); 9831 jcc(Assembler::notEqual, slow); 9832 9833 // If successful, push object to lock-stack. 9834 movl(tmp, Address(thread, JavaThread::lock_stack_top_offset())); 9835 movptr(Address(thread, tmp), obj); 9836 incrementl(tmp, oopSize); 9837 movl(Address(thread, JavaThread::lock_stack_top_offset()), tmp); 9838 } 9839 9840 // Implements fast-unlocking. 9841 // Branches to slow upon failure, with ZF cleared. 9842 // Falls through upon success, with unspecified ZF. 9843 // 9844 // obj: the object to be unlocked 9845 // hdr: the (pre-loaded) header of the object, must be rax 9846 // tmp: a temporary register 9847 void MacroAssembler::fast_unlock_impl(Register obj, Register hdr, Register tmp, Label& slow) { 9848 assert(hdr == rax, "header must be in rax for cmpxchg"); 9849 assert_different_registers(obj, hdr, tmp); 9850 9851 // Mark-word must be lock_mask now, try to swing it back to unlocked_value. 9852 movptr(tmp, hdr); // The expected old value 9853 orptr(tmp, markWord::unlocked_value); 9854 lock(); 9855 cmpxchgptr(tmp, Address(obj, oopDesc::mark_offset_in_bytes())); 9856 jcc(Assembler::notEqual, slow); 9857 // Pop the lock object from the lock-stack. 9858 #ifdef _LP64 9859 const Register thread = r15_thread; 9860 #else 9861 const Register thread = rax; 9862 get_thread(thread); 9863 #endif 9864 subl(Address(thread, JavaThread::lock_stack_top_offset()), oopSize); 9865 #ifdef ASSERT 9866 movl(tmp, Address(thread, JavaThread::lock_stack_top_offset())); 9867 movptr(Address(thread, tmp), 0); 9868 #endif 9869 }