1 /*
2 * Copyright (c) 1997, 2023, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #ifndef CPU_X86_VM_VERSION_X86_HPP
26 #define CPU_X86_VM_VERSION_X86_HPP
27
28 #include "runtime/abstract_vm_version.hpp"
29 #include "utilities/macros.hpp"
30 #include "utilities/sizes.hpp"
31
32 class VM_Version : public Abstract_VM_Version {
33 friend class VMStructs;
34 friend class JVMCIVMStructs;
35
36 public:
37 // cpuid result register layouts. These are all unions of a uint32_t
38 // (in case anyone wants access to the register as a whole) and a bitfield.
39
40 union StdCpuid1Eax {
41 uint32_t value;
42 struct {
43 uint32_t stepping : 4,
44 model : 4,
45 family : 4,
46 proc_type : 2,
47 : 2,
48 ext_model : 4,
49 ext_family : 8,
50 : 4;
51 } bits;
52 };
53
54 union StdCpuid1Ebx { // example, unused
55 uint32_t value;
56 struct {
57 uint32_t brand_id : 8,
58 clflush_size : 8,
59 threads_per_cpu : 8,
60 apic_id : 8;
61 } bits;
62 };
63
64 union StdCpuid1Ecx {
65 uint32_t value;
66 struct {
67 uint32_t sse3 : 1,
68 clmul : 1,
69 : 1,
70 monitor : 1,
71 : 1,
72 vmx : 1,
73 : 1,
74 est : 1,
75 : 1,
76 ssse3 : 1,
77 cid : 1,
78 : 1,
79 fma : 1,
80 cmpxchg16: 1,
81 : 4,
82 dca : 1,
83 sse4_1 : 1,
84 sse4_2 : 1,
85 : 2,
86 popcnt : 1,
87 : 1,
88 aes : 1,
89 : 1,
90 osxsave : 1,
91 avx : 1,
92 f16c : 1,
93 : 1,
94 hv : 1;
95 } bits;
96 };
97
98 union StdCpuid1Edx {
99 uint32_t value;
100 struct {
101 uint32_t : 4,
102 tsc : 1,
103 : 3,
104 cmpxchg8 : 1,
105 : 6,
106 cmov : 1,
107 : 3,
108 clflush : 1,
109 : 3,
110 mmx : 1,
111 fxsr : 1,
112 sse : 1,
113 sse2 : 1,
114 : 1,
115 ht : 1,
116 : 3;
117 } bits;
118 };
119
120 union DcpCpuid4Eax {
121 uint32_t value;
122 struct {
123 uint32_t cache_type : 5,
124 : 21,
125 cores_per_cpu : 6;
126 } bits;
127 };
128
129 union DcpCpuid4Ebx {
130 uint32_t value;
131 struct {
132 uint32_t L1_line_size : 12,
133 partitions : 10,
134 associativity : 10;
135 } bits;
136 };
137
138 union TplCpuidBEbx {
139 uint32_t value;
140 struct {
141 uint32_t logical_cpus : 16,
142 : 16;
143 } bits;
144 };
145
146 union ExtCpuid1Ecx {
147 uint32_t value;
148 struct {
149 uint32_t LahfSahf : 1,
150 CmpLegacy : 1,
151 : 3,
152 lzcnt : 1,
153 sse4a : 1,
154 misalignsse : 1,
155 prefetchw : 1,
156 : 23;
157 } bits;
158 };
159
160 union ExtCpuid1Edx {
161 uint32_t value;
162 struct {
163 uint32_t : 22,
164 mmx_amd : 1,
165 mmx : 1,
166 fxsr : 1,
167 fxsr_opt : 1,
168 pdpe1gb : 1,
169 rdtscp : 1,
170 : 1,
171 long_mode : 1,
172 tdnow2 : 1,
173 tdnow : 1;
174 } bits;
175 };
176
177 union ExtCpuid5Ex {
178 uint32_t value;
179 struct {
180 uint32_t L1_line_size : 8,
181 L1_tag_lines : 8,
182 L1_assoc : 8,
183 L1_size : 8;
184 } bits;
185 };
186
187 union ExtCpuid7Edx {
188 uint32_t value;
189 struct {
190 uint32_t : 8,
191 tsc_invariance : 1,
192 : 23;
193 } bits;
194 };
195
196 union ExtCpuid8Ecx {
197 uint32_t value;
198 struct {
199 uint32_t cores_per_cpu : 8,
200 : 24;
201 } bits;
202 };
203
204 union SefCpuid7Eax {
205 uint32_t value;
206 };
207
208 union SefCpuid7Ebx {
209 uint32_t value;
210 struct {
211 uint32_t fsgsbase : 1,
212 : 2,
213 bmi1 : 1,
214 : 1,
215 avx2 : 1,
216 : 2,
217 bmi2 : 1,
218 erms : 1,
219 : 1,
220 rtm : 1,
221 : 4,
222 avx512f : 1,
223 avx512dq : 1,
224 : 1,
225 adx : 1,
226 : 1,
227 avx512ifma : 1,
228 : 1,
229 clflushopt : 1,
230 clwb : 1,
231 : 1,
232 avx512pf : 1,
233 avx512er : 1,
234 avx512cd : 1,
235 sha : 1,
236 avx512bw : 1,
237 avx512vl : 1;
238 } bits;
239 };
240
241 union SefCpuid7Ecx {
242 uint32_t value;
243 struct {
244 uint32_t prefetchwt1 : 1,
245 avx512_vbmi : 1,
246 umip : 1,
247 pku : 1,
248 ospke : 1,
249 : 1,
250 avx512_vbmi2 : 1,
251 cet_ss : 1,
252 gfni : 1,
253 vaes : 1,
254 avx512_vpclmulqdq : 1,
255 avx512_vnni : 1,
256 avx512_bitalg : 1,
257 : 1,
258 avx512_vpopcntdq : 1,
259 : 1,
260 : 1,
261 mawau : 5,
262 rdpid : 1,
263 : 9;
264 } bits;
265 };
266
267 union SefCpuid7Edx {
268 uint32_t value;
269 struct {
270 uint32_t : 2,
271 avx512_4vnniw : 1,
272 avx512_4fmaps : 1,
273 fast_short_rep_mov : 1,
274 : 9,
275 serialize : 1,
276 : 5,
277 cet_ibt : 1,
278 : 11;
279 } bits;
280 };
281
282 union ExtCpuid1EEbx {
283 uint32_t value;
284 struct {
285 uint32_t : 8,
286 threads_per_core : 8,
287 : 16;
288 } bits;
289 };
290
291 union XemXcr0Eax {
292 uint32_t value;
293 struct {
294 uint32_t x87 : 1,
295 sse : 1,
296 ymm : 1,
297 bndregs : 1,
298 bndcsr : 1,
299 opmask : 1,
300 zmm512 : 1,
301 zmm32 : 1,
302 : 24;
303 } bits;
304 };
305
306 protected:
307 static int _cpu;
308 static int _model;
309 static int _stepping;
310
311 static bool _has_intel_jcc_erratum;
312
313 static address _cpuinfo_segv_addr; // address of instruction which causes SEGV
314 static address _cpuinfo_cont_addr; // address of instruction after the one which causes SEGV
315
316 /*
317 * Update following files when declaring new flags:
318 * test/lib-test/jdk/test/whitebox/CPUInfoTest.java
319 * src/jdk.internal.vm.ci/share/classes/jdk.vm.ci.amd64/src/jdk/vm/ci/amd64/AMD64.java
320 */
321 enum Feature_Flag : uint64_t {
322 #define CPU_FEATURE_FLAGS(decl) \
323 decl(CX8, "cx8", 0) /* next bits are from cpuid 1 (EDX) */ \
324 decl(CMOV, "cmov", 1) \
325 decl(FXSR, "fxsr", 2) \
326 decl(HT, "ht", 3) \
327 \
328 decl(MMX, "mmx", 4) \
329 decl(3DNOW_PREFETCH, "3dnowpref", 5) /* Processor supports 3dnow prefetch and prefetchw instructions */ \
330 /* may not necessarily support other 3dnow instructions */ \
331 decl(SSE, "sse", 6) \
332 decl(SSE2, "sse2", 7) \
333 \
334 decl(SSE3, "sse3", 8 ) /* SSE3 comes from cpuid 1 (ECX) */ \
335 decl(SSSE3, "ssse3", 9 ) \
336 decl(SSE4A, "sse4a", 10) \
337 decl(SSE4_1, "sse4.1", 11) \
338 \
339 decl(SSE4_2, "sse4.2", 12) \
340 decl(POPCNT, "popcnt", 13) \
341 decl(LZCNT, "lzcnt", 14) \
342 decl(TSC, "tsc", 15) \
343 \
344 decl(TSCINV_BIT, "tscinvbit", 16) \
345 decl(TSCINV, "tscinv", 17) \
346 decl(AVX, "avx", 18) \
347 decl(AVX2, "avx2", 19) \
348 \
349 decl(AES, "aes", 20) \
350 decl(ERMS, "erms", 21) /* enhanced 'rep movsb/stosb' instructions */ \
351 decl(CLMUL, "clmul", 22) /* carryless multiply for CRC */ \
352 decl(BMI1, "bmi1", 23) \
353 \
354 decl(BMI2, "bmi2", 24) \
355 decl(RTM, "rtm", 25) /* Restricted Transactional Memory instructions */ \
356 decl(ADX, "adx", 26) \
357 decl(AVX512F, "avx512f", 27) /* AVX 512bit foundation instructions */ \
358 \
359 decl(AVX512DQ, "avx512dq", 28) \
360 decl(AVX512PF, "avx512pf", 29) \
361 decl(AVX512ER, "avx512er", 30) \
362 decl(AVX512CD, "avx512cd", 31) \
363 \
364 decl(AVX512BW, "avx512bw", 32) /* Byte and word vector instructions */ \
365 decl(AVX512VL, "avx512vl", 33) /* EVEX instructions with smaller vector length */ \
366 decl(SHA, "sha", 34) /* SHA instructions */ \
367 decl(FMA, "fma", 35) /* FMA instructions */ \
368 \
369 decl(VZEROUPPER, "vzeroupper", 36) /* Vzeroupper instruction */ \
370 decl(AVX512_VPOPCNTDQ, "avx512_vpopcntdq", 37) /* Vector popcount */ \
371 decl(AVX512_VPCLMULQDQ, "avx512_vpclmulqdq", 38) /* Vector carryless multiplication */ \
372 decl(AVX512_VAES, "avx512_vaes", 39) /* Vector AES instruction */ \
373 \
374 decl(AVX512_VNNI, "avx512_vnni", 40) /* Vector Neural Network Instructions */ \
375 decl(FLUSH, "clflush", 41) /* flush instruction */ \
376 decl(FLUSHOPT, "clflushopt", 42) /* flusopth instruction */ \
377 decl(CLWB, "clwb", 43) /* clwb instruction */ \
378 \
379 decl(AVX512_VBMI2, "avx512_vbmi2", 44) /* VBMI2 shift left double instructions */ \
380 decl(AVX512_VBMI, "avx512_vbmi", 45) /* Vector BMI instructions */ \
381 decl(HV, "hv", 46) /* Hypervisor instructions */ \
382 decl(SERIALIZE, "serialize", 47) /* CPU SERIALIZE */ \
383 decl(RDTSCP, "rdtscp", 48) /* RDTSCP instruction */ \
384 decl(RDPID, "rdpid", 49) /* RDPID instruction */ \
385 decl(FSRM, "fsrm", 50) /* Fast Short REP MOV */ \
386 decl(GFNI, "gfni", 51) /* Vector GFNI instructions */ \
387 decl(AVX512_BITALG, "avx512_bitalg", 52) /* Vector sub-word popcount and bit gather instructions */\
388 decl(F16C, "f16c", 53) /* Half-precision and single precision FP conversion instructions*/ \
389 decl(PKU, "pku", 54) /* Protection keys for user-mode pages */ \
390 decl(OSPKE, "ospke", 55) /* OS enables protection keys */ \
391 decl(CET_IBT, "cet_ibt", 56) /* Control Flow Enforcement - Indirect Branch Tracking */ \
392 decl(CET_SS, "cet_ss", 57) /* Control Flow Enforcement - Shadow Stack */ \
393 decl(AVX512_IFMA, "avx512_ifma", 58) /* Integer Vector FMA instructions*/
394
395 #define DECLARE_CPU_FEATURE_FLAG(id, name, bit) CPU_##id = (1ULL << bit),
396 CPU_FEATURE_FLAGS(DECLARE_CPU_FEATURE_FLAG)
397 #undef DECLARE_CPU_FEATURE_FLAG
398 };
399
400 static const char* _features_names[];
401
402 enum Extended_Family {
403 // AMD
404 CPU_FAMILY_AMD_11H = 0x11,
405 // ZX
406 CPU_FAMILY_ZX_CORE_F6 = 6,
407 CPU_FAMILY_ZX_CORE_F7 = 7,
408 // Intel
409 CPU_FAMILY_INTEL_CORE = 6,
410 CPU_MODEL_NEHALEM = 0x1e,
411 CPU_MODEL_NEHALEM_EP = 0x1a,
412 CPU_MODEL_NEHALEM_EX = 0x2e,
413 CPU_MODEL_WESTMERE = 0x25,
414 CPU_MODEL_WESTMERE_EP = 0x2c,
415 CPU_MODEL_WESTMERE_EX = 0x2f,
416 CPU_MODEL_SANDYBRIDGE = 0x2a,
417 CPU_MODEL_SANDYBRIDGE_EP = 0x2d,
418 CPU_MODEL_IVYBRIDGE_EP = 0x3a,
419 CPU_MODEL_HASWELL_E3 = 0x3c,
420 CPU_MODEL_HASWELL_E7 = 0x3f,
421 CPU_MODEL_BROADWELL = 0x3d,
422 CPU_MODEL_SKYLAKE = 0x55
423 };
424
425 // cpuid information block. All info derived from executing cpuid with
426 // various function numbers is stored here. Intel and AMD info is
427 // merged in this block: accessor methods disentangle it.
428 //
429 // The info block is laid out in subblocks of 4 dwords corresponding to
430 // eax, ebx, ecx and edx, whether or not they contain anything useful.
431 struct CpuidInfo {
432 // cpuid function 0
433 uint32_t std_max_function;
434 uint32_t std_vendor_name_0;
435 uint32_t std_vendor_name_1;
436 uint32_t std_vendor_name_2;
437
438 // cpuid function 1
439 StdCpuid1Eax std_cpuid1_eax;
440 StdCpuid1Ebx std_cpuid1_ebx;
441 StdCpuid1Ecx std_cpuid1_ecx;
442 StdCpuid1Edx std_cpuid1_edx;
443
444 // cpuid function 4 (deterministic cache parameters)
445 DcpCpuid4Eax dcp_cpuid4_eax;
446 DcpCpuid4Ebx dcp_cpuid4_ebx;
447 uint32_t dcp_cpuid4_ecx; // unused currently
448 uint32_t dcp_cpuid4_edx; // unused currently
449
450 // cpuid function 7 (structured extended features)
451 SefCpuid7Eax sef_cpuid7_eax;
452 SefCpuid7Ebx sef_cpuid7_ebx;
453 SefCpuid7Ecx sef_cpuid7_ecx;
454 SefCpuid7Edx sef_cpuid7_edx;
455
456 // cpuid function 0xB (processor topology)
457 // ecx = 0
458 uint32_t tpl_cpuidB0_eax;
459 TplCpuidBEbx tpl_cpuidB0_ebx;
460 uint32_t tpl_cpuidB0_ecx; // unused currently
461 uint32_t tpl_cpuidB0_edx; // unused currently
462
463 // ecx = 1
464 uint32_t tpl_cpuidB1_eax;
465 TplCpuidBEbx tpl_cpuidB1_ebx;
466 uint32_t tpl_cpuidB1_ecx; // unused currently
467 uint32_t tpl_cpuidB1_edx; // unused currently
468
469 // ecx = 2
470 uint32_t tpl_cpuidB2_eax;
471 TplCpuidBEbx tpl_cpuidB2_ebx;
472 uint32_t tpl_cpuidB2_ecx; // unused currently
473 uint32_t tpl_cpuidB2_edx; // unused currently
474
475 // cpuid function 0x80000000 // example, unused
476 uint32_t ext_max_function;
477 uint32_t ext_vendor_name_0;
478 uint32_t ext_vendor_name_1;
479 uint32_t ext_vendor_name_2;
480
481 // cpuid function 0x80000001
482 uint32_t ext_cpuid1_eax; // reserved
483 uint32_t ext_cpuid1_ebx; // reserved
484 ExtCpuid1Ecx ext_cpuid1_ecx;
485 ExtCpuid1Edx ext_cpuid1_edx;
486
487 // cpuid functions 0x80000002 thru 0x80000004: example, unused
488 uint32_t proc_name_0, proc_name_1, proc_name_2, proc_name_3;
489 uint32_t proc_name_4, proc_name_5, proc_name_6, proc_name_7;
490 uint32_t proc_name_8, proc_name_9, proc_name_10,proc_name_11;
491
492 // cpuid function 0x80000005 // AMD L1, Intel reserved
493 uint32_t ext_cpuid5_eax; // unused currently
494 uint32_t ext_cpuid5_ebx; // reserved
495 ExtCpuid5Ex ext_cpuid5_ecx; // L1 data cache info (AMD)
496 ExtCpuid5Ex ext_cpuid5_edx; // L1 instruction cache info (AMD)
497
498 // cpuid function 0x80000007
499 uint32_t ext_cpuid7_eax; // reserved
500 uint32_t ext_cpuid7_ebx; // reserved
501 uint32_t ext_cpuid7_ecx; // reserved
502 ExtCpuid7Edx ext_cpuid7_edx; // tscinv
503
504 // cpuid function 0x80000008
505 uint32_t ext_cpuid8_eax; // unused currently
506 uint32_t ext_cpuid8_ebx; // reserved
507 ExtCpuid8Ecx ext_cpuid8_ecx;
508 uint32_t ext_cpuid8_edx; // reserved
509
510 // cpuid function 0x8000001E // AMD 17h
511 uint32_t ext_cpuid1E_eax;
512 ExtCpuid1EEbx ext_cpuid1E_ebx; // threads per core (AMD17h)
513 uint32_t ext_cpuid1E_ecx;
514 uint32_t ext_cpuid1E_edx; // unused currently
515
516 // extended control register XCR0 (the XFEATURE_ENABLED_MASK register)
517 XemXcr0Eax xem_xcr0_eax;
518 uint32_t xem_xcr0_edx; // reserved
519
520 // Space to save ymm registers after signal handle
521 int ymm_save[8*4]; // Save ymm0, ymm7, ymm8, ymm15
522
523 // Space to save zmm registers after signal handle
524 int zmm_save[16*4]; // Save zmm0, zmm7, zmm8, zmm31
525 };
526
527 private:
528 // The actual cpuid info block
529 static CpuidInfo _cpuid_info;
530
531 // Extractors and predicates
532 static uint32_t extended_cpu_family() {
533 uint32_t result = _cpuid_info.std_cpuid1_eax.bits.family;
534 result += _cpuid_info.std_cpuid1_eax.bits.ext_family;
535 return result;
536 }
537
538 static uint32_t extended_cpu_model() {
539 uint32_t result = _cpuid_info.std_cpuid1_eax.bits.model;
540 result |= _cpuid_info.std_cpuid1_eax.bits.ext_model << 4;
541 return result;
542 }
543
544 static uint32_t cpu_stepping() {
545 uint32_t result = _cpuid_info.std_cpuid1_eax.bits.stepping;
546 return result;
547 }
548
549 static uint logical_processor_count() {
550 uint result = threads_per_core();
551 return result;
552 }
553
554 static bool compute_has_intel_jcc_erratum();
555
556 static uint64_t feature_flags();
557 static bool os_supports_avx_vectors();
558 static void get_processor_features();
559
560 public:
561 // Offsets for cpuid asm stub
562 static ByteSize std_cpuid0_offset() { return byte_offset_of(CpuidInfo, std_max_function); }
563 static ByteSize std_cpuid1_offset() { return byte_offset_of(CpuidInfo, std_cpuid1_eax); }
564 static ByteSize dcp_cpuid4_offset() { return byte_offset_of(CpuidInfo, dcp_cpuid4_eax); }
565 static ByteSize sef_cpuid7_offset() { return byte_offset_of(CpuidInfo, sef_cpuid7_eax); }
566 static ByteSize ext_cpuid1_offset() { return byte_offset_of(CpuidInfo, ext_cpuid1_eax); }
567 static ByteSize ext_cpuid5_offset() { return byte_offset_of(CpuidInfo, ext_cpuid5_eax); }
568 static ByteSize ext_cpuid7_offset() { return byte_offset_of(CpuidInfo, ext_cpuid7_eax); }
569 static ByteSize ext_cpuid8_offset() { return byte_offset_of(CpuidInfo, ext_cpuid8_eax); }
570 static ByteSize ext_cpuid1E_offset() { return byte_offset_of(CpuidInfo, ext_cpuid1E_eax); }
571 static ByteSize tpl_cpuidB0_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB0_eax); }
572 static ByteSize tpl_cpuidB1_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB1_eax); }
573 static ByteSize tpl_cpuidB2_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB2_eax); }
574 static ByteSize xem_xcr0_offset() { return byte_offset_of(CpuidInfo, xem_xcr0_eax); }
575 static ByteSize ymm_save_offset() { return byte_offset_of(CpuidInfo, ymm_save); }
576 static ByteSize zmm_save_offset() { return byte_offset_of(CpuidInfo, zmm_save); }
577
578 // The value used to check ymm register after signal handle
579 static int ymm_test_value() { return 0xCAFEBABE; }
580
581 static void get_cpu_info_wrapper();
582 static void set_cpuinfo_segv_addr(address pc) { _cpuinfo_segv_addr = pc; }
583 static bool is_cpuinfo_segv_addr(address pc) { return _cpuinfo_segv_addr == pc; }
584 static void set_cpuinfo_cont_addr(address pc) { _cpuinfo_cont_addr = pc; }
585 static address cpuinfo_cont_addr() { return _cpuinfo_cont_addr; }
586
587 static void clean_cpuFeatures() { _features = 0; }
588 static void set_avx_cpuFeatures() { _features = (CPU_SSE | CPU_SSE2 | CPU_AVX | CPU_VZEROUPPER ); }
589 static void set_evex_cpuFeatures() { _features = (CPU_AVX512F | CPU_SSE | CPU_SSE2 | CPU_VZEROUPPER ); }
590
591 // Initialization
592 static void initialize();
593
594 // Override Abstract_VM_Version implementation
595 static void print_platform_virtualization_info(outputStream*);
596
597 // Asserts
598 static void assert_is_initialized() {
599 assert(_cpuid_info.std_cpuid1_eax.bits.family != 0, "VM_Version not initialized");
600 }
601
602 //
603 // Processor family:
604 // 3 - 386
605 // 4 - 486
606 // 5 - Pentium
607 // 6 - PentiumPro, Pentium II, Celeron, Xeon, Pentium III, Athlon,
608 // Pentium M, Core Solo, Core Duo, Core2 Duo
609 // family 6 model: 9, 13, 14, 15
610 // 0x0f - Pentium 4, Opteron
611 //
612 // Note: The cpu family should be used to select between
613 // instruction sequences which are valid on all Intel
614 // processors. Use the feature test functions below to
615 // determine whether a particular instruction is supported.
616 //
617 static int cpu_family() { return _cpu;}
618 static bool is_P6() { return cpu_family() >= 6; }
619 static bool is_amd() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x68747541; } // 'htuA'
620 static bool is_hygon() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x6F677948; } // 'ogyH'
621 static bool is_amd_family() { return is_amd() || is_hygon(); }
622 static bool is_intel() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x756e6547; } // 'uneG'
623 static bool is_zx() { assert_is_initialized(); return (_cpuid_info.std_vendor_name_0 == 0x746e6543) || (_cpuid_info.std_vendor_name_0 == 0x68532020); } // 'tneC'||'hS '
624 static bool is_atom_family() { return ((cpu_family() == 0x06) && ((extended_cpu_model() == 0x36) || (extended_cpu_model() == 0x37) || (extended_cpu_model() == 0x4D))); } //Silvermont and Centerton
625 static bool is_knights_family() { return UseKNLSetting || ((cpu_family() == 0x06) && ((extended_cpu_model() == 0x57) || (extended_cpu_model() == 0x85))); } // Xeon Phi 3200/5200/7200 and Future Xeon Phi
626
627 static bool supports_processor_topology() {
628 return (_cpuid_info.std_max_function >= 0xB) &&
629 // eax[4:0] | ebx[0:15] == 0 indicates invalid topology level.
630 // Some cpus have max cpuid >= 0xB but do not support processor topology.
631 (((_cpuid_info.tpl_cpuidB0_eax & 0x1f) | _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus) != 0);
632 }
633
634 static uint cores_per_cpu();
635 static uint threads_per_core();
636 static uint L1_line_size();
637
638 static uint prefetch_data_size() {
639 return L1_line_size();
640 }
641
642 //
643 // Feature identification
644 //
645 static bool supports_cpuid() { return _features != 0; }
646 static bool supports_cmpxchg8() { return (_features & CPU_CX8) != 0; }
647 static bool supports_cmov() { return (_features & CPU_CMOV) != 0; }
648 static bool supports_fxsr() { return (_features & CPU_FXSR) != 0; }
649 static bool supports_ht() { return (_features & CPU_HT) != 0; }
650 static bool supports_mmx() { return (_features & CPU_MMX) != 0; }
651 static bool supports_sse() { return (_features & CPU_SSE) != 0; }
652 static bool supports_sse2() { return (_features & CPU_SSE2) != 0; }
653 static bool supports_sse3() { return (_features & CPU_SSE3) != 0; }
654 static bool supports_ssse3() { return (_features & CPU_SSSE3)!= 0; }
655 static bool supports_sse4_1() { return (_features & CPU_SSE4_1) != 0; }
656 static bool supports_sse4_2() { return (_features & CPU_SSE4_2) != 0; }
657 static bool supports_popcnt() { return (_features & CPU_POPCNT) != 0; }
658 static bool supports_avx() { return (_features & CPU_AVX) != 0; }
659 static bool supports_avx2() { return (_features & CPU_AVX2) != 0; }
660 static bool supports_tsc() { return (_features & CPU_TSC) != 0; }
661 static bool supports_rdtscp() { return (_features & CPU_RDTSCP) != 0; }
662 static bool supports_rdpid() { return (_features & CPU_RDPID) != 0; }
663 static bool supports_aes() { return (_features & CPU_AES) != 0; }
664 static bool supports_erms() { return (_features & CPU_ERMS) != 0; }
665 static bool supports_fsrm() { return (_features & CPU_FSRM) != 0; }
666 static bool supports_clmul() { return (_features & CPU_CLMUL) != 0; }
667 static bool supports_rtm() { return (_features & CPU_RTM) != 0; }
668 static bool supports_bmi1() { return (_features & CPU_BMI1) != 0; }
669 static bool supports_bmi2() { return (_features & CPU_BMI2) != 0; }
670 static bool supports_adx() { return (_features & CPU_ADX) != 0; }
671 static bool supports_evex() { return (_features & CPU_AVX512F) != 0; }
672 static bool supports_avx512dq() { return (_features & CPU_AVX512DQ) != 0; }
673 static bool supports_avx512ifma() { return (_features & CPU_AVX512_IFMA) != 0; }
674 static bool supports_avx512pf() { return (_features & CPU_AVX512PF) != 0; }
675 static bool supports_avx512er() { return (_features & CPU_AVX512ER) != 0; }
676 static bool supports_avx512cd() { return (_features & CPU_AVX512CD) != 0; }
677 static bool supports_avx512bw() { return (_features & CPU_AVX512BW) != 0; }
678 static bool supports_avx512vl() { return (_features & CPU_AVX512VL) != 0; }
679 static bool supports_avx512vlbw() { return (supports_evex() && supports_avx512bw() && supports_avx512vl()); }
680 static bool supports_avx512bwdq() { return (supports_evex() && supports_avx512bw() && supports_avx512dq()); }
681 static bool supports_avx512vldq() { return (supports_evex() && supports_avx512dq() && supports_avx512vl()); }
682 static bool supports_avx512vlbwdq() { return (supports_evex() && supports_avx512vl() &&
683 supports_avx512bw() && supports_avx512dq()); }
684 static bool supports_avx512novl() { return (supports_evex() && !supports_avx512vl()); }
685 static bool supports_avx512nobw() { return (supports_evex() && !supports_avx512bw()); }
686 static bool supports_avx256only() { return (supports_avx2() && !supports_evex()); }
687 static bool supports_avxonly() { return ((supports_avx2() || supports_avx()) && !supports_evex()); }
688 static bool supports_sha() { return (_features & CPU_SHA) != 0; }
689 static bool supports_fma() { return (_features & CPU_FMA) != 0 && supports_avx(); }
690 static bool supports_vzeroupper() { return (_features & CPU_VZEROUPPER) != 0; }
691 static bool supports_avx512_vpopcntdq() { return (_features & CPU_AVX512_VPOPCNTDQ) != 0; }
692 static bool supports_avx512_vpclmulqdq() { return (_features & CPU_AVX512_VPCLMULQDQ) != 0; }
693 static bool supports_avx512_vaes() { return (_features & CPU_AVX512_VAES) != 0; }
694 static bool supports_gfni() { return (_features & CPU_GFNI) != 0; }
695 static bool supports_avx512_vnni() { return (_features & CPU_AVX512_VNNI) != 0; }
696 static bool supports_avx512_bitalg() { return (_features & CPU_AVX512_BITALG) != 0; }
697 static bool supports_avx512_vbmi() { return (_features & CPU_AVX512_VBMI) != 0; }
698 static bool supports_avx512_vbmi2() { return (_features & CPU_AVX512_VBMI2) != 0; }
699 static bool supports_hv() { return (_features & CPU_HV) != 0; }
700 static bool supports_serialize() { return (_features & CPU_SERIALIZE) != 0; }
701 static bool supports_f16c() { return (_features & CPU_F16C) != 0; }
702 static bool supports_pku() { return (_features & CPU_PKU) != 0; }
703 static bool supports_ospke() { return (_features & CPU_OSPKE) != 0; }
704 static bool supports_cet_ss() { return (_features & CPU_CET_SS) != 0; }
705 static bool supports_cet_ibt() { return (_features & CPU_CET_IBT) != 0; }
706
707 // Intel features
708 static bool is_intel_family_core() { return is_intel() &&
709 extended_cpu_family() == CPU_FAMILY_INTEL_CORE; }
710
711 static bool is_intel_skylake() { return is_intel_family_core() &&
712 extended_cpu_model() == CPU_MODEL_SKYLAKE; }
713
714 #ifdef COMPILER2
715 // Determine if it's running on Cascade Lake using default options.
716 static bool is_default_intel_cascade_lake();
717 #endif
718
719 static bool is_intel_cascade_lake();
720
721 static int avx3_threshold();
722
723 static bool is_intel_tsc_synched_at_init();
724
725 // This checks if the JVM is potentially affected by an erratum on Intel CPUs (SKX102)
726 // that causes unpredictable behaviour when jcc crosses 64 byte boundaries. Its microcode
727 // mitigation causes regressions when jumps or fused conditional branches cross or end at
728 // 32 byte boundaries.
729 static bool has_intel_jcc_erratum() { return _has_intel_jcc_erratum; }
730
731 // AMD features
732 static bool supports_3dnow_prefetch() { return (_features & CPU_3DNOW_PREFETCH) != 0; }
733 static bool supports_lzcnt() { return (_features & CPU_LZCNT) != 0; }
734 static bool supports_sse4a() { return (_features & CPU_SSE4A) != 0; }
735
736 static bool is_amd_Barcelona() { return is_amd() &&
737 extended_cpu_family() == CPU_FAMILY_AMD_11H; }
738
739 // Intel and AMD newer cores support fast timestamps well
740 static bool supports_tscinv_bit() {
741 return (_features & CPU_TSCINV_BIT) != 0;
742 }
743 static bool supports_tscinv() {
744 return (_features & CPU_TSCINV) != 0;
745 }
746
747 // Intel Core and newer cpus have fast IDIV instruction (excluding Atom).
748 static bool has_fast_idiv() { return is_intel() && cpu_family() == 6 &&
749 supports_sse3() && _model != 0x1C; }
750
751 static bool supports_compare_and_exchange() { return true; }
752
753 static intx allocate_prefetch_distance(bool use_watermark_prefetch);
754
755 // SSE2 and later processors implement a 'pause' instruction
756 // that can be used for efficient implementation of
757 // the intrinsic for java.lang.Thread.onSpinWait()
758 static bool supports_on_spin_wait() { return supports_sse2(); }
759
760 // x86_64 supports fast class initialization checks for static methods.
761 static bool supports_fast_class_init_checks() {
762 return LP64_ONLY(true) NOT_LP64(false); // not implemented on x86_32
763 }
764
765 constexpr static bool supports_stack_watermark_barrier() {
766 return true;
767 }
768
769 // For AVX CPUs only. f16c support is disabled if UseAVX == 0.
770 static bool supports_float16() {
771 return supports_f16c() || supports_avx512vl();
772 }
773
774 // Check intrinsic support
775 static bool is_intrinsic_supported(vmIntrinsicID id);
776
777 // there are several insns to force cache line sync to memory which
778 // we can use to ensure mapped non-volatile memory is up to date with
779 // pending in-cache changes.
780 //
781 // 64 bit cpus always support clflush which writes back and evicts
782 // on 32 bit cpus support is recorded via a feature flag
783 //
784 // clflushopt is optional and acts like clflush except it does
785 // not synchronize with other memory ops. it needs a preceding
786 // and trailing StoreStore fence
787 //
788 // clwb is an optional intel-specific instruction which
789 // writes back without evicting the line. it also does not
790 // synchronize with other memory ops. so, it needs preceding
791 // and trailing StoreStore fences.
792
793 #ifdef _LP64
794 static bool supports_clflush(); // Can't inline due to header file conflict
795 #else
796 static bool supports_clflush() { return ((_features & CPU_FLUSH) != 0); }
797 #endif // _LP64
798
799 // Note: CPU_FLUSHOPT and CPU_CLWB bits should always be zero for 32-bit
800 static bool supports_clflushopt() { return ((_features & CPU_FLUSHOPT) != 0); }
801 static bool supports_clwb() { return ((_features & CPU_CLWB) != 0); }
802
803 // Old CPUs perform lea on AGU which causes additional latency transferring the
804 // value from/to ALU for other operations
805 static bool supports_fast_2op_lea() {
806 return (is_intel() && supports_avx()) || // Sandy Bridge and above
807 (is_amd() && supports_avx()); // Jaguar and Bulldozer and above
808 }
809
810 // Pre Icelake Intels suffer inefficiency regarding 3-operand lea, which contains
811 // all of base register, index register and displacement immediate, with 3 latency.
812 // Note that when the address contains no displacement but the base register is
813 // rbp or r13, the machine code must contain a zero displacement immediate,
814 // effectively transform a 2-operand lea into a 3-operand lea. This can be
815 // replaced by add-add or lea-add
816 static bool supports_fast_3op_lea() {
817 return supports_fast_2op_lea() &&
818 ((is_intel() && supports_clwb() && !is_intel_skylake()) || // Icelake and above
819 is_amd());
820 }
821
822 #ifdef __APPLE__
823 // Is the CPU running emulated (for example macOS Rosetta running x86_64 code on M1 ARM (aarch64)
824 static bool is_cpu_emulated();
825 #endif
826
827 // support functions for virtualization detection
828 private:
829 static void check_virtualizations();
830
831 static const char* cpu_family_description(void);
832 static const char* cpu_model_description(void);
833 static const char* cpu_brand(void);
834 static const char* cpu_brand_string(void);
835
836 static int cpu_type_description(char* const buf, size_t buf_len);
837 static int cpu_detailed_description(char* const buf, size_t buf_len);
838 static int cpu_extended_brand_string(char* const buf, size_t buf_len);
839
840 static bool cpu_is_em64t(void);
841 static bool is_netburst(void);
842
843 // Returns bytes written excluding termninating null byte.
844 static size_t cpu_write_support_string(char* const buf, size_t buf_len);
845 static void resolve_cpu_information_details(void);
846 static int64_t max_qualified_cpu_freq_from_brand_string(void);
847
848 public:
849 // Offsets for cpuid asm stub brand string
850 static ByteSize proc_name_0_offset() { return byte_offset_of(CpuidInfo, proc_name_0); }
851 static ByteSize proc_name_1_offset() { return byte_offset_of(CpuidInfo, proc_name_1); }
852 static ByteSize proc_name_2_offset() { return byte_offset_of(CpuidInfo, proc_name_2); }
853 static ByteSize proc_name_3_offset() { return byte_offset_of(CpuidInfo, proc_name_3); }
854 static ByteSize proc_name_4_offset() { return byte_offset_of(CpuidInfo, proc_name_4); }
855 static ByteSize proc_name_5_offset() { return byte_offset_of(CpuidInfo, proc_name_5); }
856 static ByteSize proc_name_6_offset() { return byte_offset_of(CpuidInfo, proc_name_6); }
857 static ByteSize proc_name_7_offset() { return byte_offset_of(CpuidInfo, proc_name_7); }
858 static ByteSize proc_name_8_offset() { return byte_offset_of(CpuidInfo, proc_name_8); }
859 static ByteSize proc_name_9_offset() { return byte_offset_of(CpuidInfo, proc_name_9); }
860 static ByteSize proc_name_10_offset() { return byte_offset_of(CpuidInfo, proc_name_10); }
861 static ByteSize proc_name_11_offset() { return byte_offset_of(CpuidInfo, proc_name_11); }
862
863 static int64_t maximum_qualified_cpu_frequency(void);
864
865 static bool supports_tscinv_ext(void);
866
867 static void initialize_tsc();
868 static void initialize_cpu_information(void);
869 };
870
871 #endif // CPU_X86_VM_VERSION_X86_HPP