1 /*
  2  * Copyright (c) 1997, 2023, Oracle and/or its affiliates. All rights reserved.
  3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  4  *
  5  * This code is free software; you can redistribute it and/or modify it
  6  * under the terms of the GNU General Public License version 2 only, as
  7  * published by the Free Software Foundation.
  8  *
  9  * This code is distributed in the hope that it will be useful, but WITHOUT
 10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 12  * version 2 for more details (a copy is included in the LICENSE file that
 13  * accompanied this code).
 14  *
 15  * You should have received a copy of the GNU General Public License version
 16  * 2 along with this work; if not, write to the Free Software Foundation,
 17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
 18  *
 19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
 20  * or visit www.oracle.com if you need additional information or have any
 21  * questions.
 22  *

749                                            supports_sse3() && _model != 0x1C; }
750 
751   static bool supports_compare_and_exchange() { return true; }
752 
753   static intx allocate_prefetch_distance(bool use_watermark_prefetch);
754 
755   // SSE2 and later processors implement a 'pause' instruction
756   // that can be used for efficient implementation of
757   // the intrinsic for java.lang.Thread.onSpinWait()
758   static bool supports_on_spin_wait() { return supports_sse2(); }
759 
760   // x86_64 supports fast class initialization checks for static methods.
761   static bool supports_fast_class_init_checks() {
762     return LP64_ONLY(true) NOT_LP64(false); // not implemented on x86_32
763   }
764 
765   constexpr static bool supports_stack_watermark_barrier() {
766     return true;
767   }
768 




769   // For AVX CPUs only. f16c support is disabled if UseAVX == 0.
770   static bool supports_float16() {
771     return supports_f16c() || supports_avx512vl();
772   }
773 
774   // Check intrinsic support
775   static bool is_intrinsic_supported(vmIntrinsicID id);
776 
777   // there are several insns to force cache line sync to memory which
778   // we can use to ensure mapped non-volatile memory is up to date with
779   // pending in-cache changes.
780   //
781   // 64 bit cpus always support clflush which writes back and evicts
782   // on 32 bit cpus support is recorded via a feature flag
783   //
784   // clflushopt is optional and acts like clflush except it does
785   // not synchronize with other memory ops. it needs a preceding
786   // and trailing StoreStore fence
787   //
788   // clwb is an optional intel-specific instruction which

  1 /*
  2  * Copyright (c) 1997, 2024, Oracle and/or its affiliates. All rights reserved.
  3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  4  *
  5  * This code is free software; you can redistribute it and/or modify it
  6  * under the terms of the GNU General Public License version 2 only, as
  7  * published by the Free Software Foundation.
  8  *
  9  * This code is distributed in the hope that it will be useful, but WITHOUT
 10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 12  * version 2 for more details (a copy is included in the LICENSE file that
 13  * accompanied this code).
 14  *
 15  * You should have received a copy of the GNU General Public License version
 16  * 2 along with this work; if not, write to the Free Software Foundation,
 17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
 18  *
 19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
 20  * or visit www.oracle.com if you need additional information or have any
 21  * questions.
 22  *

749                                            supports_sse3() && _model != 0x1C; }
750 
751   static bool supports_compare_and_exchange() { return true; }
752 
753   static intx allocate_prefetch_distance(bool use_watermark_prefetch);
754 
755   // SSE2 and later processors implement a 'pause' instruction
756   // that can be used for efficient implementation of
757   // the intrinsic for java.lang.Thread.onSpinWait()
758   static bool supports_on_spin_wait() { return supports_sse2(); }
759 
760   // x86_64 supports fast class initialization checks for static methods.
761   static bool supports_fast_class_init_checks() {
762     return LP64_ONLY(true) NOT_LP64(false); // not implemented on x86_32
763   }
764 
765   constexpr static bool supports_stack_watermark_barrier() {
766     return true;
767   }
768 
769   constexpr static bool supports_recursive_lightweight_locking() {
770     return true;
771   }
772 
773   // For AVX CPUs only. f16c support is disabled if UseAVX == 0.
774   static bool supports_float16() {
775     return supports_f16c() || supports_avx512vl();
776   }
777 
778   // Check intrinsic support
779   static bool is_intrinsic_supported(vmIntrinsicID id);
780 
781   // there are several insns to force cache line sync to memory which
782   // we can use to ensure mapped non-volatile memory is up to date with
783   // pending in-cache changes.
784   //
785   // 64 bit cpus always support clflush which writes back and evicts
786   // on 32 bit cpus support is recorded via a feature flag
787   //
788   // clflushopt is optional and acts like clflush except it does
789   // not synchronize with other memory ops. it needs a preceding
790   // and trailing StoreStore fence
791   //
792   // clwb is an optional intel-specific instruction which