1 /* 2 * Copyright (c) 2000, 2022, Oracle and/or its affiliates. All rights reserved. 3 * Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved. 4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 5 * 6 * This code is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 only, as 8 * published by the Free Software Foundation. 9 * 10 * This code is distributed in the hope that it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 13 * version 2 for more details (a copy is included in the LICENSE file that 14 * accompanied this code). 15 * 16 * You should have received a copy of the GNU General Public License version 17 * 2 along with this work; if not, write to the Free Software Foundation, 18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 19 * 20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 21 * or visit www.oracle.com if you need additional information or have any 22 * questions. 23 * 24 */ 25 26 #include "precompiled.hpp" 27 #include "asm/macroAssembler.inline.hpp" 28 #include "asm/assembler.hpp" 29 #include "c1/c1_CodeStubs.hpp" 30 #include "c1/c1_Compilation.hpp" 31 #include "c1/c1_LIRAssembler.hpp" 32 #include "c1/c1_MacroAssembler.hpp" 33 #include "c1/c1_Runtime1.hpp" 34 #include "c1/c1_ValueStack.hpp" 35 #include "ci/ciArrayKlass.hpp" 36 #include "ci/ciInstance.hpp" 37 #include "code/compiledIC.hpp" 38 #include "gc/shared/collectedHeap.hpp" 39 #include "gc/shared/gc_globals.hpp" 40 #include "nativeInst_aarch64.hpp" 41 #include "oops/objArrayKlass.hpp" 42 #include "runtime/frame.inline.hpp" 43 #include "runtime/sharedRuntime.hpp" 44 #include "runtime/stubRoutines.hpp" 45 #include "utilities/powerOfTwo.hpp" 46 #include "vmreg_aarch64.inline.hpp" 47 48 49 #ifndef PRODUCT 50 #define COMMENT(x) do { __ block_comment(x); } while (0) 51 #else 52 #define COMMENT(x) 53 #endif 54 55 NEEDS_CLEANUP // remove this definitions ? 56 const Register IC_Klass = rscratch2; // where the IC klass is cached 57 const Register SYNC_header = r0; // synchronization header 58 const Register SHIFT_count = r0; // where count for shift operations must be 59 60 #define __ _masm-> 61 62 63 static void select_different_registers(Register preserve, 64 Register extra, 65 Register &tmp1, 66 Register &tmp2) { 67 if (tmp1 == preserve) { 68 assert_different_registers(tmp1, tmp2, extra); 69 tmp1 = extra; 70 } else if (tmp2 == preserve) { 71 assert_different_registers(tmp1, tmp2, extra); 72 tmp2 = extra; 73 } 74 assert_different_registers(preserve, tmp1, tmp2); 75 } 76 77 78 79 static void select_different_registers(Register preserve, 80 Register extra, 81 Register &tmp1, 82 Register &tmp2, 83 Register &tmp3) { 84 if (tmp1 == preserve) { 85 assert_different_registers(tmp1, tmp2, tmp3, extra); 86 tmp1 = extra; 87 } else if (tmp2 == preserve) { 88 assert_different_registers(tmp1, tmp2, tmp3, extra); 89 tmp2 = extra; 90 } else if (tmp3 == preserve) { 91 assert_different_registers(tmp1, tmp2, tmp3, extra); 92 tmp3 = extra; 93 } 94 assert_different_registers(preserve, tmp1, tmp2, tmp3); 95 } 96 97 98 bool LIR_Assembler::is_small_constant(LIR_Opr opr) { Unimplemented(); return false; } 99 100 101 LIR_Opr LIR_Assembler::receiverOpr() { 102 return FrameMap::receiver_opr; 103 } 104 105 LIR_Opr LIR_Assembler::osrBufferPointer() { 106 return FrameMap::as_pointer_opr(receiverOpr()->as_register()); 107 } 108 109 //--------------fpu register translations----------------------- 110 111 112 address LIR_Assembler::float_constant(float f) { 113 address const_addr = __ float_constant(f); 114 if (const_addr == NULL) { 115 bailout("const section overflow"); 116 return __ code()->consts()->start(); 117 } else { 118 return const_addr; 119 } 120 } 121 122 123 address LIR_Assembler::double_constant(double d) { 124 address const_addr = __ double_constant(d); 125 if (const_addr == NULL) { 126 bailout("const section overflow"); 127 return __ code()->consts()->start(); 128 } else { 129 return const_addr; 130 } 131 } 132 133 address LIR_Assembler::int_constant(jlong n) { 134 address const_addr = __ long_constant(n); 135 if (const_addr == NULL) { 136 bailout("const section overflow"); 137 return __ code()->consts()->start(); 138 } else { 139 return const_addr; 140 } 141 } 142 143 void LIR_Assembler::breakpoint() { Unimplemented(); } 144 145 void LIR_Assembler::push(LIR_Opr opr) { Unimplemented(); } 146 147 void LIR_Assembler::pop(LIR_Opr opr) { Unimplemented(); } 148 149 bool LIR_Assembler::is_literal_address(LIR_Address* addr) { Unimplemented(); return false; } 150 //------------------------------------------- 151 152 static Register as_reg(LIR_Opr op) { 153 return op->is_double_cpu() ? op->as_register_lo() : op->as_register(); 154 } 155 156 static jlong as_long(LIR_Opr data) { 157 jlong result; 158 switch (data->type()) { 159 case T_INT: 160 result = (data->as_jint()); 161 break; 162 case T_LONG: 163 result = (data->as_jlong()); 164 break; 165 default: 166 ShouldNotReachHere(); 167 result = 0; // unreachable 168 } 169 return result; 170 } 171 172 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) { 173 Register base = addr->base()->as_pointer_register(); 174 LIR_Opr opr = addr->index(); 175 if (opr->is_cpu_register()) { 176 Register index; 177 if (opr->is_single_cpu()) 178 index = opr->as_register(); 179 else 180 index = opr->as_register_lo(); 181 assert(addr->disp() == 0, "must be"); 182 switch(opr->type()) { 183 case T_INT: 184 return Address(base, index, Address::sxtw(addr->scale())); 185 case T_LONG: 186 return Address(base, index, Address::lsl(addr->scale())); 187 default: 188 ShouldNotReachHere(); 189 } 190 } else { 191 assert(addr->scale() == 0, 192 "expected for immediate operand, was: %d", addr->scale()); 193 ptrdiff_t offset = ptrdiff_t(addr->disp()); 194 // NOTE: Does not handle any 16 byte vector access. 195 const uint type_size = type2aelembytes(addr->type(), true); 196 return __ legitimize_address(Address(base, offset), type_size, tmp); 197 } 198 return Address(); 199 } 200 201 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) { 202 ShouldNotReachHere(); 203 return Address(); 204 } 205 206 Address LIR_Assembler::as_Address(LIR_Address* addr) { 207 return as_Address(addr, rscratch1); 208 } 209 210 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) { 211 return as_Address(addr, rscratch1); // Ouch 212 // FIXME: This needs to be much more clever. See x86. 213 } 214 215 // Ensure a valid Address (base + offset) to a stack-slot. If stack access is 216 // not encodable as a base + (immediate) offset, generate an explicit address 217 // calculation to hold the address in a temporary register. 218 Address LIR_Assembler::stack_slot_address(int index, uint size, Register tmp, int adjust) { 219 precond(size == 4 || size == 8); 220 Address addr = frame_map()->address_for_slot(index, adjust); 221 precond(addr.getMode() == Address::base_plus_offset); 222 precond(addr.base() == sp); 223 precond(addr.offset() > 0); 224 uint mask = size - 1; 225 assert((addr.offset() & mask) == 0, "scaled offsets only"); 226 return __ legitimize_address(addr, size, tmp); 227 } 228 229 void LIR_Assembler::osr_entry() { 230 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset()); 231 BlockBegin* osr_entry = compilation()->hir()->osr_entry(); 232 ValueStack* entry_state = osr_entry->state(); 233 int number_of_locks = entry_state->locks_size(); 234 235 // we jump here if osr happens with the interpreter 236 // state set up to continue at the beginning of the 237 // loop that triggered osr - in particular, we have 238 // the following registers setup: 239 // 240 // r2: osr buffer 241 // 242 243 // build frame 244 ciMethod* m = compilation()->method(); 245 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes()); 246 247 // OSR buffer is 248 // 249 // locals[nlocals-1..0] 250 // monitors[0..number_of_locks] 251 // 252 // locals is a direct copy of the interpreter frame so in the osr buffer 253 // so first slot in the local array is the last local from the interpreter 254 // and last slot is local[0] (receiver) from the interpreter 255 // 256 // Similarly with locks. The first lock slot in the osr buffer is the nth lock 257 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock 258 // in the interpreter frame (the method lock if a sync method) 259 260 // Initialize monitors in the compiled activation. 261 // r2: pointer to osr buffer 262 // 263 // All other registers are dead at this point and the locals will be 264 // copied into place by code emitted in the IR. 265 266 Register OSR_buf = osrBufferPointer()->as_pointer_register(); 267 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below"); 268 int monitor_offset = BytesPerWord * method()->max_locals() + 269 (2 * BytesPerWord) * (number_of_locks - 1); 270 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in 271 // the OSR buffer using 2 word entries: first the lock and then 272 // the oop. 273 for (int i = 0; i < number_of_locks; i++) { 274 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord); 275 #ifdef ASSERT 276 // verify the interpreter's monitor has a non-null object 277 { 278 Label L; 279 __ ldr(rscratch1, Address(OSR_buf, slot_offset + 1*BytesPerWord)); 280 __ cbnz(rscratch1, L); 281 __ stop("locked object is NULL"); 282 __ bind(L); 283 } 284 #endif 285 __ ldp(r19, r20, Address(OSR_buf, slot_offset)); 286 __ str(r19, frame_map()->address_for_monitor_lock(i)); 287 __ str(r20, frame_map()->address_for_monitor_object(i)); 288 } 289 } 290 } 291 292 293 // inline cache check; done before the frame is built. 294 int LIR_Assembler::check_icache() { 295 Register receiver = FrameMap::receiver_opr->as_register(); 296 Register ic_klass = IC_Klass; 297 int start_offset = __ offset(); 298 __ inline_cache_check(receiver, ic_klass); 299 300 // if icache check fails, then jump to runtime routine 301 // Note: RECEIVER must still contain the receiver! 302 Label dont; 303 __ br(Assembler::EQ, dont); 304 __ far_jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub())); 305 306 // We align the verified entry point unless the method body 307 // (including its inline cache check) will fit in a single 64-byte 308 // icache line. 309 if (! method()->is_accessor() || __ offset() - start_offset > 4 * 4) { 310 // force alignment after the cache check. 311 __ align(CodeEntryAlignment); 312 } 313 314 __ bind(dont); 315 return start_offset; 316 } 317 318 void LIR_Assembler::clinit_barrier(ciMethod* method) { 319 assert(VM_Version::supports_fast_class_init_checks(), "sanity"); 320 assert(!method->holder()->is_not_initialized(), "initialization should have been started"); 321 322 Label L_skip_barrier; 323 324 __ mov_metadata(rscratch2, method->holder()->constant_encoding()); 325 __ clinit_barrier(rscratch2, rscratch1, &L_skip_barrier /*L_fast_path*/); 326 __ far_jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub())); 327 __ bind(L_skip_barrier); 328 } 329 330 void LIR_Assembler::jobject2reg(jobject o, Register reg) { 331 if (o == NULL) { 332 __ mov(reg, zr); 333 } else { 334 __ movoop(reg, o); 335 } 336 } 337 338 void LIR_Assembler::deoptimize_trap(CodeEmitInfo *info) { 339 address target = NULL; 340 relocInfo::relocType reloc_type = relocInfo::none; 341 342 switch (patching_id(info)) { 343 case PatchingStub::access_field_id: 344 target = Runtime1::entry_for(Runtime1::access_field_patching_id); 345 reloc_type = relocInfo::section_word_type; 346 break; 347 case PatchingStub::load_klass_id: 348 target = Runtime1::entry_for(Runtime1::load_klass_patching_id); 349 reloc_type = relocInfo::metadata_type; 350 break; 351 case PatchingStub::load_mirror_id: 352 target = Runtime1::entry_for(Runtime1::load_mirror_patching_id); 353 reloc_type = relocInfo::oop_type; 354 break; 355 case PatchingStub::load_appendix_id: 356 target = Runtime1::entry_for(Runtime1::load_appendix_patching_id); 357 reloc_type = relocInfo::oop_type; 358 break; 359 default: ShouldNotReachHere(); 360 } 361 362 __ far_call(RuntimeAddress(target)); 363 add_call_info_here(info); 364 } 365 366 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) { 367 deoptimize_trap(info); 368 } 369 370 371 // This specifies the rsp decrement needed to build the frame 372 int LIR_Assembler::initial_frame_size_in_bytes() const { 373 // if rounding, must let FrameMap know! 374 375 return in_bytes(frame_map()->framesize_in_bytes()); 376 } 377 378 379 int LIR_Assembler::emit_exception_handler() { 380 // generate code for exception handler 381 address handler_base = __ start_a_stub(exception_handler_size()); 382 if (handler_base == NULL) { 383 // not enough space left for the handler 384 bailout("exception handler overflow"); 385 return -1; 386 } 387 388 int offset = code_offset(); 389 390 // the exception oop and pc are in r0, and r3 391 // no other registers need to be preserved, so invalidate them 392 __ invalidate_registers(false, true, true, false, true, true); 393 394 // check that there is really an exception 395 __ verify_not_null_oop(r0); 396 397 // search an exception handler (r0: exception oop, r3: throwing pc) 398 __ far_call(RuntimeAddress(Runtime1::entry_for(Runtime1::handle_exception_from_callee_id))); 399 __ should_not_reach_here(); 400 guarantee(code_offset() - offset <= exception_handler_size(), "overflow"); 401 __ end_a_stub(); 402 403 return offset; 404 } 405 406 407 // Emit the code to remove the frame from the stack in the exception 408 // unwind path. 409 int LIR_Assembler::emit_unwind_handler() { 410 #ifndef PRODUCT 411 if (CommentedAssembly) { 412 _masm->block_comment("Unwind handler"); 413 } 414 #endif 415 416 int offset = code_offset(); 417 418 // Fetch the exception from TLS and clear out exception related thread state 419 __ ldr(r0, Address(rthread, JavaThread::exception_oop_offset())); 420 __ str(zr, Address(rthread, JavaThread::exception_oop_offset())); 421 __ str(zr, Address(rthread, JavaThread::exception_pc_offset())); 422 423 __ bind(_unwind_handler_entry); 424 __ verify_not_null_oop(r0); 425 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) { 426 __ mov(r19, r0); // Preserve the exception 427 } 428 429 // Perform needed unlocking 430 MonitorExitStub* stub = NULL; 431 if (method()->is_synchronized()) { 432 monitor_address(0, FrameMap::r0_opr); 433 stub = new MonitorExitStub(FrameMap::r0_opr, true, 0); 434 if (UseHeavyMonitors) { 435 __ b(*stub->entry()); 436 } else { 437 __ unlock_object(r5, r4, r0, *stub->entry()); 438 } 439 __ bind(*stub->continuation()); 440 } 441 442 if (compilation()->env()->dtrace_method_probes()) { 443 __ mov(c_rarg0, rthread); 444 __ mov_metadata(c_rarg1, method()->constant_encoding()); 445 __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit), c_rarg0, c_rarg1); 446 } 447 448 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) { 449 __ mov(r0, r19); // Restore the exception 450 } 451 452 // remove the activation and dispatch to the unwind handler 453 __ block_comment("remove_frame and dispatch to the unwind handler"); 454 __ remove_frame(initial_frame_size_in_bytes()); 455 __ far_jump(RuntimeAddress(Runtime1::entry_for(Runtime1::unwind_exception_id))); 456 457 // Emit the slow path assembly 458 if (stub != NULL) { 459 stub->emit_code(this); 460 } 461 462 return offset; 463 } 464 465 466 int LIR_Assembler::emit_deopt_handler() { 467 // generate code for exception handler 468 address handler_base = __ start_a_stub(deopt_handler_size()); 469 if (handler_base == NULL) { 470 // not enough space left for the handler 471 bailout("deopt handler overflow"); 472 return -1; 473 } 474 475 int offset = code_offset(); 476 477 __ adr(lr, pc()); 478 __ far_jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack())); 479 guarantee(code_offset() - offset <= deopt_handler_size(), "overflow"); 480 __ end_a_stub(); 481 482 return offset; 483 } 484 485 void LIR_Assembler::add_debug_info_for_branch(address adr, CodeEmitInfo* info) { 486 _masm->code_section()->relocate(adr, relocInfo::poll_type); 487 int pc_offset = code_offset(); 488 flush_debug_info(pc_offset); 489 info->record_debug_info(compilation()->debug_info_recorder(), pc_offset); 490 if (info->exception_handlers() != NULL) { 491 compilation()->add_exception_handlers_for_pco(pc_offset, info->exception_handlers()); 492 } 493 } 494 495 void LIR_Assembler::return_op(LIR_Opr result, C1SafepointPollStub* code_stub) { 496 assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == r0, "word returns are in r0,"); 497 498 // Pop the stack before the safepoint code 499 __ remove_frame(initial_frame_size_in_bytes()); 500 501 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) { 502 __ reserved_stack_check(); 503 } 504 505 code_stub->set_safepoint_offset(__ offset()); 506 __ relocate(relocInfo::poll_return_type); 507 __ safepoint_poll(*code_stub->entry(), true /* at_return */, false /* acquire */, true /* in_nmethod */); 508 __ ret(lr); 509 } 510 511 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) { 512 guarantee(info != NULL, "Shouldn't be NULL"); 513 __ get_polling_page(rscratch1, relocInfo::poll_type); 514 add_debug_info_for_branch(info); // This isn't just debug info: 515 // it's the oop map 516 __ read_polling_page(rscratch1, relocInfo::poll_type); 517 return __ offset(); 518 } 519 520 521 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) { 522 if (from_reg == r31_sp) 523 from_reg = sp; 524 if (to_reg == r31_sp) 525 to_reg = sp; 526 __ mov(to_reg, from_reg); 527 } 528 529 void LIR_Assembler::swap_reg(Register a, Register b) { Unimplemented(); } 530 531 532 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) { 533 assert(src->is_constant(), "should not call otherwise"); 534 assert(dest->is_register(), "should not call otherwise"); 535 LIR_Const* c = src->as_constant_ptr(); 536 537 switch (c->type()) { 538 case T_INT: { 539 assert(patch_code == lir_patch_none, "no patching handled here"); 540 __ movw(dest->as_register(), c->as_jint()); 541 break; 542 } 543 544 case T_ADDRESS: { 545 assert(patch_code == lir_patch_none, "no patching handled here"); 546 __ mov(dest->as_register(), c->as_jint()); 547 break; 548 } 549 550 case T_LONG: { 551 assert(patch_code == lir_patch_none, "no patching handled here"); 552 __ mov(dest->as_register_lo(), (intptr_t)c->as_jlong()); 553 break; 554 } 555 556 case T_OBJECT: { 557 if (patch_code == lir_patch_none) { 558 jobject2reg(c->as_jobject(), dest->as_register()); 559 } else { 560 jobject2reg_with_patching(dest->as_register(), info); 561 } 562 break; 563 } 564 565 case T_METADATA: { 566 if (patch_code != lir_patch_none) { 567 klass2reg_with_patching(dest->as_register(), info); 568 } else { 569 __ mov_metadata(dest->as_register(), c->as_metadata()); 570 } 571 break; 572 } 573 574 case T_FLOAT: { 575 if (__ operand_valid_for_float_immediate(c->as_jfloat())) { 576 __ fmovs(dest->as_float_reg(), (c->as_jfloat())); 577 } else { 578 __ adr(rscratch1, InternalAddress(float_constant(c->as_jfloat()))); 579 __ ldrs(dest->as_float_reg(), Address(rscratch1)); 580 } 581 break; 582 } 583 584 case T_DOUBLE: { 585 if (__ operand_valid_for_float_immediate(c->as_jdouble())) { 586 __ fmovd(dest->as_double_reg(), (c->as_jdouble())); 587 } else { 588 __ adr(rscratch1, InternalAddress(double_constant(c->as_jdouble()))); 589 __ ldrd(dest->as_double_reg(), Address(rscratch1)); 590 } 591 break; 592 } 593 594 default: 595 ShouldNotReachHere(); 596 } 597 } 598 599 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) { 600 LIR_Const* c = src->as_constant_ptr(); 601 switch (c->type()) { 602 case T_OBJECT: 603 { 604 if (! c->as_jobject()) 605 __ str(zr, frame_map()->address_for_slot(dest->single_stack_ix())); 606 else { 607 const2reg(src, FrameMap::rscratch1_opr, lir_patch_none, NULL); 608 reg2stack(FrameMap::rscratch1_opr, dest, c->type(), false); 609 } 610 } 611 break; 612 case T_ADDRESS: 613 { 614 const2reg(src, FrameMap::rscratch1_opr, lir_patch_none, NULL); 615 reg2stack(FrameMap::rscratch1_opr, dest, c->type(), false); 616 } 617 case T_INT: 618 case T_FLOAT: 619 { 620 Register reg = zr; 621 if (c->as_jint_bits() == 0) 622 __ strw(zr, frame_map()->address_for_slot(dest->single_stack_ix())); 623 else { 624 __ movw(rscratch1, c->as_jint_bits()); 625 __ strw(rscratch1, frame_map()->address_for_slot(dest->single_stack_ix())); 626 } 627 } 628 break; 629 case T_LONG: 630 case T_DOUBLE: 631 { 632 Register reg = zr; 633 if (c->as_jlong_bits() == 0) 634 __ str(zr, frame_map()->address_for_slot(dest->double_stack_ix(), 635 lo_word_offset_in_bytes)); 636 else { 637 __ mov(rscratch1, (intptr_t)c->as_jlong_bits()); 638 __ str(rscratch1, frame_map()->address_for_slot(dest->double_stack_ix(), 639 lo_word_offset_in_bytes)); 640 } 641 } 642 break; 643 default: 644 ShouldNotReachHere(); 645 } 646 } 647 648 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) { 649 assert(src->is_constant(), "should not call otherwise"); 650 LIR_Const* c = src->as_constant_ptr(); 651 LIR_Address* to_addr = dest->as_address_ptr(); 652 653 void (Assembler::* insn)(Register Rt, const Address &adr); 654 655 switch (type) { 656 case T_ADDRESS: 657 assert(c->as_jint() == 0, "should be"); 658 insn = &Assembler::str; 659 break; 660 case T_LONG: 661 assert(c->as_jlong() == 0, "should be"); 662 insn = &Assembler::str; 663 break; 664 case T_INT: 665 assert(c->as_jint() == 0, "should be"); 666 insn = &Assembler::strw; 667 break; 668 case T_OBJECT: 669 case T_ARRAY: 670 assert(c->as_jobject() == 0, "should be"); 671 if (UseCompressedOops && !wide) { 672 insn = &Assembler::strw; 673 } else { 674 insn = &Assembler::str; 675 } 676 break; 677 case T_CHAR: 678 case T_SHORT: 679 assert(c->as_jint() == 0, "should be"); 680 insn = &Assembler::strh; 681 break; 682 case T_BOOLEAN: 683 case T_BYTE: 684 assert(c->as_jint() == 0, "should be"); 685 insn = &Assembler::strb; 686 break; 687 default: 688 ShouldNotReachHere(); 689 insn = &Assembler::str; // unreachable 690 } 691 692 if (info) add_debug_info_for_null_check_here(info); 693 (_masm->*insn)(zr, as_Address(to_addr, rscratch1)); 694 } 695 696 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) { 697 assert(src->is_register(), "should not call otherwise"); 698 assert(dest->is_register(), "should not call otherwise"); 699 700 // move between cpu-registers 701 if (dest->is_single_cpu()) { 702 if (src->type() == T_LONG) { 703 // Can do LONG -> OBJECT 704 move_regs(src->as_register_lo(), dest->as_register()); 705 return; 706 } 707 assert(src->is_single_cpu(), "must match"); 708 if (src->type() == T_OBJECT) { 709 __ verify_oop(src->as_register()); 710 } 711 move_regs(src->as_register(), dest->as_register()); 712 713 } else if (dest->is_double_cpu()) { 714 if (is_reference_type(src->type())) { 715 // Surprising to me but we can see move of a long to t_object 716 __ verify_oop(src->as_register()); 717 move_regs(src->as_register(), dest->as_register_lo()); 718 return; 719 } 720 assert(src->is_double_cpu(), "must match"); 721 Register f_lo = src->as_register_lo(); 722 Register f_hi = src->as_register_hi(); 723 Register t_lo = dest->as_register_lo(); 724 Register t_hi = dest->as_register_hi(); 725 assert(f_hi == f_lo, "must be same"); 726 assert(t_hi == t_lo, "must be same"); 727 move_regs(f_lo, t_lo); 728 729 } else if (dest->is_single_fpu()) { 730 __ fmovs(dest->as_float_reg(), src->as_float_reg()); 731 732 } else if (dest->is_double_fpu()) { 733 __ fmovd(dest->as_double_reg(), src->as_double_reg()); 734 735 } else { 736 ShouldNotReachHere(); 737 } 738 } 739 740 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) { 741 precond(src->is_register() && dest->is_stack()); 742 743 uint const c_sz32 = sizeof(uint32_t); 744 uint const c_sz64 = sizeof(uint64_t); 745 746 if (src->is_single_cpu()) { 747 int index = dest->single_stack_ix(); 748 if (is_reference_type(type)) { 749 __ str(src->as_register(), stack_slot_address(index, c_sz64, rscratch1)); 750 __ verify_oop(src->as_register()); 751 } else if (type == T_METADATA || type == T_DOUBLE || type == T_ADDRESS) { 752 __ str(src->as_register(), stack_slot_address(index, c_sz64, rscratch1)); 753 } else { 754 __ strw(src->as_register(), stack_slot_address(index, c_sz32, rscratch1)); 755 } 756 757 } else if (src->is_double_cpu()) { 758 int index = dest->double_stack_ix(); 759 Address dest_addr_LO = stack_slot_address(index, c_sz64, rscratch1, lo_word_offset_in_bytes); 760 __ str(src->as_register_lo(), dest_addr_LO); 761 762 } else if (src->is_single_fpu()) { 763 int index = dest->single_stack_ix(); 764 __ strs(src->as_float_reg(), stack_slot_address(index, c_sz32, rscratch1)); 765 766 } else if (src->is_double_fpu()) { 767 int index = dest->double_stack_ix(); 768 __ strd(src->as_double_reg(), stack_slot_address(index, c_sz64, rscratch1)); 769 770 } else { 771 ShouldNotReachHere(); 772 } 773 } 774 775 776 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool wide) { 777 LIR_Address* to_addr = dest->as_address_ptr(); 778 PatchingStub* patch = NULL; 779 Register compressed_src = rscratch1; 780 781 if (patch_code != lir_patch_none) { 782 deoptimize_trap(info); 783 return; 784 } 785 786 if (is_reference_type(type)) { 787 __ verify_oop(src->as_register()); 788 789 if (UseCompressedOops && !wide) { 790 __ encode_heap_oop(compressed_src, src->as_register()); 791 } else { 792 compressed_src = src->as_register(); 793 } 794 } 795 796 int null_check_here = code_offset(); 797 switch (type) { 798 case T_FLOAT: { 799 __ strs(src->as_float_reg(), as_Address(to_addr)); 800 break; 801 } 802 803 case T_DOUBLE: { 804 __ strd(src->as_double_reg(), as_Address(to_addr)); 805 break; 806 } 807 808 case T_ARRAY: // fall through 809 case T_OBJECT: // fall through 810 if (UseCompressedOops && !wide) { 811 __ strw(compressed_src, as_Address(to_addr, rscratch2)); 812 } else { 813 __ str(compressed_src, as_Address(to_addr)); 814 } 815 break; 816 case T_METADATA: 817 // We get here to store a method pointer to the stack to pass to 818 // a dtrace runtime call. This can't work on 64 bit with 819 // compressed klass ptrs: T_METADATA can be a compressed klass 820 // ptr or a 64 bit method pointer. 821 ShouldNotReachHere(); 822 __ str(src->as_register(), as_Address(to_addr)); 823 break; 824 case T_ADDRESS: 825 __ str(src->as_register(), as_Address(to_addr)); 826 break; 827 case T_INT: 828 __ strw(src->as_register(), as_Address(to_addr)); 829 break; 830 831 case T_LONG: { 832 __ str(src->as_register_lo(), as_Address_lo(to_addr)); 833 break; 834 } 835 836 case T_BYTE: // fall through 837 case T_BOOLEAN: { 838 __ strb(src->as_register(), as_Address(to_addr)); 839 break; 840 } 841 842 case T_CHAR: // fall through 843 case T_SHORT: 844 __ strh(src->as_register(), as_Address(to_addr)); 845 break; 846 847 default: 848 ShouldNotReachHere(); 849 } 850 if (info != NULL) { 851 add_debug_info_for_null_check(null_check_here, info); 852 } 853 } 854 855 856 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) { 857 precond(src->is_stack() && dest->is_register()); 858 859 uint const c_sz32 = sizeof(uint32_t); 860 uint const c_sz64 = sizeof(uint64_t); 861 862 if (dest->is_single_cpu()) { 863 int index = src->single_stack_ix(); 864 if (is_reference_type(type)) { 865 __ ldr(dest->as_register(), stack_slot_address(index, c_sz64, rscratch1)); 866 __ verify_oop(dest->as_register()); 867 } else if (type == T_METADATA || type == T_ADDRESS) { 868 __ ldr(dest->as_register(), stack_slot_address(index, c_sz64, rscratch1)); 869 } else { 870 __ ldrw(dest->as_register(), stack_slot_address(index, c_sz32, rscratch1)); 871 } 872 873 } else if (dest->is_double_cpu()) { 874 int index = src->double_stack_ix(); 875 Address src_addr_LO = stack_slot_address(index, c_sz64, rscratch1, lo_word_offset_in_bytes); 876 __ ldr(dest->as_register_lo(), src_addr_LO); 877 878 } else if (dest->is_single_fpu()) { 879 int index = src->single_stack_ix(); 880 __ ldrs(dest->as_float_reg(), stack_slot_address(index, c_sz32, rscratch1)); 881 882 } else if (dest->is_double_fpu()) { 883 int index = src->double_stack_ix(); 884 __ ldrd(dest->as_double_reg(), stack_slot_address(index, c_sz64, rscratch1)); 885 886 } else { 887 ShouldNotReachHere(); 888 } 889 } 890 891 892 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) { 893 address target = NULL; 894 relocInfo::relocType reloc_type = relocInfo::none; 895 896 switch (patching_id(info)) { 897 case PatchingStub::access_field_id: 898 target = Runtime1::entry_for(Runtime1::access_field_patching_id); 899 reloc_type = relocInfo::section_word_type; 900 break; 901 case PatchingStub::load_klass_id: 902 target = Runtime1::entry_for(Runtime1::load_klass_patching_id); 903 reloc_type = relocInfo::metadata_type; 904 break; 905 case PatchingStub::load_mirror_id: 906 target = Runtime1::entry_for(Runtime1::load_mirror_patching_id); 907 reloc_type = relocInfo::oop_type; 908 break; 909 case PatchingStub::load_appendix_id: 910 target = Runtime1::entry_for(Runtime1::load_appendix_patching_id); 911 reloc_type = relocInfo::oop_type; 912 break; 913 default: ShouldNotReachHere(); 914 } 915 916 __ far_call(RuntimeAddress(target)); 917 add_call_info_here(info); 918 } 919 920 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) { 921 922 LIR_Opr temp; 923 if (type == T_LONG || type == T_DOUBLE) 924 temp = FrameMap::rscratch1_long_opr; 925 else 926 temp = FrameMap::rscratch1_opr; 927 928 stack2reg(src, temp, src->type()); 929 reg2stack(temp, dest, dest->type(), false); 930 } 931 932 933 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide) { 934 LIR_Address* addr = src->as_address_ptr(); 935 LIR_Address* from_addr = src->as_address_ptr(); 936 937 if (addr->base()->type() == T_OBJECT) { 938 __ verify_oop(addr->base()->as_pointer_register()); 939 } 940 941 if (patch_code != lir_patch_none) { 942 deoptimize_trap(info); 943 return; 944 } 945 946 if (info != NULL) { 947 add_debug_info_for_null_check_here(info); 948 } 949 int null_check_here = code_offset(); 950 switch (type) { 951 case T_FLOAT: { 952 __ ldrs(dest->as_float_reg(), as_Address(from_addr)); 953 break; 954 } 955 956 case T_DOUBLE: { 957 __ ldrd(dest->as_double_reg(), as_Address(from_addr)); 958 break; 959 } 960 961 case T_ARRAY: // fall through 962 case T_OBJECT: // fall through 963 if (UseCompressedOops && !wide) { 964 __ ldrw(dest->as_register(), as_Address(from_addr)); 965 } else { 966 __ ldr(dest->as_register(), as_Address(from_addr)); 967 } 968 break; 969 case T_METADATA: 970 // We get here to store a method pointer to the stack to pass to 971 // a dtrace runtime call. This can't work on 64 bit with 972 // compressed klass ptrs: T_METADATA can be a compressed klass 973 // ptr or a 64 bit method pointer. 974 ShouldNotReachHere(); 975 __ ldr(dest->as_register(), as_Address(from_addr)); 976 break; 977 case T_ADDRESS: 978 __ ldr(dest->as_register(), as_Address(from_addr)); 979 break; 980 case T_INT: 981 __ ldrw(dest->as_register(), as_Address(from_addr)); 982 break; 983 984 case T_LONG: { 985 __ ldr(dest->as_register_lo(), as_Address_lo(from_addr)); 986 break; 987 } 988 989 case T_BYTE: 990 __ ldrsb(dest->as_register(), as_Address(from_addr)); 991 break; 992 case T_BOOLEAN: { 993 __ ldrb(dest->as_register(), as_Address(from_addr)); 994 break; 995 } 996 997 case T_CHAR: 998 __ ldrh(dest->as_register(), as_Address(from_addr)); 999 break; 1000 case T_SHORT: 1001 __ ldrsh(dest->as_register(), as_Address(from_addr)); 1002 break; 1003 1004 default: 1005 ShouldNotReachHere(); 1006 } 1007 1008 if (is_reference_type(type)) { 1009 if (UseCompressedOops && !wide) { 1010 __ decode_heap_oop(dest->as_register()); 1011 } 1012 1013 if (!UseZGC) { 1014 // Load barrier has not yet been applied, so ZGC can't verify the oop here 1015 __ verify_oop(dest->as_register()); 1016 } 1017 } 1018 } 1019 1020 1021 int LIR_Assembler::array_element_size(BasicType type) const { 1022 int elem_size = type2aelembytes(type); 1023 return exact_log2(elem_size); 1024 } 1025 1026 1027 void LIR_Assembler::emit_op3(LIR_Op3* op) { 1028 switch (op->code()) { 1029 case lir_idiv: 1030 case lir_irem: 1031 arithmetic_idiv(op->code(), 1032 op->in_opr1(), 1033 op->in_opr2(), 1034 op->in_opr3(), 1035 op->result_opr(), 1036 op->info()); 1037 break; 1038 case lir_fmad: 1039 __ fmaddd(op->result_opr()->as_double_reg(), 1040 op->in_opr1()->as_double_reg(), 1041 op->in_opr2()->as_double_reg(), 1042 op->in_opr3()->as_double_reg()); 1043 break; 1044 case lir_fmaf: 1045 __ fmadds(op->result_opr()->as_float_reg(), 1046 op->in_opr1()->as_float_reg(), 1047 op->in_opr2()->as_float_reg(), 1048 op->in_opr3()->as_float_reg()); 1049 break; 1050 default: ShouldNotReachHere(); break; 1051 } 1052 } 1053 1054 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) { 1055 #ifdef ASSERT 1056 assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label"); 1057 if (op->block() != NULL) _branch_target_blocks.append(op->block()); 1058 if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock()); 1059 #endif 1060 1061 if (op->cond() == lir_cond_always) { 1062 if (op->info() != NULL) add_debug_info_for_branch(op->info()); 1063 __ b(*(op->label())); 1064 } else { 1065 Assembler::Condition acond; 1066 if (op->code() == lir_cond_float_branch) { 1067 bool is_unordered = (op->ublock() == op->block()); 1068 // Assembler::EQ does not permit unordered branches, so we add 1069 // another branch here. Likewise, Assembler::NE does not permit 1070 // ordered branches. 1071 if ((is_unordered && op->cond() == lir_cond_equal) 1072 || (!is_unordered && op->cond() == lir_cond_notEqual)) 1073 __ br(Assembler::VS, *(op->ublock()->label())); 1074 switch(op->cond()) { 1075 case lir_cond_equal: acond = Assembler::EQ; break; 1076 case lir_cond_notEqual: acond = Assembler::NE; break; 1077 case lir_cond_less: acond = (is_unordered ? Assembler::LT : Assembler::LO); break; 1078 case lir_cond_lessEqual: acond = (is_unordered ? Assembler::LE : Assembler::LS); break; 1079 case lir_cond_greaterEqual: acond = (is_unordered ? Assembler::HS : Assembler::GE); break; 1080 case lir_cond_greater: acond = (is_unordered ? Assembler::HI : Assembler::GT); break; 1081 default: ShouldNotReachHere(); 1082 acond = Assembler::EQ; // unreachable 1083 } 1084 } else { 1085 switch (op->cond()) { 1086 case lir_cond_equal: acond = Assembler::EQ; break; 1087 case lir_cond_notEqual: acond = Assembler::NE; break; 1088 case lir_cond_less: acond = Assembler::LT; break; 1089 case lir_cond_lessEqual: acond = Assembler::LE; break; 1090 case lir_cond_greaterEqual: acond = Assembler::GE; break; 1091 case lir_cond_greater: acond = Assembler::GT; break; 1092 case lir_cond_belowEqual: acond = Assembler::LS; break; 1093 case lir_cond_aboveEqual: acond = Assembler::HS; break; 1094 default: ShouldNotReachHere(); 1095 acond = Assembler::EQ; // unreachable 1096 } 1097 } 1098 __ br(acond,*(op->label())); 1099 } 1100 } 1101 1102 1103 1104 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) { 1105 LIR_Opr src = op->in_opr(); 1106 LIR_Opr dest = op->result_opr(); 1107 1108 switch (op->bytecode()) { 1109 case Bytecodes::_i2f: 1110 { 1111 __ scvtfws(dest->as_float_reg(), src->as_register()); 1112 break; 1113 } 1114 case Bytecodes::_i2d: 1115 { 1116 __ scvtfwd(dest->as_double_reg(), src->as_register()); 1117 break; 1118 } 1119 case Bytecodes::_l2d: 1120 { 1121 __ scvtfd(dest->as_double_reg(), src->as_register_lo()); 1122 break; 1123 } 1124 case Bytecodes::_l2f: 1125 { 1126 __ scvtfs(dest->as_float_reg(), src->as_register_lo()); 1127 break; 1128 } 1129 case Bytecodes::_f2d: 1130 { 1131 __ fcvts(dest->as_double_reg(), src->as_float_reg()); 1132 break; 1133 } 1134 case Bytecodes::_d2f: 1135 { 1136 __ fcvtd(dest->as_float_reg(), src->as_double_reg()); 1137 break; 1138 } 1139 case Bytecodes::_i2c: 1140 { 1141 __ ubfx(dest->as_register(), src->as_register(), 0, 16); 1142 break; 1143 } 1144 case Bytecodes::_i2l: 1145 { 1146 __ sxtw(dest->as_register_lo(), src->as_register()); 1147 break; 1148 } 1149 case Bytecodes::_i2s: 1150 { 1151 __ sxth(dest->as_register(), src->as_register()); 1152 break; 1153 } 1154 case Bytecodes::_i2b: 1155 { 1156 __ sxtb(dest->as_register(), src->as_register()); 1157 break; 1158 } 1159 case Bytecodes::_l2i: 1160 { 1161 _masm->block_comment("FIXME: This could be a no-op"); 1162 __ uxtw(dest->as_register(), src->as_register_lo()); 1163 break; 1164 } 1165 case Bytecodes::_d2l: 1166 { 1167 __ fcvtzd(dest->as_register_lo(), src->as_double_reg()); 1168 break; 1169 } 1170 case Bytecodes::_f2i: 1171 { 1172 __ fcvtzsw(dest->as_register(), src->as_float_reg()); 1173 break; 1174 } 1175 case Bytecodes::_f2l: 1176 { 1177 __ fcvtzs(dest->as_register_lo(), src->as_float_reg()); 1178 break; 1179 } 1180 case Bytecodes::_d2i: 1181 { 1182 __ fcvtzdw(dest->as_register(), src->as_double_reg()); 1183 break; 1184 } 1185 default: ShouldNotReachHere(); 1186 } 1187 } 1188 1189 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) { 1190 if (op->init_check()) { 1191 __ ldrb(rscratch1, Address(op->klass()->as_register(), 1192 InstanceKlass::init_state_offset())); 1193 __ cmpw(rscratch1, InstanceKlass::fully_initialized); 1194 add_debug_info_for_null_check_here(op->stub()->info()); 1195 __ br(Assembler::NE, *op->stub()->entry()); 1196 } 1197 __ allocate_object(op->obj()->as_register(), 1198 op->tmp1()->as_register(), 1199 op->tmp2()->as_register(), 1200 op->header_size(), 1201 op->object_size(), 1202 op->klass()->as_register(), 1203 *op->stub()->entry()); 1204 __ bind(*op->stub()->continuation()); 1205 } 1206 1207 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) { 1208 Register len = op->len()->as_register(); 1209 __ uxtw(len, len); 1210 1211 if (UseSlowPath || 1212 (!UseFastNewObjectArray && is_reference_type(op->type())) || 1213 (!UseFastNewTypeArray && !is_reference_type(op->type()))) { 1214 __ b(*op->stub()->entry()); 1215 } else { 1216 Register tmp1 = op->tmp1()->as_register(); 1217 Register tmp2 = op->tmp2()->as_register(); 1218 Register tmp3 = op->tmp3()->as_register(); 1219 if (len == tmp1) { 1220 tmp1 = tmp3; 1221 } else if (len == tmp2) { 1222 tmp2 = tmp3; 1223 } else if (len == tmp3) { 1224 // everything is ok 1225 } else { 1226 __ mov(tmp3, len); 1227 } 1228 __ allocate_array(op->obj()->as_register(), 1229 len, 1230 tmp1, 1231 tmp2, 1232 arrayOopDesc::header_size(op->type()), 1233 array_element_size(op->type()), 1234 op->klass()->as_register(), 1235 *op->stub()->entry()); 1236 } 1237 __ bind(*op->stub()->continuation()); 1238 } 1239 1240 void LIR_Assembler::type_profile_helper(Register mdo, 1241 ciMethodData *md, ciProfileData *data, 1242 Register recv, Label* update_done) { 1243 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) { 1244 Label next_test; 1245 // See if the receiver is receiver[n]. 1246 __ lea(rscratch2, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)))); 1247 __ ldr(rscratch1, Address(rscratch2)); 1248 __ cmp(recv, rscratch1); 1249 __ br(Assembler::NE, next_test); 1250 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))); 1251 __ addptr(data_addr, DataLayout::counter_increment); 1252 __ b(*update_done); 1253 __ bind(next_test); 1254 } 1255 1256 // Didn't find receiver; find next empty slot and fill it in 1257 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) { 1258 Label next_test; 1259 __ lea(rscratch2, 1260 Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)))); 1261 Address recv_addr(rscratch2); 1262 __ ldr(rscratch1, recv_addr); 1263 __ cbnz(rscratch1, next_test); 1264 __ str(recv, recv_addr); 1265 __ mov(rscratch1, DataLayout::counter_increment); 1266 __ lea(rscratch2, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)))); 1267 __ str(rscratch1, Address(rscratch2)); 1268 __ b(*update_done); 1269 __ bind(next_test); 1270 } 1271 } 1272 1273 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) { 1274 // we always need a stub for the failure case. 1275 CodeStub* stub = op->stub(); 1276 Register obj = op->object()->as_register(); 1277 Register k_RInfo = op->tmp1()->as_register(); 1278 Register klass_RInfo = op->tmp2()->as_register(); 1279 Register dst = op->result_opr()->as_register(); 1280 ciKlass* k = op->klass(); 1281 Register Rtmp1 = noreg; 1282 1283 // check if it needs to be profiled 1284 ciMethodData* md; 1285 ciProfileData* data; 1286 1287 const bool should_profile = op->should_profile(); 1288 1289 if (should_profile) { 1290 ciMethod* method = op->profiled_method(); 1291 assert(method != NULL, "Should have method"); 1292 int bci = op->profiled_bci(); 1293 md = method->method_data_or_null(); 1294 assert(md != NULL, "Sanity"); 1295 data = md->bci_to_data(bci); 1296 assert(data != NULL, "need data for type check"); 1297 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check"); 1298 } 1299 Label profile_cast_success, profile_cast_failure; 1300 Label *success_target = should_profile ? &profile_cast_success : success; 1301 Label *failure_target = should_profile ? &profile_cast_failure : failure; 1302 1303 if (obj == k_RInfo) { 1304 k_RInfo = dst; 1305 } else if (obj == klass_RInfo) { 1306 klass_RInfo = dst; 1307 } 1308 if (k->is_loaded() && !UseCompressedClassPointers) { 1309 select_different_registers(obj, dst, k_RInfo, klass_RInfo); 1310 } else { 1311 Rtmp1 = op->tmp3()->as_register(); 1312 select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1); 1313 } 1314 1315 assert_different_registers(obj, k_RInfo, klass_RInfo); 1316 1317 if (should_profile) { 1318 Label not_null; 1319 __ cbnz(obj, not_null); 1320 // Object is null; update MDO and exit 1321 Register mdo = klass_RInfo; 1322 __ mov_metadata(mdo, md->constant_encoding()); 1323 Address data_addr 1324 = __ form_address(rscratch2, mdo, 1325 md->byte_offset_of_slot(data, DataLayout::flags_offset()), 1326 0); 1327 __ ldrb(rscratch1, data_addr); 1328 __ orr(rscratch1, rscratch1, BitData::null_seen_byte_constant()); 1329 __ strb(rscratch1, data_addr); 1330 __ b(*obj_is_null); 1331 __ bind(not_null); 1332 } else { 1333 __ cbz(obj, *obj_is_null); 1334 } 1335 1336 if (!k->is_loaded()) { 1337 klass2reg_with_patching(k_RInfo, op->info_for_patch()); 1338 } else { 1339 __ mov_metadata(k_RInfo, k->constant_encoding()); 1340 } 1341 __ verify_oop(obj); 1342 1343 if (op->fast_check()) { 1344 // get object class 1345 // not a safepoint as obj null check happens earlier 1346 __ load_klass(rscratch1, obj); 1347 __ cmp( rscratch1, k_RInfo); 1348 1349 __ br(Assembler::NE, *failure_target); 1350 // successful cast, fall through to profile or jump 1351 } else { 1352 // get object class 1353 // not a safepoint as obj null check happens earlier 1354 __ load_klass(klass_RInfo, obj); 1355 if (k->is_loaded()) { 1356 // See if we get an immediate positive hit 1357 __ ldr(rscratch1, Address(klass_RInfo, int64_t(k->super_check_offset()))); 1358 __ cmp(k_RInfo, rscratch1); 1359 if ((juint)in_bytes(Klass::secondary_super_cache_offset()) != k->super_check_offset()) { 1360 __ br(Assembler::NE, *failure_target); 1361 // successful cast, fall through to profile or jump 1362 } else { 1363 // See if we get an immediate positive hit 1364 __ br(Assembler::EQ, *success_target); 1365 // check for self 1366 __ cmp(klass_RInfo, k_RInfo); 1367 __ br(Assembler::EQ, *success_target); 1368 1369 __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize))); 1370 __ far_call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); 1371 __ ldr(klass_RInfo, Address(__ post(sp, 2 * wordSize))); 1372 // result is a boolean 1373 __ cbzw(klass_RInfo, *failure_target); 1374 // successful cast, fall through to profile or jump 1375 } 1376 } else { 1377 // perform the fast part of the checking logic 1378 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL); 1379 // call out-of-line instance of __ check_klass_subtype_slow_path(...): 1380 __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize))); 1381 __ far_call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); 1382 __ ldp(k_RInfo, klass_RInfo, Address(__ post(sp, 2 * wordSize))); 1383 // result is a boolean 1384 __ cbz(k_RInfo, *failure_target); 1385 // successful cast, fall through to profile or jump 1386 } 1387 } 1388 if (should_profile) { 1389 Register mdo = klass_RInfo, recv = k_RInfo; 1390 __ bind(profile_cast_success); 1391 __ mov_metadata(mdo, md->constant_encoding()); 1392 __ load_klass(recv, obj); 1393 Label update_done; 1394 type_profile_helper(mdo, md, data, recv, success); 1395 __ b(*success); 1396 1397 __ bind(profile_cast_failure); 1398 __ mov_metadata(mdo, md->constant_encoding()); 1399 Address counter_addr 1400 = __ form_address(rscratch2, mdo, 1401 md->byte_offset_of_slot(data, CounterData::count_offset()), 1402 0); 1403 __ ldr(rscratch1, counter_addr); 1404 __ sub(rscratch1, rscratch1, DataLayout::counter_increment); 1405 __ str(rscratch1, counter_addr); 1406 __ b(*failure); 1407 } 1408 __ b(*success); 1409 } 1410 1411 1412 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) { 1413 const bool should_profile = op->should_profile(); 1414 1415 LIR_Code code = op->code(); 1416 if (code == lir_store_check) { 1417 Register value = op->object()->as_register(); 1418 Register array = op->array()->as_register(); 1419 Register k_RInfo = op->tmp1()->as_register(); 1420 Register klass_RInfo = op->tmp2()->as_register(); 1421 Register Rtmp1 = op->tmp3()->as_register(); 1422 1423 CodeStub* stub = op->stub(); 1424 1425 // check if it needs to be profiled 1426 ciMethodData* md; 1427 ciProfileData* data; 1428 1429 if (should_profile) { 1430 ciMethod* method = op->profiled_method(); 1431 assert(method != NULL, "Should have method"); 1432 int bci = op->profiled_bci(); 1433 md = method->method_data_or_null(); 1434 assert(md != NULL, "Sanity"); 1435 data = md->bci_to_data(bci); 1436 assert(data != NULL, "need data for type check"); 1437 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check"); 1438 } 1439 Label profile_cast_success, profile_cast_failure, done; 1440 Label *success_target = should_profile ? &profile_cast_success : &done; 1441 Label *failure_target = should_profile ? &profile_cast_failure : stub->entry(); 1442 1443 if (should_profile) { 1444 Label not_null; 1445 __ cbnz(value, not_null); 1446 // Object is null; update MDO and exit 1447 Register mdo = klass_RInfo; 1448 __ mov_metadata(mdo, md->constant_encoding()); 1449 Address data_addr 1450 = __ form_address(rscratch2, mdo, 1451 md->byte_offset_of_slot(data, DataLayout::flags_offset()), 1452 0); 1453 __ ldrb(rscratch1, data_addr); 1454 __ orr(rscratch1, rscratch1, BitData::null_seen_byte_constant()); 1455 __ strb(rscratch1, data_addr); 1456 __ b(done); 1457 __ bind(not_null); 1458 } else { 1459 __ cbz(value, done); 1460 } 1461 1462 add_debug_info_for_null_check_here(op->info_for_exception()); 1463 __ load_klass(k_RInfo, array); 1464 __ load_klass(klass_RInfo, value); 1465 1466 // get instance klass (it's already uncompressed) 1467 __ ldr(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset())); 1468 // perform the fast part of the checking logic 1469 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL); 1470 // call out-of-line instance of __ check_klass_subtype_slow_path(...): 1471 __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize))); 1472 __ far_call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); 1473 __ ldp(k_RInfo, klass_RInfo, Address(__ post(sp, 2 * wordSize))); 1474 // result is a boolean 1475 __ cbzw(k_RInfo, *failure_target); 1476 // fall through to the success case 1477 1478 if (should_profile) { 1479 Register mdo = klass_RInfo, recv = k_RInfo; 1480 __ bind(profile_cast_success); 1481 __ mov_metadata(mdo, md->constant_encoding()); 1482 __ load_klass(recv, value); 1483 Label update_done; 1484 type_profile_helper(mdo, md, data, recv, &done); 1485 __ b(done); 1486 1487 __ bind(profile_cast_failure); 1488 __ mov_metadata(mdo, md->constant_encoding()); 1489 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset())); 1490 __ lea(rscratch2, counter_addr); 1491 __ ldr(rscratch1, Address(rscratch2)); 1492 __ sub(rscratch1, rscratch1, DataLayout::counter_increment); 1493 __ str(rscratch1, Address(rscratch2)); 1494 __ b(*stub->entry()); 1495 } 1496 1497 __ bind(done); 1498 } else if (code == lir_checkcast) { 1499 Register obj = op->object()->as_register(); 1500 Register dst = op->result_opr()->as_register(); 1501 Label success; 1502 emit_typecheck_helper(op, &success, op->stub()->entry(), &success); 1503 __ bind(success); 1504 if (dst != obj) { 1505 __ mov(dst, obj); 1506 } 1507 } else if (code == lir_instanceof) { 1508 Register obj = op->object()->as_register(); 1509 Register dst = op->result_opr()->as_register(); 1510 Label success, failure, done; 1511 emit_typecheck_helper(op, &success, &failure, &failure); 1512 __ bind(failure); 1513 __ mov(dst, zr); 1514 __ b(done); 1515 __ bind(success); 1516 __ mov(dst, 1); 1517 __ bind(done); 1518 } else { 1519 ShouldNotReachHere(); 1520 } 1521 } 1522 1523 void LIR_Assembler::casw(Register addr, Register newval, Register cmpval) { 1524 __ cmpxchg(addr, cmpval, newval, Assembler::word, /* acquire*/ true, /* release*/ true, /* weak*/ false, rscratch1); 1525 __ cset(rscratch1, Assembler::NE); 1526 __ membar(__ AnyAny); 1527 } 1528 1529 void LIR_Assembler::casl(Register addr, Register newval, Register cmpval) { 1530 __ cmpxchg(addr, cmpval, newval, Assembler::xword, /* acquire*/ true, /* release*/ true, /* weak*/ false, rscratch1); 1531 __ cset(rscratch1, Assembler::NE); 1532 __ membar(__ AnyAny); 1533 } 1534 1535 1536 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) { 1537 assert(VM_Version::supports_cx8(), "wrong machine"); 1538 Register addr; 1539 if (op->addr()->is_register()) { 1540 addr = as_reg(op->addr()); 1541 } else { 1542 assert(op->addr()->is_address(), "what else?"); 1543 LIR_Address* addr_ptr = op->addr()->as_address_ptr(); 1544 assert(addr_ptr->disp() == 0, "need 0 disp"); 1545 assert(addr_ptr->index() == LIR_Opr::illegalOpr(), "need 0 index"); 1546 addr = as_reg(addr_ptr->base()); 1547 } 1548 Register newval = as_reg(op->new_value()); 1549 Register cmpval = as_reg(op->cmp_value()); 1550 1551 if (op->code() == lir_cas_obj) { 1552 if (UseCompressedOops) { 1553 Register t1 = op->tmp1()->as_register(); 1554 assert(op->tmp1()->is_valid(), "must be"); 1555 __ encode_heap_oop(t1, cmpval); 1556 cmpval = t1; 1557 __ encode_heap_oop(rscratch2, newval); 1558 newval = rscratch2; 1559 casw(addr, newval, cmpval); 1560 } else { 1561 casl(addr, newval, cmpval); 1562 } 1563 } else if (op->code() == lir_cas_int) { 1564 casw(addr, newval, cmpval); 1565 } else { 1566 casl(addr, newval, cmpval); 1567 } 1568 } 1569 1570 1571 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type, 1572 LIR_Opr cmp_opr1, LIR_Opr cmp_opr2) { 1573 assert(cmp_opr1 == LIR_OprFact::illegalOpr && cmp_opr2 == LIR_OprFact::illegalOpr, "unnecessary cmp oprs on aarch64"); 1574 1575 Assembler::Condition acond, ncond; 1576 switch (condition) { 1577 case lir_cond_equal: acond = Assembler::EQ; ncond = Assembler::NE; break; 1578 case lir_cond_notEqual: acond = Assembler::NE; ncond = Assembler::EQ; break; 1579 case lir_cond_less: acond = Assembler::LT; ncond = Assembler::GE; break; 1580 case lir_cond_lessEqual: acond = Assembler::LE; ncond = Assembler::GT; break; 1581 case lir_cond_greaterEqual: acond = Assembler::GE; ncond = Assembler::LT; break; 1582 case lir_cond_greater: acond = Assembler::GT; ncond = Assembler::LE; break; 1583 case lir_cond_belowEqual: 1584 case lir_cond_aboveEqual: 1585 default: ShouldNotReachHere(); 1586 acond = Assembler::EQ; ncond = Assembler::NE; // unreachable 1587 } 1588 1589 assert(result->is_single_cpu() || result->is_double_cpu(), 1590 "expect single register for result"); 1591 if (opr1->is_constant() && opr2->is_constant() 1592 && opr1->type() == T_INT && opr2->type() == T_INT) { 1593 jint val1 = opr1->as_jint(); 1594 jint val2 = opr2->as_jint(); 1595 if (val1 == 0 && val2 == 1) { 1596 __ cset(result->as_register(), ncond); 1597 return; 1598 } else if (val1 == 1 && val2 == 0) { 1599 __ cset(result->as_register(), acond); 1600 return; 1601 } 1602 } 1603 1604 if (opr1->is_constant() && opr2->is_constant() 1605 && opr1->type() == T_LONG && opr2->type() == T_LONG) { 1606 jlong val1 = opr1->as_jlong(); 1607 jlong val2 = opr2->as_jlong(); 1608 if (val1 == 0 && val2 == 1) { 1609 __ cset(result->as_register_lo(), ncond); 1610 return; 1611 } else if (val1 == 1 && val2 == 0) { 1612 __ cset(result->as_register_lo(), acond); 1613 return; 1614 } 1615 } 1616 1617 if (opr1->is_stack()) { 1618 stack2reg(opr1, FrameMap::rscratch1_opr, result->type()); 1619 opr1 = FrameMap::rscratch1_opr; 1620 } else if (opr1->is_constant()) { 1621 LIR_Opr tmp 1622 = opr1->type() == T_LONG ? FrameMap::rscratch1_long_opr : FrameMap::rscratch1_opr; 1623 const2reg(opr1, tmp, lir_patch_none, NULL); 1624 opr1 = tmp; 1625 } 1626 1627 if (opr2->is_stack()) { 1628 stack2reg(opr2, FrameMap::rscratch2_opr, result->type()); 1629 opr2 = FrameMap::rscratch2_opr; 1630 } else if (opr2->is_constant()) { 1631 LIR_Opr tmp 1632 = opr2->type() == T_LONG ? FrameMap::rscratch2_long_opr : FrameMap::rscratch2_opr; 1633 const2reg(opr2, tmp, lir_patch_none, NULL); 1634 opr2 = tmp; 1635 } 1636 1637 if (result->type() == T_LONG) 1638 __ csel(result->as_register_lo(), opr1->as_register_lo(), opr2->as_register_lo(), acond); 1639 else 1640 __ csel(result->as_register(), opr1->as_register(), opr2->as_register(), acond); 1641 } 1642 1643 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) { 1644 assert(info == NULL, "should never be used, idiv/irem and ldiv/lrem not handled by this method"); 1645 1646 if (left->is_single_cpu()) { 1647 Register lreg = left->as_register(); 1648 Register dreg = as_reg(dest); 1649 1650 if (right->is_single_cpu()) { 1651 // cpu register - cpu register 1652 1653 assert(left->type() == T_INT && right->type() == T_INT && dest->type() == T_INT, 1654 "should be"); 1655 Register rreg = right->as_register(); 1656 switch (code) { 1657 case lir_add: __ addw (dest->as_register(), lreg, rreg); break; 1658 case lir_sub: __ subw (dest->as_register(), lreg, rreg); break; 1659 case lir_mul: __ mulw (dest->as_register(), lreg, rreg); break; 1660 default: ShouldNotReachHere(); 1661 } 1662 1663 } else if (right->is_double_cpu()) { 1664 Register rreg = right->as_register_lo(); 1665 // single_cpu + double_cpu: can happen with obj+long 1666 assert(code == lir_add || code == lir_sub, "mismatched arithmetic op"); 1667 switch (code) { 1668 case lir_add: __ add(dreg, lreg, rreg); break; 1669 case lir_sub: __ sub(dreg, lreg, rreg); break; 1670 default: ShouldNotReachHere(); 1671 } 1672 } else if (right->is_constant()) { 1673 // cpu register - constant 1674 jlong c; 1675 1676 // FIXME. This is fugly: we really need to factor all this logic. 1677 switch(right->type()) { 1678 case T_LONG: 1679 c = right->as_constant_ptr()->as_jlong(); 1680 break; 1681 case T_INT: 1682 case T_ADDRESS: 1683 c = right->as_constant_ptr()->as_jint(); 1684 break; 1685 default: 1686 ShouldNotReachHere(); 1687 c = 0; // unreachable 1688 break; 1689 } 1690 1691 assert(code == lir_add || code == lir_sub, "mismatched arithmetic op"); 1692 if (c == 0 && dreg == lreg) { 1693 COMMENT("effective nop elided"); 1694 return; 1695 } 1696 switch(left->type()) { 1697 case T_INT: 1698 switch (code) { 1699 case lir_add: __ addw(dreg, lreg, c); break; 1700 case lir_sub: __ subw(dreg, lreg, c); break; 1701 default: ShouldNotReachHere(); 1702 } 1703 break; 1704 case T_OBJECT: 1705 case T_ADDRESS: 1706 switch (code) { 1707 case lir_add: __ add(dreg, lreg, c); break; 1708 case lir_sub: __ sub(dreg, lreg, c); break; 1709 default: ShouldNotReachHere(); 1710 } 1711 break; 1712 default: 1713 ShouldNotReachHere(); 1714 } 1715 } else { 1716 ShouldNotReachHere(); 1717 } 1718 1719 } else if (left->is_double_cpu()) { 1720 Register lreg_lo = left->as_register_lo(); 1721 1722 if (right->is_double_cpu()) { 1723 // cpu register - cpu register 1724 Register rreg_lo = right->as_register_lo(); 1725 switch (code) { 1726 case lir_add: __ add (dest->as_register_lo(), lreg_lo, rreg_lo); break; 1727 case lir_sub: __ sub (dest->as_register_lo(), lreg_lo, rreg_lo); break; 1728 case lir_mul: __ mul (dest->as_register_lo(), lreg_lo, rreg_lo); break; 1729 case lir_div: __ corrected_idivq(dest->as_register_lo(), lreg_lo, rreg_lo, false, rscratch1); break; 1730 case lir_rem: __ corrected_idivq(dest->as_register_lo(), lreg_lo, rreg_lo, true, rscratch1); break; 1731 default: 1732 ShouldNotReachHere(); 1733 } 1734 1735 } else if (right->is_constant()) { 1736 jlong c = right->as_constant_ptr()->as_jlong(); 1737 Register dreg = as_reg(dest); 1738 switch (code) { 1739 case lir_add: 1740 case lir_sub: 1741 if (c == 0 && dreg == lreg_lo) { 1742 COMMENT("effective nop elided"); 1743 return; 1744 } 1745 code == lir_add ? __ add(dreg, lreg_lo, c) : __ sub(dreg, lreg_lo, c); 1746 break; 1747 case lir_div: 1748 assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant"); 1749 if (c == 1) { 1750 // move lreg_lo to dreg if divisor is 1 1751 __ mov(dreg, lreg_lo); 1752 } else { 1753 unsigned int shift = log2i_exact(c); 1754 // use rscratch1 as intermediate result register 1755 __ asr(rscratch1, lreg_lo, 63); 1756 __ add(rscratch1, lreg_lo, rscratch1, Assembler::LSR, 64 - shift); 1757 __ asr(dreg, rscratch1, shift); 1758 } 1759 break; 1760 case lir_rem: 1761 assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant"); 1762 if (c == 1) { 1763 // move 0 to dreg if divisor is 1 1764 __ mov(dreg, zr); 1765 } else { 1766 // use rscratch1 as intermediate result register 1767 __ negs(rscratch1, lreg_lo); 1768 __ andr(dreg, lreg_lo, c - 1); 1769 __ andr(rscratch1, rscratch1, c - 1); 1770 __ csneg(dreg, dreg, rscratch1, Assembler::MI); 1771 } 1772 break; 1773 default: 1774 ShouldNotReachHere(); 1775 } 1776 } else { 1777 ShouldNotReachHere(); 1778 } 1779 } else if (left->is_single_fpu()) { 1780 assert(right->is_single_fpu(), "right hand side of float arithmetics needs to be float register"); 1781 switch (code) { 1782 case lir_add: __ fadds (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break; 1783 case lir_sub: __ fsubs (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break; 1784 case lir_mul: __ fmuls (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break; 1785 case lir_div: __ fdivs (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break; 1786 default: 1787 ShouldNotReachHere(); 1788 } 1789 } else if (left->is_double_fpu()) { 1790 if (right->is_double_fpu()) { 1791 // fpu register - fpu register 1792 switch (code) { 1793 case lir_add: __ faddd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break; 1794 case lir_sub: __ fsubd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break; 1795 case lir_mul: __ fmuld (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break; 1796 case lir_div: __ fdivd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break; 1797 default: 1798 ShouldNotReachHere(); 1799 } 1800 } else { 1801 if (right->is_constant()) { 1802 ShouldNotReachHere(); 1803 } 1804 ShouldNotReachHere(); 1805 } 1806 } else if (left->is_single_stack() || left->is_address()) { 1807 assert(left == dest, "left and dest must be equal"); 1808 ShouldNotReachHere(); 1809 } else { 1810 ShouldNotReachHere(); 1811 } 1812 } 1813 1814 void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) { Unimplemented(); } 1815 1816 1817 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr unused, LIR_Opr dest, LIR_Op* op) { 1818 switch(code) { 1819 case lir_abs : __ fabsd(dest->as_double_reg(), value->as_double_reg()); break; 1820 case lir_sqrt: __ fsqrtd(dest->as_double_reg(), value->as_double_reg()); break; 1821 default : ShouldNotReachHere(); 1822 } 1823 } 1824 1825 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) { 1826 1827 assert(left->is_single_cpu() || left->is_double_cpu(), "expect single or double register"); 1828 Register Rleft = left->is_single_cpu() ? left->as_register() : 1829 left->as_register_lo(); 1830 if (dst->is_single_cpu()) { 1831 Register Rdst = dst->as_register(); 1832 if (right->is_constant()) { 1833 switch (code) { 1834 case lir_logic_and: __ andw (Rdst, Rleft, right->as_jint()); break; 1835 case lir_logic_or: __ orrw (Rdst, Rleft, right->as_jint()); break; 1836 case lir_logic_xor: __ eorw (Rdst, Rleft, right->as_jint()); break; 1837 default: ShouldNotReachHere(); break; 1838 } 1839 } else { 1840 Register Rright = right->is_single_cpu() ? right->as_register() : 1841 right->as_register_lo(); 1842 switch (code) { 1843 case lir_logic_and: __ andw (Rdst, Rleft, Rright); break; 1844 case lir_logic_or: __ orrw (Rdst, Rleft, Rright); break; 1845 case lir_logic_xor: __ eorw (Rdst, Rleft, Rright); break; 1846 default: ShouldNotReachHere(); break; 1847 } 1848 } 1849 } else { 1850 Register Rdst = dst->as_register_lo(); 1851 if (right->is_constant()) { 1852 switch (code) { 1853 case lir_logic_and: __ andr (Rdst, Rleft, right->as_jlong()); break; 1854 case lir_logic_or: __ orr (Rdst, Rleft, right->as_jlong()); break; 1855 case lir_logic_xor: __ eor (Rdst, Rleft, right->as_jlong()); break; 1856 default: ShouldNotReachHere(); break; 1857 } 1858 } else { 1859 Register Rright = right->is_single_cpu() ? right->as_register() : 1860 right->as_register_lo(); 1861 switch (code) { 1862 case lir_logic_and: __ andr (Rdst, Rleft, Rright); break; 1863 case lir_logic_or: __ orr (Rdst, Rleft, Rright); break; 1864 case lir_logic_xor: __ eor (Rdst, Rleft, Rright); break; 1865 default: ShouldNotReachHere(); break; 1866 } 1867 } 1868 } 1869 } 1870 1871 1872 1873 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr illegal, LIR_Opr result, CodeEmitInfo* info) { 1874 1875 // opcode check 1876 assert((code == lir_idiv) || (code == lir_irem), "opcode must be idiv or irem"); 1877 bool is_irem = (code == lir_irem); 1878 1879 // operand check 1880 assert(left->is_single_cpu(), "left must be register"); 1881 assert(right->is_single_cpu() || right->is_constant(), "right must be register or constant"); 1882 assert(result->is_single_cpu(), "result must be register"); 1883 Register lreg = left->as_register(); 1884 Register dreg = result->as_register(); 1885 1886 // power-of-2 constant check and codegen 1887 if (right->is_constant()) { 1888 int c = right->as_constant_ptr()->as_jint(); 1889 assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant"); 1890 if (is_irem) { 1891 if (c == 1) { 1892 // move 0 to dreg if divisor is 1 1893 __ movw(dreg, zr); 1894 } else { 1895 // use rscratch1 as intermediate result register 1896 __ negsw(rscratch1, lreg); 1897 __ andw(dreg, lreg, c - 1); 1898 __ andw(rscratch1, rscratch1, c - 1); 1899 __ csnegw(dreg, dreg, rscratch1, Assembler::MI); 1900 } 1901 } else { 1902 if (c == 1) { 1903 // move lreg to dreg if divisor is 1 1904 __ movw(dreg, lreg); 1905 } else { 1906 unsigned int shift = exact_log2(c); 1907 // use rscratch1 as intermediate result register 1908 __ asrw(rscratch1, lreg, 31); 1909 __ addw(rscratch1, lreg, rscratch1, Assembler::LSR, 32 - shift); 1910 __ asrw(dreg, rscratch1, shift); 1911 } 1912 } 1913 } else { 1914 Register rreg = right->as_register(); 1915 __ corrected_idivl(dreg, lreg, rreg, is_irem, rscratch1); 1916 } 1917 } 1918 1919 1920 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) { 1921 if (opr1->is_constant() && opr2->is_single_cpu()) { 1922 // tableswitch 1923 Register reg = as_reg(opr2); 1924 struct tableswitch &table = switches[opr1->as_constant_ptr()->as_jint()]; 1925 __ tableswitch(reg, table._first_key, table._last_key, table._branches, table._after); 1926 } else if (opr1->is_single_cpu() || opr1->is_double_cpu()) { 1927 Register reg1 = as_reg(opr1); 1928 if (opr2->is_single_cpu()) { 1929 // cpu register - cpu register 1930 Register reg2 = opr2->as_register(); 1931 if (is_reference_type(opr1->type())) { 1932 __ cmpoop(reg1, reg2); 1933 } else { 1934 assert(!is_reference_type(opr2->type()), "cmp int, oop?"); 1935 __ cmpw(reg1, reg2); 1936 } 1937 return; 1938 } 1939 if (opr2->is_double_cpu()) { 1940 // cpu register - cpu register 1941 Register reg2 = opr2->as_register_lo(); 1942 __ cmp(reg1, reg2); 1943 return; 1944 } 1945 1946 if (opr2->is_constant()) { 1947 bool is_32bit = false; // width of register operand 1948 jlong imm; 1949 1950 switch(opr2->type()) { 1951 case T_INT: 1952 imm = opr2->as_constant_ptr()->as_jint(); 1953 is_32bit = true; 1954 break; 1955 case T_LONG: 1956 imm = opr2->as_constant_ptr()->as_jlong(); 1957 break; 1958 case T_ADDRESS: 1959 imm = opr2->as_constant_ptr()->as_jint(); 1960 break; 1961 case T_METADATA: 1962 imm = (intptr_t)(opr2->as_constant_ptr()->as_metadata()); 1963 break; 1964 case T_OBJECT: 1965 case T_ARRAY: 1966 jobject2reg(opr2->as_constant_ptr()->as_jobject(), rscratch1); 1967 __ cmpoop(reg1, rscratch1); 1968 return; 1969 default: 1970 ShouldNotReachHere(); 1971 imm = 0; // unreachable 1972 break; 1973 } 1974 1975 if (Assembler::operand_valid_for_add_sub_immediate(imm)) { 1976 if (is_32bit) 1977 __ cmpw(reg1, imm); 1978 else 1979 __ subs(zr, reg1, imm); 1980 return; 1981 } else { 1982 __ mov(rscratch1, imm); 1983 if (is_32bit) 1984 __ cmpw(reg1, rscratch1); 1985 else 1986 __ cmp(reg1, rscratch1); 1987 return; 1988 } 1989 } else 1990 ShouldNotReachHere(); 1991 } else if (opr1->is_single_fpu()) { 1992 FloatRegister reg1 = opr1->as_float_reg(); 1993 assert(opr2->is_single_fpu(), "expect single float register"); 1994 FloatRegister reg2 = opr2->as_float_reg(); 1995 __ fcmps(reg1, reg2); 1996 } else if (opr1->is_double_fpu()) { 1997 FloatRegister reg1 = opr1->as_double_reg(); 1998 assert(opr2->is_double_fpu(), "expect double float register"); 1999 FloatRegister reg2 = opr2->as_double_reg(); 2000 __ fcmpd(reg1, reg2); 2001 } else { 2002 ShouldNotReachHere(); 2003 } 2004 } 2005 2006 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op){ 2007 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) { 2008 bool is_unordered_less = (code == lir_ucmp_fd2i); 2009 if (left->is_single_fpu()) { 2010 __ float_cmp(true, is_unordered_less ? -1 : 1, left->as_float_reg(), right->as_float_reg(), dst->as_register()); 2011 } else if (left->is_double_fpu()) { 2012 __ float_cmp(false, is_unordered_less ? -1 : 1, left->as_double_reg(), right->as_double_reg(), dst->as_register()); 2013 } else { 2014 ShouldNotReachHere(); 2015 } 2016 } else if (code == lir_cmp_l2i) { 2017 Label done; 2018 __ cmp(left->as_register_lo(), right->as_register_lo()); 2019 __ mov(dst->as_register(), (uint64_t)-1L); 2020 __ br(Assembler::LT, done); 2021 __ csinc(dst->as_register(), zr, zr, Assembler::EQ); 2022 __ bind(done); 2023 } else { 2024 ShouldNotReachHere(); 2025 } 2026 } 2027 2028 2029 void LIR_Assembler::align_call(LIR_Code code) { } 2030 2031 2032 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) { 2033 address call = __ trampoline_call(Address(op->addr(), rtype)); 2034 if (call == NULL) { 2035 bailout("trampoline stub overflow"); 2036 return; 2037 } 2038 add_call_info(code_offset(), op->info()); 2039 __ post_call_nop(); 2040 } 2041 2042 2043 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) { 2044 address call = __ ic_call(op->addr()); 2045 if (call == NULL) { 2046 bailout("trampoline stub overflow"); 2047 return; 2048 } 2049 add_call_info(code_offset(), op->info()); 2050 __ post_call_nop(); 2051 } 2052 2053 void LIR_Assembler::emit_static_call_stub() { 2054 address call_pc = __ pc(); 2055 address stub = __ start_a_stub(call_stub_size()); 2056 if (stub == NULL) { 2057 bailout("static call stub overflow"); 2058 return; 2059 } 2060 2061 int start = __ offset(); 2062 2063 __ relocate(static_stub_Relocation::spec(call_pc)); 2064 __ emit_static_call_stub(); 2065 2066 assert(__ offset() - start + CompiledStaticCall::to_trampoline_stub_size() 2067 <= call_stub_size(), "stub too big"); 2068 __ end_a_stub(); 2069 } 2070 2071 2072 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) { 2073 assert(exceptionOop->as_register() == r0, "must match"); 2074 assert(exceptionPC->as_register() == r3, "must match"); 2075 2076 // exception object is not added to oop map by LinearScan 2077 // (LinearScan assumes that no oops are in fixed registers) 2078 info->add_register_oop(exceptionOop); 2079 Runtime1::StubID unwind_id; 2080 2081 // get current pc information 2082 // pc is only needed if the method has an exception handler, the unwind code does not need it. 2083 if (compilation()->debug_info_recorder()->last_pc_offset() == __ offset()) { 2084 // As no instructions have been generated yet for this LIR node it's 2085 // possible that an oop map already exists for the current offset. 2086 // In that case insert an dummy NOP here to ensure all oop map PCs 2087 // are unique. See JDK-8237483. 2088 __ nop(); 2089 } 2090 int pc_for_athrow_offset = __ offset(); 2091 InternalAddress pc_for_athrow(__ pc()); 2092 __ adr(exceptionPC->as_register(), pc_for_athrow); 2093 add_call_info(pc_for_athrow_offset, info); // for exception handler 2094 2095 __ verify_not_null_oop(r0); 2096 // search an exception handler (r0: exception oop, r3: throwing pc) 2097 if (compilation()->has_fpu_code()) { 2098 unwind_id = Runtime1::handle_exception_id; 2099 } else { 2100 unwind_id = Runtime1::handle_exception_nofpu_id; 2101 } 2102 __ far_call(RuntimeAddress(Runtime1::entry_for(unwind_id))); 2103 2104 // FIXME: enough room for two byte trap ???? 2105 __ nop(); 2106 } 2107 2108 2109 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) { 2110 assert(exceptionOop->as_register() == r0, "must match"); 2111 2112 __ b(_unwind_handler_entry); 2113 } 2114 2115 2116 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) { 2117 Register lreg = left->is_single_cpu() ? left->as_register() : left->as_register_lo(); 2118 Register dreg = dest->is_single_cpu() ? dest->as_register() : dest->as_register_lo(); 2119 2120 switch (left->type()) { 2121 case T_INT: { 2122 switch (code) { 2123 case lir_shl: __ lslvw (dreg, lreg, count->as_register()); break; 2124 case lir_shr: __ asrvw (dreg, lreg, count->as_register()); break; 2125 case lir_ushr: __ lsrvw (dreg, lreg, count->as_register()); break; 2126 default: 2127 ShouldNotReachHere(); 2128 break; 2129 } 2130 break; 2131 case T_LONG: 2132 case T_ADDRESS: 2133 case T_OBJECT: 2134 switch (code) { 2135 case lir_shl: __ lslv (dreg, lreg, count->as_register()); break; 2136 case lir_shr: __ asrv (dreg, lreg, count->as_register()); break; 2137 case lir_ushr: __ lsrv (dreg, lreg, count->as_register()); break; 2138 default: 2139 ShouldNotReachHere(); 2140 break; 2141 } 2142 break; 2143 default: 2144 ShouldNotReachHere(); 2145 break; 2146 } 2147 } 2148 } 2149 2150 2151 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) { 2152 Register dreg = dest->is_single_cpu() ? dest->as_register() : dest->as_register_lo(); 2153 Register lreg = left->is_single_cpu() ? left->as_register() : left->as_register_lo(); 2154 2155 switch (left->type()) { 2156 case T_INT: { 2157 switch (code) { 2158 case lir_shl: __ lslw (dreg, lreg, count); break; 2159 case lir_shr: __ asrw (dreg, lreg, count); break; 2160 case lir_ushr: __ lsrw (dreg, lreg, count); break; 2161 default: 2162 ShouldNotReachHere(); 2163 break; 2164 } 2165 break; 2166 case T_LONG: 2167 case T_ADDRESS: 2168 case T_OBJECT: 2169 switch (code) { 2170 case lir_shl: __ lsl (dreg, lreg, count); break; 2171 case lir_shr: __ asr (dreg, lreg, count); break; 2172 case lir_ushr: __ lsr (dreg, lreg, count); break; 2173 default: 2174 ShouldNotReachHere(); 2175 break; 2176 } 2177 break; 2178 default: 2179 ShouldNotReachHere(); 2180 break; 2181 } 2182 } 2183 } 2184 2185 2186 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) { 2187 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); 2188 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; 2189 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); 2190 __ str (r, Address(sp, offset_from_rsp_in_bytes)); 2191 } 2192 2193 2194 void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) { 2195 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); 2196 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; 2197 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); 2198 __ mov (rscratch1, c); 2199 __ str (rscratch1, Address(sp, offset_from_rsp_in_bytes)); 2200 } 2201 2202 2203 void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) { 2204 ShouldNotReachHere(); 2205 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); 2206 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; 2207 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); 2208 __ lea(rscratch1, __ constant_oop_address(o)); 2209 __ str(rscratch1, Address(sp, offset_from_rsp_in_bytes)); 2210 } 2211 2212 2213 // This code replaces a call to arraycopy; no exception may 2214 // be thrown in this code, they must be thrown in the System.arraycopy 2215 // activation frame; we could save some checks if this would not be the case 2216 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) { 2217 ciArrayKlass* default_type = op->expected_type(); 2218 Register src = op->src()->as_register(); 2219 Register dst = op->dst()->as_register(); 2220 Register src_pos = op->src_pos()->as_register(); 2221 Register dst_pos = op->dst_pos()->as_register(); 2222 Register length = op->length()->as_register(); 2223 Register tmp = op->tmp()->as_register(); 2224 2225 CodeStub* stub = op->stub(); 2226 int flags = op->flags(); 2227 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL; 2228 if (is_reference_type(basic_type)) basic_type = T_OBJECT; 2229 2230 // if we don't know anything, just go through the generic arraycopy 2231 if (default_type == NULL // || basic_type == T_OBJECT 2232 ) { 2233 Label done; 2234 assert(src == r1 && src_pos == r2, "mismatch in calling convention"); 2235 2236 // Save the arguments in case the generic arraycopy fails and we 2237 // have to fall back to the JNI stub 2238 __ stp(dst, dst_pos, Address(sp, 0*BytesPerWord)); 2239 __ stp(length, src_pos, Address(sp, 2*BytesPerWord)); 2240 __ str(src, Address(sp, 4*BytesPerWord)); 2241 2242 address copyfunc_addr = StubRoutines::generic_arraycopy(); 2243 assert(copyfunc_addr != NULL, "generic arraycopy stub required"); 2244 2245 // The arguments are in java calling convention so we shift them 2246 // to C convention 2247 assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4); 2248 __ mov(c_rarg0, j_rarg0); 2249 assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4); 2250 __ mov(c_rarg1, j_rarg1); 2251 assert_different_registers(c_rarg2, j_rarg3, j_rarg4); 2252 __ mov(c_rarg2, j_rarg2); 2253 assert_different_registers(c_rarg3, j_rarg4); 2254 __ mov(c_rarg3, j_rarg3); 2255 __ mov(c_rarg4, j_rarg4); 2256 #ifndef PRODUCT 2257 if (PrintC1Statistics) { 2258 __ incrementw(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt)); 2259 } 2260 #endif 2261 __ far_call(RuntimeAddress(copyfunc_addr)); 2262 2263 __ cbz(r0, *stub->continuation()); 2264 2265 // Reload values from the stack so they are where the stub 2266 // expects them. 2267 __ ldp(dst, dst_pos, Address(sp, 0*BytesPerWord)); 2268 __ ldp(length, src_pos, Address(sp, 2*BytesPerWord)); 2269 __ ldr(src, Address(sp, 4*BytesPerWord)); 2270 2271 // r0 is -1^K where K == partial copied count 2272 __ eonw(rscratch1, r0, zr); 2273 // adjust length down and src/end pos up by partial copied count 2274 __ subw(length, length, rscratch1); 2275 __ addw(src_pos, src_pos, rscratch1); 2276 __ addw(dst_pos, dst_pos, rscratch1); 2277 __ b(*stub->entry()); 2278 2279 __ bind(*stub->continuation()); 2280 return; 2281 } 2282 2283 assert(default_type != NULL && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point"); 2284 2285 int elem_size = type2aelembytes(basic_type); 2286 int scale = exact_log2(elem_size); 2287 2288 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes()); 2289 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes()); 2290 Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes()); 2291 Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes()); 2292 2293 // test for NULL 2294 if (flags & LIR_OpArrayCopy::src_null_check) { 2295 __ cbz(src, *stub->entry()); 2296 } 2297 if (flags & LIR_OpArrayCopy::dst_null_check) { 2298 __ cbz(dst, *stub->entry()); 2299 } 2300 2301 // If the compiler was not able to prove that exact type of the source or the destination 2302 // of the arraycopy is an array type, check at runtime if the source or the destination is 2303 // an instance type. 2304 if (flags & LIR_OpArrayCopy::type_check) { 2305 if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::dst_objarray)) { 2306 __ load_klass(tmp, dst); 2307 __ ldrw(rscratch1, Address(tmp, in_bytes(Klass::layout_helper_offset()))); 2308 __ cmpw(rscratch1, Klass::_lh_neutral_value); 2309 __ br(Assembler::GE, *stub->entry()); 2310 } 2311 2312 if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::src_objarray)) { 2313 __ load_klass(tmp, src); 2314 __ ldrw(rscratch1, Address(tmp, in_bytes(Klass::layout_helper_offset()))); 2315 __ cmpw(rscratch1, Klass::_lh_neutral_value); 2316 __ br(Assembler::GE, *stub->entry()); 2317 } 2318 } 2319 2320 // check if negative 2321 if (flags & LIR_OpArrayCopy::src_pos_positive_check) { 2322 __ cmpw(src_pos, 0); 2323 __ br(Assembler::LT, *stub->entry()); 2324 } 2325 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) { 2326 __ cmpw(dst_pos, 0); 2327 __ br(Assembler::LT, *stub->entry()); 2328 } 2329 2330 if (flags & LIR_OpArrayCopy::length_positive_check) { 2331 __ cmpw(length, 0); 2332 __ br(Assembler::LT, *stub->entry()); 2333 } 2334 2335 if (flags & LIR_OpArrayCopy::src_range_check) { 2336 __ addw(tmp, src_pos, length); 2337 __ ldrw(rscratch1, src_length_addr); 2338 __ cmpw(tmp, rscratch1); 2339 __ br(Assembler::HI, *stub->entry()); 2340 } 2341 if (flags & LIR_OpArrayCopy::dst_range_check) { 2342 __ addw(tmp, dst_pos, length); 2343 __ ldrw(rscratch1, dst_length_addr); 2344 __ cmpw(tmp, rscratch1); 2345 __ br(Assembler::HI, *stub->entry()); 2346 } 2347 2348 if (flags & LIR_OpArrayCopy::type_check) { 2349 // We don't know the array types are compatible 2350 if (basic_type != T_OBJECT) { 2351 // Simple test for basic type arrays 2352 if (UseCompressedClassPointers) { 2353 __ ldrw(tmp, src_klass_addr); 2354 __ ldrw(rscratch1, dst_klass_addr); 2355 __ cmpw(tmp, rscratch1); 2356 } else { 2357 __ ldr(tmp, src_klass_addr); 2358 __ ldr(rscratch1, dst_klass_addr); 2359 __ cmp(tmp, rscratch1); 2360 } 2361 __ br(Assembler::NE, *stub->entry()); 2362 } else { 2363 // For object arrays, if src is a sub class of dst then we can 2364 // safely do the copy. 2365 Label cont, slow; 2366 2367 #define PUSH(r1, r2) \ 2368 stp(r1, r2, __ pre(sp, -2 * wordSize)); 2369 2370 #define POP(r1, r2) \ 2371 ldp(r1, r2, __ post(sp, 2 * wordSize)); 2372 2373 __ PUSH(src, dst); 2374 2375 __ load_klass(src, src); 2376 __ load_klass(dst, dst); 2377 2378 __ check_klass_subtype_fast_path(src, dst, tmp, &cont, &slow, NULL); 2379 2380 __ PUSH(src, dst); 2381 __ far_call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); 2382 __ POP(src, dst); 2383 2384 __ cbnz(src, cont); 2385 2386 __ bind(slow); 2387 __ POP(src, dst); 2388 2389 address copyfunc_addr = StubRoutines::checkcast_arraycopy(); 2390 if (copyfunc_addr != NULL) { // use stub if available 2391 // src is not a sub class of dst so we have to do a 2392 // per-element check. 2393 2394 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray; 2395 if ((flags & mask) != mask) { 2396 // Check that at least both of them object arrays. 2397 assert(flags & mask, "one of the two should be known to be an object array"); 2398 2399 if (!(flags & LIR_OpArrayCopy::src_objarray)) { 2400 __ load_klass(tmp, src); 2401 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) { 2402 __ load_klass(tmp, dst); 2403 } 2404 int lh_offset = in_bytes(Klass::layout_helper_offset()); 2405 Address klass_lh_addr(tmp, lh_offset); 2406 jint objArray_lh = Klass::array_layout_helper(T_OBJECT); 2407 __ ldrw(rscratch1, klass_lh_addr); 2408 __ mov(rscratch2, objArray_lh); 2409 __ eorw(rscratch1, rscratch1, rscratch2); 2410 __ cbnzw(rscratch1, *stub->entry()); 2411 } 2412 2413 // Spill because stubs can use any register they like and it's 2414 // easier to restore just those that we care about. 2415 __ stp(dst, dst_pos, Address(sp, 0*BytesPerWord)); 2416 __ stp(length, src_pos, Address(sp, 2*BytesPerWord)); 2417 __ str(src, Address(sp, 4*BytesPerWord)); 2418 2419 __ lea(c_rarg0, Address(src, src_pos, Address::uxtw(scale))); 2420 __ add(c_rarg0, c_rarg0, arrayOopDesc::base_offset_in_bytes(basic_type)); 2421 assert_different_registers(c_rarg0, dst, dst_pos, length); 2422 __ lea(c_rarg1, Address(dst, dst_pos, Address::uxtw(scale))); 2423 __ add(c_rarg1, c_rarg1, arrayOopDesc::base_offset_in_bytes(basic_type)); 2424 assert_different_registers(c_rarg1, dst, length); 2425 __ uxtw(c_rarg2, length); 2426 assert_different_registers(c_rarg2, dst); 2427 2428 __ load_klass(c_rarg4, dst); 2429 __ ldr(c_rarg4, Address(c_rarg4, ObjArrayKlass::element_klass_offset())); 2430 __ ldrw(c_rarg3, Address(c_rarg4, Klass::super_check_offset_offset())); 2431 __ far_call(RuntimeAddress(copyfunc_addr)); 2432 2433 #ifndef PRODUCT 2434 if (PrintC1Statistics) { 2435 Label failed; 2436 __ cbnz(r0, failed); 2437 __ incrementw(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt)); 2438 __ bind(failed); 2439 } 2440 #endif 2441 2442 __ cbz(r0, *stub->continuation()); 2443 2444 #ifndef PRODUCT 2445 if (PrintC1Statistics) { 2446 __ incrementw(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt)); 2447 } 2448 #endif 2449 assert_different_registers(dst, dst_pos, length, src_pos, src, r0, rscratch1); 2450 2451 // Restore previously spilled arguments 2452 __ ldp(dst, dst_pos, Address(sp, 0*BytesPerWord)); 2453 __ ldp(length, src_pos, Address(sp, 2*BytesPerWord)); 2454 __ ldr(src, Address(sp, 4*BytesPerWord)); 2455 2456 // return value is -1^K where K is partial copied count 2457 __ eonw(rscratch1, r0, zr); 2458 // adjust length down and src/end pos up by partial copied count 2459 __ subw(length, length, rscratch1); 2460 __ addw(src_pos, src_pos, rscratch1); 2461 __ addw(dst_pos, dst_pos, rscratch1); 2462 } 2463 2464 __ b(*stub->entry()); 2465 2466 __ bind(cont); 2467 __ POP(src, dst); 2468 } 2469 } 2470 2471 #ifdef ASSERT 2472 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) { 2473 // Sanity check the known type with the incoming class. For the 2474 // primitive case the types must match exactly with src.klass and 2475 // dst.klass each exactly matching the default type. For the 2476 // object array case, if no type check is needed then either the 2477 // dst type is exactly the expected type and the src type is a 2478 // subtype which we can't check or src is the same array as dst 2479 // but not necessarily exactly of type default_type. 2480 Label known_ok, halt; 2481 __ mov_metadata(tmp, default_type->constant_encoding()); 2482 if (UseCompressedClassPointers) { 2483 __ encode_klass_not_null(tmp); 2484 } 2485 2486 if (basic_type != T_OBJECT) { 2487 2488 if (UseCompressedClassPointers) { 2489 __ ldrw(rscratch1, dst_klass_addr); 2490 __ cmpw(tmp, rscratch1); 2491 } else { 2492 __ ldr(rscratch1, dst_klass_addr); 2493 __ cmp(tmp, rscratch1); 2494 } 2495 __ br(Assembler::NE, halt); 2496 if (UseCompressedClassPointers) { 2497 __ ldrw(rscratch1, src_klass_addr); 2498 __ cmpw(tmp, rscratch1); 2499 } else { 2500 __ ldr(rscratch1, src_klass_addr); 2501 __ cmp(tmp, rscratch1); 2502 } 2503 __ br(Assembler::EQ, known_ok); 2504 } else { 2505 if (UseCompressedClassPointers) { 2506 __ ldrw(rscratch1, dst_klass_addr); 2507 __ cmpw(tmp, rscratch1); 2508 } else { 2509 __ ldr(rscratch1, dst_klass_addr); 2510 __ cmp(tmp, rscratch1); 2511 } 2512 __ br(Assembler::EQ, known_ok); 2513 __ cmp(src, dst); 2514 __ br(Assembler::EQ, known_ok); 2515 } 2516 __ bind(halt); 2517 __ stop("incorrect type information in arraycopy"); 2518 __ bind(known_ok); 2519 } 2520 #endif 2521 2522 #ifndef PRODUCT 2523 if (PrintC1Statistics) { 2524 __ incrementw(ExternalAddress(Runtime1::arraycopy_count_address(basic_type))); 2525 } 2526 #endif 2527 2528 __ lea(c_rarg0, Address(src, src_pos, Address::uxtw(scale))); 2529 __ add(c_rarg0, c_rarg0, arrayOopDesc::base_offset_in_bytes(basic_type)); 2530 assert_different_registers(c_rarg0, dst, dst_pos, length); 2531 __ lea(c_rarg1, Address(dst, dst_pos, Address::uxtw(scale))); 2532 __ add(c_rarg1, c_rarg1, arrayOopDesc::base_offset_in_bytes(basic_type)); 2533 assert_different_registers(c_rarg1, dst, length); 2534 __ uxtw(c_rarg2, length); 2535 assert_different_registers(c_rarg2, dst); 2536 2537 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0; 2538 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0; 2539 const char *name; 2540 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false); 2541 2542 CodeBlob *cb = CodeCache::find_blob(entry); 2543 if (cb) { 2544 __ far_call(RuntimeAddress(entry)); 2545 } else { 2546 __ call_VM_leaf(entry, 3); 2547 } 2548 2549 __ bind(*stub->continuation()); 2550 } 2551 2552 2553 2554 2555 void LIR_Assembler::emit_lock(LIR_OpLock* op) { 2556 Register obj = op->obj_opr()->as_register(); // may not be an oop 2557 Register hdr = op->hdr_opr()->as_register(); 2558 Register lock = op->lock_opr()->as_register(); 2559 if (UseHeavyMonitors) { 2560 if (op->info() != NULL) { 2561 add_debug_info_for_null_check_here(op->info()); 2562 __ null_check(obj, -1); 2563 } 2564 __ b(*op->stub()->entry()); 2565 } else if (op->code() == lir_lock) { 2566 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); 2567 // add debug info for NullPointerException only if one is possible 2568 int null_check_offset = __ lock_object(hdr, obj, lock, *op->stub()->entry()); 2569 if (op->info() != NULL) { 2570 add_debug_info_for_null_check(null_check_offset, op->info()); 2571 } 2572 // done 2573 } else if (op->code() == lir_unlock) { 2574 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); 2575 __ unlock_object(hdr, obj, lock, *op->stub()->entry()); 2576 } else { 2577 Unimplemented(); 2578 } 2579 __ bind(*op->stub()->continuation()); 2580 } 2581 2582 void LIR_Assembler::emit_load_klass(LIR_OpLoadKlass* op) { 2583 Register obj = op->obj()->as_pointer_register(); 2584 Register result = op->result_opr()->as_pointer_register(); 2585 2586 CodeEmitInfo* info = op->info(); 2587 if (info != NULL) { 2588 add_debug_info_for_null_check_here(info); 2589 } 2590 2591 if (UseCompressedClassPointers) { 2592 __ ldrw(result, Address (obj, oopDesc::klass_offset_in_bytes())); 2593 __ decode_klass_not_null(result); 2594 } else { 2595 __ ldr(result, Address (obj, oopDesc::klass_offset_in_bytes())); 2596 } 2597 } 2598 2599 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) { 2600 ciMethod* method = op->profiled_method(); 2601 int bci = op->profiled_bci(); 2602 ciMethod* callee = op->profiled_callee(); 2603 2604 // Update counter for all call types 2605 ciMethodData* md = method->method_data_or_null(); 2606 assert(md != NULL, "Sanity"); 2607 ciProfileData* data = md->bci_to_data(bci); 2608 assert(data != NULL && data->is_CounterData(), "need CounterData for calls"); 2609 assert(op->mdo()->is_single_cpu(), "mdo must be allocated"); 2610 Register mdo = op->mdo()->as_register(); 2611 __ mov_metadata(mdo, md->constant_encoding()); 2612 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset())); 2613 // Perform additional virtual call profiling for invokevirtual and 2614 // invokeinterface bytecodes 2615 if (op->should_profile_receiver_type()) { 2616 assert(op->recv()->is_single_cpu(), "recv must be allocated"); 2617 Register recv = op->recv()->as_register(); 2618 assert_different_registers(mdo, recv); 2619 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls"); 2620 ciKlass* known_klass = op->known_holder(); 2621 if (C1OptimizeVirtualCallProfiling && known_klass != NULL) { 2622 // We know the type that will be seen at this call site; we can 2623 // statically update the MethodData* rather than needing to do 2624 // dynamic tests on the receiver type 2625 2626 // NOTE: we should probably put a lock around this search to 2627 // avoid collisions by concurrent compilations 2628 ciVirtualCallData* vc_data = (ciVirtualCallData*) data; 2629 uint i; 2630 for (i = 0; i < VirtualCallData::row_limit(); i++) { 2631 ciKlass* receiver = vc_data->receiver(i); 2632 if (known_klass->equals(receiver)) { 2633 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i))); 2634 __ addptr(data_addr, DataLayout::counter_increment); 2635 return; 2636 } 2637 } 2638 2639 // Receiver type not found in profile data; select an empty slot 2640 2641 // Note that this is less efficient than it should be because it 2642 // always does a write to the receiver part of the 2643 // VirtualCallData rather than just the first time 2644 for (i = 0; i < VirtualCallData::row_limit(); i++) { 2645 ciKlass* receiver = vc_data->receiver(i); 2646 if (receiver == NULL) { 2647 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i))); 2648 __ mov_metadata(rscratch1, known_klass->constant_encoding()); 2649 __ lea(rscratch2, recv_addr); 2650 __ str(rscratch1, Address(rscratch2)); 2651 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i))); 2652 __ addptr(data_addr, DataLayout::counter_increment); 2653 return; 2654 } 2655 } 2656 } else { 2657 __ load_klass(recv, recv); 2658 Label update_done; 2659 type_profile_helper(mdo, md, data, recv, &update_done); 2660 // Receiver did not match any saved receiver and there is no empty row for it. 2661 // Increment total counter to indicate polymorphic case. 2662 __ addptr(counter_addr, DataLayout::counter_increment); 2663 2664 __ bind(update_done); 2665 } 2666 } else { 2667 // Static call 2668 __ addptr(counter_addr, DataLayout::counter_increment); 2669 } 2670 } 2671 2672 2673 void LIR_Assembler::emit_delay(LIR_OpDelay*) { 2674 Unimplemented(); 2675 } 2676 2677 2678 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) { 2679 __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no)); 2680 } 2681 2682 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) { 2683 assert(op->crc()->is_single_cpu(), "crc must be register"); 2684 assert(op->val()->is_single_cpu(), "byte value must be register"); 2685 assert(op->result_opr()->is_single_cpu(), "result must be register"); 2686 Register crc = op->crc()->as_register(); 2687 Register val = op->val()->as_register(); 2688 Register res = op->result_opr()->as_register(); 2689 2690 assert_different_registers(val, crc, res); 2691 uint64_t offset; 2692 __ adrp(res, ExternalAddress(StubRoutines::crc_table_addr()), offset); 2693 __ add(res, res, offset); 2694 2695 __ mvnw(crc, crc); // ~crc 2696 __ update_byte_crc32(crc, val, res); 2697 __ mvnw(res, crc); // ~crc 2698 } 2699 2700 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) { 2701 COMMENT("emit_profile_type {"); 2702 Register obj = op->obj()->as_register(); 2703 Register tmp = op->tmp()->as_pointer_register(); 2704 Address mdo_addr = as_Address(op->mdp()->as_address_ptr()); 2705 ciKlass* exact_klass = op->exact_klass(); 2706 intptr_t current_klass = op->current_klass(); 2707 bool not_null = op->not_null(); 2708 bool no_conflict = op->no_conflict(); 2709 2710 Label update, next, none; 2711 2712 bool do_null = !not_null; 2713 bool exact_klass_set = exact_klass != NULL && ciTypeEntries::valid_ciklass(current_klass) == exact_klass; 2714 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set; 2715 2716 assert(do_null || do_update, "why are we here?"); 2717 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?"); 2718 assert(mdo_addr.base() != rscratch1, "wrong register"); 2719 2720 __ verify_oop(obj); 2721 2722 if (tmp != obj) { 2723 __ mov(tmp, obj); 2724 } 2725 if (do_null) { 2726 __ cbnz(tmp, update); 2727 if (!TypeEntries::was_null_seen(current_klass)) { 2728 __ ldr(rscratch2, mdo_addr); 2729 __ orr(rscratch2, rscratch2, TypeEntries::null_seen); 2730 __ str(rscratch2, mdo_addr); 2731 } 2732 if (do_update) { 2733 #ifndef ASSERT 2734 __ b(next); 2735 } 2736 #else 2737 __ b(next); 2738 } 2739 } else { 2740 __ cbnz(tmp, update); 2741 __ stop("unexpected null obj"); 2742 #endif 2743 } 2744 2745 __ bind(update); 2746 2747 if (do_update) { 2748 #ifdef ASSERT 2749 if (exact_klass != NULL) { 2750 Label ok; 2751 __ load_klass(tmp, tmp); 2752 __ mov_metadata(rscratch1, exact_klass->constant_encoding()); 2753 __ eor(rscratch1, tmp, rscratch1); 2754 __ cbz(rscratch1, ok); 2755 __ stop("exact klass and actual klass differ"); 2756 __ bind(ok); 2757 } 2758 #endif 2759 if (!no_conflict) { 2760 if (exact_klass == NULL || TypeEntries::is_type_none(current_klass)) { 2761 if (exact_klass != NULL) { 2762 __ mov_metadata(tmp, exact_klass->constant_encoding()); 2763 } else { 2764 __ load_klass(tmp, tmp); 2765 } 2766 2767 __ ldr(rscratch2, mdo_addr); 2768 __ eor(tmp, tmp, rscratch2); 2769 __ andr(rscratch1, tmp, TypeEntries::type_klass_mask); 2770 // klass seen before, nothing to do. The unknown bit may have been 2771 // set already but no need to check. 2772 __ cbz(rscratch1, next); 2773 2774 __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore. 2775 2776 if (TypeEntries::is_type_none(current_klass)) { 2777 __ cbz(rscratch2, none); 2778 __ cmp(rscratch2, (u1)TypeEntries::null_seen); 2779 __ br(Assembler::EQ, none); 2780 // There is a chance that the checks above (re-reading profiling 2781 // data from memory) fail if another thread has just set the 2782 // profiling to this obj's klass 2783 __ dmb(Assembler::ISHLD); 2784 __ ldr(rscratch2, mdo_addr); 2785 __ eor(tmp, tmp, rscratch2); 2786 __ andr(rscratch1, tmp, TypeEntries::type_klass_mask); 2787 __ cbz(rscratch1, next); 2788 } 2789 } else { 2790 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL && 2791 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only"); 2792 2793 __ ldr(tmp, mdo_addr); 2794 __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore. 2795 } 2796 2797 // different than before. Cannot keep accurate profile. 2798 __ ldr(rscratch2, mdo_addr); 2799 __ orr(rscratch2, rscratch2, TypeEntries::type_unknown); 2800 __ str(rscratch2, mdo_addr); 2801 2802 if (TypeEntries::is_type_none(current_klass)) { 2803 __ b(next); 2804 2805 __ bind(none); 2806 // first time here. Set profile type. 2807 __ str(tmp, mdo_addr); 2808 } 2809 } else { 2810 // There's a single possible klass at this profile point 2811 assert(exact_klass != NULL, "should be"); 2812 if (TypeEntries::is_type_none(current_klass)) { 2813 __ mov_metadata(tmp, exact_klass->constant_encoding()); 2814 __ ldr(rscratch2, mdo_addr); 2815 __ eor(tmp, tmp, rscratch2); 2816 __ andr(rscratch1, tmp, TypeEntries::type_klass_mask); 2817 __ cbz(rscratch1, next); 2818 #ifdef ASSERT 2819 { 2820 Label ok; 2821 __ ldr(rscratch1, mdo_addr); 2822 __ cbz(rscratch1, ok); 2823 __ cmp(rscratch1, (u1)TypeEntries::null_seen); 2824 __ br(Assembler::EQ, ok); 2825 // may have been set by another thread 2826 __ dmb(Assembler::ISHLD); 2827 __ mov_metadata(rscratch1, exact_klass->constant_encoding()); 2828 __ ldr(rscratch2, mdo_addr); 2829 __ eor(rscratch2, rscratch1, rscratch2); 2830 __ andr(rscratch2, rscratch2, TypeEntries::type_mask); 2831 __ cbz(rscratch2, ok); 2832 2833 __ stop("unexpected profiling mismatch"); 2834 __ bind(ok); 2835 } 2836 #endif 2837 // first time here. Set profile type. 2838 __ str(tmp, mdo_addr); 2839 } else { 2840 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL && 2841 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent"); 2842 2843 __ ldr(tmp, mdo_addr); 2844 __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore. 2845 2846 __ orr(tmp, tmp, TypeEntries::type_unknown); 2847 __ str(tmp, mdo_addr); 2848 // FIXME: Write barrier needed here? 2849 } 2850 } 2851 2852 __ bind(next); 2853 } 2854 COMMENT("} emit_profile_type"); 2855 } 2856 2857 2858 void LIR_Assembler::align_backward_branch_target() { 2859 } 2860 2861 2862 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) { 2863 // tmp must be unused 2864 assert(tmp->is_illegal(), "wasting a register if tmp is allocated"); 2865 2866 if (left->is_single_cpu()) { 2867 assert(dest->is_single_cpu(), "expect single result reg"); 2868 __ negw(dest->as_register(), left->as_register()); 2869 } else if (left->is_double_cpu()) { 2870 assert(dest->is_double_cpu(), "expect double result reg"); 2871 __ neg(dest->as_register_lo(), left->as_register_lo()); 2872 } else if (left->is_single_fpu()) { 2873 assert(dest->is_single_fpu(), "expect single float result reg"); 2874 __ fnegs(dest->as_float_reg(), left->as_float_reg()); 2875 } else { 2876 assert(left->is_double_fpu(), "expect double float operand reg"); 2877 assert(dest->is_double_fpu(), "expect double float result reg"); 2878 __ fnegd(dest->as_double_reg(), left->as_double_reg()); 2879 } 2880 } 2881 2882 2883 void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) { 2884 if (patch_code != lir_patch_none) { 2885 deoptimize_trap(info); 2886 return; 2887 } 2888 2889 __ lea(dest->as_register_lo(), as_Address(addr->as_address_ptr())); 2890 } 2891 2892 2893 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) { 2894 assert(!tmp->is_valid(), "don't need temporary"); 2895 2896 CodeBlob *cb = CodeCache::find_blob(dest); 2897 if (cb) { 2898 __ far_call(RuntimeAddress(dest)); 2899 } else { 2900 __ mov(rscratch1, RuntimeAddress(dest)); 2901 __ blr(rscratch1); 2902 } 2903 2904 if (info != NULL) { 2905 add_call_info_here(info); 2906 } 2907 __ post_call_nop(); 2908 } 2909 2910 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) { 2911 if (dest->is_address() || src->is_address()) { 2912 move_op(src, dest, type, lir_patch_none, info, 2913 /*pop_fpu_stack*/false, /*wide*/false); 2914 } else { 2915 ShouldNotReachHere(); 2916 } 2917 } 2918 2919 #ifdef ASSERT 2920 // emit run-time assertion 2921 void LIR_Assembler::emit_assert(LIR_OpAssert* op) { 2922 assert(op->code() == lir_assert, "must be"); 2923 2924 if (op->in_opr1()->is_valid()) { 2925 assert(op->in_opr2()->is_valid(), "both operands must be valid"); 2926 comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op); 2927 } else { 2928 assert(op->in_opr2()->is_illegal(), "both operands must be illegal"); 2929 assert(op->condition() == lir_cond_always, "no other conditions allowed"); 2930 } 2931 2932 Label ok; 2933 if (op->condition() != lir_cond_always) { 2934 Assembler::Condition acond = Assembler::AL; 2935 switch (op->condition()) { 2936 case lir_cond_equal: acond = Assembler::EQ; break; 2937 case lir_cond_notEqual: acond = Assembler::NE; break; 2938 case lir_cond_less: acond = Assembler::LT; break; 2939 case lir_cond_lessEqual: acond = Assembler::LE; break; 2940 case lir_cond_greaterEqual: acond = Assembler::GE; break; 2941 case lir_cond_greater: acond = Assembler::GT; break; 2942 case lir_cond_belowEqual: acond = Assembler::LS; break; 2943 case lir_cond_aboveEqual: acond = Assembler::HS; break; 2944 default: ShouldNotReachHere(); 2945 } 2946 __ br(acond, ok); 2947 } 2948 if (op->halt()) { 2949 const char* str = __ code_string(op->msg()); 2950 __ stop(str); 2951 } else { 2952 breakpoint(); 2953 } 2954 __ bind(ok); 2955 } 2956 #endif 2957 2958 #ifndef PRODUCT 2959 #define COMMENT(x) do { __ block_comment(x); } while (0) 2960 #else 2961 #define COMMENT(x) 2962 #endif 2963 2964 void LIR_Assembler::membar() { 2965 COMMENT("membar"); 2966 __ membar(MacroAssembler::AnyAny); 2967 } 2968 2969 void LIR_Assembler::membar_acquire() { 2970 __ membar(Assembler::LoadLoad|Assembler::LoadStore); 2971 } 2972 2973 void LIR_Assembler::membar_release() { 2974 __ membar(Assembler::LoadStore|Assembler::StoreStore); 2975 } 2976 2977 void LIR_Assembler::membar_loadload() { 2978 __ membar(Assembler::LoadLoad); 2979 } 2980 2981 void LIR_Assembler::membar_storestore() { 2982 __ membar(MacroAssembler::StoreStore); 2983 } 2984 2985 void LIR_Assembler::membar_loadstore() { __ membar(MacroAssembler::LoadStore); } 2986 2987 void LIR_Assembler::membar_storeload() { __ membar(MacroAssembler::StoreLoad); } 2988 2989 void LIR_Assembler::on_spin_wait() { 2990 __ spin_wait(); 2991 } 2992 2993 void LIR_Assembler::get_thread(LIR_Opr result_reg) { 2994 __ mov(result_reg->as_register(), rthread); 2995 } 2996 2997 2998 void LIR_Assembler::peephole(LIR_List *lir) { 2999 #if 0 3000 if (tableswitch_count >= max_tableswitches) 3001 return; 3002 3003 /* 3004 This finite-state automaton recognizes sequences of compare-and- 3005 branch instructions. We will turn them into a tableswitch. You 3006 could argue that C1 really shouldn't be doing this sort of 3007 optimization, but without it the code is really horrible. 3008 */ 3009 3010 enum { start_s, cmp1_s, beq_s, cmp_s } state; 3011 int first_key, last_key = -2147483648; 3012 int next_key = 0; 3013 int start_insn = -1; 3014 int last_insn = -1; 3015 Register reg = noreg; 3016 LIR_Opr reg_opr; 3017 state = start_s; 3018 3019 LIR_OpList* inst = lir->instructions_list(); 3020 for (int i = 0; i < inst->length(); i++) { 3021 LIR_Op* op = inst->at(i); 3022 switch (state) { 3023 case start_s: 3024 first_key = -1; 3025 start_insn = i; 3026 switch (op->code()) { 3027 case lir_cmp: 3028 LIR_Opr opr1 = op->as_Op2()->in_opr1(); 3029 LIR_Opr opr2 = op->as_Op2()->in_opr2(); 3030 if (opr1->is_cpu_register() && opr1->is_single_cpu() 3031 && opr2->is_constant() 3032 && opr2->type() == T_INT) { 3033 reg_opr = opr1; 3034 reg = opr1->as_register(); 3035 first_key = opr2->as_constant_ptr()->as_jint(); 3036 next_key = first_key + 1; 3037 state = cmp_s; 3038 goto next_state; 3039 } 3040 break; 3041 } 3042 break; 3043 case cmp_s: 3044 switch (op->code()) { 3045 case lir_branch: 3046 if (op->as_OpBranch()->cond() == lir_cond_equal) { 3047 state = beq_s; 3048 last_insn = i; 3049 goto next_state; 3050 } 3051 } 3052 state = start_s; 3053 break; 3054 case beq_s: 3055 switch (op->code()) { 3056 case lir_cmp: { 3057 LIR_Opr opr1 = op->as_Op2()->in_opr1(); 3058 LIR_Opr opr2 = op->as_Op2()->in_opr2(); 3059 if (opr1->is_cpu_register() && opr1->is_single_cpu() 3060 && opr1->as_register() == reg 3061 && opr2->is_constant() 3062 && opr2->type() == T_INT 3063 && opr2->as_constant_ptr()->as_jint() == next_key) { 3064 last_key = next_key; 3065 next_key++; 3066 state = cmp_s; 3067 goto next_state; 3068 } 3069 } 3070 } 3071 last_key = next_key; 3072 state = start_s; 3073 break; 3074 default: 3075 assert(false, "impossible state"); 3076 } 3077 if (state == start_s) { 3078 if (first_key < last_key - 5L && reg != noreg) { 3079 { 3080 // printf("found run register %d starting at insn %d low value %d high value %d\n", 3081 // reg->encoding(), 3082 // start_insn, first_key, last_key); 3083 // for (int i = 0; i < inst->length(); i++) { 3084 // inst->at(i)->print(); 3085 // tty->print("\n"); 3086 // } 3087 // tty->print("\n"); 3088 } 3089 3090 struct tableswitch *sw = &switches[tableswitch_count]; 3091 sw->_insn_index = start_insn, sw->_first_key = first_key, 3092 sw->_last_key = last_key, sw->_reg = reg; 3093 inst->insert_before(last_insn + 1, new LIR_OpLabel(&sw->_after)); 3094 { 3095 // Insert the new table of branches 3096 int offset = last_insn; 3097 for (int n = first_key; n < last_key; n++) { 3098 inst->insert_before 3099 (last_insn + 1, 3100 new LIR_OpBranch(lir_cond_always, T_ILLEGAL, 3101 inst->at(offset)->as_OpBranch()->label())); 3102 offset -= 2, i++; 3103 } 3104 } 3105 // Delete all the old compare-and-branch instructions 3106 for (int n = first_key; n < last_key; n++) { 3107 inst->remove_at(start_insn); 3108 inst->remove_at(start_insn); 3109 } 3110 // Insert the tableswitch instruction 3111 inst->insert_before(start_insn, 3112 new LIR_Op2(lir_cmp, lir_cond_always, 3113 LIR_OprFact::intConst(tableswitch_count), 3114 reg_opr)); 3115 inst->insert_before(start_insn + 1, new LIR_OpLabel(&sw->_branches)); 3116 tableswitch_count++; 3117 } 3118 reg = noreg; 3119 last_key = -2147483648; 3120 } 3121 next_state: 3122 ; 3123 } 3124 #endif 3125 } 3126 3127 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp_op) { 3128 Address addr = as_Address(src->as_address_ptr()); 3129 BasicType type = src->type(); 3130 bool is_oop = is_reference_type(type); 3131 3132 void (MacroAssembler::* add)(Register prev, RegisterOrConstant incr, Register addr); 3133 void (MacroAssembler::* xchg)(Register prev, Register newv, Register addr); 3134 3135 switch(type) { 3136 case T_INT: 3137 xchg = &MacroAssembler::atomic_xchgalw; 3138 add = &MacroAssembler::atomic_addalw; 3139 break; 3140 case T_LONG: 3141 xchg = &MacroAssembler::atomic_xchgal; 3142 add = &MacroAssembler::atomic_addal; 3143 break; 3144 case T_OBJECT: 3145 case T_ARRAY: 3146 if (UseCompressedOops) { 3147 xchg = &MacroAssembler::atomic_xchgalw; 3148 add = &MacroAssembler::atomic_addalw; 3149 } else { 3150 xchg = &MacroAssembler::atomic_xchgal; 3151 add = &MacroAssembler::atomic_addal; 3152 } 3153 break; 3154 default: 3155 ShouldNotReachHere(); 3156 xchg = &MacroAssembler::atomic_xchgal; 3157 add = &MacroAssembler::atomic_addal; // unreachable 3158 } 3159 3160 switch (code) { 3161 case lir_xadd: 3162 { 3163 RegisterOrConstant inc; 3164 Register tmp = as_reg(tmp_op); 3165 Register dst = as_reg(dest); 3166 if (data->is_constant()) { 3167 inc = RegisterOrConstant(as_long(data)); 3168 assert_different_registers(dst, addr.base(), tmp, 3169 rscratch1, rscratch2); 3170 } else { 3171 inc = RegisterOrConstant(as_reg(data)); 3172 assert_different_registers(inc.as_register(), dst, addr.base(), tmp, 3173 rscratch1, rscratch2); 3174 } 3175 __ lea(tmp, addr); 3176 (_masm->*add)(dst, inc, tmp); 3177 break; 3178 } 3179 case lir_xchg: 3180 { 3181 Register tmp = tmp_op->as_register(); 3182 Register obj = as_reg(data); 3183 Register dst = as_reg(dest); 3184 if (is_oop && UseCompressedOops) { 3185 __ encode_heap_oop(rscratch2, obj); 3186 obj = rscratch2; 3187 } 3188 assert_different_registers(obj, addr.base(), tmp, rscratch1); 3189 assert_different_registers(dst, addr.base(), tmp, rscratch1); 3190 __ lea(tmp, addr); 3191 (_masm->*xchg)(dst, obj, tmp); 3192 if (is_oop && UseCompressedOops) { 3193 __ decode_heap_oop(dst); 3194 } 3195 } 3196 break; 3197 default: 3198 ShouldNotReachHere(); 3199 } 3200 __ membar(__ AnyAny); 3201 } 3202 3203 #undef __