1 /* 2 * Copyright (c) 2000, 2024, Oracle and/or its affiliates. All rights reserved. 3 * Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved. 4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 5 * 6 * This code is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 only, as 8 * published by the Free Software Foundation. 9 * 10 * This code is distributed in the hope that it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 13 * version 2 for more details (a copy is included in the LICENSE file that 14 * accompanied this code). 15 * 16 * You should have received a copy of the GNU General Public License version 17 * 2 along with this work; if not, write to the Free Software Foundation, 18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 19 * 20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 21 * or visit www.oracle.com if you need additional information or have any 22 * questions. 23 * 24 */ 25 26 #include "precompiled.hpp" 27 #include "asm/macroAssembler.inline.hpp" 28 #include "asm/assembler.hpp" 29 #include "c1/c1_CodeStubs.hpp" 30 #include "c1/c1_Compilation.hpp" 31 #include "c1/c1_LIRAssembler.hpp" 32 #include "c1/c1_MacroAssembler.hpp" 33 #include "c1/c1_Runtime1.hpp" 34 #include "c1/c1_ValueStack.hpp" 35 #include "ci/ciArrayKlass.hpp" 36 #include "ci/ciInstance.hpp" 37 #include "code/compiledIC.hpp" 38 #include "gc/shared/collectedHeap.hpp" 39 #include "gc/shared/gc_globals.hpp" 40 #include "nativeInst_aarch64.hpp" 41 #include "oops/objArrayKlass.hpp" 42 #include "runtime/frame.inline.hpp" 43 #include "runtime/sharedRuntime.hpp" 44 #include "runtime/stubRoutines.hpp" 45 #include "utilities/powerOfTwo.hpp" 46 #include "vmreg_aarch64.inline.hpp" 47 48 49 #ifndef PRODUCT 50 #define COMMENT(x) do { __ block_comment(x); } while (0) 51 #else 52 #define COMMENT(x) 53 #endif 54 55 NEEDS_CLEANUP // remove this definitions ? 56 const Register SYNC_header = r0; // synchronization header 57 const Register SHIFT_count = r0; // where count for shift operations must be 58 59 #define __ _masm-> 60 61 62 static void select_different_registers(Register preserve, 63 Register extra, 64 Register &tmp1, 65 Register &tmp2) { 66 if (tmp1 == preserve) { 67 assert_different_registers(tmp1, tmp2, extra); 68 tmp1 = extra; 69 } else if (tmp2 == preserve) { 70 assert_different_registers(tmp1, tmp2, extra); 71 tmp2 = extra; 72 } 73 assert_different_registers(preserve, tmp1, tmp2); 74 } 75 76 77 78 static void select_different_registers(Register preserve, 79 Register extra, 80 Register &tmp1, 81 Register &tmp2, 82 Register &tmp3) { 83 if (tmp1 == preserve) { 84 assert_different_registers(tmp1, tmp2, tmp3, extra); 85 tmp1 = extra; 86 } else if (tmp2 == preserve) { 87 assert_different_registers(tmp1, tmp2, tmp3, extra); 88 tmp2 = extra; 89 } else if (tmp3 == preserve) { 90 assert_different_registers(tmp1, tmp2, tmp3, extra); 91 tmp3 = extra; 92 } 93 assert_different_registers(preserve, tmp1, tmp2, tmp3); 94 } 95 96 97 bool LIR_Assembler::is_small_constant(LIR_Opr opr) { Unimplemented(); return false; } 98 99 100 LIR_Opr LIR_Assembler::receiverOpr() { 101 return FrameMap::receiver_opr; 102 } 103 104 LIR_Opr LIR_Assembler::osrBufferPointer() { 105 return FrameMap::as_pointer_opr(receiverOpr()->as_register()); 106 } 107 108 //--------------fpu register translations----------------------- 109 110 111 address LIR_Assembler::float_constant(float f) { 112 address const_addr = __ float_constant(f); 113 if (const_addr == nullptr) { 114 bailout("const section overflow"); 115 return __ code()->consts()->start(); 116 } else { 117 return const_addr; 118 } 119 } 120 121 122 address LIR_Assembler::double_constant(double d) { 123 address const_addr = __ double_constant(d); 124 if (const_addr == nullptr) { 125 bailout("const section overflow"); 126 return __ code()->consts()->start(); 127 } else { 128 return const_addr; 129 } 130 } 131 132 address LIR_Assembler::int_constant(jlong n) { 133 address const_addr = __ long_constant(n); 134 if (const_addr == nullptr) { 135 bailout("const section overflow"); 136 return __ code()->consts()->start(); 137 } else { 138 return const_addr; 139 } 140 } 141 142 void LIR_Assembler::breakpoint() { Unimplemented(); } 143 144 void LIR_Assembler::push(LIR_Opr opr) { Unimplemented(); } 145 146 void LIR_Assembler::pop(LIR_Opr opr) { Unimplemented(); } 147 148 bool LIR_Assembler::is_literal_address(LIR_Address* addr) { Unimplemented(); return false; } 149 //------------------------------------------- 150 151 static Register as_reg(LIR_Opr op) { 152 return op->is_double_cpu() ? op->as_register_lo() : op->as_register(); 153 } 154 155 static jlong as_long(LIR_Opr data) { 156 jlong result; 157 switch (data->type()) { 158 case T_INT: 159 result = (data->as_jint()); 160 break; 161 case T_LONG: 162 result = (data->as_jlong()); 163 break; 164 default: 165 ShouldNotReachHere(); 166 result = 0; // unreachable 167 } 168 return result; 169 } 170 171 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) { 172 Register base = addr->base()->as_pointer_register(); 173 LIR_Opr opr = addr->index(); 174 if (opr->is_cpu_register()) { 175 Register index; 176 if (opr->is_single_cpu()) 177 index = opr->as_register(); 178 else 179 index = opr->as_register_lo(); 180 assert(addr->disp() == 0, "must be"); 181 switch(opr->type()) { 182 case T_INT: 183 return Address(base, index, Address::sxtw(addr->scale())); 184 case T_LONG: 185 return Address(base, index, Address::lsl(addr->scale())); 186 default: 187 ShouldNotReachHere(); 188 } 189 } else { 190 assert(addr->scale() == 0, 191 "expected for immediate operand, was: %d", addr->scale()); 192 ptrdiff_t offset = ptrdiff_t(addr->disp()); 193 // NOTE: Does not handle any 16 byte vector access. 194 const uint type_size = type2aelembytes(addr->type(), true); 195 return __ legitimize_address(Address(base, offset), type_size, tmp); 196 } 197 return Address(); 198 } 199 200 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) { 201 ShouldNotReachHere(); 202 return Address(); 203 } 204 205 Address LIR_Assembler::as_Address(LIR_Address* addr) { 206 return as_Address(addr, rscratch1); 207 } 208 209 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) { 210 return as_Address(addr, rscratch1); // Ouch 211 // FIXME: This needs to be much more clever. See x86. 212 } 213 214 // Ensure a valid Address (base + offset) to a stack-slot. If stack access is 215 // not encodable as a base + (immediate) offset, generate an explicit address 216 // calculation to hold the address in a temporary register. 217 Address LIR_Assembler::stack_slot_address(int index, uint size, Register tmp, int adjust) { 218 precond(size == 4 || size == 8); 219 Address addr = frame_map()->address_for_slot(index, adjust); 220 precond(addr.getMode() == Address::base_plus_offset); 221 precond(addr.base() == sp); 222 precond(addr.offset() > 0); 223 uint mask = size - 1; 224 assert((addr.offset() & mask) == 0, "scaled offsets only"); 225 return __ legitimize_address(addr, size, tmp); 226 } 227 228 void LIR_Assembler::osr_entry() { 229 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset()); 230 BlockBegin* osr_entry = compilation()->hir()->osr_entry(); 231 ValueStack* entry_state = osr_entry->state(); 232 int number_of_locks = entry_state->locks_size(); 233 234 // we jump here if osr happens with the interpreter 235 // state set up to continue at the beginning of the 236 // loop that triggered osr - in particular, we have 237 // the following registers setup: 238 // 239 // r2: osr buffer 240 // 241 242 // build frame 243 ciMethod* m = compilation()->method(); 244 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes()); 245 246 // OSR buffer is 247 // 248 // locals[nlocals-1..0] 249 // monitors[0..number_of_locks] 250 // 251 // locals is a direct copy of the interpreter frame so in the osr buffer 252 // so first slot in the local array is the last local from the interpreter 253 // and last slot is local[0] (receiver) from the interpreter 254 // 255 // Similarly with locks. The first lock slot in the osr buffer is the nth lock 256 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock 257 // in the interpreter frame (the method lock if a sync method) 258 259 // Initialize monitors in the compiled activation. 260 // r2: pointer to osr buffer 261 // 262 // All other registers are dead at this point and the locals will be 263 // copied into place by code emitted in the IR. 264 265 Register OSR_buf = osrBufferPointer()->as_pointer_register(); 266 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below"); 267 int monitor_offset = BytesPerWord * method()->max_locals() + 268 (2 * BytesPerWord) * (number_of_locks - 1); 269 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in 270 // the OSR buffer using 2 word entries: first the lock and then 271 // the oop. 272 for (int i = 0; i < number_of_locks; i++) { 273 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord); 274 #ifdef ASSERT 275 // verify the interpreter's monitor has a non-null object 276 { 277 Label L; 278 __ ldr(rscratch1, Address(OSR_buf, slot_offset + 1*BytesPerWord)); 279 __ cbnz(rscratch1, L); 280 __ stop("locked object is null"); 281 __ bind(L); 282 } 283 #endif 284 __ ldr(r19, Address(OSR_buf, slot_offset)); 285 __ ldr(r20, Address(OSR_buf, slot_offset + BytesPerWord)); 286 __ str(r19, frame_map()->address_for_monitor_lock(i)); 287 __ str(r20, frame_map()->address_for_monitor_object(i)); 288 } 289 } 290 } 291 292 293 // inline cache check; done before the frame is built. 294 int LIR_Assembler::check_icache() { 295 return __ ic_check(CodeEntryAlignment); 296 } 297 298 void LIR_Assembler::clinit_barrier(ciMethod* method) { 299 assert(VM_Version::supports_fast_class_init_checks(), "sanity"); 300 assert(!method->holder()->is_not_initialized(), "initialization should have been started"); 301 302 Label L_skip_barrier; 303 304 __ mov_metadata(rscratch2, method->holder()->constant_encoding()); 305 __ clinit_barrier(rscratch2, rscratch1, &L_skip_barrier /*L_fast_path*/); 306 __ far_jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub())); 307 __ bind(L_skip_barrier); 308 } 309 310 void LIR_Assembler::jobject2reg(jobject o, Register reg) { 311 if (o == nullptr) { 312 __ mov(reg, zr); 313 } else { 314 __ movoop(reg, o); 315 } 316 } 317 318 void LIR_Assembler::deoptimize_trap(CodeEmitInfo *info) { 319 address target = nullptr; 320 relocInfo::relocType reloc_type = relocInfo::none; 321 322 switch (patching_id(info)) { 323 case PatchingStub::access_field_id: 324 target = Runtime1::entry_for(Runtime1::access_field_patching_id); 325 reloc_type = relocInfo::section_word_type; 326 break; 327 case PatchingStub::load_klass_id: 328 target = Runtime1::entry_for(Runtime1::load_klass_patching_id); 329 reloc_type = relocInfo::metadata_type; 330 break; 331 case PatchingStub::load_mirror_id: 332 target = Runtime1::entry_for(Runtime1::load_mirror_patching_id); 333 reloc_type = relocInfo::oop_type; 334 break; 335 case PatchingStub::load_appendix_id: 336 target = Runtime1::entry_for(Runtime1::load_appendix_patching_id); 337 reloc_type = relocInfo::oop_type; 338 break; 339 default: ShouldNotReachHere(); 340 } 341 342 __ far_call(RuntimeAddress(target)); 343 add_call_info_here(info); 344 } 345 346 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) { 347 deoptimize_trap(info); 348 } 349 350 351 // This specifies the rsp decrement needed to build the frame 352 int LIR_Assembler::initial_frame_size_in_bytes() const { 353 // if rounding, must let FrameMap know! 354 355 return in_bytes(frame_map()->framesize_in_bytes()); 356 } 357 358 359 int LIR_Assembler::emit_exception_handler() { 360 // generate code for exception handler 361 address handler_base = __ start_a_stub(exception_handler_size()); 362 if (handler_base == nullptr) { 363 // not enough space left for the handler 364 bailout("exception handler overflow"); 365 return -1; 366 } 367 368 int offset = code_offset(); 369 370 // the exception oop and pc are in r0, and r3 371 // no other registers need to be preserved, so invalidate them 372 __ invalidate_registers(false, true, true, false, true, true); 373 374 // check that there is really an exception 375 __ verify_not_null_oop(r0); 376 377 // search an exception handler (r0: exception oop, r3: throwing pc) 378 __ far_call(RuntimeAddress(Runtime1::entry_for(Runtime1::handle_exception_from_callee_id))); 379 __ should_not_reach_here(); 380 guarantee(code_offset() - offset <= exception_handler_size(), "overflow"); 381 __ end_a_stub(); 382 383 return offset; 384 } 385 386 387 // Emit the code to remove the frame from the stack in the exception 388 // unwind path. 389 int LIR_Assembler::emit_unwind_handler() { 390 #ifndef PRODUCT 391 if (CommentedAssembly) { 392 _masm->block_comment("Unwind handler"); 393 } 394 #endif 395 396 int offset = code_offset(); 397 398 // Fetch the exception from TLS and clear out exception related thread state 399 __ ldr(r0, Address(rthread, JavaThread::exception_oop_offset())); 400 __ str(zr, Address(rthread, JavaThread::exception_oop_offset())); 401 __ str(zr, Address(rthread, JavaThread::exception_pc_offset())); 402 403 __ bind(_unwind_handler_entry); 404 __ verify_not_null_oop(r0); 405 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) { 406 __ mov(r19, r0); // Preserve the exception 407 } 408 409 // Perform needed unlocking 410 MonitorExitStub* stub = nullptr; 411 if (method()->is_synchronized()) { 412 monitor_address(0, FrameMap::r0_opr); 413 stub = new MonitorExitStub(FrameMap::r0_opr, true, 0); 414 if (LockingMode == LM_MONITOR) { 415 __ b(*stub->entry()); 416 } else { 417 __ unlock_object(r5, r4, r0, r6, *stub->entry()); 418 } 419 __ bind(*stub->continuation()); 420 } 421 422 if (compilation()->env()->dtrace_method_probes()) { 423 __ mov(c_rarg0, rthread); 424 __ mov_metadata(c_rarg1, method()->constant_encoding()); 425 __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit), c_rarg0, c_rarg1); 426 } 427 428 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) { 429 __ mov(r0, r19); // Restore the exception 430 } 431 432 // remove the activation and dispatch to the unwind handler 433 __ block_comment("remove_frame and dispatch to the unwind handler"); 434 __ remove_frame(initial_frame_size_in_bytes()); 435 __ far_jump(RuntimeAddress(Runtime1::entry_for(Runtime1::unwind_exception_id))); 436 437 // Emit the slow path assembly 438 if (stub != nullptr) { 439 stub->emit_code(this); 440 } 441 442 return offset; 443 } 444 445 446 int LIR_Assembler::emit_deopt_handler() { 447 // generate code for exception handler 448 address handler_base = __ start_a_stub(deopt_handler_size()); 449 if (handler_base == nullptr) { 450 // not enough space left for the handler 451 bailout("deopt handler overflow"); 452 return -1; 453 } 454 455 int offset = code_offset(); 456 457 __ adr(lr, pc()); 458 __ far_jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack())); 459 guarantee(code_offset() - offset <= deopt_handler_size(), "overflow"); 460 __ end_a_stub(); 461 462 return offset; 463 } 464 465 void LIR_Assembler::add_debug_info_for_branch(address adr, CodeEmitInfo* info) { 466 _masm->code_section()->relocate(adr, relocInfo::poll_type); 467 int pc_offset = code_offset(); 468 flush_debug_info(pc_offset); 469 info->record_debug_info(compilation()->debug_info_recorder(), pc_offset); 470 if (info->exception_handlers() != nullptr) { 471 compilation()->add_exception_handlers_for_pco(pc_offset, info->exception_handlers()); 472 } 473 } 474 475 void LIR_Assembler::return_op(LIR_Opr result, C1SafepointPollStub* code_stub) { 476 assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == r0, "word returns are in r0,"); 477 478 // Pop the stack before the safepoint code 479 __ remove_frame(initial_frame_size_in_bytes()); 480 481 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) { 482 __ reserved_stack_check(); 483 } 484 485 code_stub->set_safepoint_offset(__ offset()); 486 __ relocate(relocInfo::poll_return_type); 487 __ safepoint_poll(*code_stub->entry(), true /* at_return */, false /* acquire */, true /* in_nmethod */); 488 __ ret(lr); 489 } 490 491 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) { 492 guarantee(info != nullptr, "Shouldn't be null"); 493 __ get_polling_page(rscratch1, relocInfo::poll_type); 494 add_debug_info_for_branch(info); // This isn't just debug info: 495 // it's the oop map 496 __ read_polling_page(rscratch1, relocInfo::poll_type); 497 return __ offset(); 498 } 499 500 501 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) { 502 if (from_reg == r31_sp) 503 from_reg = sp; 504 if (to_reg == r31_sp) 505 to_reg = sp; 506 __ mov(to_reg, from_reg); 507 } 508 509 void LIR_Assembler::swap_reg(Register a, Register b) { Unimplemented(); } 510 511 512 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) { 513 assert(src->is_constant(), "should not call otherwise"); 514 assert(dest->is_register(), "should not call otherwise"); 515 LIR_Const* c = src->as_constant_ptr(); 516 517 switch (c->type()) { 518 case T_INT: { 519 assert(patch_code == lir_patch_none, "no patching handled here"); 520 __ movw(dest->as_register(), c->as_jint()); 521 break; 522 } 523 524 case T_ADDRESS: { 525 assert(patch_code == lir_patch_none, "no patching handled here"); 526 __ mov(dest->as_register(), c->as_jint()); 527 break; 528 } 529 530 case T_LONG: { 531 assert(patch_code == lir_patch_none, "no patching handled here"); 532 __ mov(dest->as_register_lo(), (intptr_t)c->as_jlong()); 533 break; 534 } 535 536 case T_OBJECT: { 537 if (patch_code == lir_patch_none) { 538 jobject2reg(c->as_jobject(), dest->as_register()); 539 } else { 540 jobject2reg_with_patching(dest->as_register(), info); 541 } 542 break; 543 } 544 545 case T_METADATA: { 546 if (patch_code != lir_patch_none) { 547 klass2reg_with_patching(dest->as_register(), info); 548 } else { 549 __ mov_metadata(dest->as_register(), c->as_metadata()); 550 } 551 break; 552 } 553 554 case T_FLOAT: { 555 if (__ operand_valid_for_float_immediate(c->as_jfloat())) { 556 __ fmovs(dest->as_float_reg(), (c->as_jfloat())); 557 } else { 558 __ adr(rscratch1, InternalAddress(float_constant(c->as_jfloat()))); 559 __ ldrs(dest->as_float_reg(), Address(rscratch1)); 560 } 561 break; 562 } 563 564 case T_DOUBLE: { 565 if (__ operand_valid_for_float_immediate(c->as_jdouble())) { 566 __ fmovd(dest->as_double_reg(), (c->as_jdouble())); 567 } else { 568 __ adr(rscratch1, InternalAddress(double_constant(c->as_jdouble()))); 569 __ ldrd(dest->as_double_reg(), Address(rscratch1)); 570 } 571 break; 572 } 573 574 default: 575 ShouldNotReachHere(); 576 } 577 } 578 579 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) { 580 LIR_Const* c = src->as_constant_ptr(); 581 switch (c->type()) { 582 case T_OBJECT: 583 { 584 if (! c->as_jobject()) 585 __ str(zr, frame_map()->address_for_slot(dest->single_stack_ix())); 586 else { 587 const2reg(src, FrameMap::rscratch1_opr, lir_patch_none, nullptr); 588 reg2stack(FrameMap::rscratch1_opr, dest, c->type(), false); 589 } 590 } 591 break; 592 case T_ADDRESS: 593 { 594 const2reg(src, FrameMap::rscratch1_opr, lir_patch_none, nullptr); 595 reg2stack(FrameMap::rscratch1_opr, dest, c->type(), false); 596 } 597 case T_INT: 598 case T_FLOAT: 599 { 600 Register reg = zr; 601 if (c->as_jint_bits() == 0) 602 __ strw(zr, frame_map()->address_for_slot(dest->single_stack_ix())); 603 else { 604 __ movw(rscratch1, c->as_jint_bits()); 605 __ strw(rscratch1, frame_map()->address_for_slot(dest->single_stack_ix())); 606 } 607 } 608 break; 609 case T_LONG: 610 case T_DOUBLE: 611 { 612 Register reg = zr; 613 if (c->as_jlong_bits() == 0) 614 __ str(zr, frame_map()->address_for_slot(dest->double_stack_ix(), 615 lo_word_offset_in_bytes)); 616 else { 617 __ mov(rscratch1, (intptr_t)c->as_jlong_bits()); 618 __ str(rscratch1, frame_map()->address_for_slot(dest->double_stack_ix(), 619 lo_word_offset_in_bytes)); 620 } 621 } 622 break; 623 default: 624 ShouldNotReachHere(); 625 } 626 } 627 628 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) { 629 assert(src->is_constant(), "should not call otherwise"); 630 LIR_Const* c = src->as_constant_ptr(); 631 LIR_Address* to_addr = dest->as_address_ptr(); 632 633 void (Assembler::* insn)(Register Rt, const Address &adr); 634 635 switch (type) { 636 case T_ADDRESS: 637 assert(c->as_jint() == 0, "should be"); 638 insn = &Assembler::str; 639 break; 640 case T_LONG: 641 assert(c->as_jlong() == 0, "should be"); 642 insn = &Assembler::str; 643 break; 644 case T_INT: 645 assert(c->as_jint() == 0, "should be"); 646 insn = &Assembler::strw; 647 break; 648 case T_OBJECT: 649 case T_ARRAY: 650 assert(c->as_jobject() == 0, "should be"); 651 if (UseCompressedOops && !wide) { 652 insn = &Assembler::strw; 653 } else { 654 insn = &Assembler::str; 655 } 656 break; 657 case T_CHAR: 658 case T_SHORT: 659 assert(c->as_jint() == 0, "should be"); 660 insn = &Assembler::strh; 661 break; 662 case T_BOOLEAN: 663 case T_BYTE: 664 assert(c->as_jint() == 0, "should be"); 665 insn = &Assembler::strb; 666 break; 667 default: 668 ShouldNotReachHere(); 669 insn = &Assembler::str; // unreachable 670 } 671 672 if (info) add_debug_info_for_null_check_here(info); 673 (_masm->*insn)(zr, as_Address(to_addr, rscratch1)); 674 } 675 676 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) { 677 assert(src->is_register(), "should not call otherwise"); 678 assert(dest->is_register(), "should not call otherwise"); 679 680 // move between cpu-registers 681 if (dest->is_single_cpu()) { 682 if (src->type() == T_LONG) { 683 // Can do LONG -> OBJECT 684 move_regs(src->as_register_lo(), dest->as_register()); 685 return; 686 } 687 assert(src->is_single_cpu(), "must match"); 688 if (src->type() == T_OBJECT) { 689 __ verify_oop(src->as_register()); 690 } 691 move_regs(src->as_register(), dest->as_register()); 692 693 } else if (dest->is_double_cpu()) { 694 if (is_reference_type(src->type())) { 695 // Surprising to me but we can see move of a long to t_object 696 __ verify_oop(src->as_register()); 697 move_regs(src->as_register(), dest->as_register_lo()); 698 return; 699 } 700 assert(src->is_double_cpu(), "must match"); 701 Register f_lo = src->as_register_lo(); 702 Register f_hi = src->as_register_hi(); 703 Register t_lo = dest->as_register_lo(); 704 Register t_hi = dest->as_register_hi(); 705 assert(f_hi == f_lo, "must be same"); 706 assert(t_hi == t_lo, "must be same"); 707 move_regs(f_lo, t_lo); 708 709 } else if (dest->is_single_fpu()) { 710 __ fmovs(dest->as_float_reg(), src->as_float_reg()); 711 712 } else if (dest->is_double_fpu()) { 713 __ fmovd(dest->as_double_reg(), src->as_double_reg()); 714 715 } else { 716 ShouldNotReachHere(); 717 } 718 } 719 720 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) { 721 precond(src->is_register() && dest->is_stack()); 722 723 uint const c_sz32 = sizeof(uint32_t); 724 uint const c_sz64 = sizeof(uint64_t); 725 726 if (src->is_single_cpu()) { 727 int index = dest->single_stack_ix(); 728 if (is_reference_type(type)) { 729 __ str(src->as_register(), stack_slot_address(index, c_sz64, rscratch1)); 730 __ verify_oop(src->as_register()); 731 } else if (type == T_METADATA || type == T_DOUBLE || type == T_ADDRESS) { 732 __ str(src->as_register(), stack_slot_address(index, c_sz64, rscratch1)); 733 } else { 734 __ strw(src->as_register(), stack_slot_address(index, c_sz32, rscratch1)); 735 } 736 737 } else if (src->is_double_cpu()) { 738 int index = dest->double_stack_ix(); 739 Address dest_addr_LO = stack_slot_address(index, c_sz64, rscratch1, lo_word_offset_in_bytes); 740 __ str(src->as_register_lo(), dest_addr_LO); 741 742 } else if (src->is_single_fpu()) { 743 int index = dest->single_stack_ix(); 744 __ strs(src->as_float_reg(), stack_slot_address(index, c_sz32, rscratch1)); 745 746 } else if (src->is_double_fpu()) { 747 int index = dest->double_stack_ix(); 748 __ strd(src->as_double_reg(), stack_slot_address(index, c_sz64, rscratch1)); 749 750 } else { 751 ShouldNotReachHere(); 752 } 753 } 754 755 756 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool wide) { 757 LIR_Address* to_addr = dest->as_address_ptr(); 758 PatchingStub* patch = nullptr; 759 Register compressed_src = rscratch1; 760 761 if (patch_code != lir_patch_none) { 762 deoptimize_trap(info); 763 return; 764 } 765 766 if (is_reference_type(type)) { 767 __ verify_oop(src->as_register()); 768 769 if (UseCompressedOops && !wide) { 770 __ encode_heap_oop(compressed_src, src->as_register()); 771 } else { 772 compressed_src = src->as_register(); 773 } 774 } 775 776 int null_check_here = code_offset(); 777 switch (type) { 778 case T_FLOAT: { 779 __ strs(src->as_float_reg(), as_Address(to_addr)); 780 break; 781 } 782 783 case T_DOUBLE: { 784 __ strd(src->as_double_reg(), as_Address(to_addr)); 785 break; 786 } 787 788 case T_ARRAY: // fall through 789 case T_OBJECT: // fall through 790 if (UseCompressedOops && !wide) { 791 __ strw(compressed_src, as_Address(to_addr, rscratch2)); 792 } else { 793 __ str(compressed_src, as_Address(to_addr)); 794 } 795 break; 796 case T_METADATA: 797 // We get here to store a method pointer to the stack to pass to 798 // a dtrace runtime call. This can't work on 64 bit with 799 // compressed klass ptrs: T_METADATA can be a compressed klass 800 // ptr or a 64 bit method pointer. 801 ShouldNotReachHere(); 802 __ str(src->as_register(), as_Address(to_addr)); 803 break; 804 case T_ADDRESS: 805 __ str(src->as_register(), as_Address(to_addr)); 806 break; 807 case T_INT: 808 __ strw(src->as_register(), as_Address(to_addr)); 809 break; 810 811 case T_LONG: { 812 __ str(src->as_register_lo(), as_Address_lo(to_addr)); 813 break; 814 } 815 816 case T_BYTE: // fall through 817 case T_BOOLEAN: { 818 __ strb(src->as_register(), as_Address(to_addr)); 819 break; 820 } 821 822 case T_CHAR: // fall through 823 case T_SHORT: 824 __ strh(src->as_register(), as_Address(to_addr)); 825 break; 826 827 default: 828 ShouldNotReachHere(); 829 } 830 if (info != nullptr) { 831 add_debug_info_for_null_check(null_check_here, info); 832 } 833 } 834 835 836 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) { 837 precond(src->is_stack() && dest->is_register()); 838 839 uint const c_sz32 = sizeof(uint32_t); 840 uint const c_sz64 = sizeof(uint64_t); 841 842 if (dest->is_single_cpu()) { 843 int index = src->single_stack_ix(); 844 if (is_reference_type(type)) { 845 __ ldr(dest->as_register(), stack_slot_address(index, c_sz64, rscratch1)); 846 __ verify_oop(dest->as_register()); 847 } else if (type == T_METADATA || type == T_ADDRESS) { 848 __ ldr(dest->as_register(), stack_slot_address(index, c_sz64, rscratch1)); 849 } else { 850 __ ldrw(dest->as_register(), stack_slot_address(index, c_sz32, rscratch1)); 851 } 852 853 } else if (dest->is_double_cpu()) { 854 int index = src->double_stack_ix(); 855 Address src_addr_LO = stack_slot_address(index, c_sz64, rscratch1, lo_word_offset_in_bytes); 856 __ ldr(dest->as_register_lo(), src_addr_LO); 857 858 } else if (dest->is_single_fpu()) { 859 int index = src->single_stack_ix(); 860 __ ldrs(dest->as_float_reg(), stack_slot_address(index, c_sz32, rscratch1)); 861 862 } else if (dest->is_double_fpu()) { 863 int index = src->double_stack_ix(); 864 __ ldrd(dest->as_double_reg(), stack_slot_address(index, c_sz64, rscratch1)); 865 866 } else { 867 ShouldNotReachHere(); 868 } 869 } 870 871 872 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) { 873 address target = nullptr; 874 relocInfo::relocType reloc_type = relocInfo::none; 875 876 switch (patching_id(info)) { 877 case PatchingStub::access_field_id: 878 target = Runtime1::entry_for(Runtime1::access_field_patching_id); 879 reloc_type = relocInfo::section_word_type; 880 break; 881 case PatchingStub::load_klass_id: 882 target = Runtime1::entry_for(Runtime1::load_klass_patching_id); 883 reloc_type = relocInfo::metadata_type; 884 break; 885 case PatchingStub::load_mirror_id: 886 target = Runtime1::entry_for(Runtime1::load_mirror_patching_id); 887 reloc_type = relocInfo::oop_type; 888 break; 889 case PatchingStub::load_appendix_id: 890 target = Runtime1::entry_for(Runtime1::load_appendix_patching_id); 891 reloc_type = relocInfo::oop_type; 892 break; 893 default: ShouldNotReachHere(); 894 } 895 896 __ far_call(RuntimeAddress(target)); 897 add_call_info_here(info); 898 } 899 900 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) { 901 902 LIR_Opr temp; 903 if (type == T_LONG || type == T_DOUBLE) 904 temp = FrameMap::rscratch1_long_opr; 905 else 906 temp = FrameMap::rscratch1_opr; 907 908 stack2reg(src, temp, src->type()); 909 reg2stack(temp, dest, dest->type(), false); 910 } 911 912 913 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide) { 914 LIR_Address* addr = src->as_address_ptr(); 915 LIR_Address* from_addr = src->as_address_ptr(); 916 917 if (addr->base()->type() == T_OBJECT) { 918 __ verify_oop(addr->base()->as_pointer_register()); 919 } 920 921 if (patch_code != lir_patch_none) { 922 deoptimize_trap(info); 923 return; 924 } 925 926 if (info != nullptr) { 927 add_debug_info_for_null_check_here(info); 928 } 929 int null_check_here = code_offset(); 930 switch (type) { 931 case T_FLOAT: { 932 __ ldrs(dest->as_float_reg(), as_Address(from_addr)); 933 break; 934 } 935 936 case T_DOUBLE: { 937 __ ldrd(dest->as_double_reg(), as_Address(from_addr)); 938 break; 939 } 940 941 case T_ARRAY: // fall through 942 case T_OBJECT: // fall through 943 if (UseCompressedOops && !wide) { 944 __ ldrw(dest->as_register(), as_Address(from_addr)); 945 } else { 946 __ ldr(dest->as_register(), as_Address(from_addr)); 947 } 948 break; 949 case T_METADATA: 950 // We get here to store a method pointer to the stack to pass to 951 // a dtrace runtime call. This can't work on 64 bit with 952 // compressed klass ptrs: T_METADATA can be a compressed klass 953 // ptr or a 64 bit method pointer. 954 ShouldNotReachHere(); 955 __ ldr(dest->as_register(), as_Address(from_addr)); 956 break; 957 case T_ADDRESS: 958 __ ldr(dest->as_register(), as_Address(from_addr)); 959 break; 960 case T_INT: 961 __ ldrw(dest->as_register(), as_Address(from_addr)); 962 break; 963 964 case T_LONG: { 965 __ ldr(dest->as_register_lo(), as_Address_lo(from_addr)); 966 break; 967 } 968 969 case T_BYTE: 970 __ ldrsb(dest->as_register(), as_Address(from_addr)); 971 break; 972 case T_BOOLEAN: { 973 __ ldrb(dest->as_register(), as_Address(from_addr)); 974 break; 975 } 976 977 case T_CHAR: 978 __ ldrh(dest->as_register(), as_Address(from_addr)); 979 break; 980 case T_SHORT: 981 __ ldrsh(dest->as_register(), as_Address(from_addr)); 982 break; 983 984 default: 985 ShouldNotReachHere(); 986 } 987 988 if (is_reference_type(type)) { 989 if (UseCompressedOops && !wide) { 990 __ decode_heap_oop(dest->as_register()); 991 } 992 993 if (!(UseZGC && !ZGenerational)) { 994 // Load barrier has not yet been applied, so ZGC can't verify the oop here 995 __ verify_oop(dest->as_register()); 996 } 997 } 998 } 999 1000 1001 int LIR_Assembler::array_element_size(BasicType type) const { 1002 int elem_size = type2aelembytes(type); 1003 return exact_log2(elem_size); 1004 } 1005 1006 1007 void LIR_Assembler::emit_op3(LIR_Op3* op) { 1008 switch (op->code()) { 1009 case lir_idiv: 1010 case lir_irem: 1011 arithmetic_idiv(op->code(), 1012 op->in_opr1(), 1013 op->in_opr2(), 1014 op->in_opr3(), 1015 op->result_opr(), 1016 op->info()); 1017 break; 1018 case lir_fmad: 1019 __ fmaddd(op->result_opr()->as_double_reg(), 1020 op->in_opr1()->as_double_reg(), 1021 op->in_opr2()->as_double_reg(), 1022 op->in_opr3()->as_double_reg()); 1023 break; 1024 case lir_fmaf: 1025 __ fmadds(op->result_opr()->as_float_reg(), 1026 op->in_opr1()->as_float_reg(), 1027 op->in_opr2()->as_float_reg(), 1028 op->in_opr3()->as_float_reg()); 1029 break; 1030 default: ShouldNotReachHere(); break; 1031 } 1032 } 1033 1034 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) { 1035 #ifdef ASSERT 1036 assert(op->block() == nullptr || op->block()->label() == op->label(), "wrong label"); 1037 if (op->block() != nullptr) _branch_target_blocks.append(op->block()); 1038 if (op->ublock() != nullptr) _branch_target_blocks.append(op->ublock()); 1039 #endif 1040 1041 if (op->cond() == lir_cond_always) { 1042 if (op->info() != nullptr) add_debug_info_for_branch(op->info()); 1043 __ b(*(op->label())); 1044 } else { 1045 Assembler::Condition acond; 1046 if (op->code() == lir_cond_float_branch) { 1047 bool is_unordered = (op->ublock() == op->block()); 1048 // Assembler::EQ does not permit unordered branches, so we add 1049 // another branch here. Likewise, Assembler::NE does not permit 1050 // ordered branches. 1051 if ((is_unordered && op->cond() == lir_cond_equal) 1052 || (!is_unordered && op->cond() == lir_cond_notEqual)) 1053 __ br(Assembler::VS, *(op->ublock()->label())); 1054 switch(op->cond()) { 1055 case lir_cond_equal: acond = Assembler::EQ; break; 1056 case lir_cond_notEqual: acond = Assembler::NE; break; 1057 case lir_cond_less: acond = (is_unordered ? Assembler::LT : Assembler::LO); break; 1058 case lir_cond_lessEqual: acond = (is_unordered ? Assembler::LE : Assembler::LS); break; 1059 case lir_cond_greaterEqual: acond = (is_unordered ? Assembler::HS : Assembler::GE); break; 1060 case lir_cond_greater: acond = (is_unordered ? Assembler::HI : Assembler::GT); break; 1061 default: ShouldNotReachHere(); 1062 acond = Assembler::EQ; // unreachable 1063 } 1064 } else { 1065 switch (op->cond()) { 1066 case lir_cond_equal: acond = Assembler::EQ; break; 1067 case lir_cond_notEqual: acond = Assembler::NE; break; 1068 case lir_cond_less: acond = Assembler::LT; break; 1069 case lir_cond_lessEqual: acond = Assembler::LE; break; 1070 case lir_cond_greaterEqual: acond = Assembler::GE; break; 1071 case lir_cond_greater: acond = Assembler::GT; break; 1072 case lir_cond_belowEqual: acond = Assembler::LS; break; 1073 case lir_cond_aboveEqual: acond = Assembler::HS; break; 1074 default: ShouldNotReachHere(); 1075 acond = Assembler::EQ; // unreachable 1076 } 1077 } 1078 __ br(acond,*(op->label())); 1079 } 1080 } 1081 1082 1083 1084 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) { 1085 LIR_Opr src = op->in_opr(); 1086 LIR_Opr dest = op->result_opr(); 1087 1088 switch (op->bytecode()) { 1089 case Bytecodes::_i2f: 1090 { 1091 __ scvtfws(dest->as_float_reg(), src->as_register()); 1092 break; 1093 } 1094 case Bytecodes::_i2d: 1095 { 1096 __ scvtfwd(dest->as_double_reg(), src->as_register()); 1097 break; 1098 } 1099 case Bytecodes::_l2d: 1100 { 1101 __ scvtfd(dest->as_double_reg(), src->as_register_lo()); 1102 break; 1103 } 1104 case Bytecodes::_l2f: 1105 { 1106 __ scvtfs(dest->as_float_reg(), src->as_register_lo()); 1107 break; 1108 } 1109 case Bytecodes::_f2d: 1110 { 1111 __ fcvts(dest->as_double_reg(), src->as_float_reg()); 1112 break; 1113 } 1114 case Bytecodes::_d2f: 1115 { 1116 __ fcvtd(dest->as_float_reg(), src->as_double_reg()); 1117 break; 1118 } 1119 case Bytecodes::_i2c: 1120 { 1121 __ ubfx(dest->as_register(), src->as_register(), 0, 16); 1122 break; 1123 } 1124 case Bytecodes::_i2l: 1125 { 1126 __ sxtw(dest->as_register_lo(), src->as_register()); 1127 break; 1128 } 1129 case Bytecodes::_i2s: 1130 { 1131 __ sxth(dest->as_register(), src->as_register()); 1132 break; 1133 } 1134 case Bytecodes::_i2b: 1135 { 1136 __ sxtb(dest->as_register(), src->as_register()); 1137 break; 1138 } 1139 case Bytecodes::_l2i: 1140 { 1141 _masm->block_comment("FIXME: This could be a no-op"); 1142 __ uxtw(dest->as_register(), src->as_register_lo()); 1143 break; 1144 } 1145 case Bytecodes::_d2l: 1146 { 1147 __ fcvtzd(dest->as_register_lo(), src->as_double_reg()); 1148 break; 1149 } 1150 case Bytecodes::_f2i: 1151 { 1152 __ fcvtzsw(dest->as_register(), src->as_float_reg()); 1153 break; 1154 } 1155 case Bytecodes::_f2l: 1156 { 1157 __ fcvtzs(dest->as_register_lo(), src->as_float_reg()); 1158 break; 1159 } 1160 case Bytecodes::_d2i: 1161 { 1162 __ fcvtzdw(dest->as_register(), src->as_double_reg()); 1163 break; 1164 } 1165 default: ShouldNotReachHere(); 1166 } 1167 } 1168 1169 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) { 1170 if (op->init_check()) { 1171 __ ldrb(rscratch1, Address(op->klass()->as_register(), 1172 InstanceKlass::init_state_offset())); 1173 __ cmpw(rscratch1, InstanceKlass::fully_initialized); 1174 add_debug_info_for_null_check_here(op->stub()->info()); 1175 __ br(Assembler::NE, *op->stub()->entry()); 1176 } 1177 __ allocate_object(op->obj()->as_register(), 1178 op->tmp1()->as_register(), 1179 op->tmp2()->as_register(), 1180 op->header_size(), 1181 op->object_size(), 1182 op->klass()->as_register(), 1183 *op->stub()->entry()); 1184 __ bind(*op->stub()->continuation()); 1185 } 1186 1187 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) { 1188 Register len = op->len()->as_register(); 1189 __ uxtw(len, len); 1190 1191 if (UseSlowPath || 1192 (!UseFastNewObjectArray && is_reference_type(op->type())) || 1193 (!UseFastNewTypeArray && !is_reference_type(op->type()))) { 1194 __ b(*op->stub()->entry()); 1195 } else { 1196 Register tmp1 = op->tmp1()->as_register(); 1197 Register tmp2 = op->tmp2()->as_register(); 1198 Register tmp3 = op->tmp3()->as_register(); 1199 if (len == tmp1) { 1200 tmp1 = tmp3; 1201 } else if (len == tmp2) { 1202 tmp2 = tmp3; 1203 } else if (len == tmp3) { 1204 // everything is ok 1205 } else { 1206 __ mov(tmp3, len); 1207 } 1208 __ allocate_array(op->obj()->as_register(), 1209 len, 1210 tmp1, 1211 tmp2, 1212 arrayOopDesc::base_offset_in_bytes(op->type()), 1213 array_element_size(op->type()), 1214 op->klass()->as_register(), 1215 *op->stub()->entry()); 1216 } 1217 __ bind(*op->stub()->continuation()); 1218 } 1219 1220 void LIR_Assembler::type_profile_helper(Register mdo, 1221 ciMethodData *md, ciProfileData *data, 1222 Register recv, Label* update_done) { 1223 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) { 1224 Label next_test; 1225 // See if the receiver is receiver[n]. 1226 __ lea(rscratch2, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)))); 1227 __ ldr(rscratch1, Address(rscratch2)); 1228 __ cmp(recv, rscratch1); 1229 __ br(Assembler::NE, next_test); 1230 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))); 1231 __ addptr(data_addr, DataLayout::counter_increment); 1232 __ b(*update_done); 1233 __ bind(next_test); 1234 } 1235 1236 // Didn't find receiver; find next empty slot and fill it in 1237 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) { 1238 Label next_test; 1239 __ lea(rscratch2, 1240 Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)))); 1241 Address recv_addr(rscratch2); 1242 __ ldr(rscratch1, recv_addr); 1243 __ cbnz(rscratch1, next_test); 1244 __ str(recv, recv_addr); 1245 __ mov(rscratch1, DataLayout::counter_increment); 1246 __ lea(rscratch2, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)))); 1247 __ str(rscratch1, Address(rscratch2)); 1248 __ b(*update_done); 1249 __ bind(next_test); 1250 } 1251 } 1252 1253 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) { 1254 // we always need a stub for the failure case. 1255 CodeStub* stub = op->stub(); 1256 Register obj = op->object()->as_register(); 1257 Register k_RInfo = op->tmp1()->as_register(); 1258 Register klass_RInfo = op->tmp2()->as_register(); 1259 Register dst = op->result_opr()->as_register(); 1260 ciKlass* k = op->klass(); 1261 Register Rtmp1 = noreg; 1262 1263 // check if it needs to be profiled 1264 ciMethodData* md; 1265 ciProfileData* data; 1266 1267 const bool should_profile = op->should_profile(); 1268 1269 if (should_profile) { 1270 ciMethod* method = op->profiled_method(); 1271 assert(method != nullptr, "Should have method"); 1272 int bci = op->profiled_bci(); 1273 md = method->method_data_or_null(); 1274 assert(md != nullptr, "Sanity"); 1275 data = md->bci_to_data(bci); 1276 assert(data != nullptr, "need data for type check"); 1277 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check"); 1278 } 1279 Label* success_target = success; 1280 Label* failure_target = failure; 1281 1282 if (obj == k_RInfo) { 1283 k_RInfo = dst; 1284 } else if (obj == klass_RInfo) { 1285 klass_RInfo = dst; 1286 } 1287 if (k->is_loaded() && !UseCompressedClassPointers) { 1288 select_different_registers(obj, dst, k_RInfo, klass_RInfo); 1289 } else { 1290 Rtmp1 = op->tmp3()->as_register(); 1291 select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1); 1292 } 1293 1294 assert_different_registers(obj, k_RInfo, klass_RInfo); 1295 1296 if (should_profile) { 1297 Register mdo = klass_RInfo; 1298 __ mov_metadata(mdo, md->constant_encoding()); 1299 Label not_null; 1300 __ cbnz(obj, not_null); 1301 // Object is null; update MDO and exit 1302 Address data_addr 1303 = __ form_address(rscratch2, mdo, 1304 md->byte_offset_of_slot(data, DataLayout::flags_offset()), 1305 0); 1306 __ ldrb(rscratch1, data_addr); 1307 __ orr(rscratch1, rscratch1, BitData::null_seen_byte_constant()); 1308 __ strb(rscratch1, data_addr); 1309 __ b(*obj_is_null); 1310 __ bind(not_null); 1311 1312 Label update_done; 1313 Register recv = k_RInfo; 1314 __ load_klass(recv, obj); 1315 type_profile_helper(mdo, md, data, recv, &update_done); 1316 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset())); 1317 __ addptr(counter_addr, DataLayout::counter_increment); 1318 1319 __ bind(update_done); 1320 } else { 1321 __ cbz(obj, *obj_is_null); 1322 } 1323 1324 if (!k->is_loaded()) { 1325 klass2reg_with_patching(k_RInfo, op->info_for_patch()); 1326 } else { 1327 __ mov_metadata(k_RInfo, k->constant_encoding()); 1328 } 1329 __ verify_oop(obj); 1330 1331 if (op->fast_check()) { 1332 // get object class 1333 // not a safepoint as obj null check happens earlier 1334 __ load_klass(rscratch1, obj); 1335 __ cmp( rscratch1, k_RInfo); 1336 1337 __ br(Assembler::NE, *failure_target); 1338 // successful cast, fall through to profile or jump 1339 } else { 1340 // get object class 1341 // not a safepoint as obj null check happens earlier 1342 __ load_klass(klass_RInfo, obj); 1343 if (k->is_loaded()) { 1344 // See if we get an immediate positive hit 1345 __ ldr(rscratch1, Address(klass_RInfo, int64_t(k->super_check_offset()))); 1346 __ cmp(k_RInfo, rscratch1); 1347 if ((juint)in_bytes(Klass::secondary_super_cache_offset()) != k->super_check_offset()) { 1348 __ br(Assembler::NE, *failure_target); 1349 // successful cast, fall through to profile or jump 1350 } else { 1351 // See if we get an immediate positive hit 1352 __ br(Assembler::EQ, *success_target); 1353 // check for self 1354 __ cmp(klass_RInfo, k_RInfo); 1355 __ br(Assembler::EQ, *success_target); 1356 1357 __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize))); 1358 __ far_call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); 1359 __ ldr(klass_RInfo, Address(__ post(sp, 2 * wordSize))); 1360 // result is a boolean 1361 __ cbzw(klass_RInfo, *failure_target); 1362 // successful cast, fall through to profile or jump 1363 } 1364 } else { 1365 // perform the fast part of the checking logic 1366 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, nullptr); 1367 // call out-of-line instance of __ check_klass_subtype_slow_path(...): 1368 __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize))); 1369 __ far_call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); 1370 __ ldp(k_RInfo, klass_RInfo, Address(__ post(sp, 2 * wordSize))); 1371 // result is a boolean 1372 __ cbz(k_RInfo, *failure_target); 1373 // successful cast, fall through to profile or jump 1374 } 1375 } 1376 __ b(*success); 1377 } 1378 1379 1380 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) { 1381 const bool should_profile = op->should_profile(); 1382 1383 LIR_Code code = op->code(); 1384 if (code == lir_store_check) { 1385 Register value = op->object()->as_register(); 1386 Register array = op->array()->as_register(); 1387 Register k_RInfo = op->tmp1()->as_register(); 1388 Register klass_RInfo = op->tmp2()->as_register(); 1389 Register Rtmp1 = op->tmp3()->as_register(); 1390 1391 CodeStub* stub = op->stub(); 1392 1393 // check if it needs to be profiled 1394 ciMethodData* md; 1395 ciProfileData* data; 1396 1397 if (should_profile) { 1398 ciMethod* method = op->profiled_method(); 1399 assert(method != nullptr, "Should have method"); 1400 int bci = op->profiled_bci(); 1401 md = method->method_data_or_null(); 1402 assert(md != nullptr, "Sanity"); 1403 data = md->bci_to_data(bci); 1404 assert(data != nullptr, "need data for type check"); 1405 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check"); 1406 } 1407 Label done; 1408 Label* success_target = &done; 1409 Label* failure_target = stub->entry(); 1410 1411 if (should_profile) { 1412 Label not_null; 1413 Register mdo = klass_RInfo; 1414 __ mov_metadata(mdo, md->constant_encoding()); 1415 __ cbnz(value, not_null); 1416 // Object is null; update MDO and exit 1417 Address data_addr 1418 = __ form_address(rscratch2, mdo, 1419 md->byte_offset_of_slot(data, DataLayout::flags_offset()), 1420 0); 1421 __ ldrb(rscratch1, data_addr); 1422 __ orr(rscratch1, rscratch1, BitData::null_seen_byte_constant()); 1423 __ strb(rscratch1, data_addr); 1424 __ b(done); 1425 __ bind(not_null); 1426 1427 Label update_done; 1428 Register recv = k_RInfo; 1429 __ load_klass(recv, value); 1430 type_profile_helper(mdo, md, data, recv, &update_done); 1431 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset())); 1432 __ addptr(counter_addr, DataLayout::counter_increment); 1433 __ bind(update_done); 1434 } else { 1435 __ cbz(value, done); 1436 } 1437 1438 add_debug_info_for_null_check_here(op->info_for_exception()); 1439 __ load_klass(k_RInfo, array); 1440 __ load_klass(klass_RInfo, value); 1441 1442 // get instance klass (it's already uncompressed) 1443 __ ldr(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset())); 1444 // perform the fast part of the checking logic 1445 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, nullptr); 1446 // call out-of-line instance of __ check_klass_subtype_slow_path(...): 1447 __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize))); 1448 __ far_call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); 1449 __ ldp(k_RInfo, klass_RInfo, Address(__ post(sp, 2 * wordSize))); 1450 // result is a boolean 1451 __ cbzw(k_RInfo, *failure_target); 1452 // fall through to the success case 1453 1454 __ bind(done); 1455 } else if (code == lir_checkcast) { 1456 Register obj = op->object()->as_register(); 1457 Register dst = op->result_opr()->as_register(); 1458 Label success; 1459 emit_typecheck_helper(op, &success, op->stub()->entry(), &success); 1460 __ bind(success); 1461 if (dst != obj) { 1462 __ mov(dst, obj); 1463 } 1464 } else if (code == lir_instanceof) { 1465 Register obj = op->object()->as_register(); 1466 Register dst = op->result_opr()->as_register(); 1467 Label success, failure, done; 1468 emit_typecheck_helper(op, &success, &failure, &failure); 1469 __ bind(failure); 1470 __ mov(dst, zr); 1471 __ b(done); 1472 __ bind(success); 1473 __ mov(dst, 1); 1474 __ bind(done); 1475 } else { 1476 ShouldNotReachHere(); 1477 } 1478 } 1479 1480 void LIR_Assembler::casw(Register addr, Register newval, Register cmpval) { 1481 __ cmpxchg(addr, cmpval, newval, Assembler::word, /* acquire*/ true, /* release*/ true, /* weak*/ false, rscratch1); 1482 __ cset(rscratch1, Assembler::NE); 1483 __ membar(__ AnyAny); 1484 } 1485 1486 void LIR_Assembler::casl(Register addr, Register newval, Register cmpval) { 1487 __ cmpxchg(addr, cmpval, newval, Assembler::xword, /* acquire*/ true, /* release*/ true, /* weak*/ false, rscratch1); 1488 __ cset(rscratch1, Assembler::NE); 1489 __ membar(__ AnyAny); 1490 } 1491 1492 1493 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) { 1494 Register addr; 1495 if (op->addr()->is_register()) { 1496 addr = as_reg(op->addr()); 1497 } else { 1498 assert(op->addr()->is_address(), "what else?"); 1499 LIR_Address* addr_ptr = op->addr()->as_address_ptr(); 1500 assert(addr_ptr->disp() == 0, "need 0 disp"); 1501 assert(addr_ptr->index() == LIR_Opr::illegalOpr(), "need 0 index"); 1502 addr = as_reg(addr_ptr->base()); 1503 } 1504 Register newval = as_reg(op->new_value()); 1505 Register cmpval = as_reg(op->cmp_value()); 1506 1507 if (op->code() == lir_cas_obj) { 1508 if (UseCompressedOops) { 1509 Register t1 = op->tmp1()->as_register(); 1510 assert(op->tmp1()->is_valid(), "must be"); 1511 __ encode_heap_oop(t1, cmpval); 1512 cmpval = t1; 1513 __ encode_heap_oop(rscratch2, newval); 1514 newval = rscratch2; 1515 casw(addr, newval, cmpval); 1516 } else { 1517 casl(addr, newval, cmpval); 1518 } 1519 } else if (op->code() == lir_cas_int) { 1520 casw(addr, newval, cmpval); 1521 } else { 1522 casl(addr, newval, cmpval); 1523 } 1524 } 1525 1526 1527 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type, 1528 LIR_Opr cmp_opr1, LIR_Opr cmp_opr2) { 1529 assert(cmp_opr1 == LIR_OprFact::illegalOpr && cmp_opr2 == LIR_OprFact::illegalOpr, "unnecessary cmp oprs on aarch64"); 1530 1531 Assembler::Condition acond, ncond; 1532 switch (condition) { 1533 case lir_cond_equal: acond = Assembler::EQ; ncond = Assembler::NE; break; 1534 case lir_cond_notEqual: acond = Assembler::NE; ncond = Assembler::EQ; break; 1535 case lir_cond_less: acond = Assembler::LT; ncond = Assembler::GE; break; 1536 case lir_cond_lessEqual: acond = Assembler::LE; ncond = Assembler::GT; break; 1537 case lir_cond_greaterEqual: acond = Assembler::GE; ncond = Assembler::LT; break; 1538 case lir_cond_greater: acond = Assembler::GT; ncond = Assembler::LE; break; 1539 case lir_cond_belowEqual: 1540 case lir_cond_aboveEqual: 1541 default: ShouldNotReachHere(); 1542 acond = Assembler::EQ; ncond = Assembler::NE; // unreachable 1543 } 1544 1545 assert(result->is_single_cpu() || result->is_double_cpu(), 1546 "expect single register for result"); 1547 if (opr1->is_constant() && opr2->is_constant() 1548 && opr1->type() == T_INT && opr2->type() == T_INT) { 1549 jint val1 = opr1->as_jint(); 1550 jint val2 = opr2->as_jint(); 1551 if (val1 == 0 && val2 == 1) { 1552 __ cset(result->as_register(), ncond); 1553 return; 1554 } else if (val1 == 1 && val2 == 0) { 1555 __ cset(result->as_register(), acond); 1556 return; 1557 } 1558 } 1559 1560 if (opr1->is_constant() && opr2->is_constant() 1561 && opr1->type() == T_LONG && opr2->type() == T_LONG) { 1562 jlong val1 = opr1->as_jlong(); 1563 jlong val2 = opr2->as_jlong(); 1564 if (val1 == 0 && val2 == 1) { 1565 __ cset(result->as_register_lo(), ncond); 1566 return; 1567 } else if (val1 == 1 && val2 == 0) { 1568 __ cset(result->as_register_lo(), acond); 1569 return; 1570 } 1571 } 1572 1573 if (opr1->is_stack()) { 1574 stack2reg(opr1, FrameMap::rscratch1_opr, result->type()); 1575 opr1 = FrameMap::rscratch1_opr; 1576 } else if (opr1->is_constant()) { 1577 LIR_Opr tmp 1578 = opr1->type() == T_LONG ? FrameMap::rscratch1_long_opr : FrameMap::rscratch1_opr; 1579 const2reg(opr1, tmp, lir_patch_none, nullptr); 1580 opr1 = tmp; 1581 } 1582 1583 if (opr2->is_stack()) { 1584 stack2reg(opr2, FrameMap::rscratch2_opr, result->type()); 1585 opr2 = FrameMap::rscratch2_opr; 1586 } else if (opr2->is_constant()) { 1587 LIR_Opr tmp 1588 = opr2->type() == T_LONG ? FrameMap::rscratch2_long_opr : FrameMap::rscratch2_opr; 1589 const2reg(opr2, tmp, lir_patch_none, nullptr); 1590 opr2 = tmp; 1591 } 1592 1593 if (result->type() == T_LONG) 1594 __ csel(result->as_register_lo(), opr1->as_register_lo(), opr2->as_register_lo(), acond); 1595 else 1596 __ csel(result->as_register(), opr1->as_register(), opr2->as_register(), acond); 1597 } 1598 1599 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) { 1600 assert(info == nullptr, "should never be used, idiv/irem and ldiv/lrem not handled by this method"); 1601 1602 if (left->is_single_cpu()) { 1603 Register lreg = left->as_register(); 1604 Register dreg = as_reg(dest); 1605 1606 if (right->is_single_cpu()) { 1607 // cpu register - cpu register 1608 1609 assert(left->type() == T_INT && right->type() == T_INT && dest->type() == T_INT, 1610 "should be"); 1611 Register rreg = right->as_register(); 1612 switch (code) { 1613 case lir_add: __ addw (dest->as_register(), lreg, rreg); break; 1614 case lir_sub: __ subw (dest->as_register(), lreg, rreg); break; 1615 case lir_mul: __ mulw (dest->as_register(), lreg, rreg); break; 1616 default: ShouldNotReachHere(); 1617 } 1618 1619 } else if (right->is_double_cpu()) { 1620 Register rreg = right->as_register_lo(); 1621 // single_cpu + double_cpu: can happen with obj+long 1622 assert(code == lir_add || code == lir_sub, "mismatched arithmetic op"); 1623 switch (code) { 1624 case lir_add: __ add(dreg, lreg, rreg); break; 1625 case lir_sub: __ sub(dreg, lreg, rreg); break; 1626 default: ShouldNotReachHere(); 1627 } 1628 } else if (right->is_constant()) { 1629 // cpu register - constant 1630 jlong c; 1631 1632 // FIXME. This is fugly: we really need to factor all this logic. 1633 switch(right->type()) { 1634 case T_LONG: 1635 c = right->as_constant_ptr()->as_jlong(); 1636 break; 1637 case T_INT: 1638 case T_ADDRESS: 1639 c = right->as_constant_ptr()->as_jint(); 1640 break; 1641 default: 1642 ShouldNotReachHere(); 1643 c = 0; // unreachable 1644 break; 1645 } 1646 1647 assert(code == lir_add || code == lir_sub, "mismatched arithmetic op"); 1648 if (c == 0 && dreg == lreg) { 1649 COMMENT("effective nop elided"); 1650 return; 1651 } 1652 switch(left->type()) { 1653 case T_INT: 1654 switch (code) { 1655 case lir_add: __ addw(dreg, lreg, c); break; 1656 case lir_sub: __ subw(dreg, lreg, c); break; 1657 default: ShouldNotReachHere(); 1658 } 1659 break; 1660 case T_OBJECT: 1661 case T_ADDRESS: 1662 switch (code) { 1663 case lir_add: __ add(dreg, lreg, c); break; 1664 case lir_sub: __ sub(dreg, lreg, c); break; 1665 default: ShouldNotReachHere(); 1666 } 1667 break; 1668 default: 1669 ShouldNotReachHere(); 1670 } 1671 } else { 1672 ShouldNotReachHere(); 1673 } 1674 1675 } else if (left->is_double_cpu()) { 1676 Register lreg_lo = left->as_register_lo(); 1677 1678 if (right->is_double_cpu()) { 1679 // cpu register - cpu register 1680 Register rreg_lo = right->as_register_lo(); 1681 switch (code) { 1682 case lir_add: __ add (dest->as_register_lo(), lreg_lo, rreg_lo); break; 1683 case lir_sub: __ sub (dest->as_register_lo(), lreg_lo, rreg_lo); break; 1684 case lir_mul: __ mul (dest->as_register_lo(), lreg_lo, rreg_lo); break; 1685 case lir_div: __ corrected_idivq(dest->as_register_lo(), lreg_lo, rreg_lo, false, rscratch1); break; 1686 case lir_rem: __ corrected_idivq(dest->as_register_lo(), lreg_lo, rreg_lo, true, rscratch1); break; 1687 default: 1688 ShouldNotReachHere(); 1689 } 1690 1691 } else if (right->is_constant()) { 1692 jlong c = right->as_constant_ptr()->as_jlong(); 1693 Register dreg = as_reg(dest); 1694 switch (code) { 1695 case lir_add: 1696 case lir_sub: 1697 if (c == 0 && dreg == lreg_lo) { 1698 COMMENT("effective nop elided"); 1699 return; 1700 } 1701 code == lir_add ? __ add(dreg, lreg_lo, c) : __ sub(dreg, lreg_lo, c); 1702 break; 1703 case lir_div: 1704 assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant"); 1705 if (c == 1) { 1706 // move lreg_lo to dreg if divisor is 1 1707 __ mov(dreg, lreg_lo); 1708 } else { 1709 unsigned int shift = log2i_exact(c); 1710 // use rscratch1 as intermediate result register 1711 __ asr(rscratch1, lreg_lo, 63); 1712 __ add(rscratch1, lreg_lo, rscratch1, Assembler::LSR, 64 - shift); 1713 __ asr(dreg, rscratch1, shift); 1714 } 1715 break; 1716 case lir_rem: 1717 assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant"); 1718 if (c == 1) { 1719 // move 0 to dreg if divisor is 1 1720 __ mov(dreg, zr); 1721 } else { 1722 // use rscratch1 as intermediate result register 1723 __ negs(rscratch1, lreg_lo); 1724 __ andr(dreg, lreg_lo, c - 1); 1725 __ andr(rscratch1, rscratch1, c - 1); 1726 __ csneg(dreg, dreg, rscratch1, Assembler::MI); 1727 } 1728 break; 1729 default: 1730 ShouldNotReachHere(); 1731 } 1732 } else { 1733 ShouldNotReachHere(); 1734 } 1735 } else if (left->is_single_fpu()) { 1736 assert(right->is_single_fpu(), "right hand side of float arithmetics needs to be float register"); 1737 switch (code) { 1738 case lir_add: __ fadds (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break; 1739 case lir_sub: __ fsubs (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break; 1740 case lir_mul: __ fmuls (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break; 1741 case lir_div: __ fdivs (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break; 1742 default: 1743 ShouldNotReachHere(); 1744 } 1745 } else if (left->is_double_fpu()) { 1746 if (right->is_double_fpu()) { 1747 // fpu register - fpu register 1748 switch (code) { 1749 case lir_add: __ faddd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break; 1750 case lir_sub: __ fsubd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break; 1751 case lir_mul: __ fmuld (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break; 1752 case lir_div: __ fdivd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break; 1753 default: 1754 ShouldNotReachHere(); 1755 } 1756 } else { 1757 if (right->is_constant()) { 1758 ShouldNotReachHere(); 1759 } 1760 ShouldNotReachHere(); 1761 } 1762 } else if (left->is_single_stack() || left->is_address()) { 1763 assert(left == dest, "left and dest must be equal"); 1764 ShouldNotReachHere(); 1765 } else { 1766 ShouldNotReachHere(); 1767 } 1768 } 1769 1770 void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) { Unimplemented(); } 1771 1772 1773 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr tmp, LIR_Opr dest, LIR_Op* op) { 1774 switch(code) { 1775 case lir_abs : __ fabsd(dest->as_double_reg(), value->as_double_reg()); break; 1776 case lir_sqrt: __ fsqrtd(dest->as_double_reg(), value->as_double_reg()); break; 1777 case lir_f2hf: __ flt_to_flt16(dest->as_register(), value->as_float_reg(), tmp->as_float_reg()); break; 1778 case lir_hf2f: __ flt16_to_flt(dest->as_float_reg(), value->as_register(), tmp->as_float_reg()); break; 1779 default : ShouldNotReachHere(); 1780 } 1781 } 1782 1783 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) { 1784 1785 assert(left->is_single_cpu() || left->is_double_cpu(), "expect single or double register"); 1786 Register Rleft = left->is_single_cpu() ? left->as_register() : 1787 left->as_register_lo(); 1788 if (dst->is_single_cpu()) { 1789 Register Rdst = dst->as_register(); 1790 if (right->is_constant()) { 1791 switch (code) { 1792 case lir_logic_and: __ andw (Rdst, Rleft, right->as_jint()); break; 1793 case lir_logic_or: __ orrw (Rdst, Rleft, right->as_jint()); break; 1794 case lir_logic_xor: __ eorw (Rdst, Rleft, right->as_jint()); break; 1795 default: ShouldNotReachHere(); break; 1796 } 1797 } else { 1798 Register Rright = right->is_single_cpu() ? right->as_register() : 1799 right->as_register_lo(); 1800 switch (code) { 1801 case lir_logic_and: __ andw (Rdst, Rleft, Rright); break; 1802 case lir_logic_or: __ orrw (Rdst, Rleft, Rright); break; 1803 case lir_logic_xor: __ eorw (Rdst, Rleft, Rright); break; 1804 default: ShouldNotReachHere(); break; 1805 } 1806 } 1807 } else { 1808 Register Rdst = dst->as_register_lo(); 1809 if (right->is_constant()) { 1810 switch (code) { 1811 case lir_logic_and: __ andr (Rdst, Rleft, right->as_jlong()); break; 1812 case lir_logic_or: __ orr (Rdst, Rleft, right->as_jlong()); break; 1813 case lir_logic_xor: __ eor (Rdst, Rleft, right->as_jlong()); break; 1814 default: ShouldNotReachHere(); break; 1815 } 1816 } else { 1817 Register Rright = right->is_single_cpu() ? right->as_register() : 1818 right->as_register_lo(); 1819 switch (code) { 1820 case lir_logic_and: __ andr (Rdst, Rleft, Rright); break; 1821 case lir_logic_or: __ orr (Rdst, Rleft, Rright); break; 1822 case lir_logic_xor: __ eor (Rdst, Rleft, Rright); break; 1823 default: ShouldNotReachHere(); break; 1824 } 1825 } 1826 } 1827 } 1828 1829 1830 1831 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr illegal, LIR_Opr result, CodeEmitInfo* info) { 1832 1833 // opcode check 1834 assert((code == lir_idiv) || (code == lir_irem), "opcode must be idiv or irem"); 1835 bool is_irem = (code == lir_irem); 1836 1837 // operand check 1838 assert(left->is_single_cpu(), "left must be register"); 1839 assert(right->is_single_cpu() || right->is_constant(), "right must be register or constant"); 1840 assert(result->is_single_cpu(), "result must be register"); 1841 Register lreg = left->as_register(); 1842 Register dreg = result->as_register(); 1843 1844 // power-of-2 constant check and codegen 1845 if (right->is_constant()) { 1846 int c = right->as_constant_ptr()->as_jint(); 1847 assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant"); 1848 if (is_irem) { 1849 if (c == 1) { 1850 // move 0 to dreg if divisor is 1 1851 __ movw(dreg, zr); 1852 } else { 1853 // use rscratch1 as intermediate result register 1854 __ negsw(rscratch1, lreg); 1855 __ andw(dreg, lreg, c - 1); 1856 __ andw(rscratch1, rscratch1, c - 1); 1857 __ csnegw(dreg, dreg, rscratch1, Assembler::MI); 1858 } 1859 } else { 1860 if (c == 1) { 1861 // move lreg to dreg if divisor is 1 1862 __ movw(dreg, lreg); 1863 } else { 1864 unsigned int shift = exact_log2(c); 1865 // use rscratch1 as intermediate result register 1866 __ asrw(rscratch1, lreg, 31); 1867 __ addw(rscratch1, lreg, rscratch1, Assembler::LSR, 32 - shift); 1868 __ asrw(dreg, rscratch1, shift); 1869 } 1870 } 1871 } else { 1872 Register rreg = right->as_register(); 1873 __ corrected_idivl(dreg, lreg, rreg, is_irem, rscratch1); 1874 } 1875 } 1876 1877 1878 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) { 1879 if (opr1->is_constant() && opr2->is_single_cpu()) { 1880 // tableswitch 1881 Register reg = as_reg(opr2); 1882 struct tableswitch &table = switches[opr1->as_constant_ptr()->as_jint()]; 1883 __ tableswitch(reg, table._first_key, table._last_key, table._branches, table._after); 1884 } else if (opr1->is_single_cpu() || opr1->is_double_cpu()) { 1885 Register reg1 = as_reg(opr1); 1886 if (opr2->is_single_cpu()) { 1887 // cpu register - cpu register 1888 Register reg2 = opr2->as_register(); 1889 if (is_reference_type(opr1->type())) { 1890 __ cmpoop(reg1, reg2); 1891 } else { 1892 assert(!is_reference_type(opr2->type()), "cmp int, oop?"); 1893 __ cmpw(reg1, reg2); 1894 } 1895 return; 1896 } 1897 if (opr2->is_double_cpu()) { 1898 // cpu register - cpu register 1899 Register reg2 = opr2->as_register_lo(); 1900 __ cmp(reg1, reg2); 1901 return; 1902 } 1903 1904 if (opr2->is_constant()) { 1905 bool is_32bit = false; // width of register operand 1906 jlong imm; 1907 1908 switch(opr2->type()) { 1909 case T_INT: 1910 imm = opr2->as_constant_ptr()->as_jint(); 1911 is_32bit = true; 1912 break; 1913 case T_LONG: 1914 imm = opr2->as_constant_ptr()->as_jlong(); 1915 break; 1916 case T_ADDRESS: 1917 imm = opr2->as_constant_ptr()->as_jint(); 1918 break; 1919 case T_METADATA: 1920 imm = (intptr_t)(opr2->as_constant_ptr()->as_metadata()); 1921 break; 1922 case T_OBJECT: 1923 case T_ARRAY: 1924 jobject2reg(opr2->as_constant_ptr()->as_jobject(), rscratch1); 1925 __ cmpoop(reg1, rscratch1); 1926 return; 1927 default: 1928 ShouldNotReachHere(); 1929 imm = 0; // unreachable 1930 break; 1931 } 1932 1933 if (Assembler::operand_valid_for_add_sub_immediate(imm)) { 1934 if (is_32bit) 1935 __ cmpw(reg1, imm); 1936 else 1937 __ subs(zr, reg1, imm); 1938 return; 1939 } else { 1940 __ mov(rscratch1, imm); 1941 if (is_32bit) 1942 __ cmpw(reg1, rscratch1); 1943 else 1944 __ cmp(reg1, rscratch1); 1945 return; 1946 } 1947 } else 1948 ShouldNotReachHere(); 1949 } else if (opr1->is_single_fpu()) { 1950 FloatRegister reg1 = opr1->as_float_reg(); 1951 assert(opr2->is_single_fpu(), "expect single float register"); 1952 FloatRegister reg2 = opr2->as_float_reg(); 1953 __ fcmps(reg1, reg2); 1954 } else if (opr1->is_double_fpu()) { 1955 FloatRegister reg1 = opr1->as_double_reg(); 1956 assert(opr2->is_double_fpu(), "expect double float register"); 1957 FloatRegister reg2 = opr2->as_double_reg(); 1958 __ fcmpd(reg1, reg2); 1959 } else { 1960 ShouldNotReachHere(); 1961 } 1962 } 1963 1964 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op){ 1965 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) { 1966 bool is_unordered_less = (code == lir_ucmp_fd2i); 1967 if (left->is_single_fpu()) { 1968 __ float_cmp(true, is_unordered_less ? -1 : 1, left->as_float_reg(), right->as_float_reg(), dst->as_register()); 1969 } else if (left->is_double_fpu()) { 1970 __ float_cmp(false, is_unordered_less ? -1 : 1, left->as_double_reg(), right->as_double_reg(), dst->as_register()); 1971 } else { 1972 ShouldNotReachHere(); 1973 } 1974 } else if (code == lir_cmp_l2i) { 1975 Label done; 1976 __ cmp(left->as_register_lo(), right->as_register_lo()); 1977 __ mov(dst->as_register(), (uint64_t)-1L); 1978 __ br(Assembler::LT, done); 1979 __ csinc(dst->as_register(), zr, zr, Assembler::EQ); 1980 __ bind(done); 1981 } else { 1982 ShouldNotReachHere(); 1983 } 1984 } 1985 1986 1987 void LIR_Assembler::align_call(LIR_Code code) { } 1988 1989 1990 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) { 1991 address call = __ trampoline_call(Address(op->addr(), rtype)); 1992 if (call == nullptr) { 1993 bailout("trampoline stub overflow"); 1994 return; 1995 } 1996 add_call_info(code_offset(), op->info()); 1997 __ post_call_nop(); 1998 } 1999 2000 2001 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) { 2002 address call = __ ic_call(op->addr()); 2003 if (call == nullptr) { 2004 bailout("trampoline stub overflow"); 2005 return; 2006 } 2007 add_call_info(code_offset(), op->info()); 2008 __ post_call_nop(); 2009 } 2010 2011 void LIR_Assembler::emit_static_call_stub() { 2012 address call_pc = __ pc(); 2013 address stub = __ start_a_stub(call_stub_size()); 2014 if (stub == nullptr) { 2015 bailout("static call stub overflow"); 2016 return; 2017 } 2018 2019 int start = __ offset(); 2020 2021 __ relocate(static_stub_Relocation::spec(call_pc)); 2022 __ emit_static_call_stub(); 2023 2024 assert(__ offset() - start + CompiledDirectCall::to_trampoline_stub_size() 2025 <= call_stub_size(), "stub too big"); 2026 __ end_a_stub(); 2027 } 2028 2029 2030 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) { 2031 assert(exceptionOop->as_register() == r0, "must match"); 2032 assert(exceptionPC->as_register() == r3, "must match"); 2033 2034 // exception object is not added to oop map by LinearScan 2035 // (LinearScan assumes that no oops are in fixed registers) 2036 info->add_register_oop(exceptionOop); 2037 Runtime1::StubID unwind_id; 2038 2039 // get current pc information 2040 // pc is only needed if the method has an exception handler, the unwind code does not need it. 2041 if (compilation()->debug_info_recorder()->last_pc_offset() == __ offset()) { 2042 // As no instructions have been generated yet for this LIR node it's 2043 // possible that an oop map already exists for the current offset. 2044 // In that case insert an dummy NOP here to ensure all oop map PCs 2045 // are unique. See JDK-8237483. 2046 __ nop(); 2047 } 2048 int pc_for_athrow_offset = __ offset(); 2049 InternalAddress pc_for_athrow(__ pc()); 2050 __ adr(exceptionPC->as_register(), pc_for_athrow); 2051 add_call_info(pc_for_athrow_offset, info); // for exception handler 2052 2053 __ verify_not_null_oop(r0); 2054 // search an exception handler (r0: exception oop, r3: throwing pc) 2055 if (compilation()->has_fpu_code()) { 2056 unwind_id = Runtime1::handle_exception_id; 2057 } else { 2058 unwind_id = Runtime1::handle_exception_nofpu_id; 2059 } 2060 __ far_call(RuntimeAddress(Runtime1::entry_for(unwind_id))); 2061 2062 // FIXME: enough room for two byte trap ???? 2063 __ nop(); 2064 } 2065 2066 2067 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) { 2068 assert(exceptionOop->as_register() == r0, "must match"); 2069 2070 __ b(_unwind_handler_entry); 2071 } 2072 2073 2074 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) { 2075 Register lreg = left->is_single_cpu() ? left->as_register() : left->as_register_lo(); 2076 Register dreg = dest->is_single_cpu() ? dest->as_register() : dest->as_register_lo(); 2077 2078 switch (left->type()) { 2079 case T_INT: { 2080 switch (code) { 2081 case lir_shl: __ lslvw (dreg, lreg, count->as_register()); break; 2082 case lir_shr: __ asrvw (dreg, lreg, count->as_register()); break; 2083 case lir_ushr: __ lsrvw (dreg, lreg, count->as_register()); break; 2084 default: 2085 ShouldNotReachHere(); 2086 break; 2087 } 2088 break; 2089 case T_LONG: 2090 case T_ADDRESS: 2091 case T_OBJECT: 2092 switch (code) { 2093 case lir_shl: __ lslv (dreg, lreg, count->as_register()); break; 2094 case lir_shr: __ asrv (dreg, lreg, count->as_register()); break; 2095 case lir_ushr: __ lsrv (dreg, lreg, count->as_register()); break; 2096 default: 2097 ShouldNotReachHere(); 2098 break; 2099 } 2100 break; 2101 default: 2102 ShouldNotReachHere(); 2103 break; 2104 } 2105 } 2106 } 2107 2108 2109 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) { 2110 Register dreg = dest->is_single_cpu() ? dest->as_register() : dest->as_register_lo(); 2111 Register lreg = left->is_single_cpu() ? left->as_register() : left->as_register_lo(); 2112 2113 switch (left->type()) { 2114 case T_INT: { 2115 switch (code) { 2116 case lir_shl: __ lslw (dreg, lreg, count); break; 2117 case lir_shr: __ asrw (dreg, lreg, count); break; 2118 case lir_ushr: __ lsrw (dreg, lreg, count); break; 2119 default: 2120 ShouldNotReachHere(); 2121 break; 2122 } 2123 break; 2124 case T_LONG: 2125 case T_ADDRESS: 2126 case T_OBJECT: 2127 switch (code) { 2128 case lir_shl: __ lsl (dreg, lreg, count); break; 2129 case lir_shr: __ asr (dreg, lreg, count); break; 2130 case lir_ushr: __ lsr (dreg, lreg, count); break; 2131 default: 2132 ShouldNotReachHere(); 2133 break; 2134 } 2135 break; 2136 default: 2137 ShouldNotReachHere(); 2138 break; 2139 } 2140 } 2141 } 2142 2143 2144 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) { 2145 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); 2146 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; 2147 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); 2148 __ str (r, Address(sp, offset_from_rsp_in_bytes)); 2149 } 2150 2151 2152 void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) { 2153 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); 2154 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; 2155 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); 2156 __ mov (rscratch1, c); 2157 __ str (rscratch1, Address(sp, offset_from_rsp_in_bytes)); 2158 } 2159 2160 2161 void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) { 2162 ShouldNotReachHere(); 2163 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); 2164 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; 2165 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); 2166 __ lea(rscratch1, __ constant_oop_address(o)); 2167 __ str(rscratch1, Address(sp, offset_from_rsp_in_bytes)); 2168 } 2169 2170 2171 // This code replaces a call to arraycopy; no exception may 2172 // be thrown in this code, they must be thrown in the System.arraycopy 2173 // activation frame; we could save some checks if this would not be the case 2174 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) { 2175 ciArrayKlass* default_type = op->expected_type(); 2176 Register src = op->src()->as_register(); 2177 Register dst = op->dst()->as_register(); 2178 Register src_pos = op->src_pos()->as_register(); 2179 Register dst_pos = op->dst_pos()->as_register(); 2180 Register length = op->length()->as_register(); 2181 Register tmp = op->tmp()->as_register(); 2182 2183 CodeStub* stub = op->stub(); 2184 int flags = op->flags(); 2185 BasicType basic_type = default_type != nullptr ? default_type->element_type()->basic_type() : T_ILLEGAL; 2186 if (is_reference_type(basic_type)) basic_type = T_OBJECT; 2187 2188 // if we don't know anything, just go through the generic arraycopy 2189 if (default_type == nullptr // || basic_type == T_OBJECT 2190 ) { 2191 Label done; 2192 assert(src == r1 && src_pos == r2, "mismatch in calling convention"); 2193 2194 // Save the arguments in case the generic arraycopy fails and we 2195 // have to fall back to the JNI stub 2196 __ stp(dst, dst_pos, Address(sp, 0*BytesPerWord)); 2197 __ stp(length, src_pos, Address(sp, 2*BytesPerWord)); 2198 __ str(src, Address(sp, 4*BytesPerWord)); 2199 2200 address copyfunc_addr = StubRoutines::generic_arraycopy(); 2201 assert(copyfunc_addr != nullptr, "generic arraycopy stub required"); 2202 2203 // The arguments are in java calling convention so we shift them 2204 // to C convention 2205 assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4); 2206 __ mov(c_rarg0, j_rarg0); 2207 assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4); 2208 __ mov(c_rarg1, j_rarg1); 2209 assert_different_registers(c_rarg2, j_rarg3, j_rarg4); 2210 __ mov(c_rarg2, j_rarg2); 2211 assert_different_registers(c_rarg3, j_rarg4); 2212 __ mov(c_rarg3, j_rarg3); 2213 __ mov(c_rarg4, j_rarg4); 2214 #ifndef PRODUCT 2215 if (PrintC1Statistics) { 2216 __ incrementw(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt)); 2217 } 2218 #endif 2219 __ far_call(RuntimeAddress(copyfunc_addr)); 2220 2221 __ cbz(r0, *stub->continuation()); 2222 2223 // Reload values from the stack so they are where the stub 2224 // expects them. 2225 __ ldp(dst, dst_pos, Address(sp, 0*BytesPerWord)); 2226 __ ldp(length, src_pos, Address(sp, 2*BytesPerWord)); 2227 __ ldr(src, Address(sp, 4*BytesPerWord)); 2228 2229 // r0 is -1^K where K == partial copied count 2230 __ eonw(rscratch1, r0, zr); 2231 // adjust length down and src/end pos up by partial copied count 2232 __ subw(length, length, rscratch1); 2233 __ addw(src_pos, src_pos, rscratch1); 2234 __ addw(dst_pos, dst_pos, rscratch1); 2235 __ b(*stub->entry()); 2236 2237 __ bind(*stub->continuation()); 2238 return; 2239 } 2240 2241 assert(default_type != nullptr && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point"); 2242 2243 int elem_size = type2aelembytes(basic_type); 2244 int scale = exact_log2(elem_size); 2245 2246 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes()); 2247 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes()); 2248 2249 // test for null 2250 if (flags & LIR_OpArrayCopy::src_null_check) { 2251 __ cbz(src, *stub->entry()); 2252 } 2253 if (flags & LIR_OpArrayCopy::dst_null_check) { 2254 __ cbz(dst, *stub->entry()); 2255 } 2256 2257 // If the compiler was not able to prove that exact type of the source or the destination 2258 // of the arraycopy is an array type, check at runtime if the source or the destination is 2259 // an instance type. 2260 if (flags & LIR_OpArrayCopy::type_check) { 2261 if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::dst_objarray)) { 2262 __ load_klass(tmp, dst); 2263 __ ldrw(rscratch1, Address(tmp, in_bytes(Klass::layout_helper_offset()))); 2264 __ cmpw(rscratch1, Klass::_lh_neutral_value); 2265 __ br(Assembler::GE, *stub->entry()); 2266 } 2267 2268 if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::src_objarray)) { 2269 __ load_klass(tmp, src); 2270 __ ldrw(rscratch1, Address(tmp, in_bytes(Klass::layout_helper_offset()))); 2271 __ cmpw(rscratch1, Klass::_lh_neutral_value); 2272 __ br(Assembler::GE, *stub->entry()); 2273 } 2274 } 2275 2276 // check if negative 2277 if (flags & LIR_OpArrayCopy::src_pos_positive_check) { 2278 __ cmpw(src_pos, 0); 2279 __ br(Assembler::LT, *stub->entry()); 2280 } 2281 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) { 2282 __ cmpw(dst_pos, 0); 2283 __ br(Assembler::LT, *stub->entry()); 2284 } 2285 2286 if (flags & LIR_OpArrayCopy::length_positive_check) { 2287 __ cmpw(length, 0); 2288 __ br(Assembler::LT, *stub->entry()); 2289 } 2290 2291 if (flags & LIR_OpArrayCopy::src_range_check) { 2292 __ addw(tmp, src_pos, length); 2293 __ ldrw(rscratch1, src_length_addr); 2294 __ cmpw(tmp, rscratch1); 2295 __ br(Assembler::HI, *stub->entry()); 2296 } 2297 if (flags & LIR_OpArrayCopy::dst_range_check) { 2298 __ addw(tmp, dst_pos, length); 2299 __ ldrw(rscratch1, dst_length_addr); 2300 __ cmpw(tmp, rscratch1); 2301 __ br(Assembler::HI, *stub->entry()); 2302 } 2303 2304 if (flags & LIR_OpArrayCopy::type_check) { 2305 // We don't know the array types are compatible 2306 if (basic_type != T_OBJECT) { 2307 // Simple test for basic type arrays 2308 __ cmp_klass(src, dst, tmp, rscratch1); 2309 __ br(Assembler::NE, *stub->entry()); 2310 } else { 2311 // For object arrays, if src is a sub class of dst then we can 2312 // safely do the copy. 2313 Label cont, slow; 2314 2315 #define PUSH(r1, r2) \ 2316 stp(r1, r2, __ pre(sp, -2 * wordSize)); 2317 2318 #define POP(r1, r2) \ 2319 ldp(r1, r2, __ post(sp, 2 * wordSize)); 2320 2321 __ PUSH(src, dst); 2322 2323 __ load_klass(src, src); 2324 __ load_klass(dst, dst); 2325 2326 __ check_klass_subtype_fast_path(src, dst, tmp, &cont, &slow, nullptr); 2327 2328 __ PUSH(src, dst); 2329 __ far_call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); 2330 __ POP(src, dst); 2331 2332 __ cbnz(src, cont); 2333 2334 __ bind(slow); 2335 __ POP(src, dst); 2336 2337 address copyfunc_addr = StubRoutines::checkcast_arraycopy(); 2338 if (copyfunc_addr != nullptr) { // use stub if available 2339 // src is not a sub class of dst so we have to do a 2340 // per-element check. 2341 2342 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray; 2343 if ((flags & mask) != mask) { 2344 // Check that at least both of them object arrays. 2345 assert(flags & mask, "one of the two should be known to be an object array"); 2346 2347 if (!(flags & LIR_OpArrayCopy::src_objarray)) { 2348 __ load_klass(tmp, src); 2349 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) { 2350 __ load_klass(tmp, dst); 2351 } 2352 int lh_offset = in_bytes(Klass::layout_helper_offset()); 2353 Address klass_lh_addr(tmp, lh_offset); 2354 jint objArray_lh = Klass::array_layout_helper(T_OBJECT); 2355 __ ldrw(rscratch1, klass_lh_addr); 2356 __ mov(rscratch2, objArray_lh); 2357 __ eorw(rscratch1, rscratch1, rscratch2); 2358 __ cbnzw(rscratch1, *stub->entry()); 2359 } 2360 2361 // Spill because stubs can use any register they like and it's 2362 // easier to restore just those that we care about. 2363 __ stp(dst, dst_pos, Address(sp, 0*BytesPerWord)); 2364 __ stp(length, src_pos, Address(sp, 2*BytesPerWord)); 2365 __ str(src, Address(sp, 4*BytesPerWord)); 2366 2367 __ lea(c_rarg0, Address(src, src_pos, Address::uxtw(scale))); 2368 __ add(c_rarg0, c_rarg0, arrayOopDesc::base_offset_in_bytes(basic_type)); 2369 assert_different_registers(c_rarg0, dst, dst_pos, length); 2370 __ lea(c_rarg1, Address(dst, dst_pos, Address::uxtw(scale))); 2371 __ add(c_rarg1, c_rarg1, arrayOopDesc::base_offset_in_bytes(basic_type)); 2372 assert_different_registers(c_rarg1, dst, length); 2373 __ uxtw(c_rarg2, length); 2374 assert_different_registers(c_rarg2, dst); 2375 2376 __ load_klass(c_rarg4, dst); 2377 __ ldr(c_rarg4, Address(c_rarg4, ObjArrayKlass::element_klass_offset())); 2378 __ ldrw(c_rarg3, Address(c_rarg4, Klass::super_check_offset_offset())); 2379 __ far_call(RuntimeAddress(copyfunc_addr)); 2380 2381 #ifndef PRODUCT 2382 if (PrintC1Statistics) { 2383 Label failed; 2384 __ cbnz(r0, failed); 2385 __ incrementw(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt)); 2386 __ bind(failed); 2387 } 2388 #endif 2389 2390 __ cbz(r0, *stub->continuation()); 2391 2392 #ifndef PRODUCT 2393 if (PrintC1Statistics) { 2394 __ incrementw(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt)); 2395 } 2396 #endif 2397 assert_different_registers(dst, dst_pos, length, src_pos, src, r0, rscratch1); 2398 2399 // Restore previously spilled arguments 2400 __ ldp(dst, dst_pos, Address(sp, 0*BytesPerWord)); 2401 __ ldp(length, src_pos, Address(sp, 2*BytesPerWord)); 2402 __ ldr(src, Address(sp, 4*BytesPerWord)); 2403 2404 // return value is -1^K where K is partial copied count 2405 __ eonw(rscratch1, r0, zr); 2406 // adjust length down and src/end pos up by partial copied count 2407 __ subw(length, length, rscratch1); 2408 __ addw(src_pos, src_pos, rscratch1); 2409 __ addw(dst_pos, dst_pos, rscratch1); 2410 } 2411 2412 __ b(*stub->entry()); 2413 2414 __ bind(cont); 2415 __ POP(src, dst); 2416 } 2417 } 2418 2419 #ifdef ASSERT 2420 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) { 2421 // Sanity check the known type with the incoming class. For the 2422 // primitive case the types must match exactly with src.klass and 2423 // dst.klass each exactly matching the default type. For the 2424 // object array case, if no type check is needed then either the 2425 // dst type is exactly the expected type and the src type is a 2426 // subtype which we can't check or src is the same array as dst 2427 // but not necessarily exactly of type default_type. 2428 Label known_ok, halt; 2429 __ mov_metadata(tmp, default_type->constant_encoding()); 2430 2431 if (basic_type != T_OBJECT) { 2432 __ cmp_klass(dst, tmp, rscratch1); 2433 __ br(Assembler::NE, halt); 2434 __ cmp_klass(src, tmp, rscratch1); 2435 __ br(Assembler::EQ, known_ok); 2436 } else { 2437 __ cmp_klass(dst, tmp, rscratch1); 2438 __ br(Assembler::EQ, known_ok); 2439 __ cmp(src, dst); 2440 __ br(Assembler::EQ, known_ok); 2441 } 2442 __ bind(halt); 2443 __ stop("incorrect type information in arraycopy"); 2444 __ bind(known_ok); 2445 } 2446 #endif 2447 2448 #ifndef PRODUCT 2449 if (PrintC1Statistics) { 2450 __ incrementw(ExternalAddress(Runtime1::arraycopy_count_address(basic_type))); 2451 } 2452 #endif 2453 2454 __ lea(c_rarg0, Address(src, src_pos, Address::uxtw(scale))); 2455 __ add(c_rarg0, c_rarg0, arrayOopDesc::base_offset_in_bytes(basic_type)); 2456 assert_different_registers(c_rarg0, dst, dst_pos, length); 2457 __ lea(c_rarg1, Address(dst, dst_pos, Address::uxtw(scale))); 2458 __ add(c_rarg1, c_rarg1, arrayOopDesc::base_offset_in_bytes(basic_type)); 2459 assert_different_registers(c_rarg1, dst, length); 2460 __ uxtw(c_rarg2, length); 2461 assert_different_registers(c_rarg2, dst); 2462 2463 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0; 2464 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0; 2465 const char *name; 2466 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false); 2467 2468 CodeBlob *cb = CodeCache::find_blob(entry); 2469 if (cb) { 2470 __ far_call(RuntimeAddress(entry)); 2471 } else { 2472 __ call_VM_leaf(entry, 3); 2473 } 2474 2475 __ bind(*stub->continuation()); 2476 } 2477 2478 2479 2480 2481 void LIR_Assembler::emit_lock(LIR_OpLock* op) { 2482 Register obj = op->obj_opr()->as_register(); // may not be an oop 2483 Register hdr = op->hdr_opr()->as_register(); 2484 Register lock = op->lock_opr()->as_register(); 2485 Register temp = op->scratch_opr()->as_register(); 2486 if (LockingMode == LM_MONITOR) { 2487 if (op->info() != nullptr) { 2488 add_debug_info_for_null_check_here(op->info()); 2489 __ null_check(obj, -1); 2490 } 2491 __ b(*op->stub()->entry()); 2492 } else if (op->code() == lir_lock) { 2493 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); 2494 // add debug info for NullPointerException only if one is possible 2495 int null_check_offset = __ lock_object(hdr, obj, lock, temp, *op->stub()->entry()); 2496 if (op->info() != nullptr) { 2497 add_debug_info_for_null_check(null_check_offset, op->info()); 2498 } 2499 // done 2500 } else if (op->code() == lir_unlock) { 2501 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); 2502 __ unlock_object(hdr, obj, lock, temp, *op->stub()->entry()); 2503 } else { 2504 Unimplemented(); 2505 } 2506 __ bind(*op->stub()->continuation()); 2507 } 2508 2509 void LIR_Assembler::emit_load_klass(LIR_OpLoadKlass* op) { 2510 Register obj = op->obj()->as_pointer_register(); 2511 Register result = op->result_opr()->as_pointer_register(); 2512 2513 CodeEmitInfo* info = op->info(); 2514 if (info != nullptr) { 2515 add_debug_info_for_null_check_here(info); 2516 } 2517 2518 if (UseCompressedClassPointers) { 2519 if (UseCompactObjectHeaders) { 2520 __ ldr(result, Address(obj, oopDesc::mark_offset_in_bytes())); 2521 __ lsr(result, result, markWord::klass_shift); 2522 } else { 2523 __ ldrw(result, Address (obj, oopDesc::klass_offset_in_bytes())); 2524 } 2525 __ decode_klass_not_null(result); 2526 } else { 2527 __ ldr(result, Address (obj, oopDesc::klass_offset_in_bytes())); 2528 } 2529 } 2530 2531 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) { 2532 ciMethod* method = op->profiled_method(); 2533 int bci = op->profiled_bci(); 2534 ciMethod* callee = op->profiled_callee(); 2535 2536 // Update counter for all call types 2537 ciMethodData* md = method->method_data_or_null(); 2538 assert(md != nullptr, "Sanity"); 2539 ciProfileData* data = md->bci_to_data(bci); 2540 assert(data != nullptr && data->is_CounterData(), "need CounterData for calls"); 2541 assert(op->mdo()->is_single_cpu(), "mdo must be allocated"); 2542 Register mdo = op->mdo()->as_register(); 2543 __ mov_metadata(mdo, md->constant_encoding()); 2544 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset())); 2545 // Perform additional virtual call profiling for invokevirtual and 2546 // invokeinterface bytecodes 2547 if (op->should_profile_receiver_type()) { 2548 assert(op->recv()->is_single_cpu(), "recv must be allocated"); 2549 Register recv = op->recv()->as_register(); 2550 assert_different_registers(mdo, recv); 2551 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls"); 2552 ciKlass* known_klass = op->known_holder(); 2553 if (C1OptimizeVirtualCallProfiling && known_klass != nullptr) { 2554 // We know the type that will be seen at this call site; we can 2555 // statically update the MethodData* rather than needing to do 2556 // dynamic tests on the receiver type 2557 2558 // NOTE: we should probably put a lock around this search to 2559 // avoid collisions by concurrent compilations 2560 ciVirtualCallData* vc_data = (ciVirtualCallData*) data; 2561 uint i; 2562 for (i = 0; i < VirtualCallData::row_limit(); i++) { 2563 ciKlass* receiver = vc_data->receiver(i); 2564 if (known_klass->equals(receiver)) { 2565 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i))); 2566 __ addptr(data_addr, DataLayout::counter_increment); 2567 return; 2568 } 2569 } 2570 2571 // Receiver type not found in profile data; select an empty slot 2572 2573 // Note that this is less efficient than it should be because it 2574 // always does a write to the receiver part of the 2575 // VirtualCallData rather than just the first time 2576 for (i = 0; i < VirtualCallData::row_limit(); i++) { 2577 ciKlass* receiver = vc_data->receiver(i); 2578 if (receiver == nullptr) { 2579 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i))); 2580 __ mov_metadata(rscratch1, known_klass->constant_encoding()); 2581 __ lea(rscratch2, recv_addr); 2582 __ str(rscratch1, Address(rscratch2)); 2583 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i))); 2584 __ addptr(data_addr, DataLayout::counter_increment); 2585 return; 2586 } 2587 } 2588 } else { 2589 __ load_klass(recv, recv); 2590 Label update_done; 2591 type_profile_helper(mdo, md, data, recv, &update_done); 2592 // Receiver did not match any saved receiver and there is no empty row for it. 2593 // Increment total counter to indicate polymorphic case. 2594 __ addptr(counter_addr, DataLayout::counter_increment); 2595 2596 __ bind(update_done); 2597 } 2598 } else { 2599 // Static call 2600 __ addptr(counter_addr, DataLayout::counter_increment); 2601 } 2602 } 2603 2604 2605 void LIR_Assembler::emit_delay(LIR_OpDelay*) { 2606 Unimplemented(); 2607 } 2608 2609 2610 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) { 2611 __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no)); 2612 } 2613 2614 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) { 2615 assert(op->crc()->is_single_cpu(), "crc must be register"); 2616 assert(op->val()->is_single_cpu(), "byte value must be register"); 2617 assert(op->result_opr()->is_single_cpu(), "result must be register"); 2618 Register crc = op->crc()->as_register(); 2619 Register val = op->val()->as_register(); 2620 Register res = op->result_opr()->as_register(); 2621 2622 assert_different_registers(val, crc, res); 2623 uint64_t offset; 2624 __ adrp(res, ExternalAddress(StubRoutines::crc_table_addr()), offset); 2625 __ add(res, res, offset); 2626 2627 __ mvnw(crc, crc); // ~crc 2628 __ update_byte_crc32(crc, val, res); 2629 __ mvnw(res, crc); // ~crc 2630 } 2631 2632 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) { 2633 COMMENT("emit_profile_type {"); 2634 Register obj = op->obj()->as_register(); 2635 Register tmp = op->tmp()->as_pointer_register(); 2636 Address mdo_addr = as_Address(op->mdp()->as_address_ptr()); 2637 ciKlass* exact_klass = op->exact_klass(); 2638 intptr_t current_klass = op->current_klass(); 2639 bool not_null = op->not_null(); 2640 bool no_conflict = op->no_conflict(); 2641 2642 Label update, next, none; 2643 2644 bool do_null = !not_null; 2645 bool exact_klass_set = exact_klass != nullptr && ciTypeEntries::valid_ciklass(current_klass) == exact_klass; 2646 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set; 2647 2648 assert(do_null || do_update, "why are we here?"); 2649 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?"); 2650 assert(mdo_addr.base() != rscratch1, "wrong register"); 2651 2652 __ verify_oop(obj); 2653 2654 if (tmp != obj) { 2655 assert_different_registers(obj, tmp, rscratch1, rscratch2, mdo_addr.base(), mdo_addr.index()); 2656 __ mov(tmp, obj); 2657 } else { 2658 assert_different_registers(obj, rscratch1, rscratch2, mdo_addr.base(), mdo_addr.index()); 2659 } 2660 if (do_null) { 2661 __ cbnz(tmp, update); 2662 if (!TypeEntries::was_null_seen(current_klass)) { 2663 __ ldr(rscratch2, mdo_addr); 2664 __ orr(rscratch2, rscratch2, TypeEntries::null_seen); 2665 __ str(rscratch2, mdo_addr); 2666 } 2667 if (do_update) { 2668 #ifndef ASSERT 2669 __ b(next); 2670 } 2671 #else 2672 __ b(next); 2673 } 2674 } else { 2675 __ cbnz(tmp, update); 2676 __ stop("unexpected null obj"); 2677 #endif 2678 } 2679 2680 __ bind(update); 2681 2682 if (do_update) { 2683 #ifdef ASSERT 2684 if (exact_klass != nullptr) { 2685 Label ok; 2686 __ load_klass(tmp, tmp); 2687 __ mov_metadata(rscratch1, exact_klass->constant_encoding()); 2688 __ eor(rscratch1, tmp, rscratch1); 2689 __ cbz(rscratch1, ok); 2690 __ stop("exact klass and actual klass differ"); 2691 __ bind(ok); 2692 } 2693 #endif 2694 if (!no_conflict) { 2695 if (exact_klass == nullptr || TypeEntries::is_type_none(current_klass)) { 2696 if (exact_klass != nullptr) { 2697 __ mov_metadata(tmp, exact_klass->constant_encoding()); 2698 } else { 2699 __ load_klass(tmp, tmp); 2700 } 2701 2702 __ ldr(rscratch2, mdo_addr); 2703 __ eor(tmp, tmp, rscratch2); 2704 __ andr(rscratch1, tmp, TypeEntries::type_klass_mask); 2705 // klass seen before, nothing to do. The unknown bit may have been 2706 // set already but no need to check. 2707 __ cbz(rscratch1, next); 2708 2709 __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore. 2710 2711 if (TypeEntries::is_type_none(current_klass)) { 2712 __ cbz(rscratch2, none); 2713 __ cmp(rscratch2, (u1)TypeEntries::null_seen); 2714 __ br(Assembler::EQ, none); 2715 // There is a chance that the checks above 2716 // fail if another thread has just set the 2717 // profiling to this obj's klass 2718 __ dmb(Assembler::ISHLD); 2719 __ eor(tmp, tmp, rscratch2); // get back original value before XOR 2720 __ ldr(rscratch2, mdo_addr); 2721 __ eor(tmp, tmp, rscratch2); 2722 __ andr(rscratch1, tmp, TypeEntries::type_klass_mask); 2723 __ cbz(rscratch1, next); 2724 } 2725 } else { 2726 assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr && 2727 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only"); 2728 2729 __ ldr(tmp, mdo_addr); 2730 __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore. 2731 } 2732 2733 // different than before. Cannot keep accurate profile. 2734 __ ldr(rscratch2, mdo_addr); 2735 __ orr(rscratch2, rscratch2, TypeEntries::type_unknown); 2736 __ str(rscratch2, mdo_addr); 2737 2738 if (TypeEntries::is_type_none(current_klass)) { 2739 __ b(next); 2740 2741 __ bind(none); 2742 // first time here. Set profile type. 2743 __ str(tmp, mdo_addr); 2744 #ifdef ASSERT 2745 __ andr(tmp, tmp, TypeEntries::type_mask); 2746 __ verify_klass_ptr(tmp); 2747 #endif 2748 } 2749 } else { 2750 // There's a single possible klass at this profile point 2751 assert(exact_klass != nullptr, "should be"); 2752 if (TypeEntries::is_type_none(current_klass)) { 2753 __ mov_metadata(tmp, exact_klass->constant_encoding()); 2754 __ ldr(rscratch2, mdo_addr); 2755 __ eor(tmp, tmp, rscratch2); 2756 __ andr(rscratch1, tmp, TypeEntries::type_klass_mask); 2757 __ cbz(rscratch1, next); 2758 #ifdef ASSERT 2759 { 2760 Label ok; 2761 __ ldr(rscratch1, mdo_addr); 2762 __ cbz(rscratch1, ok); 2763 __ cmp(rscratch1, (u1)TypeEntries::null_seen); 2764 __ br(Assembler::EQ, ok); 2765 // may have been set by another thread 2766 __ dmb(Assembler::ISHLD); 2767 __ mov_metadata(rscratch1, exact_klass->constant_encoding()); 2768 __ ldr(rscratch2, mdo_addr); 2769 __ eor(rscratch2, rscratch1, rscratch2); 2770 __ andr(rscratch2, rscratch2, TypeEntries::type_mask); 2771 __ cbz(rscratch2, ok); 2772 2773 __ stop("unexpected profiling mismatch"); 2774 __ bind(ok); 2775 } 2776 #endif 2777 // first time here. Set profile type. 2778 __ str(tmp, mdo_addr); 2779 #ifdef ASSERT 2780 __ andr(tmp, tmp, TypeEntries::type_mask); 2781 __ verify_klass_ptr(tmp); 2782 #endif 2783 } else { 2784 assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr && 2785 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent"); 2786 2787 __ ldr(tmp, mdo_addr); 2788 __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore. 2789 2790 __ orr(tmp, tmp, TypeEntries::type_unknown); 2791 __ str(tmp, mdo_addr); 2792 // FIXME: Write barrier needed here? 2793 } 2794 } 2795 2796 __ bind(next); 2797 } 2798 COMMENT("} emit_profile_type"); 2799 } 2800 2801 2802 void LIR_Assembler::align_backward_branch_target() { 2803 } 2804 2805 2806 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) { 2807 // tmp must be unused 2808 assert(tmp->is_illegal(), "wasting a register if tmp is allocated"); 2809 2810 if (left->is_single_cpu()) { 2811 assert(dest->is_single_cpu(), "expect single result reg"); 2812 __ negw(dest->as_register(), left->as_register()); 2813 } else if (left->is_double_cpu()) { 2814 assert(dest->is_double_cpu(), "expect double result reg"); 2815 __ neg(dest->as_register_lo(), left->as_register_lo()); 2816 } else if (left->is_single_fpu()) { 2817 assert(dest->is_single_fpu(), "expect single float result reg"); 2818 __ fnegs(dest->as_float_reg(), left->as_float_reg()); 2819 } else { 2820 assert(left->is_double_fpu(), "expect double float operand reg"); 2821 assert(dest->is_double_fpu(), "expect double float result reg"); 2822 __ fnegd(dest->as_double_reg(), left->as_double_reg()); 2823 } 2824 } 2825 2826 2827 void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) { 2828 if (patch_code != lir_patch_none) { 2829 deoptimize_trap(info); 2830 return; 2831 } 2832 2833 __ lea(dest->as_register_lo(), as_Address(addr->as_address_ptr())); 2834 } 2835 2836 2837 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) { 2838 assert(!tmp->is_valid(), "don't need temporary"); 2839 2840 CodeBlob *cb = CodeCache::find_blob(dest); 2841 if (cb) { 2842 __ far_call(RuntimeAddress(dest)); 2843 } else { 2844 __ mov(rscratch1, RuntimeAddress(dest)); 2845 __ blr(rscratch1); 2846 } 2847 2848 if (info != nullptr) { 2849 add_call_info_here(info); 2850 } 2851 __ post_call_nop(); 2852 } 2853 2854 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) { 2855 if (dest->is_address() || src->is_address()) { 2856 move_op(src, dest, type, lir_patch_none, info, 2857 /*pop_fpu_stack*/false, /*wide*/false); 2858 } else { 2859 ShouldNotReachHere(); 2860 } 2861 } 2862 2863 #ifdef ASSERT 2864 // emit run-time assertion 2865 void LIR_Assembler::emit_assert(LIR_OpAssert* op) { 2866 assert(op->code() == lir_assert, "must be"); 2867 2868 if (op->in_opr1()->is_valid()) { 2869 assert(op->in_opr2()->is_valid(), "both operands must be valid"); 2870 comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op); 2871 } else { 2872 assert(op->in_opr2()->is_illegal(), "both operands must be illegal"); 2873 assert(op->condition() == lir_cond_always, "no other conditions allowed"); 2874 } 2875 2876 Label ok; 2877 if (op->condition() != lir_cond_always) { 2878 Assembler::Condition acond = Assembler::AL; 2879 switch (op->condition()) { 2880 case lir_cond_equal: acond = Assembler::EQ; break; 2881 case lir_cond_notEqual: acond = Assembler::NE; break; 2882 case lir_cond_less: acond = Assembler::LT; break; 2883 case lir_cond_lessEqual: acond = Assembler::LE; break; 2884 case lir_cond_greaterEqual: acond = Assembler::GE; break; 2885 case lir_cond_greater: acond = Assembler::GT; break; 2886 case lir_cond_belowEqual: acond = Assembler::LS; break; 2887 case lir_cond_aboveEqual: acond = Assembler::HS; break; 2888 default: ShouldNotReachHere(); 2889 } 2890 __ br(acond, ok); 2891 } 2892 if (op->halt()) { 2893 const char* str = __ code_string(op->msg()); 2894 __ stop(str); 2895 } else { 2896 breakpoint(); 2897 } 2898 __ bind(ok); 2899 } 2900 #endif 2901 2902 #ifndef PRODUCT 2903 #define COMMENT(x) do { __ block_comment(x); } while (0) 2904 #else 2905 #define COMMENT(x) 2906 #endif 2907 2908 void LIR_Assembler::membar() { 2909 COMMENT("membar"); 2910 __ membar(MacroAssembler::AnyAny); 2911 } 2912 2913 void LIR_Assembler::membar_acquire() { 2914 __ membar(Assembler::LoadLoad|Assembler::LoadStore); 2915 } 2916 2917 void LIR_Assembler::membar_release() { 2918 __ membar(Assembler::LoadStore|Assembler::StoreStore); 2919 } 2920 2921 void LIR_Assembler::membar_loadload() { 2922 __ membar(Assembler::LoadLoad); 2923 } 2924 2925 void LIR_Assembler::membar_storestore() { 2926 __ membar(MacroAssembler::StoreStore); 2927 } 2928 2929 void LIR_Assembler::membar_loadstore() { __ membar(MacroAssembler::LoadStore); } 2930 2931 void LIR_Assembler::membar_storeload() { __ membar(MacroAssembler::StoreLoad); } 2932 2933 void LIR_Assembler::on_spin_wait() { 2934 __ spin_wait(); 2935 } 2936 2937 void LIR_Assembler::get_thread(LIR_Opr result_reg) { 2938 __ mov(result_reg->as_register(), rthread); 2939 } 2940 2941 2942 void LIR_Assembler::peephole(LIR_List *lir) { 2943 #if 0 2944 if (tableswitch_count >= max_tableswitches) 2945 return; 2946 2947 /* 2948 This finite-state automaton recognizes sequences of compare-and- 2949 branch instructions. We will turn them into a tableswitch. You 2950 could argue that C1 really shouldn't be doing this sort of 2951 optimization, but without it the code is really horrible. 2952 */ 2953 2954 enum { start_s, cmp1_s, beq_s, cmp_s } state; 2955 int first_key, last_key = -2147483648; 2956 int next_key = 0; 2957 int start_insn = -1; 2958 int last_insn = -1; 2959 Register reg = noreg; 2960 LIR_Opr reg_opr; 2961 state = start_s; 2962 2963 LIR_OpList* inst = lir->instructions_list(); 2964 for (int i = 0; i < inst->length(); i++) { 2965 LIR_Op* op = inst->at(i); 2966 switch (state) { 2967 case start_s: 2968 first_key = -1; 2969 start_insn = i; 2970 switch (op->code()) { 2971 case lir_cmp: 2972 LIR_Opr opr1 = op->as_Op2()->in_opr1(); 2973 LIR_Opr opr2 = op->as_Op2()->in_opr2(); 2974 if (opr1->is_cpu_register() && opr1->is_single_cpu() 2975 && opr2->is_constant() 2976 && opr2->type() == T_INT) { 2977 reg_opr = opr1; 2978 reg = opr1->as_register(); 2979 first_key = opr2->as_constant_ptr()->as_jint(); 2980 next_key = first_key + 1; 2981 state = cmp_s; 2982 goto next_state; 2983 } 2984 break; 2985 } 2986 break; 2987 case cmp_s: 2988 switch (op->code()) { 2989 case lir_branch: 2990 if (op->as_OpBranch()->cond() == lir_cond_equal) { 2991 state = beq_s; 2992 last_insn = i; 2993 goto next_state; 2994 } 2995 } 2996 state = start_s; 2997 break; 2998 case beq_s: 2999 switch (op->code()) { 3000 case lir_cmp: { 3001 LIR_Opr opr1 = op->as_Op2()->in_opr1(); 3002 LIR_Opr opr2 = op->as_Op2()->in_opr2(); 3003 if (opr1->is_cpu_register() && opr1->is_single_cpu() 3004 && opr1->as_register() == reg 3005 && opr2->is_constant() 3006 && opr2->type() == T_INT 3007 && opr2->as_constant_ptr()->as_jint() == next_key) { 3008 last_key = next_key; 3009 next_key++; 3010 state = cmp_s; 3011 goto next_state; 3012 } 3013 } 3014 } 3015 last_key = next_key; 3016 state = start_s; 3017 break; 3018 default: 3019 assert(false, "impossible state"); 3020 } 3021 if (state == start_s) { 3022 if (first_key < last_key - 5L && reg != noreg) { 3023 { 3024 // printf("found run register %d starting at insn %d low value %d high value %d\n", 3025 // reg->encoding(), 3026 // start_insn, first_key, last_key); 3027 // for (int i = 0; i < inst->length(); i++) { 3028 // inst->at(i)->print(); 3029 // tty->print("\n"); 3030 // } 3031 // tty->print("\n"); 3032 } 3033 3034 struct tableswitch *sw = &switches[tableswitch_count]; 3035 sw->_insn_index = start_insn, sw->_first_key = first_key, 3036 sw->_last_key = last_key, sw->_reg = reg; 3037 inst->insert_before(last_insn + 1, new LIR_OpLabel(&sw->_after)); 3038 { 3039 // Insert the new table of branches 3040 int offset = last_insn; 3041 for (int n = first_key; n < last_key; n++) { 3042 inst->insert_before 3043 (last_insn + 1, 3044 new LIR_OpBranch(lir_cond_always, T_ILLEGAL, 3045 inst->at(offset)->as_OpBranch()->label())); 3046 offset -= 2, i++; 3047 } 3048 } 3049 // Delete all the old compare-and-branch instructions 3050 for (int n = first_key; n < last_key; n++) { 3051 inst->remove_at(start_insn); 3052 inst->remove_at(start_insn); 3053 } 3054 // Insert the tableswitch instruction 3055 inst->insert_before(start_insn, 3056 new LIR_Op2(lir_cmp, lir_cond_always, 3057 LIR_OprFact::intConst(tableswitch_count), 3058 reg_opr)); 3059 inst->insert_before(start_insn + 1, new LIR_OpLabel(&sw->_branches)); 3060 tableswitch_count++; 3061 } 3062 reg = noreg; 3063 last_key = -2147483648; 3064 } 3065 next_state: 3066 ; 3067 } 3068 #endif 3069 } 3070 3071 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp_op) { 3072 Address addr = as_Address(src->as_address_ptr()); 3073 BasicType type = src->type(); 3074 bool is_oop = is_reference_type(type); 3075 3076 void (MacroAssembler::* add)(Register prev, RegisterOrConstant incr, Register addr); 3077 void (MacroAssembler::* xchg)(Register prev, Register newv, Register addr); 3078 3079 switch(type) { 3080 case T_INT: 3081 xchg = &MacroAssembler::atomic_xchgalw; 3082 add = &MacroAssembler::atomic_addalw; 3083 break; 3084 case T_LONG: 3085 xchg = &MacroAssembler::atomic_xchgal; 3086 add = &MacroAssembler::atomic_addal; 3087 break; 3088 case T_OBJECT: 3089 case T_ARRAY: 3090 if (UseCompressedOops) { 3091 xchg = &MacroAssembler::atomic_xchgalw; 3092 add = &MacroAssembler::atomic_addalw; 3093 } else { 3094 xchg = &MacroAssembler::atomic_xchgal; 3095 add = &MacroAssembler::atomic_addal; 3096 } 3097 break; 3098 default: 3099 ShouldNotReachHere(); 3100 xchg = &MacroAssembler::atomic_xchgal; 3101 add = &MacroAssembler::atomic_addal; // unreachable 3102 } 3103 3104 switch (code) { 3105 case lir_xadd: 3106 { 3107 RegisterOrConstant inc; 3108 Register tmp = as_reg(tmp_op); 3109 Register dst = as_reg(dest); 3110 if (data->is_constant()) { 3111 inc = RegisterOrConstant(as_long(data)); 3112 assert_different_registers(dst, addr.base(), tmp, 3113 rscratch1, rscratch2); 3114 } else { 3115 inc = RegisterOrConstant(as_reg(data)); 3116 assert_different_registers(inc.as_register(), dst, addr.base(), tmp, 3117 rscratch1, rscratch2); 3118 } 3119 __ lea(tmp, addr); 3120 (_masm->*add)(dst, inc, tmp); 3121 break; 3122 } 3123 case lir_xchg: 3124 { 3125 Register tmp = tmp_op->as_register(); 3126 Register obj = as_reg(data); 3127 Register dst = as_reg(dest); 3128 if (is_oop && UseCompressedOops) { 3129 __ encode_heap_oop(rscratch2, obj); 3130 obj = rscratch2; 3131 } 3132 assert_different_registers(obj, addr.base(), tmp, rscratch1); 3133 assert_different_registers(dst, addr.base(), tmp, rscratch1); 3134 __ lea(tmp, addr); 3135 (_masm->*xchg)(dst, obj, tmp); 3136 if (is_oop && UseCompressedOops) { 3137 __ decode_heap_oop(dst); 3138 } 3139 } 3140 break; 3141 default: 3142 ShouldNotReachHere(); 3143 } 3144 __ membar(__ AnyAny); 3145 } 3146 3147 #undef __