1 /*
   2  * Copyright (c) 2000, 2022, Oracle and/or its affiliates. All rights reserved.
   3  * Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
   4  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   5  *
   6  * This code is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 only, as
   8  * published by the Free Software Foundation.
   9  *
  10  * This code is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  * version 2 for more details (a copy is included in the LICENSE file that
  14  * accompanied this code).
  15  *
  16  * You should have received a copy of the GNU General Public License version
  17  * 2 along with this work; if not, write to the Free Software Foundation,
  18  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  19  *
  20  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  21  * or visit www.oracle.com if you need additional information or have any
  22  * questions.
  23  *
  24  */
  25 
  26 #include "precompiled.hpp"
  27 #include "asm/macroAssembler.inline.hpp"
  28 #include "asm/assembler.hpp"
  29 #include "c1/c1_CodeStubs.hpp"
  30 #include "c1/c1_Compilation.hpp"
  31 #include "c1/c1_LIRAssembler.hpp"
  32 #include "c1/c1_MacroAssembler.hpp"
  33 #include "c1/c1_Runtime1.hpp"
  34 #include "c1/c1_ValueStack.hpp"
  35 #include "ci/ciArrayKlass.hpp"
  36 #include "ci/ciInstance.hpp"
  37 #include "code/compiledIC.hpp"
  38 #include "gc/shared/collectedHeap.hpp"
  39 #include "gc/shared/gc_globals.hpp"
  40 #include "nativeInst_aarch64.hpp"
  41 #include "oops/objArrayKlass.hpp"
  42 #include "runtime/frame.inline.hpp"
  43 #include "runtime/sharedRuntime.hpp"
  44 #include "runtime/stubRoutines.hpp"
  45 #include "utilities/powerOfTwo.hpp"
  46 #include "vmreg_aarch64.inline.hpp"
  47 
  48 
  49 #ifndef PRODUCT
  50 #define COMMENT(x)   do { __ block_comment(x); } while (0)
  51 #else
  52 #define COMMENT(x)
  53 #endif
  54 
  55 NEEDS_CLEANUP // remove this definitions ?
  56 const Register IC_Klass    = rscratch2;   // where the IC klass is cached
  57 const Register SYNC_header = r0;   // synchronization header
  58 const Register SHIFT_count = r0;   // where count for shift operations must be
  59 
  60 #define __ _masm->
  61 
  62 
  63 static void select_different_registers(Register preserve,
  64                                        Register extra,
  65                                        Register &tmp1,
  66                                        Register &tmp2) {
  67   if (tmp1 == preserve) {
  68     assert_different_registers(tmp1, tmp2, extra);
  69     tmp1 = extra;
  70   } else if (tmp2 == preserve) {
  71     assert_different_registers(tmp1, tmp2, extra);
  72     tmp2 = extra;
  73   }
  74   assert_different_registers(preserve, tmp1, tmp2);
  75 }
  76 
  77 
  78 
  79 static void select_different_registers(Register preserve,
  80                                        Register extra,
  81                                        Register &tmp1,
  82                                        Register &tmp2,
  83                                        Register &tmp3) {
  84   if (tmp1 == preserve) {
  85     assert_different_registers(tmp1, tmp2, tmp3, extra);
  86     tmp1 = extra;
  87   } else if (tmp2 == preserve) {
  88     assert_different_registers(tmp1, tmp2, tmp3, extra);
  89     tmp2 = extra;
  90   } else if (tmp3 == preserve) {
  91     assert_different_registers(tmp1, tmp2, tmp3, extra);
  92     tmp3 = extra;
  93   }
  94   assert_different_registers(preserve, tmp1, tmp2, tmp3);
  95 }
  96 
  97 
  98 bool LIR_Assembler::is_small_constant(LIR_Opr opr) { Unimplemented(); return false; }
  99 
 100 
 101 LIR_Opr LIR_Assembler::receiverOpr() {
 102   return FrameMap::receiver_opr;
 103 }
 104 
 105 LIR_Opr LIR_Assembler::osrBufferPointer() {
 106   return FrameMap::as_pointer_opr(receiverOpr()->as_register());
 107 }
 108 
 109 //--------------fpu register translations-----------------------
 110 
 111 
 112 address LIR_Assembler::float_constant(float f) {
 113   address const_addr = __ float_constant(f);
 114   if (const_addr == NULL) {
 115     bailout("const section overflow");
 116     return __ code()->consts()->start();
 117   } else {
 118     return const_addr;
 119   }
 120 }
 121 
 122 
 123 address LIR_Assembler::double_constant(double d) {
 124   address const_addr = __ double_constant(d);
 125   if (const_addr == NULL) {
 126     bailout("const section overflow");
 127     return __ code()->consts()->start();
 128   } else {
 129     return const_addr;
 130   }
 131 }
 132 
 133 address LIR_Assembler::int_constant(jlong n) {
 134   address const_addr = __ long_constant(n);
 135   if (const_addr == NULL) {
 136     bailout("const section overflow");
 137     return __ code()->consts()->start();
 138   } else {
 139     return const_addr;
 140   }
 141 }
 142 
 143 void LIR_Assembler::breakpoint() { Unimplemented(); }
 144 
 145 void LIR_Assembler::push(LIR_Opr opr) { Unimplemented(); }
 146 
 147 void LIR_Assembler::pop(LIR_Opr opr) { Unimplemented(); }
 148 
 149 bool LIR_Assembler::is_literal_address(LIR_Address* addr) { Unimplemented(); return false; }
 150 //-------------------------------------------
 151 
 152 static Register as_reg(LIR_Opr op) {
 153   return op->is_double_cpu() ? op->as_register_lo() : op->as_register();
 154 }
 155 
 156 static jlong as_long(LIR_Opr data) {
 157   jlong result;
 158   switch (data->type()) {
 159   case T_INT:
 160     result = (data->as_jint());
 161     break;
 162   case T_LONG:
 163     result = (data->as_jlong());
 164     break;
 165   default:
 166     ShouldNotReachHere();
 167     result = 0;  // unreachable
 168   }
 169   return result;
 170 }
 171 
 172 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) {
 173   Register base = addr->base()->as_pointer_register();
 174   LIR_Opr opr = addr->index();
 175   if (opr->is_cpu_register()) {
 176     Register index;
 177     if (opr->is_single_cpu())
 178       index = opr->as_register();
 179     else
 180       index = opr->as_register_lo();
 181     assert(addr->disp() == 0, "must be");
 182     switch(opr->type()) {
 183       case T_INT:
 184         return Address(base, index, Address::sxtw(addr->scale()));
 185       case T_LONG:
 186         return Address(base, index, Address::lsl(addr->scale()));
 187       default:
 188         ShouldNotReachHere();
 189       }
 190   } else {
 191     assert(addr->scale() == 0,
 192            "expected for immediate operand, was: %d", addr->scale());
 193     ptrdiff_t offset = ptrdiff_t(addr->disp());
 194     // NOTE: Does not handle any 16 byte vector access.
 195     const uint type_size = type2aelembytes(addr->type(), true);
 196     return __ legitimize_address(Address(base, offset), type_size, tmp);
 197   }
 198   return Address();
 199 }
 200 
 201 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
 202   ShouldNotReachHere();
 203   return Address();
 204 }
 205 
 206 Address LIR_Assembler::as_Address(LIR_Address* addr) {
 207   return as_Address(addr, rscratch1);
 208 }
 209 
 210 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
 211   return as_Address(addr, rscratch1);  // Ouch
 212   // FIXME: This needs to be much more clever.  See x86.
 213 }
 214 
 215 // Ensure a valid Address (base + offset) to a stack-slot. If stack access is
 216 // not encodable as a base + (immediate) offset, generate an explicit address
 217 // calculation to hold the address in a temporary register.
 218 Address LIR_Assembler::stack_slot_address(int index, uint size, Register tmp, int adjust) {
 219   precond(size == 4 || size == 8);
 220   Address addr = frame_map()->address_for_slot(index, adjust);
 221   precond(addr.getMode() == Address::base_plus_offset);
 222   precond(addr.base() == sp);
 223   precond(addr.offset() > 0);
 224   uint mask = size - 1;
 225   assert((addr.offset() & mask) == 0, "scaled offsets only");
 226   return __ legitimize_address(addr, size, tmp);
 227 }
 228 
 229 void LIR_Assembler::osr_entry() {
 230   offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
 231   BlockBegin* osr_entry = compilation()->hir()->osr_entry();
 232   ValueStack* entry_state = osr_entry->state();
 233   int number_of_locks = entry_state->locks_size();
 234 
 235   // we jump here if osr happens with the interpreter
 236   // state set up to continue at the beginning of the
 237   // loop that triggered osr - in particular, we have
 238   // the following registers setup:
 239   //
 240   // r2: osr buffer
 241   //
 242 
 243   // build frame
 244   ciMethod* m = compilation()->method();
 245   __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
 246 
 247   // OSR buffer is
 248   //
 249   // locals[nlocals-1..0]
 250   // monitors[0..number_of_locks]
 251   //
 252   // locals is a direct copy of the interpreter frame so in the osr buffer
 253   // so first slot in the local array is the last local from the interpreter
 254   // and last slot is local[0] (receiver) from the interpreter
 255   //
 256   // Similarly with locks. The first lock slot in the osr buffer is the nth lock
 257   // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
 258   // in the interpreter frame (the method lock if a sync method)
 259 
 260   // Initialize monitors in the compiled activation.
 261   //   r2: pointer to osr buffer
 262   //
 263   // All other registers are dead at this point and the locals will be
 264   // copied into place by code emitted in the IR.
 265 
 266   Register OSR_buf = osrBufferPointer()->as_pointer_register();
 267   { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
 268     int monitor_offset = BytesPerWord * method()->max_locals() +
 269       (2 * BytesPerWord) * (number_of_locks - 1);
 270     // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
 271     // the OSR buffer using 2 word entries: first the lock and then
 272     // the oop.
 273     for (int i = 0; i < number_of_locks; i++) {
 274       int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
 275 #ifdef ASSERT
 276       // verify the interpreter's monitor has a non-null object
 277       {
 278         Label L;
 279         __ ldr(rscratch1, Address(OSR_buf, slot_offset + 1*BytesPerWord));
 280         __ cbnz(rscratch1, L);
 281         __ stop("locked object is NULL");
 282         __ bind(L);
 283       }
 284 #endif
 285       __ ldr(r19, Address(OSR_buf, slot_offset + 0));
 286       __ str(r19, frame_map()->address_for_monitor_lock(i));
 287       __ ldr(r19, Address(OSR_buf, slot_offset + 1*BytesPerWord));
 288       __ str(r19, frame_map()->address_for_monitor_object(i));
 289     }
 290   }
 291 }
 292 
 293 
 294 // inline cache check; done before the frame is built.
 295 int LIR_Assembler::check_icache() {
 296   Register receiver = FrameMap::receiver_opr->as_register();
 297   Register ic_klass = IC_Klass;
 298   int start_offset = __ offset();
 299   __ inline_cache_check(receiver, ic_klass);
 300 
 301   // if icache check fails, then jump to runtime routine
 302   // Note: RECEIVER must still contain the receiver!
 303   Label dont;
 304   __ br(Assembler::EQ, dont);
 305   __ far_jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
 306 
 307   // We align the verified entry point unless the method body
 308   // (including its inline cache check) will fit in a single 64-byte
 309   // icache line.
 310   if (! method()->is_accessor() || __ offset() - start_offset > 4 * 4) {
 311     // force alignment after the cache check.
 312     __ align(CodeEntryAlignment);
 313   }
 314 
 315   __ bind(dont);
 316   return start_offset;
 317 }
 318 
 319 void LIR_Assembler::clinit_barrier(ciMethod* method) {
 320   assert(VM_Version::supports_fast_class_init_checks(), "sanity");
 321   assert(!method->holder()->is_not_initialized(), "initialization should have been started");
 322 
 323   Label L_skip_barrier;
 324 
 325   __ mov_metadata(rscratch2, method->holder()->constant_encoding());
 326   __ clinit_barrier(rscratch2, rscratch1, &L_skip_barrier /*L_fast_path*/);
 327   __ far_jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub()));
 328   __ bind(L_skip_barrier);
 329 }
 330 
 331 void LIR_Assembler::jobject2reg(jobject o, Register reg) {
 332   if (o == NULL) {
 333     __ mov(reg, zr);
 334   } else {
 335     __ movoop(reg, o, /*immediate*/true);
 336   }
 337 }
 338 
 339 void LIR_Assembler::deoptimize_trap(CodeEmitInfo *info) {
 340   address target = NULL;
 341   relocInfo::relocType reloc_type = relocInfo::none;
 342 
 343   switch (patching_id(info)) {
 344   case PatchingStub::access_field_id:
 345     target = Runtime1::entry_for(Runtime1::access_field_patching_id);
 346     reloc_type = relocInfo::section_word_type;
 347     break;
 348   case PatchingStub::load_klass_id:
 349     target = Runtime1::entry_for(Runtime1::load_klass_patching_id);
 350     reloc_type = relocInfo::metadata_type;
 351     break;
 352   case PatchingStub::load_mirror_id:
 353     target = Runtime1::entry_for(Runtime1::load_mirror_patching_id);
 354     reloc_type = relocInfo::oop_type;
 355     break;
 356   case PatchingStub::load_appendix_id:
 357     target = Runtime1::entry_for(Runtime1::load_appendix_patching_id);
 358     reloc_type = relocInfo::oop_type;
 359     break;
 360   default: ShouldNotReachHere();
 361   }
 362 
 363   __ far_call(RuntimeAddress(target));
 364   add_call_info_here(info);
 365 }
 366 
 367 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) {
 368   deoptimize_trap(info);
 369 }
 370 
 371 
 372 // This specifies the rsp decrement needed to build the frame
 373 int LIR_Assembler::initial_frame_size_in_bytes() const {
 374   // if rounding, must let FrameMap know!
 375 
 376   return in_bytes(frame_map()->framesize_in_bytes());
 377 }
 378 
 379 
 380 int LIR_Assembler::emit_exception_handler() {
 381   // if the last instruction is a call (typically to do a throw which
 382   // is coming at the end after block reordering) the return address
 383   // must still point into the code area in order to avoid assertion
 384   // failures when searching for the corresponding bci => add a nop
 385   // (was bug 5/14/1999 - gri)
 386   __ nop();
 387 
 388   // generate code for exception handler
 389   address handler_base = __ start_a_stub(exception_handler_size());
 390   if (handler_base == NULL) {
 391     // not enough space left for the handler
 392     bailout("exception handler overflow");
 393     return -1;
 394   }
 395 
 396   int offset = code_offset();
 397 
 398   // the exception oop and pc are in r0, and r3
 399   // no other registers need to be preserved, so invalidate them
 400   __ invalidate_registers(false, true, true, false, true, true);
 401 
 402   // check that there is really an exception
 403   __ verify_not_null_oop(r0);
 404 
 405   // search an exception handler (r0: exception oop, r3: throwing pc)
 406   __ far_call(RuntimeAddress(Runtime1::entry_for(Runtime1::handle_exception_from_callee_id)));  __ should_not_reach_here();
 407   guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
 408   __ end_a_stub();
 409 
 410   return offset;
 411 }
 412 
 413 
 414 // Emit the code to remove the frame from the stack in the exception
 415 // unwind path.
 416 int LIR_Assembler::emit_unwind_handler() {
 417 #ifndef PRODUCT
 418   if (CommentedAssembly) {
 419     _masm->block_comment("Unwind handler");
 420   }
 421 #endif
 422 
 423   int offset = code_offset();
 424 
 425   // Fetch the exception from TLS and clear out exception related thread state
 426   __ ldr(r0, Address(rthread, JavaThread::exception_oop_offset()));
 427   __ str(zr, Address(rthread, JavaThread::exception_oop_offset()));
 428   __ str(zr, Address(rthread, JavaThread::exception_pc_offset()));
 429 
 430   __ bind(_unwind_handler_entry);
 431   __ verify_not_null_oop(r0);
 432   if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
 433     __ mov(r19, r0);  // Preserve the exception
 434   }
 435 
 436   // Perform needed unlocking
 437   MonitorExitStub* stub = NULL;
 438   if (method()->is_synchronized()) {
 439     monitor_address(0, FrameMap::r0_opr);
 440     stub = new MonitorExitStub(FrameMap::r0_opr, true, 0);
 441     if (UseHeavyMonitors) {
 442       __ b(*stub->entry());
 443     } else {
 444       __ unlock_object(r5, r4, r0, *stub->entry());
 445     }
 446     __ bind(*stub->continuation());
 447   }
 448 
 449   if (compilation()->env()->dtrace_method_probes()) {
 450     __ mov(c_rarg0, rthread);
 451     __ mov_metadata(c_rarg1, method()->constant_encoding());
 452     __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit), c_rarg0, c_rarg1);
 453   }
 454 
 455   if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
 456     __ mov(r0, r19);  // Restore the exception
 457   }
 458 
 459   // remove the activation and dispatch to the unwind handler
 460   __ block_comment("remove_frame and dispatch to the unwind handler");
 461   __ remove_frame(initial_frame_size_in_bytes());
 462   __ far_jump(RuntimeAddress(Runtime1::entry_for(Runtime1::unwind_exception_id)));
 463 
 464   // Emit the slow path assembly
 465   if (stub != NULL) {
 466     stub->emit_code(this);
 467   }
 468 
 469   return offset;
 470 }
 471 
 472 
 473 int LIR_Assembler::emit_deopt_handler() {
 474   // if the last instruction is a call (typically to do a throw which
 475   // is coming at the end after block reordering) the return address
 476   // must still point into the code area in order to avoid assertion
 477   // failures when searching for the corresponding bci => add a nop
 478   // (was bug 5/14/1999 - gri)
 479   __ nop();
 480 
 481   // generate code for exception handler
 482   address handler_base = __ start_a_stub(deopt_handler_size());
 483   if (handler_base == NULL) {
 484     // not enough space left for the handler
 485     bailout("deopt handler overflow");
 486     return -1;
 487   }
 488 
 489   int offset = code_offset();
 490 
 491   __ adr(lr, pc());
 492   __ far_jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
 493   guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
 494   __ end_a_stub();
 495 
 496   return offset;
 497 }
 498 
 499 void LIR_Assembler::add_debug_info_for_branch(address adr, CodeEmitInfo* info) {
 500   _masm->code_section()->relocate(adr, relocInfo::poll_type);
 501   int pc_offset = code_offset();
 502   flush_debug_info(pc_offset);
 503   info->record_debug_info(compilation()->debug_info_recorder(), pc_offset);
 504   if (info->exception_handlers() != NULL) {
 505     compilation()->add_exception_handlers_for_pco(pc_offset, info->exception_handlers());
 506   }
 507 }
 508 
 509 void LIR_Assembler::return_op(LIR_Opr result, C1SafepointPollStub* code_stub) {
 510   assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == r0, "word returns are in r0,");
 511 
 512   // Pop the stack before the safepoint code
 513   __ remove_frame(initial_frame_size_in_bytes());
 514 
 515   if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
 516     __ reserved_stack_check();
 517   }
 518 
 519   code_stub->set_safepoint_offset(__ offset());
 520   __ relocate(relocInfo::poll_return_type);
 521   __ safepoint_poll(*code_stub->entry(), true /* at_return */, false /* acquire */, true /* in_nmethod */);
 522   __ ret(lr);
 523 }
 524 
 525 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
 526   guarantee(info != NULL, "Shouldn't be NULL");
 527   __ get_polling_page(rscratch1, relocInfo::poll_type);
 528   add_debug_info_for_branch(info);  // This isn't just debug info:
 529                                     // it's the oop map
 530   __ read_polling_page(rscratch1, relocInfo::poll_type);
 531   return __ offset();
 532 }
 533 
 534 
 535 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
 536   if (from_reg == r31_sp)
 537     from_reg = sp;
 538   if (to_reg == r31_sp)
 539     to_reg = sp;
 540   __ mov(to_reg, from_reg);
 541 }
 542 
 543 void LIR_Assembler::swap_reg(Register a, Register b) { Unimplemented(); }
 544 
 545 
 546 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
 547   assert(src->is_constant(), "should not call otherwise");
 548   assert(dest->is_register(), "should not call otherwise");
 549   LIR_Const* c = src->as_constant_ptr();
 550 
 551   switch (c->type()) {
 552     case T_INT: {
 553       assert(patch_code == lir_patch_none, "no patching handled here");
 554       __ movw(dest->as_register(), c->as_jint());
 555       break;
 556     }
 557 
 558     case T_ADDRESS: {
 559       assert(patch_code == lir_patch_none, "no patching handled here");
 560       __ mov(dest->as_register(), c->as_jint());
 561       break;
 562     }
 563 
 564     case T_LONG: {
 565       assert(patch_code == lir_patch_none, "no patching handled here");
 566       __ mov(dest->as_register_lo(), (intptr_t)c->as_jlong());
 567       break;
 568     }
 569 
 570     case T_OBJECT: {
 571         if (patch_code == lir_patch_none) {
 572           jobject2reg(c->as_jobject(), dest->as_register());
 573         } else {
 574           jobject2reg_with_patching(dest->as_register(), info);
 575         }
 576       break;
 577     }
 578 
 579     case T_METADATA: {
 580       if (patch_code != lir_patch_none) {
 581         klass2reg_with_patching(dest->as_register(), info);
 582       } else {
 583         __ mov_metadata(dest->as_register(), c->as_metadata());
 584       }
 585       break;
 586     }
 587 
 588     case T_FLOAT: {
 589       if (__ operand_valid_for_float_immediate(c->as_jfloat())) {
 590         __ fmovs(dest->as_float_reg(), (c->as_jfloat()));
 591       } else {
 592         __ adr(rscratch1, InternalAddress(float_constant(c->as_jfloat())));
 593         __ ldrs(dest->as_float_reg(), Address(rscratch1));
 594       }
 595       break;
 596     }
 597 
 598     case T_DOUBLE: {
 599       if (__ operand_valid_for_float_immediate(c->as_jdouble())) {
 600         __ fmovd(dest->as_double_reg(), (c->as_jdouble()));
 601       } else {
 602         __ adr(rscratch1, InternalAddress(double_constant(c->as_jdouble())));
 603         __ ldrd(dest->as_double_reg(), Address(rscratch1));
 604       }
 605       break;
 606     }
 607 
 608     default:
 609       ShouldNotReachHere();
 610   }
 611 }
 612 
 613 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
 614   LIR_Const* c = src->as_constant_ptr();
 615   switch (c->type()) {
 616   case T_OBJECT:
 617     {
 618       if (! c->as_jobject())
 619         __ str(zr, frame_map()->address_for_slot(dest->single_stack_ix()));
 620       else {
 621         const2reg(src, FrameMap::rscratch1_opr, lir_patch_none, NULL);
 622         reg2stack(FrameMap::rscratch1_opr, dest, c->type(), false);
 623       }
 624     }
 625     break;
 626   case T_ADDRESS:
 627     {
 628       const2reg(src, FrameMap::rscratch1_opr, lir_patch_none, NULL);
 629       reg2stack(FrameMap::rscratch1_opr, dest, c->type(), false);
 630     }
 631   case T_INT:
 632   case T_FLOAT:
 633     {
 634       Register reg = zr;
 635       if (c->as_jint_bits() == 0)
 636         __ strw(zr, frame_map()->address_for_slot(dest->single_stack_ix()));
 637       else {
 638         __ movw(rscratch1, c->as_jint_bits());
 639         __ strw(rscratch1, frame_map()->address_for_slot(dest->single_stack_ix()));
 640       }
 641     }
 642     break;
 643   case T_LONG:
 644   case T_DOUBLE:
 645     {
 646       Register reg = zr;
 647       if (c->as_jlong_bits() == 0)
 648         __ str(zr, frame_map()->address_for_slot(dest->double_stack_ix(),
 649                                                  lo_word_offset_in_bytes));
 650       else {
 651         __ mov(rscratch1, (intptr_t)c->as_jlong_bits());
 652         __ str(rscratch1, frame_map()->address_for_slot(dest->double_stack_ix(),
 653                                                         lo_word_offset_in_bytes));
 654       }
 655     }
 656     break;
 657   default:
 658     ShouldNotReachHere();
 659   }
 660 }
 661 
 662 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
 663   assert(src->is_constant(), "should not call otherwise");
 664   LIR_Const* c = src->as_constant_ptr();
 665   LIR_Address* to_addr = dest->as_address_ptr();
 666 
 667   void (Assembler::* insn)(Register Rt, const Address &adr);
 668 
 669   switch (type) {
 670   case T_ADDRESS:
 671     assert(c->as_jint() == 0, "should be");
 672     insn = &Assembler::str;
 673     break;
 674   case T_LONG:
 675     assert(c->as_jlong() == 0, "should be");
 676     insn = &Assembler::str;
 677     break;
 678   case T_INT:
 679     assert(c->as_jint() == 0, "should be");
 680     insn = &Assembler::strw;
 681     break;
 682   case T_OBJECT:
 683   case T_ARRAY:
 684     assert(c->as_jobject() == 0, "should be");
 685     if (UseCompressedOops && !wide) {
 686       insn = &Assembler::strw;
 687     } else {
 688       insn = &Assembler::str;
 689     }
 690     break;
 691   case T_CHAR:
 692   case T_SHORT:
 693     assert(c->as_jint() == 0, "should be");
 694     insn = &Assembler::strh;
 695     break;
 696   case T_BOOLEAN:
 697   case T_BYTE:
 698     assert(c->as_jint() == 0, "should be");
 699     insn = &Assembler::strb;
 700     break;
 701   default:
 702     ShouldNotReachHere();
 703     insn = &Assembler::str;  // unreachable
 704   }
 705 
 706   if (info) add_debug_info_for_null_check_here(info);
 707   (_masm->*insn)(zr, as_Address(to_addr, rscratch1));
 708 }
 709 
 710 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
 711   assert(src->is_register(), "should not call otherwise");
 712   assert(dest->is_register(), "should not call otherwise");
 713 
 714   // move between cpu-registers
 715   if (dest->is_single_cpu()) {
 716     if (src->type() == T_LONG) {
 717       // Can do LONG -> OBJECT
 718       move_regs(src->as_register_lo(), dest->as_register());
 719       return;
 720     }
 721     assert(src->is_single_cpu(), "must match");
 722     if (src->type() == T_OBJECT) {
 723       __ verify_oop(src->as_register());
 724     }
 725     move_regs(src->as_register(), dest->as_register());
 726 
 727   } else if (dest->is_double_cpu()) {
 728     if (is_reference_type(src->type())) {
 729       // Surprising to me but we can see move of a long to t_object
 730       __ verify_oop(src->as_register());
 731       move_regs(src->as_register(), dest->as_register_lo());
 732       return;
 733     }
 734     assert(src->is_double_cpu(), "must match");
 735     Register f_lo = src->as_register_lo();
 736     Register f_hi = src->as_register_hi();
 737     Register t_lo = dest->as_register_lo();
 738     Register t_hi = dest->as_register_hi();
 739     assert(f_hi == f_lo, "must be same");
 740     assert(t_hi == t_lo, "must be same");
 741     move_regs(f_lo, t_lo);
 742 
 743   } else if (dest->is_single_fpu()) {
 744     __ fmovs(dest->as_float_reg(), src->as_float_reg());
 745 
 746   } else if (dest->is_double_fpu()) {
 747     __ fmovd(dest->as_double_reg(), src->as_double_reg());
 748 
 749   } else {
 750     ShouldNotReachHere();
 751   }
 752 }
 753 
 754 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
 755   precond(src->is_register() && dest->is_stack());
 756 
 757   uint const c_sz32 = sizeof(uint32_t);
 758   uint const c_sz64 = sizeof(uint64_t);
 759 
 760   if (src->is_single_cpu()) {
 761     int index = dest->single_stack_ix();
 762     if (is_reference_type(type)) {
 763       __ str(src->as_register(), stack_slot_address(index, c_sz64, rscratch1));
 764       __ verify_oop(src->as_register());
 765     } else if (type == T_METADATA || type == T_DOUBLE || type == T_ADDRESS) {
 766       __ str(src->as_register(), stack_slot_address(index, c_sz64, rscratch1));
 767     } else {
 768       __ strw(src->as_register(), stack_slot_address(index, c_sz32, rscratch1));
 769     }
 770 
 771   } else if (src->is_double_cpu()) {
 772     int index = dest->double_stack_ix();
 773     Address dest_addr_LO = stack_slot_address(index, c_sz64, rscratch1, lo_word_offset_in_bytes);
 774     __ str(src->as_register_lo(), dest_addr_LO);
 775 
 776   } else if (src->is_single_fpu()) {
 777     int index = dest->single_stack_ix();
 778     __ strs(src->as_float_reg(), stack_slot_address(index, c_sz32, rscratch1));
 779 
 780   } else if (src->is_double_fpu()) {
 781     int index = dest->double_stack_ix();
 782     __ strd(src->as_double_reg(), stack_slot_address(index, c_sz64, rscratch1));
 783 
 784   } else {
 785     ShouldNotReachHere();
 786   }
 787 }
 788 
 789 
 790 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool wide) {
 791   LIR_Address* to_addr = dest->as_address_ptr();
 792   PatchingStub* patch = NULL;
 793   Register compressed_src = rscratch1;
 794 
 795   if (patch_code != lir_patch_none) {
 796     deoptimize_trap(info);
 797     return;
 798   }
 799 
 800   if (is_reference_type(type)) {
 801     __ verify_oop(src->as_register());
 802 
 803     if (UseCompressedOops && !wide) {
 804       __ encode_heap_oop(compressed_src, src->as_register());
 805     } else {
 806       compressed_src = src->as_register();
 807     }
 808   }
 809 
 810   int null_check_here = code_offset();
 811   switch (type) {
 812     case T_FLOAT: {
 813       __ strs(src->as_float_reg(), as_Address(to_addr));
 814       break;
 815     }
 816 
 817     case T_DOUBLE: {
 818       __ strd(src->as_double_reg(), as_Address(to_addr));
 819       break;
 820     }
 821 
 822     case T_ARRAY:   // fall through
 823     case T_OBJECT:  // fall through
 824       if (UseCompressedOops && !wide) {
 825         __ strw(compressed_src, as_Address(to_addr, rscratch2));
 826       } else {
 827          __ str(compressed_src, as_Address(to_addr));
 828       }
 829       break;
 830     case T_METADATA:
 831       // We get here to store a method pointer to the stack to pass to
 832       // a dtrace runtime call. This can't work on 64 bit with
 833       // compressed klass ptrs: T_METADATA can be a compressed klass
 834       // ptr or a 64 bit method pointer.
 835       ShouldNotReachHere();
 836       __ str(src->as_register(), as_Address(to_addr));
 837       break;
 838     case T_ADDRESS:
 839       __ str(src->as_register(), as_Address(to_addr));
 840       break;
 841     case T_INT:
 842       __ strw(src->as_register(), as_Address(to_addr));
 843       break;
 844 
 845     case T_LONG: {
 846       __ str(src->as_register_lo(), as_Address_lo(to_addr));
 847       break;
 848     }
 849 
 850     case T_BYTE:    // fall through
 851     case T_BOOLEAN: {
 852       __ strb(src->as_register(), as_Address(to_addr));
 853       break;
 854     }
 855 
 856     case T_CHAR:    // fall through
 857     case T_SHORT:
 858       __ strh(src->as_register(), as_Address(to_addr));
 859       break;
 860 
 861     default:
 862       ShouldNotReachHere();
 863   }
 864   if (info != NULL) {
 865     add_debug_info_for_null_check(null_check_here, info);
 866   }
 867 }
 868 
 869 
 870 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
 871   precond(src->is_stack() && dest->is_register());
 872 
 873   uint const c_sz32 = sizeof(uint32_t);
 874   uint const c_sz64 = sizeof(uint64_t);
 875 
 876   if (dest->is_single_cpu()) {
 877     int index = src->single_stack_ix();
 878     if (is_reference_type(type)) {
 879       __ ldr(dest->as_register(), stack_slot_address(index, c_sz64, rscratch1));
 880       __ verify_oop(dest->as_register());
 881     } else if (type == T_METADATA || type == T_ADDRESS) {
 882       __ ldr(dest->as_register(), stack_slot_address(index, c_sz64, rscratch1));
 883     } else {
 884       __ ldrw(dest->as_register(), stack_slot_address(index, c_sz32, rscratch1));
 885     }
 886 
 887   } else if (dest->is_double_cpu()) {
 888     int index = src->double_stack_ix();
 889     Address src_addr_LO = stack_slot_address(index, c_sz64, rscratch1, lo_word_offset_in_bytes);
 890     __ ldr(dest->as_register_lo(), src_addr_LO);
 891 
 892   } else if (dest->is_single_fpu()) {
 893     int index = src->single_stack_ix();
 894     __ ldrs(dest->as_float_reg(), stack_slot_address(index, c_sz32, rscratch1));
 895 
 896   } else if (dest->is_double_fpu()) {
 897     int index = src->double_stack_ix();
 898     __ ldrd(dest->as_double_reg(), stack_slot_address(index, c_sz64, rscratch1));
 899 
 900   } else {
 901     ShouldNotReachHere();
 902   }
 903 }
 904 
 905 
 906 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) {
 907   address target = NULL;
 908   relocInfo::relocType reloc_type = relocInfo::none;
 909 
 910   switch (patching_id(info)) {
 911   case PatchingStub::access_field_id:
 912     target = Runtime1::entry_for(Runtime1::access_field_patching_id);
 913     reloc_type = relocInfo::section_word_type;
 914     break;
 915   case PatchingStub::load_klass_id:
 916     target = Runtime1::entry_for(Runtime1::load_klass_patching_id);
 917     reloc_type = relocInfo::metadata_type;
 918     break;
 919   case PatchingStub::load_mirror_id:
 920     target = Runtime1::entry_for(Runtime1::load_mirror_patching_id);
 921     reloc_type = relocInfo::oop_type;
 922     break;
 923   case PatchingStub::load_appendix_id:
 924     target = Runtime1::entry_for(Runtime1::load_appendix_patching_id);
 925     reloc_type = relocInfo::oop_type;
 926     break;
 927   default: ShouldNotReachHere();
 928   }
 929 
 930   __ far_call(RuntimeAddress(target));
 931   add_call_info_here(info);
 932 }
 933 
 934 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
 935 
 936   LIR_Opr temp;
 937   if (type == T_LONG || type == T_DOUBLE)
 938     temp = FrameMap::rscratch1_long_opr;
 939   else
 940     temp = FrameMap::rscratch1_opr;
 941 
 942   stack2reg(src, temp, src->type());
 943   reg2stack(temp, dest, dest->type(), false);
 944 }
 945 
 946 
 947 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide) {
 948   LIR_Address* addr = src->as_address_ptr();
 949   LIR_Address* from_addr = src->as_address_ptr();
 950 
 951   if (addr->base()->type() == T_OBJECT) {
 952     __ verify_oop(addr->base()->as_pointer_register());
 953   }
 954 
 955   if (patch_code != lir_patch_none) {
 956     deoptimize_trap(info);
 957     return;
 958   }
 959 
 960   if (info != NULL) {
 961     add_debug_info_for_null_check_here(info);
 962   }
 963   int null_check_here = code_offset();
 964   switch (type) {
 965     case T_FLOAT: {
 966       __ ldrs(dest->as_float_reg(), as_Address(from_addr));
 967       break;
 968     }
 969 
 970     case T_DOUBLE: {
 971       __ ldrd(dest->as_double_reg(), as_Address(from_addr));
 972       break;
 973     }
 974 
 975     case T_ARRAY:   // fall through
 976     case T_OBJECT:  // fall through
 977       if (UseCompressedOops && !wide) {
 978         __ ldrw(dest->as_register(), as_Address(from_addr));
 979       } else {
 980          __ ldr(dest->as_register(), as_Address(from_addr));
 981       }
 982       break;
 983     case T_METADATA:
 984       // We get here to store a method pointer to the stack to pass to
 985       // a dtrace runtime call. This can't work on 64 bit with
 986       // compressed klass ptrs: T_METADATA can be a compressed klass
 987       // ptr or a 64 bit method pointer.
 988       ShouldNotReachHere();
 989       __ ldr(dest->as_register(), as_Address(from_addr));
 990       break;
 991     case T_ADDRESS:
 992       __ ldr(dest->as_register(), as_Address(from_addr));
 993       break;
 994     case T_INT:
 995       __ ldrw(dest->as_register(), as_Address(from_addr));
 996       break;
 997 
 998     case T_LONG: {
 999       __ ldr(dest->as_register_lo(), as_Address_lo(from_addr));
1000       break;
1001     }
1002 
1003     case T_BYTE:
1004       __ ldrsb(dest->as_register(), as_Address(from_addr));
1005       break;
1006     case T_BOOLEAN: {
1007       __ ldrb(dest->as_register(), as_Address(from_addr));
1008       break;
1009     }
1010 
1011     case T_CHAR:
1012       __ ldrh(dest->as_register(), as_Address(from_addr));
1013       break;
1014     case T_SHORT:
1015       __ ldrsh(dest->as_register(), as_Address(from_addr));
1016       break;
1017 
1018     default:
1019       ShouldNotReachHere();
1020   }
1021 
1022   if (is_reference_type(type)) {
1023     if (UseCompressedOops && !wide) {
1024       __ decode_heap_oop(dest->as_register());
1025     }
1026 
1027     if (!UseZGC) {
1028       // Load barrier has not yet been applied, so ZGC can't verify the oop here
1029       __ verify_oop(dest->as_register());
1030     }
1031   }
1032 }
1033 
1034 
1035 int LIR_Assembler::array_element_size(BasicType type) const {
1036   int elem_size = type2aelembytes(type);
1037   return exact_log2(elem_size);
1038 }
1039 
1040 
1041 void LIR_Assembler::emit_op3(LIR_Op3* op) {
1042   switch (op->code()) {
1043   case lir_idiv:
1044   case lir_irem:
1045     arithmetic_idiv(op->code(),
1046                     op->in_opr1(),
1047                     op->in_opr2(),
1048                     op->in_opr3(),
1049                     op->result_opr(),
1050                     op->info());
1051     break;
1052   case lir_fmad:
1053     __ fmaddd(op->result_opr()->as_double_reg(),
1054               op->in_opr1()->as_double_reg(),
1055               op->in_opr2()->as_double_reg(),
1056               op->in_opr3()->as_double_reg());
1057     break;
1058   case lir_fmaf:
1059     __ fmadds(op->result_opr()->as_float_reg(),
1060               op->in_opr1()->as_float_reg(),
1061               op->in_opr2()->as_float_reg(),
1062               op->in_opr3()->as_float_reg());
1063     break;
1064   default:      ShouldNotReachHere(); break;
1065   }
1066 }
1067 
1068 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
1069 #ifdef ASSERT
1070   assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label");
1071   if (op->block() != NULL)  _branch_target_blocks.append(op->block());
1072   if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock());
1073 #endif
1074 
1075   if (op->cond() == lir_cond_always) {
1076     if (op->info() != NULL) add_debug_info_for_branch(op->info());
1077     __ b(*(op->label()));
1078   } else {
1079     Assembler::Condition acond;
1080     if (op->code() == lir_cond_float_branch) {
1081       bool is_unordered = (op->ublock() == op->block());
1082       // Assembler::EQ does not permit unordered branches, so we add
1083       // another branch here.  Likewise, Assembler::NE does not permit
1084       // ordered branches.
1085       if ((is_unordered && op->cond() == lir_cond_equal)
1086           || (!is_unordered && op->cond() == lir_cond_notEqual))
1087         __ br(Assembler::VS, *(op->ublock()->label()));
1088       switch(op->cond()) {
1089       case lir_cond_equal:        acond = Assembler::EQ; break;
1090       case lir_cond_notEqual:     acond = Assembler::NE; break;
1091       case lir_cond_less:         acond = (is_unordered ? Assembler::LT : Assembler::LO); break;
1092       case lir_cond_lessEqual:    acond = (is_unordered ? Assembler::LE : Assembler::LS); break;
1093       case lir_cond_greaterEqual: acond = (is_unordered ? Assembler::HS : Assembler::GE); break;
1094       case lir_cond_greater:      acond = (is_unordered ? Assembler::HI : Assembler::GT); break;
1095       default:                    ShouldNotReachHere();
1096         acond = Assembler::EQ;  // unreachable
1097       }
1098     } else {
1099       switch (op->cond()) {
1100         case lir_cond_equal:        acond = Assembler::EQ; break;
1101         case lir_cond_notEqual:     acond = Assembler::NE; break;
1102         case lir_cond_less:         acond = Assembler::LT; break;
1103         case lir_cond_lessEqual:    acond = Assembler::LE; break;
1104         case lir_cond_greaterEqual: acond = Assembler::GE; break;
1105         case lir_cond_greater:      acond = Assembler::GT; break;
1106         case lir_cond_belowEqual:   acond = Assembler::LS; break;
1107         case lir_cond_aboveEqual:   acond = Assembler::HS; break;
1108         default:                    ShouldNotReachHere();
1109           acond = Assembler::EQ;  // unreachable
1110       }
1111     }
1112     __ br(acond,*(op->label()));
1113   }
1114 }
1115 
1116 
1117 
1118 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
1119   LIR_Opr src  = op->in_opr();
1120   LIR_Opr dest = op->result_opr();
1121 
1122   switch (op->bytecode()) {
1123     case Bytecodes::_i2f:
1124       {
1125         __ scvtfws(dest->as_float_reg(), src->as_register());
1126         break;
1127       }
1128     case Bytecodes::_i2d:
1129       {
1130         __ scvtfwd(dest->as_double_reg(), src->as_register());
1131         break;
1132       }
1133     case Bytecodes::_l2d:
1134       {
1135         __ scvtfd(dest->as_double_reg(), src->as_register_lo());
1136         break;
1137       }
1138     case Bytecodes::_l2f:
1139       {
1140         __ scvtfs(dest->as_float_reg(), src->as_register_lo());
1141         break;
1142       }
1143     case Bytecodes::_f2d:
1144       {
1145         __ fcvts(dest->as_double_reg(), src->as_float_reg());
1146         break;
1147       }
1148     case Bytecodes::_d2f:
1149       {
1150         __ fcvtd(dest->as_float_reg(), src->as_double_reg());
1151         break;
1152       }
1153     case Bytecodes::_i2c:
1154       {
1155         __ ubfx(dest->as_register(), src->as_register(), 0, 16);
1156         break;
1157       }
1158     case Bytecodes::_i2l:
1159       {
1160         __ sxtw(dest->as_register_lo(), src->as_register());
1161         break;
1162       }
1163     case Bytecodes::_i2s:
1164       {
1165         __ sxth(dest->as_register(), src->as_register());
1166         break;
1167       }
1168     case Bytecodes::_i2b:
1169       {
1170         __ sxtb(dest->as_register(), src->as_register());
1171         break;
1172       }
1173     case Bytecodes::_l2i:
1174       {
1175         _masm->block_comment("FIXME: This could be a no-op");
1176         __ uxtw(dest->as_register(), src->as_register_lo());
1177         break;
1178       }
1179     case Bytecodes::_d2l:
1180       {
1181         __ fcvtzd(dest->as_register_lo(), src->as_double_reg());
1182         break;
1183       }
1184     case Bytecodes::_f2i:
1185       {
1186         __ fcvtzsw(dest->as_register(), src->as_float_reg());
1187         break;
1188       }
1189     case Bytecodes::_f2l:
1190       {
1191         __ fcvtzs(dest->as_register_lo(), src->as_float_reg());
1192         break;
1193       }
1194     case Bytecodes::_d2i:
1195       {
1196         __ fcvtzdw(dest->as_register(), src->as_double_reg());
1197         break;
1198       }
1199     default: ShouldNotReachHere();
1200   }
1201 }
1202 
1203 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
1204   if (op->init_check()) {
1205     __ ldrb(rscratch1, Address(op->klass()->as_register(),
1206                                InstanceKlass::init_state_offset()));
1207     __ cmpw(rscratch1, InstanceKlass::fully_initialized);
1208     add_debug_info_for_null_check_here(op->stub()->info());
1209     __ br(Assembler::NE, *op->stub()->entry());
1210   }
1211   __ allocate_object(op->obj()->as_register(),
1212                      op->tmp1()->as_register(),
1213                      op->tmp2()->as_register(),
1214                      op->header_size(),
1215                      op->object_size(),
1216                      op->klass()->as_register(),
1217                      *op->stub()->entry());
1218   __ bind(*op->stub()->continuation());
1219 }
1220 
1221 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
1222   Register len =  op->len()->as_register();
1223   __ uxtw(len, len);
1224 
1225   if (UseSlowPath ||
1226       (!UseFastNewObjectArray && is_reference_type(op->type())) ||
1227       (!UseFastNewTypeArray   && !is_reference_type(op->type()))) {
1228     __ b(*op->stub()->entry());
1229   } else {
1230     Register tmp1 = op->tmp1()->as_register();
1231     Register tmp2 = op->tmp2()->as_register();
1232     Register tmp3 = op->tmp3()->as_register();
1233     if (len == tmp1) {
1234       tmp1 = tmp3;
1235     } else if (len == tmp2) {
1236       tmp2 = tmp3;
1237     } else if (len == tmp3) {
1238       // everything is ok
1239     } else {
1240       __ mov(tmp3, len);
1241     }
1242     __ allocate_array(op->obj()->as_register(),
1243                       len,
1244                       tmp1,
1245                       tmp2,
1246                       arrayOopDesc::header_size(op->type()),
1247                       array_element_size(op->type()),
1248                       op->klass()->as_register(),
1249                       *op->stub()->entry());
1250   }
1251   __ bind(*op->stub()->continuation());
1252 }
1253 
1254 void LIR_Assembler::type_profile_helper(Register mdo,
1255                                         ciMethodData *md, ciProfileData *data,
1256                                         Register recv, Label* update_done) {
1257   for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1258     Label next_test;
1259     // See if the receiver is receiver[n].
1260     __ lea(rscratch2, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))));
1261     __ ldr(rscratch1, Address(rscratch2));
1262     __ cmp(recv, rscratch1);
1263     __ br(Assembler::NE, next_test);
1264     Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)));
1265     __ addptr(data_addr, DataLayout::counter_increment);
1266     __ b(*update_done);
1267     __ bind(next_test);
1268   }
1269 
1270   // Didn't find receiver; find next empty slot and fill it in
1271   for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1272     Label next_test;
1273     __ lea(rscratch2,
1274            Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))));
1275     Address recv_addr(rscratch2);
1276     __ ldr(rscratch1, recv_addr);
1277     __ cbnz(rscratch1, next_test);
1278     __ str(recv, recv_addr);
1279     __ mov(rscratch1, DataLayout::counter_increment);
1280     __ lea(rscratch2, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))));
1281     __ str(rscratch1, Address(rscratch2));
1282     __ b(*update_done);
1283     __ bind(next_test);
1284   }
1285 }
1286 
1287 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
1288   // we always need a stub for the failure case.
1289   CodeStub* stub = op->stub();
1290   Register obj = op->object()->as_register();
1291   Register k_RInfo = op->tmp1()->as_register();
1292   Register klass_RInfo = op->tmp2()->as_register();
1293   Register dst = op->result_opr()->as_register();
1294   ciKlass* k = op->klass();
1295   Register Rtmp1 = noreg;
1296 
1297   // check if it needs to be profiled
1298   ciMethodData* md;
1299   ciProfileData* data;
1300 
1301   const bool should_profile = op->should_profile();
1302 
1303   if (should_profile) {
1304     ciMethod* method = op->profiled_method();
1305     assert(method != NULL, "Should have method");
1306     int bci = op->profiled_bci();
1307     md = method->method_data_or_null();
1308     assert(md != NULL, "Sanity");
1309     data = md->bci_to_data(bci);
1310     assert(data != NULL,                "need data for type check");
1311     assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1312   }
1313   Label profile_cast_success, profile_cast_failure;
1314   Label *success_target = should_profile ? &profile_cast_success : success;
1315   Label *failure_target = should_profile ? &profile_cast_failure : failure;
1316 
1317   if (obj == k_RInfo) {
1318     k_RInfo = dst;
1319   } else if (obj == klass_RInfo) {
1320     klass_RInfo = dst;
1321   }
1322   if (k->is_loaded() && !UseCompressedClassPointers) {
1323     select_different_registers(obj, dst, k_RInfo, klass_RInfo);
1324   } else {
1325     Rtmp1 = op->tmp3()->as_register();
1326     select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1);
1327   }
1328 
1329   assert_different_registers(obj, k_RInfo, klass_RInfo);
1330 
1331     if (should_profile) {
1332       Label not_null;
1333       __ cbnz(obj, not_null);
1334       // Object is null; update MDO and exit
1335       Register mdo  = klass_RInfo;
1336       __ mov_metadata(mdo, md->constant_encoding());
1337       Address data_addr
1338         = __ form_address(rscratch2, mdo,
1339                           md->byte_offset_of_slot(data, DataLayout::flags_offset()),
1340                           0);
1341       __ ldrb(rscratch1, data_addr);
1342       __ orr(rscratch1, rscratch1, BitData::null_seen_byte_constant());
1343       __ strb(rscratch1, data_addr);
1344       __ b(*obj_is_null);
1345       __ bind(not_null);
1346     } else {
1347       __ cbz(obj, *obj_is_null);
1348     }
1349 
1350   if (!k->is_loaded()) {
1351     klass2reg_with_patching(k_RInfo, op->info_for_patch());
1352   } else {
1353     __ mov_metadata(k_RInfo, k->constant_encoding());
1354   }
1355   __ verify_oop(obj);
1356 
1357   if (op->fast_check()) {
1358     // get object class
1359     // not a safepoint as obj null check happens earlier
1360     __ load_klass(rscratch1, obj);
1361     __ cmp( rscratch1, k_RInfo);
1362 
1363     __ br(Assembler::NE, *failure_target);
1364     // successful cast, fall through to profile or jump
1365   } else {
1366     // get object class
1367     // not a safepoint as obj null check happens earlier
1368     __ load_klass(klass_RInfo, obj);
1369     if (k->is_loaded()) {
1370       // See if we get an immediate positive hit
1371       __ ldr(rscratch1, Address(klass_RInfo, int64_t(k->super_check_offset())));
1372       __ cmp(k_RInfo, rscratch1);
1373       if ((juint)in_bytes(Klass::secondary_super_cache_offset()) != k->super_check_offset()) {
1374         __ br(Assembler::NE, *failure_target);
1375         // successful cast, fall through to profile or jump
1376       } else {
1377         // See if we get an immediate positive hit
1378         __ br(Assembler::EQ, *success_target);
1379         // check for self
1380         __ cmp(klass_RInfo, k_RInfo);
1381         __ br(Assembler::EQ, *success_target);
1382 
1383         __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1384         __ far_call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1385         __ ldr(klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1386         // result is a boolean
1387         __ cbzw(klass_RInfo, *failure_target);
1388         // successful cast, fall through to profile or jump
1389       }
1390     } else {
1391       // perform the fast part of the checking logic
1392       __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL);
1393       // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1394       __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1395       __ far_call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1396       __ ldp(k_RInfo, klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1397       // result is a boolean
1398       __ cbz(k_RInfo, *failure_target);
1399       // successful cast, fall through to profile or jump
1400     }
1401   }
1402   if (should_profile) {
1403     Register mdo  = klass_RInfo, recv = k_RInfo;
1404     __ bind(profile_cast_success);
1405     __ mov_metadata(mdo, md->constant_encoding());
1406     __ load_klass(recv, obj);
1407     Label update_done;
1408     type_profile_helper(mdo, md, data, recv, success);
1409     __ b(*success);
1410 
1411     __ bind(profile_cast_failure);
1412     __ mov_metadata(mdo, md->constant_encoding());
1413     Address counter_addr
1414       = __ form_address(rscratch2, mdo,
1415                         md->byte_offset_of_slot(data, CounterData::count_offset()),
1416                         0);
1417     __ ldr(rscratch1, counter_addr);
1418     __ sub(rscratch1, rscratch1, DataLayout::counter_increment);
1419     __ str(rscratch1, counter_addr);
1420     __ b(*failure);
1421   }
1422   __ b(*success);
1423 }
1424 
1425 
1426 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
1427   const bool should_profile = op->should_profile();
1428 
1429   LIR_Code code = op->code();
1430   if (code == lir_store_check) {
1431     Register value = op->object()->as_register();
1432     Register array = op->array()->as_register();
1433     Register k_RInfo = op->tmp1()->as_register();
1434     Register klass_RInfo = op->tmp2()->as_register();
1435     Register Rtmp1 = op->tmp3()->as_register();
1436 
1437     CodeStub* stub = op->stub();
1438 
1439     // check if it needs to be profiled
1440     ciMethodData* md;
1441     ciProfileData* data;
1442 
1443     if (should_profile) {
1444       ciMethod* method = op->profiled_method();
1445       assert(method != NULL, "Should have method");
1446       int bci = op->profiled_bci();
1447       md = method->method_data_or_null();
1448       assert(md != NULL, "Sanity");
1449       data = md->bci_to_data(bci);
1450       assert(data != NULL,                "need data for type check");
1451       assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1452     }
1453     Label profile_cast_success, profile_cast_failure, done;
1454     Label *success_target = should_profile ? &profile_cast_success : &done;
1455     Label *failure_target = should_profile ? &profile_cast_failure : stub->entry();
1456 
1457     if (should_profile) {
1458       Label not_null;
1459       __ cbnz(value, not_null);
1460       // Object is null; update MDO and exit
1461       Register mdo  = klass_RInfo;
1462       __ mov_metadata(mdo, md->constant_encoding());
1463       Address data_addr
1464         = __ form_address(rscratch2, mdo,
1465                           md->byte_offset_of_slot(data, DataLayout::flags_offset()),
1466                           0);
1467       __ ldrb(rscratch1, data_addr);
1468       __ orr(rscratch1, rscratch1, BitData::null_seen_byte_constant());
1469       __ strb(rscratch1, data_addr);
1470       __ b(done);
1471       __ bind(not_null);
1472     } else {
1473       __ cbz(value, done);
1474     }
1475 
1476     add_debug_info_for_null_check_here(op->info_for_exception());
1477     __ load_klass(k_RInfo, array);
1478     __ load_klass(klass_RInfo, value);
1479 
1480     // get instance klass (it's already uncompressed)
1481     __ ldr(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset()));
1482     // perform the fast part of the checking logic
1483     __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL);
1484     // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1485     __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1486     __ far_call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1487     __ ldp(k_RInfo, klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1488     // result is a boolean
1489     __ cbzw(k_RInfo, *failure_target);
1490     // fall through to the success case
1491 
1492     if (should_profile) {
1493       Register mdo  = klass_RInfo, recv = k_RInfo;
1494       __ bind(profile_cast_success);
1495       __ mov_metadata(mdo, md->constant_encoding());
1496       __ load_klass(recv, value);
1497       Label update_done;
1498       type_profile_helper(mdo, md, data, recv, &done);
1499       __ b(done);
1500 
1501       __ bind(profile_cast_failure);
1502       __ mov_metadata(mdo, md->constant_encoding());
1503       Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1504       __ lea(rscratch2, counter_addr);
1505       __ ldr(rscratch1, Address(rscratch2));
1506       __ sub(rscratch1, rscratch1, DataLayout::counter_increment);
1507       __ str(rscratch1, Address(rscratch2));
1508       __ b(*stub->entry());
1509     }
1510 
1511     __ bind(done);
1512   } else if (code == lir_checkcast) {
1513     Register obj = op->object()->as_register();
1514     Register dst = op->result_opr()->as_register();
1515     Label success;
1516     emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
1517     __ bind(success);
1518     if (dst != obj) {
1519       __ mov(dst, obj);
1520     }
1521   } else if (code == lir_instanceof) {
1522     Register obj = op->object()->as_register();
1523     Register dst = op->result_opr()->as_register();
1524     Label success, failure, done;
1525     emit_typecheck_helper(op, &success, &failure, &failure);
1526     __ bind(failure);
1527     __ mov(dst, zr);
1528     __ b(done);
1529     __ bind(success);
1530     __ mov(dst, 1);
1531     __ bind(done);
1532   } else {
1533     ShouldNotReachHere();
1534   }
1535 }
1536 
1537 void LIR_Assembler::casw(Register addr, Register newval, Register cmpval) {
1538   __ cmpxchg(addr, cmpval, newval, Assembler::word, /* acquire*/ true, /* release*/ true, /* weak*/ false, rscratch1);
1539   __ cset(rscratch1, Assembler::NE);
1540   __ membar(__ AnyAny);
1541 }
1542 
1543 void LIR_Assembler::casl(Register addr, Register newval, Register cmpval) {
1544   __ cmpxchg(addr, cmpval, newval, Assembler::xword, /* acquire*/ true, /* release*/ true, /* weak*/ false, rscratch1);
1545   __ cset(rscratch1, Assembler::NE);
1546   __ membar(__ AnyAny);
1547 }
1548 
1549 
1550 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
1551   assert(VM_Version::supports_cx8(), "wrong machine");
1552   Register addr;
1553   if (op->addr()->is_register()) {
1554     addr = as_reg(op->addr());
1555   } else {
1556     assert(op->addr()->is_address(), "what else?");
1557     LIR_Address* addr_ptr = op->addr()->as_address_ptr();
1558     assert(addr_ptr->disp() == 0, "need 0 disp");
1559     assert(addr_ptr->index() == LIR_Opr::illegalOpr(), "need 0 index");
1560     addr = as_reg(addr_ptr->base());
1561   }
1562   Register newval = as_reg(op->new_value());
1563   Register cmpval = as_reg(op->cmp_value());
1564 
1565   if (op->code() == lir_cas_obj) {
1566     if (UseCompressedOops) {
1567       Register t1 = op->tmp1()->as_register();
1568       assert(op->tmp1()->is_valid(), "must be");
1569       __ encode_heap_oop(t1, cmpval);
1570       cmpval = t1;
1571       __ encode_heap_oop(rscratch2, newval);
1572       newval = rscratch2;
1573       casw(addr, newval, cmpval);
1574     } else {
1575       casl(addr, newval, cmpval);
1576     }
1577   } else if (op->code() == lir_cas_int) {
1578     casw(addr, newval, cmpval);
1579   } else {
1580     casl(addr, newval, cmpval);
1581   }
1582 }
1583 
1584 
1585 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type,
1586                           LIR_Opr cmp_opr1, LIR_Opr cmp_opr2) {
1587   assert(cmp_opr1 == LIR_OprFact::illegalOpr && cmp_opr2 == LIR_OprFact::illegalOpr, "unnecessary cmp oprs on aarch64");
1588 
1589   Assembler::Condition acond, ncond;
1590   switch (condition) {
1591   case lir_cond_equal:        acond = Assembler::EQ; ncond = Assembler::NE; break;
1592   case lir_cond_notEqual:     acond = Assembler::NE; ncond = Assembler::EQ; break;
1593   case lir_cond_less:         acond = Assembler::LT; ncond = Assembler::GE; break;
1594   case lir_cond_lessEqual:    acond = Assembler::LE; ncond = Assembler::GT; break;
1595   case lir_cond_greaterEqual: acond = Assembler::GE; ncond = Assembler::LT; break;
1596   case lir_cond_greater:      acond = Assembler::GT; ncond = Assembler::LE; break;
1597   case lir_cond_belowEqual:
1598   case lir_cond_aboveEqual:
1599   default:                    ShouldNotReachHere();
1600     acond = Assembler::EQ; ncond = Assembler::NE;  // unreachable
1601   }
1602 
1603   assert(result->is_single_cpu() || result->is_double_cpu(),
1604          "expect single register for result");
1605   if (opr1->is_constant() && opr2->is_constant()
1606       && opr1->type() == T_INT && opr2->type() == T_INT) {
1607     jint val1 = opr1->as_jint();
1608     jint val2 = opr2->as_jint();
1609     if (val1 == 0 && val2 == 1) {
1610       __ cset(result->as_register(), ncond);
1611       return;
1612     } else if (val1 == 1 && val2 == 0) {
1613       __ cset(result->as_register(), acond);
1614       return;
1615     }
1616   }
1617 
1618   if (opr1->is_constant() && opr2->is_constant()
1619       && opr1->type() == T_LONG && opr2->type() == T_LONG) {
1620     jlong val1 = opr1->as_jlong();
1621     jlong val2 = opr2->as_jlong();
1622     if (val1 == 0 && val2 == 1) {
1623       __ cset(result->as_register_lo(), ncond);
1624       return;
1625     } else if (val1 == 1 && val2 == 0) {
1626       __ cset(result->as_register_lo(), acond);
1627       return;
1628     }
1629   }
1630 
1631   if (opr1->is_stack()) {
1632     stack2reg(opr1, FrameMap::rscratch1_opr, result->type());
1633     opr1 = FrameMap::rscratch1_opr;
1634   } else if (opr1->is_constant()) {
1635     LIR_Opr tmp
1636       = opr1->type() == T_LONG ? FrameMap::rscratch1_long_opr : FrameMap::rscratch1_opr;
1637     const2reg(opr1, tmp, lir_patch_none, NULL);
1638     opr1 = tmp;
1639   }
1640 
1641   if (opr2->is_stack()) {
1642     stack2reg(opr2, FrameMap::rscratch2_opr, result->type());
1643     opr2 = FrameMap::rscratch2_opr;
1644   } else if (opr2->is_constant()) {
1645     LIR_Opr tmp
1646       = opr2->type() == T_LONG ? FrameMap::rscratch2_long_opr : FrameMap::rscratch2_opr;
1647     const2reg(opr2, tmp, lir_patch_none, NULL);
1648     opr2 = tmp;
1649   }
1650 
1651   if (result->type() == T_LONG)
1652     __ csel(result->as_register_lo(), opr1->as_register_lo(), opr2->as_register_lo(), acond);
1653   else
1654     __ csel(result->as_register(), opr1->as_register(), opr2->as_register(), acond);
1655 }
1656 
1657 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) {
1658   assert(info == NULL, "should never be used, idiv/irem and ldiv/lrem not handled by this method");
1659 
1660   if (left->is_single_cpu()) {
1661     Register lreg = left->as_register();
1662     Register dreg = as_reg(dest);
1663 
1664     if (right->is_single_cpu()) {
1665       // cpu register - cpu register
1666 
1667       assert(left->type() == T_INT && right->type() == T_INT && dest->type() == T_INT,
1668              "should be");
1669       Register rreg = right->as_register();
1670       switch (code) {
1671       case lir_add: __ addw (dest->as_register(), lreg, rreg); break;
1672       case lir_sub: __ subw (dest->as_register(), lreg, rreg); break;
1673       case lir_mul: __ mulw (dest->as_register(), lreg, rreg); break;
1674       default:      ShouldNotReachHere();
1675       }
1676 
1677     } else if (right->is_double_cpu()) {
1678       Register rreg = right->as_register_lo();
1679       // single_cpu + double_cpu: can happen with obj+long
1680       assert(code == lir_add || code == lir_sub, "mismatched arithmetic op");
1681       switch (code) {
1682       case lir_add: __ add(dreg, lreg, rreg); break;
1683       case lir_sub: __ sub(dreg, lreg, rreg); break;
1684       default: ShouldNotReachHere();
1685       }
1686     } else if (right->is_constant()) {
1687       // cpu register - constant
1688       jlong c;
1689 
1690       // FIXME.  This is fugly: we really need to factor all this logic.
1691       switch(right->type()) {
1692       case T_LONG:
1693         c = right->as_constant_ptr()->as_jlong();
1694         break;
1695       case T_INT:
1696       case T_ADDRESS:
1697         c = right->as_constant_ptr()->as_jint();
1698         break;
1699       default:
1700         ShouldNotReachHere();
1701         c = 0;  // unreachable
1702         break;
1703       }
1704 
1705       assert(code == lir_add || code == lir_sub, "mismatched arithmetic op");
1706       if (c == 0 && dreg == lreg) {
1707         COMMENT("effective nop elided");
1708         return;
1709       }
1710       switch(left->type()) {
1711       case T_INT:
1712         switch (code) {
1713         case lir_add: __ addw(dreg, lreg, c); break;
1714         case lir_sub: __ subw(dreg, lreg, c); break;
1715         default: ShouldNotReachHere();
1716         }
1717         break;
1718       case T_OBJECT:
1719       case T_ADDRESS:
1720         switch (code) {
1721         case lir_add: __ add(dreg, lreg, c); break;
1722         case lir_sub: __ sub(dreg, lreg, c); break;
1723         default: ShouldNotReachHere();
1724         }
1725         break;
1726       default:
1727         ShouldNotReachHere();
1728       }
1729     } else {
1730       ShouldNotReachHere();
1731     }
1732 
1733   } else if (left->is_double_cpu()) {
1734     Register lreg_lo = left->as_register_lo();
1735 
1736     if (right->is_double_cpu()) {
1737       // cpu register - cpu register
1738       Register rreg_lo = right->as_register_lo();
1739       switch (code) {
1740       case lir_add: __ add (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1741       case lir_sub: __ sub (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1742       case lir_mul: __ mul (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1743       case lir_div: __ corrected_idivq(dest->as_register_lo(), lreg_lo, rreg_lo, false, rscratch1); break;
1744       case lir_rem: __ corrected_idivq(dest->as_register_lo(), lreg_lo, rreg_lo, true, rscratch1); break;
1745       default:
1746         ShouldNotReachHere();
1747       }
1748 
1749     } else if (right->is_constant()) {
1750       jlong c = right->as_constant_ptr()->as_jlong();
1751       Register dreg = as_reg(dest);
1752       switch (code) {
1753         case lir_add:
1754         case lir_sub:
1755           if (c == 0 && dreg == lreg_lo) {
1756             COMMENT("effective nop elided");
1757             return;
1758           }
1759           code == lir_add ? __ add(dreg, lreg_lo, c) : __ sub(dreg, lreg_lo, c);
1760           break;
1761         case lir_div:
1762           assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant");
1763           if (c == 1) {
1764             // move lreg_lo to dreg if divisor is 1
1765             __ mov(dreg, lreg_lo);
1766           } else {
1767             unsigned int shift = log2i_exact(c);
1768             // use rscratch1 as intermediate result register
1769             __ asr(rscratch1, lreg_lo, 63);
1770             __ add(rscratch1, lreg_lo, rscratch1, Assembler::LSR, 64 - shift);
1771             __ asr(dreg, rscratch1, shift);
1772           }
1773           break;
1774         case lir_rem:
1775           assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant");
1776           if (c == 1) {
1777             // move 0 to dreg if divisor is 1
1778             __ mov(dreg, zr);
1779           } else {
1780             // use rscratch1 as intermediate result register
1781             __ negs(rscratch1, lreg_lo);
1782             __ andr(dreg, lreg_lo, c - 1);
1783             __ andr(rscratch1, rscratch1, c - 1);
1784             __ csneg(dreg, dreg, rscratch1, Assembler::MI);
1785           }
1786           break;
1787         default:
1788           ShouldNotReachHere();
1789       }
1790     } else {
1791       ShouldNotReachHere();
1792     }
1793   } else if (left->is_single_fpu()) {
1794     assert(right->is_single_fpu(), "right hand side of float arithmetics needs to be float register");
1795     switch (code) {
1796     case lir_add: __ fadds (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1797     case lir_sub: __ fsubs (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1798     case lir_mul: __ fmuls (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1799     case lir_div: __ fdivs (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1800     default:
1801       ShouldNotReachHere();
1802     }
1803   } else if (left->is_double_fpu()) {
1804     if (right->is_double_fpu()) {
1805       // fpu register - fpu register
1806       switch (code) {
1807       case lir_add: __ faddd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1808       case lir_sub: __ fsubd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1809       case lir_mul: __ fmuld (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1810       case lir_div: __ fdivd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1811       default:
1812         ShouldNotReachHere();
1813       }
1814     } else {
1815       if (right->is_constant()) {
1816         ShouldNotReachHere();
1817       }
1818       ShouldNotReachHere();
1819     }
1820   } else if (left->is_single_stack() || left->is_address()) {
1821     assert(left == dest, "left and dest must be equal");
1822     ShouldNotReachHere();
1823   } else {
1824     ShouldNotReachHere();
1825   }
1826 }
1827 
1828 void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) { Unimplemented(); }
1829 
1830 
1831 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr unused, LIR_Opr dest, LIR_Op* op) {
1832   switch(code) {
1833   case lir_abs : __ fabsd(dest->as_double_reg(), value->as_double_reg()); break;
1834   case lir_sqrt: __ fsqrtd(dest->as_double_reg(), value->as_double_reg()); break;
1835   default      : ShouldNotReachHere();
1836   }
1837 }
1838 
1839 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) {
1840 
1841   assert(left->is_single_cpu() || left->is_double_cpu(), "expect single or double register");
1842   Register Rleft = left->is_single_cpu() ? left->as_register() :
1843                                            left->as_register_lo();
1844    if (dst->is_single_cpu()) {
1845      Register Rdst = dst->as_register();
1846      if (right->is_constant()) {
1847        switch (code) {
1848          case lir_logic_and: __ andw (Rdst, Rleft, right->as_jint()); break;
1849          case lir_logic_or:  __ orrw (Rdst, Rleft, right->as_jint()); break;
1850          case lir_logic_xor: __ eorw (Rdst, Rleft, right->as_jint()); break;
1851          default: ShouldNotReachHere(); break;
1852        }
1853      } else {
1854        Register Rright = right->is_single_cpu() ? right->as_register() :
1855                                                   right->as_register_lo();
1856        switch (code) {
1857          case lir_logic_and: __ andw (Rdst, Rleft, Rright); break;
1858          case lir_logic_or:  __ orrw (Rdst, Rleft, Rright); break;
1859          case lir_logic_xor: __ eorw (Rdst, Rleft, Rright); break;
1860          default: ShouldNotReachHere(); break;
1861        }
1862      }
1863    } else {
1864      Register Rdst = dst->as_register_lo();
1865      if (right->is_constant()) {
1866        switch (code) {
1867          case lir_logic_and: __ andr (Rdst, Rleft, right->as_jlong()); break;
1868          case lir_logic_or:  __ orr (Rdst, Rleft, right->as_jlong()); break;
1869          case lir_logic_xor: __ eor (Rdst, Rleft, right->as_jlong()); break;
1870          default: ShouldNotReachHere(); break;
1871        }
1872      } else {
1873        Register Rright = right->is_single_cpu() ? right->as_register() :
1874                                                   right->as_register_lo();
1875        switch (code) {
1876          case lir_logic_and: __ andr (Rdst, Rleft, Rright); break;
1877          case lir_logic_or:  __ orr (Rdst, Rleft, Rright); break;
1878          case lir_logic_xor: __ eor (Rdst, Rleft, Rright); break;
1879          default: ShouldNotReachHere(); break;
1880        }
1881      }
1882    }
1883 }
1884 
1885 
1886 
1887 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr illegal, LIR_Opr result, CodeEmitInfo* info) {
1888 
1889   // opcode check
1890   assert((code == lir_idiv) || (code == lir_irem), "opcode must be idiv or irem");
1891   bool is_irem = (code == lir_irem);
1892 
1893   // operand check
1894   assert(left->is_single_cpu(),   "left must be register");
1895   assert(right->is_single_cpu() || right->is_constant(),  "right must be register or constant");
1896   assert(result->is_single_cpu(), "result must be register");
1897   Register lreg = left->as_register();
1898   Register dreg = result->as_register();
1899 
1900   // power-of-2 constant check and codegen
1901   if (right->is_constant()) {
1902     int c = right->as_constant_ptr()->as_jint();
1903     assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant");
1904     if (is_irem) {
1905       if (c == 1) {
1906         // move 0 to dreg if divisor is 1
1907         __ movw(dreg, zr);
1908       } else {
1909         // use rscratch1 as intermediate result register
1910         __ negsw(rscratch1, lreg);
1911         __ andw(dreg, lreg, c - 1);
1912         __ andw(rscratch1, rscratch1, c - 1);
1913         __ csnegw(dreg, dreg, rscratch1, Assembler::MI);
1914       }
1915     } else {
1916       if (c == 1) {
1917         // move lreg to dreg if divisor is 1
1918         __ movw(dreg, lreg);
1919       } else {
1920         unsigned int shift = exact_log2(c);
1921         // use rscratch1 as intermediate result register
1922         __ asrw(rscratch1, lreg, 31);
1923         __ addw(rscratch1, lreg, rscratch1, Assembler::LSR, 32 - shift);
1924         __ asrw(dreg, rscratch1, shift);
1925       }
1926     }
1927   } else {
1928     Register rreg = right->as_register();
1929     __ corrected_idivl(dreg, lreg, rreg, is_irem, rscratch1);
1930   }
1931 }
1932 
1933 
1934 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
1935   if (opr1->is_constant() && opr2->is_single_cpu()) {
1936     // tableswitch
1937     Register reg = as_reg(opr2);
1938     struct tableswitch &table = switches[opr1->as_constant_ptr()->as_jint()];
1939     __ tableswitch(reg, table._first_key, table._last_key, table._branches, table._after);
1940   } else if (opr1->is_single_cpu() || opr1->is_double_cpu()) {
1941     Register reg1 = as_reg(opr1);
1942     if (opr2->is_single_cpu()) {
1943       // cpu register - cpu register
1944       Register reg2 = opr2->as_register();
1945       if (is_reference_type(opr1->type())) {
1946         __ cmpoop(reg1, reg2);
1947       } else {
1948         assert(!is_reference_type(opr2->type()), "cmp int, oop?");
1949         __ cmpw(reg1, reg2);
1950       }
1951       return;
1952     }
1953     if (opr2->is_double_cpu()) {
1954       // cpu register - cpu register
1955       Register reg2 = opr2->as_register_lo();
1956       __ cmp(reg1, reg2);
1957       return;
1958     }
1959 
1960     if (opr2->is_constant()) {
1961       bool is_32bit = false; // width of register operand
1962       jlong imm;
1963 
1964       switch(opr2->type()) {
1965       case T_INT:
1966         imm = opr2->as_constant_ptr()->as_jint();
1967         is_32bit = true;
1968         break;
1969       case T_LONG:
1970         imm = opr2->as_constant_ptr()->as_jlong();
1971         break;
1972       case T_ADDRESS:
1973         imm = opr2->as_constant_ptr()->as_jint();
1974         break;
1975       case T_METADATA:
1976         imm = (intptr_t)(opr2->as_constant_ptr()->as_metadata());
1977         break;
1978       case T_OBJECT:
1979       case T_ARRAY:
1980         jobject2reg(opr2->as_constant_ptr()->as_jobject(), rscratch1);
1981         __ cmpoop(reg1, rscratch1);
1982         return;
1983       default:
1984         ShouldNotReachHere();
1985         imm = 0;  // unreachable
1986         break;
1987       }
1988 
1989       if (Assembler::operand_valid_for_add_sub_immediate(imm)) {
1990         if (is_32bit)
1991           __ cmpw(reg1, imm);
1992         else
1993           __ subs(zr, reg1, imm);
1994         return;
1995       } else {
1996         __ mov(rscratch1, imm);
1997         if (is_32bit)
1998           __ cmpw(reg1, rscratch1);
1999         else
2000           __ cmp(reg1, rscratch1);
2001         return;
2002       }
2003     } else
2004       ShouldNotReachHere();
2005   } else if (opr1->is_single_fpu()) {
2006     FloatRegister reg1 = opr1->as_float_reg();
2007     assert(opr2->is_single_fpu(), "expect single float register");
2008     FloatRegister reg2 = opr2->as_float_reg();
2009     __ fcmps(reg1, reg2);
2010   } else if (opr1->is_double_fpu()) {
2011     FloatRegister reg1 = opr1->as_double_reg();
2012     assert(opr2->is_double_fpu(), "expect double float register");
2013     FloatRegister reg2 = opr2->as_double_reg();
2014     __ fcmpd(reg1, reg2);
2015   } else {
2016     ShouldNotReachHere();
2017   }
2018 }
2019 
2020 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op){
2021   if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
2022     bool is_unordered_less = (code == lir_ucmp_fd2i);
2023     if (left->is_single_fpu()) {
2024       __ float_cmp(true, is_unordered_less ? -1 : 1, left->as_float_reg(), right->as_float_reg(), dst->as_register());
2025     } else if (left->is_double_fpu()) {
2026       __ float_cmp(false, is_unordered_less ? -1 : 1, left->as_double_reg(), right->as_double_reg(), dst->as_register());
2027     } else {
2028       ShouldNotReachHere();
2029     }
2030   } else if (code == lir_cmp_l2i) {
2031     Label done;
2032     __ cmp(left->as_register_lo(), right->as_register_lo());
2033     __ mov(dst->as_register(), (uint64_t)-1L);
2034     __ br(Assembler::LT, done);
2035     __ csinc(dst->as_register(), zr, zr, Assembler::EQ);
2036     __ bind(done);
2037   } else {
2038     ShouldNotReachHere();
2039   }
2040 }
2041 
2042 
2043 void LIR_Assembler::align_call(LIR_Code code) {  }
2044 
2045 
2046 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
2047   address call = __ trampoline_call(Address(op->addr(), rtype));
2048   if (call == NULL) {
2049     bailout("trampoline stub overflow");
2050     return;
2051   }
2052   add_call_info(code_offset(), op->info());
2053 }
2054 
2055 
2056 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
2057   address call = __ ic_call(op->addr());
2058   if (call == NULL) {
2059     bailout("trampoline stub overflow");
2060     return;
2061   }
2062   add_call_info(code_offset(), op->info());
2063 }
2064 
2065 void LIR_Assembler::emit_static_call_stub() {
2066   address call_pc = __ pc();
2067   address stub = __ start_a_stub(call_stub_size());
2068   if (stub == NULL) {
2069     bailout("static call stub overflow");
2070     return;
2071   }
2072 
2073   int start = __ offset();
2074 
2075   __ relocate(static_stub_Relocation::spec(call_pc));
2076   __ emit_static_call_stub();
2077 
2078   assert(__ offset() - start + CompiledStaticCall::to_trampoline_stub_size()
2079         <= call_stub_size(), "stub too big");
2080   __ end_a_stub();
2081 }
2082 
2083 
2084 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
2085   assert(exceptionOop->as_register() == r0, "must match");
2086   assert(exceptionPC->as_register() == r3, "must match");
2087 
2088   // exception object is not added to oop map by LinearScan
2089   // (LinearScan assumes that no oops are in fixed registers)
2090   info->add_register_oop(exceptionOop);
2091   Runtime1::StubID unwind_id;
2092 
2093   // get current pc information
2094   // pc is only needed if the method has an exception handler, the unwind code does not need it.
2095   if (compilation()->debug_info_recorder()->last_pc_offset() == __ offset()) {
2096     // As no instructions have been generated yet for this LIR node it's
2097     // possible that an oop map already exists for the current offset.
2098     // In that case insert an dummy NOP here to ensure all oop map PCs
2099     // are unique. See JDK-8237483.
2100     __ nop();
2101   }
2102   int pc_for_athrow_offset = __ offset();
2103   InternalAddress pc_for_athrow(__ pc());
2104   __ adr(exceptionPC->as_register(), pc_for_athrow);
2105   add_call_info(pc_for_athrow_offset, info); // for exception handler
2106 
2107   __ verify_not_null_oop(r0);
2108   // search an exception handler (r0: exception oop, r3: throwing pc)
2109   if (compilation()->has_fpu_code()) {
2110     unwind_id = Runtime1::handle_exception_id;
2111   } else {
2112     unwind_id = Runtime1::handle_exception_nofpu_id;
2113   }
2114   __ far_call(RuntimeAddress(Runtime1::entry_for(unwind_id)));
2115 
2116   // FIXME: enough room for two byte trap   ????
2117   __ nop();
2118 }
2119 
2120 
2121 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
2122   assert(exceptionOop->as_register() == r0, "must match");
2123 
2124   __ b(_unwind_handler_entry);
2125 }
2126 
2127 
2128 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2129   Register lreg = left->is_single_cpu() ? left->as_register() : left->as_register_lo();
2130   Register dreg = dest->is_single_cpu() ? dest->as_register() : dest->as_register_lo();
2131 
2132   switch (left->type()) {
2133     case T_INT: {
2134       switch (code) {
2135       case lir_shl:  __ lslvw (dreg, lreg, count->as_register()); break;
2136       case lir_shr:  __ asrvw (dreg, lreg, count->as_register()); break;
2137       case lir_ushr: __ lsrvw (dreg, lreg, count->as_register()); break;
2138       default:
2139         ShouldNotReachHere();
2140         break;
2141       }
2142       break;
2143     case T_LONG:
2144     case T_ADDRESS:
2145     case T_OBJECT:
2146       switch (code) {
2147       case lir_shl:  __ lslv (dreg, lreg, count->as_register()); break;
2148       case lir_shr:  __ asrv (dreg, lreg, count->as_register()); break;
2149       case lir_ushr: __ lsrv (dreg, lreg, count->as_register()); break;
2150       default:
2151         ShouldNotReachHere();
2152         break;
2153       }
2154       break;
2155     default:
2156       ShouldNotReachHere();
2157       break;
2158     }
2159   }
2160 }
2161 
2162 
2163 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2164   Register dreg = dest->is_single_cpu() ? dest->as_register() : dest->as_register_lo();
2165   Register lreg = left->is_single_cpu() ? left->as_register() : left->as_register_lo();
2166 
2167   switch (left->type()) {
2168     case T_INT: {
2169       switch (code) {
2170       case lir_shl:  __ lslw (dreg, lreg, count); break;
2171       case lir_shr:  __ asrw (dreg, lreg, count); break;
2172       case lir_ushr: __ lsrw (dreg, lreg, count); break;
2173       default:
2174         ShouldNotReachHere();
2175         break;
2176       }
2177       break;
2178     case T_LONG:
2179     case T_ADDRESS:
2180     case T_OBJECT:
2181       switch (code) {
2182       case lir_shl:  __ lsl (dreg, lreg, count); break;
2183       case lir_shr:  __ asr (dreg, lreg, count); break;
2184       case lir_ushr: __ lsr (dreg, lreg, count); break;
2185       default:
2186         ShouldNotReachHere();
2187         break;
2188       }
2189       break;
2190     default:
2191       ShouldNotReachHere();
2192       break;
2193     }
2194   }
2195 }
2196 
2197 
2198 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) {
2199   assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2200   int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2201   assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2202   __ str (r, Address(sp, offset_from_rsp_in_bytes));
2203 }
2204 
2205 
2206 void LIR_Assembler::store_parameter(jint c,     int offset_from_rsp_in_words) {
2207   assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2208   int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2209   assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2210   __ mov (rscratch1, c);
2211   __ str (rscratch1, Address(sp, offset_from_rsp_in_bytes));
2212 }
2213 
2214 
2215 void LIR_Assembler::store_parameter(jobject o,  int offset_from_rsp_in_words) {
2216   ShouldNotReachHere();
2217   assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2218   int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2219   assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2220   __ lea(rscratch1, __ constant_oop_address(o));
2221   __ str(rscratch1, Address(sp, offset_from_rsp_in_bytes));
2222 }
2223 
2224 
2225 // This code replaces a call to arraycopy; no exception may
2226 // be thrown in this code, they must be thrown in the System.arraycopy
2227 // activation frame; we could save some checks if this would not be the case
2228 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
2229   ciArrayKlass* default_type = op->expected_type();
2230   Register src = op->src()->as_register();
2231   Register dst = op->dst()->as_register();
2232   Register src_pos = op->src_pos()->as_register();
2233   Register dst_pos = op->dst_pos()->as_register();
2234   Register length  = op->length()->as_register();
2235   Register tmp = op->tmp()->as_register();
2236 
2237   CodeStub* stub = op->stub();
2238   int flags = op->flags();
2239   BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL;
2240   if (is_reference_type(basic_type)) basic_type = T_OBJECT;
2241 
2242   // if we don't know anything, just go through the generic arraycopy
2243   if (default_type == NULL // || basic_type == T_OBJECT
2244       ) {
2245     Label done;
2246     assert(src == r1 && src_pos == r2, "mismatch in calling convention");
2247 
2248     // Save the arguments in case the generic arraycopy fails and we
2249     // have to fall back to the JNI stub
2250     __ stp(dst,     dst_pos, Address(sp, 0*BytesPerWord));
2251     __ stp(length,  src_pos, Address(sp, 2*BytesPerWord));
2252     __ str(src,              Address(sp, 4*BytesPerWord));
2253 
2254     address copyfunc_addr = StubRoutines::generic_arraycopy();
2255     assert(copyfunc_addr != NULL, "generic arraycopy stub required");
2256 
2257     // The arguments are in java calling convention so we shift them
2258     // to C convention
2259     assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4);
2260     __ mov(c_rarg0, j_rarg0);
2261     assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4);
2262     __ mov(c_rarg1, j_rarg1);
2263     assert_different_registers(c_rarg2, j_rarg3, j_rarg4);
2264     __ mov(c_rarg2, j_rarg2);
2265     assert_different_registers(c_rarg3, j_rarg4);
2266     __ mov(c_rarg3, j_rarg3);
2267     __ mov(c_rarg4, j_rarg4);
2268 #ifndef PRODUCT
2269     if (PrintC1Statistics) {
2270       __ incrementw(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
2271     }
2272 #endif
2273     __ far_call(RuntimeAddress(copyfunc_addr));
2274 
2275     __ cbz(r0, *stub->continuation());
2276 
2277     // Reload values from the stack so they are where the stub
2278     // expects them.
2279     __ ldp(dst,     dst_pos, Address(sp, 0*BytesPerWord));
2280     __ ldp(length,  src_pos, Address(sp, 2*BytesPerWord));
2281     __ ldr(src,              Address(sp, 4*BytesPerWord));
2282 
2283     // r0 is -1^K where K == partial copied count
2284     __ eonw(rscratch1, r0, zr);
2285     // adjust length down and src/end pos up by partial copied count
2286     __ subw(length, length, rscratch1);
2287     __ addw(src_pos, src_pos, rscratch1);
2288     __ addw(dst_pos, dst_pos, rscratch1);
2289     __ b(*stub->entry());
2290 
2291     __ bind(*stub->continuation());
2292     return;
2293   }
2294 
2295   assert(default_type != NULL && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
2296 
2297   int elem_size = type2aelembytes(basic_type);
2298   int scale = exact_log2(elem_size);
2299 
2300   Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes());
2301   Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes());
2302   Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes());
2303   Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes());
2304 
2305   // test for NULL
2306   if (flags & LIR_OpArrayCopy::src_null_check) {
2307     __ cbz(src, *stub->entry());
2308   }
2309   if (flags & LIR_OpArrayCopy::dst_null_check) {
2310     __ cbz(dst, *stub->entry());
2311   }
2312 
2313   // If the compiler was not able to prove that exact type of the source or the destination
2314   // of the arraycopy is an array type, check at runtime if the source or the destination is
2315   // an instance type.
2316   if (flags & LIR_OpArrayCopy::type_check) {
2317     if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::dst_objarray)) {
2318       __ load_klass(tmp, dst);
2319       __ ldrw(rscratch1, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2320       __ cmpw(rscratch1, Klass::_lh_neutral_value);
2321       __ br(Assembler::GE, *stub->entry());
2322     }
2323 
2324     if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::src_objarray)) {
2325       __ load_klass(tmp, src);
2326       __ ldrw(rscratch1, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2327       __ cmpw(rscratch1, Klass::_lh_neutral_value);
2328       __ br(Assembler::GE, *stub->entry());
2329     }
2330   }
2331 
2332   // check if negative
2333   if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
2334     __ cmpw(src_pos, 0);
2335     __ br(Assembler::LT, *stub->entry());
2336   }
2337   if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
2338     __ cmpw(dst_pos, 0);
2339     __ br(Assembler::LT, *stub->entry());
2340   }
2341 
2342   if (flags & LIR_OpArrayCopy::length_positive_check) {
2343     __ cmpw(length, 0);
2344     __ br(Assembler::LT, *stub->entry());
2345   }
2346 
2347   if (flags & LIR_OpArrayCopy::src_range_check) {
2348     __ addw(tmp, src_pos, length);
2349     __ ldrw(rscratch1, src_length_addr);
2350     __ cmpw(tmp, rscratch1);
2351     __ br(Assembler::HI, *stub->entry());
2352   }
2353   if (flags & LIR_OpArrayCopy::dst_range_check) {
2354     __ addw(tmp, dst_pos, length);
2355     __ ldrw(rscratch1, dst_length_addr);
2356     __ cmpw(tmp, rscratch1);
2357     __ br(Assembler::HI, *stub->entry());
2358   }
2359 
2360   if (flags & LIR_OpArrayCopy::type_check) {
2361     // We don't know the array types are compatible
2362     if (basic_type != T_OBJECT) {
2363       // Simple test for basic type arrays
2364       if (UseCompressedClassPointers) {
2365         __ ldrw(tmp, src_klass_addr);
2366         __ ldrw(rscratch1, dst_klass_addr);
2367         __ cmpw(tmp, rscratch1);
2368       } else {
2369         __ ldr(tmp, src_klass_addr);
2370         __ ldr(rscratch1, dst_klass_addr);
2371         __ cmp(tmp, rscratch1);
2372       }
2373       __ br(Assembler::NE, *stub->entry());
2374     } else {
2375       // For object arrays, if src is a sub class of dst then we can
2376       // safely do the copy.
2377       Label cont, slow;
2378 
2379 #define PUSH(r1, r2)                                    \
2380       stp(r1, r2, __ pre(sp, -2 * wordSize));
2381 
2382 #define POP(r1, r2)                                     \
2383       ldp(r1, r2, __ post(sp, 2 * wordSize));
2384 
2385       __ PUSH(src, dst);
2386 
2387       __ load_klass(src, src);
2388       __ load_klass(dst, dst);


2389 
2390       __ check_klass_subtype_fast_path(src, dst, tmp, &cont, &slow, NULL);
2391 
2392       __ PUSH(src, dst);
2393       __ far_call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
2394       __ POP(src, dst);
2395 
2396       __ cbnz(src, cont);
2397 
2398       __ bind(slow);
2399       __ POP(src, dst);
2400 
2401       address copyfunc_addr = StubRoutines::checkcast_arraycopy();
2402       if (copyfunc_addr != NULL) { // use stub if available
2403         // src is not a sub class of dst so we have to do a
2404         // per-element check.
2405 
2406         int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
2407         if ((flags & mask) != mask) {
2408           // Check that at least both of them object arrays.
2409           assert(flags & mask, "one of the two should be known to be an object array");
2410 
2411           if (!(flags & LIR_OpArrayCopy::src_objarray)) {
2412             __ load_klass(tmp, src);
2413           } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
2414             __ load_klass(tmp, dst);
2415           }
2416           int lh_offset = in_bytes(Klass::layout_helper_offset());
2417           Address klass_lh_addr(tmp, lh_offset);
2418           jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
2419           __ ldrw(rscratch1, klass_lh_addr);
2420           __ mov(rscratch2, objArray_lh);
2421           __ eorw(rscratch1, rscratch1, rscratch2);
2422           __ cbnzw(rscratch1, *stub->entry());
2423         }
2424 
2425        // Spill because stubs can use any register they like and it's
2426        // easier to restore just those that we care about.
2427         __ stp(dst,     dst_pos, Address(sp, 0*BytesPerWord));
2428         __ stp(length,  src_pos, Address(sp, 2*BytesPerWord));
2429         __ str(src,              Address(sp, 4*BytesPerWord));
2430 
2431         __ lea(c_rarg0, Address(src, src_pos, Address::uxtw(scale)));
2432         __ add(c_rarg0, c_rarg0, arrayOopDesc::base_offset_in_bytes(basic_type));
2433         assert_different_registers(c_rarg0, dst, dst_pos, length);
2434         __ lea(c_rarg1, Address(dst, dst_pos, Address::uxtw(scale)));
2435         __ add(c_rarg1, c_rarg1, arrayOopDesc::base_offset_in_bytes(basic_type));
2436         assert_different_registers(c_rarg1, dst, length);
2437         __ uxtw(c_rarg2, length);
2438         assert_different_registers(c_rarg2, dst);
2439 
2440         __ load_klass(c_rarg4, dst);
2441         __ ldr(c_rarg4, Address(c_rarg4, ObjArrayKlass::element_klass_offset()));
2442         __ ldrw(c_rarg3, Address(c_rarg4, Klass::super_check_offset_offset()));
2443         __ far_call(RuntimeAddress(copyfunc_addr));
2444 
2445 #ifndef PRODUCT
2446         if (PrintC1Statistics) {
2447           Label failed;
2448           __ cbnz(r0, failed);
2449           __ incrementw(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt));
2450           __ bind(failed);
2451         }
2452 #endif
2453 
2454         __ cbz(r0, *stub->continuation());
2455 
2456 #ifndef PRODUCT
2457         if (PrintC1Statistics) {
2458           __ incrementw(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt));
2459         }
2460 #endif
2461         assert_different_registers(dst, dst_pos, length, src_pos, src, r0, rscratch1);
2462 
2463         // Restore previously spilled arguments
2464         __ ldp(dst,     dst_pos, Address(sp, 0*BytesPerWord));
2465         __ ldp(length,  src_pos, Address(sp, 2*BytesPerWord));
2466         __ ldr(src,              Address(sp, 4*BytesPerWord));
2467 
2468         // return value is -1^K where K is partial copied count
2469         __ eonw(rscratch1, r0, zr);
2470         // adjust length down and src/end pos up by partial copied count
2471         __ subw(length, length, rscratch1);
2472         __ addw(src_pos, src_pos, rscratch1);
2473         __ addw(dst_pos, dst_pos, rscratch1);
2474       }
2475 
2476       __ b(*stub->entry());
2477 
2478       __ bind(cont);
2479       __ POP(src, dst);
2480     }
2481   }
2482 
2483 #ifdef ASSERT
2484   if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
2485     // Sanity check the known type with the incoming class.  For the
2486     // primitive case the types must match exactly with src.klass and
2487     // dst.klass each exactly matching the default type.  For the
2488     // object array case, if no type check is needed then either the
2489     // dst type is exactly the expected type and the src type is a
2490     // subtype which we can't check or src is the same array as dst
2491     // but not necessarily exactly of type default_type.
2492     Label known_ok, halt;
2493     __ mov_metadata(tmp, default_type->constant_encoding());
2494     if (UseCompressedClassPointers) {
2495       __ encode_klass_not_null(tmp);
2496     }
2497 

2498     if (basic_type != T_OBJECT) {
2499 
2500       if (UseCompressedClassPointers) {
2501         __ ldrw(rscratch1, dst_klass_addr);
2502         __ cmpw(tmp, rscratch1);
2503       } else {
2504         __ ldr(rscratch1, dst_klass_addr);
2505         __ cmp(tmp, rscratch1);
2506       }
2507       __ br(Assembler::NE, halt);
2508       if (UseCompressedClassPointers) {
2509         __ ldrw(rscratch1, src_klass_addr);
2510         __ cmpw(tmp, rscratch1);
2511       } else {
2512         __ ldr(rscratch1, src_klass_addr);
2513         __ cmp(tmp, rscratch1);
2514       }
2515       __ br(Assembler::EQ, known_ok);
2516     } else {
2517       if (UseCompressedClassPointers) {
2518         __ ldrw(rscratch1, dst_klass_addr);
2519         __ cmpw(tmp, rscratch1);
2520       } else {
2521         __ ldr(rscratch1, dst_klass_addr);
2522         __ cmp(tmp, rscratch1);
2523       }
2524       __ br(Assembler::EQ, known_ok);
2525       __ cmp(src, dst);
2526       __ br(Assembler::EQ, known_ok);
2527     }
2528     __ bind(halt);
2529     __ stop("incorrect type information in arraycopy");
2530     __ bind(known_ok);
2531   }
2532 #endif
2533 
2534 #ifndef PRODUCT
2535   if (PrintC1Statistics) {
2536     __ incrementw(ExternalAddress(Runtime1::arraycopy_count_address(basic_type)));
2537   }
2538 #endif
2539 
2540   __ lea(c_rarg0, Address(src, src_pos, Address::uxtw(scale)));
2541   __ add(c_rarg0, c_rarg0, arrayOopDesc::base_offset_in_bytes(basic_type));
2542   assert_different_registers(c_rarg0, dst, dst_pos, length);
2543   __ lea(c_rarg1, Address(dst, dst_pos, Address::uxtw(scale)));
2544   __ add(c_rarg1, c_rarg1, arrayOopDesc::base_offset_in_bytes(basic_type));
2545   assert_different_registers(c_rarg1, dst, length);
2546   __ uxtw(c_rarg2, length);
2547   assert_different_registers(c_rarg2, dst);
2548 
2549   bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
2550   bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
2551   const char *name;
2552   address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
2553 
2554  CodeBlob *cb = CodeCache::find_blob(entry);
2555  if (cb) {
2556    __ far_call(RuntimeAddress(entry));
2557  } else {
2558    __ call_VM_leaf(entry, 3);
2559  }
2560 
2561   __ bind(*stub->continuation());
2562 }
2563 
2564 
2565 
2566 
2567 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
2568   Register obj = op->obj_opr()->as_register();  // may not be an oop
2569   Register hdr = op->hdr_opr()->as_register();
2570   Register lock = op->lock_opr()->as_register();
2571   if (UseHeavyMonitors) {
2572     __ b(*op->stub()->entry());
2573   } else if (op->code() == lir_lock) {
2574     assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2575     // add debug info for NullPointerException only if one is possible
2576     int null_check_offset = __ lock_object(hdr, obj, lock, *op->stub()->entry());
2577     if (op->info() != NULL) {
2578       add_debug_info_for_null_check(null_check_offset, op->info());
2579     }
2580     // done
2581   } else if (op->code() == lir_unlock) {
2582     assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2583     __ unlock_object(hdr, obj, lock, *op->stub()->entry());
2584   } else {
2585     Unimplemented();
2586   }
2587   __ bind(*op->stub()->continuation());
2588 }
2589 
2590 void LIR_Assembler::emit_load_klass(LIR_OpLoadKlass* op) {
2591   Register obj = op->obj()->as_pointer_register();
2592   Register result = op->result_opr()->as_pointer_register();

2593 
2594   CodeEmitInfo* info = op->info();
2595   if (info != NULL) {
2596     add_debug_info_for_null_check_here(info);
2597   }
2598 
2599   if (UseCompressedClassPointers) {
2600     __ ldrw(result, Address (obj, oopDesc::klass_offset_in_bytes()));
2601     __ decode_klass_not_null(result);
2602   } else {
2603     __ ldr(result, Address (obj, oopDesc::klass_offset_in_bytes()));
2604   }








2605 }
2606 
2607 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
2608   ciMethod* method = op->profiled_method();
2609   int bci          = op->profiled_bci();
2610   ciMethod* callee = op->profiled_callee();
2611 
2612   // Update counter for all call types
2613   ciMethodData* md = method->method_data_or_null();
2614   assert(md != NULL, "Sanity");
2615   ciProfileData* data = md->bci_to_data(bci);
2616   assert(data != NULL && data->is_CounterData(), "need CounterData for calls");
2617   assert(op->mdo()->is_single_cpu(),  "mdo must be allocated");
2618   Register mdo  = op->mdo()->as_register();
2619   __ mov_metadata(mdo, md->constant_encoding());
2620   Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
2621   // Perform additional virtual call profiling for invokevirtual and
2622   // invokeinterface bytecodes
2623   if (op->should_profile_receiver_type()) {
2624     assert(op->recv()->is_single_cpu(), "recv must be allocated");
2625     Register recv = op->recv()->as_register();
2626     assert_different_registers(mdo, recv);
2627     assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
2628     ciKlass* known_klass = op->known_holder();
2629     if (C1OptimizeVirtualCallProfiling && known_klass != NULL) {
2630       // We know the type that will be seen at this call site; we can
2631       // statically update the MethodData* rather than needing to do
2632       // dynamic tests on the receiver type
2633 
2634       // NOTE: we should probably put a lock around this search to
2635       // avoid collisions by concurrent compilations
2636       ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
2637       uint i;
2638       for (i = 0; i < VirtualCallData::row_limit(); i++) {
2639         ciKlass* receiver = vc_data->receiver(i);
2640         if (known_klass->equals(receiver)) {
2641           Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
2642           __ addptr(data_addr, DataLayout::counter_increment);
2643           return;
2644         }
2645       }
2646 
2647       // Receiver type not found in profile data; select an empty slot
2648 
2649       // Note that this is less efficient than it should be because it
2650       // always does a write to the receiver part of the
2651       // VirtualCallData rather than just the first time
2652       for (i = 0; i < VirtualCallData::row_limit(); i++) {
2653         ciKlass* receiver = vc_data->receiver(i);
2654         if (receiver == NULL) {
2655           Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)));
2656           __ mov_metadata(rscratch1, known_klass->constant_encoding());
2657           __ lea(rscratch2, recv_addr);
2658           __ str(rscratch1, Address(rscratch2));
2659           Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
2660           __ addptr(data_addr, DataLayout::counter_increment);
2661           return;
2662         }
2663       }
2664     } else {
2665       __ load_klass(recv, recv);

2666       Label update_done;
2667       type_profile_helper(mdo, md, data, recv, &update_done);
2668       // Receiver did not match any saved receiver and there is no empty row for it.
2669       // Increment total counter to indicate polymorphic case.
2670       __ addptr(counter_addr, DataLayout::counter_increment);
2671 
2672       __ bind(update_done);
2673     }
2674   } else {
2675     // Static call
2676     __ addptr(counter_addr, DataLayout::counter_increment);
2677   }
2678 }
2679 
2680 
2681 void LIR_Assembler::emit_delay(LIR_OpDelay*) {
2682   Unimplemented();
2683 }
2684 
2685 
2686 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) {
2687   __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no));
2688 }
2689 
2690 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
2691   assert(op->crc()->is_single_cpu(),  "crc must be register");
2692   assert(op->val()->is_single_cpu(),  "byte value must be register");
2693   assert(op->result_opr()->is_single_cpu(), "result must be register");
2694   Register crc = op->crc()->as_register();
2695   Register val = op->val()->as_register();
2696   Register res = op->result_opr()->as_register();
2697 
2698   assert_different_registers(val, crc, res);
2699   uint64_t offset;
2700   __ adrp(res, ExternalAddress(StubRoutines::crc_table_addr()), offset);
2701   if (offset) __ add(res, res, offset);
2702 
2703   __ mvnw(crc, crc); // ~crc
2704   __ update_byte_crc32(crc, val, res);
2705   __ mvnw(res, crc); // ~crc
2706 }
2707 
2708 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
2709   COMMENT("emit_profile_type {");
2710   Register obj = op->obj()->as_register();
2711   Register tmp = op->tmp()->as_pointer_register();
2712   Address mdo_addr = as_Address(op->mdp()->as_address_ptr());
2713   ciKlass* exact_klass = op->exact_klass();
2714   intptr_t current_klass = op->current_klass();
2715   bool not_null = op->not_null();
2716   bool no_conflict = op->no_conflict();
2717 
2718   Label update, next, none;
2719 
2720   bool do_null = !not_null;
2721   bool exact_klass_set = exact_klass != NULL && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
2722   bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
2723 
2724   assert(do_null || do_update, "why are we here?");
2725   assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
2726   assert(mdo_addr.base() != rscratch1, "wrong register");
2727 
2728   __ verify_oop(obj);
2729 
2730   if (tmp != obj) {
2731     __ mov(tmp, obj);
2732   }
2733   if (do_null) {
2734     __ cbnz(tmp, update);
2735     if (!TypeEntries::was_null_seen(current_klass)) {
2736       __ ldr(rscratch2, mdo_addr);
2737       __ orr(rscratch2, rscratch2, TypeEntries::null_seen);
2738       __ str(rscratch2, mdo_addr);
2739     }
2740     if (do_update) {
2741 #ifndef ASSERT
2742       __ b(next);
2743     }
2744 #else
2745       __ b(next);
2746     }
2747   } else {
2748     __ cbnz(tmp, update);
2749     __ stop("unexpected null obj");
2750 #endif
2751   }
2752 
2753   __ bind(update);
2754 
2755   if (do_update) {
2756 #ifdef ASSERT
2757     if (exact_klass != NULL) {
2758       Label ok;
2759       __ load_klass(tmp, tmp);

2760       __ mov_metadata(rscratch1, exact_klass->constant_encoding());
2761       __ eor(rscratch1, tmp, rscratch1);
2762       __ cbz(rscratch1, ok);
2763       __ stop("exact klass and actual klass differ");
2764       __ bind(ok);
2765     }
2766 #endif
2767     if (!no_conflict) {
2768       if (exact_klass == NULL || TypeEntries::is_type_none(current_klass)) {
2769         if (exact_klass != NULL) {
2770           __ mov_metadata(tmp, exact_klass->constant_encoding());
2771         } else {
2772           __ load_klass(tmp, tmp);

2773         }
2774 
2775         __ ldr(rscratch2, mdo_addr);
2776         __ eor(tmp, tmp, rscratch2);
2777         __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2778         // klass seen before, nothing to do. The unknown bit may have been
2779         // set already but no need to check.
2780         __ cbz(rscratch1, next);
2781 
2782         __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2783 
2784         if (TypeEntries::is_type_none(current_klass)) {
2785           __ cbz(rscratch2, none);
2786           __ cmp(rscratch2, (u1)TypeEntries::null_seen);
2787           __ br(Assembler::EQ, none);
2788           // There is a chance that the checks above (re-reading profiling
2789           // data from memory) fail if another thread has just set the
2790           // profiling to this obj's klass
2791           __ dmb(Assembler::ISHLD);
2792           __ ldr(rscratch2, mdo_addr);
2793           __ eor(tmp, tmp, rscratch2);
2794           __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2795           __ cbz(rscratch1, next);
2796         }
2797       } else {
2798         assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
2799                ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
2800 
2801         __ ldr(tmp, mdo_addr);
2802         __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2803       }
2804 
2805       // different than before. Cannot keep accurate profile.
2806       __ ldr(rscratch2, mdo_addr);
2807       __ orr(rscratch2, rscratch2, TypeEntries::type_unknown);
2808       __ str(rscratch2, mdo_addr);
2809 
2810       if (TypeEntries::is_type_none(current_klass)) {
2811         __ b(next);
2812 
2813         __ bind(none);
2814         // first time here. Set profile type.
2815         __ str(tmp, mdo_addr);
2816       }
2817     } else {
2818       // There's a single possible klass at this profile point
2819       assert(exact_klass != NULL, "should be");
2820       if (TypeEntries::is_type_none(current_klass)) {
2821         __ mov_metadata(tmp, exact_klass->constant_encoding());
2822         __ ldr(rscratch2, mdo_addr);
2823         __ eor(tmp, tmp, rscratch2);
2824         __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2825         __ cbz(rscratch1, next);
2826 #ifdef ASSERT
2827         {
2828           Label ok;
2829           __ ldr(rscratch1, mdo_addr);
2830           __ cbz(rscratch1, ok);
2831           __ cmp(rscratch1, (u1)TypeEntries::null_seen);
2832           __ br(Assembler::EQ, ok);
2833           // may have been set by another thread
2834           __ dmb(Assembler::ISHLD);
2835           __ mov_metadata(rscratch1, exact_klass->constant_encoding());
2836           __ ldr(rscratch2, mdo_addr);
2837           __ eor(rscratch2, rscratch1, rscratch2);
2838           __ andr(rscratch2, rscratch2, TypeEntries::type_mask);
2839           __ cbz(rscratch2, ok);
2840 
2841           __ stop("unexpected profiling mismatch");
2842           __ bind(ok);
2843         }
2844 #endif
2845         // first time here. Set profile type.
2846         __ str(tmp, mdo_addr);
2847       } else {
2848         assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
2849                ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
2850 
2851         __ ldr(tmp, mdo_addr);
2852         __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2853 
2854         __ orr(tmp, tmp, TypeEntries::type_unknown);
2855         __ str(tmp, mdo_addr);
2856         // FIXME: Write barrier needed here?
2857       }
2858     }
2859 
2860     __ bind(next);
2861   }
2862   COMMENT("} emit_profile_type");
2863 }
2864 
2865 
2866 void LIR_Assembler::align_backward_branch_target() {
2867 }
2868 
2869 
2870 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) {
2871   // tmp must be unused
2872   assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2873 
2874   if (left->is_single_cpu()) {
2875     assert(dest->is_single_cpu(), "expect single result reg");
2876     __ negw(dest->as_register(), left->as_register());
2877   } else if (left->is_double_cpu()) {
2878     assert(dest->is_double_cpu(), "expect double result reg");
2879     __ neg(dest->as_register_lo(), left->as_register_lo());
2880   } else if (left->is_single_fpu()) {
2881     assert(dest->is_single_fpu(), "expect single float result reg");
2882     __ fnegs(dest->as_float_reg(), left->as_float_reg());
2883   } else {
2884     assert(left->is_double_fpu(), "expect double float operand reg");
2885     assert(dest->is_double_fpu(), "expect double float result reg");
2886     __ fnegd(dest->as_double_reg(), left->as_double_reg());
2887   }
2888 }
2889 
2890 
2891 void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
2892   if (patch_code != lir_patch_none) {
2893     deoptimize_trap(info);
2894     return;
2895   }
2896 
2897   __ lea(dest->as_register_lo(), as_Address(addr->as_address_ptr()));
2898 }
2899 
2900 
2901 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
2902   assert(!tmp->is_valid(), "don't need temporary");
2903 
2904   CodeBlob *cb = CodeCache::find_blob(dest);
2905   if (cb) {
2906     __ far_call(RuntimeAddress(dest));
2907   } else {
2908     __ mov(rscratch1, RuntimeAddress(dest));
2909     __ blr(rscratch1);
2910   }
2911 
2912   if (info != NULL) {
2913     add_call_info_here(info);
2914   }
2915 }
2916 
2917 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
2918   if (dest->is_address() || src->is_address()) {
2919     move_op(src, dest, type, lir_patch_none, info,
2920             /*pop_fpu_stack*/false, /*wide*/false);
2921   } else {
2922     ShouldNotReachHere();
2923   }
2924 }
2925 
2926 #ifdef ASSERT
2927 // emit run-time assertion
2928 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
2929   assert(op->code() == lir_assert, "must be");
2930 
2931   if (op->in_opr1()->is_valid()) {
2932     assert(op->in_opr2()->is_valid(), "both operands must be valid");
2933     comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
2934   } else {
2935     assert(op->in_opr2()->is_illegal(), "both operands must be illegal");
2936     assert(op->condition() == lir_cond_always, "no other conditions allowed");
2937   }
2938 
2939   Label ok;
2940   if (op->condition() != lir_cond_always) {
2941     Assembler::Condition acond = Assembler::AL;
2942     switch (op->condition()) {
2943       case lir_cond_equal:        acond = Assembler::EQ;  break;
2944       case lir_cond_notEqual:     acond = Assembler::NE;  break;
2945       case lir_cond_less:         acond = Assembler::LT;  break;
2946       case lir_cond_lessEqual:    acond = Assembler::LE;  break;
2947       case lir_cond_greaterEqual: acond = Assembler::GE;  break;
2948       case lir_cond_greater:      acond = Assembler::GT;  break;
2949       case lir_cond_belowEqual:   acond = Assembler::LS;  break;
2950       case lir_cond_aboveEqual:   acond = Assembler::HS;  break;
2951       default:                    ShouldNotReachHere();
2952     }
2953     __ br(acond, ok);
2954   }
2955   if (op->halt()) {
2956     const char* str = __ code_string(op->msg());
2957     __ stop(str);
2958   } else {
2959     breakpoint();
2960   }
2961   __ bind(ok);
2962 }
2963 #endif
2964 
2965 #ifndef PRODUCT
2966 #define COMMENT(x)   do { __ block_comment(x); } while (0)
2967 #else
2968 #define COMMENT(x)
2969 #endif
2970 
2971 void LIR_Assembler::membar() {
2972   COMMENT("membar");
2973   __ membar(MacroAssembler::AnyAny);
2974 }
2975 
2976 void LIR_Assembler::membar_acquire() {
2977   __ membar(Assembler::LoadLoad|Assembler::LoadStore);
2978 }
2979 
2980 void LIR_Assembler::membar_release() {
2981   __ membar(Assembler::LoadStore|Assembler::StoreStore);
2982 }
2983 
2984 void LIR_Assembler::membar_loadload() {
2985   __ membar(Assembler::LoadLoad);
2986 }
2987 
2988 void LIR_Assembler::membar_storestore() {
2989   __ membar(MacroAssembler::StoreStore);
2990 }
2991 
2992 void LIR_Assembler::membar_loadstore() { __ membar(MacroAssembler::LoadStore); }
2993 
2994 void LIR_Assembler::membar_storeload() { __ membar(MacroAssembler::StoreLoad); }
2995 
2996 void LIR_Assembler::on_spin_wait() {
2997   __ spin_wait();
2998 }
2999 
3000 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
3001   __ mov(result_reg->as_register(), rthread);
3002 }
3003 
3004 
3005 void LIR_Assembler::peephole(LIR_List *lir) {
3006 #if 0
3007   if (tableswitch_count >= max_tableswitches)
3008     return;
3009 
3010   /*
3011     This finite-state automaton recognizes sequences of compare-and-
3012     branch instructions.  We will turn them into a tableswitch.  You
3013     could argue that C1 really shouldn't be doing this sort of
3014     optimization, but without it the code is really horrible.
3015   */
3016 
3017   enum { start_s, cmp1_s, beq_s, cmp_s } state;
3018   int first_key, last_key = -2147483648;
3019   int next_key = 0;
3020   int start_insn = -1;
3021   int last_insn = -1;
3022   Register reg = noreg;
3023   LIR_Opr reg_opr;
3024   state = start_s;
3025 
3026   LIR_OpList* inst = lir->instructions_list();
3027   for (int i = 0; i < inst->length(); i++) {
3028     LIR_Op* op = inst->at(i);
3029     switch (state) {
3030     case start_s:
3031       first_key = -1;
3032       start_insn = i;
3033       switch (op->code()) {
3034       case lir_cmp:
3035         LIR_Opr opr1 = op->as_Op2()->in_opr1();
3036         LIR_Opr opr2 = op->as_Op2()->in_opr2();
3037         if (opr1->is_cpu_register() && opr1->is_single_cpu()
3038             && opr2->is_constant()
3039             && opr2->type() == T_INT) {
3040           reg_opr = opr1;
3041           reg = opr1->as_register();
3042           first_key = opr2->as_constant_ptr()->as_jint();
3043           next_key = first_key + 1;
3044           state = cmp_s;
3045           goto next_state;
3046         }
3047         break;
3048       }
3049       break;
3050     case cmp_s:
3051       switch (op->code()) {
3052       case lir_branch:
3053         if (op->as_OpBranch()->cond() == lir_cond_equal) {
3054           state = beq_s;
3055           last_insn = i;
3056           goto next_state;
3057         }
3058       }
3059       state = start_s;
3060       break;
3061     case beq_s:
3062       switch (op->code()) {
3063       case lir_cmp: {
3064         LIR_Opr opr1 = op->as_Op2()->in_opr1();
3065         LIR_Opr opr2 = op->as_Op2()->in_opr2();
3066         if (opr1->is_cpu_register() && opr1->is_single_cpu()
3067             && opr1->as_register() == reg
3068             && opr2->is_constant()
3069             && opr2->type() == T_INT
3070             && opr2->as_constant_ptr()->as_jint() == next_key) {
3071           last_key = next_key;
3072           next_key++;
3073           state = cmp_s;
3074           goto next_state;
3075         }
3076       }
3077       }
3078       last_key = next_key;
3079       state = start_s;
3080       break;
3081     default:
3082       assert(false, "impossible state");
3083     }
3084     if (state == start_s) {
3085       if (first_key < last_key - 5L && reg != noreg) {
3086         {
3087           // printf("found run register %d starting at insn %d low value %d high value %d\n",
3088           //        reg->encoding(),
3089           //        start_insn, first_key, last_key);
3090           //   for (int i = 0; i < inst->length(); i++) {
3091           //     inst->at(i)->print();
3092           //     tty->print("\n");
3093           //   }
3094           //   tty->print("\n");
3095         }
3096 
3097         struct tableswitch *sw = &switches[tableswitch_count];
3098         sw->_insn_index = start_insn, sw->_first_key = first_key,
3099           sw->_last_key = last_key, sw->_reg = reg;
3100         inst->insert_before(last_insn + 1, new LIR_OpLabel(&sw->_after));
3101         {
3102           // Insert the new table of branches
3103           int offset = last_insn;
3104           for (int n = first_key; n < last_key; n++) {
3105             inst->insert_before
3106               (last_insn + 1,
3107                new LIR_OpBranch(lir_cond_always, T_ILLEGAL,
3108                                 inst->at(offset)->as_OpBranch()->label()));
3109             offset -= 2, i++;
3110           }
3111         }
3112         // Delete all the old compare-and-branch instructions
3113         for (int n = first_key; n < last_key; n++) {
3114           inst->remove_at(start_insn);
3115           inst->remove_at(start_insn);
3116         }
3117         // Insert the tableswitch instruction
3118         inst->insert_before(start_insn,
3119                             new LIR_Op2(lir_cmp, lir_cond_always,
3120                                         LIR_OprFact::intConst(tableswitch_count),
3121                                         reg_opr));
3122         inst->insert_before(start_insn + 1, new LIR_OpLabel(&sw->_branches));
3123         tableswitch_count++;
3124       }
3125       reg = noreg;
3126       last_key = -2147483648;
3127     }
3128   next_state:
3129     ;
3130   }
3131 #endif
3132 }
3133 
3134 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp_op) {
3135   Address addr = as_Address(src->as_address_ptr());
3136   BasicType type = src->type();
3137   bool is_oop = is_reference_type(type);
3138 
3139   void (MacroAssembler::* add)(Register prev, RegisterOrConstant incr, Register addr);
3140   void (MacroAssembler::* xchg)(Register prev, Register newv, Register addr);
3141 
3142   switch(type) {
3143   case T_INT:
3144     xchg = &MacroAssembler::atomic_xchgalw;
3145     add = &MacroAssembler::atomic_addalw;
3146     break;
3147   case T_LONG:
3148     xchg = &MacroAssembler::atomic_xchgal;
3149     add = &MacroAssembler::atomic_addal;
3150     break;
3151   case T_OBJECT:
3152   case T_ARRAY:
3153     if (UseCompressedOops) {
3154       xchg = &MacroAssembler::atomic_xchgalw;
3155       add = &MacroAssembler::atomic_addalw;
3156     } else {
3157       xchg = &MacroAssembler::atomic_xchgal;
3158       add = &MacroAssembler::atomic_addal;
3159     }
3160     break;
3161   default:
3162     ShouldNotReachHere();
3163     xchg = &MacroAssembler::atomic_xchgal;
3164     add = &MacroAssembler::atomic_addal; // unreachable
3165   }
3166 
3167   switch (code) {
3168   case lir_xadd:
3169     {
3170       RegisterOrConstant inc;
3171       Register tmp = as_reg(tmp_op);
3172       Register dst = as_reg(dest);
3173       if (data->is_constant()) {
3174         inc = RegisterOrConstant(as_long(data));
3175         assert_different_registers(dst, addr.base(), tmp,
3176                                    rscratch1, rscratch2);
3177       } else {
3178         inc = RegisterOrConstant(as_reg(data));
3179         assert_different_registers(inc.as_register(), dst, addr.base(), tmp,
3180                                    rscratch1, rscratch2);
3181       }
3182       __ lea(tmp, addr);
3183       (_masm->*add)(dst, inc, tmp);
3184       break;
3185     }
3186   case lir_xchg:
3187     {
3188       Register tmp = tmp_op->as_register();
3189       Register obj = as_reg(data);
3190       Register dst = as_reg(dest);
3191       if (is_oop && UseCompressedOops) {
3192         __ encode_heap_oop(rscratch2, obj);
3193         obj = rscratch2;
3194       }
3195       assert_different_registers(obj, addr.base(), tmp, rscratch1, dst);
3196       __ lea(tmp, addr);
3197       (_masm->*xchg)(dst, obj, tmp);
3198       if (is_oop && UseCompressedOops) {
3199         __ decode_heap_oop(dst);
3200       }
3201     }
3202     break;
3203   default:
3204     ShouldNotReachHere();
3205   }
3206   __ membar(__ AnyAny);
3207 }
3208 
3209 #undef __
--- EOF ---