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src/hotspot/cpu/aarch64/c2_MacroAssembler_aarch64.hpp

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160   void sve_compress_byte(FloatRegister dst, FloatRegister src, PRegister mask,
161                          FloatRegister vtmp1, FloatRegister vtmp2,
162                          FloatRegister vtmp3, FloatRegister vtmp4,
163                          PRegister ptmp, PRegister pgtmp);
164 
165   void sve_compress_short(FloatRegister dst, FloatRegister src, PRegister mask,
166                           FloatRegister vtmp1, FloatRegister vtmp2,
167                           PRegister pgtmp);
168 
169   void neon_reverse_bits(FloatRegister dst, FloatRegister src, BasicType bt, bool isQ);
170 
171   void neon_reverse_bytes(FloatRegister dst, FloatRegister src, BasicType bt, bool isQ);
172 
173   // java.lang.Math::signum intrinsics
174   void vector_signum_neon(FloatRegister dst, FloatRegister src, FloatRegister zero,
175                           FloatRegister one, SIMD_Arrangement T);
176 
177   void vector_signum_sve(FloatRegister dst, FloatRegister src, FloatRegister zero,
178                          FloatRegister one, FloatRegister vtmp, PRegister pgtmp, SIMD_RegVariant T);
179 


180 #endif // CPU_AARCH64_C2_MACROASSEMBLER_AARCH64_HPP

160   void sve_compress_byte(FloatRegister dst, FloatRegister src, PRegister mask,
161                          FloatRegister vtmp1, FloatRegister vtmp2,
162                          FloatRegister vtmp3, FloatRegister vtmp4,
163                          PRegister ptmp, PRegister pgtmp);
164 
165   void sve_compress_short(FloatRegister dst, FloatRegister src, PRegister mask,
166                           FloatRegister vtmp1, FloatRegister vtmp2,
167                           PRegister pgtmp);
168 
169   void neon_reverse_bits(FloatRegister dst, FloatRegister src, BasicType bt, bool isQ);
170 
171   void neon_reverse_bytes(FloatRegister dst, FloatRegister src, BasicType bt, bool isQ);
172 
173   // java.lang.Math::signum intrinsics
174   void vector_signum_neon(FloatRegister dst, FloatRegister src, FloatRegister zero,
175                           FloatRegister one, SIMD_Arrangement T);
176 
177   void vector_signum_sve(FloatRegister dst, FloatRegister src, FloatRegister zero,
178                          FloatRegister one, FloatRegister vtmp, PRegister pgtmp, SIMD_RegVariant T);
179 
180   void load_nklass_compact(Register dst, Register obj, Register index, int scale, int disp);
181 
182 #endif // CPU_AARCH64_C2_MACROASSEMBLER_AARCH64_HPP
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