@@ -175,6 +175,8 @@ FloatRegister one, SIMD_Arrangement T); void vector_signum_sve(FloatRegister dst, FloatRegister src, FloatRegister zero, FloatRegister one, FloatRegister vtmp, PRegister pgtmp, SIMD_RegVariant T); + void load_nklass_compact(Register dst, Register obj, Register index, int scale, int disp); + #endif // CPU_AARCH64_C2_MACROASSEMBLER_AARCH64_HPP