1 /*
   2  * Copyright (c) 1997, 2022, Oracle and/or its affiliates. All rights reserved.
   3  * Copyright (c) 2014, 2021, Red Hat Inc. All rights reserved.
   4  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   5  *
   6  * This code is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 only, as
   8  * published by the Free Software Foundation.
   9  *
  10  * This code is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  * version 2 for more details (a copy is included in the LICENSE file that
  14  * accompanied this code).
  15  *
  16  * You should have received a copy of the GNU General Public License version
  17  * 2 along with this work; if not, write to the Free Software Foundation,
  18  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  19  *
  20  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  21  * or visit www.oracle.com if you need additional information or have any
  22  * questions.
  23  *
  24  */
  25 
  26 #ifndef CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
  27 #define CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
  28 
  29 #include "asm/assembler.inline.hpp"
  30 #include "metaprogramming/enableIf.hpp"
  31 #include "oops/compressedOops.hpp"
  32 #include "runtime/vm_version.hpp"
  33 #include "utilities/powerOfTwo.hpp"
  34 
  35 // MacroAssembler extends Assembler by frequently used macros.
  36 //
  37 // Instructions for which a 'better' code sequence exists depending
  38 // on arguments should also go in here.
  39 
  40 class MacroAssembler: public Assembler {
  41   friend class LIR_Assembler;
  42 
  43  public:
  44   using Assembler::mov;
  45   using Assembler::movi;
  46 
  47  protected:
  48 
  49   // Support for VM calls
  50   //
  51   // This is the base routine called by the different versions of call_VM_leaf. The interpreter
  52   // may customize this version by overriding it for its purposes (e.g., to save/restore
  53   // additional registers when doing a VM call).
  54   virtual void call_VM_leaf_base(
  55     address entry_point,               // the entry point
  56     int     number_of_arguments,        // the number of arguments to pop after the call
  57     Label *retaddr = NULL
  58   );
  59 
  60   virtual void call_VM_leaf_base(
  61     address entry_point,               // the entry point
  62     int     number_of_arguments,        // the number of arguments to pop after the call
  63     Label &retaddr) {
  64     call_VM_leaf_base(entry_point, number_of_arguments, &retaddr);
  65   }
  66 
  67   // This is the base routine called by the different versions of call_VM. The interpreter
  68   // may customize this version by overriding it for its purposes (e.g., to save/restore
  69   // additional registers when doing a VM call).
  70   //
  71   // If no java_thread register is specified (noreg) than rthread will be used instead. call_VM_base
  72   // returns the register which contains the thread upon return. If a thread register has been
  73   // specified, the return value will correspond to that register. If no last_java_sp is specified
  74   // (noreg) than rsp will be used instead.
  75   virtual void call_VM_base(           // returns the register containing the thread upon return
  76     Register oop_result,               // where an oop-result ends up if any; use noreg otherwise
  77     Register java_thread,              // the thread if computed before     ; use noreg otherwise
  78     Register last_java_sp,             // to set up last_Java_frame in stubs; use noreg otherwise
  79     address  entry_point,              // the entry point
  80     int      number_of_arguments,      // the number of arguments (w/o thread) to pop after the call
  81     bool     check_exceptions          // whether to check for pending exceptions after return
  82   );
  83 
  84   void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
  85 
  86   enum KlassDecodeMode {
  87     KlassDecodeNone,
  88     KlassDecodeZero,
  89     KlassDecodeXor,
  90     KlassDecodeMovk
  91   };
  92 
  93   KlassDecodeMode klass_decode_mode();
  94 
  95  private:
  96   static KlassDecodeMode _klass_decode_mode;
  97 
  98  public:
  99   MacroAssembler(CodeBuffer* code) : Assembler(code) {}
 100 
 101  // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
 102  // The implementation is only non-empty for the InterpreterMacroAssembler,
 103  // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
 104  virtual void check_and_handle_popframe(Register java_thread);
 105  virtual void check_and_handle_earlyret(Register java_thread);
 106 
 107   void safepoint_poll(Label& slow_path, bool at_return, bool acquire, bool in_nmethod);
 108 
 109   // Helper functions for statistics gathering.
 110   // Unconditional atomic increment.
 111   void atomic_incw(Register counter_addr, Register tmp, Register tmp2);
 112   void atomic_incw(Address counter_addr, Register tmp1, Register tmp2, Register tmp3) {
 113     lea(tmp1, counter_addr);
 114     atomic_incw(tmp1, tmp2, tmp3);
 115   }
 116   // Load Effective Address
 117   void lea(Register r, const Address &a) {
 118     InstructionMark im(this);
 119     code_section()->relocate(inst_mark(), a.rspec());
 120     a.lea(this, r);
 121   }
 122 
 123   /* Sometimes we get misaligned loads and stores, usually from Unsafe
 124      accesses, and these can exceed the offset range. */
 125   Address legitimize_address(const Address &a, int size, Register scratch) {
 126     if (a.getMode() == Address::base_plus_offset) {
 127       if (! Address::offset_ok_for_immed(a.offset(), exact_log2(size))) {
 128         block_comment("legitimize_address {");
 129         lea(scratch, a);
 130         block_comment("} legitimize_address");
 131         return Address(scratch);
 132       }
 133     }
 134     return a;
 135   }
 136 
 137   void addmw(Address a, Register incr, Register scratch) {
 138     ldrw(scratch, a);
 139     addw(scratch, scratch, incr);
 140     strw(scratch, a);
 141   }
 142 
 143   // Add constant to memory word
 144   void addmw(Address a, int imm, Register scratch) {
 145     ldrw(scratch, a);
 146     if (imm > 0)
 147       addw(scratch, scratch, (unsigned)imm);
 148     else
 149       subw(scratch, scratch, (unsigned)-imm);
 150     strw(scratch, a);
 151   }
 152 
 153   void bind(Label& L) {
 154     Assembler::bind(L);
 155     code()->clear_last_insn();
 156   }
 157 
 158   void membar(Membar_mask_bits order_constraint);
 159 
 160   using Assembler::ldr;
 161   using Assembler::str;
 162   using Assembler::ldrw;
 163   using Assembler::strw;
 164 
 165   void ldr(Register Rx, const Address &adr);
 166   void ldrw(Register Rw, const Address &adr);
 167   void str(Register Rx, const Address &adr);
 168   void strw(Register Rx, const Address &adr);
 169 
 170   // Frame creation and destruction shared between JITs.
 171   void build_frame(int framesize);
 172   void remove_frame(int framesize);
 173 
 174   virtual void _call_Unimplemented(address call_site) {
 175     mov(rscratch2, call_site);
 176   }
 177 
 178 // Microsoft's MSVC team thinks that the __FUNCSIG__ is approximately (sympathy for calling conventions) equivalent to __PRETTY_FUNCTION__
 179 // Also, from Clang patch: "It is very similar to GCC's PRETTY_FUNCTION, except it prints the calling convention."
 180 // https://reviews.llvm.org/D3311
 181 
 182 #ifdef _WIN64
 183 #define call_Unimplemented() _call_Unimplemented((address)__FUNCSIG__)
 184 #else
 185 #define call_Unimplemented() _call_Unimplemented((address)__PRETTY_FUNCTION__)
 186 #endif
 187 
 188   // aliases defined in AARCH64 spec
 189 
 190   template<class T>
 191   inline void cmpw(Register Rd, T imm)  { subsw(zr, Rd, imm); }
 192 
 193   inline void cmp(Register Rd, unsigned char imm8)  { subs(zr, Rd, imm8); }
 194   inline void cmp(Register Rd, unsigned imm) = delete;
 195 
 196   inline void cmnw(Register Rd, unsigned imm) { addsw(zr, Rd, imm); }
 197   inline void cmn(Register Rd, unsigned imm) { adds(zr, Rd, imm); }
 198 
 199   void cset(Register Rd, Assembler::Condition cond) {
 200     csinc(Rd, zr, zr, ~cond);
 201   }
 202   void csetw(Register Rd, Assembler::Condition cond) {
 203     csincw(Rd, zr, zr, ~cond);
 204   }
 205 
 206   void cneg(Register Rd, Register Rn, Assembler::Condition cond) {
 207     csneg(Rd, Rn, Rn, ~cond);
 208   }
 209   void cnegw(Register Rd, Register Rn, Assembler::Condition cond) {
 210     csnegw(Rd, Rn, Rn, ~cond);
 211   }
 212 
 213   inline void movw(Register Rd, Register Rn) {
 214     if (Rd == sp || Rn == sp) {
 215       addw(Rd, Rn, 0U);
 216     } else {
 217       orrw(Rd, zr, Rn);
 218     }
 219   }
 220   inline void mov(Register Rd, Register Rn) {
 221     assert(Rd != r31_sp && Rn != r31_sp, "should be");
 222     if (Rd == Rn) {
 223     } else if (Rd == sp || Rn == sp) {
 224       add(Rd, Rn, 0U);
 225     } else {
 226       orr(Rd, zr, Rn);
 227     }
 228   }
 229 
 230   inline void moviw(Register Rd, unsigned imm) { orrw(Rd, zr, imm); }
 231   inline void movi(Register Rd, unsigned imm) { orr(Rd, zr, imm); }
 232 
 233   inline void tstw(Register Rd, Register Rn) { andsw(zr, Rd, Rn); }
 234   inline void tst(Register Rd, Register Rn) { ands(zr, Rd, Rn); }
 235 
 236   inline void tstw(Register Rd, uint64_t imm) { andsw(zr, Rd, imm); }
 237   inline void tst(Register Rd, uint64_t imm) { ands(zr, Rd, imm); }
 238 
 239   inline void bfiw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 240     bfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
 241   }
 242   inline void bfi(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 243     bfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
 244   }
 245 
 246   inline void bfxilw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 247     bfmw(Rd, Rn, lsb, (lsb + width - 1));
 248   }
 249   inline void bfxil(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 250     bfm(Rd, Rn, lsb , (lsb + width - 1));
 251   }
 252 
 253   inline void sbfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 254     sbfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
 255   }
 256   inline void sbfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 257     sbfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
 258   }
 259 
 260   inline void sbfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 261     sbfmw(Rd, Rn, lsb, (lsb + width - 1));
 262   }
 263   inline void sbfx(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 264     sbfm(Rd, Rn, lsb , (lsb + width - 1));
 265   }
 266 
 267   inline void ubfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 268     ubfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
 269   }
 270   inline void ubfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 271     ubfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
 272   }
 273 
 274   inline void ubfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 275     ubfmw(Rd, Rn, lsb, (lsb + width - 1));
 276   }
 277   inline void ubfx(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 278     ubfm(Rd, Rn, lsb , (lsb + width - 1));
 279   }
 280 
 281   inline void asrw(Register Rd, Register Rn, unsigned imm) {
 282     sbfmw(Rd, Rn, imm, 31);
 283   }
 284 
 285   inline void asr(Register Rd, Register Rn, unsigned imm) {
 286     sbfm(Rd, Rn, imm, 63);
 287   }
 288 
 289   inline void lslw(Register Rd, Register Rn, unsigned imm) {
 290     ubfmw(Rd, Rn, ((32 - imm) & 31), (31 - imm));
 291   }
 292 
 293   inline void lsl(Register Rd, Register Rn, unsigned imm) {
 294     ubfm(Rd, Rn, ((64 - imm) & 63), (63 - imm));
 295   }
 296 
 297   inline void lsrw(Register Rd, Register Rn, unsigned imm) {
 298     ubfmw(Rd, Rn, imm, 31);
 299   }
 300 
 301   inline void lsr(Register Rd, Register Rn, unsigned imm) {
 302     ubfm(Rd, Rn, imm, 63);
 303   }
 304 
 305   inline void rorw(Register Rd, Register Rn, unsigned imm) {
 306     extrw(Rd, Rn, Rn, imm);
 307   }
 308 
 309   inline void ror(Register Rd, Register Rn, unsigned imm) {
 310     extr(Rd, Rn, Rn, imm);
 311   }
 312 
 313   inline void sxtbw(Register Rd, Register Rn) {
 314     sbfmw(Rd, Rn, 0, 7);
 315   }
 316   inline void sxthw(Register Rd, Register Rn) {
 317     sbfmw(Rd, Rn, 0, 15);
 318   }
 319   inline void sxtb(Register Rd, Register Rn) {
 320     sbfm(Rd, Rn, 0, 7);
 321   }
 322   inline void sxth(Register Rd, Register Rn) {
 323     sbfm(Rd, Rn, 0, 15);
 324   }
 325   inline void sxtw(Register Rd, Register Rn) {
 326     sbfm(Rd, Rn, 0, 31);
 327   }
 328 
 329   inline void uxtbw(Register Rd, Register Rn) {
 330     ubfmw(Rd, Rn, 0, 7);
 331   }
 332   inline void uxthw(Register Rd, Register Rn) {
 333     ubfmw(Rd, Rn, 0, 15);
 334   }
 335   inline void uxtb(Register Rd, Register Rn) {
 336     ubfm(Rd, Rn, 0, 7);
 337   }
 338   inline void uxth(Register Rd, Register Rn) {
 339     ubfm(Rd, Rn, 0, 15);
 340   }
 341   inline void uxtw(Register Rd, Register Rn) {
 342     ubfm(Rd, Rn, 0, 31);
 343   }
 344 
 345   inline void cmnw(Register Rn, Register Rm) {
 346     addsw(zr, Rn, Rm);
 347   }
 348   inline void cmn(Register Rn, Register Rm) {
 349     adds(zr, Rn, Rm);
 350   }
 351 
 352   inline void cmpw(Register Rn, Register Rm) {
 353     subsw(zr, Rn, Rm);
 354   }
 355   inline void cmp(Register Rn, Register Rm) {
 356     subs(zr, Rn, Rm);
 357   }
 358 
 359   inline void negw(Register Rd, Register Rn) {
 360     subw(Rd, zr, Rn);
 361   }
 362 
 363   inline void neg(Register Rd, Register Rn) {
 364     sub(Rd, zr, Rn);
 365   }
 366 
 367   inline void negsw(Register Rd, Register Rn) {
 368     subsw(Rd, zr, Rn);
 369   }
 370 
 371   inline void negs(Register Rd, Register Rn) {
 372     subs(Rd, zr, Rn);
 373   }
 374 
 375   inline void cmnw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
 376     addsw(zr, Rn, Rm, kind, shift);
 377   }
 378   inline void cmn(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
 379     adds(zr, Rn, Rm, kind, shift);
 380   }
 381 
 382   inline void cmpw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
 383     subsw(zr, Rn, Rm, kind, shift);
 384   }
 385   inline void cmp(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
 386     subs(zr, Rn, Rm, kind, shift);
 387   }
 388 
 389   inline void negw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
 390     subw(Rd, zr, Rn, kind, shift);
 391   }
 392 
 393   inline void neg(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
 394     sub(Rd, zr, Rn, kind, shift);
 395   }
 396 
 397   inline void negsw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
 398     subsw(Rd, zr, Rn, kind, shift);
 399   }
 400 
 401   inline void negs(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
 402     subs(Rd, zr, Rn, kind, shift);
 403   }
 404 
 405   inline void mnegw(Register Rd, Register Rn, Register Rm) {
 406     msubw(Rd, Rn, Rm, zr);
 407   }
 408   inline void mneg(Register Rd, Register Rn, Register Rm) {
 409     msub(Rd, Rn, Rm, zr);
 410   }
 411 
 412   inline void mulw(Register Rd, Register Rn, Register Rm) {
 413     maddw(Rd, Rn, Rm, zr);
 414   }
 415   inline void mul(Register Rd, Register Rn, Register Rm) {
 416     madd(Rd, Rn, Rm, zr);
 417   }
 418 
 419   inline void smnegl(Register Rd, Register Rn, Register Rm) {
 420     smsubl(Rd, Rn, Rm, zr);
 421   }
 422   inline void smull(Register Rd, Register Rn, Register Rm) {
 423     smaddl(Rd, Rn, Rm, zr);
 424   }
 425 
 426   inline void umnegl(Register Rd, Register Rn, Register Rm) {
 427     umsubl(Rd, Rn, Rm, zr);
 428   }
 429   inline void umull(Register Rd, Register Rn, Register Rm) {
 430     umaddl(Rd, Rn, Rm, zr);
 431   }
 432 
 433 #define WRAP(INSN)                                                            \
 434   void INSN(Register Rd, Register Rn, Register Rm, Register Ra) {             \
 435     if (VM_Version::supports_a53mac() && Ra != zr)                            \
 436       nop();                                                                  \
 437     Assembler::INSN(Rd, Rn, Rm, Ra);                                          \
 438   }
 439 
 440   WRAP(madd) WRAP(msub) WRAP(maddw) WRAP(msubw)
 441   WRAP(smaddl) WRAP(smsubl) WRAP(umaddl) WRAP(umsubl)
 442 #undef WRAP
 443 
 444 
 445   // macro assembly operations needed for aarch64
 446 
 447   // first two private routines for loading 32 bit or 64 bit constants
 448 private:
 449 
 450   void mov_immediate64(Register dst, uint64_t imm64);
 451   void mov_immediate32(Register dst, uint32_t imm32);
 452 
 453   int push(unsigned int bitset, Register stack);
 454   int pop(unsigned int bitset, Register stack);
 455 
 456   int push_fp(unsigned int bitset, Register stack);
 457   int pop_fp(unsigned int bitset, Register stack);
 458 
 459   int push_p(unsigned int bitset, Register stack);
 460   int pop_p(unsigned int bitset, Register stack);
 461 
 462   void mov(Register dst, Address a);
 463 
 464 public:
 465   void push(RegSet regs, Register stack) { if (regs.bits()) push(regs.bits(), stack); }
 466   void pop(RegSet regs, Register stack) { if (regs.bits()) pop(regs.bits(), stack); }
 467 
 468   void push_fp(FloatRegSet regs, Register stack) { if (regs.bits()) push_fp(regs.bits(), stack); }
 469   void pop_fp(FloatRegSet regs, Register stack) { if (regs.bits()) pop_fp(regs.bits(), stack); }
 470 
 471   static RegSet call_clobbered_gp_registers();
 472 
 473   void push_p(PRegSet regs, Register stack) { if (regs.bits()) push_p(regs.bits(), stack); }
 474   void pop_p(PRegSet regs, Register stack) { if (regs.bits()) pop_p(regs.bits(), stack); }
 475 
 476   // Push and pop everything that might be clobbered by a native
 477   // runtime call except rscratch1 and rscratch2.  (They are always
 478   // scratch, so we don't have to protect them.)  Only save the lower
 479   // 64 bits of each vector register. Additional registers can be excluded
 480   // in a passed RegSet.
 481   void push_call_clobbered_registers_except(RegSet exclude);
 482   void pop_call_clobbered_registers_except(RegSet exclude);
 483 
 484   void push_call_clobbered_registers() {
 485     push_call_clobbered_registers_except(RegSet());
 486   }
 487   void pop_call_clobbered_registers() {
 488     pop_call_clobbered_registers_except(RegSet());
 489   }
 490 
 491 
 492   // now mov instructions for loading absolute addresses and 32 or
 493   // 64 bit integers
 494 
 495   inline void mov(Register dst, address addr)             { mov_immediate64(dst, (uint64_t)addr); }
 496 
 497   template<typename T, ENABLE_IF(std::is_integral<T>::value)>
 498   inline void mov(Register dst, T o)                      { mov_immediate64(dst, (uint64_t)o); }
 499 
 500   inline void movw(Register dst, uint32_t imm32)          { mov_immediate32(dst, imm32); }
 501 
 502   void mov(Register dst, RegisterOrConstant src) {
 503     if (src.is_register())
 504       mov(dst, src.as_register());
 505     else
 506       mov(dst, src.as_constant());
 507   }
 508 
 509   void movptr(Register r, uintptr_t imm64);
 510 
 511   void mov(FloatRegister Vd, SIMD_Arrangement T, uint64_t imm64);
 512 
 513   void mov(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) {
 514     orr(Vd, T, Vn, Vn);
 515   }
 516 
 517 
 518 public:
 519 
 520   // Generalized Test Bit And Branch, including a "far" variety which
 521   // spans more than 32KiB.
 522   void tbr(Condition cond, Register Rt, int bitpos, Label &dest, bool isfar = false) {
 523     assert(cond == EQ || cond == NE, "must be");
 524 
 525     if (isfar)
 526       cond = ~cond;
 527 
 528     void (Assembler::* branch)(Register Rt, int bitpos, Label &L);
 529     if (cond == Assembler::EQ)
 530       branch = &Assembler::tbz;
 531     else
 532       branch = &Assembler::tbnz;
 533 
 534     if (isfar) {
 535       Label L;
 536       (this->*branch)(Rt, bitpos, L);
 537       b(dest);
 538       bind(L);
 539     } else {
 540       (this->*branch)(Rt, bitpos, dest);
 541     }
 542   }
 543 
 544   // macro instructions for accessing and updating floating point
 545   // status register
 546   //
 547   // FPSR : op1 == 011
 548   //        CRn == 0100
 549   //        CRm == 0100
 550   //        op2 == 001
 551 
 552   inline void get_fpsr(Register reg)
 553   {
 554     mrs(0b11, 0b0100, 0b0100, 0b001, reg);
 555   }
 556 
 557   inline void set_fpsr(Register reg)
 558   {
 559     msr(0b011, 0b0100, 0b0100, 0b001, reg);
 560   }
 561 
 562   inline void clear_fpsr()
 563   {
 564     msr(0b011, 0b0100, 0b0100, 0b001, zr);
 565   }
 566 
 567   // DCZID_EL0: op1 == 011
 568   //            CRn == 0000
 569   //            CRm == 0000
 570   //            op2 == 111
 571   inline void get_dczid_el0(Register reg)
 572   {
 573     mrs(0b011, 0b0000, 0b0000, 0b111, reg);
 574   }
 575 
 576   // CTR_EL0:   op1 == 011
 577   //            CRn == 0000
 578   //            CRm == 0000
 579   //            op2 == 001
 580   inline void get_ctr_el0(Register reg)
 581   {
 582     mrs(0b011, 0b0000, 0b0000, 0b001, reg);
 583   }
 584 
 585   // idiv variant which deals with MINLONG as dividend and -1 as divisor
 586   int corrected_idivl(Register result, Register ra, Register rb,
 587                       bool want_remainder, Register tmp = rscratch1);
 588   int corrected_idivq(Register result, Register ra, Register rb,
 589                       bool want_remainder, Register tmp = rscratch1);
 590 
 591   // Support for NULL-checks
 592   //
 593   // Generates code that causes a NULL OS exception if the content of reg is NULL.
 594   // If the accessed location is M[reg + offset] and the offset is known, provide the
 595   // offset. No explicit code generation is needed if the offset is within a certain
 596   // range (0 <= offset <= page_size).
 597 
 598   virtual void null_check(Register reg, int offset = -1);
 599   static bool needs_explicit_null_check(intptr_t offset);
 600   static bool uses_implicit_null_check(void* address);
 601 
 602   static address target_addr_for_insn(address insn_addr, unsigned insn);
 603   static address target_addr_for_insn_or_null(address insn_addr, unsigned insn);
 604   static address target_addr_for_insn(address insn_addr) {
 605     unsigned insn = *(unsigned*)insn_addr;
 606     return target_addr_for_insn(insn_addr, insn);
 607   }
 608   static address target_addr_for_insn_or_null(address insn_addr) {
 609     unsigned insn = *(unsigned*)insn_addr;
 610     return target_addr_for_insn_or_null(insn_addr, insn);
 611   }
 612 
 613   // Required platform-specific helpers for Label::patch_instructions.
 614   // They _shadow_ the declarations in AbstractAssembler, which are undefined.
 615   static int pd_patch_instruction_size(address branch, address target);
 616   static void pd_patch_instruction(address branch, address target, const char* file = NULL, int line = 0) {
 617     pd_patch_instruction_size(branch, target);
 618   }
 619   static address pd_call_destination(address branch) {
 620     return target_addr_for_insn(branch);
 621   }
 622 #ifndef PRODUCT
 623   static void pd_print_patched_instruction(address branch);
 624 #endif
 625 
 626   static int patch_oop(address insn_addr, address o);
 627   static int patch_narrow_klass(address insn_addr, narrowKlass n);
 628 
 629   address emit_trampoline_stub(int insts_call_instruction_offset, address target);
 630   void emit_static_call_stub();
 631 
 632   // The following 4 methods return the offset of the appropriate move instruction
 633 
 634   // Support for fast byte/short loading with zero extension (depending on particular CPU)
 635   int load_unsigned_byte(Register dst, Address src);
 636   int load_unsigned_short(Register dst, Address src);
 637 
 638   // Support for fast byte/short loading with sign extension (depending on particular CPU)
 639   int load_signed_byte(Register dst, Address src);
 640   int load_signed_short(Register dst, Address src);
 641 
 642   int load_signed_byte32(Register dst, Address src);
 643   int load_signed_short32(Register dst, Address src);
 644 
 645   // Support for sign-extension (hi:lo = extend_sign(lo))
 646   void extend_sign(Register hi, Register lo);
 647 
 648   // Load and store values by size and signed-ness
 649   void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg);
 650   void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg);
 651 
 652   // Support for inc/dec with optimal instruction selection depending on value
 653 
 654   // x86_64 aliases an unqualified register/address increment and
 655   // decrement to call incrementq and decrementq but also supports
 656   // explicitly sized calls to incrementq/decrementq or
 657   // incrementl/decrementl
 658 
 659   // for aarch64 the proper convention would be to use
 660   // increment/decrement for 64 bit operations and
 661   // incrementw/decrementw for 32 bit operations. so when porting
 662   // x86_64 code we can leave calls to increment/decrement as is,
 663   // replace incrementq/decrementq with increment/decrement and
 664   // replace incrementl/decrementl with incrementw/decrementw.
 665 
 666   // n.b. increment/decrement calls with an Address destination will
 667   // need to use a scratch register to load the value to be
 668   // incremented. increment/decrement calls which add or subtract a
 669   // constant value greater than 2^12 will need to use a 2nd scratch
 670   // register to hold the constant. so, a register increment/decrement
 671   // may trash rscratch2 and an address increment/decrement trash
 672   // rscratch and rscratch2
 673 
 674   void decrementw(Address dst, int value = 1);
 675   void decrementw(Register reg, int value = 1);
 676 
 677   void decrement(Register reg, int value = 1);
 678   void decrement(Address dst, int value = 1);
 679 
 680   void incrementw(Address dst, int value = 1);
 681   void incrementw(Register reg, int value = 1);
 682 
 683   void increment(Register reg, int value = 1);
 684   void increment(Address dst, int value = 1);
 685 
 686 
 687   // Alignment
 688   void align(int modulus);
 689 
 690   // Stack frame creation/removal
 691   void enter(bool strip_ret_addr = false);
 692   void leave();
 693 
 694   // ROP Protection
 695   void protect_return_address();
 696   void protect_return_address(Register return_reg, Register temp_reg);
 697   void authenticate_return_address(Register return_reg = lr);
 698   void authenticate_return_address(Register return_reg, Register temp_reg);
 699   void strip_return_address();
 700   void check_return_address(Register return_reg=lr) PRODUCT_RETURN;
 701 
 702   // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
 703   // The pointer will be loaded into the thread register.
 704   void get_thread(Register thread);
 705 
 706 
 707   // Support for VM calls
 708   //
 709   // It is imperative that all calls into the VM are handled via the call_VM macros.
 710   // They make sure that the stack linkage is setup correctly. call_VM's correspond
 711   // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
 712 
 713 
 714   void call_VM(Register oop_result,
 715                address entry_point,
 716                bool check_exceptions = true);
 717   void call_VM(Register oop_result,
 718                address entry_point,
 719                Register arg_1,
 720                bool check_exceptions = true);
 721   void call_VM(Register oop_result,
 722                address entry_point,
 723                Register arg_1, Register arg_2,
 724                bool check_exceptions = true);
 725   void call_VM(Register oop_result,
 726                address entry_point,
 727                Register arg_1, Register arg_2, Register arg_3,
 728                bool check_exceptions = true);
 729 
 730   // Overloadings with last_Java_sp
 731   void call_VM(Register oop_result,
 732                Register last_java_sp,
 733                address entry_point,
 734                int number_of_arguments = 0,
 735                bool check_exceptions = true);
 736   void call_VM(Register oop_result,
 737                Register last_java_sp,
 738                address entry_point,
 739                Register arg_1, bool
 740                check_exceptions = true);
 741   void call_VM(Register oop_result,
 742                Register last_java_sp,
 743                address entry_point,
 744                Register arg_1, Register arg_2,
 745                bool check_exceptions = true);
 746   void call_VM(Register oop_result,
 747                Register last_java_sp,
 748                address entry_point,
 749                Register arg_1, Register arg_2, Register arg_3,
 750                bool check_exceptions = true);
 751 
 752   void get_vm_result  (Register oop_result, Register thread);
 753   void get_vm_result_2(Register metadata_result, Register thread);
 754 
 755   // These always tightly bind to MacroAssembler::call_VM_base
 756   // bypassing the virtual implementation
 757   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
 758   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
 759   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
 760   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
 761   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
 762 
 763   void call_VM_leaf(address entry_point,
 764                     int number_of_arguments = 0);
 765   void call_VM_leaf(address entry_point,
 766                     Register arg_1);
 767   void call_VM_leaf(address entry_point,
 768                     Register arg_1, Register arg_2);
 769   void call_VM_leaf(address entry_point,
 770                     Register arg_1, Register arg_2, Register arg_3);
 771 
 772   // These always tightly bind to MacroAssembler::call_VM_leaf_base
 773   // bypassing the virtual implementation
 774   void super_call_VM_leaf(address entry_point);
 775   void super_call_VM_leaf(address entry_point, Register arg_1);
 776   void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
 777   void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
 778   void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
 779 
 780   // last Java Frame (fills frame anchor)
 781   void set_last_Java_frame(Register last_java_sp,
 782                            Register last_java_fp,
 783                            address last_java_pc,
 784                            Register scratch);
 785 
 786   void set_last_Java_frame(Register last_java_sp,
 787                            Register last_java_fp,
 788                            Label &last_java_pc,
 789                            Register scratch);
 790 
 791   void set_last_Java_frame(Register last_java_sp,
 792                            Register last_java_fp,
 793                            Register last_java_pc,
 794                            Register scratch);
 795 
 796   void reset_last_Java_frame(Register thread);
 797 
 798   // thread in the default location (rthread)
 799   void reset_last_Java_frame(bool clear_fp);
 800 
 801   // Stores
 802   void store_check(Register obj);                // store check for obj - register is destroyed afterwards
 803   void store_check(Register obj, Address dst);   // same as above, dst is exact store location (reg. is destroyed)
 804 
 805   void resolve_jobject(Register value, Register thread, Register tmp);
 806 
 807   // C 'boolean' to Java boolean: x == 0 ? 0 : 1
 808   void c2bool(Register x);
 809 
 810   void load_method_holder_cld(Register rresult, Register rmethod);
 811   void load_method_holder(Register holder, Register method);
 812 
 813   // oop manipulations
 814   void load_klass(Register dst, Register src);
 815   void store_klass(Register dst, Register src);
 816   void cmp_klass(Register oop, Register trial_klass, Register tmp);
 817 
 818   void resolve_weak_handle(Register result, Register tmp);
 819   void resolve_oop_handle(Register result, Register tmp = r5);
 820   void load_mirror(Register dst, Register method, Register tmp = r5);
 821 
 822   void access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
 823                       Register tmp1, Register tmp_thread);
 824 
 825   void access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register src,
 826                        Register tmp1, Register tmp_thread);
 827 
 828   void load_heap_oop(Register dst, Address src, Register tmp1 = noreg,
 829                      Register thread_tmp = noreg, DecoratorSet decorators = 0);
 830 
 831   void load_heap_oop_not_null(Register dst, Address src, Register tmp1 = noreg,
 832                               Register thread_tmp = noreg, DecoratorSet decorators = 0);
 833   void store_heap_oop(Address dst, Register src, Register tmp1 = noreg,
 834                       Register tmp_thread = noreg, DecoratorSet decorators = 0);
 835 
 836   // currently unimplemented
 837   // Used for storing NULL. All other oop constants should be
 838   // stored using routines that take a jobject.
 839   void store_heap_oop_null(Address dst);
 840 
 841   void store_klass_gap(Register dst, Register src);
 842 
 843   // This dummy is to prevent a call to store_heap_oop from
 844   // converting a zero (like NULL) into a Register by giving
 845   // the compiler two choices it can't resolve
 846 
 847   void store_heap_oop(Address dst, void* dummy);
 848 
 849   void encode_heap_oop(Register d, Register s);
 850   void encode_heap_oop(Register r) { encode_heap_oop(r, r); }
 851   void decode_heap_oop(Register d, Register s);
 852   void decode_heap_oop(Register r) { decode_heap_oop(r, r); }
 853   void encode_heap_oop_not_null(Register r);
 854   void decode_heap_oop_not_null(Register r);
 855   void encode_heap_oop_not_null(Register dst, Register src);
 856   void decode_heap_oop_not_null(Register dst, Register src);
 857 
 858   void set_narrow_oop(Register dst, jobject obj);
 859 
 860   void encode_klass_not_null(Register r);
 861   void decode_klass_not_null(Register r);
 862   void encode_klass_not_null(Register dst, Register src);
 863   void decode_klass_not_null(Register dst, Register src);
 864 
 865   void set_narrow_klass(Register dst, Klass* k);
 866 
 867   // if heap base register is used - reinit it with the correct value
 868   void reinit_heapbase();
 869 
 870   DEBUG_ONLY(void verify_heapbase(const char* msg);)
 871 
 872   void push_CPU_state(bool save_vectors = false, bool use_sve = false,
 873                       int sve_vector_size_in_bytes = 0, int total_predicate_in_bytes = 0);
 874   void pop_CPU_state(bool restore_vectors = false, bool use_sve = false,
 875                      int sve_vector_size_in_bytes = 0, int total_predicate_in_bytes = 0);
 876 
 877   // Round up to a power of two
 878   void round_to(Register reg, int modulus);
 879 
 880   // java.lang.Math::round intrinsics
 881   void java_round_double(Register dst, FloatRegister src, FloatRegister ftmp);
 882   void java_round_float(Register dst, FloatRegister src, FloatRegister ftmp);
 883 
 884   // allocation
 885   void eden_allocate(
 886     Register obj,                      // result: pointer to object after successful allocation
 887     Register var_size_in_bytes,        // object size in bytes if unknown at compile time; invalid otherwise
 888     int      con_size_in_bytes,        // object size in bytes if   known at compile time
 889     Register t1,                       // temp register
 890     Label&   slow_case                 // continuation point if fast allocation fails
 891   );
 892   void tlab_allocate(
 893     Register obj,                      // result: pointer to object after successful allocation
 894     Register var_size_in_bytes,        // object size in bytes if unknown at compile time; invalid otherwise
 895     int      con_size_in_bytes,        // object size in bytes if   known at compile time
 896     Register t1,                       // temp register
 897     Register t2,                       // temp register
 898     Label&   slow_case                 // continuation point if fast allocation fails
 899   );
 900   void verify_tlab();
 901 
 902   // interface method calling
 903   void lookup_interface_method(Register recv_klass,
 904                                Register intf_klass,
 905                                RegisterOrConstant itable_index,
 906                                Register method_result,
 907                                Register scan_temp,
 908                                Label& no_such_interface,
 909                    bool return_method = true);
 910 
 911   // virtual method calling
 912   // n.b. x86 allows RegisterOrConstant for vtable_index
 913   void lookup_virtual_method(Register recv_klass,
 914                              RegisterOrConstant vtable_index,
 915                              Register method_result);
 916 
 917   // Test sub_klass against super_klass, with fast and slow paths.
 918 
 919   // The fast path produces a tri-state answer: yes / no / maybe-slow.
 920   // One of the three labels can be NULL, meaning take the fall-through.
 921   // If super_check_offset is -1, the value is loaded up from super_klass.
 922   // No registers are killed, except temp_reg.
 923   void check_klass_subtype_fast_path(Register sub_klass,
 924                                      Register super_klass,
 925                                      Register temp_reg,
 926                                      Label* L_success,
 927                                      Label* L_failure,
 928                                      Label* L_slow_path,
 929                 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
 930 
 931   // The rest of the type check; must be wired to a corresponding fast path.
 932   // It does not repeat the fast path logic, so don't use it standalone.
 933   // The temp_reg and temp2_reg can be noreg, if no temps are available.
 934   // Updates the sub's secondary super cache as necessary.
 935   // If set_cond_codes, condition codes will be Z on success, NZ on failure.
 936   void check_klass_subtype_slow_path(Register sub_klass,
 937                                      Register super_klass,
 938                                      Register temp_reg,
 939                                      Register temp2_reg,
 940                                      Label* L_success,
 941                                      Label* L_failure,
 942                                      bool set_cond_codes = false);
 943 
 944   // Simplified, combined version, good for typical uses.
 945   // Falls through on failure.
 946   void check_klass_subtype(Register sub_klass,
 947                            Register super_klass,
 948                            Register temp_reg,
 949                            Label& L_success);
 950 
 951   void clinit_barrier(Register klass,
 952                       Register thread,
 953                       Label* L_fast_path = NULL,
 954                       Label* L_slow_path = NULL);
 955 
 956   Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
 957 
 958   void verify_sve_vector_length();
 959   void reinitialize_ptrue() {
 960     if (UseSVE > 0) {
 961       sve_ptrue(ptrue, B);
 962     }
 963   }
 964   void verify_ptrue();
 965 
 966   // Debugging
 967 
 968   // only if +VerifyOops
 969   void _verify_oop(Register reg, const char* s, const char* file, int line);
 970   void _verify_oop_addr(Address addr, const char * s, const char* file, int line);
 971 
 972   void _verify_oop_checked(Register reg, const char* s, const char* file, int line) {
 973     if (VerifyOops) {
 974       _verify_oop(reg, s, file, line);
 975     }
 976   }
 977   void _verify_oop_addr_checked(Address reg, const char* s, const char* file, int line) {
 978     if (VerifyOops) {
 979       _verify_oop_addr(reg, s, file, line);
 980     }
 981   }
 982 
 983 // TODO: verify method and klass metadata (compare against vptr?)
 984   void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
 985   void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
 986 
 987 #define verify_oop(reg) _verify_oop_checked(reg, "broken oop " #reg, __FILE__, __LINE__)
 988 #define verify_oop_msg(reg, msg) _verify_oop_checked(reg, "broken oop " #reg ", " #msg, __FILE__, __LINE__)
 989 #define verify_oop_addr(addr) _verify_oop_addr_checked(addr, "broken oop addr " #addr, __FILE__, __LINE__)
 990 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
 991 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
 992 
 993   // only if +VerifyFPU
 994   void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
 995 
 996   // prints msg, dumps registers and stops execution
 997   void stop(const char* msg);
 998 
 999   static void debug64(char* msg, int64_t pc, int64_t regs[]);
1000 
1001   void untested()                                { stop("untested"); }
1002 
1003   void unimplemented(const char* what = "");
1004 
1005   void should_not_reach_here()                   { stop("should not reach here"); }
1006 
1007   // Stack overflow checking
1008   void bang_stack_with_offset(int offset) {
1009     // stack grows down, caller passes positive offset
1010     assert(offset > 0, "must bang with negative offset");
1011     sub(rscratch2, sp, offset);
1012     str(zr, Address(rscratch2));
1013   }
1014 
1015   // Writes to stack successive pages until offset reached to check for
1016   // stack overflow + shadow pages.  Also, clobbers tmp
1017   void bang_stack_size(Register size, Register tmp);
1018 
1019   // Check for reserved stack access in method being exited (for JIT)
1020   void reserved_stack_check();
1021 
1022   // Arithmetics
1023 
1024   void addptr(const Address &dst, int32_t src);
1025   void cmpptr(Register src1, Address src2);
1026 
1027   void cmpoop(Register obj1, Register obj2);
1028 
1029   // Various forms of CAS
1030 
1031   void cmpxchg_obj_header(Register oldv, Register newv, Register obj, Register tmp,
1032                           Label &succeed, Label *fail);
1033   void cmpxchgptr(Register oldv, Register newv, Register addr, Register tmp,
1034                   Label &succeed, Label *fail);
1035 
1036   void cmpxchgw(Register oldv, Register newv, Register addr, Register tmp,
1037                   Label &succeed, Label *fail);
1038 
1039   void atomic_add(Register prev, RegisterOrConstant incr, Register addr);
1040   void atomic_addw(Register prev, RegisterOrConstant incr, Register addr);
1041   void atomic_addal(Register prev, RegisterOrConstant incr, Register addr);
1042   void atomic_addalw(Register prev, RegisterOrConstant incr, Register addr);
1043 
1044   void atomic_xchg(Register prev, Register newv, Register addr);
1045   void atomic_xchgw(Register prev, Register newv, Register addr);
1046   void atomic_xchgl(Register prev, Register newv, Register addr);
1047   void atomic_xchglw(Register prev, Register newv, Register addr);
1048   void atomic_xchgal(Register prev, Register newv, Register addr);
1049   void atomic_xchgalw(Register prev, Register newv, Register addr);
1050 
1051   void orptr(Address adr, RegisterOrConstant src) {
1052     ldr(rscratch1, adr);
1053     if (src.is_register())
1054       orr(rscratch1, rscratch1, src.as_register());
1055     else
1056       orr(rscratch1, rscratch1, src.as_constant());
1057     str(rscratch1, adr);
1058   }
1059 
1060   // A generic CAS; success or failure is in the EQ flag.
1061   // Clobbers rscratch1
1062   void cmpxchg(Register addr, Register expected, Register new_val,
1063                enum operand_size size,
1064                bool acquire, bool release, bool weak,
1065                Register result);
1066 
1067 private:
1068   void compare_eq(Register rn, Register rm, enum operand_size size);
1069 
1070 #ifdef ASSERT
1071   // Template short-hand support to clean-up after a failed call to trampoline
1072   // call generation (see trampoline_call() below),  when a set of Labels must
1073   // be reset (before returning).
1074   template<typename Label, typename... More>
1075   void reset_labels(Label &lbl, More&... more) {
1076     lbl.reset(); reset_labels(more...);
1077   }
1078   template<typename Label>
1079   void reset_labels(Label &lbl) {
1080     lbl.reset();
1081   }
1082 #endif
1083 
1084 public:
1085   // Calls
1086 
1087   address trampoline_call(Address entry, CodeBuffer* cbuf = NULL);
1088 
1089   static bool far_branches() {
1090     return ReservedCodeCacheSize > branch_range;
1091   }
1092 
1093   // Check if branches to the the non nmethod section require a far jump
1094   static bool codestub_branch_needs_far_jump() {
1095     return CodeCache::max_distance_to_non_nmethod() > branch_range;
1096   }
1097 
1098   // Jumps that can reach anywhere in the code cache.
1099   // Trashes tmp.
1100   void far_call(Address entry, CodeBuffer *cbuf = NULL, Register tmp = rscratch1);
1101   int far_jump(Address entry, CodeBuffer *cbuf = NULL, Register tmp = rscratch1);
1102 
1103   static int far_codestub_branch_size() {
1104     if (codestub_branch_needs_far_jump()) {
1105       return 3 * 4;  // adrp, add, br
1106     } else {
1107       return 4;
1108     }
1109   }
1110 
1111   // Emit the CompiledIC call idiom
1112   address ic_call(address entry, jint method_index = 0);
1113 
1114 public:
1115 
1116   // Data
1117 
1118   void mov_metadata(Register dst, Metadata* obj);
1119   Address allocate_metadata_address(Metadata* obj);
1120   Address constant_oop_address(jobject obj);
1121 
1122   void movoop(Register dst, jobject obj, bool immediate = false);
1123 
1124   // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
1125   void kernel_crc32(Register crc, Register buf, Register len,
1126         Register table0, Register table1, Register table2, Register table3,
1127         Register tmp, Register tmp2, Register tmp3);
1128   // CRC32 code for java.util.zip.CRC32C::updateBytes() intrinsic.
1129   void kernel_crc32c(Register crc, Register buf, Register len,
1130         Register table0, Register table1, Register table2, Register table3,
1131         Register tmp, Register tmp2, Register tmp3);
1132 
1133   // Stack push and pop individual 64 bit registers
1134   void push(Register src);
1135   void pop(Register dst);
1136 
1137   void repne_scan(Register addr, Register value, Register count,
1138                   Register scratch);
1139   void repne_scanw(Register addr, Register value, Register count,
1140                    Register scratch);
1141 
1142   typedef void (MacroAssembler::* add_sub_imm_insn)(Register Rd, Register Rn, unsigned imm);
1143   typedef void (MacroAssembler::* add_sub_reg_insn)(Register Rd, Register Rn, Register Rm, enum shift_kind kind, unsigned shift);
1144 
1145   // If a constant does not fit in an immediate field, generate some
1146   // number of MOV instructions and then perform the operation
1147   void wrap_add_sub_imm_insn(Register Rd, Register Rn, unsigned imm,
1148                              add_sub_imm_insn insn1,
1149                              add_sub_reg_insn insn2);
1150   // Separate vsn which sets the flags
1151   void wrap_adds_subs_imm_insn(Register Rd, Register Rn, unsigned imm,
1152                              add_sub_imm_insn insn1,
1153                              add_sub_reg_insn insn2);
1154 
1155 #define WRAP(INSN)                                                      \
1156   void INSN(Register Rd, Register Rn, unsigned imm) {                   \
1157     wrap_add_sub_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN); \
1158   }                                                                     \
1159                                                                         \
1160   void INSN(Register Rd, Register Rn, Register Rm,                      \
1161              enum shift_kind kind, unsigned shift = 0) {                \
1162     Assembler::INSN(Rd, Rn, Rm, kind, shift);                           \
1163   }                                                                     \
1164                                                                         \
1165   void INSN(Register Rd, Register Rn, Register Rm) {                    \
1166     Assembler::INSN(Rd, Rn, Rm);                                        \
1167   }                                                                     \
1168                                                                         \
1169   void INSN(Register Rd, Register Rn, Register Rm,                      \
1170            ext::operation option, int amount = 0) {                     \
1171     Assembler::INSN(Rd, Rn, Rm, option, amount);                        \
1172   }
1173 
1174   WRAP(add) WRAP(addw) WRAP(sub) WRAP(subw)
1175 
1176 #undef WRAP
1177 #define WRAP(INSN)                                                      \
1178   void INSN(Register Rd, Register Rn, unsigned imm) {                   \
1179     wrap_adds_subs_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN); \
1180   }                                                                     \
1181                                                                         \
1182   void INSN(Register Rd, Register Rn, Register Rm,                      \
1183              enum shift_kind kind, unsigned shift = 0) {                \
1184     Assembler::INSN(Rd, Rn, Rm, kind, shift);                           \
1185   }                                                                     \
1186                                                                         \
1187   void INSN(Register Rd, Register Rn, Register Rm) {                    \
1188     Assembler::INSN(Rd, Rn, Rm);                                        \
1189   }                                                                     \
1190                                                                         \
1191   void INSN(Register Rd, Register Rn, Register Rm,                      \
1192            ext::operation option, int amount = 0) {                     \
1193     Assembler::INSN(Rd, Rn, Rm, option, amount);                        \
1194   }
1195 
1196   WRAP(adds) WRAP(addsw) WRAP(subs) WRAP(subsw)
1197 
1198   void add(Register Rd, Register Rn, RegisterOrConstant increment);
1199   void addw(Register Rd, Register Rn, RegisterOrConstant increment);
1200   void sub(Register Rd, Register Rn, RegisterOrConstant decrement);
1201   void subw(Register Rd, Register Rn, RegisterOrConstant decrement);
1202 
1203   void adrp(Register reg1, const Address &dest, uint64_t &byte_offset);
1204 
1205   void tableswitch(Register index, jint lowbound, jint highbound,
1206                    Label &jumptable, Label &jumptable_end, int stride = 1) {
1207     adr(rscratch1, jumptable);
1208     subsw(rscratch2, index, lowbound);
1209     subsw(zr, rscratch2, highbound - lowbound);
1210     br(Assembler::HS, jumptable_end);
1211     add(rscratch1, rscratch1, rscratch2,
1212         ext::sxtw, exact_log2(stride * Assembler::instruction_size));
1213     br(rscratch1);
1214   }
1215 
1216   // Form an address from base + offset in Rd.  Rd may or may not
1217   // actually be used: you must use the Address that is returned.  It
1218   // is up to you to ensure that the shift provided matches the size
1219   // of your data.
1220   Address form_address(Register Rd, Register base, int64_t byte_offset, int shift);
1221 
1222   // Return true iff an address is within the 48-bit AArch64 address
1223   // space.
1224   bool is_valid_AArch64_address(address a) {
1225     return ((uint64_t)a >> 48) == 0;
1226   }
1227 
1228   // Load the base of the cardtable byte map into reg.
1229   void load_byte_map_base(Register reg);
1230 
1231   // Prolog generator routines to support switch between x86 code and
1232   // generated ARM code
1233 
1234   // routine to generate an x86 prolog for a stub function which
1235   // bootstraps into the generated ARM code which directly follows the
1236   // stub
1237   //
1238 
1239   public:
1240 
1241   void ldr_constant(Register dest, const Address &const_addr) {
1242     if (NearCpool) {
1243       ldr(dest, const_addr);
1244     } else {
1245       uint64_t offset;
1246       adrp(dest, InternalAddress(const_addr.target()), offset);
1247       ldr(dest, Address(dest, offset));
1248     }
1249   }
1250 
1251   address read_polling_page(Register r, relocInfo::relocType rtype);
1252   void get_polling_page(Register dest, relocInfo::relocType rtype);
1253 
1254   // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
1255   void update_byte_crc32(Register crc, Register val, Register table);
1256   void update_word_crc32(Register crc, Register v, Register tmp,
1257         Register table0, Register table1, Register table2, Register table3,
1258         bool upper = false);
1259 
1260   address count_positives(Register ary1, Register len, Register result);
1261 
1262   address arrays_equals(Register a1, Register a2, Register result, Register cnt1,
1263                         Register tmp1, Register tmp2, Register tmp3, int elem_size);
1264 
1265   void string_equals(Register a1, Register a2, Register result, Register cnt1,
1266                      int elem_size);
1267 
1268   void fill_words(Register base, Register cnt, Register value);
1269   void zero_words(Register base, uint64_t cnt);
1270   address zero_words(Register ptr, Register cnt);
1271   void zero_dcache_blocks(Register base, Register cnt);
1272 
1273   static const int zero_words_block_size;
1274 
1275   address byte_array_inflate(Register src, Register dst, Register len,
1276                              FloatRegister vtmp1, FloatRegister vtmp2,
1277                              FloatRegister vtmp3, Register tmp4);
1278 
1279   void char_array_compress(Register src, Register dst, Register len,
1280                            Register res,
1281                            FloatRegister vtmp0, FloatRegister vtmp1,
1282                            FloatRegister vtmp2, FloatRegister vtmp3);
1283 
1284   void encode_iso_array(Register src, Register dst,
1285                         Register len, Register res, bool ascii,
1286                         FloatRegister vtmp0, FloatRegister vtmp1,
1287                         FloatRegister vtmp2, FloatRegister vtmp3);
1288 
1289   void fast_log(FloatRegister vtmp0, FloatRegister vtmp1, FloatRegister vtmp2,
1290                 FloatRegister vtmp3, FloatRegister vtmp4, FloatRegister vtmp5,
1291                 FloatRegister tmpC1, FloatRegister tmpC2, FloatRegister tmpC3,
1292                 FloatRegister tmpC4, Register tmp1, Register tmp2,
1293                 Register tmp3, Register tmp4, Register tmp5);
1294   void generate_dsin_dcos(bool isCos, address npio2_hw, address two_over_pi,
1295       address pio2, address dsin_coef, address dcos_coef);
1296  private:
1297   // begin trigonometric functions support block
1298   void generate__ieee754_rem_pio2(address npio2_hw, address two_over_pi, address pio2);
1299   void generate__kernel_rem_pio2(address two_over_pi, address pio2);
1300   void generate_kernel_sin(FloatRegister x, bool iyIsOne, address dsin_coef);
1301   void generate_kernel_cos(FloatRegister x, address dcos_coef);
1302   // end trigonometric functions support block
1303   void add2_with_carry(Register final_dest_hi, Register dest_hi, Register dest_lo,
1304                        Register src1, Register src2);
1305   void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
1306     add2_with_carry(dest_hi, dest_hi, dest_lo, src1, src2);
1307   }
1308   void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
1309                              Register y, Register y_idx, Register z,
1310                              Register carry, Register product,
1311                              Register idx, Register kdx);
1312   void multiply_128_x_128_loop(Register y, Register z,
1313                                Register carry, Register carry2,
1314                                Register idx, Register jdx,
1315                                Register yz_idx1, Register yz_idx2,
1316                                Register tmp, Register tmp3, Register tmp4,
1317                                Register tmp7, Register product_hi);
1318   void kernel_crc32_using_crc32(Register crc, Register buf,
1319         Register len, Register tmp0, Register tmp1, Register tmp2,
1320         Register tmp3);
1321   void kernel_crc32c_using_crc32c(Register crc, Register buf,
1322         Register len, Register tmp0, Register tmp1, Register tmp2,
1323         Register tmp3);
1324 
1325   void ghash_modmul (FloatRegister result,
1326                      FloatRegister result_lo, FloatRegister result_hi, FloatRegister b,
1327                      FloatRegister a, FloatRegister vzr, FloatRegister a1_xor_a0, FloatRegister p,
1328                      FloatRegister t1, FloatRegister t2, FloatRegister t3);
1329   void ghash_load_wide(int index, Register data, FloatRegister result, FloatRegister state);
1330 public:
1331   void multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z,
1332                        Register zlen, Register tmp1, Register tmp2, Register tmp3,
1333                        Register tmp4, Register tmp5, Register tmp6, Register tmp7);
1334   void mul_add(Register out, Register in, Register offs, Register len, Register k);
1335   void ghash_multiply(FloatRegister result_lo, FloatRegister result_hi,
1336                       FloatRegister a, FloatRegister b, FloatRegister a1_xor_a0,
1337                       FloatRegister tmp1, FloatRegister tmp2, FloatRegister tmp3);
1338   void ghash_multiply_wide(int index,
1339                            FloatRegister result_lo, FloatRegister result_hi,
1340                            FloatRegister a, FloatRegister b, FloatRegister a1_xor_a0,
1341                            FloatRegister tmp1, FloatRegister tmp2, FloatRegister tmp3);
1342   void ghash_reduce(FloatRegister result, FloatRegister lo, FloatRegister hi,
1343                     FloatRegister p, FloatRegister z, FloatRegister t1);
1344   void ghash_reduce_wide(int index, FloatRegister result, FloatRegister lo, FloatRegister hi,
1345                     FloatRegister p, FloatRegister z, FloatRegister t1);
1346   void ghash_processBlocks_wide(address p, Register state, Register subkeyH,
1347                                 Register data, Register blocks, int unrolls);
1348 
1349 
1350   void aesenc_loadkeys(Register key, Register keylen);
1351   void aesecb_encrypt(Register from, Register to, Register keylen,
1352                       FloatRegister data = v0, int unrolls = 1);
1353   void aesecb_decrypt(Register from, Register to, Register key, Register keylen);
1354   void aes_round(FloatRegister input, FloatRegister subkey);
1355 
1356   // Place an ISB after code may have been modified due to a safepoint.
1357   void safepoint_isb();
1358 
1359 private:
1360   // Return the effective address r + (r1 << ext) + offset.
1361   // Uses rscratch2.
1362   Address offsetted_address(Register r, Register r1, Address::extend ext,
1363                             int offset, int size);
1364 
1365 private:
1366   // Returns an address on the stack which is reachable with a ldr/str of size
1367   // Uses rscratch2 if the address is not directly reachable
1368   Address spill_address(int size, int offset, Register tmp=rscratch2);
1369   Address sve_spill_address(int sve_reg_size_in_bytes, int offset, Register tmp=rscratch2);
1370 
1371   bool merge_alignment_check(Register base, size_t size, int64_t cur_offset, int64_t prev_offset) const;
1372 
1373   // Check whether two loads/stores can be merged into ldp/stp.
1374   bool ldst_can_merge(Register rx, const Address &adr, size_t cur_size_in_bytes, bool is_store) const;
1375 
1376   // Merge current load/store with previous load/store into ldp/stp.
1377   void merge_ldst(Register rx, const Address &adr, size_t cur_size_in_bytes, bool is_store);
1378 
1379   // Try to merge two loads/stores into ldp/stp. If success, returns true else false.
1380   bool try_merge_ldst(Register rt, const Address &adr, size_t cur_size_in_bytes, bool is_store);
1381 
1382 public:
1383   void spill(Register Rx, bool is64, int offset) {
1384     if (is64) {
1385       str(Rx, spill_address(8, offset));
1386     } else {
1387       strw(Rx, spill_address(4, offset));
1388     }
1389   }
1390   void spill(FloatRegister Vx, SIMD_RegVariant T, int offset) {
1391     str(Vx, T, spill_address(1 << (int)T, offset));
1392   }
1393 
1394   void spill_sve_vector(FloatRegister Zx, int offset, int vector_reg_size_in_bytes) {
1395     sve_str(Zx, sve_spill_address(vector_reg_size_in_bytes, offset));
1396   }
1397   void spill_sve_predicate(PRegister pr, int offset, int predicate_reg_size_in_bytes) {
1398     sve_str(pr, sve_spill_address(predicate_reg_size_in_bytes, offset));
1399   }
1400 
1401   void unspill(Register Rx, bool is64, int offset) {
1402     if (is64) {
1403       ldr(Rx, spill_address(8, offset));
1404     } else {
1405       ldrw(Rx, spill_address(4, offset));
1406     }
1407   }
1408   void unspill(FloatRegister Vx, SIMD_RegVariant T, int offset) {
1409     ldr(Vx, T, spill_address(1 << (int)T, offset));
1410   }
1411 
1412   void unspill_sve_vector(FloatRegister Zx, int offset, int vector_reg_size_in_bytes) {
1413     sve_ldr(Zx, sve_spill_address(vector_reg_size_in_bytes, offset));
1414   }
1415   void unspill_sve_predicate(PRegister pr, int offset, int predicate_reg_size_in_bytes) {
1416     sve_ldr(pr, sve_spill_address(predicate_reg_size_in_bytes, offset));
1417   }
1418 
1419   void spill_copy128(int src_offset, int dst_offset,
1420                      Register tmp1=rscratch1, Register tmp2=rscratch2) {
1421     if (src_offset < 512 && (src_offset & 7) == 0 &&
1422         dst_offset < 512 && (dst_offset & 7) == 0) {
1423       ldp(tmp1, tmp2, Address(sp, src_offset));
1424       stp(tmp1, tmp2, Address(sp, dst_offset));
1425     } else {
1426       unspill(tmp1, true, src_offset);
1427       spill(tmp1, true, dst_offset);
1428       unspill(tmp1, true, src_offset+8);
1429       spill(tmp1, true, dst_offset+8);
1430     }
1431   }
1432   void spill_copy_sve_vector_stack_to_stack(int src_offset, int dst_offset,
1433                                             int sve_vec_reg_size_in_bytes) {
1434     assert(sve_vec_reg_size_in_bytes % 16 == 0, "unexpected sve vector reg size");
1435     for (int i = 0; i < sve_vec_reg_size_in_bytes / 16; i++) {
1436       spill_copy128(src_offset, dst_offset);
1437       src_offset += 16;
1438       dst_offset += 16;
1439     }
1440   }
1441   void spill_copy_sve_predicate_stack_to_stack(int src_offset, int dst_offset,
1442                                                int sve_predicate_reg_size_in_bytes) {
1443     sve_ldr(ptrue, sve_spill_address(sve_predicate_reg_size_in_bytes, src_offset));
1444     sve_str(ptrue, sve_spill_address(sve_predicate_reg_size_in_bytes, dst_offset));
1445     reinitialize_ptrue();
1446   }
1447   void cache_wb(Address line);
1448   void cache_wbsync(bool is_pre);
1449 
1450   // Code for java.lang.Thread::onSpinWait() intrinsic.
1451   void spin_wait();
1452 
1453 private:
1454   // Check the current thread doesn't need a cross modify fence.
1455   void verify_cross_modify_fence_not_required() PRODUCT_RETURN;
1456 
1457 };
1458 
1459 #ifdef ASSERT
1460 inline bool AbstractAssembler::pd_check_instruction_mark() { return false; }
1461 #endif
1462 
1463 /**
1464  * class SkipIfEqual:
1465  *
1466  * Instantiating this class will result in assembly code being output that will
1467  * jump around any code emitted between the creation of the instance and it's
1468  * automatic destruction at the end of a scope block, depending on the value of
1469  * the flag passed to the constructor, which will be checked at run-time.
1470  */
1471 class SkipIfEqual {
1472  private:
1473   MacroAssembler* _masm;
1474   Label _label;
1475 
1476  public:
1477    SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
1478    ~SkipIfEqual();
1479 };
1480 
1481 struct tableswitch {
1482   Register _reg;
1483   int _insn_index; jint _first_key; jint _last_key;
1484   Label _after;
1485   Label _branches;
1486 };
1487 
1488 #endif // CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP