1 /*
   2  * Copyright (c) 1997, 2023, Oracle and/or its affiliates. All rights reserved.
   3  * Copyright (c) 2014, 2021, Red Hat Inc. All rights reserved.
   4  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   5  *
   6  * This code is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 only, as
   8  * published by the Free Software Foundation.
   9  *
  10  * This code is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  * version 2 for more details (a copy is included in the LICENSE file that
  14  * accompanied this code).
  15  *
  16  * You should have received a copy of the GNU General Public License version
  17  * 2 along with this work; if not, write to the Free Software Foundation,
  18  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  19  *
  20  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  21  * or visit www.oracle.com if you need additional information or have any
  22  * questions.
  23  *
  24  */
  25 
  26 #ifndef CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
  27 #define CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
  28 
  29 #include "asm/assembler.inline.hpp"
  30 #include "code/vmreg.hpp"
  31 #include "metaprogramming/enableIf.hpp"
  32 #include "oops/compressedOops.hpp"
  33 #include "runtime/vm_version.hpp"
  34 #include "utilities/powerOfTwo.hpp"
  35 
  36 class OopMap;
  37 
  38 // MacroAssembler extends Assembler by frequently used macros.
  39 //
  40 // Instructions for which a 'better' code sequence exists depending
  41 // on arguments should also go in here.
  42 
  43 class MacroAssembler: public Assembler {
  44   friend class LIR_Assembler;
  45 
  46  public:
  47   using Assembler::mov;
  48   using Assembler::movi;
  49 
  50  protected:
  51 
  52   // Support for VM calls
  53   //
  54   // This is the base routine called by the different versions of call_VM_leaf. The interpreter
  55   // may customize this version by overriding it for its purposes (e.g., to save/restore
  56   // additional registers when doing a VM call).
  57   virtual void call_VM_leaf_base(
  58     address entry_point,               // the entry point
  59     int     number_of_arguments,        // the number of arguments to pop after the call
  60     Label *retaddr = NULL
  61   );
  62 
  63   virtual void call_VM_leaf_base(
  64     address entry_point,               // the entry point
  65     int     number_of_arguments,        // the number of arguments to pop after the call
  66     Label &retaddr) {
  67     call_VM_leaf_base(entry_point, number_of_arguments, &retaddr);
  68   }
  69 
  70   // This is the base routine called by the different versions of call_VM. The interpreter
  71   // may customize this version by overriding it for its purposes (e.g., to save/restore
  72   // additional registers when doing a VM call).
  73   //
  74   // If no java_thread register is specified (noreg) than rthread will be used instead. call_VM_base
  75   // returns the register which contains the thread upon return. If a thread register has been
  76   // specified, the return value will correspond to that register. If no last_java_sp is specified
  77   // (noreg) than rsp will be used instead.
  78   virtual void call_VM_base(           // returns the register containing the thread upon return
  79     Register oop_result,               // where an oop-result ends up if any; use noreg otherwise
  80     Register java_thread,              // the thread if computed before     ; use noreg otherwise
  81     Register last_java_sp,             // to set up last_Java_frame in stubs; use noreg otherwise
  82     address  entry_point,              // the entry point
  83     int      number_of_arguments,      // the number of arguments (w/o thread) to pop after the call
  84     bool     check_exceptions          // whether to check for pending exceptions after return
  85   );
  86 
  87   void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
  88 
  89   enum KlassDecodeMode {
  90     KlassDecodeNone,
  91     KlassDecodeZero,
  92     KlassDecodeXor,
  93     KlassDecodeMovk
  94   };
  95 
  96   KlassDecodeMode klass_decode_mode();
  97 
  98  private:
  99   static KlassDecodeMode _klass_decode_mode;
 100 
 101  public:
 102   MacroAssembler(CodeBuffer* code) : Assembler(code) {}
 103 
 104  // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
 105  // The implementation is only non-empty for the InterpreterMacroAssembler,
 106  // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
 107  virtual void check_and_handle_popframe(Register java_thread);
 108  virtual void check_and_handle_earlyret(Register java_thread);
 109 
 110   void safepoint_poll(Label& slow_path, bool at_return, bool acquire, bool in_nmethod, Register tmp = rscratch1);
 111   void rt_call(address dest, Register tmp = rscratch1);
 112 
 113   // Load Effective Address
 114   void lea(Register r, const Address &a) {
 115     InstructionMark im(this);
 116     a.lea(this, r);
 117   }
 118 
 119   /* Sometimes we get misaligned loads and stores, usually from Unsafe
 120      accesses, and these can exceed the offset range. */
 121   Address legitimize_address(const Address &a, int size, Register scratch) {
 122     if (a.getMode() == Address::base_plus_offset) {
 123       if (! Address::offset_ok_for_immed(a.offset(), exact_log2(size))) {
 124         block_comment("legitimize_address {");
 125         lea(scratch, a);
 126         block_comment("} legitimize_address");
 127         return Address(scratch);
 128       }
 129     }
 130     return a;
 131   }
 132 
 133   void addmw(Address a, Register incr, Register scratch) {
 134     ldrw(scratch, a);
 135     addw(scratch, scratch, incr);
 136     strw(scratch, a);
 137   }
 138 
 139   // Add constant to memory word
 140   void addmw(Address a, int imm, Register scratch) {
 141     ldrw(scratch, a);
 142     if (imm > 0)
 143       addw(scratch, scratch, (unsigned)imm);
 144     else
 145       subw(scratch, scratch, (unsigned)-imm);
 146     strw(scratch, a);
 147   }
 148 
 149   void bind(Label& L) {
 150     Assembler::bind(L);
 151     code()->clear_last_insn();
 152   }
 153 
 154   void membar(Membar_mask_bits order_constraint);
 155 
 156   using Assembler::ldr;
 157   using Assembler::str;
 158   using Assembler::ldrw;
 159   using Assembler::strw;
 160 
 161   void ldr(Register Rx, const Address &adr);
 162   void ldrw(Register Rw, const Address &adr);
 163   void str(Register Rx, const Address &adr);
 164   void strw(Register Rx, const Address &adr);
 165 
 166   // Frame creation and destruction shared between JITs.
 167   void build_frame(int framesize);
 168   void remove_frame(int framesize);
 169 
 170   virtual void _call_Unimplemented(address call_site) {
 171     mov(rscratch2, call_site);
 172   }
 173 
 174 // Microsoft's MSVC team thinks that the __FUNCSIG__ is approximately (sympathy for calling conventions) equivalent to __PRETTY_FUNCTION__
 175 // Also, from Clang patch: "It is very similar to GCC's PRETTY_FUNCTION, except it prints the calling convention."
 176 // https://reviews.llvm.org/D3311
 177 
 178 #ifdef _WIN64
 179 #define call_Unimplemented() _call_Unimplemented((address)__FUNCSIG__)
 180 #else
 181 #define call_Unimplemented() _call_Unimplemented((address)__PRETTY_FUNCTION__)
 182 #endif
 183 
 184   // aliases defined in AARCH64 spec
 185 
 186   template<class T>
 187   inline void cmpw(Register Rd, T imm)  { subsw(zr, Rd, imm); }
 188 
 189   inline void cmp(Register Rd, unsigned char imm8)  { subs(zr, Rd, imm8); }
 190   inline void cmp(Register Rd, unsigned imm) = delete;
 191 
 192   template<class T>
 193   inline void cmnw(Register Rd, T imm) { addsw(zr, Rd, imm); }
 194 
 195   inline void cmn(Register Rd, unsigned char imm8)  { adds(zr, Rd, imm8); }
 196   inline void cmn(Register Rd, unsigned imm) = delete;
 197 
 198   void cset(Register Rd, Assembler::Condition cond) {
 199     csinc(Rd, zr, zr, ~cond);
 200   }
 201   void csetw(Register Rd, Assembler::Condition cond) {
 202     csincw(Rd, zr, zr, ~cond);
 203   }
 204 
 205   void cneg(Register Rd, Register Rn, Assembler::Condition cond) {
 206     csneg(Rd, Rn, Rn, ~cond);
 207   }
 208   void cnegw(Register Rd, Register Rn, Assembler::Condition cond) {
 209     csnegw(Rd, Rn, Rn, ~cond);
 210   }
 211 
 212   inline void movw(Register Rd, Register Rn) {
 213     if (Rd == sp || Rn == sp) {
 214       Assembler::addw(Rd, Rn, 0U);
 215     } else {
 216       orrw(Rd, zr, Rn);
 217     }
 218   }
 219   inline void mov(Register Rd, Register Rn) {
 220     assert(Rd != r31_sp && Rn != r31_sp, "should be");
 221     if (Rd == Rn) {
 222     } else if (Rd == sp || Rn == sp) {
 223       Assembler::add(Rd, Rn, 0U);
 224     } else {
 225       orr(Rd, zr, Rn);
 226     }
 227   }
 228 
 229   inline void moviw(Register Rd, unsigned imm) { orrw(Rd, zr, imm); }
 230   inline void movi(Register Rd, unsigned imm) { orr(Rd, zr, imm); }
 231 
 232   inline void tstw(Register Rd, Register Rn) { andsw(zr, Rd, Rn); }
 233   inline void tst(Register Rd, Register Rn) { ands(zr, Rd, Rn); }
 234 
 235   inline void tstw(Register Rd, uint64_t imm) { andsw(zr, Rd, imm); }
 236   inline void tst(Register Rd, uint64_t imm) { ands(zr, Rd, imm); }
 237 
 238   inline void bfiw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 239     bfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
 240   }
 241   inline void bfi(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 242     bfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
 243   }
 244 
 245   inline void bfxilw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 246     bfmw(Rd, Rn, lsb, (lsb + width - 1));
 247   }
 248   inline void bfxil(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 249     bfm(Rd, Rn, lsb , (lsb + width - 1));
 250   }
 251 
 252   inline void sbfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 253     sbfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
 254   }
 255   inline void sbfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 256     sbfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
 257   }
 258 
 259   inline void sbfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 260     sbfmw(Rd, Rn, lsb, (lsb + width - 1));
 261   }
 262   inline void sbfx(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 263     sbfm(Rd, Rn, lsb , (lsb + width - 1));
 264   }
 265 
 266   inline void ubfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 267     ubfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
 268   }
 269   inline void ubfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 270     ubfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
 271   }
 272 
 273   inline void ubfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 274     ubfmw(Rd, Rn, lsb, (lsb + width - 1));
 275   }
 276   inline void ubfx(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 277     ubfm(Rd, Rn, lsb , (lsb + width - 1));
 278   }
 279 
 280   inline void asrw(Register Rd, Register Rn, unsigned imm) {
 281     sbfmw(Rd, Rn, imm, 31);
 282   }
 283 
 284   inline void asr(Register Rd, Register Rn, unsigned imm) {
 285     sbfm(Rd, Rn, imm, 63);
 286   }
 287 
 288   inline void lslw(Register Rd, Register Rn, unsigned imm) {
 289     ubfmw(Rd, Rn, ((32 - imm) & 31), (31 - imm));
 290   }
 291 
 292   inline void lsl(Register Rd, Register Rn, unsigned imm) {
 293     ubfm(Rd, Rn, ((64 - imm) & 63), (63 - imm));
 294   }
 295 
 296   inline void lsrw(Register Rd, Register Rn, unsigned imm) {
 297     ubfmw(Rd, Rn, imm, 31);
 298   }
 299 
 300   inline void lsr(Register Rd, Register Rn, unsigned imm) {
 301     ubfm(Rd, Rn, imm, 63);
 302   }
 303 
 304   inline void rorw(Register Rd, Register Rn, unsigned imm) {
 305     extrw(Rd, Rn, Rn, imm);
 306   }
 307 
 308   inline void ror(Register Rd, Register Rn, unsigned imm) {
 309     extr(Rd, Rn, Rn, imm);
 310   }
 311 
 312   inline void sxtbw(Register Rd, Register Rn) {
 313     sbfmw(Rd, Rn, 0, 7);
 314   }
 315   inline void sxthw(Register Rd, Register Rn) {
 316     sbfmw(Rd, Rn, 0, 15);
 317   }
 318   inline void sxtb(Register Rd, Register Rn) {
 319     sbfm(Rd, Rn, 0, 7);
 320   }
 321   inline void sxth(Register Rd, Register Rn) {
 322     sbfm(Rd, Rn, 0, 15);
 323   }
 324   inline void sxtw(Register Rd, Register Rn) {
 325     sbfm(Rd, Rn, 0, 31);
 326   }
 327 
 328   inline void uxtbw(Register Rd, Register Rn) {
 329     ubfmw(Rd, Rn, 0, 7);
 330   }
 331   inline void uxthw(Register Rd, Register Rn) {
 332     ubfmw(Rd, Rn, 0, 15);
 333   }
 334   inline void uxtb(Register Rd, Register Rn) {
 335     ubfm(Rd, Rn, 0, 7);
 336   }
 337   inline void uxth(Register Rd, Register Rn) {
 338     ubfm(Rd, Rn, 0, 15);
 339   }
 340   inline void uxtw(Register Rd, Register Rn) {
 341     ubfm(Rd, Rn, 0, 31);
 342   }
 343 
 344   inline void cmnw(Register Rn, Register Rm) {
 345     addsw(zr, Rn, Rm);
 346   }
 347   inline void cmn(Register Rn, Register Rm) {
 348     adds(zr, Rn, Rm);
 349   }
 350 
 351   inline void cmpw(Register Rn, Register Rm) {
 352     subsw(zr, Rn, Rm);
 353   }
 354   inline void cmp(Register Rn, Register Rm) {
 355     subs(zr, Rn, Rm);
 356   }
 357 
 358   inline void negw(Register Rd, Register Rn) {
 359     subw(Rd, zr, Rn);
 360   }
 361 
 362   inline void neg(Register Rd, Register Rn) {
 363     sub(Rd, zr, Rn);
 364   }
 365 
 366   inline void negsw(Register Rd, Register Rn) {
 367     subsw(Rd, zr, Rn);
 368   }
 369 
 370   inline void negs(Register Rd, Register Rn) {
 371     subs(Rd, zr, Rn);
 372   }
 373 
 374   inline void cmnw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
 375     addsw(zr, Rn, Rm, kind, shift);
 376   }
 377   inline void cmn(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
 378     adds(zr, Rn, Rm, kind, shift);
 379   }
 380 
 381   inline void cmpw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
 382     subsw(zr, Rn, Rm, kind, shift);
 383   }
 384   inline void cmp(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
 385     subs(zr, Rn, Rm, kind, shift);
 386   }
 387 
 388   inline void negw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
 389     subw(Rd, zr, Rn, kind, shift);
 390   }
 391 
 392   inline void neg(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
 393     sub(Rd, zr, Rn, kind, shift);
 394   }
 395 
 396   inline void negsw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
 397     subsw(Rd, zr, Rn, kind, shift);
 398   }
 399 
 400   inline void negs(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
 401     subs(Rd, zr, Rn, kind, shift);
 402   }
 403 
 404   inline void mnegw(Register Rd, Register Rn, Register Rm) {
 405     msubw(Rd, Rn, Rm, zr);
 406   }
 407   inline void mneg(Register Rd, Register Rn, Register Rm) {
 408     msub(Rd, Rn, Rm, zr);
 409   }
 410 
 411   inline void mulw(Register Rd, Register Rn, Register Rm) {
 412     maddw(Rd, Rn, Rm, zr);
 413   }
 414   inline void mul(Register Rd, Register Rn, Register Rm) {
 415     madd(Rd, Rn, Rm, zr);
 416   }
 417 
 418   inline void smnegl(Register Rd, Register Rn, Register Rm) {
 419     smsubl(Rd, Rn, Rm, zr);
 420   }
 421   inline void smull(Register Rd, Register Rn, Register Rm) {
 422     smaddl(Rd, Rn, Rm, zr);
 423   }
 424 
 425   inline void umnegl(Register Rd, Register Rn, Register Rm) {
 426     umsubl(Rd, Rn, Rm, zr);
 427   }
 428   inline void umull(Register Rd, Register Rn, Register Rm) {
 429     umaddl(Rd, Rn, Rm, zr);
 430   }
 431 
 432 #define WRAP(INSN)                                                            \
 433   void INSN(Register Rd, Register Rn, Register Rm, Register Ra) {             \
 434     if (VM_Version::supports_a53mac() && Ra != zr)                            \
 435       nop();                                                                  \
 436     Assembler::INSN(Rd, Rn, Rm, Ra);                                          \
 437   }
 438 
 439   WRAP(madd) WRAP(msub) WRAP(maddw) WRAP(msubw)
 440   WRAP(smaddl) WRAP(smsubl) WRAP(umaddl) WRAP(umsubl)
 441 #undef WRAP
 442 
 443 
 444   // macro assembly operations needed for aarch64
 445 
 446   // first two private routines for loading 32 bit or 64 bit constants
 447 private:
 448 
 449   void mov_immediate64(Register dst, uint64_t imm64);
 450   void mov_immediate32(Register dst, uint32_t imm32);
 451 
 452   int push(unsigned int bitset, Register stack);
 453   int pop(unsigned int bitset, Register stack);
 454 
 455   int push_fp(unsigned int bitset, Register stack);
 456   int pop_fp(unsigned int bitset, Register stack);
 457 
 458   int push_p(unsigned int bitset, Register stack);
 459   int pop_p(unsigned int bitset, Register stack);
 460 
 461   void mov(Register dst, Address a);
 462 
 463 public:
 464   void push(RegSet regs, Register stack) { if (regs.bits()) push(regs.bits(), stack); }
 465   void pop(RegSet regs, Register stack) { if (regs.bits()) pop(regs.bits(), stack); }
 466 
 467   void push_fp(FloatRegSet regs, Register stack) { if (regs.bits()) push_fp(regs.bits(), stack); }
 468   void pop_fp(FloatRegSet regs, Register stack) { if (regs.bits()) pop_fp(regs.bits(), stack); }
 469 
 470   static RegSet call_clobbered_gp_registers();
 471 
 472   void push_p(PRegSet regs, Register stack) { if (regs.bits()) push_p(regs.bits(), stack); }
 473   void pop_p(PRegSet regs, Register stack) { if (regs.bits()) pop_p(regs.bits(), stack); }
 474 
 475   // Push and pop everything that might be clobbered by a native
 476   // runtime call except rscratch1 and rscratch2.  (They are always
 477   // scratch, so we don't have to protect them.)  Only save the lower
 478   // 64 bits of each vector register. Additional registers can be excluded
 479   // in a passed RegSet.
 480   void push_call_clobbered_registers_except(RegSet exclude);
 481   void pop_call_clobbered_registers_except(RegSet exclude);
 482 
 483   void push_call_clobbered_registers() {
 484     push_call_clobbered_registers_except(RegSet());
 485   }
 486   void pop_call_clobbered_registers() {
 487     pop_call_clobbered_registers_except(RegSet());
 488   }
 489 
 490 
 491   // now mov instructions for loading absolute addresses and 32 or
 492   // 64 bit integers
 493 
 494   inline void mov(Register dst, address addr)             { mov_immediate64(dst, (uint64_t)addr); }
 495 
 496   template<typename T, ENABLE_IF(std::is_integral<T>::value)>
 497   inline void mov(Register dst, T o)                      { mov_immediate64(dst, (uint64_t)o); }
 498 
 499   inline void movw(Register dst, uint32_t imm32)          { mov_immediate32(dst, imm32); }
 500 
 501   void mov(Register dst, RegisterOrConstant src) {
 502     if (src.is_register())
 503       mov(dst, src.as_register());
 504     else
 505       mov(dst, src.as_constant());
 506   }
 507 
 508   void movptr(Register r, uintptr_t imm64);
 509 
 510   void mov(FloatRegister Vd, SIMD_Arrangement T, uint64_t imm64);
 511 
 512   void mov(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) {
 513     orr(Vd, T, Vn, Vn);
 514   }
 515 
 516 
 517 public:
 518 
 519   // Generalized Test Bit And Branch, including a "far" variety which
 520   // spans more than 32KiB.
 521   void tbr(Condition cond, Register Rt, int bitpos, Label &dest, bool isfar = false) {
 522     assert(cond == EQ || cond == NE, "must be");
 523 
 524     if (isfar)
 525       cond = ~cond;
 526 
 527     void (Assembler::* branch)(Register Rt, int bitpos, Label &L);
 528     if (cond == Assembler::EQ)
 529       branch = &Assembler::tbz;
 530     else
 531       branch = &Assembler::tbnz;
 532 
 533     if (isfar) {
 534       Label L;
 535       (this->*branch)(Rt, bitpos, L);
 536       b(dest);
 537       bind(L);
 538     } else {
 539       (this->*branch)(Rt, bitpos, dest);
 540     }
 541   }
 542 
 543   // macro instructions for accessing and updating floating point
 544   // status register
 545   //
 546   // FPSR : op1 == 011
 547   //        CRn == 0100
 548   //        CRm == 0100
 549   //        op2 == 001
 550 
 551   inline void get_fpsr(Register reg)
 552   {
 553     mrs(0b11, 0b0100, 0b0100, 0b001, reg);
 554   }
 555 
 556   inline void set_fpsr(Register reg)
 557   {
 558     msr(0b011, 0b0100, 0b0100, 0b001, reg);
 559   }
 560 
 561   inline void clear_fpsr()
 562   {
 563     msr(0b011, 0b0100, 0b0100, 0b001, zr);
 564   }
 565 
 566   // DCZID_EL0: op1 == 011
 567   //            CRn == 0000
 568   //            CRm == 0000
 569   //            op2 == 111
 570   inline void get_dczid_el0(Register reg)
 571   {
 572     mrs(0b011, 0b0000, 0b0000, 0b111, reg);
 573   }
 574 
 575   // CTR_EL0:   op1 == 011
 576   //            CRn == 0000
 577   //            CRm == 0000
 578   //            op2 == 001
 579   inline void get_ctr_el0(Register reg)
 580   {
 581     mrs(0b011, 0b0000, 0b0000, 0b001, reg);
 582   }
 583 
 584   inline void get_nzcv(Register reg) {
 585     mrs(0b011, 0b0100, 0b0010, 0b000, reg);
 586   }
 587 
 588   inline void set_nzcv(Register reg) {
 589     msr(0b011, 0b0100, 0b0010, 0b000, reg);
 590   }
 591 
 592   // idiv variant which deals with MINLONG as dividend and -1 as divisor
 593   int corrected_idivl(Register result, Register ra, Register rb,
 594                       bool want_remainder, Register tmp = rscratch1);
 595   int corrected_idivq(Register result, Register ra, Register rb,
 596                       bool want_remainder, Register tmp = rscratch1);
 597 
 598   // Support for NULL-checks
 599   //
 600   // Generates code that causes a NULL OS exception if the content of reg is NULL.
 601   // If the accessed location is M[reg + offset] and the offset is known, provide the
 602   // offset. No explicit code generation is needed if the offset is within a certain
 603   // range (0 <= offset <= page_size).
 604 
 605   virtual void null_check(Register reg, int offset = -1);
 606   static bool needs_explicit_null_check(intptr_t offset);
 607   static bool uses_implicit_null_check(void* address);
 608 
 609   static address target_addr_for_insn(address insn_addr, unsigned insn);
 610   static address target_addr_for_insn_or_null(address insn_addr, unsigned insn);
 611   static address target_addr_for_insn(address insn_addr) {
 612     unsigned insn = *(unsigned*)insn_addr;
 613     return target_addr_for_insn(insn_addr, insn);
 614   }
 615   static address target_addr_for_insn_or_null(address insn_addr) {
 616     unsigned insn = *(unsigned*)insn_addr;
 617     return target_addr_for_insn_or_null(insn_addr, insn);
 618   }
 619 
 620   // Required platform-specific helpers for Label::patch_instructions.
 621   // They _shadow_ the declarations in AbstractAssembler, which are undefined.
 622   static int pd_patch_instruction_size(address branch, address target);
 623   static void pd_patch_instruction(address branch, address target, const char* file = NULL, int line = 0) {
 624     pd_patch_instruction_size(branch, target);
 625   }
 626   static address pd_call_destination(address branch) {
 627     return target_addr_for_insn(branch);
 628   }
 629 #ifndef PRODUCT
 630   static void pd_print_patched_instruction(address branch);
 631 #endif
 632 
 633   static int patch_oop(address insn_addr, address o);
 634   static int patch_narrow_klass(address insn_addr, narrowKlass n);
 635 
 636   // Return whether code is emitted to a scratch blob.
 637   virtual bool in_scratch_emit_size() {
 638     return false;
 639   }
 640   address emit_trampoline_stub(int insts_call_instruction_offset, address target);
 641   static int max_trampoline_stub_size();
 642   void emit_static_call_stub();
 643   static int static_call_stub_size();
 644 
 645   // The following 4 methods return the offset of the appropriate move instruction
 646 
 647   // Support for fast byte/short loading with zero extension (depending on particular CPU)
 648   int load_unsigned_byte(Register dst, Address src);
 649   int load_unsigned_short(Register dst, Address src);
 650 
 651   // Support for fast byte/short loading with sign extension (depending on particular CPU)
 652   int load_signed_byte(Register dst, Address src);
 653   int load_signed_short(Register dst, Address src);
 654 
 655   int load_signed_byte32(Register dst, Address src);
 656   int load_signed_short32(Register dst, Address src);
 657 
 658   // Support for sign-extension (hi:lo = extend_sign(lo))
 659   void extend_sign(Register hi, Register lo);
 660 
 661   // Load and store values by size and signed-ness
 662   void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed);
 663   void store_sized_value(Address dst, Register src, size_t size_in_bytes);
 664 
 665   // Support for inc/dec with optimal instruction selection depending on value
 666 
 667   // x86_64 aliases an unqualified register/address increment and
 668   // decrement to call incrementq and decrementq but also supports
 669   // explicitly sized calls to incrementq/decrementq or
 670   // incrementl/decrementl
 671 
 672   // for aarch64 the proper convention would be to use
 673   // increment/decrement for 64 bit operations and
 674   // incrementw/decrementw for 32 bit operations. so when porting
 675   // x86_64 code we can leave calls to increment/decrement as is,
 676   // replace incrementq/decrementq with increment/decrement and
 677   // replace incrementl/decrementl with incrementw/decrementw.
 678 
 679   // n.b. increment/decrement calls with an Address destination will
 680   // need to use a scratch register to load the value to be
 681   // incremented. increment/decrement calls which add or subtract a
 682   // constant value greater than 2^12 will need to use a 2nd scratch
 683   // register to hold the constant. so, a register increment/decrement
 684   // may trash rscratch2 and an address increment/decrement trash
 685   // rscratch and rscratch2
 686 
 687   void decrementw(Address dst, int value = 1);
 688   void decrementw(Register reg, int value = 1);
 689 
 690   void decrement(Register reg, int value = 1);
 691   void decrement(Address dst, int value = 1);
 692 
 693   void incrementw(Address dst, int value = 1);
 694   void incrementw(Register reg, int value = 1);
 695 
 696   void increment(Register reg, int value = 1);
 697   void increment(Address dst, int value = 1);
 698 
 699 
 700   // Alignment
 701   void align(int modulus);
 702 
 703   // nop
 704   void post_call_nop();
 705 
 706   // Stack frame creation/removal
 707   void enter(bool strip_ret_addr = false);
 708   void leave();
 709 
 710   // ROP Protection
 711   void protect_return_address();
 712   void protect_return_address(Register return_reg, Register temp_reg);
 713   void authenticate_return_address(Register return_reg = lr);
 714   void authenticate_return_address(Register return_reg, Register temp_reg);
 715   void strip_return_address();
 716   void check_return_address(Register return_reg=lr) PRODUCT_RETURN;
 717 
 718   // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
 719   // The pointer will be loaded into the thread register.
 720   void get_thread(Register thread);
 721 
 722   // support for argument shuffling
 723   void move32_64(VMRegPair src, VMRegPair dst, Register tmp = rscratch1);
 724   void float_move(VMRegPair src, VMRegPair dst, Register tmp = rscratch1);
 725   void long_move(VMRegPair src, VMRegPair dst, Register tmp = rscratch1);
 726   void double_move(VMRegPair src, VMRegPair dst, Register tmp = rscratch1);
 727   void object_move(
 728                    OopMap* map,
 729                    int oop_handle_offset,
 730                    int framesize_in_slots,
 731                    VMRegPair src,
 732                    VMRegPair dst,
 733                    bool is_receiver,
 734                    int* receiver_offset);
 735 
 736 
 737   // Support for VM calls
 738   //
 739   // It is imperative that all calls into the VM are handled via the call_VM macros.
 740   // They make sure that the stack linkage is setup correctly. call_VM's correspond
 741   // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
 742 
 743 
 744   void call_VM(Register oop_result,
 745                address entry_point,
 746                bool check_exceptions = true);
 747   void call_VM(Register oop_result,
 748                address entry_point,
 749                Register arg_1,
 750                bool check_exceptions = true);
 751   void call_VM(Register oop_result,
 752                address entry_point,
 753                Register arg_1, Register arg_2,
 754                bool check_exceptions = true);
 755   void call_VM(Register oop_result,
 756                address entry_point,
 757                Register arg_1, Register arg_2, Register arg_3,
 758                bool check_exceptions = true);
 759 
 760   // Overloadings with last_Java_sp
 761   void call_VM(Register oop_result,
 762                Register last_java_sp,
 763                address entry_point,
 764                int number_of_arguments = 0,
 765                bool check_exceptions = true);
 766   void call_VM(Register oop_result,
 767                Register last_java_sp,
 768                address entry_point,
 769                Register arg_1, bool
 770                check_exceptions = true);
 771   void call_VM(Register oop_result,
 772                Register last_java_sp,
 773                address entry_point,
 774                Register arg_1, Register arg_2,
 775                bool check_exceptions = true);
 776   void call_VM(Register oop_result,
 777                Register last_java_sp,
 778                address entry_point,
 779                Register arg_1, Register arg_2, Register arg_3,
 780                bool check_exceptions = true);
 781 
 782   void get_vm_result  (Register oop_result, Register thread);
 783   void get_vm_result_2(Register metadata_result, Register thread);
 784 
 785   // These always tightly bind to MacroAssembler::call_VM_base
 786   // bypassing the virtual implementation
 787   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
 788   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
 789   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
 790   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
 791   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
 792 
 793   void call_VM_leaf(address entry_point,
 794                     int number_of_arguments = 0);
 795   void call_VM_leaf(address entry_point,
 796                     Register arg_1);
 797   void call_VM_leaf(address entry_point,
 798                     Register arg_1, Register arg_2);
 799   void call_VM_leaf(address entry_point,
 800                     Register arg_1, Register arg_2, Register arg_3);
 801 
 802   // These always tightly bind to MacroAssembler::call_VM_leaf_base
 803   // bypassing the virtual implementation
 804   void super_call_VM_leaf(address entry_point);
 805   void super_call_VM_leaf(address entry_point, Register arg_1);
 806   void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
 807   void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
 808   void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
 809 
 810   // last Java Frame (fills frame anchor)
 811   void set_last_Java_frame(Register last_java_sp,
 812                            Register last_java_fp,
 813                            address last_java_pc,
 814                            Register scratch);
 815 
 816   void set_last_Java_frame(Register last_java_sp,
 817                            Register last_java_fp,
 818                            Label &last_java_pc,
 819                            Register scratch);
 820 
 821   void set_last_Java_frame(Register last_java_sp,
 822                            Register last_java_fp,
 823                            Register last_java_pc,
 824                            Register scratch);
 825 
 826   void reset_last_Java_frame(Register thread);
 827 
 828   // thread in the default location (rthread)
 829   void reset_last_Java_frame(bool clear_fp);
 830 
 831   // Stores
 832   void store_check(Register obj);                // store check for obj - register is destroyed afterwards
 833   void store_check(Register obj, Address dst);   // same as above, dst is exact store location (reg. is destroyed)
 834 
 835   void resolve_jobject(Register value, Register tmp1, Register tmp2);
 836   void resolve_global_jobject(Register value, Register tmp1, Register tmp2);
 837 
 838   // C 'boolean' to Java boolean: x == 0 ? 0 : 1
 839   void c2bool(Register x);
 840 
 841   void load_method_holder_cld(Register rresult, Register rmethod);
 842   void load_method_holder(Register holder, Register method);
 843 
 844   // oop manipulations
 845   void load_klass(Register dst, Register src);
 846   void load_klass_check_null(Register dst, Register src);
 847   void store_klass(Register dst, Register src);
 848   void cmp_klass(Register oop, Register trial_klass, Register tmp);
 849 
 850   void resolve_weak_handle(Register result, Register tmp1, Register tmp2);
 851   void resolve_oop_handle(Register result, Register tmp1, Register tmp2);
 852   void load_mirror(Register dst, Register method, Register tmp1, Register tmp2);
 853 
 854   void access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
 855                       Register tmp1, Register tmp2);
 856 
 857   void access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register val,
 858                        Register tmp1, Register tmp2, Register tmp3);
 859 
 860   void load_heap_oop(Register dst, Address src, Register tmp1,
 861                      Register tmp2, DecoratorSet decorators = 0);
 862 
 863   void load_heap_oop_not_null(Register dst, Address src, Register tmp1,
 864                               Register tmp2, DecoratorSet decorators = 0);
 865   void store_heap_oop(Address dst, Register val, Register tmp1,
 866                       Register tmp2, Register tmp3, DecoratorSet decorators = 0);
 867 
 868   // currently unimplemented
 869   // Used for storing NULL. All other oop constants should be
 870   // stored using routines that take a jobject.
 871   void store_heap_oop_null(Address dst);
 872 
 873   void store_klass_gap(Register dst, Register src);
 874 
 875   // This dummy is to prevent a call to store_heap_oop from
 876   // converting a zero (like NULL) into a Register by giving
 877   // the compiler two choices it can't resolve
 878 
 879   void store_heap_oop(Address dst, void* dummy);
 880 
 881   void encode_heap_oop(Register d, Register s);
 882   void encode_heap_oop(Register r) { encode_heap_oop(r, r); }
 883   void decode_heap_oop(Register d, Register s);
 884   void decode_heap_oop(Register r) { decode_heap_oop(r, r); }
 885   void encode_heap_oop_not_null(Register r);
 886   void decode_heap_oop_not_null(Register r);
 887   void encode_heap_oop_not_null(Register dst, Register src);
 888   void decode_heap_oop_not_null(Register dst, Register src);
 889 
 890   void set_narrow_oop(Register dst, jobject obj);
 891 
 892   void encode_klass_not_null(Register r);
 893   void decode_klass_not_null(Register r);
 894   void encode_klass_not_null(Register dst, Register src);
 895   void decode_klass_not_null(Register dst, Register src);
 896 
 897   void set_narrow_klass(Register dst, Klass* k);
 898 
 899   // if heap base register is used - reinit it with the correct value
 900   void reinit_heapbase();
 901 
 902   DEBUG_ONLY(void verify_heapbase(const char* msg);)
 903 
 904   void push_CPU_state(bool save_vectors = false, bool use_sve = false,
 905                       int sve_vector_size_in_bytes = 0, int total_predicate_in_bytes = 0);
 906   void pop_CPU_state(bool restore_vectors = false, bool use_sve = false,
 907                      int sve_vector_size_in_bytes = 0, int total_predicate_in_bytes = 0);
 908 
 909   void push_cont_fastpath(Register java_thread);
 910   void pop_cont_fastpath(Register java_thread);
 911 
 912   // Round up to a power of two
 913   void round_to(Register reg, int modulus);
 914 
 915   // java.lang.Math::round intrinsics
 916   void java_round_double(Register dst, FloatRegister src, FloatRegister ftmp);
 917   void java_round_float(Register dst, FloatRegister src, FloatRegister ftmp);
 918 
 919   // allocation
 920   void tlab_allocate(
 921     Register obj,                      // result: pointer to object after successful allocation
 922     Register var_size_in_bytes,        // object size in bytes if unknown at compile time; invalid otherwise
 923     int      con_size_in_bytes,        // object size in bytes if   known at compile time
 924     Register t1,                       // temp register
 925     Register t2,                       // temp register
 926     Label&   slow_case                 // continuation point if fast allocation fails
 927   );
 928   void verify_tlab();
 929 
 930   // interface method calling
 931   void lookup_interface_method(Register recv_klass,
 932                                Register intf_klass,
 933                                RegisterOrConstant itable_index,
 934                                Register method_result,
 935                                Register scan_temp,
 936                                Label& no_such_interface,
 937                    bool return_method = true);
 938 
 939   // virtual method calling
 940   // n.b. x86 allows RegisterOrConstant for vtable_index
 941   void lookup_virtual_method(Register recv_klass,
 942                              RegisterOrConstant vtable_index,
 943                              Register method_result);
 944 
 945   // Test sub_klass against super_klass, with fast and slow paths.
 946 
 947   // The fast path produces a tri-state answer: yes / no / maybe-slow.
 948   // One of the three labels can be NULL, meaning take the fall-through.
 949   // If super_check_offset is -1, the value is loaded up from super_klass.
 950   // No registers are killed, except temp_reg.
 951   void check_klass_subtype_fast_path(Register sub_klass,
 952                                      Register super_klass,
 953                                      Register temp_reg,
 954                                      Label* L_success,
 955                                      Label* L_failure,
 956                                      Label* L_slow_path,
 957                 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
 958 
 959   // The rest of the type check; must be wired to a corresponding fast path.
 960   // It does not repeat the fast path logic, so don't use it standalone.
 961   // The temp_reg and temp2_reg can be noreg, if no temps are available.
 962   // Updates the sub's secondary super cache as necessary.
 963   // If set_cond_codes, condition codes will be Z on success, NZ on failure.
 964   void check_klass_subtype_slow_path(Register sub_klass,
 965                                      Register super_klass,
 966                                      Register temp_reg,
 967                                      Register temp2_reg,
 968                                      Label* L_success,
 969                                      Label* L_failure,
 970                                      bool set_cond_codes = false);
 971 
 972   // Simplified, combined version, good for typical uses.
 973   // Falls through on failure.
 974   void check_klass_subtype(Register sub_klass,
 975                            Register super_klass,
 976                            Register temp_reg,
 977                            Label& L_success);
 978 
 979   void clinit_barrier(Register klass,
 980                       Register thread,
 981                       Label* L_fast_path = NULL,
 982                       Label* L_slow_path = NULL);
 983 
 984   Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
 985 
 986   void verify_sve_vector_length(Register tmp = rscratch1);
 987   void reinitialize_ptrue() {
 988     if (UseSVE > 0) {
 989       sve_ptrue(ptrue, B);
 990     }
 991   }
 992   void verify_ptrue();
 993 
 994   // Debugging
 995 
 996   // only if +VerifyOops
 997   void _verify_oop(Register reg, const char* s, const char* file, int line);
 998   void _verify_oop_addr(Address addr, const char * s, const char* file, int line);
 999 
1000   void _verify_oop_checked(Register reg, const char* s, const char* file, int line) {
1001     if (VerifyOops) {
1002       _verify_oop(reg, s, file, line);
1003     }
1004   }
1005   void _verify_oop_addr_checked(Address reg, const char* s, const char* file, int line) {
1006     if (VerifyOops) {
1007       _verify_oop_addr(reg, s, file, line);
1008     }
1009   }
1010 
1011 // TODO: verify method and klass metadata (compare against vptr?)
1012   void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
1013   void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
1014 
1015 #define verify_oop(reg) _verify_oop_checked(reg, "broken oop " #reg, __FILE__, __LINE__)
1016 #define verify_oop_msg(reg, msg) _verify_oop_checked(reg, "broken oop " #reg ", " #msg, __FILE__, __LINE__)
1017 #define verify_oop_addr(addr) _verify_oop_addr_checked(addr, "broken oop addr " #addr, __FILE__, __LINE__)
1018 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
1019 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
1020 
1021   // only if +VerifyFPU
1022   void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
1023 
1024   // prints msg, dumps registers and stops execution
1025   void stop(const char* msg);
1026 
1027   static void debug64(char* msg, int64_t pc, int64_t regs[]);
1028 
1029   void untested()                                { stop("untested"); }
1030 
1031   void unimplemented(const char* what = "");
1032 
1033   void should_not_reach_here()                   { stop("should not reach here"); }
1034 
1035   void _assert_asm(Condition cc, const char* msg);
1036 #define assert_asm0(cc, msg) _assert_asm(cc, FILE_AND_LINE ": " msg)
1037 #define assert_asm(masm, command, cc, msg) DEBUG_ONLY(command; (masm)->_assert_asm(cc, FILE_AND_LINE ": " #command " " #cc ": " msg))
1038 
1039   // Stack overflow checking
1040   void bang_stack_with_offset(int offset) {
1041     // stack grows down, caller passes positive offset
1042     assert(offset > 0, "must bang with negative offset");
1043     sub(rscratch2, sp, offset);
1044     str(zr, Address(rscratch2));
1045   }
1046 
1047   // Writes to stack successive pages until offset reached to check for
1048   // stack overflow + shadow pages.  Also, clobbers tmp
1049   void bang_stack_size(Register size, Register tmp);
1050 
1051   // Check for reserved stack access in method being exited (for JIT)
1052   void reserved_stack_check();
1053 
1054   // Arithmetics
1055 
1056   void addptr(const Address &dst, int32_t src);
1057   void cmpptr(Register src1, Address src2);
1058 
1059   void cmpoop(Register obj1, Register obj2);
1060 
1061   // Various forms of CAS
1062 
1063   void cmpxchg_obj_header(Register oldv, Register newv, Register obj, Register tmp,
1064                           Label &succeed, Label *fail);
1065   void cmpxchgptr(Register oldv, Register newv, Register addr, Register tmp,
1066                   Label &succeed, Label *fail);
1067 
1068   void cmpxchgw(Register oldv, Register newv, Register addr, Register tmp,
1069                   Label &succeed, Label *fail);
1070 
1071   void atomic_add(Register prev, RegisterOrConstant incr, Register addr);
1072   void atomic_addw(Register prev, RegisterOrConstant incr, Register addr);
1073   void atomic_addal(Register prev, RegisterOrConstant incr, Register addr);
1074   void atomic_addalw(Register prev, RegisterOrConstant incr, Register addr);
1075 
1076   void atomic_xchg(Register prev, Register newv, Register addr);
1077   void atomic_xchgw(Register prev, Register newv, Register addr);
1078   void atomic_xchgl(Register prev, Register newv, Register addr);
1079   void atomic_xchglw(Register prev, Register newv, Register addr);
1080   void atomic_xchgal(Register prev, Register newv, Register addr);
1081   void atomic_xchgalw(Register prev, Register newv, Register addr);
1082 
1083   void orptr(Address adr, RegisterOrConstant src) {
1084     ldr(rscratch1, adr);
1085     if (src.is_register())
1086       orr(rscratch1, rscratch1, src.as_register());
1087     else
1088       orr(rscratch1, rscratch1, src.as_constant());
1089     str(rscratch1, adr);
1090   }
1091 
1092   // A generic CAS; success or failure is in the EQ flag.
1093   // Clobbers rscratch1
1094   void cmpxchg(Register addr, Register expected, Register new_val,
1095                enum operand_size size,
1096                bool acquire, bool release, bool weak,
1097                Register result);
1098 
1099 #ifdef ASSERT
1100   // Template short-hand support to clean-up after a failed call to trampoline
1101   // call generation (see trampoline_call() below),  when a set of Labels must
1102   // be reset (before returning).
1103   template<typename Label, typename... More>
1104   void reset_labels(Label &lbl, More&... more) {
1105     lbl.reset(); reset_labels(more...);
1106   }
1107   template<typename Label>
1108   void reset_labels(Label &lbl) {
1109     lbl.reset();
1110   }
1111 #endif
1112 
1113 private:
1114   void compare_eq(Register rn, Register rm, enum operand_size size);
1115 
1116 public:
1117   // AArch64 OpenJDK uses four different types of calls:
1118   //   - direct call: bl pc_relative_offset
1119   //     This is the shortest and the fastest, but the offset has the range:
1120   //     +/-128MB for the release build, +/-2MB for the debug build.
1121   //
1122   //   - far call: adrp reg, pc_relative_offset; add; bl reg
1123   //     This is longer than a direct call. The offset has
1124   //     the range +/-4GB. As the code cache size is limited to 4GB,
1125   //     far calls can reach anywhere in the code cache. If a jump is
1126   //     needed rather than a call, a far jump 'b reg' can be used instead.
1127   //     All instructions are embedded at a call site.
1128   //
1129   //   - trampoline call:
1130   //     This is only available in C1/C2-generated code (nmethod). It is a combination
1131   //     of a direct call, which is used if the destination of a call is in range,
1132   //     and a register-indirect call. It has the advantages of reaching anywhere in
1133   //     the AArch64 address space and being patchable at runtime when the generated
1134   //     code is being executed by other threads.
1135   //
1136   //     [Main code section]
1137   //       bl trampoline
1138   //     [Stub code section]
1139   //     trampoline:
1140   //       ldr reg, pc + 8
1141   //       br reg
1142   //       <64-bit destination address>
1143   //
1144   //     If the destination is in range when the generated code is moved to the code
1145   //     cache, 'bl trampoline' is replaced with 'bl destination' and the trampoline
1146   //     is not used.
1147   //     The optimization does not remove the trampoline from the stub section.
1148   //     This is necessary because the trampoline may well be redirected later when
1149   //     code is patched, and the new destination may not be reachable by a simple BR
1150   //     instruction.
1151   //
1152   //   - indirect call: move reg, address; blr reg
1153   //     This too can reach anywhere in the address space, but it cannot be
1154   //     patched while code is running, so it must only be modified at a safepoint.
1155   //     This form of call is most suitable for targets at fixed addresses, which
1156   //     will never be patched.
1157   //
1158   // The patching we do conforms to the "Concurrent modification and
1159   // execution of instructions" section of the Arm Architectural
1160   // Reference Manual, which only allows B, BL, BRK, HVC, ISB, NOP, SMC,
1161   // or SVC instructions to be modified while another thread is
1162   // executing them.
1163   //
1164   // To patch a trampoline call when the BL can't reach, we first modify
1165   // the 64-bit destination address in the trampoline, then modify the
1166   // BL to point to the trampoline, then flush the instruction cache to
1167   // broadcast the change to all executing threads. See
1168   // NativeCall::set_destination_mt_safe for the details.
1169   //
1170   // There is a benign race in that the other thread might observe the
1171   // modified BL before it observes the modified 64-bit destination
1172   // address. That does not matter because the destination method has been
1173   // invalidated, so there will be a trap at its start.
1174   // For this to work, the destination address in the trampoline is
1175   // always updated, even if we're not using the trampoline.
1176 
1177   // Emit a direct call if the entry address will always be in range,
1178   // otherwise a trampoline call.
1179   // Supported entry.rspec():
1180   // - relocInfo::runtime_call_type
1181   // - relocInfo::opt_virtual_call_type
1182   // - relocInfo::static_call_type
1183   // - relocInfo::virtual_call_type
1184   //
1185   // Return: the call PC or NULL if CodeCache is full.
1186   address trampoline_call(Address entry);
1187 
1188   static bool far_branches() {
1189     return ReservedCodeCacheSize > branch_range;
1190   }
1191 
1192   // Check if branches to the non nmethod section require a far jump
1193   static bool codestub_branch_needs_far_jump() {
1194     return CodeCache::max_distance_to_non_nmethod() > branch_range;
1195   }
1196 
1197   // Emit a direct call/jump if the entry address will always be in range,
1198   // otherwise a far call/jump.
1199   // The address must be inside the code cache.
1200   // Supported entry.rspec():
1201   // - relocInfo::external_word_type
1202   // - relocInfo::runtime_call_type
1203   // - relocInfo::none
1204   // In the case of a far call/jump, the entry address is put in the tmp register.
1205   // The tmp register is invalidated.
1206   //
1207   // Far_jump returns the amount of the emitted code.
1208   void far_call(Address entry, Register tmp = rscratch1);
1209   int far_jump(Address entry, Register tmp = rscratch1);
1210 
1211   static int far_codestub_branch_size() {
1212     if (codestub_branch_needs_far_jump()) {
1213       return 3 * 4;  // adrp, add, br
1214     } else {
1215       return 4;
1216     }
1217   }
1218 
1219   // Emit the CompiledIC call idiom
1220   address ic_call(address entry, jint method_index = 0);
1221 
1222 public:
1223 
1224   // Data
1225 
1226   void mov_metadata(Register dst, Metadata* obj);
1227   Address allocate_metadata_address(Metadata* obj);
1228   Address constant_oop_address(jobject obj);
1229 
1230   void movoop(Register dst, jobject obj);
1231 
1232   // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
1233   void kernel_crc32(Register crc, Register buf, Register len,
1234         Register table0, Register table1, Register table2, Register table3,
1235         Register tmp, Register tmp2, Register tmp3);
1236   // CRC32 code for java.util.zip.CRC32C::updateBytes() intrinsic.
1237   void kernel_crc32c(Register crc, Register buf, Register len,
1238         Register table0, Register table1, Register table2, Register table3,
1239         Register tmp, Register tmp2, Register tmp3);
1240 
1241   // Stack push and pop individual 64 bit registers
1242   void push(Register src);
1243   void pop(Register dst);
1244 
1245   void repne_scan(Register addr, Register value, Register count,
1246                   Register scratch);
1247   void repne_scanw(Register addr, Register value, Register count,
1248                    Register scratch);
1249 
1250   typedef void (MacroAssembler::* add_sub_imm_insn)(Register Rd, Register Rn, unsigned imm);
1251   typedef void (MacroAssembler::* add_sub_reg_insn)(Register Rd, Register Rn, Register Rm, enum shift_kind kind, unsigned shift);
1252 
1253   // If a constant does not fit in an immediate field, generate some
1254   // number of MOV instructions and then perform the operation
1255   void wrap_add_sub_imm_insn(Register Rd, Register Rn, uint64_t imm,
1256                              add_sub_imm_insn insn1,
1257                              add_sub_reg_insn insn2, bool is32);
1258   // Separate vsn which sets the flags
1259   void wrap_adds_subs_imm_insn(Register Rd, Register Rn, uint64_t imm,
1260                                add_sub_imm_insn insn1,
1261                                add_sub_reg_insn insn2, bool is32);
1262 
1263 #define WRAP(INSN, is32)                                                \
1264   void INSN(Register Rd, Register Rn, uint64_t imm) {                   \
1265     wrap_add_sub_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN, is32); \
1266   }                                                                     \
1267                                                                         \
1268   void INSN(Register Rd, Register Rn, Register Rm,                      \
1269              enum shift_kind kind, unsigned shift = 0) {                \
1270     Assembler::INSN(Rd, Rn, Rm, kind, shift);                           \
1271   }                                                                     \
1272                                                                         \
1273   void INSN(Register Rd, Register Rn, Register Rm) {                    \
1274     Assembler::INSN(Rd, Rn, Rm);                                        \
1275   }                                                                     \
1276                                                                         \
1277   void INSN(Register Rd, Register Rn, Register Rm,                      \
1278            ext::operation option, int amount = 0) {                     \
1279     Assembler::INSN(Rd, Rn, Rm, option, amount);                        \
1280   }
1281 
1282   WRAP(add, false) WRAP(addw, true) WRAP(sub, false) WRAP(subw, true)
1283 
1284 #undef WRAP
1285 #define WRAP(INSN, is32)                                                \
1286   void INSN(Register Rd, Register Rn, uint64_t imm) {                   \
1287     wrap_adds_subs_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN, is32); \
1288   }                                                                     \
1289                                                                         \
1290   void INSN(Register Rd, Register Rn, Register Rm,                      \
1291              enum shift_kind kind, unsigned shift = 0) {                \
1292     Assembler::INSN(Rd, Rn, Rm, kind, shift);                           \
1293   }                                                                     \
1294                                                                         \
1295   void INSN(Register Rd, Register Rn, Register Rm) {                    \
1296     Assembler::INSN(Rd, Rn, Rm);                                        \
1297   }                                                                     \
1298                                                                         \
1299   void INSN(Register Rd, Register Rn, Register Rm,                      \
1300            ext::operation option, int amount = 0) {                     \
1301     Assembler::INSN(Rd, Rn, Rm, option, amount);                        \
1302   }
1303 
1304   WRAP(adds, false) WRAP(addsw, true) WRAP(subs, false) WRAP(subsw, true)
1305 
1306   void add(Register Rd, Register Rn, RegisterOrConstant increment);
1307   void addw(Register Rd, Register Rn, RegisterOrConstant increment);
1308   void sub(Register Rd, Register Rn, RegisterOrConstant decrement);
1309   void subw(Register Rd, Register Rn, RegisterOrConstant decrement);
1310 
1311   void adrp(Register reg1, const Address &dest, uint64_t &byte_offset);
1312 
1313   void tableswitch(Register index, jint lowbound, jint highbound,
1314                    Label &jumptable, Label &jumptable_end, int stride = 1) {
1315     adr(rscratch1, jumptable);
1316     subsw(rscratch2, index, lowbound);
1317     subsw(zr, rscratch2, highbound - lowbound);
1318     br(Assembler::HS, jumptable_end);
1319     add(rscratch1, rscratch1, rscratch2,
1320         ext::sxtw, exact_log2(stride * Assembler::instruction_size));
1321     br(rscratch1);
1322   }
1323 
1324   // Form an address from base + offset in Rd.  Rd may or may not
1325   // actually be used: you must use the Address that is returned.  It
1326   // is up to you to ensure that the shift provided matches the size
1327   // of your data.
1328   Address form_address(Register Rd, Register base, int64_t byte_offset, int shift);
1329 
1330   // Return true iff an address is within the 48-bit AArch64 address
1331   // space.
1332   bool is_valid_AArch64_address(address a) {
1333     return ((uint64_t)a >> 48) == 0;
1334   }
1335 
1336   // Load the base of the cardtable byte map into reg.
1337   void load_byte_map_base(Register reg);
1338 
1339   // Prolog generator routines to support switch between x86 code and
1340   // generated ARM code
1341 
1342   // routine to generate an x86 prolog for a stub function which
1343   // bootstraps into the generated ARM code which directly follows the
1344   // stub
1345   //
1346 
1347   public:
1348 
1349   void ldr_constant(Register dest, const Address &const_addr) {
1350     if (NearCpool) {
1351       ldr(dest, const_addr);
1352     } else {
1353       uint64_t offset;
1354       adrp(dest, InternalAddress(const_addr.target()), offset);
1355       ldr(dest, Address(dest, offset));
1356     }
1357   }
1358 
1359   address read_polling_page(Register r, relocInfo::relocType rtype);
1360   void get_polling_page(Register dest, relocInfo::relocType rtype);
1361 
1362   // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
1363   void update_byte_crc32(Register crc, Register val, Register table);
1364   void update_word_crc32(Register crc, Register v, Register tmp,
1365         Register table0, Register table1, Register table2, Register table3,
1366         bool upper = false);
1367 
1368   address count_positives(Register ary1, Register len, Register result);
1369 
1370   address arrays_equals(Register a1, Register a2, Register result, Register cnt1,
1371                         Register tmp1, Register tmp2, Register tmp3, int elem_size);
1372 
1373   void string_equals(Register a1, Register a2, Register result, Register cnt1,
1374                      int elem_size);
1375 
1376   void fill_words(Register base, Register cnt, Register value);
1377   address zero_words(Register base, uint64_t cnt);
1378   address zero_words(Register ptr, Register cnt);
1379   void zero_dcache_blocks(Register base, Register cnt);
1380 
1381   static const int zero_words_block_size;
1382 
1383   address byte_array_inflate(Register src, Register dst, Register len,
1384                              FloatRegister vtmp1, FloatRegister vtmp2,
1385                              FloatRegister vtmp3, Register tmp4);
1386 
1387   void char_array_compress(Register src, Register dst, Register len,
1388                            Register res,
1389                            FloatRegister vtmp0, FloatRegister vtmp1,
1390                            FloatRegister vtmp2, FloatRegister vtmp3);
1391 
1392   void encode_iso_array(Register src, Register dst,
1393                         Register len, Register res, bool ascii,
1394                         FloatRegister vtmp0, FloatRegister vtmp1,
1395                         FloatRegister vtmp2, FloatRegister vtmp3);
1396 
1397   void fast_log(FloatRegister vtmp0, FloatRegister vtmp1, FloatRegister vtmp2,
1398                 FloatRegister vtmp3, FloatRegister vtmp4, FloatRegister vtmp5,
1399                 FloatRegister tmpC1, FloatRegister tmpC2, FloatRegister tmpC3,
1400                 FloatRegister tmpC4, Register tmp1, Register tmp2,
1401                 Register tmp3, Register tmp4, Register tmp5);
1402   void generate_dsin_dcos(bool isCos, address npio2_hw, address two_over_pi,
1403       address pio2, address dsin_coef, address dcos_coef);
1404  private:
1405   // begin trigonometric functions support block
1406   void generate__ieee754_rem_pio2(address npio2_hw, address two_over_pi, address pio2);
1407   void generate__kernel_rem_pio2(address two_over_pi, address pio2);
1408   void generate_kernel_sin(FloatRegister x, bool iyIsOne, address dsin_coef);
1409   void generate_kernel_cos(FloatRegister x, address dcos_coef);
1410   // end trigonometric functions support block
1411   void add2_with_carry(Register final_dest_hi, Register dest_hi, Register dest_lo,
1412                        Register src1, Register src2);
1413   void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
1414     add2_with_carry(dest_hi, dest_hi, dest_lo, src1, src2);
1415   }
1416   void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
1417                              Register y, Register y_idx, Register z,
1418                              Register carry, Register product,
1419                              Register idx, Register kdx);
1420   void multiply_128_x_128_loop(Register y, Register z,
1421                                Register carry, Register carry2,
1422                                Register idx, Register jdx,
1423                                Register yz_idx1, Register yz_idx2,
1424                                Register tmp, Register tmp3, Register tmp4,
1425                                Register tmp7, Register product_hi);
1426   void kernel_crc32_using_crypto_pmull(Register crc, Register buf,
1427         Register len, Register tmp0, Register tmp1, Register tmp2,
1428         Register tmp3);
1429   void kernel_crc32_using_crc32(Register crc, Register buf,
1430         Register len, Register tmp0, Register tmp1, Register tmp2,
1431         Register tmp3);
1432   void kernel_crc32c_using_crc32c(Register crc, Register buf,
1433         Register len, Register tmp0, Register tmp1, Register tmp2,
1434         Register tmp3);
1435   void kernel_crc32_common_fold_using_crypto_pmull(Register crc, Register buf,
1436         Register len, Register tmp0, Register tmp1, Register tmp2,
1437         size_t table_offset);
1438 
1439   void ghash_modmul (FloatRegister result,
1440                      FloatRegister result_lo, FloatRegister result_hi, FloatRegister b,
1441                      FloatRegister a, FloatRegister vzr, FloatRegister a1_xor_a0, FloatRegister p,
1442                      FloatRegister t1, FloatRegister t2, FloatRegister t3);
1443   void ghash_load_wide(int index, Register data, FloatRegister result, FloatRegister state);
1444 public:
1445   void multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z,
1446                        Register zlen, Register tmp1, Register tmp2, Register tmp3,
1447                        Register tmp4, Register tmp5, Register tmp6, Register tmp7);
1448   void mul_add(Register out, Register in, Register offs, Register len, Register k);
1449   void ghash_multiply(FloatRegister result_lo, FloatRegister result_hi,
1450                       FloatRegister a, FloatRegister b, FloatRegister a1_xor_a0,
1451                       FloatRegister tmp1, FloatRegister tmp2, FloatRegister tmp3);
1452   void ghash_multiply_wide(int index,
1453                            FloatRegister result_lo, FloatRegister result_hi,
1454                            FloatRegister a, FloatRegister b, FloatRegister a1_xor_a0,
1455                            FloatRegister tmp1, FloatRegister tmp2, FloatRegister tmp3);
1456   void ghash_reduce(FloatRegister result, FloatRegister lo, FloatRegister hi,
1457                     FloatRegister p, FloatRegister z, FloatRegister t1);
1458   void ghash_reduce_wide(int index, FloatRegister result, FloatRegister lo, FloatRegister hi,
1459                     FloatRegister p, FloatRegister z, FloatRegister t1);
1460   void ghash_processBlocks_wide(address p, Register state, Register subkeyH,
1461                                 Register data, Register blocks, int unrolls);
1462 
1463 
1464   void aesenc_loadkeys(Register key, Register keylen);
1465   void aesecb_encrypt(Register from, Register to, Register keylen,
1466                       FloatRegister data = v0, int unrolls = 1);
1467   void aesecb_decrypt(Register from, Register to, Register key, Register keylen);
1468   void aes_round(FloatRegister input, FloatRegister subkey);
1469 
1470   // ChaCha20 functions support block
1471   void cc20_quarter_round(FloatRegister aVec, FloatRegister bVec,
1472           FloatRegister cVec, FloatRegister dVec, FloatRegister scratch,
1473           FloatRegister tbl);
1474   void cc20_shift_lane_org(FloatRegister bVec, FloatRegister cVec,
1475           FloatRegister dVec, bool colToDiag);
1476 
1477   // Place an ISB after code may have been modified due to a safepoint.
1478   void safepoint_isb();
1479 
1480 private:
1481   // Return the effective address r + (r1 << ext) + offset.
1482   // Uses rscratch2.
1483   Address offsetted_address(Register r, Register r1, Address::extend ext,
1484                             int offset, int size);
1485 
1486 private:
1487   // Returns an address on the stack which is reachable with a ldr/str of size
1488   // Uses rscratch2 if the address is not directly reachable
1489   Address spill_address(int size, int offset, Register tmp=rscratch2);
1490   Address sve_spill_address(int sve_reg_size_in_bytes, int offset, Register tmp=rscratch2);
1491 
1492   bool merge_alignment_check(Register base, size_t size, int64_t cur_offset, int64_t prev_offset) const;
1493 
1494   // Check whether two loads/stores can be merged into ldp/stp.
1495   bool ldst_can_merge(Register rx, const Address &adr, size_t cur_size_in_bytes, bool is_store) const;
1496 
1497   // Merge current load/store with previous load/store into ldp/stp.
1498   void merge_ldst(Register rx, const Address &adr, size_t cur_size_in_bytes, bool is_store);
1499 
1500   // Try to merge two loads/stores into ldp/stp. If success, returns true else false.
1501   bool try_merge_ldst(Register rt, const Address &adr, size_t cur_size_in_bytes, bool is_store);
1502 
1503 public:
1504   void spill(Register Rx, bool is64, int offset) {
1505     if (is64) {
1506       str(Rx, spill_address(8, offset));
1507     } else {
1508       strw(Rx, spill_address(4, offset));
1509     }
1510   }
1511   void spill(FloatRegister Vx, SIMD_RegVariant T, int offset) {
1512     str(Vx, T, spill_address(1 << (int)T, offset));
1513   }
1514 
1515   void spill_sve_vector(FloatRegister Zx, int offset, int vector_reg_size_in_bytes) {
1516     sve_str(Zx, sve_spill_address(vector_reg_size_in_bytes, offset));
1517   }
1518   void spill_sve_predicate(PRegister pr, int offset, int predicate_reg_size_in_bytes) {
1519     sve_str(pr, sve_spill_address(predicate_reg_size_in_bytes, offset));
1520   }
1521 
1522   void unspill(Register Rx, bool is64, int offset) {
1523     if (is64) {
1524       ldr(Rx, spill_address(8, offset));
1525     } else {
1526       ldrw(Rx, spill_address(4, offset));
1527     }
1528   }
1529   void unspill(FloatRegister Vx, SIMD_RegVariant T, int offset) {
1530     ldr(Vx, T, spill_address(1 << (int)T, offset));
1531   }
1532 
1533   void unspill_sve_vector(FloatRegister Zx, int offset, int vector_reg_size_in_bytes) {
1534     sve_ldr(Zx, sve_spill_address(vector_reg_size_in_bytes, offset));
1535   }
1536   void unspill_sve_predicate(PRegister pr, int offset, int predicate_reg_size_in_bytes) {
1537     sve_ldr(pr, sve_spill_address(predicate_reg_size_in_bytes, offset));
1538   }
1539 
1540   void spill_copy128(int src_offset, int dst_offset,
1541                      Register tmp1=rscratch1, Register tmp2=rscratch2) {
1542     if (src_offset < 512 && (src_offset & 7) == 0 &&
1543         dst_offset < 512 && (dst_offset & 7) == 0) {
1544       ldp(tmp1, tmp2, Address(sp, src_offset));
1545       stp(tmp1, tmp2, Address(sp, dst_offset));
1546     } else {
1547       unspill(tmp1, true, src_offset);
1548       spill(tmp1, true, dst_offset);
1549       unspill(tmp1, true, src_offset+8);
1550       spill(tmp1, true, dst_offset+8);
1551     }
1552   }
1553   void spill_copy_sve_vector_stack_to_stack(int src_offset, int dst_offset,
1554                                             int sve_vec_reg_size_in_bytes) {
1555     assert(sve_vec_reg_size_in_bytes % 16 == 0, "unexpected sve vector reg size");
1556     for (int i = 0; i < sve_vec_reg_size_in_bytes / 16; i++) {
1557       spill_copy128(src_offset, dst_offset);
1558       src_offset += 16;
1559       dst_offset += 16;
1560     }
1561   }
1562   void spill_copy_sve_predicate_stack_to_stack(int src_offset, int dst_offset,
1563                                                int sve_predicate_reg_size_in_bytes) {
1564     sve_ldr(ptrue, sve_spill_address(sve_predicate_reg_size_in_bytes, src_offset));
1565     sve_str(ptrue, sve_spill_address(sve_predicate_reg_size_in_bytes, dst_offset));
1566     reinitialize_ptrue();
1567   }
1568   void cache_wb(Address line);
1569   void cache_wbsync(bool is_pre);
1570 
1571   // Code for java.lang.Thread::onSpinWait() intrinsic.
1572   void spin_wait();
1573 
1574 private:
1575   // Check the current thread doesn't need a cross modify fence.
1576   void verify_cross_modify_fence_not_required() PRODUCT_RETURN;
1577 
1578 };
1579 
1580 #ifdef ASSERT
1581 inline bool AbstractAssembler::pd_check_instruction_mark() { return false; }
1582 #endif
1583 
1584 /**
1585  * class SkipIfEqual:
1586  *
1587  * Instantiating this class will result in assembly code being output that will
1588  * jump around any code emitted between the creation of the instance and it's
1589  * automatic destruction at the end of a scope block, depending on the value of
1590  * the flag passed to the constructor, which will be checked at run-time.
1591  */
1592 class SkipIfEqual {
1593  private:
1594   MacroAssembler* _masm;
1595   Label _label;
1596 
1597  public:
1598    SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
1599    ~SkipIfEqual();
1600 };
1601 
1602 struct tableswitch {
1603   Register _reg;
1604   int _insn_index; jint _first_key; jint _last_key;
1605   Label _after;
1606   Label _branches;
1607 };
1608 
1609 #endif // CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP