1 /*
   2  * Copyright (c) 1997, 2022, Oracle and/or its affiliates. All rights reserved.
   3  * Copyright (c) 2014, 2021, Red Hat Inc. All rights reserved.
   4  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   5  *
   6  * This code is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 only, as
   8  * published by the Free Software Foundation.
   9  *
  10  * This code is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  * version 2 for more details (a copy is included in the LICENSE file that
  14  * accompanied this code).
  15  *
  16  * You should have received a copy of the GNU General Public License version
  17  * 2 along with this work; if not, write to the Free Software Foundation,
  18  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  19  *
  20  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  21  * or visit www.oracle.com if you need additional information or have any
  22  * questions.
  23  *
  24  */
  25 
  26 #ifndef CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
  27 #define CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
  28 
  29 #include "asm/assembler.inline.hpp"
  30 #include "code/vmreg.hpp"
  31 #include "metaprogramming/enableIf.hpp"
  32 #include "oops/compressedOops.hpp"
  33 #include "runtime/vm_version.hpp"
  34 #include "utilities/powerOfTwo.hpp"
  35 
  36 class OopMap;
  37 
  38 // MacroAssembler extends Assembler by frequently used macros.
  39 //
  40 // Instructions for which a 'better' code sequence exists depending
  41 // on arguments should also go in here.
  42 
  43 class MacroAssembler: public Assembler {
  44   friend class LIR_Assembler;
  45 
  46  public:
  47   using Assembler::mov;
  48   using Assembler::movi;
  49 
  50  protected:
  51 
  52   // Support for VM calls
  53   //
  54   // This is the base routine called by the different versions of call_VM_leaf. The interpreter
  55   // may customize this version by overriding it for its purposes (e.g., to save/restore
  56   // additional registers when doing a VM call).
  57   virtual void call_VM_leaf_base(
  58     address entry_point,               // the entry point
  59     int     number_of_arguments,        // the number of arguments to pop after the call
  60     Label *retaddr = NULL
  61   );
  62 
  63   virtual void call_VM_leaf_base(
  64     address entry_point,               // the entry point
  65     int     number_of_arguments,        // the number of arguments to pop after the call
  66     Label &retaddr) {
  67     call_VM_leaf_base(entry_point, number_of_arguments, &retaddr);
  68   }
  69 
  70   // This is the base routine called by the different versions of call_VM. The interpreter
  71   // may customize this version by overriding it for its purposes (e.g., to save/restore
  72   // additional registers when doing a VM call).
  73   //
  74   // If no java_thread register is specified (noreg) than rthread will be used instead. call_VM_base
  75   // returns the register which contains the thread upon return. If a thread register has been
  76   // specified, the return value will correspond to that register. If no last_java_sp is specified
  77   // (noreg) than rsp will be used instead.
  78   virtual void call_VM_base(           // returns the register containing the thread upon return
  79     Register oop_result,               // where an oop-result ends up if any; use noreg otherwise
  80     Register java_thread,              // the thread if computed before     ; use noreg otherwise
  81     Register last_java_sp,             // to set up last_Java_frame in stubs; use noreg otherwise
  82     address  entry_point,              // the entry point
  83     int      number_of_arguments,      // the number of arguments (w/o thread) to pop after the call
  84     bool     check_exceptions          // whether to check for pending exceptions after return
  85   );
  86 
  87   void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
  88 
  89   enum KlassDecodeMode {
  90     KlassDecodeNone,
  91     KlassDecodeZero,
  92     KlassDecodeXor,
  93     KlassDecodeMovk
  94   };
  95 
  96   KlassDecodeMode klass_decode_mode();
  97 
  98  private:
  99   static KlassDecodeMode _klass_decode_mode;
 100 
 101  public:
 102   MacroAssembler(CodeBuffer* code) : Assembler(code) {}
 103 
 104  // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
 105  // The implementation is only non-empty for the InterpreterMacroAssembler,
 106  // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
 107  virtual void check_and_handle_popframe(Register java_thread);
 108  virtual void check_and_handle_earlyret(Register java_thread);
 109 
 110   void safepoint_poll(Label& slow_path, bool at_return, bool acquire, bool in_nmethod, Register tmp = rscratch1);
 111   void rt_call(address dest, Register tmp = rscratch1);
 112 
 113   // Helper functions for statistics gathering.
 114   // Unconditional atomic increment.
 115   void atomic_incw(Register counter_addr, Register tmp, Register tmp2);
 116   void atomic_incw(Address counter_addr, Register tmp1, Register tmp2, Register tmp3) {
 117     lea(tmp1, counter_addr);
 118     atomic_incw(tmp1, tmp2, tmp3);
 119   }
 120   // Load Effective Address
 121   void lea(Register r, const Address &a) {
 122     InstructionMark im(this);
 123     code_section()->relocate(inst_mark(), a.rspec());
 124     a.lea(this, r);
 125   }
 126 
 127   /* Sometimes we get misaligned loads and stores, usually from Unsafe
 128      accesses, and these can exceed the offset range. */
 129   Address legitimize_address(const Address &a, int size, Register scratch) {
 130     if (a.getMode() == Address::base_plus_offset) {
 131       if (! Address::offset_ok_for_immed(a.offset(), exact_log2(size))) {
 132         block_comment("legitimize_address {");
 133         lea(scratch, a);
 134         block_comment("} legitimize_address");
 135         return Address(scratch);
 136       }
 137     }
 138     return a;
 139   }
 140 
 141   void addmw(Address a, Register incr, Register scratch) {
 142     ldrw(scratch, a);
 143     addw(scratch, scratch, incr);
 144     strw(scratch, a);
 145   }
 146 
 147   // Add constant to memory word
 148   void addmw(Address a, int imm, Register scratch) {
 149     ldrw(scratch, a);
 150     if (imm > 0)
 151       addw(scratch, scratch, (unsigned)imm);
 152     else
 153       subw(scratch, scratch, (unsigned)-imm);
 154     strw(scratch, a);
 155   }
 156 
 157   void bind(Label& L) {
 158     Assembler::bind(L);
 159     code()->clear_last_insn();
 160   }
 161 
 162   void membar(Membar_mask_bits order_constraint);
 163 
 164   using Assembler::ldr;
 165   using Assembler::str;
 166   using Assembler::ldrw;
 167   using Assembler::strw;
 168 
 169   void ldr(Register Rx, const Address &adr);
 170   void ldrw(Register Rw, const Address &adr);
 171   void str(Register Rx, const Address &adr);
 172   void strw(Register Rx, const Address &adr);
 173 
 174   // Frame creation and destruction shared between JITs.
 175   void build_frame(int framesize);
 176   void remove_frame(int framesize);
 177 
 178   virtual void _call_Unimplemented(address call_site) {
 179     mov(rscratch2, call_site);
 180   }
 181 
 182 // Microsoft's MSVC team thinks that the __FUNCSIG__ is approximately (sympathy for calling conventions) equivalent to __PRETTY_FUNCTION__
 183 // Also, from Clang patch: "It is very similar to GCC's PRETTY_FUNCTION, except it prints the calling convention."
 184 // https://reviews.llvm.org/D3311
 185 
 186 #ifdef _WIN64
 187 #define call_Unimplemented() _call_Unimplemented((address)__FUNCSIG__)
 188 #else
 189 #define call_Unimplemented() _call_Unimplemented((address)__PRETTY_FUNCTION__)
 190 #endif
 191 
 192   // aliases defined in AARCH64 spec
 193 
 194   template<class T>
 195   inline void cmpw(Register Rd, T imm)  { subsw(zr, Rd, imm); }
 196 
 197   inline void cmp(Register Rd, unsigned char imm8)  { subs(zr, Rd, imm8); }
 198   inline void cmp(Register Rd, unsigned imm) = delete;
 199 
 200   template<class T>
 201   inline void cmnw(Register Rd, T imm) { addsw(zr, Rd, imm); }
 202 
 203   inline void cmn(Register Rd, unsigned char imm8)  { adds(zr, Rd, imm8); }
 204   inline void cmn(Register Rd, unsigned imm) = delete;
 205 
 206   void cset(Register Rd, Assembler::Condition cond) {
 207     csinc(Rd, zr, zr, ~cond);
 208   }
 209   void csetw(Register Rd, Assembler::Condition cond) {
 210     csincw(Rd, zr, zr, ~cond);
 211   }
 212 
 213   void cneg(Register Rd, Register Rn, Assembler::Condition cond) {
 214     csneg(Rd, Rn, Rn, ~cond);
 215   }
 216   void cnegw(Register Rd, Register Rn, Assembler::Condition cond) {
 217     csnegw(Rd, Rn, Rn, ~cond);
 218   }
 219 
 220   inline void movw(Register Rd, Register Rn) {
 221     if (Rd == sp || Rn == sp) {
 222       Assembler::addw(Rd, Rn, 0U);
 223     } else {
 224       orrw(Rd, zr, Rn);
 225     }
 226   }
 227   inline void mov(Register Rd, Register Rn) {
 228     assert(Rd != r31_sp && Rn != r31_sp, "should be");
 229     if (Rd == Rn) {
 230     } else if (Rd == sp || Rn == sp) {
 231       Assembler::add(Rd, Rn, 0U);
 232     } else {
 233       orr(Rd, zr, Rn);
 234     }
 235   }
 236 
 237   inline void moviw(Register Rd, unsigned imm) { orrw(Rd, zr, imm); }
 238   inline void movi(Register Rd, unsigned imm) { orr(Rd, zr, imm); }
 239 
 240   inline void tstw(Register Rd, Register Rn) { andsw(zr, Rd, Rn); }
 241   inline void tst(Register Rd, Register Rn) { ands(zr, Rd, Rn); }
 242 
 243   inline void tstw(Register Rd, uint64_t imm) { andsw(zr, Rd, imm); }
 244   inline void tst(Register Rd, uint64_t imm) { ands(zr, Rd, imm); }
 245 
 246   inline void bfiw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 247     bfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
 248   }
 249   inline void bfi(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 250     bfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
 251   }
 252 
 253   inline void bfxilw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 254     bfmw(Rd, Rn, lsb, (lsb + width - 1));
 255   }
 256   inline void bfxil(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 257     bfm(Rd, Rn, lsb , (lsb + width - 1));
 258   }
 259 
 260   inline void sbfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 261     sbfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
 262   }
 263   inline void sbfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 264     sbfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
 265   }
 266 
 267   inline void sbfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 268     sbfmw(Rd, Rn, lsb, (lsb + width - 1));
 269   }
 270   inline void sbfx(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 271     sbfm(Rd, Rn, lsb , (lsb + width - 1));
 272   }
 273 
 274   inline void ubfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 275     ubfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
 276   }
 277   inline void ubfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 278     ubfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
 279   }
 280 
 281   inline void ubfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 282     ubfmw(Rd, Rn, lsb, (lsb + width - 1));
 283   }
 284   inline void ubfx(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 285     ubfm(Rd, Rn, lsb , (lsb + width - 1));
 286   }
 287 
 288   inline void asrw(Register Rd, Register Rn, unsigned imm) {
 289     sbfmw(Rd, Rn, imm, 31);
 290   }
 291 
 292   inline void asr(Register Rd, Register Rn, unsigned imm) {
 293     sbfm(Rd, Rn, imm, 63);
 294   }
 295 
 296   inline void lslw(Register Rd, Register Rn, unsigned imm) {
 297     ubfmw(Rd, Rn, ((32 - imm) & 31), (31 - imm));
 298   }
 299 
 300   inline void lsl(Register Rd, Register Rn, unsigned imm) {
 301     ubfm(Rd, Rn, ((64 - imm) & 63), (63 - imm));
 302   }
 303 
 304   inline void lsrw(Register Rd, Register Rn, unsigned imm) {
 305     ubfmw(Rd, Rn, imm, 31);
 306   }
 307 
 308   inline void lsr(Register Rd, Register Rn, unsigned imm) {
 309     ubfm(Rd, Rn, imm, 63);
 310   }
 311 
 312   inline void rorw(Register Rd, Register Rn, unsigned imm) {
 313     extrw(Rd, Rn, Rn, imm);
 314   }
 315 
 316   inline void ror(Register Rd, Register Rn, unsigned imm) {
 317     extr(Rd, Rn, Rn, imm);
 318   }
 319 
 320   inline void sxtbw(Register Rd, Register Rn) {
 321     sbfmw(Rd, Rn, 0, 7);
 322   }
 323   inline void sxthw(Register Rd, Register Rn) {
 324     sbfmw(Rd, Rn, 0, 15);
 325   }
 326   inline void sxtb(Register Rd, Register Rn) {
 327     sbfm(Rd, Rn, 0, 7);
 328   }
 329   inline void sxth(Register Rd, Register Rn) {
 330     sbfm(Rd, Rn, 0, 15);
 331   }
 332   inline void sxtw(Register Rd, Register Rn) {
 333     sbfm(Rd, Rn, 0, 31);
 334   }
 335 
 336   inline void uxtbw(Register Rd, Register Rn) {
 337     ubfmw(Rd, Rn, 0, 7);
 338   }
 339   inline void uxthw(Register Rd, Register Rn) {
 340     ubfmw(Rd, Rn, 0, 15);
 341   }
 342   inline void uxtb(Register Rd, Register Rn) {
 343     ubfm(Rd, Rn, 0, 7);
 344   }
 345   inline void uxth(Register Rd, Register Rn) {
 346     ubfm(Rd, Rn, 0, 15);
 347   }
 348   inline void uxtw(Register Rd, Register Rn) {
 349     ubfm(Rd, Rn, 0, 31);
 350   }
 351 
 352   inline void cmnw(Register Rn, Register Rm) {
 353     addsw(zr, Rn, Rm);
 354   }
 355   inline void cmn(Register Rn, Register Rm) {
 356     adds(zr, Rn, Rm);
 357   }
 358 
 359   inline void cmpw(Register Rn, Register Rm) {
 360     subsw(zr, Rn, Rm);
 361   }
 362   inline void cmp(Register Rn, Register Rm) {
 363     subs(zr, Rn, Rm);
 364   }
 365 
 366   inline void negw(Register Rd, Register Rn) {
 367     subw(Rd, zr, Rn);
 368   }
 369 
 370   inline void neg(Register Rd, Register Rn) {
 371     sub(Rd, zr, Rn);
 372   }
 373 
 374   inline void negsw(Register Rd, Register Rn) {
 375     subsw(Rd, zr, Rn);
 376   }
 377 
 378   inline void negs(Register Rd, Register Rn) {
 379     subs(Rd, zr, Rn);
 380   }
 381 
 382   inline void cmnw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
 383     addsw(zr, Rn, Rm, kind, shift);
 384   }
 385   inline void cmn(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
 386     adds(zr, Rn, Rm, kind, shift);
 387   }
 388 
 389   inline void cmpw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
 390     subsw(zr, Rn, Rm, kind, shift);
 391   }
 392   inline void cmp(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
 393     subs(zr, Rn, Rm, kind, shift);
 394   }
 395 
 396   inline void negw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
 397     subw(Rd, zr, Rn, kind, shift);
 398   }
 399 
 400   inline void neg(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
 401     sub(Rd, zr, Rn, kind, shift);
 402   }
 403 
 404   inline void negsw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
 405     subsw(Rd, zr, Rn, kind, shift);
 406   }
 407 
 408   inline void negs(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
 409     subs(Rd, zr, Rn, kind, shift);
 410   }
 411 
 412   inline void mnegw(Register Rd, Register Rn, Register Rm) {
 413     msubw(Rd, Rn, Rm, zr);
 414   }
 415   inline void mneg(Register Rd, Register Rn, Register Rm) {
 416     msub(Rd, Rn, Rm, zr);
 417   }
 418 
 419   inline void mulw(Register Rd, Register Rn, Register Rm) {
 420     maddw(Rd, Rn, Rm, zr);
 421   }
 422   inline void mul(Register Rd, Register Rn, Register Rm) {
 423     madd(Rd, Rn, Rm, zr);
 424   }
 425 
 426   inline void smnegl(Register Rd, Register Rn, Register Rm) {
 427     smsubl(Rd, Rn, Rm, zr);
 428   }
 429   inline void smull(Register Rd, Register Rn, Register Rm) {
 430     smaddl(Rd, Rn, Rm, zr);
 431   }
 432 
 433   inline void umnegl(Register Rd, Register Rn, Register Rm) {
 434     umsubl(Rd, Rn, Rm, zr);
 435   }
 436   inline void umull(Register Rd, Register Rn, Register Rm) {
 437     umaddl(Rd, Rn, Rm, zr);
 438   }
 439 
 440 #define WRAP(INSN)                                                            \
 441   void INSN(Register Rd, Register Rn, Register Rm, Register Ra) {             \
 442     if (VM_Version::supports_a53mac() && Ra != zr)                            \
 443       nop();                                                                  \
 444     Assembler::INSN(Rd, Rn, Rm, Ra);                                          \
 445   }
 446 
 447   WRAP(madd) WRAP(msub) WRAP(maddw) WRAP(msubw)
 448   WRAP(smaddl) WRAP(smsubl) WRAP(umaddl) WRAP(umsubl)
 449 #undef WRAP
 450 
 451 
 452   // macro assembly operations needed for aarch64
 453 
 454   // first two private routines for loading 32 bit or 64 bit constants
 455 private:
 456 
 457   void mov_immediate64(Register dst, uint64_t imm64);
 458   void mov_immediate32(Register dst, uint32_t imm32);
 459 
 460   int push(unsigned int bitset, Register stack);
 461   int pop(unsigned int bitset, Register stack);
 462 
 463   int push_fp(unsigned int bitset, Register stack);
 464   int pop_fp(unsigned int bitset, Register stack);
 465 
 466   int push_p(unsigned int bitset, Register stack);
 467   int pop_p(unsigned int bitset, Register stack);
 468 
 469   void mov(Register dst, Address a);
 470 
 471 public:
 472   void push(RegSet regs, Register stack) { if (regs.bits()) push(regs.bits(), stack); }
 473   void pop(RegSet regs, Register stack) { if (regs.bits()) pop(regs.bits(), stack); }
 474 
 475   void push_fp(FloatRegSet regs, Register stack) { if (regs.bits()) push_fp(regs.bits(), stack); }
 476   void pop_fp(FloatRegSet regs, Register stack) { if (regs.bits()) pop_fp(regs.bits(), stack); }
 477 
 478   static RegSet call_clobbered_gp_registers();
 479 
 480   void push_p(PRegSet regs, Register stack) { if (regs.bits()) push_p(regs.bits(), stack); }
 481   void pop_p(PRegSet regs, Register stack) { if (regs.bits()) pop_p(regs.bits(), stack); }
 482 
 483   // Push and pop everything that might be clobbered by a native
 484   // runtime call except rscratch1 and rscratch2.  (They are always
 485   // scratch, so we don't have to protect them.)  Only save the lower
 486   // 64 bits of each vector register. Additional registers can be excluded
 487   // in a passed RegSet.
 488   void push_call_clobbered_registers_except(RegSet exclude);
 489   void pop_call_clobbered_registers_except(RegSet exclude);
 490 
 491   void push_call_clobbered_registers() {
 492     push_call_clobbered_registers_except(RegSet());
 493   }
 494   void pop_call_clobbered_registers() {
 495     pop_call_clobbered_registers_except(RegSet());
 496   }
 497 
 498 
 499   // now mov instructions for loading absolute addresses and 32 or
 500   // 64 bit integers
 501 
 502   inline void mov(Register dst, address addr)             { mov_immediate64(dst, (uint64_t)addr); }
 503 
 504   template<typename T, ENABLE_IF(std::is_integral<T>::value)>
 505   inline void mov(Register dst, T o)                      { mov_immediate64(dst, (uint64_t)o); }
 506 
 507   inline void movw(Register dst, uint32_t imm32)          { mov_immediate32(dst, imm32); }
 508 
 509   void mov(Register dst, RegisterOrConstant src) {
 510     if (src.is_register())
 511       mov(dst, src.as_register());
 512     else
 513       mov(dst, src.as_constant());
 514   }
 515 
 516   void movptr(Register r, uintptr_t imm64);
 517 
 518   void mov(FloatRegister Vd, SIMD_Arrangement T, uint64_t imm64);
 519 
 520   void mov(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) {
 521     orr(Vd, T, Vn, Vn);
 522   }
 523 
 524 
 525 public:
 526 
 527   // Generalized Test Bit And Branch, including a "far" variety which
 528   // spans more than 32KiB.
 529   void tbr(Condition cond, Register Rt, int bitpos, Label &dest, bool isfar = false) {
 530     assert(cond == EQ || cond == NE, "must be");
 531 
 532     if (isfar)
 533       cond = ~cond;
 534 
 535     void (Assembler::* branch)(Register Rt, int bitpos, Label &L);
 536     if (cond == Assembler::EQ)
 537       branch = &Assembler::tbz;
 538     else
 539       branch = &Assembler::tbnz;
 540 
 541     if (isfar) {
 542       Label L;
 543       (this->*branch)(Rt, bitpos, L);
 544       b(dest);
 545       bind(L);
 546     } else {
 547       (this->*branch)(Rt, bitpos, dest);
 548     }
 549   }
 550 
 551   // macro instructions for accessing and updating floating point
 552   // status register
 553   //
 554   // FPSR : op1 == 011
 555   //        CRn == 0100
 556   //        CRm == 0100
 557   //        op2 == 001
 558 
 559   inline void get_fpsr(Register reg)
 560   {
 561     mrs(0b11, 0b0100, 0b0100, 0b001, reg);
 562   }
 563 
 564   inline void set_fpsr(Register reg)
 565   {
 566     msr(0b011, 0b0100, 0b0100, 0b001, reg);
 567   }
 568 
 569   inline void clear_fpsr()
 570   {
 571     msr(0b011, 0b0100, 0b0100, 0b001, zr);
 572   }
 573 
 574   // DCZID_EL0: op1 == 011
 575   //            CRn == 0000
 576   //            CRm == 0000
 577   //            op2 == 111
 578   inline void get_dczid_el0(Register reg)
 579   {
 580     mrs(0b011, 0b0000, 0b0000, 0b111, reg);
 581   }
 582 
 583   // CTR_EL0:   op1 == 011
 584   //            CRn == 0000
 585   //            CRm == 0000
 586   //            op2 == 001
 587   inline void get_ctr_el0(Register reg)
 588   {
 589     mrs(0b011, 0b0000, 0b0000, 0b001, reg);
 590   }
 591 
 592   // idiv variant which deals with MINLONG as dividend and -1 as divisor
 593   int corrected_idivl(Register result, Register ra, Register rb,
 594                       bool want_remainder, Register tmp = rscratch1);
 595   int corrected_idivq(Register result, Register ra, Register rb,
 596                       bool want_remainder, Register tmp = rscratch1);
 597 
 598   // Support for NULL-checks
 599   //
 600   // Generates code that causes a NULL OS exception if the content of reg is NULL.
 601   // If the accessed location is M[reg + offset] and the offset is known, provide the
 602   // offset. No explicit code generation is needed if the offset is within a certain
 603   // range (0 <= offset <= page_size).
 604 
 605   virtual void null_check(Register reg, int offset = -1);
 606   static bool needs_explicit_null_check(intptr_t offset);
 607   static bool uses_implicit_null_check(void* address);
 608 
 609   static address target_addr_for_insn(address insn_addr, unsigned insn);
 610   static address target_addr_for_insn_or_null(address insn_addr, unsigned insn);
 611   static address target_addr_for_insn(address insn_addr) {
 612     unsigned insn = *(unsigned*)insn_addr;
 613     return target_addr_for_insn(insn_addr, insn);
 614   }
 615   static address target_addr_for_insn_or_null(address insn_addr) {
 616     unsigned insn = *(unsigned*)insn_addr;
 617     return target_addr_for_insn_or_null(insn_addr, insn);
 618   }
 619 
 620   // Required platform-specific helpers for Label::patch_instructions.
 621   // They _shadow_ the declarations in AbstractAssembler, which are undefined.
 622   static int pd_patch_instruction_size(address branch, address target);
 623   static void pd_patch_instruction(address branch, address target, const char* file = NULL, int line = 0) {
 624     pd_patch_instruction_size(branch, target);
 625   }
 626   static address pd_call_destination(address branch) {
 627     return target_addr_for_insn(branch);
 628   }
 629 #ifndef PRODUCT
 630   static void pd_print_patched_instruction(address branch);
 631 #endif
 632 
 633   static int patch_oop(address insn_addr, address o);
 634   static int patch_narrow_klass(address insn_addr, narrowKlass n);
 635 
 636   // Return whether code is emitted to a scratch blob.
 637   virtual bool in_scratch_emit_size() {
 638     return false;
 639   }
 640   address emit_trampoline_stub(int insts_call_instruction_offset, address target);
 641   void emit_static_call_stub();
 642 
 643   // The following 4 methods return the offset of the appropriate move instruction
 644 
 645   // Support for fast byte/short loading with zero extension (depending on particular CPU)
 646   int load_unsigned_byte(Register dst, Address src);
 647   int load_unsigned_short(Register dst, Address src);
 648 
 649   // Support for fast byte/short loading with sign extension (depending on particular CPU)
 650   int load_signed_byte(Register dst, Address src);
 651   int load_signed_short(Register dst, Address src);
 652 
 653   int load_signed_byte32(Register dst, Address src);
 654   int load_signed_short32(Register dst, Address src);
 655 
 656   // Support for sign-extension (hi:lo = extend_sign(lo))
 657   void extend_sign(Register hi, Register lo);
 658 
 659   // Load and store values by size and signed-ness
 660   void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg);
 661   void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg);
 662 
 663   // Support for inc/dec with optimal instruction selection depending on value
 664 
 665   // x86_64 aliases an unqualified register/address increment and
 666   // decrement to call incrementq and decrementq but also supports
 667   // explicitly sized calls to incrementq/decrementq or
 668   // incrementl/decrementl
 669 
 670   // for aarch64 the proper convention would be to use
 671   // increment/decrement for 64 bit operations and
 672   // incrementw/decrementw for 32 bit operations. so when porting
 673   // x86_64 code we can leave calls to increment/decrement as is,
 674   // replace incrementq/decrementq with increment/decrement and
 675   // replace incrementl/decrementl with incrementw/decrementw.
 676 
 677   // n.b. increment/decrement calls with an Address destination will
 678   // need to use a scratch register to load the value to be
 679   // incremented. increment/decrement calls which add or subtract a
 680   // constant value greater than 2^12 will need to use a 2nd scratch
 681   // register to hold the constant. so, a register increment/decrement
 682   // may trash rscratch2 and an address increment/decrement trash
 683   // rscratch and rscratch2
 684 
 685   void decrementw(Address dst, int value = 1);
 686   void decrementw(Register reg, int value = 1);
 687 
 688   void decrement(Register reg, int value = 1);
 689   void decrement(Address dst, int value = 1);
 690 
 691   void incrementw(Address dst, int value = 1);
 692   void incrementw(Register reg, int value = 1);
 693 
 694   void increment(Register reg, int value = 1);
 695   void increment(Address dst, int value = 1);
 696 
 697 
 698   // Alignment
 699   void align(int modulus);
 700 
 701   // nop
 702   void post_call_nop();
 703 
 704   // Stack frame creation/removal
 705   void enter(bool strip_ret_addr = false);
 706   void leave();
 707 
 708   // ROP Protection
 709   void protect_return_address();
 710   void protect_return_address(Register return_reg, Register temp_reg);
 711   void authenticate_return_address(Register return_reg = lr);
 712   void authenticate_return_address(Register return_reg, Register temp_reg);
 713   void strip_return_address();
 714   void check_return_address(Register return_reg=lr) PRODUCT_RETURN;
 715 
 716   // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
 717   // The pointer will be loaded into the thread register.
 718   void get_thread(Register thread);
 719 
 720   // support for argument shuffling
 721   void move32_64(VMRegPair src, VMRegPair dst, Register tmp = rscratch1);
 722   void float_move(VMRegPair src, VMRegPair dst, Register tmp = rscratch1);
 723   void long_move(VMRegPair src, VMRegPair dst, Register tmp = rscratch1);
 724   void double_move(VMRegPair src, VMRegPair dst, Register tmp = rscratch1);
 725   void object_move(
 726                    OopMap* map,
 727                    int oop_handle_offset,
 728                    int framesize_in_slots,
 729                    VMRegPair src,
 730                    VMRegPair dst,
 731                    bool is_receiver,
 732                    int* receiver_offset);
 733 
 734 
 735   // Support for VM calls
 736   //
 737   // It is imperative that all calls into the VM are handled via the call_VM macros.
 738   // They make sure that the stack linkage is setup correctly. call_VM's correspond
 739   // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
 740 
 741 
 742   void call_VM(Register oop_result,
 743                address entry_point,
 744                bool check_exceptions = true);
 745   void call_VM(Register oop_result,
 746                address entry_point,
 747                Register arg_1,
 748                bool check_exceptions = true);
 749   void call_VM(Register oop_result,
 750                address entry_point,
 751                Register arg_1, Register arg_2,
 752                bool check_exceptions = true);
 753   void call_VM(Register oop_result,
 754                address entry_point,
 755                Register arg_1, Register arg_2, Register arg_3,
 756                bool check_exceptions = true);
 757 
 758   // Overloadings with last_Java_sp
 759   void call_VM(Register oop_result,
 760                Register last_java_sp,
 761                address entry_point,
 762                int number_of_arguments = 0,
 763                bool check_exceptions = true);
 764   void call_VM(Register oop_result,
 765                Register last_java_sp,
 766                address entry_point,
 767                Register arg_1, bool
 768                check_exceptions = true);
 769   void call_VM(Register oop_result,
 770                Register last_java_sp,
 771                address entry_point,
 772                Register arg_1, Register arg_2,
 773                bool check_exceptions = true);
 774   void call_VM(Register oop_result,
 775                Register last_java_sp,
 776                address entry_point,
 777                Register arg_1, Register arg_2, Register arg_3,
 778                bool check_exceptions = true);
 779 
 780   void get_vm_result  (Register oop_result, Register thread);
 781   void get_vm_result_2(Register metadata_result, Register thread);
 782 
 783   // These always tightly bind to MacroAssembler::call_VM_base
 784   // bypassing the virtual implementation
 785   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
 786   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
 787   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
 788   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
 789   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
 790 
 791   void call_VM_leaf(address entry_point,
 792                     int number_of_arguments = 0);
 793   void call_VM_leaf(address entry_point,
 794                     Register arg_1);
 795   void call_VM_leaf(address entry_point,
 796                     Register arg_1, Register arg_2);
 797   void call_VM_leaf(address entry_point,
 798                     Register arg_1, Register arg_2, Register arg_3);
 799 
 800   // These always tightly bind to MacroAssembler::call_VM_leaf_base
 801   // bypassing the virtual implementation
 802   void super_call_VM_leaf(address entry_point);
 803   void super_call_VM_leaf(address entry_point, Register arg_1);
 804   void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
 805   void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
 806   void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
 807 
 808   // last Java Frame (fills frame anchor)
 809   void set_last_Java_frame(Register last_java_sp,
 810                            Register last_java_fp,
 811                            address last_java_pc,
 812                            Register scratch);
 813 
 814   void set_last_Java_frame(Register last_java_sp,
 815                            Register last_java_fp,
 816                            Label &last_java_pc,
 817                            Register scratch);
 818 
 819   void set_last_Java_frame(Register last_java_sp,
 820                            Register last_java_fp,
 821                            Register last_java_pc,
 822                            Register scratch);
 823 
 824   void reset_last_Java_frame(Register thread);
 825 
 826   // thread in the default location (rthread)
 827   void reset_last_Java_frame(bool clear_fp);
 828 
 829   // Stores
 830   void store_check(Register obj);                // store check for obj - register is destroyed afterwards
 831   void store_check(Register obj, Address dst);   // same as above, dst is exact store location (reg. is destroyed)
 832 
 833   void resolve_jobject(Register value, Register tmp1, Register tmp2);
 834 
 835   // C 'boolean' to Java boolean: x == 0 ? 0 : 1
 836   void c2bool(Register x);
 837 
 838   void load_method_holder_cld(Register rresult, Register rmethod);
 839   void load_method_holder(Register holder, Register method);
 840 
 841   // oop manipulations
 842   void load_klass(Register dst, Register src);
 843   void store_klass(Register dst, Register src);
 844   void cmp_klass(Register oop, Register trial_klass, Register tmp);
 845 
 846   void resolve_weak_handle(Register result, Register tmp1, Register tmp2);
 847   void resolve_oop_handle(Register result, Register tmp1, Register tmp2);
 848   void load_mirror(Register dst, Register method, Register tmp1, Register tmp2);
 849 
 850   void access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
 851                       Register tmp1, Register tmp2);
 852 
 853   void access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register src,
 854                        Register tmp1, Register tmp2, Register tmp3);
 855 
 856   void load_heap_oop(Register dst, Address src, Register tmp1 = noreg,
 857                      Register tmp2 = noreg, DecoratorSet decorators = 0);
 858 
 859   void load_heap_oop_not_null(Register dst, Address src, Register tmp1 = noreg,
 860                               Register tmp2 = noreg, DecoratorSet decorators = 0);
 861   void store_heap_oop(Address dst, Register src, Register tmp1 = noreg,
 862                       Register tmp2 = noreg, Register tmp3 = noreg, DecoratorSet decorators = 0);
 863 
 864   // currently unimplemented
 865   // Used for storing NULL. All other oop constants should be
 866   // stored using routines that take a jobject.
 867   void store_heap_oop_null(Address dst);
 868 
 869   void store_klass_gap(Register dst, Register src);
 870 
 871   // This dummy is to prevent a call to store_heap_oop from
 872   // converting a zero (like NULL) into a Register by giving
 873   // the compiler two choices it can't resolve
 874 
 875   void store_heap_oop(Address dst, void* dummy);
 876 
 877   void encode_heap_oop(Register d, Register s);
 878   void encode_heap_oop(Register r) { encode_heap_oop(r, r); }
 879   void decode_heap_oop(Register d, Register s);
 880   void decode_heap_oop(Register r) { decode_heap_oop(r, r); }
 881   void encode_heap_oop_not_null(Register r);
 882   void decode_heap_oop_not_null(Register r);
 883   void encode_heap_oop_not_null(Register dst, Register src);
 884   void decode_heap_oop_not_null(Register dst, Register src);
 885 
 886   void set_narrow_oop(Register dst, jobject obj);
 887 
 888   void encode_klass_not_null(Register r);
 889   void decode_klass_not_null(Register r);
 890   void encode_klass_not_null(Register dst, Register src);
 891   void decode_klass_not_null(Register dst, Register src);
 892 
 893   void set_narrow_klass(Register dst, Klass* k);
 894 
 895   // if heap base register is used - reinit it with the correct value
 896   void reinit_heapbase();
 897 
 898   DEBUG_ONLY(void verify_heapbase(const char* msg);)
 899 
 900   void push_CPU_state(bool save_vectors = false, bool use_sve = false,
 901                       int sve_vector_size_in_bytes = 0, int total_predicate_in_bytes = 0);
 902   void pop_CPU_state(bool restore_vectors = false, bool use_sve = false,
 903                      int sve_vector_size_in_bytes = 0, int total_predicate_in_bytes = 0);
 904 
 905   void push_cont_fastpath(Register java_thread);
 906   void pop_cont_fastpath(Register java_thread);
 907 
 908   // Round up to a power of two
 909   void round_to(Register reg, int modulus);
 910 
 911   // java.lang.Math::round intrinsics
 912   void java_round_double(Register dst, FloatRegister src, FloatRegister ftmp);
 913   void java_round_float(Register dst, FloatRegister src, FloatRegister ftmp);
 914 
 915   // allocation
 916   void tlab_allocate(
 917     Register obj,                      // result: pointer to object after successful allocation
 918     Register var_size_in_bytes,        // object size in bytes if unknown at compile time; invalid otherwise
 919     int      con_size_in_bytes,        // object size in bytes if   known at compile time
 920     Register t1,                       // temp register
 921     Register t2,                       // temp register
 922     Label&   slow_case                 // continuation point if fast allocation fails
 923   );
 924   void verify_tlab();
 925 
 926   // interface method calling
 927   void lookup_interface_method(Register recv_klass,
 928                                Register intf_klass,
 929                                RegisterOrConstant itable_index,
 930                                Register method_result,
 931                                Register scan_temp,
 932                                Label& no_such_interface,
 933                    bool return_method = true);
 934 
 935   // virtual method calling
 936   // n.b. x86 allows RegisterOrConstant for vtable_index
 937   void lookup_virtual_method(Register recv_klass,
 938                              RegisterOrConstant vtable_index,
 939                              Register method_result);
 940 
 941   // Test sub_klass against super_klass, with fast and slow paths.
 942 
 943   // The fast path produces a tri-state answer: yes / no / maybe-slow.
 944   // One of the three labels can be NULL, meaning take the fall-through.
 945   // If super_check_offset is -1, the value is loaded up from super_klass.
 946   // No registers are killed, except temp_reg.
 947   void check_klass_subtype_fast_path(Register sub_klass,
 948                                      Register super_klass,
 949                                      Register temp_reg,
 950                                      Label* L_success,
 951                                      Label* L_failure,
 952                                      Label* L_slow_path,
 953                 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
 954 
 955   // The rest of the type check; must be wired to a corresponding fast path.
 956   // It does not repeat the fast path logic, so don't use it standalone.
 957   // The temp_reg and temp2_reg can be noreg, if no temps are available.
 958   // Updates the sub's secondary super cache as necessary.
 959   // If set_cond_codes, condition codes will be Z on success, NZ on failure.
 960   void check_klass_subtype_slow_path(Register sub_klass,
 961                                      Register super_klass,
 962                                      Register temp_reg,
 963                                      Register temp2_reg,
 964                                      Label* L_success,
 965                                      Label* L_failure,
 966                                      bool set_cond_codes = false);
 967 
 968   // Simplified, combined version, good for typical uses.
 969   // Falls through on failure.
 970   void check_klass_subtype(Register sub_klass,
 971                            Register super_klass,
 972                            Register temp_reg,
 973                            Label& L_success);
 974 
 975   void clinit_barrier(Register klass,
 976                       Register thread,
 977                       Label* L_fast_path = NULL,
 978                       Label* L_slow_path = NULL);
 979 
 980   Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
 981 
 982   void verify_sve_vector_length(Register tmp = rscratch1);
 983   void reinitialize_ptrue() {
 984     if (UseSVE > 0) {
 985       sve_ptrue(ptrue, B);
 986     }
 987   }
 988   void verify_ptrue();
 989 
 990   // Debugging
 991 
 992   // only if +VerifyOops
 993   void _verify_oop(Register reg, const char* s, const char* file, int line);
 994   void _verify_oop_addr(Address addr, const char * s, const char* file, int line);
 995 
 996   void _verify_oop_checked(Register reg, const char* s, const char* file, int line) {
 997     if (VerifyOops) {
 998       _verify_oop(reg, s, file, line);
 999     }
1000   }
1001   void _verify_oop_addr_checked(Address reg, const char* s, const char* file, int line) {
1002     if (VerifyOops) {
1003       _verify_oop_addr(reg, s, file, line);
1004     }
1005   }
1006 
1007 // TODO: verify method and klass metadata (compare against vptr?)
1008   void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
1009   void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
1010 
1011 #define verify_oop(reg) _verify_oop_checked(reg, "broken oop " #reg, __FILE__, __LINE__)
1012 #define verify_oop_msg(reg, msg) _verify_oop_checked(reg, "broken oop " #reg ", " #msg, __FILE__, __LINE__)
1013 #define verify_oop_addr(addr) _verify_oop_addr_checked(addr, "broken oop addr " #addr, __FILE__, __LINE__)
1014 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
1015 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
1016 
1017   // only if +VerifyFPU
1018   void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
1019 
1020   // prints msg, dumps registers and stops execution
1021   void stop(const char* msg);
1022 
1023   static void debug64(char* msg, int64_t pc, int64_t regs[]);
1024 
1025   void untested()                                { stop("untested"); }
1026 
1027   void unimplemented(const char* what = "");
1028 
1029   void should_not_reach_here()                   { stop("should not reach here"); }
1030 
1031   void _assert_asm(Condition cc, const char* msg);
1032 #define assert_asm0(cc, msg) _assert_asm(cc, FILE_AND_LINE ": " msg)
1033 #define assert_asm(masm, command, cc, msg) DEBUG_ONLY(command; (masm)->_assert_asm(cc, FILE_AND_LINE ": " #command " " #cc ": " msg))
1034 
1035   // Stack overflow checking
1036   void bang_stack_with_offset(int offset) {
1037     // stack grows down, caller passes positive offset
1038     assert(offset > 0, "must bang with negative offset");
1039     sub(rscratch2, sp, offset);
1040     str(zr, Address(rscratch2));
1041   }
1042 
1043   // Writes to stack successive pages until offset reached to check for
1044   // stack overflow + shadow pages.  Also, clobbers tmp
1045   void bang_stack_size(Register size, Register tmp);
1046 
1047   // Check for reserved stack access in method being exited (for JIT)
1048   void reserved_stack_check();
1049 
1050   // Arithmetics
1051 
1052   void addptr(const Address &dst, int32_t src);
1053   void cmpptr(Register src1, Address src2);
1054 
1055   void cmpoop(Register obj1, Register obj2);
1056 
1057   // Various forms of CAS
1058 
1059   void cmpxchg_obj_header(Register oldv, Register newv, Register obj, Register tmp,
1060                           Label &succeed, Label *fail);
1061   void cmpxchgptr(Register oldv, Register newv, Register addr, Register tmp,
1062                   Label &succeed, Label *fail);
1063 
1064   void cmpxchgw(Register oldv, Register newv, Register addr, Register tmp,
1065                   Label &succeed, Label *fail);
1066 
1067   void atomic_add(Register prev, RegisterOrConstant incr, Register addr);
1068   void atomic_addw(Register prev, RegisterOrConstant incr, Register addr);
1069   void atomic_addal(Register prev, RegisterOrConstant incr, Register addr);
1070   void atomic_addalw(Register prev, RegisterOrConstant incr, Register addr);
1071 
1072   void atomic_xchg(Register prev, Register newv, Register addr);
1073   void atomic_xchgw(Register prev, Register newv, Register addr);
1074   void atomic_xchgl(Register prev, Register newv, Register addr);
1075   void atomic_xchglw(Register prev, Register newv, Register addr);
1076   void atomic_xchgal(Register prev, Register newv, Register addr);
1077   void atomic_xchgalw(Register prev, Register newv, Register addr);
1078 
1079   void orptr(Address adr, RegisterOrConstant src) {
1080     ldr(rscratch1, adr);
1081     if (src.is_register())
1082       orr(rscratch1, rscratch1, src.as_register());
1083     else
1084       orr(rscratch1, rscratch1, src.as_constant());
1085     str(rscratch1, adr);
1086   }
1087 
1088   // A generic CAS; success or failure is in the EQ flag.
1089   // Clobbers rscratch1
1090   void cmpxchg(Register addr, Register expected, Register new_val,
1091                enum operand_size size,
1092                bool acquire, bool release, bool weak,
1093                Register result);
1094 
1095 private:
1096   void compare_eq(Register rn, Register rm, enum operand_size size);
1097 
1098 #ifdef ASSERT
1099   // Template short-hand support to clean-up after a failed call to trampoline
1100   // call generation (see trampoline_call() below),  when a set of Labels must
1101   // be reset (before returning).
1102   template<typename Label, typename... More>
1103   void reset_labels(Label &lbl, More&... more) {
1104     lbl.reset(); reset_labels(more...);
1105   }
1106   template<typename Label>
1107   void reset_labels(Label &lbl) {
1108     lbl.reset();
1109   }
1110 #endif
1111 
1112 public:
1113   // AArch64 OpenJDK uses four different types of calls:
1114   //   - direct call: bl pc_relative_offset
1115   //     This is the shortest and the fastest, but the offset has the range:
1116   //     +/-128MB for the release build, +/-2MB for the debug build.
1117   //
1118   //   - far call: adrp reg, pc_relative_offset; add; bl reg
1119   //     This is longer than a direct call. The offset has
1120   //     the range +/-4GB. As the code cache size is limited to 4GB,
1121   //     far calls can reach anywhere in the code cache. If a jump is
1122   //     needed rather than a call, a far jump 'b reg' can be used instead.
1123   //     All instructions are embedded at a call site.
1124   //
1125   //   - trampoline call:
1126   //     This is only available in C1/C2-generated code (nmethod). It is a combination
1127   //     of a direct call, which is used if the destination of a call is in range,
1128   //     and a register-indirect call. It has the advantages of reaching anywhere in
1129   //     the AArch64 address space and being patchable at runtime when the generated
1130   //     code is being executed by other threads.
1131   //
1132   //     [Main code section]
1133   //       bl trampoline
1134   //     [Stub code section]
1135   //     trampoline:
1136   //       ldr reg, pc + 8
1137   //       br reg
1138   //       <64-bit destination address>
1139   //
1140   //     If the destination is in range when the generated code is moved to the code
1141   //     cache, 'bl trampoline' is replaced with 'bl destination' and the trampoline
1142   //     is not used.
1143   //     The optimization does not remove the trampoline from the stub section.
1144   //     This is necessary because the trampoline may well be redirected later when
1145   //     code is patched, and the new destination may not be reachable by a simple BR
1146   //     instruction.
1147   //
1148   //   - indirect call: move reg, address; blr reg
1149   //     This too can reach anywhere in the address space, but it cannot be
1150   //     patched while code is running, so it must only be modified at a safepoint.
1151   //     This form of call is most suitable for targets at fixed addresses, which
1152   //     will never be patched.
1153   //
1154   // The patching we do conforms to the "Concurrent modification and
1155   // execution of instructions" section of the Arm Architectural
1156   // Reference Manual, which only allows B, BL, BRK, HVC, ISB, NOP, SMC,
1157   // or SVC instructions to be modified while another thread is
1158   // executing them.
1159   //
1160   // To patch a trampoline call when the BL can't reach, we first modify
1161   // the 64-bit destination address in the trampoline, then modify the
1162   // BL to point to the trampoline, then flush the instruction cache to
1163   // broadcast the change to all executing threads. See
1164   // NativeCall::set_destination_mt_safe for the details.
1165   //
1166   // There is a benign race in that the other thread might observe the
1167   // modified BL before it observes the modified 64-bit destination
1168   // address. That does not matter because the destination method has been
1169   // invalidated, so there will be a trap at its start.
1170   // For this to work, the destination address in the trampoline is
1171   // always updated, even if we're not using the trampoline.
1172 
1173   // Emit a direct call if the entry address will always be in range,
1174   // otherwise a trampoline call.
1175   // Supported entry.rspec():
1176   // - relocInfo::runtime_call_type
1177   // - relocInfo::opt_virtual_call_type
1178   // - relocInfo::static_call_type
1179   // - relocInfo::virtual_call_type
1180   //
1181   // Return: the call PC or NULL if CodeCache is full.
1182   address trampoline_call(Address entry);
1183 
1184   static bool far_branches() {
1185     return ReservedCodeCacheSize > branch_range;
1186   }
1187 
1188   // Check if branches to the the non nmethod section require a far jump
1189   static bool codestub_branch_needs_far_jump() {
1190     return CodeCache::max_distance_to_non_nmethod() > branch_range;
1191   }
1192 
1193   // Emit a direct call/jump if the entry address will always be in range,
1194   // otherwise a far call/jump.
1195   // The address must be inside the code cache.
1196   // Supported entry.rspec():
1197   // - relocInfo::external_word_type
1198   // - relocInfo::runtime_call_type
1199   // - relocInfo::none
1200   // In the case of a far call/jump, the entry address is put in the tmp register.
1201   // The tmp register is invalidated.
1202   //
1203   // Far_jump returns the amount of the emitted code.
1204   void far_call(Address entry, Register tmp = rscratch1);
1205   int far_jump(Address entry, Register tmp = rscratch1);
1206 
1207   static int far_codestub_branch_size() {
1208     if (codestub_branch_needs_far_jump()) {
1209       return 3 * 4;  // adrp, add, br
1210     } else {
1211       return 4;
1212     }
1213   }
1214 
1215   // Emit the CompiledIC call idiom
1216   address ic_call(address entry, jint method_index = 0);
1217 
1218 public:
1219 
1220   // Data
1221 
1222   void mov_metadata(Register dst, Metadata* obj);
1223   Address allocate_metadata_address(Metadata* obj);
1224   Address constant_oop_address(jobject obj);
1225 
1226   void movoop(Register dst, jobject obj);
1227 
1228   // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
1229   void kernel_crc32(Register crc, Register buf, Register len,
1230         Register table0, Register table1, Register table2, Register table3,
1231         Register tmp, Register tmp2, Register tmp3);
1232   // CRC32 code for java.util.zip.CRC32C::updateBytes() intrinsic.
1233   void kernel_crc32c(Register crc, Register buf, Register len,
1234         Register table0, Register table1, Register table2, Register table3,
1235         Register tmp, Register tmp2, Register tmp3);
1236 
1237   // Stack push and pop individual 64 bit registers
1238   void push(Register src);
1239   void pop(Register dst);
1240 
1241   void repne_scan(Register addr, Register value, Register count,
1242                   Register scratch);
1243   void repne_scanw(Register addr, Register value, Register count,
1244                    Register scratch);
1245 
1246   typedef void (MacroAssembler::* add_sub_imm_insn)(Register Rd, Register Rn, unsigned imm);
1247   typedef void (MacroAssembler::* add_sub_reg_insn)(Register Rd, Register Rn, Register Rm, enum shift_kind kind, unsigned shift);
1248 
1249   // If a constant does not fit in an immediate field, generate some
1250   // number of MOV instructions and then perform the operation
1251   void wrap_add_sub_imm_insn(Register Rd, Register Rn, uint64_t imm,
1252                              add_sub_imm_insn insn1,
1253                              add_sub_reg_insn insn2, bool is32);
1254   // Separate vsn which sets the flags
1255   void wrap_adds_subs_imm_insn(Register Rd, Register Rn, uint64_t imm,
1256                                add_sub_imm_insn insn1,
1257                                add_sub_reg_insn insn2, bool is32);
1258 
1259 #define WRAP(INSN, is32)                                                \
1260   void INSN(Register Rd, Register Rn, uint64_t imm) {                   \
1261     wrap_add_sub_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN, is32); \
1262   }                                                                     \
1263                                                                         \
1264   void INSN(Register Rd, Register Rn, Register Rm,                      \
1265              enum shift_kind kind, unsigned shift = 0) {                \
1266     Assembler::INSN(Rd, Rn, Rm, kind, shift);                           \
1267   }                                                                     \
1268                                                                         \
1269   void INSN(Register Rd, Register Rn, Register Rm) {                    \
1270     Assembler::INSN(Rd, Rn, Rm);                                        \
1271   }                                                                     \
1272                                                                         \
1273   void INSN(Register Rd, Register Rn, Register Rm,                      \
1274            ext::operation option, int amount = 0) {                     \
1275     Assembler::INSN(Rd, Rn, Rm, option, amount);                        \
1276   }
1277 
1278   WRAP(add, false) WRAP(addw, true) WRAP(sub, false) WRAP(subw, true)
1279 
1280 #undef WRAP
1281 #define WRAP(INSN, is32)                                                \
1282   void INSN(Register Rd, Register Rn, uint64_t imm) {                   \
1283     wrap_adds_subs_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN, is32); \
1284   }                                                                     \
1285                                                                         \
1286   void INSN(Register Rd, Register Rn, Register Rm,                      \
1287              enum shift_kind kind, unsigned shift = 0) {                \
1288     Assembler::INSN(Rd, Rn, Rm, kind, shift);                           \
1289   }                                                                     \
1290                                                                         \
1291   void INSN(Register Rd, Register Rn, Register Rm) {                    \
1292     Assembler::INSN(Rd, Rn, Rm);                                        \
1293   }                                                                     \
1294                                                                         \
1295   void INSN(Register Rd, Register Rn, Register Rm,                      \
1296            ext::operation option, int amount = 0) {                     \
1297     Assembler::INSN(Rd, Rn, Rm, option, amount);                        \
1298   }
1299 
1300   WRAP(adds, false) WRAP(addsw, true) WRAP(subs, false) WRAP(subsw, true)
1301 
1302   void add(Register Rd, Register Rn, RegisterOrConstant increment);
1303   void addw(Register Rd, Register Rn, RegisterOrConstant increment);
1304   void sub(Register Rd, Register Rn, RegisterOrConstant decrement);
1305   void subw(Register Rd, Register Rn, RegisterOrConstant decrement);
1306 
1307   void adrp(Register reg1, const Address &dest, uint64_t &byte_offset);
1308 
1309   void tableswitch(Register index, jint lowbound, jint highbound,
1310                    Label &jumptable, Label &jumptable_end, int stride = 1) {
1311     adr(rscratch1, jumptable);
1312     subsw(rscratch2, index, lowbound);
1313     subsw(zr, rscratch2, highbound - lowbound);
1314     br(Assembler::HS, jumptable_end);
1315     add(rscratch1, rscratch1, rscratch2,
1316         ext::sxtw, exact_log2(stride * Assembler::instruction_size));
1317     br(rscratch1);
1318   }
1319 
1320   // Form an address from base + offset in Rd.  Rd may or may not
1321   // actually be used: you must use the Address that is returned.  It
1322   // is up to you to ensure that the shift provided matches the size
1323   // of your data.
1324   Address form_address(Register Rd, Register base, int64_t byte_offset, int shift);
1325 
1326   // Return true iff an address is within the 48-bit AArch64 address
1327   // space.
1328   bool is_valid_AArch64_address(address a) {
1329     return ((uint64_t)a >> 48) == 0;
1330   }
1331 
1332   // Load the base of the cardtable byte map into reg.
1333   void load_byte_map_base(Register reg);
1334 
1335   // Prolog generator routines to support switch between x86 code and
1336   // generated ARM code
1337 
1338   // routine to generate an x86 prolog for a stub function which
1339   // bootstraps into the generated ARM code which directly follows the
1340   // stub
1341   //
1342 
1343   public:
1344 
1345   void ldr_constant(Register dest, const Address &const_addr) {
1346     if (NearCpool) {
1347       ldr(dest, const_addr);
1348     } else {
1349       uint64_t offset;
1350       adrp(dest, InternalAddress(const_addr.target()), offset);
1351       ldr(dest, Address(dest, offset));
1352     }
1353   }
1354 
1355   address read_polling_page(Register r, relocInfo::relocType rtype);
1356   void get_polling_page(Register dest, relocInfo::relocType rtype);
1357 
1358   // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
1359   void update_byte_crc32(Register crc, Register val, Register table);
1360   void update_word_crc32(Register crc, Register v, Register tmp,
1361         Register table0, Register table1, Register table2, Register table3,
1362         bool upper = false);
1363 
1364   address count_positives(Register ary1, Register len, Register result);
1365 
1366   address arrays_equals(Register a1, Register a2, Register result, Register cnt1,
1367                         Register tmp1, Register tmp2, Register tmp3, int elem_size);
1368 
1369   void string_equals(Register a1, Register a2, Register result, Register cnt1,
1370                      int elem_size);
1371 
1372   void fill_words(Register base, Register cnt, Register value);
1373   address zero_words(Register base, uint64_t cnt);
1374   address zero_words(Register ptr, Register cnt);
1375   void zero_dcache_blocks(Register base, Register cnt);
1376 
1377   static const int zero_words_block_size;
1378 
1379   address byte_array_inflate(Register src, Register dst, Register len,
1380                              FloatRegister vtmp1, FloatRegister vtmp2,
1381                              FloatRegister vtmp3, Register tmp4);
1382 
1383   void char_array_compress(Register src, Register dst, Register len,
1384                            Register res,
1385                            FloatRegister vtmp0, FloatRegister vtmp1,
1386                            FloatRegister vtmp2, FloatRegister vtmp3);
1387 
1388   void encode_iso_array(Register src, Register dst,
1389                         Register len, Register res, bool ascii,
1390                         FloatRegister vtmp0, FloatRegister vtmp1,
1391                         FloatRegister vtmp2, FloatRegister vtmp3);
1392 
1393   void fast_log(FloatRegister vtmp0, FloatRegister vtmp1, FloatRegister vtmp2,
1394                 FloatRegister vtmp3, FloatRegister vtmp4, FloatRegister vtmp5,
1395                 FloatRegister tmpC1, FloatRegister tmpC2, FloatRegister tmpC3,
1396                 FloatRegister tmpC4, Register tmp1, Register tmp2,
1397                 Register tmp3, Register tmp4, Register tmp5);
1398   void generate_dsin_dcos(bool isCos, address npio2_hw, address two_over_pi,
1399       address pio2, address dsin_coef, address dcos_coef);
1400  private:
1401   // begin trigonometric functions support block
1402   void generate__ieee754_rem_pio2(address npio2_hw, address two_over_pi, address pio2);
1403   void generate__kernel_rem_pio2(address two_over_pi, address pio2);
1404   void generate_kernel_sin(FloatRegister x, bool iyIsOne, address dsin_coef);
1405   void generate_kernel_cos(FloatRegister x, address dcos_coef);
1406   // end trigonometric functions support block
1407   void add2_with_carry(Register final_dest_hi, Register dest_hi, Register dest_lo,
1408                        Register src1, Register src2);
1409   void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
1410     add2_with_carry(dest_hi, dest_hi, dest_lo, src1, src2);
1411   }
1412   void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
1413                              Register y, Register y_idx, Register z,
1414                              Register carry, Register product,
1415                              Register idx, Register kdx);
1416   void multiply_128_x_128_loop(Register y, Register z,
1417                                Register carry, Register carry2,
1418                                Register idx, Register jdx,
1419                                Register yz_idx1, Register yz_idx2,
1420                                Register tmp, Register tmp3, Register tmp4,
1421                                Register tmp7, Register product_hi);
1422   void kernel_crc32_using_crc32(Register crc, Register buf,
1423         Register len, Register tmp0, Register tmp1, Register tmp2,
1424         Register tmp3);
1425   void kernel_crc32c_using_crc32c(Register crc, Register buf,
1426         Register len, Register tmp0, Register tmp1, Register tmp2,
1427         Register tmp3);
1428 
1429   void ghash_modmul (FloatRegister result,
1430                      FloatRegister result_lo, FloatRegister result_hi, FloatRegister b,
1431                      FloatRegister a, FloatRegister vzr, FloatRegister a1_xor_a0, FloatRegister p,
1432                      FloatRegister t1, FloatRegister t2, FloatRegister t3);
1433   void ghash_load_wide(int index, Register data, FloatRegister result, FloatRegister state);
1434 public:
1435   void multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z,
1436                        Register zlen, Register tmp1, Register tmp2, Register tmp3,
1437                        Register tmp4, Register tmp5, Register tmp6, Register tmp7);
1438   void mul_add(Register out, Register in, Register offs, Register len, Register k);
1439   void ghash_multiply(FloatRegister result_lo, FloatRegister result_hi,
1440                       FloatRegister a, FloatRegister b, FloatRegister a1_xor_a0,
1441                       FloatRegister tmp1, FloatRegister tmp2, FloatRegister tmp3);
1442   void ghash_multiply_wide(int index,
1443                            FloatRegister result_lo, FloatRegister result_hi,
1444                            FloatRegister a, FloatRegister b, FloatRegister a1_xor_a0,
1445                            FloatRegister tmp1, FloatRegister tmp2, FloatRegister tmp3);
1446   void ghash_reduce(FloatRegister result, FloatRegister lo, FloatRegister hi,
1447                     FloatRegister p, FloatRegister z, FloatRegister t1);
1448   void ghash_reduce_wide(int index, FloatRegister result, FloatRegister lo, FloatRegister hi,
1449                     FloatRegister p, FloatRegister z, FloatRegister t1);
1450   void ghash_processBlocks_wide(address p, Register state, Register subkeyH,
1451                                 Register data, Register blocks, int unrolls);
1452 
1453 
1454   void aesenc_loadkeys(Register key, Register keylen);
1455   void aesecb_encrypt(Register from, Register to, Register keylen,
1456                       FloatRegister data = v0, int unrolls = 1);
1457   void aesecb_decrypt(Register from, Register to, Register key, Register keylen);
1458   void aes_round(FloatRegister input, FloatRegister subkey);
1459 
1460   // Place an ISB after code may have been modified due to a safepoint.
1461   void safepoint_isb();
1462 
1463 private:
1464   // Return the effective address r + (r1 << ext) + offset.
1465   // Uses rscratch2.
1466   Address offsetted_address(Register r, Register r1, Address::extend ext,
1467                             int offset, int size);
1468 
1469 private:
1470   // Returns an address on the stack which is reachable with a ldr/str of size
1471   // Uses rscratch2 if the address is not directly reachable
1472   Address spill_address(int size, int offset, Register tmp=rscratch2);
1473   Address sve_spill_address(int sve_reg_size_in_bytes, int offset, Register tmp=rscratch2);
1474 
1475   bool merge_alignment_check(Register base, size_t size, int64_t cur_offset, int64_t prev_offset) const;
1476 
1477   // Check whether two loads/stores can be merged into ldp/stp.
1478   bool ldst_can_merge(Register rx, const Address &adr, size_t cur_size_in_bytes, bool is_store) const;
1479 
1480   // Merge current load/store with previous load/store into ldp/stp.
1481   void merge_ldst(Register rx, const Address &adr, size_t cur_size_in_bytes, bool is_store);
1482 
1483   // Try to merge two loads/stores into ldp/stp. If success, returns true else false.
1484   bool try_merge_ldst(Register rt, const Address &adr, size_t cur_size_in_bytes, bool is_store);
1485 
1486 public:
1487   void spill(Register Rx, bool is64, int offset) {
1488     if (is64) {
1489       str(Rx, spill_address(8, offset));
1490     } else {
1491       strw(Rx, spill_address(4, offset));
1492     }
1493   }
1494   void spill(FloatRegister Vx, SIMD_RegVariant T, int offset) {
1495     str(Vx, T, spill_address(1 << (int)T, offset));
1496   }
1497 
1498   void spill_sve_vector(FloatRegister Zx, int offset, int vector_reg_size_in_bytes) {
1499     sve_str(Zx, sve_spill_address(vector_reg_size_in_bytes, offset));
1500   }
1501   void spill_sve_predicate(PRegister pr, int offset, int predicate_reg_size_in_bytes) {
1502     sve_str(pr, sve_spill_address(predicate_reg_size_in_bytes, offset));
1503   }
1504 
1505   void unspill(Register Rx, bool is64, int offset) {
1506     if (is64) {
1507       ldr(Rx, spill_address(8, offset));
1508     } else {
1509       ldrw(Rx, spill_address(4, offset));
1510     }
1511   }
1512   void unspill(FloatRegister Vx, SIMD_RegVariant T, int offset) {
1513     ldr(Vx, T, spill_address(1 << (int)T, offset));
1514   }
1515 
1516   void unspill_sve_vector(FloatRegister Zx, int offset, int vector_reg_size_in_bytes) {
1517     sve_ldr(Zx, sve_spill_address(vector_reg_size_in_bytes, offset));
1518   }
1519   void unspill_sve_predicate(PRegister pr, int offset, int predicate_reg_size_in_bytes) {
1520     sve_ldr(pr, sve_spill_address(predicate_reg_size_in_bytes, offset));
1521   }
1522 
1523   void spill_copy128(int src_offset, int dst_offset,
1524                      Register tmp1=rscratch1, Register tmp2=rscratch2) {
1525     if (src_offset < 512 && (src_offset & 7) == 0 &&
1526         dst_offset < 512 && (dst_offset & 7) == 0) {
1527       ldp(tmp1, tmp2, Address(sp, src_offset));
1528       stp(tmp1, tmp2, Address(sp, dst_offset));
1529     } else {
1530       unspill(tmp1, true, src_offset);
1531       spill(tmp1, true, dst_offset);
1532       unspill(tmp1, true, src_offset+8);
1533       spill(tmp1, true, dst_offset+8);
1534     }
1535   }
1536   void spill_copy_sve_vector_stack_to_stack(int src_offset, int dst_offset,
1537                                             int sve_vec_reg_size_in_bytes) {
1538     assert(sve_vec_reg_size_in_bytes % 16 == 0, "unexpected sve vector reg size");
1539     for (int i = 0; i < sve_vec_reg_size_in_bytes / 16; i++) {
1540       spill_copy128(src_offset, dst_offset);
1541       src_offset += 16;
1542       dst_offset += 16;
1543     }
1544   }
1545   void spill_copy_sve_predicate_stack_to_stack(int src_offset, int dst_offset,
1546                                                int sve_predicate_reg_size_in_bytes) {
1547     sve_ldr(ptrue, sve_spill_address(sve_predicate_reg_size_in_bytes, src_offset));
1548     sve_str(ptrue, sve_spill_address(sve_predicate_reg_size_in_bytes, dst_offset));
1549     reinitialize_ptrue();
1550   }
1551   void cache_wb(Address line);
1552   void cache_wbsync(bool is_pre);
1553 
1554   // Code for java.lang.Thread::onSpinWait() intrinsic.
1555   void spin_wait();
1556 
1557 private:
1558   // Check the current thread doesn't need a cross modify fence.
1559   void verify_cross_modify_fence_not_required() PRODUCT_RETURN;
1560 
1561 };
1562 
1563 #ifdef ASSERT
1564 inline bool AbstractAssembler::pd_check_instruction_mark() { return false; }
1565 #endif
1566 
1567 /**
1568  * class SkipIfEqual:
1569  *
1570  * Instantiating this class will result in assembly code being output that will
1571  * jump around any code emitted between the creation of the instance and it's
1572  * automatic destruction at the end of a scope block, depending on the value of
1573  * the flag passed to the constructor, which will be checked at run-time.
1574  */
1575 class SkipIfEqual {
1576  private:
1577   MacroAssembler* _masm;
1578   Label _label;
1579 
1580  public:
1581    SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
1582    ~SkipIfEqual();
1583 };
1584 
1585 struct tableswitch {
1586   Register _reg;
1587   int _insn_index; jint _first_key; jint _last_key;
1588   Label _after;
1589   Label _branches;
1590 };
1591 
1592 #endif // CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP