1 /*
   2  * Copyright (c) 1997, 2023, Oracle and/or its affiliates. All rights reserved.
   3  * Copyright (c) 2014, 2021, Red Hat Inc. All rights reserved.
   4  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   5  *
   6  * This code is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 only, as
   8  * published by the Free Software Foundation.
   9  *
  10  * This code is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  * version 2 for more details (a copy is included in the LICENSE file that
  14  * accompanied this code).
  15  *
  16  * You should have received a copy of the GNU General Public License version
  17  * 2 along with this work; if not, write to the Free Software Foundation,
  18  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  19  *
  20  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  21  * or visit www.oracle.com if you need additional information or have any
  22  * questions.
  23  *
  24  */
  25 
  26 #ifndef CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
  27 #define CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
  28 
  29 #include "asm/assembler.inline.hpp"
  30 #include "code/vmreg.hpp"
  31 #include "metaprogramming/enableIf.hpp"
  32 #include "oops/compressedOops.hpp"
  33 #include "oops/compressedKlass.hpp"
  34 #include "runtime/vm_version.hpp"
  35 #include "utilities/powerOfTwo.hpp"
  36 
  37 class OopMap;
  38 
  39 // MacroAssembler extends Assembler by frequently used macros.
  40 //
  41 // Instructions for which a 'better' code sequence exists depending
  42 // on arguments should also go in here.
  43 
  44 class MacroAssembler: public Assembler {
  45   friend class LIR_Assembler;
  46 
  47  public:
  48   using Assembler::mov;
  49   using Assembler::movi;
  50 
  51  protected:
  52 
  53   // Support for VM calls
  54   //
  55   // This is the base routine called by the different versions of call_VM_leaf. The interpreter
  56   // may customize this version by overriding it for its purposes (e.g., to save/restore
  57   // additional registers when doing a VM call).
  58   virtual void call_VM_leaf_base(
  59     address entry_point,               // the entry point
  60     int     number_of_arguments,        // the number of arguments to pop after the call
  61     Label *retaddr = nullptr
  62   );
  63 
  64   virtual void call_VM_leaf_base(
  65     address entry_point,               // the entry point
  66     int     number_of_arguments,        // the number of arguments to pop after the call
  67     Label &retaddr) {
  68     call_VM_leaf_base(entry_point, number_of_arguments, &retaddr);
  69   }
  70 
  71   // This is the base routine called by the different versions of call_VM. The interpreter
  72   // may customize this version by overriding it for its purposes (e.g., to save/restore
  73   // additional registers when doing a VM call).
  74   //
  75   // If no java_thread register is specified (noreg) than rthread will be used instead. call_VM_base
  76   // returns the register which contains the thread upon return. If a thread register has been
  77   // specified, the return value will correspond to that register. If no last_java_sp is specified
  78   // (noreg) than rsp will be used instead.
  79   virtual void call_VM_base(           // returns the register containing the thread upon return
  80     Register oop_result,               // where an oop-result ends up if any; use noreg otherwise
  81     Register java_thread,              // the thread if computed before     ; use noreg otherwise
  82     Register last_java_sp,             // to set up last_Java_frame in stubs; use noreg otherwise
  83     address  entry_point,              // the entry point
  84     int      number_of_arguments,      // the number of arguments (w/o thread) to pop after the call
  85     bool     check_exceptions          // whether to check for pending exceptions after return
  86   );
  87 
  88   void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
  89 
  90   enum KlassDecodeMode {
  91     KlassDecodeNone,
  92     KlassDecodeZero,
  93     KlassDecodeXor,
  94     KlassDecodeMovk
  95   };
  96 
  97   KlassDecodeMode klass_decode_mode();
  98 
  99  private:
 100   static KlassDecodeMode _klass_decode_mode;
 101 
 102  public:
 103   MacroAssembler(CodeBuffer* code) : Assembler(code) {}
 104 
 105  // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
 106  // The implementation is only non-empty for the InterpreterMacroAssembler,
 107  // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
 108  virtual void check_and_handle_popframe(Register java_thread);
 109  virtual void check_and_handle_earlyret(Register java_thread);
 110 
 111   void safepoint_poll(Label& slow_path, bool at_return, bool acquire, bool in_nmethod, Register tmp = rscratch1);
 112   void rt_call(address dest, Register tmp = rscratch1);
 113 
 114   // Load Effective Address
 115   void lea(Register r, const Address &a) {
 116     InstructionMark im(this);
 117     a.lea(this, r);
 118   }
 119 
 120   /* Sometimes we get misaligned loads and stores, usually from Unsafe
 121      accesses, and these can exceed the offset range. */
 122   Address legitimize_address(const Address &a, int size, Register scratch) {
 123     if (a.getMode() == Address::base_plus_offset) {
 124       if (! Address::offset_ok_for_immed(a.offset(), exact_log2(size))) {
 125         block_comment("legitimize_address {");
 126         lea(scratch, a);
 127         block_comment("} legitimize_address");
 128         return Address(scratch);
 129       }
 130     }
 131     return a;
 132   }
 133 
 134   void addmw(Address a, Register incr, Register scratch) {
 135     ldrw(scratch, a);
 136     addw(scratch, scratch, incr);
 137     strw(scratch, a);
 138   }
 139 
 140   // Add constant to memory word
 141   void addmw(Address a, int imm, Register scratch) {
 142     ldrw(scratch, a);
 143     if (imm > 0)
 144       addw(scratch, scratch, (unsigned)imm);
 145     else
 146       subw(scratch, scratch, (unsigned)-imm);
 147     strw(scratch, a);
 148   }
 149 
 150   void bind(Label& L) {
 151     Assembler::bind(L);
 152     code()->clear_last_insn();
 153   }
 154 
 155   void membar(Membar_mask_bits order_constraint);
 156 
 157   using Assembler::ldr;
 158   using Assembler::str;
 159   using Assembler::ldrw;
 160   using Assembler::strw;
 161 
 162   void ldr(Register Rx, const Address &adr);
 163   void ldrw(Register Rw, const Address &adr);
 164   void str(Register Rx, const Address &adr);
 165   void strw(Register Rx, const Address &adr);
 166 
 167   // Frame creation and destruction shared between JITs.
 168   void build_frame(int framesize);
 169   void remove_frame(int framesize);
 170 
 171   virtual void _call_Unimplemented(address call_site) {
 172     mov(rscratch2, call_site);
 173   }
 174 
 175 // Microsoft's MSVC team thinks that the __FUNCSIG__ is approximately (sympathy for calling conventions) equivalent to __PRETTY_FUNCTION__
 176 // Also, from Clang patch: "It is very similar to GCC's PRETTY_FUNCTION, except it prints the calling convention."
 177 // https://reviews.llvm.org/D3311
 178 
 179 #ifdef _WIN64
 180 #define call_Unimplemented() _call_Unimplemented((address)__FUNCSIG__)
 181 #else
 182 #define call_Unimplemented() _call_Unimplemented((address)__PRETTY_FUNCTION__)
 183 #endif
 184 
 185   // aliases defined in AARCH64 spec
 186 
 187   template<class T>
 188   inline void cmpw(Register Rd, T imm)  { subsw(zr, Rd, imm); }
 189 
 190   inline void cmp(Register Rd, unsigned char imm8)  { subs(zr, Rd, imm8); }
 191   inline void cmp(Register Rd, unsigned imm) = delete;
 192 
 193   template<class T>
 194   inline void cmnw(Register Rd, T imm) { addsw(zr, Rd, imm); }
 195 
 196   inline void cmn(Register Rd, unsigned char imm8)  { adds(zr, Rd, imm8); }
 197   inline void cmn(Register Rd, unsigned imm) = delete;
 198 
 199   void cset(Register Rd, Assembler::Condition cond) {
 200     csinc(Rd, zr, zr, ~cond);
 201   }
 202   void csetw(Register Rd, Assembler::Condition cond) {
 203     csincw(Rd, zr, zr, ~cond);
 204   }
 205 
 206   void cneg(Register Rd, Register Rn, Assembler::Condition cond) {
 207     csneg(Rd, Rn, Rn, ~cond);
 208   }
 209   void cnegw(Register Rd, Register Rn, Assembler::Condition cond) {
 210     csnegw(Rd, Rn, Rn, ~cond);
 211   }
 212 
 213   inline void movw(Register Rd, Register Rn) {
 214     if (Rd == sp || Rn == sp) {
 215       Assembler::addw(Rd, Rn, 0U);
 216     } else {
 217       orrw(Rd, zr, Rn);
 218     }
 219   }
 220   inline void mov(Register Rd, Register Rn) {
 221     assert(Rd != r31_sp && Rn != r31_sp, "should be");
 222     if (Rd == Rn) {
 223     } else if (Rd == sp || Rn == sp) {
 224       Assembler::add(Rd, Rn, 0U);
 225     } else {
 226       orr(Rd, zr, Rn);
 227     }
 228   }
 229 
 230   inline void moviw(Register Rd, unsigned imm) { orrw(Rd, zr, imm); }
 231   inline void movi(Register Rd, unsigned imm) { orr(Rd, zr, imm); }
 232 
 233   inline void tstw(Register Rd, Register Rn) { andsw(zr, Rd, Rn); }
 234   inline void tst(Register Rd, Register Rn) { ands(zr, Rd, Rn); }
 235 
 236   inline void tstw(Register Rd, uint64_t imm) { andsw(zr, Rd, imm); }
 237   inline void tst(Register Rd, uint64_t imm) { ands(zr, Rd, imm); }
 238 
 239   inline void bfiw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 240     bfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
 241   }
 242   inline void bfi(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 243     bfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
 244   }
 245 
 246   inline void bfxilw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 247     bfmw(Rd, Rn, lsb, (lsb + width - 1));
 248   }
 249   inline void bfxil(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 250     bfm(Rd, Rn, lsb , (lsb + width - 1));
 251   }
 252 
 253   inline void sbfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 254     sbfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
 255   }
 256   inline void sbfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 257     sbfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
 258   }
 259 
 260   inline void sbfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 261     sbfmw(Rd, Rn, lsb, (lsb + width - 1));
 262   }
 263   inline void sbfx(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 264     sbfm(Rd, Rn, lsb , (lsb + width - 1));
 265   }
 266 
 267   inline void ubfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 268     ubfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
 269   }
 270   inline void ubfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 271     ubfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
 272   }
 273 
 274   inline void ubfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 275     ubfmw(Rd, Rn, lsb, (lsb + width - 1));
 276   }
 277   inline void ubfx(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 278     ubfm(Rd, Rn, lsb , (lsb + width - 1));
 279   }
 280 
 281   inline void asrw(Register Rd, Register Rn, unsigned imm) {
 282     sbfmw(Rd, Rn, imm, 31);
 283   }
 284 
 285   inline void asr(Register Rd, Register Rn, unsigned imm) {
 286     sbfm(Rd, Rn, imm, 63);
 287   }
 288 
 289   inline void lslw(Register Rd, Register Rn, unsigned imm) {
 290     ubfmw(Rd, Rn, ((32 - imm) & 31), (31 - imm));
 291   }
 292 
 293   inline void lsl(Register Rd, Register Rn, unsigned imm) {
 294     ubfm(Rd, Rn, ((64 - imm) & 63), (63 - imm));
 295   }
 296 
 297   inline void lsrw(Register Rd, Register Rn, unsigned imm) {
 298     ubfmw(Rd, Rn, imm, 31);
 299   }
 300 
 301   inline void lsr(Register Rd, Register Rn, unsigned imm) {
 302     ubfm(Rd, Rn, imm, 63);
 303   }
 304 
 305   inline void rorw(Register Rd, Register Rn, unsigned imm) {
 306     extrw(Rd, Rn, Rn, imm);
 307   }
 308 
 309   inline void ror(Register Rd, Register Rn, unsigned imm) {
 310     extr(Rd, Rn, Rn, imm);
 311   }
 312 
 313   inline void sxtbw(Register Rd, Register Rn) {
 314     sbfmw(Rd, Rn, 0, 7);
 315   }
 316   inline void sxthw(Register Rd, Register Rn) {
 317     sbfmw(Rd, Rn, 0, 15);
 318   }
 319   inline void sxtb(Register Rd, Register Rn) {
 320     sbfm(Rd, Rn, 0, 7);
 321   }
 322   inline void sxth(Register Rd, Register Rn) {
 323     sbfm(Rd, Rn, 0, 15);
 324   }
 325   inline void sxtw(Register Rd, Register Rn) {
 326     sbfm(Rd, Rn, 0, 31);
 327   }
 328 
 329   inline void uxtbw(Register Rd, Register Rn) {
 330     ubfmw(Rd, Rn, 0, 7);
 331   }
 332   inline void uxthw(Register Rd, Register Rn) {
 333     ubfmw(Rd, Rn, 0, 15);
 334   }
 335   inline void uxtb(Register Rd, Register Rn) {
 336     ubfm(Rd, Rn, 0, 7);
 337   }
 338   inline void uxth(Register Rd, Register Rn) {
 339     ubfm(Rd, Rn, 0, 15);
 340   }
 341   inline void uxtw(Register Rd, Register Rn) {
 342     ubfm(Rd, Rn, 0, 31);
 343   }
 344 
 345   inline void cmnw(Register Rn, Register Rm) {
 346     addsw(zr, Rn, Rm);
 347   }
 348   inline void cmn(Register Rn, Register Rm) {
 349     adds(zr, Rn, Rm);
 350   }
 351 
 352   inline void cmpw(Register Rn, Register Rm) {
 353     subsw(zr, Rn, Rm);
 354   }
 355   inline void cmp(Register Rn, Register Rm) {
 356     subs(zr, Rn, Rm);
 357   }
 358 
 359   inline void negw(Register Rd, Register Rn) {
 360     subw(Rd, zr, Rn);
 361   }
 362 
 363   inline void neg(Register Rd, Register Rn) {
 364     sub(Rd, zr, Rn);
 365   }
 366 
 367   inline void negsw(Register Rd, Register Rn) {
 368     subsw(Rd, zr, Rn);
 369   }
 370 
 371   inline void negs(Register Rd, Register Rn) {
 372     subs(Rd, zr, Rn);
 373   }
 374 
 375   inline void cmnw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
 376     addsw(zr, Rn, Rm, kind, shift);
 377   }
 378   inline void cmn(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
 379     adds(zr, Rn, Rm, kind, shift);
 380   }
 381 
 382   inline void cmpw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
 383     subsw(zr, Rn, Rm, kind, shift);
 384   }
 385   inline void cmp(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
 386     subs(zr, Rn, Rm, kind, shift);
 387   }
 388 
 389   inline void negw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
 390     subw(Rd, zr, Rn, kind, shift);
 391   }
 392 
 393   inline void neg(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
 394     sub(Rd, zr, Rn, kind, shift);
 395   }
 396 
 397   inline void negsw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
 398     subsw(Rd, zr, Rn, kind, shift);
 399   }
 400 
 401   inline void negs(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
 402     subs(Rd, zr, Rn, kind, shift);
 403   }
 404 
 405   inline void mnegw(Register Rd, Register Rn, Register Rm) {
 406     msubw(Rd, Rn, Rm, zr);
 407   }
 408   inline void mneg(Register Rd, Register Rn, Register Rm) {
 409     msub(Rd, Rn, Rm, zr);
 410   }
 411 
 412   inline void mulw(Register Rd, Register Rn, Register Rm) {
 413     maddw(Rd, Rn, Rm, zr);
 414   }
 415   inline void mul(Register Rd, Register Rn, Register Rm) {
 416     madd(Rd, Rn, Rm, zr);
 417   }
 418 
 419   inline void smnegl(Register Rd, Register Rn, Register Rm) {
 420     smsubl(Rd, Rn, Rm, zr);
 421   }
 422   inline void smull(Register Rd, Register Rn, Register Rm) {
 423     smaddl(Rd, Rn, Rm, zr);
 424   }
 425 
 426   inline void umnegl(Register Rd, Register Rn, Register Rm) {
 427     umsubl(Rd, Rn, Rm, zr);
 428   }
 429   inline void umull(Register Rd, Register Rn, Register Rm) {
 430     umaddl(Rd, Rn, Rm, zr);
 431   }
 432 
 433 #define WRAP(INSN)                                                            \
 434   void INSN(Register Rd, Register Rn, Register Rm, Register Ra) {             \
 435     if (VM_Version::supports_a53mac() && Ra != zr)                            \
 436       nop();                                                                  \
 437     Assembler::INSN(Rd, Rn, Rm, Ra);                                          \
 438   }
 439 
 440   WRAP(madd) WRAP(msub) WRAP(maddw) WRAP(msubw)
 441   WRAP(smaddl) WRAP(smsubl) WRAP(umaddl) WRAP(umsubl)
 442 #undef WRAP
 443 
 444 
 445   // macro assembly operations needed for aarch64
 446 
 447   // first two private routines for loading 32 bit or 64 bit constants
 448 private:
 449 
 450   void mov_immediate64(Register dst, uint64_t imm64);
 451   void mov_immediate32(Register dst, uint32_t imm32);
 452 
 453   int push(unsigned int bitset, Register stack);
 454   int pop(unsigned int bitset, Register stack);
 455 
 456   int push_fp(unsigned int bitset, Register stack);
 457   int pop_fp(unsigned int bitset, Register stack);
 458 
 459   int push_p(unsigned int bitset, Register stack);
 460   int pop_p(unsigned int bitset, Register stack);
 461 
 462   void mov(Register dst, Address a);
 463 
 464 public:
 465   void push(RegSet regs, Register stack) { if (regs.bits()) push(regs.bits(), stack); }
 466   void pop(RegSet regs, Register stack) { if (regs.bits()) pop(regs.bits(), stack); }
 467 
 468   void push_fp(FloatRegSet regs, Register stack) { if (regs.bits()) push_fp(regs.bits(), stack); }
 469   void pop_fp(FloatRegSet regs, Register stack) { if (regs.bits()) pop_fp(regs.bits(), stack); }
 470 
 471   static RegSet call_clobbered_gp_registers();
 472 
 473   void push_p(PRegSet regs, Register stack) { if (regs.bits()) push_p(regs.bits(), stack); }
 474   void pop_p(PRegSet regs, Register stack) { if (regs.bits()) pop_p(regs.bits(), stack); }
 475 
 476   // Push and pop everything that might be clobbered by a native
 477   // runtime call except rscratch1 and rscratch2.  (They are always
 478   // scratch, so we don't have to protect them.)  Only save the lower
 479   // 64 bits of each vector register. Additional registers can be excluded
 480   // in a passed RegSet.
 481   void push_call_clobbered_registers_except(RegSet exclude);
 482   void pop_call_clobbered_registers_except(RegSet exclude);
 483 
 484   void push_call_clobbered_registers() {
 485     push_call_clobbered_registers_except(RegSet());
 486   }
 487   void pop_call_clobbered_registers() {
 488     pop_call_clobbered_registers_except(RegSet());
 489   }
 490 
 491 
 492   // now mov instructions for loading absolute addresses and 32 or
 493   // 64 bit integers
 494 
 495   inline void mov(Register dst, address addr)             { mov_immediate64(dst, (uint64_t)addr); }
 496 
 497   template<typename T, ENABLE_IF(std::is_integral<T>::value)>
 498   inline void mov(Register dst, T o)                      { mov_immediate64(dst, (uint64_t)o); }
 499 
 500   inline void movw(Register dst, uint32_t imm32)          { mov_immediate32(dst, imm32); }
 501 
 502   void mov(Register dst, RegisterOrConstant src) {
 503     if (src.is_register())
 504       mov(dst, src.as_register());
 505     else
 506       mov(dst, src.as_constant());
 507   }
 508 
 509   void movptr(Register r, uintptr_t imm64);
 510 
 511   void mov(FloatRegister Vd, SIMD_Arrangement T, uint64_t imm64);
 512 
 513   void mov(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) {
 514     orr(Vd, T, Vn, Vn);
 515   }
 516 
 517   void flt_to_flt16(Register dst, FloatRegister src, FloatRegister tmp) {
 518     fcvtsh(tmp, src);
 519     smov(dst, tmp, H, 0);
 520   }
 521 
 522   void flt16_to_flt(FloatRegister dst, Register src, FloatRegister tmp) {
 523     mov(tmp, H, 0, src);
 524     fcvths(dst, tmp);
 525   }
 526 
 527   // Generalized Test Bit And Branch, including a "far" variety which
 528   // spans more than 32KiB.
 529   void tbr(Condition cond, Register Rt, int bitpos, Label &dest, bool isfar = false) {
 530     assert(cond == EQ || cond == NE, "must be");
 531 
 532     if (isfar)
 533       cond = ~cond;
 534 
 535     void (Assembler::* branch)(Register Rt, int bitpos, Label &L);
 536     if (cond == Assembler::EQ)
 537       branch = &Assembler::tbz;
 538     else
 539       branch = &Assembler::tbnz;
 540 
 541     if (isfar) {
 542       Label L;
 543       (this->*branch)(Rt, bitpos, L);
 544       b(dest);
 545       bind(L);
 546     } else {
 547       (this->*branch)(Rt, bitpos, dest);
 548     }
 549   }
 550 
 551   // macro instructions for accessing and updating floating point
 552   // status register
 553   //
 554   // FPSR : op1 == 011
 555   //        CRn == 0100
 556   //        CRm == 0100
 557   //        op2 == 001
 558 
 559   inline void get_fpsr(Register reg)
 560   {
 561     mrs(0b11, 0b0100, 0b0100, 0b001, reg);
 562   }
 563 
 564   inline void set_fpsr(Register reg)
 565   {
 566     msr(0b011, 0b0100, 0b0100, 0b001, reg);
 567   }
 568 
 569   inline void clear_fpsr()
 570   {
 571     msr(0b011, 0b0100, 0b0100, 0b001, zr);
 572   }
 573 
 574   // DCZID_EL0: op1 == 011
 575   //            CRn == 0000
 576   //            CRm == 0000
 577   //            op2 == 111
 578   inline void get_dczid_el0(Register reg)
 579   {
 580     mrs(0b011, 0b0000, 0b0000, 0b111, reg);
 581   }
 582 
 583   // CTR_EL0:   op1 == 011
 584   //            CRn == 0000
 585   //            CRm == 0000
 586   //            op2 == 001
 587   inline void get_ctr_el0(Register reg)
 588   {
 589     mrs(0b011, 0b0000, 0b0000, 0b001, reg);
 590   }
 591 
 592   inline void get_nzcv(Register reg) {
 593     mrs(0b011, 0b0100, 0b0010, 0b000, reg);
 594   }
 595 
 596   inline void set_nzcv(Register reg) {
 597     msr(0b011, 0b0100, 0b0010, 0b000, reg);
 598   }
 599 
 600   // idiv variant which deals with MINLONG as dividend and -1 as divisor
 601   int corrected_idivl(Register result, Register ra, Register rb,
 602                       bool want_remainder, Register tmp = rscratch1);
 603   int corrected_idivq(Register result, Register ra, Register rb,
 604                       bool want_remainder, Register tmp = rscratch1);
 605 
 606   // Support for null-checks
 607   //
 608   // Generates code that causes a null OS exception if the content of reg is null.
 609   // If the accessed location is M[reg + offset] and the offset is known, provide the
 610   // offset. No explicit code generation is needed if the offset is within a certain
 611   // range (0 <= offset <= page_size).
 612 
 613   virtual void null_check(Register reg, int offset = -1);
 614   static bool needs_explicit_null_check(intptr_t offset);
 615   static bool uses_implicit_null_check(void* address);
 616 
 617   static address target_addr_for_insn(address insn_addr, unsigned insn);
 618   static address target_addr_for_insn_or_null(address insn_addr, unsigned insn);
 619   static address target_addr_for_insn(address insn_addr) {
 620     unsigned insn = *(unsigned*)insn_addr;
 621     return target_addr_for_insn(insn_addr, insn);
 622   }
 623   static address target_addr_for_insn_or_null(address insn_addr) {
 624     unsigned insn = *(unsigned*)insn_addr;
 625     return target_addr_for_insn_or_null(insn_addr, insn);
 626   }
 627 
 628   // Required platform-specific helpers for Label::patch_instructions.
 629   // They _shadow_ the declarations in AbstractAssembler, which are undefined.
 630   static int pd_patch_instruction_size(address branch, address target);
 631   static void pd_patch_instruction(address branch, address target, const char* file = nullptr, int line = 0) {
 632     pd_patch_instruction_size(branch, target);
 633   }
 634   static address pd_call_destination(address branch) {
 635     return target_addr_for_insn(branch);
 636   }
 637 #ifndef PRODUCT
 638   static void pd_print_patched_instruction(address branch);
 639 #endif
 640 
 641   static int patch_oop(address insn_addr, address o);
 642   static int patch_narrow_klass(address insn_addr, narrowKlass n);
 643 
 644   // Return whether code is emitted to a scratch blob.
 645   virtual bool in_scratch_emit_size() {
 646     return false;
 647   }
 648   address emit_trampoline_stub(int insts_call_instruction_offset, address target);
 649   static int max_trampoline_stub_size();
 650   void emit_static_call_stub();
 651   static int static_call_stub_size();
 652 
 653   // The following 4 methods return the offset of the appropriate move instruction
 654 
 655   // Support for fast byte/short loading with zero extension (depending on particular CPU)
 656   int load_unsigned_byte(Register dst, Address src);
 657   int load_unsigned_short(Register dst, Address src);
 658 
 659   // Support for fast byte/short loading with sign extension (depending on particular CPU)
 660   int load_signed_byte(Register dst, Address src);
 661   int load_signed_short(Register dst, Address src);
 662 
 663   int load_signed_byte32(Register dst, Address src);
 664   int load_signed_short32(Register dst, Address src);
 665 
 666   // Support for sign-extension (hi:lo = extend_sign(lo))
 667   void extend_sign(Register hi, Register lo);
 668 
 669   // Load and store values by size and signed-ness
 670   void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed);
 671   void store_sized_value(Address dst, Register src, size_t size_in_bytes);
 672 
 673   // Support for inc/dec with optimal instruction selection depending on value
 674 
 675   // x86_64 aliases an unqualified register/address increment and
 676   // decrement to call incrementq and decrementq but also supports
 677   // explicitly sized calls to incrementq/decrementq or
 678   // incrementl/decrementl
 679 
 680   // for aarch64 the proper convention would be to use
 681   // increment/decrement for 64 bit operations and
 682   // incrementw/decrementw for 32 bit operations. so when porting
 683   // x86_64 code we can leave calls to increment/decrement as is,
 684   // replace incrementq/decrementq with increment/decrement and
 685   // replace incrementl/decrementl with incrementw/decrementw.
 686 
 687   // n.b. increment/decrement calls with an Address destination will
 688   // need to use a scratch register to load the value to be
 689   // incremented. increment/decrement calls which add or subtract a
 690   // constant value greater than 2^12 will need to use a 2nd scratch
 691   // register to hold the constant. so, a register increment/decrement
 692   // may trash rscratch2 and an address increment/decrement trash
 693   // rscratch and rscratch2
 694 
 695   void decrementw(Address dst, int value = 1);
 696   void decrementw(Register reg, int value = 1);
 697 
 698   void decrement(Register reg, int value = 1);
 699   void decrement(Address dst, int value = 1);
 700 
 701   void incrementw(Address dst, int value = 1);
 702   void incrementw(Register reg, int value = 1);
 703 
 704   void increment(Register reg, int value = 1);
 705   void increment(Address dst, int value = 1);
 706 
 707 
 708   // Alignment
 709   void align(int modulus);
 710 
 711   // nop
 712   void post_call_nop();
 713 
 714   // Stack frame creation/removal
 715   void enter(bool strip_ret_addr = false);
 716   void leave();
 717 
 718   // ROP Protection
 719   void protect_return_address();
 720   void protect_return_address(Register return_reg, Register temp_reg);
 721   void authenticate_return_address(Register return_reg = lr);
 722   void authenticate_return_address(Register return_reg, Register temp_reg);
 723   void strip_return_address();
 724   void check_return_address(Register return_reg=lr) PRODUCT_RETURN;
 725 
 726   // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
 727   // The pointer will be loaded into the thread register.
 728   void get_thread(Register thread);
 729 
 730   // support for argument shuffling
 731   void move32_64(VMRegPair src, VMRegPair dst, Register tmp = rscratch1);
 732   void float_move(VMRegPair src, VMRegPair dst, Register tmp = rscratch1);
 733   void long_move(VMRegPair src, VMRegPair dst, Register tmp = rscratch1);
 734   void double_move(VMRegPair src, VMRegPair dst, Register tmp = rscratch1);
 735   void object_move(
 736                    OopMap* map,
 737                    int oop_handle_offset,
 738                    int framesize_in_slots,
 739                    VMRegPair src,
 740                    VMRegPair dst,
 741                    bool is_receiver,
 742                    int* receiver_offset);
 743 
 744 
 745   // Support for VM calls
 746   //
 747   // It is imperative that all calls into the VM are handled via the call_VM macros.
 748   // They make sure that the stack linkage is setup correctly. call_VM's correspond
 749   // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
 750 
 751 
 752   void call_VM(Register oop_result,
 753                address entry_point,
 754                bool check_exceptions = true);
 755   void call_VM(Register oop_result,
 756                address entry_point,
 757                Register arg_1,
 758                bool check_exceptions = true);
 759   void call_VM(Register oop_result,
 760                address entry_point,
 761                Register arg_1, Register arg_2,
 762                bool check_exceptions = true);
 763   void call_VM(Register oop_result,
 764                address entry_point,
 765                Register arg_1, Register arg_2, Register arg_3,
 766                bool check_exceptions = true);
 767 
 768   // Overloadings with last_Java_sp
 769   void call_VM(Register oop_result,
 770                Register last_java_sp,
 771                address entry_point,
 772                int number_of_arguments = 0,
 773                bool check_exceptions = true);
 774   void call_VM(Register oop_result,
 775                Register last_java_sp,
 776                address entry_point,
 777                Register arg_1, bool
 778                check_exceptions = true);
 779   void call_VM(Register oop_result,
 780                Register last_java_sp,
 781                address entry_point,
 782                Register arg_1, Register arg_2,
 783                bool check_exceptions = true);
 784   void call_VM(Register oop_result,
 785                Register last_java_sp,
 786                address entry_point,
 787                Register arg_1, Register arg_2, Register arg_3,
 788                bool check_exceptions = true);
 789 
 790   void get_vm_result  (Register oop_result, Register thread);
 791   void get_vm_result_2(Register metadata_result, Register thread);
 792 
 793   // These always tightly bind to MacroAssembler::call_VM_base
 794   // bypassing the virtual implementation
 795   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
 796   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
 797   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
 798   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
 799   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
 800 
 801   void call_VM_leaf(address entry_point,
 802                     int number_of_arguments = 0);
 803   void call_VM_leaf(address entry_point,
 804                     Register arg_1);
 805   void call_VM_leaf(address entry_point,
 806                     Register arg_1, Register arg_2);
 807   void call_VM_leaf(address entry_point,
 808                     Register arg_1, Register arg_2, Register arg_3);
 809 
 810   // These always tightly bind to MacroAssembler::call_VM_leaf_base
 811   // bypassing the virtual implementation
 812   void super_call_VM_leaf(address entry_point);
 813   void super_call_VM_leaf(address entry_point, Register arg_1);
 814   void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
 815   void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
 816   void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
 817 
 818   // last Java Frame (fills frame anchor)
 819   void set_last_Java_frame(Register last_java_sp,
 820                            Register last_java_fp,
 821                            address last_java_pc,
 822                            Register scratch);
 823 
 824   void set_last_Java_frame(Register last_java_sp,
 825                            Register last_java_fp,
 826                            Label &last_java_pc,
 827                            Register scratch);
 828 
 829   void set_last_Java_frame(Register last_java_sp,
 830                            Register last_java_fp,
 831                            Register last_java_pc,
 832                            Register scratch);
 833 
 834   void reset_last_Java_frame(Register thread);
 835 
 836   // thread in the default location (rthread)
 837   void reset_last_Java_frame(bool clear_fp);
 838 
 839   // Stores
 840   void store_check(Register obj);                // store check for obj - register is destroyed afterwards
 841   void store_check(Register obj, Address dst);   // same as above, dst is exact store location (reg. is destroyed)
 842 
 843   void resolve_jobject(Register value, Register tmp1, Register tmp2);
 844   void resolve_global_jobject(Register value, Register tmp1, Register tmp2);
 845 
 846   // C 'boolean' to Java boolean: x == 0 ? 0 : 1
 847   void c2bool(Register x);
 848 
 849   void load_method_holder_cld(Register rresult, Register rmethod);
 850   void load_method_holder(Register holder, Register method);
 851 
 852   // oop manipulations
 853   void load_nklass(Register dst, Register src);
 854   void load_klass(Register dst, Register src);
 855   void store_klass(Register dst, Register src);
 856   void cmp_klass(Register oop, Register trial_klass, Register tmp);
 857 
 858   void resolve_weak_handle(Register result, Register tmp1, Register tmp2);
 859   void resolve_oop_handle(Register result, Register tmp1, Register tmp2);
 860   void load_mirror(Register dst, Register method, Register tmp1, Register tmp2);
 861 
 862   void access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
 863                       Register tmp1, Register tmp2);
 864 
 865   void access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register val,
 866                        Register tmp1, Register tmp2, Register tmp3);
 867 
 868   void load_heap_oop(Register dst, Address src, Register tmp1,
 869                      Register tmp2, DecoratorSet decorators = 0);
 870 
 871   void load_heap_oop_not_null(Register dst, Address src, Register tmp1,
 872                               Register tmp2, DecoratorSet decorators = 0);
 873   void store_heap_oop(Address dst, Register val, Register tmp1,
 874                       Register tmp2, Register tmp3, DecoratorSet decorators = 0);
 875 
 876   // currently unimplemented
 877   // Used for storing null. All other oop constants should be
 878   // stored using routines that take a jobject.
 879   void store_heap_oop_null(Address dst);
 880 
 881   void store_klass_gap(Register dst, Register src);
 882 
 883   // This dummy is to prevent a call to store_heap_oop from
 884   // converting a zero (like null) into a Register by giving
 885   // the compiler two choices it can't resolve
 886 
 887   void store_heap_oop(Address dst, void* dummy);
 888 
 889   void encode_heap_oop(Register d, Register s);
 890   void encode_heap_oop(Register r) { encode_heap_oop(r, r); }
 891   void decode_heap_oop(Register d, Register s);
 892   void decode_heap_oop(Register r) { decode_heap_oop(r, r); }
 893   void encode_heap_oop_not_null(Register r);
 894   void decode_heap_oop_not_null(Register r);
 895   void encode_heap_oop_not_null(Register dst, Register src);
 896   void decode_heap_oop_not_null(Register dst, Register src);
 897 
 898   void set_narrow_oop(Register dst, jobject obj);
 899 
 900   void encode_klass_not_null(Register r);
 901   void decode_klass_not_null(Register r);
 902   void encode_klass_not_null(Register dst, Register src);
 903   void decode_klass_not_null(Register dst, Register src);
 904 
 905   void set_narrow_klass(Register dst, Klass* k);
 906 
 907   // if heap base register is used - reinit it with the correct value
 908   void reinit_heapbase();
 909 
 910   DEBUG_ONLY(void verify_heapbase(const char* msg);)
 911 
 912   void push_CPU_state(bool save_vectors = false, bool use_sve = false,
 913                       int sve_vector_size_in_bytes = 0, int total_predicate_in_bytes = 0);
 914   void pop_CPU_state(bool restore_vectors = false, bool use_sve = false,
 915                      int sve_vector_size_in_bytes = 0, int total_predicate_in_bytes = 0);
 916 
 917   void push_cont_fastpath(Register java_thread);
 918   void pop_cont_fastpath(Register java_thread);
 919 
 920   // Round up to a power of two
 921   void round_to(Register reg, int modulus);
 922 
 923   // java.lang.Math::round intrinsics
 924   void java_round_double(Register dst, FloatRegister src, FloatRegister ftmp);
 925   void java_round_float(Register dst, FloatRegister src, FloatRegister ftmp);
 926 
 927   // allocation
 928   void tlab_allocate(
 929     Register obj,                      // result: pointer to object after successful allocation
 930     Register var_size_in_bytes,        // object size in bytes if unknown at compile time; invalid otherwise
 931     int      con_size_in_bytes,        // object size in bytes if   known at compile time
 932     Register t1,                       // temp register
 933     Register t2,                       // temp register
 934     Label&   slow_case                 // continuation point if fast allocation fails
 935   );
 936   void verify_tlab();
 937 
 938   // interface method calling
 939   void lookup_interface_method(Register recv_klass,
 940                                Register intf_klass,
 941                                RegisterOrConstant itable_index,
 942                                Register method_result,
 943                                Register scan_temp,
 944                                Label& no_such_interface,
 945                    bool return_method = true);
 946 
 947   // virtual method calling
 948   // n.b. x86 allows RegisterOrConstant for vtable_index
 949   void lookup_virtual_method(Register recv_klass,
 950                              RegisterOrConstant vtable_index,
 951                              Register method_result);
 952 
 953   // Test sub_klass against super_klass, with fast and slow paths.
 954 
 955   // The fast path produces a tri-state answer: yes / no / maybe-slow.
 956   // One of the three labels can be null, meaning take the fall-through.
 957   // If super_check_offset is -1, the value is loaded up from super_klass.
 958   // No registers are killed, except temp_reg.
 959   void check_klass_subtype_fast_path(Register sub_klass,
 960                                      Register super_klass,
 961                                      Register temp_reg,
 962                                      Label* L_success,
 963                                      Label* L_failure,
 964                                      Label* L_slow_path,
 965                 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
 966 
 967   // The rest of the type check; must be wired to a corresponding fast path.
 968   // It does not repeat the fast path logic, so don't use it standalone.
 969   // The temp_reg and temp2_reg can be noreg, if no temps are available.
 970   // Updates the sub's secondary super cache as necessary.
 971   // If set_cond_codes, condition codes will be Z on success, NZ on failure.
 972   void check_klass_subtype_slow_path(Register sub_klass,
 973                                      Register super_klass,
 974                                      Register temp_reg,
 975                                      Register temp2_reg,
 976                                      Label* L_success,
 977                                      Label* L_failure,
 978                                      bool set_cond_codes = false);
 979 
 980   // Simplified, combined version, good for typical uses.
 981   // Falls through on failure.
 982   void check_klass_subtype(Register sub_klass,
 983                            Register super_klass,
 984                            Register temp_reg,
 985                            Label& L_success);
 986 
 987   void clinit_barrier(Register klass,
 988                       Register thread,
 989                       Label* L_fast_path = nullptr,
 990                       Label* L_slow_path = nullptr);
 991 
 992   Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
 993 
 994   void verify_sve_vector_length(Register tmp = rscratch1);
 995   void reinitialize_ptrue() {
 996     if (UseSVE > 0) {
 997       sve_ptrue(ptrue, B);
 998     }
 999   }
1000   void verify_ptrue();
1001 
1002   // Debugging
1003 
1004   // only if +VerifyOops
1005   void _verify_oop(Register reg, const char* s, const char* file, int line);
1006   void _verify_oop_addr(Address addr, const char * s, const char* file, int line);
1007 
1008   void _verify_oop_checked(Register reg, const char* s, const char* file, int line) {
1009     if (VerifyOops) {
1010       _verify_oop(reg, s, file, line);
1011     }
1012   }
1013   void _verify_oop_addr_checked(Address reg, const char* s, const char* file, int line) {
1014     if (VerifyOops) {
1015       _verify_oop_addr(reg, s, file, line);
1016     }
1017   }
1018 
1019 // TODO: verify method and klass metadata (compare against vptr?)
1020   void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
1021   void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
1022 
1023 #define verify_oop(reg) _verify_oop_checked(reg, "broken oop " #reg, __FILE__, __LINE__)
1024 #define verify_oop_msg(reg, msg) _verify_oop_checked(reg, "broken oop " #reg ", " #msg, __FILE__, __LINE__)
1025 #define verify_oop_addr(addr) _verify_oop_addr_checked(addr, "broken oop addr " #addr, __FILE__, __LINE__)
1026 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
1027 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
1028 
1029   // only if +VerifyFPU
1030   void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
1031 
1032   // prints msg, dumps registers and stops execution
1033   void stop(const char* msg);
1034 
1035   static void debug64(char* msg, int64_t pc, int64_t regs[]);
1036 
1037   void untested()                                { stop("untested"); }
1038 
1039   void unimplemented(const char* what = "");
1040 
1041   void should_not_reach_here()                   { stop("should not reach here"); }
1042 
1043   void _assert_asm(Condition cc, const char* msg);
1044 #define assert_asm0(cc, msg) _assert_asm(cc, FILE_AND_LINE ": " msg)
1045 #define assert_asm(masm, command, cc, msg) DEBUG_ONLY(command; (masm)->_assert_asm(cc, FILE_AND_LINE ": " #command " " #cc ": " msg))
1046 
1047   // Stack overflow checking
1048   void bang_stack_with_offset(int offset) {
1049     // stack grows down, caller passes positive offset
1050     assert(offset > 0, "must bang with negative offset");
1051     sub(rscratch2, sp, offset);
1052     str(zr, Address(rscratch2));
1053   }
1054 
1055   // Writes to stack successive pages until offset reached to check for
1056   // stack overflow + shadow pages.  Also, clobbers tmp
1057   void bang_stack_size(Register size, Register tmp);
1058 
1059   // Check for reserved stack access in method being exited (for JIT)
1060   void reserved_stack_check();
1061 
1062   // Arithmetics
1063 
1064   void addptr(const Address &dst, int32_t src);
1065   void cmpptr(Register src1, Address src2);
1066 
1067   void cmpoop(Register obj1, Register obj2);
1068 
1069   // Various forms of CAS
1070 
1071   void cmpxchg_obj_header(Register oldv, Register newv, Register obj, Register tmp,
1072                           Label &succeed, Label *fail);
1073   void cmpxchgptr(Register oldv, Register newv, Register addr, Register tmp,
1074                   Label &succeed, Label *fail);
1075 
1076   void cmpxchgw(Register oldv, Register newv, Register addr, Register tmp,
1077                   Label &succeed, Label *fail);
1078 
1079   void atomic_add(Register prev, RegisterOrConstant incr, Register addr);
1080   void atomic_addw(Register prev, RegisterOrConstant incr, Register addr);
1081   void atomic_addal(Register prev, RegisterOrConstant incr, Register addr);
1082   void atomic_addalw(Register prev, RegisterOrConstant incr, Register addr);
1083 
1084   void atomic_xchg(Register prev, Register newv, Register addr);
1085   void atomic_xchgw(Register prev, Register newv, Register addr);
1086   void atomic_xchgl(Register prev, Register newv, Register addr);
1087   void atomic_xchglw(Register prev, Register newv, Register addr);
1088   void atomic_xchgal(Register prev, Register newv, Register addr);
1089   void atomic_xchgalw(Register prev, Register newv, Register addr);
1090 
1091   void orptr(Address adr, RegisterOrConstant src) {
1092     ldr(rscratch1, adr);
1093     if (src.is_register())
1094       orr(rscratch1, rscratch1, src.as_register());
1095     else
1096       orr(rscratch1, rscratch1, src.as_constant());
1097     str(rscratch1, adr);
1098   }
1099 
1100   // A generic CAS; success or failure is in the EQ flag.
1101   // Clobbers rscratch1
1102   void cmpxchg(Register addr, Register expected, Register new_val,
1103                enum operand_size size,
1104                bool acquire, bool release, bool weak,
1105                Register result);
1106 
1107 #ifdef ASSERT
1108   // Template short-hand support to clean-up after a failed call to trampoline
1109   // call generation (see trampoline_call() below),  when a set of Labels must
1110   // be reset (before returning).
1111   template<typename Label, typename... More>
1112   void reset_labels(Label &lbl, More&... more) {
1113     lbl.reset(); reset_labels(more...);
1114   }
1115   template<typename Label>
1116   void reset_labels(Label &lbl) {
1117     lbl.reset();
1118   }
1119 #endif
1120 
1121 private:
1122   void compare_eq(Register rn, Register rm, enum operand_size size);
1123 
1124 public:
1125   // AArch64 OpenJDK uses four different types of calls:
1126   //   - direct call: bl pc_relative_offset
1127   //     This is the shortest and the fastest, but the offset has the range:
1128   //     +/-128MB for the release build, +/-2MB for the debug build.
1129   //
1130   //   - far call: adrp reg, pc_relative_offset; add; bl reg
1131   //     This is longer than a direct call. The offset has
1132   //     the range +/-4GB. As the code cache size is limited to 4GB,
1133   //     far calls can reach anywhere in the code cache. If a jump is
1134   //     needed rather than a call, a far jump 'b reg' can be used instead.
1135   //     All instructions are embedded at a call site.
1136   //
1137   //   - trampoline call:
1138   //     This is only available in C1/C2-generated code (nmethod). It is a combination
1139   //     of a direct call, which is used if the destination of a call is in range,
1140   //     and a register-indirect call. It has the advantages of reaching anywhere in
1141   //     the AArch64 address space and being patchable at runtime when the generated
1142   //     code is being executed by other threads.
1143   //
1144   //     [Main code section]
1145   //       bl trampoline
1146   //     [Stub code section]
1147   //     trampoline:
1148   //       ldr reg, pc + 8
1149   //       br reg
1150   //       <64-bit destination address>
1151   //
1152   //     If the destination is in range when the generated code is moved to the code
1153   //     cache, 'bl trampoline' is replaced with 'bl destination' and the trampoline
1154   //     is not used.
1155   //     The optimization does not remove the trampoline from the stub section.
1156   //     This is necessary because the trampoline may well be redirected later when
1157   //     code is patched, and the new destination may not be reachable by a simple BR
1158   //     instruction.
1159   //
1160   //   - indirect call: move reg, address; blr reg
1161   //     This too can reach anywhere in the address space, but it cannot be
1162   //     patched while code is running, so it must only be modified at a safepoint.
1163   //     This form of call is most suitable for targets at fixed addresses, which
1164   //     will never be patched.
1165   //
1166   // The patching we do conforms to the "Concurrent modification and
1167   // execution of instructions" section of the Arm Architectural
1168   // Reference Manual, which only allows B, BL, BRK, HVC, ISB, NOP, SMC,
1169   // or SVC instructions to be modified while another thread is
1170   // executing them.
1171   //
1172   // To patch a trampoline call when the BL can't reach, we first modify
1173   // the 64-bit destination address in the trampoline, then modify the
1174   // BL to point to the trampoline, then flush the instruction cache to
1175   // broadcast the change to all executing threads. See
1176   // NativeCall::set_destination_mt_safe for the details.
1177   //
1178   // There is a benign race in that the other thread might observe the
1179   // modified BL before it observes the modified 64-bit destination
1180   // address. That does not matter because the destination method has been
1181   // invalidated, so there will be a trap at its start.
1182   // For this to work, the destination address in the trampoline is
1183   // always updated, even if we're not using the trampoline.
1184 
1185   // Emit a direct call if the entry address will always be in range,
1186   // otherwise a trampoline call.
1187   // Supported entry.rspec():
1188   // - relocInfo::runtime_call_type
1189   // - relocInfo::opt_virtual_call_type
1190   // - relocInfo::static_call_type
1191   // - relocInfo::virtual_call_type
1192   //
1193   // Return: the call PC or null if CodeCache is full.
1194   address trampoline_call(Address entry);
1195 
1196   static bool far_branches() {
1197     return ReservedCodeCacheSize > branch_range;
1198   }
1199 
1200   // Check if branches to the non nmethod section require a far jump
1201   static bool codestub_branch_needs_far_jump() {
1202     return CodeCache::max_distance_to_non_nmethod() > branch_range;
1203   }
1204 
1205   // Emit a direct call/jump if the entry address will always be in range,
1206   // otherwise a far call/jump.
1207   // The address must be inside the code cache.
1208   // Supported entry.rspec():
1209   // - relocInfo::external_word_type
1210   // - relocInfo::runtime_call_type
1211   // - relocInfo::none
1212   // In the case of a far call/jump, the entry address is put in the tmp register.
1213   // The tmp register is invalidated.
1214   //
1215   // Far_jump returns the amount of the emitted code.
1216   void far_call(Address entry, Register tmp = rscratch1);
1217   int far_jump(Address entry, Register tmp = rscratch1);
1218 
1219   static int far_codestub_branch_size() {
1220     if (codestub_branch_needs_far_jump()) {
1221       return 3 * 4;  // adrp, add, br
1222     } else {
1223       return 4;
1224     }
1225   }
1226 
1227   // Emit the CompiledIC call idiom
1228   address ic_call(address entry, jint method_index = 0);
1229 
1230 public:
1231 
1232   // Data
1233 
1234   void mov_metadata(Register dst, Metadata* obj);
1235   Address allocate_metadata_address(Metadata* obj);
1236   Address constant_oop_address(jobject obj);
1237 
1238   void movoop(Register dst, jobject obj);
1239 
1240   // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
1241   void kernel_crc32(Register crc, Register buf, Register len,
1242         Register table0, Register table1, Register table2, Register table3,
1243         Register tmp, Register tmp2, Register tmp3);
1244   // CRC32 code for java.util.zip.CRC32C::updateBytes() intrinsic.
1245   void kernel_crc32c(Register crc, Register buf, Register len,
1246         Register table0, Register table1, Register table2, Register table3,
1247         Register tmp, Register tmp2, Register tmp3);
1248 
1249   // Stack push and pop individual 64 bit registers
1250   void push(Register src);
1251   void pop(Register dst);
1252 
1253   void repne_scan(Register addr, Register value, Register count,
1254                   Register scratch);
1255   void repne_scanw(Register addr, Register value, Register count,
1256                    Register scratch);
1257 
1258   typedef void (MacroAssembler::* add_sub_imm_insn)(Register Rd, Register Rn, unsigned imm);
1259   typedef void (MacroAssembler::* add_sub_reg_insn)(Register Rd, Register Rn, Register Rm, enum shift_kind kind, unsigned shift);
1260 
1261   // If a constant does not fit in an immediate field, generate some
1262   // number of MOV instructions and then perform the operation
1263   void wrap_add_sub_imm_insn(Register Rd, Register Rn, uint64_t imm,
1264                              add_sub_imm_insn insn1,
1265                              add_sub_reg_insn insn2, bool is32);
1266   // Separate vsn which sets the flags
1267   void wrap_adds_subs_imm_insn(Register Rd, Register Rn, uint64_t imm,
1268                                add_sub_imm_insn insn1,
1269                                add_sub_reg_insn insn2, bool is32);
1270 
1271 #define WRAP(INSN, is32)                                                \
1272   void INSN(Register Rd, Register Rn, uint64_t imm) {                   \
1273     wrap_add_sub_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN, is32); \
1274   }                                                                     \
1275                                                                         \
1276   void INSN(Register Rd, Register Rn, Register Rm,                      \
1277              enum shift_kind kind, unsigned shift = 0) {                \
1278     Assembler::INSN(Rd, Rn, Rm, kind, shift);                           \
1279   }                                                                     \
1280                                                                         \
1281   void INSN(Register Rd, Register Rn, Register Rm) {                    \
1282     Assembler::INSN(Rd, Rn, Rm);                                        \
1283   }                                                                     \
1284                                                                         \
1285   void INSN(Register Rd, Register Rn, Register Rm,                      \
1286            ext::operation option, int amount = 0) {                     \
1287     Assembler::INSN(Rd, Rn, Rm, option, amount);                        \
1288   }
1289 
1290   WRAP(add, false) WRAP(addw, true) WRAP(sub, false) WRAP(subw, true)
1291 
1292 #undef WRAP
1293 #define WRAP(INSN, is32)                                                \
1294   void INSN(Register Rd, Register Rn, uint64_t imm) {                   \
1295     wrap_adds_subs_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN, is32); \
1296   }                                                                     \
1297                                                                         \
1298   void INSN(Register Rd, Register Rn, Register Rm,                      \
1299              enum shift_kind kind, unsigned shift = 0) {                \
1300     Assembler::INSN(Rd, Rn, Rm, kind, shift);                           \
1301   }                                                                     \
1302                                                                         \
1303   void INSN(Register Rd, Register Rn, Register Rm) {                    \
1304     Assembler::INSN(Rd, Rn, Rm);                                        \
1305   }                                                                     \
1306                                                                         \
1307   void INSN(Register Rd, Register Rn, Register Rm,                      \
1308            ext::operation option, int amount = 0) {                     \
1309     Assembler::INSN(Rd, Rn, Rm, option, amount);                        \
1310   }
1311 
1312   WRAP(adds, false) WRAP(addsw, true) WRAP(subs, false) WRAP(subsw, true)
1313 
1314   void add(Register Rd, Register Rn, RegisterOrConstant increment);
1315   void addw(Register Rd, Register Rn, RegisterOrConstant increment);
1316   void sub(Register Rd, Register Rn, RegisterOrConstant decrement);
1317   void subw(Register Rd, Register Rn, RegisterOrConstant decrement);
1318 
1319   void adrp(Register reg1, const Address &dest, uint64_t &byte_offset);
1320 
1321   void tableswitch(Register index, jint lowbound, jint highbound,
1322                    Label &jumptable, Label &jumptable_end, int stride = 1) {
1323     adr(rscratch1, jumptable);
1324     subsw(rscratch2, index, lowbound);
1325     subsw(zr, rscratch2, highbound - lowbound);
1326     br(Assembler::HS, jumptable_end);
1327     add(rscratch1, rscratch1, rscratch2,
1328         ext::sxtw, exact_log2(stride * Assembler::instruction_size));
1329     br(rscratch1);
1330   }
1331 
1332   // Form an address from base + offset in Rd.  Rd may or may not
1333   // actually be used: you must use the Address that is returned.  It
1334   // is up to you to ensure that the shift provided matches the size
1335   // of your data.
1336   Address form_address(Register Rd, Register base, int64_t byte_offset, int shift);
1337 
1338   // Return true iff an address is within the 48-bit AArch64 address
1339   // space.
1340   bool is_valid_AArch64_address(address a) {
1341     return ((uint64_t)a >> 48) == 0;
1342   }
1343 
1344   // Load the base of the cardtable byte map into reg.
1345   void load_byte_map_base(Register reg);
1346 
1347   // Prolog generator routines to support switch between x86 code and
1348   // generated ARM code
1349 
1350   // routine to generate an x86 prolog for a stub function which
1351   // bootstraps into the generated ARM code which directly follows the
1352   // stub
1353   //
1354 
1355   public:
1356 
1357   void ldr_constant(Register dest, const Address &const_addr) {
1358     if (NearCpool) {
1359       ldr(dest, const_addr);
1360     } else {
1361       uint64_t offset;
1362       adrp(dest, InternalAddress(const_addr.target()), offset);
1363       ldr(dest, Address(dest, offset));
1364     }
1365   }
1366 
1367   address read_polling_page(Register r, relocInfo::relocType rtype);
1368   void get_polling_page(Register dest, relocInfo::relocType rtype);
1369 
1370   // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
1371   void update_byte_crc32(Register crc, Register val, Register table);
1372   void update_word_crc32(Register crc, Register v, Register tmp,
1373         Register table0, Register table1, Register table2, Register table3,
1374         bool upper = false);
1375 
1376   address count_positives(Register ary1, Register len, Register result);
1377 
1378   address arrays_equals(Register a1, Register a2, Register result, Register cnt1,
1379                         Register tmp1, Register tmp2, Register tmp3, int elem_size);
1380 
1381   void string_equals(Register a1, Register a2, Register result, Register cnt1,
1382                      int elem_size);
1383 
1384   void fill_words(Register base, Register cnt, Register value);
1385   address zero_words(Register base, uint64_t cnt);
1386   address zero_words(Register ptr, Register cnt);
1387   void zero_dcache_blocks(Register base, Register cnt);
1388 
1389   static const int zero_words_block_size;
1390 
1391   address byte_array_inflate(Register src, Register dst, Register len,
1392                              FloatRegister vtmp1, FloatRegister vtmp2,
1393                              FloatRegister vtmp3, Register tmp4);
1394 
1395   void char_array_compress(Register src, Register dst, Register len,
1396                            Register res,
1397                            FloatRegister vtmp0, FloatRegister vtmp1,
1398                            FloatRegister vtmp2, FloatRegister vtmp3,
1399                            FloatRegister vtmp4, FloatRegister vtmp5);
1400 
1401   void encode_iso_array(Register src, Register dst,
1402                         Register len, Register res, bool ascii,
1403                         FloatRegister vtmp0, FloatRegister vtmp1,
1404                         FloatRegister vtmp2, FloatRegister vtmp3,
1405                         FloatRegister vtmp4, FloatRegister vtmp5);
1406 
1407   void fast_log(FloatRegister vtmp0, FloatRegister vtmp1, FloatRegister vtmp2,
1408                 FloatRegister vtmp3, FloatRegister vtmp4, FloatRegister vtmp5,
1409                 FloatRegister tmpC1, FloatRegister tmpC2, FloatRegister tmpC3,
1410                 FloatRegister tmpC4, Register tmp1, Register tmp2,
1411                 Register tmp3, Register tmp4, Register tmp5);
1412   void generate_dsin_dcos(bool isCos, address npio2_hw, address two_over_pi,
1413       address pio2, address dsin_coef, address dcos_coef);
1414  private:
1415   // begin trigonometric functions support block
1416   void generate__ieee754_rem_pio2(address npio2_hw, address two_over_pi, address pio2);
1417   void generate__kernel_rem_pio2(address two_over_pi, address pio2);
1418   void generate_kernel_sin(FloatRegister x, bool iyIsOne, address dsin_coef);
1419   void generate_kernel_cos(FloatRegister x, address dcos_coef);
1420   // end trigonometric functions support block
1421   void add2_with_carry(Register final_dest_hi, Register dest_hi, Register dest_lo,
1422                        Register src1, Register src2);
1423   void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
1424     add2_with_carry(dest_hi, dest_hi, dest_lo, src1, src2);
1425   }
1426   void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
1427                              Register y, Register y_idx, Register z,
1428                              Register carry, Register product,
1429                              Register idx, Register kdx);
1430   void multiply_128_x_128_loop(Register y, Register z,
1431                                Register carry, Register carry2,
1432                                Register idx, Register jdx,
1433                                Register yz_idx1, Register yz_idx2,
1434                                Register tmp, Register tmp3, Register tmp4,
1435                                Register tmp7, Register product_hi);
1436   void kernel_crc32_using_crypto_pmull(Register crc, Register buf,
1437         Register len, Register tmp0, Register tmp1, Register tmp2,
1438         Register tmp3);
1439   void kernel_crc32_using_crc32(Register crc, Register buf,
1440         Register len, Register tmp0, Register tmp1, Register tmp2,
1441         Register tmp3);
1442   void kernel_crc32c_using_crypto_pmull(Register crc, Register buf,
1443         Register len, Register tmp0, Register tmp1, Register tmp2,
1444         Register tmp3);
1445   void kernel_crc32c_using_crc32c(Register crc, Register buf,
1446         Register len, Register tmp0, Register tmp1, Register tmp2,
1447         Register tmp3);
1448   void kernel_crc32_common_fold_using_crypto_pmull(Register crc, Register buf,
1449         Register len, Register tmp0, Register tmp1, Register tmp2,
1450         size_t table_offset);
1451 
1452   void ghash_modmul (FloatRegister result,
1453                      FloatRegister result_lo, FloatRegister result_hi, FloatRegister b,
1454                      FloatRegister a, FloatRegister vzr, FloatRegister a1_xor_a0, FloatRegister p,
1455                      FloatRegister t1, FloatRegister t2, FloatRegister t3);
1456   void ghash_load_wide(int index, Register data, FloatRegister result, FloatRegister state);
1457 public:
1458   void multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z,
1459                        Register zlen, Register tmp1, Register tmp2, Register tmp3,
1460                        Register tmp4, Register tmp5, Register tmp6, Register tmp7);
1461   void mul_add(Register out, Register in, Register offs, Register len, Register k);
1462   void ghash_multiply(FloatRegister result_lo, FloatRegister result_hi,
1463                       FloatRegister a, FloatRegister b, FloatRegister a1_xor_a0,
1464                       FloatRegister tmp1, FloatRegister tmp2, FloatRegister tmp3);
1465   void ghash_multiply_wide(int index,
1466                            FloatRegister result_lo, FloatRegister result_hi,
1467                            FloatRegister a, FloatRegister b, FloatRegister a1_xor_a0,
1468                            FloatRegister tmp1, FloatRegister tmp2, FloatRegister tmp3);
1469   void ghash_reduce(FloatRegister result, FloatRegister lo, FloatRegister hi,
1470                     FloatRegister p, FloatRegister z, FloatRegister t1);
1471   void ghash_reduce_wide(int index, FloatRegister result, FloatRegister lo, FloatRegister hi,
1472                     FloatRegister p, FloatRegister z, FloatRegister t1);
1473   void ghash_processBlocks_wide(address p, Register state, Register subkeyH,
1474                                 Register data, Register blocks, int unrolls);
1475 
1476 
1477   void aesenc_loadkeys(Register key, Register keylen);
1478   void aesecb_encrypt(Register from, Register to, Register keylen,
1479                       FloatRegister data = v0, int unrolls = 1);
1480   void aesecb_decrypt(Register from, Register to, Register key, Register keylen);
1481   void aes_round(FloatRegister input, FloatRegister subkey);
1482 
1483   // ChaCha20 functions support block
1484   void cc20_quarter_round(FloatRegister aVec, FloatRegister bVec,
1485           FloatRegister cVec, FloatRegister dVec, FloatRegister scratch,
1486           FloatRegister tbl);
1487   void cc20_shift_lane_org(FloatRegister bVec, FloatRegister cVec,
1488           FloatRegister dVec, bool colToDiag);
1489 
1490   // Place an ISB after code may have been modified due to a safepoint.
1491   void safepoint_isb();
1492 
1493 private:
1494   // Return the effective address r + (r1 << ext) + offset.
1495   // Uses rscratch2.
1496   Address offsetted_address(Register r, Register r1, Address::extend ext,
1497                             int offset, int size);
1498 
1499 private:
1500   // Returns an address on the stack which is reachable with a ldr/str of size
1501   // Uses rscratch2 if the address is not directly reachable
1502   Address spill_address(int size, int offset, Register tmp=rscratch2);
1503   Address sve_spill_address(int sve_reg_size_in_bytes, int offset, Register tmp=rscratch2);
1504 
1505   bool merge_alignment_check(Register base, size_t size, int64_t cur_offset, int64_t prev_offset) const;
1506 
1507   // Check whether two loads/stores can be merged into ldp/stp.
1508   bool ldst_can_merge(Register rx, const Address &adr, size_t cur_size_in_bytes, bool is_store) const;
1509 
1510   // Merge current load/store with previous load/store into ldp/stp.
1511   void merge_ldst(Register rx, const Address &adr, size_t cur_size_in_bytes, bool is_store);
1512 
1513   // Try to merge two loads/stores into ldp/stp. If success, returns true else false.
1514   bool try_merge_ldst(Register rt, const Address &adr, size_t cur_size_in_bytes, bool is_store);
1515 
1516 public:
1517   void spill(Register Rx, bool is64, int offset) {
1518     if (is64) {
1519       str(Rx, spill_address(8, offset));
1520     } else {
1521       strw(Rx, spill_address(4, offset));
1522     }
1523   }
1524   void spill(FloatRegister Vx, SIMD_RegVariant T, int offset) {
1525     str(Vx, T, spill_address(1 << (int)T, offset));
1526   }
1527 
1528   void spill_sve_vector(FloatRegister Zx, int offset, int vector_reg_size_in_bytes) {
1529     sve_str(Zx, sve_spill_address(vector_reg_size_in_bytes, offset));
1530   }
1531   void spill_sve_predicate(PRegister pr, int offset, int predicate_reg_size_in_bytes) {
1532     sve_str(pr, sve_spill_address(predicate_reg_size_in_bytes, offset));
1533   }
1534 
1535   void unspill(Register Rx, bool is64, int offset) {
1536     if (is64) {
1537       ldr(Rx, spill_address(8, offset));
1538     } else {
1539       ldrw(Rx, spill_address(4, offset));
1540     }
1541   }
1542   void unspill(FloatRegister Vx, SIMD_RegVariant T, int offset) {
1543     ldr(Vx, T, spill_address(1 << (int)T, offset));
1544   }
1545 
1546   void unspill_sve_vector(FloatRegister Zx, int offset, int vector_reg_size_in_bytes) {
1547     sve_ldr(Zx, sve_spill_address(vector_reg_size_in_bytes, offset));
1548   }
1549   void unspill_sve_predicate(PRegister pr, int offset, int predicate_reg_size_in_bytes) {
1550     sve_ldr(pr, sve_spill_address(predicate_reg_size_in_bytes, offset));
1551   }
1552 
1553   void spill_copy128(int src_offset, int dst_offset,
1554                      Register tmp1=rscratch1, Register tmp2=rscratch2) {
1555     if (src_offset < 512 && (src_offset & 7) == 0 &&
1556         dst_offset < 512 && (dst_offset & 7) == 0) {
1557       ldp(tmp1, tmp2, Address(sp, src_offset));
1558       stp(tmp1, tmp2, Address(sp, dst_offset));
1559     } else {
1560       unspill(tmp1, true, src_offset);
1561       spill(tmp1, true, dst_offset);
1562       unspill(tmp1, true, src_offset+8);
1563       spill(tmp1, true, dst_offset+8);
1564     }
1565   }
1566   void spill_copy_sve_vector_stack_to_stack(int src_offset, int dst_offset,
1567                                             int sve_vec_reg_size_in_bytes) {
1568     assert(sve_vec_reg_size_in_bytes % 16 == 0, "unexpected sve vector reg size");
1569     for (int i = 0; i < sve_vec_reg_size_in_bytes / 16; i++) {
1570       spill_copy128(src_offset, dst_offset);
1571       src_offset += 16;
1572       dst_offset += 16;
1573     }
1574   }
1575   void spill_copy_sve_predicate_stack_to_stack(int src_offset, int dst_offset,
1576                                                int sve_predicate_reg_size_in_bytes) {
1577     sve_ldr(ptrue, sve_spill_address(sve_predicate_reg_size_in_bytes, src_offset));
1578     sve_str(ptrue, sve_spill_address(sve_predicate_reg_size_in_bytes, dst_offset));
1579     reinitialize_ptrue();
1580   }
1581   void cache_wb(Address line);
1582   void cache_wbsync(bool is_pre);
1583 
1584   // Code for java.lang.Thread::onSpinWait() intrinsic.
1585   void spin_wait();
1586 
1587   void fast_lock(Register obj, Register hdr, Register t1, Register t2, Label& slow);
1588   void fast_unlock(Register obj, Register hdr, Register t1, Register t2, Label& slow);
1589 
1590 private:
1591   // Check the current thread doesn't need a cross modify fence.
1592   void verify_cross_modify_fence_not_required() PRODUCT_RETURN;
1593 
1594 };
1595 
1596 #ifdef ASSERT
1597 inline bool AbstractAssembler::pd_check_instruction_mark() { return false; }
1598 #endif
1599 
1600 /**
1601  * class SkipIfEqual:
1602  *
1603  * Instantiating this class will result in assembly code being output that will
1604  * jump around any code emitted between the creation of the instance and it's
1605  * automatic destruction at the end of a scope block, depending on the value of
1606  * the flag passed to the constructor, which will be checked at run-time.
1607  */
1608 class SkipIfEqual {
1609  private:
1610   MacroAssembler* _masm;
1611   Label _label;
1612 
1613  public:
1614    SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
1615    ~SkipIfEqual();
1616 };
1617 
1618 struct tableswitch {
1619   Register _reg;
1620   int _insn_index; jint _first_key; jint _last_key;
1621   Label _after;
1622   Label _branches;
1623 };
1624 
1625 #endif // CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP