1 /*
   2  * Copyright (c) 1997, 2021, Oracle and/or its affiliates. All rights reserved.
   3  * Copyright (c) 2014, 2021, Red Hat Inc. All rights reserved.
   4  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   5  *
   6  * This code is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 only, as
   8  * published by the Free Software Foundation.
   9  *
  10  * This code is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  * version 2 for more details (a copy is included in the LICENSE file that
  14  * accompanied this code).
  15  *
  16  * You should have received a copy of the GNU General Public License version
  17  * 2 along with this work; if not, write to the Free Software Foundation,
  18  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  19  *
  20  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  21  * or visit www.oracle.com if you need additional information or have any
  22  * questions.
  23  *
  24  */
  25 
  26 #ifndef CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
  27 #define CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
  28 
  29 #include "asm/assembler.inline.hpp"
  30 #include "oops/compressedOops.hpp"
  31 #include "runtime/vm_version.hpp"
  32 #include "utilities/powerOfTwo.hpp"
  33 
  34 // MacroAssembler extends Assembler by frequently used macros.
  35 //
  36 // Instructions for which a 'better' code sequence exists depending
  37 // on arguments should also go in here.
  38 
  39 class MacroAssembler: public Assembler {
  40   friend class LIR_Assembler;
  41 
  42  public:
  43   using Assembler::mov;
  44   using Assembler::movi;
  45 
  46  protected:
  47 
  48   // Support for VM calls
  49   //
  50   // This is the base routine called by the different versions of call_VM_leaf. The interpreter
  51   // may customize this version by overriding it for its purposes (e.g., to save/restore
  52   // additional registers when doing a VM call).
  53   virtual void call_VM_leaf_base(
  54     address entry_point,               // the entry point
  55     int     number_of_arguments,        // the number of arguments to pop after the call
  56     Label *retaddr = NULL
  57   );
  58 
  59   virtual void call_VM_leaf_base(
  60     address entry_point,               // the entry point
  61     int     number_of_arguments,        // the number of arguments to pop after the call
  62     Label &retaddr) {
  63     call_VM_leaf_base(entry_point, number_of_arguments, &retaddr);
  64   }
  65 
  66   // This is the base routine called by the different versions of call_VM. The interpreter
  67   // may customize this version by overriding it for its purposes (e.g., to save/restore
  68   // additional registers when doing a VM call).
  69   //
  70   // If no java_thread register is specified (noreg) than rthread will be used instead. call_VM_base
  71   // returns the register which contains the thread upon return. If a thread register has been
  72   // specified, the return value will correspond to that register. If no last_java_sp is specified
  73   // (noreg) than rsp will be used instead.
  74   virtual void call_VM_base(           // returns the register containing the thread upon return
  75     Register oop_result,               // where an oop-result ends up if any; use noreg otherwise
  76     Register java_thread,              // the thread if computed before     ; use noreg otherwise
  77     Register last_java_sp,             // to set up last_Java_frame in stubs; use noreg otherwise
  78     address  entry_point,              // the entry point
  79     int      number_of_arguments,      // the number of arguments (w/o thread) to pop after the call
  80     bool     check_exceptions          // whether to check for pending exceptions after return
  81   );
  82 
  83   void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
  84 
  85  public:
  86 
  87   enum KlassDecodeMode {
  88     KlassDecodeNone,
  89     KlassDecodeZero,
  90     KlassDecodeXor,
  91     KlassDecodeMovk
  92   };
  93 
  94   // Return the current narrow Klass pointer decode mode. Initialized on first call.
  95   static KlassDecodeMode klass_decode_mode();
  96 
  97   // Given an arbitrary base address, return the KlassDecodeMode that would be used. Return KlassDecodeNone
  98   // if base address is not valid for encoding.
  99   static KlassDecodeMode klass_decode_mode_for_base(address base);
 100 
 101   // Returns a static string
 102   static const char* describe_klass_decode_mode(KlassDecodeMode mode);
 103 
 104  private:
 105 
 106   static KlassDecodeMode _klass_decode_mode;
 107 
 108  public:
 109   MacroAssembler(CodeBuffer* code) : Assembler(code) {}
 110 
 111  // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
 112  // The implementation is only non-empty for the InterpreterMacroAssembler,
 113  // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
 114  virtual void check_and_handle_popframe(Register java_thread);
 115  virtual void check_and_handle_earlyret(Register java_thread);
 116 
 117   void safepoint_poll(Label& slow_path, bool at_return, bool acquire, bool in_nmethod);
 118 
 119   // Helper functions for statistics gathering.
 120   // Unconditional atomic increment.
 121   void atomic_incw(Register counter_addr, Register tmp, Register tmp2);
 122   void atomic_incw(Address counter_addr, Register tmp1, Register tmp2, Register tmp3) {
 123     lea(tmp1, counter_addr);
 124     atomic_incw(tmp1, tmp2, tmp3);
 125   }
 126   // Load Effective Address
 127   void lea(Register r, const Address &a) {
 128     InstructionMark im(this);
 129     code_section()->relocate(inst_mark(), a.rspec());
 130     a.lea(this, r);
 131   }
 132 
 133   /* Sometimes we get misaligned loads and stores, usually from Unsafe
 134      accesses, and these can exceed the offset range. */
 135   Address legitimize_address(const Address &a, int size, Register scratch) {
 136     if (a.getMode() == Address::base_plus_offset) {
 137       if (! Address::offset_ok_for_immed(a.offset(), exact_log2(size))) {
 138         block_comment("legitimize_address {");
 139         lea(scratch, a);
 140         block_comment("} legitimize_address");
 141         return Address(scratch);
 142       }
 143     }
 144     return a;
 145   }
 146 
 147   void addmw(Address a, Register incr, Register scratch) {
 148     ldrw(scratch, a);
 149     addw(scratch, scratch, incr);
 150     strw(scratch, a);
 151   }
 152 
 153   // Add constant to memory word
 154   void addmw(Address a, int imm, Register scratch) {
 155     ldrw(scratch, a);
 156     if (imm > 0)
 157       addw(scratch, scratch, (unsigned)imm);
 158     else
 159       subw(scratch, scratch, (unsigned)-imm);
 160     strw(scratch, a);
 161   }
 162 
 163   void bind(Label& L) {
 164     Assembler::bind(L);
 165     code()->clear_last_insn();
 166   }
 167 
 168   void membar(Membar_mask_bits order_constraint);
 169 
 170   using Assembler::ldr;
 171   using Assembler::str;
 172   using Assembler::ldrw;
 173   using Assembler::strw;
 174 
 175   void ldr(Register Rx, const Address &adr);
 176   void ldrw(Register Rw, const Address &adr);
 177   void str(Register Rx, const Address &adr);
 178   void strw(Register Rx, const Address &adr);
 179 
 180   // Frame creation and destruction shared between JITs.
 181   void build_frame(int framesize);
 182   void remove_frame(int framesize);
 183 
 184   virtual void _call_Unimplemented(address call_site) {
 185     mov(rscratch2, call_site);
 186   }
 187 
 188 // Microsoft's MSVC team thinks that the __FUNCSIG__ is approximately (sympathy for calling conventions) equivalent to __PRETTY_FUNCTION__
 189 // Also, from Clang patch: "It is very similar to GCC's PRETTY_FUNCTION, except it prints the calling convention."
 190 // https://reviews.llvm.org/D3311
 191 
 192 #ifdef _WIN64
 193 #define call_Unimplemented() _call_Unimplemented((address)__FUNCSIG__)
 194 #else
 195 #define call_Unimplemented() _call_Unimplemented((address)__PRETTY_FUNCTION__)
 196 #endif
 197 
 198   // aliases defined in AARCH64 spec
 199 
 200   template<class T>
 201   inline void cmpw(Register Rd, T imm)  { subsw(zr, Rd, imm); }
 202 
 203   inline void cmp(Register Rd, unsigned char imm8)  { subs(zr, Rd, imm8); }
 204   inline void cmp(Register Rd, unsigned imm) = delete;
 205 
 206   inline void cmnw(Register Rd, unsigned imm) { addsw(zr, Rd, imm); }
 207   inline void cmn(Register Rd, unsigned imm) { adds(zr, Rd, imm); }
 208 
 209   void cset(Register Rd, Assembler::Condition cond) {
 210     csinc(Rd, zr, zr, ~cond);
 211   }
 212   void csetw(Register Rd, Assembler::Condition cond) {
 213     csincw(Rd, zr, zr, ~cond);
 214   }
 215 
 216   void cneg(Register Rd, Register Rn, Assembler::Condition cond) {
 217     csneg(Rd, Rn, Rn, ~cond);
 218   }
 219   void cnegw(Register Rd, Register Rn, Assembler::Condition cond) {
 220     csnegw(Rd, Rn, Rn, ~cond);
 221   }
 222 
 223   inline void movw(Register Rd, Register Rn) {
 224     if (Rd == sp || Rn == sp) {
 225       addw(Rd, Rn, 0U);
 226     } else {
 227       orrw(Rd, zr, Rn);
 228     }
 229   }
 230   inline void mov(Register Rd, Register Rn) {
 231     assert(Rd != r31_sp && Rn != r31_sp, "should be");
 232     if (Rd == Rn) {
 233     } else if (Rd == sp || Rn == sp) {
 234       add(Rd, Rn, 0U);
 235     } else {
 236       orr(Rd, zr, Rn);
 237     }
 238   }
 239 
 240   inline void moviw(Register Rd, unsigned imm) { orrw(Rd, zr, imm); }
 241   inline void movi(Register Rd, unsigned imm) { orr(Rd, zr, imm); }
 242 
 243   inline void tstw(Register Rd, Register Rn) { andsw(zr, Rd, Rn); }
 244   inline void tst(Register Rd, Register Rn) { ands(zr, Rd, Rn); }
 245 
 246   inline void tstw(Register Rd, uint64_t imm) { andsw(zr, Rd, imm); }
 247   inline void tst(Register Rd, uint64_t imm) { ands(zr, Rd, imm); }
 248 
 249   inline void bfiw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 250     bfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
 251   }
 252   inline void bfi(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 253     bfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
 254   }
 255 
 256   inline void bfxilw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 257     bfmw(Rd, Rn, lsb, (lsb + width - 1));
 258   }
 259   inline void bfxil(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 260     bfm(Rd, Rn, lsb , (lsb + width - 1));
 261   }
 262 
 263   inline void sbfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 264     sbfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
 265   }
 266   inline void sbfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 267     sbfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
 268   }
 269 
 270   inline void sbfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 271     sbfmw(Rd, Rn, lsb, (lsb + width - 1));
 272   }
 273   inline void sbfx(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 274     sbfm(Rd, Rn, lsb , (lsb + width - 1));
 275   }
 276 
 277   inline void ubfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 278     ubfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
 279   }
 280   inline void ubfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 281     ubfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
 282   }
 283 
 284   inline void ubfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 285     ubfmw(Rd, Rn, lsb, (lsb + width - 1));
 286   }
 287   inline void ubfx(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 288     ubfm(Rd, Rn, lsb , (lsb + width - 1));
 289   }
 290 
 291   inline void asrw(Register Rd, Register Rn, unsigned imm) {
 292     sbfmw(Rd, Rn, imm, 31);
 293   }
 294 
 295   inline void asr(Register Rd, Register Rn, unsigned imm) {
 296     sbfm(Rd, Rn, imm, 63);
 297   }
 298 
 299   inline void lslw(Register Rd, Register Rn, unsigned imm) {
 300     ubfmw(Rd, Rn, ((32 - imm) & 31), (31 - imm));
 301   }
 302 
 303   inline void lsl(Register Rd, Register Rn, unsigned imm) {
 304     ubfm(Rd, Rn, ((64 - imm) & 63), (63 - imm));
 305   }
 306 
 307   inline void lsrw(Register Rd, Register Rn, unsigned imm) {
 308     ubfmw(Rd, Rn, imm, 31);
 309   }
 310 
 311   inline void lsr(Register Rd, Register Rn, unsigned imm) {
 312     ubfm(Rd, Rn, imm, 63);
 313   }
 314 
 315   inline void rorw(Register Rd, Register Rn, unsigned imm) {
 316     extrw(Rd, Rn, Rn, imm);
 317   }
 318 
 319   inline void ror(Register Rd, Register Rn, unsigned imm) {
 320     extr(Rd, Rn, Rn, imm);
 321   }
 322 
 323   inline void sxtbw(Register Rd, Register Rn) {
 324     sbfmw(Rd, Rn, 0, 7);
 325   }
 326   inline void sxthw(Register Rd, Register Rn) {
 327     sbfmw(Rd, Rn, 0, 15);
 328   }
 329   inline void sxtb(Register Rd, Register Rn) {
 330     sbfm(Rd, Rn, 0, 7);
 331   }
 332   inline void sxth(Register Rd, Register Rn) {
 333     sbfm(Rd, Rn, 0, 15);
 334   }
 335   inline void sxtw(Register Rd, Register Rn) {
 336     sbfm(Rd, Rn, 0, 31);
 337   }
 338 
 339   inline void uxtbw(Register Rd, Register Rn) {
 340     ubfmw(Rd, Rn, 0, 7);
 341   }
 342   inline void uxthw(Register Rd, Register Rn) {
 343     ubfmw(Rd, Rn, 0, 15);
 344   }
 345   inline void uxtb(Register Rd, Register Rn) {
 346     ubfm(Rd, Rn, 0, 7);
 347   }
 348   inline void uxth(Register Rd, Register Rn) {
 349     ubfm(Rd, Rn, 0, 15);
 350   }
 351   inline void uxtw(Register Rd, Register Rn) {
 352     ubfm(Rd, Rn, 0, 31);
 353   }
 354 
 355   inline void cmnw(Register Rn, Register Rm) {
 356     addsw(zr, Rn, Rm);
 357   }
 358   inline void cmn(Register Rn, Register Rm) {
 359     adds(zr, Rn, Rm);
 360   }
 361 
 362   inline void cmpw(Register Rn, Register Rm) {
 363     subsw(zr, Rn, Rm);
 364   }
 365   inline void cmp(Register Rn, Register Rm) {
 366     subs(zr, Rn, Rm);
 367   }
 368 
 369   inline void negw(Register Rd, Register Rn) {
 370     subw(Rd, zr, Rn);
 371   }
 372 
 373   inline void neg(Register Rd, Register Rn) {
 374     sub(Rd, zr, Rn);
 375   }
 376 
 377   inline void negsw(Register Rd, Register Rn) {
 378     subsw(Rd, zr, Rn);
 379   }
 380 
 381   inline void negs(Register Rd, Register Rn) {
 382     subs(Rd, zr, Rn);
 383   }
 384 
 385   inline void cmnw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
 386     addsw(zr, Rn, Rm, kind, shift);
 387   }
 388   inline void cmn(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
 389     adds(zr, Rn, Rm, kind, shift);
 390   }
 391 
 392   inline void cmpw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
 393     subsw(zr, Rn, Rm, kind, shift);
 394   }
 395   inline void cmp(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
 396     subs(zr, Rn, Rm, kind, shift);
 397   }
 398 
 399   inline void negw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
 400     subw(Rd, zr, Rn, kind, shift);
 401   }
 402 
 403   inline void neg(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
 404     sub(Rd, zr, Rn, kind, shift);
 405   }
 406 
 407   inline void negsw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
 408     subsw(Rd, zr, Rn, kind, shift);
 409   }
 410 
 411   inline void negs(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
 412     subs(Rd, zr, Rn, kind, shift);
 413   }
 414 
 415   inline void mnegw(Register Rd, Register Rn, Register Rm) {
 416     msubw(Rd, Rn, Rm, zr);
 417   }
 418   inline void mneg(Register Rd, Register Rn, Register Rm) {
 419     msub(Rd, Rn, Rm, zr);
 420   }
 421 
 422   inline void mulw(Register Rd, Register Rn, Register Rm) {
 423     maddw(Rd, Rn, Rm, zr);
 424   }
 425   inline void mul(Register Rd, Register Rn, Register Rm) {
 426     madd(Rd, Rn, Rm, zr);
 427   }
 428 
 429   inline void smnegl(Register Rd, Register Rn, Register Rm) {
 430     smsubl(Rd, Rn, Rm, zr);
 431   }
 432   inline void smull(Register Rd, Register Rn, Register Rm) {
 433     smaddl(Rd, Rn, Rm, zr);
 434   }
 435 
 436   inline void umnegl(Register Rd, Register Rn, Register Rm) {
 437     umsubl(Rd, Rn, Rm, zr);
 438   }
 439   inline void umull(Register Rd, Register Rn, Register Rm) {
 440     umaddl(Rd, Rn, Rm, zr);
 441   }
 442 
 443 #define WRAP(INSN)                                                            \
 444   void INSN(Register Rd, Register Rn, Register Rm, Register Ra) {             \
 445     if ((VM_Version::features() & VM_Version::CPU_A53MAC) && Ra != zr)        \
 446       nop();                                                                  \
 447     Assembler::INSN(Rd, Rn, Rm, Ra);                                          \
 448   }
 449 
 450   WRAP(madd) WRAP(msub) WRAP(maddw) WRAP(msubw)
 451   WRAP(smaddl) WRAP(smsubl) WRAP(umaddl) WRAP(umsubl)
 452 #undef WRAP
 453 
 454 
 455   // macro assembly operations needed for aarch64
 456 
 457   // first two private routines for loading 32 bit or 64 bit constants
 458 private:
 459 
 460   void mov_immediate64(Register dst, uint64_t imm64);
 461   void mov_immediate32(Register dst, uint32_t imm32);
 462 
 463   int push(unsigned int bitset, Register stack);
 464   int pop(unsigned int bitset, Register stack);
 465 
 466   int push_fp(unsigned int bitset, Register stack);
 467   int pop_fp(unsigned int bitset, Register stack);
 468 
 469   int push_p(unsigned int bitset, Register stack);
 470   int pop_p(unsigned int bitset, Register stack);
 471 
 472   void mov(Register dst, Address a);
 473 
 474 public:
 475   void push(RegSet regs, Register stack) { if (regs.bits()) push(regs.bits(), stack); }
 476   void pop(RegSet regs, Register stack) { if (regs.bits()) pop(regs.bits(), stack); }
 477 
 478   void push_fp(FloatRegSet regs, Register stack) { if (regs.bits()) push_fp(regs.bits(), stack); }
 479   void pop_fp(FloatRegSet regs, Register stack) { if (regs.bits()) pop_fp(regs.bits(), stack); }
 480 
 481   static RegSet call_clobbered_registers();
 482 
 483   void push_p(PRegSet regs, Register stack) { if (regs.bits()) push_p(regs.bits(), stack); }
 484   void pop_p(PRegSet regs, Register stack) { if (regs.bits()) pop_p(regs.bits(), stack); }
 485 
 486   // Push and pop everything that might be clobbered by a native
 487   // runtime call except rscratch1 and rscratch2.  (They are always
 488   // scratch, so we don't have to protect them.)  Only save the lower
 489   // 64 bits of each vector register. Additonal registers can be excluded
 490   // in a passed RegSet.
 491   void push_call_clobbered_registers_except(RegSet exclude);
 492   void pop_call_clobbered_registers_except(RegSet exclude);
 493 
 494   void push_call_clobbered_registers() {
 495     push_call_clobbered_registers_except(RegSet());
 496   }
 497   void pop_call_clobbered_registers() {
 498     pop_call_clobbered_registers_except(RegSet());
 499   }
 500 
 501 
 502   // now mov instructions for loading absolute addresses and 32 or
 503   // 64 bit integers
 504 
 505   inline void mov(Register dst, address addr)             { mov_immediate64(dst, (uint64_t)addr); }
 506 
 507   inline void mov(Register dst, int imm64)                { mov_immediate64(dst, (uint64_t)imm64); }
 508   inline void mov(Register dst, long imm64)               { mov_immediate64(dst, (uint64_t)imm64); }
 509   inline void mov(Register dst, long long imm64)          { mov_immediate64(dst, (uint64_t)imm64); }
 510   inline void mov(Register dst, unsigned int imm64)       { mov_immediate64(dst, (uint64_t)imm64); }
 511   inline void mov(Register dst, unsigned long imm64)      { mov_immediate64(dst, (uint64_t)imm64); }
 512   inline void mov(Register dst, unsigned long long imm64) { mov_immediate64(dst, (uint64_t)imm64); }
 513 
 514   inline void movw(Register dst, uint32_t imm32)
 515   {
 516     mov_immediate32(dst, imm32);
 517   }
 518 
 519   void mov(Register dst, RegisterOrConstant src) {
 520     if (src.is_register())
 521       mov(dst, src.as_register());
 522     else
 523       mov(dst, src.as_constant());
 524   }
 525 
 526   void movptr(Register r, uintptr_t imm64);
 527 
 528   void mov(FloatRegister Vd, SIMD_Arrangement T, uint32_t imm32);
 529 
 530   void mov(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) {
 531     orr(Vd, T, Vn, Vn);
 532   }
 533 
 534 
 535 public:
 536 
 537   // Generalized Test Bit And Branch, including a "far" variety which
 538   // spans more than 32KiB.
 539   void tbr(Condition cond, Register Rt, int bitpos, Label &dest, bool isfar = false) {
 540     assert(cond == EQ || cond == NE, "must be");
 541 
 542     if (isfar)
 543       cond = ~cond;
 544 
 545     void (Assembler::* branch)(Register Rt, int bitpos, Label &L);
 546     if (cond == Assembler::EQ)
 547       branch = &Assembler::tbz;
 548     else
 549       branch = &Assembler::tbnz;
 550 
 551     if (isfar) {
 552       Label L;
 553       (this->*branch)(Rt, bitpos, L);
 554       b(dest);
 555       bind(L);
 556     } else {
 557       (this->*branch)(Rt, bitpos, dest);
 558     }
 559   }
 560 
 561   // macro instructions for accessing and updating floating point
 562   // status register
 563   //
 564   // FPSR : op1 == 011
 565   //        CRn == 0100
 566   //        CRm == 0100
 567   //        op2 == 001
 568 
 569   inline void get_fpsr(Register reg)
 570   {
 571     mrs(0b11, 0b0100, 0b0100, 0b001, reg);
 572   }
 573 
 574   inline void set_fpsr(Register reg)
 575   {
 576     msr(0b011, 0b0100, 0b0100, 0b001, reg);
 577   }
 578 
 579   inline void clear_fpsr()
 580   {
 581     msr(0b011, 0b0100, 0b0100, 0b001, zr);
 582   }
 583 
 584   // DCZID_EL0: op1 == 011
 585   //            CRn == 0000
 586   //            CRm == 0000
 587   //            op2 == 111
 588   inline void get_dczid_el0(Register reg)
 589   {
 590     mrs(0b011, 0b0000, 0b0000, 0b111, reg);
 591   }
 592 
 593   // CTR_EL0:   op1 == 011
 594   //            CRn == 0000
 595   //            CRm == 0000
 596   //            op2 == 001
 597   inline void get_ctr_el0(Register reg)
 598   {
 599     mrs(0b011, 0b0000, 0b0000, 0b001, reg);
 600   }
 601 
 602   // idiv variant which deals with MINLONG as dividend and -1 as divisor
 603   int corrected_idivl(Register result, Register ra, Register rb,
 604                       bool want_remainder, Register tmp = rscratch1);
 605   int corrected_idivq(Register result, Register ra, Register rb,
 606                       bool want_remainder, Register tmp = rscratch1);
 607 
 608   // Support for NULL-checks
 609   //
 610   // Generates code that causes a NULL OS exception if the content of reg is NULL.
 611   // If the accessed location is M[reg + offset] and the offset is known, provide the
 612   // offset. No explicit code generation is needed if the offset is within a certain
 613   // range (0 <= offset <= page_size).
 614 
 615   virtual void null_check(Register reg, int offset = -1);
 616   static bool needs_explicit_null_check(intptr_t offset);
 617   static bool uses_implicit_null_check(void* address);
 618 
 619   static address target_addr_for_insn(address insn_addr, unsigned insn);
 620   static address target_addr_for_insn(address insn_addr) {
 621     unsigned insn = *(unsigned*)insn_addr;
 622     return target_addr_for_insn(insn_addr, insn);
 623   }
 624 
 625   // Required platform-specific helpers for Label::patch_instructions.
 626   // They _shadow_ the declarations in AbstractAssembler, which are undefined.
 627   static int pd_patch_instruction_size(address branch, address target);
 628   static void pd_patch_instruction(address branch, address target, const char* file = NULL, int line = 0) {
 629     pd_patch_instruction_size(branch, target);
 630   }
 631   static address pd_call_destination(address branch) {
 632     return target_addr_for_insn(branch);
 633   }
 634 #ifndef PRODUCT
 635   static void pd_print_patched_instruction(address branch);
 636 #endif
 637 
 638   static int patch_oop(address insn_addr, address o);
 639   static int patch_narrow_klass(address insn_addr, narrowKlass n);
 640 
 641   address emit_trampoline_stub(int insts_call_instruction_offset, address target);
 642   void emit_static_call_stub();
 643 
 644   // The following 4 methods return the offset of the appropriate move instruction
 645 
 646   // Support for fast byte/short loading with zero extension (depending on particular CPU)
 647   int load_unsigned_byte(Register dst, Address src);
 648   int load_unsigned_short(Register dst, Address src);
 649 
 650   // Support for fast byte/short loading with sign extension (depending on particular CPU)
 651   int load_signed_byte(Register dst, Address src);
 652   int load_signed_short(Register dst, Address src);
 653 
 654   int load_signed_byte32(Register dst, Address src);
 655   int load_signed_short32(Register dst, Address src);
 656 
 657   // Support for sign-extension (hi:lo = extend_sign(lo))
 658   void extend_sign(Register hi, Register lo);
 659 
 660   // Load and store values by size and signed-ness
 661   void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg);
 662   void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg);
 663 
 664   // Support for inc/dec with optimal instruction selection depending on value
 665 
 666   // x86_64 aliases an unqualified register/address increment and
 667   // decrement to call incrementq and decrementq but also supports
 668   // explicitly sized calls to incrementq/decrementq or
 669   // incrementl/decrementl
 670 
 671   // for aarch64 the proper convention would be to use
 672   // increment/decrement for 64 bit operatons and
 673   // incrementw/decrementw for 32 bit operations. so when porting
 674   // x86_64 code we can leave calls to increment/decrement as is,
 675   // replace incrementq/decrementq with increment/decrement and
 676   // replace incrementl/decrementl with incrementw/decrementw.
 677 
 678   // n.b. increment/decrement calls with an Address destination will
 679   // need to use a scratch register to load the value to be
 680   // incremented. increment/decrement calls which add or subtract a
 681   // constant value greater than 2^12 will need to use a 2nd scratch
 682   // register to hold the constant. so, a register increment/decrement
 683   // may trash rscratch2 and an address increment/decrement trash
 684   // rscratch and rscratch2
 685 
 686   void decrementw(Address dst, int value = 1);
 687   void decrementw(Register reg, int value = 1);
 688 
 689   void decrement(Register reg, int value = 1);
 690   void decrement(Address dst, int value = 1);
 691 
 692   void incrementw(Address dst, int value = 1);
 693   void incrementw(Register reg, int value = 1);
 694 
 695   void increment(Register reg, int value = 1);
 696   void increment(Address dst, int value = 1);
 697 
 698 
 699   // Alignment
 700   void align(int modulus);
 701 
 702   // Stack frame creation/removal
 703   void enter()
 704   {
 705     stp(rfp, lr, Address(pre(sp, -2 * wordSize)));
 706     mov(rfp, sp);
 707   }
 708   void leave()
 709   {
 710     mov(sp, rfp);
 711     ldp(rfp, lr, Address(post(sp, 2 * wordSize)));
 712   }
 713 
 714   // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
 715   // The pointer will be loaded into the thread register.
 716   void get_thread(Register thread);
 717 
 718 
 719   // Support for VM calls
 720   //
 721   // It is imperative that all calls into the VM are handled via the call_VM macros.
 722   // They make sure that the stack linkage is setup correctly. call_VM's correspond
 723   // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
 724 
 725 
 726   void call_VM(Register oop_result,
 727                address entry_point,
 728                bool check_exceptions = true);
 729   void call_VM(Register oop_result,
 730                address entry_point,
 731                Register arg_1,
 732                bool check_exceptions = true);
 733   void call_VM(Register oop_result,
 734                address entry_point,
 735                Register arg_1, Register arg_2,
 736                bool check_exceptions = true);
 737   void call_VM(Register oop_result,
 738                address entry_point,
 739                Register arg_1, Register arg_2, Register arg_3,
 740                bool check_exceptions = true);
 741 
 742   // Overloadings with last_Java_sp
 743   void call_VM(Register oop_result,
 744                Register last_java_sp,
 745                address entry_point,
 746                int number_of_arguments = 0,
 747                bool check_exceptions = true);
 748   void call_VM(Register oop_result,
 749                Register last_java_sp,
 750                address entry_point,
 751                Register arg_1, bool
 752                check_exceptions = true);
 753   void call_VM(Register oop_result,
 754                Register last_java_sp,
 755                address entry_point,
 756                Register arg_1, Register arg_2,
 757                bool check_exceptions = true);
 758   void call_VM(Register oop_result,
 759                Register last_java_sp,
 760                address entry_point,
 761                Register arg_1, Register arg_2, Register arg_3,
 762                bool check_exceptions = true);
 763 
 764   void get_vm_result  (Register oop_result, Register thread);
 765   void get_vm_result_2(Register metadata_result, Register thread);
 766 
 767   // These always tightly bind to MacroAssembler::call_VM_base
 768   // bypassing the virtual implementation
 769   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
 770   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
 771   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
 772   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
 773   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
 774 
 775   void call_VM_leaf(address entry_point,
 776                     int number_of_arguments = 0);
 777   void call_VM_leaf(address entry_point,
 778                     Register arg_1);
 779   void call_VM_leaf(address entry_point,
 780                     Register arg_1, Register arg_2);
 781   void call_VM_leaf(address entry_point,
 782                     Register arg_1, Register arg_2, Register arg_3);
 783 
 784   // These always tightly bind to MacroAssembler::call_VM_leaf_base
 785   // bypassing the virtual implementation
 786   void super_call_VM_leaf(address entry_point);
 787   void super_call_VM_leaf(address entry_point, Register arg_1);
 788   void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
 789   void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
 790   void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
 791 
 792   // last Java Frame (fills frame anchor)
 793   void set_last_Java_frame(Register last_java_sp,
 794                            Register last_java_fp,
 795                            address last_java_pc,
 796                            Register scratch);
 797 
 798   void set_last_Java_frame(Register last_java_sp,
 799                            Register last_java_fp,
 800                            Label &last_java_pc,
 801                            Register scratch);
 802 
 803   void set_last_Java_frame(Register last_java_sp,
 804                            Register last_java_fp,
 805                            Register last_java_pc,
 806                            Register scratch);
 807 
 808   void reset_last_Java_frame(Register thread);
 809 
 810   // thread in the default location (rthread)
 811   void reset_last_Java_frame(bool clear_fp);
 812 
 813   // Stores
 814   void store_check(Register obj);                // store check for obj - register is destroyed afterwards
 815   void store_check(Register obj, Address dst);   // same as above, dst is exact store location (reg. is destroyed)
 816 
 817   void resolve_jobject(Register value, Register thread, Register tmp);
 818 
 819   // C 'boolean' to Java boolean: x == 0 ? 0 : 1
 820   void c2bool(Register x);
 821 
 822   void load_method_holder_cld(Register rresult, Register rmethod);
 823   void load_method_holder(Register holder, Register method);
 824 
 825   // oop manipulations
 826   void load_klass(Register dst, Register src);
 827   void store_klass(Register dst, Register src);
 828   void cmp_klass(Register oop, Register trial_klass, Register tmp);
 829 
 830   void resolve_weak_handle(Register result, Register tmp);
 831   void resolve_oop_handle(Register result, Register tmp = r5);
 832   void load_mirror(Register dst, Register method, Register tmp = r5);
 833 
 834   void access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
 835                       Register tmp1, Register tmp_thread);
 836 
 837   void access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register src,
 838                        Register tmp1, Register tmp_thread);
 839 
 840   void load_heap_oop(Register dst, Address src, Register tmp1 = noreg,
 841                      Register thread_tmp = noreg, DecoratorSet decorators = 0);
 842 
 843   void load_heap_oop_not_null(Register dst, Address src, Register tmp1 = noreg,
 844                               Register thread_tmp = noreg, DecoratorSet decorators = 0);
 845   void store_heap_oop(Address dst, Register src, Register tmp1 = noreg,
 846                       Register tmp_thread = noreg, DecoratorSet decorators = 0);
 847 
 848   // currently unimplemented
 849   // Used for storing NULL. All other oop constants should be
 850   // stored using routines that take a jobject.
 851   void store_heap_oop_null(Address dst);
 852 
 853   void store_klass_gap(Register dst, Register src);
 854 
 855   // This dummy is to prevent a call to store_heap_oop from
 856   // converting a zero (like NULL) into a Register by giving
 857   // the compiler two choices it can't resolve
 858 
 859   void store_heap_oop(Address dst, void* dummy);
 860 
 861   void encode_heap_oop(Register d, Register s);
 862   void encode_heap_oop(Register r) { encode_heap_oop(r, r); }
 863   void decode_heap_oop(Register d, Register s);
 864   void decode_heap_oop(Register r) { decode_heap_oop(r, r); }
 865   void encode_heap_oop_not_null(Register r);
 866   void decode_heap_oop_not_null(Register r);
 867   void encode_heap_oop_not_null(Register dst, Register src);
 868   void decode_heap_oop_not_null(Register dst, Register src);
 869 
 870   void set_narrow_oop(Register dst, jobject obj);
 871 
 872   void encode_klass_not_null(Register r);
 873   void decode_klass_not_null(Register r);
 874   void encode_klass_not_null(Register dst, Register src);
 875   void decode_klass_not_null(Register dst, Register src);
 876 
 877   void set_narrow_klass(Register dst, Klass* k);
 878 
 879   // if heap base register is used - reinit it with the correct value
 880   void reinit_heapbase();
 881 
 882   DEBUG_ONLY(void verify_heapbase(const char* msg);)
 883 
 884   void push_CPU_state(bool save_vectors = false, bool use_sve = false,
 885                       int sve_vector_size_in_bytes = 0, int total_predicate_in_bytes = 0);
 886   void pop_CPU_state(bool restore_vectors = false, bool use_sve = false,
 887                      int sve_vector_size_in_bytes = 0, int total_predicate_in_bytes = 0);
 888 
 889   // Round up to a power of two
 890   void round_to(Register reg, int modulus);
 891 
 892   // allocation
 893   void eden_allocate(
 894     Register obj,                      // result: pointer to object after successful allocation
 895     Register var_size_in_bytes,        // object size in bytes if unknown at compile time; invalid otherwise
 896     int      con_size_in_bytes,        // object size in bytes if   known at compile time
 897     Register t1,                       // temp register
 898     Label&   slow_case                 // continuation point if fast allocation fails
 899   );
 900   void tlab_allocate(
 901     Register obj,                      // result: pointer to object after successful allocation
 902     Register var_size_in_bytes,        // object size in bytes if unknown at compile time; invalid otherwise
 903     int      con_size_in_bytes,        // object size in bytes if   known at compile time
 904     Register t1,                       // temp register
 905     Register t2,                       // temp register
 906     Label&   slow_case                 // continuation point if fast allocation fails
 907   );
 908   void verify_tlab();
 909 
 910   // interface method calling
 911   void lookup_interface_method(Register recv_klass,
 912                                Register intf_klass,
 913                                RegisterOrConstant itable_index,
 914                                Register method_result,
 915                                Register scan_temp,
 916                                Label& no_such_interface,
 917                    bool return_method = true);
 918 
 919   // virtual method calling
 920   // n.b. x86 allows RegisterOrConstant for vtable_index
 921   void lookup_virtual_method(Register recv_klass,
 922                              RegisterOrConstant vtable_index,
 923                              Register method_result);
 924 
 925   // Test sub_klass against super_klass, with fast and slow paths.
 926 
 927   // The fast path produces a tri-state answer: yes / no / maybe-slow.
 928   // One of the three labels can be NULL, meaning take the fall-through.
 929   // If super_check_offset is -1, the value is loaded up from super_klass.
 930   // No registers are killed, except temp_reg.
 931   void check_klass_subtype_fast_path(Register sub_klass,
 932                                      Register super_klass,
 933                                      Register temp_reg,
 934                                      Label* L_success,
 935                                      Label* L_failure,
 936                                      Label* L_slow_path,
 937                 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
 938 
 939   // The rest of the type check; must be wired to a corresponding fast path.
 940   // It does not repeat the fast path logic, so don't use it standalone.
 941   // The temp_reg and temp2_reg can be noreg, if no temps are available.
 942   // Updates the sub's secondary super cache as necessary.
 943   // If set_cond_codes, condition codes will be Z on success, NZ on failure.
 944   void check_klass_subtype_slow_path(Register sub_klass,
 945                                      Register super_klass,
 946                                      Register temp_reg,
 947                                      Register temp2_reg,
 948                                      Label* L_success,
 949                                      Label* L_failure,
 950                                      bool set_cond_codes = false);
 951 
 952   // Simplified, combined version, good for typical uses.
 953   // Falls through on failure.
 954   void check_klass_subtype(Register sub_klass,
 955                            Register super_klass,
 956                            Register temp_reg,
 957                            Label& L_success);
 958 
 959   void clinit_barrier(Register klass,
 960                       Register thread,
 961                       Label* L_fast_path = NULL,
 962                       Label* L_slow_path = NULL);
 963 
 964   Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
 965 
 966   void verify_sve_vector_length();
 967   void reinitialize_ptrue() {
 968     if (UseSVE > 0) {
 969       sve_ptrue(ptrue, B);
 970     }
 971   }
 972   void verify_ptrue();
 973 
 974   // Debugging
 975 
 976   // only if +VerifyOops
 977   void verify_oop(Register reg, const char* s = "broken oop");
 978   void verify_oop_addr(Address addr, const char * s = "broken oop addr");
 979 
 980 // TODO: verify method and klass metadata (compare against vptr?)
 981   void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
 982   void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
 983 
 984 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
 985 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
 986 
 987   // only if +VerifyFPU
 988   void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
 989 
 990   // prints msg, dumps registers and stops execution
 991   void stop(const char* msg);
 992 
 993   static void debug64(char* msg, int64_t pc, int64_t regs[]);
 994 
 995   void untested()                                { stop("untested"); }
 996 
 997   void unimplemented(const char* what = "");
 998 
 999   void should_not_reach_here()                   { stop("should not reach here"); }
1000 
1001   // Stack overflow checking
1002   void bang_stack_with_offset(int offset) {
1003     // stack grows down, caller passes positive offset
1004     assert(offset > 0, "must bang with negative offset");
1005     sub(rscratch2, sp, offset);
1006     str(zr, Address(rscratch2));
1007   }
1008 
1009   // Writes to stack successive pages until offset reached to check for
1010   // stack overflow + shadow pages.  Also, clobbers tmp
1011   void bang_stack_size(Register size, Register tmp);
1012 
1013   // Check for reserved stack access in method being exited (for JIT)
1014   void reserved_stack_check();
1015 
1016   // Arithmetics
1017 
1018   void addptr(const Address &dst, int32_t src);
1019   void cmpptr(Register src1, Address src2);
1020 
1021   void cmpoop(Register obj1, Register obj2);
1022 
1023   // Various forms of CAS
1024 
1025   void cmpxchg_obj_header(Register oldv, Register newv, Register obj, Register tmp,
1026                           Label &suceed, Label *fail);
1027   void cmpxchgptr(Register oldv, Register newv, Register addr, Register tmp,
1028                   Label &suceed, Label *fail);
1029 
1030   void cmpxchgw(Register oldv, Register newv, Register addr, Register tmp,
1031                   Label &suceed, Label *fail);
1032 
1033   void atomic_add(Register prev, RegisterOrConstant incr, Register addr);
1034   void atomic_addw(Register prev, RegisterOrConstant incr, Register addr);
1035   void atomic_addal(Register prev, RegisterOrConstant incr, Register addr);
1036   void atomic_addalw(Register prev, RegisterOrConstant incr, Register addr);
1037 
1038   void atomic_xchg(Register prev, Register newv, Register addr);
1039   void atomic_xchgw(Register prev, Register newv, Register addr);
1040   void atomic_xchgl(Register prev, Register newv, Register addr);
1041   void atomic_xchglw(Register prev, Register newv, Register addr);
1042   void atomic_xchgal(Register prev, Register newv, Register addr);
1043   void atomic_xchgalw(Register prev, Register newv, Register addr);
1044 
1045   void orptr(Address adr, RegisterOrConstant src) {
1046     ldr(rscratch1, adr);
1047     if (src.is_register())
1048       orr(rscratch1, rscratch1, src.as_register());
1049     else
1050       orr(rscratch1, rscratch1, src.as_constant());
1051     str(rscratch1, adr);
1052   }
1053 
1054   // A generic CAS; success or failure is in the EQ flag.
1055   // Clobbers rscratch1
1056   void cmpxchg(Register addr, Register expected, Register new_val,
1057                enum operand_size size,
1058                bool acquire, bool release, bool weak,
1059                Register result);
1060 
1061 private:
1062   void compare_eq(Register rn, Register rm, enum operand_size size);
1063 
1064 #ifdef ASSERT
1065   // Template short-hand support to clean-up after a failed call to trampoline
1066   // call generation (see trampoline_call() below),  when a set of Labels must
1067   // be reset (before returning).
1068   template<typename Label, typename... More>
1069   void reset_labels(Label &lbl, More&... more) {
1070     lbl.reset(); reset_labels(more...);
1071   }
1072   template<typename Label>
1073   void reset_labels(Label &lbl) {
1074     lbl.reset();
1075   }
1076 #endif
1077 
1078 public:
1079   // Calls
1080 
1081   address trampoline_call(Address entry, CodeBuffer* cbuf = NULL);
1082 
1083   static bool far_branches() {
1084     return ReservedCodeCacheSize > branch_range;
1085   }
1086 
1087   // Jumps that can reach anywhere in the code cache.
1088   // Trashes tmp.
1089   void far_call(Address entry, CodeBuffer *cbuf = NULL, Register tmp = rscratch1);
1090   void far_jump(Address entry, CodeBuffer *cbuf = NULL, Register tmp = rscratch1);
1091 
1092   static int far_branch_size() {
1093     if (far_branches()) {
1094       return 3 * 4;  // adrp, add, br
1095     } else {
1096       return 4;
1097     }
1098   }
1099 
1100   // Emit the CompiledIC call idiom
1101   address ic_call(address entry, jint method_index = 0);
1102 
1103 public:
1104 
1105   // Data
1106 
1107   void mov_metadata(Register dst, Metadata* obj);
1108   Address allocate_metadata_address(Metadata* obj);
1109   Address constant_oop_address(jobject obj);
1110 
1111   void movoop(Register dst, jobject obj, bool immediate = false);
1112 
1113   // CRC32 code for java.util.zip.CRC32::updateBytes() instrinsic.
1114   void kernel_crc32(Register crc, Register buf, Register len,
1115         Register table0, Register table1, Register table2, Register table3,
1116         Register tmp, Register tmp2, Register tmp3);
1117   // CRC32 code for java.util.zip.CRC32C::updateBytes() instrinsic.
1118   void kernel_crc32c(Register crc, Register buf, Register len,
1119         Register table0, Register table1, Register table2, Register table3,
1120         Register tmp, Register tmp2, Register tmp3);
1121 
1122   // Stack push and pop individual 64 bit registers
1123   void push(Register src);
1124   void pop(Register dst);
1125 
1126   void repne_scan(Register addr, Register value, Register count,
1127                   Register scratch);
1128   void repne_scanw(Register addr, Register value, Register count,
1129                    Register scratch);
1130 
1131   typedef void (MacroAssembler::* add_sub_imm_insn)(Register Rd, Register Rn, unsigned imm);
1132   typedef void (MacroAssembler::* add_sub_reg_insn)(Register Rd, Register Rn, Register Rm, enum shift_kind kind, unsigned shift);
1133 
1134   // If a constant does not fit in an immediate field, generate some
1135   // number of MOV instructions and then perform the operation
1136   void wrap_add_sub_imm_insn(Register Rd, Register Rn, unsigned imm,
1137                              add_sub_imm_insn insn1,
1138                              add_sub_reg_insn insn2);
1139   // Seperate vsn which sets the flags
1140   void wrap_adds_subs_imm_insn(Register Rd, Register Rn, unsigned imm,
1141                              add_sub_imm_insn insn1,
1142                              add_sub_reg_insn insn2);
1143 
1144 #define WRAP(INSN)                                                      \
1145   void INSN(Register Rd, Register Rn, unsigned imm) {                   \
1146     wrap_add_sub_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN); \
1147   }                                                                     \
1148                                                                         \
1149   void INSN(Register Rd, Register Rn, Register Rm,                      \
1150              enum shift_kind kind, unsigned shift = 0) {                \
1151     Assembler::INSN(Rd, Rn, Rm, kind, shift);                           \
1152   }                                                                     \
1153                                                                         \
1154   void INSN(Register Rd, Register Rn, Register Rm) {                    \
1155     Assembler::INSN(Rd, Rn, Rm);                                        \
1156   }                                                                     \
1157                                                                         \
1158   void INSN(Register Rd, Register Rn, Register Rm,                      \
1159            ext::operation option, int amount = 0) {                     \
1160     Assembler::INSN(Rd, Rn, Rm, option, amount);                        \
1161   }
1162 
1163   WRAP(add) WRAP(addw) WRAP(sub) WRAP(subw)
1164 
1165 #undef WRAP
1166 #define WRAP(INSN)                                                      \
1167   void INSN(Register Rd, Register Rn, unsigned imm) {                   \
1168     wrap_adds_subs_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN); \
1169   }                                                                     \
1170                                                                         \
1171   void INSN(Register Rd, Register Rn, Register Rm,                      \
1172              enum shift_kind kind, unsigned shift = 0) {                \
1173     Assembler::INSN(Rd, Rn, Rm, kind, shift);                           \
1174   }                                                                     \
1175                                                                         \
1176   void INSN(Register Rd, Register Rn, Register Rm) {                    \
1177     Assembler::INSN(Rd, Rn, Rm);                                        \
1178   }                                                                     \
1179                                                                         \
1180   void INSN(Register Rd, Register Rn, Register Rm,                      \
1181            ext::operation option, int amount = 0) {                     \
1182     Assembler::INSN(Rd, Rn, Rm, option, amount);                        \
1183   }
1184 
1185   WRAP(adds) WRAP(addsw) WRAP(subs) WRAP(subsw)
1186 
1187   void add(Register Rd, Register Rn, RegisterOrConstant increment);
1188   void addw(Register Rd, Register Rn, RegisterOrConstant increment);
1189   void sub(Register Rd, Register Rn, RegisterOrConstant decrement);
1190   void subw(Register Rd, Register Rn, RegisterOrConstant decrement);
1191 
1192   void adrp(Register reg1, const Address &dest, uint64_t &byte_offset);
1193 
1194   void tableswitch(Register index, jint lowbound, jint highbound,
1195                    Label &jumptable, Label &jumptable_end, int stride = 1) {
1196     adr(rscratch1, jumptable);
1197     subsw(rscratch2, index, lowbound);
1198     subsw(zr, rscratch2, highbound - lowbound);
1199     br(Assembler::HS, jumptable_end);
1200     add(rscratch1, rscratch1, rscratch2,
1201         ext::sxtw, exact_log2(stride * Assembler::instruction_size));
1202     br(rscratch1);
1203   }
1204 
1205   // Form an address from base + offset in Rd.  Rd may or may not
1206   // actually be used: you must use the Address that is returned.  It
1207   // is up to you to ensure that the shift provided matches the size
1208   // of your data.
1209   Address form_address(Register Rd, Register base, int64_t byte_offset, int shift);
1210 
1211   // Return true iff an address is within the 48-bit AArch64 address
1212   // space.
1213   bool is_valid_AArch64_address(address a) {
1214     return ((uint64_t)a >> 48) == 0;
1215   }
1216 
1217   // Load the base of the cardtable byte map into reg.
1218   void load_byte_map_base(Register reg);
1219 
1220   // Prolog generator routines to support switch between x86 code and
1221   // generated ARM code
1222 
1223   // routine to generate an x86 prolog for a stub function which
1224   // bootstraps into the generated ARM code which directly follows the
1225   // stub
1226   //
1227 
1228   public:
1229 
1230   void ldr_constant(Register dest, const Address &const_addr) {
1231     if (NearCpool) {
1232       ldr(dest, const_addr);
1233     } else {
1234       uint64_t offset;
1235       adrp(dest, InternalAddress(const_addr.target()), offset);
1236       ldr(dest, Address(dest, offset));
1237     }
1238   }
1239 
1240   address read_polling_page(Register r, relocInfo::relocType rtype);
1241   void get_polling_page(Register dest, relocInfo::relocType rtype);
1242 
1243   // CRC32 code for java.util.zip.CRC32::updateBytes() instrinsic.
1244   void update_byte_crc32(Register crc, Register val, Register table);
1245   void update_word_crc32(Register crc, Register v, Register tmp,
1246         Register table0, Register table1, Register table2, Register table3,
1247         bool upper = false);
1248 
1249   address has_negatives(Register ary1, Register len, Register result);
1250 
1251   address arrays_equals(Register a1, Register a2, Register result, Register cnt1,
1252                         Register tmp1, Register tmp2, Register tmp3, int elem_size);
1253 
1254   void string_equals(Register a1, Register a2, Register result, Register cnt1,
1255                      int elem_size);
1256 
1257   void fill_words(Register base, Register cnt, Register value);
1258   void zero_words(Register base, uint64_t cnt);
1259   address zero_words(Register ptr, Register cnt);
1260   void zero_dcache_blocks(Register base, Register cnt);
1261 
1262   static const int zero_words_block_size;
1263 
1264   address byte_array_inflate(Register src, Register dst, Register len,
1265                              FloatRegister vtmp1, FloatRegister vtmp2,
1266                              FloatRegister vtmp3, Register tmp4);
1267 
1268   void char_array_compress(Register src, Register dst, Register len,
1269                            FloatRegister tmp1Reg, FloatRegister tmp2Reg,
1270                            FloatRegister tmp3Reg, FloatRegister tmp4Reg,
1271                            Register result);
1272 
1273   void encode_iso_array(Register src, Register dst,
1274                         Register len, Register result,
1275                         FloatRegister Vtmp1, FloatRegister Vtmp2,
1276                         FloatRegister Vtmp3, FloatRegister Vtmp4);
1277   void fast_log(FloatRegister vtmp0, FloatRegister vtmp1, FloatRegister vtmp2,
1278                 FloatRegister vtmp3, FloatRegister vtmp4, FloatRegister vtmp5,
1279                 FloatRegister tmpC1, FloatRegister tmpC2, FloatRegister tmpC3,
1280                 FloatRegister tmpC4, Register tmp1, Register tmp2,
1281                 Register tmp3, Register tmp4, Register tmp5);
1282   void generate_dsin_dcos(bool isCos, address npio2_hw, address two_over_pi,
1283       address pio2, address dsin_coef, address dcos_coef);
1284  private:
1285   // begin trigonometric functions support block
1286   void generate__ieee754_rem_pio2(address npio2_hw, address two_over_pi, address pio2);
1287   void generate__kernel_rem_pio2(address two_over_pi, address pio2);
1288   void generate_kernel_sin(FloatRegister x, bool iyIsOne, address dsin_coef);
1289   void generate_kernel_cos(FloatRegister x, address dcos_coef);
1290   // end trigonometric functions support block
1291   void add2_with_carry(Register final_dest_hi, Register dest_hi, Register dest_lo,
1292                        Register src1, Register src2);
1293   void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
1294     add2_with_carry(dest_hi, dest_hi, dest_lo, src1, src2);
1295   }
1296   void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
1297                              Register y, Register y_idx, Register z,
1298                              Register carry, Register product,
1299                              Register idx, Register kdx);
1300   void multiply_128_x_128_loop(Register y, Register z,
1301                                Register carry, Register carry2,
1302                                Register idx, Register jdx,
1303                                Register yz_idx1, Register yz_idx2,
1304                                Register tmp, Register tmp3, Register tmp4,
1305                                Register tmp7, Register product_hi);
1306   void kernel_crc32_using_crc32(Register crc, Register buf,
1307         Register len, Register tmp0, Register tmp1, Register tmp2,
1308         Register tmp3);
1309   void kernel_crc32c_using_crc32c(Register crc, Register buf,
1310         Register len, Register tmp0, Register tmp1, Register tmp2,
1311         Register tmp3);
1312 
1313   void ghash_modmul (FloatRegister result,
1314                      FloatRegister result_lo, FloatRegister result_hi, FloatRegister b,
1315                      FloatRegister a, FloatRegister vzr, FloatRegister a1_xor_a0, FloatRegister p,
1316                      FloatRegister t1, FloatRegister t2, FloatRegister t3);
1317   void ghash_load_wide(int index, Register data, FloatRegister result, FloatRegister state);
1318 public:
1319   void multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z,
1320                        Register zlen, Register tmp1, Register tmp2, Register tmp3,
1321                        Register tmp4, Register tmp5, Register tmp6, Register tmp7);
1322   void mul_add(Register out, Register in, Register offs, Register len, Register k);
1323   void ghash_multiply(FloatRegister result_lo, FloatRegister result_hi,
1324                       FloatRegister a, FloatRegister b, FloatRegister a1_xor_a0,
1325                       FloatRegister tmp1, FloatRegister tmp2, FloatRegister tmp3);
1326   void ghash_multiply_wide(int index,
1327                            FloatRegister result_lo, FloatRegister result_hi,
1328                            FloatRegister a, FloatRegister b, FloatRegister a1_xor_a0,
1329                            FloatRegister tmp1, FloatRegister tmp2, FloatRegister tmp3);
1330   void ghash_reduce(FloatRegister result, FloatRegister lo, FloatRegister hi,
1331                     FloatRegister p, FloatRegister z, FloatRegister t1);
1332   void ghash_reduce_wide(int index, FloatRegister result, FloatRegister lo, FloatRegister hi,
1333                     FloatRegister p, FloatRegister z, FloatRegister t1);
1334   void ghash_processBlocks_wide(address p, Register state, Register subkeyH,
1335                                 Register data, Register blocks, int unrolls);
1336 
1337 
1338   void aesenc_loadkeys(Register key, Register keylen);
1339   void aesecb_encrypt(Register from, Register to, Register keylen,
1340                       FloatRegister data = v0, int unrolls = 1);
1341   void aesecb_decrypt(Register from, Register to, Register key, Register keylen);
1342   void aes_round(FloatRegister input, FloatRegister subkey);
1343 
1344   // Place an ISB after code may have been modified due to a safepoint.
1345   void safepoint_isb();
1346 
1347 private:
1348   // Return the effective address r + (r1 << ext) + offset.
1349   // Uses rscratch2.
1350   Address offsetted_address(Register r, Register r1, Address::extend ext,
1351                             int offset, int size);
1352 
1353 private:
1354   // Returns an address on the stack which is reachable with a ldr/str of size
1355   // Uses rscratch2 if the address is not directly reachable
1356   Address spill_address(int size, int offset, Register tmp=rscratch2);
1357   Address sve_spill_address(int sve_reg_size_in_bytes, int offset, Register tmp=rscratch2);
1358 
1359   bool merge_alignment_check(Register base, size_t size, int64_t cur_offset, int64_t prev_offset) const;
1360 
1361   // Check whether two loads/stores can be merged into ldp/stp.
1362   bool ldst_can_merge(Register rx, const Address &adr, size_t cur_size_in_bytes, bool is_store) const;
1363 
1364   // Merge current load/store with previous load/store into ldp/stp.
1365   void merge_ldst(Register rx, const Address &adr, size_t cur_size_in_bytes, bool is_store);
1366 
1367   // Try to merge two loads/stores into ldp/stp. If success, returns true else false.
1368   bool try_merge_ldst(Register rt, const Address &adr, size_t cur_size_in_bytes, bool is_store);
1369 
1370 public:
1371   void spill(Register Rx, bool is64, int offset) {
1372     if (is64) {
1373       str(Rx, spill_address(8, offset));
1374     } else {
1375       strw(Rx, spill_address(4, offset));
1376     }
1377   }
1378   void spill(FloatRegister Vx, SIMD_RegVariant T, int offset) {
1379     str(Vx, T, spill_address(1 << (int)T, offset));
1380   }
1381 
1382   void spill_sve_vector(FloatRegister Zx, int offset, int vector_reg_size_in_bytes) {
1383     sve_str(Zx, sve_spill_address(vector_reg_size_in_bytes, offset));
1384   }
1385   void spill_sve_predicate(PRegister pr, int offset, int predicate_reg_size_in_bytes) {
1386     sve_str(pr, sve_spill_address(predicate_reg_size_in_bytes, offset));
1387   }
1388 
1389   void unspill(Register Rx, bool is64, int offset) {
1390     if (is64) {
1391       ldr(Rx, spill_address(8, offset));
1392     } else {
1393       ldrw(Rx, spill_address(4, offset));
1394     }
1395   }
1396   void unspill(FloatRegister Vx, SIMD_RegVariant T, int offset) {
1397     ldr(Vx, T, spill_address(1 << (int)T, offset));
1398   }
1399 
1400   void unspill_sve_vector(FloatRegister Zx, int offset, int vector_reg_size_in_bytes) {
1401     sve_ldr(Zx, sve_spill_address(vector_reg_size_in_bytes, offset));
1402   }
1403   void unspill_sve_predicate(PRegister pr, int offset, int predicate_reg_size_in_bytes) {
1404     sve_ldr(pr, sve_spill_address(predicate_reg_size_in_bytes, offset));
1405   }
1406 
1407   void spill_copy128(int src_offset, int dst_offset,
1408                      Register tmp1=rscratch1, Register tmp2=rscratch2) {
1409     if (src_offset < 512 && (src_offset & 7) == 0 &&
1410         dst_offset < 512 && (dst_offset & 7) == 0) {
1411       ldp(tmp1, tmp2, Address(sp, src_offset));
1412       stp(tmp1, tmp2, Address(sp, dst_offset));
1413     } else {
1414       unspill(tmp1, true, src_offset);
1415       spill(tmp1, true, dst_offset);
1416       unspill(tmp1, true, src_offset+8);
1417       spill(tmp1, true, dst_offset+8);
1418     }
1419   }
1420   void spill_copy_sve_vector_stack_to_stack(int src_offset, int dst_offset,
1421                                             int sve_vec_reg_size_in_bytes) {
1422     assert(sve_vec_reg_size_in_bytes % 16 == 0, "unexpected sve vector reg size");
1423     for (int i = 0; i < sve_vec_reg_size_in_bytes / 16; i++) {
1424       spill_copy128(src_offset, dst_offset);
1425       src_offset += 16;
1426       dst_offset += 16;
1427     }
1428   }
1429   void spill_copy_sve_predicate_stack_to_stack(int src_offset, int dst_offset,
1430                                                int sve_predicate_reg_size_in_bytes) {
1431     sve_ldr(ptrue, sve_spill_address(sve_predicate_reg_size_in_bytes, src_offset));
1432     sve_str(ptrue, sve_spill_address(sve_predicate_reg_size_in_bytes, dst_offset));
1433     reinitialize_ptrue();
1434   }
1435   void cache_wb(Address line);
1436   void cache_wbsync(bool is_pre);
1437 
1438   // Code for java.lang.Thread::onSpinWait() intrinsic.
1439   void spin_wait();
1440 
1441 private:
1442   // Check the current thread doesn't need a cross modify fence.
1443   void verify_cross_modify_fence_not_required() PRODUCT_RETURN;
1444 
1445 };
1446 
1447 #ifdef ASSERT
1448 inline bool AbstractAssembler::pd_check_instruction_mark() { return false; }
1449 #endif
1450 
1451 /**
1452  * class SkipIfEqual:
1453  *
1454  * Instantiating this class will result in assembly code being output that will
1455  * jump around any code emitted between the creation of the instance and it's
1456  * automatic destruction at the end of a scope block, depending on the value of
1457  * the flag passed to the constructor, which will be checked at run-time.
1458  */
1459 class SkipIfEqual {
1460  private:
1461   MacroAssembler* _masm;
1462   Label _label;
1463 
1464  public:
1465    SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
1466    ~SkipIfEqual();
1467 };
1468 
1469 struct tableswitch {
1470   Register _reg;
1471   int _insn_index; jint _first_key; jint _last_key;
1472   Label _after;
1473   Label _branches;
1474 };
1475 
1476 #endif // CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP