1 /*
   2  * Copyright (c) 1997, 2023, Oracle and/or its affiliates. All rights reserved.
   3  * Copyright (c) 2014, 2021, Red Hat Inc. All rights reserved.
   4  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   5  *
   6  * This code is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 only, as
   8  * published by the Free Software Foundation.
   9  *
  10  * This code is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  * version 2 for more details (a copy is included in the LICENSE file that
  14  * accompanied this code).
  15  *
  16  * You should have received a copy of the GNU General Public License version
  17  * 2 along with this work; if not, write to the Free Software Foundation,
  18  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  19  *
  20  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  21  * or visit www.oracle.com if you need additional information or have any
  22  * questions.
  23  *
  24  */
  25 
  26 #ifndef CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
  27 #define CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
  28 
  29 #include "asm/assembler.inline.hpp"
  30 #include "code/vmreg.hpp"
  31 #include "metaprogramming/enableIf.hpp"
  32 #include "oops/compressedOops.hpp"
  33 #include "runtime/vm_version.hpp"
  34 #include "utilities/powerOfTwo.hpp"
  35 
  36 class OopMap;
  37 
  38 // MacroAssembler extends Assembler by frequently used macros.
  39 //
  40 // Instructions for which a 'better' code sequence exists depending
  41 // on arguments should also go in here.
  42 
  43 class MacroAssembler: public Assembler {
  44   friend class LIR_Assembler;
  45 
  46  public:
  47   using Assembler::mov;
  48   using Assembler::movi;
  49 
  50  protected:
  51 
  52   // Support for VM calls
  53   //
  54   // This is the base routine called by the different versions of call_VM_leaf. The interpreter
  55   // may customize this version by overriding it for its purposes (e.g., to save/restore
  56   // additional registers when doing a VM call).
  57   virtual void call_VM_leaf_base(
  58     address entry_point,               // the entry point
  59     int     number_of_arguments,        // the number of arguments to pop after the call
  60     Label *retaddr = NULL
  61   );
  62 
  63   virtual void call_VM_leaf_base(
  64     address entry_point,               // the entry point
  65     int     number_of_arguments,        // the number of arguments to pop after the call
  66     Label &retaddr) {
  67     call_VM_leaf_base(entry_point, number_of_arguments, &retaddr);
  68   }
  69 
  70   // This is the base routine called by the different versions of call_VM. The interpreter
  71   // may customize this version by overriding it for its purposes (e.g., to save/restore
  72   // additional registers when doing a VM call).
  73   //
  74   // If no java_thread register is specified (noreg) than rthread will be used instead. call_VM_base
  75   // returns the register which contains the thread upon return. If a thread register has been
  76   // specified, the return value will correspond to that register. If no last_java_sp is specified
  77   // (noreg) than rsp will be used instead.
  78   virtual void call_VM_base(           // returns the register containing the thread upon return
  79     Register oop_result,               // where an oop-result ends up if any; use noreg otherwise
  80     Register java_thread,              // the thread if computed before     ; use noreg otherwise
  81     Register last_java_sp,             // to set up last_Java_frame in stubs; use noreg otherwise
  82     address  entry_point,              // the entry point
  83     int      number_of_arguments,      // the number of arguments (w/o thread) to pop after the call
  84     bool     check_exceptions          // whether to check for pending exceptions after return
  85   );
  86 
  87   void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
  88 
  89  public:
  90 
  91   enum KlassDecodeMode {
  92     KlassDecodeNone,
  93     KlassDecodeZero,
  94     KlassDecodeXor,
  95     KlassDecodeMovk
  96   };
  97 
  98   // Return the current narrow Klass pointer decode mode. Initialized on first call.
  99   static KlassDecodeMode klass_decode_mode();
 100 
 101   // Given an arbitrary base address, return the KlassDecodeMode that would be used. Return KlassDecodeNone
 102   // if base address is not valid for encoding.
 103   static KlassDecodeMode klass_decode_mode_for_base(address base);
 104 
 105   // Returns a static string
 106   static const char* describe_klass_decode_mode(KlassDecodeMode mode);
 107 
 108  private:
 109   static KlassDecodeMode _klass_decode_mode;
 110 
 111  public:
 112   MacroAssembler(CodeBuffer* code) : Assembler(code) {}
 113 
 114  // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
 115  // The implementation is only non-empty for the InterpreterMacroAssembler,
 116  // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
 117  virtual void check_and_handle_popframe(Register java_thread);
 118  virtual void check_and_handle_earlyret(Register java_thread);
 119 
 120   void safepoint_poll(Label& slow_path, bool at_return, bool acquire, bool in_nmethod, Register tmp = rscratch1);
 121   void rt_call(address dest, Register tmp = rscratch1);
 122 
 123   // Load Effective Address
 124   void lea(Register r, const Address &a) {
 125     InstructionMark im(this);
 126     a.lea(this, r);
 127   }
 128 
 129   /* Sometimes we get misaligned loads and stores, usually from Unsafe
 130      accesses, and these can exceed the offset range. */
 131   Address legitimize_address(const Address &a, int size, Register scratch) {
 132     if (a.getMode() == Address::base_plus_offset) {
 133       if (! Address::offset_ok_for_immed(a.offset(), exact_log2(size))) {
 134         block_comment("legitimize_address {");
 135         lea(scratch, a);
 136         block_comment("} legitimize_address");
 137         return Address(scratch);
 138       }
 139     }
 140     return a;
 141   }
 142 
 143   void addmw(Address a, Register incr, Register scratch) {
 144     ldrw(scratch, a);
 145     addw(scratch, scratch, incr);
 146     strw(scratch, a);
 147   }
 148 
 149   // Add constant to memory word
 150   void addmw(Address a, int imm, Register scratch) {
 151     ldrw(scratch, a);
 152     if (imm > 0)
 153       addw(scratch, scratch, (unsigned)imm);
 154     else
 155       subw(scratch, scratch, (unsigned)-imm);
 156     strw(scratch, a);
 157   }
 158 
 159   void bind(Label& L) {
 160     Assembler::bind(L);
 161     code()->clear_last_insn();
 162   }
 163 
 164   void membar(Membar_mask_bits order_constraint);
 165 
 166   using Assembler::ldr;
 167   using Assembler::str;
 168   using Assembler::ldrw;
 169   using Assembler::strw;
 170 
 171   void ldr(Register Rx, const Address &adr);
 172   void ldrw(Register Rw, const Address &adr);
 173   void str(Register Rx, const Address &adr);
 174   void strw(Register Rx, const Address &adr);
 175 
 176   // Frame creation and destruction shared between JITs.
 177   void build_frame(int framesize);
 178   void remove_frame(int framesize);
 179 
 180   virtual void _call_Unimplemented(address call_site) {
 181     mov(rscratch2, call_site);
 182   }
 183 
 184 // Microsoft's MSVC team thinks that the __FUNCSIG__ is approximately (sympathy for calling conventions) equivalent to __PRETTY_FUNCTION__
 185 // Also, from Clang patch: "It is very similar to GCC's PRETTY_FUNCTION, except it prints the calling convention."
 186 // https://reviews.llvm.org/D3311
 187 
 188 #ifdef _WIN64
 189 #define call_Unimplemented() _call_Unimplemented((address)__FUNCSIG__)
 190 #else
 191 #define call_Unimplemented() _call_Unimplemented((address)__PRETTY_FUNCTION__)
 192 #endif
 193 
 194   // aliases defined in AARCH64 spec
 195 
 196   template<class T>
 197   inline void cmpw(Register Rd, T imm)  { subsw(zr, Rd, imm); }
 198 
 199   inline void cmp(Register Rd, unsigned char imm8)  { subs(zr, Rd, imm8); }
 200   inline void cmp(Register Rd, unsigned imm) = delete;
 201 
 202   template<class T>
 203   inline void cmnw(Register Rd, T imm) { addsw(zr, Rd, imm); }
 204 
 205   inline void cmn(Register Rd, unsigned char imm8)  { adds(zr, Rd, imm8); }
 206   inline void cmn(Register Rd, unsigned imm) = delete;
 207 
 208   void cset(Register Rd, Assembler::Condition cond) {
 209     csinc(Rd, zr, zr, ~cond);
 210   }
 211   void csetw(Register Rd, Assembler::Condition cond) {
 212     csincw(Rd, zr, zr, ~cond);
 213   }
 214 
 215   void cneg(Register Rd, Register Rn, Assembler::Condition cond) {
 216     csneg(Rd, Rn, Rn, ~cond);
 217   }
 218   void cnegw(Register Rd, Register Rn, Assembler::Condition cond) {
 219     csnegw(Rd, Rn, Rn, ~cond);
 220   }
 221 
 222   inline void movw(Register Rd, Register Rn) {
 223     if (Rd == sp || Rn == sp) {
 224       Assembler::addw(Rd, Rn, 0U);
 225     } else {
 226       orrw(Rd, zr, Rn);
 227     }
 228   }
 229   inline void mov(Register Rd, Register Rn) {
 230     assert(Rd != r31_sp && Rn != r31_sp, "should be");
 231     if (Rd == Rn) {
 232     } else if (Rd == sp || Rn == sp) {
 233       Assembler::add(Rd, Rn, 0U);
 234     } else {
 235       orr(Rd, zr, Rn);
 236     }
 237   }
 238 
 239   inline void moviw(Register Rd, unsigned imm) { orrw(Rd, zr, imm); }
 240   inline void movi(Register Rd, unsigned imm) { orr(Rd, zr, imm); }
 241 
 242   inline void tstw(Register Rd, Register Rn) { andsw(zr, Rd, Rn); }
 243   inline void tst(Register Rd, Register Rn) { ands(zr, Rd, Rn); }
 244 
 245   inline void tstw(Register Rd, uint64_t imm) { andsw(zr, Rd, imm); }
 246   inline void tst(Register Rd, uint64_t imm) { ands(zr, Rd, imm); }
 247 
 248   inline void bfiw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 249     bfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
 250   }
 251   inline void bfi(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 252     bfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
 253   }
 254 
 255   inline void bfxilw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 256     bfmw(Rd, Rn, lsb, (lsb + width - 1));
 257   }
 258   inline void bfxil(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 259     bfm(Rd, Rn, lsb , (lsb + width - 1));
 260   }
 261 
 262   inline void sbfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 263     sbfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
 264   }
 265   inline void sbfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 266     sbfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
 267   }
 268 
 269   inline void sbfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 270     sbfmw(Rd, Rn, lsb, (lsb + width - 1));
 271   }
 272   inline void sbfx(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 273     sbfm(Rd, Rn, lsb , (lsb + width - 1));
 274   }
 275 
 276   inline void ubfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 277     ubfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
 278   }
 279   inline void ubfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 280     ubfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
 281   }
 282 
 283   inline void ubfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 284     ubfmw(Rd, Rn, lsb, (lsb + width - 1));
 285   }
 286   inline void ubfx(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 287     ubfm(Rd, Rn, lsb , (lsb + width - 1));
 288   }
 289 
 290   inline void asrw(Register Rd, Register Rn, unsigned imm) {
 291     sbfmw(Rd, Rn, imm, 31);
 292   }
 293 
 294   inline void asr(Register Rd, Register Rn, unsigned imm) {
 295     sbfm(Rd, Rn, imm, 63);
 296   }
 297 
 298   inline void lslw(Register Rd, Register Rn, unsigned imm) {
 299     ubfmw(Rd, Rn, ((32 - imm) & 31), (31 - imm));
 300   }
 301 
 302   inline void lsl(Register Rd, Register Rn, unsigned imm) {
 303     ubfm(Rd, Rn, ((64 - imm) & 63), (63 - imm));
 304   }
 305 
 306   inline void lsrw(Register Rd, Register Rn, unsigned imm) {
 307     ubfmw(Rd, Rn, imm, 31);
 308   }
 309 
 310   inline void lsr(Register Rd, Register Rn, unsigned imm) {
 311     ubfm(Rd, Rn, imm, 63);
 312   }
 313 
 314   inline void rorw(Register Rd, Register Rn, unsigned imm) {
 315     extrw(Rd, Rn, Rn, imm);
 316   }
 317 
 318   inline void ror(Register Rd, Register Rn, unsigned imm) {
 319     extr(Rd, Rn, Rn, imm);
 320   }
 321 
 322   inline void sxtbw(Register Rd, Register Rn) {
 323     sbfmw(Rd, Rn, 0, 7);
 324   }
 325   inline void sxthw(Register Rd, Register Rn) {
 326     sbfmw(Rd, Rn, 0, 15);
 327   }
 328   inline void sxtb(Register Rd, Register Rn) {
 329     sbfm(Rd, Rn, 0, 7);
 330   }
 331   inline void sxth(Register Rd, Register Rn) {
 332     sbfm(Rd, Rn, 0, 15);
 333   }
 334   inline void sxtw(Register Rd, Register Rn) {
 335     sbfm(Rd, Rn, 0, 31);
 336   }
 337 
 338   inline void uxtbw(Register Rd, Register Rn) {
 339     ubfmw(Rd, Rn, 0, 7);
 340   }
 341   inline void uxthw(Register Rd, Register Rn) {
 342     ubfmw(Rd, Rn, 0, 15);
 343   }
 344   inline void uxtb(Register Rd, Register Rn) {
 345     ubfm(Rd, Rn, 0, 7);
 346   }
 347   inline void uxth(Register Rd, Register Rn) {
 348     ubfm(Rd, Rn, 0, 15);
 349   }
 350   inline void uxtw(Register Rd, Register Rn) {
 351     ubfm(Rd, Rn, 0, 31);
 352   }
 353 
 354   inline void cmnw(Register Rn, Register Rm) {
 355     addsw(zr, Rn, Rm);
 356   }
 357   inline void cmn(Register Rn, Register Rm) {
 358     adds(zr, Rn, Rm);
 359   }
 360 
 361   inline void cmpw(Register Rn, Register Rm) {
 362     subsw(zr, Rn, Rm);
 363   }
 364   inline void cmp(Register Rn, Register Rm) {
 365     subs(zr, Rn, Rm);
 366   }
 367 
 368   inline void negw(Register Rd, Register Rn) {
 369     subw(Rd, zr, Rn);
 370   }
 371 
 372   inline void neg(Register Rd, Register Rn) {
 373     sub(Rd, zr, Rn);
 374   }
 375 
 376   inline void negsw(Register Rd, Register Rn) {
 377     subsw(Rd, zr, Rn);
 378   }
 379 
 380   inline void negs(Register Rd, Register Rn) {
 381     subs(Rd, zr, Rn);
 382   }
 383 
 384   inline void cmnw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
 385     addsw(zr, Rn, Rm, kind, shift);
 386   }
 387   inline void cmn(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
 388     adds(zr, Rn, Rm, kind, shift);
 389   }
 390 
 391   inline void cmpw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
 392     subsw(zr, Rn, Rm, kind, shift);
 393   }
 394   inline void cmp(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
 395     subs(zr, Rn, Rm, kind, shift);
 396   }
 397 
 398   inline void negw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
 399     subw(Rd, zr, Rn, kind, shift);
 400   }
 401 
 402   inline void neg(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
 403     sub(Rd, zr, Rn, kind, shift);
 404   }
 405 
 406   inline void negsw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
 407     subsw(Rd, zr, Rn, kind, shift);
 408   }
 409 
 410   inline void negs(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
 411     subs(Rd, zr, Rn, kind, shift);
 412   }
 413 
 414   inline void mnegw(Register Rd, Register Rn, Register Rm) {
 415     msubw(Rd, Rn, Rm, zr);
 416   }
 417   inline void mneg(Register Rd, Register Rn, Register Rm) {
 418     msub(Rd, Rn, Rm, zr);
 419   }
 420 
 421   inline void mulw(Register Rd, Register Rn, Register Rm) {
 422     maddw(Rd, Rn, Rm, zr);
 423   }
 424   inline void mul(Register Rd, Register Rn, Register Rm) {
 425     madd(Rd, Rn, Rm, zr);
 426   }
 427 
 428   inline void smnegl(Register Rd, Register Rn, Register Rm) {
 429     smsubl(Rd, Rn, Rm, zr);
 430   }
 431   inline void smull(Register Rd, Register Rn, Register Rm) {
 432     smaddl(Rd, Rn, Rm, zr);
 433   }
 434 
 435   inline void umnegl(Register Rd, Register Rn, Register Rm) {
 436     umsubl(Rd, Rn, Rm, zr);
 437   }
 438   inline void umull(Register Rd, Register Rn, Register Rm) {
 439     umaddl(Rd, Rn, Rm, zr);
 440   }
 441 
 442 #define WRAP(INSN)                                                            \
 443   void INSN(Register Rd, Register Rn, Register Rm, Register Ra) {             \
 444     if (VM_Version::supports_a53mac() && Ra != zr)                            \
 445       nop();                                                                  \
 446     Assembler::INSN(Rd, Rn, Rm, Ra);                                          \
 447   }
 448 
 449   WRAP(madd) WRAP(msub) WRAP(maddw) WRAP(msubw)
 450   WRAP(smaddl) WRAP(smsubl) WRAP(umaddl) WRAP(umsubl)
 451 #undef WRAP
 452 
 453 
 454   // macro assembly operations needed for aarch64
 455 
 456   // first two private routines for loading 32 bit or 64 bit constants
 457 private:
 458 
 459   void mov_immediate64(Register dst, uint64_t imm64);
 460   void mov_immediate32(Register dst, uint32_t imm32);
 461 
 462   int push(unsigned int bitset, Register stack);
 463   int pop(unsigned int bitset, Register stack);
 464 
 465   int push_fp(unsigned int bitset, Register stack);
 466   int pop_fp(unsigned int bitset, Register stack);
 467 
 468   int push_p(unsigned int bitset, Register stack);
 469   int pop_p(unsigned int bitset, Register stack);
 470 
 471   void mov(Register dst, Address a);
 472 
 473 public:
 474   void push(RegSet regs, Register stack) { if (regs.bits()) push(regs.bits(), stack); }
 475   void pop(RegSet regs, Register stack) { if (regs.bits()) pop(regs.bits(), stack); }
 476 
 477   void push_fp(FloatRegSet regs, Register stack) { if (regs.bits()) push_fp(regs.bits(), stack); }
 478   void pop_fp(FloatRegSet regs, Register stack) { if (regs.bits()) pop_fp(regs.bits(), stack); }
 479 
 480   static RegSet call_clobbered_gp_registers();
 481 
 482   void push_p(PRegSet regs, Register stack) { if (regs.bits()) push_p(regs.bits(), stack); }
 483   void pop_p(PRegSet regs, Register stack) { if (regs.bits()) pop_p(regs.bits(), stack); }
 484 
 485   // Push and pop everything that might be clobbered by a native
 486   // runtime call except rscratch1 and rscratch2.  (They are always
 487   // scratch, so we don't have to protect them.)  Only save the lower
 488   // 64 bits of each vector register. Additional registers can be excluded
 489   // in a passed RegSet.
 490   void push_call_clobbered_registers_except(RegSet exclude);
 491   void pop_call_clobbered_registers_except(RegSet exclude);
 492 
 493   void push_call_clobbered_registers() {
 494     push_call_clobbered_registers_except(RegSet());
 495   }
 496   void pop_call_clobbered_registers() {
 497     pop_call_clobbered_registers_except(RegSet());
 498   }
 499 
 500 
 501   // now mov instructions for loading absolute addresses and 32 or
 502   // 64 bit integers
 503 
 504   inline void mov(Register dst, address addr)             { mov_immediate64(dst, (uint64_t)addr); }
 505 
 506   template<typename T, ENABLE_IF(std::is_integral<T>::value)>
 507   inline void mov(Register dst, T o)                      { mov_immediate64(dst, (uint64_t)o); }
 508 
 509   inline void movw(Register dst, uint32_t imm32)          { mov_immediate32(dst, imm32); }
 510 
 511   void mov(Register dst, RegisterOrConstant src) {
 512     if (src.is_register())
 513       mov(dst, src.as_register());
 514     else
 515       mov(dst, src.as_constant());
 516   }
 517 
 518   void movptr(Register r, uintptr_t imm64);
 519 
 520   void mov(FloatRegister Vd, SIMD_Arrangement T, uint64_t imm64);
 521 
 522   void mov(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) {
 523     orr(Vd, T, Vn, Vn);
 524   }
 525 
 526 
 527 public:
 528 
 529   // Generalized Test Bit And Branch, including a "far" variety which
 530   // spans more than 32KiB.
 531   void tbr(Condition cond, Register Rt, int bitpos, Label &dest, bool isfar = false) {
 532     assert(cond == EQ || cond == NE, "must be");
 533 
 534     if (isfar)
 535       cond = ~cond;
 536 
 537     void (Assembler::* branch)(Register Rt, int bitpos, Label &L);
 538     if (cond == Assembler::EQ)
 539       branch = &Assembler::tbz;
 540     else
 541       branch = &Assembler::tbnz;
 542 
 543     if (isfar) {
 544       Label L;
 545       (this->*branch)(Rt, bitpos, L);
 546       b(dest);
 547       bind(L);
 548     } else {
 549       (this->*branch)(Rt, bitpos, dest);
 550     }
 551   }
 552 
 553   // macro instructions for accessing and updating floating point
 554   // status register
 555   //
 556   // FPSR : op1 == 011
 557   //        CRn == 0100
 558   //        CRm == 0100
 559   //        op2 == 001
 560 
 561   inline void get_fpsr(Register reg)
 562   {
 563     mrs(0b11, 0b0100, 0b0100, 0b001, reg);
 564   }
 565 
 566   inline void set_fpsr(Register reg)
 567   {
 568     msr(0b011, 0b0100, 0b0100, 0b001, reg);
 569   }
 570 
 571   inline void clear_fpsr()
 572   {
 573     msr(0b011, 0b0100, 0b0100, 0b001, zr);
 574   }
 575 
 576   // DCZID_EL0: op1 == 011
 577   //            CRn == 0000
 578   //            CRm == 0000
 579   //            op2 == 111
 580   inline void get_dczid_el0(Register reg)
 581   {
 582     mrs(0b011, 0b0000, 0b0000, 0b111, reg);
 583   }
 584 
 585   // CTR_EL0:   op1 == 011
 586   //            CRn == 0000
 587   //            CRm == 0000
 588   //            op2 == 001
 589   inline void get_ctr_el0(Register reg)
 590   {
 591     mrs(0b011, 0b0000, 0b0000, 0b001, reg);
 592   }
 593 
 594   inline void get_nzcv(Register reg) {
 595     mrs(0b011, 0b0100, 0b0010, 0b000, reg);
 596   }
 597 
 598   inline void set_nzcv(Register reg) {
 599     msr(0b011, 0b0100, 0b0010, 0b000, reg);
 600   }
 601 
 602   // idiv variant which deals with MINLONG as dividend and -1 as divisor
 603   int corrected_idivl(Register result, Register ra, Register rb,
 604                       bool want_remainder, Register tmp = rscratch1);
 605   int corrected_idivq(Register result, Register ra, Register rb,
 606                       bool want_remainder, Register tmp = rscratch1);
 607 
 608   // Support for NULL-checks
 609   //
 610   // Generates code that causes a NULL OS exception if the content of reg is NULL.
 611   // If the accessed location is M[reg + offset] and the offset is known, provide the
 612   // offset. No explicit code generation is needed if the offset is within a certain
 613   // range (0 <= offset <= page_size).
 614 
 615   virtual void null_check(Register reg, int offset = -1);
 616   static bool needs_explicit_null_check(intptr_t offset);
 617   static bool uses_implicit_null_check(void* address);
 618 
 619   static address target_addr_for_insn(address insn_addr, unsigned insn);
 620   static address target_addr_for_insn_or_null(address insn_addr, unsigned insn);
 621   static address target_addr_for_insn(address insn_addr) {
 622     unsigned insn = *(unsigned*)insn_addr;
 623     return target_addr_for_insn(insn_addr, insn);
 624   }
 625   static address target_addr_for_insn_or_null(address insn_addr) {
 626     unsigned insn = *(unsigned*)insn_addr;
 627     return target_addr_for_insn_or_null(insn_addr, insn);
 628   }
 629 
 630   // Required platform-specific helpers for Label::patch_instructions.
 631   // They _shadow_ the declarations in AbstractAssembler, which are undefined.
 632   static int pd_patch_instruction_size(address branch, address target);
 633   static void pd_patch_instruction(address branch, address target, const char* file = NULL, int line = 0) {
 634     pd_patch_instruction_size(branch, target);
 635   }
 636   static address pd_call_destination(address branch) {
 637     return target_addr_for_insn(branch);
 638   }
 639 #ifndef PRODUCT
 640   static void pd_print_patched_instruction(address branch);
 641 #endif
 642 
 643   static int patch_oop(address insn_addr, address o);
 644   static int patch_narrow_klass(address insn_addr, narrowKlass n);
 645 
 646   // Return whether code is emitted to a scratch blob.
 647   virtual bool in_scratch_emit_size() {
 648     return false;
 649   }
 650   address emit_trampoline_stub(int insts_call_instruction_offset, address target);
 651   static int max_trampoline_stub_size();
 652   void emit_static_call_stub();
 653   static int static_call_stub_size();
 654 
 655   // The following 4 methods return the offset of the appropriate move instruction
 656 
 657   // Support for fast byte/short loading with zero extension (depending on particular CPU)
 658   int load_unsigned_byte(Register dst, Address src);
 659   int load_unsigned_short(Register dst, Address src);
 660 
 661   // Support for fast byte/short loading with sign extension (depending on particular CPU)
 662   int load_signed_byte(Register dst, Address src);
 663   int load_signed_short(Register dst, Address src);
 664 
 665   int load_signed_byte32(Register dst, Address src);
 666   int load_signed_short32(Register dst, Address src);
 667 
 668   // Support for sign-extension (hi:lo = extend_sign(lo))
 669   void extend_sign(Register hi, Register lo);
 670 
 671   // Load and store values by size and signed-ness
 672   void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed);
 673   void store_sized_value(Address dst, Register src, size_t size_in_bytes);
 674 
 675   // Support for inc/dec with optimal instruction selection depending on value
 676 
 677   // x86_64 aliases an unqualified register/address increment and
 678   // decrement to call incrementq and decrementq but also supports
 679   // explicitly sized calls to incrementq/decrementq or
 680   // incrementl/decrementl
 681 
 682   // for aarch64 the proper convention would be to use
 683   // increment/decrement for 64 bit operations and
 684   // incrementw/decrementw for 32 bit operations. so when porting
 685   // x86_64 code we can leave calls to increment/decrement as is,
 686   // replace incrementq/decrementq with increment/decrement and
 687   // replace incrementl/decrementl with incrementw/decrementw.
 688 
 689   // n.b. increment/decrement calls with an Address destination will
 690   // need to use a scratch register to load the value to be
 691   // incremented. increment/decrement calls which add or subtract a
 692   // constant value greater than 2^12 will need to use a 2nd scratch
 693   // register to hold the constant. so, a register increment/decrement
 694   // may trash rscratch2 and an address increment/decrement trash
 695   // rscratch and rscratch2
 696 
 697   void decrementw(Address dst, int value = 1);
 698   void decrementw(Register reg, int value = 1);
 699 
 700   void decrement(Register reg, int value = 1);
 701   void decrement(Address dst, int value = 1);
 702 
 703   void incrementw(Address dst, int value = 1);
 704   void incrementw(Register reg, int value = 1);
 705 
 706   void increment(Register reg, int value = 1);
 707   void increment(Address dst, int value = 1);
 708 
 709 
 710   // Alignment
 711   void align(int modulus);
 712 
 713   // nop
 714   void post_call_nop();
 715 
 716   // Stack frame creation/removal
 717   void enter(bool strip_ret_addr = false);
 718   void leave();
 719 
 720   // ROP Protection
 721   void protect_return_address();
 722   void protect_return_address(Register return_reg, Register temp_reg);
 723   void authenticate_return_address(Register return_reg = lr);
 724   void authenticate_return_address(Register return_reg, Register temp_reg);
 725   void strip_return_address();
 726   void check_return_address(Register return_reg=lr) PRODUCT_RETURN;
 727 
 728   // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
 729   // The pointer will be loaded into the thread register.
 730   void get_thread(Register thread);
 731 
 732   // support for argument shuffling
 733   void move32_64(VMRegPair src, VMRegPair dst, Register tmp = rscratch1);
 734   void float_move(VMRegPair src, VMRegPair dst, Register tmp = rscratch1);
 735   void long_move(VMRegPair src, VMRegPair dst, Register tmp = rscratch1);
 736   void double_move(VMRegPair src, VMRegPair dst, Register tmp = rscratch1);
 737   void object_move(
 738                    OopMap* map,
 739                    int oop_handle_offset,
 740                    int framesize_in_slots,
 741                    VMRegPair src,
 742                    VMRegPair dst,
 743                    bool is_receiver,
 744                    int* receiver_offset);
 745 
 746 
 747   // Support for VM calls
 748   //
 749   // It is imperative that all calls into the VM are handled via the call_VM macros.
 750   // They make sure that the stack linkage is setup correctly. call_VM's correspond
 751   // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
 752 
 753 
 754   void call_VM(Register oop_result,
 755                address entry_point,
 756                bool check_exceptions = true);
 757   void call_VM(Register oop_result,
 758                address entry_point,
 759                Register arg_1,
 760                bool check_exceptions = true);
 761   void call_VM(Register oop_result,
 762                address entry_point,
 763                Register arg_1, Register arg_2,
 764                bool check_exceptions = true);
 765   void call_VM(Register oop_result,
 766                address entry_point,
 767                Register arg_1, Register arg_2, Register arg_3,
 768                bool check_exceptions = true);
 769 
 770   // Overloadings with last_Java_sp
 771   void call_VM(Register oop_result,
 772                Register last_java_sp,
 773                address entry_point,
 774                int number_of_arguments = 0,
 775                bool check_exceptions = true);
 776   void call_VM(Register oop_result,
 777                Register last_java_sp,
 778                address entry_point,
 779                Register arg_1, bool
 780                check_exceptions = true);
 781   void call_VM(Register oop_result,
 782                Register last_java_sp,
 783                address entry_point,
 784                Register arg_1, Register arg_2,
 785                bool check_exceptions = true);
 786   void call_VM(Register oop_result,
 787                Register last_java_sp,
 788                address entry_point,
 789                Register arg_1, Register arg_2, Register arg_3,
 790                bool check_exceptions = true);
 791 
 792   void get_vm_result  (Register oop_result, Register thread);
 793   void get_vm_result_2(Register metadata_result, Register thread);
 794 
 795   // These always tightly bind to MacroAssembler::call_VM_base
 796   // bypassing the virtual implementation
 797   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
 798   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
 799   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
 800   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
 801   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
 802 
 803   void call_VM_leaf(address entry_point,
 804                     int number_of_arguments = 0);
 805   void call_VM_leaf(address entry_point,
 806                     Register arg_1);
 807   void call_VM_leaf(address entry_point,
 808                     Register arg_1, Register arg_2);
 809   void call_VM_leaf(address entry_point,
 810                     Register arg_1, Register arg_2, Register arg_3);
 811 
 812   // These always tightly bind to MacroAssembler::call_VM_leaf_base
 813   // bypassing the virtual implementation
 814   void super_call_VM_leaf(address entry_point);
 815   void super_call_VM_leaf(address entry_point, Register arg_1);
 816   void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
 817   void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
 818   void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
 819 
 820   // last Java Frame (fills frame anchor)
 821   void set_last_Java_frame(Register last_java_sp,
 822                            Register last_java_fp,
 823                            address last_java_pc,
 824                            Register scratch);
 825 
 826   void set_last_Java_frame(Register last_java_sp,
 827                            Register last_java_fp,
 828                            Label &last_java_pc,
 829                            Register scratch);
 830 
 831   void set_last_Java_frame(Register last_java_sp,
 832                            Register last_java_fp,
 833                            Register last_java_pc,
 834                            Register scratch);
 835 
 836   void reset_last_Java_frame(Register thread);
 837 
 838   // thread in the default location (rthread)
 839   void reset_last_Java_frame(bool clear_fp);
 840 
 841   // Stores
 842   void store_check(Register obj);                // store check for obj - register is destroyed afterwards
 843   void store_check(Register obj, Address dst);   // same as above, dst is exact store location (reg. is destroyed)
 844 
 845   void resolve_jobject(Register value, Register tmp1, Register tmp2);
 846   void resolve_global_jobject(Register value, Register tmp1, Register tmp2);
 847 
 848   // C 'boolean' to Java boolean: x == 0 ? 0 : 1
 849   void c2bool(Register x);
 850 
 851   void load_method_holder_cld(Register rresult, Register rmethod);
 852   void load_method_holder(Register holder, Register method);
 853 
 854   // oop manipulations
 855   void load_nklass(Register dst, Register src);
 856   void load_klass(Register dst, Register src);
 857   void load_klass_check_null(Register dst, Register src);
 858   void store_klass(Register dst, Register src);
 859   void cmp_klass(Register oop, Register trial_klass, Register tmp);
 860 
 861   void resolve_weak_handle(Register result, Register tmp1, Register tmp2);
 862   void resolve_oop_handle(Register result, Register tmp1, Register tmp2);
 863   void load_mirror(Register dst, Register method, Register tmp1, Register tmp2);
 864 
 865   void access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
 866                       Register tmp1, Register tmp2);
 867 
 868   void access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register val,
 869                        Register tmp1, Register tmp2, Register tmp3);
 870 
 871   void load_heap_oop(Register dst, Address src, Register tmp1,
 872                      Register tmp2, DecoratorSet decorators = 0);
 873 
 874   void load_heap_oop_not_null(Register dst, Address src, Register tmp1,
 875                               Register tmp2, DecoratorSet decorators = 0);
 876   void store_heap_oop(Address dst, Register val, Register tmp1,
 877                       Register tmp2, Register tmp3, DecoratorSet decorators = 0);
 878 
 879   // currently unimplemented
 880   // Used for storing NULL. All other oop constants should be
 881   // stored using routines that take a jobject.
 882   void store_heap_oop_null(Address dst);
 883 
 884   void store_klass_gap(Register dst, Register src);
 885 
 886   // This dummy is to prevent a call to store_heap_oop from
 887   // converting a zero (like NULL) into a Register by giving
 888   // the compiler two choices it can't resolve
 889 
 890   void store_heap_oop(Address dst, void* dummy);
 891 
 892   void encode_heap_oop(Register d, Register s);
 893   void encode_heap_oop(Register r) { encode_heap_oop(r, r); }
 894   void decode_heap_oop(Register d, Register s);
 895   void decode_heap_oop(Register r) { decode_heap_oop(r, r); }
 896   void encode_heap_oop_not_null(Register r);
 897   void decode_heap_oop_not_null(Register r);
 898   void encode_heap_oop_not_null(Register dst, Register src);
 899   void decode_heap_oop_not_null(Register dst, Register src);
 900 
 901   void set_narrow_oop(Register dst, jobject obj);
 902 
 903   void encode_klass_not_null(Register r);
 904   void decode_klass_not_null(Register r);
 905   void encode_klass_not_null(Register dst, Register src);
 906   void decode_klass_not_null(Register dst, Register src);
 907 
 908   void set_narrow_klass(Register dst, Klass* k);
 909 
 910   // if heap base register is used - reinit it with the correct value
 911   void reinit_heapbase();
 912 
 913   DEBUG_ONLY(void verify_heapbase(const char* msg);)
 914 
 915   void push_CPU_state(bool save_vectors = false, bool use_sve = false,
 916                       int sve_vector_size_in_bytes = 0, int total_predicate_in_bytes = 0);
 917   void pop_CPU_state(bool restore_vectors = false, bool use_sve = false,
 918                      int sve_vector_size_in_bytes = 0, int total_predicate_in_bytes = 0);
 919 
 920   void push_cont_fastpath(Register java_thread);
 921   void pop_cont_fastpath(Register java_thread);
 922 
 923   // Round up to a power of two
 924   void round_to(Register reg, int modulus);
 925 
 926   // java.lang.Math::round intrinsics
 927   void java_round_double(Register dst, FloatRegister src, FloatRegister ftmp);
 928   void java_round_float(Register dst, FloatRegister src, FloatRegister ftmp);
 929 
 930   // allocation
 931   void tlab_allocate(
 932     Register obj,                      // result: pointer to object after successful allocation
 933     Register var_size_in_bytes,        // object size in bytes if unknown at compile time; invalid otherwise
 934     int      con_size_in_bytes,        // object size in bytes if   known at compile time
 935     Register t1,                       // temp register
 936     Register t2,                       // temp register
 937     Label&   slow_case                 // continuation point if fast allocation fails
 938   );
 939   void verify_tlab();
 940 
 941   // interface method calling
 942   void lookup_interface_method(Register recv_klass,
 943                                Register intf_klass,
 944                                RegisterOrConstant itable_index,
 945                                Register method_result,
 946                                Register scan_temp,
 947                                Label& no_such_interface,
 948                    bool return_method = true);
 949 
 950   // virtual method calling
 951   // n.b. x86 allows RegisterOrConstant for vtable_index
 952   void lookup_virtual_method(Register recv_klass,
 953                              RegisterOrConstant vtable_index,
 954                              Register method_result);
 955 
 956   // Test sub_klass against super_klass, with fast and slow paths.
 957 
 958   // The fast path produces a tri-state answer: yes / no / maybe-slow.
 959   // One of the three labels can be NULL, meaning take the fall-through.
 960   // If super_check_offset is -1, the value is loaded up from super_klass.
 961   // No registers are killed, except temp_reg.
 962   void check_klass_subtype_fast_path(Register sub_klass,
 963                                      Register super_klass,
 964                                      Register temp_reg,
 965                                      Label* L_success,
 966                                      Label* L_failure,
 967                                      Label* L_slow_path,
 968                 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
 969 
 970   // The rest of the type check; must be wired to a corresponding fast path.
 971   // It does not repeat the fast path logic, so don't use it standalone.
 972   // The temp_reg and temp2_reg can be noreg, if no temps are available.
 973   // Updates the sub's secondary super cache as necessary.
 974   // If set_cond_codes, condition codes will be Z on success, NZ on failure.
 975   void check_klass_subtype_slow_path(Register sub_klass,
 976                                      Register super_klass,
 977                                      Register temp_reg,
 978                                      Register temp2_reg,
 979                                      Label* L_success,
 980                                      Label* L_failure,
 981                                      bool set_cond_codes = false);
 982 
 983   // Simplified, combined version, good for typical uses.
 984   // Falls through on failure.
 985   void check_klass_subtype(Register sub_klass,
 986                            Register super_klass,
 987                            Register temp_reg,
 988                            Label& L_success);
 989 
 990   void clinit_barrier(Register klass,
 991                       Register thread,
 992                       Label* L_fast_path = NULL,
 993                       Label* L_slow_path = NULL);
 994 
 995   Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
 996 
 997   void verify_sve_vector_length(Register tmp = rscratch1);
 998   void reinitialize_ptrue() {
 999     if (UseSVE > 0) {
1000       sve_ptrue(ptrue, B);
1001     }
1002   }
1003   void verify_ptrue();
1004 
1005   // Debugging
1006 
1007   // only if +VerifyOops
1008   void _verify_oop(Register reg, const char* s, const char* file, int line);
1009   void _verify_oop_addr(Address addr, const char * s, const char* file, int line);
1010 
1011   void _verify_oop_checked(Register reg, const char* s, const char* file, int line) {
1012     if (VerifyOops) {
1013       _verify_oop(reg, s, file, line);
1014     }
1015   }
1016   void _verify_oop_addr_checked(Address reg, const char* s, const char* file, int line) {
1017     if (VerifyOops) {
1018       _verify_oop_addr(reg, s, file, line);
1019     }
1020   }
1021 
1022 // TODO: verify method and klass metadata (compare against vptr?)
1023   void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
1024   void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
1025 
1026 #define verify_oop(reg) _verify_oop_checked(reg, "broken oop " #reg, __FILE__, __LINE__)
1027 #define verify_oop_msg(reg, msg) _verify_oop_checked(reg, "broken oop " #reg ", " #msg, __FILE__, __LINE__)
1028 #define verify_oop_addr(addr) _verify_oop_addr_checked(addr, "broken oop addr " #addr, __FILE__, __LINE__)
1029 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
1030 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
1031 
1032   // only if +VerifyFPU
1033   void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
1034 
1035   // prints msg, dumps registers and stops execution
1036   void stop(const char* msg);
1037 
1038   static void debug64(char* msg, int64_t pc, int64_t regs[]);
1039 
1040   void untested()                                { stop("untested"); }
1041 
1042   void unimplemented(const char* what = "");
1043 
1044   void should_not_reach_here()                   { stop("should not reach here"); }
1045 
1046   void _assert_asm(Condition cc, const char* msg);
1047 #define assert_asm0(cc, msg) _assert_asm(cc, FILE_AND_LINE ": " msg)
1048 #define assert_asm(masm, command, cc, msg) DEBUG_ONLY(command; (masm)->_assert_asm(cc, FILE_AND_LINE ": " #command " " #cc ": " msg))
1049 
1050   // Stack overflow checking
1051   void bang_stack_with_offset(int offset) {
1052     // stack grows down, caller passes positive offset
1053     assert(offset > 0, "must bang with negative offset");
1054     sub(rscratch2, sp, offset);
1055     str(zr, Address(rscratch2));
1056   }
1057 
1058   // Writes to stack successive pages until offset reached to check for
1059   // stack overflow + shadow pages.  Also, clobbers tmp
1060   void bang_stack_size(Register size, Register tmp);
1061 
1062   // Check for reserved stack access in method being exited (for JIT)
1063   void reserved_stack_check();
1064 
1065   // Arithmetics
1066 
1067   void addptr(const Address &dst, int32_t src);
1068   void cmpptr(Register src1, Address src2);
1069 
1070   void cmpoop(Register obj1, Register obj2);
1071 
1072   // Various forms of CAS
1073 
1074   void cmpxchg_obj_header(Register oldv, Register newv, Register obj, Register tmp,
1075                           Label &succeed, Label *fail);
1076   void cmpxchgptr(Register oldv, Register newv, Register addr, Register tmp,
1077                   Label &succeed, Label *fail);
1078 
1079   void cmpxchgw(Register oldv, Register newv, Register addr, Register tmp,
1080                   Label &succeed, Label *fail);
1081 
1082   void atomic_add(Register prev, RegisterOrConstant incr, Register addr);
1083   void atomic_addw(Register prev, RegisterOrConstant incr, Register addr);
1084   void atomic_addal(Register prev, RegisterOrConstant incr, Register addr);
1085   void atomic_addalw(Register prev, RegisterOrConstant incr, Register addr);
1086 
1087   void atomic_xchg(Register prev, Register newv, Register addr);
1088   void atomic_xchgw(Register prev, Register newv, Register addr);
1089   void atomic_xchgl(Register prev, Register newv, Register addr);
1090   void atomic_xchglw(Register prev, Register newv, Register addr);
1091   void atomic_xchgal(Register prev, Register newv, Register addr);
1092   void atomic_xchgalw(Register prev, Register newv, Register addr);
1093 
1094   void orptr(Address adr, RegisterOrConstant src) {
1095     ldr(rscratch1, adr);
1096     if (src.is_register())
1097       orr(rscratch1, rscratch1, src.as_register());
1098     else
1099       orr(rscratch1, rscratch1, src.as_constant());
1100     str(rscratch1, adr);
1101   }
1102 
1103   // A generic CAS; success or failure is in the EQ flag.
1104   // Clobbers rscratch1
1105   void cmpxchg(Register addr, Register expected, Register new_val,
1106                enum operand_size size,
1107                bool acquire, bool release, bool weak,
1108                Register result);
1109 
1110 #ifdef ASSERT
1111   // Template short-hand support to clean-up after a failed call to trampoline
1112   // call generation (see trampoline_call() below),  when a set of Labels must
1113   // be reset (before returning).
1114   template<typename Label, typename... More>
1115   void reset_labels(Label &lbl, More&... more) {
1116     lbl.reset(); reset_labels(more...);
1117   }
1118   template<typename Label>
1119   void reset_labels(Label &lbl) {
1120     lbl.reset();
1121   }
1122 #endif
1123 
1124 private:
1125   void compare_eq(Register rn, Register rm, enum operand_size size);
1126 
1127 public:
1128   // AArch64 OpenJDK uses four different types of calls:
1129   //   - direct call: bl pc_relative_offset
1130   //     This is the shortest and the fastest, but the offset has the range:
1131   //     +/-128MB for the release build, +/-2MB for the debug build.
1132   //
1133   //   - far call: adrp reg, pc_relative_offset; add; bl reg
1134   //     This is longer than a direct call. The offset has
1135   //     the range +/-4GB. As the code cache size is limited to 4GB,
1136   //     far calls can reach anywhere in the code cache. If a jump is
1137   //     needed rather than a call, a far jump 'b reg' can be used instead.
1138   //     All instructions are embedded at a call site.
1139   //
1140   //   - trampoline call:
1141   //     This is only available in C1/C2-generated code (nmethod). It is a combination
1142   //     of a direct call, which is used if the destination of a call is in range,
1143   //     and a register-indirect call. It has the advantages of reaching anywhere in
1144   //     the AArch64 address space and being patchable at runtime when the generated
1145   //     code is being executed by other threads.
1146   //
1147   //     [Main code section]
1148   //       bl trampoline
1149   //     [Stub code section]
1150   //     trampoline:
1151   //       ldr reg, pc + 8
1152   //       br reg
1153   //       <64-bit destination address>
1154   //
1155   //     If the destination is in range when the generated code is moved to the code
1156   //     cache, 'bl trampoline' is replaced with 'bl destination' and the trampoline
1157   //     is not used.
1158   //     The optimization does not remove the trampoline from the stub section.
1159   //     This is necessary because the trampoline may well be redirected later when
1160   //     code is patched, and the new destination may not be reachable by a simple BR
1161   //     instruction.
1162   //
1163   //   - indirect call: move reg, address; blr reg
1164   //     This too can reach anywhere in the address space, but it cannot be
1165   //     patched while code is running, so it must only be modified at a safepoint.
1166   //     This form of call is most suitable for targets at fixed addresses, which
1167   //     will never be patched.
1168   //
1169   // The patching we do conforms to the "Concurrent modification and
1170   // execution of instructions" section of the Arm Architectural
1171   // Reference Manual, which only allows B, BL, BRK, HVC, ISB, NOP, SMC,
1172   // or SVC instructions to be modified while another thread is
1173   // executing them.
1174   //
1175   // To patch a trampoline call when the BL can't reach, we first modify
1176   // the 64-bit destination address in the trampoline, then modify the
1177   // BL to point to the trampoline, then flush the instruction cache to
1178   // broadcast the change to all executing threads. See
1179   // NativeCall::set_destination_mt_safe for the details.
1180   //
1181   // There is a benign race in that the other thread might observe the
1182   // modified BL before it observes the modified 64-bit destination
1183   // address. That does not matter because the destination method has been
1184   // invalidated, so there will be a trap at its start.
1185   // For this to work, the destination address in the trampoline is
1186   // always updated, even if we're not using the trampoline.
1187 
1188   // Emit a direct call if the entry address will always be in range,
1189   // otherwise a trampoline call.
1190   // Supported entry.rspec():
1191   // - relocInfo::runtime_call_type
1192   // - relocInfo::opt_virtual_call_type
1193   // - relocInfo::static_call_type
1194   // - relocInfo::virtual_call_type
1195   //
1196   // Return: the call PC or NULL if CodeCache is full.
1197   address trampoline_call(Address entry);
1198 
1199   static bool far_branches() {
1200     return ReservedCodeCacheSize > branch_range;
1201   }
1202 
1203   // Check if branches to the non nmethod section require a far jump
1204   static bool codestub_branch_needs_far_jump() {
1205     return CodeCache::max_distance_to_non_nmethod() > branch_range;
1206   }
1207 
1208   // Emit a direct call/jump if the entry address will always be in range,
1209   // otherwise a far call/jump.
1210   // The address must be inside the code cache.
1211   // Supported entry.rspec():
1212   // - relocInfo::external_word_type
1213   // - relocInfo::runtime_call_type
1214   // - relocInfo::none
1215   // In the case of a far call/jump, the entry address is put in the tmp register.
1216   // The tmp register is invalidated.
1217   //
1218   // Far_jump returns the amount of the emitted code.
1219   void far_call(Address entry, Register tmp = rscratch1);
1220   int far_jump(Address entry, Register tmp = rscratch1);
1221 
1222   static int far_codestub_branch_size() {
1223     if (codestub_branch_needs_far_jump()) {
1224       return 3 * 4;  // adrp, add, br
1225     } else {
1226       return 4;
1227     }
1228   }
1229 
1230   // Emit the CompiledIC call idiom
1231   address ic_call(address entry, jint method_index = 0);
1232 
1233 public:
1234 
1235   // Data
1236 
1237   void mov_metadata(Register dst, Metadata* obj);
1238   Address allocate_metadata_address(Metadata* obj);
1239   Address constant_oop_address(jobject obj);
1240 
1241   void movoop(Register dst, jobject obj);
1242 
1243   // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
1244   void kernel_crc32(Register crc, Register buf, Register len,
1245         Register table0, Register table1, Register table2, Register table3,
1246         Register tmp, Register tmp2, Register tmp3);
1247   // CRC32 code for java.util.zip.CRC32C::updateBytes() intrinsic.
1248   void kernel_crc32c(Register crc, Register buf, Register len,
1249         Register table0, Register table1, Register table2, Register table3,
1250         Register tmp, Register tmp2, Register tmp3);
1251 
1252   // Stack push and pop individual 64 bit registers
1253   void push(Register src);
1254   void pop(Register dst);
1255 
1256   void repne_scan(Register addr, Register value, Register count,
1257                   Register scratch);
1258   void repne_scanw(Register addr, Register value, Register count,
1259                    Register scratch);
1260 
1261   typedef void (MacroAssembler::* add_sub_imm_insn)(Register Rd, Register Rn, unsigned imm);
1262   typedef void (MacroAssembler::* add_sub_reg_insn)(Register Rd, Register Rn, Register Rm, enum shift_kind kind, unsigned shift);
1263 
1264   // If a constant does not fit in an immediate field, generate some
1265   // number of MOV instructions and then perform the operation
1266   void wrap_add_sub_imm_insn(Register Rd, Register Rn, uint64_t imm,
1267                              add_sub_imm_insn insn1,
1268                              add_sub_reg_insn insn2, bool is32);
1269   // Separate vsn which sets the flags
1270   void wrap_adds_subs_imm_insn(Register Rd, Register Rn, uint64_t imm,
1271                                add_sub_imm_insn insn1,
1272                                add_sub_reg_insn insn2, bool is32);
1273 
1274 #define WRAP(INSN, is32)                                                \
1275   void INSN(Register Rd, Register Rn, uint64_t imm) {                   \
1276     wrap_add_sub_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN, is32); \
1277   }                                                                     \
1278                                                                         \
1279   void INSN(Register Rd, Register Rn, Register Rm,                      \
1280              enum shift_kind kind, unsigned shift = 0) {                \
1281     Assembler::INSN(Rd, Rn, Rm, kind, shift);                           \
1282   }                                                                     \
1283                                                                         \
1284   void INSN(Register Rd, Register Rn, Register Rm) {                    \
1285     Assembler::INSN(Rd, Rn, Rm);                                        \
1286   }                                                                     \
1287                                                                         \
1288   void INSN(Register Rd, Register Rn, Register Rm,                      \
1289            ext::operation option, int amount = 0) {                     \
1290     Assembler::INSN(Rd, Rn, Rm, option, amount);                        \
1291   }
1292 
1293   WRAP(add, false) WRAP(addw, true) WRAP(sub, false) WRAP(subw, true)
1294 
1295 #undef WRAP
1296 #define WRAP(INSN, is32)                                                \
1297   void INSN(Register Rd, Register Rn, uint64_t imm) {                   \
1298     wrap_adds_subs_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN, is32); \
1299   }                                                                     \
1300                                                                         \
1301   void INSN(Register Rd, Register Rn, Register Rm,                      \
1302              enum shift_kind kind, unsigned shift = 0) {                \
1303     Assembler::INSN(Rd, Rn, Rm, kind, shift);                           \
1304   }                                                                     \
1305                                                                         \
1306   void INSN(Register Rd, Register Rn, Register Rm) {                    \
1307     Assembler::INSN(Rd, Rn, Rm);                                        \
1308   }                                                                     \
1309                                                                         \
1310   void INSN(Register Rd, Register Rn, Register Rm,                      \
1311            ext::operation option, int amount = 0) {                     \
1312     Assembler::INSN(Rd, Rn, Rm, option, amount);                        \
1313   }
1314 
1315   WRAP(adds, false) WRAP(addsw, true) WRAP(subs, false) WRAP(subsw, true)
1316 
1317   void add(Register Rd, Register Rn, RegisterOrConstant increment);
1318   void addw(Register Rd, Register Rn, RegisterOrConstant increment);
1319   void sub(Register Rd, Register Rn, RegisterOrConstant decrement);
1320   void subw(Register Rd, Register Rn, RegisterOrConstant decrement);
1321 
1322   void adrp(Register reg1, const Address &dest, uint64_t &byte_offset);
1323 
1324   void tableswitch(Register index, jint lowbound, jint highbound,
1325                    Label &jumptable, Label &jumptable_end, int stride = 1) {
1326     adr(rscratch1, jumptable);
1327     subsw(rscratch2, index, lowbound);
1328     subsw(zr, rscratch2, highbound - lowbound);
1329     br(Assembler::HS, jumptable_end);
1330     add(rscratch1, rscratch1, rscratch2,
1331         ext::sxtw, exact_log2(stride * Assembler::instruction_size));
1332     br(rscratch1);
1333   }
1334 
1335   // Form an address from base + offset in Rd.  Rd may or may not
1336   // actually be used: you must use the Address that is returned.  It
1337   // is up to you to ensure that the shift provided matches the size
1338   // of your data.
1339   Address form_address(Register Rd, Register base, int64_t byte_offset, int shift);
1340 
1341   // Return true iff an address is within the 48-bit AArch64 address
1342   // space.
1343   bool is_valid_AArch64_address(address a) {
1344     return ((uint64_t)a >> 48) == 0;
1345   }
1346 
1347   // Load the base of the cardtable byte map into reg.
1348   void load_byte_map_base(Register reg);
1349 
1350   // Prolog generator routines to support switch between x86 code and
1351   // generated ARM code
1352 
1353   // routine to generate an x86 prolog for a stub function which
1354   // bootstraps into the generated ARM code which directly follows the
1355   // stub
1356   //
1357 
1358   public:
1359 
1360   void ldr_constant(Register dest, const Address &const_addr) {
1361     if (NearCpool) {
1362       ldr(dest, const_addr);
1363     } else {
1364       uint64_t offset;
1365       adrp(dest, InternalAddress(const_addr.target()), offset);
1366       ldr(dest, Address(dest, offset));
1367     }
1368   }
1369 
1370   address read_polling_page(Register r, relocInfo::relocType rtype);
1371   void get_polling_page(Register dest, relocInfo::relocType rtype);
1372 
1373   // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
1374   void update_byte_crc32(Register crc, Register val, Register table);
1375   void update_word_crc32(Register crc, Register v, Register tmp,
1376         Register table0, Register table1, Register table2, Register table3,
1377         bool upper = false);
1378 
1379   address count_positives(Register ary1, Register len, Register result);
1380 
1381   address arrays_equals(Register a1, Register a2, Register result, Register cnt1,
1382                         Register tmp1, Register tmp2, Register tmp3, int elem_size);
1383 
1384   void string_equals(Register a1, Register a2, Register result, Register cnt1,
1385                      int elem_size);
1386 
1387   void fill_words(Register base, Register cnt, Register value);
1388   address zero_words(Register base, uint64_t cnt);
1389   address zero_words(Register ptr, Register cnt);
1390   void zero_dcache_blocks(Register base, Register cnt);
1391 
1392   static const int zero_words_block_size;
1393 
1394   address byte_array_inflate(Register src, Register dst, Register len,
1395                              FloatRegister vtmp1, FloatRegister vtmp2,
1396                              FloatRegister vtmp3, Register tmp4);
1397 
1398   void char_array_compress(Register src, Register dst, Register len,
1399                            Register res,
1400                            FloatRegister vtmp0, FloatRegister vtmp1,
1401                            FloatRegister vtmp2, FloatRegister vtmp3);
1402 
1403   void encode_iso_array(Register src, Register dst,
1404                         Register len, Register res, bool ascii,
1405                         FloatRegister vtmp0, FloatRegister vtmp1,
1406                         FloatRegister vtmp2, FloatRegister vtmp3);
1407 
1408   void fast_log(FloatRegister vtmp0, FloatRegister vtmp1, FloatRegister vtmp2,
1409                 FloatRegister vtmp3, FloatRegister vtmp4, FloatRegister vtmp5,
1410                 FloatRegister tmpC1, FloatRegister tmpC2, FloatRegister tmpC3,
1411                 FloatRegister tmpC4, Register tmp1, Register tmp2,
1412                 Register tmp3, Register tmp4, Register tmp5);
1413   void generate_dsin_dcos(bool isCos, address npio2_hw, address two_over_pi,
1414       address pio2, address dsin_coef, address dcos_coef);
1415  private:
1416   // begin trigonometric functions support block
1417   void generate__ieee754_rem_pio2(address npio2_hw, address two_over_pi, address pio2);
1418   void generate__kernel_rem_pio2(address two_over_pi, address pio2);
1419   void generate_kernel_sin(FloatRegister x, bool iyIsOne, address dsin_coef);
1420   void generate_kernel_cos(FloatRegister x, address dcos_coef);
1421   // end trigonometric functions support block
1422   void add2_with_carry(Register final_dest_hi, Register dest_hi, Register dest_lo,
1423                        Register src1, Register src2);
1424   void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
1425     add2_with_carry(dest_hi, dest_hi, dest_lo, src1, src2);
1426   }
1427   void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
1428                              Register y, Register y_idx, Register z,
1429                              Register carry, Register product,
1430                              Register idx, Register kdx);
1431   void multiply_128_x_128_loop(Register y, Register z,
1432                                Register carry, Register carry2,
1433                                Register idx, Register jdx,
1434                                Register yz_idx1, Register yz_idx2,
1435                                Register tmp, Register tmp3, Register tmp4,
1436                                Register tmp7, Register product_hi);
1437   void kernel_crc32_using_crypto_pmull(Register crc, Register buf,
1438         Register len, Register tmp0, Register tmp1, Register tmp2,
1439         Register tmp3);
1440   void kernel_crc32_using_crc32(Register crc, Register buf,
1441         Register len, Register tmp0, Register tmp1, Register tmp2,
1442         Register tmp3);
1443   void kernel_crc32c_using_crc32c(Register crc, Register buf,
1444         Register len, Register tmp0, Register tmp1, Register tmp2,
1445         Register tmp3);
1446   void kernel_crc32_common_fold_using_crypto_pmull(Register crc, Register buf,
1447         Register len, Register tmp0, Register tmp1, Register tmp2,
1448         size_t table_offset);
1449 
1450   void ghash_modmul (FloatRegister result,
1451                      FloatRegister result_lo, FloatRegister result_hi, FloatRegister b,
1452                      FloatRegister a, FloatRegister vzr, FloatRegister a1_xor_a0, FloatRegister p,
1453                      FloatRegister t1, FloatRegister t2, FloatRegister t3);
1454   void ghash_load_wide(int index, Register data, FloatRegister result, FloatRegister state);
1455 public:
1456   void multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z,
1457                        Register zlen, Register tmp1, Register tmp2, Register tmp3,
1458                        Register tmp4, Register tmp5, Register tmp6, Register tmp7);
1459   void mul_add(Register out, Register in, Register offs, Register len, Register k);
1460   void ghash_multiply(FloatRegister result_lo, FloatRegister result_hi,
1461                       FloatRegister a, FloatRegister b, FloatRegister a1_xor_a0,
1462                       FloatRegister tmp1, FloatRegister tmp2, FloatRegister tmp3);
1463   void ghash_multiply_wide(int index,
1464                            FloatRegister result_lo, FloatRegister result_hi,
1465                            FloatRegister a, FloatRegister b, FloatRegister a1_xor_a0,
1466                            FloatRegister tmp1, FloatRegister tmp2, FloatRegister tmp3);
1467   void ghash_reduce(FloatRegister result, FloatRegister lo, FloatRegister hi,
1468                     FloatRegister p, FloatRegister z, FloatRegister t1);
1469   void ghash_reduce_wide(int index, FloatRegister result, FloatRegister lo, FloatRegister hi,
1470                     FloatRegister p, FloatRegister z, FloatRegister t1);
1471   void ghash_processBlocks_wide(address p, Register state, Register subkeyH,
1472                                 Register data, Register blocks, int unrolls);
1473 
1474 
1475   void aesenc_loadkeys(Register key, Register keylen);
1476   void aesecb_encrypt(Register from, Register to, Register keylen,
1477                       FloatRegister data = v0, int unrolls = 1);
1478   void aesecb_decrypt(Register from, Register to, Register key, Register keylen);
1479   void aes_round(FloatRegister input, FloatRegister subkey);
1480 
1481   // ChaCha20 functions support block
1482   void cc20_quarter_round(FloatRegister aVec, FloatRegister bVec,
1483           FloatRegister cVec, FloatRegister dVec, FloatRegister scratch,
1484           FloatRegister tbl);
1485   void cc20_shift_lane_org(FloatRegister bVec, FloatRegister cVec,
1486           FloatRegister dVec, bool colToDiag);
1487 
1488   // Place an ISB after code may have been modified due to a safepoint.
1489   void safepoint_isb();
1490 
1491 private:
1492   // Return the effective address r + (r1 << ext) + offset.
1493   // Uses rscratch2.
1494   Address offsetted_address(Register r, Register r1, Address::extend ext,
1495                             int offset, int size);
1496 
1497 private:
1498   // Returns an address on the stack which is reachable with a ldr/str of size
1499   // Uses rscratch2 if the address is not directly reachable
1500   Address spill_address(int size, int offset, Register tmp=rscratch2);
1501   Address sve_spill_address(int sve_reg_size_in_bytes, int offset, Register tmp=rscratch2);
1502 
1503   bool merge_alignment_check(Register base, size_t size, int64_t cur_offset, int64_t prev_offset) const;
1504 
1505   // Check whether two loads/stores can be merged into ldp/stp.
1506   bool ldst_can_merge(Register rx, const Address &adr, size_t cur_size_in_bytes, bool is_store) const;
1507 
1508   // Merge current load/store with previous load/store into ldp/stp.
1509   void merge_ldst(Register rx, const Address &adr, size_t cur_size_in_bytes, bool is_store);
1510 
1511   // Try to merge two loads/stores into ldp/stp. If success, returns true else false.
1512   bool try_merge_ldst(Register rt, const Address &adr, size_t cur_size_in_bytes, bool is_store);
1513 
1514 public:
1515   void spill(Register Rx, bool is64, int offset) {
1516     if (is64) {
1517       str(Rx, spill_address(8, offset));
1518     } else {
1519       strw(Rx, spill_address(4, offset));
1520     }
1521   }
1522   void spill(FloatRegister Vx, SIMD_RegVariant T, int offset) {
1523     str(Vx, T, spill_address(1 << (int)T, offset));
1524   }
1525 
1526   void spill_sve_vector(FloatRegister Zx, int offset, int vector_reg_size_in_bytes) {
1527     sve_str(Zx, sve_spill_address(vector_reg_size_in_bytes, offset));
1528   }
1529   void spill_sve_predicate(PRegister pr, int offset, int predicate_reg_size_in_bytes) {
1530     sve_str(pr, sve_spill_address(predicate_reg_size_in_bytes, offset));
1531   }
1532 
1533   void unspill(Register Rx, bool is64, int offset) {
1534     if (is64) {
1535       ldr(Rx, spill_address(8, offset));
1536     } else {
1537       ldrw(Rx, spill_address(4, offset));
1538     }
1539   }
1540   void unspill(FloatRegister Vx, SIMD_RegVariant T, int offset) {
1541     ldr(Vx, T, spill_address(1 << (int)T, offset));
1542   }
1543 
1544   void unspill_sve_vector(FloatRegister Zx, int offset, int vector_reg_size_in_bytes) {
1545     sve_ldr(Zx, sve_spill_address(vector_reg_size_in_bytes, offset));
1546   }
1547   void unspill_sve_predicate(PRegister pr, int offset, int predicate_reg_size_in_bytes) {
1548     sve_ldr(pr, sve_spill_address(predicate_reg_size_in_bytes, offset));
1549   }
1550 
1551   void spill_copy128(int src_offset, int dst_offset,
1552                      Register tmp1=rscratch1, Register tmp2=rscratch2) {
1553     if (src_offset < 512 && (src_offset & 7) == 0 &&
1554         dst_offset < 512 && (dst_offset & 7) == 0) {
1555       ldp(tmp1, tmp2, Address(sp, src_offset));
1556       stp(tmp1, tmp2, Address(sp, dst_offset));
1557     } else {
1558       unspill(tmp1, true, src_offset);
1559       spill(tmp1, true, dst_offset);
1560       unspill(tmp1, true, src_offset+8);
1561       spill(tmp1, true, dst_offset+8);
1562     }
1563   }
1564   void spill_copy_sve_vector_stack_to_stack(int src_offset, int dst_offset,
1565                                             int sve_vec_reg_size_in_bytes) {
1566     assert(sve_vec_reg_size_in_bytes % 16 == 0, "unexpected sve vector reg size");
1567     for (int i = 0; i < sve_vec_reg_size_in_bytes / 16; i++) {
1568       spill_copy128(src_offset, dst_offset);
1569       src_offset += 16;
1570       dst_offset += 16;
1571     }
1572   }
1573   void spill_copy_sve_predicate_stack_to_stack(int src_offset, int dst_offset,
1574                                                int sve_predicate_reg_size_in_bytes) {
1575     sve_ldr(ptrue, sve_spill_address(sve_predicate_reg_size_in_bytes, src_offset));
1576     sve_str(ptrue, sve_spill_address(sve_predicate_reg_size_in_bytes, dst_offset));
1577     reinitialize_ptrue();
1578   }
1579   void cache_wb(Address line);
1580   void cache_wbsync(bool is_pre);
1581 
1582   // Code for java.lang.Thread::onSpinWait() intrinsic.
1583   void spin_wait();
1584 
1585   void fast_lock(Register obj, Register hdr, Register t1, Register t2, Label& slow, bool rt_check_stack = true);
1586   void fast_unlock(Register obj, Register hdr, Register t1, Register t2, Label& slow);
1587 
1588 private:
1589   // Check the current thread doesn't need a cross modify fence.
1590   void verify_cross_modify_fence_not_required() PRODUCT_RETURN;
1591 
1592 };
1593 
1594 #ifdef ASSERT
1595 inline bool AbstractAssembler::pd_check_instruction_mark() { return false; }
1596 #endif
1597 
1598 /**
1599  * class SkipIfEqual:
1600  *
1601  * Instantiating this class will result in assembly code being output that will
1602  * jump around any code emitted between the creation of the instance and it's
1603  * automatic destruction at the end of a scope block, depending on the value of
1604  * the flag passed to the constructor, which will be checked at run-time.
1605  */
1606 class SkipIfEqual {
1607  private:
1608   MacroAssembler* _masm;
1609   Label _label;
1610 
1611  public:
1612    SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
1613    ~SkipIfEqual();
1614 };
1615 
1616 struct tableswitch {
1617   Register _reg;
1618   int _insn_index; jint _first_key; jint _last_key;
1619   Label _after;
1620   Label _branches;
1621 };
1622 
1623 #endif // CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP