1 /*
   2  * Copyright (c) 1997, 2024, Oracle and/or its affiliates. All rights reserved.
   3  * Copyright (c) 2014, 2024, Red Hat Inc. All rights reserved.
   4  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   5  *
   6  * This code is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 only, as
   8  * published by the Free Software Foundation.
   9  *
  10  * This code is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  * version 2 for more details (a copy is included in the LICENSE file that
  14  * accompanied this code).
  15  *
  16  * You should have received a copy of the GNU General Public License version
  17  * 2 along with this work; if not, write to the Free Software Foundation,
  18  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  19  *
  20  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  21  * or visit www.oracle.com if you need additional information or have any
  22  * questions.
  23  *
  24  */
  25 
  26 #ifndef CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
  27 #define CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
  28 
  29 #include "asm/assembler.inline.hpp"
  30 #include "code/vmreg.hpp"
  31 #include "metaprogramming/enableIf.hpp"
  32 #include "oops/compressedOops.hpp"
  33 #include "oops/compressedKlass.hpp"
  34 #include "runtime/vm_version.hpp"
  35 #include "utilities/powerOfTwo.hpp"
  36 
  37 class OopMap;
  38 
  39 // MacroAssembler extends Assembler by frequently used macros.
  40 //
  41 // Instructions for which a 'better' code sequence exists depending
  42 // on arguments should also go in here.
  43 
  44 class MacroAssembler: public Assembler {
  45   friend class LIR_Assembler;
  46 
  47  public:
  48   using Assembler::mov;
  49   using Assembler::movi;
  50 
  51  protected:
  52 
  53   // Support for VM calls
  54   //
  55   // This is the base routine called by the different versions of call_VM_leaf. The interpreter
  56   // may customize this version by overriding it for its purposes (e.g., to save/restore
  57   // additional registers when doing a VM call).
  58   virtual void call_VM_leaf_base(
  59     address entry_point,               // the entry point
  60     int     number_of_arguments,        // the number of arguments to pop after the call
  61     Label *retaddr = nullptr
  62   );
  63 
  64   virtual void call_VM_leaf_base(
  65     address entry_point,               // the entry point
  66     int     number_of_arguments,        // the number of arguments to pop after the call
  67     Label &retaddr) {
  68     call_VM_leaf_base(entry_point, number_of_arguments, &retaddr);
  69   }
  70 
  71   // This is the base routine called by the different versions of call_VM. The interpreter
  72   // may customize this version by overriding it for its purposes (e.g., to save/restore
  73   // additional registers when doing a VM call).
  74   //
  75   // If no java_thread register is specified (noreg) than rthread will be used instead. call_VM_base
  76   // returns the register which contains the thread upon return. If a thread register has been
  77   // specified, the return value will correspond to that register. If no last_java_sp is specified
  78   // (noreg) than rsp will be used instead.
  79   virtual void call_VM_base(           // returns the register containing the thread upon return
  80     Register oop_result,               // where an oop-result ends up if any; use noreg otherwise
  81     Register java_thread,              // the thread if computed before     ; use noreg otherwise
  82     Register last_java_sp,             // to set up last_Java_frame in stubs; use noreg otherwise
  83     address  entry_point,              // the entry point
  84     int      number_of_arguments,      // the number of arguments (w/o thread) to pop after the call
  85     bool     check_exceptions          // whether to check for pending exceptions after return
  86   );
  87 
  88   void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
  89 
  90   enum KlassDecodeMode {
  91     KlassDecodeNone,
  92     KlassDecodeZero,
  93     KlassDecodeXor,
  94     KlassDecodeMovk
  95   };
  96 
  97   KlassDecodeMode klass_decode_mode();
  98 
  99  private:
 100   static KlassDecodeMode _klass_decode_mode;
 101 
 102  public:
 103   MacroAssembler(CodeBuffer* code) : Assembler(code) {}
 104 
 105  // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
 106  // The implementation is only non-empty for the InterpreterMacroAssembler,
 107  // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
 108  virtual void check_and_handle_popframe(Register java_thread);
 109  virtual void check_and_handle_earlyret(Register java_thread);
 110 
 111   void safepoint_poll(Label& slow_path, bool at_return, bool acquire, bool in_nmethod, Register tmp = rscratch1);
 112   void rt_call(address dest, Register tmp = rscratch1);
 113 
 114   // Load Effective Address
 115   void lea(Register r, const Address &a) {
 116     InstructionMark im(this);
 117     a.lea(this, r);
 118   }
 119 
 120   /* Sometimes we get misaligned loads and stores, usually from Unsafe
 121      accesses, and these can exceed the offset range. */
 122   Address legitimize_address(const Address &a, int size, Register scratch) {
 123     if (a.getMode() == Address::base_plus_offset) {
 124       if (! Address::offset_ok_for_immed(a.offset(), exact_log2(size))) {
 125         block_comment("legitimize_address {");
 126         lea(scratch, a);
 127         block_comment("} legitimize_address");
 128         return Address(scratch);
 129       }
 130     }
 131     return a;
 132   }
 133 
 134   void addmw(Address a, Register incr, Register scratch) {
 135     ldrw(scratch, a);
 136     addw(scratch, scratch, incr);
 137     strw(scratch, a);
 138   }
 139 
 140   // Add constant to memory word
 141   void addmw(Address a, int imm, Register scratch) {
 142     ldrw(scratch, a);
 143     if (imm > 0)
 144       addw(scratch, scratch, (unsigned)imm);
 145     else
 146       subw(scratch, scratch, (unsigned)-imm);
 147     strw(scratch, a);
 148   }
 149 
 150   void bind(Label& L) {
 151     Assembler::bind(L);
 152     code()->clear_last_insn();
 153     code()->set_last_label(pc());
 154   }
 155 
 156   void membar(Membar_mask_bits order_constraint);
 157 
 158   using Assembler::ldr;
 159   using Assembler::str;
 160   using Assembler::ldrw;
 161   using Assembler::strw;
 162 
 163   void ldr(Register Rx, const Address &adr);
 164   void ldrw(Register Rw, const Address &adr);
 165   void str(Register Rx, const Address &adr);
 166   void strw(Register Rx, const Address &adr);
 167 
 168   // Frame creation and destruction shared between JITs.
 169   void build_frame(int framesize);
 170   void remove_frame(int framesize);
 171 
 172   virtual void _call_Unimplemented(address call_site) {
 173     mov(rscratch2, call_site);
 174   }
 175 
 176 // Microsoft's MSVC team thinks that the __FUNCSIG__ is approximately (sympathy for calling conventions) equivalent to __PRETTY_FUNCTION__
 177 // Also, from Clang patch: "It is very similar to GCC's PRETTY_FUNCTION, except it prints the calling convention."
 178 // https://reviews.llvm.org/D3311
 179 
 180 #ifdef _WIN64
 181 #define call_Unimplemented() _call_Unimplemented((address)__FUNCSIG__)
 182 #else
 183 #define call_Unimplemented() _call_Unimplemented((address)__PRETTY_FUNCTION__)
 184 #endif
 185 
 186   // aliases defined in AARCH64 spec
 187 
 188   template<class T>
 189   inline void cmpw(Register Rd, T imm)  { subsw(zr, Rd, imm); }
 190 
 191   inline void cmp(Register Rd, unsigned char imm8)  { subs(zr, Rd, imm8); }
 192   inline void cmp(Register Rd, unsigned imm) = delete;
 193 
 194   template<class T>
 195   inline void cmnw(Register Rd, T imm) { addsw(zr, Rd, imm); }
 196 
 197   inline void cmn(Register Rd, unsigned char imm8)  { adds(zr, Rd, imm8); }
 198   inline void cmn(Register Rd, unsigned imm) = delete;
 199 
 200   void cset(Register Rd, Assembler::Condition cond) {
 201     csinc(Rd, zr, zr, ~cond);
 202   }
 203   void csetw(Register Rd, Assembler::Condition cond) {
 204     csincw(Rd, zr, zr, ~cond);
 205   }
 206 
 207   void cneg(Register Rd, Register Rn, Assembler::Condition cond) {
 208     csneg(Rd, Rn, Rn, ~cond);
 209   }
 210   void cnegw(Register Rd, Register Rn, Assembler::Condition cond) {
 211     csnegw(Rd, Rn, Rn, ~cond);
 212   }
 213 
 214   inline void movw(Register Rd, Register Rn) {
 215     if (Rd == sp || Rn == sp) {
 216       Assembler::addw(Rd, Rn, 0U);
 217     } else {
 218       orrw(Rd, zr, Rn);
 219     }
 220   }
 221   inline void mov(Register Rd, Register Rn) {
 222     assert(Rd != r31_sp && Rn != r31_sp, "should be");
 223     if (Rd == Rn) {
 224     } else if (Rd == sp || Rn == sp) {
 225       Assembler::add(Rd, Rn, 0U);
 226     } else {
 227       orr(Rd, zr, Rn);
 228     }
 229   }
 230 
 231   inline void moviw(Register Rd, unsigned imm) { orrw(Rd, zr, imm); }
 232   inline void movi(Register Rd, unsigned imm) { orr(Rd, zr, imm); }
 233 
 234   inline void tstw(Register Rd, Register Rn) { andsw(zr, Rd, Rn); }
 235   inline void tst(Register Rd, Register Rn) { ands(zr, Rd, Rn); }
 236 
 237   inline void tstw(Register Rd, uint64_t imm) { andsw(zr, Rd, imm); }
 238   inline void tst(Register Rd, uint64_t imm) { ands(zr, Rd, imm); }
 239 
 240   inline void bfiw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 241     bfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
 242   }
 243   inline void bfi(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 244     bfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
 245   }
 246 
 247   inline void bfxilw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 248     bfmw(Rd, Rn, lsb, (lsb + width - 1));
 249   }
 250   inline void bfxil(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 251     bfm(Rd, Rn, lsb , (lsb + width - 1));
 252   }
 253 
 254   inline void sbfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 255     sbfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
 256   }
 257   inline void sbfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 258     sbfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
 259   }
 260 
 261   inline void sbfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 262     sbfmw(Rd, Rn, lsb, (lsb + width - 1));
 263   }
 264   inline void sbfx(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 265     sbfm(Rd, Rn, lsb , (lsb + width - 1));
 266   }
 267 
 268   inline void ubfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 269     ubfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
 270   }
 271   inline void ubfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 272     ubfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
 273   }
 274 
 275   inline void ubfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 276     ubfmw(Rd, Rn, lsb, (lsb + width - 1));
 277   }
 278   inline void ubfx(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 279     ubfm(Rd, Rn, lsb , (lsb + width - 1));
 280   }
 281 
 282   inline void asrw(Register Rd, Register Rn, unsigned imm) {
 283     sbfmw(Rd, Rn, imm, 31);
 284   }
 285 
 286   inline void asr(Register Rd, Register Rn, unsigned imm) {
 287     sbfm(Rd, Rn, imm, 63);
 288   }
 289 
 290   inline void lslw(Register Rd, Register Rn, unsigned imm) {
 291     ubfmw(Rd, Rn, ((32 - imm) & 31), (31 - imm));
 292   }
 293 
 294   inline void lsl(Register Rd, Register Rn, unsigned imm) {
 295     ubfm(Rd, Rn, ((64 - imm) & 63), (63 - imm));
 296   }
 297 
 298   inline void lsrw(Register Rd, Register Rn, unsigned imm) {
 299     ubfmw(Rd, Rn, imm, 31);
 300   }
 301 
 302   inline void lsr(Register Rd, Register Rn, unsigned imm) {
 303     ubfm(Rd, Rn, imm, 63);
 304   }
 305 
 306   inline void rorw(Register Rd, Register Rn, unsigned imm) {
 307     extrw(Rd, Rn, Rn, imm);
 308   }
 309 
 310   inline void ror(Register Rd, Register Rn, unsigned imm) {
 311     extr(Rd, Rn, Rn, imm);
 312   }
 313 
 314   inline void sxtbw(Register Rd, Register Rn) {
 315     sbfmw(Rd, Rn, 0, 7);
 316   }
 317   inline void sxthw(Register Rd, Register Rn) {
 318     sbfmw(Rd, Rn, 0, 15);
 319   }
 320   inline void sxtb(Register Rd, Register Rn) {
 321     sbfm(Rd, Rn, 0, 7);
 322   }
 323   inline void sxth(Register Rd, Register Rn) {
 324     sbfm(Rd, Rn, 0, 15);
 325   }
 326   inline void sxtw(Register Rd, Register Rn) {
 327     sbfm(Rd, Rn, 0, 31);
 328   }
 329 
 330   inline void uxtbw(Register Rd, Register Rn) {
 331     ubfmw(Rd, Rn, 0, 7);
 332   }
 333   inline void uxthw(Register Rd, Register Rn) {
 334     ubfmw(Rd, Rn, 0, 15);
 335   }
 336   inline void uxtb(Register Rd, Register Rn) {
 337     ubfm(Rd, Rn, 0, 7);
 338   }
 339   inline void uxth(Register Rd, Register Rn) {
 340     ubfm(Rd, Rn, 0, 15);
 341   }
 342   inline void uxtw(Register Rd, Register Rn) {
 343     ubfm(Rd, Rn, 0, 31);
 344   }
 345 
 346   inline void cmnw(Register Rn, Register Rm) {
 347     addsw(zr, Rn, Rm);
 348   }
 349   inline void cmn(Register Rn, Register Rm) {
 350     adds(zr, Rn, Rm);
 351   }
 352 
 353   inline void cmpw(Register Rn, Register Rm) {
 354     subsw(zr, Rn, Rm);
 355   }
 356   inline void cmp(Register Rn, Register Rm) {
 357     subs(zr, Rn, Rm);
 358   }
 359 
 360   inline void negw(Register Rd, Register Rn) {
 361     subw(Rd, zr, Rn);
 362   }
 363 
 364   inline void neg(Register Rd, Register Rn) {
 365     sub(Rd, zr, Rn);
 366   }
 367 
 368   inline void negsw(Register Rd, Register Rn) {
 369     subsw(Rd, zr, Rn);
 370   }
 371 
 372   inline void negs(Register Rd, Register Rn) {
 373     subs(Rd, zr, Rn);
 374   }
 375 
 376   inline void cmnw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
 377     addsw(zr, Rn, Rm, kind, shift);
 378   }
 379   inline void cmn(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
 380     adds(zr, Rn, Rm, kind, shift);
 381   }
 382 
 383   inline void cmpw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
 384     subsw(zr, Rn, Rm, kind, shift);
 385   }
 386   inline void cmp(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
 387     subs(zr, Rn, Rm, kind, shift);
 388   }
 389 
 390   inline void negw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
 391     subw(Rd, zr, Rn, kind, shift);
 392   }
 393 
 394   inline void neg(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
 395     sub(Rd, zr, Rn, kind, shift);
 396   }
 397 
 398   inline void negsw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
 399     subsw(Rd, zr, Rn, kind, shift);
 400   }
 401 
 402   inline void negs(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
 403     subs(Rd, zr, Rn, kind, shift);
 404   }
 405 
 406   inline void mnegw(Register Rd, Register Rn, Register Rm) {
 407     msubw(Rd, Rn, Rm, zr);
 408   }
 409   inline void mneg(Register Rd, Register Rn, Register Rm) {
 410     msub(Rd, Rn, Rm, zr);
 411   }
 412 
 413   inline void mulw(Register Rd, Register Rn, Register Rm) {
 414     maddw(Rd, Rn, Rm, zr);
 415   }
 416   inline void mul(Register Rd, Register Rn, Register Rm) {
 417     madd(Rd, Rn, Rm, zr);
 418   }
 419 
 420   inline void smnegl(Register Rd, Register Rn, Register Rm) {
 421     smsubl(Rd, Rn, Rm, zr);
 422   }
 423   inline void smull(Register Rd, Register Rn, Register Rm) {
 424     smaddl(Rd, Rn, Rm, zr);
 425   }
 426 
 427   inline void umnegl(Register Rd, Register Rn, Register Rm) {
 428     umsubl(Rd, Rn, Rm, zr);
 429   }
 430   inline void umull(Register Rd, Register Rn, Register Rm) {
 431     umaddl(Rd, Rn, Rm, zr);
 432   }
 433 
 434 #define WRAP(INSN)                                                            \
 435   void INSN(Register Rd, Register Rn, Register Rm, Register Ra) {             \
 436     if (VM_Version::supports_a53mac() && Ra != zr)                            \
 437       nop();                                                                  \
 438     Assembler::INSN(Rd, Rn, Rm, Ra);                                          \
 439   }
 440 
 441   WRAP(madd) WRAP(msub) WRAP(maddw) WRAP(msubw)
 442   WRAP(smaddl) WRAP(smsubl) WRAP(umaddl) WRAP(umsubl)
 443 #undef WRAP
 444 
 445 
 446   // macro assembly operations needed for aarch64
 447 
 448 public:
 449 
 450   enum FpPushPopMode {
 451     PushPopFull,
 452     PushPopSVE,
 453     PushPopNeon,
 454     PushPopFp
 455   };
 456 
 457   // first two private routines for loading 32 bit or 64 bit constants
 458 private:
 459 
 460   void mov_immediate64(Register dst, uint64_t imm64);
 461   void mov_immediate32(Register dst, uint32_t imm32);
 462 
 463   int push(unsigned int bitset, Register stack);
 464   int pop(unsigned int bitset, Register stack);
 465 
 466   int push_fp(unsigned int bitset, Register stack, FpPushPopMode mode);
 467   int pop_fp(unsigned int bitset, Register stack, FpPushPopMode mode);
 468 
 469   int push_p(unsigned int bitset, Register stack);
 470   int pop_p(unsigned int bitset, Register stack);
 471 
 472   void mov(Register dst, Address a);
 473 
 474 public:
 475 
 476   void push(RegSet regs, Register stack) { if (regs.bits()) push(regs.bits(), stack); }
 477   void pop(RegSet regs, Register stack) { if (regs.bits()) pop(regs.bits(), stack); }
 478 
 479   void push_fp(FloatRegSet regs, Register stack, FpPushPopMode mode = PushPopFull) { if (regs.bits()) push_fp(regs.bits(), stack, mode); }
 480   void pop_fp(FloatRegSet regs, Register stack, FpPushPopMode mode = PushPopFull) { if (regs.bits()) pop_fp(regs.bits(), stack, mode); }
 481 
 482   static RegSet call_clobbered_gp_registers();
 483 
 484   void push_p(PRegSet regs, Register stack) { if (regs.bits()) push_p(regs.bits(), stack); }
 485   void pop_p(PRegSet regs, Register stack) { if (regs.bits()) pop_p(regs.bits(), stack); }
 486 
 487   // Push and pop everything that might be clobbered by a native
 488   // runtime call except rscratch1 and rscratch2.  (They are always
 489   // scratch, so we don't have to protect them.)  Only save the lower
 490   // 64 bits of each vector register. Additional registers can be excluded
 491   // in a passed RegSet.
 492   void push_call_clobbered_registers_except(RegSet exclude);
 493   void pop_call_clobbered_registers_except(RegSet exclude);
 494 
 495   void push_call_clobbered_registers() {
 496     push_call_clobbered_registers_except(RegSet());
 497   }
 498   void pop_call_clobbered_registers() {
 499     pop_call_clobbered_registers_except(RegSet());
 500   }
 501 
 502 
 503   // now mov instructions for loading absolute addresses and 32 or
 504   // 64 bit integers
 505 
 506   inline void mov(Register dst, address addr)             { mov_immediate64(dst, (uint64_t)addr); }
 507 
 508   template<typename T, ENABLE_IF(std::is_integral<T>::value)>
 509   inline void mov(Register dst, T o)                      { mov_immediate64(dst, (uint64_t)o); }
 510 
 511   inline void movw(Register dst, uint32_t imm32)          { mov_immediate32(dst, imm32); }
 512 
 513   void mov(Register dst, RegisterOrConstant src) {
 514     if (src.is_register())
 515       mov(dst, src.as_register());
 516     else
 517       mov(dst, src.as_constant());
 518   }
 519 
 520   void movptr(Register r, uintptr_t imm64);
 521 
 522   void mov(FloatRegister Vd, SIMD_Arrangement T, uint64_t imm64);
 523 
 524   void mov(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) {
 525     orr(Vd, T, Vn, Vn);
 526   }
 527 
 528   void flt_to_flt16(Register dst, FloatRegister src, FloatRegister tmp) {
 529     fcvtsh(tmp, src);
 530     smov(dst, tmp, H, 0);
 531   }
 532 
 533   void flt16_to_flt(FloatRegister dst, Register src, FloatRegister tmp) {
 534     mov(tmp, H, 0, src);
 535     fcvths(dst, tmp);
 536   }
 537 
 538   // Generalized Test Bit And Branch, including a "far" variety which
 539   // spans more than 32KiB.
 540   void tbr(Condition cond, Register Rt, int bitpos, Label &dest, bool isfar = false) {
 541     assert(cond == EQ || cond == NE, "must be");
 542 
 543     if (isfar)
 544       cond = ~cond;
 545 
 546     void (Assembler::* branch)(Register Rt, int bitpos, Label &L);
 547     if (cond == Assembler::EQ)
 548       branch = &Assembler::tbz;
 549     else
 550       branch = &Assembler::tbnz;
 551 
 552     if (isfar) {
 553       Label L;
 554       (this->*branch)(Rt, bitpos, L);
 555       b(dest);
 556       bind(L);
 557     } else {
 558       (this->*branch)(Rt, bitpos, dest);
 559     }
 560   }
 561 
 562   // macro instructions for accessing and updating floating point
 563   // status register
 564   //
 565   // FPSR : op1 == 011
 566   //        CRn == 0100
 567   //        CRm == 0100
 568   //        op2 == 001
 569 
 570   inline void get_fpsr(Register reg)
 571   {
 572     mrs(0b11, 0b0100, 0b0100, 0b001, reg);
 573   }
 574 
 575   inline void set_fpsr(Register reg)
 576   {
 577     msr(0b011, 0b0100, 0b0100, 0b001, reg);
 578   }
 579 
 580   inline void clear_fpsr()
 581   {
 582     msr(0b011, 0b0100, 0b0100, 0b001, zr);
 583   }
 584 
 585   // FPCR : op1 == 011
 586   //        CRn == 0100
 587   //        CRm == 0100
 588   //        op2 == 000
 589 
 590   inline void get_fpcr(Register reg) {
 591     mrs(0b11, 0b0100, 0b0100, 0b000, reg);
 592   }
 593 
 594   inline void set_fpcr(Register reg) {
 595     msr(0b011, 0b0100, 0b0100, 0b000, reg);
 596   }
 597 
 598   // DCZID_EL0: op1 == 011
 599   //            CRn == 0000
 600   //            CRm == 0000
 601   //            op2 == 111
 602   inline void get_dczid_el0(Register reg)
 603   {
 604     mrs(0b011, 0b0000, 0b0000, 0b111, reg);
 605   }
 606 
 607   // CTR_EL0:   op1 == 011
 608   //            CRn == 0000
 609   //            CRm == 0000
 610   //            op2 == 001
 611   inline void get_ctr_el0(Register reg)
 612   {
 613     mrs(0b011, 0b0000, 0b0000, 0b001, reg);
 614   }
 615 
 616   inline void get_nzcv(Register reg) {
 617     mrs(0b011, 0b0100, 0b0010, 0b000, reg);
 618   }
 619 
 620   inline void set_nzcv(Register reg) {
 621     msr(0b011, 0b0100, 0b0010, 0b000, reg);
 622   }
 623 
 624   // idiv variant which deals with MINLONG as dividend and -1 as divisor
 625   int corrected_idivl(Register result, Register ra, Register rb,
 626                       bool want_remainder, Register tmp = rscratch1);
 627   int corrected_idivq(Register result, Register ra, Register rb,
 628                       bool want_remainder, Register tmp = rscratch1);
 629 
 630   // Support for null-checks
 631   //
 632   // Generates code that causes a null OS exception if the content of reg is null.
 633   // If the accessed location is M[reg + offset] and the offset is known, provide the
 634   // offset. No explicit code generation is needed if the offset is within a certain
 635   // range (0 <= offset <= page_size).
 636 
 637   virtual void null_check(Register reg, int offset = -1);
 638   static bool needs_explicit_null_check(intptr_t offset);
 639   static bool uses_implicit_null_check(void* address);
 640 
 641   static address target_addr_for_insn(address insn_addr, unsigned insn);
 642   static address target_addr_for_insn_or_null(address insn_addr, unsigned insn);
 643   static address target_addr_for_insn(address insn_addr) {
 644     unsigned insn = *(unsigned*)insn_addr;
 645     return target_addr_for_insn(insn_addr, insn);
 646   }
 647   static address target_addr_for_insn_or_null(address insn_addr) {
 648     unsigned insn = *(unsigned*)insn_addr;
 649     return target_addr_for_insn_or_null(insn_addr, insn);
 650   }
 651 
 652   // Required platform-specific helpers for Label::patch_instructions.
 653   // They _shadow_ the declarations in AbstractAssembler, which are undefined.
 654   static int pd_patch_instruction_size(address branch, address target);
 655   static void pd_patch_instruction(address branch, address target, const char* file = nullptr, int line = 0) {
 656     pd_patch_instruction_size(branch, target);
 657   }
 658   static address pd_call_destination(address branch) {
 659     return target_addr_for_insn(branch);
 660   }
 661 #ifndef PRODUCT
 662   static void pd_print_patched_instruction(address branch);
 663 #endif
 664 
 665   static int patch_oop(address insn_addr, address o);
 666   static int patch_narrow_klass(address insn_addr, narrowKlass n);
 667 
 668   // Return whether code is emitted to a scratch blob.
 669   virtual bool in_scratch_emit_size() {
 670     return false;
 671   }
 672   address emit_trampoline_stub(int insts_call_instruction_offset, address target);
 673   static int max_trampoline_stub_size();
 674   void emit_static_call_stub();
 675   static int static_call_stub_size();
 676 
 677   // The following 4 methods return the offset of the appropriate move instruction
 678 
 679   // Support for fast byte/short loading with zero extension (depending on particular CPU)
 680   int load_unsigned_byte(Register dst, Address src);
 681   int load_unsigned_short(Register dst, Address src);
 682 
 683   // Support for fast byte/short loading with sign extension (depending on particular CPU)
 684   int load_signed_byte(Register dst, Address src);
 685   int load_signed_short(Register dst, Address src);
 686 
 687   int load_signed_byte32(Register dst, Address src);
 688   int load_signed_short32(Register dst, Address src);
 689 
 690   // Support for sign-extension (hi:lo = extend_sign(lo))
 691   void extend_sign(Register hi, Register lo);
 692 
 693   // Load and store values by size and signed-ness
 694   void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed);
 695   void store_sized_value(Address dst, Register src, size_t size_in_bytes);
 696 
 697   // Support for inc/dec with optimal instruction selection depending on value
 698 
 699   // x86_64 aliases an unqualified register/address increment and
 700   // decrement to call incrementq and decrementq but also supports
 701   // explicitly sized calls to incrementq/decrementq or
 702   // incrementl/decrementl
 703 
 704   // for aarch64 the proper convention would be to use
 705   // increment/decrement for 64 bit operations and
 706   // incrementw/decrementw for 32 bit operations. so when porting
 707   // x86_64 code we can leave calls to increment/decrement as is,
 708   // replace incrementq/decrementq with increment/decrement and
 709   // replace incrementl/decrementl with incrementw/decrementw.
 710 
 711   // n.b. increment/decrement calls with an Address destination will
 712   // need to use a scratch register to load the value to be
 713   // incremented. increment/decrement calls which add or subtract a
 714   // constant value greater than 2^12 will need to use a 2nd scratch
 715   // register to hold the constant. so, a register increment/decrement
 716   // may trash rscratch2 and an address increment/decrement trash
 717   // rscratch and rscratch2
 718 
 719   void decrementw(Address dst, int value = 1);
 720   void decrementw(Register reg, int value = 1);
 721 
 722   void decrement(Register reg, int value = 1);
 723   void decrement(Address dst, int value = 1);
 724 
 725   void incrementw(Address dst, int value = 1);
 726   void incrementw(Register reg, int value = 1);
 727 
 728   void increment(Register reg, int value = 1);
 729   void increment(Address dst, int value = 1);
 730 
 731 
 732   // Alignment
 733   void align(int modulus);
 734   void align(int modulus, int target);
 735 
 736   // nop
 737   void post_call_nop();
 738 
 739   // Stack frame creation/removal
 740   void enter(bool strip_ret_addr = false);
 741   void leave();
 742 
 743   // ROP Protection
 744   void protect_return_address();
 745   void protect_return_address(Register return_reg);
 746   void authenticate_return_address();
 747   void authenticate_return_address(Register return_reg);
 748   void strip_return_address();
 749   void check_return_address(Register return_reg=lr) PRODUCT_RETURN;
 750 
 751   // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
 752   // The pointer will be loaded into the thread register.
 753   void get_thread(Register thread);
 754 
 755   // support for argument shuffling
 756   void move32_64(VMRegPair src, VMRegPair dst, Register tmp = rscratch1);
 757   void float_move(VMRegPair src, VMRegPair dst, Register tmp = rscratch1);
 758   void long_move(VMRegPair src, VMRegPair dst, Register tmp = rscratch1);
 759   void double_move(VMRegPair src, VMRegPair dst, Register tmp = rscratch1);
 760   void object_move(
 761                    OopMap* map,
 762                    int oop_handle_offset,
 763                    int framesize_in_slots,
 764                    VMRegPair src,
 765                    VMRegPair dst,
 766                    bool is_receiver,
 767                    int* receiver_offset);
 768 
 769 
 770   // Support for VM calls
 771   //
 772   // It is imperative that all calls into the VM are handled via the call_VM macros.
 773   // They make sure that the stack linkage is setup correctly. call_VM's correspond
 774   // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
 775 
 776 
 777   void call_VM(Register oop_result,
 778                address entry_point,
 779                bool check_exceptions = true);
 780   void call_VM(Register oop_result,
 781                address entry_point,
 782                Register arg_1,
 783                bool check_exceptions = true);
 784   void call_VM(Register oop_result,
 785                address entry_point,
 786                Register arg_1, Register arg_2,
 787                bool check_exceptions = true);
 788   void call_VM(Register oop_result,
 789                address entry_point,
 790                Register arg_1, Register arg_2, Register arg_3,
 791                bool check_exceptions = true);
 792 
 793   // Overloadings with last_Java_sp
 794   void call_VM(Register oop_result,
 795                Register last_java_sp,
 796                address entry_point,
 797                int number_of_arguments = 0,
 798                bool check_exceptions = true);
 799   void call_VM(Register oop_result,
 800                Register last_java_sp,
 801                address entry_point,
 802                Register arg_1, bool
 803                check_exceptions = true);
 804   void call_VM(Register oop_result,
 805                Register last_java_sp,
 806                address entry_point,
 807                Register arg_1, Register arg_2,
 808                bool check_exceptions = true);
 809   void call_VM(Register oop_result,
 810                Register last_java_sp,
 811                address entry_point,
 812                Register arg_1, Register arg_2, Register arg_3,
 813                bool check_exceptions = true);
 814 
 815   void get_vm_result  (Register oop_result, Register thread);
 816   void get_vm_result_2(Register metadata_result, Register thread);
 817 
 818   // These always tightly bind to MacroAssembler::call_VM_base
 819   // bypassing the virtual implementation
 820   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
 821   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
 822   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
 823   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
 824   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
 825 
 826   void call_VM_leaf(address entry_point,
 827                     int number_of_arguments = 0);
 828   void call_VM_leaf(address entry_point,
 829                     Register arg_1);
 830   void call_VM_leaf(address entry_point,
 831                     Register arg_1, Register arg_2);
 832   void call_VM_leaf(address entry_point,
 833                     Register arg_1, Register arg_2, Register arg_3);
 834 
 835   // These always tightly bind to MacroAssembler::call_VM_leaf_base
 836   // bypassing the virtual implementation
 837   void super_call_VM_leaf(address entry_point);
 838   void super_call_VM_leaf(address entry_point, Register arg_1);
 839   void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
 840   void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
 841   void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
 842 
 843   // last Java Frame (fills frame anchor)
 844   void set_last_Java_frame(Register last_java_sp,
 845                            Register last_java_fp,
 846                            address last_java_pc,
 847                            Register scratch);
 848 
 849   void set_last_Java_frame(Register last_java_sp,
 850                            Register last_java_fp,
 851                            Label &last_java_pc,
 852                            Register scratch);
 853 
 854   void set_last_Java_frame(Register last_java_sp,
 855                            Register last_java_fp,
 856                            Register last_java_pc,
 857                            Register scratch);
 858 
 859   void reset_last_Java_frame(Register thread);
 860 
 861   // thread in the default location (rthread)
 862   void reset_last_Java_frame(bool clear_fp);
 863 
 864   // Stores
 865   void store_check(Register obj);                // store check for obj - register is destroyed afterwards
 866   void store_check(Register obj, Address dst);   // same as above, dst is exact store location (reg. is destroyed)
 867 
 868   void resolve_jobject(Register value, Register tmp1, Register tmp2);
 869   void resolve_global_jobject(Register value, Register tmp1, Register tmp2);
 870 
 871   // C 'boolean' to Java boolean: x == 0 ? 0 : 1
 872   void c2bool(Register x);
 873 
 874   void load_method_holder_cld(Register rresult, Register rmethod);
 875   void load_method_holder(Register holder, Register method);
 876 
 877   // oop manipulations
 878   void load_nklass_compact(Register dst, Register src);
 879   void load_klass(Register dst, Register src);
 880   void store_klass(Register dst, Register src);
 881   void cmp_klass(Register oop, Register trial_klass, Register tmp);
 882   void cmp_klass(Register src, Register dst, Register tmp1, Register tmp2);
 883 
 884   void resolve_weak_handle(Register result, Register tmp1, Register tmp2);
 885   void resolve_oop_handle(Register result, Register tmp1, Register tmp2);
 886   void load_mirror(Register dst, Register method, Register tmp1, Register tmp2);
 887 
 888   void access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
 889                       Register tmp1, Register tmp2);
 890 
 891   void access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register val,
 892                        Register tmp1, Register tmp2, Register tmp3);
 893 
 894   void load_heap_oop(Register dst, Address src, Register tmp1,
 895                      Register tmp2, DecoratorSet decorators = 0);
 896 
 897   void load_heap_oop_not_null(Register dst, Address src, Register tmp1,
 898                               Register tmp2, DecoratorSet decorators = 0);
 899   void store_heap_oop(Address dst, Register val, Register tmp1,
 900                       Register tmp2, Register tmp3, DecoratorSet decorators = 0);
 901 
 902   // currently unimplemented
 903   // Used for storing null. All other oop constants should be
 904   // stored using routines that take a jobject.
 905   void store_heap_oop_null(Address dst);
 906 
 907   void store_klass_gap(Register dst, Register src);
 908 
 909   // This dummy is to prevent a call to store_heap_oop from
 910   // converting a zero (like null) into a Register by giving
 911   // the compiler two choices it can't resolve
 912 
 913   void store_heap_oop(Address dst, void* dummy);
 914 
 915   void encode_heap_oop(Register d, Register s);
 916   void encode_heap_oop(Register r) { encode_heap_oop(r, r); }
 917   void decode_heap_oop(Register d, Register s);
 918   void decode_heap_oop(Register r) { decode_heap_oop(r, r); }
 919   void encode_heap_oop_not_null(Register r);
 920   void decode_heap_oop_not_null(Register r);
 921   void encode_heap_oop_not_null(Register dst, Register src);
 922   void decode_heap_oop_not_null(Register dst, Register src);
 923 
 924   void set_narrow_oop(Register dst, jobject obj);
 925 
 926   void encode_klass_not_null(Register r);
 927   void decode_klass_not_null(Register r);
 928   void encode_klass_not_null(Register dst, Register src);
 929   void decode_klass_not_null(Register dst, Register src);
 930 
 931   void set_narrow_klass(Register dst, Klass* k);
 932 
 933   // if heap base register is used - reinit it with the correct value
 934   void reinit_heapbase();
 935 
 936   DEBUG_ONLY(void verify_heapbase(const char* msg);)
 937 
 938   void push_CPU_state(bool save_vectors = false, bool use_sve = false,
 939                       int sve_vector_size_in_bytes = 0, int total_predicate_in_bytes = 0);
 940   void pop_CPU_state(bool restore_vectors = false, bool use_sve = false,
 941                      int sve_vector_size_in_bytes = 0, int total_predicate_in_bytes = 0);
 942 
 943   void push_cont_fastpath(Register java_thread);
 944   void pop_cont_fastpath(Register java_thread);
 945 
 946   // Round up to a power of two
 947   void round_to(Register reg, int modulus);
 948 
 949   // java.lang.Math::round intrinsics
 950   void java_round_double(Register dst, FloatRegister src, FloatRegister ftmp);
 951   void java_round_float(Register dst, FloatRegister src, FloatRegister ftmp);
 952 
 953   // allocation
 954   void tlab_allocate(
 955     Register obj,                      // result: pointer to object after successful allocation
 956     Register var_size_in_bytes,        // object size in bytes if unknown at compile time; invalid otherwise
 957     int      con_size_in_bytes,        // object size in bytes if   known at compile time
 958     Register t1,                       // temp register
 959     Register t2,                       // temp register
 960     Label&   slow_case                 // continuation point if fast allocation fails
 961   );
 962   void verify_tlab();
 963 
 964   // interface method calling
 965   void lookup_interface_method(Register recv_klass,
 966                                Register intf_klass,
 967                                RegisterOrConstant itable_index,
 968                                Register method_result,
 969                                Register scan_temp,
 970                                Label& no_such_interface,
 971                    bool return_method = true);
 972 
 973   void lookup_interface_method_stub(Register recv_klass,
 974                                     Register holder_klass,
 975                                     Register resolved_klass,
 976                                     Register method_result,
 977                                     Register temp_reg,
 978                                     Register temp_reg2,
 979                                     int itable_index,
 980                                     Label& L_no_such_interface);
 981 
 982   // virtual method calling
 983   // n.b. x86 allows RegisterOrConstant for vtable_index
 984   void lookup_virtual_method(Register recv_klass,
 985                              RegisterOrConstant vtable_index,
 986                              Register method_result);
 987 
 988   // Test sub_klass against super_klass, with fast and slow paths.
 989 
 990   // The fast path produces a tri-state answer: yes / no / maybe-slow.
 991   // One of the three labels can be null, meaning take the fall-through.
 992   // If super_check_offset is -1, the value is loaded up from super_klass.
 993   // No registers are killed, except temp_reg.
 994   void check_klass_subtype_fast_path(Register sub_klass,
 995                                      Register super_klass,
 996                                      Register temp_reg,
 997                                      Label* L_success,
 998                                      Label* L_failure,
 999                                      Label* L_slow_path,
1000                 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
1001 
1002   // The rest of the type check; must be wired to a corresponding fast path.
1003   // It does not repeat the fast path logic, so don't use it standalone.
1004   // The temp_reg and temp2_reg can be noreg, if no temps are available.
1005   // Updates the sub's secondary super cache as necessary.
1006   // If set_cond_codes, condition codes will be Z on success, NZ on failure.
1007   void check_klass_subtype_slow_path(Register sub_klass,
1008                                      Register super_klass,
1009                                      Register temp_reg,
1010                                      Register temp2_reg,
1011                                      Label* L_success,
1012                                      Label* L_failure,
1013                                      bool set_cond_codes = false);
1014 
1015   // As above, but with a constant super_klass.
1016   // The result is in Register result, not the condition codes.
1017   bool lookup_secondary_supers_table(Register r_sub_klass,
1018                                      Register r_super_klass,
1019                                      Register temp1,
1020                                      Register temp2,
1021                                      Register temp3,
1022                                      FloatRegister vtemp,
1023                                      Register result,
1024                                      u1 super_klass_slot,
1025                                      bool stub_is_near = false);
1026 
1027   void verify_secondary_supers_table(Register r_sub_klass,
1028                                      Register r_super_klass,
1029                                      Register temp1,
1030                                      Register temp2,
1031                                      Register result);
1032 
1033   void lookup_secondary_supers_table_slow_path(Register r_super_klass,
1034                                                Register r_array_base,
1035                                                Register r_array_index,
1036                                                Register r_bitmap,
1037                                                Register temp1,
1038                                                Register result);
1039 
1040   // Simplified, combined version, good for typical uses.
1041   // Falls through on failure.
1042   void check_klass_subtype(Register sub_klass,
1043                            Register super_klass,
1044                            Register temp_reg,
1045                            Label& L_success);
1046 
1047   void clinit_barrier(Register klass,
1048                       Register thread,
1049                       Label* L_fast_path = nullptr,
1050                       Label* L_slow_path = nullptr);
1051 
1052   Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
1053 
1054   void verify_sve_vector_length(Register tmp = rscratch1);
1055   void reinitialize_ptrue() {
1056     if (UseSVE > 0) {
1057       sve_ptrue(ptrue, B);
1058     }
1059   }
1060   void verify_ptrue();
1061 
1062   // Debugging
1063 
1064   // only if +VerifyOops
1065   void _verify_oop(Register reg, const char* s, const char* file, int line);
1066   void _verify_oop_addr(Address addr, const char * s, const char* file, int line);
1067 
1068   void _verify_oop_checked(Register reg, const char* s, const char* file, int line) {
1069     if (VerifyOops) {
1070       _verify_oop(reg, s, file, line);
1071     }
1072   }
1073   void _verify_oop_addr_checked(Address reg, const char* s, const char* file, int line) {
1074     if (VerifyOops) {
1075       _verify_oop_addr(reg, s, file, line);
1076     }
1077   }
1078 
1079 // TODO: verify method and klass metadata (compare against vptr?)
1080   void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
1081   void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
1082 
1083 #define verify_oop(reg) _verify_oop_checked(reg, "broken oop " #reg, __FILE__, __LINE__)
1084 #define verify_oop_msg(reg, msg) _verify_oop_checked(reg, "broken oop " #reg ", " #msg, __FILE__, __LINE__)
1085 #define verify_oop_addr(addr) _verify_oop_addr_checked(addr, "broken oop addr " #addr, __FILE__, __LINE__)
1086 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
1087 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
1088 
1089   // Restore cpu control state after JNI call
1090   void restore_cpu_control_state_after_jni(Register tmp1, Register tmp2);
1091 
1092   // prints msg, dumps registers and stops execution
1093   void stop(const char* msg);
1094 
1095   static void debug64(char* msg, int64_t pc, int64_t regs[]);
1096 
1097   void untested()                                { stop("untested"); }
1098 
1099   void unimplemented(const char* what = "");
1100 
1101   void should_not_reach_here()                   { stop("should not reach here"); }
1102 
1103   void _assert_asm(Condition cc, const char* msg);
1104 #define assert_asm0(cc, msg) _assert_asm(cc, FILE_AND_LINE ": " msg)
1105 #define assert_asm(masm, command, cc, msg) DEBUG_ONLY(command; (masm)->_assert_asm(cc, FILE_AND_LINE ": " #command " " #cc ": " msg))
1106 
1107   // Stack overflow checking
1108   void bang_stack_with_offset(int offset) {
1109     // stack grows down, caller passes positive offset
1110     assert(offset > 0, "must bang with negative offset");
1111     sub(rscratch2, sp, offset);
1112     str(zr, Address(rscratch2));
1113   }
1114 
1115   // Writes to stack successive pages until offset reached to check for
1116   // stack overflow + shadow pages.  Also, clobbers tmp
1117   void bang_stack_size(Register size, Register tmp);
1118 
1119   // Check for reserved stack access in method being exited (for JIT)
1120   void reserved_stack_check();
1121 
1122   // Arithmetics
1123 
1124   void addptr(const Address &dst, int32_t src);
1125   void cmpptr(Register src1, Address src2);
1126 
1127   void cmpoop(Register obj1, Register obj2);
1128 
1129   // Various forms of CAS
1130 
1131   void cmpxchg_obj_header(Register oldv, Register newv, Register obj, Register tmp,
1132                           Label &succeed, Label *fail);
1133   void cmpxchgptr(Register oldv, Register newv, Register addr, Register tmp,
1134                   Label &succeed, Label *fail);
1135 
1136   void cmpxchgw(Register oldv, Register newv, Register addr, Register tmp,
1137                   Label &succeed, Label *fail);
1138 
1139   void atomic_add(Register prev, RegisterOrConstant incr, Register addr);
1140   void atomic_addw(Register prev, RegisterOrConstant incr, Register addr);
1141   void atomic_addal(Register prev, RegisterOrConstant incr, Register addr);
1142   void atomic_addalw(Register prev, RegisterOrConstant incr, Register addr);
1143 
1144   void atomic_xchg(Register prev, Register newv, Register addr);
1145   void atomic_xchgw(Register prev, Register newv, Register addr);
1146   void atomic_xchgl(Register prev, Register newv, Register addr);
1147   void atomic_xchglw(Register prev, Register newv, Register addr);
1148   void atomic_xchgal(Register prev, Register newv, Register addr);
1149   void atomic_xchgalw(Register prev, Register newv, Register addr);
1150 
1151   void orptr(Address adr, RegisterOrConstant src) {
1152     ldr(rscratch1, adr);
1153     if (src.is_register())
1154       orr(rscratch1, rscratch1, src.as_register());
1155     else
1156       orr(rscratch1, rscratch1, src.as_constant());
1157     str(rscratch1, adr);
1158   }
1159 
1160   // A generic CAS; success or failure is in the EQ flag.
1161   // Clobbers rscratch1
1162   void cmpxchg(Register addr, Register expected, Register new_val,
1163                enum operand_size size,
1164                bool acquire, bool release, bool weak,
1165                Register result);
1166 
1167 #ifdef ASSERT
1168   // Template short-hand support to clean-up after a failed call to trampoline
1169   // call generation (see trampoline_call() below),  when a set of Labels must
1170   // be reset (before returning).
1171   template<typename Label, typename... More>
1172   void reset_labels(Label &lbl, More&... more) {
1173     lbl.reset(); reset_labels(more...);
1174   }
1175   template<typename Label>
1176   void reset_labels(Label &lbl) {
1177     lbl.reset();
1178   }
1179 #endif
1180 
1181 private:
1182   void compare_eq(Register rn, Register rm, enum operand_size size);
1183 
1184 public:
1185   // AArch64 OpenJDK uses four different types of calls:
1186   //   - direct call: bl pc_relative_offset
1187   //     This is the shortest and the fastest, but the offset has the range:
1188   //     +/-128MB for the release build, +/-2MB for the debug build.
1189   //
1190   //   - far call: adrp reg, pc_relative_offset; add; bl reg
1191   //     This is longer than a direct call. The offset has
1192   //     the range +/-4GB. As the code cache size is limited to 4GB,
1193   //     far calls can reach anywhere in the code cache. If a jump is
1194   //     needed rather than a call, a far jump 'b reg' can be used instead.
1195   //     All instructions are embedded at a call site.
1196   //
1197   //   - trampoline call:
1198   //     This is only available in C1/C2-generated code (nmethod). It is a combination
1199   //     of a direct call, which is used if the destination of a call is in range,
1200   //     and a register-indirect call. It has the advantages of reaching anywhere in
1201   //     the AArch64 address space and being patchable at runtime when the generated
1202   //     code is being executed by other threads.
1203   //
1204   //     [Main code section]
1205   //       bl trampoline
1206   //     [Stub code section]
1207   //     trampoline:
1208   //       ldr reg, pc + 8
1209   //       br reg
1210   //       <64-bit destination address>
1211   //
1212   //     If the destination is in range when the generated code is moved to the code
1213   //     cache, 'bl trampoline' is replaced with 'bl destination' and the trampoline
1214   //     is not used.
1215   //     The optimization does not remove the trampoline from the stub section.
1216   //     This is necessary because the trampoline may well be redirected later when
1217   //     code is patched, and the new destination may not be reachable by a simple BR
1218   //     instruction.
1219   //
1220   //   - indirect call: move reg, address; blr reg
1221   //     This too can reach anywhere in the address space, but it cannot be
1222   //     patched while code is running, so it must only be modified at a safepoint.
1223   //     This form of call is most suitable for targets at fixed addresses, which
1224   //     will never be patched.
1225   //
1226   // The patching we do conforms to the "Concurrent modification and
1227   // execution of instructions" section of the Arm Architectural
1228   // Reference Manual, which only allows B, BL, BRK, HVC, ISB, NOP, SMC,
1229   // or SVC instructions to be modified while another thread is
1230   // executing them.
1231   //
1232   // To patch a trampoline call when the BL can't reach, we first modify
1233   // the 64-bit destination address in the trampoline, then modify the
1234   // BL to point to the trampoline, then flush the instruction cache to
1235   // broadcast the change to all executing threads. See
1236   // NativeCall::set_destination_mt_safe for the details.
1237   //
1238   // There is a benign race in that the other thread might observe the
1239   // modified BL before it observes the modified 64-bit destination
1240   // address. That does not matter because the destination method has been
1241   // invalidated, so there will be a trap at its start.
1242   // For this to work, the destination address in the trampoline is
1243   // always updated, even if we're not using the trampoline.
1244 
1245   // Emit a direct call if the entry address will always be in range,
1246   // otherwise a trampoline call.
1247   // Supported entry.rspec():
1248   // - relocInfo::runtime_call_type
1249   // - relocInfo::opt_virtual_call_type
1250   // - relocInfo::static_call_type
1251   // - relocInfo::virtual_call_type
1252   //
1253   // Return: the call PC or null if CodeCache is full.
1254   // Clobbers: rscratch1
1255   address trampoline_call(Address entry);
1256 
1257   static bool far_branches() {
1258     return ReservedCodeCacheSize > branch_range;
1259   }
1260 
1261   // Check if branches to the non nmethod section require a far jump
1262   static bool codestub_branch_needs_far_jump() {
1263     return CodeCache::max_distance_to_non_nmethod() > branch_range;
1264   }
1265 
1266   // Emit a direct call/jump if the entry address will always be in range,
1267   // otherwise a far call/jump.
1268   // The address must be inside the code cache.
1269   // Supported entry.rspec():
1270   // - relocInfo::external_word_type
1271   // - relocInfo::runtime_call_type
1272   // - relocInfo::none
1273   // In the case of a far call/jump, the entry address is put in the tmp register.
1274   // The tmp register is invalidated.
1275   //
1276   // Far_jump returns the amount of the emitted code.
1277   void far_call(Address entry, Register tmp = rscratch1);
1278   int far_jump(Address entry, Register tmp = rscratch1);
1279 
1280   static int far_codestub_branch_size() {
1281     if (codestub_branch_needs_far_jump()) {
1282       return 3 * 4;  // adrp, add, br
1283     } else {
1284       return 4;
1285     }
1286   }
1287 
1288   // Emit the CompiledIC call idiom
1289   address ic_call(address entry, jint method_index = 0);
1290   static int ic_check_size();
1291   int ic_check(int end_alignment);
1292 
1293 public:
1294 
1295   // Data
1296 
1297   void mov_metadata(Register dst, Metadata* obj);
1298   Address allocate_metadata_address(Metadata* obj);
1299   Address constant_oop_address(jobject obj);
1300 
1301   void movoop(Register dst, jobject obj);
1302 
1303   // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
1304   void kernel_crc32(Register crc, Register buf, Register len,
1305         Register table0, Register table1, Register table2, Register table3,
1306         Register tmp, Register tmp2, Register tmp3);
1307   // CRC32 code for java.util.zip.CRC32C::updateBytes() intrinsic.
1308   void kernel_crc32c(Register crc, Register buf, Register len,
1309         Register table0, Register table1, Register table2, Register table3,
1310         Register tmp, Register tmp2, Register tmp3);
1311 
1312   // Stack push and pop individual 64 bit registers
1313   void push(Register src);
1314   void pop(Register dst);
1315 
1316   void repne_scan(Register addr, Register value, Register count,
1317                   Register scratch);
1318   void repne_scanw(Register addr, Register value, Register count,
1319                    Register scratch);
1320 
1321   typedef void (MacroAssembler::* add_sub_imm_insn)(Register Rd, Register Rn, unsigned imm);
1322   typedef void (MacroAssembler::* add_sub_reg_insn)(Register Rd, Register Rn, Register Rm, enum shift_kind kind, unsigned shift);
1323 
1324   // If a constant does not fit in an immediate field, generate some
1325   // number of MOV instructions and then perform the operation
1326   void wrap_add_sub_imm_insn(Register Rd, Register Rn, uint64_t imm,
1327                              add_sub_imm_insn insn1,
1328                              add_sub_reg_insn insn2, bool is32);
1329   // Separate vsn which sets the flags
1330   void wrap_adds_subs_imm_insn(Register Rd, Register Rn, uint64_t imm,
1331                                add_sub_imm_insn insn1,
1332                                add_sub_reg_insn insn2, bool is32);
1333 
1334 #define WRAP(INSN, is32)                                                \
1335   void INSN(Register Rd, Register Rn, uint64_t imm) {                   \
1336     wrap_add_sub_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN, is32); \
1337   }                                                                     \
1338                                                                         \
1339   void INSN(Register Rd, Register Rn, Register Rm,                      \
1340              enum shift_kind kind, unsigned shift = 0) {                \
1341     Assembler::INSN(Rd, Rn, Rm, kind, shift);                           \
1342   }                                                                     \
1343                                                                         \
1344   void INSN(Register Rd, Register Rn, Register Rm) {                    \
1345     Assembler::INSN(Rd, Rn, Rm);                                        \
1346   }                                                                     \
1347                                                                         \
1348   void INSN(Register Rd, Register Rn, Register Rm,                      \
1349            ext::operation option, int amount = 0) {                     \
1350     Assembler::INSN(Rd, Rn, Rm, option, amount);                        \
1351   }
1352 
1353   WRAP(add, false) WRAP(addw, true) WRAP(sub, false) WRAP(subw, true)
1354 
1355 #undef WRAP
1356 #define WRAP(INSN, is32)                                                \
1357   void INSN(Register Rd, Register Rn, uint64_t imm) {                   \
1358     wrap_adds_subs_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN, is32); \
1359   }                                                                     \
1360                                                                         \
1361   void INSN(Register Rd, Register Rn, Register Rm,                      \
1362              enum shift_kind kind, unsigned shift = 0) {                \
1363     Assembler::INSN(Rd, Rn, Rm, kind, shift);                           \
1364   }                                                                     \
1365                                                                         \
1366   void INSN(Register Rd, Register Rn, Register Rm) {                    \
1367     Assembler::INSN(Rd, Rn, Rm);                                        \
1368   }                                                                     \
1369                                                                         \
1370   void INSN(Register Rd, Register Rn, Register Rm,                      \
1371            ext::operation option, int amount = 0) {                     \
1372     Assembler::INSN(Rd, Rn, Rm, option, amount);                        \
1373   }
1374 
1375   WRAP(adds, false) WRAP(addsw, true) WRAP(subs, false) WRAP(subsw, true)
1376 
1377   void add(Register Rd, Register Rn, RegisterOrConstant increment);
1378   void addw(Register Rd, Register Rn, RegisterOrConstant increment);
1379   void sub(Register Rd, Register Rn, RegisterOrConstant decrement);
1380   void subw(Register Rd, Register Rn, RegisterOrConstant decrement);
1381 
1382   void adrp(Register reg1, const Address &dest, uint64_t &byte_offset);
1383 
1384   void tableswitch(Register index, jint lowbound, jint highbound,
1385                    Label &jumptable, Label &jumptable_end, int stride = 1) {
1386     adr(rscratch1, jumptable);
1387     subsw(rscratch2, index, lowbound);
1388     subsw(zr, rscratch2, highbound - lowbound);
1389     br(Assembler::HS, jumptable_end);
1390     add(rscratch1, rscratch1, rscratch2,
1391         ext::sxtw, exact_log2(stride * Assembler::instruction_size));
1392     br(rscratch1);
1393   }
1394 
1395   // Form an address from base + offset in Rd.  Rd may or may not
1396   // actually be used: you must use the Address that is returned.  It
1397   // is up to you to ensure that the shift provided matches the size
1398   // of your data.
1399   Address form_address(Register Rd, Register base, int64_t byte_offset, int shift);
1400 
1401   // Return true iff an address is within the 48-bit AArch64 address
1402   // space.
1403   bool is_valid_AArch64_address(address a) {
1404     return ((uint64_t)a >> 48) == 0;
1405   }
1406 
1407   // Load the base of the cardtable byte map into reg.
1408   void load_byte_map_base(Register reg);
1409 
1410   // Prolog generator routines to support switch between x86 code and
1411   // generated ARM code
1412 
1413   // routine to generate an x86 prolog for a stub function which
1414   // bootstraps into the generated ARM code which directly follows the
1415   // stub
1416   //
1417 
1418   public:
1419 
1420   void ldr_constant(Register dest, const Address &const_addr) {
1421     if (NearCpool) {
1422       ldr(dest, const_addr);
1423     } else {
1424       uint64_t offset;
1425       adrp(dest, InternalAddress(const_addr.target()), offset);
1426       ldr(dest, Address(dest, offset));
1427     }
1428   }
1429 
1430   address read_polling_page(Register r, relocInfo::relocType rtype);
1431   void get_polling_page(Register dest, relocInfo::relocType rtype);
1432 
1433   // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
1434   void update_byte_crc32(Register crc, Register val, Register table);
1435   void update_word_crc32(Register crc, Register v, Register tmp,
1436         Register table0, Register table1, Register table2, Register table3,
1437         bool upper = false);
1438 
1439   address count_positives(Register ary1, Register len, Register result);
1440 
1441   address arrays_equals(Register a1, Register a2, Register result, Register cnt1,
1442                         Register tmp1, Register tmp2, Register tmp3, int elem_size);
1443 
1444   void string_equals(Register a1, Register a2, Register result, Register cnt1);
1445 
1446   void fill_words(Register base, Register cnt, Register value);
1447   address zero_words(Register base, uint64_t cnt);
1448   address zero_words(Register ptr, Register cnt);
1449   void zero_dcache_blocks(Register base, Register cnt);
1450 
1451   static const int zero_words_block_size;
1452 
1453   address byte_array_inflate(Register src, Register dst, Register len,
1454                              FloatRegister vtmp1, FloatRegister vtmp2,
1455                              FloatRegister vtmp3, Register tmp4);
1456 
1457   void char_array_compress(Register src, Register dst, Register len,
1458                            Register res,
1459                            FloatRegister vtmp0, FloatRegister vtmp1,
1460                            FloatRegister vtmp2, FloatRegister vtmp3,
1461                            FloatRegister vtmp4, FloatRegister vtmp5);
1462 
1463   void encode_iso_array(Register src, Register dst,
1464                         Register len, Register res, bool ascii,
1465                         FloatRegister vtmp0, FloatRegister vtmp1,
1466                         FloatRegister vtmp2, FloatRegister vtmp3,
1467                         FloatRegister vtmp4, FloatRegister vtmp5);
1468 
1469   void generate_dsin_dcos(bool isCos, address npio2_hw, address two_over_pi,
1470       address pio2, address dsin_coef, address dcos_coef);
1471  private:
1472   // begin trigonometric functions support block
1473   void generate__ieee754_rem_pio2(address npio2_hw, address two_over_pi, address pio2);
1474   void generate__kernel_rem_pio2(address two_over_pi, address pio2);
1475   void generate_kernel_sin(FloatRegister x, bool iyIsOne, address dsin_coef);
1476   void generate_kernel_cos(FloatRegister x, address dcos_coef);
1477   // end trigonometric functions support block
1478   void add2_with_carry(Register final_dest_hi, Register dest_hi, Register dest_lo,
1479                        Register src1, Register src2);
1480   void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
1481     add2_with_carry(dest_hi, dest_hi, dest_lo, src1, src2);
1482   }
1483   void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
1484                              Register y, Register y_idx, Register z,
1485                              Register carry, Register product,
1486                              Register idx, Register kdx);
1487   void multiply_128_x_128_loop(Register y, Register z,
1488                                Register carry, Register carry2,
1489                                Register idx, Register jdx,
1490                                Register yz_idx1, Register yz_idx2,
1491                                Register tmp, Register tmp3, Register tmp4,
1492                                Register tmp7, Register product_hi);
1493   void kernel_crc32_using_crypto_pmull(Register crc, Register buf,
1494         Register len, Register tmp0, Register tmp1, Register tmp2,
1495         Register tmp3);
1496   void kernel_crc32_using_crc32(Register crc, Register buf,
1497         Register len, Register tmp0, Register tmp1, Register tmp2,
1498         Register tmp3);
1499   void kernel_crc32c_using_crypto_pmull(Register crc, Register buf,
1500         Register len, Register tmp0, Register tmp1, Register tmp2,
1501         Register tmp3);
1502   void kernel_crc32c_using_crc32c(Register crc, Register buf,
1503         Register len, Register tmp0, Register tmp1, Register tmp2,
1504         Register tmp3);
1505   void kernel_crc32_common_fold_using_crypto_pmull(Register crc, Register buf,
1506         Register len, Register tmp0, Register tmp1, Register tmp2,
1507         size_t table_offset);
1508 
1509   void ghash_modmul (FloatRegister result,
1510                      FloatRegister result_lo, FloatRegister result_hi, FloatRegister b,
1511                      FloatRegister a, FloatRegister vzr, FloatRegister a1_xor_a0, FloatRegister p,
1512                      FloatRegister t1, FloatRegister t2, FloatRegister t3);
1513   void ghash_load_wide(int index, Register data, FloatRegister result, FloatRegister state);
1514 public:
1515   void multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z,
1516                        Register tmp0, Register tmp1, Register tmp2, Register tmp3,
1517                        Register tmp4, Register tmp5, Register tmp6, Register tmp7);
1518   void mul_add(Register out, Register in, Register offs, Register len, Register k);
1519   void ghash_multiply(FloatRegister result_lo, FloatRegister result_hi,
1520                       FloatRegister a, FloatRegister b, FloatRegister a1_xor_a0,
1521                       FloatRegister tmp1, FloatRegister tmp2, FloatRegister tmp3);
1522   void ghash_multiply_wide(int index,
1523                            FloatRegister result_lo, FloatRegister result_hi,
1524                            FloatRegister a, FloatRegister b, FloatRegister a1_xor_a0,
1525                            FloatRegister tmp1, FloatRegister tmp2, FloatRegister tmp3);
1526   void ghash_reduce(FloatRegister result, FloatRegister lo, FloatRegister hi,
1527                     FloatRegister p, FloatRegister z, FloatRegister t1);
1528   void ghash_reduce_wide(int index, FloatRegister result, FloatRegister lo, FloatRegister hi,
1529                     FloatRegister p, FloatRegister z, FloatRegister t1);
1530   void ghash_processBlocks_wide(address p, Register state, Register subkeyH,
1531                                 Register data, Register blocks, int unrolls);
1532 
1533 
1534   void aesenc_loadkeys(Register key, Register keylen);
1535   void aesecb_encrypt(Register from, Register to, Register keylen,
1536                       FloatRegister data = v0, int unrolls = 1);
1537   void aesecb_decrypt(Register from, Register to, Register key, Register keylen);
1538   void aes_round(FloatRegister input, FloatRegister subkey);
1539 
1540   // ChaCha20 functions support block
1541   void cc20_quarter_round(FloatRegister aVec, FloatRegister bVec,
1542           FloatRegister cVec, FloatRegister dVec, FloatRegister scratch,
1543           FloatRegister tbl);
1544   void cc20_shift_lane_org(FloatRegister bVec, FloatRegister cVec,
1545           FloatRegister dVec, bool colToDiag);
1546 
1547   // Place an ISB after code may have been modified due to a safepoint.
1548   void safepoint_isb();
1549 
1550 private:
1551   // Return the effective address r + (r1 << ext) + offset.
1552   // Uses rscratch2.
1553   Address offsetted_address(Register r, Register r1, Address::extend ext,
1554                             int offset, int size);
1555 
1556 private:
1557   // Returns an address on the stack which is reachable with a ldr/str of size
1558   // Uses rscratch2 if the address is not directly reachable
1559   Address spill_address(int size, int offset, Register tmp=rscratch2);
1560   Address sve_spill_address(int sve_reg_size_in_bytes, int offset, Register tmp=rscratch2);
1561 
1562   bool merge_alignment_check(Register base, size_t size, int64_t cur_offset, int64_t prev_offset) const;
1563 
1564   // Check whether two loads/stores can be merged into ldp/stp.
1565   bool ldst_can_merge(Register rx, const Address &adr, size_t cur_size_in_bytes, bool is_store) const;
1566 
1567   // Merge current load/store with previous load/store into ldp/stp.
1568   void merge_ldst(Register rx, const Address &adr, size_t cur_size_in_bytes, bool is_store);
1569 
1570   // Try to merge two loads/stores into ldp/stp. If success, returns true else false.
1571   bool try_merge_ldst(Register rt, const Address &adr, size_t cur_size_in_bytes, bool is_store);
1572 
1573 public:
1574   void spill(Register Rx, bool is64, int offset) {
1575     if (is64) {
1576       str(Rx, spill_address(8, offset));
1577     } else {
1578       strw(Rx, spill_address(4, offset));
1579     }
1580   }
1581   void spill(FloatRegister Vx, SIMD_RegVariant T, int offset) {
1582     str(Vx, T, spill_address(1 << (int)T, offset));
1583   }
1584 
1585   void spill_sve_vector(FloatRegister Zx, int offset, int vector_reg_size_in_bytes) {
1586     sve_str(Zx, sve_spill_address(vector_reg_size_in_bytes, offset));
1587   }
1588   void spill_sve_predicate(PRegister pr, int offset, int predicate_reg_size_in_bytes) {
1589     sve_str(pr, sve_spill_address(predicate_reg_size_in_bytes, offset));
1590   }
1591 
1592   void unspill(Register Rx, bool is64, int offset) {
1593     if (is64) {
1594       ldr(Rx, spill_address(8, offset));
1595     } else {
1596       ldrw(Rx, spill_address(4, offset));
1597     }
1598   }
1599   void unspill(FloatRegister Vx, SIMD_RegVariant T, int offset) {
1600     ldr(Vx, T, spill_address(1 << (int)T, offset));
1601   }
1602 
1603   void unspill_sve_vector(FloatRegister Zx, int offset, int vector_reg_size_in_bytes) {
1604     sve_ldr(Zx, sve_spill_address(vector_reg_size_in_bytes, offset));
1605   }
1606   void unspill_sve_predicate(PRegister pr, int offset, int predicate_reg_size_in_bytes) {
1607     sve_ldr(pr, sve_spill_address(predicate_reg_size_in_bytes, offset));
1608   }
1609 
1610   void spill_copy128(int src_offset, int dst_offset,
1611                      Register tmp1=rscratch1, Register tmp2=rscratch2) {
1612     if (src_offset < 512 && (src_offset & 7) == 0 &&
1613         dst_offset < 512 && (dst_offset & 7) == 0) {
1614       ldp(tmp1, tmp2, Address(sp, src_offset));
1615       stp(tmp1, tmp2, Address(sp, dst_offset));
1616     } else {
1617       unspill(tmp1, true, src_offset);
1618       spill(tmp1, true, dst_offset);
1619       unspill(tmp1, true, src_offset+8);
1620       spill(tmp1, true, dst_offset+8);
1621     }
1622   }
1623   void spill_copy_sve_vector_stack_to_stack(int src_offset, int dst_offset,
1624                                             int sve_vec_reg_size_in_bytes) {
1625     assert(sve_vec_reg_size_in_bytes % 16 == 0, "unexpected sve vector reg size");
1626     for (int i = 0; i < sve_vec_reg_size_in_bytes / 16; i++) {
1627       spill_copy128(src_offset, dst_offset);
1628       src_offset += 16;
1629       dst_offset += 16;
1630     }
1631   }
1632   void spill_copy_sve_predicate_stack_to_stack(int src_offset, int dst_offset,
1633                                                int sve_predicate_reg_size_in_bytes) {
1634     sve_ldr(ptrue, sve_spill_address(sve_predicate_reg_size_in_bytes, src_offset));
1635     sve_str(ptrue, sve_spill_address(sve_predicate_reg_size_in_bytes, dst_offset));
1636     reinitialize_ptrue();
1637   }
1638   void cache_wb(Address line);
1639   void cache_wbsync(bool is_pre);
1640 
1641   // Code for java.lang.Thread::onSpinWait() intrinsic.
1642   void spin_wait();
1643 
1644   void lightweight_lock(Register basic_lock, Register obj, Register t1, Register t2, Register t3, Label& slow);
1645   void lightweight_unlock(Register obj, Register t1, Register t2, Register t3, Label& slow);
1646 
1647 private:
1648   // Check the current thread doesn't need a cross modify fence.
1649   void verify_cross_modify_fence_not_required() PRODUCT_RETURN;
1650 
1651 };
1652 
1653 #ifdef ASSERT
1654 inline bool AbstractAssembler::pd_check_instruction_mark() { return false; }
1655 #endif
1656 
1657 /**
1658  * class SkipIfEqual:
1659  *
1660  * Instantiating this class will result in assembly code being output that will
1661  * jump around any code emitted between the creation of the instance and it's
1662  * automatic destruction at the end of a scope block, depending on the value of
1663  * the flag passed to the constructor, which will be checked at run-time.
1664  */
1665 class SkipIfEqual {
1666  private:
1667   MacroAssembler* _masm;
1668   Label _label;
1669 
1670  public:
1671    SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
1672    ~SkipIfEqual();
1673 };
1674 
1675 struct tableswitch {
1676   Register _reg;
1677   int _insn_index; jint _first_key; jint _last_key;
1678   Label _after;
1679   Label _branches;
1680 };
1681 
1682 #endif // CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP