1 /*
2 * Copyright (c) 1997, 2022, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2014, 2021, Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #ifndef CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
27 #define CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
28
29 #include "asm/assembler.inline.hpp"
30 #include "code/vmreg.hpp"
31 #include "metaprogramming/enableIf.hpp"
32 #include "oops/compressedOops.hpp"
33 #include "runtime/vm_version.hpp"
34 #include "utilities/powerOfTwo.hpp"
35
36 class OopMap;
37
38 // MacroAssembler extends Assembler by frequently used macros.
39 //
40 // Instructions for which a 'better' code sequence exists depending
41 // on arguments should also go in here.
42
43 class MacroAssembler: public Assembler {
44 friend class LIR_Assembler;
45
46 public:
47 using Assembler::mov;
48 using Assembler::movi;
49
50 protected:
51
52 // Support for VM calls
53 //
54 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
55 // may customize this version by overriding it for its purposes (e.g., to save/restore
56 // additional registers when doing a VM call).
57 virtual void call_VM_leaf_base(
58 address entry_point, // the entry point
59 int number_of_arguments, // the number of arguments to pop after the call
60 Label *retaddr = NULL
61 );
62
63 virtual void call_VM_leaf_base(
64 address entry_point, // the entry point
65 int number_of_arguments, // the number of arguments to pop after the call
66 Label &retaddr) {
67 call_VM_leaf_base(entry_point, number_of_arguments, &retaddr);
68 }
69
70 // This is the base routine called by the different versions of call_VM. The interpreter
71 // may customize this version by overriding it for its purposes (e.g., to save/restore
72 // additional registers when doing a VM call).
73 //
74 // If no java_thread register is specified (noreg) than rthread will be used instead. call_VM_base
75 // returns the register which contains the thread upon return. If a thread register has been
76 // specified, the return value will correspond to that register. If no last_java_sp is specified
77 // (noreg) than rsp will be used instead.
78 virtual void call_VM_base( // returns the register containing the thread upon return
79 Register oop_result, // where an oop-result ends up if any; use noreg otherwise
80 Register java_thread, // the thread if computed before ; use noreg otherwise
81 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise
82 address entry_point, // the entry point
83 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call
84 bool check_exceptions // whether to check for pending exceptions after return
85 );
86
87 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
88
89 public:
90
91 enum KlassDecodeMode {
92 KlassDecodeNone,
93 KlassDecodeZero,
94 KlassDecodeXor,
95 KlassDecodeMovk
96 };
97
98 // Return the current narrow Klass pointer decode mode. Initialized on first call.
99 static KlassDecodeMode klass_decode_mode();
100
101 // Given an arbitrary base address, return the KlassDecodeMode that would be used. Return KlassDecodeNone
102 // if base address is not valid for encoding.
103 static KlassDecodeMode klass_decode_mode_for_base(address base);
104
105 // Returns a static string
106 static const char* describe_klass_decode_mode(KlassDecodeMode mode);
107
108 private:
109
110 static KlassDecodeMode _klass_decode_mode;
111
112 public:
113 MacroAssembler(CodeBuffer* code) : Assembler(code) {}
114
115 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
116 // The implementation is only non-empty for the InterpreterMacroAssembler,
117 // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
118 virtual void check_and_handle_popframe(Register java_thread);
119 virtual void check_and_handle_earlyret(Register java_thread);
120
121 void safepoint_poll(Label& slow_path, bool at_return, bool acquire, bool in_nmethod, Register tmp = rscratch1);
122 void rt_call(address dest, Register tmp = rscratch1);
123
124 // Helper functions for statistics gathering.
125 // Unconditional atomic increment.
126 void atomic_incw(Register counter_addr, Register tmp, Register tmp2);
127 void atomic_incw(Address counter_addr, Register tmp1, Register tmp2, Register tmp3) {
128 lea(tmp1, counter_addr);
129 atomic_incw(tmp1, tmp2, tmp3);
130 }
131 // Load Effective Address
132 void lea(Register r, const Address &a) {
133 InstructionMark im(this);
134 code_section()->relocate(inst_mark(), a.rspec());
135 a.lea(this, r);
136 }
137
138 /* Sometimes we get misaligned loads and stores, usually from Unsafe
139 accesses, and these can exceed the offset range. */
140 Address legitimize_address(const Address &a, int size, Register scratch) {
141 if (a.getMode() == Address::base_plus_offset) {
142 if (! Address::offset_ok_for_immed(a.offset(), exact_log2(size))) {
143 block_comment("legitimize_address {");
144 lea(scratch, a);
145 block_comment("} legitimize_address");
146 return Address(scratch);
147 }
148 }
149 return a;
150 }
151
152 void addmw(Address a, Register incr, Register scratch) {
153 ldrw(scratch, a);
154 addw(scratch, scratch, incr);
155 strw(scratch, a);
156 }
157
158 // Add constant to memory word
159 void addmw(Address a, int imm, Register scratch) {
160 ldrw(scratch, a);
161 if (imm > 0)
162 addw(scratch, scratch, (unsigned)imm);
163 else
164 subw(scratch, scratch, (unsigned)-imm);
165 strw(scratch, a);
166 }
167
168 void bind(Label& L) {
169 Assembler::bind(L);
170 code()->clear_last_insn();
171 }
172
173 void membar(Membar_mask_bits order_constraint);
174
175 using Assembler::ldr;
176 using Assembler::str;
177 using Assembler::ldrw;
178 using Assembler::strw;
179
180 void ldr(Register Rx, const Address &adr);
181 void ldrw(Register Rw, const Address &adr);
182 void str(Register Rx, const Address &adr);
183 void strw(Register Rx, const Address &adr);
184
185 // Frame creation and destruction shared between JITs.
186 void build_frame(int framesize);
187 void remove_frame(int framesize);
188
189 virtual void _call_Unimplemented(address call_site) {
190 mov(rscratch2, call_site);
191 }
192
193 // Microsoft's MSVC team thinks that the __FUNCSIG__ is approximately (sympathy for calling conventions) equivalent to __PRETTY_FUNCTION__
194 // Also, from Clang patch: "It is very similar to GCC's PRETTY_FUNCTION, except it prints the calling convention."
195 // https://reviews.llvm.org/D3311
196
197 #ifdef _WIN64
198 #define call_Unimplemented() _call_Unimplemented((address)__FUNCSIG__)
199 #else
200 #define call_Unimplemented() _call_Unimplemented((address)__PRETTY_FUNCTION__)
201 #endif
202
203 // aliases defined in AARCH64 spec
204
205 template<class T>
206 inline void cmpw(Register Rd, T imm) { subsw(zr, Rd, imm); }
207
208 inline void cmp(Register Rd, unsigned char imm8) { subs(zr, Rd, imm8); }
209 inline void cmp(Register Rd, unsigned imm) = delete;
210
211 template<class T>
212 inline void cmnw(Register Rd, T imm) { addsw(zr, Rd, imm); }
213
214 inline void cmn(Register Rd, unsigned char imm8) { adds(zr, Rd, imm8); }
215 inline void cmn(Register Rd, unsigned imm) = delete;
216
217 void cset(Register Rd, Assembler::Condition cond) {
218 csinc(Rd, zr, zr, ~cond);
219 }
220 void csetw(Register Rd, Assembler::Condition cond) {
221 csincw(Rd, zr, zr, ~cond);
222 }
223
224 void cneg(Register Rd, Register Rn, Assembler::Condition cond) {
225 csneg(Rd, Rn, Rn, ~cond);
226 }
227 void cnegw(Register Rd, Register Rn, Assembler::Condition cond) {
228 csnegw(Rd, Rn, Rn, ~cond);
229 }
230
231 inline void movw(Register Rd, Register Rn) {
232 if (Rd == sp || Rn == sp) {
233 Assembler::addw(Rd, Rn, 0U);
234 } else {
235 orrw(Rd, zr, Rn);
236 }
237 }
238 inline void mov(Register Rd, Register Rn) {
239 assert(Rd != r31_sp && Rn != r31_sp, "should be");
240 if (Rd == Rn) {
241 } else if (Rd == sp || Rn == sp) {
242 Assembler::add(Rd, Rn, 0U);
243 } else {
244 orr(Rd, zr, Rn);
245 }
246 }
247
248 inline void moviw(Register Rd, unsigned imm) { orrw(Rd, zr, imm); }
249 inline void movi(Register Rd, unsigned imm) { orr(Rd, zr, imm); }
250
251 inline void tstw(Register Rd, Register Rn) { andsw(zr, Rd, Rn); }
252 inline void tst(Register Rd, Register Rn) { ands(zr, Rd, Rn); }
253
254 inline void tstw(Register Rd, uint64_t imm) { andsw(zr, Rd, imm); }
255 inline void tst(Register Rd, uint64_t imm) { ands(zr, Rd, imm); }
256
257 inline void bfiw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
258 bfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
259 }
260 inline void bfi(Register Rd, Register Rn, unsigned lsb, unsigned width) {
261 bfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
262 }
263
264 inline void bfxilw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
265 bfmw(Rd, Rn, lsb, (lsb + width - 1));
266 }
267 inline void bfxil(Register Rd, Register Rn, unsigned lsb, unsigned width) {
268 bfm(Rd, Rn, lsb , (lsb + width - 1));
269 }
270
271 inline void sbfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
272 sbfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
273 }
274 inline void sbfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) {
275 sbfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
276 }
277
278 inline void sbfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
279 sbfmw(Rd, Rn, lsb, (lsb + width - 1));
280 }
281 inline void sbfx(Register Rd, Register Rn, unsigned lsb, unsigned width) {
282 sbfm(Rd, Rn, lsb , (lsb + width - 1));
283 }
284
285 inline void ubfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
286 ubfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
287 }
288 inline void ubfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) {
289 ubfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
290 }
291
292 inline void ubfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
293 ubfmw(Rd, Rn, lsb, (lsb + width - 1));
294 }
295 inline void ubfx(Register Rd, Register Rn, unsigned lsb, unsigned width) {
296 ubfm(Rd, Rn, lsb , (lsb + width - 1));
297 }
298
299 inline void asrw(Register Rd, Register Rn, unsigned imm) {
300 sbfmw(Rd, Rn, imm, 31);
301 }
302
303 inline void asr(Register Rd, Register Rn, unsigned imm) {
304 sbfm(Rd, Rn, imm, 63);
305 }
306
307 inline void lslw(Register Rd, Register Rn, unsigned imm) {
308 ubfmw(Rd, Rn, ((32 - imm) & 31), (31 - imm));
309 }
310
311 inline void lsl(Register Rd, Register Rn, unsigned imm) {
312 ubfm(Rd, Rn, ((64 - imm) & 63), (63 - imm));
313 }
314
315 inline void lsrw(Register Rd, Register Rn, unsigned imm) {
316 ubfmw(Rd, Rn, imm, 31);
317 }
318
319 inline void lsr(Register Rd, Register Rn, unsigned imm) {
320 ubfm(Rd, Rn, imm, 63);
321 }
322
323 inline void rorw(Register Rd, Register Rn, unsigned imm) {
324 extrw(Rd, Rn, Rn, imm);
325 }
326
327 inline void ror(Register Rd, Register Rn, unsigned imm) {
328 extr(Rd, Rn, Rn, imm);
329 }
330
331 inline void sxtbw(Register Rd, Register Rn) {
332 sbfmw(Rd, Rn, 0, 7);
333 }
334 inline void sxthw(Register Rd, Register Rn) {
335 sbfmw(Rd, Rn, 0, 15);
336 }
337 inline void sxtb(Register Rd, Register Rn) {
338 sbfm(Rd, Rn, 0, 7);
339 }
340 inline void sxth(Register Rd, Register Rn) {
341 sbfm(Rd, Rn, 0, 15);
342 }
343 inline void sxtw(Register Rd, Register Rn) {
344 sbfm(Rd, Rn, 0, 31);
345 }
346
347 inline void uxtbw(Register Rd, Register Rn) {
348 ubfmw(Rd, Rn, 0, 7);
349 }
350 inline void uxthw(Register Rd, Register Rn) {
351 ubfmw(Rd, Rn, 0, 15);
352 }
353 inline void uxtb(Register Rd, Register Rn) {
354 ubfm(Rd, Rn, 0, 7);
355 }
356 inline void uxth(Register Rd, Register Rn) {
357 ubfm(Rd, Rn, 0, 15);
358 }
359 inline void uxtw(Register Rd, Register Rn) {
360 ubfm(Rd, Rn, 0, 31);
361 }
362
363 inline void cmnw(Register Rn, Register Rm) {
364 addsw(zr, Rn, Rm);
365 }
366 inline void cmn(Register Rn, Register Rm) {
367 adds(zr, Rn, Rm);
368 }
369
370 inline void cmpw(Register Rn, Register Rm) {
371 subsw(zr, Rn, Rm);
372 }
373 inline void cmp(Register Rn, Register Rm) {
374 subs(zr, Rn, Rm);
375 }
376
377 inline void negw(Register Rd, Register Rn) {
378 subw(Rd, zr, Rn);
379 }
380
381 inline void neg(Register Rd, Register Rn) {
382 sub(Rd, zr, Rn);
383 }
384
385 inline void negsw(Register Rd, Register Rn) {
386 subsw(Rd, zr, Rn);
387 }
388
389 inline void negs(Register Rd, Register Rn) {
390 subs(Rd, zr, Rn);
391 }
392
393 inline void cmnw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
394 addsw(zr, Rn, Rm, kind, shift);
395 }
396 inline void cmn(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
397 adds(zr, Rn, Rm, kind, shift);
398 }
399
400 inline void cmpw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
401 subsw(zr, Rn, Rm, kind, shift);
402 }
403 inline void cmp(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
404 subs(zr, Rn, Rm, kind, shift);
405 }
406
407 inline void negw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
408 subw(Rd, zr, Rn, kind, shift);
409 }
410
411 inline void neg(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
412 sub(Rd, zr, Rn, kind, shift);
413 }
414
415 inline void negsw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
416 subsw(Rd, zr, Rn, kind, shift);
417 }
418
419 inline void negs(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
420 subs(Rd, zr, Rn, kind, shift);
421 }
422
423 inline void mnegw(Register Rd, Register Rn, Register Rm) {
424 msubw(Rd, Rn, Rm, zr);
425 }
426 inline void mneg(Register Rd, Register Rn, Register Rm) {
427 msub(Rd, Rn, Rm, zr);
428 }
429
430 inline void mulw(Register Rd, Register Rn, Register Rm) {
431 maddw(Rd, Rn, Rm, zr);
432 }
433 inline void mul(Register Rd, Register Rn, Register Rm) {
434 madd(Rd, Rn, Rm, zr);
435 }
436
437 inline void smnegl(Register Rd, Register Rn, Register Rm) {
438 smsubl(Rd, Rn, Rm, zr);
439 }
440 inline void smull(Register Rd, Register Rn, Register Rm) {
441 smaddl(Rd, Rn, Rm, zr);
442 }
443
444 inline void umnegl(Register Rd, Register Rn, Register Rm) {
445 umsubl(Rd, Rn, Rm, zr);
446 }
447 inline void umull(Register Rd, Register Rn, Register Rm) {
448 umaddl(Rd, Rn, Rm, zr);
449 }
450
451 #define WRAP(INSN) \
452 void INSN(Register Rd, Register Rn, Register Rm, Register Ra) { \
453 if (VM_Version::supports_a53mac() && Ra != zr) \
454 nop(); \
455 Assembler::INSN(Rd, Rn, Rm, Ra); \
456 }
457
458 WRAP(madd) WRAP(msub) WRAP(maddw) WRAP(msubw)
459 WRAP(smaddl) WRAP(smsubl) WRAP(umaddl) WRAP(umsubl)
460 #undef WRAP
461
462
463 // macro assembly operations needed for aarch64
464
465 // first two private routines for loading 32 bit or 64 bit constants
466 private:
467
468 void mov_immediate64(Register dst, uint64_t imm64);
469 void mov_immediate32(Register dst, uint32_t imm32);
470
471 int push(unsigned int bitset, Register stack);
472 int pop(unsigned int bitset, Register stack);
473
474 int push_fp(unsigned int bitset, Register stack);
475 int pop_fp(unsigned int bitset, Register stack);
476
477 int push_p(unsigned int bitset, Register stack);
478 int pop_p(unsigned int bitset, Register stack);
479
480 void mov(Register dst, Address a);
481
482 public:
483 void push(RegSet regs, Register stack) { if (regs.bits()) push(regs.bits(), stack); }
484 void pop(RegSet regs, Register stack) { if (regs.bits()) pop(regs.bits(), stack); }
485
486 void push_fp(FloatRegSet regs, Register stack) { if (regs.bits()) push_fp(regs.bits(), stack); }
487 void pop_fp(FloatRegSet regs, Register stack) { if (regs.bits()) pop_fp(regs.bits(), stack); }
488
489 static RegSet call_clobbered_gp_registers();
490
491 void push_p(PRegSet regs, Register stack) { if (regs.bits()) push_p(regs.bits(), stack); }
492 void pop_p(PRegSet regs, Register stack) { if (regs.bits()) pop_p(regs.bits(), stack); }
493
494 // Push and pop everything that might be clobbered by a native
495 // runtime call except rscratch1 and rscratch2. (They are always
496 // scratch, so we don't have to protect them.) Only save the lower
497 // 64 bits of each vector register. Additional registers can be excluded
498 // in a passed RegSet.
499 void push_call_clobbered_registers_except(RegSet exclude);
500 void pop_call_clobbered_registers_except(RegSet exclude);
501
502 void push_call_clobbered_registers() {
503 push_call_clobbered_registers_except(RegSet());
504 }
505 void pop_call_clobbered_registers() {
506 pop_call_clobbered_registers_except(RegSet());
507 }
508
509
510 // now mov instructions for loading absolute addresses and 32 or
511 // 64 bit integers
512
513 inline void mov(Register dst, address addr) { mov_immediate64(dst, (uint64_t)addr); }
514
515 template<typename T, ENABLE_IF(std::is_integral<T>::value)>
516 inline void mov(Register dst, T o) { mov_immediate64(dst, (uint64_t)o); }
517
518 inline void movw(Register dst, uint32_t imm32) { mov_immediate32(dst, imm32); }
519
520 void mov(Register dst, RegisterOrConstant src) {
521 if (src.is_register())
522 mov(dst, src.as_register());
523 else
524 mov(dst, src.as_constant());
525 }
526
527 void movptr(Register r, uintptr_t imm64);
528
529 void mov(FloatRegister Vd, SIMD_Arrangement T, uint64_t imm64);
530
531 void mov(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) {
532 orr(Vd, T, Vn, Vn);
533 }
534
535
536 public:
537
538 // Generalized Test Bit And Branch, including a "far" variety which
539 // spans more than 32KiB.
540 void tbr(Condition cond, Register Rt, int bitpos, Label &dest, bool isfar = false) {
541 assert(cond == EQ || cond == NE, "must be");
542
543 if (isfar)
544 cond = ~cond;
545
546 void (Assembler::* branch)(Register Rt, int bitpos, Label &L);
547 if (cond == Assembler::EQ)
548 branch = &Assembler::tbz;
549 else
550 branch = &Assembler::tbnz;
551
552 if (isfar) {
553 Label L;
554 (this->*branch)(Rt, bitpos, L);
555 b(dest);
556 bind(L);
557 } else {
558 (this->*branch)(Rt, bitpos, dest);
559 }
560 }
561
562 // macro instructions for accessing and updating floating point
563 // status register
564 //
565 // FPSR : op1 == 011
566 // CRn == 0100
567 // CRm == 0100
568 // op2 == 001
569
570 inline void get_fpsr(Register reg)
571 {
572 mrs(0b11, 0b0100, 0b0100, 0b001, reg);
573 }
574
575 inline void set_fpsr(Register reg)
576 {
577 msr(0b011, 0b0100, 0b0100, 0b001, reg);
578 }
579
580 inline void clear_fpsr()
581 {
582 msr(0b011, 0b0100, 0b0100, 0b001, zr);
583 }
584
585 // DCZID_EL0: op1 == 011
586 // CRn == 0000
587 // CRm == 0000
588 // op2 == 111
589 inline void get_dczid_el0(Register reg)
590 {
591 mrs(0b011, 0b0000, 0b0000, 0b111, reg);
592 }
593
594 // CTR_EL0: op1 == 011
595 // CRn == 0000
596 // CRm == 0000
597 // op2 == 001
598 inline void get_ctr_el0(Register reg)
599 {
600 mrs(0b011, 0b0000, 0b0000, 0b001, reg);
601 }
602
603 // idiv variant which deals with MINLONG as dividend and -1 as divisor
604 int corrected_idivl(Register result, Register ra, Register rb,
605 bool want_remainder, Register tmp = rscratch1);
606 int corrected_idivq(Register result, Register ra, Register rb,
607 bool want_remainder, Register tmp = rscratch1);
608
609 // Support for NULL-checks
610 //
611 // Generates code that causes a NULL OS exception if the content of reg is NULL.
612 // If the accessed location is M[reg + offset] and the offset is known, provide the
613 // offset. No explicit code generation is needed if the offset is within a certain
614 // range (0 <= offset <= page_size).
615
616 virtual void null_check(Register reg, int offset = -1);
617 static bool needs_explicit_null_check(intptr_t offset);
618 static bool uses_implicit_null_check(void* address);
619
620 static address target_addr_for_insn(address insn_addr, unsigned insn);
621 static address target_addr_for_insn_or_null(address insn_addr, unsigned insn);
622 static address target_addr_for_insn(address insn_addr) {
623 unsigned insn = *(unsigned*)insn_addr;
624 return target_addr_for_insn(insn_addr, insn);
625 }
626 static address target_addr_for_insn_or_null(address insn_addr) {
627 unsigned insn = *(unsigned*)insn_addr;
628 return target_addr_for_insn_or_null(insn_addr, insn);
629 }
630
631 // Required platform-specific helpers for Label::patch_instructions.
632 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
633 static int pd_patch_instruction_size(address branch, address target);
634 static void pd_patch_instruction(address branch, address target, const char* file = NULL, int line = 0) {
635 pd_patch_instruction_size(branch, target);
636 }
637 static address pd_call_destination(address branch) {
638 return target_addr_for_insn(branch);
639 }
640 #ifndef PRODUCT
641 static void pd_print_patched_instruction(address branch);
642 #endif
643
644 static int patch_oop(address insn_addr, address o);
645 static int patch_narrow_klass(address insn_addr, narrowKlass n);
646
647 // Return whether code is emitted to a scratch blob.
648 virtual bool in_scratch_emit_size() {
649 return false;
650 }
651 address emit_trampoline_stub(int insts_call_instruction_offset, address target);
652 void emit_static_call_stub();
653
654 // The following 4 methods return the offset of the appropriate move instruction
655
656 // Support for fast byte/short loading with zero extension (depending on particular CPU)
657 int load_unsigned_byte(Register dst, Address src);
658 int load_unsigned_short(Register dst, Address src);
659
660 // Support for fast byte/short loading with sign extension (depending on particular CPU)
661 int load_signed_byte(Register dst, Address src);
662 int load_signed_short(Register dst, Address src);
663
664 int load_signed_byte32(Register dst, Address src);
665 int load_signed_short32(Register dst, Address src);
666
667 // Support for sign-extension (hi:lo = extend_sign(lo))
668 void extend_sign(Register hi, Register lo);
669
670 // Load and store values by size and signed-ness
671 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg);
672 void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg);
673
674 // Support for inc/dec with optimal instruction selection depending on value
675
676 // x86_64 aliases an unqualified register/address increment and
677 // decrement to call incrementq and decrementq but also supports
678 // explicitly sized calls to incrementq/decrementq or
679 // incrementl/decrementl
680
681 // for aarch64 the proper convention would be to use
682 // increment/decrement for 64 bit operations and
683 // incrementw/decrementw for 32 bit operations. so when porting
684 // x86_64 code we can leave calls to increment/decrement as is,
685 // replace incrementq/decrementq with increment/decrement and
686 // replace incrementl/decrementl with incrementw/decrementw.
687
688 // n.b. increment/decrement calls with an Address destination will
689 // need to use a scratch register to load the value to be
690 // incremented. increment/decrement calls which add or subtract a
691 // constant value greater than 2^12 will need to use a 2nd scratch
692 // register to hold the constant. so, a register increment/decrement
693 // may trash rscratch2 and an address increment/decrement trash
694 // rscratch and rscratch2
695
696 void decrementw(Address dst, int value = 1);
697 void decrementw(Register reg, int value = 1);
698
699 void decrement(Register reg, int value = 1);
700 void decrement(Address dst, int value = 1);
701
702 void incrementw(Address dst, int value = 1);
703 void incrementw(Register reg, int value = 1);
704
705 void increment(Register reg, int value = 1);
706 void increment(Address dst, int value = 1);
707
708
709 // Alignment
710 void align(int modulus);
711
712 // nop
713 void post_call_nop();
714
715 // Stack frame creation/removal
716 void enter(bool strip_ret_addr = false);
717 void leave();
718
719 // ROP Protection
720 void protect_return_address();
721 void protect_return_address(Register return_reg, Register temp_reg);
722 void authenticate_return_address(Register return_reg = lr);
723 void authenticate_return_address(Register return_reg, Register temp_reg);
724 void strip_return_address();
725 void check_return_address(Register return_reg=lr) PRODUCT_RETURN;
726
727 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
728 // The pointer will be loaded into the thread register.
729 void get_thread(Register thread);
730
731 // support for argument shuffling
732 void move32_64(VMRegPair src, VMRegPair dst, Register tmp = rscratch1);
733 void float_move(VMRegPair src, VMRegPair dst, Register tmp = rscratch1);
734 void long_move(VMRegPair src, VMRegPair dst, Register tmp = rscratch1);
735 void double_move(VMRegPair src, VMRegPair dst, Register tmp = rscratch1);
736 void object_move(
737 OopMap* map,
738 int oop_handle_offset,
739 int framesize_in_slots,
740 VMRegPair src,
741 VMRegPair dst,
742 bool is_receiver,
743 int* receiver_offset);
744
745
746 // Support for VM calls
747 //
748 // It is imperative that all calls into the VM are handled via the call_VM macros.
749 // They make sure that the stack linkage is setup correctly. call_VM's correspond
750 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
751
752
753 void call_VM(Register oop_result,
754 address entry_point,
755 bool check_exceptions = true);
756 void call_VM(Register oop_result,
757 address entry_point,
758 Register arg_1,
759 bool check_exceptions = true);
760 void call_VM(Register oop_result,
761 address entry_point,
762 Register arg_1, Register arg_2,
763 bool check_exceptions = true);
764 void call_VM(Register oop_result,
765 address entry_point,
766 Register arg_1, Register arg_2, Register arg_3,
767 bool check_exceptions = true);
768
769 // Overloadings with last_Java_sp
770 void call_VM(Register oop_result,
771 Register last_java_sp,
772 address entry_point,
773 int number_of_arguments = 0,
774 bool check_exceptions = true);
775 void call_VM(Register oop_result,
776 Register last_java_sp,
777 address entry_point,
778 Register arg_1, bool
779 check_exceptions = true);
780 void call_VM(Register oop_result,
781 Register last_java_sp,
782 address entry_point,
783 Register arg_1, Register arg_2,
784 bool check_exceptions = true);
785 void call_VM(Register oop_result,
786 Register last_java_sp,
787 address entry_point,
788 Register arg_1, Register arg_2, Register arg_3,
789 bool check_exceptions = true);
790
791 void get_vm_result (Register oop_result, Register thread);
792 void get_vm_result_2(Register metadata_result, Register thread);
793
794 // These always tightly bind to MacroAssembler::call_VM_base
795 // bypassing the virtual implementation
796 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
797 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
798 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
799 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
800 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
801
802 void call_VM_leaf(address entry_point,
803 int number_of_arguments = 0);
804 void call_VM_leaf(address entry_point,
805 Register arg_1);
806 void call_VM_leaf(address entry_point,
807 Register arg_1, Register arg_2);
808 void call_VM_leaf(address entry_point,
809 Register arg_1, Register arg_2, Register arg_3);
810
811 // These always tightly bind to MacroAssembler::call_VM_leaf_base
812 // bypassing the virtual implementation
813 void super_call_VM_leaf(address entry_point);
814 void super_call_VM_leaf(address entry_point, Register arg_1);
815 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
816 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
817 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
818
819 // last Java Frame (fills frame anchor)
820 void set_last_Java_frame(Register last_java_sp,
821 Register last_java_fp,
822 address last_java_pc,
823 Register scratch);
824
825 void set_last_Java_frame(Register last_java_sp,
826 Register last_java_fp,
827 Label &last_java_pc,
828 Register scratch);
829
830 void set_last_Java_frame(Register last_java_sp,
831 Register last_java_fp,
832 Register last_java_pc,
833 Register scratch);
834
835 void reset_last_Java_frame(Register thread);
836
837 // thread in the default location (rthread)
838 void reset_last_Java_frame(bool clear_fp);
839
840 // Stores
841 void store_check(Register obj); // store check for obj - register is destroyed afterwards
842 void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed)
843
844 void resolve_jobject(Register value, Register tmp1, Register tmp2);
845
846 // C 'boolean' to Java boolean: x == 0 ? 0 : 1
847 void c2bool(Register x);
848
849 void load_method_holder_cld(Register rresult, Register rmethod);
850 void load_method_holder(Register holder, Register method);
851
852 // oop manipulations
853 void load_nklass(Register dst, Register src);
854 void load_klass(Register dst, Register src);
855 void cmp_klass(Register oop, Register trial_klass, Register tmp);
856
857 void resolve_weak_handle(Register result, Register tmp1, Register tmp2);
858 void resolve_oop_handle(Register result, Register tmp1, Register tmp2);
859 void load_mirror(Register dst, Register method, Register tmp1, Register tmp2);
860
861 void access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
862 Register tmp1, Register tmp2);
863
864 void access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register src,
865 Register tmp1, Register tmp2, Register tmp3);
866
867 void load_heap_oop(Register dst, Address src, Register tmp1 = noreg,
868 Register tmp2 = noreg, DecoratorSet decorators = 0);
869
870 void load_heap_oop_not_null(Register dst, Address src, Register tmp1 = noreg,
871 Register tmp2 = noreg, DecoratorSet decorators = 0);
872 void store_heap_oop(Address dst, Register src, Register tmp1 = noreg,
873 Register tmp2 = noreg, Register tmp3 = noreg, DecoratorSet decorators = 0);
874
875 // currently unimplemented
876 // Used for storing NULL. All other oop constants should be
877 // stored using routines that take a jobject.
878 void store_heap_oop_null(Address dst);
879
880 // This dummy is to prevent a call to store_heap_oop from
881 // converting a zero (like NULL) into a Register by giving
882 // the compiler two choices it can't resolve
883
884 void store_heap_oop(Address dst, void* dummy);
885
886 void encode_heap_oop(Register d, Register s);
887 void encode_heap_oop(Register r) { encode_heap_oop(r, r); }
888 void decode_heap_oop(Register d, Register s);
889 void decode_heap_oop(Register r) { decode_heap_oop(r, r); }
890 void encode_heap_oop_not_null(Register r);
891 void decode_heap_oop_not_null(Register r);
892 void encode_heap_oop_not_null(Register dst, Register src);
893 void decode_heap_oop_not_null(Register dst, Register src);
894
895 void set_narrow_oop(Register dst, jobject obj);
896
897 void encode_klass_not_null(Register r);
898 void decode_klass_not_null(Register r);
899 void encode_klass_not_null(Register dst, Register src);
900 void decode_klass_not_null(Register dst, Register src);
901
902 void set_narrow_klass(Register dst, Klass* k);
903
904 // if heap base register is used - reinit it with the correct value
905 void reinit_heapbase();
906
907 DEBUG_ONLY(void verify_heapbase(const char* msg);)
908
909 void push_CPU_state(bool save_vectors = false, bool use_sve = false,
910 int sve_vector_size_in_bytes = 0, int total_predicate_in_bytes = 0);
911 void pop_CPU_state(bool restore_vectors = false, bool use_sve = false,
912 int sve_vector_size_in_bytes = 0, int total_predicate_in_bytes = 0);
913
914 void push_cont_fastpath(Register java_thread);
915 void pop_cont_fastpath(Register java_thread);
916
917 // Round up to a power of two
918 void round_to(Register reg, int modulus);
919
920 // java.lang.Math::round intrinsics
921 void java_round_double(Register dst, FloatRegister src, FloatRegister ftmp);
922 void java_round_float(Register dst, FloatRegister src, FloatRegister ftmp);
923
924 // allocation
925 void tlab_allocate(
926 Register obj, // result: pointer to object after successful allocation
927 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
928 int con_size_in_bytes, // object size in bytes if known at compile time
929 Register t1, // temp register
930 Register t2, // temp register
931 Label& slow_case // continuation point if fast allocation fails
932 );
933 void verify_tlab();
934
935 // interface method calling
936 void lookup_interface_method(Register recv_klass,
937 Register intf_klass,
938 RegisterOrConstant itable_index,
939 Register method_result,
940 Register scan_temp,
941 Label& no_such_interface,
942 bool return_method = true);
943
944 // virtual method calling
945 // n.b. x86 allows RegisterOrConstant for vtable_index
946 void lookup_virtual_method(Register recv_klass,
947 RegisterOrConstant vtable_index,
948 Register method_result);
949
950 // Test sub_klass against super_klass, with fast and slow paths.
951
952 // The fast path produces a tri-state answer: yes / no / maybe-slow.
953 // One of the three labels can be NULL, meaning take the fall-through.
954 // If super_check_offset is -1, the value is loaded up from super_klass.
955 // No registers are killed, except temp_reg.
956 void check_klass_subtype_fast_path(Register sub_klass,
957 Register super_klass,
958 Register temp_reg,
959 Label* L_success,
960 Label* L_failure,
961 Label* L_slow_path,
962 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
963
964 // The rest of the type check; must be wired to a corresponding fast path.
965 // It does not repeat the fast path logic, so don't use it standalone.
966 // The temp_reg and temp2_reg can be noreg, if no temps are available.
967 // Updates the sub's secondary super cache as necessary.
968 // If set_cond_codes, condition codes will be Z on success, NZ on failure.
969 void check_klass_subtype_slow_path(Register sub_klass,
970 Register super_klass,
971 Register temp_reg,
972 Register temp2_reg,
973 Label* L_success,
974 Label* L_failure,
975 bool set_cond_codes = false);
976
977 // Simplified, combined version, good for typical uses.
978 // Falls through on failure.
979 void check_klass_subtype(Register sub_klass,
980 Register super_klass,
981 Register temp_reg,
982 Label& L_success);
983
984 void clinit_barrier(Register klass,
985 Register thread,
986 Label* L_fast_path = NULL,
987 Label* L_slow_path = NULL);
988
989 Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
990
991 void verify_sve_vector_length(Register tmp = rscratch1);
992 void reinitialize_ptrue() {
993 if (UseSVE > 0) {
994 sve_ptrue(ptrue, B);
995 }
996 }
997 void verify_ptrue();
998
999 // Debugging
1000
1001 // only if +VerifyOops
1002 void _verify_oop(Register reg, const char* s, const char* file, int line);
1003 void _verify_oop_addr(Address addr, const char * s, const char* file, int line);
1004
1005 void _verify_oop_checked(Register reg, const char* s, const char* file, int line) {
1006 if (VerifyOops) {
1007 _verify_oop(reg, s, file, line);
1008 }
1009 }
1010 void _verify_oop_addr_checked(Address reg, const char* s, const char* file, int line) {
1011 if (VerifyOops) {
1012 _verify_oop_addr(reg, s, file, line);
1013 }
1014 }
1015
1016 // TODO: verify method and klass metadata (compare against vptr?)
1017 void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
1018 void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
1019
1020 #define verify_oop(reg) _verify_oop_checked(reg, "broken oop " #reg, __FILE__, __LINE__)
1021 #define verify_oop_msg(reg, msg) _verify_oop_checked(reg, "broken oop " #reg ", " #msg, __FILE__, __LINE__)
1022 #define verify_oop_addr(addr) _verify_oop_addr_checked(addr, "broken oop addr " #addr, __FILE__, __LINE__)
1023 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
1024 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
1025
1026 // only if +VerifyFPU
1027 void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
1028
1029 // prints msg, dumps registers and stops execution
1030 void stop(const char* msg);
1031
1032 static void debug64(char* msg, int64_t pc, int64_t regs[]);
1033
1034 void untested() { stop("untested"); }
1035
1036 void unimplemented(const char* what = "");
1037
1038 void should_not_reach_here() { stop("should not reach here"); }
1039
1040 void _assert_asm(Condition cc, const char* msg);
1041 #define assert_asm0(cc, msg) _assert_asm(cc, FILE_AND_LINE ": " msg)
1042 #define assert_asm(masm, command, cc, msg) DEBUG_ONLY(command; (masm)->_assert_asm(cc, FILE_AND_LINE ": " #command " " #cc ": " msg))
1043
1044 // Stack overflow checking
1045 void bang_stack_with_offset(int offset) {
1046 // stack grows down, caller passes positive offset
1047 assert(offset > 0, "must bang with negative offset");
1048 sub(rscratch2, sp, offset);
1049 str(zr, Address(rscratch2));
1050 }
1051
1052 // Writes to stack successive pages until offset reached to check for
1053 // stack overflow + shadow pages. Also, clobbers tmp
1054 void bang_stack_size(Register size, Register tmp);
1055
1056 // Check for reserved stack access in method being exited (for JIT)
1057 void reserved_stack_check();
1058
1059 // Arithmetics
1060
1061 void addptr(const Address &dst, int32_t src);
1062 void cmpptr(Register src1, Address src2);
1063
1064 void cmpoop(Register obj1, Register obj2);
1065
1066 // Various forms of CAS
1067
1068 void cmpxchg_obj_header(Register oldv, Register newv, Register obj, Register tmp,
1069 Label &succeed, Label *fail);
1070 void cmpxchgptr(Register oldv, Register newv, Register addr, Register tmp,
1071 Label &succeed, Label *fail);
1072
1073 void cmpxchgw(Register oldv, Register newv, Register addr, Register tmp,
1074 Label &succeed, Label *fail);
1075
1076 void atomic_add(Register prev, RegisterOrConstant incr, Register addr);
1077 void atomic_addw(Register prev, RegisterOrConstant incr, Register addr);
1078 void atomic_addal(Register prev, RegisterOrConstant incr, Register addr);
1079 void atomic_addalw(Register prev, RegisterOrConstant incr, Register addr);
1080
1081 void atomic_xchg(Register prev, Register newv, Register addr);
1082 void atomic_xchgw(Register prev, Register newv, Register addr);
1083 void atomic_xchgl(Register prev, Register newv, Register addr);
1084 void atomic_xchglw(Register prev, Register newv, Register addr);
1085 void atomic_xchgal(Register prev, Register newv, Register addr);
1086 void atomic_xchgalw(Register prev, Register newv, Register addr);
1087
1088 void orptr(Address adr, RegisterOrConstant src) {
1089 ldr(rscratch1, adr);
1090 if (src.is_register())
1091 orr(rscratch1, rscratch1, src.as_register());
1092 else
1093 orr(rscratch1, rscratch1, src.as_constant());
1094 str(rscratch1, adr);
1095 }
1096
1097 // A generic CAS; success or failure is in the EQ flag.
1098 // Clobbers rscratch1
1099 void cmpxchg(Register addr, Register expected, Register new_val,
1100 enum operand_size size,
1101 bool acquire, bool release, bool weak,
1102 Register result);
1103
1104 private:
1105 void compare_eq(Register rn, Register rm, enum operand_size size);
1106
1107 #ifdef ASSERT
1108 // Template short-hand support to clean-up after a failed call to trampoline
1109 // call generation (see trampoline_call() below), when a set of Labels must
1110 // be reset (before returning).
1111 template<typename Label, typename... More>
1112 void reset_labels(Label &lbl, More&... more) {
1113 lbl.reset(); reset_labels(more...);
1114 }
1115 template<typename Label>
1116 void reset_labels(Label &lbl) {
1117 lbl.reset();
1118 }
1119 #endif
1120
1121 public:
1122 // AArch64 OpenJDK uses four different types of calls:
1123 // - direct call: bl pc_relative_offset
1124 // This is the shortest and the fastest, but the offset has the range:
1125 // +/-128MB for the release build, +/-2MB for the debug build.
1126 //
1127 // - far call: adrp reg, pc_relative_offset; add; bl reg
1128 // This is longer than a direct call. The offset has
1129 // the range +/-4GB. As the code cache size is limited to 4GB,
1130 // far calls can reach anywhere in the code cache. If a jump is
1131 // needed rather than a call, a far jump 'b reg' can be used instead.
1132 // All instructions are embedded at a call site.
1133 //
1134 // - trampoline call:
1135 // This is only available in C1/C2-generated code (nmethod). It is a combination
1136 // of a direct call, which is used if the destination of a call is in range,
1137 // and a register-indirect call. It has the advantages of reaching anywhere in
1138 // the AArch64 address space and being patchable at runtime when the generated
1139 // code is being executed by other threads.
1140 //
1141 // [Main code section]
1142 // bl trampoline
1143 // [Stub code section]
1144 // trampoline:
1145 // ldr reg, pc + 8
1146 // br reg
1147 // <64-bit destination address>
1148 //
1149 // If the destination is in range when the generated code is moved to the code
1150 // cache, 'bl trampoline' is replaced with 'bl destination' and the trampoline
1151 // is not used.
1152 // The optimization does not remove the trampoline from the stub section.
1153 // This is necessary because the trampoline may well be redirected later when
1154 // code is patched, and the new destination may not be reachable by a simple BR
1155 // instruction.
1156 //
1157 // - indirect call: move reg, address; blr reg
1158 // This too can reach anywhere in the address space, but it cannot be
1159 // patched while code is running, so it must only be modified at a safepoint.
1160 // This form of call is most suitable for targets at fixed addresses, which
1161 // will never be patched.
1162 //
1163 // The patching we do conforms to the "Concurrent modification and
1164 // execution of instructions" section of the Arm Architectural
1165 // Reference Manual, which only allows B, BL, BRK, HVC, ISB, NOP, SMC,
1166 // or SVC instructions to be modified while another thread is
1167 // executing them.
1168 //
1169 // To patch a trampoline call when the BL can't reach, we first modify
1170 // the 64-bit destination address in the trampoline, then modify the
1171 // BL to point to the trampoline, then flush the instruction cache to
1172 // broadcast the change to all executing threads. See
1173 // NativeCall::set_destination_mt_safe for the details.
1174 //
1175 // There is a benign race in that the other thread might observe the
1176 // modified BL before it observes the modified 64-bit destination
1177 // address. That does not matter because the destination method has been
1178 // invalidated, so there will be a trap at its start.
1179 // For this to work, the destination address in the trampoline is
1180 // always updated, even if we're not using the trampoline.
1181
1182 // Emit a direct call if the entry address will always be in range,
1183 // otherwise a trampoline call.
1184 // Supported entry.rspec():
1185 // - relocInfo::runtime_call_type
1186 // - relocInfo::opt_virtual_call_type
1187 // - relocInfo::static_call_type
1188 // - relocInfo::virtual_call_type
1189 //
1190 // Return: the call PC or NULL if CodeCache is full.
1191 address trampoline_call(Address entry);
1192
1193 static bool far_branches() {
1194 return ReservedCodeCacheSize > branch_range;
1195 }
1196
1197 // Check if branches to the the non nmethod section require a far jump
1198 static bool codestub_branch_needs_far_jump() {
1199 return CodeCache::max_distance_to_non_nmethod() > branch_range;
1200 }
1201
1202 // Emit a direct call/jump if the entry address will always be in range,
1203 // otherwise a far call/jump.
1204 // The address must be inside the code cache.
1205 // Supported entry.rspec():
1206 // - relocInfo::external_word_type
1207 // - relocInfo::runtime_call_type
1208 // - relocInfo::none
1209 // In the case of a far call/jump, the entry address is put in the tmp register.
1210 // The tmp register is invalidated.
1211 //
1212 // Far_jump returns the amount of the emitted code.
1213 void far_call(Address entry, Register tmp = rscratch1);
1214 int far_jump(Address entry, Register tmp = rscratch1);
1215
1216 static int far_codestub_branch_size() {
1217 if (codestub_branch_needs_far_jump()) {
1218 return 3 * 4; // adrp, add, br
1219 } else {
1220 return 4;
1221 }
1222 }
1223
1224 // Emit the CompiledIC call idiom
1225 address ic_call(address entry, jint method_index = 0);
1226
1227 public:
1228
1229 // Data
1230
1231 void mov_metadata(Register dst, Metadata* obj);
1232 Address allocate_metadata_address(Metadata* obj);
1233 Address constant_oop_address(jobject obj);
1234
1235 void movoop(Register dst, jobject obj);
1236
1237 // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
1238 void kernel_crc32(Register crc, Register buf, Register len,
1239 Register table0, Register table1, Register table2, Register table3,
1240 Register tmp, Register tmp2, Register tmp3);
1241 // CRC32 code for java.util.zip.CRC32C::updateBytes() intrinsic.
1242 void kernel_crc32c(Register crc, Register buf, Register len,
1243 Register table0, Register table1, Register table2, Register table3,
1244 Register tmp, Register tmp2, Register tmp3);
1245
1246 // Stack push and pop individual 64 bit registers
1247 void push(Register src);
1248 void pop(Register dst);
1249
1250 void repne_scan(Register addr, Register value, Register count,
1251 Register scratch);
1252 void repne_scanw(Register addr, Register value, Register count,
1253 Register scratch);
1254
1255 typedef void (MacroAssembler::* add_sub_imm_insn)(Register Rd, Register Rn, unsigned imm);
1256 typedef void (MacroAssembler::* add_sub_reg_insn)(Register Rd, Register Rn, Register Rm, enum shift_kind kind, unsigned shift);
1257
1258 // If a constant does not fit in an immediate field, generate some
1259 // number of MOV instructions and then perform the operation
1260 void wrap_add_sub_imm_insn(Register Rd, Register Rn, uint64_t imm,
1261 add_sub_imm_insn insn1,
1262 add_sub_reg_insn insn2, bool is32);
1263 // Separate vsn which sets the flags
1264 void wrap_adds_subs_imm_insn(Register Rd, Register Rn, uint64_t imm,
1265 add_sub_imm_insn insn1,
1266 add_sub_reg_insn insn2, bool is32);
1267
1268 #define WRAP(INSN, is32) \
1269 void INSN(Register Rd, Register Rn, uint64_t imm) { \
1270 wrap_add_sub_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN, is32); \
1271 } \
1272 \
1273 void INSN(Register Rd, Register Rn, Register Rm, \
1274 enum shift_kind kind, unsigned shift = 0) { \
1275 Assembler::INSN(Rd, Rn, Rm, kind, shift); \
1276 } \
1277 \
1278 void INSN(Register Rd, Register Rn, Register Rm) { \
1279 Assembler::INSN(Rd, Rn, Rm); \
1280 } \
1281 \
1282 void INSN(Register Rd, Register Rn, Register Rm, \
1283 ext::operation option, int amount = 0) { \
1284 Assembler::INSN(Rd, Rn, Rm, option, amount); \
1285 }
1286
1287 WRAP(add, false) WRAP(addw, true) WRAP(sub, false) WRAP(subw, true)
1288
1289 #undef WRAP
1290 #define WRAP(INSN, is32) \
1291 void INSN(Register Rd, Register Rn, uint64_t imm) { \
1292 wrap_adds_subs_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN, is32); \
1293 } \
1294 \
1295 void INSN(Register Rd, Register Rn, Register Rm, \
1296 enum shift_kind kind, unsigned shift = 0) { \
1297 Assembler::INSN(Rd, Rn, Rm, kind, shift); \
1298 } \
1299 \
1300 void INSN(Register Rd, Register Rn, Register Rm) { \
1301 Assembler::INSN(Rd, Rn, Rm); \
1302 } \
1303 \
1304 void INSN(Register Rd, Register Rn, Register Rm, \
1305 ext::operation option, int amount = 0) { \
1306 Assembler::INSN(Rd, Rn, Rm, option, amount); \
1307 }
1308
1309 WRAP(adds, false) WRAP(addsw, true) WRAP(subs, false) WRAP(subsw, true)
1310
1311 void add(Register Rd, Register Rn, RegisterOrConstant increment);
1312 void addw(Register Rd, Register Rn, RegisterOrConstant increment);
1313 void sub(Register Rd, Register Rn, RegisterOrConstant decrement);
1314 void subw(Register Rd, Register Rn, RegisterOrConstant decrement);
1315
1316 void adrp(Register reg1, const Address &dest, uint64_t &byte_offset);
1317
1318 void tableswitch(Register index, jint lowbound, jint highbound,
1319 Label &jumptable, Label &jumptable_end, int stride = 1) {
1320 adr(rscratch1, jumptable);
1321 subsw(rscratch2, index, lowbound);
1322 subsw(zr, rscratch2, highbound - lowbound);
1323 br(Assembler::HS, jumptable_end);
1324 add(rscratch1, rscratch1, rscratch2,
1325 ext::sxtw, exact_log2(stride * Assembler::instruction_size));
1326 br(rscratch1);
1327 }
1328
1329 // Form an address from base + offset in Rd. Rd may or may not
1330 // actually be used: you must use the Address that is returned. It
1331 // is up to you to ensure that the shift provided matches the size
1332 // of your data.
1333 Address form_address(Register Rd, Register base, int64_t byte_offset, int shift);
1334
1335 // Return true iff an address is within the 48-bit AArch64 address
1336 // space.
1337 bool is_valid_AArch64_address(address a) {
1338 return ((uint64_t)a >> 48) == 0;
1339 }
1340
1341 // Load the base of the cardtable byte map into reg.
1342 void load_byte_map_base(Register reg);
1343
1344 // Prolog generator routines to support switch between x86 code and
1345 // generated ARM code
1346
1347 // routine to generate an x86 prolog for a stub function which
1348 // bootstraps into the generated ARM code which directly follows the
1349 // stub
1350 //
1351
1352 public:
1353
1354 void ldr_constant(Register dest, const Address &const_addr) {
1355 if (NearCpool) {
1356 ldr(dest, const_addr);
1357 } else {
1358 uint64_t offset;
1359 adrp(dest, InternalAddress(const_addr.target()), offset);
1360 ldr(dest, Address(dest, offset));
1361 }
1362 }
1363
1364 address read_polling_page(Register r, relocInfo::relocType rtype);
1365 void get_polling_page(Register dest, relocInfo::relocType rtype);
1366
1367 // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
1368 void update_byte_crc32(Register crc, Register val, Register table);
1369 void update_word_crc32(Register crc, Register v, Register tmp,
1370 Register table0, Register table1, Register table2, Register table3,
1371 bool upper = false);
1372
1373 address count_positives(Register ary1, Register len, Register result);
1374
1375 address arrays_equals(Register a1, Register a2, Register result, Register cnt1,
1376 Register tmp1, Register tmp2, Register tmp3, int elem_size);
1377
1378 void string_equals(Register a1, Register a2, Register result, Register cnt1,
1379 int elem_size);
1380
1381 void fill_words(Register base, Register cnt, Register value);
1382 address zero_words(Register base, uint64_t cnt);
1383 address zero_words(Register ptr, Register cnt);
1384 void zero_dcache_blocks(Register base, Register cnt);
1385
1386 static const int zero_words_block_size;
1387
1388 address byte_array_inflate(Register src, Register dst, Register len,
1389 FloatRegister vtmp1, FloatRegister vtmp2,
1390 FloatRegister vtmp3, Register tmp4);
1391
1392 void char_array_compress(Register src, Register dst, Register len,
1393 Register res,
1394 FloatRegister vtmp0, FloatRegister vtmp1,
1395 FloatRegister vtmp2, FloatRegister vtmp3);
1396
1397 void encode_iso_array(Register src, Register dst,
1398 Register len, Register res, bool ascii,
1399 FloatRegister vtmp0, FloatRegister vtmp1,
1400 FloatRegister vtmp2, FloatRegister vtmp3);
1401
1402 void fast_log(FloatRegister vtmp0, FloatRegister vtmp1, FloatRegister vtmp2,
1403 FloatRegister vtmp3, FloatRegister vtmp4, FloatRegister vtmp5,
1404 FloatRegister tmpC1, FloatRegister tmpC2, FloatRegister tmpC3,
1405 FloatRegister tmpC4, Register tmp1, Register tmp2,
1406 Register tmp3, Register tmp4, Register tmp5);
1407 void generate_dsin_dcos(bool isCos, address npio2_hw, address two_over_pi,
1408 address pio2, address dsin_coef, address dcos_coef);
1409 private:
1410 // begin trigonometric functions support block
1411 void generate__ieee754_rem_pio2(address npio2_hw, address two_over_pi, address pio2);
1412 void generate__kernel_rem_pio2(address two_over_pi, address pio2);
1413 void generate_kernel_sin(FloatRegister x, bool iyIsOne, address dsin_coef);
1414 void generate_kernel_cos(FloatRegister x, address dcos_coef);
1415 // end trigonometric functions support block
1416 void add2_with_carry(Register final_dest_hi, Register dest_hi, Register dest_lo,
1417 Register src1, Register src2);
1418 void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
1419 add2_with_carry(dest_hi, dest_hi, dest_lo, src1, src2);
1420 }
1421 void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
1422 Register y, Register y_idx, Register z,
1423 Register carry, Register product,
1424 Register idx, Register kdx);
1425 void multiply_128_x_128_loop(Register y, Register z,
1426 Register carry, Register carry2,
1427 Register idx, Register jdx,
1428 Register yz_idx1, Register yz_idx2,
1429 Register tmp, Register tmp3, Register tmp4,
1430 Register tmp7, Register product_hi);
1431 void kernel_crc32_using_crc32(Register crc, Register buf,
1432 Register len, Register tmp0, Register tmp1, Register tmp2,
1433 Register tmp3);
1434 void kernel_crc32c_using_crc32c(Register crc, Register buf,
1435 Register len, Register tmp0, Register tmp1, Register tmp2,
1436 Register tmp3);
1437
1438 void ghash_modmul (FloatRegister result,
1439 FloatRegister result_lo, FloatRegister result_hi, FloatRegister b,
1440 FloatRegister a, FloatRegister vzr, FloatRegister a1_xor_a0, FloatRegister p,
1441 FloatRegister t1, FloatRegister t2, FloatRegister t3);
1442 void ghash_load_wide(int index, Register data, FloatRegister result, FloatRegister state);
1443 public:
1444 void multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z,
1445 Register zlen, Register tmp1, Register tmp2, Register tmp3,
1446 Register tmp4, Register tmp5, Register tmp6, Register tmp7);
1447 void mul_add(Register out, Register in, Register offs, Register len, Register k);
1448 void ghash_multiply(FloatRegister result_lo, FloatRegister result_hi,
1449 FloatRegister a, FloatRegister b, FloatRegister a1_xor_a0,
1450 FloatRegister tmp1, FloatRegister tmp2, FloatRegister tmp3);
1451 void ghash_multiply_wide(int index,
1452 FloatRegister result_lo, FloatRegister result_hi,
1453 FloatRegister a, FloatRegister b, FloatRegister a1_xor_a0,
1454 FloatRegister tmp1, FloatRegister tmp2, FloatRegister tmp3);
1455 void ghash_reduce(FloatRegister result, FloatRegister lo, FloatRegister hi,
1456 FloatRegister p, FloatRegister z, FloatRegister t1);
1457 void ghash_reduce_wide(int index, FloatRegister result, FloatRegister lo, FloatRegister hi,
1458 FloatRegister p, FloatRegister z, FloatRegister t1);
1459 void ghash_processBlocks_wide(address p, Register state, Register subkeyH,
1460 Register data, Register blocks, int unrolls);
1461
1462
1463 void aesenc_loadkeys(Register key, Register keylen);
1464 void aesecb_encrypt(Register from, Register to, Register keylen,
1465 FloatRegister data = v0, int unrolls = 1);
1466 void aesecb_decrypt(Register from, Register to, Register key, Register keylen);
1467 void aes_round(FloatRegister input, FloatRegister subkey);
1468
1469 // Place an ISB after code may have been modified due to a safepoint.
1470 void safepoint_isb();
1471
1472 private:
1473 // Return the effective address r + (r1 << ext) + offset.
1474 // Uses rscratch2.
1475 Address offsetted_address(Register r, Register r1, Address::extend ext,
1476 int offset, int size);
1477
1478 private:
1479 // Returns an address on the stack which is reachable with a ldr/str of size
1480 // Uses rscratch2 if the address is not directly reachable
1481 Address spill_address(int size, int offset, Register tmp=rscratch2);
1482 Address sve_spill_address(int sve_reg_size_in_bytes, int offset, Register tmp=rscratch2);
1483
1484 bool merge_alignment_check(Register base, size_t size, int64_t cur_offset, int64_t prev_offset) const;
1485
1486 // Check whether two loads/stores can be merged into ldp/stp.
1487 bool ldst_can_merge(Register rx, const Address &adr, size_t cur_size_in_bytes, bool is_store) const;
1488
1489 // Merge current load/store with previous load/store into ldp/stp.
1490 void merge_ldst(Register rx, const Address &adr, size_t cur_size_in_bytes, bool is_store);
1491
1492 // Try to merge two loads/stores into ldp/stp. If success, returns true else false.
1493 bool try_merge_ldst(Register rt, const Address &adr, size_t cur_size_in_bytes, bool is_store);
1494
1495 public:
1496 void spill(Register Rx, bool is64, int offset) {
1497 if (is64) {
1498 str(Rx, spill_address(8, offset));
1499 } else {
1500 strw(Rx, spill_address(4, offset));
1501 }
1502 }
1503 void spill(FloatRegister Vx, SIMD_RegVariant T, int offset) {
1504 str(Vx, T, spill_address(1 << (int)T, offset));
1505 }
1506
1507 void spill_sve_vector(FloatRegister Zx, int offset, int vector_reg_size_in_bytes) {
1508 sve_str(Zx, sve_spill_address(vector_reg_size_in_bytes, offset));
1509 }
1510 void spill_sve_predicate(PRegister pr, int offset, int predicate_reg_size_in_bytes) {
1511 sve_str(pr, sve_spill_address(predicate_reg_size_in_bytes, offset));
1512 }
1513
1514 void unspill(Register Rx, bool is64, int offset) {
1515 if (is64) {
1516 ldr(Rx, spill_address(8, offset));
1517 } else {
1518 ldrw(Rx, spill_address(4, offset));
1519 }
1520 }
1521 void unspill(FloatRegister Vx, SIMD_RegVariant T, int offset) {
1522 ldr(Vx, T, spill_address(1 << (int)T, offset));
1523 }
1524
1525 void unspill_sve_vector(FloatRegister Zx, int offset, int vector_reg_size_in_bytes) {
1526 sve_ldr(Zx, sve_spill_address(vector_reg_size_in_bytes, offset));
1527 }
1528 void unspill_sve_predicate(PRegister pr, int offset, int predicate_reg_size_in_bytes) {
1529 sve_ldr(pr, sve_spill_address(predicate_reg_size_in_bytes, offset));
1530 }
1531
1532 void spill_copy128(int src_offset, int dst_offset,
1533 Register tmp1=rscratch1, Register tmp2=rscratch2) {
1534 if (src_offset < 512 && (src_offset & 7) == 0 &&
1535 dst_offset < 512 && (dst_offset & 7) == 0) {
1536 ldp(tmp1, tmp2, Address(sp, src_offset));
1537 stp(tmp1, tmp2, Address(sp, dst_offset));
1538 } else {
1539 unspill(tmp1, true, src_offset);
1540 spill(tmp1, true, dst_offset);
1541 unspill(tmp1, true, src_offset+8);
1542 spill(tmp1, true, dst_offset+8);
1543 }
1544 }
1545 void spill_copy_sve_vector_stack_to_stack(int src_offset, int dst_offset,
1546 int sve_vec_reg_size_in_bytes) {
1547 assert(sve_vec_reg_size_in_bytes % 16 == 0, "unexpected sve vector reg size");
1548 for (int i = 0; i < sve_vec_reg_size_in_bytes / 16; i++) {
1549 spill_copy128(src_offset, dst_offset);
1550 src_offset += 16;
1551 dst_offset += 16;
1552 }
1553 }
1554 void spill_copy_sve_predicate_stack_to_stack(int src_offset, int dst_offset,
1555 int sve_predicate_reg_size_in_bytes) {
1556 sve_ldr(ptrue, sve_spill_address(sve_predicate_reg_size_in_bytes, src_offset));
1557 sve_str(ptrue, sve_spill_address(sve_predicate_reg_size_in_bytes, dst_offset));
1558 reinitialize_ptrue();
1559 }
1560 void cache_wb(Address line);
1561 void cache_wbsync(bool is_pre);
1562
1563 // Code for java.lang.Thread::onSpinWait() intrinsic.
1564 void spin_wait();
1565
1566 private:
1567 // Check the current thread doesn't need a cross modify fence.
1568 void verify_cross_modify_fence_not_required() PRODUCT_RETURN;
1569
1570 public:
1571 void fast_lock(Register obj, Register hdr, Register t1, Register t2, Register t3, Label& slow);
1572 void fast_unlock(Register obj, Register hdr, Register t1, Register t2, Label& slow);
1573 };
1574
1575 #ifdef ASSERT
1576 inline bool AbstractAssembler::pd_check_instruction_mark() { return false; }
1577 #endif
1578
1579 /**
1580 * class SkipIfEqual:
1581 *
1582 * Instantiating this class will result in assembly code being output that will
1583 * jump around any code emitted between the creation of the instance and it's
1584 * automatic destruction at the end of a scope block, depending on the value of
1585 * the flag passed to the constructor, which will be checked at run-time.
1586 */
1587 class SkipIfEqual {
1588 private:
1589 MacroAssembler* _masm;
1590 Label _label;
1591
1592 public:
1593 SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
1594 ~SkipIfEqual();
1595 };
1596
1597 struct tableswitch {
1598 Register _reg;
1599 int _insn_index; jint _first_key; jint _last_key;
1600 Label _after;
1601 Label _branches;
1602 };
1603
1604 #endif // CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP