1 /*
2 * Copyright (c) 2008, 2022, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/macroAssembler.inline.hpp"
27 #include "c1/c1_Compilation.hpp"
28 #include "c1/c1_LIRAssembler.hpp"
29 #include "c1/c1_MacroAssembler.hpp"
30 #include "c1/c1_Runtime1.hpp"
31 #include "c1/c1_ValueStack.hpp"
32 #include "ci/ciArrayKlass.hpp"
33 #include "ci/ciInstance.hpp"
34 #include "gc/shared/collectedHeap.hpp"
35 #include "memory/universe.hpp"
36 #include "nativeInst_arm.hpp"
37 #include "oops/objArrayKlass.hpp"
38 #include "runtime/frame.inline.hpp"
39 #include "runtime/sharedRuntime.hpp"
40 #include "runtime/stubRoutines.hpp"
41 #include "utilities/powerOfTwo.hpp"
42 #include "vmreg_arm.inline.hpp"
43
44 #define __ _masm->
45
46 // Note: Rtemp usage is this file should not impact C2 and should be
47 // correct as long as it is not implicitly used in lower layers (the
48 // arm [macro]assembler) and used with care in the other C1 specific
49 // files.
50
51 bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
52 ShouldNotCallThis(); // Not used on ARM
53 return false;
54 }
55
56
57 LIR_Opr LIR_Assembler::receiverOpr() {
58 // The first register in Java calling conventions
59 return FrameMap::R0_oop_opr;
60 }
61
62 LIR_Opr LIR_Assembler::osrBufferPointer() {
63 return FrameMap::as_pointer_opr(R0);
64 }
65
66 #ifndef PRODUCT
67 void LIR_Assembler::verify_reserved_argument_area_size(int args_count) {
68 assert(args_count * wordSize <= frame_map()->reserved_argument_area_size(), "not enough space for arguments");
69 }
70 #endif // !PRODUCT
71
72 void LIR_Assembler::store_parameter(jint c, int offset_from_sp_in_words) {
73 assert(offset_from_sp_in_words >= 0, "invalid offset from sp");
74 int offset_from_sp_in_bytes = offset_from_sp_in_words * BytesPerWord;
75 assert(offset_from_sp_in_bytes < frame_map()->reserved_argument_area_size(), "not enough space");
76 __ mov_slow(Rtemp, c);
77 __ str(Rtemp, Address(SP, offset_from_sp_in_bytes));
78 }
79
80 void LIR_Assembler::store_parameter(Metadata* m, int offset_from_sp_in_words) {
81 assert(offset_from_sp_in_words >= 0, "invalid offset from sp");
82 int offset_from_sp_in_bytes = offset_from_sp_in_words * BytesPerWord;
83 assert(offset_from_sp_in_bytes < frame_map()->reserved_argument_area_size(), "not enough space");
84 __ mov_metadata(Rtemp, m);
85 __ str(Rtemp, Address(SP, offset_from_sp_in_bytes));
86 }
87
88 //--------------fpu register translations-----------------------
89
90
91 void LIR_Assembler::breakpoint() {
92 __ breakpoint();
93 }
94
95 void LIR_Assembler::push(LIR_Opr opr) {
96 Unimplemented();
97 }
98
99 void LIR_Assembler::pop(LIR_Opr opr) {
100 Unimplemented();
101 }
102
103 //-------------------------------------------
104 Address LIR_Assembler::as_Address(LIR_Address* addr) {
105 Register base = addr->base()->as_pointer_register();
106
107
108 if (addr->index()->is_illegal() || addr->index()->is_constant()) {
109 int offset = addr->disp();
110 if (addr->index()->is_constant()) {
111 offset += addr->index()->as_constant_ptr()->as_jint() << addr->scale();
112 }
113
114 if ((offset <= -4096) || (offset >= 4096)) {
115 BAILOUT_("offset not in range", Address(base));
116 }
117
118 return Address(base, offset);
119
120 } else {
121 assert(addr->disp() == 0, "can't have both");
122 int scale = addr->scale();
123
124 assert(addr->index()->is_single_cpu(), "should be");
125 return scale >= 0 ? Address(base, addr->index()->as_register(), lsl, scale) :
126 Address(base, addr->index()->as_register(), lsr, -scale);
127 }
128 }
129
130 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
131 Address base = as_Address(addr);
132 assert(base.index() == noreg, "must be");
133 if (base.disp() + BytesPerWord >= 4096) { BAILOUT_("offset not in range", Address(base.base(),0)); }
134 return Address(base.base(), base.disp() + BytesPerWord);
135 }
136
137 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
138 return as_Address(addr);
139 }
140
141
142 void LIR_Assembler::osr_entry() {
143 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
144 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
145 ValueStack* entry_state = osr_entry->end()->state();
146 int number_of_locks = entry_state->locks_size();
147
148 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
149 Register OSR_buf = osrBufferPointer()->as_pointer_register();
150
151 assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
152 int monitor_offset = (method()->max_locals() + (number_of_locks - 1)) * BytesPerWord;
153 for (int i = 0; i < number_of_locks; i++) {
154 int slot_offset = monitor_offset - (i * BytesPerWord);
155 __ ldr(R1, Address(OSR_buf, slot_offset));
156 __ str(R1, frame_map()->address_for_monitor_object(i));
157 }
158 }
159
160
161 int LIR_Assembler::check_icache() {
162 Register receiver = LIR_Assembler::receiverOpr()->as_register();
163 int offset = __ offset();
164 __ inline_cache_check(receiver, Ricklass);
165 return offset;
166 }
167
168 void LIR_Assembler::clinit_barrier(ciMethod* method) {
169 ShouldNotReachHere(); // not implemented
170 }
171
172 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo* info) {
173 jobject o = (jobject)Universe::non_oop_word();
174 int index = __ oop_recorder()->allocate_oop_index(o);
175
176 PatchingStub* patch = new PatchingStub(_masm, patching_id(info), index);
177
178 __ patchable_mov_oop(reg, o, index);
179 patching_epilog(patch, lir_patch_normal, reg, info);
180 }
181
182
183 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) {
184 Metadata* o = (Metadata*)Universe::non_oop_word();
185 int index = __ oop_recorder()->allocate_metadata_index(o);
186 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id, index);
187
188 __ patchable_mov_metadata(reg, o, index);
189 patching_epilog(patch, lir_patch_normal, reg, info);
190 }
191
192
193 int LIR_Assembler::initial_frame_size_in_bytes() const {
194 // Subtracts two words to account for return address and link
195 return frame_map()->framesize()*VMRegImpl::stack_slot_size - 2*wordSize;
196 }
197
198
199 int LIR_Assembler::emit_exception_handler() {
200 address handler_base = __ start_a_stub(exception_handler_size());
201 if (handler_base == NULL) {
202 bailout("exception handler overflow");
203 return -1;
204 }
205
206 int offset = code_offset();
207
208 // check that there is really an exception
209 __ verify_not_null_oop(Rexception_obj);
210
211 __ call(Runtime1::entry_for(Runtime1::handle_exception_from_callee_id), relocInfo::runtime_call_type);
212 __ should_not_reach_here();
213
214 assert(code_offset() - offset <= exception_handler_size(), "overflow");
215 __ end_a_stub();
216
217 return offset;
218 }
219
220 // Emit the code to remove the frame from the stack in the exception
221 // unwind path.
222 int LIR_Assembler::emit_unwind_handler() {
223 #ifndef PRODUCT
224 if (CommentedAssembly) {
225 _masm->block_comment("Unwind handler");
226 }
227 #endif
228
229 int offset = code_offset();
230
231 // Fetch the exception from TLS and clear out exception related thread state
232 Register zero = __ zero_register(Rtemp);
233 __ ldr(Rexception_obj, Address(Rthread, JavaThread::exception_oop_offset()));
234 __ str(zero, Address(Rthread, JavaThread::exception_oop_offset()));
235 __ str(zero, Address(Rthread, JavaThread::exception_pc_offset()));
236
237 __ bind(_unwind_handler_entry);
238 __ verify_not_null_oop(Rexception_obj);
239
240 // Perform needed unlocking
241 MonitorExitStub* stub = NULL;
242 if (method()->is_synchronized()) {
243 monitor_address(0, FrameMap::R0_opr);
244 __ ldr(R1, Address(R0, BasicObjectLock::obj_offset_in_bytes()));
245 stub = new MonitorExitStub(FrameMap::R1_opr);
246 __ b(*stub->entry());
247 __ bind(*stub->continuation());
248 }
249
250 // remove the activation and dispatch to the unwind handler
251 __ remove_frame(initial_frame_size_in_bytes()); // restores FP and LR
252 __ jump(Runtime1::entry_for(Runtime1::unwind_exception_id), relocInfo::runtime_call_type, Rtemp);
253
254 // Emit the slow path assembly
255 if (stub != NULL) {
256 stub->emit_code(this);
257 }
258
259 return offset;
260 }
261
262
263 int LIR_Assembler::emit_deopt_handler() {
264 address handler_base = __ start_a_stub(deopt_handler_size());
265 if (handler_base == NULL) {
266 bailout("deopt handler overflow");
267 return -1;
268 }
269
270 int offset = code_offset();
271
272 __ mov_relative_address(LR, __ pc());
273 __ push(LR); // stub expects LR to be saved
274 __ jump(SharedRuntime::deopt_blob()->unpack(), relocInfo::runtime_call_type, noreg);
275
276 assert(code_offset() - offset <= deopt_handler_size(), "overflow");
277 __ end_a_stub();
278
279 return offset;
280 }
281
282
283 void LIR_Assembler::return_op(LIR_Opr result, C1SafepointPollStub* code_stub) {
284 // Pop the frame before safepoint polling
285 __ remove_frame(initial_frame_size_in_bytes());
286 __ read_polling_page(Rtemp, relocInfo::poll_return_type);
287 __ ret();
288 }
289
290 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
291
292 int offset = __ offset();
293 __ get_polling_page(Rtemp);
294 __ relocate(relocInfo::poll_type);
295 add_debug_info_for_branch(info); // help pc_desc_at to find correct scope for current PC
296 __ ldr(Rtemp, Address(Rtemp));
297
298 return offset;
299 }
300
301
302 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
303 if (from_reg != to_reg) {
304 __ mov(to_reg, from_reg);
305 }
306 }
307
308 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
309 assert(src->is_constant() && dest->is_register(), "must be");
310 LIR_Const* c = src->as_constant_ptr();
311
312 switch (c->type()) {
313 case T_ADDRESS:
314 case T_INT:
315 assert(patch_code == lir_patch_none, "no patching handled here");
316 __ mov_slow(dest->as_register(), c->as_jint());
317 break;
318
319 case T_LONG:
320 assert(patch_code == lir_patch_none, "no patching handled here");
321 __ mov_slow(dest->as_register_lo(), c->as_jint_lo());
322 __ mov_slow(dest->as_register_hi(), c->as_jint_hi());
323 break;
324
325 case T_OBJECT:
326 if (patch_code == lir_patch_none) {
327 __ mov_oop(dest->as_register(), c->as_jobject());
328 } else {
329 jobject2reg_with_patching(dest->as_register(), info);
330 }
331 break;
332
333 case T_METADATA:
334 if (patch_code == lir_patch_none) {
335 __ mov_metadata(dest->as_register(), c->as_metadata());
336 } else {
337 klass2reg_with_patching(dest->as_register(), info);
338 }
339 break;
340
341 case T_FLOAT:
342 if (dest->is_single_fpu()) {
343 __ mov_float(dest->as_float_reg(), c->as_jfloat());
344 } else {
345 // Simple getters can return float constant directly into r0
346 __ mov_slow(dest->as_register(), c->as_jint_bits());
347 }
348 break;
349
350 case T_DOUBLE:
351 if (dest->is_double_fpu()) {
352 __ mov_double(dest->as_double_reg(), c->as_jdouble());
353 } else {
354 // Simple getters can return double constant directly into r1r0
355 __ mov_slow(dest->as_register_lo(), c->as_jint_lo_bits());
356 __ mov_slow(dest->as_register_hi(), c->as_jint_hi_bits());
357 }
358 break;
359
360 default:
361 ShouldNotReachHere();
362 }
363 }
364
365 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
366 assert(src->is_constant(), "must be");
367 assert(dest->is_stack(), "must be");
368 LIR_Const* c = src->as_constant_ptr();
369
370 switch (c->type()) {
371 case T_INT: // fall through
372 case T_FLOAT:
373 __ mov_slow(Rtemp, c->as_jint_bits());
374 __ str_32(Rtemp, frame_map()->address_for_slot(dest->single_stack_ix()));
375 break;
376
377 case T_ADDRESS:
378 __ mov_slow(Rtemp, c->as_jint());
379 __ str(Rtemp, frame_map()->address_for_slot(dest->single_stack_ix()));
380 break;
381
382 case T_OBJECT:
383 __ mov_oop(Rtemp, c->as_jobject());
384 __ str(Rtemp, frame_map()->address_for_slot(dest->single_stack_ix()));
385 break;
386
387 case T_LONG: // fall through
388 case T_DOUBLE:
389 __ mov_slow(Rtemp, c->as_jint_lo_bits());
390 __ str(Rtemp, frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes));
391 if (c->as_jint_hi_bits() != c->as_jint_lo_bits()) {
392 __ mov_slow(Rtemp, c->as_jint_hi_bits());
393 }
394 __ str(Rtemp, frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes));
395 break;
396
397 default:
398 ShouldNotReachHere();
399 }
400 }
401
402 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type,
403 CodeEmitInfo* info, bool wide) {
404 assert((src->as_constant_ptr()->type() == T_OBJECT && src->as_constant_ptr()->as_jobject() == NULL),"cannot handle otherwise");
405 __ mov(Rtemp, 0);
406
407 int null_check_offset = code_offset();
408 __ str(Rtemp, as_Address(dest->as_address_ptr()));
409
410 if (info != NULL) {
411 assert(false, "arm32 didn't support this before, investigate if bug");
412 add_debug_info_for_null_check(null_check_offset, info);
413 }
414 }
415
416 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
417 assert(src->is_register() && dest->is_register(), "must be");
418
419 if (src->is_single_cpu()) {
420 if (dest->is_single_cpu()) {
421 move_regs(src->as_register(), dest->as_register());
422 } else if (dest->is_single_fpu()) {
423 __ fmsr(dest->as_float_reg(), src->as_register());
424 } else {
425 ShouldNotReachHere();
426 }
427 } else if (src->is_double_cpu()) {
428 if (dest->is_double_cpu()) {
429 __ long_move(dest->as_register_lo(), dest->as_register_hi(), src->as_register_lo(), src->as_register_hi());
430 } else {
431 __ fmdrr(dest->as_double_reg(), src->as_register_lo(), src->as_register_hi());
432 }
433 } else if (src->is_single_fpu()) {
434 if (dest->is_single_fpu()) {
435 __ mov_float(dest->as_float_reg(), src->as_float_reg());
436 } else if (dest->is_single_cpu()) {
437 __ mov_fpr2gpr_float(dest->as_register(), src->as_float_reg());
438 } else {
439 ShouldNotReachHere();
440 }
441 } else if (src->is_double_fpu()) {
442 if (dest->is_double_fpu()) {
443 __ mov_double(dest->as_double_reg(), src->as_double_reg());
444 } else if (dest->is_double_cpu()) {
445 __ fmrrd(dest->as_register_lo(), dest->as_register_hi(), src->as_double_reg());
446 } else {
447 ShouldNotReachHere();
448 }
449 } else {
450 ShouldNotReachHere();
451 }
452 }
453
454 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
455 assert(src->is_register(), "should not call otherwise");
456 assert(dest->is_stack(), "should not call otherwise");
457
458 Address addr = dest->is_single_word() ?
459 frame_map()->address_for_slot(dest->single_stack_ix()) :
460 frame_map()->address_for_slot(dest->double_stack_ix());
461
462 assert(lo_word_offset_in_bytes == 0 && hi_word_offset_in_bytes == 4, "little ending");
463 if (src->is_single_fpu() || src->is_double_fpu()) {
464 if (addr.disp() >= 1024) { BAILOUT("Too exotic case to handle here"); }
465 }
466
467 if (src->is_single_cpu()) {
468 switch (type) {
469 case T_OBJECT:
470 case T_ARRAY: __ verify_oop(src->as_register()); // fall through
471 case T_ADDRESS:
472 case T_METADATA: __ str(src->as_register(), addr); break;
473 case T_FLOAT: // used in intBitsToFloat intrinsic implementation, fall through
474 case T_INT: __ str_32(src->as_register(), addr); break;
475 default:
476 ShouldNotReachHere();
477 }
478 } else if (src->is_double_cpu()) {
479 __ str(src->as_register_lo(), addr);
480 __ str(src->as_register_hi(), frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes));
481 } else if (src->is_single_fpu()) {
482 __ str_float(src->as_float_reg(), addr);
483 } else if (src->is_double_fpu()) {
484 __ str_double(src->as_double_reg(), addr);
485 } else {
486 ShouldNotReachHere();
487 }
488 }
489
490
491 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type,
492 LIR_PatchCode patch_code, CodeEmitInfo* info,
493 bool pop_fpu_stack, bool wide) {
494 LIR_Address* to_addr = dest->as_address_ptr();
495 Register base_reg = to_addr->base()->as_pointer_register();
496 const bool needs_patching = (patch_code != lir_patch_none);
497
498 PatchingStub* patch = NULL;
499 if (needs_patching) {
500 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
501 }
502
503 int null_check_offset = code_offset();
504
505 switch (type) {
506 case T_ARRAY:
507 case T_OBJECT:
508 if (UseCompressedOops && !wide) {
509 ShouldNotReachHere();
510 } else {
511 __ str(src->as_register(), as_Address(to_addr));
512 }
513 break;
514
515 case T_ADDRESS:
516 __ str(src->as_pointer_register(), as_Address(to_addr));
517 break;
518
519 case T_BYTE:
520 case T_BOOLEAN:
521 __ strb(src->as_register(), as_Address(to_addr));
522 break;
523
524 case T_CHAR:
525 case T_SHORT:
526 __ strh(src->as_register(), as_Address(to_addr));
527 break;
528
529 case T_INT:
530 #ifdef __SOFTFP__
531 case T_FLOAT:
532 #endif // __SOFTFP__
533 __ str_32(src->as_register(), as_Address(to_addr));
534 break;
535
536
537 #ifdef __SOFTFP__
538 case T_DOUBLE:
539 #endif // __SOFTFP__
540 case T_LONG: {
541 Register from_lo = src->as_register_lo();
542 Register from_hi = src->as_register_hi();
543 if (to_addr->index()->is_register()) {
544 assert(to_addr->scale() == LIR_Address::times_1,"Unexpected scaled register");
545 assert(to_addr->disp() == 0, "Not yet supporting both");
546 __ add(Rtemp, base_reg, to_addr->index()->as_register());
547 base_reg = Rtemp;
548 __ str(from_lo, Address(Rtemp));
549 if (patch != NULL) {
550 __ nop(); // see comment before patching_epilog for 2nd str
551 patching_epilog(patch, lir_patch_low, base_reg, info);
552 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
553 patch_code = lir_patch_high;
554 }
555 __ str(from_hi, Address(Rtemp, BytesPerWord));
556 } else if (base_reg == from_lo) {
557 __ str(from_hi, as_Address_hi(to_addr));
558 if (patch != NULL) {
559 __ nop(); // see comment before patching_epilog for 2nd str
560 patching_epilog(patch, lir_patch_high, base_reg, info);
561 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
562 patch_code = lir_patch_low;
563 }
564 __ str(from_lo, as_Address_lo(to_addr));
565 } else {
566 __ str(from_lo, as_Address_lo(to_addr));
567 if (patch != NULL) {
568 __ nop(); // see comment before patching_epilog for 2nd str
569 patching_epilog(patch, lir_patch_low, base_reg, info);
570 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
571 patch_code = lir_patch_high;
572 }
573 __ str(from_hi, as_Address_hi(to_addr));
574 }
575 break;
576 }
577
578 #ifndef __SOFTFP__
579 case T_FLOAT:
580 if (to_addr->index()->is_register()) {
581 assert(to_addr->scale() == LIR_Address::times_1,"Unexpected scaled register");
582 __ add(Rtemp, base_reg, to_addr->index()->as_register());
583 if ((to_addr->disp() <= -4096) || (to_addr->disp() >= 4096)) { BAILOUT("offset not in range"); }
584 __ fsts(src->as_float_reg(), Address(Rtemp, to_addr->disp()));
585 } else {
586 __ fsts(src->as_float_reg(), as_Address(to_addr));
587 }
588 break;
589
590 case T_DOUBLE:
591 if (to_addr->index()->is_register()) {
592 assert(to_addr->scale() == LIR_Address::times_1,"Unexpected scaled register");
593 __ add(Rtemp, base_reg, to_addr->index()->as_register());
594 if ((to_addr->disp() <= -4096) || (to_addr->disp() >= 4096)) { BAILOUT("offset not in range"); }
595 __ fstd(src->as_double_reg(), Address(Rtemp, to_addr->disp()));
596 } else {
597 __ fstd(src->as_double_reg(), as_Address(to_addr));
598 }
599 break;
600 #endif // __SOFTFP__
601
602
603 default:
604 ShouldNotReachHere();
605 }
606
607 if (info != NULL) {
608 add_debug_info_for_null_check(null_check_offset, info);
609 }
610
611 if (patch != NULL) {
612 // Offset embedded into LDR/STR instruction may appear not enough
613 // to address a field. So, provide a space for one more instruction
614 // that will deal with larger offsets.
615 __ nop();
616 patching_epilog(patch, patch_code, base_reg, info);
617 }
618 }
619
620
621 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
622 assert(src->is_stack(), "should not call otherwise");
623 assert(dest->is_register(), "should not call otherwise");
624
625 Address addr = src->is_single_word() ?
626 frame_map()->address_for_slot(src->single_stack_ix()) :
627 frame_map()->address_for_slot(src->double_stack_ix());
628
629 assert(lo_word_offset_in_bytes == 0 && hi_word_offset_in_bytes == 4, "little ending");
630 if (dest->is_single_fpu() || dest->is_double_fpu()) {
631 if (addr.disp() >= 1024) { BAILOUT("Too exotic case to handle here"); }
632 }
633
634 if (dest->is_single_cpu()) {
635 switch (type) {
636 case T_OBJECT:
637 case T_ARRAY:
638 case T_ADDRESS:
639 case T_METADATA: __ ldr(dest->as_register(), addr); break;
640 case T_FLOAT: // used in floatToRawIntBits intrinsic implementation
641 case T_INT: __ ldr_u32(dest->as_register(), addr); break;
642 default:
643 ShouldNotReachHere();
644 }
645 if ((type == T_OBJECT) || (type == T_ARRAY)) {
646 __ verify_oop(dest->as_register());
647 }
648 } else if (dest->is_double_cpu()) {
649 __ ldr(dest->as_register_lo(), addr);
650 __ ldr(dest->as_register_hi(), frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes));
651 } else if (dest->is_single_fpu()) {
652 __ ldr_float(dest->as_float_reg(), addr);
653 } else if (dest->is_double_fpu()) {
654 __ ldr_double(dest->as_double_reg(), addr);
655 } else {
656 ShouldNotReachHere();
657 }
658 }
659
660
661 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
662 if (src->is_single_stack()) {
663 switch (src->type()) {
664 case T_OBJECT:
665 case T_ARRAY:
666 case T_ADDRESS:
667 case T_METADATA:
668 __ ldr(Rtemp, frame_map()->address_for_slot(src->single_stack_ix()));
669 __ str(Rtemp, frame_map()->address_for_slot(dest->single_stack_ix()));
670 break;
671
672 case T_INT:
673 case T_FLOAT:
674 __ ldr_u32(Rtemp, frame_map()->address_for_slot(src->single_stack_ix()));
675 __ str_32(Rtemp, frame_map()->address_for_slot(dest->single_stack_ix()));
676 break;
677
678 default:
679 ShouldNotReachHere();
680 }
681 } else {
682 assert(src->is_double_stack(), "must be");
683 __ ldr(Rtemp, frame_map()->address_for_slot(src->double_stack_ix(), lo_word_offset_in_bytes));
684 __ str(Rtemp, frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes));
685 __ ldr(Rtemp, frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes));
686 __ str(Rtemp, frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes));
687 }
688 }
689
690
691 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type,
692 LIR_PatchCode patch_code, CodeEmitInfo* info,
693 bool wide) {
694 assert(src->is_address(), "should not call otherwise");
695 assert(dest->is_register(), "should not call otherwise");
696 LIR_Address* addr = src->as_address_ptr();
697
698 Register base_reg = addr->base()->as_pointer_register();
699
700 PatchingStub* patch = NULL;
701 if (patch_code != lir_patch_none) {
702 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
703 }
704 if (info != NULL) {
705 add_debug_info_for_null_check_here(info);
706 }
707
708 switch (type) {
709 case T_OBJECT: // fall through
710 case T_ARRAY:
711 if (UseCompressedOops && !wide) {
712 __ ldr_u32(dest->as_register(), as_Address(addr));
713 } else {
714 __ ldr(dest->as_register(), as_Address(addr));
715 }
716 break;
717
718 case T_ADDRESS:
719 __ ldr(dest->as_pointer_register(), as_Address(addr));
720 break;
721
722 case T_INT:
723 #ifdef __SOFTFP__
724 case T_FLOAT:
725 #endif // __SOFTFP__
726 __ ldr(dest->as_pointer_register(), as_Address(addr));
727 break;
728
729 case T_BOOLEAN:
730 __ ldrb(dest->as_register(), as_Address(addr));
731 break;
732
733 case T_BYTE:
734 __ ldrsb(dest->as_register(), as_Address(addr));
735 break;
736
737 case T_CHAR:
738 __ ldrh(dest->as_register(), as_Address(addr));
739 break;
740
741 case T_SHORT:
742 __ ldrsh(dest->as_register(), as_Address(addr));
743 break;
744
745
746 #ifdef __SOFTFP__
747 case T_DOUBLE:
748 #endif // __SOFTFP__
749 case T_LONG: {
750 Register to_lo = dest->as_register_lo();
751 Register to_hi = dest->as_register_hi();
752 if (addr->index()->is_register()) {
753 assert(addr->scale() == LIR_Address::times_1,"Unexpected scaled register");
754 assert(addr->disp() == 0, "Not yet supporting both");
755 __ add(Rtemp, base_reg, addr->index()->as_register());
756 base_reg = Rtemp;
757 __ ldr(to_lo, Address(Rtemp));
758 if (patch != NULL) {
759 __ nop(); // see comment before patching_epilog for 2nd ldr
760 patching_epilog(patch, lir_patch_low, base_reg, info);
761 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
762 patch_code = lir_patch_high;
763 }
764 __ ldr(to_hi, Address(Rtemp, BytesPerWord));
765 } else if (base_reg == to_lo) {
766 __ ldr(to_hi, as_Address_hi(addr));
767 if (patch != NULL) {
768 __ nop(); // see comment before patching_epilog for 2nd ldr
769 patching_epilog(patch, lir_patch_high, base_reg, info);
770 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
771 patch_code = lir_patch_low;
772 }
773 __ ldr(to_lo, as_Address_lo(addr));
774 } else {
775 __ ldr(to_lo, as_Address_lo(addr));
776 if (patch != NULL) {
777 __ nop(); // see comment before patching_epilog for 2nd ldr
778 patching_epilog(patch, lir_patch_low, base_reg, info);
779 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
780 patch_code = lir_patch_high;
781 }
782 __ ldr(to_hi, as_Address_hi(addr));
783 }
784 break;
785 }
786
787 #ifndef __SOFTFP__
788 case T_FLOAT:
789 if (addr->index()->is_register()) {
790 assert(addr->scale() == LIR_Address::times_1,"Unexpected scaled register");
791 __ add(Rtemp, base_reg, addr->index()->as_register());
792 if ((addr->disp() <= -4096) || (addr->disp() >= 4096)) { BAILOUT("offset not in range"); }
793 __ flds(dest->as_float_reg(), Address(Rtemp, addr->disp()));
794 } else {
795 __ flds(dest->as_float_reg(), as_Address(addr));
796 }
797 break;
798
799 case T_DOUBLE:
800 if (addr->index()->is_register()) {
801 assert(addr->scale() == LIR_Address::times_1,"Unexpected scaled register");
802 __ add(Rtemp, base_reg, addr->index()->as_register());
803 if ((addr->disp() <= -4096) || (addr->disp() >= 4096)) { BAILOUT("offset not in range"); }
804 __ fldd(dest->as_double_reg(), Address(Rtemp, addr->disp()));
805 } else {
806 __ fldd(dest->as_double_reg(), as_Address(addr));
807 }
808 break;
809 #endif // __SOFTFP__
810
811
812 default:
813 ShouldNotReachHere();
814 }
815
816 if (patch != NULL) {
817 // Offset embedded into LDR/STR instruction may appear not enough
818 // to address a field. So, provide a space for one more instruction
819 // that will deal with larger offsets.
820 __ nop();
821 patching_epilog(patch, patch_code, base_reg, info);
822 }
823
824 }
825
826
827 void LIR_Assembler::emit_op3(LIR_Op3* op) {
828 bool is_32 = op->result_opr()->is_single_cpu();
829
830 if (op->code() == lir_idiv && op->in_opr2()->is_constant() && is_32) {
831 int c = op->in_opr2()->as_constant_ptr()->as_jint();
832 assert(is_power_of_2(c), "non power-of-2 constant should be put in a register");
833
834 Register left = op->in_opr1()->as_register();
835 Register dest = op->result_opr()->as_register();
836 if (c == 1) {
837 __ mov(dest, left);
838 } else if (c == 2) {
839 __ add_32(dest, left, AsmOperand(left, lsr, 31));
840 __ asr_32(dest, dest, 1);
841 } else if (c != (int) 0x80000000) {
842 int power = log2i_exact(c);
843 __ asr_32(Rtemp, left, 31);
844 __ add_32(dest, left, AsmOperand(Rtemp, lsr, 32-power)); // dest = left + (left < 0 ? 2^power - 1 : 0);
845 __ asr_32(dest, dest, power); // dest = dest >>> power;
846 } else {
847 // x/0x80000000 is a special case, since dividend is a power of two, but is negative.
848 // The only possible result values are 0 and 1, with 1 only for dividend == divisor == 0x80000000.
849 __ cmp_32(left, c);
850 __ mov(dest, 0, ne);
851 __ mov(dest, 1, eq);
852 }
853 } else {
854 assert(op->code() == lir_idiv || op->code() == lir_irem, "unexpected op3");
855 __ call(StubRoutines::Arm::idiv_irem_entry(), relocInfo::runtime_call_type);
856 add_debug_info_for_div0_here(op->info());
857 }
858 }
859
860
861 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
862 #ifdef ASSERT
863 assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label");
864 if (op->block() != NULL) _branch_target_blocks.append(op->block());
865 if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock());
866 assert(op->info() == NULL, "CodeEmitInfo?");
867 #endif // ASSERT
868
869 #ifdef __SOFTFP__
870 assert (op->code() != lir_cond_float_branch, "this should be impossible");
871 #else
872 if (op->code() == lir_cond_float_branch) {
873 __ fmstat();
874 __ b(*(op->ublock()->label()), vs);
875 }
876 #endif // __SOFTFP__
877
878 AsmCondition acond = al;
879 switch (op->cond()) {
880 case lir_cond_equal: acond = eq; break;
881 case lir_cond_notEqual: acond = ne; break;
882 case lir_cond_less: acond = lt; break;
883 case lir_cond_lessEqual: acond = le; break;
884 case lir_cond_greaterEqual: acond = ge; break;
885 case lir_cond_greater: acond = gt; break;
886 case lir_cond_aboveEqual: acond = hs; break;
887 case lir_cond_belowEqual: acond = ls; break;
888 default: assert(op->cond() == lir_cond_always, "must be");
889 }
890 __ b(*(op->label()), acond);
891 }
892
893
894 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
895 LIR_Opr src = op->in_opr();
896 LIR_Opr dest = op->result_opr();
897
898 switch (op->bytecode()) {
899 case Bytecodes::_i2l:
900 move_regs(src->as_register(), dest->as_register_lo());
901 __ mov(dest->as_register_hi(), AsmOperand(src->as_register(), asr, 31));
902 break;
903 case Bytecodes::_l2i:
904 move_regs(src->as_register_lo(), dest->as_register());
905 break;
906 case Bytecodes::_i2b:
907 __ sign_extend(dest->as_register(), src->as_register(), 8);
908 break;
909 case Bytecodes::_i2s:
910 __ sign_extend(dest->as_register(), src->as_register(), 16);
911 break;
912 case Bytecodes::_i2c:
913 __ zero_extend(dest->as_register(), src->as_register(), 16);
914 break;
915 case Bytecodes::_f2d:
916 __ convert_f2d(dest->as_double_reg(), src->as_float_reg());
917 break;
918 case Bytecodes::_d2f:
919 __ convert_d2f(dest->as_float_reg(), src->as_double_reg());
920 break;
921 case Bytecodes::_i2f:
922 __ fmsr(Stemp, src->as_register());
923 __ fsitos(dest->as_float_reg(), Stemp);
924 break;
925 case Bytecodes::_i2d:
926 __ fmsr(Stemp, src->as_register());
927 __ fsitod(dest->as_double_reg(), Stemp);
928 break;
929 case Bytecodes::_f2i:
930 __ ftosizs(Stemp, src->as_float_reg());
931 __ fmrs(dest->as_register(), Stemp);
932 break;
933 case Bytecodes::_d2i:
934 __ ftosizd(Stemp, src->as_double_reg());
935 __ fmrs(dest->as_register(), Stemp);
936 break;
937 default:
938 ShouldNotReachHere();
939 }
940 }
941
942
943 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
944 if (op->init_check()) {
945 Register tmp = op->tmp1()->as_register();
946 __ ldrb(tmp, Address(op->klass()->as_register(), InstanceKlass::init_state_offset()));
947 add_debug_info_for_null_check_here(op->stub()->info());
948 __ cmp(tmp, InstanceKlass::fully_initialized);
949 __ b(*op->stub()->entry(), ne);
950 }
951 __ allocate_object(op->obj()->as_register(),
952 op->tmp1()->as_register(),
953 op->tmp2()->as_register(),
954 op->tmp3()->as_register(),
955 op->header_size(),
956 op->object_size(),
957 op->klass()->as_register(),
958 *op->stub()->entry());
959 __ bind(*op->stub()->continuation());
960 }
961
962 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
963 if (UseSlowPath ||
964 (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) ||
965 (!UseFastNewTypeArray && (op->type() != T_OBJECT && op->type() != T_ARRAY))) {
966 __ b(*op->stub()->entry());
967 } else {
968 __ allocate_array(op->obj()->as_register(),
969 op->len()->as_register(),
970 op->tmp1()->as_register(),
971 op->tmp2()->as_register(),
972 op->tmp3()->as_register(),
973 arrayOopDesc::base_offset_in_bytes(op->type()),
974 type2aelembytes(op->type()),
975 op->klass()->as_register(),
976 *op->stub()->entry());
977 }
978 __ bind(*op->stub()->continuation());
979 }
980
981 void LIR_Assembler::type_profile_helper(Register mdo, int mdo_offset_bias,
982 ciMethodData *md, ciProfileData *data,
983 Register recv, Register tmp1, Label* update_done) {
984 assert_different_registers(mdo, recv, tmp1);
985 uint i;
986 for (i = 0; i < VirtualCallData::row_limit(); i++) {
987 Label next_test;
988 // See if the receiver is receiver[n].
989 Address receiver_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) -
990 mdo_offset_bias);
991 __ ldr(tmp1, receiver_addr);
992 __ verify_klass_ptr(tmp1);
993 __ cmp(recv, tmp1);
994 __ b(next_test, ne);
995 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) -
996 mdo_offset_bias);
997 __ ldr(tmp1, data_addr);
998 __ add(tmp1, tmp1, DataLayout::counter_increment);
999 __ str(tmp1, data_addr);
1000 __ b(*update_done);
1001 __ bind(next_test);
1002 }
1003
1004 // Didn't find receiver; find next empty slot and fill it in
1005 for (i = 0; i < VirtualCallData::row_limit(); i++) {
1006 Label next_test;
1007 Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) -
1008 mdo_offset_bias);
1009 __ ldr(tmp1, recv_addr);
1010 __ cbnz(tmp1, next_test);
1011 __ str(recv, recv_addr);
1012 __ mov(tmp1, DataLayout::counter_increment);
1013 __ str(tmp1, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) -
1014 mdo_offset_bias));
1015 __ b(*update_done);
1016 __ bind(next_test);
1017 }
1018 }
1019
1020 void LIR_Assembler::setup_md_access(ciMethod* method, int bci,
1021 ciMethodData*& md, ciProfileData*& data, int& mdo_offset_bias) {
1022 md = method->method_data_or_null();
1023 assert(md != NULL, "Sanity");
1024 data = md->bci_to_data(bci);
1025 assert(data != NULL, "need data for checkcast");
1026 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1027 if (md->byte_offset_of_slot(data, DataLayout::header_offset()) + data->size_in_bytes() >= 4096) {
1028 // The offset is large so bias the mdo by the base of the slot so
1029 // that the ldr can use an immediate offset to reference the slots of the data
1030 mdo_offset_bias = md->byte_offset_of_slot(data, DataLayout::header_offset());
1031 }
1032 }
1033
1034 // On 32-bit ARM, code before this helper should test obj for null (ZF should be set if obj is null).
1035 void LIR_Assembler::typecheck_profile_helper1(ciMethod* method, int bci,
1036 ciMethodData*& md, ciProfileData*& data, int& mdo_offset_bias,
1037 Register obj, Register mdo, Register data_val, Label* obj_is_null) {
1038 assert(method != NULL, "Should have method");
1039 assert_different_registers(obj, mdo, data_val);
1040 setup_md_access(method, bci, md, data, mdo_offset_bias);
1041 Label not_null;
1042 __ b(not_null, ne);
1043 __ mov_metadata(mdo, md->constant_encoding());
1044 if (mdo_offset_bias > 0) {
1045 __ mov_slow(data_val, mdo_offset_bias);
1046 __ add(mdo, mdo, data_val);
1047 }
1048 Address flags_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias);
1049 __ ldrb(data_val, flags_addr);
1050 __ orr(data_val, data_val, (uint)BitData::null_seen_byte_constant());
1051 __ strb(data_val, flags_addr);
1052 __ b(*obj_is_null);
1053 __ bind(not_null);
1054 }
1055
1056 void LIR_Assembler::typecheck_profile_helper2(ciMethodData* md, ciProfileData* data, int mdo_offset_bias,
1057 Register mdo, Register recv, Register value, Register tmp1,
1058 Label* profile_cast_success, Label* profile_cast_failure,
1059 Label* success, Label* failure) {
1060 assert_different_registers(mdo, value, tmp1);
1061 __ bind(*profile_cast_success);
1062 __ mov_metadata(mdo, md->constant_encoding());
1063 if (mdo_offset_bias > 0) {
1064 __ mov_slow(tmp1, mdo_offset_bias);
1065 __ add(mdo, mdo, tmp1);
1066 }
1067 __ load_klass(recv, value);
1068 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, success);
1069 __ b(*success);
1070 // Cast failure case
1071 __ bind(*profile_cast_failure);
1072 __ mov_metadata(mdo, md->constant_encoding());
1073 if (mdo_offset_bias > 0) {
1074 __ mov_slow(tmp1, mdo_offset_bias);
1075 __ add(mdo, mdo, tmp1);
1076 }
1077 Address data_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias);
1078 __ ldr(tmp1, data_addr);
1079 __ sub(tmp1, tmp1, DataLayout::counter_increment);
1080 __ str(tmp1, data_addr);
1081 __ b(*failure);
1082 }
1083
1084 // Sets `res` to true, if `cond` holds.
1085 static void set_instanceof_result(MacroAssembler* _masm, Register res, AsmCondition cond) {
1086 __ mov(res, 1, cond);
1087 }
1088
1089
1090 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
1091 // TODO: ARM - can be more effective with one more register
1092 switch (op->code()) {
1093 case lir_store_check: {
1094 CodeStub* stub = op->stub();
1095 Register value = op->object()->as_register();
1096 Register array = op->array()->as_register();
1097 Register klass_RInfo = op->tmp1()->as_register();
1098 Register k_RInfo = op->tmp2()->as_register();
1099 assert_different_registers(klass_RInfo, k_RInfo, Rtemp);
1100 if (op->should_profile()) {
1101 assert_different_registers(value, klass_RInfo, k_RInfo, Rtemp);
1102 }
1103
1104 // check if it needs to be profiled
1105 ciMethodData* md;
1106 ciProfileData* data;
1107 int mdo_offset_bias = 0;
1108 Label profile_cast_success, profile_cast_failure, done;
1109 Label *success_target = op->should_profile() ? &profile_cast_success : &done;
1110 Label *failure_target = op->should_profile() ? &profile_cast_failure : stub->entry();
1111
1112 if (op->should_profile()) {
1113 __ cmp(value, 0);
1114 typecheck_profile_helper1(op->profiled_method(), op->profiled_bci(), md, data, mdo_offset_bias, value, k_RInfo, Rtemp, &done);
1115 } else {
1116 __ cbz(value, done);
1117 }
1118 assert_different_registers(k_RInfo, value);
1119 add_debug_info_for_null_check_here(op->info_for_exception());
1120 __ load_klass(k_RInfo, array);
1121 __ load_klass(klass_RInfo, value);
1122 __ ldr(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset()));
1123 __ ldr_u32(Rtemp, Address(k_RInfo, Klass::super_check_offset_offset()));
1124 // check for immediate positive hit
1125 __ ldr(Rtemp, Address(klass_RInfo, Rtemp));
1126 __ cmp(klass_RInfo, k_RInfo);
1127 __ cond_cmp(Rtemp, k_RInfo, ne);
1128 __ b(*success_target, eq);
1129 // check for immediate negative hit
1130 __ ldr_u32(Rtemp, Address(k_RInfo, Klass::super_check_offset_offset()));
1131 __ cmp(Rtemp, in_bytes(Klass::secondary_super_cache_offset()));
1132 __ b(*failure_target, ne);
1133 // slow case
1134 assert(klass_RInfo == R0 && k_RInfo == R1, "runtime call setup");
1135 __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type);
1136 __ cbz(R0, *failure_target);
1137 if (op->should_profile()) {
1138 Register mdo = klass_RInfo, recv = k_RInfo, tmp1 = Rtemp;
1139 if (mdo == value) {
1140 mdo = k_RInfo;
1141 recv = klass_RInfo;
1142 }
1143 typecheck_profile_helper2(md, data, mdo_offset_bias, mdo, recv, value, tmp1,
1144 &profile_cast_success, &profile_cast_failure,
1145 &done, stub->entry());
1146 }
1147 __ bind(done);
1148 break;
1149 }
1150
1151 case lir_checkcast: {
1152 CodeStub* stub = op->stub();
1153 Register obj = op->object()->as_register();
1154 Register res = op->result_opr()->as_register();
1155 Register klass_RInfo = op->tmp1()->as_register();
1156 Register k_RInfo = op->tmp2()->as_register();
1157 ciKlass* k = op->klass();
1158 assert_different_registers(res, k_RInfo, klass_RInfo, Rtemp);
1159
1160 if (stub->is_simple_exception_stub()) {
1161 // TODO: ARM - Late binding is used to prevent confusion of register allocator
1162 assert(stub->is_exception_throw_stub(), "must be");
1163 ((SimpleExceptionStub*)stub)->set_obj(op->result_opr());
1164 }
1165 ciMethodData* md;
1166 ciProfileData* data;
1167 int mdo_offset_bias = 0;
1168
1169 Label done;
1170
1171 Label profile_cast_failure, profile_cast_success;
1172 Label *failure_target = op->should_profile() ? &profile_cast_failure : op->stub()->entry();
1173 Label *success_target = op->should_profile() ? &profile_cast_success : &done;
1174
1175
1176 __ movs(res, obj);
1177 if (op->should_profile()) {
1178 typecheck_profile_helper1(op->profiled_method(), op->profiled_bci(), md, data, mdo_offset_bias, res, klass_RInfo, Rtemp, &done);
1179 } else {
1180 __ b(done, eq);
1181 }
1182 if (k->is_loaded()) {
1183 __ mov_metadata(k_RInfo, k->constant_encoding());
1184 } else if (k_RInfo != obj) {
1185 klass2reg_with_patching(k_RInfo, op->info_for_patch());
1186 __ movs(res, obj);
1187 } else {
1188 // Patching doesn't update "res" register after GC, so do patching first
1189 klass2reg_with_patching(Rtemp, op->info_for_patch());
1190 __ movs(res, obj);
1191 __ mov(k_RInfo, Rtemp);
1192 }
1193 __ load_klass(klass_RInfo, res, ne);
1194
1195 if (op->fast_check()) {
1196 __ cmp(klass_RInfo, k_RInfo, ne);
1197 __ b(*failure_target, ne);
1198 } else if (k->is_loaded()) {
1199 __ b(*success_target, eq);
1200 __ ldr(Rtemp, Address(klass_RInfo, k->super_check_offset()));
1201 if (in_bytes(Klass::secondary_super_cache_offset()) != (int) k->super_check_offset()) {
1202 __ cmp(Rtemp, k_RInfo);
1203 __ b(*failure_target, ne);
1204 } else {
1205 __ cmp(klass_RInfo, k_RInfo);
1206 __ cmp(Rtemp, k_RInfo, ne);
1207 __ b(*success_target, eq);
1208 assert(klass_RInfo == R0 && k_RInfo == R1, "runtime call setup");
1209 __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type);
1210 __ cbz(R0, *failure_target);
1211 }
1212 } else {
1213 __ ldr_u32(Rtemp, Address(k_RInfo, Klass::super_check_offset_offset()));
1214 __ b(*success_target, eq);
1215 // check for immediate positive hit
1216 __ ldr(Rtemp, Address(klass_RInfo, Rtemp));
1217 __ cmp(klass_RInfo, k_RInfo);
1218 __ cmp(Rtemp, k_RInfo, ne);
1219 __ b(*success_target, eq);
1220 // check for immediate negative hit
1221 __ ldr_u32(Rtemp, Address(k_RInfo, Klass::super_check_offset_offset()));
1222 __ cmp(Rtemp, in_bytes(Klass::secondary_super_cache_offset()));
1223 __ b(*failure_target, ne);
1224 // slow case
1225 assert(klass_RInfo == R0 && k_RInfo == R1, "runtime call setup");
1226 __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type);
1227 __ cbz(R0, *failure_target);
1228 }
1229
1230 if (op->should_profile()) {
1231 Register mdo = klass_RInfo, recv = k_RInfo, tmp1 = Rtemp;
1232 typecheck_profile_helper2(md, data, mdo_offset_bias, mdo, recv, res, tmp1,
1233 &profile_cast_success, &profile_cast_failure,
1234 &done, stub->entry());
1235 }
1236 __ bind(done);
1237 break;
1238 }
1239
1240 case lir_instanceof: {
1241 Register obj = op->object()->as_register();
1242 Register res = op->result_opr()->as_register();
1243 Register klass_RInfo = op->tmp1()->as_register();
1244 Register k_RInfo = op->tmp2()->as_register();
1245 ciKlass* k = op->klass();
1246 assert_different_registers(res, klass_RInfo, k_RInfo, Rtemp);
1247
1248 ciMethodData* md;
1249 ciProfileData* data;
1250 int mdo_offset_bias = 0;
1251
1252 Label done;
1253
1254 Label profile_cast_failure, profile_cast_success;
1255 Label *failure_target = op->should_profile() ? &profile_cast_failure : &done;
1256 Label *success_target = op->should_profile() ? &profile_cast_success : &done;
1257
1258 __ movs(res, obj);
1259
1260 if (op->should_profile()) {
1261 typecheck_profile_helper1(op->profiled_method(), op->profiled_bci(), md, data, mdo_offset_bias, res, klass_RInfo, Rtemp, &done);
1262 } else {
1263 __ b(done, eq);
1264 }
1265
1266 if (k->is_loaded()) {
1267 __ mov_metadata(k_RInfo, k->constant_encoding());
1268 } else {
1269 op->info_for_patch()->add_register_oop(FrameMap::as_oop_opr(res));
1270 klass2reg_with_patching(k_RInfo, op->info_for_patch());
1271 }
1272 __ load_klass(klass_RInfo, res);
1273
1274 if (!op->should_profile()) {
1275 __ mov(res, 0);
1276 }
1277
1278 if (op->fast_check()) {
1279 __ cmp(klass_RInfo, k_RInfo);
1280 if (!op->should_profile()) {
1281 set_instanceof_result(_masm, res, eq);
1282 } else {
1283 __ b(profile_cast_failure, ne);
1284 }
1285 } else if (k->is_loaded()) {
1286 __ ldr(Rtemp, Address(klass_RInfo, k->super_check_offset()));
1287 if (in_bytes(Klass::secondary_super_cache_offset()) != (int) k->super_check_offset()) {
1288 __ cmp(Rtemp, k_RInfo);
1289 if (!op->should_profile()) {
1290 set_instanceof_result(_masm, res, eq);
1291 } else {
1292 __ b(profile_cast_failure, ne);
1293 }
1294 } else {
1295 __ cmp(klass_RInfo, k_RInfo);
1296 __ cond_cmp(Rtemp, k_RInfo, ne);
1297 if (!op->should_profile()) {
1298 set_instanceof_result(_masm, res, eq);
1299 }
1300 __ b(*success_target, eq);
1301 assert(klass_RInfo == R0 && k_RInfo == R1, "runtime call setup");
1302 __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type);
1303 if (!op->should_profile()) {
1304 move_regs(R0, res);
1305 } else {
1306 __ cbz(R0, *failure_target);
1307 }
1308 }
1309 } else {
1310 __ ldr_u32(Rtemp, Address(k_RInfo, Klass::super_check_offset_offset()));
1311 // check for immediate positive hit
1312 __ cmp(klass_RInfo, k_RInfo);
1313 if (!op->should_profile()) {
1314 __ ldr(res, Address(klass_RInfo, Rtemp), ne);
1315 __ cond_cmp(res, k_RInfo, ne);
1316 set_instanceof_result(_masm, res, eq);
1317 } else {
1318 __ ldr(Rtemp, Address(klass_RInfo, Rtemp), ne);
1319 __ cond_cmp(Rtemp, k_RInfo, ne);
1320 }
1321 __ b(*success_target, eq);
1322 // check for immediate negative hit
1323 if (op->should_profile()) {
1324 __ ldr_u32(Rtemp, Address(k_RInfo, Klass::super_check_offset_offset()));
1325 }
1326 __ cmp(Rtemp, in_bytes(Klass::secondary_super_cache_offset()));
1327 if (!op->should_profile()) {
1328 __ mov(res, 0, ne);
1329 }
1330 __ b(*failure_target, ne);
1331 // slow case
1332 assert(klass_RInfo == R0 && k_RInfo == R1, "runtime call setup");
1333 __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type);
1334 if (!op->should_profile()) {
1335 move_regs(R0, res);
1336 }
1337 if (op->should_profile()) {
1338 __ cbz(R0, *failure_target);
1339 }
1340 }
1341
1342 if (op->should_profile()) {
1343 Label done_ok, done_failure;
1344 Register mdo = klass_RInfo, recv = k_RInfo, tmp1 = Rtemp;
1345 typecheck_profile_helper2(md, data, mdo_offset_bias, mdo, recv, res, tmp1,
1346 &profile_cast_success, &profile_cast_failure,
1347 &done_ok, &done_failure);
1348 __ bind(done_failure);
1349 __ mov(res, 0);
1350 __ b(done);
1351 __ bind(done_ok);
1352 __ mov(res, 1);
1353 }
1354 __ bind(done);
1355 break;
1356 }
1357 default:
1358 ShouldNotReachHere();
1359 }
1360 }
1361
1362
1363 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
1364 // if (*addr == cmpval) {
1365 // *addr = newval;
1366 // dest = 1;
1367 // } else {
1368 // dest = 0;
1369 // }
1370 // FIXME: membar_release
1371 __ membar(MacroAssembler::Membar_mask_bits(MacroAssembler::StoreStore | MacroAssembler::LoadStore), Rtemp);
1372 Register addr = op->addr()->is_register() ?
1373 op->addr()->as_pointer_register() :
1374 op->addr()->as_address_ptr()->base()->as_pointer_register();
1375 assert(op->addr()->is_register() || op->addr()->as_address_ptr()->disp() == 0, "unexpected disp");
1376 assert(op->addr()->is_register() || op->addr()->as_address_ptr()->index() == LIR_Opr::illegalOpr(), "unexpected index");
1377 if (op->code() == lir_cas_int || op->code() == lir_cas_obj) {
1378 Register cmpval = op->cmp_value()->as_register();
1379 Register newval = op->new_value()->as_register();
1380 Register dest = op->result_opr()->as_register();
1381 assert_different_registers(dest, addr, cmpval, newval, Rtemp);
1382
1383 __ atomic_cas_bool(cmpval, newval, addr, 0, Rtemp); // Rtemp free by default at C1 LIR layer
1384 __ mov(dest, 1, eq);
1385 __ mov(dest, 0, ne);
1386 } else if (op->code() == lir_cas_long) {
1387 assert(VM_Version::supports_cx8(), "wrong machine");
1388 Register cmp_value_lo = op->cmp_value()->as_register_lo();
1389 Register cmp_value_hi = op->cmp_value()->as_register_hi();
1390 Register new_value_lo = op->new_value()->as_register_lo();
1391 Register new_value_hi = op->new_value()->as_register_hi();
1392 Register dest = op->result_opr()->as_register();
1393 Register tmp_lo = op->tmp1()->as_register_lo();
1394 Register tmp_hi = op->tmp1()->as_register_hi();
1395
1396 assert_different_registers(tmp_lo, tmp_hi, cmp_value_lo, cmp_value_hi, dest, new_value_lo, new_value_hi, addr);
1397 assert(tmp_hi->encoding() == tmp_lo->encoding() + 1, "non aligned register pair");
1398 assert(new_value_hi->encoding() == new_value_lo->encoding() + 1, "non aligned register pair");
1399 assert((tmp_lo->encoding() & 0x1) == 0, "misaligned register pair");
1400 assert((new_value_lo->encoding() & 0x1) == 0, "misaligned register pair");
1401 __ atomic_cas64(tmp_lo, tmp_hi, dest, cmp_value_lo, cmp_value_hi,
1402 new_value_lo, new_value_hi, addr, 0);
1403 } else {
1404 Unimplemented();
1405 }
1406 // FIXME: is full membar really needed instead of just membar_acquire?
1407 __ membar(MacroAssembler::Membar_mask_bits(MacroAssembler::StoreLoad | MacroAssembler::StoreStore), Rtemp);
1408 }
1409
1410
1411 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type,
1412 LIR_Opr cmp_opr1, LIR_Opr cmp_opr2) {
1413 assert(cmp_opr1 == LIR_OprFact::illegalOpr && cmp_opr2 == LIR_OprFact::illegalOpr, "unnecessary cmp oprs on arm");
1414
1415 AsmCondition acond = al;
1416 AsmCondition ncond = nv;
1417 if (opr1 != opr2) {
1418 switch (condition) {
1419 case lir_cond_equal: acond = eq; ncond = ne; break;
1420 case lir_cond_notEqual: acond = ne; ncond = eq; break;
1421 case lir_cond_less: acond = lt; ncond = ge; break;
1422 case lir_cond_lessEqual: acond = le; ncond = gt; break;
1423 case lir_cond_greaterEqual: acond = ge; ncond = lt; break;
1424 case lir_cond_greater: acond = gt; ncond = le; break;
1425 case lir_cond_aboveEqual: acond = hs; ncond = lo; break;
1426 case lir_cond_belowEqual: acond = ls; ncond = hi; break;
1427 default: ShouldNotReachHere();
1428 }
1429 }
1430
1431 for (;;) { // two iterations only
1432 if (opr1 == result) {
1433 // do nothing
1434 } else if (opr1->is_single_cpu()) {
1435 __ mov(result->as_register(), opr1->as_register(), acond);
1436 } else if (opr1->is_double_cpu()) {
1437 __ long_move(result->as_register_lo(), result->as_register_hi(),
1438 opr1->as_register_lo(), opr1->as_register_hi(), acond);
1439 } else if (opr1->is_single_stack()) {
1440 __ ldr(result->as_register(), frame_map()->address_for_slot(opr1->single_stack_ix()), acond);
1441 } else if (opr1->is_double_stack()) {
1442 __ ldr(result->as_register_lo(),
1443 frame_map()->address_for_slot(opr1->double_stack_ix(), lo_word_offset_in_bytes), acond);
1444 __ ldr(result->as_register_hi(),
1445 frame_map()->address_for_slot(opr1->double_stack_ix(), hi_word_offset_in_bytes), acond);
1446 } else if (opr1->is_illegal()) {
1447 // do nothing: this part of the cmove has been optimized away in the peephole optimizer
1448 } else {
1449 assert(opr1->is_constant(), "must be");
1450 LIR_Const* c = opr1->as_constant_ptr();
1451
1452 switch (c->type()) {
1453 case T_INT:
1454 __ mov_slow(result->as_register(), c->as_jint(), acond);
1455 break;
1456 case T_LONG:
1457 __ mov_slow(result->as_register_lo(), c->as_jint_lo(), acond);
1458 __ mov_slow(result->as_register_hi(), c->as_jint_hi(), acond);
1459 break;
1460 case T_OBJECT:
1461 __ mov_oop(result->as_register(), c->as_jobject(), 0, acond);
1462 break;
1463 case T_FLOAT:
1464 #ifdef __SOFTFP__
1465 // not generated now.
1466 __ mov_slow(result->as_register(), c->as_jint(), acond);
1467 #else
1468 __ mov_float(result->as_float_reg(), c->as_jfloat(), acond);
1469 #endif // __SOFTFP__
1470 break;
1471 case T_DOUBLE:
1472 #ifdef __SOFTFP__
1473 // not generated now.
1474 __ mov_slow(result->as_register_lo(), c->as_jint_lo(), acond);
1475 __ mov_slow(result->as_register_hi(), c->as_jint_hi(), acond);
1476 #else
1477 __ mov_double(result->as_double_reg(), c->as_jdouble(), acond);
1478 #endif // __SOFTFP__
1479 break;
1480 case T_METADATA:
1481 __ mov_metadata(result->as_register(), c->as_metadata(), acond);
1482 break;
1483 default:
1484 ShouldNotReachHere();
1485 }
1486 }
1487
1488 // Negate the condition and repeat the algorithm with the second operand
1489 if (opr1 == opr2) { break; }
1490 opr1 = opr2;
1491 acond = ncond;
1492 }
1493 }
1494
1495 #ifdef ASSERT
1496 static int reg_size(LIR_Opr op) {
1497 switch (op->type()) {
1498 case T_FLOAT:
1499 case T_INT: return BytesPerInt;
1500 case T_LONG:
1501 case T_DOUBLE: return BytesPerLong;
1502 case T_OBJECT:
1503 case T_ARRAY:
1504 case T_METADATA: return BytesPerWord;
1505 case T_ADDRESS:
1506 case T_ILLEGAL: // fall through
1507 default: ShouldNotReachHere(); return -1;
1508 }
1509 }
1510 #endif
1511
1512 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) {
1513 assert(info == NULL, "unused on this code path");
1514 assert(dest->is_register(), "wrong items state");
1515
1516 if (right->is_address()) {
1517 // special case for adding shifted/extended register
1518 const Register res = dest->as_pointer_register();
1519 const Register lreg = left->as_pointer_register();
1520 const LIR_Address* addr = right->as_address_ptr();
1521
1522 assert(addr->base()->as_pointer_register() == lreg && addr->index()->is_register() && addr->disp() == 0, "must be");
1523
1524 int scale = addr->scale();
1525 AsmShift shift = lsl;
1526
1527
1528 assert(reg_size(addr->base()) == reg_size(addr->index()), "should be");
1529 assert(reg_size(addr->base()) == reg_size(dest), "should be");
1530 assert(reg_size(dest) == wordSize, "should be");
1531
1532 AsmOperand operand(addr->index()->as_pointer_register(), shift, scale);
1533 switch (code) {
1534 case lir_add: __ add(res, lreg, operand); break;
1535 case lir_sub: __ sub(res, lreg, operand); break;
1536 default: ShouldNotReachHere();
1537 }
1538
1539 } else if (left->is_address()) {
1540 assert(code == lir_sub && right->is_single_cpu(), "special case used by strength_reduce_multiply()");
1541 const LIR_Address* addr = left->as_address_ptr();
1542 const Register res = dest->as_register();
1543 const Register rreg = right->as_register();
1544 assert(addr->base()->as_register() == rreg && addr->index()->is_register() && addr->disp() == 0, "must be");
1545 __ rsb(res, rreg, AsmOperand(addr->index()->as_register(), lsl, addr->scale()));
1546
1547 } else if (dest->is_single_cpu()) {
1548 assert(left->is_single_cpu(), "unexpected left operand");
1549
1550 const Register res = dest->as_register();
1551 const Register lreg = left->as_register();
1552
1553 if (right->is_single_cpu()) {
1554 const Register rreg = right->as_register();
1555 switch (code) {
1556 case lir_add: __ add_32(res, lreg, rreg); break;
1557 case lir_sub: __ sub_32(res, lreg, rreg); break;
1558 case lir_mul: __ mul_32(res, lreg, rreg); break;
1559 default: ShouldNotReachHere();
1560 }
1561 } else {
1562 assert(right->is_constant(), "must be");
1563 const jint c = right->as_constant_ptr()->as_jint();
1564 if (!Assembler::is_arith_imm_in_range(c)) {
1565 BAILOUT("illegal arithmetic operand");
1566 }
1567 switch (code) {
1568 case lir_add: __ add_32(res, lreg, c); break;
1569 case lir_sub: __ sub_32(res, lreg, c); break;
1570 default: ShouldNotReachHere();
1571 }
1572 }
1573
1574 } else if (dest->is_double_cpu()) {
1575 Register res_lo = dest->as_register_lo();
1576 Register res_hi = dest->as_register_hi();
1577 Register lreg_lo = left->as_register_lo();
1578 Register lreg_hi = left->as_register_hi();
1579 if (right->is_double_cpu()) {
1580 Register rreg_lo = right->as_register_lo();
1581 Register rreg_hi = right->as_register_hi();
1582 if (res_lo == lreg_hi || res_lo == rreg_hi) {
1583 res_lo = Rtemp;
1584 }
1585 switch (code) {
1586 case lir_add:
1587 __ adds(res_lo, lreg_lo, rreg_lo);
1588 __ adc(res_hi, lreg_hi, rreg_hi);
1589 break;
1590 case lir_sub:
1591 __ subs(res_lo, lreg_lo, rreg_lo);
1592 __ sbc(res_hi, lreg_hi, rreg_hi);
1593 break;
1594 default:
1595 ShouldNotReachHere();
1596 }
1597 } else {
1598 assert(right->is_constant(), "must be");
1599 assert((right->as_constant_ptr()->as_jlong() >> 32) == 0, "out of range");
1600 const jint c = (jint) right->as_constant_ptr()->as_jlong();
1601 if (res_lo == lreg_hi) {
1602 res_lo = Rtemp;
1603 }
1604 switch (code) {
1605 case lir_add:
1606 __ adds(res_lo, lreg_lo, c);
1607 __ adc(res_hi, lreg_hi, 0);
1608 break;
1609 case lir_sub:
1610 __ subs(res_lo, lreg_lo, c);
1611 __ sbc(res_hi, lreg_hi, 0);
1612 break;
1613 default:
1614 ShouldNotReachHere();
1615 }
1616 }
1617 move_regs(res_lo, dest->as_register_lo());
1618
1619 } else if (dest->is_single_fpu()) {
1620 assert(left->is_single_fpu(), "must be");
1621 assert(right->is_single_fpu(), "must be");
1622 const FloatRegister res = dest->as_float_reg();
1623 const FloatRegister lreg = left->as_float_reg();
1624 const FloatRegister rreg = right->as_float_reg();
1625 switch (code) {
1626 case lir_add: __ add_float(res, lreg, rreg); break;
1627 case lir_sub: __ sub_float(res, lreg, rreg); break;
1628 case lir_mul: __ mul_float(res, lreg, rreg); break;
1629 case lir_div: __ div_float(res, lreg, rreg); break;
1630 default: ShouldNotReachHere();
1631 }
1632 } else if (dest->is_double_fpu()) {
1633 assert(left->is_double_fpu(), "must be");
1634 assert(right->is_double_fpu(), "must be");
1635 const FloatRegister res = dest->as_double_reg();
1636 const FloatRegister lreg = left->as_double_reg();
1637 const FloatRegister rreg = right->as_double_reg();
1638 switch (code) {
1639 case lir_add: __ add_double(res, lreg, rreg); break;
1640 case lir_sub: __ sub_double(res, lreg, rreg); break;
1641 case lir_mul: __ mul_double(res, lreg, rreg); break;
1642 case lir_div: __ div_double(res, lreg, rreg); break;
1643 default: ShouldNotReachHere();
1644 }
1645 } else {
1646 ShouldNotReachHere();
1647 }
1648 }
1649
1650
1651 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr unused, LIR_Opr dest, LIR_Op* op) {
1652 switch (code) {
1653 case lir_abs:
1654 __ abs_double(dest->as_double_reg(), value->as_double_reg());
1655 break;
1656 case lir_sqrt:
1657 __ sqrt_double(dest->as_double_reg(), value->as_double_reg());
1658 break;
1659 default:
1660 ShouldNotReachHere();
1661 }
1662 }
1663
1664
1665 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest) {
1666 assert(dest->is_register(), "wrong items state");
1667 assert(left->is_register(), "wrong items state");
1668
1669 if (dest->is_single_cpu()) {
1670
1671 const Register res = dest->as_register();
1672 const Register lreg = left->as_register();
1673
1674 if (right->is_single_cpu()) {
1675 const Register rreg = right->as_register();
1676 switch (code) {
1677 case lir_logic_and: __ and_32(res, lreg, rreg); break;
1678 case lir_logic_or: __ orr_32(res, lreg, rreg); break;
1679 case lir_logic_xor: __ eor_32(res, lreg, rreg); break;
1680 default: ShouldNotReachHere();
1681 }
1682 } else {
1683 assert(right->is_constant(), "must be");
1684 const uint c = (uint)right->as_constant_ptr()->as_jint();
1685 if (!Assembler::is_arith_imm_in_range(c)) {
1686 BAILOUT("illegal arithmetic operand");
1687 }
1688 switch (code) {
1689 case lir_logic_and: __ and_32(res, lreg, c); break;
1690 case lir_logic_or: __ orr_32(res, lreg, c); break;
1691 case lir_logic_xor: __ eor_32(res, lreg, c); break;
1692 default: ShouldNotReachHere();
1693 }
1694 }
1695 } else {
1696 assert(dest->is_double_cpu(), "should be");
1697 Register res_lo = dest->as_register_lo();
1698
1699 assert (dest->type() == T_LONG, "unexpected result type");
1700 assert (left->type() == T_LONG, "unexpected left type");
1701 assert (right->type() == T_LONG, "unexpected right type");
1702
1703 const Register res_hi = dest->as_register_hi();
1704 const Register lreg_lo = left->as_register_lo();
1705 const Register lreg_hi = left->as_register_hi();
1706
1707 if (right->is_register()) {
1708 const Register rreg_lo = right->as_register_lo();
1709 const Register rreg_hi = right->as_register_hi();
1710 if (res_lo == lreg_hi || res_lo == rreg_hi) {
1711 res_lo = Rtemp; // Temp register helps to avoid overlap between result and input
1712 }
1713 switch (code) {
1714 case lir_logic_and:
1715 __ andr(res_lo, lreg_lo, rreg_lo);
1716 __ andr(res_hi, lreg_hi, rreg_hi);
1717 break;
1718 case lir_logic_or:
1719 __ orr(res_lo, lreg_lo, rreg_lo);
1720 __ orr(res_hi, lreg_hi, rreg_hi);
1721 break;
1722 case lir_logic_xor:
1723 __ eor(res_lo, lreg_lo, rreg_lo);
1724 __ eor(res_hi, lreg_hi, rreg_hi);
1725 break;
1726 default:
1727 ShouldNotReachHere();
1728 }
1729 move_regs(res_lo, dest->as_register_lo());
1730 } else {
1731 assert(right->is_constant(), "must be");
1732 const jint c_lo = (jint) right->as_constant_ptr()->as_jlong();
1733 const jint c_hi = (jint) (right->as_constant_ptr()->as_jlong() >> 32);
1734 // Case for logic_or from do_ClassIDIntrinsic()
1735 if (c_hi == 0 && AsmOperand::is_rotated_imm(c_lo)) {
1736 switch (code) {
1737 case lir_logic_and:
1738 __ andr(res_lo, lreg_lo, c_lo);
1739 __ mov(res_hi, 0);
1740 break;
1741 case lir_logic_or:
1742 __ orr(res_lo, lreg_lo, c_lo);
1743 break;
1744 case lir_logic_xor:
1745 __ eor(res_lo, lreg_lo, c_lo);
1746 break;
1747 default:
1748 ShouldNotReachHere();
1749 }
1750 } else if (code == lir_logic_and &&
1751 c_hi == -1 &&
1752 (AsmOperand::is_rotated_imm(c_lo) ||
1753 AsmOperand::is_rotated_imm(~c_lo))) {
1754 // Another case which handles logic_and from do_ClassIDIntrinsic()
1755 if (AsmOperand::is_rotated_imm(c_lo)) {
1756 __ andr(res_lo, lreg_lo, c_lo);
1757 } else {
1758 __ bic(res_lo, lreg_lo, ~c_lo);
1759 }
1760 if (res_hi != lreg_hi) {
1761 __ mov(res_hi, lreg_hi);
1762 }
1763 } else {
1764 BAILOUT("64 bit constant cannot be inlined");
1765 }
1766 }
1767 }
1768 }
1769
1770
1771
1772 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
1773 if (opr1->is_single_cpu()) {
1774 if (opr2->is_constant()) {
1775 switch (opr2->as_constant_ptr()->type()) {
1776 case T_INT: {
1777 const jint c = opr2->as_constant_ptr()->as_jint();
1778 if (Assembler::is_arith_imm_in_range(c)) {
1779 __ cmp_32(opr1->as_register(), c);
1780 } else if (Assembler::is_arith_imm_in_range(-c)) {
1781 __ cmn_32(opr1->as_register(), -c);
1782 } else {
1783 // This can happen when compiling lookupswitch
1784 __ mov_slow(Rtemp, c);
1785 __ cmp_32(opr1->as_register(), Rtemp);
1786 }
1787 break;
1788 }
1789 case T_OBJECT:
1790 assert(opr2->as_constant_ptr()->as_jobject() == NULL, "cannot handle otherwise");
1791 __ cmp(opr1->as_register(), 0);
1792 break;
1793 case T_METADATA:
1794 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "Only equality tests");
1795 assert(opr2->as_constant_ptr()->as_metadata() == NULL, "cannot handle otherwise");
1796 __ cmp(opr1->as_register(), 0);
1797 break;
1798 default:
1799 ShouldNotReachHere();
1800 }
1801 } else if (opr2->is_single_cpu()) {
1802 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) {
1803 assert(opr2->type() == T_OBJECT || opr2->type() == T_ARRAY, "incompatibe type");
1804 __ cmpoop(opr1->as_register(), opr2->as_register());
1805 } else if (opr1->type() == T_METADATA || opr1->type() == T_ADDRESS) {
1806 assert(opr2->type() == T_METADATA || opr2->type() == T_ADDRESS, "incompatibe type");
1807 __ cmp(opr1->as_register(), opr2->as_register());
1808 } else {
1809 assert(opr2->type() != T_OBJECT && opr2->type() != T_ARRAY && opr2->type() != T_METADATA && opr2->type() != T_ADDRESS, "incompatibe type");
1810 __ cmp_32(opr1->as_register(), opr2->as_register());
1811 }
1812 } else {
1813 ShouldNotReachHere();
1814 }
1815 } else if (opr1->is_double_cpu()) {
1816 Register xlo = opr1->as_register_lo();
1817 Register xhi = opr1->as_register_hi();
1818 if (opr2->is_constant() && opr2->as_jlong() == 0) {
1819 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "cannot handle otherwise");
1820 __ orrs(Rtemp, xlo, xhi);
1821 } else if (opr2->is_register()) {
1822 Register ylo = opr2->as_register_lo();
1823 Register yhi = opr2->as_register_hi();
1824 if (condition == lir_cond_equal || condition == lir_cond_notEqual) {
1825 __ teq(xhi, yhi);
1826 __ teq(xlo, ylo, eq);
1827 } else {
1828 __ subs(Rtemp, xlo, ylo);
1829 __ sbcs(Rtemp, xhi, yhi);
1830 }
1831 } else {
1832 ShouldNotReachHere();
1833 }
1834 } else if (opr1->is_single_fpu()) {
1835 if (opr2->is_constant()) {
1836 assert(opr2->as_jfloat() == 0.0f, "cannot handle otherwise");
1837 __ cmp_zero_float(opr1->as_float_reg());
1838 } else {
1839 __ cmp_float(opr1->as_float_reg(), opr2->as_float_reg());
1840 }
1841 } else if (opr1->is_double_fpu()) {
1842 if (opr2->is_constant()) {
1843 assert(opr2->as_jdouble() == 0.0, "cannot handle otherwise");
1844 __ cmp_zero_double(opr1->as_double_reg());
1845 } else {
1846 __ cmp_double(opr1->as_double_reg(), opr2->as_double_reg());
1847 }
1848 } else {
1849 ShouldNotReachHere();
1850 }
1851 }
1852
1853 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op) {
1854 const Register res = dst->as_register();
1855 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
1856 comp_op(lir_cond_unknown, left, right, op);
1857 __ fmstat();
1858 if (code == lir_ucmp_fd2i) { // unordered is less
1859 __ mvn(res, 0, lt);
1860 __ mov(res, 1, ge);
1861 } else { // unordered is greater
1862 __ mov(res, 1, cs);
1863 __ mvn(res, 0, cc);
1864 }
1865 __ mov(res, 0, eq);
1866
1867 } else {
1868 assert(code == lir_cmp_l2i, "must be");
1869
1870 Label done;
1871 const Register xlo = left->as_register_lo();
1872 const Register xhi = left->as_register_hi();
1873 const Register ylo = right->as_register_lo();
1874 const Register yhi = right->as_register_hi();
1875 __ cmp(xhi, yhi);
1876 __ mov(res, 1, gt);
1877 __ mvn(res, 0, lt);
1878 __ b(done, ne);
1879 __ subs(res, xlo, ylo);
1880 __ mov(res, 1, hi);
1881 __ mvn(res, 0, lo);
1882 __ bind(done);
1883 }
1884 }
1885
1886
1887 void LIR_Assembler::align_call(LIR_Code code) {
1888 // Not needed
1889 }
1890
1891
1892 void LIR_Assembler::call(LIR_OpJavaCall *op, relocInfo::relocType rtype) {
1893 int ret_addr_offset = __ patchable_call(op->addr(), rtype);
1894 assert(ret_addr_offset == __ offset(), "embedded return address not allowed");
1895 add_call_info_here(op->info());
1896 }
1897
1898
1899 void LIR_Assembler::ic_call(LIR_OpJavaCall *op) {
1900 bool near_range = __ cache_fully_reachable();
1901 address oop_address = pc();
1902
1903 bool use_movw = VM_Version::supports_movw();
1904
1905 // Ricklass may contain something that is not a metadata pointer so
1906 // mov_metadata can't be used
1907 InlinedAddress value((address)Universe::non_oop_word());
1908 InlinedAddress addr(op->addr());
1909 if (use_movw) {
1910 __ movw(Ricklass, ((unsigned int)Universe::non_oop_word()) & 0xffff);
1911 __ movt(Ricklass, ((unsigned int)Universe::non_oop_word()) >> 16);
1912 } else {
1913 // No movw/movt, must be load a pc relative value but no
1914 // relocation so no metadata table to load from.
1915 // Use a b instruction rather than a bl, inline constant after the
1916 // branch, use a PC relative ldr to load the constant, arrange for
1917 // the call to return after the constant(s).
1918 __ ldr_literal(Ricklass, value);
1919 }
1920 __ relocate(virtual_call_Relocation::spec(oop_address));
1921 if (near_range && use_movw) {
1922 __ bl(op->addr());
1923 } else {
1924 Label call_return;
1925 __ adr(LR, call_return);
1926 if (near_range) {
1927 __ b(op->addr());
1928 } else {
1929 __ indirect_jump(addr, Rtemp);
1930 __ bind_literal(addr);
1931 }
1932 if (!use_movw) {
1933 __ bind_literal(value);
1934 }
1935 __ bind(call_return);
1936 }
1937 add_call_info(code_offset(), op->info());
1938 }
1939
1940 void LIR_Assembler::emit_static_call_stub() {
1941 address call_pc = __ pc();
1942 address stub = __ start_a_stub(call_stub_size());
1943 if (stub == NULL) {
1944 BAILOUT("static call stub overflow");
1945 }
1946
1947 DEBUG_ONLY(int offset = code_offset();)
1948
1949 InlinedMetadata metadata_literal(NULL);
1950 __ relocate(static_stub_Relocation::spec(call_pc));
1951 // If not a single instruction, NativeMovConstReg::next_instruction_address()
1952 // must jump over the whole following ldr_literal.
1953 // (See CompiledStaticCall::set_to_interpreted())
1954 #ifdef ASSERT
1955 address ldr_site = __ pc();
1956 #endif
1957 __ ldr_literal(Rmethod, metadata_literal);
1958 assert(nativeMovConstReg_at(ldr_site)->next_instruction_address() == __ pc(), "Fix ldr_literal or its parsing");
1959 bool near_range = __ cache_fully_reachable();
1960 InlinedAddress dest((address)-1);
1961 if (near_range) {
1962 address branch_site = __ pc();
1963 __ b(branch_site); // b to self maps to special NativeJump -1 destination
1964 } else {
1965 __ indirect_jump(dest, Rtemp);
1966 }
1967 __ bind_literal(metadata_literal); // includes spec_for_immediate reloc
1968 if (!near_range) {
1969 __ bind_literal(dest); // special NativeJump -1 destination
1970 }
1971
1972 assert(code_offset() - offset <= call_stub_size(), "overflow");
1973 __ end_a_stub();
1974 }
1975
1976 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
1977 assert(exceptionOop->as_register() == Rexception_obj, "must match");
1978 assert(exceptionPC->as_register() == Rexception_pc, "must match");
1979 info->add_register_oop(exceptionOop);
1980
1981 Runtime1::StubID handle_id = compilation()->has_fpu_code() ?
1982 Runtime1::handle_exception_id :
1983 Runtime1::handle_exception_nofpu_id;
1984 Label return_address;
1985 __ adr(Rexception_pc, return_address);
1986 __ call(Runtime1::entry_for(handle_id), relocInfo::runtime_call_type);
1987 __ bind(return_address);
1988 add_call_info_here(info); // for exception handler
1989 }
1990
1991 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
1992 assert(exceptionOop->as_register() == Rexception_obj, "must match");
1993 __ b(_unwind_handler_entry);
1994 }
1995
1996 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
1997 AsmShift shift = lsl;
1998 switch (code) {
1999 case lir_shl: shift = lsl; break;
2000 case lir_shr: shift = asr; break;
2001 case lir_ushr: shift = lsr; break;
2002 default: ShouldNotReachHere();
2003 }
2004
2005 if (dest->is_single_cpu()) {
2006 __ andr(Rtemp, count->as_register(), 31);
2007 __ mov(dest->as_register(), AsmOperand(left->as_register(), shift, Rtemp));
2008 } else if (dest->is_double_cpu()) {
2009 Register dest_lo = dest->as_register_lo();
2010 Register dest_hi = dest->as_register_hi();
2011 Register src_lo = left->as_register_lo();
2012 Register src_hi = left->as_register_hi();
2013 Register Rcount = count->as_register();
2014 // Resolve possible register conflicts
2015 if (shift == lsl && dest_hi == src_lo) {
2016 dest_hi = Rtemp;
2017 } else if (shift != lsl && dest_lo == src_hi) {
2018 dest_lo = Rtemp;
2019 } else if (dest_lo == src_lo && dest_hi == src_hi) {
2020 dest_lo = Rtemp;
2021 } else if (dest_lo == Rcount || dest_hi == Rcount) {
2022 Rcount = Rtemp;
2023 }
2024 __ andr(Rcount, count->as_register(), 63);
2025 __ long_shift(dest_lo, dest_hi, src_lo, src_hi, shift, Rcount);
2026 move_regs(dest_lo, dest->as_register_lo());
2027 move_regs(dest_hi, dest->as_register_hi());
2028 } else {
2029 ShouldNotReachHere();
2030 }
2031 }
2032
2033
2034 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2035 AsmShift shift = lsl;
2036 switch (code) {
2037 case lir_shl: shift = lsl; break;
2038 case lir_shr: shift = asr; break;
2039 case lir_ushr: shift = lsr; break;
2040 default: ShouldNotReachHere();
2041 }
2042
2043 if (dest->is_single_cpu()) {
2044 count &= 31;
2045 if (count != 0) {
2046 __ mov(dest->as_register(), AsmOperand(left->as_register(), shift, count));
2047 } else {
2048 move_regs(left->as_register(), dest->as_register());
2049 }
2050 } else if (dest->is_double_cpu()) {
2051 count &= 63;
2052 if (count != 0) {
2053 Register dest_lo = dest->as_register_lo();
2054 Register dest_hi = dest->as_register_hi();
2055 Register src_lo = left->as_register_lo();
2056 Register src_hi = left->as_register_hi();
2057 // Resolve possible register conflicts
2058 if (shift == lsl && dest_hi == src_lo) {
2059 dest_hi = Rtemp;
2060 } else if (shift != lsl && dest_lo == src_hi) {
2061 dest_lo = Rtemp;
2062 }
2063 __ long_shift(dest_lo, dest_hi, src_lo, src_hi, shift, count);
2064 move_regs(dest_lo, dest->as_register_lo());
2065 move_regs(dest_hi, dest->as_register_hi());
2066 } else {
2067 __ long_move(dest->as_register_lo(), dest->as_register_hi(),
2068 left->as_register_lo(), left->as_register_hi());
2069 }
2070 } else {
2071 ShouldNotReachHere();
2072 }
2073 }
2074
2075
2076 // Saves 4 given registers in reserved argument area.
2077 void LIR_Assembler::save_in_reserved_area(Register r1, Register r2, Register r3, Register r4) {
2078 verify_reserved_argument_area_size(4);
2079 __ stmia(SP, RegisterSet(r1) | RegisterSet(r2) | RegisterSet(r3) | RegisterSet(r4));
2080 }
2081
2082 // Restores 4 given registers from reserved argument area.
2083 void LIR_Assembler::restore_from_reserved_area(Register r1, Register r2, Register r3, Register r4) {
2084 __ ldmia(SP, RegisterSet(r1) | RegisterSet(r2) | RegisterSet(r3) | RegisterSet(r4), no_writeback);
2085 }
2086
2087
2088 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
2089 ciArrayKlass* default_type = op->expected_type();
2090 Register src = op->src()->as_register();
2091 Register src_pos = op->src_pos()->as_register();
2092 Register dst = op->dst()->as_register();
2093 Register dst_pos = op->dst_pos()->as_register();
2094 Register length = op->length()->as_register();
2095 Register tmp = op->tmp()->as_register();
2096 Register tmp2 = Rtemp;
2097
2098 assert(src == R0 && src_pos == R1 && dst == R2 && dst_pos == R3, "code assumption");
2099
2100 CodeStub* stub = op->stub();
2101
2102 int flags = op->flags();
2103 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL;
2104 if (basic_type == T_ARRAY) basic_type = T_OBJECT;
2105
2106 // If we don't know anything or it's an object array, just go through the generic arraycopy
2107 if (default_type == NULL) {
2108
2109 // save arguments, because they will be killed by a runtime call
2110 save_in_reserved_area(R0, R1, R2, R3);
2111
2112 // pass length argument on SP[0]
2113 __ str(length, Address(SP, -2*wordSize, pre_indexed)); // 2 words for a proper stack alignment
2114
2115 address copyfunc_addr = StubRoutines::generic_arraycopy();
2116 assert(copyfunc_addr != NULL, "generic arraycopy stub required");
2117 #ifndef PRODUCT
2118 if (PrintC1Statistics) {
2119 __ inc_counter((address)&Runtime1::_generic_arraycopystub_cnt, tmp, tmp2);
2120 }
2121 #endif // !PRODUCT
2122 // the stub is in the code cache so close enough
2123 __ call(copyfunc_addr, relocInfo::runtime_call_type);
2124
2125 __ add(SP, SP, 2*wordSize);
2126
2127 __ cbz_32(R0, *stub->continuation());
2128
2129 __ mvn_32(tmp, R0);
2130 restore_from_reserved_area(R0, R1, R2, R3); // load saved arguments in slow case only
2131 __ sub_32(length, length, tmp);
2132 __ add_32(src_pos, src_pos, tmp);
2133 __ add_32(dst_pos, dst_pos, tmp);
2134
2135 __ b(*stub->entry());
2136
2137 __ bind(*stub->continuation());
2138 return;
2139 }
2140
2141 assert(default_type != NULL && default_type->is_array_klass() && default_type->is_loaded(),
2142 "must be true at this point");
2143 int elem_size = type2aelembytes(basic_type);
2144 int shift = exact_log2(elem_size);
2145
2146 // Check for NULL
2147 if (flags & LIR_OpArrayCopy::src_null_check) {
2148 if (flags & LIR_OpArrayCopy::dst_null_check) {
2149 __ cmp(src, 0);
2150 __ cond_cmp(dst, 0, ne); // make one instruction shorter if both checks are needed
2151 __ b(*stub->entry(), eq);
2152 } else {
2153 __ cbz(src, *stub->entry());
2154 }
2155 } else if (flags & LIR_OpArrayCopy::dst_null_check) {
2156 __ cbz(dst, *stub->entry());
2157 }
2158
2159 // If the compiler was not able to prove that exact type of the source or the destination
2160 // of the arraycopy is an array type, check at runtime if the source or the destination is
2161 // an instance type.
2162 if (flags & LIR_OpArrayCopy::type_check) {
2163 if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::dst_objarray)) {
2164 __ load_klass(tmp, dst);
2165 __ ldr_u32(tmp2, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2166 __ mov_slow(tmp, Klass::_lh_neutral_value);
2167 __ cmp_32(tmp2, tmp);
2168 __ b(*stub->entry(), ge);
2169 }
2170
2171 if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::src_objarray)) {
2172 __ load_klass(tmp, src);
2173 __ ldr_u32(tmp2, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2174 __ mov_slow(tmp, Klass::_lh_neutral_value);
2175 __ cmp_32(tmp2, tmp);
2176 __ b(*stub->entry(), ge);
2177 }
2178 }
2179
2180 // Check if negative
2181 const int all_positive_checks = LIR_OpArrayCopy::src_pos_positive_check |
2182 LIR_OpArrayCopy::dst_pos_positive_check |
2183 LIR_OpArrayCopy::length_positive_check;
2184 switch (flags & all_positive_checks) {
2185 case LIR_OpArrayCopy::src_pos_positive_check:
2186 __ branch_if_negative_32(src_pos, *stub->entry());
2187 break;
2188 case LIR_OpArrayCopy::dst_pos_positive_check:
2189 __ branch_if_negative_32(dst_pos, *stub->entry());
2190 break;
2191 case LIR_OpArrayCopy::length_positive_check:
2192 __ branch_if_negative_32(length, *stub->entry());
2193 break;
2194 case LIR_OpArrayCopy::src_pos_positive_check | LIR_OpArrayCopy::dst_pos_positive_check:
2195 __ branch_if_any_negative_32(src_pos, dst_pos, tmp, *stub->entry());
2196 break;
2197 case LIR_OpArrayCopy::src_pos_positive_check | LIR_OpArrayCopy::length_positive_check:
2198 __ branch_if_any_negative_32(src_pos, length, tmp, *stub->entry());
2199 break;
2200 case LIR_OpArrayCopy::dst_pos_positive_check | LIR_OpArrayCopy::length_positive_check:
2201 __ branch_if_any_negative_32(dst_pos, length, tmp, *stub->entry());
2202 break;
2203 case all_positive_checks:
2204 __ branch_if_any_negative_32(src_pos, dst_pos, length, tmp, *stub->entry());
2205 break;
2206 default:
2207 assert((flags & all_positive_checks) == 0, "the last option");
2208 }
2209
2210 // Range checks
2211 if (flags & LIR_OpArrayCopy::src_range_check) {
2212 __ ldr_s32(tmp2, Address(src, arrayOopDesc::length_offset_in_bytes()));
2213 __ add_32(tmp, src_pos, length);
2214 __ cmp_32(tmp, tmp2);
2215 __ b(*stub->entry(), hi);
2216 }
2217 if (flags & LIR_OpArrayCopy::dst_range_check) {
2218 __ ldr_s32(tmp2, Address(dst, arrayOopDesc::length_offset_in_bytes()));
2219 __ add_32(tmp, dst_pos, length);
2220 __ cmp_32(tmp, tmp2);
2221 __ b(*stub->entry(), hi);
2222 }
2223
2224 // Check if src and dst are of the same type
2225 if (flags & LIR_OpArrayCopy::type_check) {
2226 // We don't know the array types are compatible
2227 if (basic_type != T_OBJECT) {
2228 // Simple test for basic type arrays
2229 if (UseCompressedClassPointers) {
2230 // We don't need decode because we just need to compare
2231 __ ldr_u32(tmp, Address(src, oopDesc::klass_offset_in_bytes()));
2232 __ ldr_u32(tmp2, Address(dst, oopDesc::klass_offset_in_bytes()));
2233 __ cmp_32(tmp, tmp2);
2234 } else {
2235 __ load_klass(tmp, src);
2236 __ load_klass(tmp2, dst);
2237 __ cmp(tmp, tmp2);
2238 }
2239 __ b(*stub->entry(), ne);
2240 } else {
2241 // For object arrays, if src is a sub class of dst then we can
2242 // safely do the copy.
2243 Label cont, slow;
2244
2245 address copyfunc_addr = StubRoutines::checkcast_arraycopy();
2246
2247 __ load_klass(tmp, src);
2248 __ load_klass(tmp2, dst);
2249
2250 // We are at a call so all live registers are saved before we
2251 // get here
2252 assert_different_registers(tmp, tmp2, R6, altFP_7_11);
2253
2254 __ check_klass_subtype_fast_path(tmp, tmp2, R6, altFP_7_11, &cont, copyfunc_addr == NULL ? stub->entry() : &slow, NULL);
2255
2256 __ mov(R6, R0);
2257 __ mov(altFP_7_11, R1);
2258 __ mov(R0, tmp);
2259 __ mov(R1, tmp2);
2260 __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type); // does not blow any registers except R0, LR and Rtemp
2261 __ cmp_32(R0, 0);
2262 __ mov(R0, R6);
2263 __ mov(R1, altFP_7_11);
2264
2265 if (copyfunc_addr != NULL) { // use stub if available
2266 // src is not a sub class of dst so we have to do a
2267 // per-element check.
2268
2269 __ b(cont, ne);
2270
2271 __ bind(slow);
2272
2273 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
2274 if ((flags & mask) != mask) {
2275 // Check that at least both of them object arrays.
2276 assert(flags & mask, "one of the two should be known to be an object array");
2277
2278 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
2279 __ load_klass(tmp, src);
2280 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
2281 __ load_klass(tmp, dst);
2282 }
2283 int lh_offset = in_bytes(Klass::layout_helper_offset());
2284
2285 __ ldr_u32(tmp2, Address(tmp, lh_offset));
2286
2287 jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
2288 __ mov_slow(tmp, objArray_lh);
2289 __ cmp_32(tmp, tmp2);
2290 __ b(*stub->entry(), ne);
2291 }
2292
2293 save_in_reserved_area(R0, R1, R2, R3);
2294
2295 Register src_ptr = R0;
2296 Register dst_ptr = R1;
2297 Register len = R2;
2298 Register chk_off = R3;
2299 Register super_k = tmp;
2300
2301 __ add(src_ptr, src, arrayOopDesc::base_offset_in_bytes(basic_type));
2302 __ add_ptr_scaled_int32(src_ptr, src_ptr, src_pos, shift);
2303
2304 __ add(dst_ptr, dst, arrayOopDesc::base_offset_in_bytes(basic_type));
2305 __ add_ptr_scaled_int32(dst_ptr, dst_ptr, dst_pos, shift);
2306 __ load_klass(tmp, dst);
2307
2308 int ek_offset = in_bytes(ObjArrayKlass::element_klass_offset());
2309 int sco_offset = in_bytes(Klass::super_check_offset_offset());
2310
2311 __ ldr(super_k, Address(tmp, ek_offset));
2312
2313 __ mov(len, length);
2314 __ ldr_u32(chk_off, Address(super_k, sco_offset));
2315 __ push(super_k);
2316
2317 __ call(copyfunc_addr, relocInfo::runtime_call_type);
2318
2319 #ifndef PRODUCT
2320 if (PrintC1Statistics) {
2321 Label failed;
2322 __ cbnz_32(R0, failed);
2323 __ inc_counter((address)&Runtime1::_arraycopy_checkcast_cnt, tmp, tmp2);
2324 __ bind(failed);
2325 }
2326 #endif // PRODUCT
2327
2328 __ add(SP, SP, wordSize); // Drop super_k argument
2329
2330 __ cbz_32(R0, *stub->continuation());
2331 __ mvn_32(tmp, R0);
2332
2333 // load saved arguments in slow case only
2334 restore_from_reserved_area(R0, R1, R2, R3);
2335
2336 __ sub_32(length, length, tmp);
2337 __ add_32(src_pos, src_pos, tmp);
2338 __ add_32(dst_pos, dst_pos, tmp);
2339
2340 #ifndef PRODUCT
2341 if (PrintC1Statistics) {
2342 __ inc_counter((address)&Runtime1::_arraycopy_checkcast_attempt_cnt, tmp, tmp2);
2343 }
2344 #endif
2345
2346 __ b(*stub->entry());
2347
2348 __ bind(cont);
2349 } else {
2350 __ b(*stub->entry(), eq);
2351 __ bind(cont);
2352 }
2353 }
2354 }
2355
2356 #ifndef PRODUCT
2357 if (PrintC1Statistics) {
2358 address counter = Runtime1::arraycopy_count_address(basic_type);
2359 __ inc_counter(counter, tmp, tmp2);
2360 }
2361 #endif // !PRODUCT
2362
2363 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
2364 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
2365 const char *name;
2366 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
2367
2368 Register src_ptr = R0;
2369 Register dst_ptr = R1;
2370 Register len = R2;
2371
2372 __ add(src_ptr, src, arrayOopDesc::base_offset_in_bytes(basic_type));
2373 __ add_ptr_scaled_int32(src_ptr, src_ptr, src_pos, shift);
2374
2375 __ add(dst_ptr, dst, arrayOopDesc::base_offset_in_bytes(basic_type));
2376 __ add_ptr_scaled_int32(dst_ptr, dst_ptr, dst_pos, shift);
2377
2378 __ mov(len, length);
2379
2380 __ call(entry, relocInfo::runtime_call_type);
2381
2382 __ bind(*stub->continuation());
2383 }
2384
2385 #ifdef ASSERT
2386 // emit run-time assertion
2387 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
2388 assert(op->code() == lir_assert, "must be");
2389
2390 if (op->in_opr1()->is_valid()) {
2391 assert(op->in_opr2()->is_valid(), "both operands must be valid");
2392 comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
2393 } else {
2394 assert(op->in_opr2()->is_illegal(), "both operands must be illegal");
2395 assert(op->condition() == lir_cond_always, "no other conditions allowed");
2396 }
2397
2398 Label ok;
2399 if (op->condition() != lir_cond_always) {
2400 AsmCondition acond = al;
2401 switch (op->condition()) {
2402 case lir_cond_equal: acond = eq; break;
2403 case lir_cond_notEqual: acond = ne; break;
2404 case lir_cond_less: acond = lt; break;
2405 case lir_cond_lessEqual: acond = le; break;
2406 case lir_cond_greaterEqual: acond = ge; break;
2407 case lir_cond_greater: acond = gt; break;
2408 case lir_cond_aboveEqual: acond = hs; break;
2409 case lir_cond_belowEqual: acond = ls; break;
2410 default: ShouldNotReachHere();
2411 }
2412 __ b(ok, acond);
2413 }
2414 if (op->halt()) {
2415 const char* str = __ code_string(op->msg());
2416 __ stop(str);
2417 } else {
2418 breakpoint();
2419 }
2420 __ bind(ok);
2421 }
2422 #endif // ASSERT
2423
2424 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
2425 fatal("CRC32 intrinsic is not implemented on this platform");
2426 }
2427
2428 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
2429 Register obj = op->obj_opr()->as_pointer_register();
2430 Register hdr = op->hdr_opr()->as_pointer_register();
2431 Register lock = op->lock_opr()->as_pointer_register();
2432
2433 // TODO: Implement fast-locking.
2434 __ b(*op->stub()->entry());
2435 __ bind(*op->stub()->continuation());
2436 }
2437
2438 void LIR_Assembler::emit_load_klass(LIR_OpLoadKlass* op) {
2439 Register obj = op->obj()->as_pointer_register();
2440 Register result = op->result_opr()->as_pointer_register();
2441
2442 CodeEmitInfo* info = op->info();
2443 if (info != NULL) {
2444 add_debug_info_for_null_check_here(info);
2445 }
2446
2447 if (UseCompressedClassPointers) { // On 32 bit arm??
2448 __ ldr_u32(result, Address(obj, oopDesc::klass_offset_in_bytes()));
2449 } else {
2450 __ ldr(result, Address(obj, oopDesc::klass_offset_in_bytes()));
2451 }
2452 }
2453
2454 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
2455 ciMethod* method = op->profiled_method();
2456 int bci = op->profiled_bci();
2457 ciMethod* callee = op->profiled_callee();
2458
2459 // Update counter for all call types
2460 ciMethodData* md = method->method_data_or_null();
2461 assert(md != NULL, "Sanity");
2462 ciProfileData* data = md->bci_to_data(bci);
2463 assert(data != NULL && data->is_CounterData(), "need CounterData for calls");
2464 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
2465 Register mdo = op->mdo()->as_register();
2466 assert(op->tmp1()->is_register(), "tmp1 must be allocated");
2467 Register tmp1 = op->tmp1()->as_pointer_register();
2468 assert_different_registers(mdo, tmp1);
2469 __ mov_metadata(mdo, md->constant_encoding());
2470 int mdo_offset_bias = 0;
2471 int max_offset = 4096;
2472 if (md->byte_offset_of_slot(data, CounterData::count_offset()) + data->size_in_bytes() >= max_offset) {
2473 // The offset is large so bias the mdo by the base of the slot so
2474 // that the ldr can use an immediate offset to reference the slots of the data
2475 mdo_offset_bias = md->byte_offset_of_slot(data, CounterData::count_offset());
2476 __ mov_slow(tmp1, mdo_offset_bias);
2477 __ add(mdo, mdo, tmp1);
2478 }
2479
2480 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias);
2481 // Perform additional virtual call profiling for invokevirtual and
2482 // invokeinterface bytecodes
2483 if (op->should_profile_receiver_type()) {
2484 assert(op->recv()->is_single_cpu(), "recv must be allocated");
2485 Register recv = op->recv()->as_register();
2486 assert_different_registers(mdo, tmp1, recv);
2487 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
2488 ciKlass* known_klass = op->known_holder();
2489 if (C1OptimizeVirtualCallProfiling && known_klass != NULL) {
2490 // We know the type that will be seen at this call site; we can
2491 // statically update the MethodData* rather than needing to do
2492 // dynamic tests on the receiver type
2493
2494 // NOTE: we should probably put a lock around this search to
2495 // avoid collisions by concurrent compilations
2496 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
2497 uint i;
2498 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2499 ciKlass* receiver = vc_data->receiver(i);
2500 if (known_klass->equals(receiver)) {
2501 Address data_addr(mdo, md->byte_offset_of_slot(data,
2502 VirtualCallData::receiver_count_offset(i)) -
2503 mdo_offset_bias);
2504 __ ldr(tmp1, data_addr);
2505 __ add(tmp1, tmp1, DataLayout::counter_increment);
2506 __ str(tmp1, data_addr);
2507 return;
2508 }
2509 }
2510
2511 // Receiver type not found in profile data; select an empty slot
2512
2513 // Note that this is less efficient than it should be because it
2514 // always does a write to the receiver part of the
2515 // VirtualCallData rather than just the first time
2516 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2517 ciKlass* receiver = vc_data->receiver(i);
2518 if (receiver == NULL) {
2519 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)) -
2520 mdo_offset_bias);
2521 __ mov_metadata(tmp1, known_klass->constant_encoding());
2522 __ str(tmp1, recv_addr);
2523 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) -
2524 mdo_offset_bias);
2525 __ ldr(tmp1, data_addr);
2526 __ add(tmp1, tmp1, DataLayout::counter_increment);
2527 __ str(tmp1, data_addr);
2528 return;
2529 }
2530 }
2531 } else {
2532 __ load_klass(recv, recv);
2533 Label update_done;
2534 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, &update_done);
2535 // Receiver did not match any saved receiver and there is no empty row for it.
2536 // Increment total counter to indicate polymorphic case.
2537 __ ldr(tmp1, counter_addr);
2538 __ add(tmp1, tmp1, DataLayout::counter_increment);
2539 __ str(tmp1, counter_addr);
2540
2541 __ bind(update_done);
2542 }
2543 } else {
2544 // Static call
2545 __ ldr(tmp1, counter_addr);
2546 __ add(tmp1, tmp1, DataLayout::counter_increment);
2547 __ str(tmp1, counter_addr);
2548 }
2549 }
2550
2551 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
2552 fatal("Type profiling not implemented on this platform");
2553 }
2554
2555 void LIR_Assembler::emit_delay(LIR_OpDelay*) {
2556 Unimplemented();
2557 }
2558
2559
2560 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) {
2561 Address mon_addr = frame_map()->address_for_monitor_object(monitor_no);
2562 __ add_slow(dst->as_pointer_register(), mon_addr.base(), mon_addr.disp());
2563 }
2564
2565
2566 void LIR_Assembler::align_backward_branch_target() {
2567 // Some ARM processors do better with 8-byte branch target alignment
2568 __ align(8);
2569 }
2570
2571
2572 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) {
2573 // tmp must be unused
2574 assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2575
2576 if (left->is_single_cpu()) {
2577 assert (dest->type() == T_INT, "unexpected result type");
2578 assert (left->type() == T_INT, "unexpected left type");
2579 __ neg_32(dest->as_register(), left->as_register());
2580 } else if (left->is_double_cpu()) {
2581 Register dest_lo = dest->as_register_lo();
2582 Register dest_hi = dest->as_register_hi();
2583 Register src_lo = left->as_register_lo();
2584 Register src_hi = left->as_register_hi();
2585 if (dest_lo == src_hi) {
2586 dest_lo = Rtemp;
2587 }
2588 __ rsbs(dest_lo, src_lo, 0);
2589 __ rsc(dest_hi, src_hi, 0);
2590 move_regs(dest_lo, dest->as_register_lo());
2591 } else if (left->is_single_fpu()) {
2592 __ neg_float(dest->as_float_reg(), left->as_float_reg());
2593 } else if (left->is_double_fpu()) {
2594 __ neg_double(dest->as_double_reg(), left->as_double_reg());
2595 } else {
2596 ShouldNotReachHere();
2597 }
2598 }
2599
2600
2601 void LIR_Assembler::leal(LIR_Opr addr_opr, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
2602 assert(patch_code == lir_patch_none, "Patch code not supported");
2603 LIR_Address* addr = addr_opr->as_address_ptr();
2604 if (addr->index()->is_illegal()) {
2605 jint c = addr->disp();
2606 if (!Assembler::is_arith_imm_in_range(c)) {
2607 BAILOUT("illegal arithmetic operand");
2608 }
2609 __ add(dest->as_pointer_register(), addr->base()->as_pointer_register(), c);
2610 } else {
2611 assert(addr->disp() == 0, "cannot handle otherwise");
2612 __ add(dest->as_pointer_register(), addr->base()->as_pointer_register(),
2613 AsmOperand(addr->index()->as_pointer_register(), lsl, addr->scale()));
2614 }
2615 }
2616
2617
2618 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
2619 assert(!tmp->is_valid(), "don't need temporary");
2620 __ call(dest);
2621 if (info != NULL) {
2622 add_call_info_here(info);
2623 }
2624 }
2625
2626
2627 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
2628 assert(src->is_double_cpu() && dest->is_address() ||
2629 src->is_address() && dest->is_double_cpu(),
2630 "Simple move_op is called for all other cases");
2631
2632 int null_check_offset;
2633 if (dest->is_address()) {
2634 // Store
2635 const LIR_Address* addr = dest->as_address_ptr();
2636 const Register src_lo = src->as_register_lo();
2637 const Register src_hi = src->as_register_hi();
2638 assert(addr->index()->is_illegal() && addr->disp() == 0, "The address is simple already");
2639
2640 if (src_lo < src_hi) {
2641 null_check_offset = __ offset();
2642 __ stmia(addr->base()->as_register(), RegisterSet(src_lo) | RegisterSet(src_hi));
2643 } else {
2644 assert(src_lo < Rtemp, "Rtemp is higher than any allocatable register");
2645 __ mov(Rtemp, src_hi);
2646 null_check_offset = __ offset();
2647 __ stmia(addr->base()->as_register(), RegisterSet(src_lo) | RegisterSet(Rtemp));
2648 }
2649 } else {
2650 // Load
2651 const LIR_Address* addr = src->as_address_ptr();
2652 const Register dest_lo = dest->as_register_lo();
2653 const Register dest_hi = dest->as_register_hi();
2654 assert(addr->index()->is_illegal() && addr->disp() == 0, "The address is simple already");
2655
2656 null_check_offset = __ offset();
2657 if (dest_lo < dest_hi) {
2658 __ ldmia(addr->base()->as_register(), RegisterSet(dest_lo) | RegisterSet(dest_hi));
2659 } else {
2660 assert(dest_lo < Rtemp, "Rtemp is higher than any allocatable register");
2661 __ ldmia(addr->base()->as_register(), RegisterSet(dest_lo) | RegisterSet(Rtemp));
2662 __ mov(dest_hi, Rtemp);
2663 }
2664 }
2665
2666 if (info != NULL) {
2667 add_debug_info_for_null_check(null_check_offset, info);
2668 }
2669 }
2670
2671
2672 void LIR_Assembler::membar() {
2673 __ membar(MacroAssembler::StoreLoad, Rtemp);
2674 }
2675
2676 void LIR_Assembler::membar_acquire() {
2677 __ membar(MacroAssembler::Membar_mask_bits(MacroAssembler::LoadLoad | MacroAssembler::LoadStore), Rtemp);
2678 }
2679
2680 void LIR_Assembler::membar_release() {
2681 __ membar(MacroAssembler::Membar_mask_bits(MacroAssembler::StoreStore | MacroAssembler::LoadStore), Rtemp);
2682 }
2683
2684 void LIR_Assembler::membar_loadload() {
2685 __ membar(MacroAssembler::LoadLoad, Rtemp);
2686 }
2687
2688 void LIR_Assembler::membar_storestore() {
2689 __ membar(MacroAssembler::StoreStore, Rtemp);
2690 }
2691
2692 void LIR_Assembler::membar_loadstore() {
2693 __ membar(MacroAssembler::LoadStore, Rtemp);
2694 }
2695
2696 void LIR_Assembler::membar_storeload() {
2697 __ membar(MacroAssembler::StoreLoad, Rtemp);
2698 }
2699
2700 void LIR_Assembler::on_spin_wait() {
2701 Unimplemented();
2702 }
2703
2704 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
2705 // Not used on ARM
2706 Unimplemented();
2707 }
2708
2709 void LIR_Assembler::peephole(LIR_List* lir) {
2710 LIR_OpList* inst = lir->instructions_list();
2711 const int inst_length = inst->length();
2712 for (int i = 0; i < inst_length; i++) {
2713 LIR_Op* op = inst->at(i);
2714 switch (op->code()) {
2715 case lir_cmp: {
2716 // Replace:
2717 // cmp rX, y
2718 // cmove [EQ] y, z, rX
2719 // with
2720 // cmp rX, y
2721 // cmove [EQ] illegalOpr, z, rX
2722 //
2723 // or
2724 // cmp rX, y
2725 // cmove [NE] z, y, rX
2726 // with
2727 // cmp rX, y
2728 // cmove [NE] z, illegalOpr, rX
2729 //
2730 // moves from illegalOpr should be removed when converting LIR to native assembly
2731
2732 LIR_Op2* cmp = op->as_Op2();
2733 assert(cmp != NULL, "cmp LIR instruction is not an op2");
2734
2735 if (i + 1 < inst_length) {
2736 LIR_Op2* cmove = inst->at(i + 1)->as_Op2();
2737 if (cmove != NULL && cmove->code() == lir_cmove) {
2738 LIR_Opr cmove_res = cmove->result_opr();
2739 bool res_is_op1 = cmove_res == cmp->in_opr1();
2740 bool res_is_op2 = cmove_res == cmp->in_opr2();
2741 LIR_Opr cmp_res, cmp_arg;
2742 if (res_is_op1) {
2743 cmp_res = cmp->in_opr1();
2744 cmp_arg = cmp->in_opr2();
2745 } else if (res_is_op2) {
2746 cmp_res = cmp->in_opr2();
2747 cmp_arg = cmp->in_opr1();
2748 } else {
2749 cmp_res = LIR_OprFact::illegalOpr;
2750 cmp_arg = LIR_OprFact::illegalOpr;
2751 }
2752
2753 if (cmp_res != LIR_OprFact::illegalOpr) {
2754 LIR_Condition cond = cmove->condition();
2755 if (cond == lir_cond_equal && cmove->in_opr1() == cmp_arg) {
2756 cmove->set_in_opr1(LIR_OprFact::illegalOpr);
2757 } else if (cond == lir_cond_notEqual && cmove->in_opr2() == cmp_arg) {
2758 cmove->set_in_opr2(LIR_OprFact::illegalOpr);
2759 }
2760 }
2761 }
2762 }
2763 break;
2764 }
2765
2766 default:
2767 break;
2768 }
2769 }
2770 }
2771
2772 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) {
2773 assert(src->is_address(), "sanity");
2774 Address addr = as_Address(src->as_address_ptr());
2775
2776 if (code == lir_xchg) {
2777 } else {
2778 assert (!data->is_oop(), "xadd for oops");
2779 }
2780
2781 __ membar(MacroAssembler::Membar_mask_bits(MacroAssembler::StoreStore | MacroAssembler::LoadStore), Rtemp);
2782
2783 Label retry;
2784 __ bind(retry);
2785
2786 if (data->type() == T_INT || data->is_oop()) {
2787 Register dst = dest->as_register();
2788 Register new_val = noreg;
2789 __ ldrex(dst, addr);
2790 if (code == lir_xadd) {
2791 Register tmp_reg = tmp->as_register();
2792 if (data->is_constant()) {
2793 assert_different_registers(dst, tmp_reg);
2794 __ add_32(tmp_reg, dst, data->as_constant_ptr()->as_jint());
2795 } else {
2796 assert_different_registers(dst, tmp_reg, data->as_register());
2797 __ add_32(tmp_reg, dst, data->as_register());
2798 }
2799 new_val = tmp_reg;
2800 } else {
2801 if (UseCompressedOops && data->is_oop()) {
2802 new_val = tmp->as_pointer_register();
2803 } else {
2804 new_val = data->as_register();
2805 }
2806 assert_different_registers(dst, new_val);
2807 }
2808 __ strex(Rtemp, new_val, addr);
2809
2810 } else if (data->type() == T_LONG) {
2811 Register dst_lo = dest->as_register_lo();
2812 Register new_val_lo = noreg;
2813 Register dst_hi = dest->as_register_hi();
2814
2815 assert(dst_hi->encoding() == dst_lo->encoding() + 1, "non aligned register pair");
2816 assert((dst_lo->encoding() & 0x1) == 0, "misaligned register pair");
2817
2818 __ bind(retry);
2819 __ ldrexd(dst_lo, addr);
2820 if (code == lir_xadd) {
2821 Register tmp_lo = tmp->as_register_lo();
2822 Register tmp_hi = tmp->as_register_hi();
2823
2824 assert(tmp_hi->encoding() == tmp_lo->encoding() + 1, "non aligned register pair");
2825 assert((tmp_lo->encoding() & 0x1) == 0, "misaligned register pair");
2826
2827 if (data->is_constant()) {
2828 jlong c = data->as_constant_ptr()->as_jlong();
2829 assert((jlong)((jint)c) == c, "overflow");
2830 assert_different_registers(dst_lo, dst_hi, tmp_lo, tmp_hi);
2831 __ adds(tmp_lo, dst_lo, (jint)c);
2832 __ adc(tmp_hi, dst_hi, 0);
2833 } else {
2834 Register new_val_lo = data->as_register_lo();
2835 Register new_val_hi = data->as_register_hi();
2836 __ adds(tmp_lo, dst_lo, new_val_lo);
2837 __ adc(tmp_hi, dst_hi, new_val_hi);
2838 assert_different_registers(dst_lo, dst_hi, tmp_lo, tmp_hi, new_val_lo, new_val_hi);
2839 }
2840 new_val_lo = tmp_lo;
2841 } else {
2842 new_val_lo = data->as_register_lo();
2843 Register new_val_hi = data->as_register_hi();
2844
2845 assert_different_registers(dst_lo, dst_hi, new_val_lo, new_val_hi);
2846 assert(new_val_hi->encoding() == new_val_lo->encoding() + 1, "non aligned register pair");
2847 assert((new_val_lo->encoding() & 0x1) == 0, "misaligned register pair");
2848 }
2849 __ strexd(Rtemp, new_val_lo, addr);
2850 } else {
2851 ShouldNotReachHere();
2852 }
2853
2854 __ cbnz_32(Rtemp, retry);
2855 __ membar(MacroAssembler::Membar_mask_bits(MacroAssembler::StoreLoad | MacroAssembler::StoreStore), Rtemp);
2856
2857 }
2858
2859 #undef __