1 /*
   2  * Copyright (c) 2000, 2022, Oracle and/or its affiliates. All rights reserved.
   3  * Copyright (c) 2012, 2021 SAP SE. All rights reserved.
   4  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   5  *
   6  * This code is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 only, as
   8  * published by the Free Software Foundation.
   9  *
  10  * This code is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  * version 2 for more details (a copy is included in the LICENSE file that
  14  * accompanied this code).
  15  *
  16  * You should have received a copy of the GNU General Public License version
  17  * 2 along with this work; if not, write to the Free Software Foundation,
  18  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  19  *
  20  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  21  * or visit www.oracle.com if you need additional information or have any
  22  * questions.
  23  *
  24  */
  25 
  26 #include "precompiled.hpp"
  27 #include "asm/macroAssembler.inline.hpp"
  28 #include "c1/c1_Compilation.hpp"
  29 #include "c1/c1_LIRAssembler.hpp"
  30 #include "c1/c1_MacroAssembler.hpp"
  31 #include "c1/c1_Runtime1.hpp"
  32 #include "c1/c1_ValueStack.hpp"
  33 #include "ci/ciArrayKlass.hpp"
  34 #include "ci/ciInstance.hpp"
  35 #include "gc/shared/collectedHeap.hpp"
  36 #include "memory/universe.hpp"
  37 #include "nativeInst_ppc.hpp"
  38 #include "oops/compressedOops.hpp"
  39 #include "oops/objArrayKlass.hpp"
  40 #include "runtime/frame.inline.hpp"
  41 #include "runtime/os.inline.hpp"
  42 #include "runtime/safepointMechanism.inline.hpp"
  43 #include "runtime/sharedRuntime.hpp"
  44 #include "runtime/stubRoutines.hpp"
  45 #include "runtime/vm_version.hpp"
  46 #include "utilities/macros.hpp"
  47 #include "utilities/powerOfTwo.hpp"
  48 
  49 #define __ _masm->
  50 
  51 
  52 const ConditionRegister LIR_Assembler::BOOL_RESULT = CCR5;
  53 
  54 
  55 bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
  56   Unimplemented(); return false; // Currently not used on this platform.
  57 }
  58 
  59 
  60 LIR_Opr LIR_Assembler::receiverOpr() {
  61   return FrameMap::R3_oop_opr;
  62 }
  63 
  64 
  65 LIR_Opr LIR_Assembler::osrBufferPointer() {
  66   return FrameMap::R3_opr;
  67 }
  68 
  69 
  70 // This specifies the stack pointer decrement needed to build the frame.
  71 int LIR_Assembler::initial_frame_size_in_bytes() const {
  72   return in_bytes(frame_map()->framesize_in_bytes());
  73 }
  74 
  75 
  76 // Inline cache check: the inline cached class is in inline_cache_reg;
  77 // we fetch the class of the receiver and compare it with the cached class.
  78 // If they do not match we jump to slow case.
  79 int LIR_Assembler::check_icache() {
  80   int offset = __ offset();
  81   __ inline_cache_check(R3_ARG1, R19_inline_cache_reg);
  82   return offset;
  83 }
  84 
  85 void LIR_Assembler::clinit_barrier(ciMethod* method) {
  86   assert(!method->holder()->is_not_initialized(), "initialization should have been started");
  87 
  88   Label L_skip_barrier;
  89   Register klass = R20;
  90 
  91   metadata2reg(method->holder()->constant_encoding(), klass);
  92   __ clinit_barrier(klass, R16_thread, &L_skip_barrier /*L_fast_path*/);
  93 
  94   __ load_const_optimized(klass, SharedRuntime::get_handle_wrong_method_stub(), R0);
  95   __ mtctr(klass);
  96   __ bctr();
  97 
  98   __ bind(L_skip_barrier);
  99 }
 100 
 101 void LIR_Assembler::osr_entry() {
 102   // On-stack-replacement entry sequence:
 103   //
 104   //   1. Create a new compiled activation.
 105   //   2. Initialize local variables in the compiled activation. The expression
 106   //      stack must be empty at the osr_bci; it is not initialized.
 107   //   3. Jump to the continuation address in compiled code to resume execution.
 108 
 109   // OSR entry point
 110   offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
 111   BlockBegin* osr_entry = compilation()->hir()->osr_entry();
 112   ValueStack* entry_state = osr_entry->end()->state();
 113   int number_of_locks = entry_state->locks_size();
 114 
 115   // Create a frame for the compiled activation.
 116   __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
 117 
 118   // OSR buffer is
 119   //
 120   // locals[nlocals-1..0]
 121   // monitors[number_of_locks-1..0]
 122   //
 123   // Locals is a direct copy of the interpreter frame so in the osr buffer
 124   // the first slot in the local array is the last local from the interpreter
 125   // and the last slot is local[0] (receiver) from the interpreter.
 126   //
 127   // Similarly with locks. The first lock slot in the osr buffer is the nth lock
 128   // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
 129   // in the interpreter frame (the method lock if a sync method).
 130 
 131   // Initialize monitors in the compiled activation.
 132   //   R3: pointer to osr buffer
 133   //
 134   // All other registers are dead at this point and the locals will be
 135   // copied into place by code emitted in the IR.
 136 
 137   Register OSR_buf = osrBufferPointer()->as_register();
 138   { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
 139     int monitor_offset = BytesPerWord * method()->max_locals() +
 140       BytesPerWord * (number_of_locks - 1);
 141     for (int i = 0; i < number_of_locks; i++) {
 142       int slot_offset = monitor_offset - (i * BytesPerWord);
 143 #ifdef ASSERT
 144       // Verify the interpreter's monitor has a non-null object.
 145       {
 146         Label L;
 147         __ ld(R0, slot_offset + 1*BytesPerWord, OSR_buf);
 148         __ cmpdi(CCR0, R0, 0);
 149         __ bne(CCR0, L);
 150         __ stop("locked object is NULL");
 151         __ bind(L);
 152       }
 153 #endif // ASSERT
 154       // Copy the lock field into the compiled activation.
 155       Address mo = frame_map()->address_for_monitor_object(i);
 156       assert(mo.index() == noreg, "sanity");
 157       __ ld(R0, slot_offset + 0, OSR_buf);
 158       __ std(R0, mo.disp(), mo.base());
 159     }
 160   }
 161 }
 162 
 163 
 164 int LIR_Assembler::emit_exception_handler() {
 165   // Generate code for the exception handler.
 166   address handler_base = __ start_a_stub(exception_handler_size());
 167 
 168   if (handler_base == NULL) {
 169     // Not enough space left for the handler.
 170     bailout("exception handler overflow");
 171     return -1;
 172   }
 173 
 174   int offset = code_offset();
 175   address entry_point = CAST_FROM_FN_PTR(address, Runtime1::entry_for(Runtime1::handle_exception_from_callee_id));
 176   //__ load_const_optimized(R0, entry_point);
 177   __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(entry_point));
 178   __ mtctr(R0);
 179   __ bctr();
 180 
 181   guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
 182   __ end_a_stub();
 183 
 184   return offset;
 185 }
 186 
 187 
 188 // Emit the code to remove the frame from the stack in the exception
 189 // unwind path.
 190 int LIR_Assembler::emit_unwind_handler() {
 191   _masm->block_comment("Unwind handler");
 192 
 193   int offset = code_offset();
 194   bool preserve_exception = method()->is_synchronized() || compilation()->env()->dtrace_method_probes();
 195   const Register Rexception = R3 /*LIRGenerator::exceptionOopOpr()*/, Rexception_save = R31;
 196 
 197   // Fetch the exception from TLS and clear out exception related thread state.
 198   __ ld(Rexception, in_bytes(JavaThread::exception_oop_offset()), R16_thread);
 199   __ li(R0, 0);
 200   __ std(R0, in_bytes(JavaThread::exception_oop_offset()), R16_thread);
 201   __ std(R0, in_bytes(JavaThread::exception_pc_offset()), R16_thread);
 202 
 203   __ bind(_unwind_handler_entry);
 204   __ verify_not_null_oop(Rexception);
 205   if (preserve_exception) { __ mr(Rexception_save, Rexception); }
 206 
 207   // Perform needed unlocking
 208   MonitorExitStub* stub = NULL;
 209   if (method()->is_synchronized()) {
 210     monitor_address(0, FrameMap::R4_opr);
 211     __ ld(R4, BasicObjectLock::obj_offset_in_bytes(), R4);
 212     stub = new MonitorExitStub(FrameMap::R4_opr);
 213     __ b(*stub->entry());
 214     __ bind(*stub->continuation());
 215   }
 216 
 217   if (compilation()->env()->dtrace_method_probes()) {
 218     Unimplemented();
 219   }
 220 
 221   // Dispatch to the unwind logic.
 222   address unwind_stub = Runtime1::entry_for(Runtime1::unwind_exception_id);
 223   //__ load_const_optimized(R0, unwind_stub);
 224   __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(unwind_stub));
 225   if (preserve_exception) { __ mr(Rexception, Rexception_save); }
 226   __ mtctr(R0);
 227   __ bctr();
 228 
 229   // Emit the slow path assembly.
 230   if (stub != NULL) {
 231     stub->emit_code(this);
 232   }
 233 
 234   return offset;
 235 }
 236 
 237 
 238 int LIR_Assembler::emit_deopt_handler() {
 239   // Generate code for deopt handler.
 240   address handler_base = __ start_a_stub(deopt_handler_size());
 241 
 242   if (handler_base == NULL) {
 243     // Not enough space left for the handler.
 244     bailout("deopt handler overflow");
 245     return -1;
 246   }
 247 
 248   int offset = code_offset();
 249   __ bl64_patchable(SharedRuntime::deopt_blob()->unpack(), relocInfo::runtime_call_type);
 250 
 251   guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
 252   __ end_a_stub();
 253 
 254   return offset;
 255 }
 256 
 257 
 258 void LIR_Assembler::jobject2reg(jobject o, Register reg) {
 259   if (o == NULL) {
 260     __ li(reg, 0);
 261   } else {
 262     AddressLiteral addrlit = __ constant_oop_address(o);
 263     __ load_const(reg, addrlit, (reg != R0) ? R0 : noreg);
 264   }
 265 }
 266 
 267 
 268 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) {
 269   // Allocate a new index in table to hold the object once it's been patched.
 270   int oop_index = __ oop_recorder()->allocate_oop_index(NULL);
 271   PatchingStub* patch = new PatchingStub(_masm, patching_id(info), oop_index);
 272 
 273   AddressLiteral addrlit((address)NULL, oop_Relocation::spec(oop_index));
 274   __ load_const(reg, addrlit, R0);
 275 
 276   patching_epilog(patch, lir_patch_normal, reg, info);
 277 }
 278 
 279 
 280 void LIR_Assembler::metadata2reg(Metadata* o, Register reg) {
 281   AddressLiteral md = __ constant_metadata_address(o); // Notify OOP recorder (don't need the relocation)
 282   __ load_const_optimized(reg, md.value(), (reg != R0) ? R0 : noreg);
 283 }
 284 
 285 
 286 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo *info) {
 287   // Allocate a new index in table to hold the klass once it's been patched.
 288   int index = __ oop_recorder()->allocate_metadata_index(NULL);
 289   PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id, index);
 290 
 291   AddressLiteral addrlit((address)NULL, metadata_Relocation::spec(index));
 292   assert(addrlit.rspec().type() == relocInfo::metadata_type, "must be an metadata reloc");
 293   __ load_const(reg, addrlit, R0);
 294 
 295   patching_epilog(patch, lir_patch_normal, reg, info);
 296 }
 297 
 298 
 299 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) {
 300   const bool is_int = result->is_single_cpu();
 301   Register Rdividend = is_int ? left->as_register() : left->as_register_lo();
 302   Register Rdivisor  = noreg;
 303   Register Rscratch  = temp->as_register();
 304   Register Rresult   = is_int ? result->as_register() : result->as_register_lo();
 305   long divisor = -1;
 306 
 307   if (right->is_register()) {
 308     Rdivisor = is_int ? right->as_register() : right->as_register_lo();
 309   } else {
 310     divisor = is_int ? right->as_constant_ptr()->as_jint()
 311                      : right->as_constant_ptr()->as_jlong();
 312   }
 313 
 314   assert(Rdividend != Rscratch, "");
 315   assert(Rdivisor  != Rscratch, "");
 316   assert(code == lir_idiv || code == lir_irem, "Must be irem or idiv");
 317 
 318   if (Rdivisor == noreg) {
 319     if (divisor == 1) { // stupid, but can happen
 320       if (code == lir_idiv) {
 321         __ mr_if_needed(Rresult, Rdividend);
 322       } else {
 323         __ li(Rresult, 0);
 324       }
 325 
 326     } else if (is_power_of_2(divisor)) {
 327       // Convert division by a power of two into some shifts and logical operations.
 328       int log2 = log2i_exact(divisor);
 329 
 330       // Round towards 0.
 331       if (divisor == 2) {
 332         if (is_int) {
 333           __ srwi(Rscratch, Rdividend, 31);
 334         } else {
 335           __ srdi(Rscratch, Rdividend, 63);
 336         }
 337       } else {
 338         if (is_int) {
 339           __ srawi(Rscratch, Rdividend, 31);
 340         } else {
 341           __ sradi(Rscratch, Rdividend, 63);
 342         }
 343         __ clrldi(Rscratch, Rscratch, 64-log2);
 344       }
 345       __ add(Rscratch, Rdividend, Rscratch);
 346 
 347       if (code == lir_idiv) {
 348         if (is_int) {
 349           __ srawi(Rresult, Rscratch, log2);
 350         } else {
 351           __ sradi(Rresult, Rscratch, log2);
 352         }
 353       } else { // lir_irem
 354         __ clrrdi(Rscratch, Rscratch, log2);
 355         __ sub(Rresult, Rdividend, Rscratch);
 356       }
 357 
 358     } else if (divisor == -1) {
 359       if (code == lir_idiv) {
 360         __ neg(Rresult, Rdividend);
 361       } else {
 362         __ li(Rresult, 0);
 363       }
 364 
 365     } else {
 366       __ load_const_optimized(Rscratch, divisor);
 367       if (code == lir_idiv) {
 368         if (is_int) {
 369           __ divw(Rresult, Rdividend, Rscratch); // Can't divide minint/-1.
 370         } else {
 371           __ divd(Rresult, Rdividend, Rscratch); // Can't divide minint/-1.
 372         }
 373       } else {
 374         assert(Rscratch != R0, "need both");
 375         if (is_int) {
 376           __ divw(R0, Rdividend, Rscratch); // Can't divide minint/-1.
 377           __ mullw(Rscratch, R0, Rscratch);
 378         } else {
 379           __ divd(R0, Rdividend, Rscratch); // Can't divide minint/-1.
 380           __ mulld(Rscratch, R0, Rscratch);
 381         }
 382         __ sub(Rresult, Rdividend, Rscratch);
 383       }
 384 
 385     }
 386     return;
 387   }
 388 
 389   Label regular, done;
 390   if (is_int) {
 391     __ cmpwi(CCR0, Rdivisor, -1);
 392   } else {
 393     __ cmpdi(CCR0, Rdivisor, -1);
 394   }
 395   __ bne(CCR0, regular);
 396   if (code == lir_idiv) {
 397     __ neg(Rresult, Rdividend);
 398     __ b(done);
 399     __ bind(regular);
 400     if (is_int) {
 401       __ divw(Rresult, Rdividend, Rdivisor); // Can't divide minint/-1.
 402     } else {
 403       __ divd(Rresult, Rdividend, Rdivisor); // Can't divide minint/-1.
 404     }
 405   } else { // lir_irem
 406     __ li(Rresult, 0);
 407     __ b(done);
 408     __ bind(regular);
 409     if (is_int) {
 410       __ divw(Rscratch, Rdividend, Rdivisor); // Can't divide minint/-1.
 411       __ mullw(Rscratch, Rscratch, Rdivisor);
 412     } else {
 413       __ divd(Rscratch, Rdividend, Rdivisor); // Can't divide minint/-1.
 414       __ mulld(Rscratch, Rscratch, Rdivisor);
 415     }
 416     __ sub(Rresult, Rdividend, Rscratch);
 417   }
 418   __ bind(done);
 419 }
 420 
 421 
 422 void LIR_Assembler::emit_op3(LIR_Op3* op) {
 423   switch (op->code()) {
 424   case lir_idiv:
 425   case lir_irem:
 426     arithmetic_idiv(op->code(), op->in_opr1(), op->in_opr2(), op->in_opr3(),
 427                     op->result_opr(), op->info());
 428     break;
 429   case lir_fmad:
 430     __ fmadd(op->result_opr()->as_double_reg(), op->in_opr1()->as_double_reg(),
 431              op->in_opr2()->as_double_reg(), op->in_opr3()->as_double_reg());
 432     break;
 433   case lir_fmaf:
 434     __ fmadds(op->result_opr()->as_float_reg(), op->in_opr1()->as_float_reg(),
 435               op->in_opr2()->as_float_reg(), op->in_opr3()->as_float_reg());
 436     break;
 437   default: ShouldNotReachHere(); break;
 438   }
 439 }
 440 
 441 
 442 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
 443 #ifdef ASSERT
 444   assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label");
 445   if (op->block() != NULL)  _branch_target_blocks.append(op->block());
 446   if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock());
 447   assert(op->info() == NULL, "shouldn't have CodeEmitInfo");
 448 #endif
 449 
 450   Label *L = op->label();
 451   if (op->cond() == lir_cond_always) {
 452     __ b(*L);
 453   } else {
 454     Label done;
 455     bool is_unordered = false;
 456     if (op->code() == lir_cond_float_branch) {
 457       assert(op->ublock() != NULL, "must have unordered successor");
 458       is_unordered = true;
 459     } else {
 460       assert(op->code() == lir_branch, "just checking");
 461     }
 462 
 463     bool positive = false;
 464     Assembler::Condition cond = Assembler::equal;
 465     switch (op->cond()) {
 466       case lir_cond_equal:        positive = true ; cond = Assembler::equal  ; is_unordered = false; break;
 467       case lir_cond_notEqual:     positive = false; cond = Assembler::equal  ; is_unordered = false; break;
 468       case lir_cond_less:         positive = true ; cond = Assembler::less   ; break;
 469       case lir_cond_belowEqual:   assert(op->code() != lir_cond_float_branch, ""); // fallthru
 470       case lir_cond_lessEqual:    positive = false; cond = Assembler::greater; break;
 471       case lir_cond_greater:      positive = true ; cond = Assembler::greater; break;
 472       case lir_cond_aboveEqual:   assert(op->code() != lir_cond_float_branch, ""); // fallthru
 473       case lir_cond_greaterEqual: positive = false; cond = Assembler::less   ; break;
 474       default:                    ShouldNotReachHere();
 475     }
 476     int bo = positive ? Assembler::bcondCRbiIs1 : Assembler::bcondCRbiIs0;
 477     int bi = Assembler::bi0(BOOL_RESULT, cond);
 478     if (is_unordered) {
 479       if (positive) {
 480         if (op->ublock() == op->block()) {
 481           __ bc_far_optimized(Assembler::bcondCRbiIs1, __ bi0(BOOL_RESULT, Assembler::summary_overflow), *L);
 482         }
 483       } else {
 484         if (op->ublock() != op->block()) { __ bso(BOOL_RESULT, done); }
 485       }
 486     }
 487     __ bc_far_optimized(bo, bi, *L);
 488     __ bind(done);
 489   }
 490 }
 491 
 492 
 493 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
 494   Bytecodes::Code code = op->bytecode();
 495   LIR_Opr src = op->in_opr(),
 496           dst = op->result_opr();
 497 
 498   switch(code) {
 499     case Bytecodes::_i2l: {
 500       __ extsw(dst->as_register_lo(), src->as_register());
 501       break;
 502     }
 503     case Bytecodes::_l2i: {
 504       __ mr_if_needed(dst->as_register(), src->as_register_lo()); // high bits are garbage
 505       break;
 506     }
 507     case Bytecodes::_i2b: {
 508       __ extsb(dst->as_register(), src->as_register());
 509       break;
 510     }
 511     case Bytecodes::_i2c: {
 512       __ clrldi(dst->as_register(), src->as_register(), 64-16);
 513       break;
 514     }
 515     case Bytecodes::_i2s: {
 516       __ extsh(dst->as_register(), src->as_register());
 517       break;
 518     }
 519     case Bytecodes::_i2d:
 520     case Bytecodes::_l2d: {
 521       bool src_in_memory = !VM_Version::has_mtfprd();
 522       FloatRegister rdst = dst->as_double_reg();
 523       FloatRegister rsrc;
 524       if (src_in_memory) {
 525         rsrc = src->as_double_reg(); // via mem
 526       } else {
 527         // move src to dst register
 528         if (code == Bytecodes::_i2d) {
 529           __ mtfprwa(rdst, src->as_register());
 530         } else {
 531           __ mtfprd(rdst, src->as_register_lo());
 532         }
 533         rsrc = rdst;
 534       }
 535       __ fcfid(rdst, rsrc);
 536       break;
 537     }
 538     case Bytecodes::_i2f:
 539     case Bytecodes::_l2f: {
 540       bool src_in_memory = !VM_Version::has_mtfprd();
 541       FloatRegister rdst = dst->as_float_reg();
 542       FloatRegister rsrc;
 543       if (src_in_memory) {
 544         rsrc = src->as_double_reg(); // via mem
 545       } else {
 546         // move src to dst register
 547         if (code == Bytecodes::_i2f) {
 548           __ mtfprwa(rdst, src->as_register());
 549         } else {
 550           __ mtfprd(rdst, src->as_register_lo());
 551         }
 552         rsrc = rdst;
 553       }
 554       if (VM_Version::has_fcfids()) {
 555         __ fcfids(rdst, rsrc);
 556       } else {
 557         assert(code == Bytecodes::_i2f, "fcfid+frsp needs fixup code to avoid rounding incompatibility");
 558         __ fcfid(rdst, rsrc);
 559         __ frsp(rdst, rdst);
 560       }
 561       break;
 562     }
 563     case Bytecodes::_f2d: {
 564       __ fmr_if_needed(dst->as_double_reg(), src->as_float_reg());
 565       break;
 566     }
 567     case Bytecodes::_d2f: {
 568       __ frsp(dst->as_float_reg(), src->as_double_reg());
 569       break;
 570     }
 571     case Bytecodes::_d2i:
 572     case Bytecodes::_f2i: {
 573       bool dst_in_memory = !VM_Version::has_mtfprd();
 574       FloatRegister rsrc = (code == Bytecodes::_d2i) ? src->as_double_reg() : src->as_float_reg();
 575       Address       addr = dst_in_memory ? frame_map()->address_for_slot(dst->double_stack_ix()) : NULL;
 576       Label L;
 577       // Result must be 0 if value is NaN; test by comparing value to itself.
 578       __ fcmpu(CCR0, rsrc, rsrc);
 579       if (dst_in_memory) {
 580         __ li(R0, 0); // 0 in case of NAN
 581         __ std(R0, addr.disp(), addr.base());
 582       } else {
 583         __ li(dst->as_register(), 0);
 584       }
 585       __ bso(CCR0, L);
 586       __ fctiwz(rsrc, rsrc); // USE_KILL
 587       if (dst_in_memory) {
 588         __ stfd(rsrc, addr.disp(), addr.base());
 589       } else {
 590         __ mffprd(dst->as_register(), rsrc);
 591       }
 592       __ bind(L);
 593       break;
 594     }
 595     case Bytecodes::_d2l:
 596     case Bytecodes::_f2l: {
 597       bool dst_in_memory = !VM_Version::has_mtfprd();
 598       FloatRegister rsrc = (code == Bytecodes::_d2l) ? src->as_double_reg() : src->as_float_reg();
 599       Address       addr = dst_in_memory ? frame_map()->address_for_slot(dst->double_stack_ix()) : NULL;
 600       Label L;
 601       // Result must be 0 if value is NaN; test by comparing value to itself.
 602       __ fcmpu(CCR0, rsrc, rsrc);
 603       if (dst_in_memory) {
 604         __ li(R0, 0); // 0 in case of NAN
 605         __ std(R0, addr.disp(), addr.base());
 606       } else {
 607         __ li(dst->as_register_lo(), 0);
 608       }
 609       __ bso(CCR0, L);
 610       __ fctidz(rsrc, rsrc); // USE_KILL
 611       if (dst_in_memory) {
 612         __ stfd(rsrc, addr.disp(), addr.base());
 613       } else {
 614         __ mffprd(dst->as_register_lo(), rsrc);
 615       }
 616       __ bind(L);
 617       break;
 618     }
 619 
 620     default: ShouldNotReachHere();
 621   }
 622 }
 623 
 624 
 625 void LIR_Assembler::align_call(LIR_Code) {
 626   // do nothing since all instructions are word aligned on ppc
 627 }
 628 
 629 
 630 bool LIR_Assembler::emit_trampoline_stub_for_call(address target, Register Rtoc) {
 631   int start_offset = __ offset();
 632   // Put the entry point as a constant into the constant pool.
 633   const address entry_point_toc_addr   = __ address_constant(target, RelocationHolder::none);
 634   if (entry_point_toc_addr == NULL) {
 635     bailout("const section overflow");
 636     return false;
 637   }
 638   const int     entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr);
 639 
 640   // Emit the trampoline stub which will be related to the branch-and-link below.
 641   address stub = __ emit_trampoline_stub(entry_point_toc_offset, start_offset, Rtoc);
 642   if (!stub) {
 643     bailout("no space for trampoline stub");
 644     return false;
 645   }
 646   return true;
 647 }
 648 
 649 
 650 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
 651   assert(rtype==relocInfo::opt_virtual_call_type || rtype==relocInfo::static_call_type, "unexpected rtype");
 652 
 653   bool success = emit_trampoline_stub_for_call(op->addr());
 654   if (!success) { return; }
 655 
 656   __ relocate(rtype);
 657   // Note: At this point we do not have the address of the trampoline
 658   // stub, and the entry point might be too far away for bl, so __ pc()
 659   // serves as dummy and the bl will be patched later.
 660   __ code()->set_insts_mark();
 661   __ bl(__ pc());
 662   add_call_info(code_offset(), op->info());
 663 }
 664 
 665 
 666 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
 667   __ calculate_address_from_global_toc(R2_TOC, __ method_toc());
 668 
 669   // Virtual call relocation will point to ic load.
 670   address virtual_call_meta_addr = __ pc();
 671   // Load a clear inline cache.
 672   AddressLiteral empty_ic((address) Universe::non_oop_word());
 673   bool success = __ load_const_from_method_toc(R19_inline_cache_reg, empty_ic, R2_TOC);
 674   if (!success) {
 675     bailout("const section overflow");
 676     return;
 677   }
 678   // Call to fixup routine. Fixup routine uses ScopeDesc info
 679   // to determine who we intended to call.
 680   __ relocate(virtual_call_Relocation::spec(virtual_call_meta_addr));
 681 
 682   success = emit_trampoline_stub_for_call(op->addr(), R2_TOC);
 683   if (!success) { return; }
 684 
 685   // Note: At this point we do not have the address of the trampoline
 686   // stub, and the entry point might be too far away for bl, so __ pc()
 687   // serves as dummy and the bl will be patched later.
 688   __ bl(__ pc());
 689   add_call_info(code_offset(), op->info());
 690 }
 691 
 692 void LIR_Assembler::explicit_null_check(Register addr, CodeEmitInfo* info) {
 693   ImplicitNullCheckStub* stub = new ImplicitNullCheckStub(code_offset(), info);
 694   __ null_check(addr, stub->entry());
 695   append_code_stub(stub);
 696 }
 697 
 698 
 699 // Attention: caller must encode oop if needed
 700 int LIR_Assembler::store(LIR_Opr from_reg, Register base, int offset, BasicType type, bool wide) {
 701   int store_offset;
 702   if (!Assembler::is_simm16(offset)) {
 703     // For offsets larger than a simm16 we setup the offset.
 704     assert(wide && !from_reg->is_same_register(FrameMap::R0_opr), "large offset only supported in special case");
 705     __ load_const_optimized(R0, offset);
 706     store_offset = store(from_reg, base, R0, type, wide);
 707   } else {
 708     store_offset = code_offset();
 709     switch (type) {
 710       case T_BOOLEAN: // fall through
 711       case T_BYTE  : __ stb(from_reg->as_register(), offset, base); break;
 712       case T_CHAR  :
 713       case T_SHORT : __ sth(from_reg->as_register(), offset, base); break;
 714       case T_INT   : __ stw(from_reg->as_register(), offset, base); break;
 715       case T_LONG  : __ std(from_reg->as_register_lo(), offset, base); break;
 716       case T_ADDRESS:
 717       case T_METADATA: __ std(from_reg->as_register(), offset, base); break;
 718       case T_ARRAY : // fall through
 719       case T_OBJECT:
 720         {
 721           if (UseCompressedOops && !wide) {
 722             // Encoding done in caller
 723             __ stw(from_reg->as_register(), offset, base);
 724             __ verify_coop(from_reg->as_register(), FILE_AND_LINE);
 725           } else {
 726             __ std(from_reg->as_register(), offset, base);
 727             __ verify_oop(from_reg->as_register(), FILE_AND_LINE);
 728           }
 729           break;
 730         }
 731       case T_FLOAT : __ stfs(from_reg->as_float_reg(), offset, base); break;
 732       case T_DOUBLE: __ stfd(from_reg->as_double_reg(), offset, base); break;
 733       default      : ShouldNotReachHere();
 734     }
 735   }
 736   return store_offset;
 737 }
 738 
 739 
 740 // Attention: caller must encode oop if needed
 741 int LIR_Assembler::store(LIR_Opr from_reg, Register base, Register disp, BasicType type, bool wide) {
 742   int store_offset = code_offset();
 743   switch (type) {
 744     case T_BOOLEAN: // fall through
 745     case T_BYTE  : __ stbx(from_reg->as_register(), base, disp); break;
 746     case T_CHAR  :
 747     case T_SHORT : __ sthx(from_reg->as_register(), base, disp); break;
 748     case T_INT   : __ stwx(from_reg->as_register(), base, disp); break;
 749     case T_LONG  :
 750 #ifdef _LP64
 751       __ stdx(from_reg->as_register_lo(), base, disp);
 752 #else
 753       Unimplemented();
 754 #endif
 755       break;
 756     case T_ADDRESS:
 757       __ stdx(from_reg->as_register(), base, disp);
 758       break;
 759     case T_ARRAY : // fall through
 760     case T_OBJECT:
 761       {
 762         if (UseCompressedOops && !wide) {
 763           // Encoding done in caller.
 764           __ stwx(from_reg->as_register(), base, disp);
 765           __ verify_coop(from_reg->as_register(), FILE_AND_LINE); // kills R0
 766         } else {
 767           __ stdx(from_reg->as_register(), base, disp);
 768           __ verify_oop(from_reg->as_register(), FILE_AND_LINE); // kills R0
 769         }
 770         break;
 771       }
 772     case T_FLOAT : __ stfsx(from_reg->as_float_reg(), base, disp); break;
 773     case T_DOUBLE: __ stfdx(from_reg->as_double_reg(), base, disp); break;
 774     default      : ShouldNotReachHere();
 775   }
 776   return store_offset;
 777 }
 778 
 779 
 780 int LIR_Assembler::load(Register base, int offset, LIR_Opr to_reg, BasicType type, bool wide) {
 781   int load_offset;
 782   if (!Assembler::is_simm16(offset)) {
 783     // For offsets larger than a simm16 we setup the offset.
 784     __ load_const_optimized(R0, offset);
 785     load_offset = load(base, R0, to_reg, type, wide);
 786   } else {
 787     load_offset = code_offset();
 788     switch(type) {
 789       case T_BOOLEAN: // fall through
 790       case T_BYTE  :   __ lbz(to_reg->as_register(), offset, base);
 791                        __ extsb(to_reg->as_register(), to_reg->as_register()); break;
 792       case T_CHAR  :   __ lhz(to_reg->as_register(), offset, base); break;
 793       case T_SHORT :   __ lha(to_reg->as_register(), offset, base); break;
 794       case T_INT   :   __ lwa(to_reg->as_register(), offset, base); break;
 795       case T_LONG  :   __ ld(to_reg->as_register_lo(), offset, base); break;
 796       case T_METADATA: __ ld(to_reg->as_register(), offset, base); break;
 797       case T_ADDRESS:
 798         __ ld(to_reg->as_register(), offset, base);
 799         break;
 800       case T_ARRAY : // fall through
 801       case T_OBJECT:
 802         {
 803           if (UseCompressedOops && !wide) {
 804             __ lwz(to_reg->as_register(), offset, base);
 805             __ decode_heap_oop(to_reg->as_register());
 806           } else {
 807             __ ld(to_reg->as_register(), offset, base);
 808           }
 809           __ verify_oop(to_reg->as_register(), FILE_AND_LINE);
 810           break;
 811         }
 812       case T_FLOAT:  __ lfs(to_reg->as_float_reg(), offset, base); break;
 813       case T_DOUBLE: __ lfd(to_reg->as_double_reg(), offset, base); break;
 814       default      : ShouldNotReachHere();
 815     }
 816   }
 817   return load_offset;
 818 }
 819 
 820 
 821 int LIR_Assembler::load(Register base, Register disp, LIR_Opr to_reg, BasicType type, bool wide) {
 822   int load_offset = code_offset();
 823   switch(type) {
 824     case T_BOOLEAN: // fall through
 825     case T_BYTE  :  __ lbzx(to_reg->as_register(), base, disp);
 826                     __ extsb(to_reg->as_register(), to_reg->as_register()); break;
 827     case T_CHAR  :  __ lhzx(to_reg->as_register(), base, disp); break;
 828     case T_SHORT :  __ lhax(to_reg->as_register(), base, disp); break;
 829     case T_INT   :  __ lwax(to_reg->as_register(), base, disp); break;
 830     case T_ADDRESS: __ ldx(to_reg->as_register(), base, disp); break;
 831     case T_ARRAY : // fall through
 832     case T_OBJECT:
 833       {
 834         if (UseCompressedOops && !wide) {
 835           __ lwzx(to_reg->as_register(), base, disp);
 836           __ decode_heap_oop(to_reg->as_register());
 837         } else {
 838           __ ldx(to_reg->as_register(), base, disp);
 839         }
 840         __ verify_oop(to_reg->as_register(), FILE_AND_LINE);
 841         break;
 842       }
 843     case T_FLOAT:  __ lfsx(to_reg->as_float_reg() , base, disp); break;
 844     case T_DOUBLE: __ lfdx(to_reg->as_double_reg(), base, disp); break;
 845     case T_LONG  :
 846 #ifdef _LP64
 847       __ ldx(to_reg->as_register_lo(), base, disp);
 848 #else
 849       Unimplemented();
 850 #endif
 851       break;
 852     default      : ShouldNotReachHere();
 853   }
 854   return load_offset;
 855 }
 856 
 857 
 858 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
 859   LIR_Const* c = src->as_constant_ptr();
 860   Register src_reg = R0;
 861   switch (c->type()) {
 862     case T_INT:
 863     case T_FLOAT: {
 864       int value = c->as_jint_bits();
 865       __ load_const_optimized(src_reg, value);
 866       Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
 867       __ stw(src_reg, addr.disp(), addr.base());
 868       break;
 869     }
 870     case T_ADDRESS: {
 871       int value = c->as_jint_bits();
 872       __ load_const_optimized(src_reg, value);
 873       Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
 874       __ std(src_reg, addr.disp(), addr.base());
 875       break;
 876     }
 877     case T_OBJECT: {
 878       jobject2reg(c->as_jobject(), src_reg);
 879       Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
 880       __ std(src_reg, addr.disp(), addr.base());
 881       break;
 882     }
 883     case T_LONG:
 884     case T_DOUBLE: {
 885       int value = c->as_jlong_bits();
 886       __ load_const_optimized(src_reg, value);
 887       Address addr = frame_map()->address_for_double_slot(dest->double_stack_ix());
 888       __ std(src_reg, addr.disp(), addr.base());
 889       break;
 890     }
 891     default:
 892       Unimplemented();
 893   }
 894 }
 895 
 896 
 897 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
 898   LIR_Const* c = src->as_constant_ptr();
 899   LIR_Address* addr = dest->as_address_ptr();
 900   Register base = addr->base()->as_pointer_register();
 901   LIR_Opr tmp = LIR_OprFact::illegalOpr;
 902   int offset = -1;
 903   // Null check for large offsets in LIRGenerator::do_StoreField.
 904   bool needs_explicit_null_check = !ImplicitNullChecks;
 905 
 906   if (info != NULL && needs_explicit_null_check) {
 907     explicit_null_check(base, info);
 908   }
 909 
 910   switch (c->type()) {
 911     case T_FLOAT: type = T_INT;
 912     case T_INT:
 913     case T_ADDRESS: {
 914       tmp = FrameMap::R0_opr;
 915       __ load_const_optimized(tmp->as_register(), c->as_jint_bits());
 916       break;
 917     }
 918     case T_DOUBLE: type = T_LONG;
 919     case T_LONG: {
 920       tmp = FrameMap::R0_long_opr;
 921       __ load_const_optimized(tmp->as_register_lo(), c->as_jlong_bits());
 922       break;
 923     }
 924     case T_OBJECT: {
 925       tmp = FrameMap::R0_opr;
 926       if (UseCompressedOops && !wide && c->as_jobject() != NULL) {
 927         AddressLiteral oop_addr = __ constant_oop_address(c->as_jobject());
 928         // Don't care about sign extend (will use stw).
 929         __ lis(R0, 0); // Will get patched.
 930         __ relocate(oop_addr.rspec(), /*compressed format*/ 1);
 931         __ ori(R0, R0, 0); // Will get patched.
 932       } else {
 933         jobject2reg(c->as_jobject(), R0);
 934       }
 935       break;
 936     }
 937     default:
 938       Unimplemented();
 939   }
 940 
 941   // Handle either reg+reg or reg+disp address.
 942   if (addr->index()->is_valid()) {
 943     assert(addr->disp() == 0, "must be zero");
 944     offset = store(tmp, base, addr->index()->as_pointer_register(), type, wide);
 945   } else {
 946     assert(Assembler::is_simm16(addr->disp()), "can't handle larger addresses");
 947     offset = store(tmp, base, addr->disp(), type, wide);
 948   }
 949 
 950   if (info != NULL) {
 951     assert(offset != -1, "offset should've been set");
 952     if (!needs_explicit_null_check) {
 953       add_debug_info_for_null_check(offset, info);
 954     }
 955   }
 956 }
 957 
 958 
 959 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
 960   LIR_Const* c = src->as_constant_ptr();
 961   LIR_Opr to_reg = dest;
 962 
 963   switch (c->type()) {
 964     case T_INT: {
 965       assert(patch_code == lir_patch_none, "no patching handled here");
 966       __ load_const_optimized(dest->as_register(), c->as_jint(), R0);
 967       break;
 968     }
 969     case T_ADDRESS: {
 970       assert(patch_code == lir_patch_none, "no patching handled here");
 971       __ load_const_optimized(dest->as_register(), c->as_jint(), R0);  // Yes, as_jint ...
 972       break;
 973     }
 974     case T_LONG: {
 975       assert(patch_code == lir_patch_none, "no patching handled here");
 976       __ load_const_optimized(dest->as_register_lo(), c->as_jlong(), R0);
 977       break;
 978     }
 979 
 980     case T_OBJECT: {
 981       if (patch_code == lir_patch_none) {
 982         jobject2reg(c->as_jobject(), to_reg->as_register());
 983       } else {
 984         jobject2reg_with_patching(to_reg->as_register(), info);
 985       }
 986       break;
 987     }
 988 
 989     case T_METADATA:
 990       {
 991         if (patch_code == lir_patch_none) {
 992           metadata2reg(c->as_metadata(), to_reg->as_register());
 993         } else {
 994           klass2reg_with_patching(to_reg->as_register(), info);
 995         }
 996       }
 997       break;
 998 
 999     case T_FLOAT:
1000       {
1001         if (to_reg->is_single_fpu()) {
1002           address const_addr = __ float_constant(c->as_jfloat());
1003           if (const_addr == NULL) {
1004             bailout("const section overflow");
1005             break;
1006           }
1007           RelocationHolder rspec = internal_word_Relocation::spec(const_addr);
1008           __ relocate(rspec);
1009           __ load_const(R0, const_addr);
1010           __ lfsx(to_reg->as_float_reg(), R0);
1011         } else {
1012           assert(to_reg->is_single_cpu(), "Must be a cpu register.");
1013           __ load_const_optimized(to_reg->as_register(), jint_cast(c->as_jfloat()), R0);
1014         }
1015       }
1016       break;
1017 
1018     case T_DOUBLE:
1019       {
1020         if (to_reg->is_double_fpu()) {
1021           address const_addr = __ double_constant(c->as_jdouble());
1022           if (const_addr == NULL) {
1023             bailout("const section overflow");
1024             break;
1025           }
1026           RelocationHolder rspec = internal_word_Relocation::spec(const_addr);
1027           __ relocate(rspec);
1028           __ load_const(R0, const_addr);
1029           __ lfdx(to_reg->as_double_reg(), R0);
1030         } else {
1031           assert(to_reg->is_double_cpu(), "Must be a long register.");
1032           __ load_const_optimized(to_reg->as_register_lo(), jlong_cast(c->as_jdouble()), R0);
1033         }
1034       }
1035       break;
1036 
1037     default:
1038       ShouldNotReachHere();
1039   }
1040 }
1041 
1042 
1043 Address LIR_Assembler::as_Address(LIR_Address* addr) {
1044   Unimplemented(); return Address();
1045 }
1046 
1047 
1048 inline RegisterOrConstant index_or_disp(LIR_Address* addr) {
1049   if (addr->index()->is_illegal()) {
1050     return (RegisterOrConstant)(addr->disp());
1051   } else {
1052     return (RegisterOrConstant)(addr->index()->as_pointer_register());
1053   }
1054 }
1055 
1056 
1057 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
1058   const Register tmp = R0;
1059   switch (type) {
1060     case T_INT:
1061     case T_FLOAT: {
1062       Address from = frame_map()->address_for_slot(src->single_stack_ix());
1063       Address to   = frame_map()->address_for_slot(dest->single_stack_ix());
1064       __ lwz(tmp, from.disp(), from.base());
1065       __ stw(tmp, to.disp(), to.base());
1066       break;
1067     }
1068     case T_ADDRESS:
1069     case T_OBJECT: {
1070       Address from = frame_map()->address_for_slot(src->single_stack_ix());
1071       Address to   = frame_map()->address_for_slot(dest->single_stack_ix());
1072       __ ld(tmp, from.disp(), from.base());
1073       __ std(tmp, to.disp(), to.base());
1074       break;
1075     }
1076     case T_LONG:
1077     case T_DOUBLE: {
1078       Address from = frame_map()->address_for_double_slot(src->double_stack_ix());
1079       Address to   = frame_map()->address_for_double_slot(dest->double_stack_ix());
1080       __ ld(tmp, from.disp(), from.base());
1081       __ std(tmp, to.disp(), to.base());
1082       break;
1083     }
1084 
1085     default:
1086       ShouldNotReachHere();
1087   }
1088 }
1089 
1090 
1091 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
1092   Unimplemented(); return Address();
1093 }
1094 
1095 
1096 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
1097   Unimplemented(); return Address();
1098 }
1099 
1100 
1101 void LIR_Assembler::mem2reg(LIR_Opr src_opr, LIR_Opr dest, BasicType type,
1102                             LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide) {
1103 
1104   assert(type != T_METADATA, "load of metadata ptr not supported");
1105   LIR_Address* addr = src_opr->as_address_ptr();
1106   LIR_Opr to_reg = dest;
1107 
1108   Register src = addr->base()->as_pointer_register();
1109   Register disp_reg = noreg;
1110   int disp_value = addr->disp();
1111   bool needs_patching = (patch_code != lir_patch_none);
1112   // null check for large offsets in LIRGenerator::do_LoadField
1113   bool needs_explicit_null_check = !os::zero_page_read_protected() || !ImplicitNullChecks;
1114 
1115   if (info != NULL && needs_explicit_null_check) {
1116     explicit_null_check(src, info);
1117   }
1118 
1119   if (addr->base()->type() == T_OBJECT) {
1120     __ verify_oop(src, FILE_AND_LINE);
1121   }
1122 
1123   PatchingStub* patch = NULL;
1124   if (needs_patching) {
1125     patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1126     assert(!to_reg->is_double_cpu() ||
1127            patch_code == lir_patch_none ||
1128            patch_code == lir_patch_normal, "patching doesn't match register");
1129   }
1130 
1131   if (addr->index()->is_illegal()) {
1132     if (!Assembler::is_simm16(disp_value)) {
1133       if (needs_patching) {
1134         __ load_const32(R0, 0); // patchable int
1135       } else {
1136         __ load_const_optimized(R0, disp_value);
1137       }
1138       disp_reg = R0;
1139     }
1140   } else {
1141     disp_reg = addr->index()->as_pointer_register();
1142     assert(disp_value == 0, "can't handle 3 operand addresses");
1143   }
1144 
1145   // Remember the offset of the load. The patching_epilog must be done
1146   // before the call to add_debug_info, otherwise the PcDescs don't get
1147   // entered in increasing order.
1148   int offset;
1149 
1150   if (disp_reg == noreg) {
1151     assert(Assembler::is_simm16(disp_value), "should have set this up");
1152     offset = load(src, disp_value, to_reg, type, wide);
1153   } else {
1154     offset = load(src, disp_reg, to_reg, type, wide);
1155   }
1156 
1157   if (patch != NULL) {
1158     patching_epilog(patch, patch_code, src, info);
1159   }
1160   if (info != NULL && !needs_explicit_null_check) {
1161     add_debug_info_for_null_check(offset, info);
1162   }
1163 }
1164 
1165 
1166 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
1167   Address addr;
1168   if (src->is_single_word()) {
1169     addr = frame_map()->address_for_slot(src->single_stack_ix());
1170   } else if (src->is_double_word())  {
1171     addr = frame_map()->address_for_double_slot(src->double_stack_ix());
1172   }
1173 
1174   load(addr.base(), addr.disp(), dest, dest->type(), true /*wide*/);
1175 }
1176 
1177 
1178 void LIR_Assembler::reg2stack(LIR_Opr from_reg, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
1179   Address addr;
1180   if (dest->is_single_word()) {
1181     addr = frame_map()->address_for_slot(dest->single_stack_ix());
1182   } else if (dest->is_double_word())  {
1183     addr = frame_map()->address_for_slot(dest->double_stack_ix());
1184   }
1185 
1186   store(from_reg, addr.base(), addr.disp(), from_reg->type(), true /*wide*/);
1187 }
1188 
1189 
1190 void LIR_Assembler::reg2reg(LIR_Opr from_reg, LIR_Opr to_reg) {
1191   if (from_reg->is_float_kind() && to_reg->is_float_kind()) {
1192     if (from_reg->is_double_fpu()) {
1193       // double to double moves
1194       assert(to_reg->is_double_fpu(), "should match");
1195       __ fmr_if_needed(to_reg->as_double_reg(), from_reg->as_double_reg());
1196     } else {
1197       // float to float moves
1198       assert(to_reg->is_single_fpu(), "should match");
1199       __ fmr_if_needed(to_reg->as_float_reg(), from_reg->as_float_reg());
1200     }
1201   } else if (!from_reg->is_float_kind() && !to_reg->is_float_kind()) {
1202     if (from_reg->is_double_cpu()) {
1203       __ mr_if_needed(to_reg->as_pointer_register(), from_reg->as_pointer_register());
1204     } else if (to_reg->is_double_cpu()) {
1205       // int to int moves
1206       __ mr_if_needed(to_reg->as_register_lo(), from_reg->as_register());
1207     } else {
1208       // int to int moves
1209       __ mr_if_needed(to_reg->as_register(), from_reg->as_register());
1210     }
1211   } else {
1212     ShouldNotReachHere();
1213   }
1214   if (is_reference_type(to_reg->type())) {
1215     __ verify_oop(to_reg->as_register(), FILE_AND_LINE);
1216   }
1217 }
1218 
1219 
1220 void LIR_Assembler::reg2mem(LIR_Opr from_reg, LIR_Opr dest, BasicType type,
1221                             LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack,
1222                             bool wide) {
1223   assert(type != T_METADATA, "store of metadata ptr not supported");
1224   LIR_Address* addr = dest->as_address_ptr();
1225 
1226   Register src = addr->base()->as_pointer_register();
1227   Register disp_reg = noreg;
1228   int disp_value = addr->disp();
1229   bool needs_patching = (patch_code != lir_patch_none);
1230   bool compress_oop = (is_reference_type(type)) && UseCompressedOops && !wide &&
1231                       CompressedOops::mode() != CompressedOops::UnscaledNarrowOop;
1232   bool load_disp = addr->index()->is_illegal() && !Assembler::is_simm16(disp_value);
1233   bool use_R29 = compress_oop && load_disp; // Avoid register conflict, also do null check before killing R29.
1234   // Null check for large offsets in LIRGenerator::do_StoreField.
1235   bool needs_explicit_null_check = !ImplicitNullChecks || use_R29;
1236 
1237   if (info != NULL && needs_explicit_null_check) {
1238     explicit_null_check(src, info);
1239   }
1240 
1241   if (addr->base()->is_oop_register()) {
1242     __ verify_oop(src, FILE_AND_LINE);
1243   }
1244 
1245   PatchingStub* patch = NULL;
1246   if (needs_patching) {
1247     patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1248     assert(!from_reg->is_double_cpu() ||
1249            patch_code == lir_patch_none ||
1250            patch_code == lir_patch_normal, "patching doesn't match register");
1251   }
1252 
1253   if (addr->index()->is_illegal()) {
1254     if (load_disp) {
1255       disp_reg = use_R29 ? R29_TOC : R0;
1256       if (needs_patching) {
1257         __ load_const32(disp_reg, 0); // patchable int
1258       } else {
1259         __ load_const_optimized(disp_reg, disp_value);
1260       }
1261     }
1262   } else {
1263     disp_reg = addr->index()->as_pointer_register();
1264     assert(disp_value == 0, "can't handle 3 operand addresses");
1265   }
1266 
1267   // remember the offset of the store. The patching_epilog must be done
1268   // before the call to add_debug_info_for_null_check, otherwise the PcDescs don't get
1269   // entered in increasing order.
1270   int offset;
1271 
1272   if (compress_oop) {
1273     Register co = __ encode_heap_oop(R0, from_reg->as_register());
1274     from_reg = FrameMap::as_opr(co);
1275   }
1276 
1277   if (disp_reg == noreg) {
1278     assert(Assembler::is_simm16(disp_value), "should have set this up");
1279     offset = store(from_reg, src, disp_value, type, wide);
1280   } else {
1281     offset = store(from_reg, src, disp_reg, type, wide);
1282   }
1283 
1284   if (use_R29) {
1285     __ load_const_optimized(R29_TOC, MacroAssembler::global_toc(), R0); // reinit
1286   }
1287 
1288   if (patch != NULL) {
1289     patching_epilog(patch, patch_code, src, info);
1290   }
1291 
1292   if (info != NULL && !needs_explicit_null_check) {
1293     add_debug_info_for_null_check(offset, info);
1294   }
1295 }
1296 
1297 
1298 void LIR_Assembler::return_op(LIR_Opr result, C1SafepointPollStub* code_stub) {
1299   const Register return_pc = R31;  // Must survive C-call to enable_stack_reserved_zone().
1300   const Register temp      = R12;
1301 
1302   // Pop the stack before the safepoint code.
1303   int frame_size = initial_frame_size_in_bytes();
1304   if (Assembler::is_simm(frame_size, 16)) {
1305     __ addi(R1_SP, R1_SP, frame_size);
1306   } else {
1307     __ pop_frame();
1308   }
1309 
1310   // Restore return pc relative to callers' sp.
1311   __ ld(return_pc, _abi0(lr), R1_SP);
1312   // Move return pc to LR.
1313   __ mtlr(return_pc);
1314 
1315   if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
1316     __ reserved_stack_check(return_pc);
1317   }
1318 
1319   // We need to mark the code position where the load from the safepoint
1320   // polling page was emitted as relocInfo::poll_return_type here.
1321   if (!UseSIGTRAP) {
1322     code_stub->set_safepoint_offset(__ offset());
1323     __ relocate(relocInfo::poll_return_type);
1324   }
1325   __ safepoint_poll(*code_stub->entry(), temp, true /* at_return */, true /* in_nmethod */);
1326 
1327   // Return.
1328   __ blr();
1329 }
1330 
1331 
1332 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
1333   const Register poll_addr = tmp->as_register();
1334   __ ld(poll_addr, in_bytes(JavaThread::polling_page_offset()), R16_thread);
1335   if (info != NULL) {
1336     add_debug_info_for_branch(info);
1337   }
1338   int offset = __ offset();
1339   __ relocate(relocInfo::poll_type);
1340   __ load_from_polling_page(poll_addr);
1341 
1342   return offset;
1343 }
1344 
1345 
1346 void LIR_Assembler::emit_static_call_stub() {
1347   address call_pc = __ pc();
1348   address stub = __ start_a_stub(static_call_stub_size());
1349   if (stub == NULL) {
1350     bailout("static call stub overflow");
1351     return;
1352   }
1353 
1354   // For java_to_interp stubs we use R11_scratch1 as scratch register
1355   // and in call trampoline stubs we use R12_scratch2. This way we
1356   // can distinguish them (see is_NativeCallTrampolineStub_at()).
1357   const Register reg_scratch = R11_scratch1;
1358 
1359   // Create a static stub relocation which relates this stub
1360   // with the call instruction at insts_call_instruction_offset in the
1361   // instructions code-section.
1362   int start = __ offset();
1363   __ relocate(static_stub_Relocation::spec(call_pc));
1364 
1365   // Now, create the stub's code:
1366   // - load the TOC
1367   // - load the inline cache oop from the constant pool
1368   // - load the call target from the constant pool
1369   // - call
1370   __ calculate_address_from_global_toc(reg_scratch, __ method_toc());
1371   AddressLiteral ic = __ allocate_metadata_address((Metadata *)NULL);
1372   bool success = __ load_const_from_method_toc(R19_inline_cache_reg, ic, reg_scratch, /*fixed_size*/ true);
1373 
1374   if (ReoptimizeCallSequences) {
1375     __ b64_patchable((address)-1, relocInfo::none);
1376   } else {
1377     AddressLiteral a((address)-1);
1378     success = success && __ load_const_from_method_toc(reg_scratch, a, reg_scratch, /*fixed_size*/ true);
1379     __ mtctr(reg_scratch);
1380     __ bctr();
1381   }
1382   if (!success) {
1383     bailout("const section overflow");
1384     return;
1385   }
1386 
1387   assert(__ offset() - start <= static_call_stub_size(), "stub too big");
1388   __ end_a_stub();
1389 }
1390 
1391 
1392 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
1393   bool unsigned_comp = (condition == lir_cond_belowEqual || condition == lir_cond_aboveEqual);
1394   if (opr1->is_single_fpu()) {
1395     __ fcmpu(BOOL_RESULT, opr1->as_float_reg(), opr2->as_float_reg());
1396   } else if (opr1->is_double_fpu()) {
1397     __ fcmpu(BOOL_RESULT, opr1->as_double_reg(), opr2->as_double_reg());
1398   } else if (opr1->is_single_cpu()) {
1399     if (opr2->is_constant()) {
1400       switch (opr2->as_constant_ptr()->type()) {
1401         case T_INT:
1402           {
1403             jint con = opr2->as_constant_ptr()->as_jint();
1404             if (unsigned_comp) {
1405               if (Assembler::is_uimm(con, 16)) {
1406                 __ cmplwi(BOOL_RESULT, opr1->as_register(), con);
1407               } else {
1408                 __ load_const_optimized(R0, con);
1409                 __ cmplw(BOOL_RESULT, opr1->as_register(), R0);
1410               }
1411             } else {
1412               if (Assembler::is_simm(con, 16)) {
1413                 __ cmpwi(BOOL_RESULT, opr1->as_register(), con);
1414               } else {
1415                 __ load_const_optimized(R0, con);
1416                 __ cmpw(BOOL_RESULT, opr1->as_register(), R0);
1417               }
1418             }
1419           }
1420           break;
1421 
1422         case T_OBJECT:
1423           // There are only equal/notequal comparisons on objects.
1424           {
1425             assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "oops");
1426             jobject con = opr2->as_constant_ptr()->as_jobject();
1427             if (con == NULL) {
1428               __ cmpdi(BOOL_RESULT, opr1->as_register(), 0);
1429             } else {
1430               jobject2reg(con, R0);
1431               __ cmpd(BOOL_RESULT, opr1->as_register(), R0);
1432             }
1433           }
1434           break;
1435 
1436         case T_METADATA:
1437           // We only need, for now, comparison with NULL for metadata.
1438           {
1439             assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "oops");
1440             Metadata* p = opr2->as_constant_ptr()->as_metadata();
1441             if (p == NULL) {
1442               __ cmpdi(BOOL_RESULT, opr1->as_register(), 0);
1443             } else {
1444               ShouldNotReachHere();
1445             }
1446           }
1447           break;
1448 
1449         default:
1450           ShouldNotReachHere();
1451           break;
1452       }
1453     } else {
1454       assert(opr1->type() != T_ADDRESS && opr2->type() != T_ADDRESS, "currently unsupported");
1455       if (is_reference_type(opr1->type())) {
1456         // There are only equal/notequal comparisons on objects.
1457         assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "oops");
1458         __ cmpd(BOOL_RESULT, opr1->as_register(), opr2->as_register());
1459       } else {
1460         if (unsigned_comp) {
1461           __ cmplw(BOOL_RESULT, opr1->as_register(), opr2->as_register());
1462         } else {
1463           __ cmpw(BOOL_RESULT, opr1->as_register(), opr2->as_register());
1464         }
1465       }
1466     }
1467   } else if (opr1->is_double_cpu()) {
1468     if (opr2->is_constant()) {
1469       jlong con = opr2->as_constant_ptr()->as_jlong();
1470       if (unsigned_comp) {
1471         if (Assembler::is_uimm(con, 16)) {
1472           __ cmpldi(BOOL_RESULT, opr1->as_register_lo(), con);
1473         } else {
1474           __ load_const_optimized(R0, con);
1475           __ cmpld(BOOL_RESULT, opr1->as_register_lo(), R0);
1476         }
1477       } else {
1478         if (Assembler::is_simm(con, 16)) {
1479           __ cmpdi(BOOL_RESULT, opr1->as_register_lo(), con);
1480         } else {
1481           __ load_const_optimized(R0, con);
1482           __ cmpd(BOOL_RESULT, opr1->as_register_lo(), R0);
1483         }
1484       }
1485     } else if (opr2->is_register()) {
1486       if (unsigned_comp) {
1487         __ cmpld(BOOL_RESULT, opr1->as_register_lo(), opr2->as_register_lo());
1488       } else {
1489         __ cmpd(BOOL_RESULT, opr1->as_register_lo(), opr2->as_register_lo());
1490       }
1491     } else {
1492       ShouldNotReachHere();
1493     }
1494   } else {
1495     ShouldNotReachHere();
1496   }
1497 }
1498 
1499 
1500 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op){
1501   const Register Rdst = dst->as_register();
1502   if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
1503     bool is_unordered_less = (code == lir_ucmp_fd2i);
1504     if (left->is_single_fpu()) {
1505       __ fcmpu(CCR0, left->as_float_reg(), right->as_float_reg());
1506     } else if (left->is_double_fpu()) {
1507       __ fcmpu(CCR0, left->as_double_reg(), right->as_double_reg());
1508     } else {
1509       ShouldNotReachHere();
1510     }
1511     __ set_cmpu3(Rdst, is_unordered_less); // is_unordered_less ? -1 : 1
1512   } else if (code == lir_cmp_l2i) {
1513     __ cmpd(CCR0, left->as_register_lo(), right->as_register_lo());
1514     __ set_cmp3(Rdst);  // set result as follows: <: -1, =: 0, >: 1
1515   } else {
1516     ShouldNotReachHere();
1517   }
1518 }
1519 
1520 
1521 inline void load_to_reg(LIR_Assembler *lasm, LIR_Opr src, LIR_Opr dst) {
1522   if (src->is_constant()) {
1523     lasm->const2reg(src, dst, lir_patch_none, NULL);
1524   } else if (src->is_register()) {
1525     lasm->reg2reg(src, dst);
1526   } else if (src->is_stack()) {
1527     lasm->stack2reg(src, dst, dst->type());
1528   } else {
1529     ShouldNotReachHere();
1530   }
1531 }
1532 
1533 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type,
1534                           LIR_Opr cmp_opr1, LIR_Opr cmp_opr2) {
1535   assert(cmp_opr1 == LIR_OprFact::illegalOpr && cmp_opr2 == LIR_OprFact::illegalOpr, "unnecessary cmp oprs on ppc");
1536 
1537   if (opr1->is_equal(opr2) || opr1->is_same_register(opr2)) {
1538     load_to_reg(this, opr1, result); // Condition doesn't matter.
1539     return;
1540   }
1541 
1542   bool positive = false;
1543   Assembler::Condition cond = Assembler::equal;
1544   switch (condition) {
1545     case lir_cond_equal:        positive = true ; cond = Assembler::equal  ; break;
1546     case lir_cond_notEqual:     positive = false; cond = Assembler::equal  ; break;
1547     case lir_cond_less:         positive = true ; cond = Assembler::less   ; break;
1548     case lir_cond_belowEqual:
1549     case lir_cond_lessEqual:    positive = false; cond = Assembler::greater; break;
1550     case lir_cond_greater:      positive = true ; cond = Assembler::greater; break;
1551     case lir_cond_aboveEqual:
1552     case lir_cond_greaterEqual: positive = false; cond = Assembler::less   ; break;
1553     default:                    ShouldNotReachHere();
1554   }
1555 
1556   // Try to use isel on >=Power7.
1557   if (VM_Version::has_isel() && result->is_cpu_register()) {
1558     bool o1_is_reg = opr1->is_cpu_register(), o2_is_reg = opr2->is_cpu_register();
1559     const Register result_reg = result->is_single_cpu() ? result->as_register() : result->as_register_lo();
1560 
1561     // We can use result_reg to load one operand if not already in register.
1562     Register first  = o1_is_reg ? (opr1->is_single_cpu() ? opr1->as_register() : opr1->as_register_lo()) : result_reg,
1563              second = o2_is_reg ? (opr2->is_single_cpu() ? opr2->as_register() : opr2->as_register_lo()) : result_reg;
1564 
1565     if (first != second) {
1566       if (!o1_is_reg) {
1567         load_to_reg(this, opr1, result);
1568       }
1569 
1570       if (!o2_is_reg) {
1571         load_to_reg(this, opr2, result);
1572       }
1573 
1574       __ isel(result_reg, BOOL_RESULT, cond, !positive, first, second);
1575       return;
1576     }
1577   } // isel
1578 
1579   load_to_reg(this, opr1, result);
1580 
1581   Label skip;
1582   int bo = positive ? Assembler::bcondCRbiIs1 : Assembler::bcondCRbiIs0;
1583   int bi = Assembler::bi0(BOOL_RESULT, cond);
1584   __ bc(bo, bi, skip);
1585 
1586   load_to_reg(this, opr2, result);
1587   __ bind(skip);
1588 }
1589 
1590 
1591 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest,
1592                              CodeEmitInfo* info, bool pop_fpu_stack) {
1593   assert(info == NULL, "unused on this code path");
1594   assert(left->is_register(), "wrong items state");
1595   assert(dest->is_register(), "wrong items state");
1596 
1597   if (right->is_register()) {
1598     if (dest->is_float_kind()) {
1599 
1600       FloatRegister lreg, rreg, res;
1601       if (right->is_single_fpu()) {
1602         lreg = left->as_float_reg();
1603         rreg = right->as_float_reg();
1604         res  = dest->as_float_reg();
1605         switch (code) {
1606           case lir_add: __ fadds(res, lreg, rreg); break;
1607           case lir_sub: __ fsubs(res, lreg, rreg); break;
1608           case lir_mul: __ fmuls(res, lreg, rreg); break;
1609           case lir_div: __ fdivs(res, lreg, rreg); break;
1610           default: ShouldNotReachHere();
1611         }
1612       } else {
1613         lreg = left->as_double_reg();
1614         rreg = right->as_double_reg();
1615         res  = dest->as_double_reg();
1616         switch (code) {
1617           case lir_add: __ fadd(res, lreg, rreg); break;
1618           case lir_sub: __ fsub(res, lreg, rreg); break;
1619           case lir_mul: __ fmul(res, lreg, rreg); break;
1620           case lir_div: __ fdiv(res, lreg, rreg); break;
1621           default: ShouldNotReachHere();
1622         }
1623       }
1624 
1625     } else if (dest->is_double_cpu()) {
1626 
1627       Register dst_lo = dest->as_register_lo();
1628       Register op1_lo = left->as_pointer_register();
1629       Register op2_lo = right->as_pointer_register();
1630 
1631       switch (code) {
1632         case lir_add: __ add(dst_lo, op1_lo, op2_lo); break;
1633         case lir_sub: __ sub(dst_lo, op1_lo, op2_lo); break;
1634         case lir_mul: __ mulld(dst_lo, op1_lo, op2_lo); break;
1635         default: ShouldNotReachHere();
1636       }
1637     } else {
1638       assert (right->is_single_cpu(), "Just Checking");
1639 
1640       Register lreg = left->as_register();
1641       Register res  = dest->as_register();
1642       Register rreg = right->as_register();
1643       switch (code) {
1644         case lir_add:  __ add  (res, lreg, rreg); break;
1645         case lir_sub:  __ sub  (res, lreg, rreg); break;
1646         case lir_mul:  __ mullw(res, lreg, rreg); break;
1647         default: ShouldNotReachHere();
1648       }
1649     }
1650   } else {
1651     assert (right->is_constant(), "must be constant");
1652 
1653     if (dest->is_single_cpu()) {
1654       Register lreg = left->as_register();
1655       Register res  = dest->as_register();
1656       int    simm16 = right->as_constant_ptr()->as_jint();
1657 
1658       switch (code) {
1659         case lir_sub:  assert(Assembler::is_simm16(-simm16), "cannot encode"); // see do_ArithmeticOp_Int
1660                        simm16 = -simm16;
1661         case lir_add:  if (res == lreg && simm16 == 0) break;
1662                        __ addi(res, lreg, simm16); break;
1663         case lir_mul:  if (res == lreg && simm16 == 1) break;
1664                        __ mulli(res, lreg, simm16); break;
1665         default: ShouldNotReachHere();
1666       }
1667     } else {
1668       Register lreg = left->as_pointer_register();
1669       Register res  = dest->as_register_lo();
1670       long con = right->as_constant_ptr()->as_jlong();
1671       assert(Assembler::is_simm16(con), "must be simm16");
1672 
1673       switch (code) {
1674         case lir_sub:  assert(Assembler::is_simm16(-con), "cannot encode");  // see do_ArithmeticOp_Long
1675                        con = -con;
1676         case lir_add:  if (res == lreg && con == 0) break;
1677                        __ addi(res, lreg, (int)con); break;
1678         case lir_mul:  if (res == lreg && con == 1) break;
1679                        __ mulli(res, lreg, (int)con); break;
1680         default: ShouldNotReachHere();
1681       }
1682     }
1683   }
1684 }
1685 
1686 
1687 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr thread, LIR_Opr dest, LIR_Op* op) {
1688   switch (code) {
1689     case lir_sqrt: {
1690       __ fsqrt(dest->as_double_reg(), value->as_double_reg());
1691       break;
1692     }
1693     case lir_abs: {
1694       __ fabs(dest->as_double_reg(), value->as_double_reg());
1695       break;
1696     }
1697     default: {
1698       ShouldNotReachHere();
1699       break;
1700     }
1701   }
1702 }
1703 
1704 
1705 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest) {
1706   if (right->is_constant()) { // see do_LogicOp
1707     long uimm;
1708     Register d, l;
1709     if (dest->is_single_cpu()) {
1710       uimm = right->as_constant_ptr()->as_jint();
1711       d = dest->as_register();
1712       l = left->as_register();
1713     } else {
1714       uimm = right->as_constant_ptr()->as_jlong();
1715       d = dest->as_register_lo();
1716       l = left->as_register_lo();
1717     }
1718     long uimms  = (unsigned long)uimm >> 16,
1719          uimmss = (unsigned long)uimm >> 32;
1720 
1721     switch (code) {
1722       case lir_logic_and:
1723         if (uimmss != 0 || (uimms != 0 && (uimm & 0xFFFF) != 0) || is_power_of_2(uimm)) {
1724           __ andi(d, l, uimm); // special cases
1725         } else if (uimms != 0) { __ andis_(d, l, uimms); }
1726         else { __ andi_(d, l, uimm); }
1727         break;
1728 
1729       case lir_logic_or:
1730         if (uimms != 0) { assert((uimm & 0xFFFF) == 0, "sanity"); __ oris(d, l, uimms); }
1731         else { __ ori(d, l, uimm); }
1732         break;
1733 
1734       case lir_logic_xor:
1735         if (uimm == -1) { __ nand(d, l, l); } // special case
1736         else if (uimms != 0) { assert((uimm & 0xFFFF) == 0, "sanity"); __ xoris(d, l, uimms); }
1737         else { __ xori(d, l, uimm); }
1738         break;
1739 
1740       default: ShouldNotReachHere();
1741     }
1742   } else {
1743     assert(right->is_register(), "right should be in register");
1744 
1745     if (dest->is_single_cpu()) {
1746       switch (code) {
1747         case lir_logic_and: __ andr(dest->as_register(), left->as_register(), right->as_register()); break;
1748         case lir_logic_or:  __ orr (dest->as_register(), left->as_register(), right->as_register()); break;
1749         case lir_logic_xor: __ xorr(dest->as_register(), left->as_register(), right->as_register()); break;
1750         default: ShouldNotReachHere();
1751       }
1752     } else {
1753       Register l = (left->is_single_cpu() && left->is_oop_register()) ? left->as_register() :
1754                                                                         left->as_register_lo();
1755       Register r = (right->is_single_cpu() && right->is_oop_register()) ? right->as_register() :
1756                                                                           right->as_register_lo();
1757 
1758       switch (code) {
1759         case lir_logic_and: __ andr(dest->as_register_lo(), l, r); break;
1760         case lir_logic_or:  __ orr (dest->as_register_lo(), l, r); break;
1761         case lir_logic_xor: __ xorr(dest->as_register_lo(), l, r); break;
1762         default: ShouldNotReachHere();
1763       }
1764     }
1765   }
1766 }
1767 
1768 
1769 int LIR_Assembler::shift_amount(BasicType t) {
1770   int elem_size = type2aelembytes(t);
1771   switch (elem_size) {
1772     case 1 : return 0;
1773     case 2 : return 1;
1774     case 4 : return 2;
1775     case 8 : return 3;
1776   }
1777   ShouldNotReachHere();
1778   return -1;
1779 }
1780 
1781 
1782 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
1783   info->add_register_oop(exceptionOop);
1784 
1785   // Reuse the debug info from the safepoint poll for the throw op itself.
1786   address pc_for_athrow = __ pc();
1787   int pc_for_athrow_offset = __ offset();
1788   //RelocationHolder rspec = internal_word_Relocation::spec(pc_for_athrow);
1789   //__ relocate(rspec);
1790   //__ load_const(exceptionPC->as_register(), pc_for_athrow, R0);
1791   __ calculate_address_from_global_toc(exceptionPC->as_register(), pc_for_athrow, true, true, /*add_relocation*/ true);
1792   add_call_info(pc_for_athrow_offset, info); // for exception handler
1793 
1794   address stub = Runtime1::entry_for(compilation()->has_fpu_code() ? Runtime1::handle_exception_id
1795                                                                    : Runtime1::handle_exception_nofpu_id);
1796   //__ load_const_optimized(R0, stub);
1797   __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(stub));
1798   __ mtctr(R0);
1799   __ bctr();
1800 }
1801 
1802 
1803 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
1804   // Note: Not used with EnableDebuggingOnDemand.
1805   assert(exceptionOop->as_register() == R3, "should match");
1806   __ b(_unwind_handler_entry);
1807 }
1808 
1809 
1810 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
1811   Register src = op->src()->as_register();
1812   Register dst = op->dst()->as_register();
1813   Register src_pos = op->src_pos()->as_register();
1814   Register dst_pos = op->dst_pos()->as_register();
1815   Register length  = op->length()->as_register();
1816   Register tmp = op->tmp()->as_register();
1817   Register tmp2 = R0;
1818 
1819   int flags = op->flags();
1820   ciArrayKlass* default_type = op->expected_type();
1821   BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL;
1822   if (basic_type == T_ARRAY) basic_type = T_OBJECT;
1823 
1824   // Set up the arraycopy stub information.
1825   ArrayCopyStub* stub = op->stub();
1826   const int frame_resize = frame::abi_reg_args_size - sizeof(frame::jit_abi); // C calls need larger frame.
1827 
1828   // Always do stub if no type information is available. It's ok if
1829   // the known type isn't loaded since the code sanity checks
1830   // in debug mode and the type isn't required when we know the exact type
1831   // also check that the type is an array type.
1832   if (op->expected_type() == NULL) {
1833     assert(src->is_nonvolatile() && src_pos->is_nonvolatile() && dst->is_nonvolatile() && dst_pos->is_nonvolatile() &&
1834            length->is_nonvolatile(), "must preserve");
1835     address copyfunc_addr = StubRoutines::generic_arraycopy();
1836     assert(copyfunc_addr != NULL, "generic arraycopy stub required");
1837 
1838     // 3 parms are int. Convert to long.
1839     __ mr(R3_ARG1, src);
1840     __ extsw(R4_ARG2, src_pos);
1841     __ mr(R5_ARG3, dst);
1842     __ extsw(R6_ARG4, dst_pos);
1843     __ extsw(R7_ARG5, length);
1844 
1845 #ifndef PRODUCT
1846     if (PrintC1Statistics) {
1847       address counter = (address)&Runtime1::_generic_arraycopystub_cnt;
1848       int simm16_offs = __ load_const_optimized(tmp, counter, tmp2, true);
1849       __ lwz(R11_scratch1, simm16_offs, tmp);
1850       __ addi(R11_scratch1, R11_scratch1, 1);
1851       __ stw(R11_scratch1, simm16_offs, tmp);
1852     }
1853 #endif
1854     __ call_c_with_frame_resize(copyfunc_addr, /*stub does not need resized frame*/ 0);
1855 
1856     __ nand(tmp, R3_RET, R3_RET);
1857     __ subf(length, tmp, length);
1858     __ add(src_pos, tmp, src_pos);
1859     __ add(dst_pos, tmp, dst_pos);
1860 
1861     __ cmpwi(CCR0, R3_RET, 0);
1862     __ bc_far_optimized(Assembler::bcondCRbiIs1, __ bi0(CCR0, Assembler::less), *stub->entry());
1863     __ bind(*stub->continuation());
1864     return;
1865   }
1866 
1867   assert(default_type != NULL && default_type->is_array_klass(), "must be true at this point");
1868   Label cont, slow, copyfunc;
1869 
1870   bool simple_check_flag_set = flags & (LIR_OpArrayCopy::src_null_check |
1871                                         LIR_OpArrayCopy::dst_null_check |
1872                                         LIR_OpArrayCopy::src_pos_positive_check |
1873                                         LIR_OpArrayCopy::dst_pos_positive_check |
1874                                         LIR_OpArrayCopy::length_positive_check);
1875 
1876   // Use only one conditional branch for simple checks.
1877   if (simple_check_flag_set) {
1878     ConditionRegister combined_check = CCR1, tmp_check = CCR1;
1879 
1880     // Make sure src and dst are non-null.
1881     if (flags & LIR_OpArrayCopy::src_null_check) {
1882       __ cmpdi(combined_check, src, 0);
1883       tmp_check = CCR0;
1884     }
1885 
1886     if (flags & LIR_OpArrayCopy::dst_null_check) {
1887       __ cmpdi(tmp_check, dst, 0);
1888       if (tmp_check != combined_check) {
1889         __ cror(combined_check, Assembler::equal, tmp_check, Assembler::equal);
1890       }
1891       tmp_check = CCR0;
1892     }
1893 
1894     // Clear combined_check.eq if not already used.
1895     if (tmp_check == combined_check) {
1896       __ crandc(combined_check, Assembler::equal, combined_check, Assembler::equal);
1897       tmp_check = CCR0;
1898     }
1899 
1900     if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
1901       // Test src_pos register.
1902       __ cmpwi(tmp_check, src_pos, 0);
1903       __ cror(combined_check, Assembler::equal, tmp_check, Assembler::less);
1904     }
1905 
1906     if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
1907       // Test dst_pos register.
1908       __ cmpwi(tmp_check, dst_pos, 0);
1909       __ cror(combined_check, Assembler::equal, tmp_check, Assembler::less);
1910     }
1911 
1912     if (flags & LIR_OpArrayCopy::length_positive_check) {
1913       // Make sure length isn't negative.
1914       __ cmpwi(tmp_check, length, 0);
1915       __ cror(combined_check, Assembler::equal, tmp_check, Assembler::less);
1916     }
1917 
1918     __ beq(combined_check, slow);
1919   }
1920 
1921   // If the compiler was not able to prove that exact type of the source or the destination
1922   // of the arraycopy is an array type, check at runtime if the source or the destination is
1923   // an instance type.
1924   if (flags & LIR_OpArrayCopy::type_check) {
1925     if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
1926       __ load_klass(tmp, dst);
1927       __ lwz(tmp2, in_bytes(Klass::layout_helper_offset()), tmp);
1928       __ cmpwi(CCR0, tmp2, Klass::_lh_neutral_value);
1929       __ bge(CCR0, slow);
1930     }
1931 
1932     if (!(flags & LIR_OpArrayCopy::src_objarray)) {
1933       __ load_klass(tmp, src);
1934       __ lwz(tmp2, in_bytes(Klass::layout_helper_offset()), tmp);
1935       __ cmpwi(CCR0, tmp2, Klass::_lh_neutral_value);
1936       __ bge(CCR0, slow);
1937     }
1938   }
1939 
1940   // Higher 32bits must be null.
1941   __ extsw(length, length);
1942 
1943   __ extsw(src_pos, src_pos);
1944   if (flags & LIR_OpArrayCopy::src_range_check) {
1945     __ lwz(tmp2, arrayOopDesc::length_offset_in_bytes(), src);
1946     __ add(tmp, length, src_pos);
1947     __ cmpld(CCR0, tmp2, tmp);
1948     __ ble(CCR0, slow);
1949   }
1950 
1951   __ extsw(dst_pos, dst_pos);
1952   if (flags & LIR_OpArrayCopy::dst_range_check) {
1953     __ lwz(tmp2, arrayOopDesc::length_offset_in_bytes(), dst);
1954     __ add(tmp, length, dst_pos);
1955     __ cmpld(CCR0, tmp2, tmp);
1956     __ ble(CCR0, slow);
1957   }
1958 
1959   int shift = shift_amount(basic_type);
1960 
1961   if (!(flags & LIR_OpArrayCopy::type_check)) {
1962     __ b(cont);
1963   } else {
1964     // We don't know the array types are compatible.
1965     if (basic_type != T_OBJECT) {
1966       // Simple test for basic type arrays.
1967       if (UseCompressedClassPointers) {
1968         // We don't need decode because we just need to compare.
1969         __ lwz(tmp, oopDesc::klass_offset_in_bytes(), src);
1970         __ lwz(tmp2, oopDesc::klass_offset_in_bytes(), dst);
1971         __ cmpw(CCR0, tmp, tmp2);
1972       } else {
1973         __ ld(tmp, oopDesc::klass_offset_in_bytes(), src);
1974         __ ld(tmp2, oopDesc::klass_offset_in_bytes(), dst);
1975         __ cmpd(CCR0, tmp, tmp2);
1976       }
1977       __ beq(CCR0, cont);
1978     } else {
1979       // For object arrays, if src is a sub class of dst then we can
1980       // safely do the copy.
1981       address copyfunc_addr = StubRoutines::checkcast_arraycopy();
1982 
1983       const Register sub_klass = R5, super_klass = R4; // like CheckCast/InstanceOf
1984       assert_different_registers(tmp, tmp2, sub_klass, super_klass);
1985 
1986       __ load_klass(sub_klass, src);
1987       __ load_klass(super_klass, dst);
1988 
1989       __ check_klass_subtype_fast_path(sub_klass, super_klass, tmp, tmp2,
1990                                        &cont, copyfunc_addr != NULL ? &copyfunc : &slow, NULL);
1991 
1992       address slow_stc = Runtime1::entry_for(Runtime1::slow_subtype_check_id);
1993       //__ load_const_optimized(tmp, slow_stc, tmp2);
1994       __ calculate_address_from_global_toc(tmp, slow_stc, true, true, false);
1995       __ mtctr(tmp);
1996       __ bctrl(); // sets CR0
1997       __ beq(CCR0, cont);
1998 
1999       if (copyfunc_addr != NULL) { // Use stub if available.
2000         __ bind(copyfunc);
2001         // Src is not a sub class of dst so we have to do a
2002         // per-element check.
2003         int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
2004         if ((flags & mask) != mask) {
2005           assert(flags & mask, "one of the two should be known to be an object array");
2006 
2007           if (!(flags & LIR_OpArrayCopy::src_objarray)) {
2008             __ load_klass(tmp, src);
2009           } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
2010             __ load_klass(tmp, dst);
2011           }
2012 
2013           __ lwz(tmp2, in_bytes(Klass::layout_helper_offset()), tmp);
2014 
2015           jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
2016           __ load_const_optimized(tmp, objArray_lh);
2017           __ cmpw(CCR0, tmp, tmp2);
2018           __ bne(CCR0, slow);
2019         }
2020 
2021         Register src_ptr = R3_ARG1;
2022         Register dst_ptr = R4_ARG2;
2023         Register len     = R5_ARG3;
2024         Register chk_off = R6_ARG4;
2025         Register super_k = R7_ARG5;
2026 
2027         __ addi(src_ptr, src, arrayOopDesc::base_offset_in_bytes(basic_type));
2028         __ addi(dst_ptr, dst, arrayOopDesc::base_offset_in_bytes(basic_type));
2029         if (shift == 0) {
2030           __ add(src_ptr, src_pos, src_ptr);
2031           __ add(dst_ptr, dst_pos, dst_ptr);
2032         } else {
2033           __ sldi(tmp, src_pos, shift);
2034           __ sldi(tmp2, dst_pos, shift);
2035           __ add(src_ptr, tmp, src_ptr);
2036           __ add(dst_ptr, tmp2, dst_ptr);
2037         }
2038 
2039         __ load_klass(tmp, dst);
2040         __ mr(len, length);
2041 
2042         int ek_offset = in_bytes(ObjArrayKlass::element_klass_offset());
2043         __ ld(super_k, ek_offset, tmp);
2044 
2045         int sco_offset = in_bytes(Klass::super_check_offset_offset());
2046         __ lwz(chk_off, sco_offset, super_k);
2047 
2048         __ call_c_with_frame_resize(copyfunc_addr, /*stub does not need resized frame*/ 0);
2049 
2050 #ifndef PRODUCT
2051         if (PrintC1Statistics) {
2052           Label failed;
2053           __ cmpwi(CCR0, R3_RET, 0);
2054           __ bne(CCR0, failed);
2055           address counter = (address)&Runtime1::_arraycopy_checkcast_cnt;
2056           int simm16_offs = __ load_const_optimized(tmp, counter, tmp2, true);
2057           __ lwz(R11_scratch1, simm16_offs, tmp);
2058           __ addi(R11_scratch1, R11_scratch1, 1);
2059           __ stw(R11_scratch1, simm16_offs, tmp);
2060           __ bind(failed);
2061         }
2062 #endif
2063 
2064         __ nand(tmp, R3_RET, R3_RET);
2065         __ cmpwi(CCR0, R3_RET, 0);
2066         __ beq(CCR0, *stub->continuation());
2067 
2068 #ifndef PRODUCT
2069         if (PrintC1Statistics) {
2070           address counter = (address)&Runtime1::_arraycopy_checkcast_attempt_cnt;
2071           int simm16_offs = __ load_const_optimized(tmp, counter, tmp2, true);
2072           __ lwz(R11_scratch1, simm16_offs, tmp);
2073           __ addi(R11_scratch1, R11_scratch1, 1);
2074           __ stw(R11_scratch1, simm16_offs, tmp);
2075         }
2076 #endif
2077 
2078         __ subf(length, tmp, length);
2079         __ add(src_pos, tmp, src_pos);
2080         __ add(dst_pos, tmp, dst_pos);
2081       }
2082     }
2083   }
2084   __ bind(slow);
2085   __ b(*stub->entry());
2086   __ bind(cont);
2087 
2088 #ifdef ASSERT
2089   if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
2090     // Sanity check the known type with the incoming class. For the
2091     // primitive case the types must match exactly with src.klass and
2092     // dst.klass each exactly matching the default type. For the
2093     // object array case, if no type check is needed then either the
2094     // dst type is exactly the expected type and the src type is a
2095     // subtype which we can't check or src is the same array as dst
2096     // but not necessarily exactly of type default_type.
2097     Label known_ok, halt;
2098     metadata2reg(op->expected_type()->constant_encoding(), tmp);
2099     if (UseCompressedClassPointers) {
2100       // Tmp holds the default type. It currently comes uncompressed after the
2101       // load of a constant, so encode it.
2102       __ encode_klass_not_null(tmp);
2103       // Load the raw value of the dst klass, since we will be comparing
2104       // uncompressed values directly.
2105       __ lwz(tmp2, oopDesc::klass_offset_in_bytes(), dst);
2106       __ cmpw(CCR0, tmp, tmp2);
2107       if (basic_type != T_OBJECT) {
2108         __ bne(CCR0, halt);
2109         // Load the raw value of the src klass.
2110         __ lwz(tmp2, oopDesc::klass_offset_in_bytes(), src);
2111         __ cmpw(CCR0, tmp, tmp2);
2112         __ beq(CCR0, known_ok);
2113       } else {
2114         __ beq(CCR0, known_ok);
2115         __ cmpw(CCR0, src, dst);
2116         __ beq(CCR0, known_ok);
2117       }
2118     } else {
2119       __ ld(tmp2, oopDesc::klass_offset_in_bytes(), dst);
2120       __ cmpd(CCR0, tmp, tmp2);
2121       if (basic_type != T_OBJECT) {
2122         __ bne(CCR0, halt);
2123         // Load the raw value of the src klass.
2124         __ ld(tmp2, oopDesc::klass_offset_in_bytes(), src);
2125         __ cmpd(CCR0, tmp, tmp2);
2126         __ beq(CCR0, known_ok);
2127       } else {
2128         __ beq(CCR0, known_ok);
2129         __ cmpd(CCR0, src, dst);
2130         __ beq(CCR0, known_ok);
2131       }
2132     }
2133     __ bind(halt);
2134     __ stop("incorrect type information in arraycopy");
2135     __ bind(known_ok);
2136   }
2137 #endif
2138 
2139 #ifndef PRODUCT
2140   if (PrintC1Statistics) {
2141     address counter = Runtime1::arraycopy_count_address(basic_type);
2142     int simm16_offs = __ load_const_optimized(tmp, counter, tmp2, true);
2143     __ lwz(R11_scratch1, simm16_offs, tmp);
2144     __ addi(R11_scratch1, R11_scratch1, 1);
2145     __ stw(R11_scratch1, simm16_offs, tmp);
2146   }
2147 #endif
2148 
2149   Register src_ptr = R3_ARG1;
2150   Register dst_ptr = R4_ARG2;
2151   Register len     = R5_ARG3;
2152 
2153   __ addi(src_ptr, src, arrayOopDesc::base_offset_in_bytes(basic_type));
2154   __ addi(dst_ptr, dst, arrayOopDesc::base_offset_in_bytes(basic_type));
2155   if (shift == 0) {
2156     __ add(src_ptr, src_pos, src_ptr);
2157     __ add(dst_ptr, dst_pos, dst_ptr);
2158   } else {
2159     __ sldi(tmp, src_pos, shift);
2160     __ sldi(tmp2, dst_pos, shift);
2161     __ add(src_ptr, tmp, src_ptr);
2162     __ add(dst_ptr, tmp2, dst_ptr);
2163   }
2164 
2165   bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
2166   bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
2167   const char *name;
2168   address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
2169 
2170   // Arraycopy stubs takes a length in number of elements, so don't scale it.
2171   __ mr(len, length);
2172   __ call_c_with_frame_resize(entry, /*stub does not need resized frame*/ 0);
2173 
2174   __ bind(*stub->continuation());
2175 }
2176 
2177 
2178 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2179   if (dest->is_single_cpu()) {
2180     __ rldicl(tmp->as_register(), count->as_register(), 0, 64-5);
2181 #ifdef _LP64
2182     if (left->type() == T_OBJECT) {
2183       switch (code) {
2184         case lir_shl:  __ sld(dest->as_register(), left->as_register(), tmp->as_register()); break;
2185         case lir_shr:  __ srad(dest->as_register(), left->as_register(), tmp->as_register()); break;
2186         case lir_ushr: __ srd(dest->as_register(), left->as_register(), tmp->as_register()); break;
2187         default: ShouldNotReachHere();
2188       }
2189     } else
2190 #endif
2191       switch (code) {
2192         case lir_shl:  __ slw(dest->as_register(), left->as_register(), tmp->as_register()); break;
2193         case lir_shr:  __ sraw(dest->as_register(), left->as_register(), tmp->as_register()); break;
2194         case lir_ushr: __ srw(dest->as_register(), left->as_register(), tmp->as_register()); break;
2195         default: ShouldNotReachHere();
2196       }
2197   } else {
2198     __ rldicl(tmp->as_register(), count->as_register(), 0, 64-6);
2199     switch (code) {
2200       case lir_shl:  __ sld(dest->as_register_lo(), left->as_register_lo(), tmp->as_register()); break;
2201       case lir_shr:  __ srad(dest->as_register_lo(), left->as_register_lo(), tmp->as_register()); break;
2202       case lir_ushr: __ srd(dest->as_register_lo(), left->as_register_lo(), tmp->as_register()); break;
2203       default: ShouldNotReachHere();
2204     }
2205   }
2206 }
2207 
2208 
2209 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2210 #ifdef _LP64
2211   if (left->type() == T_OBJECT) {
2212     count = count & 63;  // Shouldn't shift by more than sizeof(intptr_t).
2213     if (count == 0) { __ mr_if_needed(dest->as_register_lo(), left->as_register()); }
2214     else {
2215       switch (code) {
2216         case lir_shl:  __ sldi(dest->as_register_lo(), left->as_register(), count); break;
2217         case lir_shr:  __ sradi(dest->as_register_lo(), left->as_register(), count); break;
2218         case lir_ushr: __ srdi(dest->as_register_lo(), left->as_register(), count); break;
2219         default: ShouldNotReachHere();
2220       }
2221     }
2222     return;
2223   }
2224 #endif
2225 
2226   if (dest->is_single_cpu()) {
2227     count = count & 0x1F; // Java spec
2228     if (count == 0) { __ mr_if_needed(dest->as_register(), left->as_register()); }
2229     else {
2230       switch (code) {
2231         case lir_shl: __ slwi(dest->as_register(), left->as_register(), count); break;
2232         case lir_shr:  __ srawi(dest->as_register(), left->as_register(), count); break;
2233         case lir_ushr: __ srwi(dest->as_register(), left->as_register(), count); break;
2234         default: ShouldNotReachHere();
2235       }
2236     }
2237   } else if (dest->is_double_cpu()) {
2238     count = count & 63; // Java spec
2239     if (count == 0) { __ mr_if_needed(dest->as_pointer_register(), left->as_pointer_register()); }
2240     else {
2241       switch (code) {
2242         case lir_shl:  __ sldi(dest->as_pointer_register(), left->as_pointer_register(), count); break;
2243         case lir_shr:  __ sradi(dest->as_pointer_register(), left->as_pointer_register(), count); break;
2244         case lir_ushr: __ srdi(dest->as_pointer_register(), left->as_pointer_register(), count); break;
2245         default: ShouldNotReachHere();
2246       }
2247     }
2248   } else {
2249     ShouldNotReachHere();
2250   }
2251 }
2252 
2253 
2254 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
2255   if (op->init_check()) {
2256     if (!os::zero_page_read_protected() || !ImplicitNullChecks) {
2257       explicit_null_check(op->klass()->as_register(), op->stub()->info());
2258     } else {
2259       add_debug_info_for_null_check_here(op->stub()->info());
2260     }
2261     __ lbz(op->tmp1()->as_register(),
2262            in_bytes(InstanceKlass::init_state_offset()), op->klass()->as_register());
2263     __ cmpwi(CCR0, op->tmp1()->as_register(), InstanceKlass::fully_initialized);
2264     __ bc_far_optimized(Assembler::bcondCRbiIs0, __ bi0(CCR0, Assembler::equal), *op->stub()->entry());
2265   }
2266   __ allocate_object(op->obj()->as_register(),
2267                      op->tmp1()->as_register(),
2268                      op->tmp2()->as_register(),
2269                      op->tmp3()->as_register(),
2270                      op->header_size(),
2271                      op->object_size(),
2272                      op->klass()->as_register(),
2273                      *op->stub()->entry());
2274 
2275   __ bind(*op->stub()->continuation());
2276   __ verify_oop(op->obj()->as_register(), FILE_AND_LINE);
2277 }
2278 
2279 
2280 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
2281   LP64_ONLY( __ extsw(op->len()->as_register(), op->len()->as_register()); )
2282   if (UseSlowPath ||
2283       (!UseFastNewObjectArray && (is_reference_type(op->type()))) ||
2284       (!UseFastNewTypeArray   && (!is_reference_type(op->type())))) {
2285     __ b(*op->stub()->entry());
2286   } else {
2287     __ allocate_array(op->obj()->as_register(),
2288                       op->len()->as_register(),
2289                       op->tmp1()->as_register(),
2290                       op->tmp2()->as_register(),
2291                       op->tmp3()->as_register(),
2292                       arrayOopDesc::header_size(op->type()),
2293                       type2aelembytes(op->type()),
2294                       op->klass()->as_register(),
2295                       *op->stub()->entry());
2296   }
2297   __ bind(*op->stub()->continuation());
2298 }
2299 
2300 
2301 void LIR_Assembler::type_profile_helper(Register mdo, int mdo_offset_bias,
2302                                         ciMethodData *md, ciProfileData *data,
2303                                         Register recv, Register tmp1, Label* update_done) {
2304   uint i;
2305   for (i = 0; i < VirtualCallData::row_limit(); i++) {
2306     Label next_test;
2307     // See if the receiver is receiver[n].
2308     __ ld(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) - mdo_offset_bias, mdo);
2309     __ verify_klass_ptr(tmp1);
2310     __ cmpd(CCR0, recv, tmp1);
2311     __ bne(CCR0, next_test);
2312 
2313     __ ld(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2314     __ addi(tmp1, tmp1, DataLayout::counter_increment);
2315     __ std(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2316     __ b(*update_done);
2317 
2318     __ bind(next_test);
2319   }
2320 
2321   // Didn't find receiver; find next empty slot and fill it in.
2322   for (i = 0; i < VirtualCallData::row_limit(); i++) {
2323     Label next_test;
2324     __ ld(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) - mdo_offset_bias, mdo);
2325     __ cmpdi(CCR0, tmp1, 0);
2326     __ bne(CCR0, next_test);
2327     __ li(tmp1, DataLayout::counter_increment);
2328     __ std(recv, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) - mdo_offset_bias, mdo);
2329     __ std(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2330     __ b(*update_done);
2331 
2332     __ bind(next_test);
2333   }
2334 }
2335 
2336 
2337 void LIR_Assembler::setup_md_access(ciMethod* method, int bci,
2338                                     ciMethodData*& md, ciProfileData*& data, int& mdo_offset_bias) {
2339   md = method->method_data_or_null();
2340   assert(md != NULL, "Sanity");
2341   data = md->bci_to_data(bci);
2342   assert(data != NULL,       "need data for checkcast");
2343   assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
2344   if (!Assembler::is_simm16(md->byte_offset_of_slot(data, DataLayout::header_offset()) + data->size_in_bytes())) {
2345     // The offset is large so bias the mdo by the base of the slot so
2346     // that the ld can use simm16s to reference the slots of the data.
2347     mdo_offset_bias = md->byte_offset_of_slot(data, DataLayout::header_offset());
2348   }
2349 }
2350 
2351 
2352 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
2353   const Register obj = op->object()->as_register(); // Needs to live in this register at safepoint (patching stub).
2354   Register k_RInfo = op->tmp1()->as_register();
2355   Register klass_RInfo = op->tmp2()->as_register();
2356   Register Rtmp1 = op->tmp3()->as_register();
2357   Register dst = op->result_opr()->as_register();
2358   ciKlass* k = op->klass();
2359   bool should_profile = op->should_profile();
2360   // Attention: do_temp(opTypeCheck->_object) is not used, i.e. obj may be same as one of the temps.
2361   bool reg_conflict = false;
2362   if (obj == k_RInfo) {
2363     k_RInfo = dst;
2364     reg_conflict = true;
2365   } else if (obj == klass_RInfo) {
2366     klass_RInfo = dst;
2367     reg_conflict = true;
2368   } else if (obj == Rtmp1) {
2369     Rtmp1 = dst;
2370     reg_conflict = true;
2371   }
2372   assert_different_registers(obj, k_RInfo, klass_RInfo, Rtmp1);
2373 
2374   __ cmpdi(CCR0, obj, 0);
2375 
2376   ciMethodData* md = NULL;
2377   ciProfileData* data = NULL;
2378   int mdo_offset_bias = 0;
2379   if (should_profile) {
2380     ciMethod* method = op->profiled_method();
2381     assert(method != NULL, "Should have method");
2382     setup_md_access(method, op->profiled_bci(), md, data, mdo_offset_bias);
2383 
2384     Register mdo      = k_RInfo;
2385     Register data_val = Rtmp1;
2386     Label not_null;
2387     __ bne(CCR0, not_null);
2388     metadata2reg(md->constant_encoding(), mdo);
2389     __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2390     __ lbz(data_val, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias, mdo);
2391     __ ori(data_val, data_val, BitData::null_seen_byte_constant());
2392     __ stb(data_val, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias, mdo);
2393     __ b(*obj_is_null);
2394     __ bind(not_null);
2395   } else {
2396     __ beq(CCR0, *obj_is_null);
2397   }
2398 
2399   // get object class
2400   __ load_klass(klass_RInfo, obj);
2401 
2402   if (k->is_loaded()) {
2403     metadata2reg(k->constant_encoding(), k_RInfo);
2404   } else {
2405     klass2reg_with_patching(k_RInfo, op->info_for_patch());
2406   }
2407 
2408   Label profile_cast_failure, failure_restore_obj, profile_cast_success;
2409   Label *failure_target = should_profile ? &profile_cast_failure : failure;
2410   Label *success_target = should_profile ? &profile_cast_success : success;
2411 
2412   if (op->fast_check()) {
2413     assert_different_registers(klass_RInfo, k_RInfo);
2414     __ cmpd(CCR0, k_RInfo, klass_RInfo);
2415     if (should_profile) {
2416       __ bne(CCR0, *failure_target);
2417       // Fall through to success case.
2418     } else {
2419       __ beq(CCR0, *success);
2420       // Fall through to failure case.
2421     }
2422   } else {
2423     bool need_slow_path = true;
2424     if (k->is_loaded()) {
2425       if ((int) k->super_check_offset() != in_bytes(Klass::secondary_super_cache_offset())) {
2426         need_slow_path = false;
2427       }
2428       // Perform the fast part of the checking logic.
2429       __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, R0, (need_slow_path ? success_target : NULL),
2430                                        failure_target, NULL, RegisterOrConstant(k->super_check_offset()));
2431     } else {
2432       // Perform the fast part of the checking logic.
2433       __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, R0, success_target, failure_target);
2434     }
2435     if (!need_slow_path) {
2436       if (!should_profile) { __ b(*success); }
2437     } else {
2438       // Call out-of-line instance of __ check_klass_subtype_slow_path(...):
2439       address entry = Runtime1::entry_for(Runtime1::slow_subtype_check_id);
2440       // Stub needs fixed registers (tmp1-3).
2441       Register original_k_RInfo = op->tmp1()->as_register();
2442       Register original_klass_RInfo = op->tmp2()->as_register();
2443       Register original_Rtmp1 = op->tmp3()->as_register();
2444       bool keep_obj_alive = reg_conflict && (op->code() == lir_checkcast);
2445       bool keep_klass_RInfo_alive = (obj == original_klass_RInfo) && should_profile;
2446       if (keep_obj_alive && (obj != original_Rtmp1)) { __ mr(R0, obj); }
2447       __ mr_if_needed(original_k_RInfo, k_RInfo);
2448       __ mr_if_needed(original_klass_RInfo, klass_RInfo);
2449       if (keep_obj_alive) { __ mr(dst, (obj == original_Rtmp1) ? obj : R0); }
2450       //__ load_const_optimized(original_Rtmp1, entry, R0);
2451       __ calculate_address_from_global_toc(original_Rtmp1, entry, true, true, false);
2452       __ mtctr(original_Rtmp1);
2453       __ bctrl(); // sets CR0
2454       if (keep_obj_alive) {
2455         if (keep_klass_RInfo_alive) { __ mr(R0, obj); }
2456         __ mr(obj, dst);
2457       }
2458       if (should_profile) {
2459         __ bne(CCR0, *failure_target);
2460         if (keep_klass_RInfo_alive) { __ mr(klass_RInfo, keep_obj_alive ? R0 : obj); }
2461         // Fall through to success case.
2462       } else {
2463         __ beq(CCR0, *success);
2464         // Fall through to failure case.
2465       }
2466     }
2467   }
2468 
2469   if (should_profile) {
2470     Register mdo = k_RInfo, recv = klass_RInfo;
2471     assert_different_registers(mdo, recv, Rtmp1);
2472     __ bind(profile_cast_success);
2473     metadata2reg(md->constant_encoding(), mdo);
2474     __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2475     type_profile_helper(mdo, mdo_offset_bias, md, data, recv, Rtmp1, success);
2476     __ b(*success);
2477 
2478     // Cast failure case.
2479     __ bind(profile_cast_failure);
2480     metadata2reg(md->constant_encoding(), mdo);
2481     __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2482     __ ld(Rtmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2483     __ addi(Rtmp1, Rtmp1, -DataLayout::counter_increment);
2484     __ std(Rtmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2485   }
2486 
2487   __ bind(*failure);
2488 }
2489 
2490 
2491 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
2492   LIR_Code code = op->code();
2493   if (code == lir_store_check) {
2494     Register value = op->object()->as_register();
2495     Register array = op->array()->as_register();
2496     Register k_RInfo = op->tmp1()->as_register();
2497     Register klass_RInfo = op->tmp2()->as_register();
2498     Register Rtmp1 = op->tmp3()->as_register();
2499     bool should_profile = op->should_profile();
2500 
2501     __ verify_oop(value, FILE_AND_LINE);
2502     CodeStub* stub = op->stub();
2503     // Check if it needs to be profiled.
2504     ciMethodData* md = NULL;
2505     ciProfileData* data = NULL;
2506     int mdo_offset_bias = 0;
2507     if (should_profile) {
2508       ciMethod* method = op->profiled_method();
2509       assert(method != NULL, "Should have method");
2510       setup_md_access(method, op->profiled_bci(), md, data, mdo_offset_bias);
2511     }
2512     Label profile_cast_success, failure, done;
2513     Label *success_target = should_profile ? &profile_cast_success : &done;
2514 
2515     __ cmpdi(CCR0, value, 0);
2516     if (should_profile) {
2517       Label not_null;
2518       __ bne(CCR0, not_null);
2519       Register mdo      = k_RInfo;
2520       Register data_val = Rtmp1;
2521       metadata2reg(md->constant_encoding(), mdo);
2522       __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2523       __ lbz(data_val, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias, mdo);
2524       __ ori(data_val, data_val, BitData::null_seen_byte_constant());
2525       __ stb(data_val, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias, mdo);
2526       __ b(done);
2527       __ bind(not_null);
2528     } else {
2529       __ beq(CCR0, done);
2530     }
2531     if (!os::zero_page_read_protected() || !ImplicitNullChecks) {
2532       explicit_null_check(array, op->info_for_exception());
2533     } else {
2534       add_debug_info_for_null_check_here(op->info_for_exception());
2535     }
2536     __ load_klass(k_RInfo, array);
2537     __ load_klass(klass_RInfo, value);
2538 
2539     // Get instance klass.
2540     __ ld(k_RInfo, in_bytes(ObjArrayKlass::element_klass_offset()), k_RInfo);
2541     // Perform the fast part of the checking logic.
2542     __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, R0, success_target, &failure, NULL);
2543 
2544     // Call out-of-line instance of __ check_klass_subtype_slow_path(...):
2545     const address slow_path = Runtime1::entry_for(Runtime1::slow_subtype_check_id);
2546     //__ load_const_optimized(R0, slow_path);
2547     __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(slow_path));
2548     __ mtctr(R0);
2549     __ bctrl(); // sets CR0
2550     if (!should_profile) {
2551       __ beq(CCR0, done);
2552       __ bind(failure);
2553     } else {
2554       __ bne(CCR0, failure);
2555       // Fall through to the success case.
2556 
2557       Register mdo  = klass_RInfo, recv = k_RInfo, tmp1 = Rtmp1;
2558       assert_different_registers(value, mdo, recv, tmp1);
2559       __ bind(profile_cast_success);
2560       metadata2reg(md->constant_encoding(), mdo);
2561       __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2562       __ load_klass(recv, value);
2563       type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, &done);
2564       __ b(done);
2565 
2566       // Cast failure case.
2567       __ bind(failure);
2568       metadata2reg(md->constant_encoding(), mdo);
2569       __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2570       Address data_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias);
2571       __ ld(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2572       __ addi(tmp1, tmp1, -DataLayout::counter_increment);
2573       __ std(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2574     }
2575     __ b(*stub->entry());
2576     __ bind(done);
2577 
2578   } else if (code == lir_checkcast) {
2579     Label success, failure;
2580     emit_typecheck_helper(op, &success, /*fallthru*/&failure, &success);
2581     __ b(*op->stub()->entry());
2582     __ align(32, 12);
2583     __ bind(success);
2584     __ mr_if_needed(op->result_opr()->as_register(), op->object()->as_register());
2585   } else if (code == lir_instanceof) {
2586     Register dst = op->result_opr()->as_register();
2587     Label success, failure, done;
2588     emit_typecheck_helper(op, &success, /*fallthru*/&failure, &failure);
2589     __ li(dst, 0);
2590     __ b(done);
2591     __ align(32, 12);
2592     __ bind(success);
2593     __ li(dst, 1);
2594     __ bind(done);
2595   } else {
2596     ShouldNotReachHere();
2597   }
2598 }
2599 
2600 
2601 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
2602   Register addr = op->addr()->as_pointer_register();
2603   Register cmp_value = noreg, new_value = noreg;
2604   bool is_64bit = false;
2605 
2606   if (op->code() == lir_cas_long) {
2607     cmp_value = op->cmp_value()->as_register_lo();
2608     new_value = op->new_value()->as_register_lo();
2609     is_64bit = true;
2610   } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj) {
2611     cmp_value = op->cmp_value()->as_register();
2612     new_value = op->new_value()->as_register();
2613     if (op->code() == lir_cas_obj) {
2614       if (UseCompressedOops) {
2615         Register t1 = op->tmp1()->as_register();
2616         Register t2 = op->tmp2()->as_register();
2617         cmp_value = __ encode_heap_oop(t1, cmp_value);
2618         new_value = __ encode_heap_oop(t2, new_value);
2619       } else {
2620         is_64bit = true;
2621       }
2622     }
2623   } else {
2624     Unimplemented();
2625   }
2626 
2627   if (is_64bit) {
2628     __ cmpxchgd(BOOL_RESULT, /*current_value=*/R0, cmp_value, new_value, addr,
2629                 MacroAssembler::MemBarNone,
2630                 MacroAssembler::cmpxchgx_hint_atomic_update(),
2631                 noreg, NULL, /*check without ldarx first*/true);
2632   } else {
2633     __ cmpxchgw(BOOL_RESULT, /*current_value=*/R0, cmp_value, new_value, addr,
2634                 MacroAssembler::MemBarNone,
2635                 MacroAssembler::cmpxchgx_hint_atomic_update(),
2636                 noreg, /*check without ldarx first*/true);
2637   }
2638 
2639   if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
2640     __ isync();
2641   } else {
2642     __ sync();
2643   }
2644 }
2645 
2646 void LIR_Assembler::breakpoint() {
2647   __ illtrap();
2648 }
2649 
2650 
2651 void LIR_Assembler::push(LIR_Opr opr) {
2652   Unimplemented();
2653 }
2654 
2655 void LIR_Assembler::pop(LIR_Opr opr) {
2656   Unimplemented();
2657 }
2658 
2659 
2660 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst_opr) {
2661   Address mon_addr = frame_map()->address_for_monitor_object(monitor_no);
2662   Register dst = dst_opr->as_register();
2663   Register reg = mon_addr.base();
2664   int offset = mon_addr.disp();
2665   // Compute pointer to BasicLock.
2666   __ add_const_optimized(dst, reg, offset);
2667 }
2668 
2669 
2670 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
2671   Register obj = op->obj_opr()->as_register();
2672   Register hdr = op->hdr_opr()->as_register();
2673   Register lock = op->lock_opr()->as_register();
2674 
2675   // Obj may not be an oop.
2676   if (op->code() == lir_lock) {
2677     MonitorEnterStub* stub = (MonitorEnterStub*)op->stub();
2678     // always do slow locking
2679     // note: The slow locking code could be inlined here, however if we use
2680     //       slow locking, speed doesn't matter anyway and this solution is
2681     //       simpler and requires less duplicated code - additionally, the
2682     //       slow locking code is the same in either case which simplifies
2683     //       debugging.
2684     if (op->info() != NULL) {
2685       add_debug_info_for_null_check_here(op->info());
2686       __ null_check(obj);
2687     }
2688     __ b(*op->stub()->entry());
2689   } else {
2690     assert (op->code() == lir_unlock, "Invalid code, expected lir_unlock");
2691     // always do slow unlocking
2692     // note: The slow unlocking code could be inlined here, however if we use
2693     //       slow unlocking, speed doesn't matter anyway and this solution is
2694     //       simpler and requires less duplicated code - additionally, the
2695     //       slow unlocking code is the same in either case which simplifies
2696     //       debugging.
2697     __ b(*op->stub()->entry());
2698   }
2699   __ bind(*op->stub()->continuation());
2700 }
2701 
2702 void LIR_Assembler::emit_load_klass(LIR_OpLoadKlass* op) {
2703   Register obj = op->obj()->as_pointer_register();
2704   Register result = op->result_opr()->as_pointer_register();
2705 
2706   CodeEmitInfo* info = op->info();
2707   if (info != NULL) {
2708     if (!os::zero_page_read_protected() || !ImplicitNullChecks) {
2709       explicit_null_check(obj, info);
2710     } else {
2711       add_debug_info_for_null_check_here(info);
2712     }
2713   }
2714 
2715   if (UseCompressedClassPointers) {
2716     __ lwz(result, oopDesc::klass_offset_in_bytes(), obj);
2717     __ decode_klass_not_null(result);
2718   } else {
2719     __ ld(result, oopDesc::klass_offset_in_bytes(), obj);
2720   }
2721 }
2722 
2723 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
2724   ciMethod* method = op->profiled_method();
2725   int bci          = op->profiled_bci();
2726   ciMethod* callee = op->profiled_callee();
2727 
2728   // Update counter for all call types.
2729   ciMethodData* md = method->method_data_or_null();
2730   assert(md != NULL, "Sanity");
2731   ciProfileData* data = md->bci_to_data(bci);
2732   assert(data != NULL && data->is_CounterData(), "need CounterData for calls");
2733   assert(op->mdo()->is_single_cpu(),  "mdo must be allocated");
2734   Register mdo = op->mdo()->as_register();
2735 #ifdef _LP64
2736   assert(op->tmp1()->is_double_cpu(), "tmp1 must be allocated");
2737   Register tmp1 = op->tmp1()->as_register_lo();
2738 #else
2739   assert(op->tmp1()->is_single_cpu(), "tmp1 must be allocated");
2740   Register tmp1 = op->tmp1()->as_register();
2741 #endif
2742   metadata2reg(md->constant_encoding(), mdo);
2743   int mdo_offset_bias = 0;
2744   if (!Assembler::is_simm16(md->byte_offset_of_slot(data, CounterData::count_offset()) +
2745                             data->size_in_bytes())) {
2746     // The offset is large so bias the mdo by the base of the slot so
2747     // that the ld can use simm16s to reference the slots of the data.
2748     mdo_offset_bias = md->byte_offset_of_slot(data, CounterData::count_offset());
2749     __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2750   }
2751 
2752   // Perform additional virtual call profiling for invokevirtual and
2753   // invokeinterface bytecodes
2754   if (op->should_profile_receiver_type()) {
2755     assert(op->recv()->is_single_cpu(), "recv must be allocated");
2756     Register recv = op->recv()->as_register();
2757     assert_different_registers(mdo, tmp1, recv);
2758     assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
2759     ciKlass* known_klass = op->known_holder();
2760     if (C1OptimizeVirtualCallProfiling && known_klass != NULL) {
2761       // We know the type that will be seen at this call site; we can
2762       // statically update the MethodData* rather than needing to do
2763       // dynamic tests on the receiver type.
2764 
2765       // NOTE: we should probably put a lock around this search to
2766       // avoid collisions by concurrent compilations.
2767       ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
2768       uint i;
2769       for (i = 0; i < VirtualCallData::row_limit(); i++) {
2770         ciKlass* receiver = vc_data->receiver(i);
2771         if (known_klass->equals(receiver)) {
2772           __ ld(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2773           __ addi(tmp1, tmp1, DataLayout::counter_increment);
2774           __ std(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2775           return;
2776         }
2777       }
2778 
2779       // Receiver type not found in profile data; select an empty slot.
2780 
2781       // Note that this is less efficient than it should be because it
2782       // always does a write to the receiver part of the
2783       // VirtualCallData rather than just the first time.
2784       for (i = 0; i < VirtualCallData::row_limit(); i++) {
2785         ciKlass* receiver = vc_data->receiver(i);
2786         if (receiver == NULL) {
2787           metadata2reg(known_klass->constant_encoding(), tmp1);
2788           __ std(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)) - mdo_offset_bias, mdo);
2789 
2790           __ ld(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2791           __ addi(tmp1, tmp1, DataLayout::counter_increment);
2792           __ std(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2793           return;
2794         }
2795       }
2796     } else {
2797       __ load_klass(recv, recv);
2798       Label update_done;
2799       type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, &update_done);
2800       // Receiver did not match any saved receiver and there is no empty row for it.
2801       // Increment total counter to indicate polymorphic case.
2802       __ ld(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2803       __ addi(tmp1, tmp1, DataLayout::counter_increment);
2804       __ std(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2805 
2806       __ bind(update_done);
2807     }
2808   } else {
2809     // Static call
2810     __ ld(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2811     __ addi(tmp1, tmp1, DataLayout::counter_increment);
2812     __ std(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2813   }
2814 }
2815 
2816 
2817 void LIR_Assembler::align_backward_branch_target() {
2818   __ align(32, 12); // Insert up to 3 nops to align with 32 byte boundary.
2819 }
2820 
2821 
2822 void LIR_Assembler::emit_delay(LIR_OpDelay* op) {
2823   Unimplemented();
2824 }
2825 
2826 
2827 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) {
2828   // tmp must be unused
2829   assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2830   assert(left->is_register(), "can only handle registers");
2831 
2832   if (left->is_single_cpu()) {
2833     __ neg(dest->as_register(), left->as_register());
2834   } else if (left->is_single_fpu()) {
2835     __ fneg(dest->as_float_reg(), left->as_float_reg());
2836   } else if (left->is_double_fpu()) {
2837     __ fneg(dest->as_double_reg(), left->as_double_reg());
2838   } else {
2839     assert (left->is_double_cpu(), "Must be a long");
2840     __ neg(dest->as_register_lo(), left->as_register_lo());
2841   }
2842 }
2843 
2844 
2845 void LIR_Assembler::rt_call(LIR_Opr result, address dest,
2846                             const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
2847   // Stubs: Called via rt_call, but dest is a stub address (no function descriptor).
2848   if (dest == Runtime1::entry_for(Runtime1::register_finalizer_id) ||
2849       dest == Runtime1::entry_for(Runtime1::new_multi_array_id   )) {
2850     //__ load_const_optimized(R0, dest);
2851     __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(dest));
2852     __ mtctr(R0);
2853     __ bctrl();
2854     assert(info != NULL, "sanity");
2855     add_call_info_here(info);
2856     return;
2857   }
2858 
2859   __ call_c_with_frame_resize(dest, /*no resizing*/ 0);
2860   if (info != NULL) {
2861     add_call_info_here(info);
2862   }
2863 }
2864 
2865 
2866 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
2867   ShouldNotReachHere(); // Not needed on _LP64.
2868 }
2869 
2870 void LIR_Assembler::membar() {
2871   __ fence();
2872 }
2873 
2874 void LIR_Assembler::membar_acquire() {
2875   __ acquire();
2876 }
2877 
2878 void LIR_Assembler::membar_release() {
2879   __ release();
2880 }
2881 
2882 void LIR_Assembler::membar_loadload() {
2883   __ membar(Assembler::LoadLoad);
2884 }
2885 
2886 void LIR_Assembler::membar_storestore() {
2887   __ membar(Assembler::StoreStore);
2888 }
2889 
2890 void LIR_Assembler::membar_loadstore() {
2891   __ membar(Assembler::LoadStore);
2892 }
2893 
2894 void LIR_Assembler::membar_storeload() {
2895   __ membar(Assembler::StoreLoad);
2896 }
2897 
2898 void LIR_Assembler::on_spin_wait() {
2899   Unimplemented();
2900 }
2901 
2902 void LIR_Assembler::leal(LIR_Opr addr_opr, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
2903   LIR_Address* addr = addr_opr->as_address_ptr();
2904   assert(addr->scale() == LIR_Address::times_1, "no scaling on this platform");
2905 
2906   if (addr->index()->is_illegal()) {
2907     if (patch_code != lir_patch_none) {
2908       PatchingStub* patch = new PatchingStub(_masm, PatchingStub::access_field_id);
2909       __ load_const32(R0, 0); // patchable int
2910       __ add(dest->as_pointer_register(), addr->base()->as_pointer_register(), R0);
2911       patching_epilog(patch, patch_code, addr->base()->as_register(), info);
2912     } else {
2913       __ add_const_optimized(dest->as_pointer_register(), addr->base()->as_pointer_register(), addr->disp());
2914     }
2915   } else {
2916     assert(patch_code == lir_patch_none, "Patch code not supported");
2917     assert(addr->disp() == 0, "can't have both: index and disp");
2918     __ add(dest->as_pointer_register(), addr->index()->as_pointer_register(), addr->base()->as_pointer_register());
2919   }
2920 }
2921 
2922 
2923 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
2924   ShouldNotReachHere();
2925 }
2926 
2927 
2928 #ifdef ASSERT
2929 // Emit run-time assertion.
2930 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
2931   Unimplemented();
2932 }
2933 #endif
2934 
2935 
2936 void LIR_Assembler::peephole(LIR_List* lir) {
2937   // Optimize instruction pairs before emitting.
2938   LIR_OpList* inst = lir->instructions_list();
2939   for (int i = 1; i < inst->length(); i++) {
2940     LIR_Op* op = inst->at(i);
2941 
2942     // 2 register-register-moves
2943     if (op->code() == lir_move) {
2944       LIR_Opr in2  = ((LIR_Op1*)op)->in_opr(),
2945               res2 = ((LIR_Op1*)op)->result_opr();
2946       if (in2->is_register() && res2->is_register()) {
2947         LIR_Op* prev = inst->at(i - 1);
2948         if (prev && prev->code() == lir_move) {
2949           LIR_Opr in1  = ((LIR_Op1*)prev)->in_opr(),
2950                   res1 = ((LIR_Op1*)prev)->result_opr();
2951           if (in1->is_same_register(res2) && in2->is_same_register(res1)) {
2952             inst->remove_at(i);
2953           }
2954         }
2955       }
2956     }
2957 
2958   }
2959   return;
2960 }
2961 
2962 
2963 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) {
2964   const LIR_Address *addr = src->as_address_ptr();
2965   assert(addr->disp() == 0 && addr->index()->is_illegal(), "use leal!");
2966   const Register Rptr = addr->base()->as_pointer_register(),
2967                  Rtmp = tmp->as_register();
2968   Register Rco = noreg;
2969   if (UseCompressedOops && data->is_oop()) {
2970     Rco = __ encode_heap_oop(Rtmp, data->as_register());
2971   }
2972 
2973   Label Lretry;
2974   __ bind(Lretry);
2975 
2976   if (data->type() == T_INT) {
2977     const Register Rold = dest->as_register(),
2978                    Rsrc = data->as_register();
2979     assert_different_registers(Rptr, Rtmp, Rold, Rsrc);
2980     __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
2981     if (code == lir_xadd) {
2982       __ add(Rtmp, Rsrc, Rold);
2983       __ stwcx_(Rtmp, Rptr);
2984     } else {
2985       __ stwcx_(Rsrc, Rptr);
2986     }
2987   } else if (data->is_oop()) {
2988     assert(code == lir_xchg, "xadd for oops");
2989     const Register Rold = dest->as_register();
2990     if (UseCompressedOops) {
2991       assert_different_registers(Rptr, Rold, Rco);
2992       __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
2993       __ stwcx_(Rco, Rptr);
2994     } else {
2995       const Register Robj = data->as_register();
2996       assert_different_registers(Rptr, Rold, Robj);
2997       __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
2998       __ stdcx_(Robj, Rptr);
2999     }
3000   } else if (data->type() == T_LONG) {
3001     const Register Rold = dest->as_register_lo(),
3002                    Rsrc = data->as_register_lo();
3003     assert_different_registers(Rptr, Rtmp, Rold, Rsrc);
3004     __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3005     if (code == lir_xadd) {
3006       __ add(Rtmp, Rsrc, Rold);
3007       __ stdcx_(Rtmp, Rptr);
3008     } else {
3009       __ stdcx_(Rsrc, Rptr);
3010     }
3011   } else {
3012     ShouldNotReachHere();
3013   }
3014 
3015   if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
3016     __ bne_predict_not_taken(CCR0, Lretry);
3017   } else {
3018     __ bne(                  CCR0, Lretry);
3019   }
3020 
3021   if (UseCompressedOops && data->is_oop()) {
3022     __ decode_heap_oop(dest->as_register());
3023   }
3024 }
3025 
3026 
3027 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
3028   Register obj = op->obj()->as_register();
3029   Register tmp = op->tmp()->as_pointer_register();
3030   LIR_Address* mdo_addr = op->mdp()->as_address_ptr();
3031   ciKlass* exact_klass = op->exact_klass();
3032   intptr_t current_klass = op->current_klass();
3033   bool not_null = op->not_null();
3034   bool no_conflict = op->no_conflict();
3035 
3036   Label Lupdate, Ldo_update, Ldone;
3037 
3038   bool do_null = !not_null;
3039   bool exact_klass_set = exact_klass != NULL && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
3040   bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
3041 
3042   assert(do_null || do_update, "why are we here?");
3043   assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
3044 
3045   __ verify_oop(obj, FILE_AND_LINE);
3046 
3047   if (do_null) {
3048     if (!TypeEntries::was_null_seen(current_klass)) {
3049       __ cmpdi(CCR0, obj, 0);
3050       __ bne(CCR0, Lupdate);
3051       __ ld(R0, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3052       __ ori(R0, R0, TypeEntries::null_seen);
3053       if (do_update) {
3054         __ b(Ldo_update);
3055       } else {
3056         __ std(R0, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3057       }
3058     } else {
3059       if (do_update) {
3060         __ cmpdi(CCR0, obj, 0);
3061         __ beq(CCR0, Ldone);
3062       }
3063     }
3064 #ifdef ASSERT
3065   } else {
3066     __ cmpdi(CCR0, obj, 0);
3067     __ bne(CCR0, Lupdate);
3068     __ stop("unexpected null obj");
3069 #endif
3070   }
3071 
3072   __ bind(Lupdate);
3073   if (do_update) {
3074     Label Lnext;
3075     const Register klass = R29_TOC; // kill and reload
3076     bool klass_reg_used = false;
3077 #ifdef ASSERT
3078     if (exact_klass != NULL) {
3079       Label ok;
3080       klass_reg_used = true;
3081       __ load_klass(klass, obj);
3082       metadata2reg(exact_klass->constant_encoding(), R0);
3083       __ cmpd(CCR0, klass, R0);
3084       __ beq(CCR0, ok);
3085       __ stop("exact klass and actual klass differ");
3086       __ bind(ok);
3087     }
3088 #endif
3089 
3090     if (!no_conflict) {
3091       if (exact_klass == NULL || TypeEntries::is_type_none(current_klass)) {
3092         klass_reg_used = true;
3093         if (exact_klass != NULL) {
3094           __ ld(tmp, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3095           metadata2reg(exact_klass->constant_encoding(), klass);
3096         } else {
3097           __ load_klass(klass, obj);
3098           __ ld(tmp, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register()); // may kill obj
3099         }
3100 
3101         // Like InterpreterMacroAssembler::profile_obj_type
3102         __ clrrdi(R0, tmp, exact_log2(-TypeEntries::type_klass_mask));
3103         // Basically same as andi(R0, tmp, TypeEntries::type_klass_mask);
3104         __ cmpd(CCR1, R0, klass);
3105         // Klass seen before, nothing to do (regardless of unknown bit).
3106         //beq(CCR1, do_nothing);
3107 
3108         __ andi_(R0, klass, TypeEntries::type_unknown);
3109         // Already unknown. Nothing to do anymore.
3110         //bne(CCR0, do_nothing);
3111         __ crorc(CCR0, Assembler::equal, CCR1, Assembler::equal); // cr0 eq = cr1 eq or cr0 ne
3112         __ beq(CCR0, Lnext);
3113 
3114         if (TypeEntries::is_type_none(current_klass)) {
3115           __ clrrdi_(R0, tmp, exact_log2(-TypeEntries::type_mask));
3116           __ orr(R0, klass, tmp); // Combine klass and null_seen bit (only used if (tmp & type_mask)==0).
3117           __ beq(CCR0, Ldo_update); // First time here. Set profile type.
3118         }
3119 
3120       } else {
3121         assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
3122                ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
3123 
3124         __ ld(tmp, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3125         __ andi_(R0, tmp, TypeEntries::type_unknown);
3126         // Already unknown. Nothing to do anymore.
3127         __ bne(CCR0, Lnext);
3128       }
3129 
3130       // Different than before. Cannot keep accurate profile.
3131       __ ori(R0, tmp, TypeEntries::type_unknown);
3132     } else {
3133       // There's a single possible klass at this profile point
3134       assert(exact_klass != NULL, "should be");
3135       __ ld(tmp, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3136 
3137       if (TypeEntries::is_type_none(current_klass)) {
3138         klass_reg_used = true;
3139         metadata2reg(exact_klass->constant_encoding(), klass);
3140 
3141         __ clrrdi(R0, tmp, exact_log2(-TypeEntries::type_klass_mask));
3142         // Basically same as andi(R0, tmp, TypeEntries::type_klass_mask);
3143         __ cmpd(CCR1, R0, klass);
3144         // Klass seen before, nothing to do (regardless of unknown bit).
3145         __ beq(CCR1, Lnext);
3146 #ifdef ASSERT
3147         {
3148           Label ok;
3149           __ clrrdi_(R0, tmp, exact_log2(-TypeEntries::type_mask));
3150           __ beq(CCR0, ok); // First time here.
3151 
3152           __ stop("unexpected profiling mismatch");
3153           __ bind(ok);
3154         }
3155 #endif
3156         // First time here. Set profile type.
3157         __ orr(R0, klass, tmp); // Combine klass and null_seen bit (only used if (tmp & type_mask)==0).
3158       } else {
3159         assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
3160                ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
3161 
3162         // Already unknown. Nothing to do anymore.
3163         __ andi_(R0, tmp, TypeEntries::type_unknown);
3164         __ bne(CCR0, Lnext);
3165 
3166         // Different than before. Cannot keep accurate profile.
3167         __ ori(R0, tmp, TypeEntries::type_unknown);
3168       }
3169     }
3170 
3171     __ bind(Ldo_update);
3172     __ std(R0, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3173 
3174     __ bind(Lnext);
3175     if (klass_reg_used) { __ load_const_optimized(R29_TOC, MacroAssembler::global_toc(), R0); } // reinit
3176   }
3177   __ bind(Ldone);
3178 }
3179 
3180 
3181 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
3182   assert(op->crc()->is_single_cpu(), "crc must be register");
3183   assert(op->val()->is_single_cpu(), "byte value must be register");
3184   assert(op->result_opr()->is_single_cpu(), "result must be register");
3185   Register crc = op->crc()->as_register();
3186   Register val = op->val()->as_register();
3187   Register res = op->result_opr()->as_register();
3188 
3189   assert_different_registers(val, crc, res);
3190 
3191   __ load_const_optimized(res, StubRoutines::crc_table_addr(), R0);
3192   __ kernel_crc32_singleByteReg(crc, val, res, true);
3193   __ mr(res, crc);
3194 }
3195 
3196 #undef __