1 /*
2 * Copyright (c) 2000, 2022, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2012, 2022 SAP SE. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "precompiled.hpp"
27 #include "asm/macroAssembler.inline.hpp"
28 #include "c1/c1_Compilation.hpp"
29 #include "c1/c1_LIRAssembler.hpp"
30 #include "c1/c1_MacroAssembler.hpp"
31 #include "c1/c1_Runtime1.hpp"
32 #include "c1/c1_ValueStack.hpp"
33 #include "ci/ciArrayKlass.hpp"
34 #include "ci/ciInstance.hpp"
35 #include "gc/shared/collectedHeap.hpp"
36 #include "memory/universe.hpp"
37 #include "nativeInst_ppc.hpp"
38 #include "oops/compressedOops.hpp"
39 #include "oops/objArrayKlass.hpp"
40 #include "runtime/frame.inline.hpp"
41 #include "runtime/os.inline.hpp"
42 #include "runtime/safepointMechanism.inline.hpp"
43 #include "runtime/sharedRuntime.hpp"
44 #include "runtime/stubRoutines.hpp"
45 #include "runtime/vm_version.hpp"
46 #include "utilities/macros.hpp"
47 #include "utilities/powerOfTwo.hpp"
48
49 #define __ _masm->
50
51
52 const ConditionRegister LIR_Assembler::BOOL_RESULT = CCR5;
53
54
55 bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
56 Unimplemented(); return false; // Currently not used on this platform.
57 }
58
59
60 LIR_Opr LIR_Assembler::receiverOpr() {
61 return FrameMap::R3_oop_opr;
62 }
63
64
65 LIR_Opr LIR_Assembler::osrBufferPointer() {
66 return FrameMap::R3_opr;
67 }
68
69
70 // This specifies the stack pointer decrement needed to build the frame.
71 int LIR_Assembler::initial_frame_size_in_bytes() const {
72 return in_bytes(frame_map()->framesize_in_bytes());
73 }
74
75
76 // Inline cache check: the inline cached class is in inline_cache_reg;
77 // we fetch the class of the receiver and compare it with the cached class.
78 // If they do not match we jump to slow case.
79 int LIR_Assembler::check_icache() {
80 int offset = __ offset();
81 __ inline_cache_check(R3_ARG1, R19_inline_cache_reg);
82 return offset;
83 }
84
85 void LIR_Assembler::clinit_barrier(ciMethod* method) {
86 assert(!method->holder()->is_not_initialized(), "initialization should have been started");
87
88 Label L_skip_barrier;
89 Register klass = R20;
90
91 metadata2reg(method->holder()->constant_encoding(), klass);
92 __ clinit_barrier(klass, R16_thread, &L_skip_barrier /*L_fast_path*/);
93
94 __ load_const_optimized(klass, SharedRuntime::get_handle_wrong_method_stub(), R0);
95 __ mtctr(klass);
96 __ bctr();
97
98 __ bind(L_skip_barrier);
99 }
100
101 void LIR_Assembler::osr_entry() {
102 // On-stack-replacement entry sequence:
103 //
104 // 1. Create a new compiled activation.
105 // 2. Initialize local variables in the compiled activation. The expression
106 // stack must be empty at the osr_bci; it is not initialized.
107 // 3. Jump to the continuation address in compiled code to resume execution.
108
109 // OSR entry point
110 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
111 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
112 ValueStack* entry_state = osr_entry->end()->state();
113 int number_of_locks = entry_state->locks_size();
114
115 // Create a frame for the compiled activation.
116 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes(), compilation()->max_monitors());
117
118 // OSR buffer is
119 //
120 // locals[nlocals-1..0]
121 // monitors[number_of_locks-1..0]
122 //
123 // Locals is a direct copy of the interpreter frame so in the osr buffer
124 // the first slot in the local array is the last local from the interpreter
125 // and the last slot is local[0] (receiver) from the interpreter.
126 //
127 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
128 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
129 // in the interpreter frame (the method lock if a sync method).
130
131 // Initialize monitors in the compiled activation.
132 // R3: pointer to osr buffer
133 //
134 // All other registers are dead at this point and the locals will be
135 // copied into place by code emitted in the IR.
136
137 Register OSR_buf = osrBufferPointer()->as_register();
138 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
139 int monitor_offset = BytesPerWord * method()->max_locals() +
140 (2 * BytesPerWord) * (number_of_locks - 1);
141 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
142 // the OSR buffer using 2 word entries: first the lock and then
143 // the oop.
144 for (int i = 0; i < number_of_locks; i++) {
145 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
146 #ifdef ASSERT
147 // Verify the interpreter's monitor has a non-null object.
148 {
149 Label L;
150 __ ld(R0, slot_offset + 1*BytesPerWord, OSR_buf);
151 __ cmpdi(CCR0, R0, 0);
152 __ bne(CCR0, L);
153 __ stop("locked object is NULL");
154 __ bind(L);
155 }
156 #endif // ASSERT
157 // Copy the lock field into the compiled activation.
158 Address ml = frame_map()->address_for_monitor_lock(i),
159 mo = frame_map()->address_for_monitor_object(i);
160 assert(ml.index() == noreg && mo.index() == noreg, "sanity");
161 __ ld(R0, slot_offset + 0, OSR_buf);
162 __ std(R0, ml.disp(), ml.base());
163 __ ld(R0, slot_offset + 1*BytesPerWord, OSR_buf);
164 __ std(R0, mo.disp(), mo.base());
165 }
166 }
167 }
168
169
170 int LIR_Assembler::emit_exception_handler() {
171 // Generate code for the exception handler.
172 address handler_base = __ start_a_stub(exception_handler_size());
173
174 if (handler_base == NULL) {
175 // Not enough space left for the handler.
176 bailout("exception handler overflow");
177 return -1;
178 }
179
180 int offset = code_offset();
181 address entry_point = CAST_FROM_FN_PTR(address, Runtime1::entry_for(Runtime1::handle_exception_from_callee_id));
182 //__ load_const_optimized(R0, entry_point);
183 __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(entry_point));
184 __ mtctr(R0);
185 __ bctr();
186
187 guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
188 __ end_a_stub();
189
190 return offset;
191 }
192
193
194 // Emit the code to remove the frame from the stack in the exception
195 // unwind path.
196 int LIR_Assembler::emit_unwind_handler() {
197 _masm->block_comment("Unwind handler");
198
199 int offset = code_offset();
200 bool preserve_exception = method()->is_synchronized() || compilation()->env()->dtrace_method_probes();
201 const Register Rexception = R3 /*LIRGenerator::exceptionOopOpr()*/, Rexception_save = R31;
202
203 // Fetch the exception from TLS and clear out exception related thread state.
204 __ ld(Rexception, in_bytes(JavaThread::exception_oop_offset()), R16_thread);
205 __ li(R0, 0);
206 __ std(R0, in_bytes(JavaThread::exception_oop_offset()), R16_thread);
207 __ std(R0, in_bytes(JavaThread::exception_pc_offset()), R16_thread);
208
209 __ bind(_unwind_handler_entry);
210 __ verify_not_null_oop(Rexception);
211 if (preserve_exception) { __ mr(Rexception_save, Rexception); }
212
213 // Perform needed unlocking
214 MonitorExitStub* stub = NULL;
215 if (method()->is_synchronized()) {
216 monitor_address(0, FrameMap::R4_opr);
217 stub = new MonitorExitStub(FrameMap::R4_opr, true, 0);
218 __ unlock_object(R5, R6, R4, *stub->entry());
219 __ bind(*stub->continuation());
220 }
221
222 if (compilation()->env()->dtrace_method_probes()) {
223 Unimplemented();
224 }
225
226 // Dispatch to the unwind logic.
227 address unwind_stub = Runtime1::entry_for(Runtime1::unwind_exception_id);
228 //__ load_const_optimized(R0, unwind_stub);
229 __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(unwind_stub));
230 if (preserve_exception) { __ mr(Rexception, Rexception_save); }
231 __ mtctr(R0);
232 __ bctr();
233
234 // Emit the slow path assembly.
235 if (stub != NULL) {
236 stub->emit_code(this);
237 }
238
239 return offset;
240 }
241
242
243 int LIR_Assembler::emit_deopt_handler() {
244 // Generate code for deopt handler.
245 address handler_base = __ start_a_stub(deopt_handler_size());
246
247 if (handler_base == NULL) {
248 // Not enough space left for the handler.
249 bailout("deopt handler overflow");
250 return -1;
251 }
252
253 int offset = code_offset();
254 __ bl64_patchable(SharedRuntime::deopt_blob()->unpack(), relocInfo::runtime_call_type);
255
256 guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
257 __ end_a_stub();
258
259 return offset;
260 }
261
262
263 void LIR_Assembler::jobject2reg(jobject o, Register reg) {
264 if (o == NULL) {
265 __ li(reg, 0);
266 } else {
267 AddressLiteral addrlit = __ constant_oop_address(o);
268 __ load_const(reg, addrlit, (reg != R0) ? R0 : noreg);
269 }
270 }
271
272
273 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) {
274 // Allocate a new index in table to hold the object once it's been patched.
275 int oop_index = __ oop_recorder()->allocate_oop_index(NULL);
276 PatchingStub* patch = new PatchingStub(_masm, patching_id(info), oop_index);
277
278 AddressLiteral addrlit((address)NULL, oop_Relocation::spec(oop_index));
279 __ load_const(reg, addrlit, R0);
280
281 patching_epilog(patch, lir_patch_normal, reg, info);
282 }
283
284
285 void LIR_Assembler::metadata2reg(Metadata* o, Register reg) {
286 AddressLiteral md = __ constant_metadata_address(o); // Notify OOP recorder (don't need the relocation)
287 __ load_const_optimized(reg, md.value(), (reg != R0) ? R0 : noreg);
288 }
289
290
291 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo *info) {
292 // Allocate a new index in table to hold the klass once it's been patched.
293 int index = __ oop_recorder()->allocate_metadata_index(NULL);
294 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id, index);
295
296 AddressLiteral addrlit((address)NULL, metadata_Relocation::spec(index));
297 assert(addrlit.rspec().type() == relocInfo::metadata_type, "must be an metadata reloc");
298 __ load_const(reg, addrlit, R0);
299
300 patching_epilog(patch, lir_patch_normal, reg, info);
301 }
302
303
304 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) {
305 const bool is_int = result->is_single_cpu();
306 Register Rdividend = is_int ? left->as_register() : left->as_register_lo();
307 Register Rdivisor = noreg;
308 Register Rscratch = temp->as_register();
309 Register Rresult = is_int ? result->as_register() : result->as_register_lo();
310 long divisor = -1;
311
312 if (right->is_register()) {
313 Rdivisor = is_int ? right->as_register() : right->as_register_lo();
314 } else {
315 divisor = is_int ? right->as_constant_ptr()->as_jint()
316 : right->as_constant_ptr()->as_jlong();
317 }
318
319 assert(Rdividend != Rscratch, "");
320 assert(Rdivisor != Rscratch, "");
321 assert(code == lir_idiv || code == lir_irem, "Must be irem or idiv");
322
323 if (Rdivisor == noreg) {
324 if (divisor == 1) { // stupid, but can happen
325 if (code == lir_idiv) {
326 __ mr_if_needed(Rresult, Rdividend);
327 } else {
328 __ li(Rresult, 0);
329 }
330
331 } else if (is_power_of_2(divisor)) {
332 // Convert division by a power of two into some shifts and logical operations.
333 int log2 = log2i_exact(divisor);
334
335 // Round towards 0.
336 if (divisor == 2) {
337 if (is_int) {
338 __ srwi(Rscratch, Rdividend, 31);
339 } else {
340 __ srdi(Rscratch, Rdividend, 63);
341 }
342 } else {
343 if (is_int) {
344 __ srawi(Rscratch, Rdividend, 31);
345 } else {
346 __ sradi(Rscratch, Rdividend, 63);
347 }
348 __ clrldi(Rscratch, Rscratch, 64-log2);
349 }
350 __ add(Rscratch, Rdividend, Rscratch);
351
352 if (code == lir_idiv) {
353 if (is_int) {
354 __ srawi(Rresult, Rscratch, log2);
355 } else {
356 __ sradi(Rresult, Rscratch, log2);
357 }
358 } else { // lir_irem
359 __ clrrdi(Rscratch, Rscratch, log2);
360 __ sub(Rresult, Rdividend, Rscratch);
361 }
362
363 } else if (divisor == -1) {
364 if (code == lir_idiv) {
365 __ neg(Rresult, Rdividend);
366 } else {
367 __ li(Rresult, 0);
368 }
369
370 } else {
371 __ load_const_optimized(Rscratch, divisor);
372 if (code == lir_idiv) {
373 if (is_int) {
374 __ divw(Rresult, Rdividend, Rscratch); // Can't divide minint/-1.
375 } else {
376 __ divd(Rresult, Rdividend, Rscratch); // Can't divide minint/-1.
377 }
378 } else {
379 assert(Rscratch != R0, "need both");
380 if (is_int) {
381 __ divw(R0, Rdividend, Rscratch); // Can't divide minint/-1.
382 __ mullw(Rscratch, R0, Rscratch);
383 } else {
384 __ divd(R0, Rdividend, Rscratch); // Can't divide minint/-1.
385 __ mulld(Rscratch, R0, Rscratch);
386 }
387 __ sub(Rresult, Rdividend, Rscratch);
388 }
389
390 }
391 return;
392 }
393
394 Label regular, done;
395 if (is_int) {
396 __ cmpwi(CCR0, Rdivisor, -1);
397 } else {
398 __ cmpdi(CCR0, Rdivisor, -1);
399 }
400 __ bne(CCR0, regular);
401 if (code == lir_idiv) {
402 __ neg(Rresult, Rdividend);
403 __ b(done);
404 __ bind(regular);
405 if (is_int) {
406 __ divw(Rresult, Rdividend, Rdivisor); // Can't divide minint/-1.
407 } else {
408 __ divd(Rresult, Rdividend, Rdivisor); // Can't divide minint/-1.
409 }
410 } else { // lir_irem
411 __ li(Rresult, 0);
412 __ b(done);
413 __ bind(regular);
414 if (is_int) {
415 __ divw(Rscratch, Rdividend, Rdivisor); // Can't divide minint/-1.
416 __ mullw(Rscratch, Rscratch, Rdivisor);
417 } else {
418 __ divd(Rscratch, Rdividend, Rdivisor); // Can't divide minint/-1.
419 __ mulld(Rscratch, Rscratch, Rdivisor);
420 }
421 __ sub(Rresult, Rdividend, Rscratch);
422 }
423 __ bind(done);
424 }
425
426
427 void LIR_Assembler::emit_op3(LIR_Op3* op) {
428 switch (op->code()) {
429 case lir_idiv:
430 case lir_irem:
431 arithmetic_idiv(op->code(), op->in_opr1(), op->in_opr2(), op->in_opr3(),
432 op->result_opr(), op->info());
433 break;
434 case lir_fmad:
435 __ fmadd(op->result_opr()->as_double_reg(), op->in_opr1()->as_double_reg(),
436 op->in_opr2()->as_double_reg(), op->in_opr3()->as_double_reg());
437 break;
438 case lir_fmaf:
439 __ fmadds(op->result_opr()->as_float_reg(), op->in_opr1()->as_float_reg(),
440 op->in_opr2()->as_float_reg(), op->in_opr3()->as_float_reg());
441 break;
442 default: ShouldNotReachHere(); break;
443 }
444 }
445
446
447 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
448 #ifdef ASSERT
449 assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label");
450 if (op->block() != NULL) _branch_target_blocks.append(op->block());
451 if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock());
452 assert(op->info() == NULL, "shouldn't have CodeEmitInfo");
453 #endif
454
455 Label *L = op->label();
456 if (op->cond() == lir_cond_always) {
457 __ b(*L);
458 } else {
459 Label done;
460 bool is_unordered = false;
461 if (op->code() == lir_cond_float_branch) {
462 assert(op->ublock() != NULL, "must have unordered successor");
463 is_unordered = true;
464 } else {
465 assert(op->code() == lir_branch, "just checking");
466 }
467
468 bool positive = false;
469 Assembler::Condition cond = Assembler::equal;
470 switch (op->cond()) {
471 case lir_cond_equal: positive = true ; cond = Assembler::equal ; is_unordered = false; break;
472 case lir_cond_notEqual: positive = false; cond = Assembler::equal ; is_unordered = false; break;
473 case lir_cond_less: positive = true ; cond = Assembler::less ; break;
474 case lir_cond_belowEqual: assert(op->code() != lir_cond_float_branch, ""); // fallthru
475 case lir_cond_lessEqual: positive = false; cond = Assembler::greater; break;
476 case lir_cond_greater: positive = true ; cond = Assembler::greater; break;
477 case lir_cond_aboveEqual: assert(op->code() != lir_cond_float_branch, ""); // fallthru
478 case lir_cond_greaterEqual: positive = false; cond = Assembler::less ; break;
479 default: ShouldNotReachHere();
480 }
481 int bo = positive ? Assembler::bcondCRbiIs1 : Assembler::bcondCRbiIs0;
482 int bi = Assembler::bi0(BOOL_RESULT, cond);
483 if (is_unordered) {
484 if (positive) {
485 if (op->ublock() == op->block()) {
486 __ bc_far_optimized(Assembler::bcondCRbiIs1, __ bi0(BOOL_RESULT, Assembler::summary_overflow), *L);
487 }
488 } else {
489 if (op->ublock() != op->block()) { __ bso(BOOL_RESULT, done); }
490 }
491 }
492 __ bc_far_optimized(bo, bi, *L);
493 __ bind(done);
494 }
495 }
496
497
498 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
499 Bytecodes::Code code = op->bytecode();
500 LIR_Opr src = op->in_opr(),
501 dst = op->result_opr();
502
503 switch(code) {
504 case Bytecodes::_i2l: {
505 __ extsw(dst->as_register_lo(), src->as_register());
506 break;
507 }
508 case Bytecodes::_l2i: {
509 __ mr_if_needed(dst->as_register(), src->as_register_lo()); // high bits are garbage
510 break;
511 }
512 case Bytecodes::_i2b: {
513 __ extsb(dst->as_register(), src->as_register());
514 break;
515 }
516 case Bytecodes::_i2c: {
517 __ clrldi(dst->as_register(), src->as_register(), 64-16);
518 break;
519 }
520 case Bytecodes::_i2s: {
521 __ extsh(dst->as_register(), src->as_register());
522 break;
523 }
524 case Bytecodes::_i2d:
525 case Bytecodes::_l2d: {
526 bool src_in_memory = !VM_Version::has_mtfprd();
527 FloatRegister rdst = dst->as_double_reg();
528 FloatRegister rsrc;
529 if (src_in_memory) {
530 rsrc = src->as_double_reg(); // via mem
531 } else {
532 // move src to dst register
533 if (code == Bytecodes::_i2d) {
534 __ mtfprwa(rdst, src->as_register());
535 } else {
536 __ mtfprd(rdst, src->as_register_lo());
537 }
538 rsrc = rdst;
539 }
540 __ fcfid(rdst, rsrc);
541 break;
542 }
543 case Bytecodes::_i2f:
544 case Bytecodes::_l2f: {
545 bool src_in_memory = !VM_Version::has_mtfprd();
546 FloatRegister rdst = dst->as_float_reg();
547 FloatRegister rsrc;
548 if (src_in_memory) {
549 rsrc = src->as_double_reg(); // via mem
550 } else {
551 // move src to dst register
552 if (code == Bytecodes::_i2f) {
553 __ mtfprwa(rdst, src->as_register());
554 } else {
555 __ mtfprd(rdst, src->as_register_lo());
556 }
557 rsrc = rdst;
558 }
559 if (VM_Version::has_fcfids()) {
560 __ fcfids(rdst, rsrc);
561 } else {
562 assert(code == Bytecodes::_i2f, "fcfid+frsp needs fixup code to avoid rounding incompatibility");
563 __ fcfid(rdst, rsrc);
564 __ frsp(rdst, rdst);
565 }
566 break;
567 }
568 case Bytecodes::_f2d: {
569 __ fmr_if_needed(dst->as_double_reg(), src->as_float_reg());
570 break;
571 }
572 case Bytecodes::_d2f: {
573 __ frsp(dst->as_float_reg(), src->as_double_reg());
574 break;
575 }
576 case Bytecodes::_d2i:
577 case Bytecodes::_f2i: {
578 bool dst_in_memory = !VM_Version::has_mtfprd();
579 FloatRegister rsrc = (code == Bytecodes::_d2i) ? src->as_double_reg() : src->as_float_reg();
580 Address addr = dst_in_memory ? frame_map()->address_for_slot(dst->double_stack_ix()) : Address();
581 Label L;
582 // Result must be 0 if value is NaN; test by comparing value to itself.
583 __ fcmpu(CCR0, rsrc, rsrc);
584 if (dst_in_memory) {
585 __ li(R0, 0); // 0 in case of NAN
586 __ std(R0, addr.disp(), addr.base());
587 } else {
588 __ li(dst->as_register(), 0);
589 }
590 __ bso(CCR0, L);
591 __ fctiwz(rsrc, rsrc); // USE_KILL
592 if (dst_in_memory) {
593 __ stfd(rsrc, addr.disp(), addr.base());
594 } else {
595 __ mffprd(dst->as_register(), rsrc);
596 }
597 __ bind(L);
598 break;
599 }
600 case Bytecodes::_d2l:
601 case Bytecodes::_f2l: {
602 bool dst_in_memory = !VM_Version::has_mtfprd();
603 FloatRegister rsrc = (code == Bytecodes::_d2l) ? src->as_double_reg() : src->as_float_reg();
604 Address addr = dst_in_memory ? frame_map()->address_for_slot(dst->double_stack_ix()) : Address();
605 Label L;
606 // Result must be 0 if value is NaN; test by comparing value to itself.
607 __ fcmpu(CCR0, rsrc, rsrc);
608 if (dst_in_memory) {
609 __ li(R0, 0); // 0 in case of NAN
610 __ std(R0, addr.disp(), addr.base());
611 } else {
612 __ li(dst->as_register_lo(), 0);
613 }
614 __ bso(CCR0, L);
615 __ fctidz(rsrc, rsrc); // USE_KILL
616 if (dst_in_memory) {
617 __ stfd(rsrc, addr.disp(), addr.base());
618 } else {
619 __ mffprd(dst->as_register_lo(), rsrc);
620 }
621 __ bind(L);
622 break;
623 }
624
625 default: ShouldNotReachHere();
626 }
627 }
628
629
630 void LIR_Assembler::align_call(LIR_Code) {
631 // do nothing since all instructions are word aligned on ppc
632 }
633
634
635 bool LIR_Assembler::emit_trampoline_stub_for_call(address target, Register Rtoc) {
636 int start_offset = __ offset();
637 // Put the entry point as a constant into the constant pool.
638 const address entry_point_toc_addr = __ address_constant(target, RelocationHolder::none);
639 if (entry_point_toc_addr == NULL) {
640 bailout("const section overflow");
641 return false;
642 }
643 const int entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr);
644
645 // Emit the trampoline stub which will be related to the branch-and-link below.
646 address stub = __ emit_trampoline_stub(entry_point_toc_offset, start_offset, Rtoc);
647 if (!stub) {
648 bailout("no space for trampoline stub");
649 return false;
650 }
651 return true;
652 }
653
654
655 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
656 assert(rtype==relocInfo::opt_virtual_call_type || rtype==relocInfo::static_call_type, "unexpected rtype");
657
658 bool success = emit_trampoline_stub_for_call(op->addr());
659 if (!success) { return; }
660
661 __ relocate(rtype);
662 // Note: At this point we do not have the address of the trampoline
663 // stub, and the entry point might be too far away for bl, so __ pc()
664 // serves as dummy and the bl will be patched later.
665 __ code()->set_insts_mark();
666 __ bl(__ pc());
667 add_call_info(code_offset(), op->info());
668 __ post_call_nop();
669 }
670
671
672 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
673 __ calculate_address_from_global_toc(R2_TOC, __ method_toc());
674
675 // Virtual call relocation will point to ic load.
676 address virtual_call_meta_addr = __ pc();
677 // Load a clear inline cache.
678 AddressLiteral empty_ic((address) Universe::non_oop_word());
679 bool success = __ load_const_from_method_toc(R19_inline_cache_reg, empty_ic, R2_TOC);
680 if (!success) {
681 bailout("const section overflow");
682 return;
683 }
684 // Call to fixup routine. Fixup routine uses ScopeDesc info
685 // to determine who we intended to call.
686 __ relocate(virtual_call_Relocation::spec(virtual_call_meta_addr));
687
688 success = emit_trampoline_stub_for_call(op->addr(), R2_TOC);
689 if (!success) { return; }
690
691 // Note: At this point we do not have the address of the trampoline
692 // stub, and the entry point might be too far away for bl, so __ pc()
693 // serves as dummy and the bl will be patched later.
694 __ bl(__ pc());
695 add_call_info(code_offset(), op->info());
696 __ post_call_nop();
697 }
698
699 void LIR_Assembler::explicit_null_check(Register addr, CodeEmitInfo* info) {
700 ImplicitNullCheckStub* stub = new ImplicitNullCheckStub(code_offset(), info);
701 __ null_check(addr, stub->entry());
702 append_code_stub(stub);
703 }
704
705
706 // Attention: caller must encode oop if needed
707 int LIR_Assembler::store(LIR_Opr from_reg, Register base, int offset, BasicType type, bool wide) {
708 int store_offset;
709 if (!Assembler::is_simm16(offset)) {
710 // For offsets larger than a simm16 we setup the offset.
711 assert(wide && !from_reg->is_same_register(FrameMap::R0_opr), "large offset only supported in special case");
712 __ load_const_optimized(R0, offset);
713 store_offset = store(from_reg, base, R0, type, wide);
714 } else {
715 store_offset = code_offset();
716 switch (type) {
717 case T_BOOLEAN: // fall through
718 case T_BYTE : __ stb(from_reg->as_register(), offset, base); break;
719 case T_CHAR :
720 case T_SHORT : __ sth(from_reg->as_register(), offset, base); break;
721 case T_INT : __ stw(from_reg->as_register(), offset, base); break;
722 case T_LONG : __ std(from_reg->as_register_lo(), offset, base); break;
723 case T_ADDRESS:
724 case T_METADATA: __ std(from_reg->as_register(), offset, base); break;
725 case T_ARRAY : // fall through
726 case T_OBJECT:
727 {
728 if (UseCompressedOops && !wide) {
729 // Encoding done in caller
730 __ stw(from_reg->as_register(), offset, base);
731 __ verify_coop(from_reg->as_register(), FILE_AND_LINE);
732 } else {
733 __ std(from_reg->as_register(), offset, base);
734 if (VerifyOops) {
735 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
736 bs->check_oop(_masm, from_reg->as_register(), FILE_AND_LINE); // kills R0
737 }
738 }
739 break;
740 }
741 case T_FLOAT : __ stfs(from_reg->as_float_reg(), offset, base); break;
742 case T_DOUBLE: __ stfd(from_reg->as_double_reg(), offset, base); break;
743 default : ShouldNotReachHere();
744 }
745 }
746 return store_offset;
747 }
748
749
750 // Attention: caller must encode oop if needed
751 int LIR_Assembler::store(LIR_Opr from_reg, Register base, Register disp, BasicType type, bool wide) {
752 int store_offset = code_offset();
753 switch (type) {
754 case T_BOOLEAN: // fall through
755 case T_BYTE : __ stbx(from_reg->as_register(), base, disp); break;
756 case T_CHAR :
757 case T_SHORT : __ sthx(from_reg->as_register(), base, disp); break;
758 case T_INT : __ stwx(from_reg->as_register(), base, disp); break;
759 case T_LONG :
760 #ifdef _LP64
761 __ stdx(from_reg->as_register_lo(), base, disp);
762 #else
763 Unimplemented();
764 #endif
765 break;
766 case T_ADDRESS:
767 __ stdx(from_reg->as_register(), base, disp);
768 break;
769 case T_ARRAY : // fall through
770 case T_OBJECT:
771 {
772 if (UseCompressedOops && !wide) {
773 // Encoding done in caller.
774 __ stwx(from_reg->as_register(), base, disp);
775 __ verify_coop(from_reg->as_register(), FILE_AND_LINE); // kills R0
776 } else {
777 __ stdx(from_reg->as_register(), base, disp);
778 if (VerifyOops) {
779 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
780 bs->check_oop(_masm, from_reg->as_register(), FILE_AND_LINE); // kills R0
781 }
782 }
783 break;
784 }
785 case T_FLOAT : __ stfsx(from_reg->as_float_reg(), base, disp); break;
786 case T_DOUBLE: __ stfdx(from_reg->as_double_reg(), base, disp); break;
787 default : ShouldNotReachHere();
788 }
789 return store_offset;
790 }
791
792
793 int LIR_Assembler::load(Register base, int offset, LIR_Opr to_reg, BasicType type, bool wide) {
794 int load_offset;
795 if (!Assembler::is_simm16(offset)) {
796 // For offsets larger than a simm16 we setup the offset.
797 __ load_const_optimized(R0, offset);
798 load_offset = load(base, R0, to_reg, type, wide);
799 } else {
800 load_offset = code_offset();
801 switch(type) {
802 case T_BOOLEAN: // fall through
803 case T_BYTE : __ lbz(to_reg->as_register(), offset, base);
804 __ extsb(to_reg->as_register(), to_reg->as_register()); break;
805 case T_CHAR : __ lhz(to_reg->as_register(), offset, base); break;
806 case T_SHORT : __ lha(to_reg->as_register(), offset, base); break;
807 case T_INT : __ lwa(to_reg->as_register(), offset, base); break;
808 case T_LONG : __ ld(to_reg->as_register_lo(), offset, base); break;
809 case T_METADATA: __ ld(to_reg->as_register(), offset, base); break;
810 case T_ADDRESS:
811 __ ld(to_reg->as_register(), offset, base);
812 break;
813 case T_ARRAY : // fall through
814 case T_OBJECT:
815 {
816 if (UseCompressedOops && !wide) {
817 __ lwz(to_reg->as_register(), offset, base);
818 __ decode_heap_oop(to_reg->as_register());
819 } else {
820 __ ld(to_reg->as_register(), offset, base);
821 }
822 if (VerifyOops) {
823 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
824 bs->check_oop(_masm, to_reg->as_register(), FILE_AND_LINE); // kills R0
825 }
826 break;
827 }
828 case T_FLOAT: __ lfs(to_reg->as_float_reg(), offset, base); break;
829 case T_DOUBLE: __ lfd(to_reg->as_double_reg(), offset, base); break;
830 default : ShouldNotReachHere();
831 }
832 }
833 return load_offset;
834 }
835
836
837 int LIR_Assembler::load(Register base, Register disp, LIR_Opr to_reg, BasicType type, bool wide) {
838 int load_offset = code_offset();
839 switch(type) {
840 case T_BOOLEAN: // fall through
841 case T_BYTE : __ lbzx(to_reg->as_register(), base, disp);
842 __ extsb(to_reg->as_register(), to_reg->as_register()); break;
843 case T_CHAR : __ lhzx(to_reg->as_register(), base, disp); break;
844 case T_SHORT : __ lhax(to_reg->as_register(), base, disp); break;
845 case T_INT : __ lwax(to_reg->as_register(), base, disp); break;
846 case T_ADDRESS: __ ldx(to_reg->as_register(), base, disp); break;
847 case T_ARRAY : // fall through
848 case T_OBJECT:
849 {
850 if (UseCompressedOops && !wide) {
851 __ lwzx(to_reg->as_register(), base, disp);
852 __ decode_heap_oop(to_reg->as_register());
853 } else {
854 __ ldx(to_reg->as_register(), base, disp);
855 }
856 if (VerifyOops) {
857 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
858 bs->check_oop(_masm, to_reg->as_register(), FILE_AND_LINE); // kills R0
859 }
860 break;
861 }
862 case T_FLOAT: __ lfsx(to_reg->as_float_reg() , base, disp); break;
863 case T_DOUBLE: __ lfdx(to_reg->as_double_reg(), base, disp); break;
864 case T_LONG :
865 #ifdef _LP64
866 __ ldx(to_reg->as_register_lo(), base, disp);
867 #else
868 Unimplemented();
869 #endif
870 break;
871 default : ShouldNotReachHere();
872 }
873 return load_offset;
874 }
875
876
877 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
878 LIR_Const* c = src->as_constant_ptr();
879 Register src_reg = R0;
880 switch (c->type()) {
881 case T_INT:
882 case T_FLOAT: {
883 int value = c->as_jint_bits();
884 __ load_const_optimized(src_reg, value);
885 Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
886 __ stw(src_reg, addr.disp(), addr.base());
887 break;
888 }
889 case T_ADDRESS: {
890 int value = c->as_jint_bits();
891 __ load_const_optimized(src_reg, value);
892 Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
893 __ std(src_reg, addr.disp(), addr.base());
894 break;
895 }
896 case T_OBJECT: {
897 jobject2reg(c->as_jobject(), src_reg);
898 Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
899 __ std(src_reg, addr.disp(), addr.base());
900 break;
901 }
902 case T_LONG:
903 case T_DOUBLE: {
904 int value = c->as_jlong_bits();
905 __ load_const_optimized(src_reg, value);
906 Address addr = frame_map()->address_for_double_slot(dest->double_stack_ix());
907 __ std(src_reg, addr.disp(), addr.base());
908 break;
909 }
910 default:
911 Unimplemented();
912 }
913 }
914
915
916 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
917 LIR_Const* c = src->as_constant_ptr();
918 LIR_Address* addr = dest->as_address_ptr();
919 Register base = addr->base()->as_pointer_register();
920 LIR_Opr tmp = LIR_OprFact::illegalOpr;
921 int offset = -1;
922 // Null check for large offsets in LIRGenerator::do_StoreField.
923 bool needs_explicit_null_check = !ImplicitNullChecks;
924
925 if (info != NULL && needs_explicit_null_check) {
926 explicit_null_check(base, info);
927 }
928
929 switch (c->type()) {
930 case T_FLOAT: type = T_INT;
931 case T_INT:
932 case T_ADDRESS: {
933 tmp = FrameMap::R0_opr;
934 __ load_const_optimized(tmp->as_register(), c->as_jint_bits());
935 break;
936 }
937 case T_DOUBLE: type = T_LONG;
938 case T_LONG: {
939 tmp = FrameMap::R0_long_opr;
940 __ load_const_optimized(tmp->as_register_lo(), c->as_jlong_bits());
941 break;
942 }
943 case T_OBJECT: {
944 tmp = FrameMap::R0_opr;
945 if (UseCompressedOops && !wide && c->as_jobject() != NULL) {
946 AddressLiteral oop_addr = __ constant_oop_address(c->as_jobject());
947 // Don't care about sign extend (will use stw).
948 __ lis(R0, 0); // Will get patched.
949 __ relocate(oop_addr.rspec(), /*compressed format*/ 1);
950 __ ori(R0, R0, 0); // Will get patched.
951 } else {
952 jobject2reg(c->as_jobject(), R0);
953 }
954 break;
955 }
956 default:
957 Unimplemented();
958 }
959
960 // Handle either reg+reg or reg+disp address.
961 if (addr->index()->is_valid()) {
962 assert(addr->disp() == 0, "must be zero");
963 offset = store(tmp, base, addr->index()->as_pointer_register(), type, wide);
964 } else {
965 assert(Assembler::is_simm16(addr->disp()), "can't handle larger addresses");
966 offset = store(tmp, base, addr->disp(), type, wide);
967 }
968
969 if (info != NULL) {
970 assert(offset != -1, "offset should've been set");
971 if (!needs_explicit_null_check) {
972 add_debug_info_for_null_check(offset, info);
973 }
974 }
975 }
976
977
978 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
979 LIR_Const* c = src->as_constant_ptr();
980 LIR_Opr to_reg = dest;
981
982 switch (c->type()) {
983 case T_INT: {
984 assert(patch_code == lir_patch_none, "no patching handled here");
985 __ load_const_optimized(dest->as_register(), c->as_jint(), R0);
986 break;
987 }
988 case T_ADDRESS: {
989 assert(patch_code == lir_patch_none, "no patching handled here");
990 __ load_const_optimized(dest->as_register(), c->as_jint(), R0); // Yes, as_jint ...
991 break;
992 }
993 case T_LONG: {
994 assert(patch_code == lir_patch_none, "no patching handled here");
995 __ load_const_optimized(dest->as_register_lo(), c->as_jlong(), R0);
996 break;
997 }
998
999 case T_OBJECT: {
1000 if (patch_code == lir_patch_none) {
1001 jobject2reg(c->as_jobject(), to_reg->as_register());
1002 } else {
1003 jobject2reg_with_patching(to_reg->as_register(), info);
1004 }
1005 break;
1006 }
1007
1008 case T_METADATA:
1009 {
1010 if (patch_code == lir_patch_none) {
1011 metadata2reg(c->as_metadata(), to_reg->as_register());
1012 } else {
1013 klass2reg_with_patching(to_reg->as_register(), info);
1014 }
1015 }
1016 break;
1017
1018 case T_FLOAT:
1019 {
1020 if (to_reg->is_single_fpu()) {
1021 address const_addr = __ float_constant(c->as_jfloat());
1022 if (const_addr == NULL) {
1023 bailout("const section overflow");
1024 break;
1025 }
1026 RelocationHolder rspec = internal_word_Relocation::spec(const_addr);
1027 __ relocate(rspec);
1028 __ load_const(R0, const_addr);
1029 __ lfsx(to_reg->as_float_reg(), R0);
1030 } else {
1031 assert(to_reg->is_single_cpu(), "Must be a cpu register.");
1032 __ load_const_optimized(to_reg->as_register(), jint_cast(c->as_jfloat()), R0);
1033 }
1034 }
1035 break;
1036
1037 case T_DOUBLE:
1038 {
1039 if (to_reg->is_double_fpu()) {
1040 address const_addr = __ double_constant(c->as_jdouble());
1041 if (const_addr == NULL) {
1042 bailout("const section overflow");
1043 break;
1044 }
1045 RelocationHolder rspec = internal_word_Relocation::spec(const_addr);
1046 __ relocate(rspec);
1047 __ load_const(R0, const_addr);
1048 __ lfdx(to_reg->as_double_reg(), R0);
1049 } else {
1050 assert(to_reg->is_double_cpu(), "Must be a long register.");
1051 __ load_const_optimized(to_reg->as_register_lo(), jlong_cast(c->as_jdouble()), R0);
1052 }
1053 }
1054 break;
1055
1056 default:
1057 ShouldNotReachHere();
1058 }
1059 }
1060
1061
1062 Address LIR_Assembler::as_Address(LIR_Address* addr) {
1063 Unimplemented(); return Address();
1064 }
1065
1066
1067 inline RegisterOrConstant index_or_disp(LIR_Address* addr) {
1068 if (addr->index()->is_illegal()) {
1069 return (RegisterOrConstant)(addr->disp());
1070 } else {
1071 return (RegisterOrConstant)(addr->index()->as_pointer_register());
1072 }
1073 }
1074
1075
1076 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
1077 const Register tmp = R0;
1078 switch (type) {
1079 case T_INT:
1080 case T_FLOAT: {
1081 Address from = frame_map()->address_for_slot(src->single_stack_ix());
1082 Address to = frame_map()->address_for_slot(dest->single_stack_ix());
1083 __ lwz(tmp, from.disp(), from.base());
1084 __ stw(tmp, to.disp(), to.base());
1085 break;
1086 }
1087 case T_ADDRESS:
1088 case T_OBJECT: {
1089 Address from = frame_map()->address_for_slot(src->single_stack_ix());
1090 Address to = frame_map()->address_for_slot(dest->single_stack_ix());
1091 __ ld(tmp, from.disp(), from.base());
1092 __ std(tmp, to.disp(), to.base());
1093 break;
1094 }
1095 case T_LONG:
1096 case T_DOUBLE: {
1097 Address from = frame_map()->address_for_double_slot(src->double_stack_ix());
1098 Address to = frame_map()->address_for_double_slot(dest->double_stack_ix());
1099 __ ld(tmp, from.disp(), from.base());
1100 __ std(tmp, to.disp(), to.base());
1101 break;
1102 }
1103
1104 default:
1105 ShouldNotReachHere();
1106 }
1107 }
1108
1109
1110 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
1111 Unimplemented(); return Address();
1112 }
1113
1114
1115 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
1116 Unimplemented(); return Address();
1117 }
1118
1119
1120 void LIR_Assembler::mem2reg(LIR_Opr src_opr, LIR_Opr dest, BasicType type,
1121 LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide) {
1122
1123 assert(type != T_METADATA, "load of metadata ptr not supported");
1124 LIR_Address* addr = src_opr->as_address_ptr();
1125 LIR_Opr to_reg = dest;
1126
1127 Register src = addr->base()->as_pointer_register();
1128 Register disp_reg = noreg;
1129 int disp_value = addr->disp();
1130 bool needs_patching = (patch_code != lir_patch_none);
1131 // null check for large offsets in LIRGenerator::do_LoadField
1132 bool needs_explicit_null_check = !os::zero_page_read_protected() || !ImplicitNullChecks;
1133
1134 if (info != NULL && needs_explicit_null_check) {
1135 explicit_null_check(src, info);
1136 }
1137
1138 if (addr->base()->type() == T_OBJECT) {
1139 __ verify_oop(src, FILE_AND_LINE);
1140 }
1141
1142 PatchingStub* patch = NULL;
1143 if (needs_patching) {
1144 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1145 assert(!to_reg->is_double_cpu() ||
1146 patch_code == lir_patch_none ||
1147 patch_code == lir_patch_normal, "patching doesn't match register");
1148 }
1149
1150 if (addr->index()->is_illegal()) {
1151 if (!Assembler::is_simm16(disp_value)) {
1152 if (needs_patching) {
1153 __ load_const32(R0, 0); // patchable int
1154 } else {
1155 __ load_const_optimized(R0, disp_value);
1156 }
1157 disp_reg = R0;
1158 }
1159 } else {
1160 disp_reg = addr->index()->as_pointer_register();
1161 assert(disp_value == 0, "can't handle 3 operand addresses");
1162 }
1163
1164 // Remember the offset of the load. The patching_epilog must be done
1165 // before the call to add_debug_info, otherwise the PcDescs don't get
1166 // entered in increasing order.
1167 int offset;
1168
1169 if (disp_reg == noreg) {
1170 assert(Assembler::is_simm16(disp_value), "should have set this up");
1171 offset = load(src, disp_value, to_reg, type, wide);
1172 } else {
1173 offset = load(src, disp_reg, to_reg, type, wide);
1174 }
1175
1176 if (patch != NULL) {
1177 patching_epilog(patch, patch_code, src, info);
1178 }
1179 if (info != NULL && !needs_explicit_null_check) {
1180 add_debug_info_for_null_check(offset, info);
1181 }
1182 }
1183
1184
1185 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
1186 Address addr;
1187 if (src->is_single_word()) {
1188 addr = frame_map()->address_for_slot(src->single_stack_ix());
1189 } else if (src->is_double_word()) {
1190 addr = frame_map()->address_for_double_slot(src->double_stack_ix());
1191 }
1192
1193 load(addr.base(), addr.disp(), dest, dest->type(), true /*wide*/);
1194 }
1195
1196
1197 void LIR_Assembler::reg2stack(LIR_Opr from_reg, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
1198 Address addr;
1199 if (dest->is_single_word()) {
1200 addr = frame_map()->address_for_slot(dest->single_stack_ix());
1201 } else if (dest->is_double_word()) {
1202 addr = frame_map()->address_for_slot(dest->double_stack_ix());
1203 }
1204
1205 store(from_reg, addr.base(), addr.disp(), from_reg->type(), true /*wide*/);
1206 }
1207
1208
1209 void LIR_Assembler::reg2reg(LIR_Opr from_reg, LIR_Opr to_reg) {
1210 if (from_reg->is_float_kind() && to_reg->is_float_kind()) {
1211 if (from_reg->is_double_fpu()) {
1212 // double to double moves
1213 assert(to_reg->is_double_fpu(), "should match");
1214 __ fmr_if_needed(to_reg->as_double_reg(), from_reg->as_double_reg());
1215 } else {
1216 // float to float moves
1217 assert(to_reg->is_single_fpu(), "should match");
1218 __ fmr_if_needed(to_reg->as_float_reg(), from_reg->as_float_reg());
1219 }
1220 } else if (!from_reg->is_float_kind() && !to_reg->is_float_kind()) {
1221 if (from_reg->is_double_cpu()) {
1222 __ mr_if_needed(to_reg->as_pointer_register(), from_reg->as_pointer_register());
1223 } else if (to_reg->is_double_cpu()) {
1224 // int to int moves
1225 __ mr_if_needed(to_reg->as_register_lo(), from_reg->as_register());
1226 } else {
1227 // int to int moves
1228 __ mr_if_needed(to_reg->as_register(), from_reg->as_register());
1229 }
1230 } else {
1231 ShouldNotReachHere();
1232 }
1233 if (is_reference_type(to_reg->type())) {
1234 __ verify_oop(to_reg->as_register(), FILE_AND_LINE);
1235 }
1236 }
1237
1238
1239 void LIR_Assembler::reg2mem(LIR_Opr from_reg, LIR_Opr dest, BasicType type,
1240 LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack,
1241 bool wide) {
1242 assert(type != T_METADATA, "store of metadata ptr not supported");
1243 LIR_Address* addr = dest->as_address_ptr();
1244
1245 Register src = addr->base()->as_pointer_register();
1246 Register disp_reg = noreg;
1247 int disp_value = addr->disp();
1248 bool needs_patching = (patch_code != lir_patch_none);
1249 bool compress_oop = (is_reference_type(type)) && UseCompressedOops && !wide &&
1250 CompressedOops::mode() != CompressedOops::UnscaledNarrowOop;
1251 bool load_disp = addr->index()->is_illegal() && !Assembler::is_simm16(disp_value);
1252 bool use_R29 = compress_oop && load_disp; // Avoid register conflict, also do null check before killing R29.
1253 // Null check for large offsets in LIRGenerator::do_StoreField.
1254 bool needs_explicit_null_check = !ImplicitNullChecks || use_R29;
1255
1256 if (info != NULL && needs_explicit_null_check) {
1257 explicit_null_check(src, info);
1258 }
1259
1260 if (addr->base()->is_oop_register()) {
1261 __ verify_oop(src, FILE_AND_LINE);
1262 }
1263
1264 PatchingStub* patch = NULL;
1265 if (needs_patching) {
1266 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1267 assert(!from_reg->is_double_cpu() ||
1268 patch_code == lir_patch_none ||
1269 patch_code == lir_patch_normal, "patching doesn't match register");
1270 }
1271
1272 if (addr->index()->is_illegal()) {
1273 if (load_disp) {
1274 disp_reg = use_R29 ? R29_TOC : R0;
1275 if (needs_patching) {
1276 __ load_const32(disp_reg, 0); // patchable int
1277 } else {
1278 __ load_const_optimized(disp_reg, disp_value);
1279 }
1280 }
1281 } else {
1282 disp_reg = addr->index()->as_pointer_register();
1283 assert(disp_value == 0, "can't handle 3 operand addresses");
1284 }
1285
1286 // remember the offset of the store. The patching_epilog must be done
1287 // before the call to add_debug_info_for_null_check, otherwise the PcDescs don't get
1288 // entered in increasing order.
1289 int offset;
1290
1291 if (compress_oop) {
1292 Register co = __ encode_heap_oop(R0, from_reg->as_register());
1293 from_reg = FrameMap::as_opr(co);
1294 }
1295
1296 if (disp_reg == noreg) {
1297 assert(Assembler::is_simm16(disp_value), "should have set this up");
1298 offset = store(from_reg, src, disp_value, type, wide);
1299 } else {
1300 offset = store(from_reg, src, disp_reg, type, wide);
1301 }
1302
1303 if (use_R29) {
1304 __ load_const_optimized(R29_TOC, MacroAssembler::global_toc(), R0); // reinit
1305 }
1306
1307 if (patch != NULL) {
1308 patching_epilog(patch, patch_code, src, info);
1309 }
1310
1311 if (info != NULL && !needs_explicit_null_check) {
1312 add_debug_info_for_null_check(offset, info);
1313 }
1314 }
1315
1316
1317 void LIR_Assembler::return_op(LIR_Opr result, C1SafepointPollStub* code_stub) {
1318 const Register return_pc = R31; // Must survive C-call to enable_stack_reserved_zone().
1319 const Register temp = R12;
1320
1321 // Pop the stack before the safepoint code.
1322 int frame_size = initial_frame_size_in_bytes();
1323 if (Assembler::is_simm(frame_size, 16)) {
1324 __ addi(R1_SP, R1_SP, frame_size);
1325 } else {
1326 __ pop_frame();
1327 }
1328
1329 // Restore return pc relative to callers' sp.
1330 __ ld(return_pc, _abi0(lr), R1_SP);
1331 // Move return pc to LR.
1332 __ mtlr(return_pc);
1333
1334 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
1335 __ reserved_stack_check(return_pc);
1336 }
1337
1338 // We need to mark the code position where the load from the safepoint
1339 // polling page was emitted as relocInfo::poll_return_type here.
1340 if (!UseSIGTRAP) {
1341 code_stub->set_safepoint_offset(__ offset());
1342 __ relocate(relocInfo::poll_return_type);
1343 }
1344 __ safepoint_poll(*code_stub->entry(), temp, true /* at_return */, true /* in_nmethod */);
1345
1346 // Return.
1347 __ blr();
1348 }
1349
1350
1351 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
1352 const Register poll_addr = tmp->as_register();
1353 __ ld(poll_addr, in_bytes(JavaThread::polling_page_offset()), R16_thread);
1354 if (info != NULL) {
1355 add_debug_info_for_branch(info);
1356 }
1357 int offset = __ offset();
1358 __ relocate(relocInfo::poll_type);
1359 __ load_from_polling_page(poll_addr);
1360
1361 return offset;
1362 }
1363
1364
1365 void LIR_Assembler::emit_static_call_stub() {
1366 address call_pc = __ pc();
1367 address stub = __ start_a_stub(static_call_stub_size());
1368 if (stub == NULL) {
1369 bailout("static call stub overflow");
1370 return;
1371 }
1372
1373 // For java_to_interp stubs we use R11_scratch1 as scratch register
1374 // and in call trampoline stubs we use R12_scratch2. This way we
1375 // can distinguish them (see is_NativeCallTrampolineStub_at()).
1376 const Register reg_scratch = R11_scratch1;
1377
1378 // Create a static stub relocation which relates this stub
1379 // with the call instruction at insts_call_instruction_offset in the
1380 // instructions code-section.
1381 int start = __ offset();
1382 __ relocate(static_stub_Relocation::spec(call_pc));
1383
1384 // Now, create the stub's code:
1385 // - load the TOC
1386 // - load the inline cache oop from the constant pool
1387 // - load the call target from the constant pool
1388 // - call
1389 __ calculate_address_from_global_toc(reg_scratch, __ method_toc());
1390 AddressLiteral ic = __ allocate_metadata_address((Metadata *)NULL);
1391 bool success = __ load_const_from_method_toc(R19_inline_cache_reg, ic, reg_scratch, /*fixed_size*/ true);
1392
1393 if (ReoptimizeCallSequences) {
1394 __ b64_patchable((address)-1, relocInfo::none);
1395 } else {
1396 AddressLiteral a((address)-1);
1397 success = success && __ load_const_from_method_toc(reg_scratch, a, reg_scratch, /*fixed_size*/ true);
1398 __ mtctr(reg_scratch);
1399 __ bctr();
1400 }
1401 if (!success) {
1402 bailout("const section overflow");
1403 return;
1404 }
1405
1406 assert(__ offset() - start <= static_call_stub_size(), "stub too big");
1407 __ end_a_stub();
1408 }
1409
1410
1411 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
1412 bool unsigned_comp = (condition == lir_cond_belowEqual || condition == lir_cond_aboveEqual);
1413 if (opr1->is_single_fpu()) {
1414 __ fcmpu(BOOL_RESULT, opr1->as_float_reg(), opr2->as_float_reg());
1415 } else if (opr1->is_double_fpu()) {
1416 __ fcmpu(BOOL_RESULT, opr1->as_double_reg(), opr2->as_double_reg());
1417 } else if (opr1->is_single_cpu()) {
1418 if (opr2->is_constant()) {
1419 switch (opr2->as_constant_ptr()->type()) {
1420 case T_INT:
1421 {
1422 jint con = opr2->as_constant_ptr()->as_jint();
1423 if (unsigned_comp) {
1424 if (Assembler::is_uimm(con, 16)) {
1425 __ cmplwi(BOOL_RESULT, opr1->as_register(), con);
1426 } else {
1427 __ load_const_optimized(R0, con);
1428 __ cmplw(BOOL_RESULT, opr1->as_register(), R0);
1429 }
1430 } else {
1431 if (Assembler::is_simm(con, 16)) {
1432 __ cmpwi(BOOL_RESULT, opr1->as_register(), con);
1433 } else {
1434 __ load_const_optimized(R0, con);
1435 __ cmpw(BOOL_RESULT, opr1->as_register(), R0);
1436 }
1437 }
1438 }
1439 break;
1440
1441 case T_OBJECT:
1442 // There are only equal/notequal comparisons on objects.
1443 {
1444 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "oops");
1445 jobject con = opr2->as_constant_ptr()->as_jobject();
1446 if (con == NULL) {
1447 __ cmpdi(BOOL_RESULT, opr1->as_register(), 0);
1448 } else {
1449 jobject2reg(con, R0);
1450 __ cmpd(BOOL_RESULT, opr1->as_register(), R0);
1451 }
1452 }
1453 break;
1454
1455 case T_METADATA:
1456 // We only need, for now, comparison with NULL for metadata.
1457 {
1458 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "oops");
1459 Metadata* p = opr2->as_constant_ptr()->as_metadata();
1460 if (p == NULL) {
1461 __ cmpdi(BOOL_RESULT, opr1->as_register(), 0);
1462 } else {
1463 ShouldNotReachHere();
1464 }
1465 }
1466 break;
1467
1468 default:
1469 ShouldNotReachHere();
1470 break;
1471 }
1472 } else {
1473 assert(opr1->type() != T_ADDRESS && opr2->type() != T_ADDRESS, "currently unsupported");
1474 if (is_reference_type(opr1->type())) {
1475 // There are only equal/notequal comparisons on objects.
1476 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "oops");
1477 __ cmpd(BOOL_RESULT, opr1->as_register(), opr2->as_register());
1478 } else {
1479 if (unsigned_comp) {
1480 __ cmplw(BOOL_RESULT, opr1->as_register(), opr2->as_register());
1481 } else {
1482 __ cmpw(BOOL_RESULT, opr1->as_register(), opr2->as_register());
1483 }
1484 }
1485 }
1486 } else if (opr1->is_double_cpu()) {
1487 if (opr2->is_constant()) {
1488 jlong con = opr2->as_constant_ptr()->as_jlong();
1489 if (unsigned_comp) {
1490 if (Assembler::is_uimm(con, 16)) {
1491 __ cmpldi(BOOL_RESULT, opr1->as_register_lo(), con);
1492 } else {
1493 __ load_const_optimized(R0, con);
1494 __ cmpld(BOOL_RESULT, opr1->as_register_lo(), R0);
1495 }
1496 } else {
1497 if (Assembler::is_simm(con, 16)) {
1498 __ cmpdi(BOOL_RESULT, opr1->as_register_lo(), con);
1499 } else {
1500 __ load_const_optimized(R0, con);
1501 __ cmpd(BOOL_RESULT, opr1->as_register_lo(), R0);
1502 }
1503 }
1504 } else if (opr2->is_register()) {
1505 if (unsigned_comp) {
1506 __ cmpld(BOOL_RESULT, opr1->as_register_lo(), opr2->as_register_lo());
1507 } else {
1508 __ cmpd(BOOL_RESULT, opr1->as_register_lo(), opr2->as_register_lo());
1509 }
1510 } else {
1511 ShouldNotReachHere();
1512 }
1513 } else {
1514 ShouldNotReachHere();
1515 }
1516 }
1517
1518
1519 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op){
1520 const Register Rdst = dst->as_register();
1521 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
1522 bool is_unordered_less = (code == lir_ucmp_fd2i);
1523 if (left->is_single_fpu()) {
1524 __ fcmpu(CCR0, left->as_float_reg(), right->as_float_reg());
1525 } else if (left->is_double_fpu()) {
1526 __ fcmpu(CCR0, left->as_double_reg(), right->as_double_reg());
1527 } else {
1528 ShouldNotReachHere();
1529 }
1530 __ set_cmpu3(Rdst, is_unordered_less); // is_unordered_less ? -1 : 1
1531 } else if (code == lir_cmp_l2i) {
1532 __ cmpd(CCR0, left->as_register_lo(), right->as_register_lo());
1533 __ set_cmp3(Rdst); // set result as follows: <: -1, =: 0, >: 1
1534 } else {
1535 ShouldNotReachHere();
1536 }
1537 }
1538
1539
1540 inline void load_to_reg(LIR_Assembler *lasm, LIR_Opr src, LIR_Opr dst) {
1541 if (src->is_constant()) {
1542 lasm->const2reg(src, dst, lir_patch_none, NULL);
1543 } else if (src->is_register()) {
1544 lasm->reg2reg(src, dst);
1545 } else if (src->is_stack()) {
1546 lasm->stack2reg(src, dst, dst->type());
1547 } else {
1548 ShouldNotReachHere();
1549 }
1550 }
1551
1552 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type,
1553 LIR_Opr cmp_opr1, LIR_Opr cmp_opr2) {
1554 assert(cmp_opr1 == LIR_OprFact::illegalOpr && cmp_opr2 == LIR_OprFact::illegalOpr, "unnecessary cmp oprs on ppc");
1555
1556 if (opr1->is_equal(opr2) || opr1->is_same_register(opr2)) {
1557 load_to_reg(this, opr1, result); // Condition doesn't matter.
1558 return;
1559 }
1560
1561 bool positive = false;
1562 Assembler::Condition cond = Assembler::equal;
1563 switch (condition) {
1564 case lir_cond_equal: positive = true ; cond = Assembler::equal ; break;
1565 case lir_cond_notEqual: positive = false; cond = Assembler::equal ; break;
1566 case lir_cond_less: positive = true ; cond = Assembler::less ; break;
1567 case lir_cond_belowEqual:
1568 case lir_cond_lessEqual: positive = false; cond = Assembler::greater; break;
1569 case lir_cond_greater: positive = true ; cond = Assembler::greater; break;
1570 case lir_cond_aboveEqual:
1571 case lir_cond_greaterEqual: positive = false; cond = Assembler::less ; break;
1572 default: ShouldNotReachHere();
1573 }
1574
1575 // Try to use isel on >=Power7.
1576 if (VM_Version::has_isel() && result->is_cpu_register()) {
1577 bool o1_is_reg = opr1->is_cpu_register(), o2_is_reg = opr2->is_cpu_register();
1578 const Register result_reg = result->is_single_cpu() ? result->as_register() : result->as_register_lo();
1579
1580 // We can use result_reg to load one operand if not already in register.
1581 Register first = o1_is_reg ? (opr1->is_single_cpu() ? opr1->as_register() : opr1->as_register_lo()) : result_reg,
1582 second = o2_is_reg ? (opr2->is_single_cpu() ? opr2->as_register() : opr2->as_register_lo()) : result_reg;
1583
1584 if (first != second) {
1585 if (!o1_is_reg) {
1586 load_to_reg(this, opr1, result);
1587 }
1588
1589 if (!o2_is_reg) {
1590 load_to_reg(this, opr2, result);
1591 }
1592
1593 __ isel(result_reg, BOOL_RESULT, cond, !positive, first, second);
1594 return;
1595 }
1596 } // isel
1597
1598 load_to_reg(this, opr1, result);
1599
1600 Label skip;
1601 int bo = positive ? Assembler::bcondCRbiIs1 : Assembler::bcondCRbiIs0;
1602 int bi = Assembler::bi0(BOOL_RESULT, cond);
1603 __ bc(bo, bi, skip);
1604
1605 load_to_reg(this, opr2, result);
1606 __ bind(skip);
1607 }
1608
1609
1610 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest,
1611 CodeEmitInfo* info, bool pop_fpu_stack) {
1612 assert(info == NULL, "unused on this code path");
1613 assert(left->is_register(), "wrong items state");
1614 assert(dest->is_register(), "wrong items state");
1615
1616 if (right->is_register()) {
1617 if (dest->is_float_kind()) {
1618
1619 FloatRegister lreg, rreg, res;
1620 if (right->is_single_fpu()) {
1621 lreg = left->as_float_reg();
1622 rreg = right->as_float_reg();
1623 res = dest->as_float_reg();
1624 switch (code) {
1625 case lir_add: __ fadds(res, lreg, rreg); break;
1626 case lir_sub: __ fsubs(res, lreg, rreg); break;
1627 case lir_mul: __ fmuls(res, lreg, rreg); break;
1628 case lir_div: __ fdivs(res, lreg, rreg); break;
1629 default: ShouldNotReachHere();
1630 }
1631 } else {
1632 lreg = left->as_double_reg();
1633 rreg = right->as_double_reg();
1634 res = dest->as_double_reg();
1635 switch (code) {
1636 case lir_add: __ fadd(res, lreg, rreg); break;
1637 case lir_sub: __ fsub(res, lreg, rreg); break;
1638 case lir_mul: __ fmul(res, lreg, rreg); break;
1639 case lir_div: __ fdiv(res, lreg, rreg); break;
1640 default: ShouldNotReachHere();
1641 }
1642 }
1643
1644 } else if (dest->is_double_cpu()) {
1645
1646 Register dst_lo = dest->as_register_lo();
1647 Register op1_lo = left->as_pointer_register();
1648 Register op2_lo = right->as_pointer_register();
1649
1650 switch (code) {
1651 case lir_add: __ add(dst_lo, op1_lo, op2_lo); break;
1652 case lir_sub: __ sub(dst_lo, op1_lo, op2_lo); break;
1653 case lir_mul: __ mulld(dst_lo, op1_lo, op2_lo); break;
1654 default: ShouldNotReachHere();
1655 }
1656 } else {
1657 assert (right->is_single_cpu(), "Just Checking");
1658
1659 Register lreg = left->as_register();
1660 Register res = dest->as_register();
1661 Register rreg = right->as_register();
1662 switch (code) {
1663 case lir_add: __ add (res, lreg, rreg); break;
1664 case lir_sub: __ sub (res, lreg, rreg); break;
1665 case lir_mul: __ mullw(res, lreg, rreg); break;
1666 default: ShouldNotReachHere();
1667 }
1668 }
1669 } else {
1670 assert (right->is_constant(), "must be constant");
1671
1672 if (dest->is_single_cpu()) {
1673 Register lreg = left->as_register();
1674 Register res = dest->as_register();
1675 int simm16 = right->as_constant_ptr()->as_jint();
1676
1677 switch (code) {
1678 case lir_sub: assert(Assembler::is_simm16(-simm16), "cannot encode"); // see do_ArithmeticOp_Int
1679 simm16 = -simm16;
1680 case lir_add: if (res == lreg && simm16 == 0) break;
1681 __ addi(res, lreg, simm16); break;
1682 case lir_mul: if (res == lreg && simm16 == 1) break;
1683 __ mulli(res, lreg, simm16); break;
1684 default: ShouldNotReachHere();
1685 }
1686 } else {
1687 Register lreg = left->as_pointer_register();
1688 Register res = dest->as_register_lo();
1689 long con = right->as_constant_ptr()->as_jlong();
1690 assert(Assembler::is_simm16(con), "must be simm16");
1691
1692 switch (code) {
1693 case lir_sub: assert(Assembler::is_simm16(-con), "cannot encode"); // see do_ArithmeticOp_Long
1694 con = -con;
1695 case lir_add: if (res == lreg && con == 0) break;
1696 __ addi(res, lreg, (int)con); break;
1697 case lir_mul: if (res == lreg && con == 1) break;
1698 __ mulli(res, lreg, (int)con); break;
1699 default: ShouldNotReachHere();
1700 }
1701 }
1702 }
1703 }
1704
1705
1706 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr thread, LIR_Opr dest, LIR_Op* op) {
1707 switch (code) {
1708 case lir_sqrt: {
1709 __ fsqrt(dest->as_double_reg(), value->as_double_reg());
1710 break;
1711 }
1712 case lir_abs: {
1713 __ fabs(dest->as_double_reg(), value->as_double_reg());
1714 break;
1715 }
1716 default: {
1717 ShouldNotReachHere();
1718 break;
1719 }
1720 }
1721 }
1722
1723
1724 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest) {
1725 if (right->is_constant()) { // see do_LogicOp
1726 long uimm;
1727 Register d, l;
1728 if (dest->is_single_cpu()) {
1729 uimm = right->as_constant_ptr()->as_jint();
1730 d = dest->as_register();
1731 l = left->as_register();
1732 } else {
1733 uimm = right->as_constant_ptr()->as_jlong();
1734 d = dest->as_register_lo();
1735 l = left->as_register_lo();
1736 }
1737 long uimms = (unsigned long)uimm >> 16,
1738 uimmss = (unsigned long)uimm >> 32;
1739
1740 switch (code) {
1741 case lir_logic_and:
1742 if (uimmss != 0 || (uimms != 0 && (uimm & 0xFFFF) != 0) || is_power_of_2(uimm)) {
1743 __ andi(d, l, uimm); // special cases
1744 } else if (uimms != 0) { __ andis_(d, l, uimms); }
1745 else { __ andi_(d, l, uimm); }
1746 break;
1747
1748 case lir_logic_or:
1749 if (uimms != 0) { assert((uimm & 0xFFFF) == 0, "sanity"); __ oris(d, l, uimms); }
1750 else { __ ori(d, l, uimm); }
1751 break;
1752
1753 case lir_logic_xor:
1754 if (uimm == -1) { __ nand(d, l, l); } // special case
1755 else if (uimms != 0) { assert((uimm & 0xFFFF) == 0, "sanity"); __ xoris(d, l, uimms); }
1756 else { __ xori(d, l, uimm); }
1757 break;
1758
1759 default: ShouldNotReachHere();
1760 }
1761 } else {
1762 assert(right->is_register(), "right should be in register");
1763
1764 if (dest->is_single_cpu()) {
1765 switch (code) {
1766 case lir_logic_and: __ andr(dest->as_register(), left->as_register(), right->as_register()); break;
1767 case lir_logic_or: __ orr (dest->as_register(), left->as_register(), right->as_register()); break;
1768 case lir_logic_xor: __ xorr(dest->as_register(), left->as_register(), right->as_register()); break;
1769 default: ShouldNotReachHere();
1770 }
1771 } else {
1772 Register l = (left->is_single_cpu() && left->is_oop_register()) ? left->as_register() :
1773 left->as_register_lo();
1774 Register r = (right->is_single_cpu() && right->is_oop_register()) ? right->as_register() :
1775 right->as_register_lo();
1776
1777 switch (code) {
1778 case lir_logic_and: __ andr(dest->as_register_lo(), l, r); break;
1779 case lir_logic_or: __ orr (dest->as_register_lo(), l, r); break;
1780 case lir_logic_xor: __ xorr(dest->as_register_lo(), l, r); break;
1781 default: ShouldNotReachHere();
1782 }
1783 }
1784 }
1785 }
1786
1787
1788 int LIR_Assembler::shift_amount(BasicType t) {
1789 int elem_size = type2aelembytes(t);
1790 switch (elem_size) {
1791 case 1 : return 0;
1792 case 2 : return 1;
1793 case 4 : return 2;
1794 case 8 : return 3;
1795 }
1796 ShouldNotReachHere();
1797 return -1;
1798 }
1799
1800
1801 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
1802 info->add_register_oop(exceptionOop);
1803
1804 // Reuse the debug info from the safepoint poll for the throw op itself.
1805 address pc_for_athrow = __ pc();
1806 int pc_for_athrow_offset = __ offset();
1807 //RelocationHolder rspec = internal_word_Relocation::spec(pc_for_athrow);
1808 //__ relocate(rspec);
1809 //__ load_const(exceptionPC->as_register(), pc_for_athrow, R0);
1810 __ calculate_address_from_global_toc(exceptionPC->as_register(), pc_for_athrow, true, true, /*add_relocation*/ true);
1811 add_call_info(pc_for_athrow_offset, info); // for exception handler
1812
1813 address stub = Runtime1::entry_for(compilation()->has_fpu_code() ? Runtime1::handle_exception_id
1814 : Runtime1::handle_exception_nofpu_id);
1815 //__ load_const_optimized(R0, stub);
1816 __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(stub));
1817 __ mtctr(R0);
1818 __ bctr();
1819 }
1820
1821
1822 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
1823 // Note: Not used with EnableDebuggingOnDemand.
1824 assert(exceptionOop->as_register() == R3, "should match");
1825 __ b(_unwind_handler_entry);
1826 }
1827
1828
1829 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
1830 Register src = op->src()->as_register();
1831 Register dst = op->dst()->as_register();
1832 Register src_pos = op->src_pos()->as_register();
1833 Register dst_pos = op->dst_pos()->as_register();
1834 Register length = op->length()->as_register();
1835 Register tmp = op->tmp()->as_register();
1836 Register tmp2 = R0;
1837
1838 int flags = op->flags();
1839 ciArrayKlass* default_type = op->expected_type();
1840 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL;
1841 if (basic_type == T_ARRAY) basic_type = T_OBJECT;
1842
1843 // Set up the arraycopy stub information.
1844 ArrayCopyStub* stub = op->stub();
1845 const int frame_resize = frame::abi_reg_args_size - sizeof(frame::jit_abi); // C calls need larger frame.
1846
1847 // Always do stub if no type information is available. It's ok if
1848 // the known type isn't loaded since the code sanity checks
1849 // in debug mode and the type isn't required when we know the exact type
1850 // also check that the type is an array type.
1851 if (op->expected_type() == NULL) {
1852 assert(src->is_nonvolatile() && src_pos->is_nonvolatile() && dst->is_nonvolatile() && dst_pos->is_nonvolatile() &&
1853 length->is_nonvolatile(), "must preserve");
1854 address copyfunc_addr = StubRoutines::generic_arraycopy();
1855 assert(copyfunc_addr != NULL, "generic arraycopy stub required");
1856
1857 // 3 parms are int. Convert to long.
1858 __ mr(R3_ARG1, src);
1859 __ extsw(R4_ARG2, src_pos);
1860 __ mr(R5_ARG3, dst);
1861 __ extsw(R6_ARG4, dst_pos);
1862 __ extsw(R7_ARG5, length);
1863
1864 #ifndef PRODUCT
1865 if (PrintC1Statistics) {
1866 address counter = (address)&Runtime1::_generic_arraycopystub_cnt;
1867 int simm16_offs = __ load_const_optimized(tmp, counter, tmp2, true);
1868 __ lwz(R11_scratch1, simm16_offs, tmp);
1869 __ addi(R11_scratch1, R11_scratch1, 1);
1870 __ stw(R11_scratch1, simm16_offs, tmp);
1871 }
1872 #endif
1873 __ call_c_with_frame_resize(copyfunc_addr, /*stub does not need resized frame*/ 0);
1874
1875 __ nand(tmp, R3_RET, R3_RET);
1876 __ subf(length, tmp, length);
1877 __ add(src_pos, tmp, src_pos);
1878 __ add(dst_pos, tmp, dst_pos);
1879
1880 __ cmpwi(CCR0, R3_RET, 0);
1881 __ bc_far_optimized(Assembler::bcondCRbiIs1, __ bi0(CCR0, Assembler::less), *stub->entry());
1882 __ bind(*stub->continuation());
1883 return;
1884 }
1885
1886 assert(default_type != NULL && default_type->is_array_klass(), "must be true at this point");
1887 Label cont, slow, copyfunc;
1888
1889 bool simple_check_flag_set = flags & (LIR_OpArrayCopy::src_null_check |
1890 LIR_OpArrayCopy::dst_null_check |
1891 LIR_OpArrayCopy::src_pos_positive_check |
1892 LIR_OpArrayCopy::dst_pos_positive_check |
1893 LIR_OpArrayCopy::length_positive_check);
1894
1895 // Use only one conditional branch for simple checks.
1896 if (simple_check_flag_set) {
1897 ConditionRegister combined_check = CCR1, tmp_check = CCR1;
1898
1899 // Make sure src and dst are non-null.
1900 if (flags & LIR_OpArrayCopy::src_null_check) {
1901 __ cmpdi(combined_check, src, 0);
1902 tmp_check = CCR0;
1903 }
1904
1905 if (flags & LIR_OpArrayCopy::dst_null_check) {
1906 __ cmpdi(tmp_check, dst, 0);
1907 if (tmp_check != combined_check) {
1908 __ cror(combined_check, Assembler::equal, tmp_check, Assembler::equal);
1909 }
1910 tmp_check = CCR0;
1911 }
1912
1913 // Clear combined_check.eq if not already used.
1914 if (tmp_check == combined_check) {
1915 __ crandc(combined_check, Assembler::equal, combined_check, Assembler::equal);
1916 tmp_check = CCR0;
1917 }
1918
1919 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
1920 // Test src_pos register.
1921 __ cmpwi(tmp_check, src_pos, 0);
1922 __ cror(combined_check, Assembler::equal, tmp_check, Assembler::less);
1923 }
1924
1925 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
1926 // Test dst_pos register.
1927 __ cmpwi(tmp_check, dst_pos, 0);
1928 __ cror(combined_check, Assembler::equal, tmp_check, Assembler::less);
1929 }
1930
1931 if (flags & LIR_OpArrayCopy::length_positive_check) {
1932 // Make sure length isn't negative.
1933 __ cmpwi(tmp_check, length, 0);
1934 __ cror(combined_check, Assembler::equal, tmp_check, Assembler::less);
1935 }
1936
1937 __ beq(combined_check, slow);
1938 }
1939
1940 // If the compiler was not able to prove that exact type of the source or the destination
1941 // of the arraycopy is an array type, check at runtime if the source or the destination is
1942 // an instance type.
1943 if (flags & LIR_OpArrayCopy::type_check) {
1944 if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
1945 __ load_klass(tmp, dst);
1946 __ lwz(tmp2, in_bytes(Klass::layout_helper_offset()), tmp);
1947 __ cmpwi(CCR0, tmp2, Klass::_lh_neutral_value);
1948 __ bge(CCR0, slow);
1949 }
1950
1951 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
1952 __ load_klass(tmp, src);
1953 __ lwz(tmp2, in_bytes(Klass::layout_helper_offset()), tmp);
1954 __ cmpwi(CCR0, tmp2, Klass::_lh_neutral_value);
1955 __ bge(CCR0, slow);
1956 }
1957 }
1958
1959 // Higher 32bits must be null.
1960 __ extsw(length, length);
1961
1962 __ extsw(src_pos, src_pos);
1963 if (flags & LIR_OpArrayCopy::src_range_check) {
1964 __ lwz(tmp2, arrayOopDesc::length_offset_in_bytes(), src);
1965 __ add(tmp, length, src_pos);
1966 __ cmpld(CCR0, tmp2, tmp);
1967 __ ble(CCR0, slow);
1968 }
1969
1970 __ extsw(dst_pos, dst_pos);
1971 if (flags & LIR_OpArrayCopy::dst_range_check) {
1972 __ lwz(tmp2, arrayOopDesc::length_offset_in_bytes(), dst);
1973 __ add(tmp, length, dst_pos);
1974 __ cmpld(CCR0, tmp2, tmp);
1975 __ ble(CCR0, slow);
1976 }
1977
1978 int shift = shift_amount(basic_type);
1979
1980 if (!(flags & LIR_OpArrayCopy::type_check)) {
1981 __ b(cont);
1982 } else {
1983 // We don't know the array types are compatible.
1984 if (basic_type != T_OBJECT) {
1985 // Simple test for basic type arrays.
1986 if (UseCompressedClassPointers) {
1987 // We don't need decode because we just need to compare.
1988 __ lwz(tmp, oopDesc::klass_offset_in_bytes(), src);
1989 __ lwz(tmp2, oopDesc::klass_offset_in_bytes(), dst);
1990 __ cmpw(CCR0, tmp, tmp2);
1991 } else {
1992 __ ld(tmp, oopDesc::klass_offset_in_bytes(), src);
1993 __ ld(tmp2, oopDesc::klass_offset_in_bytes(), dst);
1994 __ cmpd(CCR0, tmp, tmp2);
1995 }
1996 __ beq(CCR0, cont);
1997 } else {
1998 // For object arrays, if src is a sub class of dst then we can
1999 // safely do the copy.
2000 address copyfunc_addr = StubRoutines::checkcast_arraycopy();
2001
2002 const Register sub_klass = R5, super_klass = R4; // like CheckCast/InstanceOf
2003 assert_different_registers(tmp, tmp2, sub_klass, super_klass);
2004
2005 __ load_klass(sub_klass, src);
2006 __ load_klass(super_klass, dst);
2007
2008 __ check_klass_subtype_fast_path(sub_klass, super_klass, tmp, tmp2,
2009 &cont, copyfunc_addr != NULL ? ©func : &slow, NULL);
2010
2011 address slow_stc = Runtime1::entry_for(Runtime1::slow_subtype_check_id);
2012 //__ load_const_optimized(tmp, slow_stc, tmp2);
2013 __ calculate_address_from_global_toc(tmp, slow_stc, true, true, false);
2014 __ mtctr(tmp);
2015 __ bctrl(); // sets CR0
2016 __ beq(CCR0, cont);
2017
2018 if (copyfunc_addr != NULL) { // Use stub if available.
2019 __ bind(copyfunc);
2020 // Src is not a sub class of dst so we have to do a
2021 // per-element check.
2022 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
2023 if ((flags & mask) != mask) {
2024 assert(flags & mask, "one of the two should be known to be an object array");
2025
2026 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
2027 __ load_klass(tmp, src);
2028 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
2029 __ load_klass(tmp, dst);
2030 }
2031
2032 __ lwz(tmp2, in_bytes(Klass::layout_helper_offset()), tmp);
2033
2034 jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
2035 __ load_const_optimized(tmp, objArray_lh);
2036 __ cmpw(CCR0, tmp, tmp2);
2037 __ bne(CCR0, slow);
2038 }
2039
2040 Register src_ptr = R3_ARG1;
2041 Register dst_ptr = R4_ARG2;
2042 Register len = R5_ARG3;
2043 Register chk_off = R6_ARG4;
2044 Register super_k = R7_ARG5;
2045
2046 __ addi(src_ptr, src, arrayOopDesc::base_offset_in_bytes(basic_type));
2047 __ addi(dst_ptr, dst, arrayOopDesc::base_offset_in_bytes(basic_type));
2048 if (shift == 0) {
2049 __ add(src_ptr, src_pos, src_ptr);
2050 __ add(dst_ptr, dst_pos, dst_ptr);
2051 } else {
2052 __ sldi(tmp, src_pos, shift);
2053 __ sldi(tmp2, dst_pos, shift);
2054 __ add(src_ptr, tmp, src_ptr);
2055 __ add(dst_ptr, tmp2, dst_ptr);
2056 }
2057
2058 __ load_klass(tmp, dst);
2059 __ mr(len, length);
2060
2061 int ek_offset = in_bytes(ObjArrayKlass::element_klass_offset());
2062 __ ld(super_k, ek_offset, tmp);
2063
2064 int sco_offset = in_bytes(Klass::super_check_offset_offset());
2065 __ lwz(chk_off, sco_offset, super_k);
2066
2067 __ call_c_with_frame_resize(copyfunc_addr, /*stub does not need resized frame*/ 0);
2068
2069 #ifndef PRODUCT
2070 if (PrintC1Statistics) {
2071 Label failed;
2072 __ cmpwi(CCR0, R3_RET, 0);
2073 __ bne(CCR0, failed);
2074 address counter = (address)&Runtime1::_arraycopy_checkcast_cnt;
2075 int simm16_offs = __ load_const_optimized(tmp, counter, tmp2, true);
2076 __ lwz(R11_scratch1, simm16_offs, tmp);
2077 __ addi(R11_scratch1, R11_scratch1, 1);
2078 __ stw(R11_scratch1, simm16_offs, tmp);
2079 __ bind(failed);
2080 }
2081 #endif
2082
2083 __ nand(tmp, R3_RET, R3_RET);
2084 __ cmpwi(CCR0, R3_RET, 0);
2085 __ beq(CCR0, *stub->continuation());
2086
2087 #ifndef PRODUCT
2088 if (PrintC1Statistics) {
2089 address counter = (address)&Runtime1::_arraycopy_checkcast_attempt_cnt;
2090 int simm16_offs = __ load_const_optimized(tmp, counter, tmp2, true);
2091 __ lwz(R11_scratch1, simm16_offs, tmp);
2092 __ addi(R11_scratch1, R11_scratch1, 1);
2093 __ stw(R11_scratch1, simm16_offs, tmp);
2094 }
2095 #endif
2096
2097 __ subf(length, tmp, length);
2098 __ add(src_pos, tmp, src_pos);
2099 __ add(dst_pos, tmp, dst_pos);
2100 }
2101 }
2102 }
2103 __ bind(slow);
2104 __ b(*stub->entry());
2105 __ bind(cont);
2106
2107 #ifdef ASSERT
2108 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
2109 // Sanity check the known type with the incoming class. For the
2110 // primitive case the types must match exactly with src.klass and
2111 // dst.klass each exactly matching the default type. For the
2112 // object array case, if no type check is needed then either the
2113 // dst type is exactly the expected type and the src type is a
2114 // subtype which we can't check or src is the same array as dst
2115 // but not necessarily exactly of type default_type.
2116 Label known_ok, halt;
2117 metadata2reg(op->expected_type()->constant_encoding(), tmp);
2118 if (UseCompressedClassPointers) {
2119 // Tmp holds the default type. It currently comes uncompressed after the
2120 // load of a constant, so encode it.
2121 __ encode_klass_not_null(tmp);
2122 // Load the raw value of the dst klass, since we will be comparing
2123 // uncompressed values directly.
2124 __ lwz(tmp2, oopDesc::klass_offset_in_bytes(), dst);
2125 __ cmpw(CCR0, tmp, tmp2);
2126 if (basic_type != T_OBJECT) {
2127 __ bne(CCR0, halt);
2128 // Load the raw value of the src klass.
2129 __ lwz(tmp2, oopDesc::klass_offset_in_bytes(), src);
2130 __ cmpw(CCR0, tmp, tmp2);
2131 __ beq(CCR0, known_ok);
2132 } else {
2133 __ beq(CCR0, known_ok);
2134 __ cmpw(CCR0, src, dst);
2135 __ beq(CCR0, known_ok);
2136 }
2137 } else {
2138 __ ld(tmp2, oopDesc::klass_offset_in_bytes(), dst);
2139 __ cmpd(CCR0, tmp, tmp2);
2140 if (basic_type != T_OBJECT) {
2141 __ bne(CCR0, halt);
2142 // Load the raw value of the src klass.
2143 __ ld(tmp2, oopDesc::klass_offset_in_bytes(), src);
2144 __ cmpd(CCR0, tmp, tmp2);
2145 __ beq(CCR0, known_ok);
2146 } else {
2147 __ beq(CCR0, known_ok);
2148 __ cmpd(CCR0, src, dst);
2149 __ beq(CCR0, known_ok);
2150 }
2151 }
2152 __ bind(halt);
2153 __ stop("incorrect type information in arraycopy");
2154 __ bind(known_ok);
2155 }
2156 #endif
2157
2158 #ifndef PRODUCT
2159 if (PrintC1Statistics) {
2160 address counter = Runtime1::arraycopy_count_address(basic_type);
2161 int simm16_offs = __ load_const_optimized(tmp, counter, tmp2, true);
2162 __ lwz(R11_scratch1, simm16_offs, tmp);
2163 __ addi(R11_scratch1, R11_scratch1, 1);
2164 __ stw(R11_scratch1, simm16_offs, tmp);
2165 }
2166 #endif
2167
2168 Register src_ptr = R3_ARG1;
2169 Register dst_ptr = R4_ARG2;
2170 Register len = R5_ARG3;
2171
2172 __ addi(src_ptr, src, arrayOopDesc::base_offset_in_bytes(basic_type));
2173 __ addi(dst_ptr, dst, arrayOopDesc::base_offset_in_bytes(basic_type));
2174 if (shift == 0) {
2175 __ add(src_ptr, src_pos, src_ptr);
2176 __ add(dst_ptr, dst_pos, dst_ptr);
2177 } else {
2178 __ sldi(tmp, src_pos, shift);
2179 __ sldi(tmp2, dst_pos, shift);
2180 __ add(src_ptr, tmp, src_ptr);
2181 __ add(dst_ptr, tmp2, dst_ptr);
2182 }
2183
2184 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
2185 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
2186 const char *name;
2187 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
2188
2189 // Arraycopy stubs takes a length in number of elements, so don't scale it.
2190 __ mr(len, length);
2191 __ call_c_with_frame_resize(entry, /*stub does not need resized frame*/ 0);
2192
2193 __ bind(*stub->continuation());
2194 }
2195
2196
2197 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2198 if (dest->is_single_cpu()) {
2199 __ rldicl(tmp->as_register(), count->as_register(), 0, 64-5);
2200 #ifdef _LP64
2201 if (left->type() == T_OBJECT) {
2202 switch (code) {
2203 case lir_shl: __ sld(dest->as_register(), left->as_register(), tmp->as_register()); break;
2204 case lir_shr: __ srad(dest->as_register(), left->as_register(), tmp->as_register()); break;
2205 case lir_ushr: __ srd(dest->as_register(), left->as_register(), tmp->as_register()); break;
2206 default: ShouldNotReachHere();
2207 }
2208 } else
2209 #endif
2210 switch (code) {
2211 case lir_shl: __ slw(dest->as_register(), left->as_register(), tmp->as_register()); break;
2212 case lir_shr: __ sraw(dest->as_register(), left->as_register(), tmp->as_register()); break;
2213 case lir_ushr: __ srw(dest->as_register(), left->as_register(), tmp->as_register()); break;
2214 default: ShouldNotReachHere();
2215 }
2216 } else {
2217 __ rldicl(tmp->as_register(), count->as_register(), 0, 64-6);
2218 switch (code) {
2219 case lir_shl: __ sld(dest->as_register_lo(), left->as_register_lo(), tmp->as_register()); break;
2220 case lir_shr: __ srad(dest->as_register_lo(), left->as_register_lo(), tmp->as_register()); break;
2221 case lir_ushr: __ srd(dest->as_register_lo(), left->as_register_lo(), tmp->as_register()); break;
2222 default: ShouldNotReachHere();
2223 }
2224 }
2225 }
2226
2227
2228 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2229 #ifdef _LP64
2230 if (left->type() == T_OBJECT) {
2231 count = count & 63; // Shouldn't shift by more than sizeof(intptr_t).
2232 if (count == 0) { __ mr_if_needed(dest->as_register_lo(), left->as_register()); }
2233 else {
2234 switch (code) {
2235 case lir_shl: __ sldi(dest->as_register_lo(), left->as_register(), count); break;
2236 case lir_shr: __ sradi(dest->as_register_lo(), left->as_register(), count); break;
2237 case lir_ushr: __ srdi(dest->as_register_lo(), left->as_register(), count); break;
2238 default: ShouldNotReachHere();
2239 }
2240 }
2241 return;
2242 }
2243 #endif
2244
2245 if (dest->is_single_cpu()) {
2246 count = count & 0x1F; // Java spec
2247 if (count == 0) { __ mr_if_needed(dest->as_register(), left->as_register()); }
2248 else {
2249 switch (code) {
2250 case lir_shl: __ slwi(dest->as_register(), left->as_register(), count); break;
2251 case lir_shr: __ srawi(dest->as_register(), left->as_register(), count); break;
2252 case lir_ushr: __ srwi(dest->as_register(), left->as_register(), count); break;
2253 default: ShouldNotReachHere();
2254 }
2255 }
2256 } else if (dest->is_double_cpu()) {
2257 count = count & 63; // Java spec
2258 if (count == 0) { __ mr_if_needed(dest->as_pointer_register(), left->as_pointer_register()); }
2259 else {
2260 switch (code) {
2261 case lir_shl: __ sldi(dest->as_pointer_register(), left->as_pointer_register(), count); break;
2262 case lir_shr: __ sradi(dest->as_pointer_register(), left->as_pointer_register(), count); break;
2263 case lir_ushr: __ srdi(dest->as_pointer_register(), left->as_pointer_register(), count); break;
2264 default: ShouldNotReachHere();
2265 }
2266 }
2267 } else {
2268 ShouldNotReachHere();
2269 }
2270 }
2271
2272
2273 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
2274 if (op->init_check()) {
2275 if (!os::zero_page_read_protected() || !ImplicitNullChecks) {
2276 explicit_null_check(op->klass()->as_register(), op->stub()->info());
2277 } else {
2278 add_debug_info_for_null_check_here(op->stub()->info());
2279 }
2280 __ lbz(op->tmp1()->as_register(),
2281 in_bytes(InstanceKlass::init_state_offset()), op->klass()->as_register());
2282 __ cmpwi(CCR0, op->tmp1()->as_register(), InstanceKlass::fully_initialized);
2283 __ bc_far_optimized(Assembler::bcondCRbiIs0, __ bi0(CCR0, Assembler::equal), *op->stub()->entry());
2284 }
2285 __ allocate_object(op->obj()->as_register(),
2286 op->tmp1()->as_register(),
2287 op->tmp2()->as_register(),
2288 op->tmp3()->as_register(),
2289 op->header_size(),
2290 op->object_size(),
2291 op->klass()->as_register(),
2292 *op->stub()->entry());
2293
2294 __ bind(*op->stub()->continuation());
2295 __ verify_oop(op->obj()->as_register(), FILE_AND_LINE);
2296 }
2297
2298
2299 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
2300 LP64_ONLY( __ extsw(op->len()->as_register(), op->len()->as_register()); )
2301 if (UseSlowPath ||
2302 (!UseFastNewObjectArray && (is_reference_type(op->type()))) ||
2303 (!UseFastNewTypeArray && (!is_reference_type(op->type())))) {
2304 __ b(*op->stub()->entry());
2305 } else {
2306 __ allocate_array(op->obj()->as_register(),
2307 op->len()->as_register(),
2308 op->tmp1()->as_register(),
2309 op->tmp2()->as_register(),
2310 op->tmp3()->as_register(),
2311 arrayOopDesc::header_size(op->type()),
2312 type2aelembytes(op->type()),
2313 op->klass()->as_register(),
2314 *op->stub()->entry());
2315 }
2316 __ bind(*op->stub()->continuation());
2317 }
2318
2319
2320 void LIR_Assembler::type_profile_helper(Register mdo, int mdo_offset_bias,
2321 ciMethodData *md, ciProfileData *data,
2322 Register recv, Register tmp1, Label* update_done) {
2323 uint i;
2324 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2325 Label next_test;
2326 // See if the receiver is receiver[n].
2327 __ ld(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) - mdo_offset_bias, mdo);
2328 __ verify_klass_ptr(tmp1);
2329 __ cmpd(CCR0, recv, tmp1);
2330 __ bne(CCR0, next_test);
2331
2332 __ ld(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2333 __ addi(tmp1, tmp1, DataLayout::counter_increment);
2334 __ std(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2335 __ b(*update_done);
2336
2337 __ bind(next_test);
2338 }
2339
2340 // Didn't find receiver; find next empty slot and fill it in.
2341 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2342 Label next_test;
2343 __ ld(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) - mdo_offset_bias, mdo);
2344 __ cmpdi(CCR0, tmp1, 0);
2345 __ bne(CCR0, next_test);
2346 __ li(tmp1, DataLayout::counter_increment);
2347 __ std(recv, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) - mdo_offset_bias, mdo);
2348 __ std(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2349 __ b(*update_done);
2350
2351 __ bind(next_test);
2352 }
2353 }
2354
2355
2356 void LIR_Assembler::setup_md_access(ciMethod* method, int bci,
2357 ciMethodData*& md, ciProfileData*& data, int& mdo_offset_bias) {
2358 md = method->method_data_or_null();
2359 assert(md != NULL, "Sanity");
2360 data = md->bci_to_data(bci);
2361 assert(data != NULL, "need data for checkcast");
2362 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
2363 if (!Assembler::is_simm16(md->byte_offset_of_slot(data, DataLayout::header_offset()) + data->size_in_bytes())) {
2364 // The offset is large so bias the mdo by the base of the slot so
2365 // that the ld can use simm16s to reference the slots of the data.
2366 mdo_offset_bias = md->byte_offset_of_slot(data, DataLayout::header_offset());
2367 }
2368 }
2369
2370
2371 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
2372 const Register obj = op->object()->as_register(); // Needs to live in this register at safepoint (patching stub).
2373 Register k_RInfo = op->tmp1()->as_register();
2374 Register klass_RInfo = op->tmp2()->as_register();
2375 Register Rtmp1 = op->tmp3()->as_register();
2376 Register dst = op->result_opr()->as_register();
2377 ciKlass* k = op->klass();
2378 bool should_profile = op->should_profile();
2379 // Attention: do_temp(opTypeCheck->_object) is not used, i.e. obj may be same as one of the temps.
2380 bool reg_conflict = false;
2381 if (obj == k_RInfo) {
2382 k_RInfo = dst;
2383 reg_conflict = true;
2384 } else if (obj == klass_RInfo) {
2385 klass_RInfo = dst;
2386 reg_conflict = true;
2387 } else if (obj == Rtmp1) {
2388 Rtmp1 = dst;
2389 reg_conflict = true;
2390 }
2391 assert_different_registers(obj, k_RInfo, klass_RInfo, Rtmp1);
2392
2393 __ cmpdi(CCR0, obj, 0);
2394
2395 ciMethodData* md = NULL;
2396 ciProfileData* data = NULL;
2397 int mdo_offset_bias = 0;
2398 if (should_profile) {
2399 ciMethod* method = op->profiled_method();
2400 assert(method != NULL, "Should have method");
2401 setup_md_access(method, op->profiled_bci(), md, data, mdo_offset_bias);
2402
2403 Register mdo = k_RInfo;
2404 Register data_val = Rtmp1;
2405 Label not_null;
2406 __ bne(CCR0, not_null);
2407 metadata2reg(md->constant_encoding(), mdo);
2408 __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2409 __ lbz(data_val, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias, mdo);
2410 __ ori(data_val, data_val, BitData::null_seen_byte_constant());
2411 __ stb(data_val, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias, mdo);
2412 __ b(*obj_is_null);
2413 __ bind(not_null);
2414 } else {
2415 __ beq(CCR0, *obj_is_null);
2416 }
2417
2418 // get object class
2419 __ load_klass(klass_RInfo, obj);
2420
2421 if (k->is_loaded()) {
2422 metadata2reg(k->constant_encoding(), k_RInfo);
2423 } else {
2424 klass2reg_with_patching(k_RInfo, op->info_for_patch());
2425 }
2426
2427 Label profile_cast_failure, failure_restore_obj, profile_cast_success;
2428 Label *failure_target = should_profile ? &profile_cast_failure : failure;
2429 Label *success_target = should_profile ? &profile_cast_success : success;
2430
2431 if (op->fast_check()) {
2432 assert_different_registers(klass_RInfo, k_RInfo);
2433 __ cmpd(CCR0, k_RInfo, klass_RInfo);
2434 if (should_profile) {
2435 __ bne(CCR0, *failure_target);
2436 // Fall through to success case.
2437 } else {
2438 __ beq(CCR0, *success);
2439 // Fall through to failure case.
2440 }
2441 } else {
2442 bool need_slow_path = true;
2443 if (k->is_loaded()) {
2444 if ((int) k->super_check_offset() != in_bytes(Klass::secondary_super_cache_offset())) {
2445 need_slow_path = false;
2446 }
2447 // Perform the fast part of the checking logic.
2448 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, R0, (need_slow_path ? success_target : NULL),
2449 failure_target, NULL, RegisterOrConstant(k->super_check_offset()));
2450 } else {
2451 // Perform the fast part of the checking logic.
2452 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, R0, success_target, failure_target);
2453 }
2454 if (!need_slow_path) {
2455 if (!should_profile) { __ b(*success); }
2456 } else {
2457 // Call out-of-line instance of __ check_klass_subtype_slow_path(...):
2458 address entry = Runtime1::entry_for(Runtime1::slow_subtype_check_id);
2459 // Stub needs fixed registers (tmp1-3).
2460 Register original_k_RInfo = op->tmp1()->as_register();
2461 Register original_klass_RInfo = op->tmp2()->as_register();
2462 Register original_Rtmp1 = op->tmp3()->as_register();
2463 bool keep_obj_alive = reg_conflict && (op->code() == lir_checkcast);
2464 bool keep_klass_RInfo_alive = (obj == original_klass_RInfo) && should_profile;
2465 if (keep_obj_alive && (obj != original_Rtmp1)) { __ mr(R0, obj); }
2466 __ mr_if_needed(original_k_RInfo, k_RInfo);
2467 __ mr_if_needed(original_klass_RInfo, klass_RInfo);
2468 if (keep_obj_alive) { __ mr(dst, (obj == original_Rtmp1) ? obj : R0); }
2469 //__ load_const_optimized(original_Rtmp1, entry, R0);
2470 __ calculate_address_from_global_toc(original_Rtmp1, entry, true, true, false);
2471 __ mtctr(original_Rtmp1);
2472 __ bctrl(); // sets CR0
2473 if (keep_obj_alive) {
2474 if (keep_klass_RInfo_alive) { __ mr(R0, obj); }
2475 __ mr(obj, dst);
2476 }
2477 if (should_profile) {
2478 __ bne(CCR0, *failure_target);
2479 if (keep_klass_RInfo_alive) { __ mr(klass_RInfo, keep_obj_alive ? R0 : obj); }
2480 // Fall through to success case.
2481 } else {
2482 __ beq(CCR0, *success);
2483 // Fall through to failure case.
2484 }
2485 }
2486 }
2487
2488 if (should_profile) {
2489 Register mdo = k_RInfo, recv = klass_RInfo;
2490 assert_different_registers(mdo, recv, Rtmp1);
2491 __ bind(profile_cast_success);
2492 metadata2reg(md->constant_encoding(), mdo);
2493 __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2494 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, Rtmp1, success);
2495 __ b(*success);
2496
2497 // Cast failure case.
2498 __ bind(profile_cast_failure);
2499 metadata2reg(md->constant_encoding(), mdo);
2500 __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2501 __ ld(Rtmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2502 __ addi(Rtmp1, Rtmp1, -DataLayout::counter_increment);
2503 __ std(Rtmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2504 }
2505
2506 __ bind(*failure);
2507 }
2508
2509
2510 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
2511 LIR_Code code = op->code();
2512 if (code == lir_store_check) {
2513 Register value = op->object()->as_register();
2514 Register array = op->array()->as_register();
2515 Register k_RInfo = op->tmp1()->as_register();
2516 Register klass_RInfo = op->tmp2()->as_register();
2517 Register Rtmp1 = op->tmp3()->as_register();
2518 bool should_profile = op->should_profile();
2519
2520 __ verify_oop(value, FILE_AND_LINE);
2521 CodeStub* stub = op->stub();
2522 // Check if it needs to be profiled.
2523 ciMethodData* md = NULL;
2524 ciProfileData* data = NULL;
2525 int mdo_offset_bias = 0;
2526 if (should_profile) {
2527 ciMethod* method = op->profiled_method();
2528 assert(method != NULL, "Should have method");
2529 setup_md_access(method, op->profiled_bci(), md, data, mdo_offset_bias);
2530 }
2531 Label profile_cast_success, failure, done;
2532 Label *success_target = should_profile ? &profile_cast_success : &done;
2533
2534 __ cmpdi(CCR0, value, 0);
2535 if (should_profile) {
2536 Label not_null;
2537 __ bne(CCR0, not_null);
2538 Register mdo = k_RInfo;
2539 Register data_val = Rtmp1;
2540 metadata2reg(md->constant_encoding(), mdo);
2541 __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2542 __ lbz(data_val, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias, mdo);
2543 __ ori(data_val, data_val, BitData::null_seen_byte_constant());
2544 __ stb(data_val, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias, mdo);
2545 __ b(done);
2546 __ bind(not_null);
2547 } else {
2548 __ beq(CCR0, done);
2549 }
2550 if (!os::zero_page_read_protected() || !ImplicitNullChecks) {
2551 explicit_null_check(array, op->info_for_exception());
2552 } else {
2553 add_debug_info_for_null_check_here(op->info_for_exception());
2554 }
2555 __ load_klass(k_RInfo, array);
2556 __ load_klass(klass_RInfo, value);
2557
2558 // Get instance klass.
2559 __ ld(k_RInfo, in_bytes(ObjArrayKlass::element_klass_offset()), k_RInfo);
2560 // Perform the fast part of the checking logic.
2561 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, R0, success_target, &failure, NULL);
2562
2563 // Call out-of-line instance of __ check_klass_subtype_slow_path(...):
2564 const address slow_path = Runtime1::entry_for(Runtime1::slow_subtype_check_id);
2565 //__ load_const_optimized(R0, slow_path);
2566 __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(slow_path));
2567 __ mtctr(R0);
2568 __ bctrl(); // sets CR0
2569 if (!should_profile) {
2570 __ beq(CCR0, done);
2571 __ bind(failure);
2572 } else {
2573 __ bne(CCR0, failure);
2574 // Fall through to the success case.
2575
2576 Register mdo = klass_RInfo, recv = k_RInfo, tmp1 = Rtmp1;
2577 assert_different_registers(value, mdo, recv, tmp1);
2578 __ bind(profile_cast_success);
2579 metadata2reg(md->constant_encoding(), mdo);
2580 __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2581 __ load_klass(recv, value);
2582 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, &done);
2583 __ b(done);
2584
2585 // Cast failure case.
2586 __ bind(failure);
2587 metadata2reg(md->constant_encoding(), mdo);
2588 __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2589 Address data_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias);
2590 __ ld(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2591 __ addi(tmp1, tmp1, -DataLayout::counter_increment);
2592 __ std(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2593 }
2594 __ b(*stub->entry());
2595 __ bind(done);
2596
2597 } else if (code == lir_checkcast) {
2598 Label success, failure;
2599 emit_typecheck_helper(op, &success, /*fallthru*/&failure, &success);
2600 __ b(*op->stub()->entry());
2601 __ align(32, 12);
2602 __ bind(success);
2603 __ mr_if_needed(op->result_opr()->as_register(), op->object()->as_register());
2604 } else if (code == lir_instanceof) {
2605 Register dst = op->result_opr()->as_register();
2606 Label success, failure, done;
2607 emit_typecheck_helper(op, &success, /*fallthru*/&failure, &failure);
2608 __ li(dst, 0);
2609 __ b(done);
2610 __ align(32, 12);
2611 __ bind(success);
2612 __ li(dst, 1);
2613 __ bind(done);
2614 } else {
2615 ShouldNotReachHere();
2616 }
2617 }
2618
2619
2620 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
2621 Register addr = op->addr()->as_pointer_register();
2622 Register cmp_value = noreg, new_value = noreg;
2623 bool is_64bit = false;
2624
2625 if (op->code() == lir_cas_long) {
2626 cmp_value = op->cmp_value()->as_register_lo();
2627 new_value = op->new_value()->as_register_lo();
2628 is_64bit = true;
2629 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj) {
2630 cmp_value = op->cmp_value()->as_register();
2631 new_value = op->new_value()->as_register();
2632 if (op->code() == lir_cas_obj) {
2633 if (UseCompressedOops) {
2634 Register t1 = op->tmp1()->as_register();
2635 Register t2 = op->tmp2()->as_register();
2636 cmp_value = __ encode_heap_oop(t1, cmp_value);
2637 new_value = __ encode_heap_oop(t2, new_value);
2638 } else {
2639 is_64bit = true;
2640 }
2641 }
2642 } else {
2643 Unimplemented();
2644 }
2645
2646 if (is_64bit) {
2647 __ cmpxchgd(BOOL_RESULT, /*current_value=*/R0, cmp_value, new_value, addr,
2648 MacroAssembler::MemBarNone,
2649 MacroAssembler::cmpxchgx_hint_atomic_update(),
2650 noreg, NULL, /*check without ldarx first*/true);
2651 } else {
2652 __ cmpxchgw(BOOL_RESULT, /*current_value=*/R0, cmp_value, new_value, addr,
2653 MacroAssembler::MemBarNone,
2654 MacroAssembler::cmpxchgx_hint_atomic_update(),
2655 noreg, /*check without ldarx first*/true);
2656 }
2657
2658 if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
2659 __ isync();
2660 } else {
2661 __ sync();
2662 }
2663 }
2664
2665 void LIR_Assembler::breakpoint() {
2666 __ illtrap();
2667 }
2668
2669
2670 void LIR_Assembler::push(LIR_Opr opr) {
2671 Unimplemented();
2672 }
2673
2674 void LIR_Assembler::pop(LIR_Opr opr) {
2675 Unimplemented();
2676 }
2677
2678
2679 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst_opr) {
2680 Address mon_addr = frame_map()->address_for_monitor_lock(monitor_no);
2681 Register dst = dst_opr->as_register();
2682 Register reg = mon_addr.base();
2683 int offset = mon_addr.disp();
2684 // Compute pointer to BasicLock.
2685 __ add_const_optimized(dst, reg, offset);
2686 }
2687
2688
2689 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
2690 Register obj = op->obj_opr()->as_register();
2691 Register hdr = op->hdr_opr()->as_register();
2692 Register lock = op->lock_opr()->as_register();
2693
2694 // Obj may not be an oop.
2695 if (op->code() == lir_lock) {
2696 MonitorEnterStub* stub = (MonitorEnterStub*)op->stub();
2697 if (!UseHeavyMonitors) {
2698 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2699 // Add debug info for NullPointerException only if one is possible.
2700 if (op->info() != NULL) {
2701 if (!os::zero_page_read_protected() || !ImplicitNullChecks) {
2702 explicit_null_check(obj, op->info());
2703 } else {
2704 add_debug_info_for_null_check_here(op->info());
2705 }
2706 }
2707 __ lock_object(hdr, obj, lock, op->scratch_opr()->as_register(), *op->stub()->entry());
2708 } else {
2709 // always do slow locking
2710 // note: The slow locking code could be inlined here, however if we use
2711 // slow locking, speed doesn't matter anyway and this solution is
2712 // simpler and requires less duplicated code - additionally, the
2713 // slow locking code is the same in either case which simplifies
2714 // debugging.
2715 if (op->info() != NULL) {
2716 add_debug_info_for_null_check_here(op->info());
2717 __ null_check(obj);
2718 }
2719 __ b(*op->stub()->entry());
2720 }
2721 } else {
2722 assert (op->code() == lir_unlock, "Invalid code, expected lir_unlock");
2723 if (!UseHeavyMonitors) {
2724 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2725 __ unlock_object(hdr, obj, lock, *op->stub()->entry());
2726 } else {
2727 // always do slow unlocking
2728 // note: The slow unlocking code could be inlined here, however if we use
2729 // slow unlocking, speed doesn't matter anyway and this solution is
2730 // simpler and requires less duplicated code - additionally, the
2731 // slow unlocking code is the same in either case which simplifies
2732 // debugging.
2733 __ b(*op->stub()->entry());
2734 }
2735 }
2736 __ bind(*op->stub()->continuation());
2737 }
2738
2739 void LIR_Assembler::emit_load_klass(LIR_OpLoadKlass* op) {
2740 Register obj = op->obj()->as_pointer_register();
2741 Register result = op->result_opr()->as_pointer_register();
2742
2743 CodeEmitInfo* info = op->info();
2744 if (info != NULL) {
2745 if (!os::zero_page_read_protected() || !ImplicitNullChecks) {
2746 explicit_null_check(obj, info);
2747 } else {
2748 add_debug_info_for_null_check_here(info);
2749 }
2750 }
2751
2752 if (UseCompressedClassPointers) {
2753 __ lwz(result, oopDesc::klass_offset_in_bytes(), obj);
2754 __ decode_klass_not_null(result);
2755 } else {
2756 __ ld(result, oopDesc::klass_offset_in_bytes(), obj);
2757 }
2758 }
2759
2760 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
2761 ciMethod* method = op->profiled_method();
2762 int bci = op->profiled_bci();
2763 ciMethod* callee = op->profiled_callee();
2764
2765 // Update counter for all call types.
2766 ciMethodData* md = method->method_data_or_null();
2767 assert(md != NULL, "Sanity");
2768 ciProfileData* data = md->bci_to_data(bci);
2769 assert(data != NULL && data->is_CounterData(), "need CounterData for calls");
2770 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
2771 Register mdo = op->mdo()->as_register();
2772 #ifdef _LP64
2773 assert(op->tmp1()->is_double_cpu(), "tmp1 must be allocated");
2774 Register tmp1 = op->tmp1()->as_register_lo();
2775 #else
2776 assert(op->tmp1()->is_single_cpu(), "tmp1 must be allocated");
2777 Register tmp1 = op->tmp1()->as_register();
2778 #endif
2779 metadata2reg(md->constant_encoding(), mdo);
2780 int mdo_offset_bias = 0;
2781 if (!Assembler::is_simm16(md->byte_offset_of_slot(data, CounterData::count_offset()) +
2782 data->size_in_bytes())) {
2783 // The offset is large so bias the mdo by the base of the slot so
2784 // that the ld can use simm16s to reference the slots of the data.
2785 mdo_offset_bias = md->byte_offset_of_slot(data, CounterData::count_offset());
2786 __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2787 }
2788
2789 // Perform additional virtual call profiling for invokevirtual and
2790 // invokeinterface bytecodes
2791 if (op->should_profile_receiver_type()) {
2792 assert(op->recv()->is_single_cpu(), "recv must be allocated");
2793 Register recv = op->recv()->as_register();
2794 assert_different_registers(mdo, tmp1, recv);
2795 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
2796 ciKlass* known_klass = op->known_holder();
2797 if (C1OptimizeVirtualCallProfiling && known_klass != NULL) {
2798 // We know the type that will be seen at this call site; we can
2799 // statically update the MethodData* rather than needing to do
2800 // dynamic tests on the receiver type.
2801
2802 // NOTE: we should probably put a lock around this search to
2803 // avoid collisions by concurrent compilations.
2804 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
2805 uint i;
2806 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2807 ciKlass* receiver = vc_data->receiver(i);
2808 if (known_klass->equals(receiver)) {
2809 __ ld(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2810 __ addi(tmp1, tmp1, DataLayout::counter_increment);
2811 __ std(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2812 return;
2813 }
2814 }
2815
2816 // Receiver type not found in profile data; select an empty slot.
2817
2818 // Note that this is less efficient than it should be because it
2819 // always does a write to the receiver part of the
2820 // VirtualCallData rather than just the first time.
2821 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2822 ciKlass* receiver = vc_data->receiver(i);
2823 if (receiver == NULL) {
2824 metadata2reg(known_klass->constant_encoding(), tmp1);
2825 __ std(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)) - mdo_offset_bias, mdo);
2826
2827 __ ld(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2828 __ addi(tmp1, tmp1, DataLayout::counter_increment);
2829 __ std(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2830 return;
2831 }
2832 }
2833 } else {
2834 __ load_klass(recv, recv);
2835 Label update_done;
2836 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, &update_done);
2837 // Receiver did not match any saved receiver and there is no empty row for it.
2838 // Increment total counter to indicate polymorphic case.
2839 __ ld(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2840 __ addi(tmp1, tmp1, DataLayout::counter_increment);
2841 __ std(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2842
2843 __ bind(update_done);
2844 }
2845 } else {
2846 // Static call
2847 __ ld(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2848 __ addi(tmp1, tmp1, DataLayout::counter_increment);
2849 __ std(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2850 }
2851 }
2852
2853
2854 void LIR_Assembler::align_backward_branch_target() {
2855 __ align(32, 12); // Insert up to 3 nops to align with 32 byte boundary.
2856 }
2857
2858
2859 void LIR_Assembler::emit_delay(LIR_OpDelay* op) {
2860 Unimplemented();
2861 }
2862
2863
2864 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) {
2865 // tmp must be unused
2866 assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2867 assert(left->is_register(), "can only handle registers");
2868
2869 if (left->is_single_cpu()) {
2870 __ neg(dest->as_register(), left->as_register());
2871 } else if (left->is_single_fpu()) {
2872 __ fneg(dest->as_float_reg(), left->as_float_reg());
2873 } else if (left->is_double_fpu()) {
2874 __ fneg(dest->as_double_reg(), left->as_double_reg());
2875 } else {
2876 assert (left->is_double_cpu(), "Must be a long");
2877 __ neg(dest->as_register_lo(), left->as_register_lo());
2878 }
2879 }
2880
2881
2882 void LIR_Assembler::rt_call(LIR_Opr result, address dest,
2883 const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
2884 // Stubs: Called via rt_call, but dest is a stub address (no function descriptor).
2885 if (dest == Runtime1::entry_for(Runtime1::register_finalizer_id) ||
2886 dest == Runtime1::entry_for(Runtime1::new_multi_array_id )) {
2887 //__ load_const_optimized(R0, dest);
2888 __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(dest));
2889 __ mtctr(R0);
2890 __ bctrl();
2891 assert(info != NULL, "sanity");
2892 add_call_info_here(info);
2893 __ post_call_nop();
2894 return;
2895 }
2896
2897 __ call_c_with_frame_resize(dest, /*no resizing*/ 0);
2898 if (info != NULL) {
2899 add_call_info_here(info);
2900 }
2901 __ post_call_nop();
2902 }
2903
2904
2905 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
2906 ShouldNotReachHere(); // Not needed on _LP64.
2907 }
2908
2909 void LIR_Assembler::membar() {
2910 __ fence();
2911 }
2912
2913 void LIR_Assembler::membar_acquire() {
2914 __ acquire();
2915 }
2916
2917 void LIR_Assembler::membar_release() {
2918 __ release();
2919 }
2920
2921 void LIR_Assembler::membar_loadload() {
2922 __ membar(Assembler::LoadLoad);
2923 }
2924
2925 void LIR_Assembler::membar_storestore() {
2926 __ membar(Assembler::StoreStore);
2927 }
2928
2929 void LIR_Assembler::membar_loadstore() {
2930 __ membar(Assembler::LoadStore);
2931 }
2932
2933 void LIR_Assembler::membar_storeload() {
2934 __ membar(Assembler::StoreLoad);
2935 }
2936
2937 void LIR_Assembler::on_spin_wait() {
2938 Unimplemented();
2939 }
2940
2941 void LIR_Assembler::leal(LIR_Opr addr_opr, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
2942 LIR_Address* addr = addr_opr->as_address_ptr();
2943 assert(addr->scale() == LIR_Address::times_1, "no scaling on this platform");
2944
2945 if (addr->index()->is_illegal()) {
2946 if (patch_code != lir_patch_none) {
2947 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::access_field_id);
2948 __ load_const32(R0, 0); // patchable int
2949 __ add(dest->as_pointer_register(), addr->base()->as_pointer_register(), R0);
2950 patching_epilog(patch, patch_code, addr->base()->as_register(), info);
2951 } else {
2952 __ add_const_optimized(dest->as_pointer_register(), addr->base()->as_pointer_register(), addr->disp());
2953 }
2954 } else {
2955 assert(patch_code == lir_patch_none, "Patch code not supported");
2956 assert(addr->disp() == 0, "can't have both: index and disp");
2957 __ add(dest->as_pointer_register(), addr->index()->as_pointer_register(), addr->base()->as_pointer_register());
2958 }
2959 }
2960
2961
2962 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
2963 ShouldNotReachHere();
2964 }
2965
2966
2967 #ifdef ASSERT
2968 // Emit run-time assertion.
2969 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
2970 Unimplemented();
2971 }
2972 #endif
2973
2974
2975 void LIR_Assembler::peephole(LIR_List* lir) {
2976 // Optimize instruction pairs before emitting.
2977 LIR_OpList* inst = lir->instructions_list();
2978 for (int i = 1; i < inst->length(); i++) {
2979 LIR_Op* op = inst->at(i);
2980
2981 // 2 register-register-moves
2982 if (op->code() == lir_move) {
2983 LIR_Opr in2 = ((LIR_Op1*)op)->in_opr(),
2984 res2 = ((LIR_Op1*)op)->result_opr();
2985 if (in2->is_register() && res2->is_register()) {
2986 LIR_Op* prev = inst->at(i - 1);
2987 if (prev && prev->code() == lir_move) {
2988 LIR_Opr in1 = ((LIR_Op1*)prev)->in_opr(),
2989 res1 = ((LIR_Op1*)prev)->result_opr();
2990 if (in1->is_same_register(res2) && in2->is_same_register(res1)) {
2991 inst->remove_at(i);
2992 }
2993 }
2994 }
2995 }
2996
2997 }
2998 return;
2999 }
3000
3001
3002 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) {
3003 const LIR_Address *addr = src->as_address_ptr();
3004 assert(addr->disp() == 0 && addr->index()->is_illegal(), "use leal!");
3005 const Register Rptr = addr->base()->as_pointer_register(),
3006 Rtmp = tmp->as_register();
3007 Register Rco = noreg;
3008 if (UseCompressedOops && data->is_oop()) {
3009 Rco = __ encode_heap_oop(Rtmp, data->as_register());
3010 }
3011
3012 Label Lretry;
3013 __ bind(Lretry);
3014
3015 if (data->type() == T_INT) {
3016 const Register Rold = dest->as_register(),
3017 Rsrc = data->as_register();
3018 assert_different_registers(Rptr, Rtmp, Rold, Rsrc);
3019 __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3020 if (code == lir_xadd) {
3021 __ add(Rtmp, Rsrc, Rold);
3022 __ stwcx_(Rtmp, Rptr);
3023 } else {
3024 __ stwcx_(Rsrc, Rptr);
3025 }
3026 } else if (data->is_oop()) {
3027 assert(code == lir_xchg, "xadd for oops");
3028 const Register Rold = dest->as_register();
3029 if (UseCompressedOops) {
3030 assert_different_registers(Rptr, Rold, Rco);
3031 __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3032 __ stwcx_(Rco, Rptr);
3033 } else {
3034 Register Robj = data->as_register();
3035 assert_different_registers(Rptr, Rold, Rtmp);
3036 assert_different_registers(Rptr, Robj, Rtmp);
3037 if (Robj == Rold) { // May happen with ZGC.
3038 __ mr(Rtmp, Robj);
3039 Robj = Rtmp;
3040 }
3041 __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3042 __ stdcx_(Robj, Rptr);
3043 }
3044 } else if (data->type() == T_LONG) {
3045 const Register Rold = dest->as_register_lo(),
3046 Rsrc = data->as_register_lo();
3047 assert_different_registers(Rptr, Rtmp, Rold, Rsrc);
3048 __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3049 if (code == lir_xadd) {
3050 __ add(Rtmp, Rsrc, Rold);
3051 __ stdcx_(Rtmp, Rptr);
3052 } else {
3053 __ stdcx_(Rsrc, Rptr);
3054 }
3055 } else {
3056 ShouldNotReachHere();
3057 }
3058
3059 if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
3060 __ bne_predict_not_taken(CCR0, Lretry);
3061 } else {
3062 __ bne( CCR0, Lretry);
3063 }
3064
3065 if (UseCompressedOops && data->is_oop()) {
3066 __ decode_heap_oop(dest->as_register());
3067 }
3068 }
3069
3070
3071 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
3072 Register obj = op->obj()->as_register();
3073 Register tmp = op->tmp()->as_pointer_register();
3074 LIR_Address* mdo_addr = op->mdp()->as_address_ptr();
3075 ciKlass* exact_klass = op->exact_klass();
3076 intptr_t current_klass = op->current_klass();
3077 bool not_null = op->not_null();
3078 bool no_conflict = op->no_conflict();
3079
3080 Label Lupdate, Ldo_update, Ldone;
3081
3082 bool do_null = !not_null;
3083 bool exact_klass_set = exact_klass != NULL && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
3084 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
3085
3086 assert(do_null || do_update, "why are we here?");
3087 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
3088
3089 __ verify_oop(obj, FILE_AND_LINE);
3090
3091 if (do_null) {
3092 if (!TypeEntries::was_null_seen(current_klass)) {
3093 __ cmpdi(CCR0, obj, 0);
3094 __ bne(CCR0, Lupdate);
3095 __ ld(R0, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3096 __ ori(R0, R0, TypeEntries::null_seen);
3097 if (do_update) {
3098 __ b(Ldo_update);
3099 } else {
3100 __ std(R0, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3101 }
3102 } else {
3103 if (do_update) {
3104 __ cmpdi(CCR0, obj, 0);
3105 __ beq(CCR0, Ldone);
3106 }
3107 }
3108 #ifdef ASSERT
3109 } else {
3110 __ cmpdi(CCR0, obj, 0);
3111 __ bne(CCR0, Lupdate);
3112 __ stop("unexpected null obj");
3113 #endif
3114 }
3115
3116 __ bind(Lupdate);
3117 if (do_update) {
3118 Label Lnext;
3119 const Register klass = R29_TOC; // kill and reload
3120 bool klass_reg_used = false;
3121 #ifdef ASSERT
3122 if (exact_klass != NULL) {
3123 Label ok;
3124 klass_reg_used = true;
3125 __ load_klass(klass, obj);
3126 metadata2reg(exact_klass->constant_encoding(), R0);
3127 __ cmpd(CCR0, klass, R0);
3128 __ beq(CCR0, ok);
3129 __ stop("exact klass and actual klass differ");
3130 __ bind(ok);
3131 }
3132 #endif
3133
3134 if (!no_conflict) {
3135 if (exact_klass == NULL || TypeEntries::is_type_none(current_klass)) {
3136 klass_reg_used = true;
3137 if (exact_klass != NULL) {
3138 __ ld(tmp, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3139 metadata2reg(exact_klass->constant_encoding(), klass);
3140 } else {
3141 __ load_klass(klass, obj);
3142 __ ld(tmp, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register()); // may kill obj
3143 }
3144
3145 // Like InterpreterMacroAssembler::profile_obj_type
3146 __ clrrdi(R0, tmp, exact_log2(-TypeEntries::type_klass_mask));
3147 // Basically same as andi(R0, tmp, TypeEntries::type_klass_mask);
3148 __ cmpd(CCR1, R0, klass);
3149 // Klass seen before, nothing to do (regardless of unknown bit).
3150 //beq(CCR1, do_nothing);
3151
3152 __ andi_(R0, klass, TypeEntries::type_unknown);
3153 // Already unknown. Nothing to do anymore.
3154 //bne(CCR0, do_nothing);
3155 __ crorc(CCR0, Assembler::equal, CCR1, Assembler::equal); // cr0 eq = cr1 eq or cr0 ne
3156 __ beq(CCR0, Lnext);
3157
3158 if (TypeEntries::is_type_none(current_klass)) {
3159 __ clrrdi_(R0, tmp, exact_log2(-TypeEntries::type_mask));
3160 __ orr(R0, klass, tmp); // Combine klass and null_seen bit (only used if (tmp & type_mask)==0).
3161 __ beq(CCR0, Ldo_update); // First time here. Set profile type.
3162 }
3163
3164 } else {
3165 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
3166 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
3167
3168 __ ld(tmp, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3169 __ andi_(R0, tmp, TypeEntries::type_unknown);
3170 // Already unknown. Nothing to do anymore.
3171 __ bne(CCR0, Lnext);
3172 }
3173
3174 // Different than before. Cannot keep accurate profile.
3175 __ ori(R0, tmp, TypeEntries::type_unknown);
3176 } else {
3177 // There's a single possible klass at this profile point
3178 assert(exact_klass != NULL, "should be");
3179 __ ld(tmp, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3180
3181 if (TypeEntries::is_type_none(current_klass)) {
3182 klass_reg_used = true;
3183 metadata2reg(exact_klass->constant_encoding(), klass);
3184
3185 __ clrrdi(R0, tmp, exact_log2(-TypeEntries::type_klass_mask));
3186 // Basically same as andi(R0, tmp, TypeEntries::type_klass_mask);
3187 __ cmpd(CCR1, R0, klass);
3188 // Klass seen before, nothing to do (regardless of unknown bit).
3189 __ beq(CCR1, Lnext);
3190 #ifdef ASSERT
3191 {
3192 Label ok;
3193 __ clrrdi_(R0, tmp, exact_log2(-TypeEntries::type_mask));
3194 __ beq(CCR0, ok); // First time here.
3195
3196 __ stop("unexpected profiling mismatch");
3197 __ bind(ok);
3198 }
3199 #endif
3200 // First time here. Set profile type.
3201 __ orr(R0, klass, tmp); // Combine klass and null_seen bit (only used if (tmp & type_mask)==0).
3202 } else {
3203 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
3204 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
3205
3206 // Already unknown. Nothing to do anymore.
3207 __ andi_(R0, tmp, TypeEntries::type_unknown);
3208 __ bne(CCR0, Lnext);
3209
3210 // Different than before. Cannot keep accurate profile.
3211 __ ori(R0, tmp, TypeEntries::type_unknown);
3212 }
3213 }
3214
3215 __ bind(Ldo_update);
3216 __ std(R0, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3217
3218 __ bind(Lnext);
3219 if (klass_reg_used) { __ load_const_optimized(R29_TOC, MacroAssembler::global_toc(), R0); } // reinit
3220 }
3221 __ bind(Ldone);
3222 }
3223
3224
3225 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
3226 assert(op->crc()->is_single_cpu(), "crc must be register");
3227 assert(op->val()->is_single_cpu(), "byte value must be register");
3228 assert(op->result_opr()->is_single_cpu(), "result must be register");
3229 Register crc = op->crc()->as_register();
3230 Register val = op->val()->as_register();
3231 Register res = op->result_opr()->as_register();
3232
3233 assert_different_registers(val, crc, res);
3234
3235 __ load_const_optimized(res, StubRoutines::crc_table_addr(), R0);
3236 __ kernel_crc32_singleByteReg(crc, val, res, true);
3237 __ mr(res, crc);
3238 }
3239
3240 #undef __