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src/hotspot/cpu/riscv/macroAssembler_riscv.hpp

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539 
540   // logic
541   void andrw(Register Rd, Register Rs1, Register Rs2);
542   void orrw(Register Rd, Register Rs1, Register Rs2);
543   void xorrw(Register Rd, Register Rs1, Register Rs2);
544 
545   // revb
546   void revb_h_h(Register Rd, Register Rs, Register tmp = t0);                           // reverse bytes in halfword in lower 16 bits, sign-extend
547   void revb_w_w(Register Rd, Register Rs, Register tmp1 = t0, Register tmp2 = t1);      // reverse bytes in lower word, sign-extend
548   void revb_h_h_u(Register Rd, Register Rs, Register tmp = t0);                         // reverse bytes in halfword in lower 16 bits, zero-extend
549   void revb_h_w_u(Register Rd, Register Rs, Register tmp1 = t0, Register tmp2 = t1);    // reverse bytes in halfwords in lower 32 bits, zero-extend
550   void revb_h_helper(Register Rd, Register Rs, Register tmp1 = t0, Register tmp2= t1);  // reverse bytes in upper 16 bits (48:63) and move to lower
551   void revb_h(Register Rd, Register Rs, Register tmp1 = t0, Register tmp2= t1);         // reverse bytes in each halfword
552   void revb_w(Register Rd, Register Rs, Register tmp1 = t0, Register tmp2= t1);         // reverse bytes in each word
553   void revb(Register Rd, Register Rs, Register tmp1 = t0, Register tmp2 = t1);          // reverse bytes in doubleword
554 
555   void ror_imm(Register dst, Register src, uint32_t shift, Register tmp = t0);
556   void andi(Register Rd, Register Rn, int64_t imm, Register tmp = t0);
557   void orptr(Address adr, RegisterOrConstant src, Register tmp1 = t0, Register tmp2 = t1);
558 
559   void cmpxchg_obj_header(Register oldv, Register newv, Register obj, Register tmp, Label &succeed, Label *fail);
560   void cmpxchgptr(Register oldv, Register newv, Register addr, Register tmp, Label &succeed, Label *fail);
561   void cmpxchg(Register addr, Register expected,
562                Register new_val,
563                enum operand_size size,
564                Assembler::Aqrl acquire, Assembler::Aqrl release,
565                Register result, bool result_as_bool = false);
566   void cmpxchg_weak(Register addr, Register expected,
567                     Register new_val,
568                     enum operand_size size,
569                     Assembler::Aqrl acquire, Assembler::Aqrl release,
570                     Register result);
571   void cmpxchg_narrow_value_helper(Register addr, Register expected,
572                                    Register new_val,
573                                    enum operand_size size,
574                                    Register tmp1, Register tmp2, Register tmp3);
575   void cmpxchg_narrow_value(Register addr, Register expected,
576                             Register new_val,
577                             enum operand_size size,
578                             Assembler::Aqrl acquire, Assembler::Aqrl release,
579                             Register result, bool result_as_bool,

911   bool is_valid_riscv64_address(address addr) {
912     // sv48: must have bits 63–48 all equal to bit 47
913     return ((uintptr_t)addr >> 47) == 0;
914   }
915 
916   void ld_constant(Register dest, const Address &const_addr) {
917     if (NearCpool) {
918       ld(dest, const_addr);
919     } else {
920       int32_t offset = 0;
921       la_patchable(dest, InternalAddress(const_addr.target()), offset);
922       ld(dest, Address(dest, offset));
923     }
924   }
925 
926   int bitset_to_regs(unsigned int bitset, unsigned char* regs);
927   Address add_memory_helper(const Address dst);
928 
929   void load_reserved(Register addr, enum operand_size size, Assembler::Aqrl acquire);
930   void store_conditional(Register addr, Register new_val, enum operand_size size, Assembler::Aqrl release);




931 };
932 
933 #ifdef ASSERT
934 inline bool AbstractAssembler::pd_check_instruction_mark() { return false; }
935 #endif
936 
937 /**
938  * class SkipIfEqual:
939  *
940  * Instantiating this class will result in assembly code being output that will
941  * jump around any code emitted between the creation of the instance and it's
942  * automatic destruction at the end of a scope block, depending on the value of
943  * the flag passed to the constructor, which will be checked at run-time.
944  */
945 class SkipIfEqual {
946  private:
947   MacroAssembler* _masm;
948   Label _label;
949 
950  public:

539 
540   // logic
541   void andrw(Register Rd, Register Rs1, Register Rs2);
542   void orrw(Register Rd, Register Rs1, Register Rs2);
543   void xorrw(Register Rd, Register Rs1, Register Rs2);
544 
545   // revb
546   void revb_h_h(Register Rd, Register Rs, Register tmp = t0);                           // reverse bytes in halfword in lower 16 bits, sign-extend
547   void revb_w_w(Register Rd, Register Rs, Register tmp1 = t0, Register tmp2 = t1);      // reverse bytes in lower word, sign-extend
548   void revb_h_h_u(Register Rd, Register Rs, Register tmp = t0);                         // reverse bytes in halfword in lower 16 bits, zero-extend
549   void revb_h_w_u(Register Rd, Register Rs, Register tmp1 = t0, Register tmp2 = t1);    // reverse bytes in halfwords in lower 32 bits, zero-extend
550   void revb_h_helper(Register Rd, Register Rs, Register tmp1 = t0, Register tmp2= t1);  // reverse bytes in upper 16 bits (48:63) and move to lower
551   void revb_h(Register Rd, Register Rs, Register tmp1 = t0, Register tmp2= t1);         // reverse bytes in each halfword
552   void revb_w(Register Rd, Register Rs, Register tmp1 = t0, Register tmp2= t1);         // reverse bytes in each word
553   void revb(Register Rd, Register Rs, Register tmp1 = t0, Register tmp2 = t1);          // reverse bytes in doubleword
554 
555   void ror_imm(Register dst, Register src, uint32_t shift, Register tmp = t0);
556   void andi(Register Rd, Register Rn, int64_t imm, Register tmp = t0);
557   void orptr(Address adr, RegisterOrConstant src, Register tmp1 = t0, Register tmp2 = t1);
558 

559   void cmpxchgptr(Register oldv, Register newv, Register addr, Register tmp, Label &succeed, Label *fail);
560   void cmpxchg(Register addr, Register expected,
561                Register new_val,
562                enum operand_size size,
563                Assembler::Aqrl acquire, Assembler::Aqrl release,
564                Register result, bool result_as_bool = false);
565   void cmpxchg_weak(Register addr, Register expected,
566                     Register new_val,
567                     enum operand_size size,
568                     Assembler::Aqrl acquire, Assembler::Aqrl release,
569                     Register result);
570   void cmpxchg_narrow_value_helper(Register addr, Register expected,
571                                    Register new_val,
572                                    enum operand_size size,
573                                    Register tmp1, Register tmp2, Register tmp3);
574   void cmpxchg_narrow_value(Register addr, Register expected,
575                             Register new_val,
576                             enum operand_size size,
577                             Assembler::Aqrl acquire, Assembler::Aqrl release,
578                             Register result, bool result_as_bool,

910   bool is_valid_riscv64_address(address addr) {
911     // sv48: must have bits 63–48 all equal to bit 47
912     return ((uintptr_t)addr >> 47) == 0;
913   }
914 
915   void ld_constant(Register dest, const Address &const_addr) {
916     if (NearCpool) {
917       ld(dest, const_addr);
918     } else {
919       int32_t offset = 0;
920       la_patchable(dest, InternalAddress(const_addr.target()), offset);
921       ld(dest, Address(dest, offset));
922     }
923   }
924 
925   int bitset_to_regs(unsigned int bitset, unsigned char* regs);
926   Address add_memory_helper(const Address dst);
927 
928   void load_reserved(Register addr, enum operand_size size, Assembler::Aqrl acquire);
929   void store_conditional(Register addr, Register new_val, enum operand_size size, Assembler::Aqrl release);
930 
931 public:
932   void fast_lock(Register obj, Register hdr, Register tmp1, Register tmp2, Register tmp3, Label& slow);
933   void fast_unlock(Register obj, Register hdr, Register tmp1, Register tmp2, Label& slow);
934 };
935 
936 #ifdef ASSERT
937 inline bool AbstractAssembler::pd_check_instruction_mark() { return false; }
938 #endif
939 
940 /**
941  * class SkipIfEqual:
942  *
943  * Instantiating this class will result in assembly code being output that will
944  * jump around any code emitted between the creation of the instance and it's
945  * automatic destruction at the end of a scope block, depending on the value of
946  * the flag passed to the constructor, which will be checked at run-time.
947  */
948 class SkipIfEqual {
949  private:
950   MacroAssembler* _masm;
951   Label _label;
952 
953  public:
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