1 //
    2 // Copyright (c) 2003, 2023, Oracle and/or its affiliates. All rights reserved.
    3 // Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
    4 // Copyright (c) 2020, 2023, Huawei Technologies Co., Ltd. All rights reserved.
    5 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
    6 //
    7 // This code is free software; you can redistribute it and/or modify it
    8 // under the terms of the GNU General Public License version 2 only, as
    9 // published by the Free Software Foundation.
   10 //
   11 // This code is distributed in the hope that it will be useful, but WITHOUT
   12 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
   13 // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
   14 // version 2 for more details (a copy is included in the LICENSE file that
   15 // accompanied this code).
   16 //
   17 // You should have received a copy of the GNU General Public License version
   18 // 2 along with this work; if not, write to the Free Software Foundation,
   19 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
   20 //
   21 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
   22 // or visit www.oracle.com if you need additional information or have any
   23 // questions.
   24 //
   25 //
   26 
   27 // RISCV Architecture Description File
   28 
   29 //----------REGISTER DEFINITION BLOCK------------------------------------------
   30 // This information is used by the matcher and the register allocator to
   31 // describe individual registers and classes of registers within the target
   32 // architecture.
   33 
   34 register %{
   35 //----------Architecture Description Register Definitions----------------------
   36 // General Registers
   37 // "reg_def"  name ( register save type, C convention save type,
   38 //                   ideal register type, encoding );
   39 // Register Save Types:
   40 //
   41 // NS  = No-Save:       The register allocator assumes that these registers
   42 //                      can be used without saving upon entry to the method, &
   43 //                      that they do not need to be saved at call sites.
   44 //
   45 // SOC = Save-On-Call:  The register allocator assumes that these registers
   46 //                      can be used without saving upon entry to the method,
   47 //                      but that they must be saved at call sites.
   48 //
   49 // SOE = Save-On-Entry: The register allocator assumes that these registers
   50 //                      must be saved before using them upon entry to the
   51 //                      method, but they do not need to be saved at call
   52 //                      sites.
   53 //
   54 // AS  = Always-Save:   The register allocator assumes that these registers
   55 //                      must be saved before using them upon entry to the
   56 //                      method, & that they must be saved at call sites.
   57 //
   58 // Ideal Register Type is used to determine how to save & restore a
   59 // register.  Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
   60 // spilled with LoadP/StoreP.  If the register supports both, use Op_RegI.
   61 //
   62 // The encoding number is the actual bit-pattern placed into the opcodes.
   63 
   64 // We must define the 64 bit int registers in two 32 bit halves, the
   65 // real lower register and a virtual upper half register. upper halves
   66 // are used by the register allocator but are not actually supplied as
   67 // operands to memory ops.
   68 //
   69 // follow the C1 compiler in making registers
   70 //
   71 //   x7, x9-x17, x27-x31 volatile (caller save)
   72 //   x0-x4, x8, x23 system (no save, no allocate)
   73 //   x5-x6 non-allocatable (so we can use them as temporary regs)
   74 
   75 //
   76 // as regards Java usage. we don't use any callee save registers
   77 // because this makes it difficult to de-optimise a frame (see comment
   78 // in x86 implementation of Deoptimization::unwind_callee_save_values)
   79 //
   80 
   81 // General Registers
   82 
   83 reg_def R0      ( NS,  NS,  Op_RegI, 0,  x0->as_VMReg()         ); // zr
   84 reg_def R0_H    ( NS,  NS,  Op_RegI, 0,  x0->as_VMReg()->next() );
   85 reg_def R1      ( NS,  SOC, Op_RegI, 1,  x1->as_VMReg()         ); // ra
   86 reg_def R1_H    ( NS,  SOC, Op_RegI, 1,  x1->as_VMReg()->next() );
   87 reg_def R2      ( NS,  SOE, Op_RegI, 2,  x2->as_VMReg()         ); // sp
   88 reg_def R2_H    ( NS,  SOE, Op_RegI, 2,  x2->as_VMReg()->next() );
   89 reg_def R3      ( NS,  NS,  Op_RegI, 3,  x3->as_VMReg()         ); // gp
   90 reg_def R3_H    ( NS,  NS,  Op_RegI, 3,  x3->as_VMReg()->next() );
   91 reg_def R4      ( NS,  NS,  Op_RegI, 4,  x4->as_VMReg()         ); // tp
   92 reg_def R4_H    ( NS,  NS,  Op_RegI, 4,  x4->as_VMReg()->next() );
   93 reg_def R7      ( SOC, SOC, Op_RegI, 7,  x7->as_VMReg()         );
   94 reg_def R7_H    ( SOC, SOC, Op_RegI, 7,  x7->as_VMReg()->next() );
   95 reg_def R8      ( NS,  SOE, Op_RegI, 8,  x8->as_VMReg()         ); // fp
   96 reg_def R8_H    ( NS,  SOE, Op_RegI, 8,  x8->as_VMReg()->next() );
   97 reg_def R9      ( SOC, SOE, Op_RegI, 9,  x9->as_VMReg()         );
   98 reg_def R9_H    ( SOC, SOE, Op_RegI, 9,  x9->as_VMReg()->next() );
   99 reg_def R10     ( SOC, SOC, Op_RegI, 10, x10->as_VMReg()        );
  100 reg_def R10_H   ( SOC, SOC, Op_RegI, 10, x10->as_VMReg()->next());
  101 reg_def R11     ( SOC, SOC, Op_RegI, 11, x11->as_VMReg()        );
  102 reg_def R11_H   ( SOC, SOC, Op_RegI, 11, x11->as_VMReg()->next());
  103 reg_def R12     ( SOC, SOC, Op_RegI, 12, x12->as_VMReg()        );
  104 reg_def R12_H   ( SOC, SOC, Op_RegI, 12, x12->as_VMReg()->next());
  105 reg_def R13     ( SOC, SOC, Op_RegI, 13, x13->as_VMReg()        );
  106 reg_def R13_H   ( SOC, SOC, Op_RegI, 13, x13->as_VMReg()->next());
  107 reg_def R14     ( SOC, SOC, Op_RegI, 14, x14->as_VMReg()        );
  108 reg_def R14_H   ( SOC, SOC, Op_RegI, 14, x14->as_VMReg()->next());
  109 reg_def R15     ( SOC, SOC, Op_RegI, 15, x15->as_VMReg()        );
  110 reg_def R15_H   ( SOC, SOC, Op_RegI, 15, x15->as_VMReg()->next());
  111 reg_def R16     ( SOC, SOC, Op_RegI, 16, x16->as_VMReg()        );
  112 reg_def R16_H   ( SOC, SOC, Op_RegI, 16, x16->as_VMReg()->next());
  113 reg_def R17     ( SOC, SOC, Op_RegI, 17, x17->as_VMReg()        );
  114 reg_def R17_H   ( SOC, SOC, Op_RegI, 17, x17->as_VMReg()->next());
  115 reg_def R18     ( SOC, SOE, Op_RegI, 18, x18->as_VMReg()        );
  116 reg_def R18_H   ( SOC, SOE, Op_RegI, 18, x18->as_VMReg()->next());
  117 reg_def R19     ( SOC, SOE, Op_RegI, 19, x19->as_VMReg()        );
  118 reg_def R19_H   ( SOC, SOE, Op_RegI, 19, x19->as_VMReg()->next());
  119 reg_def R20     ( SOC, SOE, Op_RegI, 20, x20->as_VMReg()        ); // caller esp
  120 reg_def R20_H   ( SOC, SOE, Op_RegI, 20, x20->as_VMReg()->next());
  121 reg_def R21     ( SOC, SOE, Op_RegI, 21, x21->as_VMReg()        );
  122 reg_def R21_H   ( SOC, SOE, Op_RegI, 21, x21->as_VMReg()->next());
  123 reg_def R22     ( SOC, SOE, Op_RegI, 22, x22->as_VMReg()        );
  124 reg_def R22_H   ( SOC, SOE, Op_RegI, 22, x22->as_VMReg()->next());
  125 reg_def R23     ( NS,  SOE, Op_RegI, 23, x23->as_VMReg()        ); // java thread
  126 reg_def R23_H   ( NS,  SOE, Op_RegI, 23, x23->as_VMReg()->next());
  127 reg_def R24     ( SOC, SOE, Op_RegI, 24, x24->as_VMReg()        );
  128 reg_def R24_H   ( SOC, SOE, Op_RegI, 24, x24->as_VMReg()->next());
  129 reg_def R25     ( SOC, SOE, Op_RegI, 25, x25->as_VMReg()        );
  130 reg_def R25_H   ( SOC, SOE, Op_RegI, 25, x25->as_VMReg()->next());
  131 reg_def R26     ( SOC, SOE, Op_RegI, 26, x26->as_VMReg()        );
  132 reg_def R26_H   ( SOC, SOE, Op_RegI, 26, x26->as_VMReg()->next());
  133 reg_def R27     ( SOC, SOE, Op_RegI, 27, x27->as_VMReg()        ); // heapbase
  134 reg_def R27_H   ( SOC, SOE, Op_RegI, 27, x27->as_VMReg()->next());
  135 reg_def R28     ( SOC, SOC, Op_RegI, 28, x28->as_VMReg()        );
  136 reg_def R28_H   ( SOC, SOC, Op_RegI, 28, x28->as_VMReg()->next());
  137 reg_def R29     ( SOC, SOC, Op_RegI, 29, x29->as_VMReg()        );
  138 reg_def R29_H   ( SOC, SOC, Op_RegI, 29, x29->as_VMReg()->next());
  139 reg_def R30     ( SOC, SOC, Op_RegI, 30, x30->as_VMReg()        );
  140 reg_def R30_H   ( SOC, SOC, Op_RegI, 30, x30->as_VMReg()->next());
  141 reg_def R31     ( SOC, SOC, Op_RegI, 31, x31->as_VMReg()        );
  142 reg_def R31_H   ( SOC, SOC, Op_RegI, 31, x31->as_VMReg()->next());
  143 
  144 // ----------------------------
  145 // Float/Double Registers
  146 // ----------------------------
  147 
  148 // Double Registers
  149 
  150 // The rules of ADL require that double registers be defined in pairs.
  151 // Each pair must be two 32-bit values, but not necessarily a pair of
  152 // single float registers. In each pair, ADLC-assigned register numbers
  153 // must be adjacent, with the lower number even. Finally, when the
  154 // CPU stores such a register pair to memory, the word associated with
  155 // the lower ADLC-assigned number must be stored to the lower address.
  156 
  157 // RISCV has 32 floating-point registers. Each can store a single
  158 // or double precision floating-point value.
  159 
  160 // for Java use float registers f0-f31 are always save on call whereas
  161 // the platform ABI treats f8-f9 and f18-f27 as callee save). Other
  162 // float registers are SOC as per the platform spec
  163 
  164 reg_def F0    ( SOC, SOC, Op_RegF,  0,  f0->as_VMReg()          );
  165 reg_def F0_H  ( SOC, SOC, Op_RegF,  0,  f0->as_VMReg()->next()  );
  166 reg_def F1    ( SOC, SOC, Op_RegF,  1,  f1->as_VMReg()          );
  167 reg_def F1_H  ( SOC, SOC, Op_RegF,  1,  f1->as_VMReg()->next()  );
  168 reg_def F2    ( SOC, SOC, Op_RegF,  2,  f2->as_VMReg()          );
  169 reg_def F2_H  ( SOC, SOC, Op_RegF,  2,  f2->as_VMReg()->next()  );
  170 reg_def F3    ( SOC, SOC, Op_RegF,  3,  f3->as_VMReg()          );
  171 reg_def F3_H  ( SOC, SOC, Op_RegF,  3,  f3->as_VMReg()->next()  );
  172 reg_def F4    ( SOC, SOC, Op_RegF,  4,  f4->as_VMReg()          );
  173 reg_def F4_H  ( SOC, SOC, Op_RegF,  4,  f4->as_VMReg()->next()  );
  174 reg_def F5    ( SOC, SOC, Op_RegF,  5,  f5->as_VMReg()          );
  175 reg_def F5_H  ( SOC, SOC, Op_RegF,  5,  f5->as_VMReg()->next()  );
  176 reg_def F6    ( SOC, SOC, Op_RegF,  6,  f6->as_VMReg()          );
  177 reg_def F6_H  ( SOC, SOC, Op_RegF,  6,  f6->as_VMReg()->next()  );
  178 reg_def F7    ( SOC, SOC, Op_RegF,  7,  f7->as_VMReg()          );
  179 reg_def F7_H  ( SOC, SOC, Op_RegF,  7,  f7->as_VMReg()->next()  );
  180 reg_def F8    ( SOC, SOE, Op_RegF,  8,  f8->as_VMReg()          );
  181 reg_def F8_H  ( SOC, SOE, Op_RegF,  8,  f8->as_VMReg()->next()  );
  182 reg_def F9    ( SOC, SOE, Op_RegF,  9,  f9->as_VMReg()          );
  183 reg_def F9_H  ( SOC, SOE, Op_RegF,  9,  f9->as_VMReg()->next()  );
  184 reg_def F10   ( SOC, SOC, Op_RegF,  10, f10->as_VMReg()         );
  185 reg_def F10_H ( SOC, SOC, Op_RegF,  10, f10->as_VMReg()->next() );
  186 reg_def F11   ( SOC, SOC, Op_RegF,  11, f11->as_VMReg()         );
  187 reg_def F11_H ( SOC, SOC, Op_RegF,  11, f11->as_VMReg()->next() );
  188 reg_def F12   ( SOC, SOC, Op_RegF,  12, f12->as_VMReg()         );
  189 reg_def F12_H ( SOC, SOC, Op_RegF,  12, f12->as_VMReg()->next() );
  190 reg_def F13   ( SOC, SOC, Op_RegF,  13, f13->as_VMReg()         );
  191 reg_def F13_H ( SOC, SOC, Op_RegF,  13, f13->as_VMReg()->next() );
  192 reg_def F14   ( SOC, SOC, Op_RegF,  14, f14->as_VMReg()         );
  193 reg_def F14_H ( SOC, SOC, Op_RegF,  14, f14->as_VMReg()->next() );
  194 reg_def F15   ( SOC, SOC, Op_RegF,  15, f15->as_VMReg()         );
  195 reg_def F15_H ( SOC, SOC, Op_RegF,  15, f15->as_VMReg()->next() );
  196 reg_def F16   ( SOC, SOC, Op_RegF,  16, f16->as_VMReg()         );
  197 reg_def F16_H ( SOC, SOC, Op_RegF,  16, f16->as_VMReg()->next() );
  198 reg_def F17   ( SOC, SOC, Op_RegF,  17, f17->as_VMReg()         );
  199 reg_def F17_H ( SOC, SOC, Op_RegF,  17, f17->as_VMReg()->next() );
  200 reg_def F18   ( SOC, SOE, Op_RegF,  18, f18->as_VMReg()         );
  201 reg_def F18_H ( SOC, SOE, Op_RegF,  18, f18->as_VMReg()->next() );
  202 reg_def F19   ( SOC, SOE, Op_RegF,  19, f19->as_VMReg()         );
  203 reg_def F19_H ( SOC, SOE, Op_RegF,  19, f19->as_VMReg()->next() );
  204 reg_def F20   ( SOC, SOE, Op_RegF,  20, f20->as_VMReg()         );
  205 reg_def F20_H ( SOC, SOE, Op_RegF,  20, f20->as_VMReg()->next() );
  206 reg_def F21   ( SOC, SOE, Op_RegF,  21, f21->as_VMReg()         );
  207 reg_def F21_H ( SOC, SOE, Op_RegF,  21, f21->as_VMReg()->next() );
  208 reg_def F22   ( SOC, SOE, Op_RegF,  22, f22->as_VMReg()         );
  209 reg_def F22_H ( SOC, SOE, Op_RegF,  22, f22->as_VMReg()->next() );
  210 reg_def F23   ( SOC, SOE, Op_RegF,  23, f23->as_VMReg()         );
  211 reg_def F23_H ( SOC, SOE, Op_RegF,  23, f23->as_VMReg()->next() );
  212 reg_def F24   ( SOC, SOE, Op_RegF,  24, f24->as_VMReg()         );
  213 reg_def F24_H ( SOC, SOE, Op_RegF,  24, f24->as_VMReg()->next() );
  214 reg_def F25   ( SOC, SOE, Op_RegF,  25, f25->as_VMReg()         );
  215 reg_def F25_H ( SOC, SOE, Op_RegF,  25, f25->as_VMReg()->next() );
  216 reg_def F26   ( SOC, SOE, Op_RegF,  26, f26->as_VMReg()         );
  217 reg_def F26_H ( SOC, SOE, Op_RegF,  26, f26->as_VMReg()->next() );
  218 reg_def F27   ( SOC, SOE, Op_RegF,  27, f27->as_VMReg()         );
  219 reg_def F27_H ( SOC, SOE, Op_RegF,  27, f27->as_VMReg()->next() );
  220 reg_def F28   ( SOC, SOC, Op_RegF,  28, f28->as_VMReg()         );
  221 reg_def F28_H ( SOC, SOC, Op_RegF,  28, f28->as_VMReg()->next() );
  222 reg_def F29   ( SOC, SOC, Op_RegF,  29, f29->as_VMReg()         );
  223 reg_def F29_H ( SOC, SOC, Op_RegF,  29, f29->as_VMReg()->next() );
  224 reg_def F30   ( SOC, SOC, Op_RegF,  30, f30->as_VMReg()         );
  225 reg_def F30_H ( SOC, SOC, Op_RegF,  30, f30->as_VMReg()->next() );
  226 reg_def F31   ( SOC, SOC, Op_RegF,  31, f31->as_VMReg()         );
  227 reg_def F31_H ( SOC, SOC, Op_RegF,  31, f31->as_VMReg()->next() );
  228 
  229 // ----------------------------
  230 // Vector Registers
  231 // ----------------------------
  232 
  233 // For RVV vector registers, we simply extend vector register size to 4
  234 // 'logical' slots. This is nominally 128 bits but it actually covers
  235 // all possible 'physical' RVV vector register lengths from 128 ~ 1024
  236 // bits. The 'physical' RVV vector register length is detected during
  237 // startup, so the register allocator is able to identify the correct
  238 // number of bytes needed for an RVV spill/unspill.
  239 
  240 reg_def V0    ( SOC, SOC, Op_VecA, 0,  v0->as_VMReg()           );
  241 reg_def V0_H  ( SOC, SOC, Op_VecA, 0,  v0->as_VMReg()->next()   );
  242 reg_def V0_J  ( SOC, SOC, Op_VecA, 0,  v0->as_VMReg()->next(2)  );
  243 reg_def V0_K  ( SOC, SOC, Op_VecA, 0,  v0->as_VMReg()->next(3)  );
  244 
  245 reg_def V1    ( SOC, SOC, Op_VecA, 1,  v1->as_VMReg() 	        );
  246 reg_def V1_H  ( SOC, SOC, Op_VecA, 1,  v1->as_VMReg()->next()   );
  247 reg_def V1_J  ( SOC, SOC, Op_VecA, 1,  v1->as_VMReg()->next(2)  );
  248 reg_def V1_K  ( SOC, SOC, Op_VecA, 1,  v1->as_VMReg()->next(3)  );
  249 
  250 reg_def V2    ( SOC, SOC, Op_VecA, 2,  v2->as_VMReg()           );
  251 reg_def V2_H  ( SOC, SOC, Op_VecA, 2,  v2->as_VMReg()->next()   );
  252 reg_def V2_J  ( SOC, SOC, Op_VecA, 2,  v2->as_VMReg()->next(2)  );
  253 reg_def V2_K  ( SOC, SOC, Op_VecA, 2,  v2->as_VMReg()->next(3)  );
  254 
  255 reg_def V3    ( SOC, SOC, Op_VecA, 3,  v3->as_VMReg()           );
  256 reg_def V3_H  ( SOC, SOC, Op_VecA, 3,  v3->as_VMReg()->next()   );
  257 reg_def V3_J  ( SOC, SOC, Op_VecA, 3,  v3->as_VMReg()->next(2)  );
  258 reg_def V3_K  ( SOC, SOC, Op_VecA, 3,  v3->as_VMReg()->next(3)  );
  259 
  260 reg_def V4    ( SOC, SOC, Op_VecA, 4,  v4->as_VMReg()           );
  261 reg_def V4_H  ( SOC, SOC, Op_VecA, 4,  v4->as_VMReg()->next()   );
  262 reg_def V4_J  ( SOC, SOC, Op_VecA, 4,  v4->as_VMReg()->next(2)  );
  263 reg_def V4_K  ( SOC, SOC, Op_VecA, 4,  v4->as_VMReg()->next(3)  );
  264 
  265 reg_def V5    ( SOC, SOC, Op_VecA, 5,  v5->as_VMReg() 	        );
  266 reg_def V5_H  ( SOC, SOC, Op_VecA, 5,  v5->as_VMReg()->next()   );
  267 reg_def V5_J  ( SOC, SOC, Op_VecA, 5,  v5->as_VMReg()->next(2)  );
  268 reg_def V5_K  ( SOC, SOC, Op_VecA, 5,  v5->as_VMReg()->next(3)  );
  269 
  270 reg_def V6    ( SOC, SOC, Op_VecA, 6,  v6->as_VMReg()           );
  271 reg_def V6_H  ( SOC, SOC, Op_VecA, 6,  v6->as_VMReg()->next()   );
  272 reg_def V6_J  ( SOC, SOC, Op_VecA, 6,  v6->as_VMReg()->next(2)  );
  273 reg_def V6_K  ( SOC, SOC, Op_VecA, 6,  v6->as_VMReg()->next(3)  );
  274 
  275 reg_def V7    ( SOC, SOC, Op_VecA, 7,  v7->as_VMReg() 	        );
  276 reg_def V7_H  ( SOC, SOC, Op_VecA, 7,  v7->as_VMReg()->next()   );
  277 reg_def V7_J  ( SOC, SOC, Op_VecA, 7,  v7->as_VMReg()->next(2)  );
  278 reg_def V7_K  ( SOC, SOC, Op_VecA, 7,  v7->as_VMReg()->next(3)  );
  279 
  280 reg_def V8    ( SOC, SOC, Op_VecA, 8,  v8->as_VMReg()           );
  281 reg_def V8_H  ( SOC, SOC, Op_VecA, 8,  v8->as_VMReg()->next()   );
  282 reg_def V8_J  ( SOC, SOC, Op_VecA, 8,  v8->as_VMReg()->next(2)  );
  283 reg_def V8_K  ( SOC, SOC, Op_VecA, 8,  v8->as_VMReg()->next(3)  );
  284 
  285 reg_def V9    ( SOC, SOC, Op_VecA, 9,  v9->as_VMReg()           );
  286 reg_def V9_H  ( SOC, SOC, Op_VecA, 9,  v9->as_VMReg()->next()   );
  287 reg_def V9_J  ( SOC, SOC, Op_VecA, 9,  v9->as_VMReg()->next(2)  );
  288 reg_def V9_K  ( SOC, SOC, Op_VecA, 9,  v9->as_VMReg()->next(3)  );
  289 
  290 reg_def V10   ( SOC, SOC, Op_VecA, 10, v10->as_VMReg()          );
  291 reg_def V10_H ( SOC, SOC, Op_VecA, 10, v10->as_VMReg()->next()  );
  292 reg_def V10_J ( SOC, SOC, Op_VecA, 10, v10->as_VMReg()->next(2) );
  293 reg_def V10_K ( SOC, SOC, Op_VecA, 10, v10->as_VMReg()->next(3) );
  294 
  295 reg_def V11   ( SOC, SOC, Op_VecA, 11, v11->as_VMReg()          );
  296 reg_def V11_H ( SOC, SOC, Op_VecA, 11, v11->as_VMReg()->next()  );
  297 reg_def V11_J ( SOC, SOC, Op_VecA, 11, v11->as_VMReg()->next(2) );
  298 reg_def V11_K ( SOC, SOC, Op_VecA, 11, v11->as_VMReg()->next(3) );
  299 
  300 reg_def V12   ( SOC, SOC, Op_VecA, 12, v12->as_VMReg()          );
  301 reg_def V12_H ( SOC, SOC, Op_VecA, 12, v12->as_VMReg()->next()  );
  302 reg_def V12_J ( SOC, SOC, Op_VecA, 12, v12->as_VMReg()->next(2) );
  303 reg_def V12_K ( SOC, SOC, Op_VecA, 12, v12->as_VMReg()->next(3) );
  304 
  305 reg_def V13   ( SOC, SOC, Op_VecA, 13, v13->as_VMReg()          );
  306 reg_def V13_H ( SOC, SOC, Op_VecA, 13, v13->as_VMReg()->next()  );
  307 reg_def V13_J ( SOC, SOC, Op_VecA, 13, v13->as_VMReg()->next(2) );
  308 reg_def V13_K ( SOC, SOC, Op_VecA, 13, v13->as_VMReg()->next(3) );
  309 
  310 reg_def V14   ( SOC, SOC, Op_VecA, 14, v14->as_VMReg()          );
  311 reg_def V14_H ( SOC, SOC, Op_VecA, 14, v14->as_VMReg()->next()  );
  312 reg_def V14_J ( SOC, SOC, Op_VecA, 14, v14->as_VMReg()->next(2) );
  313 reg_def V14_K ( SOC, SOC, Op_VecA, 14, v14->as_VMReg()->next(3) );
  314 
  315 reg_def V15   ( SOC, SOC, Op_VecA, 15, v15->as_VMReg()          );
  316 reg_def V15_H ( SOC, SOC, Op_VecA, 15, v15->as_VMReg()->next()  );
  317 reg_def V15_J ( SOC, SOC, Op_VecA, 15, v15->as_VMReg()->next(2) );
  318 reg_def V15_K ( SOC, SOC, Op_VecA, 15, v15->as_VMReg()->next(3) );
  319 
  320 reg_def V16   ( SOC, SOC, Op_VecA, 16, v16->as_VMReg()          );
  321 reg_def V16_H ( SOC, SOC, Op_VecA, 16, v16->as_VMReg()->next()  );
  322 reg_def V16_J ( SOC, SOC, Op_VecA, 16, v16->as_VMReg()->next(2) );
  323 reg_def V16_K ( SOC, SOC, Op_VecA, 16, v16->as_VMReg()->next(3) );
  324 
  325 reg_def V17   ( SOC, SOC, Op_VecA, 17, v17->as_VMReg()          );
  326 reg_def V17_H ( SOC, SOC, Op_VecA, 17, v17->as_VMReg()->next()  );
  327 reg_def V17_J ( SOC, SOC, Op_VecA, 17, v17->as_VMReg()->next(2) );
  328 reg_def V17_K ( SOC, SOC, Op_VecA, 17, v17->as_VMReg()->next(3) );
  329 
  330 reg_def V18   ( SOC, SOC, Op_VecA, 18, v18->as_VMReg()          );
  331 reg_def V18_H ( SOC, SOC, Op_VecA, 18, v18->as_VMReg()->next()  );
  332 reg_def V18_J ( SOC, SOC, Op_VecA, 18, v18->as_VMReg()->next(2) );
  333 reg_def V18_K ( SOC, SOC, Op_VecA, 18, v18->as_VMReg()->next(3) );
  334 
  335 reg_def V19   ( SOC, SOC, Op_VecA, 19, v19->as_VMReg()          );
  336 reg_def V19_H ( SOC, SOC, Op_VecA, 19, v19->as_VMReg()->next()  );
  337 reg_def V19_J ( SOC, SOC, Op_VecA, 19, v19->as_VMReg()->next(2) );
  338 reg_def V19_K ( SOC, SOC, Op_VecA, 19, v19->as_VMReg()->next(3) );
  339 
  340 reg_def V20   ( SOC, SOC, Op_VecA, 20, v20->as_VMReg()          );
  341 reg_def V20_H ( SOC, SOC, Op_VecA, 20, v20->as_VMReg()->next()  );
  342 reg_def V20_J ( SOC, SOC, Op_VecA, 20, v20->as_VMReg()->next(2) );
  343 reg_def V20_K ( SOC, SOC, Op_VecA, 20, v20->as_VMReg()->next(3) );
  344 
  345 reg_def V21   ( SOC, SOC, Op_VecA, 21, v21->as_VMReg()          );
  346 reg_def V21_H ( SOC, SOC, Op_VecA, 21, v21->as_VMReg()->next()  );
  347 reg_def V21_J ( SOC, SOC, Op_VecA, 21, v21->as_VMReg()->next(2) );
  348 reg_def V21_K ( SOC, SOC, Op_VecA, 21, v21->as_VMReg()->next(3) );
  349 
  350 reg_def V22   ( SOC, SOC, Op_VecA, 22, v22->as_VMReg()          );
  351 reg_def V22_H ( SOC, SOC, Op_VecA, 22, v22->as_VMReg()->next()  );
  352 reg_def V22_J ( SOC, SOC, Op_VecA, 22, v22->as_VMReg()->next(2) );
  353 reg_def V22_K ( SOC, SOC, Op_VecA, 22, v22->as_VMReg()->next(3) );
  354 
  355 reg_def V23   ( SOC, SOC, Op_VecA, 23, v23->as_VMReg()          );
  356 reg_def V23_H ( SOC, SOC, Op_VecA, 23, v23->as_VMReg()->next()  );
  357 reg_def V23_J ( SOC, SOC, Op_VecA, 23, v23->as_VMReg()->next(2) );
  358 reg_def V23_K ( SOC, SOC, Op_VecA, 23, v23->as_VMReg()->next(3) );
  359 
  360 reg_def V24   ( SOC, SOC, Op_VecA, 24, v24->as_VMReg()          );
  361 reg_def V24_H ( SOC, SOC, Op_VecA, 24, v24->as_VMReg()->next()  );
  362 reg_def V24_J ( SOC, SOC, Op_VecA, 24, v24->as_VMReg()->next(2) );
  363 reg_def V24_K ( SOC, SOC, Op_VecA, 24, v24->as_VMReg()->next(3) );
  364 
  365 reg_def V25   ( SOC, SOC, Op_VecA, 25, v25->as_VMReg()          );
  366 reg_def V25_H ( SOC, SOC, Op_VecA, 25, v25->as_VMReg()->next()  );
  367 reg_def V25_J ( SOC, SOC, Op_VecA, 25, v25->as_VMReg()->next(2) );
  368 reg_def V25_K ( SOC, SOC, Op_VecA, 25, v25->as_VMReg()->next(3) );
  369 
  370 reg_def V26   ( SOC, SOC, Op_VecA, 26, v26->as_VMReg()          );
  371 reg_def V26_H ( SOC, SOC, Op_VecA, 26, v26->as_VMReg()->next()  );
  372 reg_def V26_J ( SOC, SOC, Op_VecA, 26, v26->as_VMReg()->next(2) );
  373 reg_def V26_K ( SOC, SOC, Op_VecA, 26, v26->as_VMReg()->next(3) );
  374 
  375 reg_def V27   ( SOC, SOC, Op_VecA, 27, v27->as_VMReg()          );
  376 reg_def V27_H ( SOC, SOC, Op_VecA, 27, v27->as_VMReg()->next()  );
  377 reg_def V27_J ( SOC, SOC, Op_VecA, 27, v27->as_VMReg()->next(2) );
  378 reg_def V27_K ( SOC, SOC, Op_VecA, 27, v27->as_VMReg()->next(3) );
  379 
  380 reg_def V28   ( SOC, SOC, Op_VecA, 28, v28->as_VMReg()          );
  381 reg_def V28_H ( SOC, SOC, Op_VecA, 28, v28->as_VMReg()->next()  );
  382 reg_def V28_J ( SOC, SOC, Op_VecA, 28, v28->as_VMReg()->next(2) );
  383 reg_def V28_K ( SOC, SOC, Op_VecA, 28, v28->as_VMReg()->next(3) );
  384 
  385 reg_def V29   ( SOC, SOC, Op_VecA, 29, v29->as_VMReg()          );
  386 reg_def V29_H ( SOC, SOC, Op_VecA, 29, v29->as_VMReg()->next()  );
  387 reg_def V29_J ( SOC, SOC, Op_VecA, 29, v29->as_VMReg()->next(2) );
  388 reg_def V29_K ( SOC, SOC, Op_VecA, 29, v29->as_VMReg()->next(3) );
  389 
  390 reg_def V30   ( SOC, SOC, Op_VecA, 30, v30->as_VMReg()          );
  391 reg_def V30_H ( SOC, SOC, Op_VecA, 30, v30->as_VMReg()->next()  );
  392 reg_def V30_J ( SOC, SOC, Op_VecA, 30, v30->as_VMReg()->next(2) );
  393 reg_def V30_K ( SOC, SOC, Op_VecA, 30, v30->as_VMReg()->next(3) );
  394 
  395 reg_def V31   ( SOC, SOC, Op_VecA, 31, v31->as_VMReg()          );
  396 reg_def V31_H ( SOC, SOC, Op_VecA, 31, v31->as_VMReg()->next()  );
  397 reg_def V31_J ( SOC, SOC, Op_VecA, 31, v31->as_VMReg()->next(2) );
  398 reg_def V31_K ( SOC, SOC, Op_VecA, 31, v31->as_VMReg()->next(3) );
  399 
  400 // ----------------------------
  401 // Special Registers
  402 // ----------------------------
  403 
  404 // On riscv, the physical flag register is missing, so we use t1 instead,
  405 // to bridge the RegFlag semantics in share/opto
  406 
  407 reg_def RFLAGS   (SOC, SOC, Op_RegFlags, 6, x6->as_VMReg()        );
  408 
  409 // Specify priority of register selection within phases of register
  410 // allocation.  Highest priority is first.  A useful heuristic is to
  411 // give registers a low priority when they are required by machine
  412 // instructions, like EAX and EDX on I486, and choose no-save registers
  413 // before save-on-call, & save-on-call before save-on-entry.  Registers
  414 // which participate in fixed calling sequences should come last.
  415 // Registers which are used as pairs must fall on an even boundary.
  416 
  417 alloc_class chunk0(
  418     // volatiles
  419     R7,  R7_H,
  420     R28, R28_H,
  421     R29, R29_H,
  422     R30, R30_H,
  423     R31, R31_H,
  424 
  425     // arg registers
  426     R10, R10_H,
  427     R11, R11_H,
  428     R12, R12_H,
  429     R13, R13_H,
  430     R14, R14_H,
  431     R15, R15_H,
  432     R16, R16_H,
  433     R17, R17_H,
  434 
  435     // non-volatiles
  436     R9,  R9_H,
  437     R18, R18_H,
  438     R19, R19_H,
  439     R20, R20_H,
  440     R21, R21_H,
  441     R22, R22_H,
  442     R24, R24_H,
  443     R25, R25_H,
  444     R26, R26_H,
  445 
  446     // non-allocatable registers
  447     R23, R23_H, // java thread
  448     R27, R27_H, // heapbase
  449     R4,  R4_H,  // thread
  450     R8,  R8_H,  // fp
  451     R0,  R0_H,  // zero
  452     R1,  R1_H,  // ra
  453     R2,  R2_H,  // sp
  454     R3,  R3_H,  // gp
  455 );
  456 
  457 alloc_class chunk1(
  458 
  459     // no save
  460     F0,  F0_H,
  461     F1,  F1_H,
  462     F2,  F2_H,
  463     F3,  F3_H,
  464     F4,  F4_H,
  465     F5,  F5_H,
  466     F6,  F6_H,
  467     F7,  F7_H,
  468     F28, F28_H,
  469     F29, F29_H,
  470     F30, F30_H,
  471     F31, F31_H,
  472 
  473     // arg registers
  474     F10, F10_H,
  475     F11, F11_H,
  476     F12, F12_H,
  477     F13, F13_H,
  478     F14, F14_H,
  479     F15, F15_H,
  480     F16, F16_H,
  481     F17, F17_H,
  482 
  483     // non-volatiles
  484     F8,  F8_H,
  485     F9,  F9_H,
  486     F18, F18_H,
  487     F19, F19_H,
  488     F20, F20_H,
  489     F21, F21_H,
  490     F22, F22_H,
  491     F23, F23_H,
  492     F24, F24_H,
  493     F25, F25_H,
  494     F26, F26_H,
  495     F27, F27_H,
  496 );
  497 
  498 alloc_class chunk2(
  499     V0, V0_H, V0_J, V0_K,
  500     V1, V1_H, V1_J, V1_K,
  501     V2, V2_H, V2_J, V2_K,
  502     V3, V3_H, V3_J, V3_K,
  503     V4, V4_H, V4_J, V4_K,
  504     V5, V5_H, V5_J, V5_K,
  505     V6, V6_H, V6_J, V6_K,
  506     V7, V7_H, V7_J, V7_K,
  507     V8, V8_H, V8_J, V8_K,
  508     V9, V9_H, V9_J, V9_K,
  509     V10, V10_H, V10_J, V10_K,
  510     V11, V11_H, V11_J, V11_K,
  511     V12, V12_H, V12_J, V12_K,
  512     V13, V13_H, V13_J, V13_K,
  513     V14, V14_H, V14_J, V14_K,
  514     V15, V15_H, V15_J, V15_K,
  515     V16, V16_H, V16_J, V16_K,
  516     V17, V17_H, V17_J, V17_K,
  517     V18, V18_H, V18_J, V18_K,
  518     V19, V19_H, V19_J, V19_K,
  519     V20, V20_H, V20_J, V20_K,
  520     V21, V21_H, V21_J, V21_K,
  521     V22, V22_H, V22_J, V22_K,
  522     V23, V23_H, V23_J, V23_K,
  523     V24, V24_H, V24_J, V24_K,
  524     V25, V25_H, V25_J, V25_K,
  525     V26, V26_H, V26_J, V26_K,
  526     V27, V27_H, V27_J, V27_K,
  527     V28, V28_H, V28_J, V28_K,
  528     V29, V29_H, V29_J, V29_K,
  529     V30, V30_H, V30_J, V30_K,
  530     V31, V31_H, V31_J, V31_K,
  531 );
  532 
  533 alloc_class chunk3(RFLAGS);
  534 
  535 //----------Architecture Description Register Classes--------------------------
  536 // Several register classes are automatically defined based upon information in
  537 // this architecture description.
  538 // 1) reg_class inline_cache_reg           ( /* as def'd in frame section */ )
  539 // 2) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
  540 //
  541 
  542 // Class for all 32 bit general purpose registers
  543 reg_class all_reg32(
  544     R0,
  545     R1,
  546     R2,
  547     R3,
  548     R4,
  549     R7,
  550     R8,
  551     R9,
  552     R10,
  553     R11,
  554     R12,
  555     R13,
  556     R14,
  557     R15,
  558     R16,
  559     R17,
  560     R18,
  561     R19,
  562     R20,
  563     R21,
  564     R22,
  565     R23,
  566     R24,
  567     R25,
  568     R26,
  569     R27,
  570     R28,
  571     R29,
  572     R30,
  573     R31
  574 );
  575 
  576 // Class for any 32 bit integer registers (excluding zr)
  577 reg_class any_reg32 %{
  578   return _ANY_REG32_mask;
  579 %}
  580 
  581 // Singleton class for R10 int register
  582 reg_class int_r10_reg(R10);
  583 
  584 // Singleton class for R12 int register
  585 reg_class int_r12_reg(R12);
  586 
  587 // Singleton class for R13 int register
  588 reg_class int_r13_reg(R13);
  589 
  590 // Singleton class for R14 int register
  591 reg_class int_r14_reg(R14);
  592 
  593 // Class for all long integer registers
  594 reg_class all_reg(
  595     R0,  R0_H,
  596     R1,  R1_H,
  597     R2,  R2_H,
  598     R3,  R3_H,
  599     R4,  R4_H,
  600     R7,  R7_H,
  601     R8,  R8_H,
  602     R9,  R9_H,
  603     R10, R10_H,
  604     R11, R11_H,
  605     R12, R12_H,
  606     R13, R13_H,
  607     R14, R14_H,
  608     R15, R15_H,
  609     R16, R16_H,
  610     R17, R17_H,
  611     R18, R18_H,
  612     R19, R19_H,
  613     R20, R20_H,
  614     R21, R21_H,
  615     R22, R22_H,
  616     R23, R23_H,
  617     R24, R24_H,
  618     R25, R25_H,
  619     R26, R26_H,
  620     R27, R27_H,
  621     R28, R28_H,
  622     R29, R29_H,
  623     R30, R30_H,
  624     R31, R31_H
  625 );
  626 
  627 // Class for all long integer registers (excluding zr)
  628 reg_class any_reg %{
  629   return _ANY_REG_mask;
  630 %}
  631 
  632 // Class for non-allocatable 32 bit registers
  633 reg_class non_allocatable_reg32(
  634     R0,                       // zr
  635     R1,                       // ra
  636     R2,                       // sp
  637     R3,                       // gp
  638     R4,                       // tp
  639     R23                       // java thread
  640 );
  641 
  642 // Class for non-allocatable 64 bit registers
  643 reg_class non_allocatable_reg(
  644     R0,  R0_H,                // zr
  645     R1,  R1_H,                // ra
  646     R2,  R2_H,                // sp
  647     R3,  R3_H,                // gp
  648     R4,  R4_H,                // tp
  649     R23, R23_H                // java thread
  650 );
  651 
  652 reg_class no_special_reg32 %{
  653   return _NO_SPECIAL_REG32_mask;
  654 %}
  655 
  656 reg_class no_special_reg %{
  657   return _NO_SPECIAL_REG_mask;
  658 %}
  659 
  660 reg_class ptr_reg %{
  661   return _PTR_REG_mask;
  662 %}
  663 
  664 reg_class no_special_ptr_reg %{
  665   return _NO_SPECIAL_PTR_REG_mask;
  666 %}
  667 
  668 // Class for 64 bit register r10
  669 reg_class r10_reg(
  670     R10, R10_H
  671 );
  672 
  673 // Class for 64 bit register r11
  674 reg_class r11_reg(
  675     R11, R11_H
  676 );
  677 
  678 // Class for 64 bit register r12
  679 reg_class r12_reg(
  680     R12, R12_H
  681 );
  682 
  683 // Class for 64 bit register r13
  684 reg_class r13_reg(
  685     R13, R13_H
  686 );
  687 
  688 // Class for 64 bit register r14
  689 reg_class r14_reg(
  690     R14, R14_H
  691 );
  692 
  693 // Class for 64 bit register r15
  694 reg_class r15_reg(
  695     R15, R15_H
  696 );
  697 
  698 // Class for 64 bit register r16
  699 reg_class r16_reg(
  700     R16, R16_H
  701 );
  702 
  703 // Class for method register
  704 reg_class method_reg(
  705     R31, R31_H
  706 );
  707 
  708 // Class for heapbase register
  709 reg_class heapbase_reg(
  710     R27, R27_H
  711 );
  712 
  713 // Class for java thread register
  714 reg_class java_thread_reg(
  715     R23, R23_H
  716 );
  717 
  718 reg_class r28_reg(
  719     R28, R28_H
  720 );
  721 
  722 reg_class r29_reg(
  723     R29, R29_H
  724 );
  725 
  726 reg_class r30_reg(
  727     R30, R30_H
  728 );
  729 
  730 reg_class r31_reg(
  731     R31, R31_H
  732 );
  733 
  734 // Class for zero registesr
  735 reg_class zr_reg(
  736     R0, R0_H
  737 );
  738 
  739 // Class for thread register
  740 reg_class thread_reg(
  741     R4, R4_H
  742 );
  743 
  744 // Class for frame pointer register
  745 reg_class fp_reg(
  746     R8, R8_H
  747 );
  748 
  749 // Class for link register
  750 reg_class ra_reg(
  751     R1, R1_H
  752 );
  753 
  754 // Class for long sp register
  755 reg_class sp_reg(
  756     R2, R2_H
  757 );
  758 
  759 // Class for all float registers
  760 reg_class float_reg(
  761     F0,
  762     F1,
  763     F2,
  764     F3,
  765     F4,
  766     F5,
  767     F6,
  768     F7,
  769     F8,
  770     F9,
  771     F10,
  772     F11,
  773     F12,
  774     F13,
  775     F14,
  776     F15,
  777     F16,
  778     F17,
  779     F18,
  780     F19,
  781     F20,
  782     F21,
  783     F22,
  784     F23,
  785     F24,
  786     F25,
  787     F26,
  788     F27,
  789     F28,
  790     F29,
  791     F30,
  792     F31
  793 );
  794 
  795 // Double precision float registers have virtual `high halves' that
  796 // are needed by the allocator.
  797 // Class for all double registers
  798 reg_class double_reg(
  799     F0,  F0_H,
  800     F1,  F1_H,
  801     F2,  F2_H,
  802     F3,  F3_H,
  803     F4,  F4_H,
  804     F5,  F5_H,
  805     F6,  F6_H,
  806     F7,  F7_H,
  807     F8,  F8_H,
  808     F9,  F9_H,
  809     F10, F10_H,
  810     F11, F11_H,
  811     F12, F12_H,
  812     F13, F13_H,
  813     F14, F14_H,
  814     F15, F15_H,
  815     F16, F16_H,
  816     F17, F17_H,
  817     F18, F18_H,
  818     F19, F19_H,
  819     F20, F20_H,
  820     F21, F21_H,
  821     F22, F22_H,
  822     F23, F23_H,
  823     F24, F24_H,
  824     F25, F25_H,
  825     F26, F26_H,
  826     F27, F27_H,
  827     F28, F28_H,
  828     F29, F29_H,
  829     F30, F30_H,
  830     F31, F31_H
  831 );
  832 
  833 // Class for all RVV vector registers
  834 reg_class vectora_reg(
  835     V1, V1_H, V1_J, V1_K,
  836     V2, V2_H, V2_J, V2_K,
  837     V3, V3_H, V3_J, V3_K,
  838     V4, V4_H, V4_J, V4_K,
  839     V5, V5_H, V5_J, V5_K,
  840     V6, V6_H, V6_J, V6_K,
  841     V7, V7_H, V7_J, V7_K,
  842     V8, V8_H, V8_J, V8_K,
  843     V9, V9_H, V9_J, V9_K,
  844     V10, V10_H, V10_J, V10_K,
  845     V11, V11_H, V11_J, V11_K,
  846     V12, V12_H, V12_J, V12_K,
  847     V13, V13_H, V13_J, V13_K,
  848     V14, V14_H, V14_J, V14_K,
  849     V15, V15_H, V15_J, V15_K,
  850     V16, V16_H, V16_J, V16_K,
  851     V17, V17_H, V17_J, V17_K,
  852     V18, V18_H, V18_J, V18_K,
  853     V19, V19_H, V19_J, V19_K,
  854     V20, V20_H, V20_J, V20_K,
  855     V21, V21_H, V21_J, V21_K,
  856     V22, V22_H, V22_J, V22_K,
  857     V23, V23_H, V23_J, V23_K,
  858     V24, V24_H, V24_J, V24_K,
  859     V25, V25_H, V25_J, V25_K,
  860     V26, V26_H, V26_J, V26_K,
  861     V27, V27_H, V27_J, V27_K,
  862     V28, V28_H, V28_J, V28_K,
  863     V29, V29_H, V29_J, V29_K,
  864     V30, V30_H, V30_J, V30_K,
  865     V31, V31_H, V31_J, V31_K
  866 );
  867 
  868 // Class for 64 bit register f0
  869 reg_class f0_reg(
  870     F0, F0_H
  871 );
  872 
  873 // Class for 64 bit register f1
  874 reg_class f1_reg(
  875     F1, F1_H
  876 );
  877 
  878 // Class for 64 bit register f2
  879 reg_class f2_reg(
  880     F2, F2_H
  881 );
  882 
  883 // Class for 64 bit register f3
  884 reg_class f3_reg(
  885     F3, F3_H
  886 );
  887 
  888 // class for vector register v1
  889 reg_class v1_reg(
  890     V1, V1_H, V1_J, V1_K
  891 );
  892 
  893 // class for vector register v2
  894 reg_class v2_reg(
  895     V2, V2_H, V2_J, V2_K
  896 );
  897 
  898 // class for vector register v3
  899 reg_class v3_reg(
  900     V3, V3_H, V3_J, V3_K
  901 );
  902 
  903 // class for vector register v4
  904 reg_class v4_reg(
  905     V4, V4_H, V4_J, V4_K
  906 );
  907 
  908 // class for vector register v5
  909 reg_class v5_reg(
  910     V5, V5_H, V5_J, V5_K
  911 );
  912 
  913 // class for condition codes
  914 reg_class reg_flags(RFLAGS);
  915 %}
  916 
  917 //----------DEFINITION BLOCK---------------------------------------------------
  918 // Define name --> value mappings to inform the ADLC of an integer valued name
  919 // Current support includes integer values in the range [0, 0x7FFFFFFF]
  920 // Format:
  921 //        int_def  <name>         ( <int_value>, <expression>);
  922 // Generated Code in ad_<arch>.hpp
  923 //        #define  <name>   (<expression>)
  924 //        // value == <int_value>
  925 // Generated code in ad_<arch>.cpp adlc_verification()
  926 //        assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
  927 //
  928 
  929 // we follow the ppc-aix port in using a simple cost model which ranks
  930 // register operations as cheap, memory ops as more expensive and
  931 // branches as most expensive. the first two have a low as well as a
  932 // normal cost. huge cost appears to be a way of saying don't do
  933 // something
  934 
  935 definitions %{
  936   // The default cost (of a register move instruction).
  937   int_def DEFAULT_COST         (  100,               100);
  938   int_def ALU_COST             (  100,  1 * DEFAULT_COST);          // unknown, const, arith, shift, slt,
  939                                                                     // multi, auipc, nop, logical, move
  940   int_def LOAD_COST            (  300,  3 * DEFAULT_COST);          // load, fpload
  941   int_def STORE_COST           (  100,  1 * DEFAULT_COST);          // store, fpstore
  942   int_def XFER_COST            (  300,  3 * DEFAULT_COST);          // mfc, mtc, fcvt, fmove, fcmp
  943   int_def BRANCH_COST          (  200,  2 * DEFAULT_COST);          // branch, jmp, call
  944   int_def IMUL_COST            ( 1000, 10 * DEFAULT_COST);          // imul
  945   int_def IDIVSI_COST          ( 3400, 34 * DEFAULT_COST);          // idivdi
  946   int_def IDIVDI_COST          ( 6600, 66 * DEFAULT_COST);          // idivsi
  947   int_def FMUL_SINGLE_COST     (  500,  5 * DEFAULT_COST);          // fmul, fmadd
  948   int_def FMUL_DOUBLE_COST     (  700,  7 * DEFAULT_COST);          // fmul, fmadd
  949   int_def FDIV_COST            ( 2000, 20 * DEFAULT_COST);          // fdiv
  950   int_def FSQRT_COST           ( 2500, 25 * DEFAULT_COST);          // fsqrt
  951   int_def VOLATILE_REF_COST    ( 1000, 10 * DEFAULT_COST);
  952   int_def CACHE_MISS_COST      ( 2000, 20 * DEFAULT_COST);          // typicall cache miss penalty
  953 %}
  954 
  955 
  956 
  957 //----------SOURCE BLOCK-------------------------------------------------------
  958 // This is a block of C++ code which provides values, functions, and
  959 // definitions necessary in the rest of the architecture description
  960 
  961 source_hpp %{
  962 
  963 #include "asm/macroAssembler.hpp"
  964 #include "gc/shared/barrierSetAssembler.hpp"
  965 #include "gc/shared/cardTable.hpp"
  966 #include "gc/shared/cardTableBarrierSet.hpp"
  967 #include "gc/shared/collectedHeap.hpp"
  968 #include "opto/addnode.hpp"
  969 #include "opto/convertnode.hpp"
  970 #include "runtime/objectMonitor.hpp"
  971 
  972 extern RegMask _ANY_REG32_mask;
  973 extern RegMask _ANY_REG_mask;
  974 extern RegMask _PTR_REG_mask;
  975 extern RegMask _NO_SPECIAL_REG32_mask;
  976 extern RegMask _NO_SPECIAL_REG_mask;
  977 extern RegMask _NO_SPECIAL_PTR_REG_mask;
  978 
  979 class CallStubImpl {
  980 
  981   //--------------------------------------------------------------
  982   //---<  Used for optimization in Compile::shorten_branches  >---
  983   //--------------------------------------------------------------
  984 
  985  public:
  986   // Size of call trampoline stub.
  987   static uint size_call_trampoline() {
  988     return 0; // no call trampolines on this platform
  989   }
  990 
  991   // number of relocations needed by a call trampoline stub
  992   static uint reloc_call_trampoline() {
  993     return 0; // no call trampolines on this platform
  994   }
  995 };
  996 
  997 class HandlerImpl {
  998 
  999  public:
 1000 
 1001   static int emit_exception_handler(CodeBuffer &cbuf);
 1002   static int emit_deopt_handler(CodeBuffer& cbuf);
 1003 
 1004   static uint size_exception_handler() {
 1005     return MacroAssembler::far_branch_size();
 1006   }
 1007 
 1008   static uint size_deopt_handler() {
 1009     // count auipc + far branch
 1010     return NativeInstruction::instruction_size + MacroAssembler::far_branch_size();
 1011   }
 1012 };
 1013 
 1014 class Node::PD {
 1015 public:
 1016   enum NodeFlags {
 1017     _last_flag = Node::_last_flag
 1018   };
 1019 };
 1020 
 1021 bool is_CAS(int opcode, bool maybe_volatile);
 1022 
 1023 // predicate controlling translation of CompareAndSwapX
 1024 bool needs_acquiring_load_reserved(const Node *load);
 1025 
 1026 // predicate controlling addressing modes
 1027 bool size_fits_all_mem_uses(AddPNode* addp, int shift);
 1028 %}
 1029 
 1030 source %{
 1031 
 1032 // Derived RegMask with conditionally allocatable registers
 1033 
 1034 RegMask _ANY_REG32_mask;
 1035 RegMask _ANY_REG_mask;
 1036 RegMask _PTR_REG_mask;
 1037 RegMask _NO_SPECIAL_REG32_mask;
 1038 RegMask _NO_SPECIAL_REG_mask;
 1039 RegMask _NO_SPECIAL_PTR_REG_mask;
 1040 
 1041 void reg_mask_init() {
 1042 
 1043   _ANY_REG32_mask = _ALL_REG32_mask;
 1044   _ANY_REG32_mask.Remove(OptoReg::as_OptoReg(x0->as_VMReg()));
 1045 
 1046   _ANY_REG_mask = _ALL_REG_mask;
 1047   _ANY_REG_mask.SUBTRACT(_ZR_REG_mask);
 1048 
 1049   _PTR_REG_mask = _ALL_REG_mask;
 1050   _PTR_REG_mask.SUBTRACT(_ZR_REG_mask);
 1051 
 1052   _NO_SPECIAL_REG32_mask = _ALL_REG32_mask;
 1053   _NO_SPECIAL_REG32_mask.SUBTRACT(_NON_ALLOCATABLE_REG32_mask);
 1054 
 1055   _NO_SPECIAL_REG_mask = _ALL_REG_mask;
 1056   _NO_SPECIAL_REG_mask.SUBTRACT(_NON_ALLOCATABLE_REG_mask);
 1057 
 1058   _NO_SPECIAL_PTR_REG_mask = _ALL_REG_mask;
 1059   _NO_SPECIAL_PTR_REG_mask.SUBTRACT(_NON_ALLOCATABLE_REG_mask);
 1060 
 1061   // x27 is not allocatable when compressed oops is on
 1062   if (UseCompressedOops) {
 1063     _NO_SPECIAL_REG32_mask.Remove(OptoReg::as_OptoReg(x27->as_VMReg()));
 1064     _NO_SPECIAL_REG_mask.SUBTRACT(_HEAPBASE_REG_mask);
 1065     _NO_SPECIAL_PTR_REG_mask.SUBTRACT(_HEAPBASE_REG_mask);
 1066   }
 1067 
 1068   // x8 is not allocatable when PreserveFramePointer is on
 1069   if (PreserveFramePointer) {
 1070     _NO_SPECIAL_REG32_mask.Remove(OptoReg::as_OptoReg(x8->as_VMReg()));
 1071     _NO_SPECIAL_REG_mask.SUBTRACT(_FP_REG_mask);
 1072     _NO_SPECIAL_PTR_REG_mask.SUBTRACT(_FP_REG_mask);
 1073   }
 1074 }
 1075 
 1076 void PhaseOutput::pd_perform_mach_node_analysis() {
 1077 }
 1078 
 1079 int MachNode::pd_alignment_required() const {
 1080   return 1;
 1081 }
 1082 
 1083 int MachNode::compute_padding(int current_offset) const {
 1084   return 0;
 1085 }
 1086 
 1087 // is_CAS(int opcode, bool maybe_volatile)
 1088 //
 1089 // return true if opcode is one of the possible CompareAndSwapX
 1090 // values otherwise false.
 1091 bool is_CAS(int opcode, bool maybe_volatile)
 1092 {
 1093   switch (opcode) {
 1094     // We handle these
 1095     case Op_CompareAndSwapI:
 1096     case Op_CompareAndSwapL:
 1097     case Op_CompareAndSwapP:
 1098     case Op_CompareAndSwapN:
 1099     case Op_ShenandoahCompareAndSwapP:
 1100     case Op_ShenandoahCompareAndSwapN:
 1101     case Op_CompareAndSwapB:
 1102     case Op_CompareAndSwapS:
 1103     case Op_GetAndSetI:
 1104     case Op_GetAndSetL:
 1105     case Op_GetAndSetP:
 1106     case Op_GetAndSetN:
 1107     case Op_GetAndAddI:
 1108     case Op_GetAndAddL:
 1109       return true;
 1110     case Op_CompareAndExchangeI:
 1111     case Op_CompareAndExchangeN:
 1112     case Op_CompareAndExchangeB:
 1113     case Op_CompareAndExchangeS:
 1114     case Op_CompareAndExchangeL:
 1115     case Op_CompareAndExchangeP:
 1116     case Op_WeakCompareAndSwapB:
 1117     case Op_WeakCompareAndSwapS:
 1118     case Op_WeakCompareAndSwapI:
 1119     case Op_WeakCompareAndSwapL:
 1120     case Op_WeakCompareAndSwapP:
 1121     case Op_WeakCompareAndSwapN:
 1122     case Op_ShenandoahWeakCompareAndSwapP:
 1123     case Op_ShenandoahWeakCompareAndSwapN:
 1124     case Op_ShenandoahCompareAndExchangeP:
 1125     case Op_ShenandoahCompareAndExchangeN:
 1126       return maybe_volatile;
 1127     default:
 1128       return false;
 1129   }
 1130 }
 1131 
 1132 // predicate controlling translation of CAS
 1133 //
 1134 // returns true if CAS needs to use an acquiring load otherwise false
 1135 bool needs_acquiring_load_reserved(const Node *n)
 1136 {
 1137   assert(n != NULL && is_CAS(n->Opcode(), true), "expecting a compare and swap");
 1138 
 1139   LoadStoreNode* ldst = n->as_LoadStore();
 1140   if (n != NULL && is_CAS(n->Opcode(), false)) {
 1141     assert(ldst != NULL && ldst->trailing_membar() != NULL, "expected trailing membar");
 1142   } else {
 1143     return ldst != NULL && ldst->trailing_membar() != NULL;
 1144   }
 1145   // so we can just return true here
 1146   return true;
 1147 }
 1148 #define __ _masm.
 1149 
 1150 // advance declarations for helper functions to convert register
 1151 // indices to register objects
 1152 
 1153 // the ad file has to provide implementations of certain methods
 1154 // expected by the generic code
 1155 //
 1156 // REQUIRED FUNCTIONALITY
 1157 
 1158 //=============================================================================
 1159 
 1160 // !!!!! Special hack to get all types of calls to specify the byte offset
 1161 //       from the start of the call to the point where the return address
 1162 //       will point.
 1163 
 1164 int MachCallStaticJavaNode::ret_addr_offset()
 1165 {
 1166   // jal
 1167   return 1 * NativeInstruction::instruction_size;
 1168 }
 1169 
 1170 int MachCallDynamicJavaNode::ret_addr_offset()
 1171 {
 1172   return 7 * NativeInstruction::instruction_size; // movptr, jal
 1173 }
 1174 
 1175 int MachCallRuntimeNode::ret_addr_offset() {
 1176   // for generated stubs the call will be
 1177   //   jal(addr)
 1178   // or with far branches
 1179   //   jal(trampoline_stub)
 1180   // for real runtime callouts it will be 11 instructions
 1181   // see riscv_enc_java_to_runtime
 1182   //   la(t1, retaddr)                ->  auipc + addi
 1183   //   la(t0, RuntimeAddress(addr))   ->  lui + addi + slli + addi + slli + addi
 1184   //   addi(sp, sp, -2 * wordSize)    ->  addi
 1185   //   sd(t1, Address(sp, wordSize))  ->  sd
 1186   //   jalr(t0)                       ->  jalr
 1187   CodeBlob *cb = CodeCache::find_blob(_entry_point);
 1188   if (cb != NULL) {
 1189     return 1 * NativeInstruction::instruction_size;
 1190   } else {
 1191     return 11 * NativeInstruction::instruction_size;
 1192   }
 1193 }
 1194 
 1195 //
 1196 // Compute padding required for nodes which need alignment
 1197 //
 1198 
 1199 // With RVC a call instruction may get 2-byte aligned.
 1200 // The address of the call instruction needs to be 4-byte aligned to
 1201 // ensure that it does not span a cache line so that it can be patched.
 1202 int CallStaticJavaDirectNode::compute_padding(int current_offset) const
 1203 {
 1204   // to make sure the address of jal 4-byte aligned.
 1205   return align_up(current_offset, alignment_required()) - current_offset;
 1206 }
 1207 
 1208 // With RVC a call instruction may get 2-byte aligned.
 1209 // The address of the call instruction needs to be 4-byte aligned to
 1210 // ensure that it does not span a cache line so that it can be patched.
 1211 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const
 1212 {
 1213   // skip the movptr in MacroAssembler::ic_call():
 1214   // lui + addi + slli + addi + slli + addi
 1215   // Though movptr() has already 4-byte aligned with or without RVC,
 1216   // We need to prevent from further changes by explicitly calculating the size.
 1217   const int movptr_size = 6 * NativeInstruction::instruction_size;
 1218   current_offset += movptr_size;
 1219   // to make sure the address of jal 4-byte aligned.
 1220   return align_up(current_offset, alignment_required()) - current_offset;
 1221 }
 1222 
 1223 //=============================================================================
 1224 
 1225 #ifndef PRODUCT
 1226 void MachBreakpointNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
 1227   assert_cond(st != NULL);
 1228   st->print("BREAKPOINT");
 1229 }
 1230 #endif
 1231 
 1232 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
 1233   C2_MacroAssembler _masm(&cbuf);
 1234   __ ebreak();
 1235 }
 1236 
 1237 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
 1238   return MachNode::size(ra_);
 1239 }
 1240 
 1241 //=============================================================================
 1242 
 1243 #ifndef PRODUCT
 1244   void MachNopNode::format(PhaseRegAlloc*, outputStream* st) const {
 1245     st->print("nop \t# %d bytes pad for loops and calls", _count);
 1246   }
 1247 #endif
 1248 
 1249   void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc*) const {
 1250     C2_MacroAssembler _masm(&cbuf);
 1251     Assembler::CompressibleRegion cr(&_masm); // nops shall be 2-byte under RVC for alignment purposes.
 1252     for (int i = 0; i < _count; i++) {
 1253       __ nop();
 1254     }
 1255   }
 1256 
 1257   uint MachNopNode::size(PhaseRegAlloc*) const {
 1258     return _count * (UseRVC ? NativeInstruction::compressed_instruction_size : NativeInstruction::instruction_size);
 1259   }
 1260 
 1261 //=============================================================================
 1262 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;
 1263 
 1264 int ConstantTable::calculate_table_base_offset() const {
 1265   return 0;  // absolute addressing, no offset
 1266 }
 1267 
 1268 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
 1269 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
 1270   ShouldNotReachHere();
 1271 }
 1272 
 1273 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
 1274   // Empty encoding
 1275 }
 1276 
 1277 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
 1278   return 0;
 1279 }
 1280 
 1281 #ifndef PRODUCT
 1282 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
 1283   assert_cond(st != NULL);
 1284   st->print("-- \t// MachConstantBaseNode (empty encoding)");
 1285 }
 1286 #endif
 1287 
 1288 #ifndef PRODUCT
 1289 void MachPrologNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
 1290   assert_cond(st != NULL && ra_ != NULL);
 1291   Compile* C = ra_->C;
 1292 
 1293   int framesize = C->output()->frame_slots() << LogBytesPerInt;
 1294 
 1295   if (C->output()->need_stack_bang(framesize)) {
 1296     st->print("# stack bang size=%d\n\t", framesize);
 1297   }
 1298 
 1299   st->print("sd  fp, [sp, #%d]\n\t", - 2 * wordSize);
 1300   st->print("sd  ra, [sp, #%d]\n\t", - wordSize);
 1301   if (PreserveFramePointer) { st->print("sub  fp, sp, #%d\n\t", 2 * wordSize); }
 1302   st->print("sub sp, sp, #%d\n\t", framesize);
 1303 
 1304   if (C->stub_function() == NULL && BarrierSet::barrier_set()->barrier_set_nmethod() != NULL) {
 1305     st->print("ld  t0, [guard]\n\t");
 1306     st->print("membar LoadLoad\n\t");
 1307     st->print("ld  t1, [xthread, #thread_disarmed_guard_value_offset]\n\t");
 1308     st->print("beq t0, t1, skip\n\t");
 1309     st->print("jalr #nmethod_entry_barrier_stub\n\t");
 1310     st->print("j skip\n\t");
 1311     st->print("guard: int\n\t");
 1312     st->print("skip:\n\t");
 1313   }
 1314 }
 1315 #endif
 1316 
 1317 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
 1318   assert_cond(ra_ != NULL);
 1319   Compile* C = ra_->C;
 1320   C2_MacroAssembler _masm(&cbuf);
 1321 
 1322   // n.b. frame size includes space for return pc and fp
 1323   const int framesize = C->output()->frame_size_in_bytes();
 1324 
 1325   // insert a nop at the start of the prolog so we can patch in a
 1326   // branch if we need to invalidate the method later
 1327   {
 1328     Assembler::IncompressibleRegion ir(&_masm);  // keep the nop as 4 bytes for patching.
 1329     MacroAssembler::assert_alignment(__ pc());
 1330     __ nop();  // 4 bytes
 1331   }
 1332 
 1333   assert_cond(C != NULL);
 1334 
 1335   if (C->clinit_barrier_on_entry()) {
 1336     assert(!C->method()->holder()->is_not_initialized(), "initialization should have been started");
 1337 
 1338     Label L_skip_barrier;
 1339 
 1340     __ mov_metadata(t1, C->method()->holder()->constant_encoding());
 1341     __ clinit_barrier(t1, t0, &L_skip_barrier);
 1342     __ far_jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub()));
 1343     __ bind(L_skip_barrier);
 1344   }
 1345 
 1346   int bangsize = C->output()->bang_size_in_bytes();
 1347   if (C->output()->need_stack_bang(bangsize)) {
 1348     __ generate_stack_overflow_check(bangsize);
 1349   }
 1350 
 1351   __ build_frame(framesize);
 1352 
 1353   if (C->stub_function() == NULL) {
 1354     BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
 1355     if (BarrierSet::barrier_set()->barrier_set_nmethod() != NULL) {
 1356       // Dummy labels for just measuring the code size
 1357       Label dummy_slow_path;
 1358       Label dummy_continuation;
 1359       Label dummy_guard;
 1360       Label* slow_path = &dummy_slow_path;
 1361       Label* continuation = &dummy_continuation;
 1362       Label* guard = &dummy_guard;
 1363       if (!Compile::current()->output()->in_scratch_emit_size()) {
 1364         // Use real labels from actual stub when not emitting code for purpose of measuring its size
 1365         C2EntryBarrierStub* stub = new (Compile::current()->comp_arena()) C2EntryBarrierStub();
 1366         Compile::current()->output()->add_stub(stub);
 1367         slow_path = &stub->entry();
 1368         continuation = &stub->continuation();
 1369         guard = &stub->guard();
 1370       }
 1371       // In the C2 code, we move the non-hot part of nmethod entry barriers out-of-line to a stub.
 1372       bs->nmethod_entry_barrier(&_masm, slow_path, continuation, guard);
 1373     }
 1374   }
 1375 
 1376   if (VerifyStackAtCalls) {
 1377     Unimplemented();
 1378   }
 1379 
 1380   C->output()->set_frame_complete(cbuf.insts_size());
 1381 
 1382   if (C->has_mach_constant_base_node()) {
 1383     // NOTE: We set the table base offset here because users might be
 1384     // emitted before MachConstantBaseNode.
 1385     ConstantTable& constant_table = C->output()->constant_table();
 1386     constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
 1387   }
 1388 }
 1389 
 1390 uint MachPrologNode::size(PhaseRegAlloc* ra_) const
 1391 {
 1392   assert_cond(ra_ != NULL);
 1393   return MachNode::size(ra_); // too many variables; just compute it
 1394                               // the hard way
 1395 }
 1396 
 1397 int MachPrologNode::reloc() const
 1398 {
 1399   return 0;
 1400 }
 1401 
 1402 //=============================================================================
 1403 
 1404 #ifndef PRODUCT
 1405 void MachEpilogNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
 1406   assert_cond(st != NULL && ra_ != NULL);
 1407   Compile* C = ra_->C;
 1408   assert_cond(C != NULL);
 1409   int framesize = C->output()->frame_size_in_bytes();
 1410 
 1411   st->print("# pop frame %d\n\t", framesize);
 1412 
 1413   if (framesize == 0) {
 1414     st->print("ld  ra, [sp,#%d]\n\t", (2 * wordSize));
 1415     st->print("ld  fp, [sp,#%d]\n\t", (3 * wordSize));
 1416     st->print("add sp, sp, #%d\n\t", (2 * wordSize));
 1417   } else {
 1418     st->print("add  sp, sp, #%d\n\t", framesize);
 1419     st->print("ld  ra, [sp,#%d]\n\t", - 2 * wordSize);
 1420     st->print("ld  fp, [sp,#%d]\n\t", - wordSize);
 1421   }
 1422 
 1423   if (do_polling() && C->is_method_compilation()) {
 1424     st->print("# test polling word\n\t");
 1425     st->print("ld t0, [xthread,#%d]\n\t", in_bytes(JavaThread::polling_word_offset()));
 1426     st->print("bgtu sp, t0, #slow_path");
 1427   }
 1428 }
 1429 #endif
 1430 
 1431 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
 1432   assert_cond(ra_ != NULL);
 1433   Compile* C = ra_->C;
 1434   C2_MacroAssembler _masm(&cbuf);
 1435   assert_cond(C != NULL);
 1436   int framesize = C->output()->frame_size_in_bytes();
 1437 
 1438   __ remove_frame(framesize);
 1439 
 1440   if (StackReservedPages > 0 && C->has_reserved_stack_access()) {
 1441     __ reserved_stack_check();
 1442   }
 1443 
 1444   if (do_polling() && C->is_method_compilation()) {
 1445     Label dummy_label;
 1446     Label* code_stub = &dummy_label;
 1447     if (!C->output()->in_scratch_emit_size()) {
 1448       C2SafepointPollStub* stub = new (C->comp_arena()) C2SafepointPollStub(__ offset());
 1449       C->output()->add_stub(stub);
 1450       code_stub = &stub->entry();
 1451     }
 1452     __ relocate(relocInfo::poll_return_type);
 1453     __ safepoint_poll(*code_stub, true /* at_return */, false /* acquire */, true /* in_nmethod */);
 1454   }
 1455 }
 1456 
 1457 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
 1458   assert_cond(ra_ != NULL);
 1459   // Variable size. Determine dynamically.
 1460   return MachNode::size(ra_);
 1461 }
 1462 
 1463 int MachEpilogNode::reloc() const {
 1464   // Return number of relocatable values contained in this instruction.
 1465   return 1; // 1 for polling page.
 1466 }
 1467 const Pipeline * MachEpilogNode::pipeline() const {
 1468   return MachNode::pipeline_class();
 1469 }
 1470 
 1471 //=============================================================================
 1472 
 1473 // Figure out which register class each belongs in: rc_int, rc_float or
 1474 // rc_stack.
 1475 enum RC { rc_bad, rc_int, rc_float, rc_vector, rc_stack };
 1476 
 1477 static enum RC rc_class(OptoReg::Name reg) {
 1478 
 1479   if (reg == OptoReg::Bad) {
 1480     return rc_bad;
 1481   }
 1482 
 1483   // we have 30 int registers * 2 halves
 1484   // (t0 and t1 are omitted)
 1485   int slots_of_int_registers = Register::max_slots_per_register * (Register::number_of_registers - 2);
 1486   if (reg < slots_of_int_registers) {
 1487     return rc_int;
 1488   }
 1489 
 1490   // we have 32 float register * 2 halves
 1491   int slots_of_float_registers = FloatRegister::max_slots_per_register * FloatRegister::number_of_registers;
 1492   if (reg < slots_of_int_registers + slots_of_float_registers) {
 1493     return rc_float;
 1494   }
 1495 
 1496   // we have 32 vector register * 4 halves
 1497   int slots_of_vector_registers = VectorRegister::max_slots_per_register * VectorRegister::number_of_registers;
 1498   if (reg < slots_of_int_registers + slots_of_float_registers + slots_of_vector_registers) {
 1499     return rc_vector;
 1500   }
 1501 
 1502   // Between vector regs & stack is the flags regs.
 1503   assert(OptoReg::is_stack(reg), "blow up if spilling flags");
 1504 
 1505   return rc_stack;
 1506 }
 1507 
 1508 uint MachSpillCopyNode::implementation(CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream *st) const {
 1509   assert_cond(ra_ != NULL);
 1510   Compile* C = ra_->C;
 1511 
 1512   // Get registers to move.
 1513   OptoReg::Name src_hi = ra_->get_reg_second(in(1));
 1514   OptoReg::Name src_lo = ra_->get_reg_first(in(1));
 1515   OptoReg::Name dst_hi = ra_->get_reg_second(this);
 1516   OptoReg::Name dst_lo = ra_->get_reg_first(this);
 1517 
 1518   enum RC src_hi_rc = rc_class(src_hi);
 1519   enum RC src_lo_rc = rc_class(src_lo);
 1520   enum RC dst_hi_rc = rc_class(dst_hi);
 1521   enum RC dst_lo_rc = rc_class(dst_lo);
 1522 
 1523   assert(src_lo != OptoReg::Bad && dst_lo != OptoReg::Bad, "must move at least 1 register");
 1524 
 1525   if (src_hi != OptoReg::Bad) {
 1526     assert((src_lo & 1) == 0 && src_lo + 1 == src_hi &&
 1527            (dst_lo & 1) == 0 && dst_lo + 1 == dst_hi,
 1528            "expected aligned-adjacent pairs");
 1529   }
 1530 
 1531   if (src_lo == dst_lo && src_hi == dst_hi) {
 1532     return 0;            // Self copy, no move.
 1533   }
 1534 
 1535   bool is64 = (src_lo & 1) == 0 && src_lo + 1 == src_hi &&
 1536               (dst_lo & 1) == 0 && dst_lo + 1 == dst_hi;
 1537   int src_offset = ra_->reg2offset(src_lo);
 1538   int dst_offset = ra_->reg2offset(dst_lo);
 1539 
 1540   if (bottom_type()->isa_vect() != NULL) {
 1541     uint ireg = ideal_reg();
 1542     if (ireg == Op_VecA && cbuf) {
 1543       C2_MacroAssembler _masm(cbuf);
 1544       int vector_reg_size_in_bytes = Matcher::scalable_vector_reg_size(T_BYTE);
 1545       if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
 1546         // stack to stack
 1547         __ spill_copy_vector_stack_to_stack(src_offset, dst_offset,
 1548                                             vector_reg_size_in_bytes);
 1549       } else if (src_lo_rc == rc_vector && dst_lo_rc == rc_stack) {
 1550         // vpr to stack
 1551         __ spill(as_VectorRegister(Matcher::_regEncode[src_lo]), ra_->reg2offset(dst_lo));
 1552       } else if (src_lo_rc == rc_stack && dst_lo_rc == rc_vector) {
 1553         // stack to vpr
 1554         __ unspill(as_VectorRegister(Matcher::_regEncode[dst_lo]), ra_->reg2offset(src_lo));
 1555       } else if (src_lo_rc == rc_vector && dst_lo_rc == rc_vector) {
 1556         // vpr to vpr
 1557         __ vmv1r_v(as_VectorRegister(Matcher::_regEncode[dst_lo]), as_VectorRegister(Matcher::_regEncode[src_lo]));
 1558       } else {
 1559         ShouldNotReachHere();
 1560       }
 1561     }
 1562   } else if (cbuf != NULL) {
 1563     C2_MacroAssembler _masm(cbuf);
 1564     switch (src_lo_rc) {
 1565       case rc_int:
 1566         if (dst_lo_rc == rc_int) {  // gpr --> gpr copy
 1567           if (!is64 && this->ideal_reg() != Op_RegI) { // zero extended for narrow oop or klass
 1568             __ zero_extend(as_Register(Matcher::_regEncode[dst_lo]), as_Register(Matcher::_regEncode[src_lo]), 32);
 1569           } else {
 1570             __ mv(as_Register(Matcher::_regEncode[dst_lo]), as_Register(Matcher::_regEncode[src_lo]));
 1571           }
 1572         } else if (dst_lo_rc == rc_float) { // gpr --> fpr copy
 1573           if (is64) {
 1574             __ fmv_d_x(as_FloatRegister(Matcher::_regEncode[dst_lo]),
 1575                        as_Register(Matcher::_regEncode[src_lo]));
 1576           } else {
 1577             __ fmv_w_x(as_FloatRegister(Matcher::_regEncode[dst_lo]),
 1578                        as_Register(Matcher::_regEncode[src_lo]));
 1579           }
 1580         } else {                    // gpr --> stack spill
 1581           assert(dst_lo_rc == rc_stack, "spill to bad register class");
 1582           __ spill(as_Register(Matcher::_regEncode[src_lo]), is64, dst_offset);
 1583         }
 1584         break;
 1585       case rc_float:
 1586         if (dst_lo_rc == rc_int) {  // fpr --> gpr copy
 1587           if (is64) {
 1588             __ fmv_x_d(as_Register(Matcher::_regEncode[dst_lo]),
 1589                        as_FloatRegister(Matcher::_regEncode[src_lo]));
 1590           } else {
 1591             __ fmv_x_w(as_Register(Matcher::_regEncode[dst_lo]),
 1592                        as_FloatRegister(Matcher::_regEncode[src_lo]));
 1593           }
 1594         } else if (dst_lo_rc == rc_float) { // fpr --> fpr copy
 1595           if (is64) {
 1596             __ fmv_d(as_FloatRegister(Matcher::_regEncode[dst_lo]),
 1597                      as_FloatRegister(Matcher::_regEncode[src_lo]));
 1598           } else {
 1599             __ fmv_s(as_FloatRegister(Matcher::_regEncode[dst_lo]),
 1600                      as_FloatRegister(Matcher::_regEncode[src_lo]));
 1601           }
 1602         } else {                    // fpr --> stack spill
 1603           assert(dst_lo_rc == rc_stack, "spill to bad register class");
 1604           __ spill(as_FloatRegister(Matcher::_regEncode[src_lo]),
 1605                    is64, dst_offset);
 1606         }
 1607         break;
 1608       case rc_stack:
 1609         if (dst_lo_rc == rc_int) {  // stack --> gpr load
 1610           if (this->ideal_reg() == Op_RegI) {
 1611             __ unspill(as_Register(Matcher::_regEncode[dst_lo]), is64, src_offset);
 1612           } else { // // zero extended for narrow oop or klass
 1613             __ unspillu(as_Register(Matcher::_regEncode[dst_lo]), is64, src_offset);
 1614           }
 1615         } else if (dst_lo_rc == rc_float) { // stack --> fpr load
 1616           __ unspill(as_FloatRegister(Matcher::_regEncode[dst_lo]),
 1617                      is64, src_offset);
 1618         } else {                    // stack --> stack copy
 1619           assert(dst_lo_rc == rc_stack, "spill to bad register class");
 1620           if (this->ideal_reg() == Op_RegI) {
 1621             __ unspill(t0, is64, src_offset);
 1622           } else { // zero extended for narrow oop or klass
 1623             __ unspillu(t0, is64, src_offset);
 1624           }
 1625           __ spill(t0, is64, dst_offset);
 1626         }
 1627         break;
 1628       default:
 1629         ShouldNotReachHere();
 1630     }
 1631   }
 1632 
 1633   if (st != NULL) {
 1634     st->print("spill ");
 1635     if (src_lo_rc == rc_stack) {
 1636       st->print("[sp, #%d] -> ", src_offset);
 1637     } else {
 1638       st->print("%s -> ", Matcher::regName[src_lo]);
 1639     }
 1640     if (dst_lo_rc == rc_stack) {
 1641       st->print("[sp, #%d]", dst_offset);
 1642     } else {
 1643       st->print("%s", Matcher::regName[dst_lo]);
 1644     }
 1645     if (bottom_type()->isa_vect() != NULL) {
 1646       int vsize = 0;
 1647       if (ideal_reg() == Op_VecA) {
 1648         vsize = Matcher::scalable_vector_reg_size(T_BYTE) * 8;
 1649       } else {
 1650         ShouldNotReachHere();
 1651       }
 1652       st->print("\t# vector spill size = %d", vsize);
 1653     } else {
 1654       st->print("\t# spill size = %d", is64 ? 64 : 32);
 1655     }
 1656   }
 1657 
 1658   return 0;
 1659 }
 1660 
 1661 #ifndef PRODUCT
 1662 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
 1663   if (ra_ == NULL) {
 1664     st->print("N%d = SpillCopy(N%d)", _idx, in(1)->_idx);
 1665   } else {
 1666     implementation(NULL, ra_, false, st);
 1667   }
 1668 }
 1669 #endif
 1670 
 1671 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
 1672   implementation(&cbuf, ra_, false, NULL);
 1673 }
 1674 
 1675 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
 1676   return MachNode::size(ra_);
 1677 }
 1678 
 1679 //=============================================================================
 1680 
 1681 #ifndef PRODUCT
 1682 void BoxLockNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
 1683   assert_cond(ra_ != NULL && st != NULL);
 1684   int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
 1685   int reg = ra_->get_reg_first(this);
 1686   st->print("add %s, sp, #%d\t# box lock",
 1687             Matcher::regName[reg], offset);
 1688 }
 1689 #endif
 1690 
 1691 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
 1692   C2_MacroAssembler _masm(&cbuf);
 1693   Assembler::IncompressibleRegion ir(&_masm);  // Fixed length: see BoxLockNode::size()
 1694 
 1695   assert_cond(ra_ != NULL);
 1696   int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
 1697   int reg    = ra_->get_encode(this);
 1698 
 1699   if (is_imm_in_range(offset, 12, 0)) {
 1700     __ addi(as_Register(reg), sp, offset);
 1701   } else if (is_imm_in_range(offset, 32, 0)) {
 1702     __ li32(t0, offset);
 1703     __ add(as_Register(reg), sp, t0);
 1704   } else {
 1705     ShouldNotReachHere();
 1706   }
 1707 }
 1708 
 1709 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
 1710   // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_).
 1711   int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
 1712 
 1713   if (is_imm_in_range(offset, 12, 0)) {
 1714     return NativeInstruction::instruction_size;
 1715   } else {
 1716     return 3 * NativeInstruction::instruction_size; // lui + addiw + add;
 1717   }
 1718 }
 1719 
 1720 //=============================================================================
 1721 
 1722 #ifndef PRODUCT
 1723 void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const
 1724 {
 1725   assert_cond(st != NULL);
 1726   st->print_cr("# MachUEPNode");
 1727   if (UseCompressedClassPointers) {
 1728     st->print_cr("\tlwu t0, [j_rarg0, oopDesc::klass_offset_in_bytes()]\t# compressed klass");
 1729     if (CompressedKlassPointers::shift() != 0) {
 1730       st->print_cr("\tdecode_klass_not_null t0, t0");
 1731     }
 1732   } else {
 1733     st->print_cr("\tld t0, [j_rarg0, oopDesc::klass_offset_in_bytes()]\t# compressed klass");
 1734   }
 1735   st->print_cr("\tbeq t0, t1, ic_hit");
 1736   st->print_cr("\tj, SharedRuntime::_ic_miss_stub\t # Inline cache check");
 1737   st->print_cr("\tic_hit:");
 1738 }
 1739 #endif
 1740 
 1741 void MachUEPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
 1742 {
 1743   // This is the unverified entry point.
 1744   C2_MacroAssembler _masm(&cbuf);
 1745 
 1746   Label skip;
 1747   __ cmp_klass(j_rarg0, t1, t0, t2 /* call-clobbered t2 as a tmp */, skip);
 1748   __ far_jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
 1749   __ bind(skip);
 1750 
 1751   // These NOPs are critical so that verified entry point is properly
 1752   // 4 bytes aligned for patching by NativeJump::patch_verified_entry()
 1753   __ align(NativeInstruction::instruction_size);
 1754 }
 1755 
 1756 uint MachUEPNode::size(PhaseRegAlloc* ra_) const
 1757 {
 1758   assert_cond(ra_ != NULL);
 1759   return MachNode::size(ra_);
 1760 }
 1761 
 1762 // REQUIRED EMIT CODE
 1763 
 1764 //=============================================================================
 1765 
 1766 // Emit exception handler code.
 1767 int HandlerImpl::emit_exception_handler(CodeBuffer& cbuf)
 1768 {
 1769   // la_patchable t0, #exception_blob_entry_point
 1770   // jr (offset)t0
 1771   // or
 1772   // j #exception_blob_entry_point
 1773   // Note that the code buffer's insts_mark is always relative to insts.
 1774   // That's why we must use the macroassembler to generate a handler.
 1775   C2_MacroAssembler _masm(&cbuf);
 1776   address base = __ start_a_stub(size_exception_handler());
 1777   if (base == NULL) {
 1778     ciEnv::current()->record_failure("CodeCache is full");
 1779     return 0;  // CodeBuffer::expand failed
 1780   }
 1781   int offset = __ offset();
 1782   __ far_jump(RuntimeAddress(OptoRuntime::exception_blob()->entry_point()));
 1783   assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
 1784   __ end_a_stub();
 1785   return offset;
 1786 }
 1787 
 1788 // Emit deopt handler code.
 1789 int HandlerImpl::emit_deopt_handler(CodeBuffer& cbuf)
 1790 {
 1791   // Note that the code buffer's insts_mark is always relative to insts.
 1792   // That's why we must use the macroassembler to generate a handler.
 1793   C2_MacroAssembler _masm(&cbuf);
 1794   address base = __ start_a_stub(size_deopt_handler());
 1795   if (base == NULL) {
 1796     ciEnv::current()->record_failure("CodeCache is full");
 1797     return 0;  // CodeBuffer::expand failed
 1798   }
 1799   int offset = __ offset();
 1800 
 1801   __ auipc(ra, 0);
 1802   __ far_jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
 1803 
 1804   assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
 1805   __ end_a_stub();
 1806   return offset;
 1807 
 1808 }
 1809 // REQUIRED MATCHER CODE
 1810 
 1811 //=============================================================================
 1812 
 1813 const bool Matcher::match_rule_supported(int opcode) {
 1814   if (!has_match_rule(opcode)) {
 1815     return false;
 1816   }
 1817 
 1818   switch (opcode) {
 1819     case Op_OnSpinWait:
 1820       return VM_Version::supports_on_spin_wait();
 1821     case Op_CacheWB:           // fall through
 1822     case Op_CacheWBPreSync:    // fall through
 1823     case Op_CacheWBPostSync:
 1824       if (!VM_Version::supports_data_cache_line_flush()) {
 1825         return false;
 1826       }
 1827       break;
 1828 
 1829     case Op_StrCompressedCopy: // fall through
 1830     case Op_StrInflatedCopy:   // fall through
 1831     case Op_CountPositives:
 1832       return UseRVV;
 1833 
 1834     case Op_EncodeISOArray:
 1835       return UseRVV && SpecialEncodeISOArray;
 1836 
 1837     case Op_PopCountI:
 1838     case Op_PopCountL:
 1839       return UsePopCountInstruction;
 1840 
 1841     case Op_RotateRight:
 1842     case Op_RotateLeft:
 1843     case Op_CountLeadingZerosI:
 1844     case Op_CountLeadingZerosL:
 1845     case Op_CountTrailingZerosI:
 1846     case Op_CountTrailingZerosL:
 1847       return UseZbb;
 1848 
 1849     case Op_ConvF2HF:
 1850     case Op_ConvHF2F:
 1851       return UseZfhmin;
 1852   }
 1853 
 1854   return true; // Per default match rules are supported.
 1855 }
 1856 
 1857 const bool Matcher::match_rule_supported_superword(int opcode, int vlen, BasicType bt) {
 1858   return match_rule_supported_vector(opcode, vlen, bt);
 1859 }
 1860 
 1861 // Identify extra cases that we might want to provide match rules for vector nodes and
 1862 // other intrinsics guarded with vector length (vlen) and element type (bt).
 1863 const bool Matcher::match_rule_supported_vector(int opcode, int vlen, BasicType bt) {
 1864   if (!match_rule_supported(opcode) || !vector_size_supported(bt, vlen)) {
 1865     return false;
 1866   }
 1867 
 1868   return op_vec_supported(opcode);
 1869 }
 1870 
 1871 const bool Matcher::match_rule_supported_vector_masked(int opcode, int vlen, BasicType bt) {
 1872   return false;
 1873 }
 1874 
 1875 const bool Matcher::vector_needs_partial_operations(Node* node, const TypeVect* vt) {
 1876   return false;
 1877 }
 1878 
 1879 const RegMask* Matcher::predicate_reg_mask(void) {
 1880   return NULL;
 1881 }
 1882 
 1883 const TypeVectMask* Matcher::predicate_reg_type(const Type* elemTy, int length) {
 1884   return NULL;
 1885 }
 1886 
 1887 // Vector calling convention not yet implemented.
 1888 const bool Matcher::supports_vector_calling_convention(void) {
 1889   return false;
 1890 }
 1891 
 1892 OptoRegPair Matcher::vector_return_value(uint ideal_reg) {
 1893   Unimplemented();
 1894   return OptoRegPair(0, 0);
 1895 }
 1896 
 1897 // Is this branch offset short enough that a short branch can be used?
 1898 //
 1899 // NOTE: If the platform does not provide any short branch variants, then
 1900 //       this method should return false for offset 0.
 1901 // |---label(L1)-----|
 1902 // |-----------------|
 1903 // |-----------------|----------eq: float-------------------
 1904 // |-----------------| // far_cmpD_branch   |   cmpD_branch
 1905 // |------- ---------|    feq;              |      feq;
 1906 // |-far_cmpD_branch-|    beqz done;        |      bnez L;
 1907 // |-----------------|    j L;              |
 1908 // |-----------------|    bind(done);       |
 1909 // |-----------------|--------------------------------------
 1910 // |-----------------| // so shortBrSize = br_size - 4;
 1911 // |-----------------| // so offs = offset - shortBrSize + 4;
 1912 // |---label(L2)-----|
 1913 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
 1914   // The passed offset is relative to address of the branch.
 1915   int shortBrSize = br_size - 4;
 1916   int offs = offset - shortBrSize + 4;
 1917   return (-4096 <= offs && offs < 4096);
 1918 }
 1919 
 1920 // Vector width in bytes.
 1921 const int Matcher::vector_width_in_bytes(BasicType bt) {
 1922   if (UseRVV) {
 1923     // The MaxVectorSize should have been set by detecting RVV max vector register size when check UseRVV.
 1924     // MaxVectorSize == VM_Version::_initial_vector_length
 1925     int size = MaxVectorSize;
 1926     // Minimum 2 values in vector
 1927     if (size < 2 * type2aelembytes(bt)) size = 0;
 1928     // But never < 4
 1929     if (size < 4) size = 0;
 1930     return size;
 1931   }
 1932   return 0;
 1933 }
 1934 
 1935 // Limits on vector size (number of elements) loaded into vector.
 1936 const int Matcher::max_vector_size(const BasicType bt) {
 1937   return vector_width_in_bytes(bt) / type2aelembytes(bt);
 1938 }
 1939 
 1940 const int Matcher::min_vector_size(const BasicType bt) {
 1941   int max_size = max_vector_size(bt);
 1942   // Limit the min vector size to 8 bytes.
 1943   int size = 8 / type2aelembytes(bt);
 1944   if (bt == T_BOOLEAN) {
 1945     // To support vector api load/store mask.
 1946     size = 2;
 1947   }
 1948   if (size < 2) size = 2;
 1949   return MIN2(size, max_size);
 1950 }
 1951 
 1952 // Vector ideal reg.
 1953 const uint Matcher::vector_ideal_reg(int len) {
 1954   assert(MaxVectorSize >= len, "");
 1955   if (UseRVV) {
 1956     return Op_VecA;
 1957   }
 1958 
 1959   ShouldNotReachHere();
 1960   return 0;
 1961 }
 1962 
 1963 const int Matcher::scalable_vector_reg_size(const BasicType bt) {
 1964   return Matcher::max_vector_size(bt);
 1965 }
 1966 
 1967 MachOper* Matcher::pd_specialize_generic_vector_operand(MachOper* original_opnd, uint ideal_reg, bool is_temp) {
 1968   ShouldNotReachHere(); // generic vector operands not supported
 1969   return NULL;
 1970 }
 1971 
 1972 bool Matcher::is_reg2reg_move(MachNode* m) {
 1973   ShouldNotReachHere(); // generic vector operands not supported
 1974   return false;
 1975 }
 1976 
 1977 bool Matcher::is_generic_vector(MachOper* opnd) {
 1978   ShouldNotReachHere(); // generic vector operands not supported
 1979   return false;
 1980 }
 1981 
 1982 // Return whether or not this register is ever used as an argument.
 1983 // This function is used on startup to build the trampoline stubs in
 1984 // generateOptoStub.  Registers not mentioned will be killed by the VM
 1985 // call in the trampoline, and arguments in those registers not be
 1986 // available to the callee.
 1987 bool Matcher::can_be_java_arg(int reg)
 1988 {
 1989   return
 1990     reg ==  R10_num || reg == R10_H_num ||
 1991     reg ==  R11_num || reg == R11_H_num ||
 1992     reg ==  R12_num || reg == R12_H_num ||
 1993     reg ==  R13_num || reg == R13_H_num ||
 1994     reg ==  R14_num || reg == R14_H_num ||
 1995     reg ==  R15_num || reg == R15_H_num ||
 1996     reg ==  R16_num || reg == R16_H_num ||
 1997     reg ==  R17_num || reg == R17_H_num ||
 1998     reg ==  F10_num || reg == F10_H_num ||
 1999     reg ==  F11_num || reg == F11_H_num ||
 2000     reg ==  F12_num || reg == F12_H_num ||
 2001     reg ==  F13_num || reg == F13_H_num ||
 2002     reg ==  F14_num || reg == F14_H_num ||
 2003     reg ==  F15_num || reg == F15_H_num ||
 2004     reg ==  F16_num || reg == F16_H_num ||
 2005     reg ==  F17_num || reg == F17_H_num;
 2006 }
 2007 
 2008 bool Matcher::is_spillable_arg(int reg)
 2009 {
 2010   return can_be_java_arg(reg);
 2011 }
 2012 
 2013 uint Matcher::int_pressure_limit()
 2014 {
 2015   // A derived pointer is live at CallNode and then is flagged by RA
 2016   // as a spilled LRG. Spilling heuristics(Spill-USE) explicitly skip
 2017   // derived pointers and lastly fail to spill after reaching maximum
 2018   // number of iterations. Lowering the default pressure threshold to
 2019   // (_NO_SPECIAL_REG32_mask.Size() minus 1) forces CallNode to become
 2020   // a high register pressure area of the code so that split_DEF can
 2021   // generate DefinitionSpillCopy for the derived pointer.
 2022   uint default_int_pressure_threshold = _NO_SPECIAL_REG32_mask.Size() - 1;
 2023   if (!PreserveFramePointer) {
 2024     // When PreserveFramePointer is off, frame pointer is allocatable,
 2025     // but different from other SOC registers, it is excluded from
 2026     // fatproj's mask because its save type is No-Save. Decrease 1 to
 2027     // ensure high pressure at fatproj when PreserveFramePointer is off.
 2028     // See check_pressure_at_fatproj().
 2029     default_int_pressure_threshold--;
 2030   }
 2031   return (INTPRESSURE == -1) ? default_int_pressure_threshold : INTPRESSURE;
 2032 }
 2033 
 2034 uint Matcher::float_pressure_limit()
 2035 {
 2036   // _FLOAT_REG_mask is generated by adlc from the float_reg register class.
 2037   return (FLOATPRESSURE == -1) ? _FLOAT_REG_mask.Size() : FLOATPRESSURE;
 2038 }
 2039 
 2040 bool Matcher::use_asm_for_ldiv_by_con(jlong divisor) {
 2041   return false;
 2042 }
 2043 
 2044 RegMask Matcher::divI_proj_mask() {
 2045   ShouldNotReachHere();
 2046   return RegMask();
 2047 }
 2048 
 2049 // Register for MODI projection of divmodI.
 2050 RegMask Matcher::modI_proj_mask() {
 2051   ShouldNotReachHere();
 2052   return RegMask();
 2053 }
 2054 
 2055 // Register for DIVL projection of divmodL.
 2056 RegMask Matcher::divL_proj_mask() {
 2057   ShouldNotReachHere();
 2058   return RegMask();
 2059 }
 2060 
 2061 // Register for MODL projection of divmodL.
 2062 RegMask Matcher::modL_proj_mask() {
 2063   ShouldNotReachHere();
 2064   return RegMask();
 2065 }
 2066 
 2067 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
 2068   return FP_REG_mask();
 2069 }
 2070 
 2071 bool size_fits_all_mem_uses(AddPNode* addp, int shift) {
 2072   assert_cond(addp != NULL);
 2073   for (DUIterator_Fast imax, i = addp->fast_outs(imax); i < imax; i++) {
 2074     Node* u = addp->fast_out(i);
 2075     if (u != NULL && u->is_Mem()) {
 2076       int opsize = u->as_Mem()->memory_size();
 2077       assert(opsize > 0, "unexpected memory operand size");
 2078       if (u->as_Mem()->memory_size() != (1 << shift)) {
 2079         return false;
 2080       }
 2081     }
 2082   }
 2083   return true;
 2084 }
 2085 
 2086 // Should the Matcher clone input 'm' of node 'n'?
 2087 bool Matcher::pd_clone_node(Node* n, Node* m, Matcher::MStack& mstack) {
 2088   assert_cond(m != NULL);
 2089   if (is_vshift_con_pattern(n, m)) { // ShiftV src (ShiftCntV con)
 2090     mstack.push(m, Visit);           // m = ShiftCntV
 2091     return true;
 2092   }
 2093   return false;
 2094 }
 2095 
 2096 // Should the Matcher clone shifts on addressing modes, expecting them
 2097 // to be subsumed into complex addressing expressions or compute them
 2098 // into registers?
 2099 bool Matcher::pd_clone_address_expressions(AddPNode* m, Matcher::MStack& mstack, VectorSet& address_visited) {
 2100   return clone_base_plus_offset_address(m, mstack, address_visited);
 2101 }
 2102 
 2103 %}
 2104 
 2105 
 2106 
 2107 //----------ENCODING BLOCK-----------------------------------------------------
 2108 // This block specifies the encoding classes used by the compiler to
 2109 // output byte streams.  Encoding classes are parameterized macros
 2110 // used by Machine Instruction Nodes in order to generate the bit
 2111 // encoding of the instruction.  Operands specify their base encoding
 2112 // interface with the interface keyword.  There are currently
 2113 // supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, &
 2114 // COND_INTER.  REG_INTER causes an operand to generate a function
 2115 // which returns its register number when queried.  CONST_INTER causes
 2116 // an operand to generate a function which returns the value of the
 2117 // constant when queried.  MEMORY_INTER causes an operand to generate
 2118 // four functions which return the Base Register, the Index Register,
 2119 // the Scale Value, and the Offset Value of the operand when queried.
 2120 // COND_INTER causes an operand to generate six functions which return
 2121 // the encoding code (ie - encoding bits for the instruction)
 2122 // associated with each basic boolean condition for a conditional
 2123 // instruction.
 2124 //
 2125 // Instructions specify two basic values for encoding.  Again, a
 2126 // function is available to check if the constant displacement is an
 2127 // oop. They use the ins_encode keyword to specify their encoding
 2128 // classes (which must be a sequence of enc_class names, and their
 2129 // parameters, specified in the encoding block), and they use the
 2130 // opcode keyword to specify, in order, their primary, secondary, and
 2131 // tertiary opcode.  Only the opcode sections which a particular
 2132 // instruction needs for encoding need to be specified.
 2133 encode %{
 2134   // BEGIN Non-volatile memory access
 2135 
 2136   enc_class riscv_enc_li_imm(iRegIorL dst, immIorL src) %{
 2137     C2_MacroAssembler _masm(&cbuf);
 2138     int64_t con = (int64_t)$src$$constant;
 2139     Register dst_reg = as_Register($dst$$reg);
 2140     __ mv(dst_reg, con);
 2141   %}
 2142 
 2143   enc_class riscv_enc_mov_p(iRegP dst, immP src) %{
 2144     C2_MacroAssembler _masm(&cbuf);
 2145     Register dst_reg = as_Register($dst$$reg);
 2146     address con = (address)$src$$constant;
 2147     if (con == NULL || con == (address)1) {
 2148       ShouldNotReachHere();
 2149     } else {
 2150       relocInfo::relocType rtype = $src->constant_reloc();
 2151       if (rtype == relocInfo::oop_type) {
 2152         __ movoop(dst_reg, (jobject)con);
 2153       } else if (rtype == relocInfo::metadata_type) {
 2154         __ mov_metadata(dst_reg, (Metadata*)con);
 2155       } else {
 2156         assert(rtype == relocInfo::none, "unexpected reloc type");
 2157         __ mv(dst_reg, $src$$constant);
 2158       }
 2159     }
 2160   %}
 2161 
 2162   enc_class riscv_enc_mov_p1(iRegP dst) %{
 2163     C2_MacroAssembler _masm(&cbuf);
 2164     Register dst_reg = as_Register($dst$$reg);
 2165     __ mv(dst_reg, 1);
 2166   %}
 2167 
 2168   enc_class riscv_enc_mov_byte_map_base(iRegP dst) %{
 2169     C2_MacroAssembler _masm(&cbuf);
 2170     __ load_byte_map_base($dst$$Register);
 2171   %}
 2172 
 2173   enc_class riscv_enc_mov_n(iRegN dst, immN src) %{
 2174     C2_MacroAssembler _masm(&cbuf);
 2175     Register dst_reg = as_Register($dst$$reg);
 2176     address con = (address)$src$$constant;
 2177     if (con == NULL) {
 2178       ShouldNotReachHere();
 2179     } else {
 2180       relocInfo::relocType rtype = $src->constant_reloc();
 2181       assert(rtype == relocInfo::oop_type, "unexpected reloc type");
 2182       __ set_narrow_oop(dst_reg, (jobject)con);
 2183     }
 2184   %}
 2185 
 2186   enc_class riscv_enc_mov_zero(iRegNorP dst) %{
 2187     C2_MacroAssembler _masm(&cbuf);
 2188     Register dst_reg = as_Register($dst$$reg);
 2189     __ mv(dst_reg, zr);
 2190   %}
 2191 
 2192   enc_class riscv_enc_mov_nk(iRegN dst, immNKlass src) %{
 2193     C2_MacroAssembler _masm(&cbuf);
 2194     Register dst_reg = as_Register($dst$$reg);
 2195     address con = (address)$src$$constant;
 2196     if (con == NULL) {
 2197       ShouldNotReachHere();
 2198     } else {
 2199       relocInfo::relocType rtype = $src->constant_reloc();
 2200       assert(rtype == relocInfo::metadata_type, "unexpected reloc type");
 2201       __ set_narrow_klass(dst_reg, (Klass *)con);
 2202     }
 2203   %}
 2204 
 2205   enc_class riscv_enc_cmpxchgw(iRegINoSp res, memory mem, iRegI oldval, iRegI newval) %{
 2206     C2_MacroAssembler _masm(&cbuf);
 2207     __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
 2208                /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
 2209                /*result as bool*/ true);
 2210   %}
 2211 
 2212   enc_class riscv_enc_cmpxchgn(iRegINoSp res, memory mem, iRegI oldval, iRegI newval) %{
 2213     C2_MacroAssembler _masm(&cbuf);
 2214     __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
 2215                /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
 2216                /*result as bool*/ true);
 2217   %}
 2218 
 2219   enc_class riscv_enc_cmpxchg(iRegINoSp res, memory mem, iRegL oldval, iRegL newval) %{
 2220     C2_MacroAssembler _masm(&cbuf);
 2221     __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
 2222                /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
 2223                /*result as bool*/ true);
 2224   %}
 2225 
 2226   enc_class riscv_enc_cmpxchgw_acq(iRegINoSp res, memory mem, iRegI oldval, iRegI newval) %{
 2227     C2_MacroAssembler _masm(&cbuf);
 2228     __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
 2229                /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
 2230                /*result as bool*/ true);
 2231   %}
 2232 
 2233   enc_class riscv_enc_cmpxchgn_acq(iRegINoSp res, memory mem, iRegI oldval, iRegI newval) %{
 2234     C2_MacroAssembler _masm(&cbuf);
 2235     __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
 2236                /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
 2237                /*result as bool*/ true);
 2238   %}
 2239 
 2240   enc_class riscv_enc_cmpxchg_acq(iRegINoSp res, memory mem, iRegL oldval, iRegL newval) %{
 2241     C2_MacroAssembler _masm(&cbuf);
 2242     __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
 2243                /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
 2244                /*result as bool*/ true);
 2245   %}
 2246 
 2247   // compare and branch instruction encodings
 2248 
 2249   enc_class riscv_enc_j(label lbl) %{
 2250     C2_MacroAssembler _masm(&cbuf);
 2251     Label* L = $lbl$$label;
 2252     __ j(*L);
 2253   %}
 2254 
 2255   enc_class riscv_enc_far_cmpULtGe_imm0_branch(cmpOpULtGe cmp, iRegIorL op1, label lbl) %{
 2256     C2_MacroAssembler _masm(&cbuf);
 2257     Label* L = $lbl$$label;
 2258     switch ($cmp$$cmpcode) {
 2259       case(BoolTest::ge):
 2260         __ j(*L);
 2261         break;
 2262       case(BoolTest::lt):
 2263         break;
 2264       default:
 2265         Unimplemented();
 2266     }
 2267   %}
 2268 
 2269   // call instruction encodings
 2270 
 2271   enc_class riscv_enc_partial_subtype_check(iRegP sub, iRegP super, iRegP temp, iRegP result) %{
 2272     Register sub_reg = as_Register($sub$$reg);
 2273     Register super_reg = as_Register($super$$reg);
 2274     Register temp_reg = as_Register($temp$$reg);
 2275     Register result_reg = as_Register($result$$reg);
 2276     Register cr_reg = t1;
 2277 
 2278     Label miss;
 2279     Label done;
 2280     C2_MacroAssembler _masm(&cbuf);
 2281     __ check_klass_subtype_slow_path(sub_reg, super_reg, temp_reg, result_reg,
 2282                                      NULL, &miss);
 2283     if ($primary) {
 2284       __ mv(result_reg, zr);
 2285     } else {
 2286       __ mv(cr_reg, zr);
 2287       __ j(done);
 2288     }
 2289 
 2290     __ bind(miss);
 2291     if (!$primary) {
 2292       __ mv(cr_reg, 1);
 2293     }
 2294 
 2295     __ bind(done);
 2296   %}
 2297 
 2298   enc_class riscv_enc_java_static_call(method meth) %{
 2299     C2_MacroAssembler _masm(&cbuf);
 2300     Assembler::IncompressibleRegion ir(&_masm);  // Fixed length: see ret_addr_offset
 2301 
 2302     address addr = (address)$meth$$method;
 2303     address call = NULL;
 2304     assert_cond(addr != NULL);
 2305     if (!_method) {
 2306       // A call to a runtime wrapper, e.g. new, new_typeArray_Java, uncommon_trap.
 2307       call = __ trampoline_call(Address(addr, relocInfo::runtime_call_type));
 2308       if (call == NULL) {
 2309         ciEnv::current()->record_failure("CodeCache is full");
 2310         return;
 2311       }
 2312     } else {
 2313       int method_index = resolved_method_index(cbuf);
 2314       RelocationHolder rspec = _optimized_virtual ? opt_virtual_call_Relocation::spec(method_index)
 2315                                                   : static_call_Relocation::spec(method_index);
 2316       call = __ trampoline_call(Address(addr, rspec));
 2317       if (call == NULL) {
 2318         ciEnv::current()->record_failure("CodeCache is full");
 2319         return;
 2320       }
 2321 
 2322       if (CodeBuffer::supports_shared_stubs() && _method->can_be_statically_bound()) {
 2323         // Calls of the same statically bound method can share
 2324         // a stub to the interpreter.
 2325         cbuf.shared_stub_to_interp_for(_method, call - cbuf.insts_begin());
 2326       } else {
 2327         // Emit stub for static call
 2328         address stub = CompiledStaticCall::emit_to_interp_stub(cbuf, call);
 2329         if (stub == NULL) {
 2330           ciEnv::current()->record_failure("CodeCache is full");
 2331           return;
 2332         }
 2333       }
 2334     }
 2335 
 2336     __ post_call_nop();
 2337   %}
 2338 
 2339   enc_class riscv_enc_java_dynamic_call(method meth) %{
 2340     C2_MacroAssembler _masm(&cbuf);
 2341     Assembler::IncompressibleRegion ir(&_masm);  // Fixed length: see ret_addr_offset
 2342     int method_index = resolved_method_index(cbuf);
 2343     address call = __ ic_call((address)$meth$$method, method_index);
 2344     if (call == NULL) {
 2345       ciEnv::current()->record_failure("CodeCache is full");
 2346       return;
 2347     }
 2348 
 2349     __ post_call_nop();
 2350   %}
 2351 
 2352   enc_class riscv_enc_call_epilog() %{
 2353     C2_MacroAssembler _masm(&cbuf);
 2354     if (VerifyStackAtCalls) {
 2355       // Check that stack depth is unchanged: find majik cookie on stack
 2356       __ call_Unimplemented();
 2357     }
 2358   %}
 2359 
 2360   enc_class riscv_enc_java_to_runtime(method meth) %{
 2361     C2_MacroAssembler _masm(&cbuf);
 2362     Assembler::IncompressibleRegion ir(&_masm);  // Fixed length: see ret_addr_offset
 2363 
 2364     // some calls to generated routines (arraycopy code) are scheduled
 2365     // by C2 as runtime calls. if so we can call them using a jr (they
 2366     // will be in a reachable segment) otherwise we have to use a jalr
 2367     // which loads the absolute address into a register.
 2368     address entry = (address)$meth$$method;
 2369     CodeBlob *cb = CodeCache::find_blob(entry);
 2370     if (cb != NULL) {
 2371       address call = __ trampoline_call(Address(entry, relocInfo::runtime_call_type));
 2372       if (call == NULL) {
 2373         ciEnv::current()->record_failure("CodeCache is full");
 2374         return;
 2375       }
 2376       __ post_call_nop();
 2377     } else {
 2378       Label retaddr;
 2379       __ la(t1, retaddr);
 2380       __ la(t0, RuntimeAddress(entry));
 2381       // Leave a breadcrumb for JavaFrameAnchor::capture_last_Java_pc()
 2382       __ addi(sp, sp, -2 * wordSize);
 2383       __ sd(t1, Address(sp, wordSize));
 2384       __ jalr(t0);
 2385       __ bind(retaddr);
 2386       __ post_call_nop();
 2387       __ addi(sp, sp, 2 * wordSize);
 2388     }
 2389   %}
 2390 
 2391   // using the cr register as the bool result: 0 for success; others failed.
 2392   enc_class riscv_enc_fast_lock(iRegP object, iRegP box, iRegPNoSp tmp1, iRegPNoSp tmp2) %{
 2393     C2_MacroAssembler _masm(&cbuf);
 2394     Register flag = t1;
 2395     Register oop = as_Register($object$$reg);
 2396     Register box = as_Register($box$$reg);
 2397     Register disp_hdr = as_Register($tmp1$$reg);
 2398     Register tmp = as_Register($tmp2$$reg);
 2399     Label cont;
 2400     Label object_has_monitor;
 2401     Label no_count;
 2402 
 2403     assert_different_registers(oop, box, tmp, disp_hdr, t0);
 2404 
 2405     // Load markWord from object into displaced_header.
 2406     __ ld(disp_hdr, Address(oop, oopDesc::mark_offset_in_bytes()));
 2407 
 2408     if (DiagnoseSyncOnValueBasedClasses != 0) {
 2409       __ load_klass(flag, oop);
 2410       __ lwu(flag, Address(flag, Klass::access_flags_offset()));
 2411       __ andi(flag, flag, JVM_ACC_IS_VALUE_BASED_CLASS, tmp /* tmp */);
 2412       __ bnez(flag, cont, true /* is_far */);
 2413     }
 2414 
 2415     // Check for existing monitor
 2416     __ andi(t0, disp_hdr, markWord::monitor_value);
 2417     __ bnez(t0, object_has_monitor);
 2418 
 2419     if (!UseHeavyMonitors) {
 2420       // Set tmp to be (markWord of object | UNLOCK_VALUE).
 2421       __ ori(tmp, disp_hdr, markWord::unlocked_value);
 2422 
 2423       // Initialize the box. (Must happen before we update the object mark!)
 2424       __ sd(tmp, Address(box, BasicLock::displaced_header_offset_in_bytes()));
 2425 
 2426       // Compare object markWord with an unlocked value (tmp) and if
 2427       // equal exchange the stack address of our box with object markWord.
 2428       // On failure disp_hdr contains the possibly locked markWord.
 2429       __ cmpxchg(/*memory address*/oop, /*expected value*/tmp, /*new value*/box, Assembler::int64, Assembler::aq,
 2430                  Assembler::rl, /*result*/disp_hdr);
 2431       __ mv(flag, zr);
 2432       __ beq(disp_hdr, tmp, cont); // prepare zero flag and goto cont if we won the cas
 2433 
 2434       assert(oopDesc::mark_offset_in_bytes() == 0, "offset of _mark is not 0");
 2435 
 2436       // If the compare-and-exchange succeeded, then we found an unlocked
 2437       // object, will have now locked it will continue at label cont
 2438       // We did not see an unlocked object so try the fast recursive case.
 2439 
 2440       // Check if the owner is self by comparing the value in the
 2441       // markWord of object (disp_hdr) with the stack pointer.
 2442       __ sub(disp_hdr, disp_hdr, sp);
 2443       __ mv(tmp, (intptr_t) (~(os::vm_page_size()-1) | (uintptr_t)markWord::lock_mask_in_place));
 2444       // If (mark & lock_mask) == 0 and mark - sp < page_size, we are stack-locking and goto cont,
 2445       // hence we can store 0 as the displaced header in the box, which indicates that it is a
 2446       // recursive lock.
 2447       __ andr(tmp/*==0?*/, disp_hdr, tmp);
 2448       __ sd(tmp/*==0, perhaps*/, Address(box, BasicLock::displaced_header_offset_in_bytes()));
 2449       __ mv(flag, tmp); // we can use the value of tmp as the result here
 2450     } else {
 2451       __ mv(flag, 1); // Set non-zero flag to indicate 'failure' -> take slow-path
 2452     }
 2453 
 2454     __ j(cont);
 2455 
 2456     // Handle existing monitor.
 2457     __ bind(object_has_monitor);
 2458     // The object's monitor m is unlocked iff m->owner == NULL,
 2459     // otherwise m->owner may contain a thread or a stack address.
 2460     //
 2461     // Try to CAS m->owner from NULL to current thread.
 2462     __ add(tmp, disp_hdr, (ObjectMonitor::owner_offset_in_bytes() - markWord::monitor_value));
 2463     __ cmpxchg(/*memory address*/tmp, /*expected value*/zr, /*new value*/xthread, Assembler::int64, Assembler::aq,
 2464              Assembler::rl, /*result*/flag); // cas succeeds if flag == zr(expected)
 2465 
 2466     // Store a non-null value into the box to avoid looking like a re-entrant
 2467     // lock. The fast-path monitor unlock code checks for
 2468     // markWord::monitor_value so use markWord::unused_mark which has the
 2469     // relevant bit set, and also matches ObjectSynchronizer::slow_enter.
 2470     __ mv(tmp, (address)markWord::unused_mark().value());
 2471     __ sd(tmp, Address(box, BasicLock::displaced_header_offset_in_bytes()));
 2472 
 2473     __ beqz(flag, cont); // CAS success means locking succeeded
 2474 
 2475     __ bne(flag, xthread, cont); // Check for recursive locking
 2476 
 2477     // Recursive lock case
 2478     __ mv(flag, zr);
 2479     __ increment(Address(disp_hdr, ObjectMonitor::recursions_offset_in_bytes() - markWord::monitor_value), 1, t0, tmp);
 2480 
 2481     __ bind(cont);
 2482 
 2483     __ bnez(flag, no_count);
 2484 
 2485     __ increment(Address(xthread, JavaThread::held_monitor_count_offset()), 1, t0, tmp);
 2486 
 2487     __ bind(no_count);
 2488   %}
 2489 
 2490   // using cr flag to indicate the fast_unlock result: 0 for success; others failed.
 2491   enc_class riscv_enc_fast_unlock(iRegP object, iRegP box, iRegPNoSp tmp1, iRegPNoSp tmp2) %{
 2492     C2_MacroAssembler _masm(&cbuf);
 2493     Register flag = t1;
 2494     Register oop = as_Register($object$$reg);
 2495     Register box = as_Register($box$$reg);
 2496     Register disp_hdr = as_Register($tmp1$$reg);
 2497     Register tmp = as_Register($tmp2$$reg);
 2498     Label cont;
 2499     Label object_has_monitor;
 2500     Label no_count;
 2501 
 2502     assert_different_registers(oop, box, tmp, disp_hdr, flag);
 2503 
 2504     if (!UseHeavyMonitors) {
 2505       // Find the lock address and load the displaced header from the stack.
 2506       __ ld(disp_hdr, Address(box, BasicLock::displaced_header_offset_in_bytes()));
 2507 
 2508       // If the displaced header is 0, we have a recursive unlock.
 2509       __ mv(flag, disp_hdr);
 2510       __ beqz(disp_hdr, cont);
 2511     }
 2512 
 2513     // Handle existing monitor.
 2514     __ ld(tmp, Address(oop, oopDesc::mark_offset_in_bytes()));
 2515     __ andi(t0, tmp, markWord::monitor_value);
 2516     __ bnez(t0, object_has_monitor);
 2517 
 2518     if (!UseHeavyMonitors) {
 2519       // Check if it is still a light weight lock, this is true if we
 2520       // see the stack address of the basicLock in the markWord of the
 2521       // object.
 2522 
 2523       __ cmpxchg(/*memory address*/oop, /*expected value*/box, /*new value*/disp_hdr, Assembler::int64, Assembler::relaxed,
 2524                  Assembler::rl, /*result*/tmp);
 2525       __ xorr(flag, box, tmp); // box == tmp if cas succeeds
 2526     } else {
 2527       __ mv(flag, 1); // Set non-zero flag to indicate 'failure' -> take slow path
 2528     }
 2529     __ j(cont);
 2530 
 2531     assert(oopDesc::mark_offset_in_bytes() == 0, "offset of _mark is not 0");
 2532 
 2533     // Handle existing monitor.
 2534     __ bind(object_has_monitor);
 2535     STATIC_ASSERT(markWord::monitor_value <= INT_MAX);
 2536     __ add(tmp, tmp, -(int)markWord::monitor_value); // monitor
 2537     __ ld(disp_hdr, Address(tmp, ObjectMonitor::recursions_offset_in_bytes()));
 2538 
 2539     Label notRecursive;
 2540     __ beqz(disp_hdr, notRecursive); // Will be 0 if not recursive.
 2541 
 2542     // Recursive lock
 2543     __ addi(disp_hdr, disp_hdr, -1);
 2544     __ sd(disp_hdr, Address(tmp, ObjectMonitor::recursions_offset_in_bytes()));
 2545     __ mv(flag, zr);
 2546     __ j(cont);
 2547 
 2548     __ bind(notRecursive);
 2549     __ ld(flag, Address(tmp, ObjectMonitor::EntryList_offset_in_bytes()));
 2550     __ ld(disp_hdr, Address(tmp, ObjectMonitor::cxq_offset_in_bytes()));
 2551     __ orr(flag, flag, disp_hdr); // Will be 0 if both are 0.
 2552     __ bnez(flag, cont);
 2553     // need a release store here
 2554     __ la(tmp, Address(tmp, ObjectMonitor::owner_offset_in_bytes()));
 2555     __ membar(MacroAssembler::LoadStore | MacroAssembler::StoreStore);
 2556     __ sd(zr, Address(tmp)); // set unowned
 2557 
 2558     __ bind(cont);
 2559 
 2560     __ bnez(flag, no_count);
 2561 
 2562     __ decrement(Address(xthread, JavaThread::held_monitor_count_offset()), 1, t0, tmp);
 2563 
 2564     __ bind(no_count);
 2565   %}
 2566 
 2567   // arithmetic encodings
 2568 
 2569   enc_class riscv_enc_divw(iRegI dst, iRegI src1, iRegI src2) %{
 2570     C2_MacroAssembler _masm(&cbuf);
 2571     Register dst_reg = as_Register($dst$$reg);
 2572     Register src1_reg = as_Register($src1$$reg);
 2573     Register src2_reg = as_Register($src2$$reg);
 2574     __ corrected_idivl(dst_reg, src1_reg, src2_reg, false);
 2575   %}
 2576 
 2577   enc_class riscv_enc_div(iRegI dst, iRegI src1, iRegI src2) %{
 2578     C2_MacroAssembler _masm(&cbuf);
 2579     Register dst_reg = as_Register($dst$$reg);
 2580     Register src1_reg = as_Register($src1$$reg);
 2581     Register src2_reg = as_Register($src2$$reg);
 2582     __ corrected_idivq(dst_reg, src1_reg, src2_reg, false);
 2583   %}
 2584 
 2585   enc_class riscv_enc_modw(iRegI dst, iRegI src1, iRegI src2) %{
 2586     C2_MacroAssembler _masm(&cbuf);
 2587     Register dst_reg = as_Register($dst$$reg);
 2588     Register src1_reg = as_Register($src1$$reg);
 2589     Register src2_reg = as_Register($src2$$reg);
 2590     __ corrected_idivl(dst_reg, src1_reg, src2_reg, true);
 2591   %}
 2592 
 2593   enc_class riscv_enc_mod(iRegI dst, iRegI src1, iRegI src2) %{
 2594     C2_MacroAssembler _masm(&cbuf);
 2595     Register dst_reg = as_Register($dst$$reg);
 2596     Register src1_reg = as_Register($src1$$reg);
 2597     Register src2_reg = as_Register($src2$$reg);
 2598     __ corrected_idivq(dst_reg, src1_reg, src2_reg, true);
 2599   %}
 2600 
 2601   enc_class riscv_enc_tail_call(iRegP jump_target) %{
 2602     C2_MacroAssembler _masm(&cbuf);
 2603     Register target_reg = as_Register($jump_target$$reg);
 2604     __ jr(target_reg);
 2605   %}
 2606 
 2607   enc_class riscv_enc_tail_jmp(iRegP jump_target) %{
 2608     C2_MacroAssembler _masm(&cbuf);
 2609     Register target_reg = as_Register($jump_target$$reg);
 2610     // exception oop should be in x10
 2611     // ret addr has been popped into ra
 2612     // callee expects it in x13
 2613     __ mv(x13, ra);
 2614     __ jr(target_reg);
 2615   %}
 2616 
 2617   enc_class riscv_enc_rethrow() %{
 2618     C2_MacroAssembler _masm(&cbuf);
 2619     __ far_jump(RuntimeAddress(OptoRuntime::rethrow_stub()));
 2620   %}
 2621 
 2622   enc_class riscv_enc_ret() %{
 2623     C2_MacroAssembler _masm(&cbuf);
 2624     __ ret();
 2625   %}
 2626 
 2627 %}
 2628 
 2629 //----------FRAME--------------------------------------------------------------
 2630 // Definition of frame structure and management information.
 2631 //
 2632 //  S T A C K   L A Y O U T    Allocators stack-slot number
 2633 //                             |   (to get allocators register number
 2634 //  G  Owned by    |        |  v    add OptoReg::stack0())
 2635 //  r   CALLER     |        |
 2636 //  o     |        +--------+      pad to even-align allocators stack-slot
 2637 //  w     V        |  pad0  |        numbers; owned by CALLER
 2638 //  t   -----------+--------+----> Matcher::_in_arg_limit, unaligned
 2639 //  h     ^        |   in   |  5
 2640 //        |        |  args  |  4   Holes in incoming args owned by SELF
 2641 //  |     |        |        |  3
 2642 //  |     |        +--------+
 2643 //  V     |        | old out|      Empty on Intel, window on Sparc
 2644 //        |    old |preserve|      Must be even aligned.
 2645 //        |     SP-+--------+----> Matcher::_old_SP, even aligned
 2646 //        |        |   in   |  3   area for Intel ret address
 2647 //     Owned by    |preserve|      Empty on Sparc.
 2648 //       SELF      +--------+
 2649 //        |        |  pad2  |  2   pad to align old SP
 2650 //        |        +--------+  1
 2651 //        |        | locks  |  0
 2652 //        |        +--------+----> OptoReg::stack0(), even aligned
 2653 //        |        |  pad1  | 11   pad to align new SP
 2654 //        |        +--------+
 2655 //        |        |        | 10
 2656 //        |        | spills |  9   spills
 2657 //        V        |        |  8   (pad0 slot for callee)
 2658 //      -----------+--------+----> Matcher::_out_arg_limit, unaligned
 2659 //        ^        |  out   |  7
 2660 //        |        |  args  |  6   Holes in outgoing args owned by CALLEE
 2661 //     Owned by    +--------+
 2662 //      CALLEE     | new out|  6   Empty on Intel, window on Sparc
 2663 //        |    new |preserve|      Must be even-aligned.
 2664 //        |     SP-+--------+----> Matcher::_new_SP, even aligned
 2665 //        |        |        |
 2666 //
 2667 // Note 1: Only region 8-11 is determined by the allocator.  Region 0-5 is
 2668 //         known from SELF's arguments and the Java calling convention.
 2669 //         Region 6-7 is determined per call site.
 2670 // Note 2: If the calling convention leaves holes in the incoming argument
 2671 //         area, those holes are owned by SELF.  Holes in the outgoing area
 2672 //         are owned by the CALLEE.  Holes should not be necessary in the
 2673 //         incoming area, as the Java calling convention is completely under
 2674 //         the control of the AD file.  Doubles can be sorted and packed to
 2675 //         avoid holes.  Holes in the outgoing arguments may be necessary for
 2676 //         varargs C calling conventions.
 2677 // Note 3: Region 0-3 is even aligned, with pad2 as needed.  Region 3-5 is
 2678 //         even aligned with pad0 as needed.
 2679 //         Region 6 is even aligned.  Region 6-7 is NOT even aligned;
 2680 //           (the latter is true on Intel but is it false on RISCV?)
 2681 //         region 6-11 is even aligned; it may be padded out more so that
 2682 //         the region from SP to FP meets the minimum stack alignment.
 2683 // Note 4: For I2C adapters, the incoming FP may not meet the minimum stack
 2684 //         alignment.  Region 11, pad1, may be dynamically extended so that
 2685 //         SP meets the minimum alignment.
 2686 
 2687 frame %{
 2688   // These three registers define part of the calling convention
 2689   // between compiled code and the interpreter.
 2690 
 2691   // Inline Cache Register or methodOop for I2C.
 2692   inline_cache_reg(R31);
 2693 
 2694   // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
 2695   cisc_spilling_operand_name(indOffset);
 2696 
 2697   // Number of stack slots consumed by locking an object
 2698   // generate Compile::sync_stack_slots
 2699   // VMRegImpl::slots_per_word = wordSize / stack_slot_size = 8 / 4 = 2
 2700   sync_stack_slots(1 * VMRegImpl::slots_per_word);
 2701 
 2702   // Compiled code's Frame Pointer
 2703   frame_pointer(R2);
 2704 
 2705   // Interpreter stores its frame pointer in a register which is
 2706   // stored to the stack by I2CAdaptors.
 2707   // I2CAdaptors convert from interpreted java to compiled java.
 2708   interpreter_frame_pointer(R8);
 2709 
 2710   // Stack alignment requirement
 2711   stack_alignment(StackAlignmentInBytes); // Alignment size in bytes (128-bit -> 16 bytes)
 2712 
 2713   // Number of outgoing stack slots killed above the out_preserve_stack_slots
 2714   // for calls to C.  Supports the var-args backing area for register parms.
 2715   varargs_C_out_slots_killed(frame::arg_reg_save_area_bytes / BytesPerInt);
 2716 
 2717   // The after-PROLOG location of the return address.  Location of
 2718   // return address specifies a type (REG or STACK) and a number
 2719   // representing the register number (i.e. - use a register name) or
 2720   // stack slot.
 2721   // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
 2722   // Otherwise, it is above the locks and verification slot and alignment word
 2723   // TODO this may well be correct but need to check why that - 2 is there
 2724   // ppc port uses 0 but we definitely need to allow for fixed_slots
 2725   // which folds in the space used for monitors
 2726   return_addr(STACK - 2 +
 2727               align_up((Compile::current()->in_preserve_stack_slots() +
 2728                         Compile::current()->fixed_slots()),
 2729                        stack_alignment_in_slots()));
 2730 
 2731   // Location of compiled Java return values.  Same as C for now.
 2732   return_value
 2733   %{
 2734     assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL,
 2735            "only return normal values");
 2736 
 2737     static const int lo[Op_RegL + 1] = { // enum name
 2738       0,                                 // Op_Node
 2739       0,                                 // Op_Set
 2740       R10_num,                           // Op_RegN
 2741       R10_num,                           // Op_RegI
 2742       R10_num,                           // Op_RegP
 2743       F10_num,                           // Op_RegF
 2744       F10_num,                           // Op_RegD
 2745       R10_num                            // Op_RegL
 2746     };
 2747 
 2748     static const int hi[Op_RegL + 1] = { // enum name
 2749       0,                                 // Op_Node
 2750       0,                                 // Op_Set
 2751       OptoReg::Bad,                      // Op_RegN
 2752       OptoReg::Bad,                      // Op_RegI
 2753       R10_H_num,                         // Op_RegP
 2754       OptoReg::Bad,                      // Op_RegF
 2755       F10_H_num,                         // Op_RegD
 2756       R10_H_num                          // Op_RegL
 2757     };
 2758 
 2759     return OptoRegPair(hi[ideal_reg], lo[ideal_reg]);
 2760   %}
 2761 %}
 2762 
 2763 //----------ATTRIBUTES---------------------------------------------------------
 2764 //----------Operand Attributes-------------------------------------------------
 2765 op_attrib op_cost(1);        // Required cost attribute
 2766 
 2767 //----------Instruction Attributes---------------------------------------------
 2768 ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute
 2769 ins_attrib ins_size(32);        // Required size attribute (in bits)
 2770 ins_attrib ins_short_branch(0); // Required flag: is this instruction
 2771                                 // a non-matching short branch variant
 2772                                 // of some long branch?
 2773 ins_attrib ins_alignment(4);    // Required alignment attribute (must
 2774                                 // be a power of 2) specifies the
 2775                                 // alignment that some part of the
 2776                                 // instruction (not necessarily the
 2777                                 // start) requires.  If > 1, a
 2778                                 // compute_padding() function must be
 2779                                 // provided for the instruction
 2780 
 2781 //----------OPERANDS-----------------------------------------------------------
 2782 // Operand definitions must precede instruction definitions for correct parsing
 2783 // in the ADLC because operands constitute user defined types which are used in
 2784 // instruction definitions.
 2785 
 2786 //----------Simple Operands----------------------------------------------------
 2787 
 2788 // Integer operands 32 bit
 2789 // 32 bit immediate
 2790 operand immI()
 2791 %{
 2792   match(ConI);
 2793 
 2794   op_cost(0);
 2795   format %{ %}
 2796   interface(CONST_INTER);
 2797 %}
 2798 
 2799 // 32 bit zero
 2800 operand immI0()
 2801 %{
 2802   predicate(n->get_int() == 0);
 2803   match(ConI);
 2804 
 2805   op_cost(0);
 2806   format %{ %}
 2807   interface(CONST_INTER);
 2808 %}
 2809 
 2810 // 32 bit unit increment
 2811 operand immI_1()
 2812 %{
 2813   predicate(n->get_int() == 1);
 2814   match(ConI);
 2815 
 2816   op_cost(0);
 2817   format %{ %}
 2818   interface(CONST_INTER);
 2819 %}
 2820 
 2821 // 32 bit unit decrement
 2822 operand immI_M1()
 2823 %{
 2824   predicate(n->get_int() == -1);
 2825   match(ConI);
 2826 
 2827   op_cost(0);
 2828   format %{ %}
 2829   interface(CONST_INTER);
 2830 %}
 2831 
 2832 // Unsigned Integer Immediate:  6-bit int, greater than 32
 2833 operand uimmI6_ge32() %{
 2834   predicate(((unsigned int)(n->get_int()) < 64) && (n->get_int() >= 32));
 2835   match(ConI);
 2836   op_cost(0);
 2837   format %{ %}
 2838   interface(CONST_INTER);
 2839 %}
 2840 
 2841 operand immI_le_4()
 2842 %{
 2843   predicate(n->get_int() <= 4);
 2844   match(ConI);
 2845 
 2846   op_cost(0);
 2847   format %{ %}
 2848   interface(CONST_INTER);
 2849 %}
 2850 
 2851 operand immI_16()
 2852 %{
 2853   predicate(n->get_int() == 16);
 2854   match(ConI);
 2855   op_cost(0);
 2856   format %{ %}
 2857   interface(CONST_INTER);
 2858 %}
 2859 
 2860 operand immI_24()
 2861 %{
 2862   predicate(n->get_int() == 24);
 2863   match(ConI);
 2864   op_cost(0);
 2865   format %{ %}
 2866   interface(CONST_INTER);
 2867 %}
 2868 
 2869 operand immI_31()
 2870 %{
 2871   predicate(n->get_int() == 31);
 2872   match(ConI);
 2873 
 2874   op_cost(0);
 2875   format %{ %}
 2876   interface(CONST_INTER);
 2877 %}
 2878 
 2879 operand immI_63()
 2880 %{
 2881   predicate(n->get_int() == 63);
 2882   match(ConI);
 2883 
 2884   op_cost(0);
 2885   format %{ %}
 2886   interface(CONST_INTER);
 2887 %}
 2888 
 2889 // 32 bit integer valid for add immediate
 2890 operand immIAdd()
 2891 %{
 2892   predicate(Assembler::operand_valid_for_add_immediate((int64_t)n->get_int()));
 2893   match(ConI);
 2894   op_cost(0);
 2895   format %{ %}
 2896   interface(CONST_INTER);
 2897 %}
 2898 
 2899 // 32 bit integer valid for sub immediate
 2900 operand immISub()
 2901 %{
 2902   predicate(Assembler::operand_valid_for_add_immediate(-(int64_t)n->get_int()));
 2903   match(ConI);
 2904   op_cost(0);
 2905   format %{ %}
 2906   interface(CONST_INTER);
 2907 %}
 2908 
 2909 // 5 bit signed value.
 2910 operand immI5()
 2911 %{
 2912   predicate(n->get_int() <= 15 && n->get_int() >= -16);
 2913   match(ConI);
 2914 
 2915   op_cost(0);
 2916   format %{ %}
 2917   interface(CONST_INTER);
 2918 %}
 2919 
 2920 // 5 bit signed value (simm5)
 2921 operand immL5()
 2922 %{
 2923   predicate(n->get_long() <= 15 && n->get_long() >= -16);
 2924   match(ConL);
 2925 
 2926   op_cost(0);
 2927   format %{ %}
 2928   interface(CONST_INTER);
 2929 %}
 2930 
 2931 // Integer operands 64 bit
 2932 // 64 bit immediate
 2933 operand immL()
 2934 %{
 2935   match(ConL);
 2936 
 2937   op_cost(0);
 2938   format %{ %}
 2939   interface(CONST_INTER);
 2940 %}
 2941 
 2942 // 64 bit zero
 2943 operand immL0()
 2944 %{
 2945   predicate(n->get_long() == 0);
 2946   match(ConL);
 2947 
 2948   op_cost(0);
 2949   format %{ %}
 2950   interface(CONST_INTER);
 2951 %}
 2952 
 2953 // Pointer operands
 2954 // Pointer Immediate
 2955 operand immP()
 2956 %{
 2957   match(ConP);
 2958 
 2959   op_cost(0);
 2960   format %{ %}
 2961   interface(CONST_INTER);
 2962 %}
 2963 
 2964 // NULL Pointer Immediate
 2965 operand immP0()
 2966 %{
 2967   predicate(n->get_ptr() == 0);
 2968   match(ConP);
 2969 
 2970   op_cost(0);
 2971   format %{ %}
 2972   interface(CONST_INTER);
 2973 %}
 2974 
 2975 // Pointer Immediate One
 2976 // this is used in object initialization (initial object header)
 2977 operand immP_1()
 2978 %{
 2979   predicate(n->get_ptr() == 1);
 2980   match(ConP);
 2981 
 2982   op_cost(0);
 2983   format %{ %}
 2984   interface(CONST_INTER);
 2985 %}
 2986 
 2987 // Card Table Byte Map Base
 2988 operand immByteMapBase()
 2989 %{
 2990   // Get base of card map
 2991   predicate(BarrierSet::barrier_set()->is_a(BarrierSet::CardTableBarrierSet) &&
 2992             (CardTable::CardValue*)n->get_ptr() ==
 2993              ((CardTableBarrierSet*)(BarrierSet::barrier_set()))->card_table()->byte_map_base());
 2994   match(ConP);
 2995 
 2996   op_cost(0);
 2997   format %{ %}
 2998   interface(CONST_INTER);
 2999 %}
 3000 
 3001 // Int Immediate: low 16-bit mask
 3002 operand immI_16bits()
 3003 %{
 3004   predicate(n->get_int() == 0xFFFF);
 3005   match(ConI);
 3006   op_cost(0);
 3007   format %{ %}
 3008   interface(CONST_INTER);
 3009 %}
 3010 
 3011 operand immIpowerOf2() %{
 3012   predicate(is_power_of_2((juint)(n->get_int())));
 3013   match(ConI);
 3014   op_cost(0);
 3015   format %{ %}
 3016   interface(CONST_INTER);
 3017 %}
 3018 
 3019 // Long Immediate: low 32-bit mask
 3020 operand immL_32bits()
 3021 %{
 3022   predicate(n->get_long() == 0xFFFFFFFFL);
 3023   match(ConL);
 3024   op_cost(0);
 3025   format %{ %}
 3026   interface(CONST_INTER);
 3027 %}
 3028 
 3029 // 64 bit unit decrement
 3030 operand immL_M1()
 3031 %{
 3032   predicate(n->get_long() == -1);
 3033   match(ConL);
 3034 
 3035   op_cost(0);
 3036   format %{ %}
 3037   interface(CONST_INTER);
 3038 %}
 3039 
 3040 
 3041 // 32 bit offset of pc in thread anchor
 3042 
 3043 operand immL_pc_off()
 3044 %{
 3045   predicate(n->get_long() == in_bytes(JavaThread::frame_anchor_offset()) +
 3046                              in_bytes(JavaFrameAnchor::last_Java_pc_offset()));
 3047   match(ConL);
 3048 
 3049   op_cost(0);
 3050   format %{ %}
 3051   interface(CONST_INTER);
 3052 %}
 3053 
 3054 // 64 bit integer valid for add immediate
 3055 operand immLAdd()
 3056 %{
 3057   predicate(Assembler::operand_valid_for_add_immediate(n->get_long()));
 3058   match(ConL);
 3059   op_cost(0);
 3060   format %{ %}
 3061   interface(CONST_INTER);
 3062 %}
 3063 
 3064 // 64 bit integer valid for sub immediate
 3065 operand immLSub()
 3066 %{
 3067   predicate(Assembler::operand_valid_for_add_immediate(-(n->get_long())));
 3068   match(ConL);
 3069   op_cost(0);
 3070   format %{ %}
 3071   interface(CONST_INTER);
 3072 %}
 3073 
 3074 // Narrow pointer operands
 3075 // Narrow Pointer Immediate
 3076 operand immN()
 3077 %{
 3078   match(ConN);
 3079 
 3080   op_cost(0);
 3081   format %{ %}
 3082   interface(CONST_INTER);
 3083 %}
 3084 
 3085 // Narrow NULL Pointer Immediate
 3086 operand immN0()
 3087 %{
 3088   predicate(n->get_narrowcon() == 0);
 3089   match(ConN);
 3090 
 3091   op_cost(0);
 3092   format %{ %}
 3093   interface(CONST_INTER);
 3094 %}
 3095 
 3096 operand immNKlass()
 3097 %{
 3098   match(ConNKlass);
 3099 
 3100   op_cost(0);
 3101   format %{ %}
 3102   interface(CONST_INTER);
 3103 %}
 3104 
 3105 // Float and Double operands
 3106 // Double Immediate
 3107 operand immD()
 3108 %{
 3109   match(ConD);
 3110   op_cost(0);
 3111   format %{ %}
 3112   interface(CONST_INTER);
 3113 %}
 3114 
 3115 // Double Immediate: +0.0d
 3116 operand immD0()
 3117 %{
 3118   predicate(jlong_cast(n->getd()) == 0);
 3119   match(ConD);
 3120 
 3121   op_cost(0);
 3122   format %{ %}
 3123   interface(CONST_INTER);
 3124 %}
 3125 
 3126 // Float Immediate
 3127 operand immF()
 3128 %{
 3129   match(ConF);
 3130   op_cost(0);
 3131   format %{ %}
 3132   interface(CONST_INTER);
 3133 %}
 3134 
 3135 // Float Immediate: +0.0f.
 3136 operand immF0()
 3137 %{
 3138   predicate(jint_cast(n->getf()) == 0);
 3139   match(ConF);
 3140 
 3141   op_cost(0);
 3142   format %{ %}
 3143   interface(CONST_INTER);
 3144 %}
 3145 
 3146 operand immIOffset()
 3147 %{
 3148   predicate(is_imm_in_range(n->get_int(), 12, 0));
 3149   match(ConI);
 3150   op_cost(0);
 3151   format %{ %}
 3152   interface(CONST_INTER);
 3153 %}
 3154 
 3155 operand immLOffset()
 3156 %{
 3157   predicate(is_imm_in_range(n->get_long(), 12, 0));
 3158   match(ConL);
 3159   op_cost(0);
 3160   format %{ %}
 3161   interface(CONST_INTER);
 3162 %}
 3163 
 3164 // Scale values
 3165 operand immIScale()
 3166 %{
 3167   predicate(1 <= n->get_int() && (n->get_int() <= 3));
 3168   match(ConI);
 3169 
 3170   op_cost(0);
 3171   format %{ %}
 3172   interface(CONST_INTER);
 3173 %}
 3174 
 3175 // Integer 32 bit Register Operands
 3176 operand iRegI()
 3177 %{
 3178   constraint(ALLOC_IN_RC(any_reg32));
 3179   match(RegI);
 3180   match(iRegINoSp);
 3181   op_cost(0);
 3182   format %{ %}
 3183   interface(REG_INTER);
 3184 %}
 3185 
 3186 // Integer 32 bit Register not Special
 3187 operand iRegINoSp()
 3188 %{
 3189   constraint(ALLOC_IN_RC(no_special_reg32));
 3190   match(RegI);
 3191   op_cost(0);
 3192   format %{ %}
 3193   interface(REG_INTER);
 3194 %}
 3195 
 3196 // Register R10 only
 3197 operand iRegI_R10()
 3198 %{
 3199   constraint(ALLOC_IN_RC(int_r10_reg));
 3200   match(RegI);
 3201   match(iRegINoSp);
 3202   op_cost(0);
 3203   format %{ %}
 3204   interface(REG_INTER);
 3205 %}
 3206 
 3207 // Register R12 only
 3208 operand iRegI_R12()
 3209 %{
 3210   constraint(ALLOC_IN_RC(int_r12_reg));
 3211   match(RegI);
 3212   match(iRegINoSp);
 3213   op_cost(0);
 3214   format %{ %}
 3215   interface(REG_INTER);
 3216 %}
 3217 
 3218 // Register R13 only
 3219 operand iRegI_R13()
 3220 %{
 3221   constraint(ALLOC_IN_RC(int_r13_reg));
 3222   match(RegI);
 3223   match(iRegINoSp);
 3224   op_cost(0);
 3225   format %{ %}
 3226   interface(REG_INTER);
 3227 %}
 3228 
 3229 // Register R14 only
 3230 operand iRegI_R14()
 3231 %{
 3232   constraint(ALLOC_IN_RC(int_r14_reg));
 3233   match(RegI);
 3234   match(iRegINoSp);
 3235   op_cost(0);
 3236   format %{ %}
 3237   interface(REG_INTER);
 3238 %}
 3239 
 3240 // Integer 64 bit Register Operands
 3241 operand iRegL()
 3242 %{
 3243   constraint(ALLOC_IN_RC(any_reg));
 3244   match(RegL);
 3245   match(iRegLNoSp);
 3246   op_cost(0);
 3247   format %{ %}
 3248   interface(REG_INTER);
 3249 %}
 3250 
 3251 // Integer 64 bit Register not Special
 3252 operand iRegLNoSp()
 3253 %{
 3254   constraint(ALLOC_IN_RC(no_special_reg));
 3255   match(RegL);
 3256   match(iRegL_R10);
 3257   format %{ %}
 3258   interface(REG_INTER);
 3259 %}
 3260 
 3261 // Long 64 bit Register R28 only
 3262 operand iRegL_R28()
 3263 %{
 3264   constraint(ALLOC_IN_RC(r28_reg));
 3265   match(RegL);
 3266   match(iRegLNoSp);
 3267   op_cost(0);
 3268   format %{ %}
 3269   interface(REG_INTER);
 3270 %}
 3271 
 3272 // Long 64 bit Register R29 only
 3273 operand iRegL_R29()
 3274 %{
 3275   constraint(ALLOC_IN_RC(r29_reg));
 3276   match(RegL);
 3277   match(iRegLNoSp);
 3278   op_cost(0);
 3279   format %{ %}
 3280   interface(REG_INTER);
 3281 %}
 3282 
 3283 // Long 64 bit Register R30 only
 3284 operand iRegL_R30()
 3285 %{
 3286   constraint(ALLOC_IN_RC(r30_reg));
 3287   match(RegL);
 3288   match(iRegLNoSp);
 3289   op_cost(0);
 3290   format %{ %}
 3291   interface(REG_INTER);
 3292 %}
 3293 
 3294 // Pointer Register Operands
 3295 // Pointer Register
 3296 operand iRegP()
 3297 %{
 3298   constraint(ALLOC_IN_RC(ptr_reg));
 3299   match(RegP);
 3300   match(iRegPNoSp);
 3301   match(iRegP_R10);
 3302   match(iRegP_R15);
 3303   match(javaThread_RegP);
 3304   op_cost(0);
 3305   format %{ %}
 3306   interface(REG_INTER);
 3307 %}
 3308 
 3309 // Pointer 64 bit Register not Special
 3310 operand iRegPNoSp()
 3311 %{
 3312   constraint(ALLOC_IN_RC(no_special_ptr_reg));
 3313   match(RegP);
 3314   op_cost(0);
 3315   format %{ %}
 3316   interface(REG_INTER);
 3317 %}
 3318 
 3319 operand iRegP_R10()
 3320 %{
 3321   constraint(ALLOC_IN_RC(r10_reg));
 3322   match(RegP);
 3323   // match(iRegP);
 3324   match(iRegPNoSp);
 3325   op_cost(0);
 3326   format %{ %}
 3327   interface(REG_INTER);
 3328 %}
 3329 
 3330 // Pointer 64 bit Register R11 only
 3331 operand iRegP_R11()
 3332 %{
 3333   constraint(ALLOC_IN_RC(r11_reg));
 3334   match(RegP);
 3335   match(iRegPNoSp);
 3336   op_cost(0);
 3337   format %{ %}
 3338   interface(REG_INTER);
 3339 %}
 3340 
 3341 operand iRegP_R12()
 3342 %{
 3343   constraint(ALLOC_IN_RC(r12_reg));
 3344   match(RegP);
 3345   // match(iRegP);
 3346   match(iRegPNoSp);
 3347   op_cost(0);
 3348   format %{ %}
 3349   interface(REG_INTER);
 3350 %}
 3351 
 3352 // Pointer 64 bit Register R13 only
 3353 operand iRegP_R13()
 3354 %{
 3355   constraint(ALLOC_IN_RC(r13_reg));
 3356   match(RegP);
 3357   match(iRegPNoSp);
 3358   op_cost(0);
 3359   format %{ %}
 3360   interface(REG_INTER);
 3361 %}
 3362 
 3363 operand iRegP_R14()
 3364 %{
 3365   constraint(ALLOC_IN_RC(r14_reg));
 3366   match(RegP);
 3367   // match(iRegP);
 3368   match(iRegPNoSp);
 3369   op_cost(0);
 3370   format %{ %}
 3371   interface(REG_INTER);
 3372 %}
 3373 
 3374 operand iRegP_R15()
 3375 %{
 3376   constraint(ALLOC_IN_RC(r15_reg));
 3377   match(RegP);
 3378   // match(iRegP);
 3379   match(iRegPNoSp);
 3380   op_cost(0);
 3381   format %{ %}
 3382   interface(REG_INTER);
 3383 %}
 3384 
 3385 operand iRegP_R16()
 3386 %{
 3387   constraint(ALLOC_IN_RC(r16_reg));
 3388   match(RegP);
 3389   // match(iRegP);
 3390   match(iRegPNoSp);
 3391   op_cost(0);
 3392   format %{ %}
 3393   interface(REG_INTER);
 3394 %}
 3395 
 3396 // Pointer 64 bit Register R28 only
 3397 operand iRegP_R28()
 3398 %{
 3399   constraint(ALLOC_IN_RC(r28_reg));
 3400   match(RegP);
 3401   match(iRegPNoSp);
 3402   op_cost(0);
 3403   format %{ %}
 3404   interface(REG_INTER);
 3405 %}
 3406 
 3407 // Pointer 64 bit Register R30 only
 3408 operand iRegP_R30()
 3409 %{
 3410   constraint(ALLOC_IN_RC(r30_reg));
 3411   match(RegP);
 3412   match(iRegPNoSp);
 3413   op_cost(0);
 3414   format %{ %}
 3415   interface(REG_INTER);
 3416 %}
 3417 
 3418 // Pointer 64 bit Register R31 only
 3419 operand iRegP_R31()
 3420 %{
 3421   constraint(ALLOC_IN_RC(r31_reg));
 3422   match(RegP);
 3423   match(iRegPNoSp);
 3424   op_cost(0);
 3425   format %{ %}
 3426   interface(REG_INTER);
 3427 %}
 3428 
 3429 // Pointer Register Operands
 3430 // Narrow Pointer Register
 3431 operand iRegN()
 3432 %{
 3433   constraint(ALLOC_IN_RC(any_reg32));
 3434   match(RegN);
 3435   match(iRegNNoSp);
 3436   op_cost(0);
 3437   format %{ %}
 3438   interface(REG_INTER);
 3439 %}
 3440 
 3441 // Integer 64 bit Register not Special
 3442 operand iRegNNoSp()
 3443 %{
 3444   constraint(ALLOC_IN_RC(no_special_reg32));
 3445   match(RegN);
 3446   op_cost(0);
 3447   format %{ %}
 3448   interface(REG_INTER);
 3449 %}
 3450 
 3451 // heap base register -- used for encoding immN0
 3452 operand iRegIHeapbase()
 3453 %{
 3454   constraint(ALLOC_IN_RC(heapbase_reg));
 3455   match(RegI);
 3456   op_cost(0);
 3457   format %{ %}
 3458   interface(REG_INTER);
 3459 %}
 3460 
 3461 // Long 64 bit Register R10 only
 3462 operand iRegL_R10()
 3463 %{
 3464   constraint(ALLOC_IN_RC(r10_reg));
 3465   match(RegL);
 3466   match(iRegLNoSp);
 3467   op_cost(0);
 3468   format %{ %}
 3469   interface(REG_INTER);
 3470 %}
 3471 
 3472 // Float Register
 3473 // Float register operands
 3474 operand fRegF()
 3475 %{
 3476   constraint(ALLOC_IN_RC(float_reg));
 3477   match(RegF);
 3478 
 3479   op_cost(0);
 3480   format %{ %}
 3481   interface(REG_INTER);
 3482 %}
 3483 
 3484 // Double Register
 3485 // Double register operands
 3486 operand fRegD()
 3487 %{
 3488   constraint(ALLOC_IN_RC(double_reg));
 3489   match(RegD);
 3490 
 3491   op_cost(0);
 3492   format %{ %}
 3493   interface(REG_INTER);
 3494 %}
 3495 
 3496 // Generic vector class. This will be used for
 3497 // all vector operands.
 3498 operand vReg()
 3499 %{
 3500   constraint(ALLOC_IN_RC(vectora_reg));
 3501   match(VecA);
 3502   op_cost(0);
 3503   format %{ %}
 3504   interface(REG_INTER);
 3505 %}
 3506 
 3507 operand vReg_V1()
 3508 %{
 3509   constraint(ALLOC_IN_RC(v1_reg));
 3510   match(VecA);
 3511   match(vReg);
 3512   op_cost(0);
 3513   format %{ %}
 3514   interface(REG_INTER);
 3515 %}
 3516 
 3517 operand vReg_V2()
 3518 %{
 3519   constraint(ALLOC_IN_RC(v2_reg));
 3520   match(VecA);
 3521   match(vReg);
 3522   op_cost(0);
 3523   format %{ %}
 3524   interface(REG_INTER);
 3525 %}
 3526 
 3527 operand vReg_V3()
 3528 %{
 3529   constraint(ALLOC_IN_RC(v3_reg));
 3530   match(VecA);
 3531   match(vReg);
 3532   op_cost(0);
 3533   format %{ %}
 3534   interface(REG_INTER);
 3535 %}
 3536 
 3537 operand vReg_V4()
 3538 %{
 3539   constraint(ALLOC_IN_RC(v4_reg));
 3540   match(VecA);
 3541   match(vReg);
 3542   op_cost(0);
 3543   format %{ %}
 3544   interface(REG_INTER);
 3545 %}
 3546 
 3547 operand vReg_V5()
 3548 %{
 3549   constraint(ALLOC_IN_RC(v5_reg));
 3550   match(VecA);
 3551   match(vReg);
 3552   op_cost(0);
 3553   format %{ %}
 3554   interface(REG_INTER);
 3555 %}
 3556 
 3557 // Java Thread Register
 3558 operand javaThread_RegP(iRegP reg)
 3559 %{
 3560   constraint(ALLOC_IN_RC(java_thread_reg)); // java_thread_reg
 3561   match(reg);
 3562   op_cost(0);
 3563   format %{ %}
 3564   interface(REG_INTER);
 3565 %}
 3566 
 3567 //----------Memory Operands----------------------------------------------------
 3568 // RISCV has only base_plus_offset and literal address mode, so no need to use
 3569 // index and scale. Here set index as 0xffffffff and scale as 0x0.
 3570 operand indirect(iRegP reg)
 3571 %{
 3572   constraint(ALLOC_IN_RC(ptr_reg));
 3573   match(reg);
 3574   op_cost(0);
 3575   format %{ "[$reg]" %}
 3576   interface(MEMORY_INTER) %{
 3577     base($reg);
 3578     index(0xffffffff);
 3579     scale(0x0);
 3580     disp(0x0);
 3581   %}
 3582 %}
 3583 
 3584 operand indOffI(iRegP reg, immIOffset off)
 3585 %{
 3586   constraint(ALLOC_IN_RC(ptr_reg));
 3587   match(AddP reg off);
 3588   op_cost(0);
 3589   format %{ "[$reg, $off]" %}
 3590   interface(MEMORY_INTER) %{
 3591     base($reg);
 3592     index(0xffffffff);
 3593     scale(0x0);
 3594     disp($off);
 3595   %}
 3596 %}
 3597 
 3598 operand indOffL(iRegP reg, immLOffset off)
 3599 %{
 3600   constraint(ALLOC_IN_RC(ptr_reg));
 3601   match(AddP reg off);
 3602   op_cost(0);
 3603   format %{ "[$reg, $off]" %}
 3604   interface(MEMORY_INTER) %{
 3605     base($reg);
 3606     index(0xffffffff);
 3607     scale(0x0);
 3608     disp($off);
 3609   %}
 3610 %}
 3611 
 3612 operand indirectN(iRegN reg)
 3613 %{
 3614   predicate(CompressedOops::shift() == 0);
 3615   constraint(ALLOC_IN_RC(ptr_reg));
 3616   match(DecodeN reg);
 3617   op_cost(0);
 3618   format %{ "[$reg]\t# narrow" %}
 3619   interface(MEMORY_INTER) %{
 3620     base($reg);
 3621     index(0xffffffff);
 3622     scale(0x0);
 3623     disp(0x0);
 3624   %}
 3625 %}
 3626 
 3627 operand indOffIN(iRegN reg, immIOffset off)
 3628 %{
 3629   predicate(CompressedOops::shift() == 0);
 3630   constraint(ALLOC_IN_RC(ptr_reg));
 3631   match(AddP (DecodeN reg) off);
 3632   op_cost(0);
 3633   format %{ "[$reg, $off]\t# narrow" %}
 3634   interface(MEMORY_INTER) %{
 3635     base($reg);
 3636     index(0xffffffff);
 3637     scale(0x0);
 3638     disp($off);
 3639   %}
 3640 %}
 3641 
 3642 operand indOffLN(iRegN reg, immLOffset off)
 3643 %{
 3644   predicate(CompressedOops::shift() == 0);
 3645   constraint(ALLOC_IN_RC(ptr_reg));
 3646   match(AddP (DecodeN reg) off);
 3647   op_cost(0);
 3648   format %{ "[$reg, $off]\t# narrow" %}
 3649   interface(MEMORY_INTER) %{
 3650     base($reg);
 3651     index(0xffffffff);
 3652     scale(0x0);
 3653     disp($off);
 3654   %}
 3655 %}
 3656 
 3657 // RISCV opto stubs need to write to the pc slot in the thread anchor
 3658 operand thread_anchor_pc(javaThread_RegP reg, immL_pc_off off)
 3659 %{
 3660   constraint(ALLOC_IN_RC(ptr_reg));
 3661   match(AddP reg off);
 3662   op_cost(0);
 3663   format %{ "[$reg, $off]" %}
 3664   interface(MEMORY_INTER) %{
 3665     base($reg);
 3666     index(0xffffffff);
 3667     scale(0x0);
 3668     disp($off);
 3669   %}
 3670 %}
 3671 
 3672 
 3673 //----------Special Memory Operands--------------------------------------------
 3674 // Stack Slot Operand - This operand is used for loading and storing temporary
 3675 //                      values on the stack where a match requires a value to
 3676 //                      flow through memory.
 3677 operand stackSlotI(sRegI reg)
 3678 %{
 3679   constraint(ALLOC_IN_RC(stack_slots));
 3680   // No match rule because this operand is only generated in matching
 3681   // match(RegI);
 3682   format %{ "[$reg]" %}
 3683   interface(MEMORY_INTER) %{
 3684     base(0x02);  // RSP
 3685     index(0xffffffff);  // No Index
 3686     scale(0x0);  // No Scale
 3687     disp($reg);  // Stack Offset
 3688   %}
 3689 %}
 3690 
 3691 operand stackSlotF(sRegF reg)
 3692 %{
 3693   constraint(ALLOC_IN_RC(stack_slots));
 3694   // No match rule because this operand is only generated in matching
 3695   // match(RegF);
 3696   format %{ "[$reg]" %}
 3697   interface(MEMORY_INTER) %{
 3698     base(0x02);  // RSP
 3699     index(0xffffffff);  // No Index
 3700     scale(0x0);  // No Scale
 3701     disp($reg);  // Stack Offset
 3702   %}
 3703 %}
 3704 
 3705 operand stackSlotD(sRegD reg)
 3706 %{
 3707   constraint(ALLOC_IN_RC(stack_slots));
 3708   // No match rule because this operand is only generated in matching
 3709   // match(RegD);
 3710   format %{ "[$reg]" %}
 3711   interface(MEMORY_INTER) %{
 3712     base(0x02);  // RSP
 3713     index(0xffffffff);  // No Index
 3714     scale(0x0);  // No Scale
 3715     disp($reg);  // Stack Offset
 3716   %}
 3717 %}
 3718 
 3719 operand stackSlotL(sRegL reg)
 3720 %{
 3721   constraint(ALLOC_IN_RC(stack_slots));
 3722   // No match rule because this operand is only generated in matching
 3723   // match(RegL);
 3724   format %{ "[$reg]" %}
 3725   interface(MEMORY_INTER) %{
 3726     base(0x02);  // RSP
 3727     index(0xffffffff);  // No Index
 3728     scale(0x0);  // No Scale
 3729     disp($reg);  // Stack Offset
 3730   %}
 3731 %}
 3732 
 3733 // Special operand allowing long args to int ops to be truncated for free
 3734 
 3735 operand iRegL2I(iRegL reg) %{
 3736 
 3737   op_cost(0);
 3738 
 3739   match(ConvL2I reg);
 3740 
 3741   format %{ "l2i($reg)" %}
 3742 
 3743   interface(REG_INTER)
 3744 %}
 3745 
 3746 
 3747 // Comparison Operands
 3748 // NOTE: Label is a predefined operand which should not be redefined in
 3749 //       the AD file. It is generically handled within the ADLC.
 3750 
 3751 //----------Conditional Branch Operands----------------------------------------
 3752 // Comparison Op  - This is the operation of the comparison, and is limited to
 3753 //                  the following set of codes:
 3754 //                  L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
 3755 //
 3756 // Other attributes of the comparison, such as unsignedness, are specified
 3757 // by the comparison instruction that sets a condition code flags register.
 3758 // That result is represented by a flags operand whose subtype is appropriate
 3759 // to the unsignedness (etc.) of the comparison.
 3760 //
 3761 // Later, the instruction which matches both the Comparison Op (a Bool) and
 3762 // the flags (produced by the Cmp) specifies the coding of the comparison op
 3763 // by matching a specific subtype of Bool operand below, such as cmpOpU.
 3764 
 3765 
 3766 // used for signed integral comparisons and fp comparisons
 3767 operand cmpOp()
 3768 %{
 3769   match(Bool);
 3770 
 3771   format %{ "" %}
 3772 
 3773   // the values in interface derives from struct BoolTest::mask
 3774   interface(COND_INTER) %{
 3775     equal(0x0, "eq");
 3776     greater(0x1, "gt");
 3777     overflow(0x2, "overflow");
 3778     less(0x3, "lt");
 3779     not_equal(0x4, "ne");
 3780     less_equal(0x5, "le");
 3781     no_overflow(0x6, "no_overflow");
 3782     greater_equal(0x7, "ge");
 3783   %}
 3784 %}
 3785 
 3786 // used for unsigned integral comparisons
 3787 operand cmpOpU()
 3788 %{
 3789   match(Bool);
 3790 
 3791   format %{ "" %}
 3792   // the values in interface derives from struct BoolTest::mask
 3793   interface(COND_INTER) %{
 3794     equal(0x0, "eq");
 3795     greater(0x1, "gtu");
 3796     overflow(0x2, "overflow");
 3797     less(0x3, "ltu");
 3798     not_equal(0x4, "ne");
 3799     less_equal(0x5, "leu");
 3800     no_overflow(0x6, "no_overflow");
 3801     greater_equal(0x7, "geu");
 3802   %}
 3803 %}
 3804 
 3805 // used for certain integral comparisons which can be
 3806 // converted to bxx instructions
 3807 operand cmpOpEqNe()
 3808 %{
 3809   match(Bool);
 3810   op_cost(0);
 3811   predicate(n->as_Bool()->_test._test == BoolTest::ne ||
 3812             n->as_Bool()->_test._test == BoolTest::eq);
 3813 
 3814   format %{ "" %}
 3815   interface(COND_INTER) %{
 3816     equal(0x0, "eq");
 3817     greater(0x1, "gt");
 3818     overflow(0x2, "overflow");
 3819     less(0x3, "lt");
 3820     not_equal(0x4, "ne");
 3821     less_equal(0x5, "le");
 3822     no_overflow(0x6, "no_overflow");
 3823     greater_equal(0x7, "ge");
 3824   %}
 3825 %}
 3826 
 3827 operand cmpOpULtGe()
 3828 %{
 3829   match(Bool);
 3830   op_cost(0);
 3831   predicate(n->as_Bool()->_test._test == BoolTest::lt ||
 3832             n->as_Bool()->_test._test == BoolTest::ge);
 3833 
 3834   format %{ "" %}
 3835   interface(COND_INTER) %{
 3836     equal(0x0, "eq");
 3837     greater(0x1, "gtu");
 3838     overflow(0x2, "overflow");
 3839     less(0x3, "ltu");
 3840     not_equal(0x4, "ne");
 3841     less_equal(0x5, "leu");
 3842     no_overflow(0x6, "no_overflow");
 3843     greater_equal(0x7, "geu");
 3844   %}
 3845 %}
 3846 
 3847 operand cmpOpUEqNeLeGt()
 3848 %{
 3849   match(Bool);
 3850   op_cost(0);
 3851   predicate(n->as_Bool()->_test._test == BoolTest::ne ||
 3852             n->as_Bool()->_test._test == BoolTest::eq ||
 3853             n->as_Bool()->_test._test == BoolTest::le ||
 3854             n->as_Bool()->_test._test == BoolTest::gt);
 3855 
 3856   format %{ "" %}
 3857   interface(COND_INTER) %{
 3858     equal(0x0, "eq");
 3859     greater(0x1, "gtu");
 3860     overflow(0x2, "overflow");
 3861     less(0x3, "ltu");
 3862     not_equal(0x4, "ne");
 3863     less_equal(0x5, "leu");
 3864     no_overflow(0x6, "no_overflow");
 3865     greater_equal(0x7, "geu");
 3866   %}
 3867 %}
 3868 
 3869 
 3870 // Flags register, used as output of compare logic
 3871 operand rFlagsReg()
 3872 %{
 3873   constraint(ALLOC_IN_RC(reg_flags));
 3874   match(RegFlags);
 3875 
 3876   op_cost(0);
 3877   format %{ "RFLAGS" %}
 3878   interface(REG_INTER);
 3879 %}
 3880 
 3881 // Special Registers
 3882 
 3883 // Method Register
 3884 operand inline_cache_RegP(iRegP reg)
 3885 %{
 3886   constraint(ALLOC_IN_RC(method_reg)); // inline_cache_reg
 3887   match(reg);
 3888   match(iRegPNoSp);
 3889   op_cost(0);
 3890   format %{ %}
 3891   interface(REG_INTER);
 3892 %}
 3893 
 3894 //----------OPERAND CLASSES----------------------------------------------------
 3895 // Operand Classes are groups of operands that are used as to simplify
 3896 // instruction definitions by not requiring the AD writer to specify
 3897 // separate instructions for every form of operand when the
 3898 // instruction accepts multiple operand types with the same basic
 3899 // encoding and format. The classic case of this is memory operands.
 3900 
 3901 // memory is used to define read/write location for load/store
 3902 // instruction defs. we can turn a memory op into an Address
 3903 
 3904 opclass memory(indirect, indOffI, indOffL, indirectN, indOffIN, indOffLN);
 3905 
 3906 // iRegIorL2I is used for src inputs in rules for 32 bit int (I)
 3907 // operations. it allows the src to be either an iRegI or a (ConvL2I
 3908 // iRegL). in the latter case the l2i normally planted for a ConvL2I
 3909 // can be elided because the 32-bit instruction will just employ the
 3910 // lower 32 bits anyway.
 3911 //
 3912 // n.b. this does not elide all L2I conversions. if the truncated
 3913 // value is consumed by more than one operation then the ConvL2I
 3914 // cannot be bundled into the consuming nodes so an l2i gets planted
 3915 // (actually an addiw $dst, $src, 0) and the downstream instructions
 3916 // consume the result of the L2I as an iRegI input. That's a shame since
 3917 // the addiw is actually redundant but its not too costly.
 3918 
 3919 opclass iRegIorL2I(iRegI, iRegL2I);
 3920 opclass iRegIorL(iRegI, iRegL);
 3921 opclass iRegNorP(iRegN, iRegP);
 3922 opclass iRegILNP(iRegI, iRegL, iRegN, iRegP);
 3923 opclass iRegILNPNoSp(iRegINoSp, iRegLNoSp, iRegNNoSp, iRegPNoSp);
 3924 opclass immIorL(immI, immL);
 3925 
 3926 //----------PIPELINE-----------------------------------------------------------
 3927 // Rules which define the behavior of the target architectures pipeline.
 3928 
 3929 // For specific pipelines, e.g. generic RISC-V, define the stages of that pipeline
 3930 //pipe_desc(ID, EX, MEM, WR);
 3931 #define ID   S0
 3932 #define EX   S1
 3933 #define MEM  S2
 3934 #define WR   S3
 3935 
 3936 // Integer ALU reg operation
 3937 pipeline %{
 3938 
 3939 attributes %{
 3940   // RISC-V instructions are of fixed length
 3941   fixed_size_instructions;           // Fixed size instructions TODO does
 3942   max_instructions_per_bundle = 2;   // Generic RISC-V 1, Sifive Series 7 2
 3943   // RISC-V instructions come in 32-bit word units
 3944   instruction_unit_size = 4;         // An instruction is 4 bytes long
 3945   instruction_fetch_unit_size = 64;  // The processor fetches one line
 3946   instruction_fetch_units = 1;       // of 64 bytes
 3947 
 3948   // List of nop instructions
 3949   nops( MachNop );
 3950 %}
 3951 
 3952 // We don't use an actual pipeline model so don't care about resources
 3953 // or description. we do use pipeline classes to introduce fixed
 3954 // latencies
 3955 
 3956 //----------RESOURCES----------------------------------------------------------
 3957 // Resources are the functional units available to the machine
 3958 
 3959 // Generic RISC-V pipeline
 3960 // 1 decoder
 3961 // 1 instruction decoded per cycle
 3962 // 1 load/store ops per cycle, 1 branch, 1 FPU
 3963 // 1 mul, 1 div
 3964 
 3965 resources ( DECODE,
 3966             ALU,
 3967             MUL,
 3968             DIV,
 3969             BRANCH,
 3970             LDST,
 3971             FPU);
 3972 
 3973 //----------PIPELINE DESCRIPTION-----------------------------------------------
 3974 // Pipeline Description specifies the stages in the machine's pipeline
 3975 
 3976 // Define the pipeline as a generic 6 stage pipeline
 3977 pipe_desc(S0, S1, S2, S3, S4, S5);
 3978 
 3979 //----------PIPELINE CLASSES---------------------------------------------------
 3980 // Pipeline Classes describe the stages in which input and output are
 3981 // referenced by the hardware pipeline.
 3982 
 3983 pipe_class fp_dop_reg_reg_s(fRegF dst, fRegF src1, fRegF src2)
 3984 %{
 3985   single_instruction;
 3986   src1   : S1(read);
 3987   src2   : S2(read);
 3988   dst    : S5(write);
 3989   DECODE : ID;
 3990   FPU    : S5;
 3991 %}
 3992 
 3993 pipe_class fp_dop_reg_reg_d(fRegD dst, fRegD src1, fRegD src2)
 3994 %{
 3995   src1   : S1(read);
 3996   src2   : S2(read);
 3997   dst    : S5(write);
 3998   DECODE : ID;
 3999   FPU    : S5;
 4000 %}
 4001 
 4002 pipe_class fp_uop_s(fRegF dst, fRegF src)
 4003 %{
 4004   single_instruction;
 4005   src    : S1(read);
 4006   dst    : S5(write);
 4007   DECODE : ID;
 4008   FPU    : S5;
 4009 %}
 4010 
 4011 pipe_class fp_uop_d(fRegD dst, fRegD src)
 4012 %{
 4013   single_instruction;
 4014   src    : S1(read);
 4015   dst    : S5(write);
 4016   DECODE : ID;
 4017   FPU    : S5;
 4018 %}
 4019 
 4020 pipe_class fp_d2f(fRegF dst, fRegD src)
 4021 %{
 4022   single_instruction;
 4023   src    : S1(read);
 4024   dst    : S5(write);
 4025   DECODE : ID;
 4026   FPU    : S5;
 4027 %}
 4028 
 4029 pipe_class fp_f2d(fRegD dst, fRegF src)
 4030 %{
 4031   single_instruction;
 4032   src    : S1(read);
 4033   dst    : S5(write);
 4034   DECODE : ID;
 4035   FPU    : S5;
 4036 %}
 4037 
 4038 pipe_class fp_f2i(iRegINoSp dst, fRegF src)
 4039 %{
 4040   single_instruction;
 4041   src    : S1(read);
 4042   dst    : S5(write);
 4043   DECODE : ID;
 4044   FPU    : S5;
 4045 %}
 4046 
 4047 pipe_class fp_f2l(iRegLNoSp dst, fRegF src)
 4048 %{
 4049   single_instruction;
 4050   src    : S1(read);
 4051   dst    : S5(write);
 4052   DECODE : ID;
 4053   FPU    : S5;
 4054 %}
 4055 
 4056 pipe_class fp_i2f(fRegF dst, iRegIorL2I src)
 4057 %{
 4058   single_instruction;
 4059   src    : S1(read);
 4060   dst    : S5(write);
 4061   DECODE : ID;
 4062   FPU    : S5;
 4063 %}
 4064 
 4065 pipe_class fp_l2f(fRegF dst, iRegL src)
 4066 %{
 4067   single_instruction;
 4068   src    : S1(read);
 4069   dst    : S5(write);
 4070   DECODE : ID;
 4071   FPU    : S5;
 4072 %}
 4073 
 4074 pipe_class fp_d2i(iRegINoSp dst, fRegD src)
 4075 %{
 4076   single_instruction;
 4077   src    : S1(read);
 4078   dst    : S5(write);
 4079   DECODE : ID;
 4080   FPU    : S5;
 4081 %}
 4082 
 4083 pipe_class fp_d2l(iRegLNoSp dst, fRegD src)
 4084 %{
 4085   single_instruction;
 4086   src    : S1(read);
 4087   dst    : S5(write);
 4088   DECODE : ID;
 4089   FPU    : S5;
 4090 %}
 4091 
 4092 pipe_class fp_i2d(fRegD dst, iRegIorL2I src)
 4093 %{
 4094   single_instruction;
 4095   src    : S1(read);
 4096   dst    : S5(write);
 4097   DECODE : ID;
 4098   FPU    : S5;
 4099 %}
 4100 
 4101 pipe_class fp_l2d(fRegD dst, iRegIorL2I src)
 4102 %{
 4103   single_instruction;
 4104   src    : S1(read);
 4105   dst    : S5(write);
 4106   DECODE : ID;
 4107   FPU    : S5;
 4108 %}
 4109 
 4110 pipe_class fp_div_s(fRegF dst, fRegF src1, fRegF src2)
 4111 %{
 4112   single_instruction;
 4113   src1   : S1(read);
 4114   src2   : S2(read);
 4115   dst    : S5(write);
 4116   DECODE : ID;
 4117   FPU    : S5;
 4118 %}
 4119 
 4120 pipe_class fp_div_d(fRegD dst, fRegD src1, fRegD src2)
 4121 %{
 4122   single_instruction;
 4123   src1   : S1(read);
 4124   src2   : S2(read);
 4125   dst    : S5(write);
 4126   DECODE : ID;
 4127   FPU    : S5;
 4128 %}
 4129 
 4130 pipe_class fp_sqrt_s(fRegF dst, fRegF src1, fRegF src2)
 4131 %{
 4132   single_instruction;
 4133   src1   : S1(read);
 4134   src2   : S2(read);
 4135   dst    : S5(write);
 4136   DECODE : ID;
 4137   FPU    : S5;
 4138 %}
 4139 
 4140 pipe_class fp_sqrt_d(fRegD dst, fRegD src1, fRegD src2)
 4141 %{
 4142   single_instruction;
 4143   src1   : S1(read);
 4144   src2   : S2(read);
 4145   dst    : S5(write);
 4146   DECODE : ID;
 4147   FPU    : S5;
 4148 %}
 4149 
 4150 pipe_class fp_load_constant_s(fRegF dst)
 4151 %{
 4152   single_instruction;
 4153   dst    : S5(write);
 4154   DECODE : ID;
 4155   FPU    : S5;
 4156 %}
 4157 
 4158 pipe_class fp_load_constant_d(fRegD dst)
 4159 %{
 4160   single_instruction;
 4161   dst    : S5(write);
 4162   DECODE : ID;
 4163   FPU    : S5;
 4164 %}
 4165 
 4166 pipe_class fp_load_mem_s(fRegF dst, memory mem)
 4167 %{
 4168   single_instruction;
 4169   mem    : S1(read);
 4170   dst    : S5(write);
 4171   DECODE : ID;
 4172   LDST   : MEM;
 4173 %}
 4174 
 4175 pipe_class fp_load_mem_d(fRegD dst, memory mem)
 4176 %{
 4177   single_instruction;
 4178   mem    : S1(read);
 4179   dst    : S5(write);
 4180   DECODE : ID;
 4181   LDST   : MEM;
 4182 %}
 4183 
 4184 pipe_class fp_store_reg_s(fRegF src, memory mem)
 4185 %{
 4186   single_instruction;
 4187   src    : S1(read);
 4188   mem    : S5(write);
 4189   DECODE : ID;
 4190   LDST   : MEM;
 4191 %}
 4192 
 4193 pipe_class fp_store_reg_d(fRegD src, memory mem)
 4194 %{
 4195   single_instruction;
 4196   src    : S1(read);
 4197   mem    : S5(write);
 4198   DECODE : ID;
 4199   LDST   : MEM;
 4200 %}
 4201 
 4202 //------- Integer ALU operations --------------------------
 4203 
 4204 // Integer ALU reg-reg operation
 4205 // Operands needs in ID, result generated in EX
 4206 // E.g.  ADD   Rd, Rs1, Rs2
 4207 pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2)
 4208 %{
 4209   single_instruction;
 4210   dst    : EX(write);
 4211   src1   : ID(read);
 4212   src2   : ID(read);
 4213   DECODE : ID;
 4214   ALU    : EX;
 4215 %}
 4216 
 4217 // Integer ALU reg operation with constant shift
 4218 // E.g. SLLI    Rd, Rs1, #shift
 4219 pipe_class ialu_reg_shift(iRegI dst, iRegI src1)
 4220 %{
 4221   single_instruction;
 4222   dst    : EX(write);
 4223   src1   : ID(read);
 4224   DECODE : ID;
 4225   ALU    : EX;
 4226 %}
 4227 
 4228 // Integer ALU reg-reg operation with variable shift
 4229 // both operands must be available in ID
 4230 // E.g. SLL   Rd, Rs1, Rs2
 4231 pipe_class ialu_reg_reg_vshift(iRegI dst, iRegI src1, iRegI src2)
 4232 %{
 4233   single_instruction;
 4234   dst    : EX(write);
 4235   src1   : ID(read);
 4236   src2   : ID(read);
 4237   DECODE : ID;
 4238   ALU    : EX;
 4239 %}
 4240 
 4241 // Integer ALU reg operation
 4242 // E.g. NEG   Rd, Rs2
 4243 pipe_class ialu_reg(iRegI dst, iRegI src)
 4244 %{
 4245   single_instruction;
 4246   dst    : EX(write);
 4247   src    : ID(read);
 4248   DECODE : ID;
 4249   ALU    : EX;
 4250 %}
 4251 
 4252 // Integer ALU reg immediate operation
 4253 // E.g. ADDI   Rd, Rs1, #imm
 4254 pipe_class ialu_reg_imm(iRegI dst, iRegI src1)
 4255 %{
 4256   single_instruction;
 4257   dst    : EX(write);
 4258   src1   : ID(read);
 4259   DECODE : ID;
 4260   ALU    : EX;
 4261 %}
 4262 
 4263 // Integer ALU immediate operation (no source operands)
 4264 // E.g. LI    Rd, #imm
 4265 pipe_class ialu_imm(iRegI dst)
 4266 %{
 4267   single_instruction;
 4268   dst    : EX(write);
 4269   DECODE : ID;
 4270   ALU    : EX;
 4271 %}
 4272 
 4273 //------- Multiply pipeline operations --------------------
 4274 
 4275 // Multiply reg-reg
 4276 // E.g. MULW   Rd, Rs1, Rs2
 4277 pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2)
 4278 %{
 4279   single_instruction;
 4280   dst    : WR(write);
 4281   src1   : ID(read);
 4282   src2   : ID(read);
 4283   DECODE : ID;
 4284   MUL    : WR;
 4285 %}
 4286 
 4287 // E.g. MUL   RD, Rs1, Rs2
 4288 pipe_class lmul_reg_reg(iRegL dst, iRegL src1, iRegL src2)
 4289 %{
 4290   single_instruction;
 4291   fixed_latency(3); // Maximum latency for 64 bit mul
 4292   dst    : WR(write);
 4293   src1   : ID(read);
 4294   src2   : ID(read);
 4295   DECODE : ID;
 4296   MUL    : WR;
 4297 %}
 4298 
 4299 //------- Divide pipeline operations --------------------
 4300 
 4301 // E.g. DIVW   Rd, Rs1, Rs2
 4302 pipe_class idiv_reg_reg(iRegI dst, iRegI src1, iRegI src2)
 4303 %{
 4304   single_instruction;
 4305   fixed_latency(8); // Maximum latency for 32 bit divide
 4306   dst    : WR(write);
 4307   src1   : ID(read);
 4308   src2   : ID(read);
 4309   DECODE : ID;
 4310   DIV    : WR;
 4311 %}
 4312 
 4313 // E.g. DIV   RD, Rs1, Rs2
 4314 pipe_class ldiv_reg_reg(iRegL dst, iRegL src1, iRegL src2)
 4315 %{
 4316   single_instruction;
 4317   fixed_latency(16); // Maximum latency for 64 bit divide
 4318   dst    : WR(write);
 4319   src1   : ID(read);
 4320   src2   : ID(read);
 4321   DECODE : ID;
 4322   DIV    : WR;
 4323 %}
 4324 
 4325 //------- Load pipeline operations ------------------------
 4326 
 4327 // Load - prefetch
 4328 // Eg.  PREFETCH_W  mem
 4329 pipe_class iload_prefetch(memory mem)
 4330 %{
 4331   single_instruction;
 4332   mem    : ID(read);
 4333   DECODE : ID;
 4334   LDST   : MEM;
 4335 %}
 4336 
 4337 // Load - reg, mem
 4338 // E.g. LA    Rd, mem
 4339 pipe_class iload_reg_mem(iRegI dst, memory mem)
 4340 %{
 4341   single_instruction;
 4342   dst    : WR(write);
 4343   mem    : ID(read);
 4344   DECODE : ID;
 4345   LDST   : MEM;
 4346 %}
 4347 
 4348 // Load - reg, reg
 4349 // E.g. LD    Rd, Rs
 4350 pipe_class iload_reg_reg(iRegI dst, iRegI src)
 4351 %{
 4352   single_instruction;
 4353   dst    : WR(write);
 4354   src    : ID(read);
 4355   DECODE : ID;
 4356   LDST   : MEM;
 4357 %}
 4358 
 4359 //------- Store pipeline operations -----------------------
 4360 
 4361 // Store - zr, mem
 4362 // E.g. SD    zr, mem
 4363 pipe_class istore_mem(memory mem)
 4364 %{
 4365   single_instruction;
 4366   mem    : ID(read);
 4367   DECODE : ID;
 4368   LDST   : MEM;
 4369 %}
 4370 
 4371 // Store - reg, mem
 4372 // E.g. SD    Rs, mem
 4373 pipe_class istore_reg_mem(iRegI src, memory mem)
 4374 %{
 4375   single_instruction;
 4376   mem    : ID(read);
 4377   src    : EX(read);
 4378   DECODE : ID;
 4379   LDST   : MEM;
 4380 %}
 4381 
 4382 // Store - reg, reg
 4383 // E.g. SD    Rs2, Rs1
 4384 pipe_class istore_reg_reg(iRegI dst, iRegI src)
 4385 %{
 4386   single_instruction;
 4387   dst    : ID(read);
 4388   src    : EX(read);
 4389   DECODE : ID;
 4390   LDST   : MEM;
 4391 %}
 4392 
 4393 //------- Control transfer pipeline operations ------------
 4394 
 4395 // Branch
 4396 pipe_class pipe_branch()
 4397 %{
 4398   single_instruction;
 4399   DECODE : ID;
 4400   BRANCH : EX;
 4401 %}
 4402 
 4403 // Branch
 4404 pipe_class pipe_branch_reg(iRegI src)
 4405 %{
 4406   single_instruction;
 4407   src    : ID(read);
 4408   DECODE : ID;
 4409   BRANCH : EX;
 4410 %}
 4411 
 4412 // Compare & Branch
 4413 // E.g. BEQ   Rs1, Rs2, L
 4414 pipe_class pipe_cmp_branch(iRegI src1, iRegI src2)
 4415 %{
 4416   single_instruction;
 4417   src1   : ID(read);
 4418   src2   : ID(read);
 4419   DECODE : ID;
 4420   BRANCH : EX;
 4421 %}
 4422 
 4423 // E.g. BEQZ Rs, L
 4424 pipe_class pipe_cmpz_branch(iRegI src)
 4425 %{
 4426   single_instruction;
 4427   src    : ID(read);
 4428   DECODE : ID;
 4429   BRANCH : EX;
 4430 %}
 4431 
 4432 //------- Synchronisation operations ----------------------
 4433 // Any operation requiring serialization
 4434 // E.g. FENCE/Atomic Ops/Load Acquire/Store Release
 4435 pipe_class pipe_serial()
 4436 %{
 4437   single_instruction;
 4438   force_serialization;
 4439   fixed_latency(16);
 4440   DECODE : ID;
 4441   LDST   : MEM;
 4442 %}
 4443 
 4444 pipe_class pipe_slow()
 4445 %{
 4446   instruction_count(10);
 4447   multiple_bundles;
 4448   force_serialization;
 4449   fixed_latency(16);
 4450   DECODE : ID;
 4451   LDST   : MEM;
 4452 %}
 4453 
 4454 // Empty pipeline class
 4455 pipe_class pipe_class_empty()
 4456 %{
 4457   single_instruction;
 4458   fixed_latency(0);
 4459 %}
 4460 
 4461 // Default pipeline class.
 4462 pipe_class pipe_class_default()
 4463 %{
 4464   single_instruction;
 4465   fixed_latency(2);
 4466 %}
 4467 
 4468 // Pipeline class for compares.
 4469 pipe_class pipe_class_compare()
 4470 %{
 4471   single_instruction;
 4472   fixed_latency(16);
 4473 %}
 4474 
 4475 // Pipeline class for memory operations.
 4476 pipe_class pipe_class_memory()
 4477 %{
 4478   single_instruction;
 4479   fixed_latency(16);
 4480 %}
 4481 
 4482 // Pipeline class for call.
 4483 pipe_class pipe_class_call()
 4484 %{
 4485   single_instruction;
 4486   fixed_latency(100);
 4487 %}
 4488 
 4489 // Define the class for the Nop node.
 4490 define %{
 4491    MachNop = pipe_class_empty;
 4492 %}
 4493 %}
 4494 //----------INSTRUCTIONS-------------------------------------------------------
 4495 //
 4496 // match      -- States which machine-independent subtree may be replaced
 4497 //               by this instruction.
 4498 // ins_cost   -- The estimated cost of this instruction is used by instruction
 4499 //               selection to identify a minimum cost tree of machine
 4500 //               instructions that matches a tree of machine-independent
 4501 //               instructions.
 4502 // format     -- A string providing the disassembly for this instruction.
 4503 //               The value of an instruction's operand may be inserted
 4504 //               by referring to it with a '$' prefix.
 4505 // opcode     -- Three instruction opcodes may be provided.  These are referred
 4506 //               to within an encode class as $primary, $secondary, and $tertiary
 4507 //               rrspectively.  The primary opcode is commonly used to
 4508 //               indicate the type of machine instruction, while secondary
 4509 //               and tertiary are often used for prefix options or addressing
 4510 //               modes.
 4511 // ins_encode -- A list of encode classes with parameters. The encode class
 4512 //               name must have been defined in an 'enc_class' specification
 4513 //               in the encode section of the architecture description.
 4514 
 4515 // ============================================================================
 4516 // Memory (Load/Store) Instructions
 4517 
 4518 // Load Instructions
 4519 
 4520 // Load Byte (8 bit signed)
 4521 instruct loadB(iRegINoSp dst, memory mem)
 4522 %{
 4523   match(Set dst (LoadB mem));
 4524 
 4525   ins_cost(LOAD_COST);
 4526   format %{ "lb  $dst, $mem\t# byte, #@loadB" %}
 4527 
 4528   ins_encode %{
 4529     __ lb(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4530   %}
 4531 
 4532   ins_pipe(iload_reg_mem);
 4533 %}
 4534 
 4535 // Load Byte (8 bit signed) into long
 4536 instruct loadB2L(iRegLNoSp dst, memory mem)
 4537 %{
 4538   match(Set dst (ConvI2L (LoadB mem)));
 4539 
 4540   ins_cost(LOAD_COST);
 4541   format %{ "lb  $dst, $mem\t# byte, #@loadB2L" %}
 4542 
 4543   ins_encode %{
 4544     __ lb(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4545   %}
 4546 
 4547   ins_pipe(iload_reg_mem);
 4548 %}
 4549 
 4550 // Load Byte (8 bit unsigned)
 4551 instruct loadUB(iRegINoSp dst, memory mem)
 4552 %{
 4553   match(Set dst (LoadUB mem));
 4554 
 4555   ins_cost(LOAD_COST);
 4556   format %{ "lbu  $dst, $mem\t# byte, #@loadUB" %}
 4557 
 4558   ins_encode %{
 4559     __ lbu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4560   %}
 4561 
 4562   ins_pipe(iload_reg_mem);
 4563 %}
 4564 
 4565 // Load Byte (8 bit unsigned) into long
 4566 instruct loadUB2L(iRegLNoSp dst, memory mem)
 4567 %{
 4568   match(Set dst (ConvI2L (LoadUB mem)));
 4569 
 4570   ins_cost(LOAD_COST);
 4571   format %{ "lbu  $dst, $mem\t# byte, #@loadUB2L" %}
 4572 
 4573   ins_encode %{
 4574     __ lbu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4575   %}
 4576 
 4577   ins_pipe(iload_reg_mem);
 4578 %}
 4579 
 4580 // Load Short (16 bit signed)
 4581 instruct loadS(iRegINoSp dst, memory mem)
 4582 %{
 4583   match(Set dst (LoadS mem));
 4584 
 4585   ins_cost(LOAD_COST);
 4586   format %{ "lh  $dst, $mem\t# short, #@loadS" %}
 4587 
 4588   ins_encode %{
 4589     __ lh(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4590   %}
 4591 
 4592   ins_pipe(iload_reg_mem);
 4593 %}
 4594 
 4595 // Load Short (16 bit signed) into long
 4596 instruct loadS2L(iRegLNoSp dst, memory mem)
 4597 %{
 4598   match(Set dst (ConvI2L (LoadS mem)));
 4599 
 4600   ins_cost(LOAD_COST);
 4601   format %{ "lh  $dst, $mem\t# short, #@loadS2L" %}
 4602 
 4603   ins_encode %{
 4604     __ lh(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4605   %}
 4606 
 4607   ins_pipe(iload_reg_mem);
 4608 %}
 4609 
 4610 // Load Char (16 bit unsigned)
 4611 instruct loadUS(iRegINoSp dst, memory mem)
 4612 %{
 4613   match(Set dst (LoadUS mem));
 4614 
 4615   ins_cost(LOAD_COST);
 4616   format %{ "lhu  $dst, $mem\t# short, #@loadUS" %}
 4617 
 4618   ins_encode %{
 4619     __ lhu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4620   %}
 4621 
 4622   ins_pipe(iload_reg_mem);
 4623 %}
 4624 
 4625 // Load Short/Char (16 bit unsigned) into long
 4626 instruct loadUS2L(iRegLNoSp dst, memory mem)
 4627 %{
 4628   match(Set dst (ConvI2L (LoadUS mem)));
 4629 
 4630   ins_cost(LOAD_COST);
 4631   format %{ "lhu  $dst, $mem\t# short, #@loadUS2L" %}
 4632 
 4633   ins_encode %{
 4634     __ lhu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4635   %}
 4636 
 4637   ins_pipe(iload_reg_mem);
 4638 %}
 4639 
 4640 // Load Integer (32 bit signed)
 4641 instruct loadI(iRegINoSp dst, memory mem)
 4642 %{
 4643   match(Set dst (LoadI mem));
 4644 
 4645   ins_cost(LOAD_COST);
 4646   format %{ "lw  $dst, $mem\t# int, #@loadI" %}
 4647 
 4648   ins_encode %{
 4649     __ lw(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4650   %}
 4651 
 4652   ins_pipe(iload_reg_mem);
 4653 %}
 4654 
 4655 // Load Integer (32 bit signed) into long
 4656 instruct loadI2L(iRegLNoSp dst, memory mem)
 4657 %{
 4658   match(Set dst (ConvI2L (LoadI mem)));
 4659 
 4660   ins_cost(LOAD_COST);
 4661   format %{ "lw  $dst, $mem\t# int, #@loadI2L" %}
 4662 
 4663   ins_encode %{
 4664     __ lw(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4665   %}
 4666 
 4667   ins_pipe(iload_reg_mem);
 4668 %}
 4669 
 4670 // Load Integer (32 bit unsigned) into long
 4671 instruct loadUI2L(iRegLNoSp dst, memory mem, immL_32bits mask)
 4672 %{
 4673   match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
 4674 
 4675   ins_cost(LOAD_COST);
 4676   format %{ "lwu  $dst, $mem\t# int, #@loadUI2L" %}
 4677 
 4678   ins_encode %{
 4679     __ lwu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4680   %}
 4681 
 4682   ins_pipe(iload_reg_mem);
 4683 %}
 4684 
 4685 // Load Long (64 bit signed)
 4686 instruct loadL(iRegLNoSp dst, memory mem)
 4687 %{
 4688   match(Set dst (LoadL mem));
 4689 
 4690   ins_cost(LOAD_COST);
 4691   format %{ "ld  $dst, $mem\t# int, #@loadL" %}
 4692 
 4693   ins_encode %{
 4694     __ ld(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4695   %}
 4696 
 4697   ins_pipe(iload_reg_mem);
 4698 %}
 4699 
 4700 // Load Range
 4701 instruct loadRange(iRegINoSp dst, memory mem)
 4702 %{
 4703   match(Set dst (LoadRange mem));
 4704 
 4705   ins_cost(LOAD_COST);
 4706   format %{ "lwu  $dst, $mem\t# range, #@loadRange" %}
 4707 
 4708   ins_encode %{
 4709     __ lwu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4710   %}
 4711 
 4712   ins_pipe(iload_reg_mem);
 4713 %}
 4714 
 4715 // Load Pointer
 4716 instruct loadP(iRegPNoSp dst, memory mem)
 4717 %{
 4718   match(Set dst (LoadP mem));
 4719   predicate(n->as_Load()->barrier_data() == 0);
 4720 
 4721   ins_cost(LOAD_COST);
 4722   format %{ "ld  $dst, $mem\t# ptr, #@loadP" %}
 4723 
 4724   ins_encode %{
 4725     __ ld(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4726   %}
 4727 
 4728   ins_pipe(iload_reg_mem);
 4729 %}
 4730 
 4731 // Load Compressed Pointer
 4732 instruct loadN(iRegNNoSp dst, memory mem)
 4733 %{
 4734   match(Set dst (LoadN mem));
 4735 
 4736   ins_cost(LOAD_COST);
 4737   format %{ "lwu  $dst, $mem\t# loadN, compressed ptr, #@loadN" %}
 4738 
 4739   ins_encode %{
 4740     __ lwu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4741   %}
 4742 
 4743   ins_pipe(iload_reg_mem);
 4744 %}
 4745 
 4746 // Load Klass Pointer
 4747 instruct loadKlass(iRegPNoSp dst, memory mem)
 4748 %{
 4749   match(Set dst (LoadKlass mem));
 4750 
 4751   ins_cost(LOAD_COST);
 4752   format %{ "ld  $dst, $mem\t# class, #@loadKlass" %}
 4753 
 4754   ins_encode %{
 4755     __ ld(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4756   %}
 4757 
 4758   ins_pipe(iload_reg_mem);
 4759 %}
 4760 
 4761 // Load Narrow Klass Pointer
 4762 instruct loadNKlass(iRegNNoSp dst, memory mem)
 4763 %{
 4764   match(Set dst (LoadNKlass mem));
 4765 
 4766   ins_cost(LOAD_COST);
 4767   format %{ "lwu  $dst, $mem\t# loadNKlass, compressed class ptr, #@loadNKlass" %}
 4768 
 4769   ins_encode %{
 4770     __ lwu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4771   %}
 4772 
 4773   ins_pipe(iload_reg_mem);
 4774 %}
 4775 
 4776 // Load Float
 4777 instruct loadF(fRegF dst, memory mem)
 4778 %{
 4779   match(Set dst (LoadF mem));
 4780 
 4781   ins_cost(LOAD_COST);
 4782   format %{ "flw  $dst, $mem\t# float, #@loadF" %}
 4783 
 4784   ins_encode %{
 4785     __ flw(as_FloatRegister($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4786   %}
 4787 
 4788   ins_pipe(fp_load_mem_s);
 4789 %}
 4790 
 4791 // Load Double
 4792 instruct loadD(fRegD dst, memory mem)
 4793 %{
 4794   match(Set dst (LoadD mem));
 4795 
 4796   ins_cost(LOAD_COST);
 4797   format %{ "fld  $dst, $mem\t# double, #@loadD" %}
 4798 
 4799   ins_encode %{
 4800     __ fld(as_FloatRegister($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4801   %}
 4802 
 4803   ins_pipe(fp_load_mem_d);
 4804 %}
 4805 
 4806 // Load Int Constant
 4807 instruct loadConI(iRegINoSp dst, immI src)
 4808 %{
 4809   match(Set dst src);
 4810 
 4811   ins_cost(ALU_COST);
 4812   format %{ "li $dst, $src\t# int, #@loadConI" %}
 4813 
 4814   ins_encode(riscv_enc_li_imm(dst, src));
 4815 
 4816   ins_pipe(ialu_imm);
 4817 %}
 4818 
 4819 // Load Long Constant
 4820 instruct loadConL(iRegLNoSp dst, immL src)
 4821 %{
 4822   match(Set dst src);
 4823 
 4824   ins_cost(ALU_COST);
 4825   format %{ "li $dst, $src\t# long, #@loadConL" %}
 4826 
 4827   ins_encode(riscv_enc_li_imm(dst, src));
 4828 
 4829   ins_pipe(ialu_imm);
 4830 %}
 4831 
 4832 // Load Pointer Constant
 4833 instruct loadConP(iRegPNoSp dst, immP con)
 4834 %{
 4835   match(Set dst con);
 4836 
 4837   ins_cost(ALU_COST);
 4838   format %{ "mv  $dst, $con\t# ptr, #@loadConP" %}
 4839 
 4840   ins_encode(riscv_enc_mov_p(dst, con));
 4841 
 4842   ins_pipe(ialu_imm);
 4843 %}
 4844 
 4845 // Load Null Pointer Constant
 4846 instruct loadConP0(iRegPNoSp dst, immP0 con)
 4847 %{
 4848   match(Set dst con);
 4849 
 4850   ins_cost(ALU_COST);
 4851   format %{ "mv  $dst, $con\t# NULL ptr, #@loadConP0" %}
 4852 
 4853   ins_encode(riscv_enc_mov_zero(dst));
 4854 
 4855   ins_pipe(ialu_imm);
 4856 %}
 4857 
 4858 // Load Pointer Constant One
 4859 instruct loadConP1(iRegPNoSp dst, immP_1 con)
 4860 %{
 4861   match(Set dst con);
 4862 
 4863   ins_cost(ALU_COST);
 4864   format %{ "mv  $dst, $con\t# load ptr constant one, #@loadConP1" %}
 4865 
 4866   ins_encode(riscv_enc_mov_p1(dst));
 4867 
 4868   ins_pipe(ialu_imm);
 4869 %}
 4870 
 4871 // Load Byte Map Base Constant
 4872 instruct loadByteMapBase(iRegPNoSp dst, immByteMapBase con)
 4873 %{
 4874   match(Set dst con);
 4875   ins_cost(ALU_COST);
 4876   format %{ "mv  $dst, $con\t# Byte Map Base, #@loadByteMapBase" %}
 4877 
 4878   ins_encode(riscv_enc_mov_byte_map_base(dst));
 4879 
 4880   ins_pipe(ialu_imm);
 4881 %}
 4882 
 4883 // Load Narrow Pointer Constant
 4884 instruct loadConN(iRegNNoSp dst, immN con)
 4885 %{
 4886   match(Set dst con);
 4887 
 4888   ins_cost(ALU_COST * 4);
 4889   format %{ "mv  $dst, $con\t# compressed ptr, #@loadConN" %}
 4890 
 4891   ins_encode(riscv_enc_mov_n(dst, con));
 4892 
 4893   ins_pipe(ialu_imm);
 4894 %}
 4895 
 4896 // Load Narrow Null Pointer Constant
 4897 instruct loadConN0(iRegNNoSp dst, immN0 con)
 4898 %{
 4899   match(Set dst con);
 4900 
 4901   ins_cost(ALU_COST);
 4902   format %{ "mv  $dst, $con\t# compressed NULL ptr, #@loadConN0" %}
 4903 
 4904   ins_encode(riscv_enc_mov_zero(dst));
 4905 
 4906   ins_pipe(ialu_imm);
 4907 %}
 4908 
 4909 // Load Narrow Klass Constant
 4910 instruct loadConNKlass(iRegNNoSp dst, immNKlass con)
 4911 %{
 4912   match(Set dst con);
 4913 
 4914   ins_cost(ALU_COST * 6);
 4915   format %{ "mv  $dst, $con\t# compressed klass ptr, #@loadConNKlass" %}
 4916 
 4917   ins_encode(riscv_enc_mov_nk(dst, con));
 4918 
 4919   ins_pipe(ialu_imm);
 4920 %}
 4921 
 4922 // Load Float Constant
 4923 instruct loadConF(fRegF dst, immF con) %{
 4924   match(Set dst con);
 4925 
 4926   ins_cost(LOAD_COST);
 4927   format %{
 4928     "flw $dst, [$constantaddress]\t# load from constant table: float=$con, #@loadConF"
 4929   %}
 4930 
 4931   ins_encode %{
 4932     __ flw(as_FloatRegister($dst$$reg), $constantaddress($con));
 4933   %}
 4934 
 4935   ins_pipe(fp_load_constant_s);
 4936 %}
 4937 
 4938 instruct loadConF0(fRegF dst, immF0 con) %{
 4939   match(Set dst con);
 4940 
 4941   ins_cost(XFER_COST);
 4942 
 4943   format %{ "fmv.w.x $dst, zr\t# float, #@loadConF0" %}
 4944 
 4945   ins_encode %{
 4946     __ fmv_w_x(as_FloatRegister($dst$$reg), zr);
 4947   %}
 4948 
 4949   ins_pipe(fp_load_constant_s);
 4950 %}
 4951 
 4952 // Load Double Constant
 4953 instruct loadConD(fRegD dst, immD con) %{
 4954   match(Set dst con);
 4955 
 4956   ins_cost(LOAD_COST);
 4957   format %{
 4958     "fld $dst, [$constantaddress]\t# load from constant table: double=$con, #@loadConD"
 4959   %}
 4960 
 4961   ins_encode %{
 4962     __ fld(as_FloatRegister($dst$$reg), $constantaddress($con));
 4963   %}
 4964 
 4965   ins_pipe(fp_load_constant_d);
 4966 %}
 4967 
 4968 instruct loadConD0(fRegD dst, immD0 con) %{
 4969   match(Set dst con);
 4970 
 4971   ins_cost(XFER_COST);
 4972 
 4973   format %{ "fmv.d.x $dst, zr\t# double, #@loadConD0" %}
 4974 
 4975   ins_encode %{
 4976     __ fmv_d_x(as_FloatRegister($dst$$reg), zr);
 4977   %}
 4978 
 4979   ins_pipe(fp_load_constant_d);
 4980 %}
 4981 
 4982 // Store Instructions
 4983 // Store CMS card-mark Immediate
 4984 instruct storeimmCM0(immI0 zero, memory mem)
 4985 %{
 4986   match(Set mem (StoreCM mem zero));
 4987 
 4988   ins_cost(STORE_COST);
 4989   format %{ "storestore (elided)\n\t"
 4990             "sb zr, $mem\t# byte, #@storeimmCM0" %}
 4991 
 4992   ins_encode %{
 4993     __ sb(zr, Address(as_Register($mem$$base), $mem$$disp));
 4994   %}
 4995 
 4996   ins_pipe(istore_mem);
 4997 %}
 4998 
 4999 // Store CMS card-mark Immediate with intervening StoreStore
 5000 // needed when using CMS with no conditional card marking
 5001 instruct storeimmCM0_ordered(immI0 zero, memory mem)
 5002 %{
 5003   match(Set mem (StoreCM mem zero));
 5004 
 5005   ins_cost(ALU_COST + STORE_COST);
 5006   format %{ "membar(StoreStore)\n\t"
 5007             "sb zr, $mem\t# byte, #@storeimmCM0_ordered" %}
 5008 
 5009   ins_encode %{
 5010     __ membar(MacroAssembler::LoadStore | MacroAssembler::StoreStore);
 5011     __ sb(zr, Address(as_Register($mem$$base), $mem$$disp));
 5012   %}
 5013 
 5014   ins_pipe(istore_mem);
 5015 %}
 5016 
 5017 // Store Byte
 5018 instruct storeB(iRegIorL2I src, memory mem)
 5019 %{
 5020   match(Set mem (StoreB mem src));
 5021 
 5022   ins_cost(STORE_COST);
 5023   format %{ "sb  $src, $mem\t# byte, #@storeB" %}
 5024 
 5025   ins_encode %{
 5026     __ sb(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
 5027   %}
 5028 
 5029   ins_pipe(istore_reg_mem);
 5030 %}
 5031 
 5032 instruct storeimmB0(immI0 zero, memory mem)
 5033 %{
 5034   match(Set mem (StoreB mem zero));
 5035 
 5036   ins_cost(STORE_COST);
 5037   format %{ "sb zr, $mem\t# byte, #@storeimmB0" %}
 5038 
 5039   ins_encode %{
 5040     __ sb(zr, Address(as_Register($mem$$base), $mem$$disp));
 5041   %}
 5042 
 5043   ins_pipe(istore_mem);
 5044 %}
 5045 
 5046 // Store Char/Short
 5047 instruct storeC(iRegIorL2I src, memory mem)
 5048 %{
 5049   match(Set mem (StoreC mem src));
 5050 
 5051   ins_cost(STORE_COST);
 5052   format %{ "sh  $src, $mem\t# short, #@storeC" %}
 5053 
 5054   ins_encode %{
 5055     __ sh(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
 5056   %}
 5057 
 5058   ins_pipe(istore_reg_mem);
 5059 %}
 5060 
 5061 instruct storeimmC0(immI0 zero, memory mem)
 5062 %{
 5063   match(Set mem (StoreC mem zero));
 5064 
 5065   ins_cost(STORE_COST);
 5066   format %{ "sh  zr, $mem\t# short, #@storeimmC0" %}
 5067 
 5068   ins_encode %{
 5069     __ sh(zr, Address(as_Register($mem$$base), $mem$$disp));
 5070   %}
 5071 
 5072   ins_pipe(istore_mem);
 5073 %}
 5074 
 5075 // Store Integer
 5076 instruct storeI(iRegIorL2I src, memory mem)
 5077 %{
 5078   match(Set mem(StoreI mem src));
 5079 
 5080   ins_cost(STORE_COST);
 5081   format %{ "sw  $src, $mem\t# int, #@storeI" %}
 5082 
 5083   ins_encode %{
 5084     __ sw(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
 5085   %}
 5086 
 5087   ins_pipe(istore_reg_mem);
 5088 %}
 5089 
 5090 instruct storeimmI0(immI0 zero, memory mem)
 5091 %{
 5092   match(Set mem(StoreI mem zero));
 5093 
 5094   ins_cost(STORE_COST);
 5095   format %{ "sw  zr, $mem\t# int, #@storeimmI0" %}
 5096 
 5097   ins_encode %{
 5098     __ sw(zr, Address(as_Register($mem$$base), $mem$$disp));
 5099   %}
 5100 
 5101   ins_pipe(istore_mem);
 5102 %}
 5103 
 5104 // Store Long (64 bit signed)
 5105 instruct storeL(iRegL src, memory mem)
 5106 %{
 5107   match(Set mem (StoreL mem src));
 5108 
 5109   ins_cost(STORE_COST);
 5110   format %{ "sd  $src, $mem\t# long, #@storeL" %}
 5111 
 5112   ins_encode %{
 5113     __ sd(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
 5114   %}
 5115 
 5116   ins_pipe(istore_reg_mem);
 5117 %}
 5118 
 5119 // Store Long (64 bit signed)
 5120 instruct storeimmL0(immL0 zero, memory mem)
 5121 %{
 5122   match(Set mem (StoreL mem zero));
 5123 
 5124   ins_cost(STORE_COST);
 5125   format %{ "sd  zr, $mem\t# long, #@storeimmL0" %}
 5126 
 5127   ins_encode %{
 5128     __ sd(zr, Address(as_Register($mem$$base), $mem$$disp));
 5129   %}
 5130 
 5131   ins_pipe(istore_mem);
 5132 %}
 5133 
 5134 // Store Pointer
 5135 instruct storeP(iRegP src, memory mem)
 5136 %{
 5137   match(Set mem (StoreP mem src));
 5138   predicate(n->as_Store()->barrier_data() == 0);
 5139 
 5140   ins_cost(STORE_COST);
 5141   format %{ "sd  $src, $mem\t# ptr, #@storeP" %}
 5142 
 5143   ins_encode %{
 5144     __ sd(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
 5145   %}
 5146 
 5147   ins_pipe(istore_reg_mem);
 5148 %}
 5149 
 5150 // Store Pointer
 5151 instruct storeimmP0(immP0 zero, memory mem)
 5152 %{
 5153   match(Set mem (StoreP mem zero));
 5154   predicate(n->as_Store()->barrier_data() == 0);
 5155 
 5156   ins_cost(STORE_COST);
 5157   format %{ "sd zr, $mem\t# ptr, #@storeimmP0" %}
 5158 
 5159   ins_encode %{
 5160     __ sd(zr, Address(as_Register($mem$$base), $mem$$disp));
 5161   %}
 5162 
 5163   ins_pipe(istore_mem);
 5164 %}
 5165 
 5166 // Store Compressed Pointer
 5167 instruct storeN(iRegN src, memory mem)
 5168 %{
 5169   match(Set mem (StoreN mem src));
 5170 
 5171   ins_cost(STORE_COST);
 5172   format %{ "sw  $src, $mem\t# compressed ptr, #@storeN" %}
 5173 
 5174   ins_encode %{
 5175     __ sw(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
 5176   %}
 5177 
 5178   ins_pipe(istore_reg_mem);
 5179 %}
 5180 
 5181 instruct storeImmN0(iRegIHeapbase heapbase, immN0 zero, memory mem)
 5182 %{
 5183   match(Set mem (StoreN mem zero));
 5184 
 5185   ins_cost(STORE_COST);
 5186   format %{ "sw  rheapbase, $mem\t# compressed ptr (rheapbase==0), #@storeImmN0" %}
 5187 
 5188   ins_encode %{
 5189     __ sw(as_Register($heapbase$$reg), Address(as_Register($mem$$base), $mem$$disp));
 5190   %}
 5191 
 5192   ins_pipe(istore_reg_mem);
 5193 %}
 5194 
 5195 // Store Float
 5196 instruct storeF(fRegF src, memory mem)
 5197 %{
 5198   match(Set mem (StoreF mem src));
 5199 
 5200   ins_cost(STORE_COST);
 5201   format %{ "fsw  $src, $mem\t# float, #@storeF" %}
 5202 
 5203   ins_encode %{
 5204     __ fsw(as_FloatRegister($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
 5205   %}
 5206 
 5207   ins_pipe(fp_store_reg_s);
 5208 %}
 5209 
 5210 // Store Double
 5211 instruct storeD(fRegD src, memory mem)
 5212 %{
 5213   match(Set mem (StoreD mem src));
 5214 
 5215   ins_cost(STORE_COST);
 5216   format %{ "fsd  $src, $mem\t# double, #@storeD" %}
 5217 
 5218   ins_encode %{
 5219     __ fsd(as_FloatRegister($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
 5220   %}
 5221 
 5222   ins_pipe(fp_store_reg_d);
 5223 %}
 5224 
 5225 // Store Compressed Klass Pointer
 5226 instruct storeNKlass(iRegN src, memory mem)
 5227 %{
 5228   match(Set mem (StoreNKlass mem src));
 5229 
 5230   ins_cost(STORE_COST);
 5231   format %{ "sw  $src, $mem\t# compressed klass ptr, #@storeNKlass" %}
 5232 
 5233   ins_encode %{
 5234     __ sw(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
 5235   %}
 5236 
 5237   ins_pipe(istore_reg_mem);
 5238 %}
 5239 
 5240 // ============================================================================
 5241 // Prefetch instructions
 5242 // Must be safe to execute with invalid address (cannot fault).
 5243 
 5244 instruct prefetchalloc( memory mem ) %{
 5245   predicate(UseZicbop);
 5246   match(PrefetchAllocation mem);
 5247 
 5248   ins_cost(ALU_COST * 1);
 5249   format %{ "prefetch_w $mem\t# Prefetch for write" %}
 5250 
 5251   ins_encode %{
 5252     if (is_imm_in_range($mem$$disp, 12, 0)) {
 5253       if (($mem$$disp & 0x1f) == 0) {
 5254         __ prefetch_w(as_Register($mem$$base), $mem$$disp);
 5255       } else {
 5256         __ addi(t0, as_Register($mem$$base), $mem$$disp);
 5257         __ prefetch_w(t0, 0);
 5258       }
 5259     } else {
 5260       __ mv(t0, $mem$$disp);
 5261       __ add(t0, as_Register($mem$$base), t0);
 5262       __ prefetch_w(t0, 0);
 5263     }
 5264   %}
 5265 
 5266   ins_pipe(iload_prefetch);
 5267 %}
 5268 
 5269 // ============================================================================
 5270 // Atomic operation instructions
 5271 //
 5272 
 5273 // standard CompareAndSwapX when we are using barriers
 5274 // these have higher priority than the rules selected by a predicate
 5275 instruct compareAndSwapB(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
 5276                          iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
 5277 %{
 5278   match(Set res (CompareAndSwapB mem (Binary oldval newval)));
 5279 
 5280   ins_cost(LOAD_COST + STORE_COST + ALU_COST * 10 + BRANCH_COST * 4);
 5281 
 5282   effect(TEMP_DEF res, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3, KILL cr);
 5283 
 5284   format %{
 5285     "cmpxchg $mem, $oldval, $newval\t# (byte) if $mem == $oldval then $mem <-- $newval\n\t"
 5286     "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapB"
 5287   %}
 5288 
 5289   ins_encode %{
 5290     __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
 5291                             Assembler::relaxed /* acquire */, Assembler::rl /* release */, $res$$Register,
 5292                             true /* result as bool */, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
 5293   %}
 5294 
 5295   ins_pipe(pipe_slow);
 5296 %}
 5297 
 5298 instruct compareAndSwapS(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
 5299                          iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
 5300 %{
 5301   match(Set res (CompareAndSwapS mem (Binary oldval newval)));
 5302 
 5303   ins_cost(LOAD_COST + STORE_COST + ALU_COST * 11 + BRANCH_COST * 4);
 5304 
 5305   effect(TEMP_DEF res, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3, KILL cr);
 5306 
 5307   format %{
 5308     "cmpxchg $mem, $oldval, $newval\t# (short) if $mem == $oldval then $mem <-- $newval\n\t"
 5309     "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapS"
 5310   %}
 5311 
 5312   ins_encode %{
 5313     __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
 5314                             Assembler::relaxed /* acquire */, Assembler::rl /* release */, $res$$Register,
 5315                             true /* result as bool */, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
 5316   %}
 5317 
 5318   ins_pipe(pipe_slow);
 5319 %}
 5320 
 5321 instruct compareAndSwapI(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
 5322 %{
 5323   match(Set res (CompareAndSwapI mem (Binary oldval newval)));
 5324 
 5325   ins_cost(LOAD_COST + STORE_COST + ALU_COST * 6 + BRANCH_COST * 4);
 5326 
 5327   format %{
 5328     "cmpxchg $mem, $oldval, $newval\t# (int) if $mem == $oldval then $mem <-- $newval\n\t"
 5329     "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapI"
 5330   %}
 5331 
 5332   ins_encode(riscv_enc_cmpxchgw(res, mem, oldval, newval));
 5333 
 5334   ins_pipe(pipe_slow);
 5335 %}
 5336 
 5337 instruct compareAndSwapL(iRegINoSp res, indirect mem, iRegL oldval, iRegL newval)
 5338 %{
 5339   match(Set res (CompareAndSwapL mem (Binary oldval newval)));
 5340 
 5341   ins_cost(LOAD_COST + STORE_COST + ALU_COST * 6 + BRANCH_COST * 4);
 5342 
 5343   format %{
 5344     "cmpxchg $mem, $oldval, $newval\t# (long) if $mem == $oldval then $mem <-- $newval\n\t"
 5345     "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapL"
 5346   %}
 5347 
 5348   ins_encode(riscv_enc_cmpxchg(res, mem, oldval, newval));
 5349 
 5350   ins_pipe(pipe_slow);
 5351 %}
 5352 
 5353 instruct compareAndSwapP(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval)
 5354 %{
 5355   predicate(n->as_LoadStore()->barrier_data() == 0);
 5356 
 5357   match(Set res (CompareAndSwapP mem (Binary oldval newval)));
 5358 
 5359   ins_cost(LOAD_COST + STORE_COST + ALU_COST * 6 + BRANCH_COST * 4);
 5360 
 5361   format %{
 5362     "cmpxchg $mem, $oldval, $newval\t# (ptr) if $mem == $oldval then $mem <-- $newval\n\t"
 5363     "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapP"
 5364   %}
 5365 
 5366   ins_encode(riscv_enc_cmpxchg(res, mem, oldval, newval));
 5367 
 5368   ins_pipe(pipe_slow);
 5369 %}
 5370 
 5371 instruct compareAndSwapN(iRegINoSp res, indirect mem, iRegN oldval, iRegN newval)
 5372 %{
 5373   match(Set res (CompareAndSwapN mem (Binary oldval newval)));
 5374 
 5375   ins_cost(LOAD_COST + STORE_COST + ALU_COST * 8 + BRANCH_COST * 4);
 5376 
 5377   format %{
 5378     "cmpxchg $mem, $oldval, $newval\t# (narrow oop) if $mem == $oldval then $mem <-- $newval\n\t"
 5379     "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapN"
 5380   %}
 5381 
 5382   ins_encode(riscv_enc_cmpxchgn(res, mem, oldval, newval));
 5383 
 5384   ins_pipe(pipe_slow);
 5385 %}
 5386 
 5387 // alternative CompareAndSwapX when we are eliding barriers
 5388 instruct compareAndSwapBAcq(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
 5389                             iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
 5390 %{
 5391   predicate(needs_acquiring_load_reserved(n));
 5392 
 5393   match(Set res (CompareAndSwapB mem (Binary oldval newval)));
 5394 
 5395   ins_cost(LOAD_COST + STORE_COST + ALU_COST * 10 + BRANCH_COST * 4);
 5396 
 5397   effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
 5398 
 5399   format %{
 5400     "cmpxchg_acq $mem, $oldval, $newval\t# (byte) if $mem == $oldval then $mem <-- $newval\n\t"
 5401     "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapBAcq"
 5402   %}
 5403 
 5404   ins_encode %{
 5405     __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
 5406                             Assembler::aq /* acquire */, Assembler::rl /* release */, $res$$Register,
 5407                             true /* result as bool */, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
 5408   %}
 5409 
 5410   ins_pipe(pipe_slow);
 5411 %}
 5412 
 5413 instruct compareAndSwapSAcq(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
 5414                             iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
 5415 %{
 5416   predicate(needs_acquiring_load_reserved(n));
 5417 
 5418   match(Set res (CompareAndSwapS mem (Binary oldval newval)));
 5419 
 5420   ins_cost(LOAD_COST + STORE_COST + ALU_COST * 11 + BRANCH_COST * 4);
 5421 
 5422   effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
 5423 
 5424   format %{
 5425     "cmpxchg_acq $mem, $oldval, $newval\t# (short) if $mem == $oldval then $mem <-- $newval\n\t"
 5426     "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapSAcq"
 5427   %}
 5428 
 5429   ins_encode %{
 5430     __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
 5431                             Assembler::aq /* acquire */, Assembler::rl /* release */, $res$$Register,
 5432                             true /* result as bool */, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
 5433   %}
 5434 
 5435   ins_pipe(pipe_slow);
 5436 %}
 5437 
 5438 instruct compareAndSwapIAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
 5439 %{
 5440   predicate(needs_acquiring_load_reserved(n));
 5441 
 5442   match(Set res (CompareAndSwapI mem (Binary oldval newval)));
 5443 
 5444   ins_cost(LOAD_COST + STORE_COST + ALU_COST * 6 + BRANCH_COST * 4);
 5445 
 5446   format %{
 5447     "cmpxchg_acq $mem, $oldval, $newval\t# (int) if $mem == $oldval then $mem <-- $newval\n\t"
 5448     "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapIAcq"
 5449   %}
 5450 
 5451   ins_encode(riscv_enc_cmpxchgw_acq(res, mem, oldval, newval));
 5452 
 5453   ins_pipe(pipe_slow);
 5454 %}
 5455 
 5456 instruct compareAndSwapLAcq(iRegINoSp res, indirect mem, iRegL oldval, iRegL newval)
 5457 %{
 5458   predicate(needs_acquiring_load_reserved(n));
 5459 
 5460   match(Set res (CompareAndSwapL mem (Binary oldval newval)));
 5461 
 5462   ins_cost(LOAD_COST + STORE_COST + ALU_COST * 6 + BRANCH_COST * 4);
 5463 
 5464   format %{
 5465     "cmpxchg_acq $mem, $oldval, $newval\t# (long) if $mem == $oldval then $mem <-- $newval\n\t"
 5466     "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapLAcq"
 5467   %}
 5468 
 5469   ins_encode(riscv_enc_cmpxchg_acq(res, mem, oldval, newval));
 5470 
 5471   ins_pipe(pipe_slow);
 5472 %}
 5473 
 5474 instruct compareAndSwapPAcq(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval)
 5475 %{
 5476   predicate(needs_acquiring_load_reserved(n) && (n->as_LoadStore()->barrier_data() == 0));
 5477 
 5478   match(Set res (CompareAndSwapP mem (Binary oldval newval)));
 5479 
 5480   ins_cost(LOAD_COST + STORE_COST + ALU_COST * 6 + BRANCH_COST * 4);
 5481 
 5482   format %{
 5483     "cmpxchg_acq $mem, $oldval, $newval\t# (ptr) if $mem == $oldval then $mem <-- $newval\n\t"
 5484     "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapPAcq"
 5485   %}
 5486 
 5487   ins_encode(riscv_enc_cmpxchg_acq(res, mem, oldval, newval));
 5488 
 5489   ins_pipe(pipe_slow);
 5490 %}
 5491 
 5492 instruct compareAndSwapNAcq(iRegINoSp res, indirect mem, iRegN oldval, iRegN newval)
 5493 %{
 5494   predicate(needs_acquiring_load_reserved(n));
 5495 
 5496   match(Set res (CompareAndSwapN mem (Binary oldval newval)));
 5497 
 5498   ins_cost(LOAD_COST + STORE_COST + ALU_COST * 8 + BRANCH_COST * 4);
 5499 
 5500   format %{
 5501     "cmpxchg_acq $mem, $oldval, $newval\t# (narrow oop) if $mem == $oldval then $mem <-- $newval\n\t"
 5502     "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapNAcq"
 5503   %}
 5504 
 5505   ins_encode(riscv_enc_cmpxchgn_acq(res, mem, oldval, newval));
 5506 
 5507   ins_pipe(pipe_slow);
 5508 %}
 5509 
 5510 // Sundry CAS operations.  Note that release is always true,
 5511 // regardless of the memory ordering of the CAS.  This is because we
 5512 // need the volatile case to be sequentially consistent but there is
 5513 // no trailing StoreLoad barrier emitted by C2.  Unfortunately we
 5514 // can't check the type of memory ordering here, so we always emit a
 5515 // sc_d(w) with rl bit set.
 5516 instruct compareAndExchangeB(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
 5517                              iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
 5518 %{
 5519   match(Set res (CompareAndExchangeB mem (Binary oldval newval)));
 5520 
 5521   ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST * 5);
 5522 
 5523   effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
 5524 
 5525   format %{
 5526     "cmpxchg $res = $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeB"
 5527   %}
 5528 
 5529   ins_encode %{
 5530     __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
 5531                             /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
 5532                             /*result_as_bool*/ false, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
 5533   %}
 5534 
 5535   ins_pipe(pipe_slow);
 5536 %}
 5537 
 5538 instruct compareAndExchangeS(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
 5539                              iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
 5540 %{
 5541   match(Set res (CompareAndExchangeS mem (Binary oldval newval)));
 5542 
 5543   ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST * 6);
 5544 
 5545   effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
 5546 
 5547   format %{
 5548     "cmpxchg $res = $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeS"
 5549   %}
 5550 
 5551   ins_encode %{
 5552     __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
 5553                             /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
 5554                             /*result_as_bool*/ false, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
 5555   %}
 5556 
 5557   ins_pipe(pipe_slow);
 5558 %}
 5559 
 5560 instruct compareAndExchangeI(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
 5561 %{
 5562   match(Set res (CompareAndExchangeI mem (Binary oldval newval)));
 5563 
 5564   ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST);
 5565 
 5566   effect(TEMP_DEF res);
 5567 
 5568   format %{
 5569     "cmpxchg $res = $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeI"
 5570   %}
 5571 
 5572   ins_encode %{
 5573     __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
 5574                /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
 5575   %}
 5576 
 5577   ins_pipe(pipe_slow);
 5578 %}
 5579 
 5580 instruct compareAndExchangeL(iRegLNoSp res, indirect mem, iRegL oldval, iRegL newval)
 5581 %{
 5582   match(Set res (CompareAndExchangeL mem (Binary oldval newval)));
 5583 
 5584   ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST);
 5585 
 5586   effect(TEMP_DEF res);
 5587 
 5588   format %{
 5589     "cmpxchg $res = $mem, $oldval, $newval\t# (long, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeL"
 5590   %}
 5591 
 5592   ins_encode %{
 5593     __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
 5594                /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
 5595   %}
 5596 
 5597   ins_pipe(pipe_slow);
 5598 %}
 5599 
 5600 instruct compareAndExchangeN(iRegNNoSp res, indirect mem, iRegN oldval, iRegN newval)
 5601 %{
 5602   match(Set res (CompareAndExchangeN mem (Binary oldval newval)));
 5603 
 5604   ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST * 3);
 5605 
 5606   effect(TEMP_DEF res);
 5607 
 5608   format %{
 5609     "cmpxchg $res = $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeN"
 5610   %}
 5611 
 5612   ins_encode %{
 5613     __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
 5614                /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
 5615   %}
 5616 
 5617   ins_pipe(pipe_slow);
 5618 %}
 5619 
 5620 instruct compareAndExchangeP(iRegPNoSp res, indirect mem, iRegP oldval, iRegP newval)
 5621 %{
 5622   predicate(n->as_LoadStore()->barrier_data() == 0);
 5623   match(Set res (CompareAndExchangeP mem (Binary oldval newval)));
 5624 
 5625   ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST);
 5626 
 5627   effect(TEMP_DEF res);
 5628 
 5629   format %{
 5630     "cmpxchg $res = $mem, $oldval, $newval\t# (ptr, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeP"
 5631   %}
 5632 
 5633   ins_encode %{
 5634     __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
 5635                /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
 5636   %}
 5637 
 5638   ins_pipe(pipe_slow);
 5639 %}
 5640 
 5641 instruct compareAndExchangeBAcq(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
 5642                                 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
 5643 %{
 5644   predicate(needs_acquiring_load_reserved(n));
 5645 
 5646   match(Set res (CompareAndExchangeB mem (Binary oldval newval)));
 5647 
 5648   ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST * 5);
 5649 
 5650   effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
 5651 
 5652   format %{
 5653     "cmpxchg_acq $res = $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeBAcq"
 5654   %}
 5655 
 5656   ins_encode %{
 5657     __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
 5658                             /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
 5659                             /*result_as_bool*/ false, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
 5660   %}
 5661 
 5662   ins_pipe(pipe_slow);
 5663 %}
 5664 
 5665 instruct compareAndExchangeSAcq(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
 5666                                 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
 5667 %{
 5668   predicate(needs_acquiring_load_reserved(n));
 5669 
 5670   match(Set res (CompareAndExchangeS mem (Binary oldval newval)));
 5671 
 5672   ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST * 6);
 5673 
 5674   effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
 5675 
 5676   format %{
 5677     "cmpxchg_acq $res = $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeSAcq"
 5678   %}
 5679 
 5680   ins_encode %{
 5681     __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
 5682                             /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
 5683                             /*result_as_bool*/ false, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
 5684   %}
 5685 
 5686   ins_pipe(pipe_slow);
 5687 %}
 5688 
 5689 instruct compareAndExchangeIAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
 5690 %{
 5691   predicate(needs_acquiring_load_reserved(n));
 5692 
 5693   match(Set res (CompareAndExchangeI mem (Binary oldval newval)));
 5694 
 5695   ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST);
 5696 
 5697   effect(TEMP_DEF res);
 5698 
 5699   format %{
 5700     "cmpxchg_acq $res = $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeIAcq"
 5701   %}
 5702 
 5703   ins_encode %{
 5704     __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
 5705                /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
 5706   %}
 5707 
 5708   ins_pipe(pipe_slow);
 5709 %}
 5710 
 5711 instruct compareAndExchangeLAcq(iRegLNoSp res, indirect mem, iRegL oldval, iRegL newval)
 5712 %{
 5713   predicate(needs_acquiring_load_reserved(n));
 5714 
 5715   match(Set res (CompareAndExchangeL mem (Binary oldval newval)));
 5716 
 5717   ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST);
 5718 
 5719   effect(TEMP_DEF res);
 5720 
 5721   format %{
 5722     "cmpxchg_acq $res = $mem, $oldval, $newval\t# (long, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeLAcq"
 5723   %}
 5724 
 5725   ins_encode %{
 5726     __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
 5727                /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
 5728   %}
 5729 
 5730   ins_pipe(pipe_slow);
 5731 %}
 5732 
 5733 instruct compareAndExchangeNAcq(iRegNNoSp res, indirect mem, iRegN oldval, iRegN newval)
 5734 %{
 5735   predicate(needs_acquiring_load_reserved(n));
 5736 
 5737   match(Set res (CompareAndExchangeN mem (Binary oldval newval)));
 5738 
 5739   ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST);
 5740 
 5741   effect(TEMP_DEF res);
 5742 
 5743   format %{
 5744     "cmpxchg_acq $res = $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeNAcq"
 5745   %}
 5746 
 5747   ins_encode %{
 5748     __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
 5749                /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
 5750   %}
 5751 
 5752   ins_pipe(pipe_slow);
 5753 %}
 5754 
 5755 instruct compareAndExchangePAcq(iRegPNoSp res, indirect mem, iRegP oldval, iRegP newval)
 5756 %{
 5757   predicate(needs_acquiring_load_reserved(n) && (n->as_LoadStore()->barrier_data() == 0));
 5758 
 5759   match(Set res (CompareAndExchangeP mem (Binary oldval newval)));
 5760 
 5761   ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST);
 5762 
 5763   effect(TEMP_DEF res);
 5764 
 5765   format %{
 5766     "cmpxchg_acq $res = $mem, $oldval, $newval\t# (ptr, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangePAcq"
 5767   %}
 5768 
 5769   ins_encode %{
 5770     __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
 5771                /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
 5772   %}
 5773 
 5774   ins_pipe(pipe_slow);
 5775 %}
 5776 
 5777 instruct weakCompareAndSwapB(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
 5778                              iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
 5779 %{
 5780   match(Set res (WeakCompareAndSwapB mem (Binary oldval newval)));
 5781 
 5782   ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 6);
 5783 
 5784   effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
 5785 
 5786   format %{
 5787     "cmpxchg_weak $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval\n\t"
 5788     "# $res == 1 when success, #@weakCompareAndSwapB"
 5789   %}
 5790 
 5791   ins_encode %{
 5792     __ weak_cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
 5793                                  /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
 5794                                  $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
 5795   %}
 5796 
 5797   ins_pipe(pipe_slow);
 5798 %}
 5799 
 5800 instruct weakCompareAndSwapS(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
 5801                              iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
 5802 %{
 5803   match(Set res (WeakCompareAndSwapS mem (Binary oldval newval)));
 5804 
 5805   ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 7);
 5806 
 5807   effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
 5808 
 5809   format %{
 5810     "cmpxchg_weak $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval\n\t"
 5811     "# $res == 1 when success, #@weakCompareAndSwapS"
 5812   %}
 5813 
 5814   ins_encode %{
 5815     __ weak_cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
 5816                                  /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
 5817                                  $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
 5818   %}
 5819 
 5820   ins_pipe(pipe_slow);
 5821 %}
 5822 
 5823 instruct weakCompareAndSwapI(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
 5824 %{
 5825   match(Set res (WeakCompareAndSwapI mem (Binary oldval newval)));
 5826 
 5827   ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 2);
 5828 
 5829   format %{
 5830     "cmpxchg_weak $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval\n\t"
 5831     "# $res == 1 when success, #@weakCompareAndSwapI"
 5832   %}
 5833 
 5834   ins_encode %{
 5835     __ cmpxchg_weak(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
 5836                     /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
 5837   %}
 5838 
 5839   ins_pipe(pipe_slow);
 5840 %}
 5841 
 5842 instruct weakCompareAndSwapL(iRegINoSp res, indirect mem, iRegL oldval, iRegL newval)
 5843 %{
 5844   match(Set res (WeakCompareAndSwapL mem (Binary oldval newval)));
 5845 
 5846   ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 2);
 5847 
 5848   format %{
 5849     "cmpxchg_weak $mem, $oldval, $newval\t# (long, weak) if $mem == $oldval then $mem <-- $newval\n\t"
 5850     "# $res == 1 when success, #@weakCompareAndSwapL"
 5851   %}
 5852 
 5853   ins_encode %{
 5854     __ cmpxchg_weak(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
 5855                     /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
 5856   %}
 5857 
 5858   ins_pipe(pipe_slow);
 5859 %}
 5860 
 5861 instruct weakCompareAndSwapN(iRegINoSp res, indirect mem, iRegN oldval, iRegN newval)
 5862 %{
 5863   match(Set res (WeakCompareAndSwapN mem (Binary oldval newval)));
 5864 
 5865   ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 4);
 5866 
 5867   format %{
 5868     "cmpxchg_weak $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval\n\t"
 5869     "# $res == 1 when success, #@weakCompareAndSwapN"
 5870   %}
 5871 
 5872   ins_encode %{
 5873     __ cmpxchg_weak(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
 5874                     /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
 5875   %}
 5876 
 5877   ins_pipe(pipe_slow);
 5878 %}
 5879 
 5880 instruct weakCompareAndSwapP(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval)
 5881 %{
 5882   predicate(n->as_LoadStore()->barrier_data() == 0);
 5883   match(Set res (WeakCompareAndSwapP mem (Binary oldval newval)));
 5884 
 5885   ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 2);
 5886 
 5887   format %{
 5888     "cmpxchg_weak $mem, $oldval, $newval\t# (ptr, weak) if $mem == $oldval then $mem <-- $newval\n\t"
 5889     "# $res == 1 when success, #@weakCompareAndSwapP"
 5890   %}
 5891 
 5892   ins_encode %{
 5893     __ cmpxchg_weak(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
 5894                     /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
 5895   %}
 5896 
 5897   ins_pipe(pipe_slow);
 5898 %}
 5899 
 5900 instruct weakCompareAndSwapBAcq(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
 5901                                 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
 5902 %{
 5903   predicate(needs_acquiring_load_reserved(n));
 5904 
 5905   match(Set res (WeakCompareAndSwapB mem (Binary oldval newval)));
 5906 
 5907   ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 6);
 5908 
 5909   effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
 5910 
 5911   format %{
 5912     "cmpxchg_weak_acq $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval\n\t"
 5913     "# $res == 1 when success, #@weakCompareAndSwapBAcq"
 5914   %}
 5915 
 5916   ins_encode %{
 5917     __ weak_cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
 5918                                  /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
 5919                                  $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
 5920   %}
 5921 
 5922   ins_pipe(pipe_slow);
 5923 %}
 5924 
 5925 instruct weakCompareAndSwapSAcq(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
 5926                                 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
 5927 %{
 5928   predicate(needs_acquiring_load_reserved(n));
 5929 
 5930   match(Set res (WeakCompareAndSwapS mem (Binary oldval newval)));
 5931 
 5932   ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 7);
 5933 
 5934   effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
 5935 
 5936   format %{
 5937     "cmpxchg_weak_acq $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval\n\t"
 5938     "# $res == 1 when success, #@weakCompareAndSwapSAcq"
 5939   %}
 5940 
 5941   ins_encode %{
 5942     __ weak_cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
 5943                                  /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
 5944                                  $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
 5945   %}
 5946 
 5947   ins_pipe(pipe_slow);
 5948 %}
 5949 
 5950 instruct weakCompareAndSwapIAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
 5951 %{
 5952   predicate(needs_acquiring_load_reserved(n));
 5953 
 5954   match(Set res (WeakCompareAndSwapI mem (Binary oldval newval)));
 5955 
 5956   ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 2);
 5957 
 5958   format %{
 5959     "cmpxchg_weak_acq $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval\n\t"
 5960     "# $res == 1 when success, #@weakCompareAndSwapIAcq"
 5961   %}
 5962 
 5963   ins_encode %{
 5964     __ cmpxchg_weak(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
 5965                     /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
 5966   %}
 5967 
 5968   ins_pipe(pipe_slow);
 5969 %}
 5970 
 5971 instruct weakCompareAndSwapLAcq(iRegINoSp res, indirect mem, iRegL oldval, iRegL newval)
 5972 %{
 5973   predicate(needs_acquiring_load_reserved(n));
 5974 
 5975   match(Set res (WeakCompareAndSwapL mem (Binary oldval newval)));
 5976 
 5977   ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 2);
 5978 
 5979   format %{
 5980     "cmpxchg_weak_acq $mem, $oldval, $newval\t# (long, weak) if $mem == $oldval then $mem <-- $newval\n\t"
 5981     "# $res == 1 when success, #@weakCompareAndSwapLAcq"
 5982   %}
 5983 
 5984   ins_encode %{
 5985     __ cmpxchg_weak(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
 5986                     /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
 5987   %}
 5988 
 5989   ins_pipe(pipe_slow);
 5990 %}
 5991 
 5992 instruct weakCompareAndSwapNAcq(iRegINoSp res, indirect mem, iRegN oldval, iRegN newval)
 5993 %{
 5994   predicate(needs_acquiring_load_reserved(n));
 5995 
 5996   match(Set res (WeakCompareAndSwapN mem (Binary oldval newval)));
 5997 
 5998   ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 4);
 5999 
 6000   format %{
 6001     "cmpxchg_weak_acq $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval\n\t"
 6002     "# $res == 1 when success, #@weakCompareAndSwapNAcq"
 6003   %}
 6004 
 6005   ins_encode %{
 6006     __ cmpxchg_weak(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
 6007                     /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
 6008   %}
 6009 
 6010   ins_pipe(pipe_slow);
 6011 %}
 6012 
 6013 instruct weakCompareAndSwapPAcq(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval)
 6014 %{
 6015   predicate(needs_acquiring_load_reserved(n) && (n->as_LoadStore()->barrier_data() == 0));
 6016 
 6017   match(Set res (WeakCompareAndSwapP mem (Binary oldval newval)));
 6018 
 6019   ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 2);
 6020 
 6021   format %{
 6022     "cmpxchg_weak_acq $mem, $oldval, $newval\t# (ptr, weak) if $mem == $oldval then $mem <-- $newval\n\t"
 6023     "\t# $res == 1 when success, #@weakCompareAndSwapPAcq"
 6024   %}
 6025 
 6026   ins_encode %{
 6027     __ cmpxchg_weak(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
 6028                     /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
 6029   %}
 6030 
 6031   ins_pipe(pipe_slow);
 6032 %}
 6033 
 6034 instruct get_and_setI(indirect mem, iRegI newv, iRegINoSp prev)
 6035 %{
 6036   match(Set prev (GetAndSetI mem newv));
 6037 
 6038   ins_cost(ALU_COST);
 6039 
 6040   format %{ "atomic_xchgw  $prev, $newv, [$mem]\t#@get_and_setI" %}
 6041 
 6042   ins_encode %{
 6043     __ atomic_xchgw($prev$$Register, $newv$$Register, as_Register($mem$$base));
 6044   %}
 6045 
 6046   ins_pipe(pipe_serial);
 6047 %}
 6048 
 6049 instruct get_and_setL(indirect mem, iRegL newv, iRegLNoSp prev)
 6050 %{
 6051   match(Set prev (GetAndSetL mem newv));
 6052 
 6053   ins_cost(ALU_COST);
 6054 
 6055   format %{ "atomic_xchg  $prev, $newv, [$mem]\t#@get_and_setL" %}
 6056 
 6057   ins_encode %{
 6058     __ atomic_xchg($prev$$Register, $newv$$Register, as_Register($mem$$base));
 6059   %}
 6060 
 6061   ins_pipe(pipe_serial);
 6062 %}
 6063 
 6064 instruct get_and_setN(indirect mem, iRegN newv, iRegINoSp prev)
 6065 %{
 6066   match(Set prev (GetAndSetN mem newv));
 6067 
 6068   ins_cost(ALU_COST);
 6069 
 6070   format %{ "atomic_xchgwu $prev, $newv, [$mem]\t#@get_and_setN" %}
 6071 
 6072   ins_encode %{
 6073     __ atomic_xchgwu($prev$$Register, $newv$$Register, as_Register($mem$$base));
 6074   %}
 6075 
 6076   ins_pipe(pipe_serial);
 6077 %}
 6078 
 6079 instruct get_and_setP(indirect mem, iRegP newv, iRegPNoSp prev)
 6080 %{
 6081   predicate(n->as_LoadStore()->barrier_data() == 0);
 6082   match(Set prev (GetAndSetP mem newv));
 6083 
 6084   ins_cost(ALU_COST);
 6085 
 6086   format %{ "atomic_xchg  $prev, $newv, [$mem]\t#@get_and_setP" %}
 6087 
 6088   ins_encode %{
 6089     __ atomic_xchg($prev$$Register, $newv$$Register, as_Register($mem$$base));
 6090   %}
 6091 
 6092   ins_pipe(pipe_serial);
 6093 %}
 6094 
 6095 instruct get_and_setIAcq(indirect mem, iRegI newv, iRegINoSp prev)
 6096 %{
 6097   predicate(needs_acquiring_load_reserved(n));
 6098 
 6099   match(Set prev (GetAndSetI mem newv));
 6100 
 6101   ins_cost(ALU_COST);
 6102 
 6103   format %{ "atomic_xchgw_acq  $prev, $newv, [$mem]\t#@get_and_setIAcq" %}
 6104 
 6105   ins_encode %{
 6106     __ atomic_xchgalw($prev$$Register, $newv$$Register, as_Register($mem$$base));
 6107   %}
 6108 
 6109   ins_pipe(pipe_serial);
 6110 %}
 6111 
 6112 instruct get_and_setLAcq(indirect mem, iRegL newv, iRegLNoSp prev)
 6113 %{
 6114   predicate(needs_acquiring_load_reserved(n));
 6115 
 6116   match(Set prev (GetAndSetL mem newv));
 6117 
 6118   ins_cost(ALU_COST);
 6119 
 6120   format %{ "atomic_xchg_acq  $prev, $newv, [$mem]\t#@get_and_setLAcq" %}
 6121 
 6122   ins_encode %{
 6123     __ atomic_xchgal($prev$$Register, $newv$$Register, as_Register($mem$$base));
 6124   %}
 6125 
 6126   ins_pipe(pipe_serial);
 6127 %}
 6128 
 6129 instruct get_and_setNAcq(indirect mem, iRegN newv, iRegINoSp prev)
 6130 %{
 6131   predicate(needs_acquiring_load_reserved(n));
 6132 
 6133   match(Set prev (GetAndSetN mem newv));
 6134 
 6135   ins_cost(ALU_COST);
 6136 
 6137   format %{ "atomic_xchgwu_acq $prev, $newv, [$mem]\t#@get_and_setNAcq" %}
 6138 
 6139   ins_encode %{
 6140     __ atomic_xchgalwu($prev$$Register, $newv$$Register, as_Register($mem$$base));
 6141   %}
 6142 
 6143   ins_pipe(pipe_serial);
 6144 %}
 6145 
 6146 instruct get_and_setPAcq(indirect mem, iRegP newv, iRegPNoSp prev)
 6147 %{
 6148   predicate(needs_acquiring_load_reserved(n) && (n->as_LoadStore()->barrier_data() == 0));
 6149 
 6150   match(Set prev (GetAndSetP mem newv));
 6151 
 6152   ins_cost(ALU_COST);
 6153 
 6154   format %{ "atomic_xchg_acq  $prev, $newv, [$mem]\t#@get_and_setPAcq" %}
 6155 
 6156   ins_encode %{
 6157     __ atomic_xchgal($prev$$Register, $newv$$Register, as_Register($mem$$base));
 6158   %}
 6159 
 6160   ins_pipe(pipe_serial);
 6161 %}
 6162 
 6163 instruct get_and_addL(indirect mem, iRegLNoSp newval, iRegL incr)
 6164 %{
 6165   match(Set newval (GetAndAddL mem incr));
 6166 
 6167   ins_cost(ALU_COST);
 6168 
 6169   format %{ "get_and_addL $newval, [$mem], $incr\t#@get_and_addL" %}
 6170 
 6171   ins_encode %{
 6172     __ atomic_add($newval$$Register, $incr$$Register, as_Register($mem$$base));
 6173   %}
 6174 
 6175   ins_pipe(pipe_serial);
 6176 %}
 6177 
 6178 instruct get_and_addL_no_res(indirect mem, Universe dummy, iRegL incr)
 6179 %{
 6180   predicate(n->as_LoadStore()->result_not_used());
 6181 
 6182   match(Set dummy (GetAndAddL mem incr));
 6183 
 6184   ins_cost(ALU_COST);
 6185 
 6186   format %{ "get_and_addL [$mem], $incr\t#@get_and_addL_no_res" %}
 6187 
 6188   ins_encode %{
 6189     __ atomic_add(noreg, $incr$$Register, as_Register($mem$$base));
 6190   %}
 6191 
 6192   ins_pipe(pipe_serial);
 6193 %}
 6194 
 6195 instruct get_and_addLi(indirect mem, iRegLNoSp newval, immLAdd incr)
 6196 %{
 6197   match(Set newval (GetAndAddL mem incr));
 6198 
 6199   ins_cost(ALU_COST);
 6200 
 6201   format %{ "get_and_addL $newval, [$mem], $incr\t#@get_and_addLi" %}
 6202 
 6203   ins_encode %{
 6204     __ atomic_add($newval$$Register, $incr$$constant, as_Register($mem$$base));
 6205   %}
 6206 
 6207   ins_pipe(pipe_serial);
 6208 %}
 6209 
 6210 instruct get_and_addLi_no_res(indirect mem, Universe dummy, immLAdd incr)
 6211 %{
 6212   predicate(n->as_LoadStore()->result_not_used());
 6213 
 6214   match(Set dummy (GetAndAddL mem incr));
 6215 
 6216   ins_cost(ALU_COST);
 6217 
 6218   format %{ "get_and_addL [$mem], $incr\t#@get_and_addLi_no_res" %}
 6219 
 6220   ins_encode %{
 6221     __ atomic_add(noreg, $incr$$constant, as_Register($mem$$base));
 6222   %}
 6223 
 6224   ins_pipe(pipe_serial);
 6225 %}
 6226 
 6227 instruct get_and_addI(indirect mem, iRegINoSp newval, iRegIorL2I incr)
 6228 %{
 6229   match(Set newval (GetAndAddI mem incr));
 6230 
 6231   ins_cost(ALU_COST);
 6232 
 6233   format %{ "get_and_addI $newval, [$mem], $incr\t#@get_and_addI" %}
 6234 
 6235   ins_encode %{
 6236     __ atomic_addw($newval$$Register, $incr$$Register, as_Register($mem$$base));
 6237   %}
 6238 
 6239   ins_pipe(pipe_serial);
 6240 %}
 6241 
 6242 instruct get_and_addI_no_res(indirect mem, Universe dummy, iRegIorL2I incr)
 6243 %{
 6244   predicate(n->as_LoadStore()->result_not_used());
 6245 
 6246   match(Set dummy (GetAndAddI mem incr));
 6247 
 6248   ins_cost(ALU_COST);
 6249 
 6250   format %{ "get_and_addI [$mem], $incr\t#@get_and_addI_no_res" %}
 6251 
 6252   ins_encode %{
 6253     __ atomic_addw(noreg, $incr$$Register, as_Register($mem$$base));
 6254   %}
 6255 
 6256   ins_pipe(pipe_serial);
 6257 %}
 6258 
 6259 instruct get_and_addIi(indirect mem, iRegINoSp newval, immIAdd incr)
 6260 %{
 6261   match(Set newval (GetAndAddI mem incr));
 6262 
 6263   ins_cost(ALU_COST);
 6264 
 6265   format %{ "get_and_addI $newval, [$mem], $incr\t#@get_and_addIi" %}
 6266 
 6267   ins_encode %{
 6268     __ atomic_addw($newval$$Register, $incr$$constant, as_Register($mem$$base));
 6269   %}
 6270 
 6271   ins_pipe(pipe_serial);
 6272 %}
 6273 
 6274 instruct get_and_addIi_no_res(indirect mem, Universe dummy, immIAdd incr)
 6275 %{
 6276   predicate(n->as_LoadStore()->result_not_used());
 6277 
 6278   match(Set dummy (GetAndAddI mem incr));
 6279 
 6280   ins_cost(ALU_COST);
 6281 
 6282   format %{ "get_and_addI [$mem], $incr\t#@get_and_addIi_no_res" %}
 6283 
 6284   ins_encode %{
 6285     __ atomic_addw(noreg, $incr$$constant, as_Register($mem$$base));
 6286   %}
 6287 
 6288   ins_pipe(pipe_serial);
 6289 %}
 6290 
 6291 instruct get_and_addLAcq(indirect mem, iRegLNoSp newval, iRegL incr)
 6292 %{
 6293   predicate(needs_acquiring_load_reserved(n));
 6294 
 6295   match(Set newval (GetAndAddL mem incr));
 6296 
 6297   ins_cost(ALU_COST);
 6298 
 6299   format %{ "get_and_addL_acq $newval, [$mem], $incr\t#@get_and_addLAcq" %}
 6300 
 6301   ins_encode %{
 6302     __ atomic_addal($newval$$Register, $incr$$Register, as_Register($mem$$base));
 6303   %}
 6304 
 6305   ins_pipe(pipe_serial);
 6306 %}
 6307 
 6308 instruct get_and_addL_no_resAcq(indirect mem, Universe dummy, iRegL incr) %{
 6309   predicate(n->as_LoadStore()->result_not_used() && needs_acquiring_load_reserved(n));
 6310 
 6311   match(Set dummy (GetAndAddL mem incr));
 6312 
 6313   ins_cost(ALU_COST);
 6314 
 6315   format %{ "get_and_addL_acq [$mem], $incr\t#@get_and_addL_no_resAcq" %}
 6316 
 6317   ins_encode %{
 6318     __ atomic_addal(noreg, $incr$$Register, as_Register($mem$$base));
 6319   %}
 6320 
 6321   ins_pipe(pipe_serial);
 6322 %}
 6323 
 6324 instruct get_and_addLiAcq(indirect mem, iRegLNoSp newval, immLAdd incr)
 6325 %{
 6326   predicate(needs_acquiring_load_reserved(n));
 6327 
 6328   match(Set newval (GetAndAddL mem incr));
 6329 
 6330   ins_cost(ALU_COST);
 6331 
 6332   format %{ "get_and_addL_acq $newval, [$mem], $incr\t#@get_and_addLiAcq" %}
 6333 
 6334   ins_encode %{
 6335     __ atomic_addal($newval$$Register, $incr$$constant, as_Register($mem$$base));
 6336   %}
 6337 
 6338   ins_pipe(pipe_serial);
 6339 %}
 6340 
 6341 instruct get_and_addLi_no_resAcq(indirect mem, Universe dummy, immLAdd incr)
 6342 %{
 6343   predicate(n->as_LoadStore()->result_not_used() && needs_acquiring_load_reserved(n));
 6344 
 6345   match(Set dummy (GetAndAddL mem incr));
 6346 
 6347   ins_cost(ALU_COST);
 6348 
 6349   format %{ "get_and_addL_acq [$mem], $incr\t#@get_and_addLi_no_resAcq" %}
 6350 
 6351   ins_encode %{
 6352     __ atomic_addal(noreg, $incr$$constant, as_Register($mem$$base));
 6353   %}
 6354 
 6355   ins_pipe(pipe_serial);
 6356 %}
 6357 
 6358 instruct get_and_addIAcq(indirect mem, iRegINoSp newval, iRegIorL2I incr)
 6359 %{
 6360   predicate(needs_acquiring_load_reserved(n));
 6361 
 6362   match(Set newval (GetAndAddI mem incr));
 6363 
 6364   ins_cost(ALU_COST);
 6365 
 6366   format %{ "get_and_addI_acq $newval, [$mem], $incr\t#@get_and_addIAcq" %}
 6367 
 6368   ins_encode %{
 6369     __ atomic_addalw($newval$$Register, $incr$$Register, as_Register($mem$$base));
 6370   %}
 6371 
 6372   ins_pipe(pipe_serial);
 6373 %}
 6374 
 6375 instruct get_and_addI_no_resAcq(indirect mem, Universe dummy, iRegIorL2I incr)
 6376 %{
 6377   predicate(n->as_LoadStore()->result_not_used() && needs_acquiring_load_reserved(n));
 6378 
 6379   match(Set dummy (GetAndAddI mem incr));
 6380 
 6381   ins_cost(ALU_COST);
 6382 
 6383   format %{ "get_and_addI_acq [$mem], $incr\t#@get_and_addI_no_resAcq" %}
 6384 
 6385   ins_encode %{
 6386     __ atomic_addalw(noreg, $incr$$Register, as_Register($mem$$base));
 6387   %}
 6388 
 6389   ins_pipe(pipe_serial);
 6390 %}
 6391 
 6392 instruct get_and_addIiAcq(indirect mem, iRegINoSp newval, immIAdd incr)
 6393 %{
 6394   predicate(needs_acquiring_load_reserved(n));
 6395 
 6396   match(Set newval (GetAndAddI mem incr));
 6397 
 6398   ins_cost(ALU_COST);
 6399 
 6400   format %{ "get_and_addI_acq $newval, [$mem], $incr\t#@get_and_addIiAcq" %}
 6401 
 6402   ins_encode %{
 6403     __ atomic_addalw($newval$$Register, $incr$$constant, as_Register($mem$$base));
 6404   %}
 6405 
 6406   ins_pipe(pipe_serial);
 6407 %}
 6408 
 6409 instruct get_and_addIi_no_resAcq(indirect mem, Universe dummy, immIAdd incr)
 6410 %{
 6411   predicate(n->as_LoadStore()->result_not_used() && needs_acquiring_load_reserved(n));
 6412 
 6413   match(Set dummy (GetAndAddI mem incr));
 6414 
 6415   ins_cost(ALU_COST);
 6416 
 6417   format %{ "get_and_addI_acq [$mem], $incr\t#@get_and_addIi_no_resAcq" %}
 6418 
 6419   ins_encode %{
 6420     __ atomic_addalw(noreg, $incr$$constant, as_Register($mem$$base));
 6421   %}
 6422 
 6423   ins_pipe(pipe_serial);
 6424 %}
 6425 
 6426 // ============================================================================
 6427 // Arithmetic Instructions
 6428 //
 6429 
 6430 // Integer Addition
 6431 
 6432 // TODO
 6433 // these currently employ operations which do not set CR and hence are
 6434 // not flagged as killing CR but we would like to isolate the cases
 6435 // where we want to set flags from those where we don't. need to work
 6436 // out how to do that.
 6437 instruct addI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
 6438   match(Set dst (AddI src1 src2));
 6439 
 6440   ins_cost(ALU_COST);
 6441   format %{ "addw  $dst, $src1, $src2\t#@addI_reg_reg" %}
 6442 
 6443   ins_encode %{
 6444     __ addw(as_Register($dst$$reg),
 6445             as_Register($src1$$reg),
 6446             as_Register($src2$$reg));
 6447   %}
 6448 
 6449   ins_pipe(ialu_reg_reg);
 6450 %}
 6451 
 6452 instruct addI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immIAdd src2) %{
 6453   match(Set dst (AddI src1 src2));
 6454 
 6455   ins_cost(ALU_COST);
 6456   format %{ "addiw  $dst, $src1, $src2\t#@addI_reg_imm" %}
 6457 
 6458   ins_encode %{
 6459     int32_t con = (int32_t)$src2$$constant;
 6460     __ addiw(as_Register($dst$$reg),
 6461              as_Register($src1$$reg),
 6462              $src2$$constant);
 6463   %}
 6464 
 6465   ins_pipe(ialu_reg_imm);
 6466 %}
 6467 
 6468 instruct addI_reg_imm_l2i(iRegINoSp dst, iRegL src1, immIAdd src2) %{
 6469   match(Set dst (AddI (ConvL2I src1) src2));
 6470 
 6471   ins_cost(ALU_COST);
 6472   format %{ "addiw  $dst, $src1, $src2\t#@addI_reg_imm_l2i" %}
 6473 
 6474   ins_encode %{
 6475     __ addiw(as_Register($dst$$reg),
 6476              as_Register($src1$$reg),
 6477              $src2$$constant);
 6478   %}
 6479 
 6480   ins_pipe(ialu_reg_imm);
 6481 %}
 6482 
 6483 // Pointer Addition
 6484 instruct addP_reg_reg(iRegPNoSp dst, iRegP src1, iRegL src2) %{
 6485   match(Set dst (AddP src1 src2));
 6486 
 6487   ins_cost(ALU_COST);
 6488   format %{ "add $dst, $src1, $src2\t# ptr, #@addP_reg_reg" %}
 6489 
 6490   ins_encode %{
 6491     __ add(as_Register($dst$$reg),
 6492            as_Register($src1$$reg),
 6493            as_Register($src2$$reg));
 6494   %}
 6495 
 6496   ins_pipe(ialu_reg_reg);
 6497 %}
 6498 
 6499 // If we shift more than 32 bits, we need not convert I2L.
 6500 instruct lShiftL_regI_immGE32(iRegLNoSp dst, iRegI src, uimmI6_ge32 scale) %{
 6501   match(Set dst (LShiftL (ConvI2L src) scale));
 6502   ins_cost(ALU_COST);
 6503   format %{ "slli  $dst, $src, $scale & 63\t#@lShiftL_regI_immGE32" %}
 6504 
 6505   ins_encode %{
 6506     __ slli(as_Register($dst$$reg), as_Register($src$$reg), $scale$$constant & 63);
 6507   %}
 6508 
 6509   ins_pipe(ialu_reg_shift);
 6510 %}
 6511 
 6512 // Pointer Immediate Addition
 6513 // n.b. this needs to be more expensive than using an indirect memory
 6514 // operand
 6515 instruct addP_reg_imm(iRegPNoSp dst, iRegP src1, immLAdd src2) %{
 6516   match(Set dst (AddP src1 src2));
 6517   ins_cost(ALU_COST);
 6518   format %{ "addi  $dst, $src1, $src2\t# ptr, #@addP_reg_imm" %}
 6519 
 6520   ins_encode %{
 6521     // src2 is imm, so actually call the addi
 6522     __ add(as_Register($dst$$reg),
 6523            as_Register($src1$$reg),
 6524            $src2$$constant);
 6525   %}
 6526 
 6527   ins_pipe(ialu_reg_imm);
 6528 %}
 6529 
 6530 // Long Addition
 6531 instruct addL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
 6532   match(Set dst (AddL src1 src2));
 6533   ins_cost(ALU_COST);
 6534   format %{ "add  $dst, $src1, $src2\t#@addL_reg_reg" %}
 6535 
 6536   ins_encode %{
 6537     __ add(as_Register($dst$$reg),
 6538            as_Register($src1$$reg),
 6539            as_Register($src2$$reg));
 6540   %}
 6541 
 6542   ins_pipe(ialu_reg_reg);
 6543 %}
 6544 
 6545 // No constant pool entries requiredLong Immediate Addition.
 6546 instruct addL_reg_imm(iRegLNoSp dst, iRegL src1, immLAdd src2) %{
 6547   match(Set dst (AddL src1 src2));
 6548   ins_cost(ALU_COST);
 6549   format %{ "addi  $dst, $src1, $src2\t#@addL_reg_imm" %}
 6550 
 6551   ins_encode %{
 6552     // src2 is imm, so actually call the addi
 6553     __ add(as_Register($dst$$reg),
 6554            as_Register($src1$$reg),
 6555            $src2$$constant);
 6556   %}
 6557 
 6558   ins_pipe(ialu_reg_imm);
 6559 %}
 6560 
 6561 // Integer Subtraction
 6562 instruct subI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
 6563   match(Set dst (SubI src1 src2));
 6564 
 6565   ins_cost(ALU_COST);
 6566   format %{ "subw  $dst, $src1, $src2\t#@subI_reg_reg" %}
 6567 
 6568   ins_encode %{
 6569     __ subw(as_Register($dst$$reg),
 6570             as_Register($src1$$reg),
 6571             as_Register($src2$$reg));
 6572   %}
 6573 
 6574   ins_pipe(ialu_reg_reg);
 6575 %}
 6576 
 6577 // Immediate Subtraction
 6578 instruct subI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immISub src2) %{
 6579   match(Set dst (SubI src1 src2));
 6580 
 6581   ins_cost(ALU_COST);
 6582   format %{ "addiw  $dst, $src1, -$src2\t#@subI_reg_imm" %}
 6583 
 6584   ins_encode %{
 6585     // src2 is imm, so actually call the addiw
 6586     __ subw(as_Register($dst$$reg),
 6587             as_Register($src1$$reg),
 6588             $src2$$constant);
 6589   %}
 6590 
 6591   ins_pipe(ialu_reg_imm);
 6592 %}
 6593 
 6594 // Long Subtraction
 6595 instruct subL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
 6596   match(Set dst (SubL src1 src2));
 6597   ins_cost(ALU_COST);
 6598   format %{ "sub  $dst, $src1, $src2\t#@subL_reg_reg" %}
 6599 
 6600   ins_encode %{
 6601     __ sub(as_Register($dst$$reg),
 6602            as_Register($src1$$reg),
 6603            as_Register($src2$$reg));
 6604   %}
 6605 
 6606   ins_pipe(ialu_reg_reg);
 6607 %}
 6608 
 6609 // No constant pool entries requiredLong Immediate Subtraction.
 6610 instruct subL_reg_imm(iRegLNoSp dst, iRegL src1, immLSub src2) %{
 6611   match(Set dst (SubL src1 src2));
 6612   ins_cost(ALU_COST);
 6613   format %{ "addi  $dst, $src1, -$src2\t#@subL_reg_imm" %}
 6614 
 6615   ins_encode %{
 6616     // src2 is imm, so actually call the addi
 6617     __ sub(as_Register($dst$$reg),
 6618            as_Register($src1$$reg),
 6619            $src2$$constant);
 6620   %}
 6621 
 6622   ins_pipe(ialu_reg_imm);
 6623 %}
 6624 
 6625 // Integer Negation (special case for sub)
 6626 
 6627 instruct negI_reg(iRegINoSp dst, iRegIorL2I src, immI0 zero) %{
 6628   match(Set dst (SubI zero src));
 6629   ins_cost(ALU_COST);
 6630   format %{ "subw  $dst, x0, $src\t# int, #@negI_reg" %}
 6631 
 6632   ins_encode %{
 6633     // actually call the subw
 6634     __ negw(as_Register($dst$$reg),
 6635             as_Register($src$$reg));
 6636   %}
 6637 
 6638   ins_pipe(ialu_reg);
 6639 %}
 6640 
 6641 // Long Negation
 6642 
 6643 instruct negL_reg(iRegLNoSp dst, iRegL src, immL0 zero) %{
 6644   match(Set dst (SubL zero src));
 6645   ins_cost(ALU_COST);
 6646   format %{ "sub  $dst, x0, $src\t# long, #@negL_reg" %}
 6647 
 6648   ins_encode %{
 6649     // actually call the sub
 6650     __ neg(as_Register($dst$$reg),
 6651            as_Register($src$$reg));
 6652   %}
 6653 
 6654   ins_pipe(ialu_reg);
 6655 %}
 6656 
 6657 // Integer Multiply
 6658 
 6659 instruct mulI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
 6660   match(Set dst (MulI src1 src2));
 6661   ins_cost(IMUL_COST);
 6662   format %{ "mulw  $dst, $src1, $src2\t#@mulI" %}
 6663 
 6664   //this means 2 word multi, and no sign extend to 64 bits
 6665   ins_encode %{
 6666     // riscv64 mulw will sign-extension to high 32 bits in dst reg
 6667     __ mulw(as_Register($dst$$reg),
 6668             as_Register($src1$$reg),
 6669             as_Register($src2$$reg));
 6670   %}
 6671 
 6672   ins_pipe(imul_reg_reg);
 6673 %}
 6674 
 6675 // Long Multiply
 6676 
 6677 instruct mulL(iRegLNoSp dst, iRegL src1, iRegL src2) %{
 6678   match(Set dst (MulL src1 src2));
 6679   ins_cost(IMUL_COST);
 6680   format %{ "mul  $dst, $src1, $src2\t#@mulL" %}
 6681 
 6682   ins_encode %{
 6683     __ mul(as_Register($dst$$reg),
 6684            as_Register($src1$$reg),
 6685            as_Register($src2$$reg));
 6686   %}
 6687 
 6688   ins_pipe(lmul_reg_reg);
 6689 %}
 6690 
 6691 instruct mulHiL_rReg(iRegLNoSp dst, iRegL src1, iRegL src2)
 6692 %{
 6693   match(Set dst (MulHiL src1 src2));
 6694   ins_cost(IMUL_COST);
 6695   format %{ "mulh  $dst, $src1, $src2\t# mulhi, #@mulHiL_rReg" %}
 6696 
 6697   ins_encode %{
 6698     __ mulh(as_Register($dst$$reg),
 6699             as_Register($src1$$reg),
 6700             as_Register($src2$$reg));
 6701   %}
 6702 
 6703   ins_pipe(lmul_reg_reg);
 6704 %}
 6705 
 6706 // Integer Divide
 6707 
 6708 instruct divI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
 6709   match(Set dst (DivI src1 src2));
 6710   ins_cost(IDIVSI_COST);
 6711   format %{ "divw  $dst, $src1, $src2\t#@divI"%}
 6712 
 6713   ins_encode(riscv_enc_divw(dst, src1, src2));
 6714   ins_pipe(idiv_reg_reg);
 6715 %}
 6716 
 6717 instruct signExtract(iRegINoSp dst, iRegIorL2I src1, immI_31 div1, immI_31 div2) %{
 6718   match(Set dst (URShiftI (RShiftI src1 div1) div2));
 6719   ins_cost(ALU_COST);
 6720   format %{ "srliw $dst, $src1, $div1\t# int signExtract, #@signExtract" %}
 6721 
 6722   ins_encode %{
 6723     __ srliw(as_Register($dst$$reg), as_Register($src1$$reg), 31);
 6724   %}
 6725   ins_pipe(ialu_reg_shift);
 6726 %}
 6727 
 6728 // Long Divide
 6729 
 6730 instruct divL(iRegLNoSp dst, iRegL src1, iRegL src2) %{
 6731   match(Set dst (DivL src1 src2));
 6732   ins_cost(IDIVDI_COST);
 6733   format %{ "div  $dst, $src1, $src2\t#@divL" %}
 6734 
 6735   ins_encode(riscv_enc_div(dst, src1, src2));
 6736   ins_pipe(ldiv_reg_reg);
 6737 %}
 6738 
 6739 instruct signExtractL(iRegLNoSp dst, iRegL src1, immI_63 div1, immI_63 div2) %{
 6740   match(Set dst (URShiftL (RShiftL src1 div1) div2));
 6741   ins_cost(ALU_COST);
 6742   format %{ "srli $dst, $src1, $div1\t# long signExtract, #@signExtractL" %}
 6743 
 6744   ins_encode %{
 6745     __ srli(as_Register($dst$$reg), as_Register($src1$$reg), 63);
 6746   %}
 6747   ins_pipe(ialu_reg_shift);
 6748 %}
 6749 
 6750 // Integer Remainder
 6751 
 6752 instruct modI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
 6753   match(Set dst (ModI src1 src2));
 6754   ins_cost(IDIVSI_COST);
 6755   format %{ "remw  $dst, $src1, $src2\t#@modI" %}
 6756 
 6757   ins_encode(riscv_enc_modw(dst, src1, src2));
 6758   ins_pipe(ialu_reg_reg);
 6759 %}
 6760 
 6761 // Long Remainder
 6762 
 6763 instruct modL(iRegLNoSp dst, iRegL src1, iRegL src2) %{
 6764   match(Set dst (ModL src1 src2));
 6765   ins_cost(IDIVDI_COST);
 6766   format %{ "rem  $dst, $src1, $src2\t#@modL" %}
 6767 
 6768   ins_encode(riscv_enc_mod(dst, src1, src2));
 6769   ins_pipe(ialu_reg_reg);
 6770 %}
 6771 
 6772 // Integer Shifts
 6773 
 6774 // Shift Left Register
 6775 // In RV64I, only the low 5 bits of src2 are considered for the shift amount
 6776 instruct lShiftI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
 6777   match(Set dst (LShiftI src1 src2));
 6778   ins_cost(ALU_COST);
 6779   format %{ "sllw  $dst, $src1, $src2\t#@lShiftI_reg_reg" %}
 6780 
 6781   ins_encode %{
 6782     __ sllw(as_Register($dst$$reg),
 6783             as_Register($src1$$reg),
 6784             as_Register($src2$$reg));
 6785   %}
 6786 
 6787   ins_pipe(ialu_reg_reg_vshift);
 6788 %}
 6789 
 6790 // Shift Left Immediate
 6791 instruct lShiftI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immI src2) %{
 6792   match(Set dst (LShiftI src1 src2));
 6793   ins_cost(ALU_COST);
 6794   format %{ "slliw  $dst, $src1, ($src2 & 0x1f)\t#@lShiftI_reg_imm" %}
 6795 
 6796   ins_encode %{
 6797     // the shift amount is encoded in the lower
 6798     // 5 bits of the I-immediate field for RV32I
 6799     __ slliw(as_Register($dst$$reg),
 6800              as_Register($src1$$reg),
 6801              (unsigned) $src2$$constant & 0x1f);
 6802   %}
 6803 
 6804   ins_pipe(ialu_reg_shift);
 6805 %}
 6806 
 6807 // Shift Right Logical Register
 6808 // In RV64I, only the low 5 bits of src2 are considered for the shift amount
 6809 instruct urShiftI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
 6810   match(Set dst (URShiftI src1 src2));
 6811   ins_cost(ALU_COST);
 6812   format %{ "srlw  $dst, $src1, $src2\t#@urShiftI_reg_reg" %}
 6813 
 6814   ins_encode %{
 6815     __ srlw(as_Register($dst$$reg),
 6816             as_Register($src1$$reg),
 6817             as_Register($src2$$reg));
 6818   %}
 6819 
 6820   ins_pipe(ialu_reg_reg_vshift);
 6821 %}
 6822 
 6823 // Shift Right Logical Immediate
 6824 instruct urShiftI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immI src2) %{
 6825   match(Set dst (URShiftI src1 src2));
 6826   ins_cost(ALU_COST);
 6827   format %{ "srliw  $dst, $src1, ($src2 & 0x1f)\t#@urShiftI_reg_imm" %}
 6828 
 6829   ins_encode %{
 6830     // the shift amount is encoded in the lower
 6831     // 6 bits of the I-immediate field for RV64I
 6832     __ srliw(as_Register($dst$$reg),
 6833              as_Register($src1$$reg),
 6834              (unsigned) $src2$$constant & 0x1f);
 6835   %}
 6836 
 6837   ins_pipe(ialu_reg_shift);
 6838 %}
 6839 
 6840 // Shift Right Arithmetic Register
 6841 // In RV64I, only the low 5 bits of src2 are considered for the shift amount
 6842 instruct rShiftI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
 6843   match(Set dst (RShiftI src1 src2));
 6844   ins_cost(ALU_COST);
 6845   format %{ "sraw  $dst, $src1, $src2\t#@rShiftI_reg_reg" %}
 6846 
 6847   ins_encode %{
 6848     // riscv will sign-ext dst high 32 bits
 6849     __ sraw(as_Register($dst$$reg),
 6850             as_Register($src1$$reg),
 6851             as_Register($src2$$reg));
 6852   %}
 6853 
 6854   ins_pipe(ialu_reg_reg_vshift);
 6855 %}
 6856 
 6857 // Shift Right Arithmetic Immediate
 6858 instruct rShiftI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immI src2) %{
 6859   match(Set dst (RShiftI src1 src2));
 6860   ins_cost(ALU_COST);
 6861   format %{ "sraiw  $dst, $src1, ($src2 & 0x1f)\t#@rShiftI_reg_imm" %}
 6862 
 6863   ins_encode %{
 6864     // riscv will sign-ext dst high 32 bits
 6865     __ sraiw(as_Register($dst$$reg),
 6866              as_Register($src1$$reg),
 6867              (unsigned) $src2$$constant & 0x1f);
 6868   %}
 6869 
 6870   ins_pipe(ialu_reg_shift);
 6871 %}
 6872 
 6873 // Long Shifts
 6874 
 6875 // Shift Left Register
 6876 // In RV64I, only the low 6 bits of src2 are considered for the shift amount
 6877 instruct lShiftL_reg_reg(iRegLNoSp dst, iRegL src1, iRegIorL2I src2) %{
 6878   match(Set dst (LShiftL src1 src2));
 6879 
 6880   ins_cost(ALU_COST);
 6881   format %{ "sll  $dst, $src1, $src2\t#@lShiftL_reg_reg" %}
 6882 
 6883   ins_encode %{
 6884     __ sll(as_Register($dst$$reg),
 6885            as_Register($src1$$reg),
 6886            as_Register($src2$$reg));
 6887   %}
 6888 
 6889   ins_pipe(ialu_reg_reg_vshift);
 6890 %}
 6891 
 6892 // Shift Left Immediate
 6893 instruct lShiftL_reg_imm(iRegLNoSp dst, iRegL src1, immI src2) %{
 6894   match(Set dst (LShiftL src1 src2));
 6895 
 6896   ins_cost(ALU_COST);
 6897   format %{ "slli  $dst, $src1, ($src2 & 0x3f)\t#@lShiftL_reg_imm" %}
 6898 
 6899   ins_encode %{
 6900     // the shift amount is encoded in the lower
 6901     // 6 bits of the I-immediate field for RV64I
 6902     __ slli(as_Register($dst$$reg),
 6903             as_Register($src1$$reg),
 6904             (unsigned) $src2$$constant & 0x3f);
 6905   %}
 6906 
 6907   ins_pipe(ialu_reg_shift);
 6908 %}
 6909 
 6910 // Shift Right Logical Register
 6911 // In RV64I, only the low 6 bits of src2 are considered for the shift amount
 6912 instruct urShiftL_reg_reg(iRegLNoSp dst, iRegL src1, iRegIorL2I src2) %{
 6913   match(Set dst (URShiftL src1 src2));
 6914 
 6915   ins_cost(ALU_COST);
 6916   format %{ "srl  $dst, $src1, $src2\t#@urShiftL_reg_reg" %}
 6917 
 6918   ins_encode %{
 6919     __ srl(as_Register($dst$$reg),
 6920             as_Register($src1$$reg),
 6921             as_Register($src2$$reg));
 6922   %}
 6923 
 6924   ins_pipe(ialu_reg_reg_vshift);
 6925 %}
 6926 
 6927 // Shift Right Logical Immediate
 6928 instruct urShiftL_reg_imm(iRegLNoSp dst, iRegL src1, immI src2) %{
 6929   match(Set dst (URShiftL src1 src2));
 6930 
 6931   ins_cost(ALU_COST);
 6932   format %{ "srli  $dst, $src1, ($src2 & 0x3f)\t#@urShiftL_reg_imm" %}
 6933 
 6934   ins_encode %{
 6935     // the shift amount is encoded in the lower
 6936     // 6 bits of the I-immediate field for RV64I
 6937     __ srli(as_Register($dst$$reg),
 6938             as_Register($src1$$reg),
 6939             (unsigned) $src2$$constant & 0x3f);
 6940   %}
 6941 
 6942   ins_pipe(ialu_reg_shift);
 6943 %}
 6944 
 6945 // A special-case pattern for card table stores.
 6946 instruct urShiftP_reg_imm(iRegLNoSp dst, iRegP src1, immI src2) %{
 6947   match(Set dst (URShiftL (CastP2X src1) src2));
 6948 
 6949   ins_cost(ALU_COST);
 6950   format %{ "srli  $dst, p2x($src1), ($src2 & 0x3f)\t#@urShiftP_reg_imm" %}
 6951 
 6952   ins_encode %{
 6953     // the shift amount is encoded in the lower
 6954     // 6 bits of the I-immediate field for RV64I
 6955     __ srli(as_Register($dst$$reg),
 6956             as_Register($src1$$reg),
 6957             (unsigned) $src2$$constant & 0x3f);
 6958   %}
 6959 
 6960   ins_pipe(ialu_reg_shift);
 6961 %}
 6962 
 6963 // Shift Right Arithmetic Register
 6964 // In RV64I, only the low 6 bits of src2 are considered for the shift amount
 6965 instruct rShiftL_reg_reg(iRegLNoSp dst, iRegL src1, iRegIorL2I src2) %{
 6966   match(Set dst (RShiftL src1 src2));
 6967 
 6968   ins_cost(ALU_COST);
 6969   format %{ "sra  $dst, $src1, $src2\t#@rShiftL_reg_reg" %}
 6970 
 6971   ins_encode %{
 6972     __ sra(as_Register($dst$$reg),
 6973            as_Register($src1$$reg),
 6974            as_Register($src2$$reg));
 6975   %}
 6976 
 6977   ins_pipe(ialu_reg_reg_vshift);
 6978 %}
 6979 
 6980 // Shift Right Arithmetic Immediate
 6981 instruct rShiftL_reg_imm(iRegLNoSp dst, iRegL src1, immI src2) %{
 6982   match(Set dst (RShiftL src1 src2));
 6983 
 6984   ins_cost(ALU_COST);
 6985   format %{ "srai  $dst, $src1, ($src2 & 0x3f)\t#@rShiftL_reg_imm" %}
 6986 
 6987   ins_encode %{
 6988     // the shift amount is encoded in the lower
 6989     // 6 bits of the I-immediate field for RV64I
 6990     __ srai(as_Register($dst$$reg),
 6991             as_Register($src1$$reg),
 6992             (unsigned) $src2$$constant & 0x3f);
 6993   %}
 6994 
 6995   ins_pipe(ialu_reg_shift);
 6996 %}
 6997 
 6998 instruct regI_not_reg(iRegINoSp dst, iRegI src1, immI_M1 m1) %{
 6999   match(Set dst (XorI src1 m1));
 7000   ins_cost(ALU_COST);
 7001   format %{ "xori  $dst, $src1, -1\t#@regI_not_reg" %}
 7002 
 7003   ins_encode %{
 7004     __ xori(as_Register($dst$$reg), as_Register($src1$$reg), -1);
 7005   %}
 7006 
 7007   ins_pipe(ialu_reg_imm);
 7008 %}
 7009 
 7010 instruct regL_not_reg(iRegLNoSp dst, iRegL src1, immL_M1 m1) %{
 7011   match(Set dst (XorL src1 m1));
 7012   ins_cost(ALU_COST);
 7013   format %{ "xori  $dst, $src1, -1\t#@regL_not_reg" %}
 7014 
 7015   ins_encode %{
 7016     __ xori(as_Register($dst$$reg), as_Register($src1$$reg), -1);
 7017   %}
 7018 
 7019   ins_pipe(ialu_reg_imm);
 7020 %}
 7021 
 7022 
 7023 // ============================================================================
 7024 // Floating Point Arithmetic Instructions
 7025 
 7026 instruct addF_reg_reg(fRegF dst, fRegF src1, fRegF src2) %{
 7027   match(Set dst (AddF src1 src2));
 7028 
 7029   ins_cost(DEFAULT_COST * 5);
 7030   format %{ "fadd.s  $dst, $src1, $src2\t#@addF_reg_reg" %}
 7031 
 7032   ins_encode %{
 7033     __ fadd_s(as_FloatRegister($dst$$reg),
 7034               as_FloatRegister($src1$$reg),
 7035               as_FloatRegister($src2$$reg));
 7036   %}
 7037 
 7038   ins_pipe(fp_dop_reg_reg_s);
 7039 %}
 7040 
 7041 instruct addD_reg_reg(fRegD dst, fRegD src1, fRegD src2) %{
 7042   match(Set dst (AddD src1 src2));
 7043 
 7044   ins_cost(DEFAULT_COST * 5);
 7045   format %{ "fadd.d  $dst, $src1, $src2\t#@addD_reg_reg" %}
 7046 
 7047   ins_encode %{
 7048     __ fadd_d(as_FloatRegister($dst$$reg),
 7049               as_FloatRegister($src1$$reg),
 7050               as_FloatRegister($src2$$reg));
 7051   %}
 7052 
 7053   ins_pipe(fp_dop_reg_reg_d);
 7054 %}
 7055 
 7056 instruct subF_reg_reg(fRegF dst, fRegF src1, fRegF src2) %{
 7057   match(Set dst (SubF src1 src2));
 7058 
 7059   ins_cost(DEFAULT_COST * 5);
 7060   format %{ "fsub.s  $dst, $src1, $src2\t#@subF_reg_reg" %}
 7061 
 7062   ins_encode %{
 7063     __ fsub_s(as_FloatRegister($dst$$reg),
 7064               as_FloatRegister($src1$$reg),
 7065               as_FloatRegister($src2$$reg));
 7066   %}
 7067 
 7068   ins_pipe(fp_dop_reg_reg_s);
 7069 %}
 7070 
 7071 instruct subD_reg_reg(fRegD dst, fRegD src1, fRegD src2) %{
 7072   match(Set dst (SubD src1 src2));
 7073 
 7074   ins_cost(DEFAULT_COST * 5);
 7075   format %{ "fsub.d  $dst, $src1, $src2\t#@subD_reg_reg" %}
 7076 
 7077   ins_encode %{
 7078     __ fsub_d(as_FloatRegister($dst$$reg),
 7079               as_FloatRegister($src1$$reg),
 7080               as_FloatRegister($src2$$reg));
 7081   %}
 7082 
 7083   ins_pipe(fp_dop_reg_reg_d);
 7084 %}
 7085 
 7086 instruct mulF_reg_reg(fRegF dst, fRegF src1, fRegF src2) %{
 7087   match(Set dst (MulF src1 src2));
 7088 
 7089   ins_cost(FMUL_SINGLE_COST);
 7090   format %{ "fmul.s  $dst, $src1, $src2\t#@mulF_reg_reg" %}
 7091 
 7092   ins_encode %{
 7093     __ fmul_s(as_FloatRegister($dst$$reg),
 7094               as_FloatRegister($src1$$reg),
 7095               as_FloatRegister($src2$$reg));
 7096   %}
 7097 
 7098   ins_pipe(fp_dop_reg_reg_s);
 7099 %}
 7100 
 7101 instruct mulD_reg_reg(fRegD dst, fRegD src1, fRegD src2) %{
 7102   match(Set dst (MulD src1 src2));
 7103 
 7104   ins_cost(FMUL_DOUBLE_COST);
 7105   format %{ "fmul.d  $dst, $src1, $src2\t#@mulD_reg_reg" %}
 7106 
 7107   ins_encode %{
 7108     __ fmul_d(as_FloatRegister($dst$$reg),
 7109               as_FloatRegister($src1$$reg),
 7110               as_FloatRegister($src2$$reg));
 7111   %}
 7112 
 7113   ins_pipe(fp_dop_reg_reg_d);
 7114 %}
 7115 
 7116 // src1 * src2 + src3
 7117 instruct maddF_reg_reg(fRegF dst, fRegF src1, fRegF src2, fRegF src3) %{
 7118   predicate(UseFMA);
 7119   match(Set dst (FmaF src3 (Binary src1 src2)));
 7120 
 7121   ins_cost(FMUL_SINGLE_COST);
 7122   format %{ "fmadd.s  $dst, $src1, $src2, $src3\t#@maddF_reg_reg" %}
 7123 
 7124   ins_encode %{
 7125     __ fmadd_s(as_FloatRegister($dst$$reg),
 7126                as_FloatRegister($src1$$reg),
 7127                as_FloatRegister($src2$$reg),
 7128                as_FloatRegister($src3$$reg));
 7129   %}
 7130 
 7131   ins_pipe(pipe_class_default);
 7132 %}
 7133 
 7134 // src1 * src2 + src3
 7135 instruct maddD_reg_reg(fRegD dst, fRegD src1, fRegD src2, fRegD src3) %{
 7136   predicate(UseFMA);
 7137   match(Set dst (FmaD src3 (Binary src1 src2)));
 7138 
 7139   ins_cost(FMUL_DOUBLE_COST);
 7140   format %{ "fmadd.d  $dst, $src1, $src2, $src3\t#@maddD_reg_reg" %}
 7141 
 7142   ins_encode %{
 7143     __ fmadd_d(as_FloatRegister($dst$$reg),
 7144                as_FloatRegister($src1$$reg),
 7145                as_FloatRegister($src2$$reg),
 7146                as_FloatRegister($src3$$reg));
 7147   %}
 7148 
 7149   ins_pipe(pipe_class_default);
 7150 %}
 7151 
 7152 // src1 * src2 - src3
 7153 instruct msubF_reg_reg(fRegF dst, fRegF src1, fRegF src2, fRegF src3) %{
 7154   predicate(UseFMA);
 7155   match(Set dst (FmaF (NegF src3) (Binary src1 src2)));
 7156 
 7157   ins_cost(FMUL_SINGLE_COST);
 7158   format %{ "fmsub.s  $dst, $src1, $src2, $src3\t#@msubF_reg_reg" %}
 7159 
 7160   ins_encode %{
 7161     __ fmsub_s(as_FloatRegister($dst$$reg),
 7162                as_FloatRegister($src1$$reg),
 7163                as_FloatRegister($src2$$reg),
 7164                as_FloatRegister($src3$$reg));
 7165   %}
 7166 
 7167   ins_pipe(pipe_class_default);
 7168 %}
 7169 
 7170 // src1 * src2 - src3
 7171 instruct msubD_reg_reg(fRegD dst, fRegD src1, fRegD src2, fRegD src3) %{
 7172   predicate(UseFMA);
 7173   match(Set dst (FmaD (NegD src3) (Binary src1 src2)));
 7174 
 7175   ins_cost(FMUL_DOUBLE_COST);
 7176   format %{ "fmsub.d  $dst, $src1, $src2, $src3\t#@msubD_reg_reg" %}
 7177 
 7178   ins_encode %{
 7179     __ fmsub_d(as_FloatRegister($dst$$reg),
 7180                as_FloatRegister($src1$$reg),
 7181                as_FloatRegister($src2$$reg),
 7182                as_FloatRegister($src3$$reg));
 7183   %}
 7184 
 7185   ins_pipe(pipe_class_default);
 7186 %}
 7187 
 7188 // -src1 * src2 + src3
 7189 instruct nmsubF_reg_reg(fRegF dst, fRegF src1, fRegF src2, fRegF src3) %{
 7190   predicate(UseFMA);
 7191   match(Set dst (FmaF src3 (Binary (NegF src1) src2)));
 7192   match(Set dst (FmaF src3 (Binary src1 (NegF src2))));
 7193 
 7194   ins_cost(FMUL_SINGLE_COST);
 7195   format %{ "fnmsub.s  $dst, $src1, $src2, $src3\t#@nmsubF_reg_reg" %}
 7196 
 7197   ins_encode %{
 7198     __ fnmsub_s(as_FloatRegister($dst$$reg),
 7199                 as_FloatRegister($src1$$reg),
 7200                 as_FloatRegister($src2$$reg),
 7201                 as_FloatRegister($src3$$reg));
 7202   %}
 7203 
 7204   ins_pipe(pipe_class_default);
 7205 %}
 7206 
 7207 // -src1 * src2 + src3
 7208 instruct nmsubD_reg_reg(fRegD dst, fRegD src1, fRegD src2, fRegD src3) %{
 7209   predicate(UseFMA);
 7210   match(Set dst (FmaD src3 (Binary (NegD src1) src2)));
 7211   match(Set dst (FmaD src3 (Binary src1 (NegD src2))));
 7212 
 7213   ins_cost(FMUL_DOUBLE_COST);
 7214   format %{ "fnmsub.d  $dst, $src1, $src2, $src3\t#@nmsubD_reg_reg" %}
 7215 
 7216   ins_encode %{
 7217     __ fnmsub_d(as_FloatRegister($dst$$reg),
 7218                 as_FloatRegister($src1$$reg),
 7219                 as_FloatRegister($src2$$reg),
 7220                 as_FloatRegister($src3$$reg));
 7221   %}
 7222 
 7223   ins_pipe(pipe_class_default);
 7224 %}
 7225 
 7226 // -src1 * src2 - src3
 7227 instruct nmaddF_reg_reg(fRegF dst, fRegF src1, fRegF src2, fRegF src3) %{
 7228   predicate(UseFMA);
 7229   match(Set dst (FmaF (NegF src3) (Binary (NegF src1) src2)));
 7230   match(Set dst (FmaF (NegF src3) (Binary src1 (NegF src2))));
 7231 
 7232   ins_cost(FMUL_SINGLE_COST);
 7233   format %{ "fnmadd.s  $dst, $src1, $src2, $src3\t#@nmaddF_reg_reg" %}
 7234 
 7235   ins_encode %{
 7236     __ fnmadd_s(as_FloatRegister($dst$$reg),
 7237                 as_FloatRegister($src1$$reg),
 7238                 as_FloatRegister($src2$$reg),
 7239                 as_FloatRegister($src3$$reg));
 7240   %}
 7241 
 7242   ins_pipe(pipe_class_default);
 7243 %}
 7244 
 7245 // -src1 * src2 - src3
 7246 instruct nmaddD_reg_reg(fRegD dst, fRegD src1, fRegD src2, fRegD src3) %{
 7247   predicate(UseFMA);
 7248   match(Set dst (FmaD (NegD src3) (Binary (NegD src1) src2)));
 7249   match(Set dst (FmaD (NegD src3) (Binary src1 (NegD src2))));
 7250 
 7251   ins_cost(FMUL_DOUBLE_COST);
 7252   format %{ "fnmadd.d  $dst, $src1, $src2, $src3\t#@nmaddD_reg_reg" %}
 7253 
 7254   ins_encode %{
 7255     __ fnmadd_d(as_FloatRegister($dst$$reg),
 7256                 as_FloatRegister($src1$$reg),
 7257                 as_FloatRegister($src2$$reg),
 7258                 as_FloatRegister($src3$$reg));
 7259   %}
 7260 
 7261   ins_pipe(pipe_class_default);
 7262 %}
 7263 
 7264 // Math.max(FF)F
 7265 instruct maxF_reg_reg(fRegF dst, fRegF src1, fRegF src2, rFlagsReg cr) %{
 7266   match(Set dst (MaxF src1 src2));
 7267   effect(TEMP_DEF dst, KILL cr);
 7268 
 7269   format %{ "maxF $dst, $src1, $src2" %}
 7270 
 7271   ins_encode %{
 7272     __ minmax_FD(as_FloatRegister($dst$$reg),
 7273                  as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg),
 7274                  false /* is_double */, false /* is_min */);
 7275   %}
 7276 
 7277   ins_pipe(pipe_class_default);
 7278 %}
 7279 
 7280 // Math.min(FF)F
 7281 instruct minF_reg_reg(fRegF dst, fRegF src1, fRegF src2, rFlagsReg cr) %{
 7282   match(Set dst (MinF src1 src2));
 7283   effect(TEMP_DEF dst, KILL cr);
 7284 
 7285   format %{ "minF $dst, $src1, $src2" %}
 7286 
 7287   ins_encode %{
 7288     __ minmax_FD(as_FloatRegister($dst$$reg),
 7289                  as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg),
 7290                  false /* is_double */, true /* is_min */);
 7291   %}
 7292 
 7293   ins_pipe(pipe_class_default);
 7294 %}
 7295 
 7296 // Math.max(DD)D
 7297 instruct maxD_reg_reg(fRegD dst, fRegD src1, fRegD src2, rFlagsReg cr) %{
 7298   match(Set dst (MaxD src1 src2));
 7299   effect(TEMP_DEF dst, KILL cr);
 7300 
 7301   format %{ "maxD $dst, $src1, $src2" %}
 7302 
 7303   ins_encode %{
 7304     __ minmax_FD(as_FloatRegister($dst$$reg),
 7305                  as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg),
 7306                  true /* is_double */, false /* is_min */);
 7307   %}
 7308 
 7309   ins_pipe(pipe_class_default);
 7310 %}
 7311 
 7312 // Math.min(DD)D
 7313 instruct minD_reg_reg(fRegD dst, fRegD src1, fRegD src2, rFlagsReg cr) %{
 7314   match(Set dst (MinD src1 src2));
 7315   effect(TEMP_DEF dst, KILL cr);
 7316 
 7317   format %{ "minD $dst, $src1, $src2" %}
 7318 
 7319   ins_encode %{
 7320     __ minmax_FD(as_FloatRegister($dst$$reg),
 7321                  as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg),
 7322                  true /* is_double */, true /* is_min */);
 7323   %}
 7324 
 7325   ins_pipe(pipe_class_default);
 7326 %}
 7327 
 7328 // Float.isInfinite
 7329 instruct isInfiniteF_reg_reg(iRegINoSp dst, fRegF src)
 7330 %{
 7331   match(Set dst (IsInfiniteF src));
 7332 
 7333   format %{ "isInfinite $dst, $src" %}
 7334   ins_encode %{
 7335     __ fclass_s(as_Register($dst$$reg), as_FloatRegister($src$$reg));
 7336     __ andi(as_Register($dst$$reg), as_Register($dst$$reg), 0b0010000001);
 7337     __ slt(as_Register($dst$$reg), zr, as_Register($dst$$reg));
 7338   %}
 7339 
 7340   ins_pipe(pipe_class_default);
 7341 %}
 7342 
 7343 // Double.isInfinite
 7344 instruct isInfiniteD_reg_reg(iRegINoSp dst, fRegD src)
 7345 %{
 7346   match(Set dst (IsInfiniteD src));
 7347 
 7348   format %{ "isInfinite $dst, $src" %}
 7349   ins_encode %{
 7350     __ fclass_d(as_Register($dst$$reg), as_FloatRegister($src$$reg));
 7351     __ andi(as_Register($dst$$reg), as_Register($dst$$reg), 0b0010000001);
 7352     __ slt(as_Register($dst$$reg), zr, as_Register($dst$$reg));
 7353   %}
 7354 
 7355   ins_pipe(pipe_class_default);
 7356 %}
 7357 
 7358 // Float.isFinite
 7359 instruct isFiniteF_reg_reg(iRegINoSp dst, fRegF src)
 7360 %{
 7361   match(Set dst (IsFiniteF src));
 7362 
 7363   format %{ "isFinite $dst, $src" %}
 7364   ins_encode %{
 7365     __ fclass_s(as_Register($dst$$reg), as_FloatRegister($src$$reg));
 7366     __ andi(as_Register($dst$$reg), as_Register($dst$$reg), 0b0001111110);
 7367     __ slt(as_Register($dst$$reg), zr, as_Register($dst$$reg));
 7368   %}
 7369 
 7370   ins_pipe(pipe_class_default);
 7371 %}
 7372 
 7373 // Double.isFinite
 7374 instruct isFiniteD_reg_reg(iRegINoSp dst, fRegD src)
 7375 %{
 7376   match(Set dst (IsFiniteD src));
 7377 
 7378   format %{ "isFinite $dst, $src" %}
 7379   ins_encode %{
 7380     __ fclass_d(as_Register($dst$$reg), as_FloatRegister($src$$reg));
 7381     __ andi(as_Register($dst$$reg), as_Register($dst$$reg), 0b0001111110);
 7382     __ slt(as_Register($dst$$reg), zr, as_Register($dst$$reg));
 7383   %}
 7384 
 7385   ins_pipe(pipe_class_default);
 7386 %}
 7387 
 7388 instruct divF_reg_reg(fRegF dst, fRegF src1, fRegF src2) %{
 7389   match(Set dst (DivF src1  src2));
 7390 
 7391   ins_cost(FDIV_COST);
 7392   format %{ "fdiv.s  $dst, $src1, $src2\t#@divF_reg_reg" %}
 7393 
 7394   ins_encode %{
 7395     __ fdiv_s(as_FloatRegister($dst$$reg),
 7396               as_FloatRegister($src1$$reg),
 7397               as_FloatRegister($src2$$reg));
 7398   %}
 7399 
 7400   ins_pipe(fp_div_s);
 7401 %}
 7402 
 7403 instruct divD_reg_reg(fRegD dst, fRegD src1, fRegD src2) %{
 7404   match(Set dst (DivD src1  src2));
 7405 
 7406   ins_cost(FDIV_COST);
 7407   format %{ "fdiv.d  $dst, $src1, $src2\t#@divD_reg_reg" %}
 7408 
 7409   ins_encode %{
 7410     __ fdiv_d(as_FloatRegister($dst$$reg),
 7411               as_FloatRegister($src1$$reg),
 7412               as_FloatRegister($src2$$reg));
 7413   %}
 7414 
 7415   ins_pipe(fp_div_d);
 7416 %}
 7417 
 7418 instruct negF_reg_reg(fRegF dst, fRegF src) %{
 7419   match(Set dst (NegF src));
 7420 
 7421   ins_cost(XFER_COST);
 7422   format %{ "fsgnjn.s  $dst, $src, $src\t#@negF_reg_reg" %}
 7423 
 7424   ins_encode %{
 7425     __ fneg_s(as_FloatRegister($dst$$reg),
 7426               as_FloatRegister($src$$reg));
 7427   %}
 7428 
 7429   ins_pipe(fp_uop_s);
 7430 %}
 7431 
 7432 instruct negD_reg_reg(fRegD dst, fRegD src) %{
 7433   match(Set dst (NegD src));
 7434 
 7435   ins_cost(XFER_COST);
 7436   format %{ "fsgnjn.d  $dst, $src, $src\t#@negD_reg_reg" %}
 7437 
 7438   ins_encode %{
 7439     __ fneg_d(as_FloatRegister($dst$$reg),
 7440               as_FloatRegister($src$$reg));
 7441   %}
 7442 
 7443   ins_pipe(fp_uop_d);
 7444 %}
 7445 
 7446 instruct absI_reg(iRegINoSp dst, iRegIorL2I src) %{
 7447   match(Set dst (AbsI src));
 7448 
 7449   ins_cost(ALU_COST * 3);
 7450   format %{
 7451     "sraiw  t0, $src, 0x1f\n\t"
 7452     "addw  $dst, $src, t0\n\t"
 7453     "xorr  $dst, $dst, t0\t#@absI_reg"
 7454   %}
 7455 
 7456   ins_encode %{
 7457     __ sraiw(t0, as_Register($src$$reg), 0x1f);
 7458     __ addw(as_Register($dst$$reg), as_Register($src$$reg), t0);
 7459     __ xorr(as_Register($dst$$reg), as_Register($dst$$reg), t0);
 7460   %}
 7461 
 7462   ins_pipe(pipe_class_default);
 7463 %}
 7464 
 7465 instruct absL_reg(iRegLNoSp dst, iRegL src) %{
 7466   match(Set dst (AbsL src));
 7467 
 7468   ins_cost(ALU_COST * 3);
 7469   format %{
 7470     "srai  t0, $src, 0x3f\n\t"
 7471     "add  $dst, $src, t0\n\t"
 7472     "xorr  $dst, $dst, t0\t#@absL_reg"
 7473   %}
 7474 
 7475   ins_encode %{
 7476     __ srai(t0, as_Register($src$$reg), 0x3f);
 7477     __ add(as_Register($dst$$reg), as_Register($src$$reg), t0);
 7478     __ xorr(as_Register($dst$$reg), as_Register($dst$$reg), t0);
 7479   %}
 7480 
 7481   ins_pipe(pipe_class_default);
 7482 %}
 7483 
 7484 instruct absF_reg(fRegF dst, fRegF src) %{
 7485   match(Set dst (AbsF src));
 7486 
 7487   ins_cost(XFER_COST);
 7488   format %{ "fsgnjx.s  $dst, $src, $src\t#@absF_reg" %}
 7489   ins_encode %{
 7490     __ fabs_s(as_FloatRegister($dst$$reg),
 7491               as_FloatRegister($src$$reg));
 7492   %}
 7493 
 7494   ins_pipe(fp_uop_s);
 7495 %}
 7496 
 7497 instruct absD_reg(fRegD dst, fRegD src) %{
 7498   match(Set dst (AbsD src));
 7499 
 7500   ins_cost(XFER_COST);
 7501   format %{ "fsgnjx.d  $dst, $src, $src\t#@absD_reg" %}
 7502   ins_encode %{
 7503     __ fabs_d(as_FloatRegister($dst$$reg),
 7504               as_FloatRegister($src$$reg));
 7505   %}
 7506 
 7507   ins_pipe(fp_uop_d);
 7508 %}
 7509 
 7510 instruct sqrtF_reg(fRegF dst, fRegF src) %{
 7511   match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
 7512 
 7513   ins_cost(FSQRT_COST);
 7514   format %{ "fsqrt.s  $dst, $src\t#@sqrtF_reg" %}
 7515   ins_encode %{
 7516     __ fsqrt_s(as_FloatRegister($dst$$reg),
 7517                as_FloatRegister($src$$reg));
 7518   %}
 7519 
 7520   ins_pipe(fp_sqrt_s);
 7521 %}
 7522 
 7523 instruct sqrtD_reg(fRegD dst, fRegD src) %{
 7524   match(Set dst (SqrtD src));
 7525 
 7526   ins_cost(FSQRT_COST);
 7527   format %{ "fsqrt.d  $dst, $src\t#@sqrtD_reg" %}
 7528   ins_encode %{
 7529     __ fsqrt_d(as_FloatRegister($dst$$reg),
 7530                as_FloatRegister($src$$reg));
 7531   %}
 7532 
 7533   ins_pipe(fp_sqrt_d);
 7534 %}
 7535 
 7536 // Arithmetic Instructions End
 7537 
 7538 // ============================================================================
 7539 // Logical Instructions
 7540 
 7541 // Register And
 7542 instruct andI_reg_reg(iRegINoSp dst, iRegI src1, iRegI src2) %{
 7543   match(Set dst (AndI src1 src2));
 7544 
 7545   format %{ "andr  $dst, $src1, $src2\t#@andI_reg_reg" %}
 7546 
 7547   ins_cost(ALU_COST);
 7548   ins_encode %{
 7549     __ andr(as_Register($dst$$reg),
 7550             as_Register($src1$$reg),
 7551             as_Register($src2$$reg));
 7552   %}
 7553 
 7554   ins_pipe(ialu_reg_reg);
 7555 %}
 7556 
 7557 // Immediate And
 7558 instruct andI_reg_imm(iRegINoSp dst, iRegI src1, immIAdd src2) %{
 7559   match(Set dst (AndI src1 src2));
 7560 
 7561   format %{ "andi  $dst, $src1, $src2\t#@andI_reg_imm" %}
 7562 
 7563   ins_cost(ALU_COST);
 7564   ins_encode %{
 7565     __ andi(as_Register($dst$$reg),
 7566             as_Register($src1$$reg),
 7567             (int32_t)($src2$$constant));
 7568   %}
 7569 
 7570   ins_pipe(ialu_reg_imm);
 7571 %}
 7572 
 7573 // Register Or
 7574 instruct orI_reg_reg(iRegINoSp dst, iRegI src1, iRegI src2) %{
 7575   match(Set dst (OrI src1 src2));
 7576 
 7577   format %{ "orr  $dst, $src1, $src2\t#@orI_reg_reg" %}
 7578 
 7579   ins_cost(ALU_COST);
 7580   ins_encode %{
 7581     __ orr(as_Register($dst$$reg),
 7582            as_Register($src1$$reg),
 7583            as_Register($src2$$reg));
 7584   %}
 7585 
 7586   ins_pipe(ialu_reg_reg);
 7587 %}
 7588 
 7589 // Immediate Or
 7590 instruct orI_reg_imm(iRegINoSp dst, iRegI src1, immIAdd src2) %{
 7591   match(Set dst (OrI src1 src2));
 7592 
 7593   format %{ "ori  $dst, $src1, $src2\t#@orI_reg_imm" %}
 7594 
 7595   ins_cost(ALU_COST);
 7596   ins_encode %{
 7597     __ ori(as_Register($dst$$reg),
 7598            as_Register($src1$$reg),
 7599            (int32_t)($src2$$constant));
 7600   %}
 7601 
 7602   ins_pipe(ialu_reg_imm);
 7603 %}
 7604 
 7605 // Register Xor
 7606 instruct xorI_reg_reg(iRegINoSp dst, iRegI src1, iRegI src2) %{
 7607   match(Set dst (XorI src1 src2));
 7608 
 7609   format %{ "xorr  $dst, $src1, $src2\t#@xorI_reg_reg" %}
 7610 
 7611   ins_cost(ALU_COST);
 7612   ins_encode %{
 7613     __ xorr(as_Register($dst$$reg),
 7614             as_Register($src1$$reg),
 7615             as_Register($src2$$reg));
 7616   %}
 7617 
 7618   ins_pipe(ialu_reg_reg);
 7619 %}
 7620 
 7621 // Immediate Xor
 7622 instruct xorI_reg_imm(iRegINoSp dst, iRegI src1, immIAdd src2) %{
 7623   match(Set dst (XorI src1 src2));
 7624 
 7625   format %{ "xori  $dst, $src1, $src2\t#@xorI_reg_imm" %}
 7626 
 7627   ins_cost(ALU_COST);
 7628   ins_encode %{
 7629     __ xori(as_Register($dst$$reg),
 7630             as_Register($src1$$reg),
 7631             (int32_t)($src2$$constant));
 7632   %}
 7633 
 7634   ins_pipe(ialu_reg_imm);
 7635 %}
 7636 
 7637 // Register And Long
 7638 instruct andL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
 7639   match(Set dst (AndL src1 src2));
 7640 
 7641   format %{ "andr  $dst, $src1, $src2\t#@andL_reg_reg" %}
 7642 
 7643   ins_cost(ALU_COST);
 7644   ins_encode %{
 7645     __ andr(as_Register($dst$$reg),
 7646             as_Register($src1$$reg),
 7647             as_Register($src2$$reg));
 7648   %}
 7649 
 7650   ins_pipe(ialu_reg_reg);
 7651 %}
 7652 
 7653 // Immediate And Long
 7654 instruct andL_reg_imm(iRegLNoSp dst, iRegL src1, immLAdd src2) %{
 7655   match(Set dst (AndL src1 src2));
 7656 
 7657   format %{ "andi  $dst, $src1, $src2\t#@andL_reg_imm" %}
 7658 
 7659   ins_cost(ALU_COST);
 7660   ins_encode %{
 7661     __ andi(as_Register($dst$$reg),
 7662             as_Register($src1$$reg),
 7663             (int32_t)($src2$$constant));
 7664   %}
 7665 
 7666   ins_pipe(ialu_reg_imm);
 7667 %}
 7668 
 7669 // Register Or Long
 7670 instruct orL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
 7671   match(Set dst (OrL src1 src2));
 7672 
 7673   format %{ "orr  $dst, $src1, $src2\t#@orL_reg_reg" %}
 7674 
 7675   ins_cost(ALU_COST);
 7676   ins_encode %{
 7677     __ orr(as_Register($dst$$reg),
 7678            as_Register($src1$$reg),
 7679            as_Register($src2$$reg));
 7680   %}
 7681 
 7682   ins_pipe(ialu_reg_reg);
 7683 %}
 7684 
 7685 // Immediate Or Long
 7686 instruct orL_reg_imm(iRegLNoSp dst, iRegL src1, immLAdd src2) %{
 7687   match(Set dst (OrL src1 src2));
 7688 
 7689   format %{ "ori  $dst, $src1, $src2\t#@orL_reg_imm" %}
 7690 
 7691   ins_cost(ALU_COST);
 7692   ins_encode %{
 7693     __ ori(as_Register($dst$$reg),
 7694            as_Register($src1$$reg),
 7695            (int32_t)($src2$$constant));
 7696   %}
 7697 
 7698   ins_pipe(ialu_reg_imm);
 7699 %}
 7700 
 7701 // Register Xor Long
 7702 instruct xorL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
 7703   match(Set dst (XorL src1 src2));
 7704 
 7705   format %{ "xorr  $dst, $src1, $src2\t#@xorL_reg_reg" %}
 7706 
 7707   ins_cost(ALU_COST);
 7708   ins_encode %{
 7709     __ xorr(as_Register($dst$$reg),
 7710             as_Register($src1$$reg),
 7711             as_Register($src2$$reg));
 7712   %}
 7713 
 7714   ins_pipe(ialu_reg_reg);
 7715 %}
 7716 
 7717 // Immediate Xor Long
 7718 instruct xorL_reg_imm(iRegLNoSp dst, iRegL src1, immLAdd src2) %{
 7719   match(Set dst (XorL src1 src2));
 7720 
 7721   ins_cost(ALU_COST);
 7722   format %{ "xori  $dst, $src1, $src2\t#@xorL_reg_imm" %}
 7723 
 7724   ins_encode %{
 7725     __ xori(as_Register($dst$$reg),
 7726             as_Register($src1$$reg),
 7727             (int32_t)($src2$$constant));
 7728   %}
 7729 
 7730   ins_pipe(ialu_reg_imm);
 7731 %}
 7732 
 7733 // ============================================================================
 7734 // BSWAP Instructions
 7735 
 7736 instruct bytes_reverse_int(iRegINoSp dst, iRegIorL2I src, rFlagsReg cr) %{
 7737   match(Set dst (ReverseBytesI src));
 7738   effect(KILL cr);
 7739 
 7740   ins_cost(ALU_COST * 13);
 7741   format %{ "revb_w_w  $dst, $src\t#@bytes_reverse_int" %}
 7742 
 7743   ins_encode %{
 7744     __ revb_w_w(as_Register($dst$$reg), as_Register($src$$reg));
 7745   %}
 7746 
 7747   ins_pipe(pipe_class_default);
 7748 %}
 7749 
 7750 instruct bytes_reverse_long(iRegLNoSp dst, iRegL src, rFlagsReg cr) %{
 7751   match(Set dst (ReverseBytesL src));
 7752   effect(KILL cr);
 7753 
 7754   ins_cost(ALU_COST * 29);
 7755   format %{ "revb  $dst, $src\t#@bytes_reverse_long" %}
 7756 
 7757   ins_encode %{
 7758     __ revb(as_Register($dst$$reg), as_Register($src$$reg));
 7759   %}
 7760 
 7761   ins_pipe(pipe_class_default);
 7762 %}
 7763 
 7764 instruct bytes_reverse_unsigned_short(iRegINoSp dst, iRegIorL2I src) %{
 7765   match(Set dst (ReverseBytesUS src));
 7766 
 7767   ins_cost(ALU_COST * 5);
 7768   format %{ "revb_h_h_u  $dst, $src\t#@bytes_reverse_unsigned_short" %}
 7769 
 7770   ins_encode %{
 7771     __ revb_h_h_u(as_Register($dst$$reg), as_Register($src$$reg));
 7772   %}
 7773 
 7774   ins_pipe(pipe_class_default);
 7775 %}
 7776 
 7777 instruct bytes_reverse_short(iRegINoSp dst, iRegIorL2I src) %{
 7778   match(Set dst (ReverseBytesS src));
 7779 
 7780   ins_cost(ALU_COST * 5);
 7781   format %{ "revb_h_h  $dst, $src\t#@bytes_reverse_short" %}
 7782 
 7783   ins_encode %{
 7784     __ revb_h_h(as_Register($dst$$reg), as_Register($src$$reg));
 7785   %}
 7786 
 7787   ins_pipe(pipe_class_default);
 7788 %}
 7789 
 7790 // ============================================================================
 7791 // MemBar Instruction
 7792 
 7793 instruct load_fence() %{
 7794   match(LoadFence);
 7795   ins_cost(ALU_COST);
 7796 
 7797   format %{ "#@load_fence" %}
 7798 
 7799   ins_encode %{
 7800     __ membar(MacroAssembler::LoadLoad | MacroAssembler::LoadStore);
 7801   %}
 7802   ins_pipe(pipe_serial);
 7803 %}
 7804 
 7805 instruct membar_acquire() %{
 7806   match(MemBarAcquire);
 7807   ins_cost(ALU_COST);
 7808 
 7809   format %{ "#@membar_acquire\n\t"
 7810             "fence ir iorw" %}
 7811 
 7812   ins_encode %{
 7813     __ block_comment("membar_acquire");
 7814     __ membar(MacroAssembler::LoadLoad | MacroAssembler::LoadStore);
 7815   %}
 7816 
 7817   ins_pipe(pipe_serial);
 7818 %}
 7819 
 7820 instruct membar_acquire_lock() %{
 7821   match(MemBarAcquireLock);
 7822   ins_cost(0);
 7823 
 7824   format %{ "#@membar_acquire_lock (elided)" %}
 7825 
 7826   ins_encode %{
 7827     __ block_comment("membar_acquire_lock (elided)");
 7828   %}
 7829 
 7830   ins_pipe(pipe_serial);
 7831 %}
 7832 
 7833 instruct store_fence() %{
 7834   match(StoreFence);
 7835   ins_cost(ALU_COST);
 7836 
 7837   format %{ "#@store_fence" %}
 7838 
 7839   ins_encode %{
 7840     __ membar(MacroAssembler::LoadStore | MacroAssembler::StoreStore);
 7841   %}
 7842   ins_pipe(pipe_serial);
 7843 %}
 7844 
 7845 instruct membar_release() %{
 7846   match(MemBarRelease);
 7847   ins_cost(ALU_COST);
 7848 
 7849   format %{ "#@membar_release\n\t"
 7850             "fence iorw ow" %}
 7851 
 7852   ins_encode %{
 7853     __ block_comment("membar_release");
 7854     __ membar(MacroAssembler::LoadStore | MacroAssembler::StoreStore);
 7855   %}
 7856   ins_pipe(pipe_serial);
 7857 %}
 7858 
 7859 instruct membar_storestore() %{
 7860   match(MemBarStoreStore);
 7861   match(StoreStoreFence);
 7862   ins_cost(ALU_COST);
 7863 
 7864   format %{ "MEMBAR-store-store\t#@membar_storestore" %}
 7865 
 7866   ins_encode %{
 7867     __ membar(MacroAssembler::StoreStore);
 7868   %}
 7869   ins_pipe(pipe_serial);
 7870 %}
 7871 
 7872 instruct membar_release_lock() %{
 7873   match(MemBarReleaseLock);
 7874   ins_cost(0);
 7875 
 7876   format %{ "#@membar_release_lock (elided)" %}
 7877 
 7878   ins_encode %{
 7879     __ block_comment("membar_release_lock (elided)");
 7880   %}
 7881 
 7882   ins_pipe(pipe_serial);
 7883 %}
 7884 
 7885 instruct membar_volatile() %{
 7886   match(MemBarVolatile);
 7887   ins_cost(ALU_COST);
 7888 
 7889   format %{ "#@membar_volatile\n\t"
 7890              "fence iorw iorw"%}
 7891 
 7892   ins_encode %{
 7893     __ block_comment("membar_volatile");
 7894     __ membar(MacroAssembler::StoreLoad);
 7895   %}
 7896 
 7897   ins_pipe(pipe_serial);
 7898 %}
 7899 
 7900 instruct spin_wait() %{
 7901   predicate(UseZihintpause);
 7902   match(OnSpinWait);
 7903   ins_cost(CACHE_MISS_COST);
 7904 
 7905   format %{ "spin_wait" %}
 7906 
 7907   ins_encode %{
 7908     __ pause();
 7909   %}
 7910 
 7911   ins_pipe(pipe_serial);
 7912 %}
 7913 
 7914 // ============================================================================
 7915 // Cast Instructions (Java-level type cast)
 7916 
 7917 instruct castX2P(iRegPNoSp dst, iRegL src) %{
 7918   match(Set dst (CastX2P src));
 7919 
 7920   ins_cost(ALU_COST);
 7921   format %{ "mv  $dst, $src\t# long -> ptr, #@castX2P" %}
 7922 
 7923   ins_encode %{
 7924     if ($dst$$reg != $src$$reg) {
 7925       __ mv(as_Register($dst$$reg), as_Register($src$$reg));
 7926     }
 7927   %}
 7928 
 7929   ins_pipe(ialu_reg);
 7930 %}
 7931 
 7932 instruct castP2X(iRegLNoSp dst, iRegP src) %{
 7933   match(Set dst (CastP2X src));
 7934 
 7935   ins_cost(ALU_COST);
 7936   format %{ "mv  $dst, $src\t# ptr -> long, #@castP2X" %}
 7937 
 7938   ins_encode %{
 7939     if ($dst$$reg != $src$$reg) {
 7940       __ mv(as_Register($dst$$reg), as_Register($src$$reg));
 7941     }
 7942   %}
 7943 
 7944   ins_pipe(ialu_reg);
 7945 %}
 7946 
 7947 instruct castPP(iRegPNoSp dst)
 7948 %{
 7949   match(Set dst (CastPP dst));
 7950   ins_cost(0);
 7951 
 7952   size(0);
 7953   format %{ "# castPP of $dst, #@castPP" %}
 7954   ins_encode(/* empty encoding */);
 7955   ins_pipe(pipe_class_empty);
 7956 %}
 7957 
 7958 instruct castLL(iRegL dst)
 7959 %{
 7960   match(Set dst (CastLL dst));
 7961 
 7962   size(0);
 7963   format %{ "# castLL of $dst, #@castLL" %}
 7964   ins_encode(/* empty encoding */);
 7965   ins_cost(0);
 7966   ins_pipe(pipe_class_empty);
 7967 %}
 7968 
 7969 instruct castII(iRegI dst)
 7970 %{
 7971   match(Set dst (CastII dst));
 7972 
 7973   size(0);
 7974   format %{ "# castII of $dst, #@castII" %}
 7975   ins_encode(/* empty encoding */);
 7976   ins_cost(0);
 7977   ins_pipe(pipe_class_empty);
 7978 %}
 7979 
 7980 instruct checkCastPP(iRegPNoSp dst)
 7981 %{
 7982   match(Set dst (CheckCastPP dst));
 7983 
 7984   size(0);
 7985   ins_cost(0);
 7986   format %{ "# checkcastPP of $dst, #@checkCastPP" %}
 7987   ins_encode(/* empty encoding */);
 7988   ins_pipe(pipe_class_empty);
 7989 %}
 7990 
 7991 instruct castFF(fRegF dst)
 7992 %{
 7993   match(Set dst (CastFF dst));
 7994 
 7995   size(0);
 7996   format %{ "# castFF of $dst" %}
 7997   ins_encode(/* empty encoding */);
 7998   ins_cost(0);
 7999   ins_pipe(pipe_class_empty);
 8000 %}
 8001 
 8002 instruct castDD(fRegD dst)
 8003 %{
 8004   match(Set dst (CastDD dst));
 8005 
 8006   size(0);
 8007   format %{ "# castDD of $dst" %}
 8008   ins_encode(/* empty encoding */);
 8009   ins_cost(0);
 8010   ins_pipe(pipe_class_empty);
 8011 %}
 8012 
 8013 instruct castVV(vReg dst)
 8014 %{
 8015   match(Set dst (CastVV dst));
 8016 
 8017   size(0);
 8018   format %{ "# castVV of $dst" %}
 8019   ins_encode(/* empty encoding */);
 8020   ins_cost(0);
 8021   ins_pipe(pipe_class_empty);
 8022 %}
 8023 
 8024 // ============================================================================
 8025 // Convert Instructions
 8026 
 8027 // int to bool
 8028 instruct convI2Bool(iRegINoSp dst, iRegI src)
 8029 %{
 8030   match(Set dst (Conv2B src));
 8031 
 8032   ins_cost(ALU_COST);
 8033   format %{ "snez  $dst, $src\t#@convI2Bool" %}
 8034 
 8035   ins_encode %{
 8036     __ snez(as_Register($dst$$reg), as_Register($src$$reg));
 8037   %}
 8038 
 8039   ins_pipe(ialu_reg);
 8040 %}
 8041 
 8042 // pointer to bool
 8043 instruct convP2Bool(iRegINoSp dst, iRegP src)
 8044 %{
 8045   match(Set dst (Conv2B src));
 8046 
 8047   ins_cost(ALU_COST);
 8048   format %{ "snez  $dst, $src\t#@convP2Bool" %}
 8049 
 8050   ins_encode %{
 8051     __ snez(as_Register($dst$$reg), as_Register($src$$reg));
 8052   %}
 8053 
 8054   ins_pipe(ialu_reg);
 8055 %}
 8056 
 8057 // int <-> long
 8058 
 8059 instruct convI2L_reg_reg(iRegLNoSp dst, iRegIorL2I src)
 8060 %{
 8061   match(Set dst (ConvI2L src));
 8062 
 8063   ins_cost(ALU_COST);
 8064   format %{ "addw  $dst, $src, zr\t#@convI2L_reg_reg" %}
 8065   ins_encode %{
 8066     __ addw(as_Register($dst$$reg), as_Register($src$$reg), zr);
 8067   %}
 8068   ins_pipe(ialu_reg);
 8069 %}
 8070 
 8071 instruct convL2I_reg(iRegINoSp dst, iRegL src) %{
 8072   match(Set dst (ConvL2I src));
 8073 
 8074   ins_cost(ALU_COST);
 8075   format %{ "addw  $dst, $src, zr\t#@convL2I_reg" %}
 8076 
 8077   ins_encode %{
 8078     __ addw(as_Register($dst$$reg), as_Register($src$$reg), zr);
 8079   %}
 8080 
 8081   ins_pipe(ialu_reg);
 8082 %}
 8083 
 8084 // int to unsigned long (Zero-extend)
 8085 instruct convI2UL_reg_reg(iRegLNoSp dst, iRegIorL2I src, immL_32bits mask)
 8086 %{
 8087   match(Set dst (AndL (ConvI2L src) mask));
 8088 
 8089   ins_cost(ALU_COST * 2);
 8090   format %{ "zero_extend $dst, $src, 32\t# i2ul, #@convI2UL_reg_reg" %}
 8091 
 8092   ins_encode %{
 8093     __ zero_extend(as_Register($dst$$reg), as_Register($src$$reg), 32);
 8094   %}
 8095 
 8096   ins_pipe(ialu_reg_shift);
 8097 %}
 8098 
 8099 // float <-> double
 8100 
 8101 instruct convF2D_reg(fRegD dst, fRegF src) %{
 8102   match(Set dst (ConvF2D src));
 8103 
 8104   ins_cost(XFER_COST);
 8105   format %{ "fcvt.d.s  $dst, $src\t#@convF2D_reg" %}
 8106 
 8107   ins_encode %{
 8108     __ fcvt_d_s(as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg));
 8109   %}
 8110 
 8111   ins_pipe(fp_f2d);
 8112 %}
 8113 
 8114 instruct convD2F_reg(fRegF dst, fRegD src) %{
 8115   match(Set dst (ConvD2F src));
 8116 
 8117   ins_cost(XFER_COST);
 8118   format %{ "fcvt.s.d  $dst, $src\t#@convD2F_reg" %}
 8119 
 8120   ins_encode %{
 8121     __ fcvt_s_d(as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg));
 8122   %}
 8123 
 8124   ins_pipe(fp_d2f);
 8125 %}
 8126 
 8127 // float <-> int
 8128 
 8129 instruct convF2I_reg_reg(iRegINoSp dst, fRegF src) %{
 8130   match(Set dst (ConvF2I src));
 8131 
 8132   ins_cost(XFER_COST);
 8133   format %{ "fcvt.w.s  $dst, $src\t#@convF2I_reg_reg" %}
 8134 
 8135   ins_encode %{
 8136     __ fcvt_w_s_safe($dst$$Register, $src$$FloatRegister);
 8137   %}
 8138 
 8139   ins_pipe(fp_f2i);
 8140 %}
 8141 
 8142 instruct convI2F_reg_reg(fRegF dst, iRegIorL2I src) %{
 8143   match(Set dst (ConvI2F src));
 8144 
 8145   ins_cost(XFER_COST);
 8146   format %{ "fcvt.s.w  $dst, $src\t#@convI2F_reg_reg" %}
 8147 
 8148   ins_encode %{
 8149     __ fcvt_s_w(as_FloatRegister($dst$$reg), as_Register($src$$reg));
 8150   %}
 8151 
 8152   ins_pipe(fp_i2f);
 8153 %}
 8154 
 8155 // float <-> long
 8156 
 8157 instruct convF2L_reg_reg(iRegLNoSp dst, fRegF src) %{
 8158   match(Set dst (ConvF2L src));
 8159 
 8160   ins_cost(XFER_COST);
 8161   format %{ "fcvt.l.s  $dst, $src\t#@convF2L_reg_reg" %}
 8162 
 8163   ins_encode %{
 8164     __ fcvt_l_s_safe($dst$$Register, $src$$FloatRegister);
 8165   %}
 8166 
 8167   ins_pipe(fp_f2l);
 8168 %}
 8169 
 8170 instruct convL2F_reg_reg(fRegF dst, iRegL src) %{
 8171   match(Set dst (ConvL2F src));
 8172 
 8173   ins_cost(XFER_COST);
 8174   format %{ "fcvt.s.l  $dst, $src\t#@convL2F_reg_reg" %}
 8175 
 8176   ins_encode %{
 8177     __ fcvt_s_l(as_FloatRegister($dst$$reg), as_Register($src$$reg));
 8178   %}
 8179 
 8180   ins_pipe(fp_l2f);
 8181 %}
 8182 
 8183 // float <-> half float
 8184 
 8185 instruct convHF2F_reg_reg(fRegF dst, iRegINoSp src, fRegF tmp) %{
 8186   predicate(UseZfhmin);
 8187   match(Set dst (ConvHF2F src));
 8188   effect(TEMP tmp);
 8189 
 8190   ins_cost(XFER_COST);
 8191   format %{ "fmv.h.x $tmp, $src\t#@convHF2F_reg_reg\n\t"
 8192             "fcvt.s.h $dst, $tmp\t#@convHF2F_reg_reg"
 8193   %}
 8194 
 8195   ins_encode %{
 8196     __ fmv_h_x($tmp$$FloatRegister, $src$$Register);
 8197     __ fcvt_s_h($dst$$FloatRegister, $tmp$$FloatRegister);
 8198   %}
 8199 
 8200   ins_pipe(fp_i2f);
 8201 %}
 8202 
 8203 instruct convF2HF_reg_reg(iRegINoSp dst, fRegF src, fRegF tmp) %{
 8204   predicate(UseZfhmin);
 8205   match(Set dst (ConvF2HF src));
 8206   effect(TEMP tmp);
 8207 
 8208   ins_cost(XFER_COST);
 8209   format %{ "fcvt.h.s $tmp, $src\t#@convF2HF_reg_reg\n\t"
 8210             "fmv.x.h $dst, $tmp\t#@convF2HF_reg_reg"
 8211   %}
 8212 
 8213   ins_encode %{
 8214     __ fcvt_h_s($tmp$$FloatRegister, $src$$FloatRegister);
 8215     __ fmv_x_h($dst$$Register, $tmp$$FloatRegister);
 8216   %}
 8217 
 8218   ins_pipe(fp_f2i);
 8219 %}
 8220 
 8221 // double <-> int
 8222 
 8223 instruct convD2I_reg_reg(iRegINoSp dst, fRegD src) %{
 8224   match(Set dst (ConvD2I src));
 8225 
 8226   ins_cost(XFER_COST);
 8227   format %{ "fcvt.w.d  $dst, $src\t#@convD2I_reg_reg" %}
 8228 
 8229   ins_encode %{
 8230     __ fcvt_w_d_safe($dst$$Register, $src$$FloatRegister);
 8231   %}
 8232 
 8233   ins_pipe(fp_d2i);
 8234 %}
 8235 
 8236 instruct convI2D_reg_reg(fRegD dst, iRegIorL2I src) %{
 8237   match(Set dst (ConvI2D src));
 8238 
 8239   ins_cost(XFER_COST);
 8240   format %{ "fcvt.d.w  $dst, $src\t#@convI2D_reg_reg" %}
 8241 
 8242   ins_encode %{
 8243     __ fcvt_d_w(as_FloatRegister($dst$$reg), as_Register($src$$reg));
 8244   %}
 8245 
 8246   ins_pipe(fp_i2d);
 8247 %}
 8248 
 8249 // double <-> long
 8250 
 8251 instruct convD2L_reg_reg(iRegLNoSp dst, fRegD src) %{
 8252   match(Set dst (ConvD2L src));
 8253 
 8254   ins_cost(XFER_COST);
 8255   format %{ "fcvt.l.d  $dst, $src\t#@convD2L_reg_reg" %}
 8256 
 8257   ins_encode %{
 8258     __ fcvt_l_d_safe($dst$$Register, $src$$FloatRegister);
 8259   %}
 8260 
 8261   ins_pipe(fp_d2l);
 8262 %}
 8263 
 8264 instruct convL2D_reg_reg(fRegD dst, iRegL src) %{
 8265   match(Set dst (ConvL2D src));
 8266 
 8267   ins_cost(XFER_COST);
 8268   format %{ "fcvt.d.l  $dst, $src\t#@convL2D_reg_reg" %}
 8269 
 8270   ins_encode %{
 8271     __ fcvt_d_l(as_FloatRegister($dst$$reg), as_Register($src$$reg));
 8272   %}
 8273 
 8274   ins_pipe(fp_l2d);
 8275 %}
 8276 
 8277 // Convert oop into int for vectors alignment masking
 8278 instruct convP2I(iRegINoSp dst, iRegP src) %{
 8279   match(Set dst (ConvL2I (CastP2X src)));
 8280 
 8281   ins_cost(ALU_COST * 2);
 8282   format %{ "zero_extend $dst, $src, 32\t# ptr -> int, #@convP2I" %}
 8283 
 8284   ins_encode %{
 8285     __ zero_extend($dst$$Register, $src$$Register, 32);
 8286   %}
 8287 
 8288   ins_pipe(ialu_reg);
 8289 %}
 8290 
 8291 // Convert compressed oop into int for vectors alignment masking
 8292 // in case of 32bit oops (heap < 4Gb).
 8293 instruct convN2I(iRegINoSp dst, iRegN src)
 8294 %{
 8295   predicate(CompressedOops::shift() == 0);
 8296   match(Set dst (ConvL2I (CastP2X (DecodeN src))));
 8297 
 8298   ins_cost(ALU_COST);
 8299   format %{ "mv  $dst, $src\t# compressed ptr -> int, #@convN2I" %}
 8300 
 8301   ins_encode %{
 8302     __ mv($dst$$Register, $src$$Register);
 8303   %}
 8304 
 8305   ins_pipe(ialu_reg);
 8306 %}
 8307 
 8308 // Convert oop pointer into compressed form
 8309 instruct encodeHeapOop(iRegNNoSp dst, iRegP src) %{
 8310   match(Set dst (EncodeP src));
 8311   ins_cost(ALU_COST);
 8312   format %{ "encode_heap_oop  $dst, $src\t#@encodeHeapOop" %}
 8313   ins_encode %{
 8314     Register s = $src$$Register;
 8315     Register d = $dst$$Register;
 8316     __ encode_heap_oop(d, s);
 8317   %}
 8318   ins_pipe(pipe_class_default);
 8319 %}
 8320 
 8321 instruct decodeHeapOop(iRegPNoSp dst, iRegN src) %{
 8322   predicate(n->bottom_type()->is_ptr()->ptr() != TypePtr::NotNull &&
 8323             n->bottom_type()->is_ptr()->ptr() != TypePtr::Constant);
 8324   match(Set dst (DecodeN src));
 8325 
 8326   ins_cost(0);
 8327   format %{ "decode_heap_oop  $dst, $src\t#@decodeHeapOop" %}
 8328   ins_encode %{
 8329     Register s = $src$$Register;
 8330     Register d = $dst$$Register;
 8331     __ decode_heap_oop(d, s);
 8332   %}
 8333   ins_pipe(pipe_class_default);
 8334 %}
 8335 
 8336 instruct decodeHeapOop_not_null(iRegPNoSp dst, iRegN src) %{
 8337   predicate(n->bottom_type()->is_ptr()->ptr() == TypePtr::NotNull ||
 8338             n->bottom_type()->is_ptr()->ptr() == TypePtr::Constant);
 8339   match(Set dst (DecodeN src));
 8340 
 8341   ins_cost(0);
 8342   format %{ "decode_heap_oop_not_null $dst, $src\t#@decodeHeapOop_not_null" %}
 8343   ins_encode %{
 8344     Register s = $src$$Register;
 8345     Register d = $dst$$Register;
 8346     __ decode_heap_oop_not_null(d, s);
 8347   %}
 8348   ins_pipe(pipe_class_default);
 8349 %}
 8350 
 8351 // Convert klass pointer into compressed form.
 8352 instruct encodeKlass_not_null(iRegNNoSp dst, iRegP src) %{
 8353   match(Set dst (EncodePKlass src));
 8354 
 8355   ins_cost(ALU_COST);
 8356   format %{ "encode_klass_not_null  $dst, $src\t#@encodeKlass_not_null" %}
 8357 
 8358   ins_encode %{
 8359     Register src_reg = as_Register($src$$reg);
 8360     Register dst_reg = as_Register($dst$$reg);
 8361     __ encode_klass_not_null(dst_reg, src_reg, t0);
 8362   %}
 8363 
 8364    ins_pipe(pipe_class_default);
 8365 %}
 8366 
 8367 instruct decodeKlass_not_null(iRegPNoSp dst, iRegN src, iRegPNoSp tmp) %{
 8368   match(Set dst (DecodeNKlass src));
 8369 
 8370   effect(TEMP tmp);
 8371 
 8372   ins_cost(ALU_COST);
 8373   format %{ "decode_klass_not_null  $dst, $src\t#@decodeKlass_not_null" %}
 8374 
 8375   ins_encode %{
 8376     Register src_reg = as_Register($src$$reg);
 8377     Register dst_reg = as_Register($dst$$reg);
 8378     Register tmp_reg = as_Register($tmp$$reg);
 8379     __ decode_klass_not_null(dst_reg, src_reg, tmp_reg);
 8380   %}
 8381 
 8382    ins_pipe(pipe_class_default);
 8383 %}
 8384 
 8385 // stack <-> reg and reg <-> reg shuffles with no conversion
 8386 
 8387 instruct MoveF2I_stack_reg(iRegINoSp dst, stackSlotF src) %{
 8388 
 8389   match(Set dst (MoveF2I src));
 8390 
 8391   effect(DEF dst, USE src);
 8392 
 8393   ins_cost(LOAD_COST);
 8394 
 8395   format %{ "lw  $dst, $src\t#@MoveF2I_stack_reg" %}
 8396 
 8397   ins_encode %{
 8398     __ lw(as_Register($dst$$reg), Address(sp, $src$$disp));
 8399   %}
 8400 
 8401   ins_pipe(iload_reg_reg);
 8402 
 8403 %}
 8404 
 8405 instruct MoveI2F_stack_reg(fRegF dst, stackSlotI src) %{
 8406 
 8407   match(Set dst (MoveI2F src));
 8408 
 8409   effect(DEF dst, USE src);
 8410 
 8411   ins_cost(LOAD_COST);
 8412 
 8413   format %{ "flw  $dst, $src\t#@MoveI2F_stack_reg" %}
 8414 
 8415   ins_encode %{
 8416     __ flw(as_FloatRegister($dst$$reg), Address(sp, $src$$disp));
 8417   %}
 8418 
 8419   ins_pipe(fp_load_mem_s);
 8420 
 8421 %}
 8422 
 8423 instruct MoveD2L_stack_reg(iRegLNoSp dst, stackSlotD src) %{
 8424 
 8425   match(Set dst (MoveD2L src));
 8426 
 8427   effect(DEF dst, USE src);
 8428 
 8429   ins_cost(LOAD_COST);
 8430 
 8431   format %{ "ld  $dst, $src\t#@MoveD2L_stack_reg" %}
 8432 
 8433   ins_encode %{
 8434     __ ld(as_Register($dst$$reg), Address(sp, $src$$disp));
 8435   %}
 8436 
 8437   ins_pipe(iload_reg_reg);
 8438 
 8439 %}
 8440 
 8441 instruct MoveL2D_stack_reg(fRegD dst, stackSlotL src) %{
 8442 
 8443   match(Set dst (MoveL2D src));
 8444 
 8445   effect(DEF dst, USE src);
 8446 
 8447   ins_cost(LOAD_COST);
 8448 
 8449   format %{ "fld  $dst, $src\t#@MoveL2D_stack_reg" %}
 8450 
 8451   ins_encode %{
 8452     __ fld(as_FloatRegister($dst$$reg), Address(sp, $src$$disp));
 8453   %}
 8454 
 8455   ins_pipe(fp_load_mem_d);
 8456 
 8457 %}
 8458 
 8459 instruct MoveF2I_reg_stack(stackSlotI dst, fRegF src) %{
 8460 
 8461   match(Set dst (MoveF2I src));
 8462 
 8463   effect(DEF dst, USE src);
 8464 
 8465   ins_cost(STORE_COST);
 8466 
 8467   format %{ "fsw  $src, $dst\t#@MoveF2I_reg_stack" %}
 8468 
 8469   ins_encode %{
 8470     __ fsw(as_FloatRegister($src$$reg), Address(sp, $dst$$disp));
 8471   %}
 8472 
 8473   ins_pipe(fp_store_reg_s);
 8474 
 8475 %}
 8476 
 8477 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{
 8478 
 8479   match(Set dst (MoveI2F src));
 8480 
 8481   effect(DEF dst, USE src);
 8482 
 8483   ins_cost(STORE_COST);
 8484 
 8485   format %{ "sw  $src, $dst\t#@MoveI2F_reg_stack" %}
 8486 
 8487   ins_encode %{
 8488     __ sw(as_Register($src$$reg), Address(sp, $dst$$disp));
 8489   %}
 8490 
 8491   ins_pipe(istore_reg_reg);
 8492 
 8493 %}
 8494 
 8495 instruct MoveD2L_reg_stack(stackSlotL dst, fRegD src) %{
 8496 
 8497   match(Set dst (MoveD2L src));
 8498 
 8499   effect(DEF dst, USE src);
 8500 
 8501   ins_cost(STORE_COST);
 8502 
 8503   format %{ "fsd  $dst, $src\t#@MoveD2L_reg_stack" %}
 8504 
 8505   ins_encode %{
 8506     __ fsd(as_FloatRegister($src$$reg), Address(sp, $dst$$disp));
 8507   %}
 8508 
 8509   ins_pipe(fp_store_reg_d);
 8510 
 8511 %}
 8512 
 8513 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{
 8514 
 8515   match(Set dst (MoveL2D src));
 8516 
 8517   effect(DEF dst, USE src);
 8518 
 8519   ins_cost(STORE_COST);
 8520 
 8521   format %{ "sd  $src, $dst\t#@MoveL2D_reg_stack" %}
 8522 
 8523   ins_encode %{
 8524     __ sd(as_Register($src$$reg), Address(sp, $dst$$disp));
 8525   %}
 8526 
 8527   ins_pipe(istore_reg_reg);
 8528 
 8529 %}
 8530 
 8531 instruct MoveF2I_reg_reg(iRegINoSp dst, fRegF src) %{
 8532 
 8533   match(Set dst (MoveF2I src));
 8534 
 8535   effect(DEF dst, USE src);
 8536 
 8537   ins_cost(XFER_COST);
 8538 
 8539   format %{ "fmv.x.w  $dst, $src\t#@MoveL2D_reg_stack" %}
 8540 
 8541   ins_encode %{
 8542     __ fmv_x_w(as_Register($dst$$reg), as_FloatRegister($src$$reg));
 8543   %}
 8544 
 8545   ins_pipe(fp_f2i);
 8546 
 8547 %}
 8548 
 8549 instruct MoveI2F_reg_reg(fRegF dst, iRegI src) %{
 8550 
 8551   match(Set dst (MoveI2F src));
 8552 
 8553   effect(DEF dst, USE src);
 8554 
 8555   ins_cost(XFER_COST);
 8556 
 8557   format %{ "fmv.w.x  $dst, $src\t#@MoveI2F_reg_reg" %}
 8558 
 8559   ins_encode %{
 8560     __ fmv_w_x(as_FloatRegister($dst$$reg), as_Register($src$$reg));
 8561   %}
 8562 
 8563   ins_pipe(fp_i2f);
 8564 
 8565 %}
 8566 
 8567 instruct MoveD2L_reg_reg(iRegLNoSp dst, fRegD src) %{
 8568 
 8569   match(Set dst (MoveD2L src));
 8570 
 8571   effect(DEF dst, USE src);
 8572 
 8573   ins_cost(XFER_COST);
 8574 
 8575   format %{ "fmv.x.d $dst, $src\t#@MoveD2L_reg_reg" %}
 8576 
 8577   ins_encode %{
 8578     __ fmv_x_d(as_Register($dst$$reg), as_FloatRegister($src$$reg));
 8579   %}
 8580 
 8581   ins_pipe(fp_d2l);
 8582 
 8583 %}
 8584 
 8585 instruct MoveL2D_reg_reg(fRegD dst, iRegL src) %{
 8586 
 8587   match(Set dst (MoveL2D src));
 8588 
 8589   effect(DEF dst, USE src);
 8590 
 8591   ins_cost(XFER_COST);
 8592 
 8593   format %{ "fmv.d.x  $dst, $src\t#@MoveD2L_reg_reg" %}
 8594 
 8595   ins_encode %{
 8596     __ fmv_d_x(as_FloatRegister($dst$$reg), as_Register($src$$reg));
 8597   %}
 8598 
 8599   ins_pipe(fp_l2d);
 8600 
 8601 %}
 8602 
 8603 // ============================================================================
 8604 // Compare Instructions which set the result float comparisons in dest register.
 8605 
 8606 instruct cmpF3_reg_reg(iRegINoSp dst, fRegF op1, fRegF op2)
 8607 %{
 8608   match(Set dst (CmpF3 op1 op2));
 8609 
 8610   ins_cost(XFER_COST * 2 + BRANCH_COST + ALU_COST);
 8611   format %{ "flt.s  $dst, $op2, $op1\t#@cmpF3_reg_reg\n\t"
 8612             "bgtz   $dst, done\n\t"
 8613             "feq.s  $dst, $op1, $op2\n\t"
 8614             "addi   $dst, $dst, -1\t#@cmpF3_reg_reg"
 8615   %}
 8616 
 8617   ins_encode %{
 8618     // we want -1 for unordered or less than, 0 for equal and 1 for greater than.
 8619     __ float_compare(as_Register($dst$$reg), as_FloatRegister($op1$$reg),
 8620                      as_FloatRegister($op2$$reg), -1 /*unordered_result < 0*/);
 8621   %}
 8622 
 8623   ins_pipe(pipe_class_default);
 8624 %}
 8625 
 8626 instruct cmpD3_reg_reg(iRegINoSp dst, fRegD op1, fRegD op2)
 8627 %{
 8628   match(Set dst (CmpD3 op1 op2));
 8629 
 8630   ins_cost(XFER_COST * 2 + BRANCH_COST + ALU_COST);
 8631   format %{ "flt.d  $dst, $op2, $op1\t#@cmpD3_reg_reg\n\t"
 8632             "bgtz   $dst, done\n\t"
 8633             "feq.d  $dst, $op1, $op2\n\t"
 8634             "addi   $dst, $dst, -1\t#@cmpD3_reg_reg"
 8635   %}
 8636 
 8637   ins_encode %{
 8638     // we want -1 for unordered or less than, 0 for equal and 1 for greater than.
 8639     __ double_compare(as_Register($dst$$reg), as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg), -1 /*unordered_result < 0*/);
 8640   %}
 8641 
 8642   ins_pipe(pipe_class_default);
 8643 %}
 8644 
 8645 instruct cmpL3_reg_reg(iRegINoSp dst, iRegL op1, iRegL op2)
 8646 %{
 8647   match(Set dst (CmpL3 op1 op2));
 8648 
 8649   ins_cost(ALU_COST * 3 + BRANCH_COST);
 8650   format %{ "slt   $dst, $op2, $op1\t#@cmpL3_reg_reg\n\t"
 8651             "bnez  $dst, done\n\t"
 8652             "slt  $dst, $op1, $op2\n\t"
 8653             "neg   $dst, $dst\t#@cmpL3_reg_reg"
 8654   %}
 8655   ins_encode %{
 8656     __ cmp_l2i(t0, as_Register($op1$$reg), as_Register($op2$$reg));
 8657     __ mv(as_Register($dst$$reg), t0);
 8658   %}
 8659 
 8660   ins_pipe(pipe_class_default);
 8661 %}
 8662 
 8663 instruct cmpLTMask_reg_reg(iRegINoSp dst, iRegI p, iRegI q)
 8664 %{
 8665   match(Set dst (CmpLTMask p q));
 8666 
 8667   ins_cost(2 * ALU_COST);
 8668 
 8669   format %{ "slt $dst, $p, $q\t#@cmpLTMask_reg_reg\n\t"
 8670             "subw $dst, zr, $dst\t#@cmpLTMask_reg_reg"
 8671   %}
 8672 
 8673   ins_encode %{
 8674     __ slt(as_Register($dst$$reg), as_Register($p$$reg), as_Register($q$$reg));
 8675     __ subw(as_Register($dst$$reg), zr, as_Register($dst$$reg));
 8676   %}
 8677 
 8678   ins_pipe(ialu_reg_reg);
 8679 %}
 8680 
 8681 instruct cmpLTMask_reg_zero(iRegINoSp dst, iRegIorL2I op, immI0 zero)
 8682 %{
 8683   match(Set dst (CmpLTMask op zero));
 8684 
 8685   ins_cost(ALU_COST);
 8686 
 8687   format %{ "sraiw $dst, $dst, 31\t#@cmpLTMask_reg_reg" %}
 8688 
 8689   ins_encode %{
 8690     __ sraiw(as_Register($dst$$reg), as_Register($op$$reg), 31);
 8691   %}
 8692 
 8693   ins_pipe(ialu_reg_shift);
 8694 %}
 8695 
 8696 
 8697 // ============================================================================
 8698 // Max and Min
 8699 
 8700 instruct minI_reg_reg(iRegINoSp dst, iRegI src)
 8701 %{
 8702   match(Set dst (MinI dst src));
 8703 
 8704   ins_cost(BRANCH_COST + ALU_COST);
 8705   format %{
 8706     "ble $dst, $src, skip\t#@minI_reg_reg\n\t"
 8707     "mv  $dst, $src\n\t"
 8708     "skip:"
 8709   %}
 8710 
 8711   ins_encode %{
 8712     Label Lskip;
 8713     __ ble(as_Register($dst$$reg), as_Register($src$$reg), Lskip);
 8714     __ mv(as_Register($dst$$reg), as_Register($src$$reg));
 8715     __ bind(Lskip);
 8716   %}
 8717 
 8718   ins_pipe(pipe_class_compare);
 8719 %}
 8720 
 8721 instruct maxI_reg_reg(iRegINoSp dst, iRegI src)
 8722 %{
 8723   match(Set dst (MaxI dst src));
 8724 
 8725   ins_cost(BRANCH_COST + ALU_COST);
 8726   format %{
 8727     "bge $dst, $src, skip\t#@maxI_reg_reg\n\t"
 8728     "mv  $dst, $src\n\t"
 8729     "skip:"
 8730   %}
 8731 
 8732   ins_encode %{
 8733     Label Lskip;
 8734     __ bge(as_Register($dst$$reg), as_Register($src$$reg), Lskip);
 8735     __ mv(as_Register($dst$$reg), as_Register($src$$reg));
 8736     __ bind(Lskip);
 8737   %}
 8738 
 8739   ins_pipe(pipe_class_compare);
 8740 %}
 8741 
 8742 // special case for comparing with zero
 8743 // n.b. this is selected in preference to the rule above because it
 8744 // avoids loading constant 0 into a source register
 8745 
 8746 instruct minI_reg_zero(iRegINoSp dst, immI0 zero)
 8747 %{
 8748   match(Set dst (MinI dst zero));
 8749   match(Set dst (MinI zero dst));
 8750 
 8751   ins_cost(BRANCH_COST + ALU_COST);
 8752   format %{
 8753     "blez $dst, skip\t#@minI_reg_zero\n\t"
 8754     "mv   $dst, zr\n\t"
 8755     "skip:"
 8756   %}
 8757 
 8758   ins_encode %{
 8759     Label Lskip;
 8760     __ blez(as_Register($dst$$reg), Lskip);
 8761     __ mv(as_Register($dst$$reg), zr);
 8762     __ bind(Lskip);
 8763   %}
 8764 
 8765   ins_pipe(pipe_class_compare);
 8766 %}
 8767 
 8768 instruct maxI_reg_zero(iRegINoSp dst, immI0 zero)
 8769 %{
 8770   match(Set dst (MaxI dst zero));
 8771   match(Set dst (MaxI zero dst));
 8772 
 8773   ins_cost(BRANCH_COST + ALU_COST);
 8774   format %{
 8775     "bgez $dst, skip\t#@maxI_reg_zero\n\t"
 8776     "mv   $dst, zr\n\t"
 8777     "skip:"
 8778   %}
 8779 
 8780   ins_encode %{
 8781     Label Lskip;
 8782     __ bgez(as_Register($dst$$reg), Lskip);
 8783     __ mv(as_Register($dst$$reg), zr);
 8784     __ bind(Lskip);
 8785   %}
 8786 
 8787   ins_pipe(pipe_class_compare);
 8788 %}
 8789 
 8790 instruct minI_rReg(iRegINoSp dst, iRegI src1, iRegI src2)
 8791 %{
 8792   match(Set dst (MinI src1 src2));
 8793 
 8794   effect(DEF dst, USE src1, USE src2);
 8795 
 8796   ins_cost(BRANCH_COST + ALU_COST * 2);
 8797   format %{
 8798     "ble $src1, $src2, Lsrc1.\t#@minI_rReg\n\t"
 8799     "mv $dst, $src2\n\t"
 8800     "j Ldone\n\t"
 8801     "bind Lsrc1\n\t"
 8802     "mv $dst, $src1\n\t"
 8803     "bind\t#@minI_rReg"
 8804   %}
 8805 
 8806   ins_encode %{
 8807     Label Lsrc1, Ldone;
 8808     __ ble(as_Register($src1$$reg), as_Register($src2$$reg), Lsrc1);
 8809     __ mv(as_Register($dst$$reg), as_Register($src2$$reg));
 8810     __ j(Ldone);
 8811     __ bind(Lsrc1);
 8812     __ mv(as_Register($dst$$reg), as_Register($src1$$reg));
 8813     __ bind(Ldone);
 8814   %}
 8815 
 8816   ins_pipe(pipe_class_compare);
 8817 %}
 8818 
 8819 instruct maxI_rReg(iRegINoSp dst, iRegI src1, iRegI src2)
 8820 %{
 8821   match(Set dst (MaxI src1 src2));
 8822 
 8823   effect(DEF dst, USE src1, USE src2);
 8824 
 8825   ins_cost(BRANCH_COST + ALU_COST * 2);
 8826   format %{
 8827     "bge $src1, $src2, Lsrc1\t#@maxI_rReg\n\t"
 8828     "mv $dst, $src2\n\t"
 8829     "j Ldone\n\t"
 8830     "bind Lsrc1\n\t"
 8831     "mv $dst, $src1\n\t"
 8832     "bind\t#@maxI_rReg"
 8833   %}
 8834 
 8835   ins_encode %{
 8836     Label Lsrc1, Ldone;
 8837     __ bge(as_Register($src1$$reg), as_Register($src2$$reg), Lsrc1);
 8838     __ mv(as_Register($dst$$reg), as_Register($src2$$reg));
 8839     __ j(Ldone);
 8840     __ bind(Lsrc1);
 8841     __ mv(as_Register($dst$$reg), as_Register($src1$$reg));
 8842     __ bind(Ldone);
 8843 
 8844   %}
 8845 
 8846   ins_pipe(pipe_class_compare);
 8847 %}
 8848 
 8849 // ============================================================================
 8850 // Branch Instructions
 8851 // Direct Branch.
 8852 instruct branch(label lbl)
 8853 %{
 8854   match(Goto);
 8855 
 8856   effect(USE lbl);
 8857 
 8858   ins_cost(BRANCH_COST);
 8859   format %{ "j  $lbl\t#@branch" %}
 8860 
 8861   ins_encode(riscv_enc_j(lbl));
 8862 
 8863   ins_pipe(pipe_branch);
 8864 %}
 8865 
 8866 // ============================================================================
 8867 // Compare and Branch Instructions
 8868 
 8869 // Patterns for short (< 12KiB) variants
 8870 
 8871 // Compare flags and branch near instructions.
 8872 instruct cmpFlag_branch(cmpOpEqNe cmp, rFlagsReg cr, label lbl) %{
 8873   match(If cmp cr);
 8874   effect(USE lbl);
 8875 
 8876   ins_cost(BRANCH_COST);
 8877   format %{ "b$cmp  $cr, zr, $lbl\t#@cmpFlag_branch" %}
 8878 
 8879   ins_encode %{
 8880     __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($cr$$reg), *($lbl$$label));
 8881   %}
 8882   ins_pipe(pipe_cmpz_branch);
 8883   ins_short_branch(1);
 8884 %}
 8885 
 8886 // Compare signed int and branch near instructions
 8887 instruct cmpI_branch(cmpOp cmp, iRegI op1, iRegI op2, label lbl)
 8888 %{
 8889   // Same match rule as `far_cmpI_branch'.
 8890   match(If cmp (CmpI op1 op2));
 8891 
 8892   effect(USE lbl);
 8893 
 8894   ins_cost(BRANCH_COST);
 8895 
 8896   format %{ "b$cmp  $op1, $op2, $lbl\t#@cmpI_branch" %}
 8897 
 8898   ins_encode %{
 8899     __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label));
 8900   %}
 8901 
 8902   ins_pipe(pipe_cmp_branch);
 8903   ins_short_branch(1);
 8904 %}
 8905 
 8906 instruct cmpI_loop(cmpOp cmp, iRegI op1, iRegI op2, label lbl)
 8907 %{
 8908   // Same match rule as `far_cmpI_loop'.
 8909   match(CountedLoopEnd cmp (CmpI op1 op2));
 8910 
 8911   effect(USE lbl);
 8912 
 8913   ins_cost(BRANCH_COST);
 8914 
 8915   format %{ "b$cmp  $op1, $op2, $lbl\t#@cmpI_loop" %}
 8916 
 8917   ins_encode %{
 8918     __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label));
 8919   %}
 8920 
 8921   ins_pipe(pipe_cmp_branch);
 8922   ins_short_branch(1);
 8923 %}
 8924 
 8925 // Compare unsigned int and branch near instructions
 8926 instruct cmpU_branch(cmpOpU cmp, iRegI op1, iRegI op2, label lbl)
 8927 %{
 8928   // Same match rule as `far_cmpU_branch'.
 8929   match(If cmp (CmpU op1 op2));
 8930 
 8931   effect(USE lbl);
 8932 
 8933   ins_cost(BRANCH_COST);
 8934 
 8935   format %{ "b$cmp  $op1, $op2, $lbl\t#@cmpU_branch" %}
 8936 
 8937   ins_encode %{
 8938     __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
 8939                   as_Register($op2$$reg), *($lbl$$label));
 8940   %}
 8941 
 8942   ins_pipe(pipe_cmp_branch);
 8943   ins_short_branch(1);
 8944 %}
 8945 
 8946 instruct cmpU_loop(cmpOpU cmp, iRegI op1, iRegI op2, label lbl)
 8947 %{
 8948   // Same match rule as `far_cmpU_loop'.
 8949   match(CountedLoopEnd cmp (CmpU op1 op2));
 8950 
 8951   effect(USE lbl);
 8952 
 8953   ins_cost(BRANCH_COST);
 8954 
 8955   format %{ "b$cmp  $op1, $op2, $lbl\t#@cmpU_loop" %}
 8956 
 8957   ins_encode %{
 8958     __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
 8959                   as_Register($op2$$reg), *($lbl$$label));
 8960   %}
 8961 
 8962   ins_pipe(pipe_cmp_branch);
 8963   ins_short_branch(1);
 8964 %}
 8965 
 8966 // Compare signed long and branch near instructions
 8967 instruct cmpL_branch(cmpOp cmp, iRegL op1, iRegL op2, label lbl)
 8968 %{
 8969   // Same match rule as `far_cmpL_branch'.
 8970   match(If cmp (CmpL op1 op2));
 8971 
 8972   effect(USE lbl);
 8973 
 8974   ins_cost(BRANCH_COST);
 8975 
 8976   format %{ "b$cmp  $op1, $op2, $lbl\t#@cmpL_branch" %}
 8977 
 8978   ins_encode %{
 8979     __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label));
 8980   %}
 8981 
 8982   ins_pipe(pipe_cmp_branch);
 8983   ins_short_branch(1);
 8984 %}
 8985 
 8986 instruct cmpL_loop(cmpOp cmp, iRegL op1, iRegL op2, label lbl)
 8987 %{
 8988   // Same match rule as `far_cmpL_loop'.
 8989   match(CountedLoopEnd cmp (CmpL op1 op2));
 8990 
 8991   effect(USE lbl);
 8992 
 8993   ins_cost(BRANCH_COST);
 8994 
 8995   format %{ "b$cmp  $op1, $op2, $lbl\t#@cmpL_loop" %}
 8996 
 8997   ins_encode %{
 8998     __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label));
 8999   %}
 9000 
 9001   ins_pipe(pipe_cmp_branch);
 9002   ins_short_branch(1);
 9003 %}
 9004 
 9005 // Compare unsigned long and branch near instructions
 9006 instruct cmpUL_branch(cmpOpU cmp, iRegL op1, iRegL op2, label lbl)
 9007 %{
 9008   // Same match rule as `far_cmpUL_branch'.
 9009   match(If cmp (CmpUL op1 op2));
 9010 
 9011   effect(USE lbl);
 9012 
 9013   ins_cost(BRANCH_COST);
 9014   format %{ "b$cmp  $op1, $op2, $lbl\t#@cmpUL_branch" %}
 9015 
 9016   ins_encode %{
 9017     __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
 9018                   as_Register($op2$$reg), *($lbl$$label));
 9019   %}
 9020 
 9021   ins_pipe(pipe_cmp_branch);
 9022   ins_short_branch(1);
 9023 %}
 9024 
 9025 instruct cmpUL_loop(cmpOpU cmp, iRegL op1, iRegL op2, label lbl)
 9026 %{
 9027   // Same match rule as `far_cmpUL_loop'.
 9028   match(CountedLoopEnd cmp (CmpUL op1 op2));
 9029 
 9030   effect(USE lbl);
 9031 
 9032   ins_cost(BRANCH_COST);
 9033   format %{ "b$cmp  $op1, $op2, $lbl\t#@cmpUL_loop" %}
 9034 
 9035   ins_encode %{
 9036     __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
 9037                   as_Register($op2$$reg), *($lbl$$label));
 9038   %}
 9039 
 9040   ins_pipe(pipe_cmp_branch);
 9041   ins_short_branch(1);
 9042 %}
 9043 
 9044 // Compare pointer and branch near instructions
 9045 instruct cmpP_branch(cmpOpU cmp, iRegP op1, iRegP op2, label lbl)
 9046 %{
 9047   // Same match rule as `far_cmpP_branch'.
 9048   match(If cmp (CmpP op1 op2));
 9049 
 9050   effect(USE lbl);
 9051 
 9052   ins_cost(BRANCH_COST);
 9053 
 9054   format %{ "b$cmp  $op1, $op2, $lbl\t#@cmpP_branch" %}
 9055 
 9056   ins_encode %{
 9057     __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
 9058                   as_Register($op2$$reg), *($lbl$$label));
 9059   %}
 9060 
 9061   ins_pipe(pipe_cmp_branch);
 9062   ins_short_branch(1);
 9063 %}
 9064 
 9065 instruct cmpP_loop(cmpOpU cmp, iRegP op1, iRegP op2, label lbl)
 9066 %{
 9067   // Same match rule as `far_cmpP_loop'.
 9068   match(CountedLoopEnd cmp (CmpP op1 op2));
 9069 
 9070   effect(USE lbl);
 9071 
 9072   ins_cost(BRANCH_COST);
 9073 
 9074   format %{ "b$cmp  $op1, $op2, $lbl\t#@cmpP_loop" %}
 9075 
 9076   ins_encode %{
 9077     __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
 9078                   as_Register($op2$$reg), *($lbl$$label));
 9079   %}
 9080 
 9081   ins_pipe(pipe_cmp_branch);
 9082   ins_short_branch(1);
 9083 %}
 9084 
 9085 // Compare narrow pointer and branch near instructions
 9086 instruct cmpN_branch(cmpOpU cmp, iRegN op1, iRegN op2, label lbl)
 9087 %{
 9088   // Same match rule as `far_cmpN_branch'.
 9089   match(If cmp (CmpN op1 op2));
 9090 
 9091   effect(USE lbl);
 9092 
 9093   ins_cost(BRANCH_COST);
 9094 
 9095   format %{ "b$cmp  $op1, $op2, $lbl\t#@cmpN_branch" %}
 9096 
 9097   ins_encode %{
 9098     __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
 9099                   as_Register($op2$$reg), *($lbl$$label));
 9100   %}
 9101 
 9102   ins_pipe(pipe_cmp_branch);
 9103   ins_short_branch(1);
 9104 %}
 9105 
 9106 instruct cmpN_loop(cmpOpU cmp, iRegN op1, iRegN op2, label lbl)
 9107 %{
 9108   // Same match rule as `far_cmpN_loop'.
 9109   match(CountedLoopEnd cmp (CmpN op1 op2));
 9110 
 9111   effect(USE lbl);
 9112 
 9113   ins_cost(BRANCH_COST);
 9114 
 9115   format %{ "b$cmp  $op1, $op2, $lbl\t#@cmpN_loop" %}
 9116 
 9117   ins_encode %{
 9118     __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
 9119                   as_Register($op2$$reg), *($lbl$$label));
 9120   %}
 9121 
 9122   ins_pipe(pipe_cmp_branch);
 9123   ins_short_branch(1);
 9124 %}
 9125 
 9126 // Compare float and branch near instructions
 9127 instruct cmpF_branch(cmpOp cmp, fRegF op1, fRegF op2, label lbl)
 9128 %{
 9129   // Same match rule as `far_cmpF_branch'.
 9130   match(If cmp (CmpF op1 op2));
 9131 
 9132   effect(USE lbl);
 9133 
 9134   ins_cost(XFER_COST + BRANCH_COST);
 9135   format %{ "float_b$cmp $op1, $op2, $lbl \t#@cmpF_branch"%}
 9136 
 9137   ins_encode %{
 9138     __ float_cmp_branch($cmp$$cmpcode, as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg), *($lbl$$label));
 9139   %}
 9140 
 9141   ins_pipe(pipe_class_compare);
 9142   ins_short_branch(1);
 9143 %}
 9144 
 9145 instruct cmpF_loop(cmpOp cmp, fRegF op1, fRegF op2, label lbl)
 9146 %{
 9147   // Same match rule as `far_cmpF_loop'.
 9148   match(CountedLoopEnd cmp (CmpF op1 op2));
 9149   effect(USE lbl);
 9150 
 9151   ins_cost(XFER_COST + BRANCH_COST);
 9152   format %{ "float_b$cmp $op1, $op2, $lbl\t#@cmpF_loop"%}
 9153 
 9154   ins_encode %{
 9155     __ float_cmp_branch($cmp$$cmpcode, as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg), *($lbl$$label));
 9156   %}
 9157 
 9158   ins_pipe(pipe_class_compare);
 9159   ins_short_branch(1);
 9160 %}
 9161 
 9162 // Compare double and branch near instructions
 9163 instruct cmpD_branch(cmpOp cmp, fRegD op1, fRegD op2, label lbl)
 9164 %{
 9165   // Same match rule as `far_cmpD_branch'.
 9166   match(If cmp (CmpD op1 op2));
 9167   effect(USE lbl);
 9168 
 9169   ins_cost(XFER_COST + BRANCH_COST);
 9170   format %{ "double_b$cmp $op1, $op2, $lbl\t#@cmpD_branch"%}
 9171 
 9172   ins_encode %{
 9173     __ float_cmp_branch($cmp$$cmpcode | C2_MacroAssembler::double_branch_mask, as_FloatRegister($op1$$reg),
 9174                         as_FloatRegister($op2$$reg), *($lbl$$label));
 9175   %}
 9176 
 9177   ins_pipe(pipe_class_compare);
 9178   ins_short_branch(1);
 9179 %}
 9180 
 9181 instruct cmpD_loop(cmpOp cmp, fRegD op1, fRegD op2, label lbl)
 9182 %{
 9183   // Same match rule as `far_cmpD_loop'.
 9184   match(CountedLoopEnd cmp (CmpD op1 op2));
 9185   effect(USE lbl);
 9186 
 9187   ins_cost(XFER_COST + BRANCH_COST);
 9188   format %{ "double_b$cmp $op1, $op2, $lbl\t#@cmpD_loop"%}
 9189 
 9190   ins_encode %{
 9191     __ float_cmp_branch($cmp$$cmpcode | C2_MacroAssembler::double_branch_mask, as_FloatRegister($op1$$reg),
 9192                         as_FloatRegister($op2$$reg), *($lbl$$label));
 9193   %}
 9194 
 9195   ins_pipe(pipe_class_compare);
 9196   ins_short_branch(1);
 9197 %}
 9198 
 9199 // Compare signed int with zero and branch near instructions
 9200 instruct cmpI_reg_imm0_branch(cmpOp cmp, iRegI op1, immI0 zero, label lbl)
 9201 %{
 9202   // Same match rule as `far_cmpI_reg_imm0_branch'.
 9203   match(If cmp (CmpI op1 zero));
 9204 
 9205   effect(USE op1, USE lbl);
 9206 
 9207   ins_cost(BRANCH_COST);
 9208   format %{ "b$cmp  $op1, zr, $lbl\t#@cmpI_reg_imm0_branch" %}
 9209 
 9210   ins_encode %{
 9211     __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label));
 9212   %}
 9213 
 9214   ins_pipe(pipe_cmpz_branch);
 9215   ins_short_branch(1);
 9216 %}
 9217 
 9218 instruct cmpI_reg_imm0_loop(cmpOp cmp, iRegI op1, immI0 zero, label lbl)
 9219 %{
 9220   // Same match rule as `far_cmpI_reg_imm0_loop'.
 9221   match(CountedLoopEnd cmp (CmpI op1 zero));
 9222 
 9223   effect(USE op1, USE lbl);
 9224 
 9225   ins_cost(BRANCH_COST);
 9226 
 9227   format %{ "b$cmp  $op1, zr, $lbl\t#@cmpI_reg_imm0_loop" %}
 9228 
 9229   ins_encode %{
 9230     __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label));
 9231   %}
 9232 
 9233   ins_pipe(pipe_cmpz_branch);
 9234   ins_short_branch(1);
 9235 %}
 9236 
 9237 // Compare unsigned int with zero and branch near instructions
 9238 instruct cmpUEqNeLeGt_reg_imm0_branch(cmpOpUEqNeLeGt cmp, iRegI op1, immI0 zero, label lbl)
 9239 %{
 9240   // Same match rule as `far_cmpUEqNeLeGt_reg_imm0_branch'.
 9241   match(If cmp (CmpU op1 zero));
 9242 
 9243   effect(USE op1, USE lbl);
 9244 
 9245   ins_cost(BRANCH_COST);
 9246 
 9247   format %{ "b$cmp  $op1, zr, $lbl\t#@cmpUEqNeLeGt_reg_imm0_branch" %}
 9248 
 9249   ins_encode %{
 9250     __ enc_cmpUEqNeLeGt_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
 9251   %}
 9252 
 9253   ins_pipe(pipe_cmpz_branch);
 9254   ins_short_branch(1);
 9255 %}
 9256 
 9257 instruct cmpUEqNeLeGt_reg_imm0_loop(cmpOpUEqNeLeGt cmp, iRegI op1, immI0 zero, label lbl)
 9258 %{
 9259   // Same match rule as `far_cmpUEqNeLeGt_reg_imm0_loop'.
 9260   match(CountedLoopEnd cmp (CmpU op1 zero));
 9261 
 9262   effect(USE op1, USE lbl);
 9263 
 9264   ins_cost(BRANCH_COST);
 9265 
 9266   format %{ "b$cmp  $op1, zr, $lbl\t#@cmpUEqNeLeGt_reg_imm0_loop" %}
 9267 
 9268 
 9269   ins_encode %{
 9270     __ enc_cmpUEqNeLeGt_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
 9271   %}
 9272 
 9273   ins_pipe(pipe_cmpz_branch);
 9274   ins_short_branch(1);
 9275 %}
 9276 
 9277 // Compare signed long with zero and branch near instructions
 9278 instruct cmpL_reg_imm0_branch(cmpOp cmp, iRegL op1, immL0 zero, label lbl)
 9279 %{
 9280   // Same match rule as `far_cmpL_reg_imm0_branch'.
 9281   match(If cmp (CmpL op1 zero));
 9282 
 9283   effect(USE op1, USE lbl);
 9284 
 9285   ins_cost(BRANCH_COST);
 9286 
 9287   format %{ "b$cmp  $op1, zr, $lbl\t#@cmpL_reg_imm0_branch" %}
 9288 
 9289   ins_encode %{
 9290     __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label));
 9291   %}
 9292 
 9293   ins_pipe(pipe_cmpz_branch);
 9294   ins_short_branch(1);
 9295 %}
 9296 
 9297 instruct cmpL_reg_imm0_loop(cmpOp cmp, iRegL op1, immL0 zero, label lbl)
 9298 %{
 9299   // Same match rule as `far_cmpL_reg_imm0_loop'.
 9300   match(CountedLoopEnd cmp (CmpL op1 zero));
 9301 
 9302   effect(USE op1, USE lbl);
 9303 
 9304   ins_cost(BRANCH_COST);
 9305 
 9306   format %{ "b$cmp  $op1, zr, $lbl\t#@cmpL_reg_imm0_loop" %}
 9307 
 9308   ins_encode %{
 9309     __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label));
 9310   %}
 9311 
 9312   ins_pipe(pipe_cmpz_branch);
 9313   ins_short_branch(1);
 9314 %}
 9315 
 9316 // Compare unsigned long with zero and branch near instructions
 9317 instruct cmpULEqNeLeGt_reg_imm0_branch(cmpOpUEqNeLeGt cmp, iRegL op1, immL0 zero, label lbl)
 9318 %{
 9319   // Same match rule as `far_cmpULEqNeLeGt_reg_imm0_branch'.
 9320   match(If cmp (CmpUL op1 zero));
 9321 
 9322   effect(USE op1, USE lbl);
 9323 
 9324   ins_cost(BRANCH_COST);
 9325 
 9326   format %{ "b$cmp  $op1, zr, $lbl\t#@cmpULEqNeLeGt_reg_imm0_branch" %}
 9327 
 9328   ins_encode %{
 9329     __ enc_cmpUEqNeLeGt_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
 9330   %}
 9331 
 9332   ins_pipe(pipe_cmpz_branch);
 9333   ins_short_branch(1);
 9334 %}
 9335 
 9336 instruct cmpULEqNeLeGt_reg_imm0_loop(cmpOpUEqNeLeGt cmp, iRegL op1, immL0 zero, label lbl)
 9337 %{
 9338   // Same match rule as `far_cmpULEqNeLeGt_reg_imm0_loop'.
 9339   match(CountedLoopEnd cmp (CmpUL op1 zero));
 9340 
 9341   effect(USE op1, USE lbl);
 9342 
 9343   ins_cost(BRANCH_COST);
 9344 
 9345   format %{ "b$cmp  $op1, zr, $lbl\t#@cmpULEqNeLeGt_reg_imm0_loop" %}
 9346 
 9347   ins_encode %{
 9348     __ enc_cmpUEqNeLeGt_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
 9349   %}
 9350 
 9351   ins_pipe(pipe_cmpz_branch);
 9352   ins_short_branch(1);
 9353 %}
 9354 
 9355 // Compare pointer with zero and branch near instructions
 9356 instruct cmpP_imm0_branch(cmpOpEqNe cmp, iRegP op1, immP0 zero, label lbl) %{
 9357   // Same match rule as `far_cmpP_reg_imm0_branch'.
 9358   match(If cmp (CmpP op1 zero));
 9359   effect(USE lbl);
 9360 
 9361   ins_cost(BRANCH_COST);
 9362   format %{ "b$cmp   $op1, zr, $lbl\t#@cmpP_imm0_branch" %}
 9363 
 9364   ins_encode %{
 9365     __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
 9366   %}
 9367 
 9368   ins_pipe(pipe_cmpz_branch);
 9369   ins_short_branch(1);
 9370 %}
 9371 
 9372 instruct cmpP_imm0_loop(cmpOpEqNe cmp, iRegP op1, immP0 zero, label lbl) %{
 9373   // Same match rule as `far_cmpP_reg_imm0_loop'.
 9374   match(CountedLoopEnd cmp (CmpP op1 zero));
 9375   effect(USE lbl);
 9376 
 9377   ins_cost(BRANCH_COST);
 9378   format %{ "b$cmp   $op1, zr, $lbl\t#@cmpP_imm0_loop" %}
 9379 
 9380   ins_encode %{
 9381     __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
 9382   %}
 9383 
 9384   ins_pipe(pipe_cmpz_branch);
 9385   ins_short_branch(1);
 9386 %}
 9387 
 9388 // Compare narrow pointer with zero and branch near instructions
 9389 instruct cmpN_imm0_branch(cmpOpEqNe cmp, iRegN op1, immN0 zero, label lbl) %{
 9390   // Same match rule as `far_cmpN_reg_imm0_branch'.
 9391   match(If cmp (CmpN op1 zero));
 9392   effect(USE lbl);
 9393 
 9394   ins_cost(BRANCH_COST);
 9395 
 9396   format %{ "b$cmp  $op1, zr, $lbl\t#@cmpN_imm0_branch" %}
 9397 
 9398   ins_encode %{
 9399     __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
 9400   %}
 9401 
 9402   ins_pipe(pipe_cmpz_branch);
 9403   ins_short_branch(1);
 9404 %}
 9405 
 9406 instruct cmpN_imm0_loop(cmpOpEqNe cmp, iRegN op1, immN0 zero, label lbl) %{
 9407   // Same match rule as `far_cmpN_reg_imm0_loop'.
 9408   match(CountedLoopEnd cmp (CmpN op1 zero));
 9409   effect(USE lbl);
 9410 
 9411   ins_cost(BRANCH_COST);
 9412 
 9413   format %{ "b$cmp  $op1, zr, $lbl\t#@cmpN_imm0_loop" %}
 9414 
 9415   ins_encode %{
 9416     __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
 9417   %}
 9418 
 9419   ins_pipe(pipe_cmpz_branch);
 9420   ins_short_branch(1);
 9421 %}
 9422 
 9423 // Compare narrow pointer with pointer zero and branch near instructions
 9424 instruct cmpP_narrowOop_imm0_branch(cmpOpEqNe cmp, iRegN op1, immP0 zero, label lbl) %{
 9425   // Same match rule as `far_cmpP_narrowOop_imm0_branch'.
 9426   match(If cmp (CmpP (DecodeN op1) zero));
 9427   effect(USE lbl);
 9428 
 9429   ins_cost(BRANCH_COST);
 9430   format %{ "b$cmp   $op1, zr, $lbl\t#@cmpP_narrowOop_imm0_branch" %}
 9431 
 9432   ins_encode %{
 9433     __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
 9434   %}
 9435 
 9436   ins_pipe(pipe_cmpz_branch);
 9437   ins_short_branch(1);
 9438 %}
 9439 
 9440 instruct cmpP_narrowOop_imm0_loop(cmpOpEqNe cmp, iRegN op1, immP0 zero, label lbl) %{
 9441   // Same match rule as `far_cmpP_narrowOop_imm0_loop'.
 9442   match(CountedLoopEnd cmp (CmpP (DecodeN op1) zero));
 9443   effect(USE lbl);
 9444 
 9445   ins_cost(BRANCH_COST);
 9446   format %{ "b$cmp   $op1, zr, $lbl\t#@cmpP_narrowOop_imm0_loop" %}
 9447 
 9448   ins_encode %{
 9449     __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
 9450   %}
 9451 
 9452   ins_pipe(pipe_cmpz_branch);
 9453   ins_short_branch(1);
 9454 %}
 9455 
 9456 // Patterns for far (20KiB) variants
 9457 
 9458 instruct far_cmpFlag_branch(cmpOp cmp, rFlagsReg cr, label lbl) %{
 9459   match(If cmp cr);
 9460   effect(USE lbl);
 9461 
 9462   ins_cost(BRANCH_COST);
 9463   format %{ "far_b$cmp $cr, zr, $lbl\t#@far_cmpFlag_branch"%}
 9464 
 9465   ins_encode %{
 9466     __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($cr$$reg), *($lbl$$label), /* is_far */ true);
 9467   %}
 9468 
 9469   ins_pipe(pipe_cmpz_branch);
 9470 %}
 9471 
 9472 // Compare signed int and branch far instructions
 9473 instruct far_cmpI_branch(cmpOp cmp, iRegI op1, iRegI op2, label lbl) %{
 9474   match(If cmp (CmpI op1 op2));
 9475   effect(USE lbl);
 9476 
 9477   ins_cost(BRANCH_COST * 2);
 9478 
 9479   // the format instruction [far_b$cmp] here is be used as two insructions
 9480   // in macroassembler: b$not_cmp(op1, op2, done), j($lbl), bind(done)
 9481   format %{ "far_b$cmp  $op1, $op2, $lbl\t#@far_cmpI_branch" %}
 9482 
 9483   ins_encode %{
 9484     __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
 9485   %}
 9486 
 9487   ins_pipe(pipe_cmp_branch);
 9488 %}
 9489 
 9490 instruct far_cmpI_loop(cmpOp cmp, iRegI op1, iRegI op2, label lbl) %{
 9491   match(CountedLoopEnd cmp (CmpI op1 op2));
 9492   effect(USE lbl);
 9493 
 9494   ins_cost(BRANCH_COST * 2);
 9495   format %{ "far_b$cmp  $op1, $op2, $lbl\t#@far_cmpI_loop" %}
 9496 
 9497   ins_encode %{
 9498     __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
 9499   %}
 9500 
 9501   ins_pipe(pipe_cmp_branch);
 9502 %}
 9503 
 9504 instruct far_cmpU_branch(cmpOpU cmp, iRegI op1, iRegI op2, label lbl) %{
 9505   match(If cmp (CmpU op1 op2));
 9506   effect(USE lbl);
 9507 
 9508   ins_cost(BRANCH_COST * 2);
 9509   format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpU_branch" %}
 9510 
 9511   ins_encode %{
 9512     __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
 9513                        as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
 9514   %}
 9515 
 9516   ins_pipe(pipe_cmp_branch);
 9517 %}
 9518 
 9519 instruct far_cmpU_loop(cmpOpU cmp, iRegI op1, iRegI op2, label lbl) %{
 9520   match(CountedLoopEnd cmp (CmpU op1 op2));
 9521   effect(USE lbl);
 9522 
 9523   ins_cost(BRANCH_COST * 2);
 9524   format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpU_loop" %}
 9525 
 9526   ins_encode %{
 9527     __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
 9528                        as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
 9529   %}
 9530 
 9531   ins_pipe(pipe_cmp_branch);
 9532 %}
 9533 
 9534 instruct far_cmpL_branch(cmpOp cmp, iRegL op1, iRegL op2, label lbl) %{
 9535   match(If cmp (CmpL op1 op2));
 9536   effect(USE lbl);
 9537 
 9538   ins_cost(BRANCH_COST * 2);
 9539   format %{ "far_b$cmp  $op1, $op2, $lbl\t#@far_cmpL_branch" %}
 9540 
 9541   ins_encode %{
 9542     __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
 9543   %}
 9544 
 9545   ins_pipe(pipe_cmp_branch);
 9546 %}
 9547 
 9548 instruct far_cmpLloop(cmpOp cmp, iRegL op1, iRegL op2, label lbl) %{
 9549   match(CountedLoopEnd cmp (CmpL op1 op2));
 9550   effect(USE lbl);
 9551 
 9552   ins_cost(BRANCH_COST * 2);
 9553   format %{ "far_b$cmp  $op1, $op2, $lbl\t#@far_cmpL_loop" %}
 9554 
 9555   ins_encode %{
 9556     __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
 9557   %}
 9558 
 9559   ins_pipe(pipe_cmp_branch);
 9560 %}
 9561 
 9562 instruct far_cmpUL_branch(cmpOpU cmp, iRegL op1, iRegL op2, label lbl) %{
 9563   match(If cmp (CmpUL op1 op2));
 9564   effect(USE lbl);
 9565 
 9566   ins_cost(BRANCH_COST * 2);
 9567   format %{ "far_b$cmp  $op1, $op2, $lbl\t#@far_cmpUL_branch" %}
 9568 
 9569   ins_encode %{
 9570     __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
 9571                        as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
 9572   %}
 9573 
 9574   ins_pipe(pipe_cmp_branch);
 9575 %}
 9576 
 9577 instruct far_cmpUL_loop(cmpOpU cmp, iRegL op1, iRegL op2, label lbl) %{
 9578   match(CountedLoopEnd cmp (CmpUL op1 op2));
 9579   effect(USE lbl);
 9580 
 9581   ins_cost(BRANCH_COST * 2);
 9582   format %{ "far_b$cmp  $op1, $op2, $lbl\t#@far_cmpUL_loop" %}
 9583 
 9584   ins_encode %{
 9585     __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
 9586                        as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
 9587   %}
 9588 
 9589   ins_pipe(pipe_cmp_branch);
 9590 %}
 9591 
 9592 instruct far_cmpP_branch(cmpOpU cmp, iRegP op1, iRegP op2, label lbl)
 9593 %{
 9594   match(If cmp (CmpP op1 op2));
 9595 
 9596   effect(USE lbl);
 9597 
 9598   ins_cost(BRANCH_COST * 2);
 9599 
 9600   format %{ "far_b$cmp  $op1, $op2, $lbl\t#@far_cmpP_branch" %}
 9601 
 9602   ins_encode %{
 9603     __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
 9604                        as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
 9605   %}
 9606 
 9607   ins_pipe(pipe_cmp_branch);
 9608 %}
 9609 
 9610 instruct far_cmpP_loop(cmpOpU cmp, iRegP op1, iRegP op2, label lbl)
 9611 %{
 9612   match(CountedLoopEnd cmp (CmpP op1 op2));
 9613 
 9614   effect(USE lbl);
 9615 
 9616   ins_cost(BRANCH_COST * 2);
 9617 
 9618   format %{ "far_b$cmp  $op1, $op2, $lbl\t#@far_cmpP_loop" %}
 9619 
 9620   ins_encode %{
 9621     __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
 9622                        as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
 9623   %}
 9624 
 9625   ins_pipe(pipe_cmp_branch);
 9626 %}
 9627 
 9628 instruct far_cmpN_branch(cmpOpU cmp, iRegN op1, iRegN op2, label lbl)
 9629 %{
 9630   match(If cmp (CmpN op1 op2));
 9631 
 9632   effect(USE lbl);
 9633 
 9634   ins_cost(BRANCH_COST * 2);
 9635 
 9636   format %{ "far_b$cmp  $op1, $op2, $lbl\t#@far_cmpN_branch" %}
 9637 
 9638   ins_encode %{
 9639     __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
 9640                        as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
 9641   %}
 9642 
 9643   ins_pipe(pipe_cmp_branch);
 9644 %}
 9645 
 9646 instruct far_cmpN_loop(cmpOpU cmp, iRegN op1, iRegN op2, label lbl)
 9647 %{
 9648   match(CountedLoopEnd cmp (CmpN op1 op2));
 9649 
 9650   effect(USE lbl);
 9651 
 9652   ins_cost(BRANCH_COST * 2);
 9653 
 9654   format %{ "far_b$cmp  $op1, $op2, $lbl\t#@far_cmpN_loop" %}
 9655 
 9656   ins_encode %{
 9657     __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
 9658                   as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
 9659   %}
 9660 
 9661   ins_pipe(pipe_cmp_branch);
 9662 %}
 9663 
 9664 // Float compare and branch instructions
 9665 instruct far_cmpF_branch(cmpOp cmp, fRegF op1, fRegF op2, label lbl)
 9666 %{
 9667   match(If cmp (CmpF op1 op2));
 9668 
 9669   effect(USE lbl);
 9670 
 9671   ins_cost(XFER_COST + BRANCH_COST * 2);
 9672   format %{ "far_float_b$cmp $op1, $op2, $lbl\t#@far_cmpF_branch"%}
 9673 
 9674   ins_encode %{
 9675     __ float_cmp_branch($cmp$$cmpcode, as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg),
 9676                         *($lbl$$label), /* is_far */ true);
 9677   %}
 9678 
 9679   ins_pipe(pipe_class_compare);
 9680 %}
 9681 
 9682 instruct far_cmpF_loop(cmpOp cmp, fRegF op1, fRegF op2, label lbl)
 9683 %{
 9684   match(CountedLoopEnd cmp (CmpF op1 op2));
 9685   effect(USE lbl);
 9686 
 9687   ins_cost(XFER_COST + BRANCH_COST * 2);
 9688   format %{ "far_float_b$cmp $op1, $op2, $lbl\t#@far_cmpF_loop"%}
 9689 
 9690   ins_encode %{
 9691     __ float_cmp_branch($cmp$$cmpcode, as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg),
 9692                         *($lbl$$label), /* is_far */ true);
 9693   %}
 9694 
 9695   ins_pipe(pipe_class_compare);
 9696 %}
 9697 
 9698 // Double compare and branch instructions
 9699 instruct far_cmpD_branch(cmpOp cmp, fRegD op1, fRegD op2, label lbl)
 9700 %{
 9701   match(If cmp (CmpD op1 op2));
 9702   effect(USE lbl);
 9703 
 9704   ins_cost(XFER_COST + BRANCH_COST * 2);
 9705   format %{ "far_double_b$cmp $op1, $op2, $lbl\t#@far_cmpD_branch"%}
 9706 
 9707   ins_encode %{
 9708     __ float_cmp_branch($cmp$$cmpcode | C2_MacroAssembler::double_branch_mask, as_FloatRegister($op1$$reg),
 9709                         as_FloatRegister($op2$$reg), *($lbl$$label), /* is_far */ true);
 9710   %}
 9711 
 9712   ins_pipe(pipe_class_compare);
 9713 %}
 9714 
 9715 instruct far_cmpD_loop(cmpOp cmp, fRegD op1, fRegD op2, label lbl)
 9716 %{
 9717   match(CountedLoopEnd cmp (CmpD op1 op2));
 9718   effect(USE lbl);
 9719 
 9720   ins_cost(XFER_COST + BRANCH_COST * 2);
 9721   format %{ "far_double_b$cmp $op1, $op2, $lbl\t#@far_cmpD_loop"%}
 9722 
 9723   ins_encode %{
 9724     __ float_cmp_branch($cmp$$cmpcode | C2_MacroAssembler::double_branch_mask, as_FloatRegister($op1$$reg),
 9725                         as_FloatRegister($op2$$reg), *($lbl$$label), /* is_far */ true);
 9726   %}
 9727 
 9728   ins_pipe(pipe_class_compare);
 9729 %}
 9730 
 9731 instruct far_cmpI_reg_imm0_branch(cmpOp cmp, iRegI op1, immI0 zero, label lbl)
 9732 %{
 9733   match(If cmp (CmpI op1 zero));
 9734 
 9735   effect(USE op1, USE lbl);
 9736 
 9737   ins_cost(BRANCH_COST * 2);
 9738 
 9739   format %{ "far_b$cmp  $op1, zr, $lbl\t#@far_cmpI_reg_imm0_branch" %}
 9740 
 9741   ins_encode %{
 9742     __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label), /* is_far */ true);
 9743   %}
 9744 
 9745   ins_pipe(pipe_cmpz_branch);
 9746 %}
 9747 
 9748 instruct far_cmpI_reg_imm0_loop(cmpOp cmp, iRegI op1, immI0 zero, label lbl)
 9749 %{
 9750   match(CountedLoopEnd cmp (CmpI op1 zero));
 9751 
 9752   effect(USE op1, USE lbl);
 9753 
 9754   ins_cost(BRANCH_COST * 2);
 9755 
 9756   format %{ "far_b$cmp  $op1, zr, $lbl\t#@far_cmpI_reg_imm0_loop" %}
 9757 
 9758   ins_encode %{
 9759     __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label), /* is_far */ true);
 9760   %}
 9761 
 9762   ins_pipe(pipe_cmpz_branch);
 9763 %}
 9764 
 9765 instruct far_cmpUEqNeLeGt_imm0_branch(cmpOpUEqNeLeGt cmp, iRegI op1, immI0 zero, label lbl)
 9766 %{
 9767   match(If cmp (CmpU op1 zero));
 9768 
 9769   effect(USE op1, USE lbl);
 9770 
 9771   ins_cost(BRANCH_COST * 2);
 9772 
 9773   format %{ "far_b$cmp  $op1, zr, $lbl\t#@far_cmpUEqNeLeGt_imm0_branch" %}
 9774 
 9775   ins_encode %{
 9776     __ enc_cmpUEqNeLeGt_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
 9777   %}
 9778 
 9779   ins_pipe(pipe_cmpz_branch);
 9780 %}
 9781 
 9782 instruct far_cmpUEqNeLeGt_reg_imm0_loop(cmpOpUEqNeLeGt cmp, iRegI op1, immI0 zero, label lbl)
 9783 %{
 9784   match(CountedLoopEnd cmp (CmpU op1 zero));
 9785 
 9786   effect(USE op1, USE lbl);
 9787 
 9788   ins_cost(BRANCH_COST * 2);
 9789 
 9790   format %{ "far_b$cmp  $op1, zr, $lbl\t#@far_cmpUEqNeLeGt_reg_imm0_loop" %}
 9791 
 9792 
 9793   ins_encode %{
 9794     __ enc_cmpUEqNeLeGt_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
 9795   %}
 9796 
 9797   ins_pipe(pipe_cmpz_branch);
 9798 %}
 9799 
 9800 // compare lt/ge unsigned instructs has no short instruct with same match
 9801 instruct far_cmpULtGe_reg_imm0_branch(cmpOpULtGe cmp, iRegI op1, immI0 zero, label lbl)
 9802 %{
 9803   match(If cmp (CmpU op1 zero));
 9804 
 9805   effect(USE op1, USE lbl);
 9806 
 9807   ins_cost(BRANCH_COST);
 9808 
 9809   format %{ "j  $lbl if $cmp == ge\t#@far_cmpULtGe_reg_imm0_branch" %}
 9810 
 9811   ins_encode(riscv_enc_far_cmpULtGe_imm0_branch(cmp, op1, lbl));
 9812 
 9813   ins_pipe(pipe_cmpz_branch);
 9814 %}
 9815 
 9816 instruct far_cmpULtGe_reg_imm0_loop(cmpOpULtGe cmp, iRegI op1, immI0 zero, label lbl)
 9817 %{
 9818   match(CountedLoopEnd cmp (CmpU op1 zero));
 9819 
 9820   effect(USE op1, USE lbl);
 9821 
 9822   ins_cost(BRANCH_COST);
 9823 
 9824   format %{ "j  $lbl if $cmp == ge\t#@far_cmpULtGe_reg_imm0_loop" %}
 9825 
 9826   ins_encode(riscv_enc_far_cmpULtGe_imm0_branch(cmp, op1, lbl));
 9827 
 9828   ins_pipe(pipe_cmpz_branch);
 9829 %}
 9830 
 9831 instruct far_cmpL_reg_imm0_branch(cmpOp cmp, iRegL op1, immL0 zero, label lbl)
 9832 %{
 9833   match(If cmp (CmpL op1 zero));
 9834 
 9835   effect(USE op1, USE lbl);
 9836 
 9837   ins_cost(BRANCH_COST * 2);
 9838 
 9839   format %{ "far_b$cmp  $op1, zr, $lbl\t#@far_cmpL_reg_imm0_branch" %}
 9840 
 9841   ins_encode %{
 9842     __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label), /* is_far */ true);
 9843   %}
 9844 
 9845   ins_pipe(pipe_cmpz_branch);
 9846 %}
 9847 
 9848 instruct far_cmpL_reg_imm0_loop(cmpOp cmp, iRegL op1, immL0 zero, label lbl)
 9849 %{
 9850   match(CountedLoopEnd cmp (CmpL op1 zero));
 9851 
 9852   effect(USE op1, USE lbl);
 9853 
 9854   ins_cost(BRANCH_COST * 2);
 9855 
 9856   format %{ "far_b$cmp  $op1, zr, $lbl\t#@far_cmpL_reg_imm0_loop" %}
 9857 
 9858   ins_encode %{
 9859     __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label), /* is_far */ true);
 9860   %}
 9861 
 9862   ins_pipe(pipe_cmpz_branch);
 9863 %}
 9864 
 9865 instruct far_cmpULEqNeLeGt_reg_imm0_branch(cmpOpUEqNeLeGt cmp, iRegL op1, immL0 zero, label lbl)
 9866 %{
 9867   match(If cmp (CmpUL op1 zero));
 9868 
 9869   effect(USE op1, USE lbl);
 9870 
 9871   ins_cost(BRANCH_COST * 2);
 9872 
 9873   format %{ "far_b$cmp  $op1, zr, $lbl\t#@far_cmpULEqNeLeGt_reg_imm0_branch" %}
 9874 
 9875   ins_encode %{
 9876     __ enc_cmpUEqNeLeGt_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
 9877   %}
 9878 
 9879   ins_pipe(pipe_cmpz_branch);
 9880 %}
 9881 
 9882 instruct far_cmpULEqNeLeGt_reg_imm0_loop(cmpOpUEqNeLeGt cmp, iRegL op1, immL0 zero, label lbl)
 9883 %{
 9884   match(CountedLoopEnd cmp (CmpUL op1 zero));
 9885 
 9886   effect(USE op1, USE lbl);
 9887 
 9888   ins_cost(BRANCH_COST * 2);
 9889 
 9890   format %{ "far_b$cmp  $op1, zr, $lbl\t#@far_cmpULEqNeLeGt_reg_imm0_loop" %}
 9891 
 9892   ins_encode %{
 9893     __ enc_cmpUEqNeLeGt_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
 9894   %}
 9895 
 9896   ins_pipe(pipe_cmpz_branch);
 9897 %}
 9898 
 9899 // compare lt/ge unsigned instructs has no short instruct with same match
 9900 instruct far_cmpULLtGe_reg_imm0_branch(cmpOpULtGe cmp, iRegL op1, immL0 zero, label lbl)
 9901 %{
 9902   match(If cmp (CmpUL op1 zero));
 9903 
 9904   effect(USE op1, USE lbl);
 9905 
 9906   ins_cost(BRANCH_COST);
 9907 
 9908   format %{ "j  $lbl if $cmp == ge\t#@far_cmpULLtGe_reg_imm0_branch" %}
 9909 
 9910   ins_encode(riscv_enc_far_cmpULtGe_imm0_branch(cmp, op1, lbl));
 9911 
 9912   ins_pipe(pipe_cmpz_branch);
 9913 %}
 9914 
 9915 instruct far_cmpULLtGe_reg_imm0_loop(cmpOpULtGe cmp, iRegL op1, immL0 zero, label lbl)
 9916 %{
 9917   match(CountedLoopEnd cmp (CmpUL op1 zero));
 9918 
 9919   effect(USE op1, USE lbl);
 9920 
 9921   ins_cost(BRANCH_COST);
 9922 
 9923   format %{ "j  $lbl if $cmp == ge\t#@far_cmpULLtGe_reg_imm0_loop" %}
 9924 
 9925   ins_encode(riscv_enc_far_cmpULtGe_imm0_branch(cmp, op1, lbl));
 9926 
 9927   ins_pipe(pipe_cmpz_branch);
 9928 %}
 9929 
 9930 instruct far_cmpP_imm0_branch(cmpOpEqNe cmp, iRegP op1, immP0 zero, label lbl) %{
 9931   match(If cmp (CmpP op1 zero));
 9932   effect(USE lbl);
 9933 
 9934   ins_cost(BRANCH_COST * 2);
 9935   format %{ "far_b$cmp   $op1, zr, $lbl\t#@far_cmpP_imm0_branch" %}
 9936 
 9937   ins_encode %{
 9938     __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
 9939   %}
 9940 
 9941   ins_pipe(pipe_cmpz_branch);
 9942 %}
 9943 
 9944 instruct far_cmpP_imm0_loop(cmpOpEqNe cmp, iRegP op1, immP0 zero, label lbl) %{
 9945   match(CountedLoopEnd cmp (CmpP op1 zero));
 9946   effect(USE lbl);
 9947 
 9948   ins_cost(BRANCH_COST * 2);
 9949   format %{ "far_b$cmp   $op1, zr, $lbl\t#@far_cmpP_imm0_loop" %}
 9950 
 9951   ins_encode %{
 9952     __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
 9953   %}
 9954 
 9955   ins_pipe(pipe_cmpz_branch);
 9956 %}
 9957 
 9958 instruct far_cmpN_imm0_branch(cmpOpEqNe cmp, iRegN op1, immN0 zero, label lbl) %{
 9959   match(If cmp (CmpN op1 zero));
 9960   effect(USE lbl);
 9961 
 9962   ins_cost(BRANCH_COST * 2);
 9963 
 9964   format %{ "far_b$cmp  $op1, zr, $lbl\t#@far_cmpN_imm0_branch" %}
 9965 
 9966   ins_encode %{
 9967     __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
 9968   %}
 9969 
 9970   ins_pipe(pipe_cmpz_branch);
 9971 %}
 9972 
 9973 instruct far_cmpN_imm0_loop(cmpOpEqNe cmp, iRegN op1, immN0 zero, label lbl) %{
 9974   match(CountedLoopEnd cmp (CmpN op1 zero));
 9975   effect(USE lbl);
 9976 
 9977   ins_cost(BRANCH_COST * 2);
 9978 
 9979   format %{ "far_b$cmp  $op1, zr, $lbl\t#@far_cmpN_imm0_loop" %}
 9980 
 9981   ins_encode %{
 9982     __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
 9983   %}
 9984 
 9985   ins_pipe(pipe_cmpz_branch);
 9986 %}
 9987 
 9988 instruct far_cmpP_narrowOop_imm0_branch(cmpOpEqNe cmp, iRegN op1, immP0 zero, label lbl) %{
 9989   match(If cmp (CmpP (DecodeN op1) zero));
 9990   effect(USE lbl);
 9991 
 9992   ins_cost(BRANCH_COST * 2);
 9993   format %{ "far_b$cmp   $op1, zr, $lbl\t#@far_cmpP_narrowOop_imm0_branch" %}
 9994 
 9995   ins_encode %{
 9996     __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
 9997   %}
 9998 
 9999   ins_pipe(pipe_cmpz_branch);
10000 %}
10001 
10002 instruct far_cmpP_narrowOop_imm0_loop(cmpOpEqNe cmp, iRegN op1, immP0 zero, label lbl) %{
10003   match(CountedLoopEnd cmp (CmpP (DecodeN op1) zero));
10004   effect(USE lbl);
10005 
10006   ins_cost(BRANCH_COST * 2);
10007   format %{ "far_b$cmp   $op1, zr, $lbl\t#@far_cmpP_narrowOop_imm0_loop" %}
10008 
10009   ins_encode %{
10010     __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
10011   %}
10012 
10013   ins_pipe(pipe_cmpz_branch);
10014 %}
10015 
10016 // ============================================================================
10017 // Conditional Move Instructions
10018 instruct cmovI_cmpI(iRegINoSp dst, iRegI src, iRegI op1, iRegI op2, cmpOp cop) %{
10019   match(Set dst (CMoveI (Binary cop (CmpI op1 op2)) (Binary dst src)));
10020   ins_cost(ALU_COST + BRANCH_COST);
10021 
10022   format %{
10023     "CMove $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpI\n\t"
10024   %}
10025 
10026   ins_encode %{
10027     __ enc_cmove($cop$$cmpcode,
10028                  as_Register($op1$$reg), as_Register($op2$$reg),
10029                  as_Register($dst$$reg), as_Register($src$$reg));
10030   %}
10031 
10032   ins_pipe(pipe_class_compare);
10033 %}
10034 
10035 instruct cmovI_cmpU(iRegINoSp dst, iRegI src, iRegI op1, iRegI op2, cmpOpU cop) %{
10036   match(Set dst (CMoveI (Binary cop (CmpU op1 op2)) (Binary dst src)));
10037   ins_cost(ALU_COST + BRANCH_COST);
10038 
10039   format %{
10040     "CMove $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpU\n\t"
10041   %}
10042 
10043   ins_encode %{
10044     __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10045                  as_Register($op1$$reg), as_Register($op2$$reg),
10046                  as_Register($dst$$reg), as_Register($src$$reg));
10047   %}
10048 
10049   ins_pipe(pipe_class_compare);
10050 %}
10051 
10052 instruct cmovI_cmpL(iRegINoSp dst, iRegI src, iRegL op1, iRegL op2, cmpOp cop) %{
10053   match(Set dst (CMoveI (Binary cop (CmpL op1 op2)) (Binary dst src)));
10054   ins_cost(ALU_COST + BRANCH_COST);
10055 
10056   format %{
10057     "CMove $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpL\n\t"
10058   %}
10059 
10060   ins_encode %{
10061     __ enc_cmove($cop$$cmpcode,
10062                  as_Register($op1$$reg), as_Register($op2$$reg),
10063                  as_Register($dst$$reg), as_Register($src$$reg));
10064   %}
10065 
10066   ins_pipe(pipe_class_compare);
10067 %}
10068 
10069 instruct cmovI_cmpUL(iRegINoSp dst, iRegI src, iRegL op1, iRegL op2, cmpOpU cop) %{
10070   match(Set dst (CMoveI (Binary cop (CmpUL op1 op2)) (Binary dst src)));
10071   ins_cost(ALU_COST + BRANCH_COST);
10072 
10073   format %{
10074     "CMove $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpUL\n\t"
10075   %}
10076 
10077   ins_encode %{
10078     __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10079                  as_Register($op1$$reg), as_Register($op2$$reg),
10080                  as_Register($dst$$reg), as_Register($src$$reg));
10081   %}
10082 
10083   ins_pipe(pipe_class_compare);
10084 %}
10085 
10086 instruct cmovL_cmpL(iRegLNoSp dst, iRegL src, iRegL op1, iRegL op2, cmpOp cop) %{
10087   match(Set dst (CMoveL (Binary cop (CmpL op1 op2)) (Binary dst src)));
10088   ins_cost(ALU_COST + BRANCH_COST);
10089 
10090   format %{
10091     "CMove $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpL\n\t"
10092   %}
10093 
10094   ins_encode %{
10095     __ enc_cmove($cop$$cmpcode,
10096                  as_Register($op1$$reg), as_Register($op2$$reg),
10097                  as_Register($dst$$reg), as_Register($src$$reg));
10098   %}
10099 
10100   ins_pipe(pipe_class_compare);
10101 %}
10102 
10103 instruct cmovL_cmpUL(iRegLNoSp dst, iRegL src, iRegL op1, iRegL op2, cmpOpU cop) %{
10104   match(Set dst (CMoveL (Binary cop (CmpUL op1 op2)) (Binary dst src)));
10105   ins_cost(ALU_COST + BRANCH_COST);
10106 
10107   format %{
10108     "CMove $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpUL\n\t"
10109   %}
10110 
10111   ins_encode %{
10112     __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10113                  as_Register($op1$$reg), as_Register($op2$$reg),
10114                  as_Register($dst$$reg), as_Register($src$$reg));
10115   %}
10116 
10117   ins_pipe(pipe_class_compare);
10118 %}
10119 
10120 instruct cmovL_cmpI(iRegLNoSp dst, iRegL src, iRegI op1, iRegI op2, cmpOp cop) %{
10121   match(Set dst (CMoveL (Binary cop (CmpI op1 op2)) (Binary dst src)));
10122   ins_cost(ALU_COST + BRANCH_COST);
10123 
10124   format %{
10125     "CMove $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpI\n\t"
10126   %}
10127 
10128   ins_encode %{
10129     __ enc_cmove($cop$$cmpcode,
10130                  as_Register($op1$$reg), as_Register($op2$$reg),
10131                  as_Register($dst$$reg), as_Register($src$$reg));
10132   %}
10133 
10134   ins_pipe(pipe_class_compare);
10135 %}
10136 
10137 instruct cmovL_cmpU(iRegLNoSp dst, iRegL src, iRegI op1, iRegI op2, cmpOpU cop) %{
10138   match(Set dst (CMoveL (Binary cop (CmpU op1 op2)) (Binary dst src)));
10139   ins_cost(ALU_COST + BRANCH_COST);
10140 
10141   format %{
10142     "CMove $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpU\n\t"
10143   %}
10144 
10145   ins_encode %{
10146     __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10147                  as_Register($op1$$reg), as_Register($op2$$reg),
10148                  as_Register($dst$$reg), as_Register($src$$reg));
10149   %}
10150 
10151   ins_pipe(pipe_class_compare);
10152 %}
10153 
10154 // ============================================================================
10155 // Procedure Call/Return Instructions
10156 
10157 // Call Java Static Instruction
10158 // Note: If this code changes, the corresponding ret_addr_offset() and
10159 //       compute_padding() functions will have to be adjusted.
10160 instruct CallStaticJavaDirect(method meth)
10161 %{
10162   match(CallStaticJava);
10163 
10164   effect(USE meth);
10165 
10166   ins_cost(BRANCH_COST);
10167 
10168   format %{ "CALL,static $meth\t#@CallStaticJavaDirect" %}
10169 
10170   ins_encode(riscv_enc_java_static_call(meth),
10171              riscv_enc_call_epilog);
10172 
10173   ins_pipe(pipe_class_call);
10174   ins_alignment(4);
10175 %}
10176 
10177 // TO HERE
10178 
10179 // Call Java Dynamic Instruction
10180 // Note: If this code changes, the corresponding ret_addr_offset() and
10181 //       compute_padding() functions will have to be adjusted.
10182 instruct CallDynamicJavaDirect(method meth, rFlagsReg cr)
10183 %{
10184   match(CallDynamicJava);
10185 
10186   effect(USE meth, KILL cr);
10187 
10188   ins_cost(BRANCH_COST + ALU_COST * 6);
10189 
10190   format %{ "CALL,dynamic $meth\t#@CallDynamicJavaDirect" %}
10191 
10192   ins_encode(riscv_enc_java_dynamic_call(meth),
10193              riscv_enc_call_epilog);
10194 
10195   ins_pipe(pipe_class_call);
10196   ins_alignment(4);
10197 %}
10198 
10199 // Call Runtime Instruction
10200 
10201 instruct CallRuntimeDirect(method meth, rFlagsReg cr)
10202 %{
10203   match(CallRuntime);
10204 
10205   effect(USE meth, KILL cr);
10206 
10207   ins_cost(BRANCH_COST);
10208 
10209   format %{ "CALL, runtime $meth\t#@CallRuntimeDirect" %}
10210 
10211   ins_encode(riscv_enc_java_to_runtime(meth));
10212 
10213   ins_pipe(pipe_class_call);
10214 %}
10215 
10216 // Call Runtime Instruction
10217 
10218 instruct CallLeafDirect(method meth, rFlagsReg cr)
10219 %{
10220   match(CallLeaf);
10221 
10222   effect(USE meth, KILL cr);
10223 
10224   ins_cost(BRANCH_COST);
10225 
10226   format %{ "CALL, runtime leaf $meth\t#@CallLeafDirect" %}
10227 
10228   ins_encode(riscv_enc_java_to_runtime(meth));
10229 
10230   ins_pipe(pipe_class_call);
10231 %}
10232 
10233 // Call Runtime Instruction
10234 
10235 instruct CallLeafNoFPDirect(method meth, rFlagsReg cr)
10236 %{
10237   match(CallLeafNoFP);
10238 
10239   effect(USE meth, KILL cr);
10240 
10241   ins_cost(BRANCH_COST);
10242 
10243   format %{ "CALL, runtime leaf nofp $meth\t#@CallLeafNoFPDirect" %}
10244 
10245   ins_encode(riscv_enc_java_to_runtime(meth));
10246 
10247   ins_pipe(pipe_class_call);
10248 %}
10249 
10250 // ============================================================================
10251 // Partial Subtype Check
10252 //
10253 // superklass array for an instance of the superklass.  Set a hidden
10254 // internal cache on a hit (cache is checked with exposed code in
10255 // gen_subtype_check()).  Return zero for a hit.  The encoding
10256 // ALSO sets flags.
10257 
10258 instruct partialSubtypeCheck(iRegP_R15 result, iRegP_R14 sub, iRegP_R10 super, iRegP_R12 tmp, rFlagsReg cr)
10259 %{
10260   match(Set result (PartialSubtypeCheck sub super));
10261   effect(KILL tmp, KILL cr);
10262 
10263   ins_cost(2 * STORE_COST + 3 * LOAD_COST + 4 * ALU_COST + BRANCH_COST * 4);
10264   format %{ "partialSubtypeCheck $result, $sub, $super\t#@partialSubtypeCheck" %}
10265 
10266   ins_encode(riscv_enc_partial_subtype_check(sub, super, tmp, result));
10267 
10268   opcode(0x1); // Force zero of result reg on hit
10269 
10270   ins_pipe(pipe_class_memory);
10271 %}
10272 
10273 instruct partialSubtypeCheckVsZero(iRegP_R15 result, iRegP_R14 sub, iRegP_R10 super, iRegP_R12 tmp,
10274                                    immP0 zero, rFlagsReg cr)
10275 %{
10276   match(Set cr (CmpP (PartialSubtypeCheck sub super) zero));
10277   effect(KILL tmp, KILL result);
10278 
10279   ins_cost(2 * STORE_COST + 3 * LOAD_COST + 4 * ALU_COST + BRANCH_COST * 4);
10280   format %{ "partialSubtypeCheck $result, $sub, $super == 0\t#@partialSubtypeCheckVsZero" %}
10281 
10282   ins_encode(riscv_enc_partial_subtype_check(sub, super, tmp, result));
10283 
10284   opcode(0x0); // Don't zero result reg on hit
10285 
10286   ins_pipe(pipe_class_memory);
10287 %}
10288 
10289 instruct string_compareU(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
10290                          iRegI_R10 result, iRegP_R28 tmp1, iRegL_R29 tmp2, iRegL_R30 tmp3, rFlagsReg cr)
10291 %{
10292   predicate(!UseRVV && ((StrCompNode *)n)->encoding() == StrIntrinsicNode::UU);
10293   match(Set result (StrComp(Binary str1 cnt1)(Binary str2 cnt2)));
10294   effect(KILL tmp1, KILL tmp2, KILL tmp3, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
10295 
10296   format %{ "String Compare $str1, $cnt1, $str2, $cnt2 -> $result\t#@string_compareU" %}
10297   ins_encode %{
10298     // Count is in 8-bit bytes; non-Compact chars are 16 bits.
10299     __ string_compare($str1$$Register, $str2$$Register,
10300                       $cnt1$$Register, $cnt2$$Register, $result$$Register,
10301                       $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
10302                       StrIntrinsicNode::UU);
10303   %}
10304   ins_pipe(pipe_class_memory);
10305 %}
10306 
10307 instruct string_compareL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
10308                          iRegI_R10 result, iRegP_R28 tmp1, iRegL_R29 tmp2, iRegL_R30 tmp3, rFlagsReg cr)
10309 %{
10310   predicate(!UseRVV && ((StrCompNode *)n)->encoding() == StrIntrinsicNode::LL);
10311   match(Set result (StrComp(Binary str1 cnt1)(Binary str2 cnt2)));
10312   effect(KILL tmp1, KILL tmp2, KILL tmp3, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
10313 
10314   format %{ "String Compare $str1, $cnt1, $str2, $cnt2 -> $result\t#@string_compareL" %}
10315   ins_encode %{
10316     __ string_compare($str1$$Register, $str2$$Register,
10317                       $cnt1$$Register, $cnt2$$Register, $result$$Register,
10318                       $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
10319                       StrIntrinsicNode::LL);
10320   %}
10321   ins_pipe(pipe_class_memory);
10322 %}
10323 
10324 instruct string_compareUL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
10325                           iRegI_R10 result, iRegP_R28 tmp1, iRegL_R29 tmp2, iRegL_R30 tmp3, rFlagsReg cr)
10326 %{
10327   predicate(!UseRVV && ((StrCompNode *)n)->encoding() == StrIntrinsicNode::UL);
10328   match(Set result (StrComp(Binary str1 cnt1)(Binary str2 cnt2)));
10329   effect(KILL tmp1, KILL tmp2, KILL tmp3, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
10330 
10331   format %{"String Compare $str1, $cnt1, $str2, $cnt2 -> $result\t#@string_compareUL" %}
10332   ins_encode %{
10333     __ string_compare($str1$$Register, $str2$$Register,
10334                       $cnt1$$Register, $cnt2$$Register, $result$$Register,
10335                       $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
10336                       StrIntrinsicNode::UL);
10337   %}
10338   ins_pipe(pipe_class_memory);
10339 %}
10340 
10341 instruct string_compareLU(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
10342                           iRegI_R10 result, iRegP_R28 tmp1, iRegL_R29 tmp2, iRegL_R30 tmp3,
10343                           rFlagsReg cr)
10344 %{
10345   predicate(!UseRVV && ((StrCompNode *)n)->encoding() == StrIntrinsicNode::LU);
10346   match(Set result (StrComp(Binary str1 cnt1)(Binary str2 cnt2)));
10347   effect(KILL tmp1, KILL tmp2, KILL tmp3, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
10348 
10349   format %{ "String Compare $str1, $cnt1, $str2, $cnt2 -> $result\t#@string_compareLU" %}
10350   ins_encode %{
10351     __ string_compare($str1$$Register, $str2$$Register,
10352                       $cnt1$$Register, $cnt2$$Register, $result$$Register,
10353                       $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
10354                       StrIntrinsicNode::LU);
10355   %}
10356   ins_pipe(pipe_class_memory);
10357 %}
10358 
10359 instruct string_indexofUU(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
10360                           iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3,
10361                           iRegINoSp tmp4, iRegINoSp tmp5, iRegINoSp tmp6, rFlagsReg cr)
10362 %{
10363   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU);
10364   match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
10365   effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, TEMP_DEF result,
10366          TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, TEMP tmp6, KILL cr);
10367 
10368   format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result (UU)" %}
10369   ins_encode %{
10370     __ string_indexof($str1$$Register, $str2$$Register,
10371                       $cnt1$$Register, $cnt2$$Register,
10372                       $tmp1$$Register, $tmp2$$Register,
10373                       $tmp3$$Register, $tmp4$$Register,
10374                       $tmp5$$Register, $tmp6$$Register,
10375                       $result$$Register, StrIntrinsicNode::UU);
10376   %}
10377   ins_pipe(pipe_class_memory);
10378 %}
10379 
10380 instruct string_indexofLL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
10381                           iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3,
10382                           iRegINoSp tmp4, iRegINoSp tmp5, iRegINoSp tmp6, rFlagsReg cr)
10383 %{
10384   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL);
10385   match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
10386   effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, TEMP_DEF result,
10387          TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, TEMP tmp6, KILL cr);
10388 
10389   format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result (LL)" %}
10390   ins_encode %{
10391     __ string_indexof($str1$$Register, $str2$$Register,
10392                       $cnt1$$Register, $cnt2$$Register,
10393                       $tmp1$$Register, $tmp2$$Register,
10394                       $tmp3$$Register, $tmp4$$Register,
10395                       $tmp5$$Register, $tmp6$$Register,
10396                       $result$$Register, StrIntrinsicNode::LL);
10397   %}
10398   ins_pipe(pipe_class_memory);
10399 %}
10400 
10401 instruct string_indexofUL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
10402                           iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3,
10403                           iRegINoSp tmp4, iRegINoSp tmp5, iRegINoSp tmp6, rFlagsReg cr)
10404 %{
10405   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL);
10406   match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
10407   effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, TEMP_DEF result,
10408          TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, TEMP tmp6, KILL cr);
10409   format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result (UL)" %}
10410 
10411   ins_encode %{
10412     __ string_indexof($str1$$Register, $str2$$Register,
10413                       $cnt1$$Register, $cnt2$$Register,
10414                       $tmp1$$Register, $tmp2$$Register,
10415                       $tmp3$$Register, $tmp4$$Register,
10416                       $tmp5$$Register, $tmp6$$Register,
10417                       $result$$Register, StrIntrinsicNode::UL);
10418   %}
10419   ins_pipe(pipe_class_memory);
10420 %}
10421 
10422 instruct string_indexof_conUU(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2,
10423                               immI_le_4 int_cnt2, iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2,
10424                               iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
10425 %{
10426   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU);
10427   match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
10428   effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, TEMP_DEF result,
10429          TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
10430 
10431   format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result (UU)" %}
10432 
10433   ins_encode %{
10434     int icnt2 = (int)$int_cnt2$$constant;
10435     __ string_indexof_linearscan($str1$$Register, $str2$$Register,
10436                                  $cnt1$$Register, zr,
10437                                  $tmp1$$Register, $tmp2$$Register,
10438                                  $tmp3$$Register, $tmp4$$Register,
10439                                  icnt2, $result$$Register, StrIntrinsicNode::UU);
10440   %}
10441   ins_pipe(pipe_class_memory);
10442 %}
10443 
10444 instruct string_indexof_conLL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2,
10445                               immI_le_4 int_cnt2, iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2,
10446                               iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
10447 %{
10448   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL);
10449   match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
10450   effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, TEMP_DEF result,
10451          TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
10452 
10453   format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result (LL)" %}
10454   ins_encode %{
10455     int icnt2 = (int)$int_cnt2$$constant;
10456     __ string_indexof_linearscan($str1$$Register, $str2$$Register,
10457                                  $cnt1$$Register, zr,
10458                                  $tmp1$$Register, $tmp2$$Register,
10459                                  $tmp3$$Register, $tmp4$$Register,
10460                                  icnt2, $result$$Register, StrIntrinsicNode::LL);
10461   %}
10462   ins_pipe(pipe_class_memory);
10463 %}
10464 
10465 instruct string_indexof_conUL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2,
10466                               immI_1 int_cnt2, iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2,
10467                               iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
10468 %{
10469   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL);
10470   match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
10471   effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, TEMP_DEF result,
10472          TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
10473 
10474   format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result (UL)" %}
10475   ins_encode %{
10476     int icnt2 = (int)$int_cnt2$$constant;
10477     __ string_indexof_linearscan($str1$$Register, $str2$$Register,
10478                                  $cnt1$$Register, zr,
10479                                  $tmp1$$Register, $tmp2$$Register,
10480                                  $tmp3$$Register, $tmp4$$Register,
10481                                  icnt2, $result$$Register, StrIntrinsicNode::UL);
10482   %}
10483   ins_pipe(pipe_class_memory);
10484 %}
10485 
10486 instruct stringU_indexof_char(iRegP_R11 str1, iRegI_R12 cnt1, iRegI_R13 ch,
10487                               iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2,
10488                               iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
10489 %{
10490   match(Set result (StrIndexOfChar (Binary str1 cnt1) ch));
10491   predicate(!UseRVV && (((StrIndexOfCharNode*)n)->encoding() == StrIntrinsicNode::U));
10492   effect(USE_KILL str1, USE_KILL cnt1, USE_KILL ch, TEMP_DEF result,
10493          TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
10494 
10495   format %{ "StringUTF16 IndexOf char[] $str1,$cnt1,$ch -> $result" %}
10496   ins_encode %{
10497     __ string_indexof_char($str1$$Register, $cnt1$$Register, $ch$$Register,
10498                            $result$$Register, $tmp1$$Register, $tmp2$$Register,
10499                            $tmp3$$Register, $tmp4$$Register, false /* isU */);
10500   %}
10501   ins_pipe(pipe_class_memory);
10502 %}
10503 
10504 
10505 instruct stringL_indexof_char(iRegP_R11 str1, iRegI_R12 cnt1, iRegI_R13 ch,
10506                               iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2,
10507                               iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
10508 %{
10509   match(Set result (StrIndexOfChar (Binary str1 cnt1) ch));
10510   predicate(!UseRVV && (((StrIndexOfCharNode*)n)->encoding() == StrIntrinsicNode::L));
10511   effect(USE_KILL str1, USE_KILL cnt1, USE_KILL ch, TEMP_DEF result,
10512          TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
10513 
10514   format %{ "StringUTF16 IndexOf char[] $str1,$cnt1,$ch -> $result" %}
10515   ins_encode %{
10516     __ string_indexof_char($str1$$Register, $cnt1$$Register, $ch$$Register,
10517                            $result$$Register, $tmp1$$Register, $tmp2$$Register,
10518                            $tmp3$$Register, $tmp4$$Register, true /* isL */);
10519   %}
10520   ins_pipe(pipe_class_memory);
10521 %}
10522 
10523 // clearing of an array
10524 instruct clearArray_reg_reg(iRegL_R29 cnt, iRegP_R28 base, iRegP_R30 tmp1,
10525                             iRegP_R31 tmp2, Universe dummy)
10526 %{
10527   // temp registers must match the one used in StubGenerator::generate_zero_blocks()
10528   predicate(UseBlockZeroing || !UseRVV);
10529   match(Set dummy (ClearArray cnt base));
10530   effect(USE_KILL cnt, USE_KILL base, TEMP tmp1, TEMP tmp2);
10531 
10532   ins_cost(4 * DEFAULT_COST);
10533   format %{ "ClearArray $cnt, $base\t#@clearArray_reg_reg" %}
10534 
10535   ins_encode %{
10536     address tpc = __ zero_words($base$$Register, $cnt$$Register);
10537     if (tpc == NULL) {
10538       ciEnv::current()->record_failure("CodeCache is full");
10539       return;
10540     }
10541   %}
10542 
10543   ins_pipe(pipe_class_memory);
10544 %}
10545 
10546 instruct clearArray_imm_reg(immL cnt, iRegP_R28 base, Universe dummy, rFlagsReg cr)
10547 %{
10548   predicate(!UseRVV && (uint64_t)n->in(2)->get_long()
10549             < (uint64_t)(BlockZeroingLowLimit >> LogBytesPerWord));
10550   match(Set dummy (ClearArray cnt base));
10551   effect(USE_KILL base, KILL cr);
10552 
10553   ins_cost(4 * DEFAULT_COST);
10554   format %{ "ClearArray $cnt, $base\t#@clearArray_imm_reg" %}
10555 
10556   ins_encode %{
10557     __ zero_words($base$$Register, (uint64_t)$cnt$$constant);
10558   %}
10559 
10560   ins_pipe(pipe_class_memory);
10561 %}
10562 
10563 instruct string_equalsL(iRegP_R11 str1, iRegP_R13 str2, iRegI_R14 cnt,
10564                         iRegI_R10 result, rFlagsReg cr)
10565 %{
10566   predicate(!UseRVV && ((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::LL);
10567   match(Set result (StrEquals (Binary str1 str2) cnt));
10568   effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL cr);
10569 
10570   format %{ "String Equals $str1, $str2, $cnt -> $result\t#@string_equalsL" %}
10571   ins_encode %{
10572     // Count is in 8-bit bytes; non-Compact chars are 16 bits.
10573     __ string_equals($str1$$Register, $str2$$Register,
10574                      $result$$Register, $cnt$$Register, 1);
10575   %}
10576   ins_pipe(pipe_class_memory);
10577 %}
10578 
10579 instruct string_equalsU(iRegP_R11 str1, iRegP_R13 str2, iRegI_R14 cnt,
10580                         iRegI_R10 result, rFlagsReg cr)
10581 %{
10582   predicate(!UseRVV && ((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::UU);
10583   match(Set result (StrEquals (Binary str1 str2) cnt));
10584   effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL cr);
10585 
10586   format %{ "String Equals $str1, $str2, $cnt -> $result\t#@string_equalsU" %}
10587   ins_encode %{
10588     // Count is in 8-bit bytes; non-Compact chars are 16 bits.
10589     __ string_equals($str1$$Register, $str2$$Register,
10590                      $result$$Register, $cnt$$Register, 2);
10591   %}
10592   ins_pipe(pipe_class_memory);
10593 %}
10594 
10595 instruct array_equalsB(iRegP_R11 ary1, iRegP_R12 ary2, iRegI_R10 result,
10596                        iRegP_R13 tmp1, iRegP_R14 tmp2, iRegP_R15 tmp3,
10597                        iRegP_R16 tmp4, iRegP_R28 tmp5, rFlagsReg cr)
10598 %{
10599   predicate(!UseRVV && ((AryEqNode*)n)->encoding() == StrIntrinsicNode::LL);
10600   match(Set result (AryEq ary1 ary2));
10601   effect(USE_KILL ary1, USE_KILL ary2, TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL tmp5, KILL cr);
10602 
10603   format %{ "Array Equals $ary1, ary2 -> $result\t#@array_equalsB // KILL $tmp5" %}
10604   ins_encode %{
10605     __ arrays_equals($ary1$$Register, $ary2$$Register,
10606                      $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register,
10607                      $result$$Register, $tmp5$$Register, 1);
10608   %}
10609   ins_pipe(pipe_class_memory);
10610 %}
10611 
10612 instruct array_equalsC(iRegP_R11 ary1, iRegP_R12 ary2, iRegI_R10 result,
10613                        iRegP_R13 tmp1, iRegP_R14 tmp2, iRegP_R15 tmp3,
10614                        iRegP_R16 tmp4, iRegP_R28 tmp5, rFlagsReg cr)
10615 %{
10616   predicate(!UseRVV && ((AryEqNode*)n)->encoding() == StrIntrinsicNode::UU);
10617   match(Set result (AryEq ary1 ary2));
10618   effect(USE_KILL ary1, USE_KILL ary2, TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL tmp5, KILL cr);
10619 
10620   format %{ "Array Equals $ary1, ary2 -> $result\t#@array_equalsC // KILL $tmp5" %}
10621   ins_encode %{
10622     __ arrays_equals($ary1$$Register, $ary2$$Register,
10623                      $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register,
10624                      $result$$Register, $tmp5$$Register, 2);
10625   %}
10626   ins_pipe(pipe_class_memory);
10627 %}
10628 
10629 // ============================================================================
10630 // Safepoint Instructions
10631 
10632 instruct safePoint(iRegP poll)
10633 %{
10634   match(SafePoint poll);
10635 
10636   ins_cost(2 * LOAD_COST);
10637   format %{
10638     "lwu zr, [$poll]\t# Safepoint: poll for GC, #@safePoint"
10639   %}
10640   ins_encode %{
10641     __ read_polling_page(as_Register($poll$$reg), 0, relocInfo::poll_type);
10642   %}
10643   ins_pipe(pipe_serial); // ins_pipe(iload_reg_mem);
10644 %}
10645 
10646 // ============================================================================
10647 // This name is KNOWN by the ADLC and cannot be changed.
10648 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
10649 // for this guy.
10650 instruct tlsLoadP(javaThread_RegP dst)
10651 %{
10652   match(Set dst (ThreadLocal));
10653 
10654   ins_cost(0);
10655 
10656   format %{ " -- \t// $dst=Thread::current(), empty, #@tlsLoadP" %}
10657 
10658   size(0);
10659 
10660   ins_encode( /*empty*/ );
10661 
10662   ins_pipe(pipe_class_empty);
10663 %}
10664 
10665 // inlined locking and unlocking
10666 // using t1 as the 'flag' register to bridge the BoolNode producers and consumers
10667 instruct cmpFastLock(rFlagsReg cr, iRegP object, iRegP box, iRegPNoSp tmp1, iRegPNoSp tmp2)
10668 %{
10669   match(Set cr (FastLock object box));
10670   effect(TEMP tmp1, TEMP tmp2);
10671 
10672   ins_cost(LOAD_COST * 2 + STORE_COST * 3 + ALU_COST * 6 + BRANCH_COST * 3);
10673   format %{ "fastlock $object,$box\t! kills $tmp1,$tmp2, #@cmpFastLock" %}
10674 
10675   ins_encode(riscv_enc_fast_lock(object, box, tmp1, tmp2));
10676 
10677   ins_pipe(pipe_serial);
10678 %}
10679 
10680 // using t1 as the 'flag' register to bridge the BoolNode producers and consumers
10681 instruct cmpFastUnlock(rFlagsReg cr, iRegP object, iRegP box, iRegPNoSp tmp1, iRegPNoSp tmp2)
10682 %{
10683   match(Set cr (FastUnlock object box));
10684   effect(TEMP tmp1, TEMP tmp2);
10685 
10686   ins_cost(LOAD_COST * 2 + STORE_COST + ALU_COST * 2 + BRANCH_COST * 4);
10687   format %{ "fastunlock $object,$box\t! kills $tmp1, $tmp2, #@cmpFastUnlock" %}
10688 
10689   ins_encode(riscv_enc_fast_unlock(object, box, tmp1, tmp2));
10690 
10691   ins_pipe(pipe_serial);
10692 %}
10693 
10694 // Tail Call; Jump from runtime stub to Java code.
10695 // Also known as an 'interprocedural jump'.
10696 // Target of jump will eventually return to caller.
10697 // TailJump below removes the return address.
10698 instruct TailCalljmpInd(iRegPNoSp jump_target, inline_cache_RegP method_oop)
10699 %{
10700   match(TailCall jump_target method_oop);
10701 
10702   ins_cost(BRANCH_COST);
10703 
10704   format %{ "jalr $jump_target\t# $method_oop holds method oop, #@TailCalljmpInd." %}
10705 
10706   ins_encode(riscv_enc_tail_call(jump_target));
10707 
10708   ins_pipe(pipe_class_call);
10709 %}
10710 
10711 instruct TailjmpInd(iRegPNoSp jump_target, iRegP_R10 ex_oop)
10712 %{
10713   match(TailJump jump_target ex_oop);
10714 
10715   ins_cost(ALU_COST + BRANCH_COST);
10716 
10717   format %{ "jalr $jump_target\t# $ex_oop holds exception oop, #@TailjmpInd." %}
10718 
10719   ins_encode(riscv_enc_tail_jmp(jump_target));
10720 
10721   ins_pipe(pipe_class_call);
10722 %}
10723 
10724 // Create exception oop: created by stack-crawling runtime code.
10725 // Created exception is now available to this handler, and is setup
10726 // just prior to jumping to this handler. No code emitted.
10727 instruct CreateException(iRegP_R10 ex_oop)
10728 %{
10729   match(Set ex_oop (CreateEx));
10730 
10731   ins_cost(0);
10732   format %{ " -- \t// exception oop; no code emitted, #@CreateException" %}
10733 
10734   size(0);
10735 
10736   ins_encode( /*empty*/ );
10737 
10738   ins_pipe(pipe_class_empty);
10739 %}
10740 
10741 // Rethrow exception: The exception oop will come in the first
10742 // argument position. Then JUMP (not call) to the rethrow stub code.
10743 instruct RethrowException()
10744 %{
10745   match(Rethrow);
10746 
10747   ins_cost(BRANCH_COST);
10748 
10749   format %{ "j rethrow_stub\t#@RethrowException" %}
10750 
10751   ins_encode(riscv_enc_rethrow());
10752 
10753   ins_pipe(pipe_class_call);
10754 %}
10755 
10756 // Return Instruction
10757 // epilog node loads ret address into ra as part of frame pop
10758 instruct Ret()
10759 %{
10760   match(Return);
10761 
10762   ins_cost(BRANCH_COST);
10763   format %{ "ret\t// return register, #@Ret" %}
10764 
10765   ins_encode(riscv_enc_ret());
10766 
10767   ins_pipe(pipe_branch);
10768 %}
10769 
10770 // Die now.
10771 instruct ShouldNotReachHere() %{
10772   match(Halt);
10773 
10774   ins_cost(BRANCH_COST);
10775 
10776   format %{ "#@ShouldNotReachHere" %}
10777 
10778   ins_encode %{
10779     if (is_reachable()) {
10780       __ stop(_halt_reason);
10781     }
10782   %}
10783 
10784   ins_pipe(pipe_class_default);
10785 %}
10786 
10787 
10788 //----------PEEPHOLE RULES-----------------------------------------------------
10789 // These must follow all instruction definitions as they use the names
10790 // defined in the instructions definitions.
10791 //
10792 // peepmatch ( root_instr_name [preceding_instruction]* );
10793 //
10794 // peepconstraint %{
10795 // (instruction_number.operand_name relational_op instruction_number.operand_name
10796 //  [, ...] );
10797 // // instruction numbers are zero-based using left to right order in peepmatch
10798 //
10799 // peepreplace ( instr_name  ( [instruction_number.operand_name]* ) );
10800 // // provide an instruction_number.operand_name for each operand that appears
10801 // // in the replacement instruction's match rule
10802 //
10803 // ---------VM FLAGS---------------------------------------------------------
10804 //
10805 // All peephole optimizations can be turned off using -XX:-OptoPeephole
10806 //
10807 // Each peephole rule is given an identifying number starting with zero and
10808 // increasing by one in the order seen by the parser.  An individual peephole
10809 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
10810 // on the command-line.
10811 //
10812 // ---------CURRENT LIMITATIONS----------------------------------------------
10813 //
10814 // Only match adjacent instructions in same basic block
10815 // Only equality constraints
10816 // Only constraints between operands, not (0.dest_reg == RAX_enc)
10817 // Only one replacement instruction
10818 //
10819 //----------SMARTSPILL RULES---------------------------------------------------
10820 // These must follow all instruction definitions as they use the names
10821 // defined in the instructions definitions.
10822 
10823 // Local Variables:
10824 // mode: c++
10825 // End: