1 //
2 // Copyright (c) 2003, 2022, Oracle and/or its affiliates. All rights reserved.
3 // Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
4 // Copyright (c) 2020, 2022, Huawei Technologies Co., Ltd. All rights reserved.
5 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
6 //
7 // This code is free software; you can redistribute it and/or modify it
8 // under the terms of the GNU General Public License version 2 only, as
9 // published by the Free Software Foundation.
10 //
11 // This code is distributed in the hope that it will be useful, but WITHOUT
12 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 // version 2 for more details (a copy is included in the LICENSE file that
15 // accompanied this code).
16 //
17 // You should have received a copy of the GNU General Public License version
18 // 2 along with this work; if not, write to the Free Software Foundation,
19 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
20 //
21 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
22 // or visit www.oracle.com if you need additional information or have any
23 // questions.
24 //
25 //
26
27 // RISCV Architecture Description File
28
29 //----------REGISTER DEFINITION BLOCK------------------------------------------
30 // This information is used by the matcher and the register allocator to
31 // describe individual registers and classes of registers within the target
32 // architecture.
33
34 register %{
35 //----------Architecture Description Register Definitions----------------------
36 // General Registers
37 // "reg_def" name ( register save type, C convention save type,
38 // ideal register type, encoding );
39 // Register Save Types:
40 //
41 // NS = No-Save: The register allocator assumes that these registers
42 // can be used without saving upon entry to the method, &
43 // that they do not need to be saved at call sites.
44 //
45 // SOC = Save-On-Call: The register allocator assumes that these registers
46 // can be used without saving upon entry to the method,
47 // but that they must be saved at call sites.
48 //
49 // SOE = Save-On-Entry: The register allocator assumes that these registers
50 // must be saved before using them upon entry to the
51 // method, but they do not need to be saved at call
52 // sites.
53 //
54 // AS = Always-Save: The register allocator assumes that these registers
55 // must be saved before using them upon entry to the
56 // method, & that they must be saved at call sites.
57 //
58 // Ideal Register Type is used to determine how to save & restore a
59 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
60 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
61 //
62 // The encoding number is the actual bit-pattern placed into the opcodes.
63
64 // We must define the 64 bit int registers in two 32 bit halves, the
65 // real lower register and a virtual upper half register. upper halves
66 // are used by the register allocator but are not actually supplied as
67 // operands to memory ops.
68 //
69 // follow the C1 compiler in making registers
70 //
71 // x7, x9-x17, x27-x31 volatile (caller save)
72 // x0-x4, x8, x23 system (no save, no allocate)
73 // x5-x6 non-allocatable (so we can use them as temporary regs)
74
75 //
76 // as regards Java usage. we don't use any callee save registers
77 // because this makes it difficult to de-optimise a frame (see comment
78 // in x86 implementation of Deoptimization::unwind_callee_save_values)
79 //
80
81 // General Registers
82
83 reg_def R0 ( NS, NS, Op_RegI, 0, x0->as_VMReg() ); // zr
84 reg_def R0_H ( NS, NS, Op_RegI, 0, x0->as_VMReg()->next() );
85 reg_def R1 ( NS, SOC, Op_RegI, 1, x1->as_VMReg() ); // ra
86 reg_def R1_H ( NS, SOC, Op_RegI, 1, x1->as_VMReg()->next() );
87 reg_def R2 ( NS, SOE, Op_RegI, 2, x2->as_VMReg() ); // sp
88 reg_def R2_H ( NS, SOE, Op_RegI, 2, x2->as_VMReg()->next() );
89 reg_def R3 ( NS, NS, Op_RegI, 3, x3->as_VMReg() ); // gp
90 reg_def R3_H ( NS, NS, Op_RegI, 3, x3->as_VMReg()->next() );
91 reg_def R4 ( NS, NS, Op_RegI, 4, x4->as_VMReg() ); // tp
92 reg_def R4_H ( NS, NS, Op_RegI, 4, x4->as_VMReg()->next() );
93 reg_def R7 ( SOC, SOC, Op_RegI, 7, x7->as_VMReg() );
94 reg_def R7_H ( SOC, SOC, Op_RegI, 7, x7->as_VMReg()->next() );
95 reg_def R8 ( NS, SOE, Op_RegI, 8, x8->as_VMReg() ); // fp
96 reg_def R8_H ( NS, SOE, Op_RegI, 8, x8->as_VMReg()->next() );
97 reg_def R9 ( SOC, SOE, Op_RegI, 9, x9->as_VMReg() );
98 reg_def R9_H ( SOC, SOE, Op_RegI, 9, x9->as_VMReg()->next() );
99 reg_def R10 ( SOC, SOC, Op_RegI, 10, x10->as_VMReg() );
100 reg_def R10_H ( SOC, SOC, Op_RegI, 10, x10->as_VMReg()->next());
101 reg_def R11 ( SOC, SOC, Op_RegI, 11, x11->as_VMReg() );
102 reg_def R11_H ( SOC, SOC, Op_RegI, 11, x11->as_VMReg()->next());
103 reg_def R12 ( SOC, SOC, Op_RegI, 12, x12->as_VMReg() );
104 reg_def R12_H ( SOC, SOC, Op_RegI, 12, x12->as_VMReg()->next());
105 reg_def R13 ( SOC, SOC, Op_RegI, 13, x13->as_VMReg() );
106 reg_def R13_H ( SOC, SOC, Op_RegI, 13, x13->as_VMReg()->next());
107 reg_def R14 ( SOC, SOC, Op_RegI, 14, x14->as_VMReg() );
108 reg_def R14_H ( SOC, SOC, Op_RegI, 14, x14->as_VMReg()->next());
109 reg_def R15 ( SOC, SOC, Op_RegI, 15, x15->as_VMReg() );
110 reg_def R15_H ( SOC, SOC, Op_RegI, 15, x15->as_VMReg()->next());
111 reg_def R16 ( SOC, SOC, Op_RegI, 16, x16->as_VMReg() );
112 reg_def R16_H ( SOC, SOC, Op_RegI, 16, x16->as_VMReg()->next());
113 reg_def R17 ( SOC, SOC, Op_RegI, 17, x17->as_VMReg() );
114 reg_def R17_H ( SOC, SOC, Op_RegI, 17, x17->as_VMReg()->next());
115 reg_def R18 ( SOC, SOE, Op_RegI, 18, x18->as_VMReg() );
116 reg_def R18_H ( SOC, SOE, Op_RegI, 18, x18->as_VMReg()->next());
117 reg_def R19 ( SOC, SOE, Op_RegI, 19, x19->as_VMReg() );
118 reg_def R19_H ( SOC, SOE, Op_RegI, 19, x19->as_VMReg()->next());
119 reg_def R20 ( SOC, SOE, Op_RegI, 20, x20->as_VMReg() ); // caller esp
120 reg_def R20_H ( SOC, SOE, Op_RegI, 20, x20->as_VMReg()->next());
121 reg_def R21 ( SOC, SOE, Op_RegI, 21, x21->as_VMReg() );
122 reg_def R21_H ( SOC, SOE, Op_RegI, 21, x21->as_VMReg()->next());
123 reg_def R22 ( SOC, SOE, Op_RegI, 22, x22->as_VMReg() );
124 reg_def R22_H ( SOC, SOE, Op_RegI, 22, x22->as_VMReg()->next());
125 reg_def R23 ( NS, SOE, Op_RegI, 23, x23->as_VMReg() ); // java thread
126 reg_def R23_H ( NS, SOE, Op_RegI, 23, x23->as_VMReg()->next());
127 reg_def R24 ( SOC, SOE, Op_RegI, 24, x24->as_VMReg() );
128 reg_def R24_H ( SOC, SOE, Op_RegI, 24, x24->as_VMReg()->next());
129 reg_def R25 ( SOC, SOE, Op_RegI, 25, x25->as_VMReg() );
130 reg_def R25_H ( SOC, SOE, Op_RegI, 25, x25->as_VMReg()->next());
131 reg_def R26 ( SOC, SOE, Op_RegI, 26, x26->as_VMReg() );
132 reg_def R26_H ( SOC, SOE, Op_RegI, 26, x26->as_VMReg()->next());
133 reg_def R27 ( SOC, SOE, Op_RegI, 27, x27->as_VMReg() ); // heapbase
134 reg_def R27_H ( SOC, SOE, Op_RegI, 27, x27->as_VMReg()->next());
135 reg_def R28 ( SOC, SOC, Op_RegI, 28, x28->as_VMReg() );
136 reg_def R28_H ( SOC, SOC, Op_RegI, 28, x28->as_VMReg()->next());
137 reg_def R29 ( SOC, SOC, Op_RegI, 29, x29->as_VMReg() );
138 reg_def R29_H ( SOC, SOC, Op_RegI, 29, x29->as_VMReg()->next());
139 reg_def R30 ( SOC, SOC, Op_RegI, 30, x30->as_VMReg() );
140 reg_def R30_H ( SOC, SOC, Op_RegI, 30, x30->as_VMReg()->next());
141 reg_def R31 ( SOC, SOC, Op_RegI, 31, x31->as_VMReg() );
142 reg_def R31_H ( SOC, SOC, Op_RegI, 31, x31->as_VMReg()->next());
143
144 // ----------------------------
145 // Float/Double Registers
146 // ----------------------------
147
148 // Double Registers
149
150 // The rules of ADL require that double registers be defined in pairs.
151 // Each pair must be two 32-bit values, but not necessarily a pair of
152 // single float registers. In each pair, ADLC-assigned register numbers
153 // must be adjacent, with the lower number even. Finally, when the
154 // CPU stores such a register pair to memory, the word associated with
155 // the lower ADLC-assigned number must be stored to the lower address.
156
157 // RISCV has 32 floating-point registers. Each can store a single
158 // or double precision floating-point value.
159
160 // for Java use float registers f0-f31 are always save on call whereas
161 // the platform ABI treats f8-f9 and f18-f27 as callee save). Other
162 // float registers are SOC as per the platform spec
163
164 reg_def F0 ( SOC, SOC, Op_RegF, 0, f0->as_VMReg() );
165 reg_def F0_H ( SOC, SOC, Op_RegF, 0, f0->as_VMReg()->next() );
166 reg_def F1 ( SOC, SOC, Op_RegF, 1, f1->as_VMReg() );
167 reg_def F1_H ( SOC, SOC, Op_RegF, 1, f1->as_VMReg()->next() );
168 reg_def F2 ( SOC, SOC, Op_RegF, 2, f2->as_VMReg() );
169 reg_def F2_H ( SOC, SOC, Op_RegF, 2, f2->as_VMReg()->next() );
170 reg_def F3 ( SOC, SOC, Op_RegF, 3, f3->as_VMReg() );
171 reg_def F3_H ( SOC, SOC, Op_RegF, 3, f3->as_VMReg()->next() );
172 reg_def F4 ( SOC, SOC, Op_RegF, 4, f4->as_VMReg() );
173 reg_def F4_H ( SOC, SOC, Op_RegF, 4, f4->as_VMReg()->next() );
174 reg_def F5 ( SOC, SOC, Op_RegF, 5, f5->as_VMReg() );
175 reg_def F5_H ( SOC, SOC, Op_RegF, 5, f5->as_VMReg()->next() );
176 reg_def F6 ( SOC, SOC, Op_RegF, 6, f6->as_VMReg() );
177 reg_def F6_H ( SOC, SOC, Op_RegF, 6, f6->as_VMReg()->next() );
178 reg_def F7 ( SOC, SOC, Op_RegF, 7, f7->as_VMReg() );
179 reg_def F7_H ( SOC, SOC, Op_RegF, 7, f7->as_VMReg()->next() );
180 reg_def F8 ( SOC, SOE, Op_RegF, 8, f8->as_VMReg() );
181 reg_def F8_H ( SOC, SOE, Op_RegF, 8, f8->as_VMReg()->next() );
182 reg_def F9 ( SOC, SOE, Op_RegF, 9, f9->as_VMReg() );
183 reg_def F9_H ( SOC, SOE, Op_RegF, 9, f9->as_VMReg()->next() );
184 reg_def F10 ( SOC, SOC, Op_RegF, 10, f10->as_VMReg() );
185 reg_def F10_H ( SOC, SOC, Op_RegF, 10, f10->as_VMReg()->next() );
186 reg_def F11 ( SOC, SOC, Op_RegF, 11, f11->as_VMReg() );
187 reg_def F11_H ( SOC, SOC, Op_RegF, 11, f11->as_VMReg()->next() );
188 reg_def F12 ( SOC, SOC, Op_RegF, 12, f12->as_VMReg() );
189 reg_def F12_H ( SOC, SOC, Op_RegF, 12, f12->as_VMReg()->next() );
190 reg_def F13 ( SOC, SOC, Op_RegF, 13, f13->as_VMReg() );
191 reg_def F13_H ( SOC, SOC, Op_RegF, 13, f13->as_VMReg()->next() );
192 reg_def F14 ( SOC, SOC, Op_RegF, 14, f14->as_VMReg() );
193 reg_def F14_H ( SOC, SOC, Op_RegF, 14, f14->as_VMReg()->next() );
194 reg_def F15 ( SOC, SOC, Op_RegF, 15, f15->as_VMReg() );
195 reg_def F15_H ( SOC, SOC, Op_RegF, 15, f15->as_VMReg()->next() );
196 reg_def F16 ( SOC, SOC, Op_RegF, 16, f16->as_VMReg() );
197 reg_def F16_H ( SOC, SOC, Op_RegF, 16, f16->as_VMReg()->next() );
198 reg_def F17 ( SOC, SOC, Op_RegF, 17, f17->as_VMReg() );
199 reg_def F17_H ( SOC, SOC, Op_RegF, 17, f17->as_VMReg()->next() );
200 reg_def F18 ( SOC, SOE, Op_RegF, 18, f18->as_VMReg() );
201 reg_def F18_H ( SOC, SOE, Op_RegF, 18, f18->as_VMReg()->next() );
202 reg_def F19 ( SOC, SOE, Op_RegF, 19, f19->as_VMReg() );
203 reg_def F19_H ( SOC, SOE, Op_RegF, 19, f19->as_VMReg()->next() );
204 reg_def F20 ( SOC, SOE, Op_RegF, 20, f20->as_VMReg() );
205 reg_def F20_H ( SOC, SOE, Op_RegF, 20, f20->as_VMReg()->next() );
206 reg_def F21 ( SOC, SOE, Op_RegF, 21, f21->as_VMReg() );
207 reg_def F21_H ( SOC, SOE, Op_RegF, 21, f21->as_VMReg()->next() );
208 reg_def F22 ( SOC, SOE, Op_RegF, 22, f22->as_VMReg() );
209 reg_def F22_H ( SOC, SOE, Op_RegF, 22, f22->as_VMReg()->next() );
210 reg_def F23 ( SOC, SOE, Op_RegF, 23, f23->as_VMReg() );
211 reg_def F23_H ( SOC, SOE, Op_RegF, 23, f23->as_VMReg()->next() );
212 reg_def F24 ( SOC, SOE, Op_RegF, 24, f24->as_VMReg() );
213 reg_def F24_H ( SOC, SOE, Op_RegF, 24, f24->as_VMReg()->next() );
214 reg_def F25 ( SOC, SOE, Op_RegF, 25, f25->as_VMReg() );
215 reg_def F25_H ( SOC, SOE, Op_RegF, 25, f25->as_VMReg()->next() );
216 reg_def F26 ( SOC, SOE, Op_RegF, 26, f26->as_VMReg() );
217 reg_def F26_H ( SOC, SOE, Op_RegF, 26, f26->as_VMReg()->next() );
218 reg_def F27 ( SOC, SOE, Op_RegF, 27, f27->as_VMReg() );
219 reg_def F27_H ( SOC, SOE, Op_RegF, 27, f27->as_VMReg()->next() );
220 reg_def F28 ( SOC, SOC, Op_RegF, 28, f28->as_VMReg() );
221 reg_def F28_H ( SOC, SOC, Op_RegF, 28, f28->as_VMReg()->next() );
222 reg_def F29 ( SOC, SOC, Op_RegF, 29, f29->as_VMReg() );
223 reg_def F29_H ( SOC, SOC, Op_RegF, 29, f29->as_VMReg()->next() );
224 reg_def F30 ( SOC, SOC, Op_RegF, 30, f30->as_VMReg() );
225 reg_def F30_H ( SOC, SOC, Op_RegF, 30, f30->as_VMReg()->next() );
226 reg_def F31 ( SOC, SOC, Op_RegF, 31, f31->as_VMReg() );
227 reg_def F31_H ( SOC, SOC, Op_RegF, 31, f31->as_VMReg()->next() );
228
229 // ----------------------------
230 // Vector Registers
231 // ----------------------------
232
233 // For RVV vector registers, we simply extend vector register size to 4
234 // 'logical' slots. This is nominally 128 bits but it actually covers
235 // all possible 'physical' RVV vector register lengths from 128 ~ 1024
236 // bits. The 'physical' RVV vector register length is detected during
237 // startup, so the register allocator is able to identify the correct
238 // number of bytes needed for an RVV spill/unspill.
239
240 reg_def V0 ( SOC, SOC, Op_VecA, 0, v0->as_VMReg() );
241 reg_def V0_H ( SOC, SOC, Op_VecA, 0, v0->as_VMReg()->next() );
242 reg_def V0_J ( SOC, SOC, Op_VecA, 0, v0->as_VMReg()->next(2) );
243 reg_def V0_K ( SOC, SOC, Op_VecA, 0, v0->as_VMReg()->next(3) );
244
245 reg_def V1 ( SOC, SOC, Op_VecA, 1, v1->as_VMReg() );
246 reg_def V1_H ( SOC, SOC, Op_VecA, 1, v1->as_VMReg()->next() );
247 reg_def V1_J ( SOC, SOC, Op_VecA, 1, v1->as_VMReg()->next(2) );
248 reg_def V1_K ( SOC, SOC, Op_VecA, 1, v1->as_VMReg()->next(3) );
249
250 reg_def V2 ( SOC, SOC, Op_VecA, 2, v2->as_VMReg() );
251 reg_def V2_H ( SOC, SOC, Op_VecA, 2, v2->as_VMReg()->next() );
252 reg_def V2_J ( SOC, SOC, Op_VecA, 2, v2->as_VMReg()->next(2) );
253 reg_def V2_K ( SOC, SOC, Op_VecA, 2, v2->as_VMReg()->next(3) );
254
255 reg_def V3 ( SOC, SOC, Op_VecA, 3, v3->as_VMReg() );
256 reg_def V3_H ( SOC, SOC, Op_VecA, 3, v3->as_VMReg()->next() );
257 reg_def V3_J ( SOC, SOC, Op_VecA, 3, v3->as_VMReg()->next(2) );
258 reg_def V3_K ( SOC, SOC, Op_VecA, 3, v3->as_VMReg()->next(3) );
259
260 reg_def V4 ( SOC, SOC, Op_VecA, 4, v4->as_VMReg() );
261 reg_def V4_H ( SOC, SOC, Op_VecA, 4, v4->as_VMReg()->next() );
262 reg_def V4_J ( SOC, SOC, Op_VecA, 4, v4->as_VMReg()->next(2) );
263 reg_def V4_K ( SOC, SOC, Op_VecA, 4, v4->as_VMReg()->next(3) );
264
265 reg_def V5 ( SOC, SOC, Op_VecA, 5, v5->as_VMReg() );
266 reg_def V5_H ( SOC, SOC, Op_VecA, 5, v5->as_VMReg()->next() );
267 reg_def V5_J ( SOC, SOC, Op_VecA, 5, v5->as_VMReg()->next(2) );
268 reg_def V5_K ( SOC, SOC, Op_VecA, 5, v5->as_VMReg()->next(3) );
269
270 reg_def V6 ( SOC, SOC, Op_VecA, 6, v6->as_VMReg() );
271 reg_def V6_H ( SOC, SOC, Op_VecA, 6, v6->as_VMReg()->next() );
272 reg_def V6_J ( SOC, SOC, Op_VecA, 6, v6->as_VMReg()->next(2) );
273 reg_def V6_K ( SOC, SOC, Op_VecA, 6, v6->as_VMReg()->next(3) );
274
275 reg_def V7 ( SOC, SOC, Op_VecA, 7, v7->as_VMReg() );
276 reg_def V7_H ( SOC, SOC, Op_VecA, 7, v7->as_VMReg()->next() );
277 reg_def V7_J ( SOC, SOC, Op_VecA, 7, v7->as_VMReg()->next(2) );
278 reg_def V7_K ( SOC, SOC, Op_VecA, 7, v7->as_VMReg()->next(3) );
279
280 reg_def V8 ( SOC, SOC, Op_VecA, 8, v8->as_VMReg() );
281 reg_def V8_H ( SOC, SOC, Op_VecA, 8, v8->as_VMReg()->next() );
282 reg_def V8_J ( SOC, SOC, Op_VecA, 8, v8->as_VMReg()->next(2) );
283 reg_def V8_K ( SOC, SOC, Op_VecA, 8, v8->as_VMReg()->next(3) );
284
285 reg_def V9 ( SOC, SOC, Op_VecA, 9, v9->as_VMReg() );
286 reg_def V9_H ( SOC, SOC, Op_VecA, 9, v9->as_VMReg()->next() );
287 reg_def V9_J ( SOC, SOC, Op_VecA, 9, v9->as_VMReg()->next(2) );
288 reg_def V9_K ( SOC, SOC, Op_VecA, 9, v9->as_VMReg()->next(3) );
289
290 reg_def V10 ( SOC, SOC, Op_VecA, 10, v10->as_VMReg() );
291 reg_def V10_H ( SOC, SOC, Op_VecA, 10, v10->as_VMReg()->next() );
292 reg_def V10_J ( SOC, SOC, Op_VecA, 10, v10->as_VMReg()->next(2) );
293 reg_def V10_K ( SOC, SOC, Op_VecA, 10, v10->as_VMReg()->next(3) );
294
295 reg_def V11 ( SOC, SOC, Op_VecA, 11, v11->as_VMReg() );
296 reg_def V11_H ( SOC, SOC, Op_VecA, 11, v11->as_VMReg()->next() );
297 reg_def V11_J ( SOC, SOC, Op_VecA, 11, v11->as_VMReg()->next(2) );
298 reg_def V11_K ( SOC, SOC, Op_VecA, 11, v11->as_VMReg()->next(3) );
299
300 reg_def V12 ( SOC, SOC, Op_VecA, 12, v12->as_VMReg() );
301 reg_def V12_H ( SOC, SOC, Op_VecA, 12, v12->as_VMReg()->next() );
302 reg_def V12_J ( SOC, SOC, Op_VecA, 12, v12->as_VMReg()->next(2) );
303 reg_def V12_K ( SOC, SOC, Op_VecA, 12, v12->as_VMReg()->next(3) );
304
305 reg_def V13 ( SOC, SOC, Op_VecA, 13, v13->as_VMReg() );
306 reg_def V13_H ( SOC, SOC, Op_VecA, 13, v13->as_VMReg()->next() );
307 reg_def V13_J ( SOC, SOC, Op_VecA, 13, v13->as_VMReg()->next(2) );
308 reg_def V13_K ( SOC, SOC, Op_VecA, 13, v13->as_VMReg()->next(3) );
309
310 reg_def V14 ( SOC, SOC, Op_VecA, 14, v14->as_VMReg() );
311 reg_def V14_H ( SOC, SOC, Op_VecA, 14, v14->as_VMReg()->next() );
312 reg_def V14_J ( SOC, SOC, Op_VecA, 14, v14->as_VMReg()->next(2) );
313 reg_def V14_K ( SOC, SOC, Op_VecA, 14, v14->as_VMReg()->next(3) );
314
315 reg_def V15 ( SOC, SOC, Op_VecA, 15, v15->as_VMReg() );
316 reg_def V15_H ( SOC, SOC, Op_VecA, 15, v15->as_VMReg()->next() );
317 reg_def V15_J ( SOC, SOC, Op_VecA, 15, v15->as_VMReg()->next(2) );
318 reg_def V15_K ( SOC, SOC, Op_VecA, 15, v15->as_VMReg()->next(3) );
319
320 reg_def V16 ( SOC, SOC, Op_VecA, 16, v16->as_VMReg() );
321 reg_def V16_H ( SOC, SOC, Op_VecA, 16, v16->as_VMReg()->next() );
322 reg_def V16_J ( SOC, SOC, Op_VecA, 16, v16->as_VMReg()->next(2) );
323 reg_def V16_K ( SOC, SOC, Op_VecA, 16, v16->as_VMReg()->next(3) );
324
325 reg_def V17 ( SOC, SOC, Op_VecA, 17, v17->as_VMReg() );
326 reg_def V17_H ( SOC, SOC, Op_VecA, 17, v17->as_VMReg()->next() );
327 reg_def V17_J ( SOC, SOC, Op_VecA, 17, v17->as_VMReg()->next(2) );
328 reg_def V17_K ( SOC, SOC, Op_VecA, 17, v17->as_VMReg()->next(3) );
329
330 reg_def V18 ( SOC, SOC, Op_VecA, 18, v18->as_VMReg() );
331 reg_def V18_H ( SOC, SOC, Op_VecA, 18, v18->as_VMReg()->next() );
332 reg_def V18_J ( SOC, SOC, Op_VecA, 18, v18->as_VMReg()->next(2) );
333 reg_def V18_K ( SOC, SOC, Op_VecA, 18, v18->as_VMReg()->next(3) );
334
335 reg_def V19 ( SOC, SOC, Op_VecA, 19, v19->as_VMReg() );
336 reg_def V19_H ( SOC, SOC, Op_VecA, 19, v19->as_VMReg()->next() );
337 reg_def V19_J ( SOC, SOC, Op_VecA, 19, v19->as_VMReg()->next(2) );
338 reg_def V19_K ( SOC, SOC, Op_VecA, 19, v19->as_VMReg()->next(3) );
339
340 reg_def V20 ( SOC, SOC, Op_VecA, 20, v20->as_VMReg() );
341 reg_def V20_H ( SOC, SOC, Op_VecA, 20, v20->as_VMReg()->next() );
342 reg_def V20_J ( SOC, SOC, Op_VecA, 20, v20->as_VMReg()->next(2) );
343 reg_def V20_K ( SOC, SOC, Op_VecA, 20, v20->as_VMReg()->next(3) );
344
345 reg_def V21 ( SOC, SOC, Op_VecA, 21, v21->as_VMReg() );
346 reg_def V21_H ( SOC, SOC, Op_VecA, 21, v21->as_VMReg()->next() );
347 reg_def V21_J ( SOC, SOC, Op_VecA, 21, v21->as_VMReg()->next(2) );
348 reg_def V21_K ( SOC, SOC, Op_VecA, 21, v21->as_VMReg()->next(3) );
349
350 reg_def V22 ( SOC, SOC, Op_VecA, 22, v22->as_VMReg() );
351 reg_def V22_H ( SOC, SOC, Op_VecA, 22, v22->as_VMReg()->next() );
352 reg_def V22_J ( SOC, SOC, Op_VecA, 22, v22->as_VMReg()->next(2) );
353 reg_def V22_K ( SOC, SOC, Op_VecA, 22, v22->as_VMReg()->next(3) );
354
355 reg_def V23 ( SOC, SOC, Op_VecA, 23, v23->as_VMReg() );
356 reg_def V23_H ( SOC, SOC, Op_VecA, 23, v23->as_VMReg()->next() );
357 reg_def V23_J ( SOC, SOC, Op_VecA, 23, v23->as_VMReg()->next(2) );
358 reg_def V23_K ( SOC, SOC, Op_VecA, 23, v23->as_VMReg()->next(3) );
359
360 reg_def V24 ( SOC, SOC, Op_VecA, 24, v24->as_VMReg() );
361 reg_def V24_H ( SOC, SOC, Op_VecA, 24, v24->as_VMReg()->next() );
362 reg_def V24_J ( SOC, SOC, Op_VecA, 24, v24->as_VMReg()->next(2) );
363 reg_def V24_K ( SOC, SOC, Op_VecA, 24, v24->as_VMReg()->next(3) );
364
365 reg_def V25 ( SOC, SOC, Op_VecA, 25, v25->as_VMReg() );
366 reg_def V25_H ( SOC, SOC, Op_VecA, 25, v25->as_VMReg()->next() );
367 reg_def V25_J ( SOC, SOC, Op_VecA, 25, v25->as_VMReg()->next(2) );
368 reg_def V25_K ( SOC, SOC, Op_VecA, 25, v25->as_VMReg()->next(3) );
369
370 reg_def V26 ( SOC, SOC, Op_VecA, 26, v26->as_VMReg() );
371 reg_def V26_H ( SOC, SOC, Op_VecA, 26, v26->as_VMReg()->next() );
372 reg_def V26_J ( SOC, SOC, Op_VecA, 26, v26->as_VMReg()->next(2) );
373 reg_def V26_K ( SOC, SOC, Op_VecA, 26, v26->as_VMReg()->next(3) );
374
375 reg_def V27 ( SOC, SOC, Op_VecA, 27, v27->as_VMReg() );
376 reg_def V27_H ( SOC, SOC, Op_VecA, 27, v27->as_VMReg()->next() );
377 reg_def V27_J ( SOC, SOC, Op_VecA, 27, v27->as_VMReg()->next(2) );
378 reg_def V27_K ( SOC, SOC, Op_VecA, 27, v27->as_VMReg()->next(3) );
379
380 reg_def V28 ( SOC, SOC, Op_VecA, 28, v28->as_VMReg() );
381 reg_def V28_H ( SOC, SOC, Op_VecA, 28, v28->as_VMReg()->next() );
382 reg_def V28_J ( SOC, SOC, Op_VecA, 28, v28->as_VMReg()->next(2) );
383 reg_def V28_K ( SOC, SOC, Op_VecA, 28, v28->as_VMReg()->next(3) );
384
385 reg_def V29 ( SOC, SOC, Op_VecA, 29, v29->as_VMReg() );
386 reg_def V29_H ( SOC, SOC, Op_VecA, 29, v29->as_VMReg()->next() );
387 reg_def V29_J ( SOC, SOC, Op_VecA, 29, v29->as_VMReg()->next(2) );
388 reg_def V29_K ( SOC, SOC, Op_VecA, 29, v29->as_VMReg()->next(3) );
389
390 reg_def V30 ( SOC, SOC, Op_VecA, 30, v30->as_VMReg() );
391 reg_def V30_H ( SOC, SOC, Op_VecA, 30, v30->as_VMReg()->next() );
392 reg_def V30_J ( SOC, SOC, Op_VecA, 30, v30->as_VMReg()->next(2) );
393 reg_def V30_K ( SOC, SOC, Op_VecA, 30, v30->as_VMReg()->next(3) );
394
395 reg_def V31 ( SOC, SOC, Op_VecA, 31, v31->as_VMReg() );
396 reg_def V31_H ( SOC, SOC, Op_VecA, 31, v31->as_VMReg()->next() );
397 reg_def V31_J ( SOC, SOC, Op_VecA, 31, v31->as_VMReg()->next(2) );
398 reg_def V31_K ( SOC, SOC, Op_VecA, 31, v31->as_VMReg()->next(3) );
399
400 // ----------------------------
401 // Special Registers
402 // ----------------------------
403
404 // On riscv, the physical flag register is missing, so we use t1 instead,
405 // to bridge the RegFlag semantics in share/opto
406
407 reg_def RFLAGS (SOC, SOC, Op_RegFlags, 6, x6->as_VMReg() );
408
409 // Specify priority of register selection within phases of register
410 // allocation. Highest priority is first. A useful heuristic is to
411 // give registers a low priority when they are required by machine
412 // instructions, like EAX and EDX on I486, and choose no-save registers
413 // before save-on-call, & save-on-call before save-on-entry. Registers
414 // which participate in fixed calling sequences should come last.
415 // Registers which are used as pairs must fall on an even boundary.
416
417 alloc_class chunk0(
418 // volatiles
419 R7, R7_H,
420 R28, R28_H,
421 R29, R29_H,
422 R30, R30_H,
423 R31, R31_H,
424
425 // arg registers
426 R10, R10_H,
427 R11, R11_H,
428 R12, R12_H,
429 R13, R13_H,
430 R14, R14_H,
431 R15, R15_H,
432 R16, R16_H,
433 R17, R17_H,
434
435 // non-volatiles
436 R9, R9_H,
437 R18, R18_H,
438 R19, R19_H,
439 R20, R20_H,
440 R21, R21_H,
441 R22, R22_H,
442 R24, R24_H,
443 R25, R25_H,
444 R26, R26_H,
445
446 // non-allocatable registers
447 R23, R23_H, // java thread
448 R27, R27_H, // heapbase
449 R4, R4_H, // thread
450 R8, R8_H, // fp
451 R0, R0_H, // zero
452 R1, R1_H, // ra
453 R2, R2_H, // sp
454 R3, R3_H, // gp
455 );
456
457 alloc_class chunk1(
458
459 // no save
460 F0, F0_H,
461 F1, F1_H,
462 F2, F2_H,
463 F3, F3_H,
464 F4, F4_H,
465 F5, F5_H,
466 F6, F6_H,
467 F7, F7_H,
468 F28, F28_H,
469 F29, F29_H,
470 F30, F30_H,
471 F31, F31_H,
472
473 // arg registers
474 F10, F10_H,
475 F11, F11_H,
476 F12, F12_H,
477 F13, F13_H,
478 F14, F14_H,
479 F15, F15_H,
480 F16, F16_H,
481 F17, F17_H,
482
483 // non-volatiles
484 F8, F8_H,
485 F9, F9_H,
486 F18, F18_H,
487 F19, F19_H,
488 F20, F20_H,
489 F21, F21_H,
490 F22, F22_H,
491 F23, F23_H,
492 F24, F24_H,
493 F25, F25_H,
494 F26, F26_H,
495 F27, F27_H,
496 );
497
498 alloc_class chunk2(
499 V0, V0_H, V0_J, V0_K,
500 V1, V1_H, V1_J, V1_K,
501 V2, V2_H, V2_J, V2_K,
502 V3, V3_H, V3_J, V3_K,
503 V4, V4_H, V4_J, V4_K,
504 V5, V5_H, V5_J, V5_K,
505 V6, V6_H, V6_J, V6_K,
506 V7, V7_H, V7_J, V7_K,
507 V8, V8_H, V8_J, V8_K,
508 V9, V9_H, V9_J, V9_K,
509 V10, V10_H, V10_J, V10_K,
510 V11, V11_H, V11_J, V11_K,
511 V12, V12_H, V12_J, V12_K,
512 V13, V13_H, V13_J, V13_K,
513 V14, V14_H, V14_J, V14_K,
514 V15, V15_H, V15_J, V15_K,
515 V16, V16_H, V16_J, V16_K,
516 V17, V17_H, V17_J, V17_K,
517 V18, V18_H, V18_J, V18_K,
518 V19, V19_H, V19_J, V19_K,
519 V20, V20_H, V20_J, V20_K,
520 V21, V21_H, V21_J, V21_K,
521 V22, V22_H, V22_J, V22_K,
522 V23, V23_H, V23_J, V23_K,
523 V24, V24_H, V24_J, V24_K,
524 V25, V25_H, V25_J, V25_K,
525 V26, V26_H, V26_J, V26_K,
526 V27, V27_H, V27_J, V27_K,
527 V28, V28_H, V28_J, V28_K,
528 V29, V29_H, V29_J, V29_K,
529 V30, V30_H, V30_J, V30_K,
530 V31, V31_H, V31_J, V31_K,
531 );
532
533 alloc_class chunk3(RFLAGS);
534
535 //----------Architecture Description Register Classes--------------------------
536 // Several register classes are automatically defined based upon information in
537 // this architecture description.
538 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
539 // 2) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
540 //
541
542 // Class for all 32 bit general purpose registers
543 reg_class all_reg32(
544 R0,
545 R1,
546 R2,
547 R3,
548 R4,
549 R7,
550 R8,
551 R9,
552 R10,
553 R11,
554 R12,
555 R13,
556 R14,
557 R15,
558 R16,
559 R17,
560 R18,
561 R19,
562 R20,
563 R21,
564 R22,
565 R23,
566 R24,
567 R25,
568 R26,
569 R27,
570 R28,
571 R29,
572 R30,
573 R31
574 );
575
576 // Class for any 32 bit integer registers (excluding zr)
577 reg_class any_reg32 %{
578 return _ANY_REG32_mask;
579 %}
580
581 // Singleton class for R10 int register
582 reg_class int_r10_reg(R10);
583
584 // Singleton class for R12 int register
585 reg_class int_r12_reg(R12);
586
587 // Singleton class for R13 int register
588 reg_class int_r13_reg(R13);
589
590 // Singleton class for R14 int register
591 reg_class int_r14_reg(R14);
592
593 // Class for all long integer registers
594 reg_class all_reg(
595 R0, R0_H,
596 R1, R1_H,
597 R2, R2_H,
598 R3, R3_H,
599 R4, R4_H,
600 R7, R7_H,
601 R8, R8_H,
602 R9, R9_H,
603 R10, R10_H,
604 R11, R11_H,
605 R12, R12_H,
606 R13, R13_H,
607 R14, R14_H,
608 R15, R15_H,
609 R16, R16_H,
610 R17, R17_H,
611 R18, R18_H,
612 R19, R19_H,
613 R20, R20_H,
614 R21, R21_H,
615 R22, R22_H,
616 R23, R23_H,
617 R24, R24_H,
618 R25, R25_H,
619 R26, R26_H,
620 R27, R27_H,
621 R28, R28_H,
622 R29, R29_H,
623 R30, R30_H,
624 R31, R31_H
625 );
626
627 // Class for all long integer registers (excluding zr)
628 reg_class any_reg %{
629 return _ANY_REG_mask;
630 %}
631
632 // Class for non-allocatable 32 bit registers
633 reg_class non_allocatable_reg32(
634 R0, // zr
635 R1, // ra
636 R2, // sp
637 R3, // gp
638 R4, // tp
639 R23 // java thread
640 );
641
642 // Class for non-allocatable 64 bit registers
643 reg_class non_allocatable_reg(
644 R0, R0_H, // zr
645 R1, R1_H, // ra
646 R2, R2_H, // sp
647 R3, R3_H, // gp
648 R4, R4_H, // tp
649 R23, R23_H // java thread
650 );
651
652 reg_class no_special_reg32 %{
653 return _NO_SPECIAL_REG32_mask;
654 %}
655
656 reg_class no_special_reg %{
657 return _NO_SPECIAL_REG_mask;
658 %}
659
660 reg_class ptr_reg %{
661 return _PTR_REG_mask;
662 %}
663
664 reg_class no_special_ptr_reg %{
665 return _NO_SPECIAL_PTR_REG_mask;
666 %}
667
668 // Class for 64 bit register r10
669 reg_class r10_reg(
670 R10, R10_H
671 );
672
673 // Class for 64 bit register r11
674 reg_class r11_reg(
675 R11, R11_H
676 );
677
678 // Class for 64 bit register r12
679 reg_class r12_reg(
680 R12, R12_H
681 );
682
683 // Class for 64 bit register r13
684 reg_class r13_reg(
685 R13, R13_H
686 );
687
688 // Class for 64 bit register r14
689 reg_class r14_reg(
690 R14, R14_H
691 );
692
693 // Class for 64 bit register r15
694 reg_class r15_reg(
695 R15, R15_H
696 );
697
698 // Class for 64 bit register r16
699 reg_class r16_reg(
700 R16, R16_H
701 );
702
703 // Class for method register
704 reg_class method_reg(
705 R31, R31_H
706 );
707
708 // Class for heapbase register
709 reg_class heapbase_reg(
710 R27, R27_H
711 );
712
713 // Class for java thread register
714 reg_class java_thread_reg(
715 R23, R23_H
716 );
717
718 reg_class r28_reg(
719 R28, R28_H
720 );
721
722 reg_class r29_reg(
723 R29, R29_H
724 );
725
726 reg_class r30_reg(
727 R30, R30_H
728 );
729
730 // Class for zero registesr
731 reg_class zr_reg(
732 R0, R0_H
733 );
734
735 // Class for thread register
736 reg_class thread_reg(
737 R4, R4_H
738 );
739
740 // Class for frame pointer register
741 reg_class fp_reg(
742 R8, R8_H
743 );
744
745 // Class for link register
746 reg_class ra_reg(
747 R1, R1_H
748 );
749
750 // Class for long sp register
751 reg_class sp_reg(
752 R2, R2_H
753 );
754
755 // Class for all float registers
756 reg_class float_reg(
757 F0,
758 F1,
759 F2,
760 F3,
761 F4,
762 F5,
763 F6,
764 F7,
765 F8,
766 F9,
767 F10,
768 F11,
769 F12,
770 F13,
771 F14,
772 F15,
773 F16,
774 F17,
775 F18,
776 F19,
777 F20,
778 F21,
779 F22,
780 F23,
781 F24,
782 F25,
783 F26,
784 F27,
785 F28,
786 F29,
787 F30,
788 F31
789 );
790
791 // Double precision float registers have virtual `high halves' that
792 // are needed by the allocator.
793 // Class for all double registers
794 reg_class double_reg(
795 F0, F0_H,
796 F1, F1_H,
797 F2, F2_H,
798 F3, F3_H,
799 F4, F4_H,
800 F5, F5_H,
801 F6, F6_H,
802 F7, F7_H,
803 F8, F8_H,
804 F9, F9_H,
805 F10, F10_H,
806 F11, F11_H,
807 F12, F12_H,
808 F13, F13_H,
809 F14, F14_H,
810 F15, F15_H,
811 F16, F16_H,
812 F17, F17_H,
813 F18, F18_H,
814 F19, F19_H,
815 F20, F20_H,
816 F21, F21_H,
817 F22, F22_H,
818 F23, F23_H,
819 F24, F24_H,
820 F25, F25_H,
821 F26, F26_H,
822 F27, F27_H,
823 F28, F28_H,
824 F29, F29_H,
825 F30, F30_H,
826 F31, F31_H
827 );
828
829 // Class for all RVV vector registers
830 reg_class vectora_reg(
831 V1, V1_H, V1_J, V1_K,
832 V2, V2_H, V2_J, V2_K,
833 V3, V3_H, V3_J, V3_K,
834 V4, V4_H, V4_J, V4_K,
835 V5, V5_H, V5_J, V5_K,
836 V6, V6_H, V6_J, V6_K,
837 V7, V7_H, V7_J, V7_K,
838 V8, V8_H, V8_J, V8_K,
839 V9, V9_H, V9_J, V9_K,
840 V10, V10_H, V10_J, V10_K,
841 V11, V11_H, V11_J, V11_K,
842 V12, V12_H, V12_J, V12_K,
843 V13, V13_H, V13_J, V13_K,
844 V14, V14_H, V14_J, V14_K,
845 V15, V15_H, V15_J, V15_K,
846 V16, V16_H, V16_J, V16_K,
847 V17, V17_H, V17_J, V17_K,
848 V18, V18_H, V18_J, V18_K,
849 V19, V19_H, V19_J, V19_K,
850 V20, V20_H, V20_J, V20_K,
851 V21, V21_H, V21_J, V21_K,
852 V22, V22_H, V22_J, V22_K,
853 V23, V23_H, V23_J, V23_K,
854 V24, V24_H, V24_J, V24_K,
855 V25, V25_H, V25_J, V25_K,
856 V26, V26_H, V26_J, V26_K,
857 V27, V27_H, V27_J, V27_K,
858 V28, V28_H, V28_J, V28_K,
859 V29, V29_H, V29_J, V29_K,
860 V30, V30_H, V30_J, V30_K,
861 V31, V31_H, V31_J, V31_K
862 );
863
864 // Class for 64 bit register f0
865 reg_class f0_reg(
866 F0, F0_H
867 );
868
869 // Class for 64 bit register f1
870 reg_class f1_reg(
871 F1, F1_H
872 );
873
874 // Class for 64 bit register f2
875 reg_class f2_reg(
876 F2, F2_H
877 );
878
879 // Class for 64 bit register f3
880 reg_class f3_reg(
881 F3, F3_H
882 );
883
884 // class for vector register v1
885 reg_class v1_reg(
886 V1, V1_H, V1_J, V1_K
887 );
888
889 // class for vector register v2
890 reg_class v2_reg(
891 V2, V2_H, V2_J, V2_K
892 );
893
894 // class for vector register v3
895 reg_class v3_reg(
896 V3, V3_H, V3_J, V3_K
897 );
898
899 // class for vector register v4
900 reg_class v4_reg(
901 V4, V4_H, V4_J, V4_K
902 );
903
904 // class for vector register v5
905 reg_class v5_reg(
906 V5, V5_H, V5_J, V5_K
907 );
908
909 // class for condition codes
910 reg_class reg_flags(RFLAGS);
911 %}
912
913 //----------DEFINITION BLOCK---------------------------------------------------
914 // Define name --> value mappings to inform the ADLC of an integer valued name
915 // Current support includes integer values in the range [0, 0x7FFFFFFF]
916 // Format:
917 // int_def <name> ( <int_value>, <expression>);
918 // Generated Code in ad_<arch>.hpp
919 // #define <name> (<expression>)
920 // // value == <int_value>
921 // Generated code in ad_<arch>.cpp adlc_verification()
922 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
923 //
924
925 // we follow the ppc-aix port in using a simple cost model which ranks
926 // register operations as cheap, memory ops as more expensive and
927 // branches as most expensive. the first two have a low as well as a
928 // normal cost. huge cost appears to be a way of saying don't do
929 // something
930
931 definitions %{
932 // The default cost (of a register move instruction).
933 int_def DEFAULT_COST ( 100, 100);
934 int_def ALU_COST ( 100, 1 * DEFAULT_COST); // unknown, const, arith, shift, slt,
935 // multi, auipc, nop, logical, move
936 int_def LOAD_COST ( 300, 3 * DEFAULT_COST); // load, fpload
937 int_def STORE_COST ( 100, 1 * DEFAULT_COST); // store, fpstore
938 int_def XFER_COST ( 300, 3 * DEFAULT_COST); // mfc, mtc, fcvt, fmove, fcmp
939 int_def BRANCH_COST ( 100, 1 * DEFAULT_COST); // branch, jmp, call
940 int_def IMUL_COST ( 1000, 10 * DEFAULT_COST); // imul
941 int_def IDIVSI_COST ( 3400, 34 * DEFAULT_COST); // idivdi
942 int_def IDIVDI_COST ( 6600, 66 * DEFAULT_COST); // idivsi
943 int_def FMUL_SINGLE_COST ( 500, 5 * DEFAULT_COST); // fadd, fmul, fmadd
944 int_def FMUL_DOUBLE_COST ( 700, 7 * DEFAULT_COST); // fadd, fmul, fmadd
945 int_def FDIV_COST ( 2000, 20 * DEFAULT_COST); // fdiv
946 int_def FSQRT_COST ( 2500, 25 * DEFAULT_COST); // fsqrt
947 int_def VOLATILE_REF_COST ( 1000, 10 * DEFAULT_COST);
948 %}
949
950
951
952 //----------SOURCE BLOCK-------------------------------------------------------
953 // This is a block of C++ code which provides values, functions, and
954 // definitions necessary in the rest of the architecture description
955
956 source_hpp %{
957
958 #include "asm/macroAssembler.hpp"
959 #include "gc/shared/cardTable.hpp"
960 #include "gc/shared/cardTableBarrierSet.hpp"
961 #include "gc/shared/collectedHeap.hpp"
962 #include "opto/addnode.hpp"
963 #include "opto/convertnode.hpp"
964
965 extern RegMask _ANY_REG32_mask;
966 extern RegMask _ANY_REG_mask;
967 extern RegMask _PTR_REG_mask;
968 extern RegMask _NO_SPECIAL_REG32_mask;
969 extern RegMask _NO_SPECIAL_REG_mask;
970 extern RegMask _NO_SPECIAL_PTR_REG_mask;
971
972 class CallStubImpl {
973
974 //--------------------------------------------------------------
975 //---< Used for optimization in Compile::shorten_branches >---
976 //--------------------------------------------------------------
977
978 public:
979 // Size of call trampoline stub.
980 static uint size_call_trampoline() {
981 return 0; // no call trampolines on this platform
982 }
983
984 // number of relocations needed by a call trampoline stub
985 static uint reloc_call_trampoline() {
986 return 0; // no call trampolines on this platform
987 }
988 };
989
990 class HandlerImpl {
991
992 public:
993
994 static int emit_exception_handler(CodeBuffer &cbuf);
995 static int emit_deopt_handler(CodeBuffer& cbuf);
996
997 static uint size_exception_handler() {
998 return MacroAssembler::far_branch_size();
999 }
1000
1001 static uint size_deopt_handler() {
1002 // count auipc + far branch
1003 return NativeInstruction::instruction_size + MacroAssembler::far_branch_size();
1004 }
1005 };
1006
1007 class Node::PD {
1008 public:
1009 enum NodeFlags {
1010 _last_flag = Node::_last_flag
1011 };
1012 };
1013
1014 bool is_CAS(int opcode, bool maybe_volatile);
1015
1016 // predicate controlling translation of CompareAndSwapX
1017 bool needs_acquiring_load_reserved(const Node *load);
1018
1019 // predicate controlling addressing modes
1020 bool size_fits_all_mem_uses(AddPNode* addp, int shift);
1021 %}
1022
1023 source %{
1024
1025 // Derived RegMask with conditionally allocatable registers
1026
1027 RegMask _ANY_REG32_mask;
1028 RegMask _ANY_REG_mask;
1029 RegMask _PTR_REG_mask;
1030 RegMask _NO_SPECIAL_REG32_mask;
1031 RegMask _NO_SPECIAL_REG_mask;
1032 RegMask _NO_SPECIAL_PTR_REG_mask;
1033
1034 void reg_mask_init() {
1035
1036 _ANY_REG32_mask = _ALL_REG32_mask;
1037 _ANY_REG32_mask.Remove(OptoReg::as_OptoReg(x0->as_VMReg()));
1038
1039 _ANY_REG_mask = _ALL_REG_mask;
1040 _ANY_REG_mask.SUBTRACT(_ZR_REG_mask);
1041
1042 _PTR_REG_mask = _ALL_REG_mask;
1043 _PTR_REG_mask.SUBTRACT(_ZR_REG_mask);
1044
1045 _NO_SPECIAL_REG32_mask = _ALL_REG32_mask;
1046 _NO_SPECIAL_REG32_mask.SUBTRACT(_NON_ALLOCATABLE_REG32_mask);
1047
1048 _NO_SPECIAL_REG_mask = _ALL_REG_mask;
1049 _NO_SPECIAL_REG_mask.SUBTRACT(_NON_ALLOCATABLE_REG_mask);
1050
1051 _NO_SPECIAL_PTR_REG_mask = _ALL_REG_mask;
1052 _NO_SPECIAL_PTR_REG_mask.SUBTRACT(_NON_ALLOCATABLE_REG_mask);
1053
1054 // x27 is not allocatable when compressed oops is on
1055 if (UseCompressedOops) {
1056 _NO_SPECIAL_REG32_mask.Remove(OptoReg::as_OptoReg(x27->as_VMReg()));
1057 _NO_SPECIAL_REG_mask.SUBTRACT(_HEAPBASE_REG_mask);
1058 _NO_SPECIAL_PTR_REG_mask.SUBTRACT(_HEAPBASE_REG_mask);
1059 }
1060
1061 // x8 is not allocatable when PreserveFramePointer is on
1062 if (PreserveFramePointer) {
1063 _NO_SPECIAL_REG32_mask.Remove(OptoReg::as_OptoReg(x8->as_VMReg()));
1064 _NO_SPECIAL_REG_mask.SUBTRACT(_FP_REG_mask);
1065 _NO_SPECIAL_PTR_REG_mask.SUBTRACT(_FP_REG_mask);
1066 }
1067 }
1068
1069 void PhaseOutput::pd_perform_mach_node_analysis() {
1070 }
1071
1072 int MachNode::pd_alignment_required() const {
1073 return 1;
1074 }
1075
1076 int MachNode::compute_padding(int current_offset) const {
1077 return 0;
1078 }
1079
1080 // is_CAS(int opcode, bool maybe_volatile)
1081 //
1082 // return true if opcode is one of the possible CompareAndSwapX
1083 // values otherwise false.
1084 bool is_CAS(int opcode, bool maybe_volatile)
1085 {
1086 switch (opcode) {
1087 // We handle these
1088 case Op_CompareAndSwapI:
1089 case Op_CompareAndSwapL:
1090 case Op_CompareAndSwapP:
1091 case Op_CompareAndSwapN:
1092 case Op_ShenandoahCompareAndSwapP:
1093 case Op_ShenandoahCompareAndSwapN:
1094 case Op_CompareAndSwapB:
1095 case Op_CompareAndSwapS:
1096 case Op_GetAndSetI:
1097 case Op_GetAndSetL:
1098 case Op_GetAndSetP:
1099 case Op_GetAndSetN:
1100 case Op_GetAndAddI:
1101 case Op_GetAndAddL:
1102 return true;
1103 case Op_CompareAndExchangeI:
1104 case Op_CompareAndExchangeN:
1105 case Op_CompareAndExchangeB:
1106 case Op_CompareAndExchangeS:
1107 case Op_CompareAndExchangeL:
1108 case Op_CompareAndExchangeP:
1109 case Op_WeakCompareAndSwapB:
1110 case Op_WeakCompareAndSwapS:
1111 case Op_WeakCompareAndSwapI:
1112 case Op_WeakCompareAndSwapL:
1113 case Op_WeakCompareAndSwapP:
1114 case Op_WeakCompareAndSwapN:
1115 case Op_ShenandoahWeakCompareAndSwapP:
1116 case Op_ShenandoahWeakCompareAndSwapN:
1117 case Op_ShenandoahCompareAndExchangeP:
1118 case Op_ShenandoahCompareAndExchangeN:
1119 return maybe_volatile;
1120 default:
1121 return false;
1122 }
1123 }
1124
1125 // predicate controlling translation of CAS
1126 //
1127 // returns true if CAS needs to use an acquiring load otherwise false
1128 bool needs_acquiring_load_reserved(const Node *n)
1129 {
1130 assert(n != NULL && is_CAS(n->Opcode(), true), "expecting a compare and swap");
1131
1132 LoadStoreNode* ldst = n->as_LoadStore();
1133 if (n != NULL && is_CAS(n->Opcode(), false)) {
1134 assert(ldst != NULL && ldst->trailing_membar() != NULL, "expected trailing membar");
1135 } else {
1136 return ldst != NULL && ldst->trailing_membar() != NULL;
1137 }
1138 // so we can just return true here
1139 return true;
1140 }
1141 #define __ _masm.
1142
1143 // advance declarations for helper functions to convert register
1144 // indices to register objects
1145
1146 // the ad file has to provide implementations of certain methods
1147 // expected by the generic code
1148 //
1149 // REQUIRED FUNCTIONALITY
1150
1151 //=============================================================================
1152
1153 // !!!!! Special hack to get all types of calls to specify the byte offset
1154 // from the start of the call to the point where the return address
1155 // will point.
1156
1157 int MachCallStaticJavaNode::ret_addr_offset()
1158 {
1159 // jal
1160 return 1 * NativeInstruction::instruction_size;
1161 }
1162
1163 int MachCallDynamicJavaNode::ret_addr_offset()
1164 {
1165 return 7 * NativeInstruction::instruction_size; // movptr, jal
1166 }
1167
1168 int MachCallRuntimeNode::ret_addr_offset() {
1169 // for generated stubs the call will be
1170 // jal(addr)
1171 // or with far branches
1172 // jal(trampoline_stub)
1173 // for real runtime callouts it will be 11 instructions
1174 // see riscv_enc_java_to_runtime
1175 // la(t1, retaddr) -> auipc + addi
1176 // la(t0, RuntimeAddress(addr)) -> lui + addi + slli + addi + slli + addi
1177 // addi(sp, sp, -2 * wordSize) -> addi
1178 // sd(t1, Address(sp, wordSize)) -> sd
1179 // jalr(t0) -> jalr
1180 CodeBlob *cb = CodeCache::find_blob(_entry_point);
1181 if (cb != NULL) {
1182 return 1 * NativeInstruction::instruction_size;
1183 } else {
1184 return 11 * NativeInstruction::instruction_size;
1185 }
1186 }
1187
1188 //
1189 // Compute padding required for nodes which need alignment
1190 //
1191
1192 // With RVC a call instruction may get 2-byte aligned.
1193 // The address of the call instruction needs to be 4-byte aligned to
1194 // ensure that it does not span a cache line so that it can be patched.
1195 int CallStaticJavaDirectNode::compute_padding(int current_offset) const
1196 {
1197 // to make sure the address of jal 4-byte aligned.
1198 return align_up(current_offset, alignment_required()) - current_offset;
1199 }
1200
1201 // With RVC a call instruction may get 2-byte aligned.
1202 // The address of the call instruction needs to be 4-byte aligned to
1203 // ensure that it does not span a cache line so that it can be patched.
1204 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const
1205 {
1206 // skip the movptr in MacroAssembler::ic_call():
1207 // lui + addi + slli + addi + slli + addi
1208 // Though movptr() has already 4-byte aligned with or without RVC,
1209 // We need to prevent from further changes by explicitly calculating the size.
1210 const int movptr_size = 6 * NativeInstruction::instruction_size;
1211 current_offset += movptr_size;
1212 // to make sure the address of jal 4-byte aligned.
1213 return align_up(current_offset, alignment_required()) - current_offset;
1214 }
1215
1216 //=============================================================================
1217
1218 #ifndef PRODUCT
1219 void MachBreakpointNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1220 assert_cond(st != NULL);
1221 st->print("BREAKPOINT");
1222 }
1223 #endif
1224
1225 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1226 C2_MacroAssembler _masm(&cbuf);
1227 Assembler::CompressibleRegion cr(&_masm);
1228 __ ebreak();
1229 }
1230
1231 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
1232 return MachNode::size(ra_);
1233 }
1234
1235 //=============================================================================
1236
1237 #ifndef PRODUCT
1238 void MachNopNode::format(PhaseRegAlloc*, outputStream* st) const {
1239 st->print("nop \t# %d bytes pad for loops and calls", _count);
1240 }
1241 #endif
1242
1243 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc*) const {
1244 C2_MacroAssembler _masm(&cbuf);
1245 Assembler::CompressibleRegion cr(&_masm); // nops shall be 2-byte under RVC for alignment purposes.
1246 for (int i = 0; i < _count; i++) {
1247 __ nop();
1248 }
1249 }
1250
1251 uint MachNopNode::size(PhaseRegAlloc*) const {
1252 return _count * (UseRVC ? NativeInstruction::compressed_instruction_size : NativeInstruction::instruction_size);
1253 }
1254
1255 //=============================================================================
1256 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;
1257
1258 int ConstantTable::calculate_table_base_offset() const {
1259 return 0; // absolute addressing, no offset
1260 }
1261
1262 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
1263 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
1264 ShouldNotReachHere();
1265 }
1266
1267 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
1268 // Empty encoding
1269 }
1270
1271 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
1272 return 0;
1273 }
1274
1275 #ifndef PRODUCT
1276 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1277 assert_cond(st != NULL);
1278 st->print("-- \t// MachConstantBaseNode (empty encoding)");
1279 }
1280 #endif
1281
1282 #ifndef PRODUCT
1283 void MachPrologNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1284 assert_cond(st != NULL && ra_ != NULL);
1285 Compile* C = ra_->C;
1286
1287 int framesize = C->output()->frame_slots() << LogBytesPerInt;
1288
1289 if (C->output()->need_stack_bang(framesize)) {
1290 st->print("# stack bang size=%d\n\t", framesize);
1291 }
1292
1293 st->print("sd fp, [sp, #%d]\n\t", - 2 * wordSize);
1294 st->print("sd ra, [sp, #%d]\n\t", - wordSize);
1295 if (PreserveFramePointer) { st->print("sub fp, sp, #%d\n\t", 2 * wordSize); }
1296 st->print("sub sp, sp, #%d\n\t", framesize);
1297
1298 if (C->stub_function() == NULL && BarrierSet::barrier_set()->barrier_set_nmethod() != NULL) {
1299 st->print("ld t0, [guard]\n\t");
1300 st->print("membar LoadLoad\n\t");
1301 st->print("ld t1, [xthread, #thread_disarmed_offset]\n\t");
1302 st->print("beq t0, t1, skip\n\t");
1303 st->print("jalr #nmethod_entry_barrier_stub\n\t");
1304 st->print("j skip\n\t");
1305 st->print("guard: int\n\t");
1306 st->print("skip:\n\t");
1307 }
1308 }
1309 #endif
1310
1311 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1312 assert_cond(ra_ != NULL);
1313 Compile* C = ra_->C;
1314 C2_MacroAssembler _masm(&cbuf);
1315
1316 // n.b. frame size includes space for return pc and fp
1317 const int framesize = C->output()->frame_size_in_bytes();
1318
1319 // insert a nop at the start of the prolog so we can patch in a
1320 // branch if we need to invalidate the method later
1321 MacroAssembler::assert_alignment(__ pc());
1322 __ nop();
1323
1324 assert_cond(C != NULL);
1325
1326 if (C->clinit_barrier_on_entry()) {
1327 assert(!C->method()->holder()->is_not_initialized(), "initialization should have been started");
1328
1329 Label L_skip_barrier;
1330
1331 __ mov_metadata(t1, C->method()->holder()->constant_encoding());
1332 __ clinit_barrier(t1, t0, &L_skip_barrier);
1333 __ far_jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub()));
1334 __ bind(L_skip_barrier);
1335 }
1336
1337 int bangsize = C->output()->bang_size_in_bytes();
1338 if (C->output()->need_stack_bang(bangsize)) {
1339 __ generate_stack_overflow_check(bangsize);
1340 }
1341
1342 __ build_frame(framesize);
1343
1344 if (C->stub_function() == NULL) {
1345 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
1346 if (BarrierSet::barrier_set()->barrier_set_nmethod() != NULL) {
1347 // Dummy labels for just measuring the code size
1348 Label dummy_slow_path;
1349 Label dummy_continuation;
1350 Label dummy_guard;
1351 Label* slow_path = &dummy_slow_path;
1352 Label* continuation = &dummy_continuation;
1353 Label* guard = &dummy_guard;
1354 if (!Compile::current()->output()->in_scratch_emit_size()) {
1355 // Use real labels from actual stub when not emitting code for purpose of measuring its size
1356 C2EntryBarrierStub* stub = Compile::current()->output()->entry_barrier_table()->add_entry_barrier();
1357 slow_path = &stub->slow_path();
1358 continuation = &stub->continuation();
1359 guard = &stub->guard();
1360 }
1361 // In the C2 code, we move the non-hot part of nmethod entry barriers out-of-line to a stub.
1362 bs->nmethod_entry_barrier(&_masm, slow_path, continuation, guard);
1363 }
1364 }
1365
1366 if (VerifyStackAtCalls) {
1367 Unimplemented();
1368 }
1369
1370 C->output()->set_frame_complete(cbuf.insts_size());
1371
1372 if (C->has_mach_constant_base_node()) {
1373 // NOTE: We set the table base offset here because users might be
1374 // emitted before MachConstantBaseNode.
1375 ConstantTable& constant_table = C->output()->constant_table();
1376 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
1377 }
1378 }
1379
1380 uint MachPrologNode::size(PhaseRegAlloc* ra_) const
1381 {
1382 assert_cond(ra_ != NULL);
1383 return MachNode::size(ra_); // too many variables; just compute it
1384 // the hard way
1385 }
1386
1387 int MachPrologNode::reloc() const
1388 {
1389 return 0;
1390 }
1391
1392 //=============================================================================
1393
1394 #ifndef PRODUCT
1395 void MachEpilogNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1396 assert_cond(st != NULL && ra_ != NULL);
1397 Compile* C = ra_->C;
1398 assert_cond(C != NULL);
1399 int framesize = C->output()->frame_size_in_bytes();
1400
1401 st->print("# pop frame %d\n\t", framesize);
1402
1403 if (framesize == 0) {
1404 st->print("ld ra, [sp,#%d]\n\t", (2 * wordSize));
1405 st->print("ld fp, [sp,#%d]\n\t", (3 * wordSize));
1406 st->print("add sp, sp, #%d\n\t", (2 * wordSize));
1407 } else {
1408 st->print("add sp, sp, #%d\n\t", framesize);
1409 st->print("ld ra, [sp,#%d]\n\t", - 2 * wordSize);
1410 st->print("ld fp, [sp,#%d]\n\t", - wordSize);
1411 }
1412
1413 if (do_polling() && C->is_method_compilation()) {
1414 st->print("# test polling word\n\t");
1415 st->print("ld t0, [xthread,#%d]\n\t", in_bytes(JavaThread::polling_word_offset()));
1416 st->print("bgtu sp, t0, #slow_path");
1417 }
1418 }
1419 #endif
1420
1421 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1422 assert_cond(ra_ != NULL);
1423 Compile* C = ra_->C;
1424 C2_MacroAssembler _masm(&cbuf);
1425 assert_cond(C != NULL);
1426 int framesize = C->output()->frame_size_in_bytes();
1427
1428 __ remove_frame(framesize);
1429
1430 if (StackReservedPages > 0 && C->has_reserved_stack_access()) {
1431 __ reserved_stack_check();
1432 }
1433
1434 if (do_polling() && C->is_method_compilation()) {
1435 Label dummy_label;
1436 Label* code_stub = &dummy_label;
1437 if (!C->output()->in_scratch_emit_size()) {
1438 code_stub = &C->output()->safepoint_poll_table()->add_safepoint(__ offset());
1439 }
1440 __ relocate(relocInfo::poll_return_type);
1441 __ safepoint_poll(*code_stub, true /* at_return */, false /* acquire */, true /* in_nmethod */);
1442 }
1443 }
1444
1445 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
1446 assert_cond(ra_ != NULL);
1447 // Variable size. Determine dynamically.
1448 return MachNode::size(ra_);
1449 }
1450
1451 int MachEpilogNode::reloc() const {
1452 // Return number of relocatable values contained in this instruction.
1453 return 1; // 1 for polling page.
1454 }
1455 const Pipeline * MachEpilogNode::pipeline() const {
1456 return MachNode::pipeline_class();
1457 }
1458
1459 //=============================================================================
1460
1461 // Figure out which register class each belongs in: rc_int, rc_float or
1462 // rc_stack.
1463 enum RC { rc_bad, rc_int, rc_float, rc_vector, rc_stack };
1464
1465 static enum RC rc_class(OptoReg::Name reg) {
1466
1467 if (reg == OptoReg::Bad) {
1468 return rc_bad;
1469 }
1470
1471 // we have 30 int registers * 2 halves
1472 // (t0 and t1 are omitted)
1473 int slots_of_int_registers = Register::max_slots_per_register * (Register::number_of_registers - 2);
1474 if (reg < slots_of_int_registers) {
1475 return rc_int;
1476 }
1477
1478 // we have 32 float register * 2 halves
1479 int slots_of_float_registers = FloatRegister::max_slots_per_register * FloatRegister::number_of_registers;
1480 if (reg < slots_of_int_registers + slots_of_float_registers) {
1481 return rc_float;
1482 }
1483
1484 // we have 32 vector register * 4 halves
1485 int slots_of_vector_registers = VectorRegister::max_slots_per_register * VectorRegister::number_of_registers;
1486 if (reg < slots_of_int_registers + slots_of_float_registers + slots_of_vector_registers) {
1487 return rc_vector;
1488 }
1489
1490 // Between vector regs & stack is the flags regs.
1491 assert(OptoReg::is_stack(reg), "blow up if spilling flags");
1492
1493 return rc_stack;
1494 }
1495
1496 uint MachSpillCopyNode::implementation(CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream *st) const {
1497 assert_cond(ra_ != NULL);
1498 Compile* C = ra_->C;
1499
1500 // Get registers to move.
1501 OptoReg::Name src_hi = ra_->get_reg_second(in(1));
1502 OptoReg::Name src_lo = ra_->get_reg_first(in(1));
1503 OptoReg::Name dst_hi = ra_->get_reg_second(this);
1504 OptoReg::Name dst_lo = ra_->get_reg_first(this);
1505
1506 enum RC src_hi_rc = rc_class(src_hi);
1507 enum RC src_lo_rc = rc_class(src_lo);
1508 enum RC dst_hi_rc = rc_class(dst_hi);
1509 enum RC dst_lo_rc = rc_class(dst_lo);
1510
1511 assert(src_lo != OptoReg::Bad && dst_lo != OptoReg::Bad, "must move at least 1 register");
1512
1513 if (src_hi != OptoReg::Bad) {
1514 assert((src_lo & 1) == 0 && src_lo + 1 == src_hi &&
1515 (dst_lo & 1) == 0 && dst_lo + 1 == dst_hi,
1516 "expected aligned-adjacent pairs");
1517 }
1518
1519 if (src_lo == dst_lo && src_hi == dst_hi) {
1520 return 0; // Self copy, no move.
1521 }
1522
1523 bool is64 = (src_lo & 1) == 0 && src_lo + 1 == src_hi &&
1524 (dst_lo & 1) == 0 && dst_lo + 1 == dst_hi;
1525 int src_offset = ra_->reg2offset(src_lo);
1526 int dst_offset = ra_->reg2offset(dst_lo);
1527
1528 if (bottom_type()->isa_vect() != NULL) {
1529 uint ireg = ideal_reg();
1530 if (ireg == Op_VecA && cbuf) {
1531 C2_MacroAssembler _masm(cbuf);
1532 Assembler::CompressibleRegion cr(&_masm);
1533 int vector_reg_size_in_bytes = Matcher::scalable_vector_reg_size(T_BYTE);
1534 if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
1535 // stack to stack
1536 __ spill_copy_vector_stack_to_stack(src_offset, dst_offset,
1537 vector_reg_size_in_bytes);
1538 } else if (src_lo_rc == rc_vector && dst_lo_rc == rc_stack) {
1539 // vpr to stack
1540 __ spill(as_VectorRegister(Matcher::_regEncode[src_lo]), ra_->reg2offset(dst_lo));
1541 } else if (src_lo_rc == rc_stack && dst_lo_rc == rc_vector) {
1542 // stack to vpr
1543 __ unspill(as_VectorRegister(Matcher::_regEncode[dst_lo]), ra_->reg2offset(src_lo));
1544 } else if (src_lo_rc == rc_vector && dst_lo_rc == rc_vector) {
1545 // vpr to vpr
1546 __ vmv1r_v(as_VectorRegister(Matcher::_regEncode[dst_lo]), as_VectorRegister(Matcher::_regEncode[src_lo]));
1547 } else {
1548 ShouldNotReachHere();
1549 }
1550 }
1551 } else if (cbuf != NULL) {
1552 C2_MacroAssembler _masm(cbuf);
1553 Assembler::CompressibleRegion cr(&_masm);
1554 switch (src_lo_rc) {
1555 case rc_int:
1556 if (dst_lo_rc == rc_int) { // gpr --> gpr copy
1557 if (!is64 && this->ideal_reg() != Op_RegI) { // zero extended for narrow oop or klass
1558 __ zero_extend(as_Register(Matcher::_regEncode[dst_lo]), as_Register(Matcher::_regEncode[src_lo]), 32);
1559 } else {
1560 __ mv(as_Register(Matcher::_regEncode[dst_lo]), as_Register(Matcher::_regEncode[src_lo]));
1561 }
1562 } else if (dst_lo_rc == rc_float) { // gpr --> fpr copy
1563 if (is64) {
1564 __ fmv_d_x(as_FloatRegister(Matcher::_regEncode[dst_lo]),
1565 as_Register(Matcher::_regEncode[src_lo]));
1566 } else {
1567 __ fmv_w_x(as_FloatRegister(Matcher::_regEncode[dst_lo]),
1568 as_Register(Matcher::_regEncode[src_lo]));
1569 }
1570 } else { // gpr --> stack spill
1571 assert(dst_lo_rc == rc_stack, "spill to bad register class");
1572 __ spill(as_Register(Matcher::_regEncode[src_lo]), is64, dst_offset);
1573 }
1574 break;
1575 case rc_float:
1576 if (dst_lo_rc == rc_int) { // fpr --> gpr copy
1577 if (is64) {
1578 __ fmv_x_d(as_Register(Matcher::_regEncode[dst_lo]),
1579 as_FloatRegister(Matcher::_regEncode[src_lo]));
1580 } else {
1581 __ fmv_x_w(as_Register(Matcher::_regEncode[dst_lo]),
1582 as_FloatRegister(Matcher::_regEncode[src_lo]));
1583 }
1584 } else if (dst_lo_rc == rc_float) { // fpr --> fpr copy
1585 if (is64) {
1586 __ fmv_d(as_FloatRegister(Matcher::_regEncode[dst_lo]),
1587 as_FloatRegister(Matcher::_regEncode[src_lo]));
1588 } else {
1589 __ fmv_s(as_FloatRegister(Matcher::_regEncode[dst_lo]),
1590 as_FloatRegister(Matcher::_regEncode[src_lo]));
1591 }
1592 } else { // fpr --> stack spill
1593 assert(dst_lo_rc == rc_stack, "spill to bad register class");
1594 __ spill(as_FloatRegister(Matcher::_regEncode[src_lo]),
1595 is64, dst_offset);
1596 }
1597 break;
1598 case rc_stack:
1599 if (dst_lo_rc == rc_int) { // stack --> gpr load
1600 if (this->ideal_reg() == Op_RegI) {
1601 __ unspill(as_Register(Matcher::_regEncode[dst_lo]), is64, src_offset);
1602 } else { // // zero extended for narrow oop or klass
1603 __ unspillu(as_Register(Matcher::_regEncode[dst_lo]), is64, src_offset);
1604 }
1605 } else if (dst_lo_rc == rc_float) { // stack --> fpr load
1606 __ unspill(as_FloatRegister(Matcher::_regEncode[dst_lo]),
1607 is64, src_offset);
1608 } else { // stack --> stack copy
1609 assert(dst_lo_rc == rc_stack, "spill to bad register class");
1610 if (this->ideal_reg() == Op_RegI) {
1611 __ unspill(t0, is64, src_offset);
1612 } else { // zero extended for narrow oop or klass
1613 __ unspillu(t0, is64, src_offset);
1614 }
1615 __ spill(t0, is64, dst_offset);
1616 }
1617 break;
1618 default:
1619 ShouldNotReachHere();
1620 }
1621 }
1622
1623 if (st != NULL) {
1624 st->print("spill ");
1625 if (src_lo_rc == rc_stack) {
1626 st->print("[sp, #%d] -> ", src_offset);
1627 } else {
1628 st->print("%s -> ", Matcher::regName[src_lo]);
1629 }
1630 if (dst_lo_rc == rc_stack) {
1631 st->print("[sp, #%d]", dst_offset);
1632 } else {
1633 st->print("%s", Matcher::regName[dst_lo]);
1634 }
1635 if (bottom_type()->isa_vect() != NULL) {
1636 int vsize = 0;
1637 if (ideal_reg() == Op_VecA) {
1638 vsize = Matcher::scalable_vector_reg_size(T_BYTE) * 8;
1639 } else {
1640 ShouldNotReachHere();
1641 }
1642 st->print("\t# vector spill size = %d", vsize);
1643 } else {
1644 st->print("\t# spill size = %d", is64 ? 64 : 32);
1645 }
1646 }
1647
1648 return 0;
1649 }
1650
1651 #ifndef PRODUCT
1652 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1653 if (ra_ == NULL) {
1654 st->print("N%d = SpillCopy(N%d)", _idx, in(1)->_idx);
1655 } else {
1656 implementation(NULL, ra_, false, st);
1657 }
1658 }
1659 #endif
1660
1661 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1662 implementation(&cbuf, ra_, false, NULL);
1663 }
1664
1665 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1666 return MachNode::size(ra_);
1667 }
1668
1669 //=============================================================================
1670
1671 #ifndef PRODUCT
1672 void BoxLockNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1673 assert_cond(ra_ != NULL && st != NULL);
1674 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1675 int reg = ra_->get_reg_first(this);
1676 st->print("add %s, sp, #%d\t# box lock",
1677 Matcher::regName[reg], offset);
1678 }
1679 #endif
1680
1681 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1682 C2_MacroAssembler _masm(&cbuf);
1683
1684 assert_cond(ra_ != NULL);
1685 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1686 int reg = ra_->get_encode(this);
1687
1688 if (is_imm_in_range(offset, 12, 0)) {
1689 __ addi(as_Register(reg), sp, offset);
1690 } else if (is_imm_in_range(offset, 32, 0)) {
1691 __ li32(t0, offset);
1692 __ add(as_Register(reg), sp, t0);
1693 } else {
1694 ShouldNotReachHere();
1695 }
1696 }
1697
1698 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1699 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_).
1700 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1701
1702 if (is_imm_in_range(offset, 12, 0)) {
1703 return NativeInstruction::instruction_size;
1704 } else {
1705 return 3 * NativeInstruction::instruction_size; // lui + addiw + add;
1706 }
1707 }
1708
1709 //=============================================================================
1710
1711 #ifndef PRODUCT
1712 void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1713 {
1714 assert_cond(st != NULL);
1715 st->print_cr("# MachUEPNode");
1716 if (UseCompressedClassPointers) {
1717 st->print_cr("\tlwu t0, [j_rarg0, oopDesc::klass_offset_in_bytes()]\t# compressed klass");
1718 if (CompressedKlassPointers::shift() != 0) {
1719 st->print_cr("\tdecode_klass_not_null t0, t0");
1720 }
1721 } else {
1722 st->print_cr("\tld t0, [j_rarg0, oopDesc::klass_offset_in_bytes()]\t# compressed klass");
1723 }
1724 st->print_cr("\tbeq t0, t1, ic_hit");
1725 st->print_cr("\tj, SharedRuntime::_ic_miss_stub\t # Inline cache check");
1726 st->print_cr("\tic_hit:");
1727 }
1728 #endif
1729
1730 void MachUEPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
1731 {
1732 // This is the unverified entry point.
1733 C2_MacroAssembler _masm(&cbuf);
1734
1735 Label skip;
1736 __ cmp_klass(j_rarg0, t1, t0, skip);
1737 __ far_jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1738 __ bind(skip);
1739
1740 // These NOPs are critical so that verified entry point is properly
1741 // 4 bytes aligned for patching by NativeJump::patch_verified_entry()
1742 __ align(NativeInstruction::instruction_size);
1743 }
1744
1745 uint MachUEPNode::size(PhaseRegAlloc* ra_) const
1746 {
1747 assert_cond(ra_ != NULL);
1748 return MachNode::size(ra_);
1749 }
1750
1751 // REQUIRED EMIT CODE
1752
1753 //=============================================================================
1754
1755 // Emit exception handler code.
1756 int HandlerImpl::emit_exception_handler(CodeBuffer& cbuf)
1757 {
1758 // la_patchable t0, #exception_blob_entry_point
1759 // jr (offset)t0
1760 // or
1761 // j #exception_blob_entry_point
1762 // Note that the code buffer's insts_mark is always relative to insts.
1763 // That's why we must use the macroassembler to generate a handler.
1764 C2_MacroAssembler _masm(&cbuf);
1765 address base = __ start_a_stub(size_exception_handler());
1766 if (base == NULL) {
1767 ciEnv::current()->record_failure("CodeCache is full");
1768 return 0; // CodeBuffer::expand failed
1769 }
1770 int offset = __ offset();
1771 __ far_jump(RuntimeAddress(OptoRuntime::exception_blob()->entry_point()));
1772 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1773 __ end_a_stub();
1774 return offset;
1775 }
1776
1777 // Emit deopt handler code.
1778 int HandlerImpl::emit_deopt_handler(CodeBuffer& cbuf)
1779 {
1780 // Note that the code buffer's insts_mark is always relative to insts.
1781 // That's why we must use the macroassembler to generate a handler.
1782 C2_MacroAssembler _masm(&cbuf);
1783 address base = __ start_a_stub(size_deopt_handler());
1784 if (base == NULL) {
1785 ciEnv::current()->record_failure("CodeCache is full");
1786 return 0; // CodeBuffer::expand failed
1787 }
1788 int offset = __ offset();
1789
1790 __ auipc(ra, 0);
1791 __ far_jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
1792
1793 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1794 __ end_a_stub();
1795 return offset;
1796
1797 }
1798 // REQUIRED MATCHER CODE
1799
1800 //=============================================================================
1801
1802 const bool Matcher::match_rule_supported(int opcode) {
1803 if (!has_match_rule(opcode)) {
1804 return false;
1805 }
1806
1807 switch (opcode) {
1808 case Op_CacheWB: // fall through
1809 case Op_CacheWBPreSync: // fall through
1810 case Op_CacheWBPostSync:
1811 if (!VM_Version::supports_data_cache_line_flush()) {
1812 return false;
1813 }
1814 break;
1815
1816 case Op_StrCompressedCopy: // fall through
1817 case Op_StrInflatedCopy: // fall through
1818 case Op_CountPositives:
1819 return UseRVV;
1820
1821 case Op_EncodeISOArray:
1822 return UseRVV && SpecialEncodeISOArray;
1823
1824 case Op_PopCountI:
1825 case Op_PopCountL:
1826 return UsePopCountInstruction;
1827
1828 case Op_RotateRight:
1829 case Op_RotateLeft:
1830 case Op_CountLeadingZerosI:
1831 case Op_CountLeadingZerosL:
1832 case Op_CountTrailingZerosI:
1833 case Op_CountTrailingZerosL:
1834 return UseZbb;
1835 }
1836
1837 return true; // Per default match rules are supported.
1838 }
1839
1840 const bool Matcher::match_rule_supported_superword(int opcode, int vlen, BasicType bt) {
1841 return match_rule_supported_vector(opcode, vlen, bt);
1842 }
1843
1844 // Identify extra cases that we might want to provide match rules for vector nodes and
1845 // other intrinsics guarded with vector length (vlen) and element type (bt).
1846 const bool Matcher::match_rule_supported_vector(int opcode, int vlen, BasicType bt) {
1847 if (!match_rule_supported(opcode) || !vector_size_supported(bt, vlen)) {
1848 return false;
1849 }
1850
1851 return op_vec_supported(opcode);
1852 }
1853
1854 const bool Matcher::match_rule_supported_vector_masked(int opcode, int vlen, BasicType bt) {
1855 return false;
1856 }
1857
1858 const bool Matcher::vector_needs_partial_operations(Node* node, const TypeVect* vt) {
1859 return false;
1860 }
1861
1862 const RegMask* Matcher::predicate_reg_mask(void) {
1863 return NULL;
1864 }
1865
1866 const TypeVectMask* Matcher::predicate_reg_type(const Type* elemTy, int length) {
1867 return NULL;
1868 }
1869
1870 // Vector calling convention not yet implemented.
1871 const bool Matcher::supports_vector_calling_convention(void) {
1872 return false;
1873 }
1874
1875 OptoRegPair Matcher::vector_return_value(uint ideal_reg) {
1876 Unimplemented();
1877 return OptoRegPair(0, 0);
1878 }
1879
1880 // Is this branch offset short enough that a short branch can be used?
1881 //
1882 // NOTE: If the platform does not provide any short branch variants, then
1883 // this method should return false for offset 0.
1884 // |---label(L1)-----|
1885 // |-----------------|
1886 // |-----------------|----------eq: float-------------------
1887 // |-----------------| // far_cmpD_branch | cmpD_branch
1888 // |------- ---------| feq; | feq;
1889 // |-far_cmpD_branch-| beqz done; | bnez L;
1890 // |-----------------| j L; |
1891 // |-----------------| bind(done); |
1892 // |-----------------|--------------------------------------
1893 // |-----------------| // so shortBrSize = br_size - 4;
1894 // |-----------------| // so offs = offset - shortBrSize + 4;
1895 // |---label(L2)-----|
1896 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1897 // The passed offset is relative to address of the branch.
1898 int shortBrSize = br_size - 4;
1899 int offs = offset - shortBrSize + 4;
1900 return (-4096 <= offs && offs < 4096);
1901 }
1902
1903 // Vector width in bytes.
1904 const int Matcher::vector_width_in_bytes(BasicType bt) {
1905 if (UseRVV) {
1906 // The MaxVectorSize should have been set by detecting RVV max vector register size when check UseRVV.
1907 // MaxVectorSize == VM_Version::_initial_vector_length
1908 return MaxVectorSize;
1909 }
1910 return 0;
1911 }
1912
1913 // Limits on vector size (number of elements) loaded into vector.
1914 const int Matcher::max_vector_size(const BasicType bt) {
1915 return vector_width_in_bytes(bt) / type2aelembytes(bt);
1916 }
1917 const int Matcher::min_vector_size(const BasicType bt) {
1918 return max_vector_size(bt);
1919 }
1920
1921 // Vector ideal reg.
1922 const uint Matcher::vector_ideal_reg(int len) {
1923 assert(MaxVectorSize >= len, "");
1924 if (UseRVV) {
1925 return Op_VecA;
1926 }
1927
1928 ShouldNotReachHere();
1929 return 0;
1930 }
1931
1932 const int Matcher::scalable_vector_reg_size(const BasicType bt) {
1933 return Matcher::max_vector_size(bt);
1934 }
1935
1936 MachOper* Matcher::pd_specialize_generic_vector_operand(MachOper* original_opnd, uint ideal_reg, bool is_temp) {
1937 ShouldNotReachHere(); // generic vector operands not supported
1938 return NULL;
1939 }
1940
1941 bool Matcher::is_reg2reg_move(MachNode* m) {
1942 ShouldNotReachHere(); // generic vector operands not supported
1943 return false;
1944 }
1945
1946 bool Matcher::is_generic_vector(MachOper* opnd) {
1947 ShouldNotReachHere(); // generic vector operands not supported
1948 return false;
1949 }
1950
1951 // Return whether or not this register is ever used as an argument.
1952 // This function is used on startup to build the trampoline stubs in
1953 // generateOptoStub. Registers not mentioned will be killed by the VM
1954 // call in the trampoline, and arguments in those registers not be
1955 // available to the callee.
1956 bool Matcher::can_be_java_arg(int reg)
1957 {
1958 return
1959 reg == R10_num || reg == R10_H_num ||
1960 reg == R11_num || reg == R11_H_num ||
1961 reg == R12_num || reg == R12_H_num ||
1962 reg == R13_num || reg == R13_H_num ||
1963 reg == R14_num || reg == R14_H_num ||
1964 reg == R15_num || reg == R15_H_num ||
1965 reg == R16_num || reg == R16_H_num ||
1966 reg == R17_num || reg == R17_H_num ||
1967 reg == F10_num || reg == F10_H_num ||
1968 reg == F11_num || reg == F11_H_num ||
1969 reg == F12_num || reg == F12_H_num ||
1970 reg == F13_num || reg == F13_H_num ||
1971 reg == F14_num || reg == F14_H_num ||
1972 reg == F15_num || reg == F15_H_num ||
1973 reg == F16_num || reg == F16_H_num ||
1974 reg == F17_num || reg == F17_H_num;
1975 }
1976
1977 bool Matcher::is_spillable_arg(int reg)
1978 {
1979 return can_be_java_arg(reg);
1980 }
1981
1982 uint Matcher::int_pressure_limit()
1983 {
1984 // A derived pointer is live at CallNode and then is flagged by RA
1985 // as a spilled LRG. Spilling heuristics(Spill-USE) explicitly skip
1986 // derived pointers and lastly fail to spill after reaching maximum
1987 // number of iterations. Lowering the default pressure threshold to
1988 // (_NO_SPECIAL_REG32_mask.Size() minus 1) forces CallNode to become
1989 // a high register pressure area of the code so that split_DEF can
1990 // generate DefinitionSpillCopy for the derived pointer.
1991 uint default_int_pressure_threshold = _NO_SPECIAL_REG32_mask.Size() - 1;
1992 if (!PreserveFramePointer) {
1993 // When PreserveFramePointer is off, frame pointer is allocatable,
1994 // but different from other SOC registers, it is excluded from
1995 // fatproj's mask because its save type is No-Save. Decrease 1 to
1996 // ensure high pressure at fatproj when PreserveFramePointer is off.
1997 // See check_pressure_at_fatproj().
1998 default_int_pressure_threshold--;
1999 }
2000 return (INTPRESSURE == -1) ? default_int_pressure_threshold : INTPRESSURE;
2001 }
2002
2003 uint Matcher::float_pressure_limit()
2004 {
2005 // _FLOAT_REG_mask is generated by adlc from the float_reg register class.
2006 return (FLOATPRESSURE == -1) ? _FLOAT_REG_mask.Size() : FLOATPRESSURE;
2007 }
2008
2009 bool Matcher::use_asm_for_ldiv_by_con(jlong divisor) {
2010 return false;
2011 }
2012
2013 RegMask Matcher::divI_proj_mask() {
2014 ShouldNotReachHere();
2015 return RegMask();
2016 }
2017
2018 // Register for MODI projection of divmodI.
2019 RegMask Matcher::modI_proj_mask() {
2020 ShouldNotReachHere();
2021 return RegMask();
2022 }
2023
2024 // Register for DIVL projection of divmodL.
2025 RegMask Matcher::divL_proj_mask() {
2026 ShouldNotReachHere();
2027 return RegMask();
2028 }
2029
2030 // Register for MODL projection of divmodL.
2031 RegMask Matcher::modL_proj_mask() {
2032 ShouldNotReachHere();
2033 return RegMask();
2034 }
2035
2036 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
2037 return FP_REG_mask();
2038 }
2039
2040 bool size_fits_all_mem_uses(AddPNode* addp, int shift) {
2041 assert_cond(addp != NULL);
2042 for (DUIterator_Fast imax, i = addp->fast_outs(imax); i < imax; i++) {
2043 Node* u = addp->fast_out(i);
2044 if (u != NULL && u->is_Mem()) {
2045 int opsize = u->as_Mem()->memory_size();
2046 assert(opsize > 0, "unexpected memory operand size");
2047 if (u->as_Mem()->memory_size() != (1 << shift)) {
2048 return false;
2049 }
2050 }
2051 }
2052 return true;
2053 }
2054
2055 // Should the Matcher clone input 'm' of node 'n'?
2056 bool Matcher::pd_clone_node(Node* n, Node* m, Matcher::MStack& mstack) {
2057 assert_cond(m != NULL);
2058 if (is_vshift_con_pattern(n, m)) { // ShiftV src (ShiftCntV con)
2059 mstack.push(m, Visit); // m = ShiftCntV
2060 return true;
2061 }
2062 return false;
2063 }
2064
2065 // Should the Matcher clone shifts on addressing modes, expecting them
2066 // to be subsumed into complex addressing expressions or compute them
2067 // into registers?
2068 bool Matcher::pd_clone_address_expressions(AddPNode* m, Matcher::MStack& mstack, VectorSet& address_visited) {
2069 return clone_base_plus_offset_address(m, mstack, address_visited);
2070 }
2071
2072 %}
2073
2074
2075
2076 //----------ENCODING BLOCK-----------------------------------------------------
2077 // This block specifies the encoding classes used by the compiler to
2078 // output byte streams. Encoding classes are parameterized macros
2079 // used by Machine Instruction Nodes in order to generate the bit
2080 // encoding of the instruction. Operands specify their base encoding
2081 // interface with the interface keyword. There are currently
2082 // supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, &
2083 // COND_INTER. REG_INTER causes an operand to generate a function
2084 // which returns its register number when queried. CONST_INTER causes
2085 // an operand to generate a function which returns the value of the
2086 // constant when queried. MEMORY_INTER causes an operand to generate
2087 // four functions which return the Base Register, the Index Register,
2088 // the Scale Value, and the Offset Value of the operand when queried.
2089 // COND_INTER causes an operand to generate six functions which return
2090 // the encoding code (ie - encoding bits for the instruction)
2091 // associated with each basic boolean condition for a conditional
2092 // instruction.
2093 //
2094 // Instructions specify two basic values for encoding. Again, a
2095 // function is available to check if the constant displacement is an
2096 // oop. They use the ins_encode keyword to specify their encoding
2097 // classes (which must be a sequence of enc_class names, and their
2098 // parameters, specified in the encoding block), and they use the
2099 // opcode keyword to specify, in order, their primary, secondary, and
2100 // tertiary opcode. Only the opcode sections which a particular
2101 // instruction needs for encoding need to be specified.
2102 encode %{
2103 // BEGIN Non-volatile memory access
2104
2105 enc_class riscv_enc_li_imm(iRegIorL dst, immIorL src) %{
2106 C2_MacroAssembler _masm(&cbuf);
2107 Assembler::CompressibleRegion cr(&_masm);
2108 int64_t con = (int64_t)$src$$constant;
2109 Register dst_reg = as_Register($dst$$reg);
2110 __ mv(dst_reg, con);
2111 %}
2112
2113 enc_class riscv_enc_mov_p(iRegP dst, immP src) %{
2114 C2_MacroAssembler _masm(&cbuf);
2115 Register dst_reg = as_Register($dst$$reg);
2116 address con = (address)$src$$constant;
2117 if (con == NULL || con == (address)1) {
2118 ShouldNotReachHere();
2119 } else {
2120 relocInfo::relocType rtype = $src->constant_reloc();
2121 if (rtype == relocInfo::oop_type) {
2122 __ movoop(dst_reg, (jobject)con);
2123 } else if (rtype == relocInfo::metadata_type) {
2124 __ mov_metadata(dst_reg, (Metadata*)con);
2125 } else {
2126 assert(rtype == relocInfo::none, "unexpected reloc type");
2127 __ mv(dst_reg, $src$$constant);
2128 }
2129 }
2130 %}
2131
2132 enc_class riscv_enc_mov_p1(iRegP dst) %{
2133 C2_MacroAssembler _masm(&cbuf);
2134 Assembler::CompressibleRegion cr(&_masm);
2135 Register dst_reg = as_Register($dst$$reg);
2136 __ mv(dst_reg, 1);
2137 %}
2138
2139 enc_class riscv_enc_mov_byte_map_base(iRegP dst) %{
2140 C2_MacroAssembler _masm(&cbuf);
2141 __ load_byte_map_base($dst$$Register);
2142 %}
2143
2144 enc_class riscv_enc_mov_n(iRegN dst, immN src) %{
2145 C2_MacroAssembler _masm(&cbuf);
2146 Register dst_reg = as_Register($dst$$reg);
2147 address con = (address)$src$$constant;
2148 if (con == NULL) {
2149 ShouldNotReachHere();
2150 } else {
2151 relocInfo::relocType rtype = $src->constant_reloc();
2152 assert(rtype == relocInfo::oop_type, "unexpected reloc type");
2153 __ set_narrow_oop(dst_reg, (jobject)con);
2154 }
2155 %}
2156
2157 enc_class riscv_enc_mov_zero(iRegNorP dst) %{
2158 C2_MacroAssembler _masm(&cbuf);
2159 Register dst_reg = as_Register($dst$$reg);
2160 __ mv(dst_reg, zr);
2161 %}
2162
2163 enc_class riscv_enc_mov_nk(iRegN dst, immNKlass src) %{
2164 C2_MacroAssembler _masm(&cbuf);
2165 Register dst_reg = as_Register($dst$$reg);
2166 address con = (address)$src$$constant;
2167 if (con == NULL) {
2168 ShouldNotReachHere();
2169 } else {
2170 relocInfo::relocType rtype = $src->constant_reloc();
2171 assert(rtype == relocInfo::metadata_type, "unexpected reloc type");
2172 __ set_narrow_klass(dst_reg, (Klass *)con);
2173 }
2174 %}
2175
2176 enc_class riscv_enc_cmpxchgw(iRegINoSp res, memory mem, iRegI oldval, iRegI newval) %{
2177 C2_MacroAssembler _masm(&cbuf);
2178 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
2179 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
2180 /*result as bool*/ true);
2181 %}
2182
2183 enc_class riscv_enc_cmpxchgn(iRegINoSp res, memory mem, iRegI oldval, iRegI newval) %{
2184 C2_MacroAssembler _masm(&cbuf);
2185 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
2186 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
2187 /*result as bool*/ true);
2188 %}
2189
2190 enc_class riscv_enc_cmpxchg(iRegINoSp res, memory mem, iRegL oldval, iRegL newval) %{
2191 C2_MacroAssembler _masm(&cbuf);
2192 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
2193 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
2194 /*result as bool*/ true);
2195 %}
2196
2197 enc_class riscv_enc_cmpxchgw_acq(iRegINoSp res, memory mem, iRegI oldval, iRegI newval) %{
2198 C2_MacroAssembler _masm(&cbuf);
2199 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
2200 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
2201 /*result as bool*/ true);
2202 %}
2203
2204 enc_class riscv_enc_cmpxchgn_acq(iRegINoSp res, memory mem, iRegI oldval, iRegI newval) %{
2205 C2_MacroAssembler _masm(&cbuf);
2206 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
2207 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
2208 /*result as bool*/ true);
2209 %}
2210
2211 enc_class riscv_enc_cmpxchg_acq(iRegINoSp res, memory mem, iRegL oldval, iRegL newval) %{
2212 C2_MacroAssembler _masm(&cbuf);
2213 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
2214 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
2215 /*result as bool*/ true);
2216 %}
2217
2218 // compare and branch instruction encodings
2219
2220 enc_class riscv_enc_j(label lbl) %{
2221 C2_MacroAssembler _masm(&cbuf);
2222 Label* L = $lbl$$label;
2223 __ j(*L);
2224 %}
2225
2226 enc_class riscv_enc_far_cmpULtGe_imm0_branch(cmpOpULtGe cmp, iRegIorL op1, label lbl) %{
2227 C2_MacroAssembler _masm(&cbuf);
2228 Label* L = $lbl$$label;
2229 switch ($cmp$$cmpcode) {
2230 case(BoolTest::ge):
2231 __ j(*L);
2232 break;
2233 case(BoolTest::lt):
2234 break;
2235 default:
2236 Unimplemented();
2237 }
2238 %}
2239
2240 // call instruction encodings
2241
2242 enc_class riscv_enc_partial_subtype_check(iRegP sub, iRegP super, iRegP temp, iRegP result) %{
2243 Register sub_reg = as_Register($sub$$reg);
2244 Register super_reg = as_Register($super$$reg);
2245 Register temp_reg = as_Register($temp$$reg);
2246 Register result_reg = as_Register($result$$reg);
2247 Register cr_reg = t1;
2248
2249 Label miss;
2250 Label done;
2251 C2_MacroAssembler _masm(&cbuf);
2252 __ check_klass_subtype_slow_path(sub_reg, super_reg, temp_reg, result_reg,
2253 NULL, &miss);
2254 if ($primary) {
2255 __ mv(result_reg, zr);
2256 } else {
2257 __ mv(cr_reg, zr);
2258 __ j(done);
2259 }
2260
2261 __ bind(miss);
2262 if (!$primary) {
2263 __ mv(cr_reg, 1);
2264 }
2265
2266 __ bind(done);
2267 %}
2268
2269 enc_class riscv_enc_java_static_call(method meth) %{
2270 C2_MacroAssembler _masm(&cbuf);
2271
2272 address addr = (address)$meth$$method;
2273 address call = NULL;
2274 assert_cond(addr != NULL);
2275 if (!_method) {
2276 // A call to a runtime wrapper, e.g. new, new_typeArray_Java, uncommon_trap.
2277 call = __ trampoline_call(Address(addr, relocInfo::runtime_call_type));
2278 if (call == NULL) {
2279 ciEnv::current()->record_failure("CodeCache is full");
2280 return;
2281 }
2282 } else {
2283 int method_index = resolved_method_index(cbuf);
2284 RelocationHolder rspec = _optimized_virtual ? opt_virtual_call_Relocation::spec(method_index)
2285 : static_call_Relocation::spec(method_index);
2286 call = __ trampoline_call(Address(addr, rspec));
2287 if (call == NULL) {
2288 ciEnv::current()->record_failure("CodeCache is full");
2289 return;
2290 }
2291
2292 if (CodeBuffer::supports_shared_stubs() && _method->can_be_statically_bound()) {
2293 // Calls of the same statically bound method can share
2294 // a stub to the interpreter.
2295 cbuf.shared_stub_to_interp_for(_method, call - cbuf.insts_begin());
2296 } else {
2297 // Emit stub for static call
2298 address stub = CompiledStaticCall::emit_to_interp_stub(cbuf, call);
2299 if (stub == NULL) {
2300 ciEnv::current()->record_failure("CodeCache is full");
2301 return;
2302 }
2303 }
2304 }
2305 %}
2306
2307 enc_class riscv_enc_java_dynamic_call(method meth) %{
2308 C2_MacroAssembler _masm(&cbuf);
2309 int method_index = resolved_method_index(cbuf);
2310 address call = __ ic_call((address)$meth$$method, method_index);
2311 if (call == NULL) {
2312 ciEnv::current()->record_failure("CodeCache is full");
2313 return;
2314 }
2315 %}
2316
2317 enc_class riscv_enc_call_epilog() %{
2318 C2_MacroAssembler _masm(&cbuf);
2319 if (VerifyStackAtCalls) {
2320 // Check that stack depth is unchanged: find majik cookie on stack
2321 __ call_Unimplemented();
2322 }
2323 %}
2324
2325 enc_class riscv_enc_java_to_runtime(method meth) %{
2326 C2_MacroAssembler _masm(&cbuf);
2327
2328 // some calls to generated routines (arraycopy code) are scheduled
2329 // by C2 as runtime calls. if so we can call them using a jr (they
2330 // will be in a reachable segment) otherwise we have to use a jalr
2331 // which loads the absolute address into a register.
2332 address entry = (address)$meth$$method;
2333 CodeBlob *cb = CodeCache::find_blob(entry);
2334 if (cb != NULL) {
2335 address call = __ trampoline_call(Address(entry, relocInfo::runtime_call_type));
2336 if (call == NULL) {
2337 ciEnv::current()->record_failure("CodeCache is full");
2338 return;
2339 }
2340 } else {
2341 Label retaddr;
2342 __ la(t1, retaddr);
2343 __ la(t0, RuntimeAddress(entry));
2344 // Leave a breadcrumb for JavaFrameAnchor::capture_last_Java_pc()
2345 __ addi(sp, sp, -2 * wordSize);
2346 __ sd(t1, Address(sp, wordSize));
2347 __ jalr(t0);
2348 __ bind(retaddr);
2349 __ addi(sp, sp, 2 * wordSize);
2350 }
2351 %}
2352
2353 // using the cr register as the bool result: 0 for success; others failed.
2354 enc_class riscv_enc_fast_lock(iRegP object, iRegP box, iRegPNoSp tmp1, iRegPNoSp tmp2) %{
2355 C2_MacroAssembler _masm(&cbuf);
2356 Register flag = t1;
2357 Register oop = as_Register($object$$reg);
2358 Register box = as_Register($box$$reg);
2359 Register disp_hdr = as_Register($tmp1$$reg);
2360 Register tmp = as_Register($tmp2$$reg);
2361 Label cont;
2362 Label object_has_monitor;
2363
2364 assert_different_registers(oop, box, tmp, disp_hdr, t0);
2365
2366 // Load markWord from object into displaced_header.
2367 __ ld(disp_hdr, Address(oop, oopDesc::mark_offset_in_bytes()));
2368
2369 if (DiagnoseSyncOnValueBasedClasses != 0) {
2370 __ load_klass(flag, oop);
2371 __ lwu(flag, Address(flag, Klass::access_flags_offset()));
2372 __ andi(flag, flag, JVM_ACC_IS_VALUE_BASED_CLASS, tmp /* tmp */);
2373 __ bnez(flag, cont, true /* is_far */);
2374 }
2375
2376 // Check for existing monitor
2377 __ andi(t0, disp_hdr, markWord::monitor_value);
2378 __ bnez(t0, object_has_monitor);
2379
2380 if (!UseHeavyMonitors) {
2381 // Set tmp to be (markWord of object | UNLOCK_VALUE).
2382 __ ori(tmp, disp_hdr, markWord::unlocked_value);
2383
2384 // Initialize the box. (Must happen before we update the object mark!)
2385 __ sd(tmp, Address(box, BasicLock::displaced_header_offset_in_bytes()));
2386
2387 // Compare object markWord with an unlocked value (tmp) and if
2388 // equal exchange the stack address of our box with object markWord.
2389 // On failure disp_hdr contains the possibly locked markWord.
2390 __ cmpxchg(/*memory address*/oop, /*expected value*/tmp, /*new value*/box, Assembler::int64, Assembler::aq,
2391 Assembler::rl, /*result*/disp_hdr);
2392 __ mv(flag, zr);
2393 __ beq(disp_hdr, tmp, cont); // prepare zero flag and goto cont if we won the cas
2394
2395 assert(oopDesc::mark_offset_in_bytes() == 0, "offset of _mark is not 0");
2396
2397 // If the compare-and-exchange succeeded, then we found an unlocked
2398 // object, will have now locked it will continue at label cont
2399 // We did not see an unlocked object so try the fast recursive case.
2400
2401 // Check if the owner is self by comparing the value in the
2402 // markWord of object (disp_hdr) with the stack pointer.
2403 __ sub(disp_hdr, disp_hdr, sp);
2404 __ mv(tmp, (intptr_t) (~(os::vm_page_size()-1) | (uintptr_t)markWord::lock_mask_in_place));
2405 // If (mark & lock_mask) == 0 and mark - sp < page_size, we are stack-locking and goto cont,
2406 // hence we can store 0 as the displaced header in the box, which indicates that it is a
2407 // recursive lock.
2408 __ andr(tmp/*==0?*/, disp_hdr, tmp);
2409 __ sd(tmp/*==0, perhaps*/, Address(box, BasicLock::displaced_header_offset_in_bytes()));
2410 __ mv(flag, tmp); // we can use the value of tmp as the result here
2411 } else {
2412 __ mv(flag, 1); // Set non-zero flag to indicate 'failure' -> take slow-path
2413 }
2414
2415 __ j(cont);
2416
2417 // Handle existing monitor.
2418 __ bind(object_has_monitor);
2419 // The object's monitor m is unlocked iff m->owner == NULL,
2420 // otherwise m->owner may contain a thread or a stack address.
2421 //
2422 // Try to CAS m->owner from NULL to current thread.
2423 __ add(tmp, disp_hdr, (ObjectMonitor::owner_offset_in_bytes() - markWord::monitor_value));
2424 __ cmpxchg(/*memory address*/tmp, /*expected value*/zr, /*new value*/xthread, Assembler::int64, Assembler::aq,
2425 Assembler::rl, /*result*/flag); // cas succeeds if flag == zr(expected)
2426
2427 // Store a non-null value into the box to avoid looking like a re-entrant
2428 // lock. The fast-path monitor unlock code checks for
2429 // markWord::monitor_value so use markWord::unused_mark which has the
2430 // relevant bit set, and also matches ObjectSynchronizer::slow_enter.
2431 __ mv(tmp, (address)markWord::unused_mark().value());
2432 __ sd(tmp, Address(box, BasicLock::displaced_header_offset_in_bytes()));
2433
2434 __ beqz(flag, cont); // CAS success means locking succeeded
2435
2436 __ bne(flag, xthread, cont); // Check for recursive locking
2437
2438 // Recursive lock case
2439 __ mv(flag, zr);
2440 __ ld(tmp, Address(disp_hdr, ObjectMonitor::recursions_offset_in_bytes() - markWord::monitor_value));
2441 __ add(tmp, tmp, 1u);
2442 __ sd(tmp, Address(disp_hdr, ObjectMonitor::recursions_offset_in_bytes() - markWord::monitor_value));
2443
2444 __ bind(cont);
2445 %}
2446
2447 // using cr flag to indicate the fast_unlock result: 0 for success; others failed.
2448 enc_class riscv_enc_fast_unlock(iRegP object, iRegP box, iRegPNoSp tmp1, iRegPNoSp tmp2) %{
2449 C2_MacroAssembler _masm(&cbuf);
2450 Register flag = t1;
2451 Register oop = as_Register($object$$reg);
2452 Register box = as_Register($box$$reg);
2453 Register disp_hdr = as_Register($tmp1$$reg);
2454 Register tmp = as_Register($tmp2$$reg);
2455 Label cont;
2456 Label object_has_monitor;
2457
2458 assert_different_registers(oop, box, tmp, disp_hdr, flag);
2459
2460 if (!UseHeavyMonitors) {
2461 // Find the lock address and load the displaced header from the stack.
2462 __ ld(disp_hdr, Address(box, BasicLock::displaced_header_offset_in_bytes()));
2463
2464 // If the displaced header is 0, we have a recursive unlock.
2465 __ mv(flag, disp_hdr);
2466 __ beqz(disp_hdr, cont);
2467 }
2468
2469 // Handle existing monitor.
2470 __ ld(tmp, Address(oop, oopDesc::mark_offset_in_bytes()));
2471 __ andi(t0, disp_hdr, markWord::monitor_value);
2472 __ bnez(t0, object_has_monitor);
2473
2474 if (!UseHeavyMonitors) {
2475 // Check if it is still a light weight lock, this is true if we
2476 // see the stack address of the basicLock in the markWord of the
2477 // object.
2478
2479 __ cmpxchg(/*memory address*/oop, /*expected value*/box, /*new value*/disp_hdr, Assembler::int64, Assembler::relaxed,
2480 Assembler::rl, /*result*/tmp);
2481 __ xorr(flag, box, tmp); // box == tmp if cas succeeds
2482 } else {
2483 __ mv(flag, 1); // Set non-zero flag to indicate 'failure' -> take slow path
2484 }
2485 __ j(cont);
2486
2487 assert(oopDesc::mark_offset_in_bytes() == 0, "offset of _mark is not 0");
2488
2489 // Handle existing monitor.
2490 __ bind(object_has_monitor);
2491 STATIC_ASSERT(markWord::monitor_value <= INT_MAX);
2492 __ add(tmp, tmp, -(int)markWord::monitor_value); // monitor
2493 __ ld(disp_hdr, Address(tmp, ObjectMonitor::recursions_offset_in_bytes()));
2494
2495 Label notRecursive;
2496 __ beqz(disp_hdr, notRecursive); // Will be 0 if not recursive.
2497
2498 // Recursive lock
2499 __ addi(disp_hdr, disp_hdr, -1);
2500 __ sd(disp_hdr, Address(tmp, ObjectMonitor::recursions_offset_in_bytes()));
2501 __ mv(flag, zr);
2502 __ j(cont);
2503
2504 __ bind(notRecursive);
2505 __ ld(flag, Address(tmp, ObjectMonitor::EntryList_offset_in_bytes()));
2506 __ ld(disp_hdr, Address(tmp, ObjectMonitor::cxq_offset_in_bytes()));
2507 __ orr(flag, flag, disp_hdr); // Will be 0 if both are 0.
2508 __ bnez(flag, cont);
2509 // need a release store here
2510 __ la(tmp, Address(tmp, ObjectMonitor::owner_offset_in_bytes()));
2511 __ membar(MacroAssembler::LoadStore | MacroAssembler::StoreStore);
2512 __ sd(zr, Address(tmp)); // set unowned
2513
2514 __ bind(cont);
2515 %}
2516
2517 // arithmetic encodings
2518
2519 enc_class riscv_enc_divw(iRegI dst, iRegI src1, iRegI src2) %{
2520 C2_MacroAssembler _masm(&cbuf);
2521 Register dst_reg = as_Register($dst$$reg);
2522 Register src1_reg = as_Register($src1$$reg);
2523 Register src2_reg = as_Register($src2$$reg);
2524 __ corrected_idivl(dst_reg, src1_reg, src2_reg, false);
2525 %}
2526
2527 enc_class riscv_enc_div(iRegI dst, iRegI src1, iRegI src2) %{
2528 C2_MacroAssembler _masm(&cbuf);
2529 Register dst_reg = as_Register($dst$$reg);
2530 Register src1_reg = as_Register($src1$$reg);
2531 Register src2_reg = as_Register($src2$$reg);
2532 __ corrected_idivq(dst_reg, src1_reg, src2_reg, false);
2533 %}
2534
2535 enc_class riscv_enc_modw(iRegI dst, iRegI src1, iRegI src2) %{
2536 C2_MacroAssembler _masm(&cbuf);
2537 Register dst_reg = as_Register($dst$$reg);
2538 Register src1_reg = as_Register($src1$$reg);
2539 Register src2_reg = as_Register($src2$$reg);
2540 __ corrected_idivl(dst_reg, src1_reg, src2_reg, true);
2541 %}
2542
2543 enc_class riscv_enc_mod(iRegI dst, iRegI src1, iRegI src2) %{
2544 C2_MacroAssembler _masm(&cbuf);
2545 Register dst_reg = as_Register($dst$$reg);
2546 Register src1_reg = as_Register($src1$$reg);
2547 Register src2_reg = as_Register($src2$$reg);
2548 __ corrected_idivq(dst_reg, src1_reg, src2_reg, true);
2549 %}
2550
2551 enc_class riscv_enc_tail_call(iRegP jump_target) %{
2552 C2_MacroAssembler _masm(&cbuf);
2553 Assembler::CompressibleRegion cr(&_masm);
2554 Register target_reg = as_Register($jump_target$$reg);
2555 __ jr(target_reg);
2556 %}
2557
2558 enc_class riscv_enc_tail_jmp(iRegP jump_target) %{
2559 C2_MacroAssembler _masm(&cbuf);
2560 Assembler::CompressibleRegion cr(&_masm);
2561 Register target_reg = as_Register($jump_target$$reg);
2562 // exception oop should be in x10
2563 // ret addr has been popped into ra
2564 // callee expects it in x13
2565 __ mv(x13, ra);
2566 __ jr(target_reg);
2567 %}
2568
2569 enc_class riscv_enc_rethrow() %{
2570 C2_MacroAssembler _masm(&cbuf);
2571 __ far_jump(RuntimeAddress(OptoRuntime::rethrow_stub()));
2572 %}
2573
2574 enc_class riscv_enc_ret() %{
2575 C2_MacroAssembler _masm(&cbuf);
2576 Assembler::CompressibleRegion cr(&_masm);
2577 __ ret();
2578 %}
2579
2580 %}
2581
2582 //----------FRAME--------------------------------------------------------------
2583 // Definition of frame structure and management information.
2584 //
2585 // S T A C K L A Y O U T Allocators stack-slot number
2586 // | (to get allocators register number
2587 // G Owned by | | v add OptoReg::stack0())
2588 // r CALLER | |
2589 // o | +--------+ pad to even-align allocators stack-slot
2590 // w V | pad0 | numbers; owned by CALLER
2591 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
2592 // h ^ | in | 5
2593 // | | args | 4 Holes in incoming args owned by SELF
2594 // | | | | 3
2595 // | | +--------+
2596 // V | | old out| Empty on Intel, window on Sparc
2597 // | old |preserve| Must be even aligned.
2598 // | SP-+--------+----> Matcher::_old_SP, even aligned
2599 // | | in | 3 area for Intel ret address
2600 // Owned by |preserve| Empty on Sparc.
2601 // SELF +--------+
2602 // | | pad2 | 2 pad to align old SP
2603 // | +--------+ 1
2604 // | | locks | 0
2605 // | +--------+----> OptoReg::stack0(), even aligned
2606 // | | pad1 | 11 pad to align new SP
2607 // | +--------+
2608 // | | | 10
2609 // | | spills | 9 spills
2610 // V | | 8 (pad0 slot for callee)
2611 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
2612 // ^ | out | 7
2613 // | | args | 6 Holes in outgoing args owned by CALLEE
2614 // Owned by +--------+
2615 // CALLEE | new out| 6 Empty on Intel, window on Sparc
2616 // | new |preserve| Must be even-aligned.
2617 // | SP-+--------+----> Matcher::_new_SP, even aligned
2618 // | | |
2619 //
2620 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
2621 // known from SELF's arguments and the Java calling convention.
2622 // Region 6-7 is determined per call site.
2623 // Note 2: If the calling convention leaves holes in the incoming argument
2624 // area, those holes are owned by SELF. Holes in the outgoing area
2625 // are owned by the CALLEE. Holes should not be necessary in the
2626 // incoming area, as the Java calling convention is completely under
2627 // the control of the AD file. Doubles can be sorted and packed to
2628 // avoid holes. Holes in the outgoing arguments may be necessary for
2629 // varargs C calling conventions.
2630 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
2631 // even aligned with pad0 as needed.
2632 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
2633 // (the latter is true on Intel but is it false on RISCV?)
2634 // region 6-11 is even aligned; it may be padded out more so that
2635 // the region from SP to FP meets the minimum stack alignment.
2636 // Note 4: For I2C adapters, the incoming FP may not meet the minimum stack
2637 // alignment. Region 11, pad1, may be dynamically extended so that
2638 // SP meets the minimum alignment.
2639
2640 frame %{
2641 // These three registers define part of the calling convention
2642 // between compiled code and the interpreter.
2643
2644 // Inline Cache Register or methodOop for I2C.
2645 inline_cache_reg(R31);
2646
2647 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
2648 cisc_spilling_operand_name(indOffset);
2649
2650 // Number of stack slots consumed by locking an object
2651 // generate Compile::sync_stack_slots
2652 // VMRegImpl::slots_per_word = wordSize / stack_slot_size = 8 / 4 = 2
2653 sync_stack_slots(1 * VMRegImpl::slots_per_word);
2654
2655 // Compiled code's Frame Pointer
2656 frame_pointer(R2);
2657
2658 // Interpreter stores its frame pointer in a register which is
2659 // stored to the stack by I2CAdaptors.
2660 // I2CAdaptors convert from interpreted java to compiled java.
2661 interpreter_frame_pointer(R8);
2662
2663 // Stack alignment requirement
2664 stack_alignment(StackAlignmentInBytes); // Alignment size in bytes (128-bit -> 16 bytes)
2665
2666 // Number of outgoing stack slots killed above the out_preserve_stack_slots
2667 // for calls to C. Supports the var-args backing area for register parms.
2668 varargs_C_out_slots_killed(frame::arg_reg_save_area_bytes / BytesPerInt);
2669
2670 // The after-PROLOG location of the return address. Location of
2671 // return address specifies a type (REG or STACK) and a number
2672 // representing the register number (i.e. - use a register name) or
2673 // stack slot.
2674 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
2675 // Otherwise, it is above the locks and verification slot and alignment word
2676 // TODO this may well be correct but need to check why that - 2 is there
2677 // ppc port uses 0 but we definitely need to allow for fixed_slots
2678 // which folds in the space used for monitors
2679 return_addr(STACK - 2 +
2680 align_up((Compile::current()->in_preserve_stack_slots() +
2681 Compile::current()->fixed_slots()),
2682 stack_alignment_in_slots()));
2683
2684 // Location of compiled Java return values. Same as C for now.
2685 return_value
2686 %{
2687 assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL,
2688 "only return normal values");
2689
2690 static const int lo[Op_RegL + 1] = { // enum name
2691 0, // Op_Node
2692 0, // Op_Set
2693 R10_num, // Op_RegN
2694 R10_num, // Op_RegI
2695 R10_num, // Op_RegP
2696 F10_num, // Op_RegF
2697 F10_num, // Op_RegD
2698 R10_num // Op_RegL
2699 };
2700
2701 static const int hi[Op_RegL + 1] = { // enum name
2702 0, // Op_Node
2703 0, // Op_Set
2704 OptoReg::Bad, // Op_RegN
2705 OptoReg::Bad, // Op_RegI
2706 R10_H_num, // Op_RegP
2707 OptoReg::Bad, // Op_RegF
2708 F10_H_num, // Op_RegD
2709 R10_H_num // Op_RegL
2710 };
2711
2712 return OptoRegPair(hi[ideal_reg], lo[ideal_reg]);
2713 %}
2714 %}
2715
2716 //----------ATTRIBUTES---------------------------------------------------------
2717 //----------Operand Attributes-------------------------------------------------
2718 op_attrib op_cost(1); // Required cost attribute
2719
2720 //----------Instruction Attributes---------------------------------------------
2721 ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute
2722 ins_attrib ins_size(32); // Required size attribute (in bits)
2723 ins_attrib ins_short_branch(0); // Required flag: is this instruction
2724 // a non-matching short branch variant
2725 // of some long branch?
2726 ins_attrib ins_alignment(4); // Required alignment attribute (must
2727 // be a power of 2) specifies the
2728 // alignment that some part of the
2729 // instruction (not necessarily the
2730 // start) requires. If > 1, a
2731 // compute_padding() function must be
2732 // provided for the instruction
2733
2734 //----------OPERANDS-----------------------------------------------------------
2735 // Operand definitions must precede instruction definitions for correct parsing
2736 // in the ADLC because operands constitute user defined types which are used in
2737 // instruction definitions.
2738
2739 //----------Simple Operands----------------------------------------------------
2740
2741 // Integer operands 32 bit
2742 // 32 bit immediate
2743 operand immI()
2744 %{
2745 match(ConI);
2746
2747 op_cost(0);
2748 format %{ %}
2749 interface(CONST_INTER);
2750 %}
2751
2752 // 32 bit zero
2753 operand immI0()
2754 %{
2755 predicate(n->get_int() == 0);
2756 match(ConI);
2757
2758 op_cost(0);
2759 format %{ %}
2760 interface(CONST_INTER);
2761 %}
2762
2763 // 32 bit unit increment
2764 operand immI_1()
2765 %{
2766 predicate(n->get_int() == 1);
2767 match(ConI);
2768
2769 op_cost(0);
2770 format %{ %}
2771 interface(CONST_INTER);
2772 %}
2773
2774 // 32 bit unit decrement
2775 operand immI_M1()
2776 %{
2777 predicate(n->get_int() == -1);
2778 match(ConI);
2779
2780 op_cost(0);
2781 format %{ %}
2782 interface(CONST_INTER);
2783 %}
2784
2785 // Unsigned Integer Immediate: 6-bit int, greater than 32
2786 operand uimmI6_ge32() %{
2787 predicate(((unsigned int)(n->get_int()) < 64) && (n->get_int() >= 32));
2788 match(ConI);
2789 op_cost(0);
2790 format %{ %}
2791 interface(CONST_INTER);
2792 %}
2793
2794 operand immI_le_4()
2795 %{
2796 predicate(n->get_int() <= 4);
2797 match(ConI);
2798
2799 op_cost(0);
2800 format %{ %}
2801 interface(CONST_INTER);
2802 %}
2803
2804 operand immI_16()
2805 %{
2806 predicate(n->get_int() == 16);
2807 match(ConI);
2808 op_cost(0);
2809 format %{ %}
2810 interface(CONST_INTER);
2811 %}
2812
2813 operand immI_24()
2814 %{
2815 predicate(n->get_int() == 24);
2816 match(ConI);
2817 op_cost(0);
2818 format %{ %}
2819 interface(CONST_INTER);
2820 %}
2821
2822 operand immI_31()
2823 %{
2824 predicate(n->get_int() == 31);
2825 match(ConI);
2826
2827 op_cost(0);
2828 format %{ %}
2829 interface(CONST_INTER);
2830 %}
2831
2832 operand immI_63()
2833 %{
2834 predicate(n->get_int() == 63);
2835 match(ConI);
2836
2837 op_cost(0);
2838 format %{ %}
2839 interface(CONST_INTER);
2840 %}
2841
2842 // 32 bit integer valid for add immediate
2843 operand immIAdd()
2844 %{
2845 predicate(Assembler::operand_valid_for_add_immediate((int64_t)n->get_int()));
2846 match(ConI);
2847 op_cost(0);
2848 format %{ %}
2849 interface(CONST_INTER);
2850 %}
2851
2852 // 32 bit integer valid for sub immediate
2853 operand immISub()
2854 %{
2855 predicate(Assembler::operand_valid_for_add_immediate(-(int64_t)n->get_int()));
2856 match(ConI);
2857 op_cost(0);
2858 format %{ %}
2859 interface(CONST_INTER);
2860 %}
2861
2862 // 5 bit signed value.
2863 operand immI5()
2864 %{
2865 predicate(n->get_int() <= 15 && n->get_int() >= -16);
2866 match(ConI);
2867
2868 op_cost(0);
2869 format %{ %}
2870 interface(CONST_INTER);
2871 %}
2872
2873 // 5 bit signed value (simm5)
2874 operand immL5()
2875 %{
2876 predicate(n->get_long() <= 15 && n->get_long() >= -16);
2877 match(ConL);
2878
2879 op_cost(0);
2880 format %{ %}
2881 interface(CONST_INTER);
2882 %}
2883
2884 // Integer operands 64 bit
2885 // 64 bit immediate
2886 operand immL()
2887 %{
2888 match(ConL);
2889
2890 op_cost(0);
2891 format %{ %}
2892 interface(CONST_INTER);
2893 %}
2894
2895 // 64 bit zero
2896 operand immL0()
2897 %{
2898 predicate(n->get_long() == 0);
2899 match(ConL);
2900
2901 op_cost(0);
2902 format %{ %}
2903 interface(CONST_INTER);
2904 %}
2905
2906 // Pointer operands
2907 // Pointer Immediate
2908 operand immP()
2909 %{
2910 match(ConP);
2911
2912 op_cost(0);
2913 format %{ %}
2914 interface(CONST_INTER);
2915 %}
2916
2917 // NULL Pointer Immediate
2918 operand immP0()
2919 %{
2920 predicate(n->get_ptr() == 0);
2921 match(ConP);
2922
2923 op_cost(0);
2924 format %{ %}
2925 interface(CONST_INTER);
2926 %}
2927
2928 // Pointer Immediate One
2929 // this is used in object initialization (initial object header)
2930 operand immP_1()
2931 %{
2932 predicate(n->get_ptr() == 1);
2933 match(ConP);
2934
2935 op_cost(0);
2936 format %{ %}
2937 interface(CONST_INTER);
2938 %}
2939
2940 // Card Table Byte Map Base
2941 operand immByteMapBase()
2942 %{
2943 // Get base of card map
2944 predicate(BarrierSet::barrier_set()->is_a(BarrierSet::CardTableBarrierSet) &&
2945 (CardTable::CardValue*)n->get_ptr() ==
2946 ((CardTableBarrierSet*)(BarrierSet::barrier_set()))->card_table()->byte_map_base());
2947 match(ConP);
2948
2949 op_cost(0);
2950 format %{ %}
2951 interface(CONST_INTER);
2952 %}
2953
2954 // Int Immediate: low 16-bit mask
2955 operand immI_16bits()
2956 %{
2957 predicate(n->get_int() == 0xFFFF);
2958 match(ConI);
2959 op_cost(0);
2960 format %{ %}
2961 interface(CONST_INTER);
2962 %}
2963
2964 // Long Immediate: low 32-bit mask
2965 operand immL_32bits()
2966 %{
2967 predicate(n->get_long() == 0xFFFFFFFFL);
2968 match(ConL);
2969 op_cost(0);
2970 format %{ %}
2971 interface(CONST_INTER);
2972 %}
2973
2974 // 64 bit unit decrement
2975 operand immL_M1()
2976 %{
2977 predicate(n->get_long() == -1);
2978 match(ConL);
2979
2980 op_cost(0);
2981 format %{ %}
2982 interface(CONST_INTER);
2983 %}
2984
2985
2986 // 32 bit offset of pc in thread anchor
2987
2988 operand immL_pc_off()
2989 %{
2990 predicate(n->get_long() == in_bytes(JavaThread::frame_anchor_offset()) +
2991 in_bytes(JavaFrameAnchor::last_Java_pc_offset()));
2992 match(ConL);
2993
2994 op_cost(0);
2995 format %{ %}
2996 interface(CONST_INTER);
2997 %}
2998
2999 // 64 bit integer valid for add immediate
3000 operand immLAdd()
3001 %{
3002 predicate(Assembler::operand_valid_for_add_immediate(n->get_long()));
3003 match(ConL);
3004 op_cost(0);
3005 format %{ %}
3006 interface(CONST_INTER);
3007 %}
3008
3009 // 64 bit integer valid for sub immediate
3010 operand immLSub()
3011 %{
3012 predicate(Assembler::operand_valid_for_add_immediate(-(n->get_long())));
3013 match(ConL);
3014 op_cost(0);
3015 format %{ %}
3016 interface(CONST_INTER);
3017 %}
3018
3019 // Narrow pointer operands
3020 // Narrow Pointer Immediate
3021 operand immN()
3022 %{
3023 match(ConN);
3024
3025 op_cost(0);
3026 format %{ %}
3027 interface(CONST_INTER);
3028 %}
3029
3030 // Narrow NULL Pointer Immediate
3031 operand immN0()
3032 %{
3033 predicate(n->get_narrowcon() == 0);
3034 match(ConN);
3035
3036 op_cost(0);
3037 format %{ %}
3038 interface(CONST_INTER);
3039 %}
3040
3041 operand immNKlass()
3042 %{
3043 match(ConNKlass);
3044
3045 op_cost(0);
3046 format %{ %}
3047 interface(CONST_INTER);
3048 %}
3049
3050 // Float and Double operands
3051 // Double Immediate
3052 operand immD()
3053 %{
3054 match(ConD);
3055 op_cost(0);
3056 format %{ %}
3057 interface(CONST_INTER);
3058 %}
3059
3060 // Double Immediate: +0.0d
3061 operand immD0()
3062 %{
3063 predicate(jlong_cast(n->getd()) == 0);
3064 match(ConD);
3065
3066 op_cost(0);
3067 format %{ %}
3068 interface(CONST_INTER);
3069 %}
3070
3071 // Float Immediate
3072 operand immF()
3073 %{
3074 match(ConF);
3075 op_cost(0);
3076 format %{ %}
3077 interface(CONST_INTER);
3078 %}
3079
3080 // Float Immediate: +0.0f.
3081 operand immF0()
3082 %{
3083 predicate(jint_cast(n->getf()) == 0);
3084 match(ConF);
3085
3086 op_cost(0);
3087 format %{ %}
3088 interface(CONST_INTER);
3089 %}
3090
3091 operand immIOffset()
3092 %{
3093 predicate(is_imm_in_range(n->get_int(), 12, 0));
3094 match(ConI);
3095 op_cost(0);
3096 format %{ %}
3097 interface(CONST_INTER);
3098 %}
3099
3100 operand immLOffset()
3101 %{
3102 predicate(is_imm_in_range(n->get_long(), 12, 0));
3103 match(ConL);
3104 op_cost(0);
3105 format %{ %}
3106 interface(CONST_INTER);
3107 %}
3108
3109 // Scale values
3110 operand immIScale()
3111 %{
3112 predicate(1 <= n->get_int() && (n->get_int() <= 3));
3113 match(ConI);
3114
3115 op_cost(0);
3116 format %{ %}
3117 interface(CONST_INTER);
3118 %}
3119
3120 // Integer 32 bit Register Operands
3121 operand iRegI()
3122 %{
3123 constraint(ALLOC_IN_RC(any_reg32));
3124 match(RegI);
3125 match(iRegINoSp);
3126 op_cost(0);
3127 format %{ %}
3128 interface(REG_INTER);
3129 %}
3130
3131 // Integer 32 bit Register not Special
3132 operand iRegINoSp()
3133 %{
3134 constraint(ALLOC_IN_RC(no_special_reg32));
3135 match(RegI);
3136 op_cost(0);
3137 format %{ %}
3138 interface(REG_INTER);
3139 %}
3140
3141 // Register R10 only
3142 operand iRegI_R10()
3143 %{
3144 constraint(ALLOC_IN_RC(int_r10_reg));
3145 match(RegI);
3146 match(iRegINoSp);
3147 op_cost(0);
3148 format %{ %}
3149 interface(REG_INTER);
3150 %}
3151
3152 // Register R12 only
3153 operand iRegI_R12()
3154 %{
3155 constraint(ALLOC_IN_RC(int_r12_reg));
3156 match(RegI);
3157 match(iRegINoSp);
3158 op_cost(0);
3159 format %{ %}
3160 interface(REG_INTER);
3161 %}
3162
3163 // Register R13 only
3164 operand iRegI_R13()
3165 %{
3166 constraint(ALLOC_IN_RC(int_r13_reg));
3167 match(RegI);
3168 match(iRegINoSp);
3169 op_cost(0);
3170 format %{ %}
3171 interface(REG_INTER);
3172 %}
3173
3174 // Register R14 only
3175 operand iRegI_R14()
3176 %{
3177 constraint(ALLOC_IN_RC(int_r14_reg));
3178 match(RegI);
3179 match(iRegINoSp);
3180 op_cost(0);
3181 format %{ %}
3182 interface(REG_INTER);
3183 %}
3184
3185 // Integer 64 bit Register Operands
3186 operand iRegL()
3187 %{
3188 constraint(ALLOC_IN_RC(any_reg));
3189 match(RegL);
3190 match(iRegLNoSp);
3191 op_cost(0);
3192 format %{ %}
3193 interface(REG_INTER);
3194 %}
3195
3196 // Integer 64 bit Register not Special
3197 operand iRegLNoSp()
3198 %{
3199 constraint(ALLOC_IN_RC(no_special_reg));
3200 match(RegL);
3201 match(iRegL_R10);
3202 format %{ %}
3203 interface(REG_INTER);
3204 %}
3205
3206 // Long 64 bit Register R28 only
3207 operand iRegL_R28()
3208 %{
3209 constraint(ALLOC_IN_RC(r28_reg));
3210 match(RegL);
3211 match(iRegLNoSp);
3212 op_cost(0);
3213 format %{ %}
3214 interface(REG_INTER);
3215 %}
3216
3217 // Long 64 bit Register R29 only
3218 operand iRegL_R29()
3219 %{
3220 constraint(ALLOC_IN_RC(r29_reg));
3221 match(RegL);
3222 match(iRegLNoSp);
3223 op_cost(0);
3224 format %{ %}
3225 interface(REG_INTER);
3226 %}
3227
3228 // Long 64 bit Register R30 only
3229 operand iRegL_R30()
3230 %{
3231 constraint(ALLOC_IN_RC(r30_reg));
3232 match(RegL);
3233 match(iRegLNoSp);
3234 op_cost(0);
3235 format %{ %}
3236 interface(REG_INTER);
3237 %}
3238
3239 // Pointer Register Operands
3240 // Pointer Register
3241 operand iRegP()
3242 %{
3243 constraint(ALLOC_IN_RC(ptr_reg));
3244 match(RegP);
3245 match(iRegPNoSp);
3246 match(iRegP_R10);
3247 match(javaThread_RegP);
3248 op_cost(0);
3249 format %{ %}
3250 interface(REG_INTER);
3251 %}
3252
3253 // Pointer 64 bit Register not Special
3254 operand iRegPNoSp()
3255 %{
3256 constraint(ALLOC_IN_RC(no_special_ptr_reg));
3257 match(RegP);
3258 op_cost(0);
3259 format %{ %}
3260 interface(REG_INTER);
3261 %}
3262
3263 operand iRegP_R10()
3264 %{
3265 constraint(ALLOC_IN_RC(r10_reg));
3266 match(RegP);
3267 // match(iRegP);
3268 match(iRegPNoSp);
3269 op_cost(0);
3270 format %{ %}
3271 interface(REG_INTER);
3272 %}
3273
3274 // Pointer 64 bit Register R11 only
3275 operand iRegP_R11()
3276 %{
3277 constraint(ALLOC_IN_RC(r11_reg));
3278 match(RegP);
3279 match(iRegPNoSp);
3280 op_cost(0);
3281 format %{ %}
3282 interface(REG_INTER);
3283 %}
3284
3285 operand iRegP_R12()
3286 %{
3287 constraint(ALLOC_IN_RC(r12_reg));
3288 match(RegP);
3289 // match(iRegP);
3290 match(iRegPNoSp);
3291 op_cost(0);
3292 format %{ %}
3293 interface(REG_INTER);
3294 %}
3295
3296 // Pointer 64 bit Register R13 only
3297 operand iRegP_R13()
3298 %{
3299 constraint(ALLOC_IN_RC(r13_reg));
3300 match(RegP);
3301 match(iRegPNoSp);
3302 op_cost(0);
3303 format %{ %}
3304 interface(REG_INTER);
3305 %}
3306
3307 operand iRegP_R14()
3308 %{
3309 constraint(ALLOC_IN_RC(r14_reg));
3310 match(RegP);
3311 // match(iRegP);
3312 match(iRegPNoSp);
3313 op_cost(0);
3314 format %{ %}
3315 interface(REG_INTER);
3316 %}
3317
3318 operand iRegP_R15()
3319 %{
3320 constraint(ALLOC_IN_RC(r15_reg));
3321 match(RegP);
3322 // match(iRegP);
3323 match(iRegPNoSp);
3324 op_cost(0);
3325 format %{ %}
3326 interface(REG_INTER);
3327 %}
3328
3329 operand iRegP_R16()
3330 %{
3331 constraint(ALLOC_IN_RC(r16_reg));
3332 match(RegP);
3333 // match(iRegP);
3334 match(iRegPNoSp);
3335 op_cost(0);
3336 format %{ %}
3337 interface(REG_INTER);
3338 %}
3339
3340 // Pointer 64 bit Register R28 only
3341 operand iRegP_R28()
3342 %{
3343 constraint(ALLOC_IN_RC(r28_reg));
3344 match(RegP);
3345 match(iRegPNoSp);
3346 op_cost(0);
3347 format %{ %}
3348 interface(REG_INTER);
3349 %}
3350
3351 // Pointer Register Operands
3352 // Narrow Pointer Register
3353 operand iRegN()
3354 %{
3355 constraint(ALLOC_IN_RC(any_reg32));
3356 match(RegN);
3357 match(iRegNNoSp);
3358 op_cost(0);
3359 format %{ %}
3360 interface(REG_INTER);
3361 %}
3362
3363 // Integer 64 bit Register not Special
3364 operand iRegNNoSp()
3365 %{
3366 constraint(ALLOC_IN_RC(no_special_reg32));
3367 match(RegN);
3368 op_cost(0);
3369 format %{ %}
3370 interface(REG_INTER);
3371 %}
3372
3373 // heap base register -- used for encoding immN0
3374 operand iRegIHeapbase()
3375 %{
3376 constraint(ALLOC_IN_RC(heapbase_reg));
3377 match(RegI);
3378 op_cost(0);
3379 format %{ %}
3380 interface(REG_INTER);
3381 %}
3382
3383 // Long 64 bit Register R10 only
3384 operand iRegL_R10()
3385 %{
3386 constraint(ALLOC_IN_RC(r10_reg));
3387 match(RegL);
3388 match(iRegLNoSp);
3389 op_cost(0);
3390 format %{ %}
3391 interface(REG_INTER);
3392 %}
3393
3394 // Float Register
3395 // Float register operands
3396 operand fRegF()
3397 %{
3398 constraint(ALLOC_IN_RC(float_reg));
3399 match(RegF);
3400
3401 op_cost(0);
3402 format %{ %}
3403 interface(REG_INTER);
3404 %}
3405
3406 // Double Register
3407 // Double register operands
3408 operand fRegD()
3409 %{
3410 constraint(ALLOC_IN_RC(double_reg));
3411 match(RegD);
3412
3413 op_cost(0);
3414 format %{ %}
3415 interface(REG_INTER);
3416 %}
3417
3418 // Generic vector class. This will be used for
3419 // all vector operands.
3420 operand vReg()
3421 %{
3422 constraint(ALLOC_IN_RC(vectora_reg));
3423 match(VecA);
3424 op_cost(0);
3425 format %{ %}
3426 interface(REG_INTER);
3427 %}
3428
3429 operand vReg_V1()
3430 %{
3431 constraint(ALLOC_IN_RC(v1_reg));
3432 match(VecA);
3433 match(vReg);
3434 op_cost(0);
3435 format %{ %}
3436 interface(REG_INTER);
3437 %}
3438
3439 operand vReg_V2()
3440 %{
3441 constraint(ALLOC_IN_RC(v2_reg));
3442 match(VecA);
3443 match(vReg);
3444 op_cost(0);
3445 format %{ %}
3446 interface(REG_INTER);
3447 %}
3448
3449 operand vReg_V3()
3450 %{
3451 constraint(ALLOC_IN_RC(v3_reg));
3452 match(VecA);
3453 match(vReg);
3454 op_cost(0);
3455 format %{ %}
3456 interface(REG_INTER);
3457 %}
3458
3459 operand vReg_V4()
3460 %{
3461 constraint(ALLOC_IN_RC(v4_reg));
3462 match(VecA);
3463 match(vReg);
3464 op_cost(0);
3465 format %{ %}
3466 interface(REG_INTER);
3467 %}
3468
3469 operand vReg_V5()
3470 %{
3471 constraint(ALLOC_IN_RC(v5_reg));
3472 match(VecA);
3473 match(vReg);
3474 op_cost(0);
3475 format %{ %}
3476 interface(REG_INTER);
3477 %}
3478
3479 // Java Thread Register
3480 operand javaThread_RegP(iRegP reg)
3481 %{
3482 constraint(ALLOC_IN_RC(java_thread_reg)); // java_thread_reg
3483 match(reg);
3484 op_cost(0);
3485 format %{ %}
3486 interface(REG_INTER);
3487 %}
3488
3489 //----------Memory Operands----------------------------------------------------
3490 // RISCV has only base_plus_offset and literal address mode, so no need to use
3491 // index and scale. Here set index as 0xffffffff and scale as 0x0.
3492 operand indirect(iRegP reg)
3493 %{
3494 constraint(ALLOC_IN_RC(ptr_reg));
3495 match(reg);
3496 op_cost(0);
3497 format %{ "[$reg]" %}
3498 interface(MEMORY_INTER) %{
3499 base($reg);
3500 index(0xffffffff);
3501 scale(0x0);
3502 disp(0x0);
3503 %}
3504 %}
3505
3506 operand indOffI(iRegP reg, immIOffset off)
3507 %{
3508 constraint(ALLOC_IN_RC(ptr_reg));
3509 match(AddP reg off);
3510 op_cost(0);
3511 format %{ "[$reg, $off]" %}
3512 interface(MEMORY_INTER) %{
3513 base($reg);
3514 index(0xffffffff);
3515 scale(0x0);
3516 disp($off);
3517 %}
3518 %}
3519
3520 operand indOffL(iRegP reg, immLOffset off)
3521 %{
3522 constraint(ALLOC_IN_RC(ptr_reg));
3523 match(AddP reg off);
3524 op_cost(0);
3525 format %{ "[$reg, $off]" %}
3526 interface(MEMORY_INTER) %{
3527 base($reg);
3528 index(0xffffffff);
3529 scale(0x0);
3530 disp($off);
3531 %}
3532 %}
3533
3534 operand indirectN(iRegN reg)
3535 %{
3536 predicate(CompressedOops::shift() == 0);
3537 constraint(ALLOC_IN_RC(ptr_reg));
3538 match(DecodeN reg);
3539 op_cost(0);
3540 format %{ "[$reg]\t# narrow" %}
3541 interface(MEMORY_INTER) %{
3542 base($reg);
3543 index(0xffffffff);
3544 scale(0x0);
3545 disp(0x0);
3546 %}
3547 %}
3548
3549 operand indOffIN(iRegN reg, immIOffset off)
3550 %{
3551 predicate(CompressedOops::shift() == 0);
3552 constraint(ALLOC_IN_RC(ptr_reg));
3553 match(AddP (DecodeN reg) off);
3554 op_cost(0);
3555 format %{ "[$reg, $off]\t# narrow" %}
3556 interface(MEMORY_INTER) %{
3557 base($reg);
3558 index(0xffffffff);
3559 scale(0x0);
3560 disp($off);
3561 %}
3562 %}
3563
3564 operand indOffLN(iRegN reg, immLOffset off)
3565 %{
3566 predicate(CompressedOops::shift() == 0);
3567 constraint(ALLOC_IN_RC(ptr_reg));
3568 match(AddP (DecodeN reg) off);
3569 op_cost(0);
3570 format %{ "[$reg, $off]\t# narrow" %}
3571 interface(MEMORY_INTER) %{
3572 base($reg);
3573 index(0xffffffff);
3574 scale(0x0);
3575 disp($off);
3576 %}
3577 %}
3578
3579 // RISCV opto stubs need to write to the pc slot in the thread anchor
3580 operand thread_anchor_pc(javaThread_RegP reg, immL_pc_off off)
3581 %{
3582 constraint(ALLOC_IN_RC(ptr_reg));
3583 match(AddP reg off);
3584 op_cost(0);
3585 format %{ "[$reg, $off]" %}
3586 interface(MEMORY_INTER) %{
3587 base($reg);
3588 index(0xffffffff);
3589 scale(0x0);
3590 disp($off);
3591 %}
3592 %}
3593
3594
3595 //----------Special Memory Operands--------------------------------------------
3596 // Stack Slot Operand - This operand is used for loading and storing temporary
3597 // values on the stack where a match requires a value to
3598 // flow through memory.
3599 operand stackSlotI(sRegI reg)
3600 %{
3601 constraint(ALLOC_IN_RC(stack_slots));
3602 // No match rule because this operand is only generated in matching
3603 // match(RegI);
3604 format %{ "[$reg]" %}
3605 interface(MEMORY_INTER) %{
3606 base(0x02); // RSP
3607 index(0xffffffff); // No Index
3608 scale(0x0); // No Scale
3609 disp($reg); // Stack Offset
3610 %}
3611 %}
3612
3613 operand stackSlotF(sRegF reg)
3614 %{
3615 constraint(ALLOC_IN_RC(stack_slots));
3616 // No match rule because this operand is only generated in matching
3617 // match(RegF);
3618 format %{ "[$reg]" %}
3619 interface(MEMORY_INTER) %{
3620 base(0x02); // RSP
3621 index(0xffffffff); // No Index
3622 scale(0x0); // No Scale
3623 disp($reg); // Stack Offset
3624 %}
3625 %}
3626
3627 operand stackSlotD(sRegD reg)
3628 %{
3629 constraint(ALLOC_IN_RC(stack_slots));
3630 // No match rule because this operand is only generated in matching
3631 // match(RegD);
3632 format %{ "[$reg]" %}
3633 interface(MEMORY_INTER) %{
3634 base(0x02); // RSP
3635 index(0xffffffff); // No Index
3636 scale(0x0); // No Scale
3637 disp($reg); // Stack Offset
3638 %}
3639 %}
3640
3641 operand stackSlotL(sRegL reg)
3642 %{
3643 constraint(ALLOC_IN_RC(stack_slots));
3644 // No match rule because this operand is only generated in matching
3645 // match(RegL);
3646 format %{ "[$reg]" %}
3647 interface(MEMORY_INTER) %{
3648 base(0x02); // RSP
3649 index(0xffffffff); // No Index
3650 scale(0x0); // No Scale
3651 disp($reg); // Stack Offset
3652 %}
3653 %}
3654
3655 // Special operand allowing long args to int ops to be truncated for free
3656
3657 operand iRegL2I(iRegL reg) %{
3658
3659 op_cost(0);
3660
3661 match(ConvL2I reg);
3662
3663 format %{ "l2i($reg)" %}
3664
3665 interface(REG_INTER)
3666 %}
3667
3668
3669 // Comparison Operands
3670 // NOTE: Label is a predefined operand which should not be redefined in
3671 // the AD file. It is generically handled within the ADLC.
3672
3673 //----------Conditional Branch Operands----------------------------------------
3674 // Comparison Op - This is the operation of the comparison, and is limited to
3675 // the following set of codes:
3676 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
3677 //
3678 // Other attributes of the comparison, such as unsignedness, are specified
3679 // by the comparison instruction that sets a condition code flags register.
3680 // That result is represented by a flags operand whose subtype is appropriate
3681 // to the unsignedness (etc.) of the comparison.
3682 //
3683 // Later, the instruction which matches both the Comparison Op (a Bool) and
3684 // the flags (produced by the Cmp) specifies the coding of the comparison op
3685 // by matching a specific subtype of Bool operand below, such as cmpOpU.
3686
3687
3688 // used for signed integral comparisons and fp comparisons
3689 operand cmpOp()
3690 %{
3691 match(Bool);
3692
3693 format %{ "" %}
3694
3695 // the values in interface derives from struct BoolTest::mask
3696 interface(COND_INTER) %{
3697 equal(0x0, "eq");
3698 greater(0x1, "gt");
3699 overflow(0x2, "overflow");
3700 less(0x3, "lt");
3701 not_equal(0x4, "ne");
3702 less_equal(0x5, "le");
3703 no_overflow(0x6, "no_overflow");
3704 greater_equal(0x7, "ge");
3705 %}
3706 %}
3707
3708 // used for unsigned integral comparisons
3709 operand cmpOpU()
3710 %{
3711 match(Bool);
3712
3713 format %{ "" %}
3714 // the values in interface derives from struct BoolTest::mask
3715 interface(COND_INTER) %{
3716 equal(0x0, "eq");
3717 greater(0x1, "gtu");
3718 overflow(0x2, "overflow");
3719 less(0x3, "ltu");
3720 not_equal(0x4, "ne");
3721 less_equal(0x5, "leu");
3722 no_overflow(0x6, "no_overflow");
3723 greater_equal(0x7, "geu");
3724 %}
3725 %}
3726
3727 // used for certain integral comparisons which can be
3728 // converted to bxx instructions
3729 operand cmpOpEqNe()
3730 %{
3731 match(Bool);
3732 op_cost(0);
3733 predicate(n->as_Bool()->_test._test == BoolTest::ne ||
3734 n->as_Bool()->_test._test == BoolTest::eq);
3735
3736 format %{ "" %}
3737 interface(COND_INTER) %{
3738 equal(0x0, "eq");
3739 greater(0x1, "gt");
3740 overflow(0x2, "overflow");
3741 less(0x3, "lt");
3742 not_equal(0x4, "ne");
3743 less_equal(0x5, "le");
3744 no_overflow(0x6, "no_overflow");
3745 greater_equal(0x7, "ge");
3746 %}
3747 %}
3748
3749 operand cmpOpULtGe()
3750 %{
3751 match(Bool);
3752 op_cost(0);
3753 predicate(n->as_Bool()->_test._test == BoolTest::lt ||
3754 n->as_Bool()->_test._test == BoolTest::ge);
3755
3756 format %{ "" %}
3757 interface(COND_INTER) %{
3758 equal(0x0, "eq");
3759 greater(0x1, "gt");
3760 overflow(0x2, "overflow");
3761 less(0x3, "lt");
3762 not_equal(0x4, "ne");
3763 less_equal(0x5, "le");
3764 no_overflow(0x6, "no_overflow");
3765 greater_equal(0x7, "ge");
3766 %}
3767 %}
3768
3769 operand cmpOpUEqNeLeGt()
3770 %{
3771 match(Bool);
3772 op_cost(0);
3773 predicate(n->as_Bool()->_test._test == BoolTest::ne ||
3774 n->as_Bool()->_test._test == BoolTest::eq ||
3775 n->as_Bool()->_test._test == BoolTest::le ||
3776 n->as_Bool()->_test._test == BoolTest::gt);
3777
3778 format %{ "" %}
3779 interface(COND_INTER) %{
3780 equal(0x0, "eq");
3781 greater(0x1, "gt");
3782 overflow(0x2, "overflow");
3783 less(0x3, "lt");
3784 not_equal(0x4, "ne");
3785 less_equal(0x5, "le");
3786 no_overflow(0x6, "no_overflow");
3787 greater_equal(0x7, "ge");
3788 %}
3789 %}
3790
3791
3792 // Flags register, used as output of compare logic
3793 operand rFlagsReg()
3794 %{
3795 constraint(ALLOC_IN_RC(reg_flags));
3796 match(RegFlags);
3797
3798 op_cost(0);
3799 format %{ "RFLAGS" %}
3800 interface(REG_INTER);
3801 %}
3802
3803 // Special Registers
3804
3805 // Method Register
3806 operand inline_cache_RegP(iRegP reg)
3807 %{
3808 constraint(ALLOC_IN_RC(method_reg)); // inline_cache_reg
3809 match(reg);
3810 match(iRegPNoSp);
3811 op_cost(0);
3812 format %{ %}
3813 interface(REG_INTER);
3814 %}
3815
3816 //----------OPERAND CLASSES----------------------------------------------------
3817 // Operand Classes are groups of operands that are used as to simplify
3818 // instruction definitions by not requiring the AD writer to specify
3819 // separate instructions for every form of operand when the
3820 // instruction accepts multiple operand types with the same basic
3821 // encoding and format. The classic case of this is memory operands.
3822
3823 // memory is used to define read/write location for load/store
3824 // instruction defs. we can turn a memory op into an Address
3825
3826 opclass memory(indirect, indOffI, indOffL, indirectN, indOffIN, indOffLN);
3827
3828 // iRegIorL2I is used for src inputs in rules for 32 bit int (I)
3829 // operations. it allows the src to be either an iRegI or a (ConvL2I
3830 // iRegL). in the latter case the l2i normally planted for a ConvL2I
3831 // can be elided because the 32-bit instruction will just employ the
3832 // lower 32 bits anyway.
3833 //
3834 // n.b. this does not elide all L2I conversions. if the truncated
3835 // value is consumed by more than one operation then the ConvL2I
3836 // cannot be bundled into the consuming nodes so an l2i gets planted
3837 // (actually a mvw $dst $src) and the downstream instructions consume
3838 // the result of the l2i as an iRegI input. That's a shame since the
3839 // mvw is actually redundant but its not too costly.
3840
3841 opclass iRegIorL2I(iRegI, iRegL2I);
3842 opclass iRegIorL(iRegI, iRegL);
3843 opclass iRegNorP(iRegN, iRegP);
3844 opclass iRegILNP(iRegI, iRegL, iRegN, iRegP);
3845 opclass iRegILNPNoSp(iRegINoSp, iRegLNoSp, iRegNNoSp, iRegPNoSp);
3846 opclass immIorL(immI, immL);
3847
3848 //----------PIPELINE-----------------------------------------------------------
3849 // Rules which define the behavior of the target architectures pipeline.
3850
3851 // For specific pipelines, e.g. generic RISC-V, define the stages of that pipeline
3852 //pipe_desc(ID, EX, MEM, WR);
3853 #define ID S0
3854 #define EX S1
3855 #define MEM S2
3856 #define WR S3
3857
3858 // Integer ALU reg operation
3859 pipeline %{
3860
3861 attributes %{
3862 // RISC-V instructions are of fixed length
3863 fixed_size_instructions; // Fixed size instructions TODO does
3864 max_instructions_per_bundle = 2; // Generic RISC-V 1, Sifive Series 7 2
3865 // RISC-V instructions come in 32-bit word units
3866 instruction_unit_size = 4; // An instruction is 4 bytes long
3867 instruction_fetch_unit_size = 64; // The processor fetches one line
3868 instruction_fetch_units = 1; // of 64 bytes
3869
3870 // List of nop instructions
3871 nops( MachNop );
3872 %}
3873
3874 // We don't use an actual pipeline model so don't care about resources
3875 // or description. we do use pipeline classes to introduce fixed
3876 // latencies
3877
3878 //----------RESOURCES----------------------------------------------------------
3879 // Resources are the functional units available to the machine
3880
3881 // Generic RISC-V pipeline
3882 // 1 decoder
3883 // 1 instruction decoded per cycle
3884 // 1 load/store ops per cycle, 1 branch, 1 FPU
3885 // 1 mul, 1 div
3886
3887 resources ( DECODE,
3888 ALU,
3889 MUL,
3890 DIV,
3891 BRANCH,
3892 LDST,
3893 FPU);
3894
3895 //----------PIPELINE DESCRIPTION-----------------------------------------------
3896 // Pipeline Description specifies the stages in the machine's pipeline
3897
3898 // Define the pipeline as a generic 6 stage pipeline
3899 pipe_desc(S0, S1, S2, S3, S4, S5);
3900
3901 //----------PIPELINE CLASSES---------------------------------------------------
3902 // Pipeline Classes describe the stages in which input and output are
3903 // referenced by the hardware pipeline.
3904
3905 pipe_class fp_dop_reg_reg_s(fRegF dst, fRegF src1, fRegF src2)
3906 %{
3907 single_instruction;
3908 src1 : S1(read);
3909 src2 : S2(read);
3910 dst : S5(write);
3911 DECODE : ID;
3912 FPU : S5;
3913 %}
3914
3915 pipe_class fp_dop_reg_reg_d(fRegD dst, fRegD src1, fRegD src2)
3916 %{
3917 src1 : S1(read);
3918 src2 : S2(read);
3919 dst : S5(write);
3920 DECODE : ID;
3921 FPU : S5;
3922 %}
3923
3924 pipe_class fp_uop_s(fRegF dst, fRegF src)
3925 %{
3926 single_instruction;
3927 src : S1(read);
3928 dst : S5(write);
3929 DECODE : ID;
3930 FPU : S5;
3931 %}
3932
3933 pipe_class fp_uop_d(fRegD dst, fRegD src)
3934 %{
3935 single_instruction;
3936 src : S1(read);
3937 dst : S5(write);
3938 DECODE : ID;
3939 FPU : S5;
3940 %}
3941
3942 pipe_class fp_d2f(fRegF dst, fRegD src)
3943 %{
3944 single_instruction;
3945 src : S1(read);
3946 dst : S5(write);
3947 DECODE : ID;
3948 FPU : S5;
3949 %}
3950
3951 pipe_class fp_f2d(fRegD dst, fRegF src)
3952 %{
3953 single_instruction;
3954 src : S1(read);
3955 dst : S5(write);
3956 DECODE : ID;
3957 FPU : S5;
3958 %}
3959
3960 pipe_class fp_f2i(iRegINoSp dst, fRegF src)
3961 %{
3962 single_instruction;
3963 src : S1(read);
3964 dst : S5(write);
3965 DECODE : ID;
3966 FPU : S5;
3967 %}
3968
3969 pipe_class fp_f2l(iRegLNoSp dst, fRegF src)
3970 %{
3971 single_instruction;
3972 src : S1(read);
3973 dst : S5(write);
3974 DECODE : ID;
3975 FPU : S5;
3976 %}
3977
3978 pipe_class fp_i2f(fRegF dst, iRegIorL2I src)
3979 %{
3980 single_instruction;
3981 src : S1(read);
3982 dst : S5(write);
3983 DECODE : ID;
3984 FPU : S5;
3985 %}
3986
3987 pipe_class fp_l2f(fRegF dst, iRegL src)
3988 %{
3989 single_instruction;
3990 src : S1(read);
3991 dst : S5(write);
3992 DECODE : ID;
3993 FPU : S5;
3994 %}
3995
3996 pipe_class fp_d2i(iRegINoSp dst, fRegD src)
3997 %{
3998 single_instruction;
3999 src : S1(read);
4000 dst : S5(write);
4001 DECODE : ID;
4002 FPU : S5;
4003 %}
4004
4005 pipe_class fp_d2l(iRegLNoSp dst, fRegD src)
4006 %{
4007 single_instruction;
4008 src : S1(read);
4009 dst : S5(write);
4010 DECODE : ID;
4011 FPU : S5;
4012 %}
4013
4014 pipe_class fp_i2d(fRegD dst, iRegIorL2I src)
4015 %{
4016 single_instruction;
4017 src : S1(read);
4018 dst : S5(write);
4019 DECODE : ID;
4020 FPU : S5;
4021 %}
4022
4023 pipe_class fp_l2d(fRegD dst, iRegIorL2I src)
4024 %{
4025 single_instruction;
4026 src : S1(read);
4027 dst : S5(write);
4028 DECODE : ID;
4029 FPU : S5;
4030 %}
4031
4032 pipe_class fp_div_s(fRegF dst, fRegF src1, fRegF src2)
4033 %{
4034 single_instruction;
4035 src1 : S1(read);
4036 src2 : S2(read);
4037 dst : S5(write);
4038 DECODE : ID;
4039 FPU : S5;
4040 %}
4041
4042 pipe_class fp_div_d(fRegD dst, fRegD src1, fRegD src2)
4043 %{
4044 single_instruction;
4045 src1 : S1(read);
4046 src2 : S2(read);
4047 dst : S5(write);
4048 DECODE : ID;
4049 FPU : S5;
4050 %}
4051
4052 pipe_class fp_sqrt_s(fRegF dst, fRegF src1, fRegF src2)
4053 %{
4054 single_instruction;
4055 src1 : S1(read);
4056 src2 : S2(read);
4057 dst : S5(write);
4058 DECODE : ID;
4059 FPU : S5;
4060 %}
4061
4062 pipe_class fp_sqrt_d(fRegD dst, fRegD src1, fRegD src2)
4063 %{
4064 single_instruction;
4065 src1 : S1(read);
4066 src2 : S2(read);
4067 dst : S5(write);
4068 DECODE : ID;
4069 FPU : S5;
4070 %}
4071
4072 pipe_class fp_load_constant_s(fRegF dst)
4073 %{
4074 single_instruction;
4075 dst : S5(write);
4076 DECODE : ID;
4077 FPU : S5;
4078 %}
4079
4080 pipe_class fp_load_constant_d(fRegD dst)
4081 %{
4082 single_instruction;
4083 dst : S5(write);
4084 DECODE : ID;
4085 FPU : S5;
4086 %}
4087
4088 pipe_class fp_load_mem_s(fRegF dst, memory mem)
4089 %{
4090 single_instruction;
4091 mem : S1(read);
4092 dst : S5(write);
4093 DECODE : ID;
4094 LDST : MEM;
4095 %}
4096
4097 pipe_class fp_load_mem_d(fRegD dst, memory mem)
4098 %{
4099 single_instruction;
4100 mem : S1(read);
4101 dst : S5(write);
4102 DECODE : ID;
4103 LDST : MEM;
4104 %}
4105
4106 pipe_class fp_store_reg_s(fRegF src, memory mem)
4107 %{
4108 single_instruction;
4109 src : S1(read);
4110 mem : S5(write);
4111 DECODE : ID;
4112 LDST : MEM;
4113 %}
4114
4115 pipe_class fp_store_reg_d(fRegD src, memory mem)
4116 %{
4117 single_instruction;
4118 src : S1(read);
4119 mem : S5(write);
4120 DECODE : ID;
4121 LDST : MEM;
4122 %}
4123
4124 //------- Integer ALU operations --------------------------
4125
4126 // Integer ALU reg-reg operation
4127 // Operands needs in ID, result generated in EX
4128 // E.g. ADD Rd, Rs1, Rs2
4129 pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2)
4130 %{
4131 single_instruction;
4132 dst : EX(write);
4133 src1 : ID(read);
4134 src2 : ID(read);
4135 DECODE : ID;
4136 ALU : EX;
4137 %}
4138
4139 // Integer ALU reg operation with constant shift
4140 // E.g. SLLI Rd, Rs1, #shift
4141 pipe_class ialu_reg_shift(iRegI dst, iRegI src1)
4142 %{
4143 single_instruction;
4144 dst : EX(write);
4145 src1 : ID(read);
4146 DECODE : ID;
4147 ALU : EX;
4148 %}
4149
4150 // Integer ALU reg-reg operation with variable shift
4151 // both operands must be available in ID
4152 // E.g. SLL Rd, Rs1, Rs2
4153 pipe_class ialu_reg_reg_vshift(iRegI dst, iRegI src1, iRegI src2)
4154 %{
4155 single_instruction;
4156 dst : EX(write);
4157 src1 : ID(read);
4158 src2 : ID(read);
4159 DECODE : ID;
4160 ALU : EX;
4161 %}
4162
4163 // Integer ALU reg operation
4164 // E.g. NEG Rd, Rs2
4165 pipe_class ialu_reg(iRegI dst, iRegI src)
4166 %{
4167 single_instruction;
4168 dst : EX(write);
4169 src : ID(read);
4170 DECODE : ID;
4171 ALU : EX;
4172 %}
4173
4174 // Integer ALU reg immediate operation
4175 // E.g. ADDI Rd, Rs1, #imm
4176 pipe_class ialu_reg_imm(iRegI dst, iRegI src1)
4177 %{
4178 single_instruction;
4179 dst : EX(write);
4180 src1 : ID(read);
4181 DECODE : ID;
4182 ALU : EX;
4183 %}
4184
4185 // Integer ALU immediate operation (no source operands)
4186 // E.g. LI Rd, #imm
4187 pipe_class ialu_imm(iRegI dst)
4188 %{
4189 single_instruction;
4190 dst : EX(write);
4191 DECODE : ID;
4192 ALU : EX;
4193 %}
4194
4195 //------- Multiply pipeline operations --------------------
4196
4197 // Multiply reg-reg
4198 // E.g. MULW Rd, Rs1, Rs2
4199 pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2)
4200 %{
4201 single_instruction;
4202 dst : WR(write);
4203 src1 : ID(read);
4204 src2 : ID(read);
4205 DECODE : ID;
4206 MUL : WR;
4207 %}
4208
4209 // E.g. MUL RD, Rs1, Rs2
4210 pipe_class lmul_reg_reg(iRegI dst, iRegI src1, iRegI src2)
4211 %{
4212 single_instruction;
4213 fixed_latency(3); // Maximum latency for 64 bit mul
4214 dst : WR(write);
4215 src1 : ID(read);
4216 src2 : ID(read);
4217 DECODE : ID;
4218 MUL : WR;
4219 %}
4220
4221 //------- Divide pipeline operations --------------------
4222
4223 // E.g. DIVW Rd, Rs1, Rs2
4224 pipe_class idiv_reg_reg(iRegI dst, iRegI src1, iRegI src2)
4225 %{
4226 single_instruction;
4227 fixed_latency(8); // Maximum latency for 32 bit divide
4228 dst : WR(write);
4229 src1 : ID(read);
4230 src2 : ID(read);
4231 DECODE : ID;
4232 DIV : WR;
4233 %}
4234
4235 // E.g. DIV RD, Rs1, Rs2
4236 pipe_class ldiv_reg_reg(iRegI dst, iRegI src1, iRegI src2)
4237 %{
4238 single_instruction;
4239 fixed_latency(16); // Maximum latency for 64 bit divide
4240 dst : WR(write);
4241 src1 : ID(read);
4242 src2 : ID(read);
4243 DECODE : ID;
4244 DIV : WR;
4245 %}
4246
4247 //------- Load pipeline operations ------------------------
4248
4249 // Load - reg, mem
4250 // E.g. LA Rd, mem
4251 pipe_class iload_reg_mem(iRegI dst, memory mem)
4252 %{
4253 single_instruction;
4254 dst : WR(write);
4255 mem : ID(read);
4256 DECODE : ID;
4257 LDST : MEM;
4258 %}
4259
4260 // Load - reg, reg
4261 // E.g. LD Rd, Rs
4262 pipe_class iload_reg_reg(iRegI dst, iRegI src)
4263 %{
4264 single_instruction;
4265 dst : WR(write);
4266 src : ID(read);
4267 DECODE : ID;
4268 LDST : MEM;
4269 %}
4270
4271 //------- Store pipeline operations -----------------------
4272
4273 // Store - zr, mem
4274 // E.g. SD zr, mem
4275 pipe_class istore_mem(memory mem)
4276 %{
4277 single_instruction;
4278 mem : ID(read);
4279 DECODE : ID;
4280 LDST : MEM;
4281 %}
4282
4283 // Store - reg, mem
4284 // E.g. SD Rs, mem
4285 pipe_class istore_reg_mem(iRegI src, memory mem)
4286 %{
4287 single_instruction;
4288 mem : ID(read);
4289 src : EX(read);
4290 DECODE : ID;
4291 LDST : MEM;
4292 %}
4293
4294 // Store - reg, reg
4295 // E.g. SD Rs2, Rs1
4296 pipe_class istore_reg_reg(iRegI dst, iRegI src)
4297 %{
4298 single_instruction;
4299 dst : ID(read);
4300 src : EX(read);
4301 DECODE : ID;
4302 LDST : MEM;
4303 %}
4304
4305 //------- Store pipeline operations -----------------------
4306
4307 // Branch
4308 pipe_class pipe_branch()
4309 %{
4310 single_instruction;
4311 DECODE : ID;
4312 BRANCH : EX;
4313 %}
4314
4315 // Branch
4316 pipe_class pipe_branch_reg(iRegI src)
4317 %{
4318 single_instruction;
4319 src : ID(read);
4320 DECODE : ID;
4321 BRANCH : EX;
4322 %}
4323
4324 // Compare & Branch
4325 // E.g. BEQ Rs1, Rs2, L
4326 pipe_class pipe_cmp_branch(iRegI src1, iRegI src2)
4327 %{
4328 single_instruction;
4329 src1 : ID(read);
4330 src2 : ID(read);
4331 DECODE : ID;
4332 BRANCH : EX;
4333 %}
4334
4335 // E.g. BEQZ Rs, L
4336 pipe_class pipe_cmpz_branch(iRegI src)
4337 %{
4338 single_instruction;
4339 src : ID(read);
4340 DECODE : ID;
4341 BRANCH : EX;
4342 %}
4343
4344 //------- Synchronisation operations ----------------------
4345 // Any operation requiring serialization
4346 // E.g. FENCE/Atomic Ops/Load Acquire/Store Release
4347 pipe_class pipe_serial()
4348 %{
4349 single_instruction;
4350 force_serialization;
4351 fixed_latency(16);
4352 DECODE : ID;
4353 LDST : MEM;
4354 %}
4355
4356 pipe_class pipe_slow()
4357 %{
4358 instruction_count(10);
4359 multiple_bundles;
4360 force_serialization;
4361 fixed_latency(16);
4362 DECODE : ID;
4363 LDST : MEM;
4364 %}
4365
4366 // Empty pipeline class
4367 pipe_class pipe_class_empty()
4368 %{
4369 single_instruction;
4370 fixed_latency(0);
4371 %}
4372
4373 // Default pipeline class.
4374 pipe_class pipe_class_default()
4375 %{
4376 single_instruction;
4377 fixed_latency(2);
4378 %}
4379
4380 // Pipeline class for compares.
4381 pipe_class pipe_class_compare()
4382 %{
4383 single_instruction;
4384 fixed_latency(16);
4385 %}
4386
4387 // Pipeline class for memory operations.
4388 pipe_class pipe_class_memory()
4389 %{
4390 single_instruction;
4391 fixed_latency(16);
4392 %}
4393
4394 // Pipeline class for call.
4395 pipe_class pipe_class_call()
4396 %{
4397 single_instruction;
4398 fixed_latency(100);
4399 %}
4400
4401 // Define the class for the Nop node.
4402 define %{
4403 MachNop = pipe_class_empty;
4404 %}
4405 %}
4406 //----------INSTRUCTIONS-------------------------------------------------------
4407 //
4408 // match -- States which machine-independent subtree may be replaced
4409 // by this instruction.
4410 // ins_cost -- The estimated cost of this instruction is used by instruction
4411 // selection to identify a minimum cost tree of machine
4412 // instructions that matches a tree of machine-independent
4413 // instructions.
4414 // format -- A string providing the disassembly for this instruction.
4415 // The value of an instruction's operand may be inserted
4416 // by referring to it with a '$' prefix.
4417 // opcode -- Three instruction opcodes may be provided. These are referred
4418 // to within an encode class as $primary, $secondary, and $tertiary
4419 // rrspectively. The primary opcode is commonly used to
4420 // indicate the type of machine instruction, while secondary
4421 // and tertiary are often used for prefix options or addressing
4422 // modes.
4423 // ins_encode -- A list of encode classes with parameters. The encode class
4424 // name must have been defined in an 'enc_class' specification
4425 // in the encode section of the architecture description.
4426
4427 // ============================================================================
4428 // Memory (Load/Store) Instructions
4429
4430 // Load Instructions
4431
4432 // Load Byte (8 bit signed)
4433 instruct loadB(iRegINoSp dst, memory mem)
4434 %{
4435 match(Set dst (LoadB mem));
4436
4437 ins_cost(LOAD_COST);
4438 format %{ "lb $dst, $mem\t# byte, #@loadB" %}
4439
4440 ins_encode %{
4441 __ lb(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4442 %}
4443
4444 ins_pipe(iload_reg_mem);
4445 %}
4446
4447 // Load Byte (8 bit signed) into long
4448 instruct loadB2L(iRegLNoSp dst, memory mem)
4449 %{
4450 match(Set dst (ConvI2L (LoadB mem)));
4451
4452 ins_cost(LOAD_COST);
4453 format %{ "lb $dst, $mem\t# byte, #@loadB2L" %}
4454
4455 ins_encode %{
4456 __ lb(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4457 %}
4458
4459 ins_pipe(iload_reg_mem);
4460 %}
4461
4462 // Load Byte (8 bit unsigned)
4463 instruct loadUB(iRegINoSp dst, memory mem)
4464 %{
4465 match(Set dst (LoadUB mem));
4466
4467 ins_cost(LOAD_COST);
4468 format %{ "lbu $dst, $mem\t# byte, #@loadUB" %}
4469
4470 ins_encode %{
4471 __ lbu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4472 %}
4473
4474 ins_pipe(iload_reg_mem);
4475 %}
4476
4477 // Load Byte (8 bit unsigned) into long
4478 instruct loadUB2L(iRegLNoSp dst, memory mem)
4479 %{
4480 match(Set dst (ConvI2L (LoadUB mem)));
4481
4482 ins_cost(LOAD_COST);
4483 format %{ "lbu $dst, $mem\t# byte, #@loadUB2L" %}
4484
4485 ins_encode %{
4486 __ lbu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4487 %}
4488
4489 ins_pipe(iload_reg_mem);
4490 %}
4491
4492 // Load Short (16 bit signed)
4493 instruct loadS(iRegINoSp dst, memory mem)
4494 %{
4495 match(Set dst (LoadS mem));
4496
4497 ins_cost(LOAD_COST);
4498 format %{ "lh $dst, $mem\t# short, #@loadS" %}
4499
4500 ins_encode %{
4501 __ lh(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4502 %}
4503
4504 ins_pipe(iload_reg_mem);
4505 %}
4506
4507 // Load Short (16 bit signed) into long
4508 instruct loadS2L(iRegLNoSp dst, memory mem)
4509 %{
4510 match(Set dst (ConvI2L (LoadS mem)));
4511
4512 ins_cost(LOAD_COST);
4513 format %{ "lh $dst, $mem\t# short, #@loadS2L" %}
4514
4515 ins_encode %{
4516 __ lh(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4517 %}
4518
4519 ins_pipe(iload_reg_mem);
4520 %}
4521
4522 // Load Char (16 bit unsigned)
4523 instruct loadUS(iRegINoSp dst, memory mem)
4524 %{
4525 match(Set dst (LoadUS mem));
4526
4527 ins_cost(LOAD_COST);
4528 format %{ "lhu $dst, $mem\t# short, #@loadUS" %}
4529
4530 ins_encode %{
4531 __ lhu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4532 %}
4533
4534 ins_pipe(iload_reg_mem);
4535 %}
4536
4537 // Load Short/Char (16 bit unsigned) into long
4538 instruct loadUS2L(iRegLNoSp dst, memory mem)
4539 %{
4540 match(Set dst (ConvI2L (LoadUS mem)));
4541
4542 ins_cost(LOAD_COST);
4543 format %{ "lhu $dst, $mem\t# short, #@loadUS2L" %}
4544
4545 ins_encode %{
4546 __ lhu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4547 %}
4548
4549 ins_pipe(iload_reg_mem);
4550 %}
4551
4552 // Load Integer (32 bit signed)
4553 instruct loadI(iRegINoSp dst, memory mem)
4554 %{
4555 match(Set dst (LoadI mem));
4556
4557 ins_cost(LOAD_COST);
4558 format %{ "lw $dst, $mem\t# int, #@loadI" %}
4559
4560 ins_encode %{
4561 Assembler::CompressibleRegion cr(&_masm);
4562 __ lw(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4563 %}
4564
4565 ins_pipe(iload_reg_mem);
4566 %}
4567
4568 // Load Integer (32 bit signed) into long
4569 instruct loadI2L(iRegLNoSp dst, memory mem)
4570 %{
4571 match(Set dst (ConvI2L (LoadI mem)));
4572
4573 ins_cost(LOAD_COST);
4574 format %{ "lw $dst, $mem\t# int, #@loadI2L" %}
4575
4576 ins_encode %{
4577 Assembler::CompressibleRegion cr(&_masm);
4578 __ lw(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4579 %}
4580
4581 ins_pipe(iload_reg_mem);
4582 %}
4583
4584 // Load Integer (32 bit unsigned) into long
4585 instruct loadUI2L(iRegLNoSp dst, memory mem, immL_32bits mask)
4586 %{
4587 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
4588
4589 ins_cost(LOAD_COST);
4590 format %{ "lwu $dst, $mem\t# int, #@loadUI2L" %}
4591
4592 ins_encode %{
4593 __ lwu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4594 %}
4595
4596 ins_pipe(iload_reg_mem);
4597 %}
4598
4599 // Load Long (64 bit signed)
4600 instruct loadL(iRegLNoSp dst, memory mem)
4601 %{
4602 match(Set dst (LoadL mem));
4603
4604 ins_cost(LOAD_COST);
4605 format %{ "ld $dst, $mem\t# int, #@loadL" %}
4606
4607 ins_encode %{
4608 Assembler::CompressibleRegion cr(&_masm);
4609 __ ld(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4610 %}
4611
4612 ins_pipe(iload_reg_mem);
4613 %}
4614
4615 // Load Range
4616 instruct loadRange(iRegINoSp dst, memory mem)
4617 %{
4618 match(Set dst (LoadRange mem));
4619
4620 ins_cost(LOAD_COST);
4621 format %{ "lwu $dst, $mem\t# range, #@loadRange" %}
4622
4623 ins_encode %{
4624 __ lwu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4625 %}
4626
4627 ins_pipe(iload_reg_mem);
4628 %}
4629
4630 // Load Pointer
4631 instruct loadP(iRegPNoSp dst, memory mem)
4632 %{
4633 match(Set dst (LoadP mem));
4634 predicate(n->as_Load()->barrier_data() == 0);
4635
4636 ins_cost(LOAD_COST);
4637 format %{ "ld $dst, $mem\t# ptr, #@loadP" %}
4638
4639 ins_encode %{
4640 Assembler::CompressibleRegion cr(&_masm);
4641 __ ld(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4642 %}
4643
4644 ins_pipe(iload_reg_mem);
4645 %}
4646
4647 // Load Compressed Pointer
4648 instruct loadN(iRegNNoSp dst, memory mem)
4649 %{
4650 match(Set dst (LoadN mem));
4651
4652 ins_cost(LOAD_COST);
4653 format %{ "lwu $dst, $mem\t# loadN, compressed ptr, #@loadN" %}
4654
4655 ins_encode %{
4656 __ lwu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4657 %}
4658
4659 ins_pipe(iload_reg_mem);
4660 %}
4661
4662 // Load Klass Pointer
4663 instruct loadKlass(iRegPNoSp dst, memory mem)
4664 %{
4665 match(Set dst (LoadKlass mem));
4666
4667 ins_cost(LOAD_COST);
4668 format %{ "ld $dst, $mem\t# class, #@loadKlass" %}
4669
4670 ins_encode %{
4671 Assembler::CompressibleRegion cr(&_masm);
4672 __ ld(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4673 %}
4674
4675 ins_pipe(iload_reg_mem);
4676 %}
4677
4678 // Load Narrow Klass Pointer
4679 instruct loadNKlass(iRegNNoSp dst, memory mem)
4680 %{
4681 match(Set dst (LoadNKlass mem));
4682
4683 ins_cost(LOAD_COST);
4684 format %{ "lwu $dst, $mem\t# loadNKlass, compressed class ptr, #@loadNKlass" %}
4685
4686 ins_encode %{
4687 __ lwu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4688 %}
4689
4690 ins_pipe(iload_reg_mem);
4691 %}
4692
4693 // Load Float
4694 instruct loadF(fRegF dst, memory mem)
4695 %{
4696 match(Set dst (LoadF mem));
4697
4698 ins_cost(LOAD_COST);
4699 format %{ "flw $dst, $mem\t# float, #@loadF" %}
4700
4701 ins_encode %{
4702 __ flw(as_FloatRegister($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4703 %}
4704
4705 ins_pipe(fp_load_mem_s);
4706 %}
4707
4708 // Load Double
4709 instruct loadD(fRegD dst, memory mem)
4710 %{
4711 match(Set dst (LoadD mem));
4712
4713 ins_cost(LOAD_COST);
4714 format %{ "fld $dst, $mem\t# double, #@loadD" %}
4715
4716 ins_encode %{
4717 Assembler::CompressibleRegion cr(&_masm);
4718 __ fld(as_FloatRegister($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4719 %}
4720
4721 ins_pipe(fp_load_mem_d);
4722 %}
4723
4724 // Load Int Constant
4725 instruct loadConI(iRegINoSp dst, immI src)
4726 %{
4727 match(Set dst src);
4728
4729 ins_cost(ALU_COST);
4730 format %{ "li $dst, $src\t# int, #@loadConI" %}
4731
4732 ins_encode(riscv_enc_li_imm(dst, src));
4733
4734 ins_pipe(ialu_imm);
4735 %}
4736
4737 // Load Long Constant
4738 instruct loadConL(iRegLNoSp dst, immL src)
4739 %{
4740 match(Set dst src);
4741
4742 ins_cost(ALU_COST);
4743 format %{ "li $dst, $src\t# long, #@loadConL" %}
4744
4745 ins_encode(riscv_enc_li_imm(dst, src));
4746
4747 ins_pipe(ialu_imm);
4748 %}
4749
4750 // Load Pointer Constant
4751 instruct loadConP(iRegPNoSp dst, immP con)
4752 %{
4753 match(Set dst con);
4754
4755 ins_cost(ALU_COST);
4756 format %{ "mv $dst, $con\t# ptr, #@loadConP" %}
4757
4758 ins_encode(riscv_enc_mov_p(dst, con));
4759
4760 ins_pipe(ialu_imm);
4761 %}
4762
4763 // Load Null Pointer Constant
4764 instruct loadConP0(iRegPNoSp dst, immP0 con)
4765 %{
4766 match(Set dst con);
4767
4768 ins_cost(ALU_COST);
4769 format %{ "mv $dst, $con\t# NULL ptr, #@loadConP0" %}
4770
4771 ins_encode(riscv_enc_mov_zero(dst));
4772
4773 ins_pipe(ialu_imm);
4774 %}
4775
4776 // Load Pointer Constant One
4777 instruct loadConP1(iRegPNoSp dst, immP_1 con)
4778 %{
4779 match(Set dst con);
4780
4781 ins_cost(ALU_COST);
4782 format %{ "mv $dst, $con\t# load ptr constant one, #@loadConP1" %}
4783
4784 ins_encode(riscv_enc_mov_p1(dst));
4785
4786 ins_pipe(ialu_imm);
4787 %}
4788
4789 // Load Byte Map Base Constant
4790 instruct loadByteMapBase(iRegPNoSp dst, immByteMapBase con)
4791 %{
4792 match(Set dst con);
4793 ins_cost(ALU_COST);
4794 format %{ "mv $dst, $con\t# Byte Map Base, #@loadByteMapBase" %}
4795
4796 ins_encode(riscv_enc_mov_byte_map_base(dst));
4797
4798 ins_pipe(ialu_imm);
4799 %}
4800
4801 // Load Narrow Pointer Constant
4802 instruct loadConN(iRegNNoSp dst, immN con)
4803 %{
4804 match(Set dst con);
4805
4806 ins_cost(ALU_COST * 4);
4807 format %{ "mv $dst, $con\t# compressed ptr, #@loadConN" %}
4808
4809 ins_encode(riscv_enc_mov_n(dst, con));
4810
4811 ins_pipe(ialu_imm);
4812 %}
4813
4814 // Load Narrow Null Pointer Constant
4815 instruct loadConN0(iRegNNoSp dst, immN0 con)
4816 %{
4817 match(Set dst con);
4818
4819 ins_cost(ALU_COST);
4820 format %{ "mv $dst, $con\t# compressed NULL ptr, #@loadConN0" %}
4821
4822 ins_encode(riscv_enc_mov_zero(dst));
4823
4824 ins_pipe(ialu_imm);
4825 %}
4826
4827 // Load Narrow Klass Constant
4828 instruct loadConNKlass(iRegNNoSp dst, immNKlass con)
4829 %{
4830 match(Set dst con);
4831
4832 ins_cost(ALU_COST * 6);
4833 format %{ "mv $dst, $con\t# compressed klass ptr, #@loadConNKlass" %}
4834
4835 ins_encode(riscv_enc_mov_nk(dst, con));
4836
4837 ins_pipe(ialu_imm);
4838 %}
4839
4840 // Load Float Constant
4841 instruct loadConF(fRegF dst, immF con) %{
4842 match(Set dst con);
4843
4844 ins_cost(LOAD_COST);
4845 format %{
4846 "flw $dst, [$constantaddress]\t# load from constant table: float=$con, #@loadConF"
4847 %}
4848
4849 ins_encode %{
4850 __ flw(as_FloatRegister($dst$$reg), $constantaddress($con));
4851 %}
4852
4853 ins_pipe(fp_load_constant_s);
4854 %}
4855
4856 instruct loadConF0(fRegF dst, immF0 con) %{
4857 match(Set dst con);
4858
4859 ins_cost(XFER_COST);
4860
4861 format %{ "fmv.w.x $dst, zr\t# float, #@loadConF0" %}
4862
4863 ins_encode %{
4864 __ fmv_w_x(as_FloatRegister($dst$$reg), zr);
4865 %}
4866
4867 ins_pipe(fp_load_constant_s);
4868 %}
4869
4870 // Load Double Constant
4871 instruct loadConD(fRegD dst, immD con) %{
4872 match(Set dst con);
4873
4874 ins_cost(LOAD_COST);
4875 format %{
4876 "fld $dst, [$constantaddress]\t# load from constant table: double=$con, #@loadConD"
4877 %}
4878
4879 ins_encode %{
4880 __ fld(as_FloatRegister($dst$$reg), $constantaddress($con));
4881 %}
4882
4883 ins_pipe(fp_load_constant_d);
4884 %}
4885
4886 instruct loadConD0(fRegD dst, immD0 con) %{
4887 match(Set dst con);
4888
4889 ins_cost(XFER_COST);
4890
4891 format %{ "fmv.d.x $dst, zr\t# double, #@loadConD0" %}
4892
4893 ins_encode %{
4894 __ fmv_d_x(as_FloatRegister($dst$$reg), zr);
4895 %}
4896
4897 ins_pipe(fp_load_constant_d);
4898 %}
4899
4900 // Store Instructions
4901 // Store CMS card-mark Immediate
4902 instruct storeimmCM0(immI0 zero, memory mem)
4903 %{
4904 match(Set mem (StoreCM mem zero));
4905
4906 ins_cost(STORE_COST);
4907 format %{ "storestore (elided)\n\t"
4908 "sb zr, $mem\t# byte, #@storeimmCM0" %}
4909
4910 ins_encode %{
4911 __ sb(zr, Address(as_Register($mem$$base), $mem$$disp));
4912 %}
4913
4914 ins_pipe(istore_mem);
4915 %}
4916
4917 // Store CMS card-mark Immediate with intervening StoreStore
4918 // needed when using CMS with no conditional card marking
4919 instruct storeimmCM0_ordered(immI0 zero, memory mem)
4920 %{
4921 match(Set mem (StoreCM mem zero));
4922
4923 ins_cost(ALU_COST + STORE_COST);
4924 format %{ "membar(StoreStore)\n\t"
4925 "sb zr, $mem\t# byte, #@storeimmCM0_ordered" %}
4926
4927 ins_encode %{
4928 __ membar(MacroAssembler::LoadStore | MacroAssembler::StoreStore);
4929 __ sb(zr, Address(as_Register($mem$$base), $mem$$disp));
4930 %}
4931
4932 ins_pipe(istore_mem);
4933 %}
4934
4935 // Store Byte
4936 instruct storeB(iRegIorL2I src, memory mem)
4937 %{
4938 match(Set mem (StoreB mem src));
4939
4940 ins_cost(STORE_COST);
4941 format %{ "sb $src, $mem\t# byte, #@storeB" %}
4942
4943 ins_encode %{
4944 __ sb(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
4945 %}
4946
4947 ins_pipe(istore_reg_mem);
4948 %}
4949
4950 instruct storeimmB0(immI0 zero, memory mem)
4951 %{
4952 match(Set mem (StoreB mem zero));
4953
4954 ins_cost(STORE_COST);
4955 format %{ "sb zr, $mem\t# byte, #@storeimmB0" %}
4956
4957 ins_encode %{
4958 __ sb(zr, Address(as_Register($mem$$base), $mem$$disp));
4959 %}
4960
4961 ins_pipe(istore_mem);
4962 %}
4963
4964 // Store Char/Short
4965 instruct storeC(iRegIorL2I src, memory mem)
4966 %{
4967 match(Set mem (StoreC mem src));
4968
4969 ins_cost(STORE_COST);
4970 format %{ "sh $src, $mem\t# short, #@storeC" %}
4971
4972 ins_encode %{
4973 __ sh(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
4974 %}
4975
4976 ins_pipe(istore_reg_mem);
4977 %}
4978
4979 instruct storeimmC0(immI0 zero, memory mem)
4980 %{
4981 match(Set mem (StoreC mem zero));
4982
4983 ins_cost(STORE_COST);
4984 format %{ "sh zr, $mem\t# short, #@storeimmC0" %}
4985
4986 ins_encode %{
4987 __ sh(zr, Address(as_Register($mem$$base), $mem$$disp));
4988 %}
4989
4990 ins_pipe(istore_mem);
4991 %}
4992
4993 // Store Integer
4994 instruct storeI(iRegIorL2I src, memory mem)
4995 %{
4996 match(Set mem(StoreI mem src));
4997
4998 ins_cost(STORE_COST);
4999 format %{ "sw $src, $mem\t# int, #@storeI" %}
5000
5001 ins_encode %{
5002 Assembler::CompressibleRegion cr(&_masm);
5003 __ sw(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5004 %}
5005
5006 ins_pipe(istore_reg_mem);
5007 %}
5008
5009 instruct storeimmI0(immI0 zero, memory mem)
5010 %{
5011 match(Set mem(StoreI mem zero));
5012
5013 ins_cost(STORE_COST);
5014 format %{ "sw zr, $mem\t# int, #@storeimmI0" %}
5015
5016 ins_encode %{
5017 __ sw(zr, Address(as_Register($mem$$base), $mem$$disp));
5018 %}
5019
5020 ins_pipe(istore_mem);
5021 %}
5022
5023 // Store Long (64 bit signed)
5024 instruct storeL(iRegL src, memory mem)
5025 %{
5026 match(Set mem (StoreL mem src));
5027
5028 ins_cost(STORE_COST);
5029 format %{ "sd $src, $mem\t# long, #@storeL" %}
5030
5031 ins_encode %{
5032 Assembler::CompressibleRegion cr(&_masm);
5033 __ sd(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5034 %}
5035
5036 ins_pipe(istore_reg_mem);
5037 %}
5038
5039 // Store Long (64 bit signed)
5040 instruct storeimmL0(immL0 zero, memory mem)
5041 %{
5042 match(Set mem (StoreL mem zero));
5043
5044 ins_cost(STORE_COST);
5045 format %{ "sd zr, $mem\t# long, #@storeimmL0" %}
5046
5047 ins_encode %{
5048 __ sd(zr, Address(as_Register($mem$$base), $mem$$disp));
5049 %}
5050
5051 ins_pipe(istore_mem);
5052 %}
5053
5054 // Store Pointer
5055 instruct storeP(iRegP src, memory mem)
5056 %{
5057 match(Set mem (StoreP mem src));
5058
5059 ins_cost(STORE_COST);
5060 format %{ "sd $src, $mem\t# ptr, #@storeP" %}
5061
5062 ins_encode %{
5063 Assembler::CompressibleRegion cr(&_masm);
5064 __ sd(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5065 %}
5066
5067 ins_pipe(istore_reg_mem);
5068 %}
5069
5070 // Store Pointer
5071 instruct storeimmP0(immP0 zero, memory mem)
5072 %{
5073 match(Set mem (StoreP mem zero));
5074
5075 ins_cost(STORE_COST);
5076 format %{ "sd zr, $mem\t# ptr, #@storeimmP0" %}
5077
5078 ins_encode %{
5079 __ sd(zr, Address(as_Register($mem$$base), $mem$$disp));
5080 %}
5081
5082 ins_pipe(istore_mem);
5083 %}
5084
5085 // Store Compressed Pointer
5086 instruct storeN(iRegN src, memory mem)
5087 %{
5088 match(Set mem (StoreN mem src));
5089
5090 ins_cost(STORE_COST);
5091 format %{ "sw $src, $mem\t# compressed ptr, #@storeN" %}
5092
5093 ins_encode %{
5094 Assembler::CompressibleRegion cr(&_masm);
5095 __ sw(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5096 %}
5097
5098 ins_pipe(istore_reg_mem);
5099 %}
5100
5101 instruct storeImmN0(iRegIHeapbase heapbase, immN0 zero, memory mem)
5102 %{
5103 match(Set mem (StoreN mem zero));
5104
5105 ins_cost(STORE_COST);
5106 format %{ "sw rheapbase, $mem\t# compressed ptr (rheapbase==0), #@storeImmN0" %}
5107
5108 ins_encode %{
5109 __ sw(as_Register($heapbase$$reg), Address(as_Register($mem$$base), $mem$$disp));
5110 %}
5111
5112 ins_pipe(istore_reg_mem);
5113 %}
5114
5115 // Store Float
5116 instruct storeF(fRegF src, memory mem)
5117 %{
5118 match(Set mem (StoreF mem src));
5119
5120 ins_cost(STORE_COST);
5121 format %{ "fsw $src, $mem\t# float, #@storeF" %}
5122
5123 ins_encode %{
5124 __ fsw(as_FloatRegister($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5125 %}
5126
5127 ins_pipe(fp_store_reg_s);
5128 %}
5129
5130 // Store Double
5131 instruct storeD(fRegD src, memory mem)
5132 %{
5133 match(Set mem (StoreD mem src));
5134
5135 ins_cost(STORE_COST);
5136 format %{ "fsd $src, $mem\t# double, #@storeD" %}
5137
5138 ins_encode %{
5139 Assembler::CompressibleRegion cr(&_masm);
5140 __ fsd(as_FloatRegister($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5141 %}
5142
5143 ins_pipe(fp_store_reg_d);
5144 %}
5145
5146 // Store Compressed Klass Pointer
5147 instruct storeNKlass(iRegN src, memory mem)
5148 %{
5149 match(Set mem (StoreNKlass mem src));
5150
5151 ins_cost(STORE_COST);
5152 format %{ "sw $src, $mem\t# compressed klass ptr, #@storeNKlass" %}
5153
5154 ins_encode %{
5155 Assembler::CompressibleRegion cr(&_masm);
5156 __ sw(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5157 %}
5158
5159 ins_pipe(istore_reg_mem);
5160 %}
5161
5162 // ============================================================================
5163 // Atomic operation instructions
5164 //
5165
5166 // standard CompareAndSwapX when we are using barriers
5167 // these have higher priority than the rules selected by a predicate
5168 instruct compareAndSwapB(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5169 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5170 %{
5171 match(Set res (CompareAndSwapB mem (Binary oldval newval)));
5172
5173 ins_cost(LOAD_COST + STORE_COST + ALU_COST * 10 + BRANCH_COST * 4);
5174
5175 effect(TEMP_DEF res, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3, KILL cr);
5176
5177 format %{
5178 "cmpxchg $mem, $oldval, $newval\t# (byte) if $mem == $oldval then $mem <-- $newval\n\t"
5179 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapB"
5180 %}
5181
5182 ins_encode %{
5183 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5184 Assembler::relaxed /* acquire */, Assembler::rl /* release */, $res$$Register,
5185 true /* result as bool */, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5186 %}
5187
5188 ins_pipe(pipe_slow);
5189 %}
5190
5191 instruct compareAndSwapS(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5192 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5193 %{
5194 match(Set res (CompareAndSwapS mem (Binary oldval newval)));
5195
5196 ins_cost(LOAD_COST + STORE_COST + ALU_COST * 11 + BRANCH_COST * 4);
5197
5198 effect(TEMP_DEF res, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3, KILL cr);
5199
5200 format %{
5201 "cmpxchg $mem, $oldval, $newval\t# (short) if $mem == $oldval then $mem <-- $newval\n\t"
5202 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapS"
5203 %}
5204
5205 ins_encode %{
5206 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5207 Assembler::relaxed /* acquire */, Assembler::rl /* release */, $res$$Register,
5208 true /* result as bool */, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5209 %}
5210
5211 ins_pipe(pipe_slow);
5212 %}
5213
5214 instruct compareAndSwapI(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5215 %{
5216 match(Set res (CompareAndSwapI mem (Binary oldval newval)));
5217
5218 ins_cost(LOAD_COST + STORE_COST + ALU_COST * 6 + BRANCH_COST * 4);
5219
5220 format %{
5221 "cmpxchg $mem, $oldval, $newval\t# (int) if $mem == $oldval then $mem <-- $newval\n\t"
5222 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapI"
5223 %}
5224
5225 ins_encode(riscv_enc_cmpxchgw(res, mem, oldval, newval));
5226
5227 ins_pipe(pipe_slow);
5228 %}
5229
5230 instruct compareAndSwapL(iRegINoSp res, indirect mem, iRegL oldval, iRegL newval)
5231 %{
5232 match(Set res (CompareAndSwapL mem (Binary oldval newval)));
5233
5234 ins_cost(LOAD_COST + STORE_COST + ALU_COST * 6 + BRANCH_COST * 4);
5235
5236 format %{
5237 "cmpxchg $mem, $oldval, $newval\t# (long) if $mem == $oldval then $mem <-- $newval\n\t"
5238 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapL"
5239 %}
5240
5241 ins_encode(riscv_enc_cmpxchg(res, mem, oldval, newval));
5242
5243 ins_pipe(pipe_slow);
5244 %}
5245
5246 instruct compareAndSwapP(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval)
5247 %{
5248 predicate(n->as_LoadStore()->barrier_data() == 0);
5249
5250 match(Set res (CompareAndSwapP mem (Binary oldval newval)));
5251
5252 ins_cost(LOAD_COST + STORE_COST + ALU_COST * 6 + BRANCH_COST * 4);
5253
5254 format %{
5255 "cmpxchg $mem, $oldval, $newval\t# (ptr) if $mem == $oldval then $mem <-- $newval\n\t"
5256 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapP"
5257 %}
5258
5259 ins_encode(riscv_enc_cmpxchg(res, mem, oldval, newval));
5260
5261 ins_pipe(pipe_slow);
5262 %}
5263
5264 instruct compareAndSwapN(iRegINoSp res, indirect mem, iRegN oldval, iRegN newval)
5265 %{
5266 match(Set res (CompareAndSwapN mem (Binary oldval newval)));
5267
5268 ins_cost(LOAD_COST + STORE_COST + ALU_COST * 8 + BRANCH_COST * 4);
5269
5270 format %{
5271 "cmpxchg $mem, $oldval, $newval\t# (narrow oop) if $mem == $oldval then $mem <-- $newval\n\t"
5272 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapN"
5273 %}
5274
5275 ins_encode(riscv_enc_cmpxchgn(res, mem, oldval, newval));
5276
5277 ins_pipe(pipe_slow);
5278 %}
5279
5280 // alternative CompareAndSwapX when we are eliding barriers
5281 instruct compareAndSwapBAcq(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5282 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5283 %{
5284 predicate(needs_acquiring_load_reserved(n));
5285
5286 match(Set res (CompareAndSwapB mem (Binary oldval newval)));
5287
5288 ins_cost(LOAD_COST + STORE_COST + ALU_COST * 10 + BRANCH_COST * 4);
5289
5290 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5291
5292 format %{
5293 "cmpxchg_acq $mem, $oldval, $newval\t# (byte) if $mem == $oldval then $mem <-- $newval\n\t"
5294 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapBAcq"
5295 %}
5296
5297 ins_encode %{
5298 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5299 Assembler::aq /* acquire */, Assembler::rl /* release */, $res$$Register,
5300 true /* result as bool */, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5301 %}
5302
5303 ins_pipe(pipe_slow);
5304 %}
5305
5306 instruct compareAndSwapSAcq(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5307 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5308 %{
5309 predicate(needs_acquiring_load_reserved(n));
5310
5311 match(Set res (CompareAndSwapS mem (Binary oldval newval)));
5312
5313 ins_cost(LOAD_COST + STORE_COST + ALU_COST * 11 + BRANCH_COST * 4);
5314
5315 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5316
5317 format %{
5318 "cmpxchg_acq $mem, $oldval, $newval\t# (short) if $mem == $oldval then $mem <-- $newval\n\t"
5319 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapSAcq"
5320 %}
5321
5322 ins_encode %{
5323 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5324 Assembler::aq /* acquire */, Assembler::rl /* release */, $res$$Register,
5325 true /* result as bool */, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5326 %}
5327
5328 ins_pipe(pipe_slow);
5329 %}
5330
5331 instruct compareAndSwapIAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5332 %{
5333 predicate(needs_acquiring_load_reserved(n));
5334
5335 match(Set res (CompareAndSwapI mem (Binary oldval newval)));
5336
5337 ins_cost(LOAD_COST + STORE_COST + ALU_COST * 6 + BRANCH_COST * 4);
5338
5339 format %{
5340 "cmpxchg_acq $mem, $oldval, $newval\t# (int) if $mem == $oldval then $mem <-- $newval\n\t"
5341 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapIAcq"
5342 %}
5343
5344 ins_encode(riscv_enc_cmpxchgw_acq(res, mem, oldval, newval));
5345
5346 ins_pipe(pipe_slow);
5347 %}
5348
5349 instruct compareAndSwapLAcq(iRegINoSp res, indirect mem, iRegL oldval, iRegL newval)
5350 %{
5351 predicate(needs_acquiring_load_reserved(n));
5352
5353 match(Set res (CompareAndSwapL mem (Binary oldval newval)));
5354
5355 ins_cost(LOAD_COST + STORE_COST + ALU_COST * 6 + BRANCH_COST * 4);
5356
5357 format %{
5358 "cmpxchg_acq $mem, $oldval, $newval\t# (long) if $mem == $oldval then $mem <-- $newval\n\t"
5359 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapLAcq"
5360 %}
5361
5362 ins_encode(riscv_enc_cmpxchg_acq(res, mem, oldval, newval));
5363
5364 ins_pipe(pipe_slow);
5365 %}
5366
5367 instruct compareAndSwapPAcq(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval)
5368 %{
5369 predicate(needs_acquiring_load_reserved(n) && (n->as_LoadStore()->barrier_data() == 0));
5370
5371 match(Set res (CompareAndSwapP mem (Binary oldval newval)));
5372
5373 ins_cost(LOAD_COST + STORE_COST + ALU_COST * 6 + BRANCH_COST * 4);
5374
5375 format %{
5376 "cmpxchg_acq $mem, $oldval, $newval\t# (ptr) if $mem == $oldval then $mem <-- $newval\n\t"
5377 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapPAcq"
5378 %}
5379
5380 ins_encode(riscv_enc_cmpxchg_acq(res, mem, oldval, newval));
5381
5382 ins_pipe(pipe_slow);
5383 %}
5384
5385 instruct compareAndSwapNAcq(iRegINoSp res, indirect mem, iRegN oldval, iRegN newval)
5386 %{
5387 predicate(needs_acquiring_load_reserved(n));
5388
5389 match(Set res (CompareAndSwapN mem (Binary oldval newval)));
5390
5391 ins_cost(LOAD_COST + STORE_COST + ALU_COST * 8 + BRANCH_COST * 4);
5392
5393 format %{
5394 "cmpxchg_acq $mem, $oldval, $newval\t# (narrow oop) if $mem == $oldval then $mem <-- $newval\n\t"
5395 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapNAcq"
5396 %}
5397
5398 ins_encode(riscv_enc_cmpxchgn_acq(res, mem, oldval, newval));
5399
5400 ins_pipe(pipe_slow);
5401 %}
5402
5403 // Sundry CAS operations. Note that release is always true,
5404 // regardless of the memory ordering of the CAS. This is because we
5405 // need the volatile case to be sequentially consistent but there is
5406 // no trailing StoreLoad barrier emitted by C2. Unfortunately we
5407 // can't check the type of memory ordering here, so we always emit a
5408 // sc_d(w) with rl bit set.
5409 instruct compareAndExchangeB(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5410 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5411 %{
5412 match(Set res (CompareAndExchangeB mem (Binary oldval newval)));
5413
5414 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST * 5);
5415
5416 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5417
5418 format %{
5419 "cmpxchg $res = $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeB"
5420 %}
5421
5422 ins_encode %{
5423 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5424 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
5425 /*result_as_bool*/ false, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5426 %}
5427
5428 ins_pipe(pipe_slow);
5429 %}
5430
5431 instruct compareAndExchangeS(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5432 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5433 %{
5434 match(Set res (CompareAndExchangeS mem (Binary oldval newval)));
5435
5436 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST * 6);
5437
5438 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5439
5440 format %{
5441 "cmpxchg $res = $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeS"
5442 %}
5443
5444 ins_encode %{
5445 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5446 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
5447 /*result_as_bool*/ false, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5448 %}
5449
5450 ins_pipe(pipe_slow);
5451 %}
5452
5453 instruct compareAndExchangeI(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5454 %{
5455 match(Set res (CompareAndExchangeI mem (Binary oldval newval)));
5456
5457 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST);
5458
5459 effect(TEMP_DEF res);
5460
5461 format %{
5462 "cmpxchg $res = $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeI"
5463 %}
5464
5465 ins_encode %{
5466 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
5467 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5468 %}
5469
5470 ins_pipe(pipe_slow);
5471 %}
5472
5473 instruct compareAndExchangeL(iRegLNoSp res, indirect mem, iRegL oldval, iRegL newval)
5474 %{
5475 match(Set res (CompareAndExchangeL mem (Binary oldval newval)));
5476
5477 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST);
5478
5479 effect(TEMP_DEF res);
5480
5481 format %{
5482 "cmpxchg $res = $mem, $oldval, $newval\t# (long, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeL"
5483 %}
5484
5485 ins_encode %{
5486 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5487 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5488 %}
5489
5490 ins_pipe(pipe_slow);
5491 %}
5492
5493 instruct compareAndExchangeN(iRegNNoSp res, indirect mem, iRegN oldval, iRegN newval)
5494 %{
5495 match(Set res (CompareAndExchangeN mem (Binary oldval newval)));
5496
5497 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST * 3);
5498
5499 effect(TEMP_DEF res);
5500
5501 format %{
5502 "cmpxchg $res = $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeN"
5503 %}
5504
5505 ins_encode %{
5506 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
5507 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5508 %}
5509
5510 ins_pipe(pipe_slow);
5511 %}
5512
5513 instruct compareAndExchangeP(iRegPNoSp res, indirect mem, iRegP oldval, iRegP newval)
5514 %{
5515 predicate(n->as_LoadStore()->barrier_data() == 0);
5516 match(Set res (CompareAndExchangeP mem (Binary oldval newval)));
5517
5518 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST);
5519
5520 effect(TEMP_DEF res);
5521
5522 format %{
5523 "cmpxchg $res = $mem, $oldval, $newval\t# (ptr, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeP"
5524 %}
5525
5526 ins_encode %{
5527 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5528 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5529 %}
5530
5531 ins_pipe(pipe_slow);
5532 %}
5533
5534 instruct compareAndExchangeBAcq(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5535 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5536 %{
5537 predicate(needs_acquiring_load_reserved(n));
5538
5539 match(Set res (CompareAndExchangeB mem (Binary oldval newval)));
5540
5541 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST * 5);
5542
5543 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5544
5545 format %{
5546 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeBAcq"
5547 %}
5548
5549 ins_encode %{
5550 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5551 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
5552 /*result_as_bool*/ false, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5553 %}
5554
5555 ins_pipe(pipe_slow);
5556 %}
5557
5558 instruct compareAndExchangeSAcq(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5559 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5560 %{
5561 predicate(needs_acquiring_load_reserved(n));
5562
5563 match(Set res (CompareAndExchangeS mem (Binary oldval newval)));
5564
5565 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST * 6);
5566
5567 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5568
5569 format %{
5570 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeSAcq"
5571 %}
5572
5573 ins_encode %{
5574 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5575 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
5576 /*result_as_bool*/ false, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5577 %}
5578
5579 ins_pipe(pipe_slow);
5580 %}
5581
5582 instruct compareAndExchangeIAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5583 %{
5584 predicate(needs_acquiring_load_reserved(n));
5585
5586 match(Set res (CompareAndExchangeI mem (Binary oldval newval)));
5587
5588 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST);
5589
5590 effect(TEMP_DEF res);
5591
5592 format %{
5593 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeIAcq"
5594 %}
5595
5596 ins_encode %{
5597 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
5598 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
5599 %}
5600
5601 ins_pipe(pipe_slow);
5602 %}
5603
5604 instruct compareAndExchangeLAcq(iRegLNoSp res, indirect mem, iRegL oldval, iRegL newval)
5605 %{
5606 predicate(needs_acquiring_load_reserved(n));
5607
5608 match(Set res (CompareAndExchangeL mem (Binary oldval newval)));
5609
5610 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST);
5611
5612 effect(TEMP_DEF res);
5613
5614 format %{
5615 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (long, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeLAcq"
5616 %}
5617
5618 ins_encode %{
5619 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5620 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
5621 %}
5622
5623 ins_pipe(pipe_slow);
5624 %}
5625
5626 instruct compareAndExchangeNAcq(iRegNNoSp res, indirect mem, iRegN oldval, iRegN newval)
5627 %{
5628 predicate(needs_acquiring_load_reserved(n));
5629
5630 match(Set res (CompareAndExchangeN mem (Binary oldval newval)));
5631
5632 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST);
5633
5634 effect(TEMP_DEF res);
5635
5636 format %{
5637 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeNAcq"
5638 %}
5639
5640 ins_encode %{
5641 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
5642 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
5643 %}
5644
5645 ins_pipe(pipe_slow);
5646 %}
5647
5648 instruct compareAndExchangePAcq(iRegPNoSp res, indirect mem, iRegP oldval, iRegP newval)
5649 %{
5650 predicate(needs_acquiring_load_reserved(n) && (n->as_LoadStore()->barrier_data() == 0));
5651
5652 match(Set res (CompareAndExchangeP mem (Binary oldval newval)));
5653
5654 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST);
5655
5656 effect(TEMP_DEF res);
5657
5658 format %{
5659 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (ptr, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangePAcq"
5660 %}
5661
5662 ins_encode %{
5663 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5664 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
5665 %}
5666
5667 ins_pipe(pipe_slow);
5668 %}
5669
5670 instruct weakCompareAndSwapB(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5671 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5672 %{
5673 match(Set res (WeakCompareAndSwapB mem (Binary oldval newval)));
5674
5675 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 6);
5676
5677 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5678
5679 format %{
5680 "cmpxchg_weak $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5681 "# $res == 1 when success, #@weakCompareAndSwapB"
5682 %}
5683
5684 ins_encode %{
5685 __ weak_cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5686 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
5687 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5688 %}
5689
5690 ins_pipe(pipe_slow);
5691 %}
5692
5693 instruct weakCompareAndSwapS(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5694 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5695 %{
5696 match(Set res (WeakCompareAndSwapS mem (Binary oldval newval)));
5697
5698 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 7);
5699
5700 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5701
5702 format %{
5703 "cmpxchg_weak $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5704 "# $res == 1 when success, #@weakCompareAndSwapS"
5705 %}
5706
5707 ins_encode %{
5708 __ weak_cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5709 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
5710 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5711 %}
5712
5713 ins_pipe(pipe_slow);
5714 %}
5715
5716 instruct weakCompareAndSwapI(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5717 %{
5718 match(Set res (WeakCompareAndSwapI mem (Binary oldval newval)));
5719
5720 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 2);
5721
5722 format %{
5723 "cmpxchg_weak $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5724 "# $res == 1 when success, #@weakCompareAndSwapI"
5725 %}
5726
5727 ins_encode %{
5728 __ cmpxchg_weak(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
5729 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5730 %}
5731
5732 ins_pipe(pipe_slow);
5733 %}
5734
5735 instruct weakCompareAndSwapL(iRegINoSp res, indirect mem, iRegL oldval, iRegL newval)
5736 %{
5737 match(Set res (WeakCompareAndSwapL mem (Binary oldval newval)));
5738
5739 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 2);
5740
5741 format %{
5742 "cmpxchg_weak $mem, $oldval, $newval\t# (long, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5743 "# $res == 1 when success, #@weakCompareAndSwapL"
5744 %}
5745
5746 ins_encode %{
5747 __ cmpxchg_weak(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5748 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5749 %}
5750
5751 ins_pipe(pipe_slow);
5752 %}
5753
5754 instruct weakCompareAndSwapN(iRegINoSp res, indirect mem, iRegN oldval, iRegN newval)
5755 %{
5756 match(Set res (WeakCompareAndSwapN mem (Binary oldval newval)));
5757
5758 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 4);
5759
5760 format %{
5761 "cmpxchg_weak $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5762 "# $res == 1 when success, #@weakCompareAndSwapN"
5763 %}
5764
5765 ins_encode %{
5766 __ cmpxchg_weak(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
5767 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5768 %}
5769
5770 ins_pipe(pipe_slow);
5771 %}
5772
5773 instruct weakCompareAndSwapP(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval)
5774 %{
5775 predicate(n->as_LoadStore()->barrier_data() == 0);
5776 match(Set res (WeakCompareAndSwapP mem (Binary oldval newval)));
5777
5778 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 2);
5779
5780 format %{
5781 "cmpxchg_weak $mem, $oldval, $newval\t# (ptr, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5782 "# $res == 1 when success, #@weakCompareAndSwapP"
5783 %}
5784
5785 ins_encode %{
5786 __ cmpxchg_weak(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5787 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5788 %}
5789
5790 ins_pipe(pipe_slow);
5791 %}
5792
5793 instruct weakCompareAndSwapBAcq(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5794 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5795 %{
5796 predicate(needs_acquiring_load_reserved(n));
5797
5798 match(Set res (WeakCompareAndSwapB mem (Binary oldval newval)));
5799
5800 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 6);
5801
5802 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5803
5804 format %{
5805 "cmpxchg_weak_acq $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5806 "# $res == 1 when success, #@weakCompareAndSwapBAcq"
5807 %}
5808
5809 ins_encode %{
5810 __ weak_cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5811 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
5812 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5813 %}
5814
5815 ins_pipe(pipe_slow);
5816 %}
5817
5818 instruct weakCompareAndSwapSAcq(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5819 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5820 %{
5821 predicate(needs_acquiring_load_reserved(n));
5822
5823 match(Set res (WeakCompareAndSwapS mem (Binary oldval newval)));
5824
5825 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 7);
5826
5827 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5828
5829 format %{
5830 "cmpxchg_weak_acq $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5831 "# $res == 1 when success, #@weakCompareAndSwapSAcq"
5832 %}
5833
5834 ins_encode %{
5835 __ weak_cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5836 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
5837 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5838 %}
5839
5840 ins_pipe(pipe_slow);
5841 %}
5842
5843 instruct weakCompareAndSwapIAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5844 %{
5845 predicate(needs_acquiring_load_reserved(n));
5846
5847 match(Set res (WeakCompareAndSwapI mem (Binary oldval newval)));
5848
5849 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 2);
5850
5851 format %{
5852 "cmpxchg_weak_acq $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5853 "# $res == 1 when success, #@weakCompareAndSwapIAcq"
5854 %}
5855
5856 ins_encode %{
5857 __ cmpxchg_weak(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
5858 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
5859 %}
5860
5861 ins_pipe(pipe_slow);
5862 %}
5863
5864 instruct weakCompareAndSwapLAcq(iRegINoSp res, indirect mem, iRegL oldval, iRegL newval)
5865 %{
5866 predicate(needs_acquiring_load_reserved(n));
5867
5868 match(Set res (WeakCompareAndSwapL mem (Binary oldval newval)));
5869
5870 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 2);
5871
5872 format %{
5873 "cmpxchg_weak_acq $mem, $oldval, $newval\t# (long, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5874 "# $res == 1 when success, #@weakCompareAndSwapLAcq"
5875 %}
5876
5877 ins_encode %{
5878 __ cmpxchg_weak(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5879 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
5880 %}
5881
5882 ins_pipe(pipe_slow);
5883 %}
5884
5885 instruct weakCompareAndSwapNAcq(iRegINoSp res, indirect mem, iRegN oldval, iRegN newval)
5886 %{
5887 predicate(needs_acquiring_load_reserved(n));
5888
5889 match(Set res (WeakCompareAndSwapN mem (Binary oldval newval)));
5890
5891 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 4);
5892
5893 format %{
5894 "cmpxchg_weak_acq $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5895 "# $res == 1 when success, #@weakCompareAndSwapNAcq"
5896 %}
5897
5898 ins_encode %{
5899 __ cmpxchg_weak(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
5900 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
5901 %}
5902
5903 ins_pipe(pipe_slow);
5904 %}
5905
5906 instruct weakCompareAndSwapPAcq(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval)
5907 %{
5908 predicate(needs_acquiring_load_reserved(n) && (n->as_LoadStore()->barrier_data() == 0));
5909
5910 match(Set res (WeakCompareAndSwapP mem (Binary oldval newval)));
5911
5912 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 2);
5913
5914 format %{
5915 "cmpxchg_weak_acq $mem, $oldval, $newval\t# (ptr, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5916 "\t# $res == 1 when success, #@weakCompareAndSwapPAcq"
5917 %}
5918
5919 ins_encode %{
5920 __ cmpxchg_weak(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5921 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
5922 %}
5923
5924 ins_pipe(pipe_slow);
5925 %}
5926
5927 instruct get_and_setI(indirect mem, iRegI newv, iRegINoSp prev)
5928 %{
5929 match(Set prev (GetAndSetI mem newv));
5930
5931 ins_cost(ALU_COST);
5932
5933 format %{ "atomic_xchgw $prev, $newv, [$mem]\t#@get_and_setI" %}
5934
5935 ins_encode %{
5936 __ atomic_xchgw($prev$$Register, $newv$$Register, as_Register($mem$$base));
5937 %}
5938
5939 ins_pipe(pipe_serial);
5940 %}
5941
5942 instruct get_and_setL(indirect mem, iRegL newv, iRegLNoSp prev)
5943 %{
5944 match(Set prev (GetAndSetL mem newv));
5945
5946 ins_cost(ALU_COST);
5947
5948 format %{ "atomic_xchg $prev, $newv, [$mem]\t#@get_and_setL" %}
5949
5950 ins_encode %{
5951 __ atomic_xchg($prev$$Register, $newv$$Register, as_Register($mem$$base));
5952 %}
5953
5954 ins_pipe(pipe_serial);
5955 %}
5956
5957 instruct get_and_setN(indirect mem, iRegN newv, iRegINoSp prev)
5958 %{
5959 match(Set prev (GetAndSetN mem newv));
5960
5961 ins_cost(ALU_COST);
5962
5963 format %{ "atomic_xchgwu $prev, $newv, [$mem]\t#@get_and_setN" %}
5964
5965 ins_encode %{
5966 __ atomic_xchgwu($prev$$Register, $newv$$Register, as_Register($mem$$base));
5967 %}
5968
5969 ins_pipe(pipe_serial);
5970 %}
5971
5972 instruct get_and_setP(indirect mem, iRegP newv, iRegPNoSp prev)
5973 %{
5974 predicate(n->as_LoadStore()->barrier_data() == 0);
5975 match(Set prev (GetAndSetP mem newv));
5976
5977 ins_cost(ALU_COST);
5978
5979 format %{ "atomic_xchg $prev, $newv, [$mem]\t#@get_and_setP" %}
5980
5981 ins_encode %{
5982 __ atomic_xchg($prev$$Register, $newv$$Register, as_Register($mem$$base));
5983 %}
5984
5985 ins_pipe(pipe_serial);
5986 %}
5987
5988 instruct get_and_setIAcq(indirect mem, iRegI newv, iRegINoSp prev)
5989 %{
5990 predicate(needs_acquiring_load_reserved(n));
5991
5992 match(Set prev (GetAndSetI mem newv));
5993
5994 ins_cost(ALU_COST);
5995
5996 format %{ "atomic_xchgw_acq $prev, $newv, [$mem]\t#@get_and_setIAcq" %}
5997
5998 ins_encode %{
5999 __ atomic_xchgalw($prev$$Register, $newv$$Register, as_Register($mem$$base));
6000 %}
6001
6002 ins_pipe(pipe_serial);
6003 %}
6004
6005 instruct get_and_setLAcq(indirect mem, iRegL newv, iRegLNoSp prev)
6006 %{
6007 predicate(needs_acquiring_load_reserved(n));
6008
6009 match(Set prev (GetAndSetL mem newv));
6010
6011 ins_cost(ALU_COST);
6012
6013 format %{ "atomic_xchg_acq $prev, $newv, [$mem]\t#@get_and_setLAcq" %}
6014
6015 ins_encode %{
6016 __ atomic_xchgal($prev$$Register, $newv$$Register, as_Register($mem$$base));
6017 %}
6018
6019 ins_pipe(pipe_serial);
6020 %}
6021
6022 instruct get_and_setNAcq(indirect mem, iRegN newv, iRegINoSp prev)
6023 %{
6024 predicate(needs_acquiring_load_reserved(n));
6025
6026 match(Set prev (GetAndSetN mem newv));
6027
6028 ins_cost(ALU_COST);
6029
6030 format %{ "atomic_xchgwu_acq $prev, $newv, [$mem]\t#@get_and_setNAcq" %}
6031
6032 ins_encode %{
6033 __ atomic_xchgalwu($prev$$Register, $newv$$Register, as_Register($mem$$base));
6034 %}
6035
6036 ins_pipe(pipe_serial);
6037 %}
6038
6039 instruct get_and_setPAcq(indirect mem, iRegP newv, iRegPNoSp prev)
6040 %{
6041 predicate(needs_acquiring_load_reserved(n) && (n->as_LoadStore()->barrier_data() == 0));
6042
6043 match(Set prev (GetAndSetP mem newv));
6044
6045 ins_cost(ALU_COST);
6046
6047 format %{ "atomic_xchg_acq $prev, $newv, [$mem]\t#@get_and_setPAcq" %}
6048
6049 ins_encode %{
6050 __ atomic_xchgal($prev$$Register, $newv$$Register, as_Register($mem$$base));
6051 %}
6052
6053 ins_pipe(pipe_serial);
6054 %}
6055
6056 instruct get_and_addL(indirect mem, iRegLNoSp newval, iRegL incr)
6057 %{
6058 match(Set newval (GetAndAddL mem incr));
6059
6060 ins_cost(ALU_COST);
6061
6062 format %{ "get_and_addL $newval, [$mem], $incr\t#@get_and_addL" %}
6063
6064 ins_encode %{
6065 __ atomic_add($newval$$Register, $incr$$Register, as_Register($mem$$base));
6066 %}
6067
6068 ins_pipe(pipe_serial);
6069 %}
6070
6071 instruct get_and_addL_no_res(indirect mem, Universe dummy, iRegL incr)
6072 %{
6073 predicate(n->as_LoadStore()->result_not_used());
6074
6075 match(Set dummy (GetAndAddL mem incr));
6076
6077 ins_cost(ALU_COST);
6078
6079 format %{ "get_and_addL [$mem], $incr\t#@get_and_addL_no_res" %}
6080
6081 ins_encode %{
6082 __ atomic_add(noreg, $incr$$Register, as_Register($mem$$base));
6083 %}
6084
6085 ins_pipe(pipe_serial);
6086 %}
6087
6088 instruct get_and_addLi(indirect mem, iRegLNoSp newval, immLAdd incr)
6089 %{
6090 match(Set newval (GetAndAddL mem incr));
6091
6092 ins_cost(ALU_COST);
6093
6094 format %{ "get_and_addL $newval, [$mem], $incr\t#@get_and_addLi" %}
6095
6096 ins_encode %{
6097 __ atomic_add($newval$$Register, $incr$$constant, as_Register($mem$$base));
6098 %}
6099
6100 ins_pipe(pipe_serial);
6101 %}
6102
6103 instruct get_and_addLi_no_res(indirect mem, Universe dummy, immLAdd incr)
6104 %{
6105 predicate(n->as_LoadStore()->result_not_used());
6106
6107 match(Set dummy (GetAndAddL mem incr));
6108
6109 ins_cost(ALU_COST);
6110
6111 format %{ "get_and_addL [$mem], $incr\t#@get_and_addLi_no_res" %}
6112
6113 ins_encode %{
6114 __ atomic_add(noreg, $incr$$constant, as_Register($mem$$base));
6115 %}
6116
6117 ins_pipe(pipe_serial);
6118 %}
6119
6120 instruct get_and_addI(indirect mem, iRegINoSp newval, iRegIorL2I incr)
6121 %{
6122 match(Set newval (GetAndAddI mem incr));
6123
6124 ins_cost(ALU_COST);
6125
6126 format %{ "get_and_addI $newval, [$mem], $incr\t#@get_and_addI" %}
6127
6128 ins_encode %{
6129 __ atomic_addw($newval$$Register, $incr$$Register, as_Register($mem$$base));
6130 %}
6131
6132 ins_pipe(pipe_serial);
6133 %}
6134
6135 instruct get_and_addI_no_res(indirect mem, Universe dummy, iRegIorL2I incr)
6136 %{
6137 predicate(n->as_LoadStore()->result_not_used());
6138
6139 match(Set dummy (GetAndAddI mem incr));
6140
6141 ins_cost(ALU_COST);
6142
6143 format %{ "get_and_addI [$mem], $incr\t#@get_and_addI_no_res" %}
6144
6145 ins_encode %{
6146 __ atomic_addw(noreg, $incr$$Register, as_Register($mem$$base));
6147 %}
6148
6149 ins_pipe(pipe_serial);
6150 %}
6151
6152 instruct get_and_addIi(indirect mem, iRegINoSp newval, immIAdd incr)
6153 %{
6154 match(Set newval (GetAndAddI mem incr));
6155
6156 ins_cost(ALU_COST);
6157
6158 format %{ "get_and_addI $newval, [$mem], $incr\t#@get_and_addIi" %}
6159
6160 ins_encode %{
6161 __ atomic_addw($newval$$Register, $incr$$constant, as_Register($mem$$base));
6162 %}
6163
6164 ins_pipe(pipe_serial);
6165 %}
6166
6167 instruct get_and_addIi_no_res(indirect mem, Universe dummy, immIAdd incr)
6168 %{
6169 predicate(n->as_LoadStore()->result_not_used());
6170
6171 match(Set dummy (GetAndAddI mem incr));
6172
6173 ins_cost(ALU_COST);
6174
6175 format %{ "get_and_addI [$mem], $incr\t#@get_and_addIi_no_res" %}
6176
6177 ins_encode %{
6178 __ atomic_addw(noreg, $incr$$constant, as_Register($mem$$base));
6179 %}
6180
6181 ins_pipe(pipe_serial);
6182 %}
6183
6184 instruct get_and_addLAcq(indirect mem, iRegLNoSp newval, iRegL incr)
6185 %{
6186 predicate(needs_acquiring_load_reserved(n));
6187
6188 match(Set newval (GetAndAddL mem incr));
6189
6190 ins_cost(ALU_COST);
6191
6192 format %{ "get_and_addL_acq $newval, [$mem], $incr\t#@get_and_addLAcq" %}
6193
6194 ins_encode %{
6195 __ atomic_addal($newval$$Register, $incr$$Register, as_Register($mem$$base));
6196 %}
6197
6198 ins_pipe(pipe_serial);
6199 %}
6200
6201 instruct get_and_addL_no_resAcq(indirect mem, Universe dummy, iRegL incr) %{
6202 predicate(n->as_LoadStore()->result_not_used() && needs_acquiring_load_reserved(n));
6203
6204 match(Set dummy (GetAndAddL mem incr));
6205
6206 ins_cost(ALU_COST);
6207
6208 format %{ "get_and_addL_acq [$mem], $incr\t#@get_and_addL_no_resAcq" %}
6209
6210 ins_encode %{
6211 __ atomic_addal(noreg, $incr$$Register, as_Register($mem$$base));
6212 %}
6213
6214 ins_pipe(pipe_serial);
6215 %}
6216
6217 instruct get_and_addLiAcq(indirect mem, iRegLNoSp newval, immLAdd incr)
6218 %{
6219 predicate(needs_acquiring_load_reserved(n));
6220
6221 match(Set newval (GetAndAddL mem incr));
6222
6223 ins_cost(ALU_COST);
6224
6225 format %{ "get_and_addL_acq $newval, [$mem], $incr\t#@get_and_addLiAcq" %}
6226
6227 ins_encode %{
6228 __ atomic_addal($newval$$Register, $incr$$constant, as_Register($mem$$base));
6229 %}
6230
6231 ins_pipe(pipe_serial);
6232 %}
6233
6234 instruct get_and_addLi_no_resAcq(indirect mem, Universe dummy, immLAdd incr)
6235 %{
6236 predicate(n->as_LoadStore()->result_not_used() && needs_acquiring_load_reserved(n));
6237
6238 match(Set dummy (GetAndAddL mem incr));
6239
6240 ins_cost(ALU_COST);
6241
6242 format %{ "get_and_addL_acq [$mem], $incr\t#@get_and_addLi_no_resAcq" %}
6243
6244 ins_encode %{
6245 __ atomic_addal(noreg, $incr$$constant, as_Register($mem$$base));
6246 %}
6247
6248 ins_pipe(pipe_serial);
6249 %}
6250
6251 instruct get_and_addIAcq(indirect mem, iRegINoSp newval, iRegIorL2I incr)
6252 %{
6253 predicate(needs_acquiring_load_reserved(n));
6254
6255 match(Set newval (GetAndAddI mem incr));
6256
6257 ins_cost(ALU_COST);
6258
6259 format %{ "get_and_addI_acq $newval, [$mem], $incr\t#@get_and_addIAcq" %}
6260
6261 ins_encode %{
6262 __ atomic_addalw($newval$$Register, $incr$$Register, as_Register($mem$$base));
6263 %}
6264
6265 ins_pipe(pipe_serial);
6266 %}
6267
6268 instruct get_and_addI_no_resAcq(indirect mem, Universe dummy, iRegIorL2I incr)
6269 %{
6270 predicate(n->as_LoadStore()->result_not_used() && needs_acquiring_load_reserved(n));
6271
6272 match(Set dummy (GetAndAddI mem incr));
6273
6274 ins_cost(ALU_COST);
6275
6276 format %{ "get_and_addI_acq [$mem], $incr\t#@get_and_addI_no_resAcq" %}
6277
6278 ins_encode %{
6279 __ atomic_addalw(noreg, $incr$$Register, as_Register($mem$$base));
6280 %}
6281
6282 ins_pipe(pipe_serial);
6283 %}
6284
6285 instruct get_and_addIiAcq(indirect mem, iRegINoSp newval, immIAdd incr)
6286 %{
6287 predicate(needs_acquiring_load_reserved(n));
6288
6289 match(Set newval (GetAndAddI mem incr));
6290
6291 ins_cost(ALU_COST);
6292
6293 format %{ "get_and_addI_acq $newval, [$mem], $incr\t#@get_and_addIiAcq" %}
6294
6295 ins_encode %{
6296 __ atomic_addalw($newval$$Register, $incr$$constant, as_Register($mem$$base));
6297 %}
6298
6299 ins_pipe(pipe_serial);
6300 %}
6301
6302 instruct get_and_addIi_no_resAcq(indirect mem, Universe dummy, immIAdd incr)
6303 %{
6304 predicate(n->as_LoadStore()->result_not_used() && needs_acquiring_load_reserved(n));
6305
6306 match(Set dummy (GetAndAddI mem incr));
6307
6308 ins_cost(ALU_COST);
6309
6310 format %{ "get_and_addI_acq [$mem], $incr\t#@get_and_addIi_no_resAcq" %}
6311
6312 ins_encode %{
6313 __ atomic_addalw(noreg, $incr$$constant, as_Register($mem$$base));
6314 %}
6315
6316 ins_pipe(pipe_serial);
6317 %}
6318
6319 // ============================================================================
6320 // Arithmetic Instructions
6321 //
6322
6323 // Integer Addition
6324
6325 // TODO
6326 // these currently employ operations which do not set CR and hence are
6327 // not flagged as killing CR but we would like to isolate the cases
6328 // where we want to set flags from those where we don't. need to work
6329 // out how to do that.
6330 instruct addI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6331 match(Set dst (AddI src1 src2));
6332
6333 ins_cost(ALU_COST);
6334 format %{ "addw $dst, $src1, $src2\t#@addI_reg_reg" %}
6335
6336 ins_encode %{
6337 Assembler::CompressibleRegion cr(&_masm);
6338 __ addw(as_Register($dst$$reg),
6339 as_Register($src1$$reg),
6340 as_Register($src2$$reg));
6341 %}
6342
6343 ins_pipe(ialu_reg_reg);
6344 %}
6345
6346 instruct addI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immIAdd src2) %{
6347 match(Set dst (AddI src1 src2));
6348
6349 ins_cost(ALU_COST);
6350 format %{ "addiw $dst, $src1, $src2\t#@addI_reg_imm" %}
6351
6352 ins_encode %{
6353 Assembler::CompressibleRegion cr(&_masm);
6354 int32_t con = (int32_t)$src2$$constant;
6355 __ addiw(as_Register($dst$$reg),
6356 as_Register($src1$$reg),
6357 $src2$$constant);
6358 %}
6359
6360 ins_pipe(ialu_reg_imm);
6361 %}
6362
6363 instruct addI_reg_imm_l2i(iRegINoSp dst, iRegL src1, immIAdd src2) %{
6364 match(Set dst (AddI (ConvL2I src1) src2));
6365
6366 ins_cost(ALU_COST);
6367 format %{ "addiw $dst, $src1, $src2\t#@addI_reg_imm_l2i" %}
6368
6369 ins_encode %{
6370 Assembler::CompressibleRegion cr(&_masm);
6371 __ addiw(as_Register($dst$$reg),
6372 as_Register($src1$$reg),
6373 $src2$$constant);
6374 %}
6375
6376 ins_pipe(ialu_reg_imm);
6377 %}
6378
6379 // Pointer Addition
6380 instruct addP_reg_reg(iRegPNoSp dst, iRegP src1, iRegL src2) %{
6381 match(Set dst (AddP src1 src2));
6382
6383 ins_cost(ALU_COST);
6384 format %{ "add $dst, $src1, $src2\t# ptr, #@addP_reg_reg" %}
6385
6386 ins_encode %{
6387 Assembler::CompressibleRegion cr(&_masm);
6388 __ add(as_Register($dst$$reg),
6389 as_Register($src1$$reg),
6390 as_Register($src2$$reg));
6391 %}
6392
6393 ins_pipe(ialu_reg_reg);
6394 %}
6395
6396 // If we shift more than 32 bits, we need not convert I2L.
6397 instruct lShiftL_regI_immGE32(iRegLNoSp dst, iRegI src, uimmI6_ge32 scale) %{
6398 match(Set dst (LShiftL (ConvI2L src) scale));
6399 ins_cost(ALU_COST);
6400 format %{ "slli $dst, $src, $scale & 63\t#@lShiftL_regI_immGE32" %}
6401
6402 ins_encode %{
6403 Assembler::CompressibleRegion cr(&_masm);
6404 __ slli(as_Register($dst$$reg), as_Register($src$$reg), $scale$$constant & 63);
6405 %}
6406
6407 ins_pipe(ialu_reg_shift);
6408 %}
6409
6410 // Pointer Immediate Addition
6411 // n.b. this needs to be more expensive than using an indirect memory
6412 // operand
6413 instruct addP_reg_imm(iRegPNoSp dst, iRegP src1, immLAdd src2) %{
6414 match(Set dst (AddP src1 src2));
6415 ins_cost(ALU_COST);
6416 format %{ "addi $dst, $src1, $src2\t# ptr, #@addP_reg_imm" %}
6417
6418 ins_encode %{
6419 Assembler::CompressibleRegion cr(&_masm);
6420 // src2 is imm, so actually call the addi
6421 __ add(as_Register($dst$$reg),
6422 as_Register($src1$$reg),
6423 $src2$$constant);
6424 %}
6425
6426 ins_pipe(ialu_reg_imm);
6427 %}
6428
6429 // Long Addition
6430 instruct addL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
6431 match(Set dst (AddL src1 src2));
6432 ins_cost(ALU_COST);
6433 format %{ "add $dst, $src1, $src2\t#@addL_reg_reg" %}
6434
6435 ins_encode %{
6436 Assembler::CompressibleRegion cr(&_masm);
6437 __ add(as_Register($dst$$reg),
6438 as_Register($src1$$reg),
6439 as_Register($src2$$reg));
6440 %}
6441
6442 ins_pipe(ialu_reg_reg);
6443 %}
6444
6445 // No constant pool entries requiredLong Immediate Addition.
6446 instruct addL_reg_imm(iRegLNoSp dst, iRegL src1, immLAdd src2) %{
6447 match(Set dst (AddL src1 src2));
6448 ins_cost(ALU_COST);
6449 format %{ "addi $dst, $src1, $src2\t#@addL_reg_imm" %}
6450
6451 ins_encode %{
6452 Assembler::CompressibleRegion cr(&_masm);
6453 // src2 is imm, so actually call the addi
6454 __ add(as_Register($dst$$reg),
6455 as_Register($src1$$reg),
6456 $src2$$constant);
6457 %}
6458
6459 ins_pipe(ialu_reg_imm);
6460 %}
6461
6462 // Integer Subtraction
6463 instruct subI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6464 match(Set dst (SubI src1 src2));
6465
6466 ins_cost(ALU_COST);
6467 format %{ "subw $dst, $src1, $src2\t#@subI_reg_reg" %}
6468
6469 ins_encode %{
6470 Assembler::CompressibleRegion cr(&_masm);
6471 __ subw(as_Register($dst$$reg),
6472 as_Register($src1$$reg),
6473 as_Register($src2$$reg));
6474 %}
6475
6476 ins_pipe(ialu_reg_reg);
6477 %}
6478
6479 // Immediate Subtraction
6480 instruct subI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immISub src2) %{
6481 match(Set dst (SubI src1 src2));
6482
6483 ins_cost(ALU_COST);
6484 format %{ "addiw $dst, $src1, -$src2\t#@subI_reg_imm" %}
6485
6486 ins_encode %{
6487 Assembler::CompressibleRegion cr(&_masm);
6488 // src2 is imm, so actually call the addiw
6489 __ subw(as_Register($dst$$reg),
6490 as_Register($src1$$reg),
6491 $src2$$constant);
6492 %}
6493
6494 ins_pipe(ialu_reg_imm);
6495 %}
6496
6497 // Long Subtraction
6498 instruct subL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
6499 match(Set dst (SubL src1 src2));
6500 ins_cost(ALU_COST);
6501 format %{ "sub $dst, $src1, $src2\t#@subL_reg_reg" %}
6502
6503 ins_encode %{
6504 Assembler::CompressibleRegion cr(&_masm);
6505 __ sub(as_Register($dst$$reg),
6506 as_Register($src1$$reg),
6507 as_Register($src2$$reg));
6508 %}
6509
6510 ins_pipe(ialu_reg_reg);
6511 %}
6512
6513 // No constant pool entries requiredLong Immediate Subtraction.
6514 instruct subL_reg_imm(iRegLNoSp dst, iRegL src1, immLSub src2) %{
6515 match(Set dst (SubL src1 src2));
6516 ins_cost(ALU_COST);
6517 format %{ "addi $dst, $src1, -$src2\t#@subL_reg_imm" %}
6518
6519 ins_encode %{
6520 Assembler::CompressibleRegion cr(&_masm);
6521 // src2 is imm, so actually call the addi
6522 __ sub(as_Register($dst$$reg),
6523 as_Register($src1$$reg),
6524 $src2$$constant);
6525 %}
6526
6527 ins_pipe(ialu_reg_imm);
6528 %}
6529
6530 // Integer Negation (special case for sub)
6531
6532 instruct negI_reg(iRegINoSp dst, iRegIorL2I src, immI0 zero) %{
6533 match(Set dst (SubI zero src));
6534 ins_cost(ALU_COST);
6535 format %{ "subw $dst, x0, $src\t# int, #@negI_reg" %}
6536
6537 ins_encode %{
6538 // actually call the subw
6539 __ negw(as_Register($dst$$reg),
6540 as_Register($src$$reg));
6541 %}
6542
6543 ins_pipe(ialu_reg);
6544 %}
6545
6546 // Long Negation
6547
6548 instruct negL_reg(iRegLNoSp dst, iRegL src, immL0 zero) %{
6549 match(Set dst (SubL zero src));
6550 ins_cost(ALU_COST);
6551 format %{ "sub $dst, x0, $src\t# long, #@negL_reg" %}
6552
6553 ins_encode %{
6554 // actually call the sub
6555 __ neg(as_Register($dst$$reg),
6556 as_Register($src$$reg));
6557 %}
6558
6559 ins_pipe(ialu_reg);
6560 %}
6561
6562 // Integer Multiply
6563
6564 instruct mulI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6565 match(Set dst (MulI src1 src2));
6566 ins_cost(IMUL_COST);
6567 format %{ "mulw $dst, $src1, $src2\t#@mulI" %}
6568
6569 //this means 2 word multi, and no sign extend to 64 bits
6570 ins_encode %{
6571 // riscv64 mulw will sign-extension to high 32 bits in dst reg
6572 __ mulw(as_Register($dst$$reg),
6573 as_Register($src1$$reg),
6574 as_Register($src2$$reg));
6575 %}
6576
6577 ins_pipe(imul_reg_reg);
6578 %}
6579
6580 // Long Multiply
6581
6582 instruct mulL(iRegLNoSp dst, iRegL src1, iRegL src2) %{
6583 match(Set dst (MulL src1 src2));
6584 ins_cost(IMUL_COST);
6585 format %{ "mul $dst, $src1, $src2\t#@mulL" %}
6586
6587 ins_encode %{
6588 __ mul(as_Register($dst$$reg),
6589 as_Register($src1$$reg),
6590 as_Register($src2$$reg));
6591 %}
6592
6593 ins_pipe(lmul_reg_reg);
6594 %}
6595
6596 instruct mulHiL_rReg(iRegLNoSp dst, iRegL src1, iRegL src2)
6597 %{
6598 match(Set dst (MulHiL src1 src2));
6599 ins_cost(IMUL_COST);
6600 format %{ "mulh $dst, $src1, $src2\t# mulhi, #@mulHiL_rReg" %}
6601
6602 ins_encode %{
6603 __ mulh(as_Register($dst$$reg),
6604 as_Register($src1$$reg),
6605 as_Register($src2$$reg));
6606 %}
6607
6608 ins_pipe(lmul_reg_reg);
6609 %}
6610
6611 // Integer Divide
6612
6613 instruct divI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6614 match(Set dst (DivI src1 src2));
6615 ins_cost(IDIVSI_COST);
6616 format %{ "divw $dst, $src1, $src2\t#@divI"%}
6617
6618 ins_encode(riscv_enc_divw(dst, src1, src2));
6619 ins_pipe(idiv_reg_reg);
6620 %}
6621
6622 instruct signExtract(iRegINoSp dst, iRegIorL2I src1, immI_31 div1, immI_31 div2) %{
6623 match(Set dst (URShiftI (RShiftI src1 div1) div2));
6624 ins_cost(ALU_COST);
6625 format %{ "srliw $dst, $src1, $div1\t# int signExtract, #@signExtract" %}
6626
6627 ins_encode %{
6628 __ srliw(as_Register($dst$$reg), as_Register($src1$$reg), 31);
6629 %}
6630 ins_pipe(ialu_reg_shift);
6631 %}
6632
6633 // Long Divide
6634
6635 instruct divL(iRegLNoSp dst, iRegL src1, iRegL src2) %{
6636 match(Set dst (DivL src1 src2));
6637 ins_cost(IDIVDI_COST);
6638 format %{ "div $dst, $src1, $src2\t#@divL" %}
6639
6640 ins_encode(riscv_enc_div(dst, src1, src2));
6641 ins_pipe(ldiv_reg_reg);
6642 %}
6643
6644 instruct signExtractL(iRegLNoSp dst, iRegL src1, immI_63 div1, immI_63 div2) %{
6645 match(Set dst (URShiftL (RShiftL src1 div1) div2));
6646 ins_cost(ALU_COST);
6647 format %{ "srli $dst, $src1, $div1\t# long signExtract, #@signExtractL" %}
6648
6649 ins_encode %{
6650 Assembler::CompressibleRegion cr(&_masm);
6651 __ srli(as_Register($dst$$reg), as_Register($src1$$reg), 63);
6652 %}
6653 ins_pipe(ialu_reg_shift);
6654 %}
6655
6656 // Integer Remainder
6657
6658 instruct modI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6659 match(Set dst (ModI src1 src2));
6660 ins_cost(IDIVSI_COST);
6661 format %{ "remw $dst, $src1, $src2\t#@modI" %}
6662
6663 ins_encode(riscv_enc_modw(dst, src1, src2));
6664 ins_pipe(ialu_reg_reg);
6665 %}
6666
6667 // Long Remainder
6668
6669 instruct modL(iRegLNoSp dst, iRegL src1, iRegL src2) %{
6670 match(Set dst (ModL src1 src2));
6671 ins_cost(IDIVDI_COST);
6672 format %{ "rem $dst, $src1, $src2\t#@modL" %}
6673
6674 ins_encode(riscv_enc_mod(dst, src1, src2));
6675 ins_pipe(ialu_reg_reg);
6676 %}
6677
6678 // Integer Shifts
6679
6680 // Shift Left Register
6681 // In RV64I, only the low 5 bits of src2 are considered for the shift amount
6682 instruct lShiftI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6683 match(Set dst (LShiftI src1 src2));
6684 ins_cost(ALU_COST);
6685 format %{ "sllw $dst, $src1, $src2\t#@lShiftI_reg_reg" %}
6686
6687 ins_encode %{
6688 __ sllw(as_Register($dst$$reg),
6689 as_Register($src1$$reg),
6690 as_Register($src2$$reg));
6691 %}
6692
6693 ins_pipe(ialu_reg_reg_vshift);
6694 %}
6695
6696 // Shift Left Immediate
6697 instruct lShiftI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immI src2) %{
6698 match(Set dst (LShiftI src1 src2));
6699 ins_cost(ALU_COST);
6700 format %{ "slliw $dst, $src1, ($src2 & 0x1f)\t#@lShiftI_reg_imm" %}
6701
6702 ins_encode %{
6703 // the shift amount is encoded in the lower
6704 // 5 bits of the I-immediate field for RV32I
6705 __ slliw(as_Register($dst$$reg),
6706 as_Register($src1$$reg),
6707 (unsigned) $src2$$constant & 0x1f);
6708 %}
6709
6710 ins_pipe(ialu_reg_shift);
6711 %}
6712
6713 // Shift Right Logical Register
6714 // In RV64I, only the low 5 bits of src2 are considered for the shift amount
6715 instruct urShiftI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6716 match(Set dst (URShiftI src1 src2));
6717 ins_cost(ALU_COST);
6718 format %{ "srlw $dst, $src1, $src2\t#@urShiftI_reg_reg" %}
6719
6720 ins_encode %{
6721 __ srlw(as_Register($dst$$reg),
6722 as_Register($src1$$reg),
6723 as_Register($src2$$reg));
6724 %}
6725
6726 ins_pipe(ialu_reg_reg_vshift);
6727 %}
6728
6729 // Shift Right Logical Immediate
6730 instruct urShiftI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immI src2) %{
6731 match(Set dst (URShiftI src1 src2));
6732 ins_cost(ALU_COST);
6733 format %{ "srliw $dst, $src1, ($src2 & 0x1f)\t#@urShiftI_reg_imm" %}
6734
6735 ins_encode %{
6736 // the shift amount is encoded in the lower
6737 // 6 bits of the I-immediate field for RV64I
6738 __ srliw(as_Register($dst$$reg),
6739 as_Register($src1$$reg),
6740 (unsigned) $src2$$constant & 0x1f);
6741 %}
6742
6743 ins_pipe(ialu_reg_shift);
6744 %}
6745
6746 // Shift Right Arithmetic Register
6747 // In RV64I, only the low 5 bits of src2 are considered for the shift amount
6748 instruct rShiftI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6749 match(Set dst (RShiftI src1 src2));
6750 ins_cost(ALU_COST);
6751 format %{ "sraw $dst, $src1, $src2\t#@rShiftI_reg_reg" %}
6752
6753 ins_encode %{
6754 // riscv will sign-ext dst high 32 bits
6755 __ sraw(as_Register($dst$$reg),
6756 as_Register($src1$$reg),
6757 as_Register($src2$$reg));
6758 %}
6759
6760 ins_pipe(ialu_reg_reg_vshift);
6761 %}
6762
6763 // Shift Right Arithmetic Immediate
6764 instruct rShiftI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immI src2) %{
6765 match(Set dst (RShiftI src1 src2));
6766 ins_cost(ALU_COST);
6767 format %{ "sraiw $dst, $src1, ($src2 & 0x1f)\t#@rShiftI_reg_imm" %}
6768
6769 ins_encode %{
6770 // riscv will sign-ext dst high 32 bits
6771 __ sraiw(as_Register($dst$$reg),
6772 as_Register($src1$$reg),
6773 (unsigned) $src2$$constant & 0x1f);
6774 %}
6775
6776 ins_pipe(ialu_reg_shift);
6777 %}
6778
6779 // Long Shifts
6780
6781 // Shift Left Register
6782 // In RV64I, only the low 6 bits of src2 are considered for the shift amount
6783 instruct lShiftL_reg_reg(iRegLNoSp dst, iRegL src1, iRegIorL2I src2) %{
6784 match(Set dst (LShiftL src1 src2));
6785
6786 ins_cost(ALU_COST);
6787 format %{ "sll $dst, $src1, $src2\t#@lShiftL_reg_reg" %}
6788
6789 ins_encode %{
6790 __ sll(as_Register($dst$$reg),
6791 as_Register($src1$$reg),
6792 as_Register($src2$$reg));
6793 %}
6794
6795 ins_pipe(ialu_reg_reg_vshift);
6796 %}
6797
6798 // Shift Left Immediate
6799 instruct lShiftL_reg_imm(iRegLNoSp dst, iRegL src1, immI src2) %{
6800 match(Set dst (LShiftL src1 src2));
6801
6802 ins_cost(ALU_COST);
6803 format %{ "slli $dst, $src1, ($src2 & 0x3f)\t#@lShiftL_reg_imm" %}
6804
6805 ins_encode %{
6806 Assembler::CompressibleRegion cr(&_masm);
6807 // the shift amount is encoded in the lower
6808 // 6 bits of the I-immediate field for RV64I
6809 __ slli(as_Register($dst$$reg),
6810 as_Register($src1$$reg),
6811 (unsigned) $src2$$constant & 0x3f);
6812 %}
6813
6814 ins_pipe(ialu_reg_shift);
6815 %}
6816
6817 // Shift Right Logical Register
6818 // In RV64I, only the low 6 bits of src2 are considered for the shift amount
6819 instruct urShiftL_reg_reg(iRegLNoSp dst, iRegL src1, iRegIorL2I src2) %{
6820 match(Set dst (URShiftL src1 src2));
6821
6822 ins_cost(ALU_COST);
6823 format %{ "srl $dst, $src1, $src2\t#@urShiftL_reg_reg" %}
6824
6825 ins_encode %{
6826 __ srl(as_Register($dst$$reg),
6827 as_Register($src1$$reg),
6828 as_Register($src2$$reg));
6829 %}
6830
6831 ins_pipe(ialu_reg_reg_vshift);
6832 %}
6833
6834 // Shift Right Logical Immediate
6835 instruct urShiftL_reg_imm(iRegLNoSp dst, iRegL src1, immI src2) %{
6836 match(Set dst (URShiftL src1 src2));
6837
6838 ins_cost(ALU_COST);
6839 format %{ "srli $dst, $src1, ($src2 & 0x3f)\t#@urShiftL_reg_imm" %}
6840
6841 ins_encode %{
6842 Assembler::CompressibleRegion cr(&_masm);
6843 // the shift amount is encoded in the lower
6844 // 6 bits of the I-immediate field for RV64I
6845 __ srli(as_Register($dst$$reg),
6846 as_Register($src1$$reg),
6847 (unsigned) $src2$$constant & 0x3f);
6848 %}
6849
6850 ins_pipe(ialu_reg_shift);
6851 %}
6852
6853 // A special-case pattern for card table stores.
6854 instruct urShiftP_reg_imm(iRegLNoSp dst, iRegP src1, immI src2) %{
6855 match(Set dst (URShiftL (CastP2X src1) src2));
6856
6857 ins_cost(ALU_COST);
6858 format %{ "srli $dst, p2x($src1), ($src2 & 0x3f)\t#@urShiftP_reg_imm" %}
6859
6860 ins_encode %{
6861 Assembler::CompressibleRegion cr(&_masm);
6862 // the shift amount is encoded in the lower
6863 // 6 bits of the I-immediate field for RV64I
6864 __ srli(as_Register($dst$$reg),
6865 as_Register($src1$$reg),
6866 (unsigned) $src2$$constant & 0x3f);
6867 %}
6868
6869 ins_pipe(ialu_reg_shift);
6870 %}
6871
6872 // Shift Right Arithmetic Register
6873 // In RV64I, only the low 6 bits of src2 are considered for the shift amount
6874 instruct rShiftL_reg_reg(iRegLNoSp dst, iRegL src1, iRegIorL2I src2) %{
6875 match(Set dst (RShiftL src1 src2));
6876
6877 ins_cost(ALU_COST);
6878 format %{ "sra $dst, $src1, $src2\t#@rShiftL_reg_reg" %}
6879
6880 ins_encode %{
6881 __ sra(as_Register($dst$$reg),
6882 as_Register($src1$$reg),
6883 as_Register($src2$$reg));
6884 %}
6885
6886 ins_pipe(ialu_reg_reg_vshift);
6887 %}
6888
6889 // Shift Right Arithmetic Immediate
6890 instruct rShiftL_reg_imm(iRegLNoSp dst, iRegL src1, immI src2) %{
6891 match(Set dst (RShiftL src1 src2));
6892
6893 ins_cost(ALU_COST);
6894 format %{ "srai $dst, $src1, ($src2 & 0x3f)\t#@rShiftL_reg_imm" %}
6895
6896 ins_encode %{
6897 Assembler::CompressibleRegion cr(&_masm);
6898 // the shift amount is encoded in the lower
6899 // 6 bits of the I-immediate field for RV64I
6900 __ srai(as_Register($dst$$reg),
6901 as_Register($src1$$reg),
6902 (unsigned) $src2$$constant & 0x3f);
6903 %}
6904
6905 ins_pipe(ialu_reg_shift);
6906 %}
6907
6908 instruct regI_not_reg(iRegINoSp dst, iRegI src1, immI_M1 m1) %{
6909 match(Set dst (XorI src1 m1));
6910 ins_cost(ALU_COST);
6911 format %{ "xori $dst, $src1, -1\t#@regI_not_reg" %}
6912
6913 ins_encode %{
6914 __ xori(as_Register($dst$$reg), as_Register($src1$$reg), -1);
6915 %}
6916
6917 ins_pipe(ialu_reg);
6918 %}
6919
6920 instruct regL_not_reg(iRegLNoSp dst, iRegL src1, immL_M1 m1) %{
6921 match(Set dst (XorL src1 m1));
6922 ins_cost(ALU_COST);
6923 format %{ "xori $dst, $src1, -1\t#@regL_not_reg" %}
6924
6925 ins_encode %{
6926 __ xori(as_Register($dst$$reg), as_Register($src1$$reg), -1);
6927 %}
6928
6929 ins_pipe(ialu_reg);
6930 %}
6931
6932
6933 // ============================================================================
6934 // Floating Point Arithmetic Instructions
6935
6936 instruct addF_reg_reg(fRegF dst, fRegF src1, fRegF src2) %{
6937 match(Set dst (AddF src1 src2));
6938
6939 ins_cost(FMUL_SINGLE_COST);
6940 format %{ "fadd.s $dst, $src1, $src2\t#@addF_reg_reg" %}
6941
6942 ins_encode %{
6943 __ fadd_s(as_FloatRegister($dst$$reg),
6944 as_FloatRegister($src1$$reg),
6945 as_FloatRegister($src2$$reg));
6946 %}
6947
6948 ins_pipe(fp_dop_reg_reg_s);
6949 %}
6950
6951 instruct addD_reg_reg(fRegD dst, fRegD src1, fRegD src2) %{
6952 match(Set dst (AddD src1 src2));
6953
6954 ins_cost(FMUL_DOUBLE_COST);
6955 format %{ "fadd.d $dst, $src1, $src2\t#@addD_reg_reg" %}
6956
6957 ins_encode %{
6958 __ fadd_d(as_FloatRegister($dst$$reg),
6959 as_FloatRegister($src1$$reg),
6960 as_FloatRegister($src2$$reg));
6961 %}
6962
6963 ins_pipe(fp_dop_reg_reg_d);
6964 %}
6965
6966 instruct subF_reg_reg(fRegF dst, fRegF src1, fRegF src2) %{
6967 match(Set dst (SubF src1 src2));
6968
6969 ins_cost(FMUL_SINGLE_COST);
6970 format %{ "fsub.s $dst, $src1, $src2\t#@subF_reg_reg" %}
6971
6972 ins_encode %{
6973 __ fsub_s(as_FloatRegister($dst$$reg),
6974 as_FloatRegister($src1$$reg),
6975 as_FloatRegister($src2$$reg));
6976 %}
6977
6978 ins_pipe(fp_dop_reg_reg_s);
6979 %}
6980
6981 instruct subD_reg_reg(fRegD dst, fRegD src1, fRegD src2) %{
6982 match(Set dst (SubD src1 src2));
6983
6984 ins_cost(FMUL_DOUBLE_COST);
6985 format %{ "fsub.d $dst, $src1, $src2\t#@subD_reg_reg" %}
6986
6987 ins_encode %{
6988 __ fsub_d(as_FloatRegister($dst$$reg),
6989 as_FloatRegister($src1$$reg),
6990 as_FloatRegister($src2$$reg));
6991 %}
6992
6993 ins_pipe(fp_dop_reg_reg_d);
6994 %}
6995
6996 instruct mulF_reg_reg(fRegF dst, fRegF src1, fRegF src2) %{
6997 match(Set dst (MulF src1 src2));
6998
6999 ins_cost(FMUL_SINGLE_COST);
7000 format %{ "fmul.s $dst, $src1, $src2\t#@mulF_reg_reg" %}
7001
7002 ins_encode %{
7003 __ fmul_s(as_FloatRegister($dst$$reg),
7004 as_FloatRegister($src1$$reg),
7005 as_FloatRegister($src2$$reg));
7006 %}
7007
7008 ins_pipe(fp_dop_reg_reg_s);
7009 %}
7010
7011 instruct mulD_reg_reg(fRegD dst, fRegD src1, fRegD src2) %{
7012 match(Set dst (MulD src1 src2));
7013
7014 ins_cost(FMUL_DOUBLE_COST);
7015 format %{ "fmul.d $dst, $src1, $src2\t#@mulD_reg_reg" %}
7016
7017 ins_encode %{
7018 __ fmul_d(as_FloatRegister($dst$$reg),
7019 as_FloatRegister($src1$$reg),
7020 as_FloatRegister($src2$$reg));
7021 %}
7022
7023 ins_pipe(fp_dop_reg_reg_d);
7024 %}
7025
7026 // src1 * src2 + src3
7027 instruct maddF_reg_reg(fRegF dst, fRegF src1, fRegF src2, fRegF src3) %{
7028 predicate(UseFMA);
7029 match(Set dst (FmaF src3 (Binary src1 src2)));
7030
7031 ins_cost(FMUL_SINGLE_COST);
7032 format %{ "fmadd.s $dst, $src1, $src2, $src3\t#@maddF_reg_reg" %}
7033
7034 ins_encode %{
7035 __ fmadd_s(as_FloatRegister($dst$$reg),
7036 as_FloatRegister($src1$$reg),
7037 as_FloatRegister($src2$$reg),
7038 as_FloatRegister($src3$$reg));
7039 %}
7040
7041 ins_pipe(pipe_class_default);
7042 %}
7043
7044 // src1 * src2 + src3
7045 instruct maddD_reg_reg(fRegD dst, fRegD src1, fRegD src2, fRegD src3) %{
7046 predicate(UseFMA);
7047 match(Set dst (FmaD src3 (Binary src1 src2)));
7048
7049 ins_cost(FMUL_DOUBLE_COST);
7050 format %{ "fmadd.d $dst, $src1, $src2, $src3\t#@maddD_reg_reg" %}
7051
7052 ins_encode %{
7053 __ fmadd_d(as_FloatRegister($dst$$reg),
7054 as_FloatRegister($src1$$reg),
7055 as_FloatRegister($src2$$reg),
7056 as_FloatRegister($src3$$reg));
7057 %}
7058
7059 ins_pipe(pipe_class_default);
7060 %}
7061
7062 // src1 * src2 - src3
7063 instruct msubF_reg_reg(fRegF dst, fRegF src1, fRegF src2, fRegF src3) %{
7064 predicate(UseFMA);
7065 match(Set dst (FmaF (NegF src3) (Binary src1 src2)));
7066
7067 ins_cost(FMUL_SINGLE_COST);
7068 format %{ "fmsub.s $dst, $src1, $src2, $src3\t#@msubF_reg_reg" %}
7069
7070 ins_encode %{
7071 __ fmsub_s(as_FloatRegister($dst$$reg),
7072 as_FloatRegister($src1$$reg),
7073 as_FloatRegister($src2$$reg),
7074 as_FloatRegister($src3$$reg));
7075 %}
7076
7077 ins_pipe(pipe_class_default);
7078 %}
7079
7080 // src1 * src2 - src3
7081 instruct msubD_reg_reg(fRegD dst, fRegD src1, fRegD src2, fRegD src3) %{
7082 predicate(UseFMA);
7083 match(Set dst (FmaD (NegD src3) (Binary src1 src2)));
7084
7085 ins_cost(FMUL_DOUBLE_COST);
7086 format %{ "fmsub.d $dst, $src1, $src2, $src3\t#@msubD_reg_reg" %}
7087
7088 ins_encode %{
7089 __ fmsub_d(as_FloatRegister($dst$$reg),
7090 as_FloatRegister($src1$$reg),
7091 as_FloatRegister($src2$$reg),
7092 as_FloatRegister($src3$$reg));
7093 %}
7094
7095 ins_pipe(pipe_class_default);
7096 %}
7097
7098 // -src1 * src2 + src3
7099 instruct nmsubF_reg_reg(fRegF dst, fRegF src1, fRegF src2, fRegF src3) %{
7100 predicate(UseFMA);
7101 match(Set dst (FmaF src3 (Binary (NegF src1) src2)));
7102 match(Set dst (FmaF src3 (Binary src1 (NegF src2))));
7103
7104 ins_cost(FMUL_SINGLE_COST);
7105 format %{ "fnmsub.s $dst, $src1, $src2, $src3\t#@nmsubF_reg_reg" %}
7106
7107 ins_encode %{
7108 __ fnmsub_s(as_FloatRegister($dst$$reg),
7109 as_FloatRegister($src1$$reg),
7110 as_FloatRegister($src2$$reg),
7111 as_FloatRegister($src3$$reg));
7112 %}
7113
7114 ins_pipe(pipe_class_default);
7115 %}
7116
7117 // -src1 * src2 + src3
7118 instruct nmsubD_reg_reg(fRegD dst, fRegD src1, fRegD src2, fRegD src3) %{
7119 predicate(UseFMA);
7120 match(Set dst (FmaD src3 (Binary (NegD src1) src2)));
7121 match(Set dst (FmaD src3 (Binary src1 (NegD src2))));
7122
7123 ins_cost(FMUL_DOUBLE_COST);
7124 format %{ "fnmsub.d $dst, $src1, $src2, $src3\t#@nmsubD_reg_reg" %}
7125
7126 ins_encode %{
7127 __ fnmsub_d(as_FloatRegister($dst$$reg),
7128 as_FloatRegister($src1$$reg),
7129 as_FloatRegister($src2$$reg),
7130 as_FloatRegister($src3$$reg));
7131 %}
7132
7133 ins_pipe(pipe_class_default);
7134 %}
7135
7136 // -src1 * src2 - src3
7137 instruct nmaddF_reg_reg(fRegF dst, fRegF src1, fRegF src2, fRegF src3) %{
7138 predicate(UseFMA);
7139 match(Set dst (FmaF (NegF src3) (Binary (NegF src1) src2)));
7140 match(Set dst (FmaF (NegF src3) (Binary src1 (NegF src2))));
7141
7142 ins_cost(FMUL_SINGLE_COST);
7143 format %{ "fnmadd.s $dst, $src1, $src2, $src3\t#@nmaddF_reg_reg" %}
7144
7145 ins_encode %{
7146 __ fnmadd_s(as_FloatRegister($dst$$reg),
7147 as_FloatRegister($src1$$reg),
7148 as_FloatRegister($src2$$reg),
7149 as_FloatRegister($src3$$reg));
7150 %}
7151
7152 ins_pipe(pipe_class_default);
7153 %}
7154
7155 // -src1 * src2 - src3
7156 instruct nmaddD_reg_reg(fRegD dst, fRegD src1, fRegD src2, fRegD src3) %{
7157 predicate(UseFMA);
7158 match(Set dst (FmaD (NegD src3) (Binary (NegD src1) src2)));
7159 match(Set dst (FmaD (NegD src3) (Binary src1 (NegD src2))));
7160
7161 ins_cost(FMUL_DOUBLE_COST);
7162 format %{ "fnmadd.d $dst, $src1, $src2, $src3\t#@nmaddD_reg_reg" %}
7163
7164 ins_encode %{
7165 __ fnmadd_d(as_FloatRegister($dst$$reg),
7166 as_FloatRegister($src1$$reg),
7167 as_FloatRegister($src2$$reg),
7168 as_FloatRegister($src3$$reg));
7169 %}
7170
7171 ins_pipe(pipe_class_default);
7172 %}
7173
7174 // Math.max(FF)F
7175 instruct maxF_reg_reg(fRegF dst, fRegF src1, fRegF src2) %{
7176 match(Set dst (MaxF src1 src2));
7177 effect(TEMP_DEF dst);
7178
7179 format %{ "maxF $dst, $src1, $src2" %}
7180
7181 ins_encode %{
7182 __ minmax_FD(as_FloatRegister($dst$$reg),
7183 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg),
7184 false /* is_double */, false /* is_min */);
7185 %}
7186
7187 ins_pipe(fp_dop_reg_reg_s);
7188 %}
7189
7190 // Math.min(FF)F
7191 instruct minF_reg_reg(fRegF dst, fRegF src1, fRegF src2) %{
7192 match(Set dst (MinF src1 src2));
7193 effect(TEMP_DEF dst);
7194
7195 format %{ "minF $dst, $src1, $src2" %}
7196
7197 ins_encode %{
7198 __ minmax_FD(as_FloatRegister($dst$$reg),
7199 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg),
7200 false /* is_double */, true /* is_min */);
7201 %}
7202
7203 ins_pipe(fp_dop_reg_reg_s);
7204 %}
7205
7206 // Math.max(DD)D
7207 instruct maxD_reg_reg(fRegD dst, fRegD src1, fRegD src2) %{
7208 match(Set dst (MaxD src1 src2));
7209 effect(TEMP_DEF dst);
7210
7211 format %{ "maxD $dst, $src1, $src2" %}
7212
7213 ins_encode %{
7214 __ minmax_FD(as_FloatRegister($dst$$reg),
7215 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg),
7216 true /* is_double */, false /* is_min */);
7217 %}
7218
7219 ins_pipe(fp_dop_reg_reg_d);
7220 %}
7221
7222 // Math.min(DD)D
7223 instruct minD_reg_reg(fRegD dst, fRegD src1, fRegD src2) %{
7224 match(Set dst (MinD src1 src2));
7225 effect(TEMP_DEF dst);
7226
7227 format %{ "minD $dst, $src1, $src2" %}
7228
7229 ins_encode %{
7230 __ minmax_FD(as_FloatRegister($dst$$reg),
7231 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg),
7232 true /* is_double */, true /* is_min */);
7233 %}
7234
7235 ins_pipe(fp_dop_reg_reg_d);
7236 %}
7237
7238 // Float.isInfinite
7239 instruct isIniniteF_reg_reg(iRegINoSp dst, fRegF src)
7240 %{
7241 match(Set dst (IsInfiniteF src));
7242 format %{ "isInfinite $dst, $src" %}
7243 ins_encode %{
7244 __ fclass_s(as_Register($dst$$reg), as_FloatRegister($src$$reg));
7245 __ andi(as_Register($dst$$reg), as_Register($dst$$reg), 0b10000001);
7246 __ slt(as_Register($dst$$reg), zr, as_Register($dst$$reg));
7247 %}
7248 ins_pipe(fp_dop_reg_reg_s);
7249 %}
7250
7251 // Double.isInfinite
7252 instruct isInfiniteD_reg_reg(iRegINoSp dst, fRegD src)
7253 %{
7254 match(Set dst (IsInfiniteD src));
7255 format %{ "isInfinite $dst, $src" %}
7256 ins_encode %{
7257 __ fclass_d(as_Register($dst$$reg), as_FloatRegister($src$$reg));
7258 __ andi(as_Register($dst$$reg), as_Register($dst$$reg), 0b10000001);
7259 __ slt(as_Register($dst$$reg), zr, as_Register($dst$$reg));
7260 %}
7261 ins_pipe(fp_dop_reg_reg_d);
7262 %}
7263
7264 instruct divF_reg_reg(fRegF dst, fRegF src1, fRegF src2) %{
7265 match(Set dst (DivF src1 src2));
7266
7267 ins_cost(FDIV_COST);
7268 format %{ "fdiv.s $dst, $src1, $src2\t#@divF_reg_reg" %}
7269
7270 ins_encode %{
7271 __ fdiv_s(as_FloatRegister($dst$$reg),
7272 as_FloatRegister($src1$$reg),
7273 as_FloatRegister($src2$$reg));
7274 %}
7275
7276 ins_pipe(fp_div_s);
7277 %}
7278
7279 instruct divD_reg_reg(fRegD dst, fRegD src1, fRegD src2) %{
7280 match(Set dst (DivD src1 src2));
7281
7282 ins_cost(FDIV_COST);
7283 format %{ "fdiv.d $dst, $src1, $src2\t#@divD_reg_reg" %}
7284
7285 ins_encode %{
7286 __ fdiv_d(as_FloatRegister($dst$$reg),
7287 as_FloatRegister($src1$$reg),
7288 as_FloatRegister($src2$$reg));
7289 %}
7290
7291 ins_pipe(fp_div_d);
7292 %}
7293
7294 instruct negF_reg_reg(fRegF dst, fRegF src) %{
7295 match(Set dst (NegF src));
7296
7297 ins_cost(XFER_COST);
7298 format %{ "fsgnjn.s $dst, $src, $src\t#@negF_reg_reg" %}
7299
7300 ins_encode %{
7301 __ fneg_s(as_FloatRegister($dst$$reg),
7302 as_FloatRegister($src$$reg));
7303 %}
7304
7305 ins_pipe(fp_uop_s);
7306 %}
7307
7308 instruct negD_reg_reg(fRegD dst, fRegD src) %{
7309 match(Set dst (NegD src));
7310
7311 ins_cost(XFER_COST);
7312 format %{ "fsgnjn.d $dst, $src, $src\t#@negD_reg_reg" %}
7313
7314 ins_encode %{
7315 __ fneg_d(as_FloatRegister($dst$$reg),
7316 as_FloatRegister($src$$reg));
7317 %}
7318
7319 ins_pipe(fp_uop_d);
7320 %}
7321
7322 instruct absI_reg(iRegINoSp dst, iRegIorL2I src) %{
7323 match(Set dst (AbsI src));
7324
7325 ins_cost(ALU_COST * 3);
7326 format %{
7327 "sraiw t0, $src, 0x1f\n\t"
7328 "addw $dst, $src, t0\n\t"
7329 "xorr $dst, $dst, t0\t#@absI_reg"
7330 %}
7331
7332 ins_encode %{
7333 __ sraiw(t0, as_Register($src$$reg), 0x1f);
7334 __ addw(as_Register($dst$$reg), as_Register($src$$reg), t0);
7335 __ xorr(as_Register($dst$$reg), as_Register($dst$$reg), t0);
7336 %}
7337
7338 ins_pipe(ialu_reg_reg);
7339 %}
7340
7341 instruct absL_reg(iRegLNoSp dst, iRegL src) %{
7342 match(Set dst (AbsL src));
7343
7344 ins_cost(ALU_COST * 3);
7345 format %{
7346 "srai t0, $src, 0x3f\n\t"
7347 "add $dst, $src, t0\n\t"
7348 "xorr $dst, $dst, t0\t#@absL_reg"
7349 %}
7350
7351 ins_encode %{
7352 __ srai(t0, as_Register($src$$reg), 0x3f);
7353 __ add(as_Register($dst$$reg), as_Register($src$$reg), t0);
7354 __ xorr(as_Register($dst$$reg), as_Register($dst$$reg), t0);
7355 %}
7356
7357 ins_pipe(ialu_reg_reg);
7358 %}
7359
7360 instruct absF_reg(fRegF dst, fRegF src) %{
7361 match(Set dst (AbsF src));
7362
7363 ins_cost(XFER_COST);
7364 format %{ "fsgnjx.s $dst, $src, $src\t#@absF_reg" %}
7365 ins_encode %{
7366 __ fabs_s(as_FloatRegister($dst$$reg),
7367 as_FloatRegister($src$$reg));
7368 %}
7369
7370 ins_pipe(fp_uop_s);
7371 %}
7372
7373 instruct absD_reg(fRegD dst, fRegD src) %{
7374 match(Set dst (AbsD src));
7375
7376 ins_cost(XFER_COST);
7377 format %{ "fsgnjx.d $dst, $src, $src\t#@absD_reg" %}
7378 ins_encode %{
7379 __ fabs_d(as_FloatRegister($dst$$reg),
7380 as_FloatRegister($src$$reg));
7381 %}
7382
7383 ins_pipe(fp_uop_d);
7384 %}
7385
7386 instruct sqrtF_reg(fRegF dst, fRegF src) %{
7387 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
7388
7389 ins_cost(FSQRT_COST);
7390 format %{ "fsqrt.s $dst, $src\t#@sqrtF_reg" %}
7391 ins_encode %{
7392 __ fsqrt_s(as_FloatRegister($dst$$reg),
7393 as_FloatRegister($src$$reg));
7394 %}
7395
7396 ins_pipe(fp_sqrt_s);
7397 %}
7398
7399 instruct sqrtD_reg(fRegD dst, fRegD src) %{
7400 match(Set dst (SqrtD src));
7401
7402 ins_cost(FSQRT_COST);
7403 format %{ "fsqrt.d $dst, $src\t#@sqrtD_reg" %}
7404 ins_encode %{
7405 __ fsqrt_d(as_FloatRegister($dst$$reg),
7406 as_FloatRegister($src$$reg));
7407 %}
7408
7409 ins_pipe(fp_sqrt_d);
7410 %}
7411
7412 // Arithmetic Instructions End
7413
7414 // ============================================================================
7415 // Logical Instructions
7416
7417 // Register And
7418 instruct andI_reg_reg(iRegINoSp dst, iRegI src1, iRegI src2) %{
7419 match(Set dst (AndI src1 src2));
7420
7421 format %{ "andr $dst, $src1, $src2\t#@andI_reg_reg" %}
7422
7423 ins_cost(ALU_COST);
7424 ins_encode %{
7425 Assembler::CompressibleRegion cr(&_masm);
7426 __ andr(as_Register($dst$$reg),
7427 as_Register($src1$$reg),
7428 as_Register($src2$$reg));
7429 %}
7430
7431 ins_pipe(ialu_reg_reg);
7432 %}
7433
7434 // Immediate And
7435 instruct andI_reg_imm(iRegINoSp dst, iRegI src1, immIAdd src2) %{
7436 match(Set dst (AndI src1 src2));
7437
7438 format %{ "andi $dst, $src1, $src2\t#@andI_reg_imm" %}
7439
7440 ins_cost(ALU_COST);
7441 ins_encode %{
7442 Assembler::CompressibleRegion cr(&_masm);
7443 __ andi(as_Register($dst$$reg),
7444 as_Register($src1$$reg),
7445 (int32_t)($src2$$constant));
7446 %}
7447
7448 ins_pipe(ialu_reg_imm);
7449 %}
7450
7451 // Register Or
7452 instruct orI_reg_reg(iRegINoSp dst, iRegI src1, iRegI src2) %{
7453 match(Set dst (OrI src1 src2));
7454
7455 format %{ "orr $dst, $src1, $src2\t#@orI_reg_reg" %}
7456
7457 ins_cost(ALU_COST);
7458 ins_encode %{
7459 Assembler::CompressibleRegion cr(&_masm);
7460 __ orr(as_Register($dst$$reg),
7461 as_Register($src1$$reg),
7462 as_Register($src2$$reg));
7463 %}
7464
7465 ins_pipe(ialu_reg_reg);
7466 %}
7467
7468 // Immediate Or
7469 instruct orI_reg_imm(iRegINoSp dst, iRegI src1, immIAdd src2) %{
7470 match(Set dst (OrI src1 src2));
7471
7472 format %{ "ori $dst, $src1, $src2\t#@orI_reg_imm" %}
7473
7474 ins_cost(ALU_COST);
7475 ins_encode %{
7476 __ ori(as_Register($dst$$reg),
7477 as_Register($src1$$reg),
7478 (int32_t)($src2$$constant));
7479 %}
7480
7481 ins_pipe(ialu_reg_imm);
7482 %}
7483
7484 // Register Xor
7485 instruct xorI_reg_reg(iRegINoSp dst, iRegI src1, iRegI src2) %{
7486 match(Set dst (XorI src1 src2));
7487
7488 format %{ "xorr $dst, $src1, $src2\t#@xorI_reg_reg" %}
7489
7490 ins_cost(ALU_COST);
7491 ins_encode %{
7492 Assembler::CompressibleRegion cr(&_masm);
7493 __ xorr(as_Register($dst$$reg),
7494 as_Register($src1$$reg),
7495 as_Register($src2$$reg));
7496 %}
7497
7498 ins_pipe(ialu_reg_reg);
7499 %}
7500
7501 // Immediate Xor
7502 instruct xorI_reg_imm(iRegINoSp dst, iRegI src1, immIAdd src2) %{
7503 match(Set dst (XorI src1 src2));
7504
7505 format %{ "xori $dst, $src1, $src2\t#@xorI_reg_imm" %}
7506
7507 ins_cost(ALU_COST);
7508 ins_encode %{
7509 __ xori(as_Register($dst$$reg),
7510 as_Register($src1$$reg),
7511 (int32_t)($src2$$constant));
7512 %}
7513
7514 ins_pipe(ialu_reg_imm);
7515 %}
7516
7517 // Register And Long
7518 instruct andL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
7519 match(Set dst (AndL src1 src2));
7520
7521 format %{ "andr $dst, $src1, $src2\t#@andL_reg_reg" %}
7522
7523 ins_cost(ALU_COST);
7524 ins_encode %{
7525 Assembler::CompressibleRegion cr(&_masm);
7526 __ andr(as_Register($dst$$reg),
7527 as_Register($src1$$reg),
7528 as_Register($src2$$reg));
7529 %}
7530
7531 ins_pipe(ialu_reg_reg);
7532 %}
7533
7534 // Immediate And Long
7535 instruct andL_reg_imm(iRegLNoSp dst, iRegL src1, immLAdd src2) %{
7536 match(Set dst (AndL src1 src2));
7537
7538 format %{ "andi $dst, $src1, $src2\t#@andL_reg_imm" %}
7539
7540 ins_cost(ALU_COST);
7541 ins_encode %{
7542 Assembler::CompressibleRegion cr(&_masm);
7543 __ andi(as_Register($dst$$reg),
7544 as_Register($src1$$reg),
7545 (int32_t)($src2$$constant));
7546 %}
7547
7548 ins_pipe(ialu_reg_imm);
7549 %}
7550
7551 // Register Or Long
7552 instruct orL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
7553 match(Set dst (OrL src1 src2));
7554
7555 format %{ "orr $dst, $src1, $src2\t#@orL_reg_reg" %}
7556
7557 ins_cost(ALU_COST);
7558 ins_encode %{
7559 Assembler::CompressibleRegion cr(&_masm);
7560 __ orr(as_Register($dst$$reg),
7561 as_Register($src1$$reg),
7562 as_Register($src2$$reg));
7563 %}
7564
7565 ins_pipe(ialu_reg_reg);
7566 %}
7567
7568 // Immediate Or Long
7569 instruct orL_reg_imm(iRegLNoSp dst, iRegL src1, immLAdd src2) %{
7570 match(Set dst (OrL src1 src2));
7571
7572 format %{ "ori $dst, $src1, $src2\t#@orL_reg_imm" %}
7573
7574 ins_cost(ALU_COST);
7575 ins_encode %{
7576 __ ori(as_Register($dst$$reg),
7577 as_Register($src1$$reg),
7578 (int32_t)($src2$$constant));
7579 %}
7580
7581 ins_pipe(ialu_reg_imm);
7582 %}
7583
7584 // Register Xor Long
7585 instruct xorL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
7586 match(Set dst (XorL src1 src2));
7587
7588 format %{ "xorr $dst, $src1, $src2\t#@xorL_reg_reg" %}
7589
7590 ins_cost(ALU_COST);
7591 ins_encode %{
7592 Assembler::CompressibleRegion cr(&_masm);
7593 __ xorr(as_Register($dst$$reg),
7594 as_Register($src1$$reg),
7595 as_Register($src2$$reg));
7596 %}
7597
7598 ins_pipe(ialu_reg_reg);
7599 %}
7600
7601 // Immediate Xor Long
7602 instruct xorL_reg_imm(iRegLNoSp dst, iRegL src1, immLAdd src2) %{
7603 match(Set dst (XorL src1 src2));
7604
7605 ins_cost(ALU_COST);
7606 format %{ "xori $dst, $src1, $src2\t#@xorL_reg_imm" %}
7607
7608 ins_encode %{
7609 __ xori(as_Register($dst$$reg),
7610 as_Register($src1$$reg),
7611 (int32_t)($src2$$constant));
7612 %}
7613
7614 ins_pipe(ialu_reg_imm);
7615 %}
7616
7617 // ============================================================================
7618 // BSWAP Instructions
7619
7620 instruct bytes_reverse_int(iRegINoSp dst, iRegIorL2I src, rFlagsReg cr) %{
7621 match(Set dst (ReverseBytesI src));
7622 effect(TEMP cr);
7623
7624 ins_cost(ALU_COST * 13);
7625 format %{ "revb_w_w $dst, $src\t#@bytes_reverse_int" %}
7626
7627 ins_encode %{
7628 __ revb_w_w(as_Register($dst$$reg), as_Register($src$$reg));
7629 %}
7630
7631 ins_pipe(ialu_reg);
7632 %}
7633
7634 instruct bytes_reverse_long(iRegLNoSp dst, iRegL src, rFlagsReg cr) %{
7635 match(Set dst (ReverseBytesL src));
7636 effect(TEMP cr);
7637
7638 ins_cost(ALU_COST * 29);
7639 format %{ "revb $dst, $src\t#@bytes_reverse_long" %}
7640
7641 ins_encode %{
7642 __ revb(as_Register($dst$$reg), as_Register($src$$reg));
7643 %}
7644
7645 ins_pipe(ialu_reg);
7646 %}
7647
7648 instruct bytes_reverse_unsigned_short(iRegINoSp dst, iRegIorL2I src) %{
7649 match(Set dst (ReverseBytesUS src));
7650
7651 ins_cost(ALU_COST * 5);
7652 format %{ "revb_h_h_u $dst, $src\t#@bytes_reverse_unsigned_short" %}
7653
7654 ins_encode %{
7655 __ revb_h_h_u(as_Register($dst$$reg), as_Register($src$$reg));
7656 %}
7657
7658 ins_pipe(ialu_reg);
7659 %}
7660
7661 instruct bytes_reverse_short(iRegINoSp dst, iRegIorL2I src) %{
7662 match(Set dst (ReverseBytesS src));
7663
7664 ins_cost(ALU_COST * 5);
7665 format %{ "revb_h_h $dst, $src\t#@bytes_reverse_short" %}
7666
7667 ins_encode %{
7668 __ revb_h_h(as_Register($dst$$reg), as_Register($src$$reg));
7669 %}
7670
7671 ins_pipe(ialu_reg);
7672 %}
7673
7674 // ============================================================================
7675 // MemBar Instruction
7676
7677 instruct load_fence() %{
7678 match(LoadFence);
7679 ins_cost(ALU_COST);
7680
7681 format %{ "#@load_fence" %}
7682
7683 ins_encode %{
7684 __ membar(MacroAssembler::LoadLoad | MacroAssembler::LoadStore);
7685 %}
7686 ins_pipe(pipe_serial);
7687 %}
7688
7689 instruct membar_acquire() %{
7690 match(MemBarAcquire);
7691 ins_cost(ALU_COST);
7692
7693 format %{ "#@membar_acquire\n\t"
7694 "fence ir iorw" %}
7695
7696 ins_encode %{
7697 __ block_comment("membar_acquire");
7698 __ membar(MacroAssembler::LoadLoad | MacroAssembler::LoadStore);
7699 %}
7700
7701 ins_pipe(pipe_serial);
7702 %}
7703
7704 instruct membar_acquire_lock() %{
7705 match(MemBarAcquireLock);
7706 ins_cost(0);
7707
7708 format %{ "#@membar_acquire_lock (elided)" %}
7709
7710 ins_encode %{
7711 __ block_comment("membar_acquire_lock (elided)");
7712 %}
7713
7714 ins_pipe(pipe_serial);
7715 %}
7716
7717 instruct store_fence() %{
7718 match(StoreFence);
7719 ins_cost(ALU_COST);
7720
7721 format %{ "#@store_fence" %}
7722
7723 ins_encode %{
7724 __ membar(MacroAssembler::LoadStore | MacroAssembler::StoreStore);
7725 %}
7726 ins_pipe(pipe_serial);
7727 %}
7728
7729 instruct membar_release() %{
7730 match(MemBarRelease);
7731 ins_cost(ALU_COST);
7732
7733 format %{ "#@membar_release\n\t"
7734 "fence iorw ow" %}
7735
7736 ins_encode %{
7737 __ block_comment("membar_release");
7738 __ membar(MacroAssembler::LoadStore | MacroAssembler::StoreStore);
7739 %}
7740 ins_pipe(pipe_serial);
7741 %}
7742
7743 instruct membar_storestore() %{
7744 match(MemBarStoreStore);
7745 match(StoreStoreFence);
7746 ins_cost(ALU_COST);
7747
7748 format %{ "MEMBAR-store-store\t#@membar_storestore" %}
7749
7750 ins_encode %{
7751 __ membar(MacroAssembler::StoreStore);
7752 %}
7753 ins_pipe(pipe_serial);
7754 %}
7755
7756 instruct membar_release_lock() %{
7757 match(MemBarReleaseLock);
7758 ins_cost(0);
7759
7760 format %{ "#@membar_release_lock (elided)" %}
7761
7762 ins_encode %{
7763 __ block_comment("membar_release_lock (elided)");
7764 %}
7765
7766 ins_pipe(pipe_serial);
7767 %}
7768
7769 instruct membar_volatile() %{
7770 match(MemBarVolatile);
7771 ins_cost(ALU_COST);
7772
7773 format %{ "#@membar_volatile\n\t"
7774 "fence iorw iorw"%}
7775
7776 ins_encode %{
7777 __ block_comment("membar_volatile");
7778 __ membar(MacroAssembler::StoreLoad);
7779 %}
7780
7781 ins_pipe(pipe_serial);
7782 %}
7783
7784 // ============================================================================
7785 // Cast Instructions (Java-level type cast)
7786
7787 instruct castX2P(iRegPNoSp dst, iRegL src) %{
7788 match(Set dst (CastX2P src));
7789
7790 ins_cost(ALU_COST);
7791 format %{ "mv $dst, $src\t# long -> ptr, #@castX2P" %}
7792
7793 ins_encode %{
7794 Assembler::CompressibleRegion cr(&_masm);
7795 if ($dst$$reg != $src$$reg) {
7796 __ mv(as_Register($dst$$reg), as_Register($src$$reg));
7797 }
7798 %}
7799
7800 ins_pipe(ialu_reg);
7801 %}
7802
7803 instruct castP2X(iRegLNoSp dst, iRegP src) %{
7804 match(Set dst (CastP2X src));
7805
7806 ins_cost(ALU_COST);
7807 format %{ "mv $dst, $src\t# ptr -> long, #@castP2X" %}
7808
7809 ins_encode %{
7810 Assembler::CompressibleRegion cr(&_masm);
7811 if ($dst$$reg != $src$$reg) {
7812 __ mv(as_Register($dst$$reg), as_Register($src$$reg));
7813 }
7814 %}
7815
7816 ins_pipe(ialu_reg);
7817 %}
7818
7819 instruct castPP(iRegPNoSp dst)
7820 %{
7821 match(Set dst (CastPP dst));
7822 ins_cost(0);
7823
7824 size(0);
7825 format %{ "# castPP of $dst, #@castPP" %}
7826 ins_encode(/* empty encoding */);
7827 ins_pipe(pipe_class_empty);
7828 %}
7829
7830 instruct castLL(iRegL dst)
7831 %{
7832 match(Set dst (CastLL dst));
7833
7834 size(0);
7835 format %{ "# castLL of $dst, #@castLL" %}
7836 ins_encode(/* empty encoding */);
7837 ins_cost(0);
7838 ins_pipe(pipe_class_empty);
7839 %}
7840
7841 instruct castII(iRegI dst)
7842 %{
7843 match(Set dst (CastII dst));
7844
7845 size(0);
7846 format %{ "# castII of $dst, #@castII" %}
7847 ins_encode(/* empty encoding */);
7848 ins_cost(0);
7849 ins_pipe(pipe_class_empty);
7850 %}
7851
7852 instruct checkCastPP(iRegPNoSp dst)
7853 %{
7854 match(Set dst (CheckCastPP dst));
7855
7856 size(0);
7857 ins_cost(0);
7858 format %{ "# checkcastPP of $dst, #@checkCastPP" %}
7859 ins_encode(/* empty encoding */);
7860 ins_pipe(pipe_class_empty);
7861 %}
7862
7863 instruct castFF(fRegF dst)
7864 %{
7865 match(Set dst (CastFF dst));
7866
7867 size(0);
7868 format %{ "# castFF of $dst" %}
7869 ins_encode(/* empty encoding */);
7870 ins_cost(0);
7871 ins_pipe(pipe_class_empty);
7872 %}
7873
7874 instruct castDD(fRegD dst)
7875 %{
7876 match(Set dst (CastDD dst));
7877
7878 size(0);
7879 format %{ "# castDD of $dst" %}
7880 ins_encode(/* empty encoding */);
7881 ins_cost(0);
7882 ins_pipe(pipe_class_empty);
7883 %}
7884
7885 instruct castVV(vReg dst)
7886 %{
7887 match(Set dst (CastVV dst));
7888
7889 size(0);
7890 format %{ "# castVV of $dst" %}
7891 ins_encode(/* empty encoding */);
7892 ins_cost(0);
7893 ins_pipe(pipe_class_empty);
7894 %}
7895
7896 // ============================================================================
7897 // Convert Instructions
7898
7899 // int to bool
7900 instruct convI2Bool(iRegINoSp dst, iRegI src)
7901 %{
7902 match(Set dst (Conv2B src));
7903
7904 ins_cost(ALU_COST);
7905 format %{ "snez $dst, $src\t#@convI2Bool" %}
7906
7907 ins_encode %{
7908 __ snez(as_Register($dst$$reg), as_Register($src$$reg));
7909 %}
7910
7911 ins_pipe(ialu_reg);
7912 %}
7913
7914 // pointer to bool
7915 instruct convP2Bool(iRegINoSp dst, iRegP src)
7916 %{
7917 match(Set dst (Conv2B src));
7918
7919 ins_cost(ALU_COST);
7920 format %{ "snez $dst, $src\t#@convP2Bool" %}
7921
7922 ins_encode %{
7923 __ snez(as_Register($dst$$reg), as_Register($src$$reg));
7924 %}
7925
7926 ins_pipe(ialu_reg);
7927 %}
7928
7929 // int <-> long
7930
7931 instruct convI2L_reg_reg(iRegLNoSp dst, iRegIorL2I src)
7932 %{
7933 match(Set dst (ConvI2L src));
7934
7935 ins_cost(ALU_COST);
7936 format %{ "addw $dst, $src, zr\t#@convI2L_reg_reg" %}
7937 ins_encode %{
7938 __ addw(as_Register($dst$$reg), as_Register($src$$reg), zr);
7939 %}
7940 ins_pipe(ialu_reg);
7941 %}
7942
7943 instruct convL2I_reg(iRegINoSp dst, iRegL src) %{
7944 match(Set dst (ConvL2I src));
7945
7946 ins_cost(ALU_COST);
7947 format %{ "addw $dst, $src, zr\t#@convL2I_reg" %}
7948
7949 ins_encode %{
7950 __ addw(as_Register($dst$$reg), as_Register($src$$reg), zr);
7951 %}
7952
7953 ins_pipe(ialu_reg);
7954 %}
7955
7956 // int to unsigned long (Zero-extend)
7957 instruct convI2UL_reg_reg(iRegLNoSp dst, iRegIorL2I src, immL_32bits mask)
7958 %{
7959 match(Set dst (AndL (ConvI2L src) mask));
7960
7961 ins_cost(ALU_COST * 2);
7962 format %{ "zero_extend $dst, $src, 32\t# i2ul, #@convI2UL_reg_reg" %}
7963
7964 ins_encode %{
7965 Assembler::CompressibleRegion cr(&_masm);
7966 __ zero_extend(as_Register($dst$$reg), as_Register($src$$reg), 32);
7967 %}
7968
7969 ins_pipe(ialu_reg_shift);
7970 %}
7971
7972 // float <-> double
7973
7974 instruct convF2D_reg(fRegD dst, fRegF src) %{
7975 match(Set dst (ConvF2D src));
7976
7977 ins_cost(XFER_COST);
7978 format %{ "fcvt.d.s $dst, $src\t#@convF2D_reg" %}
7979
7980 ins_encode %{
7981 __ fcvt_d_s(as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg));
7982 %}
7983
7984 ins_pipe(fp_f2d);
7985 %}
7986
7987 instruct convD2F_reg(fRegF dst, fRegD src) %{
7988 match(Set dst (ConvD2F src));
7989
7990 ins_cost(XFER_COST);
7991 format %{ "fcvt.s.d $dst, $src\t#@convD2F_reg" %}
7992
7993 ins_encode %{
7994 __ fcvt_s_d(as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg));
7995 %}
7996
7997 ins_pipe(fp_d2f);
7998 %}
7999
8000 // float <-> int
8001
8002 instruct convF2I_reg_reg(iRegINoSp dst, fRegF src) %{
8003 match(Set dst (ConvF2I src));
8004
8005 ins_cost(XFER_COST);
8006 format %{ "fcvt.w.s $dst, $src\t#@convF2I_reg_reg" %}
8007
8008 ins_encode %{
8009 __ fcvt_w_s_safe($dst$$Register, $src$$FloatRegister);
8010 %}
8011
8012 ins_pipe(fp_f2i);
8013 %}
8014
8015 instruct convI2F_reg_reg(fRegF dst, iRegIorL2I src) %{
8016 match(Set dst (ConvI2F src));
8017
8018 ins_cost(XFER_COST);
8019 format %{ "fcvt.s.w $dst, $src\t#@convI2F_reg_reg" %}
8020
8021 ins_encode %{
8022 __ fcvt_s_w(as_FloatRegister($dst$$reg), as_Register($src$$reg));
8023 %}
8024
8025 ins_pipe(fp_i2f);
8026 %}
8027
8028 // float <-> long
8029
8030 instruct convF2L_reg_reg(iRegLNoSp dst, fRegF src) %{
8031 match(Set dst (ConvF2L src));
8032
8033 ins_cost(XFER_COST);
8034 format %{ "fcvt.l.s $dst, $src\t#@convF2L_reg_reg" %}
8035
8036 ins_encode %{
8037 __ fcvt_l_s_safe($dst$$Register, $src$$FloatRegister);
8038 %}
8039
8040 ins_pipe(fp_f2l);
8041 %}
8042
8043 instruct convL2F_reg_reg(fRegF dst, iRegL src) %{
8044 match(Set dst (ConvL2F src));
8045
8046 ins_cost(XFER_COST);
8047 format %{ "fcvt.s.l $dst, $src\t#@convL2F_reg_reg" %}
8048
8049 ins_encode %{
8050 __ fcvt_s_l(as_FloatRegister($dst$$reg), as_Register($src$$reg));
8051 %}
8052
8053 ins_pipe(fp_l2f);
8054 %}
8055
8056 // double <-> int
8057
8058 instruct convD2I_reg_reg(iRegINoSp dst, fRegD src) %{
8059 match(Set dst (ConvD2I src));
8060
8061 ins_cost(XFER_COST);
8062 format %{ "fcvt.w.d $dst, $src\t#@convD2I_reg_reg" %}
8063
8064 ins_encode %{
8065 __ fcvt_w_d_safe($dst$$Register, $src$$FloatRegister);
8066 %}
8067
8068 ins_pipe(fp_d2i);
8069 %}
8070
8071 instruct convI2D_reg_reg(fRegD dst, iRegIorL2I src) %{
8072 match(Set dst (ConvI2D src));
8073
8074 ins_cost(XFER_COST);
8075 format %{ "fcvt.d.w $dst, $src\t#@convI2D_reg_reg" %}
8076
8077 ins_encode %{
8078 __ fcvt_d_w(as_FloatRegister($dst$$reg), as_Register($src$$reg));
8079 %}
8080
8081 ins_pipe(fp_i2d);
8082 %}
8083
8084 // double <-> long
8085
8086 instruct convD2L_reg_reg(iRegLNoSp dst, fRegD src) %{
8087 match(Set dst (ConvD2L src));
8088
8089 ins_cost(XFER_COST);
8090 format %{ "fcvt.l.d $dst, $src\t#@convD2L_reg_reg" %}
8091
8092 ins_encode %{
8093 __ fcvt_l_d_safe($dst$$Register, $src$$FloatRegister);
8094 %}
8095
8096 ins_pipe(fp_d2l);
8097 %}
8098
8099 instruct convL2D_reg_reg(fRegD dst, iRegL src) %{
8100 match(Set dst (ConvL2D src));
8101
8102 ins_cost(XFER_COST);
8103 format %{ "fcvt.d.l $dst, $src\t#@convL2D_reg_reg" %}
8104
8105 ins_encode %{
8106 __ fcvt_d_l(as_FloatRegister($dst$$reg), as_Register($src$$reg));
8107 %}
8108
8109 ins_pipe(fp_l2d);
8110 %}
8111
8112 // Convert oop into int for vectors alignment masking
8113 instruct convP2I(iRegINoSp dst, iRegP src) %{
8114 match(Set dst (ConvL2I (CastP2X src)));
8115
8116 ins_cost(ALU_COST * 2);
8117 format %{ "zero_extend $dst, $src, 32\t# ptr -> int, #@convP2I" %}
8118
8119 ins_encode %{
8120 Assembler::CompressibleRegion cr(&_masm);
8121 __ zero_extend($dst$$Register, $src$$Register, 32);
8122 %}
8123
8124 ins_pipe(ialu_reg);
8125 %}
8126
8127 // Convert compressed oop into int for vectors alignment masking
8128 // in case of 32bit oops (heap < 4Gb).
8129 instruct convN2I(iRegINoSp dst, iRegN src)
8130 %{
8131 predicate(CompressedOops::shift() == 0);
8132 match(Set dst (ConvL2I (CastP2X (DecodeN src))));
8133
8134 ins_cost(ALU_COST);
8135 format %{ "mv $dst, $src\t# compressed ptr -> int, #@convN2I" %}
8136
8137 ins_encode %{
8138 Assembler::CompressibleRegion cr(&_masm);
8139 __ mv($dst$$Register, $src$$Register);
8140 %}
8141
8142 ins_pipe(ialu_reg);
8143 %}
8144
8145 // Convert oop pointer into compressed form
8146 instruct encodeHeapOop(iRegNNoSp dst, iRegP src) %{
8147 match(Set dst (EncodeP src));
8148 ins_cost(ALU_COST);
8149 format %{ "encode_heap_oop $dst, $src\t#@encodeHeapOop" %}
8150 ins_encode %{
8151 Register s = $src$$Register;
8152 Register d = $dst$$Register;
8153 __ encode_heap_oop(d, s);
8154 %}
8155 ins_pipe(ialu_reg);
8156 %}
8157
8158 instruct decodeHeapOop(iRegPNoSp dst, iRegN src) %{
8159 predicate(n->bottom_type()->is_ptr()->ptr() != TypePtr::NotNull &&
8160 n->bottom_type()->is_ptr()->ptr() != TypePtr::Constant);
8161 match(Set dst (DecodeN src));
8162
8163 ins_cost(0);
8164 format %{ "decode_heap_oop $dst, $src\t#@decodeHeapOop" %}
8165 ins_encode %{
8166 Register s = $src$$Register;
8167 Register d = $dst$$Register;
8168 __ decode_heap_oop(d, s);
8169 %}
8170 ins_pipe(ialu_reg);
8171 %}
8172
8173 instruct decodeHeapOop_not_null(iRegPNoSp dst, iRegN src) %{
8174 predicate(n->bottom_type()->is_ptr()->ptr() == TypePtr::NotNull ||
8175 n->bottom_type()->is_ptr()->ptr() == TypePtr::Constant);
8176 match(Set dst (DecodeN src));
8177
8178 ins_cost(0);
8179 format %{ "decode_heap_oop_not_null $dst, $src\t#@decodeHeapOop_not_null" %}
8180 ins_encode %{
8181 Register s = $src$$Register;
8182 Register d = $dst$$Register;
8183 __ decode_heap_oop_not_null(d, s);
8184 %}
8185 ins_pipe(ialu_reg);
8186 %}
8187
8188 // Convert klass pointer into compressed form.
8189 instruct encodeKlass_not_null(iRegNNoSp dst, iRegP src) %{
8190 match(Set dst (EncodePKlass src));
8191
8192 ins_cost(ALU_COST);
8193 format %{ "encode_klass_not_null $dst, $src\t#@encodeKlass_not_null" %}
8194
8195 ins_encode %{
8196 Register src_reg = as_Register($src$$reg);
8197 Register dst_reg = as_Register($dst$$reg);
8198 __ encode_klass_not_null(dst_reg, src_reg, t0);
8199 %}
8200
8201 ins_pipe(ialu_reg);
8202 %}
8203
8204 instruct decodeKlass_not_null(iRegPNoSp dst, iRegN src, iRegPNoSp tmp) %{
8205 match(Set dst (DecodeNKlass src));
8206
8207 effect(TEMP tmp);
8208
8209 ins_cost(ALU_COST);
8210 format %{ "decode_klass_not_null $dst, $src\t#@decodeKlass_not_null" %}
8211
8212 ins_encode %{
8213 Register src_reg = as_Register($src$$reg);
8214 Register dst_reg = as_Register($dst$$reg);
8215 Register tmp_reg = as_Register($tmp$$reg);
8216 __ decode_klass_not_null(dst_reg, src_reg, tmp_reg);
8217 %}
8218
8219 ins_pipe(ialu_reg);
8220 %}
8221
8222 // stack <-> reg and reg <-> reg shuffles with no conversion
8223
8224 instruct MoveF2I_stack_reg(iRegINoSp dst, stackSlotF src) %{
8225
8226 match(Set dst (MoveF2I src));
8227
8228 effect(DEF dst, USE src);
8229
8230 ins_cost(LOAD_COST);
8231
8232 format %{ "lw $dst, $src\t#@MoveF2I_stack_reg" %}
8233
8234 ins_encode %{
8235 Assembler::CompressibleRegion cr(&_masm);
8236 __ lw(as_Register($dst$$reg), Address(sp, $src$$disp));
8237 %}
8238
8239 ins_pipe(iload_reg_reg);
8240
8241 %}
8242
8243 instruct MoveI2F_stack_reg(fRegF dst, stackSlotI src) %{
8244
8245 match(Set dst (MoveI2F src));
8246
8247 effect(DEF dst, USE src);
8248
8249 ins_cost(LOAD_COST);
8250
8251 format %{ "flw $dst, $src\t#@MoveI2F_stack_reg" %}
8252
8253 ins_encode %{
8254 __ flw(as_FloatRegister($dst$$reg), Address(sp, $src$$disp));
8255 %}
8256
8257 ins_pipe(pipe_class_memory);
8258
8259 %}
8260
8261 instruct MoveD2L_stack_reg(iRegLNoSp dst, stackSlotD src) %{
8262
8263 match(Set dst (MoveD2L src));
8264
8265 effect(DEF dst, USE src);
8266
8267 ins_cost(LOAD_COST);
8268
8269 format %{ "ld $dst, $src\t#@MoveD2L_stack_reg" %}
8270
8271 ins_encode %{
8272 Assembler::CompressibleRegion cr(&_masm);
8273 __ ld(as_Register($dst$$reg), Address(sp, $src$$disp));
8274 %}
8275
8276 ins_pipe(iload_reg_reg);
8277
8278 %}
8279
8280 instruct MoveL2D_stack_reg(fRegD dst, stackSlotL src) %{
8281
8282 match(Set dst (MoveL2D src));
8283
8284 effect(DEF dst, USE src);
8285
8286 ins_cost(LOAD_COST);
8287
8288 format %{ "fld $dst, $src\t#@MoveL2D_stack_reg" %}
8289
8290 ins_encode %{
8291 Assembler::CompressibleRegion cr(&_masm);
8292 __ fld(as_FloatRegister($dst$$reg), Address(sp, $src$$disp));
8293 %}
8294
8295 ins_pipe(pipe_class_memory);
8296
8297 %}
8298
8299 instruct MoveF2I_reg_stack(stackSlotI dst, fRegF src) %{
8300
8301 match(Set dst (MoveF2I src));
8302
8303 effect(DEF dst, USE src);
8304
8305 ins_cost(STORE_COST);
8306
8307 format %{ "fsw $src, $dst\t#@MoveF2I_reg_stack" %}
8308
8309 ins_encode %{
8310 __ fsw(as_FloatRegister($src$$reg), Address(sp, $dst$$disp));
8311 %}
8312
8313 ins_pipe(pipe_class_memory);
8314
8315 %}
8316
8317 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{
8318
8319 match(Set dst (MoveI2F src));
8320
8321 effect(DEF dst, USE src);
8322
8323 ins_cost(STORE_COST);
8324
8325 format %{ "sw $src, $dst\t#@MoveI2F_reg_stack" %}
8326
8327 ins_encode %{
8328 Assembler::CompressibleRegion cr(&_masm);
8329 __ sw(as_Register($src$$reg), Address(sp, $dst$$disp));
8330 %}
8331
8332 ins_pipe(istore_reg_reg);
8333
8334 %}
8335
8336 instruct MoveD2L_reg_stack(stackSlotL dst, fRegD src) %{
8337
8338 match(Set dst (MoveD2L src));
8339
8340 effect(DEF dst, USE src);
8341
8342 ins_cost(STORE_COST);
8343
8344 format %{ "fsd $dst, $src\t#@MoveD2L_reg_stack" %}
8345
8346 ins_encode %{
8347 Assembler::CompressibleRegion cr(&_masm);
8348 __ fsd(as_FloatRegister($src$$reg), Address(sp, $dst$$disp));
8349 %}
8350
8351 ins_pipe(pipe_class_memory);
8352
8353 %}
8354
8355 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{
8356
8357 match(Set dst (MoveL2D src));
8358
8359 effect(DEF dst, USE src);
8360
8361 ins_cost(STORE_COST);
8362
8363 format %{ "sd $src, $dst\t#@MoveL2D_reg_stack" %}
8364
8365 ins_encode %{
8366 Assembler::CompressibleRegion cr(&_masm);
8367 __ sd(as_Register($src$$reg), Address(sp, $dst$$disp));
8368 %}
8369
8370 ins_pipe(istore_reg_reg);
8371
8372 %}
8373
8374 instruct MoveF2I_reg_reg(iRegINoSp dst, fRegF src) %{
8375
8376 match(Set dst (MoveF2I src));
8377
8378 effect(DEF dst, USE src);
8379
8380 ins_cost(XFER_COST);
8381
8382 format %{ "fmv.x.w $dst, $src\t#@MoveL2D_reg_stack" %}
8383
8384 ins_encode %{
8385 __ fmv_x_w(as_Register($dst$$reg), as_FloatRegister($src$$reg));
8386 %}
8387
8388 ins_pipe(fp_f2i);
8389
8390 %}
8391
8392 instruct MoveI2F_reg_reg(fRegF dst, iRegI src) %{
8393
8394 match(Set dst (MoveI2F src));
8395
8396 effect(DEF dst, USE src);
8397
8398 ins_cost(XFER_COST);
8399
8400 format %{ "fmv.w.x $dst, $src\t#@MoveI2F_reg_reg" %}
8401
8402 ins_encode %{
8403 __ fmv_w_x(as_FloatRegister($dst$$reg), as_Register($src$$reg));
8404 %}
8405
8406 ins_pipe(fp_i2f);
8407
8408 %}
8409
8410 instruct MoveD2L_reg_reg(iRegLNoSp dst, fRegD src) %{
8411
8412 match(Set dst (MoveD2L src));
8413
8414 effect(DEF dst, USE src);
8415
8416 ins_cost(XFER_COST);
8417
8418 format %{ "fmv.x.d $dst, $src\t#@MoveD2L_reg_reg" %}
8419
8420 ins_encode %{
8421 __ fmv_x_d(as_Register($dst$$reg), as_FloatRegister($src$$reg));
8422 %}
8423
8424 ins_pipe(fp_d2l);
8425
8426 %}
8427
8428 instruct MoveL2D_reg_reg(fRegD dst, iRegL src) %{
8429
8430 match(Set dst (MoveL2D src));
8431
8432 effect(DEF dst, USE src);
8433
8434 ins_cost(XFER_COST);
8435
8436 format %{ "fmv.d.x $dst, $src\t#@MoveD2L_reg_reg" %}
8437
8438 ins_encode %{
8439 __ fmv_d_x(as_FloatRegister($dst$$reg), as_Register($src$$reg));
8440 %}
8441
8442 ins_pipe(fp_l2d);
8443 %}
8444
8445 // ============================================================================
8446 // Compare Instructions which set the result float comparisons in dest register.
8447
8448 instruct cmpF3_reg_reg(iRegINoSp dst, fRegF op1, fRegF op2)
8449 %{
8450 match(Set dst (CmpF3 op1 op2));
8451
8452 ins_cost(XFER_COST * 2 + BRANCH_COST + ALU_COST);
8453 format %{ "flt.s $dst, $op2, $op1\t#@cmpF3_reg_reg\n\t"
8454 "bgtz $dst, done\n\t"
8455 "feq.s $dst, $op1, $op2\n\t"
8456 "addi $dst, $dst, -1\t#@cmpF3_reg_reg"
8457 %}
8458
8459 ins_encode %{
8460 // we want -1 for unordered or less than, 0 for equal and 1 for greater than.
8461 __ float_compare(as_Register($dst$$reg), as_FloatRegister($op1$$reg),
8462 as_FloatRegister($op2$$reg), -1 /*unordered_result < 0*/);
8463 %}
8464
8465 ins_pipe(pipe_class_default);
8466 %}
8467
8468 instruct cmpD3_reg_reg(iRegINoSp dst, fRegD op1, fRegD op2)
8469 %{
8470 match(Set dst (CmpD3 op1 op2));
8471
8472 ins_cost(XFER_COST * 2 + BRANCH_COST + ALU_COST);
8473 format %{ "flt.d $dst, $op2, $op1\t#@cmpD3_reg_reg\n\t"
8474 "bgtz $dst, done\n\t"
8475 "feq.d $dst, $op1, $op2\n\t"
8476 "addi $dst, $dst, -1\t#@cmpD3_reg_reg"
8477 %}
8478
8479 ins_encode %{
8480 // we want -1 for unordered or less than, 0 for equal and 1 for greater than.
8481 __ double_compare(as_Register($dst$$reg), as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg), -1 /*unordered_result < 0*/);
8482 %}
8483
8484 ins_pipe(pipe_class_default);
8485 %}
8486
8487 instruct cmpL3_reg_reg(iRegINoSp dst, iRegL op1, iRegL op2)
8488 %{
8489 match(Set dst (CmpL3 op1 op2));
8490
8491 ins_cost(ALU_COST * 3 + BRANCH_COST);
8492 format %{ "slt $dst, $op2, $op1\t#@cmpL3_reg_reg\n\t"
8493 "bnez $dst, done\n\t"
8494 "slt $dst, $op1, $op2\n\t"
8495 "neg $dst, $dst\t#@cmpL3_reg_reg"
8496 %}
8497 ins_encode %{
8498 __ cmp_l2i(t0, as_Register($op1$$reg), as_Register($op2$$reg));
8499 __ mv(as_Register($dst$$reg), t0);
8500 %}
8501
8502 ins_pipe(pipe_class_default);
8503 %}
8504
8505 instruct cmpLTMask_reg_reg(iRegINoSp dst, iRegI p, iRegI q)
8506 %{
8507 match(Set dst (CmpLTMask p q));
8508
8509 ins_cost(2 * ALU_COST);
8510
8511 format %{ "slt $dst, $p, $q\t#@cmpLTMask_reg_reg\n\t"
8512 "subw $dst, zr, $dst\t#@cmpLTMask_reg_reg"
8513 %}
8514
8515 ins_encode %{
8516 __ slt(as_Register($dst$$reg), as_Register($p$$reg), as_Register($q$$reg));
8517 __ subw(as_Register($dst$$reg), zr, as_Register($dst$$reg));
8518 %}
8519
8520 ins_pipe(ialu_reg_reg);
8521 %}
8522
8523 instruct cmpLTMask_reg_zero(iRegINoSp dst, iRegIorL2I op, immI0 zero)
8524 %{
8525 match(Set dst (CmpLTMask op zero));
8526
8527 ins_cost(ALU_COST);
8528
8529 format %{ "sraiw $dst, $dst, 31\t#@cmpLTMask_reg_reg" %}
8530
8531 ins_encode %{
8532 __ sraiw(as_Register($dst$$reg), as_Register($op$$reg), 31);
8533 %}
8534
8535 ins_pipe(ialu_reg_shift);
8536 %}
8537
8538
8539 // ============================================================================
8540 // Max and Min
8541
8542 instruct minI_rReg(iRegINoSp dst, iRegI src1, iRegI src2)
8543 %{
8544 match(Set dst (MinI src1 src2));
8545
8546 effect(DEF dst, USE src1, USE src2);
8547
8548 ins_cost(BRANCH_COST + ALU_COST * 2);
8549 format %{
8550 "ble $src1, $src2, Lsrc1.\t#@minI_rReg\n\t"
8551 "mv $dst, $src2\n\t"
8552 "j Ldone\n\t"
8553 "bind Lsrc1\n\t"
8554 "mv $dst, $src1\n\t"
8555 "bind\t#@minI_rReg"
8556 %}
8557
8558 ins_encode %{
8559 Label Lsrc1, Ldone;
8560 __ ble(as_Register($src1$$reg), as_Register($src2$$reg), Lsrc1);
8561 __ mv(as_Register($dst$$reg), as_Register($src2$$reg));
8562 __ j(Ldone);
8563 __ bind(Lsrc1);
8564 __ mv(as_Register($dst$$reg), as_Register($src1$$reg));
8565 __ bind(Ldone);
8566 %}
8567
8568 ins_pipe(ialu_reg_reg);
8569 %}
8570
8571 instruct maxI_rReg(iRegINoSp dst, iRegI src1, iRegI src2)
8572 %{
8573 match(Set dst (MaxI src1 src2));
8574
8575 effect(DEF dst, USE src1, USE src2);
8576
8577 ins_cost(BRANCH_COST + ALU_COST * 2);
8578 format %{
8579 "bge $src1, $src2, Lsrc1\t#@maxI_rReg\n\t"
8580 "mv $dst, $src2\n\t"
8581 "j Ldone\n\t"
8582 "bind Lsrc1\n\t"
8583 "mv $dst, $src1\n\t"
8584 "bind\t#@maxI_rReg"
8585 %}
8586
8587 ins_encode %{
8588 Label Lsrc1, Ldone;
8589 __ bge(as_Register($src1$$reg), as_Register($src2$$reg), Lsrc1);
8590 __ mv(as_Register($dst$$reg), as_Register($src2$$reg));
8591 __ j(Ldone);
8592 __ bind(Lsrc1);
8593 __ mv(as_Register($dst$$reg), as_Register($src1$$reg));
8594 __ bind(Ldone);
8595
8596 %}
8597
8598 ins_pipe(ialu_reg_reg);
8599 %}
8600
8601 // ============================================================================
8602 // Branch Instructions
8603 // Direct Branch.
8604 instruct branch(label lbl)
8605 %{
8606 match(Goto);
8607
8608 effect(USE lbl);
8609
8610 ins_cost(BRANCH_COST);
8611 format %{ "j $lbl\t#@branch" %}
8612
8613 ins_encode(riscv_enc_j(lbl));
8614
8615 ins_pipe(pipe_branch);
8616 %}
8617
8618 // ============================================================================
8619 // Compare and Branch Instructions
8620
8621 // Patterns for short (< 12KiB) variants
8622
8623 // Compare flags and branch near instructions.
8624 instruct cmpFlag_branch(cmpOpEqNe cmp, rFlagsReg cr, label lbl) %{
8625 match(If cmp cr);
8626 effect(USE lbl);
8627
8628 ins_cost(BRANCH_COST);
8629 format %{ "b$cmp $cr, zr, $lbl\t#@cmpFlag_branch" %}
8630
8631 ins_encode %{
8632 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($cr$$reg), *($lbl$$label));
8633 %}
8634 ins_pipe(pipe_cmpz_branch);
8635 ins_short_branch(1);
8636 %}
8637
8638 // Compare signed int and branch near instructions
8639 instruct cmpI_branch(cmpOp cmp, iRegI op1, iRegI op2, label lbl)
8640 %{
8641 // Same match rule as `far_cmpI_branch'.
8642 match(If cmp (CmpI op1 op2));
8643
8644 effect(USE lbl);
8645
8646 ins_cost(BRANCH_COST);
8647
8648 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpI_branch" %}
8649
8650 ins_encode %{
8651 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label));
8652 %}
8653
8654 ins_pipe(pipe_cmp_branch);
8655 ins_short_branch(1);
8656 %}
8657
8658 instruct cmpI_loop(cmpOp cmp, iRegI op1, iRegI op2, label lbl)
8659 %{
8660 // Same match rule as `far_cmpI_loop'.
8661 match(CountedLoopEnd cmp (CmpI op1 op2));
8662
8663 effect(USE lbl);
8664
8665 ins_cost(BRANCH_COST);
8666
8667 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpI_loop" %}
8668
8669 ins_encode %{
8670 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label));
8671 %}
8672
8673 ins_pipe(pipe_cmp_branch);
8674 ins_short_branch(1);
8675 %}
8676
8677 // Compare unsigned int and branch near instructions
8678 instruct cmpU_branch(cmpOpU cmp, iRegI op1, iRegI op2, label lbl)
8679 %{
8680 // Same match rule as `far_cmpU_branch'.
8681 match(If cmp (CmpU op1 op2));
8682
8683 effect(USE lbl);
8684
8685 ins_cost(BRANCH_COST);
8686
8687 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpU_branch" %}
8688
8689 ins_encode %{
8690 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
8691 as_Register($op2$$reg), *($lbl$$label));
8692 %}
8693
8694 ins_pipe(pipe_cmp_branch);
8695 ins_short_branch(1);
8696 %}
8697
8698 instruct cmpU_loop(cmpOpU cmp, iRegI op1, iRegI op2, label lbl)
8699 %{
8700 // Same match rule as `far_cmpU_loop'.
8701 match(CountedLoopEnd cmp (CmpU op1 op2));
8702
8703 effect(USE lbl);
8704
8705 ins_cost(BRANCH_COST);
8706
8707 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpU_loop" %}
8708
8709 ins_encode %{
8710 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
8711 as_Register($op2$$reg), *($lbl$$label));
8712 %}
8713
8714 ins_pipe(pipe_cmp_branch);
8715 ins_short_branch(1);
8716 %}
8717
8718 // Compare signed long and branch near instructions
8719 instruct cmpL_branch(cmpOp cmp, iRegL op1, iRegL op2, label lbl)
8720 %{
8721 // Same match rule as `far_cmpL_branch'.
8722 match(If cmp (CmpL op1 op2));
8723
8724 effect(USE lbl);
8725
8726 ins_cost(BRANCH_COST);
8727
8728 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpL_branch" %}
8729
8730 ins_encode %{
8731 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label));
8732 %}
8733
8734 ins_pipe(pipe_cmp_branch);
8735 ins_short_branch(1);
8736 %}
8737
8738 instruct cmpL_loop(cmpOp cmp, iRegL op1, iRegL op2, label lbl)
8739 %{
8740 // Same match rule as `far_cmpL_loop'.
8741 match(CountedLoopEnd cmp (CmpL op1 op2));
8742
8743 effect(USE lbl);
8744
8745 ins_cost(BRANCH_COST);
8746
8747 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpL_loop" %}
8748
8749 ins_encode %{
8750 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label));
8751 %}
8752
8753 ins_pipe(pipe_cmp_branch);
8754 ins_short_branch(1);
8755 %}
8756
8757 // Compare unsigned long and branch near instructions
8758 instruct cmpUL_branch(cmpOpU cmp, iRegL op1, iRegL op2, label lbl)
8759 %{
8760 // Same match rule as `far_cmpUL_branch'.
8761 match(If cmp (CmpUL op1 op2));
8762
8763 effect(USE lbl);
8764
8765 ins_cost(BRANCH_COST);
8766 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpUL_branch" %}
8767
8768 ins_encode %{
8769 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
8770 as_Register($op2$$reg), *($lbl$$label));
8771 %}
8772
8773 ins_pipe(pipe_cmp_branch);
8774 ins_short_branch(1);
8775 %}
8776
8777 instruct cmpUL_loop(cmpOpU cmp, iRegL op1, iRegL op2, label lbl)
8778 %{
8779 // Same match rule as `far_cmpUL_loop'.
8780 match(CountedLoopEnd cmp (CmpUL op1 op2));
8781
8782 effect(USE lbl);
8783
8784 ins_cost(BRANCH_COST);
8785 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpUL_loop" %}
8786
8787 ins_encode %{
8788 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
8789 as_Register($op2$$reg), *($lbl$$label));
8790 %}
8791
8792 ins_pipe(pipe_cmp_branch);
8793 ins_short_branch(1);
8794 %}
8795
8796 // Compare pointer and branch near instructions
8797 instruct cmpP_branch(cmpOpU cmp, iRegP op1, iRegP op2, label lbl)
8798 %{
8799 // Same match rule as `far_cmpP_branch'.
8800 match(If cmp (CmpP op1 op2));
8801
8802 effect(USE lbl);
8803
8804 ins_cost(BRANCH_COST);
8805
8806 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpP_branch" %}
8807
8808 ins_encode %{
8809 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
8810 as_Register($op2$$reg), *($lbl$$label));
8811 %}
8812
8813 ins_pipe(pipe_cmp_branch);
8814 ins_short_branch(1);
8815 %}
8816
8817 instruct cmpP_loop(cmpOpU cmp, iRegP op1, iRegP op2, label lbl)
8818 %{
8819 // Same match rule as `far_cmpP_loop'.
8820 match(CountedLoopEnd cmp (CmpP op1 op2));
8821
8822 effect(USE lbl);
8823
8824 ins_cost(BRANCH_COST);
8825
8826 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpP_loop" %}
8827
8828 ins_encode %{
8829 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
8830 as_Register($op2$$reg), *($lbl$$label));
8831 %}
8832
8833 ins_pipe(pipe_cmp_branch);
8834 ins_short_branch(1);
8835 %}
8836
8837 // Compare narrow pointer and branch near instructions
8838 instruct cmpN_branch(cmpOpU cmp, iRegN op1, iRegN op2, label lbl)
8839 %{
8840 // Same match rule as `far_cmpN_branch'.
8841 match(If cmp (CmpN op1 op2));
8842
8843 effect(USE lbl);
8844
8845 ins_cost(BRANCH_COST);
8846
8847 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpN_branch" %}
8848
8849 ins_encode %{
8850 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
8851 as_Register($op2$$reg), *($lbl$$label));
8852 %}
8853
8854 ins_pipe(pipe_cmp_branch);
8855 ins_short_branch(1);
8856 %}
8857
8858 instruct cmpN_loop(cmpOpU cmp, iRegN op1, iRegN op2, label lbl)
8859 %{
8860 // Same match rule as `far_cmpN_loop'.
8861 match(CountedLoopEnd cmp (CmpN op1 op2));
8862
8863 effect(USE lbl);
8864
8865 ins_cost(BRANCH_COST);
8866
8867 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpN_loop" %}
8868
8869 ins_encode %{
8870 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
8871 as_Register($op2$$reg), *($lbl$$label));
8872 %}
8873
8874 ins_pipe(pipe_cmp_branch);
8875 ins_short_branch(1);
8876 %}
8877
8878 // Compare float and branch near instructions
8879 instruct cmpF_branch(cmpOp cmp, fRegF op1, fRegF op2, label lbl)
8880 %{
8881 // Same match rule as `far_cmpF_branch'.
8882 match(If cmp (CmpF op1 op2));
8883
8884 effect(USE lbl);
8885
8886 ins_cost(XFER_COST + BRANCH_COST);
8887 format %{ "float_b$cmp $op1, $op2, $lbl \t#@cmpF_branch"%}
8888
8889 ins_encode %{
8890 __ float_cmp_branch($cmp$$cmpcode, as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg), *($lbl$$label));
8891 %}
8892
8893 ins_pipe(pipe_class_compare);
8894 ins_short_branch(1);
8895 %}
8896
8897 instruct cmpF_loop(cmpOp cmp, fRegF op1, fRegF op2, label lbl)
8898 %{
8899 // Same match rule as `far_cmpF_loop'.
8900 match(CountedLoopEnd cmp (CmpF op1 op2));
8901 effect(USE lbl);
8902
8903 ins_cost(XFER_COST + BRANCH_COST);
8904 format %{ "float_b$cmp $op1, $op2, $lbl\t#@cmpF_loop"%}
8905
8906 ins_encode %{
8907 __ float_cmp_branch($cmp$$cmpcode, as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg), *($lbl$$label));
8908 %}
8909
8910 ins_pipe(pipe_class_compare);
8911 ins_short_branch(1);
8912 %}
8913
8914 // Compare double and branch near instructions
8915 instruct cmpD_branch(cmpOp cmp, fRegD op1, fRegD op2, label lbl)
8916 %{
8917 // Same match rule as `far_cmpD_branch'.
8918 match(If cmp (CmpD op1 op2));
8919 effect(USE lbl);
8920
8921 ins_cost(XFER_COST + BRANCH_COST);
8922 format %{ "double_b$cmp $op1, $op2, $lbl\t#@cmpD_branch"%}
8923
8924 ins_encode %{
8925 __ float_cmp_branch($cmp$$cmpcode | C2_MacroAssembler::double_branch_mask, as_FloatRegister($op1$$reg),
8926 as_FloatRegister($op2$$reg), *($lbl$$label));
8927 %}
8928
8929 ins_pipe(pipe_class_compare);
8930 ins_short_branch(1);
8931 %}
8932
8933 instruct cmpD_loop(cmpOp cmp, fRegD op1, fRegD op2, label lbl)
8934 %{
8935 // Same match rule as `far_cmpD_loop'.
8936 match(CountedLoopEnd cmp (CmpD op1 op2));
8937 effect(USE lbl);
8938
8939 ins_cost(XFER_COST + BRANCH_COST);
8940 format %{ "double_b$cmp $op1, $op2, $lbl\t#@cmpD_loop"%}
8941
8942 ins_encode %{
8943 __ float_cmp_branch($cmp$$cmpcode | C2_MacroAssembler::double_branch_mask, as_FloatRegister($op1$$reg),
8944 as_FloatRegister($op2$$reg), *($lbl$$label));
8945 %}
8946
8947 ins_pipe(pipe_class_compare);
8948 ins_short_branch(1);
8949 %}
8950
8951 // Compare signed int with zero and branch near instructions
8952 instruct cmpI_reg_imm0_branch(cmpOp cmp, iRegI op1, immI0 zero, label lbl)
8953 %{
8954 // Same match rule as `far_cmpI_reg_imm0_branch'.
8955 match(If cmp (CmpI op1 zero));
8956
8957 effect(USE op1, USE lbl);
8958
8959 ins_cost(BRANCH_COST);
8960 format %{ "b$cmp $op1, zr, $lbl\t#@cmpI_reg_imm0_branch" %}
8961
8962 ins_encode %{
8963 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label));
8964 %}
8965
8966 ins_pipe(pipe_cmpz_branch);
8967 ins_short_branch(1);
8968 %}
8969
8970 instruct cmpI_reg_imm0_loop(cmpOp cmp, iRegI op1, immI0 zero, label lbl)
8971 %{
8972 // Same match rule as `far_cmpI_reg_imm0_loop'.
8973 match(CountedLoopEnd cmp (CmpI op1 zero));
8974
8975 effect(USE op1, USE lbl);
8976
8977 ins_cost(BRANCH_COST);
8978
8979 format %{ "b$cmp $op1, zr, $lbl\t#@cmpI_reg_imm0_loop" %}
8980
8981 ins_encode %{
8982 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label));
8983 %}
8984
8985 ins_pipe(pipe_cmpz_branch);
8986 ins_short_branch(1);
8987 %}
8988
8989 // Compare unsigned int with zero and branch near instructions
8990 instruct cmpUEqNeLeGt_reg_imm0_branch(cmpOpUEqNeLeGt cmp, iRegI op1, immI0 zero, label lbl)
8991 %{
8992 // Same match rule as `far_cmpUEqNeLeGt_reg_imm0_branch'.
8993 match(If cmp (CmpU op1 zero));
8994
8995 effect(USE op1, USE lbl);
8996
8997 ins_cost(BRANCH_COST);
8998
8999 format %{ "b$cmp $op1, zr, $lbl\t#@cmpUEqNeLeGt_reg_imm0_branch" %}
9000
9001 ins_encode %{
9002 __ enc_cmpUEqNeLeGt_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
9003 %}
9004
9005 ins_pipe(pipe_cmpz_branch);
9006 ins_short_branch(1);
9007 %}
9008
9009 instruct cmpUEqNeLeGt_reg_imm0_loop(cmpOpUEqNeLeGt cmp, iRegI op1, immI0 zero, label lbl)
9010 %{
9011 // Same match rule as `far_cmpUEqNeLeGt_reg_imm0_loop'.
9012 match(CountedLoopEnd cmp (CmpU op1 zero));
9013
9014 effect(USE op1, USE lbl);
9015
9016 ins_cost(BRANCH_COST);
9017
9018 format %{ "b$cmp $op1, zr, $lbl\t#@cmpUEqNeLeGt_reg_imm0_loop" %}
9019
9020
9021 ins_encode %{
9022 __ enc_cmpUEqNeLeGt_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
9023 %}
9024
9025 ins_pipe(pipe_cmpz_branch);
9026 ins_short_branch(1);
9027 %}
9028
9029 // Compare signed long with zero and branch near instructions
9030 instruct cmpL_reg_imm0_branch(cmpOp cmp, iRegL op1, immL0 zero, label lbl)
9031 %{
9032 // Same match rule as `far_cmpL_reg_imm0_branch'.
9033 match(If cmp (CmpL op1 zero));
9034
9035 effect(USE op1, USE lbl);
9036
9037 ins_cost(BRANCH_COST);
9038
9039 format %{ "b$cmp $op1, zr, $lbl\t#@cmpL_reg_imm0_branch" %}
9040
9041 ins_encode %{
9042 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label));
9043 %}
9044
9045 ins_pipe(pipe_cmpz_branch);
9046 ins_short_branch(1);
9047 %}
9048
9049 instruct cmpL_reg_imm0_loop(cmpOp cmp, iRegL op1, immL0 zero, label lbl)
9050 %{
9051 // Same match rule as `far_cmpL_reg_imm0_loop'.
9052 match(CountedLoopEnd cmp (CmpL op1 zero));
9053
9054 effect(USE op1, USE lbl);
9055
9056 ins_cost(BRANCH_COST);
9057
9058 format %{ "b$cmp $op1, zr, $lbl\t#@cmpL_reg_imm0_loop" %}
9059
9060 ins_encode %{
9061 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label));
9062 %}
9063
9064 ins_pipe(pipe_cmpz_branch);
9065 ins_short_branch(1);
9066 %}
9067
9068 // Compare unsigned long with zero and branch near instructions
9069 instruct cmpULEqNeLeGt_reg_imm0_branch(cmpOpUEqNeLeGt cmp, iRegL op1, immL0 zero, label lbl)
9070 %{
9071 // Same match rule as `far_cmpULEqNeLeGt_reg_imm0_branch'.
9072 match(If cmp (CmpUL op1 zero));
9073
9074 effect(USE op1, USE lbl);
9075
9076 ins_cost(BRANCH_COST);
9077
9078 format %{ "b$cmp $op1, zr, $lbl\t#@cmpULEqNeLeGt_reg_imm0_branch" %}
9079
9080 ins_encode %{
9081 __ enc_cmpUEqNeLeGt_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
9082 %}
9083
9084 ins_pipe(pipe_cmpz_branch);
9085 ins_short_branch(1);
9086 %}
9087
9088 instruct cmpULEqNeLeGt_reg_imm0_loop(cmpOpUEqNeLeGt cmp, iRegL op1, immL0 zero, label lbl)
9089 %{
9090 // Same match rule as `far_cmpULEqNeLeGt_reg_imm0_loop'.
9091 match(CountedLoopEnd cmp (CmpUL op1 zero));
9092
9093 effect(USE op1, USE lbl);
9094
9095 ins_cost(BRANCH_COST);
9096
9097 format %{ "b$cmp $op1, zr, $lbl\t#@cmpULEqNeLeGt_reg_imm0_loop" %}
9098
9099 ins_encode %{
9100 __ enc_cmpUEqNeLeGt_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
9101 %}
9102
9103 ins_pipe(pipe_cmpz_branch);
9104 ins_short_branch(1);
9105 %}
9106
9107 // Compare pointer with zero and branch near instructions
9108 instruct cmpP_imm0_branch(cmpOpEqNe cmp, iRegP op1, immP0 zero, label lbl) %{
9109 // Same match rule as `far_cmpP_reg_imm0_branch'.
9110 match(If cmp (CmpP op1 zero));
9111 effect(USE lbl);
9112
9113 ins_cost(BRANCH_COST);
9114 format %{ "b$cmp $op1, zr, $lbl\t#@cmpP_imm0_branch" %}
9115
9116 ins_encode %{
9117 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
9118 %}
9119
9120 ins_pipe(pipe_cmpz_branch);
9121 ins_short_branch(1);
9122 %}
9123
9124 instruct cmpP_imm0_loop(cmpOpEqNe cmp, iRegP op1, immP0 zero, label lbl) %{
9125 // Same match rule as `far_cmpP_reg_imm0_loop'.
9126 match(CountedLoopEnd cmp (CmpP op1 zero));
9127 effect(USE lbl);
9128
9129 ins_cost(BRANCH_COST);
9130 format %{ "b$cmp $op1, zr, $lbl\t#@cmpP_imm0_loop" %}
9131
9132 ins_encode %{
9133 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
9134 %}
9135
9136 ins_pipe(pipe_cmpz_branch);
9137 ins_short_branch(1);
9138 %}
9139
9140 // Compare narrow pointer with zero and branch near instructions
9141 instruct cmpN_imm0_branch(cmpOpEqNe cmp, iRegN op1, immN0 zero, label lbl) %{
9142 // Same match rule as `far_cmpN_reg_imm0_branch'.
9143 match(If cmp (CmpN op1 zero));
9144 effect(USE lbl);
9145
9146 ins_cost(BRANCH_COST);
9147
9148 format %{ "b$cmp $op1, zr, $lbl\t#@cmpN_imm0_branch" %}
9149
9150 ins_encode %{
9151 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
9152 %}
9153
9154 ins_pipe(pipe_cmpz_branch);
9155 ins_short_branch(1);
9156 %}
9157
9158 instruct cmpN_imm0_loop(cmpOpEqNe cmp, iRegN op1, immN0 zero, label lbl) %{
9159 // Same match rule as `far_cmpN_reg_imm0_loop'.
9160 match(CountedLoopEnd cmp (CmpN op1 zero));
9161 effect(USE lbl);
9162
9163 ins_cost(BRANCH_COST);
9164
9165 format %{ "b$cmp $op1, zr, $lbl\t#@cmpN_imm0_loop" %}
9166
9167 ins_encode %{
9168 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
9169 %}
9170
9171 ins_pipe(pipe_cmpz_branch);
9172 ins_short_branch(1);
9173 %}
9174
9175 // Compare narrow pointer with pointer zero and branch near instructions
9176 instruct cmpP_narrowOop_imm0_branch(cmpOpEqNe cmp, iRegN op1, immP0 zero, label lbl) %{
9177 // Same match rule as `far_cmpP_narrowOop_imm0_branch'.
9178 match(If cmp (CmpP (DecodeN op1) zero));
9179 effect(USE lbl);
9180
9181 ins_cost(BRANCH_COST);
9182 format %{ "b$cmp $op1, zr, $lbl\t#@cmpP_narrowOop_imm0_branch" %}
9183
9184 ins_encode %{
9185 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
9186 %}
9187
9188 ins_pipe(pipe_cmpz_branch);
9189 ins_short_branch(1);
9190 %}
9191
9192 instruct cmpP_narrowOop_imm0_loop(cmpOpEqNe cmp, iRegN op1, immP0 zero, label lbl) %{
9193 // Same match rule as `far_cmpP_narrowOop_imm0_loop'.
9194 match(CountedLoopEnd cmp (CmpP (DecodeN op1) zero));
9195 effect(USE lbl);
9196
9197 ins_cost(BRANCH_COST);
9198 format %{ "b$cmp $op1, zr, $lbl\t#@cmpP_narrowOop_imm0_loop" %}
9199
9200 ins_encode %{
9201 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
9202 %}
9203
9204 ins_pipe(pipe_cmpz_branch);
9205 ins_short_branch(1);
9206 %}
9207
9208 // Patterns for far (20KiB) variants
9209
9210 instruct far_cmpFlag_branch(cmpOp cmp, rFlagsReg cr, label lbl) %{
9211 match(If cmp cr);
9212 effect(USE lbl);
9213
9214 ins_cost(BRANCH_COST);
9215 format %{ "far_b$cmp $cr, zr, $lbl\t#@far_cmpFlag_branch"%}
9216
9217 ins_encode %{
9218 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($cr$$reg), *($lbl$$label), /* is_far */ true);
9219 %}
9220
9221 ins_pipe(pipe_cmpz_branch);
9222 %}
9223
9224 // Compare signed int and branch far instructions
9225 instruct far_cmpI_branch(cmpOp cmp, iRegI op1, iRegI op2, label lbl) %{
9226 match(If cmp (CmpI op1 op2));
9227 effect(USE lbl);
9228
9229 ins_cost(BRANCH_COST * 2);
9230
9231 // the format instruction [far_b$cmp] here is be used as two insructions
9232 // in macroassembler: b$not_cmp(op1, op2, done), j($lbl), bind(done)
9233 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpI_branch" %}
9234
9235 ins_encode %{
9236 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9237 %}
9238
9239 ins_pipe(pipe_cmp_branch);
9240 %}
9241
9242 instruct far_cmpI_loop(cmpOp cmp, iRegI op1, iRegI op2, label lbl) %{
9243 match(CountedLoopEnd cmp (CmpI op1 op2));
9244 effect(USE lbl);
9245
9246 ins_cost(BRANCH_COST * 2);
9247 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpI_loop" %}
9248
9249 ins_encode %{
9250 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9251 %}
9252
9253 ins_pipe(pipe_cmp_branch);
9254 %}
9255
9256 instruct far_cmpU_branch(cmpOpU cmp, iRegI op1, iRegI op2, label lbl) %{
9257 match(If cmp (CmpU op1 op2));
9258 effect(USE lbl);
9259
9260 ins_cost(BRANCH_COST * 2);
9261 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpU_branch" %}
9262
9263 ins_encode %{
9264 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9265 as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9266 %}
9267
9268 ins_pipe(pipe_cmp_branch);
9269 %}
9270
9271 instruct far_cmpU_loop(cmpOpU cmp, iRegI op1, iRegI op2, label lbl) %{
9272 match(CountedLoopEnd cmp (CmpU op1 op2));
9273 effect(USE lbl);
9274
9275 ins_cost(BRANCH_COST * 2);
9276 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpU_loop" %}
9277
9278 ins_encode %{
9279 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9280 as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9281 %}
9282
9283 ins_pipe(pipe_cmp_branch);
9284 %}
9285
9286 instruct far_cmpL_branch(cmpOp cmp, iRegL op1, iRegL op2, label lbl) %{
9287 match(If cmp (CmpL op1 op2));
9288 effect(USE lbl);
9289
9290 ins_cost(BRANCH_COST * 2);
9291 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpL_branch" %}
9292
9293 ins_encode %{
9294 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9295 %}
9296
9297 ins_pipe(pipe_cmp_branch);
9298 %}
9299
9300 instruct far_cmpLloop(cmpOp cmp, iRegL op1, iRegL op2, label lbl) %{
9301 match(CountedLoopEnd cmp (CmpL op1 op2));
9302 effect(USE lbl);
9303
9304 ins_cost(BRANCH_COST * 2);
9305 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpL_loop" %}
9306
9307 ins_encode %{
9308 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9309 %}
9310
9311 ins_pipe(pipe_cmp_branch);
9312 %}
9313
9314 instruct far_cmpUL_branch(cmpOpU cmp, iRegL op1, iRegL op2, label lbl) %{
9315 match(If cmp (CmpUL op1 op2));
9316 effect(USE lbl);
9317
9318 ins_cost(BRANCH_COST * 2);
9319 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpUL_branch" %}
9320
9321 ins_encode %{
9322 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9323 as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9324 %}
9325
9326 ins_pipe(pipe_cmp_branch);
9327 %}
9328
9329 instruct far_cmpUL_loop(cmpOpU cmp, iRegL op1, iRegL op2, label lbl) %{
9330 match(CountedLoopEnd cmp (CmpUL op1 op2));
9331 effect(USE lbl);
9332
9333 ins_cost(BRANCH_COST * 2);
9334 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpUL_loop" %}
9335
9336 ins_encode %{
9337 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9338 as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9339 %}
9340
9341 ins_pipe(pipe_cmp_branch);
9342 %}
9343
9344 instruct far_cmpP_branch(cmpOpU cmp, iRegP op1, iRegP op2, label lbl)
9345 %{
9346 match(If cmp (CmpP op1 op2));
9347
9348 effect(USE lbl);
9349
9350 ins_cost(BRANCH_COST * 2);
9351
9352 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpP_branch" %}
9353
9354 ins_encode %{
9355 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9356 as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9357 %}
9358
9359 ins_pipe(pipe_cmp_branch);
9360 %}
9361
9362 instruct far_cmpP_loop(cmpOpU cmp, iRegP op1, iRegP op2, label lbl)
9363 %{
9364 match(CountedLoopEnd cmp (CmpP op1 op2));
9365
9366 effect(USE lbl);
9367
9368 ins_cost(BRANCH_COST * 2);
9369
9370 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpP_loop" %}
9371
9372 ins_encode %{
9373 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9374 as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9375 %}
9376
9377 ins_pipe(pipe_cmp_branch);
9378 %}
9379
9380 instruct far_cmpN_branch(cmpOpU cmp, iRegN op1, iRegN op2, label lbl)
9381 %{
9382 match(If cmp (CmpN op1 op2));
9383
9384 effect(USE lbl);
9385
9386 ins_cost(BRANCH_COST * 2);
9387
9388 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpN_branch" %}
9389
9390 ins_encode %{
9391 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9392 as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9393 %}
9394
9395 ins_pipe(pipe_cmp_branch);
9396 %}
9397
9398 instruct far_cmpN_loop(cmpOpU cmp, iRegN op1, iRegN op2, label lbl)
9399 %{
9400 match(CountedLoopEnd cmp (CmpN op1 op2));
9401
9402 effect(USE lbl);
9403
9404 ins_cost(BRANCH_COST * 2);
9405
9406 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpN_loop" %}
9407
9408 ins_encode %{
9409 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9410 as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9411 %}
9412
9413 ins_pipe(pipe_cmp_branch);
9414 %}
9415
9416 // Float compare and branch instructions
9417 instruct far_cmpF_branch(cmpOp cmp, fRegF op1, fRegF op2, label lbl)
9418 %{
9419 match(If cmp (CmpF op1 op2));
9420
9421 effect(USE lbl);
9422
9423 ins_cost(XFER_COST + BRANCH_COST * 2);
9424 format %{ "far_float_b$cmp $op1, $op2, $lbl\t#@far_cmpF_branch"%}
9425
9426 ins_encode %{
9427 __ float_cmp_branch($cmp$$cmpcode, as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg),
9428 *($lbl$$label), /* is_far */ true);
9429 %}
9430
9431 ins_pipe(pipe_class_compare);
9432 %}
9433
9434 instruct far_cmpF_loop(cmpOp cmp, fRegF op1, fRegF op2, label lbl)
9435 %{
9436 match(CountedLoopEnd cmp (CmpF op1 op2));
9437 effect(USE lbl);
9438
9439 ins_cost(XFER_COST + BRANCH_COST * 2);
9440 format %{ "far_float_b$cmp $op1, $op2, $lbl\t#@far_cmpF_loop"%}
9441
9442 ins_encode %{
9443 __ float_cmp_branch($cmp$$cmpcode, as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg),
9444 *($lbl$$label), /* is_far */ true);
9445 %}
9446
9447 ins_pipe(pipe_class_compare);
9448 %}
9449
9450 // Double compare and branch instructions
9451 instruct far_cmpD_branch(cmpOp cmp, fRegD op1, fRegD op2, label lbl)
9452 %{
9453 match(If cmp (CmpD op1 op2));
9454 effect(USE lbl);
9455
9456 ins_cost(XFER_COST + BRANCH_COST * 2);
9457 format %{ "far_double_b$cmp $op1, $op2, $lbl\t#@far_cmpD_branch"%}
9458
9459 ins_encode %{
9460 __ float_cmp_branch($cmp$$cmpcode | C2_MacroAssembler::double_branch_mask, as_FloatRegister($op1$$reg),
9461 as_FloatRegister($op2$$reg), *($lbl$$label), /* is_far */ true);
9462 %}
9463
9464 ins_pipe(pipe_class_compare);
9465 %}
9466
9467 instruct far_cmpD_loop(cmpOp cmp, fRegD op1, fRegD op2, label lbl)
9468 %{
9469 match(CountedLoopEnd cmp (CmpD op1 op2));
9470 effect(USE lbl);
9471
9472 ins_cost(XFER_COST + BRANCH_COST * 2);
9473 format %{ "far_double_b$cmp $op1, $op2, $lbl\t#@far_cmpD_loop"%}
9474
9475 ins_encode %{
9476 __ float_cmp_branch($cmp$$cmpcode | C2_MacroAssembler::double_branch_mask, as_FloatRegister($op1$$reg),
9477 as_FloatRegister($op2$$reg), *($lbl$$label), /* is_far */ true);
9478 %}
9479
9480 ins_pipe(pipe_class_compare);
9481 %}
9482
9483 instruct far_cmpI_reg_imm0_branch(cmpOp cmp, iRegI op1, immI0 zero, label lbl)
9484 %{
9485 match(If cmp (CmpI op1 zero));
9486
9487 effect(USE op1, USE lbl);
9488
9489 ins_cost(BRANCH_COST * 2);
9490
9491 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpI_reg_imm0_branch" %}
9492
9493 ins_encode %{
9494 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label), /* is_far */ true);
9495 %}
9496
9497 ins_pipe(pipe_cmpz_branch);
9498 %}
9499
9500 instruct far_cmpI_reg_imm0_loop(cmpOp cmp, iRegI op1, immI0 zero, label lbl)
9501 %{
9502 match(CountedLoopEnd cmp (CmpI op1 zero));
9503
9504 effect(USE op1, USE lbl);
9505
9506 ins_cost(BRANCH_COST * 2);
9507
9508 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpI_reg_imm0_loop" %}
9509
9510 ins_encode %{
9511 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label), /* is_far */ true);
9512 %}
9513
9514 ins_pipe(pipe_cmpz_branch);
9515 %}
9516
9517 instruct far_cmpUEqNeLeGt_imm0_branch(cmpOpUEqNeLeGt cmp, iRegI op1, immI0 zero, label lbl)
9518 %{
9519 match(If cmp (CmpU op1 zero));
9520
9521 effect(USE op1, USE lbl);
9522
9523 ins_cost(BRANCH_COST * 2);
9524
9525 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpUEqNeLeGt_imm0_branch" %}
9526
9527 ins_encode %{
9528 __ enc_cmpUEqNeLeGt_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
9529 %}
9530
9531 ins_pipe(pipe_cmpz_branch);
9532 %}
9533
9534 instruct far_cmpUEqNeLeGt_reg_imm0_loop(cmpOpUEqNeLeGt cmp, iRegI op1, immI0 zero, label lbl)
9535 %{
9536 match(CountedLoopEnd cmp (CmpU op1 zero));
9537
9538 effect(USE op1, USE lbl);
9539
9540 ins_cost(BRANCH_COST * 2);
9541
9542 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpUEqNeLeGt_reg_imm0_loop" %}
9543
9544
9545 ins_encode %{
9546 __ enc_cmpUEqNeLeGt_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
9547 %}
9548
9549 ins_pipe(pipe_cmpz_branch);
9550 %}
9551
9552 // compare lt/ge unsigned instructs has no short instruct with same match
9553 instruct far_cmpULtGe_reg_imm0_branch(cmpOpULtGe cmp, iRegI op1, immI0 zero, label lbl)
9554 %{
9555 match(If cmp (CmpU op1 zero));
9556
9557 effect(USE op1, USE lbl);
9558
9559 ins_cost(BRANCH_COST);
9560
9561 format %{ "j $lbl if $cmp == ge\t#@far_cmpULtGe_reg_imm0_branch" %}
9562
9563 ins_encode(riscv_enc_far_cmpULtGe_imm0_branch(cmp, op1, lbl));
9564
9565 ins_pipe(pipe_cmpz_branch);
9566 %}
9567
9568 instruct far_cmpULtGe_reg_imm0_loop(cmpOpULtGe cmp, iRegI op1, immI0 zero, label lbl)
9569 %{
9570 match(CountedLoopEnd cmp (CmpU op1 zero));
9571
9572 effect(USE op1, USE lbl);
9573
9574 ins_cost(BRANCH_COST);
9575
9576 format %{ "j $lbl if $cmp == ge\t#@far_cmpULtGe_reg_imm0_loop" %}
9577
9578 ins_encode(riscv_enc_far_cmpULtGe_imm0_branch(cmp, op1, lbl));
9579
9580 ins_pipe(pipe_cmpz_branch);
9581 %}
9582
9583 instruct far_cmpL_reg_imm0_branch(cmpOp cmp, iRegL op1, immL0 zero, label lbl)
9584 %{
9585 match(If cmp (CmpL op1 zero));
9586
9587 effect(USE op1, USE lbl);
9588
9589 ins_cost(BRANCH_COST * 2);
9590
9591 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpL_reg_imm0_branch" %}
9592
9593 ins_encode %{
9594 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label), /* is_far */ true);
9595 %}
9596
9597 ins_pipe(pipe_cmpz_branch);
9598 %}
9599
9600 instruct far_cmpL_reg_imm0_loop(cmpOp cmp, iRegL op1, immL0 zero, label lbl)
9601 %{
9602 match(CountedLoopEnd cmp (CmpL op1 zero));
9603
9604 effect(USE op1, USE lbl);
9605
9606 ins_cost(BRANCH_COST * 2);
9607
9608 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpL_reg_imm0_loop" %}
9609
9610 ins_encode %{
9611 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label), /* is_far */ true);
9612 %}
9613
9614 ins_pipe(pipe_cmpz_branch);
9615 %}
9616
9617 instruct far_cmpULEqNeLeGt_reg_imm0_branch(cmpOpUEqNeLeGt cmp, iRegL op1, immL0 zero, label lbl)
9618 %{
9619 match(If cmp (CmpUL op1 zero));
9620
9621 effect(USE op1, USE lbl);
9622
9623 ins_cost(BRANCH_COST * 2);
9624
9625 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpULEqNeLeGt_reg_imm0_branch" %}
9626
9627 ins_encode %{
9628 __ enc_cmpUEqNeLeGt_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
9629 %}
9630
9631 ins_pipe(pipe_cmpz_branch);
9632 %}
9633
9634 instruct far_cmpULEqNeLeGt_reg_imm0_loop(cmpOpUEqNeLeGt cmp, iRegL op1, immL0 zero, label lbl)
9635 %{
9636 match(CountedLoopEnd cmp (CmpUL op1 zero));
9637
9638 effect(USE op1, USE lbl);
9639
9640 ins_cost(BRANCH_COST * 2);
9641
9642 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpULEqNeLeGt_reg_imm0_loop" %}
9643
9644 ins_encode %{
9645 __ enc_cmpUEqNeLeGt_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
9646 %}
9647
9648 ins_pipe(pipe_cmpz_branch);
9649 %}
9650
9651 // compare lt/ge unsigned instructs has no short instruct with same match
9652 instruct far_cmpULLtGe_reg_imm0_branch(cmpOpULtGe cmp, iRegL op1, immL0 zero, label lbl)
9653 %{
9654 match(If cmp (CmpUL op1 zero));
9655
9656 effect(USE op1, USE lbl);
9657
9658 ins_cost(BRANCH_COST);
9659
9660 format %{ "j $lbl if $cmp == ge\t#@far_cmpULLtGe_reg_imm0_branch" %}
9661
9662 ins_encode(riscv_enc_far_cmpULtGe_imm0_branch(cmp, op1, lbl));
9663
9664 ins_pipe(pipe_cmpz_branch);
9665 %}
9666
9667 instruct far_cmpULLtGe_reg_imm0_loop(cmpOpULtGe cmp, iRegL op1, immL0 zero, label lbl)
9668 %{
9669 match(CountedLoopEnd cmp (CmpUL op1 zero));
9670
9671 effect(USE op1, USE lbl);
9672
9673 ins_cost(BRANCH_COST);
9674
9675 format %{ "j $lbl if $cmp == ge\t#@far_cmpULLtGe_reg_imm0_loop" %}
9676
9677 ins_encode(riscv_enc_far_cmpULtGe_imm0_branch(cmp, op1, lbl));
9678
9679 ins_pipe(pipe_cmpz_branch);
9680 %}
9681
9682 instruct far_cmpP_imm0_branch(cmpOpEqNe cmp, iRegP op1, immP0 zero, label lbl) %{
9683 match(If cmp (CmpP op1 zero));
9684 effect(USE lbl);
9685
9686 ins_cost(BRANCH_COST * 2);
9687 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpP_imm0_branch" %}
9688
9689 ins_encode %{
9690 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
9691 %}
9692
9693 ins_pipe(pipe_cmpz_branch);
9694 %}
9695
9696 instruct far_cmpP_imm0_loop(cmpOpEqNe cmp, iRegP op1, immP0 zero, label lbl) %{
9697 match(CountedLoopEnd cmp (CmpP op1 zero));
9698 effect(USE lbl);
9699
9700 ins_cost(BRANCH_COST * 2);
9701 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpP_imm0_loop" %}
9702
9703 ins_encode %{
9704 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
9705 %}
9706
9707 ins_pipe(pipe_cmpz_branch);
9708 %}
9709
9710 instruct far_cmpN_imm0_branch(cmpOpEqNe cmp, iRegN op1, immN0 zero, label lbl) %{
9711 match(If cmp (CmpN op1 zero));
9712 effect(USE lbl);
9713
9714 ins_cost(BRANCH_COST * 2);
9715
9716 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpN_imm0_branch" %}
9717
9718 ins_encode %{
9719 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
9720 %}
9721
9722 ins_pipe(pipe_cmpz_branch);
9723 %}
9724
9725 instruct far_cmpN_imm0_loop(cmpOpEqNe cmp, iRegN op1, immN0 zero, label lbl) %{
9726 match(CountedLoopEnd cmp (CmpN op1 zero));
9727 effect(USE lbl);
9728
9729 ins_cost(BRANCH_COST * 2);
9730
9731 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpN_imm0_loop" %}
9732
9733 ins_encode %{
9734 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
9735 %}
9736
9737 ins_pipe(pipe_cmpz_branch);
9738 %}
9739
9740 instruct far_cmpP_narrowOop_imm0_branch(cmpOpEqNe cmp, iRegN op1, immP0 zero, label lbl) %{
9741 match(If cmp (CmpP (DecodeN op1) zero));
9742 effect(USE lbl);
9743
9744 ins_cost(BRANCH_COST * 2);
9745 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpP_narrowOop_imm0_branch" %}
9746
9747 ins_encode %{
9748 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
9749 %}
9750
9751 ins_pipe(pipe_cmpz_branch);
9752 %}
9753
9754 instruct far_cmpP_narrowOop_imm0_loop(cmpOpEqNe cmp, iRegN op1, immP0 zero, label lbl) %{
9755 match(CountedLoopEnd cmp (CmpP (DecodeN op1) zero));
9756 effect(USE lbl);
9757
9758 ins_cost(BRANCH_COST * 2);
9759 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpP_narrowOop_imm0_loop" %}
9760
9761 ins_encode %{
9762 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
9763 %}
9764
9765 ins_pipe(pipe_cmpz_branch);
9766 %}
9767
9768 // ============================================================================
9769 // Conditional Move Instructions
9770 instruct cmovI_cmpI(iRegINoSp dst, iRegI src, iRegI op1, iRegI op2, cmpOp cop) %{
9771 match(Set dst (CMoveI (Binary cop (CmpI op1 op2)) (Binary dst src)));
9772 ins_cost(ALU_COST + BRANCH_COST);
9773
9774 format %{
9775 "bneg$cop $op1, $op2, skip\t#@cmovI_cmpI\n\t"
9776 "mv $dst, $src\n\t"
9777 "skip:"
9778 %}
9779
9780 ins_encode %{
9781 __ enc_cmove($cop$$cmpcode,
9782 as_Register($op1$$reg), as_Register($op2$$reg),
9783 as_Register($dst$$reg), as_Register($src$$reg));
9784 %}
9785
9786 ins_pipe(pipe_slow);
9787 %}
9788
9789 instruct cmovI_cmpU(iRegINoSp dst, iRegI src, iRegI op1, iRegI op2, cmpOpU cop) %{
9790 match(Set dst (CMoveI (Binary cop (CmpU op1 op2)) (Binary dst src)));
9791 ins_cost(ALU_COST + BRANCH_COST);
9792
9793 format %{
9794 "bneg$cop $op1, $op2, skip\t#@cmovI_cmpU\n\t"
9795 "mv $dst, $src\n\t"
9796 "skip:"
9797 %}
9798
9799 ins_encode %{
9800 __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
9801 as_Register($op1$$reg), as_Register($op2$$reg),
9802 as_Register($dst$$reg), as_Register($src$$reg));
9803 %}
9804
9805 ins_pipe(pipe_slow);
9806 %}
9807
9808 instruct cmovI_cmpL(iRegINoSp dst, iRegI src, iRegL op1, iRegL op2, cmpOp cop) %{
9809 match(Set dst (CMoveI (Binary cop (CmpL op1 op2)) (Binary dst src)));
9810 ins_cost(ALU_COST + BRANCH_COST);
9811
9812 format %{
9813 "bneg$cop $op1, $op2, skip\t#@cmovI_cmpL\n\t"
9814 "mv $dst, $src\n\t"
9815 "skip:"
9816 %}
9817
9818 ins_encode %{
9819 __ enc_cmove($cop$$cmpcode,
9820 as_Register($op1$$reg), as_Register($op2$$reg),
9821 as_Register($dst$$reg), as_Register($src$$reg));
9822 %}
9823
9824 ins_pipe(pipe_slow);
9825 %}
9826
9827 instruct cmovL_cmpL(iRegLNoSp dst, iRegL src, iRegL op1, iRegL op2, cmpOp cop) %{
9828 match(Set dst (CMoveL (Binary cop (CmpL op1 op2)) (Binary dst src)));
9829 ins_cost(ALU_COST + BRANCH_COST);
9830
9831 format %{
9832 "bneg$cop $op1, $op2, skip\t#@cmovL_cmpL\n\t"
9833 "mv $dst, $src\n\t"
9834 "skip:"
9835 %}
9836
9837 ins_encode %{
9838 __ enc_cmove($cop$$cmpcode,
9839 as_Register($op1$$reg), as_Register($op2$$reg),
9840 as_Register($dst$$reg), as_Register($src$$reg));
9841 %}
9842
9843 ins_pipe(pipe_slow);
9844 %}
9845
9846 instruct cmovL_cmpUL(iRegLNoSp dst, iRegL src, iRegL op1, iRegL op2, cmpOpU cop) %{
9847 match(Set dst (CMoveL (Binary cop (CmpUL op1 op2)) (Binary dst src)));
9848 ins_cost(ALU_COST + BRANCH_COST);
9849
9850 format %{
9851 "bneg$cop $op1, $op2, skip\t#@cmovL_cmpUL\n\t"
9852 "mv $dst, $src\n\t"
9853 "skip:"
9854 %}
9855
9856 ins_encode %{
9857 __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
9858 as_Register($op1$$reg), as_Register($op2$$reg),
9859 as_Register($dst$$reg), as_Register($src$$reg));
9860 %}
9861
9862 ins_pipe(pipe_slow);
9863 %}
9864
9865 instruct cmovI_cmpUL(iRegINoSp dst, iRegI src, iRegL op1, iRegL op2, cmpOpU cop) %{
9866 match(Set dst (CMoveI (Binary cop (CmpUL op1 op2)) (Binary dst src)));
9867 ins_cost(ALU_COST + BRANCH_COST);
9868 format %{
9869 "bneg$cop $op1, $op2\t#@cmovI_cmpUL\n\t"
9870 "mv $dst, $src\n\t"
9871 "skip:"
9872 %}
9873
9874 ins_encode %{
9875 __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
9876 as_Register($op1$$reg), as_Register($op2$$reg),
9877 as_Register($dst$$reg), as_Register($src$$reg));
9878 %}
9879
9880 ins_pipe(pipe_slow);
9881 %}
9882
9883
9884 // ============================================================================
9885 // Procedure Call/Return Instructions
9886
9887 // Call Java Static Instruction
9888 // Note: If this code changes, the corresponding ret_addr_offset() and
9889 // compute_padding() functions will have to be adjusted.
9890 instruct CallStaticJavaDirect(method meth)
9891 %{
9892 match(CallStaticJava);
9893
9894 effect(USE meth);
9895
9896 ins_cost(BRANCH_COST);
9897
9898 format %{ "CALL,static $meth\t#@CallStaticJavaDirect" %}
9899
9900 ins_encode(riscv_enc_java_static_call(meth),
9901 riscv_enc_call_epilog);
9902
9903 ins_pipe(pipe_class_call);
9904 ins_alignment(4);
9905 %}
9906
9907 // TO HERE
9908
9909 // Call Java Dynamic Instruction
9910 // Note: If this code changes, the corresponding ret_addr_offset() and
9911 // compute_padding() functions will have to be adjusted.
9912 instruct CallDynamicJavaDirect(method meth, rFlagsReg cr)
9913 %{
9914 match(CallDynamicJava);
9915
9916 effect(USE meth, KILL cr);
9917
9918 ins_cost(BRANCH_COST + ALU_COST * 6);
9919
9920 format %{ "CALL,dynamic $meth\t#@CallDynamicJavaDirect" %}
9921
9922 ins_encode(riscv_enc_java_dynamic_call(meth),
9923 riscv_enc_call_epilog);
9924
9925 ins_pipe(pipe_class_call);
9926 ins_alignment(4);
9927 %}
9928
9929 // Call Runtime Instruction
9930
9931 instruct CallRuntimeDirect(method meth, rFlagsReg cr)
9932 %{
9933 match(CallRuntime);
9934
9935 effect(USE meth, KILL cr);
9936
9937 ins_cost(BRANCH_COST);
9938
9939 format %{ "CALL, runtime $meth\t#@CallRuntimeDirect" %}
9940
9941 ins_encode(riscv_enc_java_to_runtime(meth));
9942
9943 ins_pipe(pipe_class_call);
9944 %}
9945
9946 // Call Runtime Instruction
9947
9948 instruct CallLeafDirect(method meth, rFlagsReg cr)
9949 %{
9950 match(CallLeaf);
9951
9952 effect(USE meth, KILL cr);
9953
9954 ins_cost(BRANCH_COST);
9955
9956 format %{ "CALL, runtime leaf $meth\t#@CallLeafDirect" %}
9957
9958 ins_encode(riscv_enc_java_to_runtime(meth));
9959
9960 ins_pipe(pipe_class_call);
9961 %}
9962
9963 // Call Runtime Instruction
9964
9965 instruct CallLeafNoFPDirect(method meth, rFlagsReg cr)
9966 %{
9967 match(CallLeafNoFP);
9968
9969 effect(USE meth, KILL cr);
9970
9971 ins_cost(BRANCH_COST);
9972
9973 format %{ "CALL, runtime leaf nofp $meth\t#@CallLeafNoFPDirect" %}
9974
9975 ins_encode(riscv_enc_java_to_runtime(meth));
9976
9977 ins_pipe(pipe_class_call);
9978 %}
9979
9980 // ============================================================================
9981 // Partial Subtype Check
9982 //
9983 // superklass array for an instance of the superklass. Set a hidden
9984 // internal cache on a hit (cache is checked with exposed code in
9985 // gen_subtype_check()). Return zero for a hit. The encoding
9986 // ALSO sets flags.
9987
9988 instruct partialSubtypeCheck(iRegP_R15 result, iRegP_R14 sub, iRegP_R10 super, iRegP_R12 tmp, rFlagsReg cr)
9989 %{
9990 match(Set result (PartialSubtypeCheck sub super));
9991 effect(KILL tmp, KILL cr);
9992
9993 ins_cost(2 * STORE_COST + 3 * LOAD_COST + 4 * ALU_COST + BRANCH_COST * 4);
9994 format %{ "partialSubtypeCheck $result, $sub, $super\t#@partialSubtypeCheck" %}
9995
9996 ins_encode(riscv_enc_partial_subtype_check(sub, super, tmp, result));
9997
9998 opcode(0x1); // Force zero of result reg on hit
9999
10000 ins_pipe(pipe_class_memory);
10001 %}
10002
10003 instruct partialSubtypeCheckVsZero(iRegP_R15 result, iRegP_R14 sub, iRegP_R10 super, iRegP_R12 tmp,
10004 immP0 zero, rFlagsReg cr)
10005 %{
10006 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero));
10007 effect(KILL tmp, KILL result);
10008
10009 ins_cost(2 * STORE_COST + 3 * LOAD_COST + 4 * ALU_COST + BRANCH_COST * 4);
10010 format %{ "partialSubtypeCheck $result, $sub, $super == 0\t#@partialSubtypeCheckVsZero" %}
10011
10012 ins_encode(riscv_enc_partial_subtype_check(sub, super, tmp, result));
10013
10014 opcode(0x0); // Don't zero result reg on hit
10015
10016 ins_pipe(pipe_class_memory);
10017 %}
10018
10019 instruct string_compareU(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
10020 iRegI_R10 result, iRegP_R28 tmp1, iRegL_R29 tmp2, iRegL_R30 tmp3, rFlagsReg cr)
10021 %{
10022 predicate(!UseRVV && ((StrCompNode *)n)->encoding() == StrIntrinsicNode::UU);
10023 match(Set result (StrComp(Binary str1 cnt1)(Binary str2 cnt2)));
10024 effect(KILL tmp1, KILL tmp2, KILL tmp3, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
10025
10026 format %{ "String Compare $str1, $cnt1, $str2, $cnt2 -> $result\t#@string_compareU" %}
10027 ins_encode %{
10028 // Count is in 8-bit bytes; non-Compact chars are 16 bits.
10029 __ string_compare($str1$$Register, $str2$$Register,
10030 $cnt1$$Register, $cnt2$$Register, $result$$Register,
10031 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
10032 StrIntrinsicNode::UU);
10033 %}
10034 ins_pipe(pipe_class_memory);
10035 %}
10036
10037 instruct string_compareL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
10038 iRegI_R10 result, iRegP_R28 tmp1, iRegL_R29 tmp2, iRegL_R30 tmp3, rFlagsReg cr)
10039 %{
10040 predicate(!UseRVV && ((StrCompNode *)n)->encoding() == StrIntrinsicNode::LL);
10041 match(Set result (StrComp(Binary str1 cnt1)(Binary str2 cnt2)));
10042 effect(KILL tmp1, KILL tmp2, KILL tmp3, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
10043
10044 format %{ "String Compare $str1, $cnt1, $str2, $cnt2 -> $result\t#@string_compareL" %}
10045 ins_encode %{
10046 __ string_compare($str1$$Register, $str2$$Register,
10047 $cnt1$$Register, $cnt2$$Register, $result$$Register,
10048 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
10049 StrIntrinsicNode::LL);
10050 %}
10051 ins_pipe(pipe_class_memory);
10052 %}
10053
10054 instruct string_compareUL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
10055 iRegI_R10 result, iRegP_R28 tmp1, iRegL_R29 tmp2, iRegL_R30 tmp3, rFlagsReg cr)
10056 %{
10057 predicate(!UseRVV && ((StrCompNode *)n)->encoding() == StrIntrinsicNode::UL);
10058 match(Set result (StrComp(Binary str1 cnt1)(Binary str2 cnt2)));
10059 effect(KILL tmp1, KILL tmp2, KILL tmp3, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
10060
10061 format %{"String Compare $str1, $cnt1, $str2, $cnt2 -> $result\t#@string_compareUL" %}
10062 ins_encode %{
10063 __ string_compare($str1$$Register, $str2$$Register,
10064 $cnt1$$Register, $cnt2$$Register, $result$$Register,
10065 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
10066 StrIntrinsicNode::UL);
10067 %}
10068 ins_pipe(pipe_class_memory);
10069 %}
10070
10071 instruct string_compareLU(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
10072 iRegI_R10 result, iRegP_R28 tmp1, iRegL_R29 tmp2, iRegL_R30 tmp3,
10073 rFlagsReg cr)
10074 %{
10075 predicate(!UseRVV && ((StrCompNode *)n)->encoding() == StrIntrinsicNode::LU);
10076 match(Set result (StrComp(Binary str1 cnt1)(Binary str2 cnt2)));
10077 effect(KILL tmp1, KILL tmp2, KILL tmp3, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
10078
10079 format %{ "String Compare $str1, $cnt1, $str2, $cnt2 -> $result\t#@string_compareLU" %}
10080 ins_encode %{
10081 __ string_compare($str1$$Register, $str2$$Register,
10082 $cnt1$$Register, $cnt2$$Register, $result$$Register,
10083 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
10084 StrIntrinsicNode::LU);
10085 %}
10086 ins_pipe(pipe_class_memory);
10087 %}
10088
10089 instruct string_indexofUU(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
10090 iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3,
10091 iRegINoSp tmp4, iRegINoSp tmp5, iRegINoSp tmp6, rFlagsReg cr)
10092 %{
10093 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU);
10094 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
10095 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, TEMP_DEF result,
10096 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, TEMP tmp6, KILL cr);
10097
10098 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result (UU)" %}
10099 ins_encode %{
10100 __ string_indexof($str1$$Register, $str2$$Register,
10101 $cnt1$$Register, $cnt2$$Register,
10102 $tmp1$$Register, $tmp2$$Register,
10103 $tmp3$$Register, $tmp4$$Register,
10104 $tmp5$$Register, $tmp6$$Register,
10105 $result$$Register, StrIntrinsicNode::UU);
10106 %}
10107 ins_pipe(pipe_class_memory);
10108 %}
10109
10110 instruct string_indexofLL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
10111 iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3,
10112 iRegINoSp tmp4, iRegINoSp tmp5, iRegINoSp tmp6, rFlagsReg cr)
10113 %{
10114 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL);
10115 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
10116 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, TEMP_DEF result,
10117 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, TEMP tmp6, KILL cr);
10118
10119 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result (LL)" %}
10120 ins_encode %{
10121 __ string_indexof($str1$$Register, $str2$$Register,
10122 $cnt1$$Register, $cnt2$$Register,
10123 $tmp1$$Register, $tmp2$$Register,
10124 $tmp3$$Register, $tmp4$$Register,
10125 $tmp5$$Register, $tmp6$$Register,
10126 $result$$Register, StrIntrinsicNode::LL);
10127 %}
10128 ins_pipe(pipe_class_memory);
10129 %}
10130
10131 instruct string_indexofUL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
10132 iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3,
10133 iRegINoSp tmp4, iRegINoSp tmp5, iRegINoSp tmp6, rFlagsReg cr)
10134 %{
10135 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL);
10136 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
10137 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, TEMP_DEF result,
10138 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, TEMP tmp6, KILL cr);
10139 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result (UL)" %}
10140
10141 ins_encode %{
10142 __ string_indexof($str1$$Register, $str2$$Register,
10143 $cnt1$$Register, $cnt2$$Register,
10144 $tmp1$$Register, $tmp2$$Register,
10145 $tmp3$$Register, $tmp4$$Register,
10146 $tmp5$$Register, $tmp6$$Register,
10147 $result$$Register, StrIntrinsicNode::UL);
10148 %}
10149 ins_pipe(pipe_class_memory);
10150 %}
10151
10152 instruct string_indexof_conUU(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2,
10153 immI_le_4 int_cnt2, iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2,
10154 iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
10155 %{
10156 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU);
10157 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
10158 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, TEMP_DEF result,
10159 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
10160
10161 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result (UU)" %}
10162
10163 ins_encode %{
10164 int icnt2 = (int)$int_cnt2$$constant;
10165 __ string_indexof_linearscan($str1$$Register, $str2$$Register,
10166 $cnt1$$Register, zr,
10167 $tmp1$$Register, $tmp2$$Register,
10168 $tmp3$$Register, $tmp4$$Register,
10169 icnt2, $result$$Register, StrIntrinsicNode::UU);
10170 %}
10171 ins_pipe(pipe_class_memory);
10172 %}
10173
10174 instruct string_indexof_conLL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2,
10175 immI_le_4 int_cnt2, iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2,
10176 iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
10177 %{
10178 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL);
10179 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
10180 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, TEMP_DEF result,
10181 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
10182
10183 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result (LL)" %}
10184 ins_encode %{
10185 int icnt2 = (int)$int_cnt2$$constant;
10186 __ string_indexof_linearscan($str1$$Register, $str2$$Register,
10187 $cnt1$$Register, zr,
10188 $tmp1$$Register, $tmp2$$Register,
10189 $tmp3$$Register, $tmp4$$Register,
10190 icnt2, $result$$Register, StrIntrinsicNode::LL);
10191 %}
10192 ins_pipe(pipe_class_memory);
10193 %}
10194
10195 instruct string_indexof_conUL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2,
10196 immI_1 int_cnt2, iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2,
10197 iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
10198 %{
10199 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL);
10200 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
10201 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, TEMP_DEF result,
10202 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
10203
10204 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result (UL)" %}
10205 ins_encode %{
10206 int icnt2 = (int)$int_cnt2$$constant;
10207 __ string_indexof_linearscan($str1$$Register, $str2$$Register,
10208 $cnt1$$Register, zr,
10209 $tmp1$$Register, $tmp2$$Register,
10210 $tmp3$$Register, $tmp4$$Register,
10211 icnt2, $result$$Register, StrIntrinsicNode::UL);
10212 %}
10213 ins_pipe(pipe_class_memory);
10214 %}
10215
10216 instruct stringU_indexof_char(iRegP_R11 str1, iRegI_R12 cnt1, iRegI_R13 ch,
10217 iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2,
10218 iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
10219 %{
10220 match(Set result (StrIndexOfChar (Binary str1 cnt1) ch));
10221 predicate(!UseRVV && (((StrIndexOfCharNode*)n)->encoding() == StrIntrinsicNode::U));
10222 effect(USE_KILL str1, USE_KILL cnt1, USE_KILL ch, TEMP_DEF result,
10223 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
10224
10225 format %{ "StringUTF16 IndexOf char[] $str1,$cnt1,$ch -> $result" %}
10226 ins_encode %{
10227 __ string_indexof_char($str1$$Register, $cnt1$$Register, $ch$$Register,
10228 $result$$Register, $tmp1$$Register, $tmp2$$Register,
10229 $tmp3$$Register, $tmp4$$Register, false /* isU */);
10230 %}
10231 ins_pipe(pipe_class_memory);
10232 %}
10233
10234
10235 instruct stringL_indexof_char(iRegP_R11 str1, iRegI_R12 cnt1, iRegI_R13 ch,
10236 iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2,
10237 iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
10238 %{
10239 match(Set result (StrIndexOfChar (Binary str1 cnt1) ch));
10240 predicate(!UseRVV && (((StrIndexOfCharNode*)n)->encoding() == StrIntrinsicNode::L));
10241 effect(USE_KILL str1, USE_KILL cnt1, USE_KILL ch, TEMP_DEF result,
10242 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
10243
10244 format %{ "StringUTF16 IndexOf char[] $str1,$cnt1,$ch -> $result" %}
10245 ins_encode %{
10246 __ string_indexof_char($str1$$Register, $cnt1$$Register, $ch$$Register,
10247 $result$$Register, $tmp1$$Register, $tmp2$$Register,
10248 $tmp3$$Register, $tmp4$$Register, true /* isL */);
10249 %}
10250 ins_pipe(pipe_class_memory);
10251 %}
10252
10253 // clearing of an array
10254 instruct clearArray_reg_reg(iRegL_R29 cnt, iRegP_R28 base, Universe dummy)
10255 %{
10256 predicate(!UseRVV);
10257 match(Set dummy (ClearArray cnt base));
10258 effect(USE_KILL cnt, USE_KILL base);
10259
10260 ins_cost(4 * DEFAULT_COST);
10261 format %{ "ClearArray $cnt, $base\t#@clearArray_reg_reg" %}
10262
10263 ins_encode %{
10264 address tpc = __ zero_words($base$$Register, $cnt$$Register);
10265 if (tpc == NULL) {
10266 ciEnv::current()->record_failure("CodeCache is full");
10267 return;
10268 }
10269 %}
10270
10271 ins_pipe(pipe_class_memory);
10272 %}
10273
10274 instruct clearArray_imm_reg(immL cnt, iRegP_R28 base, Universe dummy, rFlagsReg cr)
10275 %{
10276 predicate(!UseRVV && (uint64_t)n->in(2)->get_long()
10277 < (uint64_t)(BlockZeroingLowLimit >> LogBytesPerWord));
10278 match(Set dummy (ClearArray cnt base));
10279 effect(USE_KILL base, KILL cr);
10280
10281 ins_cost(4 * DEFAULT_COST);
10282 format %{ "ClearArray $cnt, $base\t#@clearArray_imm_reg" %}
10283
10284 ins_encode %{
10285 __ zero_words($base$$Register, (uint64_t)$cnt$$constant);
10286 %}
10287
10288 ins_pipe(pipe_class_memory);
10289 %}
10290
10291 instruct string_equalsL(iRegP_R11 str1, iRegP_R13 str2, iRegI_R14 cnt,
10292 iRegI_R10 result, rFlagsReg cr)
10293 %{
10294 predicate(!UseRVV && ((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::LL);
10295 match(Set result (StrEquals (Binary str1 str2) cnt));
10296 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL cr);
10297
10298 format %{ "String Equals $str1, $str2, $cnt -> $result\t#@string_equalsL" %}
10299 ins_encode %{
10300 // Count is in 8-bit bytes; non-Compact chars are 16 bits.
10301 __ string_equals($str1$$Register, $str2$$Register,
10302 $result$$Register, $cnt$$Register, 1);
10303 %}
10304 ins_pipe(pipe_class_memory);
10305 %}
10306
10307 instruct string_equalsU(iRegP_R11 str1, iRegP_R13 str2, iRegI_R14 cnt,
10308 iRegI_R10 result, rFlagsReg cr)
10309 %{
10310 predicate(!UseRVV && ((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::UU);
10311 match(Set result (StrEquals (Binary str1 str2) cnt));
10312 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL cr);
10313
10314 format %{ "String Equals $str1, $str2, $cnt -> $result\t#@string_equalsU" %}
10315 ins_encode %{
10316 // Count is in 8-bit bytes; non-Compact chars are 16 bits.
10317 __ string_equals($str1$$Register, $str2$$Register,
10318 $result$$Register, $cnt$$Register, 2);
10319 %}
10320 ins_pipe(pipe_class_memory);
10321 %}
10322
10323 instruct array_equalsB(iRegP_R11 ary1, iRegP_R12 ary2, iRegI_R10 result,
10324 iRegP_R13 tmp1, iRegP_R14 tmp2, iRegP_R15 tmp3,
10325 iRegP_R16 tmp4, iRegP_R28 tmp5, rFlagsReg cr)
10326 %{
10327 predicate(!UseRVV && ((AryEqNode*)n)->encoding() == StrIntrinsicNode::LL);
10328 match(Set result (AryEq ary1 ary2));
10329 effect(USE_KILL ary1, USE_KILL ary2, TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL tmp5, KILL cr);
10330
10331 format %{ "Array Equals $ary1, ary2 -> $result\t#@array_equalsB // KILL $tmp5" %}
10332 ins_encode %{
10333 __ arrays_equals($ary1$$Register, $ary2$$Register,
10334 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register,
10335 $result$$Register, $tmp5$$Register, 1);
10336 %}
10337 ins_pipe(pipe_class_memory);
10338 %}
10339
10340 instruct array_equalsC(iRegP_R11 ary1, iRegP_R12 ary2, iRegI_R10 result,
10341 iRegP_R13 tmp1, iRegP_R14 tmp2, iRegP_R15 tmp3,
10342 iRegP_R16 tmp4, iRegP_R28 tmp5, rFlagsReg cr)
10343 %{
10344 predicate(!UseRVV && ((AryEqNode*)n)->encoding() == StrIntrinsicNode::UU);
10345 match(Set result (AryEq ary1 ary2));
10346 effect(USE_KILL ary1, USE_KILL ary2, TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL tmp5, KILL cr);
10347
10348 format %{ "Array Equals $ary1, ary2 -> $result\t#@array_equalsC // KILL $tmp5" %}
10349 ins_encode %{
10350 __ arrays_equals($ary1$$Register, $ary2$$Register,
10351 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register,
10352 $result$$Register, $tmp5$$Register, 2);
10353 %}
10354 ins_pipe(pipe_class_memory);
10355 %}
10356
10357 // ============================================================================
10358 // Safepoint Instructions
10359
10360 instruct safePoint(iRegP poll)
10361 %{
10362 match(SafePoint poll);
10363
10364 ins_cost(2 * LOAD_COST);
10365 format %{
10366 "lwu zr, [$poll]\t# Safepoint: poll for GC, #@safePoint"
10367 %}
10368 ins_encode %{
10369 __ read_polling_page(as_Register($poll$$reg), 0, relocInfo::poll_type);
10370 %}
10371 ins_pipe(pipe_serial); // ins_pipe(iload_reg_mem);
10372 %}
10373
10374 // ============================================================================
10375 // This name is KNOWN by the ADLC and cannot be changed.
10376 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
10377 // for this guy.
10378 instruct tlsLoadP(javaThread_RegP dst)
10379 %{
10380 match(Set dst (ThreadLocal));
10381
10382 ins_cost(0);
10383
10384 format %{ " -- \t// $dst=Thread::current(), empty, #@tlsLoadP" %}
10385
10386 size(0);
10387
10388 ins_encode( /*empty*/ );
10389
10390 ins_pipe(pipe_class_empty);
10391 %}
10392
10393 // inlined locking and unlocking
10394 // using t1 as the 'flag' register to bridge the BoolNode producers and consumers
10395 instruct cmpFastLock(rFlagsReg cr, iRegP object, iRegP box, iRegPNoSp tmp1, iRegPNoSp tmp2)
10396 %{
10397 match(Set cr (FastLock object box));
10398 effect(TEMP tmp1, TEMP tmp2);
10399
10400 ins_cost(LOAD_COST * 2 + STORE_COST * 3 + ALU_COST * 6 + BRANCH_COST * 3);
10401 format %{ "fastlock $object,$box\t! kills $tmp1,$tmp2, #@cmpFastLock" %}
10402
10403 ins_encode(riscv_enc_fast_lock(object, box, tmp1, tmp2));
10404
10405 ins_pipe(pipe_serial);
10406 %}
10407
10408 // using t1 as the 'flag' register to bridge the BoolNode producers and consumers
10409 instruct cmpFastUnlock(rFlagsReg cr, iRegP object, iRegP box, iRegPNoSp tmp1, iRegPNoSp tmp2)
10410 %{
10411 match(Set cr (FastUnlock object box));
10412 effect(TEMP tmp1, TEMP tmp2);
10413
10414 ins_cost(LOAD_COST * 2 + STORE_COST + ALU_COST * 2 + BRANCH_COST * 4);
10415 format %{ "fastunlock $object,$box\t! kills $tmp1, $tmp2, #@cmpFastUnlock" %}
10416
10417 ins_encode(riscv_enc_fast_unlock(object, box, tmp1, tmp2));
10418
10419 ins_pipe(pipe_serial);
10420 %}
10421
10422 // Tail Call; Jump from runtime stub to Java code.
10423 // Also known as an 'interprocedural jump'.
10424 // Target of jump will eventually return to caller.
10425 // TailJump below removes the return address.
10426 instruct TailCalljmpInd(iRegPNoSp jump_target, inline_cache_RegP method_oop)
10427 %{
10428 match(TailCall jump_target method_oop);
10429
10430 ins_cost(BRANCH_COST);
10431
10432 format %{ "jalr $jump_target\t# $method_oop holds method oop, #@TailCalljmpInd." %}
10433
10434 ins_encode(riscv_enc_tail_call(jump_target));
10435
10436 ins_pipe(pipe_class_call);
10437 %}
10438
10439 instruct TailjmpInd(iRegPNoSp jump_target, iRegP_R10 ex_oop)
10440 %{
10441 match(TailJump jump_target ex_oop);
10442
10443 ins_cost(ALU_COST + BRANCH_COST);
10444
10445 format %{ "jalr $jump_target\t# $ex_oop holds exception oop, #@TailjmpInd." %}
10446
10447 ins_encode(riscv_enc_tail_jmp(jump_target));
10448
10449 ins_pipe(pipe_class_call);
10450 %}
10451
10452 // Create exception oop: created by stack-crawling runtime code.
10453 // Created exception is now available to this handler, and is setup
10454 // just prior to jumping to this handler. No code emitted.
10455 instruct CreateException(iRegP_R10 ex_oop)
10456 %{
10457 match(Set ex_oop (CreateEx));
10458
10459 ins_cost(0);
10460 format %{ " -- \t// exception oop; no code emitted, #@CreateException" %}
10461
10462 size(0);
10463
10464 ins_encode( /*empty*/ );
10465
10466 ins_pipe(pipe_class_empty);
10467 %}
10468
10469 // Rethrow exception: The exception oop will come in the first
10470 // argument position. Then JUMP (not call) to the rethrow stub code.
10471 instruct RethrowException()
10472 %{
10473 match(Rethrow);
10474
10475 ins_cost(BRANCH_COST);
10476
10477 format %{ "j rethrow_stub\t#@RethrowException" %}
10478
10479 ins_encode(riscv_enc_rethrow());
10480
10481 ins_pipe(pipe_class_call);
10482 %}
10483
10484 // Return Instruction
10485 // epilog node loads ret address into ra as part of frame pop
10486 instruct Ret()
10487 %{
10488 match(Return);
10489
10490 ins_cost(BRANCH_COST);
10491 format %{ "ret\t// return register, #@Ret" %}
10492
10493 ins_encode(riscv_enc_ret());
10494
10495 ins_pipe(pipe_branch);
10496 %}
10497
10498 // Die now.
10499 instruct ShouldNotReachHere() %{
10500 match(Halt);
10501
10502 ins_cost(BRANCH_COST);
10503
10504 format %{ "#@ShouldNotReachHere" %}
10505
10506 ins_encode %{
10507 if (is_reachable()) {
10508 __ stop(_halt_reason);
10509 }
10510 %}
10511
10512 ins_pipe(pipe_class_default);
10513 %}
10514
10515
10516 //----------PEEPHOLE RULES-----------------------------------------------------
10517 // These must follow all instruction definitions as they use the names
10518 // defined in the instructions definitions.
10519 //
10520 // peepmatch ( root_instr_name [preceding_instruction]* );
10521 //
10522 // peepconstraint %{
10523 // (instruction_number.operand_name relational_op instruction_number.operand_name
10524 // [, ...] );
10525 // // instruction numbers are zero-based using left to right order in peepmatch
10526 //
10527 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
10528 // // provide an instruction_number.operand_name for each operand that appears
10529 // // in the replacement instruction's match rule
10530 //
10531 // ---------VM FLAGS---------------------------------------------------------
10532 //
10533 // All peephole optimizations can be turned off using -XX:-OptoPeephole
10534 //
10535 // Each peephole rule is given an identifying number starting with zero and
10536 // increasing by one in the order seen by the parser. An individual peephole
10537 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
10538 // on the command-line.
10539 //
10540 // ---------CURRENT LIMITATIONS----------------------------------------------
10541 //
10542 // Only match adjacent instructions in same basic block
10543 // Only equality constraints
10544 // Only constraints between operands, not (0.dest_reg == RAX_enc)
10545 // Only one replacement instruction
10546 //
10547 //----------SMARTSPILL RULES---------------------------------------------------
10548 // These must follow all instruction definitions as they use the names
10549 // defined in the instructions definitions.
10550
10551 // Local Variables:
10552 // mode: c++
10553 // End: