1 //
2 // Copyright (c) 2003, 2024, Oracle and/or its affiliates. All rights reserved.
3 // Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
4 // Copyright (c) 2020, 2024, Huawei Technologies Co., Ltd. All rights reserved.
5 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
6 //
7 // This code is free software; you can redistribute it and/or modify it
8 // under the terms of the GNU General Public License version 2 only, as
9 // published by the Free Software Foundation.
10 //
11 // This code is distributed in the hope that it will be useful, but WITHOUT
12 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 // version 2 for more details (a copy is included in the LICENSE file that
15 // accompanied this code).
16 //
17 // You should have received a copy of the GNU General Public License version
18 // 2 along with this work; if not, write to the Free Software Foundation,
19 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
20 //
21 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
22 // or visit www.oracle.com if you need additional information or have any
23 // questions.
24 //
25 //
26
27 // RISCV Architecture Description File
28
29 //----------REGISTER DEFINITION BLOCK------------------------------------------
30 // This information is used by the matcher and the register allocator to
31 // describe individual registers and classes of registers within the target
32 // architecture.
33
34 register %{
35 //----------Architecture Description Register Definitions----------------------
36 // General Registers
37 // "reg_def" name ( register save type, C convention save type,
38 // ideal register type, encoding );
39 // Register Save Types:
40 //
41 // NS = No-Save: The register allocator assumes that these registers
42 // can be used without saving upon entry to the method, &
43 // that they do not need to be saved at call sites.
44 //
45 // SOC = Save-On-Call: The register allocator assumes that these registers
46 // can be used without saving upon entry to the method,
47 // but that they must be saved at call sites.
48 //
49 // SOE = Save-On-Entry: The register allocator assumes that these registers
50 // must be saved before using them upon entry to the
51 // method, but they do not need to be saved at call
52 // sites.
53 //
54 // AS = Always-Save: The register allocator assumes that these registers
55 // must be saved before using them upon entry to the
56 // method, & that they must be saved at call sites.
57 //
58 // Ideal Register Type is used to determine how to save & restore a
59 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
60 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
61 //
62 // The encoding number is the actual bit-pattern placed into the opcodes.
63
64 // We must define the 64 bit int registers in two 32 bit halves, the
65 // real lower register and a virtual upper half register. upper halves
66 // are used by the register allocator but are not actually supplied as
67 // operands to memory ops.
68 //
69 // follow the C1 compiler in making registers
70 //
71 // x7, x9-x17, x27-x31 volatile (caller save)
72 // x0-x4, x8, x23 system (no save, no allocate)
73 // x5-x6 non-allocatable (so we can use them as temporary regs)
74
75 //
76 // as regards Java usage. we don't use any callee save registers
77 // because this makes it difficult to de-optimise a frame (see comment
78 // in x86 implementation of Deoptimization::unwind_callee_save_values)
79 //
80
81 // General Registers
82
83 reg_def R0 ( NS, NS, Op_RegI, 0, x0->as_VMReg() ); // zr
84 reg_def R0_H ( NS, NS, Op_RegI, 0, x0->as_VMReg()->next() );
85 reg_def R1 ( NS, SOC, Op_RegI, 1, x1->as_VMReg() ); // ra
86 reg_def R1_H ( NS, SOC, Op_RegI, 1, x1->as_VMReg()->next() );
87 reg_def R2 ( NS, NS, Op_RegI, 2, x2->as_VMReg() ); // sp
88 reg_def R2_H ( NS, NS, Op_RegI, 2, x2->as_VMReg()->next() );
89 reg_def R3 ( NS, NS, Op_RegI, 3, x3->as_VMReg() ); // gp
90 reg_def R3_H ( NS, NS, Op_RegI, 3, x3->as_VMReg()->next() );
91 reg_def R4 ( NS, NS, Op_RegI, 4, x4->as_VMReg() ); // tp
92 reg_def R4_H ( NS, NS, Op_RegI, 4, x4->as_VMReg()->next() );
93 reg_def R7 ( SOC, SOC, Op_RegI, 7, x7->as_VMReg() );
94 reg_def R7_H ( SOC, SOC, Op_RegI, 7, x7->as_VMReg()->next() );
95 reg_def R8 ( NS, SOE, Op_RegI, 8, x8->as_VMReg() ); // fp
96 reg_def R8_H ( NS, SOE, Op_RegI, 8, x8->as_VMReg()->next() );
97 reg_def R9 ( SOC, SOE, Op_RegI, 9, x9->as_VMReg() );
98 reg_def R9_H ( SOC, SOE, Op_RegI, 9, x9->as_VMReg()->next() );
99 reg_def R10 ( SOC, SOC, Op_RegI, 10, x10->as_VMReg() );
100 reg_def R10_H ( SOC, SOC, Op_RegI, 10, x10->as_VMReg()->next());
101 reg_def R11 ( SOC, SOC, Op_RegI, 11, x11->as_VMReg() );
102 reg_def R11_H ( SOC, SOC, Op_RegI, 11, x11->as_VMReg()->next());
103 reg_def R12 ( SOC, SOC, Op_RegI, 12, x12->as_VMReg() );
104 reg_def R12_H ( SOC, SOC, Op_RegI, 12, x12->as_VMReg()->next());
105 reg_def R13 ( SOC, SOC, Op_RegI, 13, x13->as_VMReg() );
106 reg_def R13_H ( SOC, SOC, Op_RegI, 13, x13->as_VMReg()->next());
107 reg_def R14 ( SOC, SOC, Op_RegI, 14, x14->as_VMReg() );
108 reg_def R14_H ( SOC, SOC, Op_RegI, 14, x14->as_VMReg()->next());
109 reg_def R15 ( SOC, SOC, Op_RegI, 15, x15->as_VMReg() );
110 reg_def R15_H ( SOC, SOC, Op_RegI, 15, x15->as_VMReg()->next());
111 reg_def R16 ( SOC, SOC, Op_RegI, 16, x16->as_VMReg() );
112 reg_def R16_H ( SOC, SOC, Op_RegI, 16, x16->as_VMReg()->next());
113 reg_def R17 ( SOC, SOC, Op_RegI, 17, x17->as_VMReg() );
114 reg_def R17_H ( SOC, SOC, Op_RegI, 17, x17->as_VMReg()->next());
115 reg_def R18 ( SOC, SOE, Op_RegI, 18, x18->as_VMReg() );
116 reg_def R18_H ( SOC, SOE, Op_RegI, 18, x18->as_VMReg()->next());
117 reg_def R19 ( SOC, SOE, Op_RegI, 19, x19->as_VMReg() );
118 reg_def R19_H ( SOC, SOE, Op_RegI, 19, x19->as_VMReg()->next());
119 reg_def R20 ( SOC, SOE, Op_RegI, 20, x20->as_VMReg() ); // caller esp
120 reg_def R20_H ( SOC, SOE, Op_RegI, 20, x20->as_VMReg()->next());
121 reg_def R21 ( SOC, SOE, Op_RegI, 21, x21->as_VMReg() );
122 reg_def R21_H ( SOC, SOE, Op_RegI, 21, x21->as_VMReg()->next());
123 reg_def R22 ( SOC, SOE, Op_RegI, 22, x22->as_VMReg() );
124 reg_def R22_H ( SOC, SOE, Op_RegI, 22, x22->as_VMReg()->next());
125 reg_def R23 ( NS, SOE, Op_RegI, 23, x23->as_VMReg() ); // java thread
126 reg_def R23_H ( NS, SOE, Op_RegI, 23, x23->as_VMReg()->next());
127 reg_def R24 ( SOC, SOE, Op_RegI, 24, x24->as_VMReg() );
128 reg_def R24_H ( SOC, SOE, Op_RegI, 24, x24->as_VMReg()->next());
129 reg_def R25 ( SOC, SOE, Op_RegI, 25, x25->as_VMReg() );
130 reg_def R25_H ( SOC, SOE, Op_RegI, 25, x25->as_VMReg()->next());
131 reg_def R26 ( SOC, SOE, Op_RegI, 26, x26->as_VMReg() );
132 reg_def R26_H ( SOC, SOE, Op_RegI, 26, x26->as_VMReg()->next());
133 reg_def R27 ( SOC, SOE, Op_RegI, 27, x27->as_VMReg() ); // heapbase
134 reg_def R27_H ( SOC, SOE, Op_RegI, 27, x27->as_VMReg()->next());
135 reg_def R28 ( SOC, SOC, Op_RegI, 28, x28->as_VMReg() );
136 reg_def R28_H ( SOC, SOC, Op_RegI, 28, x28->as_VMReg()->next());
137 reg_def R29 ( SOC, SOC, Op_RegI, 29, x29->as_VMReg() );
138 reg_def R29_H ( SOC, SOC, Op_RegI, 29, x29->as_VMReg()->next());
139 reg_def R30 ( SOC, SOC, Op_RegI, 30, x30->as_VMReg() );
140 reg_def R30_H ( SOC, SOC, Op_RegI, 30, x30->as_VMReg()->next());
141 reg_def R31 ( SOC, SOC, Op_RegI, 31, x31->as_VMReg() );
142 reg_def R31_H ( SOC, SOC, Op_RegI, 31, x31->as_VMReg()->next());
143
144 // ----------------------------
145 // Float/Double Registers
146 // ----------------------------
147
148 // Double Registers
149
150 // The rules of ADL require that double registers be defined in pairs.
151 // Each pair must be two 32-bit values, but not necessarily a pair of
152 // single float registers. In each pair, ADLC-assigned register numbers
153 // must be adjacent, with the lower number even. Finally, when the
154 // CPU stores such a register pair to memory, the word associated with
155 // the lower ADLC-assigned number must be stored to the lower address.
156
157 // RISCV has 32 floating-point registers. Each can store a single
158 // or double precision floating-point value.
159
160 // for Java use float registers f0-f31 are always save on call whereas
161 // the platform ABI treats f8-f9 and f18-f27 as callee save). Other
162 // float registers are SOC as per the platform spec
163
164 reg_def F0 ( SOC, SOC, Op_RegF, 0, f0->as_VMReg() );
165 reg_def F0_H ( SOC, SOC, Op_RegF, 0, f0->as_VMReg()->next() );
166 reg_def F1 ( SOC, SOC, Op_RegF, 1, f1->as_VMReg() );
167 reg_def F1_H ( SOC, SOC, Op_RegF, 1, f1->as_VMReg()->next() );
168 reg_def F2 ( SOC, SOC, Op_RegF, 2, f2->as_VMReg() );
169 reg_def F2_H ( SOC, SOC, Op_RegF, 2, f2->as_VMReg()->next() );
170 reg_def F3 ( SOC, SOC, Op_RegF, 3, f3->as_VMReg() );
171 reg_def F3_H ( SOC, SOC, Op_RegF, 3, f3->as_VMReg()->next() );
172 reg_def F4 ( SOC, SOC, Op_RegF, 4, f4->as_VMReg() );
173 reg_def F4_H ( SOC, SOC, Op_RegF, 4, f4->as_VMReg()->next() );
174 reg_def F5 ( SOC, SOC, Op_RegF, 5, f5->as_VMReg() );
175 reg_def F5_H ( SOC, SOC, Op_RegF, 5, f5->as_VMReg()->next() );
176 reg_def F6 ( SOC, SOC, Op_RegF, 6, f6->as_VMReg() );
177 reg_def F6_H ( SOC, SOC, Op_RegF, 6, f6->as_VMReg()->next() );
178 reg_def F7 ( SOC, SOC, Op_RegF, 7, f7->as_VMReg() );
179 reg_def F7_H ( SOC, SOC, Op_RegF, 7, f7->as_VMReg()->next() );
180 reg_def F8 ( SOC, SOE, Op_RegF, 8, f8->as_VMReg() );
181 reg_def F8_H ( SOC, SOE, Op_RegF, 8, f8->as_VMReg()->next() );
182 reg_def F9 ( SOC, SOE, Op_RegF, 9, f9->as_VMReg() );
183 reg_def F9_H ( SOC, SOE, Op_RegF, 9, f9->as_VMReg()->next() );
184 reg_def F10 ( SOC, SOC, Op_RegF, 10, f10->as_VMReg() );
185 reg_def F10_H ( SOC, SOC, Op_RegF, 10, f10->as_VMReg()->next() );
186 reg_def F11 ( SOC, SOC, Op_RegF, 11, f11->as_VMReg() );
187 reg_def F11_H ( SOC, SOC, Op_RegF, 11, f11->as_VMReg()->next() );
188 reg_def F12 ( SOC, SOC, Op_RegF, 12, f12->as_VMReg() );
189 reg_def F12_H ( SOC, SOC, Op_RegF, 12, f12->as_VMReg()->next() );
190 reg_def F13 ( SOC, SOC, Op_RegF, 13, f13->as_VMReg() );
191 reg_def F13_H ( SOC, SOC, Op_RegF, 13, f13->as_VMReg()->next() );
192 reg_def F14 ( SOC, SOC, Op_RegF, 14, f14->as_VMReg() );
193 reg_def F14_H ( SOC, SOC, Op_RegF, 14, f14->as_VMReg()->next() );
194 reg_def F15 ( SOC, SOC, Op_RegF, 15, f15->as_VMReg() );
195 reg_def F15_H ( SOC, SOC, Op_RegF, 15, f15->as_VMReg()->next() );
196 reg_def F16 ( SOC, SOC, Op_RegF, 16, f16->as_VMReg() );
197 reg_def F16_H ( SOC, SOC, Op_RegF, 16, f16->as_VMReg()->next() );
198 reg_def F17 ( SOC, SOC, Op_RegF, 17, f17->as_VMReg() );
199 reg_def F17_H ( SOC, SOC, Op_RegF, 17, f17->as_VMReg()->next() );
200 reg_def F18 ( SOC, SOE, Op_RegF, 18, f18->as_VMReg() );
201 reg_def F18_H ( SOC, SOE, Op_RegF, 18, f18->as_VMReg()->next() );
202 reg_def F19 ( SOC, SOE, Op_RegF, 19, f19->as_VMReg() );
203 reg_def F19_H ( SOC, SOE, Op_RegF, 19, f19->as_VMReg()->next() );
204 reg_def F20 ( SOC, SOE, Op_RegF, 20, f20->as_VMReg() );
205 reg_def F20_H ( SOC, SOE, Op_RegF, 20, f20->as_VMReg()->next() );
206 reg_def F21 ( SOC, SOE, Op_RegF, 21, f21->as_VMReg() );
207 reg_def F21_H ( SOC, SOE, Op_RegF, 21, f21->as_VMReg()->next() );
208 reg_def F22 ( SOC, SOE, Op_RegF, 22, f22->as_VMReg() );
209 reg_def F22_H ( SOC, SOE, Op_RegF, 22, f22->as_VMReg()->next() );
210 reg_def F23 ( SOC, SOE, Op_RegF, 23, f23->as_VMReg() );
211 reg_def F23_H ( SOC, SOE, Op_RegF, 23, f23->as_VMReg()->next() );
212 reg_def F24 ( SOC, SOE, Op_RegF, 24, f24->as_VMReg() );
213 reg_def F24_H ( SOC, SOE, Op_RegF, 24, f24->as_VMReg()->next() );
214 reg_def F25 ( SOC, SOE, Op_RegF, 25, f25->as_VMReg() );
215 reg_def F25_H ( SOC, SOE, Op_RegF, 25, f25->as_VMReg()->next() );
216 reg_def F26 ( SOC, SOE, Op_RegF, 26, f26->as_VMReg() );
217 reg_def F26_H ( SOC, SOE, Op_RegF, 26, f26->as_VMReg()->next() );
218 reg_def F27 ( SOC, SOE, Op_RegF, 27, f27->as_VMReg() );
219 reg_def F27_H ( SOC, SOE, Op_RegF, 27, f27->as_VMReg()->next() );
220 reg_def F28 ( SOC, SOC, Op_RegF, 28, f28->as_VMReg() );
221 reg_def F28_H ( SOC, SOC, Op_RegF, 28, f28->as_VMReg()->next() );
222 reg_def F29 ( SOC, SOC, Op_RegF, 29, f29->as_VMReg() );
223 reg_def F29_H ( SOC, SOC, Op_RegF, 29, f29->as_VMReg()->next() );
224 reg_def F30 ( SOC, SOC, Op_RegF, 30, f30->as_VMReg() );
225 reg_def F30_H ( SOC, SOC, Op_RegF, 30, f30->as_VMReg()->next() );
226 reg_def F31 ( SOC, SOC, Op_RegF, 31, f31->as_VMReg() );
227 reg_def F31_H ( SOC, SOC, Op_RegF, 31, f31->as_VMReg()->next() );
228
229 // ----------------------------
230 // Vector Registers
231 // ----------------------------
232
233 // For RVV vector registers, we simply extend vector register size to 4
234 // 'logical' slots. This is nominally 128 bits but it actually covers
235 // all possible 'physical' RVV vector register lengths from 128 ~ 1024
236 // bits. The 'physical' RVV vector register length is detected during
237 // startup, so the register allocator is able to identify the correct
238 // number of bytes needed for an RVV spill/unspill.
239
240 reg_def V0 ( SOC, SOC, Op_VecA, 0, v0->as_VMReg() );
241 reg_def V0_H ( SOC, SOC, Op_VecA, 0, v0->as_VMReg()->next() );
242 reg_def V0_J ( SOC, SOC, Op_VecA, 0, v0->as_VMReg()->next(2) );
243 reg_def V0_K ( SOC, SOC, Op_VecA, 0, v0->as_VMReg()->next(3) );
244
245 reg_def V1 ( SOC, SOC, Op_VecA, 1, v1->as_VMReg() );
246 reg_def V1_H ( SOC, SOC, Op_VecA, 1, v1->as_VMReg()->next() );
247 reg_def V1_J ( SOC, SOC, Op_VecA, 1, v1->as_VMReg()->next(2) );
248 reg_def V1_K ( SOC, SOC, Op_VecA, 1, v1->as_VMReg()->next(3) );
249
250 reg_def V2 ( SOC, SOC, Op_VecA, 2, v2->as_VMReg() );
251 reg_def V2_H ( SOC, SOC, Op_VecA, 2, v2->as_VMReg()->next() );
252 reg_def V2_J ( SOC, SOC, Op_VecA, 2, v2->as_VMReg()->next(2) );
253 reg_def V2_K ( SOC, SOC, Op_VecA, 2, v2->as_VMReg()->next(3) );
254
255 reg_def V3 ( SOC, SOC, Op_VecA, 3, v3->as_VMReg() );
256 reg_def V3_H ( SOC, SOC, Op_VecA, 3, v3->as_VMReg()->next() );
257 reg_def V3_J ( SOC, SOC, Op_VecA, 3, v3->as_VMReg()->next(2) );
258 reg_def V3_K ( SOC, SOC, Op_VecA, 3, v3->as_VMReg()->next(3) );
259
260 reg_def V4 ( SOC, SOC, Op_VecA, 4, v4->as_VMReg() );
261 reg_def V4_H ( SOC, SOC, Op_VecA, 4, v4->as_VMReg()->next() );
262 reg_def V4_J ( SOC, SOC, Op_VecA, 4, v4->as_VMReg()->next(2) );
263 reg_def V4_K ( SOC, SOC, Op_VecA, 4, v4->as_VMReg()->next(3) );
264
265 reg_def V5 ( SOC, SOC, Op_VecA, 5, v5->as_VMReg() );
266 reg_def V5_H ( SOC, SOC, Op_VecA, 5, v5->as_VMReg()->next() );
267 reg_def V5_J ( SOC, SOC, Op_VecA, 5, v5->as_VMReg()->next(2) );
268 reg_def V5_K ( SOC, SOC, Op_VecA, 5, v5->as_VMReg()->next(3) );
269
270 reg_def V6 ( SOC, SOC, Op_VecA, 6, v6->as_VMReg() );
271 reg_def V6_H ( SOC, SOC, Op_VecA, 6, v6->as_VMReg()->next() );
272 reg_def V6_J ( SOC, SOC, Op_VecA, 6, v6->as_VMReg()->next(2) );
273 reg_def V6_K ( SOC, SOC, Op_VecA, 6, v6->as_VMReg()->next(3) );
274
275 reg_def V7 ( SOC, SOC, Op_VecA, 7, v7->as_VMReg() );
276 reg_def V7_H ( SOC, SOC, Op_VecA, 7, v7->as_VMReg()->next() );
277 reg_def V7_J ( SOC, SOC, Op_VecA, 7, v7->as_VMReg()->next(2) );
278 reg_def V7_K ( SOC, SOC, Op_VecA, 7, v7->as_VMReg()->next(3) );
279
280 reg_def V8 ( SOC, SOC, Op_VecA, 8, v8->as_VMReg() );
281 reg_def V8_H ( SOC, SOC, Op_VecA, 8, v8->as_VMReg()->next() );
282 reg_def V8_J ( SOC, SOC, Op_VecA, 8, v8->as_VMReg()->next(2) );
283 reg_def V8_K ( SOC, SOC, Op_VecA, 8, v8->as_VMReg()->next(3) );
284
285 reg_def V9 ( SOC, SOC, Op_VecA, 9, v9->as_VMReg() );
286 reg_def V9_H ( SOC, SOC, Op_VecA, 9, v9->as_VMReg()->next() );
287 reg_def V9_J ( SOC, SOC, Op_VecA, 9, v9->as_VMReg()->next(2) );
288 reg_def V9_K ( SOC, SOC, Op_VecA, 9, v9->as_VMReg()->next(3) );
289
290 reg_def V10 ( SOC, SOC, Op_VecA, 10, v10->as_VMReg() );
291 reg_def V10_H ( SOC, SOC, Op_VecA, 10, v10->as_VMReg()->next() );
292 reg_def V10_J ( SOC, SOC, Op_VecA, 10, v10->as_VMReg()->next(2) );
293 reg_def V10_K ( SOC, SOC, Op_VecA, 10, v10->as_VMReg()->next(3) );
294
295 reg_def V11 ( SOC, SOC, Op_VecA, 11, v11->as_VMReg() );
296 reg_def V11_H ( SOC, SOC, Op_VecA, 11, v11->as_VMReg()->next() );
297 reg_def V11_J ( SOC, SOC, Op_VecA, 11, v11->as_VMReg()->next(2) );
298 reg_def V11_K ( SOC, SOC, Op_VecA, 11, v11->as_VMReg()->next(3) );
299
300 reg_def V12 ( SOC, SOC, Op_VecA, 12, v12->as_VMReg() );
301 reg_def V12_H ( SOC, SOC, Op_VecA, 12, v12->as_VMReg()->next() );
302 reg_def V12_J ( SOC, SOC, Op_VecA, 12, v12->as_VMReg()->next(2) );
303 reg_def V12_K ( SOC, SOC, Op_VecA, 12, v12->as_VMReg()->next(3) );
304
305 reg_def V13 ( SOC, SOC, Op_VecA, 13, v13->as_VMReg() );
306 reg_def V13_H ( SOC, SOC, Op_VecA, 13, v13->as_VMReg()->next() );
307 reg_def V13_J ( SOC, SOC, Op_VecA, 13, v13->as_VMReg()->next(2) );
308 reg_def V13_K ( SOC, SOC, Op_VecA, 13, v13->as_VMReg()->next(3) );
309
310 reg_def V14 ( SOC, SOC, Op_VecA, 14, v14->as_VMReg() );
311 reg_def V14_H ( SOC, SOC, Op_VecA, 14, v14->as_VMReg()->next() );
312 reg_def V14_J ( SOC, SOC, Op_VecA, 14, v14->as_VMReg()->next(2) );
313 reg_def V14_K ( SOC, SOC, Op_VecA, 14, v14->as_VMReg()->next(3) );
314
315 reg_def V15 ( SOC, SOC, Op_VecA, 15, v15->as_VMReg() );
316 reg_def V15_H ( SOC, SOC, Op_VecA, 15, v15->as_VMReg()->next() );
317 reg_def V15_J ( SOC, SOC, Op_VecA, 15, v15->as_VMReg()->next(2) );
318 reg_def V15_K ( SOC, SOC, Op_VecA, 15, v15->as_VMReg()->next(3) );
319
320 reg_def V16 ( SOC, SOC, Op_VecA, 16, v16->as_VMReg() );
321 reg_def V16_H ( SOC, SOC, Op_VecA, 16, v16->as_VMReg()->next() );
322 reg_def V16_J ( SOC, SOC, Op_VecA, 16, v16->as_VMReg()->next(2) );
323 reg_def V16_K ( SOC, SOC, Op_VecA, 16, v16->as_VMReg()->next(3) );
324
325 reg_def V17 ( SOC, SOC, Op_VecA, 17, v17->as_VMReg() );
326 reg_def V17_H ( SOC, SOC, Op_VecA, 17, v17->as_VMReg()->next() );
327 reg_def V17_J ( SOC, SOC, Op_VecA, 17, v17->as_VMReg()->next(2) );
328 reg_def V17_K ( SOC, SOC, Op_VecA, 17, v17->as_VMReg()->next(3) );
329
330 reg_def V18 ( SOC, SOC, Op_VecA, 18, v18->as_VMReg() );
331 reg_def V18_H ( SOC, SOC, Op_VecA, 18, v18->as_VMReg()->next() );
332 reg_def V18_J ( SOC, SOC, Op_VecA, 18, v18->as_VMReg()->next(2) );
333 reg_def V18_K ( SOC, SOC, Op_VecA, 18, v18->as_VMReg()->next(3) );
334
335 reg_def V19 ( SOC, SOC, Op_VecA, 19, v19->as_VMReg() );
336 reg_def V19_H ( SOC, SOC, Op_VecA, 19, v19->as_VMReg()->next() );
337 reg_def V19_J ( SOC, SOC, Op_VecA, 19, v19->as_VMReg()->next(2) );
338 reg_def V19_K ( SOC, SOC, Op_VecA, 19, v19->as_VMReg()->next(3) );
339
340 reg_def V20 ( SOC, SOC, Op_VecA, 20, v20->as_VMReg() );
341 reg_def V20_H ( SOC, SOC, Op_VecA, 20, v20->as_VMReg()->next() );
342 reg_def V20_J ( SOC, SOC, Op_VecA, 20, v20->as_VMReg()->next(2) );
343 reg_def V20_K ( SOC, SOC, Op_VecA, 20, v20->as_VMReg()->next(3) );
344
345 reg_def V21 ( SOC, SOC, Op_VecA, 21, v21->as_VMReg() );
346 reg_def V21_H ( SOC, SOC, Op_VecA, 21, v21->as_VMReg()->next() );
347 reg_def V21_J ( SOC, SOC, Op_VecA, 21, v21->as_VMReg()->next(2) );
348 reg_def V21_K ( SOC, SOC, Op_VecA, 21, v21->as_VMReg()->next(3) );
349
350 reg_def V22 ( SOC, SOC, Op_VecA, 22, v22->as_VMReg() );
351 reg_def V22_H ( SOC, SOC, Op_VecA, 22, v22->as_VMReg()->next() );
352 reg_def V22_J ( SOC, SOC, Op_VecA, 22, v22->as_VMReg()->next(2) );
353 reg_def V22_K ( SOC, SOC, Op_VecA, 22, v22->as_VMReg()->next(3) );
354
355 reg_def V23 ( SOC, SOC, Op_VecA, 23, v23->as_VMReg() );
356 reg_def V23_H ( SOC, SOC, Op_VecA, 23, v23->as_VMReg()->next() );
357 reg_def V23_J ( SOC, SOC, Op_VecA, 23, v23->as_VMReg()->next(2) );
358 reg_def V23_K ( SOC, SOC, Op_VecA, 23, v23->as_VMReg()->next(3) );
359
360 reg_def V24 ( SOC, SOC, Op_VecA, 24, v24->as_VMReg() );
361 reg_def V24_H ( SOC, SOC, Op_VecA, 24, v24->as_VMReg()->next() );
362 reg_def V24_J ( SOC, SOC, Op_VecA, 24, v24->as_VMReg()->next(2) );
363 reg_def V24_K ( SOC, SOC, Op_VecA, 24, v24->as_VMReg()->next(3) );
364
365 reg_def V25 ( SOC, SOC, Op_VecA, 25, v25->as_VMReg() );
366 reg_def V25_H ( SOC, SOC, Op_VecA, 25, v25->as_VMReg()->next() );
367 reg_def V25_J ( SOC, SOC, Op_VecA, 25, v25->as_VMReg()->next(2) );
368 reg_def V25_K ( SOC, SOC, Op_VecA, 25, v25->as_VMReg()->next(3) );
369
370 reg_def V26 ( SOC, SOC, Op_VecA, 26, v26->as_VMReg() );
371 reg_def V26_H ( SOC, SOC, Op_VecA, 26, v26->as_VMReg()->next() );
372 reg_def V26_J ( SOC, SOC, Op_VecA, 26, v26->as_VMReg()->next(2) );
373 reg_def V26_K ( SOC, SOC, Op_VecA, 26, v26->as_VMReg()->next(3) );
374
375 reg_def V27 ( SOC, SOC, Op_VecA, 27, v27->as_VMReg() );
376 reg_def V27_H ( SOC, SOC, Op_VecA, 27, v27->as_VMReg()->next() );
377 reg_def V27_J ( SOC, SOC, Op_VecA, 27, v27->as_VMReg()->next(2) );
378 reg_def V27_K ( SOC, SOC, Op_VecA, 27, v27->as_VMReg()->next(3) );
379
380 reg_def V28 ( SOC, SOC, Op_VecA, 28, v28->as_VMReg() );
381 reg_def V28_H ( SOC, SOC, Op_VecA, 28, v28->as_VMReg()->next() );
382 reg_def V28_J ( SOC, SOC, Op_VecA, 28, v28->as_VMReg()->next(2) );
383 reg_def V28_K ( SOC, SOC, Op_VecA, 28, v28->as_VMReg()->next(3) );
384
385 reg_def V29 ( SOC, SOC, Op_VecA, 29, v29->as_VMReg() );
386 reg_def V29_H ( SOC, SOC, Op_VecA, 29, v29->as_VMReg()->next() );
387 reg_def V29_J ( SOC, SOC, Op_VecA, 29, v29->as_VMReg()->next(2) );
388 reg_def V29_K ( SOC, SOC, Op_VecA, 29, v29->as_VMReg()->next(3) );
389
390 reg_def V30 ( SOC, SOC, Op_VecA, 30, v30->as_VMReg() );
391 reg_def V30_H ( SOC, SOC, Op_VecA, 30, v30->as_VMReg()->next() );
392 reg_def V30_J ( SOC, SOC, Op_VecA, 30, v30->as_VMReg()->next(2) );
393 reg_def V30_K ( SOC, SOC, Op_VecA, 30, v30->as_VMReg()->next(3) );
394
395 reg_def V31 ( SOC, SOC, Op_VecA, 31, v31->as_VMReg() );
396 reg_def V31_H ( SOC, SOC, Op_VecA, 31, v31->as_VMReg()->next() );
397 reg_def V31_J ( SOC, SOC, Op_VecA, 31, v31->as_VMReg()->next(2) );
398 reg_def V31_K ( SOC, SOC, Op_VecA, 31, v31->as_VMReg()->next(3) );
399
400 // ----------------------------
401 // Special Registers
402 // ----------------------------
403
404 // On riscv, the physical flag register is missing, so we use t1 instead,
405 // to bridge the RegFlag semantics in share/opto
406
407 reg_def RFLAGS (SOC, SOC, Op_RegFlags, 6, x6->as_VMReg() );
408
409 // Specify priority of register selection within phases of register
410 // allocation. Highest priority is first. A useful heuristic is to
411 // give registers a low priority when they are required by machine
412 // instructions, like EAX and EDX on I486, and choose no-save registers
413 // before save-on-call, & save-on-call before save-on-entry. Registers
414 // which participate in fixed calling sequences should come last.
415 // Registers which are used as pairs must fall on an even boundary.
416
417 alloc_class chunk0(
418 // volatiles
419 R7, R7_H,
420 R28, R28_H,
421 R29, R29_H,
422 R30, R30_H,
423 R31, R31_H,
424
425 // arg registers
426 R10, R10_H,
427 R11, R11_H,
428 R12, R12_H,
429 R13, R13_H,
430 R14, R14_H,
431 R15, R15_H,
432 R16, R16_H,
433 R17, R17_H,
434
435 // non-volatiles
436 R9, R9_H,
437 R18, R18_H,
438 R19, R19_H,
439 R20, R20_H,
440 R21, R21_H,
441 R22, R22_H,
442 R24, R24_H,
443 R25, R25_H,
444 R26, R26_H,
445
446 // non-allocatable registers
447 R23, R23_H, // java thread
448 R27, R27_H, // heapbase
449 R4, R4_H, // thread
450 R8, R8_H, // fp
451 R0, R0_H, // zero
452 R1, R1_H, // ra
453 R2, R2_H, // sp
454 R3, R3_H, // gp
455 );
456
457 alloc_class chunk1(
458
459 // no save
460 F0, F0_H,
461 F1, F1_H,
462 F2, F2_H,
463 F3, F3_H,
464 F4, F4_H,
465 F5, F5_H,
466 F6, F6_H,
467 F7, F7_H,
468 F28, F28_H,
469 F29, F29_H,
470 F30, F30_H,
471 F31, F31_H,
472
473 // arg registers
474 F10, F10_H,
475 F11, F11_H,
476 F12, F12_H,
477 F13, F13_H,
478 F14, F14_H,
479 F15, F15_H,
480 F16, F16_H,
481 F17, F17_H,
482
483 // non-volatiles
484 F8, F8_H,
485 F9, F9_H,
486 F18, F18_H,
487 F19, F19_H,
488 F20, F20_H,
489 F21, F21_H,
490 F22, F22_H,
491 F23, F23_H,
492 F24, F24_H,
493 F25, F25_H,
494 F26, F26_H,
495 F27, F27_H,
496 );
497
498 alloc_class chunk2(
499 V0, V0_H, V0_J, V0_K,
500 V1, V1_H, V1_J, V1_K,
501 V2, V2_H, V2_J, V2_K,
502 V3, V3_H, V3_J, V3_K,
503 V4, V4_H, V4_J, V4_K,
504 V5, V5_H, V5_J, V5_K,
505 V6, V6_H, V6_J, V6_K,
506 V7, V7_H, V7_J, V7_K,
507 V8, V8_H, V8_J, V8_K,
508 V9, V9_H, V9_J, V9_K,
509 V10, V10_H, V10_J, V10_K,
510 V11, V11_H, V11_J, V11_K,
511 V12, V12_H, V12_J, V12_K,
512 V13, V13_H, V13_J, V13_K,
513 V14, V14_H, V14_J, V14_K,
514 V15, V15_H, V15_J, V15_K,
515 V16, V16_H, V16_J, V16_K,
516 V17, V17_H, V17_J, V17_K,
517 V18, V18_H, V18_J, V18_K,
518 V19, V19_H, V19_J, V19_K,
519 V20, V20_H, V20_J, V20_K,
520 V21, V21_H, V21_J, V21_K,
521 V22, V22_H, V22_J, V22_K,
522 V23, V23_H, V23_J, V23_K,
523 V24, V24_H, V24_J, V24_K,
524 V25, V25_H, V25_J, V25_K,
525 V26, V26_H, V26_J, V26_K,
526 V27, V27_H, V27_J, V27_K,
527 V28, V28_H, V28_J, V28_K,
528 V29, V29_H, V29_J, V29_K,
529 V30, V30_H, V30_J, V30_K,
530 V31, V31_H, V31_J, V31_K,
531 );
532
533 alloc_class chunk3(RFLAGS);
534
535 //----------Architecture Description Register Classes--------------------------
536 // Several register classes are automatically defined based upon information in
537 // this architecture description.
538 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
539 // 2) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
540 //
541
542 // Class for all 32 bit general purpose registers
543 reg_class all_reg32(
544 R0,
545 R1,
546 R2,
547 R3,
548 R4,
549 R7,
550 R8,
551 R9,
552 R10,
553 R11,
554 R12,
555 R13,
556 R14,
557 R15,
558 R16,
559 R17,
560 R18,
561 R19,
562 R20,
563 R21,
564 R22,
565 R23,
566 R24,
567 R25,
568 R26,
569 R27,
570 R28,
571 R29,
572 R30,
573 R31
574 );
575
576 // Class for any 32 bit integer registers (excluding zr)
577 reg_class any_reg32 %{
578 return _ANY_REG32_mask;
579 %}
580
581 // Singleton class for R10 int register
582 reg_class int_r10_reg(R10);
583
584 // Singleton class for R12 int register
585 reg_class int_r12_reg(R12);
586
587 // Singleton class for R13 int register
588 reg_class int_r13_reg(R13);
589
590 // Singleton class for R14 int register
591 reg_class int_r14_reg(R14);
592
593 // Class for all long integer registers
594 reg_class all_reg(
595 R0, R0_H,
596 R1, R1_H,
597 R2, R2_H,
598 R3, R3_H,
599 R4, R4_H,
600 R7, R7_H,
601 R8, R8_H,
602 R9, R9_H,
603 R10, R10_H,
604 R11, R11_H,
605 R12, R12_H,
606 R13, R13_H,
607 R14, R14_H,
608 R15, R15_H,
609 R16, R16_H,
610 R17, R17_H,
611 R18, R18_H,
612 R19, R19_H,
613 R20, R20_H,
614 R21, R21_H,
615 R22, R22_H,
616 R23, R23_H,
617 R24, R24_H,
618 R25, R25_H,
619 R26, R26_H,
620 R27, R27_H,
621 R28, R28_H,
622 R29, R29_H,
623 R30, R30_H,
624 R31, R31_H
625 );
626
627 // Class for all long integer registers (excluding zr)
628 reg_class any_reg %{
629 return _ANY_REG_mask;
630 %}
631
632 // Class for non-allocatable 32 bit registers
633 reg_class non_allocatable_reg32(
634 R0, // zr
635 R1, // ra
636 R2, // sp
637 R3, // gp
638 R4, // tp
639 R23 // java thread
640 );
641
642 // Class for non-allocatable 64 bit registers
643 reg_class non_allocatable_reg(
644 R0, R0_H, // zr
645 R1, R1_H, // ra
646 R2, R2_H, // sp
647 R3, R3_H, // gp
648 R4, R4_H, // tp
649 R23, R23_H // java thread
650 );
651
652 // Class for all non-special integer registers
653 reg_class no_special_reg32 %{
654 return _NO_SPECIAL_REG32_mask;
655 %}
656
657 // Class for all non-special long integer registers
658 reg_class no_special_reg %{
659 return _NO_SPECIAL_REG_mask;
660 %}
661
662 reg_class ptr_reg %{
663 return _PTR_REG_mask;
664 %}
665
666 // Class for all non_special pointer registers
667 reg_class no_special_ptr_reg %{
668 return _NO_SPECIAL_PTR_REG_mask;
669 %}
670
671 // Class for all non_special pointer registers (excluding fp)
672 reg_class no_special_no_fp_ptr_reg %{
673 return _NO_SPECIAL_NO_FP_PTR_REG_mask;
674 %}
675
676 // Class for 64 bit register r10
677 reg_class r10_reg(
678 R10, R10_H
679 );
680
681 // Class for 64 bit register r11
682 reg_class r11_reg(
683 R11, R11_H
684 );
685
686 // Class for 64 bit register r12
687 reg_class r12_reg(
688 R12, R12_H
689 );
690
691 // Class for 64 bit register r13
692 reg_class r13_reg(
693 R13, R13_H
694 );
695
696 // Class for 64 bit register r14
697 reg_class r14_reg(
698 R14, R14_H
699 );
700
701 // Class for 64 bit register r15
702 reg_class r15_reg(
703 R15, R15_H
704 );
705
706 // Class for 64 bit register r16
707 reg_class r16_reg(
708 R16, R16_H
709 );
710
711 // Class for method register
712 reg_class method_reg(
713 R31, R31_H
714 );
715
716 // Class for java thread register
717 reg_class java_thread_reg(
718 R23, R23_H
719 );
720
721 reg_class r28_reg(
722 R28, R28_H
723 );
724
725 reg_class r29_reg(
726 R29, R29_H
727 );
728
729 reg_class r30_reg(
730 R30, R30_H
731 );
732
733 reg_class r31_reg(
734 R31, R31_H
735 );
736
737 // Class for zero registesr
738 reg_class zr_reg(
739 R0, R0_H
740 );
741
742 // Class for thread register
743 reg_class thread_reg(
744 R4, R4_H
745 );
746
747 // Class for frame pointer register
748 reg_class fp_reg(
749 R8, R8_H
750 );
751
752 // Class for link register
753 reg_class ra_reg(
754 R1, R1_H
755 );
756
757 // Class for long sp register
758 reg_class sp_reg(
759 R2, R2_H
760 );
761
762 // Class for all float registers
763 reg_class float_reg(
764 F0,
765 F1,
766 F2,
767 F3,
768 F4,
769 F5,
770 F6,
771 F7,
772 F8,
773 F9,
774 F10,
775 F11,
776 F12,
777 F13,
778 F14,
779 F15,
780 F16,
781 F17,
782 F18,
783 F19,
784 F20,
785 F21,
786 F22,
787 F23,
788 F24,
789 F25,
790 F26,
791 F27,
792 F28,
793 F29,
794 F30,
795 F31
796 );
797
798 // Double precision float registers have virtual `high halves' that
799 // are needed by the allocator.
800 // Class for all double registers
801 reg_class double_reg(
802 F0, F0_H,
803 F1, F1_H,
804 F2, F2_H,
805 F3, F3_H,
806 F4, F4_H,
807 F5, F5_H,
808 F6, F6_H,
809 F7, F7_H,
810 F8, F8_H,
811 F9, F9_H,
812 F10, F10_H,
813 F11, F11_H,
814 F12, F12_H,
815 F13, F13_H,
816 F14, F14_H,
817 F15, F15_H,
818 F16, F16_H,
819 F17, F17_H,
820 F18, F18_H,
821 F19, F19_H,
822 F20, F20_H,
823 F21, F21_H,
824 F22, F22_H,
825 F23, F23_H,
826 F24, F24_H,
827 F25, F25_H,
828 F26, F26_H,
829 F27, F27_H,
830 F28, F28_H,
831 F29, F29_H,
832 F30, F30_H,
833 F31, F31_H
834 );
835
836 // Class for RVV vector registers
837 // Note: v0, v30 and v31 are used as mask registers.
838 reg_class vectora_reg(
839 V1, V1_H, V1_J, V1_K,
840 V2, V2_H, V2_J, V2_K,
841 V3, V3_H, V3_J, V3_K,
842 V4, V4_H, V4_J, V4_K,
843 V5, V5_H, V5_J, V5_K,
844 V6, V6_H, V6_J, V6_K,
845 V7, V7_H, V7_J, V7_K,
846 V8, V8_H, V8_J, V8_K,
847 V9, V9_H, V9_J, V9_K,
848 V10, V10_H, V10_J, V10_K,
849 V11, V11_H, V11_J, V11_K,
850 V12, V12_H, V12_J, V12_K,
851 V13, V13_H, V13_J, V13_K,
852 V14, V14_H, V14_J, V14_K,
853 V15, V15_H, V15_J, V15_K,
854 V16, V16_H, V16_J, V16_K,
855 V17, V17_H, V17_J, V17_K,
856 V18, V18_H, V18_J, V18_K,
857 V19, V19_H, V19_J, V19_K,
858 V20, V20_H, V20_J, V20_K,
859 V21, V21_H, V21_J, V21_K,
860 V22, V22_H, V22_J, V22_K,
861 V23, V23_H, V23_J, V23_K,
862 V24, V24_H, V24_J, V24_K,
863 V25, V25_H, V25_J, V25_K,
864 V26, V26_H, V26_J, V26_K,
865 V27, V27_H, V27_J, V27_K,
866 V28, V28_H, V28_J, V28_K,
867 V29, V29_H, V29_J, V29_K
868 );
869
870 // Class for 64 bit register f0
871 reg_class f0_reg(
872 F0, F0_H
873 );
874
875 // Class for 64 bit register f1
876 reg_class f1_reg(
877 F1, F1_H
878 );
879
880 // Class for 64 bit register f2
881 reg_class f2_reg(
882 F2, F2_H
883 );
884
885 // Class for 64 bit register f3
886 reg_class f3_reg(
887 F3, F3_H
888 );
889
890 // class for vector register v1
891 reg_class v1_reg(
892 V1, V1_H, V1_J, V1_K
893 );
894
895 // class for vector register v2
896 reg_class v2_reg(
897 V2, V2_H, V2_J, V2_K
898 );
899
900 // class for vector register v3
901 reg_class v3_reg(
902 V3, V3_H, V3_J, V3_K
903 );
904
905 // class for vector register v4
906 reg_class v4_reg(
907 V4, V4_H, V4_J, V4_K
908 );
909
910 // class for vector register v5
911 reg_class v5_reg(
912 V5, V5_H, V5_J, V5_K
913 );
914
915 // class for vector register v6
916 reg_class v6_reg(
917 V6, V6_H, V6_J, V6_K
918 );
919
920 // class for vector register v7
921 reg_class v7_reg(
922 V7, V7_H, V7_J, V7_K
923 );
924
925 // class for vector register v8
926 reg_class v8_reg(
927 V8, V8_H, V8_J, V8_K
928 );
929
930 // class for vector register v9
931 reg_class v9_reg(
932 V9, V9_H, V9_J, V9_K
933 );
934
935 // class for vector register v10
936 reg_class v10_reg(
937 V10, V10_H, V10_J, V10_K
938 );
939
940 // class for vector register v11
941 reg_class v11_reg(
942 V11, V11_H, V11_J, V11_K
943 );
944
945 // class for condition codes
946 reg_class reg_flags(RFLAGS);
947
948 // Class for RVV v0 mask register
949 // https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#53-vector-masking
950 // The mask value used to control execution of a masked vector
951 // instruction is always supplied by vector register v0.
952 reg_class vmask_reg_v0 (
953 V0
954 );
955
956 // Class for RVV mask registers
957 // We need two more vmask registers to do the vector mask logical ops,
958 // so define v30, v31 as mask register too.
959 reg_class vmask_reg (
960 V0,
961 V30,
962 V31
963 );
964 %}
965
966 //----------DEFINITION BLOCK---------------------------------------------------
967 // Define name --> value mappings to inform the ADLC of an integer valued name
968 // Current support includes integer values in the range [0, 0x7FFFFFFF]
969 // Format:
970 // int_def <name> ( <int_value>, <expression>);
971 // Generated Code in ad_<arch>.hpp
972 // #define <name> (<expression>)
973 // // value == <int_value>
974 // Generated code in ad_<arch>.cpp adlc_verification()
975 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
976 //
977
978 // we follow the ppc-aix port in using a simple cost model which ranks
979 // register operations as cheap, memory ops as more expensive and
980 // branches as most expensive. the first two have a low as well as a
981 // normal cost. huge cost appears to be a way of saying don't do
982 // something
983
984 definitions %{
985 // The default cost (of a register move instruction).
986 int_def DEFAULT_COST ( 100, 100);
987 int_def ALU_COST ( 100, 1 * DEFAULT_COST); // unknown, const, arith, shift, slt,
988 // multi, auipc, nop, logical, move
989 int_def LOAD_COST ( 300, 3 * DEFAULT_COST); // load, fpload
990 int_def STORE_COST ( 100, 1 * DEFAULT_COST); // store, fpstore
991 int_def XFER_COST ( 300, 3 * DEFAULT_COST); // mfc, mtc, fcvt, fmove, fcmp
992 int_def FMVX_COST ( 100, 1 * DEFAULT_COST); // shuffles with no conversion
993 int_def BRANCH_COST ( 200, 2 * DEFAULT_COST); // branch, jmp, call
994 int_def IMUL_COST ( 1000, 10 * DEFAULT_COST); // imul
995 int_def IDIVSI_COST ( 3400, 34 * DEFAULT_COST); // idivsi
996 int_def IDIVDI_COST ( 6600, 66 * DEFAULT_COST); // idivdi
997 int_def FMUL_SINGLE_COST ( 500, 5 * DEFAULT_COST); // fmul, fmadd
998 int_def FMUL_DOUBLE_COST ( 700, 7 * DEFAULT_COST); // fmul, fmadd
999 int_def FDIV_COST ( 2000, 20 * DEFAULT_COST); // fdiv
1000 int_def FSQRT_COST ( 2500, 25 * DEFAULT_COST); // fsqrt
1001 int_def VOLATILE_REF_COST ( 1000, 10 * DEFAULT_COST);
1002 int_def CACHE_MISS_COST ( 2000, 20 * DEFAULT_COST); // typicall cache miss penalty
1003 %}
1004
1005
1006
1007 //----------SOURCE BLOCK-------------------------------------------------------
1008 // This is a block of C++ code which provides values, functions, and
1009 // definitions necessary in the rest of the architecture description
1010
1011 source_hpp %{
1012
1013 #include "asm/macroAssembler.hpp"
1014 #include "gc/shared/barrierSetAssembler.hpp"
1015 #include "gc/shared/cardTable.hpp"
1016 #include "gc/shared/cardTableBarrierSet.hpp"
1017 #include "gc/shared/collectedHeap.hpp"
1018 #include "opto/addnode.hpp"
1019 #include "opto/convertnode.hpp"
1020 #include "runtime/objectMonitor.hpp"
1021
1022 extern RegMask _ANY_REG32_mask;
1023 extern RegMask _ANY_REG_mask;
1024 extern RegMask _PTR_REG_mask;
1025 extern RegMask _NO_SPECIAL_REG32_mask;
1026 extern RegMask _NO_SPECIAL_REG_mask;
1027 extern RegMask _NO_SPECIAL_PTR_REG_mask;
1028 extern RegMask _NO_SPECIAL_NO_FP_PTR_REG_mask;
1029
1030 class CallStubImpl {
1031
1032 //--------------------------------------------------------------
1033 //---< Used for optimization in Compile::shorten_branches >---
1034 //--------------------------------------------------------------
1035
1036 public:
1037 // Size of call trampoline stub.
1038 static uint size_call_trampoline() {
1039 return 0; // no call trampolines on this platform
1040 }
1041
1042 // number of relocations needed by a call trampoline stub
1043 static uint reloc_call_trampoline() {
1044 return 0; // no call trampolines on this platform
1045 }
1046 };
1047
1048 class HandlerImpl {
1049
1050 public:
1051
1052 static int emit_exception_handler(C2_MacroAssembler *masm);
1053 static int emit_deopt_handler(C2_MacroAssembler* masm);
1054
1055 static uint size_exception_handler() {
1056 return MacroAssembler::far_branch_size();
1057 }
1058
1059 static uint size_deopt_handler() {
1060 // count auipc + far branch
1061 return NativeInstruction::instruction_size + MacroAssembler::far_branch_size();
1062 }
1063 };
1064
1065 class Node::PD {
1066 public:
1067 enum NodeFlags {
1068 _last_flag = Node::_last_flag
1069 };
1070 };
1071
1072 bool is_CAS(int opcode, bool maybe_volatile);
1073
1074 // predicate controlling translation of CompareAndSwapX
1075 bool needs_acquiring_load_reserved(const Node *load);
1076
1077 // predicate controlling addressing modes
1078 bool size_fits_all_mem_uses(AddPNode* addp, int shift);
1079 %}
1080
1081 source %{
1082
1083 // Derived RegMask with conditionally allocatable registers
1084
1085 RegMask _ANY_REG32_mask;
1086 RegMask _ANY_REG_mask;
1087 RegMask _PTR_REG_mask;
1088 RegMask _NO_SPECIAL_REG32_mask;
1089 RegMask _NO_SPECIAL_REG_mask;
1090 RegMask _NO_SPECIAL_PTR_REG_mask;
1091 RegMask _NO_SPECIAL_NO_FP_PTR_REG_mask;
1092
1093 void reg_mask_init() {
1094
1095 _ANY_REG32_mask = _ALL_REG32_mask;
1096 _ANY_REG32_mask.Remove(OptoReg::as_OptoReg(x0->as_VMReg()));
1097
1098 _ANY_REG_mask = _ALL_REG_mask;
1099 _ANY_REG_mask.SUBTRACT(_ZR_REG_mask);
1100
1101 _PTR_REG_mask = _ALL_REG_mask;
1102 _PTR_REG_mask.SUBTRACT(_ZR_REG_mask);
1103
1104 _NO_SPECIAL_REG32_mask = _ALL_REG32_mask;
1105 _NO_SPECIAL_REG32_mask.SUBTRACT(_NON_ALLOCATABLE_REG32_mask);
1106
1107 _NO_SPECIAL_REG_mask = _ALL_REG_mask;
1108 _NO_SPECIAL_REG_mask.SUBTRACT(_NON_ALLOCATABLE_REG_mask);
1109
1110 _NO_SPECIAL_PTR_REG_mask = _ALL_REG_mask;
1111 _NO_SPECIAL_PTR_REG_mask.SUBTRACT(_NON_ALLOCATABLE_REG_mask);
1112
1113 // x27 is not allocatable when compressed oops is on
1114 if (UseCompressedOops) {
1115 _NO_SPECIAL_REG32_mask.Remove(OptoReg::as_OptoReg(x27->as_VMReg()));
1116 _NO_SPECIAL_REG_mask.Remove(OptoReg::as_OptoReg(x27->as_VMReg()));
1117 _NO_SPECIAL_PTR_REG_mask.Remove(OptoReg::as_OptoReg(x27->as_VMReg()));
1118 }
1119
1120 // x8 is not allocatable when PreserveFramePointer is on
1121 if (PreserveFramePointer) {
1122 _NO_SPECIAL_REG32_mask.Remove(OptoReg::as_OptoReg(x8->as_VMReg()));
1123 _NO_SPECIAL_REG_mask.Remove(OptoReg::as_OptoReg(x8->as_VMReg()));
1124 _NO_SPECIAL_PTR_REG_mask.Remove(OptoReg::as_OptoReg(x8->as_VMReg()));
1125 }
1126
1127 _NO_SPECIAL_NO_FP_PTR_REG_mask = _NO_SPECIAL_PTR_REG_mask;
1128 _NO_SPECIAL_NO_FP_PTR_REG_mask.Remove(OptoReg::as_OptoReg(x8->as_VMReg()));
1129 }
1130
1131 void PhaseOutput::pd_perform_mach_node_analysis() {
1132 }
1133
1134 int MachNode::pd_alignment_required() const {
1135 return 1;
1136 }
1137
1138 int MachNode::compute_padding(int current_offset) const {
1139 return 0;
1140 }
1141
1142 // is_CAS(int opcode, bool maybe_volatile)
1143 //
1144 // return true if opcode is one of the possible CompareAndSwapX
1145 // values otherwise false.
1146 bool is_CAS(int opcode, bool maybe_volatile)
1147 {
1148 switch (opcode) {
1149 // We handle these
1150 case Op_CompareAndSwapI:
1151 case Op_CompareAndSwapL:
1152 case Op_CompareAndSwapP:
1153 case Op_CompareAndSwapN:
1154 case Op_ShenandoahCompareAndSwapP:
1155 case Op_ShenandoahCompareAndSwapN:
1156 case Op_CompareAndSwapB:
1157 case Op_CompareAndSwapS:
1158 case Op_GetAndSetI:
1159 case Op_GetAndSetL:
1160 case Op_GetAndSetP:
1161 case Op_GetAndSetN:
1162 case Op_GetAndAddI:
1163 case Op_GetAndAddL:
1164 return true;
1165 case Op_CompareAndExchangeI:
1166 case Op_CompareAndExchangeN:
1167 case Op_CompareAndExchangeB:
1168 case Op_CompareAndExchangeS:
1169 case Op_CompareAndExchangeL:
1170 case Op_CompareAndExchangeP:
1171 case Op_WeakCompareAndSwapB:
1172 case Op_WeakCompareAndSwapS:
1173 case Op_WeakCompareAndSwapI:
1174 case Op_WeakCompareAndSwapL:
1175 case Op_WeakCompareAndSwapP:
1176 case Op_WeakCompareAndSwapN:
1177 case Op_ShenandoahWeakCompareAndSwapP:
1178 case Op_ShenandoahWeakCompareAndSwapN:
1179 case Op_ShenandoahCompareAndExchangeP:
1180 case Op_ShenandoahCompareAndExchangeN:
1181 return maybe_volatile;
1182 default:
1183 return false;
1184 }
1185 }
1186
1187 // predicate controlling translation of CAS
1188 //
1189 // returns true if CAS needs to use an acquiring load otherwise false
1190 bool needs_acquiring_load_reserved(const Node *n)
1191 {
1192 assert(n != nullptr && is_CAS(n->Opcode(), true), "expecting a compare and swap");
1193
1194 LoadStoreNode* ldst = n->as_LoadStore();
1195 if (n != nullptr && is_CAS(n->Opcode(), false)) {
1196 assert(ldst != nullptr && ldst->trailing_membar() != nullptr, "expected trailing membar");
1197 } else {
1198 return ldst != nullptr && ldst->trailing_membar() != nullptr;
1199 }
1200 // so we can just return true here
1201 return true;
1202 }
1203 #define __ masm->
1204
1205 // advance declarations for helper functions to convert register
1206 // indices to register objects
1207
1208 // the ad file has to provide implementations of certain methods
1209 // expected by the generic code
1210 //
1211 // REQUIRED FUNCTIONALITY
1212
1213 //=============================================================================
1214
1215 // !!!!! Special hack to get all types of calls to specify the byte offset
1216 // from the start of the call to the point where the return address
1217 // will point.
1218
1219 int MachCallStaticJavaNode::ret_addr_offset()
1220 {
1221 return 3 * NativeInstruction::instruction_size; // auipc + ld + jalr
1222 }
1223
1224 int MachCallDynamicJavaNode::ret_addr_offset()
1225 {
1226 return NativeMovConstReg::movptr2_instruction_size + (3 * NativeInstruction::instruction_size); // movptr2, auipc + ld + jal
1227 }
1228
1229 int MachCallRuntimeNode::ret_addr_offset() {
1230 // For address inside the code cache the call will be:
1231 // auipc + jalr
1232 // For real runtime callouts it will be 8 instructions
1233 // see riscv_enc_java_to_runtime
1234 // la(t0, retaddr) -> auipc + addi
1235 // sd(t0, Address(xthread, JavaThread::last_Java_pc_offset())) -> sd
1236 // movptr(t1, addr, offset, t0) -> lui + lui + slli + add
1237 // jalr(t1, offset) -> jalr
1238 if (CodeCache::contains(_entry_point)) {
1239 return 2 * NativeInstruction::instruction_size;
1240 } else {
1241 return 8 * NativeInstruction::instruction_size;
1242 }
1243 }
1244
1245 //
1246 // Compute padding required for nodes which need alignment
1247 //
1248
1249 // With RVC a call instruction may get 2-byte aligned.
1250 // The address of the call instruction needs to be 4-byte aligned to
1251 // ensure that it does not span a cache line so that it can be patched.
1252 int CallStaticJavaDirectNode::compute_padding(int current_offset) const
1253 {
1254 // to make sure the address of jal 4-byte aligned.
1255 return align_up(current_offset, alignment_required()) - current_offset;
1256 }
1257
1258 // With RVC a call instruction may get 2-byte aligned.
1259 // The address of the call instruction needs to be 4-byte aligned to
1260 // ensure that it does not span a cache line so that it can be patched.
1261 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const
1262 {
1263 // skip the movptr2 in MacroAssembler::ic_call():
1264 // lui, lui, slli, add, addi
1265 // Though movptr2() has already 4-byte aligned with or without RVC,
1266 // We need to prevent from further changes by explicitly calculating the size.
1267 current_offset += NativeMovConstReg::movptr2_instruction_size;
1268 // to make sure the address of jal 4-byte aligned.
1269 return align_up(current_offset, alignment_required()) - current_offset;
1270 }
1271
1272 //=============================================================================
1273
1274 #ifndef PRODUCT
1275 void MachBreakpointNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1276 assert_cond(st != nullptr);
1277 st->print("BREAKPOINT");
1278 }
1279 #endif
1280
1281 void MachBreakpointNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
1282 __ ebreak();
1283 }
1284
1285 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
1286 return MachNode::size(ra_);
1287 }
1288
1289 //=============================================================================
1290
1291 #ifndef PRODUCT
1292 void MachNopNode::format(PhaseRegAlloc*, outputStream* st) const {
1293 st->print("nop \t# %d bytes pad for loops and calls", _count);
1294 }
1295 #endif
1296
1297 void MachNopNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc*) const {
1298 Assembler::CompressibleRegion cr(masm); // nops shall be 2-byte under RVC for alignment purposes.
1299 for (int i = 0; i < _count; i++) {
1300 __ nop();
1301 }
1302 }
1303
1304 uint MachNopNode::size(PhaseRegAlloc*) const {
1305 return _count * (UseRVC ? NativeInstruction::compressed_instruction_size : NativeInstruction::instruction_size);
1306 }
1307
1308 //=============================================================================
1309 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;
1310
1311 int ConstantTable::calculate_table_base_offset() const {
1312 return 0; // absolute addressing, no offset
1313 }
1314
1315 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
1316 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
1317 ShouldNotReachHere();
1318 }
1319
1320 void MachConstantBaseNode::emit(C2_MacroAssembler* masm, PhaseRegAlloc* ra_) const {
1321 // Empty encoding
1322 }
1323
1324 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
1325 return 0;
1326 }
1327
1328 #ifndef PRODUCT
1329 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1330 assert_cond(st != nullptr);
1331 st->print("-- \t// MachConstantBaseNode (empty encoding)");
1332 }
1333 #endif
1334
1335 #ifndef PRODUCT
1336 void MachPrologNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1337 assert_cond(st != nullptr && ra_ != nullptr);
1338 Compile* C = ra_->C;
1339
1340 int framesize = C->output()->frame_slots() << LogBytesPerInt;
1341
1342 if (C->output()->need_stack_bang(framesize)) {
1343 st->print("# stack bang size=%d\n\t", framesize);
1344 }
1345
1346 st->print("sd fp, [sp, #%d]\n\t", - 2 * wordSize);
1347 st->print("sd ra, [sp, #%d]\n\t", - wordSize);
1348 if (PreserveFramePointer) { st->print("sub fp, sp, #%d\n\t", 2 * wordSize); }
1349 st->print("sub sp, sp, #%d\n\t", framesize);
1350
1351 if (C->stub_function() == nullptr) {
1352 st->print("ld t0, [guard]\n\t");
1353 st->print("membar LoadLoad\n\t");
1354 st->print("ld t1, [xthread, #thread_disarmed_guard_value_offset]\n\t");
1355 st->print("beq t0, t1, skip\n\t");
1356 st->print("jalr #nmethod_entry_barrier_stub\n\t");
1357 st->print("j skip\n\t");
1358 st->print("guard: int\n\t");
1359 st->print("skip:\n\t");
1360 }
1361 }
1362 #endif
1363
1364 void MachPrologNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
1365 assert_cond(ra_ != nullptr);
1366 Compile* C = ra_->C;
1367
1368 // n.b. frame size includes space for return pc and fp
1369 const int framesize = C->output()->frame_size_in_bytes();
1370
1371 // insert a nop at the start of the prolog so we can patch in a
1372 // branch if we need to invalidate the method later
1373 {
1374 Assembler::IncompressibleRegion ir(masm); // keep the nop as 4 bytes for patching.
1375 MacroAssembler::assert_alignment(__ pc());
1376 __ nop(); // 4 bytes
1377 }
1378
1379 assert_cond(C != nullptr);
1380
1381 if (C->clinit_barrier_on_entry()) {
1382 assert(!C->method()->holder()->is_not_initialized(), "initialization should have been started");
1383
1384 Label L_skip_barrier;
1385
1386 __ mov_metadata(t1, C->method()->holder()->constant_encoding());
1387 __ clinit_barrier(t1, t0, &L_skip_barrier);
1388 __ far_jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub()));
1389 __ bind(L_skip_barrier);
1390 }
1391
1392 int bangsize = C->output()->bang_size_in_bytes();
1393 if (C->output()->need_stack_bang(bangsize)) {
1394 __ generate_stack_overflow_check(bangsize);
1395 }
1396
1397 __ build_frame(framesize);
1398
1399 if (C->stub_function() == nullptr) {
1400 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
1401 // Dummy labels for just measuring the code size
1402 Label dummy_slow_path;
1403 Label dummy_continuation;
1404 Label dummy_guard;
1405 Label* slow_path = &dummy_slow_path;
1406 Label* continuation = &dummy_continuation;
1407 Label* guard = &dummy_guard;
1408 if (!Compile::current()->output()->in_scratch_emit_size()) {
1409 // Use real labels from actual stub when not emitting code for purpose of measuring its size
1410 C2EntryBarrierStub* stub = new (Compile::current()->comp_arena()) C2EntryBarrierStub();
1411 Compile::current()->output()->add_stub(stub);
1412 slow_path = &stub->entry();
1413 continuation = &stub->continuation();
1414 guard = &stub->guard();
1415 }
1416 // In the C2 code, we move the non-hot part of nmethod entry barriers out-of-line to a stub.
1417 bs->nmethod_entry_barrier(masm, slow_path, continuation, guard);
1418 }
1419
1420 if (VerifyStackAtCalls) {
1421 Unimplemented();
1422 }
1423
1424 C->output()->set_frame_complete(__ offset());
1425
1426 if (C->has_mach_constant_base_node()) {
1427 // NOTE: We set the table base offset here because users might be
1428 // emitted before MachConstantBaseNode.
1429 ConstantTable& constant_table = C->output()->constant_table();
1430 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
1431 }
1432 }
1433
1434 uint MachPrologNode::size(PhaseRegAlloc* ra_) const
1435 {
1436 assert_cond(ra_ != nullptr);
1437 return MachNode::size(ra_); // too many variables; just compute it
1438 // the hard way
1439 }
1440
1441 int MachPrologNode::reloc() const
1442 {
1443 return 0;
1444 }
1445
1446 //=============================================================================
1447
1448 #ifndef PRODUCT
1449 void MachEpilogNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1450 assert_cond(st != nullptr && ra_ != nullptr);
1451 Compile* C = ra_->C;
1452 assert_cond(C != nullptr);
1453 int framesize = C->output()->frame_size_in_bytes();
1454
1455 st->print("# pop frame %d\n\t", framesize);
1456
1457 if (framesize == 0) {
1458 st->print("ld ra, [sp,#%d]\n\t", (2 * wordSize));
1459 st->print("ld fp, [sp,#%d]\n\t", (3 * wordSize));
1460 st->print("add sp, sp, #%d\n\t", (2 * wordSize));
1461 } else {
1462 st->print("add sp, sp, #%d\n\t", framesize);
1463 st->print("ld ra, [sp,#%d]\n\t", - 2 * wordSize);
1464 st->print("ld fp, [sp,#%d]\n\t", - wordSize);
1465 }
1466
1467 if (do_polling() && C->is_method_compilation()) {
1468 st->print("# test polling word\n\t");
1469 st->print("ld t0, [xthread,#%d]\n\t", in_bytes(JavaThread::polling_word_offset()));
1470 st->print("bgtu sp, t0, #slow_path");
1471 }
1472 }
1473 #endif
1474
1475 void MachEpilogNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
1476 assert_cond(ra_ != nullptr);
1477 Compile* C = ra_->C;
1478 assert_cond(C != nullptr);
1479 int framesize = C->output()->frame_size_in_bytes();
1480
1481 __ remove_frame(framesize);
1482
1483 if (StackReservedPages > 0 && C->has_reserved_stack_access()) {
1484 __ reserved_stack_check();
1485 }
1486
1487 if (do_polling() && C->is_method_compilation()) {
1488 Label dummy_label;
1489 Label* code_stub = &dummy_label;
1490 if (!C->output()->in_scratch_emit_size()) {
1491 C2SafepointPollStub* stub = new (C->comp_arena()) C2SafepointPollStub(__ offset());
1492 C->output()->add_stub(stub);
1493 code_stub = &stub->entry();
1494 }
1495 __ relocate(relocInfo::poll_return_type);
1496 __ safepoint_poll(*code_stub, true /* at_return */, false /* acquire */, true /* in_nmethod */);
1497 }
1498 }
1499
1500 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
1501 assert_cond(ra_ != nullptr);
1502 // Variable size. Determine dynamically.
1503 return MachNode::size(ra_);
1504 }
1505
1506 int MachEpilogNode::reloc() const {
1507 // Return number of relocatable values contained in this instruction.
1508 return 1; // 1 for polling page.
1509 }
1510 const Pipeline * MachEpilogNode::pipeline() const {
1511 return MachNode::pipeline_class();
1512 }
1513
1514 //=============================================================================
1515
1516 // Figure out which register class each belongs in: rc_int, rc_float or
1517 // rc_stack.
1518 enum RC { rc_bad, rc_int, rc_float, rc_vector, rc_stack };
1519
1520 static enum RC rc_class(OptoReg::Name reg) {
1521
1522 if (reg == OptoReg::Bad) {
1523 return rc_bad;
1524 }
1525
1526 // we have 30 int registers * 2 halves
1527 // (t0 and t1 are omitted)
1528 int slots_of_int_registers = Register::max_slots_per_register * (Register::number_of_registers - 2);
1529 if (reg < slots_of_int_registers) {
1530 return rc_int;
1531 }
1532
1533 // we have 32 float register * 2 halves
1534 int slots_of_float_registers = FloatRegister::max_slots_per_register * FloatRegister::number_of_registers;
1535 if (reg < slots_of_int_registers + slots_of_float_registers) {
1536 return rc_float;
1537 }
1538
1539 // we have 32 vector register * 4 halves
1540 int slots_of_vector_registers = VectorRegister::max_slots_per_register * VectorRegister::number_of_registers;
1541 if (reg < slots_of_int_registers + slots_of_float_registers + slots_of_vector_registers) {
1542 return rc_vector;
1543 }
1544
1545 // Between vector regs & stack is the flags regs.
1546 assert(OptoReg::is_stack(reg), "blow up if spilling flags");
1547
1548 return rc_stack;
1549 }
1550
1551 uint MachSpillCopyNode::implementation(C2_MacroAssembler *masm, PhaseRegAlloc *ra_, bool do_size, outputStream *st) const {
1552 assert_cond(ra_ != nullptr);
1553 Compile* C = ra_->C;
1554
1555 // Get registers to move.
1556 OptoReg::Name src_hi = ra_->get_reg_second(in(1));
1557 OptoReg::Name src_lo = ra_->get_reg_first(in(1));
1558 OptoReg::Name dst_hi = ra_->get_reg_second(this);
1559 OptoReg::Name dst_lo = ra_->get_reg_first(this);
1560
1561 enum RC src_hi_rc = rc_class(src_hi);
1562 enum RC src_lo_rc = rc_class(src_lo);
1563 enum RC dst_hi_rc = rc_class(dst_hi);
1564 enum RC dst_lo_rc = rc_class(dst_lo);
1565
1566 assert(src_lo != OptoReg::Bad && dst_lo != OptoReg::Bad, "must move at least 1 register");
1567
1568 if (src_hi != OptoReg::Bad && !bottom_type()->isa_vectmask()) {
1569 assert((src_lo & 1) == 0 && src_lo + 1 == src_hi &&
1570 (dst_lo & 1) == 0 && dst_lo + 1 == dst_hi,
1571 "expected aligned-adjacent pairs");
1572 }
1573
1574 if (src_lo == dst_lo && src_hi == dst_hi) {
1575 return 0; // Self copy, no move.
1576 }
1577
1578 bool is64 = (src_lo & 1) == 0 && src_lo + 1 == src_hi &&
1579 (dst_lo & 1) == 0 && dst_lo + 1 == dst_hi;
1580 int src_offset = ra_->reg2offset(src_lo);
1581 int dst_offset = ra_->reg2offset(dst_lo);
1582
1583 if (bottom_type()->isa_vect() != nullptr) {
1584 uint ireg = ideal_reg();
1585 if (ireg == Op_VecA && masm) {
1586 int vector_reg_size_in_bytes = Matcher::scalable_vector_reg_size(T_BYTE);
1587 if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
1588 // stack to stack
1589 __ spill_copy_vector_stack_to_stack(src_offset, dst_offset,
1590 vector_reg_size_in_bytes);
1591 } else if (src_lo_rc == rc_vector && dst_lo_rc == rc_stack) {
1592 // vpr to stack
1593 __ spill(as_VectorRegister(Matcher::_regEncode[src_lo]), ra_->reg2offset(dst_lo));
1594 } else if (src_lo_rc == rc_stack && dst_lo_rc == rc_vector) {
1595 // stack to vpr
1596 __ unspill(as_VectorRegister(Matcher::_regEncode[dst_lo]), ra_->reg2offset(src_lo));
1597 } else if (src_lo_rc == rc_vector && dst_lo_rc == rc_vector) {
1598 // vpr to vpr
1599 __ vmv1r_v(as_VectorRegister(Matcher::_regEncode[dst_lo]), as_VectorRegister(Matcher::_regEncode[src_lo]));
1600 } else {
1601 ShouldNotReachHere();
1602 }
1603 } else if (bottom_type()->isa_vectmask() && masm) {
1604 int vmask_size_in_bytes = Matcher::scalable_predicate_reg_slots() * 32 / 8;
1605 if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
1606 // stack to stack
1607 __ spill_copy_vmask_stack_to_stack(src_offset, dst_offset,
1608 vmask_size_in_bytes);
1609 } else if (src_lo_rc == rc_vector && dst_lo_rc == rc_stack) {
1610 // vmask to stack
1611 __ spill_vmask(as_VectorRegister(Matcher::_regEncode[src_lo]), ra_->reg2offset(dst_lo));
1612 } else if (src_lo_rc == rc_stack && dst_lo_rc == rc_vector) {
1613 // stack to vmask
1614 __ unspill_vmask(as_VectorRegister(Matcher::_regEncode[dst_lo]), ra_->reg2offset(src_lo));
1615 } else if (src_lo_rc == rc_vector && dst_lo_rc == rc_vector) {
1616 // vmask to vmask
1617 __ vmv1r_v(as_VectorRegister(Matcher::_regEncode[dst_lo]), as_VectorRegister(Matcher::_regEncode[src_lo]));
1618 } else {
1619 ShouldNotReachHere();
1620 }
1621 }
1622 } else if (masm != nullptr) {
1623 switch (src_lo_rc) {
1624 case rc_int:
1625 if (dst_lo_rc == rc_int) { // gpr --> gpr copy
1626 if (!is64 && this->ideal_reg() != Op_RegI) { // zero extended for narrow oop or klass
1627 __ zext(as_Register(Matcher::_regEncode[dst_lo]), as_Register(Matcher::_regEncode[src_lo]), 32);
1628 } else {
1629 __ mv(as_Register(Matcher::_regEncode[dst_lo]), as_Register(Matcher::_regEncode[src_lo]));
1630 }
1631 } else if (dst_lo_rc == rc_float) { // gpr --> fpr copy
1632 if (is64) {
1633 __ fmv_d_x(as_FloatRegister(Matcher::_regEncode[dst_lo]),
1634 as_Register(Matcher::_regEncode[src_lo]));
1635 } else {
1636 __ fmv_w_x(as_FloatRegister(Matcher::_regEncode[dst_lo]),
1637 as_Register(Matcher::_regEncode[src_lo]));
1638 }
1639 } else { // gpr --> stack spill
1640 assert(dst_lo_rc == rc_stack, "spill to bad register class");
1641 __ spill(as_Register(Matcher::_regEncode[src_lo]), is64, dst_offset);
1642 }
1643 break;
1644 case rc_float:
1645 if (dst_lo_rc == rc_int) { // fpr --> gpr copy
1646 if (is64) {
1647 __ fmv_x_d(as_Register(Matcher::_regEncode[dst_lo]),
1648 as_FloatRegister(Matcher::_regEncode[src_lo]));
1649 } else {
1650 __ fmv_x_w(as_Register(Matcher::_regEncode[dst_lo]),
1651 as_FloatRegister(Matcher::_regEncode[src_lo]));
1652 }
1653 } else if (dst_lo_rc == rc_float) { // fpr --> fpr copy
1654 if (is64) {
1655 __ fmv_d(as_FloatRegister(Matcher::_regEncode[dst_lo]),
1656 as_FloatRegister(Matcher::_regEncode[src_lo]));
1657 } else {
1658 __ fmv_s(as_FloatRegister(Matcher::_regEncode[dst_lo]),
1659 as_FloatRegister(Matcher::_regEncode[src_lo]));
1660 }
1661 } else { // fpr --> stack spill
1662 assert(dst_lo_rc == rc_stack, "spill to bad register class");
1663 __ spill(as_FloatRegister(Matcher::_regEncode[src_lo]),
1664 is64, dst_offset);
1665 }
1666 break;
1667 case rc_stack:
1668 if (dst_lo_rc == rc_int) { // stack --> gpr load
1669 if (this->ideal_reg() == Op_RegI) {
1670 __ unspill(as_Register(Matcher::_regEncode[dst_lo]), is64, src_offset);
1671 } else { // // zero extended for narrow oop or klass
1672 __ unspillu(as_Register(Matcher::_regEncode[dst_lo]), is64, src_offset);
1673 }
1674 } else if (dst_lo_rc == rc_float) { // stack --> fpr load
1675 __ unspill(as_FloatRegister(Matcher::_regEncode[dst_lo]),
1676 is64, src_offset);
1677 } else { // stack --> stack copy
1678 assert(dst_lo_rc == rc_stack, "spill to bad register class");
1679 if (this->ideal_reg() == Op_RegI) {
1680 __ unspill(t0, is64, src_offset);
1681 } else { // zero extended for narrow oop or klass
1682 __ unspillu(t0, is64, src_offset);
1683 }
1684 __ spill(t0, is64, dst_offset);
1685 }
1686 break;
1687 default:
1688 ShouldNotReachHere();
1689 }
1690 }
1691
1692 if (st != nullptr) {
1693 st->print("spill ");
1694 if (src_lo_rc == rc_stack) {
1695 st->print("[sp, #%d] -> ", src_offset);
1696 } else {
1697 st->print("%s -> ", Matcher::regName[src_lo]);
1698 }
1699 if (dst_lo_rc == rc_stack) {
1700 st->print("[sp, #%d]", dst_offset);
1701 } else {
1702 st->print("%s", Matcher::regName[dst_lo]);
1703 }
1704 if (bottom_type()->isa_vect() && !bottom_type()->isa_vectmask()) {
1705 int vsize = 0;
1706 if (ideal_reg() == Op_VecA) {
1707 vsize = Matcher::scalable_vector_reg_size(T_BYTE) * 8;
1708 } else {
1709 ShouldNotReachHere();
1710 }
1711 st->print("\t# vector spill size = %d", vsize);
1712 } else if (ideal_reg() == Op_RegVectMask) {
1713 assert(Matcher::supports_scalable_vector(), "bad register type for spill");
1714 int vsize = Matcher::scalable_predicate_reg_slots() * 32;
1715 st->print("\t# vmask spill size = %d", vsize);
1716 } else {
1717 st->print("\t# spill size = %d", is64 ? 64 : 32);
1718 }
1719 }
1720
1721 return 0;
1722 }
1723
1724 #ifndef PRODUCT
1725 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1726 if (ra_ == nullptr) {
1727 st->print("N%d = SpillCopy(N%d)", _idx, in(1)->_idx);
1728 } else {
1729 implementation(nullptr, ra_, false, st);
1730 }
1731 }
1732 #endif
1733
1734 void MachSpillCopyNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
1735 implementation(masm, ra_, false, nullptr);
1736 }
1737
1738 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1739 return MachNode::size(ra_);
1740 }
1741
1742 //=============================================================================
1743
1744 #ifndef PRODUCT
1745 void BoxLockNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1746 assert_cond(ra_ != nullptr && st != nullptr);
1747 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1748 int reg = ra_->get_reg_first(this);
1749 st->print("add %s, sp, #%d\t# box lock",
1750 Matcher::regName[reg], offset);
1751 }
1752 #endif
1753
1754 void BoxLockNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
1755 Assembler::IncompressibleRegion ir(masm); // Fixed length: see BoxLockNode::size()
1756
1757 assert_cond(ra_ != nullptr);
1758 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1759 int reg = ra_->get_encode(this);
1760
1761 if (Assembler::is_simm12(offset)) {
1762 __ addi(as_Register(reg), sp, offset);
1763 } else {
1764 __ li32(t0, offset);
1765 __ add(as_Register(reg), sp, t0);
1766 }
1767 }
1768
1769 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1770 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_).
1771 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1772
1773 if (Assembler::is_simm12(offset)) {
1774 return NativeInstruction::instruction_size;
1775 } else {
1776 return 3 * NativeInstruction::instruction_size; // lui + addiw + add;
1777 }
1778 }
1779
1780 //=============================================================================
1781
1782 #ifndef PRODUCT
1783 void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1784 {
1785 assert_cond(st != nullptr);
1786 st->print_cr("# MachUEPNode");
1787 if (UseCompressedClassPointers) {
1788 st->print_cr("\tlwu t1, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass");
1789 st->print_cr("\tlwu t2, [t0 + CompiledICData::speculated_klass_offset()]\t# compressed klass");
1790 } else {
1791 st->print_cr("\tld t1, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass");
1792 st->print_cr("\tld t2, [t0 + CompiledICData::speculated_klass_offset()]\t# compressed klass");
1793 }
1794 st->print_cr("\tbeq t1, t2, ic_hit");
1795 st->print_cr("\tj, SharedRuntime::_ic_miss_stub\t # Inline cache check");
1796 st->print_cr("\tic_hit:");
1797 }
1798 #endif
1799
1800 void MachUEPNode::emit(C2_MacroAssembler* masm, PhaseRegAlloc* ra_) const
1801 {
1802 // This is the unverified entry point.
1803 __ ic_check(CodeEntryAlignment);
1804
1805 // Verified entry point must be properly 4 bytes aligned for patching by NativeJump::patch_verified_entry().
1806 // ic_check() aligns to CodeEntryAlignment >= InteriorEntryAlignment(min 16) > NativeInstruction::instruction_size(4).
1807 assert(((__ offset()) % CodeEntryAlignment) == 0, "Misaligned verified entry point");
1808 }
1809
1810 uint MachUEPNode::size(PhaseRegAlloc* ra_) const
1811 {
1812 assert_cond(ra_ != nullptr);
1813 return MachNode::size(ra_);
1814 }
1815
1816 // REQUIRED EMIT CODE
1817
1818 //=============================================================================
1819
1820 // Emit exception handler code.
1821 int HandlerImpl::emit_exception_handler(C2_MacroAssembler* masm)
1822 {
1823 // auipc t1, #exception_blob_entry_point
1824 // jr (offset)t1
1825 // Note that the code buffer's insts_mark is always relative to insts.
1826 // That's why we must use the macroassembler to generate a handler.
1827 address base = __ start_a_stub(size_exception_handler());
1828 if (base == nullptr) {
1829 ciEnv::current()->record_failure("CodeCache is full");
1830 return 0; // CodeBuffer::expand failed
1831 }
1832 int offset = __ offset();
1833 __ far_jump(RuntimeAddress(OptoRuntime::exception_blob()->entry_point()));
1834 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1835 __ end_a_stub();
1836 return offset;
1837 }
1838
1839 // Emit deopt handler code.
1840 int HandlerImpl::emit_deopt_handler(C2_MacroAssembler* masm)
1841 {
1842 address base = __ start_a_stub(size_deopt_handler());
1843 if (base == nullptr) {
1844 ciEnv::current()->record_failure("CodeCache is full");
1845 return 0; // CodeBuffer::expand failed
1846 }
1847 int offset = __ offset();
1848
1849 __ auipc(ra, 0);
1850 __ far_jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
1851
1852 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1853 __ end_a_stub();
1854 return offset;
1855
1856 }
1857 // REQUIRED MATCHER CODE
1858
1859 //=============================================================================
1860
1861 bool Matcher::match_rule_supported(int opcode) {
1862 if (!has_match_rule(opcode)) {
1863 return false;
1864 }
1865
1866 switch (opcode) {
1867 case Op_OnSpinWait:
1868 return VM_Version::supports_on_spin_wait();
1869 case Op_CacheWB: // fall through
1870 case Op_CacheWBPreSync: // fall through
1871 case Op_CacheWBPostSync:
1872 if (!VM_Version::supports_data_cache_line_flush()) {
1873 return false;
1874 }
1875 break;
1876
1877 case Op_StrCompressedCopy: // fall through
1878 case Op_StrInflatedCopy: // fall through
1879 case Op_CountPositives: // fall through
1880 case Op_EncodeISOArray:
1881 return UseRVV;
1882
1883 // Current test shows that, it brings performance gain when MaxVectorSize >= 32, but brings
1884 // regression when MaxVectorSize == 16. So only enable the intrinsic when MaxVectorSize >= 32.
1885 case Op_RoundVF:
1886 return UseRVV && MaxVectorSize >= 32;
1887
1888 // For double, current test shows that even with MaxVectorSize == 32, there is still some regression.
1889 // Although there is no hardware to verify it for now, from the trend of performance data on hardwares
1890 // (with vlenb == 16 and 32 respectively), it's promising to bring better performance rather than
1891 // regression for double when MaxVectorSize == 64+. So only enable the intrinsic when MaxVectorSize >= 64.
1892 case Op_RoundVD:
1893 return UseRVV && MaxVectorSize >= 64;
1894
1895 case Op_PopCountI:
1896 case Op_PopCountL:
1897 return UsePopCountInstruction;
1898
1899 case Op_ReverseI:
1900 case Op_ReverseL:
1901 return UseZbkb;
1902
1903 case Op_ReverseBytesI:
1904 case Op_ReverseBytesL:
1905 case Op_ReverseBytesS:
1906 case Op_ReverseBytesUS:
1907 case Op_RotateRight:
1908 case Op_RotateLeft:
1909 case Op_CountLeadingZerosI:
1910 case Op_CountLeadingZerosL:
1911 case Op_CountTrailingZerosI:
1912 case Op_CountTrailingZerosL:
1913 return UseZbb;
1914
1915 case Op_FmaF:
1916 case Op_FmaD:
1917 case Op_FmaVF:
1918 case Op_FmaVD:
1919 return UseFMA;
1920
1921 case Op_ConvHF2F:
1922 case Op_ConvF2HF:
1923 return VM_Version::supports_float16_float_conversion();
1924 case Op_ReinterpretS2HF:
1925 case Op_ReinterpretHF2S:
1926 return UseZfh || UseZfhmin;
1927 case Op_AddHF:
1928 case Op_DivHF:
1929 case Op_FmaHF:
1930 case Op_MaxHF:
1931 case Op_MinHF:
1932 case Op_MulHF:
1933 case Op_SubHF:
1934 case Op_SqrtHF:
1935 return UseZfh;
1936 }
1937
1938 return true; // Per default match rules are supported.
1939 }
1940
1941 const RegMask* Matcher::predicate_reg_mask(void) {
1942 return &_VMASK_REG_mask;
1943 }
1944
1945 // Vector calling convention not yet implemented.
1946 bool Matcher::supports_vector_calling_convention(void) {
1947 return EnableVectorSupport && UseVectorStubs;
1948 }
1949
1950 OptoRegPair Matcher::vector_return_value(uint ideal_reg) {
1951 assert(EnableVectorSupport && UseVectorStubs, "sanity");
1952 assert(ideal_reg == Op_VecA, "sanity");
1953 // check more info at https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-cc.adoc
1954 int lo = V8_num;
1955 int hi = V8_K_num;
1956 return OptoRegPair(hi, lo);
1957 }
1958
1959 // Is this branch offset short enough that a short branch can be used?
1960 //
1961 // NOTE: If the platform does not provide any short branch variants, then
1962 // this method should return false for offset 0.
1963 // |---label(L1)-----|
1964 // |-----------------|
1965 // |-----------------|----------eq: float-------------------
1966 // |-----------------| // far_cmpD_branch | cmpD_branch
1967 // |------- ---------| feq; | feq;
1968 // |-far_cmpD_branch-| beqz done; | bnez L;
1969 // |-----------------| j L; |
1970 // |-----------------| bind(done); |
1971 // |-----------------|--------------------------------------
1972 // |-----------------| // so shortBrSize = br_size - 4;
1973 // |-----------------| // so offs = offset - shortBrSize + 4;
1974 // |---label(L2)-----|
1975 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1976 // The passed offset is relative to address of the branch.
1977 int shortBrSize = br_size - 4;
1978 int offs = offset - shortBrSize + 4;
1979 return (-4096 <= offs && offs < 4096);
1980 }
1981
1982 // Vector width in bytes.
1983 int Matcher::vector_width_in_bytes(BasicType bt) {
1984 if (UseRVV) {
1985 // The MaxVectorSize should have been set by detecting RVV max vector register size when check UseRVV.
1986 // MaxVectorSize == VM_Version::_initial_vector_length
1987 int size = MaxVectorSize;
1988 // Minimum 2 values in vector
1989 if (size < 2 * type2aelembytes(bt)) size = 0;
1990 // But never < 4
1991 if (size < 4) size = 0;
1992 return size;
1993 }
1994 return 0;
1995 }
1996
1997 // Limits on vector size (number of elements) loaded into vector.
1998 int Matcher::max_vector_size(const BasicType bt) {
1999 return vector_width_in_bytes(bt) / type2aelembytes(bt);
2000 }
2001
2002 int Matcher::min_vector_size(const BasicType bt) {
2003 int max_size = max_vector_size(bt);
2004 // Limit the min vector size to 8 bytes.
2005 int size = 8 / type2aelembytes(bt);
2006 if (bt == T_BYTE) {
2007 // To support vector api shuffle/rearrange.
2008 size = 4;
2009 } else if (bt == T_BOOLEAN) {
2010 // To support vector api load/store mask.
2011 size = 2;
2012 }
2013 if (size < 2) size = 2;
2014 return MIN2(size, max_size);
2015 }
2016
2017 int Matcher::max_vector_size_auto_vectorization(const BasicType bt) {
2018 return Matcher::max_vector_size(bt);
2019 }
2020
2021 // Vector ideal reg.
2022 uint Matcher::vector_ideal_reg(int len) {
2023 assert(MaxVectorSize >= len, "");
2024 if (UseRVV) {
2025 return Op_VecA;
2026 }
2027
2028 ShouldNotReachHere();
2029 return 0;
2030 }
2031
2032 int Matcher::scalable_vector_reg_size(const BasicType bt) {
2033 return Matcher::max_vector_size(bt);
2034 }
2035
2036 MachOper* Matcher::pd_specialize_generic_vector_operand(MachOper* original_opnd, uint ideal_reg, bool is_temp) {
2037 ShouldNotReachHere(); // generic vector operands not supported
2038 return nullptr;
2039 }
2040
2041 bool Matcher::is_reg2reg_move(MachNode* m) {
2042 ShouldNotReachHere(); // generic vector operands not supported
2043 return false;
2044 }
2045
2046 bool Matcher::is_generic_vector(MachOper* opnd) {
2047 ShouldNotReachHere(); // generic vector operands not supported
2048 return false;
2049 }
2050
2051 // Return whether or not this register is ever used as an argument.
2052 // This function is used on startup to build the trampoline stubs in
2053 // generateOptoStub. Registers not mentioned will be killed by the VM
2054 // call in the trampoline, and arguments in those registers not be
2055 // available to the callee.
2056 bool Matcher::can_be_java_arg(int reg)
2057 {
2058 return
2059 reg == R10_num || reg == R10_H_num ||
2060 reg == R11_num || reg == R11_H_num ||
2061 reg == R12_num || reg == R12_H_num ||
2062 reg == R13_num || reg == R13_H_num ||
2063 reg == R14_num || reg == R14_H_num ||
2064 reg == R15_num || reg == R15_H_num ||
2065 reg == R16_num || reg == R16_H_num ||
2066 reg == R17_num || reg == R17_H_num ||
2067 reg == F10_num || reg == F10_H_num ||
2068 reg == F11_num || reg == F11_H_num ||
2069 reg == F12_num || reg == F12_H_num ||
2070 reg == F13_num || reg == F13_H_num ||
2071 reg == F14_num || reg == F14_H_num ||
2072 reg == F15_num || reg == F15_H_num ||
2073 reg == F16_num || reg == F16_H_num ||
2074 reg == F17_num || reg == F17_H_num;
2075 }
2076
2077 bool Matcher::is_spillable_arg(int reg)
2078 {
2079 return can_be_java_arg(reg);
2080 }
2081
2082 uint Matcher::int_pressure_limit()
2083 {
2084 // A derived pointer is live at CallNode and then is flagged by RA
2085 // as a spilled LRG. Spilling heuristics(Spill-USE) explicitly skip
2086 // derived pointers and lastly fail to spill after reaching maximum
2087 // number of iterations. Lowering the default pressure threshold to
2088 // (_NO_SPECIAL_REG32_mask.Size() minus 1) forces CallNode to become
2089 // a high register pressure area of the code so that split_DEF can
2090 // generate DefinitionSpillCopy for the derived pointer.
2091 uint default_int_pressure_threshold = _NO_SPECIAL_REG32_mask.Size() - 1;
2092 if (!PreserveFramePointer) {
2093 // When PreserveFramePointer is off, frame pointer is allocatable,
2094 // but different from other SOC registers, it is excluded from
2095 // fatproj's mask because its save type is No-Save. Decrease 1 to
2096 // ensure high pressure at fatproj when PreserveFramePointer is off.
2097 // See check_pressure_at_fatproj().
2098 default_int_pressure_threshold--;
2099 }
2100 return (INTPRESSURE == -1) ? default_int_pressure_threshold : INTPRESSURE;
2101 }
2102
2103 uint Matcher::float_pressure_limit()
2104 {
2105 // _FLOAT_REG_mask is generated by adlc from the float_reg register class.
2106 return (FLOATPRESSURE == -1) ? _FLOAT_REG_mask.Size() : FLOATPRESSURE;
2107 }
2108
2109 bool Matcher::use_asm_for_ldiv_by_con(jlong divisor) {
2110 return false;
2111 }
2112
2113 RegMask Matcher::divI_proj_mask() {
2114 ShouldNotReachHere();
2115 return RegMask();
2116 }
2117
2118 // Register for MODI projection of divmodI.
2119 RegMask Matcher::modI_proj_mask() {
2120 ShouldNotReachHere();
2121 return RegMask();
2122 }
2123
2124 // Register for DIVL projection of divmodL.
2125 RegMask Matcher::divL_proj_mask() {
2126 ShouldNotReachHere();
2127 return RegMask();
2128 }
2129
2130 // Register for MODL projection of divmodL.
2131 RegMask Matcher::modL_proj_mask() {
2132 ShouldNotReachHere();
2133 return RegMask();
2134 }
2135
2136 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
2137 return FP_REG_mask();
2138 }
2139
2140 bool size_fits_all_mem_uses(AddPNode* addp, int shift) {
2141 assert_cond(addp != nullptr);
2142 for (DUIterator_Fast imax, i = addp->fast_outs(imax); i < imax; i++) {
2143 Node* u = addp->fast_out(i);
2144 if (u != nullptr && u->is_Mem()) {
2145 int opsize = u->as_Mem()->memory_size();
2146 assert(opsize > 0, "unexpected memory operand size");
2147 if (u->as_Mem()->memory_size() != (1 << shift)) {
2148 return false;
2149 }
2150 }
2151 }
2152 return true;
2153 }
2154
2155 // Binary src (Replicate scalar/immediate)
2156 static bool is_vector_scalar_bitwise_pattern(Node* n, Node* m) {
2157 if (n == nullptr || m == nullptr) {
2158 return false;
2159 }
2160
2161 if (m->Opcode() != Op_Replicate) {
2162 return false;
2163 }
2164
2165 switch (n->Opcode()) {
2166 case Op_AndV:
2167 case Op_OrV:
2168 case Op_XorV:
2169 case Op_AddVB:
2170 case Op_AddVS:
2171 case Op_AddVI:
2172 case Op_AddVL:
2173 case Op_SubVB:
2174 case Op_SubVS:
2175 case Op_SubVI:
2176 case Op_SubVL:
2177 case Op_MulVB:
2178 case Op_MulVS:
2179 case Op_MulVI:
2180 case Op_MulVL: {
2181 return true;
2182 }
2183 default:
2184 return false;
2185 }
2186 }
2187
2188 // (XorV src (Replicate m1))
2189 // (XorVMask src (MaskAll m1))
2190 static bool is_vector_bitwise_not_pattern(Node* n, Node* m) {
2191 if (n != nullptr && m != nullptr) {
2192 return (n->Opcode() == Op_XorV || n->Opcode() == Op_XorVMask) &&
2193 VectorNode::is_all_ones_vector(m);
2194 }
2195 return false;
2196 }
2197
2198 // Should the Matcher clone input 'm' of node 'n'?
2199 bool Matcher::pd_clone_node(Node* n, Node* m, Matcher::MStack& mstack) {
2200 assert_cond(m != nullptr);
2201 if (is_vshift_con_pattern(n, m) || // ShiftV src (ShiftCntV con)
2202 is_vector_bitwise_not_pattern(n, m) ||
2203 is_vector_scalar_bitwise_pattern(n, m) ||
2204 is_encode_and_store_pattern(n, m)) {
2205 mstack.push(m, Visit);
2206 return true;
2207 }
2208 return false;
2209 }
2210
2211 // Should the Matcher clone shifts on addressing modes, expecting them
2212 // to be subsumed into complex addressing expressions or compute them
2213 // into registers?
2214 bool Matcher::pd_clone_address_expressions(AddPNode* m, Matcher::MStack& mstack, VectorSet& address_visited) {
2215 return clone_base_plus_offset_address(m, mstack, address_visited);
2216 }
2217
2218 %}
2219
2220
2221
2222 //----------ENCODING BLOCK-----------------------------------------------------
2223 // This block specifies the encoding classes used by the compiler to
2224 // output byte streams. Encoding classes are parameterized macros
2225 // used by Machine Instruction Nodes in order to generate the bit
2226 // encoding of the instruction. Operands specify their base encoding
2227 // interface with the interface keyword. There are currently
2228 // supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, &
2229 // COND_INTER. REG_INTER causes an operand to generate a function
2230 // which returns its register number when queried. CONST_INTER causes
2231 // an operand to generate a function which returns the value of the
2232 // constant when queried. MEMORY_INTER causes an operand to generate
2233 // four functions which return the Base Register, the Index Register,
2234 // the Scale Value, and the Offset Value of the operand when queried.
2235 // COND_INTER causes an operand to generate six functions which return
2236 // the encoding code (ie - encoding bits for the instruction)
2237 // associated with each basic boolean condition for a conditional
2238 // instruction.
2239 //
2240 // Instructions specify two basic values for encoding. Again, a
2241 // function is available to check if the constant displacement is an
2242 // oop. They use the ins_encode keyword to specify their encoding
2243 // classes (which must be a sequence of enc_class names, and their
2244 // parameters, specified in the encoding block), and they use the
2245 // opcode keyword to specify, in order, their primary, secondary, and
2246 // tertiary opcode. Only the opcode sections which a particular
2247 // instruction needs for encoding need to be specified.
2248 encode %{
2249 // BEGIN Non-volatile memory access
2250
2251 enc_class riscv_enc_mov_imm(iRegIorL dst, immIorL src) %{
2252 int64_t con = (int64_t)$src$$constant;
2253 Register dst_reg = as_Register($dst$$reg);
2254 __ mv(dst_reg, con);
2255 %}
2256
2257 enc_class riscv_enc_mov_p(iRegP dst, immP src) %{
2258 Register dst_reg = as_Register($dst$$reg);
2259 address con = (address)$src$$constant;
2260 if (con == nullptr || con == (address)1) {
2261 ShouldNotReachHere();
2262 } else {
2263 relocInfo::relocType rtype = $src->constant_reloc();
2264 if (rtype == relocInfo::oop_type) {
2265 __ movoop(dst_reg, (jobject)con);
2266 } else if (rtype == relocInfo::metadata_type) {
2267 __ mov_metadata(dst_reg, (Metadata*)con);
2268 } else {
2269 assert(rtype == relocInfo::none, "unexpected reloc type");
2270 __ mv(dst_reg, $src$$constant);
2271 }
2272 }
2273 %}
2274
2275 enc_class riscv_enc_mov_p1(iRegP dst) %{
2276 Register dst_reg = as_Register($dst$$reg);
2277 __ mv(dst_reg, 1);
2278 %}
2279
2280 enc_class riscv_enc_mov_byte_map_base(iRegP dst) %{
2281 __ load_byte_map_base($dst$$Register);
2282 %}
2283
2284 enc_class riscv_enc_mov_n(iRegN dst, immN src) %{
2285 Register dst_reg = as_Register($dst$$reg);
2286 address con = (address)$src$$constant;
2287 if (con == nullptr) {
2288 ShouldNotReachHere();
2289 } else {
2290 relocInfo::relocType rtype = $src->constant_reloc();
2291 assert(rtype == relocInfo::oop_type, "unexpected reloc type");
2292 __ set_narrow_oop(dst_reg, (jobject)con);
2293 }
2294 %}
2295
2296 enc_class riscv_enc_mov_zero(iRegNorP dst) %{
2297 Register dst_reg = as_Register($dst$$reg);
2298 __ mv(dst_reg, zr);
2299 %}
2300
2301 enc_class riscv_enc_mov_nk(iRegN dst, immNKlass src) %{
2302 Register dst_reg = as_Register($dst$$reg);
2303 address con = (address)$src$$constant;
2304 if (con == nullptr) {
2305 ShouldNotReachHere();
2306 } else {
2307 relocInfo::relocType rtype = $src->constant_reloc();
2308 assert(rtype == relocInfo::metadata_type, "unexpected reloc type");
2309 __ set_narrow_klass(dst_reg, (Klass *)con);
2310 }
2311 %}
2312
2313 enc_class riscv_enc_cmpxchgw(iRegINoSp res, memory mem, iRegI oldval, iRegI newval) %{
2314 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
2315 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
2316 /*result as bool*/ true);
2317 %}
2318
2319 enc_class riscv_enc_cmpxchgn(iRegINoSp res, memory mem, iRegI oldval, iRegI newval) %{
2320 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
2321 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
2322 /*result as bool*/ true);
2323 %}
2324
2325 enc_class riscv_enc_cmpxchg(iRegINoSp res, memory mem, iRegL oldval, iRegL newval) %{
2326 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
2327 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
2328 /*result as bool*/ true);
2329 %}
2330
2331 enc_class riscv_enc_cmpxchgw_acq(iRegINoSp res, memory mem, iRegI oldval, iRegI newval) %{
2332 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
2333 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
2334 /*result as bool*/ true);
2335 %}
2336
2337 enc_class riscv_enc_cmpxchgn_acq(iRegINoSp res, memory mem, iRegI oldval, iRegI newval) %{
2338 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
2339 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
2340 /*result as bool*/ true);
2341 %}
2342
2343 enc_class riscv_enc_cmpxchg_acq(iRegINoSp res, memory mem, iRegL oldval, iRegL newval) %{
2344 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
2345 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
2346 /*result as bool*/ true);
2347 %}
2348
2349 // compare and branch instruction encodings
2350
2351 enc_class riscv_enc_j(label lbl) %{
2352 Label* L = $lbl$$label;
2353 __ j(*L);
2354 %}
2355
2356 enc_class riscv_enc_far_cmpULtGe_imm0_branch(cmpOpULtGe cmp, iRegIorL op1, label lbl) %{
2357 Label* L = $lbl$$label;
2358 switch ($cmp$$cmpcode) {
2359 case(BoolTest::ge):
2360 __ j(*L);
2361 break;
2362 case(BoolTest::lt):
2363 break;
2364 default:
2365 Unimplemented();
2366 }
2367 %}
2368
2369 // call instruction encodings
2370
2371 enc_class riscv_enc_partial_subtype_check(iRegP sub, iRegP super, iRegP temp, iRegP result) %{
2372 Register sub_reg = as_Register($sub$$reg);
2373 Register super_reg = as_Register($super$$reg);
2374 Register temp_reg = as_Register($temp$$reg);
2375 Register result_reg = as_Register($result$$reg);
2376 Register cr_reg = t1;
2377
2378 Label miss;
2379 Label done;
2380 __ check_klass_subtype_slow_path(sub_reg, super_reg, temp_reg, result_reg,
2381 nullptr, &miss, /*set_cond_codes*/ true);
2382 if ($primary) {
2383 __ mv(result_reg, zr);
2384 } else {
2385 __ mv(cr_reg, zr);
2386 __ j(done);
2387 }
2388
2389 __ bind(miss);
2390 if (!$primary) {
2391 __ mv(cr_reg, 1);
2392 }
2393
2394 __ bind(done);
2395 %}
2396
2397 enc_class riscv_enc_java_static_call(method meth) %{
2398 Assembler::IncompressibleRegion ir(masm); // Fixed length: see ret_addr_offset
2399
2400 address addr = (address)$meth$$method;
2401 address call = nullptr;
2402 assert_cond(addr != nullptr);
2403 if (!_method) {
2404 // A call to a runtime wrapper, e.g. new, new_typeArray_Java, uncommon_trap.
2405 call = __ reloc_call(Address(addr, relocInfo::runtime_call_type));
2406 if (call == nullptr) {
2407 ciEnv::current()->record_failure("CodeCache is full");
2408 return;
2409 }
2410 } else if (_method->intrinsic_id() == vmIntrinsicID::_ensureMaterializedForStackWalk) {
2411 // The NOP here is purely to ensure that eliding a call to
2412 // JVM_EnsureMaterializedForStackWalk doesn't change the code size.
2413 __ nop();
2414 __ nop();
2415 __ nop();
2416 __ block_comment("call JVM_EnsureMaterializedForStackWalk (elided)");
2417 } else {
2418 int method_index = resolved_method_index(masm);
2419 RelocationHolder rspec = _optimized_virtual ? opt_virtual_call_Relocation::spec(method_index)
2420 : static_call_Relocation::spec(method_index);
2421 call = __ reloc_call(Address(addr, rspec));
2422 if (call == nullptr) {
2423 ciEnv::current()->record_failure("CodeCache is full");
2424 return;
2425 }
2426
2427 if (CodeBuffer::supports_shared_stubs() && _method->can_be_statically_bound()) {
2428 // Calls of the same statically bound method can share
2429 // a stub to the interpreter.
2430 __ code()->shared_stub_to_interp_for(_method, call - (__ begin()));
2431 } else {
2432 // Emit stub for static call
2433 address stub = CompiledDirectCall::emit_to_interp_stub(masm, call);
2434 if (stub == nullptr) {
2435 ciEnv::current()->record_failure("CodeCache is full");
2436 return;
2437 }
2438 }
2439 }
2440
2441 __ post_call_nop();
2442 %}
2443
2444 enc_class riscv_enc_java_dynamic_call(method meth) %{
2445 Assembler::IncompressibleRegion ir(masm); // Fixed length: see ret_addr_offset
2446 int method_index = resolved_method_index(masm);
2447 address call = __ ic_call((address)$meth$$method, method_index);
2448 if (call == nullptr) {
2449 ciEnv::current()->record_failure("CodeCache is full");
2450 return;
2451 }
2452
2453 __ post_call_nop();
2454 %}
2455
2456 enc_class riscv_enc_call_epilog() %{
2457 if (VerifyStackAtCalls) {
2458 // Check that stack depth is unchanged: find majik cookie on stack
2459 __ call_Unimplemented();
2460 }
2461 %}
2462
2463 enc_class riscv_enc_java_to_runtime(method meth) %{
2464 Assembler::IncompressibleRegion ir(masm); // Fixed length: see ret_addr_offset
2465
2466 // Some calls to generated routines (arraycopy code) are scheduled by C2
2467 // as runtime calls. if so we can call them using a far call (they will be
2468 // in the code cache, thus in a reachable segment) otherwise we have to use
2469 // a movptr+jalr pair which loads the absolute address into a register.
2470 address entry = (address)$meth$$method;
2471 if (CodeCache::contains(entry)) {
2472 __ far_call(Address(entry, relocInfo::runtime_call_type));
2473 __ post_call_nop();
2474 } else {
2475 Label retaddr;
2476 // Make the anchor frame walkable
2477 __ la(t0, retaddr);
2478 __ sd(t0, Address(xthread, JavaThread::last_Java_pc_offset()));
2479 int32_t offset = 0;
2480 // No relocation needed
2481 __ movptr(t1, entry, offset, t0); // lui + lui + slli + add
2482 __ jalr(t1, offset);
2483 __ bind(retaddr);
2484 __ post_call_nop();
2485 }
2486 %}
2487
2488 enc_class riscv_enc_tail_call(iRegP jump_target) %{
2489 Register target_reg = as_Register($jump_target$$reg);
2490 __ jr(target_reg);
2491 %}
2492
2493 enc_class riscv_enc_tail_jmp(iRegP jump_target) %{
2494 Register target_reg = as_Register($jump_target$$reg);
2495 // exception oop should be in x10
2496 // ret addr has been popped into ra
2497 // callee expects it in x13
2498 __ mv(x13, ra);
2499 __ jr(target_reg);
2500 %}
2501
2502 enc_class riscv_enc_rethrow() %{
2503 __ far_jump(RuntimeAddress(OptoRuntime::rethrow_stub()));
2504 %}
2505
2506 enc_class riscv_enc_ret() %{
2507 __ ret();
2508 %}
2509
2510 %}
2511
2512 //----------FRAME--------------------------------------------------------------
2513 // Definition of frame structure and management information.
2514 //
2515 // S T A C K L A Y O U T Allocators stack-slot number
2516 // | (to get allocators register number
2517 // G Owned by | | v add OptoReg::stack0())
2518 // r CALLER | |
2519 // o | +--------+ pad to even-align allocators stack-slot
2520 // w V | pad0 | numbers; owned by CALLER
2521 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
2522 // h ^ | in | 5
2523 // | | args | 4 Holes in incoming args owned by SELF
2524 // | | | | 3
2525 // | | +--------+
2526 // V | | old out| Empty on Intel, window on Sparc
2527 // | old |preserve| Must be even aligned.
2528 // | SP-+--------+----> Matcher::_old_SP, even aligned
2529 // | | in | 3 area for Intel ret address
2530 // Owned by |preserve| Empty on Sparc.
2531 // SELF +--------+
2532 // | | pad2 | 2 pad to align old SP
2533 // | +--------+ 1
2534 // | | locks | 0
2535 // | +--------+----> OptoReg::stack0(), even aligned
2536 // | | pad1 | 11 pad to align new SP
2537 // | +--------+
2538 // | | | 10
2539 // | | spills | 9 spills
2540 // V | | 8 (pad0 slot for callee)
2541 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
2542 // ^ | out | 7
2543 // | | args | 6 Holes in outgoing args owned by CALLEE
2544 // Owned by +--------+
2545 // CALLEE | new out| 6 Empty on Intel, window on Sparc
2546 // | new |preserve| Must be even-aligned.
2547 // | SP-+--------+----> Matcher::_new_SP, even aligned
2548 // | | |
2549 //
2550 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
2551 // known from SELF's arguments and the Java calling convention.
2552 // Region 6-7 is determined per call site.
2553 // Note 2: If the calling convention leaves holes in the incoming argument
2554 // area, those holes are owned by SELF. Holes in the outgoing area
2555 // are owned by the CALLEE. Holes should not be necessary in the
2556 // incoming area, as the Java calling convention is completely under
2557 // the control of the AD file. Doubles can be sorted and packed to
2558 // avoid holes. Holes in the outgoing arguments may be necessary for
2559 // varargs C calling conventions.
2560 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
2561 // even aligned with pad0 as needed.
2562 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
2563 // (the latter is true on Intel but is it false on RISCV?)
2564 // region 6-11 is even aligned; it may be padded out more so that
2565 // the region from SP to FP meets the minimum stack alignment.
2566 // Note 4: For I2C adapters, the incoming FP may not meet the minimum stack
2567 // alignment. Region 11, pad1, may be dynamically extended so that
2568 // SP meets the minimum alignment.
2569
2570 frame %{
2571 // These three registers define part of the calling convention
2572 // between compiled code and the interpreter.
2573
2574 // Inline Cache Register or methodOop for I2C.
2575 inline_cache_reg(R31);
2576
2577 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
2578 cisc_spilling_operand_name(indOffset);
2579
2580 // Number of stack slots consumed by locking an object
2581 // generate Compile::sync_stack_slots
2582 // VMRegImpl::slots_per_word = wordSize / stack_slot_size = 8 / 4 = 2
2583 sync_stack_slots(1 * VMRegImpl::slots_per_word);
2584
2585 // Compiled code's Frame Pointer
2586 frame_pointer(R2);
2587
2588 // Interpreter stores its frame pointer in a register which is
2589 // stored to the stack by I2CAdaptors.
2590 // I2CAdaptors convert from interpreted java to compiled java.
2591 interpreter_frame_pointer(R8);
2592
2593 // Stack alignment requirement
2594 stack_alignment(StackAlignmentInBytes); // Alignment size in bytes (128-bit -> 16 bytes)
2595
2596 // Number of outgoing stack slots killed above the out_preserve_stack_slots
2597 // for calls to C. Supports the var-args backing area for register parms.
2598 varargs_C_out_slots_killed(frame::arg_reg_save_area_bytes / BytesPerInt);
2599
2600 // The after-PROLOG location of the return address. Location of
2601 // return address specifies a type (REG or STACK) and a number
2602 // representing the register number (i.e. - use a register name) or
2603 // stack slot.
2604 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
2605 // Otherwise, it is above the locks and verification slot and alignment word
2606 // TODO this may well be correct but need to check why that - 2 is there
2607 // ppc port uses 0 but we definitely need to allow for fixed_slots
2608 // which folds in the space used for monitors
2609 return_addr(STACK - 2 +
2610 align_up((Compile::current()->in_preserve_stack_slots() +
2611 Compile::current()->fixed_slots()),
2612 stack_alignment_in_slots()));
2613
2614 // Location of compiled Java return values. Same as C for now.
2615 return_value
2616 %{
2617 assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL,
2618 "only return normal values");
2619
2620 static const int lo[Op_RegL + 1] = { // enum name
2621 0, // Op_Node
2622 0, // Op_Set
2623 R10_num, // Op_RegN
2624 R10_num, // Op_RegI
2625 R10_num, // Op_RegP
2626 F10_num, // Op_RegF
2627 F10_num, // Op_RegD
2628 R10_num // Op_RegL
2629 };
2630
2631 static const int hi[Op_RegL + 1] = { // enum name
2632 0, // Op_Node
2633 0, // Op_Set
2634 OptoReg::Bad, // Op_RegN
2635 OptoReg::Bad, // Op_RegI
2636 R10_H_num, // Op_RegP
2637 OptoReg::Bad, // Op_RegF
2638 F10_H_num, // Op_RegD
2639 R10_H_num // Op_RegL
2640 };
2641
2642 return OptoRegPair(hi[ideal_reg], lo[ideal_reg]);
2643 %}
2644 %}
2645
2646 //----------ATTRIBUTES---------------------------------------------------------
2647 //----------Operand Attributes-------------------------------------------------
2648 op_attrib op_cost(1); // Required cost attribute
2649
2650 //----------Instruction Attributes---------------------------------------------
2651 ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute
2652 ins_attrib ins_size(32); // Required size attribute (in bits)
2653 ins_attrib ins_short_branch(0); // Required flag: is this instruction
2654 // a non-matching short branch variant
2655 // of some long branch?
2656 ins_attrib ins_alignment(4); // Required alignment attribute (must
2657 // be a power of 2) specifies the
2658 // alignment that some part of the
2659 // instruction (not necessarily the
2660 // start) requires. If > 1, a
2661 // compute_padding() function must be
2662 // provided for the instruction
2663
2664 //----------OPERANDS-----------------------------------------------------------
2665 // Operand definitions must precede instruction definitions for correct parsing
2666 // in the ADLC because operands constitute user defined types which are used in
2667 // instruction definitions.
2668
2669 //----------Simple Operands----------------------------------------------------
2670
2671 // Integer operands 32 bit
2672 // 32 bit immediate
2673 operand immI()
2674 %{
2675 match(ConI);
2676
2677 op_cost(0);
2678 format %{ %}
2679 interface(CONST_INTER);
2680 %}
2681
2682 // 32 bit zero
2683 operand immI0()
2684 %{
2685 predicate(n->get_int() == 0);
2686 match(ConI);
2687
2688 op_cost(0);
2689 format %{ %}
2690 interface(CONST_INTER);
2691 %}
2692
2693 // 32 bit unit increment
2694 operand immI_1()
2695 %{
2696 predicate(n->get_int() == 1);
2697 match(ConI);
2698
2699 op_cost(0);
2700 format %{ %}
2701 interface(CONST_INTER);
2702 %}
2703
2704 // 32 bit unit decrement
2705 operand immI_M1()
2706 %{
2707 predicate(n->get_int() == -1);
2708 match(ConI);
2709
2710 op_cost(0);
2711 format %{ %}
2712 interface(CONST_INTER);
2713 %}
2714
2715 // Unsigned Integer Immediate: 6-bit int, greater than 32
2716 operand uimmI6_ge32() %{
2717 predicate(((unsigned int)(n->get_int()) < 64) && (n->get_int() >= 32));
2718 match(ConI);
2719 op_cost(0);
2720 format %{ %}
2721 interface(CONST_INTER);
2722 %}
2723
2724 operand immI_le_4()
2725 %{
2726 predicate(n->get_int() <= 4);
2727 match(ConI);
2728
2729 op_cost(0);
2730 format %{ %}
2731 interface(CONST_INTER);
2732 %}
2733
2734 operand immI_16()
2735 %{
2736 predicate(n->get_int() == 16);
2737 match(ConI);
2738 op_cost(0);
2739 format %{ %}
2740 interface(CONST_INTER);
2741 %}
2742
2743 operand immI_24()
2744 %{
2745 predicate(n->get_int() == 24);
2746 match(ConI);
2747 op_cost(0);
2748 format %{ %}
2749 interface(CONST_INTER);
2750 %}
2751
2752 operand immI_31()
2753 %{
2754 predicate(n->get_int() == 31);
2755 match(ConI);
2756
2757 op_cost(0);
2758 format %{ %}
2759 interface(CONST_INTER);
2760 %}
2761
2762 operand immI_63()
2763 %{
2764 predicate(n->get_int() == 63);
2765 match(ConI);
2766
2767 op_cost(0);
2768 format %{ %}
2769 interface(CONST_INTER);
2770 %}
2771
2772 // 32 bit integer valid for add immediate
2773 operand immIAdd()
2774 %{
2775 predicate(Assembler::is_simm12((int64_t)n->get_int()));
2776 match(ConI);
2777 op_cost(0);
2778 format %{ %}
2779 interface(CONST_INTER);
2780 %}
2781
2782 // 32 bit integer valid for sub immediate
2783 operand immISub()
2784 %{
2785 predicate(Assembler::is_simm12(-(int64_t)n->get_int()));
2786 match(ConI);
2787 op_cost(0);
2788 format %{ %}
2789 interface(CONST_INTER);
2790 %}
2791
2792 // 5 bit signed value.
2793 operand immI5()
2794 %{
2795 predicate(n->get_int() <= 15 && n->get_int() >= -16);
2796 match(ConI);
2797
2798 op_cost(0);
2799 format %{ %}
2800 interface(CONST_INTER);
2801 %}
2802
2803 // 5 bit signed value (simm5)
2804 operand immL5()
2805 %{
2806 predicate(n->get_long() <= 15 && n->get_long() >= -16);
2807 match(ConL);
2808
2809 op_cost(0);
2810 format %{ %}
2811 interface(CONST_INTER);
2812 %}
2813
2814 // Integer operands 64 bit
2815 // 64 bit immediate
2816 operand immL()
2817 %{
2818 match(ConL);
2819
2820 op_cost(0);
2821 format %{ %}
2822 interface(CONST_INTER);
2823 %}
2824
2825 // 64 bit zero
2826 operand immL0()
2827 %{
2828 predicate(n->get_long() == 0);
2829 match(ConL);
2830
2831 op_cost(0);
2832 format %{ %}
2833 interface(CONST_INTER);
2834 %}
2835
2836 // Pointer operands
2837 // Pointer Immediate
2838 operand immP()
2839 %{
2840 match(ConP);
2841
2842 op_cost(0);
2843 format %{ %}
2844 interface(CONST_INTER);
2845 %}
2846
2847 // Null Pointer Immediate
2848 operand immP0()
2849 %{
2850 predicate(n->get_ptr() == 0);
2851 match(ConP);
2852
2853 op_cost(0);
2854 format %{ %}
2855 interface(CONST_INTER);
2856 %}
2857
2858 // Pointer Immediate One
2859 // this is used in object initialization (initial object header)
2860 operand immP_1()
2861 %{
2862 predicate(n->get_ptr() == 1);
2863 match(ConP);
2864
2865 op_cost(0);
2866 format %{ %}
2867 interface(CONST_INTER);
2868 %}
2869
2870 // Card Table Byte Map Base
2871 operand immByteMapBase()
2872 %{
2873 // Get base of card map
2874 predicate(BarrierSet::barrier_set()->is_a(BarrierSet::CardTableBarrierSet) &&
2875 SHENANDOAHGC_ONLY(!BarrierSet::barrier_set()->is_a(BarrierSet::ShenandoahBarrierSet) &&)
2876 (CardTable::CardValue*)n->get_ptr() ==
2877 ((CardTableBarrierSet*)(BarrierSet::barrier_set()))->card_table()->byte_map_base());
2878 match(ConP);
2879
2880 op_cost(0);
2881 format %{ %}
2882 interface(CONST_INTER);
2883 %}
2884
2885 // Int Immediate: low 16-bit mask
2886 operand immI_16bits()
2887 %{
2888 predicate(n->get_int() == 0xFFFF);
2889 match(ConI);
2890 op_cost(0);
2891 format %{ %}
2892 interface(CONST_INTER);
2893 %}
2894
2895 operand immIpowerOf2() %{
2896 predicate(is_power_of_2((juint)(n->get_int())));
2897 match(ConI);
2898 op_cost(0);
2899 format %{ %}
2900 interface(CONST_INTER);
2901 %}
2902
2903 // Long Immediate: low 32-bit mask
2904 operand immL_32bits()
2905 %{
2906 predicate(n->get_long() == 0xFFFFFFFFL);
2907 match(ConL);
2908 op_cost(0);
2909 format %{ %}
2910 interface(CONST_INTER);
2911 %}
2912
2913 // 64 bit unit decrement
2914 operand immL_M1()
2915 %{
2916 predicate(n->get_long() == -1);
2917 match(ConL);
2918
2919 op_cost(0);
2920 format %{ %}
2921 interface(CONST_INTER);
2922 %}
2923
2924
2925 // 64 bit integer valid for add immediate
2926 operand immLAdd()
2927 %{
2928 predicate(Assembler::is_simm12(n->get_long()));
2929 match(ConL);
2930 op_cost(0);
2931 format %{ %}
2932 interface(CONST_INTER);
2933 %}
2934
2935 // 64 bit integer valid for sub immediate
2936 operand immLSub()
2937 %{
2938 predicate(Assembler::is_simm12(-(n->get_long())));
2939 match(ConL);
2940 op_cost(0);
2941 format %{ %}
2942 interface(CONST_INTER);
2943 %}
2944
2945 // Narrow pointer operands
2946 // Narrow Pointer Immediate
2947 operand immN()
2948 %{
2949 match(ConN);
2950
2951 op_cost(0);
2952 format %{ %}
2953 interface(CONST_INTER);
2954 %}
2955
2956 // Narrow Null Pointer Immediate
2957 operand immN0()
2958 %{
2959 predicate(n->get_narrowcon() == 0);
2960 match(ConN);
2961
2962 op_cost(0);
2963 format %{ %}
2964 interface(CONST_INTER);
2965 %}
2966
2967 operand immNKlass()
2968 %{
2969 match(ConNKlass);
2970
2971 op_cost(0);
2972 format %{ %}
2973 interface(CONST_INTER);
2974 %}
2975
2976 // Float and Double operands
2977 // Double Immediate
2978 operand immD()
2979 %{
2980 match(ConD);
2981 op_cost(0);
2982 format %{ %}
2983 interface(CONST_INTER);
2984 %}
2985
2986 // Double Immediate: +0.0d
2987 operand immD0()
2988 %{
2989 predicate(jlong_cast(n->getd()) == 0);
2990 match(ConD);
2991
2992 op_cost(0);
2993 format %{ %}
2994 interface(CONST_INTER);
2995 %}
2996
2997 // Float Immediate
2998 operand immF()
2999 %{
3000 match(ConF);
3001 op_cost(0);
3002 format %{ %}
3003 interface(CONST_INTER);
3004 %}
3005
3006 // Float Immediate: +0.0f.
3007 operand immF0()
3008 %{
3009 predicate(jint_cast(n->getf()) == 0);
3010 match(ConF);
3011
3012 op_cost(0);
3013 format %{ %}
3014 interface(CONST_INTER);
3015 %}
3016
3017 // Half Float Immediate
3018 operand immH()
3019 %{
3020 match(ConH);
3021
3022 op_cost(0);
3023 format %{ %}
3024 interface(CONST_INTER);
3025 %}
3026
3027 // Half Float Immediate: +0.0f.
3028 operand immH0()
3029 %{
3030 predicate(jint_cast(n->geth()) == 0);
3031 match(ConH);
3032
3033 op_cost(0);
3034 format %{ %}
3035 interface(CONST_INTER);
3036 %}
3037
3038 operand immIOffset()
3039 %{
3040 predicate(Assembler::is_simm12(n->get_int()));
3041 match(ConI);
3042 op_cost(0);
3043 format %{ %}
3044 interface(CONST_INTER);
3045 %}
3046
3047 operand immLOffset()
3048 %{
3049 predicate(Assembler::is_simm12(n->get_long()));
3050 match(ConL);
3051 op_cost(0);
3052 format %{ %}
3053 interface(CONST_INTER);
3054 %}
3055
3056 // Scale values
3057 operand immIScale()
3058 %{
3059 predicate(1 <= n->get_int() && (n->get_int() <= 3));
3060 match(ConI);
3061
3062 op_cost(0);
3063 format %{ %}
3064 interface(CONST_INTER);
3065 %}
3066
3067 // Integer 32 bit Register Operands
3068 operand iRegI()
3069 %{
3070 constraint(ALLOC_IN_RC(any_reg32));
3071 match(RegI);
3072 match(iRegINoSp);
3073 op_cost(0);
3074 format %{ %}
3075 interface(REG_INTER);
3076 %}
3077
3078 // Integer 32 bit Register not Special
3079 operand iRegINoSp()
3080 %{
3081 constraint(ALLOC_IN_RC(no_special_reg32));
3082 match(RegI);
3083 op_cost(0);
3084 format %{ %}
3085 interface(REG_INTER);
3086 %}
3087
3088 // Register R10 only
3089 operand iRegI_R10()
3090 %{
3091 constraint(ALLOC_IN_RC(int_r10_reg));
3092 match(RegI);
3093 match(iRegINoSp);
3094 op_cost(0);
3095 format %{ %}
3096 interface(REG_INTER);
3097 %}
3098
3099 // Register R12 only
3100 operand iRegI_R12()
3101 %{
3102 constraint(ALLOC_IN_RC(int_r12_reg));
3103 match(RegI);
3104 match(iRegINoSp);
3105 op_cost(0);
3106 format %{ %}
3107 interface(REG_INTER);
3108 %}
3109
3110 // Register R13 only
3111 operand iRegI_R13()
3112 %{
3113 constraint(ALLOC_IN_RC(int_r13_reg));
3114 match(RegI);
3115 match(iRegINoSp);
3116 op_cost(0);
3117 format %{ %}
3118 interface(REG_INTER);
3119 %}
3120
3121 // Register R14 only
3122 operand iRegI_R14()
3123 %{
3124 constraint(ALLOC_IN_RC(int_r14_reg));
3125 match(RegI);
3126 match(iRegINoSp);
3127 op_cost(0);
3128 format %{ %}
3129 interface(REG_INTER);
3130 %}
3131
3132 // Integer 64 bit Register Operands
3133 operand iRegL()
3134 %{
3135 constraint(ALLOC_IN_RC(any_reg));
3136 match(RegL);
3137 match(iRegLNoSp);
3138 op_cost(0);
3139 format %{ %}
3140 interface(REG_INTER);
3141 %}
3142
3143 // Integer 64 bit Register not Special
3144 operand iRegLNoSp()
3145 %{
3146 constraint(ALLOC_IN_RC(no_special_reg));
3147 match(RegL);
3148 match(iRegL_R10);
3149 format %{ %}
3150 interface(REG_INTER);
3151 %}
3152
3153 // Long 64 bit Register R29 only
3154 operand iRegL_R29()
3155 %{
3156 constraint(ALLOC_IN_RC(r29_reg));
3157 match(RegL);
3158 match(iRegLNoSp);
3159 op_cost(0);
3160 format %{ %}
3161 interface(REG_INTER);
3162 %}
3163
3164 // Long 64 bit Register R30 only
3165 operand iRegL_R30()
3166 %{
3167 constraint(ALLOC_IN_RC(r30_reg));
3168 match(RegL);
3169 match(iRegLNoSp);
3170 op_cost(0);
3171 format %{ %}
3172 interface(REG_INTER);
3173 %}
3174
3175 // Pointer Register Operands
3176 // Pointer Register
3177 operand iRegP()
3178 %{
3179 constraint(ALLOC_IN_RC(ptr_reg));
3180 match(RegP);
3181 match(iRegPNoSp);
3182 match(iRegP_R10);
3183 match(iRegP_R15);
3184 match(javaThread_RegP);
3185 op_cost(0);
3186 format %{ %}
3187 interface(REG_INTER);
3188 %}
3189
3190 // Pointer 64 bit Register not Special
3191 operand iRegPNoSp()
3192 %{
3193 constraint(ALLOC_IN_RC(no_special_ptr_reg));
3194 match(RegP);
3195 op_cost(0);
3196 format %{ %}
3197 interface(REG_INTER);
3198 %}
3199
3200 // This operand is not allowed to use fp even if
3201 // fp is not used to hold the frame pointer.
3202 operand iRegPNoSpNoFp()
3203 %{
3204 constraint(ALLOC_IN_RC(no_special_no_fp_ptr_reg));
3205 match(RegP);
3206 match(iRegPNoSp);
3207 op_cost(0);
3208 format %{ %}
3209 interface(REG_INTER);
3210 %}
3211
3212 operand iRegP_R10()
3213 %{
3214 constraint(ALLOC_IN_RC(r10_reg));
3215 match(RegP);
3216 // match(iRegP);
3217 match(iRegPNoSp);
3218 op_cost(0);
3219 format %{ %}
3220 interface(REG_INTER);
3221 %}
3222
3223 // Pointer 64 bit Register R11 only
3224 operand iRegP_R11()
3225 %{
3226 constraint(ALLOC_IN_RC(r11_reg));
3227 match(RegP);
3228 match(iRegPNoSp);
3229 op_cost(0);
3230 format %{ %}
3231 interface(REG_INTER);
3232 %}
3233
3234 operand iRegP_R12()
3235 %{
3236 constraint(ALLOC_IN_RC(r12_reg));
3237 match(RegP);
3238 // match(iRegP);
3239 match(iRegPNoSp);
3240 op_cost(0);
3241 format %{ %}
3242 interface(REG_INTER);
3243 %}
3244
3245 // Pointer 64 bit Register R13 only
3246 operand iRegP_R13()
3247 %{
3248 constraint(ALLOC_IN_RC(r13_reg));
3249 match(RegP);
3250 match(iRegPNoSp);
3251 op_cost(0);
3252 format %{ %}
3253 interface(REG_INTER);
3254 %}
3255
3256 operand iRegP_R14()
3257 %{
3258 constraint(ALLOC_IN_RC(r14_reg));
3259 match(RegP);
3260 // match(iRegP);
3261 match(iRegPNoSp);
3262 op_cost(0);
3263 format %{ %}
3264 interface(REG_INTER);
3265 %}
3266
3267 operand iRegP_R15()
3268 %{
3269 constraint(ALLOC_IN_RC(r15_reg));
3270 match(RegP);
3271 // match(iRegP);
3272 match(iRegPNoSp);
3273 op_cost(0);
3274 format %{ %}
3275 interface(REG_INTER);
3276 %}
3277
3278 operand iRegP_R16()
3279 %{
3280 constraint(ALLOC_IN_RC(r16_reg));
3281 match(RegP);
3282 match(iRegPNoSp);
3283 op_cost(0);
3284 format %{ %}
3285 interface(REG_INTER);
3286 %}
3287
3288 // Pointer 64 bit Register R28 only
3289 operand iRegP_R28()
3290 %{
3291 constraint(ALLOC_IN_RC(r28_reg));
3292 match(RegP);
3293 match(iRegPNoSp);
3294 op_cost(0);
3295 format %{ %}
3296 interface(REG_INTER);
3297 %}
3298
3299 // Pointer 64 bit Register R30 only
3300 operand iRegP_R30()
3301 %{
3302 constraint(ALLOC_IN_RC(r30_reg));
3303 match(RegP);
3304 match(iRegPNoSp);
3305 op_cost(0);
3306 format %{ %}
3307 interface(REG_INTER);
3308 %}
3309
3310 // Pointer 64 bit Register R31 only
3311 operand iRegP_R31()
3312 %{
3313 constraint(ALLOC_IN_RC(r31_reg));
3314 match(RegP);
3315 match(iRegPNoSp);
3316 op_cost(0);
3317 format %{ %}
3318 interface(REG_INTER);
3319 %}
3320
3321 // Pointer Register Operands
3322 // Narrow Pointer Register
3323 operand iRegN()
3324 %{
3325 constraint(ALLOC_IN_RC(any_reg32));
3326 match(RegN);
3327 match(iRegNNoSp);
3328 op_cost(0);
3329 format %{ %}
3330 interface(REG_INTER);
3331 %}
3332
3333 // Integer 64 bit Register not Special
3334 operand iRegNNoSp()
3335 %{
3336 constraint(ALLOC_IN_RC(no_special_reg32));
3337 match(RegN);
3338 op_cost(0);
3339 format %{ %}
3340 interface(REG_INTER);
3341 %}
3342
3343 // Long 64 bit Register R10 only
3344 operand iRegL_R10()
3345 %{
3346 constraint(ALLOC_IN_RC(r10_reg));
3347 match(RegL);
3348 match(iRegLNoSp);
3349 op_cost(0);
3350 format %{ %}
3351 interface(REG_INTER);
3352 %}
3353
3354 // Float Register
3355 // Float register operands
3356 operand fRegF()
3357 %{
3358 constraint(ALLOC_IN_RC(float_reg));
3359 match(RegF);
3360
3361 op_cost(0);
3362 format %{ %}
3363 interface(REG_INTER);
3364 %}
3365
3366 // Double Register
3367 // Double register operands
3368 operand fRegD()
3369 %{
3370 constraint(ALLOC_IN_RC(double_reg));
3371 match(RegD);
3372
3373 op_cost(0);
3374 format %{ %}
3375 interface(REG_INTER);
3376 %}
3377
3378 // Generic vector class. This will be used for
3379 // all vector operands.
3380 operand vReg()
3381 %{
3382 constraint(ALLOC_IN_RC(vectora_reg));
3383 match(VecA);
3384 op_cost(0);
3385 format %{ %}
3386 interface(REG_INTER);
3387 %}
3388
3389 operand vReg_V1()
3390 %{
3391 constraint(ALLOC_IN_RC(v1_reg));
3392 match(VecA);
3393 match(vReg);
3394 op_cost(0);
3395 format %{ %}
3396 interface(REG_INTER);
3397 %}
3398
3399 operand vReg_V2()
3400 %{
3401 constraint(ALLOC_IN_RC(v2_reg));
3402 match(VecA);
3403 match(vReg);
3404 op_cost(0);
3405 format %{ %}
3406 interface(REG_INTER);
3407 %}
3408
3409 operand vReg_V3()
3410 %{
3411 constraint(ALLOC_IN_RC(v3_reg));
3412 match(VecA);
3413 match(vReg);
3414 op_cost(0);
3415 format %{ %}
3416 interface(REG_INTER);
3417 %}
3418
3419 operand vReg_V4()
3420 %{
3421 constraint(ALLOC_IN_RC(v4_reg));
3422 match(VecA);
3423 match(vReg);
3424 op_cost(0);
3425 format %{ %}
3426 interface(REG_INTER);
3427 %}
3428
3429 operand vReg_V5()
3430 %{
3431 constraint(ALLOC_IN_RC(v5_reg));
3432 match(VecA);
3433 match(vReg);
3434 op_cost(0);
3435 format %{ %}
3436 interface(REG_INTER);
3437 %}
3438
3439 operand vReg_V6()
3440 %{
3441 constraint(ALLOC_IN_RC(v6_reg));
3442 match(VecA);
3443 match(vReg);
3444 op_cost(0);
3445 format %{ %}
3446 interface(REG_INTER);
3447 %}
3448
3449 operand vReg_V7()
3450 %{
3451 constraint(ALLOC_IN_RC(v7_reg));
3452 match(VecA);
3453 match(vReg);
3454 op_cost(0);
3455 format %{ %}
3456 interface(REG_INTER);
3457 %}
3458
3459 operand vReg_V8()
3460 %{
3461 constraint(ALLOC_IN_RC(v8_reg));
3462 match(VecA);
3463 match(vReg);
3464 op_cost(0);
3465 format %{ %}
3466 interface(REG_INTER);
3467 %}
3468
3469 operand vReg_V9()
3470 %{
3471 constraint(ALLOC_IN_RC(v9_reg));
3472 match(VecA);
3473 match(vReg);
3474 op_cost(0);
3475 format %{ %}
3476 interface(REG_INTER);
3477 %}
3478
3479 operand vReg_V10()
3480 %{
3481 constraint(ALLOC_IN_RC(v10_reg));
3482 match(VecA);
3483 match(vReg);
3484 op_cost(0);
3485 format %{ %}
3486 interface(REG_INTER);
3487 %}
3488
3489 operand vReg_V11()
3490 %{
3491 constraint(ALLOC_IN_RC(v11_reg));
3492 match(VecA);
3493 match(vReg);
3494 op_cost(0);
3495 format %{ %}
3496 interface(REG_INTER);
3497 %}
3498
3499 operand vRegMask()
3500 %{
3501 constraint(ALLOC_IN_RC(vmask_reg));
3502 match(RegVectMask);
3503 match(vRegMask_V0);
3504 op_cost(0);
3505 format %{ %}
3506 interface(REG_INTER);
3507 %}
3508
3509 // The mask value used to control execution of a masked
3510 // vector instruction is always supplied by vector register v0.
3511 operand vRegMask_V0()
3512 %{
3513 constraint(ALLOC_IN_RC(vmask_reg_v0));
3514 match(RegVectMask);
3515 match(vRegMask);
3516 op_cost(0);
3517 format %{ %}
3518 interface(REG_INTER);
3519 %}
3520
3521 // Java Thread Register
3522 operand javaThread_RegP(iRegP reg)
3523 %{
3524 constraint(ALLOC_IN_RC(java_thread_reg)); // java_thread_reg
3525 match(reg);
3526 op_cost(0);
3527 format %{ %}
3528 interface(REG_INTER);
3529 %}
3530
3531 //----------Memory Operands----------------------------------------------------
3532 // RISCV has only base_plus_offset and literal address mode, so no need to use
3533 // index and scale. Here set index as 0xffffffff and scale as 0x0.
3534 operand indirect(iRegP reg)
3535 %{
3536 constraint(ALLOC_IN_RC(ptr_reg));
3537 match(reg);
3538 op_cost(0);
3539 format %{ "[$reg]" %}
3540 interface(MEMORY_INTER) %{
3541 base($reg);
3542 index(0xffffffff);
3543 scale(0x0);
3544 disp(0x0);
3545 %}
3546 %}
3547
3548 operand indOffI(iRegP reg, immIOffset off)
3549 %{
3550 constraint(ALLOC_IN_RC(ptr_reg));
3551 match(AddP reg off);
3552 op_cost(0);
3553 format %{ "[$reg, $off]" %}
3554 interface(MEMORY_INTER) %{
3555 base($reg);
3556 index(0xffffffff);
3557 scale(0x0);
3558 disp($off);
3559 %}
3560 %}
3561
3562 operand indOffL(iRegP reg, immLOffset off)
3563 %{
3564 constraint(ALLOC_IN_RC(ptr_reg));
3565 match(AddP reg off);
3566 op_cost(0);
3567 format %{ "[$reg, $off]" %}
3568 interface(MEMORY_INTER) %{
3569 base($reg);
3570 index(0xffffffff);
3571 scale(0x0);
3572 disp($off);
3573 %}
3574 %}
3575
3576 operand indirectN(iRegN reg)
3577 %{
3578 predicate(CompressedOops::shift() == 0);
3579 constraint(ALLOC_IN_RC(ptr_reg));
3580 match(DecodeN reg);
3581 op_cost(0);
3582 format %{ "[$reg]\t# narrow" %}
3583 interface(MEMORY_INTER) %{
3584 base($reg);
3585 index(0xffffffff);
3586 scale(0x0);
3587 disp(0x0);
3588 %}
3589 %}
3590
3591 operand indOffIN(iRegN reg, immIOffset off)
3592 %{
3593 predicate(CompressedOops::shift() == 0);
3594 constraint(ALLOC_IN_RC(ptr_reg));
3595 match(AddP (DecodeN reg) off);
3596 op_cost(0);
3597 format %{ "[$reg, $off]\t# narrow" %}
3598 interface(MEMORY_INTER) %{
3599 base($reg);
3600 index(0xffffffff);
3601 scale(0x0);
3602 disp($off);
3603 %}
3604 %}
3605
3606 operand indOffLN(iRegN reg, immLOffset off)
3607 %{
3608 predicate(CompressedOops::shift() == 0);
3609 constraint(ALLOC_IN_RC(ptr_reg));
3610 match(AddP (DecodeN reg) off);
3611 op_cost(0);
3612 format %{ "[$reg, $off]\t# narrow" %}
3613 interface(MEMORY_INTER) %{
3614 base($reg);
3615 index(0xffffffff);
3616 scale(0x0);
3617 disp($off);
3618 %}
3619 %}
3620
3621 //----------Special Memory Operands--------------------------------------------
3622 // Stack Slot Operand - This operand is used for loading and storing temporary
3623 // values on the stack where a match requires a value to
3624 // flow through memory.
3625 operand stackSlotI(sRegI reg)
3626 %{
3627 constraint(ALLOC_IN_RC(stack_slots));
3628 // No match rule because this operand is only generated in matching
3629 // match(RegI);
3630 format %{ "[$reg]" %}
3631 interface(MEMORY_INTER) %{
3632 base(0x02); // RSP
3633 index(0xffffffff); // No Index
3634 scale(0x0); // No Scale
3635 disp($reg); // Stack Offset
3636 %}
3637 %}
3638
3639 operand stackSlotF(sRegF reg)
3640 %{
3641 constraint(ALLOC_IN_RC(stack_slots));
3642 // No match rule because this operand is only generated in matching
3643 // match(RegF);
3644 format %{ "[$reg]" %}
3645 interface(MEMORY_INTER) %{
3646 base(0x02); // RSP
3647 index(0xffffffff); // No Index
3648 scale(0x0); // No Scale
3649 disp($reg); // Stack Offset
3650 %}
3651 %}
3652
3653 operand stackSlotD(sRegD reg)
3654 %{
3655 constraint(ALLOC_IN_RC(stack_slots));
3656 // No match rule because this operand is only generated in matching
3657 // match(RegD);
3658 format %{ "[$reg]" %}
3659 interface(MEMORY_INTER) %{
3660 base(0x02); // RSP
3661 index(0xffffffff); // No Index
3662 scale(0x0); // No Scale
3663 disp($reg); // Stack Offset
3664 %}
3665 %}
3666
3667 operand stackSlotL(sRegL reg)
3668 %{
3669 constraint(ALLOC_IN_RC(stack_slots));
3670 // No match rule because this operand is only generated in matching
3671 // match(RegL);
3672 format %{ "[$reg]" %}
3673 interface(MEMORY_INTER) %{
3674 base(0x02); // RSP
3675 index(0xffffffff); // No Index
3676 scale(0x0); // No Scale
3677 disp($reg); // Stack Offset
3678 %}
3679 %}
3680
3681 // Special operand allowing long args to int ops to be truncated for free
3682
3683 operand iRegL2I(iRegL reg) %{
3684
3685 op_cost(0);
3686
3687 match(ConvL2I reg);
3688
3689 format %{ "l2i($reg)" %}
3690
3691 interface(REG_INTER)
3692 %}
3693
3694
3695 // Comparison Operands
3696 // NOTE: Label is a predefined operand which should not be redefined in
3697 // the AD file. It is generically handled within the ADLC.
3698
3699 //----------Conditional Branch Operands----------------------------------------
3700 // Comparison Op - This is the operation of the comparison, and is limited to
3701 // the following set of codes:
3702 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
3703 //
3704 // Other attributes of the comparison, such as unsignedness, are specified
3705 // by the comparison instruction that sets a condition code flags register.
3706 // That result is represented by a flags operand whose subtype is appropriate
3707 // to the unsignedness (etc.) of the comparison.
3708 //
3709 // Later, the instruction which matches both the Comparison Op (a Bool) and
3710 // the flags (produced by the Cmp) specifies the coding of the comparison op
3711 // by matching a specific subtype of Bool operand below, such as cmpOpU.
3712
3713
3714 // used for signed integral comparisons and fp comparisons
3715 operand cmpOp()
3716 %{
3717 match(Bool);
3718
3719 format %{ "" %}
3720
3721 // the values in interface derives from struct BoolTest::mask
3722 interface(COND_INTER) %{
3723 equal(0x0, "eq");
3724 greater(0x1, "gt");
3725 overflow(0x2, "overflow");
3726 less(0x3, "lt");
3727 not_equal(0x4, "ne");
3728 less_equal(0x5, "le");
3729 no_overflow(0x6, "no_overflow");
3730 greater_equal(0x7, "ge");
3731 %}
3732 %}
3733
3734 // used for unsigned integral comparisons
3735 operand cmpOpU()
3736 %{
3737 match(Bool);
3738
3739 format %{ "" %}
3740 // the values in interface derives from struct BoolTest::mask
3741 interface(COND_INTER) %{
3742 equal(0x0, "eq");
3743 greater(0x1, "gtu");
3744 overflow(0x2, "overflow");
3745 less(0x3, "ltu");
3746 not_equal(0x4, "ne");
3747 less_equal(0x5, "leu");
3748 no_overflow(0x6, "no_overflow");
3749 greater_equal(0x7, "geu");
3750 %}
3751 %}
3752
3753 // used for certain integral comparisons which can be
3754 // converted to bxx instructions
3755 operand cmpOpEqNe()
3756 %{
3757 match(Bool);
3758 op_cost(0);
3759 predicate(n->as_Bool()->_test._test == BoolTest::ne ||
3760 n->as_Bool()->_test._test == BoolTest::eq);
3761
3762 format %{ "" %}
3763 interface(COND_INTER) %{
3764 equal(0x0, "eq");
3765 greater(0x1, "gt");
3766 overflow(0x2, "overflow");
3767 less(0x3, "lt");
3768 not_equal(0x4, "ne");
3769 less_equal(0x5, "le");
3770 no_overflow(0x6, "no_overflow");
3771 greater_equal(0x7, "ge");
3772 %}
3773 %}
3774
3775 operand cmpOpULtGe()
3776 %{
3777 match(Bool);
3778 op_cost(0);
3779 predicate(n->as_Bool()->_test._test == BoolTest::lt ||
3780 n->as_Bool()->_test._test == BoolTest::ge);
3781
3782 format %{ "" %}
3783 interface(COND_INTER) %{
3784 equal(0x0, "eq");
3785 greater(0x1, "gtu");
3786 overflow(0x2, "overflow");
3787 less(0x3, "ltu");
3788 not_equal(0x4, "ne");
3789 less_equal(0x5, "leu");
3790 no_overflow(0x6, "no_overflow");
3791 greater_equal(0x7, "geu");
3792 %}
3793 %}
3794
3795 operand cmpOpUEqNeLeGt()
3796 %{
3797 match(Bool);
3798 op_cost(0);
3799 predicate(n->as_Bool()->_test._test == BoolTest::ne ||
3800 n->as_Bool()->_test._test == BoolTest::eq ||
3801 n->as_Bool()->_test._test == BoolTest::le ||
3802 n->as_Bool()->_test._test == BoolTest::gt);
3803
3804 format %{ "" %}
3805 interface(COND_INTER) %{
3806 equal(0x0, "eq");
3807 greater(0x1, "gtu");
3808 overflow(0x2, "overflow");
3809 less(0x3, "ltu");
3810 not_equal(0x4, "ne");
3811 less_equal(0x5, "leu");
3812 no_overflow(0x6, "no_overflow");
3813 greater_equal(0x7, "geu");
3814 %}
3815 %}
3816
3817
3818 // Flags register, used as output of compare logic
3819 operand rFlagsReg()
3820 %{
3821 constraint(ALLOC_IN_RC(reg_flags));
3822 match(RegFlags);
3823
3824 op_cost(0);
3825 format %{ "RFLAGS" %}
3826 interface(REG_INTER);
3827 %}
3828
3829 // Special Registers
3830
3831 // Method Register
3832 operand inline_cache_RegP(iRegP reg)
3833 %{
3834 constraint(ALLOC_IN_RC(method_reg)); // inline_cache_reg
3835 match(reg);
3836 match(iRegPNoSp);
3837 op_cost(0);
3838 format %{ %}
3839 interface(REG_INTER);
3840 %}
3841
3842 //----------OPERAND CLASSES----------------------------------------------------
3843 // Operand Classes are groups of operands that are used as to simplify
3844 // instruction definitions by not requiring the AD writer to specify
3845 // separate instructions for every form of operand when the
3846 // instruction accepts multiple operand types with the same basic
3847 // encoding and format. The classic case of this is memory operands.
3848
3849 // memory is used to define read/write location for load/store
3850 // instruction defs. we can turn a memory op into an Address
3851
3852 opclass memory(indirect, indOffI, indOffL, indirectN, indOffIN, indOffLN);
3853
3854 // iRegIorL2I is used for src inputs in rules for 32 bit int (I)
3855 // operations. it allows the src to be either an iRegI or a (ConvL2I
3856 // iRegL). in the latter case the l2i normally planted for a ConvL2I
3857 // can be elided because the 32-bit instruction will just employ the
3858 // lower 32 bits anyway.
3859 //
3860 // n.b. this does not elide all L2I conversions. if the truncated
3861 // value is consumed by more than one operation then the ConvL2I
3862 // cannot be bundled into the consuming nodes so an l2i gets planted
3863 // (actually an addiw $dst, $src, 0) and the downstream instructions
3864 // consume the result of the L2I as an iRegI input. That's a shame since
3865 // the addiw is actually redundant but its not too costly.
3866
3867 opclass iRegIorL2I(iRegI, iRegL2I);
3868 opclass iRegIorL(iRegI, iRegL);
3869 opclass iRegNorP(iRegN, iRegP);
3870 opclass iRegILNP(iRegI, iRegL, iRegN, iRegP);
3871 opclass iRegILNPNoSp(iRegINoSp, iRegLNoSp, iRegNNoSp, iRegPNoSp);
3872 opclass immIorL(immI, immL);
3873
3874 //----------PIPELINE-----------------------------------------------------------
3875 // Rules which define the behavior of the target architectures pipeline.
3876
3877 // For specific pipelines, e.g. generic RISC-V, define the stages of that pipeline
3878 //pipe_desc(ID, EX, MEM, WR);
3879 #define ID S0
3880 #define EX S1
3881 #define MEM S2
3882 #define WR S3
3883
3884 // Integer ALU reg operation
3885 pipeline %{
3886
3887 attributes %{
3888 // RISC-V instructions are of fixed length
3889 fixed_size_instructions; // Fixed size instructions TODO does
3890 max_instructions_per_bundle = 2; // Generic RISC-V 1, Sifive Series 7 2
3891 // RISC-V instructions come in 32-bit word units
3892 instruction_unit_size = 4; // An instruction is 4 bytes long
3893 instruction_fetch_unit_size = 64; // The processor fetches one line
3894 instruction_fetch_units = 1; // of 64 bytes
3895
3896 // List of nop instructions
3897 nops( MachNop );
3898 %}
3899
3900 // We don't use an actual pipeline model so don't care about resources
3901 // or description. we do use pipeline classes to introduce fixed
3902 // latencies
3903
3904 //----------RESOURCES----------------------------------------------------------
3905 // Resources are the functional units available to the machine
3906
3907 // Generic RISC-V pipeline
3908 // 1 decoder
3909 // 1 instruction decoded per cycle
3910 // 1 load/store ops per cycle, 1 branch, 1 FPU
3911 // 1 mul, 1 div
3912
3913 resources ( DECODE,
3914 ALU,
3915 MUL,
3916 DIV,
3917 BRANCH,
3918 LDST,
3919 FPU);
3920
3921 //----------PIPELINE DESCRIPTION-----------------------------------------------
3922 // Pipeline Description specifies the stages in the machine's pipeline
3923
3924 // Define the pipeline as a generic 6 stage pipeline
3925 pipe_desc(S0, S1, S2, S3, S4, S5);
3926
3927 //----------PIPELINE CLASSES---------------------------------------------------
3928 // Pipeline Classes describe the stages in which input and output are
3929 // referenced by the hardware pipeline.
3930
3931 pipe_class fp_dop_reg_reg_s(fRegF dst, fRegF src1, fRegF src2)
3932 %{
3933 single_instruction;
3934 src1 : S1(read);
3935 src2 : S2(read);
3936 dst : S5(write);
3937 DECODE : ID;
3938 FPU : S5;
3939 %}
3940
3941 pipe_class fp_dop_reg_reg_d(fRegD dst, fRegD src1, fRegD src2)
3942 %{
3943 src1 : S1(read);
3944 src2 : S2(read);
3945 dst : S5(write);
3946 DECODE : ID;
3947 FPU : S5;
3948 %}
3949
3950 pipe_class fp_uop_s(fRegF dst, fRegF src)
3951 %{
3952 single_instruction;
3953 src : S1(read);
3954 dst : S5(write);
3955 DECODE : ID;
3956 FPU : S5;
3957 %}
3958
3959 pipe_class fp_uop_d(fRegD dst, fRegD src)
3960 %{
3961 single_instruction;
3962 src : S1(read);
3963 dst : S5(write);
3964 DECODE : ID;
3965 FPU : S5;
3966 %}
3967
3968 pipe_class fp_d2f(fRegF dst, fRegD src)
3969 %{
3970 single_instruction;
3971 src : S1(read);
3972 dst : S5(write);
3973 DECODE : ID;
3974 FPU : S5;
3975 %}
3976
3977 pipe_class fp_f2d(fRegD dst, fRegF src)
3978 %{
3979 single_instruction;
3980 src : S1(read);
3981 dst : S5(write);
3982 DECODE : ID;
3983 FPU : S5;
3984 %}
3985
3986 pipe_class fp_f2i(iRegINoSp dst, fRegF src)
3987 %{
3988 single_instruction;
3989 src : S1(read);
3990 dst : S5(write);
3991 DECODE : ID;
3992 FPU : S5;
3993 %}
3994
3995 pipe_class fp_f2l(iRegLNoSp dst, fRegF src)
3996 %{
3997 single_instruction;
3998 src : S1(read);
3999 dst : S5(write);
4000 DECODE : ID;
4001 FPU : S5;
4002 %}
4003
4004 pipe_class fp_i2f(fRegF dst, iRegIorL2I src)
4005 %{
4006 single_instruction;
4007 src : S1(read);
4008 dst : S5(write);
4009 DECODE : ID;
4010 FPU : S5;
4011 %}
4012
4013 pipe_class fp_l2f(fRegF dst, iRegL src)
4014 %{
4015 single_instruction;
4016 src : S1(read);
4017 dst : S5(write);
4018 DECODE : ID;
4019 FPU : S5;
4020 %}
4021
4022 pipe_class fp_d2i(iRegINoSp dst, fRegD src)
4023 %{
4024 single_instruction;
4025 src : S1(read);
4026 dst : S5(write);
4027 DECODE : ID;
4028 FPU : S5;
4029 %}
4030
4031 pipe_class fp_d2l(iRegLNoSp dst, fRegD src)
4032 %{
4033 single_instruction;
4034 src : S1(read);
4035 dst : S5(write);
4036 DECODE : ID;
4037 FPU : S5;
4038 %}
4039
4040 pipe_class fp_i2d(fRegD dst, iRegIorL2I src)
4041 %{
4042 single_instruction;
4043 src : S1(read);
4044 dst : S5(write);
4045 DECODE : ID;
4046 FPU : S5;
4047 %}
4048
4049 pipe_class fp_l2d(fRegD dst, iRegIorL2I src)
4050 %{
4051 single_instruction;
4052 src : S1(read);
4053 dst : S5(write);
4054 DECODE : ID;
4055 FPU : S5;
4056 %}
4057
4058 pipe_class fp_div_s(fRegF dst, fRegF src1, fRegF src2)
4059 %{
4060 single_instruction;
4061 src1 : S1(read);
4062 src2 : S2(read);
4063 dst : S5(write);
4064 DECODE : ID;
4065 FPU : S5;
4066 %}
4067
4068 pipe_class fp_div_d(fRegD dst, fRegD src1, fRegD src2)
4069 %{
4070 single_instruction;
4071 src1 : S1(read);
4072 src2 : S2(read);
4073 dst : S5(write);
4074 DECODE : ID;
4075 FPU : S5;
4076 %}
4077
4078 pipe_class fp_sqrt_s(fRegF dst, fRegF src)
4079 %{
4080 single_instruction;
4081 src : S1(read);
4082 dst : S5(write);
4083 DECODE : ID;
4084 FPU : S5;
4085 %}
4086
4087 pipe_class fp_sqrt_d(fRegD dst, fRegD src)
4088 %{
4089 single_instruction;
4090 src : S1(read);
4091 dst : S5(write);
4092 DECODE : ID;
4093 FPU : S5;
4094 %}
4095
4096 pipe_class fp_load_constant_s(fRegF dst)
4097 %{
4098 single_instruction;
4099 dst : S5(write);
4100 DECODE : ID;
4101 FPU : S5;
4102 %}
4103
4104 pipe_class fp_load_constant_d(fRegD dst)
4105 %{
4106 single_instruction;
4107 dst : S5(write);
4108 DECODE : ID;
4109 FPU : S5;
4110 %}
4111
4112 pipe_class fp_load_mem_s(fRegF dst, memory mem)
4113 %{
4114 single_instruction;
4115 mem : S1(read);
4116 dst : S5(write);
4117 DECODE : ID;
4118 LDST : MEM;
4119 %}
4120
4121 pipe_class fp_load_mem_d(fRegD dst, memory mem)
4122 %{
4123 single_instruction;
4124 mem : S1(read);
4125 dst : S5(write);
4126 DECODE : ID;
4127 LDST : MEM;
4128 %}
4129
4130 pipe_class fp_store_reg_s(fRegF src, memory mem)
4131 %{
4132 single_instruction;
4133 src : S1(read);
4134 mem : S5(write);
4135 DECODE : ID;
4136 LDST : MEM;
4137 %}
4138
4139 pipe_class fp_store_reg_d(fRegD src, memory mem)
4140 %{
4141 single_instruction;
4142 src : S1(read);
4143 mem : S5(write);
4144 DECODE : ID;
4145 LDST : MEM;
4146 %}
4147
4148 //------- Integer ALU operations --------------------------
4149
4150 // Integer ALU reg-reg operation
4151 // Operands needs in ID, result generated in EX
4152 // E.g. ADD Rd, Rs1, Rs2
4153 pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2)
4154 %{
4155 single_instruction;
4156 dst : EX(write);
4157 src1 : ID(read);
4158 src2 : ID(read);
4159 DECODE : ID;
4160 ALU : EX;
4161 %}
4162
4163 // Integer ALU reg operation with constant shift
4164 // E.g. SLLI Rd, Rs1, #shift
4165 pipe_class ialu_reg_shift(iRegI dst, iRegI src1)
4166 %{
4167 single_instruction;
4168 dst : EX(write);
4169 src1 : ID(read);
4170 DECODE : ID;
4171 ALU : EX;
4172 %}
4173
4174 // Integer ALU reg-reg operation with variable shift
4175 // both operands must be available in ID
4176 // E.g. SLL Rd, Rs1, Rs2
4177 pipe_class ialu_reg_reg_vshift(iRegI dst, iRegI src1, iRegI src2)
4178 %{
4179 single_instruction;
4180 dst : EX(write);
4181 src1 : ID(read);
4182 src2 : ID(read);
4183 DECODE : ID;
4184 ALU : EX;
4185 %}
4186
4187 // Integer ALU reg operation
4188 // E.g. NEG Rd, Rs2
4189 pipe_class ialu_reg(iRegI dst, iRegI src)
4190 %{
4191 single_instruction;
4192 dst : EX(write);
4193 src : ID(read);
4194 DECODE : ID;
4195 ALU : EX;
4196 %}
4197
4198 // Integer ALU reg immediate operation
4199 // E.g. ADDI Rd, Rs1, #imm
4200 pipe_class ialu_reg_imm(iRegI dst, iRegI src1)
4201 %{
4202 single_instruction;
4203 dst : EX(write);
4204 src1 : ID(read);
4205 DECODE : ID;
4206 ALU : EX;
4207 %}
4208
4209 // Integer ALU immediate operation (no source operands)
4210 // E.g. LI Rd, #imm
4211 pipe_class ialu_imm(iRegI dst)
4212 %{
4213 single_instruction;
4214 dst : EX(write);
4215 DECODE : ID;
4216 ALU : EX;
4217 %}
4218
4219 //------- Multiply pipeline operations --------------------
4220
4221 // Multiply reg-reg
4222 // E.g. MULW Rd, Rs1, Rs2
4223 pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2)
4224 %{
4225 single_instruction;
4226 dst : WR(write);
4227 src1 : ID(read);
4228 src2 : ID(read);
4229 DECODE : ID;
4230 MUL : WR;
4231 %}
4232
4233 // E.g. MUL RD, Rs1, Rs2
4234 pipe_class lmul_reg_reg(iRegL dst, iRegL src1, iRegL src2)
4235 %{
4236 single_instruction;
4237 fixed_latency(3); // Maximum latency for 64 bit mul
4238 dst : WR(write);
4239 src1 : ID(read);
4240 src2 : ID(read);
4241 DECODE : ID;
4242 MUL : WR;
4243 %}
4244
4245 //------- Divide pipeline operations --------------------
4246
4247 // E.g. DIVW Rd, Rs1, Rs2
4248 pipe_class idiv_reg_reg(iRegI dst, iRegI src1, iRegI src2)
4249 %{
4250 single_instruction;
4251 fixed_latency(8); // Maximum latency for 32 bit divide
4252 dst : WR(write);
4253 src1 : ID(read);
4254 src2 : ID(read);
4255 DECODE : ID;
4256 DIV : WR;
4257 %}
4258
4259 // E.g. DIV RD, Rs1, Rs2
4260 pipe_class ldiv_reg_reg(iRegL dst, iRegL src1, iRegL src2)
4261 %{
4262 single_instruction;
4263 fixed_latency(16); // Maximum latency for 64 bit divide
4264 dst : WR(write);
4265 src1 : ID(read);
4266 src2 : ID(read);
4267 DECODE : ID;
4268 DIV : WR;
4269 %}
4270
4271 //------- Load pipeline operations ------------------------
4272
4273 // Load - prefetch
4274 // Eg. PREFETCH_W mem
4275 pipe_class iload_prefetch(memory mem)
4276 %{
4277 single_instruction;
4278 mem : ID(read);
4279 DECODE : ID;
4280 LDST : MEM;
4281 %}
4282
4283 // Load - reg, mem
4284 // E.g. LA Rd, mem
4285 pipe_class iload_reg_mem(iRegI dst, memory mem)
4286 %{
4287 single_instruction;
4288 dst : WR(write);
4289 mem : ID(read);
4290 DECODE : ID;
4291 LDST : MEM;
4292 %}
4293
4294 // Load - reg, reg
4295 // E.g. LD Rd, Rs
4296 pipe_class iload_reg_reg(iRegI dst, iRegI src)
4297 %{
4298 single_instruction;
4299 dst : WR(write);
4300 src : ID(read);
4301 DECODE : ID;
4302 LDST : MEM;
4303 %}
4304
4305 //------- Store pipeline operations -----------------------
4306
4307 // Store - zr, mem
4308 // E.g. SD zr, mem
4309 pipe_class istore_mem(memory mem)
4310 %{
4311 single_instruction;
4312 mem : ID(read);
4313 DECODE : ID;
4314 LDST : MEM;
4315 %}
4316
4317 // Store - reg, mem
4318 // E.g. SD Rs, mem
4319 pipe_class istore_reg_mem(iRegI src, memory mem)
4320 %{
4321 single_instruction;
4322 mem : ID(read);
4323 src : EX(read);
4324 DECODE : ID;
4325 LDST : MEM;
4326 %}
4327
4328 // Store - reg, reg
4329 // E.g. SD Rs2, Rs1
4330 pipe_class istore_reg_reg(iRegI dst, iRegI src)
4331 %{
4332 single_instruction;
4333 dst : ID(read);
4334 src : EX(read);
4335 DECODE : ID;
4336 LDST : MEM;
4337 %}
4338
4339 //------- Control transfer pipeline operations ------------
4340
4341 // Branch
4342 pipe_class pipe_branch()
4343 %{
4344 single_instruction;
4345 DECODE : ID;
4346 BRANCH : EX;
4347 %}
4348
4349 // Branch
4350 pipe_class pipe_branch_reg(iRegI src)
4351 %{
4352 single_instruction;
4353 src : ID(read);
4354 DECODE : ID;
4355 BRANCH : EX;
4356 %}
4357
4358 // Compare & Branch
4359 // E.g. BEQ Rs1, Rs2, L
4360 pipe_class pipe_cmp_branch(iRegI src1, iRegI src2)
4361 %{
4362 single_instruction;
4363 src1 : ID(read);
4364 src2 : ID(read);
4365 DECODE : ID;
4366 BRANCH : EX;
4367 %}
4368
4369 // E.g. BEQZ Rs, L
4370 pipe_class pipe_cmpz_branch(iRegI src)
4371 %{
4372 single_instruction;
4373 src : ID(read);
4374 DECODE : ID;
4375 BRANCH : EX;
4376 %}
4377
4378 //------- Synchronisation operations ----------------------
4379 // Any operation requiring serialization
4380 // E.g. FENCE/Atomic Ops/Load Acquire/Store Release
4381 pipe_class pipe_serial()
4382 %{
4383 single_instruction;
4384 force_serialization;
4385 fixed_latency(16);
4386 DECODE : ID;
4387 LDST : MEM;
4388 %}
4389
4390 pipe_class pipe_slow()
4391 %{
4392 instruction_count(10);
4393 multiple_bundles;
4394 force_serialization;
4395 fixed_latency(16);
4396 DECODE : ID;
4397 LDST : MEM;
4398 %}
4399
4400 // Empty pipeline class
4401 pipe_class pipe_class_empty()
4402 %{
4403 single_instruction;
4404 fixed_latency(0);
4405 %}
4406
4407 // Default pipeline class.
4408 pipe_class pipe_class_default()
4409 %{
4410 single_instruction;
4411 fixed_latency(2);
4412 %}
4413
4414 // Pipeline class for compares.
4415 pipe_class pipe_class_compare()
4416 %{
4417 single_instruction;
4418 fixed_latency(16);
4419 %}
4420
4421 // Pipeline class for memory operations.
4422 pipe_class pipe_class_memory()
4423 %{
4424 single_instruction;
4425 fixed_latency(16);
4426 %}
4427
4428 // Pipeline class for call.
4429 pipe_class pipe_class_call()
4430 %{
4431 single_instruction;
4432 fixed_latency(100);
4433 %}
4434
4435 // Define the class for the Nop node.
4436 define %{
4437 MachNop = pipe_class_empty;
4438 %}
4439 %}
4440 //----------INSTRUCTIONS-------------------------------------------------------
4441 //
4442 // match -- States which machine-independent subtree may be replaced
4443 // by this instruction.
4444 // ins_cost -- The estimated cost of this instruction is used by instruction
4445 // selection to identify a minimum cost tree of machine
4446 // instructions that matches a tree of machine-independent
4447 // instructions.
4448 // format -- A string providing the disassembly for this instruction.
4449 // The value of an instruction's operand may be inserted
4450 // by referring to it with a '$' prefix.
4451 // opcode -- Three instruction opcodes may be provided. These are referred
4452 // to within an encode class as $primary, $secondary, and $tertiary
4453 // rrspectively. The primary opcode is commonly used to
4454 // indicate the type of machine instruction, while secondary
4455 // and tertiary are often used for prefix options or addressing
4456 // modes.
4457 // ins_encode -- A list of encode classes with parameters. The encode class
4458 // name must have been defined in an 'enc_class' specification
4459 // in the encode section of the architecture description.
4460
4461 // ============================================================================
4462 // Memory (Load/Store) Instructions
4463
4464 // Load Instructions
4465
4466 // Load Byte (8 bit signed)
4467 instruct loadB(iRegINoSp dst, memory mem)
4468 %{
4469 match(Set dst (LoadB mem));
4470
4471 ins_cost(LOAD_COST);
4472 format %{ "lb $dst, $mem\t# byte, #@loadB" %}
4473
4474 ins_encode %{
4475 __ lb(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4476 %}
4477
4478 ins_pipe(iload_reg_mem);
4479 %}
4480
4481 // Load Byte (8 bit signed) into long
4482 instruct loadB2L(iRegLNoSp dst, memory mem)
4483 %{
4484 match(Set dst (ConvI2L (LoadB mem)));
4485
4486 ins_cost(LOAD_COST);
4487 format %{ "lb $dst, $mem\t# byte, #@loadB2L" %}
4488
4489 ins_encode %{
4490 __ lb(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4491 %}
4492
4493 ins_pipe(iload_reg_mem);
4494 %}
4495
4496 // Load Byte (8 bit unsigned)
4497 instruct loadUB(iRegINoSp dst, memory mem)
4498 %{
4499 match(Set dst (LoadUB mem));
4500
4501 ins_cost(LOAD_COST);
4502 format %{ "lbu $dst, $mem\t# byte, #@loadUB" %}
4503
4504 ins_encode %{
4505 __ lbu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4506 %}
4507
4508 ins_pipe(iload_reg_mem);
4509 %}
4510
4511 // Load Byte (8 bit unsigned) into long
4512 instruct loadUB2L(iRegLNoSp dst, memory mem)
4513 %{
4514 match(Set dst (ConvI2L (LoadUB mem)));
4515
4516 ins_cost(LOAD_COST);
4517 format %{ "lbu $dst, $mem\t# byte, #@loadUB2L" %}
4518
4519 ins_encode %{
4520 __ lbu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4521 %}
4522
4523 ins_pipe(iload_reg_mem);
4524 %}
4525
4526 // Load Short (16 bit signed)
4527 instruct loadS(iRegINoSp dst, memory mem)
4528 %{
4529 match(Set dst (LoadS mem));
4530
4531 ins_cost(LOAD_COST);
4532 format %{ "lh $dst, $mem\t# short, #@loadS" %}
4533
4534 ins_encode %{
4535 __ lh(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4536 %}
4537
4538 ins_pipe(iload_reg_mem);
4539 %}
4540
4541 // Load Short (16 bit signed) into long
4542 instruct loadS2L(iRegLNoSp dst, memory mem)
4543 %{
4544 match(Set dst (ConvI2L (LoadS mem)));
4545
4546 ins_cost(LOAD_COST);
4547 format %{ "lh $dst, $mem\t# short, #@loadS2L" %}
4548
4549 ins_encode %{
4550 __ lh(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4551 %}
4552
4553 ins_pipe(iload_reg_mem);
4554 %}
4555
4556 // Load Char (16 bit unsigned)
4557 instruct loadUS(iRegINoSp dst, memory mem)
4558 %{
4559 match(Set dst (LoadUS mem));
4560
4561 ins_cost(LOAD_COST);
4562 format %{ "lhu $dst, $mem\t# short, #@loadUS" %}
4563
4564 ins_encode %{
4565 __ lhu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4566 %}
4567
4568 ins_pipe(iload_reg_mem);
4569 %}
4570
4571 // Load Short/Char (16 bit unsigned) into long
4572 instruct loadUS2L(iRegLNoSp dst, memory mem)
4573 %{
4574 match(Set dst (ConvI2L (LoadUS mem)));
4575
4576 ins_cost(LOAD_COST);
4577 format %{ "lhu $dst, $mem\t# short, #@loadUS2L" %}
4578
4579 ins_encode %{
4580 __ lhu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4581 %}
4582
4583 ins_pipe(iload_reg_mem);
4584 %}
4585
4586 // Load Integer (32 bit signed)
4587 instruct loadI(iRegINoSp dst, memory mem)
4588 %{
4589 match(Set dst (LoadI mem));
4590
4591 ins_cost(LOAD_COST);
4592 format %{ "lw $dst, $mem\t# int, #@loadI" %}
4593
4594 ins_encode %{
4595 __ lw(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4596 %}
4597
4598 ins_pipe(iload_reg_mem);
4599 %}
4600
4601 // Load Integer (32 bit signed) into long
4602 instruct loadI2L(iRegLNoSp dst, memory mem)
4603 %{
4604 match(Set dst (ConvI2L (LoadI mem)));
4605
4606 ins_cost(LOAD_COST);
4607 format %{ "lw $dst, $mem\t# int, #@loadI2L" %}
4608
4609 ins_encode %{
4610 __ lw(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4611 %}
4612
4613 ins_pipe(iload_reg_mem);
4614 %}
4615
4616 // Load Integer (32 bit unsigned) into long
4617 instruct loadUI2L(iRegLNoSp dst, memory mem, immL_32bits mask)
4618 %{
4619 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
4620
4621 ins_cost(LOAD_COST);
4622 format %{ "lwu $dst, $mem\t# int, #@loadUI2L" %}
4623
4624 ins_encode %{
4625 __ lwu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4626 %}
4627
4628 ins_pipe(iload_reg_mem);
4629 %}
4630
4631 // Load Long (64 bit signed)
4632 instruct loadL(iRegLNoSp dst, memory mem)
4633 %{
4634 match(Set dst (LoadL mem));
4635
4636 ins_cost(LOAD_COST);
4637 format %{ "ld $dst, $mem\t# int, #@loadL" %}
4638
4639 ins_encode %{
4640 __ ld(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4641 %}
4642
4643 ins_pipe(iload_reg_mem);
4644 %}
4645
4646 // Load Range
4647 instruct loadRange(iRegINoSp dst, memory mem)
4648 %{
4649 match(Set dst (LoadRange mem));
4650
4651 ins_cost(LOAD_COST);
4652 format %{ "lwu $dst, $mem\t# range, #@loadRange" %}
4653
4654 ins_encode %{
4655 __ lwu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4656 %}
4657
4658 ins_pipe(iload_reg_mem);
4659 %}
4660
4661 // Load Pointer
4662 instruct loadP(iRegPNoSp dst, memory mem)
4663 %{
4664 match(Set dst (LoadP mem));
4665 predicate(n->as_Load()->barrier_data() == 0);
4666
4667 ins_cost(LOAD_COST);
4668 format %{ "ld $dst, $mem\t# ptr, #@loadP" %}
4669
4670 ins_encode %{
4671 __ ld(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4672 %}
4673
4674 ins_pipe(iload_reg_mem);
4675 %}
4676
4677 // Load Compressed Pointer
4678 instruct loadN(iRegNNoSp dst, memory mem)
4679 %{
4680 predicate(n->as_Load()->barrier_data() == 0);
4681 match(Set dst (LoadN mem));
4682
4683 ins_cost(LOAD_COST);
4684 format %{ "lwu $dst, $mem\t# compressed ptr, #@loadN" %}
4685
4686 ins_encode %{
4687 __ lwu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4688 %}
4689
4690 ins_pipe(iload_reg_mem);
4691 %}
4692
4693 // Load Klass Pointer
4694 instruct loadKlass(iRegPNoSp dst, memory mem)
4695 %{
4696 match(Set dst (LoadKlass mem));
4697
4698 ins_cost(LOAD_COST);
4699 format %{ "ld $dst, $mem\t# class, #@loadKlass" %}
4700
4701 ins_encode %{
4702 __ ld(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4703 %}
4704
4705 ins_pipe(iload_reg_mem);
4706 %}
4707
4708 // Load Narrow Klass Pointer
4709 instruct loadNKlass(iRegNNoSp dst, memory mem)
4710 %{
4711 predicate(!UseCompactObjectHeaders);
4712 match(Set dst (LoadNKlass mem));
4713
4714 ins_cost(LOAD_COST);
4715 format %{ "lwu $dst, $mem\t# compressed class ptr, #@loadNKlass" %}
4716
4717 ins_encode %{
4718 __ lwu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4719 %}
4720
4721 ins_pipe(iload_reg_mem);
4722 %}
4723
4724 instruct loadNKlassCompactHeaders(iRegNNoSp dst, memory mem)
4725 %{
4726 predicate(UseCompactObjectHeaders);
4727 match(Set dst (LoadNKlass mem));
4728
4729 ins_cost(LOAD_COST);
4730 format %{
4731 "lwu $dst, $mem\t# compressed klass ptr, shifted\n\t"
4732 "srli $dst, $dst, markWord::klass_shift_at_offset"
4733 %}
4734
4735 ins_encode %{
4736 __ lwu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4737 __ srli(as_Register($dst$$reg), as_Register($dst$$reg), (unsigned) markWord::klass_shift_at_offset);
4738 %}
4739
4740 ins_pipe(iload_reg_mem);
4741 %}
4742
4743 // Load Float
4744 instruct loadF(fRegF dst, memory mem)
4745 %{
4746 match(Set dst (LoadF mem));
4747
4748 ins_cost(LOAD_COST);
4749 format %{ "flw $dst, $mem\t# float, #@loadF" %}
4750
4751 ins_encode %{
4752 __ flw(as_FloatRegister($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4753 %}
4754
4755 ins_pipe(fp_load_mem_s);
4756 %}
4757
4758 // Load Double
4759 instruct loadD(fRegD dst, memory mem)
4760 %{
4761 match(Set dst (LoadD mem));
4762
4763 ins_cost(LOAD_COST);
4764 format %{ "fld $dst, $mem\t# double, #@loadD" %}
4765
4766 ins_encode %{
4767 __ fld(as_FloatRegister($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4768 %}
4769
4770 ins_pipe(fp_load_mem_d);
4771 %}
4772
4773 // Load Int Constant
4774 instruct loadConI(iRegINoSp dst, immI src)
4775 %{
4776 match(Set dst src);
4777
4778 ins_cost(ALU_COST);
4779 format %{ "mv $dst, $src\t# int, #@loadConI" %}
4780
4781 ins_encode(riscv_enc_mov_imm(dst, src));
4782
4783 ins_pipe(ialu_imm);
4784 %}
4785
4786 // Load Long Constant
4787 instruct loadConL(iRegLNoSp dst, immL src)
4788 %{
4789 match(Set dst src);
4790
4791 ins_cost(ALU_COST);
4792 format %{ "mv $dst, $src\t# long, #@loadConL" %}
4793
4794 ins_encode(riscv_enc_mov_imm(dst, src));
4795
4796 ins_pipe(ialu_imm);
4797 %}
4798
4799 // Load Pointer Constant
4800 instruct loadConP(iRegPNoSp dst, immP con)
4801 %{
4802 match(Set dst con);
4803
4804 ins_cost(ALU_COST);
4805 format %{ "mv $dst, $con\t# ptr, #@loadConP" %}
4806
4807 ins_encode(riscv_enc_mov_p(dst, con));
4808
4809 ins_pipe(ialu_imm);
4810 %}
4811
4812 // Load Null Pointer Constant
4813 instruct loadConP0(iRegPNoSp dst, immP0 con)
4814 %{
4815 match(Set dst con);
4816
4817 ins_cost(ALU_COST);
4818 format %{ "mv $dst, $con\t# null pointer, #@loadConP0" %}
4819
4820 ins_encode(riscv_enc_mov_zero(dst));
4821
4822 ins_pipe(ialu_imm);
4823 %}
4824
4825 // Load Pointer Constant One
4826 instruct loadConP1(iRegPNoSp dst, immP_1 con)
4827 %{
4828 match(Set dst con);
4829
4830 ins_cost(ALU_COST);
4831 format %{ "mv $dst, $con\t# load ptr constant one, #@loadConP1" %}
4832
4833 ins_encode(riscv_enc_mov_p1(dst));
4834
4835 ins_pipe(ialu_imm);
4836 %}
4837
4838 // Load Byte Map Base Constant
4839 instruct loadByteMapBase(iRegPNoSp dst, immByteMapBase con)
4840 %{
4841 match(Set dst con);
4842 ins_cost(ALU_COST);
4843 format %{ "mv $dst, $con\t# Byte Map Base, #@loadByteMapBase" %}
4844
4845 ins_encode(riscv_enc_mov_byte_map_base(dst));
4846
4847 ins_pipe(ialu_imm);
4848 %}
4849
4850 // Load Narrow Pointer Constant
4851 instruct loadConN(iRegNNoSp dst, immN con)
4852 %{
4853 match(Set dst con);
4854
4855 ins_cost(ALU_COST * 4);
4856 format %{ "mv $dst, $con\t# compressed ptr, #@loadConN" %}
4857
4858 ins_encode(riscv_enc_mov_n(dst, con));
4859
4860 ins_pipe(ialu_imm);
4861 %}
4862
4863 // Load Narrow Null Pointer Constant
4864 instruct loadConN0(iRegNNoSp dst, immN0 con)
4865 %{
4866 match(Set dst con);
4867
4868 ins_cost(ALU_COST);
4869 format %{ "mv $dst, $con\t# compressed null pointer, #@loadConN0" %}
4870
4871 ins_encode(riscv_enc_mov_zero(dst));
4872
4873 ins_pipe(ialu_imm);
4874 %}
4875
4876 // Load Narrow Klass Constant
4877 instruct loadConNKlass(iRegNNoSp dst, immNKlass con)
4878 %{
4879 match(Set dst con);
4880
4881 ins_cost(ALU_COST * 6);
4882 format %{ "mv $dst, $con\t# compressed klass ptr, #@loadConNKlass" %}
4883
4884 ins_encode(riscv_enc_mov_nk(dst, con));
4885
4886 ins_pipe(ialu_imm);
4887 %}
4888
4889 // Load Half Float Constant
4890 instruct loadConH(fRegF dst, immH con) %{
4891 match(Set dst con);
4892
4893 ins_cost(LOAD_COST);
4894 format %{
4895 "flh $dst, [$constantaddress]\t# load from constant table: float=$con, #@loadConH"
4896 %}
4897
4898 ins_encode %{
4899 assert(UseZfh || UseZfhmin, "must");
4900 if (MacroAssembler::can_hf_imm_load($con$$constant)) {
4901 __ fli_h(as_FloatRegister($dst$$reg), $con$$constant);
4902 } else {
4903 __ flh(as_FloatRegister($dst$$reg), $constantaddress($con));
4904 }
4905 %}
4906
4907 ins_pipe(fp_load_constant_s);
4908 %}
4909
4910 instruct loadConH0(fRegF dst, immH0 con) %{
4911 match(Set dst con);
4912
4913 ins_cost(XFER_COST);
4914
4915 format %{ "fmv.h.x $dst, zr\t# float, #@loadConH0" %}
4916
4917 ins_encode %{
4918 assert(UseZfh || UseZfhmin, "must");
4919 __ fmv_h_x(as_FloatRegister($dst$$reg), zr);
4920 %}
4921
4922 ins_pipe(fp_load_constant_s);
4923 %}
4924
4925 // Load Float Constant
4926 instruct loadConF(fRegF dst, immF con) %{
4927 match(Set dst con);
4928
4929 ins_cost(LOAD_COST);
4930 format %{
4931 "flw $dst, [$constantaddress]\t# load from constant table: float=$con, #@loadConF"
4932 %}
4933
4934 ins_encode %{
4935 if (MacroAssembler::can_fp_imm_load($con$$constant)) {
4936 __ fli_s(as_FloatRegister($dst$$reg), $con$$constant);
4937 } else {
4938 __ flw(as_FloatRegister($dst$$reg), $constantaddress($con));
4939 }
4940 %}
4941
4942 ins_pipe(fp_load_constant_s);
4943 %}
4944
4945 instruct loadConF0(fRegF dst, immF0 con) %{
4946 match(Set dst con);
4947
4948 ins_cost(XFER_COST);
4949
4950 format %{ "fmv.w.x $dst, zr\t# float, #@loadConF0" %}
4951
4952 ins_encode %{
4953 __ fmv_w_x(as_FloatRegister($dst$$reg), zr);
4954 %}
4955
4956 ins_pipe(fp_load_constant_s);
4957 %}
4958
4959 // Load Double Constant
4960 instruct loadConD(fRegD dst, immD con) %{
4961 match(Set dst con);
4962
4963 ins_cost(LOAD_COST);
4964 format %{
4965 "fld $dst, [$constantaddress]\t# load from constant table: double=$con, #@loadConD"
4966 %}
4967
4968 ins_encode %{
4969 if (MacroAssembler::can_dp_imm_load($con$$constant)) {
4970 __ fli_d(as_FloatRegister($dst$$reg), $con$$constant);
4971 } else {
4972 __ fld(as_FloatRegister($dst$$reg), $constantaddress($con));
4973 }
4974 %}
4975
4976 ins_pipe(fp_load_constant_d);
4977 %}
4978
4979 instruct loadConD0(fRegD dst, immD0 con) %{
4980 match(Set dst con);
4981
4982 ins_cost(XFER_COST);
4983
4984 format %{ "fmv.d.x $dst, zr\t# double, #@loadConD0" %}
4985
4986 ins_encode %{
4987 __ fmv_d_x(as_FloatRegister($dst$$reg), zr);
4988 %}
4989
4990 ins_pipe(fp_load_constant_d);
4991 %}
4992
4993 // Store Byte
4994 instruct storeB(iRegIorL2I src, memory mem)
4995 %{
4996 match(Set mem (StoreB mem src));
4997
4998 ins_cost(STORE_COST);
4999 format %{ "sb $src, $mem\t# byte, #@storeB" %}
5000
5001 ins_encode %{
5002 __ sb(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5003 %}
5004
5005 ins_pipe(istore_reg_mem);
5006 %}
5007
5008 instruct storeimmB0(immI0 zero, memory mem)
5009 %{
5010 match(Set mem (StoreB mem zero));
5011
5012 ins_cost(STORE_COST);
5013 format %{ "sb zr, $mem\t# byte, #@storeimmB0" %}
5014
5015 ins_encode %{
5016 __ sb(zr, Address(as_Register($mem$$base), $mem$$disp));
5017 %}
5018
5019 ins_pipe(istore_mem);
5020 %}
5021
5022 // Store Char/Short
5023 instruct storeC(iRegIorL2I src, memory mem)
5024 %{
5025 match(Set mem (StoreC mem src));
5026
5027 ins_cost(STORE_COST);
5028 format %{ "sh $src, $mem\t# short, #@storeC" %}
5029
5030 ins_encode %{
5031 __ sh(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5032 %}
5033
5034 ins_pipe(istore_reg_mem);
5035 %}
5036
5037 instruct storeimmC0(immI0 zero, memory mem)
5038 %{
5039 match(Set mem (StoreC mem zero));
5040
5041 ins_cost(STORE_COST);
5042 format %{ "sh zr, $mem\t# short, #@storeimmC0" %}
5043
5044 ins_encode %{
5045 __ sh(zr, Address(as_Register($mem$$base), $mem$$disp));
5046 %}
5047
5048 ins_pipe(istore_mem);
5049 %}
5050
5051 // Store Integer
5052 instruct storeI(iRegIorL2I src, memory mem)
5053 %{
5054 match(Set mem(StoreI mem src));
5055
5056 ins_cost(STORE_COST);
5057 format %{ "sw $src, $mem\t# int, #@storeI" %}
5058
5059 ins_encode %{
5060 __ sw(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5061 %}
5062
5063 ins_pipe(istore_reg_mem);
5064 %}
5065
5066 instruct storeimmI0(immI0 zero, memory mem)
5067 %{
5068 match(Set mem(StoreI mem zero));
5069
5070 ins_cost(STORE_COST);
5071 format %{ "sw zr, $mem\t# int, #@storeimmI0" %}
5072
5073 ins_encode %{
5074 __ sw(zr, Address(as_Register($mem$$base), $mem$$disp));
5075 %}
5076
5077 ins_pipe(istore_mem);
5078 %}
5079
5080 // Store Long (64 bit signed)
5081 instruct storeL(iRegL src, memory mem)
5082 %{
5083 match(Set mem (StoreL mem src));
5084
5085 ins_cost(STORE_COST);
5086 format %{ "sd $src, $mem\t# long, #@storeL" %}
5087
5088 ins_encode %{
5089 __ sd(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5090 %}
5091
5092 ins_pipe(istore_reg_mem);
5093 %}
5094
5095 // Store Long (64 bit signed)
5096 instruct storeimmL0(immL0 zero, memory mem)
5097 %{
5098 match(Set mem (StoreL mem zero));
5099
5100 ins_cost(STORE_COST);
5101 format %{ "sd zr, $mem\t# long, #@storeimmL0" %}
5102
5103 ins_encode %{
5104 __ sd(zr, Address(as_Register($mem$$base), $mem$$disp));
5105 %}
5106
5107 ins_pipe(istore_mem);
5108 %}
5109
5110 // Store Pointer
5111 instruct storeP(iRegP src, memory mem)
5112 %{
5113 match(Set mem (StoreP mem src));
5114 predicate(n->as_Store()->barrier_data() == 0);
5115
5116 ins_cost(STORE_COST);
5117 format %{ "sd $src, $mem\t# ptr, #@storeP" %}
5118
5119 ins_encode %{
5120 __ sd(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5121 %}
5122
5123 ins_pipe(istore_reg_mem);
5124 %}
5125
5126 // Store Pointer
5127 instruct storeimmP0(immP0 zero, memory mem)
5128 %{
5129 match(Set mem (StoreP mem zero));
5130 predicate(n->as_Store()->barrier_data() == 0);
5131
5132 ins_cost(STORE_COST);
5133 format %{ "sd zr, $mem\t# ptr, #@storeimmP0" %}
5134
5135 ins_encode %{
5136 __ sd(zr, Address(as_Register($mem$$base), $mem$$disp));
5137 %}
5138
5139 ins_pipe(istore_mem);
5140 %}
5141
5142 // Store Compressed Pointer
5143 instruct storeN(iRegN src, memory mem)
5144 %{
5145 predicate(n->as_Store()->barrier_data() == 0);
5146 match(Set mem (StoreN mem src));
5147
5148 ins_cost(STORE_COST);
5149 format %{ "sw $src, $mem\t# compressed ptr, #@storeN" %}
5150
5151 ins_encode %{
5152 __ sw(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5153 %}
5154
5155 ins_pipe(istore_reg_mem);
5156 %}
5157
5158 instruct storeImmN0(immN0 zero, memory mem)
5159 %{
5160 predicate(n->as_Store()->barrier_data() == 0);
5161 match(Set mem (StoreN mem zero));
5162
5163 ins_cost(STORE_COST);
5164 format %{ "sw zr, $mem\t# compressed ptr, #@storeImmN0" %}
5165
5166 ins_encode %{
5167 __ sw(zr, Address(as_Register($mem$$base), $mem$$disp));
5168 %}
5169
5170 ins_pipe(istore_reg_mem);
5171 %}
5172
5173 // Store Float
5174 instruct storeF(fRegF src, memory mem)
5175 %{
5176 match(Set mem (StoreF mem src));
5177
5178 ins_cost(STORE_COST);
5179 format %{ "fsw $src, $mem\t# float, #@storeF" %}
5180
5181 ins_encode %{
5182 __ fsw(as_FloatRegister($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5183 %}
5184
5185 ins_pipe(fp_store_reg_s);
5186 %}
5187
5188 // Store Double
5189 instruct storeD(fRegD src, memory mem)
5190 %{
5191 match(Set mem (StoreD mem src));
5192
5193 ins_cost(STORE_COST);
5194 format %{ "fsd $src, $mem\t# double, #@storeD" %}
5195
5196 ins_encode %{
5197 __ fsd(as_FloatRegister($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5198 %}
5199
5200 ins_pipe(fp_store_reg_d);
5201 %}
5202
5203 // Store Compressed Klass Pointer
5204 instruct storeNKlass(iRegN src, memory mem)
5205 %{
5206 match(Set mem (StoreNKlass mem src));
5207
5208 ins_cost(STORE_COST);
5209 format %{ "sw $src, $mem\t# compressed klass ptr, #@storeNKlass" %}
5210
5211 ins_encode %{
5212 __ sw(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5213 %}
5214
5215 ins_pipe(istore_reg_mem);
5216 %}
5217
5218 // ============================================================================
5219 // Prefetch instructions
5220 // Must be safe to execute with invalid address (cannot fault).
5221
5222 instruct prefetchalloc( memory mem ) %{
5223 predicate(UseZicbop);
5224 match(PrefetchAllocation mem);
5225
5226 ins_cost(ALU_COST * 1);
5227 format %{ "prefetch_w $mem\t# Prefetch for write" %}
5228
5229 ins_encode %{
5230 if (Assembler::is_simm12($mem$$disp)) {
5231 if (($mem$$disp & 0x1f) == 0) {
5232 __ prefetch_w(as_Register($mem$$base), $mem$$disp);
5233 } else {
5234 __ addi(t0, as_Register($mem$$base), $mem$$disp);
5235 __ prefetch_w(t0, 0);
5236 }
5237 } else {
5238 __ mv(t0, $mem$$disp);
5239 __ add(t0, as_Register($mem$$base), t0);
5240 __ prefetch_w(t0, 0);
5241 }
5242 %}
5243
5244 ins_pipe(iload_prefetch);
5245 %}
5246
5247 // ============================================================================
5248 // Atomic operation instructions
5249 //
5250
5251 // standard CompareAndSwapX when we are using barriers
5252 // these have higher priority than the rules selected by a predicate
5253 instruct compareAndSwapB(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5254 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5255 %{
5256 match(Set res (CompareAndSwapB mem (Binary oldval newval)));
5257
5258 ins_cost(LOAD_COST + STORE_COST + ALU_COST * 10 + BRANCH_COST * 4);
5259
5260 effect(TEMP_DEF res, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3, KILL cr);
5261
5262 format %{
5263 "cmpxchg $mem, $oldval, $newval\t# (byte) if $mem == $oldval then $mem <-- $newval\n\t"
5264 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapB"
5265 %}
5266
5267 ins_encode %{
5268 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5269 Assembler::relaxed /* acquire */, Assembler::rl /* release */, $res$$Register,
5270 true /* result as bool */, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5271 %}
5272
5273 ins_pipe(pipe_slow);
5274 %}
5275
5276 instruct compareAndSwapS(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5277 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5278 %{
5279 match(Set res (CompareAndSwapS mem (Binary oldval newval)));
5280
5281 ins_cost(LOAD_COST + STORE_COST + ALU_COST * 11 + BRANCH_COST * 4);
5282
5283 effect(TEMP_DEF res, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3, KILL cr);
5284
5285 format %{
5286 "cmpxchg $mem, $oldval, $newval\t# (short) if $mem == $oldval then $mem <-- $newval\n\t"
5287 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapS"
5288 %}
5289
5290 ins_encode %{
5291 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5292 Assembler::relaxed /* acquire */, Assembler::rl /* release */, $res$$Register,
5293 true /* result as bool */, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5294 %}
5295
5296 ins_pipe(pipe_slow);
5297 %}
5298
5299 instruct compareAndSwapI(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5300 %{
5301 match(Set res (CompareAndSwapI mem (Binary oldval newval)));
5302
5303 ins_cost(LOAD_COST + STORE_COST + ALU_COST * 6 + BRANCH_COST * 4);
5304
5305 format %{
5306 "cmpxchg $mem, $oldval, $newval\t# (int) if $mem == $oldval then $mem <-- $newval\n\t"
5307 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapI"
5308 %}
5309
5310 ins_encode(riscv_enc_cmpxchgw(res, mem, oldval, newval));
5311
5312 ins_pipe(pipe_slow);
5313 %}
5314
5315 instruct compareAndSwapL(iRegINoSp res, indirect mem, iRegL oldval, iRegL newval)
5316 %{
5317 match(Set res (CompareAndSwapL mem (Binary oldval newval)));
5318
5319 ins_cost(LOAD_COST + STORE_COST + ALU_COST * 6 + BRANCH_COST * 4);
5320
5321 format %{
5322 "cmpxchg $mem, $oldval, $newval\t# (long) if $mem == $oldval then $mem <-- $newval\n\t"
5323 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapL"
5324 %}
5325
5326 ins_encode(riscv_enc_cmpxchg(res, mem, oldval, newval));
5327
5328 ins_pipe(pipe_slow);
5329 %}
5330
5331 instruct compareAndSwapP(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval)
5332 %{
5333 predicate(n->as_LoadStore()->barrier_data() == 0);
5334
5335 match(Set res (CompareAndSwapP mem (Binary oldval newval)));
5336
5337 ins_cost(LOAD_COST + STORE_COST + ALU_COST * 6 + BRANCH_COST * 4);
5338
5339 format %{
5340 "cmpxchg $mem, $oldval, $newval\t# (ptr) if $mem == $oldval then $mem <-- $newval\n\t"
5341 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapP"
5342 %}
5343
5344 ins_encode(riscv_enc_cmpxchg(res, mem, oldval, newval));
5345
5346 ins_pipe(pipe_slow);
5347 %}
5348
5349 instruct compareAndSwapN(iRegINoSp res, indirect mem, iRegN oldval, iRegN newval)
5350 %{
5351 predicate(n->as_LoadStore()->barrier_data() == 0);
5352 match(Set res (CompareAndSwapN mem (Binary oldval newval)));
5353
5354 ins_cost(LOAD_COST + STORE_COST + ALU_COST * 8 + BRANCH_COST * 4);
5355
5356 format %{
5357 "cmpxchg $mem, $oldval, $newval\t# (narrow oop) if $mem == $oldval then $mem <-- $newval\n\t"
5358 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapN"
5359 %}
5360
5361 ins_encode(riscv_enc_cmpxchgn(res, mem, oldval, newval));
5362
5363 ins_pipe(pipe_slow);
5364 %}
5365
5366 // alternative CompareAndSwapX when we are eliding barriers
5367 instruct compareAndSwapBAcq(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5368 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5369 %{
5370 predicate(needs_acquiring_load_reserved(n));
5371
5372 match(Set res (CompareAndSwapB mem (Binary oldval newval)));
5373
5374 ins_cost(LOAD_COST + STORE_COST + ALU_COST * 10 + BRANCH_COST * 4);
5375
5376 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5377
5378 format %{
5379 "cmpxchg_acq $mem, $oldval, $newval\t# (byte) if $mem == $oldval then $mem <-- $newval\n\t"
5380 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapBAcq"
5381 %}
5382
5383 ins_encode %{
5384 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5385 Assembler::aq /* acquire */, Assembler::rl /* release */, $res$$Register,
5386 true /* result as bool */, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5387 %}
5388
5389 ins_pipe(pipe_slow);
5390 %}
5391
5392 instruct compareAndSwapSAcq(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5393 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5394 %{
5395 predicate(needs_acquiring_load_reserved(n));
5396
5397 match(Set res (CompareAndSwapS mem (Binary oldval newval)));
5398
5399 ins_cost(LOAD_COST + STORE_COST + ALU_COST * 11 + BRANCH_COST * 4);
5400
5401 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5402
5403 format %{
5404 "cmpxchg_acq $mem, $oldval, $newval\t# (short) if $mem == $oldval then $mem <-- $newval\n\t"
5405 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapSAcq"
5406 %}
5407
5408 ins_encode %{
5409 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5410 Assembler::aq /* acquire */, Assembler::rl /* release */, $res$$Register,
5411 true /* result as bool */, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5412 %}
5413
5414 ins_pipe(pipe_slow);
5415 %}
5416
5417 instruct compareAndSwapIAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5418 %{
5419 predicate(needs_acquiring_load_reserved(n));
5420
5421 match(Set res (CompareAndSwapI mem (Binary oldval newval)));
5422
5423 ins_cost(LOAD_COST + STORE_COST + ALU_COST * 6 + BRANCH_COST * 4);
5424
5425 format %{
5426 "cmpxchg_acq $mem, $oldval, $newval\t# (int) if $mem == $oldval then $mem <-- $newval\n\t"
5427 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapIAcq"
5428 %}
5429
5430 ins_encode(riscv_enc_cmpxchgw_acq(res, mem, oldval, newval));
5431
5432 ins_pipe(pipe_slow);
5433 %}
5434
5435 instruct compareAndSwapLAcq(iRegINoSp res, indirect mem, iRegL oldval, iRegL newval)
5436 %{
5437 predicate(needs_acquiring_load_reserved(n));
5438
5439 match(Set res (CompareAndSwapL mem (Binary oldval newval)));
5440
5441 ins_cost(LOAD_COST + STORE_COST + ALU_COST * 6 + BRANCH_COST * 4);
5442
5443 format %{
5444 "cmpxchg_acq $mem, $oldval, $newval\t# (long) if $mem == $oldval then $mem <-- $newval\n\t"
5445 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapLAcq"
5446 %}
5447
5448 ins_encode(riscv_enc_cmpxchg_acq(res, mem, oldval, newval));
5449
5450 ins_pipe(pipe_slow);
5451 %}
5452
5453 instruct compareAndSwapPAcq(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval)
5454 %{
5455 predicate(needs_acquiring_load_reserved(n) && (n->as_LoadStore()->barrier_data() == 0));
5456
5457 match(Set res (CompareAndSwapP mem (Binary oldval newval)));
5458
5459 ins_cost(LOAD_COST + STORE_COST + ALU_COST * 6 + BRANCH_COST * 4);
5460
5461 format %{
5462 "cmpxchg_acq $mem, $oldval, $newval\t# (ptr) if $mem == $oldval then $mem <-- $newval\n\t"
5463 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapPAcq"
5464 %}
5465
5466 ins_encode(riscv_enc_cmpxchg_acq(res, mem, oldval, newval));
5467
5468 ins_pipe(pipe_slow);
5469 %}
5470
5471 instruct compareAndSwapNAcq(iRegINoSp res, indirect mem, iRegN oldval, iRegN newval)
5472 %{
5473 predicate(needs_acquiring_load_reserved(n) && n->as_LoadStore()->barrier_data() == 0);
5474
5475 match(Set res (CompareAndSwapN mem (Binary oldval newval)));
5476
5477 ins_cost(LOAD_COST + STORE_COST + ALU_COST * 8 + BRANCH_COST * 4);
5478
5479 format %{
5480 "cmpxchg_acq $mem, $oldval, $newval\t# (narrow oop) if $mem == $oldval then $mem <-- $newval\n\t"
5481 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapNAcq"
5482 %}
5483
5484 ins_encode(riscv_enc_cmpxchgn_acq(res, mem, oldval, newval));
5485
5486 ins_pipe(pipe_slow);
5487 %}
5488
5489 // Sundry CAS operations. Note that release is always true,
5490 // regardless of the memory ordering of the CAS. This is because we
5491 // need the volatile case to be sequentially consistent but there is
5492 // no trailing StoreLoad barrier emitted by C2. Unfortunately we
5493 // can't check the type of memory ordering here, so we always emit a
5494 // sc_d(w) with rl bit set.
5495 instruct compareAndExchangeB(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5496 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5497 %{
5498 match(Set res (CompareAndExchangeB mem (Binary oldval newval)));
5499
5500 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST * 5);
5501
5502 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5503
5504 format %{
5505 "cmpxchg $res = $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeB"
5506 %}
5507
5508 ins_encode %{
5509 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5510 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
5511 /*result_as_bool*/ false, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5512 %}
5513
5514 ins_pipe(pipe_slow);
5515 %}
5516
5517 instruct compareAndExchangeS(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5518 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5519 %{
5520 match(Set res (CompareAndExchangeS mem (Binary oldval newval)));
5521
5522 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST * 6);
5523
5524 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5525
5526 format %{
5527 "cmpxchg $res = $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeS"
5528 %}
5529
5530 ins_encode %{
5531 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5532 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
5533 /*result_as_bool*/ false, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5534 %}
5535
5536 ins_pipe(pipe_slow);
5537 %}
5538
5539 instruct compareAndExchangeI(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5540 %{
5541 match(Set res (CompareAndExchangeI mem (Binary oldval newval)));
5542
5543 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST);
5544
5545 effect(TEMP_DEF res);
5546
5547 format %{
5548 "cmpxchg $res = $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeI"
5549 %}
5550
5551 ins_encode %{
5552 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
5553 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5554 %}
5555
5556 ins_pipe(pipe_slow);
5557 %}
5558
5559 instruct compareAndExchangeL(iRegLNoSp res, indirect mem, iRegL oldval, iRegL newval)
5560 %{
5561 match(Set res (CompareAndExchangeL mem (Binary oldval newval)));
5562
5563 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST);
5564
5565 effect(TEMP_DEF res);
5566
5567 format %{
5568 "cmpxchg $res = $mem, $oldval, $newval\t# (long, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeL"
5569 %}
5570
5571 ins_encode %{
5572 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5573 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5574 %}
5575
5576 ins_pipe(pipe_slow);
5577 %}
5578
5579 instruct compareAndExchangeN(iRegNNoSp res, indirect mem, iRegN oldval, iRegN newval)
5580 %{
5581 predicate(n->as_LoadStore()->barrier_data() == 0);
5582 match(Set res (CompareAndExchangeN mem (Binary oldval newval)));
5583
5584 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST * 3);
5585
5586 effect(TEMP_DEF res);
5587
5588 format %{
5589 "cmpxchg $res = $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeN"
5590 %}
5591
5592 ins_encode %{
5593 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
5594 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5595 %}
5596
5597 ins_pipe(pipe_slow);
5598 %}
5599
5600 instruct compareAndExchangeP(iRegPNoSp res, indirect mem, iRegP oldval, iRegP newval)
5601 %{
5602 predicate(n->as_LoadStore()->barrier_data() == 0);
5603 match(Set res (CompareAndExchangeP mem (Binary oldval newval)));
5604
5605 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST);
5606
5607 effect(TEMP_DEF res);
5608
5609 format %{
5610 "cmpxchg $res = $mem, $oldval, $newval\t# (ptr, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeP"
5611 %}
5612
5613 ins_encode %{
5614 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5615 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5616 %}
5617
5618 ins_pipe(pipe_slow);
5619 %}
5620
5621 instruct compareAndExchangeBAcq(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5622 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5623 %{
5624 predicate(needs_acquiring_load_reserved(n));
5625
5626 match(Set res (CompareAndExchangeB mem (Binary oldval newval)));
5627
5628 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST * 5);
5629
5630 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5631
5632 format %{
5633 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeBAcq"
5634 %}
5635
5636 ins_encode %{
5637 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5638 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
5639 /*result_as_bool*/ false, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5640 %}
5641
5642 ins_pipe(pipe_slow);
5643 %}
5644
5645 instruct compareAndExchangeSAcq(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5646 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5647 %{
5648 predicate(needs_acquiring_load_reserved(n));
5649
5650 match(Set res (CompareAndExchangeS mem (Binary oldval newval)));
5651
5652 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST * 6);
5653
5654 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5655
5656 format %{
5657 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeSAcq"
5658 %}
5659
5660 ins_encode %{
5661 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5662 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
5663 /*result_as_bool*/ false, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5664 %}
5665
5666 ins_pipe(pipe_slow);
5667 %}
5668
5669 instruct compareAndExchangeIAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5670 %{
5671 predicate(needs_acquiring_load_reserved(n));
5672
5673 match(Set res (CompareAndExchangeI mem (Binary oldval newval)));
5674
5675 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST);
5676
5677 effect(TEMP_DEF res);
5678
5679 format %{
5680 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeIAcq"
5681 %}
5682
5683 ins_encode %{
5684 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
5685 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
5686 %}
5687
5688 ins_pipe(pipe_slow);
5689 %}
5690
5691 instruct compareAndExchangeLAcq(iRegLNoSp res, indirect mem, iRegL oldval, iRegL newval)
5692 %{
5693 predicate(needs_acquiring_load_reserved(n));
5694
5695 match(Set res (CompareAndExchangeL mem (Binary oldval newval)));
5696
5697 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST);
5698
5699 effect(TEMP_DEF res);
5700
5701 format %{
5702 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (long, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeLAcq"
5703 %}
5704
5705 ins_encode %{
5706 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5707 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
5708 %}
5709
5710 ins_pipe(pipe_slow);
5711 %}
5712
5713 instruct compareAndExchangeNAcq(iRegNNoSp res, indirect mem, iRegN oldval, iRegN newval)
5714 %{
5715 predicate(needs_acquiring_load_reserved(n) && n->as_LoadStore()->barrier_data() == 0);
5716
5717 match(Set res (CompareAndExchangeN mem (Binary oldval newval)));
5718
5719 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST);
5720
5721 effect(TEMP_DEF res);
5722
5723 format %{
5724 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeNAcq"
5725 %}
5726
5727 ins_encode %{
5728 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
5729 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
5730 %}
5731
5732 ins_pipe(pipe_slow);
5733 %}
5734
5735 instruct compareAndExchangePAcq(iRegPNoSp res, indirect mem, iRegP oldval, iRegP newval)
5736 %{
5737 predicate(needs_acquiring_load_reserved(n) && (n->as_LoadStore()->barrier_data() == 0));
5738
5739 match(Set res (CompareAndExchangeP mem (Binary oldval newval)));
5740
5741 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST);
5742
5743 effect(TEMP_DEF res);
5744
5745 format %{
5746 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (ptr, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangePAcq"
5747 %}
5748
5749 ins_encode %{
5750 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5751 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
5752 %}
5753
5754 ins_pipe(pipe_slow);
5755 %}
5756
5757 instruct weakCompareAndSwapB(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5758 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5759 %{
5760 match(Set res (WeakCompareAndSwapB mem (Binary oldval newval)));
5761
5762 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 6);
5763
5764 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5765
5766 format %{
5767 "weak_cmpxchg $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5768 "# $res == 1 when success, #@weakCompareAndSwapB"
5769 %}
5770
5771 ins_encode %{
5772 __ weak_cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5773 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
5774 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5775 %}
5776
5777 ins_pipe(pipe_slow);
5778 %}
5779
5780 instruct weakCompareAndSwapS(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5781 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5782 %{
5783 match(Set res (WeakCompareAndSwapS mem (Binary oldval newval)));
5784
5785 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 7);
5786
5787 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5788
5789 format %{
5790 "weak_cmpxchg $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5791 "# $res == 1 when success, #@weakCompareAndSwapS"
5792 %}
5793
5794 ins_encode %{
5795 __ weak_cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5796 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
5797 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5798 %}
5799
5800 ins_pipe(pipe_slow);
5801 %}
5802
5803 instruct weakCompareAndSwapI(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5804 %{
5805 match(Set res (WeakCompareAndSwapI mem (Binary oldval newval)));
5806
5807 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 2);
5808
5809 format %{
5810 "weak_cmpxchg $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5811 "# $res == 1 when success, #@weakCompareAndSwapI"
5812 %}
5813
5814 ins_encode %{
5815 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
5816 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5817 %}
5818
5819 ins_pipe(pipe_slow);
5820 %}
5821
5822 instruct weakCompareAndSwapL(iRegINoSp res, indirect mem, iRegL oldval, iRegL newval)
5823 %{
5824 match(Set res (WeakCompareAndSwapL mem (Binary oldval newval)));
5825
5826 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 2);
5827
5828 format %{
5829 "weak_cmpxchg $mem, $oldval, $newval\t# (long, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5830 "# $res == 1 when success, #@weakCompareAndSwapL"
5831 %}
5832
5833 ins_encode %{
5834 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5835 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5836 %}
5837
5838 ins_pipe(pipe_slow);
5839 %}
5840
5841 instruct weakCompareAndSwapN(iRegINoSp res, indirect mem, iRegN oldval, iRegN newval)
5842 %{
5843 predicate(n->as_LoadStore()->barrier_data() == 0);
5844 match(Set res (WeakCompareAndSwapN mem (Binary oldval newval)));
5845
5846 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 4);
5847
5848 format %{
5849 "weak_cmpxchg $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5850 "# $res == 1 when success, #@weakCompareAndSwapN"
5851 %}
5852
5853 ins_encode %{
5854 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
5855 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5856 %}
5857
5858 ins_pipe(pipe_slow);
5859 %}
5860
5861 instruct weakCompareAndSwapP(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval)
5862 %{
5863 predicate(n->as_LoadStore()->barrier_data() == 0);
5864 match(Set res (WeakCompareAndSwapP mem (Binary oldval newval)));
5865
5866 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 2);
5867
5868 format %{
5869 "weak_cmpxchg $mem, $oldval, $newval\t# (ptr, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5870 "# $res == 1 when success, #@weakCompareAndSwapP"
5871 %}
5872
5873 ins_encode %{
5874 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5875 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5876 %}
5877
5878 ins_pipe(pipe_slow);
5879 %}
5880
5881 instruct weakCompareAndSwapBAcq(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5882 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5883 %{
5884 predicate(needs_acquiring_load_reserved(n));
5885
5886 match(Set res (WeakCompareAndSwapB mem (Binary oldval newval)));
5887
5888 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 6);
5889
5890 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5891
5892 format %{
5893 "weak_cmpxchg_acq $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5894 "# $res == 1 when success, #@weakCompareAndSwapBAcq"
5895 %}
5896
5897 ins_encode %{
5898 __ weak_cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5899 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
5900 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5901 %}
5902
5903 ins_pipe(pipe_slow);
5904 %}
5905
5906 instruct weakCompareAndSwapSAcq(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5907 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5908 %{
5909 predicate(needs_acquiring_load_reserved(n));
5910
5911 match(Set res (WeakCompareAndSwapS mem (Binary oldval newval)));
5912
5913 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 7);
5914
5915 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5916
5917 format %{
5918 "weak_cmpxchg_acq $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5919 "# $res == 1 when success, #@weakCompareAndSwapSAcq"
5920 %}
5921
5922 ins_encode %{
5923 __ weak_cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5924 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
5925 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5926 %}
5927
5928 ins_pipe(pipe_slow);
5929 %}
5930
5931 instruct weakCompareAndSwapIAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5932 %{
5933 predicate(needs_acquiring_load_reserved(n));
5934
5935 match(Set res (WeakCompareAndSwapI mem (Binary oldval newval)));
5936
5937 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 2);
5938
5939 format %{
5940 "weak_cmpxchg_acq $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5941 "# $res == 1 when success, #@weakCompareAndSwapIAcq"
5942 %}
5943
5944 ins_encode %{
5945 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
5946 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
5947 %}
5948
5949 ins_pipe(pipe_slow);
5950 %}
5951
5952 instruct weakCompareAndSwapLAcq(iRegINoSp res, indirect mem, iRegL oldval, iRegL newval)
5953 %{
5954 predicate(needs_acquiring_load_reserved(n));
5955
5956 match(Set res (WeakCompareAndSwapL mem (Binary oldval newval)));
5957
5958 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 2);
5959
5960 format %{
5961 "weak_cmpxchg_acq $mem, $oldval, $newval\t# (long, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5962 "# $res == 1 when success, #@weakCompareAndSwapLAcq"
5963 %}
5964
5965 ins_encode %{
5966 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5967 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
5968 %}
5969
5970 ins_pipe(pipe_slow);
5971 %}
5972
5973 instruct weakCompareAndSwapNAcq(iRegINoSp res, indirect mem, iRegN oldval, iRegN newval)
5974 %{
5975 predicate(needs_acquiring_load_reserved(n) && n->as_LoadStore()->barrier_data() == 0);
5976
5977 match(Set res (WeakCompareAndSwapN mem (Binary oldval newval)));
5978
5979 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 4);
5980
5981 format %{
5982 "weak_cmpxchg_acq $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5983 "# $res == 1 when success, #@weakCompareAndSwapNAcq"
5984 %}
5985
5986 ins_encode %{
5987 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
5988 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
5989 %}
5990
5991 ins_pipe(pipe_slow);
5992 %}
5993
5994 instruct weakCompareAndSwapPAcq(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval)
5995 %{
5996 predicate(needs_acquiring_load_reserved(n) && (n->as_LoadStore()->barrier_data() == 0));
5997
5998 match(Set res (WeakCompareAndSwapP mem (Binary oldval newval)));
5999
6000 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 2);
6001
6002 format %{
6003 "weak_cmpxchg_acq $mem, $oldval, $newval\t# (ptr, weak) if $mem == $oldval then $mem <-- $newval\n\t"
6004 "\t# $res == 1 when success, #@weakCompareAndSwapPAcq"
6005 %}
6006
6007 ins_encode %{
6008 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
6009 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
6010 %}
6011
6012 ins_pipe(pipe_slow);
6013 %}
6014
6015 instruct get_and_setI(indirect mem, iRegI newv, iRegINoSp prev)
6016 %{
6017 match(Set prev (GetAndSetI mem newv));
6018
6019 ins_cost(ALU_COST);
6020
6021 format %{ "atomic_xchgw $prev, $newv, [$mem]\t#@get_and_setI" %}
6022
6023 ins_encode %{
6024 __ atomic_xchgw($prev$$Register, $newv$$Register, as_Register($mem$$base));
6025 %}
6026
6027 ins_pipe(pipe_serial);
6028 %}
6029
6030 instruct get_and_setL(indirect mem, iRegL newv, iRegLNoSp prev)
6031 %{
6032 match(Set prev (GetAndSetL mem newv));
6033
6034 ins_cost(ALU_COST);
6035
6036 format %{ "atomic_xchg $prev, $newv, [$mem]\t#@get_and_setL" %}
6037
6038 ins_encode %{
6039 __ atomic_xchg($prev$$Register, $newv$$Register, as_Register($mem$$base));
6040 %}
6041
6042 ins_pipe(pipe_serial);
6043 %}
6044
6045 instruct get_and_setN(indirect mem, iRegN newv, iRegINoSp prev)
6046 %{
6047 predicate(n->as_LoadStore()->barrier_data() == 0);
6048
6049 match(Set prev (GetAndSetN mem newv));
6050
6051 ins_cost(ALU_COST);
6052
6053 format %{ "atomic_xchgwu $prev, $newv, [$mem]\t#@get_and_setN" %}
6054
6055 ins_encode %{
6056 __ atomic_xchgwu($prev$$Register, $newv$$Register, as_Register($mem$$base));
6057 %}
6058
6059 ins_pipe(pipe_serial);
6060 %}
6061
6062 instruct get_and_setP(indirect mem, iRegP newv, iRegPNoSp prev)
6063 %{
6064 predicate(n->as_LoadStore()->barrier_data() == 0);
6065 match(Set prev (GetAndSetP mem newv));
6066
6067 ins_cost(ALU_COST);
6068
6069 format %{ "atomic_xchg $prev, $newv, [$mem]\t#@get_and_setP" %}
6070
6071 ins_encode %{
6072 __ atomic_xchg($prev$$Register, $newv$$Register, as_Register($mem$$base));
6073 %}
6074
6075 ins_pipe(pipe_serial);
6076 %}
6077
6078 instruct get_and_setIAcq(indirect mem, iRegI newv, iRegINoSp prev)
6079 %{
6080 predicate(needs_acquiring_load_reserved(n));
6081
6082 match(Set prev (GetAndSetI mem newv));
6083
6084 ins_cost(ALU_COST);
6085
6086 format %{ "atomic_xchgw_acq $prev, $newv, [$mem]\t#@get_and_setIAcq" %}
6087
6088 ins_encode %{
6089 __ atomic_xchgalw($prev$$Register, $newv$$Register, as_Register($mem$$base));
6090 %}
6091
6092 ins_pipe(pipe_serial);
6093 %}
6094
6095 instruct get_and_setLAcq(indirect mem, iRegL newv, iRegLNoSp prev)
6096 %{
6097 predicate(needs_acquiring_load_reserved(n));
6098
6099 match(Set prev (GetAndSetL mem newv));
6100
6101 ins_cost(ALU_COST);
6102
6103 format %{ "atomic_xchg_acq $prev, $newv, [$mem]\t#@get_and_setLAcq" %}
6104
6105 ins_encode %{
6106 __ atomic_xchgal($prev$$Register, $newv$$Register, as_Register($mem$$base));
6107 %}
6108
6109 ins_pipe(pipe_serial);
6110 %}
6111
6112 instruct get_and_setNAcq(indirect mem, iRegN newv, iRegINoSp prev)
6113 %{
6114 predicate(needs_acquiring_load_reserved(n) && n->as_LoadStore()->barrier_data() == 0);
6115
6116 match(Set prev (GetAndSetN mem newv));
6117
6118 ins_cost(ALU_COST);
6119
6120 format %{ "atomic_xchgwu_acq $prev, $newv, [$mem]\t#@get_and_setNAcq" %}
6121
6122 ins_encode %{
6123 __ atomic_xchgalwu($prev$$Register, $newv$$Register, as_Register($mem$$base));
6124 %}
6125
6126 ins_pipe(pipe_serial);
6127 %}
6128
6129 instruct get_and_setPAcq(indirect mem, iRegP newv, iRegPNoSp prev)
6130 %{
6131 predicate(needs_acquiring_load_reserved(n) && (n->as_LoadStore()->barrier_data() == 0));
6132
6133 match(Set prev (GetAndSetP mem newv));
6134
6135 ins_cost(ALU_COST);
6136
6137 format %{ "atomic_xchg_acq $prev, $newv, [$mem]\t#@get_and_setPAcq" %}
6138
6139 ins_encode %{
6140 __ atomic_xchgal($prev$$Register, $newv$$Register, as_Register($mem$$base));
6141 %}
6142
6143 ins_pipe(pipe_serial);
6144 %}
6145
6146 instruct get_and_addL(indirect mem, iRegLNoSp newval, iRegL incr)
6147 %{
6148 match(Set newval (GetAndAddL mem incr));
6149
6150 ins_cost(ALU_COST);
6151
6152 format %{ "get_and_addL $newval, [$mem], $incr\t#@get_and_addL" %}
6153
6154 ins_encode %{
6155 __ atomic_add($newval$$Register, $incr$$Register, as_Register($mem$$base));
6156 %}
6157
6158 ins_pipe(pipe_serial);
6159 %}
6160
6161 instruct get_and_addL_no_res(indirect mem, Universe dummy, iRegL incr)
6162 %{
6163 predicate(n->as_LoadStore()->result_not_used());
6164
6165 match(Set dummy (GetAndAddL mem incr));
6166
6167 ins_cost(ALU_COST);
6168
6169 format %{ "get_and_addL [$mem], $incr\t#@get_and_addL_no_res" %}
6170
6171 ins_encode %{
6172 __ atomic_add(noreg, $incr$$Register, as_Register($mem$$base));
6173 %}
6174
6175 ins_pipe(pipe_serial);
6176 %}
6177
6178 instruct get_and_addLi(indirect mem, iRegLNoSp newval, immLAdd incr)
6179 %{
6180 match(Set newval (GetAndAddL mem incr));
6181
6182 ins_cost(ALU_COST);
6183
6184 format %{ "get_and_addL $newval, [$mem], $incr\t#@get_and_addLi" %}
6185
6186 ins_encode %{
6187 __ atomic_add($newval$$Register, $incr$$constant, as_Register($mem$$base));
6188 %}
6189
6190 ins_pipe(pipe_serial);
6191 %}
6192
6193 instruct get_and_addLi_no_res(indirect mem, Universe dummy, immLAdd incr)
6194 %{
6195 predicate(n->as_LoadStore()->result_not_used());
6196
6197 match(Set dummy (GetAndAddL mem incr));
6198
6199 ins_cost(ALU_COST);
6200
6201 format %{ "get_and_addL [$mem], $incr\t#@get_and_addLi_no_res" %}
6202
6203 ins_encode %{
6204 __ atomic_add(noreg, $incr$$constant, as_Register($mem$$base));
6205 %}
6206
6207 ins_pipe(pipe_serial);
6208 %}
6209
6210 instruct get_and_addI(indirect mem, iRegINoSp newval, iRegIorL2I incr)
6211 %{
6212 match(Set newval (GetAndAddI mem incr));
6213
6214 ins_cost(ALU_COST);
6215
6216 format %{ "get_and_addI $newval, [$mem], $incr\t#@get_and_addI" %}
6217
6218 ins_encode %{
6219 __ atomic_addw($newval$$Register, $incr$$Register, as_Register($mem$$base));
6220 %}
6221
6222 ins_pipe(pipe_serial);
6223 %}
6224
6225 instruct get_and_addI_no_res(indirect mem, Universe dummy, iRegIorL2I incr)
6226 %{
6227 predicate(n->as_LoadStore()->result_not_used());
6228
6229 match(Set dummy (GetAndAddI mem incr));
6230
6231 ins_cost(ALU_COST);
6232
6233 format %{ "get_and_addI [$mem], $incr\t#@get_and_addI_no_res" %}
6234
6235 ins_encode %{
6236 __ atomic_addw(noreg, $incr$$Register, as_Register($mem$$base));
6237 %}
6238
6239 ins_pipe(pipe_serial);
6240 %}
6241
6242 instruct get_and_addIi(indirect mem, iRegINoSp newval, immIAdd incr)
6243 %{
6244 match(Set newval (GetAndAddI mem incr));
6245
6246 ins_cost(ALU_COST);
6247
6248 format %{ "get_and_addI $newval, [$mem], $incr\t#@get_and_addIi" %}
6249
6250 ins_encode %{
6251 __ atomic_addw($newval$$Register, $incr$$constant, as_Register($mem$$base));
6252 %}
6253
6254 ins_pipe(pipe_serial);
6255 %}
6256
6257 instruct get_and_addIi_no_res(indirect mem, Universe dummy, immIAdd incr)
6258 %{
6259 predicate(n->as_LoadStore()->result_not_used());
6260
6261 match(Set dummy (GetAndAddI mem incr));
6262
6263 ins_cost(ALU_COST);
6264
6265 format %{ "get_and_addI [$mem], $incr\t#@get_and_addIi_no_res" %}
6266
6267 ins_encode %{
6268 __ atomic_addw(noreg, $incr$$constant, as_Register($mem$$base));
6269 %}
6270
6271 ins_pipe(pipe_serial);
6272 %}
6273
6274 instruct get_and_addLAcq(indirect mem, iRegLNoSp newval, iRegL incr)
6275 %{
6276 predicate(needs_acquiring_load_reserved(n));
6277
6278 match(Set newval (GetAndAddL mem incr));
6279
6280 ins_cost(ALU_COST);
6281
6282 format %{ "get_and_addL_acq $newval, [$mem], $incr\t#@get_and_addLAcq" %}
6283
6284 ins_encode %{
6285 __ atomic_addal($newval$$Register, $incr$$Register, as_Register($mem$$base));
6286 %}
6287
6288 ins_pipe(pipe_serial);
6289 %}
6290
6291 instruct get_and_addL_no_resAcq(indirect mem, Universe dummy, iRegL incr) %{
6292 predicate(n->as_LoadStore()->result_not_used() && needs_acquiring_load_reserved(n));
6293
6294 match(Set dummy (GetAndAddL mem incr));
6295
6296 ins_cost(ALU_COST);
6297
6298 format %{ "get_and_addL_acq [$mem], $incr\t#@get_and_addL_no_resAcq" %}
6299
6300 ins_encode %{
6301 __ atomic_addal(noreg, $incr$$Register, as_Register($mem$$base));
6302 %}
6303
6304 ins_pipe(pipe_serial);
6305 %}
6306
6307 instruct get_and_addLiAcq(indirect mem, iRegLNoSp newval, immLAdd incr)
6308 %{
6309 predicate(needs_acquiring_load_reserved(n));
6310
6311 match(Set newval (GetAndAddL mem incr));
6312
6313 ins_cost(ALU_COST);
6314
6315 format %{ "get_and_addL_acq $newval, [$mem], $incr\t#@get_and_addLiAcq" %}
6316
6317 ins_encode %{
6318 __ atomic_addal($newval$$Register, $incr$$constant, as_Register($mem$$base));
6319 %}
6320
6321 ins_pipe(pipe_serial);
6322 %}
6323
6324 instruct get_and_addLi_no_resAcq(indirect mem, Universe dummy, immLAdd incr)
6325 %{
6326 predicate(n->as_LoadStore()->result_not_used() && needs_acquiring_load_reserved(n));
6327
6328 match(Set dummy (GetAndAddL mem incr));
6329
6330 ins_cost(ALU_COST);
6331
6332 format %{ "get_and_addL_acq [$mem], $incr\t#@get_and_addLi_no_resAcq" %}
6333
6334 ins_encode %{
6335 __ atomic_addal(noreg, $incr$$constant, as_Register($mem$$base));
6336 %}
6337
6338 ins_pipe(pipe_serial);
6339 %}
6340
6341 instruct get_and_addIAcq(indirect mem, iRegINoSp newval, iRegIorL2I incr)
6342 %{
6343 predicate(needs_acquiring_load_reserved(n));
6344
6345 match(Set newval (GetAndAddI mem incr));
6346
6347 ins_cost(ALU_COST);
6348
6349 format %{ "get_and_addI_acq $newval, [$mem], $incr\t#@get_and_addIAcq" %}
6350
6351 ins_encode %{
6352 __ atomic_addalw($newval$$Register, $incr$$Register, as_Register($mem$$base));
6353 %}
6354
6355 ins_pipe(pipe_serial);
6356 %}
6357
6358 instruct get_and_addI_no_resAcq(indirect mem, Universe dummy, iRegIorL2I incr)
6359 %{
6360 predicate(n->as_LoadStore()->result_not_used() && needs_acquiring_load_reserved(n));
6361
6362 match(Set dummy (GetAndAddI mem incr));
6363
6364 ins_cost(ALU_COST);
6365
6366 format %{ "get_and_addI_acq [$mem], $incr\t#@get_and_addI_no_resAcq" %}
6367
6368 ins_encode %{
6369 __ atomic_addalw(noreg, $incr$$Register, as_Register($mem$$base));
6370 %}
6371
6372 ins_pipe(pipe_serial);
6373 %}
6374
6375 instruct get_and_addIiAcq(indirect mem, iRegINoSp newval, immIAdd incr)
6376 %{
6377 predicate(needs_acquiring_load_reserved(n));
6378
6379 match(Set newval (GetAndAddI mem incr));
6380
6381 ins_cost(ALU_COST);
6382
6383 format %{ "get_and_addI_acq $newval, [$mem], $incr\t#@get_and_addIiAcq" %}
6384
6385 ins_encode %{
6386 __ atomic_addalw($newval$$Register, $incr$$constant, as_Register($mem$$base));
6387 %}
6388
6389 ins_pipe(pipe_serial);
6390 %}
6391
6392 instruct get_and_addIi_no_resAcq(indirect mem, Universe dummy, immIAdd incr)
6393 %{
6394 predicate(n->as_LoadStore()->result_not_used() && needs_acquiring_load_reserved(n));
6395
6396 match(Set dummy (GetAndAddI mem incr));
6397
6398 ins_cost(ALU_COST);
6399
6400 format %{ "get_and_addI_acq [$mem], $incr\t#@get_and_addIi_no_resAcq" %}
6401
6402 ins_encode %{
6403 __ atomic_addalw(noreg, $incr$$constant, as_Register($mem$$base));
6404 %}
6405
6406 ins_pipe(pipe_serial);
6407 %}
6408
6409 // ============================================================================
6410 // Arithmetic Instructions
6411 //
6412
6413 // Integer Addition
6414
6415 // TODO
6416 // these currently employ operations which do not set CR and hence are
6417 // not flagged as killing CR but we would like to isolate the cases
6418 // where we want to set flags from those where we don't. need to work
6419 // out how to do that.
6420 instruct addI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6421 match(Set dst (AddI src1 src2));
6422
6423 ins_cost(ALU_COST);
6424 format %{ "addw $dst, $src1, $src2\t#@addI_reg_reg" %}
6425
6426 ins_encode %{
6427 __ addw(as_Register($dst$$reg),
6428 as_Register($src1$$reg),
6429 as_Register($src2$$reg));
6430 %}
6431
6432 ins_pipe(ialu_reg_reg);
6433 %}
6434
6435 instruct addI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immIAdd src2) %{
6436 match(Set dst (AddI src1 src2));
6437
6438 ins_cost(ALU_COST);
6439 format %{ "addiw $dst, $src1, $src2\t#@addI_reg_imm" %}
6440
6441 ins_encode %{
6442 int32_t con = (int32_t)$src2$$constant;
6443 __ addiw(as_Register($dst$$reg),
6444 as_Register($src1$$reg),
6445 $src2$$constant);
6446 %}
6447
6448 ins_pipe(ialu_reg_imm);
6449 %}
6450
6451 instruct addI_reg_imm_l2i(iRegINoSp dst, iRegL src1, immIAdd src2) %{
6452 match(Set dst (AddI (ConvL2I src1) src2));
6453
6454 ins_cost(ALU_COST);
6455 format %{ "addiw $dst, $src1, $src2\t#@addI_reg_imm_l2i" %}
6456
6457 ins_encode %{
6458 __ addiw(as_Register($dst$$reg),
6459 as_Register($src1$$reg),
6460 $src2$$constant);
6461 %}
6462
6463 ins_pipe(ialu_reg_imm);
6464 %}
6465
6466 // Pointer Addition
6467 instruct addP_reg_reg(iRegPNoSp dst, iRegP src1, iRegL src2) %{
6468 match(Set dst (AddP src1 src2));
6469
6470 ins_cost(ALU_COST);
6471 format %{ "add $dst, $src1, $src2\t# ptr, #@addP_reg_reg" %}
6472
6473 ins_encode %{
6474 __ add(as_Register($dst$$reg),
6475 as_Register($src1$$reg),
6476 as_Register($src2$$reg));
6477 %}
6478
6479 ins_pipe(ialu_reg_reg);
6480 %}
6481
6482 // If we shift more than 32 bits, we need not convert I2L.
6483 instruct lShiftL_regI_immGE32(iRegLNoSp dst, iRegI src, uimmI6_ge32 scale) %{
6484 match(Set dst (LShiftL (ConvI2L src) scale));
6485 ins_cost(ALU_COST);
6486 format %{ "slli $dst, $src, $scale & 63\t#@lShiftL_regI_immGE32" %}
6487
6488 ins_encode %{
6489 __ slli(as_Register($dst$$reg), as_Register($src$$reg), $scale$$constant & 63);
6490 %}
6491
6492 ins_pipe(ialu_reg_shift);
6493 %}
6494
6495 // Pointer Immediate Addition
6496 // n.b. this needs to be more expensive than using an indirect memory
6497 // operand
6498 instruct addP_reg_imm(iRegPNoSp dst, iRegP src1, immLAdd src2) %{
6499 match(Set dst (AddP src1 src2));
6500 ins_cost(ALU_COST);
6501 format %{ "addi $dst, $src1, $src2\t# ptr, #@addP_reg_imm" %}
6502
6503 ins_encode %{
6504 // src2 is imm, so actually call the addi
6505 __ addi(as_Register($dst$$reg),
6506 as_Register($src1$$reg),
6507 $src2$$constant);
6508 %}
6509
6510 ins_pipe(ialu_reg_imm);
6511 %}
6512
6513 // Long Addition
6514 instruct addL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
6515 match(Set dst (AddL src1 src2));
6516 ins_cost(ALU_COST);
6517 format %{ "add $dst, $src1, $src2\t#@addL_reg_reg" %}
6518
6519 ins_encode %{
6520 __ add(as_Register($dst$$reg),
6521 as_Register($src1$$reg),
6522 as_Register($src2$$reg));
6523 %}
6524
6525 ins_pipe(ialu_reg_reg);
6526 %}
6527
6528 // No constant pool entries requiredLong Immediate Addition.
6529 instruct addL_reg_imm(iRegLNoSp dst, iRegL src1, immLAdd src2) %{
6530 match(Set dst (AddL src1 src2));
6531 ins_cost(ALU_COST);
6532 format %{ "addi $dst, $src1, $src2\t#@addL_reg_imm" %}
6533
6534 ins_encode %{
6535 // src2 is imm, so actually call the addi
6536 __ addi(as_Register($dst$$reg),
6537 as_Register($src1$$reg),
6538 $src2$$constant);
6539 %}
6540
6541 ins_pipe(ialu_reg_imm);
6542 %}
6543
6544 // Integer Subtraction
6545 instruct subI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6546 match(Set dst (SubI src1 src2));
6547
6548 ins_cost(ALU_COST);
6549 format %{ "subw $dst, $src1, $src2\t#@subI_reg_reg" %}
6550
6551 ins_encode %{
6552 __ subw(as_Register($dst$$reg),
6553 as_Register($src1$$reg),
6554 as_Register($src2$$reg));
6555 %}
6556
6557 ins_pipe(ialu_reg_reg);
6558 %}
6559
6560 // Immediate Subtraction
6561 instruct subI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immISub src2) %{
6562 match(Set dst (SubI src1 src2));
6563
6564 ins_cost(ALU_COST);
6565 format %{ "addiw $dst, $src1, -$src2\t#@subI_reg_imm" %}
6566
6567 ins_encode %{
6568 // src2 is imm, so actually call the addiw
6569 __ subiw(as_Register($dst$$reg),
6570 as_Register($src1$$reg),
6571 $src2$$constant);
6572 %}
6573
6574 ins_pipe(ialu_reg_imm);
6575 %}
6576
6577 // Long Subtraction
6578 instruct subL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
6579 match(Set dst (SubL src1 src2));
6580 ins_cost(ALU_COST);
6581 format %{ "sub $dst, $src1, $src2\t#@subL_reg_reg" %}
6582
6583 ins_encode %{
6584 __ sub(as_Register($dst$$reg),
6585 as_Register($src1$$reg),
6586 as_Register($src2$$reg));
6587 %}
6588
6589 ins_pipe(ialu_reg_reg);
6590 %}
6591
6592 // No constant pool entries requiredLong Immediate Subtraction.
6593 instruct subL_reg_imm(iRegLNoSp dst, iRegL src1, immLSub src2) %{
6594 match(Set dst (SubL src1 src2));
6595 ins_cost(ALU_COST);
6596 format %{ "addi $dst, $src1, -$src2\t#@subL_reg_imm" %}
6597
6598 ins_encode %{
6599 // src2 is imm, so actually call the addi
6600 __ subi(as_Register($dst$$reg),
6601 as_Register($src1$$reg),
6602 $src2$$constant);
6603 %}
6604
6605 ins_pipe(ialu_reg_imm);
6606 %}
6607
6608 // Integer Negation (special case for sub)
6609
6610 instruct negI_reg(iRegINoSp dst, iRegIorL2I src, immI0 zero) %{
6611 match(Set dst (SubI zero src));
6612 ins_cost(ALU_COST);
6613 format %{ "subw $dst, x0, $src\t# int, #@negI_reg" %}
6614
6615 ins_encode %{
6616 // actually call the subw
6617 __ negw(as_Register($dst$$reg),
6618 as_Register($src$$reg));
6619 %}
6620
6621 ins_pipe(ialu_reg);
6622 %}
6623
6624 // Long Negation
6625
6626 instruct negL_reg(iRegLNoSp dst, iRegL src, immL0 zero) %{
6627 match(Set dst (SubL zero src));
6628 ins_cost(ALU_COST);
6629 format %{ "sub $dst, x0, $src\t# long, #@negL_reg" %}
6630
6631 ins_encode %{
6632 // actually call the sub
6633 __ neg(as_Register($dst$$reg),
6634 as_Register($src$$reg));
6635 %}
6636
6637 ins_pipe(ialu_reg);
6638 %}
6639
6640 // Integer Multiply
6641
6642 instruct mulI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6643 match(Set dst (MulI src1 src2));
6644 ins_cost(IMUL_COST);
6645 format %{ "mulw $dst, $src1, $src2\t#@mulI" %}
6646
6647 //this means 2 word multi, and no sign extend to 64 bits
6648 ins_encode %{
6649 // riscv64 mulw will sign-extension to high 32 bits in dst reg
6650 __ mulw(as_Register($dst$$reg),
6651 as_Register($src1$$reg),
6652 as_Register($src2$$reg));
6653 %}
6654
6655 ins_pipe(imul_reg_reg);
6656 %}
6657
6658 // Long Multiply
6659
6660 instruct mulL(iRegLNoSp dst, iRegL src1, iRegL src2) %{
6661 match(Set dst (MulL src1 src2));
6662 ins_cost(IMUL_COST);
6663 format %{ "mul $dst, $src1, $src2\t#@mulL" %}
6664
6665 ins_encode %{
6666 __ mul(as_Register($dst$$reg),
6667 as_Register($src1$$reg),
6668 as_Register($src2$$reg));
6669 %}
6670
6671 ins_pipe(lmul_reg_reg);
6672 %}
6673
6674 instruct mulHiL_rReg(iRegLNoSp dst, iRegL src1, iRegL src2)
6675 %{
6676 match(Set dst (MulHiL src1 src2));
6677 ins_cost(IMUL_COST);
6678 format %{ "mulh $dst, $src1, $src2\t# mulhi, #@mulHiL_rReg" %}
6679
6680 ins_encode %{
6681 __ mulh(as_Register($dst$$reg),
6682 as_Register($src1$$reg),
6683 as_Register($src2$$reg));
6684 %}
6685
6686 ins_pipe(lmul_reg_reg);
6687 %}
6688
6689 instruct umulHiL_rReg(iRegLNoSp dst, iRegL src1, iRegL src2)
6690 %{
6691 match(Set dst (UMulHiL src1 src2));
6692 ins_cost(IMUL_COST);
6693 format %{ "mulhu $dst, $src1, $src2\t# umulhi, #@umulHiL_rReg" %}
6694
6695 ins_encode %{
6696 __ mulhu(as_Register($dst$$reg),
6697 as_Register($src1$$reg),
6698 as_Register($src2$$reg));
6699 %}
6700
6701 ins_pipe(lmul_reg_reg);
6702 %}
6703
6704 // Integer Divide
6705
6706 instruct divI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6707 match(Set dst (DivI src1 src2));
6708 ins_cost(IDIVSI_COST);
6709 format %{ "divw $dst, $src1, $src2\t#@divI"%}
6710
6711 ins_encode %{
6712 __ divw(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg));
6713 %}
6714 ins_pipe(idiv_reg_reg);
6715 %}
6716
6717 instruct UdivI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6718 match(Set dst (UDivI src1 src2));
6719 ins_cost(IDIVSI_COST);
6720 format %{ "divuw $dst, $src1, $src2\t#@UdivI"%}
6721
6722 ins_encode %{
6723 __ divuw(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg));
6724 %}
6725 ins_pipe(idiv_reg_reg);
6726 %}
6727
6728 instruct signExtract(iRegINoSp dst, iRegIorL2I src1, immI_31 div1, immI_31 div2) %{
6729 match(Set dst (URShiftI (RShiftI src1 div1) div2));
6730 ins_cost(ALU_COST);
6731 format %{ "srliw $dst, $src1, $div1\t# int signExtract, #@signExtract" %}
6732
6733 ins_encode %{
6734 __ srliw(as_Register($dst$$reg), as_Register($src1$$reg), 31);
6735 %}
6736 ins_pipe(ialu_reg_shift);
6737 %}
6738
6739 // Long Divide
6740
6741 instruct divL(iRegLNoSp dst, iRegL src1, iRegL src2) %{
6742 match(Set dst (DivL src1 src2));
6743 ins_cost(IDIVDI_COST);
6744 format %{ "div $dst, $src1, $src2\t#@divL" %}
6745
6746 ins_encode %{
6747 __ div(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg));
6748 %}
6749 ins_pipe(ldiv_reg_reg);
6750 %}
6751
6752 instruct UdivL(iRegLNoSp dst, iRegL src1, iRegL src2) %{
6753 match(Set dst (UDivL src1 src2));
6754 ins_cost(IDIVDI_COST);
6755
6756 format %{ "divu $dst, $src1, $src2\t#@UdivL" %}
6757
6758 ins_encode %{
6759 __ divu(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg));
6760 %}
6761 ins_pipe(ldiv_reg_reg);
6762 %}
6763
6764 instruct signExtractL(iRegLNoSp dst, iRegL src1, immI_63 div1, immI_63 div2) %{
6765 match(Set dst (URShiftL (RShiftL src1 div1) div2));
6766 ins_cost(ALU_COST);
6767 format %{ "srli $dst, $src1, $div1\t# long signExtract, #@signExtractL" %}
6768
6769 ins_encode %{
6770 __ srli(as_Register($dst$$reg), as_Register($src1$$reg), 63);
6771 %}
6772 ins_pipe(ialu_reg_shift);
6773 %}
6774
6775 // Integer Remainder
6776
6777 instruct modI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6778 match(Set dst (ModI src1 src2));
6779 ins_cost(IDIVSI_COST);
6780 format %{ "remw $dst, $src1, $src2\t#@modI" %}
6781
6782 ins_encode %{
6783 __ remw(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg));
6784 %}
6785 ins_pipe(ialu_reg_reg);
6786 %}
6787
6788 instruct UmodI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6789 match(Set dst (UModI src1 src2));
6790 ins_cost(IDIVSI_COST);
6791 format %{ "remuw $dst, $src1, $src2\t#@UmodI" %}
6792
6793 ins_encode %{
6794 __ remuw(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg));
6795 %}
6796 ins_pipe(ialu_reg_reg);
6797 %}
6798
6799 // Long Remainder
6800
6801 instruct modL(iRegLNoSp dst, iRegL src1, iRegL src2) %{
6802 match(Set dst (ModL src1 src2));
6803 ins_cost(IDIVDI_COST);
6804 format %{ "rem $dst, $src1, $src2\t#@modL" %}
6805
6806 ins_encode %{
6807 __ rem(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg));
6808 %}
6809 ins_pipe(ialu_reg_reg);
6810 %}
6811
6812 instruct UmodL(iRegLNoSp dst, iRegL src1, iRegL src2) %{
6813 match(Set dst (UModL src1 src2));
6814 ins_cost(IDIVDI_COST);
6815 format %{ "remu $dst, $src1, $src2\t#@UmodL" %}
6816
6817 ins_encode %{
6818 __ remu(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg));
6819 %}
6820 ins_pipe(ialu_reg_reg);
6821 %}
6822
6823 // Integer Shifts
6824
6825 // Shift Left Register
6826 // In RV64I, only the low 5 bits of src2 are considered for the shift amount
6827 instruct lShiftI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6828 match(Set dst (LShiftI src1 src2));
6829 ins_cost(ALU_COST);
6830 format %{ "sllw $dst, $src1, $src2\t#@lShiftI_reg_reg" %}
6831
6832 ins_encode %{
6833 __ sllw(as_Register($dst$$reg),
6834 as_Register($src1$$reg),
6835 as_Register($src2$$reg));
6836 %}
6837
6838 ins_pipe(ialu_reg_reg_vshift);
6839 %}
6840
6841 // Shift Left Immediate
6842 instruct lShiftI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immI src2) %{
6843 match(Set dst (LShiftI src1 src2));
6844 ins_cost(ALU_COST);
6845 format %{ "slliw $dst, $src1, ($src2 & 0x1f)\t#@lShiftI_reg_imm" %}
6846
6847 ins_encode %{
6848 // the shift amount is encoded in the lower
6849 // 5 bits of the I-immediate field for RV32I
6850 __ slliw(as_Register($dst$$reg),
6851 as_Register($src1$$reg),
6852 (unsigned) $src2$$constant & 0x1f);
6853 %}
6854
6855 ins_pipe(ialu_reg_shift);
6856 %}
6857
6858 // Shift Right Logical Register
6859 // In RV64I, only the low 5 bits of src2 are considered for the shift amount
6860 instruct urShiftI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6861 match(Set dst (URShiftI src1 src2));
6862 ins_cost(ALU_COST);
6863 format %{ "srlw $dst, $src1, $src2\t#@urShiftI_reg_reg" %}
6864
6865 ins_encode %{
6866 __ srlw(as_Register($dst$$reg),
6867 as_Register($src1$$reg),
6868 as_Register($src2$$reg));
6869 %}
6870
6871 ins_pipe(ialu_reg_reg_vshift);
6872 %}
6873
6874 // Shift Right Logical Immediate
6875 instruct urShiftI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immI src2) %{
6876 match(Set dst (URShiftI src1 src2));
6877 ins_cost(ALU_COST);
6878 format %{ "srliw $dst, $src1, ($src2 & 0x1f)\t#@urShiftI_reg_imm" %}
6879
6880 ins_encode %{
6881 // the shift amount is encoded in the lower
6882 // 6 bits of the I-immediate field for RV64I
6883 __ srliw(as_Register($dst$$reg),
6884 as_Register($src1$$reg),
6885 (unsigned) $src2$$constant & 0x1f);
6886 %}
6887
6888 ins_pipe(ialu_reg_shift);
6889 %}
6890
6891 // Shift Right Arithmetic Register
6892 // In RV64I, only the low 5 bits of src2 are considered for the shift amount
6893 instruct rShiftI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6894 match(Set dst (RShiftI src1 src2));
6895 ins_cost(ALU_COST);
6896 format %{ "sraw $dst, $src1, $src2\t#@rShiftI_reg_reg" %}
6897
6898 ins_encode %{
6899 // riscv will sign-ext dst high 32 bits
6900 __ sraw(as_Register($dst$$reg),
6901 as_Register($src1$$reg),
6902 as_Register($src2$$reg));
6903 %}
6904
6905 ins_pipe(ialu_reg_reg_vshift);
6906 %}
6907
6908 // Shift Right Arithmetic Immediate
6909 instruct rShiftI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immI src2) %{
6910 match(Set dst (RShiftI src1 src2));
6911 ins_cost(ALU_COST);
6912 format %{ "sraiw $dst, $src1, ($src2 & 0x1f)\t#@rShiftI_reg_imm" %}
6913
6914 ins_encode %{
6915 // riscv will sign-ext dst high 32 bits
6916 __ sraiw(as_Register($dst$$reg),
6917 as_Register($src1$$reg),
6918 (unsigned) $src2$$constant & 0x1f);
6919 %}
6920
6921 ins_pipe(ialu_reg_shift);
6922 %}
6923
6924 // Long Shifts
6925
6926 // Shift Left Register
6927 // In RV64I, only the low 6 bits of src2 are considered for the shift amount
6928 instruct lShiftL_reg_reg(iRegLNoSp dst, iRegL src1, iRegIorL2I src2) %{
6929 match(Set dst (LShiftL src1 src2));
6930
6931 ins_cost(ALU_COST);
6932 format %{ "sll $dst, $src1, $src2\t#@lShiftL_reg_reg" %}
6933
6934 ins_encode %{
6935 __ sll(as_Register($dst$$reg),
6936 as_Register($src1$$reg),
6937 as_Register($src2$$reg));
6938 %}
6939
6940 ins_pipe(ialu_reg_reg_vshift);
6941 %}
6942
6943 // Shift Left Immediate
6944 instruct lShiftL_reg_imm(iRegLNoSp dst, iRegL src1, immI src2) %{
6945 match(Set dst (LShiftL src1 src2));
6946
6947 ins_cost(ALU_COST);
6948 format %{ "slli $dst, $src1, ($src2 & 0x3f)\t#@lShiftL_reg_imm" %}
6949
6950 ins_encode %{
6951 // the shift amount is encoded in the lower
6952 // 6 bits of the I-immediate field for RV64I
6953 __ slli(as_Register($dst$$reg),
6954 as_Register($src1$$reg),
6955 (unsigned) $src2$$constant & 0x3f);
6956 %}
6957
6958 ins_pipe(ialu_reg_shift);
6959 %}
6960
6961 // Shift Right Logical Register
6962 // In RV64I, only the low 6 bits of src2 are considered for the shift amount
6963 instruct urShiftL_reg_reg(iRegLNoSp dst, iRegL src1, iRegIorL2I src2) %{
6964 match(Set dst (URShiftL src1 src2));
6965
6966 ins_cost(ALU_COST);
6967 format %{ "srl $dst, $src1, $src2\t#@urShiftL_reg_reg" %}
6968
6969 ins_encode %{
6970 __ srl(as_Register($dst$$reg),
6971 as_Register($src1$$reg),
6972 as_Register($src2$$reg));
6973 %}
6974
6975 ins_pipe(ialu_reg_reg_vshift);
6976 %}
6977
6978 // Shift Right Logical Immediate
6979 instruct urShiftL_reg_imm(iRegLNoSp dst, iRegL src1, immI src2) %{
6980 match(Set dst (URShiftL src1 src2));
6981
6982 ins_cost(ALU_COST);
6983 format %{ "srli $dst, $src1, ($src2 & 0x3f)\t#@urShiftL_reg_imm" %}
6984
6985 ins_encode %{
6986 // the shift amount is encoded in the lower
6987 // 6 bits of the I-immediate field for RV64I
6988 __ srli(as_Register($dst$$reg),
6989 as_Register($src1$$reg),
6990 (unsigned) $src2$$constant & 0x3f);
6991 %}
6992
6993 ins_pipe(ialu_reg_shift);
6994 %}
6995
6996 // A special-case pattern for card table stores.
6997 instruct urShiftP_reg_imm(iRegLNoSp dst, iRegP src1, immI src2) %{
6998 match(Set dst (URShiftL (CastP2X src1) src2));
6999
7000 ins_cost(ALU_COST);
7001 format %{ "srli $dst, p2x($src1), ($src2 & 0x3f)\t#@urShiftP_reg_imm" %}
7002
7003 ins_encode %{
7004 // the shift amount is encoded in the lower
7005 // 6 bits of the I-immediate field for RV64I
7006 __ srli(as_Register($dst$$reg),
7007 as_Register($src1$$reg),
7008 (unsigned) $src2$$constant & 0x3f);
7009 %}
7010
7011 ins_pipe(ialu_reg_shift);
7012 %}
7013
7014 // Shift Right Arithmetic Register
7015 // In RV64I, only the low 6 bits of src2 are considered for the shift amount
7016 instruct rShiftL_reg_reg(iRegLNoSp dst, iRegL src1, iRegIorL2I src2) %{
7017 match(Set dst (RShiftL src1 src2));
7018
7019 ins_cost(ALU_COST);
7020 format %{ "sra $dst, $src1, $src2\t#@rShiftL_reg_reg" %}
7021
7022 ins_encode %{
7023 __ sra(as_Register($dst$$reg),
7024 as_Register($src1$$reg),
7025 as_Register($src2$$reg));
7026 %}
7027
7028 ins_pipe(ialu_reg_reg_vshift);
7029 %}
7030
7031 // Shift Right Arithmetic Immediate
7032 instruct rShiftL_reg_imm(iRegLNoSp dst, iRegL src1, immI src2) %{
7033 match(Set dst (RShiftL src1 src2));
7034
7035 ins_cost(ALU_COST);
7036 format %{ "srai $dst, $src1, ($src2 & 0x3f)\t#@rShiftL_reg_imm" %}
7037
7038 ins_encode %{
7039 // the shift amount is encoded in the lower
7040 // 6 bits of the I-immediate field for RV64I
7041 __ srai(as_Register($dst$$reg),
7042 as_Register($src1$$reg),
7043 (unsigned) $src2$$constant & 0x3f);
7044 %}
7045
7046 ins_pipe(ialu_reg_shift);
7047 %}
7048
7049 instruct regI_not_reg(iRegINoSp dst, iRegI src1, immI_M1 m1) %{
7050 match(Set dst (XorI src1 m1));
7051 ins_cost(ALU_COST);
7052 format %{ "xori $dst, $src1, -1\t#@regI_not_reg" %}
7053
7054 ins_encode %{
7055 __ xori(as_Register($dst$$reg), as_Register($src1$$reg), -1);
7056 %}
7057
7058 ins_pipe(ialu_reg_imm);
7059 %}
7060
7061 instruct regL_not_reg(iRegLNoSp dst, iRegL src1, immL_M1 m1) %{
7062 match(Set dst (XorL src1 m1));
7063 ins_cost(ALU_COST);
7064 format %{ "xori $dst, $src1, -1\t#@regL_not_reg" %}
7065
7066 ins_encode %{
7067 __ xori(as_Register($dst$$reg), as_Register($src1$$reg), -1);
7068 %}
7069
7070 ins_pipe(ialu_reg_imm);
7071 %}
7072
7073
7074 // ============================================================================
7075 // Floating Point Arithmetic Instructions
7076
7077 instruct addF_reg_reg(fRegF dst, fRegF src1, fRegF src2) %{
7078 match(Set dst (AddF src1 src2));
7079
7080 ins_cost(DEFAULT_COST * 5);
7081 format %{ "fadd.s $dst, $src1, $src2\t#@addF_reg_reg" %}
7082
7083 ins_encode %{
7084 __ fadd_s(as_FloatRegister($dst$$reg),
7085 as_FloatRegister($src1$$reg),
7086 as_FloatRegister($src2$$reg));
7087 %}
7088
7089 ins_pipe(fp_dop_reg_reg_s);
7090 %}
7091
7092 instruct addD_reg_reg(fRegD dst, fRegD src1, fRegD src2) %{
7093 match(Set dst (AddD src1 src2));
7094
7095 ins_cost(DEFAULT_COST * 5);
7096 format %{ "fadd.d $dst, $src1, $src2\t#@addD_reg_reg" %}
7097
7098 ins_encode %{
7099 __ fadd_d(as_FloatRegister($dst$$reg),
7100 as_FloatRegister($src1$$reg),
7101 as_FloatRegister($src2$$reg));
7102 %}
7103
7104 ins_pipe(fp_dop_reg_reg_d);
7105 %}
7106
7107 instruct subF_reg_reg(fRegF dst, fRegF src1, fRegF src2) %{
7108 match(Set dst (SubF src1 src2));
7109
7110 ins_cost(DEFAULT_COST * 5);
7111 format %{ "fsub.s $dst, $src1, $src2\t#@subF_reg_reg" %}
7112
7113 ins_encode %{
7114 __ fsub_s(as_FloatRegister($dst$$reg),
7115 as_FloatRegister($src1$$reg),
7116 as_FloatRegister($src2$$reg));
7117 %}
7118
7119 ins_pipe(fp_dop_reg_reg_s);
7120 %}
7121
7122 instruct subD_reg_reg(fRegD dst, fRegD src1, fRegD src2) %{
7123 match(Set dst (SubD src1 src2));
7124
7125 ins_cost(DEFAULT_COST * 5);
7126 format %{ "fsub.d $dst, $src1, $src2\t#@subD_reg_reg" %}
7127
7128 ins_encode %{
7129 __ fsub_d(as_FloatRegister($dst$$reg),
7130 as_FloatRegister($src1$$reg),
7131 as_FloatRegister($src2$$reg));
7132 %}
7133
7134 ins_pipe(fp_dop_reg_reg_d);
7135 %}
7136
7137 instruct mulF_reg_reg(fRegF dst, fRegF src1, fRegF src2) %{
7138 match(Set dst (MulF src1 src2));
7139
7140 ins_cost(FMUL_SINGLE_COST);
7141 format %{ "fmul.s $dst, $src1, $src2\t#@mulF_reg_reg" %}
7142
7143 ins_encode %{
7144 __ fmul_s(as_FloatRegister($dst$$reg),
7145 as_FloatRegister($src1$$reg),
7146 as_FloatRegister($src2$$reg));
7147 %}
7148
7149 ins_pipe(fp_dop_reg_reg_s);
7150 %}
7151
7152 instruct mulD_reg_reg(fRegD dst, fRegD src1, fRegD src2) %{
7153 match(Set dst (MulD src1 src2));
7154
7155 ins_cost(FMUL_DOUBLE_COST);
7156 format %{ "fmul.d $dst, $src1, $src2\t#@mulD_reg_reg" %}
7157
7158 ins_encode %{
7159 __ fmul_d(as_FloatRegister($dst$$reg),
7160 as_FloatRegister($src1$$reg),
7161 as_FloatRegister($src2$$reg));
7162 %}
7163
7164 ins_pipe(fp_dop_reg_reg_d);
7165 %}
7166
7167 // src1 * src2 + src3
7168 instruct maddF_reg_reg(fRegF dst, fRegF src1, fRegF src2, fRegF src3) %{
7169 match(Set dst (FmaF src3 (Binary src1 src2)));
7170
7171 ins_cost(FMUL_SINGLE_COST);
7172 format %{ "fmadd.s $dst, $src1, $src2, $src3\t#@maddF_reg_reg" %}
7173
7174 ins_encode %{
7175 assert(UseFMA, "Needs FMA instructions support.");
7176 __ fmadd_s(as_FloatRegister($dst$$reg),
7177 as_FloatRegister($src1$$reg),
7178 as_FloatRegister($src2$$reg),
7179 as_FloatRegister($src3$$reg));
7180 %}
7181
7182 ins_pipe(pipe_class_default);
7183 %}
7184
7185 // src1 * src2 + src3
7186 instruct maddD_reg_reg(fRegD dst, fRegD src1, fRegD src2, fRegD src3) %{
7187 match(Set dst (FmaD src3 (Binary src1 src2)));
7188
7189 ins_cost(FMUL_DOUBLE_COST);
7190 format %{ "fmadd.d $dst, $src1, $src2, $src3\t#@maddD_reg_reg" %}
7191
7192 ins_encode %{
7193 assert(UseFMA, "Needs FMA instructions support.");
7194 __ fmadd_d(as_FloatRegister($dst$$reg),
7195 as_FloatRegister($src1$$reg),
7196 as_FloatRegister($src2$$reg),
7197 as_FloatRegister($src3$$reg));
7198 %}
7199
7200 ins_pipe(pipe_class_default);
7201 %}
7202
7203 // src1 * src2 - src3
7204 instruct msubF_reg_reg(fRegF dst, fRegF src1, fRegF src2, fRegF src3) %{
7205 match(Set dst (FmaF (NegF src3) (Binary src1 src2)));
7206
7207 ins_cost(FMUL_SINGLE_COST);
7208 format %{ "fmsub.s $dst, $src1, $src2, $src3\t#@msubF_reg_reg" %}
7209
7210 ins_encode %{
7211 assert(UseFMA, "Needs FMA instructions support.");
7212 __ fmsub_s(as_FloatRegister($dst$$reg),
7213 as_FloatRegister($src1$$reg),
7214 as_FloatRegister($src2$$reg),
7215 as_FloatRegister($src3$$reg));
7216 %}
7217
7218 ins_pipe(pipe_class_default);
7219 %}
7220
7221 // src1 * src2 - src3
7222 instruct msubD_reg_reg(fRegD dst, fRegD src1, fRegD src2, fRegD src3) %{
7223 match(Set dst (FmaD (NegD src3) (Binary src1 src2)));
7224
7225 ins_cost(FMUL_DOUBLE_COST);
7226 format %{ "fmsub.d $dst, $src1, $src2, $src3\t#@msubD_reg_reg" %}
7227
7228 ins_encode %{
7229 assert(UseFMA, "Needs FMA instructions support.");
7230 __ fmsub_d(as_FloatRegister($dst$$reg),
7231 as_FloatRegister($src1$$reg),
7232 as_FloatRegister($src2$$reg),
7233 as_FloatRegister($src3$$reg));
7234 %}
7235
7236 ins_pipe(pipe_class_default);
7237 %}
7238
7239 // src1 * (-src2) + src3
7240 // "(-src1) * src2 + src3" has been idealized to "src2 * (-src1) + src3"
7241 instruct nmsubF_reg_reg(fRegF dst, fRegF src1, fRegF src2, fRegF src3) %{
7242 match(Set dst (FmaF src3 (Binary src1 (NegF src2))));
7243
7244 ins_cost(FMUL_SINGLE_COST);
7245 format %{ "fnmsub.s $dst, $src1, $src2, $src3\t#@nmsubF_reg_reg" %}
7246
7247 ins_encode %{
7248 assert(UseFMA, "Needs FMA instructions support.");
7249 __ fnmsub_s(as_FloatRegister($dst$$reg),
7250 as_FloatRegister($src1$$reg),
7251 as_FloatRegister($src2$$reg),
7252 as_FloatRegister($src3$$reg));
7253 %}
7254
7255 ins_pipe(pipe_class_default);
7256 %}
7257
7258 // src1 * (-src2) + src3
7259 // "(-src1) * src2 + src3" has been idealized to "src2 * (-src1) + src3"
7260 instruct nmsubD_reg_reg(fRegD dst, fRegD src1, fRegD src2, fRegD src3) %{
7261 match(Set dst (FmaD src3 (Binary src1 (NegD src2))));
7262
7263 ins_cost(FMUL_DOUBLE_COST);
7264 format %{ "fnmsub.d $dst, $src1, $src2, $src3\t#@nmsubD_reg_reg" %}
7265
7266 ins_encode %{
7267 assert(UseFMA, "Needs FMA instructions support.");
7268 __ fnmsub_d(as_FloatRegister($dst$$reg),
7269 as_FloatRegister($src1$$reg),
7270 as_FloatRegister($src2$$reg),
7271 as_FloatRegister($src3$$reg));
7272 %}
7273
7274 ins_pipe(pipe_class_default);
7275 %}
7276
7277 // src1 * (-src2) - src3
7278 // "(-src1) * src2 - src3" has been idealized to "src2 * (-src1) - src3"
7279 instruct nmaddF_reg_reg(fRegF dst, fRegF src1, fRegF src2, fRegF src3) %{
7280 match(Set dst (FmaF (NegF src3) (Binary src1 (NegF src2))));
7281
7282 ins_cost(FMUL_SINGLE_COST);
7283 format %{ "fnmadd.s $dst, $src1, $src2, $src3\t#@nmaddF_reg_reg" %}
7284
7285 ins_encode %{
7286 assert(UseFMA, "Needs FMA instructions support.");
7287 __ fnmadd_s(as_FloatRegister($dst$$reg),
7288 as_FloatRegister($src1$$reg),
7289 as_FloatRegister($src2$$reg),
7290 as_FloatRegister($src3$$reg));
7291 %}
7292
7293 ins_pipe(pipe_class_default);
7294 %}
7295
7296 // src1 * (-src2) - src3
7297 // "(-src1) * src2 - src3" has been idealized to "src2 * (-src1) - src3"
7298 instruct nmaddD_reg_reg(fRegD dst, fRegD src1, fRegD src2, fRegD src3) %{
7299 match(Set dst (FmaD (NegD src3) (Binary src1 (NegD src2))));
7300
7301 ins_cost(FMUL_DOUBLE_COST);
7302 format %{ "fnmadd.d $dst, $src1, $src2, $src3\t#@nmaddD_reg_reg" %}
7303
7304 ins_encode %{
7305 assert(UseFMA, "Needs FMA instructions support.");
7306 __ fnmadd_d(as_FloatRegister($dst$$reg),
7307 as_FloatRegister($src1$$reg),
7308 as_FloatRegister($src2$$reg),
7309 as_FloatRegister($src3$$reg));
7310 %}
7311
7312 ins_pipe(pipe_class_default);
7313 %}
7314
7315 // Math.max(FF)F
7316 instruct maxF_reg_reg(fRegF dst, fRegF src1, fRegF src2, rFlagsReg cr) %{
7317 predicate(!UseZfa);
7318 match(Set dst (MaxF src1 src2));
7319 effect(KILL cr);
7320
7321 format %{ "maxF $dst, $src1, $src2" %}
7322
7323 ins_encode %{
7324 __ minmax_fp(as_FloatRegister($dst$$reg),
7325 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg),
7326 __ FLOAT_TYPE::single_precision, false /* is_min */);
7327 %}
7328
7329 ins_pipe(pipe_class_default);
7330 %}
7331
7332 instruct maxF_reg_reg_zfa(fRegF dst, fRegF src1, fRegF src2) %{
7333 predicate(UseZfa);
7334 match(Set dst (MaxF src1 src2));
7335
7336 format %{ "maxF $dst, $src1, $src2" %}
7337
7338 ins_encode %{
7339 __ fmaxm_s(as_FloatRegister($dst$$reg),
7340 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
7341 %}
7342
7343 ins_pipe(pipe_class_default);
7344 %}
7345
7346 // Math.min(FF)F
7347 instruct minF_reg_reg(fRegF dst, fRegF src1, fRegF src2, rFlagsReg cr) %{
7348 predicate(!UseZfa);
7349 match(Set dst (MinF src1 src2));
7350 effect(KILL cr);
7351
7352 format %{ "minF $dst, $src1, $src2" %}
7353
7354 ins_encode %{
7355 __ minmax_fp(as_FloatRegister($dst$$reg),
7356 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg),
7357 __ FLOAT_TYPE::single_precision, true /* is_min */);
7358 %}
7359
7360 ins_pipe(pipe_class_default);
7361 %}
7362
7363 instruct minF_reg_reg_zfa(fRegF dst, fRegF src1, fRegF src2) %{
7364 predicate(UseZfa);
7365 match(Set dst (MinF src1 src2));
7366
7367 format %{ "minF $dst, $src1, $src2" %}
7368
7369 ins_encode %{
7370 __ fminm_s(as_FloatRegister($dst$$reg),
7371 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
7372 %}
7373
7374 ins_pipe(pipe_class_default);
7375 %}
7376
7377 // Math.max(DD)D
7378 instruct maxD_reg_reg(fRegD dst, fRegD src1, fRegD src2, rFlagsReg cr) %{
7379 predicate(!UseZfa);
7380 match(Set dst (MaxD src1 src2));
7381 effect(KILL cr);
7382
7383 format %{ "maxD $dst, $src1, $src2" %}
7384
7385 ins_encode %{
7386 __ minmax_fp(as_FloatRegister($dst$$reg),
7387 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg),
7388 __ FLOAT_TYPE::double_precision, false /* is_min */);
7389 %}
7390
7391 ins_pipe(pipe_class_default);
7392 %}
7393
7394 instruct maxD_reg_reg_zfa(fRegD dst, fRegD src1, fRegD src2) %{
7395 predicate(UseZfa);
7396 match(Set dst (MaxD src1 src2));
7397
7398 format %{ "maxD $dst, $src1, $src2" %}
7399
7400 ins_encode %{
7401 __ fmaxm_d(as_FloatRegister($dst$$reg),
7402 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
7403 %}
7404
7405 ins_pipe(pipe_class_default);
7406 %}
7407
7408 // Math.min(DD)D
7409 instruct minD_reg_reg(fRegD dst, fRegD src1, fRegD src2, rFlagsReg cr) %{
7410 predicate(!UseZfa);
7411 match(Set dst (MinD src1 src2));
7412 effect(KILL cr);
7413
7414 format %{ "minD $dst, $src1, $src2" %}
7415
7416 ins_encode %{
7417 __ minmax_fp(as_FloatRegister($dst$$reg),
7418 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg),
7419 __ FLOAT_TYPE::double_precision, true /* is_min */);
7420 %}
7421
7422 ins_pipe(pipe_class_default);
7423 %}
7424
7425 instruct minD_reg_reg_zfa(fRegD dst, fRegD src1, fRegD src2) %{
7426 predicate(UseZfa);
7427 match(Set dst (MinD src1 src2));
7428
7429 format %{ "minD $dst, $src1, $src2" %}
7430
7431 ins_encode %{
7432 __ fminm_d(as_FloatRegister($dst$$reg),
7433 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
7434 %}
7435
7436 ins_pipe(pipe_class_default);
7437 %}
7438
7439 // Float.isInfinite
7440 instruct isInfiniteF_reg_reg(iRegINoSp dst, fRegF src)
7441 %{
7442 match(Set dst (IsInfiniteF src));
7443
7444 format %{ "isInfinite $dst, $src" %}
7445 ins_encode %{
7446 __ fclass_s(as_Register($dst$$reg), as_FloatRegister($src$$reg));
7447 __ andi(as_Register($dst$$reg), as_Register($dst$$reg), Assembler::FClassBits::inf);
7448 __ slt(as_Register($dst$$reg), zr, as_Register($dst$$reg));
7449 %}
7450
7451 ins_pipe(pipe_class_default);
7452 %}
7453
7454 // Double.isInfinite
7455 instruct isInfiniteD_reg_reg(iRegINoSp dst, fRegD src)
7456 %{
7457 match(Set dst (IsInfiniteD src));
7458
7459 format %{ "isInfinite $dst, $src" %}
7460 ins_encode %{
7461 __ fclass_d(as_Register($dst$$reg), as_FloatRegister($src$$reg));
7462 __ andi(as_Register($dst$$reg), as_Register($dst$$reg), Assembler::FClassBits::inf);
7463 __ slt(as_Register($dst$$reg), zr, as_Register($dst$$reg));
7464 %}
7465
7466 ins_pipe(pipe_class_default);
7467 %}
7468
7469 // Float.isFinite
7470 instruct isFiniteF_reg_reg(iRegINoSp dst, fRegF src)
7471 %{
7472 match(Set dst (IsFiniteF src));
7473
7474 format %{ "isFinite $dst, $src" %}
7475 ins_encode %{
7476 __ fclass_s(as_Register($dst$$reg), as_FloatRegister($src$$reg));
7477 __ andi(as_Register($dst$$reg), as_Register($dst$$reg), Assembler::FClassBits::finite);
7478 __ slt(as_Register($dst$$reg), zr, as_Register($dst$$reg));
7479 %}
7480
7481 ins_pipe(pipe_class_default);
7482 %}
7483
7484 // Double.isFinite
7485 instruct isFiniteD_reg_reg(iRegINoSp dst, fRegD src)
7486 %{
7487 match(Set dst (IsFiniteD src));
7488
7489 format %{ "isFinite $dst, $src" %}
7490 ins_encode %{
7491 __ fclass_d(as_Register($dst$$reg), as_FloatRegister($src$$reg));
7492 __ andi(as_Register($dst$$reg), as_Register($dst$$reg), Assembler::FClassBits::finite);
7493 __ slt(as_Register($dst$$reg), zr, as_Register($dst$$reg));
7494 %}
7495
7496 ins_pipe(pipe_class_default);
7497 %}
7498
7499 instruct divF_reg_reg(fRegF dst, fRegF src1, fRegF src2) %{
7500 match(Set dst (DivF src1 src2));
7501
7502 ins_cost(FDIV_COST);
7503 format %{ "fdiv.s $dst, $src1, $src2\t#@divF_reg_reg" %}
7504
7505 ins_encode %{
7506 __ fdiv_s(as_FloatRegister($dst$$reg),
7507 as_FloatRegister($src1$$reg),
7508 as_FloatRegister($src2$$reg));
7509 %}
7510
7511 ins_pipe(fp_div_s);
7512 %}
7513
7514 instruct divD_reg_reg(fRegD dst, fRegD src1, fRegD src2) %{
7515 match(Set dst (DivD src1 src2));
7516
7517 ins_cost(FDIV_COST);
7518 format %{ "fdiv.d $dst, $src1, $src2\t#@divD_reg_reg" %}
7519
7520 ins_encode %{
7521 __ fdiv_d(as_FloatRegister($dst$$reg),
7522 as_FloatRegister($src1$$reg),
7523 as_FloatRegister($src2$$reg));
7524 %}
7525
7526 ins_pipe(fp_div_d);
7527 %}
7528
7529 instruct negF_reg_reg(fRegF dst, fRegF src) %{
7530 match(Set dst (NegF src));
7531
7532 ins_cost(XFER_COST);
7533 format %{ "fsgnjn.s $dst, $src, $src\t#@negF_reg_reg" %}
7534
7535 ins_encode %{
7536 __ fneg_s(as_FloatRegister($dst$$reg),
7537 as_FloatRegister($src$$reg));
7538 %}
7539
7540 ins_pipe(fp_uop_s);
7541 %}
7542
7543 instruct negD_reg_reg(fRegD dst, fRegD src) %{
7544 match(Set dst (NegD src));
7545
7546 ins_cost(XFER_COST);
7547 format %{ "fsgnjn.d $dst, $src, $src\t#@negD_reg_reg" %}
7548
7549 ins_encode %{
7550 __ fneg_d(as_FloatRegister($dst$$reg),
7551 as_FloatRegister($src$$reg));
7552 %}
7553
7554 ins_pipe(fp_uop_d);
7555 %}
7556
7557 instruct absI_reg(iRegINoSp dst, iRegIorL2I src) %{
7558 match(Set dst (AbsI src));
7559
7560 ins_cost(ALU_COST * 3);
7561 format %{
7562 "sraiw t0, $src, 0x1f\n\t"
7563 "addw $dst, $src, t0\n\t"
7564 "xorr $dst, $dst, t0\t#@absI_reg"
7565 %}
7566
7567 ins_encode %{
7568 __ sraiw(t0, as_Register($src$$reg), 0x1f);
7569 __ addw(as_Register($dst$$reg), as_Register($src$$reg), t0);
7570 __ xorr(as_Register($dst$$reg), as_Register($dst$$reg), t0);
7571 %}
7572
7573 ins_pipe(pipe_class_default);
7574 %}
7575
7576 instruct absL_reg(iRegLNoSp dst, iRegL src) %{
7577 match(Set dst (AbsL src));
7578
7579 ins_cost(ALU_COST * 3);
7580 format %{
7581 "srai t0, $src, 0x3f\n\t"
7582 "add $dst, $src, t0\n\t"
7583 "xorr $dst, $dst, t0\t#@absL_reg"
7584 %}
7585
7586 ins_encode %{
7587 __ srai(t0, as_Register($src$$reg), 0x3f);
7588 __ add(as_Register($dst$$reg), as_Register($src$$reg), t0);
7589 __ xorr(as_Register($dst$$reg), as_Register($dst$$reg), t0);
7590 %}
7591
7592 ins_pipe(pipe_class_default);
7593 %}
7594
7595 instruct absF_reg(fRegF dst, fRegF src) %{
7596 match(Set dst (AbsF src));
7597
7598 ins_cost(XFER_COST);
7599 format %{ "fsgnjx.s $dst, $src, $src\t#@absF_reg" %}
7600 ins_encode %{
7601 __ fabs_s(as_FloatRegister($dst$$reg),
7602 as_FloatRegister($src$$reg));
7603 %}
7604
7605 ins_pipe(fp_uop_s);
7606 %}
7607
7608 instruct absD_reg(fRegD dst, fRegD src) %{
7609 match(Set dst (AbsD src));
7610
7611 ins_cost(XFER_COST);
7612 format %{ "fsgnjx.d $dst, $src, $src\t#@absD_reg" %}
7613 ins_encode %{
7614 __ fabs_d(as_FloatRegister($dst$$reg),
7615 as_FloatRegister($src$$reg));
7616 %}
7617
7618 ins_pipe(fp_uop_d);
7619 %}
7620
7621 instruct sqrtF_reg(fRegF dst, fRegF src) %{
7622 match(Set dst (SqrtF src));
7623
7624 ins_cost(FSQRT_COST);
7625 format %{ "fsqrt.s $dst, $src\t#@sqrtF_reg" %}
7626 ins_encode %{
7627 __ fsqrt_s(as_FloatRegister($dst$$reg),
7628 as_FloatRegister($src$$reg));
7629 %}
7630
7631 ins_pipe(fp_sqrt_s);
7632 %}
7633
7634 instruct sqrtD_reg(fRegD dst, fRegD src) %{
7635 match(Set dst (SqrtD src));
7636
7637 ins_cost(FSQRT_COST);
7638 format %{ "fsqrt.d $dst, $src\t#@sqrtD_reg" %}
7639 ins_encode %{
7640 __ fsqrt_d(as_FloatRegister($dst$$reg),
7641 as_FloatRegister($src$$reg));
7642 %}
7643
7644 ins_pipe(fp_sqrt_d);
7645 %}
7646
7647 // Round Instruction
7648 instruct roundD_reg(fRegD dst, fRegD src, immI rmode, iRegLNoSp tmp1, iRegLNoSp tmp2, iRegLNoSp tmp3) %{
7649 match(Set dst (RoundDoubleMode src rmode));
7650 ins_cost(2 * XFER_COST + BRANCH_COST);
7651 effect(TEMP_DEF dst, TEMP tmp1, TEMP tmp2, TEMP tmp3);
7652
7653 format %{ "RoundDoubleMode $src, $rmode" %}
7654 ins_encode %{
7655 __ round_double_mode(as_FloatRegister($dst$$reg),
7656 as_FloatRegister($src$$reg), $rmode$$constant, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
7657 %}
7658 ins_pipe(pipe_class_default);
7659 %}
7660
7661 // Copysign and signum intrinsics
7662
7663 instruct copySignD_reg(fRegD dst, fRegD src1, fRegD src2, immD zero) %{
7664 match(Set dst (CopySignD src1 (Binary src2 zero)));
7665 format %{ "CopySignD $dst $src1 $src2" %}
7666 ins_encode %{
7667 FloatRegister dst = as_FloatRegister($dst$$reg),
7668 src1 = as_FloatRegister($src1$$reg),
7669 src2 = as_FloatRegister($src2$$reg);
7670 __ fsgnj_d(dst, src1, src2);
7671 %}
7672 ins_pipe(fp_dop_reg_reg_d);
7673 %}
7674
7675 instruct copySignF_reg(fRegF dst, fRegF src1, fRegF src2) %{
7676 match(Set dst (CopySignF src1 src2));
7677 format %{ "CopySignF $dst $src1 $src2" %}
7678 ins_encode %{
7679 FloatRegister dst = as_FloatRegister($dst$$reg),
7680 src1 = as_FloatRegister($src1$$reg),
7681 src2 = as_FloatRegister($src2$$reg);
7682 __ fsgnj_s(dst, src1, src2);
7683 %}
7684 ins_pipe(fp_dop_reg_reg_s);
7685 %}
7686
7687 instruct signumD_reg(fRegD dst, immD zero, fRegD one) %{
7688 match(Set dst (SignumD dst (Binary zero one)));
7689 format %{ "signumD $dst, $dst" %}
7690 ins_encode %{
7691 __ signum_fp(as_FloatRegister($dst$$reg), as_FloatRegister($one$$reg), true /* is_double */);
7692 %}
7693 ins_pipe(pipe_class_default);
7694 %}
7695
7696 instruct signumF_reg(fRegF dst, immF zero, fRegF one) %{
7697 match(Set dst (SignumF dst (Binary zero one)));
7698 format %{ "signumF $dst, $dst" %}
7699 ins_encode %{
7700 __ signum_fp(as_FloatRegister($dst$$reg), as_FloatRegister($one$$reg), false /* is_double */);
7701 %}
7702 ins_pipe(pipe_class_default);
7703 %}
7704
7705 // Arithmetic Instructions End
7706
7707 // ============================================================================
7708 // Logical Instructions
7709
7710 // Register And
7711 instruct andI_reg_reg(iRegINoSp dst, iRegI src1, iRegI src2) %{
7712 match(Set dst (AndI src1 src2));
7713
7714 format %{ "andr $dst, $src1, $src2\t#@andI_reg_reg" %}
7715
7716 ins_cost(ALU_COST);
7717 ins_encode %{
7718 __ andr(as_Register($dst$$reg),
7719 as_Register($src1$$reg),
7720 as_Register($src2$$reg));
7721 %}
7722
7723 ins_pipe(ialu_reg_reg);
7724 %}
7725
7726 // Immediate And
7727 instruct andI_reg_imm(iRegINoSp dst, iRegI src1, immIAdd src2) %{
7728 match(Set dst (AndI src1 src2));
7729
7730 format %{ "andi $dst, $src1, $src2\t#@andI_reg_imm" %}
7731
7732 ins_cost(ALU_COST);
7733 ins_encode %{
7734 __ andi(as_Register($dst$$reg),
7735 as_Register($src1$$reg),
7736 (int32_t)($src2$$constant));
7737 %}
7738
7739 ins_pipe(ialu_reg_imm);
7740 %}
7741
7742 // Register Or
7743 instruct orI_reg_reg(iRegINoSp dst, iRegI src1, iRegI src2) %{
7744 match(Set dst (OrI src1 src2));
7745
7746 format %{ "orr $dst, $src1, $src2\t#@orI_reg_reg" %}
7747
7748 ins_cost(ALU_COST);
7749 ins_encode %{
7750 __ orr(as_Register($dst$$reg),
7751 as_Register($src1$$reg),
7752 as_Register($src2$$reg));
7753 %}
7754
7755 ins_pipe(ialu_reg_reg);
7756 %}
7757
7758 // Immediate Or
7759 instruct orI_reg_imm(iRegINoSp dst, iRegI src1, immIAdd src2) %{
7760 match(Set dst (OrI src1 src2));
7761
7762 format %{ "ori $dst, $src1, $src2\t#@orI_reg_imm" %}
7763
7764 ins_cost(ALU_COST);
7765 ins_encode %{
7766 __ ori(as_Register($dst$$reg),
7767 as_Register($src1$$reg),
7768 (int32_t)($src2$$constant));
7769 %}
7770
7771 ins_pipe(ialu_reg_imm);
7772 %}
7773
7774 // Register Xor
7775 instruct xorI_reg_reg(iRegINoSp dst, iRegI src1, iRegI src2) %{
7776 match(Set dst (XorI src1 src2));
7777
7778 format %{ "xorr $dst, $src1, $src2\t#@xorI_reg_reg" %}
7779
7780 ins_cost(ALU_COST);
7781 ins_encode %{
7782 __ xorr(as_Register($dst$$reg),
7783 as_Register($src1$$reg),
7784 as_Register($src2$$reg));
7785 %}
7786
7787 ins_pipe(ialu_reg_reg);
7788 %}
7789
7790 // Immediate Xor
7791 instruct xorI_reg_imm(iRegINoSp dst, iRegI src1, immIAdd src2) %{
7792 match(Set dst (XorI src1 src2));
7793
7794 format %{ "xori $dst, $src1, $src2\t#@xorI_reg_imm" %}
7795
7796 ins_cost(ALU_COST);
7797 ins_encode %{
7798 __ xori(as_Register($dst$$reg),
7799 as_Register($src1$$reg),
7800 (int32_t)($src2$$constant));
7801 %}
7802
7803 ins_pipe(ialu_reg_imm);
7804 %}
7805
7806 // Register And Long
7807 instruct andL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
7808 match(Set dst (AndL src1 src2));
7809
7810 format %{ "andr $dst, $src1, $src2\t#@andL_reg_reg" %}
7811
7812 ins_cost(ALU_COST);
7813 ins_encode %{
7814 __ andr(as_Register($dst$$reg),
7815 as_Register($src1$$reg),
7816 as_Register($src2$$reg));
7817 %}
7818
7819 ins_pipe(ialu_reg_reg);
7820 %}
7821
7822 // Immediate And Long
7823 instruct andL_reg_imm(iRegLNoSp dst, iRegL src1, immLAdd src2) %{
7824 match(Set dst (AndL src1 src2));
7825
7826 format %{ "andi $dst, $src1, $src2\t#@andL_reg_imm" %}
7827
7828 ins_cost(ALU_COST);
7829 ins_encode %{
7830 __ andi(as_Register($dst$$reg),
7831 as_Register($src1$$reg),
7832 (int32_t)($src2$$constant));
7833 %}
7834
7835 ins_pipe(ialu_reg_imm);
7836 %}
7837
7838 // Register Or Long
7839 instruct orL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
7840 match(Set dst (OrL src1 src2));
7841
7842 format %{ "orr $dst, $src1, $src2\t#@orL_reg_reg" %}
7843
7844 ins_cost(ALU_COST);
7845 ins_encode %{
7846 __ orr(as_Register($dst$$reg),
7847 as_Register($src1$$reg),
7848 as_Register($src2$$reg));
7849 %}
7850
7851 ins_pipe(ialu_reg_reg);
7852 %}
7853
7854 // Immediate Or Long
7855 instruct orL_reg_imm(iRegLNoSp dst, iRegL src1, immLAdd src2) %{
7856 match(Set dst (OrL src1 src2));
7857
7858 format %{ "ori $dst, $src1, $src2\t#@orL_reg_imm" %}
7859
7860 ins_cost(ALU_COST);
7861 ins_encode %{
7862 __ ori(as_Register($dst$$reg),
7863 as_Register($src1$$reg),
7864 (int32_t)($src2$$constant));
7865 %}
7866
7867 ins_pipe(ialu_reg_imm);
7868 %}
7869
7870 // Register Xor Long
7871 instruct xorL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
7872 match(Set dst (XorL src1 src2));
7873
7874 format %{ "xorr $dst, $src1, $src2\t#@xorL_reg_reg" %}
7875
7876 ins_cost(ALU_COST);
7877 ins_encode %{
7878 __ xorr(as_Register($dst$$reg),
7879 as_Register($src1$$reg),
7880 as_Register($src2$$reg));
7881 %}
7882
7883 ins_pipe(ialu_reg_reg);
7884 %}
7885
7886 // Immediate Xor Long
7887 instruct xorL_reg_imm(iRegLNoSp dst, iRegL src1, immLAdd src2) %{
7888 match(Set dst (XorL src1 src2));
7889
7890 ins_cost(ALU_COST);
7891 format %{ "xori $dst, $src1, $src2\t#@xorL_reg_imm" %}
7892
7893 ins_encode %{
7894 __ xori(as_Register($dst$$reg),
7895 as_Register($src1$$reg),
7896 (int32_t)($src2$$constant));
7897 %}
7898
7899 ins_pipe(ialu_reg_imm);
7900 %}
7901
7902 // ============================================================================
7903 // MemBar Instruction
7904
7905 instruct load_fence() %{
7906 match(LoadFence);
7907 ins_cost(ALU_COST);
7908
7909 format %{ "#@load_fence" %}
7910
7911 ins_encode %{
7912 __ membar(MacroAssembler::LoadLoad | MacroAssembler::LoadStore);
7913 %}
7914 ins_pipe(pipe_serial);
7915 %}
7916
7917 instruct membar_acquire() %{
7918 match(MemBarAcquire);
7919 ins_cost(ALU_COST);
7920
7921 format %{ "#@membar_acquire\n\t"
7922 "fence ir iorw" %}
7923
7924 ins_encode %{
7925 __ block_comment("membar_acquire");
7926 __ membar(MacroAssembler::LoadLoad | MacroAssembler::LoadStore);
7927 %}
7928
7929 ins_pipe(pipe_serial);
7930 %}
7931
7932 instruct membar_acquire_lock() %{
7933 match(MemBarAcquireLock);
7934 ins_cost(0);
7935
7936 format %{ "#@membar_acquire_lock (elided)" %}
7937
7938 ins_encode %{
7939 __ block_comment("membar_acquire_lock (elided)");
7940 %}
7941
7942 ins_pipe(pipe_serial);
7943 %}
7944
7945 instruct store_fence() %{
7946 match(StoreFence);
7947 ins_cost(ALU_COST);
7948
7949 format %{ "#@store_fence" %}
7950
7951 ins_encode %{
7952 __ membar(MacroAssembler::LoadStore | MacroAssembler::StoreStore);
7953 %}
7954 ins_pipe(pipe_serial);
7955 %}
7956
7957 instruct membar_release() %{
7958 match(MemBarRelease);
7959 ins_cost(ALU_COST);
7960
7961 format %{ "#@membar_release\n\t"
7962 "fence iorw ow" %}
7963
7964 ins_encode %{
7965 __ block_comment("membar_release");
7966 __ membar(MacroAssembler::LoadStore | MacroAssembler::StoreStore);
7967 %}
7968 ins_pipe(pipe_serial);
7969 %}
7970
7971 instruct membar_storestore() %{
7972 match(MemBarStoreStore);
7973 match(StoreStoreFence);
7974 ins_cost(ALU_COST);
7975
7976 format %{ "MEMBAR-store-store\t#@membar_storestore" %}
7977
7978 ins_encode %{
7979 __ membar(MacroAssembler::StoreStore);
7980 %}
7981 ins_pipe(pipe_serial);
7982 %}
7983
7984 instruct membar_release_lock() %{
7985 match(MemBarReleaseLock);
7986 ins_cost(0);
7987
7988 format %{ "#@membar_release_lock (elided)" %}
7989
7990 ins_encode %{
7991 __ block_comment("membar_release_lock (elided)");
7992 %}
7993
7994 ins_pipe(pipe_serial);
7995 %}
7996
7997 instruct membar_volatile() %{
7998 match(MemBarVolatile);
7999 ins_cost(ALU_COST);
8000
8001 format %{ "#@membar_volatile\n\t"
8002 "fence iorw iorw"%}
8003
8004 ins_encode %{
8005 __ block_comment("membar_volatile");
8006 __ membar(MacroAssembler::StoreLoad);
8007 %}
8008
8009 ins_pipe(pipe_serial);
8010 %}
8011
8012 instruct spin_wait() %{
8013 predicate(UseZihintpause);
8014 match(OnSpinWait);
8015 ins_cost(CACHE_MISS_COST);
8016
8017 format %{ "spin_wait" %}
8018
8019 ins_encode %{
8020 __ pause();
8021 %}
8022
8023 ins_pipe(pipe_serial);
8024 %}
8025
8026 // ============================================================================
8027 // Cast Instructions (Java-level type cast)
8028
8029 instruct castX2P(iRegPNoSp dst, iRegL src) %{
8030 match(Set dst (CastX2P src));
8031
8032 ins_cost(ALU_COST);
8033 format %{ "mv $dst, $src\t# long -> ptr, #@castX2P" %}
8034
8035 ins_encode %{
8036 if ($dst$$reg != $src$$reg) {
8037 __ mv(as_Register($dst$$reg), as_Register($src$$reg));
8038 }
8039 %}
8040
8041 ins_pipe(ialu_reg);
8042 %}
8043
8044 instruct castP2X(iRegLNoSp dst, iRegP src) %{
8045 match(Set dst (CastP2X src));
8046
8047 ins_cost(ALU_COST);
8048 format %{ "mv $dst, $src\t# ptr -> long, #@castP2X" %}
8049
8050 ins_encode %{
8051 if ($dst$$reg != $src$$reg) {
8052 __ mv(as_Register($dst$$reg), as_Register($src$$reg));
8053 }
8054 %}
8055
8056 ins_pipe(ialu_reg);
8057 %}
8058
8059 instruct castPP(iRegPNoSp dst)
8060 %{
8061 match(Set dst (CastPP dst));
8062 ins_cost(0);
8063
8064 size(0);
8065 format %{ "# castPP of $dst, #@castPP" %}
8066 ins_encode(/* empty encoding */);
8067 ins_pipe(pipe_class_empty);
8068 %}
8069
8070 instruct castLL(iRegL dst)
8071 %{
8072 match(Set dst (CastLL dst));
8073
8074 size(0);
8075 format %{ "# castLL of $dst, #@castLL" %}
8076 ins_encode(/* empty encoding */);
8077 ins_cost(0);
8078 ins_pipe(pipe_class_empty);
8079 %}
8080
8081 instruct castII(iRegI dst)
8082 %{
8083 match(Set dst (CastII dst));
8084
8085 size(0);
8086 format %{ "# castII of $dst, #@castII" %}
8087 ins_encode(/* empty encoding */);
8088 ins_cost(0);
8089 ins_pipe(pipe_class_empty);
8090 %}
8091
8092 instruct checkCastPP(iRegPNoSp dst)
8093 %{
8094 match(Set dst (CheckCastPP dst));
8095
8096 size(0);
8097 ins_cost(0);
8098 format %{ "# checkcastPP of $dst, #@checkCastPP" %}
8099 ins_encode(/* empty encoding */);
8100 ins_pipe(pipe_class_empty);
8101 %}
8102
8103 instruct castHH(fRegF dst)
8104 %{
8105 match(Set dst (CastHH dst));
8106
8107 size(0);
8108 format %{ "# castHH of $dst" %}
8109 ins_encode(/* empty encoding */);
8110 ins_cost(0);
8111 ins_pipe(pipe_class_empty);
8112 %}
8113
8114 instruct castFF(fRegF dst)
8115 %{
8116 match(Set dst (CastFF dst));
8117
8118 size(0);
8119 format %{ "# castFF of $dst" %}
8120 ins_encode(/* empty encoding */);
8121 ins_cost(0);
8122 ins_pipe(pipe_class_empty);
8123 %}
8124
8125 instruct castDD(fRegD dst)
8126 %{
8127 match(Set dst (CastDD dst));
8128
8129 size(0);
8130 format %{ "# castDD of $dst" %}
8131 ins_encode(/* empty encoding */);
8132 ins_cost(0);
8133 ins_pipe(pipe_class_empty);
8134 %}
8135
8136 instruct castVV(vReg dst)
8137 %{
8138 match(Set dst (CastVV dst));
8139
8140 size(0);
8141 format %{ "# castVV of $dst" %}
8142 ins_encode(/* empty encoding */);
8143 ins_cost(0);
8144 ins_pipe(pipe_class_empty);
8145 %}
8146
8147 // ============================================================================
8148 // Convert Instructions
8149
8150 // int to bool
8151 instruct convI2Bool(iRegINoSp dst, iRegI src)
8152 %{
8153 match(Set dst (Conv2B src));
8154
8155 ins_cost(ALU_COST);
8156 format %{ "snez $dst, $src\t#@convI2Bool" %}
8157
8158 ins_encode %{
8159 __ snez(as_Register($dst$$reg), as_Register($src$$reg));
8160 %}
8161
8162 ins_pipe(ialu_reg);
8163 %}
8164
8165 // pointer to bool
8166 instruct convP2Bool(iRegINoSp dst, iRegP src)
8167 %{
8168 match(Set dst (Conv2B src));
8169
8170 ins_cost(ALU_COST);
8171 format %{ "snez $dst, $src\t#@convP2Bool" %}
8172
8173 ins_encode %{
8174 __ snez(as_Register($dst$$reg), as_Register($src$$reg));
8175 %}
8176
8177 ins_pipe(ialu_reg);
8178 %}
8179
8180 // int <-> long
8181
8182 instruct convI2L_reg_reg(iRegLNoSp dst, iRegIorL2I src)
8183 %{
8184 match(Set dst (ConvI2L src));
8185
8186 ins_cost(ALU_COST);
8187 format %{ "addw $dst, $src, zr\t#@convI2L_reg_reg" %}
8188 ins_encode %{
8189 __ sext(as_Register($dst$$reg), as_Register($src$$reg), 32);
8190 %}
8191 ins_pipe(ialu_reg);
8192 %}
8193
8194 instruct convL2I_reg(iRegINoSp dst, iRegL src) %{
8195 match(Set dst (ConvL2I src));
8196
8197 ins_cost(ALU_COST);
8198 format %{ "addw $dst, $src, zr\t#@convL2I_reg" %}
8199
8200 ins_encode %{
8201 __ sext(as_Register($dst$$reg), as_Register($src$$reg), 32);
8202 %}
8203
8204 ins_pipe(ialu_reg);
8205 %}
8206
8207 // int to unsigned long (Zero-extend)
8208 instruct convI2UL_reg_reg(iRegLNoSp dst, iRegIorL2I src, immL_32bits mask)
8209 %{
8210 match(Set dst (AndL (ConvI2L src) mask));
8211
8212 ins_cost(ALU_COST * 2);
8213 format %{ "zext $dst, $src, 32\t# i2ul, #@convI2UL_reg_reg" %}
8214
8215 ins_encode %{
8216 __ zext(as_Register($dst$$reg), as_Register($src$$reg), 32);
8217 %}
8218
8219 ins_pipe(ialu_reg_shift);
8220 %}
8221
8222 // float <-> double
8223
8224 instruct convF2D_reg(fRegD dst, fRegF src) %{
8225 match(Set dst (ConvF2D src));
8226
8227 ins_cost(XFER_COST);
8228 format %{ "fcvt.d.s $dst, $src\t#@convF2D_reg" %}
8229
8230 ins_encode %{
8231 __ fcvt_d_s(as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg));
8232 %}
8233
8234 ins_pipe(fp_f2d);
8235 %}
8236
8237 instruct convD2F_reg(fRegF dst, fRegD src) %{
8238 match(Set dst (ConvD2F src));
8239
8240 ins_cost(XFER_COST);
8241 format %{ "fcvt.s.d $dst, $src\t#@convD2F_reg" %}
8242
8243 ins_encode %{
8244 __ fcvt_s_d(as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg));
8245 %}
8246
8247 ins_pipe(fp_d2f);
8248 %}
8249
8250 // single <-> half precision
8251
8252 instruct convHF2F_reg_reg(fRegF dst, iRegINoSp src, iRegINoSp tmp) %{
8253 match(Set dst (ConvHF2F src));
8254 effect(TEMP tmp);
8255 format %{ "fmv.h.x $dst, $src\t# move source from $src to $dst\n\t"
8256 "fcvt.s.h $dst, $dst\t# convert half to single precision"
8257 %}
8258 ins_encode %{
8259 __ float16_to_float($dst$$FloatRegister, $src$$Register, $tmp$$Register);
8260 %}
8261 ins_pipe(pipe_slow);
8262 %}
8263
8264 instruct convF2HF_reg_reg(iRegINoSp dst, fRegF src, fRegF ftmp, iRegINoSp xtmp) %{
8265 match(Set dst (ConvF2HF src));
8266 effect(TEMP_DEF dst, TEMP ftmp, TEMP xtmp);
8267 format %{ "fcvt.h.s $ftmp, $src\t# convert single precision to half\n\t"
8268 "fmv.x.h $dst, $ftmp\t# move result from $ftmp to $dst"
8269 %}
8270 ins_encode %{
8271 __ float_to_float16($dst$$Register, $src$$FloatRegister, $ftmp$$FloatRegister, $xtmp$$Register);
8272 %}
8273 ins_pipe(pipe_slow);
8274 %}
8275
8276 // half precision operations
8277
8278 instruct reinterpretS2HF(fRegF dst, iRegI src)
8279 %{
8280 match(Set dst (ReinterpretS2HF src));
8281 format %{ "fmv.h.x $dst, $src" %}
8282 ins_encode %{
8283 __ fmv_h_x($dst$$FloatRegister, $src$$Register);
8284 %}
8285 ins_pipe(fp_i2f);
8286 %}
8287
8288 instruct convF2HFAndS2HF(fRegF dst, fRegF src)
8289 %{
8290 match(Set dst (ReinterpretS2HF (ConvF2HF src)));
8291 format %{ "convF2HFAndS2HF $dst, $src" %}
8292 ins_encode %{
8293 __ fcvt_h_s($dst$$FloatRegister, $src$$FloatRegister);
8294 %}
8295 ins_pipe(fp_uop_s);
8296 %}
8297
8298 instruct reinterpretHF2S(iRegINoSp dst, fRegF src)
8299 %{
8300 match(Set dst (ReinterpretHF2S src));
8301 format %{ "fmv.x.h $dst, $src" %}
8302 ins_encode %{
8303 __ fmv_x_h($dst$$Register, $src$$FloatRegister);
8304 %}
8305 ins_pipe(fp_f2i);
8306 %}
8307
8308 instruct convHF2SAndHF2F(fRegF dst, fRegF src)
8309 %{
8310 match(Set dst (ConvHF2F (ReinterpretHF2S src)));
8311 format %{ "convHF2SAndHF2F $dst, $src" %}
8312 ins_encode %{
8313 __ fcvt_s_h($dst$$FloatRegister, $src$$FloatRegister);
8314 %}
8315 ins_pipe(fp_uop_s);
8316 %}
8317
8318 instruct sqrt_HF_reg(fRegF dst, fRegF src)
8319 %{
8320 match(Set dst (SqrtHF src));
8321 format %{ "fsqrt.h $dst, $src" %}
8322 ins_encode %{
8323 __ fsqrt_h($dst$$FloatRegister, $src$$FloatRegister);
8324 %}
8325 ins_pipe(fp_sqrt_s);
8326 %}
8327
8328 instruct binOps_HF_reg(fRegF dst, fRegF src1, fRegF src2)
8329 %{
8330 match(Set dst (AddHF src1 src2));
8331 match(Set dst (SubHF src1 src2));
8332 match(Set dst (MulHF src1 src2));
8333 match(Set dst (DivHF src1 src2));
8334 format %{ "binop_hf $dst, $src1, $src2" %}
8335 ins_encode %{
8336 int opcode = this->ideal_Opcode();
8337 switch(opcode) {
8338 case Op_AddHF: __ fadd_h($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); break;
8339 case Op_SubHF: __ fsub_h($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); break;
8340 case Op_MulHF: __ fmul_h($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); break;
8341 case Op_DivHF: __ fdiv_h($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); break;
8342 default: assert(false, "%s is not supported here", NodeClassNames[opcode]); break;
8343 }
8344 %}
8345 ins_pipe(fp_dop_reg_reg_s);
8346 %}
8347
8348 instruct min_HF_reg(fRegF dst, fRegF src1, fRegF src2, rFlagsReg cr)
8349 %{
8350 predicate(!UseZfa);
8351 match(Set dst (MinHF src1 src2));
8352 effect(KILL cr);
8353
8354 format %{ "min_hf $dst, $src1, $src2" %}
8355
8356 ins_encode %{
8357 __ minmax_fp($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister,
8358 __ FLOAT_TYPE::half_precision, true /* is_min */);
8359 %}
8360 ins_pipe(pipe_class_default);
8361 %}
8362
8363 instruct min_HF_reg_zfa(fRegF dst, fRegF src1, fRegF src2)
8364 %{
8365 predicate(UseZfa);
8366 match(Set dst (MinHF src1 src2));
8367
8368 format %{ "min_hf $dst, $src1, $src2" %}
8369
8370 ins_encode %{
8371 __ fminm_h(as_FloatRegister($dst$$reg),
8372 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
8373 %}
8374
8375 ins_pipe(pipe_class_default);
8376 %}
8377
8378 instruct max_HF_reg(fRegF dst, fRegF src1, fRegF src2, rFlagsReg cr)
8379 %{
8380 predicate(!UseZfa);
8381 match(Set dst (MaxHF src1 src2));
8382 effect(KILL cr);
8383
8384 format %{ "max_hf $dst, $src1, $src2" %}
8385
8386 ins_encode %{
8387 __ minmax_fp($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister,
8388 __ FLOAT_TYPE::half_precision, false /* is_min */);
8389 %}
8390 ins_pipe(pipe_class_default);
8391 %}
8392
8393 instruct max_HF_reg_zfa(fRegF dst, fRegF src1, fRegF src2)
8394 %{
8395 predicate(UseZfa);
8396 match(Set dst (MaxHF src1 src2));
8397
8398 format %{ "max_hf $dst, $src1, $src2" %}
8399
8400 ins_encode %{
8401 __ fmaxm_h(as_FloatRegister($dst$$reg),
8402 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
8403 %}
8404
8405 ins_pipe(pipe_class_default);
8406 %}
8407
8408 instruct fma_HF_reg(fRegF dst, fRegF src1, fRegF src2, fRegF src3)
8409 %{
8410 match(Set dst (FmaHF src3 (Binary src1 src2)));
8411 format %{ "fmadd.h $dst, $src1, $src2, $src3\t# $dst = $src1 * $src2 + $src3 fma packedH" %}
8412 ins_encode %{
8413 __ fmadd_h($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister, $src3$$FloatRegister);
8414 %}
8415 ins_pipe(pipe_class_default);
8416 %}
8417
8418 // float <-> int
8419
8420 instruct convF2I_reg_reg(iRegINoSp dst, fRegF src) %{
8421 match(Set dst (ConvF2I src));
8422
8423 ins_cost(XFER_COST);
8424 format %{ "fcvt.w.s $dst, $src\t#@convF2I_reg_reg" %}
8425
8426 ins_encode %{
8427 __ fcvt_w_s_safe($dst$$Register, $src$$FloatRegister);
8428 %}
8429
8430 ins_pipe(fp_f2i);
8431 %}
8432
8433 instruct convI2F_reg_reg(fRegF dst, iRegIorL2I src) %{
8434 match(Set dst (ConvI2F src));
8435
8436 ins_cost(XFER_COST);
8437 format %{ "fcvt.s.w $dst, $src\t#@convI2F_reg_reg" %}
8438
8439 ins_encode %{
8440 __ fcvt_s_w(as_FloatRegister($dst$$reg), as_Register($src$$reg));
8441 %}
8442
8443 ins_pipe(fp_i2f);
8444 %}
8445
8446 // float <-> long
8447
8448 instruct convF2L_reg_reg(iRegLNoSp dst, fRegF src) %{
8449 match(Set dst (ConvF2L src));
8450
8451 ins_cost(XFER_COST);
8452 format %{ "fcvt.l.s $dst, $src\t#@convF2L_reg_reg" %}
8453
8454 ins_encode %{
8455 __ fcvt_l_s_safe($dst$$Register, $src$$FloatRegister);
8456 %}
8457
8458 ins_pipe(fp_f2l);
8459 %}
8460
8461 instruct convL2F_reg_reg(fRegF dst, iRegL src) %{
8462 match(Set dst (ConvL2F src));
8463
8464 ins_cost(XFER_COST);
8465 format %{ "fcvt.s.l $dst, $src\t#@convL2F_reg_reg" %}
8466
8467 ins_encode %{
8468 __ fcvt_s_l(as_FloatRegister($dst$$reg), as_Register($src$$reg));
8469 %}
8470
8471 ins_pipe(fp_l2f);
8472 %}
8473
8474 // double <-> int
8475
8476 instruct convD2I_reg_reg(iRegINoSp dst, fRegD src) %{
8477 match(Set dst (ConvD2I src));
8478
8479 ins_cost(XFER_COST);
8480 format %{ "fcvt.w.d $dst, $src\t#@convD2I_reg_reg" %}
8481
8482 ins_encode %{
8483 __ fcvt_w_d_safe($dst$$Register, $src$$FloatRegister);
8484 %}
8485
8486 ins_pipe(fp_d2i);
8487 %}
8488
8489 instruct convI2D_reg_reg(fRegD dst, iRegIorL2I src) %{
8490 match(Set dst (ConvI2D src));
8491
8492 ins_cost(XFER_COST);
8493 format %{ "fcvt.d.w $dst, $src\t#@convI2D_reg_reg" %}
8494
8495 ins_encode %{
8496 __ fcvt_d_w(as_FloatRegister($dst$$reg), as_Register($src$$reg));
8497 %}
8498
8499 ins_pipe(fp_i2d);
8500 %}
8501
8502 // double <-> long
8503
8504 instruct convD2L_reg_reg(iRegLNoSp dst, fRegD src) %{
8505 match(Set dst (ConvD2L src));
8506
8507 ins_cost(XFER_COST);
8508 format %{ "fcvt.l.d $dst, $src\t#@convD2L_reg_reg" %}
8509
8510 ins_encode %{
8511 __ fcvt_l_d_safe($dst$$Register, $src$$FloatRegister);
8512 %}
8513
8514 ins_pipe(fp_d2l);
8515 %}
8516
8517 instruct convL2D_reg_reg(fRegD dst, iRegL src) %{
8518 match(Set dst (ConvL2D src));
8519
8520 ins_cost(XFER_COST);
8521 format %{ "fcvt.d.l $dst, $src\t#@convL2D_reg_reg" %}
8522
8523 ins_encode %{
8524 __ fcvt_d_l(as_FloatRegister($dst$$reg), as_Register($src$$reg));
8525 %}
8526
8527 ins_pipe(fp_l2d);
8528 %}
8529
8530 // Convert oop into int for vectors alignment masking
8531 instruct convP2I(iRegINoSp dst, iRegP src) %{
8532 match(Set dst (ConvL2I (CastP2X src)));
8533
8534 ins_cost(ALU_COST * 2);
8535 format %{ "zext $dst, $src, 32\t# ptr -> int, #@convP2I" %}
8536
8537 ins_encode %{
8538 __ zext($dst$$Register, $src$$Register, 32);
8539 %}
8540
8541 ins_pipe(ialu_reg);
8542 %}
8543
8544 // Convert compressed oop into int for vectors alignment masking
8545 // in case of 32bit oops (heap < 4Gb).
8546 instruct convN2I(iRegINoSp dst, iRegN src)
8547 %{
8548 predicate(CompressedOops::shift() == 0);
8549 match(Set dst (ConvL2I (CastP2X (DecodeN src))));
8550
8551 ins_cost(ALU_COST);
8552 format %{ "mv $dst, $src\t# compressed ptr -> int, #@convN2I" %}
8553
8554 ins_encode %{
8555 __ mv($dst$$Register, $src$$Register);
8556 %}
8557
8558 ins_pipe(ialu_reg);
8559 %}
8560
8561 instruct round_double_reg(iRegLNoSp dst, fRegD src, fRegD ftmp) %{
8562 match(Set dst (RoundD src));
8563
8564 ins_cost(XFER_COST + BRANCH_COST);
8565 effect(TEMP ftmp);
8566 format %{ "java_round_double $dst, $src\t#@round_double_reg" %}
8567
8568 ins_encode %{
8569 __ java_round_double($dst$$Register, as_FloatRegister($src$$reg), as_FloatRegister($ftmp$$reg));
8570 %}
8571
8572 ins_pipe(pipe_slow);
8573 %}
8574
8575 instruct round_float_reg(iRegINoSp dst, fRegF src, fRegF ftmp) %{
8576 match(Set dst (RoundF src));
8577
8578 ins_cost(XFER_COST + BRANCH_COST);
8579 effect(TEMP ftmp);
8580 format %{ "java_round_float $dst, $src\t#@round_float_reg" %}
8581
8582 ins_encode %{
8583 __ java_round_float($dst$$Register, as_FloatRegister($src$$reg), as_FloatRegister($ftmp$$reg));
8584 %}
8585
8586 ins_pipe(pipe_slow);
8587 %}
8588
8589 // Convert oop pointer into compressed form
8590 instruct encodeHeapOop(iRegNNoSp dst, iRegP src) %{
8591 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
8592 match(Set dst (EncodeP src));
8593 ins_cost(ALU_COST);
8594 format %{ "encode_heap_oop $dst, $src\t#@encodeHeapOop" %}
8595 ins_encode %{
8596 Register s = $src$$Register;
8597 Register d = $dst$$Register;
8598 __ encode_heap_oop(d, s);
8599 %}
8600 ins_pipe(pipe_class_default);
8601 %}
8602
8603 instruct encodeHeapOop_not_null(iRegNNoSp dst, iRegP src) %{
8604 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
8605 match(Set dst (EncodeP src));
8606 ins_cost(ALU_COST);
8607 format %{ "encode_heap_oop_not_null $dst, $src\t#@encodeHeapOop_not_null" %}
8608 ins_encode %{
8609 __ encode_heap_oop_not_null($dst$$Register, $src$$Register);
8610 %}
8611 ins_pipe(pipe_class_default);
8612 %}
8613
8614 instruct decodeHeapOop(iRegPNoSp dst, iRegN src) %{
8615 predicate(n->bottom_type()->is_ptr()->ptr() != TypePtr::NotNull &&
8616 n->bottom_type()->is_ptr()->ptr() != TypePtr::Constant);
8617 match(Set dst (DecodeN src));
8618
8619 ins_cost(0);
8620 format %{ "decode_heap_oop $dst, $src\t#@decodeHeapOop" %}
8621 ins_encode %{
8622 Register s = $src$$Register;
8623 Register d = $dst$$Register;
8624 __ decode_heap_oop(d, s);
8625 %}
8626 ins_pipe(pipe_class_default);
8627 %}
8628
8629 instruct decodeHeapOop_not_null(iRegPNoSp dst, iRegN src) %{
8630 predicate(n->bottom_type()->is_ptr()->ptr() == TypePtr::NotNull ||
8631 n->bottom_type()->is_ptr()->ptr() == TypePtr::Constant);
8632 match(Set dst (DecodeN src));
8633
8634 ins_cost(0);
8635 format %{ "decode_heap_oop_not_null $dst, $src\t#@decodeHeapOop_not_null" %}
8636 ins_encode %{
8637 Register s = $src$$Register;
8638 Register d = $dst$$Register;
8639 __ decode_heap_oop_not_null(d, s);
8640 %}
8641 ins_pipe(pipe_class_default);
8642 %}
8643
8644 // Convert klass pointer into compressed form.
8645 instruct encodeKlass_not_null(iRegNNoSp dst, iRegP src) %{
8646 match(Set dst (EncodePKlass src));
8647
8648 ins_cost(ALU_COST);
8649 format %{ "encode_klass_not_null $dst, $src\t#@encodeKlass_not_null" %}
8650
8651 ins_encode %{
8652 Register src_reg = as_Register($src$$reg);
8653 Register dst_reg = as_Register($dst$$reg);
8654 __ encode_klass_not_null(dst_reg, src_reg, t0);
8655 %}
8656
8657 ins_pipe(pipe_class_default);
8658 %}
8659
8660 instruct decodeKlass_not_null(iRegPNoSp dst, iRegN src, iRegPNoSp tmp) %{
8661 match(Set dst (DecodeNKlass src));
8662
8663 effect(TEMP tmp);
8664
8665 ins_cost(ALU_COST);
8666 format %{ "decode_klass_not_null $dst, $src\t#@decodeKlass_not_null" %}
8667
8668 ins_encode %{
8669 Register src_reg = as_Register($src$$reg);
8670 Register dst_reg = as_Register($dst$$reg);
8671 Register tmp_reg = as_Register($tmp$$reg);
8672 __ decode_klass_not_null(dst_reg, src_reg, tmp_reg);
8673 %}
8674
8675 ins_pipe(pipe_class_default);
8676 %}
8677
8678 // stack <-> reg and reg <-> reg shuffles with no conversion
8679
8680 instruct MoveF2I_stack_reg(iRegINoSp dst, stackSlotF src) %{
8681
8682 match(Set dst (MoveF2I src));
8683
8684 effect(DEF dst, USE src);
8685
8686 ins_cost(LOAD_COST);
8687
8688 format %{ "lw $dst, $src\t#@MoveF2I_stack_reg" %}
8689
8690 ins_encode %{
8691 __ lw(as_Register($dst$$reg), Address(sp, $src$$disp));
8692 %}
8693
8694 ins_pipe(iload_reg_reg);
8695
8696 %}
8697
8698 instruct MoveI2F_stack_reg(fRegF dst, stackSlotI src) %{
8699
8700 match(Set dst (MoveI2F src));
8701
8702 effect(DEF dst, USE src);
8703
8704 ins_cost(LOAD_COST);
8705
8706 format %{ "flw $dst, $src\t#@MoveI2F_stack_reg" %}
8707
8708 ins_encode %{
8709 __ flw(as_FloatRegister($dst$$reg), Address(sp, $src$$disp));
8710 %}
8711
8712 ins_pipe(fp_load_mem_s);
8713
8714 %}
8715
8716 instruct MoveD2L_stack_reg(iRegLNoSp dst, stackSlotD src) %{
8717
8718 match(Set dst (MoveD2L src));
8719
8720 effect(DEF dst, USE src);
8721
8722 ins_cost(LOAD_COST);
8723
8724 format %{ "ld $dst, $src\t#@MoveD2L_stack_reg" %}
8725
8726 ins_encode %{
8727 __ ld(as_Register($dst$$reg), Address(sp, $src$$disp));
8728 %}
8729
8730 ins_pipe(iload_reg_reg);
8731
8732 %}
8733
8734 instruct MoveL2D_stack_reg(fRegD dst, stackSlotL src) %{
8735
8736 match(Set dst (MoveL2D src));
8737
8738 effect(DEF dst, USE src);
8739
8740 ins_cost(LOAD_COST);
8741
8742 format %{ "fld $dst, $src\t#@MoveL2D_stack_reg" %}
8743
8744 ins_encode %{
8745 __ fld(as_FloatRegister($dst$$reg), Address(sp, $src$$disp));
8746 %}
8747
8748 ins_pipe(fp_load_mem_d);
8749
8750 %}
8751
8752 instruct MoveF2I_reg_stack(stackSlotI dst, fRegF src) %{
8753
8754 match(Set dst (MoveF2I src));
8755
8756 effect(DEF dst, USE src);
8757
8758 ins_cost(STORE_COST);
8759
8760 format %{ "fsw $src, $dst\t#@MoveF2I_reg_stack" %}
8761
8762 ins_encode %{
8763 __ fsw(as_FloatRegister($src$$reg), Address(sp, $dst$$disp));
8764 %}
8765
8766 ins_pipe(fp_store_reg_s);
8767
8768 %}
8769
8770 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{
8771
8772 match(Set dst (MoveI2F src));
8773
8774 effect(DEF dst, USE src);
8775
8776 ins_cost(STORE_COST);
8777
8778 format %{ "sw $src, $dst\t#@MoveI2F_reg_stack" %}
8779
8780 ins_encode %{
8781 __ sw(as_Register($src$$reg), Address(sp, $dst$$disp));
8782 %}
8783
8784 ins_pipe(istore_reg_reg);
8785
8786 %}
8787
8788 instruct MoveD2L_reg_stack(stackSlotL dst, fRegD src) %{
8789
8790 match(Set dst (MoveD2L src));
8791
8792 effect(DEF dst, USE src);
8793
8794 ins_cost(STORE_COST);
8795
8796 format %{ "fsd $dst, $src\t#@MoveD2L_reg_stack" %}
8797
8798 ins_encode %{
8799 __ fsd(as_FloatRegister($src$$reg), Address(sp, $dst$$disp));
8800 %}
8801
8802 ins_pipe(fp_store_reg_d);
8803
8804 %}
8805
8806 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{
8807
8808 match(Set dst (MoveL2D src));
8809
8810 effect(DEF dst, USE src);
8811
8812 ins_cost(STORE_COST);
8813
8814 format %{ "sd $src, $dst\t#@MoveL2D_reg_stack" %}
8815
8816 ins_encode %{
8817 __ sd(as_Register($src$$reg), Address(sp, $dst$$disp));
8818 %}
8819
8820 ins_pipe(istore_reg_reg);
8821
8822 %}
8823
8824 instruct MoveF2I_reg_reg(iRegINoSp dst, fRegF src) %{
8825
8826 match(Set dst (MoveF2I src));
8827
8828 effect(DEF dst, USE src);
8829
8830 ins_cost(FMVX_COST);
8831
8832 format %{ "fmv.x.w $dst, $src\t#@MoveF2I_reg_reg" %}
8833
8834 ins_encode %{
8835 __ fmv_x_w(as_Register($dst$$reg), as_FloatRegister($src$$reg));
8836 %}
8837
8838 ins_pipe(fp_f2i);
8839
8840 %}
8841
8842 instruct MoveI2F_reg_reg(fRegF dst, iRegI src) %{
8843
8844 match(Set dst (MoveI2F src));
8845
8846 effect(DEF dst, USE src);
8847
8848 ins_cost(FMVX_COST);
8849
8850 format %{ "fmv.w.x $dst, $src\t#@MoveI2F_reg_reg" %}
8851
8852 ins_encode %{
8853 __ fmv_w_x(as_FloatRegister($dst$$reg), as_Register($src$$reg));
8854 %}
8855
8856 ins_pipe(fp_i2f);
8857
8858 %}
8859
8860 instruct MoveD2L_reg_reg(iRegLNoSp dst, fRegD src) %{
8861
8862 match(Set dst (MoveD2L src));
8863
8864 effect(DEF dst, USE src);
8865
8866 ins_cost(FMVX_COST);
8867
8868 format %{ "fmv.x.d $dst, $src\t#@MoveD2L_reg_reg" %}
8869
8870 ins_encode %{
8871 __ fmv_x_d(as_Register($dst$$reg), as_FloatRegister($src$$reg));
8872 %}
8873
8874 ins_pipe(fp_d2l);
8875
8876 %}
8877
8878 instruct MoveL2D_reg_reg(fRegD dst, iRegL src) %{
8879
8880 match(Set dst (MoveL2D src));
8881
8882 effect(DEF dst, USE src);
8883
8884 ins_cost(FMVX_COST);
8885
8886 format %{ "fmv.d.x $dst, $src\t#@MoveL2D_reg_reg" %}
8887
8888 ins_encode %{
8889 __ fmv_d_x(as_FloatRegister($dst$$reg), as_Register($src$$reg));
8890 %}
8891
8892 ins_pipe(fp_l2d);
8893
8894 %}
8895
8896 // ============================================================================
8897 // Compare Instructions which set the result float comparisons in dest register.
8898
8899 instruct cmpF3_reg_reg(iRegINoSp dst, fRegF op1, fRegF op2)
8900 %{
8901 match(Set dst (CmpF3 op1 op2));
8902
8903 ins_cost(XFER_COST * 2 + BRANCH_COST + ALU_COST);
8904 format %{ "flt.s $dst, $op2, $op1\t#@cmpF3_reg_reg\n\t"
8905 "bgtz $dst, done\n\t"
8906 "feq.s $dst, $op1, $op2\n\t"
8907 "addi $dst, $dst, -1\n\t"
8908 "done:"
8909 %}
8910
8911 ins_encode %{
8912 // we want -1 for unordered or less than, 0 for equal and 1 for greater than.
8913 __ float_compare(as_Register($dst$$reg), as_FloatRegister($op1$$reg),
8914 as_FloatRegister($op2$$reg), -1 /*unordered_result < 0*/);
8915 %}
8916
8917 ins_pipe(pipe_class_default);
8918 %}
8919
8920 instruct cmpD3_reg_reg(iRegINoSp dst, fRegD op1, fRegD op2)
8921 %{
8922 match(Set dst (CmpD3 op1 op2));
8923
8924 ins_cost(XFER_COST * 2 + BRANCH_COST + ALU_COST);
8925 format %{ "flt.d $dst, $op2, $op1\t#@cmpD3_reg_reg\n\t"
8926 "bgtz $dst, done\n\t"
8927 "feq.d $dst, $op1, $op2\n\t"
8928 "addi $dst, $dst, -1\n\t"
8929 "done:"
8930 %}
8931
8932 ins_encode %{
8933 // we want -1 for unordered or less than, 0 for equal and 1 for greater than.
8934 __ double_compare(as_Register($dst$$reg), as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg), -1 /*unordered_result < 0*/);
8935 %}
8936
8937 ins_pipe(pipe_class_default);
8938 %}
8939
8940 instruct cmpL3_reg_reg(iRegINoSp dst, iRegL op1, iRegL op2)
8941 %{
8942 match(Set dst (CmpL3 op1 op2));
8943
8944 ins_cost(ALU_COST * 3 + BRANCH_COST);
8945 format %{ "slt $dst, $op2, $op1\t#@cmpL3_reg_reg\n\t"
8946 "bnez $dst, done\n\t"
8947 "slt $dst, $op1, $op2\n\t"
8948 "neg $dst, $dst\n\t"
8949 "done:"
8950 %}
8951 ins_encode %{
8952 __ cmp_l2i(t0, as_Register($op1$$reg), as_Register($op2$$reg));
8953 __ mv(as_Register($dst$$reg), t0);
8954 %}
8955
8956 ins_pipe(pipe_class_default);
8957 %}
8958
8959 instruct cmpUL3_reg_reg(iRegINoSp dst, iRegL op1, iRegL op2)
8960 %{
8961 match(Set dst (CmpUL3 op1 op2));
8962
8963 ins_cost(ALU_COST * 3 + BRANCH_COST);
8964 format %{ "sltu $dst, $op2, $op1\t#@cmpUL3_reg_reg\n\t"
8965 "bnez $dst, done\n\t"
8966 "sltu $dst, $op1, $op2\n\t"
8967 "neg $dst, $dst\n\t"
8968 "done:"
8969 %}
8970 ins_encode %{
8971 __ cmp_ul2i(t0, as_Register($op1$$reg), as_Register($op2$$reg));
8972 __ mv(as_Register($dst$$reg), t0);
8973 %}
8974
8975 ins_pipe(pipe_class_default);
8976 %}
8977
8978 instruct cmpU3_reg_reg(iRegINoSp dst, iRegI op1, iRegI op2)
8979 %{
8980 match(Set dst (CmpU3 op1 op2));
8981
8982 ins_cost(ALU_COST * 3 + BRANCH_COST);
8983 format %{ "sltu $dst, $op2, $op1\t#@cmpU3_reg_reg\n\t"
8984 "bnez $dst, done\n\t"
8985 "sltu $dst, $op1, $op2\n\t"
8986 "neg $dst, $dst\n\t"
8987 "done:"
8988 %}
8989 ins_encode %{
8990 __ cmp_uw2i(t0, as_Register($op1$$reg), as_Register($op2$$reg));
8991 __ mv(as_Register($dst$$reg), t0);
8992 %}
8993
8994 ins_pipe(pipe_class_default);
8995 %}
8996
8997 instruct cmpLTMask_reg_reg(iRegINoSp dst, iRegI p, iRegI q)
8998 %{
8999 match(Set dst (CmpLTMask p q));
9000
9001 ins_cost(2 * ALU_COST);
9002
9003 format %{ "slt $dst, $p, $q\t#@cmpLTMask_reg_reg\n\t"
9004 "subw $dst, zr, $dst\t#@cmpLTMask_reg_reg"
9005 %}
9006
9007 ins_encode %{
9008 __ slt(as_Register($dst$$reg), as_Register($p$$reg), as_Register($q$$reg));
9009 __ subw(as_Register($dst$$reg), zr, as_Register($dst$$reg));
9010 %}
9011
9012 ins_pipe(ialu_reg_reg);
9013 %}
9014
9015 instruct cmpLTMask_reg_zero(iRegINoSp dst, iRegIorL2I op, immI0 zero)
9016 %{
9017 match(Set dst (CmpLTMask op zero));
9018
9019 ins_cost(ALU_COST);
9020
9021 format %{ "sraiw $dst, $dst, 31\t#@cmpLTMask_reg_reg" %}
9022
9023 ins_encode %{
9024 __ sraiw(as_Register($dst$$reg), as_Register($op$$reg), 31);
9025 %}
9026
9027 ins_pipe(ialu_reg_shift);
9028 %}
9029
9030
9031 // ============================================================================
9032 // Max and Min
9033
9034 instruct minI_reg_reg(iRegINoSp dst, iRegI src)
9035 %{
9036 match(Set dst (MinI dst src));
9037
9038 ins_cost(BRANCH_COST + ALU_COST);
9039 format %{"minI_reg_reg $dst, $dst, $src\t#@minI_reg_reg\n\t"%}
9040
9041 ins_encode %{
9042 __ cmov_gt(as_Register($dst$$reg), as_Register($src$$reg),
9043 as_Register($dst$$reg), as_Register($src$$reg));
9044 %}
9045
9046 ins_pipe(pipe_class_compare);
9047 %}
9048
9049 instruct maxI_reg_reg(iRegINoSp dst, iRegI src)
9050 %{
9051 match(Set dst (MaxI dst src));
9052
9053 ins_cost(BRANCH_COST + ALU_COST);
9054 format %{"maxI_reg_reg $dst, $dst, $src\t#@maxI_reg_reg\n\t"%}
9055
9056 ins_encode %{
9057 __ cmov_lt(as_Register($dst$$reg), as_Register($src$$reg),
9058 as_Register($dst$$reg), as_Register($src$$reg));
9059 %}
9060
9061 ins_pipe(pipe_class_compare);
9062 %}
9063
9064 // special case for comparing with zero
9065 // n.b. this is selected in preference to the rule above because it
9066 // avoids loading constant 0 into a source register
9067
9068 instruct minI_reg_zero(iRegINoSp dst, immI0 zero)
9069 %{
9070 match(Set dst (MinI dst zero));
9071 match(Set dst (MinI zero dst));
9072
9073 ins_cost(BRANCH_COST + ALU_COST);
9074 format %{"minI_reg_zero $dst, $dst, zr\t#@minI_reg_zero\n\t"%}
9075
9076 ins_encode %{
9077 __ cmov_gt(as_Register($dst$$reg), zr,
9078 as_Register($dst$$reg), zr);
9079 %}
9080
9081 ins_pipe(pipe_class_compare);
9082 %}
9083
9084 instruct maxI_reg_zero(iRegINoSp dst, immI0 zero)
9085 %{
9086 match(Set dst (MaxI dst zero));
9087 match(Set dst (MaxI zero dst));
9088
9089 ins_cost(BRANCH_COST + ALU_COST);
9090 format %{"maxI_reg_zero $dst, $dst, zr\t#@maxI_reg_zero\n\t"%}
9091
9092 ins_encode %{
9093 __ cmov_lt(as_Register($dst$$reg), zr,
9094 as_Register($dst$$reg), zr);
9095 %}
9096
9097 ins_pipe(pipe_class_compare);
9098 %}
9099
9100 instruct minI_rReg(iRegINoSp dst, iRegI src1, iRegI src2)
9101 %{
9102 match(Set dst (MinI src1 src2));
9103
9104 effect(DEF dst, USE src1, USE src2);
9105
9106 ins_cost(BRANCH_COST + ALU_COST * 2);
9107 format %{"minI_rReg $dst, $src1, $src2\t#@minI_rReg\n\t"%}
9108
9109 ins_encode %{
9110 __ mv(as_Register($dst$$reg), as_Register($src1$$reg));
9111 __ cmov_gt(as_Register($src1$$reg), as_Register($src2$$reg),
9112 as_Register($dst$$reg), as_Register($src2$$reg));
9113 %}
9114
9115 ins_pipe(pipe_class_compare);
9116 %}
9117
9118 instruct maxI_rReg(iRegINoSp dst, iRegI src1, iRegI src2)
9119 %{
9120 match(Set dst (MaxI src1 src2));
9121
9122 effect(DEF dst, USE src1, USE src2);
9123
9124 ins_cost(BRANCH_COST + ALU_COST * 2);
9125 format %{"maxI_rReg $dst, $src1, $src2\t#@maxI_rReg\n\t"%}
9126
9127 ins_encode %{
9128 __ mv(as_Register($dst$$reg), as_Register($src1$$reg));
9129 __ cmov_lt(as_Register($src1$$reg), as_Register($src2$$reg),
9130 as_Register($dst$$reg), as_Register($src2$$reg));
9131 %}
9132
9133 ins_pipe(pipe_class_compare);
9134 %}
9135
9136 // ============================================================================
9137 // Branch Instructions
9138 // Direct Branch.
9139 instruct branch(label lbl)
9140 %{
9141 match(Goto);
9142
9143 effect(USE lbl);
9144
9145 ins_cost(BRANCH_COST);
9146 format %{ "j $lbl\t#@branch" %}
9147
9148 ins_encode(riscv_enc_j(lbl));
9149
9150 ins_pipe(pipe_branch);
9151 %}
9152
9153 // ============================================================================
9154 // Compare and Branch Instructions
9155
9156 // Patterns for short (< 12KiB) variants
9157
9158 // Compare flags and branch near instructions.
9159 instruct cmpFlag_branch(cmpOpEqNe cmp, rFlagsReg cr, label lbl) %{
9160 match(If cmp cr);
9161 effect(USE lbl);
9162
9163 ins_cost(BRANCH_COST);
9164 format %{ "b$cmp $cr, zr, $lbl\t#@cmpFlag_branch" %}
9165
9166 ins_encode %{
9167 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($cr$$reg), *($lbl$$label));
9168 %}
9169 ins_pipe(pipe_cmpz_branch);
9170 ins_short_branch(1);
9171 %}
9172
9173 // Compare signed int and branch near instructions
9174 instruct cmpI_branch(cmpOp cmp, iRegI op1, iRegI op2, label lbl)
9175 %{
9176 // Same match rule as `far_cmpI_branch'.
9177 match(If cmp (CmpI op1 op2));
9178
9179 effect(USE lbl);
9180
9181 ins_cost(BRANCH_COST);
9182
9183 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpI_branch" %}
9184
9185 ins_encode %{
9186 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label));
9187 %}
9188
9189 ins_pipe(pipe_cmp_branch);
9190 ins_short_branch(1);
9191 %}
9192
9193 instruct cmpI_loop(cmpOp cmp, iRegI op1, iRegI op2, label lbl)
9194 %{
9195 // Same match rule as `far_cmpI_loop'.
9196 match(CountedLoopEnd cmp (CmpI op1 op2));
9197
9198 effect(USE lbl);
9199
9200 ins_cost(BRANCH_COST);
9201
9202 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpI_loop" %}
9203
9204 ins_encode %{
9205 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label));
9206 %}
9207
9208 ins_pipe(pipe_cmp_branch);
9209 ins_short_branch(1);
9210 %}
9211
9212 // Compare unsigned int and branch near instructions
9213 instruct cmpU_branch(cmpOpU cmp, iRegI op1, iRegI op2, label lbl)
9214 %{
9215 // Same match rule as `far_cmpU_branch'.
9216 match(If cmp (CmpU op1 op2));
9217
9218 effect(USE lbl);
9219
9220 ins_cost(BRANCH_COST);
9221
9222 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpU_branch" %}
9223
9224 ins_encode %{
9225 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9226 as_Register($op2$$reg), *($lbl$$label));
9227 %}
9228
9229 ins_pipe(pipe_cmp_branch);
9230 ins_short_branch(1);
9231 %}
9232
9233 // Compare signed long and branch near instructions
9234 instruct cmpL_branch(cmpOp cmp, iRegL op1, iRegL op2, label lbl)
9235 %{
9236 // Same match rule as `far_cmpL_branch'.
9237 match(If cmp (CmpL op1 op2));
9238
9239 effect(USE lbl);
9240
9241 ins_cost(BRANCH_COST);
9242
9243 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpL_branch" %}
9244
9245 ins_encode %{
9246 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label));
9247 %}
9248
9249 ins_pipe(pipe_cmp_branch);
9250 ins_short_branch(1);
9251 %}
9252
9253 instruct cmpL_loop(cmpOp cmp, iRegL op1, iRegL op2, label lbl)
9254 %{
9255 // Same match rule as `far_cmpL_loop'.
9256 match(CountedLoopEnd cmp (CmpL op1 op2));
9257
9258 effect(USE lbl);
9259
9260 ins_cost(BRANCH_COST);
9261
9262 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpL_loop" %}
9263
9264 ins_encode %{
9265 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label));
9266 %}
9267
9268 ins_pipe(pipe_cmp_branch);
9269 ins_short_branch(1);
9270 %}
9271
9272 // Compare unsigned long and branch near instructions
9273 instruct cmpUL_branch(cmpOpU cmp, iRegL op1, iRegL op2, label lbl)
9274 %{
9275 // Same match rule as `far_cmpUL_branch'.
9276 match(If cmp (CmpUL op1 op2));
9277
9278 effect(USE lbl);
9279
9280 ins_cost(BRANCH_COST);
9281 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpUL_branch" %}
9282
9283 ins_encode %{
9284 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9285 as_Register($op2$$reg), *($lbl$$label));
9286 %}
9287
9288 ins_pipe(pipe_cmp_branch);
9289 ins_short_branch(1);
9290 %}
9291
9292 // Compare pointer and branch near instructions
9293 instruct cmpP_branch(cmpOpU cmp, iRegP op1, iRegP op2, label lbl)
9294 %{
9295 // Same match rule as `far_cmpP_branch'.
9296 match(If cmp (CmpP op1 op2));
9297
9298 effect(USE lbl);
9299
9300 ins_cost(BRANCH_COST);
9301
9302 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpP_branch" %}
9303
9304 ins_encode %{
9305 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9306 as_Register($op2$$reg), *($lbl$$label));
9307 %}
9308
9309 ins_pipe(pipe_cmp_branch);
9310 ins_short_branch(1);
9311 %}
9312
9313 // Compare narrow pointer and branch near instructions
9314 instruct cmpN_branch(cmpOpU cmp, iRegN op1, iRegN op2, label lbl)
9315 %{
9316 // Same match rule as `far_cmpN_branch'.
9317 match(If cmp (CmpN op1 op2));
9318
9319 effect(USE lbl);
9320
9321 ins_cost(BRANCH_COST);
9322
9323 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpN_branch" %}
9324
9325 ins_encode %{
9326 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9327 as_Register($op2$$reg), *($lbl$$label));
9328 %}
9329
9330 ins_pipe(pipe_cmp_branch);
9331 ins_short_branch(1);
9332 %}
9333
9334 // Compare float and branch near instructions
9335 instruct cmpF_branch(cmpOp cmp, fRegF op1, fRegF op2, label lbl)
9336 %{
9337 // Same match rule as `far_cmpF_branch'.
9338 match(If cmp (CmpF op1 op2));
9339
9340 effect(USE lbl);
9341
9342 ins_cost(XFER_COST + BRANCH_COST);
9343 format %{ "float_b$cmp $op1, $op2, $lbl \t#@cmpF_branch"%}
9344
9345 ins_encode %{
9346 __ float_cmp_branch($cmp$$cmpcode, as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg), *($lbl$$label));
9347 %}
9348
9349 ins_pipe(pipe_class_compare);
9350 ins_short_branch(1);
9351 %}
9352
9353 // Compare double and branch near instructions
9354 instruct cmpD_branch(cmpOp cmp, fRegD op1, fRegD op2, label lbl)
9355 %{
9356 // Same match rule as `far_cmpD_branch'.
9357 match(If cmp (CmpD op1 op2));
9358 effect(USE lbl);
9359
9360 ins_cost(XFER_COST + BRANCH_COST);
9361 format %{ "double_b$cmp $op1, $op2, $lbl\t#@cmpD_branch"%}
9362
9363 ins_encode %{
9364 __ float_cmp_branch($cmp$$cmpcode | C2_MacroAssembler::double_branch_mask, as_FloatRegister($op1$$reg),
9365 as_FloatRegister($op2$$reg), *($lbl$$label));
9366 %}
9367
9368 ins_pipe(pipe_class_compare);
9369 ins_short_branch(1);
9370 %}
9371
9372 // Compare signed int with zero and branch near instructions
9373 instruct cmpI_reg_imm0_branch(cmpOp cmp, iRegI op1, immI0 zero, label lbl)
9374 %{
9375 // Same match rule as `far_cmpI_reg_imm0_branch'.
9376 match(If cmp (CmpI op1 zero));
9377
9378 effect(USE op1, USE lbl);
9379
9380 ins_cost(BRANCH_COST);
9381 format %{ "b$cmp $op1, zr, $lbl\t#@cmpI_reg_imm0_branch" %}
9382
9383 ins_encode %{
9384 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label));
9385 %}
9386
9387 ins_pipe(pipe_cmpz_branch);
9388 ins_short_branch(1);
9389 %}
9390
9391 instruct cmpI_reg_imm0_loop(cmpOp cmp, iRegI op1, immI0 zero, label lbl)
9392 %{
9393 // Same match rule as `far_cmpI_reg_imm0_loop'.
9394 match(CountedLoopEnd cmp (CmpI op1 zero));
9395
9396 effect(USE op1, USE lbl);
9397
9398 ins_cost(BRANCH_COST);
9399
9400 format %{ "b$cmp $op1, zr, $lbl\t#@cmpI_reg_imm0_loop" %}
9401
9402 ins_encode %{
9403 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label));
9404 %}
9405
9406 ins_pipe(pipe_cmpz_branch);
9407 ins_short_branch(1);
9408 %}
9409
9410 // Compare unsigned int with zero and branch near instructions
9411 instruct cmpUEqNeLeGt_reg_imm0_branch(cmpOpUEqNeLeGt cmp, iRegI op1, immI0 zero, label lbl)
9412 %{
9413 // Same match rule as `far_cmpUEqNeLeGt_reg_imm0_branch'.
9414 match(If cmp (CmpU op1 zero));
9415
9416 effect(USE op1, USE lbl);
9417
9418 ins_cost(BRANCH_COST);
9419
9420 format %{ "b$cmp $op1, zr, $lbl\t#@cmpUEqNeLeGt_reg_imm0_branch" %}
9421
9422 ins_encode %{
9423 __ enc_cmpUEqNeLeGt_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
9424 %}
9425
9426 ins_pipe(pipe_cmpz_branch);
9427 ins_short_branch(1);
9428 %}
9429
9430 // Compare signed long with zero and branch near instructions
9431 instruct cmpL_reg_imm0_branch(cmpOp cmp, iRegL op1, immL0 zero, label lbl)
9432 %{
9433 // Same match rule as `far_cmpL_reg_imm0_branch'.
9434 match(If cmp (CmpL op1 zero));
9435
9436 effect(USE op1, USE lbl);
9437
9438 ins_cost(BRANCH_COST);
9439
9440 format %{ "b$cmp $op1, zr, $lbl\t#@cmpL_reg_imm0_branch" %}
9441
9442 ins_encode %{
9443 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label));
9444 %}
9445
9446 ins_pipe(pipe_cmpz_branch);
9447 ins_short_branch(1);
9448 %}
9449
9450 instruct cmpL_reg_imm0_loop(cmpOp cmp, iRegL op1, immL0 zero, label lbl)
9451 %{
9452 // Same match rule as `far_cmpL_reg_imm0_loop'.
9453 match(CountedLoopEnd cmp (CmpL op1 zero));
9454
9455 effect(USE op1, USE lbl);
9456
9457 ins_cost(BRANCH_COST);
9458
9459 format %{ "b$cmp $op1, zr, $lbl\t#@cmpL_reg_imm0_loop" %}
9460
9461 ins_encode %{
9462 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label));
9463 %}
9464
9465 ins_pipe(pipe_cmpz_branch);
9466 ins_short_branch(1);
9467 %}
9468
9469 // Compare unsigned long with zero and branch near instructions
9470 instruct cmpULEqNeLeGt_reg_imm0_branch(cmpOpUEqNeLeGt cmp, iRegL op1, immL0 zero, label lbl)
9471 %{
9472 // Same match rule as `far_cmpULEqNeLeGt_reg_imm0_branch'.
9473 match(If cmp (CmpUL op1 zero));
9474
9475 effect(USE op1, USE lbl);
9476
9477 ins_cost(BRANCH_COST);
9478
9479 format %{ "b$cmp $op1, zr, $lbl\t#@cmpULEqNeLeGt_reg_imm0_branch" %}
9480
9481 ins_encode %{
9482 __ enc_cmpUEqNeLeGt_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
9483 %}
9484
9485 ins_pipe(pipe_cmpz_branch);
9486 ins_short_branch(1);
9487 %}
9488
9489 // Compare pointer with zero and branch near instructions
9490 instruct cmpP_imm0_branch(cmpOpEqNe cmp, iRegP op1, immP0 zero, label lbl) %{
9491 // Same match rule as `far_cmpP_reg_imm0_branch'.
9492 match(If cmp (CmpP op1 zero));
9493 effect(USE lbl);
9494
9495 ins_cost(BRANCH_COST);
9496 format %{ "b$cmp $op1, zr, $lbl\t#@cmpP_imm0_branch" %}
9497
9498 ins_encode %{
9499 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
9500 %}
9501
9502 ins_pipe(pipe_cmpz_branch);
9503 ins_short_branch(1);
9504 %}
9505
9506 // Compare narrow pointer with zero and branch near instructions
9507 instruct cmpN_imm0_branch(cmpOpEqNe cmp, iRegN op1, immN0 zero, label lbl) %{
9508 // Same match rule as `far_cmpN_reg_imm0_branch'.
9509 match(If cmp (CmpN op1 zero));
9510 effect(USE lbl);
9511
9512 ins_cost(BRANCH_COST);
9513
9514 format %{ "b$cmp $op1, zr, $lbl\t#@cmpN_imm0_branch" %}
9515
9516 ins_encode %{
9517 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
9518 %}
9519
9520 ins_pipe(pipe_cmpz_branch);
9521 ins_short_branch(1);
9522 %}
9523
9524 // Compare narrow pointer with pointer zero and branch near instructions
9525 instruct cmpP_narrowOop_imm0_branch(cmpOpEqNe cmp, iRegN op1, immP0 zero, label lbl) %{
9526 // Same match rule as `far_cmpP_narrowOop_imm0_branch'.
9527 match(If cmp (CmpP (DecodeN op1) zero));
9528 effect(USE lbl);
9529
9530 ins_cost(BRANCH_COST);
9531 format %{ "b$cmp $op1, zr, $lbl\t#@cmpP_narrowOop_imm0_branch" %}
9532
9533 ins_encode %{
9534 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
9535 %}
9536
9537 ins_pipe(pipe_cmpz_branch);
9538 ins_short_branch(1);
9539 %}
9540
9541 // Patterns for far (20KiB) variants
9542
9543 instruct far_cmpFlag_branch(cmpOp cmp, rFlagsReg cr, label lbl) %{
9544 match(If cmp cr);
9545 effect(USE lbl);
9546
9547 ins_cost(BRANCH_COST);
9548 format %{ "far_b$cmp $cr, zr, $lbl\t#@far_cmpFlag_branch"%}
9549
9550 ins_encode %{
9551 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($cr$$reg), *($lbl$$label), /* is_far */ true);
9552 %}
9553
9554 ins_pipe(pipe_cmpz_branch);
9555 %}
9556
9557 // Compare signed int and branch far instructions
9558 instruct far_cmpI_branch(cmpOp cmp, iRegI op1, iRegI op2, label lbl) %{
9559 match(If cmp (CmpI op1 op2));
9560 effect(USE lbl);
9561
9562 ins_cost(BRANCH_COST * 2);
9563
9564 // the format instruction [far_b$cmp] here is be used as two insructions
9565 // in macroassembler: b$not_cmp(op1, op2, done), j($lbl), bind(done)
9566 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpI_branch" %}
9567
9568 ins_encode %{
9569 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9570 %}
9571
9572 ins_pipe(pipe_cmp_branch);
9573 %}
9574
9575 instruct far_cmpI_loop(cmpOp cmp, iRegI op1, iRegI op2, label lbl) %{
9576 match(CountedLoopEnd cmp (CmpI op1 op2));
9577 effect(USE lbl);
9578
9579 ins_cost(BRANCH_COST * 2);
9580 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpI_loop" %}
9581
9582 ins_encode %{
9583 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9584 %}
9585
9586 ins_pipe(pipe_cmp_branch);
9587 %}
9588
9589 instruct far_cmpU_branch(cmpOpU cmp, iRegI op1, iRegI op2, label lbl) %{
9590 match(If cmp (CmpU op1 op2));
9591 effect(USE lbl);
9592
9593 ins_cost(BRANCH_COST * 2);
9594 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpU_branch" %}
9595
9596 ins_encode %{
9597 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9598 as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9599 %}
9600
9601 ins_pipe(pipe_cmp_branch);
9602 %}
9603
9604 instruct far_cmpL_branch(cmpOp cmp, iRegL op1, iRegL op2, label lbl) %{
9605 match(If cmp (CmpL op1 op2));
9606 effect(USE lbl);
9607
9608 ins_cost(BRANCH_COST * 2);
9609 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpL_branch" %}
9610
9611 ins_encode %{
9612 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9613 %}
9614
9615 ins_pipe(pipe_cmp_branch);
9616 %}
9617
9618 instruct far_cmpLloop(cmpOp cmp, iRegL op1, iRegL op2, label lbl) %{
9619 match(CountedLoopEnd cmp (CmpL op1 op2));
9620 effect(USE lbl);
9621
9622 ins_cost(BRANCH_COST * 2);
9623 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpL_loop" %}
9624
9625 ins_encode %{
9626 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9627 %}
9628
9629 ins_pipe(pipe_cmp_branch);
9630 %}
9631
9632 instruct far_cmpUL_branch(cmpOpU cmp, iRegL op1, iRegL op2, label lbl) %{
9633 match(If cmp (CmpUL op1 op2));
9634 effect(USE lbl);
9635
9636 ins_cost(BRANCH_COST * 2);
9637 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpUL_branch" %}
9638
9639 ins_encode %{
9640 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9641 as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9642 %}
9643
9644 ins_pipe(pipe_cmp_branch);
9645 %}
9646
9647 instruct far_cmpP_branch(cmpOpU cmp, iRegP op1, iRegP op2, label lbl)
9648 %{
9649 match(If cmp (CmpP op1 op2));
9650
9651 effect(USE lbl);
9652
9653 ins_cost(BRANCH_COST * 2);
9654
9655 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpP_branch" %}
9656
9657 ins_encode %{
9658 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9659 as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9660 %}
9661
9662 ins_pipe(pipe_cmp_branch);
9663 %}
9664
9665 instruct far_cmpN_branch(cmpOpU cmp, iRegN op1, iRegN op2, label lbl)
9666 %{
9667 match(If cmp (CmpN op1 op2));
9668
9669 effect(USE lbl);
9670
9671 ins_cost(BRANCH_COST * 2);
9672
9673 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpN_branch" %}
9674
9675 ins_encode %{
9676 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9677 as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9678 %}
9679
9680 ins_pipe(pipe_cmp_branch);
9681 %}
9682
9683 // Float compare and branch instructions
9684 instruct far_cmpF_branch(cmpOp cmp, fRegF op1, fRegF op2, label lbl)
9685 %{
9686 match(If cmp (CmpF op1 op2));
9687
9688 effect(USE lbl);
9689
9690 ins_cost(XFER_COST + BRANCH_COST * 2);
9691 format %{ "far_float_b$cmp $op1, $op2, $lbl\t#@far_cmpF_branch"%}
9692
9693 ins_encode %{
9694 __ float_cmp_branch($cmp$$cmpcode, as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg),
9695 *($lbl$$label), /* is_far */ true);
9696 %}
9697
9698 ins_pipe(pipe_class_compare);
9699 %}
9700
9701 // Double compare and branch instructions
9702 instruct far_cmpD_branch(cmpOp cmp, fRegD op1, fRegD op2, label lbl)
9703 %{
9704 match(If cmp (CmpD op1 op2));
9705 effect(USE lbl);
9706
9707 ins_cost(XFER_COST + BRANCH_COST * 2);
9708 format %{ "far_double_b$cmp $op1, $op2, $lbl\t#@far_cmpD_branch"%}
9709
9710 ins_encode %{
9711 __ float_cmp_branch($cmp$$cmpcode | C2_MacroAssembler::double_branch_mask, as_FloatRegister($op1$$reg),
9712 as_FloatRegister($op2$$reg), *($lbl$$label), /* is_far */ true);
9713 %}
9714
9715 ins_pipe(pipe_class_compare);
9716 %}
9717
9718 instruct far_cmpI_reg_imm0_branch(cmpOp cmp, iRegI op1, immI0 zero, label lbl)
9719 %{
9720 match(If cmp (CmpI op1 zero));
9721
9722 effect(USE op1, USE lbl);
9723
9724 ins_cost(BRANCH_COST * 2);
9725
9726 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpI_reg_imm0_branch" %}
9727
9728 ins_encode %{
9729 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label), /* is_far */ true);
9730 %}
9731
9732 ins_pipe(pipe_cmpz_branch);
9733 %}
9734
9735 instruct far_cmpI_reg_imm0_loop(cmpOp cmp, iRegI op1, immI0 zero, label lbl)
9736 %{
9737 match(CountedLoopEnd cmp (CmpI op1 zero));
9738
9739 effect(USE op1, USE lbl);
9740
9741 ins_cost(BRANCH_COST * 2);
9742
9743 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpI_reg_imm0_loop" %}
9744
9745 ins_encode %{
9746 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label), /* is_far */ true);
9747 %}
9748
9749 ins_pipe(pipe_cmpz_branch);
9750 %}
9751
9752 instruct far_cmpUEqNeLeGt_imm0_branch(cmpOpUEqNeLeGt cmp, iRegI op1, immI0 zero, label lbl)
9753 %{
9754 match(If cmp (CmpU op1 zero));
9755
9756 effect(USE op1, USE lbl);
9757
9758 ins_cost(BRANCH_COST * 2);
9759
9760 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpUEqNeLeGt_imm0_branch" %}
9761
9762 ins_encode %{
9763 __ enc_cmpUEqNeLeGt_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
9764 %}
9765
9766 ins_pipe(pipe_cmpz_branch);
9767 %}
9768
9769 // compare lt/ge unsigned instructs has no short instruct with same match
9770 instruct far_cmpULtGe_reg_imm0_branch(cmpOpULtGe cmp, iRegI op1, immI0 zero, label lbl)
9771 %{
9772 match(If cmp (CmpU op1 zero));
9773
9774 effect(USE op1, USE lbl);
9775
9776 ins_cost(BRANCH_COST);
9777
9778 format %{ "j $lbl if $cmp == ge\t#@far_cmpULtGe_reg_imm0_branch" %}
9779
9780 ins_encode(riscv_enc_far_cmpULtGe_imm0_branch(cmp, op1, lbl));
9781
9782 ins_pipe(pipe_cmpz_branch);
9783 %}
9784
9785 instruct far_cmpL_reg_imm0_branch(cmpOp cmp, iRegL op1, immL0 zero, label lbl)
9786 %{
9787 match(If cmp (CmpL op1 zero));
9788
9789 effect(USE op1, USE lbl);
9790
9791 ins_cost(BRANCH_COST * 2);
9792
9793 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpL_reg_imm0_branch" %}
9794
9795 ins_encode %{
9796 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label), /* is_far */ true);
9797 %}
9798
9799 ins_pipe(pipe_cmpz_branch);
9800 %}
9801
9802 instruct far_cmpL_reg_imm0_loop(cmpOp cmp, iRegL op1, immL0 zero, label lbl)
9803 %{
9804 match(CountedLoopEnd cmp (CmpL op1 zero));
9805
9806 effect(USE op1, USE lbl);
9807
9808 ins_cost(BRANCH_COST * 2);
9809
9810 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpL_reg_imm0_loop" %}
9811
9812 ins_encode %{
9813 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label), /* is_far */ true);
9814 %}
9815
9816 ins_pipe(pipe_cmpz_branch);
9817 %}
9818
9819 instruct far_cmpULEqNeLeGt_reg_imm0_branch(cmpOpUEqNeLeGt cmp, iRegL op1, immL0 zero, label lbl)
9820 %{
9821 match(If cmp (CmpUL op1 zero));
9822
9823 effect(USE op1, USE lbl);
9824
9825 ins_cost(BRANCH_COST * 2);
9826
9827 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpULEqNeLeGt_reg_imm0_branch" %}
9828
9829 ins_encode %{
9830 __ enc_cmpUEqNeLeGt_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
9831 %}
9832
9833 ins_pipe(pipe_cmpz_branch);
9834 %}
9835
9836 // compare lt/ge unsigned instructs has no short instruct with same match
9837 instruct far_cmpULLtGe_reg_imm0_branch(cmpOpULtGe cmp, iRegL op1, immL0 zero, label lbl)
9838 %{
9839 match(If cmp (CmpUL op1 zero));
9840
9841 effect(USE op1, USE lbl);
9842
9843 ins_cost(BRANCH_COST);
9844
9845 format %{ "j $lbl if $cmp == ge\t#@far_cmpULLtGe_reg_imm0_branch" %}
9846
9847 ins_encode(riscv_enc_far_cmpULtGe_imm0_branch(cmp, op1, lbl));
9848
9849 ins_pipe(pipe_cmpz_branch);
9850 %}
9851
9852 instruct far_cmpP_imm0_branch(cmpOpEqNe cmp, iRegP op1, immP0 zero, label lbl) %{
9853 match(If cmp (CmpP op1 zero));
9854 effect(USE lbl);
9855
9856 ins_cost(BRANCH_COST * 2);
9857 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpP_imm0_branch" %}
9858
9859 ins_encode %{
9860 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
9861 %}
9862
9863 ins_pipe(pipe_cmpz_branch);
9864 %}
9865
9866 instruct far_cmpN_imm0_branch(cmpOpEqNe cmp, iRegN op1, immN0 zero, label lbl) %{
9867 match(If cmp (CmpN op1 zero));
9868 effect(USE lbl);
9869
9870 ins_cost(BRANCH_COST * 2);
9871
9872 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpN_imm0_branch" %}
9873
9874 ins_encode %{
9875 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
9876 %}
9877
9878 ins_pipe(pipe_cmpz_branch);
9879 %}
9880
9881 instruct far_cmpP_narrowOop_imm0_branch(cmpOpEqNe cmp, iRegN op1, immP0 zero, label lbl) %{
9882 match(If cmp (CmpP (DecodeN op1) zero));
9883 effect(USE lbl);
9884
9885 ins_cost(BRANCH_COST * 2);
9886 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpP_narrowOop_imm0_branch" %}
9887
9888 ins_encode %{
9889 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
9890 %}
9891
9892 ins_pipe(pipe_cmpz_branch);
9893 %}
9894
9895 // ============================================================================
9896 // Conditional Move Instructions
9897 instruct cmovI_cmpI(iRegINoSp dst, iRegI src, iRegI op1, iRegI op2, cmpOp cop) %{
9898 match(Set dst (CMoveI (Binary cop (CmpI op1 op2)) (Binary dst src)));
9899 ins_cost(ALU_COST + BRANCH_COST);
9900
9901 format %{
9902 "CMove $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpI\n\t"
9903 %}
9904
9905 ins_encode %{
9906 __ enc_cmove($cop$$cmpcode,
9907 as_Register($op1$$reg), as_Register($op2$$reg),
9908 as_Register($dst$$reg), as_Register($src$$reg));
9909 %}
9910
9911 ins_pipe(pipe_class_compare);
9912 %}
9913
9914 instruct cmovI_cmpU(iRegINoSp dst, iRegI src, iRegI op1, iRegI op2, cmpOpU cop) %{
9915 match(Set dst (CMoveI (Binary cop (CmpU op1 op2)) (Binary dst src)));
9916 ins_cost(ALU_COST + BRANCH_COST);
9917
9918 format %{
9919 "CMove $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpU\n\t"
9920 %}
9921
9922 ins_encode %{
9923 __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
9924 as_Register($op1$$reg), as_Register($op2$$reg),
9925 as_Register($dst$$reg), as_Register($src$$reg));
9926 %}
9927
9928 ins_pipe(pipe_class_compare);
9929 %}
9930
9931 instruct cmovI_cmpL(iRegINoSp dst, iRegI src, iRegL op1, iRegL op2, cmpOp cop) %{
9932 match(Set dst (CMoveI (Binary cop (CmpL op1 op2)) (Binary dst src)));
9933 ins_cost(ALU_COST + BRANCH_COST);
9934
9935 format %{
9936 "CMove $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpL\n\t"
9937 %}
9938
9939 ins_encode %{
9940 __ enc_cmove($cop$$cmpcode,
9941 as_Register($op1$$reg), as_Register($op2$$reg),
9942 as_Register($dst$$reg), as_Register($src$$reg));
9943 %}
9944
9945 ins_pipe(pipe_class_compare);
9946 %}
9947
9948 instruct cmovI_cmpUL(iRegINoSp dst, iRegI src, iRegL op1, iRegL op2, cmpOpU cop) %{
9949 match(Set dst (CMoveI (Binary cop (CmpUL op1 op2)) (Binary dst src)));
9950 ins_cost(ALU_COST + BRANCH_COST);
9951
9952 format %{
9953 "CMove $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpUL\n\t"
9954 %}
9955
9956 ins_encode %{
9957 __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
9958 as_Register($op1$$reg), as_Register($op2$$reg),
9959 as_Register($dst$$reg), as_Register($src$$reg));
9960 %}
9961
9962 ins_pipe(pipe_class_compare);
9963 %}
9964
9965 instruct cmovI_cmpN(iRegINoSp dst, iRegI src, iRegN op1, iRegN op2, cmpOpU cop) %{
9966 match(Set dst (CMoveI (Binary cop (CmpN op1 op2)) (Binary dst src)));
9967 ins_cost(ALU_COST + BRANCH_COST);
9968
9969 format %{
9970 "CMove $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpN\n\t"
9971 %}
9972
9973 ins_encode %{
9974 __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
9975 as_Register($op1$$reg), as_Register($op2$$reg),
9976 as_Register($dst$$reg), as_Register($src$$reg));
9977 %}
9978
9979 ins_pipe(pipe_class_compare);
9980 %}
9981
9982 instruct cmovI_cmpP(iRegINoSp dst, iRegI src, iRegP op1, iRegP op2, cmpOpU cop) %{
9983 match(Set dst (CMoveI (Binary cop (CmpP op1 op2)) (Binary dst src)));
9984 ins_cost(ALU_COST + BRANCH_COST);
9985
9986 format %{
9987 "CMove $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpP\n\t"
9988 %}
9989
9990 ins_encode %{
9991 __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
9992 as_Register($op1$$reg), as_Register($op2$$reg),
9993 as_Register($dst$$reg), as_Register($src$$reg));
9994 %}
9995
9996 ins_pipe(pipe_class_compare);
9997 %}
9998
9999 instruct cmovL_cmpL(iRegLNoSp dst, iRegL src, iRegL op1, iRegL op2, cmpOp cop) %{
10000 match(Set dst (CMoveL (Binary cop (CmpL op1 op2)) (Binary dst src)));
10001 ins_cost(ALU_COST + BRANCH_COST);
10002
10003 format %{
10004 "CMove $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpL\n\t"
10005 %}
10006
10007 ins_encode %{
10008 __ enc_cmove($cop$$cmpcode,
10009 as_Register($op1$$reg), as_Register($op2$$reg),
10010 as_Register($dst$$reg), as_Register($src$$reg));
10011 %}
10012
10013 ins_pipe(pipe_class_compare);
10014 %}
10015
10016 instruct cmovL_cmpUL(iRegLNoSp dst, iRegL src, iRegL op1, iRegL op2, cmpOpU cop) %{
10017 match(Set dst (CMoveL (Binary cop (CmpUL op1 op2)) (Binary dst src)));
10018 ins_cost(ALU_COST + BRANCH_COST);
10019
10020 format %{
10021 "CMove $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpUL\n\t"
10022 %}
10023
10024 ins_encode %{
10025 __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10026 as_Register($op1$$reg), as_Register($op2$$reg),
10027 as_Register($dst$$reg), as_Register($src$$reg));
10028 %}
10029
10030 ins_pipe(pipe_class_compare);
10031 %}
10032
10033 instruct cmovL_cmpI(iRegLNoSp dst, iRegL src, iRegI op1, iRegI op2, cmpOp cop) %{
10034 match(Set dst (CMoveL (Binary cop (CmpI op1 op2)) (Binary dst src)));
10035 ins_cost(ALU_COST + BRANCH_COST);
10036
10037 format %{
10038 "CMove $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpI\n\t"
10039 %}
10040
10041 ins_encode %{
10042 __ enc_cmove($cop$$cmpcode,
10043 as_Register($op1$$reg), as_Register($op2$$reg),
10044 as_Register($dst$$reg), as_Register($src$$reg));
10045 %}
10046
10047 ins_pipe(pipe_class_compare);
10048 %}
10049
10050 instruct cmovL_cmpU(iRegLNoSp dst, iRegL src, iRegI op1, iRegI op2, cmpOpU cop) %{
10051 match(Set dst (CMoveL (Binary cop (CmpU op1 op2)) (Binary dst src)));
10052 ins_cost(ALU_COST + BRANCH_COST);
10053
10054 format %{
10055 "CMove $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpU\n\t"
10056 %}
10057
10058 ins_encode %{
10059 __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10060 as_Register($op1$$reg), as_Register($op2$$reg),
10061 as_Register($dst$$reg), as_Register($src$$reg));
10062 %}
10063
10064 ins_pipe(pipe_class_compare);
10065 %}
10066
10067 instruct cmovL_cmpN(iRegLNoSp dst, iRegL src, iRegN op1, iRegN op2, cmpOpU cop) %{
10068 match(Set dst (CMoveL (Binary cop (CmpN op1 op2)) (Binary dst src)));
10069 ins_cost(ALU_COST + BRANCH_COST);
10070
10071 format %{
10072 "CMove $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpN\n\t"
10073 %}
10074
10075 ins_encode %{
10076 __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10077 as_Register($op1$$reg), as_Register($op2$$reg),
10078 as_Register($dst$$reg), as_Register($src$$reg));
10079 %}
10080
10081 ins_pipe(pipe_class_compare);
10082 %}
10083
10084 instruct cmovL_cmpP(iRegLNoSp dst, iRegL src, iRegP op1, iRegP op2, cmpOpU cop) %{
10085 match(Set dst (CMoveL (Binary cop (CmpP op1 op2)) (Binary dst src)));
10086 ins_cost(ALU_COST + BRANCH_COST);
10087
10088 format %{
10089 "CMove $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpP\n\t"
10090 %}
10091
10092 ins_encode %{
10093 __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10094 as_Register($op1$$reg), as_Register($op2$$reg),
10095 as_Register($dst$$reg), as_Register($src$$reg));
10096 %}
10097
10098 ins_pipe(pipe_class_compare);
10099 %}
10100
10101 // ============================================================================
10102 // Procedure Call/Return Instructions
10103
10104 // Call Java Static Instruction
10105 // Note: If this code changes, the corresponding ret_addr_offset() and
10106 // compute_padding() functions will have to be adjusted.
10107 instruct CallStaticJavaDirect(method meth)
10108 %{
10109 match(CallStaticJava);
10110
10111 effect(USE meth);
10112
10113 ins_cost(BRANCH_COST);
10114
10115 format %{ "CALL,static $meth\t#@CallStaticJavaDirect" %}
10116
10117 ins_encode(riscv_enc_java_static_call(meth),
10118 riscv_enc_call_epilog);
10119
10120 ins_pipe(pipe_class_call);
10121 ins_alignment(4);
10122 %}
10123
10124 // TO HERE
10125
10126 // Call Java Dynamic Instruction
10127 // Note: If this code changes, the corresponding ret_addr_offset() and
10128 // compute_padding() functions will have to be adjusted.
10129 instruct CallDynamicJavaDirect(method meth)
10130 %{
10131 match(CallDynamicJava);
10132
10133 effect(USE meth);
10134
10135 ins_cost(BRANCH_COST + ALU_COST * 5);
10136
10137 format %{ "CALL,dynamic $meth\t#@CallDynamicJavaDirect" %}
10138
10139 ins_encode(riscv_enc_java_dynamic_call(meth),
10140 riscv_enc_call_epilog);
10141
10142 ins_pipe(pipe_class_call);
10143 ins_alignment(4);
10144 %}
10145
10146 // Call Runtime Instruction
10147
10148 instruct CallRuntimeDirect(method meth)
10149 %{
10150 match(CallRuntime);
10151
10152 effect(USE meth);
10153
10154 ins_cost(BRANCH_COST);
10155
10156 format %{ "CALL, runtime $meth\t#@CallRuntimeDirect" %}
10157
10158 ins_encode(riscv_enc_java_to_runtime(meth));
10159
10160 ins_pipe(pipe_class_call);
10161 %}
10162
10163 // Call Runtime Instruction
10164
10165 instruct CallLeafDirect(method meth)
10166 %{
10167 match(CallLeaf);
10168
10169 effect(USE meth);
10170
10171 ins_cost(BRANCH_COST);
10172
10173 format %{ "CALL, runtime leaf $meth\t#@CallLeafDirect" %}
10174
10175 ins_encode(riscv_enc_java_to_runtime(meth));
10176
10177 ins_pipe(pipe_class_call);
10178 %}
10179
10180 // Call Runtime Instruction without safepoint and with vector arguments
10181
10182 instruct CallLeafDirectVector(method meth)
10183 %{
10184 match(CallLeafVector);
10185
10186 effect(USE meth);
10187
10188 ins_cost(BRANCH_COST);
10189
10190 format %{ "CALL, runtime leaf vector $meth" %}
10191
10192 ins_encode(riscv_enc_java_to_runtime(meth));
10193
10194 ins_pipe(pipe_class_call);
10195 %}
10196
10197 // Call Runtime Instruction
10198
10199 instruct CallLeafNoFPDirect(method meth)
10200 %{
10201 match(CallLeafNoFP);
10202
10203 effect(USE meth);
10204
10205 ins_cost(BRANCH_COST);
10206
10207 format %{ "CALL, runtime leaf nofp $meth\t#@CallLeafNoFPDirect" %}
10208
10209 ins_encode(riscv_enc_java_to_runtime(meth));
10210
10211 ins_pipe(pipe_class_call);
10212 %}
10213
10214 // ============================================================================
10215 // Partial Subtype Check
10216 //
10217 // superklass array for an instance of the superklass. Set a hidden
10218 // internal cache on a hit (cache is checked with exposed code in
10219 // gen_subtype_check()). Return zero for a hit. The encoding
10220 // ALSO sets flags.
10221
10222 instruct partialSubtypeCheck(iRegP_R15 result, iRegP_R14 sub, iRegP_R10 super, iRegP_R12 tmp, rFlagsReg cr)
10223 %{
10224 predicate(!UseSecondarySupersTable);
10225 match(Set result (PartialSubtypeCheck sub super));
10226 effect(KILL tmp, KILL cr);
10227
10228 ins_cost(20 * DEFAULT_COST);
10229 format %{ "partialSubtypeCheck $result, $sub, $super\t#@partialSubtypeCheck" %}
10230
10231 ins_encode(riscv_enc_partial_subtype_check(sub, super, tmp, result));
10232
10233 opcode(0x1); // Force zero of result reg on hit
10234
10235 ins_pipe(pipe_class_memory);
10236 %}
10237
10238 // Two versions of partialSubtypeCheck, both used when we need to
10239 // search for a super class in the secondary supers array. The first
10240 // is used when we don't know _a priori_ the class being searched
10241 // for. The second, far more common, is used when we do know: this is
10242 // used for instanceof, checkcast, and any case where C2 can determine
10243 // it by constant propagation.
10244
10245 instruct partialSubtypeCheckVarSuper(iRegP_R14 sub, iRegP_R10 super, iRegP_R15 result,
10246 iRegP_R11 tmpR11, iRegP_R12 tmpR12, iRegP_R13 tmpR13,
10247 iRegP_R16 tmpR16, rFlagsReg cr)
10248 %{
10249 predicate(UseSecondarySupersTable);
10250 match(Set result (PartialSubtypeCheck sub super));
10251 effect(TEMP tmpR11, TEMP tmpR12, TEMP tmpR13, TEMP tmpR16, KILL cr);
10252
10253 ins_cost(10 * DEFAULT_COST); // slightly larger than the next version
10254 format %{ "partialSubtypeCheck $result, $sub, $super" %}
10255
10256 ins_encode %{
10257 __ lookup_secondary_supers_table_var($sub$$Register, $super$$Register, $result$$Register,
10258 $tmpR11$$Register, $tmpR12$$Register, $tmpR13$$Register,
10259 $tmpR16$$Register, nullptr /*L_success*/);
10260 %}
10261
10262 ins_pipe(pipe_class_memory);
10263 %}
10264
10265 instruct partialSubtypeCheckConstSuper(iRegP_R14 sub, iRegP_R10 super_reg, immP super_con, iRegP_R15 result,
10266 iRegP_R11 tmpR11, iRegP_R12 tmpR12, iRegP_R13 tmpR13, iRegP_R16 tmpR16, rFlagsReg cr)
10267 %{
10268 predicate(UseSecondarySupersTable);
10269 match(Set result (PartialSubtypeCheck sub (Binary super_reg super_con)));
10270 effect(TEMP tmpR11, TEMP tmpR12, TEMP tmpR13, TEMP tmpR16, KILL cr);
10271
10272 ins_cost(5 * DEFAULT_COST); // needs to be less than competing nodes
10273 format %{ "partialSubtypeCheck $result, $sub, $super_reg, $super_con" %}
10274
10275 ins_encode %{
10276 bool success = false;
10277 u1 super_klass_slot = ((Klass*)$super_con$$constant)->hash_slot();
10278 if (InlineSecondarySupersTest) {
10279 success = __ lookup_secondary_supers_table_const($sub$$Register, $super_reg$$Register, $result$$Register,
10280 $tmpR11$$Register, $tmpR12$$Register, $tmpR13$$Register,
10281 $tmpR16$$Register, super_klass_slot);
10282 } else {
10283 address call = __ reloc_call(RuntimeAddress(StubRoutines::lookup_secondary_supers_table_stub(super_klass_slot)));
10284 success = (call != nullptr);
10285 }
10286 if (!success) {
10287 ciEnv::current()->record_failure("CodeCache is full");
10288 return;
10289 }
10290 %}
10291
10292 ins_pipe(pipe_class_memory);
10293 %}
10294
10295 instruct string_compareU(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
10296 iRegI_R10 result, iRegP_R28 tmp1, iRegL_R29 tmp2, iRegL_R30 tmp3, rFlagsReg cr)
10297 %{
10298 predicate(!UseRVV && ((StrCompNode *)n)->encoding() == StrIntrinsicNode::UU);
10299 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10300 effect(KILL tmp1, KILL tmp2, KILL tmp3, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
10301
10302 format %{ "String Compare $str1, $cnt1, $str2, $cnt2 -> $result\t#@string_compareU" %}
10303 ins_encode %{
10304 // Count is in 8-bit bytes; non-Compact chars are 16 bits.
10305 __ string_compare($str1$$Register, $str2$$Register,
10306 $cnt1$$Register, $cnt2$$Register, $result$$Register,
10307 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
10308 StrIntrinsicNode::UU);
10309 %}
10310 ins_pipe(pipe_class_memory);
10311 %}
10312
10313 instruct string_compareL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
10314 iRegI_R10 result, iRegP_R28 tmp1, iRegL_R29 tmp2, iRegL_R30 tmp3, rFlagsReg cr)
10315 %{
10316 predicate(!UseRVV && ((StrCompNode *)n)->encoding() == StrIntrinsicNode::LL);
10317 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10318 effect(KILL tmp1, KILL tmp2, KILL tmp3, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
10319
10320 format %{ "String Compare $str1, $cnt1, $str2, $cnt2 -> $result\t#@string_compareL" %}
10321 ins_encode %{
10322 __ string_compare($str1$$Register, $str2$$Register,
10323 $cnt1$$Register, $cnt2$$Register, $result$$Register,
10324 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
10325 StrIntrinsicNode::LL);
10326 %}
10327 ins_pipe(pipe_class_memory);
10328 %}
10329
10330 instruct string_compareUL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
10331 iRegI_R10 result, iRegP_R28 tmp1, iRegL_R29 tmp2, iRegL_R30 tmp3, rFlagsReg cr)
10332 %{
10333 predicate(!UseRVV && ((StrCompNode *)n)->encoding() == StrIntrinsicNode::UL);
10334 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10335 effect(KILL tmp1, KILL tmp2, KILL tmp3, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
10336
10337 format %{"String Compare $str1, $cnt1, $str2, $cnt2 -> $result\t#@string_compareUL" %}
10338 ins_encode %{
10339 __ string_compare($str1$$Register, $str2$$Register,
10340 $cnt1$$Register, $cnt2$$Register, $result$$Register,
10341 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
10342 StrIntrinsicNode::UL);
10343 %}
10344 ins_pipe(pipe_class_memory);
10345 %}
10346
10347 instruct string_compareLU(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
10348 iRegI_R10 result, iRegP_R28 tmp1, iRegL_R29 tmp2, iRegL_R30 tmp3,
10349 rFlagsReg cr)
10350 %{
10351 predicate(!UseRVV && ((StrCompNode *)n)->encoding() == StrIntrinsicNode::LU);
10352 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10353 effect(KILL tmp1, KILL tmp2, KILL tmp3, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
10354
10355 format %{ "String Compare $str1, $cnt1, $str2, $cnt2 -> $result\t#@string_compareLU" %}
10356 ins_encode %{
10357 __ string_compare($str1$$Register, $str2$$Register,
10358 $cnt1$$Register, $cnt2$$Register, $result$$Register,
10359 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
10360 StrIntrinsicNode::LU);
10361 %}
10362 ins_pipe(pipe_class_memory);
10363 %}
10364
10365 instruct string_indexofUU(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
10366 iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3,
10367 iRegINoSp tmp4, iRegINoSp tmp5, iRegINoSp tmp6, rFlagsReg cr)
10368 %{
10369 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU);
10370 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
10371 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, TEMP_DEF result,
10372 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, TEMP tmp6, KILL cr);
10373
10374 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result (UU)" %}
10375 ins_encode %{
10376 __ string_indexof($str1$$Register, $str2$$Register,
10377 $cnt1$$Register, $cnt2$$Register,
10378 $tmp1$$Register, $tmp2$$Register,
10379 $tmp3$$Register, $tmp4$$Register,
10380 $tmp5$$Register, $tmp6$$Register,
10381 $result$$Register, StrIntrinsicNode::UU);
10382 %}
10383 ins_pipe(pipe_class_memory);
10384 %}
10385
10386 instruct string_indexofLL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
10387 iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3,
10388 iRegINoSp tmp4, iRegINoSp tmp5, iRegINoSp tmp6, rFlagsReg cr)
10389 %{
10390 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL);
10391 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
10392 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, TEMP_DEF result,
10393 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, TEMP tmp6, KILL cr);
10394
10395 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result (LL)" %}
10396 ins_encode %{
10397 __ string_indexof($str1$$Register, $str2$$Register,
10398 $cnt1$$Register, $cnt2$$Register,
10399 $tmp1$$Register, $tmp2$$Register,
10400 $tmp3$$Register, $tmp4$$Register,
10401 $tmp5$$Register, $tmp6$$Register,
10402 $result$$Register, StrIntrinsicNode::LL);
10403 %}
10404 ins_pipe(pipe_class_memory);
10405 %}
10406
10407 instruct string_indexofUL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
10408 iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3,
10409 iRegINoSp tmp4, iRegINoSp tmp5, iRegINoSp tmp6, rFlagsReg cr)
10410 %{
10411 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL);
10412 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
10413 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, TEMP_DEF result,
10414 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, TEMP tmp6, KILL cr);
10415 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result (UL)" %}
10416
10417 ins_encode %{
10418 __ string_indexof($str1$$Register, $str2$$Register,
10419 $cnt1$$Register, $cnt2$$Register,
10420 $tmp1$$Register, $tmp2$$Register,
10421 $tmp3$$Register, $tmp4$$Register,
10422 $tmp5$$Register, $tmp6$$Register,
10423 $result$$Register, StrIntrinsicNode::UL);
10424 %}
10425 ins_pipe(pipe_class_memory);
10426 %}
10427
10428 instruct string_indexof_conUU(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2,
10429 immI_le_4 int_cnt2, iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2,
10430 iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
10431 %{
10432 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU);
10433 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
10434 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, TEMP_DEF result,
10435 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
10436
10437 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result (UU)" %}
10438
10439 ins_encode %{
10440 int icnt2 = (int)$int_cnt2$$constant;
10441 __ string_indexof_linearscan($str1$$Register, $str2$$Register,
10442 $cnt1$$Register, zr,
10443 $tmp1$$Register, $tmp2$$Register,
10444 $tmp3$$Register, $tmp4$$Register,
10445 icnt2, $result$$Register, StrIntrinsicNode::UU);
10446 %}
10447 ins_pipe(pipe_class_memory);
10448 %}
10449
10450 instruct string_indexof_conLL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2,
10451 immI_le_4 int_cnt2, iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2,
10452 iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
10453 %{
10454 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL);
10455 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
10456 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, TEMP_DEF result,
10457 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
10458
10459 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result (LL)" %}
10460 ins_encode %{
10461 int icnt2 = (int)$int_cnt2$$constant;
10462 __ string_indexof_linearscan($str1$$Register, $str2$$Register,
10463 $cnt1$$Register, zr,
10464 $tmp1$$Register, $tmp2$$Register,
10465 $tmp3$$Register, $tmp4$$Register,
10466 icnt2, $result$$Register, StrIntrinsicNode::LL);
10467 %}
10468 ins_pipe(pipe_class_memory);
10469 %}
10470
10471 instruct string_indexof_conUL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2,
10472 immI_1 int_cnt2, iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2,
10473 iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
10474 %{
10475 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL);
10476 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
10477 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, TEMP_DEF result,
10478 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
10479
10480 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result (UL)" %}
10481 ins_encode %{
10482 int icnt2 = (int)$int_cnt2$$constant;
10483 __ string_indexof_linearscan($str1$$Register, $str2$$Register,
10484 $cnt1$$Register, zr,
10485 $tmp1$$Register, $tmp2$$Register,
10486 $tmp3$$Register, $tmp4$$Register,
10487 icnt2, $result$$Register, StrIntrinsicNode::UL);
10488 %}
10489 ins_pipe(pipe_class_memory);
10490 %}
10491
10492 instruct stringU_indexof_char(iRegP_R11 str1, iRegI_R12 cnt1, iRegI_R13 ch,
10493 iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2,
10494 iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
10495 %{
10496 match(Set result (StrIndexOfChar (Binary str1 cnt1) ch));
10497 predicate(!UseRVV && (((StrIndexOfCharNode*)n)->encoding() == StrIntrinsicNode::U));
10498 effect(USE_KILL str1, USE_KILL cnt1, USE_KILL ch, TEMP_DEF result,
10499 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
10500
10501 format %{ "StringUTF16 IndexOf char[] $str1, $cnt1, $ch -> $result" %}
10502 ins_encode %{
10503 __ string_indexof_char($str1$$Register, $cnt1$$Register, $ch$$Register,
10504 $result$$Register, $tmp1$$Register, $tmp2$$Register,
10505 $tmp3$$Register, $tmp4$$Register, false /* isU */);
10506 %}
10507 ins_pipe(pipe_class_memory);
10508 %}
10509
10510
10511 instruct stringL_indexof_char(iRegP_R11 str1, iRegI_R12 cnt1, iRegI_R13 ch,
10512 iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2,
10513 iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
10514 %{
10515 match(Set result (StrIndexOfChar (Binary str1 cnt1) ch));
10516 predicate(!UseRVV && (((StrIndexOfCharNode*)n)->encoding() == StrIntrinsicNode::L));
10517 effect(USE_KILL str1, USE_KILL cnt1, USE_KILL ch, TEMP_DEF result,
10518 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
10519
10520 format %{ "StringLatin1 IndexOf char[] $str1, $cnt1, $ch -> $result" %}
10521 ins_encode %{
10522 __ string_indexof_char($str1$$Register, $cnt1$$Register, $ch$$Register,
10523 $result$$Register, $tmp1$$Register, $tmp2$$Register,
10524 $tmp3$$Register, $tmp4$$Register, true /* isL */);
10525 %}
10526 ins_pipe(pipe_class_memory);
10527 %}
10528
10529 // clearing of an array
10530 instruct clearArray_reg_reg(iRegL_R29 cnt, iRegP_R28 base, iRegP_R30 tmp1,
10531 iRegP_R31 tmp2, rFlagsReg cr, Universe dummy)
10532 %{
10533 // temp registers must match the one used in StubGenerator::generate_zero_blocks()
10534 predicate(UseBlockZeroing || !UseRVV);
10535 match(Set dummy (ClearArray cnt base));
10536 effect(USE_KILL cnt, USE_KILL base, TEMP tmp1, TEMP tmp2, KILL cr);
10537
10538 ins_cost(4 * DEFAULT_COST);
10539 format %{ "ClearArray $cnt, $base\t#@clearArray_reg_reg" %}
10540
10541 ins_encode %{
10542 address tpc = __ zero_words($base$$Register, $cnt$$Register);
10543 if (tpc == nullptr) {
10544 ciEnv::current()->record_failure("CodeCache is full");
10545 return;
10546 }
10547 %}
10548
10549 ins_pipe(pipe_class_memory);
10550 %}
10551
10552 instruct clearArray_imm_reg(immL cnt, iRegP_R28 base, Universe dummy, rFlagsReg cr)
10553 %{
10554 predicate(!UseRVV && (uint64_t)n->in(2)->get_long()
10555 < (uint64_t)(BlockZeroingLowLimit >> LogBytesPerWord));
10556 match(Set dummy (ClearArray cnt base));
10557 effect(USE_KILL base, KILL cr);
10558
10559 ins_cost(4 * DEFAULT_COST);
10560 format %{ "ClearArray $cnt, $base\t#@clearArray_imm_reg" %}
10561
10562 ins_encode %{
10563 __ zero_words($base$$Register, (uint64_t)$cnt$$constant);
10564 %}
10565
10566 ins_pipe(pipe_class_memory);
10567 %}
10568
10569 instruct string_equalsL(iRegP_R11 str1, iRegP_R13 str2, iRegI_R14 cnt,
10570 iRegI_R10 result, rFlagsReg cr)
10571 %{
10572 predicate(!UseRVV && ((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::LL);
10573 match(Set result (StrEquals (Binary str1 str2) cnt));
10574 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL cr);
10575
10576 format %{ "String Equals $str1, $str2, $cnt -> $result\t#@string_equalsL" %}
10577 ins_encode %{
10578 // Count is in 8-bit bytes; non-Compact chars are 16 bits.
10579 __ string_equals($str1$$Register, $str2$$Register,
10580 $result$$Register, $cnt$$Register);
10581 %}
10582 ins_pipe(pipe_class_memory);
10583 %}
10584
10585 instruct array_equalsB(iRegP_R11 ary1, iRegP_R12 ary2, iRegI_R10 result,
10586 iRegP_R13 tmp1, iRegP_R14 tmp2, iRegP_R15 tmp3)
10587 %{
10588 predicate(!UseRVV && ((AryEqNode*)n)->encoding() == StrIntrinsicNode::LL);
10589 match(Set result (AryEq ary1 ary2));
10590 effect(USE_KILL ary1, USE_KILL ary2, TEMP tmp1, TEMP tmp2, TEMP tmp3);
10591
10592 format %{ "Array Equals $ary1, $ary2 -> $result\t#@array_equalsB // KILL all" %}
10593 ins_encode %{
10594 __ arrays_equals($ary1$$Register, $ary2$$Register,
10595 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
10596 $result$$Register, 1);
10597 %}
10598 ins_pipe(pipe_class_memory);
10599 %}
10600
10601 instruct array_equalsC(iRegP_R11 ary1, iRegP_R12 ary2, iRegI_R10 result,
10602 iRegP_R13 tmp1, iRegP_R14 tmp2, iRegP_R15 tmp3)
10603 %{
10604 predicate(!UseRVV && ((AryEqNode*)n)->encoding() == StrIntrinsicNode::UU);
10605 match(Set result (AryEq ary1 ary2));
10606 effect(USE_KILL ary1, USE_KILL ary2, TEMP tmp1, TEMP tmp2, TEMP tmp3);
10607
10608 format %{ "Array Equals $ary1, $ary2 -> $result\t#@array_equalsC // KILL all" %}
10609 ins_encode %{
10610 __ arrays_equals($ary1$$Register, $ary2$$Register,
10611 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
10612 $result$$Register, 2);
10613 %}
10614 ins_pipe(pipe_class_memory);
10615 %}
10616
10617 // fast ArraysSupport.vectorizedHashCode
10618 instruct arrays_hashcode(iRegP_R11 ary, iRegI_R12 cnt, iRegI_R10 result, immI basic_type,
10619 iRegLNoSp tmp1, iRegLNoSp tmp2,
10620 iRegLNoSp tmp3, iRegLNoSp tmp4,
10621 iRegLNoSp tmp5, iRegLNoSp tmp6, rFlagsReg cr)
10622 %{
10623 match(Set result (VectorizedHashCode (Binary ary cnt) (Binary result basic_type)));
10624 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, TEMP tmp6,
10625 USE_KILL ary, USE_KILL cnt, USE basic_type, KILL cr);
10626
10627 format %{ "Array HashCode array[] $ary,$cnt,$result,$basic_type -> $result // KILL all" %}
10628 ins_encode %{
10629 __ arrays_hashcode($ary$$Register, $cnt$$Register, $result$$Register,
10630 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
10631 $tmp4$$Register, $tmp5$$Register, $tmp6$$Register,
10632 (BasicType)$basic_type$$constant);
10633 %}
10634 ins_pipe(pipe_class_memory);
10635 %}
10636
10637 // ============================================================================
10638 // Safepoint Instructions
10639
10640 instruct safePoint(iRegP poll)
10641 %{
10642 match(SafePoint poll);
10643
10644 ins_cost(2 * LOAD_COST);
10645 format %{
10646 "lwu zr, [$poll]\t# Safepoint: poll for GC, #@safePoint"
10647 %}
10648 ins_encode %{
10649 __ read_polling_page(as_Register($poll$$reg), 0, relocInfo::poll_type);
10650 %}
10651 ins_pipe(pipe_serial); // ins_pipe(iload_reg_mem);
10652 %}
10653
10654 // ============================================================================
10655 // This name is KNOWN by the ADLC and cannot be changed.
10656 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
10657 // for this guy.
10658 instruct tlsLoadP(javaThread_RegP dst)
10659 %{
10660 match(Set dst (ThreadLocal));
10661
10662 ins_cost(0);
10663
10664 format %{ " -- \t// $dst=Thread::current(), empty, #@tlsLoadP" %}
10665
10666 size(0);
10667
10668 ins_encode( /*empty*/ );
10669
10670 ins_pipe(pipe_class_empty);
10671 %}
10672
10673 // inlined locking and unlocking
10674 // using t1 as the 'flag' register to bridge the BoolNode producers and consumers
10675 instruct cmpFastLock(rFlagsReg cr, iRegP object, iRegP box,
10676 iRegPNoSp tmp1, iRegPNoSp tmp2, iRegPNoSp tmp3, iRegPNoSp tmp4)
10677 %{
10678 predicate(LockingMode != LM_LIGHTWEIGHT);
10679 match(Set cr (FastLock object box));
10680 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4);
10681
10682 ins_cost(10 * DEFAULT_COST);
10683 format %{ "fastlock $object,$box\t! kills $tmp1,$tmp2,$tmp3,$tmp4 #@cmpFastLock" %}
10684
10685 ins_encode %{
10686 __ fast_lock($object$$Register, $box$$Register,
10687 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register);
10688 %}
10689
10690 ins_pipe(pipe_serial);
10691 %}
10692
10693 // using t1 as the 'flag' register to bridge the BoolNode producers and consumers
10694 instruct cmpFastUnlock(rFlagsReg cr, iRegP object, iRegP box, iRegPNoSp tmp1, iRegPNoSp tmp2)
10695 %{
10696 predicate(LockingMode != LM_LIGHTWEIGHT);
10697 match(Set cr (FastUnlock object box));
10698 effect(TEMP tmp1, TEMP tmp2);
10699
10700 ins_cost(10 * DEFAULT_COST);
10701 format %{ "fastunlock $object,$box\t! kills $tmp1, $tmp2, #@cmpFastUnlock" %}
10702
10703 ins_encode %{
10704 __ fast_unlock($object$$Register, $box$$Register, $tmp1$$Register, $tmp2$$Register);
10705 %}
10706
10707 ins_pipe(pipe_serial);
10708 %}
10709
10710 instruct cmpFastLockLightweight(rFlagsReg cr, iRegP object, iRegP box,
10711 iRegPNoSp tmp1, iRegPNoSp tmp2, iRegPNoSp tmp3, iRegPNoSp tmp4)
10712 %{
10713 predicate(LockingMode == LM_LIGHTWEIGHT);
10714 match(Set cr (FastLock object box));
10715 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4);
10716
10717 ins_cost(10 * DEFAULT_COST);
10718 format %{ "fastlock $object,$box\t! kills $tmp1,$tmp2,$tmp3,$tmp4 #@cmpFastLockLightweight" %}
10719
10720 ins_encode %{
10721 __ fast_lock_lightweight($object$$Register, $box$$Register,
10722 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register);
10723 %}
10724
10725 ins_pipe(pipe_serial);
10726 %}
10727
10728 instruct cmpFastUnlockLightweight(rFlagsReg cr, iRegP object, iRegP box,
10729 iRegPNoSp tmp1, iRegPNoSp tmp2, iRegPNoSp tmp3)
10730 %{
10731 predicate(LockingMode == LM_LIGHTWEIGHT);
10732 match(Set cr (FastUnlock object box));
10733 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3);
10734
10735 ins_cost(10 * DEFAULT_COST);
10736 format %{ "fastunlock $object,$box\t! kills $tmp1,$tmp2,$tmp3 #@cmpFastUnlockLightweight" %}
10737
10738 ins_encode %{
10739 __ fast_unlock_lightweight($object$$Register, $box$$Register,
10740 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
10741 %}
10742
10743 ins_pipe(pipe_serial);
10744 %}
10745
10746 // Tail Call; Jump from runtime stub to Java code.
10747 // Also known as an 'interprocedural jump'.
10748 // Target of jump will eventually return to caller.
10749 // TailJump below removes the return address.
10750 // Don't use fp for 'jump_target' because a MachEpilogNode has already been
10751 // emitted just above the TailCall which has reset fp to the caller state.
10752 instruct TailCalljmpInd(iRegPNoSpNoFp jump_target, inline_cache_RegP method_oop)
10753 %{
10754 match(TailCall jump_target method_oop);
10755
10756 ins_cost(BRANCH_COST);
10757
10758 format %{ "jalr $jump_target\t# $method_oop holds method oop, #@TailCalljmpInd." %}
10759
10760 ins_encode(riscv_enc_tail_call(jump_target));
10761
10762 ins_pipe(pipe_class_call);
10763 %}
10764
10765 instruct TailjmpInd(iRegPNoSpNoFp jump_target, iRegP_R10 ex_oop)
10766 %{
10767 match(TailJump jump_target ex_oop);
10768
10769 ins_cost(ALU_COST + BRANCH_COST);
10770
10771 format %{ "jalr $jump_target\t# $ex_oop holds exception oop, #@TailjmpInd." %}
10772
10773 ins_encode(riscv_enc_tail_jmp(jump_target));
10774
10775 ins_pipe(pipe_class_call);
10776 %}
10777
10778 // Forward exception.
10779 instruct ForwardExceptionjmp()
10780 %{
10781 match(ForwardException);
10782
10783 ins_cost(BRANCH_COST);
10784
10785 format %{ "j forward_exception_stub\t#@ForwardException" %}
10786
10787 ins_encode %{
10788 __ far_jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
10789 %}
10790
10791 ins_pipe(pipe_class_call);
10792 %}
10793
10794 // Create exception oop: created by stack-crawling runtime code.
10795 // Created exception is now available to this handler, and is setup
10796 // just prior to jumping to this handler. No code emitted.
10797 instruct CreateException(iRegP_R10 ex_oop)
10798 %{
10799 match(Set ex_oop (CreateEx));
10800
10801 ins_cost(0);
10802 format %{ " -- \t// exception oop; no code emitted, #@CreateException" %}
10803
10804 size(0);
10805
10806 ins_encode( /*empty*/ );
10807
10808 ins_pipe(pipe_class_empty);
10809 %}
10810
10811 // Rethrow exception: The exception oop will come in the first
10812 // argument position. Then JUMP (not call) to the rethrow stub code.
10813 instruct RethrowException()
10814 %{
10815 match(Rethrow);
10816
10817 ins_cost(BRANCH_COST);
10818
10819 format %{ "j rethrow_stub\t#@RethrowException" %}
10820
10821 ins_encode(riscv_enc_rethrow());
10822
10823 ins_pipe(pipe_class_call);
10824 %}
10825
10826 // Return Instruction
10827 // epilog node loads ret address into ra as part of frame pop
10828 instruct Ret()
10829 %{
10830 match(Return);
10831
10832 ins_cost(BRANCH_COST);
10833 format %{ "ret\t// return register, #@Ret" %}
10834
10835 ins_encode(riscv_enc_ret());
10836
10837 ins_pipe(pipe_branch);
10838 %}
10839
10840 // Die now.
10841 instruct ShouldNotReachHere() %{
10842 match(Halt);
10843
10844 ins_cost(BRANCH_COST);
10845
10846 format %{ "#@ShouldNotReachHere" %}
10847
10848 ins_encode %{
10849 if (is_reachable()) {
10850 __ stop(_halt_reason);
10851 }
10852 %}
10853
10854 ins_pipe(pipe_class_default);
10855 %}
10856
10857
10858 //----------PEEPHOLE RULES-----------------------------------------------------
10859 // These must follow all instruction definitions as they use the names
10860 // defined in the instructions definitions.
10861 //
10862 // peepmatch ( root_instr_name [preceding_instruction]* );
10863 //
10864 // peepconstraint %{
10865 // (instruction_number.operand_name relational_op instruction_number.operand_name
10866 // [, ...] );
10867 // // instruction numbers are zero-based using left to right order in peepmatch
10868 //
10869 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
10870 // // provide an instruction_number.operand_name for each operand that appears
10871 // // in the replacement instruction's match rule
10872 //
10873 // ---------VM FLAGS---------------------------------------------------------
10874 //
10875 // All peephole optimizations can be turned off using -XX:-OptoPeephole
10876 //
10877 // Each peephole rule is given an identifying number starting with zero and
10878 // increasing by one in the order seen by the parser. An individual peephole
10879 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
10880 // on the command-line.
10881 //
10882 // ---------CURRENT LIMITATIONS----------------------------------------------
10883 //
10884 // Only match adjacent instructions in same basic block
10885 // Only equality constraints
10886 // Only constraints between operands, not (0.dest_reg == RAX_enc)
10887 // Only one replacement instruction
10888 //
10889 //----------SMARTSPILL RULES---------------------------------------------------
10890 // These must follow all instruction definitions as they use the names
10891 // defined in the instructions definitions.
10892
10893 // Local Variables:
10894 // mode: c++
10895 // End: