1 //
2 // Copyright (c) 2003, 2025, Oracle and/or its affiliates. All rights reserved.
3 // Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
4 // Copyright (c) 2020, 2024, Huawei Technologies Co., Ltd. All rights reserved.
5 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
6 //
7 // This code is free software; you can redistribute it and/or modify it
8 // under the terms of the GNU General Public License version 2 only, as
9 // published by the Free Software Foundation.
10 //
11 // This code is distributed in the hope that it will be useful, but WITHOUT
12 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 // version 2 for more details (a copy is included in the LICENSE file that
15 // accompanied this code).
16 //
17 // You should have received a copy of the GNU General Public License version
18 // 2 along with this work; if not, write to the Free Software Foundation,
19 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
20 //
21 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
22 // or visit www.oracle.com if you need additional information or have any
23 // questions.
24 //
25 //
26
27 // RISCV Architecture Description File
28
29 //----------REGISTER DEFINITION BLOCK------------------------------------------
30 // This information is used by the matcher and the register allocator to
31 // describe individual registers and classes of registers within the target
32 // architecture.
33
34 register %{
35 //----------Architecture Description Register Definitions----------------------
36 // General Registers
37 // "reg_def" name ( register save type, C convention save type,
38 // ideal register type, encoding );
39 // Register Save Types:
40 //
41 // NS = No-Save: The register allocator assumes that these registers
42 // can be used without saving upon entry to the method, &
43 // that they do not need to be saved at call sites.
44 //
45 // SOC = Save-On-Call: The register allocator assumes that these registers
46 // can be used without saving upon entry to the method,
47 // but that they must be saved at call sites.
48 //
49 // SOE = Save-On-Entry: The register allocator assumes that these registers
50 // must be saved before using them upon entry to the
51 // method, but they do not need to be saved at call
52 // sites.
53 //
54 // AS = Always-Save: The register allocator assumes that these registers
55 // must be saved before using them upon entry to the
56 // method, & that they must be saved at call sites.
57 //
58 // Ideal Register Type is used to determine how to save & restore a
59 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
60 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
61 //
62 // The encoding number is the actual bit-pattern placed into the opcodes.
63
64 // We must define the 64 bit int registers in two 32 bit halves, the
65 // real lower register and a virtual upper half register. upper halves
66 // are used by the register allocator but are not actually supplied as
67 // operands to memory ops.
68 //
69 // follow the C1 compiler in making registers
70 //
71 // x7, x9-x17, x27-x31 volatile (caller save)
72 // x0-x4, x8, x23 system (no save, no allocate)
73 // x5-x6 non-allocatable (so we can use them as temporary regs)
74
75 //
76 // as regards Java usage. we don't use any callee save registers
77 // because this makes it difficult to de-optimise a frame (see comment
78 // in x86 implementation of Deoptimization::unwind_callee_save_values)
79 //
80
81 // General Registers
82
83 reg_def R0 ( NS, NS, Op_RegI, 0, x0->as_VMReg() ); // zr
84 reg_def R0_H ( NS, NS, Op_RegI, 0, x0->as_VMReg()->next() );
85 reg_def R1 ( NS, SOC, Op_RegI, 1, x1->as_VMReg() ); // ra
86 reg_def R1_H ( NS, SOC, Op_RegI, 1, x1->as_VMReg()->next() );
87 reg_def R2 ( NS, NS, Op_RegI, 2, x2->as_VMReg() ); // sp
88 reg_def R2_H ( NS, NS, Op_RegI, 2, x2->as_VMReg()->next() );
89 reg_def R3 ( NS, NS, Op_RegI, 3, x3->as_VMReg() ); // gp
90 reg_def R3_H ( NS, NS, Op_RegI, 3, x3->as_VMReg()->next() );
91 reg_def R4 ( NS, NS, Op_RegI, 4, x4->as_VMReg() ); // tp
92 reg_def R4_H ( NS, NS, Op_RegI, 4, x4->as_VMReg()->next() );
93 reg_def R7 ( SOC, SOC, Op_RegI, 7, x7->as_VMReg() );
94 reg_def R7_H ( SOC, SOC, Op_RegI, 7, x7->as_VMReg()->next() );
95 reg_def R8 ( NS, SOE, Op_RegI, 8, x8->as_VMReg() ); // fp
96 reg_def R8_H ( NS, SOE, Op_RegI, 8, x8->as_VMReg()->next() );
97 reg_def R9 ( SOC, SOE, Op_RegI, 9, x9->as_VMReg() );
98 reg_def R9_H ( SOC, SOE, Op_RegI, 9, x9->as_VMReg()->next() );
99 reg_def R10 ( SOC, SOC, Op_RegI, 10, x10->as_VMReg() );
100 reg_def R10_H ( SOC, SOC, Op_RegI, 10, x10->as_VMReg()->next());
101 reg_def R11 ( SOC, SOC, Op_RegI, 11, x11->as_VMReg() );
102 reg_def R11_H ( SOC, SOC, Op_RegI, 11, x11->as_VMReg()->next());
103 reg_def R12 ( SOC, SOC, Op_RegI, 12, x12->as_VMReg() );
104 reg_def R12_H ( SOC, SOC, Op_RegI, 12, x12->as_VMReg()->next());
105 reg_def R13 ( SOC, SOC, Op_RegI, 13, x13->as_VMReg() );
106 reg_def R13_H ( SOC, SOC, Op_RegI, 13, x13->as_VMReg()->next());
107 reg_def R14 ( SOC, SOC, Op_RegI, 14, x14->as_VMReg() );
108 reg_def R14_H ( SOC, SOC, Op_RegI, 14, x14->as_VMReg()->next());
109 reg_def R15 ( SOC, SOC, Op_RegI, 15, x15->as_VMReg() );
110 reg_def R15_H ( SOC, SOC, Op_RegI, 15, x15->as_VMReg()->next());
111 reg_def R16 ( SOC, SOC, Op_RegI, 16, x16->as_VMReg() );
112 reg_def R16_H ( SOC, SOC, Op_RegI, 16, x16->as_VMReg()->next());
113 reg_def R17 ( SOC, SOC, Op_RegI, 17, x17->as_VMReg() );
114 reg_def R17_H ( SOC, SOC, Op_RegI, 17, x17->as_VMReg()->next());
115 reg_def R18 ( SOC, SOE, Op_RegI, 18, x18->as_VMReg() );
116 reg_def R18_H ( SOC, SOE, Op_RegI, 18, x18->as_VMReg()->next());
117 reg_def R19 ( SOC, SOE, Op_RegI, 19, x19->as_VMReg() );
118 reg_def R19_H ( SOC, SOE, Op_RegI, 19, x19->as_VMReg()->next());
119 reg_def R20 ( SOC, SOE, Op_RegI, 20, x20->as_VMReg() ); // caller esp
120 reg_def R20_H ( SOC, SOE, Op_RegI, 20, x20->as_VMReg()->next());
121 reg_def R21 ( SOC, SOE, Op_RegI, 21, x21->as_VMReg() );
122 reg_def R21_H ( SOC, SOE, Op_RegI, 21, x21->as_VMReg()->next());
123 reg_def R22 ( SOC, SOE, Op_RegI, 22, x22->as_VMReg() );
124 reg_def R22_H ( SOC, SOE, Op_RegI, 22, x22->as_VMReg()->next());
125 reg_def R23 ( NS, SOE, Op_RegI, 23, x23->as_VMReg() ); // java thread
126 reg_def R23_H ( NS, SOE, Op_RegI, 23, x23->as_VMReg()->next());
127 reg_def R24 ( SOC, SOE, Op_RegI, 24, x24->as_VMReg() );
128 reg_def R24_H ( SOC, SOE, Op_RegI, 24, x24->as_VMReg()->next());
129 reg_def R25 ( SOC, SOE, Op_RegI, 25, x25->as_VMReg() );
130 reg_def R25_H ( SOC, SOE, Op_RegI, 25, x25->as_VMReg()->next());
131 reg_def R26 ( SOC, SOE, Op_RegI, 26, x26->as_VMReg() );
132 reg_def R26_H ( SOC, SOE, Op_RegI, 26, x26->as_VMReg()->next());
133 reg_def R27 ( SOC, SOE, Op_RegI, 27, x27->as_VMReg() ); // heapbase
134 reg_def R27_H ( SOC, SOE, Op_RegI, 27, x27->as_VMReg()->next());
135 reg_def R28 ( SOC, SOC, Op_RegI, 28, x28->as_VMReg() );
136 reg_def R28_H ( SOC, SOC, Op_RegI, 28, x28->as_VMReg()->next());
137 reg_def R29 ( SOC, SOC, Op_RegI, 29, x29->as_VMReg() );
138 reg_def R29_H ( SOC, SOC, Op_RegI, 29, x29->as_VMReg()->next());
139 reg_def R30 ( SOC, SOC, Op_RegI, 30, x30->as_VMReg() );
140 reg_def R30_H ( SOC, SOC, Op_RegI, 30, x30->as_VMReg()->next());
141 reg_def R31 ( SOC, SOC, Op_RegI, 31, x31->as_VMReg() );
142 reg_def R31_H ( SOC, SOC, Op_RegI, 31, x31->as_VMReg()->next());
143
144 // ----------------------------
145 // Float/Double Registers
146 // ----------------------------
147
148 // Double Registers
149
150 // The rules of ADL require that double registers be defined in pairs.
151 // Each pair must be two 32-bit values, but not necessarily a pair of
152 // single float registers. In each pair, ADLC-assigned register numbers
153 // must be adjacent, with the lower number even. Finally, when the
154 // CPU stores such a register pair to memory, the word associated with
155 // the lower ADLC-assigned number must be stored to the lower address.
156
157 // RISCV has 32 floating-point registers. Each can store a single
158 // or double precision floating-point value.
159
160 // for Java use float registers f0-f31 are always save on call whereas
161 // the platform ABI treats f8-f9 and f18-f27 as callee save). Other
162 // float registers are SOC as per the platform spec
163
164 reg_def F0 ( SOC, SOC, Op_RegF, 0, f0->as_VMReg() );
165 reg_def F0_H ( SOC, SOC, Op_RegF, 0, f0->as_VMReg()->next() );
166 reg_def F1 ( SOC, SOC, Op_RegF, 1, f1->as_VMReg() );
167 reg_def F1_H ( SOC, SOC, Op_RegF, 1, f1->as_VMReg()->next() );
168 reg_def F2 ( SOC, SOC, Op_RegF, 2, f2->as_VMReg() );
169 reg_def F2_H ( SOC, SOC, Op_RegF, 2, f2->as_VMReg()->next() );
170 reg_def F3 ( SOC, SOC, Op_RegF, 3, f3->as_VMReg() );
171 reg_def F3_H ( SOC, SOC, Op_RegF, 3, f3->as_VMReg()->next() );
172 reg_def F4 ( SOC, SOC, Op_RegF, 4, f4->as_VMReg() );
173 reg_def F4_H ( SOC, SOC, Op_RegF, 4, f4->as_VMReg()->next() );
174 reg_def F5 ( SOC, SOC, Op_RegF, 5, f5->as_VMReg() );
175 reg_def F5_H ( SOC, SOC, Op_RegF, 5, f5->as_VMReg()->next() );
176 reg_def F6 ( SOC, SOC, Op_RegF, 6, f6->as_VMReg() );
177 reg_def F6_H ( SOC, SOC, Op_RegF, 6, f6->as_VMReg()->next() );
178 reg_def F7 ( SOC, SOC, Op_RegF, 7, f7->as_VMReg() );
179 reg_def F7_H ( SOC, SOC, Op_RegF, 7, f7->as_VMReg()->next() );
180 reg_def F8 ( SOC, SOE, Op_RegF, 8, f8->as_VMReg() );
181 reg_def F8_H ( SOC, SOE, Op_RegF, 8, f8->as_VMReg()->next() );
182 reg_def F9 ( SOC, SOE, Op_RegF, 9, f9->as_VMReg() );
183 reg_def F9_H ( SOC, SOE, Op_RegF, 9, f9->as_VMReg()->next() );
184 reg_def F10 ( SOC, SOC, Op_RegF, 10, f10->as_VMReg() );
185 reg_def F10_H ( SOC, SOC, Op_RegF, 10, f10->as_VMReg()->next() );
186 reg_def F11 ( SOC, SOC, Op_RegF, 11, f11->as_VMReg() );
187 reg_def F11_H ( SOC, SOC, Op_RegF, 11, f11->as_VMReg()->next() );
188 reg_def F12 ( SOC, SOC, Op_RegF, 12, f12->as_VMReg() );
189 reg_def F12_H ( SOC, SOC, Op_RegF, 12, f12->as_VMReg()->next() );
190 reg_def F13 ( SOC, SOC, Op_RegF, 13, f13->as_VMReg() );
191 reg_def F13_H ( SOC, SOC, Op_RegF, 13, f13->as_VMReg()->next() );
192 reg_def F14 ( SOC, SOC, Op_RegF, 14, f14->as_VMReg() );
193 reg_def F14_H ( SOC, SOC, Op_RegF, 14, f14->as_VMReg()->next() );
194 reg_def F15 ( SOC, SOC, Op_RegF, 15, f15->as_VMReg() );
195 reg_def F15_H ( SOC, SOC, Op_RegF, 15, f15->as_VMReg()->next() );
196 reg_def F16 ( SOC, SOC, Op_RegF, 16, f16->as_VMReg() );
197 reg_def F16_H ( SOC, SOC, Op_RegF, 16, f16->as_VMReg()->next() );
198 reg_def F17 ( SOC, SOC, Op_RegF, 17, f17->as_VMReg() );
199 reg_def F17_H ( SOC, SOC, Op_RegF, 17, f17->as_VMReg()->next() );
200 reg_def F18 ( SOC, SOE, Op_RegF, 18, f18->as_VMReg() );
201 reg_def F18_H ( SOC, SOE, Op_RegF, 18, f18->as_VMReg()->next() );
202 reg_def F19 ( SOC, SOE, Op_RegF, 19, f19->as_VMReg() );
203 reg_def F19_H ( SOC, SOE, Op_RegF, 19, f19->as_VMReg()->next() );
204 reg_def F20 ( SOC, SOE, Op_RegF, 20, f20->as_VMReg() );
205 reg_def F20_H ( SOC, SOE, Op_RegF, 20, f20->as_VMReg()->next() );
206 reg_def F21 ( SOC, SOE, Op_RegF, 21, f21->as_VMReg() );
207 reg_def F21_H ( SOC, SOE, Op_RegF, 21, f21->as_VMReg()->next() );
208 reg_def F22 ( SOC, SOE, Op_RegF, 22, f22->as_VMReg() );
209 reg_def F22_H ( SOC, SOE, Op_RegF, 22, f22->as_VMReg()->next() );
210 reg_def F23 ( SOC, SOE, Op_RegF, 23, f23->as_VMReg() );
211 reg_def F23_H ( SOC, SOE, Op_RegF, 23, f23->as_VMReg()->next() );
212 reg_def F24 ( SOC, SOE, Op_RegF, 24, f24->as_VMReg() );
213 reg_def F24_H ( SOC, SOE, Op_RegF, 24, f24->as_VMReg()->next() );
214 reg_def F25 ( SOC, SOE, Op_RegF, 25, f25->as_VMReg() );
215 reg_def F25_H ( SOC, SOE, Op_RegF, 25, f25->as_VMReg()->next() );
216 reg_def F26 ( SOC, SOE, Op_RegF, 26, f26->as_VMReg() );
217 reg_def F26_H ( SOC, SOE, Op_RegF, 26, f26->as_VMReg()->next() );
218 reg_def F27 ( SOC, SOE, Op_RegF, 27, f27->as_VMReg() );
219 reg_def F27_H ( SOC, SOE, Op_RegF, 27, f27->as_VMReg()->next() );
220 reg_def F28 ( SOC, SOC, Op_RegF, 28, f28->as_VMReg() );
221 reg_def F28_H ( SOC, SOC, Op_RegF, 28, f28->as_VMReg()->next() );
222 reg_def F29 ( SOC, SOC, Op_RegF, 29, f29->as_VMReg() );
223 reg_def F29_H ( SOC, SOC, Op_RegF, 29, f29->as_VMReg()->next() );
224 reg_def F30 ( SOC, SOC, Op_RegF, 30, f30->as_VMReg() );
225 reg_def F30_H ( SOC, SOC, Op_RegF, 30, f30->as_VMReg()->next() );
226 reg_def F31 ( SOC, SOC, Op_RegF, 31, f31->as_VMReg() );
227 reg_def F31_H ( SOC, SOC, Op_RegF, 31, f31->as_VMReg()->next() );
228
229 // ----------------------------
230 // Vector Registers
231 // ----------------------------
232
233 // For RVV vector registers, we simply extend vector register size to 4
234 // 'logical' slots. This is nominally 128 bits but it actually covers
235 // all possible 'physical' RVV vector register lengths from 128 ~ 1024
236 // bits. The 'physical' RVV vector register length is detected during
237 // startup, so the register allocator is able to identify the correct
238 // number of bytes needed for an RVV spill/unspill.
239
240 reg_def V0 ( SOC, SOC, Op_VecA, 0, v0->as_VMReg() );
241 reg_def V0_H ( SOC, SOC, Op_VecA, 0, v0->as_VMReg()->next() );
242 reg_def V0_J ( SOC, SOC, Op_VecA, 0, v0->as_VMReg()->next(2) );
243 reg_def V0_K ( SOC, SOC, Op_VecA, 0, v0->as_VMReg()->next(3) );
244
245 reg_def V1 ( SOC, SOC, Op_VecA, 1, v1->as_VMReg() );
246 reg_def V1_H ( SOC, SOC, Op_VecA, 1, v1->as_VMReg()->next() );
247 reg_def V1_J ( SOC, SOC, Op_VecA, 1, v1->as_VMReg()->next(2) );
248 reg_def V1_K ( SOC, SOC, Op_VecA, 1, v1->as_VMReg()->next(3) );
249
250 reg_def V2 ( SOC, SOC, Op_VecA, 2, v2->as_VMReg() );
251 reg_def V2_H ( SOC, SOC, Op_VecA, 2, v2->as_VMReg()->next() );
252 reg_def V2_J ( SOC, SOC, Op_VecA, 2, v2->as_VMReg()->next(2) );
253 reg_def V2_K ( SOC, SOC, Op_VecA, 2, v2->as_VMReg()->next(3) );
254
255 reg_def V3 ( SOC, SOC, Op_VecA, 3, v3->as_VMReg() );
256 reg_def V3_H ( SOC, SOC, Op_VecA, 3, v3->as_VMReg()->next() );
257 reg_def V3_J ( SOC, SOC, Op_VecA, 3, v3->as_VMReg()->next(2) );
258 reg_def V3_K ( SOC, SOC, Op_VecA, 3, v3->as_VMReg()->next(3) );
259
260 reg_def V4 ( SOC, SOC, Op_VecA, 4, v4->as_VMReg() );
261 reg_def V4_H ( SOC, SOC, Op_VecA, 4, v4->as_VMReg()->next() );
262 reg_def V4_J ( SOC, SOC, Op_VecA, 4, v4->as_VMReg()->next(2) );
263 reg_def V4_K ( SOC, SOC, Op_VecA, 4, v4->as_VMReg()->next(3) );
264
265 reg_def V5 ( SOC, SOC, Op_VecA, 5, v5->as_VMReg() );
266 reg_def V5_H ( SOC, SOC, Op_VecA, 5, v5->as_VMReg()->next() );
267 reg_def V5_J ( SOC, SOC, Op_VecA, 5, v5->as_VMReg()->next(2) );
268 reg_def V5_K ( SOC, SOC, Op_VecA, 5, v5->as_VMReg()->next(3) );
269
270 reg_def V6 ( SOC, SOC, Op_VecA, 6, v6->as_VMReg() );
271 reg_def V6_H ( SOC, SOC, Op_VecA, 6, v6->as_VMReg()->next() );
272 reg_def V6_J ( SOC, SOC, Op_VecA, 6, v6->as_VMReg()->next(2) );
273 reg_def V6_K ( SOC, SOC, Op_VecA, 6, v6->as_VMReg()->next(3) );
274
275 reg_def V7 ( SOC, SOC, Op_VecA, 7, v7->as_VMReg() );
276 reg_def V7_H ( SOC, SOC, Op_VecA, 7, v7->as_VMReg()->next() );
277 reg_def V7_J ( SOC, SOC, Op_VecA, 7, v7->as_VMReg()->next(2) );
278 reg_def V7_K ( SOC, SOC, Op_VecA, 7, v7->as_VMReg()->next(3) );
279
280 reg_def V8 ( SOC, SOC, Op_VecA, 8, v8->as_VMReg() );
281 reg_def V8_H ( SOC, SOC, Op_VecA, 8, v8->as_VMReg()->next() );
282 reg_def V8_J ( SOC, SOC, Op_VecA, 8, v8->as_VMReg()->next(2) );
283 reg_def V8_K ( SOC, SOC, Op_VecA, 8, v8->as_VMReg()->next(3) );
284
285 reg_def V9 ( SOC, SOC, Op_VecA, 9, v9->as_VMReg() );
286 reg_def V9_H ( SOC, SOC, Op_VecA, 9, v9->as_VMReg()->next() );
287 reg_def V9_J ( SOC, SOC, Op_VecA, 9, v9->as_VMReg()->next(2) );
288 reg_def V9_K ( SOC, SOC, Op_VecA, 9, v9->as_VMReg()->next(3) );
289
290 reg_def V10 ( SOC, SOC, Op_VecA, 10, v10->as_VMReg() );
291 reg_def V10_H ( SOC, SOC, Op_VecA, 10, v10->as_VMReg()->next() );
292 reg_def V10_J ( SOC, SOC, Op_VecA, 10, v10->as_VMReg()->next(2) );
293 reg_def V10_K ( SOC, SOC, Op_VecA, 10, v10->as_VMReg()->next(3) );
294
295 reg_def V11 ( SOC, SOC, Op_VecA, 11, v11->as_VMReg() );
296 reg_def V11_H ( SOC, SOC, Op_VecA, 11, v11->as_VMReg()->next() );
297 reg_def V11_J ( SOC, SOC, Op_VecA, 11, v11->as_VMReg()->next(2) );
298 reg_def V11_K ( SOC, SOC, Op_VecA, 11, v11->as_VMReg()->next(3) );
299
300 reg_def V12 ( SOC, SOC, Op_VecA, 12, v12->as_VMReg() );
301 reg_def V12_H ( SOC, SOC, Op_VecA, 12, v12->as_VMReg()->next() );
302 reg_def V12_J ( SOC, SOC, Op_VecA, 12, v12->as_VMReg()->next(2) );
303 reg_def V12_K ( SOC, SOC, Op_VecA, 12, v12->as_VMReg()->next(3) );
304
305 reg_def V13 ( SOC, SOC, Op_VecA, 13, v13->as_VMReg() );
306 reg_def V13_H ( SOC, SOC, Op_VecA, 13, v13->as_VMReg()->next() );
307 reg_def V13_J ( SOC, SOC, Op_VecA, 13, v13->as_VMReg()->next(2) );
308 reg_def V13_K ( SOC, SOC, Op_VecA, 13, v13->as_VMReg()->next(3) );
309
310 reg_def V14 ( SOC, SOC, Op_VecA, 14, v14->as_VMReg() );
311 reg_def V14_H ( SOC, SOC, Op_VecA, 14, v14->as_VMReg()->next() );
312 reg_def V14_J ( SOC, SOC, Op_VecA, 14, v14->as_VMReg()->next(2) );
313 reg_def V14_K ( SOC, SOC, Op_VecA, 14, v14->as_VMReg()->next(3) );
314
315 reg_def V15 ( SOC, SOC, Op_VecA, 15, v15->as_VMReg() );
316 reg_def V15_H ( SOC, SOC, Op_VecA, 15, v15->as_VMReg()->next() );
317 reg_def V15_J ( SOC, SOC, Op_VecA, 15, v15->as_VMReg()->next(2) );
318 reg_def V15_K ( SOC, SOC, Op_VecA, 15, v15->as_VMReg()->next(3) );
319
320 reg_def V16 ( SOC, SOC, Op_VecA, 16, v16->as_VMReg() );
321 reg_def V16_H ( SOC, SOC, Op_VecA, 16, v16->as_VMReg()->next() );
322 reg_def V16_J ( SOC, SOC, Op_VecA, 16, v16->as_VMReg()->next(2) );
323 reg_def V16_K ( SOC, SOC, Op_VecA, 16, v16->as_VMReg()->next(3) );
324
325 reg_def V17 ( SOC, SOC, Op_VecA, 17, v17->as_VMReg() );
326 reg_def V17_H ( SOC, SOC, Op_VecA, 17, v17->as_VMReg()->next() );
327 reg_def V17_J ( SOC, SOC, Op_VecA, 17, v17->as_VMReg()->next(2) );
328 reg_def V17_K ( SOC, SOC, Op_VecA, 17, v17->as_VMReg()->next(3) );
329
330 reg_def V18 ( SOC, SOC, Op_VecA, 18, v18->as_VMReg() );
331 reg_def V18_H ( SOC, SOC, Op_VecA, 18, v18->as_VMReg()->next() );
332 reg_def V18_J ( SOC, SOC, Op_VecA, 18, v18->as_VMReg()->next(2) );
333 reg_def V18_K ( SOC, SOC, Op_VecA, 18, v18->as_VMReg()->next(3) );
334
335 reg_def V19 ( SOC, SOC, Op_VecA, 19, v19->as_VMReg() );
336 reg_def V19_H ( SOC, SOC, Op_VecA, 19, v19->as_VMReg()->next() );
337 reg_def V19_J ( SOC, SOC, Op_VecA, 19, v19->as_VMReg()->next(2) );
338 reg_def V19_K ( SOC, SOC, Op_VecA, 19, v19->as_VMReg()->next(3) );
339
340 reg_def V20 ( SOC, SOC, Op_VecA, 20, v20->as_VMReg() );
341 reg_def V20_H ( SOC, SOC, Op_VecA, 20, v20->as_VMReg()->next() );
342 reg_def V20_J ( SOC, SOC, Op_VecA, 20, v20->as_VMReg()->next(2) );
343 reg_def V20_K ( SOC, SOC, Op_VecA, 20, v20->as_VMReg()->next(3) );
344
345 reg_def V21 ( SOC, SOC, Op_VecA, 21, v21->as_VMReg() );
346 reg_def V21_H ( SOC, SOC, Op_VecA, 21, v21->as_VMReg()->next() );
347 reg_def V21_J ( SOC, SOC, Op_VecA, 21, v21->as_VMReg()->next(2) );
348 reg_def V21_K ( SOC, SOC, Op_VecA, 21, v21->as_VMReg()->next(3) );
349
350 reg_def V22 ( SOC, SOC, Op_VecA, 22, v22->as_VMReg() );
351 reg_def V22_H ( SOC, SOC, Op_VecA, 22, v22->as_VMReg()->next() );
352 reg_def V22_J ( SOC, SOC, Op_VecA, 22, v22->as_VMReg()->next(2) );
353 reg_def V22_K ( SOC, SOC, Op_VecA, 22, v22->as_VMReg()->next(3) );
354
355 reg_def V23 ( SOC, SOC, Op_VecA, 23, v23->as_VMReg() );
356 reg_def V23_H ( SOC, SOC, Op_VecA, 23, v23->as_VMReg()->next() );
357 reg_def V23_J ( SOC, SOC, Op_VecA, 23, v23->as_VMReg()->next(2) );
358 reg_def V23_K ( SOC, SOC, Op_VecA, 23, v23->as_VMReg()->next(3) );
359
360 reg_def V24 ( SOC, SOC, Op_VecA, 24, v24->as_VMReg() );
361 reg_def V24_H ( SOC, SOC, Op_VecA, 24, v24->as_VMReg()->next() );
362 reg_def V24_J ( SOC, SOC, Op_VecA, 24, v24->as_VMReg()->next(2) );
363 reg_def V24_K ( SOC, SOC, Op_VecA, 24, v24->as_VMReg()->next(3) );
364
365 reg_def V25 ( SOC, SOC, Op_VecA, 25, v25->as_VMReg() );
366 reg_def V25_H ( SOC, SOC, Op_VecA, 25, v25->as_VMReg()->next() );
367 reg_def V25_J ( SOC, SOC, Op_VecA, 25, v25->as_VMReg()->next(2) );
368 reg_def V25_K ( SOC, SOC, Op_VecA, 25, v25->as_VMReg()->next(3) );
369
370 reg_def V26 ( SOC, SOC, Op_VecA, 26, v26->as_VMReg() );
371 reg_def V26_H ( SOC, SOC, Op_VecA, 26, v26->as_VMReg()->next() );
372 reg_def V26_J ( SOC, SOC, Op_VecA, 26, v26->as_VMReg()->next(2) );
373 reg_def V26_K ( SOC, SOC, Op_VecA, 26, v26->as_VMReg()->next(3) );
374
375 reg_def V27 ( SOC, SOC, Op_VecA, 27, v27->as_VMReg() );
376 reg_def V27_H ( SOC, SOC, Op_VecA, 27, v27->as_VMReg()->next() );
377 reg_def V27_J ( SOC, SOC, Op_VecA, 27, v27->as_VMReg()->next(2) );
378 reg_def V27_K ( SOC, SOC, Op_VecA, 27, v27->as_VMReg()->next(3) );
379
380 reg_def V28 ( SOC, SOC, Op_VecA, 28, v28->as_VMReg() );
381 reg_def V28_H ( SOC, SOC, Op_VecA, 28, v28->as_VMReg()->next() );
382 reg_def V28_J ( SOC, SOC, Op_VecA, 28, v28->as_VMReg()->next(2) );
383 reg_def V28_K ( SOC, SOC, Op_VecA, 28, v28->as_VMReg()->next(3) );
384
385 reg_def V29 ( SOC, SOC, Op_VecA, 29, v29->as_VMReg() );
386 reg_def V29_H ( SOC, SOC, Op_VecA, 29, v29->as_VMReg()->next() );
387 reg_def V29_J ( SOC, SOC, Op_VecA, 29, v29->as_VMReg()->next(2) );
388 reg_def V29_K ( SOC, SOC, Op_VecA, 29, v29->as_VMReg()->next(3) );
389
390 reg_def V30 ( SOC, SOC, Op_VecA, 30, v30->as_VMReg() );
391 reg_def V30_H ( SOC, SOC, Op_VecA, 30, v30->as_VMReg()->next() );
392 reg_def V30_J ( SOC, SOC, Op_VecA, 30, v30->as_VMReg()->next(2) );
393 reg_def V30_K ( SOC, SOC, Op_VecA, 30, v30->as_VMReg()->next(3) );
394
395 reg_def V31 ( SOC, SOC, Op_VecA, 31, v31->as_VMReg() );
396 reg_def V31_H ( SOC, SOC, Op_VecA, 31, v31->as_VMReg()->next() );
397 reg_def V31_J ( SOC, SOC, Op_VecA, 31, v31->as_VMReg()->next(2) );
398 reg_def V31_K ( SOC, SOC, Op_VecA, 31, v31->as_VMReg()->next(3) );
399
400 // ----------------------------
401 // Special Registers
402 // ----------------------------
403
404 // On riscv, the physical flag register is missing, so we use t1 instead,
405 // to bridge the RegFlag semantics in share/opto
406
407 reg_def RFLAGS (SOC, SOC, Op_RegFlags, 6, x6->as_VMReg() );
408
409 // Specify priority of register selection within phases of register
410 // allocation. Highest priority is first. A useful heuristic is to
411 // give registers a low priority when they are required by machine
412 // instructions, like EAX and EDX on I486, and choose no-save registers
413 // before save-on-call, & save-on-call before save-on-entry. Registers
414 // which participate in fixed calling sequences should come last.
415 // Registers which are used as pairs must fall on an even boundary.
416
417 alloc_class chunk0(
418 // volatiles
419 R7, R7_H,
420 R28, R28_H,
421 R29, R29_H,
422 R30, R30_H,
423 R31, R31_H,
424
425 // arg registers
426 R10, R10_H,
427 R11, R11_H,
428 R12, R12_H,
429 R13, R13_H,
430 R14, R14_H,
431 R15, R15_H,
432 R16, R16_H,
433 R17, R17_H,
434
435 // non-volatiles
436 R9, R9_H,
437 R18, R18_H,
438 R19, R19_H,
439 R20, R20_H,
440 R21, R21_H,
441 R22, R22_H,
442 R24, R24_H,
443 R25, R25_H,
444 R26, R26_H,
445
446 // non-allocatable registers
447 R23, R23_H, // java thread
448 R27, R27_H, // heapbase
449 R4, R4_H, // thread
450 R8, R8_H, // fp
451 R0, R0_H, // zero
452 R1, R1_H, // ra
453 R2, R2_H, // sp
454 R3, R3_H, // gp
455 );
456
457 alloc_class chunk1(
458
459 // no save
460 F0, F0_H,
461 F1, F1_H,
462 F2, F2_H,
463 F3, F3_H,
464 F4, F4_H,
465 F5, F5_H,
466 F6, F6_H,
467 F7, F7_H,
468 F28, F28_H,
469 F29, F29_H,
470 F30, F30_H,
471 F31, F31_H,
472
473 // arg registers
474 F10, F10_H,
475 F11, F11_H,
476 F12, F12_H,
477 F13, F13_H,
478 F14, F14_H,
479 F15, F15_H,
480 F16, F16_H,
481 F17, F17_H,
482
483 // non-volatiles
484 F8, F8_H,
485 F9, F9_H,
486 F18, F18_H,
487 F19, F19_H,
488 F20, F20_H,
489 F21, F21_H,
490 F22, F22_H,
491 F23, F23_H,
492 F24, F24_H,
493 F25, F25_H,
494 F26, F26_H,
495 F27, F27_H,
496 );
497
498 alloc_class chunk2(
499 V0, V0_H, V0_J, V0_K,
500 V1, V1_H, V1_J, V1_K,
501 V2, V2_H, V2_J, V2_K,
502 V3, V3_H, V3_J, V3_K,
503 V4, V4_H, V4_J, V4_K,
504 V5, V5_H, V5_J, V5_K,
505 V6, V6_H, V6_J, V6_K,
506 V7, V7_H, V7_J, V7_K,
507 V8, V8_H, V8_J, V8_K,
508 V9, V9_H, V9_J, V9_K,
509 V10, V10_H, V10_J, V10_K,
510 V11, V11_H, V11_J, V11_K,
511 V12, V12_H, V12_J, V12_K,
512 V13, V13_H, V13_J, V13_K,
513 V14, V14_H, V14_J, V14_K,
514 V15, V15_H, V15_J, V15_K,
515 V16, V16_H, V16_J, V16_K,
516 V17, V17_H, V17_J, V17_K,
517 V18, V18_H, V18_J, V18_K,
518 V19, V19_H, V19_J, V19_K,
519 V20, V20_H, V20_J, V20_K,
520 V21, V21_H, V21_J, V21_K,
521 V22, V22_H, V22_J, V22_K,
522 V23, V23_H, V23_J, V23_K,
523 V24, V24_H, V24_J, V24_K,
524 V25, V25_H, V25_J, V25_K,
525 V26, V26_H, V26_J, V26_K,
526 V27, V27_H, V27_J, V27_K,
527 V28, V28_H, V28_J, V28_K,
528 V29, V29_H, V29_J, V29_K,
529 V30, V30_H, V30_J, V30_K,
530 V31, V31_H, V31_J, V31_K,
531 );
532
533 alloc_class chunk3(RFLAGS);
534
535 //----------Architecture Description Register Classes--------------------------
536 // Several register classes are automatically defined based upon information in
537 // this architecture description.
538 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
539 // 2) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
540 //
541
542 // Class for all 32 bit general purpose registers
543 reg_class all_reg32(
544 R0,
545 R1,
546 R2,
547 R3,
548 R4,
549 R7,
550 R8,
551 R9,
552 R10,
553 R11,
554 R12,
555 R13,
556 R14,
557 R15,
558 R16,
559 R17,
560 R18,
561 R19,
562 R20,
563 R21,
564 R22,
565 R23,
566 R24,
567 R25,
568 R26,
569 R27,
570 R28,
571 R29,
572 R30,
573 R31
574 );
575
576 // Class for any 32 bit integer registers (excluding zr)
577 reg_class any_reg32 %{
578 return _ANY_REG32_mask;
579 %}
580
581 // Singleton class for R10 int register
582 reg_class int_r10_reg(R10);
583
584 // Singleton class for R12 int register
585 reg_class int_r12_reg(R12);
586
587 // Singleton class for R13 int register
588 reg_class int_r13_reg(R13);
589
590 // Singleton class for R14 int register
591 reg_class int_r14_reg(R14);
592
593 // Class for all long integer registers
594 reg_class all_reg(
595 R0, R0_H,
596 R1, R1_H,
597 R2, R2_H,
598 R3, R3_H,
599 R4, R4_H,
600 R7, R7_H,
601 R8, R8_H,
602 R9, R9_H,
603 R10, R10_H,
604 R11, R11_H,
605 R12, R12_H,
606 R13, R13_H,
607 R14, R14_H,
608 R15, R15_H,
609 R16, R16_H,
610 R17, R17_H,
611 R18, R18_H,
612 R19, R19_H,
613 R20, R20_H,
614 R21, R21_H,
615 R22, R22_H,
616 R23, R23_H,
617 R24, R24_H,
618 R25, R25_H,
619 R26, R26_H,
620 R27, R27_H,
621 R28, R28_H,
622 R29, R29_H,
623 R30, R30_H,
624 R31, R31_H
625 );
626
627 // Class for all long integer registers (excluding zr)
628 reg_class any_reg %{
629 return _ANY_REG_mask;
630 %}
631
632 // Class for non-allocatable 32 bit registers
633 reg_class non_allocatable_reg32(
634 R0, // zr
635 R1, // ra
636 R2, // sp
637 R3, // gp
638 R4, // tp
639 R23 // java thread
640 );
641
642 // Class for non-allocatable 64 bit registers
643 reg_class non_allocatable_reg(
644 R0, R0_H, // zr
645 R1, R1_H, // ra
646 R2, R2_H, // sp
647 R3, R3_H, // gp
648 R4, R4_H, // tp
649 R23, R23_H // java thread
650 );
651
652 // Class for all non-special integer registers
653 reg_class no_special_reg32 %{
654 return _NO_SPECIAL_REG32_mask;
655 %}
656
657 // Class for all non-special long integer registers
658 reg_class no_special_reg %{
659 return _NO_SPECIAL_REG_mask;
660 %}
661
662 reg_class ptr_reg %{
663 return _PTR_REG_mask;
664 %}
665
666 // Class for all non_special pointer registers
667 reg_class no_special_ptr_reg %{
668 return _NO_SPECIAL_PTR_REG_mask;
669 %}
670
671 // Class for all non_special pointer registers (excluding fp)
672 reg_class no_special_no_fp_ptr_reg %{
673 return _NO_SPECIAL_NO_FP_PTR_REG_mask;
674 %}
675
676 // Class for 64 bit register r10
677 reg_class r10_reg(
678 R10, R10_H
679 );
680
681 // Class for 64 bit register r11
682 reg_class r11_reg(
683 R11, R11_H
684 );
685
686 // Class for 64 bit register r12
687 reg_class r12_reg(
688 R12, R12_H
689 );
690
691 // Class for 64 bit register r13
692 reg_class r13_reg(
693 R13, R13_H
694 );
695
696 // Class for 64 bit register r14
697 reg_class r14_reg(
698 R14, R14_H
699 );
700
701 // Class for 64 bit register r15
702 reg_class r15_reg(
703 R15, R15_H
704 );
705
706 // Class for 64 bit register r16
707 reg_class r16_reg(
708 R16, R16_H
709 );
710
711 // Class for method register
712 reg_class method_reg(
713 R31, R31_H
714 );
715
716 // Class for java thread register
717 reg_class java_thread_reg(
718 R23, R23_H
719 );
720
721 reg_class r28_reg(
722 R28, R28_H
723 );
724
725 reg_class r29_reg(
726 R29, R29_H
727 );
728
729 reg_class r30_reg(
730 R30, R30_H
731 );
732
733 reg_class r31_reg(
734 R31, R31_H
735 );
736
737 // Class for zero registesr
738 reg_class zr_reg(
739 R0, R0_H
740 );
741
742 // Class for thread register
743 reg_class thread_reg(
744 R4, R4_H
745 );
746
747 // Class for frame pointer register
748 reg_class fp_reg(
749 R8, R8_H
750 );
751
752 // Class for link register
753 reg_class ra_reg(
754 R1, R1_H
755 );
756
757 // Class for long sp register
758 reg_class sp_reg(
759 R2, R2_H
760 );
761
762 // Class for all float registers
763 reg_class float_reg(
764 F0,
765 F1,
766 F2,
767 F3,
768 F4,
769 F5,
770 F6,
771 F7,
772 F8,
773 F9,
774 F10,
775 F11,
776 F12,
777 F13,
778 F14,
779 F15,
780 F16,
781 F17,
782 F18,
783 F19,
784 F20,
785 F21,
786 F22,
787 F23,
788 F24,
789 F25,
790 F26,
791 F27,
792 F28,
793 F29,
794 F30,
795 F31
796 );
797
798 // Double precision float registers have virtual `high halves' that
799 // are needed by the allocator.
800 // Class for all double registers
801 reg_class double_reg(
802 F0, F0_H,
803 F1, F1_H,
804 F2, F2_H,
805 F3, F3_H,
806 F4, F4_H,
807 F5, F5_H,
808 F6, F6_H,
809 F7, F7_H,
810 F8, F8_H,
811 F9, F9_H,
812 F10, F10_H,
813 F11, F11_H,
814 F12, F12_H,
815 F13, F13_H,
816 F14, F14_H,
817 F15, F15_H,
818 F16, F16_H,
819 F17, F17_H,
820 F18, F18_H,
821 F19, F19_H,
822 F20, F20_H,
823 F21, F21_H,
824 F22, F22_H,
825 F23, F23_H,
826 F24, F24_H,
827 F25, F25_H,
828 F26, F26_H,
829 F27, F27_H,
830 F28, F28_H,
831 F29, F29_H,
832 F30, F30_H,
833 F31, F31_H
834 );
835
836 // Class for RVV vector registers
837 // Note: v0, v30 and v31 are used as mask registers.
838 reg_class vectora_reg(
839 V1, V1_H, V1_J, V1_K,
840 V2, V2_H, V2_J, V2_K,
841 V3, V3_H, V3_J, V3_K,
842 V4, V4_H, V4_J, V4_K,
843 V5, V5_H, V5_J, V5_K,
844 V6, V6_H, V6_J, V6_K,
845 V7, V7_H, V7_J, V7_K,
846 V8, V8_H, V8_J, V8_K,
847 V9, V9_H, V9_J, V9_K,
848 V10, V10_H, V10_J, V10_K,
849 V11, V11_H, V11_J, V11_K,
850 V12, V12_H, V12_J, V12_K,
851 V13, V13_H, V13_J, V13_K,
852 V14, V14_H, V14_J, V14_K,
853 V15, V15_H, V15_J, V15_K,
854 V16, V16_H, V16_J, V16_K,
855 V17, V17_H, V17_J, V17_K,
856 V18, V18_H, V18_J, V18_K,
857 V19, V19_H, V19_J, V19_K,
858 V20, V20_H, V20_J, V20_K,
859 V21, V21_H, V21_J, V21_K,
860 V22, V22_H, V22_J, V22_K,
861 V23, V23_H, V23_J, V23_K,
862 V24, V24_H, V24_J, V24_K,
863 V25, V25_H, V25_J, V25_K,
864 V26, V26_H, V26_J, V26_K,
865 V27, V27_H, V27_J, V27_K,
866 V28, V28_H, V28_J, V28_K,
867 V29, V29_H, V29_J, V29_K
868 );
869
870 // Class for 64 bit register f0
871 reg_class f0_reg(
872 F0, F0_H
873 );
874
875 // Class for 64 bit register f1
876 reg_class f1_reg(
877 F1, F1_H
878 );
879
880 // Class for 64 bit register f2
881 reg_class f2_reg(
882 F2, F2_H
883 );
884
885 // Class for 64 bit register f3
886 reg_class f3_reg(
887 F3, F3_H
888 );
889
890 // class for vector register v1
891 reg_class v1_reg(
892 V1, V1_H, V1_J, V1_K
893 );
894
895 // class for vector register v2
896 reg_class v2_reg(
897 V2, V2_H, V2_J, V2_K
898 );
899
900 // class for vector register v3
901 reg_class v3_reg(
902 V3, V3_H, V3_J, V3_K
903 );
904
905 // class for vector register v4
906 reg_class v4_reg(
907 V4, V4_H, V4_J, V4_K
908 );
909
910 // class for vector register v5
911 reg_class v5_reg(
912 V5, V5_H, V5_J, V5_K
913 );
914
915 // class for vector register v6
916 reg_class v6_reg(
917 V6, V6_H, V6_J, V6_K
918 );
919
920 // class for vector register v7
921 reg_class v7_reg(
922 V7, V7_H, V7_J, V7_K
923 );
924
925 // class for vector register v8
926 reg_class v8_reg(
927 V8, V8_H, V8_J, V8_K
928 );
929
930 // class for vector register v9
931 reg_class v9_reg(
932 V9, V9_H, V9_J, V9_K
933 );
934
935 // class for vector register v10
936 reg_class v10_reg(
937 V10, V10_H, V10_J, V10_K
938 );
939
940 // class for vector register v11
941 reg_class v11_reg(
942 V11, V11_H, V11_J, V11_K
943 );
944
945 // class for condition codes
946 reg_class reg_flags(RFLAGS);
947
948 // Class for RVV v0 mask register
949 // https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#53-vector-masking
950 // The mask value used to control execution of a masked vector
951 // instruction is always supplied by vector register v0.
952 reg_class vmask_reg_v0 (
953 V0
954 );
955
956 // Class for RVV mask registers
957 // We need two more vmask registers to do the vector mask logical ops,
958 // so define v30, v31 as mask register too.
959 reg_class vmask_reg (
960 V0,
961 V30,
962 V31
963 );
964 %}
965
966 //----------DEFINITION BLOCK---------------------------------------------------
967 // Define name --> value mappings to inform the ADLC of an integer valued name
968 // Current support includes integer values in the range [0, 0x7FFFFFFF]
969 // Format:
970 // int_def <name> ( <int_value>, <expression>);
971 // Generated Code in ad_<arch>.hpp
972 // #define <name> (<expression>)
973 // // value == <int_value>
974 // Generated code in ad_<arch>.cpp adlc_verification()
975 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
976 //
977
978 // we follow the ppc-aix port in using a simple cost model which ranks
979 // register operations as cheap, memory ops as more expensive and
980 // branches as most expensive. the first two have a low as well as a
981 // normal cost. huge cost appears to be a way of saying don't do
982 // something
983
984 definitions %{
985 // The default cost (of a register move instruction).
986 int_def DEFAULT_COST ( 100, 100);
987 int_def ALU_COST ( 100, 1 * DEFAULT_COST); // unknown, const, arith, shift, slt,
988 // multi, auipc, nop, logical, move
989 int_def LOAD_COST ( 300, 3 * DEFAULT_COST); // load, fpload
990 int_def STORE_COST ( 100, 1 * DEFAULT_COST); // store, fpstore
991 int_def XFER_COST ( 300, 3 * DEFAULT_COST); // mfc, mtc, fcvt, fmove, fcmp
992 int_def FMVX_COST ( 100, 1 * DEFAULT_COST); // shuffles with no conversion
993 int_def BRANCH_COST ( 200, 2 * DEFAULT_COST); // branch, jmp, call
994 int_def IMUL_COST ( 1000, 10 * DEFAULT_COST); // imul
995 int_def IDIVSI_COST ( 3400, 34 * DEFAULT_COST); // idivsi
996 int_def IDIVDI_COST ( 6600, 66 * DEFAULT_COST); // idivdi
997 int_def FMUL_SINGLE_COST ( 500, 5 * DEFAULT_COST); // fmul, fmadd
998 int_def FMUL_DOUBLE_COST ( 700, 7 * DEFAULT_COST); // fmul, fmadd
999 int_def FDIV_COST ( 2000, 20 * DEFAULT_COST); // fdiv
1000 int_def FSQRT_COST ( 2500, 25 * DEFAULT_COST); // fsqrt
1001 int_def VOLATILE_REF_COST ( 1000, 10 * DEFAULT_COST);
1002 int_def CACHE_MISS_COST ( 2000, 20 * DEFAULT_COST); // typicall cache miss penalty
1003 %}
1004
1005
1006
1007 //----------SOURCE BLOCK-------------------------------------------------------
1008 // This is a block of C++ code which provides values, functions, and
1009 // definitions necessary in the rest of the architecture description
1010
1011 source_hpp %{
1012
1013 #include "asm/macroAssembler.hpp"
1014 #include "gc/shared/barrierSetAssembler.hpp"
1015 #include "gc/shared/cardTable.hpp"
1016 #include "gc/shared/cardTableBarrierSet.hpp"
1017 #include "gc/shared/collectedHeap.hpp"
1018 #include "opto/addnode.hpp"
1019 #include "opto/convertnode.hpp"
1020 #include "runtime/objectMonitor.hpp"
1021
1022 extern RegMask _ANY_REG32_mask;
1023 extern RegMask _ANY_REG_mask;
1024 extern RegMask _PTR_REG_mask;
1025 extern RegMask _NO_SPECIAL_REG32_mask;
1026 extern RegMask _NO_SPECIAL_REG_mask;
1027 extern RegMask _NO_SPECIAL_PTR_REG_mask;
1028 extern RegMask _NO_SPECIAL_NO_FP_PTR_REG_mask;
1029
1030 class CallStubImpl {
1031
1032 //--------------------------------------------------------------
1033 //---< Used for optimization in Compile::shorten_branches >---
1034 //--------------------------------------------------------------
1035
1036 public:
1037 // Size of call trampoline stub.
1038 static uint size_call_trampoline() {
1039 return 0; // no call trampolines on this platform
1040 }
1041
1042 // number of relocations needed by a call trampoline stub
1043 static uint reloc_call_trampoline() {
1044 return 0; // no call trampolines on this platform
1045 }
1046 };
1047
1048 class HandlerImpl {
1049
1050 public:
1051
1052 static int emit_deopt_handler(C2_MacroAssembler* masm);
1053
1054 static uint size_deopt_handler() {
1055 // count far call + j
1056 return NativeInstruction::instruction_size + MacroAssembler::far_branch_size();
1057 }
1058 };
1059
1060 class Node::PD {
1061 public:
1062 enum NodeFlags {
1063 _last_flag = Node::_last_flag
1064 };
1065 };
1066
1067 bool is_CAS(int opcode, bool maybe_volatile);
1068
1069 // predicate controlling translation of CompareAndSwapX
1070 bool needs_acquiring_load_reserved(const Node *load);
1071
1072 // predicate controlling addressing modes
1073 bool size_fits_all_mem_uses(AddPNode* addp, int shift);
1074 %}
1075
1076 source %{
1077
1078 // Derived RegMask with conditionally allocatable registers
1079
1080 RegMask _ANY_REG32_mask;
1081 RegMask _ANY_REG_mask;
1082 RegMask _PTR_REG_mask;
1083 RegMask _NO_SPECIAL_REG32_mask;
1084 RegMask _NO_SPECIAL_REG_mask;
1085 RegMask _NO_SPECIAL_PTR_REG_mask;
1086 RegMask _NO_SPECIAL_NO_FP_PTR_REG_mask;
1087
1088 void reg_mask_init() {
1089
1090 _ANY_REG32_mask.assignFrom(_ALL_REG32_mask);
1091 _ANY_REG32_mask.remove(OptoReg::as_OptoReg(x0->as_VMReg()));
1092
1093 _ANY_REG_mask.assignFrom(_ALL_REG_mask);
1094 _ANY_REG_mask.subtract(_ZR_REG_mask);
1095
1096 _PTR_REG_mask.assignFrom(_ALL_REG_mask);
1097 _PTR_REG_mask.subtract(_ZR_REG_mask);
1098
1099 _NO_SPECIAL_REG32_mask.assignFrom(_ALL_REG32_mask);
1100 _NO_SPECIAL_REG32_mask.subtract(_NON_ALLOCATABLE_REG32_mask);
1101
1102 _NO_SPECIAL_REG_mask.assignFrom(_ALL_REG_mask);
1103 _NO_SPECIAL_REG_mask.subtract(_NON_ALLOCATABLE_REG_mask);
1104
1105 _NO_SPECIAL_PTR_REG_mask.assignFrom(_ALL_REG_mask);
1106 _NO_SPECIAL_PTR_REG_mask.subtract(_NON_ALLOCATABLE_REG_mask);
1107
1108 // x27 is not allocatable when compressed oops is on
1109 if (UseCompressedOops) {
1110 _NO_SPECIAL_REG32_mask.remove(OptoReg::as_OptoReg(x27->as_VMReg()));
1111 _NO_SPECIAL_REG_mask.remove(OptoReg::as_OptoReg(x27->as_VMReg()));
1112 _NO_SPECIAL_PTR_REG_mask.remove(OptoReg::as_OptoReg(x27->as_VMReg()));
1113 }
1114
1115 // x8 is not allocatable when PreserveFramePointer is on
1116 if (PreserveFramePointer) {
1117 _NO_SPECIAL_REG32_mask.remove(OptoReg::as_OptoReg(x8->as_VMReg()));
1118 _NO_SPECIAL_REG_mask.remove(OptoReg::as_OptoReg(x8->as_VMReg()));
1119 _NO_SPECIAL_PTR_REG_mask.remove(OptoReg::as_OptoReg(x8->as_VMReg()));
1120 }
1121
1122 _NO_SPECIAL_NO_FP_PTR_REG_mask.assignFrom(_NO_SPECIAL_PTR_REG_mask);
1123 _NO_SPECIAL_NO_FP_PTR_REG_mask.remove(OptoReg::as_OptoReg(x8->as_VMReg()));
1124 }
1125
1126 void PhaseOutput::pd_perform_mach_node_analysis() {
1127 }
1128
1129 int MachNode::pd_alignment_required() const {
1130 return 1;
1131 }
1132
1133 int MachNode::compute_padding(int current_offset) const {
1134 return 0;
1135 }
1136
1137 // is_CAS(int opcode, bool maybe_volatile)
1138 //
1139 // return true if opcode is one of the possible CompareAndSwapX
1140 // values otherwise false.
1141 bool is_CAS(int opcode, bool maybe_volatile)
1142 {
1143 switch (opcode) {
1144 // We handle these
1145 case Op_CompareAndSwapI:
1146 case Op_CompareAndSwapL:
1147 case Op_CompareAndSwapP:
1148 case Op_CompareAndSwapN:
1149 case Op_ShenandoahCompareAndSwapP:
1150 case Op_ShenandoahCompareAndSwapN:
1151 case Op_CompareAndSwapB:
1152 case Op_CompareAndSwapS:
1153 case Op_GetAndSetI:
1154 case Op_GetAndSetL:
1155 case Op_GetAndSetP:
1156 case Op_GetAndSetN:
1157 case Op_GetAndAddI:
1158 case Op_GetAndAddL:
1159 return true;
1160 case Op_CompareAndExchangeI:
1161 case Op_CompareAndExchangeN:
1162 case Op_CompareAndExchangeB:
1163 case Op_CompareAndExchangeS:
1164 case Op_CompareAndExchangeL:
1165 case Op_CompareAndExchangeP:
1166 case Op_WeakCompareAndSwapB:
1167 case Op_WeakCompareAndSwapS:
1168 case Op_WeakCompareAndSwapI:
1169 case Op_WeakCompareAndSwapL:
1170 case Op_WeakCompareAndSwapP:
1171 case Op_WeakCompareAndSwapN:
1172 case Op_ShenandoahWeakCompareAndSwapP:
1173 case Op_ShenandoahWeakCompareAndSwapN:
1174 case Op_ShenandoahCompareAndExchangeP:
1175 case Op_ShenandoahCompareAndExchangeN:
1176 return maybe_volatile;
1177 default:
1178 return false;
1179 }
1180 }
1181
1182 constexpr uint64_t MAJIK_DWORD = 0xabbaabbaabbaabbaull;
1183
1184 // predicate controlling translation of CAS
1185 //
1186 // returns true if CAS needs to use an acquiring load otherwise false
1187 bool needs_acquiring_load_reserved(const Node *n)
1188 {
1189 assert(n != nullptr && is_CAS(n->Opcode(), true), "expecting a compare and swap");
1190
1191 LoadStoreNode* ldst = n->as_LoadStore();
1192 if (n != nullptr && is_CAS(n->Opcode(), false)) {
1193 assert(ldst != nullptr && ldst->trailing_membar() != nullptr, "expected trailing membar");
1194 } else {
1195 return ldst != nullptr && ldst->trailing_membar() != nullptr;
1196 }
1197 // so we can just return true here
1198 return true;
1199 }
1200 #define __ masm->
1201
1202 // advance declarations for helper functions to convert register
1203 // indices to register objects
1204
1205 // the ad file has to provide implementations of certain methods
1206 // expected by the generic code
1207 //
1208 // REQUIRED FUNCTIONALITY
1209
1210 //=============================================================================
1211
1212 // !!!!! Special hack to get all types of calls to specify the byte offset
1213 // from the start of the call to the point where the return address
1214 // will point.
1215
1216 int MachCallStaticJavaNode::ret_addr_offset()
1217 {
1218 return 3 * NativeInstruction::instruction_size; // auipc + ld + jalr
1219 }
1220
1221 int MachCallDynamicJavaNode::ret_addr_offset()
1222 {
1223 return NativeMovConstReg::movptr2_instruction_size + (3 * NativeInstruction::instruction_size); // movptr2, auipc + ld + jal
1224 }
1225
1226 int MachCallRuntimeNode::ret_addr_offset() {
1227 // For address inside the code cache the call will be:
1228 // auipc + jalr
1229 // For real runtime callouts it will be 8 instructions
1230 // see riscv_enc_java_to_runtime
1231 // la(t0, retaddr) -> auipc + addi
1232 // sd(t0, Address(xthread, JavaThread::last_Java_pc_offset())) -> sd
1233 // movptr(t1, addr, offset, t0) -> lui + lui + slli + add
1234 // jalr(t1, offset) -> jalr
1235 if (CodeCache::contains(_entry_point)) {
1236 return 2 * NativeInstruction::instruction_size;
1237 } else {
1238 return 8 * NativeInstruction::instruction_size;
1239 }
1240 }
1241
1242 //
1243 // Compute padding required for nodes which need alignment
1244 //
1245
1246 // With RVC a call instruction may get 2-byte aligned.
1247 // The address of the call instruction needs to be 4-byte aligned to
1248 // ensure that it does not span a cache line so that it can be patched.
1249 int CallStaticJavaDirectNode::compute_padding(int current_offset) const
1250 {
1251 // to make sure the address of jal 4-byte aligned.
1252 return align_up(current_offset, alignment_required()) - current_offset;
1253 }
1254
1255 // With RVC a call instruction may get 2-byte aligned.
1256 // The address of the call instruction needs to be 4-byte aligned to
1257 // ensure that it does not span a cache line so that it can be patched.
1258 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const
1259 {
1260 // skip the movptr2 in MacroAssembler::ic_call():
1261 // lui, lui, slli, add, addi
1262 // Though movptr2() has already 4-byte aligned with or without RVC,
1263 // We need to prevent from further changes by explicitly calculating the size.
1264 current_offset += NativeMovConstReg::movptr2_instruction_size;
1265 // to make sure the address of jal 4-byte aligned.
1266 return align_up(current_offset, alignment_required()) - current_offset;
1267 }
1268
1269 int CallRuntimeDirectNode::compute_padding(int current_offset) const
1270 {
1271 return align_up(current_offset, alignment_required()) - current_offset;
1272 }
1273
1274 int CallLeafDirectNode::compute_padding(int current_offset) const
1275 {
1276 return align_up(current_offset, alignment_required()) - current_offset;
1277 }
1278
1279 int CallLeafDirectVectorNode::compute_padding(int current_offset) const
1280 {
1281 return align_up(current_offset, alignment_required()) - current_offset;
1282 }
1283
1284 int CallLeafNoFPDirectNode::compute_padding(int current_offset) const
1285 {
1286 return align_up(current_offset, alignment_required()) - current_offset;
1287 }
1288
1289 //=============================================================================
1290
1291 #ifndef PRODUCT
1292 void MachBreakpointNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1293 assert_cond(st != nullptr);
1294 st->print("BREAKPOINT");
1295 }
1296 #endif
1297
1298 void MachBreakpointNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
1299 __ ebreak();
1300 }
1301
1302 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
1303 return MachNode::size(ra_);
1304 }
1305
1306 //=============================================================================
1307
1308 #ifndef PRODUCT
1309 void MachNopNode::format(PhaseRegAlloc*, outputStream* st) const {
1310 st->print("nop \t# %d bytes pad for loops and calls", _count);
1311 }
1312 #endif
1313
1314 void MachNopNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc*) const {
1315 Assembler::CompressibleScope scope(masm); // nops shall be 2-byte under RVC for alignment purposes.
1316 for (int i = 0; i < _count; i++) {
1317 __ nop();
1318 }
1319 }
1320
1321 uint MachNopNode::size(PhaseRegAlloc*) const {
1322 return _count * (UseRVC ? NativeInstruction::compressed_instruction_size : NativeInstruction::instruction_size);
1323 }
1324
1325 //=============================================================================
1326 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::EMPTY;
1327
1328 int ConstantTable::calculate_table_base_offset() const {
1329 return 0; // absolute addressing, no offset
1330 }
1331
1332 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
1333 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
1334 ShouldNotReachHere();
1335 }
1336
1337 void MachConstantBaseNode::emit(C2_MacroAssembler* masm, PhaseRegAlloc* ra_) const {
1338 // Empty encoding
1339 }
1340
1341 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
1342 return 0;
1343 }
1344
1345 #ifndef PRODUCT
1346 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1347 assert_cond(st != nullptr);
1348 st->print("-- \t// MachConstantBaseNode (empty encoding)");
1349 }
1350 #endif
1351
1352 #ifndef PRODUCT
1353 void MachPrologNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1354 assert_cond(st != nullptr && ra_ != nullptr);
1355 Compile* C = ra_->C;
1356
1357 int framesize = C->output()->frame_slots() << LogBytesPerInt;
1358
1359 if (C->output()->need_stack_bang(framesize)) {
1360 st->print("# stack bang size=%d\n\t", framesize);
1361 }
1362
1363 st->print("sub sp, sp, #%d\n\t", framesize);
1364 st->print("sd fp, [sp, #%d]\n\t", framesize - 2 * wordSize);
1365 st->print("sd ra, [sp, #%d]\n\t", framesize - wordSize);
1366 if (PreserveFramePointer) { st->print("add fp, sp, #%d\n\t", framesize); }
1367
1368 if (VerifyStackAtCalls) {
1369 st->print("mv t2, %ld\n\t", MAJIK_DWORD);
1370 st->print("sd t2, [sp, #%d]\n\t", framesize - 3 * wordSize);
1371 }
1372
1373 if (C->stub_function() == nullptr) {
1374 st->print("ld t0, [guard]\n\t");
1375 st->print("membar LoadLoad\n\t");
1376 st->print("ld t1, [xthread, #thread_disarmed_guard_value_offset]\n\t");
1377 st->print("beq t0, t1, skip\n\t");
1378 st->print("jalr #nmethod_entry_barrier_stub\n\t");
1379 st->print("j skip\n\t");
1380 st->print("guard: int\n\t");
1381 st->print("skip:\n\t");
1382 }
1383 }
1384 #endif
1385
1386 void MachPrologNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
1387 assert_cond(ra_ != nullptr);
1388 Compile* C = ra_->C;
1389
1390 // n.b. frame size includes space for return pc and fp
1391 const int framesize = C->output()->frame_size_in_bytes();
1392
1393 assert_cond(C != nullptr);
1394
1395 if (C->clinit_barrier_on_entry()) {
1396 assert(!C->method()->holder()->is_not_initialized(), "initialization should have been started");
1397
1398 Label L_skip_barrier;
1399
1400 __ mov_metadata(t1, C->method()->holder()->constant_encoding());
1401 __ clinit_barrier(t1, t0, &L_skip_barrier);
1402 __ far_jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub()));
1403 __ bind(L_skip_barrier);
1404 }
1405
1406 int bangsize = C->output()->bang_size_in_bytes();
1407 if (C->output()->need_stack_bang(bangsize)) {
1408 __ generate_stack_overflow_check(bangsize);
1409 }
1410
1411 __ build_frame(framesize);
1412
1413 if (VerifyStackAtCalls) {
1414 __ mv(t2, MAJIK_DWORD);
1415 __ sd(t2, Address(sp, framesize - 3 * wordSize));
1416 }
1417
1418 if (C->stub_function() == nullptr) {
1419 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
1420 // Dummy labels for just measuring the code size
1421 Label dummy_slow_path;
1422 Label dummy_continuation;
1423 Label dummy_guard;
1424 Label* slow_path = &dummy_slow_path;
1425 Label* continuation = &dummy_continuation;
1426 Label* guard = &dummy_guard;
1427 if (!Compile::current()->output()->in_scratch_emit_size()) {
1428 // Use real labels from actual stub when not emitting code for purpose of measuring its size
1429 C2EntryBarrierStub* stub = new (Compile::current()->comp_arena()) C2EntryBarrierStub();
1430 Compile::current()->output()->add_stub(stub);
1431 slow_path = &stub->entry();
1432 continuation = &stub->continuation();
1433 guard = &stub->guard();
1434 }
1435 // In the C2 code, we move the non-hot part of nmethod entry barriers out-of-line to a stub.
1436 bs->nmethod_entry_barrier(masm, slow_path, continuation, guard);
1437 }
1438
1439 C->output()->set_frame_complete(__ offset());
1440
1441 if (C->has_mach_constant_base_node()) {
1442 // NOTE: We set the table base offset here because users might be
1443 // emitted before MachConstantBaseNode.
1444 ConstantTable& constant_table = C->output()->constant_table();
1445 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
1446 }
1447 }
1448
1449 uint MachPrologNode::size(PhaseRegAlloc* ra_) const
1450 {
1451 assert_cond(ra_ != nullptr);
1452 return MachNode::size(ra_); // too many variables; just compute it
1453 // the hard way
1454 }
1455
1456 int MachPrologNode::reloc() const
1457 {
1458 return 0;
1459 }
1460
1461 //=============================================================================
1462
1463 #ifndef PRODUCT
1464 void MachEpilogNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1465 assert_cond(st != nullptr && ra_ != nullptr);
1466 Compile* C = ra_->C;
1467 assert_cond(C != nullptr);
1468 int framesize = C->output()->frame_size_in_bytes();
1469
1470 st->print("# pop frame %d\n\t", framesize);
1471
1472 if (framesize == 0) {
1473 st->print("ld ra, [sp,#%d]\n\t", (2 * wordSize));
1474 st->print("ld fp, [sp,#%d]\n\t", (3 * wordSize));
1475 st->print("add sp, sp, #%d\n\t", (2 * wordSize));
1476 } else {
1477 st->print("add sp, sp, #%d\n\t", framesize);
1478 st->print("ld ra, [sp,#%d]\n\t", - 2 * wordSize);
1479 st->print("ld fp, [sp,#%d]\n\t", - wordSize);
1480 }
1481
1482 if (do_polling() && C->is_method_compilation()) {
1483 st->print("# test polling word\n\t");
1484 st->print("ld t0, [xthread,#%d]\n\t", in_bytes(JavaThread::polling_word_offset()));
1485 st->print("bgtu sp, t0, #slow_path");
1486 }
1487 }
1488 #endif
1489
1490 void MachEpilogNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
1491 assert_cond(ra_ != nullptr);
1492 Compile* C = ra_->C;
1493 assert_cond(C != nullptr);
1494 int framesize = C->output()->frame_size_in_bytes();
1495
1496 __ remove_frame(framesize);
1497
1498 if (StackReservedPages > 0 && C->has_reserved_stack_access()) {
1499 __ reserved_stack_check();
1500 }
1501
1502 if (do_polling() && C->is_method_compilation()) {
1503 Label dummy_label;
1504 Label* code_stub = &dummy_label;
1505 if (!C->output()->in_scratch_emit_size()) {
1506 C2SafepointPollStub* stub = new (C->comp_arena()) C2SafepointPollStub(__ offset());
1507 C->output()->add_stub(stub);
1508 code_stub = &stub->entry();
1509 }
1510 __ relocate(relocInfo::poll_return_type);
1511 __ safepoint_poll(*code_stub, true /* at_return */, true /* in_nmethod */);
1512 }
1513 }
1514
1515 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
1516 assert_cond(ra_ != nullptr);
1517 // Variable size. Determine dynamically.
1518 return MachNode::size(ra_);
1519 }
1520
1521 int MachEpilogNode::reloc() const {
1522 // Return number of relocatable values contained in this instruction.
1523 return 1; // 1 for polling page.
1524 }
1525 const Pipeline * MachEpilogNode::pipeline() const {
1526 return MachNode::pipeline_class();
1527 }
1528
1529 //=============================================================================
1530
1531 // Figure out which register class each belongs in: rc_int, rc_float or
1532 // rc_stack.
1533 enum RC { rc_bad, rc_int, rc_float, rc_vector, rc_stack };
1534
1535 static enum RC rc_class(OptoReg::Name reg) {
1536
1537 if (reg == OptoReg::Bad) {
1538 return rc_bad;
1539 }
1540
1541 // we have 30 int registers * 2 halves
1542 // (t0 and t1 are omitted)
1543 int slots_of_int_registers = Register::max_slots_per_register * (Register::number_of_registers - 2);
1544 if (reg < slots_of_int_registers) {
1545 return rc_int;
1546 }
1547
1548 // we have 32 float register * 2 halves
1549 int slots_of_float_registers = FloatRegister::max_slots_per_register * FloatRegister::number_of_registers;
1550 if (reg < slots_of_int_registers + slots_of_float_registers) {
1551 return rc_float;
1552 }
1553
1554 // we have 32 vector register * 4 halves
1555 int slots_of_vector_registers = VectorRegister::max_slots_per_register * VectorRegister::number_of_registers;
1556 if (reg < slots_of_int_registers + slots_of_float_registers + slots_of_vector_registers) {
1557 return rc_vector;
1558 }
1559
1560 // Between vector regs & stack is the flags regs.
1561 assert(OptoReg::is_stack(reg), "blow up if spilling flags");
1562
1563 return rc_stack;
1564 }
1565
1566 uint MachSpillCopyNode::implementation(C2_MacroAssembler *masm, PhaseRegAlloc *ra_, bool do_size, outputStream *st) const {
1567 assert_cond(ra_ != nullptr);
1568 Compile* C = ra_->C;
1569
1570 // Get registers to move.
1571 OptoReg::Name src_hi = ra_->get_reg_second(in(1));
1572 OptoReg::Name src_lo = ra_->get_reg_first(in(1));
1573 OptoReg::Name dst_hi = ra_->get_reg_second(this);
1574 OptoReg::Name dst_lo = ra_->get_reg_first(this);
1575
1576 enum RC src_hi_rc = rc_class(src_hi);
1577 enum RC src_lo_rc = rc_class(src_lo);
1578 enum RC dst_hi_rc = rc_class(dst_hi);
1579 enum RC dst_lo_rc = rc_class(dst_lo);
1580
1581 assert(src_lo != OptoReg::Bad && dst_lo != OptoReg::Bad, "must move at least 1 register");
1582
1583 if (src_hi != OptoReg::Bad && !bottom_type()->isa_vectmask()) {
1584 assert((src_lo & 1) == 0 && src_lo + 1 == src_hi &&
1585 (dst_lo & 1) == 0 && dst_lo + 1 == dst_hi,
1586 "expected aligned-adjacent pairs");
1587 }
1588
1589 if (src_lo == dst_lo && src_hi == dst_hi) {
1590 return 0; // Self copy, no move.
1591 }
1592
1593 bool is64 = (src_lo & 1) == 0 && src_lo + 1 == src_hi &&
1594 (dst_lo & 1) == 0 && dst_lo + 1 == dst_hi;
1595 int src_offset = ra_->reg2offset(src_lo);
1596 int dst_offset = ra_->reg2offset(dst_lo);
1597
1598 if (bottom_type()->isa_vect() != nullptr) {
1599 uint ireg = ideal_reg();
1600 if (ireg == Op_VecA && masm) {
1601 int vector_reg_size_in_bytes = Matcher::scalable_vector_reg_size(T_BYTE);
1602 if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
1603 // stack to stack
1604 __ spill_copy_vector_stack_to_stack(src_offset, dst_offset,
1605 vector_reg_size_in_bytes);
1606 } else if (src_lo_rc == rc_vector && dst_lo_rc == rc_stack) {
1607 // vpr to stack
1608 __ spill(as_VectorRegister(Matcher::_regEncode[src_lo]), ra_->reg2offset(dst_lo));
1609 } else if (src_lo_rc == rc_stack && dst_lo_rc == rc_vector) {
1610 // stack to vpr
1611 __ unspill(as_VectorRegister(Matcher::_regEncode[dst_lo]), ra_->reg2offset(src_lo));
1612 } else if (src_lo_rc == rc_vector && dst_lo_rc == rc_vector) {
1613 // vpr to vpr
1614 __ vsetvli_helper(T_BYTE, MaxVectorSize);
1615 __ vmv_v_v(as_VectorRegister(Matcher::_regEncode[dst_lo]), as_VectorRegister(Matcher::_regEncode[src_lo]));
1616 } else {
1617 ShouldNotReachHere();
1618 }
1619 } else if (bottom_type()->isa_vectmask() && masm) {
1620 int vmask_size_in_bytes = Matcher::scalable_predicate_reg_slots() * 32 / 8;
1621 if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
1622 // stack to stack
1623 __ spill_copy_vmask_stack_to_stack(src_offset, dst_offset,
1624 vmask_size_in_bytes);
1625 } else if (src_lo_rc == rc_vector && dst_lo_rc == rc_stack) {
1626 // vmask to stack
1627 __ spill_vmask(as_VectorRegister(Matcher::_regEncode[src_lo]), ra_->reg2offset(dst_lo));
1628 } else if (src_lo_rc == rc_stack && dst_lo_rc == rc_vector) {
1629 // stack to vmask
1630 __ unspill_vmask(as_VectorRegister(Matcher::_regEncode[dst_lo]), ra_->reg2offset(src_lo));
1631 } else if (src_lo_rc == rc_vector && dst_lo_rc == rc_vector) {
1632 // vmask to vmask
1633 __ vsetvli_helper(T_BYTE, MaxVectorSize >> 3);
1634 __ vmv_v_v(as_VectorRegister(Matcher::_regEncode[dst_lo]), as_VectorRegister(Matcher::_regEncode[src_lo]));
1635 } else {
1636 ShouldNotReachHere();
1637 }
1638 }
1639 } else if (masm != nullptr) {
1640 switch (src_lo_rc) {
1641 case rc_int:
1642 if (dst_lo_rc == rc_int) { // gpr --> gpr copy
1643 if (!is64 && this->ideal_reg() != Op_RegI) { // zero extended for narrow oop or klass
1644 __ zext(as_Register(Matcher::_regEncode[dst_lo]), as_Register(Matcher::_regEncode[src_lo]), 32);
1645 } else {
1646 __ mv(as_Register(Matcher::_regEncode[dst_lo]), as_Register(Matcher::_regEncode[src_lo]));
1647 }
1648 } else if (dst_lo_rc == rc_float) { // gpr --> fpr copy
1649 if (is64) {
1650 __ fmv_d_x(as_FloatRegister(Matcher::_regEncode[dst_lo]),
1651 as_Register(Matcher::_regEncode[src_lo]));
1652 } else {
1653 __ fmv_w_x(as_FloatRegister(Matcher::_regEncode[dst_lo]),
1654 as_Register(Matcher::_regEncode[src_lo]));
1655 }
1656 } else { // gpr --> stack spill
1657 assert(dst_lo_rc == rc_stack, "spill to bad register class");
1658 __ spill(as_Register(Matcher::_regEncode[src_lo]), is64, dst_offset);
1659 }
1660 break;
1661 case rc_float:
1662 if (dst_lo_rc == rc_int) { // fpr --> gpr copy
1663 if (is64) {
1664 __ fmv_x_d(as_Register(Matcher::_regEncode[dst_lo]),
1665 as_FloatRegister(Matcher::_regEncode[src_lo]));
1666 } else {
1667 __ fmv_x_w(as_Register(Matcher::_regEncode[dst_lo]),
1668 as_FloatRegister(Matcher::_regEncode[src_lo]));
1669 }
1670 } else if (dst_lo_rc == rc_float) { // fpr --> fpr copy
1671 if (is64) {
1672 __ fmv_d(as_FloatRegister(Matcher::_regEncode[dst_lo]),
1673 as_FloatRegister(Matcher::_regEncode[src_lo]));
1674 } else {
1675 __ fmv_s(as_FloatRegister(Matcher::_regEncode[dst_lo]),
1676 as_FloatRegister(Matcher::_regEncode[src_lo]));
1677 }
1678 } else { // fpr --> stack spill
1679 assert(dst_lo_rc == rc_stack, "spill to bad register class");
1680 __ spill(as_FloatRegister(Matcher::_regEncode[src_lo]),
1681 is64, dst_offset);
1682 }
1683 break;
1684 case rc_stack:
1685 if (dst_lo_rc == rc_int) { // stack --> gpr load
1686 if (this->ideal_reg() == Op_RegI) {
1687 __ unspill(as_Register(Matcher::_regEncode[dst_lo]), is64, src_offset);
1688 } else { // // zero extended for narrow oop or klass
1689 __ unspillu(as_Register(Matcher::_regEncode[dst_lo]), is64, src_offset);
1690 }
1691 } else if (dst_lo_rc == rc_float) { // stack --> fpr load
1692 __ unspill(as_FloatRegister(Matcher::_regEncode[dst_lo]),
1693 is64, src_offset);
1694 } else { // stack --> stack copy
1695 assert(dst_lo_rc == rc_stack, "spill to bad register class");
1696 if (this->ideal_reg() == Op_RegI) {
1697 __ unspill(t0, is64, src_offset);
1698 } else { // zero extended for narrow oop or klass
1699 __ unspillu(t0, is64, src_offset);
1700 }
1701 __ spill(t0, is64, dst_offset);
1702 }
1703 break;
1704 default:
1705 ShouldNotReachHere();
1706 }
1707 }
1708
1709 if (st != nullptr) {
1710 st->print("spill ");
1711 if (src_lo_rc == rc_stack) {
1712 st->print("[sp, #%d] -> ", src_offset);
1713 } else {
1714 st->print("%s -> ", Matcher::regName[src_lo]);
1715 }
1716 if (dst_lo_rc == rc_stack) {
1717 st->print("[sp, #%d]", dst_offset);
1718 } else {
1719 st->print("%s", Matcher::regName[dst_lo]);
1720 }
1721 if (bottom_type()->isa_vect() && !bottom_type()->isa_vectmask()) {
1722 int vsize = 0;
1723 if (ideal_reg() == Op_VecA) {
1724 vsize = Matcher::scalable_vector_reg_size(T_BYTE) * 8;
1725 } else {
1726 ShouldNotReachHere();
1727 }
1728 st->print("\t# vector spill size = %d", vsize);
1729 } else if (ideal_reg() == Op_RegVectMask) {
1730 assert(Matcher::supports_scalable_vector(), "bad register type for spill");
1731 int vsize = Matcher::scalable_predicate_reg_slots() * 32;
1732 st->print("\t# vmask spill size = %d", vsize);
1733 } else {
1734 st->print("\t# spill size = %d", is64 ? 64 : 32);
1735 }
1736 }
1737
1738 return 0;
1739 }
1740
1741 #ifndef PRODUCT
1742 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1743 if (ra_ == nullptr) {
1744 st->print("N%d = SpillCopy(N%d)", _idx, in(1)->_idx);
1745 } else {
1746 implementation(nullptr, ra_, false, st);
1747 }
1748 }
1749 #endif
1750
1751 void MachSpillCopyNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
1752 implementation(masm, ra_, false, nullptr);
1753 }
1754
1755 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1756 return MachNode::size(ra_);
1757 }
1758
1759 //=============================================================================
1760
1761 #ifndef PRODUCT
1762 void BoxLockNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1763 assert_cond(ra_ != nullptr && st != nullptr);
1764 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1765 int reg = ra_->get_reg_first(this);
1766 st->print("add %s, sp, #%d\t# box lock",
1767 Matcher::regName[reg], offset);
1768 }
1769 #endif
1770
1771 void BoxLockNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
1772 Assembler::IncompressibleScope scope(masm); // Fixed length: see BoxLockNode::size()
1773
1774 assert_cond(ra_ != nullptr);
1775 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1776 int reg = ra_->get_encode(this);
1777
1778 if (Assembler::is_simm12(offset)) {
1779 __ addi(as_Register(reg), sp, offset);
1780 } else {
1781 __ li32(t0, offset);
1782 __ add(as_Register(reg), sp, t0);
1783 }
1784 }
1785
1786 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1787 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_).
1788 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1789
1790 if (Assembler::is_simm12(offset)) {
1791 return NativeInstruction::instruction_size;
1792 } else {
1793 return 3 * NativeInstruction::instruction_size; // lui + addiw + add;
1794 }
1795 }
1796
1797 //=============================================================================
1798
1799 #ifndef PRODUCT
1800 void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1801 {
1802 assert_cond(st != nullptr);
1803 st->print_cr("# MachUEPNode");
1804 if (UseCompressedClassPointers) {
1805 st->print_cr("\tlwu t1, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass");
1806 st->print_cr("\tlwu t2, [t0 + CompiledICData::speculated_klass_offset()]\t# compressed klass");
1807 } else {
1808 st->print_cr("\tld t1, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass");
1809 st->print_cr("\tld t2, [t0 + CompiledICData::speculated_klass_offset()]\t# compressed klass");
1810 }
1811 st->print_cr("\tbeq t1, t2, ic_hit");
1812 st->print_cr("\tj, SharedRuntime::_ic_miss_stub\t # Inline cache check");
1813 st->print_cr("\tic_hit:");
1814 }
1815 #endif
1816
1817 void MachUEPNode::emit(C2_MacroAssembler* masm, PhaseRegAlloc* ra_) const
1818 {
1819 // This is the unverified entry point.
1820 __ ic_check(CodeEntryAlignment);
1821
1822 // ic_check() aligns to CodeEntryAlignment >= InteriorEntryAlignment(min 16) > NativeInstruction::instruction_size(4).
1823 assert(((__ offset()) % CodeEntryAlignment) == 0, "Misaligned verified entry point");
1824 }
1825
1826 uint MachUEPNode::size(PhaseRegAlloc* ra_) const
1827 {
1828 assert_cond(ra_ != nullptr);
1829 return MachNode::size(ra_);
1830 }
1831
1832 // REQUIRED EMIT CODE
1833
1834 //=============================================================================
1835
1836 // Emit deopt handler code.
1837 int HandlerImpl::emit_deopt_handler(C2_MacroAssembler* masm)
1838 {
1839 address base = __ start_a_stub(size_deopt_handler());
1840 if (base == nullptr) {
1841 ciEnv::current()->record_failure("CodeCache is full");
1842 return 0; // CodeBuffer::expand failed
1843 }
1844 int offset = __ offset();
1845
1846 Label start;
1847 __ bind(start);
1848
1849 __ far_call(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
1850
1851 int entry_offset = __ offset();
1852 __ j(start);
1853
1854 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1855 assert(__ offset() - entry_offset >= NativePostCallNop::first_check_size,
1856 "out of bounds read in post-call NOP check");
1857 __ end_a_stub();
1858 return entry_offset;
1859
1860 }
1861 // REQUIRED MATCHER CODE
1862
1863 //=============================================================================
1864
1865 bool Matcher::match_rule_supported(int opcode) {
1866 if (!has_match_rule(opcode)) {
1867 return false;
1868 }
1869
1870 switch (opcode) {
1871 case Op_OnSpinWait:
1872 return VM_Version::supports_on_spin_wait();
1873 case Op_CacheWB: // fall through
1874 case Op_CacheWBPreSync: // fall through
1875 case Op_CacheWBPostSync:
1876 if (!VM_Version::supports_data_cache_line_flush()) {
1877 return false;
1878 }
1879 break;
1880
1881 case Op_StrCompressedCopy: // fall through
1882 case Op_StrInflatedCopy: // fall through
1883 case Op_CountPositives: // fall through
1884 case Op_EncodeISOArray:
1885 return UseRVV;
1886
1887 case Op_PopCountI:
1888 case Op_PopCountL:
1889 return UsePopCountInstruction;
1890
1891 case Op_ReverseI:
1892 case Op_ReverseL:
1893 return UseZbkb;
1894
1895 case Op_ReverseBytesI:
1896 case Op_ReverseBytesL:
1897 case Op_ReverseBytesS:
1898 case Op_ReverseBytesUS:
1899 case Op_RotateRight:
1900 case Op_RotateLeft:
1901 case Op_CountLeadingZerosI:
1902 case Op_CountLeadingZerosL:
1903 case Op_CountTrailingZerosI:
1904 case Op_CountTrailingZerosL:
1905 return UseZbb;
1906
1907 case Op_FmaF:
1908 case Op_FmaD:
1909 return UseFMA;
1910
1911 case Op_ConvHF2F:
1912 case Op_ConvF2HF:
1913 return VM_Version::supports_float16_float_conversion();
1914 case Op_ReinterpretS2HF:
1915 case Op_ReinterpretHF2S:
1916 return UseZfh || UseZfhmin;
1917 case Op_AddHF:
1918 case Op_DivHF:
1919 case Op_FmaHF:
1920 case Op_MaxHF:
1921 case Op_MinHF:
1922 case Op_MulHF:
1923 case Op_SqrtHF:
1924 case Op_SubHF:
1925 return UseZfh;
1926
1927 case Op_CMoveF:
1928 case Op_CMoveD:
1929 case Op_CMoveP:
1930 case Op_CMoveN:
1931 return false;
1932 }
1933
1934 return true; // Per default match rules are supported.
1935 }
1936
1937 const RegMask* Matcher::predicate_reg_mask(void) {
1938 return &_VMASK_REG_mask;
1939 }
1940
1941 // Vector calling convention not yet implemented.
1942 bool Matcher::supports_vector_calling_convention(void) {
1943 return EnableVectorSupport;
1944 }
1945
1946 OptoRegPair Matcher::vector_return_value(uint ideal_reg) {
1947 assert(EnableVectorSupport, "sanity");
1948 assert(ideal_reg == Op_VecA, "sanity");
1949 // check more info at https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-cc.adoc
1950 int lo = V8_num;
1951 int hi = V8_K_num;
1952 return OptoRegPair(hi, lo);
1953 }
1954
1955 // Is this branch offset short enough that a short branch can be used?
1956 //
1957 // NOTE: If the platform does not provide any short branch variants, then
1958 // this method should return false for offset 0.
1959 // |---label(L1)-----|
1960 // |-----------------|
1961 // |-----------------|----------eq: float-------------------
1962 // |-----------------| // far_cmpD_branch | cmpD_branch
1963 // |------- ---------| feq; | feq;
1964 // |-far_cmpD_branch-| beqz done; | bnez L;
1965 // |-----------------| j L; |
1966 // |-----------------| bind(done); |
1967 // |-----------------|--------------------------------------
1968 // |-----------------| // so shortBrSize = br_size - 4;
1969 // |-----------------| // so offs = offset - shortBrSize + 4;
1970 // |---label(L2)-----|
1971 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1972 // The passed offset is relative to address of the branch.
1973 int shortBrSize = br_size - 4;
1974 int offs = offset - shortBrSize + 4;
1975 return (-4096 <= offs && offs < 4096);
1976 }
1977
1978 // Vector width in bytes.
1979 int Matcher::vector_width_in_bytes(BasicType bt) {
1980 if (UseRVV) {
1981 // The MaxVectorSize should have been set by detecting RVV max vector register size when check UseRVV.
1982 // MaxVectorSize == VM_Version::_initial_vector_length
1983 int size = MaxVectorSize;
1984 // Minimum 2 values in vector
1985 if (size < 2 * type2aelembytes(bt)) size = 0;
1986 // But never < 4
1987 if (size < 4) size = 0;
1988 return size;
1989 }
1990 return 0;
1991 }
1992
1993 // Limits on vector size (number of elements) loaded into vector.
1994 int Matcher::max_vector_size(const BasicType bt) {
1995 return vector_width_in_bytes(bt) / type2aelembytes(bt);
1996 }
1997
1998 int Matcher::min_vector_size(const BasicType bt) {
1999 int size;
2000 switch(bt) {
2001 case T_BOOLEAN:
2002 // Load/store a vector mask with only 2 elements for vector types
2003 // such as "2I/2F/2L/2D".
2004 size = 2;
2005 break;
2006 case T_BYTE:
2007 // Generate a "4B" vector, to support vector cast between "8B/16B"
2008 // and "4S/4I/4L/4F/4D".
2009 size = 4;
2010 break;
2011 case T_SHORT:
2012 // Generate a "2S" vector, to support vector cast between "4S/8S"
2013 // and "2I/2L/2F/2D".
2014 size = 2;
2015 break;
2016 default:
2017 // Limit the min vector length to 64-bit.
2018 size = 8 / type2aelembytes(bt);
2019 // The number of elements in a vector should be at least 2.
2020 size = MAX2(size, 2);
2021 }
2022
2023 int max_size = max_vector_size(bt);
2024 return MIN2(size, max_size);
2025 }
2026
2027 int Matcher::max_vector_size_auto_vectorization(const BasicType bt) {
2028 return Matcher::max_vector_size(bt);
2029 }
2030
2031 // Vector ideal reg.
2032 uint Matcher::vector_ideal_reg(int len) {
2033 assert(MaxVectorSize >= len, "");
2034 if (UseRVV) {
2035 return Op_VecA;
2036 }
2037
2038 ShouldNotReachHere();
2039 return 0;
2040 }
2041
2042 int Matcher::scalable_vector_reg_size(const BasicType bt) {
2043 return Matcher::max_vector_size(bt);
2044 }
2045
2046 MachOper* Matcher::pd_specialize_generic_vector_operand(MachOper* original_opnd, uint ideal_reg, bool is_temp) {
2047 ShouldNotReachHere(); // generic vector operands not supported
2048 return nullptr;
2049 }
2050
2051 bool Matcher::is_reg2reg_move(MachNode* m) {
2052 ShouldNotReachHere(); // generic vector operands not supported
2053 return false;
2054 }
2055
2056 bool Matcher::is_generic_vector(MachOper* opnd) {
2057 ShouldNotReachHere(); // generic vector operands not supported
2058 return false;
2059 }
2060
2061 // Return whether or not this register is ever used as an argument.
2062 // This function is used on startup to build the trampoline stubs in
2063 // generateOptoStub. Registers not mentioned will be killed by the VM
2064 // call in the trampoline, and arguments in those registers not be
2065 // available to the callee.
2066 bool Matcher::can_be_java_arg(int reg)
2067 {
2068 return
2069 reg == R10_num || reg == R10_H_num ||
2070 reg == R11_num || reg == R11_H_num ||
2071 reg == R12_num || reg == R12_H_num ||
2072 reg == R13_num || reg == R13_H_num ||
2073 reg == R14_num || reg == R14_H_num ||
2074 reg == R15_num || reg == R15_H_num ||
2075 reg == R16_num || reg == R16_H_num ||
2076 reg == R17_num || reg == R17_H_num ||
2077 reg == F10_num || reg == F10_H_num ||
2078 reg == F11_num || reg == F11_H_num ||
2079 reg == F12_num || reg == F12_H_num ||
2080 reg == F13_num || reg == F13_H_num ||
2081 reg == F14_num || reg == F14_H_num ||
2082 reg == F15_num || reg == F15_H_num ||
2083 reg == F16_num || reg == F16_H_num ||
2084 reg == F17_num || reg == F17_H_num;
2085 }
2086
2087 bool Matcher::is_spillable_arg(int reg)
2088 {
2089 return can_be_java_arg(reg);
2090 }
2091
2092 uint Matcher::int_pressure_limit()
2093 {
2094 // A derived pointer is live at CallNode and then is flagged by RA
2095 // as a spilled LRG. Spilling heuristics(Spill-USE) explicitly skip
2096 // derived pointers and lastly fail to spill after reaching maximum
2097 // number of iterations. Lowering the default pressure threshold to
2098 // (_NO_SPECIAL_REG32_mask.size() minus 1) forces CallNode to become
2099 // a high register pressure area of the code so that split_DEF can
2100 // generate DefinitionSpillCopy for the derived pointer.
2101 uint default_int_pressure_threshold = _NO_SPECIAL_REG32_mask.size() - 1;
2102 if (!PreserveFramePointer) {
2103 // When PreserveFramePointer is off, frame pointer is allocatable,
2104 // but different from other SOC registers, it is excluded from
2105 // fatproj's mask because its save type is No-Save. Decrease 1 to
2106 // ensure high pressure at fatproj when PreserveFramePointer is off.
2107 // See check_pressure_at_fatproj().
2108 default_int_pressure_threshold--;
2109 }
2110 return (INTPRESSURE == -1) ? default_int_pressure_threshold : INTPRESSURE;
2111 }
2112
2113 uint Matcher::float_pressure_limit()
2114 {
2115 // _FLOAT_REG_mask is generated by adlc from the float_reg register class.
2116 return (FLOATPRESSURE == -1) ? _FLOAT_REG_mask.size() : FLOATPRESSURE;
2117 }
2118
2119 bool Matcher::use_asm_for_ldiv_by_con(jlong divisor) {
2120 return false;
2121 }
2122
2123 const RegMask& Matcher::divI_proj_mask() {
2124 ShouldNotReachHere();
2125 return RegMask::EMPTY;
2126 }
2127
2128 // Register for MODI projection of divmodI.
2129 const RegMask& Matcher::modI_proj_mask() {
2130 ShouldNotReachHere();
2131 return RegMask::EMPTY;
2132 }
2133
2134 // Register for DIVL projection of divmodL.
2135 const RegMask& Matcher::divL_proj_mask() {
2136 ShouldNotReachHere();
2137 return RegMask::EMPTY;
2138 }
2139
2140 // Register for MODL projection of divmodL.
2141 const RegMask& Matcher::modL_proj_mask() {
2142 ShouldNotReachHere();
2143 return RegMask::EMPTY;
2144 }
2145
2146 bool size_fits_all_mem_uses(AddPNode* addp, int shift) {
2147 assert_cond(addp != nullptr);
2148 for (DUIterator_Fast imax, i = addp->fast_outs(imax); i < imax; i++) {
2149 Node* u = addp->fast_out(i);
2150 if (u != nullptr && u->is_Mem()) {
2151 int opsize = u->as_Mem()->memory_size();
2152 assert(opsize > 0, "unexpected memory operand size");
2153 if (u->as_Mem()->memory_size() != (1 << shift)) {
2154 return false;
2155 }
2156 }
2157 }
2158 return true;
2159 }
2160
2161 // Binary src (Replicate scalar/immediate)
2162 static bool is_vector_scalar_bitwise_pattern(Node* n, Node* m) {
2163 if (n == nullptr || m == nullptr) {
2164 return false;
2165 }
2166
2167 if (m->Opcode() != Op_Replicate) {
2168 return false;
2169 }
2170
2171 switch (n->Opcode()) {
2172 case Op_AndV:
2173 case Op_OrV:
2174 case Op_XorV:
2175 case Op_AddVB:
2176 case Op_AddVS:
2177 case Op_AddVI:
2178 case Op_AddVL:
2179 case Op_SubVB:
2180 case Op_SubVS:
2181 case Op_SubVI:
2182 case Op_SubVL:
2183 case Op_MulVB:
2184 case Op_MulVS:
2185 case Op_MulVI:
2186 case Op_MulVL: {
2187 return true;
2188 }
2189 default:
2190 return false;
2191 }
2192 }
2193
2194 // (XorV src (Replicate m1))
2195 // (XorVMask src (MaskAll m1))
2196 static bool is_vector_bitwise_not_pattern(Node* n, Node* m) {
2197 if (n != nullptr && m != nullptr) {
2198 return (n->Opcode() == Op_XorV || n->Opcode() == Op_XorVMask) &&
2199 VectorNode::is_all_ones_vector(m);
2200 }
2201 return false;
2202 }
2203
2204 // Should the Matcher clone input 'm' of node 'n'?
2205 bool Matcher::pd_clone_node(Node* n, Node* m, Matcher::MStack& mstack) {
2206 assert_cond(m != nullptr);
2207 if (is_vshift_con_pattern(n, m) || // ShiftV src (ShiftCntV con)
2208 is_vector_bitwise_not_pattern(n, m) ||
2209 is_vector_scalar_bitwise_pattern(n, m) ||
2210 is_encode_and_store_pattern(n, m)) {
2211 mstack.push(m, Visit);
2212 return true;
2213 }
2214 return false;
2215 }
2216
2217 // Should the Matcher clone shifts on addressing modes, expecting them
2218 // to be subsumed into complex addressing expressions or compute them
2219 // into registers?
2220 bool Matcher::pd_clone_address_expressions(AddPNode* m, Matcher::MStack& mstack, VectorSet& address_visited) {
2221 return clone_base_plus_offset_address(m, mstack, address_visited);
2222 }
2223
2224 %}
2225
2226
2227
2228 //----------ENCODING BLOCK-----------------------------------------------------
2229 // This block specifies the encoding classes used by the compiler to
2230 // output byte streams. Encoding classes are parameterized macros
2231 // used by Machine Instruction Nodes in order to generate the bit
2232 // encoding of the instruction. Operands specify their base encoding
2233 // interface with the interface keyword. There are currently
2234 // supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, &
2235 // COND_INTER. REG_INTER causes an operand to generate a function
2236 // which returns its register number when queried. CONST_INTER causes
2237 // an operand to generate a function which returns the value of the
2238 // constant when queried. MEMORY_INTER causes an operand to generate
2239 // four functions which return the Base Register, the Index Register,
2240 // the Scale Value, and the Offset Value of the operand when queried.
2241 // COND_INTER causes an operand to generate six functions which return
2242 // the encoding code (ie - encoding bits for the instruction)
2243 // associated with each basic boolean condition for a conditional
2244 // instruction.
2245 //
2246 // Instructions specify two basic values for encoding. Again, a
2247 // function is available to check if the constant displacement is an
2248 // oop. They use the ins_encode keyword to specify their encoding
2249 // classes (which must be a sequence of enc_class names, and their
2250 // parameters, specified in the encoding block), and they use the
2251 // opcode keyword to specify, in order, their primary, secondary, and
2252 // tertiary opcode. Only the opcode sections which a particular
2253 // instruction needs for encoding need to be specified.
2254 encode %{
2255 // BEGIN Non-volatile memory access
2256
2257 enc_class riscv_enc_mov_imm(iRegIorL dst, immIorL src) %{
2258 int64_t con = (int64_t)$src$$constant;
2259 Register dst_reg = as_Register($dst$$reg);
2260 __ mv(dst_reg, con);
2261 %}
2262
2263 enc_class riscv_enc_mov_p(iRegP dst, immP src) %{
2264 Register dst_reg = as_Register($dst$$reg);
2265 address con = (address)$src$$constant;
2266 if (con == nullptr || con == (address)1) {
2267 ShouldNotReachHere();
2268 } else {
2269 relocInfo::relocType rtype = $src->constant_reloc();
2270 if (rtype == relocInfo::oop_type) {
2271 __ movoop(dst_reg, (jobject)con);
2272 } else if (rtype == relocInfo::metadata_type) {
2273 __ mov_metadata(dst_reg, (Metadata*)con);
2274 } else {
2275 assert(rtype == relocInfo::none, "unexpected reloc type");
2276 __ mv(dst_reg, $src$$constant);
2277 }
2278 }
2279 %}
2280
2281 enc_class riscv_enc_mov_p1(iRegP dst) %{
2282 Register dst_reg = as_Register($dst$$reg);
2283 __ mv(dst_reg, 1);
2284 %}
2285
2286 enc_class riscv_enc_mov_n(iRegN dst, immN src) %{
2287 Register dst_reg = as_Register($dst$$reg);
2288 address con = (address)$src$$constant;
2289 if (con == nullptr) {
2290 ShouldNotReachHere();
2291 } else {
2292 relocInfo::relocType rtype = $src->constant_reloc();
2293 assert(rtype == relocInfo::oop_type, "unexpected reloc type");
2294 __ set_narrow_oop(dst_reg, (jobject)con);
2295 }
2296 %}
2297
2298 enc_class riscv_enc_mov_zero(iRegNorP dst) %{
2299 Register dst_reg = as_Register($dst$$reg);
2300 __ mv(dst_reg, zr);
2301 %}
2302
2303 enc_class riscv_enc_mov_nk(iRegN dst, immNKlass src) %{
2304 Register dst_reg = as_Register($dst$$reg);
2305 address con = (address)$src$$constant;
2306 if (con == nullptr) {
2307 ShouldNotReachHere();
2308 } else {
2309 relocInfo::relocType rtype = $src->constant_reloc();
2310 assert(rtype == relocInfo::metadata_type, "unexpected reloc type");
2311 __ set_narrow_klass(dst_reg, (Klass *)con);
2312 }
2313 %}
2314
2315 // compare and branch instruction encodings
2316
2317 enc_class riscv_enc_j(label lbl) %{
2318 Label* L = $lbl$$label;
2319 __ j(*L);
2320 %}
2321
2322 enc_class riscv_enc_far_cmpULtGe_imm0_branch(cmpOpULtGe cmp, iRegIorL op1, label lbl) %{
2323 Label* L = $lbl$$label;
2324 switch ($cmp$$cmpcode) {
2325 case(BoolTest::ge):
2326 __ j(*L);
2327 break;
2328 case(BoolTest::lt):
2329 break;
2330 default:
2331 Unimplemented();
2332 }
2333 %}
2334
2335 // call instruction encodings
2336
2337 enc_class riscv_enc_partial_subtype_check(iRegP sub, iRegP super, iRegP temp, iRegP result) %{
2338 Register sub_reg = as_Register($sub$$reg);
2339 Register super_reg = as_Register($super$$reg);
2340 Register temp_reg = as_Register($temp$$reg);
2341 Register result_reg = as_Register($result$$reg);
2342 Register cr_reg = t1;
2343
2344 Label miss;
2345 Label done;
2346 __ check_klass_subtype_slow_path(sub_reg, super_reg, temp_reg, result_reg,
2347 nullptr, &miss, /*set_cond_codes*/ true);
2348 if ($primary) {
2349 __ mv(result_reg, zr);
2350 } else {
2351 __ mv(cr_reg, zr);
2352 __ j(done);
2353 }
2354
2355 __ bind(miss);
2356 if (!$primary) {
2357 __ mv(cr_reg, 1);
2358 }
2359
2360 __ bind(done);
2361 %}
2362
2363 enc_class riscv_enc_java_static_call(method meth) %{
2364 Assembler::IncompressibleScope scope(masm); // Fixed length: see ret_addr_offset
2365
2366 address addr = (address)$meth$$method;
2367 address call = nullptr;
2368 assert_cond(addr != nullptr);
2369 if (!_method) {
2370 // A call to a runtime wrapper, e.g. new, new_typeArray_Java, uncommon_trap.
2371 call = __ reloc_call(Address(addr, relocInfo::runtime_call_type));
2372 if (call == nullptr) {
2373 ciEnv::current()->record_failure("CodeCache is full");
2374 return;
2375 }
2376 } else if (_method->intrinsic_id() == vmIntrinsicID::_ensureMaterializedForStackWalk) {
2377 // The NOP here is purely to ensure that eliding a call to
2378 // JVM_EnsureMaterializedForStackWalk doesn't change the code size.
2379 __ nop();
2380 __ nop();
2381 __ nop();
2382 __ block_comment("call JVM_EnsureMaterializedForStackWalk (elided)");
2383 } else {
2384 int method_index = resolved_method_index(masm);
2385 RelocationHolder rspec = _optimized_virtual ? opt_virtual_call_Relocation::spec(method_index)
2386 : static_call_Relocation::spec(method_index);
2387 call = __ reloc_call(Address(addr, rspec));
2388 if (call == nullptr) {
2389 ciEnv::current()->record_failure("CodeCache is full");
2390 return;
2391 }
2392
2393 if (CodeBuffer::supports_shared_stubs() && _method->can_be_statically_bound()) {
2394 // Calls of the same statically bound method can share
2395 // a stub to the interpreter.
2396 __ code()->shared_stub_to_interp_for(_method, call - (__ begin()));
2397 } else {
2398 // Emit stub for static call
2399 address stub = CompiledDirectCall::emit_to_interp_stub(masm, call);
2400 if (stub == nullptr) {
2401 ciEnv::current()->record_failure("CodeCache is full");
2402 return;
2403 }
2404 }
2405 }
2406
2407 __ post_call_nop();
2408 %}
2409
2410 enc_class riscv_enc_java_dynamic_call(method meth) %{
2411 Assembler::IncompressibleScope scope(masm); // Fixed length: see ret_addr_offset
2412 int method_index = resolved_method_index(masm);
2413 address call = __ ic_call((address)$meth$$method, method_index);
2414 if (call == nullptr) {
2415 ciEnv::current()->record_failure("CodeCache is full");
2416 return;
2417 }
2418
2419 __ post_call_nop();
2420 %}
2421
2422 enc_class riscv_enc_call_epilog() %{
2423 if (VerifyStackAtCalls) {
2424 // Check that stack depth is unchanged: find majik cookie on stack
2425 int framesize = ra_->reg2offset_unchecked(OptoReg::add(ra_->_matcher._old_SP, -3 * VMRegImpl::slots_per_word));
2426 Label stack_ok;
2427 __ ld(t1, Address(sp, framesize));
2428 __ mv(t2, MAJIK_DWORD);
2429 __ beq(t2, t1, stack_ok);
2430 __ stop("MAJIK_DWORD not found");
2431 __ bind(stack_ok);
2432 }
2433 %}
2434
2435 enc_class riscv_enc_java_to_runtime(method meth) %{
2436 Assembler::IncompressibleScope scope(masm); // Fixed length: see ret_addr_offset
2437
2438 // Some calls to generated routines (arraycopy code) are scheduled by C2
2439 // as runtime calls. if so we can call them using a far call (they will be
2440 // in the code cache, thus in a reachable segment) otherwise we have to use
2441 // a movptr+jalr pair which loads the absolute address into a register.
2442 address entry = (address)$meth$$method;
2443 if (CodeCache::contains(entry)) {
2444 __ far_call(Address(entry, relocInfo::runtime_call_type));
2445 __ post_call_nop();
2446 } else {
2447 Label retaddr;
2448 // Make the anchor frame walkable
2449 __ la(t0, retaddr);
2450 __ sd(t0, Address(xthread, JavaThread::last_Java_pc_offset()));
2451 int32_t offset = 0;
2452 // No relocation needed
2453 __ movptr(t1, entry, offset, t0); // lui + lui + slli + add
2454 __ jalr(t1, offset);
2455 __ bind(retaddr);
2456 __ post_call_nop();
2457 }
2458 %}
2459
2460 enc_class riscv_enc_tail_call(iRegP jump_target) %{
2461 Register target_reg = as_Register($jump_target$$reg);
2462 __ jr(target_reg);
2463 %}
2464
2465 enc_class riscv_enc_tail_jmp(iRegP jump_target) %{
2466 Register target_reg = as_Register($jump_target$$reg);
2467 // exception oop should be in x10
2468 // ret addr has been popped into ra
2469 // callee expects it in x13
2470 __ mv(x13, ra);
2471 __ jr(target_reg);
2472 %}
2473
2474 enc_class riscv_enc_rethrow() %{
2475 __ far_jump(RuntimeAddress(OptoRuntime::rethrow_stub()));
2476 %}
2477
2478 enc_class riscv_enc_ret() %{
2479 __ ret();
2480 %}
2481
2482 %}
2483
2484 //----------FRAME--------------------------------------------------------------
2485 // Definition of frame structure and management information.
2486 //
2487 // S T A C K L A Y O U T Allocators stack-slot number
2488 // | (to get allocators register number
2489 // G Owned by | | v add OptoReg::stack0())
2490 // r CALLER | |
2491 // o | +--------+ pad to even-align allocators stack-slot
2492 // w V | pad0 | numbers; owned by CALLER
2493 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
2494 // h ^ | in | 5
2495 // | | args | 4 Holes in incoming args owned by SELF
2496 // | | | | 3
2497 // | | +--------+
2498 // V | | old out| Empty on Intel, window on Sparc
2499 // | old |preserve| Must be even aligned.
2500 // | SP-+--------+----> Matcher::_old_SP, even aligned
2501 // | | in | 3 area for Intel ret address
2502 // Owned by |preserve| Empty on Sparc.
2503 // SELF +--------+
2504 // | | pad2 | 2 pad to align old SP
2505 // | +--------+ 1
2506 // | | locks | 0
2507 // | +--------+----> OptoReg::stack0(), even aligned
2508 // | | pad1 | 11 pad to align new SP
2509 // | +--------+
2510 // | | | 10
2511 // | | spills | 9 spills
2512 // V | | 8 (pad0 slot for callee)
2513 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
2514 // ^ | out | 7
2515 // | | args | 6 Holes in outgoing args owned by CALLEE
2516 // Owned by +--------+
2517 // CALLEE | new out| 6 Empty on Intel, window on Sparc
2518 // | new |preserve| Must be even-aligned.
2519 // | SP-+--------+----> Matcher::_new_SP, even aligned
2520 // | | |
2521 //
2522 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
2523 // known from SELF's arguments and the Java calling convention.
2524 // Region 6-7 is determined per call site.
2525 // Note 2: If the calling convention leaves holes in the incoming argument
2526 // area, those holes are owned by SELF. Holes in the outgoing area
2527 // are owned by the CALLEE. Holes should not be necessary in the
2528 // incoming area, as the Java calling convention is completely under
2529 // the control of the AD file. Doubles can be sorted and packed to
2530 // avoid holes. Holes in the outgoing arguments may be necessary for
2531 // varargs C calling conventions.
2532 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
2533 // even aligned with pad0 as needed.
2534 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
2535 // (the latter is true on Intel but is it false on RISCV?)
2536 // region 6-11 is even aligned; it may be padded out more so that
2537 // the region from SP to FP meets the minimum stack alignment.
2538 // Note 4: For I2C adapters, the incoming FP may not meet the minimum stack
2539 // alignment. Region 11, pad1, may be dynamically extended so that
2540 // SP meets the minimum alignment.
2541
2542 frame %{
2543 // These three registers define part of the calling convention
2544 // between compiled code and the interpreter.
2545
2546 // Inline Cache Register or methodOop for I2C.
2547 inline_cache_reg(R31);
2548
2549 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
2550 cisc_spilling_operand_name(indOffset);
2551
2552 // Number of stack slots consumed by locking an object
2553 // generate Compile::sync_stack_slots
2554 // VMRegImpl::slots_per_word = wordSize / stack_slot_size = 8 / 4 = 2
2555 sync_stack_slots(1 * VMRegImpl::slots_per_word);
2556
2557 // Compiled code's Frame Pointer
2558 frame_pointer(R2);
2559
2560 // Interpreter stores its frame pointer in a register which is
2561 // stored to the stack by I2CAdaptors.
2562 // I2CAdaptors convert from interpreted java to compiled java.
2563 interpreter_frame_pointer(R8);
2564
2565 // Stack alignment requirement
2566 stack_alignment(StackAlignmentInBytes); // Alignment size in bytes (128-bit -> 16 bytes)
2567
2568 // Number of outgoing stack slots killed above the out_preserve_stack_slots
2569 // for calls to C. Supports the var-args backing area for register parms.
2570 varargs_C_out_slots_killed(frame::arg_reg_save_area_bytes / BytesPerInt);
2571
2572 // The after-PROLOG location of the return address. Location of
2573 // return address specifies a type (REG or STACK) and a number
2574 // representing the register number (i.e. - use a register name) or
2575 // stack slot.
2576 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
2577 // Otherwise, it is above the locks and verification slot and alignment word
2578 // TODO this may well be correct but need to check why that - 2 is there
2579 // ppc port uses 0 but we definitely need to allow for fixed_slots
2580 // which folds in the space used for monitors
2581 return_addr(STACK - 2 +
2582 align_up((Compile::current()->in_preserve_stack_slots() +
2583 Compile::current()->fixed_slots()),
2584 stack_alignment_in_slots()));
2585
2586 // Location of compiled Java return values. Same as C for now.
2587 return_value
2588 %{
2589 assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL,
2590 "only return normal values");
2591
2592 static const int lo[Op_RegL + 1] = { // enum name
2593 0, // Op_Node
2594 0, // Op_Set
2595 R10_num, // Op_RegN
2596 R10_num, // Op_RegI
2597 R10_num, // Op_RegP
2598 F10_num, // Op_RegF
2599 F10_num, // Op_RegD
2600 R10_num // Op_RegL
2601 };
2602
2603 static const int hi[Op_RegL + 1] = { // enum name
2604 0, // Op_Node
2605 0, // Op_Set
2606 OptoReg::Bad, // Op_RegN
2607 OptoReg::Bad, // Op_RegI
2608 R10_H_num, // Op_RegP
2609 OptoReg::Bad, // Op_RegF
2610 F10_H_num, // Op_RegD
2611 R10_H_num // Op_RegL
2612 };
2613
2614 return OptoRegPair(hi[ideal_reg], lo[ideal_reg]);
2615 %}
2616 %}
2617
2618 //----------ATTRIBUTES---------------------------------------------------------
2619 //----------Operand Attributes-------------------------------------------------
2620 op_attrib op_cost(1); // Required cost attribute
2621
2622 //----------Instruction Attributes---------------------------------------------
2623 ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute
2624 ins_attrib ins_size(32); // Required size attribute (in bits)
2625 ins_attrib ins_short_branch(0); // Required flag: is this instruction
2626 // a non-matching short branch variant
2627 // of some long branch?
2628 ins_attrib ins_alignment(4); // Required alignment attribute (must
2629 // be a power of 2) specifies the
2630 // alignment that some part of the
2631 // instruction (not necessarily the
2632 // start) requires. If > 1, a
2633 // compute_padding() function must be
2634 // provided for the instruction
2635
2636 // Whether this node is expanded during code emission into a sequence of
2637 // instructions and the first instruction can perform an implicit null check.
2638 ins_attrib ins_is_late_expanded_null_check_candidate(false);
2639
2640 //----------OPERANDS-----------------------------------------------------------
2641 // Operand definitions must precede instruction definitions for correct parsing
2642 // in the ADLC because operands constitute user defined types which are used in
2643 // instruction definitions.
2644
2645 //----------Simple Operands----------------------------------------------------
2646
2647 // Integer operands 32 bit
2648 // 32 bit immediate
2649 operand immI()
2650 %{
2651 match(ConI);
2652
2653 op_cost(0);
2654 format %{ %}
2655 interface(CONST_INTER);
2656 %}
2657
2658 // 32 bit zero
2659 operand immI0()
2660 %{
2661 predicate(n->get_int() == 0);
2662 match(ConI);
2663
2664 op_cost(0);
2665 format %{ %}
2666 interface(CONST_INTER);
2667 %}
2668
2669 // 32 bit unit increment
2670 operand immI_1()
2671 %{
2672 predicate(n->get_int() == 1);
2673 match(ConI);
2674
2675 op_cost(0);
2676 format %{ %}
2677 interface(CONST_INTER);
2678 %}
2679
2680 // 32 bit unit decrement
2681 operand immI_M1()
2682 %{
2683 predicate(n->get_int() == -1);
2684 match(ConI);
2685
2686 op_cost(0);
2687 format %{ %}
2688 interface(CONST_INTER);
2689 %}
2690
2691 // Unsigned Integer Immediate: 6-bit int, greater than 32
2692 operand uimmI6_ge32() %{
2693 predicate(((unsigned int)(n->get_int()) < 64) && (n->get_int() >= 32));
2694 match(ConI);
2695 op_cost(0);
2696 format %{ %}
2697 interface(CONST_INTER);
2698 %}
2699
2700 operand immI_le_4()
2701 %{
2702 predicate(n->get_int() <= 4);
2703 match(ConI);
2704
2705 op_cost(0);
2706 format %{ %}
2707 interface(CONST_INTER);
2708 %}
2709
2710 operand immI_16()
2711 %{
2712 predicate(n->get_int() == 16);
2713 match(ConI);
2714 op_cost(0);
2715 format %{ %}
2716 interface(CONST_INTER);
2717 %}
2718
2719 operand immI_24()
2720 %{
2721 predicate(n->get_int() == 24);
2722 match(ConI);
2723 op_cost(0);
2724 format %{ %}
2725 interface(CONST_INTER);
2726 %}
2727
2728 operand immI_31()
2729 %{
2730 predicate(n->get_int() == 31);
2731 match(ConI);
2732
2733 op_cost(0);
2734 format %{ %}
2735 interface(CONST_INTER);
2736 %}
2737
2738 operand immI_63()
2739 %{
2740 predicate(n->get_int() == 63);
2741 match(ConI);
2742
2743 op_cost(0);
2744 format %{ %}
2745 interface(CONST_INTER);
2746 %}
2747
2748 // 32 bit integer valid for add immediate
2749 operand immIAdd()
2750 %{
2751 predicate(Assembler::is_simm12((int64_t)n->get_int()));
2752 match(ConI);
2753 op_cost(0);
2754 format %{ %}
2755 interface(CONST_INTER);
2756 %}
2757
2758 // 32 bit integer valid for sub immediate
2759 operand immISub()
2760 %{
2761 predicate(Assembler::is_simm12(-(int64_t)n->get_int()));
2762 match(ConI);
2763 op_cost(0);
2764 format %{ %}
2765 interface(CONST_INTER);
2766 %}
2767
2768 // 5 bit signed value.
2769 operand immI5()
2770 %{
2771 predicate(n->get_int() <= 15 && n->get_int() >= -16);
2772 match(ConI);
2773
2774 op_cost(0);
2775 format %{ %}
2776 interface(CONST_INTER);
2777 %}
2778
2779 // 5 bit signed value (simm5)
2780 operand immL5()
2781 %{
2782 predicate(n->get_long() <= 15 && n->get_long() >= -16);
2783 match(ConL);
2784
2785 op_cost(0);
2786 format %{ %}
2787 interface(CONST_INTER);
2788 %}
2789
2790 // Integer operands 64 bit
2791 // 64 bit immediate
2792 operand immL()
2793 %{
2794 match(ConL);
2795
2796 op_cost(0);
2797 format %{ %}
2798 interface(CONST_INTER);
2799 %}
2800
2801 // 64 bit zero
2802 operand immL0()
2803 %{
2804 predicate(n->get_long() == 0);
2805 match(ConL);
2806
2807 op_cost(0);
2808 format %{ %}
2809 interface(CONST_INTER);
2810 %}
2811
2812 // Pointer operands
2813 // Pointer Immediate
2814 operand immP()
2815 %{
2816 match(ConP);
2817
2818 op_cost(0);
2819 format %{ %}
2820 interface(CONST_INTER);
2821 %}
2822
2823 // Null Pointer Immediate
2824 operand immP0()
2825 %{
2826 predicate(n->get_ptr() == 0);
2827 match(ConP);
2828
2829 op_cost(0);
2830 format %{ %}
2831 interface(CONST_INTER);
2832 %}
2833
2834 // Pointer Immediate One
2835 // this is used in object initialization (initial object header)
2836 operand immP_1()
2837 %{
2838 predicate(n->get_ptr() == 1);
2839 match(ConP);
2840
2841 op_cost(0);
2842 format %{ %}
2843 interface(CONST_INTER);
2844 %}
2845
2846 // Int Immediate: low 16-bit mask
2847 operand immI_16bits()
2848 %{
2849 predicate(n->get_int() == 0xFFFF);
2850 match(ConI);
2851 op_cost(0);
2852 format %{ %}
2853 interface(CONST_INTER);
2854 %}
2855
2856 operand immIpowerOf2() %{
2857 predicate(is_power_of_2((juint)(n->get_int())));
2858 match(ConI);
2859 op_cost(0);
2860 format %{ %}
2861 interface(CONST_INTER);
2862 %}
2863
2864 // Long Immediate: low 32-bit mask
2865 operand immL_32bits()
2866 %{
2867 predicate(n->get_long() == 0xFFFFFFFFL);
2868 match(ConL);
2869 op_cost(0);
2870 format %{ %}
2871 interface(CONST_INTER);
2872 %}
2873
2874 // 64 bit unit decrement
2875 operand immL_M1()
2876 %{
2877 predicate(n->get_long() == -1);
2878 match(ConL);
2879
2880 op_cost(0);
2881 format %{ %}
2882 interface(CONST_INTER);
2883 %}
2884
2885
2886 // 64 bit integer valid for add immediate
2887 operand immLAdd()
2888 %{
2889 predicate(Assembler::is_simm12(n->get_long()));
2890 match(ConL);
2891 op_cost(0);
2892 format %{ %}
2893 interface(CONST_INTER);
2894 %}
2895
2896 // 64 bit integer valid for sub immediate
2897 operand immLSub()
2898 %{
2899 predicate(Assembler::is_simm12(-(n->get_long())));
2900 match(ConL);
2901 op_cost(0);
2902 format %{ %}
2903 interface(CONST_INTER);
2904 %}
2905
2906 // Narrow pointer operands
2907 // Narrow Pointer Immediate
2908 operand immN()
2909 %{
2910 match(ConN);
2911
2912 op_cost(0);
2913 format %{ %}
2914 interface(CONST_INTER);
2915 %}
2916
2917 // Narrow Null Pointer Immediate
2918 operand immN0()
2919 %{
2920 predicate(n->get_narrowcon() == 0);
2921 match(ConN);
2922
2923 op_cost(0);
2924 format %{ %}
2925 interface(CONST_INTER);
2926 %}
2927
2928 operand immNKlass()
2929 %{
2930 match(ConNKlass);
2931
2932 op_cost(0);
2933 format %{ %}
2934 interface(CONST_INTER);
2935 %}
2936
2937 // Float and Double operands
2938 // Double Immediate
2939 operand immD()
2940 %{
2941 match(ConD);
2942 op_cost(0);
2943 format %{ %}
2944 interface(CONST_INTER);
2945 %}
2946
2947 // Double Immediate: +0.0d
2948 operand immD0()
2949 %{
2950 predicate(jlong_cast(n->getd()) == 0);
2951 match(ConD);
2952
2953 op_cost(0);
2954 format %{ %}
2955 interface(CONST_INTER);
2956 %}
2957
2958 // Float Immediate
2959 operand immF()
2960 %{
2961 match(ConF);
2962 op_cost(0);
2963 format %{ %}
2964 interface(CONST_INTER);
2965 %}
2966
2967 // Float Immediate: +0.0f.
2968 operand immF0()
2969 %{
2970 predicate(jint_cast(n->getf()) == 0);
2971 match(ConF);
2972
2973 op_cost(0);
2974 format %{ %}
2975 interface(CONST_INTER);
2976 %}
2977
2978 // Half Float Immediate
2979 operand immH()
2980 %{
2981 match(ConH);
2982
2983 op_cost(0);
2984 format %{ %}
2985 interface(CONST_INTER);
2986 %}
2987
2988 // Half Float Immediate: +0.0f.
2989 operand immH0()
2990 %{
2991 predicate(jint_cast(n->geth()) == 0);
2992 match(ConH);
2993
2994 op_cost(0);
2995 format %{ %}
2996 interface(CONST_INTER);
2997 %}
2998
2999 operand immIOffset()
3000 %{
3001 predicate(Assembler::is_simm12(n->get_int()));
3002 match(ConI);
3003 op_cost(0);
3004 format %{ %}
3005 interface(CONST_INTER);
3006 %}
3007
3008 operand immLOffset()
3009 %{
3010 predicate(Assembler::is_simm12(n->get_long()));
3011 match(ConL);
3012 op_cost(0);
3013 format %{ %}
3014 interface(CONST_INTER);
3015 %}
3016
3017 // Scale values
3018 operand immIScale()
3019 %{
3020 predicate(1 <= n->get_int() && (n->get_int() <= 3));
3021 match(ConI);
3022
3023 op_cost(0);
3024 format %{ %}
3025 interface(CONST_INTER);
3026 %}
3027
3028 // Integer 32 bit Register Operands
3029 operand iRegI()
3030 %{
3031 constraint(ALLOC_IN_RC(any_reg32));
3032 match(RegI);
3033 match(iRegINoSp);
3034 op_cost(0);
3035 format %{ %}
3036 interface(REG_INTER);
3037 %}
3038
3039 // Integer 32 bit Register not Special
3040 operand iRegINoSp()
3041 %{
3042 constraint(ALLOC_IN_RC(no_special_reg32));
3043 match(RegI);
3044 op_cost(0);
3045 format %{ %}
3046 interface(REG_INTER);
3047 %}
3048
3049 // Register R10 only
3050 operand iRegI_R10()
3051 %{
3052 constraint(ALLOC_IN_RC(int_r10_reg));
3053 match(RegI);
3054 match(iRegINoSp);
3055 op_cost(0);
3056 format %{ %}
3057 interface(REG_INTER);
3058 %}
3059
3060 // Register R12 only
3061 operand iRegI_R12()
3062 %{
3063 constraint(ALLOC_IN_RC(int_r12_reg));
3064 match(RegI);
3065 match(iRegINoSp);
3066 op_cost(0);
3067 format %{ %}
3068 interface(REG_INTER);
3069 %}
3070
3071 // Register R13 only
3072 operand iRegI_R13()
3073 %{
3074 constraint(ALLOC_IN_RC(int_r13_reg));
3075 match(RegI);
3076 match(iRegINoSp);
3077 op_cost(0);
3078 format %{ %}
3079 interface(REG_INTER);
3080 %}
3081
3082 // Register R14 only
3083 operand iRegI_R14()
3084 %{
3085 constraint(ALLOC_IN_RC(int_r14_reg));
3086 match(RegI);
3087 match(iRegINoSp);
3088 op_cost(0);
3089 format %{ %}
3090 interface(REG_INTER);
3091 %}
3092
3093 // Integer 64 bit Register Operands
3094 operand iRegL()
3095 %{
3096 constraint(ALLOC_IN_RC(any_reg));
3097 match(RegL);
3098 match(iRegLNoSp);
3099 op_cost(0);
3100 format %{ %}
3101 interface(REG_INTER);
3102 %}
3103
3104 // Integer 64 bit Register not Special
3105 operand iRegLNoSp()
3106 %{
3107 constraint(ALLOC_IN_RC(no_special_reg));
3108 match(RegL);
3109 match(iRegL_R10);
3110 format %{ %}
3111 interface(REG_INTER);
3112 %}
3113
3114 // Long 64 bit Register R29 only
3115 operand iRegL_R29()
3116 %{
3117 constraint(ALLOC_IN_RC(r29_reg));
3118 match(RegL);
3119 match(iRegLNoSp);
3120 op_cost(0);
3121 format %{ %}
3122 interface(REG_INTER);
3123 %}
3124
3125 // Long 64 bit Register R30 only
3126 operand iRegL_R30()
3127 %{
3128 constraint(ALLOC_IN_RC(r30_reg));
3129 match(RegL);
3130 match(iRegLNoSp);
3131 op_cost(0);
3132 format %{ %}
3133 interface(REG_INTER);
3134 %}
3135
3136 // Pointer Register Operands
3137 // Pointer Register
3138 operand iRegP()
3139 %{
3140 constraint(ALLOC_IN_RC(ptr_reg));
3141 match(RegP);
3142 match(iRegPNoSp);
3143 match(iRegP_R10);
3144 match(iRegP_R15);
3145 match(javaThread_RegP);
3146 op_cost(0);
3147 format %{ %}
3148 interface(REG_INTER);
3149 %}
3150
3151 // Pointer 64 bit Register not Special
3152 operand iRegPNoSp()
3153 %{
3154 constraint(ALLOC_IN_RC(no_special_ptr_reg));
3155 match(RegP);
3156 op_cost(0);
3157 format %{ %}
3158 interface(REG_INTER);
3159 %}
3160
3161 // This operand is not allowed to use fp even if
3162 // fp is not used to hold the frame pointer.
3163 operand iRegPNoSpNoFp()
3164 %{
3165 constraint(ALLOC_IN_RC(no_special_no_fp_ptr_reg));
3166 match(RegP);
3167 match(iRegPNoSp);
3168 op_cost(0);
3169 format %{ %}
3170 interface(REG_INTER);
3171 %}
3172
3173 operand iRegP_R10()
3174 %{
3175 constraint(ALLOC_IN_RC(r10_reg));
3176 match(RegP);
3177 // match(iRegP);
3178 match(iRegPNoSp);
3179 op_cost(0);
3180 format %{ %}
3181 interface(REG_INTER);
3182 %}
3183
3184 // Pointer 64 bit Register R11 only
3185 operand iRegP_R11()
3186 %{
3187 constraint(ALLOC_IN_RC(r11_reg));
3188 match(RegP);
3189 match(iRegPNoSp);
3190 op_cost(0);
3191 format %{ %}
3192 interface(REG_INTER);
3193 %}
3194
3195 operand iRegP_R12()
3196 %{
3197 constraint(ALLOC_IN_RC(r12_reg));
3198 match(RegP);
3199 // match(iRegP);
3200 match(iRegPNoSp);
3201 op_cost(0);
3202 format %{ %}
3203 interface(REG_INTER);
3204 %}
3205
3206 // Pointer 64 bit Register R13 only
3207 operand iRegP_R13()
3208 %{
3209 constraint(ALLOC_IN_RC(r13_reg));
3210 match(RegP);
3211 match(iRegPNoSp);
3212 op_cost(0);
3213 format %{ %}
3214 interface(REG_INTER);
3215 %}
3216
3217 operand iRegP_R14()
3218 %{
3219 constraint(ALLOC_IN_RC(r14_reg));
3220 match(RegP);
3221 // match(iRegP);
3222 match(iRegPNoSp);
3223 op_cost(0);
3224 format %{ %}
3225 interface(REG_INTER);
3226 %}
3227
3228 operand iRegP_R15()
3229 %{
3230 constraint(ALLOC_IN_RC(r15_reg));
3231 match(RegP);
3232 // match(iRegP);
3233 match(iRegPNoSp);
3234 op_cost(0);
3235 format %{ %}
3236 interface(REG_INTER);
3237 %}
3238
3239 operand iRegP_R16()
3240 %{
3241 constraint(ALLOC_IN_RC(r16_reg));
3242 match(RegP);
3243 match(iRegPNoSp);
3244 op_cost(0);
3245 format %{ %}
3246 interface(REG_INTER);
3247 %}
3248
3249 // Pointer 64 bit Register R28 only
3250 operand iRegP_R28()
3251 %{
3252 constraint(ALLOC_IN_RC(r28_reg));
3253 match(RegP);
3254 match(iRegPNoSp);
3255 op_cost(0);
3256 format %{ %}
3257 interface(REG_INTER);
3258 %}
3259
3260 // Pointer 64 bit Register R30 only
3261 operand iRegP_R30()
3262 %{
3263 constraint(ALLOC_IN_RC(r30_reg));
3264 match(RegP);
3265 match(iRegPNoSp);
3266 op_cost(0);
3267 format %{ %}
3268 interface(REG_INTER);
3269 %}
3270
3271 // Pointer 64 bit Register R31 only
3272 operand iRegP_R31()
3273 %{
3274 constraint(ALLOC_IN_RC(r31_reg));
3275 match(RegP);
3276 match(iRegPNoSp);
3277 op_cost(0);
3278 format %{ %}
3279 interface(REG_INTER);
3280 %}
3281
3282 // Pointer Register Operands
3283 // Narrow Pointer Register
3284 operand iRegN()
3285 %{
3286 constraint(ALLOC_IN_RC(any_reg32));
3287 match(RegN);
3288 match(iRegNNoSp);
3289 op_cost(0);
3290 format %{ %}
3291 interface(REG_INTER);
3292 %}
3293
3294 // Integer 64 bit Register not Special
3295 operand iRegNNoSp()
3296 %{
3297 constraint(ALLOC_IN_RC(no_special_reg32));
3298 match(RegN);
3299 op_cost(0);
3300 format %{ %}
3301 interface(REG_INTER);
3302 %}
3303
3304 // Long 64 bit Register R10 only
3305 operand iRegL_R10()
3306 %{
3307 constraint(ALLOC_IN_RC(r10_reg));
3308 match(RegL);
3309 match(iRegLNoSp);
3310 op_cost(0);
3311 format %{ %}
3312 interface(REG_INTER);
3313 %}
3314
3315 // Float Register
3316 // Float register operands
3317 operand fRegF()
3318 %{
3319 constraint(ALLOC_IN_RC(float_reg));
3320 match(RegF);
3321
3322 op_cost(0);
3323 format %{ %}
3324 interface(REG_INTER);
3325 %}
3326
3327 // Double Register
3328 // Double register operands
3329 operand fRegD()
3330 %{
3331 constraint(ALLOC_IN_RC(double_reg));
3332 match(RegD);
3333
3334 op_cost(0);
3335 format %{ %}
3336 interface(REG_INTER);
3337 %}
3338
3339 // Generic vector class. This will be used for
3340 // all vector operands.
3341 operand vReg()
3342 %{
3343 constraint(ALLOC_IN_RC(vectora_reg));
3344 match(VecA);
3345 op_cost(0);
3346 format %{ %}
3347 interface(REG_INTER);
3348 %}
3349
3350 operand vReg_V1()
3351 %{
3352 constraint(ALLOC_IN_RC(v1_reg));
3353 match(VecA);
3354 match(vReg);
3355 op_cost(0);
3356 format %{ %}
3357 interface(REG_INTER);
3358 %}
3359
3360 operand vReg_V2()
3361 %{
3362 constraint(ALLOC_IN_RC(v2_reg));
3363 match(VecA);
3364 match(vReg);
3365 op_cost(0);
3366 format %{ %}
3367 interface(REG_INTER);
3368 %}
3369
3370 operand vReg_V3()
3371 %{
3372 constraint(ALLOC_IN_RC(v3_reg));
3373 match(VecA);
3374 match(vReg);
3375 op_cost(0);
3376 format %{ %}
3377 interface(REG_INTER);
3378 %}
3379
3380 operand vReg_V4()
3381 %{
3382 constraint(ALLOC_IN_RC(v4_reg));
3383 match(VecA);
3384 match(vReg);
3385 op_cost(0);
3386 format %{ %}
3387 interface(REG_INTER);
3388 %}
3389
3390 operand vReg_V5()
3391 %{
3392 constraint(ALLOC_IN_RC(v5_reg));
3393 match(VecA);
3394 match(vReg);
3395 op_cost(0);
3396 format %{ %}
3397 interface(REG_INTER);
3398 %}
3399
3400 operand vReg_V6()
3401 %{
3402 constraint(ALLOC_IN_RC(v6_reg));
3403 match(VecA);
3404 match(vReg);
3405 op_cost(0);
3406 format %{ %}
3407 interface(REG_INTER);
3408 %}
3409
3410 operand vReg_V7()
3411 %{
3412 constraint(ALLOC_IN_RC(v7_reg));
3413 match(VecA);
3414 match(vReg);
3415 op_cost(0);
3416 format %{ %}
3417 interface(REG_INTER);
3418 %}
3419
3420 operand vReg_V8()
3421 %{
3422 constraint(ALLOC_IN_RC(v8_reg));
3423 match(VecA);
3424 match(vReg);
3425 op_cost(0);
3426 format %{ %}
3427 interface(REG_INTER);
3428 %}
3429
3430 operand vReg_V9()
3431 %{
3432 constraint(ALLOC_IN_RC(v9_reg));
3433 match(VecA);
3434 match(vReg);
3435 op_cost(0);
3436 format %{ %}
3437 interface(REG_INTER);
3438 %}
3439
3440 operand vReg_V10()
3441 %{
3442 constraint(ALLOC_IN_RC(v10_reg));
3443 match(VecA);
3444 match(vReg);
3445 op_cost(0);
3446 format %{ %}
3447 interface(REG_INTER);
3448 %}
3449
3450 operand vReg_V11()
3451 %{
3452 constraint(ALLOC_IN_RC(v11_reg));
3453 match(VecA);
3454 match(vReg);
3455 op_cost(0);
3456 format %{ %}
3457 interface(REG_INTER);
3458 %}
3459
3460 operand vRegMask()
3461 %{
3462 constraint(ALLOC_IN_RC(vmask_reg));
3463 match(RegVectMask);
3464 match(vRegMask_V0);
3465 op_cost(0);
3466 format %{ %}
3467 interface(REG_INTER);
3468 %}
3469
3470 // The mask value used to control execution of a masked
3471 // vector instruction is always supplied by vector register v0.
3472 operand vRegMask_V0()
3473 %{
3474 constraint(ALLOC_IN_RC(vmask_reg_v0));
3475 match(RegVectMask);
3476 match(vRegMask);
3477 op_cost(0);
3478 format %{ %}
3479 interface(REG_INTER);
3480 %}
3481
3482 // Java Thread Register
3483 operand javaThread_RegP(iRegP reg)
3484 %{
3485 constraint(ALLOC_IN_RC(java_thread_reg)); // java_thread_reg
3486 match(reg);
3487 op_cost(0);
3488 format %{ %}
3489 interface(REG_INTER);
3490 %}
3491
3492 //----------Memory Operands----------------------------------------------------
3493 // RISCV has only base_plus_offset and literal address mode, so no need to use
3494 // index and scale. Here set index as 0xffffffff and scale as 0x0.
3495 operand indirect(iRegP reg)
3496 %{
3497 constraint(ALLOC_IN_RC(ptr_reg));
3498 match(reg);
3499 op_cost(0);
3500 format %{ "[$reg]" %}
3501 interface(MEMORY_INTER) %{
3502 base($reg);
3503 index(0xffffffff);
3504 scale(0x0);
3505 disp(0x0);
3506 %}
3507 %}
3508
3509 operand indOffI(iRegP reg, immIOffset off)
3510 %{
3511 constraint(ALLOC_IN_RC(ptr_reg));
3512 match(AddP reg off);
3513 op_cost(0);
3514 format %{ "[$reg, $off]" %}
3515 interface(MEMORY_INTER) %{
3516 base($reg);
3517 index(0xffffffff);
3518 scale(0x0);
3519 disp($off);
3520 %}
3521 %}
3522
3523 operand indOffL(iRegP reg, immLOffset off)
3524 %{
3525 constraint(ALLOC_IN_RC(ptr_reg));
3526 match(AddP reg off);
3527 op_cost(0);
3528 format %{ "[$reg, $off]" %}
3529 interface(MEMORY_INTER) %{
3530 base($reg);
3531 index(0xffffffff);
3532 scale(0x0);
3533 disp($off);
3534 %}
3535 %}
3536
3537 operand indirectN(iRegN reg)
3538 %{
3539 predicate(CompressedOops::shift() == 0);
3540 constraint(ALLOC_IN_RC(ptr_reg));
3541 match(DecodeN reg);
3542 op_cost(0);
3543 format %{ "[$reg]\t# narrow" %}
3544 interface(MEMORY_INTER) %{
3545 base($reg);
3546 index(0xffffffff);
3547 scale(0x0);
3548 disp(0x0);
3549 %}
3550 %}
3551
3552 operand indOffIN(iRegN reg, immIOffset off)
3553 %{
3554 predicate(CompressedOops::shift() == 0);
3555 constraint(ALLOC_IN_RC(ptr_reg));
3556 match(AddP (DecodeN reg) off);
3557 op_cost(0);
3558 format %{ "[$reg, $off]\t# narrow" %}
3559 interface(MEMORY_INTER) %{
3560 base($reg);
3561 index(0xffffffff);
3562 scale(0x0);
3563 disp($off);
3564 %}
3565 %}
3566
3567 operand indOffLN(iRegN reg, immLOffset off)
3568 %{
3569 predicate(CompressedOops::shift() == 0);
3570 constraint(ALLOC_IN_RC(ptr_reg));
3571 match(AddP (DecodeN reg) off);
3572 op_cost(0);
3573 format %{ "[$reg, $off]\t# narrow" %}
3574 interface(MEMORY_INTER) %{
3575 base($reg);
3576 index(0xffffffff);
3577 scale(0x0);
3578 disp($off);
3579 %}
3580 %}
3581
3582 //----------Special Memory Operands--------------------------------------------
3583 // Stack Slot Operand - This operand is used for loading and storing temporary
3584 // values on the stack where a match requires a value to
3585 // flow through memory.
3586 operand stackSlotI(sRegI reg)
3587 %{
3588 constraint(ALLOC_IN_RC(stack_slots));
3589 // No match rule because this operand is only generated in matching
3590 // match(RegI);
3591 format %{ "[$reg]" %}
3592 interface(MEMORY_INTER) %{
3593 base(0x02); // RSP
3594 index(0xffffffff); // No Index
3595 scale(0x0); // No Scale
3596 disp($reg); // Stack Offset
3597 %}
3598 %}
3599
3600 operand stackSlotF(sRegF reg)
3601 %{
3602 constraint(ALLOC_IN_RC(stack_slots));
3603 // No match rule because this operand is only generated in matching
3604 // match(RegF);
3605 format %{ "[$reg]" %}
3606 interface(MEMORY_INTER) %{
3607 base(0x02); // RSP
3608 index(0xffffffff); // No Index
3609 scale(0x0); // No Scale
3610 disp($reg); // Stack Offset
3611 %}
3612 %}
3613
3614 operand stackSlotD(sRegD reg)
3615 %{
3616 constraint(ALLOC_IN_RC(stack_slots));
3617 // No match rule because this operand is only generated in matching
3618 // match(RegD);
3619 format %{ "[$reg]" %}
3620 interface(MEMORY_INTER) %{
3621 base(0x02); // RSP
3622 index(0xffffffff); // No Index
3623 scale(0x0); // No Scale
3624 disp($reg); // Stack Offset
3625 %}
3626 %}
3627
3628 operand stackSlotL(sRegL reg)
3629 %{
3630 constraint(ALLOC_IN_RC(stack_slots));
3631 // No match rule because this operand is only generated in matching
3632 // match(RegL);
3633 format %{ "[$reg]" %}
3634 interface(MEMORY_INTER) %{
3635 base(0x02); // RSP
3636 index(0xffffffff); // No Index
3637 scale(0x0); // No Scale
3638 disp($reg); // Stack Offset
3639 %}
3640 %}
3641
3642 // Special operand allowing long args to int ops to be truncated for free
3643
3644 operand iRegL2I(iRegL reg) %{
3645
3646 op_cost(0);
3647
3648 match(ConvL2I reg);
3649
3650 format %{ "l2i($reg)" %}
3651
3652 interface(REG_INTER)
3653 %}
3654
3655
3656 // Comparison Operands
3657 // NOTE: Label is a predefined operand which should not be redefined in
3658 // the AD file. It is generically handled within the ADLC.
3659
3660 //----------Conditional Branch Operands----------------------------------------
3661 // Comparison Op - This is the operation of the comparison, and is limited to
3662 // the following set of codes:
3663 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
3664 //
3665 // Other attributes of the comparison, such as unsignedness, are specified
3666 // by the comparison instruction that sets a condition code flags register.
3667 // That result is represented by a flags operand whose subtype is appropriate
3668 // to the unsignedness (etc.) of the comparison.
3669 //
3670 // Later, the instruction which matches both the Comparison Op (a Bool) and
3671 // the flags (produced by the Cmp) specifies the coding of the comparison op
3672 // by matching a specific subtype of Bool operand below, such as cmpOpU.
3673
3674
3675 // used for signed integral comparisons and fp comparisons
3676 operand cmpOp()
3677 %{
3678 match(Bool);
3679
3680 format %{ "" %}
3681
3682 // the values in interface derives from struct BoolTest::mask
3683 interface(COND_INTER) %{
3684 equal(0x0, "eq");
3685 greater(0x1, "gt");
3686 overflow(0x2, "overflow");
3687 less(0x3, "lt");
3688 not_equal(0x4, "ne");
3689 less_equal(0x5, "le");
3690 no_overflow(0x6, "no_overflow");
3691 greater_equal(0x7, "ge");
3692 %}
3693 %}
3694
3695 // used for unsigned integral comparisons
3696 operand cmpOpU()
3697 %{
3698 match(Bool);
3699
3700 format %{ "" %}
3701 // the values in interface derives from struct BoolTest::mask
3702 interface(COND_INTER) %{
3703 equal(0x0, "eq");
3704 greater(0x1, "gtu");
3705 overflow(0x2, "overflow");
3706 less(0x3, "ltu");
3707 not_equal(0x4, "ne");
3708 less_equal(0x5, "leu");
3709 no_overflow(0x6, "no_overflow");
3710 greater_equal(0x7, "geu");
3711 %}
3712 %}
3713
3714 // used for certain integral comparisons which can be
3715 // converted to bxx instructions
3716 operand cmpOpEqNe()
3717 %{
3718 match(Bool);
3719 op_cost(0);
3720 predicate(n->as_Bool()->_test._test == BoolTest::ne ||
3721 n->as_Bool()->_test._test == BoolTest::eq);
3722
3723 format %{ "" %}
3724 interface(COND_INTER) %{
3725 equal(0x0, "eq");
3726 greater(0x1, "gt");
3727 overflow(0x2, "overflow");
3728 less(0x3, "lt");
3729 not_equal(0x4, "ne");
3730 less_equal(0x5, "le");
3731 no_overflow(0x6, "no_overflow");
3732 greater_equal(0x7, "ge");
3733 %}
3734 %}
3735
3736 operand cmpOpULtGe()
3737 %{
3738 match(Bool);
3739 op_cost(0);
3740 predicate(n->as_Bool()->_test._test == BoolTest::lt ||
3741 n->as_Bool()->_test._test == BoolTest::ge);
3742
3743 format %{ "" %}
3744 interface(COND_INTER) %{
3745 equal(0x0, "eq");
3746 greater(0x1, "gtu");
3747 overflow(0x2, "overflow");
3748 less(0x3, "ltu");
3749 not_equal(0x4, "ne");
3750 less_equal(0x5, "leu");
3751 no_overflow(0x6, "no_overflow");
3752 greater_equal(0x7, "geu");
3753 %}
3754 %}
3755
3756 operand cmpOpUEqNeLeGt()
3757 %{
3758 match(Bool);
3759 op_cost(0);
3760 predicate(n->as_Bool()->_test._test == BoolTest::ne ||
3761 n->as_Bool()->_test._test == BoolTest::eq ||
3762 n->as_Bool()->_test._test == BoolTest::le ||
3763 n->as_Bool()->_test._test == BoolTest::gt);
3764
3765 format %{ "" %}
3766 interface(COND_INTER) %{
3767 equal(0x0, "eq");
3768 greater(0x1, "gtu");
3769 overflow(0x2, "overflow");
3770 less(0x3, "ltu");
3771 not_equal(0x4, "ne");
3772 less_equal(0x5, "leu");
3773 no_overflow(0x6, "no_overflow");
3774 greater_equal(0x7, "geu");
3775 %}
3776 %}
3777
3778
3779 // Flags register, used as output of compare logic
3780 operand rFlagsReg()
3781 %{
3782 constraint(ALLOC_IN_RC(reg_flags));
3783 match(RegFlags);
3784
3785 op_cost(0);
3786 format %{ "RFLAGS" %}
3787 interface(REG_INTER);
3788 %}
3789
3790 // Special Registers
3791
3792 // Method Register
3793 operand inline_cache_RegP(iRegP reg)
3794 %{
3795 constraint(ALLOC_IN_RC(method_reg)); // inline_cache_reg
3796 match(reg);
3797 match(iRegPNoSp);
3798 op_cost(0);
3799 format %{ %}
3800 interface(REG_INTER);
3801 %}
3802
3803 //----------OPERAND CLASSES----------------------------------------------------
3804 // Operand Classes are groups of operands that are used as to simplify
3805 // instruction definitions by not requiring the AD writer to specify
3806 // separate instructions for every form of operand when the
3807 // instruction accepts multiple operand types with the same basic
3808 // encoding and format. The classic case of this is memory operands.
3809
3810 // memory is used to define read/write location for load/store
3811 // instruction defs. we can turn a memory op into an Address
3812
3813 opclass memory(indirect, indOffI, indOffL, indirectN, indOffIN, indOffLN);
3814
3815 // iRegIorL2I is used for src inputs in rules for 32 bit int (I)
3816 // operations. it allows the src to be either an iRegI or a (ConvL2I
3817 // iRegL). in the latter case the l2i normally planted for a ConvL2I
3818 // can be elided because the 32-bit instruction will just employ the
3819 // lower 32 bits anyway.
3820 //
3821 // n.b. this does not elide all L2I conversions. if the truncated
3822 // value is consumed by more than one operation then the ConvL2I
3823 // cannot be bundled into the consuming nodes so an l2i gets planted
3824 // (actually an addiw $dst, $src, 0) and the downstream instructions
3825 // consume the result of the L2I as an iRegI input. That's a shame since
3826 // the addiw is actually redundant but its not too costly.
3827
3828 opclass iRegIorL2I(iRegI, iRegL2I);
3829 opclass iRegIorL(iRegI, iRegL);
3830 opclass iRegNorP(iRegN, iRegP);
3831 opclass iRegILNP(iRegI, iRegL, iRegN, iRegP);
3832 opclass iRegILNPNoSp(iRegINoSp, iRegLNoSp, iRegNNoSp, iRegPNoSp);
3833 opclass immIorL(immI, immL);
3834
3835 //----------PIPELINE-----------------------------------------------------------
3836 // Rules which define the behavior of the target architectures pipeline.
3837
3838 // For specific pipelines, e.g. generic RISC-V, define the stages of that pipeline
3839 //pipe_desc(ID, EX, MEM, WR);
3840 #define ID S0
3841 #define EX S1
3842 #define MEM S2
3843 #define WR S3
3844
3845 // Integer ALU reg operation
3846 pipeline %{
3847
3848 attributes %{
3849 // RISC-V instructions are of length 2 or 4 bytes.
3850 variable_size_instructions;
3851 instruction_unit_size = 2;
3852
3853 // Up to 4 instructions per bundle
3854 max_instructions_per_bundle = 4;
3855
3856 // The RISC-V processor fetches 64 bytes...
3857 instruction_fetch_unit_size = 64;
3858
3859 // ...in one line.
3860 instruction_fetch_units = 1;
3861 %}
3862
3863 // We don't use an actual pipeline model so don't care about resources
3864 // or description. we do use pipeline classes to introduce fixed
3865 // latencies
3866
3867 //----------RESOURCES----------------------------------------------------------
3868 // Resources are the functional units available to the machine
3869
3870 // Generic RISC-V pipeline
3871 // 1 decoder
3872 // 1 instruction decoded per cycle
3873 // 1 load/store ops per cycle, 1 branch, 1 FPU
3874 // 1 mul, 1 div
3875
3876 resources ( DECODE,
3877 ALU,
3878 MUL,
3879 DIV,
3880 BRANCH,
3881 LDST,
3882 FPU);
3883
3884 //----------PIPELINE DESCRIPTION-----------------------------------------------
3885 // Pipeline Description specifies the stages in the machine's pipeline
3886
3887 // Define the pipeline as a generic 6 stage pipeline
3888 pipe_desc(S0, S1, S2, S3, S4, S5);
3889
3890 //----------PIPELINE CLASSES---------------------------------------------------
3891 // Pipeline Classes describe the stages in which input and output are
3892 // referenced by the hardware pipeline.
3893
3894 pipe_class fp_dop_reg_reg_s(fRegF dst, fRegF src1, fRegF src2)
3895 %{
3896 single_instruction;
3897 src1 : S1(read);
3898 src2 : S2(read);
3899 dst : S5(write);
3900 DECODE : ID;
3901 FPU : S5;
3902 %}
3903
3904 pipe_class fp_dop_reg_reg_d(fRegD dst, fRegD src1, fRegD src2)
3905 %{
3906 src1 : S1(read);
3907 src2 : S2(read);
3908 dst : S5(write);
3909 DECODE : ID;
3910 FPU : S5;
3911 %}
3912
3913 pipe_class fp_uop_s(fRegF dst, fRegF src)
3914 %{
3915 single_instruction;
3916 src : S1(read);
3917 dst : S5(write);
3918 DECODE : ID;
3919 FPU : S5;
3920 %}
3921
3922 pipe_class fp_uop_d(fRegD dst, fRegD src)
3923 %{
3924 single_instruction;
3925 src : S1(read);
3926 dst : S5(write);
3927 DECODE : ID;
3928 FPU : S5;
3929 %}
3930
3931 pipe_class fp_d2f(fRegF dst, fRegD src)
3932 %{
3933 single_instruction;
3934 src : S1(read);
3935 dst : S5(write);
3936 DECODE : ID;
3937 FPU : S5;
3938 %}
3939
3940 pipe_class fp_f2d(fRegD dst, fRegF src)
3941 %{
3942 single_instruction;
3943 src : S1(read);
3944 dst : S5(write);
3945 DECODE : ID;
3946 FPU : S5;
3947 %}
3948
3949 pipe_class fp_f2i(iRegINoSp dst, fRegF src)
3950 %{
3951 single_instruction;
3952 src : S1(read);
3953 dst : S5(write);
3954 DECODE : ID;
3955 FPU : S5;
3956 %}
3957
3958 pipe_class fp_f2l(iRegLNoSp dst, fRegF src)
3959 %{
3960 single_instruction;
3961 src : S1(read);
3962 dst : S5(write);
3963 DECODE : ID;
3964 FPU : S5;
3965 %}
3966
3967 pipe_class fp_i2f(fRegF dst, iRegIorL2I src)
3968 %{
3969 single_instruction;
3970 src : S1(read);
3971 dst : S5(write);
3972 DECODE : ID;
3973 FPU : S5;
3974 %}
3975
3976 pipe_class fp_l2f(fRegF dst, iRegL src)
3977 %{
3978 single_instruction;
3979 src : S1(read);
3980 dst : S5(write);
3981 DECODE : ID;
3982 FPU : S5;
3983 %}
3984
3985 pipe_class fp_d2i(iRegINoSp dst, fRegD src)
3986 %{
3987 single_instruction;
3988 src : S1(read);
3989 dst : S5(write);
3990 DECODE : ID;
3991 FPU : S5;
3992 %}
3993
3994 pipe_class fp_d2l(iRegLNoSp dst, fRegD src)
3995 %{
3996 single_instruction;
3997 src : S1(read);
3998 dst : S5(write);
3999 DECODE : ID;
4000 FPU : S5;
4001 %}
4002
4003 pipe_class fp_i2d(fRegD dst, iRegIorL2I src)
4004 %{
4005 single_instruction;
4006 src : S1(read);
4007 dst : S5(write);
4008 DECODE : ID;
4009 FPU : S5;
4010 %}
4011
4012 pipe_class fp_l2d(fRegD dst, iRegIorL2I src)
4013 %{
4014 single_instruction;
4015 src : S1(read);
4016 dst : S5(write);
4017 DECODE : ID;
4018 FPU : S5;
4019 %}
4020
4021 pipe_class fp_div_s(fRegF dst, fRegF src1, fRegF src2)
4022 %{
4023 single_instruction;
4024 src1 : S1(read);
4025 src2 : S2(read);
4026 dst : S5(write);
4027 DECODE : ID;
4028 FPU : S5;
4029 %}
4030
4031 pipe_class fp_div_d(fRegD dst, fRegD src1, fRegD src2)
4032 %{
4033 single_instruction;
4034 src1 : S1(read);
4035 src2 : S2(read);
4036 dst : S5(write);
4037 DECODE : ID;
4038 FPU : S5;
4039 %}
4040
4041 pipe_class fp_sqrt_s(fRegF dst, fRegF src)
4042 %{
4043 single_instruction;
4044 src : S1(read);
4045 dst : S5(write);
4046 DECODE : ID;
4047 FPU : S5;
4048 %}
4049
4050 pipe_class fp_sqrt_d(fRegD dst, fRegD src)
4051 %{
4052 single_instruction;
4053 src : S1(read);
4054 dst : S5(write);
4055 DECODE : ID;
4056 FPU : S5;
4057 %}
4058
4059 pipe_class fp_load_constant_s(fRegF dst)
4060 %{
4061 single_instruction;
4062 dst : S5(write);
4063 DECODE : ID;
4064 FPU : S5;
4065 %}
4066
4067 pipe_class fp_load_constant_d(fRegD dst)
4068 %{
4069 single_instruction;
4070 dst : S5(write);
4071 DECODE : ID;
4072 FPU : S5;
4073 %}
4074
4075 pipe_class fp_load_mem_s(fRegF dst, memory mem)
4076 %{
4077 single_instruction;
4078 mem : S1(read);
4079 dst : S5(write);
4080 DECODE : ID;
4081 LDST : MEM;
4082 %}
4083
4084 pipe_class fp_load_mem_d(fRegD dst, memory mem)
4085 %{
4086 single_instruction;
4087 mem : S1(read);
4088 dst : S5(write);
4089 DECODE : ID;
4090 LDST : MEM;
4091 %}
4092
4093 pipe_class fp_store_reg_s(fRegF src, memory mem)
4094 %{
4095 single_instruction;
4096 src : S1(read);
4097 mem : S5(write);
4098 DECODE : ID;
4099 LDST : MEM;
4100 %}
4101
4102 pipe_class fp_store_reg_d(fRegD src, memory mem)
4103 %{
4104 single_instruction;
4105 src : S1(read);
4106 mem : S5(write);
4107 DECODE : ID;
4108 LDST : MEM;
4109 %}
4110
4111 //------- Integer ALU operations --------------------------
4112
4113 // Integer ALU reg-reg operation
4114 // Operands needs in ID, result generated in EX
4115 // E.g. ADD Rd, Rs1, Rs2
4116 pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2)
4117 %{
4118 single_instruction;
4119 dst : EX(write);
4120 src1 : ID(read);
4121 src2 : ID(read);
4122 DECODE : ID;
4123 ALU : EX;
4124 %}
4125
4126 // Integer ALU reg operation with constant shift
4127 // E.g. SLLI Rd, Rs1, #shift
4128 pipe_class ialu_reg_shift(iRegI dst, iRegI src1)
4129 %{
4130 single_instruction;
4131 dst : EX(write);
4132 src1 : ID(read);
4133 DECODE : ID;
4134 ALU : EX;
4135 %}
4136
4137 // Integer ALU reg-reg operation with variable shift
4138 // both operands must be available in ID
4139 // E.g. SLL Rd, Rs1, Rs2
4140 pipe_class ialu_reg_reg_vshift(iRegI dst, iRegI src1, iRegI src2)
4141 %{
4142 single_instruction;
4143 dst : EX(write);
4144 src1 : ID(read);
4145 src2 : ID(read);
4146 DECODE : ID;
4147 ALU : EX;
4148 %}
4149
4150 // Integer ALU reg operation
4151 // E.g. NEG Rd, Rs2
4152 pipe_class ialu_reg(iRegI dst, iRegI src)
4153 %{
4154 single_instruction;
4155 dst : EX(write);
4156 src : ID(read);
4157 DECODE : ID;
4158 ALU : EX;
4159 %}
4160
4161 // Integer ALU reg immediate operation
4162 // E.g. ADDI Rd, Rs1, #imm
4163 pipe_class ialu_reg_imm(iRegI dst, iRegI src1)
4164 %{
4165 single_instruction;
4166 dst : EX(write);
4167 src1 : ID(read);
4168 DECODE : ID;
4169 ALU : EX;
4170 %}
4171
4172 // Integer ALU immediate operation (no source operands)
4173 // E.g. LI Rd, #imm
4174 pipe_class ialu_imm(iRegI dst)
4175 %{
4176 single_instruction;
4177 dst : EX(write);
4178 DECODE : ID;
4179 ALU : EX;
4180 %}
4181
4182 //------- Multiply pipeline operations --------------------
4183
4184 // Multiply reg-reg
4185 // E.g. MULW Rd, Rs1, Rs2
4186 pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2)
4187 %{
4188 single_instruction;
4189 dst : WR(write);
4190 src1 : ID(read);
4191 src2 : ID(read);
4192 DECODE : ID;
4193 MUL : WR;
4194 %}
4195
4196 // E.g. MUL RD, Rs1, Rs2
4197 pipe_class lmul_reg_reg(iRegL dst, iRegL src1, iRegL src2)
4198 %{
4199 single_instruction;
4200 fixed_latency(3); // Maximum latency for 64 bit mul
4201 dst : WR(write);
4202 src1 : ID(read);
4203 src2 : ID(read);
4204 DECODE : ID;
4205 MUL : WR;
4206 %}
4207
4208 //------- Divide pipeline operations --------------------
4209
4210 // E.g. DIVW Rd, Rs1, Rs2
4211 pipe_class idiv_reg_reg(iRegI dst, iRegI src1, iRegI src2)
4212 %{
4213 single_instruction;
4214 fixed_latency(8); // Maximum latency for 32 bit divide
4215 dst : WR(write);
4216 src1 : ID(read);
4217 src2 : ID(read);
4218 DECODE : ID;
4219 DIV : WR;
4220 %}
4221
4222 // E.g. DIV RD, Rs1, Rs2
4223 pipe_class ldiv_reg_reg(iRegL dst, iRegL src1, iRegL src2)
4224 %{
4225 single_instruction;
4226 fixed_latency(16); // Maximum latency for 64 bit divide
4227 dst : WR(write);
4228 src1 : ID(read);
4229 src2 : ID(read);
4230 DECODE : ID;
4231 DIV : WR;
4232 %}
4233
4234 //------- Load pipeline operations ------------------------
4235
4236 // Load - prefetch
4237 // Eg. PREFETCH_W mem
4238 pipe_class iload_prefetch(memory mem)
4239 %{
4240 single_instruction;
4241 mem : ID(read);
4242 DECODE : ID;
4243 LDST : MEM;
4244 %}
4245
4246 // Load - reg, mem
4247 // E.g. LA Rd, mem
4248 pipe_class iload_reg_mem(iRegI dst, memory mem)
4249 %{
4250 single_instruction;
4251 dst : WR(write);
4252 mem : ID(read);
4253 DECODE : ID;
4254 LDST : MEM;
4255 %}
4256
4257 // Load - reg, reg
4258 // E.g. LD Rd, Rs
4259 pipe_class iload_reg_reg(iRegI dst, iRegI src)
4260 %{
4261 single_instruction;
4262 dst : WR(write);
4263 src : ID(read);
4264 DECODE : ID;
4265 LDST : MEM;
4266 %}
4267
4268 //------- Store pipeline operations -----------------------
4269
4270 // Store - zr, mem
4271 // E.g. SD zr, mem
4272 pipe_class istore_mem(memory mem)
4273 %{
4274 single_instruction;
4275 mem : ID(read);
4276 DECODE : ID;
4277 LDST : MEM;
4278 %}
4279
4280 // Store - reg, mem
4281 // E.g. SD Rs, mem
4282 pipe_class istore_reg_mem(iRegI src, memory mem)
4283 %{
4284 single_instruction;
4285 mem : ID(read);
4286 src : EX(read);
4287 DECODE : ID;
4288 LDST : MEM;
4289 %}
4290
4291 // Store - reg, reg
4292 // E.g. SD Rs2, Rs1
4293 pipe_class istore_reg_reg(iRegI dst, iRegI src)
4294 %{
4295 single_instruction;
4296 dst : ID(read);
4297 src : EX(read);
4298 DECODE : ID;
4299 LDST : MEM;
4300 %}
4301
4302 //------- Control transfer pipeline operations ------------
4303
4304 // Branch
4305 pipe_class pipe_branch()
4306 %{
4307 single_instruction;
4308 DECODE : ID;
4309 BRANCH : EX;
4310 %}
4311
4312 // Branch
4313 pipe_class pipe_branch_reg(iRegI src)
4314 %{
4315 single_instruction;
4316 src : ID(read);
4317 DECODE : ID;
4318 BRANCH : EX;
4319 %}
4320
4321 // Compare & Branch
4322 // E.g. BEQ Rs1, Rs2, L
4323 pipe_class pipe_cmp_branch(iRegI src1, iRegI src2)
4324 %{
4325 single_instruction;
4326 src1 : ID(read);
4327 src2 : ID(read);
4328 DECODE : ID;
4329 BRANCH : EX;
4330 %}
4331
4332 // E.g. BEQZ Rs, L
4333 pipe_class pipe_cmpz_branch(iRegI src)
4334 %{
4335 single_instruction;
4336 src : ID(read);
4337 DECODE : ID;
4338 BRANCH : EX;
4339 %}
4340
4341 //------- Synchronisation operations ----------------------
4342 // Any operation requiring serialization
4343 // E.g. FENCE/Atomic Ops/Load Acquire/Store Release
4344 pipe_class pipe_serial()
4345 %{
4346 single_instruction;
4347 force_serialization;
4348 fixed_latency(16);
4349 DECODE : ID;
4350 LDST : MEM;
4351 %}
4352
4353 pipe_class pipe_slow()
4354 %{
4355 instruction_count(10);
4356 multiple_bundles;
4357 force_serialization;
4358 fixed_latency(16);
4359 DECODE : ID;
4360 LDST : MEM;
4361 %}
4362
4363 // The real do-nothing guy
4364 pipe_class real_empty()
4365 %{
4366 instruction_count(0);
4367 %}
4368
4369 // Empty pipeline class
4370 pipe_class pipe_class_empty()
4371 %{
4372 single_instruction;
4373 fixed_latency(0);
4374 %}
4375
4376 // Default pipeline class.
4377 pipe_class pipe_class_default()
4378 %{
4379 single_instruction;
4380 fixed_latency(2);
4381 %}
4382
4383 // Pipeline class for compares.
4384 pipe_class pipe_class_compare()
4385 %{
4386 single_instruction;
4387 fixed_latency(16);
4388 %}
4389
4390 // Pipeline class for memory operations.
4391 pipe_class pipe_class_memory()
4392 %{
4393 single_instruction;
4394 fixed_latency(16);
4395 %}
4396
4397 // Pipeline class for call.
4398 pipe_class pipe_class_call()
4399 %{
4400 single_instruction;
4401 fixed_latency(100);
4402 %}
4403
4404 // Define the class for the Nop node.
4405 define %{
4406 MachNop = pipe_class_empty;
4407 %}
4408 %}
4409 //----------INSTRUCTIONS-------------------------------------------------------
4410 //
4411 // match -- States which machine-independent subtree may be replaced
4412 // by this instruction.
4413 // ins_cost -- The estimated cost of this instruction is used by instruction
4414 // selection to identify a minimum cost tree of machine
4415 // instructions that matches a tree of machine-independent
4416 // instructions.
4417 // format -- A string providing the disassembly for this instruction.
4418 // The value of an instruction's operand may be inserted
4419 // by referring to it with a '$' prefix.
4420 // opcode -- Three instruction opcodes may be provided. These are referred
4421 // to within an encode class as $primary, $secondary, and $tertiary
4422 // rrspectively. The primary opcode is commonly used to
4423 // indicate the type of machine instruction, while secondary
4424 // and tertiary are often used for prefix options or addressing
4425 // modes.
4426 // ins_encode -- A list of encode classes with parameters. The encode class
4427 // name must have been defined in an 'enc_class' specification
4428 // in the encode section of the architecture description.
4429
4430 // ============================================================================
4431 // Memory (Load/Store) Instructions
4432
4433 // Load Instructions
4434
4435 // Load Byte (8 bit signed)
4436 instruct loadB(iRegINoSp dst, memory mem)
4437 %{
4438 match(Set dst (LoadB mem));
4439
4440 ins_cost(LOAD_COST);
4441 format %{ "lb $dst, $mem\t# byte, #@loadB" %}
4442
4443 ins_encode %{
4444 __ lb(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4445 %}
4446
4447 ins_pipe(iload_reg_mem);
4448 %}
4449
4450 // Load Byte (8 bit signed) into long
4451 instruct loadB2L(iRegLNoSp dst, memory mem)
4452 %{
4453 match(Set dst (ConvI2L (LoadB mem)));
4454
4455 ins_cost(LOAD_COST);
4456 format %{ "lb $dst, $mem\t# byte, #@loadB2L" %}
4457
4458 ins_encode %{
4459 __ lb(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4460 %}
4461
4462 ins_pipe(iload_reg_mem);
4463 %}
4464
4465 // Load Byte (8 bit unsigned)
4466 instruct loadUB(iRegINoSp dst, memory mem)
4467 %{
4468 match(Set dst (LoadUB mem));
4469
4470 ins_cost(LOAD_COST);
4471 format %{ "lbu $dst, $mem\t# byte, #@loadUB" %}
4472
4473 ins_encode %{
4474 __ lbu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4475 %}
4476
4477 ins_pipe(iload_reg_mem);
4478 %}
4479
4480 // Load Byte (8 bit unsigned) into long
4481 instruct loadUB2L(iRegLNoSp dst, memory mem)
4482 %{
4483 match(Set dst (ConvI2L (LoadUB mem)));
4484
4485 ins_cost(LOAD_COST);
4486 format %{ "lbu $dst, $mem\t# byte, #@loadUB2L" %}
4487
4488 ins_encode %{
4489 __ lbu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4490 %}
4491
4492 ins_pipe(iload_reg_mem);
4493 %}
4494
4495 // Load Short (16 bit signed)
4496 instruct loadS(iRegINoSp dst, memory mem)
4497 %{
4498 match(Set dst (LoadS mem));
4499
4500 ins_cost(LOAD_COST);
4501 format %{ "lh $dst, $mem\t# short, #@loadS" %}
4502
4503 ins_encode %{
4504 __ lh(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4505 %}
4506
4507 ins_pipe(iload_reg_mem);
4508 %}
4509
4510 // Load Short (16 bit signed) into long
4511 instruct loadS2L(iRegLNoSp dst, memory mem)
4512 %{
4513 match(Set dst (ConvI2L (LoadS mem)));
4514
4515 ins_cost(LOAD_COST);
4516 format %{ "lh $dst, $mem\t# short, #@loadS2L" %}
4517
4518 ins_encode %{
4519 __ lh(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4520 %}
4521
4522 ins_pipe(iload_reg_mem);
4523 %}
4524
4525 // Load Char (16 bit unsigned)
4526 instruct loadUS(iRegINoSp dst, memory mem)
4527 %{
4528 match(Set dst (LoadUS mem));
4529
4530 ins_cost(LOAD_COST);
4531 format %{ "lhu $dst, $mem\t# short, #@loadUS" %}
4532
4533 ins_encode %{
4534 __ lhu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4535 %}
4536
4537 ins_pipe(iload_reg_mem);
4538 %}
4539
4540 // Load Short/Char (16 bit unsigned) into long
4541 instruct loadUS2L(iRegLNoSp dst, memory mem)
4542 %{
4543 match(Set dst (ConvI2L (LoadUS mem)));
4544
4545 ins_cost(LOAD_COST);
4546 format %{ "lhu $dst, $mem\t# short, #@loadUS2L" %}
4547
4548 ins_encode %{
4549 __ lhu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4550 %}
4551
4552 ins_pipe(iload_reg_mem);
4553 %}
4554
4555 // Load Integer (32 bit signed)
4556 instruct loadI(iRegINoSp dst, memory mem)
4557 %{
4558 match(Set dst (LoadI mem));
4559
4560 ins_cost(LOAD_COST);
4561 format %{ "lw $dst, $mem\t# int, #@loadI" %}
4562
4563 ins_encode %{
4564 __ lw(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4565 %}
4566
4567 ins_pipe(iload_reg_mem);
4568 %}
4569
4570 // Load Integer (32 bit signed) into long
4571 instruct loadI2L(iRegLNoSp dst, memory mem)
4572 %{
4573 match(Set dst (ConvI2L (LoadI mem)));
4574
4575 ins_cost(LOAD_COST);
4576 format %{ "lw $dst, $mem\t# int, #@loadI2L" %}
4577
4578 ins_encode %{
4579 __ lw(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4580 %}
4581
4582 ins_pipe(iload_reg_mem);
4583 %}
4584
4585 // Load Integer (32 bit unsigned) into long
4586 instruct loadUI2L(iRegLNoSp dst, memory mem, immL_32bits mask)
4587 %{
4588 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
4589
4590 ins_cost(LOAD_COST);
4591 format %{ "lwu $dst, $mem\t# int, #@loadUI2L" %}
4592
4593 ins_encode %{
4594 __ lwu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4595 %}
4596
4597 ins_pipe(iload_reg_mem);
4598 %}
4599
4600 // Load Long (64 bit signed)
4601 instruct loadL(iRegLNoSp dst, memory mem)
4602 %{
4603 match(Set dst (LoadL mem));
4604
4605 ins_cost(LOAD_COST);
4606 format %{ "ld $dst, $mem\t# int, #@loadL" %}
4607
4608 ins_encode %{
4609 __ ld(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4610 %}
4611
4612 ins_pipe(iload_reg_mem);
4613 %}
4614
4615 // Load Range
4616 instruct loadRange(iRegINoSp dst, memory mem)
4617 %{
4618 match(Set dst (LoadRange mem));
4619
4620 ins_cost(LOAD_COST);
4621 format %{ "lwu $dst, $mem\t# range, #@loadRange" %}
4622
4623 ins_encode %{
4624 __ lwu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4625 %}
4626
4627 ins_pipe(iload_reg_mem);
4628 %}
4629
4630 // Load Pointer
4631 instruct loadP(iRegPNoSp dst, memory mem)
4632 %{
4633 match(Set dst (LoadP mem));
4634 predicate(n->as_Load()->barrier_data() == 0);
4635
4636 ins_cost(LOAD_COST);
4637 format %{ "ld $dst, $mem\t# ptr, #@loadP" %}
4638
4639 ins_encode %{
4640 __ ld(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4641 %}
4642
4643 ins_pipe(iload_reg_mem);
4644 %}
4645
4646 // Load Compressed Pointer
4647 instruct loadN(iRegNNoSp dst, memory mem)
4648 %{
4649 predicate(n->as_Load()->barrier_data() == 0);
4650 match(Set dst (LoadN mem));
4651
4652 ins_cost(LOAD_COST);
4653 format %{ "lwu $dst, $mem\t# compressed ptr, #@loadN" %}
4654
4655 ins_encode %{
4656 __ lwu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4657 %}
4658
4659 ins_pipe(iload_reg_mem);
4660 %}
4661
4662 // Load Klass Pointer
4663 instruct loadKlass(iRegPNoSp dst, memory mem)
4664 %{
4665 match(Set dst (LoadKlass mem));
4666
4667 ins_cost(LOAD_COST);
4668 format %{ "ld $dst, $mem\t# class, #@loadKlass" %}
4669
4670 ins_encode %{
4671 __ ld(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4672 %}
4673
4674 ins_pipe(iload_reg_mem);
4675 %}
4676
4677 // Load Narrow Klass Pointer
4678 instruct loadNKlass(iRegNNoSp dst, memory mem)
4679 %{
4680 predicate(!UseCompactObjectHeaders);
4681 match(Set dst (LoadNKlass mem));
4682
4683 ins_cost(LOAD_COST);
4684 format %{ "lwu $dst, $mem\t# compressed class ptr, #@loadNKlass" %}
4685
4686 ins_encode %{
4687 __ lwu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4688 %}
4689
4690 ins_pipe(iload_reg_mem);
4691 %}
4692
4693 instruct loadNKlassCompactHeaders(iRegNNoSp dst, memory mem)
4694 %{
4695 predicate(UseCompactObjectHeaders);
4696 match(Set dst (LoadNKlass mem));
4697
4698 ins_cost(LOAD_COST);
4699 format %{
4700 "lwu $dst, $mem\t# compressed klass ptr, shifted\n\t"
4701 "srli $dst, $dst, markWord::klass_shift_at_offset"
4702 %}
4703
4704 ins_encode %{
4705 __ lwu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4706 __ srli(as_Register($dst$$reg), as_Register($dst$$reg), (unsigned) markWord::klass_shift_at_offset);
4707 %}
4708
4709 ins_pipe(iload_reg_mem);
4710 %}
4711
4712 // Load Float
4713 instruct loadF(fRegF dst, memory mem)
4714 %{
4715 match(Set dst (LoadF mem));
4716
4717 ins_cost(LOAD_COST);
4718 format %{ "flw $dst, $mem\t# float, #@loadF" %}
4719
4720 ins_encode %{
4721 __ flw(as_FloatRegister($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4722 %}
4723
4724 ins_pipe(fp_load_mem_s);
4725 %}
4726
4727 // Load Double
4728 instruct loadD(fRegD dst, memory mem)
4729 %{
4730 match(Set dst (LoadD mem));
4731
4732 ins_cost(LOAD_COST);
4733 format %{ "fld $dst, $mem\t# double, #@loadD" %}
4734
4735 ins_encode %{
4736 __ fld(as_FloatRegister($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4737 %}
4738
4739 ins_pipe(fp_load_mem_d);
4740 %}
4741
4742 // Load Int Constant
4743 instruct loadConI(iRegINoSp dst, immI src)
4744 %{
4745 match(Set dst src);
4746
4747 ins_cost(ALU_COST);
4748 format %{ "mv $dst, $src\t# int, #@loadConI" %}
4749
4750 ins_encode(riscv_enc_mov_imm(dst, src));
4751
4752 ins_pipe(ialu_imm);
4753 %}
4754
4755 // Load Long Constant
4756 instruct loadConL(iRegLNoSp dst, immL src)
4757 %{
4758 match(Set dst src);
4759
4760 ins_cost(ALU_COST);
4761 format %{ "mv $dst, $src\t# long, #@loadConL" %}
4762
4763 ins_encode(riscv_enc_mov_imm(dst, src));
4764
4765 ins_pipe(ialu_imm);
4766 %}
4767
4768 // Load Pointer Constant
4769 instruct loadConP(iRegPNoSp dst, immP con)
4770 %{
4771 match(Set dst con);
4772
4773 ins_cost(ALU_COST);
4774 format %{ "mv $dst, $con\t# ptr, #@loadConP" %}
4775
4776 ins_encode(riscv_enc_mov_p(dst, con));
4777
4778 ins_pipe(ialu_imm);
4779 %}
4780
4781 // Load Null Pointer Constant
4782 instruct loadConP0(iRegPNoSp dst, immP0 con)
4783 %{
4784 match(Set dst con);
4785
4786 ins_cost(ALU_COST);
4787 format %{ "mv $dst, $con\t# null pointer, #@loadConP0" %}
4788
4789 ins_encode(riscv_enc_mov_zero(dst));
4790
4791 ins_pipe(ialu_imm);
4792 %}
4793
4794 // Load Pointer Constant One
4795 instruct loadConP1(iRegPNoSp dst, immP_1 con)
4796 %{
4797 match(Set dst con);
4798
4799 ins_cost(ALU_COST);
4800 format %{ "mv $dst, $con\t# load ptr constant one, #@loadConP1" %}
4801
4802 ins_encode(riscv_enc_mov_p1(dst));
4803
4804 ins_pipe(ialu_imm);
4805 %}
4806
4807 // Load Narrow Pointer Constant
4808 instruct loadConN(iRegNNoSp dst, immN con)
4809 %{
4810 match(Set dst con);
4811
4812 ins_cost(ALU_COST * 4);
4813 format %{ "mv $dst, $con\t# compressed ptr, #@loadConN" %}
4814
4815 ins_encode(riscv_enc_mov_n(dst, con));
4816
4817 ins_pipe(ialu_imm);
4818 %}
4819
4820 // Load Narrow Null Pointer Constant
4821 instruct loadConN0(iRegNNoSp dst, immN0 con)
4822 %{
4823 match(Set dst con);
4824
4825 ins_cost(ALU_COST);
4826 format %{ "mv $dst, $con\t# compressed null pointer, #@loadConN0" %}
4827
4828 ins_encode(riscv_enc_mov_zero(dst));
4829
4830 ins_pipe(ialu_imm);
4831 %}
4832
4833 // Load Narrow Klass Constant
4834 instruct loadConNKlass(iRegNNoSp dst, immNKlass con)
4835 %{
4836 match(Set dst con);
4837
4838 ins_cost(ALU_COST * 6);
4839 format %{ "mv $dst, $con\t# compressed klass ptr, #@loadConNKlass" %}
4840
4841 ins_encode(riscv_enc_mov_nk(dst, con));
4842
4843 ins_pipe(ialu_imm);
4844 %}
4845
4846 // Load Half Float Constant
4847 instruct loadConH(fRegF dst, immH con) %{
4848 match(Set dst con);
4849
4850 ins_cost(LOAD_COST);
4851 format %{
4852 "flh $dst, [$constantaddress]\t# load from constant table: float=$con, #@loadConH"
4853 %}
4854
4855 ins_encode %{
4856 assert(UseZfh || UseZfhmin, "must");
4857 if (MacroAssembler::can_hf_imm_load($con$$constant)) {
4858 __ fli_h(as_FloatRegister($dst$$reg), $con$$constant);
4859 } else {
4860 __ flh(as_FloatRegister($dst$$reg), $constantaddress($con));
4861 }
4862 %}
4863
4864 ins_pipe(fp_load_constant_s);
4865 %}
4866
4867 instruct loadConH0(fRegF dst, immH0 con) %{
4868 match(Set dst con);
4869
4870 ins_cost(XFER_COST);
4871
4872 format %{ "fmv.h.x $dst, zr\t# float, #@loadConH0" %}
4873
4874 ins_encode %{
4875 assert(UseZfh || UseZfhmin, "must");
4876 __ fmv_h_x(as_FloatRegister($dst$$reg), zr);
4877 %}
4878
4879 ins_pipe(fp_load_constant_s);
4880 %}
4881
4882 // Load Float Constant
4883 instruct loadConF(fRegF dst, immF con) %{
4884 match(Set dst con);
4885
4886 ins_cost(LOAD_COST);
4887 format %{
4888 "flw $dst, [$constantaddress]\t# load from constant table: float=$con, #@loadConF"
4889 %}
4890
4891 ins_encode %{
4892 if (MacroAssembler::can_fp_imm_load($con$$constant)) {
4893 __ fli_s(as_FloatRegister($dst$$reg), $con$$constant);
4894 } else {
4895 __ flw(as_FloatRegister($dst$$reg), $constantaddress($con));
4896 }
4897 %}
4898
4899 ins_pipe(fp_load_constant_s);
4900 %}
4901
4902 instruct loadConF0(fRegF dst, immF0 con) %{
4903 match(Set dst con);
4904
4905 ins_cost(XFER_COST);
4906
4907 format %{ "fmv.w.x $dst, zr\t# float, #@loadConF0" %}
4908
4909 ins_encode %{
4910 __ fmv_w_x(as_FloatRegister($dst$$reg), zr);
4911 %}
4912
4913 ins_pipe(fp_load_constant_s);
4914 %}
4915
4916 // Load Double Constant
4917 instruct loadConD(fRegD dst, immD con) %{
4918 match(Set dst con);
4919
4920 ins_cost(LOAD_COST);
4921 format %{
4922 "fld $dst, [$constantaddress]\t# load from constant table: double=$con, #@loadConD"
4923 %}
4924
4925 ins_encode %{
4926 if (MacroAssembler::can_dp_imm_load($con$$constant)) {
4927 __ fli_d(as_FloatRegister($dst$$reg), $con$$constant);
4928 } else {
4929 __ fld(as_FloatRegister($dst$$reg), $constantaddress($con));
4930 }
4931 %}
4932
4933 ins_pipe(fp_load_constant_d);
4934 %}
4935
4936 instruct loadConD0(fRegD dst, immD0 con) %{
4937 match(Set dst con);
4938
4939 ins_cost(XFER_COST);
4940
4941 format %{ "fmv.d.x $dst, zr\t# double, #@loadConD0" %}
4942
4943 ins_encode %{
4944 __ fmv_d_x(as_FloatRegister($dst$$reg), zr);
4945 %}
4946
4947 ins_pipe(fp_load_constant_d);
4948 %}
4949
4950 // Store Byte
4951 instruct storeB(iRegIorL2I src, memory mem)
4952 %{
4953 match(Set mem (StoreB mem src));
4954
4955 ins_cost(STORE_COST);
4956 format %{ "sb $src, $mem\t# byte, #@storeB" %}
4957
4958 ins_encode %{
4959 __ sb(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
4960 %}
4961
4962 ins_pipe(istore_reg_mem);
4963 %}
4964
4965 instruct storeimmB0(immI0 zero, memory mem)
4966 %{
4967 match(Set mem (StoreB mem zero));
4968
4969 ins_cost(STORE_COST);
4970 format %{ "sb zr, $mem\t# byte, #@storeimmB0" %}
4971
4972 ins_encode %{
4973 __ sb(zr, Address(as_Register($mem$$base), $mem$$disp));
4974 %}
4975
4976 ins_pipe(istore_mem);
4977 %}
4978
4979 // Store Char/Short
4980 instruct storeC(iRegIorL2I src, memory mem)
4981 %{
4982 match(Set mem (StoreC mem src));
4983
4984 ins_cost(STORE_COST);
4985 format %{ "sh $src, $mem\t# short, #@storeC" %}
4986
4987 ins_encode %{
4988 __ sh(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
4989 %}
4990
4991 ins_pipe(istore_reg_mem);
4992 %}
4993
4994 instruct storeimmC0(immI0 zero, memory mem)
4995 %{
4996 match(Set mem (StoreC mem zero));
4997
4998 ins_cost(STORE_COST);
4999 format %{ "sh zr, $mem\t# short, #@storeimmC0" %}
5000
5001 ins_encode %{
5002 __ sh(zr, Address(as_Register($mem$$base), $mem$$disp));
5003 %}
5004
5005 ins_pipe(istore_mem);
5006 %}
5007
5008 // Store Integer
5009 instruct storeI(iRegIorL2I src, memory mem)
5010 %{
5011 match(Set mem(StoreI mem src));
5012
5013 ins_cost(STORE_COST);
5014 format %{ "sw $src, $mem\t# int, #@storeI" %}
5015
5016 ins_encode %{
5017 __ sw(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5018 %}
5019
5020 ins_pipe(istore_reg_mem);
5021 %}
5022
5023 instruct storeimmI0(immI0 zero, memory mem)
5024 %{
5025 match(Set mem(StoreI mem zero));
5026
5027 ins_cost(STORE_COST);
5028 format %{ "sw zr, $mem\t# int, #@storeimmI0" %}
5029
5030 ins_encode %{
5031 __ sw(zr, Address(as_Register($mem$$base), $mem$$disp));
5032 %}
5033
5034 ins_pipe(istore_mem);
5035 %}
5036
5037 // Store Long (64 bit signed)
5038 instruct storeL(iRegL src, memory mem)
5039 %{
5040 match(Set mem (StoreL mem src));
5041
5042 ins_cost(STORE_COST);
5043 format %{ "sd $src, $mem\t# long, #@storeL" %}
5044
5045 ins_encode %{
5046 __ sd(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5047 %}
5048
5049 ins_pipe(istore_reg_mem);
5050 %}
5051
5052 // Store Long (64 bit signed)
5053 instruct storeimmL0(immL0 zero, memory mem)
5054 %{
5055 match(Set mem (StoreL mem zero));
5056
5057 ins_cost(STORE_COST);
5058 format %{ "sd zr, $mem\t# long, #@storeimmL0" %}
5059
5060 ins_encode %{
5061 __ sd(zr, Address(as_Register($mem$$base), $mem$$disp));
5062 %}
5063
5064 ins_pipe(istore_mem);
5065 %}
5066
5067 // Store Pointer
5068 instruct storeP(iRegP src, memory mem)
5069 %{
5070 match(Set mem (StoreP mem src));
5071 predicate(n->as_Store()->barrier_data() == 0);
5072
5073 ins_cost(STORE_COST);
5074 format %{ "sd $src, $mem\t# ptr, #@storeP" %}
5075
5076 ins_encode %{
5077 __ sd(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5078 %}
5079
5080 ins_pipe(istore_reg_mem);
5081 %}
5082
5083 // Store Pointer
5084 instruct storeimmP0(immP0 zero, memory mem)
5085 %{
5086 match(Set mem (StoreP mem zero));
5087 predicate(n->as_Store()->barrier_data() == 0);
5088
5089 ins_cost(STORE_COST);
5090 format %{ "sd zr, $mem\t# ptr, #@storeimmP0" %}
5091
5092 ins_encode %{
5093 __ sd(zr, Address(as_Register($mem$$base), $mem$$disp));
5094 %}
5095
5096 ins_pipe(istore_mem);
5097 %}
5098
5099 // Store Compressed Pointer
5100 instruct storeN(iRegN src, memory mem)
5101 %{
5102 predicate(n->as_Store()->barrier_data() == 0);
5103 match(Set mem (StoreN mem src));
5104
5105 ins_cost(STORE_COST);
5106 format %{ "sw $src, $mem\t# compressed ptr, #@storeN" %}
5107
5108 ins_encode %{
5109 __ sw(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5110 %}
5111
5112 ins_pipe(istore_reg_mem);
5113 %}
5114
5115 instruct storeImmN0(immN0 zero, memory mem)
5116 %{
5117 predicate(n->as_Store()->barrier_data() == 0);
5118 match(Set mem (StoreN mem zero));
5119
5120 ins_cost(STORE_COST);
5121 format %{ "sw zr, $mem\t# compressed ptr, #@storeImmN0" %}
5122
5123 ins_encode %{
5124 __ sw(zr, Address(as_Register($mem$$base), $mem$$disp));
5125 %}
5126
5127 ins_pipe(istore_reg_mem);
5128 %}
5129
5130 // Store Float
5131 instruct storeF(fRegF src, memory mem)
5132 %{
5133 match(Set mem (StoreF mem src));
5134
5135 ins_cost(STORE_COST);
5136 format %{ "fsw $src, $mem\t# float, #@storeF" %}
5137
5138 ins_encode %{
5139 __ fsw(as_FloatRegister($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5140 %}
5141
5142 ins_pipe(fp_store_reg_s);
5143 %}
5144
5145 // Store Double
5146 instruct storeD(fRegD src, memory mem)
5147 %{
5148 match(Set mem (StoreD mem src));
5149
5150 ins_cost(STORE_COST);
5151 format %{ "fsd $src, $mem\t# double, #@storeD" %}
5152
5153 ins_encode %{
5154 __ fsd(as_FloatRegister($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5155 %}
5156
5157 ins_pipe(fp_store_reg_d);
5158 %}
5159
5160 // Store Compressed Klass Pointer
5161 instruct storeNKlass(iRegN src, memory mem)
5162 %{
5163 match(Set mem (StoreNKlass mem src));
5164
5165 ins_cost(STORE_COST);
5166 format %{ "sw $src, $mem\t# compressed klass ptr, #@storeNKlass" %}
5167
5168 ins_encode %{
5169 __ sw(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5170 %}
5171
5172 ins_pipe(istore_reg_mem);
5173 %}
5174
5175 // ============================================================================
5176 // Prefetch instructions
5177 // Must be safe to execute with invalid address (cannot fault).
5178
5179 instruct prefetchalloc( memory mem ) %{
5180 predicate(UseZicbop);
5181 match(PrefetchAllocation mem);
5182
5183 ins_cost(ALU_COST * 1);
5184 format %{ "prefetch_w $mem\t# Prefetch for write" %}
5185
5186 ins_encode %{
5187 if (Assembler::is_simm12($mem$$disp)) {
5188 if (($mem$$disp & 0x1f) == 0) {
5189 __ prefetch_w(as_Register($mem$$base), $mem$$disp);
5190 } else {
5191 __ addi(t0, as_Register($mem$$base), $mem$$disp);
5192 __ prefetch_w(t0, 0);
5193 }
5194 } else {
5195 __ mv(t0, $mem$$disp);
5196 __ add(t0, as_Register($mem$$base), t0);
5197 __ prefetch_w(t0, 0);
5198 }
5199 %}
5200
5201 ins_pipe(iload_prefetch);
5202 %}
5203
5204 // ============================================================================
5205 // Atomic operation instructions
5206 //
5207
5208 // standard CompareAndSwapX when we are using barriers
5209 // these have higher priority than the rules selected by a predicate
5210 instruct compareAndSwapB_narrow(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5211 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5212 %{
5213 predicate(!UseZabha || !UseZacas);
5214
5215 match(Set res (CompareAndSwapB mem (Binary oldval newval)));
5216
5217 ins_cost(2 * VOLATILE_REF_COST);
5218
5219 effect(TEMP_DEF res, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3, KILL cr);
5220
5221 format %{
5222 "cmpxchg $mem, $oldval, $newval\t# (byte) if $mem == $oldval then $mem <-- $newval\n\t"
5223 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapB_narrow"
5224 %}
5225
5226 ins_encode %{
5227 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5228 Assembler::relaxed /* acquire */, Assembler::rl /* release */, $res$$Register,
5229 true /* result as bool */, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5230 %}
5231
5232 ins_pipe(pipe_slow);
5233 %}
5234
5235 instruct compareAndSwapB(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5236 %{
5237 predicate(UseZabha && UseZacas);
5238
5239 match(Set res (CompareAndSwapB mem (Binary oldval newval)));
5240
5241 ins_cost(2 * VOLATILE_REF_COST);
5242
5243 format %{
5244 "cmpxchg $mem, $oldval, $newval\t# (byte) if $mem == $oldval then $mem <-- $newval\n\t"
5245 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapB"
5246 %}
5247
5248 ins_encode %{
5249 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5250 Assembler::relaxed /* acquire */, Assembler::rl /* release */, $res$$Register,
5251 true /* result as bool */);
5252 %}
5253
5254 ins_pipe(pipe_slow);
5255 %}
5256
5257 instruct compareAndSwapS_narrow(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5258 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5259 %{
5260 predicate(!UseZabha || !UseZacas);
5261
5262 match(Set res (CompareAndSwapS mem (Binary oldval newval)));
5263
5264 ins_cost(2 * VOLATILE_REF_COST);
5265
5266 effect(TEMP_DEF res, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3, KILL cr);
5267
5268 format %{
5269 "cmpxchg $mem, $oldval, $newval\t# (short) if $mem == $oldval then $mem <-- $newval\n\t"
5270 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapS_narrow"
5271 %}
5272
5273 ins_encode %{
5274 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5275 Assembler::relaxed /* acquire */, Assembler::rl /* release */, $res$$Register,
5276 true /* result as bool */, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5277 %}
5278
5279 ins_pipe(pipe_slow);
5280 %}
5281
5282 instruct compareAndSwapS(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5283 %{
5284 predicate(UseZabha && UseZacas);
5285
5286 match(Set res (CompareAndSwapS mem (Binary oldval newval)));
5287
5288 ins_cost(2 * VOLATILE_REF_COST);
5289
5290 format %{
5291 "cmpxchg $mem, $oldval, $newval\t# (short) if $mem == $oldval then $mem <-- $newval\n\t"
5292 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapS"
5293 %}
5294
5295 ins_encode %{
5296 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5297 Assembler::relaxed /* acquire */, Assembler::rl /* release */, $res$$Register,
5298 true /* result as bool */);
5299 %}
5300
5301 ins_pipe(pipe_slow);
5302 %}
5303
5304 instruct compareAndSwapI(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5305 %{
5306 match(Set res (CompareAndSwapI mem (Binary oldval newval)));
5307
5308 ins_cost(2 * VOLATILE_REF_COST);
5309
5310 format %{
5311 "cmpxchg $mem, $oldval, $newval\t# (int) if $mem == $oldval then $mem <-- $newval\n\t"
5312 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapI"
5313 %}
5314
5315 ins_encode %{
5316 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
5317 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
5318 /*result as bool*/ true);
5319 %}
5320
5321 ins_pipe(pipe_slow);
5322 %}
5323
5324 instruct compareAndSwapL(iRegINoSp res, indirect mem, iRegL oldval, iRegL newval)
5325 %{
5326 match(Set res (CompareAndSwapL mem (Binary oldval newval)));
5327
5328 ins_cost(2 * VOLATILE_REF_COST);
5329
5330 format %{
5331 "cmpxchg $mem, $oldval, $newval\t# (long) if $mem == $oldval then $mem <-- $newval\n\t"
5332 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapL"
5333 %}
5334
5335 ins_encode %{
5336 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5337 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
5338 /*result as bool*/ true);
5339 %}
5340
5341 ins_pipe(pipe_slow);
5342 %}
5343
5344 instruct compareAndSwapP(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval)
5345 %{
5346 predicate(n->as_LoadStore()->barrier_data() == 0);
5347
5348 match(Set res (CompareAndSwapP mem (Binary oldval newval)));
5349
5350 ins_cost(2 * VOLATILE_REF_COST);
5351
5352 format %{
5353 "cmpxchg $mem, $oldval, $newval\t# (ptr) if $mem == $oldval then $mem <-- $newval\n\t"
5354 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapP"
5355 %}
5356
5357 ins_encode %{
5358 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5359 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
5360 /*result as bool*/ true);
5361 %}
5362
5363 ins_pipe(pipe_slow);
5364 %}
5365
5366 instruct compareAndSwapN(iRegINoSp res, indirect mem, iRegN oldval, iRegN newval)
5367 %{
5368 predicate(n->as_LoadStore()->barrier_data() == 0);
5369
5370 match(Set res (CompareAndSwapN mem (Binary oldval newval)));
5371
5372 ins_cost(2 * VOLATILE_REF_COST);
5373
5374 format %{
5375 "cmpxchg $mem, $oldval, $newval\t# (narrow oop) if $mem == $oldval then $mem <-- $newval\n\t"
5376 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapN"
5377 %}
5378
5379 ins_encode %{
5380 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
5381 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
5382 /*result as bool*/ true);
5383 %}
5384
5385 ins_pipe(pipe_slow);
5386 %}
5387
5388 // alternative CompareAndSwapX when we are eliding barriers
5389 instruct compareAndSwapBAcq_narrow(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5390 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5391 %{
5392 predicate((!UseZabha || !UseZacas) && needs_acquiring_load_reserved(n));
5393
5394 match(Set res (CompareAndSwapB mem (Binary oldval newval)));
5395
5396 ins_cost(2 * VOLATILE_REF_COST);
5397
5398 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5399
5400 format %{
5401 "cmpxchg_acq $mem, $oldval, $newval\t# (byte) if $mem == $oldval then $mem <-- $newval\n\t"
5402 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapBAcq_narrow"
5403 %}
5404
5405 ins_encode %{
5406 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5407 Assembler::aq /* acquire */, Assembler::rl /* release */, $res$$Register,
5408 true /* result as bool */, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5409 %}
5410
5411 ins_pipe(pipe_slow);
5412 %}
5413
5414 instruct compareAndSwapBAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5415 %{
5416 predicate((UseZabha && UseZacas) && needs_acquiring_load_reserved(n));
5417
5418 match(Set res (CompareAndSwapB mem (Binary oldval newval)));
5419
5420 ins_cost(2 * VOLATILE_REF_COST);
5421
5422 format %{
5423 "cmpxchg $mem, $oldval, $newval\t# (byte) if $mem == $oldval then $mem <-- $newval\n\t"
5424 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapBAcq"
5425 %}
5426
5427 ins_encode %{
5428 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5429 Assembler::aq /* acquire */, Assembler::rl /* release */, $res$$Register,
5430 true /* result as bool */);
5431 %}
5432
5433 ins_pipe(pipe_slow);
5434 %}
5435
5436 instruct compareAndSwapSAcq_narrow(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5437 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5438 %{
5439 predicate((!UseZabha || !UseZacas) && needs_acquiring_load_reserved(n));
5440
5441 match(Set res (CompareAndSwapS mem (Binary oldval newval)));
5442
5443 ins_cost(2 * VOLATILE_REF_COST);
5444
5445 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5446
5447 format %{
5448 "cmpxchg_acq $mem, $oldval, $newval\t# (short) if $mem == $oldval then $mem <-- $newval\n\t"
5449 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapSAcq_narrow"
5450 %}
5451
5452 ins_encode %{
5453 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5454 Assembler::aq /* acquire */, Assembler::rl /* release */, $res$$Register,
5455 true /* result as bool */, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5456 %}
5457
5458 ins_pipe(pipe_slow);
5459 %}
5460
5461 instruct compareAndSwapSAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5462 %{
5463 predicate((UseZabha && UseZacas) && needs_acquiring_load_reserved(n));
5464
5465 match(Set res (CompareAndSwapS mem (Binary oldval newval)));
5466
5467 ins_cost(2 * VOLATILE_REF_COST);
5468
5469 format %{
5470 "cmpxchg $mem, $oldval, $newval\t# (short) if $mem == $oldval then $mem <-- $newval\n\t"
5471 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapSAcq"
5472 %}
5473
5474 ins_encode %{
5475 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5476 Assembler::aq /* acquire */, Assembler::rl /* release */, $res$$Register,
5477 true /* result as bool */);
5478 %}
5479
5480 ins_pipe(pipe_slow);
5481 %}
5482
5483 instruct compareAndSwapIAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5484 %{
5485 predicate(needs_acquiring_load_reserved(n));
5486
5487 match(Set res (CompareAndSwapI mem (Binary oldval newval)));
5488
5489 ins_cost(2 * VOLATILE_REF_COST);
5490
5491 format %{
5492 "cmpxchg_acq $mem, $oldval, $newval\t# (int) if $mem == $oldval then $mem <-- $newval\n\t"
5493 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapIAcq"
5494 %}
5495
5496 ins_encode %{
5497 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
5498 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
5499 /*result as bool*/ true);
5500 %}
5501
5502 ins_pipe(pipe_slow);
5503 %}
5504
5505 instruct compareAndSwapLAcq(iRegINoSp res, indirect mem, iRegL oldval, iRegL newval)
5506 %{
5507 predicate(needs_acquiring_load_reserved(n));
5508
5509 match(Set res (CompareAndSwapL mem (Binary oldval newval)));
5510
5511 ins_cost(2 * VOLATILE_REF_COST);
5512
5513 format %{
5514 "cmpxchg_acq $mem, $oldval, $newval\t# (long) if $mem == $oldval then $mem <-- $newval\n\t"
5515 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapLAcq"
5516 %}
5517
5518 ins_encode %{
5519 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5520 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
5521 /*result as bool*/ true);
5522 %}
5523
5524 ins_pipe(pipe_slow);
5525 %}
5526
5527 instruct compareAndSwapPAcq(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval)
5528 %{
5529 predicate(needs_acquiring_load_reserved(n) && (n->as_LoadStore()->barrier_data() == 0));
5530
5531 match(Set res (CompareAndSwapP mem (Binary oldval newval)));
5532
5533 ins_cost(2 * VOLATILE_REF_COST);
5534
5535 format %{
5536 "cmpxchg_acq $mem, $oldval, $newval\t# (ptr) if $mem == $oldval then $mem <-- $newval\n\t"
5537 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapPAcq"
5538 %}
5539
5540 ins_encode %{
5541 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5542 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
5543 /*result as bool*/ true);
5544 %}
5545
5546 ins_pipe(pipe_slow);
5547 %}
5548
5549 instruct compareAndSwapNAcq(iRegINoSp res, indirect mem, iRegN oldval, iRegN newval)
5550 %{
5551 predicate(needs_acquiring_load_reserved(n) && n->as_LoadStore()->barrier_data() == 0);
5552
5553 match(Set res (CompareAndSwapN mem (Binary oldval newval)));
5554
5555 ins_cost(2 * VOLATILE_REF_COST);
5556
5557 format %{
5558 "cmpxchg_acq $mem, $oldval, $newval\t# (narrow oop) if $mem == $oldval then $mem <-- $newval\n\t"
5559 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapNAcq"
5560 %}
5561
5562 ins_encode %{
5563 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
5564 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
5565 /*result as bool*/ true);
5566 %}
5567
5568 ins_pipe(pipe_slow);
5569 %}
5570
5571 // Sundry CAS operations. Note that release is always true,
5572 // regardless of the memory ordering of the CAS. This is because we
5573 // need the volatile case to be sequentially consistent but there is
5574 // no trailing StoreLoad barrier emitted by C2. Unfortunately we
5575 // can't check the type of memory ordering here, so we always emit a
5576 // sc_d(w) with rl bit set.
5577 instruct compareAndExchangeB_narrow(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5578 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5579 %{
5580 predicate(!UseZabha || !UseZacas);
5581
5582 match(Set res (CompareAndExchangeB mem (Binary oldval newval)));
5583
5584 ins_cost(2 * VOLATILE_REF_COST);
5585
5586 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5587
5588 format %{
5589 "cmpxchg $res = $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeB_narrow"
5590 %}
5591
5592 ins_encode %{
5593 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5594 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
5595 /*result_as_bool*/ false, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5596 %}
5597
5598 ins_pipe(pipe_slow);
5599 %}
5600
5601 instruct compareAndExchangeB(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5602 %{
5603 predicate(UseZabha && UseZacas);
5604
5605 match(Set res (CompareAndExchangeB mem (Binary oldval newval)));
5606
5607 ins_cost(2 * VOLATILE_REF_COST);
5608
5609 format %{
5610 "cmpxchg $res = $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeB"
5611 %}
5612
5613 ins_encode %{
5614 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5615 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5616 %}
5617
5618 ins_pipe(pipe_slow);
5619 %}
5620
5621 instruct compareAndExchangeS_narrow(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5622 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5623 %{
5624 predicate(!UseZabha || !UseZacas);
5625
5626 match(Set res (CompareAndExchangeS mem (Binary oldval newval)));
5627
5628 ins_cost(2 * VOLATILE_REF_COST);
5629
5630 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5631
5632 format %{
5633 "cmpxchg $res = $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeS_narrow"
5634 %}
5635
5636 ins_encode %{
5637 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5638 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
5639 /*result_as_bool*/ false, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5640 %}
5641
5642 ins_pipe(pipe_slow);
5643 %}
5644
5645 instruct compareAndExchangeS(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5646 %{
5647 predicate(UseZabha && UseZacas);
5648
5649 match(Set res (CompareAndExchangeS mem (Binary oldval newval)));
5650
5651 ins_cost(2 * VOLATILE_REF_COST);
5652
5653 format %{
5654 "cmpxchg $res = $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeS"
5655 %}
5656
5657 ins_encode %{
5658 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5659 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5660 %}
5661
5662 ins_pipe(pipe_slow);
5663 %}
5664
5665 instruct compareAndExchangeI(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5666 %{
5667 match(Set res (CompareAndExchangeI mem (Binary oldval newval)));
5668
5669 ins_cost(2 * VOLATILE_REF_COST);
5670
5671 format %{
5672 "cmpxchg $res = $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeI"
5673 %}
5674
5675 ins_encode %{
5676 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
5677 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5678 %}
5679
5680 ins_pipe(pipe_slow);
5681 %}
5682
5683 instruct compareAndExchangeL(iRegLNoSp res, indirect mem, iRegL oldval, iRegL newval)
5684 %{
5685 match(Set res (CompareAndExchangeL mem (Binary oldval newval)));
5686
5687 ins_cost(2 * VOLATILE_REF_COST);
5688
5689 format %{
5690 "cmpxchg $res = $mem, $oldval, $newval\t# (long, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeL"
5691 %}
5692
5693 ins_encode %{
5694 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5695 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5696 %}
5697
5698 ins_pipe(pipe_slow);
5699 %}
5700
5701 instruct compareAndExchangeN(iRegNNoSp res, indirect mem, iRegN oldval, iRegN newval)
5702 %{
5703 predicate(n->as_LoadStore()->barrier_data() == 0);
5704
5705 match(Set res (CompareAndExchangeN mem (Binary oldval newval)));
5706
5707 ins_cost(2 * VOLATILE_REF_COST);
5708
5709 format %{
5710 "cmpxchg $res = $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeN"
5711 %}
5712
5713 ins_encode %{
5714 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
5715 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5716 %}
5717
5718 ins_pipe(pipe_slow);
5719 %}
5720
5721 instruct compareAndExchangeP(iRegPNoSp res, indirect mem, iRegP oldval, iRegP newval)
5722 %{
5723 predicate(n->as_LoadStore()->barrier_data() == 0);
5724
5725 match(Set res (CompareAndExchangeP mem (Binary oldval newval)));
5726
5727 ins_cost(2 * VOLATILE_REF_COST);
5728
5729 format %{
5730 "cmpxchg $res = $mem, $oldval, $newval\t# (ptr, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeP"
5731 %}
5732
5733 ins_encode %{
5734 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5735 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5736 %}
5737
5738 ins_pipe(pipe_slow);
5739 %}
5740
5741 instruct compareAndExchangeBAcq_narrow(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5742 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5743 %{
5744 predicate((!UseZabha || !UseZacas) && needs_acquiring_load_reserved(n));
5745
5746 match(Set res (CompareAndExchangeB mem (Binary oldval newval)));
5747
5748 ins_cost(2 * VOLATILE_REF_COST);
5749
5750 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5751
5752 format %{
5753 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeBAcq_narrow"
5754 %}
5755
5756 ins_encode %{
5757 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5758 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
5759 /*result_as_bool*/ false, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5760 %}
5761
5762 ins_pipe(pipe_slow);
5763 %}
5764
5765 instruct compareAndExchangeBAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5766 %{
5767 predicate((UseZabha && UseZacas) && needs_acquiring_load_reserved(n));
5768
5769 match(Set res (CompareAndExchangeB mem (Binary oldval newval)));
5770
5771 ins_cost(2 * VOLATILE_REF_COST);
5772
5773 format %{
5774 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeBAcq"
5775 %}
5776
5777 ins_encode %{
5778 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5779 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
5780 %}
5781
5782 ins_pipe(pipe_slow);
5783 %}
5784
5785 instruct compareAndExchangeSAcq_narrow(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5786 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5787 %{
5788 predicate((!UseZabha || !UseZacas) && needs_acquiring_load_reserved(n));
5789
5790 match(Set res (CompareAndExchangeS mem (Binary oldval newval)));
5791
5792 ins_cost(2 * VOLATILE_REF_COST);
5793
5794 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5795
5796 format %{
5797 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeSAcq_narrow"
5798 %}
5799
5800 ins_encode %{
5801 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5802 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
5803 /*result_as_bool*/ false, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5804 %}
5805
5806 ins_pipe(pipe_slow);
5807 %}
5808
5809 instruct compareAndExchangeSAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5810 %{
5811 predicate((UseZabha && UseZacas) && needs_acquiring_load_reserved(n));
5812
5813 match(Set res (CompareAndExchangeS mem (Binary oldval newval)));
5814
5815 ins_cost(2 * VOLATILE_REF_COST);
5816
5817 format %{
5818 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeSAcq"
5819 %}
5820
5821 ins_encode %{
5822 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5823 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
5824 %}
5825
5826 ins_pipe(pipe_slow);
5827 %}
5828
5829 instruct compareAndExchangeIAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5830 %{
5831 predicate(needs_acquiring_load_reserved(n));
5832
5833 match(Set res (CompareAndExchangeI mem (Binary oldval newval)));
5834
5835 ins_cost(2 * VOLATILE_REF_COST);
5836
5837 format %{
5838 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeIAcq"
5839 %}
5840
5841 ins_encode %{
5842 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
5843 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
5844 %}
5845
5846 ins_pipe(pipe_slow);
5847 %}
5848
5849 instruct compareAndExchangeLAcq(iRegLNoSp res, indirect mem, iRegL oldval, iRegL newval)
5850 %{
5851 predicate(needs_acquiring_load_reserved(n));
5852
5853 match(Set res (CompareAndExchangeL mem (Binary oldval newval)));
5854
5855 ins_cost(2 * VOLATILE_REF_COST);
5856
5857 format %{
5858 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (long, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeLAcq"
5859 %}
5860
5861 ins_encode %{
5862 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5863 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
5864 %}
5865
5866 ins_pipe(pipe_slow);
5867 %}
5868
5869 instruct compareAndExchangeNAcq(iRegNNoSp res, indirect mem, iRegN oldval, iRegN newval)
5870 %{
5871 predicate(needs_acquiring_load_reserved(n) && n->as_LoadStore()->barrier_data() == 0);
5872
5873 match(Set res (CompareAndExchangeN mem (Binary oldval newval)));
5874
5875 ins_cost(2 * VOLATILE_REF_COST);
5876
5877 format %{
5878 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeNAcq"
5879 %}
5880
5881 ins_encode %{
5882 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
5883 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
5884 %}
5885
5886 ins_pipe(pipe_slow);
5887 %}
5888
5889 instruct compareAndExchangePAcq(iRegPNoSp res, indirect mem, iRegP oldval, iRegP newval)
5890 %{
5891 predicate(needs_acquiring_load_reserved(n) && (n->as_LoadStore()->barrier_data() == 0));
5892
5893 match(Set res (CompareAndExchangeP mem (Binary oldval newval)));
5894
5895 ins_cost(2 * VOLATILE_REF_COST);
5896
5897 format %{
5898 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (ptr, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangePAcq"
5899 %}
5900
5901 ins_encode %{
5902 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5903 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
5904 %}
5905
5906 ins_pipe(pipe_slow);
5907 %}
5908
5909 instruct weakCompareAndSwapB_narrow(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5910 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5911 %{
5912 predicate(!UseZabha || !UseZacas);
5913
5914 match(Set res (WeakCompareAndSwapB mem (Binary oldval newval)));
5915
5916 ins_cost(2 * VOLATILE_REF_COST);
5917
5918 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5919
5920 format %{
5921 "weak_cmpxchg $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5922 "# $res == 1 when success, #@weakCompareAndSwapB_narrow"
5923 %}
5924
5925 ins_encode %{
5926 __ weak_cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5927 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
5928 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5929 %}
5930
5931 ins_pipe(pipe_slow);
5932 %}
5933
5934 instruct weakCompareAndSwapB(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5935 %{
5936 predicate(UseZabha && UseZacas);
5937
5938 match(Set res (WeakCompareAndSwapB mem (Binary oldval newval)));
5939
5940 ins_cost(2 * VOLATILE_REF_COST);
5941
5942 format %{
5943 "weak_cmpxchg $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5944 "# $res == 1 when success, #@weakCompareAndSwapB"
5945 %}
5946
5947 ins_encode %{
5948 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5949 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5950 %}
5951
5952 ins_pipe(pipe_slow);
5953 %}
5954
5955 instruct weakCompareAndSwapS_narrow(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5956 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5957 %{
5958 predicate(!UseZabha || !UseZacas);
5959
5960 match(Set res (WeakCompareAndSwapS mem (Binary oldval newval)));
5961
5962 ins_cost(2 * VOLATILE_REF_COST);
5963
5964 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5965
5966 format %{
5967 "weak_cmpxchg $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5968 "# $res == 1 when success, #@weakCompareAndSwapS_narrow"
5969 %}
5970
5971 ins_encode %{
5972 __ weak_cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5973 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
5974 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5975 %}
5976
5977 ins_pipe(pipe_slow);
5978 %}
5979
5980 instruct weakCompareAndSwapS(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5981 %{
5982 predicate(UseZabha && UseZacas);
5983
5984 match(Set res (WeakCompareAndSwapS mem (Binary oldval newval)));
5985
5986 ins_cost(2 * VOLATILE_REF_COST);
5987
5988 format %{
5989 "weak_cmpxchg $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5990 "# $res == 1 when success, #@weakCompareAndSwapS"
5991 %}
5992
5993 ins_encode %{
5994 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5995 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5996 %}
5997
5998 ins_pipe(pipe_slow);
5999 %}
6000
6001 instruct weakCompareAndSwapI(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
6002 %{
6003 match(Set res (WeakCompareAndSwapI mem (Binary oldval newval)));
6004
6005 ins_cost(2 * VOLATILE_REF_COST);
6006
6007 format %{
6008 "weak_cmpxchg $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval\n\t"
6009 "# $res == 1 when success, #@weakCompareAndSwapI"
6010 %}
6011
6012 ins_encode %{
6013 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
6014 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
6015 %}
6016
6017 ins_pipe(pipe_slow);
6018 %}
6019
6020 instruct weakCompareAndSwapL(iRegINoSp res, indirect mem, iRegL oldval, iRegL newval)
6021 %{
6022 match(Set res (WeakCompareAndSwapL mem (Binary oldval newval)));
6023
6024 ins_cost(2 * VOLATILE_REF_COST);
6025
6026 format %{
6027 "weak_cmpxchg $mem, $oldval, $newval\t# (long, weak) if $mem == $oldval then $mem <-- $newval\n\t"
6028 "# $res == 1 when success, #@weakCompareAndSwapL"
6029 %}
6030
6031 ins_encode %{
6032 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
6033 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
6034 %}
6035
6036 ins_pipe(pipe_slow);
6037 %}
6038
6039 instruct weakCompareAndSwapN(iRegINoSp res, indirect mem, iRegN oldval, iRegN newval)
6040 %{
6041 predicate(n->as_LoadStore()->barrier_data() == 0);
6042
6043 match(Set res (WeakCompareAndSwapN mem (Binary oldval newval)));
6044
6045 ins_cost(2 * VOLATILE_REF_COST);
6046
6047 format %{
6048 "weak_cmpxchg $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval\n\t"
6049 "# $res == 1 when success, #@weakCompareAndSwapN"
6050 %}
6051
6052 ins_encode %{
6053 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
6054 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
6055 %}
6056
6057 ins_pipe(pipe_slow);
6058 %}
6059
6060 instruct weakCompareAndSwapP(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval)
6061 %{
6062 predicate(n->as_LoadStore()->barrier_data() == 0);
6063
6064 match(Set res (WeakCompareAndSwapP mem (Binary oldval newval)));
6065
6066 ins_cost(2 * VOLATILE_REF_COST);
6067
6068 format %{
6069 "weak_cmpxchg $mem, $oldval, $newval\t# (ptr, weak) if $mem == $oldval then $mem <-- $newval\n\t"
6070 "# $res == 1 when success, #@weakCompareAndSwapP"
6071 %}
6072
6073 ins_encode %{
6074 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
6075 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
6076 %}
6077
6078 ins_pipe(pipe_slow);
6079 %}
6080
6081 instruct weakCompareAndSwapBAcq_narrow(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
6082 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
6083 %{
6084 predicate((!UseZabha || !UseZacas) && needs_acquiring_load_reserved(n));
6085
6086 match(Set res (WeakCompareAndSwapB mem (Binary oldval newval)));
6087
6088 ins_cost(2 * VOLATILE_REF_COST);
6089
6090 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
6091
6092 format %{
6093 "weak_cmpxchg_acq $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval\n\t"
6094 "# $res == 1 when success, #@weakCompareAndSwapBAcq_narrow"
6095 %}
6096
6097 ins_encode %{
6098 __ weak_cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
6099 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
6100 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
6101 %}
6102
6103 ins_pipe(pipe_slow);
6104 %}
6105
6106 instruct weakCompareAndSwapBAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
6107 %{
6108 predicate((UseZabha && UseZacas) && needs_acquiring_load_reserved(n));
6109
6110 match(Set res (WeakCompareAndSwapB mem (Binary oldval newval)));
6111
6112 ins_cost(2 * VOLATILE_REF_COST);
6113
6114 format %{
6115 "weak_cmpxchg_acq $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval\n\t"
6116 "# $res == 1 when success, #@weakCompareAndSwapBAcq"
6117 %}
6118
6119 ins_encode %{
6120 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
6121 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
6122 %}
6123
6124 ins_pipe(pipe_slow);
6125 %}
6126
6127 instruct weakCompareAndSwapSAcq_narrow(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
6128 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
6129 %{
6130 predicate((!UseZabha || !UseZacas) && needs_acquiring_load_reserved(n));
6131
6132 match(Set res (WeakCompareAndSwapS mem (Binary oldval newval)));
6133
6134 ins_cost(2 * VOLATILE_REF_COST);
6135
6136 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
6137
6138 format %{
6139 "weak_cmpxchg_acq $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval\n\t"
6140 "# $res == 1 when success, #@weakCompareAndSwapSAcq_narrow"
6141 %}
6142
6143 ins_encode %{
6144 __ weak_cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
6145 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
6146 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
6147 %}
6148
6149 ins_pipe(pipe_slow);
6150 %}
6151
6152 instruct weakCompareAndSwapSAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
6153 %{
6154 predicate((UseZabha && UseZacas) && needs_acquiring_load_reserved(n));
6155
6156 match(Set res (WeakCompareAndSwapS mem (Binary oldval newval)));
6157
6158 ins_cost(2 * VOLATILE_REF_COST);
6159
6160 format %{
6161 "weak_cmpxchg_acq $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval\n\t"
6162 "# $res == 1 when success, #@weakCompareAndSwapSAcq"
6163 %}
6164
6165 ins_encode %{
6166 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
6167 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
6168 %}
6169
6170 ins_pipe(pipe_slow);
6171 %}
6172
6173 instruct weakCompareAndSwapIAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
6174 %{
6175 predicate(needs_acquiring_load_reserved(n));
6176
6177 match(Set res (WeakCompareAndSwapI mem (Binary oldval newval)));
6178
6179 ins_cost(2 * VOLATILE_REF_COST);
6180
6181 format %{
6182 "weak_cmpxchg_acq $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval\n\t"
6183 "# $res == 1 when success, #@weakCompareAndSwapIAcq"
6184 %}
6185
6186 ins_encode %{
6187 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
6188 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
6189 %}
6190
6191 ins_pipe(pipe_slow);
6192 %}
6193
6194 instruct weakCompareAndSwapLAcq(iRegINoSp res, indirect mem, iRegL oldval, iRegL newval)
6195 %{
6196 predicate(needs_acquiring_load_reserved(n));
6197
6198 match(Set res (WeakCompareAndSwapL mem (Binary oldval newval)));
6199
6200 ins_cost(2 * VOLATILE_REF_COST);
6201
6202 format %{
6203 "weak_cmpxchg_acq $mem, $oldval, $newval\t# (long, weak) if $mem == $oldval then $mem <-- $newval\n\t"
6204 "# $res == 1 when success, #@weakCompareAndSwapLAcq"
6205 %}
6206
6207 ins_encode %{
6208 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
6209 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
6210 %}
6211
6212 ins_pipe(pipe_slow);
6213 %}
6214
6215 instruct weakCompareAndSwapNAcq(iRegINoSp res, indirect mem, iRegN oldval, iRegN newval)
6216 %{
6217 predicate(needs_acquiring_load_reserved(n) && n->as_LoadStore()->barrier_data() == 0);
6218
6219 match(Set res (WeakCompareAndSwapN mem (Binary oldval newval)));
6220
6221 ins_cost(2 * VOLATILE_REF_COST);
6222
6223 format %{
6224 "weak_cmpxchg_acq $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval\n\t"
6225 "# $res == 1 when success, #@weakCompareAndSwapNAcq"
6226 %}
6227
6228 ins_encode %{
6229 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
6230 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
6231 %}
6232
6233 ins_pipe(pipe_slow);
6234 %}
6235
6236 instruct weakCompareAndSwapPAcq(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval)
6237 %{
6238 predicate(needs_acquiring_load_reserved(n) && (n->as_LoadStore()->barrier_data() == 0));
6239
6240 match(Set res (WeakCompareAndSwapP mem (Binary oldval newval)));
6241
6242 ins_cost(2 * VOLATILE_REF_COST);
6243
6244 format %{
6245 "weak_cmpxchg_acq $mem, $oldval, $newval\t# (ptr, weak) if $mem == $oldval then $mem <-- $newval\n\t"
6246 "\t# $res == 1 when success, #@weakCompareAndSwapPAcq"
6247 %}
6248
6249 ins_encode %{
6250 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
6251 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
6252 %}
6253
6254 ins_pipe(pipe_slow);
6255 %}
6256
6257 instruct get_and_setI(indirect mem, iRegI newv, iRegINoSp prev)
6258 %{
6259 match(Set prev (GetAndSetI mem newv));
6260
6261 ins_cost(ALU_COST);
6262
6263 format %{ "atomic_xchgw $prev, $newv, [$mem]\t#@get_and_setI" %}
6264
6265 ins_encode %{
6266 __ atomic_xchgw($prev$$Register, $newv$$Register, as_Register($mem$$base));
6267 %}
6268
6269 ins_pipe(pipe_serial);
6270 %}
6271
6272 instruct get_and_setL(indirect mem, iRegL newv, iRegLNoSp prev)
6273 %{
6274 match(Set prev (GetAndSetL mem newv));
6275
6276 ins_cost(ALU_COST);
6277
6278 format %{ "atomic_xchg $prev, $newv, [$mem]\t#@get_and_setL" %}
6279
6280 ins_encode %{
6281 __ atomic_xchg($prev$$Register, $newv$$Register, as_Register($mem$$base));
6282 %}
6283
6284 ins_pipe(pipe_serial);
6285 %}
6286
6287 instruct get_and_setN(indirect mem, iRegN newv, iRegINoSp prev)
6288 %{
6289 predicate(n->as_LoadStore()->barrier_data() == 0);
6290
6291 match(Set prev (GetAndSetN mem newv));
6292
6293 ins_cost(ALU_COST);
6294
6295 format %{ "atomic_xchgwu $prev, $newv, [$mem]\t#@get_and_setN" %}
6296
6297 ins_encode %{
6298 __ atomic_xchgwu($prev$$Register, $newv$$Register, as_Register($mem$$base));
6299 %}
6300
6301 ins_pipe(pipe_serial);
6302 %}
6303
6304 instruct get_and_setP(indirect mem, iRegP newv, iRegPNoSp prev)
6305 %{
6306 predicate(n->as_LoadStore()->barrier_data() == 0);
6307 match(Set prev (GetAndSetP mem newv));
6308
6309 ins_cost(ALU_COST);
6310
6311 format %{ "atomic_xchg $prev, $newv, [$mem]\t#@get_and_setP" %}
6312
6313 ins_encode %{
6314 __ atomic_xchg($prev$$Register, $newv$$Register, as_Register($mem$$base));
6315 %}
6316
6317 ins_pipe(pipe_serial);
6318 %}
6319
6320 instruct get_and_setIAcq(indirect mem, iRegI newv, iRegINoSp prev)
6321 %{
6322 predicate(needs_acquiring_load_reserved(n));
6323
6324 match(Set prev (GetAndSetI mem newv));
6325
6326 ins_cost(ALU_COST);
6327
6328 format %{ "atomic_xchgw_acq $prev, $newv, [$mem]\t#@get_and_setIAcq" %}
6329
6330 ins_encode %{
6331 __ atomic_xchgalw($prev$$Register, $newv$$Register, as_Register($mem$$base));
6332 %}
6333
6334 ins_pipe(pipe_serial);
6335 %}
6336
6337 instruct get_and_setLAcq(indirect mem, iRegL newv, iRegLNoSp prev)
6338 %{
6339 predicate(needs_acquiring_load_reserved(n));
6340
6341 match(Set prev (GetAndSetL mem newv));
6342
6343 ins_cost(ALU_COST);
6344
6345 format %{ "atomic_xchg_acq $prev, $newv, [$mem]\t#@get_and_setLAcq" %}
6346
6347 ins_encode %{
6348 __ atomic_xchgal($prev$$Register, $newv$$Register, as_Register($mem$$base));
6349 %}
6350
6351 ins_pipe(pipe_serial);
6352 %}
6353
6354 instruct get_and_setNAcq(indirect mem, iRegN newv, iRegINoSp prev)
6355 %{
6356 predicate(needs_acquiring_load_reserved(n) && n->as_LoadStore()->barrier_data() == 0);
6357
6358 match(Set prev (GetAndSetN mem newv));
6359
6360 ins_cost(ALU_COST);
6361
6362 format %{ "atomic_xchgwu_acq $prev, $newv, [$mem]\t#@get_and_setNAcq" %}
6363
6364 ins_encode %{
6365 __ atomic_xchgalwu($prev$$Register, $newv$$Register, as_Register($mem$$base));
6366 %}
6367
6368 ins_pipe(pipe_serial);
6369 %}
6370
6371 instruct get_and_setPAcq(indirect mem, iRegP newv, iRegPNoSp prev)
6372 %{
6373 predicate(needs_acquiring_load_reserved(n) && (n->as_LoadStore()->barrier_data() == 0));
6374
6375 match(Set prev (GetAndSetP mem newv));
6376
6377 ins_cost(ALU_COST);
6378
6379 format %{ "atomic_xchg_acq $prev, $newv, [$mem]\t#@get_and_setPAcq" %}
6380
6381 ins_encode %{
6382 __ atomic_xchgal($prev$$Register, $newv$$Register, as_Register($mem$$base));
6383 %}
6384
6385 ins_pipe(pipe_serial);
6386 %}
6387
6388 instruct get_and_addL(indirect mem, iRegLNoSp newval, iRegL incr)
6389 %{
6390 match(Set newval (GetAndAddL mem incr));
6391
6392 ins_cost(ALU_COST);
6393
6394 format %{ "get_and_addL $newval, [$mem], $incr\t#@get_and_addL" %}
6395
6396 ins_encode %{
6397 __ atomic_add($newval$$Register, $incr$$Register, as_Register($mem$$base));
6398 %}
6399
6400 ins_pipe(pipe_serial);
6401 %}
6402
6403 instruct get_and_addL_no_res(indirect mem, Universe dummy, iRegL incr)
6404 %{
6405 predicate(n->as_LoadStore()->result_not_used());
6406
6407 match(Set dummy (GetAndAddL mem incr));
6408
6409 ins_cost(ALU_COST);
6410
6411 format %{ "get_and_addL [$mem], $incr\t#@get_and_addL_no_res" %}
6412
6413 ins_encode %{
6414 __ atomic_add(noreg, $incr$$Register, as_Register($mem$$base));
6415 %}
6416
6417 ins_pipe(pipe_serial);
6418 %}
6419
6420 instruct get_and_addLi(indirect mem, iRegLNoSp newval, immLAdd incr)
6421 %{
6422 match(Set newval (GetAndAddL mem incr));
6423
6424 ins_cost(ALU_COST);
6425
6426 format %{ "get_and_addL $newval, [$mem], $incr\t#@get_and_addLi" %}
6427
6428 ins_encode %{
6429 __ atomic_add($newval$$Register, $incr$$constant, as_Register($mem$$base));
6430 %}
6431
6432 ins_pipe(pipe_serial);
6433 %}
6434
6435 instruct get_and_addLi_no_res(indirect mem, Universe dummy, immLAdd incr)
6436 %{
6437 predicate(n->as_LoadStore()->result_not_used());
6438
6439 match(Set dummy (GetAndAddL mem incr));
6440
6441 ins_cost(ALU_COST);
6442
6443 format %{ "get_and_addL [$mem], $incr\t#@get_and_addLi_no_res" %}
6444
6445 ins_encode %{
6446 __ atomic_add(noreg, $incr$$constant, as_Register($mem$$base));
6447 %}
6448
6449 ins_pipe(pipe_serial);
6450 %}
6451
6452 instruct get_and_addI(indirect mem, iRegINoSp newval, iRegIorL2I incr)
6453 %{
6454 match(Set newval (GetAndAddI mem incr));
6455
6456 ins_cost(ALU_COST);
6457
6458 format %{ "get_and_addI $newval, [$mem], $incr\t#@get_and_addI" %}
6459
6460 ins_encode %{
6461 __ atomic_addw($newval$$Register, $incr$$Register, as_Register($mem$$base));
6462 %}
6463
6464 ins_pipe(pipe_serial);
6465 %}
6466
6467 instruct get_and_addI_no_res(indirect mem, Universe dummy, iRegIorL2I incr)
6468 %{
6469 predicate(n->as_LoadStore()->result_not_used());
6470
6471 match(Set dummy (GetAndAddI mem incr));
6472
6473 ins_cost(ALU_COST);
6474
6475 format %{ "get_and_addI [$mem], $incr\t#@get_and_addI_no_res" %}
6476
6477 ins_encode %{
6478 __ atomic_addw(noreg, $incr$$Register, as_Register($mem$$base));
6479 %}
6480
6481 ins_pipe(pipe_serial);
6482 %}
6483
6484 instruct get_and_addIi(indirect mem, iRegINoSp newval, immIAdd incr)
6485 %{
6486 match(Set newval (GetAndAddI mem incr));
6487
6488 ins_cost(ALU_COST);
6489
6490 format %{ "get_and_addI $newval, [$mem], $incr\t#@get_and_addIi" %}
6491
6492 ins_encode %{
6493 __ atomic_addw($newval$$Register, $incr$$constant, as_Register($mem$$base));
6494 %}
6495
6496 ins_pipe(pipe_serial);
6497 %}
6498
6499 instruct get_and_addIi_no_res(indirect mem, Universe dummy, immIAdd incr)
6500 %{
6501 predicate(n->as_LoadStore()->result_not_used());
6502
6503 match(Set dummy (GetAndAddI mem incr));
6504
6505 ins_cost(ALU_COST);
6506
6507 format %{ "get_and_addI [$mem], $incr\t#@get_and_addIi_no_res" %}
6508
6509 ins_encode %{
6510 __ atomic_addw(noreg, $incr$$constant, as_Register($mem$$base));
6511 %}
6512
6513 ins_pipe(pipe_serial);
6514 %}
6515
6516 instruct get_and_addLAcq(indirect mem, iRegLNoSp newval, iRegL incr)
6517 %{
6518 predicate(needs_acquiring_load_reserved(n));
6519
6520 match(Set newval (GetAndAddL mem incr));
6521
6522 ins_cost(ALU_COST);
6523
6524 format %{ "get_and_addL_acq $newval, [$mem], $incr\t#@get_and_addLAcq" %}
6525
6526 ins_encode %{
6527 __ atomic_addal($newval$$Register, $incr$$Register, as_Register($mem$$base));
6528 %}
6529
6530 ins_pipe(pipe_serial);
6531 %}
6532
6533 instruct get_and_addL_no_resAcq(indirect mem, Universe dummy, iRegL incr) %{
6534 predicate(n->as_LoadStore()->result_not_used() && needs_acquiring_load_reserved(n));
6535
6536 match(Set dummy (GetAndAddL mem incr));
6537
6538 ins_cost(ALU_COST);
6539
6540 format %{ "get_and_addL_acq [$mem], $incr\t#@get_and_addL_no_resAcq" %}
6541
6542 ins_encode %{
6543 __ atomic_addal(noreg, $incr$$Register, as_Register($mem$$base));
6544 %}
6545
6546 ins_pipe(pipe_serial);
6547 %}
6548
6549 instruct get_and_addLiAcq(indirect mem, iRegLNoSp newval, immLAdd incr)
6550 %{
6551 predicate(needs_acquiring_load_reserved(n));
6552
6553 match(Set newval (GetAndAddL mem incr));
6554
6555 ins_cost(ALU_COST);
6556
6557 format %{ "get_and_addL_acq $newval, [$mem], $incr\t#@get_and_addLiAcq" %}
6558
6559 ins_encode %{
6560 __ atomic_addal($newval$$Register, $incr$$constant, as_Register($mem$$base));
6561 %}
6562
6563 ins_pipe(pipe_serial);
6564 %}
6565
6566 instruct get_and_addLi_no_resAcq(indirect mem, Universe dummy, immLAdd incr)
6567 %{
6568 predicate(n->as_LoadStore()->result_not_used() && needs_acquiring_load_reserved(n));
6569
6570 match(Set dummy (GetAndAddL mem incr));
6571
6572 ins_cost(ALU_COST);
6573
6574 format %{ "get_and_addL_acq [$mem], $incr\t#@get_and_addLi_no_resAcq" %}
6575
6576 ins_encode %{
6577 __ atomic_addal(noreg, $incr$$constant, as_Register($mem$$base));
6578 %}
6579
6580 ins_pipe(pipe_serial);
6581 %}
6582
6583 instruct get_and_addIAcq(indirect mem, iRegINoSp newval, iRegIorL2I incr)
6584 %{
6585 predicate(needs_acquiring_load_reserved(n));
6586
6587 match(Set newval (GetAndAddI mem incr));
6588
6589 ins_cost(ALU_COST);
6590
6591 format %{ "get_and_addI_acq $newval, [$mem], $incr\t#@get_and_addIAcq" %}
6592
6593 ins_encode %{
6594 __ atomic_addalw($newval$$Register, $incr$$Register, as_Register($mem$$base));
6595 %}
6596
6597 ins_pipe(pipe_serial);
6598 %}
6599
6600 instruct get_and_addI_no_resAcq(indirect mem, Universe dummy, iRegIorL2I incr)
6601 %{
6602 predicate(n->as_LoadStore()->result_not_used() && needs_acquiring_load_reserved(n));
6603
6604 match(Set dummy (GetAndAddI mem incr));
6605
6606 ins_cost(ALU_COST);
6607
6608 format %{ "get_and_addI_acq [$mem], $incr\t#@get_and_addI_no_resAcq" %}
6609
6610 ins_encode %{
6611 __ atomic_addalw(noreg, $incr$$Register, as_Register($mem$$base));
6612 %}
6613
6614 ins_pipe(pipe_serial);
6615 %}
6616
6617 instruct get_and_addIiAcq(indirect mem, iRegINoSp newval, immIAdd incr)
6618 %{
6619 predicate(needs_acquiring_load_reserved(n));
6620
6621 match(Set newval (GetAndAddI mem incr));
6622
6623 ins_cost(ALU_COST);
6624
6625 format %{ "get_and_addI_acq $newval, [$mem], $incr\t#@get_and_addIiAcq" %}
6626
6627 ins_encode %{
6628 __ atomic_addalw($newval$$Register, $incr$$constant, as_Register($mem$$base));
6629 %}
6630
6631 ins_pipe(pipe_serial);
6632 %}
6633
6634 instruct get_and_addIi_no_resAcq(indirect mem, Universe dummy, immIAdd incr)
6635 %{
6636 predicate(n->as_LoadStore()->result_not_used() && needs_acquiring_load_reserved(n));
6637
6638 match(Set dummy (GetAndAddI mem incr));
6639
6640 ins_cost(ALU_COST);
6641
6642 format %{ "get_and_addI_acq [$mem], $incr\t#@get_and_addIi_no_resAcq" %}
6643
6644 ins_encode %{
6645 __ atomic_addalw(noreg, $incr$$constant, as_Register($mem$$base));
6646 %}
6647
6648 ins_pipe(pipe_serial);
6649 %}
6650
6651 // ============================================================================
6652 // Arithmetic Instructions
6653 //
6654
6655 // Integer Addition
6656
6657 // TODO
6658 // these currently employ operations which do not set CR and hence are
6659 // not flagged as killing CR but we would like to isolate the cases
6660 // where we want to set flags from those where we don't. need to work
6661 // out how to do that.
6662 instruct addI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6663 match(Set dst (AddI src1 src2));
6664
6665 ins_cost(ALU_COST);
6666 format %{ "addw $dst, $src1, $src2\t#@addI_reg_reg" %}
6667
6668 ins_encode %{
6669 __ addw(as_Register($dst$$reg),
6670 as_Register($src1$$reg),
6671 as_Register($src2$$reg));
6672 %}
6673
6674 ins_pipe(ialu_reg_reg);
6675 %}
6676
6677 instruct addI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immIAdd src2) %{
6678 match(Set dst (AddI src1 src2));
6679
6680 ins_cost(ALU_COST);
6681 format %{ "addiw $dst, $src1, $src2\t#@addI_reg_imm" %}
6682
6683 ins_encode %{
6684 __ addiw(as_Register($dst$$reg),
6685 as_Register($src1$$reg),
6686 $src2$$constant);
6687 %}
6688
6689 ins_pipe(ialu_reg_imm);
6690 %}
6691
6692 instruct addI_reg_imm_l2i(iRegINoSp dst, iRegL src1, immIAdd src2) %{
6693 match(Set dst (AddI (ConvL2I src1) src2));
6694
6695 ins_cost(ALU_COST);
6696 format %{ "addiw $dst, $src1, $src2\t#@addI_reg_imm_l2i" %}
6697
6698 ins_encode %{
6699 __ addiw(as_Register($dst$$reg),
6700 as_Register($src1$$reg),
6701 $src2$$constant);
6702 %}
6703
6704 ins_pipe(ialu_reg_imm);
6705 %}
6706
6707 // Pointer Addition
6708 instruct addP_reg_reg(iRegPNoSp dst, iRegP src1, iRegL src2) %{
6709 match(Set dst (AddP src1 src2));
6710
6711 ins_cost(ALU_COST);
6712 format %{ "add $dst, $src1, $src2\t# ptr, #@addP_reg_reg" %}
6713
6714 ins_encode %{
6715 __ add(as_Register($dst$$reg),
6716 as_Register($src1$$reg),
6717 as_Register($src2$$reg));
6718 %}
6719
6720 ins_pipe(ialu_reg_reg);
6721 %}
6722
6723 // If we shift more than 32 bits, we need not convert I2L.
6724 instruct lShiftL_regI_immGE32(iRegLNoSp dst, iRegI src, uimmI6_ge32 scale) %{
6725 match(Set dst (LShiftL (ConvI2L src) scale));
6726 ins_cost(ALU_COST);
6727 format %{ "slli $dst, $src, $scale & 63\t#@lShiftL_regI_immGE32" %}
6728
6729 ins_encode %{
6730 __ slli(as_Register($dst$$reg), as_Register($src$$reg), $scale$$constant & 63);
6731 %}
6732
6733 ins_pipe(ialu_reg_shift);
6734 %}
6735
6736 // Pointer Immediate Addition
6737 // n.b. this needs to be more expensive than using an indirect memory
6738 // operand
6739 instruct addP_reg_imm(iRegPNoSp dst, iRegP src1, immLAdd src2) %{
6740 match(Set dst (AddP src1 src2));
6741 ins_cost(ALU_COST);
6742 format %{ "addi $dst, $src1, $src2\t# ptr, #@addP_reg_imm" %}
6743
6744 ins_encode %{
6745 __ addi(as_Register($dst$$reg),
6746 as_Register($src1$$reg),
6747 $src2$$constant);
6748 %}
6749
6750 ins_pipe(ialu_reg_imm);
6751 %}
6752
6753 // Long Addition
6754 instruct addL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
6755 match(Set dst (AddL src1 src2));
6756 ins_cost(ALU_COST);
6757 format %{ "add $dst, $src1, $src2\t#@addL_reg_reg" %}
6758
6759 ins_encode %{
6760 __ add(as_Register($dst$$reg),
6761 as_Register($src1$$reg),
6762 as_Register($src2$$reg));
6763 %}
6764
6765 ins_pipe(ialu_reg_reg);
6766 %}
6767
6768 // No constant pool entries requiredLong Immediate Addition.
6769 instruct addL_reg_imm(iRegLNoSp dst, iRegL src1, immLAdd src2) %{
6770 match(Set dst (AddL src1 src2));
6771 ins_cost(ALU_COST);
6772 format %{ "addi $dst, $src1, $src2\t#@addL_reg_imm" %}
6773
6774 ins_encode %{
6775 // src2 is imm, so actually call the addi
6776 __ addi(as_Register($dst$$reg),
6777 as_Register($src1$$reg),
6778 $src2$$constant);
6779 %}
6780
6781 ins_pipe(ialu_reg_imm);
6782 %}
6783
6784 // Integer Subtraction
6785 instruct subI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6786 match(Set dst (SubI src1 src2));
6787
6788 ins_cost(ALU_COST);
6789 format %{ "subw $dst, $src1, $src2\t#@subI_reg_reg" %}
6790
6791 ins_encode %{
6792 __ subw(as_Register($dst$$reg),
6793 as_Register($src1$$reg),
6794 as_Register($src2$$reg));
6795 %}
6796
6797 ins_pipe(ialu_reg_reg);
6798 %}
6799
6800 // Immediate Subtraction
6801 instruct subI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immISub src2) %{
6802 match(Set dst (SubI src1 src2));
6803
6804 ins_cost(ALU_COST);
6805 format %{ "addiw $dst, $src1, -$src2\t#@subI_reg_imm" %}
6806
6807 ins_encode %{
6808 // src2 is imm, so actually call the addiw
6809 __ subiw(as_Register($dst$$reg),
6810 as_Register($src1$$reg),
6811 $src2$$constant);
6812 %}
6813
6814 ins_pipe(ialu_reg_imm);
6815 %}
6816
6817 // Long Subtraction
6818 instruct subL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
6819 match(Set dst (SubL src1 src2));
6820 ins_cost(ALU_COST);
6821 format %{ "sub $dst, $src1, $src2\t#@subL_reg_reg" %}
6822
6823 ins_encode %{
6824 __ sub(as_Register($dst$$reg),
6825 as_Register($src1$$reg),
6826 as_Register($src2$$reg));
6827 %}
6828
6829 ins_pipe(ialu_reg_reg);
6830 %}
6831
6832 // No constant pool entries requiredLong Immediate Subtraction.
6833 instruct subL_reg_imm(iRegLNoSp dst, iRegL src1, immLSub src2) %{
6834 match(Set dst (SubL src1 src2));
6835 ins_cost(ALU_COST);
6836 format %{ "addi $dst, $src1, -$src2\t#@subL_reg_imm" %}
6837
6838 ins_encode %{
6839 // src2 is imm, so actually call the addi
6840 __ subi(as_Register($dst$$reg),
6841 as_Register($src1$$reg),
6842 $src2$$constant);
6843 %}
6844
6845 ins_pipe(ialu_reg_imm);
6846 %}
6847
6848 // Integer Negation (special case for sub)
6849
6850 instruct negI_reg(iRegINoSp dst, iRegIorL2I src, immI0 zero) %{
6851 match(Set dst (SubI zero src));
6852 ins_cost(ALU_COST);
6853 format %{ "subw $dst, x0, $src\t# int, #@negI_reg" %}
6854
6855 ins_encode %{
6856 // actually call the subw
6857 __ negw(as_Register($dst$$reg),
6858 as_Register($src$$reg));
6859 %}
6860
6861 ins_pipe(ialu_reg);
6862 %}
6863
6864 // Long Negation
6865
6866 instruct negL_reg(iRegLNoSp dst, iRegL src, immL0 zero) %{
6867 match(Set dst (SubL zero src));
6868 ins_cost(ALU_COST);
6869 format %{ "sub $dst, x0, $src\t# long, #@negL_reg" %}
6870
6871 ins_encode %{
6872 // actually call the sub
6873 __ neg(as_Register($dst$$reg),
6874 as_Register($src$$reg));
6875 %}
6876
6877 ins_pipe(ialu_reg);
6878 %}
6879
6880 // Integer Multiply
6881
6882 instruct mulI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6883 match(Set dst (MulI src1 src2));
6884 ins_cost(IMUL_COST);
6885 format %{ "mulw $dst, $src1, $src2\t#@mulI" %}
6886
6887 //this means 2 word multi, and no sign extend to 64 bits
6888 ins_encode %{
6889 // riscv64 mulw will sign-extension to high 32 bits in dst reg
6890 __ mulw(as_Register($dst$$reg),
6891 as_Register($src1$$reg),
6892 as_Register($src2$$reg));
6893 %}
6894
6895 ins_pipe(imul_reg_reg);
6896 %}
6897
6898 // Long Multiply
6899
6900 instruct mulL(iRegLNoSp dst, iRegL src1, iRegL src2) %{
6901 match(Set dst (MulL src1 src2));
6902 ins_cost(IMUL_COST);
6903 format %{ "mul $dst, $src1, $src2\t#@mulL" %}
6904
6905 ins_encode %{
6906 __ mul(as_Register($dst$$reg),
6907 as_Register($src1$$reg),
6908 as_Register($src2$$reg));
6909 %}
6910
6911 ins_pipe(lmul_reg_reg);
6912 %}
6913
6914 instruct mulHiL_rReg(iRegLNoSp dst, iRegL src1, iRegL src2)
6915 %{
6916 match(Set dst (MulHiL src1 src2));
6917 ins_cost(IMUL_COST);
6918 format %{ "mulh $dst, $src1, $src2\t# mulhi, #@mulHiL_rReg" %}
6919
6920 ins_encode %{
6921 __ mulh(as_Register($dst$$reg),
6922 as_Register($src1$$reg),
6923 as_Register($src2$$reg));
6924 %}
6925
6926 ins_pipe(lmul_reg_reg);
6927 %}
6928
6929 instruct umulHiL_rReg(iRegLNoSp dst, iRegL src1, iRegL src2)
6930 %{
6931 match(Set dst (UMulHiL src1 src2));
6932 ins_cost(IMUL_COST);
6933 format %{ "mulhu $dst, $src1, $src2\t# umulhi, #@umulHiL_rReg" %}
6934
6935 ins_encode %{
6936 __ mulhu(as_Register($dst$$reg),
6937 as_Register($src1$$reg),
6938 as_Register($src2$$reg));
6939 %}
6940
6941 ins_pipe(lmul_reg_reg);
6942 %}
6943
6944 // Integer Divide
6945
6946 instruct divI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6947 match(Set dst (DivI src1 src2));
6948 ins_cost(IDIVSI_COST);
6949 format %{ "divw $dst, $src1, $src2\t#@divI"%}
6950
6951 ins_encode %{
6952 __ divw(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg));
6953 %}
6954 ins_pipe(idiv_reg_reg);
6955 %}
6956
6957 instruct UdivI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6958 match(Set dst (UDivI src1 src2));
6959 ins_cost(IDIVSI_COST);
6960 format %{ "divuw $dst, $src1, $src2\t#@UdivI"%}
6961
6962 ins_encode %{
6963 __ divuw(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg));
6964 %}
6965 ins_pipe(idiv_reg_reg);
6966 %}
6967
6968 instruct signExtract(iRegINoSp dst, iRegIorL2I src1, immI_31 div1, immI_31 div2) %{
6969 match(Set dst (URShiftI (RShiftI src1 div1) div2));
6970 ins_cost(ALU_COST);
6971 format %{ "srliw $dst, $src1, $div1\t# int signExtract, #@signExtract" %}
6972
6973 ins_encode %{
6974 __ srliw(as_Register($dst$$reg), as_Register($src1$$reg), 31);
6975 %}
6976 ins_pipe(ialu_reg_shift);
6977 %}
6978
6979 // Long Divide
6980
6981 instruct divL(iRegLNoSp dst, iRegL src1, iRegL src2) %{
6982 match(Set dst (DivL src1 src2));
6983 ins_cost(IDIVDI_COST);
6984 format %{ "div $dst, $src1, $src2\t#@divL" %}
6985
6986 ins_encode %{
6987 __ div(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg));
6988 %}
6989 ins_pipe(ldiv_reg_reg);
6990 %}
6991
6992 instruct UdivL(iRegLNoSp dst, iRegL src1, iRegL src2) %{
6993 match(Set dst (UDivL src1 src2));
6994 ins_cost(IDIVDI_COST);
6995
6996 format %{ "divu $dst, $src1, $src2\t#@UdivL" %}
6997
6998 ins_encode %{
6999 __ divu(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg));
7000 %}
7001 ins_pipe(ldiv_reg_reg);
7002 %}
7003
7004 instruct signExtractL(iRegLNoSp dst, iRegL src1, immI_63 div1, immI_63 div2) %{
7005 match(Set dst (URShiftL (RShiftL src1 div1) div2));
7006 ins_cost(ALU_COST);
7007 format %{ "srli $dst, $src1, $div1\t# long signExtract, #@signExtractL" %}
7008
7009 ins_encode %{
7010 __ srli(as_Register($dst$$reg), as_Register($src1$$reg), 63);
7011 %}
7012 ins_pipe(ialu_reg_shift);
7013 %}
7014
7015 // Integer Remainder
7016
7017 instruct modI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
7018 match(Set dst (ModI src1 src2));
7019 ins_cost(IDIVSI_COST);
7020 format %{ "remw $dst, $src1, $src2\t#@modI" %}
7021
7022 ins_encode %{
7023 __ remw(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg));
7024 %}
7025 ins_pipe(ialu_reg_reg);
7026 %}
7027
7028 instruct UmodI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
7029 match(Set dst (UModI src1 src2));
7030 ins_cost(IDIVSI_COST);
7031 format %{ "remuw $dst, $src1, $src2\t#@UmodI" %}
7032
7033 ins_encode %{
7034 __ remuw(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg));
7035 %}
7036 ins_pipe(ialu_reg_reg);
7037 %}
7038
7039 // Long Remainder
7040
7041 instruct modL(iRegLNoSp dst, iRegL src1, iRegL src2) %{
7042 match(Set dst (ModL src1 src2));
7043 ins_cost(IDIVDI_COST);
7044 format %{ "rem $dst, $src1, $src2\t#@modL" %}
7045
7046 ins_encode %{
7047 __ rem(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg));
7048 %}
7049 ins_pipe(ialu_reg_reg);
7050 %}
7051
7052 instruct UmodL(iRegLNoSp dst, iRegL src1, iRegL src2) %{
7053 match(Set dst (UModL src1 src2));
7054 ins_cost(IDIVDI_COST);
7055 format %{ "remu $dst, $src1, $src2\t#@UmodL" %}
7056
7057 ins_encode %{
7058 __ remu(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg));
7059 %}
7060 ins_pipe(ialu_reg_reg);
7061 %}
7062
7063 // Integer Shifts
7064
7065 // Shift Left Register
7066 // Only the low 5 bits of src2 are considered for the shift amount, all other bits are ignored.
7067 instruct lShiftI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
7068 match(Set dst (LShiftI src1 src2));
7069 ins_cost(ALU_COST);
7070 format %{ "sllw $dst, $src1, $src2\t#@lShiftI_reg_reg" %}
7071
7072 ins_encode %{
7073 __ sllw(as_Register($dst$$reg),
7074 as_Register($src1$$reg),
7075 as_Register($src2$$reg));
7076 %}
7077
7078 ins_pipe(ialu_reg_reg_vshift);
7079 %}
7080
7081 // Shift Left Immediate
7082 instruct lShiftI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immI src2) %{
7083 match(Set dst (LShiftI src1 src2));
7084 ins_cost(ALU_COST);
7085 format %{ "slliw $dst, $src1, ($src2 & 0x1f)\t#@lShiftI_reg_imm" %}
7086
7087 ins_encode %{
7088 // the shift amount is encoded in the lower
7089 // 5 bits of the I-immediate field for RV32I
7090 __ slliw(as_Register($dst$$reg),
7091 as_Register($src1$$reg),
7092 (unsigned) $src2$$constant & 0x1f);
7093 %}
7094
7095 ins_pipe(ialu_reg_shift);
7096 %}
7097
7098 // Shift Right Logical Register
7099 // Only the low 5 bits of src2 are considered for the shift amount, all other bits are ignored.
7100 instruct urShiftI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
7101 match(Set dst (URShiftI src1 src2));
7102 ins_cost(ALU_COST);
7103 format %{ "srlw $dst, $src1, $src2\t#@urShiftI_reg_reg" %}
7104
7105 ins_encode %{
7106 __ srlw(as_Register($dst$$reg),
7107 as_Register($src1$$reg),
7108 as_Register($src2$$reg));
7109 %}
7110
7111 ins_pipe(ialu_reg_reg_vshift);
7112 %}
7113
7114 // Shift Right Logical Immediate
7115 instruct urShiftI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immI src2) %{
7116 match(Set dst (URShiftI src1 src2));
7117 ins_cost(ALU_COST);
7118 format %{ "srliw $dst, $src1, ($src2 & 0x1f)\t#@urShiftI_reg_imm" %}
7119
7120 ins_encode %{
7121 // the shift amount is encoded in the lower
7122 // 6 bits of the I-immediate field for RV64I
7123 __ srliw(as_Register($dst$$reg),
7124 as_Register($src1$$reg),
7125 (unsigned) $src2$$constant & 0x1f);
7126 %}
7127
7128 ins_pipe(ialu_reg_shift);
7129 %}
7130
7131 // Shift Right Arithmetic Register
7132 // Only the low 5 bits of src2 are considered for the shift amount, all other bits are ignored.
7133 instruct rShiftI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
7134 match(Set dst (RShiftI src1 src2));
7135 ins_cost(ALU_COST);
7136 format %{ "sraw $dst, $src1, $src2\t#@rShiftI_reg_reg" %}
7137
7138 ins_encode %{
7139 // riscv will sign-ext dst high 32 bits
7140 __ sraw(as_Register($dst$$reg),
7141 as_Register($src1$$reg),
7142 as_Register($src2$$reg));
7143 %}
7144
7145 ins_pipe(ialu_reg_reg_vshift);
7146 %}
7147
7148 // Shift Right Arithmetic Immediate
7149 instruct rShiftI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immI src2) %{
7150 match(Set dst (RShiftI src1 src2));
7151 ins_cost(ALU_COST);
7152 format %{ "sraiw $dst, $src1, ($src2 & 0x1f)\t#@rShiftI_reg_imm" %}
7153
7154 ins_encode %{
7155 // riscv will sign-ext dst high 32 bits
7156 __ sraiw(as_Register($dst$$reg),
7157 as_Register($src1$$reg),
7158 (unsigned) $src2$$constant & 0x1f);
7159 %}
7160
7161 ins_pipe(ialu_reg_shift);
7162 %}
7163
7164 // Long Shifts
7165
7166 // Shift Left Register
7167 // Only the low 6 bits of src2 are considered for the shift amount, all other bits are ignored.
7168 instruct lShiftL_reg_reg(iRegLNoSp dst, iRegL src1, iRegIorL2I src2) %{
7169 match(Set dst (LShiftL src1 src2));
7170
7171 ins_cost(ALU_COST);
7172 format %{ "sll $dst, $src1, $src2\t#@lShiftL_reg_reg" %}
7173
7174 ins_encode %{
7175 __ sll(as_Register($dst$$reg),
7176 as_Register($src1$$reg),
7177 as_Register($src2$$reg));
7178 %}
7179
7180 ins_pipe(ialu_reg_reg_vshift);
7181 %}
7182
7183 // Shift Left Immediate
7184 instruct lShiftL_reg_imm(iRegLNoSp dst, iRegL src1, immI src2) %{
7185 match(Set dst (LShiftL src1 src2));
7186
7187 ins_cost(ALU_COST);
7188 format %{ "slli $dst, $src1, ($src2 & 0x3f)\t#@lShiftL_reg_imm" %}
7189
7190 ins_encode %{
7191 // the shift amount is encoded in the lower
7192 // 6 bits of the I-immediate field for RV64I
7193 __ slli(as_Register($dst$$reg),
7194 as_Register($src1$$reg),
7195 (unsigned) $src2$$constant & 0x3f);
7196 %}
7197
7198 ins_pipe(ialu_reg_shift);
7199 %}
7200
7201 // Shift Right Logical Register
7202 // Only the low 6 bits of src2 are considered for the shift amount, all other bits are ignored.
7203 instruct urShiftL_reg_reg(iRegLNoSp dst, iRegL src1, iRegIorL2I src2) %{
7204 match(Set dst (URShiftL src1 src2));
7205
7206 ins_cost(ALU_COST);
7207 format %{ "srl $dst, $src1, $src2\t#@urShiftL_reg_reg" %}
7208
7209 ins_encode %{
7210 __ srl(as_Register($dst$$reg),
7211 as_Register($src1$$reg),
7212 as_Register($src2$$reg));
7213 %}
7214
7215 ins_pipe(ialu_reg_reg_vshift);
7216 %}
7217
7218 // Shift Right Logical Immediate
7219 instruct urShiftL_reg_imm(iRegLNoSp dst, iRegL src1, immI src2) %{
7220 match(Set dst (URShiftL src1 src2));
7221
7222 ins_cost(ALU_COST);
7223 format %{ "srli $dst, $src1, ($src2 & 0x3f)\t#@urShiftL_reg_imm" %}
7224
7225 ins_encode %{
7226 // the shift amount is encoded in the lower
7227 // 6 bits of the I-immediate field for RV64I
7228 __ srli(as_Register($dst$$reg),
7229 as_Register($src1$$reg),
7230 (unsigned) $src2$$constant & 0x3f);
7231 %}
7232
7233 ins_pipe(ialu_reg_shift);
7234 %}
7235
7236 // A special-case pattern for card table stores.
7237 instruct urShiftP_reg_imm(iRegLNoSp dst, iRegP src1, immI src2) %{
7238 match(Set dst (URShiftL (CastP2X src1) src2));
7239
7240 ins_cost(ALU_COST);
7241 format %{ "srli $dst, p2x($src1), ($src2 & 0x3f)\t#@urShiftP_reg_imm" %}
7242
7243 ins_encode %{
7244 // the shift amount is encoded in the lower
7245 // 6 bits of the I-immediate field for RV64I
7246 __ srli(as_Register($dst$$reg),
7247 as_Register($src1$$reg),
7248 (unsigned) $src2$$constant & 0x3f);
7249 %}
7250
7251 ins_pipe(ialu_reg_shift);
7252 %}
7253
7254 // Shift Right Arithmetic Register
7255 // Only the low 6 bits of src2 are considered for the shift amount, all other bits are ignored.
7256 instruct rShiftL_reg_reg(iRegLNoSp dst, iRegL src1, iRegIorL2I src2) %{
7257 match(Set dst (RShiftL src1 src2));
7258
7259 ins_cost(ALU_COST);
7260 format %{ "sra $dst, $src1, $src2\t#@rShiftL_reg_reg" %}
7261
7262 ins_encode %{
7263 __ sra(as_Register($dst$$reg),
7264 as_Register($src1$$reg),
7265 as_Register($src2$$reg));
7266 %}
7267
7268 ins_pipe(ialu_reg_reg_vshift);
7269 %}
7270
7271 // Shift Right Arithmetic Immediate
7272 instruct rShiftL_reg_imm(iRegLNoSp dst, iRegL src1, immI src2) %{
7273 match(Set dst (RShiftL src1 src2));
7274
7275 ins_cost(ALU_COST);
7276 format %{ "srai $dst, $src1, ($src2 & 0x3f)\t#@rShiftL_reg_imm" %}
7277
7278 ins_encode %{
7279 // the shift amount is encoded in the lower
7280 // 6 bits of the I-immediate field for RV64I
7281 __ srai(as_Register($dst$$reg),
7282 as_Register($src1$$reg),
7283 (unsigned) $src2$$constant & 0x3f);
7284 %}
7285
7286 ins_pipe(ialu_reg_shift);
7287 %}
7288
7289 instruct regI_not_reg(iRegINoSp dst, iRegI src1, immI_M1 m1) %{
7290 match(Set dst (XorI src1 m1));
7291 ins_cost(ALU_COST);
7292 format %{ "xori $dst, $src1, -1\t#@regI_not_reg" %}
7293
7294 ins_encode %{
7295 __ xori(as_Register($dst$$reg), as_Register($src1$$reg), -1);
7296 %}
7297
7298 ins_pipe(ialu_reg_imm);
7299 %}
7300
7301 instruct regL_not_reg(iRegLNoSp dst, iRegL src1, immL_M1 m1) %{
7302 match(Set dst (XorL src1 m1));
7303 ins_cost(ALU_COST);
7304 format %{ "xori $dst, $src1, -1\t#@regL_not_reg" %}
7305
7306 ins_encode %{
7307 __ xori(as_Register($dst$$reg), as_Register($src1$$reg), -1);
7308 %}
7309
7310 ins_pipe(ialu_reg_imm);
7311 %}
7312
7313
7314 // ============================================================================
7315 // Floating Point Arithmetic Instructions
7316
7317 instruct addF_reg_reg(fRegF dst, fRegF src1, fRegF src2) %{
7318 match(Set dst (AddF src1 src2));
7319
7320 ins_cost(DEFAULT_COST * 5);
7321 format %{ "fadd.s $dst, $src1, $src2\t#@addF_reg_reg" %}
7322
7323 ins_encode %{
7324 __ fadd_s(as_FloatRegister($dst$$reg),
7325 as_FloatRegister($src1$$reg),
7326 as_FloatRegister($src2$$reg));
7327 %}
7328
7329 ins_pipe(fp_dop_reg_reg_s);
7330 %}
7331
7332 instruct addD_reg_reg(fRegD dst, fRegD src1, fRegD src2) %{
7333 match(Set dst (AddD src1 src2));
7334
7335 ins_cost(DEFAULT_COST * 5);
7336 format %{ "fadd.d $dst, $src1, $src2\t#@addD_reg_reg" %}
7337
7338 ins_encode %{
7339 __ fadd_d(as_FloatRegister($dst$$reg),
7340 as_FloatRegister($src1$$reg),
7341 as_FloatRegister($src2$$reg));
7342 %}
7343
7344 ins_pipe(fp_dop_reg_reg_d);
7345 %}
7346
7347 instruct subF_reg_reg(fRegF dst, fRegF src1, fRegF src2) %{
7348 match(Set dst (SubF src1 src2));
7349
7350 ins_cost(DEFAULT_COST * 5);
7351 format %{ "fsub.s $dst, $src1, $src2\t#@subF_reg_reg" %}
7352
7353 ins_encode %{
7354 __ fsub_s(as_FloatRegister($dst$$reg),
7355 as_FloatRegister($src1$$reg),
7356 as_FloatRegister($src2$$reg));
7357 %}
7358
7359 ins_pipe(fp_dop_reg_reg_s);
7360 %}
7361
7362 instruct subD_reg_reg(fRegD dst, fRegD src1, fRegD src2) %{
7363 match(Set dst (SubD src1 src2));
7364
7365 ins_cost(DEFAULT_COST * 5);
7366 format %{ "fsub.d $dst, $src1, $src2\t#@subD_reg_reg" %}
7367
7368 ins_encode %{
7369 __ fsub_d(as_FloatRegister($dst$$reg),
7370 as_FloatRegister($src1$$reg),
7371 as_FloatRegister($src2$$reg));
7372 %}
7373
7374 ins_pipe(fp_dop_reg_reg_d);
7375 %}
7376
7377 instruct mulF_reg_reg(fRegF dst, fRegF src1, fRegF src2) %{
7378 match(Set dst (MulF src1 src2));
7379
7380 ins_cost(FMUL_SINGLE_COST);
7381 format %{ "fmul.s $dst, $src1, $src2\t#@mulF_reg_reg" %}
7382
7383 ins_encode %{
7384 __ fmul_s(as_FloatRegister($dst$$reg),
7385 as_FloatRegister($src1$$reg),
7386 as_FloatRegister($src2$$reg));
7387 %}
7388
7389 ins_pipe(fp_dop_reg_reg_s);
7390 %}
7391
7392 instruct mulD_reg_reg(fRegD dst, fRegD src1, fRegD src2) %{
7393 match(Set dst (MulD src1 src2));
7394
7395 ins_cost(FMUL_DOUBLE_COST);
7396 format %{ "fmul.d $dst, $src1, $src2\t#@mulD_reg_reg" %}
7397
7398 ins_encode %{
7399 __ fmul_d(as_FloatRegister($dst$$reg),
7400 as_FloatRegister($src1$$reg),
7401 as_FloatRegister($src2$$reg));
7402 %}
7403
7404 ins_pipe(fp_dop_reg_reg_d);
7405 %}
7406
7407 // src1 * src2 + src3
7408 instruct maddF_reg_reg(fRegF dst, fRegF src1, fRegF src2, fRegF src3) %{
7409 match(Set dst (FmaF src3 (Binary src1 src2)));
7410
7411 ins_cost(FMUL_SINGLE_COST);
7412 format %{ "fmadd.s $dst, $src1, $src2, $src3\t#@maddF_reg_reg" %}
7413
7414 ins_encode %{
7415 assert(UseFMA, "Needs FMA instructions support.");
7416 __ fmadd_s(as_FloatRegister($dst$$reg),
7417 as_FloatRegister($src1$$reg),
7418 as_FloatRegister($src2$$reg),
7419 as_FloatRegister($src3$$reg));
7420 %}
7421
7422 ins_pipe(pipe_class_default);
7423 %}
7424
7425 // src1 * src2 + src3
7426 instruct maddD_reg_reg(fRegD dst, fRegD src1, fRegD src2, fRegD src3) %{
7427 match(Set dst (FmaD src3 (Binary src1 src2)));
7428
7429 ins_cost(FMUL_DOUBLE_COST);
7430 format %{ "fmadd.d $dst, $src1, $src2, $src3\t#@maddD_reg_reg" %}
7431
7432 ins_encode %{
7433 assert(UseFMA, "Needs FMA instructions support.");
7434 __ fmadd_d(as_FloatRegister($dst$$reg),
7435 as_FloatRegister($src1$$reg),
7436 as_FloatRegister($src2$$reg),
7437 as_FloatRegister($src3$$reg));
7438 %}
7439
7440 ins_pipe(pipe_class_default);
7441 %}
7442
7443 // src1 * src2 - src3
7444 instruct msubF_reg_reg(fRegF dst, fRegF src1, fRegF src2, fRegF src3) %{
7445 match(Set dst (FmaF (NegF src3) (Binary src1 src2)));
7446
7447 ins_cost(FMUL_SINGLE_COST);
7448 format %{ "fmsub.s $dst, $src1, $src2, $src3\t#@msubF_reg_reg" %}
7449
7450 ins_encode %{
7451 assert(UseFMA, "Needs FMA instructions support.");
7452 __ fmsub_s(as_FloatRegister($dst$$reg),
7453 as_FloatRegister($src1$$reg),
7454 as_FloatRegister($src2$$reg),
7455 as_FloatRegister($src3$$reg));
7456 %}
7457
7458 ins_pipe(pipe_class_default);
7459 %}
7460
7461 // src1 * src2 - src3
7462 instruct msubD_reg_reg(fRegD dst, fRegD src1, fRegD src2, fRegD src3) %{
7463 match(Set dst (FmaD (NegD src3) (Binary src1 src2)));
7464
7465 ins_cost(FMUL_DOUBLE_COST);
7466 format %{ "fmsub.d $dst, $src1, $src2, $src3\t#@msubD_reg_reg" %}
7467
7468 ins_encode %{
7469 assert(UseFMA, "Needs FMA instructions support.");
7470 __ fmsub_d(as_FloatRegister($dst$$reg),
7471 as_FloatRegister($src1$$reg),
7472 as_FloatRegister($src2$$reg),
7473 as_FloatRegister($src3$$reg));
7474 %}
7475
7476 ins_pipe(pipe_class_default);
7477 %}
7478
7479 // src1 * (-src2) + src3
7480 // "(-src1) * src2 + src3" has been idealized to "src2 * (-src1) + src3"
7481 instruct nmsubF_reg_reg(fRegF dst, fRegF src1, fRegF src2, fRegF src3) %{
7482 match(Set dst (FmaF src3 (Binary src1 (NegF src2))));
7483
7484 ins_cost(FMUL_SINGLE_COST);
7485 format %{ "fnmsub.s $dst, $src1, $src2, $src3\t#@nmsubF_reg_reg" %}
7486
7487 ins_encode %{
7488 assert(UseFMA, "Needs FMA instructions support.");
7489 __ fnmsub_s(as_FloatRegister($dst$$reg),
7490 as_FloatRegister($src1$$reg),
7491 as_FloatRegister($src2$$reg),
7492 as_FloatRegister($src3$$reg));
7493 %}
7494
7495 ins_pipe(pipe_class_default);
7496 %}
7497
7498 // src1 * (-src2) + src3
7499 // "(-src1) * src2 + src3" has been idealized to "src2 * (-src1) + src3"
7500 instruct nmsubD_reg_reg(fRegD dst, fRegD src1, fRegD src2, fRegD src3) %{
7501 match(Set dst (FmaD src3 (Binary src1 (NegD src2))));
7502
7503 ins_cost(FMUL_DOUBLE_COST);
7504 format %{ "fnmsub.d $dst, $src1, $src2, $src3\t#@nmsubD_reg_reg" %}
7505
7506 ins_encode %{
7507 assert(UseFMA, "Needs FMA instructions support.");
7508 __ fnmsub_d(as_FloatRegister($dst$$reg),
7509 as_FloatRegister($src1$$reg),
7510 as_FloatRegister($src2$$reg),
7511 as_FloatRegister($src3$$reg));
7512 %}
7513
7514 ins_pipe(pipe_class_default);
7515 %}
7516
7517 // src1 * (-src2) - src3
7518 // "(-src1) * src2 - src3" has been idealized to "src2 * (-src1) - src3"
7519 instruct nmaddF_reg_reg(fRegF dst, fRegF src1, fRegF src2, fRegF src3) %{
7520 match(Set dst (FmaF (NegF src3) (Binary src1 (NegF src2))));
7521
7522 ins_cost(FMUL_SINGLE_COST);
7523 format %{ "fnmadd.s $dst, $src1, $src2, $src3\t#@nmaddF_reg_reg" %}
7524
7525 ins_encode %{
7526 assert(UseFMA, "Needs FMA instructions support.");
7527 __ fnmadd_s(as_FloatRegister($dst$$reg),
7528 as_FloatRegister($src1$$reg),
7529 as_FloatRegister($src2$$reg),
7530 as_FloatRegister($src3$$reg));
7531 %}
7532
7533 ins_pipe(pipe_class_default);
7534 %}
7535
7536 // src1 * (-src2) - src3
7537 // "(-src1) * src2 - src3" has been idealized to "src2 * (-src1) - src3"
7538 instruct nmaddD_reg_reg(fRegD dst, fRegD src1, fRegD src2, fRegD src3) %{
7539 match(Set dst (FmaD (NegD src3) (Binary src1 (NegD src2))));
7540
7541 ins_cost(FMUL_DOUBLE_COST);
7542 format %{ "fnmadd.d $dst, $src1, $src2, $src3\t#@nmaddD_reg_reg" %}
7543
7544 ins_encode %{
7545 assert(UseFMA, "Needs FMA instructions support.");
7546 __ fnmadd_d(as_FloatRegister($dst$$reg),
7547 as_FloatRegister($src1$$reg),
7548 as_FloatRegister($src2$$reg),
7549 as_FloatRegister($src3$$reg));
7550 %}
7551
7552 ins_pipe(pipe_class_default);
7553 %}
7554
7555 // Math.max(FF)F
7556 instruct maxF_reg_reg(fRegF dst, fRegF src1, fRegF src2, rFlagsReg cr) %{
7557 predicate(!UseZfa);
7558 match(Set dst (MaxF src1 src2));
7559 effect(KILL cr);
7560
7561 format %{ "maxF $dst, $src1, $src2" %}
7562
7563 ins_encode %{
7564 __ minmax_fp(as_FloatRegister($dst$$reg),
7565 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg),
7566 __ FLOAT_TYPE::single_precision, false /* is_min */);
7567 %}
7568
7569 ins_pipe(pipe_class_default);
7570 %}
7571
7572 instruct maxF_reg_reg_zfa(fRegF dst, fRegF src1, fRegF src2) %{
7573 predicate(UseZfa);
7574 match(Set dst (MaxF src1 src2));
7575
7576 format %{ "maxF $dst, $src1, $src2" %}
7577
7578 ins_encode %{
7579 __ fmaxm_s(as_FloatRegister($dst$$reg),
7580 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
7581 %}
7582
7583 ins_pipe(pipe_class_default);
7584 %}
7585
7586 // Math.min(FF)F
7587 instruct minF_reg_reg(fRegF dst, fRegF src1, fRegF src2, rFlagsReg cr) %{
7588 predicate(!UseZfa);
7589 match(Set dst (MinF src1 src2));
7590 effect(KILL cr);
7591
7592 format %{ "minF $dst, $src1, $src2" %}
7593
7594 ins_encode %{
7595 __ minmax_fp(as_FloatRegister($dst$$reg),
7596 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg),
7597 __ FLOAT_TYPE::single_precision, true /* is_min */);
7598 %}
7599
7600 ins_pipe(pipe_class_default);
7601 %}
7602
7603 instruct minF_reg_reg_zfa(fRegF dst, fRegF src1, fRegF src2) %{
7604 predicate(UseZfa);
7605 match(Set dst (MinF src1 src2));
7606
7607 format %{ "minF $dst, $src1, $src2" %}
7608
7609 ins_encode %{
7610 __ fminm_s(as_FloatRegister($dst$$reg),
7611 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
7612 %}
7613
7614 ins_pipe(pipe_class_default);
7615 %}
7616
7617 // Math.max(DD)D
7618 instruct maxD_reg_reg(fRegD dst, fRegD src1, fRegD src2, rFlagsReg cr) %{
7619 predicate(!UseZfa);
7620 match(Set dst (MaxD src1 src2));
7621 effect(KILL cr);
7622
7623 format %{ "maxD $dst, $src1, $src2" %}
7624
7625 ins_encode %{
7626 __ minmax_fp(as_FloatRegister($dst$$reg),
7627 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg),
7628 __ FLOAT_TYPE::double_precision, false /* is_min */);
7629 %}
7630
7631 ins_pipe(pipe_class_default);
7632 %}
7633
7634 instruct maxD_reg_reg_zfa(fRegD dst, fRegD src1, fRegD src2) %{
7635 predicate(UseZfa);
7636 match(Set dst (MaxD src1 src2));
7637
7638 format %{ "maxD $dst, $src1, $src2" %}
7639
7640 ins_encode %{
7641 __ fmaxm_d(as_FloatRegister($dst$$reg),
7642 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
7643 %}
7644
7645 ins_pipe(pipe_class_default);
7646 %}
7647
7648 // Math.min(DD)D
7649 instruct minD_reg_reg(fRegD dst, fRegD src1, fRegD src2, rFlagsReg cr) %{
7650 predicate(!UseZfa);
7651 match(Set dst (MinD src1 src2));
7652 effect(KILL cr);
7653
7654 format %{ "minD $dst, $src1, $src2" %}
7655
7656 ins_encode %{
7657 __ minmax_fp(as_FloatRegister($dst$$reg),
7658 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg),
7659 __ FLOAT_TYPE::double_precision, true /* is_min */);
7660 %}
7661
7662 ins_pipe(pipe_class_default);
7663 %}
7664
7665 instruct minD_reg_reg_zfa(fRegD dst, fRegD src1, fRegD src2) %{
7666 predicate(UseZfa);
7667 match(Set dst (MinD src1 src2));
7668
7669 format %{ "minD $dst, $src1, $src2" %}
7670
7671 ins_encode %{
7672 __ fminm_d(as_FloatRegister($dst$$reg),
7673 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
7674 %}
7675
7676 ins_pipe(pipe_class_default);
7677 %}
7678
7679 // Float.isInfinite
7680 instruct isInfiniteF_reg_reg(iRegINoSp dst, fRegF src)
7681 %{
7682 match(Set dst (IsInfiniteF src));
7683
7684 format %{ "isInfinite $dst, $src" %}
7685 ins_encode %{
7686 __ fclass_s(as_Register($dst$$reg), as_FloatRegister($src$$reg));
7687 __ andi(as_Register($dst$$reg), as_Register($dst$$reg), Assembler::FClassBits::inf);
7688 __ slt(as_Register($dst$$reg), zr, as_Register($dst$$reg));
7689 %}
7690
7691 ins_pipe(pipe_class_default);
7692 %}
7693
7694 // Double.isInfinite
7695 instruct isInfiniteD_reg_reg(iRegINoSp dst, fRegD src)
7696 %{
7697 match(Set dst (IsInfiniteD src));
7698
7699 format %{ "isInfinite $dst, $src" %}
7700 ins_encode %{
7701 __ fclass_d(as_Register($dst$$reg), as_FloatRegister($src$$reg));
7702 __ andi(as_Register($dst$$reg), as_Register($dst$$reg), Assembler::FClassBits::inf);
7703 __ slt(as_Register($dst$$reg), zr, as_Register($dst$$reg));
7704 %}
7705
7706 ins_pipe(pipe_class_default);
7707 %}
7708
7709 // Float.isFinite
7710 instruct isFiniteF_reg_reg(iRegINoSp dst, fRegF src)
7711 %{
7712 match(Set dst (IsFiniteF src));
7713
7714 format %{ "isFinite $dst, $src" %}
7715 ins_encode %{
7716 __ fclass_s(as_Register($dst$$reg), as_FloatRegister($src$$reg));
7717 __ andi(as_Register($dst$$reg), as_Register($dst$$reg), Assembler::FClassBits::finite);
7718 __ slt(as_Register($dst$$reg), zr, as_Register($dst$$reg));
7719 %}
7720
7721 ins_pipe(pipe_class_default);
7722 %}
7723
7724 // Double.isFinite
7725 instruct isFiniteD_reg_reg(iRegINoSp dst, fRegD src)
7726 %{
7727 match(Set dst (IsFiniteD src));
7728
7729 format %{ "isFinite $dst, $src" %}
7730 ins_encode %{
7731 __ fclass_d(as_Register($dst$$reg), as_FloatRegister($src$$reg));
7732 __ andi(as_Register($dst$$reg), as_Register($dst$$reg), Assembler::FClassBits::finite);
7733 __ slt(as_Register($dst$$reg), zr, as_Register($dst$$reg));
7734 %}
7735
7736 ins_pipe(pipe_class_default);
7737 %}
7738
7739 instruct divF_reg_reg(fRegF dst, fRegF src1, fRegF src2) %{
7740 match(Set dst (DivF src1 src2));
7741
7742 ins_cost(FDIV_COST);
7743 format %{ "fdiv.s $dst, $src1, $src2\t#@divF_reg_reg" %}
7744
7745 ins_encode %{
7746 __ fdiv_s(as_FloatRegister($dst$$reg),
7747 as_FloatRegister($src1$$reg),
7748 as_FloatRegister($src2$$reg));
7749 %}
7750
7751 ins_pipe(fp_div_s);
7752 %}
7753
7754 instruct divD_reg_reg(fRegD dst, fRegD src1, fRegD src2) %{
7755 match(Set dst (DivD src1 src2));
7756
7757 ins_cost(FDIV_COST);
7758 format %{ "fdiv.d $dst, $src1, $src2\t#@divD_reg_reg" %}
7759
7760 ins_encode %{
7761 __ fdiv_d(as_FloatRegister($dst$$reg),
7762 as_FloatRegister($src1$$reg),
7763 as_FloatRegister($src2$$reg));
7764 %}
7765
7766 ins_pipe(fp_div_d);
7767 %}
7768
7769 instruct negF_reg_reg(fRegF dst, fRegF src) %{
7770 match(Set dst (NegF src));
7771
7772 ins_cost(XFER_COST);
7773 format %{ "fsgnjn.s $dst, $src, $src\t#@negF_reg_reg" %}
7774
7775 ins_encode %{
7776 __ fneg_s(as_FloatRegister($dst$$reg),
7777 as_FloatRegister($src$$reg));
7778 %}
7779
7780 ins_pipe(fp_uop_s);
7781 %}
7782
7783 instruct negD_reg_reg(fRegD dst, fRegD src) %{
7784 match(Set dst (NegD src));
7785
7786 ins_cost(XFER_COST);
7787 format %{ "fsgnjn.d $dst, $src, $src\t#@negD_reg_reg" %}
7788
7789 ins_encode %{
7790 __ fneg_d(as_FloatRegister($dst$$reg),
7791 as_FloatRegister($src$$reg));
7792 %}
7793
7794 ins_pipe(fp_uop_d);
7795 %}
7796
7797 instruct absI_reg(iRegINoSp dst, iRegIorL2I src) %{
7798 match(Set dst (AbsI src));
7799
7800 ins_cost(ALU_COST * 3);
7801 format %{
7802 "sraiw t0, $src, 0x1f\n\t"
7803 "addw $dst, $src, t0\n\t"
7804 "xorr $dst, $dst, t0\t#@absI_reg"
7805 %}
7806
7807 ins_encode %{
7808 __ sraiw(t0, as_Register($src$$reg), 0x1f);
7809 __ addw(as_Register($dst$$reg), as_Register($src$$reg), t0);
7810 __ xorr(as_Register($dst$$reg), as_Register($dst$$reg), t0);
7811 %}
7812
7813 ins_pipe(pipe_class_default);
7814 %}
7815
7816 instruct absL_reg(iRegLNoSp dst, iRegL src) %{
7817 match(Set dst (AbsL src));
7818
7819 ins_cost(ALU_COST * 3);
7820 format %{
7821 "srai t0, $src, 0x3f\n\t"
7822 "add $dst, $src, t0\n\t"
7823 "xorr $dst, $dst, t0\t#@absL_reg"
7824 %}
7825
7826 ins_encode %{
7827 __ srai(t0, as_Register($src$$reg), 0x3f);
7828 __ add(as_Register($dst$$reg), as_Register($src$$reg), t0);
7829 __ xorr(as_Register($dst$$reg), as_Register($dst$$reg), t0);
7830 %}
7831
7832 ins_pipe(pipe_class_default);
7833 %}
7834
7835 instruct absF_reg(fRegF dst, fRegF src) %{
7836 match(Set dst (AbsF src));
7837
7838 ins_cost(XFER_COST);
7839 format %{ "fsgnjx.s $dst, $src, $src\t#@absF_reg" %}
7840 ins_encode %{
7841 __ fabs_s(as_FloatRegister($dst$$reg),
7842 as_FloatRegister($src$$reg));
7843 %}
7844
7845 ins_pipe(fp_uop_s);
7846 %}
7847
7848 instruct absD_reg(fRegD dst, fRegD src) %{
7849 match(Set dst (AbsD src));
7850
7851 ins_cost(XFER_COST);
7852 format %{ "fsgnjx.d $dst, $src, $src\t#@absD_reg" %}
7853 ins_encode %{
7854 __ fabs_d(as_FloatRegister($dst$$reg),
7855 as_FloatRegister($src$$reg));
7856 %}
7857
7858 ins_pipe(fp_uop_d);
7859 %}
7860
7861 instruct sqrtF_reg(fRegF dst, fRegF src) %{
7862 match(Set dst (SqrtF src));
7863
7864 ins_cost(FSQRT_COST);
7865 format %{ "fsqrt.s $dst, $src\t#@sqrtF_reg" %}
7866 ins_encode %{
7867 __ fsqrt_s(as_FloatRegister($dst$$reg),
7868 as_FloatRegister($src$$reg));
7869 %}
7870
7871 ins_pipe(fp_sqrt_s);
7872 %}
7873
7874 instruct sqrtD_reg(fRegD dst, fRegD src) %{
7875 match(Set dst (SqrtD src));
7876
7877 ins_cost(FSQRT_COST);
7878 format %{ "fsqrt.d $dst, $src\t#@sqrtD_reg" %}
7879 ins_encode %{
7880 __ fsqrt_d(as_FloatRegister($dst$$reg),
7881 as_FloatRegister($src$$reg));
7882 %}
7883
7884 ins_pipe(fp_sqrt_d);
7885 %}
7886
7887 // Round Instruction
7888 instruct roundD_reg(fRegD dst, fRegD src, immI rmode, iRegLNoSp tmp1, iRegLNoSp tmp2, iRegLNoSp tmp3) %{
7889 match(Set dst (RoundDoubleMode src rmode));
7890 ins_cost(2 * XFER_COST + BRANCH_COST);
7891 effect(TEMP_DEF dst, TEMP tmp1, TEMP tmp2, TEMP tmp3);
7892
7893 format %{ "RoundDoubleMode $src, $rmode" %}
7894 ins_encode %{
7895 __ round_double_mode(as_FloatRegister($dst$$reg),
7896 as_FloatRegister($src$$reg), $rmode$$constant, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
7897 %}
7898 ins_pipe(pipe_class_default);
7899 %}
7900
7901 // Copysign and signum intrinsics
7902
7903 instruct copySignD_reg(fRegD dst, fRegD src1, fRegD src2, immD zero) %{
7904 match(Set dst (CopySignD src1 (Binary src2 zero)));
7905 format %{ "CopySignD $dst $src1 $src2" %}
7906 ins_encode %{
7907 FloatRegister dst = as_FloatRegister($dst$$reg),
7908 src1 = as_FloatRegister($src1$$reg),
7909 src2 = as_FloatRegister($src2$$reg);
7910 __ fsgnj_d(dst, src1, src2);
7911 %}
7912 ins_pipe(fp_dop_reg_reg_d);
7913 %}
7914
7915 instruct copySignF_reg(fRegF dst, fRegF src1, fRegF src2) %{
7916 match(Set dst (CopySignF src1 src2));
7917 format %{ "CopySignF $dst $src1 $src2" %}
7918 ins_encode %{
7919 FloatRegister dst = as_FloatRegister($dst$$reg),
7920 src1 = as_FloatRegister($src1$$reg),
7921 src2 = as_FloatRegister($src2$$reg);
7922 __ fsgnj_s(dst, src1, src2);
7923 %}
7924 ins_pipe(fp_dop_reg_reg_s);
7925 %}
7926
7927 instruct signumD_reg(fRegD dst, immD zero, fRegD one) %{
7928 match(Set dst (SignumD dst (Binary zero one)));
7929 format %{ "signumD $dst, $dst" %}
7930 ins_encode %{
7931 __ signum_fp(as_FloatRegister($dst$$reg), as_FloatRegister($one$$reg), true /* is_double */);
7932 %}
7933 ins_pipe(pipe_class_default);
7934 %}
7935
7936 instruct signumF_reg(fRegF dst, immF zero, fRegF one) %{
7937 match(Set dst (SignumF dst (Binary zero one)));
7938 format %{ "signumF $dst, $dst" %}
7939 ins_encode %{
7940 __ signum_fp(as_FloatRegister($dst$$reg), as_FloatRegister($one$$reg), false /* is_double */);
7941 %}
7942 ins_pipe(pipe_class_default);
7943 %}
7944
7945 // Arithmetic Instructions End
7946
7947 // ============================================================================
7948 // Logical Instructions
7949
7950 // Register And
7951 instruct andI_reg_reg(iRegINoSp dst, iRegI src1, iRegI src2) %{
7952 match(Set dst (AndI src1 src2));
7953
7954 format %{ "andr $dst, $src1, $src2\t#@andI_reg_reg" %}
7955
7956 ins_cost(ALU_COST);
7957 ins_encode %{
7958 __ andr(as_Register($dst$$reg),
7959 as_Register($src1$$reg),
7960 as_Register($src2$$reg));
7961 %}
7962
7963 ins_pipe(ialu_reg_reg);
7964 %}
7965
7966 // Immediate And
7967 instruct andI_reg_imm(iRegINoSp dst, iRegI src1, immIAdd src2) %{
7968 match(Set dst (AndI src1 src2));
7969
7970 format %{ "andi $dst, $src1, $src2\t#@andI_reg_imm" %}
7971
7972 ins_cost(ALU_COST);
7973 ins_encode %{
7974 __ andi(as_Register($dst$$reg),
7975 as_Register($src1$$reg),
7976 (int32_t)($src2$$constant));
7977 %}
7978
7979 ins_pipe(ialu_reg_imm);
7980 %}
7981
7982 // Register Or
7983 instruct orI_reg_reg(iRegINoSp dst, iRegI src1, iRegI src2) %{
7984 match(Set dst (OrI src1 src2));
7985
7986 format %{ "orr $dst, $src1, $src2\t#@orI_reg_reg" %}
7987
7988 ins_cost(ALU_COST);
7989 ins_encode %{
7990 __ orr(as_Register($dst$$reg),
7991 as_Register($src1$$reg),
7992 as_Register($src2$$reg));
7993 %}
7994
7995 ins_pipe(ialu_reg_reg);
7996 %}
7997
7998 // Immediate Or
7999 instruct orI_reg_imm(iRegINoSp dst, iRegI src1, immIAdd src2) %{
8000 match(Set dst (OrI src1 src2));
8001
8002 format %{ "ori $dst, $src1, $src2\t#@orI_reg_imm" %}
8003
8004 ins_cost(ALU_COST);
8005 ins_encode %{
8006 __ ori(as_Register($dst$$reg),
8007 as_Register($src1$$reg),
8008 (int32_t)($src2$$constant));
8009 %}
8010
8011 ins_pipe(ialu_reg_imm);
8012 %}
8013
8014 // Register Xor
8015 instruct xorI_reg_reg(iRegINoSp dst, iRegI src1, iRegI src2) %{
8016 match(Set dst (XorI src1 src2));
8017
8018 format %{ "xorr $dst, $src1, $src2\t#@xorI_reg_reg" %}
8019
8020 ins_cost(ALU_COST);
8021 ins_encode %{
8022 __ xorr(as_Register($dst$$reg),
8023 as_Register($src1$$reg),
8024 as_Register($src2$$reg));
8025 %}
8026
8027 ins_pipe(ialu_reg_reg);
8028 %}
8029
8030 // Immediate Xor
8031 instruct xorI_reg_imm(iRegINoSp dst, iRegI src1, immIAdd src2) %{
8032 match(Set dst (XorI src1 src2));
8033
8034 format %{ "xori $dst, $src1, $src2\t#@xorI_reg_imm" %}
8035
8036 ins_cost(ALU_COST);
8037 ins_encode %{
8038 __ xori(as_Register($dst$$reg),
8039 as_Register($src1$$reg),
8040 (int32_t)($src2$$constant));
8041 %}
8042
8043 ins_pipe(ialu_reg_imm);
8044 %}
8045
8046 // Register And Long
8047 instruct andL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
8048 match(Set dst (AndL src1 src2));
8049
8050 format %{ "andr $dst, $src1, $src2\t#@andL_reg_reg" %}
8051
8052 ins_cost(ALU_COST);
8053 ins_encode %{
8054 __ andr(as_Register($dst$$reg),
8055 as_Register($src1$$reg),
8056 as_Register($src2$$reg));
8057 %}
8058
8059 ins_pipe(ialu_reg_reg);
8060 %}
8061
8062 // Immediate And Long
8063 instruct andL_reg_imm(iRegLNoSp dst, iRegL src1, immLAdd src2) %{
8064 match(Set dst (AndL src1 src2));
8065
8066 format %{ "andi $dst, $src1, $src2\t#@andL_reg_imm" %}
8067
8068 ins_cost(ALU_COST);
8069 ins_encode %{
8070 __ andi(as_Register($dst$$reg),
8071 as_Register($src1$$reg),
8072 (int32_t)($src2$$constant));
8073 %}
8074
8075 ins_pipe(ialu_reg_imm);
8076 %}
8077
8078 // Register Or Long
8079 instruct orL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
8080 match(Set dst (OrL src1 src2));
8081
8082 format %{ "orr $dst, $src1, $src2\t#@orL_reg_reg" %}
8083
8084 ins_cost(ALU_COST);
8085 ins_encode %{
8086 __ orr(as_Register($dst$$reg),
8087 as_Register($src1$$reg),
8088 as_Register($src2$$reg));
8089 %}
8090
8091 ins_pipe(ialu_reg_reg);
8092 %}
8093
8094 // Immediate Or Long
8095 instruct orL_reg_imm(iRegLNoSp dst, iRegL src1, immLAdd src2) %{
8096 match(Set dst (OrL src1 src2));
8097
8098 format %{ "ori $dst, $src1, $src2\t#@orL_reg_imm" %}
8099
8100 ins_cost(ALU_COST);
8101 ins_encode %{
8102 __ ori(as_Register($dst$$reg),
8103 as_Register($src1$$reg),
8104 (int32_t)($src2$$constant));
8105 %}
8106
8107 ins_pipe(ialu_reg_imm);
8108 %}
8109
8110 // Register Xor Long
8111 instruct xorL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
8112 match(Set dst (XorL src1 src2));
8113
8114 format %{ "xorr $dst, $src1, $src2\t#@xorL_reg_reg" %}
8115
8116 ins_cost(ALU_COST);
8117 ins_encode %{
8118 __ xorr(as_Register($dst$$reg),
8119 as_Register($src1$$reg),
8120 as_Register($src2$$reg));
8121 %}
8122
8123 ins_pipe(ialu_reg_reg);
8124 %}
8125
8126 // Immediate Xor Long
8127 instruct xorL_reg_imm(iRegLNoSp dst, iRegL src1, immLAdd src2) %{
8128 match(Set dst (XorL src1 src2));
8129
8130 ins_cost(ALU_COST);
8131 format %{ "xori $dst, $src1, $src2\t#@xorL_reg_imm" %}
8132
8133 ins_encode %{
8134 __ xori(as_Register($dst$$reg),
8135 as_Register($src1$$reg),
8136 (int32_t)($src2$$constant));
8137 %}
8138
8139 ins_pipe(ialu_reg_imm);
8140 %}
8141
8142 // ============================================================================
8143 // MemBar Instruction
8144
8145 // RVTSO
8146
8147 instruct unnecessary_membar_rvtso() %{
8148 predicate(UseZtso);
8149 match(LoadFence);
8150 match(StoreFence);
8151 match(StoreStoreFence);
8152 match(MemBarAcquire);
8153 match(MemBarRelease);
8154 match(MemBarStoreStore);
8155 match(MemBarAcquireLock);
8156 match(MemBarReleaseLock);
8157
8158 ins_cost(0);
8159
8160 size(0);
8161
8162 format %{ "#@unnecessary_membar_rvtso elided/tso (empty encoding)" %}
8163 ins_encode %{
8164 __ block_comment("unnecessary_membar_rvtso");
8165 %}
8166 ins_pipe(real_empty);
8167 %}
8168
8169 instruct membar_volatile_rvtso() %{
8170 predicate(UseZtso);
8171 match(MemBarVolatile);
8172 ins_cost(VOLATILE_REF_COST);
8173
8174 format %{ "#@membar_volatile_rvtso\n\t"
8175 "fence w, r"%}
8176
8177 ins_encode %{
8178 __ block_comment("membar_volatile_rvtso");
8179 __ membar(MacroAssembler::StoreLoad);
8180 %}
8181
8182 ins_pipe(pipe_slow);
8183 %}
8184
8185 instruct unnecessary_membar_volatile_rvtso() %{
8186 predicate(UseZtso && Matcher::post_store_load_barrier(n));
8187 match(MemBarVolatile);
8188 ins_cost(0);
8189
8190 size(0);
8191
8192 format %{ "#@unnecessary_membar_volatile_rvtso (unnecessary so empty encoding)" %}
8193 ins_encode %{
8194 __ block_comment("unnecessary_membar_volatile_rvtso");
8195 %}
8196 ins_pipe(real_empty);
8197 %}
8198
8199 // RVWMO
8200
8201 instruct membar_aqcuire_rvwmo() %{
8202 predicate(!UseZtso);
8203 match(LoadFence);
8204 match(MemBarAcquire);
8205 ins_cost(VOLATILE_REF_COST);
8206
8207 format %{ "#@membar_aqcuire_rvwmo\n\t"
8208 "fence r, rw" %}
8209
8210 ins_encode %{
8211 __ block_comment("membar_aqcuire_rvwmo");
8212 __ membar(MacroAssembler::LoadLoad | MacroAssembler::LoadStore);
8213 %}
8214 ins_pipe(pipe_serial);
8215 %}
8216
8217 instruct membar_release_rvwmo() %{
8218 predicate(!UseZtso);
8219 match(StoreFence);
8220 match(MemBarRelease);
8221 ins_cost(VOLATILE_REF_COST);
8222
8223 format %{ "#@membar_release_rvwmo\n\t"
8224 "fence rw, w" %}
8225
8226 ins_encode %{
8227 __ block_comment("membar_release_rvwmo");
8228 __ membar(MacroAssembler::LoadStore | MacroAssembler::StoreStore);
8229 %}
8230 ins_pipe(pipe_serial);
8231 %}
8232
8233 instruct membar_storestore_rvwmo() %{
8234 predicate(!UseZtso);
8235 match(MemBarStoreStore);
8236 match(StoreStoreFence);
8237 ins_cost(VOLATILE_REF_COST);
8238
8239 format %{ "#@membar_storestore_rvwmo\n\t"
8240 "fence w, w" %}
8241
8242 ins_encode %{
8243 __ membar(MacroAssembler::StoreStore);
8244 %}
8245 ins_pipe(pipe_serial);
8246 %}
8247
8248 instruct membar_volatile_rvwmo() %{
8249 predicate(!UseZtso);
8250 match(MemBarVolatile);
8251 ins_cost(VOLATILE_REF_COST);
8252
8253 format %{ "#@membar_volatile_rvwmo\n\t"
8254 "fence w, r"%}
8255
8256 ins_encode %{
8257 __ block_comment("membar_volatile_rvwmo");
8258 __ membar(MacroAssembler::StoreLoad);
8259 %}
8260
8261 ins_pipe(pipe_serial);
8262 %}
8263
8264 instruct membar_lock_rvwmo() %{
8265 predicate(!UseZtso);
8266 match(MemBarAcquireLock);
8267 match(MemBarReleaseLock);
8268 ins_cost(0);
8269
8270 format %{ "#@membar_lock_rvwmo (elided)" %}
8271
8272 ins_encode %{
8273 __ block_comment("membar_lock_rvwmo (elided)");
8274 %}
8275
8276 ins_pipe(pipe_serial);
8277 %}
8278
8279 instruct unnecessary_membar_volatile_rvwmo() %{
8280 predicate(!UseZtso && Matcher::post_store_load_barrier(n));
8281 match(MemBarVolatile);
8282 ins_cost(0);
8283
8284 size(0);
8285 format %{ "#@unnecessary_membar_volatile_rvwmo (unnecessary so empty encoding)" %}
8286 ins_encode %{
8287 __ block_comment("unnecessary_membar_volatile_rvwmo");
8288 %}
8289 ins_pipe(real_empty);
8290 %}
8291
8292 instruct spin_wait() %{
8293 predicate(UseZihintpause);
8294 match(OnSpinWait);
8295 ins_cost(CACHE_MISS_COST);
8296
8297 format %{ "spin_wait" %}
8298
8299 ins_encode %{
8300 __ pause();
8301 %}
8302
8303 ins_pipe(pipe_serial);
8304 %}
8305
8306 // ============================================================================
8307 // Cast Instructions (Java-level type cast)
8308
8309 instruct castX2P(iRegPNoSp dst, iRegL src) %{
8310 match(Set dst (CastX2P src));
8311
8312 ins_cost(ALU_COST);
8313 format %{ "mv $dst, $src\t# long -> ptr, #@castX2P" %}
8314
8315 ins_encode %{
8316 if ($dst$$reg != $src$$reg) {
8317 __ mv(as_Register($dst$$reg), as_Register($src$$reg));
8318 }
8319 %}
8320
8321 ins_pipe(ialu_reg);
8322 %}
8323
8324 instruct castP2X(iRegLNoSp dst, iRegP src) %{
8325 match(Set dst (CastP2X src));
8326
8327 ins_cost(ALU_COST);
8328 format %{ "mv $dst, $src\t# ptr -> long, #@castP2X" %}
8329
8330 ins_encode %{
8331 if ($dst$$reg != $src$$reg) {
8332 __ mv(as_Register($dst$$reg), as_Register($src$$reg));
8333 }
8334 %}
8335
8336 ins_pipe(ialu_reg);
8337 %}
8338
8339 instruct castPP(iRegPNoSp dst)
8340 %{
8341 match(Set dst (CastPP dst));
8342 ins_cost(0);
8343
8344 size(0);
8345 format %{ "# castPP of $dst, #@castPP" %}
8346 ins_encode(/* empty encoding */);
8347 ins_pipe(pipe_class_empty);
8348 %}
8349
8350 instruct castLL(iRegL dst)
8351 %{
8352 match(Set dst (CastLL dst));
8353
8354 size(0);
8355 format %{ "# castLL of $dst, #@castLL" %}
8356 ins_encode(/* empty encoding */);
8357 ins_cost(0);
8358 ins_pipe(pipe_class_empty);
8359 %}
8360
8361 instruct castII(iRegI dst)
8362 %{
8363 match(Set dst (CastII dst));
8364
8365 size(0);
8366 format %{ "# castII of $dst, #@castII" %}
8367 ins_encode(/* empty encoding */);
8368 ins_cost(0);
8369 ins_pipe(pipe_class_empty);
8370 %}
8371
8372 instruct checkCastPP(iRegPNoSp dst)
8373 %{
8374 match(Set dst (CheckCastPP dst));
8375
8376 size(0);
8377 ins_cost(0);
8378 format %{ "# checkcastPP of $dst, #@checkCastPP" %}
8379 ins_encode(/* empty encoding */);
8380 ins_pipe(pipe_class_empty);
8381 %}
8382
8383 instruct castHH(fRegF dst)
8384 %{
8385 match(Set dst (CastHH dst));
8386
8387 size(0);
8388 format %{ "# castHH of $dst" %}
8389 ins_encode(/* empty encoding */);
8390 ins_cost(0);
8391 ins_pipe(pipe_class_empty);
8392 %}
8393
8394 instruct castFF(fRegF dst)
8395 %{
8396 match(Set dst (CastFF dst));
8397
8398 size(0);
8399 format %{ "# castFF of $dst" %}
8400 ins_encode(/* empty encoding */);
8401 ins_cost(0);
8402 ins_pipe(pipe_class_empty);
8403 %}
8404
8405 instruct castDD(fRegD dst)
8406 %{
8407 match(Set dst (CastDD dst));
8408
8409 size(0);
8410 format %{ "# castDD of $dst" %}
8411 ins_encode(/* empty encoding */);
8412 ins_cost(0);
8413 ins_pipe(pipe_class_empty);
8414 %}
8415
8416 instruct castVV(vReg dst)
8417 %{
8418 match(Set dst (CastVV dst));
8419
8420 size(0);
8421 format %{ "# castVV of $dst" %}
8422 ins_encode(/* empty encoding */);
8423 ins_cost(0);
8424 ins_pipe(pipe_class_empty);
8425 %}
8426
8427 instruct castVVMask(vRegMask dst)
8428 %{
8429 match(Set dst (CastVV dst));
8430
8431 size(0);
8432 format %{ "# castVV of $dst" %}
8433 ins_encode(/* empty encoding */);
8434 ins_cost(0);
8435 ins_pipe(pipe_class_empty);
8436 %}
8437
8438 // ============================================================================
8439 // Convert Instructions
8440
8441 // int to bool
8442 instruct convI2Bool(iRegINoSp dst, iRegI src)
8443 %{
8444 match(Set dst (Conv2B src));
8445
8446 ins_cost(ALU_COST);
8447 format %{ "snez $dst, $src\t#@convI2Bool" %}
8448
8449 ins_encode %{
8450 __ snez(as_Register($dst$$reg), as_Register($src$$reg));
8451 %}
8452
8453 ins_pipe(ialu_reg);
8454 %}
8455
8456 // pointer to bool
8457 instruct convP2Bool(iRegINoSp dst, iRegP src)
8458 %{
8459 match(Set dst (Conv2B src));
8460
8461 ins_cost(ALU_COST);
8462 format %{ "snez $dst, $src\t#@convP2Bool" %}
8463
8464 ins_encode %{
8465 __ snez(as_Register($dst$$reg), as_Register($src$$reg));
8466 %}
8467
8468 ins_pipe(ialu_reg);
8469 %}
8470
8471 // int <-> long
8472
8473 instruct convI2L_reg_reg(iRegLNoSp dst, iRegIorL2I src)
8474 %{
8475 match(Set dst (ConvI2L src));
8476
8477 ins_cost(ALU_COST);
8478 format %{ "addw $dst, $src, zr\t#@convI2L_reg_reg" %}
8479 ins_encode %{
8480 __ sext(as_Register($dst$$reg), as_Register($src$$reg), 32);
8481 %}
8482 ins_pipe(ialu_reg);
8483 %}
8484
8485 instruct convL2I_reg(iRegINoSp dst, iRegL src) %{
8486 match(Set dst (ConvL2I src));
8487
8488 ins_cost(ALU_COST);
8489 format %{ "addw $dst, $src, zr\t#@convL2I_reg" %}
8490
8491 ins_encode %{
8492 __ sext(as_Register($dst$$reg), as_Register($src$$reg), 32);
8493 %}
8494
8495 ins_pipe(ialu_reg);
8496 %}
8497
8498 // int to unsigned long (Zero-extend)
8499 instruct convI2UL_reg_reg(iRegLNoSp dst, iRegIorL2I src, immL_32bits mask)
8500 %{
8501 match(Set dst (AndL (ConvI2L src) mask));
8502
8503 ins_cost(ALU_COST * 2);
8504 format %{ "zext $dst, $src, 32\t# i2ul, #@convI2UL_reg_reg" %}
8505
8506 ins_encode %{
8507 __ zext(as_Register($dst$$reg), as_Register($src$$reg), 32);
8508 %}
8509
8510 ins_pipe(ialu_reg_shift);
8511 %}
8512
8513 // float <-> double
8514
8515 instruct convF2D_reg(fRegD dst, fRegF src) %{
8516 match(Set dst (ConvF2D src));
8517
8518 ins_cost(XFER_COST);
8519 format %{ "fcvt.d.s $dst, $src\t#@convF2D_reg" %}
8520
8521 ins_encode %{
8522 __ fcvt_d_s(as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg));
8523 %}
8524
8525 ins_pipe(fp_f2d);
8526 %}
8527
8528 instruct convD2F_reg(fRegF dst, fRegD src) %{
8529 match(Set dst (ConvD2F src));
8530
8531 ins_cost(XFER_COST);
8532 format %{ "fcvt.s.d $dst, $src\t#@convD2F_reg" %}
8533
8534 ins_encode %{
8535 __ fcvt_s_d(as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg));
8536 %}
8537
8538 ins_pipe(fp_d2f);
8539 %}
8540
8541 // single <-> half precision
8542
8543 instruct convHF2F_reg_reg(fRegF dst, iRegINoSp src, iRegINoSp tmp) %{
8544 match(Set dst (ConvHF2F src));
8545 effect(TEMP tmp);
8546 format %{ "fmv.h.x $dst, $src\t# move source from $src to $dst\n\t"
8547 "fcvt.s.h $dst, $dst\t# convert half to single precision"
8548 %}
8549 ins_encode %{
8550 __ float16_to_float($dst$$FloatRegister, $src$$Register, $tmp$$Register);
8551 %}
8552 ins_pipe(pipe_slow);
8553 %}
8554
8555 instruct convF2HF_reg_reg(iRegINoSp dst, fRegF src, fRegF ftmp, iRegINoSp xtmp) %{
8556 match(Set dst (ConvF2HF src));
8557 effect(TEMP_DEF dst, TEMP ftmp, TEMP xtmp);
8558 format %{ "fcvt.h.s $ftmp, $src\t# convert single precision to half\n\t"
8559 "fmv.x.h $dst, $ftmp\t# move result from $ftmp to $dst"
8560 %}
8561 ins_encode %{
8562 __ float_to_float16($dst$$Register, $src$$FloatRegister, $ftmp$$FloatRegister, $xtmp$$Register);
8563 %}
8564 ins_pipe(pipe_slow);
8565 %}
8566
8567 // half precision operations
8568
8569 instruct reinterpretS2HF(fRegF dst, iRegI src)
8570 %{
8571 match(Set dst (ReinterpretS2HF src));
8572 format %{ "fmv.h.x $dst, $src\t# reinterpretS2HF" %}
8573 ins_encode %{
8574 __ fmv_h_x($dst$$FloatRegister, $src$$Register);
8575 %}
8576 ins_pipe(fp_i2f);
8577 %}
8578
8579 instruct convF2HFAndS2HF(fRegF dst, fRegF src)
8580 %{
8581 match(Set dst (ReinterpretS2HF (ConvF2HF src)));
8582 format %{ "convF2HFAndS2HF $dst, $src" %}
8583 ins_encode %{
8584 __ fcvt_h_s($dst$$FloatRegister, $src$$FloatRegister);
8585 %}
8586 ins_pipe(fp_uop_s);
8587 %}
8588
8589 instruct reinterpretHF2S(iRegINoSp dst, fRegF src)
8590 %{
8591 match(Set dst (ReinterpretHF2S src));
8592 format %{ "fmv.x.h $dst, $src\t# reinterpretHF2S" %}
8593 ins_encode %{
8594 __ fmv_x_h($dst$$Register, $src$$FloatRegister);
8595 %}
8596 ins_pipe(fp_f2i);
8597 %}
8598
8599 instruct convHF2SAndHF2F(fRegF dst, fRegF src)
8600 %{
8601 match(Set dst (ConvHF2F (ReinterpretHF2S src)));
8602 format %{ "convHF2SAndHF2F $dst, $src" %}
8603 ins_encode %{
8604 __ fcvt_s_h($dst$$FloatRegister, $src$$FloatRegister);
8605 %}
8606 ins_pipe(fp_uop_s);
8607 %}
8608
8609 instruct sqrt_HF_reg(fRegF dst, fRegF src)
8610 %{
8611 match(Set dst (SqrtHF src));
8612 format %{ "fsqrt.h $dst, $src" %}
8613 ins_encode %{
8614 __ fsqrt_h($dst$$FloatRegister, $src$$FloatRegister);
8615 %}
8616 ins_pipe(fp_sqrt_s);
8617 %}
8618
8619 instruct binOps_HF_reg(fRegF dst, fRegF src1, fRegF src2)
8620 %{
8621 match(Set dst (AddHF src1 src2));
8622 match(Set dst (SubHF src1 src2));
8623 match(Set dst (MulHF src1 src2));
8624 match(Set dst (DivHF src1 src2));
8625 format %{ "binop_hf $dst, $src1, $src2" %}
8626 ins_encode %{
8627 int opcode = this->ideal_Opcode();
8628 switch(opcode) {
8629 case Op_AddHF: __ fadd_h($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); break;
8630 case Op_SubHF: __ fsub_h($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); break;
8631 case Op_MulHF: __ fmul_h($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); break;
8632 case Op_DivHF: __ fdiv_h($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); break;
8633 default: assert(false, "%s is not supported here", NodeClassNames[opcode]); break;
8634 }
8635 %}
8636 ins_pipe(fp_dop_reg_reg_s);
8637 %}
8638
8639 instruct min_HF_reg(fRegF dst, fRegF src1, fRegF src2, rFlagsReg cr)
8640 %{
8641 predicate(!UseZfa);
8642 match(Set dst (MinHF src1 src2));
8643 effect(KILL cr);
8644
8645 format %{ "min_hf $dst, $src1, $src2" %}
8646
8647 ins_encode %{
8648 __ minmax_fp($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister,
8649 __ FLOAT_TYPE::half_precision, true /* is_min */);
8650 %}
8651 ins_pipe(pipe_class_default);
8652 %}
8653
8654 instruct min_HF_reg_zfa(fRegF dst, fRegF src1, fRegF src2)
8655 %{
8656 predicate(UseZfa);
8657 match(Set dst (MinHF src1 src2));
8658
8659 format %{ "min_hf $dst, $src1, $src2" %}
8660
8661 ins_encode %{
8662 __ fminm_h(as_FloatRegister($dst$$reg),
8663 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
8664 %}
8665
8666 ins_pipe(pipe_class_default);
8667 %}
8668
8669 instruct max_HF_reg(fRegF dst, fRegF src1, fRegF src2, rFlagsReg cr)
8670 %{
8671 predicate(!UseZfa);
8672 match(Set dst (MaxHF src1 src2));
8673 effect(KILL cr);
8674
8675 format %{ "max_hf $dst, $src1, $src2" %}
8676
8677 ins_encode %{
8678 __ minmax_fp($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister,
8679 __ FLOAT_TYPE::half_precision, false /* is_min */);
8680 %}
8681 ins_pipe(pipe_class_default);
8682 %}
8683
8684 instruct max_HF_reg_zfa(fRegF dst, fRegF src1, fRegF src2)
8685 %{
8686 predicate(UseZfa);
8687 match(Set dst (MaxHF src1 src2));
8688
8689 format %{ "max_hf $dst, $src1, $src2" %}
8690
8691 ins_encode %{
8692 __ fmaxm_h(as_FloatRegister($dst$$reg),
8693 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
8694 %}
8695
8696 ins_pipe(pipe_class_default);
8697 %}
8698
8699 instruct fma_HF_reg(fRegF dst, fRegF src1, fRegF src2, fRegF src3)
8700 %{
8701 match(Set dst (FmaHF src3 (Binary src1 src2)));
8702 format %{ "fmadd.h $dst, $src1, $src2, $src3\t# $dst = $src1 * $src2 + $src3 fma packedH" %}
8703 ins_encode %{
8704 __ fmadd_h($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister, $src3$$FloatRegister);
8705 %}
8706 ins_pipe(pipe_class_default);
8707 %}
8708
8709 // float <-> int
8710
8711 instruct convF2I_reg_reg(iRegINoSp dst, fRegF src) %{
8712 match(Set dst (ConvF2I src));
8713
8714 ins_cost(XFER_COST);
8715 format %{ "fcvt.w.s $dst, $src\t#@convF2I_reg_reg" %}
8716
8717 ins_encode %{
8718 __ fcvt_w_s_safe($dst$$Register, $src$$FloatRegister);
8719 %}
8720
8721 ins_pipe(fp_f2i);
8722 %}
8723
8724 instruct convI2F_reg_reg(fRegF dst, iRegIorL2I src) %{
8725 match(Set dst (ConvI2F src));
8726
8727 ins_cost(XFER_COST);
8728 format %{ "fcvt.s.w $dst, $src\t#@convI2F_reg_reg" %}
8729
8730 ins_encode %{
8731 __ fcvt_s_w(as_FloatRegister($dst$$reg), as_Register($src$$reg));
8732 %}
8733
8734 ins_pipe(fp_i2f);
8735 %}
8736
8737 // float <-> long
8738
8739 instruct convF2L_reg_reg(iRegLNoSp dst, fRegF src) %{
8740 match(Set dst (ConvF2L src));
8741
8742 ins_cost(XFER_COST);
8743 format %{ "fcvt.l.s $dst, $src\t#@convF2L_reg_reg" %}
8744
8745 ins_encode %{
8746 __ fcvt_l_s_safe($dst$$Register, $src$$FloatRegister);
8747 %}
8748
8749 ins_pipe(fp_f2l);
8750 %}
8751
8752 instruct convL2F_reg_reg(fRegF dst, iRegL src) %{
8753 match(Set dst (ConvL2F src));
8754
8755 ins_cost(XFER_COST);
8756 format %{ "fcvt.s.l $dst, $src\t#@convL2F_reg_reg" %}
8757
8758 ins_encode %{
8759 __ fcvt_s_l(as_FloatRegister($dst$$reg), as_Register($src$$reg));
8760 %}
8761
8762 ins_pipe(fp_l2f);
8763 %}
8764
8765 // double <-> int
8766
8767 instruct convD2I_reg_reg(iRegINoSp dst, fRegD src) %{
8768 match(Set dst (ConvD2I src));
8769
8770 ins_cost(XFER_COST);
8771 format %{ "fcvt.w.d $dst, $src\t#@convD2I_reg_reg" %}
8772
8773 ins_encode %{
8774 __ fcvt_w_d_safe($dst$$Register, $src$$FloatRegister);
8775 %}
8776
8777 ins_pipe(fp_d2i);
8778 %}
8779
8780 instruct convI2D_reg_reg(fRegD dst, iRegIorL2I src) %{
8781 match(Set dst (ConvI2D src));
8782
8783 ins_cost(XFER_COST);
8784 format %{ "fcvt.d.w $dst, $src\t#@convI2D_reg_reg" %}
8785
8786 ins_encode %{
8787 __ fcvt_d_w(as_FloatRegister($dst$$reg), as_Register($src$$reg));
8788 %}
8789
8790 ins_pipe(fp_i2d);
8791 %}
8792
8793 // double <-> long
8794
8795 instruct convD2L_reg_reg(iRegLNoSp dst, fRegD src) %{
8796 match(Set dst (ConvD2L src));
8797
8798 ins_cost(XFER_COST);
8799 format %{ "fcvt.l.d $dst, $src\t#@convD2L_reg_reg" %}
8800
8801 ins_encode %{
8802 __ fcvt_l_d_safe($dst$$Register, $src$$FloatRegister);
8803 %}
8804
8805 ins_pipe(fp_d2l);
8806 %}
8807
8808 instruct convL2D_reg_reg(fRegD dst, iRegL src) %{
8809 match(Set dst (ConvL2D src));
8810
8811 ins_cost(XFER_COST);
8812 format %{ "fcvt.d.l $dst, $src\t#@convL2D_reg_reg" %}
8813
8814 ins_encode %{
8815 __ fcvt_d_l(as_FloatRegister($dst$$reg), as_Register($src$$reg));
8816 %}
8817
8818 ins_pipe(fp_l2d);
8819 %}
8820
8821 // Convert oop into int for vectors alignment masking
8822 instruct convP2I(iRegINoSp dst, iRegP src) %{
8823 match(Set dst (ConvL2I (CastP2X src)));
8824
8825 ins_cost(ALU_COST * 2);
8826 format %{ "zext $dst, $src, 32\t# ptr -> int, #@convP2I" %}
8827
8828 ins_encode %{
8829 __ zext($dst$$Register, $src$$Register, 32);
8830 %}
8831
8832 ins_pipe(ialu_reg);
8833 %}
8834
8835 // Convert compressed oop into int for vectors alignment masking
8836 // in case of 32bit oops (heap < 4Gb).
8837 instruct convN2I(iRegINoSp dst, iRegN src)
8838 %{
8839 predicate(CompressedOops::shift() == 0);
8840 match(Set dst (ConvL2I (CastP2X (DecodeN src))));
8841
8842 ins_cost(ALU_COST);
8843 format %{ "mv $dst, $src\t# compressed ptr -> int, #@convN2I" %}
8844
8845 ins_encode %{
8846 __ mv($dst$$Register, $src$$Register);
8847 %}
8848
8849 ins_pipe(ialu_reg);
8850 %}
8851
8852 instruct round_double_reg(iRegLNoSp dst, fRegD src, fRegD ftmp) %{
8853 match(Set dst (RoundD src));
8854
8855 ins_cost(XFER_COST + BRANCH_COST);
8856 effect(TEMP ftmp);
8857 format %{ "java_round_double $dst, $src\t#@round_double_reg" %}
8858
8859 ins_encode %{
8860 __ java_round_double($dst$$Register, as_FloatRegister($src$$reg), as_FloatRegister($ftmp$$reg));
8861 %}
8862
8863 ins_pipe(pipe_slow);
8864 %}
8865
8866 instruct round_float_reg(iRegINoSp dst, fRegF src, fRegF ftmp) %{
8867 match(Set dst (RoundF src));
8868
8869 ins_cost(XFER_COST + BRANCH_COST);
8870 effect(TEMP ftmp);
8871 format %{ "java_round_float $dst, $src\t#@round_float_reg" %}
8872
8873 ins_encode %{
8874 __ java_round_float($dst$$Register, as_FloatRegister($src$$reg), as_FloatRegister($ftmp$$reg));
8875 %}
8876
8877 ins_pipe(pipe_slow);
8878 %}
8879
8880 // Convert oop pointer into compressed form
8881 instruct encodeHeapOop(iRegNNoSp dst, iRegP src) %{
8882 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
8883 match(Set dst (EncodeP src));
8884 ins_cost(ALU_COST);
8885 format %{ "encode_heap_oop $dst, $src\t#@encodeHeapOop" %}
8886 ins_encode %{
8887 Register s = $src$$Register;
8888 Register d = $dst$$Register;
8889 __ encode_heap_oop(d, s);
8890 %}
8891 ins_pipe(pipe_class_default);
8892 %}
8893
8894 instruct encodeHeapOop_not_null(iRegNNoSp dst, iRegP src) %{
8895 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
8896 match(Set dst (EncodeP src));
8897 ins_cost(ALU_COST);
8898 format %{ "encode_heap_oop_not_null $dst, $src\t#@encodeHeapOop_not_null" %}
8899 ins_encode %{
8900 __ encode_heap_oop_not_null($dst$$Register, $src$$Register);
8901 %}
8902 ins_pipe(pipe_class_default);
8903 %}
8904
8905 instruct decodeHeapOop(iRegPNoSp dst, iRegN src) %{
8906 predicate(n->bottom_type()->is_ptr()->ptr() != TypePtr::NotNull &&
8907 n->bottom_type()->is_ptr()->ptr() != TypePtr::Constant);
8908 match(Set dst (DecodeN src));
8909
8910 ins_cost(0);
8911 format %{ "decode_heap_oop $dst, $src\t#@decodeHeapOop" %}
8912 ins_encode %{
8913 Register s = $src$$Register;
8914 Register d = $dst$$Register;
8915 __ decode_heap_oop(d, s);
8916 %}
8917 ins_pipe(pipe_class_default);
8918 %}
8919
8920 instruct decodeHeapOop_not_null(iRegPNoSp dst, iRegN src) %{
8921 predicate(n->bottom_type()->is_ptr()->ptr() == TypePtr::NotNull ||
8922 n->bottom_type()->is_ptr()->ptr() == TypePtr::Constant);
8923 match(Set dst (DecodeN src));
8924
8925 ins_cost(0);
8926 format %{ "decode_heap_oop_not_null $dst, $src\t#@decodeHeapOop_not_null" %}
8927 ins_encode %{
8928 Register s = $src$$Register;
8929 Register d = $dst$$Register;
8930 __ decode_heap_oop_not_null(d, s);
8931 %}
8932 ins_pipe(pipe_class_default);
8933 %}
8934
8935 // Convert klass pointer into compressed form.
8936 instruct encodeKlass_not_null(iRegNNoSp dst, iRegP src) %{
8937 match(Set dst (EncodePKlass src));
8938
8939 ins_cost(ALU_COST);
8940 format %{ "encode_klass_not_null $dst, $src\t#@encodeKlass_not_null" %}
8941
8942 ins_encode %{
8943 Register src_reg = as_Register($src$$reg);
8944 Register dst_reg = as_Register($dst$$reg);
8945 __ encode_klass_not_null(dst_reg, src_reg, t0);
8946 %}
8947
8948 ins_pipe(pipe_class_default);
8949 %}
8950
8951 instruct decodeKlass_not_null(iRegPNoSp dst, iRegN src, iRegPNoSp tmp) %{
8952 match(Set dst (DecodeNKlass src));
8953
8954 effect(TEMP_DEF dst, TEMP tmp);
8955
8956 ins_cost(ALU_COST);
8957 format %{ "decode_klass_not_null $dst, $src\t#@decodeKlass_not_null" %}
8958
8959 ins_encode %{
8960 Register src_reg = as_Register($src$$reg);
8961 Register dst_reg = as_Register($dst$$reg);
8962 Register tmp_reg = as_Register($tmp$$reg);
8963 __ decode_klass_not_null(dst_reg, src_reg, tmp_reg);
8964 %}
8965
8966 ins_pipe(pipe_class_default);
8967 %}
8968
8969 // stack <-> reg and reg <-> reg shuffles with no conversion
8970
8971 instruct MoveF2I_stack_reg(iRegINoSp dst, stackSlotF src) %{
8972
8973 match(Set dst (MoveF2I src));
8974
8975 effect(DEF dst, USE src);
8976
8977 ins_cost(LOAD_COST);
8978
8979 format %{ "lw $dst, $src\t#@MoveF2I_stack_reg" %}
8980
8981 ins_encode %{
8982 __ lw(as_Register($dst$$reg), Address(sp, $src$$disp));
8983 %}
8984
8985 ins_pipe(iload_reg_reg);
8986
8987 %}
8988
8989 instruct MoveI2F_stack_reg(fRegF dst, stackSlotI src) %{
8990
8991 match(Set dst (MoveI2F src));
8992
8993 effect(DEF dst, USE src);
8994
8995 ins_cost(LOAD_COST);
8996
8997 format %{ "flw $dst, $src\t#@MoveI2F_stack_reg" %}
8998
8999 ins_encode %{
9000 __ flw(as_FloatRegister($dst$$reg), Address(sp, $src$$disp));
9001 %}
9002
9003 ins_pipe(fp_load_mem_s);
9004
9005 %}
9006
9007 instruct MoveD2L_stack_reg(iRegLNoSp dst, stackSlotD src) %{
9008
9009 match(Set dst (MoveD2L src));
9010
9011 effect(DEF dst, USE src);
9012
9013 ins_cost(LOAD_COST);
9014
9015 format %{ "ld $dst, $src\t#@MoveD2L_stack_reg" %}
9016
9017 ins_encode %{
9018 __ ld(as_Register($dst$$reg), Address(sp, $src$$disp));
9019 %}
9020
9021 ins_pipe(iload_reg_reg);
9022
9023 %}
9024
9025 instruct MoveL2D_stack_reg(fRegD dst, stackSlotL src) %{
9026
9027 match(Set dst (MoveL2D src));
9028
9029 effect(DEF dst, USE src);
9030
9031 ins_cost(LOAD_COST);
9032
9033 format %{ "fld $dst, $src\t#@MoveL2D_stack_reg" %}
9034
9035 ins_encode %{
9036 __ fld(as_FloatRegister($dst$$reg), Address(sp, $src$$disp));
9037 %}
9038
9039 ins_pipe(fp_load_mem_d);
9040
9041 %}
9042
9043 instruct MoveF2I_reg_stack(stackSlotI dst, fRegF src) %{
9044
9045 match(Set dst (MoveF2I src));
9046
9047 effect(DEF dst, USE src);
9048
9049 ins_cost(STORE_COST);
9050
9051 format %{ "fsw $src, $dst\t#@MoveF2I_reg_stack" %}
9052
9053 ins_encode %{
9054 __ fsw(as_FloatRegister($src$$reg), Address(sp, $dst$$disp));
9055 %}
9056
9057 ins_pipe(fp_store_reg_s);
9058
9059 %}
9060
9061 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{
9062
9063 match(Set dst (MoveI2F src));
9064
9065 effect(DEF dst, USE src);
9066
9067 ins_cost(STORE_COST);
9068
9069 format %{ "sw $src, $dst\t#@MoveI2F_reg_stack" %}
9070
9071 ins_encode %{
9072 __ sw(as_Register($src$$reg), Address(sp, $dst$$disp));
9073 %}
9074
9075 ins_pipe(istore_reg_reg);
9076
9077 %}
9078
9079 instruct MoveD2L_reg_stack(stackSlotL dst, fRegD src) %{
9080
9081 match(Set dst (MoveD2L src));
9082
9083 effect(DEF dst, USE src);
9084
9085 ins_cost(STORE_COST);
9086
9087 format %{ "fsd $dst, $src\t#@MoveD2L_reg_stack" %}
9088
9089 ins_encode %{
9090 __ fsd(as_FloatRegister($src$$reg), Address(sp, $dst$$disp));
9091 %}
9092
9093 ins_pipe(fp_store_reg_d);
9094
9095 %}
9096
9097 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{
9098
9099 match(Set dst (MoveL2D src));
9100
9101 effect(DEF dst, USE src);
9102
9103 ins_cost(STORE_COST);
9104
9105 format %{ "sd $src, $dst\t#@MoveL2D_reg_stack" %}
9106
9107 ins_encode %{
9108 __ sd(as_Register($src$$reg), Address(sp, $dst$$disp));
9109 %}
9110
9111 ins_pipe(istore_reg_reg);
9112
9113 %}
9114
9115 instruct MoveF2I_reg_reg(iRegINoSp dst, fRegF src) %{
9116
9117 match(Set dst (MoveF2I src));
9118
9119 effect(DEF dst, USE src);
9120
9121 ins_cost(FMVX_COST);
9122
9123 format %{ "fmv.x.w $dst, $src\t#@MoveF2I_reg_reg" %}
9124
9125 ins_encode %{
9126 __ fmv_x_w(as_Register($dst$$reg), as_FloatRegister($src$$reg));
9127 %}
9128
9129 ins_pipe(fp_f2i);
9130
9131 %}
9132
9133 instruct MoveI2F_reg_reg(fRegF dst, iRegI src) %{
9134
9135 match(Set dst (MoveI2F src));
9136
9137 effect(DEF dst, USE src);
9138
9139 ins_cost(FMVX_COST);
9140
9141 format %{ "fmv.w.x $dst, $src\t#@MoveI2F_reg_reg" %}
9142
9143 ins_encode %{
9144 __ fmv_w_x(as_FloatRegister($dst$$reg), as_Register($src$$reg));
9145 %}
9146
9147 ins_pipe(fp_i2f);
9148
9149 %}
9150
9151 instruct MoveD2L_reg_reg(iRegLNoSp dst, fRegD src) %{
9152
9153 match(Set dst (MoveD2L src));
9154
9155 effect(DEF dst, USE src);
9156
9157 ins_cost(FMVX_COST);
9158
9159 format %{ "fmv.x.d $dst, $src\t#@MoveD2L_reg_reg" %}
9160
9161 ins_encode %{
9162 __ fmv_x_d(as_Register($dst$$reg), as_FloatRegister($src$$reg));
9163 %}
9164
9165 ins_pipe(fp_d2l);
9166
9167 %}
9168
9169 instruct MoveL2D_reg_reg(fRegD dst, iRegL src) %{
9170
9171 match(Set dst (MoveL2D src));
9172
9173 effect(DEF dst, USE src);
9174
9175 ins_cost(FMVX_COST);
9176
9177 format %{ "fmv.d.x $dst, $src\t#@MoveL2D_reg_reg" %}
9178
9179 ins_encode %{
9180 __ fmv_d_x(as_FloatRegister($dst$$reg), as_Register($src$$reg));
9181 %}
9182
9183 ins_pipe(fp_l2d);
9184
9185 %}
9186
9187 // ============================================================================
9188 // Compare Instructions which set the result float comparisons in dest register.
9189
9190 instruct cmpF3_reg_reg(iRegINoSp dst, fRegF op1, fRegF op2)
9191 %{
9192 match(Set dst (CmpF3 op1 op2));
9193
9194 ins_cost(XFER_COST * 2 + BRANCH_COST + ALU_COST);
9195 format %{ "flt.s $dst, $op2, $op1\t#@cmpF3_reg_reg\n\t"
9196 "bgtz $dst, done\n\t"
9197 "feq.s $dst, $op1, $op2\n\t"
9198 "addi $dst, $dst, -1\n\t"
9199 "done:"
9200 %}
9201
9202 ins_encode %{
9203 // we want -1 for unordered or less than, 0 for equal and 1 for greater than.
9204 __ float_compare(as_Register($dst$$reg), as_FloatRegister($op1$$reg),
9205 as_FloatRegister($op2$$reg), -1 /*unordered_result < 0*/);
9206 %}
9207
9208 ins_pipe(pipe_class_default);
9209 %}
9210
9211 instruct cmpD3_reg_reg(iRegINoSp dst, fRegD op1, fRegD op2)
9212 %{
9213 match(Set dst (CmpD3 op1 op2));
9214
9215 ins_cost(XFER_COST * 2 + BRANCH_COST + ALU_COST);
9216 format %{ "flt.d $dst, $op2, $op1\t#@cmpD3_reg_reg\n\t"
9217 "bgtz $dst, done\n\t"
9218 "feq.d $dst, $op1, $op2\n\t"
9219 "addi $dst, $dst, -1\n\t"
9220 "done:"
9221 %}
9222
9223 ins_encode %{
9224 // we want -1 for unordered or less than, 0 for equal and 1 for greater than.
9225 __ double_compare(as_Register($dst$$reg), as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg), -1 /*unordered_result < 0*/);
9226 %}
9227
9228 ins_pipe(pipe_class_default);
9229 %}
9230
9231 instruct cmpL3_reg_reg(iRegINoSp dst, iRegL op1, iRegL op2)
9232 %{
9233 match(Set dst (CmpL3 op1 op2));
9234
9235 ins_cost(ALU_COST * 3 + BRANCH_COST);
9236 format %{ "slt $dst, $op2, $op1\t#@cmpL3_reg_reg\n\t"
9237 "bnez $dst, done\n\t"
9238 "slt $dst, $op1, $op2\n\t"
9239 "neg $dst, $dst\n\t"
9240 "done:"
9241 %}
9242 ins_encode %{
9243 __ cmp_l2i(t0, as_Register($op1$$reg), as_Register($op2$$reg));
9244 __ mv(as_Register($dst$$reg), t0);
9245 %}
9246
9247 ins_pipe(pipe_class_default);
9248 %}
9249
9250 instruct cmpUL3_reg_reg(iRegINoSp dst, iRegL op1, iRegL op2)
9251 %{
9252 match(Set dst (CmpUL3 op1 op2));
9253
9254 ins_cost(ALU_COST * 3 + BRANCH_COST);
9255 format %{ "sltu $dst, $op2, $op1\t#@cmpUL3_reg_reg\n\t"
9256 "bnez $dst, done\n\t"
9257 "sltu $dst, $op1, $op2\n\t"
9258 "neg $dst, $dst\n\t"
9259 "done:"
9260 %}
9261 ins_encode %{
9262 __ cmp_ul2i(t0, as_Register($op1$$reg), as_Register($op2$$reg));
9263 __ mv(as_Register($dst$$reg), t0);
9264 %}
9265
9266 ins_pipe(pipe_class_default);
9267 %}
9268
9269 instruct cmpU3_reg_reg(iRegINoSp dst, iRegI op1, iRegI op2)
9270 %{
9271 match(Set dst (CmpU3 op1 op2));
9272
9273 ins_cost(ALU_COST * 3 + BRANCH_COST);
9274 format %{ "sltu $dst, $op2, $op1\t#@cmpU3_reg_reg\n\t"
9275 "bnez $dst, done\n\t"
9276 "sltu $dst, $op1, $op2\n\t"
9277 "neg $dst, $dst\n\t"
9278 "done:"
9279 %}
9280 ins_encode %{
9281 __ cmp_uw2i(t0, as_Register($op1$$reg), as_Register($op2$$reg));
9282 __ mv(as_Register($dst$$reg), t0);
9283 %}
9284
9285 ins_pipe(pipe_class_default);
9286 %}
9287
9288 instruct cmpLTMask_reg_reg(iRegINoSp dst, iRegI p, iRegI q)
9289 %{
9290 match(Set dst (CmpLTMask p q));
9291
9292 ins_cost(2 * ALU_COST);
9293
9294 format %{ "slt $dst, $p, $q\t#@cmpLTMask_reg_reg\n\t"
9295 "subw $dst, zr, $dst\t#@cmpLTMask_reg_reg"
9296 %}
9297
9298 ins_encode %{
9299 __ slt(as_Register($dst$$reg), as_Register($p$$reg), as_Register($q$$reg));
9300 __ subw(as_Register($dst$$reg), zr, as_Register($dst$$reg));
9301 %}
9302
9303 ins_pipe(ialu_reg_reg);
9304 %}
9305
9306 instruct cmpLTMask_reg_zero(iRegINoSp dst, iRegIorL2I op, immI0 zero)
9307 %{
9308 match(Set dst (CmpLTMask op zero));
9309
9310 ins_cost(ALU_COST);
9311
9312 format %{ "sraiw $dst, $dst, 31\t#@cmpLTMask_reg_reg" %}
9313
9314 ins_encode %{
9315 __ sraiw(as_Register($dst$$reg), as_Register($op$$reg), 31);
9316 %}
9317
9318 ins_pipe(ialu_reg_shift);
9319 %}
9320
9321
9322 // ============================================================================
9323 // Max and Min
9324
9325 instruct minI_reg_reg(iRegINoSp dst, iRegI src)
9326 %{
9327 match(Set dst (MinI dst src));
9328
9329 ins_cost(BRANCH_COST + ALU_COST);
9330 format %{"minI_reg_reg $dst, $dst, $src\t#@minI_reg_reg\n\t"%}
9331
9332 ins_encode %{
9333 __ cmov_gt(as_Register($dst$$reg), as_Register($src$$reg),
9334 as_Register($dst$$reg), as_Register($src$$reg));
9335 %}
9336
9337 ins_pipe(pipe_class_compare);
9338 %}
9339
9340 instruct maxI_reg_reg(iRegINoSp dst, iRegI src)
9341 %{
9342 match(Set dst (MaxI dst src));
9343
9344 ins_cost(BRANCH_COST + ALU_COST);
9345 format %{"maxI_reg_reg $dst, $dst, $src\t#@maxI_reg_reg\n\t"%}
9346
9347 ins_encode %{
9348 __ cmov_lt(as_Register($dst$$reg), as_Register($src$$reg),
9349 as_Register($dst$$reg), as_Register($src$$reg));
9350 %}
9351
9352 ins_pipe(pipe_class_compare);
9353 %}
9354
9355 // special case for comparing with zero
9356 // n.b. this is selected in preference to the rule above because it
9357 // avoids loading constant 0 into a source register
9358
9359 instruct minI_reg_zero(iRegINoSp dst, immI0 zero)
9360 %{
9361 match(Set dst (MinI dst zero));
9362 match(Set dst (MinI zero dst));
9363
9364 ins_cost(BRANCH_COST + ALU_COST);
9365 format %{"minI_reg_zero $dst, $dst, zr\t#@minI_reg_zero\n\t"%}
9366
9367 ins_encode %{
9368 __ cmov_gt(as_Register($dst$$reg), zr,
9369 as_Register($dst$$reg), zr);
9370 %}
9371
9372 ins_pipe(pipe_class_compare);
9373 %}
9374
9375 instruct maxI_reg_zero(iRegINoSp dst, immI0 zero)
9376 %{
9377 match(Set dst (MaxI dst zero));
9378 match(Set dst (MaxI zero dst));
9379
9380 ins_cost(BRANCH_COST + ALU_COST);
9381 format %{"maxI_reg_zero $dst, $dst, zr\t#@maxI_reg_zero\n\t"%}
9382
9383 ins_encode %{
9384 __ cmov_lt(as_Register($dst$$reg), zr,
9385 as_Register($dst$$reg), zr);
9386 %}
9387
9388 ins_pipe(pipe_class_compare);
9389 %}
9390
9391 instruct minI_rReg(iRegINoSp dst, iRegI src1, iRegI src2)
9392 %{
9393 match(Set dst (MinI src1 src2));
9394
9395 effect(DEF dst, USE src1, USE src2);
9396
9397 ins_cost(BRANCH_COST + ALU_COST * 2);
9398 format %{"minI_rReg $dst, $src1, $src2\t#@minI_rReg\n\t"%}
9399
9400 ins_encode %{
9401 __ mv(as_Register($dst$$reg), as_Register($src1$$reg));
9402 __ cmov_gt(as_Register($src1$$reg), as_Register($src2$$reg),
9403 as_Register($dst$$reg), as_Register($src2$$reg));
9404 %}
9405
9406 ins_pipe(pipe_class_compare);
9407 %}
9408
9409 instruct maxI_rReg(iRegINoSp dst, iRegI src1, iRegI src2)
9410 %{
9411 match(Set dst (MaxI src1 src2));
9412
9413 effect(DEF dst, USE src1, USE src2);
9414
9415 ins_cost(BRANCH_COST + ALU_COST * 2);
9416 format %{"maxI_rReg $dst, $src1, $src2\t#@maxI_rReg\n\t"%}
9417
9418 ins_encode %{
9419 __ mv(as_Register($dst$$reg), as_Register($src1$$reg));
9420 __ cmov_lt(as_Register($src1$$reg), as_Register($src2$$reg),
9421 as_Register($dst$$reg), as_Register($src2$$reg));
9422 %}
9423
9424 ins_pipe(pipe_class_compare);
9425 %}
9426
9427 // ============================================================================
9428 // Branch Instructions
9429 // Direct Branch.
9430 instruct branch(label lbl)
9431 %{
9432 match(Goto);
9433
9434 effect(USE lbl);
9435
9436 ins_cost(BRANCH_COST);
9437 format %{ "j $lbl\t#@branch" %}
9438
9439 ins_encode(riscv_enc_j(lbl));
9440
9441 ins_pipe(pipe_branch);
9442 %}
9443
9444 // ============================================================================
9445 // Compare and Branch Instructions
9446
9447 // Patterns for short (< 12KiB) variants
9448
9449 // Compare flags and branch near instructions.
9450 instruct cmpFlag_branch(cmpOpEqNe cmp, rFlagsReg cr, label lbl) %{
9451 match(If cmp cr);
9452 effect(USE lbl);
9453
9454 ins_cost(BRANCH_COST);
9455 format %{ "b$cmp $cr, zr, $lbl\t#@cmpFlag_branch" %}
9456
9457 ins_encode %{
9458 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($cr$$reg), *($lbl$$label));
9459 %}
9460 ins_pipe(pipe_cmpz_branch);
9461 ins_short_branch(1);
9462 %}
9463
9464 // Compare signed int and branch near instructions
9465 instruct cmpI_branch(cmpOp cmp, iRegI op1, iRegI op2, label lbl)
9466 %{
9467 // Same match rule as `far_cmpI_branch'.
9468 match(If cmp (CmpI op1 op2));
9469
9470 effect(USE lbl);
9471
9472 ins_cost(BRANCH_COST);
9473
9474 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpI_branch" %}
9475
9476 ins_encode %{
9477 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label));
9478 %}
9479
9480 ins_pipe(pipe_cmp_branch);
9481 ins_short_branch(1);
9482 %}
9483
9484 instruct cmpI_loop(cmpOp cmp, iRegI op1, iRegI op2, label lbl)
9485 %{
9486 // Same match rule as `far_cmpI_loop'.
9487 match(CountedLoopEnd cmp (CmpI op1 op2));
9488
9489 effect(USE lbl);
9490
9491 ins_cost(BRANCH_COST);
9492
9493 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpI_loop" %}
9494
9495 ins_encode %{
9496 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label));
9497 %}
9498
9499 ins_pipe(pipe_cmp_branch);
9500 ins_short_branch(1);
9501 %}
9502
9503 // Compare unsigned int and branch near instructions
9504 instruct cmpU_branch(cmpOpU cmp, iRegI op1, iRegI op2, label lbl)
9505 %{
9506 // Same match rule as `far_cmpU_branch'.
9507 match(If cmp (CmpU op1 op2));
9508
9509 effect(USE lbl);
9510
9511 ins_cost(BRANCH_COST);
9512
9513 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpU_branch" %}
9514
9515 ins_encode %{
9516 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9517 as_Register($op2$$reg), *($lbl$$label));
9518 %}
9519
9520 ins_pipe(pipe_cmp_branch);
9521 ins_short_branch(1);
9522 %}
9523
9524 // Compare signed long and branch near instructions
9525 instruct cmpL_branch(cmpOp cmp, iRegL op1, iRegL op2, label lbl)
9526 %{
9527 // Same match rule as `far_cmpL_branch'.
9528 match(If cmp (CmpL op1 op2));
9529
9530 effect(USE lbl);
9531
9532 ins_cost(BRANCH_COST);
9533
9534 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpL_branch" %}
9535
9536 ins_encode %{
9537 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label));
9538 %}
9539
9540 ins_pipe(pipe_cmp_branch);
9541 ins_short_branch(1);
9542 %}
9543
9544 instruct cmpL_loop(cmpOp cmp, iRegL op1, iRegL op2, label lbl)
9545 %{
9546 // Same match rule as `far_cmpL_loop'.
9547 match(CountedLoopEnd cmp (CmpL op1 op2));
9548
9549 effect(USE lbl);
9550
9551 ins_cost(BRANCH_COST);
9552
9553 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpL_loop" %}
9554
9555 ins_encode %{
9556 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label));
9557 %}
9558
9559 ins_pipe(pipe_cmp_branch);
9560 ins_short_branch(1);
9561 %}
9562
9563 // Compare unsigned long and branch near instructions
9564 instruct cmpUL_branch(cmpOpU cmp, iRegL op1, iRegL op2, label lbl)
9565 %{
9566 // Same match rule as `far_cmpUL_branch'.
9567 match(If cmp (CmpUL op1 op2));
9568
9569 effect(USE lbl);
9570
9571 ins_cost(BRANCH_COST);
9572 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpUL_branch" %}
9573
9574 ins_encode %{
9575 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9576 as_Register($op2$$reg), *($lbl$$label));
9577 %}
9578
9579 ins_pipe(pipe_cmp_branch);
9580 ins_short_branch(1);
9581 %}
9582
9583 // Compare pointer and branch near instructions
9584 instruct cmpP_branch(cmpOpU cmp, iRegP op1, iRegP op2, label lbl)
9585 %{
9586 // Same match rule as `far_cmpP_branch'.
9587 match(If cmp (CmpP op1 op2));
9588
9589 effect(USE lbl);
9590
9591 ins_cost(BRANCH_COST);
9592
9593 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpP_branch" %}
9594
9595 ins_encode %{
9596 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9597 as_Register($op2$$reg), *($lbl$$label));
9598 %}
9599
9600 ins_pipe(pipe_cmp_branch);
9601 ins_short_branch(1);
9602 %}
9603
9604 // Compare narrow pointer and branch near instructions
9605 instruct cmpN_branch(cmpOpU cmp, iRegN op1, iRegN op2, label lbl)
9606 %{
9607 // Same match rule as `far_cmpN_branch'.
9608 match(If cmp (CmpN op1 op2));
9609
9610 effect(USE lbl);
9611
9612 ins_cost(BRANCH_COST);
9613
9614 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpN_branch" %}
9615
9616 ins_encode %{
9617 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9618 as_Register($op2$$reg), *($lbl$$label));
9619 %}
9620
9621 ins_pipe(pipe_cmp_branch);
9622 ins_short_branch(1);
9623 %}
9624
9625 // Compare float and branch near instructions
9626 instruct cmpF_branch(cmpOp cmp, fRegF op1, fRegF op2, label lbl)
9627 %{
9628 // Same match rule as `far_cmpF_branch'.
9629 match(If cmp (CmpF op1 op2));
9630
9631 effect(USE lbl);
9632
9633 ins_cost(XFER_COST + BRANCH_COST);
9634 format %{ "float_b$cmp $op1, $op2, $lbl \t#@cmpF_branch"%}
9635
9636 ins_encode %{
9637 __ float_cmp_branch($cmp$$cmpcode, as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg), *($lbl$$label));
9638 %}
9639
9640 ins_pipe(pipe_class_compare);
9641 ins_short_branch(1);
9642 %}
9643
9644 // Compare double and branch near instructions
9645 instruct cmpD_branch(cmpOp cmp, fRegD op1, fRegD op2, label lbl)
9646 %{
9647 // Same match rule as `far_cmpD_branch'.
9648 match(If cmp (CmpD op1 op2));
9649 effect(USE lbl);
9650
9651 ins_cost(XFER_COST + BRANCH_COST);
9652 format %{ "double_b$cmp $op1, $op2, $lbl\t#@cmpD_branch"%}
9653
9654 ins_encode %{
9655 __ float_cmp_branch($cmp$$cmpcode | C2_MacroAssembler::double_branch_mask, as_FloatRegister($op1$$reg),
9656 as_FloatRegister($op2$$reg), *($lbl$$label));
9657 %}
9658
9659 ins_pipe(pipe_class_compare);
9660 ins_short_branch(1);
9661 %}
9662
9663 // Compare signed int with zero and branch near instructions
9664 instruct cmpI_reg_imm0_branch(cmpOp cmp, iRegI op1, immI0 zero, label lbl)
9665 %{
9666 // Same match rule as `far_cmpI_reg_imm0_branch'.
9667 match(If cmp (CmpI op1 zero));
9668
9669 effect(USE op1, USE lbl);
9670
9671 ins_cost(BRANCH_COST);
9672 format %{ "b$cmp $op1, zr, $lbl\t#@cmpI_reg_imm0_branch" %}
9673
9674 ins_encode %{
9675 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label));
9676 %}
9677
9678 ins_pipe(pipe_cmpz_branch);
9679 ins_short_branch(1);
9680 %}
9681
9682 instruct cmpI_reg_imm0_loop(cmpOp cmp, iRegI op1, immI0 zero, label lbl)
9683 %{
9684 // Same match rule as `far_cmpI_reg_imm0_loop'.
9685 match(CountedLoopEnd cmp (CmpI op1 zero));
9686
9687 effect(USE op1, USE lbl);
9688
9689 ins_cost(BRANCH_COST);
9690
9691 format %{ "b$cmp $op1, zr, $lbl\t#@cmpI_reg_imm0_loop" %}
9692
9693 ins_encode %{
9694 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label));
9695 %}
9696
9697 ins_pipe(pipe_cmpz_branch);
9698 ins_short_branch(1);
9699 %}
9700
9701 // Compare unsigned int with zero and branch near instructions
9702 instruct cmpUEqNeLeGt_reg_imm0_branch(cmpOpUEqNeLeGt cmp, iRegI op1, immI0 zero, label lbl)
9703 %{
9704 // Same match rule as `far_cmpUEqNeLeGt_reg_imm0_branch'.
9705 match(If cmp (CmpU op1 zero));
9706
9707 effect(USE op1, USE lbl);
9708
9709 ins_cost(BRANCH_COST);
9710
9711 format %{ "b$cmp $op1, zr, $lbl\t#@cmpUEqNeLeGt_reg_imm0_branch" %}
9712
9713 ins_encode %{
9714 __ enc_cmpUEqNeLeGt_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
9715 %}
9716
9717 ins_pipe(pipe_cmpz_branch);
9718 ins_short_branch(1);
9719 %}
9720
9721 // Compare signed long with zero and branch near instructions
9722 instruct cmpL_reg_imm0_branch(cmpOp cmp, iRegL op1, immL0 zero, label lbl)
9723 %{
9724 // Same match rule as `far_cmpL_reg_imm0_branch'.
9725 match(If cmp (CmpL op1 zero));
9726
9727 effect(USE op1, USE lbl);
9728
9729 ins_cost(BRANCH_COST);
9730
9731 format %{ "b$cmp $op1, zr, $lbl\t#@cmpL_reg_imm0_branch" %}
9732
9733 ins_encode %{
9734 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label));
9735 %}
9736
9737 ins_pipe(pipe_cmpz_branch);
9738 ins_short_branch(1);
9739 %}
9740
9741 instruct cmpL_reg_imm0_loop(cmpOp cmp, iRegL op1, immL0 zero, label lbl)
9742 %{
9743 // Same match rule as `far_cmpL_reg_imm0_loop'.
9744 match(CountedLoopEnd cmp (CmpL op1 zero));
9745
9746 effect(USE op1, USE lbl);
9747
9748 ins_cost(BRANCH_COST);
9749
9750 format %{ "b$cmp $op1, zr, $lbl\t#@cmpL_reg_imm0_loop" %}
9751
9752 ins_encode %{
9753 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label));
9754 %}
9755
9756 ins_pipe(pipe_cmpz_branch);
9757 ins_short_branch(1);
9758 %}
9759
9760 // Compare unsigned long with zero and branch near instructions
9761 instruct cmpULEqNeLeGt_reg_imm0_branch(cmpOpUEqNeLeGt cmp, iRegL op1, immL0 zero, label lbl)
9762 %{
9763 // Same match rule as `far_cmpULEqNeLeGt_reg_imm0_branch'.
9764 match(If cmp (CmpUL op1 zero));
9765
9766 effect(USE op1, USE lbl);
9767
9768 ins_cost(BRANCH_COST);
9769
9770 format %{ "b$cmp $op1, zr, $lbl\t#@cmpULEqNeLeGt_reg_imm0_branch" %}
9771
9772 ins_encode %{
9773 __ enc_cmpUEqNeLeGt_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
9774 %}
9775
9776 ins_pipe(pipe_cmpz_branch);
9777 ins_short_branch(1);
9778 %}
9779
9780 // Compare pointer with zero and branch near instructions
9781 instruct cmpP_imm0_branch(cmpOpEqNe cmp, iRegP op1, immP0 zero, label lbl) %{
9782 // Same match rule as `far_cmpP_reg_imm0_branch'.
9783 match(If cmp (CmpP op1 zero));
9784 effect(USE lbl);
9785
9786 ins_cost(BRANCH_COST);
9787 format %{ "b$cmp $op1, zr, $lbl\t#@cmpP_imm0_branch" %}
9788
9789 ins_encode %{
9790 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
9791 %}
9792
9793 ins_pipe(pipe_cmpz_branch);
9794 ins_short_branch(1);
9795 %}
9796
9797 // Compare narrow pointer with zero and branch near instructions
9798 instruct cmpN_imm0_branch(cmpOpEqNe cmp, iRegN op1, immN0 zero, label lbl) %{
9799 // Same match rule as `far_cmpN_reg_imm0_branch'.
9800 match(If cmp (CmpN op1 zero));
9801 effect(USE lbl);
9802
9803 ins_cost(BRANCH_COST);
9804
9805 format %{ "b$cmp $op1, zr, $lbl\t#@cmpN_imm0_branch" %}
9806
9807 ins_encode %{
9808 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
9809 %}
9810
9811 ins_pipe(pipe_cmpz_branch);
9812 ins_short_branch(1);
9813 %}
9814
9815 // Compare narrow pointer with pointer zero and branch near instructions
9816 instruct cmpP_narrowOop_imm0_branch(cmpOpEqNe cmp, iRegN op1, immP0 zero, label lbl) %{
9817 // Same match rule as `far_cmpP_narrowOop_imm0_branch'.
9818 match(If cmp (CmpP (DecodeN op1) zero));
9819 effect(USE lbl);
9820
9821 ins_cost(BRANCH_COST);
9822 format %{ "b$cmp $op1, zr, $lbl\t#@cmpP_narrowOop_imm0_branch" %}
9823
9824 ins_encode %{
9825 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
9826 %}
9827
9828 ins_pipe(pipe_cmpz_branch);
9829 ins_short_branch(1);
9830 %}
9831
9832 // Patterns for far (20KiB) variants
9833
9834 instruct far_cmpFlag_branch(cmpOp cmp, rFlagsReg cr, label lbl) %{
9835 match(If cmp cr);
9836 effect(USE lbl);
9837
9838 ins_cost(BRANCH_COST);
9839 format %{ "far_b$cmp $cr, zr, $lbl\t#@far_cmpFlag_branch"%}
9840
9841 ins_encode %{
9842 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($cr$$reg), *($lbl$$label), /* is_far */ true);
9843 %}
9844
9845 ins_pipe(pipe_cmpz_branch);
9846 %}
9847
9848 // Compare signed int and branch far instructions
9849 instruct far_cmpI_branch(cmpOp cmp, iRegI op1, iRegI op2, label lbl) %{
9850 match(If cmp (CmpI op1 op2));
9851 effect(USE lbl);
9852
9853 ins_cost(BRANCH_COST * 2);
9854
9855 // the format instruction [far_b$cmp] here is be used as two insructions
9856 // in macroassembler: b$not_cmp(op1, op2, done), j($lbl), bind(done)
9857 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpI_branch" %}
9858
9859 ins_encode %{
9860 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9861 %}
9862
9863 ins_pipe(pipe_cmp_branch);
9864 %}
9865
9866 instruct far_cmpI_loop(cmpOp cmp, iRegI op1, iRegI op2, label lbl) %{
9867 match(CountedLoopEnd cmp (CmpI op1 op2));
9868 effect(USE lbl);
9869
9870 ins_cost(BRANCH_COST * 2);
9871 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpI_loop" %}
9872
9873 ins_encode %{
9874 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9875 %}
9876
9877 ins_pipe(pipe_cmp_branch);
9878 %}
9879
9880 instruct far_cmpU_branch(cmpOpU cmp, iRegI op1, iRegI op2, label lbl) %{
9881 match(If cmp (CmpU op1 op2));
9882 effect(USE lbl);
9883
9884 ins_cost(BRANCH_COST * 2);
9885 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpU_branch" %}
9886
9887 ins_encode %{
9888 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9889 as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9890 %}
9891
9892 ins_pipe(pipe_cmp_branch);
9893 %}
9894
9895 instruct far_cmpL_branch(cmpOp cmp, iRegL op1, iRegL op2, label lbl) %{
9896 match(If cmp (CmpL op1 op2));
9897 effect(USE lbl);
9898
9899 ins_cost(BRANCH_COST * 2);
9900 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpL_branch" %}
9901
9902 ins_encode %{
9903 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9904 %}
9905
9906 ins_pipe(pipe_cmp_branch);
9907 %}
9908
9909 instruct far_cmpLloop(cmpOp cmp, iRegL op1, iRegL op2, label lbl) %{
9910 match(CountedLoopEnd cmp (CmpL op1 op2));
9911 effect(USE lbl);
9912
9913 ins_cost(BRANCH_COST * 2);
9914 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpL_loop" %}
9915
9916 ins_encode %{
9917 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9918 %}
9919
9920 ins_pipe(pipe_cmp_branch);
9921 %}
9922
9923 instruct far_cmpUL_branch(cmpOpU cmp, iRegL op1, iRegL op2, label lbl) %{
9924 match(If cmp (CmpUL op1 op2));
9925 effect(USE lbl);
9926
9927 ins_cost(BRANCH_COST * 2);
9928 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpUL_branch" %}
9929
9930 ins_encode %{
9931 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9932 as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9933 %}
9934
9935 ins_pipe(pipe_cmp_branch);
9936 %}
9937
9938 instruct far_cmpP_branch(cmpOpU cmp, iRegP op1, iRegP op2, label lbl)
9939 %{
9940 match(If cmp (CmpP op1 op2));
9941
9942 effect(USE lbl);
9943
9944 ins_cost(BRANCH_COST * 2);
9945
9946 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpP_branch" %}
9947
9948 ins_encode %{
9949 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9950 as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9951 %}
9952
9953 ins_pipe(pipe_cmp_branch);
9954 %}
9955
9956 instruct far_cmpN_branch(cmpOpU cmp, iRegN op1, iRegN op2, label lbl)
9957 %{
9958 match(If cmp (CmpN op1 op2));
9959
9960 effect(USE lbl);
9961
9962 ins_cost(BRANCH_COST * 2);
9963
9964 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpN_branch" %}
9965
9966 ins_encode %{
9967 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9968 as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9969 %}
9970
9971 ins_pipe(pipe_cmp_branch);
9972 %}
9973
9974 // Float compare and branch instructions
9975 instruct far_cmpF_branch(cmpOp cmp, fRegF op1, fRegF op2, label lbl)
9976 %{
9977 match(If cmp (CmpF op1 op2));
9978
9979 effect(USE lbl);
9980
9981 ins_cost(XFER_COST + BRANCH_COST * 2);
9982 format %{ "far_float_b$cmp $op1, $op2, $lbl\t#@far_cmpF_branch"%}
9983
9984 ins_encode %{
9985 __ float_cmp_branch($cmp$$cmpcode, as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg),
9986 *($lbl$$label), /* is_far */ true);
9987 %}
9988
9989 ins_pipe(pipe_class_compare);
9990 %}
9991
9992 // Double compare and branch instructions
9993 instruct far_cmpD_branch(cmpOp cmp, fRegD op1, fRegD op2, label lbl)
9994 %{
9995 match(If cmp (CmpD op1 op2));
9996 effect(USE lbl);
9997
9998 ins_cost(XFER_COST + BRANCH_COST * 2);
9999 format %{ "far_double_b$cmp $op1, $op2, $lbl\t#@far_cmpD_branch"%}
10000
10001 ins_encode %{
10002 __ float_cmp_branch($cmp$$cmpcode | C2_MacroAssembler::double_branch_mask, as_FloatRegister($op1$$reg),
10003 as_FloatRegister($op2$$reg), *($lbl$$label), /* is_far */ true);
10004 %}
10005
10006 ins_pipe(pipe_class_compare);
10007 %}
10008
10009 instruct far_cmpI_reg_imm0_branch(cmpOp cmp, iRegI op1, immI0 zero, label lbl)
10010 %{
10011 match(If cmp (CmpI op1 zero));
10012
10013 effect(USE op1, USE lbl);
10014
10015 ins_cost(BRANCH_COST * 2);
10016
10017 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpI_reg_imm0_branch" %}
10018
10019 ins_encode %{
10020 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label), /* is_far */ true);
10021 %}
10022
10023 ins_pipe(pipe_cmpz_branch);
10024 %}
10025
10026 instruct far_cmpI_reg_imm0_loop(cmpOp cmp, iRegI op1, immI0 zero, label lbl)
10027 %{
10028 match(CountedLoopEnd cmp (CmpI op1 zero));
10029
10030 effect(USE op1, USE lbl);
10031
10032 ins_cost(BRANCH_COST * 2);
10033
10034 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpI_reg_imm0_loop" %}
10035
10036 ins_encode %{
10037 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label), /* is_far */ true);
10038 %}
10039
10040 ins_pipe(pipe_cmpz_branch);
10041 %}
10042
10043 instruct far_cmpUEqNeLeGt_imm0_branch(cmpOpUEqNeLeGt cmp, iRegI op1, immI0 zero, label lbl)
10044 %{
10045 match(If cmp (CmpU op1 zero));
10046
10047 effect(USE op1, USE lbl);
10048
10049 ins_cost(BRANCH_COST * 2);
10050
10051 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpUEqNeLeGt_imm0_branch" %}
10052
10053 ins_encode %{
10054 __ enc_cmpUEqNeLeGt_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
10055 %}
10056
10057 ins_pipe(pipe_cmpz_branch);
10058 %}
10059
10060 // compare lt/ge unsigned instructs has no short instruct with same match
10061 instruct far_cmpULtGe_reg_imm0_branch(cmpOpULtGe cmp, iRegI op1, immI0 zero, label lbl)
10062 %{
10063 match(If cmp (CmpU op1 zero));
10064
10065 effect(USE op1, USE lbl);
10066
10067 ins_cost(BRANCH_COST);
10068
10069 format %{ "j $lbl if $cmp == ge\t#@far_cmpULtGe_reg_imm0_branch" %}
10070
10071 ins_encode(riscv_enc_far_cmpULtGe_imm0_branch(cmp, op1, lbl));
10072
10073 ins_pipe(pipe_cmpz_branch);
10074 %}
10075
10076 instruct far_cmpL_reg_imm0_branch(cmpOp cmp, iRegL op1, immL0 zero, label lbl)
10077 %{
10078 match(If cmp (CmpL op1 zero));
10079
10080 effect(USE op1, USE lbl);
10081
10082 ins_cost(BRANCH_COST * 2);
10083
10084 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpL_reg_imm0_branch" %}
10085
10086 ins_encode %{
10087 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label), /* is_far */ true);
10088 %}
10089
10090 ins_pipe(pipe_cmpz_branch);
10091 %}
10092
10093 instruct far_cmpL_reg_imm0_loop(cmpOp cmp, iRegL op1, immL0 zero, label lbl)
10094 %{
10095 match(CountedLoopEnd cmp (CmpL op1 zero));
10096
10097 effect(USE op1, USE lbl);
10098
10099 ins_cost(BRANCH_COST * 2);
10100
10101 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpL_reg_imm0_loop" %}
10102
10103 ins_encode %{
10104 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label), /* is_far */ true);
10105 %}
10106
10107 ins_pipe(pipe_cmpz_branch);
10108 %}
10109
10110 instruct far_cmpULEqNeLeGt_reg_imm0_branch(cmpOpUEqNeLeGt cmp, iRegL op1, immL0 zero, label lbl)
10111 %{
10112 match(If cmp (CmpUL op1 zero));
10113
10114 effect(USE op1, USE lbl);
10115
10116 ins_cost(BRANCH_COST * 2);
10117
10118 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpULEqNeLeGt_reg_imm0_branch" %}
10119
10120 ins_encode %{
10121 __ enc_cmpUEqNeLeGt_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
10122 %}
10123
10124 ins_pipe(pipe_cmpz_branch);
10125 %}
10126
10127 // compare lt/ge unsigned instructs has no short instruct with same match
10128 instruct far_cmpULLtGe_reg_imm0_branch(cmpOpULtGe cmp, iRegL op1, immL0 zero, label lbl)
10129 %{
10130 match(If cmp (CmpUL op1 zero));
10131
10132 effect(USE op1, USE lbl);
10133
10134 ins_cost(BRANCH_COST);
10135
10136 format %{ "j $lbl if $cmp == ge\t#@far_cmpULLtGe_reg_imm0_branch" %}
10137
10138 ins_encode(riscv_enc_far_cmpULtGe_imm0_branch(cmp, op1, lbl));
10139
10140 ins_pipe(pipe_cmpz_branch);
10141 %}
10142
10143 instruct far_cmpP_imm0_branch(cmpOpEqNe cmp, iRegP op1, immP0 zero, label lbl) %{
10144 match(If cmp (CmpP op1 zero));
10145 effect(USE lbl);
10146
10147 ins_cost(BRANCH_COST * 2);
10148 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpP_imm0_branch" %}
10149
10150 ins_encode %{
10151 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
10152 %}
10153
10154 ins_pipe(pipe_cmpz_branch);
10155 %}
10156
10157 instruct far_cmpN_imm0_branch(cmpOpEqNe cmp, iRegN op1, immN0 zero, label lbl) %{
10158 match(If cmp (CmpN op1 zero));
10159 effect(USE lbl);
10160
10161 ins_cost(BRANCH_COST * 2);
10162
10163 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpN_imm0_branch" %}
10164
10165 ins_encode %{
10166 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
10167 %}
10168
10169 ins_pipe(pipe_cmpz_branch);
10170 %}
10171
10172 instruct far_cmpP_narrowOop_imm0_branch(cmpOpEqNe cmp, iRegN op1, immP0 zero, label lbl) %{
10173 match(If cmp (CmpP (DecodeN op1) zero));
10174 effect(USE lbl);
10175
10176 ins_cost(BRANCH_COST * 2);
10177 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpP_narrowOop_imm0_branch" %}
10178
10179 ins_encode %{
10180 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
10181 %}
10182
10183 ins_pipe(pipe_cmpz_branch);
10184 %}
10185
10186 // ============================================================================
10187 // Conditional Move Instructions
10188
10189 // --------- CMoveI ---------
10190
10191 instruct cmovI_cmpI(iRegINoSp dst, iRegI src, iRegI op1, iRegI op2, cmpOp cop) %{
10192 match(Set dst (CMoveI (Binary cop (CmpI op1 op2)) (Binary dst src)));
10193 ins_cost(ALU_COST + BRANCH_COST);
10194
10195 format %{
10196 "CMoveI $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpI\n\t"
10197 %}
10198
10199 ins_encode %{
10200 __ enc_cmove($cop$$cmpcode,
10201 as_Register($op1$$reg), as_Register($op2$$reg),
10202 as_Register($dst$$reg), as_Register($src$$reg));
10203 %}
10204
10205 ins_pipe(pipe_class_compare);
10206 %}
10207
10208 instruct cmovI_cmpU(iRegINoSp dst, iRegI src, iRegI op1, iRegI op2, cmpOpU cop) %{
10209 match(Set dst (CMoveI (Binary cop (CmpU op1 op2)) (Binary dst src)));
10210 ins_cost(ALU_COST + BRANCH_COST);
10211
10212 format %{
10213 "CMoveI $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpU\n\t"
10214 %}
10215
10216 ins_encode %{
10217 __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10218 as_Register($op1$$reg), as_Register($op2$$reg),
10219 as_Register($dst$$reg), as_Register($src$$reg));
10220 %}
10221
10222 ins_pipe(pipe_class_compare);
10223 %}
10224
10225 instruct cmovI_cmpL(iRegINoSp dst, iRegI src, iRegL op1, iRegL op2, cmpOp cop) %{
10226 match(Set dst (CMoveI (Binary cop (CmpL op1 op2)) (Binary dst src)));
10227 ins_cost(ALU_COST + BRANCH_COST);
10228
10229 format %{
10230 "CMoveI $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpL\n\t"
10231 %}
10232
10233 ins_encode %{
10234 __ enc_cmove($cop$$cmpcode,
10235 as_Register($op1$$reg), as_Register($op2$$reg),
10236 as_Register($dst$$reg), as_Register($src$$reg));
10237 %}
10238
10239 ins_pipe(pipe_class_compare);
10240 %}
10241
10242 instruct cmovI_cmpUL(iRegINoSp dst, iRegI src, iRegL op1, iRegL op2, cmpOpU cop) %{
10243 match(Set dst (CMoveI (Binary cop (CmpUL op1 op2)) (Binary dst src)));
10244 ins_cost(ALU_COST + BRANCH_COST);
10245
10246 format %{
10247 "CMoveI $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpUL\n\t"
10248 %}
10249
10250 ins_encode %{
10251 __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10252 as_Register($op1$$reg), as_Register($op2$$reg),
10253 as_Register($dst$$reg), as_Register($src$$reg));
10254 %}
10255
10256 ins_pipe(pipe_class_compare);
10257 %}
10258
10259 instruct cmovI_cmpF(iRegINoSp dst, iRegI src, fRegF op1, fRegF op2, cmpOp cop) %{
10260 match(Set dst (CMoveI (Binary cop (CmpF op1 op2)) (Binary dst src)));
10261 ins_cost(ALU_COST + BRANCH_COST);
10262
10263 format %{
10264 "CMoveI $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpF\n\t"
10265 %}
10266
10267 ins_encode %{
10268 __ enc_cmove_cmp_fp($cop$$cmpcode,
10269 as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg),
10270 as_Register($dst$$reg), as_Register($src$$reg), true /* is_single */);
10271 %}
10272
10273 ins_pipe(pipe_class_compare);
10274 %}
10275
10276 instruct cmovI_cmpD(iRegINoSp dst, iRegI src, fRegD op1, fRegD op2, cmpOp cop) %{
10277 match(Set dst (CMoveI (Binary cop (CmpD op1 op2)) (Binary dst src)));
10278 ins_cost(ALU_COST + BRANCH_COST);
10279
10280 format %{
10281 "CMoveI $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpD\n\t"
10282 %}
10283
10284 ins_encode %{
10285 __ enc_cmove_cmp_fp($cop$$cmpcode | C2_MacroAssembler::double_branch_mask,
10286 as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg),
10287 as_Register($dst$$reg), as_Register($src$$reg), false /* is_single */);
10288 %}
10289
10290 ins_pipe(pipe_class_compare);
10291 %}
10292
10293 instruct cmovI_cmpN(iRegINoSp dst, iRegI src, iRegN op1, iRegN op2, cmpOpU cop) %{
10294 match(Set dst (CMoveI (Binary cop (CmpN op1 op2)) (Binary dst src)));
10295 ins_cost(ALU_COST + BRANCH_COST);
10296
10297 format %{
10298 "CMoveI $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpN\n\t"
10299 %}
10300
10301 ins_encode %{
10302 __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10303 as_Register($op1$$reg), as_Register($op2$$reg),
10304 as_Register($dst$$reg), as_Register($src$$reg));
10305 %}
10306
10307 ins_pipe(pipe_class_compare);
10308 %}
10309
10310 instruct cmovI_cmpP(iRegINoSp dst, iRegI src, iRegP op1, iRegP op2, cmpOpU cop) %{
10311 match(Set dst (CMoveI (Binary cop (CmpP op1 op2)) (Binary dst src)));
10312 ins_cost(ALU_COST + BRANCH_COST);
10313
10314 format %{
10315 "CMoveI $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpP\n\t"
10316 %}
10317
10318 ins_encode %{
10319 __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10320 as_Register($op1$$reg), as_Register($op2$$reg),
10321 as_Register($dst$$reg), as_Register($src$$reg));
10322 %}
10323
10324 ins_pipe(pipe_class_compare);
10325 %}
10326
10327 // --------- CMoveL ---------
10328
10329 instruct cmovL_cmpL(iRegLNoSp dst, iRegL src, iRegL op1, iRegL op2, cmpOp cop) %{
10330 match(Set dst (CMoveL (Binary cop (CmpL op1 op2)) (Binary dst src)));
10331 ins_cost(ALU_COST + BRANCH_COST);
10332
10333 format %{
10334 "CMoveL $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpL\n\t"
10335 %}
10336
10337 ins_encode %{
10338 __ enc_cmove($cop$$cmpcode,
10339 as_Register($op1$$reg), as_Register($op2$$reg),
10340 as_Register($dst$$reg), as_Register($src$$reg));
10341 %}
10342
10343 ins_pipe(pipe_class_compare);
10344 %}
10345
10346 instruct cmovL_cmpUL(iRegLNoSp dst, iRegL src, iRegL op1, iRegL op2, cmpOpU cop) %{
10347 match(Set dst (CMoveL (Binary cop (CmpUL op1 op2)) (Binary dst src)));
10348 ins_cost(ALU_COST + BRANCH_COST);
10349
10350 format %{
10351 "CMoveL $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpUL\n\t"
10352 %}
10353
10354 ins_encode %{
10355 __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10356 as_Register($op1$$reg), as_Register($op2$$reg),
10357 as_Register($dst$$reg), as_Register($src$$reg));
10358 %}
10359
10360 ins_pipe(pipe_class_compare);
10361 %}
10362
10363 instruct cmovL_cmpI(iRegLNoSp dst, iRegL src, iRegI op1, iRegI op2, cmpOp cop) %{
10364 match(Set dst (CMoveL (Binary cop (CmpI op1 op2)) (Binary dst src)));
10365 ins_cost(ALU_COST + BRANCH_COST);
10366
10367 format %{
10368 "CMoveL $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpI\n\t"
10369 %}
10370
10371 ins_encode %{
10372 __ enc_cmove($cop$$cmpcode,
10373 as_Register($op1$$reg), as_Register($op2$$reg),
10374 as_Register($dst$$reg), as_Register($src$$reg));
10375 %}
10376
10377 ins_pipe(pipe_class_compare);
10378 %}
10379
10380 instruct cmovL_cmpU(iRegLNoSp dst, iRegL src, iRegI op1, iRegI op2, cmpOpU cop) %{
10381 match(Set dst (CMoveL (Binary cop (CmpU op1 op2)) (Binary dst src)));
10382 ins_cost(ALU_COST + BRANCH_COST);
10383
10384 format %{
10385 "CMoveL $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpU\n\t"
10386 %}
10387
10388 ins_encode %{
10389 __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10390 as_Register($op1$$reg), as_Register($op2$$reg),
10391 as_Register($dst$$reg), as_Register($src$$reg));
10392 %}
10393
10394 ins_pipe(pipe_class_compare);
10395 %}
10396
10397 instruct cmovL_cmpF(iRegLNoSp dst, iRegL src, fRegF op1, fRegF op2, cmpOp cop) %{
10398 match(Set dst (CMoveL (Binary cop (CmpF op1 op2)) (Binary dst src)));
10399 ins_cost(ALU_COST + BRANCH_COST);
10400
10401 format %{
10402 "CMoveL $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpF\n\t"
10403 %}
10404
10405 ins_encode %{
10406 __ enc_cmove_cmp_fp($cop$$cmpcode,
10407 as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg),
10408 as_Register($dst$$reg), as_Register($src$$reg), true /* is_single */);
10409 %}
10410
10411 ins_pipe(pipe_class_compare);
10412 %}
10413
10414 instruct cmovL_cmpD(iRegLNoSp dst, iRegL src, fRegD op1, fRegD op2, cmpOp cop) %{
10415 match(Set dst (CMoveL (Binary cop (CmpD op1 op2)) (Binary dst src)));
10416 ins_cost(ALU_COST + BRANCH_COST);
10417
10418 format %{
10419 "CMoveL $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpD\n\t"
10420 %}
10421
10422 ins_encode %{
10423 __ enc_cmove_cmp_fp($cop$$cmpcode | C2_MacroAssembler::double_branch_mask,
10424 as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg),
10425 as_Register($dst$$reg), as_Register($src$$reg), false /* is_single */);
10426 %}
10427
10428 ins_pipe(pipe_class_compare);
10429 %}
10430
10431 instruct cmovL_cmpN(iRegLNoSp dst, iRegL src, iRegN op1, iRegN op2, cmpOpU cop) %{
10432 match(Set dst (CMoveL (Binary cop (CmpN op1 op2)) (Binary dst src)));
10433 ins_cost(ALU_COST + BRANCH_COST);
10434
10435 format %{
10436 "CMoveL $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpN\n\t"
10437 %}
10438
10439 ins_encode %{
10440 __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10441 as_Register($op1$$reg), as_Register($op2$$reg),
10442 as_Register($dst$$reg), as_Register($src$$reg));
10443 %}
10444
10445 ins_pipe(pipe_class_compare);
10446 %}
10447
10448 instruct cmovL_cmpP(iRegLNoSp dst, iRegL src, iRegP op1, iRegP op2, cmpOpU cop) %{
10449 match(Set dst (CMoveL (Binary cop (CmpP op1 op2)) (Binary dst src)));
10450 ins_cost(ALU_COST + BRANCH_COST);
10451
10452 format %{
10453 "CMoveL $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpP\n\t"
10454 %}
10455
10456 ins_encode %{
10457 __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10458 as_Register($op1$$reg), as_Register($op2$$reg),
10459 as_Register($dst$$reg), as_Register($src$$reg));
10460 %}
10461
10462 ins_pipe(pipe_class_compare);
10463 %}
10464
10465 // ============================================================================
10466 // Procedure Call/Return Instructions
10467
10468 // Call Java Static Instruction
10469 // Note: If this code changes, the corresponding ret_addr_offset() and
10470 // compute_padding() functions will have to be adjusted.
10471 instruct CallStaticJavaDirect(method meth)
10472 %{
10473 match(CallStaticJava);
10474
10475 effect(USE meth);
10476
10477 ins_cost(BRANCH_COST);
10478
10479 format %{ "CALL,static $meth\t#@CallStaticJavaDirect" %}
10480
10481 ins_encode(riscv_enc_java_static_call(meth),
10482 riscv_enc_call_epilog);
10483
10484 ins_pipe(pipe_class_call);
10485 ins_alignment(4);
10486 %}
10487
10488 // TO HERE
10489
10490 // Call Java Dynamic Instruction
10491 // Note: If this code changes, the corresponding ret_addr_offset() and
10492 // compute_padding() functions will have to be adjusted.
10493 instruct CallDynamicJavaDirect(method meth)
10494 %{
10495 match(CallDynamicJava);
10496
10497 effect(USE meth);
10498
10499 ins_cost(BRANCH_COST + ALU_COST * 5);
10500
10501 format %{ "CALL,dynamic $meth\t#@CallDynamicJavaDirect" %}
10502
10503 ins_encode(riscv_enc_java_dynamic_call(meth),
10504 riscv_enc_call_epilog);
10505
10506 ins_pipe(pipe_class_call);
10507 ins_alignment(4);
10508 %}
10509
10510 // Call Runtime Instruction
10511
10512 instruct CallRuntimeDirect(method meth)
10513 %{
10514 match(CallRuntime);
10515
10516 effect(USE meth);
10517
10518 ins_cost(BRANCH_COST);
10519
10520 format %{ "CALL, runtime $meth\t#@CallRuntimeDirect" %}
10521
10522 ins_encode(riscv_enc_java_to_runtime(meth));
10523
10524 ins_pipe(pipe_class_call);
10525 ins_alignment(4);
10526 %}
10527
10528 // Call Runtime Instruction
10529
10530 instruct CallLeafDirect(method meth)
10531 %{
10532 match(CallLeaf);
10533
10534 effect(USE meth);
10535
10536 ins_cost(BRANCH_COST);
10537
10538 format %{ "CALL, runtime leaf $meth\t#@CallLeafDirect" %}
10539
10540 ins_encode(riscv_enc_java_to_runtime(meth));
10541
10542 ins_pipe(pipe_class_call);
10543 ins_alignment(4);
10544 %}
10545
10546 // Call Runtime Instruction without safepoint and with vector arguments
10547
10548 instruct CallLeafDirectVector(method meth)
10549 %{
10550 match(CallLeafVector);
10551
10552 effect(USE meth);
10553
10554 ins_cost(BRANCH_COST);
10555
10556 format %{ "CALL, runtime leaf vector $meth" %}
10557
10558 ins_encode(riscv_enc_java_to_runtime(meth));
10559
10560 ins_pipe(pipe_class_call);
10561 ins_alignment(4);
10562 %}
10563
10564 // Call Runtime Instruction
10565
10566 instruct CallLeafNoFPDirect(method meth)
10567 %{
10568 match(CallLeafNoFP);
10569
10570 effect(USE meth);
10571
10572 ins_cost(BRANCH_COST);
10573
10574 format %{ "CALL, runtime leaf nofp $meth\t#@CallLeafNoFPDirect" %}
10575
10576 ins_encode(riscv_enc_java_to_runtime(meth));
10577
10578 ins_pipe(pipe_class_call);
10579 ins_alignment(4);
10580 %}
10581
10582 // ============================================================================
10583 // Partial Subtype Check
10584 //
10585 // superklass array for an instance of the superklass. Set a hidden
10586 // internal cache on a hit (cache is checked with exposed code in
10587 // gen_subtype_check()). Return zero for a hit. The encoding
10588 // ALSO sets flags.
10589
10590 instruct partialSubtypeCheck(iRegP_R15 result, iRegP_R14 sub, iRegP_R10 super, iRegP_R12 tmp, rFlagsReg cr)
10591 %{
10592 predicate(!UseSecondarySupersTable);
10593 match(Set result (PartialSubtypeCheck sub super));
10594 effect(KILL tmp, KILL cr);
10595
10596 ins_cost(20 * DEFAULT_COST);
10597 format %{ "partialSubtypeCheck $result, $sub, $super\t#@partialSubtypeCheck" %}
10598
10599 ins_encode(riscv_enc_partial_subtype_check(sub, super, tmp, result));
10600
10601 opcode(0x1); // Force zero of result reg on hit
10602
10603 ins_pipe(pipe_class_memory);
10604 %}
10605
10606 // Two versions of partialSubtypeCheck, both used when we need to
10607 // search for a super class in the secondary supers array. The first
10608 // is used when we don't know _a priori_ the class being searched
10609 // for. The second, far more common, is used when we do know: this is
10610 // used for instanceof, checkcast, and any case where C2 can determine
10611 // it by constant propagation.
10612
10613 instruct partialSubtypeCheckVarSuper(iRegP_R14 sub, iRegP_R10 super, iRegP_R15 result,
10614 iRegP_R11 tmpR11, iRegP_R12 tmpR12, iRegP_R13 tmpR13,
10615 iRegP_R16 tmpR16, rFlagsReg cr)
10616 %{
10617 predicate(UseSecondarySupersTable);
10618 match(Set result (PartialSubtypeCheck sub super));
10619 effect(TEMP tmpR11, TEMP tmpR12, TEMP tmpR13, TEMP tmpR16, KILL cr);
10620
10621 ins_cost(10 * DEFAULT_COST); // slightly larger than the next version
10622 format %{ "partialSubtypeCheck $result, $sub, $super" %}
10623
10624 ins_encode %{
10625 __ lookup_secondary_supers_table_var($sub$$Register, $super$$Register, $result$$Register,
10626 $tmpR11$$Register, $tmpR12$$Register, $tmpR13$$Register,
10627 $tmpR16$$Register, nullptr /*L_success*/);
10628 %}
10629
10630 ins_pipe(pipe_class_memory);
10631 %}
10632
10633 instruct partialSubtypeCheckConstSuper(iRegP_R14 sub, iRegP_R10 super_reg, immP super_con, iRegP_R15 result,
10634 iRegP_R11 tmpR11, iRegP_R12 tmpR12, iRegP_R13 tmpR13, iRegP_R16 tmpR16, rFlagsReg cr)
10635 %{
10636 predicate(UseSecondarySupersTable);
10637 match(Set result (PartialSubtypeCheck sub (Binary super_reg super_con)));
10638 effect(TEMP tmpR11, TEMP tmpR12, TEMP tmpR13, TEMP tmpR16, KILL cr);
10639
10640 ins_cost(5 * DEFAULT_COST); // needs to be less than competing nodes
10641 format %{ "partialSubtypeCheck $result, $sub, $super_reg, $super_con" %}
10642
10643 ins_encode %{
10644 bool success = false;
10645 u1 super_klass_slot = ((Klass*)$super_con$$constant)->hash_slot();
10646 if (InlineSecondarySupersTest) {
10647 success = __ lookup_secondary_supers_table_const($sub$$Register, $super_reg$$Register, $result$$Register,
10648 $tmpR11$$Register, $tmpR12$$Register, $tmpR13$$Register,
10649 $tmpR16$$Register, super_klass_slot);
10650 } else {
10651 address call = __ reloc_call(RuntimeAddress(StubRoutines::lookup_secondary_supers_table_stub(super_klass_slot)));
10652 success = (call != nullptr);
10653 }
10654 if (!success) {
10655 ciEnv::current()->record_failure("CodeCache is full");
10656 return;
10657 }
10658 %}
10659
10660 ins_pipe(pipe_class_memory);
10661 %}
10662
10663 instruct string_compareU(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
10664 iRegI_R10 result, iRegP_R28 tmp1, iRegL_R29 tmp2, iRegL_R30 tmp3, rFlagsReg cr)
10665 %{
10666 predicate(!UseRVV && ((StrCompNode *)n)->encoding() == StrIntrinsicNode::UU);
10667 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10668 effect(KILL tmp1, KILL tmp2, KILL tmp3, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
10669
10670 format %{ "String Compare $str1, $cnt1, $str2, $cnt2 -> $result\t#@string_compareU" %}
10671 ins_encode %{
10672 // Count is in 8-bit bytes; non-Compact chars are 16 bits.
10673 __ string_compare($str1$$Register, $str2$$Register,
10674 $cnt1$$Register, $cnt2$$Register, $result$$Register,
10675 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
10676 StrIntrinsicNode::UU);
10677 %}
10678 ins_pipe(pipe_class_memory);
10679 %}
10680
10681 instruct string_compareL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
10682 iRegI_R10 result, iRegP_R28 tmp1, iRegL_R29 tmp2, iRegL_R30 tmp3, rFlagsReg cr)
10683 %{
10684 predicate(!UseRVV && ((StrCompNode *)n)->encoding() == StrIntrinsicNode::LL);
10685 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10686 effect(KILL tmp1, KILL tmp2, KILL tmp3, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
10687
10688 format %{ "String Compare $str1, $cnt1, $str2, $cnt2 -> $result\t#@string_compareL" %}
10689 ins_encode %{
10690 __ string_compare($str1$$Register, $str2$$Register,
10691 $cnt1$$Register, $cnt2$$Register, $result$$Register,
10692 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
10693 StrIntrinsicNode::LL);
10694 %}
10695 ins_pipe(pipe_class_memory);
10696 %}
10697
10698 instruct string_compareUL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
10699 iRegI_R10 result, iRegP_R28 tmp1, iRegL_R29 tmp2, iRegL_R30 tmp3, rFlagsReg cr)
10700 %{
10701 predicate(!UseRVV && ((StrCompNode *)n)->encoding() == StrIntrinsicNode::UL);
10702 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10703 effect(KILL tmp1, KILL tmp2, KILL tmp3, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
10704
10705 format %{"String Compare $str1, $cnt1, $str2, $cnt2 -> $result\t#@string_compareUL" %}
10706 ins_encode %{
10707 __ string_compare($str1$$Register, $str2$$Register,
10708 $cnt1$$Register, $cnt2$$Register, $result$$Register,
10709 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
10710 StrIntrinsicNode::UL);
10711 %}
10712 ins_pipe(pipe_class_memory);
10713 %}
10714
10715 instruct string_compareLU(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
10716 iRegI_R10 result, iRegP_R28 tmp1, iRegL_R29 tmp2, iRegL_R30 tmp3,
10717 rFlagsReg cr)
10718 %{
10719 predicate(!UseRVV && ((StrCompNode *)n)->encoding() == StrIntrinsicNode::LU);
10720 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10721 effect(KILL tmp1, KILL tmp2, KILL tmp3, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
10722
10723 format %{ "String Compare $str1, $cnt1, $str2, $cnt2 -> $result\t#@string_compareLU" %}
10724 ins_encode %{
10725 __ string_compare($str1$$Register, $str2$$Register,
10726 $cnt1$$Register, $cnt2$$Register, $result$$Register,
10727 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
10728 StrIntrinsicNode::LU);
10729 %}
10730 ins_pipe(pipe_class_memory);
10731 %}
10732
10733 instruct string_indexofUU(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
10734 iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3,
10735 iRegINoSp tmp4, iRegINoSp tmp5, iRegINoSp tmp6, rFlagsReg cr)
10736 %{
10737 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU);
10738 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
10739 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, TEMP_DEF result,
10740 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, TEMP tmp6, KILL cr);
10741
10742 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result (UU)" %}
10743 ins_encode %{
10744 __ string_indexof($str1$$Register, $str2$$Register,
10745 $cnt1$$Register, $cnt2$$Register,
10746 $tmp1$$Register, $tmp2$$Register,
10747 $tmp3$$Register, $tmp4$$Register,
10748 $tmp5$$Register, $tmp6$$Register,
10749 $result$$Register, StrIntrinsicNode::UU);
10750 %}
10751 ins_pipe(pipe_class_memory);
10752 %}
10753
10754 instruct string_indexofLL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
10755 iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3,
10756 iRegINoSp tmp4, iRegINoSp tmp5, iRegINoSp tmp6, rFlagsReg cr)
10757 %{
10758 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL);
10759 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
10760 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, TEMP_DEF result,
10761 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, TEMP tmp6, KILL cr);
10762
10763 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result (LL)" %}
10764 ins_encode %{
10765 __ string_indexof($str1$$Register, $str2$$Register,
10766 $cnt1$$Register, $cnt2$$Register,
10767 $tmp1$$Register, $tmp2$$Register,
10768 $tmp3$$Register, $tmp4$$Register,
10769 $tmp5$$Register, $tmp6$$Register,
10770 $result$$Register, StrIntrinsicNode::LL);
10771 %}
10772 ins_pipe(pipe_class_memory);
10773 %}
10774
10775 instruct string_indexofUL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
10776 iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3,
10777 iRegINoSp tmp4, iRegINoSp tmp5, iRegINoSp tmp6, rFlagsReg cr)
10778 %{
10779 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL);
10780 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
10781 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, TEMP_DEF result,
10782 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, TEMP tmp6, KILL cr);
10783 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result (UL)" %}
10784
10785 ins_encode %{
10786 __ string_indexof($str1$$Register, $str2$$Register,
10787 $cnt1$$Register, $cnt2$$Register,
10788 $tmp1$$Register, $tmp2$$Register,
10789 $tmp3$$Register, $tmp4$$Register,
10790 $tmp5$$Register, $tmp6$$Register,
10791 $result$$Register, StrIntrinsicNode::UL);
10792 %}
10793 ins_pipe(pipe_class_memory);
10794 %}
10795
10796 instruct string_indexof_conUU(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2,
10797 immI_le_4 int_cnt2, iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2,
10798 iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
10799 %{
10800 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU);
10801 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
10802 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, TEMP_DEF result,
10803 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
10804
10805 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result (UU)" %}
10806
10807 ins_encode %{
10808 int icnt2 = (int)$int_cnt2$$constant;
10809 __ string_indexof_linearscan($str1$$Register, $str2$$Register,
10810 $cnt1$$Register, zr,
10811 $tmp1$$Register, $tmp2$$Register,
10812 $tmp3$$Register, $tmp4$$Register,
10813 icnt2, $result$$Register, StrIntrinsicNode::UU);
10814 %}
10815 ins_pipe(pipe_class_memory);
10816 %}
10817
10818 instruct string_indexof_conLL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2,
10819 immI_le_4 int_cnt2, iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2,
10820 iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
10821 %{
10822 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL);
10823 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
10824 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, TEMP_DEF result,
10825 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
10826
10827 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result (LL)" %}
10828 ins_encode %{
10829 int icnt2 = (int)$int_cnt2$$constant;
10830 __ string_indexof_linearscan($str1$$Register, $str2$$Register,
10831 $cnt1$$Register, zr,
10832 $tmp1$$Register, $tmp2$$Register,
10833 $tmp3$$Register, $tmp4$$Register,
10834 icnt2, $result$$Register, StrIntrinsicNode::LL);
10835 %}
10836 ins_pipe(pipe_class_memory);
10837 %}
10838
10839 instruct string_indexof_conUL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2,
10840 immI_1 int_cnt2, iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2,
10841 iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
10842 %{
10843 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL);
10844 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
10845 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, TEMP_DEF result,
10846 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
10847
10848 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result (UL)" %}
10849 ins_encode %{
10850 int icnt2 = (int)$int_cnt2$$constant;
10851 __ string_indexof_linearscan($str1$$Register, $str2$$Register,
10852 $cnt1$$Register, zr,
10853 $tmp1$$Register, $tmp2$$Register,
10854 $tmp3$$Register, $tmp4$$Register,
10855 icnt2, $result$$Register, StrIntrinsicNode::UL);
10856 %}
10857 ins_pipe(pipe_class_memory);
10858 %}
10859
10860 instruct stringU_indexof_char(iRegP_R11 str1, iRegI_R12 cnt1, iRegI_R13 ch,
10861 iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2,
10862 iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
10863 %{
10864 match(Set result (StrIndexOfChar (Binary str1 cnt1) ch));
10865 predicate(!UseRVV && (((StrIndexOfCharNode*)n)->encoding() == StrIntrinsicNode::U));
10866 effect(USE_KILL str1, USE_KILL cnt1, USE_KILL ch, TEMP_DEF result,
10867 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
10868
10869 format %{ "StringUTF16 IndexOf char[] $str1, $cnt1, $ch -> $result" %}
10870 ins_encode %{
10871 __ string_indexof_char($str1$$Register, $cnt1$$Register, $ch$$Register,
10872 $result$$Register, $tmp1$$Register, $tmp2$$Register,
10873 $tmp3$$Register, $tmp4$$Register, false /* isU */);
10874 %}
10875 ins_pipe(pipe_class_memory);
10876 %}
10877
10878
10879 instruct stringL_indexof_char(iRegP_R11 str1, iRegI_R12 cnt1, iRegI_R13 ch,
10880 iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2,
10881 iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
10882 %{
10883 match(Set result (StrIndexOfChar (Binary str1 cnt1) ch));
10884 predicate(!UseRVV && (((StrIndexOfCharNode*)n)->encoding() == StrIntrinsicNode::L));
10885 effect(USE_KILL str1, USE_KILL cnt1, USE_KILL ch, TEMP_DEF result,
10886 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
10887
10888 format %{ "StringLatin1 IndexOf char[] $str1, $cnt1, $ch -> $result" %}
10889 ins_encode %{
10890 __ string_indexof_char($str1$$Register, $cnt1$$Register, $ch$$Register,
10891 $result$$Register, $tmp1$$Register, $tmp2$$Register,
10892 $tmp3$$Register, $tmp4$$Register, true /* isL */);
10893 %}
10894 ins_pipe(pipe_class_memory);
10895 %}
10896
10897 // clearing of an array
10898 instruct clearArray_reg_reg(iRegL_R29 cnt, iRegP_R28 base, iRegP_R30 tmp1,
10899 iRegP_R31 tmp2, rFlagsReg cr, Universe dummy)
10900 %{
10901 // temp registers must match the one used in StubGenerator::generate_zero_blocks()
10902 predicate(UseBlockZeroing || !UseRVV);
10903 match(Set dummy (ClearArray cnt base));
10904 effect(USE_KILL cnt, USE_KILL base, TEMP tmp1, TEMP tmp2, KILL cr);
10905
10906 ins_cost(4 * DEFAULT_COST);
10907 format %{ "ClearArray $cnt, $base\t#@clearArray_reg_reg" %}
10908
10909 ins_encode %{
10910 address tpc = __ zero_words($base$$Register, $cnt$$Register);
10911 if (tpc == nullptr) {
10912 ciEnv::current()->record_failure("CodeCache is full");
10913 return;
10914 }
10915 %}
10916
10917 ins_pipe(pipe_class_memory);
10918 %}
10919
10920 instruct clearArray_imm_reg(immL cnt, iRegP_R28 base, Universe dummy, rFlagsReg cr)
10921 %{
10922 predicate(!UseRVV && (uint64_t)n->in(2)->get_long()
10923 < (uint64_t)(BlockZeroingLowLimit >> LogBytesPerWord));
10924 match(Set dummy (ClearArray cnt base));
10925 effect(USE_KILL base, KILL cr);
10926
10927 ins_cost(4 * DEFAULT_COST);
10928 format %{ "ClearArray $cnt, $base\t#@clearArray_imm_reg" %}
10929
10930 ins_encode %{
10931 __ zero_words($base$$Register, (uint64_t)$cnt$$constant);
10932 %}
10933
10934 ins_pipe(pipe_class_memory);
10935 %}
10936
10937 instruct string_equalsL(iRegP_R11 str1, iRegP_R13 str2, iRegI_R14 cnt,
10938 iRegI_R10 result, rFlagsReg cr)
10939 %{
10940 predicate(!UseRVV && ((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::LL);
10941 match(Set result (StrEquals (Binary str1 str2) cnt));
10942 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL cr);
10943
10944 format %{ "String Equals $str1, $str2, $cnt -> $result\t#@string_equalsL" %}
10945 ins_encode %{
10946 // Count is in 8-bit bytes; non-Compact chars are 16 bits.
10947 __ string_equals($str1$$Register, $str2$$Register,
10948 $result$$Register, $cnt$$Register);
10949 %}
10950 ins_pipe(pipe_class_memory);
10951 %}
10952
10953 instruct array_equalsB(iRegP_R11 ary1, iRegP_R12 ary2, iRegI_R10 result,
10954 iRegP_R13 tmp1, iRegP_R14 tmp2, iRegP_R15 tmp3)
10955 %{
10956 predicate(!UseRVV && ((AryEqNode*)n)->encoding() == StrIntrinsicNode::LL);
10957 match(Set result (AryEq ary1 ary2));
10958 effect(USE_KILL ary1, USE_KILL ary2, TEMP tmp1, TEMP tmp2, TEMP tmp3);
10959
10960 format %{ "Array Equals $ary1, $ary2 -> $result\t#@array_equalsB // KILL all" %}
10961 ins_encode %{
10962 __ arrays_equals($ary1$$Register, $ary2$$Register,
10963 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
10964 $result$$Register, 1);
10965 %}
10966 ins_pipe(pipe_class_memory);
10967 %}
10968
10969 instruct array_equalsC(iRegP_R11 ary1, iRegP_R12 ary2, iRegI_R10 result,
10970 iRegP_R13 tmp1, iRegP_R14 tmp2, iRegP_R15 tmp3)
10971 %{
10972 predicate(!UseRVV && ((AryEqNode*)n)->encoding() == StrIntrinsicNode::UU);
10973 match(Set result (AryEq ary1 ary2));
10974 effect(USE_KILL ary1, USE_KILL ary2, TEMP tmp1, TEMP tmp2, TEMP tmp3);
10975
10976 format %{ "Array Equals $ary1, $ary2 -> $result\t#@array_equalsC // KILL all" %}
10977 ins_encode %{
10978 __ arrays_equals($ary1$$Register, $ary2$$Register,
10979 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
10980 $result$$Register, 2);
10981 %}
10982 ins_pipe(pipe_class_memory);
10983 %}
10984
10985 // fast ArraysSupport.vectorizedHashCode
10986 instruct arrays_hashcode(iRegP_R11 ary, iRegI_R12 cnt, iRegI_R10 result, immI basic_type,
10987 iRegLNoSp tmp1, iRegLNoSp tmp2,
10988 iRegLNoSp tmp3, iRegLNoSp tmp4,
10989 iRegLNoSp tmp5, iRegLNoSp tmp6, rFlagsReg cr)
10990 %{
10991 predicate(!UseRVV);
10992 match(Set result (VectorizedHashCode (Binary ary cnt) (Binary result basic_type)));
10993 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, TEMP tmp6,
10994 USE_KILL ary, USE_KILL cnt, USE basic_type, KILL cr);
10995
10996 format %{ "Array HashCode array[] $ary,$cnt,$result,$basic_type -> $result // KILL all" %}
10997 ins_encode %{
10998 __ arrays_hashcode($ary$$Register, $cnt$$Register, $result$$Register,
10999 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
11000 $tmp4$$Register, $tmp5$$Register, $tmp6$$Register,
11001 (BasicType)$basic_type$$constant);
11002 %}
11003 ins_pipe(pipe_class_memory);
11004 %}
11005
11006 // ============================================================================
11007 // Safepoint Instructions
11008
11009 instruct safePoint(iRegP poll)
11010 %{
11011 match(SafePoint poll);
11012
11013 ins_cost(2 * LOAD_COST);
11014 format %{
11015 "lwu zr, [$poll]\t# Safepoint: poll for GC, #@safePoint"
11016 %}
11017 ins_encode %{
11018 __ read_polling_page(as_Register($poll$$reg), 0, relocInfo::poll_type);
11019 %}
11020 ins_pipe(pipe_serial); // ins_pipe(iload_reg_mem);
11021 %}
11022
11023 // ============================================================================
11024 // This name is KNOWN by the ADLC and cannot be changed.
11025 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
11026 // for this guy.
11027 instruct tlsLoadP(javaThread_RegP dst)
11028 %{
11029 match(Set dst (ThreadLocal));
11030
11031 ins_cost(0);
11032
11033 format %{ " -- \t// $dst=Thread::current(), empty, #@tlsLoadP" %}
11034
11035 size(0);
11036
11037 ins_encode( /*empty*/ );
11038
11039 ins_pipe(pipe_class_empty);
11040 %}
11041
11042 // inlined locking and unlocking
11043 // using t1 as the 'flag' register to bridge the BoolNode producers and consumers
11044 instruct cmpFastLock(rFlagsReg cr, iRegP object, iRegP box,
11045 iRegPNoSp tmp1, iRegPNoSp tmp2, iRegPNoSp tmp3, iRegPNoSp tmp4)
11046 %{
11047 match(Set cr (FastLock object box));
11048 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4);
11049
11050 ins_cost(10 * DEFAULT_COST);
11051 format %{ "fastlock $object,$box\t! kills $tmp1,$tmp2,$tmp3,$tmp4 #@cmpFastLock" %}
11052
11053 ins_encode %{
11054 __ fast_lock($object$$Register, $box$$Register,
11055 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register);
11056 %}
11057
11058 ins_pipe(pipe_serial);
11059 %}
11060
11061 // using t1 as the 'flag' register to bridge the BoolNode producers and consumers
11062 instruct cmpFastUnlock(rFlagsReg cr, iRegP object, iRegP box,
11063 iRegPNoSp tmp1, iRegPNoSp tmp2, iRegPNoSp tmp3)
11064 %{
11065 match(Set cr (FastUnlock object box));
11066 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3);
11067
11068 ins_cost(10 * DEFAULT_COST);
11069 format %{ "fastunlock $object,$box\t! kills $tmp1,$tmp2,$tmp3 #@cmpFastUnlock" %}
11070
11071 ins_encode %{
11072 __ fast_unlock($object$$Register, $box$$Register,
11073 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
11074 %}
11075
11076 ins_pipe(pipe_serial);
11077 %}
11078
11079 // Tail Call; Jump from runtime stub to Java code.
11080 // Also known as an 'interprocedural jump'.
11081 // Target of jump will eventually return to caller.
11082 // TailJump below removes the return address.
11083 // Don't use fp for 'jump_target' because a MachEpilogNode has already been
11084 // emitted just above the TailCall which has reset fp to the caller state.
11085 instruct TailCalljmpInd(iRegPNoSpNoFp jump_target, inline_cache_RegP method_oop)
11086 %{
11087 match(TailCall jump_target method_oop);
11088
11089 ins_cost(BRANCH_COST);
11090
11091 format %{ "jalr $jump_target\t# $method_oop holds method oop, #@TailCalljmpInd." %}
11092
11093 ins_encode(riscv_enc_tail_call(jump_target));
11094
11095 ins_pipe(pipe_class_call);
11096 %}
11097
11098 instruct TailjmpInd(iRegPNoSpNoFp jump_target, iRegP_R10 ex_oop)
11099 %{
11100 match(TailJump jump_target ex_oop);
11101
11102 ins_cost(ALU_COST + BRANCH_COST);
11103
11104 format %{ "jalr $jump_target\t# $ex_oop holds exception oop, #@TailjmpInd." %}
11105
11106 ins_encode(riscv_enc_tail_jmp(jump_target));
11107
11108 ins_pipe(pipe_class_call);
11109 %}
11110
11111 // Forward exception.
11112 instruct ForwardExceptionjmp()
11113 %{
11114 match(ForwardException);
11115
11116 ins_cost(BRANCH_COST);
11117
11118 format %{ "j forward_exception_stub\t#@ForwardException" %}
11119
11120 ins_encode %{
11121 __ far_jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
11122 %}
11123
11124 ins_pipe(pipe_class_call);
11125 %}
11126
11127 // Create exception oop: created by stack-crawling runtime code.
11128 // Created exception is now available to this handler, and is setup
11129 // just prior to jumping to this handler. No code emitted.
11130 instruct CreateException(iRegP_R10 ex_oop)
11131 %{
11132 match(Set ex_oop (CreateEx));
11133
11134 ins_cost(0);
11135 format %{ " -- \t// exception oop; no code emitted, #@CreateException" %}
11136
11137 size(0);
11138
11139 ins_encode( /*empty*/ );
11140
11141 ins_pipe(pipe_class_empty);
11142 %}
11143
11144 // Rethrow exception: The exception oop will come in the first
11145 // argument position. Then JUMP (not call) to the rethrow stub code.
11146 instruct RethrowException()
11147 %{
11148 match(Rethrow);
11149
11150 ins_cost(BRANCH_COST);
11151
11152 format %{ "j rethrow_stub\t#@RethrowException" %}
11153
11154 ins_encode(riscv_enc_rethrow());
11155
11156 ins_pipe(pipe_class_call);
11157 %}
11158
11159 // Return Instruction
11160 // epilog node loads ret address into ra as part of frame pop
11161 instruct Ret()
11162 %{
11163 match(Return);
11164
11165 ins_cost(BRANCH_COST);
11166 format %{ "ret\t// return register, #@Ret" %}
11167
11168 ins_encode(riscv_enc_ret());
11169
11170 ins_pipe(pipe_branch);
11171 %}
11172
11173 // Die now.
11174 instruct ShouldNotReachHere() %{
11175 match(Halt);
11176
11177 ins_cost(BRANCH_COST);
11178
11179 format %{ "#@ShouldNotReachHere" %}
11180
11181 ins_encode %{
11182 if (is_reachable()) {
11183 const char* str = __ code_string(_halt_reason);
11184 __ stop(str);
11185 }
11186 %}
11187
11188 ins_pipe(pipe_class_default);
11189 %}
11190
11191
11192 //----------PEEPHOLE RULES-----------------------------------------------------
11193 // These must follow all instruction definitions as they use the names
11194 // defined in the instructions definitions.
11195 //
11196 // peepmatch ( root_instr_name [preceding_instruction]* );
11197 //
11198 // peepconstraint %{
11199 // (instruction_number.operand_name relational_op instruction_number.operand_name
11200 // [, ...] );
11201 // // instruction numbers are zero-based using left to right order in peepmatch
11202 //
11203 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
11204 // // provide an instruction_number.operand_name for each operand that appears
11205 // // in the replacement instruction's match rule
11206 //
11207 // ---------VM FLAGS---------------------------------------------------------
11208 //
11209 // All peephole optimizations can be turned off using -XX:-OptoPeephole
11210 //
11211 // Each peephole rule is given an identifying number starting with zero and
11212 // increasing by one in the order seen by the parser. An individual peephole
11213 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
11214 // on the command-line.
11215 //
11216 // ---------CURRENT LIMITATIONS----------------------------------------------
11217 //
11218 // Only match adjacent instructions in same basic block
11219 // Only equality constraints
11220 // Only constraints between operands, not (0.dest_reg == RAX_enc)
11221 // Only one replacement instruction
11222 //
11223 //----------SMARTSPILL RULES---------------------------------------------------
11224 // These must follow all instruction definitions as they use the names
11225 // defined in the instructions definitions.
11226
11227 // Local Variables:
11228 // mode: c++
11229 // End: