1 //
2 // Copyright (c) 2003, 2026, Oracle and/or its affiliates. All rights reserved.
3 // Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
4 // Copyright (c) 2020, 2024, Huawei Technologies Co., Ltd. All rights reserved.
5 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
6 //
7 // This code is free software; you can redistribute it and/or modify it
8 // under the terms of the GNU General Public License version 2 only, as
9 // published by the Free Software Foundation.
10 //
11 // This code is distributed in the hope that it will be useful, but WITHOUT
12 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 // version 2 for more details (a copy is included in the LICENSE file that
15 // accompanied this code).
16 //
17 // You should have received a copy of the GNU General Public License version
18 // 2 along with this work; if not, write to the Free Software Foundation,
19 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
20 //
21 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
22 // or visit www.oracle.com if you need additional information or have any
23 // questions.
24 //
25 //
26
27 // RISCV Architecture Description File
28
29 //----------REGISTER DEFINITION BLOCK------------------------------------------
30 // This information is used by the matcher and the register allocator to
31 // describe individual registers and classes of registers within the target
32 // architecture.
33
34 register %{
35 //----------Architecture Description Register Definitions----------------------
36 // General Registers
37 // "reg_def" name ( register save type, C convention save type,
38 // ideal register type, encoding );
39 // Register Save Types:
40 //
41 // NS = No-Save: The register allocator assumes that these registers
42 // can be used without saving upon entry to the method, &
43 // that they do not need to be saved at call sites.
44 //
45 // SOC = Save-On-Call: The register allocator assumes that these registers
46 // can be used without saving upon entry to the method,
47 // but that they must be saved at call sites.
48 //
49 // SOE = Save-On-Entry: The register allocator assumes that these registers
50 // must be saved before using them upon entry to the
51 // method, but they do not need to be saved at call
52 // sites.
53 //
54 // AS = Always-Save: The register allocator assumes that these registers
55 // must be saved before using them upon entry to the
56 // method, & that they must be saved at call sites.
57 //
58 // Ideal Register Type is used to determine how to save & restore a
59 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
60 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
61 //
62 // The encoding number is the actual bit-pattern placed into the opcodes.
63
64 // We must define the 64 bit int registers in two 32 bit halves, the
65 // real lower register and a virtual upper half register. upper halves
66 // are used by the register allocator but are not actually supplied as
67 // operands to memory ops.
68 //
69 // follow the C1 compiler in making registers
70 //
71 // x7, x9-x17, x27-x31 volatile (caller save)
72 // x0-x4, x8, x23 system (no save, no allocate)
73 // x5-x6 non-allocatable (so we can use them as temporary regs)
74
75 //
76 // as regards Java usage. we don't use any callee save registers
77 // because this makes it difficult to de-optimise a frame (see comment
78 // in x86 implementation of Deoptimization::unwind_callee_save_values)
79 //
80
81 // General Registers
82
83 reg_def R0 ( NS, NS, Op_RegI, 0, x0->as_VMReg() ); // zr
84 reg_def R0_H ( NS, NS, Op_RegI, 0, x0->as_VMReg()->next() );
85 reg_def R1 ( NS, SOC, Op_RegI, 1, x1->as_VMReg() ); // ra
86 reg_def R1_H ( NS, SOC, Op_RegI, 1, x1->as_VMReg()->next() );
87 reg_def R2 ( NS, NS, Op_RegI, 2, x2->as_VMReg() ); // sp
88 reg_def R2_H ( NS, NS, Op_RegI, 2, x2->as_VMReg()->next() );
89 reg_def R3 ( NS, NS, Op_RegI, 3, x3->as_VMReg() ); // gp
90 reg_def R3_H ( NS, NS, Op_RegI, 3, x3->as_VMReg()->next() );
91 reg_def R4 ( NS, NS, Op_RegI, 4, x4->as_VMReg() ); // tp
92 reg_def R4_H ( NS, NS, Op_RegI, 4, x4->as_VMReg()->next() );
93 reg_def R7 ( SOC, SOC, Op_RegI, 7, x7->as_VMReg() );
94 reg_def R7_H ( SOC, SOC, Op_RegI, 7, x7->as_VMReg()->next() );
95 reg_def R8 ( NS, SOE, Op_RegI, 8, x8->as_VMReg() ); // fp
96 reg_def R8_H ( NS, SOE, Op_RegI, 8, x8->as_VMReg()->next() );
97 reg_def R9 ( SOC, SOE, Op_RegI, 9, x9->as_VMReg() );
98 reg_def R9_H ( SOC, SOE, Op_RegI, 9, x9->as_VMReg()->next() );
99 reg_def R10 ( SOC, SOC, Op_RegI, 10, x10->as_VMReg() );
100 reg_def R10_H ( SOC, SOC, Op_RegI, 10, x10->as_VMReg()->next());
101 reg_def R11 ( SOC, SOC, Op_RegI, 11, x11->as_VMReg() );
102 reg_def R11_H ( SOC, SOC, Op_RegI, 11, x11->as_VMReg()->next());
103 reg_def R12 ( SOC, SOC, Op_RegI, 12, x12->as_VMReg() );
104 reg_def R12_H ( SOC, SOC, Op_RegI, 12, x12->as_VMReg()->next());
105 reg_def R13 ( SOC, SOC, Op_RegI, 13, x13->as_VMReg() );
106 reg_def R13_H ( SOC, SOC, Op_RegI, 13, x13->as_VMReg()->next());
107 reg_def R14 ( SOC, SOC, Op_RegI, 14, x14->as_VMReg() );
108 reg_def R14_H ( SOC, SOC, Op_RegI, 14, x14->as_VMReg()->next());
109 reg_def R15 ( SOC, SOC, Op_RegI, 15, x15->as_VMReg() );
110 reg_def R15_H ( SOC, SOC, Op_RegI, 15, x15->as_VMReg()->next());
111 reg_def R16 ( SOC, SOC, Op_RegI, 16, x16->as_VMReg() );
112 reg_def R16_H ( SOC, SOC, Op_RegI, 16, x16->as_VMReg()->next());
113 reg_def R17 ( SOC, SOC, Op_RegI, 17, x17->as_VMReg() );
114 reg_def R17_H ( SOC, SOC, Op_RegI, 17, x17->as_VMReg()->next());
115 reg_def R18 ( SOC, SOE, Op_RegI, 18, x18->as_VMReg() );
116 reg_def R18_H ( SOC, SOE, Op_RegI, 18, x18->as_VMReg()->next());
117 reg_def R19 ( SOC, SOE, Op_RegI, 19, x19->as_VMReg() );
118 reg_def R19_H ( SOC, SOE, Op_RegI, 19, x19->as_VMReg()->next());
119 reg_def R20 ( SOC, SOE, Op_RegI, 20, x20->as_VMReg() ); // caller esp
120 reg_def R20_H ( SOC, SOE, Op_RegI, 20, x20->as_VMReg()->next());
121 reg_def R21 ( SOC, SOE, Op_RegI, 21, x21->as_VMReg() );
122 reg_def R21_H ( SOC, SOE, Op_RegI, 21, x21->as_VMReg()->next());
123 reg_def R22 ( SOC, SOE, Op_RegI, 22, x22->as_VMReg() );
124 reg_def R22_H ( SOC, SOE, Op_RegI, 22, x22->as_VMReg()->next());
125 reg_def R23 ( NS, SOE, Op_RegI, 23, x23->as_VMReg() ); // java thread
126 reg_def R23_H ( NS, SOE, Op_RegI, 23, x23->as_VMReg()->next());
127 reg_def R24 ( SOC, SOE, Op_RegI, 24, x24->as_VMReg() );
128 reg_def R24_H ( SOC, SOE, Op_RegI, 24, x24->as_VMReg()->next());
129 reg_def R25 ( SOC, SOE, Op_RegI, 25, x25->as_VMReg() );
130 reg_def R25_H ( SOC, SOE, Op_RegI, 25, x25->as_VMReg()->next());
131 reg_def R26 ( SOC, SOE, Op_RegI, 26, x26->as_VMReg() );
132 reg_def R26_H ( SOC, SOE, Op_RegI, 26, x26->as_VMReg()->next());
133 reg_def R27 ( SOC, SOE, Op_RegI, 27, x27->as_VMReg() ); // heapbase
134 reg_def R27_H ( SOC, SOE, Op_RegI, 27, x27->as_VMReg()->next());
135 reg_def R28 ( SOC, SOC, Op_RegI, 28, x28->as_VMReg() );
136 reg_def R28_H ( SOC, SOC, Op_RegI, 28, x28->as_VMReg()->next());
137 reg_def R29 ( SOC, SOC, Op_RegI, 29, x29->as_VMReg() );
138 reg_def R29_H ( SOC, SOC, Op_RegI, 29, x29->as_VMReg()->next());
139 reg_def R30 ( SOC, SOC, Op_RegI, 30, x30->as_VMReg() );
140 reg_def R30_H ( SOC, SOC, Op_RegI, 30, x30->as_VMReg()->next());
141 reg_def R31 ( SOC, SOC, Op_RegI, 31, x31->as_VMReg() );
142 reg_def R31_H ( SOC, SOC, Op_RegI, 31, x31->as_VMReg()->next());
143
144 // ----------------------------
145 // Float/Double Registers
146 // ----------------------------
147
148 // Double Registers
149
150 // The rules of ADL require that double registers be defined in pairs.
151 // Each pair must be two 32-bit values, but not necessarily a pair of
152 // single float registers. In each pair, ADLC-assigned register numbers
153 // must be adjacent, with the lower number even. Finally, when the
154 // CPU stores such a register pair to memory, the word associated with
155 // the lower ADLC-assigned number must be stored to the lower address.
156
157 // RISCV has 32 floating-point registers. Each can store a single
158 // or double precision floating-point value.
159
160 // for Java use float registers f0-f31 are always save on call whereas
161 // the platform ABI treats f8-f9 and f18-f27 as callee save). Other
162 // float registers are SOC as per the platform spec
163
164 reg_def F0 ( SOC, SOC, Op_RegF, 0, f0->as_VMReg() );
165 reg_def F0_H ( SOC, SOC, Op_RegF, 0, f0->as_VMReg()->next() );
166 reg_def F1 ( SOC, SOC, Op_RegF, 1, f1->as_VMReg() );
167 reg_def F1_H ( SOC, SOC, Op_RegF, 1, f1->as_VMReg()->next() );
168 reg_def F2 ( SOC, SOC, Op_RegF, 2, f2->as_VMReg() );
169 reg_def F2_H ( SOC, SOC, Op_RegF, 2, f2->as_VMReg()->next() );
170 reg_def F3 ( SOC, SOC, Op_RegF, 3, f3->as_VMReg() );
171 reg_def F3_H ( SOC, SOC, Op_RegF, 3, f3->as_VMReg()->next() );
172 reg_def F4 ( SOC, SOC, Op_RegF, 4, f4->as_VMReg() );
173 reg_def F4_H ( SOC, SOC, Op_RegF, 4, f4->as_VMReg()->next() );
174 reg_def F5 ( SOC, SOC, Op_RegF, 5, f5->as_VMReg() );
175 reg_def F5_H ( SOC, SOC, Op_RegF, 5, f5->as_VMReg()->next() );
176 reg_def F6 ( SOC, SOC, Op_RegF, 6, f6->as_VMReg() );
177 reg_def F6_H ( SOC, SOC, Op_RegF, 6, f6->as_VMReg()->next() );
178 reg_def F7 ( SOC, SOC, Op_RegF, 7, f7->as_VMReg() );
179 reg_def F7_H ( SOC, SOC, Op_RegF, 7, f7->as_VMReg()->next() );
180 reg_def F8 ( SOC, SOE, Op_RegF, 8, f8->as_VMReg() );
181 reg_def F8_H ( SOC, SOE, Op_RegF, 8, f8->as_VMReg()->next() );
182 reg_def F9 ( SOC, SOE, Op_RegF, 9, f9->as_VMReg() );
183 reg_def F9_H ( SOC, SOE, Op_RegF, 9, f9->as_VMReg()->next() );
184 reg_def F10 ( SOC, SOC, Op_RegF, 10, f10->as_VMReg() );
185 reg_def F10_H ( SOC, SOC, Op_RegF, 10, f10->as_VMReg()->next() );
186 reg_def F11 ( SOC, SOC, Op_RegF, 11, f11->as_VMReg() );
187 reg_def F11_H ( SOC, SOC, Op_RegF, 11, f11->as_VMReg()->next() );
188 reg_def F12 ( SOC, SOC, Op_RegF, 12, f12->as_VMReg() );
189 reg_def F12_H ( SOC, SOC, Op_RegF, 12, f12->as_VMReg()->next() );
190 reg_def F13 ( SOC, SOC, Op_RegF, 13, f13->as_VMReg() );
191 reg_def F13_H ( SOC, SOC, Op_RegF, 13, f13->as_VMReg()->next() );
192 reg_def F14 ( SOC, SOC, Op_RegF, 14, f14->as_VMReg() );
193 reg_def F14_H ( SOC, SOC, Op_RegF, 14, f14->as_VMReg()->next() );
194 reg_def F15 ( SOC, SOC, Op_RegF, 15, f15->as_VMReg() );
195 reg_def F15_H ( SOC, SOC, Op_RegF, 15, f15->as_VMReg()->next() );
196 reg_def F16 ( SOC, SOC, Op_RegF, 16, f16->as_VMReg() );
197 reg_def F16_H ( SOC, SOC, Op_RegF, 16, f16->as_VMReg()->next() );
198 reg_def F17 ( SOC, SOC, Op_RegF, 17, f17->as_VMReg() );
199 reg_def F17_H ( SOC, SOC, Op_RegF, 17, f17->as_VMReg()->next() );
200 reg_def F18 ( SOC, SOE, Op_RegF, 18, f18->as_VMReg() );
201 reg_def F18_H ( SOC, SOE, Op_RegF, 18, f18->as_VMReg()->next() );
202 reg_def F19 ( SOC, SOE, Op_RegF, 19, f19->as_VMReg() );
203 reg_def F19_H ( SOC, SOE, Op_RegF, 19, f19->as_VMReg()->next() );
204 reg_def F20 ( SOC, SOE, Op_RegF, 20, f20->as_VMReg() );
205 reg_def F20_H ( SOC, SOE, Op_RegF, 20, f20->as_VMReg()->next() );
206 reg_def F21 ( SOC, SOE, Op_RegF, 21, f21->as_VMReg() );
207 reg_def F21_H ( SOC, SOE, Op_RegF, 21, f21->as_VMReg()->next() );
208 reg_def F22 ( SOC, SOE, Op_RegF, 22, f22->as_VMReg() );
209 reg_def F22_H ( SOC, SOE, Op_RegF, 22, f22->as_VMReg()->next() );
210 reg_def F23 ( SOC, SOE, Op_RegF, 23, f23->as_VMReg() );
211 reg_def F23_H ( SOC, SOE, Op_RegF, 23, f23->as_VMReg()->next() );
212 reg_def F24 ( SOC, SOE, Op_RegF, 24, f24->as_VMReg() );
213 reg_def F24_H ( SOC, SOE, Op_RegF, 24, f24->as_VMReg()->next() );
214 reg_def F25 ( SOC, SOE, Op_RegF, 25, f25->as_VMReg() );
215 reg_def F25_H ( SOC, SOE, Op_RegF, 25, f25->as_VMReg()->next() );
216 reg_def F26 ( SOC, SOE, Op_RegF, 26, f26->as_VMReg() );
217 reg_def F26_H ( SOC, SOE, Op_RegF, 26, f26->as_VMReg()->next() );
218 reg_def F27 ( SOC, SOE, Op_RegF, 27, f27->as_VMReg() );
219 reg_def F27_H ( SOC, SOE, Op_RegF, 27, f27->as_VMReg()->next() );
220 reg_def F28 ( SOC, SOC, Op_RegF, 28, f28->as_VMReg() );
221 reg_def F28_H ( SOC, SOC, Op_RegF, 28, f28->as_VMReg()->next() );
222 reg_def F29 ( SOC, SOC, Op_RegF, 29, f29->as_VMReg() );
223 reg_def F29_H ( SOC, SOC, Op_RegF, 29, f29->as_VMReg()->next() );
224 reg_def F30 ( SOC, SOC, Op_RegF, 30, f30->as_VMReg() );
225 reg_def F30_H ( SOC, SOC, Op_RegF, 30, f30->as_VMReg()->next() );
226 reg_def F31 ( SOC, SOC, Op_RegF, 31, f31->as_VMReg() );
227 reg_def F31_H ( SOC, SOC, Op_RegF, 31, f31->as_VMReg()->next() );
228
229 // ----------------------------
230 // Vector Registers
231 // ----------------------------
232
233 // For RVV vector registers, we simply extend vector register size to 4
234 // 'logical' slots. This is nominally 128 bits but it actually covers
235 // all possible 'physical' RVV vector register lengths from 128 ~ 1024
236 // bits. The 'physical' RVV vector register length is detected during
237 // startup, so the register allocator is able to identify the correct
238 // number of bytes needed for an RVV spill/unspill.
239
240 reg_def V0 ( SOC, SOC, Op_VecA, 0, v0->as_VMReg() );
241 reg_def V0_H ( SOC, SOC, Op_VecA, 0, v0->as_VMReg()->next() );
242 reg_def V0_J ( SOC, SOC, Op_VecA, 0, v0->as_VMReg()->next(2) );
243 reg_def V0_K ( SOC, SOC, Op_VecA, 0, v0->as_VMReg()->next(3) );
244
245 reg_def V1 ( SOC, SOC, Op_VecA, 1, v1->as_VMReg() );
246 reg_def V1_H ( SOC, SOC, Op_VecA, 1, v1->as_VMReg()->next() );
247 reg_def V1_J ( SOC, SOC, Op_VecA, 1, v1->as_VMReg()->next(2) );
248 reg_def V1_K ( SOC, SOC, Op_VecA, 1, v1->as_VMReg()->next(3) );
249
250 reg_def V2 ( SOC, SOC, Op_VecA, 2, v2->as_VMReg() );
251 reg_def V2_H ( SOC, SOC, Op_VecA, 2, v2->as_VMReg()->next() );
252 reg_def V2_J ( SOC, SOC, Op_VecA, 2, v2->as_VMReg()->next(2) );
253 reg_def V2_K ( SOC, SOC, Op_VecA, 2, v2->as_VMReg()->next(3) );
254
255 reg_def V3 ( SOC, SOC, Op_VecA, 3, v3->as_VMReg() );
256 reg_def V3_H ( SOC, SOC, Op_VecA, 3, v3->as_VMReg()->next() );
257 reg_def V3_J ( SOC, SOC, Op_VecA, 3, v3->as_VMReg()->next(2) );
258 reg_def V3_K ( SOC, SOC, Op_VecA, 3, v3->as_VMReg()->next(3) );
259
260 reg_def V4 ( SOC, SOC, Op_VecA, 4, v4->as_VMReg() );
261 reg_def V4_H ( SOC, SOC, Op_VecA, 4, v4->as_VMReg()->next() );
262 reg_def V4_J ( SOC, SOC, Op_VecA, 4, v4->as_VMReg()->next(2) );
263 reg_def V4_K ( SOC, SOC, Op_VecA, 4, v4->as_VMReg()->next(3) );
264
265 reg_def V5 ( SOC, SOC, Op_VecA, 5, v5->as_VMReg() );
266 reg_def V5_H ( SOC, SOC, Op_VecA, 5, v5->as_VMReg()->next() );
267 reg_def V5_J ( SOC, SOC, Op_VecA, 5, v5->as_VMReg()->next(2) );
268 reg_def V5_K ( SOC, SOC, Op_VecA, 5, v5->as_VMReg()->next(3) );
269
270 reg_def V6 ( SOC, SOC, Op_VecA, 6, v6->as_VMReg() );
271 reg_def V6_H ( SOC, SOC, Op_VecA, 6, v6->as_VMReg()->next() );
272 reg_def V6_J ( SOC, SOC, Op_VecA, 6, v6->as_VMReg()->next(2) );
273 reg_def V6_K ( SOC, SOC, Op_VecA, 6, v6->as_VMReg()->next(3) );
274
275 reg_def V7 ( SOC, SOC, Op_VecA, 7, v7->as_VMReg() );
276 reg_def V7_H ( SOC, SOC, Op_VecA, 7, v7->as_VMReg()->next() );
277 reg_def V7_J ( SOC, SOC, Op_VecA, 7, v7->as_VMReg()->next(2) );
278 reg_def V7_K ( SOC, SOC, Op_VecA, 7, v7->as_VMReg()->next(3) );
279
280 reg_def V8 ( SOC, SOC, Op_VecA, 8, v8->as_VMReg() );
281 reg_def V8_H ( SOC, SOC, Op_VecA, 8, v8->as_VMReg()->next() );
282 reg_def V8_J ( SOC, SOC, Op_VecA, 8, v8->as_VMReg()->next(2) );
283 reg_def V8_K ( SOC, SOC, Op_VecA, 8, v8->as_VMReg()->next(3) );
284
285 reg_def V9 ( SOC, SOC, Op_VecA, 9, v9->as_VMReg() );
286 reg_def V9_H ( SOC, SOC, Op_VecA, 9, v9->as_VMReg()->next() );
287 reg_def V9_J ( SOC, SOC, Op_VecA, 9, v9->as_VMReg()->next(2) );
288 reg_def V9_K ( SOC, SOC, Op_VecA, 9, v9->as_VMReg()->next(3) );
289
290 reg_def V10 ( SOC, SOC, Op_VecA, 10, v10->as_VMReg() );
291 reg_def V10_H ( SOC, SOC, Op_VecA, 10, v10->as_VMReg()->next() );
292 reg_def V10_J ( SOC, SOC, Op_VecA, 10, v10->as_VMReg()->next(2) );
293 reg_def V10_K ( SOC, SOC, Op_VecA, 10, v10->as_VMReg()->next(3) );
294
295 reg_def V11 ( SOC, SOC, Op_VecA, 11, v11->as_VMReg() );
296 reg_def V11_H ( SOC, SOC, Op_VecA, 11, v11->as_VMReg()->next() );
297 reg_def V11_J ( SOC, SOC, Op_VecA, 11, v11->as_VMReg()->next(2) );
298 reg_def V11_K ( SOC, SOC, Op_VecA, 11, v11->as_VMReg()->next(3) );
299
300 reg_def V12 ( SOC, SOC, Op_VecA, 12, v12->as_VMReg() );
301 reg_def V12_H ( SOC, SOC, Op_VecA, 12, v12->as_VMReg()->next() );
302 reg_def V12_J ( SOC, SOC, Op_VecA, 12, v12->as_VMReg()->next(2) );
303 reg_def V12_K ( SOC, SOC, Op_VecA, 12, v12->as_VMReg()->next(3) );
304
305 reg_def V13 ( SOC, SOC, Op_VecA, 13, v13->as_VMReg() );
306 reg_def V13_H ( SOC, SOC, Op_VecA, 13, v13->as_VMReg()->next() );
307 reg_def V13_J ( SOC, SOC, Op_VecA, 13, v13->as_VMReg()->next(2) );
308 reg_def V13_K ( SOC, SOC, Op_VecA, 13, v13->as_VMReg()->next(3) );
309
310 reg_def V14 ( SOC, SOC, Op_VecA, 14, v14->as_VMReg() );
311 reg_def V14_H ( SOC, SOC, Op_VecA, 14, v14->as_VMReg()->next() );
312 reg_def V14_J ( SOC, SOC, Op_VecA, 14, v14->as_VMReg()->next(2) );
313 reg_def V14_K ( SOC, SOC, Op_VecA, 14, v14->as_VMReg()->next(3) );
314
315 reg_def V15 ( SOC, SOC, Op_VecA, 15, v15->as_VMReg() );
316 reg_def V15_H ( SOC, SOC, Op_VecA, 15, v15->as_VMReg()->next() );
317 reg_def V15_J ( SOC, SOC, Op_VecA, 15, v15->as_VMReg()->next(2) );
318 reg_def V15_K ( SOC, SOC, Op_VecA, 15, v15->as_VMReg()->next(3) );
319
320 reg_def V16 ( SOC, SOC, Op_VecA, 16, v16->as_VMReg() );
321 reg_def V16_H ( SOC, SOC, Op_VecA, 16, v16->as_VMReg()->next() );
322 reg_def V16_J ( SOC, SOC, Op_VecA, 16, v16->as_VMReg()->next(2) );
323 reg_def V16_K ( SOC, SOC, Op_VecA, 16, v16->as_VMReg()->next(3) );
324
325 reg_def V17 ( SOC, SOC, Op_VecA, 17, v17->as_VMReg() );
326 reg_def V17_H ( SOC, SOC, Op_VecA, 17, v17->as_VMReg()->next() );
327 reg_def V17_J ( SOC, SOC, Op_VecA, 17, v17->as_VMReg()->next(2) );
328 reg_def V17_K ( SOC, SOC, Op_VecA, 17, v17->as_VMReg()->next(3) );
329
330 reg_def V18 ( SOC, SOC, Op_VecA, 18, v18->as_VMReg() );
331 reg_def V18_H ( SOC, SOC, Op_VecA, 18, v18->as_VMReg()->next() );
332 reg_def V18_J ( SOC, SOC, Op_VecA, 18, v18->as_VMReg()->next(2) );
333 reg_def V18_K ( SOC, SOC, Op_VecA, 18, v18->as_VMReg()->next(3) );
334
335 reg_def V19 ( SOC, SOC, Op_VecA, 19, v19->as_VMReg() );
336 reg_def V19_H ( SOC, SOC, Op_VecA, 19, v19->as_VMReg()->next() );
337 reg_def V19_J ( SOC, SOC, Op_VecA, 19, v19->as_VMReg()->next(2) );
338 reg_def V19_K ( SOC, SOC, Op_VecA, 19, v19->as_VMReg()->next(3) );
339
340 reg_def V20 ( SOC, SOC, Op_VecA, 20, v20->as_VMReg() );
341 reg_def V20_H ( SOC, SOC, Op_VecA, 20, v20->as_VMReg()->next() );
342 reg_def V20_J ( SOC, SOC, Op_VecA, 20, v20->as_VMReg()->next(2) );
343 reg_def V20_K ( SOC, SOC, Op_VecA, 20, v20->as_VMReg()->next(3) );
344
345 reg_def V21 ( SOC, SOC, Op_VecA, 21, v21->as_VMReg() );
346 reg_def V21_H ( SOC, SOC, Op_VecA, 21, v21->as_VMReg()->next() );
347 reg_def V21_J ( SOC, SOC, Op_VecA, 21, v21->as_VMReg()->next(2) );
348 reg_def V21_K ( SOC, SOC, Op_VecA, 21, v21->as_VMReg()->next(3) );
349
350 reg_def V22 ( SOC, SOC, Op_VecA, 22, v22->as_VMReg() );
351 reg_def V22_H ( SOC, SOC, Op_VecA, 22, v22->as_VMReg()->next() );
352 reg_def V22_J ( SOC, SOC, Op_VecA, 22, v22->as_VMReg()->next(2) );
353 reg_def V22_K ( SOC, SOC, Op_VecA, 22, v22->as_VMReg()->next(3) );
354
355 reg_def V23 ( SOC, SOC, Op_VecA, 23, v23->as_VMReg() );
356 reg_def V23_H ( SOC, SOC, Op_VecA, 23, v23->as_VMReg()->next() );
357 reg_def V23_J ( SOC, SOC, Op_VecA, 23, v23->as_VMReg()->next(2) );
358 reg_def V23_K ( SOC, SOC, Op_VecA, 23, v23->as_VMReg()->next(3) );
359
360 reg_def V24 ( SOC, SOC, Op_VecA, 24, v24->as_VMReg() );
361 reg_def V24_H ( SOC, SOC, Op_VecA, 24, v24->as_VMReg()->next() );
362 reg_def V24_J ( SOC, SOC, Op_VecA, 24, v24->as_VMReg()->next(2) );
363 reg_def V24_K ( SOC, SOC, Op_VecA, 24, v24->as_VMReg()->next(3) );
364
365 reg_def V25 ( SOC, SOC, Op_VecA, 25, v25->as_VMReg() );
366 reg_def V25_H ( SOC, SOC, Op_VecA, 25, v25->as_VMReg()->next() );
367 reg_def V25_J ( SOC, SOC, Op_VecA, 25, v25->as_VMReg()->next(2) );
368 reg_def V25_K ( SOC, SOC, Op_VecA, 25, v25->as_VMReg()->next(3) );
369
370 reg_def V26 ( SOC, SOC, Op_VecA, 26, v26->as_VMReg() );
371 reg_def V26_H ( SOC, SOC, Op_VecA, 26, v26->as_VMReg()->next() );
372 reg_def V26_J ( SOC, SOC, Op_VecA, 26, v26->as_VMReg()->next(2) );
373 reg_def V26_K ( SOC, SOC, Op_VecA, 26, v26->as_VMReg()->next(3) );
374
375 reg_def V27 ( SOC, SOC, Op_VecA, 27, v27->as_VMReg() );
376 reg_def V27_H ( SOC, SOC, Op_VecA, 27, v27->as_VMReg()->next() );
377 reg_def V27_J ( SOC, SOC, Op_VecA, 27, v27->as_VMReg()->next(2) );
378 reg_def V27_K ( SOC, SOC, Op_VecA, 27, v27->as_VMReg()->next(3) );
379
380 reg_def V28 ( SOC, SOC, Op_VecA, 28, v28->as_VMReg() );
381 reg_def V28_H ( SOC, SOC, Op_VecA, 28, v28->as_VMReg()->next() );
382 reg_def V28_J ( SOC, SOC, Op_VecA, 28, v28->as_VMReg()->next(2) );
383 reg_def V28_K ( SOC, SOC, Op_VecA, 28, v28->as_VMReg()->next(3) );
384
385 reg_def V29 ( SOC, SOC, Op_VecA, 29, v29->as_VMReg() );
386 reg_def V29_H ( SOC, SOC, Op_VecA, 29, v29->as_VMReg()->next() );
387 reg_def V29_J ( SOC, SOC, Op_VecA, 29, v29->as_VMReg()->next(2) );
388 reg_def V29_K ( SOC, SOC, Op_VecA, 29, v29->as_VMReg()->next(3) );
389
390 reg_def V30 ( SOC, SOC, Op_VecA, 30, v30->as_VMReg() );
391 reg_def V30_H ( SOC, SOC, Op_VecA, 30, v30->as_VMReg()->next() );
392 reg_def V30_J ( SOC, SOC, Op_VecA, 30, v30->as_VMReg()->next(2) );
393 reg_def V30_K ( SOC, SOC, Op_VecA, 30, v30->as_VMReg()->next(3) );
394
395 reg_def V31 ( SOC, SOC, Op_VecA, 31, v31->as_VMReg() );
396 reg_def V31_H ( SOC, SOC, Op_VecA, 31, v31->as_VMReg()->next() );
397 reg_def V31_J ( SOC, SOC, Op_VecA, 31, v31->as_VMReg()->next(2) );
398 reg_def V31_K ( SOC, SOC, Op_VecA, 31, v31->as_VMReg()->next(3) );
399
400 // ----------------------------
401 // Special Registers
402 // ----------------------------
403
404 // On riscv, the physical flag register is missing, so we use t1 instead,
405 // to bridge the RegFlag semantics in share/opto
406
407 reg_def RFLAGS (SOC, SOC, Op_RegFlags, 6, x6->as_VMReg() );
408
409 // Specify priority of register selection within phases of register
410 // allocation. Highest priority is first. A useful heuristic is to
411 // give registers a low priority when they are required by machine
412 // instructions, like EAX and EDX on I486, and choose no-save registers
413 // before save-on-call, & save-on-call before save-on-entry. Registers
414 // which participate in fixed calling sequences should come last.
415 // Registers which are used as pairs must fall on an even boundary.
416
417 alloc_class chunk0(
418 // volatiles
419 R7, R7_H,
420 R28, R28_H,
421 R29, R29_H,
422 R30, R30_H,
423 R31, R31_H,
424
425 // arg registers
426 R10, R10_H,
427 R11, R11_H,
428 R12, R12_H,
429 R13, R13_H,
430 R14, R14_H,
431 R15, R15_H,
432 R16, R16_H,
433 R17, R17_H,
434
435 // non-volatiles
436 R9, R9_H,
437 R18, R18_H,
438 R19, R19_H,
439 R20, R20_H,
440 R21, R21_H,
441 R22, R22_H,
442 R24, R24_H,
443 R25, R25_H,
444 R26, R26_H,
445
446 // non-allocatable registers
447 R23, R23_H, // java thread
448 R27, R27_H, // heapbase
449 R4, R4_H, // thread
450 R8, R8_H, // fp
451 R0, R0_H, // zero
452 R1, R1_H, // ra
453 R2, R2_H, // sp
454 R3, R3_H, // gp
455 );
456
457 alloc_class chunk1(
458
459 // no save
460 F0, F0_H,
461 F1, F1_H,
462 F2, F2_H,
463 F3, F3_H,
464 F4, F4_H,
465 F5, F5_H,
466 F6, F6_H,
467 F7, F7_H,
468 F28, F28_H,
469 F29, F29_H,
470 F30, F30_H,
471 F31, F31_H,
472
473 // arg registers
474 F10, F10_H,
475 F11, F11_H,
476 F12, F12_H,
477 F13, F13_H,
478 F14, F14_H,
479 F15, F15_H,
480 F16, F16_H,
481 F17, F17_H,
482
483 // non-volatiles
484 F8, F8_H,
485 F9, F9_H,
486 F18, F18_H,
487 F19, F19_H,
488 F20, F20_H,
489 F21, F21_H,
490 F22, F22_H,
491 F23, F23_H,
492 F24, F24_H,
493 F25, F25_H,
494 F26, F26_H,
495 F27, F27_H,
496 );
497
498 alloc_class chunk2(
499 V0, V0_H, V0_J, V0_K,
500 V1, V1_H, V1_J, V1_K,
501 V2, V2_H, V2_J, V2_K,
502 V3, V3_H, V3_J, V3_K,
503 V4, V4_H, V4_J, V4_K,
504 V5, V5_H, V5_J, V5_K,
505 V6, V6_H, V6_J, V6_K,
506 V7, V7_H, V7_J, V7_K,
507 V8, V8_H, V8_J, V8_K,
508 V9, V9_H, V9_J, V9_K,
509 V10, V10_H, V10_J, V10_K,
510 V11, V11_H, V11_J, V11_K,
511 V12, V12_H, V12_J, V12_K,
512 V13, V13_H, V13_J, V13_K,
513 V14, V14_H, V14_J, V14_K,
514 V15, V15_H, V15_J, V15_K,
515 V16, V16_H, V16_J, V16_K,
516 V17, V17_H, V17_J, V17_K,
517 V18, V18_H, V18_J, V18_K,
518 V19, V19_H, V19_J, V19_K,
519 V20, V20_H, V20_J, V20_K,
520 V21, V21_H, V21_J, V21_K,
521 V22, V22_H, V22_J, V22_K,
522 V23, V23_H, V23_J, V23_K,
523 V24, V24_H, V24_J, V24_K,
524 V25, V25_H, V25_J, V25_K,
525 V26, V26_H, V26_J, V26_K,
526 V27, V27_H, V27_J, V27_K,
527 V28, V28_H, V28_J, V28_K,
528 V29, V29_H, V29_J, V29_K,
529 V30, V30_H, V30_J, V30_K,
530 V31, V31_H, V31_J, V31_K,
531 );
532
533 alloc_class chunk3(RFLAGS);
534
535 //----------Architecture Description Register Classes--------------------------
536 // Several register classes are automatically defined based upon information in
537 // this architecture description.
538 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
539 // 2) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
540 //
541
542 // Class for all 32 bit general purpose registers
543 reg_class all_reg32(
544 R0,
545 R1,
546 R2,
547 R3,
548 R4,
549 R7,
550 R8,
551 R9,
552 R10,
553 R11,
554 R12,
555 R13,
556 R14,
557 R15,
558 R16,
559 R17,
560 R18,
561 R19,
562 R20,
563 R21,
564 R22,
565 R23,
566 R24,
567 R25,
568 R26,
569 R27,
570 R28,
571 R29,
572 R30,
573 R31
574 );
575
576 // Class for any 32 bit integer registers (excluding zr)
577 reg_class any_reg32 %{
578 return _ANY_REG32_mask;
579 %}
580
581 // Singleton class for R10 int register
582 reg_class int_r10_reg(R10);
583
584 // Singleton class for R12 int register
585 reg_class int_r12_reg(R12);
586
587 // Singleton class for R13 int register
588 reg_class int_r13_reg(R13);
589
590 // Singleton class for R14 int register
591 reg_class int_r14_reg(R14);
592
593 // Class for all long integer registers
594 reg_class all_reg(
595 R0, R0_H,
596 R1, R1_H,
597 R2, R2_H,
598 R3, R3_H,
599 R4, R4_H,
600 R7, R7_H,
601 R8, R8_H,
602 R9, R9_H,
603 R10, R10_H,
604 R11, R11_H,
605 R12, R12_H,
606 R13, R13_H,
607 R14, R14_H,
608 R15, R15_H,
609 R16, R16_H,
610 R17, R17_H,
611 R18, R18_H,
612 R19, R19_H,
613 R20, R20_H,
614 R21, R21_H,
615 R22, R22_H,
616 R23, R23_H,
617 R24, R24_H,
618 R25, R25_H,
619 R26, R26_H,
620 R27, R27_H,
621 R28, R28_H,
622 R29, R29_H,
623 R30, R30_H,
624 R31, R31_H
625 );
626
627 // Class for all long integer registers (excluding zr)
628 reg_class any_reg %{
629 return _ANY_REG_mask;
630 %}
631
632 // Class for non-allocatable 32 bit registers
633 reg_class non_allocatable_reg32(
634 R0, // zr
635 R1, // ra
636 R2, // sp
637 R3, // gp
638 R4, // tp
639 R23 // java thread
640 );
641
642 // Class for non-allocatable 64 bit registers
643 reg_class non_allocatable_reg(
644 R0, R0_H, // zr
645 R1, R1_H, // ra
646 R2, R2_H, // sp
647 R3, R3_H, // gp
648 R4, R4_H, // tp
649 R23, R23_H // java thread
650 );
651
652 // Class for all non-special integer registers
653 reg_class no_special_reg32 %{
654 return _NO_SPECIAL_REG32_mask;
655 %}
656
657 // Class for all non-special long integer registers
658 reg_class no_special_reg %{
659 return _NO_SPECIAL_REG_mask;
660 %}
661
662 reg_class ptr_reg %{
663 return _PTR_REG_mask;
664 %}
665
666 // Class for all non_special pointer registers
667 reg_class no_special_ptr_reg %{
668 return _NO_SPECIAL_PTR_REG_mask;
669 %}
670
671 // Class for all non_special pointer registers (excluding fp)
672 reg_class no_special_no_fp_ptr_reg %{
673 return _NO_SPECIAL_NO_FP_PTR_REG_mask;
674 %}
675
676 // Class for 64 bit register r10
677 reg_class r10_reg(
678 R10, R10_H
679 );
680
681 // Class for 64 bit register r11
682 reg_class r11_reg(
683 R11, R11_H
684 );
685
686 // Class for 64 bit register r12
687 reg_class r12_reg(
688 R12, R12_H
689 );
690
691 // Class for 64 bit register r13
692 reg_class r13_reg(
693 R13, R13_H
694 );
695
696 // Class for 64 bit register r14
697 reg_class r14_reg(
698 R14, R14_H
699 );
700
701 // Class for 64 bit register r15
702 reg_class r15_reg(
703 R15, R15_H
704 );
705
706 // Class for 64 bit register r16
707 reg_class r16_reg(
708 R16, R16_H
709 );
710
711 // Class for method register
712 reg_class method_reg(
713 R31, R31_H
714 );
715
716 // Class for java thread register
717 reg_class java_thread_reg(
718 R23, R23_H
719 );
720
721 reg_class r28_reg(
722 R28, R28_H
723 );
724
725 reg_class r29_reg(
726 R29, R29_H
727 );
728
729 reg_class r30_reg(
730 R30, R30_H
731 );
732
733 reg_class r31_reg(
734 R31, R31_H
735 );
736
737 // Class for zero registesr
738 reg_class zr_reg(
739 R0, R0_H
740 );
741
742 // Class for thread register
743 reg_class thread_reg(
744 R4, R4_H
745 );
746
747 // Class for frame pointer register
748 reg_class fp_reg(
749 R8, R8_H
750 );
751
752 // Class for link register
753 reg_class ra_reg(
754 R1, R1_H
755 );
756
757 // Class for long sp register
758 reg_class sp_reg(
759 R2, R2_H
760 );
761
762 // Class for all float registers
763 reg_class float_reg(
764 F0,
765 F1,
766 F2,
767 F3,
768 F4,
769 F5,
770 F6,
771 F7,
772 F8,
773 F9,
774 F10,
775 F11,
776 F12,
777 F13,
778 F14,
779 F15,
780 F16,
781 F17,
782 F18,
783 F19,
784 F20,
785 F21,
786 F22,
787 F23,
788 F24,
789 F25,
790 F26,
791 F27,
792 F28,
793 F29,
794 F30,
795 F31
796 );
797
798 // Double precision float registers have virtual `high halves' that
799 // are needed by the allocator.
800 // Class for all double registers
801 reg_class double_reg(
802 F0, F0_H,
803 F1, F1_H,
804 F2, F2_H,
805 F3, F3_H,
806 F4, F4_H,
807 F5, F5_H,
808 F6, F6_H,
809 F7, F7_H,
810 F8, F8_H,
811 F9, F9_H,
812 F10, F10_H,
813 F11, F11_H,
814 F12, F12_H,
815 F13, F13_H,
816 F14, F14_H,
817 F15, F15_H,
818 F16, F16_H,
819 F17, F17_H,
820 F18, F18_H,
821 F19, F19_H,
822 F20, F20_H,
823 F21, F21_H,
824 F22, F22_H,
825 F23, F23_H,
826 F24, F24_H,
827 F25, F25_H,
828 F26, F26_H,
829 F27, F27_H,
830 F28, F28_H,
831 F29, F29_H,
832 F30, F30_H,
833 F31, F31_H
834 );
835
836 // Class for RVV vector registers
837 // Note: v0, v30 and v31 are used as mask registers.
838 reg_class vectora_reg(
839 V1, V1_H, V1_J, V1_K,
840 V2, V2_H, V2_J, V2_K,
841 V3, V3_H, V3_J, V3_K,
842 V4, V4_H, V4_J, V4_K,
843 V5, V5_H, V5_J, V5_K,
844 V6, V6_H, V6_J, V6_K,
845 V7, V7_H, V7_J, V7_K,
846 V8, V8_H, V8_J, V8_K,
847 V9, V9_H, V9_J, V9_K,
848 V10, V10_H, V10_J, V10_K,
849 V11, V11_H, V11_J, V11_K,
850 V12, V12_H, V12_J, V12_K,
851 V13, V13_H, V13_J, V13_K,
852 V14, V14_H, V14_J, V14_K,
853 V15, V15_H, V15_J, V15_K,
854 V16, V16_H, V16_J, V16_K,
855 V17, V17_H, V17_J, V17_K,
856 V18, V18_H, V18_J, V18_K,
857 V19, V19_H, V19_J, V19_K,
858 V20, V20_H, V20_J, V20_K,
859 V21, V21_H, V21_J, V21_K,
860 V22, V22_H, V22_J, V22_K,
861 V23, V23_H, V23_J, V23_K,
862 V24, V24_H, V24_J, V24_K,
863 V25, V25_H, V25_J, V25_K,
864 V26, V26_H, V26_J, V26_K,
865 V27, V27_H, V27_J, V27_K,
866 V28, V28_H, V28_J, V28_K,
867 V29, V29_H, V29_J, V29_K
868 );
869
870 // Class for 64 bit register f0
871 reg_class f0_reg(
872 F0, F0_H
873 );
874
875 // Class for 64 bit register f1
876 reg_class f1_reg(
877 F1, F1_H
878 );
879
880 // Class for 64 bit register f2
881 reg_class f2_reg(
882 F2, F2_H
883 );
884
885 // Class for 64 bit register f3
886 reg_class f3_reg(
887 F3, F3_H
888 );
889
890 // class for vector register v1
891 reg_class v1_reg(
892 V1, V1_H, V1_J, V1_K
893 );
894
895 // class for vector register v2
896 reg_class v2_reg(
897 V2, V2_H, V2_J, V2_K
898 );
899
900 // class for vector register v3
901 reg_class v3_reg(
902 V3, V3_H, V3_J, V3_K
903 );
904
905 // class for vector register v4
906 reg_class v4_reg(
907 V4, V4_H, V4_J, V4_K
908 );
909
910 // class for vector register v5
911 reg_class v5_reg(
912 V5, V5_H, V5_J, V5_K
913 );
914
915 // class for vector register v6
916 reg_class v6_reg(
917 V6, V6_H, V6_J, V6_K
918 );
919
920 // class for vector register v7
921 reg_class v7_reg(
922 V7, V7_H, V7_J, V7_K
923 );
924
925 // class for vector register v8
926 reg_class v8_reg(
927 V8, V8_H, V8_J, V8_K
928 );
929
930 // class for vector register v9
931 reg_class v9_reg(
932 V9, V9_H, V9_J, V9_K
933 );
934
935 // class for vector register v10
936 reg_class v10_reg(
937 V10, V10_H, V10_J, V10_K
938 );
939
940 // class for vector register v11
941 reg_class v11_reg(
942 V11, V11_H, V11_J, V11_K
943 );
944
945 // class for condition codes
946 reg_class reg_flags(RFLAGS);
947
948 // Class for RVV v0 mask register
949 // https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#53-vector-masking
950 // The mask value used to control execution of a masked vector
951 // instruction is always supplied by vector register v0.
952 reg_class vmask_reg_v0 (
953 V0
954 );
955
956 // Class for RVV mask registers
957 // We need two more vmask registers to do the vector mask logical ops,
958 // so define v30, v31 as mask register too.
959 reg_class vmask_reg (
960 V0,
961 V30,
962 V31
963 );
964 %}
965
966 //----------DEFINITION BLOCK---------------------------------------------------
967 // Define name --> value mappings to inform the ADLC of an integer valued name
968 // Current support includes integer values in the range [0, 0x7FFFFFFF]
969 // Format:
970 // int_def <name> ( <int_value>, <expression>);
971 // Generated Code in ad_<arch>.hpp
972 // #define <name> (<expression>)
973 // // value == <int_value>
974 // Generated code in ad_<arch>.cpp adlc_verification()
975 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
976 //
977
978 // we follow the ppc-aix port in using a simple cost model which ranks
979 // register operations as cheap, memory ops as more expensive and
980 // branches as most expensive. the first two have a low as well as a
981 // normal cost. huge cost appears to be a way of saying don't do
982 // something
983
984 definitions %{
985 // The default cost (of a register move instruction).
986 int_def DEFAULT_COST ( 100, 100);
987 int_def ALU_COST ( 100, 1 * DEFAULT_COST); // unknown, const, arith, shift, slt,
988 // multi, auipc, nop, logical, move
989 int_def LOAD_COST ( 300, 3 * DEFAULT_COST); // load, fpload
990 int_def STORE_COST ( 100, 1 * DEFAULT_COST); // store, fpstore
991 int_def XFER_COST ( 300, 3 * DEFAULT_COST); // mfc, mtc, fcvt, fmove, fcmp
992 int_def FMVX_COST ( 100, 1 * DEFAULT_COST); // shuffles with no conversion
993 int_def BRANCH_COST ( 200, 2 * DEFAULT_COST); // branch, jmp, call
994 int_def IMUL_COST ( 1000, 10 * DEFAULT_COST); // imul
995 int_def IDIVSI_COST ( 3400, 34 * DEFAULT_COST); // idivsi
996 int_def IDIVDI_COST ( 6600, 66 * DEFAULT_COST); // idivdi
997 int_def FMUL_SINGLE_COST ( 500, 5 * DEFAULT_COST); // fmul, fmadd
998 int_def FMUL_DOUBLE_COST ( 700, 7 * DEFAULT_COST); // fmul, fmadd
999 int_def FDIV_COST ( 2000, 20 * DEFAULT_COST); // fdiv
1000 int_def FSQRT_COST ( 2500, 25 * DEFAULT_COST); // fsqrt
1001 int_def VOLATILE_REF_COST ( 1000, 10 * DEFAULT_COST);
1002 int_def CACHE_MISS_COST ( 2000, 20 * DEFAULT_COST); // typicall cache miss penalty
1003 %}
1004
1005
1006
1007 //----------SOURCE BLOCK-------------------------------------------------------
1008 // This is a block of C++ code which provides values, functions, and
1009 // definitions necessary in the rest of the architecture description
1010
1011 source_hpp %{
1012
1013 #include "asm/macroAssembler.hpp"
1014 #include "gc/shared/barrierSetAssembler.hpp"
1015 #include "gc/shared/cardTable.hpp"
1016 #include "gc/shared/cardTableBarrierSet.hpp"
1017 #include "gc/shared/collectedHeap.hpp"
1018 #include "opto/addnode.hpp"
1019 #include "opto/convertnode.hpp"
1020 #include "runtime/objectMonitor.hpp"
1021
1022 extern RegMask _ANY_REG32_mask;
1023 extern RegMask _ANY_REG_mask;
1024 extern RegMask _PTR_REG_mask;
1025 extern RegMask _NO_SPECIAL_REG32_mask;
1026 extern RegMask _NO_SPECIAL_REG_mask;
1027 extern RegMask _NO_SPECIAL_PTR_REG_mask;
1028 extern RegMask _NO_SPECIAL_NO_FP_PTR_REG_mask;
1029
1030 class CallStubImpl {
1031
1032 //--------------------------------------------------------------
1033 //---< Used for optimization in Compile::shorten_branches >---
1034 //--------------------------------------------------------------
1035
1036 public:
1037 // Size of call trampoline stub.
1038 static uint size_call_trampoline() {
1039 return 0; // no call trampolines on this platform
1040 }
1041
1042 // number of relocations needed by a call trampoline stub
1043 static uint reloc_call_trampoline() {
1044 return 0; // no call trampolines on this platform
1045 }
1046 };
1047
1048 class HandlerImpl {
1049
1050 public:
1051
1052 static int emit_deopt_handler(C2_MacroAssembler* masm);
1053
1054 static uint size_deopt_handler() {
1055 // count far call + j
1056 return NativeInstruction::instruction_size + MacroAssembler::far_branch_size();
1057 }
1058 };
1059
1060 class Node::PD {
1061 public:
1062 enum NodeFlags {
1063 _last_flag = Node::_last_flag
1064 };
1065 };
1066
1067 bool is_CAS(int opcode, bool maybe_volatile);
1068
1069 // predicate controlling translation of CompareAndSwapX
1070 bool needs_acquiring_load_reserved(const Node *load);
1071
1072 // predicate controlling addressing modes
1073 bool size_fits_all_mem_uses(AddPNode* addp, int shift);
1074 %}
1075
1076 source %{
1077
1078 // Derived RegMask with conditionally allocatable registers
1079
1080 RegMask _ANY_REG32_mask;
1081 RegMask _ANY_REG_mask;
1082 RegMask _PTR_REG_mask;
1083 RegMask _NO_SPECIAL_REG32_mask;
1084 RegMask _NO_SPECIAL_REG_mask;
1085 RegMask _NO_SPECIAL_PTR_REG_mask;
1086 RegMask _NO_SPECIAL_NO_FP_PTR_REG_mask;
1087
1088 void reg_mask_init() {
1089
1090 _ANY_REG32_mask.assignFrom(_ALL_REG32_mask);
1091 _ANY_REG32_mask.remove(OptoReg::as_OptoReg(x0->as_VMReg()));
1092
1093 _ANY_REG_mask.assignFrom(_ALL_REG_mask);
1094 _ANY_REG_mask.subtract(_ZR_REG_mask);
1095
1096 _PTR_REG_mask.assignFrom(_ALL_REG_mask);
1097 _PTR_REG_mask.subtract(_ZR_REG_mask);
1098
1099 _NO_SPECIAL_REG32_mask.assignFrom(_ALL_REG32_mask);
1100 _NO_SPECIAL_REG32_mask.subtract(_NON_ALLOCATABLE_REG32_mask);
1101
1102 _NO_SPECIAL_REG_mask.assignFrom(_ALL_REG_mask);
1103 _NO_SPECIAL_REG_mask.subtract(_NON_ALLOCATABLE_REG_mask);
1104
1105 _NO_SPECIAL_PTR_REG_mask.assignFrom(_ALL_REG_mask);
1106 _NO_SPECIAL_PTR_REG_mask.subtract(_NON_ALLOCATABLE_REG_mask);
1107
1108 // x27 is not allocatable when compressed oops is on
1109 if (UseCompressedOops) {
1110 _NO_SPECIAL_REG32_mask.remove(OptoReg::as_OptoReg(x27->as_VMReg()));
1111 _NO_SPECIAL_REG_mask.remove(OptoReg::as_OptoReg(x27->as_VMReg()));
1112 _NO_SPECIAL_PTR_REG_mask.remove(OptoReg::as_OptoReg(x27->as_VMReg()));
1113 }
1114
1115 // x8 is not allocatable when PreserveFramePointer is on
1116 if (PreserveFramePointer) {
1117 _NO_SPECIAL_REG32_mask.remove(OptoReg::as_OptoReg(x8->as_VMReg()));
1118 _NO_SPECIAL_REG_mask.remove(OptoReg::as_OptoReg(x8->as_VMReg()));
1119 _NO_SPECIAL_PTR_REG_mask.remove(OptoReg::as_OptoReg(x8->as_VMReg()));
1120 }
1121
1122 _NO_SPECIAL_NO_FP_PTR_REG_mask.assignFrom(_NO_SPECIAL_PTR_REG_mask);
1123 _NO_SPECIAL_NO_FP_PTR_REG_mask.remove(OptoReg::as_OptoReg(x8->as_VMReg()));
1124 }
1125
1126 void PhaseOutput::pd_perform_mach_node_analysis() {
1127 }
1128
1129 int MachNode::pd_alignment_required() const {
1130 return 1;
1131 }
1132
1133 int MachNode::compute_padding(int current_offset) const {
1134 return 0;
1135 }
1136
1137 // is_CAS(int opcode, bool maybe_volatile)
1138 //
1139 // return true if opcode is one of the possible CompareAndSwapX
1140 // values otherwise false.
1141 bool is_CAS(int opcode, bool maybe_volatile)
1142 {
1143 switch (opcode) {
1144 // We handle these
1145 case Op_CompareAndSwapI:
1146 case Op_CompareAndSwapL:
1147 case Op_CompareAndSwapP:
1148 case Op_CompareAndSwapN:
1149 case Op_ShenandoahCompareAndSwapP:
1150 case Op_ShenandoahCompareAndSwapN:
1151 case Op_CompareAndSwapB:
1152 case Op_CompareAndSwapS:
1153 case Op_GetAndSetI:
1154 case Op_GetAndSetL:
1155 case Op_GetAndSetP:
1156 case Op_GetAndSetN:
1157 case Op_GetAndAddI:
1158 case Op_GetAndAddL:
1159 return true;
1160 case Op_CompareAndExchangeI:
1161 case Op_CompareAndExchangeN:
1162 case Op_CompareAndExchangeB:
1163 case Op_CompareAndExchangeS:
1164 case Op_CompareAndExchangeL:
1165 case Op_CompareAndExchangeP:
1166 case Op_WeakCompareAndSwapB:
1167 case Op_WeakCompareAndSwapS:
1168 case Op_WeakCompareAndSwapI:
1169 case Op_WeakCompareAndSwapL:
1170 case Op_WeakCompareAndSwapP:
1171 case Op_WeakCompareAndSwapN:
1172 case Op_ShenandoahWeakCompareAndSwapP:
1173 case Op_ShenandoahWeakCompareAndSwapN:
1174 case Op_ShenandoahCompareAndExchangeP:
1175 case Op_ShenandoahCompareAndExchangeN:
1176 return maybe_volatile;
1177 default:
1178 return false;
1179 }
1180 }
1181
1182 constexpr uint64_t MAJIK_DWORD = 0xabbaabbaabbaabbaull;
1183
1184 // predicate controlling translation of CAS
1185 //
1186 // returns true if CAS needs to use an acquiring load otherwise false
1187 bool needs_acquiring_load_reserved(const Node *n)
1188 {
1189 assert(n != nullptr && is_CAS(n->Opcode(), true), "expecting a compare and swap");
1190
1191 LoadStoreNode* ldst = n->as_LoadStore();
1192 if (n != nullptr && is_CAS(n->Opcode(), false)) {
1193 assert(ldst != nullptr && ldst->trailing_membar() != nullptr, "expected trailing membar");
1194 } else {
1195 return ldst != nullptr && ldst->trailing_membar() != nullptr;
1196 }
1197 // so we can just return true here
1198 return true;
1199 }
1200 #define __ masm->
1201
1202 // advance declarations for helper functions to convert register
1203 // indices to register objects
1204
1205 // the ad file has to provide implementations of certain methods
1206 // expected by the generic code
1207 //
1208 // REQUIRED FUNCTIONALITY
1209
1210 //=============================================================================
1211
1212 // !!!!! Special hack to get all types of calls to specify the byte offset
1213 // from the start of the call to the point where the return address
1214 // will point.
1215
1216 int MachCallStaticJavaNode::ret_addr_offset()
1217 {
1218 return 3 * NativeInstruction::instruction_size; // auipc + ld + jalr
1219 }
1220
1221 int MachCallDynamicJavaNode::ret_addr_offset()
1222 {
1223 return NativeMovConstReg::movptr2_instruction_size + (3 * NativeInstruction::instruction_size); // movptr2, auipc + ld + jal
1224 }
1225
1226 int MachCallRuntimeNode::ret_addr_offset() {
1227 // For address inside the code cache the call will be:
1228 // auipc + jalr
1229 // For real runtime callouts it will be 8 instructions
1230 // see riscv_enc_java_to_runtime
1231 // la(t0, retaddr) -> auipc + addi
1232 // sd(t0, Address(xthread, JavaThread::last_Java_pc_offset())) -> sd
1233 // movptr(t1, addr, offset, t0) -> lui + lui + slli + add
1234 // jalr(t1, offset) -> jalr
1235 if (CodeCache::contains(_entry_point)) {
1236 return 2 * NativeInstruction::instruction_size;
1237 } else {
1238 return 8 * NativeInstruction::instruction_size;
1239 }
1240 }
1241
1242 //
1243 // Compute padding required for nodes which need alignment
1244 //
1245
1246 // With RVC a call instruction may get 2-byte aligned.
1247 // The address of the call instruction needs to be 4-byte aligned to
1248 // ensure that it does not span a cache line so that it can be patched.
1249 int CallStaticJavaDirectNode::compute_padding(int current_offset) const
1250 {
1251 // to make sure the address of jal 4-byte aligned.
1252 return align_up(current_offset, alignment_required()) - current_offset;
1253 }
1254
1255 // With RVC a call instruction may get 2-byte aligned.
1256 // The address of the call instruction needs to be 4-byte aligned to
1257 // ensure that it does not span a cache line so that it can be patched.
1258 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const
1259 {
1260 // skip the movptr2 in MacroAssembler::ic_call():
1261 // lui, lui, slli, add, addi
1262 // Though movptr2() has already 4-byte aligned with or without RVC,
1263 // We need to prevent from further changes by explicitly calculating the size.
1264 current_offset += NativeMovConstReg::movptr2_instruction_size;
1265 // to make sure the address of jal 4-byte aligned.
1266 return align_up(current_offset, alignment_required()) - current_offset;
1267 }
1268
1269 int CallRuntimeDirectNode::compute_padding(int current_offset) const
1270 {
1271 return align_up(current_offset, alignment_required()) - current_offset;
1272 }
1273
1274 int CallLeafDirectNode::compute_padding(int current_offset) const
1275 {
1276 return align_up(current_offset, alignment_required()) - current_offset;
1277 }
1278
1279 int CallLeafDirectVectorNode::compute_padding(int current_offset) const
1280 {
1281 return align_up(current_offset, alignment_required()) - current_offset;
1282 }
1283
1284 int CallLeafNoFPDirectNode::compute_padding(int current_offset) const
1285 {
1286 return align_up(current_offset, alignment_required()) - current_offset;
1287 }
1288
1289 //=============================================================================
1290
1291 #ifndef PRODUCT
1292 void MachBreakpointNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1293 assert_cond(st != nullptr);
1294 st->print("BREAKPOINT");
1295 }
1296 #endif
1297
1298 void MachBreakpointNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
1299 __ ebreak();
1300 }
1301
1302 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
1303 return MachNode::size(ra_);
1304 }
1305
1306 //=============================================================================
1307
1308 #ifndef PRODUCT
1309 void MachNopNode::format(PhaseRegAlloc*, outputStream* st) const {
1310 st->print("nop \t# %d bytes pad for loops and calls", _count);
1311 }
1312 #endif
1313
1314 void MachNopNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc*) const {
1315 Assembler::CompressibleScope scope(masm); // nops shall be 2-byte under RVC for alignment purposes.
1316 for (int i = 0; i < _count; i++) {
1317 __ nop();
1318 }
1319 }
1320
1321 uint MachNopNode::size(PhaseRegAlloc*) const {
1322 return _count * (UseRVC ? NativeInstruction::compressed_instruction_size : NativeInstruction::instruction_size);
1323 }
1324
1325 //=============================================================================
1326 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::EMPTY;
1327
1328 int ConstantTable::calculate_table_base_offset() const {
1329 return 0; // absolute addressing, no offset
1330 }
1331
1332 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
1333 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
1334 ShouldNotReachHere();
1335 }
1336
1337 void MachConstantBaseNode::emit(C2_MacroAssembler* masm, PhaseRegAlloc* ra_) const {
1338 // Empty encoding
1339 }
1340
1341 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
1342 return 0;
1343 }
1344
1345 #ifndef PRODUCT
1346 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1347 assert_cond(st != nullptr);
1348 st->print("-- \t// MachConstantBaseNode (empty encoding)");
1349 }
1350 #endif
1351
1352 #ifndef PRODUCT
1353 void MachPrologNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1354 assert_cond(st != nullptr && ra_ != nullptr);
1355 Compile* C = ra_->C;
1356
1357 int framesize = C->output()->frame_slots() << LogBytesPerInt;
1358
1359 if (C->output()->need_stack_bang(framesize)) {
1360 st->print("# stack bang size=%d\n\t", framesize);
1361 }
1362
1363 st->print("sub sp, sp, #%d\n\t", framesize);
1364 st->print("sd fp, [sp, #%d]\n\t", framesize - 2 * wordSize);
1365 st->print("sd ra, [sp, #%d]\n\t", framesize - wordSize);
1366 if (PreserveFramePointer) { st->print("add fp, sp, #%d\n\t", framesize); }
1367
1368 if (VerifyStackAtCalls) {
1369 st->print("mv t2, %ld\n\t", MAJIK_DWORD);
1370 st->print("sd t2, [sp, #%d]\n\t", framesize - 3 * wordSize);
1371 }
1372
1373 if (C->stub_function() == nullptr) {
1374 st->print("ld t0, [guard]\n\t");
1375 st->print("membar LoadLoad\n\t");
1376 st->print("ld t1, [xthread, #thread_disarmed_guard_value_offset]\n\t");
1377 st->print("beq t0, t1, skip\n\t");
1378 st->print("jalr #nmethod_entry_barrier_stub\n\t");
1379 st->print("j skip\n\t");
1380 st->print("guard: int\n\t");
1381 st->print("skip:\n\t");
1382 }
1383 }
1384 #endif
1385
1386 void MachPrologNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
1387 assert_cond(ra_ != nullptr);
1388 Compile* C = ra_->C;
1389
1390 // n.b. frame size includes space for return pc and fp
1391 const int framesize = C->output()->frame_size_in_bytes();
1392
1393 assert_cond(C != nullptr);
1394
1395 if (C->clinit_barrier_on_entry()) {
1396 assert(!C->method()->holder()->is_not_initialized(), "initialization should have been started");
1397
1398 Label L_skip_barrier;
1399
1400 __ mov_metadata(t1, C->method()->holder()->constant_encoding());
1401 __ clinit_barrier(t1, t0, &L_skip_barrier);
1402 __ far_jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub()));
1403 __ bind(L_skip_barrier);
1404 }
1405
1406 int bangsize = C->output()->bang_size_in_bytes();
1407 if (C->output()->need_stack_bang(bangsize)) {
1408 __ generate_stack_overflow_check(bangsize);
1409 }
1410
1411 __ build_frame(framesize);
1412
1413 if (VerifyStackAtCalls) {
1414 __ mv(t2, MAJIK_DWORD);
1415 __ sd(t2, Address(sp, framesize - 3 * wordSize));
1416 }
1417
1418 if (C->stub_function() == nullptr) {
1419 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
1420 // Dummy labels for just measuring the code size
1421 Label dummy_slow_path;
1422 Label dummy_continuation;
1423 Label dummy_guard;
1424 Label* slow_path = &dummy_slow_path;
1425 Label* continuation = &dummy_continuation;
1426 Label* guard = &dummy_guard;
1427 if (!Compile::current()->output()->in_scratch_emit_size()) {
1428 // Use real labels from actual stub when not emitting code for purpose of measuring its size
1429 C2EntryBarrierStub* stub = new (Compile::current()->comp_arena()) C2EntryBarrierStub();
1430 Compile::current()->output()->add_stub(stub);
1431 slow_path = &stub->entry();
1432 continuation = &stub->continuation();
1433 guard = &stub->guard();
1434 }
1435 // In the C2 code, we move the non-hot part of nmethod entry barriers out-of-line to a stub.
1436 bs->nmethod_entry_barrier(masm, slow_path, continuation, guard);
1437 }
1438
1439 C->output()->set_frame_complete(__ offset());
1440
1441 if (C->has_mach_constant_base_node()) {
1442 // NOTE: We set the table base offset here because users might be
1443 // emitted before MachConstantBaseNode.
1444 ConstantTable& constant_table = C->output()->constant_table();
1445 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
1446 }
1447 }
1448
1449 uint MachPrologNode::size(PhaseRegAlloc* ra_) const
1450 {
1451 assert_cond(ra_ != nullptr);
1452 return MachNode::size(ra_); // too many variables; just compute it
1453 // the hard way
1454 }
1455
1456 int MachPrologNode::reloc() const
1457 {
1458 return 0;
1459 }
1460
1461 //=============================================================================
1462
1463 #ifndef PRODUCT
1464 void MachEpilogNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1465 assert_cond(st != nullptr && ra_ != nullptr);
1466 Compile* C = ra_->C;
1467 assert_cond(C != nullptr);
1468 int framesize = C->output()->frame_size_in_bytes();
1469
1470 st->print("# pop frame %d\n\t", framesize);
1471
1472 if (framesize == 0) {
1473 st->print("ld ra, [sp,#%d]\n\t", (2 * wordSize));
1474 st->print("ld fp, [sp,#%d]\n\t", (3 * wordSize));
1475 st->print("add sp, sp, #%d\n\t", (2 * wordSize));
1476 } else {
1477 st->print("add sp, sp, #%d\n\t", framesize);
1478 st->print("ld ra, [sp,#%d]\n\t", - 2 * wordSize);
1479 st->print("ld fp, [sp,#%d]\n\t", - wordSize);
1480 }
1481
1482 if (do_polling() && C->is_method_compilation()) {
1483 st->print("# test polling word\n\t");
1484 st->print("ld t0, [xthread,#%d]\n\t", in_bytes(JavaThread::polling_word_offset()));
1485 st->print("bgtu sp, t0, #slow_path");
1486 }
1487 }
1488 #endif
1489
1490 void MachEpilogNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
1491 assert_cond(ra_ != nullptr);
1492 Compile* C = ra_->C;
1493 assert_cond(C != nullptr);
1494 int framesize = C->output()->frame_size_in_bytes();
1495
1496 __ remove_frame(framesize);
1497
1498 if (StackReservedPages > 0 && C->has_reserved_stack_access()) {
1499 __ reserved_stack_check();
1500 }
1501
1502 if (do_polling() && C->is_method_compilation()) {
1503 Label dummy_label;
1504 Label* code_stub = &dummy_label;
1505 if (!C->output()->in_scratch_emit_size()) {
1506 C2SafepointPollStub* stub = new (C->comp_arena()) C2SafepointPollStub(__ offset());
1507 C->output()->add_stub(stub);
1508 code_stub = &stub->entry();
1509 }
1510 __ relocate(relocInfo::poll_return_type);
1511 __ safepoint_poll(*code_stub, true /* at_return */, true /* in_nmethod */);
1512 }
1513 }
1514
1515 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
1516 assert_cond(ra_ != nullptr);
1517 // Variable size. Determine dynamically.
1518 return MachNode::size(ra_);
1519 }
1520
1521 int MachEpilogNode::reloc() const {
1522 // Return number of relocatable values contained in this instruction.
1523 return 1; // 1 for polling page.
1524 }
1525 const Pipeline * MachEpilogNode::pipeline() const {
1526 return MachNode::pipeline_class();
1527 }
1528
1529 //=============================================================================
1530
1531 // Figure out which register class each belongs in: rc_int, rc_float or
1532 // rc_stack.
1533 enum RC { rc_bad, rc_int, rc_float, rc_vector, rc_stack };
1534
1535 static enum RC rc_class(OptoReg::Name reg) {
1536
1537 if (reg == OptoReg::Bad) {
1538 return rc_bad;
1539 }
1540
1541 // we have 30 int registers * 2 halves
1542 // (t0 and t1 are omitted)
1543 int slots_of_int_registers = Register::max_slots_per_register * (Register::number_of_registers - 2);
1544 if (reg < slots_of_int_registers) {
1545 return rc_int;
1546 }
1547
1548 // we have 32 float register * 2 halves
1549 int slots_of_float_registers = FloatRegister::max_slots_per_register * FloatRegister::number_of_registers;
1550 if (reg < slots_of_int_registers + slots_of_float_registers) {
1551 return rc_float;
1552 }
1553
1554 // we have 32 vector register * 4 halves
1555 int slots_of_vector_registers = VectorRegister::max_slots_per_register * VectorRegister::number_of_registers;
1556 if (reg < slots_of_int_registers + slots_of_float_registers + slots_of_vector_registers) {
1557 return rc_vector;
1558 }
1559
1560 // Between vector regs & stack is the flags regs.
1561 assert(OptoReg::is_stack(reg), "blow up if spilling flags");
1562
1563 return rc_stack;
1564 }
1565
1566 uint MachSpillCopyNode::implementation(C2_MacroAssembler *masm, PhaseRegAlloc *ra_, bool do_size, outputStream *st) const {
1567 assert_cond(ra_ != nullptr);
1568 Compile* C = ra_->C;
1569
1570 // Get registers to move.
1571 OptoReg::Name src_hi = ra_->get_reg_second(in(1));
1572 OptoReg::Name src_lo = ra_->get_reg_first(in(1));
1573 OptoReg::Name dst_hi = ra_->get_reg_second(this);
1574 OptoReg::Name dst_lo = ra_->get_reg_first(this);
1575
1576 enum RC src_hi_rc = rc_class(src_hi);
1577 enum RC src_lo_rc = rc_class(src_lo);
1578 enum RC dst_hi_rc = rc_class(dst_hi);
1579 enum RC dst_lo_rc = rc_class(dst_lo);
1580
1581 assert(src_lo != OptoReg::Bad && dst_lo != OptoReg::Bad, "must move at least 1 register");
1582
1583 if (src_hi != OptoReg::Bad && !bottom_type()->isa_vectmask()) {
1584 assert((src_lo & 1) == 0 && src_lo + 1 == src_hi &&
1585 (dst_lo & 1) == 0 && dst_lo + 1 == dst_hi,
1586 "expected aligned-adjacent pairs");
1587 }
1588
1589 if (src_lo == dst_lo && src_hi == dst_hi) {
1590 return 0; // Self copy, no move.
1591 }
1592
1593 bool is64 = (src_lo & 1) == 0 && src_lo + 1 == src_hi &&
1594 (dst_lo & 1) == 0 && dst_lo + 1 == dst_hi;
1595 int src_offset = ra_->reg2offset(src_lo);
1596 int dst_offset = ra_->reg2offset(dst_lo);
1597
1598 if (bottom_type()->isa_vect() != nullptr) {
1599 uint ireg = ideal_reg();
1600 if (ireg == Op_VecA && masm) {
1601 int vector_reg_size_in_bytes = Matcher::scalable_vector_reg_size(T_BYTE);
1602 if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
1603 // stack to stack
1604 __ spill_copy_vector_stack_to_stack(src_offset, dst_offset,
1605 vector_reg_size_in_bytes);
1606 } else if (src_lo_rc == rc_vector && dst_lo_rc == rc_stack) {
1607 // vpr to stack
1608 __ spill(as_VectorRegister(Matcher::_regEncode[src_lo]), ra_->reg2offset(dst_lo));
1609 } else if (src_lo_rc == rc_stack && dst_lo_rc == rc_vector) {
1610 // stack to vpr
1611 __ unspill(as_VectorRegister(Matcher::_regEncode[dst_lo]), ra_->reg2offset(src_lo));
1612 } else if (src_lo_rc == rc_vector && dst_lo_rc == rc_vector) {
1613 // vpr to vpr
1614 __ vsetvli_helper(T_BYTE, MaxVectorSize);
1615 __ vmv_v_v(as_VectorRegister(Matcher::_regEncode[dst_lo]), as_VectorRegister(Matcher::_regEncode[src_lo]));
1616 } else {
1617 ShouldNotReachHere();
1618 }
1619 } else if (bottom_type()->isa_vectmask() && masm) {
1620 int vmask_size_in_bytes = Matcher::scalable_predicate_reg_slots() * 32 / 8;
1621 if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
1622 // stack to stack
1623 __ spill_copy_vmask_stack_to_stack(src_offset, dst_offset,
1624 vmask_size_in_bytes);
1625 } else if (src_lo_rc == rc_vector && dst_lo_rc == rc_stack) {
1626 // vmask to stack
1627 __ spill_vmask(as_VectorRegister(Matcher::_regEncode[src_lo]), ra_->reg2offset(dst_lo));
1628 } else if (src_lo_rc == rc_stack && dst_lo_rc == rc_vector) {
1629 // stack to vmask
1630 __ unspill_vmask(as_VectorRegister(Matcher::_regEncode[dst_lo]), ra_->reg2offset(src_lo));
1631 } else if (src_lo_rc == rc_vector && dst_lo_rc == rc_vector) {
1632 // vmask to vmask
1633 __ vsetvli_helper(T_BYTE, MaxVectorSize >> 3);
1634 __ vmv_v_v(as_VectorRegister(Matcher::_regEncode[dst_lo]), as_VectorRegister(Matcher::_regEncode[src_lo]));
1635 } else {
1636 ShouldNotReachHere();
1637 }
1638 }
1639 } else if (masm != nullptr) {
1640 switch (src_lo_rc) {
1641 case rc_int:
1642 if (dst_lo_rc == rc_int) { // gpr --> gpr copy
1643 if (!is64 && this->ideal_reg() != Op_RegI) { // zero extended for narrow oop or klass
1644 __ zext(as_Register(Matcher::_regEncode[dst_lo]), as_Register(Matcher::_regEncode[src_lo]), 32);
1645 } else {
1646 __ mv(as_Register(Matcher::_regEncode[dst_lo]), as_Register(Matcher::_regEncode[src_lo]));
1647 }
1648 } else if (dst_lo_rc == rc_float) { // gpr --> fpr copy
1649 if (is64) {
1650 __ fmv_d_x(as_FloatRegister(Matcher::_regEncode[dst_lo]),
1651 as_Register(Matcher::_regEncode[src_lo]));
1652 } else {
1653 __ fmv_w_x(as_FloatRegister(Matcher::_regEncode[dst_lo]),
1654 as_Register(Matcher::_regEncode[src_lo]));
1655 }
1656 } else { // gpr --> stack spill
1657 assert(dst_lo_rc == rc_stack, "spill to bad register class");
1658 __ spill(as_Register(Matcher::_regEncode[src_lo]), is64, dst_offset);
1659 }
1660 break;
1661 case rc_float:
1662 if (dst_lo_rc == rc_int) { // fpr --> gpr copy
1663 if (is64) {
1664 __ fmv_x_d(as_Register(Matcher::_regEncode[dst_lo]),
1665 as_FloatRegister(Matcher::_regEncode[src_lo]));
1666 } else {
1667 __ fmv_x_w(as_Register(Matcher::_regEncode[dst_lo]),
1668 as_FloatRegister(Matcher::_regEncode[src_lo]));
1669 }
1670 } else if (dst_lo_rc == rc_float) { // fpr --> fpr copy
1671 if (is64) {
1672 __ fmv_d(as_FloatRegister(Matcher::_regEncode[dst_lo]),
1673 as_FloatRegister(Matcher::_regEncode[src_lo]));
1674 } else {
1675 __ fmv_s(as_FloatRegister(Matcher::_regEncode[dst_lo]),
1676 as_FloatRegister(Matcher::_regEncode[src_lo]));
1677 }
1678 } else { // fpr --> stack spill
1679 assert(dst_lo_rc == rc_stack, "spill to bad register class");
1680 __ spill(as_FloatRegister(Matcher::_regEncode[src_lo]),
1681 is64, dst_offset);
1682 }
1683 break;
1684 case rc_stack:
1685 if (dst_lo_rc == rc_int) { // stack --> gpr load
1686 if (this->ideal_reg() == Op_RegI) {
1687 __ unspill(as_Register(Matcher::_regEncode[dst_lo]), is64, src_offset);
1688 } else { // // zero extended for narrow oop or klass
1689 __ unspillu(as_Register(Matcher::_regEncode[dst_lo]), is64, src_offset);
1690 }
1691 } else if (dst_lo_rc == rc_float) { // stack --> fpr load
1692 __ unspill(as_FloatRegister(Matcher::_regEncode[dst_lo]),
1693 is64, src_offset);
1694 } else { // stack --> stack copy
1695 assert(dst_lo_rc == rc_stack, "spill to bad register class");
1696 if (this->ideal_reg() == Op_RegI) {
1697 __ unspill(t0, is64, src_offset);
1698 } else { // zero extended for narrow oop or klass
1699 __ unspillu(t0, is64, src_offset);
1700 }
1701 __ spill(t0, is64, dst_offset);
1702 }
1703 break;
1704 default:
1705 ShouldNotReachHere();
1706 }
1707 }
1708
1709 if (st != nullptr) {
1710 st->print("spill ");
1711 if (src_lo_rc == rc_stack) {
1712 st->print("[sp, #%d] -> ", src_offset);
1713 } else {
1714 st->print("%s -> ", Matcher::regName[src_lo]);
1715 }
1716 if (dst_lo_rc == rc_stack) {
1717 st->print("[sp, #%d]", dst_offset);
1718 } else {
1719 st->print("%s", Matcher::regName[dst_lo]);
1720 }
1721 if (bottom_type()->isa_vect() && !bottom_type()->isa_vectmask()) {
1722 int vsize = 0;
1723 if (ideal_reg() == Op_VecA) {
1724 vsize = Matcher::scalable_vector_reg_size(T_BYTE) * 8;
1725 } else {
1726 ShouldNotReachHere();
1727 }
1728 st->print("\t# vector spill size = %d", vsize);
1729 } else if (ideal_reg() == Op_RegVectMask) {
1730 assert(Matcher::supports_scalable_vector(), "bad register type for spill");
1731 int vsize = Matcher::scalable_predicate_reg_slots() * 32;
1732 st->print("\t# vmask spill size = %d", vsize);
1733 } else {
1734 st->print("\t# spill size = %d", is64 ? 64 : 32);
1735 }
1736 }
1737
1738 return 0;
1739 }
1740
1741 #ifndef PRODUCT
1742 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1743 if (ra_ == nullptr) {
1744 st->print("N%d = SpillCopy(N%d)", _idx, in(1)->_idx);
1745 } else {
1746 implementation(nullptr, ra_, false, st);
1747 }
1748 }
1749 #endif
1750
1751 void MachSpillCopyNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
1752 implementation(masm, ra_, false, nullptr);
1753 }
1754
1755 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1756 return MachNode::size(ra_);
1757 }
1758
1759 //=============================================================================
1760
1761 #ifndef PRODUCT
1762 void BoxLockNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1763 assert_cond(ra_ != nullptr && st != nullptr);
1764 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1765 int reg = ra_->get_reg_first(this);
1766 st->print("add %s, sp, #%d\t# box lock",
1767 Matcher::regName[reg], offset);
1768 }
1769 #endif
1770
1771 void BoxLockNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
1772 Assembler::IncompressibleScope scope(masm); // Fixed length: see BoxLockNode::size()
1773
1774 assert_cond(ra_ != nullptr);
1775 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1776 int reg = ra_->get_encode(this);
1777
1778 if (Assembler::is_simm12(offset)) {
1779 __ addi(as_Register(reg), sp, offset);
1780 } else {
1781 __ li32(t0, offset);
1782 __ add(as_Register(reg), sp, t0);
1783 }
1784 }
1785
1786 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1787 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_).
1788 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1789
1790 if (Assembler::is_simm12(offset)) {
1791 return NativeInstruction::instruction_size;
1792 } else {
1793 return 3 * NativeInstruction::instruction_size; // lui + addiw + add;
1794 }
1795 }
1796
1797 //=============================================================================
1798
1799 #ifndef PRODUCT
1800 void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1801 {
1802 assert_cond(st != nullptr);
1803 st->print_cr("# MachUEPNode");
1804 if (UseCompressedClassPointers) {
1805 st->print_cr("\tlwu t1, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass");
1806 st->print_cr("\tlwu t2, [t0 + CompiledICData::speculated_klass_offset()]\t# compressed klass");
1807 } else {
1808 st->print_cr("\tld t1, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass");
1809 st->print_cr("\tld t2, [t0 + CompiledICData::speculated_klass_offset()]\t# compressed klass");
1810 }
1811 st->print_cr("\tbeq t1, t2, ic_hit");
1812 st->print_cr("\tj, SharedRuntime::_ic_miss_stub\t # Inline cache check");
1813 st->print_cr("\tic_hit:");
1814 }
1815 #endif
1816
1817 void MachUEPNode::emit(C2_MacroAssembler* masm, PhaseRegAlloc* ra_) const
1818 {
1819 // This is the unverified entry point.
1820 __ ic_check(CodeEntryAlignment);
1821
1822 // ic_check() aligns to CodeEntryAlignment >= InteriorEntryAlignment(min 16) > NativeInstruction::instruction_size(4).
1823 assert(((__ offset()) % CodeEntryAlignment) == 0, "Misaligned verified entry point");
1824 }
1825
1826 uint MachUEPNode::size(PhaseRegAlloc* ra_) const
1827 {
1828 assert_cond(ra_ != nullptr);
1829 return MachNode::size(ra_);
1830 }
1831
1832 // REQUIRED EMIT CODE
1833
1834 //=============================================================================
1835
1836 // Emit deopt handler code.
1837 int HandlerImpl::emit_deopt_handler(C2_MacroAssembler* masm)
1838 {
1839 address base = __ start_a_stub(size_deopt_handler());
1840 if (base == nullptr) {
1841 ciEnv::current()->record_failure("CodeCache is full");
1842 return 0; // CodeBuffer::expand failed
1843 }
1844 int offset = __ offset();
1845
1846 Label start;
1847 __ bind(start);
1848
1849 __ far_call(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
1850
1851 int entry_offset = __ offset();
1852 __ j(start);
1853
1854 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1855 assert(__ offset() - entry_offset >= NativePostCallNop::first_check_size,
1856 "out of bounds read in post-call NOP check");
1857 __ end_a_stub();
1858 return entry_offset;
1859
1860 }
1861 // REQUIRED MATCHER CODE
1862
1863 //=============================================================================
1864
1865 bool Matcher::match_rule_supported(int opcode) {
1866 if (!has_match_rule(opcode)) {
1867 return false;
1868 }
1869
1870 switch (opcode) {
1871 case Op_OnSpinWait:
1872 return VM_Version::supports_on_spin_wait();
1873 case Op_CacheWB: // fall through
1874 case Op_CacheWBPreSync: // fall through
1875 case Op_CacheWBPostSync:
1876 if (!VM_Version::supports_data_cache_line_flush()) {
1877 return false;
1878 }
1879 break;
1880
1881 case Op_StrCompressedCopy: // fall through
1882 case Op_StrInflatedCopy: // fall through
1883 case Op_CountPositives: // fall through
1884 case Op_EncodeISOArray:
1885 return UseRVV;
1886
1887 case Op_PopCountI:
1888 case Op_PopCountL:
1889 return UsePopCountInstruction;
1890
1891 case Op_ReverseI:
1892 case Op_ReverseL:
1893 return UseZbkb;
1894
1895 case Op_ReverseBytesI:
1896 case Op_ReverseBytesL:
1897 case Op_ReverseBytesS:
1898 case Op_ReverseBytesUS:
1899 case Op_RotateRight:
1900 case Op_RotateLeft:
1901 case Op_CountLeadingZerosI:
1902 case Op_CountLeadingZerosL:
1903 case Op_CountTrailingZerosI:
1904 case Op_CountTrailingZerosL:
1905 return UseZbb;
1906
1907 case Op_FmaF:
1908 case Op_FmaD:
1909 return UseFMA;
1910
1911 case Op_ConvHF2F:
1912 case Op_ConvF2HF:
1913 return VM_Version::supports_float16_float_conversion();
1914 case Op_ReinterpretS2HF:
1915 case Op_ReinterpretHF2S:
1916 return UseZfh || UseZfhmin;
1917 case Op_AddHF:
1918 case Op_DivHF:
1919 case Op_FmaHF:
1920 case Op_MaxHF:
1921 case Op_MinHF:
1922 case Op_MulHF:
1923 case Op_SqrtHF:
1924 case Op_SubHF:
1925 return UseZfh;
1926
1927 case Op_CMoveP:
1928 case Op_CMoveN:
1929 return false;
1930 }
1931
1932 return true; // Per default match rules are supported.
1933 }
1934
1935 const RegMask* Matcher::predicate_reg_mask(void) {
1936 return &_VMASK_REG_mask;
1937 }
1938
1939 // Vector calling convention not yet implemented.
1940 bool Matcher::supports_vector_calling_convention(void) {
1941 return EnableVectorSupport;
1942 }
1943
1944 OptoRegPair Matcher::vector_return_value(uint ideal_reg) {
1945 assert(EnableVectorSupport, "sanity");
1946 assert(ideal_reg == Op_VecA, "sanity");
1947 // check more info at https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-cc.adoc
1948 int lo = V8_num;
1949 int hi = V8_K_num;
1950 return OptoRegPair(hi, lo);
1951 }
1952
1953 // Is this branch offset short enough that a short branch can be used?
1954 //
1955 // NOTE: If the platform does not provide any short branch variants, then
1956 // this method should return false for offset 0.
1957 // |---label(L1)-----|
1958 // |-----------------|
1959 // |-----------------|----------eq: float-------------------
1960 // |-----------------| // far_cmpD_branch | cmpD_branch
1961 // |------- ---------| feq; | feq;
1962 // |-far_cmpD_branch-| beqz done; | bnez L;
1963 // |-----------------| j L; |
1964 // |-----------------| bind(done); |
1965 // |-----------------|--------------------------------------
1966 // |-----------------| // so shortBrSize = br_size - 4;
1967 // |-----------------| // so offs = offset - shortBrSize + 4;
1968 // |---label(L2)-----|
1969 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1970 // The passed offset is relative to address of the branch.
1971 int shortBrSize = br_size - 4;
1972 int offs = offset - shortBrSize + 4;
1973 return (-4096 <= offs && offs < 4096);
1974 }
1975
1976 // Vector width in bytes.
1977 int Matcher::vector_width_in_bytes(BasicType bt) {
1978 if (UseRVV) {
1979 // The MaxVectorSize should have been set by detecting RVV max vector register size when check UseRVV.
1980 // MaxVectorSize == VM_Version::_initial_vector_length
1981 int size = MaxVectorSize;
1982 // Minimum 2 values in vector
1983 if (size < 2 * type2aelembytes(bt)) size = 0;
1984 // But never < 4
1985 if (size < 4) size = 0;
1986 return size;
1987 }
1988 return 0;
1989 }
1990
1991 // Limits on vector size (number of elements) loaded into vector.
1992 int Matcher::max_vector_size(const BasicType bt) {
1993 return vector_width_in_bytes(bt) / type2aelembytes(bt);
1994 }
1995
1996 int Matcher::min_vector_size(const BasicType bt) {
1997 int size;
1998 switch(bt) {
1999 case T_BOOLEAN:
2000 // Load/store a vector mask with only 2 elements for vector types
2001 // such as "2I/2F/2L/2D".
2002 size = 2;
2003 break;
2004 case T_BYTE:
2005 // Generate a "4B" vector, to support vector cast between "8B/16B"
2006 // and "4S/4I/4L/4F/4D".
2007 size = 4;
2008 break;
2009 case T_SHORT:
2010 // Generate a "2S" vector, to support vector cast between "4S/8S"
2011 // and "2I/2L/2F/2D".
2012 size = 2;
2013 break;
2014 default:
2015 // Limit the min vector length to 64-bit.
2016 size = 8 / type2aelembytes(bt);
2017 // The number of elements in a vector should be at least 2.
2018 size = MAX2(size, 2);
2019 }
2020
2021 int max_size = max_vector_size(bt);
2022 return MIN2(size, max_size);
2023 }
2024
2025 int Matcher::max_vector_size_auto_vectorization(const BasicType bt) {
2026 return Matcher::max_vector_size(bt);
2027 }
2028
2029 // Vector ideal reg.
2030 uint Matcher::vector_ideal_reg(int len) {
2031 assert(MaxVectorSize >= len, "");
2032 if (UseRVV) {
2033 return Op_VecA;
2034 }
2035
2036 ShouldNotReachHere();
2037 return 0;
2038 }
2039
2040 int Matcher::scalable_vector_reg_size(const BasicType bt) {
2041 return Matcher::max_vector_size(bt);
2042 }
2043
2044 MachOper* Matcher::pd_specialize_generic_vector_operand(MachOper* original_opnd, uint ideal_reg, bool is_temp) {
2045 ShouldNotReachHere(); // generic vector operands not supported
2046 return nullptr;
2047 }
2048
2049 bool Matcher::is_reg2reg_move(MachNode* m) {
2050 ShouldNotReachHere(); // generic vector operands not supported
2051 return false;
2052 }
2053
2054 bool Matcher::is_register_biasing_candidate(const MachNode* mdef, int oper_index) {
2055 return false;
2056 }
2057
2058 bool Matcher::is_generic_vector(MachOper* opnd) {
2059 ShouldNotReachHere(); // generic vector operands not supported
2060 return false;
2061 }
2062
2063 #ifdef ASSERT
2064 // Return whether or not this register is ever used as an argument.
2065 bool Matcher::can_be_java_arg(int reg)
2066 {
2067 return
2068 reg == R10_num || reg == R10_H_num ||
2069 reg == R11_num || reg == R11_H_num ||
2070 reg == R12_num || reg == R12_H_num ||
2071 reg == R13_num || reg == R13_H_num ||
2072 reg == R14_num || reg == R14_H_num ||
2073 reg == R15_num || reg == R15_H_num ||
2074 reg == R16_num || reg == R16_H_num ||
2075 reg == R17_num || reg == R17_H_num ||
2076 reg == F10_num || reg == F10_H_num ||
2077 reg == F11_num || reg == F11_H_num ||
2078 reg == F12_num || reg == F12_H_num ||
2079 reg == F13_num || reg == F13_H_num ||
2080 reg == F14_num || reg == F14_H_num ||
2081 reg == F15_num || reg == F15_H_num ||
2082 reg == F16_num || reg == F16_H_num ||
2083 reg == F17_num || reg == F17_H_num;
2084 }
2085 #endif
2086
2087 uint Matcher::int_pressure_limit()
2088 {
2089 // A derived pointer is live at CallNode and then is flagged by RA
2090 // as a spilled LRG. Spilling heuristics(Spill-USE) explicitly skip
2091 // derived pointers and lastly fail to spill after reaching maximum
2092 // number of iterations. Lowering the default pressure threshold to
2093 // (_NO_SPECIAL_REG32_mask.size() minus 1) forces CallNode to become
2094 // a high register pressure area of the code so that split_DEF can
2095 // generate DefinitionSpillCopy for the derived pointer.
2096 uint default_int_pressure_threshold = _NO_SPECIAL_REG32_mask.size() - 1;
2097 if (!PreserveFramePointer) {
2098 // When PreserveFramePointer is off, frame pointer is allocatable,
2099 // but different from other SOC registers, it is excluded from
2100 // fatproj's mask because its save type is No-Save. Decrease 1 to
2101 // ensure high pressure at fatproj when PreserveFramePointer is off.
2102 // See check_pressure_at_fatproj().
2103 default_int_pressure_threshold--;
2104 }
2105 return (INTPRESSURE == -1) ? default_int_pressure_threshold : INTPRESSURE;
2106 }
2107
2108 uint Matcher::float_pressure_limit()
2109 {
2110 // _FLOAT_REG_mask is generated by adlc from the float_reg register class.
2111 return (FLOATPRESSURE == -1) ? _FLOAT_REG_mask.size() : FLOATPRESSURE;
2112 }
2113
2114 bool Matcher::use_asm_for_ldiv_by_con(jlong divisor) {
2115 return false;
2116 }
2117
2118 const RegMask& Matcher::divI_proj_mask() {
2119 ShouldNotReachHere();
2120 return RegMask::EMPTY;
2121 }
2122
2123 // Register for MODI projection of divmodI.
2124 const RegMask& Matcher::modI_proj_mask() {
2125 ShouldNotReachHere();
2126 return RegMask::EMPTY;
2127 }
2128
2129 // Register for DIVL projection of divmodL.
2130 const RegMask& Matcher::divL_proj_mask() {
2131 ShouldNotReachHere();
2132 return RegMask::EMPTY;
2133 }
2134
2135 // Register for MODL projection of divmodL.
2136 const RegMask& Matcher::modL_proj_mask() {
2137 ShouldNotReachHere();
2138 return RegMask::EMPTY;
2139 }
2140
2141 bool size_fits_all_mem_uses(AddPNode* addp, int shift) {
2142 assert_cond(addp != nullptr);
2143 for (DUIterator_Fast imax, i = addp->fast_outs(imax); i < imax; i++) {
2144 Node* u = addp->fast_out(i);
2145 if (u != nullptr && u->is_Mem()) {
2146 int opsize = u->as_Mem()->memory_size();
2147 assert(opsize > 0, "unexpected memory operand size");
2148 if (u->as_Mem()->memory_size() != (1 << shift)) {
2149 return false;
2150 }
2151 }
2152 }
2153 return true;
2154 }
2155
2156 // Binary src (Replicate scalar/immediate)
2157 static bool is_vector_scalar_bitwise_pattern(Node* n, Node* m) {
2158 if (n == nullptr || m == nullptr) {
2159 return false;
2160 }
2161
2162 if (m->Opcode() != Op_Replicate) {
2163 return false;
2164 }
2165
2166 switch (n->Opcode()) {
2167 case Op_AndV:
2168 case Op_OrV:
2169 case Op_XorV:
2170 case Op_AddVB:
2171 case Op_AddVS:
2172 case Op_AddVI:
2173 case Op_AddVL:
2174 case Op_SubVB:
2175 case Op_SubVS:
2176 case Op_SubVI:
2177 case Op_SubVL:
2178 case Op_MulVB:
2179 case Op_MulVS:
2180 case Op_MulVI:
2181 case Op_MulVL: {
2182 return true;
2183 }
2184 default:
2185 return false;
2186 }
2187 }
2188
2189 // (XorV src (Replicate m1))
2190 // (XorVMask src (MaskAll m1))
2191 static bool is_vector_bitwise_not_pattern(Node* n, Node* m) {
2192 if (n != nullptr && m != nullptr) {
2193 return (n->Opcode() == Op_XorV || n->Opcode() == Op_XorVMask) &&
2194 VectorNode::is_all_ones_vector(m);
2195 }
2196 return false;
2197 }
2198
2199 // Should the Matcher clone input 'm' of node 'n'?
2200 bool Matcher::pd_clone_node(Node* n, Node* m, Matcher::MStack& mstack) {
2201 assert_cond(m != nullptr);
2202 if (is_vshift_con_pattern(n, m) || // ShiftV src (ShiftCntV con)
2203 is_vector_bitwise_not_pattern(n, m) ||
2204 is_vector_scalar_bitwise_pattern(n, m) ||
2205 is_encode_and_store_pattern(n, m)) {
2206 mstack.push(m, Visit);
2207 return true;
2208 }
2209 return false;
2210 }
2211
2212 // Should the Matcher clone shifts on addressing modes, expecting them
2213 // to be subsumed into complex addressing expressions or compute them
2214 // into registers?
2215 bool Matcher::pd_clone_address_expressions(AddPNode* m, Matcher::MStack& mstack, VectorSet& address_visited) {
2216 return clone_base_plus_offset_address(m, mstack, address_visited);
2217 }
2218
2219 %}
2220
2221
2222
2223 //----------ENCODING BLOCK-----------------------------------------------------
2224 // This block specifies the encoding classes used by the compiler to
2225 // output byte streams. Encoding classes are parameterized macros
2226 // used by Machine Instruction Nodes in order to generate the bit
2227 // encoding of the instruction. Operands specify their base encoding
2228 // interface with the interface keyword. There are currently
2229 // supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, &
2230 // COND_INTER. REG_INTER causes an operand to generate a function
2231 // which returns its register number when queried. CONST_INTER causes
2232 // an operand to generate a function which returns the value of the
2233 // constant when queried. MEMORY_INTER causes an operand to generate
2234 // four functions which return the Base Register, the Index Register,
2235 // the Scale Value, and the Offset Value of the operand when queried.
2236 // COND_INTER causes an operand to generate six functions which return
2237 // the encoding code (ie - encoding bits for the instruction)
2238 // associated with each basic boolean condition for a conditional
2239 // instruction.
2240 //
2241 // Instructions specify two basic values for encoding. Again, a
2242 // function is available to check if the constant displacement is an
2243 // oop. They use the ins_encode keyword to specify their encoding
2244 // classes (which must be a sequence of enc_class names, and their
2245 // parameters, specified in the encoding block), and they use the
2246 // opcode keyword to specify, in order, their primary, secondary, and
2247 // tertiary opcode. Only the opcode sections which a particular
2248 // instruction needs for encoding need to be specified.
2249 encode %{
2250 // BEGIN Non-volatile memory access
2251
2252 enc_class riscv_enc_mov_imm(iRegIorL dst, immIorL src) %{
2253 int64_t con = (int64_t)$src$$constant;
2254 Register dst_reg = as_Register($dst$$reg);
2255 __ mv(dst_reg, con);
2256 %}
2257
2258 enc_class riscv_enc_mov_p(iRegP dst, immP src) %{
2259 Register dst_reg = as_Register($dst$$reg);
2260 address con = (address)$src$$constant;
2261 if (con == nullptr || con == (address)1) {
2262 ShouldNotReachHere();
2263 } else {
2264 relocInfo::relocType rtype = $src->constant_reloc();
2265 if (rtype == relocInfo::oop_type) {
2266 __ movoop(dst_reg, (jobject)con);
2267 } else if (rtype == relocInfo::metadata_type) {
2268 __ mov_metadata(dst_reg, (Metadata*)con);
2269 } else {
2270 assert(rtype == relocInfo::none || rtype == relocInfo::external_word_type, "unexpected reloc type");
2271 __ mv(dst_reg, $src$$constant);
2272 }
2273 }
2274 %}
2275
2276 enc_class riscv_enc_mov_p1(iRegP dst) %{
2277 Register dst_reg = as_Register($dst$$reg);
2278 __ mv(dst_reg, 1);
2279 %}
2280
2281 enc_class riscv_enc_mov_n(iRegN dst, immN src) %{
2282 Register dst_reg = as_Register($dst$$reg);
2283 address con = (address)$src$$constant;
2284 if (con == nullptr) {
2285 ShouldNotReachHere();
2286 } else {
2287 relocInfo::relocType rtype = $src->constant_reloc();
2288 assert(rtype == relocInfo::oop_type, "unexpected reloc type");
2289 __ set_narrow_oop(dst_reg, (jobject)con);
2290 }
2291 %}
2292
2293 enc_class riscv_enc_mov_zero(iRegNorP dst) %{
2294 Register dst_reg = as_Register($dst$$reg);
2295 __ mv(dst_reg, zr);
2296 %}
2297
2298 enc_class riscv_enc_mov_nk(iRegN dst, immNKlass src) %{
2299 Register dst_reg = as_Register($dst$$reg);
2300 address con = (address)$src$$constant;
2301 if (con == nullptr) {
2302 ShouldNotReachHere();
2303 } else {
2304 relocInfo::relocType rtype = $src->constant_reloc();
2305 assert(rtype == relocInfo::metadata_type, "unexpected reloc type");
2306 __ set_narrow_klass(dst_reg, (Klass *)con);
2307 }
2308 %}
2309
2310 // compare and branch instruction encodings
2311
2312 enc_class riscv_enc_j(label lbl) %{
2313 Label* L = $lbl$$label;
2314 __ j(*L);
2315 %}
2316
2317 enc_class riscv_enc_far_cmpULtGe_imm0_branch(cmpOpULtGe cmp, iRegIorL op1, label lbl) %{
2318 Label* L = $lbl$$label;
2319 switch ($cmp$$cmpcode) {
2320 case(BoolTest::ge):
2321 __ j(*L);
2322 break;
2323 case(BoolTest::lt):
2324 break;
2325 default:
2326 Unimplemented();
2327 }
2328 %}
2329
2330 // call instruction encodings
2331
2332 enc_class riscv_enc_partial_subtype_check(iRegP sub, iRegP super, iRegP temp, iRegP result) %{
2333 Register sub_reg = as_Register($sub$$reg);
2334 Register super_reg = as_Register($super$$reg);
2335 Register temp_reg = as_Register($temp$$reg);
2336 Register result_reg = as_Register($result$$reg);
2337 Register cr_reg = t1;
2338
2339 Label miss;
2340 Label done;
2341 __ check_klass_subtype_slow_path(sub_reg, super_reg, temp_reg, result_reg,
2342 nullptr, &miss, /*set_cond_codes*/ true);
2343 if ($primary) {
2344 __ mv(result_reg, zr);
2345 } else {
2346 __ mv(cr_reg, zr);
2347 __ j(done);
2348 }
2349
2350 __ bind(miss);
2351 if (!$primary) {
2352 __ mv(cr_reg, 1);
2353 }
2354
2355 __ bind(done);
2356 %}
2357
2358 enc_class riscv_enc_java_static_call(method meth) %{
2359 Assembler::IncompressibleScope scope(masm); // Fixed length: see ret_addr_offset
2360
2361 address addr = (address)$meth$$method;
2362 address call = nullptr;
2363 assert_cond(addr != nullptr);
2364 if (!_method) {
2365 // A call to a runtime wrapper, e.g. new, new_typeArray_Java, uncommon_trap.
2366 call = __ reloc_call(Address(addr, relocInfo::runtime_call_type));
2367 if (call == nullptr) {
2368 ciEnv::current()->record_failure("CodeCache is full");
2369 return;
2370 }
2371 } else if (_method->intrinsic_id() == vmIntrinsicID::_ensureMaterializedForStackWalk) {
2372 // The NOP here is purely to ensure that eliding a call to
2373 // JVM_EnsureMaterializedForStackWalk doesn't change the code size.
2374 __ nop();
2375 __ nop();
2376 __ nop();
2377 __ block_comment("call JVM_EnsureMaterializedForStackWalk (elided)");
2378 } else {
2379 int method_index = resolved_method_index(masm);
2380 RelocationHolder rspec = _optimized_virtual ? opt_virtual_call_Relocation::spec(method_index)
2381 : static_call_Relocation::spec(method_index);
2382 call = __ reloc_call(Address(addr, rspec));
2383 if (call == nullptr) {
2384 ciEnv::current()->record_failure("CodeCache is full");
2385 return;
2386 }
2387
2388 if (CodeBuffer::supports_shared_stubs() && _method->can_be_statically_bound()) {
2389 // Calls of the same statically bound method can share
2390 // a stub to the interpreter.
2391 __ code()->shared_stub_to_interp_for(_method, call - (__ begin()));
2392 } else {
2393 // Emit stub for static call
2394 address stub = CompiledDirectCall::emit_to_interp_stub(masm, call);
2395 if (stub == nullptr) {
2396 ciEnv::current()->record_failure("CodeCache is full");
2397 return;
2398 }
2399 }
2400 }
2401
2402 __ post_call_nop();
2403 %}
2404
2405 enc_class riscv_enc_java_dynamic_call(method meth) %{
2406 Assembler::IncompressibleScope scope(masm); // Fixed length: see ret_addr_offset
2407 int method_index = resolved_method_index(masm);
2408 address call = __ ic_call((address)$meth$$method, method_index);
2409 if (call == nullptr) {
2410 ciEnv::current()->record_failure("CodeCache is full");
2411 return;
2412 }
2413
2414 __ post_call_nop();
2415 %}
2416
2417 enc_class riscv_enc_call_epilog() %{
2418 if (VerifyStackAtCalls) {
2419 // Check that stack depth is unchanged: find majik cookie on stack
2420 int framesize = ra_->reg2offset_unchecked(OptoReg::add(ra_->_matcher._old_SP, -3 * VMRegImpl::slots_per_word));
2421 Label stack_ok;
2422 __ ld(t1, Address(sp, framesize));
2423 __ mv(t2, MAJIK_DWORD);
2424 __ beq(t2, t1, stack_ok);
2425 __ stop("MAJIK_DWORD not found");
2426 __ bind(stack_ok);
2427 }
2428 %}
2429
2430 enc_class riscv_enc_java_to_runtime(method meth) %{
2431 Assembler::IncompressibleScope scope(masm); // Fixed length: see ret_addr_offset
2432
2433 // Some calls to generated routines (arraycopy code) are scheduled by C2
2434 // as runtime calls. if so we can call them using a far call (they will be
2435 // in the code cache, thus in a reachable segment) otherwise we have to use
2436 // a movptr+jalr pair which loads the absolute address into a register.
2437 address entry = (address)$meth$$method;
2438 if (CodeCache::contains(entry)) {
2439 __ far_call(Address(entry, relocInfo::runtime_call_type));
2440 __ post_call_nop();
2441 } else {
2442 Label retaddr;
2443 // Make the anchor frame walkable
2444 __ la(t0, retaddr);
2445 __ sd(t0, Address(xthread, JavaThread::last_Java_pc_offset()));
2446 int32_t offset = 0;
2447 // No relocation needed
2448 __ movptr(t1, entry, offset, t0); // lui + lui + slli + add
2449 __ jalr(t1, offset);
2450 __ bind(retaddr);
2451 __ post_call_nop();
2452 }
2453 %}
2454
2455 enc_class riscv_enc_tail_call(iRegP jump_target) %{
2456 Register target_reg = as_Register($jump_target$$reg);
2457 __ jr(target_reg);
2458 %}
2459
2460 enc_class riscv_enc_tail_jmp(iRegP jump_target) %{
2461 Register target_reg = as_Register($jump_target$$reg);
2462 // exception oop should be in x10
2463 // ret addr has been popped into ra
2464 // callee expects it in x13
2465 __ mv(x13, ra);
2466 __ jr(target_reg);
2467 %}
2468
2469 enc_class riscv_enc_rethrow() %{
2470 __ far_jump(RuntimeAddress(OptoRuntime::rethrow_stub()));
2471 %}
2472
2473 enc_class riscv_enc_ret() %{
2474 __ ret();
2475 %}
2476
2477 %}
2478
2479 //----------FRAME--------------------------------------------------------------
2480 // Definition of frame structure and management information.
2481 //
2482 // S T A C K L A Y O U T Allocators stack-slot number
2483 // | (to get allocators register number
2484 // G Owned by | | v add OptoReg::stack0())
2485 // r CALLER | |
2486 // o | +--------+ pad to even-align allocators stack-slot
2487 // w V | pad0 | numbers; owned by CALLER
2488 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
2489 // h ^ | in | 5
2490 // | | args | 4 Holes in incoming args owned by SELF
2491 // | | | | 3
2492 // | | +--------+
2493 // V | | old out| Empty on Intel, window on Sparc
2494 // | old |preserve| Must be even aligned.
2495 // | SP-+--------+----> Matcher::_old_SP, even aligned
2496 // | | in | 3 area for Intel ret address
2497 // Owned by |preserve| Empty on Sparc.
2498 // SELF +--------+
2499 // | | pad2 | 2 pad to align old SP
2500 // | +--------+ 1
2501 // | | locks | 0
2502 // | +--------+----> OptoReg::stack0(), even aligned
2503 // | | pad1 | 11 pad to align new SP
2504 // | +--------+
2505 // | | | 10
2506 // | | spills | 9 spills
2507 // V | | 8 (pad0 slot for callee)
2508 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
2509 // ^ | out | 7
2510 // | | args | 6 Holes in outgoing args owned by CALLEE
2511 // Owned by +--------+
2512 // CALLEE | new out| 6 Empty on Intel, window on Sparc
2513 // | new |preserve| Must be even-aligned.
2514 // | SP-+--------+----> Matcher::_new_SP, even aligned
2515 // | | |
2516 //
2517 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
2518 // known from SELF's arguments and the Java calling convention.
2519 // Region 6-7 is determined per call site.
2520 // Note 2: If the calling convention leaves holes in the incoming argument
2521 // area, those holes are owned by SELF. Holes in the outgoing area
2522 // are owned by the CALLEE. Holes should not be necessary in the
2523 // incoming area, as the Java calling convention is completely under
2524 // the control of the AD file. Doubles can be sorted and packed to
2525 // avoid holes. Holes in the outgoing arguments may be necessary for
2526 // varargs C calling conventions.
2527 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
2528 // even aligned with pad0 as needed.
2529 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
2530 // (the latter is true on Intel but is it false on RISCV?)
2531 // region 6-11 is even aligned; it may be padded out more so that
2532 // the region from SP to FP meets the minimum stack alignment.
2533 // Note 4: For I2C adapters, the incoming FP may not meet the minimum stack
2534 // alignment. Region 11, pad1, may be dynamically extended so that
2535 // SP meets the minimum alignment.
2536
2537 frame %{
2538 // These three registers define part of the calling convention
2539 // between compiled code and the interpreter.
2540
2541 // Inline Cache Register or methodOop for I2C.
2542 inline_cache_reg(R31);
2543
2544 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
2545 cisc_spilling_operand_name(indOffset);
2546
2547 // Number of stack slots consumed by locking an object
2548 // generate Compile::sync_stack_slots
2549 // VMRegImpl::slots_per_word = wordSize / stack_slot_size = 8 / 4 = 2
2550 sync_stack_slots(1 * VMRegImpl::slots_per_word);
2551
2552 // Compiled code's Frame Pointer
2553 frame_pointer(R2);
2554
2555 // Stack alignment requirement
2556 stack_alignment(StackAlignmentInBytes); // Alignment size in bytes (128-bit -> 16 bytes)
2557
2558 // Number of outgoing stack slots killed above the out_preserve_stack_slots
2559 // for calls to C. Supports the var-args backing area for register parms.
2560 varargs_C_out_slots_killed(frame::arg_reg_save_area_bytes / BytesPerInt);
2561
2562 // The after-PROLOG location of the return address. Location of
2563 // return address specifies a type (REG or STACK) and a number
2564 // representing the register number (i.e. - use a register name) or
2565 // stack slot.
2566 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
2567 // Otherwise, it is above the locks and verification slot and alignment word
2568 // TODO this may well be correct but need to check why that - 2 is there
2569 // ppc port uses 0 but we definitely need to allow for fixed_slots
2570 // which folds in the space used for monitors
2571 return_addr(STACK - 2 +
2572 align_up((Compile::current()->in_preserve_stack_slots() +
2573 Compile::current()->fixed_slots()),
2574 stack_alignment_in_slots()));
2575
2576 // Location of compiled Java return values. Same as C for now.
2577 return_value
2578 %{
2579 assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL,
2580 "only return normal values");
2581
2582 static const int lo[Op_RegL + 1] = { // enum name
2583 0, // Op_Node
2584 0, // Op_Set
2585 R10_num, // Op_RegN
2586 R10_num, // Op_RegI
2587 R10_num, // Op_RegP
2588 F10_num, // Op_RegF
2589 F10_num, // Op_RegD
2590 R10_num // Op_RegL
2591 };
2592
2593 static const int hi[Op_RegL + 1] = { // enum name
2594 0, // Op_Node
2595 0, // Op_Set
2596 OptoReg::Bad, // Op_RegN
2597 OptoReg::Bad, // Op_RegI
2598 R10_H_num, // Op_RegP
2599 OptoReg::Bad, // Op_RegF
2600 F10_H_num, // Op_RegD
2601 R10_H_num // Op_RegL
2602 };
2603
2604 return OptoRegPair(hi[ideal_reg], lo[ideal_reg]);
2605 %}
2606 %}
2607
2608 //----------ATTRIBUTES---------------------------------------------------------
2609 //----------Operand Attributes-------------------------------------------------
2610 op_attrib op_cost(1); // Required cost attribute
2611
2612 //----------Instruction Attributes---------------------------------------------
2613 ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute
2614 ins_attrib ins_size(32); // Required size attribute (in bits)
2615 ins_attrib ins_short_branch(0); // Required flag: is this instruction
2616 // a non-matching short branch variant
2617 // of some long branch?
2618 ins_attrib ins_alignment(4); // Required alignment attribute (must
2619 // be a power of 2) specifies the
2620 // alignment that some part of the
2621 // instruction (not necessarily the
2622 // start) requires. If > 1, a
2623 // compute_padding() function must be
2624 // provided for the instruction
2625
2626 // Whether this node is expanded during code emission into a sequence of
2627 // instructions and the first instruction can perform an implicit null check.
2628 ins_attrib ins_is_late_expanded_null_check_candidate(false);
2629
2630 //----------OPERANDS-----------------------------------------------------------
2631 // Operand definitions must precede instruction definitions for correct parsing
2632 // in the ADLC because operands constitute user defined types which are used in
2633 // instruction definitions.
2634
2635 //----------Simple Operands----------------------------------------------------
2636
2637 // Integer operands 32 bit
2638 // 32 bit immediate
2639 operand immI()
2640 %{
2641 match(ConI);
2642
2643 op_cost(0);
2644 format %{ %}
2645 interface(CONST_INTER);
2646 %}
2647
2648 // 32 bit zero
2649 operand immI0()
2650 %{
2651 predicate(n->get_int() == 0);
2652 match(ConI);
2653
2654 op_cost(0);
2655 format %{ %}
2656 interface(CONST_INTER);
2657 %}
2658
2659 // 32 bit unit increment
2660 operand immI_1()
2661 %{
2662 predicate(n->get_int() == 1);
2663 match(ConI);
2664
2665 op_cost(0);
2666 format %{ %}
2667 interface(CONST_INTER);
2668 %}
2669
2670 // 32 bit unit decrement
2671 operand immI_M1()
2672 %{
2673 predicate(n->get_int() == -1);
2674 match(ConI);
2675
2676 op_cost(0);
2677 format %{ %}
2678 interface(CONST_INTER);
2679 %}
2680
2681 // Unsigned Integer Immediate: 6-bit int, greater than 32
2682 operand uimmI6_ge32() %{
2683 predicate(((unsigned int)(n->get_int()) < 64) && (n->get_int() >= 32));
2684 match(ConI);
2685 op_cost(0);
2686 format %{ %}
2687 interface(CONST_INTER);
2688 %}
2689
2690 operand immI_le_4()
2691 %{
2692 predicate(n->get_int() <= 4);
2693 match(ConI);
2694
2695 op_cost(0);
2696 format %{ %}
2697 interface(CONST_INTER);
2698 %}
2699
2700 operand immI_16()
2701 %{
2702 predicate(n->get_int() == 16);
2703 match(ConI);
2704 op_cost(0);
2705 format %{ %}
2706 interface(CONST_INTER);
2707 %}
2708
2709 operand immI_24()
2710 %{
2711 predicate(n->get_int() == 24);
2712 match(ConI);
2713 op_cost(0);
2714 format %{ %}
2715 interface(CONST_INTER);
2716 %}
2717
2718 operand immI_31()
2719 %{
2720 predicate(n->get_int() == 31);
2721 match(ConI);
2722
2723 op_cost(0);
2724 format %{ %}
2725 interface(CONST_INTER);
2726 %}
2727
2728 operand immI_63()
2729 %{
2730 predicate(n->get_int() == 63);
2731 match(ConI);
2732
2733 op_cost(0);
2734 format %{ %}
2735 interface(CONST_INTER);
2736 %}
2737
2738 // 32 bit integer valid for add immediate
2739 operand immIAdd()
2740 %{
2741 predicate(Assembler::is_simm12((int64_t)n->get_int()));
2742 match(ConI);
2743 op_cost(0);
2744 format %{ %}
2745 interface(CONST_INTER);
2746 %}
2747
2748 // 32 bit integer valid for sub immediate
2749 operand immISub()
2750 %{
2751 predicate(Assembler::is_simm12(-(int64_t)n->get_int()));
2752 match(ConI);
2753 op_cost(0);
2754 format %{ %}
2755 interface(CONST_INTER);
2756 %}
2757
2758 // 5 bit signed value.
2759 operand immI5()
2760 %{
2761 predicate(n->get_int() <= 15 && n->get_int() >= -16);
2762 match(ConI);
2763
2764 op_cost(0);
2765 format %{ %}
2766 interface(CONST_INTER);
2767 %}
2768
2769 // 5 bit signed value (simm5)
2770 operand immL5()
2771 %{
2772 predicate(n->get_long() <= 15 && n->get_long() >= -16);
2773 match(ConL);
2774
2775 op_cost(0);
2776 format %{ %}
2777 interface(CONST_INTER);
2778 %}
2779
2780 // Integer operands 64 bit
2781 // 64 bit immediate
2782 operand immL()
2783 %{
2784 match(ConL);
2785
2786 op_cost(0);
2787 format %{ %}
2788 interface(CONST_INTER);
2789 %}
2790
2791 // 64 bit zero
2792 operand immL0()
2793 %{
2794 predicate(n->get_long() == 0);
2795 match(ConL);
2796
2797 op_cost(0);
2798 format %{ %}
2799 interface(CONST_INTER);
2800 %}
2801
2802 // Pointer operands
2803 // Pointer Immediate
2804 operand immP()
2805 %{
2806 match(ConP);
2807
2808 op_cost(0);
2809 format %{ %}
2810 interface(CONST_INTER);
2811 %}
2812
2813 // Null Pointer Immediate
2814 operand immP0()
2815 %{
2816 predicate(n->get_ptr() == 0);
2817 match(ConP);
2818
2819 op_cost(0);
2820 format %{ %}
2821 interface(CONST_INTER);
2822 %}
2823
2824 // Pointer Immediate One
2825 // this is used in object initialization (initial object header)
2826 operand immP_1()
2827 %{
2828 predicate(n->get_ptr() == 1);
2829 match(ConP);
2830
2831 op_cost(0);
2832 format %{ %}
2833 interface(CONST_INTER);
2834 %}
2835
2836 // Int Immediate: low 16-bit mask
2837 operand immI_16bits()
2838 %{
2839 predicate(n->get_int() == 0xFFFF);
2840 match(ConI);
2841 op_cost(0);
2842 format %{ %}
2843 interface(CONST_INTER);
2844 %}
2845
2846 operand immIpowerOf2() %{
2847 predicate(is_power_of_2((juint)(n->get_int())));
2848 match(ConI);
2849 op_cost(0);
2850 format %{ %}
2851 interface(CONST_INTER);
2852 %}
2853
2854 // Long Immediate: low 32-bit mask
2855 operand immL_32bits()
2856 %{
2857 predicate(n->get_long() == 0xFFFFFFFFL);
2858 match(ConL);
2859 op_cost(0);
2860 format %{ %}
2861 interface(CONST_INTER);
2862 %}
2863
2864 // 64 bit unit decrement
2865 operand immL_M1()
2866 %{
2867 predicate(n->get_long() == -1);
2868 match(ConL);
2869
2870 op_cost(0);
2871 format %{ %}
2872 interface(CONST_INTER);
2873 %}
2874
2875
2876 // 64 bit integer valid for add immediate
2877 operand immLAdd()
2878 %{
2879 predicate(Assembler::is_simm12(n->get_long()));
2880 match(ConL);
2881 op_cost(0);
2882 format %{ %}
2883 interface(CONST_INTER);
2884 %}
2885
2886 // 64 bit integer valid for sub immediate
2887 operand immLSub()
2888 %{
2889 predicate(Assembler::is_simm12(-(n->get_long())));
2890 match(ConL);
2891 op_cost(0);
2892 format %{ %}
2893 interface(CONST_INTER);
2894 %}
2895
2896 // Narrow pointer operands
2897 // Narrow Pointer Immediate
2898 operand immN()
2899 %{
2900 match(ConN);
2901
2902 op_cost(0);
2903 format %{ %}
2904 interface(CONST_INTER);
2905 %}
2906
2907 // Narrow Null Pointer Immediate
2908 operand immN0()
2909 %{
2910 predicate(n->get_narrowcon() == 0);
2911 match(ConN);
2912
2913 op_cost(0);
2914 format %{ %}
2915 interface(CONST_INTER);
2916 %}
2917
2918 operand immNKlass()
2919 %{
2920 match(ConNKlass);
2921
2922 op_cost(0);
2923 format %{ %}
2924 interface(CONST_INTER);
2925 %}
2926
2927 // Float and Double operands
2928 // Double Immediate
2929 operand immD()
2930 %{
2931 match(ConD);
2932 op_cost(0);
2933 format %{ %}
2934 interface(CONST_INTER);
2935 %}
2936
2937 // Double Immediate: +0.0d
2938 operand immD0()
2939 %{
2940 predicate(jlong_cast(n->getd()) == 0);
2941 match(ConD);
2942
2943 op_cost(0);
2944 format %{ %}
2945 interface(CONST_INTER);
2946 %}
2947
2948 // Float Immediate
2949 operand immF()
2950 %{
2951 match(ConF);
2952 op_cost(0);
2953 format %{ %}
2954 interface(CONST_INTER);
2955 %}
2956
2957 // Float Immediate: +0.0f.
2958 operand immF0()
2959 %{
2960 predicate(jint_cast(n->getf()) == 0);
2961 match(ConF);
2962
2963 op_cost(0);
2964 format %{ %}
2965 interface(CONST_INTER);
2966 %}
2967
2968 // Half Float Immediate
2969 operand immH()
2970 %{
2971 match(ConH);
2972
2973 op_cost(0);
2974 format %{ %}
2975 interface(CONST_INTER);
2976 %}
2977
2978 // Half Float Immediate: +0.0f.
2979 operand immH0()
2980 %{
2981 predicate(jint_cast(n->geth()) == 0);
2982 match(ConH);
2983
2984 op_cost(0);
2985 format %{ %}
2986 interface(CONST_INTER);
2987 %}
2988
2989 operand immIOffset()
2990 %{
2991 predicate(Assembler::is_simm12(n->get_int()));
2992 match(ConI);
2993 op_cost(0);
2994 format %{ %}
2995 interface(CONST_INTER);
2996 %}
2997
2998 operand immLOffset()
2999 %{
3000 predicate(Assembler::is_simm12(n->get_long()));
3001 match(ConL);
3002 op_cost(0);
3003 format %{ %}
3004 interface(CONST_INTER);
3005 %}
3006
3007 // Scale values
3008 operand immIScale()
3009 %{
3010 predicate(1 <= n->get_int() && (n->get_int() <= 3));
3011 match(ConI);
3012
3013 op_cost(0);
3014 format %{ %}
3015 interface(CONST_INTER);
3016 %}
3017
3018 // Integer 32 bit Register Operands
3019 operand iRegI()
3020 %{
3021 constraint(ALLOC_IN_RC(any_reg32));
3022 match(RegI);
3023 match(iRegINoSp);
3024 op_cost(0);
3025 format %{ %}
3026 interface(REG_INTER);
3027 %}
3028
3029 // Integer 32 bit Register not Special
3030 operand iRegINoSp()
3031 %{
3032 constraint(ALLOC_IN_RC(no_special_reg32));
3033 match(RegI);
3034 op_cost(0);
3035 format %{ %}
3036 interface(REG_INTER);
3037 %}
3038
3039 // Register R10 only
3040 operand iRegI_R10()
3041 %{
3042 constraint(ALLOC_IN_RC(int_r10_reg));
3043 match(RegI);
3044 match(iRegINoSp);
3045 op_cost(0);
3046 format %{ %}
3047 interface(REG_INTER);
3048 %}
3049
3050 // Register R12 only
3051 operand iRegI_R12()
3052 %{
3053 constraint(ALLOC_IN_RC(int_r12_reg));
3054 match(RegI);
3055 match(iRegINoSp);
3056 op_cost(0);
3057 format %{ %}
3058 interface(REG_INTER);
3059 %}
3060
3061 // Register R13 only
3062 operand iRegI_R13()
3063 %{
3064 constraint(ALLOC_IN_RC(int_r13_reg));
3065 match(RegI);
3066 match(iRegINoSp);
3067 op_cost(0);
3068 format %{ %}
3069 interface(REG_INTER);
3070 %}
3071
3072 // Register R14 only
3073 operand iRegI_R14()
3074 %{
3075 constraint(ALLOC_IN_RC(int_r14_reg));
3076 match(RegI);
3077 match(iRegINoSp);
3078 op_cost(0);
3079 format %{ %}
3080 interface(REG_INTER);
3081 %}
3082
3083 // Integer 64 bit Register Operands
3084 operand iRegL()
3085 %{
3086 constraint(ALLOC_IN_RC(any_reg));
3087 match(RegL);
3088 match(iRegLNoSp);
3089 op_cost(0);
3090 format %{ %}
3091 interface(REG_INTER);
3092 %}
3093
3094 // Integer 64 bit Register not Special
3095 operand iRegLNoSp()
3096 %{
3097 constraint(ALLOC_IN_RC(no_special_reg));
3098 match(RegL);
3099 match(iRegL_R10);
3100 format %{ %}
3101 interface(REG_INTER);
3102 %}
3103
3104 // Long 64 bit Register R29 only
3105 operand iRegL_R29()
3106 %{
3107 constraint(ALLOC_IN_RC(r29_reg));
3108 match(RegL);
3109 match(iRegLNoSp);
3110 op_cost(0);
3111 format %{ %}
3112 interface(REG_INTER);
3113 %}
3114
3115 // Long 64 bit Register R30 only
3116 operand iRegL_R30()
3117 %{
3118 constraint(ALLOC_IN_RC(r30_reg));
3119 match(RegL);
3120 match(iRegLNoSp);
3121 op_cost(0);
3122 format %{ %}
3123 interface(REG_INTER);
3124 %}
3125
3126 // Pointer Register Operands
3127 // Pointer Register
3128 operand iRegP()
3129 %{
3130 constraint(ALLOC_IN_RC(ptr_reg));
3131 match(RegP);
3132 match(iRegPNoSp);
3133 match(iRegP_R10);
3134 match(iRegP_R15);
3135 match(javaThread_RegP);
3136 op_cost(0);
3137 format %{ %}
3138 interface(REG_INTER);
3139 %}
3140
3141 // Pointer 64 bit Register not Special
3142 operand iRegPNoSp()
3143 %{
3144 constraint(ALLOC_IN_RC(no_special_ptr_reg));
3145 match(RegP);
3146 op_cost(0);
3147 format %{ %}
3148 interface(REG_INTER);
3149 %}
3150
3151 // This operand is not allowed to use fp even if
3152 // fp is not used to hold the frame pointer.
3153 operand iRegPNoSpNoFp()
3154 %{
3155 constraint(ALLOC_IN_RC(no_special_no_fp_ptr_reg));
3156 match(RegP);
3157 match(iRegPNoSp);
3158 op_cost(0);
3159 format %{ %}
3160 interface(REG_INTER);
3161 %}
3162
3163 operand iRegP_R10()
3164 %{
3165 constraint(ALLOC_IN_RC(r10_reg));
3166 match(RegP);
3167 // match(iRegP);
3168 match(iRegPNoSp);
3169 op_cost(0);
3170 format %{ %}
3171 interface(REG_INTER);
3172 %}
3173
3174 // Pointer 64 bit Register R11 only
3175 operand iRegP_R11()
3176 %{
3177 constraint(ALLOC_IN_RC(r11_reg));
3178 match(RegP);
3179 match(iRegPNoSp);
3180 op_cost(0);
3181 format %{ %}
3182 interface(REG_INTER);
3183 %}
3184
3185 operand iRegP_R12()
3186 %{
3187 constraint(ALLOC_IN_RC(r12_reg));
3188 match(RegP);
3189 // match(iRegP);
3190 match(iRegPNoSp);
3191 op_cost(0);
3192 format %{ %}
3193 interface(REG_INTER);
3194 %}
3195
3196 // Pointer 64 bit Register R13 only
3197 operand iRegP_R13()
3198 %{
3199 constraint(ALLOC_IN_RC(r13_reg));
3200 match(RegP);
3201 match(iRegPNoSp);
3202 op_cost(0);
3203 format %{ %}
3204 interface(REG_INTER);
3205 %}
3206
3207 operand iRegP_R14()
3208 %{
3209 constraint(ALLOC_IN_RC(r14_reg));
3210 match(RegP);
3211 // match(iRegP);
3212 match(iRegPNoSp);
3213 op_cost(0);
3214 format %{ %}
3215 interface(REG_INTER);
3216 %}
3217
3218 operand iRegP_R15()
3219 %{
3220 constraint(ALLOC_IN_RC(r15_reg));
3221 match(RegP);
3222 // match(iRegP);
3223 match(iRegPNoSp);
3224 op_cost(0);
3225 format %{ %}
3226 interface(REG_INTER);
3227 %}
3228
3229 operand iRegP_R16()
3230 %{
3231 constraint(ALLOC_IN_RC(r16_reg));
3232 match(RegP);
3233 match(iRegPNoSp);
3234 op_cost(0);
3235 format %{ %}
3236 interface(REG_INTER);
3237 %}
3238
3239 // Pointer 64 bit Register R28 only
3240 operand iRegP_R28()
3241 %{
3242 constraint(ALLOC_IN_RC(r28_reg));
3243 match(RegP);
3244 match(iRegPNoSp);
3245 op_cost(0);
3246 format %{ %}
3247 interface(REG_INTER);
3248 %}
3249
3250 // Pointer 64 bit Register R30 only
3251 operand iRegP_R30()
3252 %{
3253 constraint(ALLOC_IN_RC(r30_reg));
3254 match(RegP);
3255 match(iRegPNoSp);
3256 op_cost(0);
3257 format %{ %}
3258 interface(REG_INTER);
3259 %}
3260
3261 // Pointer 64 bit Register R31 only
3262 operand iRegP_R31()
3263 %{
3264 constraint(ALLOC_IN_RC(r31_reg));
3265 match(RegP);
3266 match(iRegPNoSp);
3267 op_cost(0);
3268 format %{ %}
3269 interface(REG_INTER);
3270 %}
3271
3272 // Pointer Register Operands
3273 // Narrow Pointer Register
3274 operand iRegN()
3275 %{
3276 constraint(ALLOC_IN_RC(any_reg32));
3277 match(RegN);
3278 match(iRegNNoSp);
3279 op_cost(0);
3280 format %{ %}
3281 interface(REG_INTER);
3282 %}
3283
3284 // Integer 64 bit Register not Special
3285 operand iRegNNoSp()
3286 %{
3287 constraint(ALLOC_IN_RC(no_special_reg32));
3288 match(RegN);
3289 op_cost(0);
3290 format %{ %}
3291 interface(REG_INTER);
3292 %}
3293
3294 // Long 64 bit Register R10 only
3295 operand iRegL_R10()
3296 %{
3297 constraint(ALLOC_IN_RC(r10_reg));
3298 match(RegL);
3299 match(iRegLNoSp);
3300 op_cost(0);
3301 format %{ %}
3302 interface(REG_INTER);
3303 %}
3304
3305 // Float Register
3306 // Float register operands
3307 operand fRegF()
3308 %{
3309 constraint(ALLOC_IN_RC(float_reg));
3310 match(RegF);
3311
3312 op_cost(0);
3313 format %{ %}
3314 interface(REG_INTER);
3315 %}
3316
3317 // Double Register
3318 // Double register operands
3319 operand fRegD()
3320 %{
3321 constraint(ALLOC_IN_RC(double_reg));
3322 match(RegD);
3323
3324 op_cost(0);
3325 format %{ %}
3326 interface(REG_INTER);
3327 %}
3328
3329 // Generic vector class. This will be used for
3330 // all vector operands.
3331 operand vReg()
3332 %{
3333 constraint(ALLOC_IN_RC(vectora_reg));
3334 match(VecA);
3335 op_cost(0);
3336 format %{ %}
3337 interface(REG_INTER);
3338 %}
3339
3340 operand vReg_V1()
3341 %{
3342 constraint(ALLOC_IN_RC(v1_reg));
3343 match(VecA);
3344 match(vReg);
3345 op_cost(0);
3346 format %{ %}
3347 interface(REG_INTER);
3348 %}
3349
3350 operand vReg_V2()
3351 %{
3352 constraint(ALLOC_IN_RC(v2_reg));
3353 match(VecA);
3354 match(vReg);
3355 op_cost(0);
3356 format %{ %}
3357 interface(REG_INTER);
3358 %}
3359
3360 operand vReg_V3()
3361 %{
3362 constraint(ALLOC_IN_RC(v3_reg));
3363 match(VecA);
3364 match(vReg);
3365 op_cost(0);
3366 format %{ %}
3367 interface(REG_INTER);
3368 %}
3369
3370 operand vReg_V4()
3371 %{
3372 constraint(ALLOC_IN_RC(v4_reg));
3373 match(VecA);
3374 match(vReg);
3375 op_cost(0);
3376 format %{ %}
3377 interface(REG_INTER);
3378 %}
3379
3380 operand vReg_V5()
3381 %{
3382 constraint(ALLOC_IN_RC(v5_reg));
3383 match(VecA);
3384 match(vReg);
3385 op_cost(0);
3386 format %{ %}
3387 interface(REG_INTER);
3388 %}
3389
3390 operand vReg_V6()
3391 %{
3392 constraint(ALLOC_IN_RC(v6_reg));
3393 match(VecA);
3394 match(vReg);
3395 op_cost(0);
3396 format %{ %}
3397 interface(REG_INTER);
3398 %}
3399
3400 operand vReg_V7()
3401 %{
3402 constraint(ALLOC_IN_RC(v7_reg));
3403 match(VecA);
3404 match(vReg);
3405 op_cost(0);
3406 format %{ %}
3407 interface(REG_INTER);
3408 %}
3409
3410 operand vReg_V8()
3411 %{
3412 constraint(ALLOC_IN_RC(v8_reg));
3413 match(VecA);
3414 match(vReg);
3415 op_cost(0);
3416 format %{ %}
3417 interface(REG_INTER);
3418 %}
3419
3420 operand vReg_V9()
3421 %{
3422 constraint(ALLOC_IN_RC(v9_reg));
3423 match(VecA);
3424 match(vReg);
3425 op_cost(0);
3426 format %{ %}
3427 interface(REG_INTER);
3428 %}
3429
3430 operand vReg_V10()
3431 %{
3432 constraint(ALLOC_IN_RC(v10_reg));
3433 match(VecA);
3434 match(vReg);
3435 op_cost(0);
3436 format %{ %}
3437 interface(REG_INTER);
3438 %}
3439
3440 operand vReg_V11()
3441 %{
3442 constraint(ALLOC_IN_RC(v11_reg));
3443 match(VecA);
3444 match(vReg);
3445 op_cost(0);
3446 format %{ %}
3447 interface(REG_INTER);
3448 %}
3449
3450 operand vRegMask()
3451 %{
3452 constraint(ALLOC_IN_RC(vmask_reg));
3453 match(RegVectMask);
3454 match(vRegMask_V0);
3455 op_cost(0);
3456 format %{ %}
3457 interface(REG_INTER);
3458 %}
3459
3460 // The mask value used to control execution of a masked
3461 // vector instruction is always supplied by vector register v0.
3462 operand vRegMask_V0()
3463 %{
3464 constraint(ALLOC_IN_RC(vmask_reg_v0));
3465 match(RegVectMask);
3466 match(vRegMask);
3467 op_cost(0);
3468 format %{ %}
3469 interface(REG_INTER);
3470 %}
3471
3472 // Java Thread Register
3473 operand javaThread_RegP(iRegP reg)
3474 %{
3475 constraint(ALLOC_IN_RC(java_thread_reg)); // java_thread_reg
3476 match(reg);
3477 op_cost(0);
3478 format %{ %}
3479 interface(REG_INTER);
3480 %}
3481
3482 //----------Memory Operands----------------------------------------------------
3483 // RISCV has only base_plus_offset and literal address mode, so no need to use
3484 // index and scale. Here set index as 0xffffffff and scale as 0x0.
3485 operand indirect(iRegP reg)
3486 %{
3487 constraint(ALLOC_IN_RC(ptr_reg));
3488 match(reg);
3489 op_cost(0);
3490 format %{ "[$reg]" %}
3491 interface(MEMORY_INTER) %{
3492 base($reg);
3493 index(0xffffffff);
3494 scale(0x0);
3495 disp(0x0);
3496 %}
3497 %}
3498
3499 operand indOffI(iRegP reg, immIOffset off)
3500 %{
3501 constraint(ALLOC_IN_RC(ptr_reg));
3502 match(AddP reg off);
3503 op_cost(0);
3504 format %{ "[$reg, $off]" %}
3505 interface(MEMORY_INTER) %{
3506 base($reg);
3507 index(0xffffffff);
3508 scale(0x0);
3509 disp($off);
3510 %}
3511 %}
3512
3513 operand indOffL(iRegP reg, immLOffset off)
3514 %{
3515 constraint(ALLOC_IN_RC(ptr_reg));
3516 match(AddP reg off);
3517 op_cost(0);
3518 format %{ "[$reg, $off]" %}
3519 interface(MEMORY_INTER) %{
3520 base($reg);
3521 index(0xffffffff);
3522 scale(0x0);
3523 disp($off);
3524 %}
3525 %}
3526
3527 operand indirectN(iRegN reg)
3528 %{
3529 predicate(CompressedOops::shift() == 0);
3530 constraint(ALLOC_IN_RC(ptr_reg));
3531 match(DecodeN reg);
3532 op_cost(0);
3533 format %{ "[$reg]\t# narrow" %}
3534 interface(MEMORY_INTER) %{
3535 base($reg);
3536 index(0xffffffff);
3537 scale(0x0);
3538 disp(0x0);
3539 %}
3540 %}
3541
3542 operand indOffIN(iRegN reg, immIOffset off)
3543 %{
3544 predicate(CompressedOops::shift() == 0);
3545 constraint(ALLOC_IN_RC(ptr_reg));
3546 match(AddP (DecodeN reg) off);
3547 op_cost(0);
3548 format %{ "[$reg, $off]\t# narrow" %}
3549 interface(MEMORY_INTER) %{
3550 base($reg);
3551 index(0xffffffff);
3552 scale(0x0);
3553 disp($off);
3554 %}
3555 %}
3556
3557 operand indOffLN(iRegN reg, immLOffset off)
3558 %{
3559 predicate(CompressedOops::shift() == 0);
3560 constraint(ALLOC_IN_RC(ptr_reg));
3561 match(AddP (DecodeN reg) off);
3562 op_cost(0);
3563 format %{ "[$reg, $off]\t# narrow" %}
3564 interface(MEMORY_INTER) %{
3565 base($reg);
3566 index(0xffffffff);
3567 scale(0x0);
3568 disp($off);
3569 %}
3570 %}
3571
3572 //----------Special Memory Operands--------------------------------------------
3573 // Stack Slot Operand - This operand is used for loading and storing temporary
3574 // values on the stack where a match requires a value to
3575 // flow through memory.
3576 operand stackSlotI(sRegI reg)
3577 %{
3578 constraint(ALLOC_IN_RC(stack_slots));
3579 // No match rule because this operand is only generated in matching
3580 // match(RegI);
3581 format %{ "[$reg]" %}
3582 interface(MEMORY_INTER) %{
3583 base(0x02); // RSP
3584 index(0xffffffff); // No Index
3585 scale(0x0); // No Scale
3586 disp($reg); // Stack Offset
3587 %}
3588 %}
3589
3590 operand stackSlotF(sRegF reg)
3591 %{
3592 constraint(ALLOC_IN_RC(stack_slots));
3593 // No match rule because this operand is only generated in matching
3594 // match(RegF);
3595 format %{ "[$reg]" %}
3596 interface(MEMORY_INTER) %{
3597 base(0x02); // RSP
3598 index(0xffffffff); // No Index
3599 scale(0x0); // No Scale
3600 disp($reg); // Stack Offset
3601 %}
3602 %}
3603
3604 operand stackSlotD(sRegD reg)
3605 %{
3606 constraint(ALLOC_IN_RC(stack_slots));
3607 // No match rule because this operand is only generated in matching
3608 // match(RegD);
3609 format %{ "[$reg]" %}
3610 interface(MEMORY_INTER) %{
3611 base(0x02); // RSP
3612 index(0xffffffff); // No Index
3613 scale(0x0); // No Scale
3614 disp($reg); // Stack Offset
3615 %}
3616 %}
3617
3618 operand stackSlotL(sRegL reg)
3619 %{
3620 constraint(ALLOC_IN_RC(stack_slots));
3621 // No match rule because this operand is only generated in matching
3622 // match(RegL);
3623 format %{ "[$reg]" %}
3624 interface(MEMORY_INTER) %{
3625 base(0x02); // RSP
3626 index(0xffffffff); // No Index
3627 scale(0x0); // No Scale
3628 disp($reg); // Stack Offset
3629 %}
3630 %}
3631
3632 // Special operand allowing long args to int ops to be truncated for free
3633
3634 operand iRegL2I(iRegL reg) %{
3635
3636 op_cost(0);
3637
3638 match(ConvL2I reg);
3639
3640 format %{ "l2i($reg)" %}
3641
3642 interface(REG_INTER)
3643 %}
3644
3645
3646 // Comparison Operands
3647 // NOTE: Label is a predefined operand which should not be redefined in
3648 // the AD file. It is generically handled within the ADLC.
3649
3650 //----------Conditional Branch Operands----------------------------------------
3651 // Comparison Op - This is the operation of the comparison, and is limited to
3652 // the following set of codes:
3653 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
3654 //
3655 // Other attributes of the comparison, such as unsignedness, are specified
3656 // by the comparison instruction that sets a condition code flags register.
3657 // That result is represented by a flags operand whose subtype is appropriate
3658 // to the unsignedness (etc.) of the comparison.
3659 //
3660 // Later, the instruction which matches both the Comparison Op (a Bool) and
3661 // the flags (produced by the Cmp) specifies the coding of the comparison op
3662 // by matching a specific subtype of Bool operand below, such as cmpOpU.
3663
3664
3665 // used for signed integral comparisons and fp comparisons
3666 operand cmpOp()
3667 %{
3668 match(Bool);
3669
3670 format %{ "" %}
3671
3672 // the values in interface derives from struct BoolTest::mask
3673 interface(COND_INTER) %{
3674 equal(0x0, "eq");
3675 greater(0x1, "gt");
3676 overflow(0x2, "overflow");
3677 less(0x3, "lt");
3678 not_equal(0x4, "ne");
3679 less_equal(0x5, "le");
3680 no_overflow(0x6, "no_overflow");
3681 greater_equal(0x7, "ge");
3682 %}
3683 %}
3684
3685 // used for unsigned integral comparisons
3686 operand cmpOpU()
3687 %{
3688 match(Bool);
3689
3690 format %{ "" %}
3691 // the values in interface derives from struct BoolTest::mask
3692 interface(COND_INTER) %{
3693 equal(0x0, "eq");
3694 greater(0x1, "gtu");
3695 overflow(0x2, "overflow");
3696 less(0x3, "ltu");
3697 not_equal(0x4, "ne");
3698 less_equal(0x5, "leu");
3699 no_overflow(0x6, "no_overflow");
3700 greater_equal(0x7, "geu");
3701 %}
3702 %}
3703
3704 // used for certain integral comparisons which can be
3705 // converted to bxx instructions
3706 operand cmpOpEqNe()
3707 %{
3708 match(Bool);
3709 op_cost(0);
3710 predicate(n->as_Bool()->_test._test == BoolTest::ne ||
3711 n->as_Bool()->_test._test == BoolTest::eq);
3712
3713 format %{ "" %}
3714 interface(COND_INTER) %{
3715 equal(0x0, "eq");
3716 greater(0x1, "gt");
3717 overflow(0x2, "overflow");
3718 less(0x3, "lt");
3719 not_equal(0x4, "ne");
3720 less_equal(0x5, "le");
3721 no_overflow(0x6, "no_overflow");
3722 greater_equal(0x7, "ge");
3723 %}
3724 %}
3725
3726 operand cmpOpULtGe()
3727 %{
3728 match(Bool);
3729 op_cost(0);
3730 predicate(n->as_Bool()->_test._test == BoolTest::lt ||
3731 n->as_Bool()->_test._test == BoolTest::ge);
3732
3733 format %{ "" %}
3734 interface(COND_INTER) %{
3735 equal(0x0, "eq");
3736 greater(0x1, "gtu");
3737 overflow(0x2, "overflow");
3738 less(0x3, "ltu");
3739 not_equal(0x4, "ne");
3740 less_equal(0x5, "leu");
3741 no_overflow(0x6, "no_overflow");
3742 greater_equal(0x7, "geu");
3743 %}
3744 %}
3745
3746 operand cmpOpUEqNeLeGt()
3747 %{
3748 match(Bool);
3749 op_cost(0);
3750 predicate(n->as_Bool()->_test._test == BoolTest::ne ||
3751 n->as_Bool()->_test._test == BoolTest::eq ||
3752 n->as_Bool()->_test._test == BoolTest::le ||
3753 n->as_Bool()->_test._test == BoolTest::gt);
3754
3755 format %{ "" %}
3756 interface(COND_INTER) %{
3757 equal(0x0, "eq");
3758 greater(0x1, "gtu");
3759 overflow(0x2, "overflow");
3760 less(0x3, "ltu");
3761 not_equal(0x4, "ne");
3762 less_equal(0x5, "leu");
3763 no_overflow(0x6, "no_overflow");
3764 greater_equal(0x7, "geu");
3765 %}
3766 %}
3767
3768
3769 // Flags register, used as output of compare logic
3770 operand rFlagsReg()
3771 %{
3772 constraint(ALLOC_IN_RC(reg_flags));
3773 match(RegFlags);
3774
3775 op_cost(0);
3776 format %{ "RFLAGS" %}
3777 interface(REG_INTER);
3778 %}
3779
3780 // Special Registers
3781
3782 // Method Register
3783 operand inline_cache_RegP(iRegP reg)
3784 %{
3785 constraint(ALLOC_IN_RC(method_reg)); // inline_cache_reg
3786 match(reg);
3787 match(iRegPNoSp);
3788 op_cost(0);
3789 format %{ %}
3790 interface(REG_INTER);
3791 %}
3792
3793 //----------OPERAND CLASSES----------------------------------------------------
3794 // Operand Classes are groups of operands that are used as to simplify
3795 // instruction definitions by not requiring the AD writer to specify
3796 // separate instructions for every form of operand when the
3797 // instruction accepts multiple operand types with the same basic
3798 // encoding and format. The classic case of this is memory operands.
3799
3800 // memory is used to define read/write location for load/store
3801 // instruction defs. we can turn a memory op into an Address
3802
3803 opclass memory(indirect, indOffI, indOffL, indirectN, indOffIN, indOffLN);
3804
3805 // iRegIorL2I is used for src inputs in rules for 32 bit int (I)
3806 // operations. it allows the src to be either an iRegI or a (ConvL2I
3807 // iRegL). in the latter case the l2i normally planted for a ConvL2I
3808 // can be elided because the 32-bit instruction will just employ the
3809 // lower 32 bits anyway.
3810 //
3811 // n.b. this does not elide all L2I conversions. if the truncated
3812 // value is consumed by more than one operation then the ConvL2I
3813 // cannot be bundled into the consuming nodes so an l2i gets planted
3814 // (actually an addiw $dst, $src, 0) and the downstream instructions
3815 // consume the result of the L2I as an iRegI input. That's a shame since
3816 // the addiw is actually redundant but its not too costly.
3817
3818 opclass iRegIorL2I(iRegI, iRegL2I);
3819 opclass iRegIorL(iRegI, iRegL);
3820 opclass iRegNorP(iRegN, iRegP);
3821 opclass iRegILNP(iRegI, iRegL, iRegN, iRegP);
3822 opclass iRegILNPNoSp(iRegINoSp, iRegLNoSp, iRegNNoSp, iRegPNoSp);
3823 opclass immIorL(immI, immL);
3824
3825 //----------PIPELINE-----------------------------------------------------------
3826 // Rules which define the behavior of the target architectures pipeline.
3827
3828 // For specific pipelines, e.g. generic RISC-V, define the stages of that pipeline
3829 //pipe_desc(ID, EX, MEM, WR);
3830 #define ID S0
3831 #define EX S1
3832 #define MEM S2
3833 #define WR S3
3834
3835 // Integer ALU reg operation
3836 pipeline %{
3837
3838 attributes %{
3839 // RISC-V instructions are of length 2 or 4 bytes.
3840 variable_size_instructions;
3841 instruction_unit_size = 2;
3842
3843 // Up to 4 instructions per bundle
3844 max_instructions_per_bundle = 4;
3845
3846 // The RISC-V processor fetches 64 bytes...
3847 instruction_fetch_unit_size = 64;
3848
3849 // ...in one line.
3850 instruction_fetch_units = 1;
3851 %}
3852
3853 // We don't use an actual pipeline model so don't care about resources
3854 // or description. we do use pipeline classes to introduce fixed
3855 // latencies
3856
3857 //----------RESOURCES----------------------------------------------------------
3858 // Resources are the functional units available to the machine
3859
3860 // Generic RISC-V pipeline
3861 // 1 decoder
3862 // 1 instruction decoded per cycle
3863 // 1 load/store ops per cycle, 1 branch, 1 FPU
3864 // 1 mul, 1 div
3865
3866 resources ( DECODE,
3867 ALU,
3868 MUL,
3869 DIV,
3870 BRANCH,
3871 LDST,
3872 FPU);
3873
3874 //----------PIPELINE DESCRIPTION-----------------------------------------------
3875 // Pipeline Description specifies the stages in the machine's pipeline
3876
3877 // Define the pipeline as a generic 6 stage pipeline
3878 pipe_desc(S0, S1, S2, S3, S4, S5);
3879
3880 //----------PIPELINE CLASSES---------------------------------------------------
3881 // Pipeline Classes describe the stages in which input and output are
3882 // referenced by the hardware pipeline.
3883
3884 pipe_class fp_dop_reg_reg_s(fRegF dst, fRegF src1, fRegF src2)
3885 %{
3886 single_instruction;
3887 src1 : S1(read);
3888 src2 : S2(read);
3889 dst : S5(write);
3890 DECODE : ID;
3891 FPU : S5;
3892 %}
3893
3894 pipe_class fp_dop_reg_reg_d(fRegD dst, fRegD src1, fRegD src2)
3895 %{
3896 src1 : S1(read);
3897 src2 : S2(read);
3898 dst : S5(write);
3899 DECODE : ID;
3900 FPU : S5;
3901 %}
3902
3903 pipe_class fp_uop_s(fRegF dst, fRegF src)
3904 %{
3905 single_instruction;
3906 src : S1(read);
3907 dst : S5(write);
3908 DECODE : ID;
3909 FPU : S5;
3910 %}
3911
3912 pipe_class fp_uop_d(fRegD dst, fRegD src)
3913 %{
3914 single_instruction;
3915 src : S1(read);
3916 dst : S5(write);
3917 DECODE : ID;
3918 FPU : S5;
3919 %}
3920
3921 pipe_class fp_d2f(fRegF dst, fRegD src)
3922 %{
3923 single_instruction;
3924 src : S1(read);
3925 dst : S5(write);
3926 DECODE : ID;
3927 FPU : S5;
3928 %}
3929
3930 pipe_class fp_f2d(fRegD dst, fRegF src)
3931 %{
3932 single_instruction;
3933 src : S1(read);
3934 dst : S5(write);
3935 DECODE : ID;
3936 FPU : S5;
3937 %}
3938
3939 pipe_class fp_f2i(iRegINoSp dst, fRegF src)
3940 %{
3941 single_instruction;
3942 src : S1(read);
3943 dst : S5(write);
3944 DECODE : ID;
3945 FPU : S5;
3946 %}
3947
3948 pipe_class fp_f2l(iRegLNoSp dst, fRegF src)
3949 %{
3950 single_instruction;
3951 src : S1(read);
3952 dst : S5(write);
3953 DECODE : ID;
3954 FPU : S5;
3955 %}
3956
3957 pipe_class fp_i2f(fRegF dst, iRegIorL2I src)
3958 %{
3959 single_instruction;
3960 src : S1(read);
3961 dst : S5(write);
3962 DECODE : ID;
3963 FPU : S5;
3964 %}
3965
3966 pipe_class fp_l2f(fRegF dst, iRegL src)
3967 %{
3968 single_instruction;
3969 src : S1(read);
3970 dst : S5(write);
3971 DECODE : ID;
3972 FPU : S5;
3973 %}
3974
3975 pipe_class fp_d2i(iRegINoSp dst, fRegD src)
3976 %{
3977 single_instruction;
3978 src : S1(read);
3979 dst : S5(write);
3980 DECODE : ID;
3981 FPU : S5;
3982 %}
3983
3984 pipe_class fp_d2l(iRegLNoSp dst, fRegD src)
3985 %{
3986 single_instruction;
3987 src : S1(read);
3988 dst : S5(write);
3989 DECODE : ID;
3990 FPU : S5;
3991 %}
3992
3993 pipe_class fp_i2d(fRegD dst, iRegIorL2I src)
3994 %{
3995 single_instruction;
3996 src : S1(read);
3997 dst : S5(write);
3998 DECODE : ID;
3999 FPU : S5;
4000 %}
4001
4002 pipe_class fp_l2d(fRegD dst, iRegIorL2I src)
4003 %{
4004 single_instruction;
4005 src : S1(read);
4006 dst : S5(write);
4007 DECODE : ID;
4008 FPU : S5;
4009 %}
4010
4011 pipe_class fp_div_s(fRegF dst, fRegF src1, fRegF src2)
4012 %{
4013 single_instruction;
4014 src1 : S1(read);
4015 src2 : S2(read);
4016 dst : S5(write);
4017 DECODE : ID;
4018 FPU : S5;
4019 %}
4020
4021 pipe_class fp_div_d(fRegD dst, fRegD src1, fRegD src2)
4022 %{
4023 single_instruction;
4024 src1 : S1(read);
4025 src2 : S2(read);
4026 dst : S5(write);
4027 DECODE : ID;
4028 FPU : S5;
4029 %}
4030
4031 pipe_class fp_sqrt_s(fRegF dst, fRegF src)
4032 %{
4033 single_instruction;
4034 src : S1(read);
4035 dst : S5(write);
4036 DECODE : ID;
4037 FPU : S5;
4038 %}
4039
4040 pipe_class fp_sqrt_d(fRegD dst, fRegD src)
4041 %{
4042 single_instruction;
4043 src : S1(read);
4044 dst : S5(write);
4045 DECODE : ID;
4046 FPU : S5;
4047 %}
4048
4049 pipe_class fp_load_constant_s(fRegF dst)
4050 %{
4051 single_instruction;
4052 dst : S5(write);
4053 DECODE : ID;
4054 FPU : S5;
4055 %}
4056
4057 pipe_class fp_load_constant_d(fRegD dst)
4058 %{
4059 single_instruction;
4060 dst : S5(write);
4061 DECODE : ID;
4062 FPU : S5;
4063 %}
4064
4065 pipe_class fp_load_mem_s(fRegF dst, memory mem)
4066 %{
4067 single_instruction;
4068 mem : S1(read);
4069 dst : S5(write);
4070 DECODE : ID;
4071 LDST : MEM;
4072 %}
4073
4074 pipe_class fp_load_mem_d(fRegD dst, memory mem)
4075 %{
4076 single_instruction;
4077 mem : S1(read);
4078 dst : S5(write);
4079 DECODE : ID;
4080 LDST : MEM;
4081 %}
4082
4083 pipe_class fp_store_reg_s(fRegF src, memory mem)
4084 %{
4085 single_instruction;
4086 src : S1(read);
4087 mem : S5(write);
4088 DECODE : ID;
4089 LDST : MEM;
4090 %}
4091
4092 pipe_class fp_store_reg_d(fRegD src, memory mem)
4093 %{
4094 single_instruction;
4095 src : S1(read);
4096 mem : S5(write);
4097 DECODE : ID;
4098 LDST : MEM;
4099 %}
4100
4101 //------- Integer ALU operations --------------------------
4102
4103 // Integer ALU reg-reg operation
4104 // Operands needs in ID, result generated in EX
4105 // E.g. ADD Rd, Rs1, Rs2
4106 pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2)
4107 %{
4108 single_instruction;
4109 dst : EX(write);
4110 src1 : ID(read);
4111 src2 : ID(read);
4112 DECODE : ID;
4113 ALU : EX;
4114 %}
4115
4116 // Integer ALU reg operation with constant shift
4117 // E.g. SLLI Rd, Rs1, #shift
4118 pipe_class ialu_reg_shift(iRegI dst, iRegI src1)
4119 %{
4120 single_instruction;
4121 dst : EX(write);
4122 src1 : ID(read);
4123 DECODE : ID;
4124 ALU : EX;
4125 %}
4126
4127 // Integer ALU reg-reg operation with variable shift
4128 // both operands must be available in ID
4129 // E.g. SLL Rd, Rs1, Rs2
4130 pipe_class ialu_reg_reg_vshift(iRegI dst, iRegI src1, iRegI src2)
4131 %{
4132 single_instruction;
4133 dst : EX(write);
4134 src1 : ID(read);
4135 src2 : ID(read);
4136 DECODE : ID;
4137 ALU : EX;
4138 %}
4139
4140 // Integer ALU reg operation
4141 // E.g. NEG Rd, Rs2
4142 pipe_class ialu_reg(iRegI dst, iRegI src)
4143 %{
4144 single_instruction;
4145 dst : EX(write);
4146 src : ID(read);
4147 DECODE : ID;
4148 ALU : EX;
4149 %}
4150
4151 // Integer ALU reg immediate operation
4152 // E.g. ADDI Rd, Rs1, #imm
4153 pipe_class ialu_reg_imm(iRegI dst, iRegI src1)
4154 %{
4155 single_instruction;
4156 dst : EX(write);
4157 src1 : ID(read);
4158 DECODE : ID;
4159 ALU : EX;
4160 %}
4161
4162 // Integer ALU immediate operation (no source operands)
4163 // E.g. LI Rd, #imm
4164 pipe_class ialu_imm(iRegI dst)
4165 %{
4166 single_instruction;
4167 dst : EX(write);
4168 DECODE : ID;
4169 ALU : EX;
4170 %}
4171
4172 //------- Multiply pipeline operations --------------------
4173
4174 // Multiply reg-reg
4175 // E.g. MULW Rd, Rs1, Rs2
4176 pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2)
4177 %{
4178 single_instruction;
4179 dst : WR(write);
4180 src1 : ID(read);
4181 src2 : ID(read);
4182 DECODE : ID;
4183 MUL : WR;
4184 %}
4185
4186 // E.g. MUL RD, Rs1, Rs2
4187 pipe_class lmul_reg_reg(iRegL dst, iRegL src1, iRegL src2)
4188 %{
4189 single_instruction;
4190 fixed_latency(3); // Maximum latency for 64 bit mul
4191 dst : WR(write);
4192 src1 : ID(read);
4193 src2 : ID(read);
4194 DECODE : ID;
4195 MUL : WR;
4196 %}
4197
4198 //------- Divide pipeline operations --------------------
4199
4200 // E.g. DIVW Rd, Rs1, Rs2
4201 pipe_class idiv_reg_reg(iRegI dst, iRegI src1, iRegI src2)
4202 %{
4203 single_instruction;
4204 fixed_latency(8); // Maximum latency for 32 bit divide
4205 dst : WR(write);
4206 src1 : ID(read);
4207 src2 : ID(read);
4208 DECODE : ID;
4209 DIV : WR;
4210 %}
4211
4212 // E.g. DIV RD, Rs1, Rs2
4213 pipe_class ldiv_reg_reg(iRegL dst, iRegL src1, iRegL src2)
4214 %{
4215 single_instruction;
4216 fixed_latency(16); // Maximum latency for 64 bit divide
4217 dst : WR(write);
4218 src1 : ID(read);
4219 src2 : ID(read);
4220 DECODE : ID;
4221 DIV : WR;
4222 %}
4223
4224 //------- Load pipeline operations ------------------------
4225
4226 // Load - prefetch
4227 // Eg. PREFETCH_W mem
4228 pipe_class iload_prefetch(memory mem)
4229 %{
4230 single_instruction;
4231 mem : ID(read);
4232 DECODE : ID;
4233 LDST : MEM;
4234 %}
4235
4236 // Load - reg, mem
4237 // E.g. LA Rd, mem
4238 pipe_class iload_reg_mem(iRegI dst, memory mem)
4239 %{
4240 single_instruction;
4241 dst : WR(write);
4242 mem : ID(read);
4243 DECODE : ID;
4244 LDST : MEM;
4245 %}
4246
4247 // Load - reg, reg
4248 // E.g. LD Rd, Rs
4249 pipe_class iload_reg_reg(iRegI dst, iRegI src)
4250 %{
4251 single_instruction;
4252 dst : WR(write);
4253 src : ID(read);
4254 DECODE : ID;
4255 LDST : MEM;
4256 %}
4257
4258 //------- Store pipeline operations -----------------------
4259
4260 // Store - zr, mem
4261 // E.g. SD zr, mem
4262 pipe_class istore_mem(memory mem)
4263 %{
4264 single_instruction;
4265 mem : ID(read);
4266 DECODE : ID;
4267 LDST : MEM;
4268 %}
4269
4270 // Store - reg, mem
4271 // E.g. SD Rs, mem
4272 pipe_class istore_reg_mem(iRegI src, memory mem)
4273 %{
4274 single_instruction;
4275 mem : ID(read);
4276 src : EX(read);
4277 DECODE : ID;
4278 LDST : MEM;
4279 %}
4280
4281 // Store - reg, reg
4282 // E.g. SD Rs2, Rs1
4283 pipe_class istore_reg_reg(iRegI dst, iRegI src)
4284 %{
4285 single_instruction;
4286 dst : ID(read);
4287 src : EX(read);
4288 DECODE : ID;
4289 LDST : MEM;
4290 %}
4291
4292 //------- Control transfer pipeline operations ------------
4293
4294 // Branch
4295 pipe_class pipe_branch()
4296 %{
4297 single_instruction;
4298 DECODE : ID;
4299 BRANCH : EX;
4300 %}
4301
4302 // Branch
4303 pipe_class pipe_branch_reg(iRegI src)
4304 %{
4305 single_instruction;
4306 src : ID(read);
4307 DECODE : ID;
4308 BRANCH : EX;
4309 %}
4310
4311 // Compare & Branch
4312 // E.g. BEQ Rs1, Rs2, L
4313 pipe_class pipe_cmp_branch(iRegI src1, iRegI src2)
4314 %{
4315 single_instruction;
4316 src1 : ID(read);
4317 src2 : ID(read);
4318 DECODE : ID;
4319 BRANCH : EX;
4320 %}
4321
4322 // E.g. BEQZ Rs, L
4323 pipe_class pipe_cmpz_branch(iRegI src)
4324 %{
4325 single_instruction;
4326 src : ID(read);
4327 DECODE : ID;
4328 BRANCH : EX;
4329 %}
4330
4331 //------- Synchronisation operations ----------------------
4332 // Any operation requiring serialization
4333 // E.g. FENCE/Atomic Ops/Load Acquire/Store Release
4334 pipe_class pipe_serial()
4335 %{
4336 single_instruction;
4337 force_serialization;
4338 fixed_latency(16);
4339 DECODE : ID;
4340 LDST : MEM;
4341 %}
4342
4343 pipe_class pipe_slow()
4344 %{
4345 instruction_count(10);
4346 multiple_bundles;
4347 force_serialization;
4348 fixed_latency(16);
4349 DECODE : ID;
4350 LDST : MEM;
4351 %}
4352
4353 // The real do-nothing guy
4354 pipe_class real_empty()
4355 %{
4356 instruction_count(0);
4357 %}
4358
4359 // Empty pipeline class
4360 pipe_class pipe_class_empty()
4361 %{
4362 single_instruction;
4363 fixed_latency(0);
4364 %}
4365
4366 // Default pipeline class.
4367 pipe_class pipe_class_default()
4368 %{
4369 single_instruction;
4370 fixed_latency(2);
4371 %}
4372
4373 // Pipeline class for compares.
4374 pipe_class pipe_class_compare()
4375 %{
4376 single_instruction;
4377 fixed_latency(16);
4378 %}
4379
4380 // Pipeline class for memory operations.
4381 pipe_class pipe_class_memory()
4382 %{
4383 single_instruction;
4384 fixed_latency(16);
4385 %}
4386
4387 // Pipeline class for call.
4388 pipe_class pipe_class_call()
4389 %{
4390 single_instruction;
4391 fixed_latency(100);
4392 %}
4393
4394 // Define the class for the Nop node.
4395 define %{
4396 MachNop = pipe_class_empty;
4397 %}
4398 %}
4399 //----------INSTRUCTIONS-------------------------------------------------------
4400 //
4401 // match -- States which machine-independent subtree may be replaced
4402 // by this instruction.
4403 // ins_cost -- The estimated cost of this instruction is used by instruction
4404 // selection to identify a minimum cost tree of machine
4405 // instructions that matches a tree of machine-independent
4406 // instructions.
4407 // format -- A string providing the disassembly for this instruction.
4408 // The value of an instruction's operand may be inserted
4409 // by referring to it with a '$' prefix.
4410 // opcode -- Three instruction opcodes may be provided. These are referred
4411 // to within an encode class as $primary, $secondary, and $tertiary
4412 // rrspectively. The primary opcode is commonly used to
4413 // indicate the type of machine instruction, while secondary
4414 // and tertiary are often used for prefix options or addressing
4415 // modes.
4416 // ins_encode -- A list of encode classes with parameters. The encode class
4417 // name must have been defined in an 'enc_class' specification
4418 // in the encode section of the architecture description.
4419
4420 // ============================================================================
4421 // Memory (Load/Store) Instructions
4422
4423 // Load Instructions
4424
4425 // Load Byte (8 bit signed)
4426 instruct loadB(iRegINoSp dst, memory mem)
4427 %{
4428 match(Set dst (LoadB mem));
4429
4430 ins_cost(LOAD_COST);
4431 format %{ "lb $dst, $mem\t# byte, #@loadB" %}
4432
4433 ins_encode %{
4434 __ lb(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4435 %}
4436
4437 ins_pipe(iload_reg_mem);
4438 %}
4439
4440 // Load Byte (8 bit signed) into long
4441 instruct loadB2L(iRegLNoSp dst, memory mem)
4442 %{
4443 match(Set dst (ConvI2L (LoadB mem)));
4444
4445 ins_cost(LOAD_COST);
4446 format %{ "lb $dst, $mem\t# byte, #@loadB2L" %}
4447
4448 ins_encode %{
4449 __ lb(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4450 %}
4451
4452 ins_pipe(iload_reg_mem);
4453 %}
4454
4455 // Load Byte (8 bit unsigned)
4456 instruct loadUB(iRegINoSp dst, memory mem)
4457 %{
4458 match(Set dst (LoadUB mem));
4459
4460 ins_cost(LOAD_COST);
4461 format %{ "lbu $dst, $mem\t# byte, #@loadUB" %}
4462
4463 ins_encode %{
4464 __ lbu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4465 %}
4466
4467 ins_pipe(iload_reg_mem);
4468 %}
4469
4470 // Load Byte (8 bit unsigned) into long
4471 instruct loadUB2L(iRegLNoSp dst, memory mem)
4472 %{
4473 match(Set dst (ConvI2L (LoadUB mem)));
4474
4475 ins_cost(LOAD_COST);
4476 format %{ "lbu $dst, $mem\t# byte, #@loadUB2L" %}
4477
4478 ins_encode %{
4479 __ lbu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4480 %}
4481
4482 ins_pipe(iload_reg_mem);
4483 %}
4484
4485 // Load Short (16 bit signed)
4486 instruct loadS(iRegINoSp dst, memory mem)
4487 %{
4488 match(Set dst (LoadS mem));
4489
4490 ins_cost(LOAD_COST);
4491 format %{ "lh $dst, $mem\t# short, #@loadS" %}
4492
4493 ins_encode %{
4494 __ lh(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4495 %}
4496
4497 ins_pipe(iload_reg_mem);
4498 %}
4499
4500 // Load Short (16 bit signed) into long
4501 instruct loadS2L(iRegLNoSp dst, memory mem)
4502 %{
4503 match(Set dst (ConvI2L (LoadS mem)));
4504
4505 ins_cost(LOAD_COST);
4506 format %{ "lh $dst, $mem\t# short, #@loadS2L" %}
4507
4508 ins_encode %{
4509 __ lh(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4510 %}
4511
4512 ins_pipe(iload_reg_mem);
4513 %}
4514
4515 // Load Char (16 bit unsigned)
4516 instruct loadUS(iRegINoSp dst, memory mem)
4517 %{
4518 match(Set dst (LoadUS mem));
4519
4520 ins_cost(LOAD_COST);
4521 format %{ "lhu $dst, $mem\t# short, #@loadUS" %}
4522
4523 ins_encode %{
4524 __ lhu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4525 %}
4526
4527 ins_pipe(iload_reg_mem);
4528 %}
4529
4530 // Load Short/Char (16 bit unsigned) into long
4531 instruct loadUS2L(iRegLNoSp dst, memory mem)
4532 %{
4533 match(Set dst (ConvI2L (LoadUS mem)));
4534
4535 ins_cost(LOAD_COST);
4536 format %{ "lhu $dst, $mem\t# short, #@loadUS2L" %}
4537
4538 ins_encode %{
4539 __ lhu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4540 %}
4541
4542 ins_pipe(iload_reg_mem);
4543 %}
4544
4545 // Load Integer (32 bit signed)
4546 instruct loadI(iRegINoSp dst, memory mem)
4547 %{
4548 match(Set dst (LoadI mem));
4549
4550 ins_cost(LOAD_COST);
4551 format %{ "lw $dst, $mem\t# int, #@loadI" %}
4552
4553 ins_encode %{
4554 __ lw(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4555 %}
4556
4557 ins_pipe(iload_reg_mem);
4558 %}
4559
4560 // Load Integer (32 bit signed) into long
4561 instruct loadI2L(iRegLNoSp dst, memory mem)
4562 %{
4563 match(Set dst (ConvI2L (LoadI mem)));
4564
4565 ins_cost(LOAD_COST);
4566 format %{ "lw $dst, $mem\t# int, #@loadI2L" %}
4567
4568 ins_encode %{
4569 __ lw(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4570 %}
4571
4572 ins_pipe(iload_reg_mem);
4573 %}
4574
4575 // Load Integer (32 bit unsigned) into long
4576 instruct loadUI2L(iRegLNoSp dst, memory mem, immL_32bits mask)
4577 %{
4578 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
4579
4580 ins_cost(LOAD_COST);
4581 format %{ "lwu $dst, $mem\t# int, #@loadUI2L" %}
4582
4583 ins_encode %{
4584 __ lwu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4585 %}
4586
4587 ins_pipe(iload_reg_mem);
4588 %}
4589
4590 // Load Long (64 bit signed)
4591 instruct loadL(iRegLNoSp dst, memory mem)
4592 %{
4593 match(Set dst (LoadL mem));
4594
4595 ins_cost(LOAD_COST);
4596 format %{ "ld $dst, $mem\t# int, #@loadL" %}
4597
4598 ins_encode %{
4599 __ ld(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4600 %}
4601
4602 ins_pipe(iload_reg_mem);
4603 %}
4604
4605 // Load Range
4606 instruct loadRange(iRegINoSp dst, memory mem)
4607 %{
4608 match(Set dst (LoadRange mem));
4609
4610 ins_cost(LOAD_COST);
4611 format %{ "lwu $dst, $mem\t# range, #@loadRange" %}
4612
4613 ins_encode %{
4614 __ lwu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4615 %}
4616
4617 ins_pipe(iload_reg_mem);
4618 %}
4619
4620 // Load Pointer
4621 instruct loadP(iRegPNoSp dst, memory mem)
4622 %{
4623 match(Set dst (LoadP mem));
4624 predicate(n->as_Load()->barrier_data() == 0);
4625
4626 ins_cost(LOAD_COST);
4627 format %{ "ld $dst, $mem\t# ptr, #@loadP" %}
4628
4629 ins_encode %{
4630 __ ld(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4631 %}
4632
4633 ins_pipe(iload_reg_mem);
4634 %}
4635
4636 // Load Compressed Pointer
4637 instruct loadN(iRegNNoSp dst, memory mem)
4638 %{
4639 predicate(n->as_Load()->barrier_data() == 0);
4640 match(Set dst (LoadN mem));
4641
4642 ins_cost(LOAD_COST);
4643 format %{ "lwu $dst, $mem\t# compressed ptr, #@loadN" %}
4644
4645 ins_encode %{
4646 __ lwu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4647 %}
4648
4649 ins_pipe(iload_reg_mem);
4650 %}
4651
4652 // Load Klass Pointer
4653 instruct loadKlass(iRegPNoSp dst, memory mem)
4654 %{
4655 match(Set dst (LoadKlass mem));
4656
4657 ins_cost(LOAD_COST);
4658 format %{ "ld $dst, $mem\t# class, #@loadKlass" %}
4659
4660 ins_encode %{
4661 __ ld(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4662 %}
4663
4664 ins_pipe(iload_reg_mem);
4665 %}
4666
4667 // Load Narrow Klass Pointer
4668 instruct loadNKlass(iRegNNoSp dst, memory mem)
4669 %{
4670 predicate(!UseCompactObjectHeaders);
4671 match(Set dst (LoadNKlass mem));
4672
4673 ins_cost(LOAD_COST);
4674 format %{ "lwu $dst, $mem\t# compressed class ptr, #@loadNKlass" %}
4675
4676 ins_encode %{
4677 __ lwu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4678 %}
4679
4680 ins_pipe(iload_reg_mem);
4681 %}
4682
4683 instruct loadNKlassCompactHeaders(iRegNNoSp dst, memory mem)
4684 %{
4685 predicate(UseCompactObjectHeaders);
4686 match(Set dst (LoadNKlass mem));
4687
4688 ins_cost(LOAD_COST);
4689 format %{
4690 "lwu $dst, $mem\t# compressed klass ptr, shifted\n\t"
4691 "srli $dst, $dst, markWord::klass_shift_at_offset"
4692 %}
4693
4694 ins_encode %{
4695 Unimplemented();
4696 // __ lwu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4697 // __ srli(as_Register($dst$$reg), as_Register($dst$$reg), (unsigned) markWord::klass_shift_at_offset);
4698 %}
4699
4700 ins_pipe(iload_reg_mem);
4701 %}
4702
4703 // Load Float
4704 instruct loadF(fRegF dst, memory mem)
4705 %{
4706 match(Set dst (LoadF mem));
4707
4708 ins_cost(LOAD_COST);
4709 format %{ "flw $dst, $mem\t# float, #@loadF" %}
4710
4711 ins_encode %{
4712 __ flw(as_FloatRegister($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4713 %}
4714
4715 ins_pipe(fp_load_mem_s);
4716 %}
4717
4718 // Load Double
4719 instruct loadD(fRegD dst, memory mem)
4720 %{
4721 match(Set dst (LoadD mem));
4722
4723 ins_cost(LOAD_COST);
4724 format %{ "fld $dst, $mem\t# double, #@loadD" %}
4725
4726 ins_encode %{
4727 __ fld(as_FloatRegister($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4728 %}
4729
4730 ins_pipe(fp_load_mem_d);
4731 %}
4732
4733 // Load Int Constant
4734 instruct loadConI(iRegINoSp dst, immI src)
4735 %{
4736 match(Set dst src);
4737
4738 ins_cost(ALU_COST);
4739 format %{ "mv $dst, $src\t# int, #@loadConI" %}
4740
4741 ins_encode(riscv_enc_mov_imm(dst, src));
4742
4743 ins_pipe(ialu_imm);
4744 %}
4745
4746 // Load Long Constant
4747 instruct loadConL(iRegLNoSp dst, immL src)
4748 %{
4749 match(Set dst src);
4750
4751 ins_cost(ALU_COST);
4752 format %{ "mv $dst, $src\t# long, #@loadConL" %}
4753
4754 ins_encode(riscv_enc_mov_imm(dst, src));
4755
4756 ins_pipe(ialu_imm);
4757 %}
4758
4759 // Load Pointer Constant
4760 instruct loadConP(iRegPNoSp dst, immP con)
4761 %{
4762 match(Set dst con);
4763
4764 ins_cost(ALU_COST);
4765 format %{ "mv $dst, $con\t# ptr, #@loadConP" %}
4766
4767 ins_encode(riscv_enc_mov_p(dst, con));
4768
4769 ins_pipe(ialu_imm);
4770 %}
4771
4772 // Load Null Pointer Constant
4773 instruct loadConP0(iRegPNoSp dst, immP0 con)
4774 %{
4775 match(Set dst con);
4776
4777 ins_cost(ALU_COST);
4778 format %{ "mv $dst, $con\t# null pointer, #@loadConP0" %}
4779
4780 ins_encode(riscv_enc_mov_zero(dst));
4781
4782 ins_pipe(ialu_imm);
4783 %}
4784
4785 // Load Pointer Constant One
4786 instruct loadConP1(iRegPNoSp dst, immP_1 con)
4787 %{
4788 match(Set dst con);
4789
4790 ins_cost(ALU_COST);
4791 format %{ "mv $dst, $con\t# load ptr constant one, #@loadConP1" %}
4792
4793 ins_encode(riscv_enc_mov_p1(dst));
4794
4795 ins_pipe(ialu_imm);
4796 %}
4797
4798 // Load Narrow Pointer Constant
4799 instruct loadConN(iRegNNoSp dst, immN con)
4800 %{
4801 match(Set dst con);
4802
4803 ins_cost(ALU_COST * 4);
4804 format %{ "mv $dst, $con\t# compressed ptr, #@loadConN" %}
4805
4806 ins_encode(riscv_enc_mov_n(dst, con));
4807
4808 ins_pipe(ialu_imm);
4809 %}
4810
4811 // Load Narrow Null Pointer Constant
4812 instruct loadConN0(iRegNNoSp dst, immN0 con)
4813 %{
4814 match(Set dst con);
4815
4816 ins_cost(ALU_COST);
4817 format %{ "mv $dst, $con\t# compressed null pointer, #@loadConN0" %}
4818
4819 ins_encode(riscv_enc_mov_zero(dst));
4820
4821 ins_pipe(ialu_imm);
4822 %}
4823
4824 // Load Narrow Klass Constant
4825 instruct loadConNKlass(iRegNNoSp dst, immNKlass con)
4826 %{
4827 match(Set dst con);
4828
4829 ins_cost(ALU_COST * 6);
4830 format %{ "mv $dst, $con\t# compressed klass ptr, #@loadConNKlass" %}
4831
4832 ins_encode(riscv_enc_mov_nk(dst, con));
4833
4834 ins_pipe(ialu_imm);
4835 %}
4836
4837 // Load Half Float Constant
4838 instruct loadConH(fRegF dst, immH con) %{
4839 match(Set dst con);
4840
4841 ins_cost(LOAD_COST);
4842 format %{
4843 "flh $dst, [$constantaddress]\t# load from constant table: float=$con, #@loadConH"
4844 %}
4845
4846 ins_encode %{
4847 assert(UseZfh || UseZfhmin, "must");
4848 if (MacroAssembler::can_hf_imm_load($con$$constant)) {
4849 __ fli_h(as_FloatRegister($dst$$reg), $con$$constant);
4850 } else {
4851 __ flh(as_FloatRegister($dst$$reg), $constantaddress($con));
4852 }
4853 %}
4854
4855 ins_pipe(fp_load_constant_s);
4856 %}
4857
4858 instruct loadConH0(fRegF dst, immH0 con) %{
4859 match(Set dst con);
4860
4861 ins_cost(XFER_COST);
4862
4863 format %{ "fmv.h.x $dst, zr\t# float, #@loadConH0" %}
4864
4865 ins_encode %{
4866 assert(UseZfh || UseZfhmin, "must");
4867 __ fmv_h_x(as_FloatRegister($dst$$reg), zr);
4868 %}
4869
4870 ins_pipe(fp_load_constant_s);
4871 %}
4872
4873 // Load Float Constant
4874 instruct loadConF(fRegF dst, immF con) %{
4875 match(Set dst con);
4876
4877 ins_cost(LOAD_COST);
4878 format %{
4879 "flw $dst, [$constantaddress]\t# load from constant table: float=$con, #@loadConF"
4880 %}
4881
4882 ins_encode %{
4883 if (MacroAssembler::can_fp_imm_load($con$$constant)) {
4884 __ fli_s(as_FloatRegister($dst$$reg), $con$$constant);
4885 } else {
4886 __ flw(as_FloatRegister($dst$$reg), $constantaddress($con));
4887 }
4888 %}
4889
4890 ins_pipe(fp_load_constant_s);
4891 %}
4892
4893 instruct loadConF0(fRegF dst, immF0 con) %{
4894 match(Set dst con);
4895
4896 ins_cost(XFER_COST);
4897
4898 format %{ "fmv.w.x $dst, zr\t# float, #@loadConF0" %}
4899
4900 ins_encode %{
4901 __ fmv_w_x(as_FloatRegister($dst$$reg), zr);
4902 %}
4903
4904 ins_pipe(fp_load_constant_s);
4905 %}
4906
4907 // Load Double Constant
4908 instruct loadConD(fRegD dst, immD con) %{
4909 match(Set dst con);
4910
4911 ins_cost(LOAD_COST);
4912 format %{
4913 "fld $dst, [$constantaddress]\t# load from constant table: double=$con, #@loadConD"
4914 %}
4915
4916 ins_encode %{
4917 if (MacroAssembler::can_dp_imm_load($con$$constant)) {
4918 __ fli_d(as_FloatRegister($dst$$reg), $con$$constant);
4919 } else {
4920 __ fld(as_FloatRegister($dst$$reg), $constantaddress($con));
4921 }
4922 %}
4923
4924 ins_pipe(fp_load_constant_d);
4925 %}
4926
4927 instruct loadConD0(fRegD dst, immD0 con) %{
4928 match(Set dst con);
4929
4930 ins_cost(XFER_COST);
4931
4932 format %{ "fmv.d.x $dst, zr\t# double, #@loadConD0" %}
4933
4934 ins_encode %{
4935 __ fmv_d_x(as_FloatRegister($dst$$reg), zr);
4936 %}
4937
4938 ins_pipe(fp_load_constant_d);
4939 %}
4940
4941 // Store Byte
4942 instruct storeB(iRegIorL2I src, memory mem)
4943 %{
4944 match(Set mem (StoreB mem src));
4945
4946 ins_cost(STORE_COST);
4947 format %{ "sb $src, $mem\t# byte, #@storeB" %}
4948
4949 ins_encode %{
4950 __ sb(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
4951 %}
4952
4953 ins_pipe(istore_reg_mem);
4954 %}
4955
4956 instruct storeimmB0(immI0 zero, memory mem)
4957 %{
4958 match(Set mem (StoreB mem zero));
4959
4960 ins_cost(STORE_COST);
4961 format %{ "sb zr, $mem\t# byte, #@storeimmB0" %}
4962
4963 ins_encode %{
4964 __ sb(zr, Address(as_Register($mem$$base), $mem$$disp));
4965 %}
4966
4967 ins_pipe(istore_mem);
4968 %}
4969
4970 // Store Char/Short
4971 instruct storeC(iRegIorL2I src, memory mem)
4972 %{
4973 match(Set mem (StoreC mem src));
4974
4975 ins_cost(STORE_COST);
4976 format %{ "sh $src, $mem\t# short, #@storeC" %}
4977
4978 ins_encode %{
4979 __ sh(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
4980 %}
4981
4982 ins_pipe(istore_reg_mem);
4983 %}
4984
4985 instruct storeimmC0(immI0 zero, memory mem)
4986 %{
4987 match(Set mem (StoreC mem zero));
4988
4989 ins_cost(STORE_COST);
4990 format %{ "sh zr, $mem\t# short, #@storeimmC0" %}
4991
4992 ins_encode %{
4993 __ sh(zr, Address(as_Register($mem$$base), $mem$$disp));
4994 %}
4995
4996 ins_pipe(istore_mem);
4997 %}
4998
4999 // Store Integer
5000 instruct storeI(iRegIorL2I src, memory mem)
5001 %{
5002 match(Set mem(StoreI mem src));
5003
5004 ins_cost(STORE_COST);
5005 format %{ "sw $src, $mem\t# int, #@storeI" %}
5006
5007 ins_encode %{
5008 __ sw(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5009 %}
5010
5011 ins_pipe(istore_reg_mem);
5012 %}
5013
5014 instruct storeimmI0(immI0 zero, memory mem)
5015 %{
5016 match(Set mem(StoreI mem zero));
5017
5018 ins_cost(STORE_COST);
5019 format %{ "sw zr, $mem\t# int, #@storeimmI0" %}
5020
5021 ins_encode %{
5022 __ sw(zr, Address(as_Register($mem$$base), $mem$$disp));
5023 %}
5024
5025 ins_pipe(istore_mem);
5026 %}
5027
5028 // Store Long (64 bit signed)
5029 instruct storeL(iRegL src, memory mem)
5030 %{
5031 match(Set mem (StoreL mem src));
5032
5033 ins_cost(STORE_COST);
5034 format %{ "sd $src, $mem\t# long, #@storeL" %}
5035
5036 ins_encode %{
5037 __ sd(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5038 %}
5039
5040 ins_pipe(istore_reg_mem);
5041 %}
5042
5043 // Store Long (64 bit signed)
5044 instruct storeimmL0(immL0 zero, memory mem)
5045 %{
5046 match(Set mem (StoreL mem zero));
5047
5048 ins_cost(STORE_COST);
5049 format %{ "sd zr, $mem\t# long, #@storeimmL0" %}
5050
5051 ins_encode %{
5052 __ sd(zr, Address(as_Register($mem$$base), $mem$$disp));
5053 %}
5054
5055 ins_pipe(istore_mem);
5056 %}
5057
5058 // Store Pointer
5059 instruct storeP(iRegP src, memory mem)
5060 %{
5061 match(Set mem (StoreP mem src));
5062 predicate(n->as_Store()->barrier_data() == 0);
5063
5064 ins_cost(STORE_COST);
5065 format %{ "sd $src, $mem\t# ptr, #@storeP" %}
5066
5067 ins_encode %{
5068 __ sd(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5069 %}
5070
5071 ins_pipe(istore_reg_mem);
5072 %}
5073
5074 // Store Pointer
5075 instruct storeimmP0(immP0 zero, memory mem)
5076 %{
5077 match(Set mem (StoreP mem zero));
5078 predicate(n->as_Store()->barrier_data() == 0);
5079
5080 ins_cost(STORE_COST);
5081 format %{ "sd zr, $mem\t# ptr, #@storeimmP0" %}
5082
5083 ins_encode %{
5084 __ sd(zr, Address(as_Register($mem$$base), $mem$$disp));
5085 %}
5086
5087 ins_pipe(istore_mem);
5088 %}
5089
5090 // Store Compressed Pointer
5091 instruct storeN(iRegN src, memory mem)
5092 %{
5093 predicate(n->as_Store()->barrier_data() == 0);
5094 match(Set mem (StoreN mem src));
5095
5096 ins_cost(STORE_COST);
5097 format %{ "sw $src, $mem\t# compressed ptr, #@storeN" %}
5098
5099 ins_encode %{
5100 __ sw(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5101 %}
5102
5103 ins_pipe(istore_reg_mem);
5104 %}
5105
5106 instruct storeImmN0(immN0 zero, memory mem)
5107 %{
5108 predicate(n->as_Store()->barrier_data() == 0);
5109 match(Set mem (StoreN mem zero));
5110
5111 ins_cost(STORE_COST);
5112 format %{ "sw zr, $mem\t# compressed ptr, #@storeImmN0" %}
5113
5114 ins_encode %{
5115 __ sw(zr, Address(as_Register($mem$$base), $mem$$disp));
5116 %}
5117
5118 ins_pipe(istore_reg_mem);
5119 %}
5120
5121 // Store Float
5122 instruct storeF(fRegF src, memory mem)
5123 %{
5124 match(Set mem (StoreF mem src));
5125
5126 ins_cost(STORE_COST);
5127 format %{ "fsw $src, $mem\t# float, #@storeF" %}
5128
5129 ins_encode %{
5130 __ fsw(as_FloatRegister($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5131 %}
5132
5133 ins_pipe(fp_store_reg_s);
5134 %}
5135
5136 // Store Double
5137 instruct storeD(fRegD src, memory mem)
5138 %{
5139 match(Set mem (StoreD mem src));
5140
5141 ins_cost(STORE_COST);
5142 format %{ "fsd $src, $mem\t# double, #@storeD" %}
5143
5144 ins_encode %{
5145 __ fsd(as_FloatRegister($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5146 %}
5147
5148 ins_pipe(fp_store_reg_d);
5149 %}
5150
5151 // Store Compressed Klass Pointer
5152 instruct storeNKlass(iRegN src, memory mem)
5153 %{
5154 match(Set mem (StoreNKlass mem src));
5155
5156 ins_cost(STORE_COST);
5157 format %{ "sw $src, $mem\t# compressed klass ptr, #@storeNKlass" %}
5158
5159 ins_encode %{
5160 __ sw(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5161 %}
5162
5163 ins_pipe(istore_reg_mem);
5164 %}
5165
5166 // ============================================================================
5167 // Prefetch instructions
5168 // Must be safe to execute with invalid address (cannot fault).
5169
5170 instruct prefetchalloc( memory mem ) %{
5171 predicate(UseZicbop);
5172 match(PrefetchAllocation mem);
5173
5174 ins_cost(ALU_COST * 1);
5175 format %{ "prefetch_w $mem\t# Prefetch for write" %}
5176
5177 ins_encode %{
5178 if (Assembler::is_simm12($mem$$disp)) {
5179 if (($mem$$disp & 0x1f) == 0) {
5180 __ prefetch_w(as_Register($mem$$base), $mem$$disp);
5181 } else {
5182 __ addi(t0, as_Register($mem$$base), $mem$$disp);
5183 __ prefetch_w(t0, 0);
5184 }
5185 } else {
5186 __ mv(t0, $mem$$disp);
5187 __ add(t0, as_Register($mem$$base), t0);
5188 __ prefetch_w(t0, 0);
5189 }
5190 %}
5191
5192 ins_pipe(iload_prefetch);
5193 %}
5194
5195 // ============================================================================
5196 // Atomic operation instructions
5197 //
5198
5199 // standard CompareAndSwapX when we are using barriers
5200 // these have higher priority than the rules selected by a predicate
5201 instruct compareAndSwapB_narrow(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5202 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5203 %{
5204 predicate(!UseZabha || !UseZacas);
5205
5206 match(Set res (CompareAndSwapB mem (Binary oldval newval)));
5207
5208 ins_cost(2 * VOLATILE_REF_COST);
5209
5210 effect(TEMP_DEF res, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3, KILL cr);
5211
5212 format %{
5213 "cmpxchg $mem, $oldval, $newval\t# (byte) if $mem == $oldval then $mem <-- $newval\n\t"
5214 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapB_narrow"
5215 %}
5216
5217 ins_encode %{
5218 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5219 Assembler::relaxed /* acquire */, Assembler::rl /* release */, $res$$Register,
5220 true /* result as bool */, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5221 %}
5222
5223 ins_pipe(pipe_slow);
5224 %}
5225
5226 instruct compareAndSwapB(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5227 %{
5228 predicate(UseZabha && UseZacas);
5229
5230 match(Set res (CompareAndSwapB mem (Binary oldval newval)));
5231
5232 ins_cost(2 * VOLATILE_REF_COST);
5233
5234 format %{
5235 "cmpxchg $mem, $oldval, $newval\t# (byte) if $mem == $oldval then $mem <-- $newval\n\t"
5236 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapB"
5237 %}
5238
5239 ins_encode %{
5240 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5241 Assembler::relaxed /* acquire */, Assembler::rl /* release */, $res$$Register,
5242 true /* result as bool */);
5243 %}
5244
5245 ins_pipe(pipe_slow);
5246 %}
5247
5248 instruct compareAndSwapS_narrow(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5249 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5250 %{
5251 predicate(!UseZabha || !UseZacas);
5252
5253 match(Set res (CompareAndSwapS mem (Binary oldval newval)));
5254
5255 ins_cost(2 * VOLATILE_REF_COST);
5256
5257 effect(TEMP_DEF res, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3, KILL cr);
5258
5259 format %{
5260 "cmpxchg $mem, $oldval, $newval\t# (short) if $mem == $oldval then $mem <-- $newval\n\t"
5261 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapS_narrow"
5262 %}
5263
5264 ins_encode %{
5265 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5266 Assembler::relaxed /* acquire */, Assembler::rl /* release */, $res$$Register,
5267 true /* result as bool */, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5268 %}
5269
5270 ins_pipe(pipe_slow);
5271 %}
5272
5273 instruct compareAndSwapS(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5274 %{
5275 predicate(UseZabha && UseZacas);
5276
5277 match(Set res (CompareAndSwapS mem (Binary oldval newval)));
5278
5279 ins_cost(2 * VOLATILE_REF_COST);
5280
5281 format %{
5282 "cmpxchg $mem, $oldval, $newval\t# (short) if $mem == $oldval then $mem <-- $newval\n\t"
5283 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapS"
5284 %}
5285
5286 ins_encode %{
5287 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5288 Assembler::relaxed /* acquire */, Assembler::rl /* release */, $res$$Register,
5289 true /* result as bool */);
5290 %}
5291
5292 ins_pipe(pipe_slow);
5293 %}
5294
5295 instruct compareAndSwapI(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5296 %{
5297 match(Set res (CompareAndSwapI mem (Binary oldval newval)));
5298
5299 ins_cost(2 * VOLATILE_REF_COST);
5300
5301 format %{
5302 "cmpxchg $mem, $oldval, $newval\t# (int) if $mem == $oldval then $mem <-- $newval\n\t"
5303 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapI"
5304 %}
5305
5306 ins_encode %{
5307 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
5308 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
5309 /*result as bool*/ true);
5310 %}
5311
5312 ins_pipe(pipe_slow);
5313 %}
5314
5315 instruct compareAndSwapL(iRegINoSp res, indirect mem, iRegL oldval, iRegL newval)
5316 %{
5317 match(Set res (CompareAndSwapL mem (Binary oldval newval)));
5318
5319 ins_cost(2 * VOLATILE_REF_COST);
5320
5321 format %{
5322 "cmpxchg $mem, $oldval, $newval\t# (long) if $mem == $oldval then $mem <-- $newval\n\t"
5323 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapL"
5324 %}
5325
5326 ins_encode %{
5327 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5328 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
5329 /*result as bool*/ true);
5330 %}
5331
5332 ins_pipe(pipe_slow);
5333 %}
5334
5335 instruct compareAndSwapP(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval)
5336 %{
5337 predicate(n->as_LoadStore()->barrier_data() == 0);
5338
5339 match(Set res (CompareAndSwapP mem (Binary oldval newval)));
5340
5341 ins_cost(2 * VOLATILE_REF_COST);
5342
5343 format %{
5344 "cmpxchg $mem, $oldval, $newval\t# (ptr) if $mem == $oldval then $mem <-- $newval\n\t"
5345 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapP"
5346 %}
5347
5348 ins_encode %{
5349 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5350 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
5351 /*result as bool*/ true);
5352 %}
5353
5354 ins_pipe(pipe_slow);
5355 %}
5356
5357 instruct compareAndSwapN(iRegINoSp res, indirect mem, iRegN oldval, iRegN newval)
5358 %{
5359 predicate(n->as_LoadStore()->barrier_data() == 0);
5360
5361 match(Set res (CompareAndSwapN mem (Binary oldval newval)));
5362
5363 ins_cost(2 * VOLATILE_REF_COST);
5364
5365 format %{
5366 "cmpxchg $mem, $oldval, $newval\t# (narrow oop) if $mem == $oldval then $mem <-- $newval\n\t"
5367 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapN"
5368 %}
5369
5370 ins_encode %{
5371 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
5372 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
5373 /*result as bool*/ true);
5374 %}
5375
5376 ins_pipe(pipe_slow);
5377 %}
5378
5379 // alternative CompareAndSwapX when we are eliding barriers
5380 instruct compareAndSwapBAcq_narrow(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5381 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5382 %{
5383 predicate((!UseZabha || !UseZacas) && needs_acquiring_load_reserved(n));
5384
5385 match(Set res (CompareAndSwapB mem (Binary oldval newval)));
5386
5387 ins_cost(2 * VOLATILE_REF_COST);
5388
5389 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5390
5391 format %{
5392 "cmpxchg_acq $mem, $oldval, $newval\t# (byte) if $mem == $oldval then $mem <-- $newval\n\t"
5393 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapBAcq_narrow"
5394 %}
5395
5396 ins_encode %{
5397 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5398 Assembler::aq /* acquire */, Assembler::rl /* release */, $res$$Register,
5399 true /* result as bool */, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5400 %}
5401
5402 ins_pipe(pipe_slow);
5403 %}
5404
5405 instruct compareAndSwapBAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5406 %{
5407 predicate((UseZabha && UseZacas) && needs_acquiring_load_reserved(n));
5408
5409 match(Set res (CompareAndSwapB mem (Binary oldval newval)));
5410
5411 ins_cost(2 * VOLATILE_REF_COST);
5412
5413 format %{
5414 "cmpxchg $mem, $oldval, $newval\t# (byte) if $mem == $oldval then $mem <-- $newval\n\t"
5415 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapBAcq"
5416 %}
5417
5418 ins_encode %{
5419 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5420 Assembler::aq /* acquire */, Assembler::rl /* release */, $res$$Register,
5421 true /* result as bool */);
5422 %}
5423
5424 ins_pipe(pipe_slow);
5425 %}
5426
5427 instruct compareAndSwapSAcq_narrow(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5428 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5429 %{
5430 predicate((!UseZabha || !UseZacas) && needs_acquiring_load_reserved(n));
5431
5432 match(Set res (CompareAndSwapS mem (Binary oldval newval)));
5433
5434 ins_cost(2 * VOLATILE_REF_COST);
5435
5436 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5437
5438 format %{
5439 "cmpxchg_acq $mem, $oldval, $newval\t# (short) if $mem == $oldval then $mem <-- $newval\n\t"
5440 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapSAcq_narrow"
5441 %}
5442
5443 ins_encode %{
5444 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5445 Assembler::aq /* acquire */, Assembler::rl /* release */, $res$$Register,
5446 true /* result as bool */, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5447 %}
5448
5449 ins_pipe(pipe_slow);
5450 %}
5451
5452 instruct compareAndSwapSAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5453 %{
5454 predicate((UseZabha && UseZacas) && needs_acquiring_load_reserved(n));
5455
5456 match(Set res (CompareAndSwapS mem (Binary oldval newval)));
5457
5458 ins_cost(2 * VOLATILE_REF_COST);
5459
5460 format %{
5461 "cmpxchg $mem, $oldval, $newval\t# (short) if $mem == $oldval then $mem <-- $newval\n\t"
5462 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapSAcq"
5463 %}
5464
5465 ins_encode %{
5466 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5467 Assembler::aq /* acquire */, Assembler::rl /* release */, $res$$Register,
5468 true /* result as bool */);
5469 %}
5470
5471 ins_pipe(pipe_slow);
5472 %}
5473
5474 instruct compareAndSwapIAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5475 %{
5476 predicate(needs_acquiring_load_reserved(n));
5477
5478 match(Set res (CompareAndSwapI mem (Binary oldval newval)));
5479
5480 ins_cost(2 * VOLATILE_REF_COST);
5481
5482 format %{
5483 "cmpxchg_acq $mem, $oldval, $newval\t# (int) if $mem == $oldval then $mem <-- $newval\n\t"
5484 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapIAcq"
5485 %}
5486
5487 ins_encode %{
5488 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
5489 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
5490 /*result as bool*/ true);
5491 %}
5492
5493 ins_pipe(pipe_slow);
5494 %}
5495
5496 instruct compareAndSwapLAcq(iRegINoSp res, indirect mem, iRegL oldval, iRegL newval)
5497 %{
5498 predicate(needs_acquiring_load_reserved(n));
5499
5500 match(Set res (CompareAndSwapL mem (Binary oldval newval)));
5501
5502 ins_cost(2 * VOLATILE_REF_COST);
5503
5504 format %{
5505 "cmpxchg_acq $mem, $oldval, $newval\t# (long) if $mem == $oldval then $mem <-- $newval\n\t"
5506 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapLAcq"
5507 %}
5508
5509 ins_encode %{
5510 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5511 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
5512 /*result as bool*/ true);
5513 %}
5514
5515 ins_pipe(pipe_slow);
5516 %}
5517
5518 instruct compareAndSwapPAcq(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval)
5519 %{
5520 predicate(needs_acquiring_load_reserved(n) && (n->as_LoadStore()->barrier_data() == 0));
5521
5522 match(Set res (CompareAndSwapP mem (Binary oldval newval)));
5523
5524 ins_cost(2 * VOLATILE_REF_COST);
5525
5526 format %{
5527 "cmpxchg_acq $mem, $oldval, $newval\t# (ptr) if $mem == $oldval then $mem <-- $newval\n\t"
5528 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapPAcq"
5529 %}
5530
5531 ins_encode %{
5532 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5533 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
5534 /*result as bool*/ true);
5535 %}
5536
5537 ins_pipe(pipe_slow);
5538 %}
5539
5540 instruct compareAndSwapNAcq(iRegINoSp res, indirect mem, iRegN oldval, iRegN newval)
5541 %{
5542 predicate(needs_acquiring_load_reserved(n) && n->as_LoadStore()->barrier_data() == 0);
5543
5544 match(Set res (CompareAndSwapN mem (Binary oldval newval)));
5545
5546 ins_cost(2 * VOLATILE_REF_COST);
5547
5548 format %{
5549 "cmpxchg_acq $mem, $oldval, $newval\t# (narrow oop) if $mem == $oldval then $mem <-- $newval\n\t"
5550 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapNAcq"
5551 %}
5552
5553 ins_encode %{
5554 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
5555 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
5556 /*result as bool*/ true);
5557 %}
5558
5559 ins_pipe(pipe_slow);
5560 %}
5561
5562 // Sundry CAS operations. Note that release is always true,
5563 // regardless of the memory ordering of the CAS. This is because we
5564 // need the volatile case to be sequentially consistent but there is
5565 // no trailing StoreLoad barrier emitted by C2. Unfortunately we
5566 // can't check the type of memory ordering here, so we always emit a
5567 // sc_d(w) with rl bit set.
5568 instruct compareAndExchangeB_narrow(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5569 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5570 %{
5571 predicate(!UseZabha || !UseZacas);
5572
5573 match(Set res (CompareAndExchangeB mem (Binary oldval newval)));
5574
5575 ins_cost(2 * VOLATILE_REF_COST);
5576
5577 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5578
5579 format %{
5580 "cmpxchg $res = $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeB_narrow"
5581 %}
5582
5583 ins_encode %{
5584 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5585 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
5586 /*result_as_bool*/ false, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5587 %}
5588
5589 ins_pipe(pipe_slow);
5590 %}
5591
5592 instruct compareAndExchangeB(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5593 %{
5594 predicate(UseZabha && UseZacas);
5595
5596 match(Set res (CompareAndExchangeB mem (Binary oldval newval)));
5597
5598 ins_cost(2 * VOLATILE_REF_COST);
5599
5600 format %{
5601 "cmpxchg $res = $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeB"
5602 %}
5603
5604 ins_encode %{
5605 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5606 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5607 %}
5608
5609 ins_pipe(pipe_slow);
5610 %}
5611
5612 instruct compareAndExchangeS_narrow(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5613 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5614 %{
5615 predicate(!UseZabha || !UseZacas);
5616
5617 match(Set res (CompareAndExchangeS mem (Binary oldval newval)));
5618
5619 ins_cost(2 * VOLATILE_REF_COST);
5620
5621 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5622
5623 format %{
5624 "cmpxchg $res = $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeS_narrow"
5625 %}
5626
5627 ins_encode %{
5628 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5629 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
5630 /*result_as_bool*/ false, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5631 %}
5632
5633 ins_pipe(pipe_slow);
5634 %}
5635
5636 instruct compareAndExchangeS(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5637 %{
5638 predicate(UseZabha && UseZacas);
5639
5640 match(Set res (CompareAndExchangeS mem (Binary oldval newval)));
5641
5642 ins_cost(2 * VOLATILE_REF_COST);
5643
5644 format %{
5645 "cmpxchg $res = $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeS"
5646 %}
5647
5648 ins_encode %{
5649 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5650 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5651 %}
5652
5653 ins_pipe(pipe_slow);
5654 %}
5655
5656 instruct compareAndExchangeI(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5657 %{
5658 match(Set res (CompareAndExchangeI mem (Binary oldval newval)));
5659
5660 ins_cost(2 * VOLATILE_REF_COST);
5661
5662 format %{
5663 "cmpxchg $res = $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeI"
5664 %}
5665
5666 ins_encode %{
5667 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
5668 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5669 %}
5670
5671 ins_pipe(pipe_slow);
5672 %}
5673
5674 instruct compareAndExchangeL(iRegLNoSp res, indirect mem, iRegL oldval, iRegL newval)
5675 %{
5676 match(Set res (CompareAndExchangeL mem (Binary oldval newval)));
5677
5678 ins_cost(2 * VOLATILE_REF_COST);
5679
5680 format %{
5681 "cmpxchg $res = $mem, $oldval, $newval\t# (long, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeL"
5682 %}
5683
5684 ins_encode %{
5685 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5686 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5687 %}
5688
5689 ins_pipe(pipe_slow);
5690 %}
5691
5692 instruct compareAndExchangeN(iRegNNoSp res, indirect mem, iRegN oldval, iRegN newval)
5693 %{
5694 predicate(n->as_LoadStore()->barrier_data() == 0);
5695
5696 match(Set res (CompareAndExchangeN mem (Binary oldval newval)));
5697
5698 ins_cost(2 * VOLATILE_REF_COST);
5699
5700 format %{
5701 "cmpxchg $res = $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeN"
5702 %}
5703
5704 ins_encode %{
5705 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
5706 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5707 %}
5708
5709 ins_pipe(pipe_slow);
5710 %}
5711
5712 instruct compareAndExchangeP(iRegPNoSp res, indirect mem, iRegP oldval, iRegP newval)
5713 %{
5714 predicate(n->as_LoadStore()->barrier_data() == 0);
5715
5716 match(Set res (CompareAndExchangeP mem (Binary oldval newval)));
5717
5718 ins_cost(2 * VOLATILE_REF_COST);
5719
5720 format %{
5721 "cmpxchg $res = $mem, $oldval, $newval\t# (ptr, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeP"
5722 %}
5723
5724 ins_encode %{
5725 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5726 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5727 %}
5728
5729 ins_pipe(pipe_slow);
5730 %}
5731
5732 instruct compareAndExchangeBAcq_narrow(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5733 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5734 %{
5735 predicate((!UseZabha || !UseZacas) && needs_acquiring_load_reserved(n));
5736
5737 match(Set res (CompareAndExchangeB mem (Binary oldval newval)));
5738
5739 ins_cost(2 * VOLATILE_REF_COST);
5740
5741 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5742
5743 format %{
5744 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeBAcq_narrow"
5745 %}
5746
5747 ins_encode %{
5748 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5749 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
5750 /*result_as_bool*/ false, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5751 %}
5752
5753 ins_pipe(pipe_slow);
5754 %}
5755
5756 instruct compareAndExchangeBAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5757 %{
5758 predicate((UseZabha && UseZacas) && needs_acquiring_load_reserved(n));
5759
5760 match(Set res (CompareAndExchangeB mem (Binary oldval newval)));
5761
5762 ins_cost(2 * VOLATILE_REF_COST);
5763
5764 format %{
5765 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeBAcq"
5766 %}
5767
5768 ins_encode %{
5769 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5770 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
5771 %}
5772
5773 ins_pipe(pipe_slow);
5774 %}
5775
5776 instruct compareAndExchangeSAcq_narrow(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5777 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5778 %{
5779 predicate((!UseZabha || !UseZacas) && needs_acquiring_load_reserved(n));
5780
5781 match(Set res (CompareAndExchangeS mem (Binary oldval newval)));
5782
5783 ins_cost(2 * VOLATILE_REF_COST);
5784
5785 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5786
5787 format %{
5788 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeSAcq_narrow"
5789 %}
5790
5791 ins_encode %{
5792 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5793 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
5794 /*result_as_bool*/ false, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5795 %}
5796
5797 ins_pipe(pipe_slow);
5798 %}
5799
5800 instruct compareAndExchangeSAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5801 %{
5802 predicate((UseZabha && UseZacas) && needs_acquiring_load_reserved(n));
5803
5804 match(Set res (CompareAndExchangeS mem (Binary oldval newval)));
5805
5806 ins_cost(2 * VOLATILE_REF_COST);
5807
5808 format %{
5809 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeSAcq"
5810 %}
5811
5812 ins_encode %{
5813 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5814 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
5815 %}
5816
5817 ins_pipe(pipe_slow);
5818 %}
5819
5820 instruct compareAndExchangeIAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5821 %{
5822 predicate(needs_acquiring_load_reserved(n));
5823
5824 match(Set res (CompareAndExchangeI mem (Binary oldval newval)));
5825
5826 ins_cost(2 * VOLATILE_REF_COST);
5827
5828 format %{
5829 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeIAcq"
5830 %}
5831
5832 ins_encode %{
5833 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
5834 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
5835 %}
5836
5837 ins_pipe(pipe_slow);
5838 %}
5839
5840 instruct compareAndExchangeLAcq(iRegLNoSp res, indirect mem, iRegL oldval, iRegL newval)
5841 %{
5842 predicate(needs_acquiring_load_reserved(n));
5843
5844 match(Set res (CompareAndExchangeL mem (Binary oldval newval)));
5845
5846 ins_cost(2 * VOLATILE_REF_COST);
5847
5848 format %{
5849 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (long, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeLAcq"
5850 %}
5851
5852 ins_encode %{
5853 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5854 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
5855 %}
5856
5857 ins_pipe(pipe_slow);
5858 %}
5859
5860 instruct compareAndExchangeNAcq(iRegNNoSp res, indirect mem, iRegN oldval, iRegN newval)
5861 %{
5862 predicate(needs_acquiring_load_reserved(n) && n->as_LoadStore()->barrier_data() == 0);
5863
5864 match(Set res (CompareAndExchangeN mem (Binary oldval newval)));
5865
5866 ins_cost(2 * VOLATILE_REF_COST);
5867
5868 format %{
5869 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeNAcq"
5870 %}
5871
5872 ins_encode %{
5873 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
5874 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
5875 %}
5876
5877 ins_pipe(pipe_slow);
5878 %}
5879
5880 instruct compareAndExchangePAcq(iRegPNoSp res, indirect mem, iRegP oldval, iRegP newval)
5881 %{
5882 predicate(needs_acquiring_load_reserved(n) && (n->as_LoadStore()->barrier_data() == 0));
5883
5884 match(Set res (CompareAndExchangeP mem (Binary oldval newval)));
5885
5886 ins_cost(2 * VOLATILE_REF_COST);
5887
5888 format %{
5889 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (ptr, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangePAcq"
5890 %}
5891
5892 ins_encode %{
5893 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5894 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
5895 %}
5896
5897 ins_pipe(pipe_slow);
5898 %}
5899
5900 instruct weakCompareAndSwapB_narrow(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5901 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5902 %{
5903 predicate(!UseZabha || !UseZacas);
5904
5905 match(Set res (WeakCompareAndSwapB mem (Binary oldval newval)));
5906
5907 ins_cost(2 * VOLATILE_REF_COST);
5908
5909 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5910
5911 format %{
5912 "weak_cmpxchg $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5913 "# $res == 1 when success, #@weakCompareAndSwapB_narrow"
5914 %}
5915
5916 ins_encode %{
5917 __ weak_cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5918 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
5919 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5920 %}
5921
5922 ins_pipe(pipe_slow);
5923 %}
5924
5925 instruct weakCompareAndSwapB(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5926 %{
5927 predicate(UseZabha && UseZacas);
5928
5929 match(Set res (WeakCompareAndSwapB mem (Binary oldval newval)));
5930
5931 ins_cost(2 * VOLATILE_REF_COST);
5932
5933 format %{
5934 "weak_cmpxchg $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5935 "# $res == 1 when success, #@weakCompareAndSwapB"
5936 %}
5937
5938 ins_encode %{
5939 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5940 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5941 %}
5942
5943 ins_pipe(pipe_slow);
5944 %}
5945
5946 instruct weakCompareAndSwapS_narrow(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5947 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5948 %{
5949 predicate(!UseZabha || !UseZacas);
5950
5951 match(Set res (WeakCompareAndSwapS mem (Binary oldval newval)));
5952
5953 ins_cost(2 * VOLATILE_REF_COST);
5954
5955 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5956
5957 format %{
5958 "weak_cmpxchg $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5959 "# $res == 1 when success, #@weakCompareAndSwapS_narrow"
5960 %}
5961
5962 ins_encode %{
5963 __ weak_cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5964 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
5965 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5966 %}
5967
5968 ins_pipe(pipe_slow);
5969 %}
5970
5971 instruct weakCompareAndSwapS(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5972 %{
5973 predicate(UseZabha && UseZacas);
5974
5975 match(Set res (WeakCompareAndSwapS mem (Binary oldval newval)));
5976
5977 ins_cost(2 * VOLATILE_REF_COST);
5978
5979 format %{
5980 "weak_cmpxchg $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5981 "# $res == 1 when success, #@weakCompareAndSwapS"
5982 %}
5983
5984 ins_encode %{
5985 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5986 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5987 %}
5988
5989 ins_pipe(pipe_slow);
5990 %}
5991
5992 instruct weakCompareAndSwapI(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5993 %{
5994 match(Set res (WeakCompareAndSwapI mem (Binary oldval newval)));
5995
5996 ins_cost(2 * VOLATILE_REF_COST);
5997
5998 format %{
5999 "weak_cmpxchg $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval\n\t"
6000 "# $res == 1 when success, #@weakCompareAndSwapI"
6001 %}
6002
6003 ins_encode %{
6004 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
6005 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
6006 %}
6007
6008 ins_pipe(pipe_slow);
6009 %}
6010
6011 instruct weakCompareAndSwapL(iRegINoSp res, indirect mem, iRegL oldval, iRegL newval)
6012 %{
6013 match(Set res (WeakCompareAndSwapL mem (Binary oldval newval)));
6014
6015 ins_cost(2 * VOLATILE_REF_COST);
6016
6017 format %{
6018 "weak_cmpxchg $mem, $oldval, $newval\t# (long, weak) if $mem == $oldval then $mem <-- $newval\n\t"
6019 "# $res == 1 when success, #@weakCompareAndSwapL"
6020 %}
6021
6022 ins_encode %{
6023 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
6024 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
6025 %}
6026
6027 ins_pipe(pipe_slow);
6028 %}
6029
6030 instruct weakCompareAndSwapN(iRegINoSp res, indirect mem, iRegN oldval, iRegN newval)
6031 %{
6032 predicate(n->as_LoadStore()->barrier_data() == 0);
6033
6034 match(Set res (WeakCompareAndSwapN mem (Binary oldval newval)));
6035
6036 ins_cost(2 * VOLATILE_REF_COST);
6037
6038 format %{
6039 "weak_cmpxchg $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval\n\t"
6040 "# $res == 1 when success, #@weakCompareAndSwapN"
6041 %}
6042
6043 ins_encode %{
6044 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
6045 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
6046 %}
6047
6048 ins_pipe(pipe_slow);
6049 %}
6050
6051 instruct weakCompareAndSwapP(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval)
6052 %{
6053 predicate(n->as_LoadStore()->barrier_data() == 0);
6054
6055 match(Set res (WeakCompareAndSwapP mem (Binary oldval newval)));
6056
6057 ins_cost(2 * VOLATILE_REF_COST);
6058
6059 format %{
6060 "weak_cmpxchg $mem, $oldval, $newval\t# (ptr, weak) if $mem == $oldval then $mem <-- $newval\n\t"
6061 "# $res == 1 when success, #@weakCompareAndSwapP"
6062 %}
6063
6064 ins_encode %{
6065 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
6066 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
6067 %}
6068
6069 ins_pipe(pipe_slow);
6070 %}
6071
6072 instruct weakCompareAndSwapBAcq_narrow(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
6073 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
6074 %{
6075 predicate((!UseZabha || !UseZacas) && needs_acquiring_load_reserved(n));
6076
6077 match(Set res (WeakCompareAndSwapB mem (Binary oldval newval)));
6078
6079 ins_cost(2 * VOLATILE_REF_COST);
6080
6081 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
6082
6083 format %{
6084 "weak_cmpxchg_acq $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval\n\t"
6085 "# $res == 1 when success, #@weakCompareAndSwapBAcq_narrow"
6086 %}
6087
6088 ins_encode %{
6089 __ weak_cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
6090 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
6091 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
6092 %}
6093
6094 ins_pipe(pipe_slow);
6095 %}
6096
6097 instruct weakCompareAndSwapBAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
6098 %{
6099 predicate((UseZabha && UseZacas) && needs_acquiring_load_reserved(n));
6100
6101 match(Set res (WeakCompareAndSwapB mem (Binary oldval newval)));
6102
6103 ins_cost(2 * VOLATILE_REF_COST);
6104
6105 format %{
6106 "weak_cmpxchg_acq $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval\n\t"
6107 "# $res == 1 when success, #@weakCompareAndSwapBAcq"
6108 %}
6109
6110 ins_encode %{
6111 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
6112 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
6113 %}
6114
6115 ins_pipe(pipe_slow);
6116 %}
6117
6118 instruct weakCompareAndSwapSAcq_narrow(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
6119 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
6120 %{
6121 predicate((!UseZabha || !UseZacas) && needs_acquiring_load_reserved(n));
6122
6123 match(Set res (WeakCompareAndSwapS mem (Binary oldval newval)));
6124
6125 ins_cost(2 * VOLATILE_REF_COST);
6126
6127 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
6128
6129 format %{
6130 "weak_cmpxchg_acq $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval\n\t"
6131 "# $res == 1 when success, #@weakCompareAndSwapSAcq_narrow"
6132 %}
6133
6134 ins_encode %{
6135 __ weak_cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
6136 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
6137 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
6138 %}
6139
6140 ins_pipe(pipe_slow);
6141 %}
6142
6143 instruct weakCompareAndSwapSAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
6144 %{
6145 predicate((UseZabha && UseZacas) && needs_acquiring_load_reserved(n));
6146
6147 match(Set res (WeakCompareAndSwapS mem (Binary oldval newval)));
6148
6149 ins_cost(2 * VOLATILE_REF_COST);
6150
6151 format %{
6152 "weak_cmpxchg_acq $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval\n\t"
6153 "# $res == 1 when success, #@weakCompareAndSwapSAcq"
6154 %}
6155
6156 ins_encode %{
6157 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
6158 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
6159 %}
6160
6161 ins_pipe(pipe_slow);
6162 %}
6163
6164 instruct weakCompareAndSwapIAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
6165 %{
6166 predicate(needs_acquiring_load_reserved(n));
6167
6168 match(Set res (WeakCompareAndSwapI mem (Binary oldval newval)));
6169
6170 ins_cost(2 * VOLATILE_REF_COST);
6171
6172 format %{
6173 "weak_cmpxchg_acq $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval\n\t"
6174 "# $res == 1 when success, #@weakCompareAndSwapIAcq"
6175 %}
6176
6177 ins_encode %{
6178 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
6179 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
6180 %}
6181
6182 ins_pipe(pipe_slow);
6183 %}
6184
6185 instruct weakCompareAndSwapLAcq(iRegINoSp res, indirect mem, iRegL oldval, iRegL newval)
6186 %{
6187 predicate(needs_acquiring_load_reserved(n));
6188
6189 match(Set res (WeakCompareAndSwapL mem (Binary oldval newval)));
6190
6191 ins_cost(2 * VOLATILE_REF_COST);
6192
6193 format %{
6194 "weak_cmpxchg_acq $mem, $oldval, $newval\t# (long, weak) if $mem == $oldval then $mem <-- $newval\n\t"
6195 "# $res == 1 when success, #@weakCompareAndSwapLAcq"
6196 %}
6197
6198 ins_encode %{
6199 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
6200 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
6201 %}
6202
6203 ins_pipe(pipe_slow);
6204 %}
6205
6206 instruct weakCompareAndSwapNAcq(iRegINoSp res, indirect mem, iRegN oldval, iRegN newval)
6207 %{
6208 predicate(needs_acquiring_load_reserved(n) && n->as_LoadStore()->barrier_data() == 0);
6209
6210 match(Set res (WeakCompareAndSwapN mem (Binary oldval newval)));
6211
6212 ins_cost(2 * VOLATILE_REF_COST);
6213
6214 format %{
6215 "weak_cmpxchg_acq $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval\n\t"
6216 "# $res == 1 when success, #@weakCompareAndSwapNAcq"
6217 %}
6218
6219 ins_encode %{
6220 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
6221 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
6222 %}
6223
6224 ins_pipe(pipe_slow);
6225 %}
6226
6227 instruct weakCompareAndSwapPAcq(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval)
6228 %{
6229 predicate(needs_acquiring_load_reserved(n) && (n->as_LoadStore()->barrier_data() == 0));
6230
6231 match(Set res (WeakCompareAndSwapP mem (Binary oldval newval)));
6232
6233 ins_cost(2 * VOLATILE_REF_COST);
6234
6235 format %{
6236 "weak_cmpxchg_acq $mem, $oldval, $newval\t# (ptr, weak) if $mem == $oldval then $mem <-- $newval\n\t"
6237 "\t# $res == 1 when success, #@weakCompareAndSwapPAcq"
6238 %}
6239
6240 ins_encode %{
6241 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
6242 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
6243 %}
6244
6245 ins_pipe(pipe_slow);
6246 %}
6247
6248 instruct get_and_setI(indirect mem, iRegI newv, iRegINoSp prev)
6249 %{
6250 match(Set prev (GetAndSetI mem newv));
6251
6252 ins_cost(ALU_COST);
6253
6254 format %{ "atomic_xchgw $prev, $newv, [$mem]\t#@get_and_setI" %}
6255
6256 ins_encode %{
6257 __ atomic_xchgw($prev$$Register, $newv$$Register, as_Register($mem$$base));
6258 %}
6259
6260 ins_pipe(pipe_serial);
6261 %}
6262
6263 instruct get_and_setL(indirect mem, iRegL newv, iRegLNoSp prev)
6264 %{
6265 match(Set prev (GetAndSetL mem newv));
6266
6267 ins_cost(ALU_COST);
6268
6269 format %{ "atomic_xchg $prev, $newv, [$mem]\t#@get_and_setL" %}
6270
6271 ins_encode %{
6272 __ atomic_xchg($prev$$Register, $newv$$Register, as_Register($mem$$base));
6273 %}
6274
6275 ins_pipe(pipe_serial);
6276 %}
6277
6278 instruct get_and_setN(indirect mem, iRegN newv, iRegINoSp prev)
6279 %{
6280 predicate(n->as_LoadStore()->barrier_data() == 0);
6281
6282 match(Set prev (GetAndSetN mem newv));
6283
6284 ins_cost(ALU_COST);
6285
6286 format %{ "atomic_xchgwu $prev, $newv, [$mem]\t#@get_and_setN" %}
6287
6288 ins_encode %{
6289 __ atomic_xchgwu($prev$$Register, $newv$$Register, as_Register($mem$$base));
6290 %}
6291
6292 ins_pipe(pipe_serial);
6293 %}
6294
6295 instruct get_and_setP(indirect mem, iRegP newv, iRegPNoSp prev)
6296 %{
6297 predicate(n->as_LoadStore()->barrier_data() == 0);
6298 match(Set prev (GetAndSetP mem newv));
6299
6300 ins_cost(ALU_COST);
6301
6302 format %{ "atomic_xchg $prev, $newv, [$mem]\t#@get_and_setP" %}
6303
6304 ins_encode %{
6305 __ atomic_xchg($prev$$Register, $newv$$Register, as_Register($mem$$base));
6306 %}
6307
6308 ins_pipe(pipe_serial);
6309 %}
6310
6311 instruct get_and_setIAcq(indirect mem, iRegI newv, iRegINoSp prev)
6312 %{
6313 predicate(needs_acquiring_load_reserved(n));
6314
6315 match(Set prev (GetAndSetI mem newv));
6316
6317 ins_cost(ALU_COST);
6318
6319 format %{ "atomic_xchgw_acq $prev, $newv, [$mem]\t#@get_and_setIAcq" %}
6320
6321 ins_encode %{
6322 __ atomic_xchgalw($prev$$Register, $newv$$Register, as_Register($mem$$base));
6323 %}
6324
6325 ins_pipe(pipe_serial);
6326 %}
6327
6328 instruct get_and_setLAcq(indirect mem, iRegL newv, iRegLNoSp prev)
6329 %{
6330 predicate(needs_acquiring_load_reserved(n));
6331
6332 match(Set prev (GetAndSetL mem newv));
6333
6334 ins_cost(ALU_COST);
6335
6336 format %{ "atomic_xchg_acq $prev, $newv, [$mem]\t#@get_and_setLAcq" %}
6337
6338 ins_encode %{
6339 __ atomic_xchgal($prev$$Register, $newv$$Register, as_Register($mem$$base));
6340 %}
6341
6342 ins_pipe(pipe_serial);
6343 %}
6344
6345 instruct get_and_setNAcq(indirect mem, iRegN newv, iRegINoSp prev)
6346 %{
6347 predicate(needs_acquiring_load_reserved(n) && n->as_LoadStore()->barrier_data() == 0);
6348
6349 match(Set prev (GetAndSetN mem newv));
6350
6351 ins_cost(ALU_COST);
6352
6353 format %{ "atomic_xchgwu_acq $prev, $newv, [$mem]\t#@get_and_setNAcq" %}
6354
6355 ins_encode %{
6356 __ atomic_xchgalwu($prev$$Register, $newv$$Register, as_Register($mem$$base));
6357 %}
6358
6359 ins_pipe(pipe_serial);
6360 %}
6361
6362 instruct get_and_setPAcq(indirect mem, iRegP newv, iRegPNoSp prev)
6363 %{
6364 predicate(needs_acquiring_load_reserved(n) && (n->as_LoadStore()->barrier_data() == 0));
6365
6366 match(Set prev (GetAndSetP mem newv));
6367
6368 ins_cost(ALU_COST);
6369
6370 format %{ "atomic_xchg_acq $prev, $newv, [$mem]\t#@get_and_setPAcq" %}
6371
6372 ins_encode %{
6373 __ atomic_xchgal($prev$$Register, $newv$$Register, as_Register($mem$$base));
6374 %}
6375
6376 ins_pipe(pipe_serial);
6377 %}
6378
6379 instruct get_and_addL(indirect mem, iRegLNoSp newval, iRegL incr)
6380 %{
6381 match(Set newval (GetAndAddL mem incr));
6382
6383 ins_cost(ALU_COST);
6384
6385 format %{ "get_and_addL $newval, [$mem], $incr\t#@get_and_addL" %}
6386
6387 ins_encode %{
6388 __ atomic_add($newval$$Register, $incr$$Register, as_Register($mem$$base));
6389 %}
6390
6391 ins_pipe(pipe_serial);
6392 %}
6393
6394 instruct get_and_addL_no_res(indirect mem, Universe dummy, iRegL incr)
6395 %{
6396 predicate(n->as_LoadStore()->result_not_used());
6397
6398 match(Set dummy (GetAndAddL mem incr));
6399
6400 ins_cost(ALU_COST);
6401
6402 format %{ "get_and_addL [$mem], $incr\t#@get_and_addL_no_res" %}
6403
6404 ins_encode %{
6405 __ atomic_add(noreg, $incr$$Register, as_Register($mem$$base));
6406 %}
6407
6408 ins_pipe(pipe_serial);
6409 %}
6410
6411 instruct get_and_addLi(indirect mem, iRegLNoSp newval, immLAdd incr)
6412 %{
6413 match(Set newval (GetAndAddL mem incr));
6414
6415 ins_cost(ALU_COST);
6416
6417 format %{ "get_and_addL $newval, [$mem], $incr\t#@get_and_addLi" %}
6418
6419 ins_encode %{
6420 __ atomic_add($newval$$Register, $incr$$constant, as_Register($mem$$base));
6421 %}
6422
6423 ins_pipe(pipe_serial);
6424 %}
6425
6426 instruct get_and_addLi_no_res(indirect mem, Universe dummy, immLAdd incr)
6427 %{
6428 predicate(n->as_LoadStore()->result_not_used());
6429
6430 match(Set dummy (GetAndAddL mem incr));
6431
6432 ins_cost(ALU_COST);
6433
6434 format %{ "get_and_addL [$mem], $incr\t#@get_and_addLi_no_res" %}
6435
6436 ins_encode %{
6437 __ atomic_add(noreg, $incr$$constant, as_Register($mem$$base));
6438 %}
6439
6440 ins_pipe(pipe_serial);
6441 %}
6442
6443 instruct get_and_addI(indirect mem, iRegINoSp newval, iRegIorL2I incr)
6444 %{
6445 match(Set newval (GetAndAddI mem incr));
6446
6447 ins_cost(ALU_COST);
6448
6449 format %{ "get_and_addI $newval, [$mem], $incr\t#@get_and_addI" %}
6450
6451 ins_encode %{
6452 __ atomic_addw($newval$$Register, $incr$$Register, as_Register($mem$$base));
6453 %}
6454
6455 ins_pipe(pipe_serial);
6456 %}
6457
6458 instruct get_and_addI_no_res(indirect mem, Universe dummy, iRegIorL2I incr)
6459 %{
6460 predicate(n->as_LoadStore()->result_not_used());
6461
6462 match(Set dummy (GetAndAddI mem incr));
6463
6464 ins_cost(ALU_COST);
6465
6466 format %{ "get_and_addI [$mem], $incr\t#@get_and_addI_no_res" %}
6467
6468 ins_encode %{
6469 __ atomic_addw(noreg, $incr$$Register, as_Register($mem$$base));
6470 %}
6471
6472 ins_pipe(pipe_serial);
6473 %}
6474
6475 instruct get_and_addIi(indirect mem, iRegINoSp newval, immIAdd incr)
6476 %{
6477 match(Set newval (GetAndAddI mem incr));
6478
6479 ins_cost(ALU_COST);
6480
6481 format %{ "get_and_addI $newval, [$mem], $incr\t#@get_and_addIi" %}
6482
6483 ins_encode %{
6484 __ atomic_addw($newval$$Register, $incr$$constant, as_Register($mem$$base));
6485 %}
6486
6487 ins_pipe(pipe_serial);
6488 %}
6489
6490 instruct get_and_addIi_no_res(indirect mem, Universe dummy, immIAdd incr)
6491 %{
6492 predicate(n->as_LoadStore()->result_not_used());
6493
6494 match(Set dummy (GetAndAddI mem incr));
6495
6496 ins_cost(ALU_COST);
6497
6498 format %{ "get_and_addI [$mem], $incr\t#@get_and_addIi_no_res" %}
6499
6500 ins_encode %{
6501 __ atomic_addw(noreg, $incr$$constant, as_Register($mem$$base));
6502 %}
6503
6504 ins_pipe(pipe_serial);
6505 %}
6506
6507 instruct get_and_addLAcq(indirect mem, iRegLNoSp newval, iRegL incr)
6508 %{
6509 predicate(needs_acquiring_load_reserved(n));
6510
6511 match(Set newval (GetAndAddL mem incr));
6512
6513 ins_cost(ALU_COST);
6514
6515 format %{ "get_and_addL_acq $newval, [$mem], $incr\t#@get_and_addLAcq" %}
6516
6517 ins_encode %{
6518 __ atomic_addal($newval$$Register, $incr$$Register, as_Register($mem$$base));
6519 %}
6520
6521 ins_pipe(pipe_serial);
6522 %}
6523
6524 instruct get_and_addL_no_resAcq(indirect mem, Universe dummy, iRegL incr) %{
6525 predicate(n->as_LoadStore()->result_not_used() && needs_acquiring_load_reserved(n));
6526
6527 match(Set dummy (GetAndAddL mem incr));
6528
6529 ins_cost(ALU_COST);
6530
6531 format %{ "get_and_addL_acq [$mem], $incr\t#@get_and_addL_no_resAcq" %}
6532
6533 ins_encode %{
6534 __ atomic_addal(noreg, $incr$$Register, as_Register($mem$$base));
6535 %}
6536
6537 ins_pipe(pipe_serial);
6538 %}
6539
6540 instruct get_and_addLiAcq(indirect mem, iRegLNoSp newval, immLAdd incr)
6541 %{
6542 predicate(needs_acquiring_load_reserved(n));
6543
6544 match(Set newval (GetAndAddL mem incr));
6545
6546 ins_cost(ALU_COST);
6547
6548 format %{ "get_and_addL_acq $newval, [$mem], $incr\t#@get_and_addLiAcq" %}
6549
6550 ins_encode %{
6551 __ atomic_addal($newval$$Register, $incr$$constant, as_Register($mem$$base));
6552 %}
6553
6554 ins_pipe(pipe_serial);
6555 %}
6556
6557 instruct get_and_addLi_no_resAcq(indirect mem, Universe dummy, immLAdd incr)
6558 %{
6559 predicate(n->as_LoadStore()->result_not_used() && needs_acquiring_load_reserved(n));
6560
6561 match(Set dummy (GetAndAddL mem incr));
6562
6563 ins_cost(ALU_COST);
6564
6565 format %{ "get_and_addL_acq [$mem], $incr\t#@get_and_addLi_no_resAcq" %}
6566
6567 ins_encode %{
6568 __ atomic_addal(noreg, $incr$$constant, as_Register($mem$$base));
6569 %}
6570
6571 ins_pipe(pipe_serial);
6572 %}
6573
6574 instruct get_and_addIAcq(indirect mem, iRegINoSp newval, iRegIorL2I incr)
6575 %{
6576 predicate(needs_acquiring_load_reserved(n));
6577
6578 match(Set newval (GetAndAddI mem incr));
6579
6580 ins_cost(ALU_COST);
6581
6582 format %{ "get_and_addI_acq $newval, [$mem], $incr\t#@get_and_addIAcq" %}
6583
6584 ins_encode %{
6585 __ atomic_addalw($newval$$Register, $incr$$Register, as_Register($mem$$base));
6586 %}
6587
6588 ins_pipe(pipe_serial);
6589 %}
6590
6591 instruct get_and_addI_no_resAcq(indirect mem, Universe dummy, iRegIorL2I incr)
6592 %{
6593 predicate(n->as_LoadStore()->result_not_used() && needs_acquiring_load_reserved(n));
6594
6595 match(Set dummy (GetAndAddI mem incr));
6596
6597 ins_cost(ALU_COST);
6598
6599 format %{ "get_and_addI_acq [$mem], $incr\t#@get_and_addI_no_resAcq" %}
6600
6601 ins_encode %{
6602 __ atomic_addalw(noreg, $incr$$Register, as_Register($mem$$base));
6603 %}
6604
6605 ins_pipe(pipe_serial);
6606 %}
6607
6608 instruct get_and_addIiAcq(indirect mem, iRegINoSp newval, immIAdd incr)
6609 %{
6610 predicate(needs_acquiring_load_reserved(n));
6611
6612 match(Set newval (GetAndAddI mem incr));
6613
6614 ins_cost(ALU_COST);
6615
6616 format %{ "get_and_addI_acq $newval, [$mem], $incr\t#@get_and_addIiAcq" %}
6617
6618 ins_encode %{
6619 __ atomic_addalw($newval$$Register, $incr$$constant, as_Register($mem$$base));
6620 %}
6621
6622 ins_pipe(pipe_serial);
6623 %}
6624
6625 instruct get_and_addIi_no_resAcq(indirect mem, Universe dummy, immIAdd incr)
6626 %{
6627 predicate(n->as_LoadStore()->result_not_used() && needs_acquiring_load_reserved(n));
6628
6629 match(Set dummy (GetAndAddI mem incr));
6630
6631 ins_cost(ALU_COST);
6632
6633 format %{ "get_and_addI_acq [$mem], $incr\t#@get_and_addIi_no_resAcq" %}
6634
6635 ins_encode %{
6636 __ atomic_addalw(noreg, $incr$$constant, as_Register($mem$$base));
6637 %}
6638
6639 ins_pipe(pipe_serial);
6640 %}
6641
6642 // ============================================================================
6643 // Arithmetic Instructions
6644 //
6645
6646 // Integer Addition
6647
6648 // TODO
6649 // these currently employ operations which do not set CR and hence are
6650 // not flagged as killing CR but we would like to isolate the cases
6651 // where we want to set flags from those where we don't. need to work
6652 // out how to do that.
6653 instruct addI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6654 match(Set dst (AddI src1 src2));
6655
6656 ins_cost(ALU_COST);
6657 format %{ "addw $dst, $src1, $src2\t#@addI_reg_reg" %}
6658
6659 ins_encode %{
6660 __ addw(as_Register($dst$$reg),
6661 as_Register($src1$$reg),
6662 as_Register($src2$$reg));
6663 %}
6664
6665 ins_pipe(ialu_reg_reg);
6666 %}
6667
6668 instruct addI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immIAdd src2) %{
6669 match(Set dst (AddI src1 src2));
6670
6671 ins_cost(ALU_COST);
6672 format %{ "addiw $dst, $src1, $src2\t#@addI_reg_imm" %}
6673
6674 ins_encode %{
6675 __ addiw(as_Register($dst$$reg),
6676 as_Register($src1$$reg),
6677 $src2$$constant);
6678 %}
6679
6680 ins_pipe(ialu_reg_imm);
6681 %}
6682
6683 instruct addI_reg_imm_l2i(iRegINoSp dst, iRegL src1, immIAdd src2) %{
6684 match(Set dst (AddI (ConvL2I src1) src2));
6685
6686 ins_cost(ALU_COST);
6687 format %{ "addiw $dst, $src1, $src2\t#@addI_reg_imm_l2i" %}
6688
6689 ins_encode %{
6690 __ addiw(as_Register($dst$$reg),
6691 as_Register($src1$$reg),
6692 $src2$$constant);
6693 %}
6694
6695 ins_pipe(ialu_reg_imm);
6696 %}
6697
6698 // Pointer Addition
6699 instruct addP_reg_reg(iRegPNoSp dst, iRegP src1, iRegL src2) %{
6700 match(Set dst (AddP src1 src2));
6701
6702 ins_cost(ALU_COST);
6703 format %{ "add $dst, $src1, $src2\t# ptr, #@addP_reg_reg" %}
6704
6705 ins_encode %{
6706 __ add(as_Register($dst$$reg),
6707 as_Register($src1$$reg),
6708 as_Register($src2$$reg));
6709 %}
6710
6711 ins_pipe(ialu_reg_reg);
6712 %}
6713
6714 // If we shift more than 32 bits, we need not convert I2L.
6715 instruct lShiftL_regI_immGE32(iRegLNoSp dst, iRegI src, uimmI6_ge32 scale) %{
6716 match(Set dst (LShiftL (ConvI2L src) scale));
6717 ins_cost(ALU_COST);
6718 format %{ "slli $dst, $src, $scale & 63\t#@lShiftL_regI_immGE32" %}
6719
6720 ins_encode %{
6721 __ slli(as_Register($dst$$reg), as_Register($src$$reg), $scale$$constant & 63);
6722 %}
6723
6724 ins_pipe(ialu_reg_shift);
6725 %}
6726
6727 // Pointer Immediate Addition
6728 // n.b. this needs to be more expensive than using an indirect memory
6729 // operand
6730 instruct addP_reg_imm(iRegPNoSp dst, iRegP src1, immLAdd src2) %{
6731 match(Set dst (AddP src1 src2));
6732 ins_cost(ALU_COST);
6733 format %{ "addi $dst, $src1, $src2\t# ptr, #@addP_reg_imm" %}
6734
6735 ins_encode %{
6736 __ addi(as_Register($dst$$reg),
6737 as_Register($src1$$reg),
6738 $src2$$constant);
6739 %}
6740
6741 ins_pipe(ialu_reg_imm);
6742 %}
6743
6744 // Long Addition
6745 instruct addL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
6746 match(Set dst (AddL src1 src2));
6747 ins_cost(ALU_COST);
6748 format %{ "add $dst, $src1, $src2\t#@addL_reg_reg" %}
6749
6750 ins_encode %{
6751 __ add(as_Register($dst$$reg),
6752 as_Register($src1$$reg),
6753 as_Register($src2$$reg));
6754 %}
6755
6756 ins_pipe(ialu_reg_reg);
6757 %}
6758
6759 // No constant pool entries requiredLong Immediate Addition.
6760 instruct addL_reg_imm(iRegLNoSp dst, iRegL src1, immLAdd src2) %{
6761 match(Set dst (AddL src1 src2));
6762 ins_cost(ALU_COST);
6763 format %{ "addi $dst, $src1, $src2\t#@addL_reg_imm" %}
6764
6765 ins_encode %{
6766 // src2 is imm, so actually call the addi
6767 __ addi(as_Register($dst$$reg),
6768 as_Register($src1$$reg),
6769 $src2$$constant);
6770 %}
6771
6772 ins_pipe(ialu_reg_imm);
6773 %}
6774
6775 // Integer Subtraction
6776 instruct subI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6777 match(Set dst (SubI src1 src2));
6778
6779 ins_cost(ALU_COST);
6780 format %{ "subw $dst, $src1, $src2\t#@subI_reg_reg" %}
6781
6782 ins_encode %{
6783 __ subw(as_Register($dst$$reg),
6784 as_Register($src1$$reg),
6785 as_Register($src2$$reg));
6786 %}
6787
6788 ins_pipe(ialu_reg_reg);
6789 %}
6790
6791 // Immediate Subtraction
6792 instruct subI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immISub src2) %{
6793 match(Set dst (SubI src1 src2));
6794
6795 ins_cost(ALU_COST);
6796 format %{ "addiw $dst, $src1, -$src2\t#@subI_reg_imm" %}
6797
6798 ins_encode %{
6799 // src2 is imm, so actually call the addiw
6800 __ subiw(as_Register($dst$$reg),
6801 as_Register($src1$$reg),
6802 $src2$$constant);
6803 %}
6804
6805 ins_pipe(ialu_reg_imm);
6806 %}
6807
6808 // Long Subtraction
6809 instruct subL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
6810 match(Set dst (SubL src1 src2));
6811 ins_cost(ALU_COST);
6812 format %{ "sub $dst, $src1, $src2\t#@subL_reg_reg" %}
6813
6814 ins_encode %{
6815 __ sub(as_Register($dst$$reg),
6816 as_Register($src1$$reg),
6817 as_Register($src2$$reg));
6818 %}
6819
6820 ins_pipe(ialu_reg_reg);
6821 %}
6822
6823 // No constant pool entries requiredLong Immediate Subtraction.
6824 instruct subL_reg_imm(iRegLNoSp dst, iRegL src1, immLSub src2) %{
6825 match(Set dst (SubL src1 src2));
6826 ins_cost(ALU_COST);
6827 format %{ "addi $dst, $src1, -$src2\t#@subL_reg_imm" %}
6828
6829 ins_encode %{
6830 // src2 is imm, so actually call the addi
6831 __ subi(as_Register($dst$$reg),
6832 as_Register($src1$$reg),
6833 $src2$$constant);
6834 %}
6835
6836 ins_pipe(ialu_reg_imm);
6837 %}
6838
6839 // Integer Negation (special case for sub)
6840
6841 instruct negI_reg(iRegINoSp dst, iRegIorL2I src, immI0 zero) %{
6842 match(Set dst (SubI zero src));
6843 ins_cost(ALU_COST);
6844 format %{ "subw $dst, x0, $src\t# int, #@negI_reg" %}
6845
6846 ins_encode %{
6847 // actually call the subw
6848 __ negw(as_Register($dst$$reg),
6849 as_Register($src$$reg));
6850 %}
6851
6852 ins_pipe(ialu_reg);
6853 %}
6854
6855 // Long Negation
6856
6857 instruct negL_reg(iRegLNoSp dst, iRegL src, immL0 zero) %{
6858 match(Set dst (SubL zero src));
6859 ins_cost(ALU_COST);
6860 format %{ "sub $dst, x0, $src\t# long, #@negL_reg" %}
6861
6862 ins_encode %{
6863 // actually call the sub
6864 __ neg(as_Register($dst$$reg),
6865 as_Register($src$$reg));
6866 %}
6867
6868 ins_pipe(ialu_reg);
6869 %}
6870
6871 // Integer Multiply
6872
6873 instruct mulI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6874 match(Set dst (MulI src1 src2));
6875 ins_cost(IMUL_COST);
6876 format %{ "mulw $dst, $src1, $src2\t#@mulI" %}
6877
6878 //this means 2 word multi, and no sign extend to 64 bits
6879 ins_encode %{
6880 // riscv64 mulw will sign-extension to high 32 bits in dst reg
6881 __ mulw(as_Register($dst$$reg),
6882 as_Register($src1$$reg),
6883 as_Register($src2$$reg));
6884 %}
6885
6886 ins_pipe(imul_reg_reg);
6887 %}
6888
6889 // Long Multiply
6890
6891 instruct mulL(iRegLNoSp dst, iRegL src1, iRegL src2) %{
6892 match(Set dst (MulL src1 src2));
6893 ins_cost(IMUL_COST);
6894 format %{ "mul $dst, $src1, $src2\t#@mulL" %}
6895
6896 ins_encode %{
6897 __ mul(as_Register($dst$$reg),
6898 as_Register($src1$$reg),
6899 as_Register($src2$$reg));
6900 %}
6901
6902 ins_pipe(lmul_reg_reg);
6903 %}
6904
6905 instruct mulHiL_rReg(iRegLNoSp dst, iRegL src1, iRegL src2)
6906 %{
6907 match(Set dst (MulHiL src1 src2));
6908 ins_cost(IMUL_COST);
6909 format %{ "mulh $dst, $src1, $src2\t# mulhi, #@mulHiL_rReg" %}
6910
6911 ins_encode %{
6912 __ mulh(as_Register($dst$$reg),
6913 as_Register($src1$$reg),
6914 as_Register($src2$$reg));
6915 %}
6916
6917 ins_pipe(lmul_reg_reg);
6918 %}
6919
6920 instruct umulHiL_rReg(iRegLNoSp dst, iRegL src1, iRegL src2)
6921 %{
6922 match(Set dst (UMulHiL src1 src2));
6923 ins_cost(IMUL_COST);
6924 format %{ "mulhu $dst, $src1, $src2\t# umulhi, #@umulHiL_rReg" %}
6925
6926 ins_encode %{
6927 __ mulhu(as_Register($dst$$reg),
6928 as_Register($src1$$reg),
6929 as_Register($src2$$reg));
6930 %}
6931
6932 ins_pipe(lmul_reg_reg);
6933 %}
6934
6935 // Integer Divide
6936
6937 instruct divI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6938 match(Set dst (DivI src1 src2));
6939 ins_cost(IDIVSI_COST);
6940 format %{ "divw $dst, $src1, $src2\t#@divI"%}
6941
6942 ins_encode %{
6943 __ divw(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg));
6944 %}
6945 ins_pipe(idiv_reg_reg);
6946 %}
6947
6948 instruct UdivI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6949 match(Set dst (UDivI src1 src2));
6950 ins_cost(IDIVSI_COST);
6951 format %{ "divuw $dst, $src1, $src2\t#@UdivI"%}
6952
6953 ins_encode %{
6954 __ divuw(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg));
6955 %}
6956 ins_pipe(idiv_reg_reg);
6957 %}
6958
6959 instruct signExtract(iRegINoSp dst, iRegIorL2I src1, immI_31 div1, immI_31 div2) %{
6960 match(Set dst (URShiftI (RShiftI src1 div1) div2));
6961 ins_cost(ALU_COST);
6962 format %{ "srliw $dst, $src1, $div1\t# int signExtract, #@signExtract" %}
6963
6964 ins_encode %{
6965 __ srliw(as_Register($dst$$reg), as_Register($src1$$reg), 31);
6966 %}
6967 ins_pipe(ialu_reg_shift);
6968 %}
6969
6970 // Long Divide
6971
6972 instruct divL(iRegLNoSp dst, iRegL src1, iRegL src2) %{
6973 match(Set dst (DivL src1 src2));
6974 ins_cost(IDIVDI_COST);
6975 format %{ "div $dst, $src1, $src2\t#@divL" %}
6976
6977 ins_encode %{
6978 __ div(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg));
6979 %}
6980 ins_pipe(ldiv_reg_reg);
6981 %}
6982
6983 instruct UdivL(iRegLNoSp dst, iRegL src1, iRegL src2) %{
6984 match(Set dst (UDivL src1 src2));
6985 ins_cost(IDIVDI_COST);
6986
6987 format %{ "divu $dst, $src1, $src2\t#@UdivL" %}
6988
6989 ins_encode %{
6990 __ divu(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg));
6991 %}
6992 ins_pipe(ldiv_reg_reg);
6993 %}
6994
6995 instruct signExtractL(iRegLNoSp dst, iRegL src1, immI_63 div1, immI_63 div2) %{
6996 match(Set dst (URShiftL (RShiftL src1 div1) div2));
6997 ins_cost(ALU_COST);
6998 format %{ "srli $dst, $src1, $div1\t# long signExtract, #@signExtractL" %}
6999
7000 ins_encode %{
7001 __ srli(as_Register($dst$$reg), as_Register($src1$$reg), 63);
7002 %}
7003 ins_pipe(ialu_reg_shift);
7004 %}
7005
7006 // Integer Remainder
7007
7008 instruct modI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
7009 match(Set dst (ModI src1 src2));
7010 ins_cost(IDIVSI_COST);
7011 format %{ "remw $dst, $src1, $src2\t#@modI" %}
7012
7013 ins_encode %{
7014 __ remw(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg));
7015 %}
7016 ins_pipe(ialu_reg_reg);
7017 %}
7018
7019 instruct UmodI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
7020 match(Set dst (UModI src1 src2));
7021 ins_cost(IDIVSI_COST);
7022 format %{ "remuw $dst, $src1, $src2\t#@UmodI" %}
7023
7024 ins_encode %{
7025 __ remuw(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg));
7026 %}
7027 ins_pipe(ialu_reg_reg);
7028 %}
7029
7030 // Long Remainder
7031
7032 instruct modL(iRegLNoSp dst, iRegL src1, iRegL src2) %{
7033 match(Set dst (ModL src1 src2));
7034 ins_cost(IDIVDI_COST);
7035 format %{ "rem $dst, $src1, $src2\t#@modL" %}
7036
7037 ins_encode %{
7038 __ rem(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg));
7039 %}
7040 ins_pipe(ialu_reg_reg);
7041 %}
7042
7043 instruct UmodL(iRegLNoSp dst, iRegL src1, iRegL src2) %{
7044 match(Set dst (UModL src1 src2));
7045 ins_cost(IDIVDI_COST);
7046 format %{ "remu $dst, $src1, $src2\t#@UmodL" %}
7047
7048 ins_encode %{
7049 __ remu(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg));
7050 %}
7051 ins_pipe(ialu_reg_reg);
7052 %}
7053
7054 // Integer Shifts
7055
7056 // Shift Left Register
7057 // Only the low 5 bits of src2 are considered for the shift amount, all other bits are ignored.
7058 instruct lShiftI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
7059 match(Set dst (LShiftI src1 src2));
7060 ins_cost(ALU_COST);
7061 format %{ "sllw $dst, $src1, $src2\t#@lShiftI_reg_reg" %}
7062
7063 ins_encode %{
7064 __ sllw(as_Register($dst$$reg),
7065 as_Register($src1$$reg),
7066 as_Register($src2$$reg));
7067 %}
7068
7069 ins_pipe(ialu_reg_reg_vshift);
7070 %}
7071
7072 // Shift Left Immediate
7073 instruct lShiftI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immI src2) %{
7074 match(Set dst (LShiftI src1 src2));
7075 ins_cost(ALU_COST);
7076 format %{ "slliw $dst, $src1, ($src2 & 0x1f)\t#@lShiftI_reg_imm" %}
7077
7078 ins_encode %{
7079 // the shift amount is encoded in the lower
7080 // 5 bits of the I-immediate field for RV32I
7081 __ slliw(as_Register($dst$$reg),
7082 as_Register($src1$$reg),
7083 (unsigned) $src2$$constant & 0x1f);
7084 %}
7085
7086 ins_pipe(ialu_reg_shift);
7087 %}
7088
7089 // Shift Right Logical Register
7090 // Only the low 5 bits of src2 are considered for the shift amount, all other bits are ignored.
7091 instruct urShiftI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
7092 match(Set dst (URShiftI src1 src2));
7093 ins_cost(ALU_COST);
7094 format %{ "srlw $dst, $src1, $src2\t#@urShiftI_reg_reg" %}
7095
7096 ins_encode %{
7097 __ srlw(as_Register($dst$$reg),
7098 as_Register($src1$$reg),
7099 as_Register($src2$$reg));
7100 %}
7101
7102 ins_pipe(ialu_reg_reg_vshift);
7103 %}
7104
7105 // Shift Right Logical Immediate
7106 instruct urShiftI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immI src2) %{
7107 match(Set dst (URShiftI src1 src2));
7108 ins_cost(ALU_COST);
7109 format %{ "srliw $dst, $src1, ($src2 & 0x1f)\t#@urShiftI_reg_imm" %}
7110
7111 ins_encode %{
7112 // the shift amount is encoded in the lower
7113 // 6 bits of the I-immediate field for RV64I
7114 __ srliw(as_Register($dst$$reg),
7115 as_Register($src1$$reg),
7116 (unsigned) $src2$$constant & 0x1f);
7117 %}
7118
7119 ins_pipe(ialu_reg_shift);
7120 %}
7121
7122 // Shift Right Arithmetic Register
7123 // Only the low 5 bits of src2 are considered for the shift amount, all other bits are ignored.
7124 instruct rShiftI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
7125 match(Set dst (RShiftI src1 src2));
7126 ins_cost(ALU_COST);
7127 format %{ "sraw $dst, $src1, $src2\t#@rShiftI_reg_reg" %}
7128
7129 ins_encode %{
7130 // riscv will sign-ext dst high 32 bits
7131 __ sraw(as_Register($dst$$reg),
7132 as_Register($src1$$reg),
7133 as_Register($src2$$reg));
7134 %}
7135
7136 ins_pipe(ialu_reg_reg_vshift);
7137 %}
7138
7139 // Shift Right Arithmetic Immediate
7140 instruct rShiftI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immI src2) %{
7141 match(Set dst (RShiftI src1 src2));
7142 ins_cost(ALU_COST);
7143 format %{ "sraiw $dst, $src1, ($src2 & 0x1f)\t#@rShiftI_reg_imm" %}
7144
7145 ins_encode %{
7146 // riscv will sign-ext dst high 32 bits
7147 __ sraiw(as_Register($dst$$reg),
7148 as_Register($src1$$reg),
7149 (unsigned) $src2$$constant & 0x1f);
7150 %}
7151
7152 ins_pipe(ialu_reg_shift);
7153 %}
7154
7155 // Long Shifts
7156
7157 // Shift Left Register
7158 // Only the low 6 bits of src2 are considered for the shift amount, all other bits are ignored.
7159 instruct lShiftL_reg_reg(iRegLNoSp dst, iRegL src1, iRegIorL2I src2) %{
7160 match(Set dst (LShiftL src1 src2));
7161
7162 ins_cost(ALU_COST);
7163 format %{ "sll $dst, $src1, $src2\t#@lShiftL_reg_reg" %}
7164
7165 ins_encode %{
7166 __ sll(as_Register($dst$$reg),
7167 as_Register($src1$$reg),
7168 as_Register($src2$$reg));
7169 %}
7170
7171 ins_pipe(ialu_reg_reg_vshift);
7172 %}
7173
7174 // Shift Left Immediate
7175 instruct lShiftL_reg_imm(iRegLNoSp dst, iRegL src1, immI src2) %{
7176 match(Set dst (LShiftL src1 src2));
7177
7178 ins_cost(ALU_COST);
7179 format %{ "slli $dst, $src1, ($src2 & 0x3f)\t#@lShiftL_reg_imm" %}
7180
7181 ins_encode %{
7182 // the shift amount is encoded in the lower
7183 // 6 bits of the I-immediate field for RV64I
7184 __ slli(as_Register($dst$$reg),
7185 as_Register($src1$$reg),
7186 (unsigned) $src2$$constant & 0x3f);
7187 %}
7188
7189 ins_pipe(ialu_reg_shift);
7190 %}
7191
7192 // Shift Right Logical Register
7193 // Only the low 6 bits of src2 are considered for the shift amount, all other bits are ignored.
7194 instruct urShiftL_reg_reg(iRegLNoSp dst, iRegL src1, iRegIorL2I src2) %{
7195 match(Set dst (URShiftL src1 src2));
7196
7197 ins_cost(ALU_COST);
7198 format %{ "srl $dst, $src1, $src2\t#@urShiftL_reg_reg" %}
7199
7200 ins_encode %{
7201 __ srl(as_Register($dst$$reg),
7202 as_Register($src1$$reg),
7203 as_Register($src2$$reg));
7204 %}
7205
7206 ins_pipe(ialu_reg_reg_vshift);
7207 %}
7208
7209 // Shift Right Logical Immediate
7210 instruct urShiftL_reg_imm(iRegLNoSp dst, iRegL src1, immI src2) %{
7211 match(Set dst (URShiftL src1 src2));
7212
7213 ins_cost(ALU_COST);
7214 format %{ "srli $dst, $src1, ($src2 & 0x3f)\t#@urShiftL_reg_imm" %}
7215
7216 ins_encode %{
7217 // the shift amount is encoded in the lower
7218 // 6 bits of the I-immediate field for RV64I
7219 __ srli(as_Register($dst$$reg),
7220 as_Register($src1$$reg),
7221 (unsigned) $src2$$constant & 0x3f);
7222 %}
7223
7224 ins_pipe(ialu_reg_shift);
7225 %}
7226
7227 // A special-case pattern for card table stores.
7228 instruct urShiftP_reg_imm(iRegLNoSp dst, iRegP src1, immI src2) %{
7229 match(Set dst (URShiftL (CastP2X src1) src2));
7230
7231 ins_cost(ALU_COST);
7232 format %{ "srli $dst, p2x($src1), ($src2 & 0x3f)\t#@urShiftP_reg_imm" %}
7233
7234 ins_encode %{
7235 // the shift amount is encoded in the lower
7236 // 6 bits of the I-immediate field for RV64I
7237 __ srli(as_Register($dst$$reg),
7238 as_Register($src1$$reg),
7239 (unsigned) $src2$$constant & 0x3f);
7240 %}
7241
7242 ins_pipe(ialu_reg_shift);
7243 %}
7244
7245 // Shift Right Arithmetic Register
7246 // Only the low 6 bits of src2 are considered for the shift amount, all other bits are ignored.
7247 instruct rShiftL_reg_reg(iRegLNoSp dst, iRegL src1, iRegIorL2I src2) %{
7248 match(Set dst (RShiftL src1 src2));
7249
7250 ins_cost(ALU_COST);
7251 format %{ "sra $dst, $src1, $src2\t#@rShiftL_reg_reg" %}
7252
7253 ins_encode %{
7254 __ sra(as_Register($dst$$reg),
7255 as_Register($src1$$reg),
7256 as_Register($src2$$reg));
7257 %}
7258
7259 ins_pipe(ialu_reg_reg_vshift);
7260 %}
7261
7262 // Shift Right Arithmetic Immediate
7263 instruct rShiftL_reg_imm(iRegLNoSp dst, iRegL src1, immI src2) %{
7264 match(Set dst (RShiftL src1 src2));
7265
7266 ins_cost(ALU_COST);
7267 format %{ "srai $dst, $src1, ($src2 & 0x3f)\t#@rShiftL_reg_imm" %}
7268
7269 ins_encode %{
7270 // the shift amount is encoded in the lower
7271 // 6 bits of the I-immediate field for RV64I
7272 __ srai(as_Register($dst$$reg),
7273 as_Register($src1$$reg),
7274 (unsigned) $src2$$constant & 0x3f);
7275 %}
7276
7277 ins_pipe(ialu_reg_shift);
7278 %}
7279
7280 instruct regI_not_reg(iRegINoSp dst, iRegI src1, immI_M1 m1) %{
7281 match(Set dst (XorI src1 m1));
7282 ins_cost(ALU_COST);
7283 format %{ "xori $dst, $src1, -1\t#@regI_not_reg" %}
7284
7285 ins_encode %{
7286 __ xori(as_Register($dst$$reg), as_Register($src1$$reg), -1);
7287 %}
7288
7289 ins_pipe(ialu_reg_imm);
7290 %}
7291
7292 instruct regL_not_reg(iRegLNoSp dst, iRegL src1, immL_M1 m1) %{
7293 match(Set dst (XorL src1 m1));
7294 ins_cost(ALU_COST);
7295 format %{ "xori $dst, $src1, -1\t#@regL_not_reg" %}
7296
7297 ins_encode %{
7298 __ xori(as_Register($dst$$reg), as_Register($src1$$reg), -1);
7299 %}
7300
7301 ins_pipe(ialu_reg_imm);
7302 %}
7303
7304
7305 // ============================================================================
7306 // Floating Point Arithmetic Instructions
7307
7308 instruct addF_reg_reg(fRegF dst, fRegF src1, fRegF src2) %{
7309 match(Set dst (AddF src1 src2));
7310
7311 ins_cost(DEFAULT_COST * 5);
7312 format %{ "fadd.s $dst, $src1, $src2\t#@addF_reg_reg" %}
7313
7314 ins_encode %{
7315 __ fadd_s(as_FloatRegister($dst$$reg),
7316 as_FloatRegister($src1$$reg),
7317 as_FloatRegister($src2$$reg));
7318 %}
7319
7320 ins_pipe(fp_dop_reg_reg_s);
7321 %}
7322
7323 instruct addD_reg_reg(fRegD dst, fRegD src1, fRegD src2) %{
7324 match(Set dst (AddD src1 src2));
7325
7326 ins_cost(DEFAULT_COST * 5);
7327 format %{ "fadd.d $dst, $src1, $src2\t#@addD_reg_reg" %}
7328
7329 ins_encode %{
7330 __ fadd_d(as_FloatRegister($dst$$reg),
7331 as_FloatRegister($src1$$reg),
7332 as_FloatRegister($src2$$reg));
7333 %}
7334
7335 ins_pipe(fp_dop_reg_reg_d);
7336 %}
7337
7338 instruct subF_reg_reg(fRegF dst, fRegF src1, fRegF src2) %{
7339 match(Set dst (SubF src1 src2));
7340
7341 ins_cost(DEFAULT_COST * 5);
7342 format %{ "fsub.s $dst, $src1, $src2\t#@subF_reg_reg" %}
7343
7344 ins_encode %{
7345 __ fsub_s(as_FloatRegister($dst$$reg),
7346 as_FloatRegister($src1$$reg),
7347 as_FloatRegister($src2$$reg));
7348 %}
7349
7350 ins_pipe(fp_dop_reg_reg_s);
7351 %}
7352
7353 instruct subD_reg_reg(fRegD dst, fRegD src1, fRegD src2) %{
7354 match(Set dst (SubD src1 src2));
7355
7356 ins_cost(DEFAULT_COST * 5);
7357 format %{ "fsub.d $dst, $src1, $src2\t#@subD_reg_reg" %}
7358
7359 ins_encode %{
7360 __ fsub_d(as_FloatRegister($dst$$reg),
7361 as_FloatRegister($src1$$reg),
7362 as_FloatRegister($src2$$reg));
7363 %}
7364
7365 ins_pipe(fp_dop_reg_reg_d);
7366 %}
7367
7368 instruct mulF_reg_reg(fRegF dst, fRegF src1, fRegF src2) %{
7369 match(Set dst (MulF src1 src2));
7370
7371 ins_cost(FMUL_SINGLE_COST);
7372 format %{ "fmul.s $dst, $src1, $src2\t#@mulF_reg_reg" %}
7373
7374 ins_encode %{
7375 __ fmul_s(as_FloatRegister($dst$$reg),
7376 as_FloatRegister($src1$$reg),
7377 as_FloatRegister($src2$$reg));
7378 %}
7379
7380 ins_pipe(fp_dop_reg_reg_s);
7381 %}
7382
7383 instruct mulD_reg_reg(fRegD dst, fRegD src1, fRegD src2) %{
7384 match(Set dst (MulD src1 src2));
7385
7386 ins_cost(FMUL_DOUBLE_COST);
7387 format %{ "fmul.d $dst, $src1, $src2\t#@mulD_reg_reg" %}
7388
7389 ins_encode %{
7390 __ fmul_d(as_FloatRegister($dst$$reg),
7391 as_FloatRegister($src1$$reg),
7392 as_FloatRegister($src2$$reg));
7393 %}
7394
7395 ins_pipe(fp_dop_reg_reg_d);
7396 %}
7397
7398 // src1 * src2 + src3
7399 instruct maddF_reg_reg(fRegF dst, fRegF src1, fRegF src2, fRegF src3) %{
7400 match(Set dst (FmaF src3 (Binary src1 src2)));
7401
7402 ins_cost(FMUL_SINGLE_COST);
7403 format %{ "fmadd.s $dst, $src1, $src2, $src3\t#@maddF_reg_reg" %}
7404
7405 ins_encode %{
7406 assert(UseFMA, "Needs FMA instructions support.");
7407 __ fmadd_s(as_FloatRegister($dst$$reg),
7408 as_FloatRegister($src1$$reg),
7409 as_FloatRegister($src2$$reg),
7410 as_FloatRegister($src3$$reg));
7411 %}
7412
7413 ins_pipe(pipe_class_default);
7414 %}
7415
7416 // src1 * src2 + src3
7417 instruct maddD_reg_reg(fRegD dst, fRegD src1, fRegD src2, fRegD src3) %{
7418 match(Set dst (FmaD src3 (Binary src1 src2)));
7419
7420 ins_cost(FMUL_DOUBLE_COST);
7421 format %{ "fmadd.d $dst, $src1, $src2, $src3\t#@maddD_reg_reg" %}
7422
7423 ins_encode %{
7424 assert(UseFMA, "Needs FMA instructions support.");
7425 __ fmadd_d(as_FloatRegister($dst$$reg),
7426 as_FloatRegister($src1$$reg),
7427 as_FloatRegister($src2$$reg),
7428 as_FloatRegister($src3$$reg));
7429 %}
7430
7431 ins_pipe(pipe_class_default);
7432 %}
7433
7434 // src1 * src2 - src3
7435 instruct msubF_reg_reg(fRegF dst, fRegF src1, fRegF src2, fRegF src3) %{
7436 match(Set dst (FmaF (NegF src3) (Binary src1 src2)));
7437
7438 ins_cost(FMUL_SINGLE_COST);
7439 format %{ "fmsub.s $dst, $src1, $src2, $src3\t#@msubF_reg_reg" %}
7440
7441 ins_encode %{
7442 assert(UseFMA, "Needs FMA instructions support.");
7443 __ fmsub_s(as_FloatRegister($dst$$reg),
7444 as_FloatRegister($src1$$reg),
7445 as_FloatRegister($src2$$reg),
7446 as_FloatRegister($src3$$reg));
7447 %}
7448
7449 ins_pipe(pipe_class_default);
7450 %}
7451
7452 // src1 * src2 - src3
7453 instruct msubD_reg_reg(fRegD dst, fRegD src1, fRegD src2, fRegD src3) %{
7454 match(Set dst (FmaD (NegD src3) (Binary src1 src2)));
7455
7456 ins_cost(FMUL_DOUBLE_COST);
7457 format %{ "fmsub.d $dst, $src1, $src2, $src3\t#@msubD_reg_reg" %}
7458
7459 ins_encode %{
7460 assert(UseFMA, "Needs FMA instructions support.");
7461 __ fmsub_d(as_FloatRegister($dst$$reg),
7462 as_FloatRegister($src1$$reg),
7463 as_FloatRegister($src2$$reg),
7464 as_FloatRegister($src3$$reg));
7465 %}
7466
7467 ins_pipe(pipe_class_default);
7468 %}
7469
7470 // src1 * (-src2) + src3
7471 // "(-src1) * src2 + src3" has been idealized to "src2 * (-src1) + src3"
7472 instruct nmsubF_reg_reg(fRegF dst, fRegF src1, fRegF src2, fRegF src3) %{
7473 match(Set dst (FmaF src3 (Binary src1 (NegF src2))));
7474
7475 ins_cost(FMUL_SINGLE_COST);
7476 format %{ "fnmsub.s $dst, $src1, $src2, $src3\t#@nmsubF_reg_reg" %}
7477
7478 ins_encode %{
7479 assert(UseFMA, "Needs FMA instructions support.");
7480 __ fnmsub_s(as_FloatRegister($dst$$reg),
7481 as_FloatRegister($src1$$reg),
7482 as_FloatRegister($src2$$reg),
7483 as_FloatRegister($src3$$reg));
7484 %}
7485
7486 ins_pipe(pipe_class_default);
7487 %}
7488
7489 // src1 * (-src2) + src3
7490 // "(-src1) * src2 + src3" has been idealized to "src2 * (-src1) + src3"
7491 instruct nmsubD_reg_reg(fRegD dst, fRegD src1, fRegD src2, fRegD src3) %{
7492 match(Set dst (FmaD src3 (Binary src1 (NegD src2))));
7493
7494 ins_cost(FMUL_DOUBLE_COST);
7495 format %{ "fnmsub.d $dst, $src1, $src2, $src3\t#@nmsubD_reg_reg" %}
7496
7497 ins_encode %{
7498 assert(UseFMA, "Needs FMA instructions support.");
7499 __ fnmsub_d(as_FloatRegister($dst$$reg),
7500 as_FloatRegister($src1$$reg),
7501 as_FloatRegister($src2$$reg),
7502 as_FloatRegister($src3$$reg));
7503 %}
7504
7505 ins_pipe(pipe_class_default);
7506 %}
7507
7508 // src1 * (-src2) - src3
7509 // "(-src1) * src2 - src3" has been idealized to "src2 * (-src1) - src3"
7510 instruct nmaddF_reg_reg(fRegF dst, fRegF src1, fRegF src2, fRegF src3) %{
7511 match(Set dst (FmaF (NegF src3) (Binary src1 (NegF src2))));
7512
7513 ins_cost(FMUL_SINGLE_COST);
7514 format %{ "fnmadd.s $dst, $src1, $src2, $src3\t#@nmaddF_reg_reg" %}
7515
7516 ins_encode %{
7517 assert(UseFMA, "Needs FMA instructions support.");
7518 __ fnmadd_s(as_FloatRegister($dst$$reg),
7519 as_FloatRegister($src1$$reg),
7520 as_FloatRegister($src2$$reg),
7521 as_FloatRegister($src3$$reg));
7522 %}
7523
7524 ins_pipe(pipe_class_default);
7525 %}
7526
7527 // src1 * (-src2) - src3
7528 // "(-src1) * src2 - src3" has been idealized to "src2 * (-src1) - src3"
7529 instruct nmaddD_reg_reg(fRegD dst, fRegD src1, fRegD src2, fRegD src3) %{
7530 match(Set dst (FmaD (NegD src3) (Binary src1 (NegD src2))));
7531
7532 ins_cost(FMUL_DOUBLE_COST);
7533 format %{ "fnmadd.d $dst, $src1, $src2, $src3\t#@nmaddD_reg_reg" %}
7534
7535 ins_encode %{
7536 assert(UseFMA, "Needs FMA instructions support.");
7537 __ fnmadd_d(as_FloatRegister($dst$$reg),
7538 as_FloatRegister($src1$$reg),
7539 as_FloatRegister($src2$$reg),
7540 as_FloatRegister($src3$$reg));
7541 %}
7542
7543 ins_pipe(pipe_class_default);
7544 %}
7545
7546 // Math.max(FF)F
7547 instruct maxF_reg_reg(fRegF dst, fRegF src1, fRegF src2, rFlagsReg cr) %{
7548 predicate(!UseZfa);
7549 match(Set dst (MaxF src1 src2));
7550 effect(KILL cr);
7551
7552 format %{ "maxF $dst, $src1, $src2" %}
7553
7554 ins_encode %{
7555 __ minmax_fp(as_FloatRegister($dst$$reg),
7556 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg),
7557 __ FLOAT_TYPE::single_precision, false /* is_min */);
7558 %}
7559
7560 ins_pipe(pipe_class_default);
7561 %}
7562
7563 instruct maxF_reg_reg_zfa(fRegF dst, fRegF src1, fRegF src2) %{
7564 predicate(UseZfa);
7565 match(Set dst (MaxF src1 src2));
7566
7567 format %{ "maxF $dst, $src1, $src2" %}
7568
7569 ins_encode %{
7570 __ fmaxm_s(as_FloatRegister($dst$$reg),
7571 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
7572 %}
7573
7574 ins_pipe(pipe_class_default);
7575 %}
7576
7577 // Math.min(FF)F
7578 instruct minF_reg_reg(fRegF dst, fRegF src1, fRegF src2, rFlagsReg cr) %{
7579 predicate(!UseZfa);
7580 match(Set dst (MinF src1 src2));
7581 effect(KILL cr);
7582
7583 format %{ "minF $dst, $src1, $src2" %}
7584
7585 ins_encode %{
7586 __ minmax_fp(as_FloatRegister($dst$$reg),
7587 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg),
7588 __ FLOAT_TYPE::single_precision, true /* is_min */);
7589 %}
7590
7591 ins_pipe(pipe_class_default);
7592 %}
7593
7594 instruct minF_reg_reg_zfa(fRegF dst, fRegF src1, fRegF src2) %{
7595 predicate(UseZfa);
7596 match(Set dst (MinF src1 src2));
7597
7598 format %{ "minF $dst, $src1, $src2" %}
7599
7600 ins_encode %{
7601 __ fminm_s(as_FloatRegister($dst$$reg),
7602 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
7603 %}
7604
7605 ins_pipe(pipe_class_default);
7606 %}
7607
7608 // Math.max(DD)D
7609 instruct maxD_reg_reg(fRegD dst, fRegD src1, fRegD src2, rFlagsReg cr) %{
7610 predicate(!UseZfa);
7611 match(Set dst (MaxD src1 src2));
7612 effect(KILL cr);
7613
7614 format %{ "maxD $dst, $src1, $src2" %}
7615
7616 ins_encode %{
7617 __ minmax_fp(as_FloatRegister($dst$$reg),
7618 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg),
7619 __ FLOAT_TYPE::double_precision, false /* is_min */);
7620 %}
7621
7622 ins_pipe(pipe_class_default);
7623 %}
7624
7625 instruct maxD_reg_reg_zfa(fRegD dst, fRegD src1, fRegD src2) %{
7626 predicate(UseZfa);
7627 match(Set dst (MaxD src1 src2));
7628
7629 format %{ "maxD $dst, $src1, $src2" %}
7630
7631 ins_encode %{
7632 __ fmaxm_d(as_FloatRegister($dst$$reg),
7633 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
7634 %}
7635
7636 ins_pipe(pipe_class_default);
7637 %}
7638
7639 // Math.min(DD)D
7640 instruct minD_reg_reg(fRegD dst, fRegD src1, fRegD src2, rFlagsReg cr) %{
7641 predicate(!UseZfa);
7642 match(Set dst (MinD src1 src2));
7643 effect(KILL cr);
7644
7645 format %{ "minD $dst, $src1, $src2" %}
7646
7647 ins_encode %{
7648 __ minmax_fp(as_FloatRegister($dst$$reg),
7649 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg),
7650 __ FLOAT_TYPE::double_precision, true /* is_min */);
7651 %}
7652
7653 ins_pipe(pipe_class_default);
7654 %}
7655
7656 instruct minD_reg_reg_zfa(fRegD dst, fRegD src1, fRegD src2) %{
7657 predicate(UseZfa);
7658 match(Set dst (MinD src1 src2));
7659
7660 format %{ "minD $dst, $src1, $src2" %}
7661
7662 ins_encode %{
7663 __ fminm_d(as_FloatRegister($dst$$reg),
7664 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
7665 %}
7666
7667 ins_pipe(pipe_class_default);
7668 %}
7669
7670 // Float.isInfinite
7671 instruct isInfiniteF_reg_reg(iRegINoSp dst, fRegF src)
7672 %{
7673 match(Set dst (IsInfiniteF src));
7674
7675 format %{ "isInfinite $dst, $src" %}
7676 ins_encode %{
7677 __ fclass_s(as_Register($dst$$reg), as_FloatRegister($src$$reg));
7678 __ andi(as_Register($dst$$reg), as_Register($dst$$reg), Assembler::FClassBits::inf);
7679 __ slt(as_Register($dst$$reg), zr, as_Register($dst$$reg));
7680 %}
7681
7682 ins_pipe(pipe_class_default);
7683 %}
7684
7685 // Double.isInfinite
7686 instruct isInfiniteD_reg_reg(iRegINoSp dst, fRegD src)
7687 %{
7688 match(Set dst (IsInfiniteD src));
7689
7690 format %{ "isInfinite $dst, $src" %}
7691 ins_encode %{
7692 __ fclass_d(as_Register($dst$$reg), as_FloatRegister($src$$reg));
7693 __ andi(as_Register($dst$$reg), as_Register($dst$$reg), Assembler::FClassBits::inf);
7694 __ slt(as_Register($dst$$reg), zr, as_Register($dst$$reg));
7695 %}
7696
7697 ins_pipe(pipe_class_default);
7698 %}
7699
7700 // Float.isFinite
7701 instruct isFiniteF_reg_reg(iRegINoSp dst, fRegF src)
7702 %{
7703 match(Set dst (IsFiniteF src));
7704
7705 format %{ "isFinite $dst, $src" %}
7706 ins_encode %{
7707 __ fclass_s(as_Register($dst$$reg), as_FloatRegister($src$$reg));
7708 __ andi(as_Register($dst$$reg), as_Register($dst$$reg), Assembler::FClassBits::finite);
7709 __ slt(as_Register($dst$$reg), zr, as_Register($dst$$reg));
7710 %}
7711
7712 ins_pipe(pipe_class_default);
7713 %}
7714
7715 // Double.isFinite
7716 instruct isFiniteD_reg_reg(iRegINoSp dst, fRegD src)
7717 %{
7718 match(Set dst (IsFiniteD src));
7719
7720 format %{ "isFinite $dst, $src" %}
7721 ins_encode %{
7722 __ fclass_d(as_Register($dst$$reg), as_FloatRegister($src$$reg));
7723 __ andi(as_Register($dst$$reg), as_Register($dst$$reg), Assembler::FClassBits::finite);
7724 __ slt(as_Register($dst$$reg), zr, as_Register($dst$$reg));
7725 %}
7726
7727 ins_pipe(pipe_class_default);
7728 %}
7729
7730 instruct divF_reg_reg(fRegF dst, fRegF src1, fRegF src2) %{
7731 match(Set dst (DivF src1 src2));
7732
7733 ins_cost(FDIV_COST);
7734 format %{ "fdiv.s $dst, $src1, $src2\t#@divF_reg_reg" %}
7735
7736 ins_encode %{
7737 __ fdiv_s(as_FloatRegister($dst$$reg),
7738 as_FloatRegister($src1$$reg),
7739 as_FloatRegister($src2$$reg));
7740 %}
7741
7742 ins_pipe(fp_div_s);
7743 %}
7744
7745 instruct divD_reg_reg(fRegD dst, fRegD src1, fRegD src2) %{
7746 match(Set dst (DivD src1 src2));
7747
7748 ins_cost(FDIV_COST);
7749 format %{ "fdiv.d $dst, $src1, $src2\t#@divD_reg_reg" %}
7750
7751 ins_encode %{
7752 __ fdiv_d(as_FloatRegister($dst$$reg),
7753 as_FloatRegister($src1$$reg),
7754 as_FloatRegister($src2$$reg));
7755 %}
7756
7757 ins_pipe(fp_div_d);
7758 %}
7759
7760 instruct negF_reg_reg(fRegF dst, fRegF src) %{
7761 match(Set dst (NegF src));
7762
7763 ins_cost(XFER_COST);
7764 format %{ "fsgnjn.s $dst, $src, $src\t#@negF_reg_reg" %}
7765
7766 ins_encode %{
7767 __ fneg_s(as_FloatRegister($dst$$reg),
7768 as_FloatRegister($src$$reg));
7769 %}
7770
7771 ins_pipe(fp_uop_s);
7772 %}
7773
7774 instruct negD_reg_reg(fRegD dst, fRegD src) %{
7775 match(Set dst (NegD src));
7776
7777 ins_cost(XFER_COST);
7778 format %{ "fsgnjn.d $dst, $src, $src\t#@negD_reg_reg" %}
7779
7780 ins_encode %{
7781 __ fneg_d(as_FloatRegister($dst$$reg),
7782 as_FloatRegister($src$$reg));
7783 %}
7784
7785 ins_pipe(fp_uop_d);
7786 %}
7787
7788 instruct absI_reg(iRegINoSp dst, iRegIorL2I src) %{
7789 match(Set dst (AbsI src));
7790
7791 ins_cost(ALU_COST * 3);
7792 format %{
7793 "sraiw t0, $src, 0x1f\n\t"
7794 "addw $dst, $src, t0\n\t"
7795 "xorr $dst, $dst, t0\t#@absI_reg"
7796 %}
7797
7798 ins_encode %{
7799 __ sraiw(t0, as_Register($src$$reg), 0x1f);
7800 __ addw(as_Register($dst$$reg), as_Register($src$$reg), t0);
7801 __ xorr(as_Register($dst$$reg), as_Register($dst$$reg), t0);
7802 %}
7803
7804 ins_pipe(pipe_class_default);
7805 %}
7806
7807 instruct absL_reg(iRegLNoSp dst, iRegL src) %{
7808 match(Set dst (AbsL src));
7809
7810 ins_cost(ALU_COST * 3);
7811 format %{
7812 "srai t0, $src, 0x3f\n\t"
7813 "add $dst, $src, t0\n\t"
7814 "xorr $dst, $dst, t0\t#@absL_reg"
7815 %}
7816
7817 ins_encode %{
7818 __ srai(t0, as_Register($src$$reg), 0x3f);
7819 __ add(as_Register($dst$$reg), as_Register($src$$reg), t0);
7820 __ xorr(as_Register($dst$$reg), as_Register($dst$$reg), t0);
7821 %}
7822
7823 ins_pipe(pipe_class_default);
7824 %}
7825
7826 instruct absF_reg(fRegF dst, fRegF src) %{
7827 match(Set dst (AbsF src));
7828
7829 ins_cost(XFER_COST);
7830 format %{ "fsgnjx.s $dst, $src, $src\t#@absF_reg" %}
7831 ins_encode %{
7832 __ fabs_s(as_FloatRegister($dst$$reg),
7833 as_FloatRegister($src$$reg));
7834 %}
7835
7836 ins_pipe(fp_uop_s);
7837 %}
7838
7839 instruct absD_reg(fRegD dst, fRegD src) %{
7840 match(Set dst (AbsD src));
7841
7842 ins_cost(XFER_COST);
7843 format %{ "fsgnjx.d $dst, $src, $src\t#@absD_reg" %}
7844 ins_encode %{
7845 __ fabs_d(as_FloatRegister($dst$$reg),
7846 as_FloatRegister($src$$reg));
7847 %}
7848
7849 ins_pipe(fp_uop_d);
7850 %}
7851
7852 instruct sqrtF_reg(fRegF dst, fRegF src) %{
7853 match(Set dst (SqrtF src));
7854
7855 ins_cost(FSQRT_COST);
7856 format %{ "fsqrt.s $dst, $src\t#@sqrtF_reg" %}
7857 ins_encode %{
7858 __ fsqrt_s(as_FloatRegister($dst$$reg),
7859 as_FloatRegister($src$$reg));
7860 %}
7861
7862 ins_pipe(fp_sqrt_s);
7863 %}
7864
7865 instruct sqrtD_reg(fRegD dst, fRegD src) %{
7866 match(Set dst (SqrtD src));
7867
7868 ins_cost(FSQRT_COST);
7869 format %{ "fsqrt.d $dst, $src\t#@sqrtD_reg" %}
7870 ins_encode %{
7871 __ fsqrt_d(as_FloatRegister($dst$$reg),
7872 as_FloatRegister($src$$reg));
7873 %}
7874
7875 ins_pipe(fp_sqrt_d);
7876 %}
7877
7878 // Round Instruction
7879 instruct roundD_reg(fRegD dst, fRegD src, immI rmode, iRegLNoSp tmp1, iRegLNoSp tmp2, iRegLNoSp tmp3) %{
7880 match(Set dst (RoundDoubleMode src rmode));
7881 ins_cost(2 * XFER_COST + BRANCH_COST);
7882 effect(TEMP_DEF dst, TEMP tmp1, TEMP tmp2, TEMP tmp3);
7883
7884 format %{ "RoundDoubleMode $src, $rmode" %}
7885 ins_encode %{
7886 __ round_double_mode(as_FloatRegister($dst$$reg),
7887 as_FloatRegister($src$$reg), $rmode$$constant, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
7888 %}
7889 ins_pipe(pipe_class_default);
7890 %}
7891
7892 // Copysign and signum intrinsics
7893
7894 instruct copySignD_reg(fRegD dst, fRegD src1, fRegD src2, immD zero) %{
7895 match(Set dst (CopySignD src1 (Binary src2 zero)));
7896 format %{ "CopySignD $dst $src1 $src2" %}
7897 ins_encode %{
7898 FloatRegister dst = as_FloatRegister($dst$$reg),
7899 src1 = as_FloatRegister($src1$$reg),
7900 src2 = as_FloatRegister($src2$$reg);
7901 __ fsgnj_d(dst, src1, src2);
7902 %}
7903 ins_pipe(fp_dop_reg_reg_d);
7904 %}
7905
7906 instruct copySignF_reg(fRegF dst, fRegF src1, fRegF src2) %{
7907 match(Set dst (CopySignF src1 src2));
7908 format %{ "CopySignF $dst $src1 $src2" %}
7909 ins_encode %{
7910 FloatRegister dst = as_FloatRegister($dst$$reg),
7911 src1 = as_FloatRegister($src1$$reg),
7912 src2 = as_FloatRegister($src2$$reg);
7913 __ fsgnj_s(dst, src1, src2);
7914 %}
7915 ins_pipe(fp_dop_reg_reg_s);
7916 %}
7917
7918 instruct signumD_reg(fRegD dst, immD zero, fRegD one) %{
7919 match(Set dst (SignumD dst (Binary zero one)));
7920 format %{ "signumD $dst, $dst" %}
7921 ins_encode %{
7922 __ signum_fp(as_FloatRegister($dst$$reg), as_FloatRegister($one$$reg), true /* is_double */);
7923 %}
7924 ins_pipe(pipe_class_default);
7925 %}
7926
7927 instruct signumF_reg(fRegF dst, immF zero, fRegF one) %{
7928 match(Set dst (SignumF dst (Binary zero one)));
7929 format %{ "signumF $dst, $dst" %}
7930 ins_encode %{
7931 __ signum_fp(as_FloatRegister($dst$$reg), as_FloatRegister($one$$reg), false /* is_double */);
7932 %}
7933 ins_pipe(pipe_class_default);
7934 %}
7935
7936 // Arithmetic Instructions End
7937
7938 // ============================================================================
7939 // Logical Instructions
7940
7941 // Register And
7942 instruct andI_reg_reg(iRegINoSp dst, iRegI src1, iRegI src2) %{
7943 match(Set dst (AndI src1 src2));
7944
7945 format %{ "andr $dst, $src1, $src2\t#@andI_reg_reg" %}
7946
7947 ins_cost(ALU_COST);
7948 ins_encode %{
7949 __ andr(as_Register($dst$$reg),
7950 as_Register($src1$$reg),
7951 as_Register($src2$$reg));
7952 %}
7953
7954 ins_pipe(ialu_reg_reg);
7955 %}
7956
7957 // Immediate And
7958 instruct andI_reg_imm(iRegINoSp dst, iRegI src1, immIAdd src2) %{
7959 match(Set dst (AndI src1 src2));
7960
7961 format %{ "andi $dst, $src1, $src2\t#@andI_reg_imm" %}
7962
7963 ins_cost(ALU_COST);
7964 ins_encode %{
7965 __ andi(as_Register($dst$$reg),
7966 as_Register($src1$$reg),
7967 (int32_t)($src2$$constant));
7968 %}
7969
7970 ins_pipe(ialu_reg_imm);
7971 %}
7972
7973 // Register Or
7974 instruct orI_reg_reg(iRegINoSp dst, iRegI src1, iRegI src2) %{
7975 match(Set dst (OrI src1 src2));
7976
7977 format %{ "orr $dst, $src1, $src2\t#@orI_reg_reg" %}
7978
7979 ins_cost(ALU_COST);
7980 ins_encode %{
7981 __ orr(as_Register($dst$$reg),
7982 as_Register($src1$$reg),
7983 as_Register($src2$$reg));
7984 %}
7985
7986 ins_pipe(ialu_reg_reg);
7987 %}
7988
7989 // Immediate Or
7990 instruct orI_reg_imm(iRegINoSp dst, iRegI src1, immIAdd src2) %{
7991 match(Set dst (OrI src1 src2));
7992
7993 format %{ "ori $dst, $src1, $src2\t#@orI_reg_imm" %}
7994
7995 ins_cost(ALU_COST);
7996 ins_encode %{
7997 __ ori(as_Register($dst$$reg),
7998 as_Register($src1$$reg),
7999 (int32_t)($src2$$constant));
8000 %}
8001
8002 ins_pipe(ialu_reg_imm);
8003 %}
8004
8005 // Register Xor
8006 instruct xorI_reg_reg(iRegINoSp dst, iRegI src1, iRegI src2) %{
8007 match(Set dst (XorI src1 src2));
8008
8009 format %{ "xorr $dst, $src1, $src2\t#@xorI_reg_reg" %}
8010
8011 ins_cost(ALU_COST);
8012 ins_encode %{
8013 __ xorr(as_Register($dst$$reg),
8014 as_Register($src1$$reg),
8015 as_Register($src2$$reg));
8016 %}
8017
8018 ins_pipe(ialu_reg_reg);
8019 %}
8020
8021 // Immediate Xor
8022 instruct xorI_reg_imm(iRegINoSp dst, iRegI src1, immIAdd src2) %{
8023 match(Set dst (XorI src1 src2));
8024
8025 format %{ "xori $dst, $src1, $src2\t#@xorI_reg_imm" %}
8026
8027 ins_cost(ALU_COST);
8028 ins_encode %{
8029 __ xori(as_Register($dst$$reg),
8030 as_Register($src1$$reg),
8031 (int32_t)($src2$$constant));
8032 %}
8033
8034 ins_pipe(ialu_reg_imm);
8035 %}
8036
8037 // Register And Long
8038 instruct andL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
8039 match(Set dst (AndL src1 src2));
8040
8041 format %{ "andr $dst, $src1, $src2\t#@andL_reg_reg" %}
8042
8043 ins_cost(ALU_COST);
8044 ins_encode %{
8045 __ andr(as_Register($dst$$reg),
8046 as_Register($src1$$reg),
8047 as_Register($src2$$reg));
8048 %}
8049
8050 ins_pipe(ialu_reg_reg);
8051 %}
8052
8053 // Immediate And Long
8054 instruct andL_reg_imm(iRegLNoSp dst, iRegL src1, immLAdd src2) %{
8055 match(Set dst (AndL src1 src2));
8056
8057 format %{ "andi $dst, $src1, $src2\t#@andL_reg_imm" %}
8058
8059 ins_cost(ALU_COST);
8060 ins_encode %{
8061 __ andi(as_Register($dst$$reg),
8062 as_Register($src1$$reg),
8063 (int32_t)($src2$$constant));
8064 %}
8065
8066 ins_pipe(ialu_reg_imm);
8067 %}
8068
8069 // Register Or Long
8070 instruct orL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
8071 match(Set dst (OrL src1 src2));
8072
8073 format %{ "orr $dst, $src1, $src2\t#@orL_reg_reg" %}
8074
8075 ins_cost(ALU_COST);
8076 ins_encode %{
8077 __ orr(as_Register($dst$$reg),
8078 as_Register($src1$$reg),
8079 as_Register($src2$$reg));
8080 %}
8081
8082 ins_pipe(ialu_reg_reg);
8083 %}
8084
8085 // Immediate Or Long
8086 instruct orL_reg_imm(iRegLNoSp dst, iRegL src1, immLAdd src2) %{
8087 match(Set dst (OrL src1 src2));
8088
8089 format %{ "ori $dst, $src1, $src2\t#@orL_reg_imm" %}
8090
8091 ins_cost(ALU_COST);
8092 ins_encode %{
8093 __ ori(as_Register($dst$$reg),
8094 as_Register($src1$$reg),
8095 (int32_t)($src2$$constant));
8096 %}
8097
8098 ins_pipe(ialu_reg_imm);
8099 %}
8100
8101 // Register Xor Long
8102 instruct xorL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
8103 match(Set dst (XorL src1 src2));
8104
8105 format %{ "xorr $dst, $src1, $src2\t#@xorL_reg_reg" %}
8106
8107 ins_cost(ALU_COST);
8108 ins_encode %{
8109 __ xorr(as_Register($dst$$reg),
8110 as_Register($src1$$reg),
8111 as_Register($src2$$reg));
8112 %}
8113
8114 ins_pipe(ialu_reg_reg);
8115 %}
8116
8117 // Immediate Xor Long
8118 instruct xorL_reg_imm(iRegLNoSp dst, iRegL src1, immLAdd src2) %{
8119 match(Set dst (XorL src1 src2));
8120
8121 ins_cost(ALU_COST);
8122 format %{ "xori $dst, $src1, $src2\t#@xorL_reg_imm" %}
8123
8124 ins_encode %{
8125 __ xori(as_Register($dst$$reg),
8126 as_Register($src1$$reg),
8127 (int32_t)($src2$$constant));
8128 %}
8129
8130 ins_pipe(ialu_reg_imm);
8131 %}
8132
8133 // ============================================================================
8134 // MemBar Instruction
8135
8136 // RVTSO
8137
8138 instruct unnecessary_membar_rvtso() %{
8139 predicate(UseZtso);
8140 match(LoadFence);
8141 match(StoreFence);
8142 match(StoreStoreFence);
8143 match(MemBarAcquire);
8144 match(MemBarRelease);
8145 match(MemBarStoreStore);
8146 match(MemBarAcquireLock);
8147 match(MemBarReleaseLock);
8148
8149 ins_cost(0);
8150
8151 size(0);
8152
8153 format %{ "#@unnecessary_membar_rvtso elided/tso (empty encoding)" %}
8154 ins_encode %{
8155 __ block_comment("unnecessary_membar_rvtso");
8156 %}
8157 ins_pipe(real_empty);
8158 %}
8159
8160 instruct membar_storeload_rvtso() %{
8161 predicate(UseZtso);
8162 match(MemBarStoreLoad);
8163 ins_cost(VOLATILE_REF_COST);
8164
8165 format %{ "#@membar_storeload_rvtso\n\t"
8166 "fence w, r"%}
8167
8168 ins_encode %{
8169 __ block_comment("membar_storeload_rvtso");
8170 __ membar(MacroAssembler::StoreLoad);
8171 %}
8172
8173 ins_pipe(pipe_slow);
8174 %}
8175
8176 instruct membar_volatile_rvtso() %{
8177 predicate(UseZtso);
8178 match(MemBarVolatile);
8179 ins_cost(VOLATILE_REF_COST);
8180
8181 format %{ "#@membar_volatile_rvtso\n\t"
8182 "fence w, r"%}
8183
8184 ins_encode %{
8185 __ block_comment("membar_volatile_rvtso");
8186 __ membar(MacroAssembler::StoreLoad);
8187 %}
8188
8189 ins_pipe(pipe_slow);
8190 %}
8191
8192 instruct unnecessary_membar_volatile_rvtso() %{
8193 predicate(UseZtso && Matcher::post_store_load_barrier(n));
8194 match(MemBarVolatile);
8195 ins_cost(0);
8196
8197 size(0);
8198
8199 format %{ "#@unnecessary_membar_volatile_rvtso (unnecessary so empty encoding)" %}
8200 ins_encode %{
8201 __ block_comment("unnecessary_membar_volatile_rvtso");
8202 %}
8203 ins_pipe(real_empty);
8204 %}
8205
8206 instruct membar_full_rvtso() %{
8207 predicate(UseZtso);
8208 match(MemBarFull);
8209 ins_cost(VOLATILE_REF_COST);
8210
8211 format %{ "#@membar_full_rvtso\n\t"
8212 "fence rw, rw" %}
8213
8214 ins_encode %{
8215 __ block_comment("membar_full_rvtso");
8216 __ membar(MacroAssembler::AnyAny);
8217 %}
8218
8219 ins_pipe(pipe_slow);
8220 %}
8221
8222 // RVWMO
8223
8224 instruct membar_aqcuire_rvwmo() %{
8225 predicate(!UseZtso);
8226 match(LoadFence);
8227 match(MemBarAcquire);
8228 ins_cost(VOLATILE_REF_COST);
8229
8230 format %{ "#@membar_aqcuire_rvwmo\n\t"
8231 "fence r, rw" %}
8232
8233 ins_encode %{
8234 __ block_comment("membar_aqcuire_rvwmo");
8235 __ membar(MacroAssembler::LoadLoad | MacroAssembler::LoadStore);
8236 %}
8237 ins_pipe(pipe_serial);
8238 %}
8239
8240 instruct membar_release_rvwmo() %{
8241 predicate(!UseZtso);
8242 match(StoreFence);
8243 match(MemBarRelease);
8244 ins_cost(VOLATILE_REF_COST);
8245
8246 format %{ "#@membar_release_rvwmo\n\t"
8247 "fence rw, w" %}
8248
8249 ins_encode %{
8250 __ block_comment("membar_release_rvwmo");
8251 __ membar(MacroAssembler::LoadStore | MacroAssembler::StoreStore);
8252 %}
8253 ins_pipe(pipe_serial);
8254 %}
8255
8256 instruct membar_storestore_rvwmo() %{
8257 predicate(!UseZtso);
8258 match(MemBarStoreStore);
8259 match(StoreStoreFence);
8260 ins_cost(VOLATILE_REF_COST);
8261
8262 format %{ "#@membar_storestore_rvwmo\n\t"
8263 "fence w, w" %}
8264
8265 ins_encode %{
8266 __ membar(MacroAssembler::StoreStore);
8267 %}
8268 ins_pipe(pipe_serial);
8269 %}
8270
8271 instruct membar_storeload_rvwmo() %{
8272 predicate(!UseZtso);
8273 match(MemBarStoreLoad);
8274 ins_cost(VOLATILE_REF_COST);
8275
8276 format %{ "#@membar_storeload_rvwmo\n\t"
8277 "fence w, r"%}
8278
8279 ins_encode %{
8280 __ block_comment("membar_storeload_rvwmo");
8281 __ membar(MacroAssembler::StoreLoad);
8282 %}
8283
8284 ins_pipe(pipe_serial);
8285 %}
8286
8287 instruct membar_volatile_rvwmo() %{
8288 predicate(!UseZtso);
8289 match(MemBarVolatile);
8290 ins_cost(VOLATILE_REF_COST);
8291
8292 format %{ "#@membar_volatile_rvwmo\n\t"
8293 "fence w, r"%}
8294
8295 ins_encode %{
8296 __ block_comment("membar_volatile_rvwmo");
8297 __ membar(MacroAssembler::StoreLoad);
8298 %}
8299
8300 ins_pipe(pipe_serial);
8301 %}
8302
8303 instruct membar_lock_rvwmo() %{
8304 predicate(!UseZtso);
8305 match(MemBarAcquireLock);
8306 match(MemBarReleaseLock);
8307 ins_cost(0);
8308
8309 format %{ "#@membar_lock_rvwmo (elided)" %}
8310
8311 ins_encode %{
8312 __ block_comment("membar_lock_rvwmo (elided)");
8313 %}
8314
8315 ins_pipe(pipe_serial);
8316 %}
8317
8318 instruct unnecessary_membar_volatile_rvwmo() %{
8319 predicate(!UseZtso && Matcher::post_store_load_barrier(n));
8320 match(MemBarVolatile);
8321 ins_cost(0);
8322
8323 size(0);
8324 format %{ "#@unnecessary_membar_volatile_rvwmo (unnecessary so empty encoding)" %}
8325 ins_encode %{
8326 __ block_comment("unnecessary_membar_volatile_rvwmo");
8327 %}
8328 ins_pipe(real_empty);
8329 %}
8330
8331 instruct membar_full_rvwmo() %{
8332 predicate(!UseZtso);
8333 match(MemBarFull);
8334 ins_cost(VOLATILE_REF_COST);
8335
8336 format %{ "#@membar_full_rvwmo\n\t"
8337 "fence rw, rw" %}
8338
8339 ins_encode %{
8340 __ block_comment("membar_full_rvwmo");
8341 __ membar(MacroAssembler::AnyAny);
8342 %}
8343
8344 ins_pipe(pipe_serial);
8345 %}
8346
8347 instruct spin_wait() %{
8348 predicate(UseZihintpause);
8349 match(OnSpinWait);
8350 ins_cost(CACHE_MISS_COST);
8351
8352 format %{ "spin_wait" %}
8353
8354 ins_encode %{
8355 __ pause();
8356 %}
8357
8358 ins_pipe(pipe_serial);
8359 %}
8360
8361 // ============================================================================
8362 // Cast Instructions (Java-level type cast)
8363
8364 instruct castX2P(iRegPNoSp dst, iRegL src) %{
8365 match(Set dst (CastX2P src));
8366
8367 ins_cost(ALU_COST);
8368 format %{ "mv $dst, $src\t# long -> ptr, #@castX2P" %}
8369
8370 ins_encode %{
8371 if ($dst$$reg != $src$$reg) {
8372 __ mv(as_Register($dst$$reg), as_Register($src$$reg));
8373 }
8374 %}
8375
8376 ins_pipe(ialu_reg);
8377 %}
8378
8379 instruct castP2X(iRegLNoSp dst, iRegP src) %{
8380 match(Set dst (CastP2X src));
8381
8382 ins_cost(ALU_COST);
8383 format %{ "mv $dst, $src\t# ptr -> long, #@castP2X" %}
8384
8385 ins_encode %{
8386 if ($dst$$reg != $src$$reg) {
8387 __ mv(as_Register($dst$$reg), as_Register($src$$reg));
8388 }
8389 %}
8390
8391 ins_pipe(ialu_reg);
8392 %}
8393
8394 instruct castPP(iRegPNoSp dst)
8395 %{
8396 match(Set dst (CastPP dst));
8397 ins_cost(0);
8398
8399 size(0);
8400 format %{ "# castPP of $dst, #@castPP" %}
8401 ins_encode(/* empty encoding */);
8402 ins_pipe(pipe_class_empty);
8403 %}
8404
8405 instruct castLL(iRegL dst)
8406 %{
8407 match(Set dst (CastLL dst));
8408
8409 size(0);
8410 format %{ "# castLL of $dst, #@castLL" %}
8411 ins_encode(/* empty encoding */);
8412 ins_cost(0);
8413 ins_pipe(pipe_class_empty);
8414 %}
8415
8416 instruct castII(iRegI dst)
8417 %{
8418 match(Set dst (CastII dst));
8419
8420 size(0);
8421 format %{ "# castII of $dst, #@castII" %}
8422 ins_encode(/* empty encoding */);
8423 ins_cost(0);
8424 ins_pipe(pipe_class_empty);
8425 %}
8426
8427 instruct checkCastPP(iRegPNoSp dst)
8428 %{
8429 match(Set dst (CheckCastPP dst));
8430
8431 size(0);
8432 ins_cost(0);
8433 format %{ "# checkcastPP of $dst, #@checkCastPP" %}
8434 ins_encode(/* empty encoding */);
8435 ins_pipe(pipe_class_empty);
8436 %}
8437
8438 instruct castHH(fRegF dst)
8439 %{
8440 match(Set dst (CastHH dst));
8441
8442 size(0);
8443 format %{ "# castHH of $dst" %}
8444 ins_encode(/* empty encoding */);
8445 ins_cost(0);
8446 ins_pipe(pipe_class_empty);
8447 %}
8448
8449 instruct castFF(fRegF dst)
8450 %{
8451 match(Set dst (CastFF dst));
8452
8453 size(0);
8454 format %{ "# castFF of $dst" %}
8455 ins_encode(/* empty encoding */);
8456 ins_cost(0);
8457 ins_pipe(pipe_class_empty);
8458 %}
8459
8460 instruct castDD(fRegD dst)
8461 %{
8462 match(Set dst (CastDD dst));
8463
8464 size(0);
8465 format %{ "# castDD of $dst" %}
8466 ins_encode(/* empty encoding */);
8467 ins_cost(0);
8468 ins_pipe(pipe_class_empty);
8469 %}
8470
8471 instruct castVV(vReg dst)
8472 %{
8473 match(Set dst (CastVV dst));
8474
8475 size(0);
8476 format %{ "# castVV of $dst" %}
8477 ins_encode(/* empty encoding */);
8478 ins_cost(0);
8479 ins_pipe(pipe_class_empty);
8480 %}
8481
8482 instruct castVVMask(vRegMask dst)
8483 %{
8484 match(Set dst (CastVV dst));
8485
8486 size(0);
8487 format %{ "# castVV of $dst" %}
8488 ins_encode(/* empty encoding */);
8489 ins_cost(0);
8490 ins_pipe(pipe_class_empty);
8491 %}
8492
8493 // ============================================================================
8494 // Convert Instructions
8495
8496 // int to bool
8497 instruct convI2Bool(iRegINoSp dst, iRegI src)
8498 %{
8499 match(Set dst (Conv2B src));
8500
8501 ins_cost(ALU_COST);
8502 format %{ "snez $dst, $src\t#@convI2Bool" %}
8503
8504 ins_encode %{
8505 __ snez(as_Register($dst$$reg), as_Register($src$$reg));
8506 %}
8507
8508 ins_pipe(ialu_reg);
8509 %}
8510
8511 // pointer to bool
8512 instruct convP2Bool(iRegINoSp dst, iRegP src)
8513 %{
8514 match(Set dst (Conv2B src));
8515
8516 ins_cost(ALU_COST);
8517 format %{ "snez $dst, $src\t#@convP2Bool" %}
8518
8519 ins_encode %{
8520 __ snez(as_Register($dst$$reg), as_Register($src$$reg));
8521 %}
8522
8523 ins_pipe(ialu_reg);
8524 %}
8525
8526 // int <-> long
8527
8528 instruct convI2L_reg_reg(iRegLNoSp dst, iRegIorL2I src)
8529 %{
8530 match(Set dst (ConvI2L src));
8531
8532 ins_cost(ALU_COST);
8533 format %{ "addw $dst, $src, zr\t#@convI2L_reg_reg" %}
8534 ins_encode %{
8535 __ sext(as_Register($dst$$reg), as_Register($src$$reg), 32);
8536 %}
8537 ins_pipe(ialu_reg);
8538 %}
8539
8540 instruct convL2I_reg(iRegINoSp dst, iRegL src) %{
8541 match(Set dst (ConvL2I src));
8542
8543 ins_cost(ALU_COST);
8544 format %{ "addw $dst, $src, zr\t#@convL2I_reg" %}
8545
8546 ins_encode %{
8547 __ sext(as_Register($dst$$reg), as_Register($src$$reg), 32);
8548 %}
8549
8550 ins_pipe(ialu_reg);
8551 %}
8552
8553 // int to unsigned long (Zero-extend)
8554 instruct convI2UL_reg_reg(iRegLNoSp dst, iRegIorL2I src, immL_32bits mask)
8555 %{
8556 match(Set dst (AndL (ConvI2L src) mask));
8557
8558 ins_cost(ALU_COST * 2);
8559 format %{ "zext $dst, $src, 32\t# i2ul, #@convI2UL_reg_reg" %}
8560
8561 ins_encode %{
8562 __ zext(as_Register($dst$$reg), as_Register($src$$reg), 32);
8563 %}
8564
8565 ins_pipe(ialu_reg_shift);
8566 %}
8567
8568 // float <-> double
8569
8570 instruct convF2D_reg(fRegD dst, fRegF src) %{
8571 match(Set dst (ConvF2D src));
8572
8573 ins_cost(XFER_COST);
8574 format %{ "fcvt.d.s $dst, $src\t#@convF2D_reg" %}
8575
8576 ins_encode %{
8577 __ fcvt_d_s(as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg));
8578 %}
8579
8580 ins_pipe(fp_f2d);
8581 %}
8582
8583 instruct convD2F_reg(fRegF dst, fRegD src) %{
8584 match(Set dst (ConvD2F src));
8585
8586 ins_cost(XFER_COST);
8587 format %{ "fcvt.s.d $dst, $src\t#@convD2F_reg" %}
8588
8589 ins_encode %{
8590 __ fcvt_s_d(as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg));
8591 %}
8592
8593 ins_pipe(fp_d2f);
8594 %}
8595
8596 // single <-> half precision
8597
8598 instruct convHF2F_reg_reg(fRegF dst, iRegIorL2I src, iRegINoSp tmp) %{
8599 match(Set dst (ConvHF2F src));
8600 effect(TEMP tmp);
8601 format %{ "fmv.h.x $dst, $src\t# move source from $src to $dst\n\t"
8602 "fcvt.s.h $dst, $dst\t# convert half to single precision"
8603 %}
8604 ins_encode %{
8605 __ float16_to_float($dst$$FloatRegister, $src$$Register, $tmp$$Register);
8606 %}
8607 ins_pipe(pipe_slow);
8608 %}
8609
8610 instruct convF2HF_reg_reg(iRegINoSp dst, fRegF src, fRegF ftmp, iRegINoSp xtmp) %{
8611 match(Set dst (ConvF2HF src));
8612 effect(TEMP_DEF dst, TEMP ftmp, TEMP xtmp);
8613 format %{ "fcvt.h.s $ftmp, $src\t# convert single precision to half\n\t"
8614 "fmv.x.h $dst, $ftmp\t# move result from $ftmp to $dst"
8615 %}
8616 ins_encode %{
8617 __ float_to_float16($dst$$Register, $src$$FloatRegister, $ftmp$$FloatRegister, $xtmp$$Register);
8618 %}
8619 ins_pipe(pipe_slow);
8620 %}
8621
8622 // half precision operations
8623
8624 instruct reinterpretS2HF(fRegF dst, iRegI src)
8625 %{
8626 match(Set dst (ReinterpretS2HF src));
8627 format %{ "fmv.h.x $dst, $src\t# reinterpretS2HF" %}
8628 ins_encode %{
8629 __ fmv_h_x($dst$$FloatRegister, $src$$Register);
8630 %}
8631 ins_pipe(fp_i2f);
8632 %}
8633
8634 instruct convF2HFAndS2HF(fRegF dst, fRegF src)
8635 %{
8636 match(Set dst (ReinterpretS2HF (ConvF2HF src)));
8637 format %{ "convF2HFAndS2HF $dst, $src" %}
8638 ins_encode %{
8639 __ fcvt_h_s($dst$$FloatRegister, $src$$FloatRegister);
8640 %}
8641 ins_pipe(fp_uop_s);
8642 %}
8643
8644 instruct reinterpretHF2S(iRegINoSp dst, fRegF src)
8645 %{
8646 match(Set dst (ReinterpretHF2S src));
8647 format %{ "fmv.x.h $dst, $src\t# reinterpretHF2S" %}
8648 ins_encode %{
8649 __ fmv_x_h($dst$$Register, $src$$FloatRegister);
8650 %}
8651 ins_pipe(fp_f2i);
8652 %}
8653
8654 instruct convHF2SAndHF2F(fRegF dst, fRegF src)
8655 %{
8656 match(Set dst (ConvHF2F (ReinterpretHF2S src)));
8657 format %{ "convHF2SAndHF2F $dst, $src" %}
8658 ins_encode %{
8659 __ fcvt_s_h($dst$$FloatRegister, $src$$FloatRegister);
8660 %}
8661 ins_pipe(fp_uop_s);
8662 %}
8663
8664 instruct sqrt_HF_reg(fRegF dst, fRegF src)
8665 %{
8666 match(Set dst (SqrtHF src));
8667 format %{ "fsqrt.h $dst, $src" %}
8668 ins_encode %{
8669 __ fsqrt_h($dst$$FloatRegister, $src$$FloatRegister);
8670 %}
8671 ins_pipe(fp_sqrt_s);
8672 %}
8673
8674 instruct binOps_HF_reg(fRegF dst, fRegF src1, fRegF src2)
8675 %{
8676 match(Set dst (AddHF src1 src2));
8677 match(Set dst (SubHF src1 src2));
8678 match(Set dst (MulHF src1 src2));
8679 match(Set dst (DivHF src1 src2));
8680 format %{ "binop_hf $dst, $src1, $src2" %}
8681 ins_encode %{
8682 int opcode = this->ideal_Opcode();
8683 switch(opcode) {
8684 case Op_AddHF: __ fadd_h($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); break;
8685 case Op_SubHF: __ fsub_h($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); break;
8686 case Op_MulHF: __ fmul_h($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); break;
8687 case Op_DivHF: __ fdiv_h($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); break;
8688 default: assert(false, "%s is not supported here", NodeClassNames[opcode]); break;
8689 }
8690 %}
8691 ins_pipe(fp_dop_reg_reg_s);
8692 %}
8693
8694 instruct min_HF_reg(fRegF dst, fRegF src1, fRegF src2, rFlagsReg cr)
8695 %{
8696 predicate(!UseZfa);
8697 match(Set dst (MinHF src1 src2));
8698 effect(KILL cr);
8699
8700 format %{ "min_hf $dst, $src1, $src2" %}
8701
8702 ins_encode %{
8703 __ minmax_fp($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister,
8704 __ FLOAT_TYPE::half_precision, true /* is_min */);
8705 %}
8706 ins_pipe(pipe_class_default);
8707 %}
8708
8709 instruct min_HF_reg_zfa(fRegF dst, fRegF src1, fRegF src2)
8710 %{
8711 predicate(UseZfa);
8712 match(Set dst (MinHF src1 src2));
8713
8714 format %{ "min_hf $dst, $src1, $src2" %}
8715
8716 ins_encode %{
8717 __ fminm_h(as_FloatRegister($dst$$reg),
8718 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
8719 %}
8720
8721 ins_pipe(pipe_class_default);
8722 %}
8723
8724 instruct max_HF_reg(fRegF dst, fRegF src1, fRegF src2, rFlagsReg cr)
8725 %{
8726 predicate(!UseZfa);
8727 match(Set dst (MaxHF src1 src2));
8728 effect(KILL cr);
8729
8730 format %{ "max_hf $dst, $src1, $src2" %}
8731
8732 ins_encode %{
8733 __ minmax_fp($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister,
8734 __ FLOAT_TYPE::half_precision, false /* is_min */);
8735 %}
8736 ins_pipe(pipe_class_default);
8737 %}
8738
8739 instruct max_HF_reg_zfa(fRegF dst, fRegF src1, fRegF src2)
8740 %{
8741 predicate(UseZfa);
8742 match(Set dst (MaxHF src1 src2));
8743
8744 format %{ "max_hf $dst, $src1, $src2" %}
8745
8746 ins_encode %{
8747 __ fmaxm_h(as_FloatRegister($dst$$reg),
8748 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
8749 %}
8750
8751 ins_pipe(pipe_class_default);
8752 %}
8753
8754 instruct fma_HF_reg(fRegF dst, fRegF src1, fRegF src2, fRegF src3)
8755 %{
8756 match(Set dst (FmaHF src3 (Binary src1 src2)));
8757 format %{ "fmadd.h $dst, $src1, $src2, $src3\t# $dst = $src1 * $src2 + $src3 fma packedH" %}
8758 ins_encode %{
8759 __ fmadd_h($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister, $src3$$FloatRegister);
8760 %}
8761 ins_pipe(pipe_class_default);
8762 %}
8763
8764 // float <-> int
8765
8766 instruct convF2I_reg_reg(iRegINoSp dst, fRegF src) %{
8767 match(Set dst (ConvF2I src));
8768
8769 ins_cost(XFER_COST);
8770 format %{ "fcvt.w.s $dst, $src\t#@convF2I_reg_reg" %}
8771
8772 ins_encode %{
8773 __ fcvt_w_s_safe($dst$$Register, $src$$FloatRegister);
8774 %}
8775
8776 ins_pipe(fp_f2i);
8777 %}
8778
8779 instruct convI2F_reg_reg(fRegF dst, iRegIorL2I src) %{
8780 match(Set dst (ConvI2F src));
8781
8782 ins_cost(XFER_COST);
8783 format %{ "fcvt.s.w $dst, $src\t#@convI2F_reg_reg" %}
8784
8785 ins_encode %{
8786 __ fcvt_s_w(as_FloatRegister($dst$$reg), as_Register($src$$reg));
8787 %}
8788
8789 ins_pipe(fp_i2f);
8790 %}
8791
8792 // float <-> long
8793
8794 instruct convF2L_reg_reg(iRegLNoSp dst, fRegF src) %{
8795 match(Set dst (ConvF2L src));
8796
8797 ins_cost(XFER_COST);
8798 format %{ "fcvt.l.s $dst, $src\t#@convF2L_reg_reg" %}
8799
8800 ins_encode %{
8801 __ fcvt_l_s_safe($dst$$Register, $src$$FloatRegister);
8802 %}
8803
8804 ins_pipe(fp_f2l);
8805 %}
8806
8807 instruct convL2F_reg_reg(fRegF dst, iRegL src) %{
8808 match(Set dst (ConvL2F src));
8809
8810 ins_cost(XFER_COST);
8811 format %{ "fcvt.s.l $dst, $src\t#@convL2F_reg_reg" %}
8812
8813 ins_encode %{
8814 __ fcvt_s_l(as_FloatRegister($dst$$reg), as_Register($src$$reg));
8815 %}
8816
8817 ins_pipe(fp_l2f);
8818 %}
8819
8820 // double <-> int
8821
8822 instruct convD2I_reg_reg(iRegINoSp dst, fRegD src) %{
8823 match(Set dst (ConvD2I src));
8824
8825 ins_cost(XFER_COST);
8826 format %{ "fcvt.w.d $dst, $src\t#@convD2I_reg_reg" %}
8827
8828 ins_encode %{
8829 __ fcvt_w_d_safe($dst$$Register, $src$$FloatRegister);
8830 %}
8831
8832 ins_pipe(fp_d2i);
8833 %}
8834
8835 instruct convI2D_reg_reg(fRegD dst, iRegIorL2I src) %{
8836 match(Set dst (ConvI2D src));
8837
8838 ins_cost(XFER_COST);
8839 format %{ "fcvt.d.w $dst, $src\t#@convI2D_reg_reg" %}
8840
8841 ins_encode %{
8842 __ fcvt_d_w(as_FloatRegister($dst$$reg), as_Register($src$$reg));
8843 %}
8844
8845 ins_pipe(fp_i2d);
8846 %}
8847
8848 // double <-> long
8849
8850 instruct convD2L_reg_reg(iRegLNoSp dst, fRegD src) %{
8851 match(Set dst (ConvD2L src));
8852
8853 ins_cost(XFER_COST);
8854 format %{ "fcvt.l.d $dst, $src\t#@convD2L_reg_reg" %}
8855
8856 ins_encode %{
8857 __ fcvt_l_d_safe($dst$$Register, $src$$FloatRegister);
8858 %}
8859
8860 ins_pipe(fp_d2l);
8861 %}
8862
8863 instruct convL2D_reg_reg(fRegD dst, iRegL src) %{
8864 match(Set dst (ConvL2D src));
8865
8866 ins_cost(XFER_COST);
8867 format %{ "fcvt.d.l $dst, $src\t#@convL2D_reg_reg" %}
8868
8869 ins_encode %{
8870 __ fcvt_d_l(as_FloatRegister($dst$$reg), as_Register($src$$reg));
8871 %}
8872
8873 ins_pipe(fp_l2d);
8874 %}
8875
8876 // Convert oop into int for vectors alignment masking
8877 instruct convP2I(iRegINoSp dst, iRegP src) %{
8878 match(Set dst (ConvL2I (CastP2X src)));
8879
8880 ins_cost(ALU_COST * 2);
8881 format %{ "zext $dst, $src, 32\t# ptr -> int, #@convP2I" %}
8882
8883 ins_encode %{
8884 __ zext($dst$$Register, $src$$Register, 32);
8885 %}
8886
8887 ins_pipe(ialu_reg);
8888 %}
8889
8890 // Convert compressed oop into int for vectors alignment masking
8891 // in case of 32bit oops (heap < 4Gb).
8892 instruct convN2I(iRegINoSp dst, iRegN src)
8893 %{
8894 predicate(CompressedOops::shift() == 0);
8895 match(Set dst (ConvL2I (CastP2X (DecodeN src))));
8896
8897 ins_cost(ALU_COST);
8898 format %{ "mv $dst, $src\t# compressed ptr -> int, #@convN2I" %}
8899
8900 ins_encode %{
8901 __ mv($dst$$Register, $src$$Register);
8902 %}
8903
8904 ins_pipe(ialu_reg);
8905 %}
8906
8907 instruct round_double_reg(iRegLNoSp dst, fRegD src, fRegD ftmp) %{
8908 match(Set dst (RoundD src));
8909
8910 ins_cost(XFER_COST + BRANCH_COST);
8911 effect(TEMP ftmp);
8912 format %{ "java_round_double $dst, $src\t#@round_double_reg" %}
8913
8914 ins_encode %{
8915 __ java_round_double($dst$$Register, as_FloatRegister($src$$reg), as_FloatRegister($ftmp$$reg));
8916 %}
8917
8918 ins_pipe(pipe_slow);
8919 %}
8920
8921 instruct round_float_reg(iRegINoSp dst, fRegF src, fRegF ftmp) %{
8922 match(Set dst (RoundF src));
8923
8924 ins_cost(XFER_COST + BRANCH_COST);
8925 effect(TEMP ftmp);
8926 format %{ "java_round_float $dst, $src\t#@round_float_reg" %}
8927
8928 ins_encode %{
8929 __ java_round_float($dst$$Register, as_FloatRegister($src$$reg), as_FloatRegister($ftmp$$reg));
8930 %}
8931
8932 ins_pipe(pipe_slow);
8933 %}
8934
8935 // Convert oop pointer into compressed form
8936 instruct encodeHeapOop(iRegNNoSp dst, iRegP src) %{
8937 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
8938 match(Set dst (EncodeP src));
8939 ins_cost(ALU_COST);
8940 format %{ "encode_heap_oop $dst, $src\t#@encodeHeapOop" %}
8941 ins_encode %{
8942 Register s = $src$$Register;
8943 Register d = $dst$$Register;
8944 __ encode_heap_oop(d, s);
8945 %}
8946 ins_pipe(pipe_class_default);
8947 %}
8948
8949 instruct encodeHeapOop_not_null(iRegNNoSp dst, iRegP src) %{
8950 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
8951 match(Set dst (EncodeP src));
8952 ins_cost(ALU_COST);
8953 format %{ "encode_heap_oop_not_null $dst, $src\t#@encodeHeapOop_not_null" %}
8954 ins_encode %{
8955 __ encode_heap_oop_not_null($dst$$Register, $src$$Register);
8956 %}
8957 ins_pipe(pipe_class_default);
8958 %}
8959
8960 instruct decodeHeapOop(iRegPNoSp dst, iRegN src) %{
8961 predicate(n->bottom_type()->is_ptr()->ptr() != TypePtr::NotNull &&
8962 n->bottom_type()->is_ptr()->ptr() != TypePtr::Constant);
8963 match(Set dst (DecodeN src));
8964
8965 ins_cost(0);
8966 format %{ "decode_heap_oop $dst, $src\t#@decodeHeapOop" %}
8967 ins_encode %{
8968 Register s = $src$$Register;
8969 Register d = $dst$$Register;
8970 __ decode_heap_oop(d, s);
8971 %}
8972 ins_pipe(pipe_class_default);
8973 %}
8974
8975 instruct decodeHeapOop_not_null(iRegPNoSp dst, iRegN src) %{
8976 predicate(n->bottom_type()->is_ptr()->ptr() == TypePtr::NotNull ||
8977 n->bottom_type()->is_ptr()->ptr() == TypePtr::Constant);
8978 match(Set dst (DecodeN src));
8979
8980 ins_cost(0);
8981 format %{ "decode_heap_oop_not_null $dst, $src\t#@decodeHeapOop_not_null" %}
8982 ins_encode %{
8983 Register s = $src$$Register;
8984 Register d = $dst$$Register;
8985 __ decode_heap_oop_not_null(d, s);
8986 %}
8987 ins_pipe(pipe_class_default);
8988 %}
8989
8990 // Convert klass pointer into compressed form.
8991 instruct encodeKlass_not_null(iRegNNoSp dst, iRegP src) %{
8992 match(Set dst (EncodePKlass src));
8993
8994 ins_cost(ALU_COST);
8995 format %{ "encode_klass_not_null $dst, $src\t#@encodeKlass_not_null" %}
8996
8997 ins_encode %{
8998 Register src_reg = as_Register($src$$reg);
8999 Register dst_reg = as_Register($dst$$reg);
9000 __ encode_klass_not_null(dst_reg, src_reg, t0);
9001 %}
9002
9003 ins_pipe(pipe_class_default);
9004 %}
9005
9006 instruct decodeKlass_not_null(iRegPNoSp dst, iRegN src, iRegPNoSp tmp) %{
9007 match(Set dst (DecodeNKlass src));
9008
9009 effect(TEMP_DEF dst, TEMP tmp);
9010
9011 ins_cost(ALU_COST);
9012 format %{ "decode_klass_not_null $dst, $src\t#@decodeKlass_not_null" %}
9013
9014 ins_encode %{
9015 Register src_reg = as_Register($src$$reg);
9016 Register dst_reg = as_Register($dst$$reg);
9017 Register tmp_reg = as_Register($tmp$$reg);
9018 __ decode_klass_not_null(dst_reg, src_reg, tmp_reg);
9019 %}
9020
9021 ins_pipe(pipe_class_default);
9022 %}
9023
9024 // stack <-> reg and reg <-> reg shuffles with no conversion
9025
9026 instruct MoveF2I_stack_reg(iRegINoSp dst, stackSlotF src) %{
9027
9028 match(Set dst (MoveF2I src));
9029
9030 effect(DEF dst, USE src);
9031
9032 ins_cost(LOAD_COST);
9033
9034 format %{ "lw $dst, $src\t#@MoveF2I_stack_reg" %}
9035
9036 ins_encode %{
9037 __ lw(as_Register($dst$$reg), Address(sp, $src$$disp));
9038 %}
9039
9040 ins_pipe(iload_reg_reg);
9041
9042 %}
9043
9044 instruct MoveI2F_stack_reg(fRegF dst, stackSlotI src) %{
9045
9046 match(Set dst (MoveI2F src));
9047
9048 effect(DEF dst, USE src);
9049
9050 ins_cost(LOAD_COST);
9051
9052 format %{ "flw $dst, $src\t#@MoveI2F_stack_reg" %}
9053
9054 ins_encode %{
9055 __ flw(as_FloatRegister($dst$$reg), Address(sp, $src$$disp));
9056 %}
9057
9058 ins_pipe(fp_load_mem_s);
9059
9060 %}
9061
9062 instruct MoveD2L_stack_reg(iRegLNoSp dst, stackSlotD src) %{
9063
9064 match(Set dst (MoveD2L src));
9065
9066 effect(DEF dst, USE src);
9067
9068 ins_cost(LOAD_COST);
9069
9070 format %{ "ld $dst, $src\t#@MoveD2L_stack_reg" %}
9071
9072 ins_encode %{
9073 __ ld(as_Register($dst$$reg), Address(sp, $src$$disp));
9074 %}
9075
9076 ins_pipe(iload_reg_reg);
9077
9078 %}
9079
9080 instruct MoveL2D_stack_reg(fRegD dst, stackSlotL src) %{
9081
9082 match(Set dst (MoveL2D src));
9083
9084 effect(DEF dst, USE src);
9085
9086 ins_cost(LOAD_COST);
9087
9088 format %{ "fld $dst, $src\t#@MoveL2D_stack_reg" %}
9089
9090 ins_encode %{
9091 __ fld(as_FloatRegister($dst$$reg), Address(sp, $src$$disp));
9092 %}
9093
9094 ins_pipe(fp_load_mem_d);
9095
9096 %}
9097
9098 instruct MoveF2I_reg_stack(stackSlotI dst, fRegF src) %{
9099
9100 match(Set dst (MoveF2I src));
9101
9102 effect(DEF dst, USE src);
9103
9104 ins_cost(STORE_COST);
9105
9106 format %{ "fsw $src, $dst\t#@MoveF2I_reg_stack" %}
9107
9108 ins_encode %{
9109 __ fsw(as_FloatRegister($src$$reg), Address(sp, $dst$$disp));
9110 %}
9111
9112 ins_pipe(fp_store_reg_s);
9113
9114 %}
9115
9116 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{
9117
9118 match(Set dst (MoveI2F src));
9119
9120 effect(DEF dst, USE src);
9121
9122 ins_cost(STORE_COST);
9123
9124 format %{ "sw $src, $dst\t#@MoveI2F_reg_stack" %}
9125
9126 ins_encode %{
9127 __ sw(as_Register($src$$reg), Address(sp, $dst$$disp));
9128 %}
9129
9130 ins_pipe(istore_reg_reg);
9131
9132 %}
9133
9134 instruct MoveD2L_reg_stack(stackSlotL dst, fRegD src) %{
9135
9136 match(Set dst (MoveD2L src));
9137
9138 effect(DEF dst, USE src);
9139
9140 ins_cost(STORE_COST);
9141
9142 format %{ "fsd $dst, $src\t#@MoveD2L_reg_stack" %}
9143
9144 ins_encode %{
9145 __ fsd(as_FloatRegister($src$$reg), Address(sp, $dst$$disp));
9146 %}
9147
9148 ins_pipe(fp_store_reg_d);
9149
9150 %}
9151
9152 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{
9153
9154 match(Set dst (MoveL2D src));
9155
9156 effect(DEF dst, USE src);
9157
9158 ins_cost(STORE_COST);
9159
9160 format %{ "sd $src, $dst\t#@MoveL2D_reg_stack" %}
9161
9162 ins_encode %{
9163 __ sd(as_Register($src$$reg), Address(sp, $dst$$disp));
9164 %}
9165
9166 ins_pipe(istore_reg_reg);
9167
9168 %}
9169
9170 instruct MoveF2I_reg_reg(iRegINoSp dst, fRegF src) %{
9171
9172 match(Set dst (MoveF2I src));
9173
9174 effect(DEF dst, USE src);
9175
9176 ins_cost(FMVX_COST);
9177
9178 format %{ "fmv.x.w $dst, $src\t#@MoveF2I_reg_reg" %}
9179
9180 ins_encode %{
9181 __ fmv_x_w(as_Register($dst$$reg), as_FloatRegister($src$$reg));
9182 %}
9183
9184 ins_pipe(fp_f2i);
9185
9186 %}
9187
9188 instruct MoveI2F_reg_reg(fRegF dst, iRegI src) %{
9189
9190 match(Set dst (MoveI2F src));
9191
9192 effect(DEF dst, USE src);
9193
9194 ins_cost(FMVX_COST);
9195
9196 format %{ "fmv.w.x $dst, $src\t#@MoveI2F_reg_reg" %}
9197
9198 ins_encode %{
9199 __ fmv_w_x(as_FloatRegister($dst$$reg), as_Register($src$$reg));
9200 %}
9201
9202 ins_pipe(fp_i2f);
9203
9204 %}
9205
9206 instruct MoveD2L_reg_reg(iRegLNoSp dst, fRegD src) %{
9207
9208 match(Set dst (MoveD2L src));
9209
9210 effect(DEF dst, USE src);
9211
9212 ins_cost(FMVX_COST);
9213
9214 format %{ "fmv.x.d $dst, $src\t#@MoveD2L_reg_reg" %}
9215
9216 ins_encode %{
9217 __ fmv_x_d(as_Register($dst$$reg), as_FloatRegister($src$$reg));
9218 %}
9219
9220 ins_pipe(fp_d2l);
9221
9222 %}
9223
9224 instruct MoveL2D_reg_reg(fRegD dst, iRegL src) %{
9225
9226 match(Set dst (MoveL2D src));
9227
9228 effect(DEF dst, USE src);
9229
9230 ins_cost(FMVX_COST);
9231
9232 format %{ "fmv.d.x $dst, $src\t#@MoveL2D_reg_reg" %}
9233
9234 ins_encode %{
9235 __ fmv_d_x(as_FloatRegister($dst$$reg), as_Register($src$$reg));
9236 %}
9237
9238 ins_pipe(fp_l2d);
9239
9240 %}
9241
9242 // ============================================================================
9243 // Compare Instructions which set the result float comparisons in dest register.
9244
9245 instruct cmpF3_reg_reg(iRegINoSp dst, fRegF op1, fRegF op2)
9246 %{
9247 match(Set dst (CmpF3 op1 op2));
9248
9249 ins_cost(XFER_COST * 2 + BRANCH_COST + ALU_COST);
9250 format %{ "flt.s $dst, $op2, $op1\t#@cmpF3_reg_reg\n\t"
9251 "bgtz $dst, done\n\t"
9252 "feq.s $dst, $op1, $op2\n\t"
9253 "addi $dst, $dst, -1\n\t"
9254 "done:"
9255 %}
9256
9257 ins_encode %{
9258 // we want -1 for unordered or less than, 0 for equal and 1 for greater than.
9259 __ float_compare(as_Register($dst$$reg), as_FloatRegister($op1$$reg),
9260 as_FloatRegister($op2$$reg), -1 /*unordered_result < 0*/);
9261 %}
9262
9263 ins_pipe(pipe_class_default);
9264 %}
9265
9266 instruct cmpD3_reg_reg(iRegINoSp dst, fRegD op1, fRegD op2)
9267 %{
9268 match(Set dst (CmpD3 op1 op2));
9269
9270 ins_cost(XFER_COST * 2 + BRANCH_COST + ALU_COST);
9271 format %{ "flt.d $dst, $op2, $op1\t#@cmpD3_reg_reg\n\t"
9272 "bgtz $dst, done\n\t"
9273 "feq.d $dst, $op1, $op2\n\t"
9274 "addi $dst, $dst, -1\n\t"
9275 "done:"
9276 %}
9277
9278 ins_encode %{
9279 // we want -1 for unordered or less than, 0 for equal and 1 for greater than.
9280 __ double_compare(as_Register($dst$$reg), as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg), -1 /*unordered_result < 0*/);
9281 %}
9282
9283 ins_pipe(pipe_class_default);
9284 %}
9285
9286 instruct cmpL3_reg_reg(iRegINoSp dst, iRegL op1, iRegL op2)
9287 %{
9288 match(Set dst (CmpL3 op1 op2));
9289
9290 ins_cost(ALU_COST * 3 + BRANCH_COST);
9291 format %{ "slt $dst, $op2, $op1\t#@cmpL3_reg_reg\n\t"
9292 "bnez $dst, done\n\t"
9293 "slt $dst, $op1, $op2\n\t"
9294 "neg $dst, $dst\n\t"
9295 "done:"
9296 %}
9297 ins_encode %{
9298 __ cmp_l2i(t0, as_Register($op1$$reg), as_Register($op2$$reg));
9299 __ mv(as_Register($dst$$reg), t0);
9300 %}
9301
9302 ins_pipe(pipe_class_default);
9303 %}
9304
9305 instruct cmpUL3_reg_reg(iRegINoSp dst, iRegL op1, iRegL op2)
9306 %{
9307 match(Set dst (CmpUL3 op1 op2));
9308
9309 ins_cost(ALU_COST * 3 + BRANCH_COST);
9310 format %{ "sltu $dst, $op2, $op1\t#@cmpUL3_reg_reg\n\t"
9311 "bnez $dst, done\n\t"
9312 "sltu $dst, $op1, $op2\n\t"
9313 "neg $dst, $dst\n\t"
9314 "done:"
9315 %}
9316 ins_encode %{
9317 __ cmp_ul2i(t0, as_Register($op1$$reg), as_Register($op2$$reg));
9318 __ mv(as_Register($dst$$reg), t0);
9319 %}
9320
9321 ins_pipe(pipe_class_default);
9322 %}
9323
9324 instruct cmpU3_reg_reg(iRegINoSp dst, iRegI op1, iRegI op2)
9325 %{
9326 match(Set dst (CmpU3 op1 op2));
9327
9328 ins_cost(ALU_COST * 3 + BRANCH_COST);
9329 format %{ "sltu $dst, $op2, $op1\t#@cmpU3_reg_reg\n\t"
9330 "bnez $dst, done\n\t"
9331 "sltu $dst, $op1, $op2\n\t"
9332 "neg $dst, $dst\n\t"
9333 "done:"
9334 %}
9335 ins_encode %{
9336 __ cmp_uw2i(t0, as_Register($op1$$reg), as_Register($op2$$reg));
9337 __ mv(as_Register($dst$$reg), t0);
9338 %}
9339
9340 ins_pipe(pipe_class_default);
9341 %}
9342
9343 instruct cmpLTMask_reg_reg(iRegINoSp dst, iRegI p, iRegI q)
9344 %{
9345 match(Set dst (CmpLTMask p q));
9346
9347 ins_cost(2 * ALU_COST);
9348
9349 format %{ "slt $dst, $p, $q\t#@cmpLTMask_reg_reg\n\t"
9350 "subw $dst, zr, $dst\t#@cmpLTMask_reg_reg"
9351 %}
9352
9353 ins_encode %{
9354 __ slt(as_Register($dst$$reg), as_Register($p$$reg), as_Register($q$$reg));
9355 __ subw(as_Register($dst$$reg), zr, as_Register($dst$$reg));
9356 %}
9357
9358 ins_pipe(ialu_reg_reg);
9359 %}
9360
9361 instruct cmpLTMask_reg_zero(iRegINoSp dst, iRegIorL2I op, immI0 zero)
9362 %{
9363 match(Set dst (CmpLTMask op zero));
9364
9365 ins_cost(ALU_COST);
9366
9367 format %{ "sraiw $dst, $dst, 31\t#@cmpLTMask_reg_reg" %}
9368
9369 ins_encode %{
9370 __ sraiw(as_Register($dst$$reg), as_Register($op$$reg), 31);
9371 %}
9372
9373 ins_pipe(ialu_reg_shift);
9374 %}
9375
9376
9377 // ============================================================================
9378 // Max and Min
9379
9380 instruct minI_reg_reg(iRegINoSp dst, iRegI src)
9381 %{
9382 match(Set dst (MinI dst src));
9383
9384 ins_cost(BRANCH_COST + ALU_COST);
9385 format %{"minI_reg_reg $dst, $dst, $src\t#@minI_reg_reg\n\t"%}
9386
9387 ins_encode %{
9388 __ cmov_gt(as_Register($dst$$reg), as_Register($src$$reg),
9389 as_Register($dst$$reg), as_Register($src$$reg));
9390 %}
9391
9392 ins_pipe(pipe_class_compare);
9393 %}
9394
9395 instruct maxI_reg_reg(iRegINoSp dst, iRegI src)
9396 %{
9397 match(Set dst (MaxI dst src));
9398
9399 ins_cost(BRANCH_COST + ALU_COST);
9400 format %{"maxI_reg_reg $dst, $dst, $src\t#@maxI_reg_reg\n\t"%}
9401
9402 ins_encode %{
9403 __ cmov_lt(as_Register($dst$$reg), as_Register($src$$reg),
9404 as_Register($dst$$reg), as_Register($src$$reg));
9405 %}
9406
9407 ins_pipe(pipe_class_compare);
9408 %}
9409
9410 // special case for comparing with zero
9411 // n.b. this is selected in preference to the rule above because it
9412 // avoids loading constant 0 into a source register
9413
9414 instruct minI_reg_zero(iRegINoSp dst, immI0 zero)
9415 %{
9416 match(Set dst (MinI dst zero));
9417 match(Set dst (MinI zero dst));
9418
9419 ins_cost(BRANCH_COST + ALU_COST);
9420 format %{"minI_reg_zero $dst, $dst, zr\t#@minI_reg_zero\n\t"%}
9421
9422 ins_encode %{
9423 __ cmov_gt(as_Register($dst$$reg), zr,
9424 as_Register($dst$$reg), zr);
9425 %}
9426
9427 ins_pipe(pipe_class_compare);
9428 %}
9429
9430 instruct maxI_reg_zero(iRegINoSp dst, immI0 zero)
9431 %{
9432 match(Set dst (MaxI dst zero));
9433 match(Set dst (MaxI zero dst));
9434
9435 ins_cost(BRANCH_COST + ALU_COST);
9436 format %{"maxI_reg_zero $dst, $dst, zr\t#@maxI_reg_zero\n\t"%}
9437
9438 ins_encode %{
9439 __ cmov_lt(as_Register($dst$$reg), zr,
9440 as_Register($dst$$reg), zr);
9441 %}
9442
9443 ins_pipe(pipe_class_compare);
9444 %}
9445
9446 instruct minI_rReg(iRegINoSp dst, iRegI src1, iRegI src2)
9447 %{
9448 match(Set dst (MinI src1 src2));
9449
9450 effect(DEF dst, USE src1, USE src2);
9451
9452 ins_cost(BRANCH_COST + ALU_COST * 2);
9453 format %{"minI_rReg $dst, $src1, $src2\t#@minI_rReg\n\t"%}
9454
9455 ins_encode %{
9456 __ mv(as_Register($dst$$reg), as_Register($src1$$reg));
9457 __ cmov_gt(as_Register($src1$$reg), as_Register($src2$$reg),
9458 as_Register($dst$$reg), as_Register($src2$$reg));
9459 %}
9460
9461 ins_pipe(pipe_class_compare);
9462 %}
9463
9464 instruct maxI_rReg(iRegINoSp dst, iRegI src1, iRegI src2)
9465 %{
9466 match(Set dst (MaxI src1 src2));
9467
9468 effect(DEF dst, USE src1, USE src2);
9469
9470 ins_cost(BRANCH_COST + ALU_COST * 2);
9471 format %{"maxI_rReg $dst, $src1, $src2\t#@maxI_rReg\n\t"%}
9472
9473 ins_encode %{
9474 __ mv(as_Register($dst$$reg), as_Register($src1$$reg));
9475 __ cmov_lt(as_Register($src1$$reg), as_Register($src2$$reg),
9476 as_Register($dst$$reg), as_Register($src2$$reg));
9477 %}
9478
9479 ins_pipe(pipe_class_compare);
9480 %}
9481
9482 // ============================================================================
9483 // Branch Instructions
9484 // Direct Branch.
9485 instruct branch(label lbl)
9486 %{
9487 match(Goto);
9488
9489 effect(USE lbl);
9490
9491 ins_cost(BRANCH_COST);
9492 format %{ "j $lbl\t#@branch" %}
9493
9494 ins_encode(riscv_enc_j(lbl));
9495
9496 ins_pipe(pipe_branch);
9497 %}
9498
9499 // ============================================================================
9500 // Compare and Branch Instructions
9501
9502 // Patterns for short (< 12KiB) variants
9503
9504 // Compare flags and branch near instructions.
9505 instruct cmpFlag_branch(cmpOpEqNe cmp, rFlagsReg cr, label lbl) %{
9506 match(If cmp cr);
9507 effect(USE lbl);
9508
9509 ins_cost(BRANCH_COST);
9510 format %{ "b$cmp $cr, zr, $lbl\t#@cmpFlag_branch" %}
9511
9512 ins_encode %{
9513 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($cr$$reg), *($lbl$$label));
9514 %}
9515 ins_pipe(pipe_cmpz_branch);
9516 ins_short_branch(1);
9517 %}
9518
9519 // Compare signed int and branch near instructions
9520 instruct cmpI_branch(cmpOp cmp, iRegI op1, iRegI op2, label lbl)
9521 %{
9522 // Same match rule as `far_cmpI_branch'.
9523 match(If cmp (CmpI op1 op2));
9524
9525 effect(USE lbl);
9526
9527 ins_cost(BRANCH_COST);
9528
9529 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpI_branch" %}
9530
9531 ins_encode %{
9532 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label));
9533 %}
9534
9535 ins_pipe(pipe_cmp_branch);
9536 ins_short_branch(1);
9537 %}
9538
9539 instruct cmpI_loop(cmpOp cmp, iRegI op1, iRegI op2, label lbl)
9540 %{
9541 // Same match rule as `far_cmpI_loop'.
9542 match(CountedLoopEnd cmp (CmpI op1 op2));
9543
9544 effect(USE lbl);
9545
9546 ins_cost(BRANCH_COST);
9547
9548 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpI_loop" %}
9549
9550 ins_encode %{
9551 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label));
9552 %}
9553
9554 ins_pipe(pipe_cmp_branch);
9555 ins_short_branch(1);
9556 %}
9557
9558 // Compare unsigned int and branch near instructions
9559 instruct cmpU_branch(cmpOpU cmp, iRegI op1, iRegI op2, label lbl)
9560 %{
9561 // Same match rule as `far_cmpU_branch'.
9562 match(If cmp (CmpU op1 op2));
9563
9564 effect(USE lbl);
9565
9566 ins_cost(BRANCH_COST);
9567
9568 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpU_branch" %}
9569
9570 ins_encode %{
9571 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9572 as_Register($op2$$reg), *($lbl$$label));
9573 %}
9574
9575 ins_pipe(pipe_cmp_branch);
9576 ins_short_branch(1);
9577 %}
9578
9579 // Compare signed long and branch near instructions
9580 instruct cmpL_branch(cmpOp cmp, iRegL op1, iRegL op2, label lbl)
9581 %{
9582 // Same match rule as `far_cmpL_branch'.
9583 match(If cmp (CmpL op1 op2));
9584
9585 effect(USE lbl);
9586
9587 ins_cost(BRANCH_COST);
9588
9589 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpL_branch" %}
9590
9591 ins_encode %{
9592 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label));
9593 %}
9594
9595 ins_pipe(pipe_cmp_branch);
9596 ins_short_branch(1);
9597 %}
9598
9599 instruct cmpL_loop(cmpOp cmp, iRegL op1, iRegL op2, label lbl)
9600 %{
9601 // Same match rule as `far_cmpL_loop'.
9602 match(CountedLoopEnd cmp (CmpL op1 op2));
9603
9604 effect(USE lbl);
9605
9606 ins_cost(BRANCH_COST);
9607
9608 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpL_loop" %}
9609
9610 ins_encode %{
9611 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label));
9612 %}
9613
9614 ins_pipe(pipe_cmp_branch);
9615 ins_short_branch(1);
9616 %}
9617
9618 // Compare unsigned long and branch near instructions
9619 instruct cmpUL_branch(cmpOpU cmp, iRegL op1, iRegL op2, label lbl)
9620 %{
9621 // Same match rule as `far_cmpUL_branch'.
9622 match(If cmp (CmpUL op1 op2));
9623
9624 effect(USE lbl);
9625
9626 ins_cost(BRANCH_COST);
9627 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpUL_branch" %}
9628
9629 ins_encode %{
9630 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9631 as_Register($op2$$reg), *($lbl$$label));
9632 %}
9633
9634 ins_pipe(pipe_cmp_branch);
9635 ins_short_branch(1);
9636 %}
9637
9638 // Compare pointer and branch near instructions
9639 instruct cmpP_branch(cmpOpU cmp, iRegP op1, iRegP op2, label lbl)
9640 %{
9641 // Same match rule as `far_cmpP_branch'.
9642 match(If cmp (CmpP op1 op2));
9643
9644 effect(USE lbl);
9645
9646 ins_cost(BRANCH_COST);
9647
9648 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpP_branch" %}
9649
9650 ins_encode %{
9651 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9652 as_Register($op2$$reg), *($lbl$$label));
9653 %}
9654
9655 ins_pipe(pipe_cmp_branch);
9656 ins_short_branch(1);
9657 %}
9658
9659 // Compare narrow pointer and branch near instructions
9660 instruct cmpN_branch(cmpOpU cmp, iRegN op1, iRegN op2, label lbl)
9661 %{
9662 // Same match rule as `far_cmpN_branch'.
9663 match(If cmp (CmpN op1 op2));
9664
9665 effect(USE lbl);
9666
9667 ins_cost(BRANCH_COST);
9668
9669 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpN_branch" %}
9670
9671 ins_encode %{
9672 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9673 as_Register($op2$$reg), *($lbl$$label));
9674 %}
9675
9676 ins_pipe(pipe_cmp_branch);
9677 ins_short_branch(1);
9678 %}
9679
9680 // Compare float and branch near instructions
9681 instruct cmpF_branch(cmpOp cmp, fRegF op1, fRegF op2, label lbl)
9682 %{
9683 // Same match rule as `far_cmpF_branch'.
9684 match(If cmp (CmpF op1 op2));
9685
9686 effect(USE lbl);
9687
9688 ins_cost(XFER_COST + BRANCH_COST);
9689 format %{ "float_b$cmp $op1, $op2, $lbl \t#@cmpF_branch"%}
9690
9691 ins_encode %{
9692 __ float_cmp_branch($cmp$$cmpcode, as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg), *($lbl$$label));
9693 %}
9694
9695 ins_pipe(pipe_class_compare);
9696 ins_short_branch(1);
9697 %}
9698
9699 // Compare double and branch near instructions
9700 instruct cmpD_branch(cmpOp cmp, fRegD op1, fRegD op2, label lbl)
9701 %{
9702 // Same match rule as `far_cmpD_branch'.
9703 match(If cmp (CmpD op1 op2));
9704 effect(USE lbl);
9705
9706 ins_cost(XFER_COST + BRANCH_COST);
9707 format %{ "double_b$cmp $op1, $op2, $lbl\t#@cmpD_branch"%}
9708
9709 ins_encode %{
9710 __ float_cmp_branch($cmp$$cmpcode | C2_MacroAssembler::double_branch_mask, as_FloatRegister($op1$$reg),
9711 as_FloatRegister($op2$$reg), *($lbl$$label));
9712 %}
9713
9714 ins_pipe(pipe_class_compare);
9715 ins_short_branch(1);
9716 %}
9717
9718 // Compare signed int with zero and branch near instructions
9719 instruct cmpI_reg_imm0_branch(cmpOp cmp, iRegI op1, immI0 zero, label lbl)
9720 %{
9721 // Same match rule as `far_cmpI_reg_imm0_branch'.
9722 match(If cmp (CmpI op1 zero));
9723
9724 effect(USE op1, USE lbl);
9725
9726 ins_cost(BRANCH_COST);
9727 format %{ "b$cmp $op1, zr, $lbl\t#@cmpI_reg_imm0_branch" %}
9728
9729 ins_encode %{
9730 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label));
9731 %}
9732
9733 ins_pipe(pipe_cmpz_branch);
9734 ins_short_branch(1);
9735 %}
9736
9737 instruct cmpI_reg_imm0_loop(cmpOp cmp, iRegI op1, immI0 zero, label lbl)
9738 %{
9739 // Same match rule as `far_cmpI_reg_imm0_loop'.
9740 match(CountedLoopEnd cmp (CmpI op1 zero));
9741
9742 effect(USE op1, USE lbl);
9743
9744 ins_cost(BRANCH_COST);
9745
9746 format %{ "b$cmp $op1, zr, $lbl\t#@cmpI_reg_imm0_loop" %}
9747
9748 ins_encode %{
9749 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label));
9750 %}
9751
9752 ins_pipe(pipe_cmpz_branch);
9753 ins_short_branch(1);
9754 %}
9755
9756 // Compare unsigned int with zero and branch near instructions
9757 instruct cmpUEqNeLeGt_reg_imm0_branch(cmpOpUEqNeLeGt cmp, iRegI op1, immI0 zero, label lbl)
9758 %{
9759 // Same match rule as `far_cmpUEqNeLeGt_reg_imm0_branch'.
9760 match(If cmp (CmpU op1 zero));
9761
9762 effect(USE op1, USE lbl);
9763
9764 ins_cost(BRANCH_COST);
9765
9766 format %{ "b$cmp $op1, zr, $lbl\t#@cmpUEqNeLeGt_reg_imm0_branch" %}
9767
9768 ins_encode %{
9769 __ enc_cmpUEqNeLeGt_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
9770 %}
9771
9772 ins_pipe(pipe_cmpz_branch);
9773 ins_short_branch(1);
9774 %}
9775
9776 // Compare signed long with zero and branch near instructions
9777 instruct cmpL_reg_imm0_branch(cmpOp cmp, iRegL op1, immL0 zero, label lbl)
9778 %{
9779 // Same match rule as `far_cmpL_reg_imm0_branch'.
9780 match(If cmp (CmpL op1 zero));
9781
9782 effect(USE op1, USE lbl);
9783
9784 ins_cost(BRANCH_COST);
9785
9786 format %{ "b$cmp $op1, zr, $lbl\t#@cmpL_reg_imm0_branch" %}
9787
9788 ins_encode %{
9789 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label));
9790 %}
9791
9792 ins_pipe(pipe_cmpz_branch);
9793 ins_short_branch(1);
9794 %}
9795
9796 instruct cmpL_reg_imm0_loop(cmpOp cmp, iRegL op1, immL0 zero, label lbl)
9797 %{
9798 // Same match rule as `far_cmpL_reg_imm0_loop'.
9799 match(CountedLoopEnd cmp (CmpL op1 zero));
9800
9801 effect(USE op1, USE lbl);
9802
9803 ins_cost(BRANCH_COST);
9804
9805 format %{ "b$cmp $op1, zr, $lbl\t#@cmpL_reg_imm0_loop" %}
9806
9807 ins_encode %{
9808 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label));
9809 %}
9810
9811 ins_pipe(pipe_cmpz_branch);
9812 ins_short_branch(1);
9813 %}
9814
9815 // Compare unsigned long with zero and branch near instructions
9816 instruct cmpULEqNeLeGt_reg_imm0_branch(cmpOpUEqNeLeGt cmp, iRegL op1, immL0 zero, label lbl)
9817 %{
9818 // Same match rule as `far_cmpULEqNeLeGt_reg_imm0_branch'.
9819 match(If cmp (CmpUL op1 zero));
9820
9821 effect(USE op1, USE lbl);
9822
9823 ins_cost(BRANCH_COST);
9824
9825 format %{ "b$cmp $op1, zr, $lbl\t#@cmpULEqNeLeGt_reg_imm0_branch" %}
9826
9827 ins_encode %{
9828 __ enc_cmpUEqNeLeGt_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
9829 %}
9830
9831 ins_pipe(pipe_cmpz_branch);
9832 ins_short_branch(1);
9833 %}
9834
9835 // Compare pointer with zero and branch near instructions
9836 instruct cmpP_imm0_branch(cmpOpEqNe cmp, iRegP op1, immP0 zero, label lbl) %{
9837 // Same match rule as `far_cmpP_reg_imm0_branch'.
9838 match(If cmp (CmpP op1 zero));
9839 effect(USE lbl);
9840
9841 ins_cost(BRANCH_COST);
9842 format %{ "b$cmp $op1, zr, $lbl\t#@cmpP_imm0_branch" %}
9843
9844 ins_encode %{
9845 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
9846 %}
9847
9848 ins_pipe(pipe_cmpz_branch);
9849 ins_short_branch(1);
9850 %}
9851
9852 // Compare narrow pointer with zero and branch near instructions
9853 instruct cmpN_imm0_branch(cmpOpEqNe cmp, iRegN op1, immN0 zero, label lbl) %{
9854 // Same match rule as `far_cmpN_reg_imm0_branch'.
9855 match(If cmp (CmpN op1 zero));
9856 effect(USE lbl);
9857
9858 ins_cost(BRANCH_COST);
9859
9860 format %{ "b$cmp $op1, zr, $lbl\t#@cmpN_imm0_branch" %}
9861
9862 ins_encode %{
9863 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
9864 %}
9865
9866 ins_pipe(pipe_cmpz_branch);
9867 ins_short_branch(1);
9868 %}
9869
9870 // Compare narrow pointer with pointer zero and branch near instructions
9871 instruct cmpP_narrowOop_imm0_branch(cmpOpEqNe cmp, iRegN op1, immP0 zero, label lbl) %{
9872 // Same match rule as `far_cmpP_narrowOop_imm0_branch'.
9873 match(If cmp (CmpP (DecodeN op1) zero));
9874 effect(USE lbl);
9875
9876 ins_cost(BRANCH_COST);
9877 format %{ "b$cmp $op1, zr, $lbl\t#@cmpP_narrowOop_imm0_branch" %}
9878
9879 ins_encode %{
9880 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
9881 %}
9882
9883 ins_pipe(pipe_cmpz_branch);
9884 ins_short_branch(1);
9885 %}
9886
9887 // Patterns for far (20KiB) variants
9888
9889 instruct far_cmpFlag_branch(cmpOp cmp, rFlagsReg cr, label lbl) %{
9890 match(If cmp cr);
9891 effect(USE lbl);
9892
9893 ins_cost(BRANCH_COST);
9894 format %{ "far_b$cmp $cr, zr, $lbl\t#@far_cmpFlag_branch"%}
9895
9896 ins_encode %{
9897 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($cr$$reg), *($lbl$$label), /* is_far */ true);
9898 %}
9899
9900 ins_pipe(pipe_cmpz_branch);
9901 %}
9902
9903 // Compare signed int and branch far instructions
9904 instruct far_cmpI_branch(cmpOp cmp, iRegI op1, iRegI op2, label lbl) %{
9905 match(If cmp (CmpI op1 op2));
9906 effect(USE lbl);
9907
9908 ins_cost(BRANCH_COST * 2);
9909
9910 // the format instruction [far_b$cmp] here is be used as two insructions
9911 // in macroassembler: b$not_cmp(op1, op2, done), j($lbl), bind(done)
9912 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpI_branch" %}
9913
9914 ins_encode %{
9915 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9916 %}
9917
9918 ins_pipe(pipe_cmp_branch);
9919 %}
9920
9921 instruct far_cmpI_loop(cmpOp cmp, iRegI op1, iRegI op2, label lbl) %{
9922 match(CountedLoopEnd cmp (CmpI op1 op2));
9923 effect(USE lbl);
9924
9925 ins_cost(BRANCH_COST * 2);
9926 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpI_loop" %}
9927
9928 ins_encode %{
9929 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9930 %}
9931
9932 ins_pipe(pipe_cmp_branch);
9933 %}
9934
9935 instruct far_cmpU_branch(cmpOpU cmp, iRegI op1, iRegI op2, label lbl) %{
9936 match(If cmp (CmpU op1 op2));
9937 effect(USE lbl);
9938
9939 ins_cost(BRANCH_COST * 2);
9940 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpU_branch" %}
9941
9942 ins_encode %{
9943 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9944 as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9945 %}
9946
9947 ins_pipe(pipe_cmp_branch);
9948 %}
9949
9950 instruct far_cmpL_branch(cmpOp cmp, iRegL op1, iRegL op2, label lbl) %{
9951 match(If cmp (CmpL op1 op2));
9952 effect(USE lbl);
9953
9954 ins_cost(BRANCH_COST * 2);
9955 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpL_branch" %}
9956
9957 ins_encode %{
9958 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9959 %}
9960
9961 ins_pipe(pipe_cmp_branch);
9962 %}
9963
9964 instruct far_cmpLloop(cmpOp cmp, iRegL op1, iRegL op2, label lbl) %{
9965 match(CountedLoopEnd cmp (CmpL op1 op2));
9966 effect(USE lbl);
9967
9968 ins_cost(BRANCH_COST * 2);
9969 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpL_loop" %}
9970
9971 ins_encode %{
9972 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9973 %}
9974
9975 ins_pipe(pipe_cmp_branch);
9976 %}
9977
9978 instruct far_cmpUL_branch(cmpOpU cmp, iRegL op1, iRegL op2, label lbl) %{
9979 match(If cmp (CmpUL op1 op2));
9980 effect(USE lbl);
9981
9982 ins_cost(BRANCH_COST * 2);
9983 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpUL_branch" %}
9984
9985 ins_encode %{
9986 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9987 as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9988 %}
9989
9990 ins_pipe(pipe_cmp_branch);
9991 %}
9992
9993 instruct far_cmpP_branch(cmpOpU cmp, iRegP op1, iRegP op2, label lbl)
9994 %{
9995 match(If cmp (CmpP op1 op2));
9996
9997 effect(USE lbl);
9998
9999 ins_cost(BRANCH_COST * 2);
10000
10001 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpP_branch" %}
10002
10003 ins_encode %{
10004 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
10005 as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
10006 %}
10007
10008 ins_pipe(pipe_cmp_branch);
10009 %}
10010
10011 instruct far_cmpN_branch(cmpOpU cmp, iRegN op1, iRegN op2, label lbl)
10012 %{
10013 match(If cmp (CmpN op1 op2));
10014
10015 effect(USE lbl);
10016
10017 ins_cost(BRANCH_COST * 2);
10018
10019 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpN_branch" %}
10020
10021 ins_encode %{
10022 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
10023 as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
10024 %}
10025
10026 ins_pipe(pipe_cmp_branch);
10027 %}
10028
10029 // Float compare and branch instructions
10030 instruct far_cmpF_branch(cmpOp cmp, fRegF op1, fRegF op2, label lbl)
10031 %{
10032 match(If cmp (CmpF op1 op2));
10033
10034 effect(USE lbl);
10035
10036 ins_cost(XFER_COST + BRANCH_COST * 2);
10037 format %{ "far_float_b$cmp $op1, $op2, $lbl\t#@far_cmpF_branch"%}
10038
10039 ins_encode %{
10040 __ float_cmp_branch($cmp$$cmpcode, as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg),
10041 *($lbl$$label), /* is_far */ true);
10042 %}
10043
10044 ins_pipe(pipe_class_compare);
10045 %}
10046
10047 // Double compare and branch instructions
10048 instruct far_cmpD_branch(cmpOp cmp, fRegD op1, fRegD op2, label lbl)
10049 %{
10050 match(If cmp (CmpD op1 op2));
10051 effect(USE lbl);
10052
10053 ins_cost(XFER_COST + BRANCH_COST * 2);
10054 format %{ "far_double_b$cmp $op1, $op2, $lbl\t#@far_cmpD_branch"%}
10055
10056 ins_encode %{
10057 __ float_cmp_branch($cmp$$cmpcode | C2_MacroAssembler::double_branch_mask, as_FloatRegister($op1$$reg),
10058 as_FloatRegister($op2$$reg), *($lbl$$label), /* is_far */ true);
10059 %}
10060
10061 ins_pipe(pipe_class_compare);
10062 %}
10063
10064 instruct far_cmpI_reg_imm0_branch(cmpOp cmp, iRegI op1, immI0 zero, label lbl)
10065 %{
10066 match(If cmp (CmpI op1 zero));
10067
10068 effect(USE op1, USE lbl);
10069
10070 ins_cost(BRANCH_COST * 2);
10071
10072 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpI_reg_imm0_branch" %}
10073
10074 ins_encode %{
10075 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label), /* is_far */ true);
10076 %}
10077
10078 ins_pipe(pipe_cmpz_branch);
10079 %}
10080
10081 instruct far_cmpI_reg_imm0_loop(cmpOp cmp, iRegI op1, immI0 zero, label lbl)
10082 %{
10083 match(CountedLoopEnd cmp (CmpI op1 zero));
10084
10085 effect(USE op1, USE lbl);
10086
10087 ins_cost(BRANCH_COST * 2);
10088
10089 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpI_reg_imm0_loop" %}
10090
10091 ins_encode %{
10092 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label), /* is_far */ true);
10093 %}
10094
10095 ins_pipe(pipe_cmpz_branch);
10096 %}
10097
10098 instruct far_cmpUEqNeLeGt_imm0_branch(cmpOpUEqNeLeGt cmp, iRegI op1, immI0 zero, label lbl)
10099 %{
10100 match(If cmp (CmpU op1 zero));
10101
10102 effect(USE op1, USE lbl);
10103
10104 ins_cost(BRANCH_COST * 2);
10105
10106 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpUEqNeLeGt_imm0_branch" %}
10107
10108 ins_encode %{
10109 __ enc_cmpUEqNeLeGt_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
10110 %}
10111
10112 ins_pipe(pipe_cmpz_branch);
10113 %}
10114
10115 // compare lt/ge unsigned instructs has no short instruct with same match
10116 instruct far_cmpULtGe_reg_imm0_branch(cmpOpULtGe cmp, iRegI op1, immI0 zero, label lbl)
10117 %{
10118 match(If cmp (CmpU op1 zero));
10119
10120 effect(USE op1, USE lbl);
10121
10122 ins_cost(BRANCH_COST);
10123
10124 format %{ "j $lbl if $cmp == ge\t#@far_cmpULtGe_reg_imm0_branch" %}
10125
10126 ins_encode(riscv_enc_far_cmpULtGe_imm0_branch(cmp, op1, lbl));
10127
10128 ins_pipe(pipe_cmpz_branch);
10129 %}
10130
10131 instruct far_cmpL_reg_imm0_branch(cmpOp cmp, iRegL op1, immL0 zero, label lbl)
10132 %{
10133 match(If cmp (CmpL op1 zero));
10134
10135 effect(USE op1, USE lbl);
10136
10137 ins_cost(BRANCH_COST * 2);
10138
10139 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpL_reg_imm0_branch" %}
10140
10141 ins_encode %{
10142 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label), /* is_far */ true);
10143 %}
10144
10145 ins_pipe(pipe_cmpz_branch);
10146 %}
10147
10148 instruct far_cmpL_reg_imm0_loop(cmpOp cmp, iRegL op1, immL0 zero, label lbl)
10149 %{
10150 match(CountedLoopEnd cmp (CmpL op1 zero));
10151
10152 effect(USE op1, USE lbl);
10153
10154 ins_cost(BRANCH_COST * 2);
10155
10156 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpL_reg_imm0_loop" %}
10157
10158 ins_encode %{
10159 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label), /* is_far */ true);
10160 %}
10161
10162 ins_pipe(pipe_cmpz_branch);
10163 %}
10164
10165 instruct far_cmpULEqNeLeGt_reg_imm0_branch(cmpOpUEqNeLeGt cmp, iRegL op1, immL0 zero, label lbl)
10166 %{
10167 match(If cmp (CmpUL op1 zero));
10168
10169 effect(USE op1, USE lbl);
10170
10171 ins_cost(BRANCH_COST * 2);
10172
10173 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpULEqNeLeGt_reg_imm0_branch" %}
10174
10175 ins_encode %{
10176 __ enc_cmpUEqNeLeGt_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
10177 %}
10178
10179 ins_pipe(pipe_cmpz_branch);
10180 %}
10181
10182 // compare lt/ge unsigned instructs has no short instruct with same match
10183 instruct far_cmpULLtGe_reg_imm0_branch(cmpOpULtGe cmp, iRegL op1, immL0 zero, label lbl)
10184 %{
10185 match(If cmp (CmpUL op1 zero));
10186
10187 effect(USE op1, USE lbl);
10188
10189 ins_cost(BRANCH_COST);
10190
10191 format %{ "j $lbl if $cmp == ge\t#@far_cmpULLtGe_reg_imm0_branch" %}
10192
10193 ins_encode(riscv_enc_far_cmpULtGe_imm0_branch(cmp, op1, lbl));
10194
10195 ins_pipe(pipe_cmpz_branch);
10196 %}
10197
10198 instruct far_cmpP_imm0_branch(cmpOpEqNe cmp, iRegP op1, immP0 zero, label lbl) %{
10199 match(If cmp (CmpP op1 zero));
10200 effect(USE lbl);
10201
10202 ins_cost(BRANCH_COST * 2);
10203 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpP_imm0_branch" %}
10204
10205 ins_encode %{
10206 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
10207 %}
10208
10209 ins_pipe(pipe_cmpz_branch);
10210 %}
10211
10212 instruct far_cmpN_imm0_branch(cmpOpEqNe cmp, iRegN op1, immN0 zero, label lbl) %{
10213 match(If cmp (CmpN op1 zero));
10214 effect(USE lbl);
10215
10216 ins_cost(BRANCH_COST * 2);
10217
10218 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpN_imm0_branch" %}
10219
10220 ins_encode %{
10221 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
10222 %}
10223
10224 ins_pipe(pipe_cmpz_branch);
10225 %}
10226
10227 instruct far_cmpP_narrowOop_imm0_branch(cmpOpEqNe cmp, iRegN op1, immP0 zero, label lbl) %{
10228 match(If cmp (CmpP (DecodeN op1) zero));
10229 effect(USE lbl);
10230
10231 ins_cost(BRANCH_COST * 2);
10232 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpP_narrowOop_imm0_branch" %}
10233
10234 ins_encode %{
10235 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
10236 %}
10237
10238 ins_pipe(pipe_cmpz_branch);
10239 %}
10240
10241 // ============================================================================
10242 // Conditional Move Instructions
10243
10244 // --------- CMoveI ---------
10245
10246 instruct cmovI_cmpI(iRegINoSp dst, iRegI src, iRegI op1, iRegI op2, cmpOp cop) %{
10247 match(Set dst (CMoveI (Binary cop (CmpI op1 op2)) (Binary dst src)));
10248 ins_cost(ALU_COST + BRANCH_COST);
10249
10250 format %{
10251 "CMoveI $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpI\n\t"
10252 %}
10253
10254 ins_encode %{
10255 __ enc_cmove($cop$$cmpcode,
10256 as_Register($op1$$reg), as_Register($op2$$reg),
10257 as_Register($dst$$reg), as_Register($src$$reg));
10258 %}
10259
10260 ins_pipe(pipe_class_compare);
10261 %}
10262
10263 instruct cmovI_cmpU(iRegINoSp dst, iRegI src, iRegI op1, iRegI op2, cmpOpU cop) %{
10264 match(Set dst (CMoveI (Binary cop (CmpU op1 op2)) (Binary dst src)));
10265 ins_cost(ALU_COST + BRANCH_COST);
10266
10267 format %{
10268 "CMoveI $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpU\n\t"
10269 %}
10270
10271 ins_encode %{
10272 __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10273 as_Register($op1$$reg), as_Register($op2$$reg),
10274 as_Register($dst$$reg), as_Register($src$$reg));
10275 %}
10276
10277 ins_pipe(pipe_class_compare);
10278 %}
10279
10280 instruct cmovI_cmpL(iRegINoSp dst, iRegI src, iRegL op1, iRegL op2, cmpOp cop) %{
10281 match(Set dst (CMoveI (Binary cop (CmpL op1 op2)) (Binary dst src)));
10282 ins_cost(ALU_COST + BRANCH_COST);
10283
10284 format %{
10285 "CMoveI $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpL\n\t"
10286 %}
10287
10288 ins_encode %{
10289 __ enc_cmove($cop$$cmpcode,
10290 as_Register($op1$$reg), as_Register($op2$$reg),
10291 as_Register($dst$$reg), as_Register($src$$reg));
10292 %}
10293
10294 ins_pipe(pipe_class_compare);
10295 %}
10296
10297 instruct cmovI_cmpUL(iRegINoSp dst, iRegI src, iRegL op1, iRegL op2, cmpOpU cop) %{
10298 match(Set dst (CMoveI (Binary cop (CmpUL op1 op2)) (Binary dst src)));
10299 ins_cost(ALU_COST + BRANCH_COST);
10300
10301 format %{
10302 "CMoveI $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpUL\n\t"
10303 %}
10304
10305 ins_encode %{
10306 __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10307 as_Register($op1$$reg), as_Register($op2$$reg),
10308 as_Register($dst$$reg), as_Register($src$$reg));
10309 %}
10310
10311 ins_pipe(pipe_class_compare);
10312 %}
10313
10314 instruct cmovI_cmpF(iRegINoSp dst, iRegI src, fRegF op1, fRegF op2, cmpOp cop) %{
10315 match(Set dst (CMoveI (Binary cop (CmpF op1 op2)) (Binary dst src)));
10316 ins_cost(ALU_COST + BRANCH_COST);
10317
10318 format %{
10319 "CMoveI $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpF\n\t"
10320 %}
10321
10322 ins_encode %{
10323 __ enc_cmove_cmp_fp($cop$$cmpcode,
10324 as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg),
10325 as_Register($dst$$reg), as_Register($src$$reg), true /* is_single */);
10326 %}
10327
10328 ins_pipe(pipe_class_compare);
10329 %}
10330
10331 instruct cmovI_cmpD(iRegINoSp dst, iRegI src, fRegD op1, fRegD op2, cmpOp cop) %{
10332 match(Set dst (CMoveI (Binary cop (CmpD op1 op2)) (Binary dst src)));
10333 ins_cost(ALU_COST + BRANCH_COST);
10334
10335 format %{
10336 "CMoveI $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpD\n\t"
10337 %}
10338
10339 ins_encode %{
10340 __ enc_cmove_cmp_fp($cop$$cmpcode | C2_MacroAssembler::double_branch_mask,
10341 as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg),
10342 as_Register($dst$$reg), as_Register($src$$reg), false /* is_single */);
10343 %}
10344
10345 ins_pipe(pipe_class_compare);
10346 %}
10347
10348 instruct cmovI_cmpN(iRegINoSp dst, iRegI src, iRegN op1, iRegN op2, cmpOpU cop) %{
10349 match(Set dst (CMoveI (Binary cop (CmpN op1 op2)) (Binary dst src)));
10350 ins_cost(ALU_COST + BRANCH_COST);
10351
10352 format %{
10353 "CMoveI $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpN\n\t"
10354 %}
10355
10356 ins_encode %{
10357 __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10358 as_Register($op1$$reg), as_Register($op2$$reg),
10359 as_Register($dst$$reg), as_Register($src$$reg));
10360 %}
10361
10362 ins_pipe(pipe_class_compare);
10363 %}
10364
10365 instruct cmovI_cmpP(iRegINoSp dst, iRegI src, iRegP op1, iRegP op2, cmpOpU cop) %{
10366 match(Set dst (CMoveI (Binary cop (CmpP op1 op2)) (Binary dst src)));
10367 ins_cost(ALU_COST + BRANCH_COST);
10368
10369 format %{
10370 "CMoveI $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpP\n\t"
10371 %}
10372
10373 ins_encode %{
10374 __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10375 as_Register($op1$$reg), as_Register($op2$$reg),
10376 as_Register($dst$$reg), as_Register($src$$reg));
10377 %}
10378
10379 ins_pipe(pipe_class_compare);
10380 %}
10381
10382 // --------- CMoveL ---------
10383
10384 instruct cmovL_cmpL(iRegLNoSp dst, iRegL src, iRegL op1, iRegL op2, cmpOp cop) %{
10385 match(Set dst (CMoveL (Binary cop (CmpL op1 op2)) (Binary dst src)));
10386 ins_cost(ALU_COST + BRANCH_COST);
10387
10388 format %{
10389 "CMoveL $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpL\n\t"
10390 %}
10391
10392 ins_encode %{
10393 __ enc_cmove($cop$$cmpcode,
10394 as_Register($op1$$reg), as_Register($op2$$reg),
10395 as_Register($dst$$reg), as_Register($src$$reg));
10396 %}
10397
10398 ins_pipe(pipe_class_compare);
10399 %}
10400
10401 instruct cmovL_cmpUL(iRegLNoSp dst, iRegL src, iRegL op1, iRegL op2, cmpOpU cop) %{
10402 match(Set dst (CMoveL (Binary cop (CmpUL op1 op2)) (Binary dst src)));
10403 ins_cost(ALU_COST + BRANCH_COST);
10404
10405 format %{
10406 "CMoveL $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpUL\n\t"
10407 %}
10408
10409 ins_encode %{
10410 __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10411 as_Register($op1$$reg), as_Register($op2$$reg),
10412 as_Register($dst$$reg), as_Register($src$$reg));
10413 %}
10414
10415 ins_pipe(pipe_class_compare);
10416 %}
10417
10418 instruct cmovL_cmpI(iRegLNoSp dst, iRegL src, iRegI op1, iRegI op2, cmpOp cop) %{
10419 match(Set dst (CMoveL (Binary cop (CmpI op1 op2)) (Binary dst src)));
10420 ins_cost(ALU_COST + BRANCH_COST);
10421
10422 format %{
10423 "CMoveL $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpI\n\t"
10424 %}
10425
10426 ins_encode %{
10427 __ enc_cmove($cop$$cmpcode,
10428 as_Register($op1$$reg), as_Register($op2$$reg),
10429 as_Register($dst$$reg), as_Register($src$$reg));
10430 %}
10431
10432 ins_pipe(pipe_class_compare);
10433 %}
10434
10435 instruct cmovL_cmpU(iRegLNoSp dst, iRegL src, iRegI op1, iRegI op2, cmpOpU cop) %{
10436 match(Set dst (CMoveL (Binary cop (CmpU op1 op2)) (Binary dst src)));
10437 ins_cost(ALU_COST + BRANCH_COST);
10438
10439 format %{
10440 "CMoveL $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpU\n\t"
10441 %}
10442
10443 ins_encode %{
10444 __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10445 as_Register($op1$$reg), as_Register($op2$$reg),
10446 as_Register($dst$$reg), as_Register($src$$reg));
10447 %}
10448
10449 ins_pipe(pipe_class_compare);
10450 %}
10451
10452 instruct cmovL_cmpF(iRegLNoSp dst, iRegL src, fRegF op1, fRegF op2, cmpOp cop) %{
10453 match(Set dst (CMoveL (Binary cop (CmpF op1 op2)) (Binary dst src)));
10454 ins_cost(ALU_COST + BRANCH_COST);
10455
10456 format %{
10457 "CMoveL $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpF\n\t"
10458 %}
10459
10460 ins_encode %{
10461 __ enc_cmove_cmp_fp($cop$$cmpcode,
10462 as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg),
10463 as_Register($dst$$reg), as_Register($src$$reg), true /* is_single */);
10464 %}
10465
10466 ins_pipe(pipe_class_compare);
10467 %}
10468
10469 instruct cmovL_cmpD(iRegLNoSp dst, iRegL src, fRegD op1, fRegD op2, cmpOp cop) %{
10470 match(Set dst (CMoveL (Binary cop (CmpD op1 op2)) (Binary dst src)));
10471 ins_cost(ALU_COST + BRANCH_COST);
10472
10473 format %{
10474 "CMoveL $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpD\n\t"
10475 %}
10476
10477 ins_encode %{
10478 __ enc_cmove_cmp_fp($cop$$cmpcode | C2_MacroAssembler::double_branch_mask,
10479 as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg),
10480 as_Register($dst$$reg), as_Register($src$$reg), false /* is_single */);
10481 %}
10482
10483 ins_pipe(pipe_class_compare);
10484 %}
10485
10486 instruct cmovL_cmpN(iRegLNoSp dst, iRegL src, iRegN op1, iRegN op2, cmpOpU cop) %{
10487 match(Set dst (CMoveL (Binary cop (CmpN op1 op2)) (Binary dst src)));
10488 ins_cost(ALU_COST + BRANCH_COST);
10489
10490 format %{
10491 "CMoveL $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpN\n\t"
10492 %}
10493
10494 ins_encode %{
10495 __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10496 as_Register($op1$$reg), as_Register($op2$$reg),
10497 as_Register($dst$$reg), as_Register($src$$reg));
10498 %}
10499
10500 ins_pipe(pipe_class_compare);
10501 %}
10502
10503 instruct cmovL_cmpP(iRegLNoSp dst, iRegL src, iRegP op1, iRegP op2, cmpOpU cop) %{
10504 match(Set dst (CMoveL (Binary cop (CmpP op1 op2)) (Binary dst src)));
10505 ins_cost(ALU_COST + BRANCH_COST);
10506
10507 format %{
10508 "CMoveL $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpP\n\t"
10509 %}
10510
10511 ins_encode %{
10512 __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10513 as_Register($op1$$reg), as_Register($op2$$reg),
10514 as_Register($dst$$reg), as_Register($src$$reg));
10515 %}
10516
10517 ins_pipe(pipe_class_compare);
10518 %}
10519
10520 // --------- CMoveF ---------
10521
10522 instruct cmovF_cmpI(fRegF dst, fRegF src, iRegI op1, iRegI op2, cmpOp cop) %{
10523 match(Set dst (CMoveF (Binary cop (CmpI op1 op2)) (Binary dst src)));
10524 ins_cost(ALU_COST + BRANCH_COST);
10525
10526 format %{
10527 "CMoveF $dst, ($op1 $cop $op2), $dst, $src\t#@cmovF_cmpI\n\t"
10528 %}
10529
10530 ins_encode %{
10531 __ enc_cmove_fp_cmp($cop$$cmpcode,
10532 as_Register($op1$$reg), as_Register($op2$$reg),
10533 as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg), true /* is_single */);
10534 %}
10535
10536 ins_pipe(pipe_class_compare);
10537 %}
10538
10539 instruct cmovF_cmpU(fRegF dst, fRegF src, iRegI op1, iRegI op2, cmpOpU cop) %{
10540 match(Set dst (CMoveF (Binary cop (CmpU op1 op2)) (Binary dst src)));
10541 ins_cost(ALU_COST + BRANCH_COST);
10542
10543 format %{
10544 "CMoveF $dst, ($op1 $cop $op2), $dst, $src\t#@cmovF_cmpU\n\t"
10545 %}
10546
10547 ins_encode %{
10548 __ enc_cmove_fp_cmp($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10549 as_Register($op1$$reg), as_Register($op2$$reg),
10550 as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg), true /* is_single */);
10551 %}
10552
10553 ins_pipe(pipe_class_compare);
10554 %}
10555
10556 instruct cmovF_cmpL(fRegF dst, fRegF src, iRegL op1, iRegL op2, cmpOp cop) %{
10557 match(Set dst (CMoveF (Binary cop (CmpL op1 op2)) (Binary dst src)));
10558 ins_cost(ALU_COST + BRANCH_COST);
10559
10560 format %{
10561 "CMoveF $dst, ($op1 $cop $op2), $dst, $src\t#@cmovF_cmpL\n\t"
10562 %}
10563
10564 ins_encode %{
10565 __ enc_cmove_fp_cmp($cop$$cmpcode,
10566 as_Register($op1$$reg), as_Register($op2$$reg),
10567 as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg), true /* is_single */);
10568 %}
10569
10570 ins_pipe(pipe_class_compare);
10571 %}
10572
10573 instruct cmovF_cmpUL(fRegF dst, fRegF src, iRegL op1, iRegL op2, cmpOpU cop) %{
10574 match(Set dst (CMoveF (Binary cop (CmpUL op1 op2)) (Binary dst src)));
10575 ins_cost(ALU_COST + BRANCH_COST);
10576
10577 format %{
10578 "CMoveF $dst, ($op1 $cop $op2), $dst, $src\t#@cmovF_cmpUL\n\t"
10579 %}
10580
10581 ins_encode %{
10582 __ enc_cmove_fp_cmp($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10583 as_Register($op1$$reg), as_Register($op2$$reg),
10584 as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg), true /* is_single */);
10585 %}
10586
10587 ins_pipe(pipe_class_compare);
10588 %}
10589
10590 instruct cmovF_cmpF(fRegF dst, fRegF src, fRegF op1, fRegF op2, cmpOp cop) %{
10591 match(Set dst (CMoveF (Binary cop (CmpF op1 op2)) (Binary dst src)));
10592 ins_cost(ALU_COST + BRANCH_COST);
10593
10594 format %{
10595 "CMoveF $dst, ($op1 $cop $op2), $dst, $src\t#@cmovF_cmpF\n\t"
10596 %}
10597
10598 ins_encode %{
10599 __ enc_cmove_fp_cmp_fp($cop$$cmpcode,
10600 as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg),
10601 as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg),
10602 true /* cmp_single */, true /* cmov_single */);
10603 %}
10604
10605 ins_pipe(pipe_class_compare);
10606 %}
10607
10608 instruct cmovF_cmpD(fRegF dst, fRegF src, fRegD op1, fRegD op2, cmpOp cop) %{
10609 match(Set dst (CMoveF (Binary cop (CmpD op1 op2)) (Binary dst src)));
10610 ins_cost(ALU_COST + BRANCH_COST);
10611
10612 format %{
10613 "CMoveF $dst, ($op1 $cop $op2), $dst, $src\t#@cmovF_cmpD\n\t"
10614 %}
10615
10616 ins_encode %{
10617 __ enc_cmove_fp_cmp_fp($cop$$cmpcode | C2_MacroAssembler::double_branch_mask,
10618 as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg),
10619 as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg),
10620 false /* cmp_single */, true /* cmov_single */);
10621 %}
10622
10623 ins_pipe(pipe_class_compare);
10624 %}
10625
10626 instruct cmovF_cmpN(fRegF dst, fRegF src, iRegN op1, iRegN op2, cmpOp cop) %{
10627 match(Set dst (CMoveF (Binary cop (CmpN op1 op2)) (Binary dst src)));
10628 ins_cost(ALU_COST + BRANCH_COST);
10629
10630 format %{
10631 "CMoveF $dst, ($op1 $cop $op2), $dst, $src\t#@cmovF_cmpN\n\t"
10632 %}
10633
10634 ins_encode %{
10635 __ enc_cmove_fp_cmp($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10636 as_Register($op1$$reg), as_Register($op2$$reg),
10637 as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg), true /* is_single */);
10638 %}
10639
10640 ins_pipe(pipe_class_compare);
10641 %}
10642
10643 instruct cmovF_cmpP(fRegF dst, fRegF src, iRegP op1, iRegP op2, cmpOp cop) %{
10644 match(Set dst (CMoveF (Binary cop (CmpP op1 op2)) (Binary dst src)));
10645 ins_cost(ALU_COST + BRANCH_COST);
10646
10647 format %{
10648 "CMoveF $dst, ($op1 $cop $op2), $dst, $src\t#@cmovF_cmpP\n\t"
10649 %}
10650
10651 ins_encode %{
10652 __ enc_cmove_fp_cmp($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10653 as_Register($op1$$reg), as_Register($op2$$reg),
10654 as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg), true /* is_single */);
10655 %}
10656
10657 ins_pipe(pipe_class_compare);
10658 %}
10659
10660 // --------- CMoveD ---------
10661
10662 instruct cmovD_cmpI(fRegD dst, fRegD src, iRegI op1, iRegI op2, cmpOp cop) %{
10663 match(Set dst (CMoveD (Binary cop (CmpI op1 op2)) (Binary dst src)));
10664 ins_cost(ALU_COST + BRANCH_COST);
10665
10666 format %{
10667 "CMoveD $dst, ($op1 $cop $op2), $dst, $src\t#@cmovD_cmpI\n\t"
10668 %}
10669
10670 ins_encode %{
10671 __ enc_cmove_fp_cmp($cop$$cmpcode,
10672 as_Register($op1$$reg), as_Register($op2$$reg),
10673 as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg), false /* is_single */);
10674 %}
10675
10676 ins_pipe(pipe_class_compare);
10677 %}
10678
10679 instruct cmovD_cmpU(fRegD dst, fRegD src, iRegI op1, iRegI op2, cmpOpU cop) %{
10680 match(Set dst (CMoveD (Binary cop (CmpU op1 op2)) (Binary dst src)));
10681 ins_cost(ALU_COST + BRANCH_COST);
10682
10683 format %{
10684 "CMoveD $dst, ($op1 $cop $op2), $dst, $src\t#@cmovD_cmpU\n\t"
10685 %}
10686
10687 ins_encode %{
10688 __ enc_cmove_fp_cmp($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10689 as_Register($op1$$reg), as_Register($op2$$reg),
10690 as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg), false /* is_single */);
10691 %}
10692
10693 ins_pipe(pipe_class_compare);
10694 %}
10695
10696 instruct cmovD_cmpL(fRegD dst, fRegD src, iRegL op1, iRegL op2, cmpOp cop) %{
10697 match(Set dst (CMoveD (Binary cop (CmpL op1 op2)) (Binary dst src)));
10698 ins_cost(ALU_COST + BRANCH_COST);
10699
10700 format %{
10701 "CMoveD $dst, ($op1 $cop $op2), $dst, $src\t#@cmovD_cmpL\n\t"
10702 %}
10703
10704 ins_encode %{
10705 __ enc_cmove_fp_cmp($cop$$cmpcode,
10706 as_Register($op1$$reg), as_Register($op2$$reg),
10707 as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg), false /* is_single */);
10708 %}
10709
10710 ins_pipe(pipe_class_compare);
10711 %}
10712
10713 instruct cmovD_cmpUL(fRegD dst, fRegD src, iRegL op1, iRegL op2, cmpOpU cop) %{
10714 match(Set dst (CMoveD (Binary cop (CmpUL op1 op2)) (Binary dst src)));
10715 ins_cost(ALU_COST + BRANCH_COST);
10716
10717 format %{
10718 "CMoveD $dst, ($op1 $cop $op2), $dst, $src\t#@cmovD_cmpUL\n\t"
10719 %}
10720
10721 ins_encode %{
10722 __ enc_cmove_fp_cmp($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10723 as_Register($op1$$reg), as_Register($op2$$reg),
10724 as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg), false /* is_single */);
10725 %}
10726
10727 ins_pipe(pipe_class_compare);
10728 %}
10729
10730 instruct cmovD_cmpF(fRegD dst, fRegD src, fRegF op1, fRegF op2, cmpOp cop) %{
10731 match(Set dst (CMoveD (Binary cop (CmpF op1 op2)) (Binary dst src)));
10732 ins_cost(ALU_COST + BRANCH_COST);
10733
10734 format %{
10735 "CMoveD $dst, ($op1 $cop $op2), $dst, $src\t#@cmovD_cmpF\n\t"
10736 %}
10737
10738 ins_encode %{
10739 __ enc_cmove_fp_cmp_fp($cop$$cmpcode,
10740 as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg),
10741 as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg),
10742 true /* cmp_single */, false /* cmov_single */);
10743 %}
10744
10745 ins_pipe(pipe_class_compare);
10746 %}
10747
10748 instruct cmovD_cmpD(fRegD dst, fRegD src, fRegD op1, fRegD op2, cmpOp cop) %{
10749 match(Set dst (CMoveD (Binary cop (CmpD op1 op2)) (Binary dst src)));
10750 ins_cost(ALU_COST + BRANCH_COST);
10751
10752 format %{
10753 "CMoveD $dst, ($op1 $cop $op2), $dst, $src\t#@cmovD_cmpD\n\t"
10754 %}
10755
10756 ins_encode %{
10757 __ enc_cmove_fp_cmp_fp($cop$$cmpcode | C2_MacroAssembler::double_branch_mask,
10758 as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg),
10759 as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg),
10760 false /* cmp_single */, false /* cmov_single */);
10761 %}
10762
10763 ins_pipe(pipe_class_compare);
10764 %}
10765
10766 instruct cmovD_cmpN(fRegD dst, fRegD src, iRegN op1, iRegN op2, cmpOp cop) %{
10767 match(Set dst (CMoveD (Binary cop (CmpN op1 op2)) (Binary dst src)));
10768 ins_cost(ALU_COST + BRANCH_COST);
10769
10770 format %{
10771 "CMoveD $dst, ($op1 $cop $op2), $dst, $src\t#@cmovD_cmpN\n\t"
10772 %}
10773
10774 ins_encode %{
10775 __ enc_cmove_fp_cmp($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10776 as_Register($op1$$reg), as_Register($op2$$reg),
10777 as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg), false /* is_single */);
10778 %}
10779
10780 ins_pipe(pipe_class_compare);
10781 %}
10782
10783 instruct cmovD_cmpP(fRegD dst, fRegD src, iRegP op1, iRegP op2, cmpOp cop) %{
10784 match(Set dst (CMoveD (Binary cop (CmpP op1 op2)) (Binary dst src)));
10785 ins_cost(ALU_COST + BRANCH_COST);
10786
10787 format %{
10788 "CMoveD $dst, ($op1 $cop $op2), $dst, $src\t#@cmovD_cmpP\n\t"
10789 %}
10790
10791 ins_encode %{
10792 __ enc_cmove_fp_cmp($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10793 as_Register($op1$$reg), as_Register($op2$$reg),
10794 as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg), false /* is_single */);
10795 %}
10796
10797 ins_pipe(pipe_class_compare);
10798 %}
10799
10800 // ============================================================================
10801 // Procedure Call/Return Instructions
10802
10803 // Call Java Static Instruction
10804 // Note: If this code changes, the corresponding ret_addr_offset() and
10805 // compute_padding() functions will have to be adjusted.
10806 instruct CallStaticJavaDirect(method meth)
10807 %{
10808 match(CallStaticJava);
10809
10810 effect(USE meth);
10811
10812 ins_cost(BRANCH_COST);
10813
10814 format %{ "CALL,static $meth\t#@CallStaticJavaDirect" %}
10815
10816 ins_encode(riscv_enc_java_static_call(meth),
10817 riscv_enc_call_epilog);
10818
10819 ins_pipe(pipe_class_call);
10820 ins_alignment(4);
10821 %}
10822
10823 // TO HERE
10824
10825 // Call Java Dynamic Instruction
10826 // Note: If this code changes, the corresponding ret_addr_offset() and
10827 // compute_padding() functions will have to be adjusted.
10828 instruct CallDynamicJavaDirect(method meth)
10829 %{
10830 match(CallDynamicJava);
10831
10832 effect(USE meth);
10833
10834 ins_cost(BRANCH_COST + ALU_COST * 5);
10835
10836 format %{ "CALL,dynamic $meth\t#@CallDynamicJavaDirect" %}
10837
10838 ins_encode(riscv_enc_java_dynamic_call(meth),
10839 riscv_enc_call_epilog);
10840
10841 ins_pipe(pipe_class_call);
10842 ins_alignment(4);
10843 %}
10844
10845 // Call Runtime Instruction
10846
10847 instruct CallRuntimeDirect(method meth)
10848 %{
10849 match(CallRuntime);
10850
10851 effect(USE meth);
10852
10853 ins_cost(BRANCH_COST);
10854
10855 format %{ "CALL, runtime $meth\t#@CallRuntimeDirect" %}
10856
10857 ins_encode(riscv_enc_java_to_runtime(meth));
10858
10859 ins_pipe(pipe_class_call);
10860 ins_alignment(4);
10861 %}
10862
10863 // Call Runtime Instruction
10864
10865 instruct CallLeafDirect(method meth)
10866 %{
10867 match(CallLeaf);
10868
10869 effect(USE meth);
10870
10871 ins_cost(BRANCH_COST);
10872
10873 format %{ "CALL, runtime leaf $meth\t#@CallLeafDirect" %}
10874
10875 ins_encode(riscv_enc_java_to_runtime(meth));
10876
10877 ins_pipe(pipe_class_call);
10878 ins_alignment(4);
10879 %}
10880
10881 // Call Runtime Instruction without safepoint and with vector arguments
10882
10883 instruct CallLeafDirectVector(method meth)
10884 %{
10885 match(CallLeafVector);
10886
10887 effect(USE meth);
10888
10889 ins_cost(BRANCH_COST);
10890
10891 format %{ "CALL, runtime leaf vector $meth" %}
10892
10893 ins_encode(riscv_enc_java_to_runtime(meth));
10894
10895 ins_pipe(pipe_class_call);
10896 ins_alignment(4);
10897 %}
10898
10899 // Call Runtime Instruction
10900
10901 instruct CallLeafNoFPDirect(method meth)
10902 %{
10903 match(CallLeafNoFP);
10904
10905 effect(USE meth);
10906
10907 ins_cost(BRANCH_COST);
10908
10909 format %{ "CALL, runtime leaf nofp $meth\t#@CallLeafNoFPDirect" %}
10910
10911 ins_encode(riscv_enc_java_to_runtime(meth));
10912
10913 ins_pipe(pipe_class_call);
10914 ins_alignment(4);
10915 %}
10916
10917 // ============================================================================
10918 // Partial Subtype Check
10919 //
10920 // superklass array for an instance of the superklass. Set a hidden
10921 // internal cache on a hit (cache is checked with exposed code in
10922 // gen_subtype_check()). Return zero for a hit. The encoding
10923 // ALSO sets flags.
10924
10925 instruct partialSubtypeCheck(iRegP_R15 result, iRegP_R14 sub, iRegP_R10 super, iRegP_R12 tmp, rFlagsReg cr)
10926 %{
10927 predicate(!UseSecondarySupersTable);
10928 match(Set result (PartialSubtypeCheck sub super));
10929 effect(KILL tmp, KILL cr);
10930
10931 ins_cost(20 * DEFAULT_COST);
10932 format %{ "partialSubtypeCheck $result, $sub, $super\t#@partialSubtypeCheck" %}
10933
10934 ins_encode(riscv_enc_partial_subtype_check(sub, super, tmp, result));
10935
10936 opcode(0x1); // Force zero of result reg on hit
10937
10938 ins_pipe(pipe_class_memory);
10939 %}
10940
10941 // Two versions of partialSubtypeCheck, both used when we need to
10942 // search for a super class in the secondary supers array. The first
10943 // is used when we don't know _a priori_ the class being searched
10944 // for. The second, far more common, is used when we do know: this is
10945 // used for instanceof, checkcast, and any case where C2 can determine
10946 // it by constant propagation.
10947
10948 instruct partialSubtypeCheckVarSuper(iRegP_R14 sub, iRegP_R10 super, iRegP_R15 result,
10949 iRegP_R11 tmpR11, iRegP_R12 tmpR12, iRegP_R13 tmpR13,
10950 iRegP_R16 tmpR16, rFlagsReg cr)
10951 %{
10952 predicate(UseSecondarySupersTable);
10953 match(Set result (PartialSubtypeCheck sub super));
10954 effect(TEMP tmpR11, TEMP tmpR12, TEMP tmpR13, TEMP tmpR16, KILL cr);
10955
10956 ins_cost(10 * DEFAULT_COST); // slightly larger than the next version
10957 format %{ "partialSubtypeCheck $result, $sub, $super" %}
10958
10959 ins_encode %{
10960 __ lookup_secondary_supers_table_var($sub$$Register, $super$$Register, $result$$Register,
10961 $tmpR11$$Register, $tmpR12$$Register, $tmpR13$$Register,
10962 $tmpR16$$Register, nullptr /*L_success*/);
10963 %}
10964
10965 ins_pipe(pipe_class_memory);
10966 %}
10967
10968 instruct partialSubtypeCheckConstSuper(iRegP_R14 sub, iRegP_R10 super_reg, immP super_con, iRegP_R15 result,
10969 iRegP_R11 tmpR11, iRegP_R12 tmpR12, iRegP_R13 tmpR13, iRegP_R16 tmpR16, rFlagsReg cr)
10970 %{
10971 predicate(UseSecondarySupersTable);
10972 match(Set result (PartialSubtypeCheck sub (Binary super_reg super_con)));
10973 effect(TEMP tmpR11, TEMP tmpR12, TEMP tmpR13, TEMP tmpR16, KILL cr);
10974
10975 ins_cost(5 * DEFAULT_COST); // needs to be less than competing nodes
10976 format %{ "partialSubtypeCheck $result, $sub, $super_reg, $super_con" %}
10977
10978 ins_encode %{
10979 bool success = false;
10980 u1 super_klass_slot = ((Klass*)$super_con$$constant)->hash_slot();
10981 if (InlineSecondarySupersTest) {
10982 success = __ lookup_secondary_supers_table_const($sub$$Register, $super_reg$$Register, $result$$Register,
10983 $tmpR11$$Register, $tmpR12$$Register, $tmpR13$$Register,
10984 $tmpR16$$Register, super_klass_slot);
10985 } else {
10986 address call = __ reloc_call(RuntimeAddress(StubRoutines::lookup_secondary_supers_table_stub(super_klass_slot)));
10987 success = (call != nullptr);
10988 }
10989 if (!success) {
10990 ciEnv::current()->record_failure("CodeCache is full");
10991 return;
10992 }
10993 %}
10994
10995 ins_pipe(pipe_class_memory);
10996 %}
10997
10998 instruct string_compareU(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
10999 iRegI_R10 result, iRegP_R28 tmp1, iRegL_R29 tmp2, iRegL_R30 tmp3, rFlagsReg cr)
11000 %{
11001 predicate(!UseRVV && ((StrCompNode *)n)->encoding() == StrIntrinsicNode::UU);
11002 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11003 effect(KILL tmp1, KILL tmp2, KILL tmp3, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11004
11005 format %{ "String Compare $str1, $cnt1, $str2, $cnt2 -> $result\t#@string_compareU" %}
11006 ins_encode %{
11007 // Count is in 8-bit bytes; non-Compact chars are 16 bits.
11008 __ string_compare($str1$$Register, $str2$$Register,
11009 $cnt1$$Register, $cnt2$$Register, $result$$Register,
11010 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
11011 StrIntrinsicNode::UU);
11012 %}
11013 ins_pipe(pipe_class_memory);
11014 %}
11015
11016 instruct string_compareL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
11017 iRegI_R10 result, iRegP_R28 tmp1, iRegL_R29 tmp2, iRegL_R30 tmp3, rFlagsReg cr)
11018 %{
11019 predicate(!UseRVV && ((StrCompNode *)n)->encoding() == StrIntrinsicNode::LL);
11020 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11021 effect(KILL tmp1, KILL tmp2, KILL tmp3, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11022
11023 format %{ "String Compare $str1, $cnt1, $str2, $cnt2 -> $result\t#@string_compareL" %}
11024 ins_encode %{
11025 __ string_compare($str1$$Register, $str2$$Register,
11026 $cnt1$$Register, $cnt2$$Register, $result$$Register,
11027 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
11028 StrIntrinsicNode::LL);
11029 %}
11030 ins_pipe(pipe_class_memory);
11031 %}
11032
11033 instruct string_compareUL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
11034 iRegI_R10 result, iRegP_R28 tmp1, iRegL_R29 tmp2, iRegL_R30 tmp3, rFlagsReg cr)
11035 %{
11036 predicate(!UseRVV && ((StrCompNode *)n)->encoding() == StrIntrinsicNode::UL);
11037 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11038 effect(KILL tmp1, KILL tmp2, KILL tmp3, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11039
11040 format %{"String Compare $str1, $cnt1, $str2, $cnt2 -> $result\t#@string_compareUL" %}
11041 ins_encode %{
11042 __ string_compare($str1$$Register, $str2$$Register,
11043 $cnt1$$Register, $cnt2$$Register, $result$$Register,
11044 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
11045 StrIntrinsicNode::UL);
11046 %}
11047 ins_pipe(pipe_class_memory);
11048 %}
11049
11050 instruct string_compareLU(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
11051 iRegI_R10 result, iRegP_R28 tmp1, iRegL_R29 tmp2, iRegL_R30 tmp3,
11052 rFlagsReg cr)
11053 %{
11054 predicate(!UseRVV && ((StrCompNode *)n)->encoding() == StrIntrinsicNode::LU);
11055 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11056 effect(KILL tmp1, KILL tmp2, KILL tmp3, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11057
11058 format %{ "String Compare $str1, $cnt1, $str2, $cnt2 -> $result\t#@string_compareLU" %}
11059 ins_encode %{
11060 __ string_compare($str1$$Register, $str2$$Register,
11061 $cnt1$$Register, $cnt2$$Register, $result$$Register,
11062 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
11063 StrIntrinsicNode::LU);
11064 %}
11065 ins_pipe(pipe_class_memory);
11066 %}
11067
11068 instruct string_indexofUU(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
11069 iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3,
11070 iRegINoSp tmp4, iRegINoSp tmp5, iRegINoSp tmp6, rFlagsReg cr)
11071 %{
11072 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU);
11073 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
11074 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, TEMP_DEF result,
11075 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, TEMP tmp6, KILL cr);
11076
11077 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result (UU)" %}
11078 ins_encode %{
11079 __ string_indexof($str1$$Register, $str2$$Register,
11080 $cnt1$$Register, $cnt2$$Register,
11081 $tmp1$$Register, $tmp2$$Register,
11082 $tmp3$$Register, $tmp4$$Register,
11083 $tmp5$$Register, $tmp6$$Register,
11084 $result$$Register, StrIntrinsicNode::UU);
11085 %}
11086 ins_pipe(pipe_class_memory);
11087 %}
11088
11089 instruct string_indexofLL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
11090 iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3,
11091 iRegINoSp tmp4, iRegINoSp tmp5, iRegINoSp tmp6, rFlagsReg cr)
11092 %{
11093 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL);
11094 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
11095 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, TEMP_DEF result,
11096 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, TEMP tmp6, KILL cr);
11097
11098 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result (LL)" %}
11099 ins_encode %{
11100 __ string_indexof($str1$$Register, $str2$$Register,
11101 $cnt1$$Register, $cnt2$$Register,
11102 $tmp1$$Register, $tmp2$$Register,
11103 $tmp3$$Register, $tmp4$$Register,
11104 $tmp5$$Register, $tmp6$$Register,
11105 $result$$Register, StrIntrinsicNode::LL);
11106 %}
11107 ins_pipe(pipe_class_memory);
11108 %}
11109
11110 instruct string_indexofUL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
11111 iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3,
11112 iRegINoSp tmp4, iRegINoSp tmp5, iRegINoSp tmp6, rFlagsReg cr)
11113 %{
11114 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL);
11115 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
11116 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, TEMP_DEF result,
11117 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, TEMP tmp6, KILL cr);
11118 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result (UL)" %}
11119
11120 ins_encode %{
11121 __ string_indexof($str1$$Register, $str2$$Register,
11122 $cnt1$$Register, $cnt2$$Register,
11123 $tmp1$$Register, $tmp2$$Register,
11124 $tmp3$$Register, $tmp4$$Register,
11125 $tmp5$$Register, $tmp6$$Register,
11126 $result$$Register, StrIntrinsicNode::UL);
11127 %}
11128 ins_pipe(pipe_class_memory);
11129 %}
11130
11131 instruct string_indexof_conUU(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2,
11132 immI_le_4 int_cnt2, iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2,
11133 iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
11134 %{
11135 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU);
11136 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
11137 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, TEMP_DEF result,
11138 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
11139
11140 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result (UU)" %}
11141
11142 ins_encode %{
11143 int icnt2 = (int)$int_cnt2$$constant;
11144 __ string_indexof_linearscan($str1$$Register, $str2$$Register,
11145 $cnt1$$Register, zr,
11146 $tmp1$$Register, $tmp2$$Register,
11147 $tmp3$$Register, $tmp4$$Register,
11148 icnt2, $result$$Register, StrIntrinsicNode::UU);
11149 %}
11150 ins_pipe(pipe_class_memory);
11151 %}
11152
11153 instruct string_indexof_conLL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2,
11154 immI_le_4 int_cnt2, iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2,
11155 iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
11156 %{
11157 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL);
11158 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
11159 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, TEMP_DEF result,
11160 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
11161
11162 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result (LL)" %}
11163 ins_encode %{
11164 int icnt2 = (int)$int_cnt2$$constant;
11165 __ string_indexof_linearscan($str1$$Register, $str2$$Register,
11166 $cnt1$$Register, zr,
11167 $tmp1$$Register, $tmp2$$Register,
11168 $tmp3$$Register, $tmp4$$Register,
11169 icnt2, $result$$Register, StrIntrinsicNode::LL);
11170 %}
11171 ins_pipe(pipe_class_memory);
11172 %}
11173
11174 instruct string_indexof_conUL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2,
11175 immI_1 int_cnt2, iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2,
11176 iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
11177 %{
11178 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL);
11179 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
11180 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, TEMP_DEF result,
11181 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
11182
11183 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result (UL)" %}
11184 ins_encode %{
11185 int icnt2 = (int)$int_cnt2$$constant;
11186 __ string_indexof_linearscan($str1$$Register, $str2$$Register,
11187 $cnt1$$Register, zr,
11188 $tmp1$$Register, $tmp2$$Register,
11189 $tmp3$$Register, $tmp4$$Register,
11190 icnt2, $result$$Register, StrIntrinsicNode::UL);
11191 %}
11192 ins_pipe(pipe_class_memory);
11193 %}
11194
11195 instruct stringU_indexof_char(iRegP_R11 str1, iRegI_R12 cnt1, iRegI_R13 ch,
11196 iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2,
11197 iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
11198 %{
11199 match(Set result (StrIndexOfChar (Binary str1 cnt1) ch));
11200 predicate(!UseRVV && (((StrIndexOfCharNode*)n)->encoding() == StrIntrinsicNode::U));
11201 effect(USE_KILL str1, USE_KILL cnt1, USE_KILL ch, TEMP_DEF result,
11202 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
11203
11204 format %{ "StringUTF16 IndexOf char[] $str1, $cnt1, $ch -> $result" %}
11205 ins_encode %{
11206 __ string_indexof_char($str1$$Register, $cnt1$$Register, $ch$$Register,
11207 $result$$Register, $tmp1$$Register, $tmp2$$Register,
11208 $tmp3$$Register, $tmp4$$Register, false /* isU */);
11209 %}
11210 ins_pipe(pipe_class_memory);
11211 %}
11212
11213
11214 instruct stringL_indexof_char(iRegP_R11 str1, iRegI_R12 cnt1, iRegI_R13 ch,
11215 iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2,
11216 iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
11217 %{
11218 match(Set result (StrIndexOfChar (Binary str1 cnt1) ch));
11219 predicate(!UseRVV && (((StrIndexOfCharNode*)n)->encoding() == StrIntrinsicNode::L));
11220 effect(USE_KILL str1, USE_KILL cnt1, USE_KILL ch, TEMP_DEF result,
11221 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
11222
11223 format %{ "StringLatin1 IndexOf char[] $str1, $cnt1, $ch -> $result" %}
11224 ins_encode %{
11225 __ string_indexof_char($str1$$Register, $cnt1$$Register, $ch$$Register,
11226 $result$$Register, $tmp1$$Register, $tmp2$$Register,
11227 $tmp3$$Register, $tmp4$$Register, true /* isL */);
11228 %}
11229 ins_pipe(pipe_class_memory);
11230 %}
11231
11232 // clearing of an array
11233 instruct clearArray_reg_reg(iRegL_R29 cnt, iRegP_R28 base, iRegP_R30 tmp1,
11234 iRegP_R31 tmp2, rFlagsReg cr, Universe dummy)
11235 %{
11236 // temp registers must match the one used in StubGenerator::generate_zero_blocks()
11237 predicate(UseBlockZeroing || !UseRVV);
11238 match(Set dummy (ClearArray cnt base));
11239 effect(USE_KILL cnt, USE_KILL base, TEMP tmp1, TEMP tmp2, KILL cr);
11240
11241 ins_cost(4 * DEFAULT_COST);
11242 format %{ "ClearArray $cnt, $base\t#@clearArray_reg_reg" %}
11243
11244 ins_encode %{
11245 address tpc = __ zero_words($base$$Register, $cnt$$Register);
11246 if (tpc == nullptr) {
11247 ciEnv::current()->record_failure("CodeCache is full");
11248 return;
11249 }
11250 %}
11251
11252 ins_pipe(pipe_class_memory);
11253 %}
11254
11255 instruct clearArray_imm_reg(immL cnt, iRegP_R28 base, Universe dummy, rFlagsReg cr)
11256 %{
11257 predicate(!UseRVV && (uint64_t)n->in(2)->get_long()
11258 < (uint64_t)(BlockZeroingLowLimit >> LogBytesPerWord));
11259 match(Set dummy (ClearArray cnt base));
11260 effect(USE_KILL base, KILL cr);
11261
11262 ins_cost(4 * DEFAULT_COST);
11263 format %{ "ClearArray $cnt, $base\t#@clearArray_imm_reg" %}
11264
11265 ins_encode %{
11266 __ zero_words($base$$Register, (uint64_t)$cnt$$constant);
11267 %}
11268
11269 ins_pipe(pipe_class_memory);
11270 %}
11271
11272 instruct string_equalsL(iRegP_R11 str1, iRegP_R13 str2, iRegI_R14 cnt,
11273 iRegI_R10 result, rFlagsReg cr)
11274 %{
11275 predicate(!UseRVV && ((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::LL);
11276 match(Set result (StrEquals (Binary str1 str2) cnt));
11277 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL cr);
11278
11279 format %{ "String Equals $str1, $str2, $cnt -> $result\t#@string_equalsL" %}
11280 ins_encode %{
11281 // Count is in 8-bit bytes; non-Compact chars are 16 bits.
11282 __ string_equals($str1$$Register, $str2$$Register,
11283 $result$$Register, $cnt$$Register);
11284 %}
11285 ins_pipe(pipe_class_memory);
11286 %}
11287
11288 instruct array_equalsB(iRegP_R11 ary1, iRegP_R12 ary2, iRegI_R10 result,
11289 iRegP_R13 tmp1, iRegP_R14 tmp2, iRegP_R15 tmp3)
11290 %{
11291 predicate(!UseRVV && ((AryEqNode*)n)->encoding() == StrIntrinsicNode::LL);
11292 match(Set result (AryEq ary1 ary2));
11293 effect(USE_KILL ary1, USE_KILL ary2, TEMP tmp1, TEMP tmp2, TEMP tmp3);
11294
11295 format %{ "Array Equals $ary1, $ary2 -> $result\t#@array_equalsB // KILL all" %}
11296 ins_encode %{
11297 __ arrays_equals($ary1$$Register, $ary2$$Register,
11298 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
11299 $result$$Register, 1);
11300 %}
11301 ins_pipe(pipe_class_memory);
11302 %}
11303
11304 instruct array_equalsC(iRegP_R11 ary1, iRegP_R12 ary2, iRegI_R10 result,
11305 iRegP_R13 tmp1, iRegP_R14 tmp2, iRegP_R15 tmp3)
11306 %{
11307 predicate(!UseRVV && ((AryEqNode*)n)->encoding() == StrIntrinsicNode::UU);
11308 match(Set result (AryEq ary1 ary2));
11309 effect(USE_KILL ary1, USE_KILL ary2, TEMP tmp1, TEMP tmp2, TEMP tmp3);
11310
11311 format %{ "Array Equals $ary1, $ary2 -> $result\t#@array_equalsC // KILL all" %}
11312 ins_encode %{
11313 __ arrays_equals($ary1$$Register, $ary2$$Register,
11314 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
11315 $result$$Register, 2);
11316 %}
11317 ins_pipe(pipe_class_memory);
11318 %}
11319
11320 // fast ArraysSupport.vectorizedHashCode
11321 instruct arrays_hashcode(iRegP_R11 ary, iRegI_R12 cnt, iRegI_R10 result, immI basic_type,
11322 iRegLNoSp tmp1, iRegLNoSp tmp2,
11323 iRegLNoSp tmp3, iRegLNoSp tmp4,
11324 iRegLNoSp tmp5, iRegLNoSp tmp6, rFlagsReg cr)
11325 %{
11326 predicate(!UseRVV);
11327 match(Set result (VectorizedHashCode (Binary ary cnt) (Binary result basic_type)));
11328 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, TEMP tmp6,
11329 USE_KILL ary, USE_KILL cnt, USE basic_type, KILL cr);
11330
11331 format %{ "Array HashCode array[] $ary,$cnt,$result,$basic_type -> $result // KILL all" %}
11332 ins_encode %{
11333 __ arrays_hashcode($ary$$Register, $cnt$$Register, $result$$Register,
11334 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
11335 $tmp4$$Register, $tmp5$$Register, $tmp6$$Register,
11336 (BasicType)$basic_type$$constant);
11337 %}
11338 ins_pipe(pipe_class_memory);
11339 %}
11340
11341 // ============================================================================
11342 // Safepoint Instructions
11343
11344 instruct safePoint(iRegP poll)
11345 %{
11346 match(SafePoint poll);
11347
11348 ins_cost(2 * LOAD_COST);
11349 format %{
11350 "lwu zr, [$poll]\t# Safepoint: poll for GC, #@safePoint"
11351 %}
11352 ins_encode %{
11353 __ read_polling_page(as_Register($poll$$reg), 0, relocInfo::poll_type);
11354 %}
11355 ins_pipe(pipe_serial); // ins_pipe(iload_reg_mem);
11356 %}
11357
11358 // ============================================================================
11359 // This name is KNOWN by the ADLC and cannot be changed.
11360 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
11361 // for this guy.
11362 instruct tlsLoadP(javaThread_RegP dst)
11363 %{
11364 match(Set dst (ThreadLocal));
11365
11366 ins_cost(0);
11367
11368 format %{ " -- \t// $dst=Thread::current(), empty, #@tlsLoadP" %}
11369
11370 size(0);
11371
11372 ins_encode( /*empty*/ );
11373
11374 ins_pipe(pipe_class_empty);
11375 %}
11376
11377 // inlined locking and unlocking
11378 // using t1 as the 'flag' register to bridge the BoolNode producers and consumers
11379 instruct cmpFastLock(rFlagsReg cr, iRegP object, iRegP box,
11380 iRegPNoSp tmp1, iRegPNoSp tmp2, iRegPNoSp tmp3, iRegPNoSp tmp4)
11381 %{
11382 match(Set cr (FastLock object box));
11383 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4);
11384
11385 ins_cost(10 * DEFAULT_COST);
11386 format %{ "fastlock $object,$box\t! kills $tmp1,$tmp2,$tmp3,$tmp4 #@cmpFastLock" %}
11387
11388 ins_encode %{
11389 __ fast_lock($object$$Register, $box$$Register,
11390 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register);
11391 %}
11392
11393 ins_pipe(pipe_serial);
11394 %}
11395
11396 // using t1 as the 'flag' register to bridge the BoolNode producers and consumers
11397 instruct cmpFastUnlock(rFlagsReg cr, iRegP object, iRegP box,
11398 iRegPNoSp tmp1, iRegPNoSp tmp2, iRegPNoSp tmp3)
11399 %{
11400 match(Set cr (FastUnlock object box));
11401 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3);
11402
11403 ins_cost(10 * DEFAULT_COST);
11404 format %{ "fastunlock $object,$box\t! kills $tmp1,$tmp2,$tmp3 #@cmpFastUnlock" %}
11405
11406 ins_encode %{
11407 __ fast_unlock($object$$Register, $box$$Register,
11408 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
11409 %}
11410
11411 ins_pipe(pipe_serial);
11412 %}
11413
11414 // Tail Call; Jump from runtime stub to Java code.
11415 // Also known as an 'interprocedural jump'.
11416 // Target of jump will eventually return to caller.
11417 // TailJump below removes the return address.
11418 // Don't use fp for 'jump_target' because a MachEpilogNode has already been
11419 // emitted just above the TailCall which has reset fp to the caller state.
11420 instruct TailCalljmpInd(iRegPNoSpNoFp jump_target, inline_cache_RegP method_oop)
11421 %{
11422 match(TailCall jump_target method_oop);
11423
11424 ins_cost(BRANCH_COST);
11425
11426 format %{ "jalr $jump_target\t# $method_oop holds method oop, #@TailCalljmpInd." %}
11427
11428 ins_encode(riscv_enc_tail_call(jump_target));
11429
11430 ins_pipe(pipe_class_call);
11431 %}
11432
11433 instruct TailjmpInd(iRegPNoSpNoFp jump_target, iRegP_R10 ex_oop)
11434 %{
11435 match(TailJump jump_target ex_oop);
11436
11437 ins_cost(ALU_COST + BRANCH_COST);
11438
11439 format %{ "jalr $jump_target\t# $ex_oop holds exception oop, #@TailjmpInd." %}
11440
11441 ins_encode(riscv_enc_tail_jmp(jump_target));
11442
11443 ins_pipe(pipe_class_call);
11444 %}
11445
11446 // Forward exception.
11447 instruct ForwardExceptionjmp()
11448 %{
11449 match(ForwardException);
11450
11451 ins_cost(BRANCH_COST);
11452
11453 format %{ "j forward_exception_stub\t#@ForwardException" %}
11454
11455 ins_encode %{
11456 __ far_jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
11457 %}
11458
11459 ins_pipe(pipe_class_call);
11460 %}
11461
11462 // Create exception oop: created by stack-crawling runtime code.
11463 // Created exception is now available to this handler, and is setup
11464 // just prior to jumping to this handler. No code emitted.
11465 instruct CreateException(iRegP_R10 ex_oop)
11466 %{
11467 match(Set ex_oop (CreateEx));
11468
11469 ins_cost(0);
11470 format %{ " -- \t// exception oop; no code emitted, #@CreateException" %}
11471
11472 size(0);
11473
11474 ins_encode( /*empty*/ );
11475
11476 ins_pipe(pipe_class_empty);
11477 %}
11478
11479 // Rethrow exception: The exception oop will come in the first
11480 // argument position. Then JUMP (not call) to the rethrow stub code.
11481 instruct RethrowException()
11482 %{
11483 match(Rethrow);
11484
11485 ins_cost(BRANCH_COST);
11486
11487 format %{ "j rethrow_stub\t#@RethrowException" %}
11488
11489 ins_encode(riscv_enc_rethrow());
11490
11491 ins_pipe(pipe_class_call);
11492 %}
11493
11494 // Return Instruction
11495 // epilog node loads ret address into ra as part of frame pop
11496 instruct Ret()
11497 %{
11498 match(Return);
11499
11500 ins_cost(BRANCH_COST);
11501 format %{ "ret\t// return register, #@Ret" %}
11502
11503 ins_encode(riscv_enc_ret());
11504
11505 ins_pipe(pipe_branch);
11506 %}
11507
11508 // Die now.
11509 instruct ShouldNotReachHere() %{
11510 match(Halt);
11511
11512 ins_cost(BRANCH_COST);
11513
11514 format %{ "#@ShouldNotReachHere" %}
11515
11516 ins_encode %{
11517 if (is_reachable()) {
11518 const char* str = __ code_string(_halt_reason);
11519 __ stop(str);
11520 }
11521 %}
11522
11523 ins_pipe(pipe_class_default);
11524 %}
11525
11526
11527 //----------PEEPHOLE RULES-----------------------------------------------------
11528 // These must follow all instruction definitions as they use the names
11529 // defined in the instructions definitions.
11530 //
11531 // peepmatch ( root_instr_name [preceding_instruction]* );
11532 //
11533 // peepconstraint %{
11534 // (instruction_number.operand_name relational_op instruction_number.operand_name
11535 // [, ...] );
11536 // // instruction numbers are zero-based using left to right order in peepmatch
11537 //
11538 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
11539 // // provide an instruction_number.operand_name for each operand that appears
11540 // // in the replacement instruction's match rule
11541 //
11542 // ---------VM FLAGS---------------------------------------------------------
11543 //
11544 // All peephole optimizations can be turned off using -XX:-OptoPeephole
11545 //
11546 // Each peephole rule is given an identifying number starting with zero and
11547 // increasing by one in the order seen by the parser. An individual peephole
11548 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
11549 // on the command-line.
11550 //
11551 // ---------CURRENT LIMITATIONS----------------------------------------------
11552 //
11553 // Only match adjacent instructions in same basic block
11554 // Only equality constraints
11555 // Only constraints between operands, not (0.dest_reg == RAX_enc)
11556 // Only one replacement instruction
11557 //
11558 //----------SMARTSPILL RULES---------------------------------------------------
11559 // These must follow all instruction definitions as they use the names
11560 // defined in the instructions definitions.
11561
11562 // Local Variables:
11563 // mode: c++
11564 // End: