1 //
2 // Copyright (c) 2003, 2023, Oracle and/or its affiliates. All rights reserved.
3 // Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
4 // Copyright (c) 2020, 2023, Huawei Technologies Co., Ltd. All rights reserved.
5 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
6 //
7 // This code is free software; you can redistribute it and/or modify it
8 // under the terms of the GNU General Public License version 2 only, as
9 // published by the Free Software Foundation.
10 //
11 // This code is distributed in the hope that it will be useful, but WITHOUT
12 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 // version 2 for more details (a copy is included in the LICENSE file that
15 // accompanied this code).
16 //
17 // You should have received a copy of the GNU General Public License version
18 // 2 along with this work; if not, write to the Free Software Foundation,
19 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
20 //
21 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
22 // or visit www.oracle.com if you need additional information or have any
23 // questions.
24 //
25 //
26
27 // RISCV Architecture Description File
28
29 //----------REGISTER DEFINITION BLOCK------------------------------------------
30 // This information is used by the matcher and the register allocator to
31 // describe individual registers and classes of registers within the target
32 // architecture.
33
34 register %{
35 //----------Architecture Description Register Definitions----------------------
36 // General Registers
37 // "reg_def" name ( register save type, C convention save type,
38 // ideal register type, encoding );
39 // Register Save Types:
40 //
41 // NS = No-Save: The register allocator assumes that these registers
42 // can be used without saving upon entry to the method, &
43 // that they do not need to be saved at call sites.
44 //
45 // SOC = Save-On-Call: The register allocator assumes that these registers
46 // can be used without saving upon entry to the method,
47 // but that they must be saved at call sites.
48 //
49 // SOE = Save-On-Entry: The register allocator assumes that these registers
50 // must be saved before using them upon entry to the
51 // method, but they do not need to be saved at call
52 // sites.
53 //
54 // AS = Always-Save: The register allocator assumes that these registers
55 // must be saved before using them upon entry to the
56 // method, & that they must be saved at call sites.
57 //
58 // Ideal Register Type is used to determine how to save & restore a
59 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
60 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
61 //
62 // The encoding number is the actual bit-pattern placed into the opcodes.
63
64 // We must define the 64 bit int registers in two 32 bit halves, the
65 // real lower register and a virtual upper half register. upper halves
66 // are used by the register allocator but are not actually supplied as
67 // operands to memory ops.
68 //
69 // follow the C1 compiler in making registers
70 //
71 // x7, x9-x17, x27-x31 volatile (caller save)
72 // x0-x4, x8, x23 system (no save, no allocate)
73 // x5-x6 non-allocatable (so we can use them as temporary regs)
74
75 //
76 // as regards Java usage. we don't use any callee save registers
77 // because this makes it difficult to de-optimise a frame (see comment
78 // in x86 implementation of Deoptimization::unwind_callee_save_values)
79 //
80
81 // General Registers
82
83 reg_def R0 ( NS, NS, Op_RegI, 0, x0->as_VMReg() ); // zr
84 reg_def R0_H ( NS, NS, Op_RegI, 0, x0->as_VMReg()->next() );
85 reg_def R1 ( NS, SOC, Op_RegI, 1, x1->as_VMReg() ); // ra
86 reg_def R1_H ( NS, SOC, Op_RegI, 1, x1->as_VMReg()->next() );
87 reg_def R2 ( NS, SOE, Op_RegI, 2, x2->as_VMReg() ); // sp
88 reg_def R2_H ( NS, SOE, Op_RegI, 2, x2->as_VMReg()->next() );
89 reg_def R3 ( NS, NS, Op_RegI, 3, x3->as_VMReg() ); // gp
90 reg_def R3_H ( NS, NS, Op_RegI, 3, x3->as_VMReg()->next() );
91 reg_def R4 ( NS, NS, Op_RegI, 4, x4->as_VMReg() ); // tp
92 reg_def R4_H ( NS, NS, Op_RegI, 4, x4->as_VMReg()->next() );
93 reg_def R7 ( SOC, SOC, Op_RegI, 7, x7->as_VMReg() );
94 reg_def R7_H ( SOC, SOC, Op_RegI, 7, x7->as_VMReg()->next() );
95 reg_def R8 ( NS, SOE, Op_RegI, 8, x8->as_VMReg() ); // fp
96 reg_def R8_H ( NS, SOE, Op_RegI, 8, x8->as_VMReg()->next() );
97 reg_def R9 ( SOC, SOE, Op_RegI, 9, x9->as_VMReg() );
98 reg_def R9_H ( SOC, SOE, Op_RegI, 9, x9->as_VMReg()->next() );
99 reg_def R10 ( SOC, SOC, Op_RegI, 10, x10->as_VMReg() );
100 reg_def R10_H ( SOC, SOC, Op_RegI, 10, x10->as_VMReg()->next());
101 reg_def R11 ( SOC, SOC, Op_RegI, 11, x11->as_VMReg() );
102 reg_def R11_H ( SOC, SOC, Op_RegI, 11, x11->as_VMReg()->next());
103 reg_def R12 ( SOC, SOC, Op_RegI, 12, x12->as_VMReg() );
104 reg_def R12_H ( SOC, SOC, Op_RegI, 12, x12->as_VMReg()->next());
105 reg_def R13 ( SOC, SOC, Op_RegI, 13, x13->as_VMReg() );
106 reg_def R13_H ( SOC, SOC, Op_RegI, 13, x13->as_VMReg()->next());
107 reg_def R14 ( SOC, SOC, Op_RegI, 14, x14->as_VMReg() );
108 reg_def R14_H ( SOC, SOC, Op_RegI, 14, x14->as_VMReg()->next());
109 reg_def R15 ( SOC, SOC, Op_RegI, 15, x15->as_VMReg() );
110 reg_def R15_H ( SOC, SOC, Op_RegI, 15, x15->as_VMReg()->next());
111 reg_def R16 ( SOC, SOC, Op_RegI, 16, x16->as_VMReg() );
112 reg_def R16_H ( SOC, SOC, Op_RegI, 16, x16->as_VMReg()->next());
113 reg_def R17 ( SOC, SOC, Op_RegI, 17, x17->as_VMReg() );
114 reg_def R17_H ( SOC, SOC, Op_RegI, 17, x17->as_VMReg()->next());
115 reg_def R18 ( SOC, SOE, Op_RegI, 18, x18->as_VMReg() );
116 reg_def R18_H ( SOC, SOE, Op_RegI, 18, x18->as_VMReg()->next());
117 reg_def R19 ( SOC, SOE, Op_RegI, 19, x19->as_VMReg() );
118 reg_def R19_H ( SOC, SOE, Op_RegI, 19, x19->as_VMReg()->next());
119 reg_def R20 ( SOC, SOE, Op_RegI, 20, x20->as_VMReg() ); // caller esp
120 reg_def R20_H ( SOC, SOE, Op_RegI, 20, x20->as_VMReg()->next());
121 reg_def R21 ( SOC, SOE, Op_RegI, 21, x21->as_VMReg() );
122 reg_def R21_H ( SOC, SOE, Op_RegI, 21, x21->as_VMReg()->next());
123 reg_def R22 ( SOC, SOE, Op_RegI, 22, x22->as_VMReg() );
124 reg_def R22_H ( SOC, SOE, Op_RegI, 22, x22->as_VMReg()->next());
125 reg_def R23 ( NS, SOE, Op_RegI, 23, x23->as_VMReg() ); // java thread
126 reg_def R23_H ( NS, SOE, Op_RegI, 23, x23->as_VMReg()->next());
127 reg_def R24 ( SOC, SOE, Op_RegI, 24, x24->as_VMReg() );
128 reg_def R24_H ( SOC, SOE, Op_RegI, 24, x24->as_VMReg()->next());
129 reg_def R25 ( SOC, SOE, Op_RegI, 25, x25->as_VMReg() );
130 reg_def R25_H ( SOC, SOE, Op_RegI, 25, x25->as_VMReg()->next());
131 reg_def R26 ( SOC, SOE, Op_RegI, 26, x26->as_VMReg() );
132 reg_def R26_H ( SOC, SOE, Op_RegI, 26, x26->as_VMReg()->next());
133 reg_def R27 ( SOC, SOE, Op_RegI, 27, x27->as_VMReg() ); // heapbase
134 reg_def R27_H ( SOC, SOE, Op_RegI, 27, x27->as_VMReg()->next());
135 reg_def R28 ( SOC, SOC, Op_RegI, 28, x28->as_VMReg() );
136 reg_def R28_H ( SOC, SOC, Op_RegI, 28, x28->as_VMReg()->next());
137 reg_def R29 ( SOC, SOC, Op_RegI, 29, x29->as_VMReg() );
138 reg_def R29_H ( SOC, SOC, Op_RegI, 29, x29->as_VMReg()->next());
139 reg_def R30 ( SOC, SOC, Op_RegI, 30, x30->as_VMReg() );
140 reg_def R30_H ( SOC, SOC, Op_RegI, 30, x30->as_VMReg()->next());
141 reg_def R31 ( SOC, SOC, Op_RegI, 31, x31->as_VMReg() );
142 reg_def R31_H ( SOC, SOC, Op_RegI, 31, x31->as_VMReg()->next());
143
144 // ----------------------------
145 // Float/Double Registers
146 // ----------------------------
147
148 // Double Registers
149
150 // The rules of ADL require that double registers be defined in pairs.
151 // Each pair must be two 32-bit values, but not necessarily a pair of
152 // single float registers. In each pair, ADLC-assigned register numbers
153 // must be adjacent, with the lower number even. Finally, when the
154 // CPU stores such a register pair to memory, the word associated with
155 // the lower ADLC-assigned number must be stored to the lower address.
156
157 // RISCV has 32 floating-point registers. Each can store a single
158 // or double precision floating-point value.
159
160 // for Java use float registers f0-f31 are always save on call whereas
161 // the platform ABI treats f8-f9 and f18-f27 as callee save). Other
162 // float registers are SOC as per the platform spec
163
164 reg_def F0 ( SOC, SOC, Op_RegF, 0, f0->as_VMReg() );
165 reg_def F0_H ( SOC, SOC, Op_RegF, 0, f0->as_VMReg()->next() );
166 reg_def F1 ( SOC, SOC, Op_RegF, 1, f1->as_VMReg() );
167 reg_def F1_H ( SOC, SOC, Op_RegF, 1, f1->as_VMReg()->next() );
168 reg_def F2 ( SOC, SOC, Op_RegF, 2, f2->as_VMReg() );
169 reg_def F2_H ( SOC, SOC, Op_RegF, 2, f2->as_VMReg()->next() );
170 reg_def F3 ( SOC, SOC, Op_RegF, 3, f3->as_VMReg() );
171 reg_def F3_H ( SOC, SOC, Op_RegF, 3, f3->as_VMReg()->next() );
172 reg_def F4 ( SOC, SOC, Op_RegF, 4, f4->as_VMReg() );
173 reg_def F4_H ( SOC, SOC, Op_RegF, 4, f4->as_VMReg()->next() );
174 reg_def F5 ( SOC, SOC, Op_RegF, 5, f5->as_VMReg() );
175 reg_def F5_H ( SOC, SOC, Op_RegF, 5, f5->as_VMReg()->next() );
176 reg_def F6 ( SOC, SOC, Op_RegF, 6, f6->as_VMReg() );
177 reg_def F6_H ( SOC, SOC, Op_RegF, 6, f6->as_VMReg()->next() );
178 reg_def F7 ( SOC, SOC, Op_RegF, 7, f7->as_VMReg() );
179 reg_def F7_H ( SOC, SOC, Op_RegF, 7, f7->as_VMReg()->next() );
180 reg_def F8 ( SOC, SOE, Op_RegF, 8, f8->as_VMReg() );
181 reg_def F8_H ( SOC, SOE, Op_RegF, 8, f8->as_VMReg()->next() );
182 reg_def F9 ( SOC, SOE, Op_RegF, 9, f9->as_VMReg() );
183 reg_def F9_H ( SOC, SOE, Op_RegF, 9, f9->as_VMReg()->next() );
184 reg_def F10 ( SOC, SOC, Op_RegF, 10, f10->as_VMReg() );
185 reg_def F10_H ( SOC, SOC, Op_RegF, 10, f10->as_VMReg()->next() );
186 reg_def F11 ( SOC, SOC, Op_RegF, 11, f11->as_VMReg() );
187 reg_def F11_H ( SOC, SOC, Op_RegF, 11, f11->as_VMReg()->next() );
188 reg_def F12 ( SOC, SOC, Op_RegF, 12, f12->as_VMReg() );
189 reg_def F12_H ( SOC, SOC, Op_RegF, 12, f12->as_VMReg()->next() );
190 reg_def F13 ( SOC, SOC, Op_RegF, 13, f13->as_VMReg() );
191 reg_def F13_H ( SOC, SOC, Op_RegF, 13, f13->as_VMReg()->next() );
192 reg_def F14 ( SOC, SOC, Op_RegF, 14, f14->as_VMReg() );
193 reg_def F14_H ( SOC, SOC, Op_RegF, 14, f14->as_VMReg()->next() );
194 reg_def F15 ( SOC, SOC, Op_RegF, 15, f15->as_VMReg() );
195 reg_def F15_H ( SOC, SOC, Op_RegF, 15, f15->as_VMReg()->next() );
196 reg_def F16 ( SOC, SOC, Op_RegF, 16, f16->as_VMReg() );
197 reg_def F16_H ( SOC, SOC, Op_RegF, 16, f16->as_VMReg()->next() );
198 reg_def F17 ( SOC, SOC, Op_RegF, 17, f17->as_VMReg() );
199 reg_def F17_H ( SOC, SOC, Op_RegF, 17, f17->as_VMReg()->next() );
200 reg_def F18 ( SOC, SOE, Op_RegF, 18, f18->as_VMReg() );
201 reg_def F18_H ( SOC, SOE, Op_RegF, 18, f18->as_VMReg()->next() );
202 reg_def F19 ( SOC, SOE, Op_RegF, 19, f19->as_VMReg() );
203 reg_def F19_H ( SOC, SOE, Op_RegF, 19, f19->as_VMReg()->next() );
204 reg_def F20 ( SOC, SOE, Op_RegF, 20, f20->as_VMReg() );
205 reg_def F20_H ( SOC, SOE, Op_RegF, 20, f20->as_VMReg()->next() );
206 reg_def F21 ( SOC, SOE, Op_RegF, 21, f21->as_VMReg() );
207 reg_def F21_H ( SOC, SOE, Op_RegF, 21, f21->as_VMReg()->next() );
208 reg_def F22 ( SOC, SOE, Op_RegF, 22, f22->as_VMReg() );
209 reg_def F22_H ( SOC, SOE, Op_RegF, 22, f22->as_VMReg()->next() );
210 reg_def F23 ( SOC, SOE, Op_RegF, 23, f23->as_VMReg() );
211 reg_def F23_H ( SOC, SOE, Op_RegF, 23, f23->as_VMReg()->next() );
212 reg_def F24 ( SOC, SOE, Op_RegF, 24, f24->as_VMReg() );
213 reg_def F24_H ( SOC, SOE, Op_RegF, 24, f24->as_VMReg()->next() );
214 reg_def F25 ( SOC, SOE, Op_RegF, 25, f25->as_VMReg() );
215 reg_def F25_H ( SOC, SOE, Op_RegF, 25, f25->as_VMReg()->next() );
216 reg_def F26 ( SOC, SOE, Op_RegF, 26, f26->as_VMReg() );
217 reg_def F26_H ( SOC, SOE, Op_RegF, 26, f26->as_VMReg()->next() );
218 reg_def F27 ( SOC, SOE, Op_RegF, 27, f27->as_VMReg() );
219 reg_def F27_H ( SOC, SOE, Op_RegF, 27, f27->as_VMReg()->next() );
220 reg_def F28 ( SOC, SOC, Op_RegF, 28, f28->as_VMReg() );
221 reg_def F28_H ( SOC, SOC, Op_RegF, 28, f28->as_VMReg()->next() );
222 reg_def F29 ( SOC, SOC, Op_RegF, 29, f29->as_VMReg() );
223 reg_def F29_H ( SOC, SOC, Op_RegF, 29, f29->as_VMReg()->next() );
224 reg_def F30 ( SOC, SOC, Op_RegF, 30, f30->as_VMReg() );
225 reg_def F30_H ( SOC, SOC, Op_RegF, 30, f30->as_VMReg()->next() );
226 reg_def F31 ( SOC, SOC, Op_RegF, 31, f31->as_VMReg() );
227 reg_def F31_H ( SOC, SOC, Op_RegF, 31, f31->as_VMReg()->next() );
228
229 // ----------------------------
230 // Vector Registers
231 // ----------------------------
232
233 // For RVV vector registers, we simply extend vector register size to 4
234 // 'logical' slots. This is nominally 128 bits but it actually covers
235 // all possible 'physical' RVV vector register lengths from 128 ~ 1024
236 // bits. The 'physical' RVV vector register length is detected during
237 // startup, so the register allocator is able to identify the correct
238 // number of bytes needed for an RVV spill/unspill.
239
240 reg_def V0 ( SOC, SOC, Op_VecA, 0, v0->as_VMReg() );
241 reg_def V0_H ( SOC, SOC, Op_VecA, 0, v0->as_VMReg()->next() );
242 reg_def V0_J ( SOC, SOC, Op_VecA, 0, v0->as_VMReg()->next(2) );
243 reg_def V0_K ( SOC, SOC, Op_VecA, 0, v0->as_VMReg()->next(3) );
244
245 reg_def V1 ( SOC, SOC, Op_VecA, 1, v1->as_VMReg() );
246 reg_def V1_H ( SOC, SOC, Op_VecA, 1, v1->as_VMReg()->next() );
247 reg_def V1_J ( SOC, SOC, Op_VecA, 1, v1->as_VMReg()->next(2) );
248 reg_def V1_K ( SOC, SOC, Op_VecA, 1, v1->as_VMReg()->next(3) );
249
250 reg_def V2 ( SOC, SOC, Op_VecA, 2, v2->as_VMReg() );
251 reg_def V2_H ( SOC, SOC, Op_VecA, 2, v2->as_VMReg()->next() );
252 reg_def V2_J ( SOC, SOC, Op_VecA, 2, v2->as_VMReg()->next(2) );
253 reg_def V2_K ( SOC, SOC, Op_VecA, 2, v2->as_VMReg()->next(3) );
254
255 reg_def V3 ( SOC, SOC, Op_VecA, 3, v3->as_VMReg() );
256 reg_def V3_H ( SOC, SOC, Op_VecA, 3, v3->as_VMReg()->next() );
257 reg_def V3_J ( SOC, SOC, Op_VecA, 3, v3->as_VMReg()->next(2) );
258 reg_def V3_K ( SOC, SOC, Op_VecA, 3, v3->as_VMReg()->next(3) );
259
260 reg_def V4 ( SOC, SOC, Op_VecA, 4, v4->as_VMReg() );
261 reg_def V4_H ( SOC, SOC, Op_VecA, 4, v4->as_VMReg()->next() );
262 reg_def V4_J ( SOC, SOC, Op_VecA, 4, v4->as_VMReg()->next(2) );
263 reg_def V4_K ( SOC, SOC, Op_VecA, 4, v4->as_VMReg()->next(3) );
264
265 reg_def V5 ( SOC, SOC, Op_VecA, 5, v5->as_VMReg() );
266 reg_def V5_H ( SOC, SOC, Op_VecA, 5, v5->as_VMReg()->next() );
267 reg_def V5_J ( SOC, SOC, Op_VecA, 5, v5->as_VMReg()->next(2) );
268 reg_def V5_K ( SOC, SOC, Op_VecA, 5, v5->as_VMReg()->next(3) );
269
270 reg_def V6 ( SOC, SOC, Op_VecA, 6, v6->as_VMReg() );
271 reg_def V6_H ( SOC, SOC, Op_VecA, 6, v6->as_VMReg()->next() );
272 reg_def V6_J ( SOC, SOC, Op_VecA, 6, v6->as_VMReg()->next(2) );
273 reg_def V6_K ( SOC, SOC, Op_VecA, 6, v6->as_VMReg()->next(3) );
274
275 reg_def V7 ( SOC, SOC, Op_VecA, 7, v7->as_VMReg() );
276 reg_def V7_H ( SOC, SOC, Op_VecA, 7, v7->as_VMReg()->next() );
277 reg_def V7_J ( SOC, SOC, Op_VecA, 7, v7->as_VMReg()->next(2) );
278 reg_def V7_K ( SOC, SOC, Op_VecA, 7, v7->as_VMReg()->next(3) );
279
280 reg_def V8 ( SOC, SOC, Op_VecA, 8, v8->as_VMReg() );
281 reg_def V8_H ( SOC, SOC, Op_VecA, 8, v8->as_VMReg()->next() );
282 reg_def V8_J ( SOC, SOC, Op_VecA, 8, v8->as_VMReg()->next(2) );
283 reg_def V8_K ( SOC, SOC, Op_VecA, 8, v8->as_VMReg()->next(3) );
284
285 reg_def V9 ( SOC, SOC, Op_VecA, 9, v9->as_VMReg() );
286 reg_def V9_H ( SOC, SOC, Op_VecA, 9, v9->as_VMReg()->next() );
287 reg_def V9_J ( SOC, SOC, Op_VecA, 9, v9->as_VMReg()->next(2) );
288 reg_def V9_K ( SOC, SOC, Op_VecA, 9, v9->as_VMReg()->next(3) );
289
290 reg_def V10 ( SOC, SOC, Op_VecA, 10, v10->as_VMReg() );
291 reg_def V10_H ( SOC, SOC, Op_VecA, 10, v10->as_VMReg()->next() );
292 reg_def V10_J ( SOC, SOC, Op_VecA, 10, v10->as_VMReg()->next(2) );
293 reg_def V10_K ( SOC, SOC, Op_VecA, 10, v10->as_VMReg()->next(3) );
294
295 reg_def V11 ( SOC, SOC, Op_VecA, 11, v11->as_VMReg() );
296 reg_def V11_H ( SOC, SOC, Op_VecA, 11, v11->as_VMReg()->next() );
297 reg_def V11_J ( SOC, SOC, Op_VecA, 11, v11->as_VMReg()->next(2) );
298 reg_def V11_K ( SOC, SOC, Op_VecA, 11, v11->as_VMReg()->next(3) );
299
300 reg_def V12 ( SOC, SOC, Op_VecA, 12, v12->as_VMReg() );
301 reg_def V12_H ( SOC, SOC, Op_VecA, 12, v12->as_VMReg()->next() );
302 reg_def V12_J ( SOC, SOC, Op_VecA, 12, v12->as_VMReg()->next(2) );
303 reg_def V12_K ( SOC, SOC, Op_VecA, 12, v12->as_VMReg()->next(3) );
304
305 reg_def V13 ( SOC, SOC, Op_VecA, 13, v13->as_VMReg() );
306 reg_def V13_H ( SOC, SOC, Op_VecA, 13, v13->as_VMReg()->next() );
307 reg_def V13_J ( SOC, SOC, Op_VecA, 13, v13->as_VMReg()->next(2) );
308 reg_def V13_K ( SOC, SOC, Op_VecA, 13, v13->as_VMReg()->next(3) );
309
310 reg_def V14 ( SOC, SOC, Op_VecA, 14, v14->as_VMReg() );
311 reg_def V14_H ( SOC, SOC, Op_VecA, 14, v14->as_VMReg()->next() );
312 reg_def V14_J ( SOC, SOC, Op_VecA, 14, v14->as_VMReg()->next(2) );
313 reg_def V14_K ( SOC, SOC, Op_VecA, 14, v14->as_VMReg()->next(3) );
314
315 reg_def V15 ( SOC, SOC, Op_VecA, 15, v15->as_VMReg() );
316 reg_def V15_H ( SOC, SOC, Op_VecA, 15, v15->as_VMReg()->next() );
317 reg_def V15_J ( SOC, SOC, Op_VecA, 15, v15->as_VMReg()->next(2) );
318 reg_def V15_K ( SOC, SOC, Op_VecA, 15, v15->as_VMReg()->next(3) );
319
320 reg_def V16 ( SOC, SOC, Op_VecA, 16, v16->as_VMReg() );
321 reg_def V16_H ( SOC, SOC, Op_VecA, 16, v16->as_VMReg()->next() );
322 reg_def V16_J ( SOC, SOC, Op_VecA, 16, v16->as_VMReg()->next(2) );
323 reg_def V16_K ( SOC, SOC, Op_VecA, 16, v16->as_VMReg()->next(3) );
324
325 reg_def V17 ( SOC, SOC, Op_VecA, 17, v17->as_VMReg() );
326 reg_def V17_H ( SOC, SOC, Op_VecA, 17, v17->as_VMReg()->next() );
327 reg_def V17_J ( SOC, SOC, Op_VecA, 17, v17->as_VMReg()->next(2) );
328 reg_def V17_K ( SOC, SOC, Op_VecA, 17, v17->as_VMReg()->next(3) );
329
330 reg_def V18 ( SOC, SOC, Op_VecA, 18, v18->as_VMReg() );
331 reg_def V18_H ( SOC, SOC, Op_VecA, 18, v18->as_VMReg()->next() );
332 reg_def V18_J ( SOC, SOC, Op_VecA, 18, v18->as_VMReg()->next(2) );
333 reg_def V18_K ( SOC, SOC, Op_VecA, 18, v18->as_VMReg()->next(3) );
334
335 reg_def V19 ( SOC, SOC, Op_VecA, 19, v19->as_VMReg() );
336 reg_def V19_H ( SOC, SOC, Op_VecA, 19, v19->as_VMReg()->next() );
337 reg_def V19_J ( SOC, SOC, Op_VecA, 19, v19->as_VMReg()->next(2) );
338 reg_def V19_K ( SOC, SOC, Op_VecA, 19, v19->as_VMReg()->next(3) );
339
340 reg_def V20 ( SOC, SOC, Op_VecA, 20, v20->as_VMReg() );
341 reg_def V20_H ( SOC, SOC, Op_VecA, 20, v20->as_VMReg()->next() );
342 reg_def V20_J ( SOC, SOC, Op_VecA, 20, v20->as_VMReg()->next(2) );
343 reg_def V20_K ( SOC, SOC, Op_VecA, 20, v20->as_VMReg()->next(3) );
344
345 reg_def V21 ( SOC, SOC, Op_VecA, 21, v21->as_VMReg() );
346 reg_def V21_H ( SOC, SOC, Op_VecA, 21, v21->as_VMReg()->next() );
347 reg_def V21_J ( SOC, SOC, Op_VecA, 21, v21->as_VMReg()->next(2) );
348 reg_def V21_K ( SOC, SOC, Op_VecA, 21, v21->as_VMReg()->next(3) );
349
350 reg_def V22 ( SOC, SOC, Op_VecA, 22, v22->as_VMReg() );
351 reg_def V22_H ( SOC, SOC, Op_VecA, 22, v22->as_VMReg()->next() );
352 reg_def V22_J ( SOC, SOC, Op_VecA, 22, v22->as_VMReg()->next(2) );
353 reg_def V22_K ( SOC, SOC, Op_VecA, 22, v22->as_VMReg()->next(3) );
354
355 reg_def V23 ( SOC, SOC, Op_VecA, 23, v23->as_VMReg() );
356 reg_def V23_H ( SOC, SOC, Op_VecA, 23, v23->as_VMReg()->next() );
357 reg_def V23_J ( SOC, SOC, Op_VecA, 23, v23->as_VMReg()->next(2) );
358 reg_def V23_K ( SOC, SOC, Op_VecA, 23, v23->as_VMReg()->next(3) );
359
360 reg_def V24 ( SOC, SOC, Op_VecA, 24, v24->as_VMReg() );
361 reg_def V24_H ( SOC, SOC, Op_VecA, 24, v24->as_VMReg()->next() );
362 reg_def V24_J ( SOC, SOC, Op_VecA, 24, v24->as_VMReg()->next(2) );
363 reg_def V24_K ( SOC, SOC, Op_VecA, 24, v24->as_VMReg()->next(3) );
364
365 reg_def V25 ( SOC, SOC, Op_VecA, 25, v25->as_VMReg() );
366 reg_def V25_H ( SOC, SOC, Op_VecA, 25, v25->as_VMReg()->next() );
367 reg_def V25_J ( SOC, SOC, Op_VecA, 25, v25->as_VMReg()->next(2) );
368 reg_def V25_K ( SOC, SOC, Op_VecA, 25, v25->as_VMReg()->next(3) );
369
370 reg_def V26 ( SOC, SOC, Op_VecA, 26, v26->as_VMReg() );
371 reg_def V26_H ( SOC, SOC, Op_VecA, 26, v26->as_VMReg()->next() );
372 reg_def V26_J ( SOC, SOC, Op_VecA, 26, v26->as_VMReg()->next(2) );
373 reg_def V26_K ( SOC, SOC, Op_VecA, 26, v26->as_VMReg()->next(3) );
374
375 reg_def V27 ( SOC, SOC, Op_VecA, 27, v27->as_VMReg() );
376 reg_def V27_H ( SOC, SOC, Op_VecA, 27, v27->as_VMReg()->next() );
377 reg_def V27_J ( SOC, SOC, Op_VecA, 27, v27->as_VMReg()->next(2) );
378 reg_def V27_K ( SOC, SOC, Op_VecA, 27, v27->as_VMReg()->next(3) );
379
380 reg_def V28 ( SOC, SOC, Op_VecA, 28, v28->as_VMReg() );
381 reg_def V28_H ( SOC, SOC, Op_VecA, 28, v28->as_VMReg()->next() );
382 reg_def V28_J ( SOC, SOC, Op_VecA, 28, v28->as_VMReg()->next(2) );
383 reg_def V28_K ( SOC, SOC, Op_VecA, 28, v28->as_VMReg()->next(3) );
384
385 reg_def V29 ( SOC, SOC, Op_VecA, 29, v29->as_VMReg() );
386 reg_def V29_H ( SOC, SOC, Op_VecA, 29, v29->as_VMReg()->next() );
387 reg_def V29_J ( SOC, SOC, Op_VecA, 29, v29->as_VMReg()->next(2) );
388 reg_def V29_K ( SOC, SOC, Op_VecA, 29, v29->as_VMReg()->next(3) );
389
390 reg_def V30 ( SOC, SOC, Op_VecA, 30, v30->as_VMReg() );
391 reg_def V30_H ( SOC, SOC, Op_VecA, 30, v30->as_VMReg()->next() );
392 reg_def V30_J ( SOC, SOC, Op_VecA, 30, v30->as_VMReg()->next(2) );
393 reg_def V30_K ( SOC, SOC, Op_VecA, 30, v30->as_VMReg()->next(3) );
394
395 reg_def V31 ( SOC, SOC, Op_VecA, 31, v31->as_VMReg() );
396 reg_def V31_H ( SOC, SOC, Op_VecA, 31, v31->as_VMReg()->next() );
397 reg_def V31_J ( SOC, SOC, Op_VecA, 31, v31->as_VMReg()->next(2) );
398 reg_def V31_K ( SOC, SOC, Op_VecA, 31, v31->as_VMReg()->next(3) );
399
400 // ----------------------------
401 // Special Registers
402 // ----------------------------
403
404 // On riscv, the physical flag register is missing, so we use t1 instead,
405 // to bridge the RegFlag semantics in share/opto
406
407 reg_def RFLAGS (SOC, SOC, Op_RegFlags, 6, x6->as_VMReg() );
408
409 // Specify priority of register selection within phases of register
410 // allocation. Highest priority is first. A useful heuristic is to
411 // give registers a low priority when they are required by machine
412 // instructions, like EAX and EDX on I486, and choose no-save registers
413 // before save-on-call, & save-on-call before save-on-entry. Registers
414 // which participate in fixed calling sequences should come last.
415 // Registers which are used as pairs must fall on an even boundary.
416
417 alloc_class chunk0(
418 // volatiles
419 R7, R7_H,
420 R28, R28_H,
421 R29, R29_H,
422 R30, R30_H,
423 R31, R31_H,
424
425 // arg registers
426 R10, R10_H,
427 R11, R11_H,
428 R12, R12_H,
429 R13, R13_H,
430 R14, R14_H,
431 R15, R15_H,
432 R16, R16_H,
433 R17, R17_H,
434
435 // non-volatiles
436 R9, R9_H,
437 R18, R18_H,
438 R19, R19_H,
439 R20, R20_H,
440 R21, R21_H,
441 R22, R22_H,
442 R24, R24_H,
443 R25, R25_H,
444 R26, R26_H,
445
446 // non-allocatable registers
447 R23, R23_H, // java thread
448 R27, R27_H, // heapbase
449 R4, R4_H, // thread
450 R8, R8_H, // fp
451 R0, R0_H, // zero
452 R1, R1_H, // ra
453 R2, R2_H, // sp
454 R3, R3_H, // gp
455 );
456
457 alloc_class chunk1(
458
459 // no save
460 F0, F0_H,
461 F1, F1_H,
462 F2, F2_H,
463 F3, F3_H,
464 F4, F4_H,
465 F5, F5_H,
466 F6, F6_H,
467 F7, F7_H,
468 F28, F28_H,
469 F29, F29_H,
470 F30, F30_H,
471 F31, F31_H,
472
473 // arg registers
474 F10, F10_H,
475 F11, F11_H,
476 F12, F12_H,
477 F13, F13_H,
478 F14, F14_H,
479 F15, F15_H,
480 F16, F16_H,
481 F17, F17_H,
482
483 // non-volatiles
484 F8, F8_H,
485 F9, F9_H,
486 F18, F18_H,
487 F19, F19_H,
488 F20, F20_H,
489 F21, F21_H,
490 F22, F22_H,
491 F23, F23_H,
492 F24, F24_H,
493 F25, F25_H,
494 F26, F26_H,
495 F27, F27_H,
496 );
497
498 alloc_class chunk2(
499 V0, V0_H, V0_J, V0_K,
500 V1, V1_H, V1_J, V1_K,
501 V2, V2_H, V2_J, V2_K,
502 V3, V3_H, V3_J, V3_K,
503 V4, V4_H, V4_J, V4_K,
504 V5, V5_H, V5_J, V5_K,
505 V6, V6_H, V6_J, V6_K,
506 V7, V7_H, V7_J, V7_K,
507 V8, V8_H, V8_J, V8_K,
508 V9, V9_H, V9_J, V9_K,
509 V10, V10_H, V10_J, V10_K,
510 V11, V11_H, V11_J, V11_K,
511 V12, V12_H, V12_J, V12_K,
512 V13, V13_H, V13_J, V13_K,
513 V14, V14_H, V14_J, V14_K,
514 V15, V15_H, V15_J, V15_K,
515 V16, V16_H, V16_J, V16_K,
516 V17, V17_H, V17_J, V17_K,
517 V18, V18_H, V18_J, V18_K,
518 V19, V19_H, V19_J, V19_K,
519 V20, V20_H, V20_J, V20_K,
520 V21, V21_H, V21_J, V21_K,
521 V22, V22_H, V22_J, V22_K,
522 V23, V23_H, V23_J, V23_K,
523 V24, V24_H, V24_J, V24_K,
524 V25, V25_H, V25_J, V25_K,
525 V26, V26_H, V26_J, V26_K,
526 V27, V27_H, V27_J, V27_K,
527 V28, V28_H, V28_J, V28_K,
528 V29, V29_H, V29_J, V29_K,
529 V30, V30_H, V30_J, V30_K,
530 V31, V31_H, V31_J, V31_K,
531 );
532
533 alloc_class chunk3(RFLAGS);
534
535 //----------Architecture Description Register Classes--------------------------
536 // Several register classes are automatically defined based upon information in
537 // this architecture description.
538 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
539 // 2) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
540 //
541
542 // Class for all 32 bit general purpose registers
543 reg_class all_reg32(
544 R0,
545 R1,
546 R2,
547 R3,
548 R4,
549 R7,
550 R8,
551 R9,
552 R10,
553 R11,
554 R12,
555 R13,
556 R14,
557 R15,
558 R16,
559 R17,
560 R18,
561 R19,
562 R20,
563 R21,
564 R22,
565 R23,
566 R24,
567 R25,
568 R26,
569 R27,
570 R28,
571 R29,
572 R30,
573 R31
574 );
575
576 // Class for any 32 bit integer registers (excluding zr)
577 reg_class any_reg32 %{
578 return _ANY_REG32_mask;
579 %}
580
581 // Singleton class for R10 int register
582 reg_class int_r10_reg(R10);
583
584 // Singleton class for R12 int register
585 reg_class int_r12_reg(R12);
586
587 // Singleton class for R13 int register
588 reg_class int_r13_reg(R13);
589
590 // Singleton class for R14 int register
591 reg_class int_r14_reg(R14);
592
593 // Class for all long integer registers
594 reg_class all_reg(
595 R0, R0_H,
596 R1, R1_H,
597 R2, R2_H,
598 R3, R3_H,
599 R4, R4_H,
600 R7, R7_H,
601 R8, R8_H,
602 R9, R9_H,
603 R10, R10_H,
604 R11, R11_H,
605 R12, R12_H,
606 R13, R13_H,
607 R14, R14_H,
608 R15, R15_H,
609 R16, R16_H,
610 R17, R17_H,
611 R18, R18_H,
612 R19, R19_H,
613 R20, R20_H,
614 R21, R21_H,
615 R22, R22_H,
616 R23, R23_H,
617 R24, R24_H,
618 R25, R25_H,
619 R26, R26_H,
620 R27, R27_H,
621 R28, R28_H,
622 R29, R29_H,
623 R30, R30_H,
624 R31, R31_H
625 );
626
627 // Class for all long integer registers (excluding zr)
628 reg_class any_reg %{
629 return _ANY_REG_mask;
630 %}
631
632 // Class for non-allocatable 32 bit registers
633 reg_class non_allocatable_reg32(
634 R0, // zr
635 R1, // ra
636 R2, // sp
637 R3, // gp
638 R4, // tp
639 R23 // java thread
640 );
641
642 // Class for non-allocatable 64 bit registers
643 reg_class non_allocatable_reg(
644 R0, R0_H, // zr
645 R1, R1_H, // ra
646 R2, R2_H, // sp
647 R3, R3_H, // gp
648 R4, R4_H, // tp
649 R23, R23_H // java thread
650 );
651
652 reg_class no_special_reg32 %{
653 return _NO_SPECIAL_REG32_mask;
654 %}
655
656 reg_class no_special_reg %{
657 return _NO_SPECIAL_REG_mask;
658 %}
659
660 reg_class ptr_reg %{
661 return _PTR_REG_mask;
662 %}
663
664 reg_class no_special_ptr_reg %{
665 return _NO_SPECIAL_PTR_REG_mask;
666 %}
667
668 // Class for 64 bit register r10
669 reg_class r10_reg(
670 R10, R10_H
671 );
672
673 // Class for 64 bit register r11
674 reg_class r11_reg(
675 R11, R11_H
676 );
677
678 // Class for 64 bit register r12
679 reg_class r12_reg(
680 R12, R12_H
681 );
682
683 // Class for 64 bit register r13
684 reg_class r13_reg(
685 R13, R13_H
686 );
687
688 // Class for 64 bit register r14
689 reg_class r14_reg(
690 R14, R14_H
691 );
692
693 // Class for 64 bit register r15
694 reg_class r15_reg(
695 R15, R15_H
696 );
697
698 // Class for 64 bit register r16
699 reg_class r16_reg(
700 R16, R16_H
701 );
702
703 // Class for method register
704 reg_class method_reg(
705 R31, R31_H
706 );
707
708 // Class for heapbase register
709 reg_class heapbase_reg(
710 R27, R27_H
711 );
712
713 // Class for java thread register
714 reg_class java_thread_reg(
715 R23, R23_H
716 );
717
718 reg_class r28_reg(
719 R28, R28_H
720 );
721
722 reg_class r29_reg(
723 R29, R29_H
724 );
725
726 reg_class r30_reg(
727 R30, R30_H
728 );
729
730 reg_class r31_reg(
731 R31, R31_H
732 );
733
734 // Class for zero registesr
735 reg_class zr_reg(
736 R0, R0_H
737 );
738
739 // Class for thread register
740 reg_class thread_reg(
741 R4, R4_H
742 );
743
744 // Class for frame pointer register
745 reg_class fp_reg(
746 R8, R8_H
747 );
748
749 // Class for link register
750 reg_class ra_reg(
751 R1, R1_H
752 );
753
754 // Class for long sp register
755 reg_class sp_reg(
756 R2, R2_H
757 );
758
759 // Class for all float registers
760 reg_class float_reg(
761 F0,
762 F1,
763 F2,
764 F3,
765 F4,
766 F5,
767 F6,
768 F7,
769 F8,
770 F9,
771 F10,
772 F11,
773 F12,
774 F13,
775 F14,
776 F15,
777 F16,
778 F17,
779 F18,
780 F19,
781 F20,
782 F21,
783 F22,
784 F23,
785 F24,
786 F25,
787 F26,
788 F27,
789 F28,
790 F29,
791 F30,
792 F31
793 );
794
795 // Double precision float registers have virtual `high halves' that
796 // are needed by the allocator.
797 // Class for all double registers
798 reg_class double_reg(
799 F0, F0_H,
800 F1, F1_H,
801 F2, F2_H,
802 F3, F3_H,
803 F4, F4_H,
804 F5, F5_H,
805 F6, F6_H,
806 F7, F7_H,
807 F8, F8_H,
808 F9, F9_H,
809 F10, F10_H,
810 F11, F11_H,
811 F12, F12_H,
812 F13, F13_H,
813 F14, F14_H,
814 F15, F15_H,
815 F16, F16_H,
816 F17, F17_H,
817 F18, F18_H,
818 F19, F19_H,
819 F20, F20_H,
820 F21, F21_H,
821 F22, F22_H,
822 F23, F23_H,
823 F24, F24_H,
824 F25, F25_H,
825 F26, F26_H,
826 F27, F27_H,
827 F28, F28_H,
828 F29, F29_H,
829 F30, F30_H,
830 F31, F31_H
831 );
832
833 // Class for all RVV vector registers
834 reg_class vectora_reg(
835 V1, V1_H, V1_J, V1_K,
836 V2, V2_H, V2_J, V2_K,
837 V3, V3_H, V3_J, V3_K,
838 V4, V4_H, V4_J, V4_K,
839 V5, V5_H, V5_J, V5_K,
840 V6, V6_H, V6_J, V6_K,
841 V7, V7_H, V7_J, V7_K,
842 V8, V8_H, V8_J, V8_K,
843 V9, V9_H, V9_J, V9_K,
844 V10, V10_H, V10_J, V10_K,
845 V11, V11_H, V11_J, V11_K,
846 V12, V12_H, V12_J, V12_K,
847 V13, V13_H, V13_J, V13_K,
848 V14, V14_H, V14_J, V14_K,
849 V15, V15_H, V15_J, V15_K,
850 V16, V16_H, V16_J, V16_K,
851 V17, V17_H, V17_J, V17_K,
852 V18, V18_H, V18_J, V18_K,
853 V19, V19_H, V19_J, V19_K,
854 V20, V20_H, V20_J, V20_K,
855 V21, V21_H, V21_J, V21_K,
856 V22, V22_H, V22_J, V22_K,
857 V23, V23_H, V23_J, V23_K,
858 V24, V24_H, V24_J, V24_K,
859 V25, V25_H, V25_J, V25_K,
860 V26, V26_H, V26_J, V26_K,
861 V27, V27_H, V27_J, V27_K,
862 V28, V28_H, V28_J, V28_K,
863 V29, V29_H, V29_J, V29_K,
864 V30, V30_H, V30_J, V30_K,
865 V31, V31_H, V31_J, V31_K
866 );
867
868 // Class for 64 bit register f0
869 reg_class f0_reg(
870 F0, F0_H
871 );
872
873 // Class for 64 bit register f1
874 reg_class f1_reg(
875 F1, F1_H
876 );
877
878 // Class for 64 bit register f2
879 reg_class f2_reg(
880 F2, F2_H
881 );
882
883 // Class for 64 bit register f3
884 reg_class f3_reg(
885 F3, F3_H
886 );
887
888 // class for vector register v1
889 reg_class v1_reg(
890 V1, V1_H, V1_J, V1_K
891 );
892
893 // class for vector register v2
894 reg_class v2_reg(
895 V2, V2_H, V2_J, V2_K
896 );
897
898 // class for vector register v3
899 reg_class v3_reg(
900 V3, V3_H, V3_J, V3_K
901 );
902
903 // class for vector register v4
904 reg_class v4_reg(
905 V4, V4_H, V4_J, V4_K
906 );
907
908 // class for vector register v5
909 reg_class v5_reg(
910 V5, V5_H, V5_J, V5_K
911 );
912
913 // class for condition codes
914 reg_class reg_flags(RFLAGS);
915 %}
916
917 //----------DEFINITION BLOCK---------------------------------------------------
918 // Define name --> value mappings to inform the ADLC of an integer valued name
919 // Current support includes integer values in the range [0, 0x7FFFFFFF]
920 // Format:
921 // int_def <name> ( <int_value>, <expression>);
922 // Generated Code in ad_<arch>.hpp
923 // #define <name> (<expression>)
924 // // value == <int_value>
925 // Generated code in ad_<arch>.cpp adlc_verification()
926 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
927 //
928
929 // we follow the ppc-aix port in using a simple cost model which ranks
930 // register operations as cheap, memory ops as more expensive and
931 // branches as most expensive. the first two have a low as well as a
932 // normal cost. huge cost appears to be a way of saying don't do
933 // something
934
935 definitions %{
936 // The default cost (of a register move instruction).
937 int_def DEFAULT_COST ( 100, 100);
938 int_def ALU_COST ( 100, 1 * DEFAULT_COST); // unknown, const, arith, shift, slt,
939 // multi, auipc, nop, logical, move
940 int_def LOAD_COST ( 300, 3 * DEFAULT_COST); // load, fpload
941 int_def STORE_COST ( 100, 1 * DEFAULT_COST); // store, fpstore
942 int_def XFER_COST ( 300, 3 * DEFAULT_COST); // mfc, mtc, fcvt, fmove, fcmp
943 int_def BRANCH_COST ( 200, 2 * DEFAULT_COST); // branch, jmp, call
944 int_def IMUL_COST ( 1000, 10 * DEFAULT_COST); // imul
945 int_def IDIVSI_COST ( 3400, 34 * DEFAULT_COST); // idivdi
946 int_def IDIVDI_COST ( 6600, 66 * DEFAULT_COST); // idivsi
947 int_def FMUL_SINGLE_COST ( 500, 5 * DEFAULT_COST); // fmul, fmadd
948 int_def FMUL_DOUBLE_COST ( 700, 7 * DEFAULT_COST); // fmul, fmadd
949 int_def FDIV_COST ( 2000, 20 * DEFAULT_COST); // fdiv
950 int_def FSQRT_COST ( 2500, 25 * DEFAULT_COST); // fsqrt
951 int_def VOLATILE_REF_COST ( 1000, 10 * DEFAULT_COST);
952 int_def CACHE_MISS_COST ( 2000, 20 * DEFAULT_COST); // typicall cache miss penalty
953 %}
954
955
956
957 //----------SOURCE BLOCK-------------------------------------------------------
958 // This is a block of C++ code which provides values, functions, and
959 // definitions necessary in the rest of the architecture description
960
961 source_hpp %{
962
963 #include "asm/macroAssembler.hpp"
964 #include "gc/shared/barrierSetAssembler.hpp"
965 #include "gc/shared/cardTable.hpp"
966 #include "gc/shared/cardTableBarrierSet.hpp"
967 #include "gc/shared/collectedHeap.hpp"
968 #include "opto/addnode.hpp"
969 #include "opto/convertnode.hpp"
970 #include "runtime/objectMonitor.hpp"
971
972 extern RegMask _ANY_REG32_mask;
973 extern RegMask _ANY_REG_mask;
974 extern RegMask _PTR_REG_mask;
975 extern RegMask _NO_SPECIAL_REG32_mask;
976 extern RegMask _NO_SPECIAL_REG_mask;
977 extern RegMask _NO_SPECIAL_PTR_REG_mask;
978
979 class CallStubImpl {
980
981 //--------------------------------------------------------------
982 //---< Used for optimization in Compile::shorten_branches >---
983 //--------------------------------------------------------------
984
985 public:
986 // Size of call trampoline stub.
987 static uint size_call_trampoline() {
988 return 0; // no call trampolines on this platform
989 }
990
991 // number of relocations needed by a call trampoline stub
992 static uint reloc_call_trampoline() {
993 return 0; // no call trampolines on this platform
994 }
995 };
996
997 class HandlerImpl {
998
999 public:
1000
1001 static int emit_exception_handler(CodeBuffer &cbuf);
1002 static int emit_deopt_handler(CodeBuffer& cbuf);
1003
1004 static uint size_exception_handler() {
1005 return MacroAssembler::far_branch_size();
1006 }
1007
1008 static uint size_deopt_handler() {
1009 // count auipc + far branch
1010 return NativeInstruction::instruction_size + MacroAssembler::far_branch_size();
1011 }
1012 };
1013
1014 class Node::PD {
1015 public:
1016 enum NodeFlags {
1017 _last_flag = Node::_last_flag
1018 };
1019 };
1020
1021 bool is_CAS(int opcode, bool maybe_volatile);
1022
1023 // predicate controlling translation of CompareAndSwapX
1024 bool needs_acquiring_load_reserved(const Node *load);
1025
1026 // predicate controlling addressing modes
1027 bool size_fits_all_mem_uses(AddPNode* addp, int shift);
1028 %}
1029
1030 source %{
1031
1032 // Derived RegMask with conditionally allocatable registers
1033
1034 RegMask _ANY_REG32_mask;
1035 RegMask _ANY_REG_mask;
1036 RegMask _PTR_REG_mask;
1037 RegMask _NO_SPECIAL_REG32_mask;
1038 RegMask _NO_SPECIAL_REG_mask;
1039 RegMask _NO_SPECIAL_PTR_REG_mask;
1040
1041 void reg_mask_init() {
1042
1043 _ANY_REG32_mask = _ALL_REG32_mask;
1044 _ANY_REG32_mask.Remove(OptoReg::as_OptoReg(x0->as_VMReg()));
1045
1046 _ANY_REG_mask = _ALL_REG_mask;
1047 _ANY_REG_mask.SUBTRACT(_ZR_REG_mask);
1048
1049 _PTR_REG_mask = _ALL_REG_mask;
1050 _PTR_REG_mask.SUBTRACT(_ZR_REG_mask);
1051
1052 _NO_SPECIAL_REG32_mask = _ALL_REG32_mask;
1053 _NO_SPECIAL_REG32_mask.SUBTRACT(_NON_ALLOCATABLE_REG32_mask);
1054
1055 _NO_SPECIAL_REG_mask = _ALL_REG_mask;
1056 _NO_SPECIAL_REG_mask.SUBTRACT(_NON_ALLOCATABLE_REG_mask);
1057
1058 _NO_SPECIAL_PTR_REG_mask = _ALL_REG_mask;
1059 _NO_SPECIAL_PTR_REG_mask.SUBTRACT(_NON_ALLOCATABLE_REG_mask);
1060
1061 // x27 is not allocatable when compressed oops is on
1062 if (UseCompressedOops) {
1063 _NO_SPECIAL_REG32_mask.Remove(OptoReg::as_OptoReg(x27->as_VMReg()));
1064 _NO_SPECIAL_REG_mask.SUBTRACT(_HEAPBASE_REG_mask);
1065 _NO_SPECIAL_PTR_REG_mask.SUBTRACT(_HEAPBASE_REG_mask);
1066 }
1067
1068 // x8 is not allocatable when PreserveFramePointer is on
1069 if (PreserveFramePointer) {
1070 _NO_SPECIAL_REG32_mask.Remove(OptoReg::as_OptoReg(x8->as_VMReg()));
1071 _NO_SPECIAL_REG_mask.SUBTRACT(_FP_REG_mask);
1072 _NO_SPECIAL_PTR_REG_mask.SUBTRACT(_FP_REG_mask);
1073 }
1074 }
1075
1076 void PhaseOutput::pd_perform_mach_node_analysis() {
1077 }
1078
1079 int MachNode::pd_alignment_required() const {
1080 return 1;
1081 }
1082
1083 int MachNode::compute_padding(int current_offset) const {
1084 return 0;
1085 }
1086
1087 // is_CAS(int opcode, bool maybe_volatile)
1088 //
1089 // return true if opcode is one of the possible CompareAndSwapX
1090 // values otherwise false.
1091 bool is_CAS(int opcode, bool maybe_volatile)
1092 {
1093 switch (opcode) {
1094 // We handle these
1095 case Op_CompareAndSwapI:
1096 case Op_CompareAndSwapL:
1097 case Op_CompareAndSwapP:
1098 case Op_CompareAndSwapN:
1099 case Op_ShenandoahCompareAndSwapP:
1100 case Op_ShenandoahCompareAndSwapN:
1101 case Op_CompareAndSwapB:
1102 case Op_CompareAndSwapS:
1103 case Op_GetAndSetI:
1104 case Op_GetAndSetL:
1105 case Op_GetAndSetP:
1106 case Op_GetAndSetN:
1107 case Op_GetAndAddI:
1108 case Op_GetAndAddL:
1109 return true;
1110 case Op_CompareAndExchangeI:
1111 case Op_CompareAndExchangeN:
1112 case Op_CompareAndExchangeB:
1113 case Op_CompareAndExchangeS:
1114 case Op_CompareAndExchangeL:
1115 case Op_CompareAndExchangeP:
1116 case Op_WeakCompareAndSwapB:
1117 case Op_WeakCompareAndSwapS:
1118 case Op_WeakCompareAndSwapI:
1119 case Op_WeakCompareAndSwapL:
1120 case Op_WeakCompareAndSwapP:
1121 case Op_WeakCompareAndSwapN:
1122 case Op_ShenandoahWeakCompareAndSwapP:
1123 case Op_ShenandoahWeakCompareAndSwapN:
1124 case Op_ShenandoahCompareAndExchangeP:
1125 case Op_ShenandoahCompareAndExchangeN:
1126 return maybe_volatile;
1127 default:
1128 return false;
1129 }
1130 }
1131
1132 // predicate controlling translation of CAS
1133 //
1134 // returns true if CAS needs to use an acquiring load otherwise false
1135 bool needs_acquiring_load_reserved(const Node *n)
1136 {
1137 assert(n != NULL && is_CAS(n->Opcode(), true), "expecting a compare and swap");
1138
1139 LoadStoreNode* ldst = n->as_LoadStore();
1140 if (n != NULL && is_CAS(n->Opcode(), false)) {
1141 assert(ldst != NULL && ldst->trailing_membar() != NULL, "expected trailing membar");
1142 } else {
1143 return ldst != NULL && ldst->trailing_membar() != NULL;
1144 }
1145 // so we can just return true here
1146 return true;
1147 }
1148 #define __ _masm.
1149
1150 // advance declarations for helper functions to convert register
1151 // indices to register objects
1152
1153 // the ad file has to provide implementations of certain methods
1154 // expected by the generic code
1155 //
1156 // REQUIRED FUNCTIONALITY
1157
1158 //=============================================================================
1159
1160 // !!!!! Special hack to get all types of calls to specify the byte offset
1161 // from the start of the call to the point where the return address
1162 // will point.
1163
1164 int MachCallStaticJavaNode::ret_addr_offset()
1165 {
1166 // jal
1167 return 1 * NativeInstruction::instruction_size;
1168 }
1169
1170 int MachCallDynamicJavaNode::ret_addr_offset()
1171 {
1172 return 7 * NativeInstruction::instruction_size; // movptr, jal
1173 }
1174
1175 int MachCallRuntimeNode::ret_addr_offset() {
1176 // for generated stubs the call will be
1177 // jal(addr)
1178 // or with far branches
1179 // jal(trampoline_stub)
1180 // for real runtime callouts it will be 11 instructions
1181 // see riscv_enc_java_to_runtime
1182 // la(t1, retaddr) -> auipc + addi
1183 // la(t0, RuntimeAddress(addr)) -> lui + addi + slli + addi + slli + addi
1184 // addi(sp, sp, -2 * wordSize) -> addi
1185 // sd(t1, Address(sp, wordSize)) -> sd
1186 // jalr(t0) -> jalr
1187 CodeBlob *cb = CodeCache::find_blob(_entry_point);
1188 if (cb != NULL) {
1189 return 1 * NativeInstruction::instruction_size;
1190 } else {
1191 return 11 * NativeInstruction::instruction_size;
1192 }
1193 }
1194
1195 //
1196 // Compute padding required for nodes which need alignment
1197 //
1198
1199 // With RVC a call instruction may get 2-byte aligned.
1200 // The address of the call instruction needs to be 4-byte aligned to
1201 // ensure that it does not span a cache line so that it can be patched.
1202 int CallStaticJavaDirectNode::compute_padding(int current_offset) const
1203 {
1204 // to make sure the address of jal 4-byte aligned.
1205 return align_up(current_offset, alignment_required()) - current_offset;
1206 }
1207
1208 // With RVC a call instruction may get 2-byte aligned.
1209 // The address of the call instruction needs to be 4-byte aligned to
1210 // ensure that it does not span a cache line so that it can be patched.
1211 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const
1212 {
1213 // skip the movptr in MacroAssembler::ic_call():
1214 // lui + addi + slli + addi + slli + addi
1215 // Though movptr() has already 4-byte aligned with or without RVC,
1216 // We need to prevent from further changes by explicitly calculating the size.
1217 const int movptr_size = 6 * NativeInstruction::instruction_size;
1218 current_offset += movptr_size;
1219 // to make sure the address of jal 4-byte aligned.
1220 return align_up(current_offset, alignment_required()) - current_offset;
1221 }
1222
1223 //=============================================================================
1224
1225 #ifndef PRODUCT
1226 void MachBreakpointNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1227 assert_cond(st != NULL);
1228 st->print("BREAKPOINT");
1229 }
1230 #endif
1231
1232 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1233 C2_MacroAssembler _masm(&cbuf);
1234 __ ebreak();
1235 }
1236
1237 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
1238 return MachNode::size(ra_);
1239 }
1240
1241 //=============================================================================
1242
1243 #ifndef PRODUCT
1244 void MachNopNode::format(PhaseRegAlloc*, outputStream* st) const {
1245 st->print("nop \t# %d bytes pad for loops and calls", _count);
1246 }
1247 #endif
1248
1249 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc*) const {
1250 C2_MacroAssembler _masm(&cbuf);
1251 Assembler::CompressibleRegion cr(&_masm); // nops shall be 2-byte under RVC for alignment purposes.
1252 for (int i = 0; i < _count; i++) {
1253 __ nop();
1254 }
1255 }
1256
1257 uint MachNopNode::size(PhaseRegAlloc*) const {
1258 return _count * (UseRVC ? NativeInstruction::compressed_instruction_size : NativeInstruction::instruction_size);
1259 }
1260
1261 //=============================================================================
1262 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;
1263
1264 int ConstantTable::calculate_table_base_offset() const {
1265 return 0; // absolute addressing, no offset
1266 }
1267
1268 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
1269 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
1270 ShouldNotReachHere();
1271 }
1272
1273 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
1274 // Empty encoding
1275 }
1276
1277 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
1278 return 0;
1279 }
1280
1281 #ifndef PRODUCT
1282 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1283 assert_cond(st != NULL);
1284 st->print("-- \t// MachConstantBaseNode (empty encoding)");
1285 }
1286 #endif
1287
1288 #ifndef PRODUCT
1289 void MachPrologNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1290 assert_cond(st != NULL && ra_ != NULL);
1291 Compile* C = ra_->C;
1292
1293 int framesize = C->output()->frame_slots() << LogBytesPerInt;
1294
1295 if (C->output()->need_stack_bang(framesize)) {
1296 st->print("# stack bang size=%d\n\t", framesize);
1297 }
1298
1299 st->print("sd fp, [sp, #%d]\n\t", - 2 * wordSize);
1300 st->print("sd ra, [sp, #%d]\n\t", - wordSize);
1301 if (PreserveFramePointer) { st->print("sub fp, sp, #%d\n\t", 2 * wordSize); }
1302 st->print("sub sp, sp, #%d\n\t", framesize);
1303
1304 if (C->stub_function() == NULL && BarrierSet::barrier_set()->barrier_set_nmethod() != NULL) {
1305 st->print("ld t0, [guard]\n\t");
1306 st->print("membar LoadLoad\n\t");
1307 st->print("ld t1, [xthread, #thread_disarmed_guard_value_offset]\n\t");
1308 st->print("beq t0, t1, skip\n\t");
1309 st->print("jalr #nmethod_entry_barrier_stub\n\t");
1310 st->print("j skip\n\t");
1311 st->print("guard: int\n\t");
1312 st->print("skip:\n\t");
1313 }
1314 }
1315 #endif
1316
1317 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1318 assert_cond(ra_ != NULL);
1319 Compile* C = ra_->C;
1320 C2_MacroAssembler _masm(&cbuf);
1321
1322 // n.b. frame size includes space for return pc and fp
1323 const int framesize = C->output()->frame_size_in_bytes();
1324
1325 // insert a nop at the start of the prolog so we can patch in a
1326 // branch if we need to invalidate the method later
1327 {
1328 Assembler::IncompressibleRegion ir(&_masm); // keep the nop as 4 bytes for patching.
1329 MacroAssembler::assert_alignment(__ pc());
1330 __ nop(); // 4 bytes
1331 }
1332
1333 assert_cond(C != NULL);
1334
1335 if (C->clinit_barrier_on_entry()) {
1336 assert(!C->method()->holder()->is_not_initialized(), "initialization should have been started");
1337
1338 Label L_skip_barrier;
1339
1340 __ mov_metadata(t1, C->method()->holder()->constant_encoding());
1341 __ clinit_barrier(t1, t0, &L_skip_barrier);
1342 __ far_jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub()));
1343 __ bind(L_skip_barrier);
1344 }
1345
1346 int bangsize = C->output()->bang_size_in_bytes();
1347 if (C->output()->need_stack_bang(bangsize)) {
1348 __ generate_stack_overflow_check(bangsize);
1349 }
1350
1351 __ build_frame(framesize);
1352
1353 if (C->stub_function() == NULL) {
1354 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
1355 if (BarrierSet::barrier_set()->barrier_set_nmethod() != NULL) {
1356 // Dummy labels for just measuring the code size
1357 Label dummy_slow_path;
1358 Label dummy_continuation;
1359 Label dummy_guard;
1360 Label* slow_path = &dummy_slow_path;
1361 Label* continuation = &dummy_continuation;
1362 Label* guard = &dummy_guard;
1363 if (!Compile::current()->output()->in_scratch_emit_size()) {
1364 // Use real labels from actual stub when not emitting code for purpose of measuring its size
1365 C2EntryBarrierStub* stub = new (Compile::current()->comp_arena()) C2EntryBarrierStub();
1366 Compile::current()->output()->add_stub(stub);
1367 slow_path = &stub->entry();
1368 continuation = &stub->continuation();
1369 guard = &stub->guard();
1370 }
1371 // In the C2 code, we move the non-hot part of nmethod entry barriers out-of-line to a stub.
1372 bs->nmethod_entry_barrier(&_masm, slow_path, continuation, guard);
1373 }
1374 }
1375
1376 if (VerifyStackAtCalls) {
1377 Unimplemented();
1378 }
1379
1380 C->output()->set_frame_complete(cbuf.insts_size());
1381
1382 if (C->has_mach_constant_base_node()) {
1383 // NOTE: We set the table base offset here because users might be
1384 // emitted before MachConstantBaseNode.
1385 ConstantTable& constant_table = C->output()->constant_table();
1386 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
1387 }
1388 }
1389
1390 uint MachPrologNode::size(PhaseRegAlloc* ra_) const
1391 {
1392 assert_cond(ra_ != NULL);
1393 return MachNode::size(ra_); // too many variables; just compute it
1394 // the hard way
1395 }
1396
1397 int MachPrologNode::reloc() const
1398 {
1399 return 0;
1400 }
1401
1402 //=============================================================================
1403
1404 #ifndef PRODUCT
1405 void MachEpilogNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1406 assert_cond(st != NULL && ra_ != NULL);
1407 Compile* C = ra_->C;
1408 assert_cond(C != NULL);
1409 int framesize = C->output()->frame_size_in_bytes();
1410
1411 st->print("# pop frame %d\n\t", framesize);
1412
1413 if (framesize == 0) {
1414 st->print("ld ra, [sp,#%d]\n\t", (2 * wordSize));
1415 st->print("ld fp, [sp,#%d]\n\t", (3 * wordSize));
1416 st->print("add sp, sp, #%d\n\t", (2 * wordSize));
1417 } else {
1418 st->print("add sp, sp, #%d\n\t", framesize);
1419 st->print("ld ra, [sp,#%d]\n\t", - 2 * wordSize);
1420 st->print("ld fp, [sp,#%d]\n\t", - wordSize);
1421 }
1422
1423 if (do_polling() && C->is_method_compilation()) {
1424 st->print("# test polling word\n\t");
1425 st->print("ld t0, [xthread,#%d]\n\t", in_bytes(JavaThread::polling_word_offset()));
1426 st->print("bgtu sp, t0, #slow_path");
1427 }
1428 }
1429 #endif
1430
1431 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1432 assert_cond(ra_ != NULL);
1433 Compile* C = ra_->C;
1434 C2_MacroAssembler _masm(&cbuf);
1435 assert_cond(C != NULL);
1436 int framesize = C->output()->frame_size_in_bytes();
1437
1438 __ remove_frame(framesize);
1439
1440 if (StackReservedPages > 0 && C->has_reserved_stack_access()) {
1441 __ reserved_stack_check();
1442 }
1443
1444 if (do_polling() && C->is_method_compilation()) {
1445 Label dummy_label;
1446 Label* code_stub = &dummy_label;
1447 if (!C->output()->in_scratch_emit_size()) {
1448 C2SafepointPollStub* stub = new (C->comp_arena()) C2SafepointPollStub(__ offset());
1449 C->output()->add_stub(stub);
1450 code_stub = &stub->entry();
1451 }
1452 __ relocate(relocInfo::poll_return_type);
1453 __ safepoint_poll(*code_stub, true /* at_return */, false /* acquire */, true /* in_nmethod */);
1454 }
1455 }
1456
1457 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
1458 assert_cond(ra_ != NULL);
1459 // Variable size. Determine dynamically.
1460 return MachNode::size(ra_);
1461 }
1462
1463 int MachEpilogNode::reloc() const {
1464 // Return number of relocatable values contained in this instruction.
1465 return 1; // 1 for polling page.
1466 }
1467 const Pipeline * MachEpilogNode::pipeline() const {
1468 return MachNode::pipeline_class();
1469 }
1470
1471 //=============================================================================
1472
1473 // Figure out which register class each belongs in: rc_int, rc_float or
1474 // rc_stack.
1475 enum RC { rc_bad, rc_int, rc_float, rc_vector, rc_stack };
1476
1477 static enum RC rc_class(OptoReg::Name reg) {
1478
1479 if (reg == OptoReg::Bad) {
1480 return rc_bad;
1481 }
1482
1483 // we have 30 int registers * 2 halves
1484 // (t0 and t1 are omitted)
1485 int slots_of_int_registers = Register::max_slots_per_register * (Register::number_of_registers - 2);
1486 if (reg < slots_of_int_registers) {
1487 return rc_int;
1488 }
1489
1490 // we have 32 float register * 2 halves
1491 int slots_of_float_registers = FloatRegister::max_slots_per_register * FloatRegister::number_of_registers;
1492 if (reg < slots_of_int_registers + slots_of_float_registers) {
1493 return rc_float;
1494 }
1495
1496 // we have 32 vector register * 4 halves
1497 int slots_of_vector_registers = VectorRegister::max_slots_per_register * VectorRegister::number_of_registers;
1498 if (reg < slots_of_int_registers + slots_of_float_registers + slots_of_vector_registers) {
1499 return rc_vector;
1500 }
1501
1502 // Between vector regs & stack is the flags regs.
1503 assert(OptoReg::is_stack(reg), "blow up if spilling flags");
1504
1505 return rc_stack;
1506 }
1507
1508 uint MachSpillCopyNode::implementation(CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream *st) const {
1509 assert_cond(ra_ != NULL);
1510 Compile* C = ra_->C;
1511
1512 // Get registers to move.
1513 OptoReg::Name src_hi = ra_->get_reg_second(in(1));
1514 OptoReg::Name src_lo = ra_->get_reg_first(in(1));
1515 OptoReg::Name dst_hi = ra_->get_reg_second(this);
1516 OptoReg::Name dst_lo = ra_->get_reg_first(this);
1517
1518 enum RC src_hi_rc = rc_class(src_hi);
1519 enum RC src_lo_rc = rc_class(src_lo);
1520 enum RC dst_hi_rc = rc_class(dst_hi);
1521 enum RC dst_lo_rc = rc_class(dst_lo);
1522
1523 assert(src_lo != OptoReg::Bad && dst_lo != OptoReg::Bad, "must move at least 1 register");
1524
1525 if (src_hi != OptoReg::Bad) {
1526 assert((src_lo & 1) == 0 && src_lo + 1 == src_hi &&
1527 (dst_lo & 1) == 0 && dst_lo + 1 == dst_hi,
1528 "expected aligned-adjacent pairs");
1529 }
1530
1531 if (src_lo == dst_lo && src_hi == dst_hi) {
1532 return 0; // Self copy, no move.
1533 }
1534
1535 bool is64 = (src_lo & 1) == 0 && src_lo + 1 == src_hi &&
1536 (dst_lo & 1) == 0 && dst_lo + 1 == dst_hi;
1537 int src_offset = ra_->reg2offset(src_lo);
1538 int dst_offset = ra_->reg2offset(dst_lo);
1539
1540 if (bottom_type()->isa_vect() != NULL) {
1541 uint ireg = ideal_reg();
1542 if (ireg == Op_VecA && cbuf) {
1543 C2_MacroAssembler _masm(cbuf);
1544 int vector_reg_size_in_bytes = Matcher::scalable_vector_reg_size(T_BYTE);
1545 if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
1546 // stack to stack
1547 __ spill_copy_vector_stack_to_stack(src_offset, dst_offset,
1548 vector_reg_size_in_bytes);
1549 } else if (src_lo_rc == rc_vector && dst_lo_rc == rc_stack) {
1550 // vpr to stack
1551 __ spill(as_VectorRegister(Matcher::_regEncode[src_lo]), ra_->reg2offset(dst_lo));
1552 } else if (src_lo_rc == rc_stack && dst_lo_rc == rc_vector) {
1553 // stack to vpr
1554 __ unspill(as_VectorRegister(Matcher::_regEncode[dst_lo]), ra_->reg2offset(src_lo));
1555 } else if (src_lo_rc == rc_vector && dst_lo_rc == rc_vector) {
1556 // vpr to vpr
1557 __ vmv1r_v(as_VectorRegister(Matcher::_regEncode[dst_lo]), as_VectorRegister(Matcher::_regEncode[src_lo]));
1558 } else {
1559 ShouldNotReachHere();
1560 }
1561 }
1562 } else if (cbuf != NULL) {
1563 C2_MacroAssembler _masm(cbuf);
1564 switch (src_lo_rc) {
1565 case rc_int:
1566 if (dst_lo_rc == rc_int) { // gpr --> gpr copy
1567 if (!is64 && this->ideal_reg() != Op_RegI) { // zero extended for narrow oop or klass
1568 __ zero_extend(as_Register(Matcher::_regEncode[dst_lo]), as_Register(Matcher::_regEncode[src_lo]), 32);
1569 } else {
1570 __ mv(as_Register(Matcher::_regEncode[dst_lo]), as_Register(Matcher::_regEncode[src_lo]));
1571 }
1572 } else if (dst_lo_rc == rc_float) { // gpr --> fpr copy
1573 if (is64) {
1574 __ fmv_d_x(as_FloatRegister(Matcher::_regEncode[dst_lo]),
1575 as_Register(Matcher::_regEncode[src_lo]));
1576 } else {
1577 __ fmv_w_x(as_FloatRegister(Matcher::_regEncode[dst_lo]),
1578 as_Register(Matcher::_regEncode[src_lo]));
1579 }
1580 } else { // gpr --> stack spill
1581 assert(dst_lo_rc == rc_stack, "spill to bad register class");
1582 __ spill(as_Register(Matcher::_regEncode[src_lo]), is64, dst_offset);
1583 }
1584 break;
1585 case rc_float:
1586 if (dst_lo_rc == rc_int) { // fpr --> gpr copy
1587 if (is64) {
1588 __ fmv_x_d(as_Register(Matcher::_regEncode[dst_lo]),
1589 as_FloatRegister(Matcher::_regEncode[src_lo]));
1590 } else {
1591 __ fmv_x_w(as_Register(Matcher::_regEncode[dst_lo]),
1592 as_FloatRegister(Matcher::_regEncode[src_lo]));
1593 }
1594 } else if (dst_lo_rc == rc_float) { // fpr --> fpr copy
1595 if (is64) {
1596 __ fmv_d(as_FloatRegister(Matcher::_regEncode[dst_lo]),
1597 as_FloatRegister(Matcher::_regEncode[src_lo]));
1598 } else {
1599 __ fmv_s(as_FloatRegister(Matcher::_regEncode[dst_lo]),
1600 as_FloatRegister(Matcher::_regEncode[src_lo]));
1601 }
1602 } else { // fpr --> stack spill
1603 assert(dst_lo_rc == rc_stack, "spill to bad register class");
1604 __ spill(as_FloatRegister(Matcher::_regEncode[src_lo]),
1605 is64, dst_offset);
1606 }
1607 break;
1608 case rc_stack:
1609 if (dst_lo_rc == rc_int) { // stack --> gpr load
1610 if (this->ideal_reg() == Op_RegI) {
1611 __ unspill(as_Register(Matcher::_regEncode[dst_lo]), is64, src_offset);
1612 } else { // // zero extended for narrow oop or klass
1613 __ unspillu(as_Register(Matcher::_regEncode[dst_lo]), is64, src_offset);
1614 }
1615 } else if (dst_lo_rc == rc_float) { // stack --> fpr load
1616 __ unspill(as_FloatRegister(Matcher::_regEncode[dst_lo]),
1617 is64, src_offset);
1618 } else { // stack --> stack copy
1619 assert(dst_lo_rc == rc_stack, "spill to bad register class");
1620 if (this->ideal_reg() == Op_RegI) {
1621 __ unspill(t0, is64, src_offset);
1622 } else { // zero extended for narrow oop or klass
1623 __ unspillu(t0, is64, src_offset);
1624 }
1625 __ spill(t0, is64, dst_offset);
1626 }
1627 break;
1628 default:
1629 ShouldNotReachHere();
1630 }
1631 }
1632
1633 if (st != NULL) {
1634 st->print("spill ");
1635 if (src_lo_rc == rc_stack) {
1636 st->print("[sp, #%d] -> ", src_offset);
1637 } else {
1638 st->print("%s -> ", Matcher::regName[src_lo]);
1639 }
1640 if (dst_lo_rc == rc_stack) {
1641 st->print("[sp, #%d]", dst_offset);
1642 } else {
1643 st->print("%s", Matcher::regName[dst_lo]);
1644 }
1645 if (bottom_type()->isa_vect() != NULL) {
1646 int vsize = 0;
1647 if (ideal_reg() == Op_VecA) {
1648 vsize = Matcher::scalable_vector_reg_size(T_BYTE) * 8;
1649 } else {
1650 ShouldNotReachHere();
1651 }
1652 st->print("\t# vector spill size = %d", vsize);
1653 } else {
1654 st->print("\t# spill size = %d", is64 ? 64 : 32);
1655 }
1656 }
1657
1658 return 0;
1659 }
1660
1661 #ifndef PRODUCT
1662 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1663 if (ra_ == NULL) {
1664 st->print("N%d = SpillCopy(N%d)", _idx, in(1)->_idx);
1665 } else {
1666 implementation(NULL, ra_, false, st);
1667 }
1668 }
1669 #endif
1670
1671 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1672 implementation(&cbuf, ra_, false, NULL);
1673 }
1674
1675 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1676 return MachNode::size(ra_);
1677 }
1678
1679 //=============================================================================
1680
1681 #ifndef PRODUCT
1682 void BoxLockNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1683 assert_cond(ra_ != NULL && st != NULL);
1684 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1685 int reg = ra_->get_reg_first(this);
1686 st->print("add %s, sp, #%d\t# box lock",
1687 Matcher::regName[reg], offset);
1688 }
1689 #endif
1690
1691 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1692 C2_MacroAssembler _masm(&cbuf);
1693 Assembler::IncompressibleRegion ir(&_masm); // Fixed length: see BoxLockNode::size()
1694
1695 assert_cond(ra_ != NULL);
1696 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1697 int reg = ra_->get_encode(this);
1698
1699 if (is_imm_in_range(offset, 12, 0)) {
1700 __ addi(as_Register(reg), sp, offset);
1701 } else if (is_imm_in_range(offset, 32, 0)) {
1702 __ li32(t0, offset);
1703 __ add(as_Register(reg), sp, t0);
1704 } else {
1705 ShouldNotReachHere();
1706 }
1707 }
1708
1709 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1710 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_).
1711 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1712
1713 if (is_imm_in_range(offset, 12, 0)) {
1714 return NativeInstruction::instruction_size;
1715 } else {
1716 return 3 * NativeInstruction::instruction_size; // lui + addiw + add;
1717 }
1718 }
1719
1720 //=============================================================================
1721
1722 #ifndef PRODUCT
1723 void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1724 {
1725 assert_cond(st != NULL);
1726 st->print_cr("# MachUEPNode");
1727 if (UseCompressedClassPointers) {
1728 st->print_cr("\tlwu t0, [j_rarg0, oopDesc::klass_offset_in_bytes()]\t# compressed klass");
1729 if (CompressedKlassPointers::shift() != 0) {
1730 st->print_cr("\tdecode_klass_not_null t0, t0");
1731 }
1732 } else {
1733 st->print_cr("\tld t0, [j_rarg0, oopDesc::klass_offset_in_bytes()]\t# compressed klass");
1734 }
1735 st->print_cr("\tbeq t0, t1, ic_hit");
1736 st->print_cr("\tj, SharedRuntime::_ic_miss_stub\t # Inline cache check");
1737 st->print_cr("\tic_hit:");
1738 }
1739 #endif
1740
1741 void MachUEPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
1742 {
1743 // This is the unverified entry point.
1744 C2_MacroAssembler _masm(&cbuf);
1745
1746 Label skip;
1747 __ cmp_klass(j_rarg0, t1, t0, t2 /* call-clobbered t2 as a tmp */, skip);
1748 __ far_jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1749 __ bind(skip);
1750
1751 // These NOPs are critical so that verified entry point is properly
1752 // 4 bytes aligned for patching by NativeJump::patch_verified_entry()
1753 __ align(NativeInstruction::instruction_size);
1754 }
1755
1756 uint MachUEPNode::size(PhaseRegAlloc* ra_) const
1757 {
1758 assert_cond(ra_ != NULL);
1759 return MachNode::size(ra_);
1760 }
1761
1762 // REQUIRED EMIT CODE
1763
1764 //=============================================================================
1765
1766 // Emit exception handler code.
1767 int HandlerImpl::emit_exception_handler(CodeBuffer& cbuf)
1768 {
1769 // la_patchable t0, #exception_blob_entry_point
1770 // jr (offset)t0
1771 // or
1772 // j #exception_blob_entry_point
1773 // Note that the code buffer's insts_mark is always relative to insts.
1774 // That's why we must use the macroassembler to generate a handler.
1775 C2_MacroAssembler _masm(&cbuf);
1776 address base = __ start_a_stub(size_exception_handler());
1777 if (base == NULL) {
1778 ciEnv::current()->record_failure("CodeCache is full");
1779 return 0; // CodeBuffer::expand failed
1780 }
1781 int offset = __ offset();
1782 __ far_jump(RuntimeAddress(OptoRuntime::exception_blob()->entry_point()));
1783 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1784 __ end_a_stub();
1785 return offset;
1786 }
1787
1788 // Emit deopt handler code.
1789 int HandlerImpl::emit_deopt_handler(CodeBuffer& cbuf)
1790 {
1791 // Note that the code buffer's insts_mark is always relative to insts.
1792 // That's why we must use the macroassembler to generate a handler.
1793 C2_MacroAssembler _masm(&cbuf);
1794 address base = __ start_a_stub(size_deopt_handler());
1795 if (base == NULL) {
1796 ciEnv::current()->record_failure("CodeCache is full");
1797 return 0; // CodeBuffer::expand failed
1798 }
1799 int offset = __ offset();
1800
1801 __ auipc(ra, 0);
1802 __ far_jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
1803
1804 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1805 __ end_a_stub();
1806 return offset;
1807
1808 }
1809 // REQUIRED MATCHER CODE
1810
1811 //=============================================================================
1812
1813 const bool Matcher::match_rule_supported(int opcode) {
1814 if (!has_match_rule(opcode)) {
1815 return false;
1816 }
1817
1818 switch (opcode) {
1819 case Op_OnSpinWait:
1820 return VM_Version::supports_on_spin_wait();
1821 case Op_CacheWB: // fall through
1822 case Op_CacheWBPreSync: // fall through
1823 case Op_CacheWBPostSync:
1824 if (!VM_Version::supports_data_cache_line_flush()) {
1825 return false;
1826 }
1827 break;
1828
1829 case Op_StrCompressedCopy: // fall through
1830 case Op_StrInflatedCopy: // fall through
1831 case Op_CountPositives:
1832 return UseRVV;
1833
1834 case Op_EncodeISOArray:
1835 return UseRVV && SpecialEncodeISOArray;
1836
1837 case Op_PopCountI:
1838 case Op_PopCountL:
1839 return UsePopCountInstruction;
1840
1841 case Op_RotateRight:
1842 case Op_RotateLeft:
1843 case Op_CountLeadingZerosI:
1844 case Op_CountLeadingZerosL:
1845 case Op_CountTrailingZerosI:
1846 case Op_CountTrailingZerosL:
1847 return UseZbb;
1848
1849 case Op_ConvF2HF:
1850 case Op_ConvHF2F:
1851 return UseZfhmin;
1852 }
1853
1854 return true; // Per default match rules are supported.
1855 }
1856
1857 const bool Matcher::match_rule_supported_superword(int opcode, int vlen, BasicType bt) {
1858 return match_rule_supported_vector(opcode, vlen, bt);
1859 }
1860
1861 // Identify extra cases that we might want to provide match rules for vector nodes and
1862 // other intrinsics guarded with vector length (vlen) and element type (bt).
1863 const bool Matcher::match_rule_supported_vector(int opcode, int vlen, BasicType bt) {
1864 if (!match_rule_supported(opcode) || !vector_size_supported(bt, vlen)) {
1865 return false;
1866 }
1867
1868 return op_vec_supported(opcode);
1869 }
1870
1871 const bool Matcher::match_rule_supported_vector_masked(int opcode, int vlen, BasicType bt) {
1872 return false;
1873 }
1874
1875 const bool Matcher::vector_needs_partial_operations(Node* node, const TypeVect* vt) {
1876 return false;
1877 }
1878
1879 const RegMask* Matcher::predicate_reg_mask(void) {
1880 return NULL;
1881 }
1882
1883 const TypeVectMask* Matcher::predicate_reg_type(const Type* elemTy, int length) {
1884 return NULL;
1885 }
1886
1887 // Vector calling convention not yet implemented.
1888 const bool Matcher::supports_vector_calling_convention(void) {
1889 return false;
1890 }
1891
1892 OptoRegPair Matcher::vector_return_value(uint ideal_reg) {
1893 Unimplemented();
1894 return OptoRegPair(0, 0);
1895 }
1896
1897 // Is this branch offset short enough that a short branch can be used?
1898 //
1899 // NOTE: If the platform does not provide any short branch variants, then
1900 // this method should return false for offset 0.
1901 // |---label(L1)-----|
1902 // |-----------------|
1903 // |-----------------|----------eq: float-------------------
1904 // |-----------------| // far_cmpD_branch | cmpD_branch
1905 // |------- ---------| feq; | feq;
1906 // |-far_cmpD_branch-| beqz done; | bnez L;
1907 // |-----------------| j L; |
1908 // |-----------------| bind(done); |
1909 // |-----------------|--------------------------------------
1910 // |-----------------| // so shortBrSize = br_size - 4;
1911 // |-----------------| // so offs = offset - shortBrSize + 4;
1912 // |---label(L2)-----|
1913 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1914 // The passed offset is relative to address of the branch.
1915 int shortBrSize = br_size - 4;
1916 int offs = offset - shortBrSize + 4;
1917 return (-4096 <= offs && offs < 4096);
1918 }
1919
1920 // Vector width in bytes.
1921 const int Matcher::vector_width_in_bytes(BasicType bt) {
1922 if (UseRVV) {
1923 // The MaxVectorSize should have been set by detecting RVV max vector register size when check UseRVV.
1924 // MaxVectorSize == VM_Version::_initial_vector_length
1925 int size = MaxVectorSize;
1926 // Minimum 2 values in vector
1927 if (size < 2 * type2aelembytes(bt)) size = 0;
1928 // But never < 4
1929 if (size < 4) size = 0;
1930 return size;
1931 }
1932 return 0;
1933 }
1934
1935 // Limits on vector size (number of elements) loaded into vector.
1936 const int Matcher::max_vector_size(const BasicType bt) {
1937 return vector_width_in_bytes(bt) / type2aelembytes(bt);
1938 }
1939
1940 const int Matcher::min_vector_size(const BasicType bt) {
1941 int max_size = max_vector_size(bt);
1942 // Limit the min vector size to 8 bytes.
1943 int size = 8 / type2aelembytes(bt);
1944 if (bt == T_BOOLEAN) {
1945 // To support vector api load/store mask.
1946 size = 2;
1947 }
1948 if (size < 2) size = 2;
1949 return MIN2(size, max_size);
1950 }
1951
1952 // Vector ideal reg.
1953 const uint Matcher::vector_ideal_reg(int len) {
1954 assert(MaxVectorSize >= len, "");
1955 if (UseRVV) {
1956 return Op_VecA;
1957 }
1958
1959 ShouldNotReachHere();
1960 return 0;
1961 }
1962
1963 const int Matcher::scalable_vector_reg_size(const BasicType bt) {
1964 return Matcher::max_vector_size(bt);
1965 }
1966
1967 MachOper* Matcher::pd_specialize_generic_vector_operand(MachOper* original_opnd, uint ideal_reg, bool is_temp) {
1968 ShouldNotReachHere(); // generic vector operands not supported
1969 return NULL;
1970 }
1971
1972 bool Matcher::is_reg2reg_move(MachNode* m) {
1973 ShouldNotReachHere(); // generic vector operands not supported
1974 return false;
1975 }
1976
1977 bool Matcher::is_generic_vector(MachOper* opnd) {
1978 ShouldNotReachHere(); // generic vector operands not supported
1979 return false;
1980 }
1981
1982 // Return whether or not this register is ever used as an argument.
1983 // This function is used on startup to build the trampoline stubs in
1984 // generateOptoStub. Registers not mentioned will be killed by the VM
1985 // call in the trampoline, and arguments in those registers not be
1986 // available to the callee.
1987 bool Matcher::can_be_java_arg(int reg)
1988 {
1989 return
1990 reg == R10_num || reg == R10_H_num ||
1991 reg == R11_num || reg == R11_H_num ||
1992 reg == R12_num || reg == R12_H_num ||
1993 reg == R13_num || reg == R13_H_num ||
1994 reg == R14_num || reg == R14_H_num ||
1995 reg == R15_num || reg == R15_H_num ||
1996 reg == R16_num || reg == R16_H_num ||
1997 reg == R17_num || reg == R17_H_num ||
1998 reg == F10_num || reg == F10_H_num ||
1999 reg == F11_num || reg == F11_H_num ||
2000 reg == F12_num || reg == F12_H_num ||
2001 reg == F13_num || reg == F13_H_num ||
2002 reg == F14_num || reg == F14_H_num ||
2003 reg == F15_num || reg == F15_H_num ||
2004 reg == F16_num || reg == F16_H_num ||
2005 reg == F17_num || reg == F17_H_num;
2006 }
2007
2008 bool Matcher::is_spillable_arg(int reg)
2009 {
2010 return can_be_java_arg(reg);
2011 }
2012
2013 uint Matcher::int_pressure_limit()
2014 {
2015 // A derived pointer is live at CallNode and then is flagged by RA
2016 // as a spilled LRG. Spilling heuristics(Spill-USE) explicitly skip
2017 // derived pointers and lastly fail to spill after reaching maximum
2018 // number of iterations. Lowering the default pressure threshold to
2019 // (_NO_SPECIAL_REG32_mask.Size() minus 1) forces CallNode to become
2020 // a high register pressure area of the code so that split_DEF can
2021 // generate DefinitionSpillCopy for the derived pointer.
2022 uint default_int_pressure_threshold = _NO_SPECIAL_REG32_mask.Size() - 1;
2023 if (!PreserveFramePointer) {
2024 // When PreserveFramePointer is off, frame pointer is allocatable,
2025 // but different from other SOC registers, it is excluded from
2026 // fatproj's mask because its save type is No-Save. Decrease 1 to
2027 // ensure high pressure at fatproj when PreserveFramePointer is off.
2028 // See check_pressure_at_fatproj().
2029 default_int_pressure_threshold--;
2030 }
2031 return (INTPRESSURE == -1) ? default_int_pressure_threshold : INTPRESSURE;
2032 }
2033
2034 uint Matcher::float_pressure_limit()
2035 {
2036 // _FLOAT_REG_mask is generated by adlc from the float_reg register class.
2037 return (FLOATPRESSURE == -1) ? _FLOAT_REG_mask.Size() : FLOATPRESSURE;
2038 }
2039
2040 bool Matcher::use_asm_for_ldiv_by_con(jlong divisor) {
2041 return false;
2042 }
2043
2044 RegMask Matcher::divI_proj_mask() {
2045 ShouldNotReachHere();
2046 return RegMask();
2047 }
2048
2049 // Register for MODI projection of divmodI.
2050 RegMask Matcher::modI_proj_mask() {
2051 ShouldNotReachHere();
2052 return RegMask();
2053 }
2054
2055 // Register for DIVL projection of divmodL.
2056 RegMask Matcher::divL_proj_mask() {
2057 ShouldNotReachHere();
2058 return RegMask();
2059 }
2060
2061 // Register for MODL projection of divmodL.
2062 RegMask Matcher::modL_proj_mask() {
2063 ShouldNotReachHere();
2064 return RegMask();
2065 }
2066
2067 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
2068 return FP_REG_mask();
2069 }
2070
2071 bool size_fits_all_mem_uses(AddPNode* addp, int shift) {
2072 assert_cond(addp != NULL);
2073 for (DUIterator_Fast imax, i = addp->fast_outs(imax); i < imax; i++) {
2074 Node* u = addp->fast_out(i);
2075 if (u != NULL && u->is_Mem()) {
2076 int opsize = u->as_Mem()->memory_size();
2077 assert(opsize > 0, "unexpected memory operand size");
2078 if (u->as_Mem()->memory_size() != (1 << shift)) {
2079 return false;
2080 }
2081 }
2082 }
2083 return true;
2084 }
2085
2086 // Should the Matcher clone input 'm' of node 'n'?
2087 bool Matcher::pd_clone_node(Node* n, Node* m, Matcher::MStack& mstack) {
2088 assert_cond(m != NULL);
2089 if (is_vshift_con_pattern(n, m)) { // ShiftV src (ShiftCntV con)
2090 mstack.push(m, Visit); // m = ShiftCntV
2091 return true;
2092 }
2093 return false;
2094 }
2095
2096 // Should the Matcher clone shifts on addressing modes, expecting them
2097 // to be subsumed into complex addressing expressions or compute them
2098 // into registers?
2099 bool Matcher::pd_clone_address_expressions(AddPNode* m, Matcher::MStack& mstack, VectorSet& address_visited) {
2100 return clone_base_plus_offset_address(m, mstack, address_visited);
2101 }
2102
2103 %}
2104
2105
2106
2107 //----------ENCODING BLOCK-----------------------------------------------------
2108 // This block specifies the encoding classes used by the compiler to
2109 // output byte streams. Encoding classes are parameterized macros
2110 // used by Machine Instruction Nodes in order to generate the bit
2111 // encoding of the instruction. Operands specify their base encoding
2112 // interface with the interface keyword. There are currently
2113 // supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, &
2114 // COND_INTER. REG_INTER causes an operand to generate a function
2115 // which returns its register number when queried. CONST_INTER causes
2116 // an operand to generate a function which returns the value of the
2117 // constant when queried. MEMORY_INTER causes an operand to generate
2118 // four functions which return the Base Register, the Index Register,
2119 // the Scale Value, and the Offset Value of the operand when queried.
2120 // COND_INTER causes an operand to generate six functions which return
2121 // the encoding code (ie - encoding bits for the instruction)
2122 // associated with each basic boolean condition for a conditional
2123 // instruction.
2124 //
2125 // Instructions specify two basic values for encoding. Again, a
2126 // function is available to check if the constant displacement is an
2127 // oop. They use the ins_encode keyword to specify their encoding
2128 // classes (which must be a sequence of enc_class names, and their
2129 // parameters, specified in the encoding block), and they use the
2130 // opcode keyword to specify, in order, their primary, secondary, and
2131 // tertiary opcode. Only the opcode sections which a particular
2132 // instruction needs for encoding need to be specified.
2133 encode %{
2134 // BEGIN Non-volatile memory access
2135
2136 enc_class riscv_enc_li_imm(iRegIorL dst, immIorL src) %{
2137 C2_MacroAssembler _masm(&cbuf);
2138 int64_t con = (int64_t)$src$$constant;
2139 Register dst_reg = as_Register($dst$$reg);
2140 __ mv(dst_reg, con);
2141 %}
2142
2143 enc_class riscv_enc_mov_p(iRegP dst, immP src) %{
2144 C2_MacroAssembler _masm(&cbuf);
2145 Register dst_reg = as_Register($dst$$reg);
2146 address con = (address)$src$$constant;
2147 if (con == NULL || con == (address)1) {
2148 ShouldNotReachHere();
2149 } else {
2150 relocInfo::relocType rtype = $src->constant_reloc();
2151 if (rtype == relocInfo::oop_type) {
2152 __ movoop(dst_reg, (jobject)con);
2153 } else if (rtype == relocInfo::metadata_type) {
2154 __ mov_metadata(dst_reg, (Metadata*)con);
2155 } else {
2156 assert(rtype == relocInfo::none, "unexpected reloc type");
2157 __ mv(dst_reg, $src$$constant);
2158 }
2159 }
2160 %}
2161
2162 enc_class riscv_enc_mov_p1(iRegP dst) %{
2163 C2_MacroAssembler _masm(&cbuf);
2164 Register dst_reg = as_Register($dst$$reg);
2165 __ mv(dst_reg, 1);
2166 %}
2167
2168 enc_class riscv_enc_mov_byte_map_base(iRegP dst) %{
2169 C2_MacroAssembler _masm(&cbuf);
2170 __ load_byte_map_base($dst$$Register);
2171 %}
2172
2173 enc_class riscv_enc_mov_n(iRegN dst, immN src) %{
2174 C2_MacroAssembler _masm(&cbuf);
2175 Register dst_reg = as_Register($dst$$reg);
2176 address con = (address)$src$$constant;
2177 if (con == NULL) {
2178 ShouldNotReachHere();
2179 } else {
2180 relocInfo::relocType rtype = $src->constant_reloc();
2181 assert(rtype == relocInfo::oop_type, "unexpected reloc type");
2182 __ set_narrow_oop(dst_reg, (jobject)con);
2183 }
2184 %}
2185
2186 enc_class riscv_enc_mov_zero(iRegNorP dst) %{
2187 C2_MacroAssembler _masm(&cbuf);
2188 Register dst_reg = as_Register($dst$$reg);
2189 __ mv(dst_reg, zr);
2190 %}
2191
2192 enc_class riscv_enc_mov_nk(iRegN dst, immNKlass src) %{
2193 C2_MacroAssembler _masm(&cbuf);
2194 Register dst_reg = as_Register($dst$$reg);
2195 address con = (address)$src$$constant;
2196 if (con == NULL) {
2197 ShouldNotReachHere();
2198 } else {
2199 relocInfo::relocType rtype = $src->constant_reloc();
2200 assert(rtype == relocInfo::metadata_type, "unexpected reloc type");
2201 __ set_narrow_klass(dst_reg, (Klass *)con);
2202 }
2203 %}
2204
2205 enc_class riscv_enc_cmpxchgw(iRegINoSp res, memory mem, iRegI oldval, iRegI newval) %{
2206 C2_MacroAssembler _masm(&cbuf);
2207 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
2208 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
2209 /*result as bool*/ true);
2210 %}
2211
2212 enc_class riscv_enc_cmpxchgn(iRegINoSp res, memory mem, iRegI oldval, iRegI newval) %{
2213 C2_MacroAssembler _masm(&cbuf);
2214 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
2215 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
2216 /*result as bool*/ true);
2217 %}
2218
2219 enc_class riscv_enc_cmpxchg(iRegINoSp res, memory mem, iRegL oldval, iRegL newval) %{
2220 C2_MacroAssembler _masm(&cbuf);
2221 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
2222 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
2223 /*result as bool*/ true);
2224 %}
2225
2226 enc_class riscv_enc_cmpxchgw_acq(iRegINoSp res, memory mem, iRegI oldval, iRegI newval) %{
2227 C2_MacroAssembler _masm(&cbuf);
2228 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
2229 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
2230 /*result as bool*/ true);
2231 %}
2232
2233 enc_class riscv_enc_cmpxchgn_acq(iRegINoSp res, memory mem, iRegI oldval, iRegI newval) %{
2234 C2_MacroAssembler _masm(&cbuf);
2235 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
2236 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
2237 /*result as bool*/ true);
2238 %}
2239
2240 enc_class riscv_enc_cmpxchg_acq(iRegINoSp res, memory mem, iRegL oldval, iRegL newval) %{
2241 C2_MacroAssembler _masm(&cbuf);
2242 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
2243 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
2244 /*result as bool*/ true);
2245 %}
2246
2247 // compare and branch instruction encodings
2248
2249 enc_class riscv_enc_j(label lbl) %{
2250 C2_MacroAssembler _masm(&cbuf);
2251 Label* L = $lbl$$label;
2252 __ j(*L);
2253 %}
2254
2255 enc_class riscv_enc_far_cmpULtGe_imm0_branch(cmpOpULtGe cmp, iRegIorL op1, label lbl) %{
2256 C2_MacroAssembler _masm(&cbuf);
2257 Label* L = $lbl$$label;
2258 switch ($cmp$$cmpcode) {
2259 case(BoolTest::ge):
2260 __ j(*L);
2261 break;
2262 case(BoolTest::lt):
2263 break;
2264 default:
2265 Unimplemented();
2266 }
2267 %}
2268
2269 // call instruction encodings
2270
2271 enc_class riscv_enc_partial_subtype_check(iRegP sub, iRegP super, iRegP temp, iRegP result) %{
2272 Register sub_reg = as_Register($sub$$reg);
2273 Register super_reg = as_Register($super$$reg);
2274 Register temp_reg = as_Register($temp$$reg);
2275 Register result_reg = as_Register($result$$reg);
2276 Register cr_reg = t1;
2277
2278 Label miss;
2279 Label done;
2280 C2_MacroAssembler _masm(&cbuf);
2281 __ check_klass_subtype_slow_path(sub_reg, super_reg, temp_reg, result_reg,
2282 NULL, &miss);
2283 if ($primary) {
2284 __ mv(result_reg, zr);
2285 } else {
2286 __ mv(cr_reg, zr);
2287 __ j(done);
2288 }
2289
2290 __ bind(miss);
2291 if (!$primary) {
2292 __ mv(cr_reg, 1);
2293 }
2294
2295 __ bind(done);
2296 %}
2297
2298 enc_class riscv_enc_java_static_call(method meth) %{
2299 C2_MacroAssembler _masm(&cbuf);
2300 Assembler::IncompressibleRegion ir(&_masm); // Fixed length: see ret_addr_offset
2301
2302 address addr = (address)$meth$$method;
2303 address call = NULL;
2304 assert_cond(addr != NULL);
2305 if (!_method) {
2306 // A call to a runtime wrapper, e.g. new, new_typeArray_Java, uncommon_trap.
2307 call = __ trampoline_call(Address(addr, relocInfo::runtime_call_type));
2308 if (call == NULL) {
2309 ciEnv::current()->record_failure("CodeCache is full");
2310 return;
2311 }
2312 } else {
2313 int method_index = resolved_method_index(cbuf);
2314 RelocationHolder rspec = _optimized_virtual ? opt_virtual_call_Relocation::spec(method_index)
2315 : static_call_Relocation::spec(method_index);
2316 call = __ trampoline_call(Address(addr, rspec));
2317 if (call == NULL) {
2318 ciEnv::current()->record_failure("CodeCache is full");
2319 return;
2320 }
2321
2322 if (CodeBuffer::supports_shared_stubs() && _method->can_be_statically_bound()) {
2323 // Calls of the same statically bound method can share
2324 // a stub to the interpreter.
2325 cbuf.shared_stub_to_interp_for(_method, call - cbuf.insts_begin());
2326 } else {
2327 // Emit stub for static call
2328 address stub = CompiledStaticCall::emit_to_interp_stub(cbuf, call);
2329 if (stub == NULL) {
2330 ciEnv::current()->record_failure("CodeCache is full");
2331 return;
2332 }
2333 }
2334 }
2335
2336 __ post_call_nop();
2337 %}
2338
2339 enc_class riscv_enc_java_dynamic_call(method meth) %{
2340 C2_MacroAssembler _masm(&cbuf);
2341 Assembler::IncompressibleRegion ir(&_masm); // Fixed length: see ret_addr_offset
2342 int method_index = resolved_method_index(cbuf);
2343 address call = __ ic_call((address)$meth$$method, method_index);
2344 if (call == NULL) {
2345 ciEnv::current()->record_failure("CodeCache is full");
2346 return;
2347 }
2348
2349 __ post_call_nop();
2350 %}
2351
2352 enc_class riscv_enc_call_epilog() %{
2353 C2_MacroAssembler _masm(&cbuf);
2354 if (VerifyStackAtCalls) {
2355 // Check that stack depth is unchanged: find majik cookie on stack
2356 __ call_Unimplemented();
2357 }
2358 %}
2359
2360 enc_class riscv_enc_java_to_runtime(method meth) %{
2361 C2_MacroAssembler _masm(&cbuf);
2362 Assembler::IncompressibleRegion ir(&_masm); // Fixed length: see ret_addr_offset
2363
2364 // some calls to generated routines (arraycopy code) are scheduled
2365 // by C2 as runtime calls. if so we can call them using a jr (they
2366 // will be in a reachable segment) otherwise we have to use a jalr
2367 // which loads the absolute address into a register.
2368 address entry = (address)$meth$$method;
2369 CodeBlob *cb = CodeCache::find_blob(entry);
2370 if (cb != NULL) {
2371 address call = __ trampoline_call(Address(entry, relocInfo::runtime_call_type));
2372 if (call == NULL) {
2373 ciEnv::current()->record_failure("CodeCache is full");
2374 return;
2375 }
2376 __ post_call_nop();
2377 } else {
2378 Label retaddr;
2379 __ la(t1, retaddr);
2380 __ la(t0, RuntimeAddress(entry));
2381 // Leave a breadcrumb for JavaFrameAnchor::capture_last_Java_pc()
2382 __ addi(sp, sp, -2 * wordSize);
2383 __ sd(t1, Address(sp, wordSize));
2384 __ jalr(t0);
2385 __ bind(retaddr);
2386 __ post_call_nop();
2387 __ addi(sp, sp, 2 * wordSize);
2388 }
2389 %}
2390
2391 // using the cr register as the bool result: 0 for success; others failed.
2392 enc_class riscv_enc_fast_lock(iRegP object, iRegP box, iRegPNoSp tmp1, iRegPNoSp tmp2) %{
2393 C2_MacroAssembler _masm(&cbuf);
2394 Register flag = t1;
2395 Register oop = as_Register($object$$reg);
2396 Register box = as_Register($box$$reg);
2397 Register disp_hdr = as_Register($tmp1$$reg);
2398 Register tmp = as_Register($tmp2$$reg);
2399 Label cont;
2400 Label object_has_monitor;
2401 Label no_count;
2402
2403 assert_different_registers(oop, box, tmp, disp_hdr, t0);
2404
2405 // Load markWord from object into displaced_header.
2406 __ ld(disp_hdr, Address(oop, oopDesc::mark_offset_in_bytes()));
2407
2408 if (DiagnoseSyncOnValueBasedClasses != 0) {
2409 __ load_klass(flag, oop);
2410 __ lwu(flag, Address(flag, Klass::access_flags_offset()));
2411 __ andi(flag, flag, JVM_ACC_IS_VALUE_BASED_CLASS, tmp /* tmp */);
2412 __ bnez(flag, cont, true /* is_far */);
2413 }
2414
2415 // Check for existing monitor
2416 __ andi(t0, disp_hdr, markWord::monitor_value);
2417 __ bnez(t0, object_has_monitor);
2418
2419 if (!UseHeavyMonitors) {
2420 if (UseFastLocking) {
2421 Label slow;
2422 __ fast_lock(oop, disp_hdr, tmp, t0, slow);
2423 // Indicate success at cont.
2424 __ mv(flag, zr);
2425 __ j(cont);
2426 __ bind(slow);
2427 __ mv(flag, 1); // Set non-zero flag to indicate 'failure' -> take slow-path
2428 } else {
2429 // Set tmp to be (markWord of object | UNLOCK_VALUE).
2430 __ ori(tmp, disp_hdr, markWord::unlocked_value);
2431
2432 // Initialize the box. (Must happen before we update the object mark!)
2433 __ sd(tmp, Address(box, BasicLock::displaced_header_offset_in_bytes()));
2434
2435 // Compare object markWord with an unlocked value (tmp) and if
2436 // equal exchange the stack address of our box with object markWord.
2437 // On failure disp_hdr contains the possibly locked markWord.
2438 __ cmpxchg(/*memory address*/oop, /*expected value*/tmp, /*new value*/box, Assembler::int64, Assembler::aq,
2439 Assembler::rl, /*result*/disp_hdr);
2440 __ mv(flag, zr);
2441 __ beq(disp_hdr, tmp, cont); // prepare zero flag and goto cont if we won the cas
2442
2443 assert(oopDesc::mark_offset_in_bytes() == 0, "offset of _mark is not 0");
2444
2445 // If the compare-and-exchange succeeded, then we found an unlocked
2446 // object, will have now locked it will continue at label cont
2447 // We did not see an unlocked object so try the fast recursive case.
2448
2449 // Check if the owner is self by comparing the value in the
2450 // markWord of object (disp_hdr) with the stack pointer.
2451 __ sub(disp_hdr, disp_hdr, sp);
2452 __ mv(tmp, (intptr_t) (~(os::vm_page_size()-1) | (uintptr_t)markWord::lock_mask_in_place));
2453 // If (mark & lock_mask) == 0 and mark - sp < page_size, we are stack-locking and goto cont,
2454 // hence we can store 0 as the displaced header in the box, which indicates that it is a
2455 // recursive lock.
2456 __ andr(tmp/*==0?*/, disp_hdr, tmp);
2457 __ sd(tmp/*==0, perhaps*/, Address(box, BasicLock::displaced_header_offset_in_bytes()));
2458 __ mv(flag, tmp); // we can use the value of tmp as the result here
2459 }
2460 } else {
2461 __ mv(flag, 1); // Set non-zero flag to indicate 'failure' -> take slow-path
2462 }
2463
2464 __ j(cont);
2465
2466 // Handle existing monitor.
2467 __ bind(object_has_monitor);
2468 // The object's monitor m is unlocked iff m->owner == NULL,
2469 // otherwise m->owner may contain a thread or a stack address.
2470 //
2471 // Try to CAS m->owner from NULL to current thread.
2472 __ add(tmp, disp_hdr, (ObjectMonitor::owner_offset_in_bytes() - markWord::monitor_value));
2473 __ cmpxchg(/*memory address*/tmp, /*expected value*/zr, /*new value*/xthread, Assembler::int64, Assembler::aq,
2474 Assembler::rl, /*result*/flag); // cas succeeds if flag == zr(expected)
2475
2476 if (!UseFastLocking) {
2477 // Store a non-null value into the box to avoid looking like a re-entrant
2478 // lock. The fast-path monitor unlock code checks for
2479 // markWord::monitor_value so use markWord::unused_mark which has the
2480 // relevant bit set, and also matches ObjectSynchronizer::slow_enter.
2481 __ mv(tmp, (address)markWord::unused_mark().value());
2482 __ sd(tmp, Address(box, BasicLock::displaced_header_offset_in_bytes()));
2483 }
2484
2485 __ beqz(flag, cont); // CAS success means locking succeeded
2486
2487 __ bne(flag, xthread, cont); // Check for recursive locking
2488
2489 // Recursive lock case
2490 __ mv(flag, zr);
2491 __ increment(Address(disp_hdr, ObjectMonitor::recursions_offset_in_bytes() - markWord::monitor_value), 1, t0, tmp);
2492
2493 __ bind(cont);
2494
2495 __ bnez(flag, no_count);
2496
2497 __ increment(Address(xthread, JavaThread::held_monitor_count_offset()), 1, t0, tmp);
2498
2499 __ bind(no_count);
2500 %}
2501
2502 // using cr flag to indicate the fast_unlock result: 0 for success; others failed.
2503 enc_class riscv_enc_fast_unlock(iRegP object, iRegP box, iRegPNoSp tmp1, iRegPNoSp tmp2) %{
2504 C2_MacroAssembler _masm(&cbuf);
2505 Register flag = t1;
2506 Register oop = as_Register($object$$reg);
2507 Register box = as_Register($box$$reg);
2508 Register disp_hdr = as_Register($tmp1$$reg);
2509 Register tmp = as_Register($tmp2$$reg);
2510 Label cont;
2511 Label object_has_monitor;
2512 Label no_count;
2513
2514 assert_different_registers(oop, box, tmp, disp_hdr, flag);
2515
2516 if (!UseHeavyMonitors && !UseFastLocking) {
2517 // Find the lock address and load the displaced header from the stack.
2518 __ ld(disp_hdr, Address(box, BasicLock::displaced_header_offset_in_bytes()));
2519
2520 // If the displaced header is 0, we have a recursive unlock.
2521 __ mv(flag, disp_hdr);
2522 __ beqz(disp_hdr, cont);
2523 }
2524
2525 // Handle existing monitor.
2526 __ ld(tmp, Address(oop, oopDesc::mark_offset_in_bytes()));
2527 __ andi(t0, tmp, markWord::monitor_value);
2528 __ bnez(t0, object_has_monitor);
2529
2530 if (!UseHeavyMonitors) {
2531 if (UseFastLocking) {
2532 Label slow;
2533 __ fast_unlock(oop, tmp, box, disp_hdr, slow);
2534
2535 // Indicate success at cont.
2536 __ mv(flag, zr);
2537 __ j(cont);
2538 __ bind(slow);
2539 __ mv(flag, 1); // Set non-zero flag to indicate 'failure' -> take slow path
2540 } else {
2541 // Check if it is still a light weight lock, this is true if we
2542 // see the stack address of the basicLock in the markWord of the
2543 // object.
2544
2545 __ cmpxchg(/*memory address*/oop, /*expected value*/box, /*new value*/disp_hdr, Assembler::int64, Assembler::relaxed,
2546 Assembler::rl, /*result*/tmp);
2547 __ xorr(flag, box, tmp); // box == tmp if cas succeeds
2548 }
2549 } else {
2550 __ mv(flag, 1); // Set non-zero flag to indicate 'failure' -> take slow path
2551 }
2552 __ j(cont);
2553
2554 assert(oopDesc::mark_offset_in_bytes() == 0, "offset of _mark is not 0");
2555
2556 // Handle existing monitor.
2557 __ bind(object_has_monitor);
2558 STATIC_ASSERT(markWord::monitor_value <= INT_MAX);
2559 __ add(tmp, tmp, -(int)markWord::monitor_value); // monitor
2560
2561 if (UseFastLocking) {
2562 Label L;
2563 __ ld(disp_hdr, Address(tmp, ObjectMonitor::owner_offset_in_bytes()));
2564 __ mv(t0, (unsigned char)(intptr_t)ANONYMOUS_OWNER);
2565 __ bne(disp_hdr, t0, L);
2566 __ mv(flag, 1); // Indicate failure at cont -- dive into slow-path.
2567 __ j(cont);
2568 __ bind(L);
2569 }
2570
2571 __ ld(disp_hdr, Address(tmp, ObjectMonitor::recursions_offset_in_bytes()));
2572
2573 Label notRecursive;
2574 __ beqz(disp_hdr, notRecursive); // Will be 0 if not recursive.
2575
2576 // Recursive lock
2577 __ addi(disp_hdr, disp_hdr, -1);
2578 __ sd(disp_hdr, Address(tmp, ObjectMonitor::recursions_offset_in_bytes()));
2579 __ mv(flag, zr);
2580 __ j(cont);
2581
2582 __ bind(notRecursive);
2583 __ ld(flag, Address(tmp, ObjectMonitor::EntryList_offset_in_bytes()));
2584 __ ld(disp_hdr, Address(tmp, ObjectMonitor::cxq_offset_in_bytes()));
2585 __ orr(flag, flag, disp_hdr); // Will be 0 if both are 0.
2586 __ bnez(flag, cont);
2587 // need a release store here
2588 __ la(tmp, Address(tmp, ObjectMonitor::owner_offset_in_bytes()));
2589 __ membar(MacroAssembler::LoadStore | MacroAssembler::StoreStore);
2590 __ sd(zr, Address(tmp)); // set unowned
2591
2592 __ bind(cont);
2593
2594 __ bnez(flag, no_count);
2595
2596 __ decrement(Address(xthread, JavaThread::held_monitor_count_offset()), 1, t0, tmp);
2597
2598 __ bind(no_count);
2599 %}
2600
2601 // arithmetic encodings
2602
2603 enc_class riscv_enc_divw(iRegI dst, iRegI src1, iRegI src2) %{
2604 C2_MacroAssembler _masm(&cbuf);
2605 Register dst_reg = as_Register($dst$$reg);
2606 Register src1_reg = as_Register($src1$$reg);
2607 Register src2_reg = as_Register($src2$$reg);
2608 __ corrected_idivl(dst_reg, src1_reg, src2_reg, false);
2609 %}
2610
2611 enc_class riscv_enc_div(iRegI dst, iRegI src1, iRegI src2) %{
2612 C2_MacroAssembler _masm(&cbuf);
2613 Register dst_reg = as_Register($dst$$reg);
2614 Register src1_reg = as_Register($src1$$reg);
2615 Register src2_reg = as_Register($src2$$reg);
2616 __ corrected_idivq(dst_reg, src1_reg, src2_reg, false);
2617 %}
2618
2619 enc_class riscv_enc_modw(iRegI dst, iRegI src1, iRegI src2) %{
2620 C2_MacroAssembler _masm(&cbuf);
2621 Register dst_reg = as_Register($dst$$reg);
2622 Register src1_reg = as_Register($src1$$reg);
2623 Register src2_reg = as_Register($src2$$reg);
2624 __ corrected_idivl(dst_reg, src1_reg, src2_reg, true);
2625 %}
2626
2627 enc_class riscv_enc_mod(iRegI dst, iRegI src1, iRegI src2) %{
2628 C2_MacroAssembler _masm(&cbuf);
2629 Register dst_reg = as_Register($dst$$reg);
2630 Register src1_reg = as_Register($src1$$reg);
2631 Register src2_reg = as_Register($src2$$reg);
2632 __ corrected_idivq(dst_reg, src1_reg, src2_reg, true);
2633 %}
2634
2635 enc_class riscv_enc_tail_call(iRegP jump_target) %{
2636 C2_MacroAssembler _masm(&cbuf);
2637 Register target_reg = as_Register($jump_target$$reg);
2638 __ jr(target_reg);
2639 %}
2640
2641 enc_class riscv_enc_tail_jmp(iRegP jump_target) %{
2642 C2_MacroAssembler _masm(&cbuf);
2643 Register target_reg = as_Register($jump_target$$reg);
2644 // exception oop should be in x10
2645 // ret addr has been popped into ra
2646 // callee expects it in x13
2647 __ mv(x13, ra);
2648 __ jr(target_reg);
2649 %}
2650
2651 enc_class riscv_enc_rethrow() %{
2652 C2_MacroAssembler _masm(&cbuf);
2653 __ far_jump(RuntimeAddress(OptoRuntime::rethrow_stub()));
2654 %}
2655
2656 enc_class riscv_enc_ret() %{
2657 C2_MacroAssembler _masm(&cbuf);
2658 __ ret();
2659 %}
2660
2661 %}
2662
2663 //----------FRAME--------------------------------------------------------------
2664 // Definition of frame structure and management information.
2665 //
2666 // S T A C K L A Y O U T Allocators stack-slot number
2667 // | (to get allocators register number
2668 // G Owned by | | v add OptoReg::stack0())
2669 // r CALLER | |
2670 // o | +--------+ pad to even-align allocators stack-slot
2671 // w V | pad0 | numbers; owned by CALLER
2672 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
2673 // h ^ | in | 5
2674 // | | args | 4 Holes in incoming args owned by SELF
2675 // | | | | 3
2676 // | | +--------+
2677 // V | | old out| Empty on Intel, window on Sparc
2678 // | old |preserve| Must be even aligned.
2679 // | SP-+--------+----> Matcher::_old_SP, even aligned
2680 // | | in | 3 area for Intel ret address
2681 // Owned by |preserve| Empty on Sparc.
2682 // SELF +--------+
2683 // | | pad2 | 2 pad to align old SP
2684 // | +--------+ 1
2685 // | | locks | 0
2686 // | +--------+----> OptoReg::stack0(), even aligned
2687 // | | pad1 | 11 pad to align new SP
2688 // | +--------+
2689 // | | | 10
2690 // | | spills | 9 spills
2691 // V | | 8 (pad0 slot for callee)
2692 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
2693 // ^ | out | 7
2694 // | | args | 6 Holes in outgoing args owned by CALLEE
2695 // Owned by +--------+
2696 // CALLEE | new out| 6 Empty on Intel, window on Sparc
2697 // | new |preserve| Must be even-aligned.
2698 // | SP-+--------+----> Matcher::_new_SP, even aligned
2699 // | | |
2700 //
2701 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
2702 // known from SELF's arguments and the Java calling convention.
2703 // Region 6-7 is determined per call site.
2704 // Note 2: If the calling convention leaves holes in the incoming argument
2705 // area, those holes are owned by SELF. Holes in the outgoing area
2706 // are owned by the CALLEE. Holes should not be necessary in the
2707 // incoming area, as the Java calling convention is completely under
2708 // the control of the AD file. Doubles can be sorted and packed to
2709 // avoid holes. Holes in the outgoing arguments may be necessary for
2710 // varargs C calling conventions.
2711 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
2712 // even aligned with pad0 as needed.
2713 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
2714 // (the latter is true on Intel but is it false on RISCV?)
2715 // region 6-11 is even aligned; it may be padded out more so that
2716 // the region from SP to FP meets the minimum stack alignment.
2717 // Note 4: For I2C adapters, the incoming FP may not meet the minimum stack
2718 // alignment. Region 11, pad1, may be dynamically extended so that
2719 // SP meets the minimum alignment.
2720
2721 frame %{
2722 // These three registers define part of the calling convention
2723 // between compiled code and the interpreter.
2724
2725 // Inline Cache Register or methodOop for I2C.
2726 inline_cache_reg(R31);
2727
2728 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
2729 cisc_spilling_operand_name(indOffset);
2730
2731 // Number of stack slots consumed by locking an object
2732 // generate Compile::sync_stack_slots
2733 // VMRegImpl::slots_per_word = wordSize / stack_slot_size = 8 / 4 = 2
2734 sync_stack_slots(1 * VMRegImpl::slots_per_word);
2735
2736 // Compiled code's Frame Pointer
2737 frame_pointer(R2);
2738
2739 // Interpreter stores its frame pointer in a register which is
2740 // stored to the stack by I2CAdaptors.
2741 // I2CAdaptors convert from interpreted java to compiled java.
2742 interpreter_frame_pointer(R8);
2743
2744 // Stack alignment requirement
2745 stack_alignment(StackAlignmentInBytes); // Alignment size in bytes (128-bit -> 16 bytes)
2746
2747 // Number of outgoing stack slots killed above the out_preserve_stack_slots
2748 // for calls to C. Supports the var-args backing area for register parms.
2749 varargs_C_out_slots_killed(frame::arg_reg_save_area_bytes / BytesPerInt);
2750
2751 // The after-PROLOG location of the return address. Location of
2752 // return address specifies a type (REG or STACK) and a number
2753 // representing the register number (i.e. - use a register name) or
2754 // stack slot.
2755 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
2756 // Otherwise, it is above the locks and verification slot and alignment word
2757 // TODO this may well be correct but need to check why that - 2 is there
2758 // ppc port uses 0 but we definitely need to allow for fixed_slots
2759 // which folds in the space used for monitors
2760 return_addr(STACK - 2 +
2761 align_up((Compile::current()->in_preserve_stack_slots() +
2762 Compile::current()->fixed_slots()),
2763 stack_alignment_in_slots()));
2764
2765 // Location of compiled Java return values. Same as C for now.
2766 return_value
2767 %{
2768 assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL,
2769 "only return normal values");
2770
2771 static const int lo[Op_RegL + 1] = { // enum name
2772 0, // Op_Node
2773 0, // Op_Set
2774 R10_num, // Op_RegN
2775 R10_num, // Op_RegI
2776 R10_num, // Op_RegP
2777 F10_num, // Op_RegF
2778 F10_num, // Op_RegD
2779 R10_num // Op_RegL
2780 };
2781
2782 static const int hi[Op_RegL + 1] = { // enum name
2783 0, // Op_Node
2784 0, // Op_Set
2785 OptoReg::Bad, // Op_RegN
2786 OptoReg::Bad, // Op_RegI
2787 R10_H_num, // Op_RegP
2788 OptoReg::Bad, // Op_RegF
2789 F10_H_num, // Op_RegD
2790 R10_H_num // Op_RegL
2791 };
2792
2793 return OptoRegPair(hi[ideal_reg], lo[ideal_reg]);
2794 %}
2795 %}
2796
2797 //----------ATTRIBUTES---------------------------------------------------------
2798 //----------Operand Attributes-------------------------------------------------
2799 op_attrib op_cost(1); // Required cost attribute
2800
2801 //----------Instruction Attributes---------------------------------------------
2802 ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute
2803 ins_attrib ins_size(32); // Required size attribute (in bits)
2804 ins_attrib ins_short_branch(0); // Required flag: is this instruction
2805 // a non-matching short branch variant
2806 // of some long branch?
2807 ins_attrib ins_alignment(4); // Required alignment attribute (must
2808 // be a power of 2) specifies the
2809 // alignment that some part of the
2810 // instruction (not necessarily the
2811 // start) requires. If > 1, a
2812 // compute_padding() function must be
2813 // provided for the instruction
2814
2815 //----------OPERANDS-----------------------------------------------------------
2816 // Operand definitions must precede instruction definitions for correct parsing
2817 // in the ADLC because operands constitute user defined types which are used in
2818 // instruction definitions.
2819
2820 //----------Simple Operands----------------------------------------------------
2821
2822 // Integer operands 32 bit
2823 // 32 bit immediate
2824 operand immI()
2825 %{
2826 match(ConI);
2827
2828 op_cost(0);
2829 format %{ %}
2830 interface(CONST_INTER);
2831 %}
2832
2833 // 32 bit zero
2834 operand immI0()
2835 %{
2836 predicate(n->get_int() == 0);
2837 match(ConI);
2838
2839 op_cost(0);
2840 format %{ %}
2841 interface(CONST_INTER);
2842 %}
2843
2844 // 32 bit unit increment
2845 operand immI_1()
2846 %{
2847 predicate(n->get_int() == 1);
2848 match(ConI);
2849
2850 op_cost(0);
2851 format %{ %}
2852 interface(CONST_INTER);
2853 %}
2854
2855 // 32 bit unit decrement
2856 operand immI_M1()
2857 %{
2858 predicate(n->get_int() == -1);
2859 match(ConI);
2860
2861 op_cost(0);
2862 format %{ %}
2863 interface(CONST_INTER);
2864 %}
2865
2866 // Unsigned Integer Immediate: 6-bit int, greater than 32
2867 operand uimmI6_ge32() %{
2868 predicate(((unsigned int)(n->get_int()) < 64) && (n->get_int() >= 32));
2869 match(ConI);
2870 op_cost(0);
2871 format %{ %}
2872 interface(CONST_INTER);
2873 %}
2874
2875 operand immI_le_4()
2876 %{
2877 predicate(n->get_int() <= 4);
2878 match(ConI);
2879
2880 op_cost(0);
2881 format %{ %}
2882 interface(CONST_INTER);
2883 %}
2884
2885 operand immI_16()
2886 %{
2887 predicate(n->get_int() == 16);
2888 match(ConI);
2889 op_cost(0);
2890 format %{ %}
2891 interface(CONST_INTER);
2892 %}
2893
2894 operand immI_24()
2895 %{
2896 predicate(n->get_int() == 24);
2897 match(ConI);
2898 op_cost(0);
2899 format %{ %}
2900 interface(CONST_INTER);
2901 %}
2902
2903 operand immI_31()
2904 %{
2905 predicate(n->get_int() == 31);
2906 match(ConI);
2907
2908 op_cost(0);
2909 format %{ %}
2910 interface(CONST_INTER);
2911 %}
2912
2913 operand immI_63()
2914 %{
2915 predicate(n->get_int() == 63);
2916 match(ConI);
2917
2918 op_cost(0);
2919 format %{ %}
2920 interface(CONST_INTER);
2921 %}
2922
2923 // 32 bit integer valid for add immediate
2924 operand immIAdd()
2925 %{
2926 predicate(Assembler::operand_valid_for_add_immediate((int64_t)n->get_int()));
2927 match(ConI);
2928 op_cost(0);
2929 format %{ %}
2930 interface(CONST_INTER);
2931 %}
2932
2933 // 32 bit integer valid for sub immediate
2934 operand immISub()
2935 %{
2936 predicate(Assembler::operand_valid_for_add_immediate(-(int64_t)n->get_int()));
2937 match(ConI);
2938 op_cost(0);
2939 format %{ %}
2940 interface(CONST_INTER);
2941 %}
2942
2943 // 5 bit signed value.
2944 operand immI5()
2945 %{
2946 predicate(n->get_int() <= 15 && n->get_int() >= -16);
2947 match(ConI);
2948
2949 op_cost(0);
2950 format %{ %}
2951 interface(CONST_INTER);
2952 %}
2953
2954 // 5 bit signed value (simm5)
2955 operand immL5()
2956 %{
2957 predicate(n->get_long() <= 15 && n->get_long() >= -16);
2958 match(ConL);
2959
2960 op_cost(0);
2961 format %{ %}
2962 interface(CONST_INTER);
2963 %}
2964
2965 // Integer operands 64 bit
2966 // 64 bit immediate
2967 operand immL()
2968 %{
2969 match(ConL);
2970
2971 op_cost(0);
2972 format %{ %}
2973 interface(CONST_INTER);
2974 %}
2975
2976 // 64 bit zero
2977 operand immL0()
2978 %{
2979 predicate(n->get_long() == 0);
2980 match(ConL);
2981
2982 op_cost(0);
2983 format %{ %}
2984 interface(CONST_INTER);
2985 %}
2986
2987 // Pointer operands
2988 // Pointer Immediate
2989 operand immP()
2990 %{
2991 match(ConP);
2992
2993 op_cost(0);
2994 format %{ %}
2995 interface(CONST_INTER);
2996 %}
2997
2998 // NULL Pointer Immediate
2999 operand immP0()
3000 %{
3001 predicate(n->get_ptr() == 0);
3002 match(ConP);
3003
3004 op_cost(0);
3005 format %{ %}
3006 interface(CONST_INTER);
3007 %}
3008
3009 // Pointer Immediate One
3010 // this is used in object initialization (initial object header)
3011 operand immP_1()
3012 %{
3013 predicate(n->get_ptr() == 1);
3014 match(ConP);
3015
3016 op_cost(0);
3017 format %{ %}
3018 interface(CONST_INTER);
3019 %}
3020
3021 // Card Table Byte Map Base
3022 operand immByteMapBase()
3023 %{
3024 // Get base of card map
3025 predicate(BarrierSet::barrier_set()->is_a(BarrierSet::CardTableBarrierSet) &&
3026 (CardTable::CardValue*)n->get_ptr() ==
3027 ((CardTableBarrierSet*)(BarrierSet::barrier_set()))->card_table()->byte_map_base());
3028 match(ConP);
3029
3030 op_cost(0);
3031 format %{ %}
3032 interface(CONST_INTER);
3033 %}
3034
3035 // Int Immediate: low 16-bit mask
3036 operand immI_16bits()
3037 %{
3038 predicate(n->get_int() == 0xFFFF);
3039 match(ConI);
3040 op_cost(0);
3041 format %{ %}
3042 interface(CONST_INTER);
3043 %}
3044
3045 operand immIpowerOf2() %{
3046 predicate(is_power_of_2((juint)(n->get_int())));
3047 match(ConI);
3048 op_cost(0);
3049 format %{ %}
3050 interface(CONST_INTER);
3051 %}
3052
3053 // Long Immediate: low 32-bit mask
3054 operand immL_32bits()
3055 %{
3056 predicate(n->get_long() == 0xFFFFFFFFL);
3057 match(ConL);
3058 op_cost(0);
3059 format %{ %}
3060 interface(CONST_INTER);
3061 %}
3062
3063 // 64 bit unit decrement
3064 operand immL_M1()
3065 %{
3066 predicate(n->get_long() == -1);
3067 match(ConL);
3068
3069 op_cost(0);
3070 format %{ %}
3071 interface(CONST_INTER);
3072 %}
3073
3074
3075 // 32 bit offset of pc in thread anchor
3076
3077 operand immL_pc_off()
3078 %{
3079 predicate(n->get_long() == in_bytes(JavaThread::frame_anchor_offset()) +
3080 in_bytes(JavaFrameAnchor::last_Java_pc_offset()));
3081 match(ConL);
3082
3083 op_cost(0);
3084 format %{ %}
3085 interface(CONST_INTER);
3086 %}
3087
3088 // 64 bit integer valid for add immediate
3089 operand immLAdd()
3090 %{
3091 predicate(Assembler::operand_valid_for_add_immediate(n->get_long()));
3092 match(ConL);
3093 op_cost(0);
3094 format %{ %}
3095 interface(CONST_INTER);
3096 %}
3097
3098 // 64 bit integer valid for sub immediate
3099 operand immLSub()
3100 %{
3101 predicate(Assembler::operand_valid_for_add_immediate(-(n->get_long())));
3102 match(ConL);
3103 op_cost(0);
3104 format %{ %}
3105 interface(CONST_INTER);
3106 %}
3107
3108 // Narrow pointer operands
3109 // Narrow Pointer Immediate
3110 operand immN()
3111 %{
3112 match(ConN);
3113
3114 op_cost(0);
3115 format %{ %}
3116 interface(CONST_INTER);
3117 %}
3118
3119 // Narrow NULL Pointer Immediate
3120 operand immN0()
3121 %{
3122 predicate(n->get_narrowcon() == 0);
3123 match(ConN);
3124
3125 op_cost(0);
3126 format %{ %}
3127 interface(CONST_INTER);
3128 %}
3129
3130 operand immNKlass()
3131 %{
3132 match(ConNKlass);
3133
3134 op_cost(0);
3135 format %{ %}
3136 interface(CONST_INTER);
3137 %}
3138
3139 // Float and Double operands
3140 // Double Immediate
3141 operand immD()
3142 %{
3143 match(ConD);
3144 op_cost(0);
3145 format %{ %}
3146 interface(CONST_INTER);
3147 %}
3148
3149 // Double Immediate: +0.0d
3150 operand immD0()
3151 %{
3152 predicate(jlong_cast(n->getd()) == 0);
3153 match(ConD);
3154
3155 op_cost(0);
3156 format %{ %}
3157 interface(CONST_INTER);
3158 %}
3159
3160 // Float Immediate
3161 operand immF()
3162 %{
3163 match(ConF);
3164 op_cost(0);
3165 format %{ %}
3166 interface(CONST_INTER);
3167 %}
3168
3169 // Float Immediate: +0.0f.
3170 operand immF0()
3171 %{
3172 predicate(jint_cast(n->getf()) == 0);
3173 match(ConF);
3174
3175 op_cost(0);
3176 format %{ %}
3177 interface(CONST_INTER);
3178 %}
3179
3180 operand immIOffset()
3181 %{
3182 predicate(is_imm_in_range(n->get_int(), 12, 0));
3183 match(ConI);
3184 op_cost(0);
3185 format %{ %}
3186 interface(CONST_INTER);
3187 %}
3188
3189 operand immLOffset()
3190 %{
3191 predicate(is_imm_in_range(n->get_long(), 12, 0));
3192 match(ConL);
3193 op_cost(0);
3194 format %{ %}
3195 interface(CONST_INTER);
3196 %}
3197
3198 // Scale values
3199 operand immIScale()
3200 %{
3201 predicate(1 <= n->get_int() && (n->get_int() <= 3));
3202 match(ConI);
3203
3204 op_cost(0);
3205 format %{ %}
3206 interface(CONST_INTER);
3207 %}
3208
3209 // Integer 32 bit Register Operands
3210 operand iRegI()
3211 %{
3212 constraint(ALLOC_IN_RC(any_reg32));
3213 match(RegI);
3214 match(iRegINoSp);
3215 op_cost(0);
3216 format %{ %}
3217 interface(REG_INTER);
3218 %}
3219
3220 // Integer 32 bit Register not Special
3221 operand iRegINoSp()
3222 %{
3223 constraint(ALLOC_IN_RC(no_special_reg32));
3224 match(RegI);
3225 op_cost(0);
3226 format %{ %}
3227 interface(REG_INTER);
3228 %}
3229
3230 // Register R10 only
3231 operand iRegI_R10()
3232 %{
3233 constraint(ALLOC_IN_RC(int_r10_reg));
3234 match(RegI);
3235 match(iRegINoSp);
3236 op_cost(0);
3237 format %{ %}
3238 interface(REG_INTER);
3239 %}
3240
3241 // Register R12 only
3242 operand iRegI_R12()
3243 %{
3244 constraint(ALLOC_IN_RC(int_r12_reg));
3245 match(RegI);
3246 match(iRegINoSp);
3247 op_cost(0);
3248 format %{ %}
3249 interface(REG_INTER);
3250 %}
3251
3252 // Register R13 only
3253 operand iRegI_R13()
3254 %{
3255 constraint(ALLOC_IN_RC(int_r13_reg));
3256 match(RegI);
3257 match(iRegINoSp);
3258 op_cost(0);
3259 format %{ %}
3260 interface(REG_INTER);
3261 %}
3262
3263 // Register R14 only
3264 operand iRegI_R14()
3265 %{
3266 constraint(ALLOC_IN_RC(int_r14_reg));
3267 match(RegI);
3268 match(iRegINoSp);
3269 op_cost(0);
3270 format %{ %}
3271 interface(REG_INTER);
3272 %}
3273
3274 // Integer 64 bit Register Operands
3275 operand iRegL()
3276 %{
3277 constraint(ALLOC_IN_RC(any_reg));
3278 match(RegL);
3279 match(iRegLNoSp);
3280 op_cost(0);
3281 format %{ %}
3282 interface(REG_INTER);
3283 %}
3284
3285 // Integer 64 bit Register not Special
3286 operand iRegLNoSp()
3287 %{
3288 constraint(ALLOC_IN_RC(no_special_reg));
3289 match(RegL);
3290 match(iRegL_R10);
3291 format %{ %}
3292 interface(REG_INTER);
3293 %}
3294
3295 // Long 64 bit Register R28 only
3296 operand iRegL_R28()
3297 %{
3298 constraint(ALLOC_IN_RC(r28_reg));
3299 match(RegL);
3300 match(iRegLNoSp);
3301 op_cost(0);
3302 format %{ %}
3303 interface(REG_INTER);
3304 %}
3305
3306 // Long 64 bit Register R29 only
3307 operand iRegL_R29()
3308 %{
3309 constraint(ALLOC_IN_RC(r29_reg));
3310 match(RegL);
3311 match(iRegLNoSp);
3312 op_cost(0);
3313 format %{ %}
3314 interface(REG_INTER);
3315 %}
3316
3317 // Long 64 bit Register R30 only
3318 operand iRegL_R30()
3319 %{
3320 constraint(ALLOC_IN_RC(r30_reg));
3321 match(RegL);
3322 match(iRegLNoSp);
3323 op_cost(0);
3324 format %{ %}
3325 interface(REG_INTER);
3326 %}
3327
3328 // Pointer Register Operands
3329 // Pointer Register
3330 operand iRegP()
3331 %{
3332 constraint(ALLOC_IN_RC(ptr_reg));
3333 match(RegP);
3334 match(iRegPNoSp);
3335 match(iRegP_R10);
3336 match(iRegP_R15);
3337 match(javaThread_RegP);
3338 op_cost(0);
3339 format %{ %}
3340 interface(REG_INTER);
3341 %}
3342
3343 // Pointer 64 bit Register not Special
3344 operand iRegPNoSp()
3345 %{
3346 constraint(ALLOC_IN_RC(no_special_ptr_reg));
3347 match(RegP);
3348 op_cost(0);
3349 format %{ %}
3350 interface(REG_INTER);
3351 %}
3352
3353 operand iRegP_R10()
3354 %{
3355 constraint(ALLOC_IN_RC(r10_reg));
3356 match(RegP);
3357 // match(iRegP);
3358 match(iRegPNoSp);
3359 op_cost(0);
3360 format %{ %}
3361 interface(REG_INTER);
3362 %}
3363
3364 // Pointer 64 bit Register R11 only
3365 operand iRegP_R11()
3366 %{
3367 constraint(ALLOC_IN_RC(r11_reg));
3368 match(RegP);
3369 match(iRegPNoSp);
3370 op_cost(0);
3371 format %{ %}
3372 interface(REG_INTER);
3373 %}
3374
3375 operand iRegP_R12()
3376 %{
3377 constraint(ALLOC_IN_RC(r12_reg));
3378 match(RegP);
3379 // match(iRegP);
3380 match(iRegPNoSp);
3381 op_cost(0);
3382 format %{ %}
3383 interface(REG_INTER);
3384 %}
3385
3386 // Pointer 64 bit Register R13 only
3387 operand iRegP_R13()
3388 %{
3389 constraint(ALLOC_IN_RC(r13_reg));
3390 match(RegP);
3391 match(iRegPNoSp);
3392 op_cost(0);
3393 format %{ %}
3394 interface(REG_INTER);
3395 %}
3396
3397 operand iRegP_R14()
3398 %{
3399 constraint(ALLOC_IN_RC(r14_reg));
3400 match(RegP);
3401 // match(iRegP);
3402 match(iRegPNoSp);
3403 op_cost(0);
3404 format %{ %}
3405 interface(REG_INTER);
3406 %}
3407
3408 operand iRegP_R15()
3409 %{
3410 constraint(ALLOC_IN_RC(r15_reg));
3411 match(RegP);
3412 // match(iRegP);
3413 match(iRegPNoSp);
3414 op_cost(0);
3415 format %{ %}
3416 interface(REG_INTER);
3417 %}
3418
3419 operand iRegP_R16()
3420 %{
3421 constraint(ALLOC_IN_RC(r16_reg));
3422 match(RegP);
3423 // match(iRegP);
3424 match(iRegPNoSp);
3425 op_cost(0);
3426 format %{ %}
3427 interface(REG_INTER);
3428 %}
3429
3430 // Pointer 64 bit Register R28 only
3431 operand iRegP_R28()
3432 %{
3433 constraint(ALLOC_IN_RC(r28_reg));
3434 match(RegP);
3435 match(iRegPNoSp);
3436 op_cost(0);
3437 format %{ %}
3438 interface(REG_INTER);
3439 %}
3440
3441 // Pointer 64 bit Register R30 only
3442 operand iRegP_R30()
3443 %{
3444 constraint(ALLOC_IN_RC(r30_reg));
3445 match(RegP);
3446 match(iRegPNoSp);
3447 op_cost(0);
3448 format %{ %}
3449 interface(REG_INTER);
3450 %}
3451
3452 // Pointer 64 bit Register R31 only
3453 operand iRegP_R31()
3454 %{
3455 constraint(ALLOC_IN_RC(r31_reg));
3456 match(RegP);
3457 match(iRegPNoSp);
3458 op_cost(0);
3459 format %{ %}
3460 interface(REG_INTER);
3461 %}
3462
3463 // Pointer Register Operands
3464 // Narrow Pointer Register
3465 operand iRegN()
3466 %{
3467 constraint(ALLOC_IN_RC(any_reg32));
3468 match(RegN);
3469 match(iRegNNoSp);
3470 op_cost(0);
3471 format %{ %}
3472 interface(REG_INTER);
3473 %}
3474
3475 // Integer 64 bit Register not Special
3476 operand iRegNNoSp()
3477 %{
3478 constraint(ALLOC_IN_RC(no_special_reg32));
3479 match(RegN);
3480 op_cost(0);
3481 format %{ %}
3482 interface(REG_INTER);
3483 %}
3484
3485 // heap base register -- used for encoding immN0
3486 operand iRegIHeapbase()
3487 %{
3488 constraint(ALLOC_IN_RC(heapbase_reg));
3489 match(RegI);
3490 op_cost(0);
3491 format %{ %}
3492 interface(REG_INTER);
3493 %}
3494
3495 // Long 64 bit Register R10 only
3496 operand iRegL_R10()
3497 %{
3498 constraint(ALLOC_IN_RC(r10_reg));
3499 match(RegL);
3500 match(iRegLNoSp);
3501 op_cost(0);
3502 format %{ %}
3503 interface(REG_INTER);
3504 %}
3505
3506 // Float Register
3507 // Float register operands
3508 operand fRegF()
3509 %{
3510 constraint(ALLOC_IN_RC(float_reg));
3511 match(RegF);
3512
3513 op_cost(0);
3514 format %{ %}
3515 interface(REG_INTER);
3516 %}
3517
3518 // Double Register
3519 // Double register operands
3520 operand fRegD()
3521 %{
3522 constraint(ALLOC_IN_RC(double_reg));
3523 match(RegD);
3524
3525 op_cost(0);
3526 format %{ %}
3527 interface(REG_INTER);
3528 %}
3529
3530 // Generic vector class. This will be used for
3531 // all vector operands.
3532 operand vReg()
3533 %{
3534 constraint(ALLOC_IN_RC(vectora_reg));
3535 match(VecA);
3536 op_cost(0);
3537 format %{ %}
3538 interface(REG_INTER);
3539 %}
3540
3541 operand vReg_V1()
3542 %{
3543 constraint(ALLOC_IN_RC(v1_reg));
3544 match(VecA);
3545 match(vReg);
3546 op_cost(0);
3547 format %{ %}
3548 interface(REG_INTER);
3549 %}
3550
3551 operand vReg_V2()
3552 %{
3553 constraint(ALLOC_IN_RC(v2_reg));
3554 match(VecA);
3555 match(vReg);
3556 op_cost(0);
3557 format %{ %}
3558 interface(REG_INTER);
3559 %}
3560
3561 operand vReg_V3()
3562 %{
3563 constraint(ALLOC_IN_RC(v3_reg));
3564 match(VecA);
3565 match(vReg);
3566 op_cost(0);
3567 format %{ %}
3568 interface(REG_INTER);
3569 %}
3570
3571 operand vReg_V4()
3572 %{
3573 constraint(ALLOC_IN_RC(v4_reg));
3574 match(VecA);
3575 match(vReg);
3576 op_cost(0);
3577 format %{ %}
3578 interface(REG_INTER);
3579 %}
3580
3581 operand vReg_V5()
3582 %{
3583 constraint(ALLOC_IN_RC(v5_reg));
3584 match(VecA);
3585 match(vReg);
3586 op_cost(0);
3587 format %{ %}
3588 interface(REG_INTER);
3589 %}
3590
3591 // Java Thread Register
3592 operand javaThread_RegP(iRegP reg)
3593 %{
3594 constraint(ALLOC_IN_RC(java_thread_reg)); // java_thread_reg
3595 match(reg);
3596 op_cost(0);
3597 format %{ %}
3598 interface(REG_INTER);
3599 %}
3600
3601 //----------Memory Operands----------------------------------------------------
3602 // RISCV has only base_plus_offset and literal address mode, so no need to use
3603 // index and scale. Here set index as 0xffffffff and scale as 0x0.
3604 operand indirect(iRegP reg)
3605 %{
3606 constraint(ALLOC_IN_RC(ptr_reg));
3607 match(reg);
3608 op_cost(0);
3609 format %{ "[$reg]" %}
3610 interface(MEMORY_INTER) %{
3611 base($reg);
3612 index(0xffffffff);
3613 scale(0x0);
3614 disp(0x0);
3615 %}
3616 %}
3617
3618 operand indOffI(iRegP reg, immIOffset off)
3619 %{
3620 constraint(ALLOC_IN_RC(ptr_reg));
3621 match(AddP reg off);
3622 op_cost(0);
3623 format %{ "[$reg, $off]" %}
3624 interface(MEMORY_INTER) %{
3625 base($reg);
3626 index(0xffffffff);
3627 scale(0x0);
3628 disp($off);
3629 %}
3630 %}
3631
3632 operand indOffL(iRegP reg, immLOffset off)
3633 %{
3634 constraint(ALLOC_IN_RC(ptr_reg));
3635 match(AddP reg off);
3636 op_cost(0);
3637 format %{ "[$reg, $off]" %}
3638 interface(MEMORY_INTER) %{
3639 base($reg);
3640 index(0xffffffff);
3641 scale(0x0);
3642 disp($off);
3643 %}
3644 %}
3645
3646 operand indirectN(iRegN reg)
3647 %{
3648 predicate(CompressedOops::shift() == 0);
3649 constraint(ALLOC_IN_RC(ptr_reg));
3650 match(DecodeN reg);
3651 op_cost(0);
3652 format %{ "[$reg]\t# narrow" %}
3653 interface(MEMORY_INTER) %{
3654 base($reg);
3655 index(0xffffffff);
3656 scale(0x0);
3657 disp(0x0);
3658 %}
3659 %}
3660
3661 operand indOffIN(iRegN reg, immIOffset off)
3662 %{
3663 predicate(CompressedOops::shift() == 0);
3664 constraint(ALLOC_IN_RC(ptr_reg));
3665 match(AddP (DecodeN reg) off);
3666 op_cost(0);
3667 format %{ "[$reg, $off]\t# narrow" %}
3668 interface(MEMORY_INTER) %{
3669 base($reg);
3670 index(0xffffffff);
3671 scale(0x0);
3672 disp($off);
3673 %}
3674 %}
3675
3676 operand indOffLN(iRegN reg, immLOffset off)
3677 %{
3678 predicate(CompressedOops::shift() == 0);
3679 constraint(ALLOC_IN_RC(ptr_reg));
3680 match(AddP (DecodeN reg) off);
3681 op_cost(0);
3682 format %{ "[$reg, $off]\t# narrow" %}
3683 interface(MEMORY_INTER) %{
3684 base($reg);
3685 index(0xffffffff);
3686 scale(0x0);
3687 disp($off);
3688 %}
3689 %}
3690
3691 // RISCV opto stubs need to write to the pc slot in the thread anchor
3692 operand thread_anchor_pc(javaThread_RegP reg, immL_pc_off off)
3693 %{
3694 constraint(ALLOC_IN_RC(ptr_reg));
3695 match(AddP reg off);
3696 op_cost(0);
3697 format %{ "[$reg, $off]" %}
3698 interface(MEMORY_INTER) %{
3699 base($reg);
3700 index(0xffffffff);
3701 scale(0x0);
3702 disp($off);
3703 %}
3704 %}
3705
3706
3707 //----------Special Memory Operands--------------------------------------------
3708 // Stack Slot Operand - This operand is used for loading and storing temporary
3709 // values on the stack where a match requires a value to
3710 // flow through memory.
3711 operand stackSlotI(sRegI reg)
3712 %{
3713 constraint(ALLOC_IN_RC(stack_slots));
3714 // No match rule because this operand is only generated in matching
3715 // match(RegI);
3716 format %{ "[$reg]" %}
3717 interface(MEMORY_INTER) %{
3718 base(0x02); // RSP
3719 index(0xffffffff); // No Index
3720 scale(0x0); // No Scale
3721 disp($reg); // Stack Offset
3722 %}
3723 %}
3724
3725 operand stackSlotF(sRegF reg)
3726 %{
3727 constraint(ALLOC_IN_RC(stack_slots));
3728 // No match rule because this operand is only generated in matching
3729 // match(RegF);
3730 format %{ "[$reg]" %}
3731 interface(MEMORY_INTER) %{
3732 base(0x02); // RSP
3733 index(0xffffffff); // No Index
3734 scale(0x0); // No Scale
3735 disp($reg); // Stack Offset
3736 %}
3737 %}
3738
3739 operand stackSlotD(sRegD reg)
3740 %{
3741 constraint(ALLOC_IN_RC(stack_slots));
3742 // No match rule because this operand is only generated in matching
3743 // match(RegD);
3744 format %{ "[$reg]" %}
3745 interface(MEMORY_INTER) %{
3746 base(0x02); // RSP
3747 index(0xffffffff); // No Index
3748 scale(0x0); // No Scale
3749 disp($reg); // Stack Offset
3750 %}
3751 %}
3752
3753 operand stackSlotL(sRegL reg)
3754 %{
3755 constraint(ALLOC_IN_RC(stack_slots));
3756 // No match rule because this operand is only generated in matching
3757 // match(RegL);
3758 format %{ "[$reg]" %}
3759 interface(MEMORY_INTER) %{
3760 base(0x02); // RSP
3761 index(0xffffffff); // No Index
3762 scale(0x0); // No Scale
3763 disp($reg); // Stack Offset
3764 %}
3765 %}
3766
3767 // Special operand allowing long args to int ops to be truncated for free
3768
3769 operand iRegL2I(iRegL reg) %{
3770
3771 op_cost(0);
3772
3773 match(ConvL2I reg);
3774
3775 format %{ "l2i($reg)" %}
3776
3777 interface(REG_INTER)
3778 %}
3779
3780
3781 // Comparison Operands
3782 // NOTE: Label is a predefined operand which should not be redefined in
3783 // the AD file. It is generically handled within the ADLC.
3784
3785 //----------Conditional Branch Operands----------------------------------------
3786 // Comparison Op - This is the operation of the comparison, and is limited to
3787 // the following set of codes:
3788 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
3789 //
3790 // Other attributes of the comparison, such as unsignedness, are specified
3791 // by the comparison instruction that sets a condition code flags register.
3792 // That result is represented by a flags operand whose subtype is appropriate
3793 // to the unsignedness (etc.) of the comparison.
3794 //
3795 // Later, the instruction which matches both the Comparison Op (a Bool) and
3796 // the flags (produced by the Cmp) specifies the coding of the comparison op
3797 // by matching a specific subtype of Bool operand below, such as cmpOpU.
3798
3799
3800 // used for signed integral comparisons and fp comparisons
3801 operand cmpOp()
3802 %{
3803 match(Bool);
3804
3805 format %{ "" %}
3806
3807 // the values in interface derives from struct BoolTest::mask
3808 interface(COND_INTER) %{
3809 equal(0x0, "eq");
3810 greater(0x1, "gt");
3811 overflow(0x2, "overflow");
3812 less(0x3, "lt");
3813 not_equal(0x4, "ne");
3814 less_equal(0x5, "le");
3815 no_overflow(0x6, "no_overflow");
3816 greater_equal(0x7, "ge");
3817 %}
3818 %}
3819
3820 // used for unsigned integral comparisons
3821 operand cmpOpU()
3822 %{
3823 match(Bool);
3824
3825 format %{ "" %}
3826 // the values in interface derives from struct BoolTest::mask
3827 interface(COND_INTER) %{
3828 equal(0x0, "eq");
3829 greater(0x1, "gtu");
3830 overflow(0x2, "overflow");
3831 less(0x3, "ltu");
3832 not_equal(0x4, "ne");
3833 less_equal(0x5, "leu");
3834 no_overflow(0x6, "no_overflow");
3835 greater_equal(0x7, "geu");
3836 %}
3837 %}
3838
3839 // used for certain integral comparisons which can be
3840 // converted to bxx instructions
3841 operand cmpOpEqNe()
3842 %{
3843 match(Bool);
3844 op_cost(0);
3845 predicate(n->as_Bool()->_test._test == BoolTest::ne ||
3846 n->as_Bool()->_test._test == BoolTest::eq);
3847
3848 format %{ "" %}
3849 interface(COND_INTER) %{
3850 equal(0x0, "eq");
3851 greater(0x1, "gt");
3852 overflow(0x2, "overflow");
3853 less(0x3, "lt");
3854 not_equal(0x4, "ne");
3855 less_equal(0x5, "le");
3856 no_overflow(0x6, "no_overflow");
3857 greater_equal(0x7, "ge");
3858 %}
3859 %}
3860
3861 operand cmpOpULtGe()
3862 %{
3863 match(Bool);
3864 op_cost(0);
3865 predicate(n->as_Bool()->_test._test == BoolTest::lt ||
3866 n->as_Bool()->_test._test == BoolTest::ge);
3867
3868 format %{ "" %}
3869 interface(COND_INTER) %{
3870 equal(0x0, "eq");
3871 greater(0x1, "gtu");
3872 overflow(0x2, "overflow");
3873 less(0x3, "ltu");
3874 not_equal(0x4, "ne");
3875 less_equal(0x5, "leu");
3876 no_overflow(0x6, "no_overflow");
3877 greater_equal(0x7, "geu");
3878 %}
3879 %}
3880
3881 operand cmpOpUEqNeLeGt()
3882 %{
3883 match(Bool);
3884 op_cost(0);
3885 predicate(n->as_Bool()->_test._test == BoolTest::ne ||
3886 n->as_Bool()->_test._test == BoolTest::eq ||
3887 n->as_Bool()->_test._test == BoolTest::le ||
3888 n->as_Bool()->_test._test == BoolTest::gt);
3889
3890 format %{ "" %}
3891 interface(COND_INTER) %{
3892 equal(0x0, "eq");
3893 greater(0x1, "gtu");
3894 overflow(0x2, "overflow");
3895 less(0x3, "ltu");
3896 not_equal(0x4, "ne");
3897 less_equal(0x5, "leu");
3898 no_overflow(0x6, "no_overflow");
3899 greater_equal(0x7, "geu");
3900 %}
3901 %}
3902
3903
3904 // Flags register, used as output of compare logic
3905 operand rFlagsReg()
3906 %{
3907 constraint(ALLOC_IN_RC(reg_flags));
3908 match(RegFlags);
3909
3910 op_cost(0);
3911 format %{ "RFLAGS" %}
3912 interface(REG_INTER);
3913 %}
3914
3915 // Special Registers
3916
3917 // Method Register
3918 operand inline_cache_RegP(iRegP reg)
3919 %{
3920 constraint(ALLOC_IN_RC(method_reg)); // inline_cache_reg
3921 match(reg);
3922 match(iRegPNoSp);
3923 op_cost(0);
3924 format %{ %}
3925 interface(REG_INTER);
3926 %}
3927
3928 //----------OPERAND CLASSES----------------------------------------------------
3929 // Operand Classes are groups of operands that are used as to simplify
3930 // instruction definitions by not requiring the AD writer to specify
3931 // separate instructions for every form of operand when the
3932 // instruction accepts multiple operand types with the same basic
3933 // encoding and format. The classic case of this is memory operands.
3934
3935 // memory is used to define read/write location for load/store
3936 // instruction defs. we can turn a memory op into an Address
3937
3938 opclass memory(indirect, indOffI, indOffL, indirectN, indOffIN, indOffLN);
3939
3940 // iRegIorL2I is used for src inputs in rules for 32 bit int (I)
3941 // operations. it allows the src to be either an iRegI or a (ConvL2I
3942 // iRegL). in the latter case the l2i normally planted for a ConvL2I
3943 // can be elided because the 32-bit instruction will just employ the
3944 // lower 32 bits anyway.
3945 //
3946 // n.b. this does not elide all L2I conversions. if the truncated
3947 // value is consumed by more than one operation then the ConvL2I
3948 // cannot be bundled into the consuming nodes so an l2i gets planted
3949 // (actually an addiw $dst, $src, 0) and the downstream instructions
3950 // consume the result of the L2I as an iRegI input. That's a shame since
3951 // the addiw is actually redundant but its not too costly.
3952
3953 opclass iRegIorL2I(iRegI, iRegL2I);
3954 opclass iRegIorL(iRegI, iRegL);
3955 opclass iRegNorP(iRegN, iRegP);
3956 opclass iRegILNP(iRegI, iRegL, iRegN, iRegP);
3957 opclass iRegILNPNoSp(iRegINoSp, iRegLNoSp, iRegNNoSp, iRegPNoSp);
3958 opclass immIorL(immI, immL);
3959
3960 //----------PIPELINE-----------------------------------------------------------
3961 // Rules which define the behavior of the target architectures pipeline.
3962
3963 // For specific pipelines, e.g. generic RISC-V, define the stages of that pipeline
3964 //pipe_desc(ID, EX, MEM, WR);
3965 #define ID S0
3966 #define EX S1
3967 #define MEM S2
3968 #define WR S3
3969
3970 // Integer ALU reg operation
3971 pipeline %{
3972
3973 attributes %{
3974 // RISC-V instructions are of fixed length
3975 fixed_size_instructions; // Fixed size instructions TODO does
3976 max_instructions_per_bundle = 2; // Generic RISC-V 1, Sifive Series 7 2
3977 // RISC-V instructions come in 32-bit word units
3978 instruction_unit_size = 4; // An instruction is 4 bytes long
3979 instruction_fetch_unit_size = 64; // The processor fetches one line
3980 instruction_fetch_units = 1; // of 64 bytes
3981
3982 // List of nop instructions
3983 nops( MachNop );
3984 %}
3985
3986 // We don't use an actual pipeline model so don't care about resources
3987 // or description. we do use pipeline classes to introduce fixed
3988 // latencies
3989
3990 //----------RESOURCES----------------------------------------------------------
3991 // Resources are the functional units available to the machine
3992
3993 // Generic RISC-V pipeline
3994 // 1 decoder
3995 // 1 instruction decoded per cycle
3996 // 1 load/store ops per cycle, 1 branch, 1 FPU
3997 // 1 mul, 1 div
3998
3999 resources ( DECODE,
4000 ALU,
4001 MUL,
4002 DIV,
4003 BRANCH,
4004 LDST,
4005 FPU);
4006
4007 //----------PIPELINE DESCRIPTION-----------------------------------------------
4008 // Pipeline Description specifies the stages in the machine's pipeline
4009
4010 // Define the pipeline as a generic 6 stage pipeline
4011 pipe_desc(S0, S1, S2, S3, S4, S5);
4012
4013 //----------PIPELINE CLASSES---------------------------------------------------
4014 // Pipeline Classes describe the stages in which input and output are
4015 // referenced by the hardware pipeline.
4016
4017 pipe_class fp_dop_reg_reg_s(fRegF dst, fRegF src1, fRegF src2)
4018 %{
4019 single_instruction;
4020 src1 : S1(read);
4021 src2 : S2(read);
4022 dst : S5(write);
4023 DECODE : ID;
4024 FPU : S5;
4025 %}
4026
4027 pipe_class fp_dop_reg_reg_d(fRegD dst, fRegD src1, fRegD src2)
4028 %{
4029 src1 : S1(read);
4030 src2 : S2(read);
4031 dst : S5(write);
4032 DECODE : ID;
4033 FPU : S5;
4034 %}
4035
4036 pipe_class fp_uop_s(fRegF dst, fRegF src)
4037 %{
4038 single_instruction;
4039 src : S1(read);
4040 dst : S5(write);
4041 DECODE : ID;
4042 FPU : S5;
4043 %}
4044
4045 pipe_class fp_uop_d(fRegD dst, fRegD src)
4046 %{
4047 single_instruction;
4048 src : S1(read);
4049 dst : S5(write);
4050 DECODE : ID;
4051 FPU : S5;
4052 %}
4053
4054 pipe_class fp_d2f(fRegF dst, fRegD src)
4055 %{
4056 single_instruction;
4057 src : S1(read);
4058 dst : S5(write);
4059 DECODE : ID;
4060 FPU : S5;
4061 %}
4062
4063 pipe_class fp_f2d(fRegD dst, fRegF src)
4064 %{
4065 single_instruction;
4066 src : S1(read);
4067 dst : S5(write);
4068 DECODE : ID;
4069 FPU : S5;
4070 %}
4071
4072 pipe_class fp_f2i(iRegINoSp dst, fRegF src)
4073 %{
4074 single_instruction;
4075 src : S1(read);
4076 dst : S5(write);
4077 DECODE : ID;
4078 FPU : S5;
4079 %}
4080
4081 pipe_class fp_f2l(iRegLNoSp dst, fRegF src)
4082 %{
4083 single_instruction;
4084 src : S1(read);
4085 dst : S5(write);
4086 DECODE : ID;
4087 FPU : S5;
4088 %}
4089
4090 pipe_class fp_i2f(fRegF dst, iRegIorL2I src)
4091 %{
4092 single_instruction;
4093 src : S1(read);
4094 dst : S5(write);
4095 DECODE : ID;
4096 FPU : S5;
4097 %}
4098
4099 pipe_class fp_l2f(fRegF dst, iRegL src)
4100 %{
4101 single_instruction;
4102 src : S1(read);
4103 dst : S5(write);
4104 DECODE : ID;
4105 FPU : S5;
4106 %}
4107
4108 pipe_class fp_d2i(iRegINoSp dst, fRegD src)
4109 %{
4110 single_instruction;
4111 src : S1(read);
4112 dst : S5(write);
4113 DECODE : ID;
4114 FPU : S5;
4115 %}
4116
4117 pipe_class fp_d2l(iRegLNoSp dst, fRegD src)
4118 %{
4119 single_instruction;
4120 src : S1(read);
4121 dst : S5(write);
4122 DECODE : ID;
4123 FPU : S5;
4124 %}
4125
4126 pipe_class fp_i2d(fRegD dst, iRegIorL2I src)
4127 %{
4128 single_instruction;
4129 src : S1(read);
4130 dst : S5(write);
4131 DECODE : ID;
4132 FPU : S5;
4133 %}
4134
4135 pipe_class fp_l2d(fRegD dst, iRegIorL2I src)
4136 %{
4137 single_instruction;
4138 src : S1(read);
4139 dst : S5(write);
4140 DECODE : ID;
4141 FPU : S5;
4142 %}
4143
4144 pipe_class fp_div_s(fRegF dst, fRegF src1, fRegF src2)
4145 %{
4146 single_instruction;
4147 src1 : S1(read);
4148 src2 : S2(read);
4149 dst : S5(write);
4150 DECODE : ID;
4151 FPU : S5;
4152 %}
4153
4154 pipe_class fp_div_d(fRegD dst, fRegD src1, fRegD src2)
4155 %{
4156 single_instruction;
4157 src1 : S1(read);
4158 src2 : S2(read);
4159 dst : S5(write);
4160 DECODE : ID;
4161 FPU : S5;
4162 %}
4163
4164 pipe_class fp_sqrt_s(fRegF dst, fRegF src1, fRegF src2)
4165 %{
4166 single_instruction;
4167 src1 : S1(read);
4168 src2 : S2(read);
4169 dst : S5(write);
4170 DECODE : ID;
4171 FPU : S5;
4172 %}
4173
4174 pipe_class fp_sqrt_d(fRegD dst, fRegD src1, fRegD src2)
4175 %{
4176 single_instruction;
4177 src1 : S1(read);
4178 src2 : S2(read);
4179 dst : S5(write);
4180 DECODE : ID;
4181 FPU : S5;
4182 %}
4183
4184 pipe_class fp_load_constant_s(fRegF dst)
4185 %{
4186 single_instruction;
4187 dst : S5(write);
4188 DECODE : ID;
4189 FPU : S5;
4190 %}
4191
4192 pipe_class fp_load_constant_d(fRegD dst)
4193 %{
4194 single_instruction;
4195 dst : S5(write);
4196 DECODE : ID;
4197 FPU : S5;
4198 %}
4199
4200 pipe_class fp_load_mem_s(fRegF dst, memory mem)
4201 %{
4202 single_instruction;
4203 mem : S1(read);
4204 dst : S5(write);
4205 DECODE : ID;
4206 LDST : MEM;
4207 %}
4208
4209 pipe_class fp_load_mem_d(fRegD dst, memory mem)
4210 %{
4211 single_instruction;
4212 mem : S1(read);
4213 dst : S5(write);
4214 DECODE : ID;
4215 LDST : MEM;
4216 %}
4217
4218 pipe_class fp_store_reg_s(fRegF src, memory mem)
4219 %{
4220 single_instruction;
4221 src : S1(read);
4222 mem : S5(write);
4223 DECODE : ID;
4224 LDST : MEM;
4225 %}
4226
4227 pipe_class fp_store_reg_d(fRegD src, memory mem)
4228 %{
4229 single_instruction;
4230 src : S1(read);
4231 mem : S5(write);
4232 DECODE : ID;
4233 LDST : MEM;
4234 %}
4235
4236 //------- Integer ALU operations --------------------------
4237
4238 // Integer ALU reg-reg operation
4239 // Operands needs in ID, result generated in EX
4240 // E.g. ADD Rd, Rs1, Rs2
4241 pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2)
4242 %{
4243 single_instruction;
4244 dst : EX(write);
4245 src1 : ID(read);
4246 src2 : ID(read);
4247 DECODE : ID;
4248 ALU : EX;
4249 %}
4250
4251 // Integer ALU reg operation with constant shift
4252 // E.g. SLLI Rd, Rs1, #shift
4253 pipe_class ialu_reg_shift(iRegI dst, iRegI src1)
4254 %{
4255 single_instruction;
4256 dst : EX(write);
4257 src1 : ID(read);
4258 DECODE : ID;
4259 ALU : EX;
4260 %}
4261
4262 // Integer ALU reg-reg operation with variable shift
4263 // both operands must be available in ID
4264 // E.g. SLL Rd, Rs1, Rs2
4265 pipe_class ialu_reg_reg_vshift(iRegI dst, iRegI src1, iRegI src2)
4266 %{
4267 single_instruction;
4268 dst : EX(write);
4269 src1 : ID(read);
4270 src2 : ID(read);
4271 DECODE : ID;
4272 ALU : EX;
4273 %}
4274
4275 // Integer ALU reg operation
4276 // E.g. NEG Rd, Rs2
4277 pipe_class ialu_reg(iRegI dst, iRegI src)
4278 %{
4279 single_instruction;
4280 dst : EX(write);
4281 src : ID(read);
4282 DECODE : ID;
4283 ALU : EX;
4284 %}
4285
4286 // Integer ALU reg immediate operation
4287 // E.g. ADDI Rd, Rs1, #imm
4288 pipe_class ialu_reg_imm(iRegI dst, iRegI src1)
4289 %{
4290 single_instruction;
4291 dst : EX(write);
4292 src1 : ID(read);
4293 DECODE : ID;
4294 ALU : EX;
4295 %}
4296
4297 // Integer ALU immediate operation (no source operands)
4298 // E.g. LI Rd, #imm
4299 pipe_class ialu_imm(iRegI dst)
4300 %{
4301 single_instruction;
4302 dst : EX(write);
4303 DECODE : ID;
4304 ALU : EX;
4305 %}
4306
4307 //------- Multiply pipeline operations --------------------
4308
4309 // Multiply reg-reg
4310 // E.g. MULW Rd, Rs1, Rs2
4311 pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2)
4312 %{
4313 single_instruction;
4314 dst : WR(write);
4315 src1 : ID(read);
4316 src2 : ID(read);
4317 DECODE : ID;
4318 MUL : WR;
4319 %}
4320
4321 // E.g. MUL RD, Rs1, Rs2
4322 pipe_class lmul_reg_reg(iRegL dst, iRegL src1, iRegL src2)
4323 %{
4324 single_instruction;
4325 fixed_latency(3); // Maximum latency for 64 bit mul
4326 dst : WR(write);
4327 src1 : ID(read);
4328 src2 : ID(read);
4329 DECODE : ID;
4330 MUL : WR;
4331 %}
4332
4333 //------- Divide pipeline operations --------------------
4334
4335 // E.g. DIVW Rd, Rs1, Rs2
4336 pipe_class idiv_reg_reg(iRegI dst, iRegI src1, iRegI src2)
4337 %{
4338 single_instruction;
4339 fixed_latency(8); // Maximum latency for 32 bit divide
4340 dst : WR(write);
4341 src1 : ID(read);
4342 src2 : ID(read);
4343 DECODE : ID;
4344 DIV : WR;
4345 %}
4346
4347 // E.g. DIV RD, Rs1, Rs2
4348 pipe_class ldiv_reg_reg(iRegL dst, iRegL src1, iRegL src2)
4349 %{
4350 single_instruction;
4351 fixed_latency(16); // Maximum latency for 64 bit divide
4352 dst : WR(write);
4353 src1 : ID(read);
4354 src2 : ID(read);
4355 DECODE : ID;
4356 DIV : WR;
4357 %}
4358
4359 //------- Load pipeline operations ------------------------
4360
4361 // Load - prefetch
4362 // Eg. PREFETCH_W mem
4363 pipe_class iload_prefetch(memory mem)
4364 %{
4365 single_instruction;
4366 mem : ID(read);
4367 DECODE : ID;
4368 LDST : MEM;
4369 %}
4370
4371 // Load - reg, mem
4372 // E.g. LA Rd, mem
4373 pipe_class iload_reg_mem(iRegI dst, memory mem)
4374 %{
4375 single_instruction;
4376 dst : WR(write);
4377 mem : ID(read);
4378 DECODE : ID;
4379 LDST : MEM;
4380 %}
4381
4382 // Load - reg, reg
4383 // E.g. LD Rd, Rs
4384 pipe_class iload_reg_reg(iRegI dst, iRegI src)
4385 %{
4386 single_instruction;
4387 dst : WR(write);
4388 src : ID(read);
4389 DECODE : ID;
4390 LDST : MEM;
4391 %}
4392
4393 //------- Store pipeline operations -----------------------
4394
4395 // Store - zr, mem
4396 // E.g. SD zr, mem
4397 pipe_class istore_mem(memory mem)
4398 %{
4399 single_instruction;
4400 mem : ID(read);
4401 DECODE : ID;
4402 LDST : MEM;
4403 %}
4404
4405 // Store - reg, mem
4406 // E.g. SD Rs, mem
4407 pipe_class istore_reg_mem(iRegI src, memory mem)
4408 %{
4409 single_instruction;
4410 mem : ID(read);
4411 src : EX(read);
4412 DECODE : ID;
4413 LDST : MEM;
4414 %}
4415
4416 // Store - reg, reg
4417 // E.g. SD Rs2, Rs1
4418 pipe_class istore_reg_reg(iRegI dst, iRegI src)
4419 %{
4420 single_instruction;
4421 dst : ID(read);
4422 src : EX(read);
4423 DECODE : ID;
4424 LDST : MEM;
4425 %}
4426
4427 //------- Control transfer pipeline operations ------------
4428
4429 // Branch
4430 pipe_class pipe_branch()
4431 %{
4432 single_instruction;
4433 DECODE : ID;
4434 BRANCH : EX;
4435 %}
4436
4437 // Branch
4438 pipe_class pipe_branch_reg(iRegI src)
4439 %{
4440 single_instruction;
4441 src : ID(read);
4442 DECODE : ID;
4443 BRANCH : EX;
4444 %}
4445
4446 // Compare & Branch
4447 // E.g. BEQ Rs1, Rs2, L
4448 pipe_class pipe_cmp_branch(iRegI src1, iRegI src2)
4449 %{
4450 single_instruction;
4451 src1 : ID(read);
4452 src2 : ID(read);
4453 DECODE : ID;
4454 BRANCH : EX;
4455 %}
4456
4457 // E.g. BEQZ Rs, L
4458 pipe_class pipe_cmpz_branch(iRegI src)
4459 %{
4460 single_instruction;
4461 src : ID(read);
4462 DECODE : ID;
4463 BRANCH : EX;
4464 %}
4465
4466 //------- Synchronisation operations ----------------------
4467 // Any operation requiring serialization
4468 // E.g. FENCE/Atomic Ops/Load Acquire/Store Release
4469 pipe_class pipe_serial()
4470 %{
4471 single_instruction;
4472 force_serialization;
4473 fixed_latency(16);
4474 DECODE : ID;
4475 LDST : MEM;
4476 %}
4477
4478 pipe_class pipe_slow()
4479 %{
4480 instruction_count(10);
4481 multiple_bundles;
4482 force_serialization;
4483 fixed_latency(16);
4484 DECODE : ID;
4485 LDST : MEM;
4486 %}
4487
4488 // Empty pipeline class
4489 pipe_class pipe_class_empty()
4490 %{
4491 single_instruction;
4492 fixed_latency(0);
4493 %}
4494
4495 // Default pipeline class.
4496 pipe_class pipe_class_default()
4497 %{
4498 single_instruction;
4499 fixed_latency(2);
4500 %}
4501
4502 // Pipeline class for compares.
4503 pipe_class pipe_class_compare()
4504 %{
4505 single_instruction;
4506 fixed_latency(16);
4507 %}
4508
4509 // Pipeline class for memory operations.
4510 pipe_class pipe_class_memory()
4511 %{
4512 single_instruction;
4513 fixed_latency(16);
4514 %}
4515
4516 // Pipeline class for call.
4517 pipe_class pipe_class_call()
4518 %{
4519 single_instruction;
4520 fixed_latency(100);
4521 %}
4522
4523 // Define the class for the Nop node.
4524 define %{
4525 MachNop = pipe_class_empty;
4526 %}
4527 %}
4528 //----------INSTRUCTIONS-------------------------------------------------------
4529 //
4530 // match -- States which machine-independent subtree may be replaced
4531 // by this instruction.
4532 // ins_cost -- The estimated cost of this instruction is used by instruction
4533 // selection to identify a minimum cost tree of machine
4534 // instructions that matches a tree of machine-independent
4535 // instructions.
4536 // format -- A string providing the disassembly for this instruction.
4537 // The value of an instruction's operand may be inserted
4538 // by referring to it with a '$' prefix.
4539 // opcode -- Three instruction opcodes may be provided. These are referred
4540 // to within an encode class as $primary, $secondary, and $tertiary
4541 // rrspectively. The primary opcode is commonly used to
4542 // indicate the type of machine instruction, while secondary
4543 // and tertiary are often used for prefix options or addressing
4544 // modes.
4545 // ins_encode -- A list of encode classes with parameters. The encode class
4546 // name must have been defined in an 'enc_class' specification
4547 // in the encode section of the architecture description.
4548
4549 // ============================================================================
4550 // Memory (Load/Store) Instructions
4551
4552 // Load Instructions
4553
4554 // Load Byte (8 bit signed)
4555 instruct loadB(iRegINoSp dst, memory mem)
4556 %{
4557 match(Set dst (LoadB mem));
4558
4559 ins_cost(LOAD_COST);
4560 format %{ "lb $dst, $mem\t# byte, #@loadB" %}
4561
4562 ins_encode %{
4563 __ lb(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4564 %}
4565
4566 ins_pipe(iload_reg_mem);
4567 %}
4568
4569 // Load Byte (8 bit signed) into long
4570 instruct loadB2L(iRegLNoSp dst, memory mem)
4571 %{
4572 match(Set dst (ConvI2L (LoadB mem)));
4573
4574 ins_cost(LOAD_COST);
4575 format %{ "lb $dst, $mem\t# byte, #@loadB2L" %}
4576
4577 ins_encode %{
4578 __ lb(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4579 %}
4580
4581 ins_pipe(iload_reg_mem);
4582 %}
4583
4584 // Load Byte (8 bit unsigned)
4585 instruct loadUB(iRegINoSp dst, memory mem)
4586 %{
4587 match(Set dst (LoadUB mem));
4588
4589 ins_cost(LOAD_COST);
4590 format %{ "lbu $dst, $mem\t# byte, #@loadUB" %}
4591
4592 ins_encode %{
4593 __ lbu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4594 %}
4595
4596 ins_pipe(iload_reg_mem);
4597 %}
4598
4599 // Load Byte (8 bit unsigned) into long
4600 instruct loadUB2L(iRegLNoSp dst, memory mem)
4601 %{
4602 match(Set dst (ConvI2L (LoadUB mem)));
4603
4604 ins_cost(LOAD_COST);
4605 format %{ "lbu $dst, $mem\t# byte, #@loadUB2L" %}
4606
4607 ins_encode %{
4608 __ lbu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4609 %}
4610
4611 ins_pipe(iload_reg_mem);
4612 %}
4613
4614 // Load Short (16 bit signed)
4615 instruct loadS(iRegINoSp dst, memory mem)
4616 %{
4617 match(Set dst (LoadS mem));
4618
4619 ins_cost(LOAD_COST);
4620 format %{ "lh $dst, $mem\t# short, #@loadS" %}
4621
4622 ins_encode %{
4623 __ lh(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4624 %}
4625
4626 ins_pipe(iload_reg_mem);
4627 %}
4628
4629 // Load Short (16 bit signed) into long
4630 instruct loadS2L(iRegLNoSp dst, memory mem)
4631 %{
4632 match(Set dst (ConvI2L (LoadS mem)));
4633
4634 ins_cost(LOAD_COST);
4635 format %{ "lh $dst, $mem\t# short, #@loadS2L" %}
4636
4637 ins_encode %{
4638 __ lh(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4639 %}
4640
4641 ins_pipe(iload_reg_mem);
4642 %}
4643
4644 // Load Char (16 bit unsigned)
4645 instruct loadUS(iRegINoSp dst, memory mem)
4646 %{
4647 match(Set dst (LoadUS mem));
4648
4649 ins_cost(LOAD_COST);
4650 format %{ "lhu $dst, $mem\t# short, #@loadUS" %}
4651
4652 ins_encode %{
4653 __ lhu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4654 %}
4655
4656 ins_pipe(iload_reg_mem);
4657 %}
4658
4659 // Load Short/Char (16 bit unsigned) into long
4660 instruct loadUS2L(iRegLNoSp dst, memory mem)
4661 %{
4662 match(Set dst (ConvI2L (LoadUS mem)));
4663
4664 ins_cost(LOAD_COST);
4665 format %{ "lhu $dst, $mem\t# short, #@loadUS2L" %}
4666
4667 ins_encode %{
4668 __ lhu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4669 %}
4670
4671 ins_pipe(iload_reg_mem);
4672 %}
4673
4674 // Load Integer (32 bit signed)
4675 instruct loadI(iRegINoSp dst, memory mem)
4676 %{
4677 match(Set dst (LoadI mem));
4678
4679 ins_cost(LOAD_COST);
4680 format %{ "lw $dst, $mem\t# int, #@loadI" %}
4681
4682 ins_encode %{
4683 __ lw(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4684 %}
4685
4686 ins_pipe(iload_reg_mem);
4687 %}
4688
4689 // Load Integer (32 bit signed) into long
4690 instruct loadI2L(iRegLNoSp dst, memory mem)
4691 %{
4692 match(Set dst (ConvI2L (LoadI mem)));
4693
4694 ins_cost(LOAD_COST);
4695 format %{ "lw $dst, $mem\t# int, #@loadI2L" %}
4696
4697 ins_encode %{
4698 __ lw(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4699 %}
4700
4701 ins_pipe(iload_reg_mem);
4702 %}
4703
4704 // Load Integer (32 bit unsigned) into long
4705 instruct loadUI2L(iRegLNoSp dst, memory mem, immL_32bits mask)
4706 %{
4707 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
4708
4709 ins_cost(LOAD_COST);
4710 format %{ "lwu $dst, $mem\t# int, #@loadUI2L" %}
4711
4712 ins_encode %{
4713 __ lwu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4714 %}
4715
4716 ins_pipe(iload_reg_mem);
4717 %}
4718
4719 // Load Long (64 bit signed)
4720 instruct loadL(iRegLNoSp dst, memory mem)
4721 %{
4722 match(Set dst (LoadL mem));
4723
4724 ins_cost(LOAD_COST);
4725 format %{ "ld $dst, $mem\t# int, #@loadL" %}
4726
4727 ins_encode %{
4728 __ ld(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4729 %}
4730
4731 ins_pipe(iload_reg_mem);
4732 %}
4733
4734 // Load Range
4735 instruct loadRange(iRegINoSp dst, memory mem)
4736 %{
4737 match(Set dst (LoadRange mem));
4738
4739 ins_cost(LOAD_COST);
4740 format %{ "lwu $dst, $mem\t# range, #@loadRange" %}
4741
4742 ins_encode %{
4743 __ lwu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4744 %}
4745
4746 ins_pipe(iload_reg_mem);
4747 %}
4748
4749 // Load Pointer
4750 instruct loadP(iRegPNoSp dst, memory mem)
4751 %{
4752 match(Set dst (LoadP mem));
4753 predicate(n->as_Load()->barrier_data() == 0);
4754
4755 ins_cost(LOAD_COST);
4756 format %{ "ld $dst, $mem\t# ptr, #@loadP" %}
4757
4758 ins_encode %{
4759 __ ld(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4760 %}
4761
4762 ins_pipe(iload_reg_mem);
4763 %}
4764
4765 // Load Compressed Pointer
4766 instruct loadN(iRegNNoSp dst, memory mem)
4767 %{
4768 match(Set dst (LoadN mem));
4769
4770 ins_cost(LOAD_COST);
4771 format %{ "lwu $dst, $mem\t# loadN, compressed ptr, #@loadN" %}
4772
4773 ins_encode %{
4774 __ lwu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4775 %}
4776
4777 ins_pipe(iload_reg_mem);
4778 %}
4779
4780 // Load Klass Pointer
4781 instruct loadKlass(iRegPNoSp dst, memory mem)
4782 %{
4783 match(Set dst (LoadKlass mem));
4784
4785 ins_cost(LOAD_COST);
4786 format %{ "ld $dst, $mem\t# class, #@loadKlass" %}
4787
4788 ins_encode %{
4789 __ ld(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4790 %}
4791
4792 ins_pipe(iload_reg_mem);
4793 %}
4794
4795 // Load Narrow Klass Pointer
4796 instruct loadNKlass(iRegNNoSp dst, memory mem)
4797 %{
4798 match(Set dst (LoadNKlass mem));
4799
4800 ins_cost(LOAD_COST);
4801 format %{ "lwu $dst, $mem\t# loadNKlass, compressed class ptr, #@loadNKlass" %}
4802
4803 ins_encode %{
4804 __ lwu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4805 %}
4806
4807 ins_pipe(iload_reg_mem);
4808 %}
4809
4810 // Load Float
4811 instruct loadF(fRegF dst, memory mem)
4812 %{
4813 match(Set dst (LoadF mem));
4814
4815 ins_cost(LOAD_COST);
4816 format %{ "flw $dst, $mem\t# float, #@loadF" %}
4817
4818 ins_encode %{
4819 __ flw(as_FloatRegister($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4820 %}
4821
4822 ins_pipe(fp_load_mem_s);
4823 %}
4824
4825 // Load Double
4826 instruct loadD(fRegD dst, memory mem)
4827 %{
4828 match(Set dst (LoadD mem));
4829
4830 ins_cost(LOAD_COST);
4831 format %{ "fld $dst, $mem\t# double, #@loadD" %}
4832
4833 ins_encode %{
4834 __ fld(as_FloatRegister($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4835 %}
4836
4837 ins_pipe(fp_load_mem_d);
4838 %}
4839
4840 // Load Int Constant
4841 instruct loadConI(iRegINoSp dst, immI src)
4842 %{
4843 match(Set dst src);
4844
4845 ins_cost(ALU_COST);
4846 format %{ "li $dst, $src\t# int, #@loadConI" %}
4847
4848 ins_encode(riscv_enc_li_imm(dst, src));
4849
4850 ins_pipe(ialu_imm);
4851 %}
4852
4853 // Load Long Constant
4854 instruct loadConL(iRegLNoSp dst, immL src)
4855 %{
4856 match(Set dst src);
4857
4858 ins_cost(ALU_COST);
4859 format %{ "li $dst, $src\t# long, #@loadConL" %}
4860
4861 ins_encode(riscv_enc_li_imm(dst, src));
4862
4863 ins_pipe(ialu_imm);
4864 %}
4865
4866 // Load Pointer Constant
4867 instruct loadConP(iRegPNoSp dst, immP con)
4868 %{
4869 match(Set dst con);
4870
4871 ins_cost(ALU_COST);
4872 format %{ "mv $dst, $con\t# ptr, #@loadConP" %}
4873
4874 ins_encode(riscv_enc_mov_p(dst, con));
4875
4876 ins_pipe(ialu_imm);
4877 %}
4878
4879 // Load Null Pointer Constant
4880 instruct loadConP0(iRegPNoSp dst, immP0 con)
4881 %{
4882 match(Set dst con);
4883
4884 ins_cost(ALU_COST);
4885 format %{ "mv $dst, $con\t# NULL ptr, #@loadConP0" %}
4886
4887 ins_encode(riscv_enc_mov_zero(dst));
4888
4889 ins_pipe(ialu_imm);
4890 %}
4891
4892 // Load Pointer Constant One
4893 instruct loadConP1(iRegPNoSp dst, immP_1 con)
4894 %{
4895 match(Set dst con);
4896
4897 ins_cost(ALU_COST);
4898 format %{ "mv $dst, $con\t# load ptr constant one, #@loadConP1" %}
4899
4900 ins_encode(riscv_enc_mov_p1(dst));
4901
4902 ins_pipe(ialu_imm);
4903 %}
4904
4905 // Load Byte Map Base Constant
4906 instruct loadByteMapBase(iRegPNoSp dst, immByteMapBase con)
4907 %{
4908 match(Set dst con);
4909 ins_cost(ALU_COST);
4910 format %{ "mv $dst, $con\t# Byte Map Base, #@loadByteMapBase" %}
4911
4912 ins_encode(riscv_enc_mov_byte_map_base(dst));
4913
4914 ins_pipe(ialu_imm);
4915 %}
4916
4917 // Load Narrow Pointer Constant
4918 instruct loadConN(iRegNNoSp dst, immN con)
4919 %{
4920 match(Set dst con);
4921
4922 ins_cost(ALU_COST * 4);
4923 format %{ "mv $dst, $con\t# compressed ptr, #@loadConN" %}
4924
4925 ins_encode(riscv_enc_mov_n(dst, con));
4926
4927 ins_pipe(ialu_imm);
4928 %}
4929
4930 // Load Narrow Null Pointer Constant
4931 instruct loadConN0(iRegNNoSp dst, immN0 con)
4932 %{
4933 match(Set dst con);
4934
4935 ins_cost(ALU_COST);
4936 format %{ "mv $dst, $con\t# compressed NULL ptr, #@loadConN0" %}
4937
4938 ins_encode(riscv_enc_mov_zero(dst));
4939
4940 ins_pipe(ialu_imm);
4941 %}
4942
4943 // Load Narrow Klass Constant
4944 instruct loadConNKlass(iRegNNoSp dst, immNKlass con)
4945 %{
4946 match(Set dst con);
4947
4948 ins_cost(ALU_COST * 6);
4949 format %{ "mv $dst, $con\t# compressed klass ptr, #@loadConNKlass" %}
4950
4951 ins_encode(riscv_enc_mov_nk(dst, con));
4952
4953 ins_pipe(ialu_imm);
4954 %}
4955
4956 // Load Float Constant
4957 instruct loadConF(fRegF dst, immF con) %{
4958 match(Set dst con);
4959
4960 ins_cost(LOAD_COST);
4961 format %{
4962 "flw $dst, [$constantaddress]\t# load from constant table: float=$con, #@loadConF"
4963 %}
4964
4965 ins_encode %{
4966 __ flw(as_FloatRegister($dst$$reg), $constantaddress($con));
4967 %}
4968
4969 ins_pipe(fp_load_constant_s);
4970 %}
4971
4972 instruct loadConF0(fRegF dst, immF0 con) %{
4973 match(Set dst con);
4974
4975 ins_cost(XFER_COST);
4976
4977 format %{ "fmv.w.x $dst, zr\t# float, #@loadConF0" %}
4978
4979 ins_encode %{
4980 __ fmv_w_x(as_FloatRegister($dst$$reg), zr);
4981 %}
4982
4983 ins_pipe(fp_load_constant_s);
4984 %}
4985
4986 // Load Double Constant
4987 instruct loadConD(fRegD dst, immD con) %{
4988 match(Set dst con);
4989
4990 ins_cost(LOAD_COST);
4991 format %{
4992 "fld $dst, [$constantaddress]\t# load from constant table: double=$con, #@loadConD"
4993 %}
4994
4995 ins_encode %{
4996 __ fld(as_FloatRegister($dst$$reg), $constantaddress($con));
4997 %}
4998
4999 ins_pipe(fp_load_constant_d);
5000 %}
5001
5002 instruct loadConD0(fRegD dst, immD0 con) %{
5003 match(Set dst con);
5004
5005 ins_cost(XFER_COST);
5006
5007 format %{ "fmv.d.x $dst, zr\t# double, #@loadConD0" %}
5008
5009 ins_encode %{
5010 __ fmv_d_x(as_FloatRegister($dst$$reg), zr);
5011 %}
5012
5013 ins_pipe(fp_load_constant_d);
5014 %}
5015
5016 // Store Instructions
5017 // Store CMS card-mark Immediate
5018 instruct storeimmCM0(immI0 zero, memory mem)
5019 %{
5020 match(Set mem (StoreCM mem zero));
5021
5022 ins_cost(STORE_COST);
5023 format %{ "storestore (elided)\n\t"
5024 "sb zr, $mem\t# byte, #@storeimmCM0" %}
5025
5026 ins_encode %{
5027 __ sb(zr, Address(as_Register($mem$$base), $mem$$disp));
5028 %}
5029
5030 ins_pipe(istore_mem);
5031 %}
5032
5033 // Store CMS card-mark Immediate with intervening StoreStore
5034 // needed when using CMS with no conditional card marking
5035 instruct storeimmCM0_ordered(immI0 zero, memory mem)
5036 %{
5037 match(Set mem (StoreCM mem zero));
5038
5039 ins_cost(ALU_COST + STORE_COST);
5040 format %{ "membar(StoreStore)\n\t"
5041 "sb zr, $mem\t# byte, #@storeimmCM0_ordered" %}
5042
5043 ins_encode %{
5044 __ membar(MacroAssembler::LoadStore | MacroAssembler::StoreStore);
5045 __ sb(zr, Address(as_Register($mem$$base), $mem$$disp));
5046 %}
5047
5048 ins_pipe(istore_mem);
5049 %}
5050
5051 // Store Byte
5052 instruct storeB(iRegIorL2I src, memory mem)
5053 %{
5054 match(Set mem (StoreB mem src));
5055
5056 ins_cost(STORE_COST);
5057 format %{ "sb $src, $mem\t# byte, #@storeB" %}
5058
5059 ins_encode %{
5060 __ sb(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5061 %}
5062
5063 ins_pipe(istore_reg_mem);
5064 %}
5065
5066 instruct storeimmB0(immI0 zero, memory mem)
5067 %{
5068 match(Set mem (StoreB mem zero));
5069
5070 ins_cost(STORE_COST);
5071 format %{ "sb zr, $mem\t# byte, #@storeimmB0" %}
5072
5073 ins_encode %{
5074 __ sb(zr, Address(as_Register($mem$$base), $mem$$disp));
5075 %}
5076
5077 ins_pipe(istore_mem);
5078 %}
5079
5080 // Store Char/Short
5081 instruct storeC(iRegIorL2I src, memory mem)
5082 %{
5083 match(Set mem (StoreC mem src));
5084
5085 ins_cost(STORE_COST);
5086 format %{ "sh $src, $mem\t# short, #@storeC" %}
5087
5088 ins_encode %{
5089 __ sh(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5090 %}
5091
5092 ins_pipe(istore_reg_mem);
5093 %}
5094
5095 instruct storeimmC0(immI0 zero, memory mem)
5096 %{
5097 match(Set mem (StoreC mem zero));
5098
5099 ins_cost(STORE_COST);
5100 format %{ "sh zr, $mem\t# short, #@storeimmC0" %}
5101
5102 ins_encode %{
5103 __ sh(zr, Address(as_Register($mem$$base), $mem$$disp));
5104 %}
5105
5106 ins_pipe(istore_mem);
5107 %}
5108
5109 // Store Integer
5110 instruct storeI(iRegIorL2I src, memory mem)
5111 %{
5112 match(Set mem(StoreI mem src));
5113
5114 ins_cost(STORE_COST);
5115 format %{ "sw $src, $mem\t# int, #@storeI" %}
5116
5117 ins_encode %{
5118 __ sw(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5119 %}
5120
5121 ins_pipe(istore_reg_mem);
5122 %}
5123
5124 instruct storeimmI0(immI0 zero, memory mem)
5125 %{
5126 match(Set mem(StoreI mem zero));
5127
5128 ins_cost(STORE_COST);
5129 format %{ "sw zr, $mem\t# int, #@storeimmI0" %}
5130
5131 ins_encode %{
5132 __ sw(zr, Address(as_Register($mem$$base), $mem$$disp));
5133 %}
5134
5135 ins_pipe(istore_mem);
5136 %}
5137
5138 // Store Long (64 bit signed)
5139 instruct storeL(iRegL src, memory mem)
5140 %{
5141 match(Set mem (StoreL mem src));
5142
5143 ins_cost(STORE_COST);
5144 format %{ "sd $src, $mem\t# long, #@storeL" %}
5145
5146 ins_encode %{
5147 __ sd(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5148 %}
5149
5150 ins_pipe(istore_reg_mem);
5151 %}
5152
5153 // Store Long (64 bit signed)
5154 instruct storeimmL0(immL0 zero, memory mem)
5155 %{
5156 match(Set mem (StoreL mem zero));
5157
5158 ins_cost(STORE_COST);
5159 format %{ "sd zr, $mem\t# long, #@storeimmL0" %}
5160
5161 ins_encode %{
5162 __ sd(zr, Address(as_Register($mem$$base), $mem$$disp));
5163 %}
5164
5165 ins_pipe(istore_mem);
5166 %}
5167
5168 // Store Pointer
5169 instruct storeP(iRegP src, memory mem)
5170 %{
5171 match(Set mem (StoreP mem src));
5172 predicate(n->as_Store()->barrier_data() == 0);
5173
5174 ins_cost(STORE_COST);
5175 format %{ "sd $src, $mem\t# ptr, #@storeP" %}
5176
5177 ins_encode %{
5178 __ sd(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5179 %}
5180
5181 ins_pipe(istore_reg_mem);
5182 %}
5183
5184 // Store Pointer
5185 instruct storeimmP0(immP0 zero, memory mem)
5186 %{
5187 match(Set mem (StoreP mem zero));
5188 predicate(n->as_Store()->barrier_data() == 0);
5189
5190 ins_cost(STORE_COST);
5191 format %{ "sd zr, $mem\t# ptr, #@storeimmP0" %}
5192
5193 ins_encode %{
5194 __ sd(zr, Address(as_Register($mem$$base), $mem$$disp));
5195 %}
5196
5197 ins_pipe(istore_mem);
5198 %}
5199
5200 // Store Compressed Pointer
5201 instruct storeN(iRegN src, memory mem)
5202 %{
5203 match(Set mem (StoreN mem src));
5204
5205 ins_cost(STORE_COST);
5206 format %{ "sw $src, $mem\t# compressed ptr, #@storeN" %}
5207
5208 ins_encode %{
5209 __ sw(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5210 %}
5211
5212 ins_pipe(istore_reg_mem);
5213 %}
5214
5215 instruct storeImmN0(iRegIHeapbase heapbase, immN0 zero, memory mem)
5216 %{
5217 match(Set mem (StoreN mem zero));
5218
5219 ins_cost(STORE_COST);
5220 format %{ "sw rheapbase, $mem\t# compressed ptr (rheapbase==0), #@storeImmN0" %}
5221
5222 ins_encode %{
5223 __ sw(as_Register($heapbase$$reg), Address(as_Register($mem$$base), $mem$$disp));
5224 %}
5225
5226 ins_pipe(istore_reg_mem);
5227 %}
5228
5229 // Store Float
5230 instruct storeF(fRegF src, memory mem)
5231 %{
5232 match(Set mem (StoreF mem src));
5233
5234 ins_cost(STORE_COST);
5235 format %{ "fsw $src, $mem\t# float, #@storeF" %}
5236
5237 ins_encode %{
5238 __ fsw(as_FloatRegister($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5239 %}
5240
5241 ins_pipe(fp_store_reg_s);
5242 %}
5243
5244 // Store Double
5245 instruct storeD(fRegD src, memory mem)
5246 %{
5247 match(Set mem (StoreD mem src));
5248
5249 ins_cost(STORE_COST);
5250 format %{ "fsd $src, $mem\t# double, #@storeD" %}
5251
5252 ins_encode %{
5253 __ fsd(as_FloatRegister($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5254 %}
5255
5256 ins_pipe(fp_store_reg_d);
5257 %}
5258
5259 // Store Compressed Klass Pointer
5260 instruct storeNKlass(iRegN src, memory mem)
5261 %{
5262 match(Set mem (StoreNKlass mem src));
5263
5264 ins_cost(STORE_COST);
5265 format %{ "sw $src, $mem\t# compressed klass ptr, #@storeNKlass" %}
5266
5267 ins_encode %{
5268 __ sw(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5269 %}
5270
5271 ins_pipe(istore_reg_mem);
5272 %}
5273
5274 // ============================================================================
5275 // Prefetch instructions
5276 // Must be safe to execute with invalid address (cannot fault).
5277
5278 instruct prefetchalloc( memory mem ) %{
5279 predicate(UseZicbop);
5280 match(PrefetchAllocation mem);
5281
5282 ins_cost(ALU_COST * 1);
5283 format %{ "prefetch_w $mem\t# Prefetch for write" %}
5284
5285 ins_encode %{
5286 if (is_imm_in_range($mem$$disp, 12, 0)) {
5287 if (($mem$$disp & 0x1f) == 0) {
5288 __ prefetch_w(as_Register($mem$$base), $mem$$disp);
5289 } else {
5290 __ addi(t0, as_Register($mem$$base), $mem$$disp);
5291 __ prefetch_w(t0, 0);
5292 }
5293 } else {
5294 __ mv(t0, $mem$$disp);
5295 __ add(t0, as_Register($mem$$base), t0);
5296 __ prefetch_w(t0, 0);
5297 }
5298 %}
5299
5300 ins_pipe(iload_prefetch);
5301 %}
5302
5303 // ============================================================================
5304 // Atomic operation instructions
5305 //
5306
5307 // standard CompareAndSwapX when we are using barriers
5308 // these have higher priority than the rules selected by a predicate
5309 instruct compareAndSwapB(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5310 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5311 %{
5312 match(Set res (CompareAndSwapB mem (Binary oldval newval)));
5313
5314 ins_cost(LOAD_COST + STORE_COST + ALU_COST * 10 + BRANCH_COST * 4);
5315
5316 effect(TEMP_DEF res, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3, KILL cr);
5317
5318 format %{
5319 "cmpxchg $mem, $oldval, $newval\t# (byte) if $mem == $oldval then $mem <-- $newval\n\t"
5320 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapB"
5321 %}
5322
5323 ins_encode %{
5324 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5325 Assembler::relaxed /* acquire */, Assembler::rl /* release */, $res$$Register,
5326 true /* result as bool */, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5327 %}
5328
5329 ins_pipe(pipe_slow);
5330 %}
5331
5332 instruct compareAndSwapS(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5333 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5334 %{
5335 match(Set res (CompareAndSwapS mem (Binary oldval newval)));
5336
5337 ins_cost(LOAD_COST + STORE_COST + ALU_COST * 11 + BRANCH_COST * 4);
5338
5339 effect(TEMP_DEF res, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3, KILL cr);
5340
5341 format %{
5342 "cmpxchg $mem, $oldval, $newval\t# (short) if $mem == $oldval then $mem <-- $newval\n\t"
5343 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapS"
5344 %}
5345
5346 ins_encode %{
5347 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5348 Assembler::relaxed /* acquire */, Assembler::rl /* release */, $res$$Register,
5349 true /* result as bool */, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5350 %}
5351
5352 ins_pipe(pipe_slow);
5353 %}
5354
5355 instruct compareAndSwapI(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5356 %{
5357 match(Set res (CompareAndSwapI mem (Binary oldval newval)));
5358
5359 ins_cost(LOAD_COST + STORE_COST + ALU_COST * 6 + BRANCH_COST * 4);
5360
5361 format %{
5362 "cmpxchg $mem, $oldval, $newval\t# (int) if $mem == $oldval then $mem <-- $newval\n\t"
5363 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapI"
5364 %}
5365
5366 ins_encode(riscv_enc_cmpxchgw(res, mem, oldval, newval));
5367
5368 ins_pipe(pipe_slow);
5369 %}
5370
5371 instruct compareAndSwapL(iRegINoSp res, indirect mem, iRegL oldval, iRegL newval)
5372 %{
5373 match(Set res (CompareAndSwapL mem (Binary oldval newval)));
5374
5375 ins_cost(LOAD_COST + STORE_COST + ALU_COST * 6 + BRANCH_COST * 4);
5376
5377 format %{
5378 "cmpxchg $mem, $oldval, $newval\t# (long) if $mem == $oldval then $mem <-- $newval\n\t"
5379 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapL"
5380 %}
5381
5382 ins_encode(riscv_enc_cmpxchg(res, mem, oldval, newval));
5383
5384 ins_pipe(pipe_slow);
5385 %}
5386
5387 instruct compareAndSwapP(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval)
5388 %{
5389 predicate(n->as_LoadStore()->barrier_data() == 0);
5390
5391 match(Set res (CompareAndSwapP mem (Binary oldval newval)));
5392
5393 ins_cost(LOAD_COST + STORE_COST + ALU_COST * 6 + BRANCH_COST * 4);
5394
5395 format %{
5396 "cmpxchg $mem, $oldval, $newval\t# (ptr) if $mem == $oldval then $mem <-- $newval\n\t"
5397 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapP"
5398 %}
5399
5400 ins_encode(riscv_enc_cmpxchg(res, mem, oldval, newval));
5401
5402 ins_pipe(pipe_slow);
5403 %}
5404
5405 instruct compareAndSwapN(iRegINoSp res, indirect mem, iRegN oldval, iRegN newval)
5406 %{
5407 match(Set res (CompareAndSwapN mem (Binary oldval newval)));
5408
5409 ins_cost(LOAD_COST + STORE_COST + ALU_COST * 8 + BRANCH_COST * 4);
5410
5411 format %{
5412 "cmpxchg $mem, $oldval, $newval\t# (narrow oop) if $mem == $oldval then $mem <-- $newval\n\t"
5413 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapN"
5414 %}
5415
5416 ins_encode(riscv_enc_cmpxchgn(res, mem, oldval, newval));
5417
5418 ins_pipe(pipe_slow);
5419 %}
5420
5421 // alternative CompareAndSwapX when we are eliding barriers
5422 instruct compareAndSwapBAcq(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5423 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5424 %{
5425 predicate(needs_acquiring_load_reserved(n));
5426
5427 match(Set res (CompareAndSwapB mem (Binary oldval newval)));
5428
5429 ins_cost(LOAD_COST + STORE_COST + ALU_COST * 10 + BRANCH_COST * 4);
5430
5431 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5432
5433 format %{
5434 "cmpxchg_acq $mem, $oldval, $newval\t# (byte) if $mem == $oldval then $mem <-- $newval\n\t"
5435 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapBAcq"
5436 %}
5437
5438 ins_encode %{
5439 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5440 Assembler::aq /* acquire */, Assembler::rl /* release */, $res$$Register,
5441 true /* result as bool */, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5442 %}
5443
5444 ins_pipe(pipe_slow);
5445 %}
5446
5447 instruct compareAndSwapSAcq(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5448 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5449 %{
5450 predicate(needs_acquiring_load_reserved(n));
5451
5452 match(Set res (CompareAndSwapS mem (Binary oldval newval)));
5453
5454 ins_cost(LOAD_COST + STORE_COST + ALU_COST * 11 + BRANCH_COST * 4);
5455
5456 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5457
5458 format %{
5459 "cmpxchg_acq $mem, $oldval, $newval\t# (short) if $mem == $oldval then $mem <-- $newval\n\t"
5460 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapSAcq"
5461 %}
5462
5463 ins_encode %{
5464 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5465 Assembler::aq /* acquire */, Assembler::rl /* release */, $res$$Register,
5466 true /* result as bool */, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5467 %}
5468
5469 ins_pipe(pipe_slow);
5470 %}
5471
5472 instruct compareAndSwapIAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5473 %{
5474 predicate(needs_acquiring_load_reserved(n));
5475
5476 match(Set res (CompareAndSwapI mem (Binary oldval newval)));
5477
5478 ins_cost(LOAD_COST + STORE_COST + ALU_COST * 6 + BRANCH_COST * 4);
5479
5480 format %{
5481 "cmpxchg_acq $mem, $oldval, $newval\t# (int) if $mem == $oldval then $mem <-- $newval\n\t"
5482 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapIAcq"
5483 %}
5484
5485 ins_encode(riscv_enc_cmpxchgw_acq(res, mem, oldval, newval));
5486
5487 ins_pipe(pipe_slow);
5488 %}
5489
5490 instruct compareAndSwapLAcq(iRegINoSp res, indirect mem, iRegL oldval, iRegL newval)
5491 %{
5492 predicate(needs_acquiring_load_reserved(n));
5493
5494 match(Set res (CompareAndSwapL mem (Binary oldval newval)));
5495
5496 ins_cost(LOAD_COST + STORE_COST + ALU_COST * 6 + BRANCH_COST * 4);
5497
5498 format %{
5499 "cmpxchg_acq $mem, $oldval, $newval\t# (long) if $mem == $oldval then $mem <-- $newval\n\t"
5500 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapLAcq"
5501 %}
5502
5503 ins_encode(riscv_enc_cmpxchg_acq(res, mem, oldval, newval));
5504
5505 ins_pipe(pipe_slow);
5506 %}
5507
5508 instruct compareAndSwapPAcq(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval)
5509 %{
5510 predicate(needs_acquiring_load_reserved(n) && (n->as_LoadStore()->barrier_data() == 0));
5511
5512 match(Set res (CompareAndSwapP mem (Binary oldval newval)));
5513
5514 ins_cost(LOAD_COST + STORE_COST + ALU_COST * 6 + BRANCH_COST * 4);
5515
5516 format %{
5517 "cmpxchg_acq $mem, $oldval, $newval\t# (ptr) if $mem == $oldval then $mem <-- $newval\n\t"
5518 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapPAcq"
5519 %}
5520
5521 ins_encode(riscv_enc_cmpxchg_acq(res, mem, oldval, newval));
5522
5523 ins_pipe(pipe_slow);
5524 %}
5525
5526 instruct compareAndSwapNAcq(iRegINoSp res, indirect mem, iRegN oldval, iRegN newval)
5527 %{
5528 predicate(needs_acquiring_load_reserved(n));
5529
5530 match(Set res (CompareAndSwapN mem (Binary oldval newval)));
5531
5532 ins_cost(LOAD_COST + STORE_COST + ALU_COST * 8 + BRANCH_COST * 4);
5533
5534 format %{
5535 "cmpxchg_acq $mem, $oldval, $newval\t# (narrow oop) if $mem == $oldval then $mem <-- $newval\n\t"
5536 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapNAcq"
5537 %}
5538
5539 ins_encode(riscv_enc_cmpxchgn_acq(res, mem, oldval, newval));
5540
5541 ins_pipe(pipe_slow);
5542 %}
5543
5544 // Sundry CAS operations. Note that release is always true,
5545 // regardless of the memory ordering of the CAS. This is because we
5546 // need the volatile case to be sequentially consistent but there is
5547 // no trailing StoreLoad barrier emitted by C2. Unfortunately we
5548 // can't check the type of memory ordering here, so we always emit a
5549 // sc_d(w) with rl bit set.
5550 instruct compareAndExchangeB(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5551 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5552 %{
5553 match(Set res (CompareAndExchangeB mem (Binary oldval newval)));
5554
5555 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST * 5);
5556
5557 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5558
5559 format %{
5560 "cmpxchg $res = $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeB"
5561 %}
5562
5563 ins_encode %{
5564 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5565 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
5566 /*result_as_bool*/ false, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5567 %}
5568
5569 ins_pipe(pipe_slow);
5570 %}
5571
5572 instruct compareAndExchangeS(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5573 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5574 %{
5575 match(Set res (CompareAndExchangeS mem (Binary oldval newval)));
5576
5577 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST * 6);
5578
5579 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5580
5581 format %{
5582 "cmpxchg $res = $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeS"
5583 %}
5584
5585 ins_encode %{
5586 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5587 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
5588 /*result_as_bool*/ false, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5589 %}
5590
5591 ins_pipe(pipe_slow);
5592 %}
5593
5594 instruct compareAndExchangeI(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5595 %{
5596 match(Set res (CompareAndExchangeI mem (Binary oldval newval)));
5597
5598 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST);
5599
5600 effect(TEMP_DEF res);
5601
5602 format %{
5603 "cmpxchg $res = $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeI"
5604 %}
5605
5606 ins_encode %{
5607 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
5608 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5609 %}
5610
5611 ins_pipe(pipe_slow);
5612 %}
5613
5614 instruct compareAndExchangeL(iRegLNoSp res, indirect mem, iRegL oldval, iRegL newval)
5615 %{
5616 match(Set res (CompareAndExchangeL mem (Binary oldval newval)));
5617
5618 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST);
5619
5620 effect(TEMP_DEF res);
5621
5622 format %{
5623 "cmpxchg $res = $mem, $oldval, $newval\t# (long, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeL"
5624 %}
5625
5626 ins_encode %{
5627 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5628 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5629 %}
5630
5631 ins_pipe(pipe_slow);
5632 %}
5633
5634 instruct compareAndExchangeN(iRegNNoSp res, indirect mem, iRegN oldval, iRegN newval)
5635 %{
5636 match(Set res (CompareAndExchangeN mem (Binary oldval newval)));
5637
5638 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST * 3);
5639
5640 effect(TEMP_DEF res);
5641
5642 format %{
5643 "cmpxchg $res = $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeN"
5644 %}
5645
5646 ins_encode %{
5647 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
5648 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5649 %}
5650
5651 ins_pipe(pipe_slow);
5652 %}
5653
5654 instruct compareAndExchangeP(iRegPNoSp res, indirect mem, iRegP oldval, iRegP newval)
5655 %{
5656 predicate(n->as_LoadStore()->barrier_data() == 0);
5657 match(Set res (CompareAndExchangeP mem (Binary oldval newval)));
5658
5659 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST);
5660
5661 effect(TEMP_DEF res);
5662
5663 format %{
5664 "cmpxchg $res = $mem, $oldval, $newval\t# (ptr, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeP"
5665 %}
5666
5667 ins_encode %{
5668 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5669 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5670 %}
5671
5672 ins_pipe(pipe_slow);
5673 %}
5674
5675 instruct compareAndExchangeBAcq(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5676 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5677 %{
5678 predicate(needs_acquiring_load_reserved(n));
5679
5680 match(Set res (CompareAndExchangeB mem (Binary oldval newval)));
5681
5682 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST * 5);
5683
5684 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5685
5686 format %{
5687 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeBAcq"
5688 %}
5689
5690 ins_encode %{
5691 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5692 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
5693 /*result_as_bool*/ false, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5694 %}
5695
5696 ins_pipe(pipe_slow);
5697 %}
5698
5699 instruct compareAndExchangeSAcq(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5700 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5701 %{
5702 predicate(needs_acquiring_load_reserved(n));
5703
5704 match(Set res (CompareAndExchangeS mem (Binary oldval newval)));
5705
5706 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST * 6);
5707
5708 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5709
5710 format %{
5711 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeSAcq"
5712 %}
5713
5714 ins_encode %{
5715 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5716 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
5717 /*result_as_bool*/ false, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5718 %}
5719
5720 ins_pipe(pipe_slow);
5721 %}
5722
5723 instruct compareAndExchangeIAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5724 %{
5725 predicate(needs_acquiring_load_reserved(n));
5726
5727 match(Set res (CompareAndExchangeI mem (Binary oldval newval)));
5728
5729 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST);
5730
5731 effect(TEMP_DEF res);
5732
5733 format %{
5734 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeIAcq"
5735 %}
5736
5737 ins_encode %{
5738 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
5739 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
5740 %}
5741
5742 ins_pipe(pipe_slow);
5743 %}
5744
5745 instruct compareAndExchangeLAcq(iRegLNoSp res, indirect mem, iRegL oldval, iRegL newval)
5746 %{
5747 predicate(needs_acquiring_load_reserved(n));
5748
5749 match(Set res (CompareAndExchangeL mem (Binary oldval newval)));
5750
5751 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST);
5752
5753 effect(TEMP_DEF res);
5754
5755 format %{
5756 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (long, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeLAcq"
5757 %}
5758
5759 ins_encode %{
5760 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5761 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
5762 %}
5763
5764 ins_pipe(pipe_slow);
5765 %}
5766
5767 instruct compareAndExchangeNAcq(iRegNNoSp res, indirect mem, iRegN oldval, iRegN newval)
5768 %{
5769 predicate(needs_acquiring_load_reserved(n));
5770
5771 match(Set res (CompareAndExchangeN mem (Binary oldval newval)));
5772
5773 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST);
5774
5775 effect(TEMP_DEF res);
5776
5777 format %{
5778 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeNAcq"
5779 %}
5780
5781 ins_encode %{
5782 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
5783 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
5784 %}
5785
5786 ins_pipe(pipe_slow);
5787 %}
5788
5789 instruct compareAndExchangePAcq(iRegPNoSp res, indirect mem, iRegP oldval, iRegP newval)
5790 %{
5791 predicate(needs_acquiring_load_reserved(n) && (n->as_LoadStore()->barrier_data() == 0));
5792
5793 match(Set res (CompareAndExchangeP mem (Binary oldval newval)));
5794
5795 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST);
5796
5797 effect(TEMP_DEF res);
5798
5799 format %{
5800 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (ptr, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangePAcq"
5801 %}
5802
5803 ins_encode %{
5804 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5805 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
5806 %}
5807
5808 ins_pipe(pipe_slow);
5809 %}
5810
5811 instruct weakCompareAndSwapB(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5812 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5813 %{
5814 match(Set res (WeakCompareAndSwapB mem (Binary oldval newval)));
5815
5816 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 6);
5817
5818 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5819
5820 format %{
5821 "cmpxchg_weak $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5822 "# $res == 1 when success, #@weakCompareAndSwapB"
5823 %}
5824
5825 ins_encode %{
5826 __ weak_cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5827 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
5828 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5829 %}
5830
5831 ins_pipe(pipe_slow);
5832 %}
5833
5834 instruct weakCompareAndSwapS(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5835 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5836 %{
5837 match(Set res (WeakCompareAndSwapS mem (Binary oldval newval)));
5838
5839 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 7);
5840
5841 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5842
5843 format %{
5844 "cmpxchg_weak $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5845 "# $res == 1 when success, #@weakCompareAndSwapS"
5846 %}
5847
5848 ins_encode %{
5849 __ weak_cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5850 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
5851 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5852 %}
5853
5854 ins_pipe(pipe_slow);
5855 %}
5856
5857 instruct weakCompareAndSwapI(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5858 %{
5859 match(Set res (WeakCompareAndSwapI mem (Binary oldval newval)));
5860
5861 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 2);
5862
5863 format %{
5864 "cmpxchg_weak $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5865 "# $res == 1 when success, #@weakCompareAndSwapI"
5866 %}
5867
5868 ins_encode %{
5869 __ cmpxchg_weak(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
5870 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5871 %}
5872
5873 ins_pipe(pipe_slow);
5874 %}
5875
5876 instruct weakCompareAndSwapL(iRegINoSp res, indirect mem, iRegL oldval, iRegL newval)
5877 %{
5878 match(Set res (WeakCompareAndSwapL mem (Binary oldval newval)));
5879
5880 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 2);
5881
5882 format %{
5883 "cmpxchg_weak $mem, $oldval, $newval\t# (long, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5884 "# $res == 1 when success, #@weakCompareAndSwapL"
5885 %}
5886
5887 ins_encode %{
5888 __ cmpxchg_weak(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5889 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5890 %}
5891
5892 ins_pipe(pipe_slow);
5893 %}
5894
5895 instruct weakCompareAndSwapN(iRegINoSp res, indirect mem, iRegN oldval, iRegN newval)
5896 %{
5897 match(Set res (WeakCompareAndSwapN mem (Binary oldval newval)));
5898
5899 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 4);
5900
5901 format %{
5902 "cmpxchg_weak $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5903 "# $res == 1 when success, #@weakCompareAndSwapN"
5904 %}
5905
5906 ins_encode %{
5907 __ cmpxchg_weak(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
5908 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5909 %}
5910
5911 ins_pipe(pipe_slow);
5912 %}
5913
5914 instruct weakCompareAndSwapP(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval)
5915 %{
5916 predicate(n->as_LoadStore()->barrier_data() == 0);
5917 match(Set res (WeakCompareAndSwapP mem (Binary oldval newval)));
5918
5919 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 2);
5920
5921 format %{
5922 "cmpxchg_weak $mem, $oldval, $newval\t# (ptr, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5923 "# $res == 1 when success, #@weakCompareAndSwapP"
5924 %}
5925
5926 ins_encode %{
5927 __ cmpxchg_weak(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5928 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5929 %}
5930
5931 ins_pipe(pipe_slow);
5932 %}
5933
5934 instruct weakCompareAndSwapBAcq(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5935 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5936 %{
5937 predicate(needs_acquiring_load_reserved(n));
5938
5939 match(Set res (WeakCompareAndSwapB mem (Binary oldval newval)));
5940
5941 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 6);
5942
5943 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5944
5945 format %{
5946 "cmpxchg_weak_acq $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5947 "# $res == 1 when success, #@weakCompareAndSwapBAcq"
5948 %}
5949
5950 ins_encode %{
5951 __ weak_cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5952 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
5953 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5954 %}
5955
5956 ins_pipe(pipe_slow);
5957 %}
5958
5959 instruct weakCompareAndSwapSAcq(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5960 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5961 %{
5962 predicate(needs_acquiring_load_reserved(n));
5963
5964 match(Set res (WeakCompareAndSwapS mem (Binary oldval newval)));
5965
5966 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 7);
5967
5968 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5969
5970 format %{
5971 "cmpxchg_weak_acq $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5972 "# $res == 1 when success, #@weakCompareAndSwapSAcq"
5973 %}
5974
5975 ins_encode %{
5976 __ weak_cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5977 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
5978 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5979 %}
5980
5981 ins_pipe(pipe_slow);
5982 %}
5983
5984 instruct weakCompareAndSwapIAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5985 %{
5986 predicate(needs_acquiring_load_reserved(n));
5987
5988 match(Set res (WeakCompareAndSwapI mem (Binary oldval newval)));
5989
5990 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 2);
5991
5992 format %{
5993 "cmpxchg_weak_acq $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5994 "# $res == 1 when success, #@weakCompareAndSwapIAcq"
5995 %}
5996
5997 ins_encode %{
5998 __ cmpxchg_weak(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
5999 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
6000 %}
6001
6002 ins_pipe(pipe_slow);
6003 %}
6004
6005 instruct weakCompareAndSwapLAcq(iRegINoSp res, indirect mem, iRegL oldval, iRegL newval)
6006 %{
6007 predicate(needs_acquiring_load_reserved(n));
6008
6009 match(Set res (WeakCompareAndSwapL mem (Binary oldval newval)));
6010
6011 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 2);
6012
6013 format %{
6014 "cmpxchg_weak_acq $mem, $oldval, $newval\t# (long, weak) if $mem == $oldval then $mem <-- $newval\n\t"
6015 "# $res == 1 when success, #@weakCompareAndSwapLAcq"
6016 %}
6017
6018 ins_encode %{
6019 __ cmpxchg_weak(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
6020 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
6021 %}
6022
6023 ins_pipe(pipe_slow);
6024 %}
6025
6026 instruct weakCompareAndSwapNAcq(iRegINoSp res, indirect mem, iRegN oldval, iRegN newval)
6027 %{
6028 predicate(needs_acquiring_load_reserved(n));
6029
6030 match(Set res (WeakCompareAndSwapN mem (Binary oldval newval)));
6031
6032 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 4);
6033
6034 format %{
6035 "cmpxchg_weak_acq $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval\n\t"
6036 "# $res == 1 when success, #@weakCompareAndSwapNAcq"
6037 %}
6038
6039 ins_encode %{
6040 __ cmpxchg_weak(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
6041 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
6042 %}
6043
6044 ins_pipe(pipe_slow);
6045 %}
6046
6047 instruct weakCompareAndSwapPAcq(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval)
6048 %{
6049 predicate(needs_acquiring_load_reserved(n) && (n->as_LoadStore()->barrier_data() == 0));
6050
6051 match(Set res (WeakCompareAndSwapP mem (Binary oldval newval)));
6052
6053 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 2);
6054
6055 format %{
6056 "cmpxchg_weak_acq $mem, $oldval, $newval\t# (ptr, weak) if $mem == $oldval then $mem <-- $newval\n\t"
6057 "\t# $res == 1 when success, #@weakCompareAndSwapPAcq"
6058 %}
6059
6060 ins_encode %{
6061 __ cmpxchg_weak(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
6062 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
6063 %}
6064
6065 ins_pipe(pipe_slow);
6066 %}
6067
6068 instruct get_and_setI(indirect mem, iRegI newv, iRegINoSp prev)
6069 %{
6070 match(Set prev (GetAndSetI mem newv));
6071
6072 ins_cost(ALU_COST);
6073
6074 format %{ "atomic_xchgw $prev, $newv, [$mem]\t#@get_and_setI" %}
6075
6076 ins_encode %{
6077 __ atomic_xchgw($prev$$Register, $newv$$Register, as_Register($mem$$base));
6078 %}
6079
6080 ins_pipe(pipe_serial);
6081 %}
6082
6083 instruct get_and_setL(indirect mem, iRegL newv, iRegLNoSp prev)
6084 %{
6085 match(Set prev (GetAndSetL mem newv));
6086
6087 ins_cost(ALU_COST);
6088
6089 format %{ "atomic_xchg $prev, $newv, [$mem]\t#@get_and_setL" %}
6090
6091 ins_encode %{
6092 __ atomic_xchg($prev$$Register, $newv$$Register, as_Register($mem$$base));
6093 %}
6094
6095 ins_pipe(pipe_serial);
6096 %}
6097
6098 instruct get_and_setN(indirect mem, iRegN newv, iRegINoSp prev)
6099 %{
6100 match(Set prev (GetAndSetN mem newv));
6101
6102 ins_cost(ALU_COST);
6103
6104 format %{ "atomic_xchgwu $prev, $newv, [$mem]\t#@get_and_setN" %}
6105
6106 ins_encode %{
6107 __ atomic_xchgwu($prev$$Register, $newv$$Register, as_Register($mem$$base));
6108 %}
6109
6110 ins_pipe(pipe_serial);
6111 %}
6112
6113 instruct get_and_setP(indirect mem, iRegP newv, iRegPNoSp prev)
6114 %{
6115 predicate(n->as_LoadStore()->barrier_data() == 0);
6116 match(Set prev (GetAndSetP mem newv));
6117
6118 ins_cost(ALU_COST);
6119
6120 format %{ "atomic_xchg $prev, $newv, [$mem]\t#@get_and_setP" %}
6121
6122 ins_encode %{
6123 __ atomic_xchg($prev$$Register, $newv$$Register, as_Register($mem$$base));
6124 %}
6125
6126 ins_pipe(pipe_serial);
6127 %}
6128
6129 instruct get_and_setIAcq(indirect mem, iRegI newv, iRegINoSp prev)
6130 %{
6131 predicate(needs_acquiring_load_reserved(n));
6132
6133 match(Set prev (GetAndSetI mem newv));
6134
6135 ins_cost(ALU_COST);
6136
6137 format %{ "atomic_xchgw_acq $prev, $newv, [$mem]\t#@get_and_setIAcq" %}
6138
6139 ins_encode %{
6140 __ atomic_xchgalw($prev$$Register, $newv$$Register, as_Register($mem$$base));
6141 %}
6142
6143 ins_pipe(pipe_serial);
6144 %}
6145
6146 instruct get_and_setLAcq(indirect mem, iRegL newv, iRegLNoSp prev)
6147 %{
6148 predicate(needs_acquiring_load_reserved(n));
6149
6150 match(Set prev (GetAndSetL mem newv));
6151
6152 ins_cost(ALU_COST);
6153
6154 format %{ "atomic_xchg_acq $prev, $newv, [$mem]\t#@get_and_setLAcq" %}
6155
6156 ins_encode %{
6157 __ atomic_xchgal($prev$$Register, $newv$$Register, as_Register($mem$$base));
6158 %}
6159
6160 ins_pipe(pipe_serial);
6161 %}
6162
6163 instruct get_and_setNAcq(indirect mem, iRegN newv, iRegINoSp prev)
6164 %{
6165 predicate(needs_acquiring_load_reserved(n));
6166
6167 match(Set prev (GetAndSetN mem newv));
6168
6169 ins_cost(ALU_COST);
6170
6171 format %{ "atomic_xchgwu_acq $prev, $newv, [$mem]\t#@get_and_setNAcq" %}
6172
6173 ins_encode %{
6174 __ atomic_xchgalwu($prev$$Register, $newv$$Register, as_Register($mem$$base));
6175 %}
6176
6177 ins_pipe(pipe_serial);
6178 %}
6179
6180 instruct get_and_setPAcq(indirect mem, iRegP newv, iRegPNoSp prev)
6181 %{
6182 predicate(needs_acquiring_load_reserved(n) && (n->as_LoadStore()->barrier_data() == 0));
6183
6184 match(Set prev (GetAndSetP mem newv));
6185
6186 ins_cost(ALU_COST);
6187
6188 format %{ "atomic_xchg_acq $prev, $newv, [$mem]\t#@get_and_setPAcq" %}
6189
6190 ins_encode %{
6191 __ atomic_xchgal($prev$$Register, $newv$$Register, as_Register($mem$$base));
6192 %}
6193
6194 ins_pipe(pipe_serial);
6195 %}
6196
6197 instruct get_and_addL(indirect mem, iRegLNoSp newval, iRegL incr)
6198 %{
6199 match(Set newval (GetAndAddL mem incr));
6200
6201 ins_cost(ALU_COST);
6202
6203 format %{ "get_and_addL $newval, [$mem], $incr\t#@get_and_addL" %}
6204
6205 ins_encode %{
6206 __ atomic_add($newval$$Register, $incr$$Register, as_Register($mem$$base));
6207 %}
6208
6209 ins_pipe(pipe_serial);
6210 %}
6211
6212 instruct get_and_addL_no_res(indirect mem, Universe dummy, iRegL incr)
6213 %{
6214 predicate(n->as_LoadStore()->result_not_used());
6215
6216 match(Set dummy (GetAndAddL mem incr));
6217
6218 ins_cost(ALU_COST);
6219
6220 format %{ "get_and_addL [$mem], $incr\t#@get_and_addL_no_res" %}
6221
6222 ins_encode %{
6223 __ atomic_add(noreg, $incr$$Register, as_Register($mem$$base));
6224 %}
6225
6226 ins_pipe(pipe_serial);
6227 %}
6228
6229 instruct get_and_addLi(indirect mem, iRegLNoSp newval, immLAdd incr)
6230 %{
6231 match(Set newval (GetAndAddL mem incr));
6232
6233 ins_cost(ALU_COST);
6234
6235 format %{ "get_and_addL $newval, [$mem], $incr\t#@get_and_addLi" %}
6236
6237 ins_encode %{
6238 __ atomic_add($newval$$Register, $incr$$constant, as_Register($mem$$base));
6239 %}
6240
6241 ins_pipe(pipe_serial);
6242 %}
6243
6244 instruct get_and_addLi_no_res(indirect mem, Universe dummy, immLAdd incr)
6245 %{
6246 predicate(n->as_LoadStore()->result_not_used());
6247
6248 match(Set dummy (GetAndAddL mem incr));
6249
6250 ins_cost(ALU_COST);
6251
6252 format %{ "get_and_addL [$mem], $incr\t#@get_and_addLi_no_res" %}
6253
6254 ins_encode %{
6255 __ atomic_add(noreg, $incr$$constant, as_Register($mem$$base));
6256 %}
6257
6258 ins_pipe(pipe_serial);
6259 %}
6260
6261 instruct get_and_addI(indirect mem, iRegINoSp newval, iRegIorL2I incr)
6262 %{
6263 match(Set newval (GetAndAddI mem incr));
6264
6265 ins_cost(ALU_COST);
6266
6267 format %{ "get_and_addI $newval, [$mem], $incr\t#@get_and_addI" %}
6268
6269 ins_encode %{
6270 __ atomic_addw($newval$$Register, $incr$$Register, as_Register($mem$$base));
6271 %}
6272
6273 ins_pipe(pipe_serial);
6274 %}
6275
6276 instruct get_and_addI_no_res(indirect mem, Universe dummy, iRegIorL2I incr)
6277 %{
6278 predicate(n->as_LoadStore()->result_not_used());
6279
6280 match(Set dummy (GetAndAddI mem incr));
6281
6282 ins_cost(ALU_COST);
6283
6284 format %{ "get_and_addI [$mem], $incr\t#@get_and_addI_no_res" %}
6285
6286 ins_encode %{
6287 __ atomic_addw(noreg, $incr$$Register, as_Register($mem$$base));
6288 %}
6289
6290 ins_pipe(pipe_serial);
6291 %}
6292
6293 instruct get_and_addIi(indirect mem, iRegINoSp newval, immIAdd incr)
6294 %{
6295 match(Set newval (GetAndAddI mem incr));
6296
6297 ins_cost(ALU_COST);
6298
6299 format %{ "get_and_addI $newval, [$mem], $incr\t#@get_and_addIi" %}
6300
6301 ins_encode %{
6302 __ atomic_addw($newval$$Register, $incr$$constant, as_Register($mem$$base));
6303 %}
6304
6305 ins_pipe(pipe_serial);
6306 %}
6307
6308 instruct get_and_addIi_no_res(indirect mem, Universe dummy, immIAdd incr)
6309 %{
6310 predicate(n->as_LoadStore()->result_not_used());
6311
6312 match(Set dummy (GetAndAddI mem incr));
6313
6314 ins_cost(ALU_COST);
6315
6316 format %{ "get_and_addI [$mem], $incr\t#@get_and_addIi_no_res" %}
6317
6318 ins_encode %{
6319 __ atomic_addw(noreg, $incr$$constant, as_Register($mem$$base));
6320 %}
6321
6322 ins_pipe(pipe_serial);
6323 %}
6324
6325 instruct get_and_addLAcq(indirect mem, iRegLNoSp newval, iRegL incr)
6326 %{
6327 predicate(needs_acquiring_load_reserved(n));
6328
6329 match(Set newval (GetAndAddL mem incr));
6330
6331 ins_cost(ALU_COST);
6332
6333 format %{ "get_and_addL_acq $newval, [$mem], $incr\t#@get_and_addLAcq" %}
6334
6335 ins_encode %{
6336 __ atomic_addal($newval$$Register, $incr$$Register, as_Register($mem$$base));
6337 %}
6338
6339 ins_pipe(pipe_serial);
6340 %}
6341
6342 instruct get_and_addL_no_resAcq(indirect mem, Universe dummy, iRegL incr) %{
6343 predicate(n->as_LoadStore()->result_not_used() && needs_acquiring_load_reserved(n));
6344
6345 match(Set dummy (GetAndAddL mem incr));
6346
6347 ins_cost(ALU_COST);
6348
6349 format %{ "get_and_addL_acq [$mem], $incr\t#@get_and_addL_no_resAcq" %}
6350
6351 ins_encode %{
6352 __ atomic_addal(noreg, $incr$$Register, as_Register($mem$$base));
6353 %}
6354
6355 ins_pipe(pipe_serial);
6356 %}
6357
6358 instruct get_and_addLiAcq(indirect mem, iRegLNoSp newval, immLAdd incr)
6359 %{
6360 predicate(needs_acquiring_load_reserved(n));
6361
6362 match(Set newval (GetAndAddL mem incr));
6363
6364 ins_cost(ALU_COST);
6365
6366 format %{ "get_and_addL_acq $newval, [$mem], $incr\t#@get_and_addLiAcq" %}
6367
6368 ins_encode %{
6369 __ atomic_addal($newval$$Register, $incr$$constant, as_Register($mem$$base));
6370 %}
6371
6372 ins_pipe(pipe_serial);
6373 %}
6374
6375 instruct get_and_addLi_no_resAcq(indirect mem, Universe dummy, immLAdd incr)
6376 %{
6377 predicate(n->as_LoadStore()->result_not_used() && needs_acquiring_load_reserved(n));
6378
6379 match(Set dummy (GetAndAddL mem incr));
6380
6381 ins_cost(ALU_COST);
6382
6383 format %{ "get_and_addL_acq [$mem], $incr\t#@get_and_addLi_no_resAcq" %}
6384
6385 ins_encode %{
6386 __ atomic_addal(noreg, $incr$$constant, as_Register($mem$$base));
6387 %}
6388
6389 ins_pipe(pipe_serial);
6390 %}
6391
6392 instruct get_and_addIAcq(indirect mem, iRegINoSp newval, iRegIorL2I incr)
6393 %{
6394 predicate(needs_acquiring_load_reserved(n));
6395
6396 match(Set newval (GetAndAddI mem incr));
6397
6398 ins_cost(ALU_COST);
6399
6400 format %{ "get_and_addI_acq $newval, [$mem], $incr\t#@get_and_addIAcq" %}
6401
6402 ins_encode %{
6403 __ atomic_addalw($newval$$Register, $incr$$Register, as_Register($mem$$base));
6404 %}
6405
6406 ins_pipe(pipe_serial);
6407 %}
6408
6409 instruct get_and_addI_no_resAcq(indirect mem, Universe dummy, iRegIorL2I incr)
6410 %{
6411 predicate(n->as_LoadStore()->result_not_used() && needs_acquiring_load_reserved(n));
6412
6413 match(Set dummy (GetAndAddI mem incr));
6414
6415 ins_cost(ALU_COST);
6416
6417 format %{ "get_and_addI_acq [$mem], $incr\t#@get_and_addI_no_resAcq" %}
6418
6419 ins_encode %{
6420 __ atomic_addalw(noreg, $incr$$Register, as_Register($mem$$base));
6421 %}
6422
6423 ins_pipe(pipe_serial);
6424 %}
6425
6426 instruct get_and_addIiAcq(indirect mem, iRegINoSp newval, immIAdd incr)
6427 %{
6428 predicate(needs_acquiring_load_reserved(n));
6429
6430 match(Set newval (GetAndAddI mem incr));
6431
6432 ins_cost(ALU_COST);
6433
6434 format %{ "get_and_addI_acq $newval, [$mem], $incr\t#@get_and_addIiAcq" %}
6435
6436 ins_encode %{
6437 __ atomic_addalw($newval$$Register, $incr$$constant, as_Register($mem$$base));
6438 %}
6439
6440 ins_pipe(pipe_serial);
6441 %}
6442
6443 instruct get_and_addIi_no_resAcq(indirect mem, Universe dummy, immIAdd incr)
6444 %{
6445 predicate(n->as_LoadStore()->result_not_used() && needs_acquiring_load_reserved(n));
6446
6447 match(Set dummy (GetAndAddI mem incr));
6448
6449 ins_cost(ALU_COST);
6450
6451 format %{ "get_and_addI_acq [$mem], $incr\t#@get_and_addIi_no_resAcq" %}
6452
6453 ins_encode %{
6454 __ atomic_addalw(noreg, $incr$$constant, as_Register($mem$$base));
6455 %}
6456
6457 ins_pipe(pipe_serial);
6458 %}
6459
6460 // ============================================================================
6461 // Arithmetic Instructions
6462 //
6463
6464 // Integer Addition
6465
6466 // TODO
6467 // these currently employ operations which do not set CR and hence are
6468 // not flagged as killing CR but we would like to isolate the cases
6469 // where we want to set flags from those where we don't. need to work
6470 // out how to do that.
6471 instruct addI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6472 match(Set dst (AddI src1 src2));
6473
6474 ins_cost(ALU_COST);
6475 format %{ "addw $dst, $src1, $src2\t#@addI_reg_reg" %}
6476
6477 ins_encode %{
6478 __ addw(as_Register($dst$$reg),
6479 as_Register($src1$$reg),
6480 as_Register($src2$$reg));
6481 %}
6482
6483 ins_pipe(ialu_reg_reg);
6484 %}
6485
6486 instruct addI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immIAdd src2) %{
6487 match(Set dst (AddI src1 src2));
6488
6489 ins_cost(ALU_COST);
6490 format %{ "addiw $dst, $src1, $src2\t#@addI_reg_imm" %}
6491
6492 ins_encode %{
6493 int32_t con = (int32_t)$src2$$constant;
6494 __ addiw(as_Register($dst$$reg),
6495 as_Register($src1$$reg),
6496 $src2$$constant);
6497 %}
6498
6499 ins_pipe(ialu_reg_imm);
6500 %}
6501
6502 instruct addI_reg_imm_l2i(iRegINoSp dst, iRegL src1, immIAdd src2) %{
6503 match(Set dst (AddI (ConvL2I src1) src2));
6504
6505 ins_cost(ALU_COST);
6506 format %{ "addiw $dst, $src1, $src2\t#@addI_reg_imm_l2i" %}
6507
6508 ins_encode %{
6509 __ addiw(as_Register($dst$$reg),
6510 as_Register($src1$$reg),
6511 $src2$$constant);
6512 %}
6513
6514 ins_pipe(ialu_reg_imm);
6515 %}
6516
6517 // Pointer Addition
6518 instruct addP_reg_reg(iRegPNoSp dst, iRegP src1, iRegL src2) %{
6519 match(Set dst (AddP src1 src2));
6520
6521 ins_cost(ALU_COST);
6522 format %{ "add $dst, $src1, $src2\t# ptr, #@addP_reg_reg" %}
6523
6524 ins_encode %{
6525 __ add(as_Register($dst$$reg),
6526 as_Register($src1$$reg),
6527 as_Register($src2$$reg));
6528 %}
6529
6530 ins_pipe(ialu_reg_reg);
6531 %}
6532
6533 // If we shift more than 32 bits, we need not convert I2L.
6534 instruct lShiftL_regI_immGE32(iRegLNoSp dst, iRegI src, uimmI6_ge32 scale) %{
6535 match(Set dst (LShiftL (ConvI2L src) scale));
6536 ins_cost(ALU_COST);
6537 format %{ "slli $dst, $src, $scale & 63\t#@lShiftL_regI_immGE32" %}
6538
6539 ins_encode %{
6540 __ slli(as_Register($dst$$reg), as_Register($src$$reg), $scale$$constant & 63);
6541 %}
6542
6543 ins_pipe(ialu_reg_shift);
6544 %}
6545
6546 // Pointer Immediate Addition
6547 // n.b. this needs to be more expensive than using an indirect memory
6548 // operand
6549 instruct addP_reg_imm(iRegPNoSp dst, iRegP src1, immLAdd src2) %{
6550 match(Set dst (AddP src1 src2));
6551 ins_cost(ALU_COST);
6552 format %{ "addi $dst, $src1, $src2\t# ptr, #@addP_reg_imm" %}
6553
6554 ins_encode %{
6555 // src2 is imm, so actually call the addi
6556 __ add(as_Register($dst$$reg),
6557 as_Register($src1$$reg),
6558 $src2$$constant);
6559 %}
6560
6561 ins_pipe(ialu_reg_imm);
6562 %}
6563
6564 // Long Addition
6565 instruct addL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
6566 match(Set dst (AddL src1 src2));
6567 ins_cost(ALU_COST);
6568 format %{ "add $dst, $src1, $src2\t#@addL_reg_reg" %}
6569
6570 ins_encode %{
6571 __ add(as_Register($dst$$reg),
6572 as_Register($src1$$reg),
6573 as_Register($src2$$reg));
6574 %}
6575
6576 ins_pipe(ialu_reg_reg);
6577 %}
6578
6579 // No constant pool entries requiredLong Immediate Addition.
6580 instruct addL_reg_imm(iRegLNoSp dst, iRegL src1, immLAdd src2) %{
6581 match(Set dst (AddL src1 src2));
6582 ins_cost(ALU_COST);
6583 format %{ "addi $dst, $src1, $src2\t#@addL_reg_imm" %}
6584
6585 ins_encode %{
6586 // src2 is imm, so actually call the addi
6587 __ add(as_Register($dst$$reg),
6588 as_Register($src1$$reg),
6589 $src2$$constant);
6590 %}
6591
6592 ins_pipe(ialu_reg_imm);
6593 %}
6594
6595 // Integer Subtraction
6596 instruct subI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6597 match(Set dst (SubI src1 src2));
6598
6599 ins_cost(ALU_COST);
6600 format %{ "subw $dst, $src1, $src2\t#@subI_reg_reg" %}
6601
6602 ins_encode %{
6603 __ subw(as_Register($dst$$reg),
6604 as_Register($src1$$reg),
6605 as_Register($src2$$reg));
6606 %}
6607
6608 ins_pipe(ialu_reg_reg);
6609 %}
6610
6611 // Immediate Subtraction
6612 instruct subI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immISub src2) %{
6613 match(Set dst (SubI src1 src2));
6614
6615 ins_cost(ALU_COST);
6616 format %{ "addiw $dst, $src1, -$src2\t#@subI_reg_imm" %}
6617
6618 ins_encode %{
6619 // src2 is imm, so actually call the addiw
6620 __ subw(as_Register($dst$$reg),
6621 as_Register($src1$$reg),
6622 $src2$$constant);
6623 %}
6624
6625 ins_pipe(ialu_reg_imm);
6626 %}
6627
6628 // Long Subtraction
6629 instruct subL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
6630 match(Set dst (SubL src1 src2));
6631 ins_cost(ALU_COST);
6632 format %{ "sub $dst, $src1, $src2\t#@subL_reg_reg" %}
6633
6634 ins_encode %{
6635 __ sub(as_Register($dst$$reg),
6636 as_Register($src1$$reg),
6637 as_Register($src2$$reg));
6638 %}
6639
6640 ins_pipe(ialu_reg_reg);
6641 %}
6642
6643 // No constant pool entries requiredLong Immediate Subtraction.
6644 instruct subL_reg_imm(iRegLNoSp dst, iRegL src1, immLSub src2) %{
6645 match(Set dst (SubL src1 src2));
6646 ins_cost(ALU_COST);
6647 format %{ "addi $dst, $src1, -$src2\t#@subL_reg_imm" %}
6648
6649 ins_encode %{
6650 // src2 is imm, so actually call the addi
6651 __ sub(as_Register($dst$$reg),
6652 as_Register($src1$$reg),
6653 $src2$$constant);
6654 %}
6655
6656 ins_pipe(ialu_reg_imm);
6657 %}
6658
6659 // Integer Negation (special case for sub)
6660
6661 instruct negI_reg(iRegINoSp dst, iRegIorL2I src, immI0 zero) %{
6662 match(Set dst (SubI zero src));
6663 ins_cost(ALU_COST);
6664 format %{ "subw $dst, x0, $src\t# int, #@negI_reg" %}
6665
6666 ins_encode %{
6667 // actually call the subw
6668 __ negw(as_Register($dst$$reg),
6669 as_Register($src$$reg));
6670 %}
6671
6672 ins_pipe(ialu_reg);
6673 %}
6674
6675 // Long Negation
6676
6677 instruct negL_reg(iRegLNoSp dst, iRegL src, immL0 zero) %{
6678 match(Set dst (SubL zero src));
6679 ins_cost(ALU_COST);
6680 format %{ "sub $dst, x0, $src\t# long, #@negL_reg" %}
6681
6682 ins_encode %{
6683 // actually call the sub
6684 __ neg(as_Register($dst$$reg),
6685 as_Register($src$$reg));
6686 %}
6687
6688 ins_pipe(ialu_reg);
6689 %}
6690
6691 // Integer Multiply
6692
6693 instruct mulI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6694 match(Set dst (MulI src1 src2));
6695 ins_cost(IMUL_COST);
6696 format %{ "mulw $dst, $src1, $src2\t#@mulI" %}
6697
6698 //this means 2 word multi, and no sign extend to 64 bits
6699 ins_encode %{
6700 // riscv64 mulw will sign-extension to high 32 bits in dst reg
6701 __ mulw(as_Register($dst$$reg),
6702 as_Register($src1$$reg),
6703 as_Register($src2$$reg));
6704 %}
6705
6706 ins_pipe(imul_reg_reg);
6707 %}
6708
6709 // Long Multiply
6710
6711 instruct mulL(iRegLNoSp dst, iRegL src1, iRegL src2) %{
6712 match(Set dst (MulL src1 src2));
6713 ins_cost(IMUL_COST);
6714 format %{ "mul $dst, $src1, $src2\t#@mulL" %}
6715
6716 ins_encode %{
6717 __ mul(as_Register($dst$$reg),
6718 as_Register($src1$$reg),
6719 as_Register($src2$$reg));
6720 %}
6721
6722 ins_pipe(lmul_reg_reg);
6723 %}
6724
6725 instruct mulHiL_rReg(iRegLNoSp dst, iRegL src1, iRegL src2)
6726 %{
6727 match(Set dst (MulHiL src1 src2));
6728 ins_cost(IMUL_COST);
6729 format %{ "mulh $dst, $src1, $src2\t# mulhi, #@mulHiL_rReg" %}
6730
6731 ins_encode %{
6732 __ mulh(as_Register($dst$$reg),
6733 as_Register($src1$$reg),
6734 as_Register($src2$$reg));
6735 %}
6736
6737 ins_pipe(lmul_reg_reg);
6738 %}
6739
6740 // Integer Divide
6741
6742 instruct divI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6743 match(Set dst (DivI src1 src2));
6744 ins_cost(IDIVSI_COST);
6745 format %{ "divw $dst, $src1, $src2\t#@divI"%}
6746
6747 ins_encode(riscv_enc_divw(dst, src1, src2));
6748 ins_pipe(idiv_reg_reg);
6749 %}
6750
6751 instruct signExtract(iRegINoSp dst, iRegIorL2I src1, immI_31 div1, immI_31 div2) %{
6752 match(Set dst (URShiftI (RShiftI src1 div1) div2));
6753 ins_cost(ALU_COST);
6754 format %{ "srliw $dst, $src1, $div1\t# int signExtract, #@signExtract" %}
6755
6756 ins_encode %{
6757 __ srliw(as_Register($dst$$reg), as_Register($src1$$reg), 31);
6758 %}
6759 ins_pipe(ialu_reg_shift);
6760 %}
6761
6762 // Long Divide
6763
6764 instruct divL(iRegLNoSp dst, iRegL src1, iRegL src2) %{
6765 match(Set dst (DivL src1 src2));
6766 ins_cost(IDIVDI_COST);
6767 format %{ "div $dst, $src1, $src2\t#@divL" %}
6768
6769 ins_encode(riscv_enc_div(dst, src1, src2));
6770 ins_pipe(ldiv_reg_reg);
6771 %}
6772
6773 instruct signExtractL(iRegLNoSp dst, iRegL src1, immI_63 div1, immI_63 div2) %{
6774 match(Set dst (URShiftL (RShiftL src1 div1) div2));
6775 ins_cost(ALU_COST);
6776 format %{ "srli $dst, $src1, $div1\t# long signExtract, #@signExtractL" %}
6777
6778 ins_encode %{
6779 __ srli(as_Register($dst$$reg), as_Register($src1$$reg), 63);
6780 %}
6781 ins_pipe(ialu_reg_shift);
6782 %}
6783
6784 // Integer Remainder
6785
6786 instruct modI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6787 match(Set dst (ModI src1 src2));
6788 ins_cost(IDIVSI_COST);
6789 format %{ "remw $dst, $src1, $src2\t#@modI" %}
6790
6791 ins_encode(riscv_enc_modw(dst, src1, src2));
6792 ins_pipe(ialu_reg_reg);
6793 %}
6794
6795 // Long Remainder
6796
6797 instruct modL(iRegLNoSp dst, iRegL src1, iRegL src2) %{
6798 match(Set dst (ModL src1 src2));
6799 ins_cost(IDIVDI_COST);
6800 format %{ "rem $dst, $src1, $src2\t#@modL" %}
6801
6802 ins_encode(riscv_enc_mod(dst, src1, src2));
6803 ins_pipe(ialu_reg_reg);
6804 %}
6805
6806 // Integer Shifts
6807
6808 // Shift Left Register
6809 // In RV64I, only the low 5 bits of src2 are considered for the shift amount
6810 instruct lShiftI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6811 match(Set dst (LShiftI src1 src2));
6812 ins_cost(ALU_COST);
6813 format %{ "sllw $dst, $src1, $src2\t#@lShiftI_reg_reg" %}
6814
6815 ins_encode %{
6816 __ sllw(as_Register($dst$$reg),
6817 as_Register($src1$$reg),
6818 as_Register($src2$$reg));
6819 %}
6820
6821 ins_pipe(ialu_reg_reg_vshift);
6822 %}
6823
6824 // Shift Left Immediate
6825 instruct lShiftI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immI src2) %{
6826 match(Set dst (LShiftI src1 src2));
6827 ins_cost(ALU_COST);
6828 format %{ "slliw $dst, $src1, ($src2 & 0x1f)\t#@lShiftI_reg_imm" %}
6829
6830 ins_encode %{
6831 // the shift amount is encoded in the lower
6832 // 5 bits of the I-immediate field for RV32I
6833 __ slliw(as_Register($dst$$reg),
6834 as_Register($src1$$reg),
6835 (unsigned) $src2$$constant & 0x1f);
6836 %}
6837
6838 ins_pipe(ialu_reg_shift);
6839 %}
6840
6841 // Shift Right Logical Register
6842 // In RV64I, only the low 5 bits of src2 are considered for the shift amount
6843 instruct urShiftI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6844 match(Set dst (URShiftI src1 src2));
6845 ins_cost(ALU_COST);
6846 format %{ "srlw $dst, $src1, $src2\t#@urShiftI_reg_reg" %}
6847
6848 ins_encode %{
6849 __ srlw(as_Register($dst$$reg),
6850 as_Register($src1$$reg),
6851 as_Register($src2$$reg));
6852 %}
6853
6854 ins_pipe(ialu_reg_reg_vshift);
6855 %}
6856
6857 // Shift Right Logical Immediate
6858 instruct urShiftI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immI src2) %{
6859 match(Set dst (URShiftI src1 src2));
6860 ins_cost(ALU_COST);
6861 format %{ "srliw $dst, $src1, ($src2 & 0x1f)\t#@urShiftI_reg_imm" %}
6862
6863 ins_encode %{
6864 // the shift amount is encoded in the lower
6865 // 6 bits of the I-immediate field for RV64I
6866 __ srliw(as_Register($dst$$reg),
6867 as_Register($src1$$reg),
6868 (unsigned) $src2$$constant & 0x1f);
6869 %}
6870
6871 ins_pipe(ialu_reg_shift);
6872 %}
6873
6874 // Shift Right Arithmetic Register
6875 // In RV64I, only the low 5 bits of src2 are considered for the shift amount
6876 instruct rShiftI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6877 match(Set dst (RShiftI src1 src2));
6878 ins_cost(ALU_COST);
6879 format %{ "sraw $dst, $src1, $src2\t#@rShiftI_reg_reg" %}
6880
6881 ins_encode %{
6882 // riscv will sign-ext dst high 32 bits
6883 __ sraw(as_Register($dst$$reg),
6884 as_Register($src1$$reg),
6885 as_Register($src2$$reg));
6886 %}
6887
6888 ins_pipe(ialu_reg_reg_vshift);
6889 %}
6890
6891 // Shift Right Arithmetic Immediate
6892 instruct rShiftI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immI src2) %{
6893 match(Set dst (RShiftI src1 src2));
6894 ins_cost(ALU_COST);
6895 format %{ "sraiw $dst, $src1, ($src2 & 0x1f)\t#@rShiftI_reg_imm" %}
6896
6897 ins_encode %{
6898 // riscv will sign-ext dst high 32 bits
6899 __ sraiw(as_Register($dst$$reg),
6900 as_Register($src1$$reg),
6901 (unsigned) $src2$$constant & 0x1f);
6902 %}
6903
6904 ins_pipe(ialu_reg_shift);
6905 %}
6906
6907 // Long Shifts
6908
6909 // Shift Left Register
6910 // In RV64I, only the low 6 bits of src2 are considered for the shift amount
6911 instruct lShiftL_reg_reg(iRegLNoSp dst, iRegL src1, iRegIorL2I src2) %{
6912 match(Set dst (LShiftL src1 src2));
6913
6914 ins_cost(ALU_COST);
6915 format %{ "sll $dst, $src1, $src2\t#@lShiftL_reg_reg" %}
6916
6917 ins_encode %{
6918 __ sll(as_Register($dst$$reg),
6919 as_Register($src1$$reg),
6920 as_Register($src2$$reg));
6921 %}
6922
6923 ins_pipe(ialu_reg_reg_vshift);
6924 %}
6925
6926 // Shift Left Immediate
6927 instruct lShiftL_reg_imm(iRegLNoSp dst, iRegL src1, immI src2) %{
6928 match(Set dst (LShiftL src1 src2));
6929
6930 ins_cost(ALU_COST);
6931 format %{ "slli $dst, $src1, ($src2 & 0x3f)\t#@lShiftL_reg_imm" %}
6932
6933 ins_encode %{
6934 // the shift amount is encoded in the lower
6935 // 6 bits of the I-immediate field for RV64I
6936 __ slli(as_Register($dst$$reg),
6937 as_Register($src1$$reg),
6938 (unsigned) $src2$$constant & 0x3f);
6939 %}
6940
6941 ins_pipe(ialu_reg_shift);
6942 %}
6943
6944 // Shift Right Logical Register
6945 // In RV64I, only the low 6 bits of src2 are considered for the shift amount
6946 instruct urShiftL_reg_reg(iRegLNoSp dst, iRegL src1, iRegIorL2I src2) %{
6947 match(Set dst (URShiftL src1 src2));
6948
6949 ins_cost(ALU_COST);
6950 format %{ "srl $dst, $src1, $src2\t#@urShiftL_reg_reg" %}
6951
6952 ins_encode %{
6953 __ srl(as_Register($dst$$reg),
6954 as_Register($src1$$reg),
6955 as_Register($src2$$reg));
6956 %}
6957
6958 ins_pipe(ialu_reg_reg_vshift);
6959 %}
6960
6961 // Shift Right Logical Immediate
6962 instruct urShiftL_reg_imm(iRegLNoSp dst, iRegL src1, immI src2) %{
6963 match(Set dst (URShiftL src1 src2));
6964
6965 ins_cost(ALU_COST);
6966 format %{ "srli $dst, $src1, ($src2 & 0x3f)\t#@urShiftL_reg_imm" %}
6967
6968 ins_encode %{
6969 // the shift amount is encoded in the lower
6970 // 6 bits of the I-immediate field for RV64I
6971 __ srli(as_Register($dst$$reg),
6972 as_Register($src1$$reg),
6973 (unsigned) $src2$$constant & 0x3f);
6974 %}
6975
6976 ins_pipe(ialu_reg_shift);
6977 %}
6978
6979 // A special-case pattern for card table stores.
6980 instruct urShiftP_reg_imm(iRegLNoSp dst, iRegP src1, immI src2) %{
6981 match(Set dst (URShiftL (CastP2X src1) src2));
6982
6983 ins_cost(ALU_COST);
6984 format %{ "srli $dst, p2x($src1), ($src2 & 0x3f)\t#@urShiftP_reg_imm" %}
6985
6986 ins_encode %{
6987 // the shift amount is encoded in the lower
6988 // 6 bits of the I-immediate field for RV64I
6989 __ srli(as_Register($dst$$reg),
6990 as_Register($src1$$reg),
6991 (unsigned) $src2$$constant & 0x3f);
6992 %}
6993
6994 ins_pipe(ialu_reg_shift);
6995 %}
6996
6997 // Shift Right Arithmetic Register
6998 // In RV64I, only the low 6 bits of src2 are considered for the shift amount
6999 instruct rShiftL_reg_reg(iRegLNoSp dst, iRegL src1, iRegIorL2I src2) %{
7000 match(Set dst (RShiftL src1 src2));
7001
7002 ins_cost(ALU_COST);
7003 format %{ "sra $dst, $src1, $src2\t#@rShiftL_reg_reg" %}
7004
7005 ins_encode %{
7006 __ sra(as_Register($dst$$reg),
7007 as_Register($src1$$reg),
7008 as_Register($src2$$reg));
7009 %}
7010
7011 ins_pipe(ialu_reg_reg_vshift);
7012 %}
7013
7014 // Shift Right Arithmetic Immediate
7015 instruct rShiftL_reg_imm(iRegLNoSp dst, iRegL src1, immI src2) %{
7016 match(Set dst (RShiftL src1 src2));
7017
7018 ins_cost(ALU_COST);
7019 format %{ "srai $dst, $src1, ($src2 & 0x3f)\t#@rShiftL_reg_imm" %}
7020
7021 ins_encode %{
7022 // the shift amount is encoded in the lower
7023 // 6 bits of the I-immediate field for RV64I
7024 __ srai(as_Register($dst$$reg),
7025 as_Register($src1$$reg),
7026 (unsigned) $src2$$constant & 0x3f);
7027 %}
7028
7029 ins_pipe(ialu_reg_shift);
7030 %}
7031
7032 instruct regI_not_reg(iRegINoSp dst, iRegI src1, immI_M1 m1) %{
7033 match(Set dst (XorI src1 m1));
7034 ins_cost(ALU_COST);
7035 format %{ "xori $dst, $src1, -1\t#@regI_not_reg" %}
7036
7037 ins_encode %{
7038 __ xori(as_Register($dst$$reg), as_Register($src1$$reg), -1);
7039 %}
7040
7041 ins_pipe(ialu_reg_imm);
7042 %}
7043
7044 instruct regL_not_reg(iRegLNoSp dst, iRegL src1, immL_M1 m1) %{
7045 match(Set dst (XorL src1 m1));
7046 ins_cost(ALU_COST);
7047 format %{ "xori $dst, $src1, -1\t#@regL_not_reg" %}
7048
7049 ins_encode %{
7050 __ xori(as_Register($dst$$reg), as_Register($src1$$reg), -1);
7051 %}
7052
7053 ins_pipe(ialu_reg_imm);
7054 %}
7055
7056
7057 // ============================================================================
7058 // Floating Point Arithmetic Instructions
7059
7060 instruct addF_reg_reg(fRegF dst, fRegF src1, fRegF src2) %{
7061 match(Set dst (AddF src1 src2));
7062
7063 ins_cost(DEFAULT_COST * 5);
7064 format %{ "fadd.s $dst, $src1, $src2\t#@addF_reg_reg" %}
7065
7066 ins_encode %{
7067 __ fadd_s(as_FloatRegister($dst$$reg),
7068 as_FloatRegister($src1$$reg),
7069 as_FloatRegister($src2$$reg));
7070 %}
7071
7072 ins_pipe(fp_dop_reg_reg_s);
7073 %}
7074
7075 instruct addD_reg_reg(fRegD dst, fRegD src1, fRegD src2) %{
7076 match(Set dst (AddD src1 src2));
7077
7078 ins_cost(DEFAULT_COST * 5);
7079 format %{ "fadd.d $dst, $src1, $src2\t#@addD_reg_reg" %}
7080
7081 ins_encode %{
7082 __ fadd_d(as_FloatRegister($dst$$reg),
7083 as_FloatRegister($src1$$reg),
7084 as_FloatRegister($src2$$reg));
7085 %}
7086
7087 ins_pipe(fp_dop_reg_reg_d);
7088 %}
7089
7090 instruct subF_reg_reg(fRegF dst, fRegF src1, fRegF src2) %{
7091 match(Set dst (SubF src1 src2));
7092
7093 ins_cost(DEFAULT_COST * 5);
7094 format %{ "fsub.s $dst, $src1, $src2\t#@subF_reg_reg" %}
7095
7096 ins_encode %{
7097 __ fsub_s(as_FloatRegister($dst$$reg),
7098 as_FloatRegister($src1$$reg),
7099 as_FloatRegister($src2$$reg));
7100 %}
7101
7102 ins_pipe(fp_dop_reg_reg_s);
7103 %}
7104
7105 instruct subD_reg_reg(fRegD dst, fRegD src1, fRegD src2) %{
7106 match(Set dst (SubD src1 src2));
7107
7108 ins_cost(DEFAULT_COST * 5);
7109 format %{ "fsub.d $dst, $src1, $src2\t#@subD_reg_reg" %}
7110
7111 ins_encode %{
7112 __ fsub_d(as_FloatRegister($dst$$reg),
7113 as_FloatRegister($src1$$reg),
7114 as_FloatRegister($src2$$reg));
7115 %}
7116
7117 ins_pipe(fp_dop_reg_reg_d);
7118 %}
7119
7120 instruct mulF_reg_reg(fRegF dst, fRegF src1, fRegF src2) %{
7121 match(Set dst (MulF src1 src2));
7122
7123 ins_cost(FMUL_SINGLE_COST);
7124 format %{ "fmul.s $dst, $src1, $src2\t#@mulF_reg_reg" %}
7125
7126 ins_encode %{
7127 __ fmul_s(as_FloatRegister($dst$$reg),
7128 as_FloatRegister($src1$$reg),
7129 as_FloatRegister($src2$$reg));
7130 %}
7131
7132 ins_pipe(fp_dop_reg_reg_s);
7133 %}
7134
7135 instruct mulD_reg_reg(fRegD dst, fRegD src1, fRegD src2) %{
7136 match(Set dst (MulD src1 src2));
7137
7138 ins_cost(FMUL_DOUBLE_COST);
7139 format %{ "fmul.d $dst, $src1, $src2\t#@mulD_reg_reg" %}
7140
7141 ins_encode %{
7142 __ fmul_d(as_FloatRegister($dst$$reg),
7143 as_FloatRegister($src1$$reg),
7144 as_FloatRegister($src2$$reg));
7145 %}
7146
7147 ins_pipe(fp_dop_reg_reg_d);
7148 %}
7149
7150 // src1 * src2 + src3
7151 instruct maddF_reg_reg(fRegF dst, fRegF src1, fRegF src2, fRegF src3) %{
7152 predicate(UseFMA);
7153 match(Set dst (FmaF src3 (Binary src1 src2)));
7154
7155 ins_cost(FMUL_SINGLE_COST);
7156 format %{ "fmadd.s $dst, $src1, $src2, $src3\t#@maddF_reg_reg" %}
7157
7158 ins_encode %{
7159 __ fmadd_s(as_FloatRegister($dst$$reg),
7160 as_FloatRegister($src1$$reg),
7161 as_FloatRegister($src2$$reg),
7162 as_FloatRegister($src3$$reg));
7163 %}
7164
7165 ins_pipe(pipe_class_default);
7166 %}
7167
7168 // src1 * src2 + src3
7169 instruct maddD_reg_reg(fRegD dst, fRegD src1, fRegD src2, fRegD src3) %{
7170 predicate(UseFMA);
7171 match(Set dst (FmaD src3 (Binary src1 src2)));
7172
7173 ins_cost(FMUL_DOUBLE_COST);
7174 format %{ "fmadd.d $dst, $src1, $src2, $src3\t#@maddD_reg_reg" %}
7175
7176 ins_encode %{
7177 __ fmadd_d(as_FloatRegister($dst$$reg),
7178 as_FloatRegister($src1$$reg),
7179 as_FloatRegister($src2$$reg),
7180 as_FloatRegister($src3$$reg));
7181 %}
7182
7183 ins_pipe(pipe_class_default);
7184 %}
7185
7186 // src1 * src2 - src3
7187 instruct msubF_reg_reg(fRegF dst, fRegF src1, fRegF src2, fRegF src3) %{
7188 predicate(UseFMA);
7189 match(Set dst (FmaF (NegF src3) (Binary src1 src2)));
7190
7191 ins_cost(FMUL_SINGLE_COST);
7192 format %{ "fmsub.s $dst, $src1, $src2, $src3\t#@msubF_reg_reg" %}
7193
7194 ins_encode %{
7195 __ fmsub_s(as_FloatRegister($dst$$reg),
7196 as_FloatRegister($src1$$reg),
7197 as_FloatRegister($src2$$reg),
7198 as_FloatRegister($src3$$reg));
7199 %}
7200
7201 ins_pipe(pipe_class_default);
7202 %}
7203
7204 // src1 * src2 - src3
7205 instruct msubD_reg_reg(fRegD dst, fRegD src1, fRegD src2, fRegD src3) %{
7206 predicate(UseFMA);
7207 match(Set dst (FmaD (NegD src3) (Binary src1 src2)));
7208
7209 ins_cost(FMUL_DOUBLE_COST);
7210 format %{ "fmsub.d $dst, $src1, $src2, $src3\t#@msubD_reg_reg" %}
7211
7212 ins_encode %{
7213 __ fmsub_d(as_FloatRegister($dst$$reg),
7214 as_FloatRegister($src1$$reg),
7215 as_FloatRegister($src2$$reg),
7216 as_FloatRegister($src3$$reg));
7217 %}
7218
7219 ins_pipe(pipe_class_default);
7220 %}
7221
7222 // -src1 * src2 + src3
7223 instruct nmsubF_reg_reg(fRegF dst, fRegF src1, fRegF src2, fRegF src3) %{
7224 predicate(UseFMA);
7225 match(Set dst (FmaF src3 (Binary (NegF src1) src2)));
7226 match(Set dst (FmaF src3 (Binary src1 (NegF src2))));
7227
7228 ins_cost(FMUL_SINGLE_COST);
7229 format %{ "fnmsub.s $dst, $src1, $src2, $src3\t#@nmsubF_reg_reg" %}
7230
7231 ins_encode %{
7232 __ fnmsub_s(as_FloatRegister($dst$$reg),
7233 as_FloatRegister($src1$$reg),
7234 as_FloatRegister($src2$$reg),
7235 as_FloatRegister($src3$$reg));
7236 %}
7237
7238 ins_pipe(pipe_class_default);
7239 %}
7240
7241 // -src1 * src2 + src3
7242 instruct nmsubD_reg_reg(fRegD dst, fRegD src1, fRegD src2, fRegD src3) %{
7243 predicate(UseFMA);
7244 match(Set dst (FmaD src3 (Binary (NegD src1) src2)));
7245 match(Set dst (FmaD src3 (Binary src1 (NegD src2))));
7246
7247 ins_cost(FMUL_DOUBLE_COST);
7248 format %{ "fnmsub.d $dst, $src1, $src2, $src3\t#@nmsubD_reg_reg" %}
7249
7250 ins_encode %{
7251 __ fnmsub_d(as_FloatRegister($dst$$reg),
7252 as_FloatRegister($src1$$reg),
7253 as_FloatRegister($src2$$reg),
7254 as_FloatRegister($src3$$reg));
7255 %}
7256
7257 ins_pipe(pipe_class_default);
7258 %}
7259
7260 // -src1 * src2 - src3
7261 instruct nmaddF_reg_reg(fRegF dst, fRegF src1, fRegF src2, fRegF src3) %{
7262 predicate(UseFMA);
7263 match(Set dst (FmaF (NegF src3) (Binary (NegF src1) src2)));
7264 match(Set dst (FmaF (NegF src3) (Binary src1 (NegF src2))));
7265
7266 ins_cost(FMUL_SINGLE_COST);
7267 format %{ "fnmadd.s $dst, $src1, $src2, $src3\t#@nmaddF_reg_reg" %}
7268
7269 ins_encode %{
7270 __ fnmadd_s(as_FloatRegister($dst$$reg),
7271 as_FloatRegister($src1$$reg),
7272 as_FloatRegister($src2$$reg),
7273 as_FloatRegister($src3$$reg));
7274 %}
7275
7276 ins_pipe(pipe_class_default);
7277 %}
7278
7279 // -src1 * src2 - src3
7280 instruct nmaddD_reg_reg(fRegD dst, fRegD src1, fRegD src2, fRegD src3) %{
7281 predicate(UseFMA);
7282 match(Set dst (FmaD (NegD src3) (Binary (NegD src1) src2)));
7283 match(Set dst (FmaD (NegD src3) (Binary src1 (NegD src2))));
7284
7285 ins_cost(FMUL_DOUBLE_COST);
7286 format %{ "fnmadd.d $dst, $src1, $src2, $src3\t#@nmaddD_reg_reg" %}
7287
7288 ins_encode %{
7289 __ fnmadd_d(as_FloatRegister($dst$$reg),
7290 as_FloatRegister($src1$$reg),
7291 as_FloatRegister($src2$$reg),
7292 as_FloatRegister($src3$$reg));
7293 %}
7294
7295 ins_pipe(pipe_class_default);
7296 %}
7297
7298 // Math.max(FF)F
7299 instruct maxF_reg_reg(fRegF dst, fRegF src1, fRegF src2, rFlagsReg cr) %{
7300 match(Set dst (MaxF src1 src2));
7301 effect(TEMP_DEF dst, KILL cr);
7302
7303 format %{ "maxF $dst, $src1, $src2" %}
7304
7305 ins_encode %{
7306 __ minmax_FD(as_FloatRegister($dst$$reg),
7307 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg),
7308 false /* is_double */, false /* is_min */);
7309 %}
7310
7311 ins_pipe(pipe_class_default);
7312 %}
7313
7314 // Math.min(FF)F
7315 instruct minF_reg_reg(fRegF dst, fRegF src1, fRegF src2, rFlagsReg cr) %{
7316 match(Set dst (MinF src1 src2));
7317 effect(TEMP_DEF dst, KILL cr);
7318
7319 format %{ "minF $dst, $src1, $src2" %}
7320
7321 ins_encode %{
7322 __ minmax_FD(as_FloatRegister($dst$$reg),
7323 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg),
7324 false /* is_double */, true /* is_min */);
7325 %}
7326
7327 ins_pipe(pipe_class_default);
7328 %}
7329
7330 // Math.max(DD)D
7331 instruct maxD_reg_reg(fRegD dst, fRegD src1, fRegD src2, rFlagsReg cr) %{
7332 match(Set dst (MaxD src1 src2));
7333 effect(TEMP_DEF dst, KILL cr);
7334
7335 format %{ "maxD $dst, $src1, $src2" %}
7336
7337 ins_encode %{
7338 __ minmax_FD(as_FloatRegister($dst$$reg),
7339 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg),
7340 true /* is_double */, false /* is_min */);
7341 %}
7342
7343 ins_pipe(pipe_class_default);
7344 %}
7345
7346 // Math.min(DD)D
7347 instruct minD_reg_reg(fRegD dst, fRegD src1, fRegD src2, rFlagsReg cr) %{
7348 match(Set dst (MinD src1 src2));
7349 effect(TEMP_DEF dst, KILL cr);
7350
7351 format %{ "minD $dst, $src1, $src2" %}
7352
7353 ins_encode %{
7354 __ minmax_FD(as_FloatRegister($dst$$reg),
7355 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg),
7356 true /* is_double */, true /* is_min */);
7357 %}
7358
7359 ins_pipe(pipe_class_default);
7360 %}
7361
7362 // Float.isInfinite
7363 instruct isInfiniteF_reg_reg(iRegINoSp dst, fRegF src)
7364 %{
7365 match(Set dst (IsInfiniteF src));
7366
7367 format %{ "isInfinite $dst, $src" %}
7368 ins_encode %{
7369 __ fclass_s(as_Register($dst$$reg), as_FloatRegister($src$$reg));
7370 __ andi(as_Register($dst$$reg), as_Register($dst$$reg), 0b0010000001);
7371 __ slt(as_Register($dst$$reg), zr, as_Register($dst$$reg));
7372 %}
7373
7374 ins_pipe(pipe_class_default);
7375 %}
7376
7377 // Double.isInfinite
7378 instruct isInfiniteD_reg_reg(iRegINoSp dst, fRegD src)
7379 %{
7380 match(Set dst (IsInfiniteD src));
7381
7382 format %{ "isInfinite $dst, $src" %}
7383 ins_encode %{
7384 __ fclass_d(as_Register($dst$$reg), as_FloatRegister($src$$reg));
7385 __ andi(as_Register($dst$$reg), as_Register($dst$$reg), 0b0010000001);
7386 __ slt(as_Register($dst$$reg), zr, as_Register($dst$$reg));
7387 %}
7388
7389 ins_pipe(pipe_class_default);
7390 %}
7391
7392 // Float.isFinite
7393 instruct isFiniteF_reg_reg(iRegINoSp dst, fRegF src)
7394 %{
7395 match(Set dst (IsFiniteF src));
7396
7397 format %{ "isFinite $dst, $src" %}
7398 ins_encode %{
7399 __ fclass_s(as_Register($dst$$reg), as_FloatRegister($src$$reg));
7400 __ andi(as_Register($dst$$reg), as_Register($dst$$reg), 0b0001111110);
7401 __ slt(as_Register($dst$$reg), zr, as_Register($dst$$reg));
7402 %}
7403
7404 ins_pipe(pipe_class_default);
7405 %}
7406
7407 // Double.isFinite
7408 instruct isFiniteD_reg_reg(iRegINoSp dst, fRegD src)
7409 %{
7410 match(Set dst (IsFiniteD src));
7411
7412 format %{ "isFinite $dst, $src" %}
7413 ins_encode %{
7414 __ fclass_d(as_Register($dst$$reg), as_FloatRegister($src$$reg));
7415 __ andi(as_Register($dst$$reg), as_Register($dst$$reg), 0b0001111110);
7416 __ slt(as_Register($dst$$reg), zr, as_Register($dst$$reg));
7417 %}
7418
7419 ins_pipe(pipe_class_default);
7420 %}
7421
7422 instruct divF_reg_reg(fRegF dst, fRegF src1, fRegF src2) %{
7423 match(Set dst (DivF src1 src2));
7424
7425 ins_cost(FDIV_COST);
7426 format %{ "fdiv.s $dst, $src1, $src2\t#@divF_reg_reg" %}
7427
7428 ins_encode %{
7429 __ fdiv_s(as_FloatRegister($dst$$reg),
7430 as_FloatRegister($src1$$reg),
7431 as_FloatRegister($src2$$reg));
7432 %}
7433
7434 ins_pipe(fp_div_s);
7435 %}
7436
7437 instruct divD_reg_reg(fRegD dst, fRegD src1, fRegD src2) %{
7438 match(Set dst (DivD src1 src2));
7439
7440 ins_cost(FDIV_COST);
7441 format %{ "fdiv.d $dst, $src1, $src2\t#@divD_reg_reg" %}
7442
7443 ins_encode %{
7444 __ fdiv_d(as_FloatRegister($dst$$reg),
7445 as_FloatRegister($src1$$reg),
7446 as_FloatRegister($src2$$reg));
7447 %}
7448
7449 ins_pipe(fp_div_d);
7450 %}
7451
7452 instruct negF_reg_reg(fRegF dst, fRegF src) %{
7453 match(Set dst (NegF src));
7454
7455 ins_cost(XFER_COST);
7456 format %{ "fsgnjn.s $dst, $src, $src\t#@negF_reg_reg" %}
7457
7458 ins_encode %{
7459 __ fneg_s(as_FloatRegister($dst$$reg),
7460 as_FloatRegister($src$$reg));
7461 %}
7462
7463 ins_pipe(fp_uop_s);
7464 %}
7465
7466 instruct negD_reg_reg(fRegD dst, fRegD src) %{
7467 match(Set dst (NegD src));
7468
7469 ins_cost(XFER_COST);
7470 format %{ "fsgnjn.d $dst, $src, $src\t#@negD_reg_reg" %}
7471
7472 ins_encode %{
7473 __ fneg_d(as_FloatRegister($dst$$reg),
7474 as_FloatRegister($src$$reg));
7475 %}
7476
7477 ins_pipe(fp_uop_d);
7478 %}
7479
7480 instruct absI_reg(iRegINoSp dst, iRegIorL2I src) %{
7481 match(Set dst (AbsI src));
7482
7483 ins_cost(ALU_COST * 3);
7484 format %{
7485 "sraiw t0, $src, 0x1f\n\t"
7486 "addw $dst, $src, t0\n\t"
7487 "xorr $dst, $dst, t0\t#@absI_reg"
7488 %}
7489
7490 ins_encode %{
7491 __ sraiw(t0, as_Register($src$$reg), 0x1f);
7492 __ addw(as_Register($dst$$reg), as_Register($src$$reg), t0);
7493 __ xorr(as_Register($dst$$reg), as_Register($dst$$reg), t0);
7494 %}
7495
7496 ins_pipe(pipe_class_default);
7497 %}
7498
7499 instruct absL_reg(iRegLNoSp dst, iRegL src) %{
7500 match(Set dst (AbsL src));
7501
7502 ins_cost(ALU_COST * 3);
7503 format %{
7504 "srai t0, $src, 0x3f\n\t"
7505 "add $dst, $src, t0\n\t"
7506 "xorr $dst, $dst, t0\t#@absL_reg"
7507 %}
7508
7509 ins_encode %{
7510 __ srai(t0, as_Register($src$$reg), 0x3f);
7511 __ add(as_Register($dst$$reg), as_Register($src$$reg), t0);
7512 __ xorr(as_Register($dst$$reg), as_Register($dst$$reg), t0);
7513 %}
7514
7515 ins_pipe(pipe_class_default);
7516 %}
7517
7518 instruct absF_reg(fRegF dst, fRegF src) %{
7519 match(Set dst (AbsF src));
7520
7521 ins_cost(XFER_COST);
7522 format %{ "fsgnjx.s $dst, $src, $src\t#@absF_reg" %}
7523 ins_encode %{
7524 __ fabs_s(as_FloatRegister($dst$$reg),
7525 as_FloatRegister($src$$reg));
7526 %}
7527
7528 ins_pipe(fp_uop_s);
7529 %}
7530
7531 instruct absD_reg(fRegD dst, fRegD src) %{
7532 match(Set dst (AbsD src));
7533
7534 ins_cost(XFER_COST);
7535 format %{ "fsgnjx.d $dst, $src, $src\t#@absD_reg" %}
7536 ins_encode %{
7537 __ fabs_d(as_FloatRegister($dst$$reg),
7538 as_FloatRegister($src$$reg));
7539 %}
7540
7541 ins_pipe(fp_uop_d);
7542 %}
7543
7544 instruct sqrtF_reg(fRegF dst, fRegF src) %{
7545 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
7546
7547 ins_cost(FSQRT_COST);
7548 format %{ "fsqrt.s $dst, $src\t#@sqrtF_reg" %}
7549 ins_encode %{
7550 __ fsqrt_s(as_FloatRegister($dst$$reg),
7551 as_FloatRegister($src$$reg));
7552 %}
7553
7554 ins_pipe(fp_sqrt_s);
7555 %}
7556
7557 instruct sqrtD_reg(fRegD dst, fRegD src) %{
7558 match(Set dst (SqrtD src));
7559
7560 ins_cost(FSQRT_COST);
7561 format %{ "fsqrt.d $dst, $src\t#@sqrtD_reg" %}
7562 ins_encode %{
7563 __ fsqrt_d(as_FloatRegister($dst$$reg),
7564 as_FloatRegister($src$$reg));
7565 %}
7566
7567 ins_pipe(fp_sqrt_d);
7568 %}
7569
7570 // Arithmetic Instructions End
7571
7572 // ============================================================================
7573 // Logical Instructions
7574
7575 // Register And
7576 instruct andI_reg_reg(iRegINoSp dst, iRegI src1, iRegI src2) %{
7577 match(Set dst (AndI src1 src2));
7578
7579 format %{ "andr $dst, $src1, $src2\t#@andI_reg_reg" %}
7580
7581 ins_cost(ALU_COST);
7582 ins_encode %{
7583 __ andr(as_Register($dst$$reg),
7584 as_Register($src1$$reg),
7585 as_Register($src2$$reg));
7586 %}
7587
7588 ins_pipe(ialu_reg_reg);
7589 %}
7590
7591 // Immediate And
7592 instruct andI_reg_imm(iRegINoSp dst, iRegI src1, immIAdd src2) %{
7593 match(Set dst (AndI src1 src2));
7594
7595 format %{ "andi $dst, $src1, $src2\t#@andI_reg_imm" %}
7596
7597 ins_cost(ALU_COST);
7598 ins_encode %{
7599 __ andi(as_Register($dst$$reg),
7600 as_Register($src1$$reg),
7601 (int32_t)($src2$$constant));
7602 %}
7603
7604 ins_pipe(ialu_reg_imm);
7605 %}
7606
7607 // Register Or
7608 instruct orI_reg_reg(iRegINoSp dst, iRegI src1, iRegI src2) %{
7609 match(Set dst (OrI src1 src2));
7610
7611 format %{ "orr $dst, $src1, $src2\t#@orI_reg_reg" %}
7612
7613 ins_cost(ALU_COST);
7614 ins_encode %{
7615 __ orr(as_Register($dst$$reg),
7616 as_Register($src1$$reg),
7617 as_Register($src2$$reg));
7618 %}
7619
7620 ins_pipe(ialu_reg_reg);
7621 %}
7622
7623 // Immediate Or
7624 instruct orI_reg_imm(iRegINoSp dst, iRegI src1, immIAdd src2) %{
7625 match(Set dst (OrI src1 src2));
7626
7627 format %{ "ori $dst, $src1, $src2\t#@orI_reg_imm" %}
7628
7629 ins_cost(ALU_COST);
7630 ins_encode %{
7631 __ ori(as_Register($dst$$reg),
7632 as_Register($src1$$reg),
7633 (int32_t)($src2$$constant));
7634 %}
7635
7636 ins_pipe(ialu_reg_imm);
7637 %}
7638
7639 // Register Xor
7640 instruct xorI_reg_reg(iRegINoSp dst, iRegI src1, iRegI src2) %{
7641 match(Set dst (XorI src1 src2));
7642
7643 format %{ "xorr $dst, $src1, $src2\t#@xorI_reg_reg" %}
7644
7645 ins_cost(ALU_COST);
7646 ins_encode %{
7647 __ xorr(as_Register($dst$$reg),
7648 as_Register($src1$$reg),
7649 as_Register($src2$$reg));
7650 %}
7651
7652 ins_pipe(ialu_reg_reg);
7653 %}
7654
7655 // Immediate Xor
7656 instruct xorI_reg_imm(iRegINoSp dst, iRegI src1, immIAdd src2) %{
7657 match(Set dst (XorI src1 src2));
7658
7659 format %{ "xori $dst, $src1, $src2\t#@xorI_reg_imm" %}
7660
7661 ins_cost(ALU_COST);
7662 ins_encode %{
7663 __ xori(as_Register($dst$$reg),
7664 as_Register($src1$$reg),
7665 (int32_t)($src2$$constant));
7666 %}
7667
7668 ins_pipe(ialu_reg_imm);
7669 %}
7670
7671 // Register And Long
7672 instruct andL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
7673 match(Set dst (AndL src1 src2));
7674
7675 format %{ "andr $dst, $src1, $src2\t#@andL_reg_reg" %}
7676
7677 ins_cost(ALU_COST);
7678 ins_encode %{
7679 __ andr(as_Register($dst$$reg),
7680 as_Register($src1$$reg),
7681 as_Register($src2$$reg));
7682 %}
7683
7684 ins_pipe(ialu_reg_reg);
7685 %}
7686
7687 // Immediate And Long
7688 instruct andL_reg_imm(iRegLNoSp dst, iRegL src1, immLAdd src2) %{
7689 match(Set dst (AndL src1 src2));
7690
7691 format %{ "andi $dst, $src1, $src2\t#@andL_reg_imm" %}
7692
7693 ins_cost(ALU_COST);
7694 ins_encode %{
7695 __ andi(as_Register($dst$$reg),
7696 as_Register($src1$$reg),
7697 (int32_t)($src2$$constant));
7698 %}
7699
7700 ins_pipe(ialu_reg_imm);
7701 %}
7702
7703 // Register Or Long
7704 instruct orL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
7705 match(Set dst (OrL src1 src2));
7706
7707 format %{ "orr $dst, $src1, $src2\t#@orL_reg_reg" %}
7708
7709 ins_cost(ALU_COST);
7710 ins_encode %{
7711 __ orr(as_Register($dst$$reg),
7712 as_Register($src1$$reg),
7713 as_Register($src2$$reg));
7714 %}
7715
7716 ins_pipe(ialu_reg_reg);
7717 %}
7718
7719 // Immediate Or Long
7720 instruct orL_reg_imm(iRegLNoSp dst, iRegL src1, immLAdd src2) %{
7721 match(Set dst (OrL src1 src2));
7722
7723 format %{ "ori $dst, $src1, $src2\t#@orL_reg_imm" %}
7724
7725 ins_cost(ALU_COST);
7726 ins_encode %{
7727 __ ori(as_Register($dst$$reg),
7728 as_Register($src1$$reg),
7729 (int32_t)($src2$$constant));
7730 %}
7731
7732 ins_pipe(ialu_reg_imm);
7733 %}
7734
7735 // Register Xor Long
7736 instruct xorL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
7737 match(Set dst (XorL src1 src2));
7738
7739 format %{ "xorr $dst, $src1, $src2\t#@xorL_reg_reg" %}
7740
7741 ins_cost(ALU_COST);
7742 ins_encode %{
7743 __ xorr(as_Register($dst$$reg),
7744 as_Register($src1$$reg),
7745 as_Register($src2$$reg));
7746 %}
7747
7748 ins_pipe(ialu_reg_reg);
7749 %}
7750
7751 // Immediate Xor Long
7752 instruct xorL_reg_imm(iRegLNoSp dst, iRegL src1, immLAdd src2) %{
7753 match(Set dst (XorL src1 src2));
7754
7755 ins_cost(ALU_COST);
7756 format %{ "xori $dst, $src1, $src2\t#@xorL_reg_imm" %}
7757
7758 ins_encode %{
7759 __ xori(as_Register($dst$$reg),
7760 as_Register($src1$$reg),
7761 (int32_t)($src2$$constant));
7762 %}
7763
7764 ins_pipe(ialu_reg_imm);
7765 %}
7766
7767 // ============================================================================
7768 // BSWAP Instructions
7769
7770 instruct bytes_reverse_int(iRegINoSp dst, iRegIorL2I src, rFlagsReg cr) %{
7771 match(Set dst (ReverseBytesI src));
7772 effect(KILL cr);
7773
7774 ins_cost(ALU_COST * 13);
7775 format %{ "revb_w_w $dst, $src\t#@bytes_reverse_int" %}
7776
7777 ins_encode %{
7778 __ revb_w_w(as_Register($dst$$reg), as_Register($src$$reg));
7779 %}
7780
7781 ins_pipe(pipe_class_default);
7782 %}
7783
7784 instruct bytes_reverse_long(iRegLNoSp dst, iRegL src, rFlagsReg cr) %{
7785 match(Set dst (ReverseBytesL src));
7786 effect(KILL cr);
7787
7788 ins_cost(ALU_COST * 29);
7789 format %{ "revb $dst, $src\t#@bytes_reverse_long" %}
7790
7791 ins_encode %{
7792 __ revb(as_Register($dst$$reg), as_Register($src$$reg));
7793 %}
7794
7795 ins_pipe(pipe_class_default);
7796 %}
7797
7798 instruct bytes_reverse_unsigned_short(iRegINoSp dst, iRegIorL2I src) %{
7799 match(Set dst (ReverseBytesUS src));
7800
7801 ins_cost(ALU_COST * 5);
7802 format %{ "revb_h_h_u $dst, $src\t#@bytes_reverse_unsigned_short" %}
7803
7804 ins_encode %{
7805 __ revb_h_h_u(as_Register($dst$$reg), as_Register($src$$reg));
7806 %}
7807
7808 ins_pipe(pipe_class_default);
7809 %}
7810
7811 instruct bytes_reverse_short(iRegINoSp dst, iRegIorL2I src) %{
7812 match(Set dst (ReverseBytesS src));
7813
7814 ins_cost(ALU_COST * 5);
7815 format %{ "revb_h_h $dst, $src\t#@bytes_reverse_short" %}
7816
7817 ins_encode %{
7818 __ revb_h_h(as_Register($dst$$reg), as_Register($src$$reg));
7819 %}
7820
7821 ins_pipe(pipe_class_default);
7822 %}
7823
7824 // ============================================================================
7825 // MemBar Instruction
7826
7827 instruct load_fence() %{
7828 match(LoadFence);
7829 ins_cost(ALU_COST);
7830
7831 format %{ "#@load_fence" %}
7832
7833 ins_encode %{
7834 __ membar(MacroAssembler::LoadLoad | MacroAssembler::LoadStore);
7835 %}
7836 ins_pipe(pipe_serial);
7837 %}
7838
7839 instruct membar_acquire() %{
7840 match(MemBarAcquire);
7841 ins_cost(ALU_COST);
7842
7843 format %{ "#@membar_acquire\n\t"
7844 "fence ir iorw" %}
7845
7846 ins_encode %{
7847 __ block_comment("membar_acquire");
7848 __ membar(MacroAssembler::LoadLoad | MacroAssembler::LoadStore);
7849 %}
7850
7851 ins_pipe(pipe_serial);
7852 %}
7853
7854 instruct membar_acquire_lock() %{
7855 match(MemBarAcquireLock);
7856 ins_cost(0);
7857
7858 format %{ "#@membar_acquire_lock (elided)" %}
7859
7860 ins_encode %{
7861 __ block_comment("membar_acquire_lock (elided)");
7862 %}
7863
7864 ins_pipe(pipe_serial);
7865 %}
7866
7867 instruct store_fence() %{
7868 match(StoreFence);
7869 ins_cost(ALU_COST);
7870
7871 format %{ "#@store_fence" %}
7872
7873 ins_encode %{
7874 __ membar(MacroAssembler::LoadStore | MacroAssembler::StoreStore);
7875 %}
7876 ins_pipe(pipe_serial);
7877 %}
7878
7879 instruct membar_release() %{
7880 match(MemBarRelease);
7881 ins_cost(ALU_COST);
7882
7883 format %{ "#@membar_release\n\t"
7884 "fence iorw ow" %}
7885
7886 ins_encode %{
7887 __ block_comment("membar_release");
7888 __ membar(MacroAssembler::LoadStore | MacroAssembler::StoreStore);
7889 %}
7890 ins_pipe(pipe_serial);
7891 %}
7892
7893 instruct membar_storestore() %{
7894 match(MemBarStoreStore);
7895 match(StoreStoreFence);
7896 ins_cost(ALU_COST);
7897
7898 format %{ "MEMBAR-store-store\t#@membar_storestore" %}
7899
7900 ins_encode %{
7901 __ membar(MacroAssembler::StoreStore);
7902 %}
7903 ins_pipe(pipe_serial);
7904 %}
7905
7906 instruct membar_release_lock() %{
7907 match(MemBarReleaseLock);
7908 ins_cost(0);
7909
7910 format %{ "#@membar_release_lock (elided)" %}
7911
7912 ins_encode %{
7913 __ block_comment("membar_release_lock (elided)");
7914 %}
7915
7916 ins_pipe(pipe_serial);
7917 %}
7918
7919 instruct membar_volatile() %{
7920 match(MemBarVolatile);
7921 ins_cost(ALU_COST);
7922
7923 format %{ "#@membar_volatile\n\t"
7924 "fence iorw iorw"%}
7925
7926 ins_encode %{
7927 __ block_comment("membar_volatile");
7928 __ membar(MacroAssembler::StoreLoad);
7929 %}
7930
7931 ins_pipe(pipe_serial);
7932 %}
7933
7934 instruct spin_wait() %{
7935 predicate(UseZihintpause);
7936 match(OnSpinWait);
7937 ins_cost(CACHE_MISS_COST);
7938
7939 format %{ "spin_wait" %}
7940
7941 ins_encode %{
7942 __ pause();
7943 %}
7944
7945 ins_pipe(pipe_serial);
7946 %}
7947
7948 // ============================================================================
7949 // Cast Instructions (Java-level type cast)
7950
7951 instruct castX2P(iRegPNoSp dst, iRegL src) %{
7952 match(Set dst (CastX2P src));
7953
7954 ins_cost(ALU_COST);
7955 format %{ "mv $dst, $src\t# long -> ptr, #@castX2P" %}
7956
7957 ins_encode %{
7958 if ($dst$$reg != $src$$reg) {
7959 __ mv(as_Register($dst$$reg), as_Register($src$$reg));
7960 }
7961 %}
7962
7963 ins_pipe(ialu_reg);
7964 %}
7965
7966 instruct castP2X(iRegLNoSp dst, iRegP src) %{
7967 match(Set dst (CastP2X src));
7968
7969 ins_cost(ALU_COST);
7970 format %{ "mv $dst, $src\t# ptr -> long, #@castP2X" %}
7971
7972 ins_encode %{
7973 if ($dst$$reg != $src$$reg) {
7974 __ mv(as_Register($dst$$reg), as_Register($src$$reg));
7975 }
7976 %}
7977
7978 ins_pipe(ialu_reg);
7979 %}
7980
7981 instruct castPP(iRegPNoSp dst)
7982 %{
7983 match(Set dst (CastPP dst));
7984 ins_cost(0);
7985
7986 size(0);
7987 format %{ "# castPP of $dst, #@castPP" %}
7988 ins_encode(/* empty encoding */);
7989 ins_pipe(pipe_class_empty);
7990 %}
7991
7992 instruct castLL(iRegL dst)
7993 %{
7994 match(Set dst (CastLL dst));
7995
7996 size(0);
7997 format %{ "# castLL of $dst, #@castLL" %}
7998 ins_encode(/* empty encoding */);
7999 ins_cost(0);
8000 ins_pipe(pipe_class_empty);
8001 %}
8002
8003 instruct castII(iRegI dst)
8004 %{
8005 match(Set dst (CastII dst));
8006
8007 size(0);
8008 format %{ "# castII of $dst, #@castII" %}
8009 ins_encode(/* empty encoding */);
8010 ins_cost(0);
8011 ins_pipe(pipe_class_empty);
8012 %}
8013
8014 instruct checkCastPP(iRegPNoSp dst)
8015 %{
8016 match(Set dst (CheckCastPP dst));
8017
8018 size(0);
8019 ins_cost(0);
8020 format %{ "# checkcastPP of $dst, #@checkCastPP" %}
8021 ins_encode(/* empty encoding */);
8022 ins_pipe(pipe_class_empty);
8023 %}
8024
8025 instruct castFF(fRegF dst)
8026 %{
8027 match(Set dst (CastFF dst));
8028
8029 size(0);
8030 format %{ "# castFF of $dst" %}
8031 ins_encode(/* empty encoding */);
8032 ins_cost(0);
8033 ins_pipe(pipe_class_empty);
8034 %}
8035
8036 instruct castDD(fRegD dst)
8037 %{
8038 match(Set dst (CastDD dst));
8039
8040 size(0);
8041 format %{ "# castDD of $dst" %}
8042 ins_encode(/* empty encoding */);
8043 ins_cost(0);
8044 ins_pipe(pipe_class_empty);
8045 %}
8046
8047 instruct castVV(vReg dst)
8048 %{
8049 match(Set dst (CastVV dst));
8050
8051 size(0);
8052 format %{ "# castVV of $dst" %}
8053 ins_encode(/* empty encoding */);
8054 ins_cost(0);
8055 ins_pipe(pipe_class_empty);
8056 %}
8057
8058 // ============================================================================
8059 // Convert Instructions
8060
8061 // int to bool
8062 instruct convI2Bool(iRegINoSp dst, iRegI src)
8063 %{
8064 match(Set dst (Conv2B src));
8065
8066 ins_cost(ALU_COST);
8067 format %{ "snez $dst, $src\t#@convI2Bool" %}
8068
8069 ins_encode %{
8070 __ snez(as_Register($dst$$reg), as_Register($src$$reg));
8071 %}
8072
8073 ins_pipe(ialu_reg);
8074 %}
8075
8076 // pointer to bool
8077 instruct convP2Bool(iRegINoSp dst, iRegP src)
8078 %{
8079 match(Set dst (Conv2B src));
8080
8081 ins_cost(ALU_COST);
8082 format %{ "snez $dst, $src\t#@convP2Bool" %}
8083
8084 ins_encode %{
8085 __ snez(as_Register($dst$$reg), as_Register($src$$reg));
8086 %}
8087
8088 ins_pipe(ialu_reg);
8089 %}
8090
8091 // int <-> long
8092
8093 instruct convI2L_reg_reg(iRegLNoSp dst, iRegIorL2I src)
8094 %{
8095 match(Set dst (ConvI2L src));
8096
8097 ins_cost(ALU_COST);
8098 format %{ "addw $dst, $src, zr\t#@convI2L_reg_reg" %}
8099 ins_encode %{
8100 __ addw(as_Register($dst$$reg), as_Register($src$$reg), zr);
8101 %}
8102 ins_pipe(ialu_reg);
8103 %}
8104
8105 instruct convL2I_reg(iRegINoSp dst, iRegL src) %{
8106 match(Set dst (ConvL2I src));
8107
8108 ins_cost(ALU_COST);
8109 format %{ "addw $dst, $src, zr\t#@convL2I_reg" %}
8110
8111 ins_encode %{
8112 __ addw(as_Register($dst$$reg), as_Register($src$$reg), zr);
8113 %}
8114
8115 ins_pipe(ialu_reg);
8116 %}
8117
8118 // int to unsigned long (Zero-extend)
8119 instruct convI2UL_reg_reg(iRegLNoSp dst, iRegIorL2I src, immL_32bits mask)
8120 %{
8121 match(Set dst (AndL (ConvI2L src) mask));
8122
8123 ins_cost(ALU_COST * 2);
8124 format %{ "zero_extend $dst, $src, 32\t# i2ul, #@convI2UL_reg_reg" %}
8125
8126 ins_encode %{
8127 __ zero_extend(as_Register($dst$$reg), as_Register($src$$reg), 32);
8128 %}
8129
8130 ins_pipe(ialu_reg_shift);
8131 %}
8132
8133 // float <-> double
8134
8135 instruct convF2D_reg(fRegD dst, fRegF src) %{
8136 match(Set dst (ConvF2D src));
8137
8138 ins_cost(XFER_COST);
8139 format %{ "fcvt.d.s $dst, $src\t#@convF2D_reg" %}
8140
8141 ins_encode %{
8142 __ fcvt_d_s(as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg));
8143 %}
8144
8145 ins_pipe(fp_f2d);
8146 %}
8147
8148 instruct convD2F_reg(fRegF dst, fRegD src) %{
8149 match(Set dst (ConvD2F src));
8150
8151 ins_cost(XFER_COST);
8152 format %{ "fcvt.s.d $dst, $src\t#@convD2F_reg" %}
8153
8154 ins_encode %{
8155 __ fcvt_s_d(as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg));
8156 %}
8157
8158 ins_pipe(fp_d2f);
8159 %}
8160
8161 // float <-> int
8162
8163 instruct convF2I_reg_reg(iRegINoSp dst, fRegF src) %{
8164 match(Set dst (ConvF2I src));
8165
8166 ins_cost(XFER_COST);
8167 format %{ "fcvt.w.s $dst, $src\t#@convF2I_reg_reg" %}
8168
8169 ins_encode %{
8170 __ fcvt_w_s_safe($dst$$Register, $src$$FloatRegister);
8171 %}
8172
8173 ins_pipe(fp_f2i);
8174 %}
8175
8176 instruct convI2F_reg_reg(fRegF dst, iRegIorL2I src) %{
8177 match(Set dst (ConvI2F src));
8178
8179 ins_cost(XFER_COST);
8180 format %{ "fcvt.s.w $dst, $src\t#@convI2F_reg_reg" %}
8181
8182 ins_encode %{
8183 __ fcvt_s_w(as_FloatRegister($dst$$reg), as_Register($src$$reg));
8184 %}
8185
8186 ins_pipe(fp_i2f);
8187 %}
8188
8189 // float <-> long
8190
8191 instruct convF2L_reg_reg(iRegLNoSp dst, fRegF src) %{
8192 match(Set dst (ConvF2L src));
8193
8194 ins_cost(XFER_COST);
8195 format %{ "fcvt.l.s $dst, $src\t#@convF2L_reg_reg" %}
8196
8197 ins_encode %{
8198 __ fcvt_l_s_safe($dst$$Register, $src$$FloatRegister);
8199 %}
8200
8201 ins_pipe(fp_f2l);
8202 %}
8203
8204 instruct convL2F_reg_reg(fRegF dst, iRegL src) %{
8205 match(Set dst (ConvL2F src));
8206
8207 ins_cost(XFER_COST);
8208 format %{ "fcvt.s.l $dst, $src\t#@convL2F_reg_reg" %}
8209
8210 ins_encode %{
8211 __ fcvt_s_l(as_FloatRegister($dst$$reg), as_Register($src$$reg));
8212 %}
8213
8214 ins_pipe(fp_l2f);
8215 %}
8216
8217 // float <-> half float
8218
8219 instruct convHF2F_reg_reg(fRegF dst, iRegINoSp src, fRegF tmp) %{
8220 predicate(UseZfhmin);
8221 match(Set dst (ConvHF2F src));
8222 effect(TEMP tmp);
8223
8224 ins_cost(XFER_COST);
8225 format %{ "fmv.h.x $tmp, $src\t#@convHF2F_reg_reg\n\t"
8226 "fcvt.s.h $dst, $tmp\t#@convHF2F_reg_reg"
8227 %}
8228
8229 ins_encode %{
8230 __ fmv_h_x($tmp$$FloatRegister, $src$$Register);
8231 __ fcvt_s_h($dst$$FloatRegister, $tmp$$FloatRegister);
8232 %}
8233
8234 ins_pipe(fp_i2f);
8235 %}
8236
8237 instruct convF2HF_reg_reg(iRegINoSp dst, fRegF src, fRegF tmp) %{
8238 predicate(UseZfhmin);
8239 match(Set dst (ConvF2HF src));
8240 effect(TEMP tmp);
8241
8242 ins_cost(XFER_COST);
8243 format %{ "fcvt.h.s $tmp, $src\t#@convF2HF_reg_reg\n\t"
8244 "fmv.x.h $dst, $tmp\t#@convF2HF_reg_reg"
8245 %}
8246
8247 ins_encode %{
8248 __ fcvt_h_s($tmp$$FloatRegister, $src$$FloatRegister);
8249 __ fmv_x_h($dst$$Register, $tmp$$FloatRegister);
8250 %}
8251
8252 ins_pipe(fp_f2i);
8253 %}
8254
8255 // double <-> int
8256
8257 instruct convD2I_reg_reg(iRegINoSp dst, fRegD src) %{
8258 match(Set dst (ConvD2I src));
8259
8260 ins_cost(XFER_COST);
8261 format %{ "fcvt.w.d $dst, $src\t#@convD2I_reg_reg" %}
8262
8263 ins_encode %{
8264 __ fcvt_w_d_safe($dst$$Register, $src$$FloatRegister);
8265 %}
8266
8267 ins_pipe(fp_d2i);
8268 %}
8269
8270 instruct convI2D_reg_reg(fRegD dst, iRegIorL2I src) %{
8271 match(Set dst (ConvI2D src));
8272
8273 ins_cost(XFER_COST);
8274 format %{ "fcvt.d.w $dst, $src\t#@convI2D_reg_reg" %}
8275
8276 ins_encode %{
8277 __ fcvt_d_w(as_FloatRegister($dst$$reg), as_Register($src$$reg));
8278 %}
8279
8280 ins_pipe(fp_i2d);
8281 %}
8282
8283 // double <-> long
8284
8285 instruct convD2L_reg_reg(iRegLNoSp dst, fRegD src) %{
8286 match(Set dst (ConvD2L src));
8287
8288 ins_cost(XFER_COST);
8289 format %{ "fcvt.l.d $dst, $src\t#@convD2L_reg_reg" %}
8290
8291 ins_encode %{
8292 __ fcvt_l_d_safe($dst$$Register, $src$$FloatRegister);
8293 %}
8294
8295 ins_pipe(fp_d2l);
8296 %}
8297
8298 instruct convL2D_reg_reg(fRegD dst, iRegL src) %{
8299 match(Set dst (ConvL2D src));
8300
8301 ins_cost(XFER_COST);
8302 format %{ "fcvt.d.l $dst, $src\t#@convL2D_reg_reg" %}
8303
8304 ins_encode %{
8305 __ fcvt_d_l(as_FloatRegister($dst$$reg), as_Register($src$$reg));
8306 %}
8307
8308 ins_pipe(fp_l2d);
8309 %}
8310
8311 // Convert oop into int for vectors alignment masking
8312 instruct convP2I(iRegINoSp dst, iRegP src) %{
8313 match(Set dst (ConvL2I (CastP2X src)));
8314
8315 ins_cost(ALU_COST * 2);
8316 format %{ "zero_extend $dst, $src, 32\t# ptr -> int, #@convP2I" %}
8317
8318 ins_encode %{
8319 __ zero_extend($dst$$Register, $src$$Register, 32);
8320 %}
8321
8322 ins_pipe(ialu_reg);
8323 %}
8324
8325 // Convert compressed oop into int for vectors alignment masking
8326 // in case of 32bit oops (heap < 4Gb).
8327 instruct convN2I(iRegINoSp dst, iRegN src)
8328 %{
8329 predicate(CompressedOops::shift() == 0);
8330 match(Set dst (ConvL2I (CastP2X (DecodeN src))));
8331
8332 ins_cost(ALU_COST);
8333 format %{ "mv $dst, $src\t# compressed ptr -> int, #@convN2I" %}
8334
8335 ins_encode %{
8336 __ mv($dst$$Register, $src$$Register);
8337 %}
8338
8339 ins_pipe(ialu_reg);
8340 %}
8341
8342 // Convert oop pointer into compressed form
8343 instruct encodeHeapOop(iRegNNoSp dst, iRegP src) %{
8344 match(Set dst (EncodeP src));
8345 ins_cost(ALU_COST);
8346 format %{ "encode_heap_oop $dst, $src\t#@encodeHeapOop" %}
8347 ins_encode %{
8348 Register s = $src$$Register;
8349 Register d = $dst$$Register;
8350 __ encode_heap_oop(d, s);
8351 %}
8352 ins_pipe(pipe_class_default);
8353 %}
8354
8355 instruct decodeHeapOop(iRegPNoSp dst, iRegN src) %{
8356 predicate(n->bottom_type()->is_ptr()->ptr() != TypePtr::NotNull &&
8357 n->bottom_type()->is_ptr()->ptr() != TypePtr::Constant);
8358 match(Set dst (DecodeN src));
8359
8360 ins_cost(0);
8361 format %{ "decode_heap_oop $dst, $src\t#@decodeHeapOop" %}
8362 ins_encode %{
8363 Register s = $src$$Register;
8364 Register d = $dst$$Register;
8365 __ decode_heap_oop(d, s);
8366 %}
8367 ins_pipe(pipe_class_default);
8368 %}
8369
8370 instruct decodeHeapOop_not_null(iRegPNoSp dst, iRegN src) %{
8371 predicate(n->bottom_type()->is_ptr()->ptr() == TypePtr::NotNull ||
8372 n->bottom_type()->is_ptr()->ptr() == TypePtr::Constant);
8373 match(Set dst (DecodeN src));
8374
8375 ins_cost(0);
8376 format %{ "decode_heap_oop_not_null $dst, $src\t#@decodeHeapOop_not_null" %}
8377 ins_encode %{
8378 Register s = $src$$Register;
8379 Register d = $dst$$Register;
8380 __ decode_heap_oop_not_null(d, s);
8381 %}
8382 ins_pipe(pipe_class_default);
8383 %}
8384
8385 // Convert klass pointer into compressed form.
8386 instruct encodeKlass_not_null(iRegNNoSp dst, iRegP src) %{
8387 match(Set dst (EncodePKlass src));
8388
8389 ins_cost(ALU_COST);
8390 format %{ "encode_klass_not_null $dst, $src\t#@encodeKlass_not_null" %}
8391
8392 ins_encode %{
8393 Register src_reg = as_Register($src$$reg);
8394 Register dst_reg = as_Register($dst$$reg);
8395 __ encode_klass_not_null(dst_reg, src_reg, t0);
8396 %}
8397
8398 ins_pipe(pipe_class_default);
8399 %}
8400
8401 instruct decodeKlass_not_null(iRegPNoSp dst, iRegN src, iRegPNoSp tmp) %{
8402 match(Set dst (DecodeNKlass src));
8403
8404 effect(TEMP tmp);
8405
8406 ins_cost(ALU_COST);
8407 format %{ "decode_klass_not_null $dst, $src\t#@decodeKlass_not_null" %}
8408
8409 ins_encode %{
8410 Register src_reg = as_Register($src$$reg);
8411 Register dst_reg = as_Register($dst$$reg);
8412 Register tmp_reg = as_Register($tmp$$reg);
8413 __ decode_klass_not_null(dst_reg, src_reg, tmp_reg);
8414 %}
8415
8416 ins_pipe(pipe_class_default);
8417 %}
8418
8419 // stack <-> reg and reg <-> reg shuffles with no conversion
8420
8421 instruct MoveF2I_stack_reg(iRegINoSp dst, stackSlotF src) %{
8422
8423 match(Set dst (MoveF2I src));
8424
8425 effect(DEF dst, USE src);
8426
8427 ins_cost(LOAD_COST);
8428
8429 format %{ "lw $dst, $src\t#@MoveF2I_stack_reg" %}
8430
8431 ins_encode %{
8432 __ lw(as_Register($dst$$reg), Address(sp, $src$$disp));
8433 %}
8434
8435 ins_pipe(iload_reg_reg);
8436
8437 %}
8438
8439 instruct MoveI2F_stack_reg(fRegF dst, stackSlotI src) %{
8440
8441 match(Set dst (MoveI2F src));
8442
8443 effect(DEF dst, USE src);
8444
8445 ins_cost(LOAD_COST);
8446
8447 format %{ "flw $dst, $src\t#@MoveI2F_stack_reg" %}
8448
8449 ins_encode %{
8450 __ flw(as_FloatRegister($dst$$reg), Address(sp, $src$$disp));
8451 %}
8452
8453 ins_pipe(fp_load_mem_s);
8454
8455 %}
8456
8457 instruct MoveD2L_stack_reg(iRegLNoSp dst, stackSlotD src) %{
8458
8459 match(Set dst (MoveD2L src));
8460
8461 effect(DEF dst, USE src);
8462
8463 ins_cost(LOAD_COST);
8464
8465 format %{ "ld $dst, $src\t#@MoveD2L_stack_reg" %}
8466
8467 ins_encode %{
8468 __ ld(as_Register($dst$$reg), Address(sp, $src$$disp));
8469 %}
8470
8471 ins_pipe(iload_reg_reg);
8472
8473 %}
8474
8475 instruct MoveL2D_stack_reg(fRegD dst, stackSlotL src) %{
8476
8477 match(Set dst (MoveL2D src));
8478
8479 effect(DEF dst, USE src);
8480
8481 ins_cost(LOAD_COST);
8482
8483 format %{ "fld $dst, $src\t#@MoveL2D_stack_reg" %}
8484
8485 ins_encode %{
8486 __ fld(as_FloatRegister($dst$$reg), Address(sp, $src$$disp));
8487 %}
8488
8489 ins_pipe(fp_load_mem_d);
8490
8491 %}
8492
8493 instruct MoveF2I_reg_stack(stackSlotI dst, fRegF src) %{
8494
8495 match(Set dst (MoveF2I src));
8496
8497 effect(DEF dst, USE src);
8498
8499 ins_cost(STORE_COST);
8500
8501 format %{ "fsw $src, $dst\t#@MoveF2I_reg_stack" %}
8502
8503 ins_encode %{
8504 __ fsw(as_FloatRegister($src$$reg), Address(sp, $dst$$disp));
8505 %}
8506
8507 ins_pipe(fp_store_reg_s);
8508
8509 %}
8510
8511 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{
8512
8513 match(Set dst (MoveI2F src));
8514
8515 effect(DEF dst, USE src);
8516
8517 ins_cost(STORE_COST);
8518
8519 format %{ "sw $src, $dst\t#@MoveI2F_reg_stack" %}
8520
8521 ins_encode %{
8522 __ sw(as_Register($src$$reg), Address(sp, $dst$$disp));
8523 %}
8524
8525 ins_pipe(istore_reg_reg);
8526
8527 %}
8528
8529 instruct MoveD2L_reg_stack(stackSlotL dst, fRegD src) %{
8530
8531 match(Set dst (MoveD2L src));
8532
8533 effect(DEF dst, USE src);
8534
8535 ins_cost(STORE_COST);
8536
8537 format %{ "fsd $dst, $src\t#@MoveD2L_reg_stack" %}
8538
8539 ins_encode %{
8540 __ fsd(as_FloatRegister($src$$reg), Address(sp, $dst$$disp));
8541 %}
8542
8543 ins_pipe(fp_store_reg_d);
8544
8545 %}
8546
8547 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{
8548
8549 match(Set dst (MoveL2D src));
8550
8551 effect(DEF dst, USE src);
8552
8553 ins_cost(STORE_COST);
8554
8555 format %{ "sd $src, $dst\t#@MoveL2D_reg_stack" %}
8556
8557 ins_encode %{
8558 __ sd(as_Register($src$$reg), Address(sp, $dst$$disp));
8559 %}
8560
8561 ins_pipe(istore_reg_reg);
8562
8563 %}
8564
8565 instruct MoveF2I_reg_reg(iRegINoSp dst, fRegF src) %{
8566
8567 match(Set dst (MoveF2I src));
8568
8569 effect(DEF dst, USE src);
8570
8571 ins_cost(XFER_COST);
8572
8573 format %{ "fmv.x.w $dst, $src\t#@MoveL2D_reg_stack" %}
8574
8575 ins_encode %{
8576 __ fmv_x_w(as_Register($dst$$reg), as_FloatRegister($src$$reg));
8577 %}
8578
8579 ins_pipe(fp_f2i);
8580
8581 %}
8582
8583 instruct MoveI2F_reg_reg(fRegF dst, iRegI src) %{
8584
8585 match(Set dst (MoveI2F src));
8586
8587 effect(DEF dst, USE src);
8588
8589 ins_cost(XFER_COST);
8590
8591 format %{ "fmv.w.x $dst, $src\t#@MoveI2F_reg_reg" %}
8592
8593 ins_encode %{
8594 __ fmv_w_x(as_FloatRegister($dst$$reg), as_Register($src$$reg));
8595 %}
8596
8597 ins_pipe(fp_i2f);
8598
8599 %}
8600
8601 instruct MoveD2L_reg_reg(iRegLNoSp dst, fRegD src) %{
8602
8603 match(Set dst (MoveD2L src));
8604
8605 effect(DEF dst, USE src);
8606
8607 ins_cost(XFER_COST);
8608
8609 format %{ "fmv.x.d $dst, $src\t#@MoveD2L_reg_reg" %}
8610
8611 ins_encode %{
8612 __ fmv_x_d(as_Register($dst$$reg), as_FloatRegister($src$$reg));
8613 %}
8614
8615 ins_pipe(fp_d2l);
8616
8617 %}
8618
8619 instruct MoveL2D_reg_reg(fRegD dst, iRegL src) %{
8620
8621 match(Set dst (MoveL2D src));
8622
8623 effect(DEF dst, USE src);
8624
8625 ins_cost(XFER_COST);
8626
8627 format %{ "fmv.d.x $dst, $src\t#@MoveD2L_reg_reg" %}
8628
8629 ins_encode %{
8630 __ fmv_d_x(as_FloatRegister($dst$$reg), as_Register($src$$reg));
8631 %}
8632
8633 ins_pipe(fp_l2d);
8634
8635 %}
8636
8637 // ============================================================================
8638 // Compare Instructions which set the result float comparisons in dest register.
8639
8640 instruct cmpF3_reg_reg(iRegINoSp dst, fRegF op1, fRegF op2)
8641 %{
8642 match(Set dst (CmpF3 op1 op2));
8643
8644 ins_cost(XFER_COST * 2 + BRANCH_COST + ALU_COST);
8645 format %{ "flt.s $dst, $op2, $op1\t#@cmpF3_reg_reg\n\t"
8646 "bgtz $dst, done\n\t"
8647 "feq.s $dst, $op1, $op2\n\t"
8648 "addi $dst, $dst, -1\t#@cmpF3_reg_reg"
8649 %}
8650
8651 ins_encode %{
8652 // we want -1 for unordered or less than, 0 for equal and 1 for greater than.
8653 __ float_compare(as_Register($dst$$reg), as_FloatRegister($op1$$reg),
8654 as_FloatRegister($op2$$reg), -1 /*unordered_result < 0*/);
8655 %}
8656
8657 ins_pipe(pipe_class_default);
8658 %}
8659
8660 instruct cmpD3_reg_reg(iRegINoSp dst, fRegD op1, fRegD op2)
8661 %{
8662 match(Set dst (CmpD3 op1 op2));
8663
8664 ins_cost(XFER_COST * 2 + BRANCH_COST + ALU_COST);
8665 format %{ "flt.d $dst, $op2, $op1\t#@cmpD3_reg_reg\n\t"
8666 "bgtz $dst, done\n\t"
8667 "feq.d $dst, $op1, $op2\n\t"
8668 "addi $dst, $dst, -1\t#@cmpD3_reg_reg"
8669 %}
8670
8671 ins_encode %{
8672 // we want -1 for unordered or less than, 0 for equal and 1 for greater than.
8673 __ double_compare(as_Register($dst$$reg), as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg), -1 /*unordered_result < 0*/);
8674 %}
8675
8676 ins_pipe(pipe_class_default);
8677 %}
8678
8679 instruct cmpL3_reg_reg(iRegINoSp dst, iRegL op1, iRegL op2)
8680 %{
8681 match(Set dst (CmpL3 op1 op2));
8682
8683 ins_cost(ALU_COST * 3 + BRANCH_COST);
8684 format %{ "slt $dst, $op2, $op1\t#@cmpL3_reg_reg\n\t"
8685 "bnez $dst, done\n\t"
8686 "slt $dst, $op1, $op2\n\t"
8687 "neg $dst, $dst\t#@cmpL3_reg_reg"
8688 %}
8689 ins_encode %{
8690 __ cmp_l2i(t0, as_Register($op1$$reg), as_Register($op2$$reg));
8691 __ mv(as_Register($dst$$reg), t0);
8692 %}
8693
8694 ins_pipe(pipe_class_default);
8695 %}
8696
8697 instruct cmpLTMask_reg_reg(iRegINoSp dst, iRegI p, iRegI q)
8698 %{
8699 match(Set dst (CmpLTMask p q));
8700
8701 ins_cost(2 * ALU_COST);
8702
8703 format %{ "slt $dst, $p, $q\t#@cmpLTMask_reg_reg\n\t"
8704 "subw $dst, zr, $dst\t#@cmpLTMask_reg_reg"
8705 %}
8706
8707 ins_encode %{
8708 __ slt(as_Register($dst$$reg), as_Register($p$$reg), as_Register($q$$reg));
8709 __ subw(as_Register($dst$$reg), zr, as_Register($dst$$reg));
8710 %}
8711
8712 ins_pipe(ialu_reg_reg);
8713 %}
8714
8715 instruct cmpLTMask_reg_zero(iRegINoSp dst, iRegIorL2I op, immI0 zero)
8716 %{
8717 match(Set dst (CmpLTMask op zero));
8718
8719 ins_cost(ALU_COST);
8720
8721 format %{ "sraiw $dst, $dst, 31\t#@cmpLTMask_reg_reg" %}
8722
8723 ins_encode %{
8724 __ sraiw(as_Register($dst$$reg), as_Register($op$$reg), 31);
8725 %}
8726
8727 ins_pipe(ialu_reg_shift);
8728 %}
8729
8730
8731 // ============================================================================
8732 // Max and Min
8733
8734 instruct minI_reg_reg(iRegINoSp dst, iRegI src)
8735 %{
8736 match(Set dst (MinI dst src));
8737
8738 ins_cost(BRANCH_COST + ALU_COST);
8739 format %{
8740 "ble $dst, $src, skip\t#@minI_reg_reg\n\t"
8741 "mv $dst, $src\n\t"
8742 "skip:"
8743 %}
8744
8745 ins_encode %{
8746 Label Lskip;
8747 __ ble(as_Register($dst$$reg), as_Register($src$$reg), Lskip);
8748 __ mv(as_Register($dst$$reg), as_Register($src$$reg));
8749 __ bind(Lskip);
8750 %}
8751
8752 ins_pipe(pipe_class_compare);
8753 %}
8754
8755 instruct maxI_reg_reg(iRegINoSp dst, iRegI src)
8756 %{
8757 match(Set dst (MaxI dst src));
8758
8759 ins_cost(BRANCH_COST + ALU_COST);
8760 format %{
8761 "bge $dst, $src, skip\t#@maxI_reg_reg\n\t"
8762 "mv $dst, $src\n\t"
8763 "skip:"
8764 %}
8765
8766 ins_encode %{
8767 Label Lskip;
8768 __ bge(as_Register($dst$$reg), as_Register($src$$reg), Lskip);
8769 __ mv(as_Register($dst$$reg), as_Register($src$$reg));
8770 __ bind(Lskip);
8771 %}
8772
8773 ins_pipe(pipe_class_compare);
8774 %}
8775
8776 // special case for comparing with zero
8777 // n.b. this is selected in preference to the rule above because it
8778 // avoids loading constant 0 into a source register
8779
8780 instruct minI_reg_zero(iRegINoSp dst, immI0 zero)
8781 %{
8782 match(Set dst (MinI dst zero));
8783 match(Set dst (MinI zero dst));
8784
8785 ins_cost(BRANCH_COST + ALU_COST);
8786 format %{
8787 "blez $dst, skip\t#@minI_reg_zero\n\t"
8788 "mv $dst, zr\n\t"
8789 "skip:"
8790 %}
8791
8792 ins_encode %{
8793 Label Lskip;
8794 __ blez(as_Register($dst$$reg), Lskip);
8795 __ mv(as_Register($dst$$reg), zr);
8796 __ bind(Lskip);
8797 %}
8798
8799 ins_pipe(pipe_class_compare);
8800 %}
8801
8802 instruct maxI_reg_zero(iRegINoSp dst, immI0 zero)
8803 %{
8804 match(Set dst (MaxI dst zero));
8805 match(Set dst (MaxI zero dst));
8806
8807 ins_cost(BRANCH_COST + ALU_COST);
8808 format %{
8809 "bgez $dst, skip\t#@maxI_reg_zero\n\t"
8810 "mv $dst, zr\n\t"
8811 "skip:"
8812 %}
8813
8814 ins_encode %{
8815 Label Lskip;
8816 __ bgez(as_Register($dst$$reg), Lskip);
8817 __ mv(as_Register($dst$$reg), zr);
8818 __ bind(Lskip);
8819 %}
8820
8821 ins_pipe(pipe_class_compare);
8822 %}
8823
8824 instruct minI_rReg(iRegINoSp dst, iRegI src1, iRegI src2)
8825 %{
8826 match(Set dst (MinI src1 src2));
8827
8828 effect(DEF dst, USE src1, USE src2);
8829
8830 ins_cost(BRANCH_COST + ALU_COST * 2);
8831 format %{
8832 "ble $src1, $src2, Lsrc1.\t#@minI_rReg\n\t"
8833 "mv $dst, $src2\n\t"
8834 "j Ldone\n\t"
8835 "bind Lsrc1\n\t"
8836 "mv $dst, $src1\n\t"
8837 "bind\t#@minI_rReg"
8838 %}
8839
8840 ins_encode %{
8841 Label Lsrc1, Ldone;
8842 __ ble(as_Register($src1$$reg), as_Register($src2$$reg), Lsrc1);
8843 __ mv(as_Register($dst$$reg), as_Register($src2$$reg));
8844 __ j(Ldone);
8845 __ bind(Lsrc1);
8846 __ mv(as_Register($dst$$reg), as_Register($src1$$reg));
8847 __ bind(Ldone);
8848 %}
8849
8850 ins_pipe(pipe_class_compare);
8851 %}
8852
8853 instruct maxI_rReg(iRegINoSp dst, iRegI src1, iRegI src2)
8854 %{
8855 match(Set dst (MaxI src1 src2));
8856
8857 effect(DEF dst, USE src1, USE src2);
8858
8859 ins_cost(BRANCH_COST + ALU_COST * 2);
8860 format %{
8861 "bge $src1, $src2, Lsrc1\t#@maxI_rReg\n\t"
8862 "mv $dst, $src2\n\t"
8863 "j Ldone\n\t"
8864 "bind Lsrc1\n\t"
8865 "mv $dst, $src1\n\t"
8866 "bind\t#@maxI_rReg"
8867 %}
8868
8869 ins_encode %{
8870 Label Lsrc1, Ldone;
8871 __ bge(as_Register($src1$$reg), as_Register($src2$$reg), Lsrc1);
8872 __ mv(as_Register($dst$$reg), as_Register($src2$$reg));
8873 __ j(Ldone);
8874 __ bind(Lsrc1);
8875 __ mv(as_Register($dst$$reg), as_Register($src1$$reg));
8876 __ bind(Ldone);
8877
8878 %}
8879
8880 ins_pipe(pipe_class_compare);
8881 %}
8882
8883 // ============================================================================
8884 // Branch Instructions
8885 // Direct Branch.
8886 instruct branch(label lbl)
8887 %{
8888 match(Goto);
8889
8890 effect(USE lbl);
8891
8892 ins_cost(BRANCH_COST);
8893 format %{ "j $lbl\t#@branch" %}
8894
8895 ins_encode(riscv_enc_j(lbl));
8896
8897 ins_pipe(pipe_branch);
8898 %}
8899
8900 // ============================================================================
8901 // Compare and Branch Instructions
8902
8903 // Patterns for short (< 12KiB) variants
8904
8905 // Compare flags and branch near instructions.
8906 instruct cmpFlag_branch(cmpOpEqNe cmp, rFlagsReg cr, label lbl) %{
8907 match(If cmp cr);
8908 effect(USE lbl);
8909
8910 ins_cost(BRANCH_COST);
8911 format %{ "b$cmp $cr, zr, $lbl\t#@cmpFlag_branch" %}
8912
8913 ins_encode %{
8914 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($cr$$reg), *($lbl$$label));
8915 %}
8916 ins_pipe(pipe_cmpz_branch);
8917 ins_short_branch(1);
8918 %}
8919
8920 // Compare signed int and branch near instructions
8921 instruct cmpI_branch(cmpOp cmp, iRegI op1, iRegI op2, label lbl)
8922 %{
8923 // Same match rule as `far_cmpI_branch'.
8924 match(If cmp (CmpI op1 op2));
8925
8926 effect(USE lbl);
8927
8928 ins_cost(BRANCH_COST);
8929
8930 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpI_branch" %}
8931
8932 ins_encode %{
8933 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label));
8934 %}
8935
8936 ins_pipe(pipe_cmp_branch);
8937 ins_short_branch(1);
8938 %}
8939
8940 instruct cmpI_loop(cmpOp cmp, iRegI op1, iRegI op2, label lbl)
8941 %{
8942 // Same match rule as `far_cmpI_loop'.
8943 match(CountedLoopEnd cmp (CmpI op1 op2));
8944
8945 effect(USE lbl);
8946
8947 ins_cost(BRANCH_COST);
8948
8949 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpI_loop" %}
8950
8951 ins_encode %{
8952 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label));
8953 %}
8954
8955 ins_pipe(pipe_cmp_branch);
8956 ins_short_branch(1);
8957 %}
8958
8959 // Compare unsigned int and branch near instructions
8960 instruct cmpU_branch(cmpOpU cmp, iRegI op1, iRegI op2, label lbl)
8961 %{
8962 // Same match rule as `far_cmpU_branch'.
8963 match(If cmp (CmpU op1 op2));
8964
8965 effect(USE lbl);
8966
8967 ins_cost(BRANCH_COST);
8968
8969 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpU_branch" %}
8970
8971 ins_encode %{
8972 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
8973 as_Register($op2$$reg), *($lbl$$label));
8974 %}
8975
8976 ins_pipe(pipe_cmp_branch);
8977 ins_short_branch(1);
8978 %}
8979
8980 instruct cmpU_loop(cmpOpU cmp, iRegI op1, iRegI op2, label lbl)
8981 %{
8982 // Same match rule as `far_cmpU_loop'.
8983 match(CountedLoopEnd cmp (CmpU op1 op2));
8984
8985 effect(USE lbl);
8986
8987 ins_cost(BRANCH_COST);
8988
8989 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpU_loop" %}
8990
8991 ins_encode %{
8992 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
8993 as_Register($op2$$reg), *($lbl$$label));
8994 %}
8995
8996 ins_pipe(pipe_cmp_branch);
8997 ins_short_branch(1);
8998 %}
8999
9000 // Compare signed long and branch near instructions
9001 instruct cmpL_branch(cmpOp cmp, iRegL op1, iRegL op2, label lbl)
9002 %{
9003 // Same match rule as `far_cmpL_branch'.
9004 match(If cmp (CmpL op1 op2));
9005
9006 effect(USE lbl);
9007
9008 ins_cost(BRANCH_COST);
9009
9010 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpL_branch" %}
9011
9012 ins_encode %{
9013 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label));
9014 %}
9015
9016 ins_pipe(pipe_cmp_branch);
9017 ins_short_branch(1);
9018 %}
9019
9020 instruct cmpL_loop(cmpOp cmp, iRegL op1, iRegL op2, label lbl)
9021 %{
9022 // Same match rule as `far_cmpL_loop'.
9023 match(CountedLoopEnd cmp (CmpL op1 op2));
9024
9025 effect(USE lbl);
9026
9027 ins_cost(BRANCH_COST);
9028
9029 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpL_loop" %}
9030
9031 ins_encode %{
9032 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label));
9033 %}
9034
9035 ins_pipe(pipe_cmp_branch);
9036 ins_short_branch(1);
9037 %}
9038
9039 // Compare unsigned long and branch near instructions
9040 instruct cmpUL_branch(cmpOpU cmp, iRegL op1, iRegL op2, label lbl)
9041 %{
9042 // Same match rule as `far_cmpUL_branch'.
9043 match(If cmp (CmpUL op1 op2));
9044
9045 effect(USE lbl);
9046
9047 ins_cost(BRANCH_COST);
9048 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpUL_branch" %}
9049
9050 ins_encode %{
9051 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9052 as_Register($op2$$reg), *($lbl$$label));
9053 %}
9054
9055 ins_pipe(pipe_cmp_branch);
9056 ins_short_branch(1);
9057 %}
9058
9059 instruct cmpUL_loop(cmpOpU cmp, iRegL op1, iRegL op2, label lbl)
9060 %{
9061 // Same match rule as `far_cmpUL_loop'.
9062 match(CountedLoopEnd cmp (CmpUL op1 op2));
9063
9064 effect(USE lbl);
9065
9066 ins_cost(BRANCH_COST);
9067 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpUL_loop" %}
9068
9069 ins_encode %{
9070 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9071 as_Register($op2$$reg), *($lbl$$label));
9072 %}
9073
9074 ins_pipe(pipe_cmp_branch);
9075 ins_short_branch(1);
9076 %}
9077
9078 // Compare pointer and branch near instructions
9079 instruct cmpP_branch(cmpOpU cmp, iRegP op1, iRegP op2, label lbl)
9080 %{
9081 // Same match rule as `far_cmpP_branch'.
9082 match(If cmp (CmpP op1 op2));
9083
9084 effect(USE lbl);
9085
9086 ins_cost(BRANCH_COST);
9087
9088 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpP_branch" %}
9089
9090 ins_encode %{
9091 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9092 as_Register($op2$$reg), *($lbl$$label));
9093 %}
9094
9095 ins_pipe(pipe_cmp_branch);
9096 ins_short_branch(1);
9097 %}
9098
9099 instruct cmpP_loop(cmpOpU cmp, iRegP op1, iRegP op2, label lbl)
9100 %{
9101 // Same match rule as `far_cmpP_loop'.
9102 match(CountedLoopEnd cmp (CmpP op1 op2));
9103
9104 effect(USE lbl);
9105
9106 ins_cost(BRANCH_COST);
9107
9108 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpP_loop" %}
9109
9110 ins_encode %{
9111 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9112 as_Register($op2$$reg), *($lbl$$label));
9113 %}
9114
9115 ins_pipe(pipe_cmp_branch);
9116 ins_short_branch(1);
9117 %}
9118
9119 // Compare narrow pointer and branch near instructions
9120 instruct cmpN_branch(cmpOpU cmp, iRegN op1, iRegN op2, label lbl)
9121 %{
9122 // Same match rule as `far_cmpN_branch'.
9123 match(If cmp (CmpN op1 op2));
9124
9125 effect(USE lbl);
9126
9127 ins_cost(BRANCH_COST);
9128
9129 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpN_branch" %}
9130
9131 ins_encode %{
9132 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9133 as_Register($op2$$reg), *($lbl$$label));
9134 %}
9135
9136 ins_pipe(pipe_cmp_branch);
9137 ins_short_branch(1);
9138 %}
9139
9140 instruct cmpN_loop(cmpOpU cmp, iRegN op1, iRegN op2, label lbl)
9141 %{
9142 // Same match rule as `far_cmpN_loop'.
9143 match(CountedLoopEnd cmp (CmpN op1 op2));
9144
9145 effect(USE lbl);
9146
9147 ins_cost(BRANCH_COST);
9148
9149 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpN_loop" %}
9150
9151 ins_encode %{
9152 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9153 as_Register($op2$$reg), *($lbl$$label));
9154 %}
9155
9156 ins_pipe(pipe_cmp_branch);
9157 ins_short_branch(1);
9158 %}
9159
9160 // Compare float and branch near instructions
9161 instruct cmpF_branch(cmpOp cmp, fRegF op1, fRegF op2, label lbl)
9162 %{
9163 // Same match rule as `far_cmpF_branch'.
9164 match(If cmp (CmpF op1 op2));
9165
9166 effect(USE lbl);
9167
9168 ins_cost(XFER_COST + BRANCH_COST);
9169 format %{ "float_b$cmp $op1, $op2, $lbl \t#@cmpF_branch"%}
9170
9171 ins_encode %{
9172 __ float_cmp_branch($cmp$$cmpcode, as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg), *($lbl$$label));
9173 %}
9174
9175 ins_pipe(pipe_class_compare);
9176 ins_short_branch(1);
9177 %}
9178
9179 instruct cmpF_loop(cmpOp cmp, fRegF op1, fRegF op2, label lbl)
9180 %{
9181 // Same match rule as `far_cmpF_loop'.
9182 match(CountedLoopEnd cmp (CmpF op1 op2));
9183 effect(USE lbl);
9184
9185 ins_cost(XFER_COST + BRANCH_COST);
9186 format %{ "float_b$cmp $op1, $op2, $lbl\t#@cmpF_loop"%}
9187
9188 ins_encode %{
9189 __ float_cmp_branch($cmp$$cmpcode, as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg), *($lbl$$label));
9190 %}
9191
9192 ins_pipe(pipe_class_compare);
9193 ins_short_branch(1);
9194 %}
9195
9196 // Compare double and branch near instructions
9197 instruct cmpD_branch(cmpOp cmp, fRegD op1, fRegD op2, label lbl)
9198 %{
9199 // Same match rule as `far_cmpD_branch'.
9200 match(If cmp (CmpD op1 op2));
9201 effect(USE lbl);
9202
9203 ins_cost(XFER_COST + BRANCH_COST);
9204 format %{ "double_b$cmp $op1, $op2, $lbl\t#@cmpD_branch"%}
9205
9206 ins_encode %{
9207 __ float_cmp_branch($cmp$$cmpcode | C2_MacroAssembler::double_branch_mask, as_FloatRegister($op1$$reg),
9208 as_FloatRegister($op2$$reg), *($lbl$$label));
9209 %}
9210
9211 ins_pipe(pipe_class_compare);
9212 ins_short_branch(1);
9213 %}
9214
9215 instruct cmpD_loop(cmpOp cmp, fRegD op1, fRegD op2, label lbl)
9216 %{
9217 // Same match rule as `far_cmpD_loop'.
9218 match(CountedLoopEnd cmp (CmpD op1 op2));
9219 effect(USE lbl);
9220
9221 ins_cost(XFER_COST + BRANCH_COST);
9222 format %{ "double_b$cmp $op1, $op2, $lbl\t#@cmpD_loop"%}
9223
9224 ins_encode %{
9225 __ float_cmp_branch($cmp$$cmpcode | C2_MacroAssembler::double_branch_mask, as_FloatRegister($op1$$reg),
9226 as_FloatRegister($op2$$reg), *($lbl$$label));
9227 %}
9228
9229 ins_pipe(pipe_class_compare);
9230 ins_short_branch(1);
9231 %}
9232
9233 // Compare signed int with zero and branch near instructions
9234 instruct cmpI_reg_imm0_branch(cmpOp cmp, iRegI op1, immI0 zero, label lbl)
9235 %{
9236 // Same match rule as `far_cmpI_reg_imm0_branch'.
9237 match(If cmp (CmpI op1 zero));
9238
9239 effect(USE op1, USE lbl);
9240
9241 ins_cost(BRANCH_COST);
9242 format %{ "b$cmp $op1, zr, $lbl\t#@cmpI_reg_imm0_branch" %}
9243
9244 ins_encode %{
9245 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label));
9246 %}
9247
9248 ins_pipe(pipe_cmpz_branch);
9249 ins_short_branch(1);
9250 %}
9251
9252 instruct cmpI_reg_imm0_loop(cmpOp cmp, iRegI op1, immI0 zero, label lbl)
9253 %{
9254 // Same match rule as `far_cmpI_reg_imm0_loop'.
9255 match(CountedLoopEnd cmp (CmpI op1 zero));
9256
9257 effect(USE op1, USE lbl);
9258
9259 ins_cost(BRANCH_COST);
9260
9261 format %{ "b$cmp $op1, zr, $lbl\t#@cmpI_reg_imm0_loop" %}
9262
9263 ins_encode %{
9264 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label));
9265 %}
9266
9267 ins_pipe(pipe_cmpz_branch);
9268 ins_short_branch(1);
9269 %}
9270
9271 // Compare unsigned int with zero and branch near instructions
9272 instruct cmpUEqNeLeGt_reg_imm0_branch(cmpOpUEqNeLeGt cmp, iRegI op1, immI0 zero, label lbl)
9273 %{
9274 // Same match rule as `far_cmpUEqNeLeGt_reg_imm0_branch'.
9275 match(If cmp (CmpU op1 zero));
9276
9277 effect(USE op1, USE lbl);
9278
9279 ins_cost(BRANCH_COST);
9280
9281 format %{ "b$cmp $op1, zr, $lbl\t#@cmpUEqNeLeGt_reg_imm0_branch" %}
9282
9283 ins_encode %{
9284 __ enc_cmpUEqNeLeGt_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
9285 %}
9286
9287 ins_pipe(pipe_cmpz_branch);
9288 ins_short_branch(1);
9289 %}
9290
9291 instruct cmpUEqNeLeGt_reg_imm0_loop(cmpOpUEqNeLeGt cmp, iRegI op1, immI0 zero, label lbl)
9292 %{
9293 // Same match rule as `far_cmpUEqNeLeGt_reg_imm0_loop'.
9294 match(CountedLoopEnd cmp (CmpU op1 zero));
9295
9296 effect(USE op1, USE lbl);
9297
9298 ins_cost(BRANCH_COST);
9299
9300 format %{ "b$cmp $op1, zr, $lbl\t#@cmpUEqNeLeGt_reg_imm0_loop" %}
9301
9302
9303 ins_encode %{
9304 __ enc_cmpUEqNeLeGt_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
9305 %}
9306
9307 ins_pipe(pipe_cmpz_branch);
9308 ins_short_branch(1);
9309 %}
9310
9311 // Compare signed long with zero and branch near instructions
9312 instruct cmpL_reg_imm0_branch(cmpOp cmp, iRegL op1, immL0 zero, label lbl)
9313 %{
9314 // Same match rule as `far_cmpL_reg_imm0_branch'.
9315 match(If cmp (CmpL op1 zero));
9316
9317 effect(USE op1, USE lbl);
9318
9319 ins_cost(BRANCH_COST);
9320
9321 format %{ "b$cmp $op1, zr, $lbl\t#@cmpL_reg_imm0_branch" %}
9322
9323 ins_encode %{
9324 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label));
9325 %}
9326
9327 ins_pipe(pipe_cmpz_branch);
9328 ins_short_branch(1);
9329 %}
9330
9331 instruct cmpL_reg_imm0_loop(cmpOp cmp, iRegL op1, immL0 zero, label lbl)
9332 %{
9333 // Same match rule as `far_cmpL_reg_imm0_loop'.
9334 match(CountedLoopEnd cmp (CmpL op1 zero));
9335
9336 effect(USE op1, USE lbl);
9337
9338 ins_cost(BRANCH_COST);
9339
9340 format %{ "b$cmp $op1, zr, $lbl\t#@cmpL_reg_imm0_loop" %}
9341
9342 ins_encode %{
9343 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label));
9344 %}
9345
9346 ins_pipe(pipe_cmpz_branch);
9347 ins_short_branch(1);
9348 %}
9349
9350 // Compare unsigned long with zero and branch near instructions
9351 instruct cmpULEqNeLeGt_reg_imm0_branch(cmpOpUEqNeLeGt cmp, iRegL op1, immL0 zero, label lbl)
9352 %{
9353 // Same match rule as `far_cmpULEqNeLeGt_reg_imm0_branch'.
9354 match(If cmp (CmpUL op1 zero));
9355
9356 effect(USE op1, USE lbl);
9357
9358 ins_cost(BRANCH_COST);
9359
9360 format %{ "b$cmp $op1, zr, $lbl\t#@cmpULEqNeLeGt_reg_imm0_branch" %}
9361
9362 ins_encode %{
9363 __ enc_cmpUEqNeLeGt_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
9364 %}
9365
9366 ins_pipe(pipe_cmpz_branch);
9367 ins_short_branch(1);
9368 %}
9369
9370 instruct cmpULEqNeLeGt_reg_imm0_loop(cmpOpUEqNeLeGt cmp, iRegL op1, immL0 zero, label lbl)
9371 %{
9372 // Same match rule as `far_cmpULEqNeLeGt_reg_imm0_loop'.
9373 match(CountedLoopEnd cmp (CmpUL op1 zero));
9374
9375 effect(USE op1, USE lbl);
9376
9377 ins_cost(BRANCH_COST);
9378
9379 format %{ "b$cmp $op1, zr, $lbl\t#@cmpULEqNeLeGt_reg_imm0_loop" %}
9380
9381 ins_encode %{
9382 __ enc_cmpUEqNeLeGt_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
9383 %}
9384
9385 ins_pipe(pipe_cmpz_branch);
9386 ins_short_branch(1);
9387 %}
9388
9389 // Compare pointer with zero and branch near instructions
9390 instruct cmpP_imm0_branch(cmpOpEqNe cmp, iRegP op1, immP0 zero, label lbl) %{
9391 // Same match rule as `far_cmpP_reg_imm0_branch'.
9392 match(If cmp (CmpP op1 zero));
9393 effect(USE lbl);
9394
9395 ins_cost(BRANCH_COST);
9396 format %{ "b$cmp $op1, zr, $lbl\t#@cmpP_imm0_branch" %}
9397
9398 ins_encode %{
9399 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
9400 %}
9401
9402 ins_pipe(pipe_cmpz_branch);
9403 ins_short_branch(1);
9404 %}
9405
9406 instruct cmpP_imm0_loop(cmpOpEqNe cmp, iRegP op1, immP0 zero, label lbl) %{
9407 // Same match rule as `far_cmpP_reg_imm0_loop'.
9408 match(CountedLoopEnd cmp (CmpP op1 zero));
9409 effect(USE lbl);
9410
9411 ins_cost(BRANCH_COST);
9412 format %{ "b$cmp $op1, zr, $lbl\t#@cmpP_imm0_loop" %}
9413
9414 ins_encode %{
9415 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
9416 %}
9417
9418 ins_pipe(pipe_cmpz_branch);
9419 ins_short_branch(1);
9420 %}
9421
9422 // Compare narrow pointer with zero and branch near instructions
9423 instruct cmpN_imm0_branch(cmpOpEqNe cmp, iRegN op1, immN0 zero, label lbl) %{
9424 // Same match rule as `far_cmpN_reg_imm0_branch'.
9425 match(If cmp (CmpN op1 zero));
9426 effect(USE lbl);
9427
9428 ins_cost(BRANCH_COST);
9429
9430 format %{ "b$cmp $op1, zr, $lbl\t#@cmpN_imm0_branch" %}
9431
9432 ins_encode %{
9433 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
9434 %}
9435
9436 ins_pipe(pipe_cmpz_branch);
9437 ins_short_branch(1);
9438 %}
9439
9440 instruct cmpN_imm0_loop(cmpOpEqNe cmp, iRegN op1, immN0 zero, label lbl) %{
9441 // Same match rule as `far_cmpN_reg_imm0_loop'.
9442 match(CountedLoopEnd cmp (CmpN op1 zero));
9443 effect(USE lbl);
9444
9445 ins_cost(BRANCH_COST);
9446
9447 format %{ "b$cmp $op1, zr, $lbl\t#@cmpN_imm0_loop" %}
9448
9449 ins_encode %{
9450 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
9451 %}
9452
9453 ins_pipe(pipe_cmpz_branch);
9454 ins_short_branch(1);
9455 %}
9456
9457 // Compare narrow pointer with pointer zero and branch near instructions
9458 instruct cmpP_narrowOop_imm0_branch(cmpOpEqNe cmp, iRegN op1, immP0 zero, label lbl) %{
9459 // Same match rule as `far_cmpP_narrowOop_imm0_branch'.
9460 match(If cmp (CmpP (DecodeN op1) zero));
9461 effect(USE lbl);
9462
9463 ins_cost(BRANCH_COST);
9464 format %{ "b$cmp $op1, zr, $lbl\t#@cmpP_narrowOop_imm0_branch" %}
9465
9466 ins_encode %{
9467 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
9468 %}
9469
9470 ins_pipe(pipe_cmpz_branch);
9471 ins_short_branch(1);
9472 %}
9473
9474 instruct cmpP_narrowOop_imm0_loop(cmpOpEqNe cmp, iRegN op1, immP0 zero, label lbl) %{
9475 // Same match rule as `far_cmpP_narrowOop_imm0_loop'.
9476 match(CountedLoopEnd cmp (CmpP (DecodeN op1) zero));
9477 effect(USE lbl);
9478
9479 ins_cost(BRANCH_COST);
9480 format %{ "b$cmp $op1, zr, $lbl\t#@cmpP_narrowOop_imm0_loop" %}
9481
9482 ins_encode %{
9483 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
9484 %}
9485
9486 ins_pipe(pipe_cmpz_branch);
9487 ins_short_branch(1);
9488 %}
9489
9490 // Patterns for far (20KiB) variants
9491
9492 instruct far_cmpFlag_branch(cmpOp cmp, rFlagsReg cr, label lbl) %{
9493 match(If cmp cr);
9494 effect(USE lbl);
9495
9496 ins_cost(BRANCH_COST);
9497 format %{ "far_b$cmp $cr, zr, $lbl\t#@far_cmpFlag_branch"%}
9498
9499 ins_encode %{
9500 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($cr$$reg), *($lbl$$label), /* is_far */ true);
9501 %}
9502
9503 ins_pipe(pipe_cmpz_branch);
9504 %}
9505
9506 // Compare signed int and branch far instructions
9507 instruct far_cmpI_branch(cmpOp cmp, iRegI op1, iRegI op2, label lbl) %{
9508 match(If cmp (CmpI op1 op2));
9509 effect(USE lbl);
9510
9511 ins_cost(BRANCH_COST * 2);
9512
9513 // the format instruction [far_b$cmp] here is be used as two insructions
9514 // in macroassembler: b$not_cmp(op1, op2, done), j($lbl), bind(done)
9515 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpI_branch" %}
9516
9517 ins_encode %{
9518 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9519 %}
9520
9521 ins_pipe(pipe_cmp_branch);
9522 %}
9523
9524 instruct far_cmpI_loop(cmpOp cmp, iRegI op1, iRegI op2, label lbl) %{
9525 match(CountedLoopEnd cmp (CmpI op1 op2));
9526 effect(USE lbl);
9527
9528 ins_cost(BRANCH_COST * 2);
9529 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpI_loop" %}
9530
9531 ins_encode %{
9532 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9533 %}
9534
9535 ins_pipe(pipe_cmp_branch);
9536 %}
9537
9538 instruct far_cmpU_branch(cmpOpU cmp, iRegI op1, iRegI op2, label lbl) %{
9539 match(If cmp (CmpU op1 op2));
9540 effect(USE lbl);
9541
9542 ins_cost(BRANCH_COST * 2);
9543 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpU_branch" %}
9544
9545 ins_encode %{
9546 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9547 as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9548 %}
9549
9550 ins_pipe(pipe_cmp_branch);
9551 %}
9552
9553 instruct far_cmpU_loop(cmpOpU cmp, iRegI op1, iRegI op2, label lbl) %{
9554 match(CountedLoopEnd cmp (CmpU op1 op2));
9555 effect(USE lbl);
9556
9557 ins_cost(BRANCH_COST * 2);
9558 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpU_loop" %}
9559
9560 ins_encode %{
9561 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9562 as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9563 %}
9564
9565 ins_pipe(pipe_cmp_branch);
9566 %}
9567
9568 instruct far_cmpL_branch(cmpOp cmp, iRegL op1, iRegL op2, label lbl) %{
9569 match(If cmp (CmpL op1 op2));
9570 effect(USE lbl);
9571
9572 ins_cost(BRANCH_COST * 2);
9573 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpL_branch" %}
9574
9575 ins_encode %{
9576 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9577 %}
9578
9579 ins_pipe(pipe_cmp_branch);
9580 %}
9581
9582 instruct far_cmpLloop(cmpOp cmp, iRegL op1, iRegL op2, label lbl) %{
9583 match(CountedLoopEnd cmp (CmpL op1 op2));
9584 effect(USE lbl);
9585
9586 ins_cost(BRANCH_COST * 2);
9587 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpL_loop" %}
9588
9589 ins_encode %{
9590 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9591 %}
9592
9593 ins_pipe(pipe_cmp_branch);
9594 %}
9595
9596 instruct far_cmpUL_branch(cmpOpU cmp, iRegL op1, iRegL op2, label lbl) %{
9597 match(If cmp (CmpUL op1 op2));
9598 effect(USE lbl);
9599
9600 ins_cost(BRANCH_COST * 2);
9601 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpUL_branch" %}
9602
9603 ins_encode %{
9604 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9605 as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9606 %}
9607
9608 ins_pipe(pipe_cmp_branch);
9609 %}
9610
9611 instruct far_cmpUL_loop(cmpOpU cmp, iRegL op1, iRegL op2, label lbl) %{
9612 match(CountedLoopEnd cmp (CmpUL op1 op2));
9613 effect(USE lbl);
9614
9615 ins_cost(BRANCH_COST * 2);
9616 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpUL_loop" %}
9617
9618 ins_encode %{
9619 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9620 as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9621 %}
9622
9623 ins_pipe(pipe_cmp_branch);
9624 %}
9625
9626 instruct far_cmpP_branch(cmpOpU cmp, iRegP op1, iRegP op2, label lbl)
9627 %{
9628 match(If cmp (CmpP op1 op2));
9629
9630 effect(USE lbl);
9631
9632 ins_cost(BRANCH_COST * 2);
9633
9634 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpP_branch" %}
9635
9636 ins_encode %{
9637 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9638 as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9639 %}
9640
9641 ins_pipe(pipe_cmp_branch);
9642 %}
9643
9644 instruct far_cmpP_loop(cmpOpU cmp, iRegP op1, iRegP op2, label lbl)
9645 %{
9646 match(CountedLoopEnd cmp (CmpP op1 op2));
9647
9648 effect(USE lbl);
9649
9650 ins_cost(BRANCH_COST * 2);
9651
9652 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpP_loop" %}
9653
9654 ins_encode %{
9655 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9656 as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9657 %}
9658
9659 ins_pipe(pipe_cmp_branch);
9660 %}
9661
9662 instruct far_cmpN_branch(cmpOpU cmp, iRegN op1, iRegN op2, label lbl)
9663 %{
9664 match(If cmp (CmpN op1 op2));
9665
9666 effect(USE lbl);
9667
9668 ins_cost(BRANCH_COST * 2);
9669
9670 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpN_branch" %}
9671
9672 ins_encode %{
9673 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9674 as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9675 %}
9676
9677 ins_pipe(pipe_cmp_branch);
9678 %}
9679
9680 instruct far_cmpN_loop(cmpOpU cmp, iRegN op1, iRegN op2, label lbl)
9681 %{
9682 match(CountedLoopEnd cmp (CmpN op1 op2));
9683
9684 effect(USE lbl);
9685
9686 ins_cost(BRANCH_COST * 2);
9687
9688 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpN_loop" %}
9689
9690 ins_encode %{
9691 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9692 as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9693 %}
9694
9695 ins_pipe(pipe_cmp_branch);
9696 %}
9697
9698 // Float compare and branch instructions
9699 instruct far_cmpF_branch(cmpOp cmp, fRegF op1, fRegF op2, label lbl)
9700 %{
9701 match(If cmp (CmpF op1 op2));
9702
9703 effect(USE lbl);
9704
9705 ins_cost(XFER_COST + BRANCH_COST * 2);
9706 format %{ "far_float_b$cmp $op1, $op2, $lbl\t#@far_cmpF_branch"%}
9707
9708 ins_encode %{
9709 __ float_cmp_branch($cmp$$cmpcode, as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg),
9710 *($lbl$$label), /* is_far */ true);
9711 %}
9712
9713 ins_pipe(pipe_class_compare);
9714 %}
9715
9716 instruct far_cmpF_loop(cmpOp cmp, fRegF op1, fRegF op2, label lbl)
9717 %{
9718 match(CountedLoopEnd cmp (CmpF op1 op2));
9719 effect(USE lbl);
9720
9721 ins_cost(XFER_COST + BRANCH_COST * 2);
9722 format %{ "far_float_b$cmp $op1, $op2, $lbl\t#@far_cmpF_loop"%}
9723
9724 ins_encode %{
9725 __ float_cmp_branch($cmp$$cmpcode, as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg),
9726 *($lbl$$label), /* is_far */ true);
9727 %}
9728
9729 ins_pipe(pipe_class_compare);
9730 %}
9731
9732 // Double compare and branch instructions
9733 instruct far_cmpD_branch(cmpOp cmp, fRegD op1, fRegD op2, label lbl)
9734 %{
9735 match(If cmp (CmpD op1 op2));
9736 effect(USE lbl);
9737
9738 ins_cost(XFER_COST + BRANCH_COST * 2);
9739 format %{ "far_double_b$cmp $op1, $op2, $lbl\t#@far_cmpD_branch"%}
9740
9741 ins_encode %{
9742 __ float_cmp_branch($cmp$$cmpcode | C2_MacroAssembler::double_branch_mask, as_FloatRegister($op1$$reg),
9743 as_FloatRegister($op2$$reg), *($lbl$$label), /* is_far */ true);
9744 %}
9745
9746 ins_pipe(pipe_class_compare);
9747 %}
9748
9749 instruct far_cmpD_loop(cmpOp cmp, fRegD op1, fRegD op2, label lbl)
9750 %{
9751 match(CountedLoopEnd cmp (CmpD op1 op2));
9752 effect(USE lbl);
9753
9754 ins_cost(XFER_COST + BRANCH_COST * 2);
9755 format %{ "far_double_b$cmp $op1, $op2, $lbl\t#@far_cmpD_loop"%}
9756
9757 ins_encode %{
9758 __ float_cmp_branch($cmp$$cmpcode | C2_MacroAssembler::double_branch_mask, as_FloatRegister($op1$$reg),
9759 as_FloatRegister($op2$$reg), *($lbl$$label), /* is_far */ true);
9760 %}
9761
9762 ins_pipe(pipe_class_compare);
9763 %}
9764
9765 instruct far_cmpI_reg_imm0_branch(cmpOp cmp, iRegI op1, immI0 zero, label lbl)
9766 %{
9767 match(If cmp (CmpI op1 zero));
9768
9769 effect(USE op1, USE lbl);
9770
9771 ins_cost(BRANCH_COST * 2);
9772
9773 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpI_reg_imm0_branch" %}
9774
9775 ins_encode %{
9776 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label), /* is_far */ true);
9777 %}
9778
9779 ins_pipe(pipe_cmpz_branch);
9780 %}
9781
9782 instruct far_cmpI_reg_imm0_loop(cmpOp cmp, iRegI op1, immI0 zero, label lbl)
9783 %{
9784 match(CountedLoopEnd cmp (CmpI op1 zero));
9785
9786 effect(USE op1, USE lbl);
9787
9788 ins_cost(BRANCH_COST * 2);
9789
9790 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpI_reg_imm0_loop" %}
9791
9792 ins_encode %{
9793 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label), /* is_far */ true);
9794 %}
9795
9796 ins_pipe(pipe_cmpz_branch);
9797 %}
9798
9799 instruct far_cmpUEqNeLeGt_imm0_branch(cmpOpUEqNeLeGt cmp, iRegI op1, immI0 zero, label lbl)
9800 %{
9801 match(If cmp (CmpU op1 zero));
9802
9803 effect(USE op1, USE lbl);
9804
9805 ins_cost(BRANCH_COST * 2);
9806
9807 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpUEqNeLeGt_imm0_branch" %}
9808
9809 ins_encode %{
9810 __ enc_cmpUEqNeLeGt_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
9811 %}
9812
9813 ins_pipe(pipe_cmpz_branch);
9814 %}
9815
9816 instruct far_cmpUEqNeLeGt_reg_imm0_loop(cmpOpUEqNeLeGt cmp, iRegI op1, immI0 zero, label lbl)
9817 %{
9818 match(CountedLoopEnd cmp (CmpU op1 zero));
9819
9820 effect(USE op1, USE lbl);
9821
9822 ins_cost(BRANCH_COST * 2);
9823
9824 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpUEqNeLeGt_reg_imm0_loop" %}
9825
9826
9827 ins_encode %{
9828 __ enc_cmpUEqNeLeGt_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
9829 %}
9830
9831 ins_pipe(pipe_cmpz_branch);
9832 %}
9833
9834 // compare lt/ge unsigned instructs has no short instruct with same match
9835 instruct far_cmpULtGe_reg_imm0_branch(cmpOpULtGe cmp, iRegI op1, immI0 zero, label lbl)
9836 %{
9837 match(If cmp (CmpU op1 zero));
9838
9839 effect(USE op1, USE lbl);
9840
9841 ins_cost(BRANCH_COST);
9842
9843 format %{ "j $lbl if $cmp == ge\t#@far_cmpULtGe_reg_imm0_branch" %}
9844
9845 ins_encode(riscv_enc_far_cmpULtGe_imm0_branch(cmp, op1, lbl));
9846
9847 ins_pipe(pipe_cmpz_branch);
9848 %}
9849
9850 instruct far_cmpULtGe_reg_imm0_loop(cmpOpULtGe cmp, iRegI op1, immI0 zero, label lbl)
9851 %{
9852 match(CountedLoopEnd cmp (CmpU op1 zero));
9853
9854 effect(USE op1, USE lbl);
9855
9856 ins_cost(BRANCH_COST);
9857
9858 format %{ "j $lbl if $cmp == ge\t#@far_cmpULtGe_reg_imm0_loop" %}
9859
9860 ins_encode(riscv_enc_far_cmpULtGe_imm0_branch(cmp, op1, lbl));
9861
9862 ins_pipe(pipe_cmpz_branch);
9863 %}
9864
9865 instruct far_cmpL_reg_imm0_branch(cmpOp cmp, iRegL op1, immL0 zero, label lbl)
9866 %{
9867 match(If cmp (CmpL op1 zero));
9868
9869 effect(USE op1, USE lbl);
9870
9871 ins_cost(BRANCH_COST * 2);
9872
9873 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpL_reg_imm0_branch" %}
9874
9875 ins_encode %{
9876 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label), /* is_far */ true);
9877 %}
9878
9879 ins_pipe(pipe_cmpz_branch);
9880 %}
9881
9882 instruct far_cmpL_reg_imm0_loop(cmpOp cmp, iRegL op1, immL0 zero, label lbl)
9883 %{
9884 match(CountedLoopEnd cmp (CmpL op1 zero));
9885
9886 effect(USE op1, USE lbl);
9887
9888 ins_cost(BRANCH_COST * 2);
9889
9890 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpL_reg_imm0_loop" %}
9891
9892 ins_encode %{
9893 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label), /* is_far */ true);
9894 %}
9895
9896 ins_pipe(pipe_cmpz_branch);
9897 %}
9898
9899 instruct far_cmpULEqNeLeGt_reg_imm0_branch(cmpOpUEqNeLeGt cmp, iRegL op1, immL0 zero, label lbl)
9900 %{
9901 match(If cmp (CmpUL op1 zero));
9902
9903 effect(USE op1, USE lbl);
9904
9905 ins_cost(BRANCH_COST * 2);
9906
9907 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpULEqNeLeGt_reg_imm0_branch" %}
9908
9909 ins_encode %{
9910 __ enc_cmpUEqNeLeGt_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
9911 %}
9912
9913 ins_pipe(pipe_cmpz_branch);
9914 %}
9915
9916 instruct far_cmpULEqNeLeGt_reg_imm0_loop(cmpOpUEqNeLeGt cmp, iRegL op1, immL0 zero, label lbl)
9917 %{
9918 match(CountedLoopEnd cmp (CmpUL op1 zero));
9919
9920 effect(USE op1, USE lbl);
9921
9922 ins_cost(BRANCH_COST * 2);
9923
9924 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpULEqNeLeGt_reg_imm0_loop" %}
9925
9926 ins_encode %{
9927 __ enc_cmpUEqNeLeGt_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
9928 %}
9929
9930 ins_pipe(pipe_cmpz_branch);
9931 %}
9932
9933 // compare lt/ge unsigned instructs has no short instruct with same match
9934 instruct far_cmpULLtGe_reg_imm0_branch(cmpOpULtGe cmp, iRegL op1, immL0 zero, label lbl)
9935 %{
9936 match(If cmp (CmpUL op1 zero));
9937
9938 effect(USE op1, USE lbl);
9939
9940 ins_cost(BRANCH_COST);
9941
9942 format %{ "j $lbl if $cmp == ge\t#@far_cmpULLtGe_reg_imm0_branch" %}
9943
9944 ins_encode(riscv_enc_far_cmpULtGe_imm0_branch(cmp, op1, lbl));
9945
9946 ins_pipe(pipe_cmpz_branch);
9947 %}
9948
9949 instruct far_cmpULLtGe_reg_imm0_loop(cmpOpULtGe cmp, iRegL op1, immL0 zero, label lbl)
9950 %{
9951 match(CountedLoopEnd cmp (CmpUL op1 zero));
9952
9953 effect(USE op1, USE lbl);
9954
9955 ins_cost(BRANCH_COST);
9956
9957 format %{ "j $lbl if $cmp == ge\t#@far_cmpULLtGe_reg_imm0_loop" %}
9958
9959 ins_encode(riscv_enc_far_cmpULtGe_imm0_branch(cmp, op1, lbl));
9960
9961 ins_pipe(pipe_cmpz_branch);
9962 %}
9963
9964 instruct far_cmpP_imm0_branch(cmpOpEqNe cmp, iRegP op1, immP0 zero, label lbl) %{
9965 match(If cmp (CmpP op1 zero));
9966 effect(USE lbl);
9967
9968 ins_cost(BRANCH_COST * 2);
9969 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpP_imm0_branch" %}
9970
9971 ins_encode %{
9972 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
9973 %}
9974
9975 ins_pipe(pipe_cmpz_branch);
9976 %}
9977
9978 instruct far_cmpP_imm0_loop(cmpOpEqNe cmp, iRegP op1, immP0 zero, label lbl) %{
9979 match(CountedLoopEnd cmp (CmpP op1 zero));
9980 effect(USE lbl);
9981
9982 ins_cost(BRANCH_COST * 2);
9983 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpP_imm0_loop" %}
9984
9985 ins_encode %{
9986 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
9987 %}
9988
9989 ins_pipe(pipe_cmpz_branch);
9990 %}
9991
9992 instruct far_cmpN_imm0_branch(cmpOpEqNe cmp, iRegN op1, immN0 zero, label lbl) %{
9993 match(If cmp (CmpN op1 zero));
9994 effect(USE lbl);
9995
9996 ins_cost(BRANCH_COST * 2);
9997
9998 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpN_imm0_branch" %}
9999
10000 ins_encode %{
10001 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
10002 %}
10003
10004 ins_pipe(pipe_cmpz_branch);
10005 %}
10006
10007 instruct far_cmpN_imm0_loop(cmpOpEqNe cmp, iRegN op1, immN0 zero, label lbl) %{
10008 match(CountedLoopEnd cmp (CmpN op1 zero));
10009 effect(USE lbl);
10010
10011 ins_cost(BRANCH_COST * 2);
10012
10013 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpN_imm0_loop" %}
10014
10015 ins_encode %{
10016 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
10017 %}
10018
10019 ins_pipe(pipe_cmpz_branch);
10020 %}
10021
10022 instruct far_cmpP_narrowOop_imm0_branch(cmpOpEqNe cmp, iRegN op1, immP0 zero, label lbl) %{
10023 match(If cmp (CmpP (DecodeN op1) zero));
10024 effect(USE lbl);
10025
10026 ins_cost(BRANCH_COST * 2);
10027 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpP_narrowOop_imm0_branch" %}
10028
10029 ins_encode %{
10030 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
10031 %}
10032
10033 ins_pipe(pipe_cmpz_branch);
10034 %}
10035
10036 instruct far_cmpP_narrowOop_imm0_loop(cmpOpEqNe cmp, iRegN op1, immP0 zero, label lbl) %{
10037 match(CountedLoopEnd cmp (CmpP (DecodeN op1) zero));
10038 effect(USE lbl);
10039
10040 ins_cost(BRANCH_COST * 2);
10041 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpP_narrowOop_imm0_loop" %}
10042
10043 ins_encode %{
10044 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
10045 %}
10046
10047 ins_pipe(pipe_cmpz_branch);
10048 %}
10049
10050 // ============================================================================
10051 // Conditional Move Instructions
10052 instruct cmovI_cmpI(iRegINoSp dst, iRegI src, iRegI op1, iRegI op2, cmpOp cop) %{
10053 match(Set dst (CMoveI (Binary cop (CmpI op1 op2)) (Binary dst src)));
10054 ins_cost(ALU_COST + BRANCH_COST);
10055
10056 format %{
10057 "CMove $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpI\n\t"
10058 %}
10059
10060 ins_encode %{
10061 __ enc_cmove($cop$$cmpcode,
10062 as_Register($op1$$reg), as_Register($op2$$reg),
10063 as_Register($dst$$reg), as_Register($src$$reg));
10064 %}
10065
10066 ins_pipe(pipe_class_compare);
10067 %}
10068
10069 instruct cmovI_cmpU(iRegINoSp dst, iRegI src, iRegI op1, iRegI op2, cmpOpU cop) %{
10070 match(Set dst (CMoveI (Binary cop (CmpU op1 op2)) (Binary dst src)));
10071 ins_cost(ALU_COST + BRANCH_COST);
10072
10073 format %{
10074 "CMove $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpU\n\t"
10075 %}
10076
10077 ins_encode %{
10078 __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10079 as_Register($op1$$reg), as_Register($op2$$reg),
10080 as_Register($dst$$reg), as_Register($src$$reg));
10081 %}
10082
10083 ins_pipe(pipe_class_compare);
10084 %}
10085
10086 instruct cmovI_cmpL(iRegINoSp dst, iRegI src, iRegL op1, iRegL op2, cmpOp cop) %{
10087 match(Set dst (CMoveI (Binary cop (CmpL op1 op2)) (Binary dst src)));
10088 ins_cost(ALU_COST + BRANCH_COST);
10089
10090 format %{
10091 "CMove $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpL\n\t"
10092 %}
10093
10094 ins_encode %{
10095 __ enc_cmove($cop$$cmpcode,
10096 as_Register($op1$$reg), as_Register($op2$$reg),
10097 as_Register($dst$$reg), as_Register($src$$reg));
10098 %}
10099
10100 ins_pipe(pipe_class_compare);
10101 %}
10102
10103 instruct cmovI_cmpUL(iRegINoSp dst, iRegI src, iRegL op1, iRegL op2, cmpOpU cop) %{
10104 match(Set dst (CMoveI (Binary cop (CmpUL op1 op2)) (Binary dst src)));
10105 ins_cost(ALU_COST + BRANCH_COST);
10106
10107 format %{
10108 "CMove $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpUL\n\t"
10109 %}
10110
10111 ins_encode %{
10112 __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10113 as_Register($op1$$reg), as_Register($op2$$reg),
10114 as_Register($dst$$reg), as_Register($src$$reg));
10115 %}
10116
10117 ins_pipe(pipe_class_compare);
10118 %}
10119
10120 instruct cmovL_cmpL(iRegLNoSp dst, iRegL src, iRegL op1, iRegL op2, cmpOp cop) %{
10121 match(Set dst (CMoveL (Binary cop (CmpL op1 op2)) (Binary dst src)));
10122 ins_cost(ALU_COST + BRANCH_COST);
10123
10124 format %{
10125 "CMove $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpL\n\t"
10126 %}
10127
10128 ins_encode %{
10129 __ enc_cmove($cop$$cmpcode,
10130 as_Register($op1$$reg), as_Register($op2$$reg),
10131 as_Register($dst$$reg), as_Register($src$$reg));
10132 %}
10133
10134 ins_pipe(pipe_class_compare);
10135 %}
10136
10137 instruct cmovL_cmpUL(iRegLNoSp dst, iRegL src, iRegL op1, iRegL op2, cmpOpU cop) %{
10138 match(Set dst (CMoveL (Binary cop (CmpUL op1 op2)) (Binary dst src)));
10139 ins_cost(ALU_COST + BRANCH_COST);
10140
10141 format %{
10142 "CMove $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpUL\n\t"
10143 %}
10144
10145 ins_encode %{
10146 __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10147 as_Register($op1$$reg), as_Register($op2$$reg),
10148 as_Register($dst$$reg), as_Register($src$$reg));
10149 %}
10150
10151 ins_pipe(pipe_class_compare);
10152 %}
10153
10154 instruct cmovL_cmpI(iRegLNoSp dst, iRegL src, iRegI op1, iRegI op2, cmpOp cop) %{
10155 match(Set dst (CMoveL (Binary cop (CmpI op1 op2)) (Binary dst src)));
10156 ins_cost(ALU_COST + BRANCH_COST);
10157
10158 format %{
10159 "CMove $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpI\n\t"
10160 %}
10161
10162 ins_encode %{
10163 __ enc_cmove($cop$$cmpcode,
10164 as_Register($op1$$reg), as_Register($op2$$reg),
10165 as_Register($dst$$reg), as_Register($src$$reg));
10166 %}
10167
10168 ins_pipe(pipe_class_compare);
10169 %}
10170
10171 instruct cmovL_cmpU(iRegLNoSp dst, iRegL src, iRegI op1, iRegI op2, cmpOpU cop) %{
10172 match(Set dst (CMoveL (Binary cop (CmpU op1 op2)) (Binary dst src)));
10173 ins_cost(ALU_COST + BRANCH_COST);
10174
10175 format %{
10176 "CMove $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpU\n\t"
10177 %}
10178
10179 ins_encode %{
10180 __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10181 as_Register($op1$$reg), as_Register($op2$$reg),
10182 as_Register($dst$$reg), as_Register($src$$reg));
10183 %}
10184
10185 ins_pipe(pipe_class_compare);
10186 %}
10187
10188 // ============================================================================
10189 // Procedure Call/Return Instructions
10190
10191 // Call Java Static Instruction
10192 // Note: If this code changes, the corresponding ret_addr_offset() and
10193 // compute_padding() functions will have to be adjusted.
10194 instruct CallStaticJavaDirect(method meth)
10195 %{
10196 match(CallStaticJava);
10197
10198 effect(USE meth);
10199
10200 ins_cost(BRANCH_COST);
10201
10202 format %{ "CALL,static $meth\t#@CallStaticJavaDirect" %}
10203
10204 ins_encode(riscv_enc_java_static_call(meth),
10205 riscv_enc_call_epilog);
10206
10207 ins_pipe(pipe_class_call);
10208 ins_alignment(4);
10209 %}
10210
10211 // TO HERE
10212
10213 // Call Java Dynamic Instruction
10214 // Note: If this code changes, the corresponding ret_addr_offset() and
10215 // compute_padding() functions will have to be adjusted.
10216 instruct CallDynamicJavaDirect(method meth, rFlagsReg cr)
10217 %{
10218 match(CallDynamicJava);
10219
10220 effect(USE meth, KILL cr);
10221
10222 ins_cost(BRANCH_COST + ALU_COST * 6);
10223
10224 format %{ "CALL,dynamic $meth\t#@CallDynamicJavaDirect" %}
10225
10226 ins_encode(riscv_enc_java_dynamic_call(meth),
10227 riscv_enc_call_epilog);
10228
10229 ins_pipe(pipe_class_call);
10230 ins_alignment(4);
10231 %}
10232
10233 // Call Runtime Instruction
10234
10235 instruct CallRuntimeDirect(method meth, rFlagsReg cr)
10236 %{
10237 match(CallRuntime);
10238
10239 effect(USE meth, KILL cr);
10240
10241 ins_cost(BRANCH_COST);
10242
10243 format %{ "CALL, runtime $meth\t#@CallRuntimeDirect" %}
10244
10245 ins_encode(riscv_enc_java_to_runtime(meth));
10246
10247 ins_pipe(pipe_class_call);
10248 %}
10249
10250 // Call Runtime Instruction
10251
10252 instruct CallLeafDirect(method meth, rFlagsReg cr)
10253 %{
10254 match(CallLeaf);
10255
10256 effect(USE meth, KILL cr);
10257
10258 ins_cost(BRANCH_COST);
10259
10260 format %{ "CALL, runtime leaf $meth\t#@CallLeafDirect" %}
10261
10262 ins_encode(riscv_enc_java_to_runtime(meth));
10263
10264 ins_pipe(pipe_class_call);
10265 %}
10266
10267 // Call Runtime Instruction
10268
10269 instruct CallLeafNoFPDirect(method meth, rFlagsReg cr)
10270 %{
10271 match(CallLeafNoFP);
10272
10273 effect(USE meth, KILL cr);
10274
10275 ins_cost(BRANCH_COST);
10276
10277 format %{ "CALL, runtime leaf nofp $meth\t#@CallLeafNoFPDirect" %}
10278
10279 ins_encode(riscv_enc_java_to_runtime(meth));
10280
10281 ins_pipe(pipe_class_call);
10282 %}
10283
10284 // ============================================================================
10285 // Partial Subtype Check
10286 //
10287 // superklass array for an instance of the superklass. Set a hidden
10288 // internal cache on a hit (cache is checked with exposed code in
10289 // gen_subtype_check()). Return zero for a hit. The encoding
10290 // ALSO sets flags.
10291
10292 instruct partialSubtypeCheck(iRegP_R15 result, iRegP_R14 sub, iRegP_R10 super, iRegP_R12 tmp, rFlagsReg cr)
10293 %{
10294 match(Set result (PartialSubtypeCheck sub super));
10295 effect(KILL tmp, KILL cr);
10296
10297 ins_cost(2 * STORE_COST + 3 * LOAD_COST + 4 * ALU_COST + BRANCH_COST * 4);
10298 format %{ "partialSubtypeCheck $result, $sub, $super\t#@partialSubtypeCheck" %}
10299
10300 ins_encode(riscv_enc_partial_subtype_check(sub, super, tmp, result));
10301
10302 opcode(0x1); // Force zero of result reg on hit
10303
10304 ins_pipe(pipe_class_memory);
10305 %}
10306
10307 instruct partialSubtypeCheckVsZero(iRegP_R15 result, iRegP_R14 sub, iRegP_R10 super, iRegP_R12 tmp,
10308 immP0 zero, rFlagsReg cr)
10309 %{
10310 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero));
10311 effect(KILL tmp, KILL result);
10312
10313 ins_cost(2 * STORE_COST + 3 * LOAD_COST + 4 * ALU_COST + BRANCH_COST * 4);
10314 format %{ "partialSubtypeCheck $result, $sub, $super == 0\t#@partialSubtypeCheckVsZero" %}
10315
10316 ins_encode(riscv_enc_partial_subtype_check(sub, super, tmp, result));
10317
10318 opcode(0x0); // Don't zero result reg on hit
10319
10320 ins_pipe(pipe_class_memory);
10321 %}
10322
10323 instruct string_compareU(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
10324 iRegI_R10 result, iRegP_R28 tmp1, iRegL_R29 tmp2, iRegL_R30 tmp3, rFlagsReg cr)
10325 %{
10326 predicate(!UseRVV && ((StrCompNode *)n)->encoding() == StrIntrinsicNode::UU);
10327 match(Set result (StrComp(Binary str1 cnt1)(Binary str2 cnt2)));
10328 effect(KILL tmp1, KILL tmp2, KILL tmp3, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
10329
10330 format %{ "String Compare $str1, $cnt1, $str2, $cnt2 -> $result\t#@string_compareU" %}
10331 ins_encode %{
10332 // Count is in 8-bit bytes; non-Compact chars are 16 bits.
10333 __ string_compare($str1$$Register, $str2$$Register,
10334 $cnt1$$Register, $cnt2$$Register, $result$$Register,
10335 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
10336 StrIntrinsicNode::UU);
10337 %}
10338 ins_pipe(pipe_class_memory);
10339 %}
10340
10341 instruct string_compareL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
10342 iRegI_R10 result, iRegP_R28 tmp1, iRegL_R29 tmp2, iRegL_R30 tmp3, rFlagsReg cr)
10343 %{
10344 predicate(!UseRVV && ((StrCompNode *)n)->encoding() == StrIntrinsicNode::LL);
10345 match(Set result (StrComp(Binary str1 cnt1)(Binary str2 cnt2)));
10346 effect(KILL tmp1, KILL tmp2, KILL tmp3, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
10347
10348 format %{ "String Compare $str1, $cnt1, $str2, $cnt2 -> $result\t#@string_compareL" %}
10349 ins_encode %{
10350 __ string_compare($str1$$Register, $str2$$Register,
10351 $cnt1$$Register, $cnt2$$Register, $result$$Register,
10352 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
10353 StrIntrinsicNode::LL);
10354 %}
10355 ins_pipe(pipe_class_memory);
10356 %}
10357
10358 instruct string_compareUL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
10359 iRegI_R10 result, iRegP_R28 tmp1, iRegL_R29 tmp2, iRegL_R30 tmp3, rFlagsReg cr)
10360 %{
10361 predicate(!UseRVV && ((StrCompNode *)n)->encoding() == StrIntrinsicNode::UL);
10362 match(Set result (StrComp(Binary str1 cnt1)(Binary str2 cnt2)));
10363 effect(KILL tmp1, KILL tmp2, KILL tmp3, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
10364
10365 format %{"String Compare $str1, $cnt1, $str2, $cnt2 -> $result\t#@string_compareUL" %}
10366 ins_encode %{
10367 __ string_compare($str1$$Register, $str2$$Register,
10368 $cnt1$$Register, $cnt2$$Register, $result$$Register,
10369 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
10370 StrIntrinsicNode::UL);
10371 %}
10372 ins_pipe(pipe_class_memory);
10373 %}
10374
10375 instruct string_compareLU(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
10376 iRegI_R10 result, iRegP_R28 tmp1, iRegL_R29 tmp2, iRegL_R30 tmp3,
10377 rFlagsReg cr)
10378 %{
10379 predicate(!UseRVV && ((StrCompNode *)n)->encoding() == StrIntrinsicNode::LU);
10380 match(Set result (StrComp(Binary str1 cnt1)(Binary str2 cnt2)));
10381 effect(KILL tmp1, KILL tmp2, KILL tmp3, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
10382
10383 format %{ "String Compare $str1, $cnt1, $str2, $cnt2 -> $result\t#@string_compareLU" %}
10384 ins_encode %{
10385 __ string_compare($str1$$Register, $str2$$Register,
10386 $cnt1$$Register, $cnt2$$Register, $result$$Register,
10387 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
10388 StrIntrinsicNode::LU);
10389 %}
10390 ins_pipe(pipe_class_memory);
10391 %}
10392
10393 instruct string_indexofUU(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
10394 iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3,
10395 iRegINoSp tmp4, iRegINoSp tmp5, iRegINoSp tmp6, rFlagsReg cr)
10396 %{
10397 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU);
10398 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
10399 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, TEMP_DEF result,
10400 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, TEMP tmp6, KILL cr);
10401
10402 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result (UU)" %}
10403 ins_encode %{
10404 __ string_indexof($str1$$Register, $str2$$Register,
10405 $cnt1$$Register, $cnt2$$Register,
10406 $tmp1$$Register, $tmp2$$Register,
10407 $tmp3$$Register, $tmp4$$Register,
10408 $tmp5$$Register, $tmp6$$Register,
10409 $result$$Register, StrIntrinsicNode::UU);
10410 %}
10411 ins_pipe(pipe_class_memory);
10412 %}
10413
10414 instruct string_indexofLL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
10415 iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3,
10416 iRegINoSp tmp4, iRegINoSp tmp5, iRegINoSp tmp6, rFlagsReg cr)
10417 %{
10418 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL);
10419 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
10420 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, TEMP_DEF result,
10421 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, TEMP tmp6, KILL cr);
10422
10423 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result (LL)" %}
10424 ins_encode %{
10425 __ string_indexof($str1$$Register, $str2$$Register,
10426 $cnt1$$Register, $cnt2$$Register,
10427 $tmp1$$Register, $tmp2$$Register,
10428 $tmp3$$Register, $tmp4$$Register,
10429 $tmp5$$Register, $tmp6$$Register,
10430 $result$$Register, StrIntrinsicNode::LL);
10431 %}
10432 ins_pipe(pipe_class_memory);
10433 %}
10434
10435 instruct string_indexofUL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
10436 iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3,
10437 iRegINoSp tmp4, iRegINoSp tmp5, iRegINoSp tmp6, rFlagsReg cr)
10438 %{
10439 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL);
10440 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
10441 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, TEMP_DEF result,
10442 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, TEMP tmp6, KILL cr);
10443 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result (UL)" %}
10444
10445 ins_encode %{
10446 __ string_indexof($str1$$Register, $str2$$Register,
10447 $cnt1$$Register, $cnt2$$Register,
10448 $tmp1$$Register, $tmp2$$Register,
10449 $tmp3$$Register, $tmp4$$Register,
10450 $tmp5$$Register, $tmp6$$Register,
10451 $result$$Register, StrIntrinsicNode::UL);
10452 %}
10453 ins_pipe(pipe_class_memory);
10454 %}
10455
10456 instruct string_indexof_conUU(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2,
10457 immI_le_4 int_cnt2, iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2,
10458 iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
10459 %{
10460 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU);
10461 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
10462 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, TEMP_DEF result,
10463 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
10464
10465 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result (UU)" %}
10466
10467 ins_encode %{
10468 int icnt2 = (int)$int_cnt2$$constant;
10469 __ string_indexof_linearscan($str1$$Register, $str2$$Register,
10470 $cnt1$$Register, zr,
10471 $tmp1$$Register, $tmp2$$Register,
10472 $tmp3$$Register, $tmp4$$Register,
10473 icnt2, $result$$Register, StrIntrinsicNode::UU);
10474 %}
10475 ins_pipe(pipe_class_memory);
10476 %}
10477
10478 instruct string_indexof_conLL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2,
10479 immI_le_4 int_cnt2, iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2,
10480 iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
10481 %{
10482 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL);
10483 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
10484 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, TEMP_DEF result,
10485 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
10486
10487 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result (LL)" %}
10488 ins_encode %{
10489 int icnt2 = (int)$int_cnt2$$constant;
10490 __ string_indexof_linearscan($str1$$Register, $str2$$Register,
10491 $cnt1$$Register, zr,
10492 $tmp1$$Register, $tmp2$$Register,
10493 $tmp3$$Register, $tmp4$$Register,
10494 icnt2, $result$$Register, StrIntrinsicNode::LL);
10495 %}
10496 ins_pipe(pipe_class_memory);
10497 %}
10498
10499 instruct string_indexof_conUL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2,
10500 immI_1 int_cnt2, iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2,
10501 iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
10502 %{
10503 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL);
10504 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
10505 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, TEMP_DEF result,
10506 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
10507
10508 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result (UL)" %}
10509 ins_encode %{
10510 int icnt2 = (int)$int_cnt2$$constant;
10511 __ string_indexof_linearscan($str1$$Register, $str2$$Register,
10512 $cnt1$$Register, zr,
10513 $tmp1$$Register, $tmp2$$Register,
10514 $tmp3$$Register, $tmp4$$Register,
10515 icnt2, $result$$Register, StrIntrinsicNode::UL);
10516 %}
10517 ins_pipe(pipe_class_memory);
10518 %}
10519
10520 instruct stringU_indexof_char(iRegP_R11 str1, iRegI_R12 cnt1, iRegI_R13 ch,
10521 iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2,
10522 iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
10523 %{
10524 match(Set result (StrIndexOfChar (Binary str1 cnt1) ch));
10525 predicate(!UseRVV && (((StrIndexOfCharNode*)n)->encoding() == StrIntrinsicNode::U));
10526 effect(USE_KILL str1, USE_KILL cnt1, USE_KILL ch, TEMP_DEF result,
10527 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
10528
10529 format %{ "StringUTF16 IndexOf char[] $str1,$cnt1,$ch -> $result" %}
10530 ins_encode %{
10531 __ string_indexof_char($str1$$Register, $cnt1$$Register, $ch$$Register,
10532 $result$$Register, $tmp1$$Register, $tmp2$$Register,
10533 $tmp3$$Register, $tmp4$$Register, false /* isU */);
10534 %}
10535 ins_pipe(pipe_class_memory);
10536 %}
10537
10538
10539 instruct stringL_indexof_char(iRegP_R11 str1, iRegI_R12 cnt1, iRegI_R13 ch,
10540 iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2,
10541 iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
10542 %{
10543 match(Set result (StrIndexOfChar (Binary str1 cnt1) ch));
10544 predicate(!UseRVV && (((StrIndexOfCharNode*)n)->encoding() == StrIntrinsicNode::L));
10545 effect(USE_KILL str1, USE_KILL cnt1, USE_KILL ch, TEMP_DEF result,
10546 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
10547
10548 format %{ "StringUTF16 IndexOf char[] $str1,$cnt1,$ch -> $result" %}
10549 ins_encode %{
10550 __ string_indexof_char($str1$$Register, $cnt1$$Register, $ch$$Register,
10551 $result$$Register, $tmp1$$Register, $tmp2$$Register,
10552 $tmp3$$Register, $tmp4$$Register, true /* isL */);
10553 %}
10554 ins_pipe(pipe_class_memory);
10555 %}
10556
10557 // clearing of an array
10558 instruct clearArray_reg_reg(iRegL_R29 cnt, iRegP_R28 base, iRegP_R30 tmp1,
10559 iRegP_R31 tmp2, Universe dummy)
10560 %{
10561 // temp registers must match the one used in StubGenerator::generate_zero_blocks()
10562 predicate(UseBlockZeroing || !UseRVV);
10563 match(Set dummy (ClearArray cnt base));
10564 effect(USE_KILL cnt, USE_KILL base, TEMP tmp1, TEMP tmp2);
10565
10566 ins_cost(4 * DEFAULT_COST);
10567 format %{ "ClearArray $cnt, $base\t#@clearArray_reg_reg" %}
10568
10569 ins_encode %{
10570 address tpc = __ zero_words($base$$Register, $cnt$$Register);
10571 if (tpc == NULL) {
10572 ciEnv::current()->record_failure("CodeCache is full");
10573 return;
10574 }
10575 %}
10576
10577 ins_pipe(pipe_class_memory);
10578 %}
10579
10580 instruct clearArray_imm_reg(immL cnt, iRegP_R28 base, Universe dummy, rFlagsReg cr)
10581 %{
10582 predicate(!UseRVV && (uint64_t)n->in(2)->get_long()
10583 < (uint64_t)(BlockZeroingLowLimit >> LogBytesPerWord));
10584 match(Set dummy (ClearArray cnt base));
10585 effect(USE_KILL base, KILL cr);
10586
10587 ins_cost(4 * DEFAULT_COST);
10588 format %{ "ClearArray $cnt, $base\t#@clearArray_imm_reg" %}
10589
10590 ins_encode %{
10591 __ zero_words($base$$Register, (uint64_t)$cnt$$constant);
10592 %}
10593
10594 ins_pipe(pipe_class_memory);
10595 %}
10596
10597 instruct string_equalsL(iRegP_R11 str1, iRegP_R13 str2, iRegI_R14 cnt,
10598 iRegI_R10 result, rFlagsReg cr)
10599 %{
10600 predicate(!UseRVV && ((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::LL);
10601 match(Set result (StrEquals (Binary str1 str2) cnt));
10602 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL cr);
10603
10604 format %{ "String Equals $str1, $str2, $cnt -> $result\t#@string_equalsL" %}
10605 ins_encode %{
10606 // Count is in 8-bit bytes; non-Compact chars are 16 bits.
10607 __ string_equals($str1$$Register, $str2$$Register,
10608 $result$$Register, $cnt$$Register, 1);
10609 %}
10610 ins_pipe(pipe_class_memory);
10611 %}
10612
10613 instruct string_equalsU(iRegP_R11 str1, iRegP_R13 str2, iRegI_R14 cnt,
10614 iRegI_R10 result, rFlagsReg cr)
10615 %{
10616 predicate(!UseRVV && ((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::UU);
10617 match(Set result (StrEquals (Binary str1 str2) cnt));
10618 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL cr);
10619
10620 format %{ "String Equals $str1, $str2, $cnt -> $result\t#@string_equalsU" %}
10621 ins_encode %{
10622 // Count is in 8-bit bytes; non-Compact chars are 16 bits.
10623 __ string_equals($str1$$Register, $str2$$Register,
10624 $result$$Register, $cnt$$Register, 2);
10625 %}
10626 ins_pipe(pipe_class_memory);
10627 %}
10628
10629 instruct array_equalsB(iRegP_R11 ary1, iRegP_R12 ary2, iRegI_R10 result,
10630 iRegP_R13 tmp1, iRegP_R14 tmp2, iRegP_R15 tmp3,
10631 iRegP_R16 tmp4, iRegP_R28 tmp5, rFlagsReg cr)
10632 %{
10633 predicate(!UseRVV && ((AryEqNode*)n)->encoding() == StrIntrinsicNode::LL);
10634 match(Set result (AryEq ary1 ary2));
10635 effect(USE_KILL ary1, USE_KILL ary2, TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL tmp5, KILL cr);
10636
10637 format %{ "Array Equals $ary1, ary2 -> $result\t#@array_equalsB // KILL $tmp5" %}
10638 ins_encode %{
10639 __ arrays_equals($ary1$$Register, $ary2$$Register,
10640 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register,
10641 $result$$Register, $tmp5$$Register, 1);
10642 %}
10643 ins_pipe(pipe_class_memory);
10644 %}
10645
10646 instruct array_equalsC(iRegP_R11 ary1, iRegP_R12 ary2, iRegI_R10 result,
10647 iRegP_R13 tmp1, iRegP_R14 tmp2, iRegP_R15 tmp3,
10648 iRegP_R16 tmp4, iRegP_R28 tmp5, rFlagsReg cr)
10649 %{
10650 predicate(!UseRVV && ((AryEqNode*)n)->encoding() == StrIntrinsicNode::UU);
10651 match(Set result (AryEq ary1 ary2));
10652 effect(USE_KILL ary1, USE_KILL ary2, TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL tmp5, KILL cr);
10653
10654 format %{ "Array Equals $ary1, ary2 -> $result\t#@array_equalsC // KILL $tmp5" %}
10655 ins_encode %{
10656 __ arrays_equals($ary1$$Register, $ary2$$Register,
10657 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register,
10658 $result$$Register, $tmp5$$Register, 2);
10659 %}
10660 ins_pipe(pipe_class_memory);
10661 %}
10662
10663 // ============================================================================
10664 // Safepoint Instructions
10665
10666 instruct safePoint(iRegP poll)
10667 %{
10668 match(SafePoint poll);
10669
10670 ins_cost(2 * LOAD_COST);
10671 format %{
10672 "lwu zr, [$poll]\t# Safepoint: poll for GC, #@safePoint"
10673 %}
10674 ins_encode %{
10675 __ read_polling_page(as_Register($poll$$reg), 0, relocInfo::poll_type);
10676 %}
10677 ins_pipe(pipe_serial); // ins_pipe(iload_reg_mem);
10678 %}
10679
10680 // ============================================================================
10681 // This name is KNOWN by the ADLC and cannot be changed.
10682 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
10683 // for this guy.
10684 instruct tlsLoadP(javaThread_RegP dst)
10685 %{
10686 match(Set dst (ThreadLocal));
10687
10688 ins_cost(0);
10689
10690 format %{ " -- \t// $dst=Thread::current(), empty, #@tlsLoadP" %}
10691
10692 size(0);
10693
10694 ins_encode( /*empty*/ );
10695
10696 ins_pipe(pipe_class_empty);
10697 %}
10698
10699 // inlined locking and unlocking
10700 // using t1 as the 'flag' register to bridge the BoolNode producers and consumers
10701 instruct cmpFastLock(rFlagsReg cr, iRegP object, iRegP box, iRegPNoSp tmp1, iRegPNoSp tmp2)
10702 %{
10703 match(Set cr (FastLock object box));
10704 effect(TEMP tmp1, TEMP tmp2);
10705
10706 ins_cost(LOAD_COST * 2 + STORE_COST * 3 + ALU_COST * 6 + BRANCH_COST * 3);
10707 format %{ "fastlock $object,$box\t! kills $tmp1,$tmp2, #@cmpFastLock" %}
10708
10709 ins_encode(riscv_enc_fast_lock(object, box, tmp1, tmp2));
10710
10711 ins_pipe(pipe_serial);
10712 %}
10713
10714 // using t1 as the 'flag' register to bridge the BoolNode producers and consumers
10715 instruct cmpFastUnlock(rFlagsReg cr, iRegP object, iRegP box, iRegPNoSp tmp1, iRegPNoSp tmp2)
10716 %{
10717 match(Set cr (FastUnlock object box));
10718 effect(TEMP tmp1, TEMP tmp2);
10719
10720 ins_cost(LOAD_COST * 2 + STORE_COST + ALU_COST * 2 + BRANCH_COST * 4);
10721 format %{ "fastunlock $object,$box\t! kills $tmp1, $tmp2, #@cmpFastUnlock" %}
10722
10723 ins_encode(riscv_enc_fast_unlock(object, box, tmp1, tmp2));
10724
10725 ins_pipe(pipe_serial);
10726 %}
10727
10728 // Tail Call; Jump from runtime stub to Java code.
10729 // Also known as an 'interprocedural jump'.
10730 // Target of jump will eventually return to caller.
10731 // TailJump below removes the return address.
10732 instruct TailCalljmpInd(iRegPNoSp jump_target, inline_cache_RegP method_oop)
10733 %{
10734 match(TailCall jump_target method_oop);
10735
10736 ins_cost(BRANCH_COST);
10737
10738 format %{ "jalr $jump_target\t# $method_oop holds method oop, #@TailCalljmpInd." %}
10739
10740 ins_encode(riscv_enc_tail_call(jump_target));
10741
10742 ins_pipe(pipe_class_call);
10743 %}
10744
10745 instruct TailjmpInd(iRegPNoSp jump_target, iRegP_R10 ex_oop)
10746 %{
10747 match(TailJump jump_target ex_oop);
10748
10749 ins_cost(ALU_COST + BRANCH_COST);
10750
10751 format %{ "jalr $jump_target\t# $ex_oop holds exception oop, #@TailjmpInd." %}
10752
10753 ins_encode(riscv_enc_tail_jmp(jump_target));
10754
10755 ins_pipe(pipe_class_call);
10756 %}
10757
10758 // Create exception oop: created by stack-crawling runtime code.
10759 // Created exception is now available to this handler, and is setup
10760 // just prior to jumping to this handler. No code emitted.
10761 instruct CreateException(iRegP_R10 ex_oop)
10762 %{
10763 match(Set ex_oop (CreateEx));
10764
10765 ins_cost(0);
10766 format %{ " -- \t// exception oop; no code emitted, #@CreateException" %}
10767
10768 size(0);
10769
10770 ins_encode( /*empty*/ );
10771
10772 ins_pipe(pipe_class_empty);
10773 %}
10774
10775 // Rethrow exception: The exception oop will come in the first
10776 // argument position. Then JUMP (not call) to the rethrow stub code.
10777 instruct RethrowException()
10778 %{
10779 match(Rethrow);
10780
10781 ins_cost(BRANCH_COST);
10782
10783 format %{ "j rethrow_stub\t#@RethrowException" %}
10784
10785 ins_encode(riscv_enc_rethrow());
10786
10787 ins_pipe(pipe_class_call);
10788 %}
10789
10790 // Return Instruction
10791 // epilog node loads ret address into ra as part of frame pop
10792 instruct Ret()
10793 %{
10794 match(Return);
10795
10796 ins_cost(BRANCH_COST);
10797 format %{ "ret\t// return register, #@Ret" %}
10798
10799 ins_encode(riscv_enc_ret());
10800
10801 ins_pipe(pipe_branch);
10802 %}
10803
10804 // Die now.
10805 instruct ShouldNotReachHere() %{
10806 match(Halt);
10807
10808 ins_cost(BRANCH_COST);
10809
10810 format %{ "#@ShouldNotReachHere" %}
10811
10812 ins_encode %{
10813 if (is_reachable()) {
10814 __ stop(_halt_reason);
10815 }
10816 %}
10817
10818 ins_pipe(pipe_class_default);
10819 %}
10820
10821
10822 //----------PEEPHOLE RULES-----------------------------------------------------
10823 // These must follow all instruction definitions as they use the names
10824 // defined in the instructions definitions.
10825 //
10826 // peepmatch ( root_instr_name [preceding_instruction]* );
10827 //
10828 // peepconstraint %{
10829 // (instruction_number.operand_name relational_op instruction_number.operand_name
10830 // [, ...] );
10831 // // instruction numbers are zero-based using left to right order in peepmatch
10832 //
10833 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
10834 // // provide an instruction_number.operand_name for each operand that appears
10835 // // in the replacement instruction's match rule
10836 //
10837 // ---------VM FLAGS---------------------------------------------------------
10838 //
10839 // All peephole optimizations can be turned off using -XX:-OptoPeephole
10840 //
10841 // Each peephole rule is given an identifying number starting with zero and
10842 // increasing by one in the order seen by the parser. An individual peephole
10843 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
10844 // on the command-line.
10845 //
10846 // ---------CURRENT LIMITATIONS----------------------------------------------
10847 //
10848 // Only match adjacent instructions in same basic block
10849 // Only equality constraints
10850 // Only constraints between operands, not (0.dest_reg == RAX_enc)
10851 // Only one replacement instruction
10852 //
10853 //----------SMARTSPILL RULES---------------------------------------------------
10854 // These must follow all instruction definitions as they use the names
10855 // defined in the instructions definitions.
10856
10857 // Local Variables:
10858 // mode: c++
10859 // End: