1 //
    2 // Copyright (c) 2003, 2022, Oracle and/or its affiliates. All rights reserved.
    3 // Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
    4 // Copyright (c) 2020, 2022, Huawei Technologies Co., Ltd. All rights reserved.
    5 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
    6 //
    7 // This code is free software; you can redistribute it and/or modify it
    8 // under the terms of the GNU General Public License version 2 only, as
    9 // published by the Free Software Foundation.
   10 //
   11 // This code is distributed in the hope that it will be useful, but WITHOUT
   12 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
   13 // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
   14 // version 2 for more details (a copy is included in the LICENSE file that
   15 // accompanied this code).
   16 //
   17 // You should have received a copy of the GNU General Public License version
   18 // 2 along with this work; if not, write to the Free Software Foundation,
   19 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
   20 //
   21 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
   22 // or visit www.oracle.com if you need additional information or have any
   23 // questions.
   24 //
   25 //
   26 
   27 // RISCV Architecture Description File
   28 
   29 //----------REGISTER DEFINITION BLOCK------------------------------------------
   30 // This information is used by the matcher and the register allocator to
   31 // describe individual registers and classes of registers within the target
   32 // architecture.
   33 
   34 register %{
   35 //----------Architecture Description Register Definitions----------------------
   36 // General Registers
   37 // "reg_def"  name ( register save type, C convention save type,
   38 //                   ideal register type, encoding );
   39 // Register Save Types:
   40 //
   41 // NS  = No-Save:       The register allocator assumes that these registers
   42 //                      can be used without saving upon entry to the method, &
   43 //                      that they do not need to be saved at call sites.
   44 //
   45 // SOC = Save-On-Call:  The register allocator assumes that these registers
   46 //                      can be used without saving upon entry to the method,
   47 //                      but that they must be saved at call sites.
   48 //
   49 // SOE = Save-On-Entry: The register allocator assumes that these registers
   50 //                      must be saved before using them upon entry to the
   51 //                      method, but they do not need to be saved at call
   52 //                      sites.
   53 //
   54 // AS  = Always-Save:   The register allocator assumes that these registers
   55 //                      must be saved before using them upon entry to the
   56 //                      method, & that they must be saved at call sites.
   57 //
   58 // Ideal Register Type is used to determine how to save & restore a
   59 // register.  Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
   60 // spilled with LoadP/StoreP.  If the register supports both, use Op_RegI.
   61 //
   62 // The encoding number is the actual bit-pattern placed into the opcodes.
   63 
   64 // We must define the 64 bit int registers in two 32 bit halves, the
   65 // real lower register and a virtual upper half register. upper halves
   66 // are used by the register allocator but are not actually supplied as
   67 // operands to memory ops.
   68 //
   69 // follow the C1 compiler in making registers
   70 //
   71 //   x7, x9-x17, x27-x31 volatile (caller save)
   72 //   x0-x4, x8, x23 system (no save, no allocate)
   73 //   x5-x6 non-allocatable (so we can use them as temporary regs)
   74 
   75 //
   76 // as regards Java usage. we don't use any callee save registers
   77 // because this makes it difficult to de-optimise a frame (see comment
   78 // in x86 implementation of Deoptimization::unwind_callee_save_values)
   79 //
   80 
   81 // General Registers
   82 
   83 reg_def R0      ( NS,  NS,  Op_RegI, 0,  x0->as_VMReg()         ); // zr
   84 reg_def R0_H    ( NS,  NS,  Op_RegI, 0,  x0->as_VMReg()->next() );
   85 reg_def R1      ( NS,  SOC, Op_RegI, 1,  x1->as_VMReg()         ); // ra
   86 reg_def R1_H    ( NS,  SOC, Op_RegI, 1,  x1->as_VMReg()->next() );
   87 reg_def R2      ( NS,  SOE, Op_RegI, 2,  x2->as_VMReg()         ); // sp
   88 reg_def R2_H    ( NS,  SOE, Op_RegI, 2,  x2->as_VMReg()->next() );
   89 reg_def R3      ( NS,  NS,  Op_RegI, 3,  x3->as_VMReg()         ); // gp
   90 reg_def R3_H    ( NS,  NS,  Op_RegI, 3,  x3->as_VMReg()->next() );
   91 reg_def R4      ( NS,  NS,  Op_RegI, 4,  x4->as_VMReg()         ); // tp
   92 reg_def R4_H    ( NS,  NS,  Op_RegI, 4,  x4->as_VMReg()->next() );
   93 reg_def R7      ( SOC, SOC, Op_RegI, 7,  x7->as_VMReg()         );
   94 reg_def R7_H    ( SOC, SOC, Op_RegI, 7,  x7->as_VMReg()->next() );
   95 reg_def R8      ( NS,  SOE, Op_RegI, 8,  x8->as_VMReg()         ); // fp
   96 reg_def R8_H    ( NS,  SOE, Op_RegI, 8,  x8->as_VMReg()->next() );
   97 reg_def R9      ( SOC, SOE, Op_RegI, 9,  x9->as_VMReg()         );
   98 reg_def R9_H    ( SOC, SOE, Op_RegI, 9,  x9->as_VMReg()->next() );
   99 reg_def R10     ( SOC, SOC, Op_RegI, 10, x10->as_VMReg()        );
  100 reg_def R10_H   ( SOC, SOC, Op_RegI, 10, x10->as_VMReg()->next());
  101 reg_def R11     ( SOC, SOC, Op_RegI, 11, x11->as_VMReg()        );
  102 reg_def R11_H   ( SOC, SOC, Op_RegI, 11, x11->as_VMReg()->next());
  103 reg_def R12     ( SOC, SOC, Op_RegI, 12, x12->as_VMReg()        );
  104 reg_def R12_H   ( SOC, SOC, Op_RegI, 12, x12->as_VMReg()->next());
  105 reg_def R13     ( SOC, SOC, Op_RegI, 13, x13->as_VMReg()        );
  106 reg_def R13_H   ( SOC, SOC, Op_RegI, 13, x13->as_VMReg()->next());
  107 reg_def R14     ( SOC, SOC, Op_RegI, 14, x14->as_VMReg()        );
  108 reg_def R14_H   ( SOC, SOC, Op_RegI, 14, x14->as_VMReg()->next());
  109 reg_def R15     ( SOC, SOC, Op_RegI, 15, x15->as_VMReg()        );
  110 reg_def R15_H   ( SOC, SOC, Op_RegI, 15, x15->as_VMReg()->next());
  111 reg_def R16     ( SOC, SOC, Op_RegI, 16, x16->as_VMReg()        );
  112 reg_def R16_H   ( SOC, SOC, Op_RegI, 16, x16->as_VMReg()->next());
  113 reg_def R17     ( SOC, SOC, Op_RegI, 17, x17->as_VMReg()        );
  114 reg_def R17_H   ( SOC, SOC, Op_RegI, 17, x17->as_VMReg()->next());
  115 reg_def R18     ( SOC, SOE, Op_RegI, 18, x18->as_VMReg()        );
  116 reg_def R18_H   ( SOC, SOE, Op_RegI, 18, x18->as_VMReg()->next());
  117 reg_def R19     ( SOC, SOE, Op_RegI, 19, x19->as_VMReg()        );
  118 reg_def R19_H   ( SOC, SOE, Op_RegI, 19, x19->as_VMReg()->next());
  119 reg_def R20     ( SOC, SOE, Op_RegI, 20, x20->as_VMReg()        ); // caller esp
  120 reg_def R20_H   ( SOC, SOE, Op_RegI, 20, x20->as_VMReg()->next());
  121 reg_def R21     ( SOC, SOE, Op_RegI, 21, x21->as_VMReg()        );
  122 reg_def R21_H   ( SOC, SOE, Op_RegI, 21, x21->as_VMReg()->next());
  123 reg_def R22     ( SOC, SOE, Op_RegI, 22, x22->as_VMReg()        );
  124 reg_def R22_H   ( SOC, SOE, Op_RegI, 22, x22->as_VMReg()->next());
  125 reg_def R23     ( NS,  SOE, Op_RegI, 23, x23->as_VMReg()        ); // java thread
  126 reg_def R23_H   ( NS,  SOE, Op_RegI, 23, x23->as_VMReg()->next());
  127 reg_def R24     ( SOC, SOE, Op_RegI, 24, x24->as_VMReg()        );
  128 reg_def R24_H   ( SOC, SOE, Op_RegI, 24, x24->as_VMReg()->next());
  129 reg_def R25     ( SOC, SOE, Op_RegI, 25, x25->as_VMReg()        );
  130 reg_def R25_H   ( SOC, SOE, Op_RegI, 25, x25->as_VMReg()->next());
  131 reg_def R26     ( SOC, SOE, Op_RegI, 26, x26->as_VMReg()        );
  132 reg_def R26_H   ( SOC, SOE, Op_RegI, 26, x26->as_VMReg()->next());
  133 reg_def R27     ( SOC, SOE, Op_RegI, 27, x27->as_VMReg()        ); // heapbase
  134 reg_def R27_H   ( SOC, SOE, Op_RegI, 27, x27->as_VMReg()->next());
  135 reg_def R28     ( SOC, SOC, Op_RegI, 28, x28->as_VMReg()        );
  136 reg_def R28_H   ( SOC, SOC, Op_RegI, 28, x28->as_VMReg()->next());
  137 reg_def R29     ( SOC, SOC, Op_RegI, 29, x29->as_VMReg()        );
  138 reg_def R29_H   ( SOC, SOC, Op_RegI, 29, x29->as_VMReg()->next());
  139 reg_def R30     ( SOC, SOC, Op_RegI, 30, x30->as_VMReg()        );
  140 reg_def R30_H   ( SOC, SOC, Op_RegI, 30, x30->as_VMReg()->next());
  141 reg_def R31     ( SOC, SOC, Op_RegI, 31, x31->as_VMReg()        );
  142 reg_def R31_H   ( SOC, SOC, Op_RegI, 31, x31->as_VMReg()->next());
  143 
  144 // ----------------------------
  145 // Float/Double Registers
  146 // ----------------------------
  147 
  148 // Double Registers
  149 
  150 // The rules of ADL require that double registers be defined in pairs.
  151 // Each pair must be two 32-bit values, but not necessarily a pair of
  152 // single float registers. In each pair, ADLC-assigned register numbers
  153 // must be adjacent, with the lower number even. Finally, when the
  154 // CPU stores such a register pair to memory, the word associated with
  155 // the lower ADLC-assigned number must be stored to the lower address.
  156 
  157 // RISCV has 32 floating-point registers. Each can store a single
  158 // or double precision floating-point value.
  159 
  160 // for Java use float registers f0-f31 are always save on call whereas
  161 // the platform ABI treats f8-f9 and f18-f27 as callee save). Other
  162 // float registers are SOC as per the platform spec
  163 
  164 reg_def F0    ( SOC, SOC, Op_RegF,  0,  f0->as_VMReg()          );
  165 reg_def F0_H  ( SOC, SOC, Op_RegF,  0,  f0->as_VMReg()->next()  );
  166 reg_def F1    ( SOC, SOC, Op_RegF,  1,  f1->as_VMReg()          );
  167 reg_def F1_H  ( SOC, SOC, Op_RegF,  1,  f1->as_VMReg()->next()  );
  168 reg_def F2    ( SOC, SOC, Op_RegF,  2,  f2->as_VMReg()          );
  169 reg_def F2_H  ( SOC, SOC, Op_RegF,  2,  f2->as_VMReg()->next()  );
  170 reg_def F3    ( SOC, SOC, Op_RegF,  3,  f3->as_VMReg()          );
  171 reg_def F3_H  ( SOC, SOC, Op_RegF,  3,  f3->as_VMReg()->next()  );
  172 reg_def F4    ( SOC, SOC, Op_RegF,  4,  f4->as_VMReg()          );
  173 reg_def F4_H  ( SOC, SOC, Op_RegF,  4,  f4->as_VMReg()->next()  );
  174 reg_def F5    ( SOC, SOC, Op_RegF,  5,  f5->as_VMReg()          );
  175 reg_def F5_H  ( SOC, SOC, Op_RegF,  5,  f5->as_VMReg()->next()  );
  176 reg_def F6    ( SOC, SOC, Op_RegF,  6,  f6->as_VMReg()          );
  177 reg_def F6_H  ( SOC, SOC, Op_RegF,  6,  f6->as_VMReg()->next()  );
  178 reg_def F7    ( SOC, SOC, Op_RegF,  7,  f7->as_VMReg()          );
  179 reg_def F7_H  ( SOC, SOC, Op_RegF,  7,  f7->as_VMReg()->next()  );
  180 reg_def F8    ( SOC, SOE, Op_RegF,  8,  f8->as_VMReg()          );
  181 reg_def F8_H  ( SOC, SOE, Op_RegF,  8,  f8->as_VMReg()->next()  );
  182 reg_def F9    ( SOC, SOE, Op_RegF,  9,  f9->as_VMReg()          );
  183 reg_def F9_H  ( SOC, SOE, Op_RegF,  9,  f9->as_VMReg()->next()  );
  184 reg_def F10   ( SOC, SOC, Op_RegF,  10, f10->as_VMReg()         );
  185 reg_def F10_H ( SOC, SOC, Op_RegF,  10, f10->as_VMReg()->next() );
  186 reg_def F11   ( SOC, SOC, Op_RegF,  11, f11->as_VMReg()         );
  187 reg_def F11_H ( SOC, SOC, Op_RegF,  11, f11->as_VMReg()->next() );
  188 reg_def F12   ( SOC, SOC, Op_RegF,  12, f12->as_VMReg()         );
  189 reg_def F12_H ( SOC, SOC, Op_RegF,  12, f12->as_VMReg()->next() );
  190 reg_def F13   ( SOC, SOC, Op_RegF,  13, f13->as_VMReg()         );
  191 reg_def F13_H ( SOC, SOC, Op_RegF,  13, f13->as_VMReg()->next() );
  192 reg_def F14   ( SOC, SOC, Op_RegF,  14, f14->as_VMReg()         );
  193 reg_def F14_H ( SOC, SOC, Op_RegF,  14, f14->as_VMReg()->next() );
  194 reg_def F15   ( SOC, SOC, Op_RegF,  15, f15->as_VMReg()         );
  195 reg_def F15_H ( SOC, SOC, Op_RegF,  15, f15->as_VMReg()->next() );
  196 reg_def F16   ( SOC, SOC, Op_RegF,  16, f16->as_VMReg()         );
  197 reg_def F16_H ( SOC, SOC, Op_RegF,  16, f16->as_VMReg()->next() );
  198 reg_def F17   ( SOC, SOC, Op_RegF,  17, f17->as_VMReg()         );
  199 reg_def F17_H ( SOC, SOC, Op_RegF,  17, f17->as_VMReg()->next() );
  200 reg_def F18   ( SOC, SOE, Op_RegF,  18, f18->as_VMReg()         );
  201 reg_def F18_H ( SOC, SOE, Op_RegF,  18, f18->as_VMReg()->next() );
  202 reg_def F19   ( SOC, SOE, Op_RegF,  19, f19->as_VMReg()         );
  203 reg_def F19_H ( SOC, SOE, Op_RegF,  19, f19->as_VMReg()->next() );
  204 reg_def F20   ( SOC, SOE, Op_RegF,  20, f20->as_VMReg()         );
  205 reg_def F20_H ( SOC, SOE, Op_RegF,  20, f20->as_VMReg()->next() );
  206 reg_def F21   ( SOC, SOE, Op_RegF,  21, f21->as_VMReg()         );
  207 reg_def F21_H ( SOC, SOE, Op_RegF,  21, f21->as_VMReg()->next() );
  208 reg_def F22   ( SOC, SOE, Op_RegF,  22, f22->as_VMReg()         );
  209 reg_def F22_H ( SOC, SOE, Op_RegF,  22, f22->as_VMReg()->next() );
  210 reg_def F23   ( SOC, SOE, Op_RegF,  23, f23->as_VMReg()         );
  211 reg_def F23_H ( SOC, SOE, Op_RegF,  23, f23->as_VMReg()->next() );
  212 reg_def F24   ( SOC, SOE, Op_RegF,  24, f24->as_VMReg()         );
  213 reg_def F24_H ( SOC, SOE, Op_RegF,  24, f24->as_VMReg()->next() );
  214 reg_def F25   ( SOC, SOE, Op_RegF,  25, f25->as_VMReg()         );
  215 reg_def F25_H ( SOC, SOE, Op_RegF,  25, f25->as_VMReg()->next() );
  216 reg_def F26   ( SOC, SOE, Op_RegF,  26, f26->as_VMReg()         );
  217 reg_def F26_H ( SOC, SOE, Op_RegF,  26, f26->as_VMReg()->next() );
  218 reg_def F27   ( SOC, SOE, Op_RegF,  27, f27->as_VMReg()         );
  219 reg_def F27_H ( SOC, SOE, Op_RegF,  27, f27->as_VMReg()->next() );
  220 reg_def F28   ( SOC, SOC, Op_RegF,  28, f28->as_VMReg()         );
  221 reg_def F28_H ( SOC, SOC, Op_RegF,  28, f28->as_VMReg()->next() );
  222 reg_def F29   ( SOC, SOC, Op_RegF,  29, f29->as_VMReg()         );
  223 reg_def F29_H ( SOC, SOC, Op_RegF,  29, f29->as_VMReg()->next() );
  224 reg_def F30   ( SOC, SOC, Op_RegF,  30, f30->as_VMReg()         );
  225 reg_def F30_H ( SOC, SOC, Op_RegF,  30, f30->as_VMReg()->next() );
  226 reg_def F31   ( SOC, SOC, Op_RegF,  31, f31->as_VMReg()         );
  227 reg_def F31_H ( SOC, SOC, Op_RegF,  31, f31->as_VMReg()->next() );
  228 
  229 // ----------------------------
  230 // Vector Registers
  231 // ----------------------------
  232 
  233 // For RVV vector registers, we simply extend vector register size to 4
  234 // 'logical' slots. This is nominally 128 bits but it actually covers
  235 // all possible 'physical' RVV vector register lengths from 128 ~ 1024
  236 // bits. The 'physical' RVV vector register length is detected during
  237 // startup, so the register allocator is able to identify the correct
  238 // number of bytes needed for an RVV spill/unspill.
  239 
  240 reg_def V0    ( SOC, SOC, Op_VecA, 0,  v0->as_VMReg()           );
  241 reg_def V0_H  ( SOC, SOC, Op_VecA, 0,  v0->as_VMReg()->next()   );
  242 reg_def V0_J  ( SOC, SOC, Op_VecA, 0,  v0->as_VMReg()->next(2)  );
  243 reg_def V0_K  ( SOC, SOC, Op_VecA, 0,  v0->as_VMReg()->next(3)  );
  244 
  245 reg_def V1    ( SOC, SOC, Op_VecA, 1,  v1->as_VMReg() 	        );
  246 reg_def V1_H  ( SOC, SOC, Op_VecA, 1,  v1->as_VMReg()->next()   );
  247 reg_def V1_J  ( SOC, SOC, Op_VecA, 1,  v1->as_VMReg()->next(2)  );
  248 reg_def V1_K  ( SOC, SOC, Op_VecA, 1,  v1->as_VMReg()->next(3)  );
  249 
  250 reg_def V2    ( SOC, SOC, Op_VecA, 2,  v2->as_VMReg()           );
  251 reg_def V2_H  ( SOC, SOC, Op_VecA, 2,  v2->as_VMReg()->next()   );
  252 reg_def V2_J  ( SOC, SOC, Op_VecA, 2,  v2->as_VMReg()->next(2)  );
  253 reg_def V2_K  ( SOC, SOC, Op_VecA, 2,  v2->as_VMReg()->next(3)  );
  254 
  255 reg_def V3    ( SOC, SOC, Op_VecA, 3,  v3->as_VMReg()           );
  256 reg_def V3_H  ( SOC, SOC, Op_VecA, 3,  v3->as_VMReg()->next()   );
  257 reg_def V3_J  ( SOC, SOC, Op_VecA, 3,  v3->as_VMReg()->next(2)  );
  258 reg_def V3_K  ( SOC, SOC, Op_VecA, 3,  v3->as_VMReg()->next(3)  );
  259 
  260 reg_def V4    ( SOC, SOC, Op_VecA, 4,  v4->as_VMReg()           );
  261 reg_def V4_H  ( SOC, SOC, Op_VecA, 4,  v4->as_VMReg()->next()   );
  262 reg_def V4_J  ( SOC, SOC, Op_VecA, 4,  v4->as_VMReg()->next(2)  );
  263 reg_def V4_K  ( SOC, SOC, Op_VecA, 4,  v4->as_VMReg()->next(3)  );
  264 
  265 reg_def V5    ( SOC, SOC, Op_VecA, 5,  v5->as_VMReg() 	        );
  266 reg_def V5_H  ( SOC, SOC, Op_VecA, 5,  v5->as_VMReg()->next()   );
  267 reg_def V5_J  ( SOC, SOC, Op_VecA, 5,  v5->as_VMReg()->next(2)  );
  268 reg_def V5_K  ( SOC, SOC, Op_VecA, 5,  v5->as_VMReg()->next(3)  );
  269 
  270 reg_def V6    ( SOC, SOC, Op_VecA, 6,  v6->as_VMReg()           );
  271 reg_def V6_H  ( SOC, SOC, Op_VecA, 6,  v6->as_VMReg()->next()   );
  272 reg_def V6_J  ( SOC, SOC, Op_VecA, 6,  v6->as_VMReg()->next(2)  );
  273 reg_def V6_K  ( SOC, SOC, Op_VecA, 6,  v6->as_VMReg()->next(3)  );
  274 
  275 reg_def V7    ( SOC, SOC, Op_VecA, 7,  v7->as_VMReg() 	        );
  276 reg_def V7_H  ( SOC, SOC, Op_VecA, 7,  v7->as_VMReg()->next()   );
  277 reg_def V7_J  ( SOC, SOC, Op_VecA, 7,  v7->as_VMReg()->next(2)  );
  278 reg_def V7_K  ( SOC, SOC, Op_VecA, 7,  v7->as_VMReg()->next(3)  );
  279 
  280 reg_def V8    ( SOC, SOC, Op_VecA, 8,  v8->as_VMReg()           );
  281 reg_def V8_H  ( SOC, SOC, Op_VecA, 8,  v8->as_VMReg()->next()   );
  282 reg_def V8_J  ( SOC, SOC, Op_VecA, 8,  v8->as_VMReg()->next(2)  );
  283 reg_def V8_K  ( SOC, SOC, Op_VecA, 8,  v8->as_VMReg()->next(3)  );
  284 
  285 reg_def V9    ( SOC, SOC, Op_VecA, 9,  v9->as_VMReg()           );
  286 reg_def V9_H  ( SOC, SOC, Op_VecA, 9,  v9->as_VMReg()->next()   );
  287 reg_def V9_J  ( SOC, SOC, Op_VecA, 9,  v9->as_VMReg()->next(2)  );
  288 reg_def V9_K  ( SOC, SOC, Op_VecA, 9,  v9->as_VMReg()->next(3)  );
  289 
  290 reg_def V10   ( SOC, SOC, Op_VecA, 10, v10->as_VMReg()          );
  291 reg_def V10_H ( SOC, SOC, Op_VecA, 10, v10->as_VMReg()->next()  );
  292 reg_def V10_J ( SOC, SOC, Op_VecA, 10, v10->as_VMReg()->next(2) );
  293 reg_def V10_K ( SOC, SOC, Op_VecA, 10, v10->as_VMReg()->next(3) );
  294 
  295 reg_def V11   ( SOC, SOC, Op_VecA, 11, v11->as_VMReg()          );
  296 reg_def V11_H ( SOC, SOC, Op_VecA, 11, v11->as_VMReg()->next()  );
  297 reg_def V11_J ( SOC, SOC, Op_VecA, 11, v11->as_VMReg()->next(2) );
  298 reg_def V11_K ( SOC, SOC, Op_VecA, 11, v11->as_VMReg()->next(3) );
  299 
  300 reg_def V12   ( SOC, SOC, Op_VecA, 12, v12->as_VMReg()          );
  301 reg_def V12_H ( SOC, SOC, Op_VecA, 12, v12->as_VMReg()->next()  );
  302 reg_def V12_J ( SOC, SOC, Op_VecA, 12, v12->as_VMReg()->next(2) );
  303 reg_def V12_K ( SOC, SOC, Op_VecA, 12, v12->as_VMReg()->next(3) );
  304 
  305 reg_def V13   ( SOC, SOC, Op_VecA, 13, v13->as_VMReg()          );
  306 reg_def V13_H ( SOC, SOC, Op_VecA, 13, v13->as_VMReg()->next()  );
  307 reg_def V13_J ( SOC, SOC, Op_VecA, 13, v13->as_VMReg()->next(2) );
  308 reg_def V13_K ( SOC, SOC, Op_VecA, 13, v13->as_VMReg()->next(3) );
  309 
  310 reg_def V14   ( SOC, SOC, Op_VecA, 14, v14->as_VMReg()          );
  311 reg_def V14_H ( SOC, SOC, Op_VecA, 14, v14->as_VMReg()->next()  );
  312 reg_def V14_J ( SOC, SOC, Op_VecA, 14, v14->as_VMReg()->next(2) );
  313 reg_def V14_K ( SOC, SOC, Op_VecA, 14, v14->as_VMReg()->next(3) );
  314 
  315 reg_def V15   ( SOC, SOC, Op_VecA, 15, v15->as_VMReg()          );
  316 reg_def V15_H ( SOC, SOC, Op_VecA, 15, v15->as_VMReg()->next()  );
  317 reg_def V15_J ( SOC, SOC, Op_VecA, 15, v15->as_VMReg()->next(2) );
  318 reg_def V15_K ( SOC, SOC, Op_VecA, 15, v15->as_VMReg()->next(3) );
  319 
  320 reg_def V16   ( SOC, SOC, Op_VecA, 16, v16->as_VMReg()          );
  321 reg_def V16_H ( SOC, SOC, Op_VecA, 16, v16->as_VMReg()->next()  );
  322 reg_def V16_J ( SOC, SOC, Op_VecA, 16, v16->as_VMReg()->next(2) );
  323 reg_def V16_K ( SOC, SOC, Op_VecA, 16, v16->as_VMReg()->next(3) );
  324 
  325 reg_def V17   ( SOC, SOC, Op_VecA, 17, v17->as_VMReg()          );
  326 reg_def V17_H ( SOC, SOC, Op_VecA, 17, v17->as_VMReg()->next()  );
  327 reg_def V17_J ( SOC, SOC, Op_VecA, 17, v17->as_VMReg()->next(2) );
  328 reg_def V17_K ( SOC, SOC, Op_VecA, 17, v17->as_VMReg()->next(3) );
  329 
  330 reg_def V18   ( SOC, SOC, Op_VecA, 18, v18->as_VMReg()          );
  331 reg_def V18_H ( SOC, SOC, Op_VecA, 18, v18->as_VMReg()->next()  );
  332 reg_def V18_J ( SOC, SOC, Op_VecA, 18, v18->as_VMReg()->next(2) );
  333 reg_def V18_K ( SOC, SOC, Op_VecA, 18, v18->as_VMReg()->next(3) );
  334 
  335 reg_def V19   ( SOC, SOC, Op_VecA, 19, v19->as_VMReg()          );
  336 reg_def V19_H ( SOC, SOC, Op_VecA, 19, v19->as_VMReg()->next()  );
  337 reg_def V19_J ( SOC, SOC, Op_VecA, 19, v19->as_VMReg()->next(2) );
  338 reg_def V19_K ( SOC, SOC, Op_VecA, 19, v19->as_VMReg()->next(3) );
  339 
  340 reg_def V20   ( SOC, SOC, Op_VecA, 20, v20->as_VMReg()          );
  341 reg_def V20_H ( SOC, SOC, Op_VecA, 20, v20->as_VMReg()->next()  );
  342 reg_def V20_J ( SOC, SOC, Op_VecA, 20, v20->as_VMReg()->next(2) );
  343 reg_def V20_K ( SOC, SOC, Op_VecA, 20, v20->as_VMReg()->next(3) );
  344 
  345 reg_def V21   ( SOC, SOC, Op_VecA, 21, v21->as_VMReg()          );
  346 reg_def V21_H ( SOC, SOC, Op_VecA, 21, v21->as_VMReg()->next()  );
  347 reg_def V21_J ( SOC, SOC, Op_VecA, 21, v21->as_VMReg()->next(2) );
  348 reg_def V21_K ( SOC, SOC, Op_VecA, 21, v21->as_VMReg()->next(3) );
  349 
  350 reg_def V22   ( SOC, SOC, Op_VecA, 22, v22->as_VMReg()          );
  351 reg_def V22_H ( SOC, SOC, Op_VecA, 22, v22->as_VMReg()->next()  );
  352 reg_def V22_J ( SOC, SOC, Op_VecA, 22, v22->as_VMReg()->next(2) );
  353 reg_def V22_K ( SOC, SOC, Op_VecA, 22, v22->as_VMReg()->next(3) );
  354 
  355 reg_def V23   ( SOC, SOC, Op_VecA, 23, v23->as_VMReg()          );
  356 reg_def V23_H ( SOC, SOC, Op_VecA, 23, v23->as_VMReg()->next()  );
  357 reg_def V23_J ( SOC, SOC, Op_VecA, 23, v23->as_VMReg()->next(2) );
  358 reg_def V23_K ( SOC, SOC, Op_VecA, 23, v23->as_VMReg()->next(3) );
  359 
  360 reg_def V24   ( SOC, SOC, Op_VecA, 24, v24->as_VMReg()          );
  361 reg_def V24_H ( SOC, SOC, Op_VecA, 24, v24->as_VMReg()->next()  );
  362 reg_def V24_J ( SOC, SOC, Op_VecA, 24, v24->as_VMReg()->next(2) );
  363 reg_def V24_K ( SOC, SOC, Op_VecA, 24, v24->as_VMReg()->next(3) );
  364 
  365 reg_def V25   ( SOC, SOC, Op_VecA, 25, v25->as_VMReg()          );
  366 reg_def V25_H ( SOC, SOC, Op_VecA, 25, v25->as_VMReg()->next()  );
  367 reg_def V25_J ( SOC, SOC, Op_VecA, 25, v25->as_VMReg()->next(2) );
  368 reg_def V25_K ( SOC, SOC, Op_VecA, 25, v25->as_VMReg()->next(3) );
  369 
  370 reg_def V26   ( SOC, SOC, Op_VecA, 26, v26->as_VMReg()          );
  371 reg_def V26_H ( SOC, SOC, Op_VecA, 26, v26->as_VMReg()->next()  );
  372 reg_def V26_J ( SOC, SOC, Op_VecA, 26, v26->as_VMReg()->next(2) );
  373 reg_def V26_K ( SOC, SOC, Op_VecA, 26, v26->as_VMReg()->next(3) );
  374 
  375 reg_def V27   ( SOC, SOC, Op_VecA, 27, v27->as_VMReg()          );
  376 reg_def V27_H ( SOC, SOC, Op_VecA, 27, v27->as_VMReg()->next()  );
  377 reg_def V27_J ( SOC, SOC, Op_VecA, 27, v27->as_VMReg()->next(2) );
  378 reg_def V27_K ( SOC, SOC, Op_VecA, 27, v27->as_VMReg()->next(3) );
  379 
  380 reg_def V28   ( SOC, SOC, Op_VecA, 28, v28->as_VMReg()          );
  381 reg_def V28_H ( SOC, SOC, Op_VecA, 28, v28->as_VMReg()->next()  );
  382 reg_def V28_J ( SOC, SOC, Op_VecA, 28, v28->as_VMReg()->next(2) );
  383 reg_def V28_K ( SOC, SOC, Op_VecA, 28, v28->as_VMReg()->next(3) );
  384 
  385 reg_def V29   ( SOC, SOC, Op_VecA, 29, v29->as_VMReg()          );
  386 reg_def V29_H ( SOC, SOC, Op_VecA, 29, v29->as_VMReg()->next()  );
  387 reg_def V29_J ( SOC, SOC, Op_VecA, 29, v29->as_VMReg()->next(2) );
  388 reg_def V29_K ( SOC, SOC, Op_VecA, 29, v29->as_VMReg()->next(3) );
  389 
  390 reg_def V30   ( SOC, SOC, Op_VecA, 30, v30->as_VMReg()          );
  391 reg_def V30_H ( SOC, SOC, Op_VecA, 30, v30->as_VMReg()->next()  );
  392 reg_def V30_J ( SOC, SOC, Op_VecA, 30, v30->as_VMReg()->next(2) );
  393 reg_def V30_K ( SOC, SOC, Op_VecA, 30, v30->as_VMReg()->next(3) );
  394 
  395 reg_def V31   ( SOC, SOC, Op_VecA, 31, v31->as_VMReg()          );
  396 reg_def V31_H ( SOC, SOC, Op_VecA, 31, v31->as_VMReg()->next()  );
  397 reg_def V31_J ( SOC, SOC, Op_VecA, 31, v31->as_VMReg()->next(2) );
  398 reg_def V31_K ( SOC, SOC, Op_VecA, 31, v31->as_VMReg()->next(3) );
  399 
  400 // ----------------------------
  401 // Special Registers
  402 // ----------------------------
  403 
  404 // On riscv, the physical flag register is missing, so we use t1 instead,
  405 // to bridge the RegFlag semantics in share/opto
  406 
  407 reg_def RFLAGS   (SOC, SOC, Op_RegFlags, 6, x6->as_VMReg()        );
  408 
  409 // Specify priority of register selection within phases of register
  410 // allocation.  Highest priority is first.  A useful heuristic is to
  411 // give registers a low priority when they are required by machine
  412 // instructions, like EAX and EDX on I486, and choose no-save registers
  413 // before save-on-call, & save-on-call before save-on-entry.  Registers
  414 // which participate in fixed calling sequences should come last.
  415 // Registers which are used as pairs must fall on an even boundary.
  416 
  417 alloc_class chunk0(
  418     // volatiles
  419     R7,  R7_H,
  420     R28, R28_H,
  421     R29, R29_H,
  422     R30, R30_H,
  423     R31, R31_H,
  424 
  425     // arg registers
  426     R10, R10_H,
  427     R11, R11_H,
  428     R12, R12_H,
  429     R13, R13_H,
  430     R14, R14_H,
  431     R15, R15_H,
  432     R16, R16_H,
  433     R17, R17_H,
  434 
  435     // non-volatiles
  436     R9,  R9_H,
  437     R18, R18_H,
  438     R19, R19_H,
  439     R20, R20_H,
  440     R21, R21_H,
  441     R22, R22_H,
  442     R24, R24_H,
  443     R25, R25_H,
  444     R26, R26_H,
  445 
  446     // non-allocatable registers
  447     R23, R23_H, // java thread
  448     R27, R27_H, // heapbase
  449     R4,  R4_H,  // thread
  450     R8,  R8_H,  // fp
  451     R0,  R0_H,  // zero
  452     R1,  R1_H,  // ra
  453     R2,  R2_H,  // sp
  454     R3,  R3_H,  // gp
  455 );
  456 
  457 alloc_class chunk1(
  458 
  459     // no save
  460     F0,  F0_H,
  461     F1,  F1_H,
  462     F2,  F2_H,
  463     F3,  F3_H,
  464     F4,  F4_H,
  465     F5,  F5_H,
  466     F6,  F6_H,
  467     F7,  F7_H,
  468     F28, F28_H,
  469     F29, F29_H,
  470     F30, F30_H,
  471     F31, F31_H,
  472 
  473     // arg registers
  474     F10, F10_H,
  475     F11, F11_H,
  476     F12, F12_H,
  477     F13, F13_H,
  478     F14, F14_H,
  479     F15, F15_H,
  480     F16, F16_H,
  481     F17, F17_H,
  482 
  483     // non-volatiles
  484     F8,  F8_H,
  485     F9,  F9_H,
  486     F18, F18_H,
  487     F19, F19_H,
  488     F20, F20_H,
  489     F21, F21_H,
  490     F22, F22_H,
  491     F23, F23_H,
  492     F24, F24_H,
  493     F25, F25_H,
  494     F26, F26_H,
  495     F27, F27_H,
  496 );
  497 
  498 alloc_class chunk2(
  499     V0, V0_H, V0_J, V0_K,
  500     V1, V1_H, V1_J, V1_K,
  501     V2, V2_H, V2_J, V2_K,
  502     V3, V3_H, V3_J, V3_K,
  503     V4, V4_H, V4_J, V4_K,
  504     V5, V5_H, V5_J, V5_K,
  505     V6, V6_H, V6_J, V6_K,
  506     V7, V7_H, V7_J, V7_K,
  507     V8, V8_H, V8_J, V8_K,
  508     V9, V9_H, V9_J, V9_K,
  509     V10, V10_H, V10_J, V10_K,
  510     V11, V11_H, V11_J, V11_K,
  511     V12, V12_H, V12_J, V12_K,
  512     V13, V13_H, V13_J, V13_K,
  513     V14, V14_H, V14_J, V14_K,
  514     V15, V15_H, V15_J, V15_K,
  515     V16, V16_H, V16_J, V16_K,
  516     V17, V17_H, V17_J, V17_K,
  517     V18, V18_H, V18_J, V18_K,
  518     V19, V19_H, V19_J, V19_K,
  519     V20, V20_H, V20_J, V20_K,
  520     V21, V21_H, V21_J, V21_K,
  521     V22, V22_H, V22_J, V22_K,
  522     V23, V23_H, V23_J, V23_K,
  523     V24, V24_H, V24_J, V24_K,
  524     V25, V25_H, V25_J, V25_K,
  525     V26, V26_H, V26_J, V26_K,
  526     V27, V27_H, V27_J, V27_K,
  527     V28, V28_H, V28_J, V28_K,
  528     V29, V29_H, V29_J, V29_K,
  529     V30, V30_H, V30_J, V30_K,
  530     V31, V31_H, V31_J, V31_K,
  531 );
  532 
  533 alloc_class chunk3(RFLAGS);
  534 
  535 //----------Architecture Description Register Classes--------------------------
  536 // Several register classes are automatically defined based upon information in
  537 // this architecture description.
  538 // 1) reg_class inline_cache_reg           ( /* as def'd in frame section */ )
  539 // 2) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
  540 //
  541 
  542 // Class for all 32 bit general purpose registers
  543 reg_class all_reg32(
  544     R0,
  545     R1,
  546     R2,
  547     R3,
  548     R4,
  549     R7,
  550     R8,
  551     R9,
  552     R10,
  553     R11,
  554     R12,
  555     R13,
  556     R14,
  557     R15,
  558     R16,
  559     R17,
  560     R18,
  561     R19,
  562     R20,
  563     R21,
  564     R22,
  565     R23,
  566     R24,
  567     R25,
  568     R26,
  569     R27,
  570     R28,
  571     R29,
  572     R30,
  573     R31
  574 );
  575 
  576 // Class for any 32 bit integer registers (excluding zr)
  577 reg_class any_reg32 %{
  578   return _ANY_REG32_mask;
  579 %}
  580 
  581 // Singleton class for R10 int register
  582 reg_class int_r10_reg(R10);
  583 
  584 // Singleton class for R12 int register
  585 reg_class int_r12_reg(R12);
  586 
  587 // Singleton class for R13 int register
  588 reg_class int_r13_reg(R13);
  589 
  590 // Singleton class for R14 int register
  591 reg_class int_r14_reg(R14);
  592 
  593 // Class for all long integer registers
  594 reg_class all_reg(
  595     R0,  R0_H,
  596     R1,  R1_H,
  597     R2,  R2_H,
  598     R3,  R3_H,
  599     R4,  R4_H,
  600     R7,  R7_H,
  601     R8,  R8_H,
  602     R9,  R9_H,
  603     R10, R10_H,
  604     R11, R11_H,
  605     R12, R12_H,
  606     R13, R13_H,
  607     R14, R14_H,
  608     R15, R15_H,
  609     R16, R16_H,
  610     R17, R17_H,
  611     R18, R18_H,
  612     R19, R19_H,
  613     R20, R20_H,
  614     R21, R21_H,
  615     R22, R22_H,
  616     R23, R23_H,
  617     R24, R24_H,
  618     R25, R25_H,
  619     R26, R26_H,
  620     R27, R27_H,
  621     R28, R28_H,
  622     R29, R29_H,
  623     R30, R30_H,
  624     R31, R31_H
  625 );
  626 
  627 // Class for all long integer registers (excluding zr)
  628 reg_class any_reg %{
  629   return _ANY_REG_mask;
  630 %}
  631 
  632 // Class for non-allocatable 32 bit registers
  633 reg_class non_allocatable_reg32(
  634     R0,                       // zr
  635     R1,                       // ra
  636     R2,                       // sp
  637     R3,                       // gp
  638     R4,                       // tp
  639     R23                       // java thread
  640 );
  641 
  642 // Class for non-allocatable 64 bit registers
  643 reg_class non_allocatable_reg(
  644     R0,  R0_H,                // zr
  645     R1,  R1_H,                // ra
  646     R2,  R2_H,                // sp
  647     R3,  R3_H,                // gp
  648     R4,  R4_H,                // tp
  649     R23, R23_H                // java thread
  650 );
  651 
  652 reg_class no_special_reg32 %{
  653   return _NO_SPECIAL_REG32_mask;
  654 %}
  655 
  656 reg_class no_special_reg %{
  657   return _NO_SPECIAL_REG_mask;
  658 %}
  659 
  660 reg_class ptr_reg %{
  661   return _PTR_REG_mask;
  662 %}
  663 
  664 reg_class no_special_ptr_reg %{
  665   return _NO_SPECIAL_PTR_REG_mask;
  666 %}
  667 
  668 // Class for 64 bit register r10
  669 reg_class r10_reg(
  670     R10, R10_H
  671 );
  672 
  673 // Class for 64 bit register r11
  674 reg_class r11_reg(
  675     R11, R11_H
  676 );
  677 
  678 // Class for 64 bit register r12
  679 reg_class r12_reg(
  680     R12, R12_H
  681 );
  682 
  683 // Class for 64 bit register r13
  684 reg_class r13_reg(
  685     R13, R13_H
  686 );
  687 
  688 // Class for 64 bit register r14
  689 reg_class r14_reg(
  690     R14, R14_H
  691 );
  692 
  693 // Class for 64 bit register r15
  694 reg_class r15_reg(
  695     R15, R15_H
  696 );
  697 
  698 // Class for 64 bit register r16
  699 reg_class r16_reg(
  700     R16, R16_H
  701 );
  702 
  703 // Class for method register
  704 reg_class method_reg(
  705     R31, R31_H
  706 );
  707 
  708 // Class for heapbase register
  709 reg_class heapbase_reg(
  710     R27, R27_H
  711 );
  712 
  713 // Class for java thread register
  714 reg_class java_thread_reg(
  715     R23, R23_H
  716 );
  717 
  718 reg_class r28_reg(
  719     R28, R28_H
  720 );
  721 
  722 reg_class r29_reg(
  723     R29, R29_H
  724 );
  725 
  726 reg_class r30_reg(
  727     R30, R30_H
  728 );
  729 
  730 // Class for zero registesr
  731 reg_class zr_reg(
  732     R0, R0_H
  733 );
  734 
  735 // Class for thread register
  736 reg_class thread_reg(
  737     R4, R4_H
  738 );
  739 
  740 // Class for frame pointer register
  741 reg_class fp_reg(
  742     R8, R8_H
  743 );
  744 
  745 // Class for link register
  746 reg_class ra_reg(
  747     R1, R1_H
  748 );
  749 
  750 // Class for long sp register
  751 reg_class sp_reg(
  752     R2, R2_H
  753 );
  754 
  755 // Class for all float registers
  756 reg_class float_reg(
  757     F0,
  758     F1,
  759     F2,
  760     F3,
  761     F4,
  762     F5,
  763     F6,
  764     F7,
  765     F8,
  766     F9,
  767     F10,
  768     F11,
  769     F12,
  770     F13,
  771     F14,
  772     F15,
  773     F16,
  774     F17,
  775     F18,
  776     F19,
  777     F20,
  778     F21,
  779     F22,
  780     F23,
  781     F24,
  782     F25,
  783     F26,
  784     F27,
  785     F28,
  786     F29,
  787     F30,
  788     F31
  789 );
  790 
  791 // Double precision float registers have virtual `high halves' that
  792 // are needed by the allocator.
  793 // Class for all double registers
  794 reg_class double_reg(
  795     F0,  F0_H,
  796     F1,  F1_H,
  797     F2,  F2_H,
  798     F3,  F3_H,
  799     F4,  F4_H,
  800     F5,  F5_H,
  801     F6,  F6_H,
  802     F7,  F7_H,
  803     F8,  F8_H,
  804     F9,  F9_H,
  805     F10, F10_H,
  806     F11, F11_H,
  807     F12, F12_H,
  808     F13, F13_H,
  809     F14, F14_H,
  810     F15, F15_H,
  811     F16, F16_H,
  812     F17, F17_H,
  813     F18, F18_H,
  814     F19, F19_H,
  815     F20, F20_H,
  816     F21, F21_H,
  817     F22, F22_H,
  818     F23, F23_H,
  819     F24, F24_H,
  820     F25, F25_H,
  821     F26, F26_H,
  822     F27, F27_H,
  823     F28, F28_H,
  824     F29, F29_H,
  825     F30, F30_H,
  826     F31, F31_H
  827 );
  828 
  829 // Class for all RVV vector registers
  830 reg_class vectora_reg(
  831     V1, V1_H, V1_J, V1_K,
  832     V2, V2_H, V2_J, V2_K,
  833     V3, V3_H, V3_J, V3_K,
  834     V4, V4_H, V4_J, V4_K,
  835     V5, V5_H, V5_J, V5_K,
  836     V6, V6_H, V6_J, V6_K,
  837     V7, V7_H, V7_J, V7_K,
  838     V8, V8_H, V8_J, V8_K,
  839     V9, V9_H, V9_J, V9_K,
  840     V10, V10_H, V10_J, V10_K,
  841     V11, V11_H, V11_J, V11_K,
  842     V12, V12_H, V12_J, V12_K,
  843     V13, V13_H, V13_J, V13_K,
  844     V14, V14_H, V14_J, V14_K,
  845     V15, V15_H, V15_J, V15_K,
  846     V16, V16_H, V16_J, V16_K,
  847     V17, V17_H, V17_J, V17_K,
  848     V18, V18_H, V18_J, V18_K,
  849     V19, V19_H, V19_J, V19_K,
  850     V20, V20_H, V20_J, V20_K,
  851     V21, V21_H, V21_J, V21_K,
  852     V22, V22_H, V22_J, V22_K,
  853     V23, V23_H, V23_J, V23_K,
  854     V24, V24_H, V24_J, V24_K,
  855     V25, V25_H, V25_J, V25_K,
  856     V26, V26_H, V26_J, V26_K,
  857     V27, V27_H, V27_J, V27_K,
  858     V28, V28_H, V28_J, V28_K,
  859     V29, V29_H, V29_J, V29_K,
  860     V30, V30_H, V30_J, V30_K,
  861     V31, V31_H, V31_J, V31_K
  862 );
  863 
  864 // Class for 64 bit register f0
  865 reg_class f0_reg(
  866     F0, F0_H
  867 );
  868 
  869 // Class for 64 bit register f1
  870 reg_class f1_reg(
  871     F1, F1_H
  872 );
  873 
  874 // Class for 64 bit register f2
  875 reg_class f2_reg(
  876     F2, F2_H
  877 );
  878 
  879 // Class for 64 bit register f3
  880 reg_class f3_reg(
  881     F3, F3_H
  882 );
  883 
  884 // class for vector register v1
  885 reg_class v1_reg(
  886     V1, V1_H, V1_J, V1_K
  887 );
  888 
  889 // class for vector register v2
  890 reg_class v2_reg(
  891     V2, V2_H, V2_J, V2_K
  892 );
  893 
  894 // class for vector register v3
  895 reg_class v3_reg(
  896     V3, V3_H, V3_J, V3_K
  897 );
  898 
  899 // class for vector register v4
  900 reg_class v4_reg(
  901     V4, V4_H, V4_J, V4_K
  902 );
  903 
  904 // class for vector register v5
  905 reg_class v5_reg(
  906     V5, V5_H, V5_J, V5_K
  907 );
  908 
  909 // class for condition codes
  910 reg_class reg_flags(RFLAGS);
  911 %}
  912 
  913 //----------DEFINITION BLOCK---------------------------------------------------
  914 // Define name --> value mappings to inform the ADLC of an integer valued name
  915 // Current support includes integer values in the range [0, 0x7FFFFFFF]
  916 // Format:
  917 //        int_def  <name>         ( <int_value>, <expression>);
  918 // Generated Code in ad_<arch>.hpp
  919 //        #define  <name>   (<expression>)
  920 //        // value == <int_value>
  921 // Generated code in ad_<arch>.cpp adlc_verification()
  922 //        assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
  923 //
  924 
  925 // we follow the ppc-aix port in using a simple cost model which ranks
  926 // register operations as cheap, memory ops as more expensive and
  927 // branches as most expensive. the first two have a low as well as a
  928 // normal cost. huge cost appears to be a way of saying don't do
  929 // something
  930 
  931 definitions %{
  932   // The default cost (of a register move instruction).
  933   int_def DEFAULT_COST         (  100,               100);
  934   int_def ALU_COST             (  100,  1 * DEFAULT_COST);          // unknown, const, arith, shift, slt,
  935                                                                     // multi, auipc, nop, logical, move
  936   int_def LOAD_COST            (  300,  3 * DEFAULT_COST);          // load, fpload
  937   int_def STORE_COST           (  100,  1 * DEFAULT_COST);          // store, fpstore
  938   int_def XFER_COST            (  300,  3 * DEFAULT_COST);          // mfc, mtc, fcvt, fmove, fcmp
  939   int_def BRANCH_COST          (  100,  1 * DEFAULT_COST);          // branch, jmp, call
  940   int_def IMUL_COST            ( 1000, 10 * DEFAULT_COST);          // imul
  941   int_def IDIVSI_COST          ( 3400, 34 * DEFAULT_COST);          // idivdi
  942   int_def IDIVDI_COST          ( 6600, 66 * DEFAULT_COST);          // idivsi
  943   int_def FMUL_SINGLE_COST     (  500,  5 * DEFAULT_COST);          // fadd, fmul, fmadd
  944   int_def FMUL_DOUBLE_COST     (  700,  7 * DEFAULT_COST);          // fadd, fmul, fmadd
  945   int_def FDIV_COST            ( 2000, 20 * DEFAULT_COST);          // fdiv
  946   int_def FSQRT_COST           ( 2500, 25 * DEFAULT_COST);          // fsqrt
  947   int_def VOLATILE_REF_COST    ( 1000, 10 * DEFAULT_COST);
  948 %}
  949 
  950 
  951 
  952 //----------SOURCE BLOCK-------------------------------------------------------
  953 // This is a block of C++ code which provides values, functions, and
  954 // definitions necessary in the rest of the architecture description
  955 
  956 source_hpp %{
  957 
  958 #include "asm/macroAssembler.hpp"
  959 #include "gc/shared/cardTable.hpp"
  960 #include "gc/shared/cardTableBarrierSet.hpp"
  961 #include "gc/shared/collectedHeap.hpp"
  962 #include "opto/addnode.hpp"
  963 #include "opto/convertnode.hpp"
  964 
  965 extern RegMask _ANY_REG32_mask;
  966 extern RegMask _ANY_REG_mask;
  967 extern RegMask _PTR_REG_mask;
  968 extern RegMask _NO_SPECIAL_REG32_mask;
  969 extern RegMask _NO_SPECIAL_REG_mask;
  970 extern RegMask _NO_SPECIAL_PTR_REG_mask;
  971 
  972 class CallStubImpl {
  973 
  974   //--------------------------------------------------------------
  975   //---<  Used for optimization in Compile::shorten_branches  >---
  976   //--------------------------------------------------------------
  977 
  978  public:
  979   // Size of call trampoline stub.
  980   static uint size_call_trampoline() {
  981     return 0; // no call trampolines on this platform
  982   }
  983 
  984   // number of relocations needed by a call trampoline stub
  985   static uint reloc_call_trampoline() {
  986     return 0; // no call trampolines on this platform
  987   }
  988 };
  989 
  990 class HandlerImpl {
  991 
  992  public:
  993 
  994   static int emit_exception_handler(CodeBuffer &cbuf);
  995   static int emit_deopt_handler(CodeBuffer& cbuf);
  996 
  997   static uint size_exception_handler() {
  998     return MacroAssembler::far_branch_size();
  999   }
 1000 
 1001   static uint size_deopt_handler() {
 1002     // count auipc + far branch
 1003     return NativeInstruction::instruction_size + MacroAssembler::far_branch_size();
 1004   }
 1005 };
 1006 
 1007 class Node::PD {
 1008 public:
 1009   enum NodeFlags {
 1010     _last_flag = Node::_last_flag
 1011   };
 1012 };
 1013 
 1014 bool is_CAS(int opcode, bool maybe_volatile);
 1015 
 1016 // predicate controlling translation of CompareAndSwapX
 1017 bool needs_acquiring_load_reserved(const Node *load);
 1018 
 1019 // predicate controlling addressing modes
 1020 bool size_fits_all_mem_uses(AddPNode* addp, int shift);
 1021 %}
 1022 
 1023 source %{
 1024 
 1025 // Derived RegMask with conditionally allocatable registers
 1026 
 1027 RegMask _ANY_REG32_mask;
 1028 RegMask _ANY_REG_mask;
 1029 RegMask _PTR_REG_mask;
 1030 RegMask _NO_SPECIAL_REG32_mask;
 1031 RegMask _NO_SPECIAL_REG_mask;
 1032 RegMask _NO_SPECIAL_PTR_REG_mask;
 1033 
 1034 void reg_mask_init() {
 1035 
 1036   _ANY_REG32_mask = _ALL_REG32_mask;
 1037   _ANY_REG32_mask.Remove(OptoReg::as_OptoReg(x0->as_VMReg()));
 1038 
 1039   _ANY_REG_mask = _ALL_REG_mask;
 1040   _ANY_REG_mask.SUBTRACT(_ZR_REG_mask);
 1041 
 1042   _PTR_REG_mask = _ALL_REG_mask;
 1043   _PTR_REG_mask.SUBTRACT(_ZR_REG_mask);
 1044 
 1045   _NO_SPECIAL_REG32_mask = _ALL_REG32_mask;
 1046   _NO_SPECIAL_REG32_mask.SUBTRACT(_NON_ALLOCATABLE_REG32_mask);
 1047 
 1048   _NO_SPECIAL_REG_mask = _ALL_REG_mask;
 1049   _NO_SPECIAL_REG_mask.SUBTRACT(_NON_ALLOCATABLE_REG_mask);
 1050 
 1051   _NO_SPECIAL_PTR_REG_mask = _ALL_REG_mask;
 1052   _NO_SPECIAL_PTR_REG_mask.SUBTRACT(_NON_ALLOCATABLE_REG_mask);
 1053 
 1054   // x27 is not allocatable when compressed oops is on
 1055   if (UseCompressedOops) {
 1056     _NO_SPECIAL_REG32_mask.Remove(OptoReg::as_OptoReg(x27->as_VMReg()));
 1057     _NO_SPECIAL_REG_mask.SUBTRACT(_HEAPBASE_REG_mask);
 1058     _NO_SPECIAL_PTR_REG_mask.SUBTRACT(_HEAPBASE_REG_mask);
 1059   }
 1060 
 1061   // x8 is not allocatable when PreserveFramePointer is on
 1062   if (PreserveFramePointer) {
 1063     _NO_SPECIAL_REG32_mask.Remove(OptoReg::as_OptoReg(x8->as_VMReg()));
 1064     _NO_SPECIAL_REG_mask.SUBTRACT(_FP_REG_mask);
 1065     _NO_SPECIAL_PTR_REG_mask.SUBTRACT(_FP_REG_mask);
 1066   }
 1067 }
 1068 
 1069 void PhaseOutput::pd_perform_mach_node_analysis() {
 1070 }
 1071 
 1072 int MachNode::pd_alignment_required() const {
 1073   return 1;
 1074 }
 1075 
 1076 int MachNode::compute_padding(int current_offset) const {
 1077   return 0;
 1078 }
 1079 
 1080 // is_CAS(int opcode, bool maybe_volatile)
 1081 //
 1082 // return true if opcode is one of the possible CompareAndSwapX
 1083 // values otherwise false.
 1084 bool is_CAS(int opcode, bool maybe_volatile)
 1085 {
 1086   switch (opcode) {
 1087     // We handle these
 1088     case Op_CompareAndSwapI:
 1089     case Op_CompareAndSwapL:
 1090     case Op_CompareAndSwapP:
 1091     case Op_CompareAndSwapN:
 1092     case Op_ShenandoahCompareAndSwapP:
 1093     case Op_ShenandoahCompareAndSwapN:
 1094     case Op_CompareAndSwapB:
 1095     case Op_CompareAndSwapS:
 1096     case Op_GetAndSetI:
 1097     case Op_GetAndSetL:
 1098     case Op_GetAndSetP:
 1099     case Op_GetAndSetN:
 1100     case Op_GetAndAddI:
 1101     case Op_GetAndAddL:
 1102       return true;
 1103     case Op_CompareAndExchangeI:
 1104     case Op_CompareAndExchangeN:
 1105     case Op_CompareAndExchangeB:
 1106     case Op_CompareAndExchangeS:
 1107     case Op_CompareAndExchangeL:
 1108     case Op_CompareAndExchangeP:
 1109     case Op_WeakCompareAndSwapB:
 1110     case Op_WeakCompareAndSwapS:
 1111     case Op_WeakCompareAndSwapI:
 1112     case Op_WeakCompareAndSwapL:
 1113     case Op_WeakCompareAndSwapP:
 1114     case Op_WeakCompareAndSwapN:
 1115     case Op_ShenandoahWeakCompareAndSwapP:
 1116     case Op_ShenandoahWeakCompareAndSwapN:
 1117     case Op_ShenandoahCompareAndExchangeP:
 1118     case Op_ShenandoahCompareAndExchangeN:
 1119       return maybe_volatile;
 1120     default:
 1121       return false;
 1122   }
 1123 }
 1124 
 1125 // predicate controlling translation of CAS
 1126 //
 1127 // returns true if CAS needs to use an acquiring load otherwise false
 1128 bool needs_acquiring_load_reserved(const Node *n)
 1129 {
 1130   assert(n != NULL && is_CAS(n->Opcode(), true), "expecting a compare and swap");
 1131 
 1132   LoadStoreNode* ldst = n->as_LoadStore();
 1133   if (n != NULL && is_CAS(n->Opcode(), false)) {
 1134     assert(ldst != NULL && ldst->trailing_membar() != NULL, "expected trailing membar");
 1135   } else {
 1136     return ldst != NULL && ldst->trailing_membar() != NULL;
 1137   }
 1138   // so we can just return true here
 1139   return true;
 1140 }
 1141 #define __ _masm.
 1142 
 1143 // advance declarations for helper functions to convert register
 1144 // indices to register objects
 1145 
 1146 // the ad file has to provide implementations of certain methods
 1147 // expected by the generic code
 1148 //
 1149 // REQUIRED FUNCTIONALITY
 1150 
 1151 //=============================================================================
 1152 
 1153 // !!!!! Special hack to get all types of calls to specify the byte offset
 1154 //       from the start of the call to the point where the return address
 1155 //       will point.
 1156 
 1157 int MachCallStaticJavaNode::ret_addr_offset()
 1158 {
 1159   // jal
 1160   return 1 * NativeInstruction::instruction_size;
 1161 }
 1162 
 1163 int MachCallDynamicJavaNode::ret_addr_offset()
 1164 {
 1165   return 7 * NativeInstruction::instruction_size; // movptr, jal
 1166 }
 1167 
 1168 int MachCallRuntimeNode::ret_addr_offset() {
 1169   // for generated stubs the call will be
 1170   //   jal(addr)
 1171   // or with far branches
 1172   //   jal(trampoline_stub)
 1173   // for real runtime callouts it will be 11 instructions
 1174   // see riscv_enc_java_to_runtime
 1175   //   la(t1, retaddr)                ->  auipc + addi
 1176   //   la(t0, RuntimeAddress(addr))   ->  lui + addi + slli + addi + slli + addi
 1177   //   addi(sp, sp, -2 * wordSize)    ->  addi
 1178   //   sd(t1, Address(sp, wordSize))  ->  sd
 1179   //   jalr(t0)                       ->  jalr
 1180   CodeBlob *cb = CodeCache::find_blob(_entry_point);
 1181   if (cb != NULL) {
 1182     return 1 * NativeInstruction::instruction_size;
 1183   } else {
 1184     return 11 * NativeInstruction::instruction_size;
 1185   }
 1186 }
 1187 
 1188 //
 1189 // Compute padding required for nodes which need alignment
 1190 //
 1191 
 1192 // With RVC a call instruction may get 2-byte aligned.
 1193 // The address of the call instruction needs to be 4-byte aligned to
 1194 // ensure that it does not span a cache line so that it can be patched.
 1195 int CallStaticJavaDirectNode::compute_padding(int current_offset) const
 1196 {
 1197   // to make sure the address of jal 4-byte aligned.
 1198   return align_up(current_offset, alignment_required()) - current_offset;
 1199 }
 1200 
 1201 // With RVC a call instruction may get 2-byte aligned.
 1202 // The address of the call instruction needs to be 4-byte aligned to
 1203 // ensure that it does not span a cache line so that it can be patched.
 1204 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const
 1205 {
 1206   // skip the movptr in MacroAssembler::ic_call():
 1207   // lui + addi + slli + addi + slli + addi
 1208   // Though movptr() has already 4-byte aligned with or without RVC,
 1209   // We need to prevent from further changes by explicitly calculating the size.
 1210   const int movptr_size = 6 * NativeInstruction::instruction_size;
 1211   current_offset += movptr_size;
 1212   // to make sure the address of jal 4-byte aligned.
 1213   return align_up(current_offset, alignment_required()) - current_offset;
 1214 }
 1215 
 1216 //=============================================================================
 1217 
 1218 #ifndef PRODUCT
 1219 void MachBreakpointNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
 1220   assert_cond(st != NULL);
 1221   st->print("BREAKPOINT");
 1222 }
 1223 #endif
 1224 
 1225 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
 1226   C2_MacroAssembler _masm(&cbuf);
 1227   Assembler::CompressibleRegion cr(&_masm);
 1228   __ ebreak();
 1229 }
 1230 
 1231 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
 1232   return MachNode::size(ra_);
 1233 }
 1234 
 1235 //=============================================================================
 1236 
 1237 #ifndef PRODUCT
 1238   void MachNopNode::format(PhaseRegAlloc*, outputStream* st) const {
 1239     st->print("nop \t# %d bytes pad for loops and calls", _count);
 1240   }
 1241 #endif
 1242 
 1243   void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc*) const {
 1244     C2_MacroAssembler _masm(&cbuf);
 1245     Assembler::CompressibleRegion cr(&_masm); // nops shall be 2-byte under RVC for alignment purposes.
 1246     for (int i = 0; i < _count; i++) {
 1247       __ nop();
 1248     }
 1249   }
 1250 
 1251   uint MachNopNode::size(PhaseRegAlloc*) const {
 1252     return _count * (UseRVC ? NativeInstruction::compressed_instruction_size : NativeInstruction::instruction_size);
 1253   }
 1254 
 1255 //=============================================================================
 1256 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;
 1257 
 1258 int ConstantTable::calculate_table_base_offset() const {
 1259   return 0;  // absolute addressing, no offset
 1260 }
 1261 
 1262 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
 1263 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
 1264   ShouldNotReachHere();
 1265 }
 1266 
 1267 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
 1268   // Empty encoding
 1269 }
 1270 
 1271 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
 1272   return 0;
 1273 }
 1274 
 1275 #ifndef PRODUCT
 1276 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
 1277   assert_cond(st != NULL);
 1278   st->print("-- \t// MachConstantBaseNode (empty encoding)");
 1279 }
 1280 #endif
 1281 
 1282 #ifndef PRODUCT
 1283 void MachPrologNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
 1284   assert_cond(st != NULL && ra_ != NULL);
 1285   Compile* C = ra_->C;
 1286 
 1287   int framesize = C->output()->frame_slots() << LogBytesPerInt;
 1288 
 1289   if (C->output()->need_stack_bang(framesize)) {
 1290     st->print("# stack bang size=%d\n\t", framesize);
 1291   }
 1292 
 1293   st->print("sd  fp, [sp, #%d]\n\t", - 2 * wordSize);
 1294   st->print("sd  ra, [sp, #%d]\n\t", - wordSize);
 1295   if (PreserveFramePointer) { st->print("sub  fp, sp, #%d\n\t", 2 * wordSize); }
 1296   st->print("sub sp, sp, #%d\n\t", framesize);
 1297 
 1298   if (C->stub_function() == NULL && BarrierSet::barrier_set()->barrier_set_nmethod() != NULL) {
 1299     st->print("ld  t0, [guard]\n\t");
 1300     st->print("membar LoadLoad\n\t");
 1301     st->print("ld  t1, [xthread, #thread_disarmed_offset]\n\t");
 1302     st->print("beq t0, t1, skip\n\t");
 1303     st->print("jalr #nmethod_entry_barrier_stub\n\t");
 1304     st->print("j skip\n\t");
 1305     st->print("guard: int\n\t");
 1306     st->print("skip:\n\t");
 1307   }
 1308 }
 1309 #endif
 1310 
 1311 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
 1312   assert_cond(ra_ != NULL);
 1313   Compile* C = ra_->C;
 1314   C2_MacroAssembler _masm(&cbuf);
 1315 
 1316   // n.b. frame size includes space for return pc and fp
 1317   const int framesize = C->output()->frame_size_in_bytes();
 1318 
 1319   // insert a nop at the start of the prolog so we can patch in a
 1320   // branch if we need to invalidate the method later
 1321   MacroAssembler::assert_alignment(__ pc());
 1322   __ nop();
 1323 
 1324   assert_cond(C != NULL);
 1325 
 1326   if (C->clinit_barrier_on_entry()) {
 1327     assert(!C->method()->holder()->is_not_initialized(), "initialization should have been started");
 1328 
 1329     Label L_skip_barrier;
 1330 
 1331     __ mov_metadata(t1, C->method()->holder()->constant_encoding());
 1332     __ clinit_barrier(t1, t0, &L_skip_barrier);
 1333     __ far_jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub()));
 1334     __ bind(L_skip_barrier);
 1335   }
 1336 
 1337   int bangsize = C->output()->bang_size_in_bytes();
 1338   if (C->output()->need_stack_bang(bangsize)) {
 1339     __ generate_stack_overflow_check(bangsize);
 1340   }
 1341 
 1342   __ build_frame(framesize);
 1343 
 1344   if (C->stub_function() == NULL) {
 1345     BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
 1346     if (BarrierSet::barrier_set()->barrier_set_nmethod() != NULL) {
 1347       // Dummy labels for just measuring the code size
 1348       Label dummy_slow_path;
 1349       Label dummy_continuation;
 1350       Label dummy_guard;
 1351       Label* slow_path = &dummy_slow_path;
 1352       Label* continuation = &dummy_continuation;
 1353       Label* guard = &dummy_guard;
 1354       if (!Compile::current()->output()->in_scratch_emit_size()) {
 1355         // Use real labels from actual stub when not emitting code for purpose of measuring its size
 1356         C2EntryBarrierStub* stub = Compile::current()->output()->entry_barrier_table()->add_entry_barrier();
 1357         slow_path = &stub->slow_path();
 1358         continuation = &stub->continuation();
 1359         guard = &stub->guard();
 1360       }
 1361       // In the C2 code, we move the non-hot part of nmethod entry barriers out-of-line to a stub.
 1362       bs->nmethod_entry_barrier(&_masm, slow_path, continuation, guard);
 1363     }
 1364   }
 1365 
 1366   if (VerifyStackAtCalls) {
 1367     Unimplemented();
 1368   }
 1369 
 1370   C->output()->set_frame_complete(cbuf.insts_size());
 1371 
 1372   if (C->has_mach_constant_base_node()) {
 1373     // NOTE: We set the table base offset here because users might be
 1374     // emitted before MachConstantBaseNode.
 1375     ConstantTable& constant_table = C->output()->constant_table();
 1376     constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
 1377   }
 1378 }
 1379 
 1380 uint MachPrologNode::size(PhaseRegAlloc* ra_) const
 1381 {
 1382   assert_cond(ra_ != NULL);
 1383   return MachNode::size(ra_); // too many variables; just compute it
 1384                               // the hard way
 1385 }
 1386 
 1387 int MachPrologNode::reloc() const
 1388 {
 1389   return 0;
 1390 }
 1391 
 1392 //=============================================================================
 1393 
 1394 #ifndef PRODUCT
 1395 void MachEpilogNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
 1396   assert_cond(st != NULL && ra_ != NULL);
 1397   Compile* C = ra_->C;
 1398   assert_cond(C != NULL);
 1399   int framesize = C->output()->frame_size_in_bytes();
 1400 
 1401   st->print("# pop frame %d\n\t", framesize);
 1402 
 1403   if (framesize == 0) {
 1404     st->print("ld  ra, [sp,#%d]\n\t", (2 * wordSize));
 1405     st->print("ld  fp, [sp,#%d]\n\t", (3 * wordSize));
 1406     st->print("add sp, sp, #%d\n\t", (2 * wordSize));
 1407   } else {
 1408     st->print("add  sp, sp, #%d\n\t", framesize);
 1409     st->print("ld  ra, [sp,#%d]\n\t", - 2 * wordSize);
 1410     st->print("ld  fp, [sp,#%d]\n\t", - wordSize);
 1411   }
 1412 
 1413   if (do_polling() && C->is_method_compilation()) {
 1414     st->print("# test polling word\n\t");
 1415     st->print("ld t0, [xthread,#%d]\n\t", in_bytes(JavaThread::polling_word_offset()));
 1416     st->print("bgtu sp, t0, #slow_path");
 1417   }
 1418 }
 1419 #endif
 1420 
 1421 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
 1422   assert_cond(ra_ != NULL);
 1423   Compile* C = ra_->C;
 1424   C2_MacroAssembler _masm(&cbuf);
 1425   assert_cond(C != NULL);
 1426   int framesize = C->output()->frame_size_in_bytes();
 1427 
 1428   __ remove_frame(framesize);
 1429 
 1430   if (StackReservedPages > 0 && C->has_reserved_stack_access()) {
 1431     __ reserved_stack_check();
 1432   }
 1433 
 1434   if (do_polling() && C->is_method_compilation()) {
 1435     Label dummy_label;
 1436     Label* code_stub = &dummy_label;
 1437     if (!C->output()->in_scratch_emit_size()) {
 1438       code_stub = &C->output()->safepoint_poll_table()->add_safepoint(__ offset());
 1439     }
 1440     __ relocate(relocInfo::poll_return_type);
 1441     __ safepoint_poll(*code_stub, true /* at_return */, false /* acquire */, true /* in_nmethod */);
 1442   }
 1443 }
 1444 
 1445 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
 1446   assert_cond(ra_ != NULL);
 1447   // Variable size. Determine dynamically.
 1448   return MachNode::size(ra_);
 1449 }
 1450 
 1451 int MachEpilogNode::reloc() const {
 1452   // Return number of relocatable values contained in this instruction.
 1453   return 1; // 1 for polling page.
 1454 }
 1455 const Pipeline * MachEpilogNode::pipeline() const {
 1456   return MachNode::pipeline_class();
 1457 }
 1458 
 1459 //=============================================================================
 1460 
 1461 // Figure out which register class each belongs in: rc_int, rc_float or
 1462 // rc_stack.
 1463 enum RC { rc_bad, rc_int, rc_float, rc_vector, rc_stack };
 1464 
 1465 static enum RC rc_class(OptoReg::Name reg) {
 1466 
 1467   if (reg == OptoReg::Bad) {
 1468     return rc_bad;
 1469   }
 1470 
 1471   // we have 30 int registers * 2 halves
 1472   // (t0 and t1 are omitted)
 1473   int slots_of_int_registers = Register::max_slots_per_register * (Register::number_of_registers - 2);
 1474   if (reg < slots_of_int_registers) {
 1475     return rc_int;
 1476   }
 1477 
 1478   // we have 32 float register * 2 halves
 1479   int slots_of_float_registers = FloatRegister::max_slots_per_register * FloatRegister::number_of_registers;
 1480   if (reg < slots_of_int_registers + slots_of_float_registers) {
 1481     return rc_float;
 1482   }
 1483 
 1484   // we have 32 vector register * 4 halves
 1485   int slots_of_vector_registers = VectorRegister::max_slots_per_register * VectorRegister::number_of_registers;
 1486   if (reg < slots_of_int_registers + slots_of_float_registers + slots_of_vector_registers) {
 1487     return rc_vector;
 1488   }
 1489 
 1490   // Between vector regs & stack is the flags regs.
 1491   assert(OptoReg::is_stack(reg), "blow up if spilling flags");
 1492 
 1493   return rc_stack;
 1494 }
 1495 
 1496 uint MachSpillCopyNode::implementation(CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream *st) const {
 1497   assert_cond(ra_ != NULL);
 1498   Compile* C = ra_->C;
 1499 
 1500   // Get registers to move.
 1501   OptoReg::Name src_hi = ra_->get_reg_second(in(1));
 1502   OptoReg::Name src_lo = ra_->get_reg_first(in(1));
 1503   OptoReg::Name dst_hi = ra_->get_reg_second(this);
 1504   OptoReg::Name dst_lo = ra_->get_reg_first(this);
 1505 
 1506   enum RC src_hi_rc = rc_class(src_hi);
 1507   enum RC src_lo_rc = rc_class(src_lo);
 1508   enum RC dst_hi_rc = rc_class(dst_hi);
 1509   enum RC dst_lo_rc = rc_class(dst_lo);
 1510 
 1511   assert(src_lo != OptoReg::Bad && dst_lo != OptoReg::Bad, "must move at least 1 register");
 1512 
 1513   if (src_hi != OptoReg::Bad) {
 1514     assert((src_lo & 1) == 0 && src_lo + 1 == src_hi &&
 1515            (dst_lo & 1) == 0 && dst_lo + 1 == dst_hi,
 1516            "expected aligned-adjacent pairs");
 1517   }
 1518 
 1519   if (src_lo == dst_lo && src_hi == dst_hi) {
 1520     return 0;            // Self copy, no move.
 1521   }
 1522 
 1523   bool is64 = (src_lo & 1) == 0 && src_lo + 1 == src_hi &&
 1524               (dst_lo & 1) == 0 && dst_lo + 1 == dst_hi;
 1525   int src_offset = ra_->reg2offset(src_lo);
 1526   int dst_offset = ra_->reg2offset(dst_lo);
 1527 
 1528   if (bottom_type()->isa_vect() != NULL) {
 1529     uint ireg = ideal_reg();
 1530     if (ireg == Op_VecA && cbuf) {
 1531       C2_MacroAssembler _masm(cbuf);
 1532       Assembler::CompressibleRegion cr(&_masm);
 1533       int vector_reg_size_in_bytes = Matcher::scalable_vector_reg_size(T_BYTE);
 1534       if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
 1535         // stack to stack
 1536         __ spill_copy_vector_stack_to_stack(src_offset, dst_offset,
 1537                                             vector_reg_size_in_bytes);
 1538       } else if (src_lo_rc == rc_vector && dst_lo_rc == rc_stack) {
 1539         // vpr to stack
 1540         __ spill(as_VectorRegister(Matcher::_regEncode[src_lo]), ra_->reg2offset(dst_lo));
 1541       } else if (src_lo_rc == rc_stack && dst_lo_rc == rc_vector) {
 1542         // stack to vpr
 1543         __ unspill(as_VectorRegister(Matcher::_regEncode[dst_lo]), ra_->reg2offset(src_lo));
 1544       } else if (src_lo_rc == rc_vector && dst_lo_rc == rc_vector) {
 1545         // vpr to vpr
 1546         __ vmv1r_v(as_VectorRegister(Matcher::_regEncode[dst_lo]), as_VectorRegister(Matcher::_regEncode[src_lo]));
 1547       } else {
 1548         ShouldNotReachHere();
 1549       }
 1550     }
 1551   } else if (cbuf != NULL) {
 1552     C2_MacroAssembler _masm(cbuf);
 1553     Assembler::CompressibleRegion cr(&_masm);
 1554     switch (src_lo_rc) {
 1555       case rc_int:
 1556         if (dst_lo_rc == rc_int) {  // gpr --> gpr copy
 1557           if (!is64 && this->ideal_reg() != Op_RegI) { // zero extended for narrow oop or klass
 1558             __ zero_extend(as_Register(Matcher::_regEncode[dst_lo]), as_Register(Matcher::_regEncode[src_lo]), 32);
 1559           } else {
 1560             __ mv(as_Register(Matcher::_regEncode[dst_lo]), as_Register(Matcher::_regEncode[src_lo]));
 1561           }
 1562         } else if (dst_lo_rc == rc_float) { // gpr --> fpr copy
 1563           if (is64) {
 1564             __ fmv_d_x(as_FloatRegister(Matcher::_regEncode[dst_lo]),
 1565                        as_Register(Matcher::_regEncode[src_lo]));
 1566           } else {
 1567             __ fmv_w_x(as_FloatRegister(Matcher::_regEncode[dst_lo]),
 1568                        as_Register(Matcher::_regEncode[src_lo]));
 1569           }
 1570         } else {                    // gpr --> stack spill
 1571           assert(dst_lo_rc == rc_stack, "spill to bad register class");
 1572           __ spill(as_Register(Matcher::_regEncode[src_lo]), is64, dst_offset);
 1573         }
 1574         break;
 1575       case rc_float:
 1576         if (dst_lo_rc == rc_int) {  // fpr --> gpr copy
 1577           if (is64) {
 1578             __ fmv_x_d(as_Register(Matcher::_regEncode[dst_lo]),
 1579                        as_FloatRegister(Matcher::_regEncode[src_lo]));
 1580           } else {
 1581             __ fmv_x_w(as_Register(Matcher::_regEncode[dst_lo]),
 1582                        as_FloatRegister(Matcher::_regEncode[src_lo]));
 1583           }
 1584         } else if (dst_lo_rc == rc_float) { // fpr --> fpr copy
 1585           if (is64) {
 1586             __ fmv_d(as_FloatRegister(Matcher::_regEncode[dst_lo]),
 1587                      as_FloatRegister(Matcher::_regEncode[src_lo]));
 1588           } else {
 1589             __ fmv_s(as_FloatRegister(Matcher::_regEncode[dst_lo]),
 1590                      as_FloatRegister(Matcher::_regEncode[src_lo]));
 1591           }
 1592         } else {                    // fpr --> stack spill
 1593           assert(dst_lo_rc == rc_stack, "spill to bad register class");
 1594           __ spill(as_FloatRegister(Matcher::_regEncode[src_lo]),
 1595                    is64, dst_offset);
 1596         }
 1597         break;
 1598       case rc_stack:
 1599         if (dst_lo_rc == rc_int) {  // stack --> gpr load
 1600           if (this->ideal_reg() == Op_RegI) {
 1601             __ unspill(as_Register(Matcher::_regEncode[dst_lo]), is64, src_offset);
 1602           } else { // // zero extended for narrow oop or klass
 1603             __ unspillu(as_Register(Matcher::_regEncode[dst_lo]), is64, src_offset);
 1604           }
 1605         } else if (dst_lo_rc == rc_float) { // stack --> fpr load
 1606           __ unspill(as_FloatRegister(Matcher::_regEncode[dst_lo]),
 1607                      is64, src_offset);
 1608         } else {                    // stack --> stack copy
 1609           assert(dst_lo_rc == rc_stack, "spill to bad register class");
 1610           if (this->ideal_reg() == Op_RegI) {
 1611             __ unspill(t0, is64, src_offset);
 1612           } else { // zero extended for narrow oop or klass
 1613             __ unspillu(t0, is64, src_offset);
 1614           }
 1615           __ spill(t0, is64, dst_offset);
 1616         }
 1617         break;
 1618       default:
 1619         ShouldNotReachHere();
 1620     }
 1621   }
 1622 
 1623   if (st != NULL) {
 1624     st->print("spill ");
 1625     if (src_lo_rc == rc_stack) {
 1626       st->print("[sp, #%d] -> ", src_offset);
 1627     } else {
 1628       st->print("%s -> ", Matcher::regName[src_lo]);
 1629     }
 1630     if (dst_lo_rc == rc_stack) {
 1631       st->print("[sp, #%d]", dst_offset);
 1632     } else {
 1633       st->print("%s", Matcher::regName[dst_lo]);
 1634     }
 1635     if (bottom_type()->isa_vect() != NULL) {
 1636       int vsize = 0;
 1637       if (ideal_reg() == Op_VecA) {
 1638         vsize = Matcher::scalable_vector_reg_size(T_BYTE) * 8;
 1639       } else {
 1640         ShouldNotReachHere();
 1641       }
 1642       st->print("\t# vector spill size = %d", vsize);
 1643     } else {
 1644       st->print("\t# spill size = %d", is64 ? 64 : 32);
 1645     }
 1646   }
 1647 
 1648   return 0;
 1649 }
 1650 
 1651 #ifndef PRODUCT
 1652 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
 1653   if (ra_ == NULL) {
 1654     st->print("N%d = SpillCopy(N%d)", _idx, in(1)->_idx);
 1655   } else {
 1656     implementation(NULL, ra_, false, st);
 1657   }
 1658 }
 1659 #endif
 1660 
 1661 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
 1662   implementation(&cbuf, ra_, false, NULL);
 1663 }
 1664 
 1665 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
 1666   return MachNode::size(ra_);
 1667 }
 1668 
 1669 //=============================================================================
 1670 
 1671 #ifndef PRODUCT
 1672 void BoxLockNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
 1673   assert_cond(ra_ != NULL && st != NULL);
 1674   int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
 1675   int reg = ra_->get_reg_first(this);
 1676   st->print("add %s, sp, #%d\t# box lock",
 1677             Matcher::regName[reg], offset);
 1678 }
 1679 #endif
 1680 
 1681 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
 1682   C2_MacroAssembler _masm(&cbuf);
 1683 
 1684   assert_cond(ra_ != NULL);
 1685   int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
 1686   int reg    = ra_->get_encode(this);
 1687 
 1688   if (is_imm_in_range(offset, 12, 0)) {
 1689     __ addi(as_Register(reg), sp, offset);
 1690   } else if (is_imm_in_range(offset, 32, 0)) {
 1691     __ li32(t0, offset);
 1692     __ add(as_Register(reg), sp, t0);
 1693   } else {
 1694     ShouldNotReachHere();
 1695   }
 1696 }
 1697 
 1698 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
 1699   // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_).
 1700   int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
 1701 
 1702   if (is_imm_in_range(offset, 12, 0)) {
 1703     return NativeInstruction::instruction_size;
 1704   } else {
 1705     return 3 * NativeInstruction::instruction_size; // lui + addiw + add;
 1706   }
 1707 }
 1708 
 1709 //=============================================================================
 1710 
 1711 #ifndef PRODUCT
 1712 void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const
 1713 {
 1714   assert_cond(st != NULL);
 1715   st->print_cr("# MachUEPNode");
 1716   if (UseCompressedClassPointers) {
 1717     st->print_cr("\tlwu t0, [j_rarg0, oopDesc::klass_offset_in_bytes()]\t# compressed klass");
 1718     if (CompressedKlassPointers::shift() != 0) {
 1719       st->print_cr("\tdecode_klass_not_null t0, t0");
 1720     }
 1721   } else {
 1722     st->print_cr("\tld t0, [j_rarg0, oopDesc::klass_offset_in_bytes()]\t# compressed klass");
 1723   }
 1724   st->print_cr("\tbeq t0, t1, ic_hit");
 1725   st->print_cr("\tj, SharedRuntime::_ic_miss_stub\t # Inline cache check");
 1726   st->print_cr("\tic_hit:");
 1727 }
 1728 #endif
 1729 
 1730 void MachUEPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
 1731 {
 1732   // This is the unverified entry point.
 1733   C2_MacroAssembler _masm(&cbuf);
 1734 
 1735   Label skip;
 1736   __ cmp_klass(j_rarg0, t1, t0, skip);
 1737   __ far_jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
 1738   __ bind(skip);
 1739 
 1740   // These NOPs are critical so that verified entry point is properly
 1741   // 4 bytes aligned for patching by NativeJump::patch_verified_entry()
 1742   __ align(NativeInstruction::instruction_size);
 1743 }
 1744 
 1745 uint MachUEPNode::size(PhaseRegAlloc* ra_) const
 1746 {
 1747   assert_cond(ra_ != NULL);
 1748   return MachNode::size(ra_);
 1749 }
 1750 
 1751 // REQUIRED EMIT CODE
 1752 
 1753 //=============================================================================
 1754 
 1755 // Emit exception handler code.
 1756 int HandlerImpl::emit_exception_handler(CodeBuffer& cbuf)
 1757 {
 1758   // la_patchable t0, #exception_blob_entry_point
 1759   // jr (offset)t0
 1760   // or
 1761   // j #exception_blob_entry_point
 1762   // Note that the code buffer's insts_mark is always relative to insts.
 1763   // That's why we must use the macroassembler to generate a handler.
 1764   C2_MacroAssembler _masm(&cbuf);
 1765   address base = __ start_a_stub(size_exception_handler());
 1766   if (base == NULL) {
 1767     ciEnv::current()->record_failure("CodeCache is full");
 1768     return 0;  // CodeBuffer::expand failed
 1769   }
 1770   int offset = __ offset();
 1771   __ far_jump(RuntimeAddress(OptoRuntime::exception_blob()->entry_point()));
 1772   assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
 1773   __ end_a_stub();
 1774   return offset;
 1775 }
 1776 
 1777 // Emit deopt handler code.
 1778 int HandlerImpl::emit_deopt_handler(CodeBuffer& cbuf)
 1779 {
 1780   // Note that the code buffer's insts_mark is always relative to insts.
 1781   // That's why we must use the macroassembler to generate a handler.
 1782   C2_MacroAssembler _masm(&cbuf);
 1783   address base = __ start_a_stub(size_deopt_handler());
 1784   if (base == NULL) {
 1785     ciEnv::current()->record_failure("CodeCache is full");
 1786     return 0;  // CodeBuffer::expand failed
 1787   }
 1788   int offset = __ offset();
 1789 
 1790   __ auipc(ra, 0);
 1791   __ far_jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
 1792 
 1793   assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
 1794   __ end_a_stub();
 1795   return offset;
 1796 
 1797 }
 1798 // REQUIRED MATCHER CODE
 1799 
 1800 //=============================================================================
 1801 
 1802 const bool Matcher::match_rule_supported(int opcode) {
 1803   if (!has_match_rule(opcode)) {
 1804     return false;
 1805   }
 1806 
 1807   switch (opcode) {
 1808     case Op_CacheWB:           // fall through
 1809     case Op_CacheWBPreSync:    // fall through
 1810     case Op_CacheWBPostSync:
 1811       if (!VM_Version::supports_data_cache_line_flush()) {
 1812         return false;
 1813       }
 1814       break;
 1815 
 1816     case Op_StrCompressedCopy: // fall through
 1817     case Op_StrInflatedCopy:   // fall through
 1818     case Op_CountPositives:
 1819       return UseRVV;
 1820 
 1821     case Op_EncodeISOArray:
 1822       return UseRVV && SpecialEncodeISOArray;
 1823 
 1824     case Op_PopCountI:
 1825     case Op_PopCountL:
 1826       return UsePopCountInstruction;
 1827 
 1828     case Op_RotateRight:
 1829     case Op_RotateLeft:
 1830     case Op_CountLeadingZerosI:
 1831     case Op_CountLeadingZerosL:
 1832     case Op_CountTrailingZerosI:
 1833     case Op_CountTrailingZerosL:
 1834       return UseZbb;
 1835   }
 1836 
 1837   return true; // Per default match rules are supported.
 1838 }
 1839 
 1840 const bool Matcher::match_rule_supported_superword(int opcode, int vlen, BasicType bt) {
 1841   return match_rule_supported_vector(opcode, vlen, bt);
 1842 }
 1843 
 1844 // Identify extra cases that we might want to provide match rules for vector nodes and
 1845 // other intrinsics guarded with vector length (vlen) and element type (bt).
 1846 const bool Matcher::match_rule_supported_vector(int opcode, int vlen, BasicType bt) {
 1847   if (!match_rule_supported(opcode) || !vector_size_supported(bt, vlen)) {
 1848     return false;
 1849   }
 1850 
 1851   return op_vec_supported(opcode);
 1852 }
 1853 
 1854 const bool Matcher::match_rule_supported_vector_masked(int opcode, int vlen, BasicType bt) {
 1855   return false;
 1856 }
 1857 
 1858 const bool Matcher::vector_needs_partial_operations(Node* node, const TypeVect* vt) {
 1859   return false;
 1860 }
 1861 
 1862 const RegMask* Matcher::predicate_reg_mask(void) {
 1863   return NULL;
 1864 }
 1865 
 1866 const TypeVectMask* Matcher::predicate_reg_type(const Type* elemTy, int length) {
 1867   return NULL;
 1868 }
 1869 
 1870 // Vector calling convention not yet implemented.
 1871 const bool Matcher::supports_vector_calling_convention(void) {
 1872   return false;
 1873 }
 1874 
 1875 OptoRegPair Matcher::vector_return_value(uint ideal_reg) {
 1876   Unimplemented();
 1877   return OptoRegPair(0, 0);
 1878 }
 1879 
 1880 // Is this branch offset short enough that a short branch can be used?
 1881 //
 1882 // NOTE: If the platform does not provide any short branch variants, then
 1883 //       this method should return false for offset 0.
 1884 // |---label(L1)-----|
 1885 // |-----------------|
 1886 // |-----------------|----------eq: float-------------------
 1887 // |-----------------| // far_cmpD_branch   |   cmpD_branch
 1888 // |------- ---------|    feq;              |      feq;
 1889 // |-far_cmpD_branch-|    beqz done;        |      bnez L;
 1890 // |-----------------|    j L;              |
 1891 // |-----------------|    bind(done);       |
 1892 // |-----------------|--------------------------------------
 1893 // |-----------------| // so shortBrSize = br_size - 4;
 1894 // |-----------------| // so offs = offset - shortBrSize + 4;
 1895 // |---label(L2)-----|
 1896 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
 1897   // The passed offset is relative to address of the branch.
 1898   int shortBrSize = br_size - 4;
 1899   int offs = offset - shortBrSize + 4;
 1900   return (-4096 <= offs && offs < 4096);
 1901 }
 1902 
 1903 // Vector width in bytes.
 1904 const int Matcher::vector_width_in_bytes(BasicType bt) {
 1905   if (UseRVV) {
 1906     // The MaxVectorSize should have been set by detecting RVV max vector register size when check UseRVV.
 1907     // MaxVectorSize == VM_Version::_initial_vector_length
 1908     return MaxVectorSize;
 1909   }
 1910   return 0;
 1911 }
 1912 
 1913 // Limits on vector size (number of elements) loaded into vector.
 1914 const int Matcher::max_vector_size(const BasicType bt) {
 1915   return vector_width_in_bytes(bt) / type2aelembytes(bt);
 1916 }
 1917 const int Matcher::min_vector_size(const BasicType bt) {
 1918   return max_vector_size(bt);
 1919 }
 1920 
 1921 // Vector ideal reg.
 1922 const uint Matcher::vector_ideal_reg(int len) {
 1923   assert(MaxVectorSize >= len, "");
 1924   if (UseRVV) {
 1925     return Op_VecA;
 1926   }
 1927 
 1928   ShouldNotReachHere();
 1929   return 0;
 1930 }
 1931 
 1932 const int Matcher::scalable_vector_reg_size(const BasicType bt) {
 1933   return Matcher::max_vector_size(bt);
 1934 }
 1935 
 1936 MachOper* Matcher::pd_specialize_generic_vector_operand(MachOper* original_opnd, uint ideal_reg, bool is_temp) {
 1937   ShouldNotReachHere(); // generic vector operands not supported
 1938   return NULL;
 1939 }
 1940 
 1941 bool Matcher::is_reg2reg_move(MachNode* m) {
 1942   ShouldNotReachHere(); // generic vector operands not supported
 1943   return false;
 1944 }
 1945 
 1946 bool Matcher::is_generic_vector(MachOper* opnd) {
 1947   ShouldNotReachHere(); // generic vector operands not supported
 1948   return false;
 1949 }
 1950 
 1951 // Return whether or not this register is ever used as an argument.
 1952 // This function is used on startup to build the trampoline stubs in
 1953 // generateOptoStub.  Registers not mentioned will be killed by the VM
 1954 // call in the trampoline, and arguments in those registers not be
 1955 // available to the callee.
 1956 bool Matcher::can_be_java_arg(int reg)
 1957 {
 1958   return
 1959     reg ==  R10_num || reg == R10_H_num ||
 1960     reg ==  R11_num || reg == R11_H_num ||
 1961     reg ==  R12_num || reg == R12_H_num ||
 1962     reg ==  R13_num || reg == R13_H_num ||
 1963     reg ==  R14_num || reg == R14_H_num ||
 1964     reg ==  R15_num || reg == R15_H_num ||
 1965     reg ==  R16_num || reg == R16_H_num ||
 1966     reg ==  R17_num || reg == R17_H_num ||
 1967     reg ==  F10_num || reg == F10_H_num ||
 1968     reg ==  F11_num || reg == F11_H_num ||
 1969     reg ==  F12_num || reg == F12_H_num ||
 1970     reg ==  F13_num || reg == F13_H_num ||
 1971     reg ==  F14_num || reg == F14_H_num ||
 1972     reg ==  F15_num || reg == F15_H_num ||
 1973     reg ==  F16_num || reg == F16_H_num ||
 1974     reg ==  F17_num || reg == F17_H_num;
 1975 }
 1976 
 1977 bool Matcher::is_spillable_arg(int reg)
 1978 {
 1979   return can_be_java_arg(reg);
 1980 }
 1981 
 1982 uint Matcher::int_pressure_limit()
 1983 {
 1984   // A derived pointer is live at CallNode and then is flagged by RA
 1985   // as a spilled LRG. Spilling heuristics(Spill-USE) explicitly skip
 1986   // derived pointers and lastly fail to spill after reaching maximum
 1987   // number of iterations. Lowering the default pressure threshold to
 1988   // (_NO_SPECIAL_REG32_mask.Size() minus 1) forces CallNode to become
 1989   // a high register pressure area of the code so that split_DEF can
 1990   // generate DefinitionSpillCopy for the derived pointer.
 1991   uint default_int_pressure_threshold = _NO_SPECIAL_REG32_mask.Size() - 1;
 1992   if (!PreserveFramePointer) {
 1993     // When PreserveFramePointer is off, frame pointer is allocatable,
 1994     // but different from other SOC registers, it is excluded from
 1995     // fatproj's mask because its save type is No-Save. Decrease 1 to
 1996     // ensure high pressure at fatproj when PreserveFramePointer is off.
 1997     // See check_pressure_at_fatproj().
 1998     default_int_pressure_threshold--;
 1999   }
 2000   return (INTPRESSURE == -1) ? default_int_pressure_threshold : INTPRESSURE;
 2001 }
 2002 
 2003 uint Matcher::float_pressure_limit()
 2004 {
 2005   // _FLOAT_REG_mask is generated by adlc from the float_reg register class.
 2006   return (FLOATPRESSURE == -1) ? _FLOAT_REG_mask.Size() : FLOATPRESSURE;
 2007 }
 2008 
 2009 bool Matcher::use_asm_for_ldiv_by_con(jlong divisor) {
 2010   return false;
 2011 }
 2012 
 2013 RegMask Matcher::divI_proj_mask() {
 2014   ShouldNotReachHere();
 2015   return RegMask();
 2016 }
 2017 
 2018 // Register for MODI projection of divmodI.
 2019 RegMask Matcher::modI_proj_mask() {
 2020   ShouldNotReachHere();
 2021   return RegMask();
 2022 }
 2023 
 2024 // Register for DIVL projection of divmodL.
 2025 RegMask Matcher::divL_proj_mask() {
 2026   ShouldNotReachHere();
 2027   return RegMask();
 2028 }
 2029 
 2030 // Register for MODL projection of divmodL.
 2031 RegMask Matcher::modL_proj_mask() {
 2032   ShouldNotReachHere();
 2033   return RegMask();
 2034 }
 2035 
 2036 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
 2037   return FP_REG_mask();
 2038 }
 2039 
 2040 bool size_fits_all_mem_uses(AddPNode* addp, int shift) {
 2041   assert_cond(addp != NULL);
 2042   for (DUIterator_Fast imax, i = addp->fast_outs(imax); i < imax; i++) {
 2043     Node* u = addp->fast_out(i);
 2044     if (u != NULL && u->is_Mem()) {
 2045       int opsize = u->as_Mem()->memory_size();
 2046       assert(opsize > 0, "unexpected memory operand size");
 2047       if (u->as_Mem()->memory_size() != (1 << shift)) {
 2048         return false;
 2049       }
 2050     }
 2051   }
 2052   return true;
 2053 }
 2054 
 2055 // Should the Matcher clone input 'm' of node 'n'?
 2056 bool Matcher::pd_clone_node(Node* n, Node* m, Matcher::MStack& mstack) {
 2057   assert_cond(m != NULL);
 2058   if (is_vshift_con_pattern(n, m)) { // ShiftV src (ShiftCntV con)
 2059     mstack.push(m, Visit);           // m = ShiftCntV
 2060     return true;
 2061   }
 2062   return false;
 2063 }
 2064 
 2065 // Should the Matcher clone shifts on addressing modes, expecting them
 2066 // to be subsumed into complex addressing expressions or compute them
 2067 // into registers?
 2068 bool Matcher::pd_clone_address_expressions(AddPNode* m, Matcher::MStack& mstack, VectorSet& address_visited) {
 2069   return clone_base_plus_offset_address(m, mstack, address_visited);
 2070 }
 2071 
 2072 %}
 2073 
 2074 
 2075 
 2076 //----------ENCODING BLOCK-----------------------------------------------------
 2077 // This block specifies the encoding classes used by the compiler to
 2078 // output byte streams.  Encoding classes are parameterized macros
 2079 // used by Machine Instruction Nodes in order to generate the bit
 2080 // encoding of the instruction.  Operands specify their base encoding
 2081 // interface with the interface keyword.  There are currently
 2082 // supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, &
 2083 // COND_INTER.  REG_INTER causes an operand to generate a function
 2084 // which returns its register number when queried.  CONST_INTER causes
 2085 // an operand to generate a function which returns the value of the
 2086 // constant when queried.  MEMORY_INTER causes an operand to generate
 2087 // four functions which return the Base Register, the Index Register,
 2088 // the Scale Value, and the Offset Value of the operand when queried.
 2089 // COND_INTER causes an operand to generate six functions which return
 2090 // the encoding code (ie - encoding bits for the instruction)
 2091 // associated with each basic boolean condition for a conditional
 2092 // instruction.
 2093 //
 2094 // Instructions specify two basic values for encoding.  Again, a
 2095 // function is available to check if the constant displacement is an
 2096 // oop. They use the ins_encode keyword to specify their encoding
 2097 // classes (which must be a sequence of enc_class names, and their
 2098 // parameters, specified in the encoding block), and they use the
 2099 // opcode keyword to specify, in order, their primary, secondary, and
 2100 // tertiary opcode.  Only the opcode sections which a particular
 2101 // instruction needs for encoding need to be specified.
 2102 encode %{
 2103   // BEGIN Non-volatile memory access
 2104 
 2105   enc_class riscv_enc_li_imm(iRegIorL dst, immIorL src) %{
 2106     C2_MacroAssembler _masm(&cbuf);
 2107     Assembler::CompressibleRegion cr(&_masm);
 2108     int64_t con = (int64_t)$src$$constant;
 2109     Register dst_reg = as_Register($dst$$reg);
 2110     __ mv(dst_reg, con);
 2111   %}
 2112 
 2113   enc_class riscv_enc_mov_p(iRegP dst, immP src) %{
 2114     C2_MacroAssembler _masm(&cbuf);
 2115     Register dst_reg = as_Register($dst$$reg);
 2116     address con = (address)$src$$constant;
 2117     if (con == NULL || con == (address)1) {
 2118       ShouldNotReachHere();
 2119     } else {
 2120       relocInfo::relocType rtype = $src->constant_reloc();
 2121       if (rtype == relocInfo::oop_type) {
 2122         __ movoop(dst_reg, (jobject)con);
 2123       } else if (rtype == relocInfo::metadata_type) {
 2124         __ mov_metadata(dst_reg, (Metadata*)con);
 2125       } else {
 2126         assert(rtype == relocInfo::none, "unexpected reloc type");
 2127         __ mv(dst_reg, $src$$constant);
 2128       }
 2129     }
 2130   %}
 2131 
 2132   enc_class riscv_enc_mov_p1(iRegP dst) %{
 2133     C2_MacroAssembler _masm(&cbuf);
 2134     Assembler::CompressibleRegion cr(&_masm);
 2135     Register dst_reg = as_Register($dst$$reg);
 2136     __ mv(dst_reg, 1);
 2137   %}
 2138 
 2139   enc_class riscv_enc_mov_byte_map_base(iRegP dst) %{
 2140     C2_MacroAssembler _masm(&cbuf);
 2141     __ load_byte_map_base($dst$$Register);
 2142   %}
 2143 
 2144   enc_class riscv_enc_mov_n(iRegN dst, immN src) %{
 2145     C2_MacroAssembler _masm(&cbuf);
 2146     Register dst_reg = as_Register($dst$$reg);
 2147     address con = (address)$src$$constant;
 2148     if (con == NULL) {
 2149       ShouldNotReachHere();
 2150     } else {
 2151       relocInfo::relocType rtype = $src->constant_reloc();
 2152       assert(rtype == relocInfo::oop_type, "unexpected reloc type");
 2153       __ set_narrow_oop(dst_reg, (jobject)con);
 2154     }
 2155   %}
 2156 
 2157   enc_class riscv_enc_mov_zero(iRegNorP dst) %{
 2158     C2_MacroAssembler _masm(&cbuf);
 2159     Register dst_reg = as_Register($dst$$reg);
 2160     __ mv(dst_reg, zr);
 2161   %}
 2162 
 2163   enc_class riscv_enc_mov_nk(iRegN dst, immNKlass src) %{
 2164     C2_MacroAssembler _masm(&cbuf);
 2165     Register dst_reg = as_Register($dst$$reg);
 2166     address con = (address)$src$$constant;
 2167     if (con == NULL) {
 2168       ShouldNotReachHere();
 2169     } else {
 2170       relocInfo::relocType rtype = $src->constant_reloc();
 2171       assert(rtype == relocInfo::metadata_type, "unexpected reloc type");
 2172       __ set_narrow_klass(dst_reg, (Klass *)con);
 2173     }
 2174   %}
 2175 
 2176   enc_class riscv_enc_cmpxchgw(iRegINoSp res, memory mem, iRegI oldval, iRegI newval) %{
 2177     C2_MacroAssembler _masm(&cbuf);
 2178     __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
 2179                /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
 2180                /*result as bool*/ true);
 2181   %}
 2182 
 2183   enc_class riscv_enc_cmpxchgn(iRegINoSp res, memory mem, iRegI oldval, iRegI newval) %{
 2184     C2_MacroAssembler _masm(&cbuf);
 2185     __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
 2186                /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
 2187                /*result as bool*/ true);
 2188   %}
 2189 
 2190   enc_class riscv_enc_cmpxchg(iRegINoSp res, memory mem, iRegL oldval, iRegL newval) %{
 2191     C2_MacroAssembler _masm(&cbuf);
 2192     __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
 2193                /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
 2194                /*result as bool*/ true);
 2195   %}
 2196 
 2197   enc_class riscv_enc_cmpxchgw_acq(iRegINoSp res, memory mem, iRegI oldval, iRegI newval) %{
 2198     C2_MacroAssembler _masm(&cbuf);
 2199     __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
 2200                /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
 2201                /*result as bool*/ true);
 2202   %}
 2203 
 2204   enc_class riscv_enc_cmpxchgn_acq(iRegINoSp res, memory mem, iRegI oldval, iRegI newval) %{
 2205     C2_MacroAssembler _masm(&cbuf);
 2206     __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
 2207                /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
 2208                /*result as bool*/ true);
 2209   %}
 2210 
 2211   enc_class riscv_enc_cmpxchg_acq(iRegINoSp res, memory mem, iRegL oldval, iRegL newval) %{
 2212     C2_MacroAssembler _masm(&cbuf);
 2213     __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
 2214                /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
 2215                /*result as bool*/ true);
 2216   %}
 2217 
 2218   // compare and branch instruction encodings
 2219 
 2220   enc_class riscv_enc_j(label lbl) %{
 2221     C2_MacroAssembler _masm(&cbuf);
 2222     Label* L = $lbl$$label;
 2223     __ j(*L);
 2224   %}
 2225 
 2226   enc_class riscv_enc_far_cmpULtGe_imm0_branch(cmpOpULtGe cmp, iRegIorL op1, label lbl) %{
 2227     C2_MacroAssembler _masm(&cbuf);
 2228     Label* L = $lbl$$label;
 2229     switch ($cmp$$cmpcode) {
 2230       case(BoolTest::ge):
 2231         __ j(*L);
 2232         break;
 2233       case(BoolTest::lt):
 2234         break;
 2235       default:
 2236         Unimplemented();
 2237     }
 2238   %}
 2239 
 2240   // call instruction encodings
 2241 
 2242   enc_class riscv_enc_partial_subtype_check(iRegP sub, iRegP super, iRegP temp, iRegP result) %{
 2243     Register sub_reg = as_Register($sub$$reg);
 2244     Register super_reg = as_Register($super$$reg);
 2245     Register temp_reg = as_Register($temp$$reg);
 2246     Register result_reg = as_Register($result$$reg);
 2247     Register cr_reg = t1;
 2248 
 2249     Label miss;
 2250     Label done;
 2251     C2_MacroAssembler _masm(&cbuf);
 2252     __ check_klass_subtype_slow_path(sub_reg, super_reg, temp_reg, result_reg,
 2253                                      NULL, &miss);
 2254     if ($primary) {
 2255       __ mv(result_reg, zr);
 2256     } else {
 2257       __ mv(cr_reg, zr);
 2258       __ j(done);
 2259     }
 2260 
 2261     __ bind(miss);
 2262     if (!$primary) {
 2263       __ mv(cr_reg, 1);
 2264     }
 2265 
 2266     __ bind(done);
 2267   %}
 2268 
 2269   enc_class riscv_enc_java_static_call(method meth) %{
 2270     C2_MacroAssembler _masm(&cbuf);
 2271 
 2272     address addr = (address)$meth$$method;
 2273     address call = NULL;
 2274     assert_cond(addr != NULL);
 2275     if (!_method) {
 2276       // A call to a runtime wrapper, e.g. new, new_typeArray_Java, uncommon_trap.
 2277       call = __ trampoline_call(Address(addr, relocInfo::runtime_call_type));
 2278       if (call == NULL) {
 2279         ciEnv::current()->record_failure("CodeCache is full");
 2280         return;
 2281       }
 2282     } else {
 2283       int method_index = resolved_method_index(cbuf);
 2284       RelocationHolder rspec = _optimized_virtual ? opt_virtual_call_Relocation::spec(method_index)
 2285                                                   : static_call_Relocation::spec(method_index);
 2286       call = __ trampoline_call(Address(addr, rspec));
 2287       if (call == NULL) {
 2288         ciEnv::current()->record_failure("CodeCache is full");
 2289         return;
 2290       }
 2291 
 2292       if (CodeBuffer::supports_shared_stubs() && _method->can_be_statically_bound()) {
 2293         // Calls of the same statically bound method can share
 2294         // a stub to the interpreter.
 2295         cbuf.shared_stub_to_interp_for(_method, call - cbuf.insts_begin());
 2296       } else {
 2297         // Emit stub for static call
 2298         address stub = CompiledStaticCall::emit_to_interp_stub(cbuf, call);
 2299         if (stub == NULL) {
 2300           ciEnv::current()->record_failure("CodeCache is full");
 2301           return;
 2302         }
 2303       }
 2304     }
 2305   %}
 2306 
 2307   enc_class riscv_enc_java_dynamic_call(method meth) %{
 2308     C2_MacroAssembler _masm(&cbuf);
 2309     int method_index = resolved_method_index(cbuf);
 2310     address call = __ ic_call((address)$meth$$method, method_index);
 2311     if (call == NULL) {
 2312       ciEnv::current()->record_failure("CodeCache is full");
 2313       return;
 2314     }
 2315   %}
 2316 
 2317   enc_class riscv_enc_call_epilog() %{
 2318     C2_MacroAssembler _masm(&cbuf);
 2319     if (VerifyStackAtCalls) {
 2320       // Check that stack depth is unchanged: find majik cookie on stack
 2321       __ call_Unimplemented();
 2322     }
 2323   %}
 2324 
 2325   enc_class riscv_enc_java_to_runtime(method meth) %{
 2326     C2_MacroAssembler _masm(&cbuf);
 2327 
 2328     // some calls to generated routines (arraycopy code) are scheduled
 2329     // by C2 as runtime calls. if so we can call them using a jr (they
 2330     // will be in a reachable segment) otherwise we have to use a jalr
 2331     // which loads the absolute address into a register.
 2332     address entry = (address)$meth$$method;
 2333     CodeBlob *cb = CodeCache::find_blob(entry);
 2334     if (cb != NULL) {
 2335       address call = __ trampoline_call(Address(entry, relocInfo::runtime_call_type));
 2336       if (call == NULL) {
 2337         ciEnv::current()->record_failure("CodeCache is full");
 2338         return;
 2339       }
 2340     } else {
 2341       Label retaddr;
 2342       __ la(t1, retaddr);
 2343       __ la(t0, RuntimeAddress(entry));
 2344       // Leave a breadcrumb for JavaFrameAnchor::capture_last_Java_pc()
 2345       __ addi(sp, sp, -2 * wordSize);
 2346       __ sd(t1, Address(sp, wordSize));
 2347       __ jalr(t0);
 2348       __ bind(retaddr);
 2349       __ addi(sp, sp, 2 * wordSize);
 2350     }
 2351   %}
 2352 
 2353   // using the cr register as the bool result: 0 for success; others failed.
 2354   enc_class riscv_enc_fast_lock(iRegP object, iRegP box, iRegPNoSp tmp1, iRegPNoSp tmp2) %{
 2355     C2_MacroAssembler _masm(&cbuf);
 2356     Register flag = t1;
 2357     Register oop = as_Register($object$$reg);
 2358     Register box = as_Register($box$$reg);
 2359     Register disp_hdr = as_Register($tmp1$$reg);
 2360     Register tmp = as_Register($tmp2$$reg);
 2361     Label cont;
 2362     Label object_has_monitor;
 2363 
 2364     assert_different_registers(oop, box, tmp, disp_hdr, t0);
 2365 
 2366     // Load markWord from object into displaced_header.
 2367     __ ld(disp_hdr, Address(oop, oopDesc::mark_offset_in_bytes()));
 2368 
 2369     if (DiagnoseSyncOnValueBasedClasses != 0) {
 2370       __ load_klass(flag, oop);
 2371       __ lwu(flag, Address(flag, Klass::access_flags_offset()));
 2372       __ andi(flag, flag, JVM_ACC_IS_VALUE_BASED_CLASS, tmp /* tmp */);
 2373       __ bnez(flag, cont, true /* is_far */);
 2374     }
 2375 
 2376     // Check for existing monitor
 2377     __ andi(t0, disp_hdr, markWord::monitor_value);
 2378     __ bnez(t0, object_has_monitor);
 2379 
 2380     if (!UseHeavyMonitors) {
 2381       Label slow;
 2382       __ fast_lock(oop, disp_hdr, box, tmp, t0, slow);
 2383 
 2384       // Indicate success at cont.
 2385       __ mv(flag, zr);
 2386       __ j(cont);
 2387       __ bind(slow);
 2388     }
 2389 
 2390     __ mv(flag, 1); // Set non-zero flag to indicate 'failure' -> take slow-path
 2391     __ j(cont);
 2392 
 2393     // Handle existing monitor.
 2394     __ bind(object_has_monitor);
 2395     // The object's monitor m is unlocked iff m->owner == NULL,
 2396     // otherwise m->owner may contain a thread or a stack address.
 2397     //
 2398     // Try to CAS m->owner from NULL to current thread.
 2399     __ add(tmp, disp_hdr, (ObjectMonitor::owner_offset_in_bytes() - markWord::monitor_value));
 2400     __ cmpxchg(/*memory address*/tmp, /*expected value*/zr, /*new value*/xthread, Assembler::int64, Assembler::aq,
 2401              Assembler::rl, /*result*/flag); // cas succeeds if flag == zr(expected)
 2402 
 2403     __ beqz(flag, cont); // CAS success means locking succeeded
 2404 
 2405     __ bne(flag, xthread, cont); // Check for recursive locking
 2406 
 2407     // Recursive lock case
 2408     __ mv(flag, zr);
 2409     __ ld(tmp, Address(disp_hdr, ObjectMonitor::recursions_offset_in_bytes() - markWord::monitor_value));
 2410     __ add(tmp, tmp, 1u);
 2411     __ sd(tmp, Address(disp_hdr, ObjectMonitor::recursions_offset_in_bytes() - markWord::monitor_value));
 2412 
 2413     __ bind(cont);
 2414   %}
 2415 
 2416   // using cr flag to indicate the fast_unlock result: 0 for success; others failed.
 2417   enc_class riscv_enc_fast_unlock(iRegP object, iRegP box, iRegPNoSp tmp1, iRegPNoSp tmp2) %{
 2418     C2_MacroAssembler _masm(&cbuf);
 2419     Register flag = t1;
 2420     Register oop = as_Register($object$$reg);
 2421     Register box = as_Register($box$$reg);
 2422     Register disp_hdr = as_Register($tmp1$$reg);
 2423     Register tmp = as_Register($tmp2$$reg);
 2424     Label cont;
 2425     Label object_has_monitor;
 2426 
 2427     assert_different_registers(oop, box, tmp, disp_hdr, flag);
 2428 
 2429     // Handle existing monitor.
 2430     __ ld(tmp, Address(oop, oopDesc::mark_offset_in_bytes()));
 2431 
 2432     assert(oopDesc::mark_offset_in_bytes() == 0, "offset of _mark is not 0");
 2433 
 2434     if (!UseHeavyMonitors) {
 2435       Label slow;
 2436       __ andi(t0, tmp, markWord::monitor_value);
 2437       __ bnez(t0, object_has_monitor);
 2438 
 2439       __ fast_unlock(oop, tmp, box, disp_hdr, slow);
 2440 
 2441       // Indicate success at cont.
 2442       __ mv(flag, zr);
 2443       __ j(cont);
 2444       __ bind(slow);
 2445     }
 2446 
 2447     __ mv(flag, 1); // Set non-zero flag to indicate 'failure' -> take slow path
 2448     __ j(cont);
 2449 
 2450     // Handle existing monitor.
 2451     __ bind(object_has_monitor);
 2452     STATIC_ASSERT(markWord::monitor_value <= INT_MAX);
 2453     __ add(tmp, tmp, -(int)markWord::monitor_value); // monitor
 2454 
 2455     // If the owner is anonymous, we need to fix it -- in the slow-path.
 2456     {
 2457       Label L;
 2458       __ ld(disp_hdr, Address(tmp, ObjectMonitor::owner_offset_in_bytes()));
 2459       __ mv(t0, (unsigned char)(intptr_t)ANONYMOUS_OWNER);
 2460       __ bne(disp_hdr, t0, L);
 2461       __ mv(flag, 1); // Indicate failure at cont -- dive into slow-path.
 2462       __ j(cont);
 2463       __ bind(L);
 2464     }
 2465 
 2466     __ ld(disp_hdr, Address(tmp, ObjectMonitor::recursions_offset_in_bytes()));
 2467 
 2468     Label notRecursive;
 2469     __ beqz(disp_hdr, notRecursive); // Will be 0 if not recursive.
 2470 
 2471     // Recursive lock
 2472     __ addi(disp_hdr, disp_hdr, -1);
 2473     __ sd(disp_hdr, Address(tmp, ObjectMonitor::recursions_offset_in_bytes()));
 2474     __ mv(flag, zr);
 2475     __ j(cont);
 2476 
 2477     __ bind(notRecursive);
 2478     __ ld(flag, Address(tmp, ObjectMonitor::EntryList_offset_in_bytes()));
 2479     __ ld(disp_hdr, Address(tmp, ObjectMonitor::cxq_offset_in_bytes()));
 2480     __ orr(flag, flag, disp_hdr); // Will be 0 if both are 0.
 2481     __ bnez(flag, cont);
 2482     // need a release store here
 2483     __ la(tmp, Address(tmp, ObjectMonitor::owner_offset_in_bytes()));
 2484     __ membar(MacroAssembler::LoadStore | MacroAssembler::StoreStore);
 2485     __ sd(zr, Address(tmp)); // set unowned
 2486 
 2487     __ bind(cont);
 2488   %}
 2489 
 2490   // arithmetic encodings
 2491 
 2492   enc_class riscv_enc_divw(iRegI dst, iRegI src1, iRegI src2) %{
 2493     C2_MacroAssembler _masm(&cbuf);
 2494     Register dst_reg = as_Register($dst$$reg);
 2495     Register src1_reg = as_Register($src1$$reg);
 2496     Register src2_reg = as_Register($src2$$reg);
 2497     __ corrected_idivl(dst_reg, src1_reg, src2_reg, false);
 2498   %}
 2499 
 2500   enc_class riscv_enc_div(iRegI dst, iRegI src1, iRegI src2) %{
 2501     C2_MacroAssembler _masm(&cbuf);
 2502     Register dst_reg = as_Register($dst$$reg);
 2503     Register src1_reg = as_Register($src1$$reg);
 2504     Register src2_reg = as_Register($src2$$reg);
 2505     __ corrected_idivq(dst_reg, src1_reg, src2_reg, false);
 2506   %}
 2507 
 2508   enc_class riscv_enc_modw(iRegI dst, iRegI src1, iRegI src2) %{
 2509     C2_MacroAssembler _masm(&cbuf);
 2510     Register dst_reg = as_Register($dst$$reg);
 2511     Register src1_reg = as_Register($src1$$reg);
 2512     Register src2_reg = as_Register($src2$$reg);
 2513     __ corrected_idivl(dst_reg, src1_reg, src2_reg, true);
 2514   %}
 2515 
 2516   enc_class riscv_enc_mod(iRegI dst, iRegI src1, iRegI src2) %{
 2517     C2_MacroAssembler _masm(&cbuf);
 2518     Register dst_reg = as_Register($dst$$reg);
 2519     Register src1_reg = as_Register($src1$$reg);
 2520     Register src2_reg = as_Register($src2$$reg);
 2521     __ corrected_idivq(dst_reg, src1_reg, src2_reg, true);
 2522   %}
 2523 
 2524   enc_class riscv_enc_tail_call(iRegP jump_target) %{
 2525     C2_MacroAssembler _masm(&cbuf);
 2526     Assembler::CompressibleRegion cr(&_masm);
 2527     Register target_reg = as_Register($jump_target$$reg);
 2528     __ jr(target_reg);
 2529   %}
 2530 
 2531   enc_class riscv_enc_tail_jmp(iRegP jump_target) %{
 2532     C2_MacroAssembler _masm(&cbuf);
 2533     Assembler::CompressibleRegion cr(&_masm);
 2534     Register target_reg = as_Register($jump_target$$reg);
 2535     // exception oop should be in x10
 2536     // ret addr has been popped into ra
 2537     // callee expects it in x13
 2538     __ mv(x13, ra);
 2539     __ jr(target_reg);
 2540   %}
 2541 
 2542   enc_class riscv_enc_rethrow() %{
 2543     C2_MacroAssembler _masm(&cbuf);
 2544     __ far_jump(RuntimeAddress(OptoRuntime::rethrow_stub()));
 2545   %}
 2546 
 2547   enc_class riscv_enc_ret() %{
 2548     C2_MacroAssembler _masm(&cbuf);
 2549     Assembler::CompressibleRegion cr(&_masm);
 2550     __ ret();
 2551   %}
 2552 
 2553 %}
 2554 
 2555 //----------FRAME--------------------------------------------------------------
 2556 // Definition of frame structure and management information.
 2557 //
 2558 //  S T A C K   L A Y O U T    Allocators stack-slot number
 2559 //                             |   (to get allocators register number
 2560 //  G  Owned by    |        |  v    add OptoReg::stack0())
 2561 //  r   CALLER     |        |
 2562 //  o     |        +--------+      pad to even-align allocators stack-slot
 2563 //  w     V        |  pad0  |        numbers; owned by CALLER
 2564 //  t   -----------+--------+----> Matcher::_in_arg_limit, unaligned
 2565 //  h     ^        |   in   |  5
 2566 //        |        |  args  |  4   Holes in incoming args owned by SELF
 2567 //  |     |        |        |  3
 2568 //  |     |        +--------+
 2569 //  V     |        | old out|      Empty on Intel, window on Sparc
 2570 //        |    old |preserve|      Must be even aligned.
 2571 //        |     SP-+--------+----> Matcher::_old_SP, even aligned
 2572 //        |        |   in   |  3   area for Intel ret address
 2573 //     Owned by    |preserve|      Empty on Sparc.
 2574 //       SELF      +--------+
 2575 //        |        |  pad2  |  2   pad to align old SP
 2576 //        |        +--------+  1
 2577 //        |        | locks  |  0
 2578 //        |        +--------+----> OptoReg::stack0(), even aligned
 2579 //        |        |  pad1  | 11   pad to align new SP
 2580 //        |        +--------+
 2581 //        |        |        | 10
 2582 //        |        | spills |  9   spills
 2583 //        V        |        |  8   (pad0 slot for callee)
 2584 //      -----------+--------+----> Matcher::_out_arg_limit, unaligned
 2585 //        ^        |  out   |  7
 2586 //        |        |  args  |  6   Holes in outgoing args owned by CALLEE
 2587 //     Owned by    +--------+
 2588 //      CALLEE     | new out|  6   Empty on Intel, window on Sparc
 2589 //        |    new |preserve|      Must be even-aligned.
 2590 //        |     SP-+--------+----> Matcher::_new_SP, even aligned
 2591 //        |        |        |
 2592 //
 2593 // Note 1: Only region 8-11 is determined by the allocator.  Region 0-5 is
 2594 //         known from SELF's arguments and the Java calling convention.
 2595 //         Region 6-7 is determined per call site.
 2596 // Note 2: If the calling convention leaves holes in the incoming argument
 2597 //         area, those holes are owned by SELF.  Holes in the outgoing area
 2598 //         are owned by the CALLEE.  Holes should not be necessary in the
 2599 //         incoming area, as the Java calling convention is completely under
 2600 //         the control of the AD file.  Doubles can be sorted and packed to
 2601 //         avoid holes.  Holes in the outgoing arguments may be necessary for
 2602 //         varargs C calling conventions.
 2603 // Note 3: Region 0-3 is even aligned, with pad2 as needed.  Region 3-5 is
 2604 //         even aligned with pad0 as needed.
 2605 //         Region 6 is even aligned.  Region 6-7 is NOT even aligned;
 2606 //           (the latter is true on Intel but is it false on RISCV?)
 2607 //         region 6-11 is even aligned; it may be padded out more so that
 2608 //         the region from SP to FP meets the minimum stack alignment.
 2609 // Note 4: For I2C adapters, the incoming FP may not meet the minimum stack
 2610 //         alignment.  Region 11, pad1, may be dynamically extended so that
 2611 //         SP meets the minimum alignment.
 2612 
 2613 frame %{
 2614   // These three registers define part of the calling convention
 2615   // between compiled code and the interpreter.
 2616 
 2617   // Inline Cache Register or methodOop for I2C.
 2618   inline_cache_reg(R31);
 2619 
 2620   // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
 2621   cisc_spilling_operand_name(indOffset);
 2622 
 2623   // Number of stack slots consumed by locking an object
 2624   // generate Compile::sync_stack_slots
 2625   // VMRegImpl::slots_per_word = wordSize / stack_slot_size = 8 / 4 = 2
 2626   sync_stack_slots(1 * VMRegImpl::slots_per_word);
 2627 
 2628   // Compiled code's Frame Pointer
 2629   frame_pointer(R2);
 2630 
 2631   // Interpreter stores its frame pointer in a register which is
 2632   // stored to the stack by I2CAdaptors.
 2633   // I2CAdaptors convert from interpreted java to compiled java.
 2634   interpreter_frame_pointer(R8);
 2635 
 2636   // Stack alignment requirement
 2637   stack_alignment(StackAlignmentInBytes); // Alignment size in bytes (128-bit -> 16 bytes)
 2638 
 2639   // Number of outgoing stack slots killed above the out_preserve_stack_slots
 2640   // for calls to C.  Supports the var-args backing area for register parms.
 2641   varargs_C_out_slots_killed(frame::arg_reg_save_area_bytes / BytesPerInt);
 2642 
 2643   // The after-PROLOG location of the return address.  Location of
 2644   // return address specifies a type (REG or STACK) and a number
 2645   // representing the register number (i.e. - use a register name) or
 2646   // stack slot.
 2647   // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
 2648   // Otherwise, it is above the locks and verification slot and alignment word
 2649   // TODO this may well be correct but need to check why that - 2 is there
 2650   // ppc port uses 0 but we definitely need to allow for fixed_slots
 2651   // which folds in the space used for monitors
 2652   return_addr(STACK - 2 +
 2653               align_up((Compile::current()->in_preserve_stack_slots() +
 2654                         Compile::current()->fixed_slots()),
 2655                        stack_alignment_in_slots()));
 2656 
 2657   // Location of compiled Java return values.  Same as C for now.
 2658   return_value
 2659   %{
 2660     assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL,
 2661            "only return normal values");
 2662 
 2663     static const int lo[Op_RegL + 1] = { // enum name
 2664       0,                                 // Op_Node
 2665       0,                                 // Op_Set
 2666       R10_num,                           // Op_RegN
 2667       R10_num,                           // Op_RegI
 2668       R10_num,                           // Op_RegP
 2669       F10_num,                           // Op_RegF
 2670       F10_num,                           // Op_RegD
 2671       R10_num                            // Op_RegL
 2672     };
 2673 
 2674     static const int hi[Op_RegL + 1] = { // enum name
 2675       0,                                 // Op_Node
 2676       0,                                 // Op_Set
 2677       OptoReg::Bad,                      // Op_RegN
 2678       OptoReg::Bad,                      // Op_RegI
 2679       R10_H_num,                         // Op_RegP
 2680       OptoReg::Bad,                      // Op_RegF
 2681       F10_H_num,                         // Op_RegD
 2682       R10_H_num                          // Op_RegL
 2683     };
 2684 
 2685     return OptoRegPair(hi[ideal_reg], lo[ideal_reg]);
 2686   %}
 2687 %}
 2688 
 2689 //----------ATTRIBUTES---------------------------------------------------------
 2690 //----------Operand Attributes-------------------------------------------------
 2691 op_attrib op_cost(1);        // Required cost attribute
 2692 
 2693 //----------Instruction Attributes---------------------------------------------
 2694 ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute
 2695 ins_attrib ins_size(32);        // Required size attribute (in bits)
 2696 ins_attrib ins_short_branch(0); // Required flag: is this instruction
 2697                                 // a non-matching short branch variant
 2698                                 // of some long branch?
 2699 ins_attrib ins_alignment(4);    // Required alignment attribute (must
 2700                                 // be a power of 2) specifies the
 2701                                 // alignment that some part of the
 2702                                 // instruction (not necessarily the
 2703                                 // start) requires.  If > 1, a
 2704                                 // compute_padding() function must be
 2705                                 // provided for the instruction
 2706 
 2707 //----------OPERANDS-----------------------------------------------------------
 2708 // Operand definitions must precede instruction definitions for correct parsing
 2709 // in the ADLC because operands constitute user defined types which are used in
 2710 // instruction definitions.
 2711 
 2712 //----------Simple Operands----------------------------------------------------
 2713 
 2714 // Integer operands 32 bit
 2715 // 32 bit immediate
 2716 operand immI()
 2717 %{
 2718   match(ConI);
 2719 
 2720   op_cost(0);
 2721   format %{ %}
 2722   interface(CONST_INTER);
 2723 %}
 2724 
 2725 // 32 bit zero
 2726 operand immI0()
 2727 %{
 2728   predicate(n->get_int() == 0);
 2729   match(ConI);
 2730 
 2731   op_cost(0);
 2732   format %{ %}
 2733   interface(CONST_INTER);
 2734 %}
 2735 
 2736 // 32 bit unit increment
 2737 operand immI_1()
 2738 %{
 2739   predicate(n->get_int() == 1);
 2740   match(ConI);
 2741 
 2742   op_cost(0);
 2743   format %{ %}
 2744   interface(CONST_INTER);
 2745 %}
 2746 
 2747 // 32 bit unit decrement
 2748 operand immI_M1()
 2749 %{
 2750   predicate(n->get_int() == -1);
 2751   match(ConI);
 2752 
 2753   op_cost(0);
 2754   format %{ %}
 2755   interface(CONST_INTER);
 2756 %}
 2757 
 2758 // Unsigned Integer Immediate:  6-bit int, greater than 32
 2759 operand uimmI6_ge32() %{
 2760   predicate(((unsigned int)(n->get_int()) < 64) && (n->get_int() >= 32));
 2761   match(ConI);
 2762   op_cost(0);
 2763   format %{ %}
 2764   interface(CONST_INTER);
 2765 %}
 2766 
 2767 operand immI_le_4()
 2768 %{
 2769   predicate(n->get_int() <= 4);
 2770   match(ConI);
 2771 
 2772   op_cost(0);
 2773   format %{ %}
 2774   interface(CONST_INTER);
 2775 %}
 2776 
 2777 operand immI_16()
 2778 %{
 2779   predicate(n->get_int() == 16);
 2780   match(ConI);
 2781   op_cost(0);
 2782   format %{ %}
 2783   interface(CONST_INTER);
 2784 %}
 2785 
 2786 operand immI_24()
 2787 %{
 2788   predicate(n->get_int() == 24);
 2789   match(ConI);
 2790   op_cost(0);
 2791   format %{ %}
 2792   interface(CONST_INTER);
 2793 %}
 2794 
 2795 operand immI_31()
 2796 %{
 2797   predicate(n->get_int() == 31);
 2798   match(ConI);
 2799 
 2800   op_cost(0);
 2801   format %{ %}
 2802   interface(CONST_INTER);
 2803 %}
 2804 
 2805 operand immI_63()
 2806 %{
 2807   predicate(n->get_int() == 63);
 2808   match(ConI);
 2809 
 2810   op_cost(0);
 2811   format %{ %}
 2812   interface(CONST_INTER);
 2813 %}
 2814 
 2815 // 32 bit integer valid for add immediate
 2816 operand immIAdd()
 2817 %{
 2818   predicate(Assembler::operand_valid_for_add_immediate((int64_t)n->get_int()));
 2819   match(ConI);
 2820   op_cost(0);
 2821   format %{ %}
 2822   interface(CONST_INTER);
 2823 %}
 2824 
 2825 // 32 bit integer valid for sub immediate
 2826 operand immISub()
 2827 %{
 2828   predicate(Assembler::operand_valid_for_add_immediate(-(int64_t)n->get_int()));
 2829   match(ConI);
 2830   op_cost(0);
 2831   format %{ %}
 2832   interface(CONST_INTER);
 2833 %}
 2834 
 2835 // 5 bit signed value.
 2836 operand immI5()
 2837 %{
 2838   predicate(n->get_int() <= 15 && n->get_int() >= -16);
 2839   match(ConI);
 2840 
 2841   op_cost(0);
 2842   format %{ %}
 2843   interface(CONST_INTER);
 2844 %}
 2845 
 2846 // 5 bit signed value (simm5)
 2847 operand immL5()
 2848 %{
 2849   predicate(n->get_long() <= 15 && n->get_long() >= -16);
 2850   match(ConL);
 2851 
 2852   op_cost(0);
 2853   format %{ %}
 2854   interface(CONST_INTER);
 2855 %}
 2856 
 2857 // Integer operands 64 bit
 2858 // 64 bit immediate
 2859 operand immL()
 2860 %{
 2861   match(ConL);
 2862 
 2863   op_cost(0);
 2864   format %{ %}
 2865   interface(CONST_INTER);
 2866 %}
 2867 
 2868 // 64 bit zero
 2869 operand immL0()
 2870 %{
 2871   predicate(n->get_long() == 0);
 2872   match(ConL);
 2873 
 2874   op_cost(0);
 2875   format %{ %}
 2876   interface(CONST_INTER);
 2877 %}
 2878 
 2879 // Pointer operands
 2880 // Pointer Immediate
 2881 operand immP()
 2882 %{
 2883   match(ConP);
 2884 
 2885   op_cost(0);
 2886   format %{ %}
 2887   interface(CONST_INTER);
 2888 %}
 2889 
 2890 // NULL Pointer Immediate
 2891 operand immP0()
 2892 %{
 2893   predicate(n->get_ptr() == 0);
 2894   match(ConP);
 2895 
 2896   op_cost(0);
 2897   format %{ %}
 2898   interface(CONST_INTER);
 2899 %}
 2900 
 2901 // Pointer Immediate One
 2902 // this is used in object initialization (initial object header)
 2903 operand immP_1()
 2904 %{
 2905   predicate(n->get_ptr() == 1);
 2906   match(ConP);
 2907 
 2908   op_cost(0);
 2909   format %{ %}
 2910   interface(CONST_INTER);
 2911 %}
 2912 
 2913 // Card Table Byte Map Base
 2914 operand immByteMapBase()
 2915 %{
 2916   // Get base of card map
 2917   predicate(BarrierSet::barrier_set()->is_a(BarrierSet::CardTableBarrierSet) &&
 2918             (CardTable::CardValue*)n->get_ptr() ==
 2919              ((CardTableBarrierSet*)(BarrierSet::barrier_set()))->card_table()->byte_map_base());
 2920   match(ConP);
 2921 
 2922   op_cost(0);
 2923   format %{ %}
 2924   interface(CONST_INTER);
 2925 %}
 2926 
 2927 // Int Immediate: low 16-bit mask
 2928 operand immI_16bits()
 2929 %{
 2930   predicate(n->get_int() == 0xFFFF);
 2931   match(ConI);
 2932   op_cost(0);
 2933   format %{ %}
 2934   interface(CONST_INTER);
 2935 %}
 2936 
 2937 // Long Immediate: low 32-bit mask
 2938 operand immL_32bits()
 2939 %{
 2940   predicate(n->get_long() == 0xFFFFFFFFL);
 2941   match(ConL);
 2942   op_cost(0);
 2943   format %{ %}
 2944   interface(CONST_INTER);
 2945 %}
 2946 
 2947 // 64 bit unit decrement
 2948 operand immL_M1()
 2949 %{
 2950   predicate(n->get_long() == -1);
 2951   match(ConL);
 2952 
 2953   op_cost(0);
 2954   format %{ %}
 2955   interface(CONST_INTER);
 2956 %}
 2957 
 2958 
 2959 // 32 bit offset of pc in thread anchor
 2960 
 2961 operand immL_pc_off()
 2962 %{
 2963   predicate(n->get_long() == in_bytes(JavaThread::frame_anchor_offset()) +
 2964                              in_bytes(JavaFrameAnchor::last_Java_pc_offset()));
 2965   match(ConL);
 2966 
 2967   op_cost(0);
 2968   format %{ %}
 2969   interface(CONST_INTER);
 2970 %}
 2971 
 2972 // 64 bit integer valid for add immediate
 2973 operand immLAdd()
 2974 %{
 2975   predicate(Assembler::operand_valid_for_add_immediate(n->get_long()));
 2976   match(ConL);
 2977   op_cost(0);
 2978   format %{ %}
 2979   interface(CONST_INTER);
 2980 %}
 2981 
 2982 // 64 bit integer valid for sub immediate
 2983 operand immLSub()
 2984 %{
 2985   predicate(Assembler::operand_valid_for_add_immediate(-(n->get_long())));
 2986   match(ConL);
 2987   op_cost(0);
 2988   format %{ %}
 2989   interface(CONST_INTER);
 2990 %}
 2991 
 2992 // Narrow pointer operands
 2993 // Narrow Pointer Immediate
 2994 operand immN()
 2995 %{
 2996   match(ConN);
 2997 
 2998   op_cost(0);
 2999   format %{ %}
 3000   interface(CONST_INTER);
 3001 %}
 3002 
 3003 // Narrow NULL Pointer Immediate
 3004 operand immN0()
 3005 %{
 3006   predicate(n->get_narrowcon() == 0);
 3007   match(ConN);
 3008 
 3009   op_cost(0);
 3010   format %{ %}
 3011   interface(CONST_INTER);
 3012 %}
 3013 
 3014 operand immNKlass()
 3015 %{
 3016   match(ConNKlass);
 3017 
 3018   op_cost(0);
 3019   format %{ %}
 3020   interface(CONST_INTER);
 3021 %}
 3022 
 3023 // Float and Double operands
 3024 // Double Immediate
 3025 operand immD()
 3026 %{
 3027   match(ConD);
 3028   op_cost(0);
 3029   format %{ %}
 3030   interface(CONST_INTER);
 3031 %}
 3032 
 3033 // Double Immediate: +0.0d
 3034 operand immD0()
 3035 %{
 3036   predicate(jlong_cast(n->getd()) == 0);
 3037   match(ConD);
 3038 
 3039   op_cost(0);
 3040   format %{ %}
 3041   interface(CONST_INTER);
 3042 %}
 3043 
 3044 // Float Immediate
 3045 operand immF()
 3046 %{
 3047   match(ConF);
 3048   op_cost(0);
 3049   format %{ %}
 3050   interface(CONST_INTER);
 3051 %}
 3052 
 3053 // Float Immediate: +0.0f.
 3054 operand immF0()
 3055 %{
 3056   predicate(jint_cast(n->getf()) == 0);
 3057   match(ConF);
 3058 
 3059   op_cost(0);
 3060   format %{ %}
 3061   interface(CONST_INTER);
 3062 %}
 3063 
 3064 operand immIOffset()
 3065 %{
 3066   predicate(is_imm_in_range(n->get_int(), 12, 0));
 3067   match(ConI);
 3068   op_cost(0);
 3069   format %{ %}
 3070   interface(CONST_INTER);
 3071 %}
 3072 
 3073 operand immLOffset()
 3074 %{
 3075   predicate(is_imm_in_range(n->get_long(), 12, 0));
 3076   match(ConL);
 3077   op_cost(0);
 3078   format %{ %}
 3079   interface(CONST_INTER);
 3080 %}
 3081 
 3082 // Scale values
 3083 operand immIScale()
 3084 %{
 3085   predicate(1 <= n->get_int() && (n->get_int() <= 3));
 3086   match(ConI);
 3087 
 3088   op_cost(0);
 3089   format %{ %}
 3090   interface(CONST_INTER);
 3091 %}
 3092 
 3093 // Integer 32 bit Register Operands
 3094 operand iRegI()
 3095 %{
 3096   constraint(ALLOC_IN_RC(any_reg32));
 3097   match(RegI);
 3098   match(iRegINoSp);
 3099   op_cost(0);
 3100   format %{ %}
 3101   interface(REG_INTER);
 3102 %}
 3103 
 3104 // Integer 32 bit Register not Special
 3105 operand iRegINoSp()
 3106 %{
 3107   constraint(ALLOC_IN_RC(no_special_reg32));
 3108   match(RegI);
 3109   op_cost(0);
 3110   format %{ %}
 3111   interface(REG_INTER);
 3112 %}
 3113 
 3114 // Register R10 only
 3115 operand iRegI_R10()
 3116 %{
 3117   constraint(ALLOC_IN_RC(int_r10_reg));
 3118   match(RegI);
 3119   match(iRegINoSp);
 3120   op_cost(0);
 3121   format %{ %}
 3122   interface(REG_INTER);
 3123 %}
 3124 
 3125 // Register R12 only
 3126 operand iRegI_R12()
 3127 %{
 3128   constraint(ALLOC_IN_RC(int_r12_reg));
 3129   match(RegI);
 3130   match(iRegINoSp);
 3131   op_cost(0);
 3132   format %{ %}
 3133   interface(REG_INTER);
 3134 %}
 3135 
 3136 // Register R13 only
 3137 operand iRegI_R13()
 3138 %{
 3139   constraint(ALLOC_IN_RC(int_r13_reg));
 3140   match(RegI);
 3141   match(iRegINoSp);
 3142   op_cost(0);
 3143   format %{ %}
 3144   interface(REG_INTER);
 3145 %}
 3146 
 3147 // Register R14 only
 3148 operand iRegI_R14()
 3149 %{
 3150   constraint(ALLOC_IN_RC(int_r14_reg));
 3151   match(RegI);
 3152   match(iRegINoSp);
 3153   op_cost(0);
 3154   format %{ %}
 3155   interface(REG_INTER);
 3156 %}
 3157 
 3158 // Integer 64 bit Register Operands
 3159 operand iRegL()
 3160 %{
 3161   constraint(ALLOC_IN_RC(any_reg));
 3162   match(RegL);
 3163   match(iRegLNoSp);
 3164   op_cost(0);
 3165   format %{ %}
 3166   interface(REG_INTER);
 3167 %}
 3168 
 3169 // Integer 64 bit Register not Special
 3170 operand iRegLNoSp()
 3171 %{
 3172   constraint(ALLOC_IN_RC(no_special_reg));
 3173   match(RegL);
 3174   match(iRegL_R10);
 3175   format %{ %}
 3176   interface(REG_INTER);
 3177 %}
 3178 
 3179 // Long 64 bit Register R28 only
 3180 operand iRegL_R28()
 3181 %{
 3182   constraint(ALLOC_IN_RC(r28_reg));
 3183   match(RegL);
 3184   match(iRegLNoSp);
 3185   op_cost(0);
 3186   format %{ %}
 3187   interface(REG_INTER);
 3188 %}
 3189 
 3190 // Long 64 bit Register R29 only
 3191 operand iRegL_R29()
 3192 %{
 3193   constraint(ALLOC_IN_RC(r29_reg));
 3194   match(RegL);
 3195   match(iRegLNoSp);
 3196   op_cost(0);
 3197   format %{ %}
 3198   interface(REG_INTER);
 3199 %}
 3200 
 3201 // Long 64 bit Register R30 only
 3202 operand iRegL_R30()
 3203 %{
 3204   constraint(ALLOC_IN_RC(r30_reg));
 3205   match(RegL);
 3206   match(iRegLNoSp);
 3207   op_cost(0);
 3208   format %{ %}
 3209   interface(REG_INTER);
 3210 %}
 3211 
 3212 // Pointer Register Operands
 3213 // Pointer Register
 3214 operand iRegP()
 3215 %{
 3216   constraint(ALLOC_IN_RC(ptr_reg));
 3217   match(RegP);
 3218   match(iRegPNoSp);
 3219   match(iRegP_R10);
 3220   match(javaThread_RegP);
 3221   op_cost(0);
 3222   format %{ %}
 3223   interface(REG_INTER);
 3224 %}
 3225 
 3226 // Pointer 64 bit Register not Special
 3227 operand iRegPNoSp()
 3228 %{
 3229   constraint(ALLOC_IN_RC(no_special_ptr_reg));
 3230   match(RegP);
 3231   op_cost(0);
 3232   format %{ %}
 3233   interface(REG_INTER);
 3234 %}
 3235 
 3236 operand iRegP_R10()
 3237 %{
 3238   constraint(ALLOC_IN_RC(r10_reg));
 3239   match(RegP);
 3240   // match(iRegP);
 3241   match(iRegPNoSp);
 3242   op_cost(0);
 3243   format %{ %}
 3244   interface(REG_INTER);
 3245 %}
 3246 
 3247 // Pointer 64 bit Register R11 only
 3248 operand iRegP_R11()
 3249 %{
 3250   constraint(ALLOC_IN_RC(r11_reg));
 3251   match(RegP);
 3252   match(iRegPNoSp);
 3253   op_cost(0);
 3254   format %{ %}
 3255   interface(REG_INTER);
 3256 %}
 3257 
 3258 operand iRegP_R12()
 3259 %{
 3260   constraint(ALLOC_IN_RC(r12_reg));
 3261   match(RegP);
 3262   // match(iRegP);
 3263   match(iRegPNoSp);
 3264   op_cost(0);
 3265   format %{ %}
 3266   interface(REG_INTER);
 3267 %}
 3268 
 3269 // Pointer 64 bit Register R13 only
 3270 operand iRegP_R13()
 3271 %{
 3272   constraint(ALLOC_IN_RC(r13_reg));
 3273   match(RegP);
 3274   match(iRegPNoSp);
 3275   op_cost(0);
 3276   format %{ %}
 3277   interface(REG_INTER);
 3278 %}
 3279 
 3280 operand iRegP_R14()
 3281 %{
 3282   constraint(ALLOC_IN_RC(r14_reg));
 3283   match(RegP);
 3284   // match(iRegP);
 3285   match(iRegPNoSp);
 3286   op_cost(0);
 3287   format %{ %}
 3288   interface(REG_INTER);
 3289 %}
 3290 
 3291 operand iRegP_R15()
 3292 %{
 3293   constraint(ALLOC_IN_RC(r15_reg));
 3294   match(RegP);
 3295   // match(iRegP);
 3296   match(iRegPNoSp);
 3297   op_cost(0);
 3298   format %{ %}
 3299   interface(REG_INTER);
 3300 %}
 3301 
 3302 operand iRegP_R16()
 3303 %{
 3304   constraint(ALLOC_IN_RC(r16_reg));
 3305   match(RegP);
 3306   // match(iRegP);
 3307   match(iRegPNoSp);
 3308   op_cost(0);
 3309   format %{ %}
 3310   interface(REG_INTER);
 3311 %}
 3312 
 3313 // Pointer 64 bit Register R28 only
 3314 operand iRegP_R28()
 3315 %{
 3316   constraint(ALLOC_IN_RC(r28_reg));
 3317   match(RegP);
 3318   match(iRegPNoSp);
 3319   op_cost(0);
 3320   format %{ %}
 3321   interface(REG_INTER);
 3322 %}
 3323 
 3324 // Pointer Register Operands
 3325 // Narrow Pointer Register
 3326 operand iRegN()
 3327 %{
 3328   constraint(ALLOC_IN_RC(any_reg32));
 3329   match(RegN);
 3330   match(iRegNNoSp);
 3331   op_cost(0);
 3332   format %{ %}
 3333   interface(REG_INTER);
 3334 %}
 3335 
 3336 // Integer 64 bit Register not Special
 3337 operand iRegNNoSp()
 3338 %{
 3339   constraint(ALLOC_IN_RC(no_special_reg32));
 3340   match(RegN);
 3341   op_cost(0);
 3342   format %{ %}
 3343   interface(REG_INTER);
 3344 %}
 3345 
 3346 // heap base register -- used for encoding immN0
 3347 operand iRegIHeapbase()
 3348 %{
 3349   constraint(ALLOC_IN_RC(heapbase_reg));
 3350   match(RegI);
 3351   op_cost(0);
 3352   format %{ %}
 3353   interface(REG_INTER);
 3354 %}
 3355 
 3356 // Long 64 bit Register R10 only
 3357 operand iRegL_R10()
 3358 %{
 3359   constraint(ALLOC_IN_RC(r10_reg));
 3360   match(RegL);
 3361   match(iRegLNoSp);
 3362   op_cost(0);
 3363   format %{ %}
 3364   interface(REG_INTER);
 3365 %}
 3366 
 3367 // Float Register
 3368 // Float register operands
 3369 operand fRegF()
 3370 %{
 3371   constraint(ALLOC_IN_RC(float_reg));
 3372   match(RegF);
 3373 
 3374   op_cost(0);
 3375   format %{ %}
 3376   interface(REG_INTER);
 3377 %}
 3378 
 3379 // Double Register
 3380 // Double register operands
 3381 operand fRegD()
 3382 %{
 3383   constraint(ALLOC_IN_RC(double_reg));
 3384   match(RegD);
 3385 
 3386   op_cost(0);
 3387   format %{ %}
 3388   interface(REG_INTER);
 3389 %}
 3390 
 3391 // Generic vector class. This will be used for
 3392 // all vector operands.
 3393 operand vReg()
 3394 %{
 3395   constraint(ALLOC_IN_RC(vectora_reg));
 3396   match(VecA);
 3397   op_cost(0);
 3398   format %{ %}
 3399   interface(REG_INTER);
 3400 %}
 3401 
 3402 operand vReg_V1()
 3403 %{
 3404   constraint(ALLOC_IN_RC(v1_reg));
 3405   match(VecA);
 3406   match(vReg);
 3407   op_cost(0);
 3408   format %{ %}
 3409   interface(REG_INTER);
 3410 %}
 3411 
 3412 operand vReg_V2()
 3413 %{
 3414   constraint(ALLOC_IN_RC(v2_reg));
 3415   match(VecA);
 3416   match(vReg);
 3417   op_cost(0);
 3418   format %{ %}
 3419   interface(REG_INTER);
 3420 %}
 3421 
 3422 operand vReg_V3()
 3423 %{
 3424   constraint(ALLOC_IN_RC(v3_reg));
 3425   match(VecA);
 3426   match(vReg);
 3427   op_cost(0);
 3428   format %{ %}
 3429   interface(REG_INTER);
 3430 %}
 3431 
 3432 operand vReg_V4()
 3433 %{
 3434   constraint(ALLOC_IN_RC(v4_reg));
 3435   match(VecA);
 3436   match(vReg);
 3437   op_cost(0);
 3438   format %{ %}
 3439   interface(REG_INTER);
 3440 %}
 3441 
 3442 operand vReg_V5()
 3443 %{
 3444   constraint(ALLOC_IN_RC(v5_reg));
 3445   match(VecA);
 3446   match(vReg);
 3447   op_cost(0);
 3448   format %{ %}
 3449   interface(REG_INTER);
 3450 %}
 3451 
 3452 // Java Thread Register
 3453 operand javaThread_RegP(iRegP reg)
 3454 %{
 3455   constraint(ALLOC_IN_RC(java_thread_reg)); // java_thread_reg
 3456   match(reg);
 3457   op_cost(0);
 3458   format %{ %}
 3459   interface(REG_INTER);
 3460 %}
 3461 
 3462 //----------Memory Operands----------------------------------------------------
 3463 // RISCV has only base_plus_offset and literal address mode, so no need to use
 3464 // index and scale. Here set index as 0xffffffff and scale as 0x0.
 3465 operand indirect(iRegP reg)
 3466 %{
 3467   constraint(ALLOC_IN_RC(ptr_reg));
 3468   match(reg);
 3469   op_cost(0);
 3470   format %{ "[$reg]" %}
 3471   interface(MEMORY_INTER) %{
 3472     base($reg);
 3473     index(0xffffffff);
 3474     scale(0x0);
 3475     disp(0x0);
 3476   %}
 3477 %}
 3478 
 3479 operand indOffI(iRegP reg, immIOffset off)
 3480 %{
 3481   constraint(ALLOC_IN_RC(ptr_reg));
 3482   match(AddP reg off);
 3483   op_cost(0);
 3484   format %{ "[$reg, $off]" %}
 3485   interface(MEMORY_INTER) %{
 3486     base($reg);
 3487     index(0xffffffff);
 3488     scale(0x0);
 3489     disp($off);
 3490   %}
 3491 %}
 3492 
 3493 operand indOffL(iRegP reg, immLOffset off)
 3494 %{
 3495   constraint(ALLOC_IN_RC(ptr_reg));
 3496   match(AddP reg off);
 3497   op_cost(0);
 3498   format %{ "[$reg, $off]" %}
 3499   interface(MEMORY_INTER) %{
 3500     base($reg);
 3501     index(0xffffffff);
 3502     scale(0x0);
 3503     disp($off);
 3504   %}
 3505 %}
 3506 
 3507 operand indirectN(iRegN reg)
 3508 %{
 3509   predicate(CompressedOops::shift() == 0);
 3510   constraint(ALLOC_IN_RC(ptr_reg));
 3511   match(DecodeN reg);
 3512   op_cost(0);
 3513   format %{ "[$reg]\t# narrow" %}
 3514   interface(MEMORY_INTER) %{
 3515     base($reg);
 3516     index(0xffffffff);
 3517     scale(0x0);
 3518     disp(0x0);
 3519   %}
 3520 %}
 3521 
 3522 operand indOffIN(iRegN reg, immIOffset off)
 3523 %{
 3524   predicate(CompressedOops::shift() == 0);
 3525   constraint(ALLOC_IN_RC(ptr_reg));
 3526   match(AddP (DecodeN reg) off);
 3527   op_cost(0);
 3528   format %{ "[$reg, $off]\t# narrow" %}
 3529   interface(MEMORY_INTER) %{
 3530     base($reg);
 3531     index(0xffffffff);
 3532     scale(0x0);
 3533     disp($off);
 3534   %}
 3535 %}
 3536 
 3537 operand indOffLN(iRegN reg, immLOffset off)
 3538 %{
 3539   predicate(CompressedOops::shift() == 0);
 3540   constraint(ALLOC_IN_RC(ptr_reg));
 3541   match(AddP (DecodeN reg) off);
 3542   op_cost(0);
 3543   format %{ "[$reg, $off]\t# narrow" %}
 3544   interface(MEMORY_INTER) %{
 3545     base($reg);
 3546     index(0xffffffff);
 3547     scale(0x0);
 3548     disp($off);
 3549   %}
 3550 %}
 3551 
 3552 // RISCV opto stubs need to write to the pc slot in the thread anchor
 3553 operand thread_anchor_pc(javaThread_RegP reg, immL_pc_off off)
 3554 %{
 3555   constraint(ALLOC_IN_RC(ptr_reg));
 3556   match(AddP reg off);
 3557   op_cost(0);
 3558   format %{ "[$reg, $off]" %}
 3559   interface(MEMORY_INTER) %{
 3560     base($reg);
 3561     index(0xffffffff);
 3562     scale(0x0);
 3563     disp($off);
 3564   %}
 3565 %}
 3566 
 3567 
 3568 //----------Special Memory Operands--------------------------------------------
 3569 // Stack Slot Operand - This operand is used for loading and storing temporary
 3570 //                      values on the stack where a match requires a value to
 3571 //                      flow through memory.
 3572 operand stackSlotI(sRegI reg)
 3573 %{
 3574   constraint(ALLOC_IN_RC(stack_slots));
 3575   // No match rule because this operand is only generated in matching
 3576   // match(RegI);
 3577   format %{ "[$reg]" %}
 3578   interface(MEMORY_INTER) %{
 3579     base(0x02);  // RSP
 3580     index(0xffffffff);  // No Index
 3581     scale(0x0);  // No Scale
 3582     disp($reg);  // Stack Offset
 3583   %}
 3584 %}
 3585 
 3586 operand stackSlotF(sRegF reg)
 3587 %{
 3588   constraint(ALLOC_IN_RC(stack_slots));
 3589   // No match rule because this operand is only generated in matching
 3590   // match(RegF);
 3591   format %{ "[$reg]" %}
 3592   interface(MEMORY_INTER) %{
 3593     base(0x02);  // RSP
 3594     index(0xffffffff);  // No Index
 3595     scale(0x0);  // No Scale
 3596     disp($reg);  // Stack Offset
 3597   %}
 3598 %}
 3599 
 3600 operand stackSlotD(sRegD reg)
 3601 %{
 3602   constraint(ALLOC_IN_RC(stack_slots));
 3603   // No match rule because this operand is only generated in matching
 3604   // match(RegD);
 3605   format %{ "[$reg]" %}
 3606   interface(MEMORY_INTER) %{
 3607     base(0x02);  // RSP
 3608     index(0xffffffff);  // No Index
 3609     scale(0x0);  // No Scale
 3610     disp($reg);  // Stack Offset
 3611   %}
 3612 %}
 3613 
 3614 operand stackSlotL(sRegL reg)
 3615 %{
 3616   constraint(ALLOC_IN_RC(stack_slots));
 3617   // No match rule because this operand is only generated in matching
 3618   // match(RegL);
 3619   format %{ "[$reg]" %}
 3620   interface(MEMORY_INTER) %{
 3621     base(0x02);  // RSP
 3622     index(0xffffffff);  // No Index
 3623     scale(0x0);  // No Scale
 3624     disp($reg);  // Stack Offset
 3625   %}
 3626 %}
 3627 
 3628 // Special operand allowing long args to int ops to be truncated for free
 3629 
 3630 operand iRegL2I(iRegL reg) %{
 3631 
 3632   op_cost(0);
 3633 
 3634   match(ConvL2I reg);
 3635 
 3636   format %{ "l2i($reg)" %}
 3637 
 3638   interface(REG_INTER)
 3639 %}
 3640 
 3641 
 3642 // Comparison Operands
 3643 // NOTE: Label is a predefined operand which should not be redefined in
 3644 //       the AD file. It is generically handled within the ADLC.
 3645 
 3646 //----------Conditional Branch Operands----------------------------------------
 3647 // Comparison Op  - This is the operation of the comparison, and is limited to
 3648 //                  the following set of codes:
 3649 //                  L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
 3650 //
 3651 // Other attributes of the comparison, such as unsignedness, are specified
 3652 // by the comparison instruction that sets a condition code flags register.
 3653 // That result is represented by a flags operand whose subtype is appropriate
 3654 // to the unsignedness (etc.) of the comparison.
 3655 //
 3656 // Later, the instruction which matches both the Comparison Op (a Bool) and
 3657 // the flags (produced by the Cmp) specifies the coding of the comparison op
 3658 // by matching a specific subtype of Bool operand below, such as cmpOpU.
 3659 
 3660 
 3661 // used for signed integral comparisons and fp comparisons
 3662 operand cmpOp()
 3663 %{
 3664   match(Bool);
 3665 
 3666   format %{ "" %}
 3667 
 3668   // the values in interface derives from struct BoolTest::mask
 3669   interface(COND_INTER) %{
 3670     equal(0x0, "eq");
 3671     greater(0x1, "gt");
 3672     overflow(0x2, "overflow");
 3673     less(0x3, "lt");
 3674     not_equal(0x4, "ne");
 3675     less_equal(0x5, "le");
 3676     no_overflow(0x6, "no_overflow");
 3677     greater_equal(0x7, "ge");
 3678   %}
 3679 %}
 3680 
 3681 // used for unsigned integral comparisons
 3682 operand cmpOpU()
 3683 %{
 3684   match(Bool);
 3685 
 3686   format %{ "" %}
 3687   // the values in interface derives from struct BoolTest::mask
 3688   interface(COND_INTER) %{
 3689     equal(0x0, "eq");
 3690     greater(0x1, "gtu");
 3691     overflow(0x2, "overflow");
 3692     less(0x3, "ltu");
 3693     not_equal(0x4, "ne");
 3694     less_equal(0x5, "leu");
 3695     no_overflow(0x6, "no_overflow");
 3696     greater_equal(0x7, "geu");
 3697   %}
 3698 %}
 3699 
 3700 // used for certain integral comparisons which can be
 3701 // converted to bxx instructions
 3702 operand cmpOpEqNe()
 3703 %{
 3704   match(Bool);
 3705   op_cost(0);
 3706   predicate(n->as_Bool()->_test._test == BoolTest::ne ||
 3707             n->as_Bool()->_test._test == BoolTest::eq);
 3708 
 3709   format %{ "" %}
 3710   interface(COND_INTER) %{
 3711     equal(0x0, "eq");
 3712     greater(0x1, "gt");
 3713     overflow(0x2, "overflow");
 3714     less(0x3, "lt");
 3715     not_equal(0x4, "ne");
 3716     less_equal(0x5, "le");
 3717     no_overflow(0x6, "no_overflow");
 3718     greater_equal(0x7, "ge");
 3719   %}
 3720 %}
 3721 
 3722 operand cmpOpULtGe()
 3723 %{
 3724   match(Bool);
 3725   op_cost(0);
 3726   predicate(n->as_Bool()->_test._test == BoolTest::lt ||
 3727             n->as_Bool()->_test._test == BoolTest::ge);
 3728 
 3729   format %{ "" %}
 3730   interface(COND_INTER) %{
 3731     equal(0x0, "eq");
 3732     greater(0x1, "gt");
 3733     overflow(0x2, "overflow");
 3734     less(0x3, "lt");
 3735     not_equal(0x4, "ne");
 3736     less_equal(0x5, "le");
 3737     no_overflow(0x6, "no_overflow");
 3738     greater_equal(0x7, "ge");
 3739   %}
 3740 %}
 3741 
 3742 operand cmpOpUEqNeLeGt()
 3743 %{
 3744   match(Bool);
 3745   op_cost(0);
 3746   predicate(n->as_Bool()->_test._test == BoolTest::ne ||
 3747             n->as_Bool()->_test._test == BoolTest::eq ||
 3748             n->as_Bool()->_test._test == BoolTest::le ||
 3749             n->as_Bool()->_test._test == BoolTest::gt);
 3750 
 3751   format %{ "" %}
 3752   interface(COND_INTER) %{
 3753     equal(0x0, "eq");
 3754     greater(0x1, "gt");
 3755     overflow(0x2, "overflow");
 3756     less(0x3, "lt");
 3757     not_equal(0x4, "ne");
 3758     less_equal(0x5, "le");
 3759     no_overflow(0x6, "no_overflow");
 3760     greater_equal(0x7, "ge");
 3761   %}
 3762 %}
 3763 
 3764 
 3765 // Flags register, used as output of compare logic
 3766 operand rFlagsReg()
 3767 %{
 3768   constraint(ALLOC_IN_RC(reg_flags));
 3769   match(RegFlags);
 3770 
 3771   op_cost(0);
 3772   format %{ "RFLAGS" %}
 3773   interface(REG_INTER);
 3774 %}
 3775 
 3776 // Special Registers
 3777 
 3778 // Method Register
 3779 operand inline_cache_RegP(iRegP reg)
 3780 %{
 3781   constraint(ALLOC_IN_RC(method_reg)); // inline_cache_reg
 3782   match(reg);
 3783   match(iRegPNoSp);
 3784   op_cost(0);
 3785   format %{ %}
 3786   interface(REG_INTER);
 3787 %}
 3788 
 3789 //----------OPERAND CLASSES----------------------------------------------------
 3790 // Operand Classes are groups of operands that are used as to simplify
 3791 // instruction definitions by not requiring the AD writer to specify
 3792 // separate instructions for every form of operand when the
 3793 // instruction accepts multiple operand types with the same basic
 3794 // encoding and format. The classic case of this is memory operands.
 3795 
 3796 // memory is used to define read/write location for load/store
 3797 // instruction defs. we can turn a memory op into an Address
 3798 
 3799 opclass memory(indirect, indOffI, indOffL, indirectN, indOffIN, indOffLN);
 3800 
 3801 // iRegIorL2I is used for src inputs in rules for 32 bit int (I)
 3802 // operations. it allows the src to be either an iRegI or a (ConvL2I
 3803 // iRegL). in the latter case the l2i normally planted for a ConvL2I
 3804 // can be elided because the 32-bit instruction will just employ the
 3805 // lower 32 bits anyway.
 3806 //
 3807 // n.b. this does not elide all L2I conversions. if the truncated
 3808 // value is consumed by more than one operation then the ConvL2I
 3809 // cannot be bundled into the consuming nodes so an l2i gets planted
 3810 // (actually a mvw $dst $src) and the downstream instructions consume
 3811 // the result of the l2i as an iRegI input. That's a shame since the
 3812 // mvw is actually redundant but its not too costly.
 3813 
 3814 opclass iRegIorL2I(iRegI, iRegL2I);
 3815 opclass iRegIorL(iRegI, iRegL);
 3816 opclass iRegNorP(iRegN, iRegP);
 3817 opclass iRegILNP(iRegI, iRegL, iRegN, iRegP);
 3818 opclass iRegILNPNoSp(iRegINoSp, iRegLNoSp, iRegNNoSp, iRegPNoSp);
 3819 opclass immIorL(immI, immL);
 3820 
 3821 //----------PIPELINE-----------------------------------------------------------
 3822 // Rules which define the behavior of the target architectures pipeline.
 3823 
 3824 // For specific pipelines, e.g. generic RISC-V, define the stages of that pipeline
 3825 //pipe_desc(ID, EX, MEM, WR);
 3826 #define ID   S0
 3827 #define EX   S1
 3828 #define MEM  S2
 3829 #define WR   S3
 3830 
 3831 // Integer ALU reg operation
 3832 pipeline %{
 3833 
 3834 attributes %{
 3835   // RISC-V instructions are of fixed length
 3836   fixed_size_instructions;           // Fixed size instructions TODO does
 3837   max_instructions_per_bundle = 2;   // Generic RISC-V 1, Sifive Series 7 2
 3838   // RISC-V instructions come in 32-bit word units
 3839   instruction_unit_size = 4;         // An instruction is 4 bytes long
 3840   instruction_fetch_unit_size = 64;  // The processor fetches one line
 3841   instruction_fetch_units = 1;       // of 64 bytes
 3842 
 3843   // List of nop instructions
 3844   nops( MachNop );
 3845 %}
 3846 
 3847 // We don't use an actual pipeline model so don't care about resources
 3848 // or description. we do use pipeline classes to introduce fixed
 3849 // latencies
 3850 
 3851 //----------RESOURCES----------------------------------------------------------
 3852 // Resources are the functional units available to the machine
 3853 
 3854 // Generic RISC-V pipeline
 3855 // 1 decoder
 3856 // 1 instruction decoded per cycle
 3857 // 1 load/store ops per cycle, 1 branch, 1 FPU
 3858 // 1 mul, 1 div
 3859 
 3860 resources ( DECODE,
 3861             ALU,
 3862             MUL,
 3863             DIV,
 3864             BRANCH,
 3865             LDST,
 3866             FPU);
 3867 
 3868 //----------PIPELINE DESCRIPTION-----------------------------------------------
 3869 // Pipeline Description specifies the stages in the machine's pipeline
 3870 
 3871 // Define the pipeline as a generic 6 stage pipeline
 3872 pipe_desc(S0, S1, S2, S3, S4, S5);
 3873 
 3874 //----------PIPELINE CLASSES---------------------------------------------------
 3875 // Pipeline Classes describe the stages in which input and output are
 3876 // referenced by the hardware pipeline.
 3877 
 3878 pipe_class fp_dop_reg_reg_s(fRegF dst, fRegF src1, fRegF src2)
 3879 %{
 3880   single_instruction;
 3881   src1   : S1(read);
 3882   src2   : S2(read);
 3883   dst    : S5(write);
 3884   DECODE : ID;
 3885   FPU    : S5;
 3886 %}
 3887 
 3888 pipe_class fp_dop_reg_reg_d(fRegD dst, fRegD src1, fRegD src2)
 3889 %{
 3890   src1   : S1(read);
 3891   src2   : S2(read);
 3892   dst    : S5(write);
 3893   DECODE : ID;
 3894   FPU    : S5;
 3895 %}
 3896 
 3897 pipe_class fp_uop_s(fRegF dst, fRegF src)
 3898 %{
 3899   single_instruction;
 3900   src    : S1(read);
 3901   dst    : S5(write);
 3902   DECODE : ID;
 3903   FPU    : S5;
 3904 %}
 3905 
 3906 pipe_class fp_uop_d(fRegD dst, fRegD src)
 3907 %{
 3908   single_instruction;
 3909   src    : S1(read);
 3910   dst    : S5(write);
 3911   DECODE : ID;
 3912   FPU    : S5;
 3913 %}
 3914 
 3915 pipe_class fp_d2f(fRegF dst, fRegD src)
 3916 %{
 3917   single_instruction;
 3918   src    : S1(read);
 3919   dst    : S5(write);
 3920   DECODE : ID;
 3921   FPU    : S5;
 3922 %}
 3923 
 3924 pipe_class fp_f2d(fRegD dst, fRegF src)
 3925 %{
 3926   single_instruction;
 3927   src    : S1(read);
 3928   dst    : S5(write);
 3929   DECODE : ID;
 3930   FPU    : S5;
 3931 %}
 3932 
 3933 pipe_class fp_f2i(iRegINoSp dst, fRegF src)
 3934 %{
 3935   single_instruction;
 3936   src    : S1(read);
 3937   dst    : S5(write);
 3938   DECODE : ID;
 3939   FPU    : S5;
 3940 %}
 3941 
 3942 pipe_class fp_f2l(iRegLNoSp dst, fRegF src)
 3943 %{
 3944   single_instruction;
 3945   src    : S1(read);
 3946   dst    : S5(write);
 3947   DECODE : ID;
 3948   FPU    : S5;
 3949 %}
 3950 
 3951 pipe_class fp_i2f(fRegF dst, iRegIorL2I src)
 3952 %{
 3953   single_instruction;
 3954   src    : S1(read);
 3955   dst    : S5(write);
 3956   DECODE : ID;
 3957   FPU    : S5;
 3958 %}
 3959 
 3960 pipe_class fp_l2f(fRegF dst, iRegL src)
 3961 %{
 3962   single_instruction;
 3963   src    : S1(read);
 3964   dst    : S5(write);
 3965   DECODE : ID;
 3966   FPU    : S5;
 3967 %}
 3968 
 3969 pipe_class fp_d2i(iRegINoSp dst, fRegD src)
 3970 %{
 3971   single_instruction;
 3972   src    : S1(read);
 3973   dst    : S5(write);
 3974   DECODE : ID;
 3975   FPU    : S5;
 3976 %}
 3977 
 3978 pipe_class fp_d2l(iRegLNoSp dst, fRegD src)
 3979 %{
 3980   single_instruction;
 3981   src    : S1(read);
 3982   dst    : S5(write);
 3983   DECODE : ID;
 3984   FPU    : S5;
 3985 %}
 3986 
 3987 pipe_class fp_i2d(fRegD dst, iRegIorL2I src)
 3988 %{
 3989   single_instruction;
 3990   src    : S1(read);
 3991   dst    : S5(write);
 3992   DECODE : ID;
 3993   FPU    : S5;
 3994 %}
 3995 
 3996 pipe_class fp_l2d(fRegD dst, iRegIorL2I src)
 3997 %{
 3998   single_instruction;
 3999   src    : S1(read);
 4000   dst    : S5(write);
 4001   DECODE : ID;
 4002   FPU    : S5;
 4003 %}
 4004 
 4005 pipe_class fp_div_s(fRegF dst, fRegF src1, fRegF src2)
 4006 %{
 4007   single_instruction;
 4008   src1   : S1(read);
 4009   src2   : S2(read);
 4010   dst    : S5(write);
 4011   DECODE : ID;
 4012   FPU    : S5;
 4013 %}
 4014 
 4015 pipe_class fp_div_d(fRegD dst, fRegD src1, fRegD src2)
 4016 %{
 4017   single_instruction;
 4018   src1   : S1(read);
 4019   src2   : S2(read);
 4020   dst    : S5(write);
 4021   DECODE : ID;
 4022   FPU    : S5;
 4023 %}
 4024 
 4025 pipe_class fp_sqrt_s(fRegF dst, fRegF src1, fRegF src2)
 4026 %{
 4027   single_instruction;
 4028   src1   : S1(read);
 4029   src2   : S2(read);
 4030   dst    : S5(write);
 4031   DECODE : ID;
 4032   FPU    : S5;
 4033 %}
 4034 
 4035 pipe_class fp_sqrt_d(fRegD dst, fRegD src1, fRegD src2)
 4036 %{
 4037   single_instruction;
 4038   src1   : S1(read);
 4039   src2   : S2(read);
 4040   dst    : S5(write);
 4041   DECODE : ID;
 4042   FPU    : S5;
 4043 %}
 4044 
 4045 pipe_class fp_load_constant_s(fRegF dst)
 4046 %{
 4047   single_instruction;
 4048   dst    : S5(write);
 4049   DECODE : ID;
 4050   FPU    : S5;
 4051 %}
 4052 
 4053 pipe_class fp_load_constant_d(fRegD dst)
 4054 %{
 4055   single_instruction;
 4056   dst    : S5(write);
 4057   DECODE : ID;
 4058   FPU    : S5;
 4059 %}
 4060 
 4061 pipe_class fp_load_mem_s(fRegF dst, memory mem)
 4062 %{
 4063   single_instruction;
 4064   mem    : S1(read);
 4065   dst    : S5(write);
 4066   DECODE : ID;
 4067   LDST   : MEM;
 4068 %}
 4069 
 4070 pipe_class fp_load_mem_d(fRegD dst, memory mem)
 4071 %{
 4072   single_instruction;
 4073   mem    : S1(read);
 4074   dst    : S5(write);
 4075   DECODE : ID;
 4076   LDST   : MEM;
 4077 %}
 4078 
 4079 pipe_class fp_store_reg_s(fRegF src, memory mem)
 4080 %{
 4081   single_instruction;
 4082   src    : S1(read);
 4083   mem    : S5(write);
 4084   DECODE : ID;
 4085   LDST   : MEM;
 4086 %}
 4087 
 4088 pipe_class fp_store_reg_d(fRegD src, memory mem)
 4089 %{
 4090   single_instruction;
 4091   src    : S1(read);
 4092   mem    : S5(write);
 4093   DECODE : ID;
 4094   LDST   : MEM;
 4095 %}
 4096 
 4097 //------- Integer ALU operations --------------------------
 4098 
 4099 // Integer ALU reg-reg operation
 4100 // Operands needs in ID, result generated in EX
 4101 // E.g.  ADD   Rd, Rs1, Rs2
 4102 pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2)
 4103 %{
 4104   single_instruction;
 4105   dst    : EX(write);
 4106   src1   : ID(read);
 4107   src2   : ID(read);
 4108   DECODE : ID;
 4109   ALU    : EX;
 4110 %}
 4111 
 4112 // Integer ALU reg operation with constant shift
 4113 // E.g. SLLI    Rd, Rs1, #shift
 4114 pipe_class ialu_reg_shift(iRegI dst, iRegI src1)
 4115 %{
 4116   single_instruction;
 4117   dst    : EX(write);
 4118   src1   : ID(read);
 4119   DECODE : ID;
 4120   ALU    : EX;
 4121 %}
 4122 
 4123 // Integer ALU reg-reg operation with variable shift
 4124 // both operands must be available in ID
 4125 // E.g. SLL   Rd, Rs1, Rs2
 4126 pipe_class ialu_reg_reg_vshift(iRegI dst, iRegI src1, iRegI src2)
 4127 %{
 4128   single_instruction;
 4129   dst    : EX(write);
 4130   src1   : ID(read);
 4131   src2   : ID(read);
 4132   DECODE : ID;
 4133   ALU    : EX;
 4134 %}
 4135 
 4136 // Integer ALU reg operation
 4137 // E.g. NEG   Rd, Rs2
 4138 pipe_class ialu_reg(iRegI dst, iRegI src)
 4139 %{
 4140   single_instruction;
 4141   dst    : EX(write);
 4142   src    : ID(read);
 4143   DECODE : ID;
 4144   ALU    : EX;
 4145 %}
 4146 
 4147 // Integer ALU reg immediate operation
 4148 // E.g. ADDI   Rd, Rs1, #imm
 4149 pipe_class ialu_reg_imm(iRegI dst, iRegI src1)
 4150 %{
 4151   single_instruction;
 4152   dst    : EX(write);
 4153   src1   : ID(read);
 4154   DECODE : ID;
 4155   ALU    : EX;
 4156 %}
 4157 
 4158 // Integer ALU immediate operation (no source operands)
 4159 // E.g. LI    Rd, #imm
 4160 pipe_class ialu_imm(iRegI dst)
 4161 %{
 4162   single_instruction;
 4163   dst    : EX(write);
 4164   DECODE : ID;
 4165   ALU    : EX;
 4166 %}
 4167 
 4168 //------- Multiply pipeline operations --------------------
 4169 
 4170 // Multiply reg-reg
 4171 // E.g. MULW   Rd, Rs1, Rs2
 4172 pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2)
 4173 %{
 4174   single_instruction;
 4175   dst    : WR(write);
 4176   src1   : ID(read);
 4177   src2   : ID(read);
 4178   DECODE : ID;
 4179   MUL    : WR;
 4180 %}
 4181 
 4182 // E.g. MUL   RD, Rs1, Rs2
 4183 pipe_class lmul_reg_reg(iRegI dst, iRegI src1, iRegI src2)
 4184 %{
 4185   single_instruction;
 4186   fixed_latency(3); // Maximum latency for 64 bit mul
 4187   dst    : WR(write);
 4188   src1   : ID(read);
 4189   src2   : ID(read);
 4190   DECODE : ID;
 4191   MUL    : WR;
 4192 %}
 4193 
 4194 //------- Divide pipeline operations --------------------
 4195 
 4196 // E.g. DIVW   Rd, Rs1, Rs2
 4197 pipe_class idiv_reg_reg(iRegI dst, iRegI src1, iRegI src2)
 4198 %{
 4199   single_instruction;
 4200   fixed_latency(8); // Maximum latency for 32 bit divide
 4201   dst    : WR(write);
 4202   src1   : ID(read);
 4203   src2   : ID(read);
 4204   DECODE : ID;
 4205   DIV    : WR;
 4206 %}
 4207 
 4208 // E.g. DIV   RD, Rs1, Rs2
 4209 pipe_class ldiv_reg_reg(iRegI dst, iRegI src1, iRegI src2)
 4210 %{
 4211   single_instruction;
 4212   fixed_latency(16); // Maximum latency for 64 bit divide
 4213   dst    : WR(write);
 4214   src1   : ID(read);
 4215   src2   : ID(read);
 4216   DECODE : ID;
 4217   DIV    : WR;
 4218 %}
 4219 
 4220 //------- Load pipeline operations ------------------------
 4221 
 4222 // Load - reg, mem
 4223 // E.g. LA    Rd, mem
 4224 pipe_class iload_reg_mem(iRegI dst, memory mem)
 4225 %{
 4226   single_instruction;
 4227   dst    : WR(write);
 4228   mem    : ID(read);
 4229   DECODE : ID;
 4230   LDST   : MEM;
 4231 %}
 4232 
 4233 // Load - reg, reg
 4234 // E.g. LD    Rd, Rs
 4235 pipe_class iload_reg_reg(iRegI dst, iRegI src)
 4236 %{
 4237   single_instruction;
 4238   dst    : WR(write);
 4239   src    : ID(read);
 4240   DECODE : ID;
 4241   LDST   : MEM;
 4242 %}
 4243 
 4244 //------- Store pipeline operations -----------------------
 4245 
 4246 // Store - zr, mem
 4247 // E.g. SD    zr, mem
 4248 pipe_class istore_mem(memory mem)
 4249 %{
 4250   single_instruction;
 4251   mem    : ID(read);
 4252   DECODE : ID;
 4253   LDST   : MEM;
 4254 %}
 4255 
 4256 // Store - reg, mem
 4257 // E.g. SD    Rs, mem
 4258 pipe_class istore_reg_mem(iRegI src, memory mem)
 4259 %{
 4260   single_instruction;
 4261   mem    : ID(read);
 4262   src    : EX(read);
 4263   DECODE : ID;
 4264   LDST   : MEM;
 4265 %}
 4266 
 4267 // Store - reg, reg
 4268 // E.g. SD    Rs2, Rs1
 4269 pipe_class istore_reg_reg(iRegI dst, iRegI src)
 4270 %{
 4271   single_instruction;
 4272   dst    : ID(read);
 4273   src    : EX(read);
 4274   DECODE : ID;
 4275   LDST   : MEM;
 4276 %}
 4277 
 4278 //------- Store pipeline operations -----------------------
 4279 
 4280 // Branch
 4281 pipe_class pipe_branch()
 4282 %{
 4283   single_instruction;
 4284   DECODE : ID;
 4285   BRANCH : EX;
 4286 %}
 4287 
 4288 // Branch
 4289 pipe_class pipe_branch_reg(iRegI src)
 4290 %{
 4291   single_instruction;
 4292   src    : ID(read);
 4293   DECODE : ID;
 4294   BRANCH : EX;
 4295 %}
 4296 
 4297 // Compare & Branch
 4298 // E.g. BEQ   Rs1, Rs2, L
 4299 pipe_class pipe_cmp_branch(iRegI src1, iRegI src2)
 4300 %{
 4301   single_instruction;
 4302   src1   : ID(read);
 4303   src2   : ID(read);
 4304   DECODE : ID;
 4305   BRANCH : EX;
 4306 %}
 4307 
 4308 // E.g. BEQZ Rs, L
 4309 pipe_class pipe_cmpz_branch(iRegI src)
 4310 %{
 4311   single_instruction;
 4312   src    : ID(read);
 4313   DECODE : ID;
 4314   BRANCH : EX;
 4315 %}
 4316 
 4317 //------- Synchronisation operations ----------------------
 4318 // Any operation requiring serialization
 4319 // E.g. FENCE/Atomic Ops/Load Acquire/Store Release
 4320 pipe_class pipe_serial()
 4321 %{
 4322   single_instruction;
 4323   force_serialization;
 4324   fixed_latency(16);
 4325   DECODE : ID;
 4326   LDST   : MEM;
 4327 %}
 4328 
 4329 pipe_class pipe_slow()
 4330 %{
 4331   instruction_count(10);
 4332   multiple_bundles;
 4333   force_serialization;
 4334   fixed_latency(16);
 4335   DECODE : ID;
 4336   LDST   : MEM;
 4337 %}
 4338 
 4339 // Empty pipeline class
 4340 pipe_class pipe_class_empty()
 4341 %{
 4342   single_instruction;
 4343   fixed_latency(0);
 4344 %}
 4345 
 4346 // Default pipeline class.
 4347 pipe_class pipe_class_default()
 4348 %{
 4349   single_instruction;
 4350   fixed_latency(2);
 4351 %}
 4352 
 4353 // Pipeline class for compares.
 4354 pipe_class pipe_class_compare()
 4355 %{
 4356   single_instruction;
 4357   fixed_latency(16);
 4358 %}
 4359 
 4360 // Pipeline class for memory operations.
 4361 pipe_class pipe_class_memory()
 4362 %{
 4363   single_instruction;
 4364   fixed_latency(16);
 4365 %}
 4366 
 4367 // Pipeline class for call.
 4368 pipe_class pipe_class_call()
 4369 %{
 4370   single_instruction;
 4371   fixed_latency(100);
 4372 %}
 4373 
 4374 // Define the class for the Nop node.
 4375 define %{
 4376    MachNop = pipe_class_empty;
 4377 %}
 4378 %}
 4379 //----------INSTRUCTIONS-------------------------------------------------------
 4380 //
 4381 // match      -- States which machine-independent subtree may be replaced
 4382 //               by this instruction.
 4383 // ins_cost   -- The estimated cost of this instruction is used by instruction
 4384 //               selection to identify a minimum cost tree of machine
 4385 //               instructions that matches a tree of machine-independent
 4386 //               instructions.
 4387 // format     -- A string providing the disassembly for this instruction.
 4388 //               The value of an instruction's operand may be inserted
 4389 //               by referring to it with a '$' prefix.
 4390 // opcode     -- Three instruction opcodes may be provided.  These are referred
 4391 //               to within an encode class as $primary, $secondary, and $tertiary
 4392 //               rrspectively.  The primary opcode is commonly used to
 4393 //               indicate the type of machine instruction, while secondary
 4394 //               and tertiary are often used for prefix options or addressing
 4395 //               modes.
 4396 // ins_encode -- A list of encode classes with parameters. The encode class
 4397 //               name must have been defined in an 'enc_class' specification
 4398 //               in the encode section of the architecture description.
 4399 
 4400 // ============================================================================
 4401 // Memory (Load/Store) Instructions
 4402 
 4403 // Load Instructions
 4404 
 4405 // Load Byte (8 bit signed)
 4406 instruct loadB(iRegINoSp dst, memory mem)
 4407 %{
 4408   match(Set dst (LoadB mem));
 4409 
 4410   ins_cost(LOAD_COST);
 4411   format %{ "lb  $dst, $mem\t# byte, #@loadB" %}
 4412 
 4413   ins_encode %{
 4414     __ lb(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4415   %}
 4416 
 4417   ins_pipe(iload_reg_mem);
 4418 %}
 4419 
 4420 // Load Byte (8 bit signed) into long
 4421 instruct loadB2L(iRegLNoSp dst, memory mem)
 4422 %{
 4423   match(Set dst (ConvI2L (LoadB mem)));
 4424 
 4425   ins_cost(LOAD_COST);
 4426   format %{ "lb  $dst, $mem\t# byte, #@loadB2L" %}
 4427 
 4428   ins_encode %{
 4429     __ lb(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4430   %}
 4431 
 4432   ins_pipe(iload_reg_mem);
 4433 %}
 4434 
 4435 // Load Byte (8 bit unsigned)
 4436 instruct loadUB(iRegINoSp dst, memory mem)
 4437 %{
 4438   match(Set dst (LoadUB mem));
 4439 
 4440   ins_cost(LOAD_COST);
 4441   format %{ "lbu  $dst, $mem\t# byte, #@loadUB" %}
 4442 
 4443   ins_encode %{
 4444     __ lbu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4445   %}
 4446 
 4447   ins_pipe(iload_reg_mem);
 4448 %}
 4449 
 4450 // Load Byte (8 bit unsigned) into long
 4451 instruct loadUB2L(iRegLNoSp dst, memory mem)
 4452 %{
 4453   match(Set dst (ConvI2L (LoadUB mem)));
 4454 
 4455   ins_cost(LOAD_COST);
 4456   format %{ "lbu  $dst, $mem\t# byte, #@loadUB2L" %}
 4457 
 4458   ins_encode %{
 4459     __ lbu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4460   %}
 4461 
 4462   ins_pipe(iload_reg_mem);
 4463 %}
 4464 
 4465 // Load Short (16 bit signed)
 4466 instruct loadS(iRegINoSp dst, memory mem)
 4467 %{
 4468   match(Set dst (LoadS mem));
 4469 
 4470   ins_cost(LOAD_COST);
 4471   format %{ "lh  $dst, $mem\t# short, #@loadS" %}
 4472 
 4473   ins_encode %{
 4474     __ lh(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4475   %}
 4476 
 4477   ins_pipe(iload_reg_mem);
 4478 %}
 4479 
 4480 // Load Short (16 bit signed) into long
 4481 instruct loadS2L(iRegLNoSp dst, memory mem)
 4482 %{
 4483   match(Set dst (ConvI2L (LoadS mem)));
 4484 
 4485   ins_cost(LOAD_COST);
 4486   format %{ "lh  $dst, $mem\t# short, #@loadS2L" %}
 4487 
 4488   ins_encode %{
 4489     __ lh(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4490   %}
 4491 
 4492   ins_pipe(iload_reg_mem);
 4493 %}
 4494 
 4495 // Load Char (16 bit unsigned)
 4496 instruct loadUS(iRegINoSp dst, memory mem)
 4497 %{
 4498   match(Set dst (LoadUS mem));
 4499 
 4500   ins_cost(LOAD_COST);
 4501   format %{ "lhu  $dst, $mem\t# short, #@loadUS" %}
 4502 
 4503   ins_encode %{
 4504     __ lhu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4505   %}
 4506 
 4507   ins_pipe(iload_reg_mem);
 4508 %}
 4509 
 4510 // Load Short/Char (16 bit unsigned) into long
 4511 instruct loadUS2L(iRegLNoSp dst, memory mem)
 4512 %{
 4513   match(Set dst (ConvI2L (LoadUS mem)));
 4514 
 4515   ins_cost(LOAD_COST);
 4516   format %{ "lhu  $dst, $mem\t# short, #@loadUS2L" %}
 4517 
 4518   ins_encode %{
 4519     __ lhu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4520   %}
 4521 
 4522   ins_pipe(iload_reg_mem);
 4523 %}
 4524 
 4525 // Load Integer (32 bit signed)
 4526 instruct loadI(iRegINoSp dst, memory mem)
 4527 %{
 4528   match(Set dst (LoadI mem));
 4529 
 4530   ins_cost(LOAD_COST);
 4531   format %{ "lw  $dst, $mem\t# int, #@loadI" %}
 4532 
 4533   ins_encode %{
 4534     Assembler::CompressibleRegion cr(&_masm);
 4535     __ lw(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4536   %}
 4537 
 4538   ins_pipe(iload_reg_mem);
 4539 %}
 4540 
 4541 // Load Integer (32 bit signed) into long
 4542 instruct loadI2L(iRegLNoSp dst, memory mem)
 4543 %{
 4544   match(Set dst (ConvI2L (LoadI mem)));
 4545 
 4546   ins_cost(LOAD_COST);
 4547   format %{ "lw  $dst, $mem\t# int, #@loadI2L" %}
 4548 
 4549   ins_encode %{
 4550     Assembler::CompressibleRegion cr(&_masm);
 4551     __ lw(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4552   %}
 4553 
 4554   ins_pipe(iload_reg_mem);
 4555 %}
 4556 
 4557 // Load Integer (32 bit unsigned) into long
 4558 instruct loadUI2L(iRegLNoSp dst, memory mem, immL_32bits mask)
 4559 %{
 4560   match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
 4561 
 4562   ins_cost(LOAD_COST);
 4563   format %{ "lwu  $dst, $mem\t# int, #@loadUI2L" %}
 4564 
 4565   ins_encode %{
 4566     __ lwu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4567   %}
 4568 
 4569   ins_pipe(iload_reg_mem);
 4570 %}
 4571 
 4572 // Load Long (64 bit signed)
 4573 instruct loadL(iRegLNoSp dst, memory mem)
 4574 %{
 4575   match(Set dst (LoadL mem));
 4576 
 4577   ins_cost(LOAD_COST);
 4578   format %{ "ld  $dst, $mem\t# int, #@loadL" %}
 4579 
 4580   ins_encode %{
 4581     Assembler::CompressibleRegion cr(&_masm);
 4582     __ ld(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4583   %}
 4584 
 4585   ins_pipe(iload_reg_mem);
 4586 %}
 4587 
 4588 // Load Range
 4589 instruct loadRange(iRegINoSp dst, memory mem)
 4590 %{
 4591   match(Set dst (LoadRange mem));
 4592 
 4593   ins_cost(LOAD_COST);
 4594   format %{ "lwu  $dst, $mem\t# range, #@loadRange" %}
 4595 
 4596   ins_encode %{
 4597     __ lwu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4598   %}
 4599 
 4600   ins_pipe(iload_reg_mem);
 4601 %}
 4602 
 4603 // Load Pointer
 4604 instruct loadP(iRegPNoSp dst, memory mem)
 4605 %{
 4606   match(Set dst (LoadP mem));
 4607   predicate(n->as_Load()->barrier_data() == 0);
 4608 
 4609   ins_cost(LOAD_COST);
 4610   format %{ "ld  $dst, $mem\t# ptr, #@loadP" %}
 4611 
 4612   ins_encode %{
 4613     Assembler::CompressibleRegion cr(&_masm);
 4614     __ ld(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4615   %}
 4616 
 4617   ins_pipe(iload_reg_mem);
 4618 %}
 4619 
 4620 // Load Compressed Pointer
 4621 instruct loadN(iRegNNoSp dst, memory mem)
 4622 %{
 4623   match(Set dst (LoadN mem));
 4624 
 4625   ins_cost(LOAD_COST);
 4626   format %{ "lwu  $dst, $mem\t# loadN, compressed ptr, #@loadN" %}
 4627 
 4628   ins_encode %{
 4629     __ lwu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4630   %}
 4631 
 4632   ins_pipe(iload_reg_mem);
 4633 %}
 4634 
 4635 // Load Klass Pointer
 4636 instruct loadKlass(iRegPNoSp dst, memory mem)
 4637 %{
 4638   match(Set dst (LoadKlass mem));
 4639 
 4640   ins_cost(LOAD_COST);
 4641   format %{ "ld  $dst, $mem\t# class, #@loadKlass" %}
 4642 
 4643   ins_encode %{
 4644     Assembler::CompressibleRegion cr(&_masm);
 4645     __ ld(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4646   %}
 4647 
 4648   ins_pipe(iload_reg_mem);
 4649 %}
 4650 
 4651 // Load Narrow Klass Pointer
 4652 instruct loadNKlass(iRegNNoSp dst, memory mem)
 4653 %{
 4654   match(Set dst (LoadNKlass mem));
 4655 
 4656   ins_cost(LOAD_COST);
 4657   format %{ "lwu  $dst, $mem\t# loadNKlass, compressed class ptr, #@loadNKlass" %}
 4658 
 4659   ins_encode %{
 4660     __ lwu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4661   %}
 4662 
 4663   ins_pipe(iload_reg_mem);
 4664 %}
 4665 
 4666 // Load Float
 4667 instruct loadF(fRegF dst, memory mem)
 4668 %{
 4669   match(Set dst (LoadF mem));
 4670 
 4671   ins_cost(LOAD_COST);
 4672   format %{ "flw  $dst, $mem\t# float, #@loadF" %}
 4673 
 4674   ins_encode %{
 4675     __ flw(as_FloatRegister($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4676   %}
 4677 
 4678   ins_pipe(fp_load_mem_s);
 4679 %}
 4680 
 4681 // Load Double
 4682 instruct loadD(fRegD dst, memory mem)
 4683 %{
 4684   match(Set dst (LoadD mem));
 4685 
 4686   ins_cost(LOAD_COST);
 4687   format %{ "fld  $dst, $mem\t# double, #@loadD" %}
 4688 
 4689   ins_encode %{
 4690     Assembler::CompressibleRegion cr(&_masm);
 4691     __ fld(as_FloatRegister($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4692   %}
 4693 
 4694   ins_pipe(fp_load_mem_d);
 4695 %}
 4696 
 4697 // Load Int Constant
 4698 instruct loadConI(iRegINoSp dst, immI src)
 4699 %{
 4700   match(Set dst src);
 4701 
 4702   ins_cost(ALU_COST);
 4703   format %{ "li $dst, $src\t# int, #@loadConI" %}
 4704 
 4705   ins_encode(riscv_enc_li_imm(dst, src));
 4706 
 4707   ins_pipe(ialu_imm);
 4708 %}
 4709 
 4710 // Load Long Constant
 4711 instruct loadConL(iRegLNoSp dst, immL src)
 4712 %{
 4713   match(Set dst src);
 4714 
 4715   ins_cost(ALU_COST);
 4716   format %{ "li $dst, $src\t# long, #@loadConL" %}
 4717 
 4718   ins_encode(riscv_enc_li_imm(dst, src));
 4719 
 4720   ins_pipe(ialu_imm);
 4721 %}
 4722 
 4723 // Load Pointer Constant
 4724 instruct loadConP(iRegPNoSp dst, immP con)
 4725 %{
 4726   match(Set dst con);
 4727 
 4728   ins_cost(ALU_COST);
 4729   format %{ "mv  $dst, $con\t# ptr, #@loadConP" %}
 4730 
 4731   ins_encode(riscv_enc_mov_p(dst, con));
 4732 
 4733   ins_pipe(ialu_imm);
 4734 %}
 4735 
 4736 // Load Null Pointer Constant
 4737 instruct loadConP0(iRegPNoSp dst, immP0 con)
 4738 %{
 4739   match(Set dst con);
 4740 
 4741   ins_cost(ALU_COST);
 4742   format %{ "mv  $dst, $con\t# NULL ptr, #@loadConP0" %}
 4743 
 4744   ins_encode(riscv_enc_mov_zero(dst));
 4745 
 4746   ins_pipe(ialu_imm);
 4747 %}
 4748 
 4749 // Load Pointer Constant One
 4750 instruct loadConP1(iRegPNoSp dst, immP_1 con)
 4751 %{
 4752   match(Set dst con);
 4753 
 4754   ins_cost(ALU_COST);
 4755   format %{ "mv  $dst, $con\t# load ptr constant one, #@loadConP1" %}
 4756 
 4757   ins_encode(riscv_enc_mov_p1(dst));
 4758 
 4759   ins_pipe(ialu_imm);
 4760 %}
 4761 
 4762 // Load Byte Map Base Constant
 4763 instruct loadByteMapBase(iRegPNoSp dst, immByteMapBase con)
 4764 %{
 4765   match(Set dst con);
 4766   ins_cost(ALU_COST);
 4767   format %{ "mv  $dst, $con\t# Byte Map Base, #@loadByteMapBase" %}
 4768 
 4769   ins_encode(riscv_enc_mov_byte_map_base(dst));
 4770 
 4771   ins_pipe(ialu_imm);
 4772 %}
 4773 
 4774 // Load Narrow Pointer Constant
 4775 instruct loadConN(iRegNNoSp dst, immN con)
 4776 %{
 4777   match(Set dst con);
 4778 
 4779   ins_cost(ALU_COST * 4);
 4780   format %{ "mv  $dst, $con\t# compressed ptr, #@loadConN" %}
 4781 
 4782   ins_encode(riscv_enc_mov_n(dst, con));
 4783 
 4784   ins_pipe(ialu_imm);
 4785 %}
 4786 
 4787 // Load Narrow Null Pointer Constant
 4788 instruct loadConN0(iRegNNoSp dst, immN0 con)
 4789 %{
 4790   match(Set dst con);
 4791 
 4792   ins_cost(ALU_COST);
 4793   format %{ "mv  $dst, $con\t# compressed NULL ptr, #@loadConN0" %}
 4794 
 4795   ins_encode(riscv_enc_mov_zero(dst));
 4796 
 4797   ins_pipe(ialu_imm);
 4798 %}
 4799 
 4800 // Load Narrow Klass Constant
 4801 instruct loadConNKlass(iRegNNoSp dst, immNKlass con)
 4802 %{
 4803   match(Set dst con);
 4804 
 4805   ins_cost(ALU_COST * 6);
 4806   format %{ "mv  $dst, $con\t# compressed klass ptr, #@loadConNKlass" %}
 4807 
 4808   ins_encode(riscv_enc_mov_nk(dst, con));
 4809 
 4810   ins_pipe(ialu_imm);
 4811 %}
 4812 
 4813 // Load Float Constant
 4814 instruct loadConF(fRegF dst, immF con) %{
 4815   match(Set dst con);
 4816 
 4817   ins_cost(LOAD_COST);
 4818   format %{
 4819     "flw $dst, [$constantaddress]\t# load from constant table: float=$con, #@loadConF"
 4820   %}
 4821 
 4822   ins_encode %{
 4823     __ flw(as_FloatRegister($dst$$reg), $constantaddress($con));
 4824   %}
 4825 
 4826   ins_pipe(fp_load_constant_s);
 4827 %}
 4828 
 4829 instruct loadConF0(fRegF dst, immF0 con) %{
 4830   match(Set dst con);
 4831 
 4832   ins_cost(XFER_COST);
 4833 
 4834   format %{ "fmv.w.x $dst, zr\t# float, #@loadConF0" %}
 4835 
 4836   ins_encode %{
 4837     __ fmv_w_x(as_FloatRegister($dst$$reg), zr);
 4838   %}
 4839 
 4840   ins_pipe(fp_load_constant_s);
 4841 %}
 4842 
 4843 // Load Double Constant
 4844 instruct loadConD(fRegD dst, immD con) %{
 4845   match(Set dst con);
 4846 
 4847   ins_cost(LOAD_COST);
 4848   format %{
 4849     "fld $dst, [$constantaddress]\t# load from constant table: double=$con, #@loadConD"
 4850   %}
 4851 
 4852   ins_encode %{
 4853     __ fld(as_FloatRegister($dst$$reg), $constantaddress($con));
 4854   %}
 4855 
 4856   ins_pipe(fp_load_constant_d);
 4857 %}
 4858 
 4859 instruct loadConD0(fRegD dst, immD0 con) %{
 4860   match(Set dst con);
 4861 
 4862   ins_cost(XFER_COST);
 4863 
 4864   format %{ "fmv.d.x $dst, zr\t# double, #@loadConD0" %}
 4865 
 4866   ins_encode %{
 4867     __ fmv_d_x(as_FloatRegister($dst$$reg), zr);
 4868   %}
 4869 
 4870   ins_pipe(fp_load_constant_d);
 4871 %}
 4872 
 4873 // Store Instructions
 4874 // Store CMS card-mark Immediate
 4875 instruct storeimmCM0(immI0 zero, memory mem)
 4876 %{
 4877   match(Set mem (StoreCM mem zero));
 4878 
 4879   ins_cost(STORE_COST);
 4880   format %{ "storestore (elided)\n\t"
 4881             "sb zr, $mem\t# byte, #@storeimmCM0" %}
 4882 
 4883   ins_encode %{
 4884     __ sb(zr, Address(as_Register($mem$$base), $mem$$disp));
 4885   %}
 4886 
 4887   ins_pipe(istore_mem);
 4888 %}
 4889 
 4890 // Store CMS card-mark Immediate with intervening StoreStore
 4891 // needed when using CMS with no conditional card marking
 4892 instruct storeimmCM0_ordered(immI0 zero, memory mem)
 4893 %{
 4894   match(Set mem (StoreCM mem zero));
 4895 
 4896   ins_cost(ALU_COST + STORE_COST);
 4897   format %{ "membar(StoreStore)\n\t"
 4898             "sb zr, $mem\t# byte, #@storeimmCM0_ordered" %}
 4899 
 4900   ins_encode %{
 4901     __ membar(MacroAssembler::LoadStore | MacroAssembler::StoreStore);
 4902     __ sb(zr, Address(as_Register($mem$$base), $mem$$disp));
 4903   %}
 4904 
 4905   ins_pipe(istore_mem);
 4906 %}
 4907 
 4908 // Store Byte
 4909 instruct storeB(iRegIorL2I src, memory mem)
 4910 %{
 4911   match(Set mem (StoreB mem src));
 4912 
 4913   ins_cost(STORE_COST);
 4914   format %{ "sb  $src, $mem\t# byte, #@storeB" %}
 4915 
 4916   ins_encode %{
 4917     __ sb(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4918   %}
 4919 
 4920   ins_pipe(istore_reg_mem);
 4921 %}
 4922 
 4923 instruct storeimmB0(immI0 zero, memory mem)
 4924 %{
 4925   match(Set mem (StoreB mem zero));
 4926 
 4927   ins_cost(STORE_COST);
 4928   format %{ "sb zr, $mem\t# byte, #@storeimmB0" %}
 4929 
 4930   ins_encode %{
 4931     __ sb(zr, Address(as_Register($mem$$base), $mem$$disp));
 4932   %}
 4933 
 4934   ins_pipe(istore_mem);
 4935 %}
 4936 
 4937 // Store Char/Short
 4938 instruct storeC(iRegIorL2I src, memory mem)
 4939 %{
 4940   match(Set mem (StoreC mem src));
 4941 
 4942   ins_cost(STORE_COST);
 4943   format %{ "sh  $src, $mem\t# short, #@storeC" %}
 4944 
 4945   ins_encode %{
 4946     __ sh(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4947   %}
 4948 
 4949   ins_pipe(istore_reg_mem);
 4950 %}
 4951 
 4952 instruct storeimmC0(immI0 zero, memory mem)
 4953 %{
 4954   match(Set mem (StoreC mem zero));
 4955 
 4956   ins_cost(STORE_COST);
 4957   format %{ "sh  zr, $mem\t# short, #@storeimmC0" %}
 4958 
 4959   ins_encode %{
 4960     __ sh(zr, Address(as_Register($mem$$base), $mem$$disp));
 4961   %}
 4962 
 4963   ins_pipe(istore_mem);
 4964 %}
 4965 
 4966 // Store Integer
 4967 instruct storeI(iRegIorL2I src, memory mem)
 4968 %{
 4969   match(Set mem(StoreI mem src));
 4970 
 4971   ins_cost(STORE_COST);
 4972   format %{ "sw  $src, $mem\t# int, #@storeI" %}
 4973 
 4974   ins_encode %{
 4975     Assembler::CompressibleRegion cr(&_masm);
 4976     __ sw(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4977   %}
 4978 
 4979   ins_pipe(istore_reg_mem);
 4980 %}
 4981 
 4982 instruct storeimmI0(immI0 zero, memory mem)
 4983 %{
 4984   match(Set mem(StoreI mem zero));
 4985 
 4986   ins_cost(STORE_COST);
 4987   format %{ "sw  zr, $mem\t# int, #@storeimmI0" %}
 4988 
 4989   ins_encode %{
 4990     __ sw(zr, Address(as_Register($mem$$base), $mem$$disp));
 4991   %}
 4992 
 4993   ins_pipe(istore_mem);
 4994 %}
 4995 
 4996 // Store Long (64 bit signed)
 4997 instruct storeL(iRegL src, memory mem)
 4998 %{
 4999   match(Set mem (StoreL mem src));
 5000 
 5001   ins_cost(STORE_COST);
 5002   format %{ "sd  $src, $mem\t# long, #@storeL" %}
 5003 
 5004   ins_encode %{
 5005     Assembler::CompressibleRegion cr(&_masm);
 5006     __ sd(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
 5007   %}
 5008 
 5009   ins_pipe(istore_reg_mem);
 5010 %}
 5011 
 5012 // Store Long (64 bit signed)
 5013 instruct storeimmL0(immL0 zero, memory mem)
 5014 %{
 5015   match(Set mem (StoreL mem zero));
 5016 
 5017   ins_cost(STORE_COST);
 5018   format %{ "sd  zr, $mem\t# long, #@storeimmL0" %}
 5019 
 5020   ins_encode %{
 5021     __ sd(zr, Address(as_Register($mem$$base), $mem$$disp));
 5022   %}
 5023 
 5024   ins_pipe(istore_mem);
 5025 %}
 5026 
 5027 // Store Pointer
 5028 instruct storeP(iRegP src, memory mem)
 5029 %{
 5030   match(Set mem (StoreP mem src));
 5031 
 5032   ins_cost(STORE_COST);
 5033   format %{ "sd  $src, $mem\t# ptr, #@storeP" %}
 5034 
 5035   ins_encode %{
 5036     Assembler::CompressibleRegion cr(&_masm);
 5037     __ sd(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
 5038   %}
 5039 
 5040   ins_pipe(istore_reg_mem);
 5041 %}
 5042 
 5043 // Store Pointer
 5044 instruct storeimmP0(immP0 zero, memory mem)
 5045 %{
 5046   match(Set mem (StoreP mem zero));
 5047 
 5048   ins_cost(STORE_COST);
 5049   format %{ "sd zr, $mem\t# ptr, #@storeimmP0" %}
 5050 
 5051   ins_encode %{
 5052     __ sd(zr, Address(as_Register($mem$$base), $mem$$disp));
 5053   %}
 5054 
 5055   ins_pipe(istore_mem);
 5056 %}
 5057 
 5058 // Store Compressed Pointer
 5059 instruct storeN(iRegN src, memory mem)
 5060 %{
 5061   match(Set mem (StoreN mem src));
 5062 
 5063   ins_cost(STORE_COST);
 5064   format %{ "sw  $src, $mem\t# compressed ptr, #@storeN" %}
 5065 
 5066   ins_encode %{
 5067     Assembler::CompressibleRegion cr(&_masm);
 5068     __ sw(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
 5069   %}
 5070 
 5071   ins_pipe(istore_reg_mem);
 5072 %}
 5073 
 5074 instruct storeImmN0(iRegIHeapbase heapbase, immN0 zero, memory mem)
 5075 %{
 5076   match(Set mem (StoreN mem zero));
 5077 
 5078   ins_cost(STORE_COST);
 5079   format %{ "sw  rheapbase, $mem\t# compressed ptr (rheapbase==0), #@storeImmN0" %}
 5080 
 5081   ins_encode %{
 5082     __ sw(as_Register($heapbase$$reg), Address(as_Register($mem$$base), $mem$$disp));
 5083   %}
 5084 
 5085   ins_pipe(istore_reg_mem);
 5086 %}
 5087 
 5088 // Store Float
 5089 instruct storeF(fRegF src, memory mem)
 5090 %{
 5091   match(Set mem (StoreF mem src));
 5092 
 5093   ins_cost(STORE_COST);
 5094   format %{ "fsw  $src, $mem\t# float, #@storeF" %}
 5095 
 5096   ins_encode %{
 5097     __ fsw(as_FloatRegister($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
 5098   %}
 5099 
 5100   ins_pipe(fp_store_reg_s);
 5101 %}
 5102 
 5103 // Store Double
 5104 instruct storeD(fRegD src, memory mem)
 5105 %{
 5106   match(Set mem (StoreD mem src));
 5107 
 5108   ins_cost(STORE_COST);
 5109   format %{ "fsd  $src, $mem\t# double, #@storeD" %}
 5110 
 5111   ins_encode %{
 5112     Assembler::CompressibleRegion cr(&_masm);
 5113     __ fsd(as_FloatRegister($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
 5114   %}
 5115 
 5116   ins_pipe(fp_store_reg_d);
 5117 %}
 5118 
 5119 // Store Compressed Klass Pointer
 5120 instruct storeNKlass(iRegN src, memory mem)
 5121 %{
 5122   match(Set mem (StoreNKlass mem src));
 5123 
 5124   ins_cost(STORE_COST);
 5125   format %{ "sw  $src, $mem\t# compressed klass ptr, #@storeNKlass" %}
 5126 
 5127   ins_encode %{
 5128     Assembler::CompressibleRegion cr(&_masm);
 5129     __ sw(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
 5130   %}
 5131 
 5132   ins_pipe(istore_reg_mem);
 5133 %}
 5134 
 5135 // ============================================================================
 5136 // Atomic operation instructions
 5137 //
 5138 
 5139 // standard CompareAndSwapX when we are using barriers
 5140 // these have higher priority than the rules selected by a predicate
 5141 instruct compareAndSwapB(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
 5142                          iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
 5143 %{
 5144   match(Set res (CompareAndSwapB mem (Binary oldval newval)));
 5145 
 5146   ins_cost(LOAD_COST + STORE_COST + ALU_COST * 10 + BRANCH_COST * 4);
 5147 
 5148   effect(TEMP_DEF res, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3, KILL cr);
 5149 
 5150   format %{
 5151     "cmpxchg $mem, $oldval, $newval\t# (byte) if $mem == $oldval then $mem <-- $newval\n\t"
 5152     "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapB"
 5153   %}
 5154 
 5155   ins_encode %{
 5156     __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
 5157                             Assembler::relaxed /* acquire */, Assembler::rl /* release */, $res$$Register,
 5158                             true /* result as bool */, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
 5159   %}
 5160 
 5161   ins_pipe(pipe_slow);
 5162 %}
 5163 
 5164 instruct compareAndSwapS(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
 5165                          iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
 5166 %{
 5167   match(Set res (CompareAndSwapS mem (Binary oldval newval)));
 5168 
 5169   ins_cost(LOAD_COST + STORE_COST + ALU_COST * 11 + BRANCH_COST * 4);
 5170 
 5171   effect(TEMP_DEF res, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3, KILL cr);
 5172 
 5173   format %{
 5174     "cmpxchg $mem, $oldval, $newval\t# (short) if $mem == $oldval then $mem <-- $newval\n\t"
 5175     "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapS"
 5176   %}
 5177 
 5178   ins_encode %{
 5179     __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
 5180                             Assembler::relaxed /* acquire */, Assembler::rl /* release */, $res$$Register,
 5181                             true /* result as bool */, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
 5182   %}
 5183 
 5184   ins_pipe(pipe_slow);
 5185 %}
 5186 
 5187 instruct compareAndSwapI(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
 5188 %{
 5189   match(Set res (CompareAndSwapI mem (Binary oldval newval)));
 5190 
 5191   ins_cost(LOAD_COST + STORE_COST + ALU_COST * 6 + BRANCH_COST * 4);
 5192 
 5193   format %{
 5194     "cmpxchg $mem, $oldval, $newval\t# (int) if $mem == $oldval then $mem <-- $newval\n\t"
 5195     "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapI"
 5196   %}
 5197 
 5198   ins_encode(riscv_enc_cmpxchgw(res, mem, oldval, newval));
 5199 
 5200   ins_pipe(pipe_slow);
 5201 %}
 5202 
 5203 instruct compareAndSwapL(iRegINoSp res, indirect mem, iRegL oldval, iRegL newval)
 5204 %{
 5205   match(Set res (CompareAndSwapL mem (Binary oldval newval)));
 5206 
 5207   ins_cost(LOAD_COST + STORE_COST + ALU_COST * 6 + BRANCH_COST * 4);
 5208 
 5209   format %{
 5210     "cmpxchg $mem, $oldval, $newval\t# (long) if $mem == $oldval then $mem <-- $newval\n\t"
 5211     "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapL"
 5212   %}
 5213 
 5214   ins_encode(riscv_enc_cmpxchg(res, mem, oldval, newval));
 5215 
 5216   ins_pipe(pipe_slow);
 5217 %}
 5218 
 5219 instruct compareAndSwapP(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval)
 5220 %{
 5221   predicate(n->as_LoadStore()->barrier_data() == 0);
 5222 
 5223   match(Set res (CompareAndSwapP mem (Binary oldval newval)));
 5224 
 5225   ins_cost(LOAD_COST + STORE_COST + ALU_COST * 6 + BRANCH_COST * 4);
 5226 
 5227   format %{
 5228     "cmpxchg $mem, $oldval, $newval\t# (ptr) if $mem == $oldval then $mem <-- $newval\n\t"
 5229     "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapP"
 5230   %}
 5231 
 5232   ins_encode(riscv_enc_cmpxchg(res, mem, oldval, newval));
 5233 
 5234   ins_pipe(pipe_slow);
 5235 %}
 5236 
 5237 instruct compareAndSwapN(iRegINoSp res, indirect mem, iRegN oldval, iRegN newval)
 5238 %{
 5239   match(Set res (CompareAndSwapN mem (Binary oldval newval)));
 5240 
 5241   ins_cost(LOAD_COST + STORE_COST + ALU_COST * 8 + BRANCH_COST * 4);
 5242 
 5243   format %{
 5244     "cmpxchg $mem, $oldval, $newval\t# (narrow oop) if $mem == $oldval then $mem <-- $newval\n\t"
 5245     "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapN"
 5246   %}
 5247 
 5248   ins_encode(riscv_enc_cmpxchgn(res, mem, oldval, newval));
 5249 
 5250   ins_pipe(pipe_slow);
 5251 %}
 5252 
 5253 // alternative CompareAndSwapX when we are eliding barriers
 5254 instruct compareAndSwapBAcq(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
 5255                             iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
 5256 %{
 5257   predicate(needs_acquiring_load_reserved(n));
 5258 
 5259   match(Set res (CompareAndSwapB mem (Binary oldval newval)));
 5260 
 5261   ins_cost(LOAD_COST + STORE_COST + ALU_COST * 10 + BRANCH_COST * 4);
 5262 
 5263   effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
 5264 
 5265   format %{
 5266     "cmpxchg_acq $mem, $oldval, $newval\t# (byte) if $mem == $oldval then $mem <-- $newval\n\t"
 5267     "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapBAcq"
 5268   %}
 5269 
 5270   ins_encode %{
 5271     __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
 5272                             Assembler::aq /* acquire */, Assembler::rl /* release */, $res$$Register,
 5273                             true /* result as bool */, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
 5274   %}
 5275 
 5276   ins_pipe(pipe_slow);
 5277 %}
 5278 
 5279 instruct compareAndSwapSAcq(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
 5280                             iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
 5281 %{
 5282   predicate(needs_acquiring_load_reserved(n));
 5283 
 5284   match(Set res (CompareAndSwapS mem (Binary oldval newval)));
 5285 
 5286   ins_cost(LOAD_COST + STORE_COST + ALU_COST * 11 + BRANCH_COST * 4);
 5287 
 5288   effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
 5289 
 5290   format %{
 5291     "cmpxchg_acq $mem, $oldval, $newval\t# (short) if $mem == $oldval then $mem <-- $newval\n\t"
 5292     "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapSAcq"
 5293   %}
 5294 
 5295   ins_encode %{
 5296     __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
 5297                             Assembler::aq /* acquire */, Assembler::rl /* release */, $res$$Register,
 5298                             true /* result as bool */, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
 5299   %}
 5300 
 5301   ins_pipe(pipe_slow);
 5302 %}
 5303 
 5304 instruct compareAndSwapIAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
 5305 %{
 5306   predicate(needs_acquiring_load_reserved(n));
 5307 
 5308   match(Set res (CompareAndSwapI mem (Binary oldval newval)));
 5309 
 5310   ins_cost(LOAD_COST + STORE_COST + ALU_COST * 6 + BRANCH_COST * 4);
 5311 
 5312   format %{
 5313     "cmpxchg_acq $mem, $oldval, $newval\t# (int) if $mem == $oldval then $mem <-- $newval\n\t"
 5314     "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapIAcq"
 5315   %}
 5316 
 5317   ins_encode(riscv_enc_cmpxchgw_acq(res, mem, oldval, newval));
 5318 
 5319   ins_pipe(pipe_slow);
 5320 %}
 5321 
 5322 instruct compareAndSwapLAcq(iRegINoSp res, indirect mem, iRegL oldval, iRegL newval)
 5323 %{
 5324   predicate(needs_acquiring_load_reserved(n));
 5325 
 5326   match(Set res (CompareAndSwapL mem (Binary oldval newval)));
 5327 
 5328   ins_cost(LOAD_COST + STORE_COST + ALU_COST * 6 + BRANCH_COST * 4);
 5329 
 5330   format %{
 5331     "cmpxchg_acq $mem, $oldval, $newval\t# (long) if $mem == $oldval then $mem <-- $newval\n\t"
 5332     "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapLAcq"
 5333   %}
 5334 
 5335   ins_encode(riscv_enc_cmpxchg_acq(res, mem, oldval, newval));
 5336 
 5337   ins_pipe(pipe_slow);
 5338 %}
 5339 
 5340 instruct compareAndSwapPAcq(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval)
 5341 %{
 5342   predicate(needs_acquiring_load_reserved(n) && (n->as_LoadStore()->barrier_data() == 0));
 5343 
 5344   match(Set res (CompareAndSwapP mem (Binary oldval newval)));
 5345 
 5346   ins_cost(LOAD_COST + STORE_COST + ALU_COST * 6 + BRANCH_COST * 4);
 5347 
 5348   format %{
 5349     "cmpxchg_acq $mem, $oldval, $newval\t# (ptr) if $mem == $oldval then $mem <-- $newval\n\t"
 5350     "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapPAcq"
 5351   %}
 5352 
 5353   ins_encode(riscv_enc_cmpxchg_acq(res, mem, oldval, newval));
 5354 
 5355   ins_pipe(pipe_slow);
 5356 %}
 5357 
 5358 instruct compareAndSwapNAcq(iRegINoSp res, indirect mem, iRegN oldval, iRegN newval)
 5359 %{
 5360   predicate(needs_acquiring_load_reserved(n));
 5361 
 5362   match(Set res (CompareAndSwapN mem (Binary oldval newval)));
 5363 
 5364   ins_cost(LOAD_COST + STORE_COST + ALU_COST * 8 + BRANCH_COST * 4);
 5365 
 5366   format %{
 5367     "cmpxchg_acq $mem, $oldval, $newval\t# (narrow oop) if $mem == $oldval then $mem <-- $newval\n\t"
 5368     "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapNAcq"
 5369   %}
 5370 
 5371   ins_encode(riscv_enc_cmpxchgn_acq(res, mem, oldval, newval));
 5372 
 5373   ins_pipe(pipe_slow);
 5374 %}
 5375 
 5376 // Sundry CAS operations.  Note that release is always true,
 5377 // regardless of the memory ordering of the CAS.  This is because we
 5378 // need the volatile case to be sequentially consistent but there is
 5379 // no trailing StoreLoad barrier emitted by C2.  Unfortunately we
 5380 // can't check the type of memory ordering here, so we always emit a
 5381 // sc_d(w) with rl bit set.
 5382 instruct compareAndExchangeB(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
 5383                              iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
 5384 %{
 5385   match(Set res (CompareAndExchangeB mem (Binary oldval newval)));
 5386 
 5387   ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST * 5);
 5388 
 5389   effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
 5390 
 5391   format %{
 5392     "cmpxchg $res = $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeB"
 5393   %}
 5394 
 5395   ins_encode %{
 5396     __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
 5397                             /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
 5398                             /*result_as_bool*/ false, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
 5399   %}
 5400 
 5401   ins_pipe(pipe_slow);
 5402 %}
 5403 
 5404 instruct compareAndExchangeS(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
 5405                              iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
 5406 %{
 5407   match(Set res (CompareAndExchangeS mem (Binary oldval newval)));
 5408 
 5409   ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST * 6);
 5410 
 5411   effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
 5412 
 5413   format %{
 5414     "cmpxchg $res = $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeS"
 5415   %}
 5416 
 5417   ins_encode %{
 5418     __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
 5419                             /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
 5420                             /*result_as_bool*/ false, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
 5421   %}
 5422 
 5423   ins_pipe(pipe_slow);
 5424 %}
 5425 
 5426 instruct compareAndExchangeI(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
 5427 %{
 5428   match(Set res (CompareAndExchangeI mem (Binary oldval newval)));
 5429 
 5430   ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST);
 5431 
 5432   effect(TEMP_DEF res);
 5433 
 5434   format %{
 5435     "cmpxchg $res = $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeI"
 5436   %}
 5437 
 5438   ins_encode %{
 5439     __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
 5440                /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
 5441   %}
 5442 
 5443   ins_pipe(pipe_slow);
 5444 %}
 5445 
 5446 instruct compareAndExchangeL(iRegLNoSp res, indirect mem, iRegL oldval, iRegL newval)
 5447 %{
 5448   match(Set res (CompareAndExchangeL mem (Binary oldval newval)));
 5449 
 5450   ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST);
 5451 
 5452   effect(TEMP_DEF res);
 5453 
 5454   format %{
 5455     "cmpxchg $res = $mem, $oldval, $newval\t# (long, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeL"
 5456   %}
 5457 
 5458   ins_encode %{
 5459     __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
 5460                /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
 5461   %}
 5462 
 5463   ins_pipe(pipe_slow);
 5464 %}
 5465 
 5466 instruct compareAndExchangeN(iRegNNoSp res, indirect mem, iRegN oldval, iRegN newval)
 5467 %{
 5468   match(Set res (CompareAndExchangeN mem (Binary oldval newval)));
 5469 
 5470   ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST * 3);
 5471 
 5472   effect(TEMP_DEF res);
 5473 
 5474   format %{
 5475     "cmpxchg $res = $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeN"
 5476   %}
 5477 
 5478   ins_encode %{
 5479     __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
 5480                /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
 5481   %}
 5482 
 5483   ins_pipe(pipe_slow);
 5484 %}
 5485 
 5486 instruct compareAndExchangeP(iRegPNoSp res, indirect mem, iRegP oldval, iRegP newval)
 5487 %{
 5488   predicate(n->as_LoadStore()->barrier_data() == 0);
 5489   match(Set res (CompareAndExchangeP mem (Binary oldval newval)));
 5490 
 5491   ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST);
 5492 
 5493   effect(TEMP_DEF res);
 5494 
 5495   format %{
 5496     "cmpxchg $res = $mem, $oldval, $newval\t# (ptr, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeP"
 5497   %}
 5498 
 5499   ins_encode %{
 5500     __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
 5501                /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
 5502   %}
 5503 
 5504   ins_pipe(pipe_slow);
 5505 %}
 5506 
 5507 instruct compareAndExchangeBAcq(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
 5508                                 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
 5509 %{
 5510   predicate(needs_acquiring_load_reserved(n));
 5511 
 5512   match(Set res (CompareAndExchangeB mem (Binary oldval newval)));
 5513 
 5514   ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST * 5);
 5515 
 5516   effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
 5517 
 5518   format %{
 5519     "cmpxchg_acq $res = $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeBAcq"
 5520   %}
 5521 
 5522   ins_encode %{
 5523     __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
 5524                             /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
 5525                             /*result_as_bool*/ false, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
 5526   %}
 5527 
 5528   ins_pipe(pipe_slow);
 5529 %}
 5530 
 5531 instruct compareAndExchangeSAcq(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
 5532                                 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
 5533 %{
 5534   predicate(needs_acquiring_load_reserved(n));
 5535 
 5536   match(Set res (CompareAndExchangeS mem (Binary oldval newval)));
 5537 
 5538   ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST * 6);
 5539 
 5540   effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
 5541 
 5542   format %{
 5543     "cmpxchg_acq $res = $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeSAcq"
 5544   %}
 5545 
 5546   ins_encode %{
 5547     __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
 5548                             /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
 5549                             /*result_as_bool*/ false, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
 5550   %}
 5551 
 5552   ins_pipe(pipe_slow);
 5553 %}
 5554 
 5555 instruct compareAndExchangeIAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
 5556 %{
 5557   predicate(needs_acquiring_load_reserved(n));
 5558 
 5559   match(Set res (CompareAndExchangeI mem (Binary oldval newval)));
 5560 
 5561   ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST);
 5562 
 5563   effect(TEMP_DEF res);
 5564 
 5565   format %{
 5566     "cmpxchg_acq $res = $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeIAcq"
 5567   %}
 5568 
 5569   ins_encode %{
 5570     __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
 5571                /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
 5572   %}
 5573 
 5574   ins_pipe(pipe_slow);
 5575 %}
 5576 
 5577 instruct compareAndExchangeLAcq(iRegLNoSp res, indirect mem, iRegL oldval, iRegL newval)
 5578 %{
 5579   predicate(needs_acquiring_load_reserved(n));
 5580 
 5581   match(Set res (CompareAndExchangeL mem (Binary oldval newval)));
 5582 
 5583   ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST);
 5584 
 5585   effect(TEMP_DEF res);
 5586 
 5587   format %{
 5588     "cmpxchg_acq $res = $mem, $oldval, $newval\t# (long, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeLAcq"
 5589   %}
 5590 
 5591   ins_encode %{
 5592     __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
 5593                /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
 5594   %}
 5595 
 5596   ins_pipe(pipe_slow);
 5597 %}
 5598 
 5599 instruct compareAndExchangeNAcq(iRegNNoSp res, indirect mem, iRegN oldval, iRegN newval)
 5600 %{
 5601   predicate(needs_acquiring_load_reserved(n));
 5602 
 5603   match(Set res (CompareAndExchangeN mem (Binary oldval newval)));
 5604 
 5605   ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST);
 5606 
 5607   effect(TEMP_DEF res);
 5608 
 5609   format %{
 5610     "cmpxchg_acq $res = $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeNAcq"
 5611   %}
 5612 
 5613   ins_encode %{
 5614     __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
 5615                /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
 5616   %}
 5617 
 5618   ins_pipe(pipe_slow);
 5619 %}
 5620 
 5621 instruct compareAndExchangePAcq(iRegPNoSp res, indirect mem, iRegP oldval, iRegP newval)
 5622 %{
 5623   predicate(needs_acquiring_load_reserved(n) && (n->as_LoadStore()->barrier_data() == 0));
 5624 
 5625   match(Set res (CompareAndExchangeP mem (Binary oldval newval)));
 5626 
 5627   ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST);
 5628 
 5629   effect(TEMP_DEF res);
 5630 
 5631   format %{
 5632     "cmpxchg_acq $res = $mem, $oldval, $newval\t# (ptr, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangePAcq"
 5633   %}
 5634 
 5635   ins_encode %{
 5636     __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
 5637                /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
 5638   %}
 5639 
 5640   ins_pipe(pipe_slow);
 5641 %}
 5642 
 5643 instruct weakCompareAndSwapB(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
 5644                              iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
 5645 %{
 5646   match(Set res (WeakCompareAndSwapB mem (Binary oldval newval)));
 5647 
 5648   ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 6);
 5649 
 5650   effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
 5651 
 5652   format %{
 5653     "cmpxchg_weak $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval\n\t"
 5654     "# $res == 1 when success, #@weakCompareAndSwapB"
 5655   %}
 5656 
 5657   ins_encode %{
 5658     __ weak_cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
 5659                                  /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
 5660                                  $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
 5661   %}
 5662 
 5663   ins_pipe(pipe_slow);
 5664 %}
 5665 
 5666 instruct weakCompareAndSwapS(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
 5667                              iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
 5668 %{
 5669   match(Set res (WeakCompareAndSwapS mem (Binary oldval newval)));
 5670 
 5671   ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 7);
 5672 
 5673   effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
 5674 
 5675   format %{
 5676     "cmpxchg_weak $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval\n\t"
 5677     "# $res == 1 when success, #@weakCompareAndSwapS"
 5678   %}
 5679 
 5680   ins_encode %{
 5681     __ weak_cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
 5682                                  /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
 5683                                  $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
 5684   %}
 5685 
 5686   ins_pipe(pipe_slow);
 5687 %}
 5688 
 5689 instruct weakCompareAndSwapI(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
 5690 %{
 5691   match(Set res (WeakCompareAndSwapI mem (Binary oldval newval)));
 5692 
 5693   ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 2);
 5694 
 5695   format %{
 5696     "cmpxchg_weak $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval\n\t"
 5697     "# $res == 1 when success, #@weakCompareAndSwapI"
 5698   %}
 5699 
 5700   ins_encode %{
 5701     __ cmpxchg_weak(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
 5702                     /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
 5703   %}
 5704 
 5705   ins_pipe(pipe_slow);
 5706 %}
 5707 
 5708 instruct weakCompareAndSwapL(iRegINoSp res, indirect mem, iRegL oldval, iRegL newval)
 5709 %{
 5710   match(Set res (WeakCompareAndSwapL mem (Binary oldval newval)));
 5711 
 5712   ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 2);
 5713 
 5714   format %{
 5715     "cmpxchg_weak $mem, $oldval, $newval\t# (long, weak) if $mem == $oldval then $mem <-- $newval\n\t"
 5716     "# $res == 1 when success, #@weakCompareAndSwapL"
 5717   %}
 5718 
 5719   ins_encode %{
 5720     __ cmpxchg_weak(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
 5721                     /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
 5722   %}
 5723 
 5724   ins_pipe(pipe_slow);
 5725 %}
 5726 
 5727 instruct weakCompareAndSwapN(iRegINoSp res, indirect mem, iRegN oldval, iRegN newval)
 5728 %{
 5729   match(Set res (WeakCompareAndSwapN mem (Binary oldval newval)));
 5730 
 5731   ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 4);
 5732 
 5733   format %{
 5734     "cmpxchg_weak $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval\n\t"
 5735     "# $res == 1 when success, #@weakCompareAndSwapN"
 5736   %}
 5737 
 5738   ins_encode %{
 5739     __ cmpxchg_weak(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
 5740                     /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
 5741   %}
 5742 
 5743   ins_pipe(pipe_slow);
 5744 %}
 5745 
 5746 instruct weakCompareAndSwapP(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval)
 5747 %{
 5748   predicate(n->as_LoadStore()->barrier_data() == 0);
 5749   match(Set res (WeakCompareAndSwapP mem (Binary oldval newval)));
 5750 
 5751   ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 2);
 5752 
 5753   format %{
 5754     "cmpxchg_weak $mem, $oldval, $newval\t# (ptr, weak) if $mem == $oldval then $mem <-- $newval\n\t"
 5755     "# $res == 1 when success, #@weakCompareAndSwapP"
 5756   %}
 5757 
 5758   ins_encode %{
 5759     __ cmpxchg_weak(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
 5760                     /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
 5761   %}
 5762 
 5763   ins_pipe(pipe_slow);
 5764 %}
 5765 
 5766 instruct weakCompareAndSwapBAcq(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
 5767                                 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
 5768 %{
 5769   predicate(needs_acquiring_load_reserved(n));
 5770 
 5771   match(Set res (WeakCompareAndSwapB mem (Binary oldval newval)));
 5772 
 5773   ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 6);
 5774 
 5775   effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
 5776 
 5777   format %{
 5778     "cmpxchg_weak_acq $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval\n\t"
 5779     "# $res == 1 when success, #@weakCompareAndSwapBAcq"
 5780   %}
 5781 
 5782   ins_encode %{
 5783     __ weak_cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
 5784                                  /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
 5785                                  $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
 5786   %}
 5787 
 5788   ins_pipe(pipe_slow);
 5789 %}
 5790 
 5791 instruct weakCompareAndSwapSAcq(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
 5792                                 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
 5793 %{
 5794   predicate(needs_acquiring_load_reserved(n));
 5795 
 5796   match(Set res (WeakCompareAndSwapS mem (Binary oldval newval)));
 5797 
 5798   ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 7);
 5799 
 5800   effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
 5801 
 5802   format %{
 5803     "cmpxchg_weak_acq $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval\n\t"
 5804     "# $res == 1 when success, #@weakCompareAndSwapSAcq"
 5805   %}
 5806 
 5807   ins_encode %{
 5808     __ weak_cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
 5809                                  /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
 5810                                  $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
 5811   %}
 5812 
 5813   ins_pipe(pipe_slow);
 5814 %}
 5815 
 5816 instruct weakCompareAndSwapIAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
 5817 %{
 5818   predicate(needs_acquiring_load_reserved(n));
 5819 
 5820   match(Set res (WeakCompareAndSwapI mem (Binary oldval newval)));
 5821 
 5822   ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 2);
 5823 
 5824   format %{
 5825     "cmpxchg_weak_acq $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval\n\t"
 5826     "# $res == 1 when success, #@weakCompareAndSwapIAcq"
 5827   %}
 5828 
 5829   ins_encode %{
 5830     __ cmpxchg_weak(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
 5831                     /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
 5832   %}
 5833 
 5834   ins_pipe(pipe_slow);
 5835 %}
 5836 
 5837 instruct weakCompareAndSwapLAcq(iRegINoSp res, indirect mem, iRegL oldval, iRegL newval)
 5838 %{
 5839   predicate(needs_acquiring_load_reserved(n));
 5840 
 5841   match(Set res (WeakCompareAndSwapL mem (Binary oldval newval)));
 5842 
 5843   ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 2);
 5844 
 5845   format %{
 5846     "cmpxchg_weak_acq $mem, $oldval, $newval\t# (long, weak) if $mem == $oldval then $mem <-- $newval\n\t"
 5847     "# $res == 1 when success, #@weakCompareAndSwapLAcq"
 5848   %}
 5849 
 5850   ins_encode %{
 5851     __ cmpxchg_weak(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
 5852                     /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
 5853   %}
 5854 
 5855   ins_pipe(pipe_slow);
 5856 %}
 5857 
 5858 instruct weakCompareAndSwapNAcq(iRegINoSp res, indirect mem, iRegN oldval, iRegN newval)
 5859 %{
 5860   predicate(needs_acquiring_load_reserved(n));
 5861 
 5862   match(Set res (WeakCompareAndSwapN mem (Binary oldval newval)));
 5863 
 5864   ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 4);
 5865 
 5866   format %{
 5867     "cmpxchg_weak_acq $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval\n\t"
 5868     "# $res == 1 when success, #@weakCompareAndSwapNAcq"
 5869   %}
 5870 
 5871   ins_encode %{
 5872     __ cmpxchg_weak(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
 5873                     /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
 5874   %}
 5875 
 5876   ins_pipe(pipe_slow);
 5877 %}
 5878 
 5879 instruct weakCompareAndSwapPAcq(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval)
 5880 %{
 5881   predicate(needs_acquiring_load_reserved(n) && (n->as_LoadStore()->barrier_data() == 0));
 5882 
 5883   match(Set res (WeakCompareAndSwapP mem (Binary oldval newval)));
 5884 
 5885   ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 2);
 5886 
 5887   format %{
 5888     "cmpxchg_weak_acq $mem, $oldval, $newval\t# (ptr, weak) if $mem == $oldval then $mem <-- $newval\n\t"
 5889     "\t# $res == 1 when success, #@weakCompareAndSwapPAcq"
 5890   %}
 5891 
 5892   ins_encode %{
 5893     __ cmpxchg_weak(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
 5894                     /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
 5895   %}
 5896 
 5897   ins_pipe(pipe_slow);
 5898 %}
 5899 
 5900 instruct get_and_setI(indirect mem, iRegI newv, iRegINoSp prev)
 5901 %{
 5902   match(Set prev (GetAndSetI mem newv));
 5903 
 5904   ins_cost(ALU_COST);
 5905 
 5906   format %{ "atomic_xchgw  $prev, $newv, [$mem]\t#@get_and_setI" %}
 5907 
 5908   ins_encode %{
 5909     __ atomic_xchgw($prev$$Register, $newv$$Register, as_Register($mem$$base));
 5910   %}
 5911 
 5912   ins_pipe(pipe_serial);
 5913 %}
 5914 
 5915 instruct get_and_setL(indirect mem, iRegL newv, iRegLNoSp prev)
 5916 %{
 5917   match(Set prev (GetAndSetL mem newv));
 5918 
 5919   ins_cost(ALU_COST);
 5920 
 5921   format %{ "atomic_xchg  $prev, $newv, [$mem]\t#@get_and_setL" %}
 5922 
 5923   ins_encode %{
 5924     __ atomic_xchg($prev$$Register, $newv$$Register, as_Register($mem$$base));
 5925   %}
 5926 
 5927   ins_pipe(pipe_serial);
 5928 %}
 5929 
 5930 instruct get_and_setN(indirect mem, iRegN newv, iRegINoSp prev)
 5931 %{
 5932   match(Set prev (GetAndSetN mem newv));
 5933 
 5934   ins_cost(ALU_COST);
 5935 
 5936   format %{ "atomic_xchgwu $prev, $newv, [$mem]\t#@get_and_setN" %}
 5937 
 5938   ins_encode %{
 5939     __ atomic_xchgwu($prev$$Register, $newv$$Register, as_Register($mem$$base));
 5940   %}
 5941 
 5942   ins_pipe(pipe_serial);
 5943 %}
 5944 
 5945 instruct get_and_setP(indirect mem, iRegP newv, iRegPNoSp prev)
 5946 %{
 5947   predicate(n->as_LoadStore()->barrier_data() == 0);
 5948   match(Set prev (GetAndSetP mem newv));
 5949 
 5950   ins_cost(ALU_COST);
 5951 
 5952   format %{ "atomic_xchg  $prev, $newv, [$mem]\t#@get_and_setP" %}
 5953 
 5954   ins_encode %{
 5955     __ atomic_xchg($prev$$Register, $newv$$Register, as_Register($mem$$base));
 5956   %}
 5957 
 5958   ins_pipe(pipe_serial);
 5959 %}
 5960 
 5961 instruct get_and_setIAcq(indirect mem, iRegI newv, iRegINoSp prev)
 5962 %{
 5963   predicate(needs_acquiring_load_reserved(n));
 5964 
 5965   match(Set prev (GetAndSetI mem newv));
 5966 
 5967   ins_cost(ALU_COST);
 5968 
 5969   format %{ "atomic_xchgw_acq  $prev, $newv, [$mem]\t#@get_and_setIAcq" %}
 5970 
 5971   ins_encode %{
 5972     __ atomic_xchgalw($prev$$Register, $newv$$Register, as_Register($mem$$base));
 5973   %}
 5974 
 5975   ins_pipe(pipe_serial);
 5976 %}
 5977 
 5978 instruct get_and_setLAcq(indirect mem, iRegL newv, iRegLNoSp prev)
 5979 %{
 5980   predicate(needs_acquiring_load_reserved(n));
 5981 
 5982   match(Set prev (GetAndSetL mem newv));
 5983 
 5984   ins_cost(ALU_COST);
 5985 
 5986   format %{ "atomic_xchg_acq  $prev, $newv, [$mem]\t#@get_and_setLAcq" %}
 5987 
 5988   ins_encode %{
 5989     __ atomic_xchgal($prev$$Register, $newv$$Register, as_Register($mem$$base));
 5990   %}
 5991 
 5992   ins_pipe(pipe_serial);
 5993 %}
 5994 
 5995 instruct get_and_setNAcq(indirect mem, iRegN newv, iRegINoSp prev)
 5996 %{
 5997   predicate(needs_acquiring_load_reserved(n));
 5998 
 5999   match(Set prev (GetAndSetN mem newv));
 6000 
 6001   ins_cost(ALU_COST);
 6002 
 6003   format %{ "atomic_xchgwu_acq $prev, $newv, [$mem]\t#@get_and_setNAcq" %}
 6004 
 6005   ins_encode %{
 6006     __ atomic_xchgalwu($prev$$Register, $newv$$Register, as_Register($mem$$base));
 6007   %}
 6008 
 6009   ins_pipe(pipe_serial);
 6010 %}
 6011 
 6012 instruct get_and_setPAcq(indirect mem, iRegP newv, iRegPNoSp prev)
 6013 %{
 6014   predicate(needs_acquiring_load_reserved(n) && (n->as_LoadStore()->barrier_data() == 0));
 6015 
 6016   match(Set prev (GetAndSetP mem newv));
 6017 
 6018   ins_cost(ALU_COST);
 6019 
 6020   format %{ "atomic_xchg_acq  $prev, $newv, [$mem]\t#@get_and_setPAcq" %}
 6021 
 6022   ins_encode %{
 6023     __ atomic_xchgal($prev$$Register, $newv$$Register, as_Register($mem$$base));
 6024   %}
 6025 
 6026   ins_pipe(pipe_serial);
 6027 %}
 6028 
 6029 instruct get_and_addL(indirect mem, iRegLNoSp newval, iRegL incr)
 6030 %{
 6031   match(Set newval (GetAndAddL mem incr));
 6032 
 6033   ins_cost(ALU_COST);
 6034 
 6035   format %{ "get_and_addL $newval, [$mem], $incr\t#@get_and_addL" %}
 6036 
 6037   ins_encode %{
 6038     __ atomic_add($newval$$Register, $incr$$Register, as_Register($mem$$base));
 6039   %}
 6040 
 6041   ins_pipe(pipe_serial);
 6042 %}
 6043 
 6044 instruct get_and_addL_no_res(indirect mem, Universe dummy, iRegL incr)
 6045 %{
 6046   predicate(n->as_LoadStore()->result_not_used());
 6047 
 6048   match(Set dummy (GetAndAddL mem incr));
 6049 
 6050   ins_cost(ALU_COST);
 6051 
 6052   format %{ "get_and_addL [$mem], $incr\t#@get_and_addL_no_res" %}
 6053 
 6054   ins_encode %{
 6055     __ atomic_add(noreg, $incr$$Register, as_Register($mem$$base));
 6056   %}
 6057 
 6058   ins_pipe(pipe_serial);
 6059 %}
 6060 
 6061 instruct get_and_addLi(indirect mem, iRegLNoSp newval, immLAdd incr)
 6062 %{
 6063   match(Set newval (GetAndAddL mem incr));
 6064 
 6065   ins_cost(ALU_COST);
 6066 
 6067   format %{ "get_and_addL $newval, [$mem], $incr\t#@get_and_addLi" %}
 6068 
 6069   ins_encode %{
 6070     __ atomic_add($newval$$Register, $incr$$constant, as_Register($mem$$base));
 6071   %}
 6072 
 6073   ins_pipe(pipe_serial);
 6074 %}
 6075 
 6076 instruct get_and_addLi_no_res(indirect mem, Universe dummy, immLAdd incr)
 6077 %{
 6078   predicate(n->as_LoadStore()->result_not_used());
 6079 
 6080   match(Set dummy (GetAndAddL mem incr));
 6081 
 6082   ins_cost(ALU_COST);
 6083 
 6084   format %{ "get_and_addL [$mem], $incr\t#@get_and_addLi_no_res" %}
 6085 
 6086   ins_encode %{
 6087     __ atomic_add(noreg, $incr$$constant, as_Register($mem$$base));
 6088   %}
 6089 
 6090   ins_pipe(pipe_serial);
 6091 %}
 6092 
 6093 instruct get_and_addI(indirect mem, iRegINoSp newval, iRegIorL2I incr)
 6094 %{
 6095   match(Set newval (GetAndAddI mem incr));
 6096 
 6097   ins_cost(ALU_COST);
 6098 
 6099   format %{ "get_and_addI $newval, [$mem], $incr\t#@get_and_addI" %}
 6100 
 6101   ins_encode %{
 6102     __ atomic_addw($newval$$Register, $incr$$Register, as_Register($mem$$base));
 6103   %}
 6104 
 6105   ins_pipe(pipe_serial);
 6106 %}
 6107 
 6108 instruct get_and_addI_no_res(indirect mem, Universe dummy, iRegIorL2I incr)
 6109 %{
 6110   predicate(n->as_LoadStore()->result_not_used());
 6111 
 6112   match(Set dummy (GetAndAddI mem incr));
 6113 
 6114   ins_cost(ALU_COST);
 6115 
 6116   format %{ "get_and_addI [$mem], $incr\t#@get_and_addI_no_res" %}
 6117 
 6118   ins_encode %{
 6119     __ atomic_addw(noreg, $incr$$Register, as_Register($mem$$base));
 6120   %}
 6121 
 6122   ins_pipe(pipe_serial);
 6123 %}
 6124 
 6125 instruct get_and_addIi(indirect mem, iRegINoSp newval, immIAdd incr)
 6126 %{
 6127   match(Set newval (GetAndAddI mem incr));
 6128 
 6129   ins_cost(ALU_COST);
 6130 
 6131   format %{ "get_and_addI $newval, [$mem], $incr\t#@get_and_addIi" %}
 6132 
 6133   ins_encode %{
 6134     __ atomic_addw($newval$$Register, $incr$$constant, as_Register($mem$$base));
 6135   %}
 6136 
 6137   ins_pipe(pipe_serial);
 6138 %}
 6139 
 6140 instruct get_and_addIi_no_res(indirect mem, Universe dummy, immIAdd incr)
 6141 %{
 6142   predicate(n->as_LoadStore()->result_not_used());
 6143 
 6144   match(Set dummy (GetAndAddI mem incr));
 6145 
 6146   ins_cost(ALU_COST);
 6147 
 6148   format %{ "get_and_addI [$mem], $incr\t#@get_and_addIi_no_res" %}
 6149 
 6150   ins_encode %{
 6151     __ atomic_addw(noreg, $incr$$constant, as_Register($mem$$base));
 6152   %}
 6153 
 6154   ins_pipe(pipe_serial);
 6155 %}
 6156 
 6157 instruct get_and_addLAcq(indirect mem, iRegLNoSp newval, iRegL incr)
 6158 %{
 6159   predicate(needs_acquiring_load_reserved(n));
 6160 
 6161   match(Set newval (GetAndAddL mem incr));
 6162 
 6163   ins_cost(ALU_COST);
 6164 
 6165   format %{ "get_and_addL_acq $newval, [$mem], $incr\t#@get_and_addLAcq" %}
 6166 
 6167   ins_encode %{
 6168     __ atomic_addal($newval$$Register, $incr$$Register, as_Register($mem$$base));
 6169   %}
 6170 
 6171   ins_pipe(pipe_serial);
 6172 %}
 6173 
 6174 instruct get_and_addL_no_resAcq(indirect mem, Universe dummy, iRegL incr) %{
 6175   predicate(n->as_LoadStore()->result_not_used() && needs_acquiring_load_reserved(n));
 6176 
 6177   match(Set dummy (GetAndAddL mem incr));
 6178 
 6179   ins_cost(ALU_COST);
 6180 
 6181   format %{ "get_and_addL_acq [$mem], $incr\t#@get_and_addL_no_resAcq" %}
 6182 
 6183   ins_encode %{
 6184     __ atomic_addal(noreg, $incr$$Register, as_Register($mem$$base));
 6185   %}
 6186 
 6187   ins_pipe(pipe_serial);
 6188 %}
 6189 
 6190 instruct get_and_addLiAcq(indirect mem, iRegLNoSp newval, immLAdd incr)
 6191 %{
 6192   predicate(needs_acquiring_load_reserved(n));
 6193 
 6194   match(Set newval (GetAndAddL mem incr));
 6195 
 6196   ins_cost(ALU_COST);
 6197 
 6198   format %{ "get_and_addL_acq $newval, [$mem], $incr\t#@get_and_addLiAcq" %}
 6199 
 6200   ins_encode %{
 6201     __ atomic_addal($newval$$Register, $incr$$constant, as_Register($mem$$base));
 6202   %}
 6203 
 6204   ins_pipe(pipe_serial);
 6205 %}
 6206 
 6207 instruct get_and_addLi_no_resAcq(indirect mem, Universe dummy, immLAdd incr)
 6208 %{
 6209   predicate(n->as_LoadStore()->result_not_used() && needs_acquiring_load_reserved(n));
 6210 
 6211   match(Set dummy (GetAndAddL mem incr));
 6212 
 6213   ins_cost(ALU_COST);
 6214 
 6215   format %{ "get_and_addL_acq [$mem], $incr\t#@get_and_addLi_no_resAcq" %}
 6216 
 6217   ins_encode %{
 6218     __ atomic_addal(noreg, $incr$$constant, as_Register($mem$$base));
 6219   %}
 6220 
 6221   ins_pipe(pipe_serial);
 6222 %}
 6223 
 6224 instruct get_and_addIAcq(indirect mem, iRegINoSp newval, iRegIorL2I incr)
 6225 %{
 6226   predicate(needs_acquiring_load_reserved(n));
 6227 
 6228   match(Set newval (GetAndAddI mem incr));
 6229 
 6230   ins_cost(ALU_COST);
 6231 
 6232   format %{ "get_and_addI_acq $newval, [$mem], $incr\t#@get_and_addIAcq" %}
 6233 
 6234   ins_encode %{
 6235     __ atomic_addalw($newval$$Register, $incr$$Register, as_Register($mem$$base));
 6236   %}
 6237 
 6238   ins_pipe(pipe_serial);
 6239 %}
 6240 
 6241 instruct get_and_addI_no_resAcq(indirect mem, Universe dummy, iRegIorL2I incr)
 6242 %{
 6243   predicate(n->as_LoadStore()->result_not_used() && needs_acquiring_load_reserved(n));
 6244 
 6245   match(Set dummy (GetAndAddI mem incr));
 6246 
 6247   ins_cost(ALU_COST);
 6248 
 6249   format %{ "get_and_addI_acq [$mem], $incr\t#@get_and_addI_no_resAcq" %}
 6250 
 6251   ins_encode %{
 6252     __ atomic_addalw(noreg, $incr$$Register, as_Register($mem$$base));
 6253   %}
 6254 
 6255   ins_pipe(pipe_serial);
 6256 %}
 6257 
 6258 instruct get_and_addIiAcq(indirect mem, iRegINoSp newval, immIAdd incr)
 6259 %{
 6260   predicate(needs_acquiring_load_reserved(n));
 6261 
 6262   match(Set newval (GetAndAddI mem incr));
 6263 
 6264   ins_cost(ALU_COST);
 6265 
 6266   format %{ "get_and_addI_acq $newval, [$mem], $incr\t#@get_and_addIiAcq" %}
 6267 
 6268   ins_encode %{
 6269     __ atomic_addalw($newval$$Register, $incr$$constant, as_Register($mem$$base));
 6270   %}
 6271 
 6272   ins_pipe(pipe_serial);
 6273 %}
 6274 
 6275 instruct get_and_addIi_no_resAcq(indirect mem, Universe dummy, immIAdd incr)
 6276 %{
 6277   predicate(n->as_LoadStore()->result_not_used() && needs_acquiring_load_reserved(n));
 6278 
 6279   match(Set dummy (GetAndAddI mem incr));
 6280 
 6281   ins_cost(ALU_COST);
 6282 
 6283   format %{ "get_and_addI_acq [$mem], $incr\t#@get_and_addIi_no_resAcq" %}
 6284 
 6285   ins_encode %{
 6286     __ atomic_addalw(noreg, $incr$$constant, as_Register($mem$$base));
 6287   %}
 6288 
 6289   ins_pipe(pipe_serial);
 6290 %}
 6291 
 6292 // ============================================================================
 6293 // Arithmetic Instructions
 6294 //
 6295 
 6296 // Integer Addition
 6297 
 6298 // TODO
 6299 // these currently employ operations which do not set CR and hence are
 6300 // not flagged as killing CR but we would like to isolate the cases
 6301 // where we want to set flags from those where we don't. need to work
 6302 // out how to do that.
 6303 instruct addI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
 6304   match(Set dst (AddI src1 src2));
 6305 
 6306   ins_cost(ALU_COST);
 6307   format %{ "addw  $dst, $src1, $src2\t#@addI_reg_reg" %}
 6308 
 6309   ins_encode %{
 6310     Assembler::CompressibleRegion cr(&_masm);
 6311     __ addw(as_Register($dst$$reg),
 6312             as_Register($src1$$reg),
 6313             as_Register($src2$$reg));
 6314   %}
 6315 
 6316   ins_pipe(ialu_reg_reg);
 6317 %}
 6318 
 6319 instruct addI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immIAdd src2) %{
 6320   match(Set dst (AddI src1 src2));
 6321 
 6322   ins_cost(ALU_COST);
 6323   format %{ "addiw  $dst, $src1, $src2\t#@addI_reg_imm" %}
 6324 
 6325   ins_encode %{
 6326     Assembler::CompressibleRegion cr(&_masm);
 6327     int32_t con = (int32_t)$src2$$constant;
 6328     __ addiw(as_Register($dst$$reg),
 6329              as_Register($src1$$reg),
 6330              $src2$$constant);
 6331   %}
 6332 
 6333   ins_pipe(ialu_reg_imm);
 6334 %}
 6335 
 6336 instruct addI_reg_imm_l2i(iRegINoSp dst, iRegL src1, immIAdd src2) %{
 6337   match(Set dst (AddI (ConvL2I src1) src2));
 6338 
 6339   ins_cost(ALU_COST);
 6340   format %{ "addiw  $dst, $src1, $src2\t#@addI_reg_imm_l2i" %}
 6341 
 6342   ins_encode %{
 6343     Assembler::CompressibleRegion cr(&_masm);
 6344     __ addiw(as_Register($dst$$reg),
 6345              as_Register($src1$$reg),
 6346              $src2$$constant);
 6347   %}
 6348 
 6349   ins_pipe(ialu_reg_imm);
 6350 %}
 6351 
 6352 // Pointer Addition
 6353 instruct addP_reg_reg(iRegPNoSp dst, iRegP src1, iRegL src2) %{
 6354   match(Set dst (AddP src1 src2));
 6355 
 6356   ins_cost(ALU_COST);
 6357   format %{ "add $dst, $src1, $src2\t# ptr, #@addP_reg_reg" %}
 6358 
 6359   ins_encode %{
 6360     Assembler::CompressibleRegion cr(&_masm);
 6361     __ add(as_Register($dst$$reg),
 6362            as_Register($src1$$reg),
 6363            as_Register($src2$$reg));
 6364   %}
 6365 
 6366   ins_pipe(ialu_reg_reg);
 6367 %}
 6368 
 6369 // If we shift more than 32 bits, we need not convert I2L.
 6370 instruct lShiftL_regI_immGE32(iRegLNoSp dst, iRegI src, uimmI6_ge32 scale) %{
 6371   match(Set dst (LShiftL (ConvI2L src) scale));
 6372   ins_cost(ALU_COST);
 6373   format %{ "slli  $dst, $src, $scale & 63\t#@lShiftL_regI_immGE32" %}
 6374 
 6375   ins_encode %{
 6376     Assembler::CompressibleRegion cr(&_masm);
 6377     __ slli(as_Register($dst$$reg), as_Register($src$$reg), $scale$$constant & 63);
 6378   %}
 6379 
 6380   ins_pipe(ialu_reg_shift);
 6381 %}
 6382 
 6383 // Pointer Immediate Addition
 6384 // n.b. this needs to be more expensive than using an indirect memory
 6385 // operand
 6386 instruct addP_reg_imm(iRegPNoSp dst, iRegP src1, immLAdd src2) %{
 6387   match(Set dst (AddP src1 src2));
 6388   ins_cost(ALU_COST);
 6389   format %{ "addi  $dst, $src1, $src2\t# ptr, #@addP_reg_imm" %}
 6390 
 6391   ins_encode %{
 6392     Assembler::CompressibleRegion cr(&_masm);
 6393     // src2 is imm, so actually call the addi
 6394     __ add(as_Register($dst$$reg),
 6395            as_Register($src1$$reg),
 6396            $src2$$constant);
 6397   %}
 6398 
 6399   ins_pipe(ialu_reg_imm);
 6400 %}
 6401 
 6402 // Long Addition
 6403 instruct addL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
 6404   match(Set dst (AddL src1 src2));
 6405   ins_cost(ALU_COST);
 6406   format %{ "add  $dst, $src1, $src2\t#@addL_reg_reg" %}
 6407 
 6408   ins_encode %{
 6409     Assembler::CompressibleRegion cr(&_masm);
 6410     __ add(as_Register($dst$$reg),
 6411            as_Register($src1$$reg),
 6412            as_Register($src2$$reg));
 6413   %}
 6414 
 6415   ins_pipe(ialu_reg_reg);
 6416 %}
 6417 
 6418 // No constant pool entries requiredLong Immediate Addition.
 6419 instruct addL_reg_imm(iRegLNoSp dst, iRegL src1, immLAdd src2) %{
 6420   match(Set dst (AddL src1 src2));
 6421   ins_cost(ALU_COST);
 6422   format %{ "addi  $dst, $src1, $src2\t#@addL_reg_imm" %}
 6423 
 6424   ins_encode %{
 6425     Assembler::CompressibleRegion cr(&_masm);
 6426     // src2 is imm, so actually call the addi
 6427     __ add(as_Register($dst$$reg),
 6428            as_Register($src1$$reg),
 6429            $src2$$constant);
 6430   %}
 6431 
 6432   ins_pipe(ialu_reg_imm);
 6433 %}
 6434 
 6435 // Integer Subtraction
 6436 instruct subI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
 6437   match(Set dst (SubI src1 src2));
 6438 
 6439   ins_cost(ALU_COST);
 6440   format %{ "subw  $dst, $src1, $src2\t#@subI_reg_reg" %}
 6441 
 6442   ins_encode %{
 6443     Assembler::CompressibleRegion cr(&_masm);
 6444     __ subw(as_Register($dst$$reg),
 6445             as_Register($src1$$reg),
 6446             as_Register($src2$$reg));
 6447   %}
 6448 
 6449   ins_pipe(ialu_reg_reg);
 6450 %}
 6451 
 6452 // Immediate Subtraction
 6453 instruct subI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immISub src2) %{
 6454   match(Set dst (SubI src1 src2));
 6455 
 6456   ins_cost(ALU_COST);
 6457   format %{ "addiw  $dst, $src1, -$src2\t#@subI_reg_imm" %}
 6458 
 6459   ins_encode %{
 6460     Assembler::CompressibleRegion cr(&_masm);
 6461     // src2 is imm, so actually call the addiw
 6462     __ subw(as_Register($dst$$reg),
 6463             as_Register($src1$$reg),
 6464             $src2$$constant);
 6465   %}
 6466 
 6467   ins_pipe(ialu_reg_imm);
 6468 %}
 6469 
 6470 // Long Subtraction
 6471 instruct subL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
 6472   match(Set dst (SubL src1 src2));
 6473   ins_cost(ALU_COST);
 6474   format %{ "sub  $dst, $src1, $src2\t#@subL_reg_reg" %}
 6475 
 6476   ins_encode %{
 6477     Assembler::CompressibleRegion cr(&_masm);
 6478     __ sub(as_Register($dst$$reg),
 6479            as_Register($src1$$reg),
 6480            as_Register($src2$$reg));
 6481   %}
 6482 
 6483   ins_pipe(ialu_reg_reg);
 6484 %}
 6485 
 6486 // No constant pool entries requiredLong Immediate Subtraction.
 6487 instruct subL_reg_imm(iRegLNoSp dst, iRegL src1, immLSub src2) %{
 6488   match(Set dst (SubL src1 src2));
 6489   ins_cost(ALU_COST);
 6490   format %{ "addi  $dst, $src1, -$src2\t#@subL_reg_imm" %}
 6491 
 6492   ins_encode %{
 6493     Assembler::CompressibleRegion cr(&_masm);
 6494     // src2 is imm, so actually call the addi
 6495     __ sub(as_Register($dst$$reg),
 6496            as_Register($src1$$reg),
 6497            $src2$$constant);
 6498   %}
 6499 
 6500   ins_pipe(ialu_reg_imm);
 6501 %}
 6502 
 6503 // Integer Negation (special case for sub)
 6504 
 6505 instruct negI_reg(iRegINoSp dst, iRegIorL2I src, immI0 zero) %{
 6506   match(Set dst (SubI zero src));
 6507   ins_cost(ALU_COST);
 6508   format %{ "subw  $dst, x0, $src\t# int, #@negI_reg" %}
 6509 
 6510   ins_encode %{
 6511     // actually call the subw
 6512     __ negw(as_Register($dst$$reg),
 6513             as_Register($src$$reg));
 6514   %}
 6515 
 6516   ins_pipe(ialu_reg);
 6517 %}
 6518 
 6519 // Long Negation
 6520 
 6521 instruct negL_reg(iRegLNoSp dst, iRegL src, immL0 zero) %{
 6522   match(Set dst (SubL zero src));
 6523   ins_cost(ALU_COST);
 6524   format %{ "sub  $dst, x0, $src\t# long, #@negL_reg" %}
 6525 
 6526   ins_encode %{
 6527     // actually call the sub
 6528     __ neg(as_Register($dst$$reg),
 6529            as_Register($src$$reg));
 6530   %}
 6531 
 6532   ins_pipe(ialu_reg);
 6533 %}
 6534 
 6535 // Integer Multiply
 6536 
 6537 instruct mulI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
 6538   match(Set dst (MulI src1 src2));
 6539   ins_cost(IMUL_COST);
 6540   format %{ "mulw  $dst, $src1, $src2\t#@mulI" %}
 6541 
 6542   //this means 2 word multi, and no sign extend to 64 bits
 6543   ins_encode %{
 6544     // riscv64 mulw will sign-extension to high 32 bits in dst reg
 6545     __ mulw(as_Register($dst$$reg),
 6546             as_Register($src1$$reg),
 6547             as_Register($src2$$reg));
 6548   %}
 6549 
 6550   ins_pipe(imul_reg_reg);
 6551 %}
 6552 
 6553 // Long Multiply
 6554 
 6555 instruct mulL(iRegLNoSp dst, iRegL src1, iRegL src2) %{
 6556   match(Set dst (MulL src1 src2));
 6557   ins_cost(IMUL_COST);
 6558   format %{ "mul  $dst, $src1, $src2\t#@mulL" %}
 6559 
 6560   ins_encode %{
 6561     __ mul(as_Register($dst$$reg),
 6562            as_Register($src1$$reg),
 6563            as_Register($src2$$reg));
 6564   %}
 6565 
 6566   ins_pipe(lmul_reg_reg);
 6567 %}
 6568 
 6569 instruct mulHiL_rReg(iRegLNoSp dst, iRegL src1, iRegL src2)
 6570 %{
 6571   match(Set dst (MulHiL src1 src2));
 6572   ins_cost(IMUL_COST);
 6573   format %{ "mulh  $dst, $src1, $src2\t# mulhi, #@mulHiL_rReg" %}
 6574 
 6575   ins_encode %{
 6576     __ mulh(as_Register($dst$$reg),
 6577             as_Register($src1$$reg),
 6578             as_Register($src2$$reg));
 6579   %}
 6580 
 6581   ins_pipe(lmul_reg_reg);
 6582 %}
 6583 
 6584 // Integer Divide
 6585 
 6586 instruct divI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
 6587   match(Set dst (DivI src1 src2));
 6588   ins_cost(IDIVSI_COST);
 6589   format %{ "divw  $dst, $src1, $src2\t#@divI"%}
 6590 
 6591   ins_encode(riscv_enc_divw(dst, src1, src2));
 6592   ins_pipe(idiv_reg_reg);
 6593 %}
 6594 
 6595 instruct signExtract(iRegINoSp dst, iRegIorL2I src1, immI_31 div1, immI_31 div2) %{
 6596   match(Set dst (URShiftI (RShiftI src1 div1) div2));
 6597   ins_cost(ALU_COST);
 6598   format %{ "srliw $dst, $src1, $div1\t# int signExtract, #@signExtract" %}
 6599 
 6600   ins_encode %{
 6601     __ srliw(as_Register($dst$$reg), as_Register($src1$$reg), 31);
 6602   %}
 6603   ins_pipe(ialu_reg_shift);
 6604 %}
 6605 
 6606 // Long Divide
 6607 
 6608 instruct divL(iRegLNoSp dst, iRegL src1, iRegL src2) %{
 6609   match(Set dst (DivL src1 src2));
 6610   ins_cost(IDIVDI_COST);
 6611   format %{ "div  $dst, $src1, $src2\t#@divL" %}
 6612 
 6613   ins_encode(riscv_enc_div(dst, src1, src2));
 6614   ins_pipe(ldiv_reg_reg);
 6615 %}
 6616 
 6617 instruct signExtractL(iRegLNoSp dst, iRegL src1, immI_63 div1, immI_63 div2) %{
 6618   match(Set dst (URShiftL (RShiftL src1 div1) div2));
 6619   ins_cost(ALU_COST);
 6620   format %{ "srli $dst, $src1, $div1\t# long signExtract, #@signExtractL" %}
 6621 
 6622   ins_encode %{
 6623     Assembler::CompressibleRegion cr(&_masm);
 6624     __ srli(as_Register($dst$$reg), as_Register($src1$$reg), 63);
 6625   %}
 6626   ins_pipe(ialu_reg_shift);
 6627 %}
 6628 
 6629 // Integer Remainder
 6630 
 6631 instruct modI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
 6632   match(Set dst (ModI src1 src2));
 6633   ins_cost(IDIVSI_COST);
 6634   format %{ "remw  $dst, $src1, $src2\t#@modI" %}
 6635 
 6636   ins_encode(riscv_enc_modw(dst, src1, src2));
 6637   ins_pipe(ialu_reg_reg);
 6638 %}
 6639 
 6640 // Long Remainder
 6641 
 6642 instruct modL(iRegLNoSp dst, iRegL src1, iRegL src2) %{
 6643   match(Set dst (ModL src1 src2));
 6644   ins_cost(IDIVDI_COST);
 6645   format %{ "rem  $dst, $src1, $src2\t#@modL" %}
 6646 
 6647   ins_encode(riscv_enc_mod(dst, src1, src2));
 6648   ins_pipe(ialu_reg_reg);
 6649 %}
 6650 
 6651 // Integer Shifts
 6652 
 6653 // Shift Left Register
 6654 // In RV64I, only the low 5 bits of src2 are considered for the shift amount
 6655 instruct lShiftI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
 6656   match(Set dst (LShiftI src1 src2));
 6657   ins_cost(ALU_COST);
 6658   format %{ "sllw  $dst, $src1, $src2\t#@lShiftI_reg_reg" %}
 6659 
 6660   ins_encode %{
 6661     __ sllw(as_Register($dst$$reg),
 6662             as_Register($src1$$reg),
 6663             as_Register($src2$$reg));
 6664   %}
 6665 
 6666   ins_pipe(ialu_reg_reg_vshift);
 6667 %}
 6668 
 6669 // Shift Left Immediate
 6670 instruct lShiftI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immI src2) %{
 6671   match(Set dst (LShiftI src1 src2));
 6672   ins_cost(ALU_COST);
 6673   format %{ "slliw  $dst, $src1, ($src2 & 0x1f)\t#@lShiftI_reg_imm" %}
 6674 
 6675   ins_encode %{
 6676     // the shift amount is encoded in the lower
 6677     // 5 bits of the I-immediate field for RV32I
 6678     __ slliw(as_Register($dst$$reg),
 6679              as_Register($src1$$reg),
 6680              (unsigned) $src2$$constant & 0x1f);
 6681   %}
 6682 
 6683   ins_pipe(ialu_reg_shift);
 6684 %}
 6685 
 6686 // Shift Right Logical Register
 6687 // In RV64I, only the low 5 bits of src2 are considered for the shift amount
 6688 instruct urShiftI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
 6689   match(Set dst (URShiftI src1 src2));
 6690   ins_cost(ALU_COST);
 6691   format %{ "srlw  $dst, $src1, $src2\t#@urShiftI_reg_reg" %}
 6692 
 6693   ins_encode %{
 6694     __ srlw(as_Register($dst$$reg),
 6695             as_Register($src1$$reg),
 6696             as_Register($src2$$reg));
 6697   %}
 6698 
 6699   ins_pipe(ialu_reg_reg_vshift);
 6700 %}
 6701 
 6702 // Shift Right Logical Immediate
 6703 instruct urShiftI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immI src2) %{
 6704   match(Set dst (URShiftI src1 src2));
 6705   ins_cost(ALU_COST);
 6706   format %{ "srliw  $dst, $src1, ($src2 & 0x1f)\t#@urShiftI_reg_imm" %}
 6707 
 6708   ins_encode %{
 6709     // the shift amount is encoded in the lower
 6710     // 6 bits of the I-immediate field for RV64I
 6711     __ srliw(as_Register($dst$$reg),
 6712              as_Register($src1$$reg),
 6713              (unsigned) $src2$$constant & 0x1f);
 6714   %}
 6715 
 6716   ins_pipe(ialu_reg_shift);
 6717 %}
 6718 
 6719 // Shift Right Arithmetic Register
 6720 // In RV64I, only the low 5 bits of src2 are considered for the shift amount
 6721 instruct rShiftI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
 6722   match(Set dst (RShiftI src1 src2));
 6723   ins_cost(ALU_COST);
 6724   format %{ "sraw  $dst, $src1, $src2\t#@rShiftI_reg_reg" %}
 6725 
 6726   ins_encode %{
 6727     // riscv will sign-ext dst high 32 bits
 6728     __ sraw(as_Register($dst$$reg),
 6729             as_Register($src1$$reg),
 6730             as_Register($src2$$reg));
 6731   %}
 6732 
 6733   ins_pipe(ialu_reg_reg_vshift);
 6734 %}
 6735 
 6736 // Shift Right Arithmetic Immediate
 6737 instruct rShiftI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immI src2) %{
 6738   match(Set dst (RShiftI src1 src2));
 6739   ins_cost(ALU_COST);
 6740   format %{ "sraiw  $dst, $src1, ($src2 & 0x1f)\t#@rShiftI_reg_imm" %}
 6741 
 6742   ins_encode %{
 6743     // riscv will sign-ext dst high 32 bits
 6744     __ sraiw(as_Register($dst$$reg),
 6745              as_Register($src1$$reg),
 6746              (unsigned) $src2$$constant & 0x1f);
 6747   %}
 6748 
 6749   ins_pipe(ialu_reg_shift);
 6750 %}
 6751 
 6752 // Long Shifts
 6753 
 6754 // Shift Left Register
 6755 // In RV64I, only the low 6 bits of src2 are considered for the shift amount
 6756 instruct lShiftL_reg_reg(iRegLNoSp dst, iRegL src1, iRegIorL2I src2) %{
 6757   match(Set dst (LShiftL src1 src2));
 6758 
 6759   ins_cost(ALU_COST);
 6760   format %{ "sll  $dst, $src1, $src2\t#@lShiftL_reg_reg" %}
 6761 
 6762   ins_encode %{
 6763     __ sll(as_Register($dst$$reg),
 6764            as_Register($src1$$reg),
 6765            as_Register($src2$$reg));
 6766   %}
 6767 
 6768   ins_pipe(ialu_reg_reg_vshift);
 6769 %}
 6770 
 6771 // Shift Left Immediate
 6772 instruct lShiftL_reg_imm(iRegLNoSp dst, iRegL src1, immI src2) %{
 6773   match(Set dst (LShiftL src1 src2));
 6774 
 6775   ins_cost(ALU_COST);
 6776   format %{ "slli  $dst, $src1, ($src2 & 0x3f)\t#@lShiftL_reg_imm" %}
 6777 
 6778   ins_encode %{
 6779     Assembler::CompressibleRegion cr(&_masm);
 6780     // the shift amount is encoded in the lower
 6781     // 6 bits of the I-immediate field for RV64I
 6782     __ slli(as_Register($dst$$reg),
 6783             as_Register($src1$$reg),
 6784             (unsigned) $src2$$constant & 0x3f);
 6785   %}
 6786 
 6787   ins_pipe(ialu_reg_shift);
 6788 %}
 6789 
 6790 // Shift Right Logical Register
 6791 // In RV64I, only the low 6 bits of src2 are considered for the shift amount
 6792 instruct urShiftL_reg_reg(iRegLNoSp dst, iRegL src1, iRegIorL2I src2) %{
 6793   match(Set dst (URShiftL src1 src2));
 6794 
 6795   ins_cost(ALU_COST);
 6796   format %{ "srl  $dst, $src1, $src2\t#@urShiftL_reg_reg" %}
 6797 
 6798   ins_encode %{
 6799     __ srl(as_Register($dst$$reg),
 6800             as_Register($src1$$reg),
 6801             as_Register($src2$$reg));
 6802   %}
 6803 
 6804   ins_pipe(ialu_reg_reg_vshift);
 6805 %}
 6806 
 6807 // Shift Right Logical Immediate
 6808 instruct urShiftL_reg_imm(iRegLNoSp dst, iRegL src1, immI src2) %{
 6809   match(Set dst (URShiftL src1 src2));
 6810 
 6811   ins_cost(ALU_COST);
 6812   format %{ "srli  $dst, $src1, ($src2 & 0x3f)\t#@urShiftL_reg_imm" %}
 6813 
 6814   ins_encode %{
 6815     Assembler::CompressibleRegion cr(&_masm);
 6816     // the shift amount is encoded in the lower
 6817     // 6 bits of the I-immediate field for RV64I
 6818     __ srli(as_Register($dst$$reg),
 6819             as_Register($src1$$reg),
 6820             (unsigned) $src2$$constant & 0x3f);
 6821   %}
 6822 
 6823   ins_pipe(ialu_reg_shift);
 6824 %}
 6825 
 6826 // A special-case pattern for card table stores.
 6827 instruct urShiftP_reg_imm(iRegLNoSp dst, iRegP src1, immI src2) %{
 6828   match(Set dst (URShiftL (CastP2X src1) src2));
 6829 
 6830   ins_cost(ALU_COST);
 6831   format %{ "srli  $dst, p2x($src1), ($src2 & 0x3f)\t#@urShiftP_reg_imm" %}
 6832 
 6833   ins_encode %{
 6834     Assembler::CompressibleRegion cr(&_masm);
 6835     // the shift amount is encoded in the lower
 6836     // 6 bits of the I-immediate field for RV64I
 6837     __ srli(as_Register($dst$$reg),
 6838             as_Register($src1$$reg),
 6839             (unsigned) $src2$$constant & 0x3f);
 6840   %}
 6841 
 6842   ins_pipe(ialu_reg_shift);
 6843 %}
 6844 
 6845 // Shift Right Arithmetic Register
 6846 // In RV64I, only the low 6 bits of src2 are considered for the shift amount
 6847 instruct rShiftL_reg_reg(iRegLNoSp dst, iRegL src1, iRegIorL2I src2) %{
 6848   match(Set dst (RShiftL src1 src2));
 6849 
 6850   ins_cost(ALU_COST);
 6851   format %{ "sra  $dst, $src1, $src2\t#@rShiftL_reg_reg" %}
 6852 
 6853   ins_encode %{
 6854     __ sra(as_Register($dst$$reg),
 6855            as_Register($src1$$reg),
 6856            as_Register($src2$$reg));
 6857   %}
 6858 
 6859   ins_pipe(ialu_reg_reg_vshift);
 6860 %}
 6861 
 6862 // Shift Right Arithmetic Immediate
 6863 instruct rShiftL_reg_imm(iRegLNoSp dst, iRegL src1, immI src2) %{
 6864   match(Set dst (RShiftL src1 src2));
 6865 
 6866   ins_cost(ALU_COST);
 6867   format %{ "srai  $dst, $src1, ($src2 & 0x3f)\t#@rShiftL_reg_imm" %}
 6868 
 6869   ins_encode %{
 6870     Assembler::CompressibleRegion cr(&_masm);
 6871     // the shift amount is encoded in the lower
 6872     // 6 bits of the I-immediate field for RV64I
 6873     __ srai(as_Register($dst$$reg),
 6874             as_Register($src1$$reg),
 6875             (unsigned) $src2$$constant & 0x3f);
 6876   %}
 6877 
 6878   ins_pipe(ialu_reg_shift);
 6879 %}
 6880 
 6881 instruct regI_not_reg(iRegINoSp dst, iRegI src1, immI_M1 m1) %{
 6882   match(Set dst (XorI src1 m1));
 6883   ins_cost(ALU_COST);
 6884   format %{ "xori  $dst, $src1, -1\t#@regI_not_reg" %}
 6885 
 6886   ins_encode %{
 6887     __ xori(as_Register($dst$$reg), as_Register($src1$$reg), -1);
 6888   %}
 6889 
 6890   ins_pipe(ialu_reg);
 6891 %}
 6892 
 6893 instruct regL_not_reg(iRegLNoSp dst, iRegL src1, immL_M1 m1) %{
 6894   match(Set dst (XorL src1 m1));
 6895   ins_cost(ALU_COST);
 6896   format %{ "xori  $dst, $src1, -1\t#@regL_not_reg" %}
 6897 
 6898   ins_encode %{
 6899     __ xori(as_Register($dst$$reg), as_Register($src1$$reg), -1);
 6900   %}
 6901 
 6902   ins_pipe(ialu_reg);
 6903 %}
 6904 
 6905 
 6906 // ============================================================================
 6907 // Floating Point Arithmetic Instructions
 6908 
 6909 instruct addF_reg_reg(fRegF dst, fRegF src1, fRegF src2) %{
 6910   match(Set dst (AddF src1 src2));
 6911 
 6912   ins_cost(FMUL_SINGLE_COST);
 6913   format %{ "fadd.s  $dst, $src1, $src2\t#@addF_reg_reg" %}
 6914 
 6915   ins_encode %{
 6916     __ fadd_s(as_FloatRegister($dst$$reg),
 6917               as_FloatRegister($src1$$reg),
 6918               as_FloatRegister($src2$$reg));
 6919   %}
 6920 
 6921   ins_pipe(fp_dop_reg_reg_s);
 6922 %}
 6923 
 6924 instruct addD_reg_reg(fRegD dst, fRegD src1, fRegD src2) %{
 6925   match(Set dst (AddD src1 src2));
 6926 
 6927   ins_cost(FMUL_DOUBLE_COST);
 6928   format %{ "fadd.d  $dst, $src1, $src2\t#@addD_reg_reg" %}
 6929 
 6930   ins_encode %{
 6931     __ fadd_d(as_FloatRegister($dst$$reg),
 6932               as_FloatRegister($src1$$reg),
 6933               as_FloatRegister($src2$$reg));
 6934   %}
 6935 
 6936   ins_pipe(fp_dop_reg_reg_d);
 6937 %}
 6938 
 6939 instruct subF_reg_reg(fRegF dst, fRegF src1, fRegF src2) %{
 6940   match(Set dst (SubF src1 src2));
 6941 
 6942   ins_cost(FMUL_SINGLE_COST);
 6943   format %{ "fsub.s  $dst, $src1, $src2\t#@subF_reg_reg" %}
 6944 
 6945   ins_encode %{
 6946     __ fsub_s(as_FloatRegister($dst$$reg),
 6947               as_FloatRegister($src1$$reg),
 6948               as_FloatRegister($src2$$reg));
 6949   %}
 6950 
 6951   ins_pipe(fp_dop_reg_reg_s);
 6952 %}
 6953 
 6954 instruct subD_reg_reg(fRegD dst, fRegD src1, fRegD src2) %{
 6955   match(Set dst (SubD src1 src2));
 6956 
 6957   ins_cost(FMUL_DOUBLE_COST);
 6958   format %{ "fsub.d  $dst, $src1, $src2\t#@subD_reg_reg" %}
 6959 
 6960   ins_encode %{
 6961     __ fsub_d(as_FloatRegister($dst$$reg),
 6962               as_FloatRegister($src1$$reg),
 6963               as_FloatRegister($src2$$reg));
 6964   %}
 6965 
 6966   ins_pipe(fp_dop_reg_reg_d);
 6967 %}
 6968 
 6969 instruct mulF_reg_reg(fRegF dst, fRegF src1, fRegF src2) %{
 6970   match(Set dst (MulF src1 src2));
 6971 
 6972   ins_cost(FMUL_SINGLE_COST);
 6973   format %{ "fmul.s  $dst, $src1, $src2\t#@mulF_reg_reg" %}
 6974 
 6975   ins_encode %{
 6976     __ fmul_s(as_FloatRegister($dst$$reg),
 6977               as_FloatRegister($src1$$reg),
 6978               as_FloatRegister($src2$$reg));
 6979   %}
 6980 
 6981   ins_pipe(fp_dop_reg_reg_s);
 6982 %}
 6983 
 6984 instruct mulD_reg_reg(fRegD dst, fRegD src1, fRegD src2) %{
 6985   match(Set dst (MulD src1 src2));
 6986 
 6987   ins_cost(FMUL_DOUBLE_COST);
 6988   format %{ "fmul.d  $dst, $src1, $src2\t#@mulD_reg_reg" %}
 6989 
 6990   ins_encode %{
 6991     __ fmul_d(as_FloatRegister($dst$$reg),
 6992               as_FloatRegister($src1$$reg),
 6993               as_FloatRegister($src2$$reg));
 6994   %}
 6995 
 6996   ins_pipe(fp_dop_reg_reg_d);
 6997 %}
 6998 
 6999 // src1 * src2 + src3
 7000 instruct maddF_reg_reg(fRegF dst, fRegF src1, fRegF src2, fRegF src3) %{
 7001   predicate(UseFMA);
 7002   match(Set dst (FmaF src3 (Binary src1 src2)));
 7003 
 7004   ins_cost(FMUL_SINGLE_COST);
 7005   format %{ "fmadd.s  $dst, $src1, $src2, $src3\t#@maddF_reg_reg" %}
 7006 
 7007   ins_encode %{
 7008     __ fmadd_s(as_FloatRegister($dst$$reg),
 7009                as_FloatRegister($src1$$reg),
 7010                as_FloatRegister($src2$$reg),
 7011                as_FloatRegister($src3$$reg));
 7012   %}
 7013 
 7014   ins_pipe(pipe_class_default);
 7015 %}
 7016 
 7017 // src1 * src2 + src3
 7018 instruct maddD_reg_reg(fRegD dst, fRegD src1, fRegD src2, fRegD src3) %{
 7019   predicate(UseFMA);
 7020   match(Set dst (FmaD src3 (Binary src1 src2)));
 7021 
 7022   ins_cost(FMUL_DOUBLE_COST);
 7023   format %{ "fmadd.d  $dst, $src1, $src2, $src3\t#@maddD_reg_reg" %}
 7024 
 7025   ins_encode %{
 7026     __ fmadd_d(as_FloatRegister($dst$$reg),
 7027                as_FloatRegister($src1$$reg),
 7028                as_FloatRegister($src2$$reg),
 7029                as_FloatRegister($src3$$reg));
 7030   %}
 7031 
 7032   ins_pipe(pipe_class_default);
 7033 %}
 7034 
 7035 // src1 * src2 - src3
 7036 instruct msubF_reg_reg(fRegF dst, fRegF src1, fRegF src2, fRegF src3) %{
 7037   predicate(UseFMA);
 7038   match(Set dst (FmaF (NegF src3) (Binary src1 src2)));
 7039 
 7040   ins_cost(FMUL_SINGLE_COST);
 7041   format %{ "fmsub.s  $dst, $src1, $src2, $src3\t#@msubF_reg_reg" %}
 7042 
 7043   ins_encode %{
 7044     __ fmsub_s(as_FloatRegister($dst$$reg),
 7045                as_FloatRegister($src1$$reg),
 7046                as_FloatRegister($src2$$reg),
 7047                as_FloatRegister($src3$$reg));
 7048   %}
 7049 
 7050   ins_pipe(pipe_class_default);
 7051 %}
 7052 
 7053 // src1 * src2 - src3
 7054 instruct msubD_reg_reg(fRegD dst, fRegD src1, fRegD src2, fRegD src3) %{
 7055   predicate(UseFMA);
 7056   match(Set dst (FmaD (NegD src3) (Binary src1 src2)));
 7057 
 7058   ins_cost(FMUL_DOUBLE_COST);
 7059   format %{ "fmsub.d  $dst, $src1, $src2, $src3\t#@msubD_reg_reg" %}
 7060 
 7061   ins_encode %{
 7062     __ fmsub_d(as_FloatRegister($dst$$reg),
 7063                as_FloatRegister($src1$$reg),
 7064                as_FloatRegister($src2$$reg),
 7065                as_FloatRegister($src3$$reg));
 7066   %}
 7067 
 7068   ins_pipe(pipe_class_default);
 7069 %}
 7070 
 7071 // -src1 * src2 + src3
 7072 instruct nmsubF_reg_reg(fRegF dst, fRegF src1, fRegF src2, fRegF src3) %{
 7073   predicate(UseFMA);
 7074   match(Set dst (FmaF src3 (Binary (NegF src1) src2)));
 7075   match(Set dst (FmaF src3 (Binary src1 (NegF src2))));
 7076 
 7077   ins_cost(FMUL_SINGLE_COST);
 7078   format %{ "fnmsub.s  $dst, $src1, $src2, $src3\t#@nmsubF_reg_reg" %}
 7079 
 7080   ins_encode %{
 7081     __ fnmsub_s(as_FloatRegister($dst$$reg),
 7082                 as_FloatRegister($src1$$reg),
 7083                 as_FloatRegister($src2$$reg),
 7084                 as_FloatRegister($src3$$reg));
 7085   %}
 7086 
 7087   ins_pipe(pipe_class_default);
 7088 %}
 7089 
 7090 // -src1 * src2 + src3
 7091 instruct nmsubD_reg_reg(fRegD dst, fRegD src1, fRegD src2, fRegD src3) %{
 7092   predicate(UseFMA);
 7093   match(Set dst (FmaD src3 (Binary (NegD src1) src2)));
 7094   match(Set dst (FmaD src3 (Binary src1 (NegD src2))));
 7095 
 7096   ins_cost(FMUL_DOUBLE_COST);
 7097   format %{ "fnmsub.d  $dst, $src1, $src2, $src3\t#@nmsubD_reg_reg" %}
 7098 
 7099   ins_encode %{
 7100     __ fnmsub_d(as_FloatRegister($dst$$reg),
 7101                 as_FloatRegister($src1$$reg),
 7102                 as_FloatRegister($src2$$reg),
 7103                 as_FloatRegister($src3$$reg));
 7104   %}
 7105 
 7106   ins_pipe(pipe_class_default);
 7107 %}
 7108 
 7109 // -src1 * src2 - src3
 7110 instruct nmaddF_reg_reg(fRegF dst, fRegF src1, fRegF src2, fRegF src3) %{
 7111   predicate(UseFMA);
 7112   match(Set dst (FmaF (NegF src3) (Binary (NegF src1) src2)));
 7113   match(Set dst (FmaF (NegF src3) (Binary src1 (NegF src2))));
 7114 
 7115   ins_cost(FMUL_SINGLE_COST);
 7116   format %{ "fnmadd.s  $dst, $src1, $src2, $src3\t#@nmaddF_reg_reg" %}
 7117 
 7118   ins_encode %{
 7119     __ fnmadd_s(as_FloatRegister($dst$$reg),
 7120                 as_FloatRegister($src1$$reg),
 7121                 as_FloatRegister($src2$$reg),
 7122                 as_FloatRegister($src3$$reg));
 7123   %}
 7124 
 7125   ins_pipe(pipe_class_default);
 7126 %}
 7127 
 7128 // -src1 * src2 - src3
 7129 instruct nmaddD_reg_reg(fRegD dst, fRegD src1, fRegD src2, fRegD src3) %{
 7130   predicate(UseFMA);
 7131   match(Set dst (FmaD (NegD src3) (Binary (NegD src1) src2)));
 7132   match(Set dst (FmaD (NegD src3) (Binary src1 (NegD src2))));
 7133 
 7134   ins_cost(FMUL_DOUBLE_COST);
 7135   format %{ "fnmadd.d  $dst, $src1, $src2, $src3\t#@nmaddD_reg_reg" %}
 7136 
 7137   ins_encode %{
 7138     __ fnmadd_d(as_FloatRegister($dst$$reg),
 7139                 as_FloatRegister($src1$$reg),
 7140                 as_FloatRegister($src2$$reg),
 7141                 as_FloatRegister($src3$$reg));
 7142   %}
 7143 
 7144   ins_pipe(pipe_class_default);
 7145 %}
 7146 
 7147 // Math.max(FF)F
 7148 instruct maxF_reg_reg(fRegF dst, fRegF src1, fRegF src2) %{
 7149   match(Set dst (MaxF src1 src2));
 7150   effect(TEMP_DEF dst);
 7151 
 7152   format %{ "maxF $dst, $src1, $src2" %}
 7153 
 7154   ins_encode %{
 7155     __ minmax_FD(as_FloatRegister($dst$$reg),
 7156                  as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg),
 7157                  false /* is_double */, false /* is_min */);
 7158   %}
 7159 
 7160   ins_pipe(fp_dop_reg_reg_s);
 7161 %}
 7162 
 7163 // Math.min(FF)F
 7164 instruct minF_reg_reg(fRegF dst, fRegF src1, fRegF src2) %{
 7165   match(Set dst (MinF src1 src2));
 7166   effect(TEMP_DEF dst);
 7167 
 7168   format %{ "minF $dst, $src1, $src2" %}
 7169 
 7170   ins_encode %{
 7171     __ minmax_FD(as_FloatRegister($dst$$reg),
 7172                  as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg),
 7173                  false /* is_double */, true /* is_min */);
 7174   %}
 7175 
 7176   ins_pipe(fp_dop_reg_reg_s);
 7177 %}
 7178 
 7179 // Math.max(DD)D
 7180 instruct maxD_reg_reg(fRegD dst, fRegD src1, fRegD src2) %{
 7181   match(Set dst (MaxD src1 src2));
 7182   effect(TEMP_DEF dst);
 7183 
 7184   format %{ "maxD $dst, $src1, $src2" %}
 7185 
 7186   ins_encode %{
 7187     __ minmax_FD(as_FloatRegister($dst$$reg),
 7188                  as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg),
 7189                  true /* is_double */, false /* is_min */);
 7190   %}
 7191 
 7192   ins_pipe(fp_dop_reg_reg_d);
 7193 %}
 7194 
 7195 // Math.min(DD)D
 7196 instruct minD_reg_reg(fRegD dst, fRegD src1, fRegD src2) %{
 7197   match(Set dst (MinD src1 src2));
 7198   effect(TEMP_DEF dst);
 7199 
 7200   format %{ "minD $dst, $src1, $src2" %}
 7201 
 7202   ins_encode %{
 7203     __ minmax_FD(as_FloatRegister($dst$$reg),
 7204                  as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg),
 7205                  true /* is_double */, true /* is_min */);
 7206   %}
 7207 
 7208   ins_pipe(fp_dop_reg_reg_d);
 7209 %}
 7210 
 7211 // Float.isInfinite
 7212 instruct isIniniteF_reg_reg(iRegINoSp dst, fRegF src)
 7213 %{
 7214   match(Set dst (IsInfiniteF src));
 7215   format %{ "isInfinite $dst, $src" %}
 7216   ins_encode %{
 7217     __ fclass_s(as_Register($dst$$reg), as_FloatRegister($src$$reg));
 7218     __ andi(as_Register($dst$$reg), as_Register($dst$$reg), 0b10000001);
 7219     __ slt(as_Register($dst$$reg), zr, as_Register($dst$$reg));
 7220   %}
 7221   ins_pipe(fp_dop_reg_reg_s);
 7222 %}
 7223 
 7224 // Double.isInfinite
 7225 instruct isInfiniteD_reg_reg(iRegINoSp dst, fRegD src)
 7226 %{
 7227   match(Set dst (IsInfiniteD src));
 7228   format %{ "isInfinite $dst, $src" %}
 7229   ins_encode %{
 7230     __ fclass_d(as_Register($dst$$reg), as_FloatRegister($src$$reg));
 7231     __ andi(as_Register($dst$$reg), as_Register($dst$$reg), 0b10000001);
 7232     __ slt(as_Register($dst$$reg), zr, as_Register($dst$$reg));
 7233   %}
 7234   ins_pipe(fp_dop_reg_reg_d);
 7235 %}
 7236 
 7237 instruct divF_reg_reg(fRegF dst, fRegF src1, fRegF src2) %{
 7238   match(Set dst (DivF src1  src2));
 7239 
 7240   ins_cost(FDIV_COST);
 7241   format %{ "fdiv.s  $dst, $src1, $src2\t#@divF_reg_reg" %}
 7242 
 7243   ins_encode %{
 7244     __ fdiv_s(as_FloatRegister($dst$$reg),
 7245               as_FloatRegister($src1$$reg),
 7246               as_FloatRegister($src2$$reg));
 7247   %}
 7248 
 7249   ins_pipe(fp_div_s);
 7250 %}
 7251 
 7252 instruct divD_reg_reg(fRegD dst, fRegD src1, fRegD src2) %{
 7253   match(Set dst (DivD src1  src2));
 7254 
 7255   ins_cost(FDIV_COST);
 7256   format %{ "fdiv.d  $dst, $src1, $src2\t#@divD_reg_reg" %}
 7257 
 7258   ins_encode %{
 7259     __ fdiv_d(as_FloatRegister($dst$$reg),
 7260               as_FloatRegister($src1$$reg),
 7261               as_FloatRegister($src2$$reg));
 7262   %}
 7263 
 7264   ins_pipe(fp_div_d);
 7265 %}
 7266 
 7267 instruct negF_reg_reg(fRegF dst, fRegF src) %{
 7268   match(Set dst (NegF src));
 7269 
 7270   ins_cost(XFER_COST);
 7271   format %{ "fsgnjn.s  $dst, $src, $src\t#@negF_reg_reg" %}
 7272 
 7273   ins_encode %{
 7274     __ fneg_s(as_FloatRegister($dst$$reg),
 7275               as_FloatRegister($src$$reg));
 7276   %}
 7277 
 7278   ins_pipe(fp_uop_s);
 7279 %}
 7280 
 7281 instruct negD_reg_reg(fRegD dst, fRegD src) %{
 7282   match(Set dst (NegD src));
 7283 
 7284   ins_cost(XFER_COST);
 7285   format %{ "fsgnjn.d  $dst, $src, $src\t#@negD_reg_reg" %}
 7286 
 7287   ins_encode %{
 7288     __ fneg_d(as_FloatRegister($dst$$reg),
 7289               as_FloatRegister($src$$reg));
 7290   %}
 7291 
 7292   ins_pipe(fp_uop_d);
 7293 %}
 7294 
 7295 instruct absI_reg(iRegINoSp dst, iRegIorL2I src) %{
 7296   match(Set dst (AbsI src));
 7297 
 7298   ins_cost(ALU_COST * 3);
 7299   format %{
 7300     "sraiw  t0, $src, 0x1f\n\t"
 7301     "addw  $dst, $src, t0\n\t"
 7302     "xorr  $dst, $dst, t0\t#@absI_reg"
 7303   %}
 7304 
 7305   ins_encode %{
 7306     __ sraiw(t0, as_Register($src$$reg), 0x1f);
 7307     __ addw(as_Register($dst$$reg), as_Register($src$$reg), t0);
 7308     __ xorr(as_Register($dst$$reg), as_Register($dst$$reg), t0);
 7309   %}
 7310 
 7311   ins_pipe(ialu_reg_reg);
 7312 %}
 7313 
 7314 instruct absL_reg(iRegLNoSp dst, iRegL src) %{
 7315   match(Set dst (AbsL src));
 7316 
 7317   ins_cost(ALU_COST * 3);
 7318   format %{
 7319     "srai  t0, $src, 0x3f\n\t"
 7320     "add  $dst, $src, t0\n\t"
 7321     "xorr  $dst, $dst, t0\t#@absL_reg"
 7322   %}
 7323 
 7324   ins_encode %{
 7325     __ srai(t0, as_Register($src$$reg), 0x3f);
 7326     __ add(as_Register($dst$$reg), as_Register($src$$reg), t0);
 7327     __ xorr(as_Register($dst$$reg), as_Register($dst$$reg), t0);
 7328   %}
 7329 
 7330   ins_pipe(ialu_reg_reg);
 7331 %}
 7332 
 7333 instruct absF_reg(fRegF dst, fRegF src) %{
 7334   match(Set dst (AbsF src));
 7335 
 7336   ins_cost(XFER_COST);
 7337   format %{ "fsgnjx.s  $dst, $src, $src\t#@absF_reg" %}
 7338   ins_encode %{
 7339     __ fabs_s(as_FloatRegister($dst$$reg),
 7340               as_FloatRegister($src$$reg));
 7341   %}
 7342 
 7343   ins_pipe(fp_uop_s);
 7344 %}
 7345 
 7346 instruct absD_reg(fRegD dst, fRegD src) %{
 7347   match(Set dst (AbsD src));
 7348 
 7349   ins_cost(XFER_COST);
 7350   format %{ "fsgnjx.d  $dst, $src, $src\t#@absD_reg" %}
 7351   ins_encode %{
 7352     __ fabs_d(as_FloatRegister($dst$$reg),
 7353               as_FloatRegister($src$$reg));
 7354   %}
 7355 
 7356   ins_pipe(fp_uop_d);
 7357 %}
 7358 
 7359 instruct sqrtF_reg(fRegF dst, fRegF src) %{
 7360   match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
 7361 
 7362   ins_cost(FSQRT_COST);
 7363   format %{ "fsqrt.s  $dst, $src\t#@sqrtF_reg" %}
 7364   ins_encode %{
 7365     __ fsqrt_s(as_FloatRegister($dst$$reg),
 7366                as_FloatRegister($src$$reg));
 7367   %}
 7368 
 7369   ins_pipe(fp_sqrt_s);
 7370 %}
 7371 
 7372 instruct sqrtD_reg(fRegD dst, fRegD src) %{
 7373   match(Set dst (SqrtD src));
 7374 
 7375   ins_cost(FSQRT_COST);
 7376   format %{ "fsqrt.d  $dst, $src\t#@sqrtD_reg" %}
 7377   ins_encode %{
 7378     __ fsqrt_d(as_FloatRegister($dst$$reg),
 7379                as_FloatRegister($src$$reg));
 7380   %}
 7381 
 7382   ins_pipe(fp_sqrt_d);
 7383 %}
 7384 
 7385 // Arithmetic Instructions End
 7386 
 7387 // ============================================================================
 7388 // Logical Instructions
 7389 
 7390 // Register And
 7391 instruct andI_reg_reg(iRegINoSp dst, iRegI src1, iRegI src2) %{
 7392   match(Set dst (AndI src1 src2));
 7393 
 7394   format %{ "andr  $dst, $src1, $src2\t#@andI_reg_reg" %}
 7395 
 7396   ins_cost(ALU_COST);
 7397   ins_encode %{
 7398     Assembler::CompressibleRegion cr(&_masm);
 7399     __ andr(as_Register($dst$$reg),
 7400             as_Register($src1$$reg),
 7401             as_Register($src2$$reg));
 7402   %}
 7403 
 7404   ins_pipe(ialu_reg_reg);
 7405 %}
 7406 
 7407 // Immediate And
 7408 instruct andI_reg_imm(iRegINoSp dst, iRegI src1, immIAdd src2) %{
 7409   match(Set dst (AndI src1 src2));
 7410 
 7411   format %{ "andi  $dst, $src1, $src2\t#@andI_reg_imm" %}
 7412 
 7413   ins_cost(ALU_COST);
 7414   ins_encode %{
 7415     Assembler::CompressibleRegion cr(&_masm);
 7416     __ andi(as_Register($dst$$reg),
 7417             as_Register($src1$$reg),
 7418             (int32_t)($src2$$constant));
 7419   %}
 7420 
 7421   ins_pipe(ialu_reg_imm);
 7422 %}
 7423 
 7424 // Register Or
 7425 instruct orI_reg_reg(iRegINoSp dst, iRegI src1, iRegI src2) %{
 7426   match(Set dst (OrI src1 src2));
 7427 
 7428   format %{ "orr  $dst, $src1, $src2\t#@orI_reg_reg" %}
 7429 
 7430   ins_cost(ALU_COST);
 7431   ins_encode %{
 7432     Assembler::CompressibleRegion cr(&_masm);
 7433     __ orr(as_Register($dst$$reg),
 7434            as_Register($src1$$reg),
 7435            as_Register($src2$$reg));
 7436   %}
 7437 
 7438   ins_pipe(ialu_reg_reg);
 7439 %}
 7440 
 7441 // Immediate Or
 7442 instruct orI_reg_imm(iRegINoSp dst, iRegI src1, immIAdd src2) %{
 7443   match(Set dst (OrI src1 src2));
 7444 
 7445   format %{ "ori  $dst, $src1, $src2\t#@orI_reg_imm" %}
 7446 
 7447   ins_cost(ALU_COST);
 7448   ins_encode %{
 7449     __ ori(as_Register($dst$$reg),
 7450            as_Register($src1$$reg),
 7451            (int32_t)($src2$$constant));
 7452   %}
 7453 
 7454   ins_pipe(ialu_reg_imm);
 7455 %}
 7456 
 7457 // Register Xor
 7458 instruct xorI_reg_reg(iRegINoSp dst, iRegI src1, iRegI src2) %{
 7459   match(Set dst (XorI src1 src2));
 7460 
 7461   format %{ "xorr  $dst, $src1, $src2\t#@xorI_reg_reg" %}
 7462 
 7463   ins_cost(ALU_COST);
 7464   ins_encode %{
 7465     Assembler::CompressibleRegion cr(&_masm);
 7466     __ xorr(as_Register($dst$$reg),
 7467             as_Register($src1$$reg),
 7468             as_Register($src2$$reg));
 7469   %}
 7470 
 7471   ins_pipe(ialu_reg_reg);
 7472 %}
 7473 
 7474 // Immediate Xor
 7475 instruct xorI_reg_imm(iRegINoSp dst, iRegI src1, immIAdd src2) %{
 7476   match(Set dst (XorI src1 src2));
 7477 
 7478   format %{ "xori  $dst, $src1, $src2\t#@xorI_reg_imm" %}
 7479 
 7480   ins_cost(ALU_COST);
 7481   ins_encode %{
 7482     __ xori(as_Register($dst$$reg),
 7483             as_Register($src1$$reg),
 7484             (int32_t)($src2$$constant));
 7485   %}
 7486 
 7487   ins_pipe(ialu_reg_imm);
 7488 %}
 7489 
 7490 // Register And Long
 7491 instruct andL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
 7492   match(Set dst (AndL src1 src2));
 7493 
 7494   format %{ "andr  $dst, $src1, $src2\t#@andL_reg_reg" %}
 7495 
 7496   ins_cost(ALU_COST);
 7497   ins_encode %{
 7498     Assembler::CompressibleRegion cr(&_masm);
 7499     __ andr(as_Register($dst$$reg),
 7500             as_Register($src1$$reg),
 7501             as_Register($src2$$reg));
 7502   %}
 7503 
 7504   ins_pipe(ialu_reg_reg);
 7505 %}
 7506 
 7507 // Immediate And Long
 7508 instruct andL_reg_imm(iRegLNoSp dst, iRegL src1, immLAdd src2) %{
 7509   match(Set dst (AndL src1 src2));
 7510 
 7511   format %{ "andi  $dst, $src1, $src2\t#@andL_reg_imm" %}
 7512 
 7513   ins_cost(ALU_COST);
 7514   ins_encode %{
 7515     Assembler::CompressibleRegion cr(&_masm);
 7516     __ andi(as_Register($dst$$reg),
 7517             as_Register($src1$$reg),
 7518             (int32_t)($src2$$constant));
 7519   %}
 7520 
 7521   ins_pipe(ialu_reg_imm);
 7522 %}
 7523 
 7524 // Register Or Long
 7525 instruct orL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
 7526   match(Set dst (OrL src1 src2));
 7527 
 7528   format %{ "orr  $dst, $src1, $src2\t#@orL_reg_reg" %}
 7529 
 7530   ins_cost(ALU_COST);
 7531   ins_encode %{
 7532     Assembler::CompressibleRegion cr(&_masm);
 7533     __ orr(as_Register($dst$$reg),
 7534            as_Register($src1$$reg),
 7535            as_Register($src2$$reg));
 7536   %}
 7537 
 7538   ins_pipe(ialu_reg_reg);
 7539 %}
 7540 
 7541 // Immediate Or Long
 7542 instruct orL_reg_imm(iRegLNoSp dst, iRegL src1, immLAdd src2) %{
 7543   match(Set dst (OrL src1 src2));
 7544 
 7545   format %{ "ori  $dst, $src1, $src2\t#@orL_reg_imm" %}
 7546 
 7547   ins_cost(ALU_COST);
 7548   ins_encode %{
 7549     __ ori(as_Register($dst$$reg),
 7550            as_Register($src1$$reg),
 7551            (int32_t)($src2$$constant));
 7552   %}
 7553 
 7554   ins_pipe(ialu_reg_imm);
 7555 %}
 7556 
 7557 // Register Xor Long
 7558 instruct xorL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
 7559   match(Set dst (XorL src1 src2));
 7560 
 7561   format %{ "xorr  $dst, $src1, $src2\t#@xorL_reg_reg" %}
 7562 
 7563   ins_cost(ALU_COST);
 7564   ins_encode %{
 7565     Assembler::CompressibleRegion cr(&_masm);
 7566     __ xorr(as_Register($dst$$reg),
 7567             as_Register($src1$$reg),
 7568             as_Register($src2$$reg));
 7569   %}
 7570 
 7571   ins_pipe(ialu_reg_reg);
 7572 %}
 7573 
 7574 // Immediate Xor Long
 7575 instruct xorL_reg_imm(iRegLNoSp dst, iRegL src1, immLAdd src2) %{
 7576   match(Set dst (XorL src1 src2));
 7577 
 7578   ins_cost(ALU_COST);
 7579   format %{ "xori  $dst, $src1, $src2\t#@xorL_reg_imm" %}
 7580 
 7581   ins_encode %{
 7582     __ xori(as_Register($dst$$reg),
 7583             as_Register($src1$$reg),
 7584             (int32_t)($src2$$constant));
 7585   %}
 7586 
 7587   ins_pipe(ialu_reg_imm);
 7588 %}
 7589 
 7590 // ============================================================================
 7591 // BSWAP Instructions
 7592 
 7593 instruct bytes_reverse_int(iRegINoSp dst, iRegIorL2I src, rFlagsReg cr) %{
 7594   match(Set dst (ReverseBytesI src));
 7595   effect(TEMP cr);
 7596 
 7597   ins_cost(ALU_COST * 13);
 7598   format %{ "revb_w_w  $dst, $src\t#@bytes_reverse_int" %}
 7599 
 7600   ins_encode %{
 7601     __ revb_w_w(as_Register($dst$$reg), as_Register($src$$reg));
 7602   %}
 7603 
 7604   ins_pipe(ialu_reg);
 7605 %}
 7606 
 7607 instruct bytes_reverse_long(iRegLNoSp dst, iRegL src, rFlagsReg cr) %{
 7608   match(Set dst (ReverseBytesL src));
 7609   effect(TEMP cr);
 7610 
 7611   ins_cost(ALU_COST * 29);
 7612   format %{ "revb  $dst, $src\t#@bytes_reverse_long" %}
 7613 
 7614   ins_encode %{
 7615     __ revb(as_Register($dst$$reg), as_Register($src$$reg));
 7616   %}
 7617 
 7618   ins_pipe(ialu_reg);
 7619 %}
 7620 
 7621 instruct bytes_reverse_unsigned_short(iRegINoSp dst, iRegIorL2I src) %{
 7622   match(Set dst (ReverseBytesUS src));
 7623 
 7624   ins_cost(ALU_COST * 5);
 7625   format %{ "revb_h_h_u  $dst, $src\t#@bytes_reverse_unsigned_short" %}
 7626 
 7627   ins_encode %{
 7628     __ revb_h_h_u(as_Register($dst$$reg), as_Register($src$$reg));
 7629   %}
 7630 
 7631   ins_pipe(ialu_reg);
 7632 %}
 7633 
 7634 instruct bytes_reverse_short(iRegINoSp dst, iRegIorL2I src) %{
 7635   match(Set dst (ReverseBytesS src));
 7636 
 7637   ins_cost(ALU_COST * 5);
 7638   format %{ "revb_h_h  $dst, $src\t#@bytes_reverse_short" %}
 7639 
 7640   ins_encode %{
 7641     __ revb_h_h(as_Register($dst$$reg), as_Register($src$$reg));
 7642   %}
 7643 
 7644   ins_pipe(ialu_reg);
 7645 %}
 7646 
 7647 // ============================================================================
 7648 // MemBar Instruction
 7649 
 7650 instruct load_fence() %{
 7651   match(LoadFence);
 7652   ins_cost(ALU_COST);
 7653 
 7654   format %{ "#@load_fence" %}
 7655 
 7656   ins_encode %{
 7657     __ membar(MacroAssembler::LoadLoad | MacroAssembler::LoadStore);
 7658   %}
 7659   ins_pipe(pipe_serial);
 7660 %}
 7661 
 7662 instruct membar_acquire() %{
 7663   match(MemBarAcquire);
 7664   ins_cost(ALU_COST);
 7665 
 7666   format %{ "#@membar_acquire\n\t"
 7667             "fence ir iorw" %}
 7668 
 7669   ins_encode %{
 7670     __ block_comment("membar_acquire");
 7671     __ membar(MacroAssembler::LoadLoad | MacroAssembler::LoadStore);
 7672   %}
 7673 
 7674   ins_pipe(pipe_serial);
 7675 %}
 7676 
 7677 instruct membar_acquire_lock() %{
 7678   match(MemBarAcquireLock);
 7679   ins_cost(0);
 7680 
 7681   format %{ "#@membar_acquire_lock (elided)" %}
 7682 
 7683   ins_encode %{
 7684     __ block_comment("membar_acquire_lock (elided)");
 7685   %}
 7686 
 7687   ins_pipe(pipe_serial);
 7688 %}
 7689 
 7690 instruct store_fence() %{
 7691   match(StoreFence);
 7692   ins_cost(ALU_COST);
 7693 
 7694   format %{ "#@store_fence" %}
 7695 
 7696   ins_encode %{
 7697     __ membar(MacroAssembler::LoadStore | MacroAssembler::StoreStore);
 7698   %}
 7699   ins_pipe(pipe_serial);
 7700 %}
 7701 
 7702 instruct membar_release() %{
 7703   match(MemBarRelease);
 7704   ins_cost(ALU_COST);
 7705 
 7706   format %{ "#@membar_release\n\t"
 7707             "fence iorw ow" %}
 7708 
 7709   ins_encode %{
 7710     __ block_comment("membar_release");
 7711     __ membar(MacroAssembler::LoadStore | MacroAssembler::StoreStore);
 7712   %}
 7713   ins_pipe(pipe_serial);
 7714 %}
 7715 
 7716 instruct membar_storestore() %{
 7717   match(MemBarStoreStore);
 7718   match(StoreStoreFence);
 7719   ins_cost(ALU_COST);
 7720 
 7721   format %{ "MEMBAR-store-store\t#@membar_storestore" %}
 7722 
 7723   ins_encode %{
 7724     __ membar(MacroAssembler::StoreStore);
 7725   %}
 7726   ins_pipe(pipe_serial);
 7727 %}
 7728 
 7729 instruct membar_release_lock() %{
 7730   match(MemBarReleaseLock);
 7731   ins_cost(0);
 7732 
 7733   format %{ "#@membar_release_lock (elided)" %}
 7734 
 7735   ins_encode %{
 7736     __ block_comment("membar_release_lock (elided)");
 7737   %}
 7738 
 7739   ins_pipe(pipe_serial);
 7740 %}
 7741 
 7742 instruct membar_volatile() %{
 7743   match(MemBarVolatile);
 7744   ins_cost(ALU_COST);
 7745 
 7746   format %{ "#@membar_volatile\n\t"
 7747              "fence iorw iorw"%}
 7748 
 7749   ins_encode %{
 7750     __ block_comment("membar_volatile");
 7751     __ membar(MacroAssembler::StoreLoad);
 7752   %}
 7753 
 7754   ins_pipe(pipe_serial);
 7755 %}
 7756 
 7757 // ============================================================================
 7758 // Cast Instructions (Java-level type cast)
 7759 
 7760 instruct castX2P(iRegPNoSp dst, iRegL src) %{
 7761   match(Set dst (CastX2P src));
 7762 
 7763   ins_cost(ALU_COST);
 7764   format %{ "mv  $dst, $src\t# long -> ptr, #@castX2P" %}
 7765 
 7766   ins_encode %{
 7767     Assembler::CompressibleRegion cr(&_masm);
 7768     if ($dst$$reg != $src$$reg) {
 7769       __ mv(as_Register($dst$$reg), as_Register($src$$reg));
 7770     }
 7771   %}
 7772 
 7773   ins_pipe(ialu_reg);
 7774 %}
 7775 
 7776 instruct castP2X(iRegLNoSp dst, iRegP src) %{
 7777   match(Set dst (CastP2X src));
 7778 
 7779   ins_cost(ALU_COST);
 7780   format %{ "mv  $dst, $src\t# ptr -> long, #@castP2X" %}
 7781 
 7782   ins_encode %{
 7783     Assembler::CompressibleRegion cr(&_masm);
 7784     if ($dst$$reg != $src$$reg) {
 7785       __ mv(as_Register($dst$$reg), as_Register($src$$reg));
 7786     }
 7787   %}
 7788 
 7789   ins_pipe(ialu_reg);
 7790 %}
 7791 
 7792 instruct castPP(iRegPNoSp dst)
 7793 %{
 7794   match(Set dst (CastPP dst));
 7795   ins_cost(0);
 7796 
 7797   size(0);
 7798   format %{ "# castPP of $dst, #@castPP" %}
 7799   ins_encode(/* empty encoding */);
 7800   ins_pipe(pipe_class_empty);
 7801 %}
 7802 
 7803 instruct castLL(iRegL dst)
 7804 %{
 7805   match(Set dst (CastLL dst));
 7806 
 7807   size(0);
 7808   format %{ "# castLL of $dst, #@castLL" %}
 7809   ins_encode(/* empty encoding */);
 7810   ins_cost(0);
 7811   ins_pipe(pipe_class_empty);
 7812 %}
 7813 
 7814 instruct castII(iRegI dst)
 7815 %{
 7816   match(Set dst (CastII dst));
 7817 
 7818   size(0);
 7819   format %{ "# castII of $dst, #@castII" %}
 7820   ins_encode(/* empty encoding */);
 7821   ins_cost(0);
 7822   ins_pipe(pipe_class_empty);
 7823 %}
 7824 
 7825 instruct checkCastPP(iRegPNoSp dst)
 7826 %{
 7827   match(Set dst (CheckCastPP dst));
 7828 
 7829   size(0);
 7830   ins_cost(0);
 7831   format %{ "# checkcastPP of $dst, #@checkCastPP" %}
 7832   ins_encode(/* empty encoding */);
 7833   ins_pipe(pipe_class_empty);
 7834 %}
 7835 
 7836 instruct castFF(fRegF dst)
 7837 %{
 7838   match(Set dst (CastFF dst));
 7839 
 7840   size(0);
 7841   format %{ "# castFF of $dst" %}
 7842   ins_encode(/* empty encoding */);
 7843   ins_cost(0);
 7844   ins_pipe(pipe_class_empty);
 7845 %}
 7846 
 7847 instruct castDD(fRegD dst)
 7848 %{
 7849   match(Set dst (CastDD dst));
 7850 
 7851   size(0);
 7852   format %{ "# castDD of $dst" %}
 7853   ins_encode(/* empty encoding */);
 7854   ins_cost(0);
 7855   ins_pipe(pipe_class_empty);
 7856 %}
 7857 
 7858 instruct castVV(vReg dst)
 7859 %{
 7860   match(Set dst (CastVV dst));
 7861 
 7862   size(0);
 7863   format %{ "# castVV of $dst" %}
 7864   ins_encode(/* empty encoding */);
 7865   ins_cost(0);
 7866   ins_pipe(pipe_class_empty);
 7867 %}
 7868 
 7869 // ============================================================================
 7870 // Convert Instructions
 7871 
 7872 // int to bool
 7873 instruct convI2Bool(iRegINoSp dst, iRegI src)
 7874 %{
 7875   match(Set dst (Conv2B src));
 7876 
 7877   ins_cost(ALU_COST);
 7878   format %{ "snez  $dst, $src\t#@convI2Bool" %}
 7879 
 7880   ins_encode %{
 7881     __ snez(as_Register($dst$$reg), as_Register($src$$reg));
 7882   %}
 7883 
 7884   ins_pipe(ialu_reg);
 7885 %}
 7886 
 7887 // pointer to bool
 7888 instruct convP2Bool(iRegINoSp dst, iRegP src)
 7889 %{
 7890   match(Set dst (Conv2B src));
 7891 
 7892   ins_cost(ALU_COST);
 7893   format %{ "snez  $dst, $src\t#@convP2Bool" %}
 7894 
 7895   ins_encode %{
 7896     __ snez(as_Register($dst$$reg), as_Register($src$$reg));
 7897   %}
 7898 
 7899   ins_pipe(ialu_reg);
 7900 %}
 7901 
 7902 // int <-> long
 7903 
 7904 instruct convI2L_reg_reg(iRegLNoSp dst, iRegIorL2I src)
 7905 %{
 7906   match(Set dst (ConvI2L src));
 7907 
 7908   ins_cost(ALU_COST);
 7909   format %{ "addw  $dst, $src, zr\t#@convI2L_reg_reg" %}
 7910   ins_encode %{
 7911     __ addw(as_Register($dst$$reg), as_Register($src$$reg), zr);
 7912   %}
 7913   ins_pipe(ialu_reg);
 7914 %}
 7915 
 7916 instruct convL2I_reg(iRegINoSp dst, iRegL src) %{
 7917   match(Set dst (ConvL2I src));
 7918 
 7919   ins_cost(ALU_COST);
 7920   format %{ "addw  $dst, $src, zr\t#@convL2I_reg" %}
 7921 
 7922   ins_encode %{
 7923     __ addw(as_Register($dst$$reg), as_Register($src$$reg), zr);
 7924   %}
 7925 
 7926   ins_pipe(ialu_reg);
 7927 %}
 7928 
 7929 // int to unsigned long (Zero-extend)
 7930 instruct convI2UL_reg_reg(iRegLNoSp dst, iRegIorL2I src, immL_32bits mask)
 7931 %{
 7932   match(Set dst (AndL (ConvI2L src) mask));
 7933 
 7934   ins_cost(ALU_COST * 2);
 7935   format %{ "zero_extend $dst, $src, 32\t# i2ul, #@convI2UL_reg_reg" %}
 7936 
 7937   ins_encode %{
 7938     Assembler::CompressibleRegion cr(&_masm);
 7939     __ zero_extend(as_Register($dst$$reg), as_Register($src$$reg), 32);
 7940   %}
 7941 
 7942   ins_pipe(ialu_reg_shift);
 7943 %}
 7944 
 7945 // float <-> double
 7946 
 7947 instruct convF2D_reg(fRegD dst, fRegF src) %{
 7948   match(Set dst (ConvF2D src));
 7949 
 7950   ins_cost(XFER_COST);
 7951   format %{ "fcvt.d.s  $dst, $src\t#@convF2D_reg" %}
 7952 
 7953   ins_encode %{
 7954     __ fcvt_d_s(as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg));
 7955   %}
 7956 
 7957   ins_pipe(fp_f2d);
 7958 %}
 7959 
 7960 instruct convD2F_reg(fRegF dst, fRegD src) %{
 7961   match(Set dst (ConvD2F src));
 7962 
 7963   ins_cost(XFER_COST);
 7964   format %{ "fcvt.s.d  $dst, $src\t#@convD2F_reg" %}
 7965 
 7966   ins_encode %{
 7967     __ fcvt_s_d(as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg));
 7968   %}
 7969 
 7970   ins_pipe(fp_d2f);
 7971 %}
 7972 
 7973 // float <-> int
 7974 
 7975 instruct convF2I_reg_reg(iRegINoSp dst, fRegF src) %{
 7976   match(Set dst (ConvF2I src));
 7977 
 7978   ins_cost(XFER_COST);
 7979   format %{ "fcvt.w.s  $dst, $src\t#@convF2I_reg_reg" %}
 7980 
 7981   ins_encode %{
 7982     __ fcvt_w_s_safe($dst$$Register, $src$$FloatRegister);
 7983   %}
 7984 
 7985   ins_pipe(fp_f2i);
 7986 %}
 7987 
 7988 instruct convI2F_reg_reg(fRegF dst, iRegIorL2I src) %{
 7989   match(Set dst (ConvI2F src));
 7990 
 7991   ins_cost(XFER_COST);
 7992   format %{ "fcvt.s.w  $dst, $src\t#@convI2F_reg_reg" %}
 7993 
 7994   ins_encode %{
 7995     __ fcvt_s_w(as_FloatRegister($dst$$reg), as_Register($src$$reg));
 7996   %}
 7997 
 7998   ins_pipe(fp_i2f);
 7999 %}
 8000 
 8001 // float <-> long
 8002 
 8003 instruct convF2L_reg_reg(iRegLNoSp dst, fRegF src) %{
 8004   match(Set dst (ConvF2L src));
 8005 
 8006   ins_cost(XFER_COST);
 8007   format %{ "fcvt.l.s  $dst, $src\t#@convF2L_reg_reg" %}
 8008 
 8009   ins_encode %{
 8010     __ fcvt_l_s_safe($dst$$Register, $src$$FloatRegister);
 8011   %}
 8012 
 8013   ins_pipe(fp_f2l);
 8014 %}
 8015 
 8016 instruct convL2F_reg_reg(fRegF dst, iRegL src) %{
 8017   match(Set dst (ConvL2F src));
 8018 
 8019   ins_cost(XFER_COST);
 8020   format %{ "fcvt.s.l  $dst, $src\t#@convL2F_reg_reg" %}
 8021 
 8022   ins_encode %{
 8023     __ fcvt_s_l(as_FloatRegister($dst$$reg), as_Register($src$$reg));
 8024   %}
 8025 
 8026   ins_pipe(fp_l2f);
 8027 %}
 8028 
 8029 // double <-> int
 8030 
 8031 instruct convD2I_reg_reg(iRegINoSp dst, fRegD src) %{
 8032   match(Set dst (ConvD2I src));
 8033 
 8034   ins_cost(XFER_COST);
 8035   format %{ "fcvt.w.d  $dst, $src\t#@convD2I_reg_reg" %}
 8036 
 8037   ins_encode %{
 8038     __ fcvt_w_d_safe($dst$$Register, $src$$FloatRegister);
 8039   %}
 8040 
 8041   ins_pipe(fp_d2i);
 8042 %}
 8043 
 8044 instruct convI2D_reg_reg(fRegD dst, iRegIorL2I src) %{
 8045   match(Set dst (ConvI2D src));
 8046 
 8047   ins_cost(XFER_COST);
 8048   format %{ "fcvt.d.w  $dst, $src\t#@convI2D_reg_reg" %}
 8049 
 8050   ins_encode %{
 8051     __ fcvt_d_w(as_FloatRegister($dst$$reg), as_Register($src$$reg));
 8052   %}
 8053 
 8054   ins_pipe(fp_i2d);
 8055 %}
 8056 
 8057 // double <-> long
 8058 
 8059 instruct convD2L_reg_reg(iRegLNoSp dst, fRegD src) %{
 8060   match(Set dst (ConvD2L src));
 8061 
 8062   ins_cost(XFER_COST);
 8063   format %{ "fcvt.l.d  $dst, $src\t#@convD2L_reg_reg" %}
 8064 
 8065   ins_encode %{
 8066     __ fcvt_l_d_safe($dst$$Register, $src$$FloatRegister);
 8067   %}
 8068 
 8069   ins_pipe(fp_d2l);
 8070 %}
 8071 
 8072 instruct convL2D_reg_reg(fRegD dst, iRegL src) %{
 8073   match(Set dst (ConvL2D src));
 8074 
 8075   ins_cost(XFER_COST);
 8076   format %{ "fcvt.d.l  $dst, $src\t#@convL2D_reg_reg" %}
 8077 
 8078   ins_encode %{
 8079     __ fcvt_d_l(as_FloatRegister($dst$$reg), as_Register($src$$reg));
 8080   %}
 8081 
 8082   ins_pipe(fp_l2d);
 8083 %}
 8084 
 8085 // Convert oop into int for vectors alignment masking
 8086 instruct convP2I(iRegINoSp dst, iRegP src) %{
 8087   match(Set dst (ConvL2I (CastP2X src)));
 8088 
 8089   ins_cost(ALU_COST * 2);
 8090   format %{ "zero_extend $dst, $src, 32\t# ptr -> int, #@convP2I" %}
 8091 
 8092   ins_encode %{
 8093     Assembler::CompressibleRegion cr(&_masm);
 8094     __ zero_extend($dst$$Register, $src$$Register, 32);
 8095   %}
 8096 
 8097   ins_pipe(ialu_reg);
 8098 %}
 8099 
 8100 // Convert compressed oop into int for vectors alignment masking
 8101 // in case of 32bit oops (heap < 4Gb).
 8102 instruct convN2I(iRegINoSp dst, iRegN src)
 8103 %{
 8104   predicate(CompressedOops::shift() == 0);
 8105   match(Set dst (ConvL2I (CastP2X (DecodeN src))));
 8106 
 8107   ins_cost(ALU_COST);
 8108   format %{ "mv  $dst, $src\t# compressed ptr -> int, #@convN2I" %}
 8109 
 8110   ins_encode %{
 8111     Assembler::CompressibleRegion cr(&_masm);
 8112     __ mv($dst$$Register, $src$$Register);
 8113   %}
 8114 
 8115   ins_pipe(ialu_reg);
 8116 %}
 8117 
 8118 // Convert oop pointer into compressed form
 8119 instruct encodeHeapOop(iRegNNoSp dst, iRegP src) %{
 8120   match(Set dst (EncodeP src));
 8121   ins_cost(ALU_COST);
 8122   format %{ "encode_heap_oop  $dst, $src\t#@encodeHeapOop" %}
 8123   ins_encode %{
 8124     Register s = $src$$Register;
 8125     Register d = $dst$$Register;
 8126     __ encode_heap_oop(d, s);
 8127   %}
 8128   ins_pipe(ialu_reg);
 8129 %}
 8130 
 8131 instruct decodeHeapOop(iRegPNoSp dst, iRegN src) %{
 8132   predicate(n->bottom_type()->is_ptr()->ptr() != TypePtr::NotNull &&
 8133             n->bottom_type()->is_ptr()->ptr() != TypePtr::Constant);
 8134   match(Set dst (DecodeN src));
 8135 
 8136   ins_cost(0);
 8137   format %{ "decode_heap_oop  $dst, $src\t#@decodeHeapOop" %}
 8138   ins_encode %{
 8139     Register s = $src$$Register;
 8140     Register d = $dst$$Register;
 8141     __ decode_heap_oop(d, s);
 8142   %}
 8143   ins_pipe(ialu_reg);
 8144 %}
 8145 
 8146 instruct decodeHeapOop_not_null(iRegPNoSp dst, iRegN src) %{
 8147   predicate(n->bottom_type()->is_ptr()->ptr() == TypePtr::NotNull ||
 8148             n->bottom_type()->is_ptr()->ptr() == TypePtr::Constant);
 8149   match(Set dst (DecodeN src));
 8150 
 8151   ins_cost(0);
 8152   format %{ "decode_heap_oop_not_null $dst, $src\t#@decodeHeapOop_not_null" %}
 8153   ins_encode %{
 8154     Register s = $src$$Register;
 8155     Register d = $dst$$Register;
 8156     __ decode_heap_oop_not_null(d, s);
 8157   %}
 8158   ins_pipe(ialu_reg);
 8159 %}
 8160 
 8161 // Convert klass pointer into compressed form.
 8162 instruct encodeKlass_not_null(iRegNNoSp dst, iRegP src) %{
 8163   match(Set dst (EncodePKlass src));
 8164 
 8165   ins_cost(ALU_COST);
 8166   format %{ "encode_klass_not_null  $dst, $src\t#@encodeKlass_not_null" %}
 8167 
 8168   ins_encode %{
 8169     Register src_reg = as_Register($src$$reg);
 8170     Register dst_reg = as_Register($dst$$reg);
 8171     __ encode_klass_not_null(dst_reg, src_reg, t0);
 8172   %}
 8173 
 8174    ins_pipe(ialu_reg);
 8175 %}
 8176 
 8177 instruct decodeKlass_not_null(iRegPNoSp dst, iRegN src, iRegPNoSp tmp) %{
 8178   match(Set dst (DecodeNKlass src));
 8179 
 8180   effect(TEMP tmp);
 8181 
 8182   ins_cost(ALU_COST);
 8183   format %{ "decode_klass_not_null  $dst, $src\t#@decodeKlass_not_null" %}
 8184 
 8185   ins_encode %{
 8186     Register src_reg = as_Register($src$$reg);
 8187     Register dst_reg = as_Register($dst$$reg);
 8188     Register tmp_reg = as_Register($tmp$$reg);
 8189     __ decode_klass_not_null(dst_reg, src_reg, tmp_reg);
 8190   %}
 8191 
 8192    ins_pipe(ialu_reg);
 8193 %}
 8194 
 8195 // stack <-> reg and reg <-> reg shuffles with no conversion
 8196 
 8197 instruct MoveF2I_stack_reg(iRegINoSp dst, stackSlotF src) %{
 8198 
 8199   match(Set dst (MoveF2I src));
 8200 
 8201   effect(DEF dst, USE src);
 8202 
 8203   ins_cost(LOAD_COST);
 8204 
 8205   format %{ "lw  $dst, $src\t#@MoveF2I_stack_reg" %}
 8206 
 8207   ins_encode %{
 8208     Assembler::CompressibleRegion cr(&_masm);
 8209     __ lw(as_Register($dst$$reg), Address(sp, $src$$disp));
 8210   %}
 8211 
 8212   ins_pipe(iload_reg_reg);
 8213 
 8214 %}
 8215 
 8216 instruct MoveI2F_stack_reg(fRegF dst, stackSlotI src) %{
 8217 
 8218   match(Set dst (MoveI2F src));
 8219 
 8220   effect(DEF dst, USE src);
 8221 
 8222   ins_cost(LOAD_COST);
 8223 
 8224   format %{ "flw  $dst, $src\t#@MoveI2F_stack_reg" %}
 8225 
 8226   ins_encode %{
 8227     __ flw(as_FloatRegister($dst$$reg), Address(sp, $src$$disp));
 8228   %}
 8229 
 8230   ins_pipe(pipe_class_memory);
 8231 
 8232 %}
 8233 
 8234 instruct MoveD2L_stack_reg(iRegLNoSp dst, stackSlotD src) %{
 8235 
 8236   match(Set dst (MoveD2L src));
 8237 
 8238   effect(DEF dst, USE src);
 8239 
 8240   ins_cost(LOAD_COST);
 8241 
 8242   format %{ "ld  $dst, $src\t#@MoveD2L_stack_reg" %}
 8243 
 8244   ins_encode %{
 8245     Assembler::CompressibleRegion cr(&_masm);
 8246     __ ld(as_Register($dst$$reg), Address(sp, $src$$disp));
 8247   %}
 8248 
 8249   ins_pipe(iload_reg_reg);
 8250 
 8251 %}
 8252 
 8253 instruct MoveL2D_stack_reg(fRegD dst, stackSlotL src) %{
 8254 
 8255   match(Set dst (MoveL2D src));
 8256 
 8257   effect(DEF dst, USE src);
 8258 
 8259   ins_cost(LOAD_COST);
 8260 
 8261   format %{ "fld  $dst, $src\t#@MoveL2D_stack_reg" %}
 8262 
 8263   ins_encode %{
 8264     Assembler::CompressibleRegion cr(&_masm);
 8265     __ fld(as_FloatRegister($dst$$reg), Address(sp, $src$$disp));
 8266   %}
 8267 
 8268   ins_pipe(pipe_class_memory);
 8269 
 8270 %}
 8271 
 8272 instruct MoveF2I_reg_stack(stackSlotI dst, fRegF src) %{
 8273 
 8274   match(Set dst (MoveF2I src));
 8275 
 8276   effect(DEF dst, USE src);
 8277 
 8278   ins_cost(STORE_COST);
 8279 
 8280   format %{ "fsw  $src, $dst\t#@MoveF2I_reg_stack" %}
 8281 
 8282   ins_encode %{
 8283     __ fsw(as_FloatRegister($src$$reg), Address(sp, $dst$$disp));
 8284   %}
 8285 
 8286   ins_pipe(pipe_class_memory);
 8287 
 8288 %}
 8289 
 8290 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{
 8291 
 8292   match(Set dst (MoveI2F src));
 8293 
 8294   effect(DEF dst, USE src);
 8295 
 8296   ins_cost(STORE_COST);
 8297 
 8298   format %{ "sw  $src, $dst\t#@MoveI2F_reg_stack" %}
 8299 
 8300   ins_encode %{
 8301     Assembler::CompressibleRegion cr(&_masm);
 8302     __ sw(as_Register($src$$reg), Address(sp, $dst$$disp));
 8303   %}
 8304 
 8305   ins_pipe(istore_reg_reg);
 8306 
 8307 %}
 8308 
 8309 instruct MoveD2L_reg_stack(stackSlotL dst, fRegD src) %{
 8310 
 8311   match(Set dst (MoveD2L src));
 8312 
 8313   effect(DEF dst, USE src);
 8314 
 8315   ins_cost(STORE_COST);
 8316 
 8317   format %{ "fsd  $dst, $src\t#@MoveD2L_reg_stack" %}
 8318 
 8319   ins_encode %{
 8320     Assembler::CompressibleRegion cr(&_masm);
 8321     __ fsd(as_FloatRegister($src$$reg), Address(sp, $dst$$disp));
 8322   %}
 8323 
 8324   ins_pipe(pipe_class_memory);
 8325 
 8326 %}
 8327 
 8328 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{
 8329 
 8330   match(Set dst (MoveL2D src));
 8331 
 8332   effect(DEF dst, USE src);
 8333 
 8334   ins_cost(STORE_COST);
 8335 
 8336   format %{ "sd  $src, $dst\t#@MoveL2D_reg_stack" %}
 8337 
 8338   ins_encode %{
 8339     Assembler::CompressibleRegion cr(&_masm);
 8340     __ sd(as_Register($src$$reg), Address(sp, $dst$$disp));
 8341   %}
 8342 
 8343   ins_pipe(istore_reg_reg);
 8344 
 8345 %}
 8346 
 8347 instruct MoveF2I_reg_reg(iRegINoSp dst, fRegF src) %{
 8348 
 8349   match(Set dst (MoveF2I src));
 8350 
 8351   effect(DEF dst, USE src);
 8352 
 8353   ins_cost(XFER_COST);
 8354 
 8355   format %{ "fmv.x.w  $dst, $src\t#@MoveL2D_reg_stack" %}
 8356 
 8357   ins_encode %{
 8358     __ fmv_x_w(as_Register($dst$$reg), as_FloatRegister($src$$reg));
 8359   %}
 8360 
 8361   ins_pipe(fp_f2i);
 8362 
 8363 %}
 8364 
 8365 instruct MoveI2F_reg_reg(fRegF dst, iRegI src) %{
 8366 
 8367   match(Set dst (MoveI2F src));
 8368 
 8369   effect(DEF dst, USE src);
 8370 
 8371   ins_cost(XFER_COST);
 8372 
 8373   format %{ "fmv.w.x  $dst, $src\t#@MoveI2F_reg_reg" %}
 8374 
 8375   ins_encode %{
 8376     __ fmv_w_x(as_FloatRegister($dst$$reg), as_Register($src$$reg));
 8377   %}
 8378 
 8379   ins_pipe(fp_i2f);
 8380 
 8381 %}
 8382 
 8383 instruct MoveD2L_reg_reg(iRegLNoSp dst, fRegD src) %{
 8384 
 8385   match(Set dst (MoveD2L src));
 8386 
 8387   effect(DEF dst, USE src);
 8388 
 8389   ins_cost(XFER_COST);
 8390 
 8391   format %{ "fmv.x.d $dst, $src\t#@MoveD2L_reg_reg" %}
 8392 
 8393   ins_encode %{
 8394     __ fmv_x_d(as_Register($dst$$reg), as_FloatRegister($src$$reg));
 8395   %}
 8396 
 8397   ins_pipe(fp_d2l);
 8398 
 8399 %}
 8400 
 8401 instruct MoveL2D_reg_reg(fRegD dst, iRegL src) %{
 8402 
 8403   match(Set dst (MoveL2D src));
 8404 
 8405   effect(DEF dst, USE src);
 8406 
 8407   ins_cost(XFER_COST);
 8408 
 8409   format %{ "fmv.d.x  $dst, $src\t#@MoveD2L_reg_reg" %}
 8410 
 8411   ins_encode %{
 8412     __ fmv_d_x(as_FloatRegister($dst$$reg), as_Register($src$$reg));
 8413   %}
 8414 
 8415   ins_pipe(fp_l2d);
 8416 %}
 8417 
 8418 // ============================================================================
 8419 // Compare Instructions which set the result float comparisons in dest register.
 8420 
 8421 instruct cmpF3_reg_reg(iRegINoSp dst, fRegF op1, fRegF op2)
 8422 %{
 8423   match(Set dst (CmpF3 op1 op2));
 8424 
 8425   ins_cost(XFER_COST * 2 + BRANCH_COST + ALU_COST);
 8426   format %{ "flt.s  $dst, $op2, $op1\t#@cmpF3_reg_reg\n\t"
 8427             "bgtz   $dst, done\n\t"
 8428             "feq.s  $dst, $op1, $op2\n\t"
 8429             "addi   $dst, $dst, -1\t#@cmpF3_reg_reg"
 8430   %}
 8431 
 8432   ins_encode %{
 8433     // we want -1 for unordered or less than, 0 for equal and 1 for greater than.
 8434     __ float_compare(as_Register($dst$$reg), as_FloatRegister($op1$$reg),
 8435                      as_FloatRegister($op2$$reg), -1 /*unordered_result < 0*/);
 8436   %}
 8437 
 8438   ins_pipe(pipe_class_default);
 8439 %}
 8440 
 8441 instruct cmpD3_reg_reg(iRegINoSp dst, fRegD op1, fRegD op2)
 8442 %{
 8443   match(Set dst (CmpD3 op1 op2));
 8444 
 8445   ins_cost(XFER_COST * 2 + BRANCH_COST + ALU_COST);
 8446   format %{ "flt.d  $dst, $op2, $op1\t#@cmpD3_reg_reg\n\t"
 8447             "bgtz   $dst, done\n\t"
 8448             "feq.d  $dst, $op1, $op2\n\t"
 8449             "addi   $dst, $dst, -1\t#@cmpD3_reg_reg"
 8450   %}
 8451 
 8452   ins_encode %{
 8453     // we want -1 for unordered or less than, 0 for equal and 1 for greater than.
 8454     __ double_compare(as_Register($dst$$reg), as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg), -1 /*unordered_result < 0*/);
 8455   %}
 8456 
 8457   ins_pipe(pipe_class_default);
 8458 %}
 8459 
 8460 instruct cmpL3_reg_reg(iRegINoSp dst, iRegL op1, iRegL op2)
 8461 %{
 8462   match(Set dst (CmpL3 op1 op2));
 8463 
 8464   ins_cost(ALU_COST * 3 + BRANCH_COST);
 8465   format %{ "slt   $dst, $op2, $op1\t#@cmpL3_reg_reg\n\t"
 8466             "bnez  $dst, done\n\t"
 8467             "slt  $dst, $op1, $op2\n\t"
 8468             "neg   $dst, $dst\t#@cmpL3_reg_reg"
 8469   %}
 8470   ins_encode %{
 8471     __ cmp_l2i(t0, as_Register($op1$$reg), as_Register($op2$$reg));
 8472     __ mv(as_Register($dst$$reg), t0);
 8473   %}
 8474 
 8475   ins_pipe(pipe_class_default);
 8476 %}
 8477 
 8478 instruct cmpLTMask_reg_reg(iRegINoSp dst, iRegI p, iRegI q)
 8479 %{
 8480   match(Set dst (CmpLTMask p q));
 8481 
 8482   ins_cost(2 * ALU_COST);
 8483 
 8484   format %{ "slt $dst, $p, $q\t#@cmpLTMask_reg_reg\n\t"
 8485             "subw $dst, zr, $dst\t#@cmpLTMask_reg_reg"
 8486   %}
 8487 
 8488   ins_encode %{
 8489     __ slt(as_Register($dst$$reg), as_Register($p$$reg), as_Register($q$$reg));
 8490     __ subw(as_Register($dst$$reg), zr, as_Register($dst$$reg));
 8491   %}
 8492 
 8493   ins_pipe(ialu_reg_reg);
 8494 %}
 8495 
 8496 instruct cmpLTMask_reg_zero(iRegINoSp dst, iRegIorL2I op, immI0 zero)
 8497 %{
 8498   match(Set dst (CmpLTMask op zero));
 8499 
 8500   ins_cost(ALU_COST);
 8501 
 8502   format %{ "sraiw $dst, $dst, 31\t#@cmpLTMask_reg_reg" %}
 8503 
 8504   ins_encode %{
 8505     __ sraiw(as_Register($dst$$reg), as_Register($op$$reg), 31);
 8506   %}
 8507 
 8508   ins_pipe(ialu_reg_shift);
 8509 %}
 8510 
 8511 
 8512 // ============================================================================
 8513 // Max and Min
 8514 
 8515 instruct minI_rReg(iRegINoSp dst, iRegI src1, iRegI src2)
 8516 %{
 8517   match(Set dst (MinI src1 src2));
 8518 
 8519   effect(DEF dst, USE src1, USE src2);
 8520 
 8521   ins_cost(BRANCH_COST + ALU_COST * 2);
 8522   format %{
 8523     "ble $src1, $src2, Lsrc1.\t#@minI_rReg\n\t"
 8524     "mv $dst, $src2\n\t"
 8525     "j Ldone\n\t"
 8526     "bind Lsrc1\n\t"
 8527     "mv $dst, $src1\n\t"
 8528     "bind\t#@minI_rReg"
 8529   %}
 8530 
 8531   ins_encode %{
 8532     Label Lsrc1, Ldone;
 8533     __ ble(as_Register($src1$$reg), as_Register($src2$$reg), Lsrc1);
 8534     __ mv(as_Register($dst$$reg), as_Register($src2$$reg));
 8535     __ j(Ldone);
 8536     __ bind(Lsrc1);
 8537     __ mv(as_Register($dst$$reg), as_Register($src1$$reg));
 8538     __ bind(Ldone);
 8539   %}
 8540 
 8541   ins_pipe(ialu_reg_reg);
 8542 %}
 8543 
 8544 instruct maxI_rReg(iRegINoSp dst, iRegI src1, iRegI src2)
 8545 %{
 8546   match(Set dst (MaxI src1 src2));
 8547 
 8548   effect(DEF dst, USE src1, USE src2);
 8549 
 8550   ins_cost(BRANCH_COST + ALU_COST * 2);
 8551   format %{
 8552     "bge $src1, $src2, Lsrc1\t#@maxI_rReg\n\t"
 8553     "mv $dst, $src2\n\t"
 8554     "j Ldone\n\t"
 8555     "bind Lsrc1\n\t"
 8556     "mv $dst, $src1\n\t"
 8557     "bind\t#@maxI_rReg"
 8558   %}
 8559 
 8560   ins_encode %{
 8561     Label Lsrc1, Ldone;
 8562     __ bge(as_Register($src1$$reg), as_Register($src2$$reg), Lsrc1);
 8563     __ mv(as_Register($dst$$reg), as_Register($src2$$reg));
 8564     __ j(Ldone);
 8565     __ bind(Lsrc1);
 8566     __ mv(as_Register($dst$$reg), as_Register($src1$$reg));
 8567     __ bind(Ldone);
 8568 
 8569   %}
 8570 
 8571   ins_pipe(ialu_reg_reg);
 8572 %}
 8573 
 8574 // ============================================================================
 8575 // Branch Instructions
 8576 // Direct Branch.
 8577 instruct branch(label lbl)
 8578 %{
 8579   match(Goto);
 8580 
 8581   effect(USE lbl);
 8582 
 8583   ins_cost(BRANCH_COST);
 8584   format %{ "j  $lbl\t#@branch" %}
 8585 
 8586   ins_encode(riscv_enc_j(lbl));
 8587 
 8588   ins_pipe(pipe_branch);
 8589 %}
 8590 
 8591 // ============================================================================
 8592 // Compare and Branch Instructions
 8593 
 8594 // Patterns for short (< 12KiB) variants
 8595 
 8596 // Compare flags and branch near instructions.
 8597 instruct cmpFlag_branch(cmpOpEqNe cmp, rFlagsReg cr, label lbl) %{
 8598   match(If cmp cr);
 8599   effect(USE lbl);
 8600 
 8601   ins_cost(BRANCH_COST);
 8602   format %{ "b$cmp  $cr, zr, $lbl\t#@cmpFlag_branch" %}
 8603 
 8604   ins_encode %{
 8605     __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($cr$$reg), *($lbl$$label));
 8606   %}
 8607   ins_pipe(pipe_cmpz_branch);
 8608   ins_short_branch(1);
 8609 %}
 8610 
 8611 // Compare signed int and branch near instructions
 8612 instruct cmpI_branch(cmpOp cmp, iRegI op1, iRegI op2, label lbl)
 8613 %{
 8614   // Same match rule as `far_cmpI_branch'.
 8615   match(If cmp (CmpI op1 op2));
 8616 
 8617   effect(USE lbl);
 8618 
 8619   ins_cost(BRANCH_COST);
 8620 
 8621   format %{ "b$cmp  $op1, $op2, $lbl\t#@cmpI_branch" %}
 8622 
 8623   ins_encode %{
 8624     __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label));
 8625   %}
 8626 
 8627   ins_pipe(pipe_cmp_branch);
 8628   ins_short_branch(1);
 8629 %}
 8630 
 8631 instruct cmpI_loop(cmpOp cmp, iRegI op1, iRegI op2, label lbl)
 8632 %{
 8633   // Same match rule as `far_cmpI_loop'.
 8634   match(CountedLoopEnd cmp (CmpI op1 op2));
 8635 
 8636   effect(USE lbl);
 8637 
 8638   ins_cost(BRANCH_COST);
 8639 
 8640   format %{ "b$cmp  $op1, $op2, $lbl\t#@cmpI_loop" %}
 8641 
 8642   ins_encode %{
 8643     __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label));
 8644   %}
 8645 
 8646   ins_pipe(pipe_cmp_branch);
 8647   ins_short_branch(1);
 8648 %}
 8649 
 8650 // Compare unsigned int and branch near instructions
 8651 instruct cmpU_branch(cmpOpU cmp, iRegI op1, iRegI op2, label lbl)
 8652 %{
 8653   // Same match rule as `far_cmpU_branch'.
 8654   match(If cmp (CmpU op1 op2));
 8655 
 8656   effect(USE lbl);
 8657 
 8658   ins_cost(BRANCH_COST);
 8659 
 8660   format %{ "b$cmp  $op1, $op2, $lbl\t#@cmpU_branch" %}
 8661 
 8662   ins_encode %{
 8663     __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
 8664                   as_Register($op2$$reg), *($lbl$$label));
 8665   %}
 8666 
 8667   ins_pipe(pipe_cmp_branch);
 8668   ins_short_branch(1);
 8669 %}
 8670 
 8671 instruct cmpU_loop(cmpOpU cmp, iRegI op1, iRegI op2, label lbl)
 8672 %{
 8673   // Same match rule as `far_cmpU_loop'.
 8674   match(CountedLoopEnd cmp (CmpU op1 op2));
 8675 
 8676   effect(USE lbl);
 8677 
 8678   ins_cost(BRANCH_COST);
 8679 
 8680   format %{ "b$cmp  $op1, $op2, $lbl\t#@cmpU_loop" %}
 8681 
 8682   ins_encode %{
 8683     __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
 8684                   as_Register($op2$$reg), *($lbl$$label));
 8685   %}
 8686 
 8687   ins_pipe(pipe_cmp_branch);
 8688   ins_short_branch(1);
 8689 %}
 8690 
 8691 // Compare signed long and branch near instructions
 8692 instruct cmpL_branch(cmpOp cmp, iRegL op1, iRegL op2, label lbl)
 8693 %{
 8694   // Same match rule as `far_cmpL_branch'.
 8695   match(If cmp (CmpL op1 op2));
 8696 
 8697   effect(USE lbl);
 8698 
 8699   ins_cost(BRANCH_COST);
 8700 
 8701   format %{ "b$cmp  $op1, $op2, $lbl\t#@cmpL_branch" %}
 8702 
 8703   ins_encode %{
 8704     __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label));
 8705   %}
 8706 
 8707   ins_pipe(pipe_cmp_branch);
 8708   ins_short_branch(1);
 8709 %}
 8710 
 8711 instruct cmpL_loop(cmpOp cmp, iRegL op1, iRegL op2, label lbl)
 8712 %{
 8713   // Same match rule as `far_cmpL_loop'.
 8714   match(CountedLoopEnd cmp (CmpL op1 op2));
 8715 
 8716   effect(USE lbl);
 8717 
 8718   ins_cost(BRANCH_COST);
 8719 
 8720   format %{ "b$cmp  $op1, $op2, $lbl\t#@cmpL_loop" %}
 8721 
 8722   ins_encode %{
 8723     __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label));
 8724   %}
 8725 
 8726   ins_pipe(pipe_cmp_branch);
 8727   ins_short_branch(1);
 8728 %}
 8729 
 8730 // Compare unsigned long and branch near instructions
 8731 instruct cmpUL_branch(cmpOpU cmp, iRegL op1, iRegL op2, label lbl)
 8732 %{
 8733   // Same match rule as `far_cmpUL_branch'.
 8734   match(If cmp (CmpUL op1 op2));
 8735 
 8736   effect(USE lbl);
 8737 
 8738   ins_cost(BRANCH_COST);
 8739   format %{ "b$cmp  $op1, $op2, $lbl\t#@cmpUL_branch" %}
 8740 
 8741   ins_encode %{
 8742     __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
 8743                   as_Register($op2$$reg), *($lbl$$label));
 8744   %}
 8745 
 8746   ins_pipe(pipe_cmp_branch);
 8747   ins_short_branch(1);
 8748 %}
 8749 
 8750 instruct cmpUL_loop(cmpOpU cmp, iRegL op1, iRegL op2, label lbl)
 8751 %{
 8752   // Same match rule as `far_cmpUL_loop'.
 8753   match(CountedLoopEnd cmp (CmpUL op1 op2));
 8754 
 8755   effect(USE lbl);
 8756 
 8757   ins_cost(BRANCH_COST);
 8758   format %{ "b$cmp  $op1, $op2, $lbl\t#@cmpUL_loop" %}
 8759 
 8760   ins_encode %{
 8761     __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
 8762                   as_Register($op2$$reg), *($lbl$$label));
 8763   %}
 8764 
 8765   ins_pipe(pipe_cmp_branch);
 8766   ins_short_branch(1);
 8767 %}
 8768 
 8769 // Compare pointer and branch near instructions
 8770 instruct cmpP_branch(cmpOpU cmp, iRegP op1, iRegP op2, label lbl)
 8771 %{
 8772   // Same match rule as `far_cmpP_branch'.
 8773   match(If cmp (CmpP op1 op2));
 8774 
 8775   effect(USE lbl);
 8776 
 8777   ins_cost(BRANCH_COST);
 8778 
 8779   format %{ "b$cmp  $op1, $op2, $lbl\t#@cmpP_branch" %}
 8780 
 8781   ins_encode %{
 8782     __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
 8783                   as_Register($op2$$reg), *($lbl$$label));
 8784   %}
 8785 
 8786   ins_pipe(pipe_cmp_branch);
 8787   ins_short_branch(1);
 8788 %}
 8789 
 8790 instruct cmpP_loop(cmpOpU cmp, iRegP op1, iRegP op2, label lbl)
 8791 %{
 8792   // Same match rule as `far_cmpP_loop'.
 8793   match(CountedLoopEnd cmp (CmpP op1 op2));
 8794 
 8795   effect(USE lbl);
 8796 
 8797   ins_cost(BRANCH_COST);
 8798 
 8799   format %{ "b$cmp  $op1, $op2, $lbl\t#@cmpP_loop" %}
 8800 
 8801   ins_encode %{
 8802     __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
 8803                   as_Register($op2$$reg), *($lbl$$label));
 8804   %}
 8805 
 8806   ins_pipe(pipe_cmp_branch);
 8807   ins_short_branch(1);
 8808 %}
 8809 
 8810 // Compare narrow pointer and branch near instructions
 8811 instruct cmpN_branch(cmpOpU cmp, iRegN op1, iRegN op2, label lbl)
 8812 %{
 8813   // Same match rule as `far_cmpN_branch'.
 8814   match(If cmp (CmpN op1 op2));
 8815 
 8816   effect(USE lbl);
 8817 
 8818   ins_cost(BRANCH_COST);
 8819 
 8820   format %{ "b$cmp  $op1, $op2, $lbl\t#@cmpN_branch" %}
 8821 
 8822   ins_encode %{
 8823     __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
 8824                   as_Register($op2$$reg), *($lbl$$label));
 8825   %}
 8826 
 8827   ins_pipe(pipe_cmp_branch);
 8828   ins_short_branch(1);
 8829 %}
 8830 
 8831 instruct cmpN_loop(cmpOpU cmp, iRegN op1, iRegN op2, label lbl)
 8832 %{
 8833   // Same match rule as `far_cmpN_loop'.
 8834   match(CountedLoopEnd cmp (CmpN op1 op2));
 8835 
 8836   effect(USE lbl);
 8837 
 8838   ins_cost(BRANCH_COST);
 8839 
 8840   format %{ "b$cmp  $op1, $op2, $lbl\t#@cmpN_loop" %}
 8841 
 8842   ins_encode %{
 8843     __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
 8844                   as_Register($op2$$reg), *($lbl$$label));
 8845   %}
 8846 
 8847   ins_pipe(pipe_cmp_branch);
 8848   ins_short_branch(1);
 8849 %}
 8850 
 8851 // Compare float and branch near instructions
 8852 instruct cmpF_branch(cmpOp cmp, fRegF op1, fRegF op2, label lbl)
 8853 %{
 8854   // Same match rule as `far_cmpF_branch'.
 8855   match(If cmp (CmpF op1 op2));
 8856 
 8857   effect(USE lbl);
 8858 
 8859   ins_cost(XFER_COST + BRANCH_COST);
 8860   format %{ "float_b$cmp $op1, $op2, $lbl \t#@cmpF_branch"%}
 8861 
 8862   ins_encode %{
 8863     __ float_cmp_branch($cmp$$cmpcode, as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg), *($lbl$$label));
 8864   %}
 8865 
 8866   ins_pipe(pipe_class_compare);
 8867   ins_short_branch(1);
 8868 %}
 8869 
 8870 instruct cmpF_loop(cmpOp cmp, fRegF op1, fRegF op2, label lbl)
 8871 %{
 8872   // Same match rule as `far_cmpF_loop'.
 8873   match(CountedLoopEnd cmp (CmpF op1 op2));
 8874   effect(USE lbl);
 8875 
 8876   ins_cost(XFER_COST + BRANCH_COST);
 8877   format %{ "float_b$cmp $op1, $op2, $lbl\t#@cmpF_loop"%}
 8878 
 8879   ins_encode %{
 8880     __ float_cmp_branch($cmp$$cmpcode, as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg), *($lbl$$label));
 8881   %}
 8882 
 8883   ins_pipe(pipe_class_compare);
 8884   ins_short_branch(1);
 8885 %}
 8886 
 8887 // Compare double and branch near instructions
 8888 instruct cmpD_branch(cmpOp cmp, fRegD op1, fRegD op2, label lbl)
 8889 %{
 8890   // Same match rule as `far_cmpD_branch'.
 8891   match(If cmp (CmpD op1 op2));
 8892   effect(USE lbl);
 8893 
 8894   ins_cost(XFER_COST + BRANCH_COST);
 8895   format %{ "double_b$cmp $op1, $op2, $lbl\t#@cmpD_branch"%}
 8896 
 8897   ins_encode %{
 8898     __ float_cmp_branch($cmp$$cmpcode | C2_MacroAssembler::double_branch_mask, as_FloatRegister($op1$$reg),
 8899                         as_FloatRegister($op2$$reg), *($lbl$$label));
 8900   %}
 8901 
 8902   ins_pipe(pipe_class_compare);
 8903   ins_short_branch(1);
 8904 %}
 8905 
 8906 instruct cmpD_loop(cmpOp cmp, fRegD op1, fRegD op2, label lbl)
 8907 %{
 8908   // Same match rule as `far_cmpD_loop'.
 8909   match(CountedLoopEnd cmp (CmpD op1 op2));
 8910   effect(USE lbl);
 8911 
 8912   ins_cost(XFER_COST + BRANCH_COST);
 8913   format %{ "double_b$cmp $op1, $op2, $lbl\t#@cmpD_loop"%}
 8914 
 8915   ins_encode %{
 8916     __ float_cmp_branch($cmp$$cmpcode | C2_MacroAssembler::double_branch_mask, as_FloatRegister($op1$$reg),
 8917                         as_FloatRegister($op2$$reg), *($lbl$$label));
 8918   %}
 8919 
 8920   ins_pipe(pipe_class_compare);
 8921   ins_short_branch(1);
 8922 %}
 8923 
 8924 // Compare signed int with zero and branch near instructions
 8925 instruct cmpI_reg_imm0_branch(cmpOp cmp, iRegI op1, immI0 zero, label lbl)
 8926 %{
 8927   // Same match rule as `far_cmpI_reg_imm0_branch'.
 8928   match(If cmp (CmpI op1 zero));
 8929 
 8930   effect(USE op1, USE lbl);
 8931 
 8932   ins_cost(BRANCH_COST);
 8933   format %{ "b$cmp  $op1, zr, $lbl\t#@cmpI_reg_imm0_branch" %}
 8934 
 8935   ins_encode %{
 8936     __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label));
 8937   %}
 8938 
 8939   ins_pipe(pipe_cmpz_branch);
 8940   ins_short_branch(1);
 8941 %}
 8942 
 8943 instruct cmpI_reg_imm0_loop(cmpOp cmp, iRegI op1, immI0 zero, label lbl)
 8944 %{
 8945   // Same match rule as `far_cmpI_reg_imm0_loop'.
 8946   match(CountedLoopEnd cmp (CmpI op1 zero));
 8947 
 8948   effect(USE op1, USE lbl);
 8949 
 8950   ins_cost(BRANCH_COST);
 8951 
 8952   format %{ "b$cmp  $op1, zr, $lbl\t#@cmpI_reg_imm0_loop" %}
 8953 
 8954   ins_encode %{
 8955     __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label));
 8956   %}
 8957 
 8958   ins_pipe(pipe_cmpz_branch);
 8959   ins_short_branch(1);
 8960 %}
 8961 
 8962 // Compare unsigned int with zero and branch near instructions
 8963 instruct cmpUEqNeLeGt_reg_imm0_branch(cmpOpUEqNeLeGt cmp, iRegI op1, immI0 zero, label lbl)
 8964 %{
 8965   // Same match rule as `far_cmpUEqNeLeGt_reg_imm0_branch'.
 8966   match(If cmp (CmpU op1 zero));
 8967 
 8968   effect(USE op1, USE lbl);
 8969 
 8970   ins_cost(BRANCH_COST);
 8971 
 8972   format %{ "b$cmp  $op1, zr, $lbl\t#@cmpUEqNeLeGt_reg_imm0_branch" %}
 8973 
 8974   ins_encode %{
 8975     __ enc_cmpUEqNeLeGt_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
 8976   %}
 8977 
 8978   ins_pipe(pipe_cmpz_branch);
 8979   ins_short_branch(1);
 8980 %}
 8981 
 8982 instruct cmpUEqNeLeGt_reg_imm0_loop(cmpOpUEqNeLeGt cmp, iRegI op1, immI0 zero, label lbl)
 8983 %{
 8984   // Same match rule as `far_cmpUEqNeLeGt_reg_imm0_loop'.
 8985   match(CountedLoopEnd cmp (CmpU op1 zero));
 8986 
 8987   effect(USE op1, USE lbl);
 8988 
 8989   ins_cost(BRANCH_COST);
 8990 
 8991   format %{ "b$cmp  $op1, zr, $lbl\t#@cmpUEqNeLeGt_reg_imm0_loop" %}
 8992 
 8993 
 8994   ins_encode %{
 8995     __ enc_cmpUEqNeLeGt_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
 8996   %}
 8997 
 8998   ins_pipe(pipe_cmpz_branch);
 8999   ins_short_branch(1);
 9000 %}
 9001 
 9002 // Compare signed long with zero and branch near instructions
 9003 instruct cmpL_reg_imm0_branch(cmpOp cmp, iRegL op1, immL0 zero, label lbl)
 9004 %{
 9005   // Same match rule as `far_cmpL_reg_imm0_branch'.
 9006   match(If cmp (CmpL op1 zero));
 9007 
 9008   effect(USE op1, USE lbl);
 9009 
 9010   ins_cost(BRANCH_COST);
 9011 
 9012   format %{ "b$cmp  $op1, zr, $lbl\t#@cmpL_reg_imm0_branch" %}
 9013 
 9014   ins_encode %{
 9015     __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label));
 9016   %}
 9017 
 9018   ins_pipe(pipe_cmpz_branch);
 9019   ins_short_branch(1);
 9020 %}
 9021 
 9022 instruct cmpL_reg_imm0_loop(cmpOp cmp, iRegL op1, immL0 zero, label lbl)
 9023 %{
 9024   // Same match rule as `far_cmpL_reg_imm0_loop'.
 9025   match(CountedLoopEnd cmp (CmpL op1 zero));
 9026 
 9027   effect(USE op1, USE lbl);
 9028 
 9029   ins_cost(BRANCH_COST);
 9030 
 9031   format %{ "b$cmp  $op1, zr, $lbl\t#@cmpL_reg_imm0_loop" %}
 9032 
 9033   ins_encode %{
 9034     __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label));
 9035   %}
 9036 
 9037   ins_pipe(pipe_cmpz_branch);
 9038   ins_short_branch(1);
 9039 %}
 9040 
 9041 // Compare unsigned long with zero and branch near instructions
 9042 instruct cmpULEqNeLeGt_reg_imm0_branch(cmpOpUEqNeLeGt cmp, iRegL op1, immL0 zero, label lbl)
 9043 %{
 9044   // Same match rule as `far_cmpULEqNeLeGt_reg_imm0_branch'.
 9045   match(If cmp (CmpUL op1 zero));
 9046 
 9047   effect(USE op1, USE lbl);
 9048 
 9049   ins_cost(BRANCH_COST);
 9050 
 9051   format %{ "b$cmp  $op1, zr, $lbl\t#@cmpULEqNeLeGt_reg_imm0_branch" %}
 9052 
 9053   ins_encode %{
 9054     __ enc_cmpUEqNeLeGt_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
 9055   %}
 9056 
 9057   ins_pipe(pipe_cmpz_branch);
 9058   ins_short_branch(1);
 9059 %}
 9060 
 9061 instruct cmpULEqNeLeGt_reg_imm0_loop(cmpOpUEqNeLeGt cmp, iRegL op1, immL0 zero, label lbl)
 9062 %{
 9063   // Same match rule as `far_cmpULEqNeLeGt_reg_imm0_loop'.
 9064   match(CountedLoopEnd cmp (CmpUL op1 zero));
 9065 
 9066   effect(USE op1, USE lbl);
 9067 
 9068   ins_cost(BRANCH_COST);
 9069 
 9070   format %{ "b$cmp  $op1, zr, $lbl\t#@cmpULEqNeLeGt_reg_imm0_loop" %}
 9071 
 9072   ins_encode %{
 9073     __ enc_cmpUEqNeLeGt_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
 9074   %}
 9075 
 9076   ins_pipe(pipe_cmpz_branch);
 9077   ins_short_branch(1);
 9078 %}
 9079 
 9080 // Compare pointer with zero and branch near instructions
 9081 instruct cmpP_imm0_branch(cmpOpEqNe cmp, iRegP op1, immP0 zero, label lbl) %{
 9082   // Same match rule as `far_cmpP_reg_imm0_branch'.
 9083   match(If cmp (CmpP op1 zero));
 9084   effect(USE lbl);
 9085 
 9086   ins_cost(BRANCH_COST);
 9087   format %{ "b$cmp   $op1, zr, $lbl\t#@cmpP_imm0_branch" %}
 9088 
 9089   ins_encode %{
 9090     __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
 9091   %}
 9092 
 9093   ins_pipe(pipe_cmpz_branch);
 9094   ins_short_branch(1);
 9095 %}
 9096 
 9097 instruct cmpP_imm0_loop(cmpOpEqNe cmp, iRegP op1, immP0 zero, label lbl) %{
 9098   // Same match rule as `far_cmpP_reg_imm0_loop'.
 9099   match(CountedLoopEnd cmp (CmpP op1 zero));
 9100   effect(USE lbl);
 9101 
 9102   ins_cost(BRANCH_COST);
 9103   format %{ "b$cmp   $op1, zr, $lbl\t#@cmpP_imm0_loop" %}
 9104 
 9105   ins_encode %{
 9106     __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
 9107   %}
 9108 
 9109   ins_pipe(pipe_cmpz_branch);
 9110   ins_short_branch(1);
 9111 %}
 9112 
 9113 // Compare narrow pointer with zero and branch near instructions
 9114 instruct cmpN_imm0_branch(cmpOpEqNe cmp, iRegN op1, immN0 zero, label lbl) %{
 9115   // Same match rule as `far_cmpN_reg_imm0_branch'.
 9116   match(If cmp (CmpN op1 zero));
 9117   effect(USE lbl);
 9118 
 9119   ins_cost(BRANCH_COST);
 9120 
 9121   format %{ "b$cmp  $op1, zr, $lbl\t#@cmpN_imm0_branch" %}
 9122 
 9123   ins_encode %{
 9124     __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
 9125   %}
 9126 
 9127   ins_pipe(pipe_cmpz_branch);
 9128   ins_short_branch(1);
 9129 %}
 9130 
 9131 instruct cmpN_imm0_loop(cmpOpEqNe cmp, iRegN op1, immN0 zero, label lbl) %{
 9132   // Same match rule as `far_cmpN_reg_imm0_loop'.
 9133   match(CountedLoopEnd cmp (CmpN op1 zero));
 9134   effect(USE lbl);
 9135 
 9136   ins_cost(BRANCH_COST);
 9137 
 9138   format %{ "b$cmp  $op1, zr, $lbl\t#@cmpN_imm0_loop" %}
 9139 
 9140   ins_encode %{
 9141     __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
 9142   %}
 9143 
 9144   ins_pipe(pipe_cmpz_branch);
 9145   ins_short_branch(1);
 9146 %}
 9147 
 9148 // Compare narrow pointer with pointer zero and branch near instructions
 9149 instruct cmpP_narrowOop_imm0_branch(cmpOpEqNe cmp, iRegN op1, immP0 zero, label lbl) %{
 9150   // Same match rule as `far_cmpP_narrowOop_imm0_branch'.
 9151   match(If cmp (CmpP (DecodeN op1) zero));
 9152   effect(USE lbl);
 9153 
 9154   ins_cost(BRANCH_COST);
 9155   format %{ "b$cmp   $op1, zr, $lbl\t#@cmpP_narrowOop_imm0_branch" %}
 9156 
 9157   ins_encode %{
 9158     __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
 9159   %}
 9160 
 9161   ins_pipe(pipe_cmpz_branch);
 9162   ins_short_branch(1);
 9163 %}
 9164 
 9165 instruct cmpP_narrowOop_imm0_loop(cmpOpEqNe cmp, iRegN op1, immP0 zero, label lbl) %{
 9166   // Same match rule as `far_cmpP_narrowOop_imm0_loop'.
 9167   match(CountedLoopEnd cmp (CmpP (DecodeN op1) zero));
 9168   effect(USE lbl);
 9169 
 9170   ins_cost(BRANCH_COST);
 9171   format %{ "b$cmp   $op1, zr, $lbl\t#@cmpP_narrowOop_imm0_loop" %}
 9172 
 9173   ins_encode %{
 9174     __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
 9175   %}
 9176 
 9177   ins_pipe(pipe_cmpz_branch);
 9178   ins_short_branch(1);
 9179 %}
 9180 
 9181 // Patterns for far (20KiB) variants
 9182 
 9183 instruct far_cmpFlag_branch(cmpOp cmp, rFlagsReg cr, label lbl) %{
 9184   match(If cmp cr);
 9185   effect(USE lbl);
 9186 
 9187   ins_cost(BRANCH_COST);
 9188   format %{ "far_b$cmp $cr, zr, $lbl\t#@far_cmpFlag_branch"%}
 9189 
 9190   ins_encode %{
 9191     __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($cr$$reg), *($lbl$$label), /* is_far */ true);
 9192   %}
 9193 
 9194   ins_pipe(pipe_cmpz_branch);
 9195 %}
 9196 
 9197 // Compare signed int and branch far instructions
 9198 instruct far_cmpI_branch(cmpOp cmp, iRegI op1, iRegI op2, label lbl) %{
 9199   match(If cmp (CmpI op1 op2));
 9200   effect(USE lbl);
 9201 
 9202   ins_cost(BRANCH_COST * 2);
 9203 
 9204   // the format instruction [far_b$cmp] here is be used as two insructions
 9205   // in macroassembler: b$not_cmp(op1, op2, done), j($lbl), bind(done)
 9206   format %{ "far_b$cmp  $op1, $op2, $lbl\t#@far_cmpI_branch" %}
 9207 
 9208   ins_encode %{
 9209     __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
 9210   %}
 9211 
 9212   ins_pipe(pipe_cmp_branch);
 9213 %}
 9214 
 9215 instruct far_cmpI_loop(cmpOp cmp, iRegI op1, iRegI op2, label lbl) %{
 9216   match(CountedLoopEnd cmp (CmpI op1 op2));
 9217   effect(USE lbl);
 9218 
 9219   ins_cost(BRANCH_COST * 2);
 9220   format %{ "far_b$cmp  $op1, $op2, $lbl\t#@far_cmpI_loop" %}
 9221 
 9222   ins_encode %{
 9223     __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
 9224   %}
 9225 
 9226   ins_pipe(pipe_cmp_branch);
 9227 %}
 9228 
 9229 instruct far_cmpU_branch(cmpOpU cmp, iRegI op1, iRegI op2, label lbl) %{
 9230   match(If cmp (CmpU op1 op2));
 9231   effect(USE lbl);
 9232 
 9233   ins_cost(BRANCH_COST * 2);
 9234   format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpU_branch" %}
 9235 
 9236   ins_encode %{
 9237     __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
 9238                        as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
 9239   %}
 9240 
 9241   ins_pipe(pipe_cmp_branch);
 9242 %}
 9243 
 9244 instruct far_cmpU_loop(cmpOpU cmp, iRegI op1, iRegI op2, label lbl) %{
 9245   match(CountedLoopEnd cmp (CmpU op1 op2));
 9246   effect(USE lbl);
 9247 
 9248   ins_cost(BRANCH_COST * 2);
 9249   format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpU_loop" %}
 9250 
 9251   ins_encode %{
 9252     __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
 9253                        as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
 9254   %}
 9255 
 9256   ins_pipe(pipe_cmp_branch);
 9257 %}
 9258 
 9259 instruct far_cmpL_branch(cmpOp cmp, iRegL op1, iRegL op2, label lbl) %{
 9260   match(If cmp (CmpL op1 op2));
 9261   effect(USE lbl);
 9262 
 9263   ins_cost(BRANCH_COST * 2);
 9264   format %{ "far_b$cmp  $op1, $op2, $lbl\t#@far_cmpL_branch" %}
 9265 
 9266   ins_encode %{
 9267     __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
 9268   %}
 9269 
 9270   ins_pipe(pipe_cmp_branch);
 9271 %}
 9272 
 9273 instruct far_cmpLloop(cmpOp cmp, iRegL op1, iRegL op2, label lbl) %{
 9274   match(CountedLoopEnd cmp (CmpL op1 op2));
 9275   effect(USE lbl);
 9276 
 9277   ins_cost(BRANCH_COST * 2);
 9278   format %{ "far_b$cmp  $op1, $op2, $lbl\t#@far_cmpL_loop" %}
 9279 
 9280   ins_encode %{
 9281     __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
 9282   %}
 9283 
 9284   ins_pipe(pipe_cmp_branch);
 9285 %}
 9286 
 9287 instruct far_cmpUL_branch(cmpOpU cmp, iRegL op1, iRegL op2, label lbl) %{
 9288   match(If cmp (CmpUL op1 op2));
 9289   effect(USE lbl);
 9290 
 9291   ins_cost(BRANCH_COST * 2);
 9292   format %{ "far_b$cmp  $op1, $op2, $lbl\t#@far_cmpUL_branch" %}
 9293 
 9294   ins_encode %{
 9295     __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
 9296                        as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
 9297   %}
 9298 
 9299   ins_pipe(pipe_cmp_branch);
 9300 %}
 9301 
 9302 instruct far_cmpUL_loop(cmpOpU cmp, iRegL op1, iRegL op2, label lbl) %{
 9303   match(CountedLoopEnd cmp (CmpUL op1 op2));
 9304   effect(USE lbl);
 9305 
 9306   ins_cost(BRANCH_COST * 2);
 9307   format %{ "far_b$cmp  $op1, $op2, $lbl\t#@far_cmpUL_loop" %}
 9308 
 9309   ins_encode %{
 9310     __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
 9311                        as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
 9312   %}
 9313 
 9314   ins_pipe(pipe_cmp_branch);
 9315 %}
 9316 
 9317 instruct far_cmpP_branch(cmpOpU cmp, iRegP op1, iRegP op2, label lbl)
 9318 %{
 9319   match(If cmp (CmpP op1 op2));
 9320 
 9321   effect(USE lbl);
 9322 
 9323   ins_cost(BRANCH_COST * 2);
 9324 
 9325   format %{ "far_b$cmp  $op1, $op2, $lbl\t#@far_cmpP_branch" %}
 9326 
 9327   ins_encode %{
 9328     __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
 9329                        as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
 9330   %}
 9331 
 9332   ins_pipe(pipe_cmp_branch);
 9333 %}
 9334 
 9335 instruct far_cmpP_loop(cmpOpU cmp, iRegP op1, iRegP op2, label lbl)
 9336 %{
 9337   match(CountedLoopEnd cmp (CmpP op1 op2));
 9338 
 9339   effect(USE lbl);
 9340 
 9341   ins_cost(BRANCH_COST * 2);
 9342 
 9343   format %{ "far_b$cmp  $op1, $op2, $lbl\t#@far_cmpP_loop" %}
 9344 
 9345   ins_encode %{
 9346     __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
 9347                        as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
 9348   %}
 9349 
 9350   ins_pipe(pipe_cmp_branch);
 9351 %}
 9352 
 9353 instruct far_cmpN_branch(cmpOpU cmp, iRegN op1, iRegN op2, label lbl)
 9354 %{
 9355   match(If cmp (CmpN op1 op2));
 9356 
 9357   effect(USE lbl);
 9358 
 9359   ins_cost(BRANCH_COST * 2);
 9360 
 9361   format %{ "far_b$cmp  $op1, $op2, $lbl\t#@far_cmpN_branch" %}
 9362 
 9363   ins_encode %{
 9364     __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
 9365                        as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
 9366   %}
 9367 
 9368   ins_pipe(pipe_cmp_branch);
 9369 %}
 9370 
 9371 instruct far_cmpN_loop(cmpOpU cmp, iRegN op1, iRegN op2, label lbl)
 9372 %{
 9373   match(CountedLoopEnd cmp (CmpN op1 op2));
 9374 
 9375   effect(USE lbl);
 9376 
 9377   ins_cost(BRANCH_COST * 2);
 9378 
 9379   format %{ "far_b$cmp  $op1, $op2, $lbl\t#@far_cmpN_loop" %}
 9380 
 9381   ins_encode %{
 9382     __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
 9383                   as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
 9384   %}
 9385 
 9386   ins_pipe(pipe_cmp_branch);
 9387 %}
 9388 
 9389 // Float compare and branch instructions
 9390 instruct far_cmpF_branch(cmpOp cmp, fRegF op1, fRegF op2, label lbl)
 9391 %{
 9392   match(If cmp (CmpF op1 op2));
 9393 
 9394   effect(USE lbl);
 9395 
 9396   ins_cost(XFER_COST + BRANCH_COST * 2);
 9397   format %{ "far_float_b$cmp $op1, $op2, $lbl\t#@far_cmpF_branch"%}
 9398 
 9399   ins_encode %{
 9400     __ float_cmp_branch($cmp$$cmpcode, as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg),
 9401                         *($lbl$$label), /* is_far */ true);
 9402   %}
 9403 
 9404   ins_pipe(pipe_class_compare);
 9405 %}
 9406 
 9407 instruct far_cmpF_loop(cmpOp cmp, fRegF op1, fRegF op2, label lbl)
 9408 %{
 9409   match(CountedLoopEnd cmp (CmpF op1 op2));
 9410   effect(USE lbl);
 9411 
 9412   ins_cost(XFER_COST + BRANCH_COST * 2);
 9413   format %{ "far_float_b$cmp $op1, $op2, $lbl\t#@far_cmpF_loop"%}
 9414 
 9415   ins_encode %{
 9416     __ float_cmp_branch($cmp$$cmpcode, as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg),
 9417                         *($lbl$$label), /* is_far */ true);
 9418   %}
 9419 
 9420   ins_pipe(pipe_class_compare);
 9421 %}
 9422 
 9423 // Double compare and branch instructions
 9424 instruct far_cmpD_branch(cmpOp cmp, fRegD op1, fRegD op2, label lbl)
 9425 %{
 9426   match(If cmp (CmpD op1 op2));
 9427   effect(USE lbl);
 9428 
 9429   ins_cost(XFER_COST + BRANCH_COST * 2);
 9430   format %{ "far_double_b$cmp $op1, $op2, $lbl\t#@far_cmpD_branch"%}
 9431 
 9432   ins_encode %{
 9433     __ float_cmp_branch($cmp$$cmpcode | C2_MacroAssembler::double_branch_mask, as_FloatRegister($op1$$reg),
 9434                         as_FloatRegister($op2$$reg), *($lbl$$label), /* is_far */ true);
 9435   %}
 9436 
 9437   ins_pipe(pipe_class_compare);
 9438 %}
 9439 
 9440 instruct far_cmpD_loop(cmpOp cmp, fRegD op1, fRegD op2, label lbl)
 9441 %{
 9442   match(CountedLoopEnd cmp (CmpD op1 op2));
 9443   effect(USE lbl);
 9444 
 9445   ins_cost(XFER_COST + BRANCH_COST * 2);
 9446   format %{ "far_double_b$cmp $op1, $op2, $lbl\t#@far_cmpD_loop"%}
 9447 
 9448   ins_encode %{
 9449     __ float_cmp_branch($cmp$$cmpcode | C2_MacroAssembler::double_branch_mask, as_FloatRegister($op1$$reg),
 9450                         as_FloatRegister($op2$$reg), *($lbl$$label), /* is_far */ true);
 9451   %}
 9452 
 9453   ins_pipe(pipe_class_compare);
 9454 %}
 9455 
 9456 instruct far_cmpI_reg_imm0_branch(cmpOp cmp, iRegI op1, immI0 zero, label lbl)
 9457 %{
 9458   match(If cmp (CmpI op1 zero));
 9459 
 9460   effect(USE op1, USE lbl);
 9461 
 9462   ins_cost(BRANCH_COST * 2);
 9463 
 9464   format %{ "far_b$cmp  $op1, zr, $lbl\t#@far_cmpI_reg_imm0_branch" %}
 9465 
 9466   ins_encode %{
 9467     __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label), /* is_far */ true);
 9468   %}
 9469 
 9470   ins_pipe(pipe_cmpz_branch);
 9471 %}
 9472 
 9473 instruct far_cmpI_reg_imm0_loop(cmpOp cmp, iRegI op1, immI0 zero, label lbl)
 9474 %{
 9475   match(CountedLoopEnd cmp (CmpI op1 zero));
 9476 
 9477   effect(USE op1, USE lbl);
 9478 
 9479   ins_cost(BRANCH_COST * 2);
 9480 
 9481   format %{ "far_b$cmp  $op1, zr, $lbl\t#@far_cmpI_reg_imm0_loop" %}
 9482 
 9483   ins_encode %{
 9484     __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label), /* is_far */ true);
 9485   %}
 9486 
 9487   ins_pipe(pipe_cmpz_branch);
 9488 %}
 9489 
 9490 instruct far_cmpUEqNeLeGt_imm0_branch(cmpOpUEqNeLeGt cmp, iRegI op1, immI0 zero, label lbl)
 9491 %{
 9492   match(If cmp (CmpU op1 zero));
 9493 
 9494   effect(USE op1, USE lbl);
 9495 
 9496   ins_cost(BRANCH_COST * 2);
 9497 
 9498   format %{ "far_b$cmp  $op1, zr, $lbl\t#@far_cmpUEqNeLeGt_imm0_branch" %}
 9499 
 9500   ins_encode %{
 9501     __ enc_cmpUEqNeLeGt_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
 9502   %}
 9503 
 9504   ins_pipe(pipe_cmpz_branch);
 9505 %}
 9506 
 9507 instruct far_cmpUEqNeLeGt_reg_imm0_loop(cmpOpUEqNeLeGt cmp, iRegI op1, immI0 zero, label lbl)
 9508 %{
 9509   match(CountedLoopEnd cmp (CmpU op1 zero));
 9510 
 9511   effect(USE op1, USE lbl);
 9512 
 9513   ins_cost(BRANCH_COST * 2);
 9514 
 9515   format %{ "far_b$cmp  $op1, zr, $lbl\t#@far_cmpUEqNeLeGt_reg_imm0_loop" %}
 9516 
 9517 
 9518   ins_encode %{
 9519     __ enc_cmpUEqNeLeGt_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
 9520   %}
 9521 
 9522   ins_pipe(pipe_cmpz_branch);
 9523 %}
 9524 
 9525 // compare lt/ge unsigned instructs has no short instruct with same match
 9526 instruct far_cmpULtGe_reg_imm0_branch(cmpOpULtGe cmp, iRegI op1, immI0 zero, label lbl)
 9527 %{
 9528   match(If cmp (CmpU op1 zero));
 9529 
 9530   effect(USE op1, USE lbl);
 9531 
 9532   ins_cost(BRANCH_COST);
 9533 
 9534   format %{ "j  $lbl if $cmp == ge\t#@far_cmpULtGe_reg_imm0_branch" %}
 9535 
 9536   ins_encode(riscv_enc_far_cmpULtGe_imm0_branch(cmp, op1, lbl));
 9537 
 9538   ins_pipe(pipe_cmpz_branch);
 9539 %}
 9540 
 9541 instruct far_cmpULtGe_reg_imm0_loop(cmpOpULtGe cmp, iRegI op1, immI0 zero, label lbl)
 9542 %{
 9543   match(CountedLoopEnd cmp (CmpU op1 zero));
 9544 
 9545   effect(USE op1, USE lbl);
 9546 
 9547   ins_cost(BRANCH_COST);
 9548 
 9549   format %{ "j  $lbl if $cmp == ge\t#@far_cmpULtGe_reg_imm0_loop" %}
 9550 
 9551   ins_encode(riscv_enc_far_cmpULtGe_imm0_branch(cmp, op1, lbl));
 9552 
 9553   ins_pipe(pipe_cmpz_branch);
 9554 %}
 9555 
 9556 instruct far_cmpL_reg_imm0_branch(cmpOp cmp, iRegL op1, immL0 zero, label lbl)
 9557 %{
 9558   match(If cmp (CmpL op1 zero));
 9559 
 9560   effect(USE op1, USE lbl);
 9561 
 9562   ins_cost(BRANCH_COST * 2);
 9563 
 9564   format %{ "far_b$cmp  $op1, zr, $lbl\t#@far_cmpL_reg_imm0_branch" %}
 9565 
 9566   ins_encode %{
 9567     __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label), /* is_far */ true);
 9568   %}
 9569 
 9570   ins_pipe(pipe_cmpz_branch);
 9571 %}
 9572 
 9573 instruct far_cmpL_reg_imm0_loop(cmpOp cmp, iRegL op1, immL0 zero, label lbl)
 9574 %{
 9575   match(CountedLoopEnd cmp (CmpL op1 zero));
 9576 
 9577   effect(USE op1, USE lbl);
 9578 
 9579   ins_cost(BRANCH_COST * 2);
 9580 
 9581   format %{ "far_b$cmp  $op1, zr, $lbl\t#@far_cmpL_reg_imm0_loop" %}
 9582 
 9583   ins_encode %{
 9584     __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label), /* is_far */ true);
 9585   %}
 9586 
 9587   ins_pipe(pipe_cmpz_branch);
 9588 %}
 9589 
 9590 instruct far_cmpULEqNeLeGt_reg_imm0_branch(cmpOpUEqNeLeGt cmp, iRegL op1, immL0 zero, label lbl)
 9591 %{
 9592   match(If cmp (CmpUL op1 zero));
 9593 
 9594   effect(USE op1, USE lbl);
 9595 
 9596   ins_cost(BRANCH_COST * 2);
 9597 
 9598   format %{ "far_b$cmp  $op1, zr, $lbl\t#@far_cmpULEqNeLeGt_reg_imm0_branch" %}
 9599 
 9600   ins_encode %{
 9601     __ enc_cmpUEqNeLeGt_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
 9602   %}
 9603 
 9604   ins_pipe(pipe_cmpz_branch);
 9605 %}
 9606 
 9607 instruct far_cmpULEqNeLeGt_reg_imm0_loop(cmpOpUEqNeLeGt cmp, iRegL op1, immL0 zero, label lbl)
 9608 %{
 9609   match(CountedLoopEnd cmp (CmpUL op1 zero));
 9610 
 9611   effect(USE op1, USE lbl);
 9612 
 9613   ins_cost(BRANCH_COST * 2);
 9614 
 9615   format %{ "far_b$cmp  $op1, zr, $lbl\t#@far_cmpULEqNeLeGt_reg_imm0_loop" %}
 9616 
 9617   ins_encode %{
 9618     __ enc_cmpUEqNeLeGt_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
 9619   %}
 9620 
 9621   ins_pipe(pipe_cmpz_branch);
 9622 %}
 9623 
 9624 // compare lt/ge unsigned instructs has no short instruct with same match
 9625 instruct far_cmpULLtGe_reg_imm0_branch(cmpOpULtGe cmp, iRegL op1, immL0 zero, label lbl)
 9626 %{
 9627   match(If cmp (CmpUL op1 zero));
 9628 
 9629   effect(USE op1, USE lbl);
 9630 
 9631   ins_cost(BRANCH_COST);
 9632 
 9633   format %{ "j  $lbl if $cmp == ge\t#@far_cmpULLtGe_reg_imm0_branch" %}
 9634 
 9635   ins_encode(riscv_enc_far_cmpULtGe_imm0_branch(cmp, op1, lbl));
 9636 
 9637   ins_pipe(pipe_cmpz_branch);
 9638 %}
 9639 
 9640 instruct far_cmpULLtGe_reg_imm0_loop(cmpOpULtGe cmp, iRegL op1, immL0 zero, label lbl)
 9641 %{
 9642   match(CountedLoopEnd cmp (CmpUL op1 zero));
 9643 
 9644   effect(USE op1, USE lbl);
 9645 
 9646   ins_cost(BRANCH_COST);
 9647 
 9648   format %{ "j  $lbl if $cmp == ge\t#@far_cmpULLtGe_reg_imm0_loop" %}
 9649 
 9650   ins_encode(riscv_enc_far_cmpULtGe_imm0_branch(cmp, op1, lbl));
 9651 
 9652   ins_pipe(pipe_cmpz_branch);
 9653 %}
 9654 
 9655 instruct far_cmpP_imm0_branch(cmpOpEqNe cmp, iRegP op1, immP0 zero, label lbl) %{
 9656   match(If cmp (CmpP op1 zero));
 9657   effect(USE lbl);
 9658 
 9659   ins_cost(BRANCH_COST * 2);
 9660   format %{ "far_b$cmp   $op1, zr, $lbl\t#@far_cmpP_imm0_branch" %}
 9661 
 9662   ins_encode %{
 9663     __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
 9664   %}
 9665 
 9666   ins_pipe(pipe_cmpz_branch);
 9667 %}
 9668 
 9669 instruct far_cmpP_imm0_loop(cmpOpEqNe cmp, iRegP op1, immP0 zero, label lbl) %{
 9670   match(CountedLoopEnd cmp (CmpP op1 zero));
 9671   effect(USE lbl);
 9672 
 9673   ins_cost(BRANCH_COST * 2);
 9674   format %{ "far_b$cmp   $op1, zr, $lbl\t#@far_cmpP_imm0_loop" %}
 9675 
 9676   ins_encode %{
 9677     __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
 9678   %}
 9679 
 9680   ins_pipe(pipe_cmpz_branch);
 9681 %}
 9682 
 9683 instruct far_cmpN_imm0_branch(cmpOpEqNe cmp, iRegN op1, immN0 zero, label lbl) %{
 9684   match(If cmp (CmpN op1 zero));
 9685   effect(USE lbl);
 9686 
 9687   ins_cost(BRANCH_COST * 2);
 9688 
 9689   format %{ "far_b$cmp  $op1, zr, $lbl\t#@far_cmpN_imm0_branch" %}
 9690 
 9691   ins_encode %{
 9692     __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
 9693   %}
 9694 
 9695   ins_pipe(pipe_cmpz_branch);
 9696 %}
 9697 
 9698 instruct far_cmpN_imm0_loop(cmpOpEqNe cmp, iRegN op1, immN0 zero, label lbl) %{
 9699   match(CountedLoopEnd cmp (CmpN op1 zero));
 9700   effect(USE lbl);
 9701 
 9702   ins_cost(BRANCH_COST * 2);
 9703 
 9704   format %{ "far_b$cmp  $op1, zr, $lbl\t#@far_cmpN_imm0_loop" %}
 9705 
 9706   ins_encode %{
 9707     __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
 9708   %}
 9709 
 9710   ins_pipe(pipe_cmpz_branch);
 9711 %}
 9712 
 9713 instruct far_cmpP_narrowOop_imm0_branch(cmpOpEqNe cmp, iRegN op1, immP0 zero, label lbl) %{
 9714   match(If cmp (CmpP (DecodeN op1) zero));
 9715   effect(USE lbl);
 9716 
 9717   ins_cost(BRANCH_COST * 2);
 9718   format %{ "far_b$cmp   $op1, zr, $lbl\t#@far_cmpP_narrowOop_imm0_branch" %}
 9719 
 9720   ins_encode %{
 9721     __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
 9722   %}
 9723 
 9724   ins_pipe(pipe_cmpz_branch);
 9725 %}
 9726 
 9727 instruct far_cmpP_narrowOop_imm0_loop(cmpOpEqNe cmp, iRegN op1, immP0 zero, label lbl) %{
 9728   match(CountedLoopEnd cmp (CmpP (DecodeN op1) zero));
 9729   effect(USE lbl);
 9730 
 9731   ins_cost(BRANCH_COST * 2);
 9732   format %{ "far_b$cmp   $op1, zr, $lbl\t#@far_cmpP_narrowOop_imm0_loop" %}
 9733 
 9734   ins_encode %{
 9735     __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
 9736   %}
 9737 
 9738   ins_pipe(pipe_cmpz_branch);
 9739 %}
 9740 
 9741 // ============================================================================
 9742 // Conditional Move Instructions
 9743 instruct cmovI_cmpI(iRegINoSp dst, iRegI src, iRegI op1, iRegI op2, cmpOp cop) %{
 9744   match(Set dst (CMoveI (Binary cop (CmpI op1 op2)) (Binary dst src)));
 9745   ins_cost(ALU_COST + BRANCH_COST);
 9746 
 9747   format %{
 9748              "bneg$cop $op1, $op2, skip\t#@cmovI_cmpI\n\t"
 9749              "mv $dst, $src\n\t"
 9750              "skip:"
 9751          %}
 9752 
 9753   ins_encode %{
 9754     __ enc_cmove($cop$$cmpcode,
 9755                  as_Register($op1$$reg), as_Register($op2$$reg),
 9756                  as_Register($dst$$reg), as_Register($src$$reg));
 9757   %}
 9758 
 9759   ins_pipe(pipe_slow);
 9760 %}
 9761 
 9762 instruct cmovI_cmpU(iRegINoSp dst, iRegI src, iRegI op1, iRegI op2, cmpOpU cop) %{
 9763   match(Set dst (CMoveI (Binary cop (CmpU op1 op2)) (Binary dst src)));
 9764   ins_cost(ALU_COST + BRANCH_COST);
 9765 
 9766   format %{
 9767              "bneg$cop $op1, $op2, skip\t#@cmovI_cmpU\n\t"
 9768              "mv $dst, $src\n\t"
 9769              "skip:"
 9770          %}
 9771 
 9772   ins_encode %{
 9773     __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
 9774                  as_Register($op1$$reg), as_Register($op2$$reg),
 9775                  as_Register($dst$$reg), as_Register($src$$reg));
 9776   %}
 9777 
 9778   ins_pipe(pipe_slow);
 9779 %}
 9780 
 9781 instruct cmovI_cmpL(iRegINoSp dst, iRegI src, iRegL op1, iRegL op2, cmpOp cop) %{
 9782   match(Set dst (CMoveI (Binary cop (CmpL op1 op2)) (Binary dst src)));
 9783   ins_cost(ALU_COST + BRANCH_COST);
 9784 
 9785   format %{
 9786              "bneg$cop $op1, $op2, skip\t#@cmovI_cmpL\n\t"
 9787              "mv $dst, $src\n\t"
 9788              "skip:"
 9789          %}
 9790 
 9791   ins_encode %{
 9792     __ enc_cmove($cop$$cmpcode,
 9793                  as_Register($op1$$reg), as_Register($op2$$reg),
 9794                  as_Register($dst$$reg), as_Register($src$$reg));
 9795   %}
 9796 
 9797   ins_pipe(pipe_slow);
 9798 %}
 9799 
 9800 instruct cmovL_cmpL(iRegLNoSp dst, iRegL src, iRegL op1, iRegL op2, cmpOp cop) %{
 9801   match(Set dst (CMoveL (Binary cop (CmpL op1 op2)) (Binary dst src)));
 9802   ins_cost(ALU_COST + BRANCH_COST);
 9803 
 9804   format %{
 9805              "bneg$cop $op1, $op2, skip\t#@cmovL_cmpL\n\t"
 9806              "mv $dst, $src\n\t"
 9807              "skip:"
 9808          %}
 9809 
 9810   ins_encode %{
 9811     __ enc_cmove($cop$$cmpcode,
 9812                  as_Register($op1$$reg), as_Register($op2$$reg),
 9813                  as_Register($dst$$reg), as_Register($src$$reg));
 9814   %}
 9815 
 9816   ins_pipe(pipe_slow);
 9817 %}
 9818 
 9819 instruct cmovL_cmpUL(iRegLNoSp dst, iRegL src, iRegL op1, iRegL op2, cmpOpU cop) %{
 9820   match(Set dst (CMoveL (Binary cop (CmpUL op1 op2)) (Binary dst src)));
 9821   ins_cost(ALU_COST + BRANCH_COST);
 9822 
 9823   format %{
 9824              "bneg$cop $op1, $op2, skip\t#@cmovL_cmpUL\n\t"
 9825              "mv $dst, $src\n\t"
 9826              "skip:"
 9827          %}
 9828 
 9829   ins_encode %{
 9830     __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
 9831                  as_Register($op1$$reg), as_Register($op2$$reg),
 9832                  as_Register($dst$$reg), as_Register($src$$reg));
 9833   %}
 9834 
 9835   ins_pipe(pipe_slow);
 9836 %}
 9837 
 9838 instruct cmovI_cmpUL(iRegINoSp dst, iRegI src, iRegL op1, iRegL op2, cmpOpU cop) %{
 9839   match(Set dst (CMoveI (Binary cop (CmpUL op1 op2)) (Binary dst src)));
 9840   ins_cost(ALU_COST + BRANCH_COST);
 9841   format %{
 9842              "bneg$cop $op1, $op2\t#@cmovI_cmpUL\n\t"
 9843              "mv $dst, $src\n\t"
 9844              "skip:"
 9845          %}
 9846 
 9847   ins_encode %{
 9848     __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
 9849                  as_Register($op1$$reg), as_Register($op2$$reg),
 9850                  as_Register($dst$$reg), as_Register($src$$reg));
 9851   %}
 9852 
 9853   ins_pipe(pipe_slow);
 9854 %}
 9855 
 9856 
 9857 // ============================================================================
 9858 // Procedure Call/Return Instructions
 9859 
 9860 // Call Java Static Instruction
 9861 // Note: If this code changes, the corresponding ret_addr_offset() and
 9862 //       compute_padding() functions will have to be adjusted.
 9863 instruct CallStaticJavaDirect(method meth)
 9864 %{
 9865   match(CallStaticJava);
 9866 
 9867   effect(USE meth);
 9868 
 9869   ins_cost(BRANCH_COST);
 9870 
 9871   format %{ "CALL,static $meth\t#@CallStaticJavaDirect" %}
 9872 
 9873   ins_encode(riscv_enc_java_static_call(meth),
 9874              riscv_enc_call_epilog);
 9875 
 9876   ins_pipe(pipe_class_call);
 9877   ins_alignment(4);
 9878 %}
 9879 
 9880 // TO HERE
 9881 
 9882 // Call Java Dynamic Instruction
 9883 // Note: If this code changes, the corresponding ret_addr_offset() and
 9884 //       compute_padding() functions will have to be adjusted.
 9885 instruct CallDynamicJavaDirect(method meth, rFlagsReg cr)
 9886 %{
 9887   match(CallDynamicJava);
 9888 
 9889   effect(USE meth, KILL cr);
 9890 
 9891   ins_cost(BRANCH_COST + ALU_COST * 6);
 9892 
 9893   format %{ "CALL,dynamic $meth\t#@CallDynamicJavaDirect" %}
 9894 
 9895   ins_encode(riscv_enc_java_dynamic_call(meth),
 9896              riscv_enc_call_epilog);
 9897 
 9898   ins_pipe(pipe_class_call);
 9899   ins_alignment(4);
 9900 %}
 9901 
 9902 // Call Runtime Instruction
 9903 
 9904 instruct CallRuntimeDirect(method meth, rFlagsReg cr)
 9905 %{
 9906   match(CallRuntime);
 9907 
 9908   effect(USE meth, KILL cr);
 9909 
 9910   ins_cost(BRANCH_COST);
 9911 
 9912   format %{ "CALL, runtime $meth\t#@CallRuntimeDirect" %}
 9913 
 9914   ins_encode(riscv_enc_java_to_runtime(meth));
 9915 
 9916   ins_pipe(pipe_class_call);
 9917 %}
 9918 
 9919 // Call Runtime Instruction
 9920 
 9921 instruct CallLeafDirect(method meth, rFlagsReg cr)
 9922 %{
 9923   match(CallLeaf);
 9924 
 9925   effect(USE meth, KILL cr);
 9926 
 9927   ins_cost(BRANCH_COST);
 9928 
 9929   format %{ "CALL, runtime leaf $meth\t#@CallLeafDirect" %}
 9930 
 9931   ins_encode(riscv_enc_java_to_runtime(meth));
 9932 
 9933   ins_pipe(pipe_class_call);
 9934 %}
 9935 
 9936 // Call Runtime Instruction
 9937 
 9938 instruct CallLeafNoFPDirect(method meth, rFlagsReg cr)
 9939 %{
 9940   match(CallLeafNoFP);
 9941 
 9942   effect(USE meth, KILL cr);
 9943 
 9944   ins_cost(BRANCH_COST);
 9945 
 9946   format %{ "CALL, runtime leaf nofp $meth\t#@CallLeafNoFPDirect" %}
 9947 
 9948   ins_encode(riscv_enc_java_to_runtime(meth));
 9949 
 9950   ins_pipe(pipe_class_call);
 9951 %}
 9952 
 9953 // ============================================================================
 9954 // Partial Subtype Check
 9955 //
 9956 // superklass array for an instance of the superklass.  Set a hidden
 9957 // internal cache on a hit (cache is checked with exposed code in
 9958 // gen_subtype_check()).  Return zero for a hit.  The encoding
 9959 // ALSO sets flags.
 9960 
 9961 instruct partialSubtypeCheck(iRegP_R15 result, iRegP_R14 sub, iRegP_R10 super, iRegP_R12 tmp, rFlagsReg cr)
 9962 %{
 9963   match(Set result (PartialSubtypeCheck sub super));
 9964   effect(KILL tmp, KILL cr);
 9965 
 9966   ins_cost(2 * STORE_COST + 3 * LOAD_COST + 4 * ALU_COST + BRANCH_COST * 4);
 9967   format %{ "partialSubtypeCheck $result, $sub, $super\t#@partialSubtypeCheck" %}
 9968 
 9969   ins_encode(riscv_enc_partial_subtype_check(sub, super, tmp, result));
 9970 
 9971   opcode(0x1); // Force zero of result reg on hit
 9972 
 9973   ins_pipe(pipe_class_memory);
 9974 %}
 9975 
 9976 instruct partialSubtypeCheckVsZero(iRegP_R15 result, iRegP_R14 sub, iRegP_R10 super, iRegP_R12 tmp,
 9977                                    immP0 zero, rFlagsReg cr)
 9978 %{
 9979   match(Set cr (CmpP (PartialSubtypeCheck sub super) zero));
 9980   effect(KILL tmp, KILL result);
 9981 
 9982   ins_cost(2 * STORE_COST + 3 * LOAD_COST + 4 * ALU_COST + BRANCH_COST * 4);
 9983   format %{ "partialSubtypeCheck $result, $sub, $super == 0\t#@partialSubtypeCheckVsZero" %}
 9984 
 9985   ins_encode(riscv_enc_partial_subtype_check(sub, super, tmp, result));
 9986 
 9987   opcode(0x0); // Don't zero result reg on hit
 9988 
 9989   ins_pipe(pipe_class_memory);
 9990 %}
 9991 
 9992 instruct string_compareU(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
 9993                          iRegI_R10 result, iRegP_R28 tmp1, iRegL_R29 tmp2, iRegL_R30 tmp3, rFlagsReg cr)
 9994 %{
 9995   predicate(!UseRVV && ((StrCompNode *)n)->encoding() == StrIntrinsicNode::UU);
 9996   match(Set result (StrComp(Binary str1 cnt1)(Binary str2 cnt2)));
 9997   effect(KILL tmp1, KILL tmp2, KILL tmp3, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
 9998 
 9999   format %{ "String Compare $str1, $cnt1, $str2, $cnt2 -> $result\t#@string_compareU" %}
10000   ins_encode %{
10001     // Count is in 8-bit bytes; non-Compact chars are 16 bits.
10002     __ string_compare($str1$$Register, $str2$$Register,
10003                       $cnt1$$Register, $cnt2$$Register, $result$$Register,
10004                       $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
10005                       StrIntrinsicNode::UU);
10006   %}
10007   ins_pipe(pipe_class_memory);
10008 %}
10009 
10010 instruct string_compareL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
10011                          iRegI_R10 result, iRegP_R28 tmp1, iRegL_R29 tmp2, iRegL_R30 tmp3, rFlagsReg cr)
10012 %{
10013   predicate(!UseRVV && ((StrCompNode *)n)->encoding() == StrIntrinsicNode::LL);
10014   match(Set result (StrComp(Binary str1 cnt1)(Binary str2 cnt2)));
10015   effect(KILL tmp1, KILL tmp2, KILL tmp3, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
10016 
10017   format %{ "String Compare $str1, $cnt1, $str2, $cnt2 -> $result\t#@string_compareL" %}
10018   ins_encode %{
10019     __ string_compare($str1$$Register, $str2$$Register,
10020                       $cnt1$$Register, $cnt2$$Register, $result$$Register,
10021                       $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
10022                       StrIntrinsicNode::LL);
10023   %}
10024   ins_pipe(pipe_class_memory);
10025 %}
10026 
10027 instruct string_compareUL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
10028                           iRegI_R10 result, iRegP_R28 tmp1, iRegL_R29 tmp2, iRegL_R30 tmp3, rFlagsReg cr)
10029 %{
10030   predicate(!UseRVV && ((StrCompNode *)n)->encoding() == StrIntrinsicNode::UL);
10031   match(Set result (StrComp(Binary str1 cnt1)(Binary str2 cnt2)));
10032   effect(KILL tmp1, KILL tmp2, KILL tmp3, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
10033 
10034   format %{"String Compare $str1, $cnt1, $str2, $cnt2 -> $result\t#@string_compareUL" %}
10035   ins_encode %{
10036     __ string_compare($str1$$Register, $str2$$Register,
10037                       $cnt1$$Register, $cnt2$$Register, $result$$Register,
10038                       $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
10039                       StrIntrinsicNode::UL);
10040   %}
10041   ins_pipe(pipe_class_memory);
10042 %}
10043 
10044 instruct string_compareLU(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
10045                           iRegI_R10 result, iRegP_R28 tmp1, iRegL_R29 tmp2, iRegL_R30 tmp3,
10046                           rFlagsReg cr)
10047 %{
10048   predicate(!UseRVV && ((StrCompNode *)n)->encoding() == StrIntrinsicNode::LU);
10049   match(Set result (StrComp(Binary str1 cnt1)(Binary str2 cnt2)));
10050   effect(KILL tmp1, KILL tmp2, KILL tmp3, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
10051 
10052   format %{ "String Compare $str1, $cnt1, $str2, $cnt2 -> $result\t#@string_compareLU" %}
10053   ins_encode %{
10054     __ string_compare($str1$$Register, $str2$$Register,
10055                       $cnt1$$Register, $cnt2$$Register, $result$$Register,
10056                       $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
10057                       StrIntrinsicNode::LU);
10058   %}
10059   ins_pipe(pipe_class_memory);
10060 %}
10061 
10062 instruct string_indexofUU(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
10063                           iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3,
10064                           iRegINoSp tmp4, iRegINoSp tmp5, iRegINoSp tmp6, rFlagsReg cr)
10065 %{
10066   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU);
10067   match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
10068   effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, TEMP_DEF result,
10069          TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, TEMP tmp6, KILL cr);
10070 
10071   format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result (UU)" %}
10072   ins_encode %{
10073     __ string_indexof($str1$$Register, $str2$$Register,
10074                       $cnt1$$Register, $cnt2$$Register,
10075                       $tmp1$$Register, $tmp2$$Register,
10076                       $tmp3$$Register, $tmp4$$Register,
10077                       $tmp5$$Register, $tmp6$$Register,
10078                       $result$$Register, StrIntrinsicNode::UU);
10079   %}
10080   ins_pipe(pipe_class_memory);
10081 %}
10082 
10083 instruct string_indexofLL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
10084                           iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3,
10085                           iRegINoSp tmp4, iRegINoSp tmp5, iRegINoSp tmp6, rFlagsReg cr)
10086 %{
10087   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL);
10088   match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
10089   effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, TEMP_DEF result,
10090          TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, TEMP tmp6, KILL cr);
10091 
10092   format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result (LL)" %}
10093   ins_encode %{
10094     __ string_indexof($str1$$Register, $str2$$Register,
10095                       $cnt1$$Register, $cnt2$$Register,
10096                       $tmp1$$Register, $tmp2$$Register,
10097                       $tmp3$$Register, $tmp4$$Register,
10098                       $tmp5$$Register, $tmp6$$Register,
10099                       $result$$Register, StrIntrinsicNode::LL);
10100   %}
10101   ins_pipe(pipe_class_memory);
10102 %}
10103 
10104 instruct string_indexofUL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
10105                           iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3,
10106                           iRegINoSp tmp4, iRegINoSp tmp5, iRegINoSp tmp6, rFlagsReg cr)
10107 %{
10108   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL);
10109   match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
10110   effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, TEMP_DEF result,
10111          TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, TEMP tmp6, KILL cr);
10112   format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result (UL)" %}
10113 
10114   ins_encode %{
10115     __ string_indexof($str1$$Register, $str2$$Register,
10116                       $cnt1$$Register, $cnt2$$Register,
10117                       $tmp1$$Register, $tmp2$$Register,
10118                       $tmp3$$Register, $tmp4$$Register,
10119                       $tmp5$$Register, $tmp6$$Register,
10120                       $result$$Register, StrIntrinsicNode::UL);
10121   %}
10122   ins_pipe(pipe_class_memory);
10123 %}
10124 
10125 instruct string_indexof_conUU(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2,
10126                               immI_le_4 int_cnt2, iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2,
10127                               iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
10128 %{
10129   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU);
10130   match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
10131   effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, TEMP_DEF result,
10132          TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
10133 
10134   format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result (UU)" %}
10135 
10136   ins_encode %{
10137     int icnt2 = (int)$int_cnt2$$constant;
10138     __ string_indexof_linearscan($str1$$Register, $str2$$Register,
10139                                  $cnt1$$Register, zr,
10140                                  $tmp1$$Register, $tmp2$$Register,
10141                                  $tmp3$$Register, $tmp4$$Register,
10142                                  icnt2, $result$$Register, StrIntrinsicNode::UU);
10143   %}
10144   ins_pipe(pipe_class_memory);
10145 %}
10146 
10147 instruct string_indexof_conLL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2,
10148                               immI_le_4 int_cnt2, iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2,
10149                               iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
10150 %{
10151   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL);
10152   match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
10153   effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, TEMP_DEF result,
10154          TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
10155 
10156   format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result (LL)" %}
10157   ins_encode %{
10158     int icnt2 = (int)$int_cnt2$$constant;
10159     __ string_indexof_linearscan($str1$$Register, $str2$$Register,
10160                                  $cnt1$$Register, zr,
10161                                  $tmp1$$Register, $tmp2$$Register,
10162                                  $tmp3$$Register, $tmp4$$Register,
10163                                  icnt2, $result$$Register, StrIntrinsicNode::LL);
10164   %}
10165   ins_pipe(pipe_class_memory);
10166 %}
10167 
10168 instruct string_indexof_conUL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2,
10169                               immI_1 int_cnt2, iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2,
10170                               iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
10171 %{
10172   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL);
10173   match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
10174   effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, TEMP_DEF result,
10175          TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
10176 
10177   format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result (UL)" %}
10178   ins_encode %{
10179     int icnt2 = (int)$int_cnt2$$constant;
10180     __ string_indexof_linearscan($str1$$Register, $str2$$Register,
10181                                  $cnt1$$Register, zr,
10182                                  $tmp1$$Register, $tmp2$$Register,
10183                                  $tmp3$$Register, $tmp4$$Register,
10184                                  icnt2, $result$$Register, StrIntrinsicNode::UL);
10185   %}
10186   ins_pipe(pipe_class_memory);
10187 %}
10188 
10189 instruct stringU_indexof_char(iRegP_R11 str1, iRegI_R12 cnt1, iRegI_R13 ch,
10190                               iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2,
10191                               iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
10192 %{
10193   match(Set result (StrIndexOfChar (Binary str1 cnt1) ch));
10194   predicate(!UseRVV && (((StrIndexOfCharNode*)n)->encoding() == StrIntrinsicNode::U));
10195   effect(USE_KILL str1, USE_KILL cnt1, USE_KILL ch, TEMP_DEF result,
10196          TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
10197 
10198   format %{ "StringUTF16 IndexOf char[] $str1,$cnt1,$ch -> $result" %}
10199   ins_encode %{
10200     __ string_indexof_char($str1$$Register, $cnt1$$Register, $ch$$Register,
10201                            $result$$Register, $tmp1$$Register, $tmp2$$Register,
10202                            $tmp3$$Register, $tmp4$$Register, false /* isU */);
10203   %}
10204   ins_pipe(pipe_class_memory);
10205 %}
10206 
10207 
10208 instruct stringL_indexof_char(iRegP_R11 str1, iRegI_R12 cnt1, iRegI_R13 ch,
10209                               iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2,
10210                               iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
10211 %{
10212   match(Set result (StrIndexOfChar (Binary str1 cnt1) ch));
10213   predicate(!UseRVV && (((StrIndexOfCharNode*)n)->encoding() == StrIntrinsicNode::L));
10214   effect(USE_KILL str1, USE_KILL cnt1, USE_KILL ch, TEMP_DEF result,
10215          TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
10216 
10217   format %{ "StringUTF16 IndexOf char[] $str1,$cnt1,$ch -> $result" %}
10218   ins_encode %{
10219     __ string_indexof_char($str1$$Register, $cnt1$$Register, $ch$$Register,
10220                            $result$$Register, $tmp1$$Register, $tmp2$$Register,
10221                            $tmp3$$Register, $tmp4$$Register, true /* isL */);
10222   %}
10223   ins_pipe(pipe_class_memory);
10224 %}
10225 
10226 // clearing of an array
10227 instruct clearArray_reg_reg(iRegL_R29 cnt, iRegP_R28 base, Universe dummy)
10228 %{
10229   predicate(!UseRVV);
10230   match(Set dummy (ClearArray cnt base));
10231   effect(USE_KILL cnt, USE_KILL base);
10232 
10233   ins_cost(4 * DEFAULT_COST);
10234   format %{ "ClearArray $cnt, $base\t#@clearArray_reg_reg" %}
10235 
10236   ins_encode %{
10237     address tpc = __ zero_words($base$$Register, $cnt$$Register);
10238     if (tpc == NULL) {
10239       ciEnv::current()->record_failure("CodeCache is full");
10240       return;
10241     }
10242   %}
10243 
10244   ins_pipe(pipe_class_memory);
10245 %}
10246 
10247 instruct clearArray_imm_reg(immL cnt, iRegP_R28 base, Universe dummy, rFlagsReg cr)
10248 %{
10249   predicate(!UseRVV && (uint64_t)n->in(2)->get_long()
10250             < (uint64_t)(BlockZeroingLowLimit >> LogBytesPerWord));
10251   match(Set dummy (ClearArray cnt base));
10252   effect(USE_KILL base, KILL cr);
10253 
10254   ins_cost(4 * DEFAULT_COST);
10255   format %{ "ClearArray $cnt, $base\t#@clearArray_imm_reg" %}
10256 
10257   ins_encode %{
10258     __ zero_words($base$$Register, (uint64_t)$cnt$$constant);
10259   %}
10260 
10261   ins_pipe(pipe_class_memory);
10262 %}
10263 
10264 instruct string_equalsL(iRegP_R11 str1, iRegP_R13 str2, iRegI_R14 cnt,
10265                         iRegI_R10 result, rFlagsReg cr)
10266 %{
10267   predicate(!UseRVV && ((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::LL);
10268   match(Set result (StrEquals (Binary str1 str2) cnt));
10269   effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL cr);
10270 
10271   format %{ "String Equals $str1, $str2, $cnt -> $result\t#@string_equalsL" %}
10272   ins_encode %{
10273     // Count is in 8-bit bytes; non-Compact chars are 16 bits.
10274     __ string_equals($str1$$Register, $str2$$Register,
10275                      $result$$Register, $cnt$$Register, 1);
10276   %}
10277   ins_pipe(pipe_class_memory);
10278 %}
10279 
10280 instruct string_equalsU(iRegP_R11 str1, iRegP_R13 str2, iRegI_R14 cnt,
10281                         iRegI_R10 result, rFlagsReg cr)
10282 %{
10283   predicate(!UseRVV && ((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::UU);
10284   match(Set result (StrEquals (Binary str1 str2) cnt));
10285   effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL cr);
10286 
10287   format %{ "String Equals $str1, $str2, $cnt -> $result\t#@string_equalsU" %}
10288   ins_encode %{
10289     // Count is in 8-bit bytes; non-Compact chars are 16 bits.
10290     __ string_equals($str1$$Register, $str2$$Register,
10291                      $result$$Register, $cnt$$Register, 2);
10292   %}
10293   ins_pipe(pipe_class_memory);
10294 %}
10295 
10296 instruct array_equalsB(iRegP_R11 ary1, iRegP_R12 ary2, iRegI_R10 result,
10297                        iRegP_R13 tmp1, iRegP_R14 tmp2, iRegP_R15 tmp3,
10298                        iRegP_R16 tmp4, iRegP_R28 tmp5, rFlagsReg cr)
10299 %{
10300   predicate(!UseRVV && ((AryEqNode*)n)->encoding() == StrIntrinsicNode::LL);
10301   match(Set result (AryEq ary1 ary2));
10302   effect(USE_KILL ary1, USE_KILL ary2, TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL tmp5, KILL cr);
10303 
10304   format %{ "Array Equals $ary1, ary2 -> $result\t#@array_equalsB // KILL $tmp5" %}
10305   ins_encode %{
10306     __ arrays_equals($ary1$$Register, $ary2$$Register,
10307                      $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register,
10308                      $result$$Register, $tmp5$$Register, 1);
10309   %}
10310   ins_pipe(pipe_class_memory);
10311 %}
10312 
10313 instruct array_equalsC(iRegP_R11 ary1, iRegP_R12 ary2, iRegI_R10 result,
10314                        iRegP_R13 tmp1, iRegP_R14 tmp2, iRegP_R15 tmp3,
10315                        iRegP_R16 tmp4, iRegP_R28 tmp5, rFlagsReg cr)
10316 %{
10317   predicate(!UseRVV && ((AryEqNode*)n)->encoding() == StrIntrinsicNode::UU);
10318   match(Set result (AryEq ary1 ary2));
10319   effect(USE_KILL ary1, USE_KILL ary2, TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL tmp5, KILL cr);
10320 
10321   format %{ "Array Equals $ary1, ary2 -> $result\t#@array_equalsC // KILL $tmp5" %}
10322   ins_encode %{
10323     __ arrays_equals($ary1$$Register, $ary2$$Register,
10324                      $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register,
10325                      $result$$Register, $tmp5$$Register, 2);
10326   %}
10327   ins_pipe(pipe_class_memory);
10328 %}
10329 
10330 // ============================================================================
10331 // Safepoint Instructions
10332 
10333 instruct safePoint(iRegP poll)
10334 %{
10335   match(SafePoint poll);
10336 
10337   ins_cost(2 * LOAD_COST);
10338   format %{
10339     "lwu zr, [$poll]\t# Safepoint: poll for GC, #@safePoint"
10340   %}
10341   ins_encode %{
10342     __ read_polling_page(as_Register($poll$$reg), 0, relocInfo::poll_type);
10343   %}
10344   ins_pipe(pipe_serial); // ins_pipe(iload_reg_mem);
10345 %}
10346 
10347 // ============================================================================
10348 // This name is KNOWN by the ADLC and cannot be changed.
10349 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
10350 // for this guy.
10351 instruct tlsLoadP(javaThread_RegP dst)
10352 %{
10353   match(Set dst (ThreadLocal));
10354 
10355   ins_cost(0);
10356 
10357   format %{ " -- \t// $dst=Thread::current(), empty, #@tlsLoadP" %}
10358 
10359   size(0);
10360 
10361   ins_encode( /*empty*/ );
10362 
10363   ins_pipe(pipe_class_empty);
10364 %}
10365 
10366 // inlined locking and unlocking
10367 // using t1 as the 'flag' register to bridge the BoolNode producers and consumers
10368 instruct cmpFastLock(rFlagsReg cr, iRegP object, iRegP box, iRegPNoSp tmp1, iRegPNoSp tmp2)
10369 %{
10370   match(Set cr (FastLock object));
10371   effect(TEMP box, TEMP tmp1, TEMP tmp2);
10372 
10373   ins_cost(LOAD_COST * 2 + STORE_COST * 3 + ALU_COST * 6 + BRANCH_COST * 3);
10374   format %{ "fastlock $object,$box\t! kills $tmp1,$tmp2, #@cmpFastLock" %}
10375 
10376   ins_encode(riscv_enc_fast_lock(object, box, tmp1, tmp2));
10377 
10378   ins_pipe(pipe_serial);
10379 %}
10380 
10381 // using t1 as the 'flag' register to bridge the BoolNode producers and consumers
10382 instruct cmpFastUnlock(rFlagsReg cr, iRegP object, iRegP box, iRegPNoSp tmp1, iRegPNoSp tmp2)
10383 %{
10384   match(Set cr (FastUnlock object));
10385   effect(TEMP box, TEMP tmp1, TEMP tmp2);
10386 
10387   ins_cost(LOAD_COST * 2 + STORE_COST + ALU_COST * 2 + BRANCH_COST * 4);
10388   format %{ "fastunlock $object,$box\t! kills $tmp1, $tmp2, #@cmpFastUnlock" %}
10389 
10390   ins_encode(riscv_enc_fast_unlock(object, box, tmp1, tmp2));
10391 
10392   ins_pipe(pipe_serial);
10393 %}
10394 
10395 // Tail Call; Jump from runtime stub to Java code.
10396 // Also known as an 'interprocedural jump'.
10397 // Target of jump will eventually return to caller.
10398 // TailJump below removes the return address.
10399 instruct TailCalljmpInd(iRegPNoSp jump_target, inline_cache_RegP method_oop)
10400 %{
10401   match(TailCall jump_target method_oop);
10402 
10403   ins_cost(BRANCH_COST);
10404 
10405   format %{ "jalr $jump_target\t# $method_oop holds method oop, #@TailCalljmpInd." %}
10406 
10407   ins_encode(riscv_enc_tail_call(jump_target));
10408 
10409   ins_pipe(pipe_class_call);
10410 %}
10411 
10412 instruct TailjmpInd(iRegPNoSp jump_target, iRegP_R10 ex_oop)
10413 %{
10414   match(TailJump jump_target ex_oop);
10415 
10416   ins_cost(ALU_COST + BRANCH_COST);
10417 
10418   format %{ "jalr $jump_target\t# $ex_oop holds exception oop, #@TailjmpInd." %}
10419 
10420   ins_encode(riscv_enc_tail_jmp(jump_target));
10421 
10422   ins_pipe(pipe_class_call);
10423 %}
10424 
10425 // Create exception oop: created by stack-crawling runtime code.
10426 // Created exception is now available to this handler, and is setup
10427 // just prior to jumping to this handler. No code emitted.
10428 instruct CreateException(iRegP_R10 ex_oop)
10429 %{
10430   match(Set ex_oop (CreateEx));
10431 
10432   ins_cost(0);
10433   format %{ " -- \t// exception oop; no code emitted, #@CreateException" %}
10434 
10435   size(0);
10436 
10437   ins_encode( /*empty*/ );
10438 
10439   ins_pipe(pipe_class_empty);
10440 %}
10441 
10442 // Rethrow exception: The exception oop will come in the first
10443 // argument position. Then JUMP (not call) to the rethrow stub code.
10444 instruct RethrowException()
10445 %{
10446   match(Rethrow);
10447 
10448   ins_cost(BRANCH_COST);
10449 
10450   format %{ "j rethrow_stub\t#@RethrowException" %}
10451 
10452   ins_encode(riscv_enc_rethrow());
10453 
10454   ins_pipe(pipe_class_call);
10455 %}
10456 
10457 // Return Instruction
10458 // epilog node loads ret address into ra as part of frame pop
10459 instruct Ret()
10460 %{
10461   match(Return);
10462 
10463   ins_cost(BRANCH_COST);
10464   format %{ "ret\t// return register, #@Ret" %}
10465 
10466   ins_encode(riscv_enc_ret());
10467 
10468   ins_pipe(pipe_branch);
10469 %}
10470 
10471 // Die now.
10472 instruct ShouldNotReachHere() %{
10473   match(Halt);
10474 
10475   ins_cost(BRANCH_COST);
10476 
10477   format %{ "#@ShouldNotReachHere" %}
10478 
10479   ins_encode %{
10480     if (is_reachable()) {
10481       __ stop(_halt_reason);
10482     }
10483   %}
10484 
10485   ins_pipe(pipe_class_default);
10486 %}
10487 
10488 
10489 //----------PEEPHOLE RULES-----------------------------------------------------
10490 // These must follow all instruction definitions as they use the names
10491 // defined in the instructions definitions.
10492 //
10493 // peepmatch ( root_instr_name [preceding_instruction]* );
10494 //
10495 // peepconstraint %{
10496 // (instruction_number.operand_name relational_op instruction_number.operand_name
10497 //  [, ...] );
10498 // // instruction numbers are zero-based using left to right order in peepmatch
10499 //
10500 // peepreplace ( instr_name  ( [instruction_number.operand_name]* ) );
10501 // // provide an instruction_number.operand_name for each operand that appears
10502 // // in the replacement instruction's match rule
10503 //
10504 // ---------VM FLAGS---------------------------------------------------------
10505 //
10506 // All peephole optimizations can be turned off using -XX:-OptoPeephole
10507 //
10508 // Each peephole rule is given an identifying number starting with zero and
10509 // increasing by one in the order seen by the parser.  An individual peephole
10510 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
10511 // on the command-line.
10512 //
10513 // ---------CURRENT LIMITATIONS----------------------------------------------
10514 //
10515 // Only match adjacent instructions in same basic block
10516 // Only equality constraints
10517 // Only constraints between operands, not (0.dest_reg == RAX_enc)
10518 // Only one replacement instruction
10519 //
10520 //----------SMARTSPILL RULES---------------------------------------------------
10521 // These must follow all instruction definitions as they use the names
10522 // defined in the instructions definitions.
10523 
10524 // Local Variables:
10525 // mode: c++
10526 // End: