1 //
    2 // Copyright (c) 2003, 2024, Oracle and/or its affiliates. All rights reserved.
    3 // Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
    4 // Copyright (c) 2020, 2024, Huawei Technologies Co., Ltd. All rights reserved.
    5 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
    6 //
    7 // This code is free software; you can redistribute it and/or modify it
    8 // under the terms of the GNU General Public License version 2 only, as
    9 // published by the Free Software Foundation.
   10 //
   11 // This code is distributed in the hope that it will be useful, but WITHOUT
   12 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
   13 // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
   14 // version 2 for more details (a copy is included in the LICENSE file that
   15 // accompanied this code).
   16 //
   17 // You should have received a copy of the GNU General Public License version
   18 // 2 along with this work; if not, write to the Free Software Foundation,
   19 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
   20 //
   21 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
   22 // or visit www.oracle.com if you need additional information or have any
   23 // questions.
   24 //
   25 //
   26 
   27 // RISCV Architecture Description File
   28 
   29 //----------REGISTER DEFINITION BLOCK------------------------------------------
   30 // This information is used by the matcher and the register allocator to
   31 // describe individual registers and classes of registers within the target
   32 // architecture.
   33 
   34 register %{
   35 //----------Architecture Description Register Definitions----------------------
   36 // General Registers
   37 // "reg_def"  name ( register save type, C convention save type,
   38 //                   ideal register type, encoding );
   39 // Register Save Types:
   40 //
   41 // NS  = No-Save:       The register allocator assumes that these registers
   42 //                      can be used without saving upon entry to the method, &
   43 //                      that they do not need to be saved at call sites.
   44 //
   45 // SOC = Save-On-Call:  The register allocator assumes that these registers
   46 //                      can be used without saving upon entry to the method,
   47 //                      but that they must be saved at call sites.
   48 //
   49 // SOE = Save-On-Entry: The register allocator assumes that these registers
   50 //                      must be saved before using them upon entry to the
   51 //                      method, but they do not need to be saved at call
   52 //                      sites.
   53 //
   54 // AS  = Always-Save:   The register allocator assumes that these registers
   55 //                      must be saved before using them upon entry to the
   56 //                      method, & that they must be saved at call sites.
   57 //
   58 // Ideal Register Type is used to determine how to save & restore a
   59 // register.  Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
   60 // spilled with LoadP/StoreP.  If the register supports both, use Op_RegI.
   61 //
   62 // The encoding number is the actual bit-pattern placed into the opcodes.
   63 
   64 // We must define the 64 bit int registers in two 32 bit halves, the
   65 // real lower register and a virtual upper half register. upper halves
   66 // are used by the register allocator but are not actually supplied as
   67 // operands to memory ops.
   68 //
   69 // follow the C1 compiler in making registers
   70 //
   71 //   x7, x9-x17, x27-x31 volatile (caller save)
   72 //   x0-x4, x8, x23 system (no save, no allocate)
   73 //   x5-x6 non-allocatable (so we can use them as temporary regs)
   74 
   75 //
   76 // as regards Java usage. we don't use any callee save registers
   77 // because this makes it difficult to de-optimise a frame (see comment
   78 // in x86 implementation of Deoptimization::unwind_callee_save_values)
   79 //
   80 
   81 // General Registers
   82 
   83 reg_def R0      ( NS,  NS,  Op_RegI, 0,  x0->as_VMReg()         ); // zr
   84 reg_def R0_H    ( NS,  NS,  Op_RegI, 0,  x0->as_VMReg()->next() );
   85 reg_def R1      ( NS,  SOC, Op_RegI, 1,  x1->as_VMReg()         ); // ra
   86 reg_def R1_H    ( NS,  SOC, Op_RegI, 1,  x1->as_VMReg()->next() );
   87 reg_def R2      ( NS,  NS,  Op_RegI, 2,  x2->as_VMReg()         ); // sp
   88 reg_def R2_H    ( NS,  NS,  Op_RegI, 2,  x2->as_VMReg()->next() );
   89 reg_def R3      ( NS,  NS,  Op_RegI, 3,  x3->as_VMReg()         ); // gp
   90 reg_def R3_H    ( NS,  NS,  Op_RegI, 3,  x3->as_VMReg()->next() );
   91 reg_def R4      ( NS,  NS,  Op_RegI, 4,  x4->as_VMReg()         ); // tp
   92 reg_def R4_H    ( NS,  NS,  Op_RegI, 4,  x4->as_VMReg()->next() );
   93 reg_def R7      ( SOC, SOC, Op_RegI, 7,  x7->as_VMReg()         );
   94 reg_def R7_H    ( SOC, SOC, Op_RegI, 7,  x7->as_VMReg()->next() );
   95 reg_def R8      ( NS,  SOE, Op_RegI, 8,  x8->as_VMReg()         ); // fp
   96 reg_def R8_H    ( NS,  SOE, Op_RegI, 8,  x8->as_VMReg()->next() );
   97 reg_def R9      ( SOC, SOE, Op_RegI, 9,  x9->as_VMReg()         );
   98 reg_def R9_H    ( SOC, SOE, Op_RegI, 9,  x9->as_VMReg()->next() );
   99 reg_def R10     ( SOC, SOC, Op_RegI, 10, x10->as_VMReg()        );
  100 reg_def R10_H   ( SOC, SOC, Op_RegI, 10, x10->as_VMReg()->next());
  101 reg_def R11     ( SOC, SOC, Op_RegI, 11, x11->as_VMReg()        );
  102 reg_def R11_H   ( SOC, SOC, Op_RegI, 11, x11->as_VMReg()->next());
  103 reg_def R12     ( SOC, SOC, Op_RegI, 12, x12->as_VMReg()        );
  104 reg_def R12_H   ( SOC, SOC, Op_RegI, 12, x12->as_VMReg()->next());
  105 reg_def R13     ( SOC, SOC, Op_RegI, 13, x13->as_VMReg()        );
  106 reg_def R13_H   ( SOC, SOC, Op_RegI, 13, x13->as_VMReg()->next());
  107 reg_def R14     ( SOC, SOC, Op_RegI, 14, x14->as_VMReg()        );
  108 reg_def R14_H   ( SOC, SOC, Op_RegI, 14, x14->as_VMReg()->next());
  109 reg_def R15     ( SOC, SOC, Op_RegI, 15, x15->as_VMReg()        );
  110 reg_def R15_H   ( SOC, SOC, Op_RegI, 15, x15->as_VMReg()->next());
  111 reg_def R16     ( SOC, SOC, Op_RegI, 16, x16->as_VMReg()        );
  112 reg_def R16_H   ( SOC, SOC, Op_RegI, 16, x16->as_VMReg()->next());
  113 reg_def R17     ( SOC, SOC, Op_RegI, 17, x17->as_VMReg()        );
  114 reg_def R17_H   ( SOC, SOC, Op_RegI, 17, x17->as_VMReg()->next());
  115 reg_def R18     ( SOC, SOE, Op_RegI, 18, x18->as_VMReg()        );
  116 reg_def R18_H   ( SOC, SOE, Op_RegI, 18, x18->as_VMReg()->next());
  117 reg_def R19     ( SOC, SOE, Op_RegI, 19, x19->as_VMReg()        );
  118 reg_def R19_H   ( SOC, SOE, Op_RegI, 19, x19->as_VMReg()->next());
  119 reg_def R20     ( SOC, SOE, Op_RegI, 20, x20->as_VMReg()        ); // caller esp
  120 reg_def R20_H   ( SOC, SOE, Op_RegI, 20, x20->as_VMReg()->next());
  121 reg_def R21     ( SOC, SOE, Op_RegI, 21, x21->as_VMReg()        );
  122 reg_def R21_H   ( SOC, SOE, Op_RegI, 21, x21->as_VMReg()->next());
  123 reg_def R22     ( SOC, SOE, Op_RegI, 22, x22->as_VMReg()        );
  124 reg_def R22_H   ( SOC, SOE, Op_RegI, 22, x22->as_VMReg()->next());
  125 reg_def R23     ( NS,  SOE, Op_RegI, 23, x23->as_VMReg()        ); // java thread
  126 reg_def R23_H   ( NS,  SOE, Op_RegI, 23, x23->as_VMReg()->next());
  127 reg_def R24     ( SOC, SOE, Op_RegI, 24, x24->as_VMReg()        );
  128 reg_def R24_H   ( SOC, SOE, Op_RegI, 24, x24->as_VMReg()->next());
  129 reg_def R25     ( SOC, SOE, Op_RegI, 25, x25->as_VMReg()        );
  130 reg_def R25_H   ( SOC, SOE, Op_RegI, 25, x25->as_VMReg()->next());
  131 reg_def R26     ( SOC, SOE, Op_RegI, 26, x26->as_VMReg()        );
  132 reg_def R26_H   ( SOC, SOE, Op_RegI, 26, x26->as_VMReg()->next());
  133 reg_def R27     ( SOC, SOE, Op_RegI, 27, x27->as_VMReg()        ); // heapbase
  134 reg_def R27_H   ( SOC, SOE, Op_RegI, 27, x27->as_VMReg()->next());
  135 reg_def R28     ( SOC, SOC, Op_RegI, 28, x28->as_VMReg()        );
  136 reg_def R28_H   ( SOC, SOC, Op_RegI, 28, x28->as_VMReg()->next());
  137 reg_def R29     ( SOC, SOC, Op_RegI, 29, x29->as_VMReg()        );
  138 reg_def R29_H   ( SOC, SOC, Op_RegI, 29, x29->as_VMReg()->next());
  139 reg_def R30     ( SOC, SOC, Op_RegI, 30, x30->as_VMReg()        );
  140 reg_def R30_H   ( SOC, SOC, Op_RegI, 30, x30->as_VMReg()->next());
  141 reg_def R31     ( SOC, SOC, Op_RegI, 31, x31->as_VMReg()        );
  142 reg_def R31_H   ( SOC, SOC, Op_RegI, 31, x31->as_VMReg()->next());
  143 
  144 // ----------------------------
  145 // Float/Double Registers
  146 // ----------------------------
  147 
  148 // Double Registers
  149 
  150 // The rules of ADL require that double registers be defined in pairs.
  151 // Each pair must be two 32-bit values, but not necessarily a pair of
  152 // single float registers. In each pair, ADLC-assigned register numbers
  153 // must be adjacent, with the lower number even. Finally, when the
  154 // CPU stores such a register pair to memory, the word associated with
  155 // the lower ADLC-assigned number must be stored to the lower address.
  156 
  157 // RISCV has 32 floating-point registers. Each can store a single
  158 // or double precision floating-point value.
  159 
  160 // for Java use float registers f0-f31 are always save on call whereas
  161 // the platform ABI treats f8-f9 and f18-f27 as callee save). Other
  162 // float registers are SOC as per the platform spec
  163 
  164 reg_def F0    ( SOC, SOC, Op_RegF,  0,  f0->as_VMReg()          );
  165 reg_def F0_H  ( SOC, SOC, Op_RegF,  0,  f0->as_VMReg()->next()  );
  166 reg_def F1    ( SOC, SOC, Op_RegF,  1,  f1->as_VMReg()          );
  167 reg_def F1_H  ( SOC, SOC, Op_RegF,  1,  f1->as_VMReg()->next()  );
  168 reg_def F2    ( SOC, SOC, Op_RegF,  2,  f2->as_VMReg()          );
  169 reg_def F2_H  ( SOC, SOC, Op_RegF,  2,  f2->as_VMReg()->next()  );
  170 reg_def F3    ( SOC, SOC, Op_RegF,  3,  f3->as_VMReg()          );
  171 reg_def F3_H  ( SOC, SOC, Op_RegF,  3,  f3->as_VMReg()->next()  );
  172 reg_def F4    ( SOC, SOC, Op_RegF,  4,  f4->as_VMReg()          );
  173 reg_def F4_H  ( SOC, SOC, Op_RegF,  4,  f4->as_VMReg()->next()  );
  174 reg_def F5    ( SOC, SOC, Op_RegF,  5,  f5->as_VMReg()          );
  175 reg_def F5_H  ( SOC, SOC, Op_RegF,  5,  f5->as_VMReg()->next()  );
  176 reg_def F6    ( SOC, SOC, Op_RegF,  6,  f6->as_VMReg()          );
  177 reg_def F6_H  ( SOC, SOC, Op_RegF,  6,  f6->as_VMReg()->next()  );
  178 reg_def F7    ( SOC, SOC, Op_RegF,  7,  f7->as_VMReg()          );
  179 reg_def F7_H  ( SOC, SOC, Op_RegF,  7,  f7->as_VMReg()->next()  );
  180 reg_def F8    ( SOC, SOE, Op_RegF,  8,  f8->as_VMReg()          );
  181 reg_def F8_H  ( SOC, SOE, Op_RegF,  8,  f8->as_VMReg()->next()  );
  182 reg_def F9    ( SOC, SOE, Op_RegF,  9,  f9->as_VMReg()          );
  183 reg_def F9_H  ( SOC, SOE, Op_RegF,  9,  f9->as_VMReg()->next()  );
  184 reg_def F10   ( SOC, SOC, Op_RegF,  10, f10->as_VMReg()         );
  185 reg_def F10_H ( SOC, SOC, Op_RegF,  10, f10->as_VMReg()->next() );
  186 reg_def F11   ( SOC, SOC, Op_RegF,  11, f11->as_VMReg()         );
  187 reg_def F11_H ( SOC, SOC, Op_RegF,  11, f11->as_VMReg()->next() );
  188 reg_def F12   ( SOC, SOC, Op_RegF,  12, f12->as_VMReg()         );
  189 reg_def F12_H ( SOC, SOC, Op_RegF,  12, f12->as_VMReg()->next() );
  190 reg_def F13   ( SOC, SOC, Op_RegF,  13, f13->as_VMReg()         );
  191 reg_def F13_H ( SOC, SOC, Op_RegF,  13, f13->as_VMReg()->next() );
  192 reg_def F14   ( SOC, SOC, Op_RegF,  14, f14->as_VMReg()         );
  193 reg_def F14_H ( SOC, SOC, Op_RegF,  14, f14->as_VMReg()->next() );
  194 reg_def F15   ( SOC, SOC, Op_RegF,  15, f15->as_VMReg()         );
  195 reg_def F15_H ( SOC, SOC, Op_RegF,  15, f15->as_VMReg()->next() );
  196 reg_def F16   ( SOC, SOC, Op_RegF,  16, f16->as_VMReg()         );
  197 reg_def F16_H ( SOC, SOC, Op_RegF,  16, f16->as_VMReg()->next() );
  198 reg_def F17   ( SOC, SOC, Op_RegF,  17, f17->as_VMReg()         );
  199 reg_def F17_H ( SOC, SOC, Op_RegF,  17, f17->as_VMReg()->next() );
  200 reg_def F18   ( SOC, SOE, Op_RegF,  18, f18->as_VMReg()         );
  201 reg_def F18_H ( SOC, SOE, Op_RegF,  18, f18->as_VMReg()->next() );
  202 reg_def F19   ( SOC, SOE, Op_RegF,  19, f19->as_VMReg()         );
  203 reg_def F19_H ( SOC, SOE, Op_RegF,  19, f19->as_VMReg()->next() );
  204 reg_def F20   ( SOC, SOE, Op_RegF,  20, f20->as_VMReg()         );
  205 reg_def F20_H ( SOC, SOE, Op_RegF,  20, f20->as_VMReg()->next() );
  206 reg_def F21   ( SOC, SOE, Op_RegF,  21, f21->as_VMReg()         );
  207 reg_def F21_H ( SOC, SOE, Op_RegF,  21, f21->as_VMReg()->next() );
  208 reg_def F22   ( SOC, SOE, Op_RegF,  22, f22->as_VMReg()         );
  209 reg_def F22_H ( SOC, SOE, Op_RegF,  22, f22->as_VMReg()->next() );
  210 reg_def F23   ( SOC, SOE, Op_RegF,  23, f23->as_VMReg()         );
  211 reg_def F23_H ( SOC, SOE, Op_RegF,  23, f23->as_VMReg()->next() );
  212 reg_def F24   ( SOC, SOE, Op_RegF,  24, f24->as_VMReg()         );
  213 reg_def F24_H ( SOC, SOE, Op_RegF,  24, f24->as_VMReg()->next() );
  214 reg_def F25   ( SOC, SOE, Op_RegF,  25, f25->as_VMReg()         );
  215 reg_def F25_H ( SOC, SOE, Op_RegF,  25, f25->as_VMReg()->next() );
  216 reg_def F26   ( SOC, SOE, Op_RegF,  26, f26->as_VMReg()         );
  217 reg_def F26_H ( SOC, SOE, Op_RegF,  26, f26->as_VMReg()->next() );
  218 reg_def F27   ( SOC, SOE, Op_RegF,  27, f27->as_VMReg()         );
  219 reg_def F27_H ( SOC, SOE, Op_RegF,  27, f27->as_VMReg()->next() );
  220 reg_def F28   ( SOC, SOC, Op_RegF,  28, f28->as_VMReg()         );
  221 reg_def F28_H ( SOC, SOC, Op_RegF,  28, f28->as_VMReg()->next() );
  222 reg_def F29   ( SOC, SOC, Op_RegF,  29, f29->as_VMReg()         );
  223 reg_def F29_H ( SOC, SOC, Op_RegF,  29, f29->as_VMReg()->next() );
  224 reg_def F30   ( SOC, SOC, Op_RegF,  30, f30->as_VMReg()         );
  225 reg_def F30_H ( SOC, SOC, Op_RegF,  30, f30->as_VMReg()->next() );
  226 reg_def F31   ( SOC, SOC, Op_RegF,  31, f31->as_VMReg()         );
  227 reg_def F31_H ( SOC, SOC, Op_RegF,  31, f31->as_VMReg()->next() );
  228 
  229 // ----------------------------
  230 // Vector Registers
  231 // ----------------------------
  232 
  233 // For RVV vector registers, we simply extend vector register size to 4
  234 // 'logical' slots. This is nominally 128 bits but it actually covers
  235 // all possible 'physical' RVV vector register lengths from 128 ~ 1024
  236 // bits. The 'physical' RVV vector register length is detected during
  237 // startup, so the register allocator is able to identify the correct
  238 // number of bytes needed for an RVV spill/unspill.
  239 
  240 reg_def V0    ( SOC, SOC, Op_VecA, 0,  v0->as_VMReg()           );
  241 reg_def V0_H  ( SOC, SOC, Op_VecA, 0,  v0->as_VMReg()->next()   );
  242 reg_def V0_J  ( SOC, SOC, Op_VecA, 0,  v0->as_VMReg()->next(2)  );
  243 reg_def V0_K  ( SOC, SOC, Op_VecA, 0,  v0->as_VMReg()->next(3)  );
  244 
  245 reg_def V1    ( SOC, SOC, Op_VecA, 1,  v1->as_VMReg()           );
  246 reg_def V1_H  ( SOC, SOC, Op_VecA, 1,  v1->as_VMReg()->next()   );
  247 reg_def V1_J  ( SOC, SOC, Op_VecA, 1,  v1->as_VMReg()->next(2)  );
  248 reg_def V1_K  ( SOC, SOC, Op_VecA, 1,  v1->as_VMReg()->next(3)  );
  249 
  250 reg_def V2    ( SOC, SOC, Op_VecA, 2,  v2->as_VMReg()           );
  251 reg_def V2_H  ( SOC, SOC, Op_VecA, 2,  v2->as_VMReg()->next()   );
  252 reg_def V2_J  ( SOC, SOC, Op_VecA, 2,  v2->as_VMReg()->next(2)  );
  253 reg_def V2_K  ( SOC, SOC, Op_VecA, 2,  v2->as_VMReg()->next(3)  );
  254 
  255 reg_def V3    ( SOC, SOC, Op_VecA, 3,  v3->as_VMReg()           );
  256 reg_def V3_H  ( SOC, SOC, Op_VecA, 3,  v3->as_VMReg()->next()   );
  257 reg_def V3_J  ( SOC, SOC, Op_VecA, 3,  v3->as_VMReg()->next(2)  );
  258 reg_def V3_K  ( SOC, SOC, Op_VecA, 3,  v3->as_VMReg()->next(3)  );
  259 
  260 reg_def V4    ( SOC, SOC, Op_VecA, 4,  v4->as_VMReg()           );
  261 reg_def V4_H  ( SOC, SOC, Op_VecA, 4,  v4->as_VMReg()->next()   );
  262 reg_def V4_J  ( SOC, SOC, Op_VecA, 4,  v4->as_VMReg()->next(2)  );
  263 reg_def V4_K  ( SOC, SOC, Op_VecA, 4,  v4->as_VMReg()->next(3)  );
  264 
  265 reg_def V5    ( SOC, SOC, Op_VecA, 5,  v5->as_VMReg()           );
  266 reg_def V5_H  ( SOC, SOC, Op_VecA, 5,  v5->as_VMReg()->next()   );
  267 reg_def V5_J  ( SOC, SOC, Op_VecA, 5,  v5->as_VMReg()->next(2)  );
  268 reg_def V5_K  ( SOC, SOC, Op_VecA, 5,  v5->as_VMReg()->next(3)  );
  269 
  270 reg_def V6    ( SOC, SOC, Op_VecA, 6,  v6->as_VMReg()           );
  271 reg_def V6_H  ( SOC, SOC, Op_VecA, 6,  v6->as_VMReg()->next()   );
  272 reg_def V6_J  ( SOC, SOC, Op_VecA, 6,  v6->as_VMReg()->next(2)  );
  273 reg_def V6_K  ( SOC, SOC, Op_VecA, 6,  v6->as_VMReg()->next(3)  );
  274 
  275 reg_def V7    ( SOC, SOC, Op_VecA, 7,  v7->as_VMReg()           );
  276 reg_def V7_H  ( SOC, SOC, Op_VecA, 7,  v7->as_VMReg()->next()   );
  277 reg_def V7_J  ( SOC, SOC, Op_VecA, 7,  v7->as_VMReg()->next(2)  );
  278 reg_def V7_K  ( SOC, SOC, Op_VecA, 7,  v7->as_VMReg()->next(3)  );
  279 
  280 reg_def V8    ( SOC, SOC, Op_VecA, 8,  v8->as_VMReg()           );
  281 reg_def V8_H  ( SOC, SOC, Op_VecA, 8,  v8->as_VMReg()->next()   );
  282 reg_def V8_J  ( SOC, SOC, Op_VecA, 8,  v8->as_VMReg()->next(2)  );
  283 reg_def V8_K  ( SOC, SOC, Op_VecA, 8,  v8->as_VMReg()->next(3)  );
  284 
  285 reg_def V9    ( SOC, SOC, Op_VecA, 9,  v9->as_VMReg()           );
  286 reg_def V9_H  ( SOC, SOC, Op_VecA, 9,  v9->as_VMReg()->next()   );
  287 reg_def V9_J  ( SOC, SOC, Op_VecA, 9,  v9->as_VMReg()->next(2)  );
  288 reg_def V9_K  ( SOC, SOC, Op_VecA, 9,  v9->as_VMReg()->next(3)  );
  289 
  290 reg_def V10   ( SOC, SOC, Op_VecA, 10, v10->as_VMReg()          );
  291 reg_def V10_H ( SOC, SOC, Op_VecA, 10, v10->as_VMReg()->next()  );
  292 reg_def V10_J ( SOC, SOC, Op_VecA, 10, v10->as_VMReg()->next(2) );
  293 reg_def V10_K ( SOC, SOC, Op_VecA, 10, v10->as_VMReg()->next(3) );
  294 
  295 reg_def V11   ( SOC, SOC, Op_VecA, 11, v11->as_VMReg()          );
  296 reg_def V11_H ( SOC, SOC, Op_VecA, 11, v11->as_VMReg()->next()  );
  297 reg_def V11_J ( SOC, SOC, Op_VecA, 11, v11->as_VMReg()->next(2) );
  298 reg_def V11_K ( SOC, SOC, Op_VecA, 11, v11->as_VMReg()->next(3) );
  299 
  300 reg_def V12   ( SOC, SOC, Op_VecA, 12, v12->as_VMReg()          );
  301 reg_def V12_H ( SOC, SOC, Op_VecA, 12, v12->as_VMReg()->next()  );
  302 reg_def V12_J ( SOC, SOC, Op_VecA, 12, v12->as_VMReg()->next(2) );
  303 reg_def V12_K ( SOC, SOC, Op_VecA, 12, v12->as_VMReg()->next(3) );
  304 
  305 reg_def V13   ( SOC, SOC, Op_VecA, 13, v13->as_VMReg()          );
  306 reg_def V13_H ( SOC, SOC, Op_VecA, 13, v13->as_VMReg()->next()  );
  307 reg_def V13_J ( SOC, SOC, Op_VecA, 13, v13->as_VMReg()->next(2) );
  308 reg_def V13_K ( SOC, SOC, Op_VecA, 13, v13->as_VMReg()->next(3) );
  309 
  310 reg_def V14   ( SOC, SOC, Op_VecA, 14, v14->as_VMReg()          );
  311 reg_def V14_H ( SOC, SOC, Op_VecA, 14, v14->as_VMReg()->next()  );
  312 reg_def V14_J ( SOC, SOC, Op_VecA, 14, v14->as_VMReg()->next(2) );
  313 reg_def V14_K ( SOC, SOC, Op_VecA, 14, v14->as_VMReg()->next(3) );
  314 
  315 reg_def V15   ( SOC, SOC, Op_VecA, 15, v15->as_VMReg()          );
  316 reg_def V15_H ( SOC, SOC, Op_VecA, 15, v15->as_VMReg()->next()  );
  317 reg_def V15_J ( SOC, SOC, Op_VecA, 15, v15->as_VMReg()->next(2) );
  318 reg_def V15_K ( SOC, SOC, Op_VecA, 15, v15->as_VMReg()->next(3) );
  319 
  320 reg_def V16   ( SOC, SOC, Op_VecA, 16, v16->as_VMReg()          );
  321 reg_def V16_H ( SOC, SOC, Op_VecA, 16, v16->as_VMReg()->next()  );
  322 reg_def V16_J ( SOC, SOC, Op_VecA, 16, v16->as_VMReg()->next(2) );
  323 reg_def V16_K ( SOC, SOC, Op_VecA, 16, v16->as_VMReg()->next(3) );
  324 
  325 reg_def V17   ( SOC, SOC, Op_VecA, 17, v17->as_VMReg()          );
  326 reg_def V17_H ( SOC, SOC, Op_VecA, 17, v17->as_VMReg()->next()  );
  327 reg_def V17_J ( SOC, SOC, Op_VecA, 17, v17->as_VMReg()->next(2) );
  328 reg_def V17_K ( SOC, SOC, Op_VecA, 17, v17->as_VMReg()->next(3) );
  329 
  330 reg_def V18   ( SOC, SOC, Op_VecA, 18, v18->as_VMReg()          );
  331 reg_def V18_H ( SOC, SOC, Op_VecA, 18, v18->as_VMReg()->next()  );
  332 reg_def V18_J ( SOC, SOC, Op_VecA, 18, v18->as_VMReg()->next(2) );
  333 reg_def V18_K ( SOC, SOC, Op_VecA, 18, v18->as_VMReg()->next(3) );
  334 
  335 reg_def V19   ( SOC, SOC, Op_VecA, 19, v19->as_VMReg()          );
  336 reg_def V19_H ( SOC, SOC, Op_VecA, 19, v19->as_VMReg()->next()  );
  337 reg_def V19_J ( SOC, SOC, Op_VecA, 19, v19->as_VMReg()->next(2) );
  338 reg_def V19_K ( SOC, SOC, Op_VecA, 19, v19->as_VMReg()->next(3) );
  339 
  340 reg_def V20   ( SOC, SOC, Op_VecA, 20, v20->as_VMReg()          );
  341 reg_def V20_H ( SOC, SOC, Op_VecA, 20, v20->as_VMReg()->next()  );
  342 reg_def V20_J ( SOC, SOC, Op_VecA, 20, v20->as_VMReg()->next(2) );
  343 reg_def V20_K ( SOC, SOC, Op_VecA, 20, v20->as_VMReg()->next(3) );
  344 
  345 reg_def V21   ( SOC, SOC, Op_VecA, 21, v21->as_VMReg()          );
  346 reg_def V21_H ( SOC, SOC, Op_VecA, 21, v21->as_VMReg()->next()  );
  347 reg_def V21_J ( SOC, SOC, Op_VecA, 21, v21->as_VMReg()->next(2) );
  348 reg_def V21_K ( SOC, SOC, Op_VecA, 21, v21->as_VMReg()->next(3) );
  349 
  350 reg_def V22   ( SOC, SOC, Op_VecA, 22, v22->as_VMReg()          );
  351 reg_def V22_H ( SOC, SOC, Op_VecA, 22, v22->as_VMReg()->next()  );
  352 reg_def V22_J ( SOC, SOC, Op_VecA, 22, v22->as_VMReg()->next(2) );
  353 reg_def V22_K ( SOC, SOC, Op_VecA, 22, v22->as_VMReg()->next(3) );
  354 
  355 reg_def V23   ( SOC, SOC, Op_VecA, 23, v23->as_VMReg()          );
  356 reg_def V23_H ( SOC, SOC, Op_VecA, 23, v23->as_VMReg()->next()  );
  357 reg_def V23_J ( SOC, SOC, Op_VecA, 23, v23->as_VMReg()->next(2) );
  358 reg_def V23_K ( SOC, SOC, Op_VecA, 23, v23->as_VMReg()->next(3) );
  359 
  360 reg_def V24   ( SOC, SOC, Op_VecA, 24, v24->as_VMReg()          );
  361 reg_def V24_H ( SOC, SOC, Op_VecA, 24, v24->as_VMReg()->next()  );
  362 reg_def V24_J ( SOC, SOC, Op_VecA, 24, v24->as_VMReg()->next(2) );
  363 reg_def V24_K ( SOC, SOC, Op_VecA, 24, v24->as_VMReg()->next(3) );
  364 
  365 reg_def V25   ( SOC, SOC, Op_VecA, 25, v25->as_VMReg()          );
  366 reg_def V25_H ( SOC, SOC, Op_VecA, 25, v25->as_VMReg()->next()  );
  367 reg_def V25_J ( SOC, SOC, Op_VecA, 25, v25->as_VMReg()->next(2) );
  368 reg_def V25_K ( SOC, SOC, Op_VecA, 25, v25->as_VMReg()->next(3) );
  369 
  370 reg_def V26   ( SOC, SOC, Op_VecA, 26, v26->as_VMReg()          );
  371 reg_def V26_H ( SOC, SOC, Op_VecA, 26, v26->as_VMReg()->next()  );
  372 reg_def V26_J ( SOC, SOC, Op_VecA, 26, v26->as_VMReg()->next(2) );
  373 reg_def V26_K ( SOC, SOC, Op_VecA, 26, v26->as_VMReg()->next(3) );
  374 
  375 reg_def V27   ( SOC, SOC, Op_VecA, 27, v27->as_VMReg()          );
  376 reg_def V27_H ( SOC, SOC, Op_VecA, 27, v27->as_VMReg()->next()  );
  377 reg_def V27_J ( SOC, SOC, Op_VecA, 27, v27->as_VMReg()->next(2) );
  378 reg_def V27_K ( SOC, SOC, Op_VecA, 27, v27->as_VMReg()->next(3) );
  379 
  380 reg_def V28   ( SOC, SOC, Op_VecA, 28, v28->as_VMReg()          );
  381 reg_def V28_H ( SOC, SOC, Op_VecA, 28, v28->as_VMReg()->next()  );
  382 reg_def V28_J ( SOC, SOC, Op_VecA, 28, v28->as_VMReg()->next(2) );
  383 reg_def V28_K ( SOC, SOC, Op_VecA, 28, v28->as_VMReg()->next(3) );
  384 
  385 reg_def V29   ( SOC, SOC, Op_VecA, 29, v29->as_VMReg()          );
  386 reg_def V29_H ( SOC, SOC, Op_VecA, 29, v29->as_VMReg()->next()  );
  387 reg_def V29_J ( SOC, SOC, Op_VecA, 29, v29->as_VMReg()->next(2) );
  388 reg_def V29_K ( SOC, SOC, Op_VecA, 29, v29->as_VMReg()->next(3) );
  389 
  390 reg_def V30   ( SOC, SOC, Op_VecA, 30, v30->as_VMReg()          );
  391 reg_def V30_H ( SOC, SOC, Op_VecA, 30, v30->as_VMReg()->next()  );
  392 reg_def V30_J ( SOC, SOC, Op_VecA, 30, v30->as_VMReg()->next(2) );
  393 reg_def V30_K ( SOC, SOC, Op_VecA, 30, v30->as_VMReg()->next(3) );
  394 
  395 reg_def V31   ( SOC, SOC, Op_VecA, 31, v31->as_VMReg()          );
  396 reg_def V31_H ( SOC, SOC, Op_VecA, 31, v31->as_VMReg()->next()  );
  397 reg_def V31_J ( SOC, SOC, Op_VecA, 31, v31->as_VMReg()->next(2) );
  398 reg_def V31_K ( SOC, SOC, Op_VecA, 31, v31->as_VMReg()->next(3) );
  399 
  400 // ----------------------------
  401 // Special Registers
  402 // ----------------------------
  403 
  404 // On riscv, the physical flag register is missing, so we use t1 instead,
  405 // to bridge the RegFlag semantics in share/opto
  406 
  407 reg_def RFLAGS   (SOC, SOC, Op_RegFlags, 6, x6->as_VMReg()        );
  408 
  409 // Specify priority of register selection within phases of register
  410 // allocation.  Highest priority is first.  A useful heuristic is to
  411 // give registers a low priority when they are required by machine
  412 // instructions, like EAX and EDX on I486, and choose no-save registers
  413 // before save-on-call, & save-on-call before save-on-entry.  Registers
  414 // which participate in fixed calling sequences should come last.
  415 // Registers which are used as pairs must fall on an even boundary.
  416 
  417 alloc_class chunk0(
  418     // volatiles
  419     R7,  R7_H,
  420     R28, R28_H,
  421     R29, R29_H,
  422     R30, R30_H,
  423     R31, R31_H,
  424 
  425     // arg registers
  426     R10, R10_H,
  427     R11, R11_H,
  428     R12, R12_H,
  429     R13, R13_H,
  430     R14, R14_H,
  431     R15, R15_H,
  432     R16, R16_H,
  433     R17, R17_H,
  434 
  435     // non-volatiles
  436     R9,  R9_H,
  437     R18, R18_H,
  438     R19, R19_H,
  439     R20, R20_H,
  440     R21, R21_H,
  441     R22, R22_H,
  442     R24, R24_H,
  443     R25, R25_H,
  444     R26, R26_H,
  445 
  446     // non-allocatable registers
  447     R23, R23_H, // java thread
  448     R27, R27_H, // heapbase
  449     R4,  R4_H,  // thread
  450     R8,  R8_H,  // fp
  451     R0,  R0_H,  // zero
  452     R1,  R1_H,  // ra
  453     R2,  R2_H,  // sp
  454     R3,  R3_H,  // gp
  455 );
  456 
  457 alloc_class chunk1(
  458 
  459     // no save
  460     F0,  F0_H,
  461     F1,  F1_H,
  462     F2,  F2_H,
  463     F3,  F3_H,
  464     F4,  F4_H,
  465     F5,  F5_H,
  466     F6,  F6_H,
  467     F7,  F7_H,
  468     F28, F28_H,
  469     F29, F29_H,
  470     F30, F30_H,
  471     F31, F31_H,
  472 
  473     // arg registers
  474     F10, F10_H,
  475     F11, F11_H,
  476     F12, F12_H,
  477     F13, F13_H,
  478     F14, F14_H,
  479     F15, F15_H,
  480     F16, F16_H,
  481     F17, F17_H,
  482 
  483     // non-volatiles
  484     F8,  F8_H,
  485     F9,  F9_H,
  486     F18, F18_H,
  487     F19, F19_H,
  488     F20, F20_H,
  489     F21, F21_H,
  490     F22, F22_H,
  491     F23, F23_H,
  492     F24, F24_H,
  493     F25, F25_H,
  494     F26, F26_H,
  495     F27, F27_H,
  496 );
  497 
  498 alloc_class chunk2(
  499     V0, V0_H, V0_J, V0_K,
  500     V1, V1_H, V1_J, V1_K,
  501     V2, V2_H, V2_J, V2_K,
  502     V3, V3_H, V3_J, V3_K,
  503     V4, V4_H, V4_J, V4_K,
  504     V5, V5_H, V5_J, V5_K,
  505     V6, V6_H, V6_J, V6_K,
  506     V7, V7_H, V7_J, V7_K,
  507     V8, V8_H, V8_J, V8_K,
  508     V9, V9_H, V9_J, V9_K,
  509     V10, V10_H, V10_J, V10_K,
  510     V11, V11_H, V11_J, V11_K,
  511     V12, V12_H, V12_J, V12_K,
  512     V13, V13_H, V13_J, V13_K,
  513     V14, V14_H, V14_J, V14_K,
  514     V15, V15_H, V15_J, V15_K,
  515     V16, V16_H, V16_J, V16_K,
  516     V17, V17_H, V17_J, V17_K,
  517     V18, V18_H, V18_J, V18_K,
  518     V19, V19_H, V19_J, V19_K,
  519     V20, V20_H, V20_J, V20_K,
  520     V21, V21_H, V21_J, V21_K,
  521     V22, V22_H, V22_J, V22_K,
  522     V23, V23_H, V23_J, V23_K,
  523     V24, V24_H, V24_J, V24_K,
  524     V25, V25_H, V25_J, V25_K,
  525     V26, V26_H, V26_J, V26_K,
  526     V27, V27_H, V27_J, V27_K,
  527     V28, V28_H, V28_J, V28_K,
  528     V29, V29_H, V29_J, V29_K,
  529     V30, V30_H, V30_J, V30_K,
  530     V31, V31_H, V31_J, V31_K,
  531 );
  532 
  533 alloc_class chunk3(RFLAGS);
  534 
  535 //----------Architecture Description Register Classes--------------------------
  536 // Several register classes are automatically defined based upon information in
  537 // this architecture description.
  538 // 1) reg_class inline_cache_reg           ( /* as def'd in frame section */ )
  539 // 2) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
  540 //
  541 
  542 // Class for all 32 bit general purpose registers
  543 reg_class all_reg32(
  544     R0,
  545     R1,
  546     R2,
  547     R3,
  548     R4,
  549     R7,
  550     R8,
  551     R9,
  552     R10,
  553     R11,
  554     R12,
  555     R13,
  556     R14,
  557     R15,
  558     R16,
  559     R17,
  560     R18,
  561     R19,
  562     R20,
  563     R21,
  564     R22,
  565     R23,
  566     R24,
  567     R25,
  568     R26,
  569     R27,
  570     R28,
  571     R29,
  572     R30,
  573     R31
  574 );
  575 
  576 // Class for any 32 bit integer registers (excluding zr)
  577 reg_class any_reg32 %{
  578   return _ANY_REG32_mask;
  579 %}
  580 
  581 // Singleton class for R10 int register
  582 reg_class int_r10_reg(R10);
  583 
  584 // Singleton class for R12 int register
  585 reg_class int_r12_reg(R12);
  586 
  587 // Singleton class for R13 int register
  588 reg_class int_r13_reg(R13);
  589 
  590 // Singleton class for R14 int register
  591 reg_class int_r14_reg(R14);
  592 
  593 // Class for all long integer registers
  594 reg_class all_reg(
  595     R0,  R0_H,
  596     R1,  R1_H,
  597     R2,  R2_H,
  598     R3,  R3_H,
  599     R4,  R4_H,
  600     R7,  R7_H,
  601     R8,  R8_H,
  602     R9,  R9_H,
  603     R10, R10_H,
  604     R11, R11_H,
  605     R12, R12_H,
  606     R13, R13_H,
  607     R14, R14_H,
  608     R15, R15_H,
  609     R16, R16_H,
  610     R17, R17_H,
  611     R18, R18_H,
  612     R19, R19_H,
  613     R20, R20_H,
  614     R21, R21_H,
  615     R22, R22_H,
  616     R23, R23_H,
  617     R24, R24_H,
  618     R25, R25_H,
  619     R26, R26_H,
  620     R27, R27_H,
  621     R28, R28_H,
  622     R29, R29_H,
  623     R30, R30_H,
  624     R31, R31_H
  625 );
  626 
  627 // Class for all long integer registers (excluding zr)
  628 reg_class any_reg %{
  629   return _ANY_REG_mask;
  630 %}
  631 
  632 // Class for non-allocatable 32 bit registers
  633 reg_class non_allocatable_reg32(
  634     R0,                       // zr
  635     R1,                       // ra
  636     R2,                       // sp
  637     R3,                       // gp
  638     R4,                       // tp
  639     R23                       // java thread
  640 );
  641 
  642 // Class for non-allocatable 64 bit registers
  643 reg_class non_allocatable_reg(
  644     R0,  R0_H,                // zr
  645     R1,  R1_H,                // ra
  646     R2,  R2_H,                // sp
  647     R3,  R3_H,                // gp
  648     R4,  R4_H,                // tp
  649     R23, R23_H                // java thread
  650 );
  651 
  652 // Class for all non-special integer registers
  653 reg_class no_special_reg32 %{
  654   return _NO_SPECIAL_REG32_mask;
  655 %}
  656 
  657 // Class for all non-special long integer registers
  658 reg_class no_special_reg %{
  659   return _NO_SPECIAL_REG_mask;
  660 %}
  661 
  662 reg_class ptr_reg %{
  663   return _PTR_REG_mask;
  664 %}
  665 
  666 // Class for all non_special pointer registers
  667 reg_class no_special_ptr_reg %{
  668   return _NO_SPECIAL_PTR_REG_mask;
  669 %}
  670 
  671 // Class for all non_special pointer registers (excluding fp)
  672 reg_class no_special_no_fp_ptr_reg %{
  673   return _NO_SPECIAL_NO_FP_PTR_REG_mask;
  674 %}
  675 
  676 // Class for 64 bit register r10
  677 reg_class r10_reg(
  678     R10, R10_H
  679 );
  680 
  681 // Class for 64 bit register r11
  682 reg_class r11_reg(
  683     R11, R11_H
  684 );
  685 
  686 // Class for 64 bit register r12
  687 reg_class r12_reg(
  688     R12, R12_H
  689 );
  690 
  691 // Class for 64 bit register r13
  692 reg_class r13_reg(
  693     R13, R13_H
  694 );
  695 
  696 // Class for 64 bit register r14
  697 reg_class r14_reg(
  698     R14, R14_H
  699 );
  700 
  701 // Class for 64 bit register r15
  702 reg_class r15_reg(
  703     R15, R15_H
  704 );
  705 
  706 // Class for 64 bit register r16
  707 reg_class r16_reg(
  708     R16, R16_H
  709 );
  710 
  711 // Class for method register
  712 reg_class method_reg(
  713     R31, R31_H
  714 );
  715 
  716 // Class for java thread register
  717 reg_class java_thread_reg(
  718     R23, R23_H
  719 );
  720 
  721 reg_class r28_reg(
  722     R28, R28_H
  723 );
  724 
  725 reg_class r29_reg(
  726     R29, R29_H
  727 );
  728 
  729 reg_class r30_reg(
  730     R30, R30_H
  731 );
  732 
  733 reg_class r31_reg(
  734     R31, R31_H
  735 );
  736 
  737 // Class for zero registesr
  738 reg_class zr_reg(
  739     R0, R0_H
  740 );
  741 
  742 // Class for thread register
  743 reg_class thread_reg(
  744     R4, R4_H
  745 );
  746 
  747 // Class for frame pointer register
  748 reg_class fp_reg(
  749     R8, R8_H
  750 );
  751 
  752 // Class for link register
  753 reg_class ra_reg(
  754     R1, R1_H
  755 );
  756 
  757 // Class for long sp register
  758 reg_class sp_reg(
  759     R2, R2_H
  760 );
  761 
  762 // Class for all float registers
  763 reg_class float_reg(
  764     F0,
  765     F1,
  766     F2,
  767     F3,
  768     F4,
  769     F5,
  770     F6,
  771     F7,
  772     F8,
  773     F9,
  774     F10,
  775     F11,
  776     F12,
  777     F13,
  778     F14,
  779     F15,
  780     F16,
  781     F17,
  782     F18,
  783     F19,
  784     F20,
  785     F21,
  786     F22,
  787     F23,
  788     F24,
  789     F25,
  790     F26,
  791     F27,
  792     F28,
  793     F29,
  794     F30,
  795     F31
  796 );
  797 
  798 // Double precision float registers have virtual `high halves' that
  799 // are needed by the allocator.
  800 // Class for all double registers
  801 reg_class double_reg(
  802     F0,  F0_H,
  803     F1,  F1_H,
  804     F2,  F2_H,
  805     F3,  F3_H,
  806     F4,  F4_H,
  807     F5,  F5_H,
  808     F6,  F6_H,
  809     F7,  F7_H,
  810     F8,  F8_H,
  811     F9,  F9_H,
  812     F10, F10_H,
  813     F11, F11_H,
  814     F12, F12_H,
  815     F13, F13_H,
  816     F14, F14_H,
  817     F15, F15_H,
  818     F16, F16_H,
  819     F17, F17_H,
  820     F18, F18_H,
  821     F19, F19_H,
  822     F20, F20_H,
  823     F21, F21_H,
  824     F22, F22_H,
  825     F23, F23_H,
  826     F24, F24_H,
  827     F25, F25_H,
  828     F26, F26_H,
  829     F27, F27_H,
  830     F28, F28_H,
  831     F29, F29_H,
  832     F30, F30_H,
  833     F31, F31_H
  834 );
  835 
  836 // Class for RVV vector registers
  837 // Note: v0, v30 and v31 are used as mask registers.
  838 reg_class vectora_reg(
  839     V1, V1_H, V1_J, V1_K,
  840     V2, V2_H, V2_J, V2_K,
  841     V3, V3_H, V3_J, V3_K,
  842     V4, V4_H, V4_J, V4_K,
  843     V5, V5_H, V5_J, V5_K,
  844     V6, V6_H, V6_J, V6_K,
  845     V7, V7_H, V7_J, V7_K,
  846     V8, V8_H, V8_J, V8_K,
  847     V9, V9_H, V9_J, V9_K,
  848     V10, V10_H, V10_J, V10_K,
  849     V11, V11_H, V11_J, V11_K,
  850     V12, V12_H, V12_J, V12_K,
  851     V13, V13_H, V13_J, V13_K,
  852     V14, V14_H, V14_J, V14_K,
  853     V15, V15_H, V15_J, V15_K,
  854     V16, V16_H, V16_J, V16_K,
  855     V17, V17_H, V17_J, V17_K,
  856     V18, V18_H, V18_J, V18_K,
  857     V19, V19_H, V19_J, V19_K,
  858     V20, V20_H, V20_J, V20_K,
  859     V21, V21_H, V21_J, V21_K,
  860     V22, V22_H, V22_J, V22_K,
  861     V23, V23_H, V23_J, V23_K,
  862     V24, V24_H, V24_J, V24_K,
  863     V25, V25_H, V25_J, V25_K,
  864     V26, V26_H, V26_J, V26_K,
  865     V27, V27_H, V27_J, V27_K,
  866     V28, V28_H, V28_J, V28_K,
  867     V29, V29_H, V29_J, V29_K
  868 );
  869 
  870 // Class for 64 bit register f0
  871 reg_class f0_reg(
  872     F0, F0_H
  873 );
  874 
  875 // Class for 64 bit register f1
  876 reg_class f1_reg(
  877     F1, F1_H
  878 );
  879 
  880 // Class for 64 bit register f2
  881 reg_class f2_reg(
  882     F2, F2_H
  883 );
  884 
  885 // Class for 64 bit register f3
  886 reg_class f3_reg(
  887     F3, F3_H
  888 );
  889 
  890 // class for vector register v1
  891 reg_class v1_reg(
  892     V1, V1_H, V1_J, V1_K
  893 );
  894 
  895 // class for vector register v2
  896 reg_class v2_reg(
  897     V2, V2_H, V2_J, V2_K
  898 );
  899 
  900 // class for vector register v3
  901 reg_class v3_reg(
  902     V3, V3_H, V3_J, V3_K
  903 );
  904 
  905 // class for vector register v4
  906 reg_class v4_reg(
  907     V4, V4_H, V4_J, V4_K
  908 );
  909 
  910 // class for vector register v5
  911 reg_class v5_reg(
  912     V5, V5_H, V5_J, V5_K
  913 );
  914 
  915 // class for vector register v6
  916 reg_class v6_reg(
  917     V6, V6_H, V6_J, V6_K
  918 );
  919 
  920 // class for vector register v7
  921 reg_class v7_reg(
  922     V7, V7_H, V7_J, V7_K
  923 );
  924 
  925 // class for vector register v8
  926 reg_class v8_reg(
  927     V8, V8_H, V8_J, V8_K
  928 );
  929 
  930 // class for vector register v9
  931 reg_class v9_reg(
  932     V9, V9_H, V9_J, V9_K
  933 );
  934 
  935 // class for vector register v10
  936 reg_class v10_reg(
  937     V10, V10_H, V10_J, V10_K
  938 );
  939 
  940 // class for vector register v11
  941 reg_class v11_reg(
  942     V11, V11_H, V11_J, V11_K
  943 );
  944 
  945 // class for condition codes
  946 reg_class reg_flags(RFLAGS);
  947 
  948 // Class for RVV v0 mask register
  949 // https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#53-vector-masking
  950 // The mask value used to control execution of a masked vector
  951 // instruction is always supplied by vector register v0.
  952 reg_class vmask_reg_v0 (
  953     V0
  954 );
  955 
  956 // Class for RVV mask registers
  957 // We need two more vmask registers to do the vector mask logical ops,
  958 // so define v30, v31 as mask register too.
  959 reg_class vmask_reg (
  960     V0,
  961     V30,
  962     V31
  963 );
  964 %}
  965 
  966 //----------DEFINITION BLOCK---------------------------------------------------
  967 // Define name --> value mappings to inform the ADLC of an integer valued name
  968 // Current support includes integer values in the range [0, 0x7FFFFFFF]
  969 // Format:
  970 //        int_def  <name>         ( <int_value>, <expression>);
  971 // Generated Code in ad_<arch>.hpp
  972 //        #define  <name>   (<expression>)
  973 //        // value == <int_value>
  974 // Generated code in ad_<arch>.cpp adlc_verification()
  975 //        assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
  976 //
  977 
  978 // we follow the ppc-aix port in using a simple cost model which ranks
  979 // register operations as cheap, memory ops as more expensive and
  980 // branches as most expensive. the first two have a low as well as a
  981 // normal cost. huge cost appears to be a way of saying don't do
  982 // something
  983 
  984 definitions %{
  985   // The default cost (of a register move instruction).
  986   int_def DEFAULT_COST         (  100,               100);
  987   int_def ALU_COST             (  100,  1 * DEFAULT_COST);          // unknown, const, arith, shift, slt,
  988                                                                     // multi, auipc, nop, logical, move
  989   int_def LOAD_COST            (  300,  3 * DEFAULT_COST);          // load, fpload
  990   int_def STORE_COST           (  100,  1 * DEFAULT_COST);          // store, fpstore
  991   int_def XFER_COST            (  300,  3 * DEFAULT_COST);          // mfc, mtc, fcvt, fmove, fcmp
  992   int_def FMVX_COST            (  100,  1 * DEFAULT_COST);          // shuffles with no conversion
  993   int_def BRANCH_COST          (  200,  2 * DEFAULT_COST);          // branch, jmp, call
  994   int_def IMUL_COST            ( 1000, 10 * DEFAULT_COST);          // imul
  995   int_def IDIVSI_COST          ( 3400, 34 * DEFAULT_COST);          // idivsi
  996   int_def IDIVDI_COST          ( 6600, 66 * DEFAULT_COST);          // idivdi
  997   int_def FMUL_SINGLE_COST     (  500,  5 * DEFAULT_COST);          // fmul, fmadd
  998   int_def FMUL_DOUBLE_COST     (  700,  7 * DEFAULT_COST);          // fmul, fmadd
  999   int_def FDIV_COST            ( 2000, 20 * DEFAULT_COST);          // fdiv
 1000   int_def FSQRT_COST           ( 2500, 25 * DEFAULT_COST);          // fsqrt
 1001   int_def VOLATILE_REF_COST    ( 1000, 10 * DEFAULT_COST);
 1002   int_def CACHE_MISS_COST      ( 2000, 20 * DEFAULT_COST);          // typicall cache miss penalty
 1003 %}
 1004 
 1005 
 1006 
 1007 //----------SOURCE BLOCK-------------------------------------------------------
 1008 // This is a block of C++ code which provides values, functions, and
 1009 // definitions necessary in the rest of the architecture description
 1010 
 1011 source_hpp %{
 1012 
 1013 #include "asm/macroAssembler.hpp"
 1014 #include "gc/shared/barrierSetAssembler.hpp"
 1015 #include "gc/shared/cardTable.hpp"
 1016 #include "gc/shared/cardTableBarrierSet.hpp"
 1017 #include "gc/shared/collectedHeap.hpp"
 1018 #include "opto/addnode.hpp"
 1019 #include "opto/convertnode.hpp"
 1020 #include "runtime/objectMonitor.hpp"
 1021 
 1022 extern RegMask _ANY_REG32_mask;
 1023 extern RegMask _ANY_REG_mask;
 1024 extern RegMask _PTR_REG_mask;
 1025 extern RegMask _NO_SPECIAL_REG32_mask;
 1026 extern RegMask _NO_SPECIAL_REG_mask;
 1027 extern RegMask _NO_SPECIAL_PTR_REG_mask;
 1028 extern RegMask _NO_SPECIAL_NO_FP_PTR_REG_mask;
 1029 
 1030 class CallStubImpl {
 1031 
 1032   //--------------------------------------------------------------
 1033   //---<  Used for optimization in Compile::shorten_branches  >---
 1034   //--------------------------------------------------------------
 1035 
 1036  public:
 1037   // Size of call trampoline stub.
 1038   static uint size_call_trampoline() {
 1039     return 0; // no call trampolines on this platform
 1040   }
 1041 
 1042   // number of relocations needed by a call trampoline stub
 1043   static uint reloc_call_trampoline() {
 1044     return 0; // no call trampolines on this platform
 1045   }
 1046 };
 1047 
 1048 class HandlerImpl {
 1049 
 1050  public:
 1051 
 1052   static int emit_exception_handler(C2_MacroAssembler *masm);
 1053   static int emit_deopt_handler(C2_MacroAssembler* masm);
 1054 
 1055   static uint size_exception_handler() {
 1056     return MacroAssembler::far_branch_size();
 1057   }
 1058 
 1059   static uint size_deopt_handler() {
 1060     // count auipc + far branch
 1061     return NativeInstruction::instruction_size + MacroAssembler::far_branch_size();
 1062   }
 1063 };
 1064 
 1065 class Node::PD {
 1066 public:
 1067   enum NodeFlags {
 1068     _last_flag = Node::_last_flag
 1069   };
 1070 };
 1071 
 1072 bool is_CAS(int opcode, bool maybe_volatile);
 1073 
 1074 // predicate controlling translation of CompareAndSwapX
 1075 bool needs_acquiring_load_reserved(const Node *load);
 1076 
 1077 // predicate controlling addressing modes
 1078 bool size_fits_all_mem_uses(AddPNode* addp, int shift);
 1079 %}
 1080 
 1081 source %{
 1082 
 1083 // Derived RegMask with conditionally allocatable registers
 1084 
 1085 RegMask _ANY_REG32_mask;
 1086 RegMask _ANY_REG_mask;
 1087 RegMask _PTR_REG_mask;
 1088 RegMask _NO_SPECIAL_REG32_mask;
 1089 RegMask _NO_SPECIAL_REG_mask;
 1090 RegMask _NO_SPECIAL_PTR_REG_mask;
 1091 RegMask _NO_SPECIAL_NO_FP_PTR_REG_mask;
 1092 
 1093 void reg_mask_init() {
 1094 
 1095   _ANY_REG32_mask = _ALL_REG32_mask;
 1096   _ANY_REG32_mask.Remove(OptoReg::as_OptoReg(x0->as_VMReg()));
 1097 
 1098   _ANY_REG_mask = _ALL_REG_mask;
 1099   _ANY_REG_mask.SUBTRACT(_ZR_REG_mask);
 1100 
 1101   _PTR_REG_mask = _ALL_REG_mask;
 1102   _PTR_REG_mask.SUBTRACT(_ZR_REG_mask);
 1103 
 1104   _NO_SPECIAL_REG32_mask = _ALL_REG32_mask;
 1105   _NO_SPECIAL_REG32_mask.SUBTRACT(_NON_ALLOCATABLE_REG32_mask);
 1106 
 1107   _NO_SPECIAL_REG_mask = _ALL_REG_mask;
 1108   _NO_SPECIAL_REG_mask.SUBTRACT(_NON_ALLOCATABLE_REG_mask);
 1109 
 1110   _NO_SPECIAL_PTR_REG_mask = _ALL_REG_mask;
 1111   _NO_SPECIAL_PTR_REG_mask.SUBTRACT(_NON_ALLOCATABLE_REG_mask);
 1112 
 1113   // x27 is not allocatable when compressed oops is on
 1114   if (UseCompressedOops) {
 1115     _NO_SPECIAL_REG32_mask.Remove(OptoReg::as_OptoReg(x27->as_VMReg()));
 1116     _NO_SPECIAL_REG_mask.Remove(OptoReg::as_OptoReg(x27->as_VMReg()));
 1117     _NO_SPECIAL_PTR_REG_mask.Remove(OptoReg::as_OptoReg(x27->as_VMReg()));
 1118   }
 1119 
 1120   // x8 is not allocatable when PreserveFramePointer is on
 1121   if (PreserveFramePointer) {
 1122     _NO_SPECIAL_REG32_mask.Remove(OptoReg::as_OptoReg(x8->as_VMReg()));
 1123     _NO_SPECIAL_REG_mask.Remove(OptoReg::as_OptoReg(x8->as_VMReg()));
 1124     _NO_SPECIAL_PTR_REG_mask.Remove(OptoReg::as_OptoReg(x8->as_VMReg()));
 1125   }
 1126 
 1127   _NO_SPECIAL_NO_FP_PTR_REG_mask = _NO_SPECIAL_PTR_REG_mask;
 1128   _NO_SPECIAL_NO_FP_PTR_REG_mask.Remove(OptoReg::as_OptoReg(x8->as_VMReg()));
 1129 }
 1130 
 1131 void PhaseOutput::pd_perform_mach_node_analysis() {
 1132 }
 1133 
 1134 int MachNode::pd_alignment_required() const {
 1135   return 1;
 1136 }
 1137 
 1138 int MachNode::compute_padding(int current_offset) const {
 1139   return 0;
 1140 }
 1141 
 1142 // is_CAS(int opcode, bool maybe_volatile)
 1143 //
 1144 // return true if opcode is one of the possible CompareAndSwapX
 1145 // values otherwise false.
 1146 bool is_CAS(int opcode, bool maybe_volatile)
 1147 {
 1148   switch (opcode) {
 1149     // We handle these
 1150     case Op_CompareAndSwapI:
 1151     case Op_CompareAndSwapL:
 1152     case Op_CompareAndSwapP:
 1153     case Op_CompareAndSwapN:
 1154     case Op_ShenandoahCompareAndSwapP:
 1155     case Op_ShenandoahCompareAndSwapN:
 1156     case Op_CompareAndSwapB:
 1157     case Op_CompareAndSwapS:
 1158     case Op_GetAndSetI:
 1159     case Op_GetAndSetL:
 1160     case Op_GetAndSetP:
 1161     case Op_GetAndSetN:
 1162     case Op_GetAndAddI:
 1163     case Op_GetAndAddL:
 1164       return true;
 1165     case Op_CompareAndExchangeI:
 1166     case Op_CompareAndExchangeN:
 1167     case Op_CompareAndExchangeB:
 1168     case Op_CompareAndExchangeS:
 1169     case Op_CompareAndExchangeL:
 1170     case Op_CompareAndExchangeP:
 1171     case Op_WeakCompareAndSwapB:
 1172     case Op_WeakCompareAndSwapS:
 1173     case Op_WeakCompareAndSwapI:
 1174     case Op_WeakCompareAndSwapL:
 1175     case Op_WeakCompareAndSwapP:
 1176     case Op_WeakCompareAndSwapN:
 1177     case Op_ShenandoahWeakCompareAndSwapP:
 1178     case Op_ShenandoahWeakCompareAndSwapN:
 1179     case Op_ShenandoahCompareAndExchangeP:
 1180     case Op_ShenandoahCompareAndExchangeN:
 1181       return maybe_volatile;
 1182     default:
 1183       return false;
 1184   }
 1185 }
 1186 
 1187 // predicate controlling translation of CAS
 1188 //
 1189 // returns true if CAS needs to use an acquiring load otherwise false
 1190 bool needs_acquiring_load_reserved(const Node *n)
 1191 {
 1192   assert(n != nullptr && is_CAS(n->Opcode(), true), "expecting a compare and swap");
 1193 
 1194   LoadStoreNode* ldst = n->as_LoadStore();
 1195   if (n != nullptr && is_CAS(n->Opcode(), false)) {
 1196     assert(ldst != nullptr && ldst->trailing_membar() != nullptr, "expected trailing membar");
 1197   } else {
 1198     return ldst != nullptr && ldst->trailing_membar() != nullptr;
 1199   }
 1200   // so we can just return true here
 1201   return true;
 1202 }
 1203 #define __ masm->
 1204 
 1205 // advance declarations for helper functions to convert register
 1206 // indices to register objects
 1207 
 1208 // the ad file has to provide implementations of certain methods
 1209 // expected by the generic code
 1210 //
 1211 // REQUIRED FUNCTIONALITY
 1212 
 1213 //=============================================================================
 1214 
 1215 // !!!!! Special hack to get all types of calls to specify the byte offset
 1216 //       from the start of the call to the point where the return address
 1217 //       will point.
 1218 
 1219 int MachCallStaticJavaNode::ret_addr_offset()
 1220 {
 1221   return 3 * NativeInstruction::instruction_size; // auipc + ld + jalr
 1222 }
 1223 
 1224 int MachCallDynamicJavaNode::ret_addr_offset()
 1225 {
 1226   return NativeMovConstReg::movptr2_instruction_size + (3 * NativeInstruction::instruction_size); // movptr2, auipc + ld + jal
 1227 }
 1228 
 1229 int MachCallRuntimeNode::ret_addr_offset() {
 1230   // For address inside the code cache the call will be:
 1231   //   auipc + jalr
 1232   // For real runtime callouts it will be 8 instructions
 1233   // see riscv_enc_java_to_runtime
 1234   //   la(t0, retaddr)                                             ->  auipc + addi
 1235   //   sd(t0, Address(xthread, JavaThread::last_Java_pc_offset())) ->  sd
 1236   //   movptr(t1, addr, offset, t0)                                ->  lui + lui + slli + add
 1237   //   jalr(t1, offset)                                            ->  jalr
 1238   if (CodeCache::contains(_entry_point)) {
 1239     return 2 * NativeInstruction::instruction_size;
 1240   } else {
 1241     return 8 * NativeInstruction::instruction_size;
 1242   }
 1243 }
 1244 
 1245 //
 1246 // Compute padding required for nodes which need alignment
 1247 //
 1248 
 1249 // With RVC a call instruction may get 2-byte aligned.
 1250 // The address of the call instruction needs to be 4-byte aligned to
 1251 // ensure that it does not span a cache line so that it can be patched.
 1252 int CallStaticJavaDirectNode::compute_padding(int current_offset) const
 1253 {
 1254   // to make sure the address of jal 4-byte aligned.
 1255   return align_up(current_offset, alignment_required()) - current_offset;
 1256 }
 1257 
 1258 // With RVC a call instruction may get 2-byte aligned.
 1259 // The address of the call instruction needs to be 4-byte aligned to
 1260 // ensure that it does not span a cache line so that it can be patched.
 1261 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const
 1262 {
 1263   // skip the movptr2 in MacroAssembler::ic_call():
 1264   // lui, lui, slli, add, addi
 1265   // Though movptr2() has already 4-byte aligned with or without RVC,
 1266   // We need to prevent from further changes by explicitly calculating the size.
 1267   current_offset += NativeMovConstReg::movptr2_instruction_size;
 1268   // to make sure the address of jal 4-byte aligned.
 1269   return align_up(current_offset, alignment_required()) - current_offset;
 1270 }
 1271 
 1272 //=============================================================================
 1273 
 1274 #ifndef PRODUCT
 1275 void MachBreakpointNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
 1276   assert_cond(st != nullptr);
 1277   st->print("BREAKPOINT");
 1278 }
 1279 #endif
 1280 
 1281 void MachBreakpointNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
 1282   __ ebreak();
 1283 }
 1284 
 1285 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
 1286   return MachNode::size(ra_);
 1287 }
 1288 
 1289 //=============================================================================
 1290 
 1291 #ifndef PRODUCT
 1292   void MachNopNode::format(PhaseRegAlloc*, outputStream* st) const {
 1293     st->print("nop \t# %d bytes pad for loops and calls", _count);
 1294   }
 1295 #endif
 1296 
 1297   void MachNopNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc*) const {
 1298     Assembler::CompressibleScope scope(masm); // nops shall be 2-byte under RVC for alignment purposes.
 1299     for (int i = 0; i < _count; i++) {
 1300       __ nop();
 1301     }
 1302   }
 1303 
 1304   uint MachNopNode::size(PhaseRegAlloc*) const {
 1305     return _count * (UseRVC ? NativeInstruction::compressed_instruction_size : NativeInstruction::instruction_size);
 1306   }
 1307 
 1308 //=============================================================================
 1309 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;
 1310 
 1311 int ConstantTable::calculate_table_base_offset() const {
 1312   return 0;  // absolute addressing, no offset
 1313 }
 1314 
 1315 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
 1316 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
 1317   ShouldNotReachHere();
 1318 }
 1319 
 1320 void MachConstantBaseNode::emit(C2_MacroAssembler* masm, PhaseRegAlloc* ra_) const {
 1321   // Empty encoding
 1322 }
 1323 
 1324 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
 1325   return 0;
 1326 }
 1327 
 1328 #ifndef PRODUCT
 1329 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
 1330   assert_cond(st != nullptr);
 1331   st->print("-- \t// MachConstantBaseNode (empty encoding)");
 1332 }
 1333 #endif
 1334 
 1335 #ifndef PRODUCT
 1336 void MachPrologNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
 1337   assert_cond(st != nullptr && ra_ != nullptr);
 1338   Compile* C = ra_->C;
 1339 
 1340   int framesize = C->output()->frame_slots() << LogBytesPerInt;
 1341 
 1342   if (C->output()->need_stack_bang(framesize)) {
 1343     st->print("# stack bang size=%d\n\t", framesize);
 1344   }
 1345 
 1346   st->print("sd  fp, [sp, #%d]\n\t", - 2 * wordSize);
 1347   st->print("sd  ra, [sp, #%d]\n\t", - wordSize);
 1348   if (PreserveFramePointer) { st->print("sub  fp, sp, #%d\n\t", 2 * wordSize); }
 1349   st->print("sub sp, sp, #%d\n\t", framesize);
 1350 
 1351   if (C->stub_function() == nullptr) {
 1352     st->print("ld  t0, [guard]\n\t");
 1353     st->print("membar LoadLoad\n\t");
 1354     st->print("ld  t1, [xthread, #thread_disarmed_guard_value_offset]\n\t");
 1355     st->print("beq t0, t1, skip\n\t");
 1356     st->print("jalr #nmethod_entry_barrier_stub\n\t");
 1357     st->print("j skip\n\t");
 1358     st->print("guard: int\n\t");
 1359     st->print("skip:\n\t");
 1360   }
 1361 }
 1362 #endif
 1363 
 1364 void MachPrologNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
 1365   assert_cond(ra_ != nullptr);
 1366   Compile* C = ra_->C;
 1367 
 1368   // n.b. frame size includes space for return pc and fp
 1369   const int framesize = C->output()->frame_size_in_bytes();
 1370 
 1371   assert_cond(C != nullptr);
 1372 
 1373   if (C->clinit_barrier_on_entry()) {
 1374     assert(!C->method()->holder()->is_not_initialized(), "initialization should have been started");
 1375 
 1376     Label L_skip_barrier;
 1377 
 1378     __ mov_metadata(t1, C->method()->holder()->constant_encoding());
 1379     __ clinit_barrier(t1, t0, &L_skip_barrier);
 1380     __ far_jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub()));
 1381     __ bind(L_skip_barrier);
 1382   }
 1383 
 1384   int bangsize = C->output()->bang_size_in_bytes();
 1385   if (C->output()->need_stack_bang(bangsize)) {
 1386     __ generate_stack_overflow_check(bangsize);
 1387   }
 1388 
 1389   __ build_frame(framesize);
 1390 
 1391   if (C->stub_function() == nullptr) {
 1392     BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
 1393     // Dummy labels for just measuring the code size
 1394     Label dummy_slow_path;
 1395     Label dummy_continuation;
 1396     Label dummy_guard;
 1397     Label* slow_path = &dummy_slow_path;
 1398     Label* continuation = &dummy_continuation;
 1399     Label* guard = &dummy_guard;
 1400     if (!Compile::current()->output()->in_scratch_emit_size()) {
 1401       // Use real labels from actual stub when not emitting code for purpose of measuring its size
 1402       C2EntryBarrierStub* stub = new (Compile::current()->comp_arena()) C2EntryBarrierStub();
 1403       Compile::current()->output()->add_stub(stub);
 1404       slow_path = &stub->entry();
 1405       continuation = &stub->continuation();
 1406       guard = &stub->guard();
 1407     }
 1408     // In the C2 code, we move the non-hot part of nmethod entry barriers out-of-line to a stub.
 1409     bs->nmethod_entry_barrier(masm, slow_path, continuation, guard);
 1410   }
 1411 
 1412   if (VerifyStackAtCalls) {
 1413     Unimplemented();
 1414   }
 1415 
 1416   C->output()->set_frame_complete(__ offset());
 1417 
 1418   if (C->has_mach_constant_base_node()) {
 1419     // NOTE: We set the table base offset here because users might be
 1420     // emitted before MachConstantBaseNode.
 1421     ConstantTable& constant_table = C->output()->constant_table();
 1422     constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
 1423   }
 1424 }
 1425 
 1426 uint MachPrologNode::size(PhaseRegAlloc* ra_) const
 1427 {
 1428   assert_cond(ra_ != nullptr);
 1429   return MachNode::size(ra_); // too many variables; just compute it
 1430                               // the hard way
 1431 }
 1432 
 1433 int MachPrologNode::reloc() const
 1434 {
 1435   return 0;
 1436 }
 1437 
 1438 //=============================================================================
 1439 
 1440 #ifndef PRODUCT
 1441 void MachEpilogNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
 1442   assert_cond(st != nullptr && ra_ != nullptr);
 1443   Compile* C = ra_->C;
 1444   assert_cond(C != nullptr);
 1445   int framesize = C->output()->frame_size_in_bytes();
 1446 
 1447   st->print("# pop frame %d\n\t", framesize);
 1448 
 1449   if (framesize == 0) {
 1450     st->print("ld  ra, [sp,#%d]\n\t", (2 * wordSize));
 1451     st->print("ld  fp, [sp,#%d]\n\t", (3 * wordSize));
 1452     st->print("add sp, sp, #%d\n\t", (2 * wordSize));
 1453   } else {
 1454     st->print("add  sp, sp, #%d\n\t", framesize);
 1455     st->print("ld  ra, [sp,#%d]\n\t", - 2 * wordSize);
 1456     st->print("ld  fp, [sp,#%d]\n\t", - wordSize);
 1457   }
 1458 
 1459   if (do_polling() && C->is_method_compilation()) {
 1460     st->print("# test polling word\n\t");
 1461     st->print("ld t0, [xthread,#%d]\n\t", in_bytes(JavaThread::polling_word_offset()));
 1462     st->print("bgtu sp, t0, #slow_path");
 1463   }
 1464 }
 1465 #endif
 1466 
 1467 void MachEpilogNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
 1468   assert_cond(ra_ != nullptr);
 1469   Compile* C = ra_->C;
 1470   assert_cond(C != nullptr);
 1471   int framesize = C->output()->frame_size_in_bytes();
 1472 
 1473   __ remove_frame(framesize);
 1474 
 1475   if (StackReservedPages > 0 && C->has_reserved_stack_access()) {
 1476     __ reserved_stack_check();
 1477   }
 1478 
 1479   if (do_polling() && C->is_method_compilation()) {
 1480     Label dummy_label;
 1481     Label* code_stub = &dummy_label;
 1482     if (!C->output()->in_scratch_emit_size()) {
 1483       C2SafepointPollStub* stub = new (C->comp_arena()) C2SafepointPollStub(__ offset());
 1484       C->output()->add_stub(stub);
 1485       code_stub = &stub->entry();
 1486     }
 1487     __ relocate(relocInfo::poll_return_type);
 1488     __ safepoint_poll(*code_stub, true /* at_return */, true /* in_nmethod */);
 1489   }
 1490 }
 1491 
 1492 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
 1493   assert_cond(ra_ != nullptr);
 1494   // Variable size. Determine dynamically.
 1495   return MachNode::size(ra_);
 1496 }
 1497 
 1498 int MachEpilogNode::reloc() const {
 1499   // Return number of relocatable values contained in this instruction.
 1500   return 1; // 1 for polling page.
 1501 }
 1502 const Pipeline * MachEpilogNode::pipeline() const {
 1503   return MachNode::pipeline_class();
 1504 }
 1505 
 1506 //=============================================================================
 1507 
 1508 // Figure out which register class each belongs in: rc_int, rc_float or
 1509 // rc_stack.
 1510 enum RC { rc_bad, rc_int, rc_float, rc_vector, rc_stack };
 1511 
 1512 static enum RC rc_class(OptoReg::Name reg) {
 1513 
 1514   if (reg == OptoReg::Bad) {
 1515     return rc_bad;
 1516   }
 1517 
 1518   // we have 30 int registers * 2 halves
 1519   // (t0 and t1 are omitted)
 1520   int slots_of_int_registers = Register::max_slots_per_register * (Register::number_of_registers - 2);
 1521   if (reg < slots_of_int_registers) {
 1522     return rc_int;
 1523   }
 1524 
 1525   // we have 32 float register * 2 halves
 1526   int slots_of_float_registers = FloatRegister::max_slots_per_register * FloatRegister::number_of_registers;
 1527   if (reg < slots_of_int_registers + slots_of_float_registers) {
 1528     return rc_float;
 1529   }
 1530 
 1531   // we have 32 vector register * 4 halves
 1532   int slots_of_vector_registers = VectorRegister::max_slots_per_register * VectorRegister::number_of_registers;
 1533   if (reg < slots_of_int_registers + slots_of_float_registers + slots_of_vector_registers) {
 1534     return rc_vector;
 1535   }
 1536 
 1537   // Between vector regs & stack is the flags regs.
 1538   assert(OptoReg::is_stack(reg), "blow up if spilling flags");
 1539 
 1540   return rc_stack;
 1541 }
 1542 
 1543 uint MachSpillCopyNode::implementation(C2_MacroAssembler *masm, PhaseRegAlloc *ra_, bool do_size, outputStream *st) const {
 1544   assert_cond(ra_ != nullptr);
 1545   Compile* C = ra_->C;
 1546 
 1547   // Get registers to move.
 1548   OptoReg::Name src_hi = ra_->get_reg_second(in(1));
 1549   OptoReg::Name src_lo = ra_->get_reg_first(in(1));
 1550   OptoReg::Name dst_hi = ra_->get_reg_second(this);
 1551   OptoReg::Name dst_lo = ra_->get_reg_first(this);
 1552 
 1553   enum RC src_hi_rc = rc_class(src_hi);
 1554   enum RC src_lo_rc = rc_class(src_lo);
 1555   enum RC dst_hi_rc = rc_class(dst_hi);
 1556   enum RC dst_lo_rc = rc_class(dst_lo);
 1557 
 1558   assert(src_lo != OptoReg::Bad && dst_lo != OptoReg::Bad, "must move at least 1 register");
 1559 
 1560   if (src_hi != OptoReg::Bad && !bottom_type()->isa_vectmask()) {
 1561     assert((src_lo & 1) == 0 && src_lo + 1 == src_hi &&
 1562            (dst_lo & 1) == 0 && dst_lo + 1 == dst_hi,
 1563            "expected aligned-adjacent pairs");
 1564   }
 1565 
 1566   if (src_lo == dst_lo && src_hi == dst_hi) {
 1567     return 0;            // Self copy, no move.
 1568   }
 1569 
 1570   bool is64 = (src_lo & 1) == 0 && src_lo + 1 == src_hi &&
 1571               (dst_lo & 1) == 0 && dst_lo + 1 == dst_hi;
 1572   int src_offset = ra_->reg2offset(src_lo);
 1573   int dst_offset = ra_->reg2offset(dst_lo);
 1574 
 1575   if (bottom_type()->isa_vect() != nullptr) {
 1576     uint ireg = ideal_reg();
 1577     if (ireg == Op_VecA && masm) {
 1578       int vector_reg_size_in_bytes = Matcher::scalable_vector_reg_size(T_BYTE);
 1579       if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
 1580         // stack to stack
 1581         __ spill_copy_vector_stack_to_stack(src_offset, dst_offset,
 1582                                             vector_reg_size_in_bytes);
 1583       } else if (src_lo_rc == rc_vector && dst_lo_rc == rc_stack) {
 1584         // vpr to stack
 1585         __ spill(as_VectorRegister(Matcher::_regEncode[src_lo]), ra_->reg2offset(dst_lo));
 1586       } else if (src_lo_rc == rc_stack && dst_lo_rc == rc_vector) {
 1587         // stack to vpr
 1588         __ unspill(as_VectorRegister(Matcher::_regEncode[dst_lo]), ra_->reg2offset(src_lo));
 1589       } else if (src_lo_rc == rc_vector && dst_lo_rc == rc_vector) {
 1590         // vpr to vpr
 1591         __ vsetvli_helper(T_BYTE, MaxVectorSize);
 1592         __ vmv_v_v(as_VectorRegister(Matcher::_regEncode[dst_lo]), as_VectorRegister(Matcher::_regEncode[src_lo]));
 1593       } else {
 1594         ShouldNotReachHere();
 1595       }
 1596     } else if (bottom_type()->isa_vectmask() && masm) {
 1597       int vmask_size_in_bytes = Matcher::scalable_predicate_reg_slots() * 32 / 8;
 1598       if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
 1599         // stack to stack
 1600         __ spill_copy_vmask_stack_to_stack(src_offset, dst_offset,
 1601                                            vmask_size_in_bytes);
 1602       } else if (src_lo_rc == rc_vector && dst_lo_rc == rc_stack) {
 1603         // vmask to stack
 1604         __ spill_vmask(as_VectorRegister(Matcher::_regEncode[src_lo]), ra_->reg2offset(dst_lo));
 1605       } else if (src_lo_rc == rc_stack && dst_lo_rc == rc_vector) {
 1606         // stack to vmask
 1607         __ unspill_vmask(as_VectorRegister(Matcher::_regEncode[dst_lo]), ra_->reg2offset(src_lo));
 1608       } else if (src_lo_rc == rc_vector && dst_lo_rc == rc_vector) {
 1609         // vmask to vmask
 1610         __ vsetvli_helper(T_BYTE, MaxVectorSize >> 3);
 1611         __ vmv_v_v(as_VectorRegister(Matcher::_regEncode[dst_lo]), as_VectorRegister(Matcher::_regEncode[src_lo]));
 1612       } else {
 1613         ShouldNotReachHere();
 1614       }
 1615     }
 1616   } else if (masm != nullptr) {
 1617     switch (src_lo_rc) {
 1618       case rc_int:
 1619         if (dst_lo_rc == rc_int) {  // gpr --> gpr copy
 1620           if (!is64 && this->ideal_reg() != Op_RegI) { // zero extended for narrow oop or klass
 1621             __ zext(as_Register(Matcher::_regEncode[dst_lo]), as_Register(Matcher::_regEncode[src_lo]), 32);
 1622           } else {
 1623             __ mv(as_Register(Matcher::_regEncode[dst_lo]), as_Register(Matcher::_regEncode[src_lo]));
 1624           }
 1625         } else if (dst_lo_rc == rc_float) { // gpr --> fpr copy
 1626           if (is64) {
 1627             __ fmv_d_x(as_FloatRegister(Matcher::_regEncode[dst_lo]),
 1628                        as_Register(Matcher::_regEncode[src_lo]));
 1629           } else {
 1630             __ fmv_w_x(as_FloatRegister(Matcher::_regEncode[dst_lo]),
 1631                        as_Register(Matcher::_regEncode[src_lo]));
 1632           }
 1633         } else {                    // gpr --> stack spill
 1634           assert(dst_lo_rc == rc_stack, "spill to bad register class");
 1635           __ spill(as_Register(Matcher::_regEncode[src_lo]), is64, dst_offset);
 1636         }
 1637         break;
 1638       case rc_float:
 1639         if (dst_lo_rc == rc_int) {  // fpr --> gpr copy
 1640           if (is64) {
 1641             __ fmv_x_d(as_Register(Matcher::_regEncode[dst_lo]),
 1642                        as_FloatRegister(Matcher::_regEncode[src_lo]));
 1643           } else {
 1644             __ fmv_x_w(as_Register(Matcher::_regEncode[dst_lo]),
 1645                        as_FloatRegister(Matcher::_regEncode[src_lo]));
 1646           }
 1647         } else if (dst_lo_rc == rc_float) { // fpr --> fpr copy
 1648           if (is64) {
 1649             __ fmv_d(as_FloatRegister(Matcher::_regEncode[dst_lo]),
 1650                      as_FloatRegister(Matcher::_regEncode[src_lo]));
 1651           } else {
 1652             __ fmv_s(as_FloatRegister(Matcher::_regEncode[dst_lo]),
 1653                      as_FloatRegister(Matcher::_regEncode[src_lo]));
 1654           }
 1655         } else {                    // fpr --> stack spill
 1656           assert(dst_lo_rc == rc_stack, "spill to bad register class");
 1657           __ spill(as_FloatRegister(Matcher::_regEncode[src_lo]),
 1658                    is64, dst_offset);
 1659         }
 1660         break;
 1661       case rc_stack:
 1662         if (dst_lo_rc == rc_int) {  // stack --> gpr load
 1663           if (this->ideal_reg() == Op_RegI) {
 1664             __ unspill(as_Register(Matcher::_regEncode[dst_lo]), is64, src_offset);
 1665           } else { // // zero extended for narrow oop or klass
 1666             __ unspillu(as_Register(Matcher::_regEncode[dst_lo]), is64, src_offset);
 1667           }
 1668         } else if (dst_lo_rc == rc_float) { // stack --> fpr load
 1669           __ unspill(as_FloatRegister(Matcher::_regEncode[dst_lo]),
 1670                      is64, src_offset);
 1671         } else {                    // stack --> stack copy
 1672           assert(dst_lo_rc == rc_stack, "spill to bad register class");
 1673           if (this->ideal_reg() == Op_RegI) {
 1674             __ unspill(t0, is64, src_offset);
 1675           } else { // zero extended for narrow oop or klass
 1676             __ unspillu(t0, is64, src_offset);
 1677           }
 1678           __ spill(t0, is64, dst_offset);
 1679         }
 1680         break;
 1681       default:
 1682         ShouldNotReachHere();
 1683     }
 1684   }
 1685 
 1686   if (st != nullptr) {
 1687     st->print("spill ");
 1688     if (src_lo_rc == rc_stack) {
 1689       st->print("[sp, #%d] -> ", src_offset);
 1690     } else {
 1691       st->print("%s -> ", Matcher::regName[src_lo]);
 1692     }
 1693     if (dst_lo_rc == rc_stack) {
 1694       st->print("[sp, #%d]", dst_offset);
 1695     } else {
 1696       st->print("%s", Matcher::regName[dst_lo]);
 1697     }
 1698     if (bottom_type()->isa_vect() && !bottom_type()->isa_vectmask()) {
 1699       int vsize = 0;
 1700       if (ideal_reg() == Op_VecA) {
 1701         vsize = Matcher::scalable_vector_reg_size(T_BYTE) * 8;
 1702       } else {
 1703         ShouldNotReachHere();
 1704       }
 1705       st->print("\t# vector spill size = %d", vsize);
 1706     } else if (ideal_reg() == Op_RegVectMask) {
 1707       assert(Matcher::supports_scalable_vector(), "bad register type for spill");
 1708       int vsize = Matcher::scalable_predicate_reg_slots() * 32;
 1709       st->print("\t# vmask spill size = %d", vsize);
 1710     } else {
 1711       st->print("\t# spill size = %d", is64 ? 64 : 32);
 1712     }
 1713   }
 1714 
 1715   return 0;
 1716 }
 1717 
 1718 #ifndef PRODUCT
 1719 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
 1720   if (ra_ == nullptr) {
 1721     st->print("N%d = SpillCopy(N%d)", _idx, in(1)->_idx);
 1722   } else {
 1723     implementation(nullptr, ra_, false, st);
 1724   }
 1725 }
 1726 #endif
 1727 
 1728 void MachSpillCopyNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
 1729   implementation(masm, ra_, false, nullptr);
 1730 }
 1731 
 1732 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
 1733   return MachNode::size(ra_);
 1734 }
 1735 
 1736 //=============================================================================
 1737 
 1738 #ifndef PRODUCT
 1739 void BoxLockNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
 1740   assert_cond(ra_ != nullptr && st != nullptr);
 1741   int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
 1742   int reg = ra_->get_reg_first(this);
 1743   st->print("add %s, sp, #%d\t# box lock",
 1744             Matcher::regName[reg], offset);
 1745 }
 1746 #endif
 1747 
 1748 void BoxLockNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
 1749   Assembler::IncompressibleScope scope(masm); // Fixed length: see BoxLockNode::size()
 1750 
 1751   assert_cond(ra_ != nullptr);
 1752   int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
 1753   int reg    = ra_->get_encode(this);
 1754 
 1755   if (Assembler::is_simm12(offset)) {
 1756     __ addi(as_Register(reg), sp, offset);
 1757   } else {
 1758     __ li32(t0, offset);
 1759     __ add(as_Register(reg), sp, t0);
 1760   }
 1761 }
 1762 
 1763 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
 1764   // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_).
 1765   int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
 1766 
 1767   if (Assembler::is_simm12(offset)) {
 1768     return NativeInstruction::instruction_size;
 1769   } else {
 1770     return 3 * NativeInstruction::instruction_size; // lui + addiw + add;
 1771   }
 1772 }
 1773 
 1774 //=============================================================================
 1775 
 1776 #ifndef PRODUCT
 1777 void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const
 1778 {
 1779   assert_cond(st != nullptr);
 1780   st->print_cr("# MachUEPNode");
 1781   if (UseCompressedClassPointers) {
 1782     st->print_cr("\tlwu t1, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass");
 1783     st->print_cr("\tlwu t2, [t0      + CompiledICData::speculated_klass_offset()]\t# compressed klass");
 1784   } else {
 1785     st->print_cr("\tld t1, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass");
 1786     st->print_cr("\tld t2, [t0      + CompiledICData::speculated_klass_offset()]\t# compressed klass");
 1787   }
 1788   st->print_cr("\tbeq t1, t2, ic_hit");
 1789   st->print_cr("\tj, SharedRuntime::_ic_miss_stub\t # Inline cache check");
 1790   st->print_cr("\tic_hit:");
 1791 }
 1792 #endif
 1793 
 1794 void MachUEPNode::emit(C2_MacroAssembler* masm, PhaseRegAlloc* ra_) const
 1795 {
 1796   // This is the unverified entry point.
 1797   __ ic_check(CodeEntryAlignment);
 1798 
 1799   // ic_check() aligns to CodeEntryAlignment >= InteriorEntryAlignment(min 16) > NativeInstruction::instruction_size(4).
 1800   assert(((__ offset()) % CodeEntryAlignment) == 0, "Misaligned verified entry point");
 1801 }
 1802 
 1803 uint MachUEPNode::size(PhaseRegAlloc* ra_) const
 1804 {
 1805   assert_cond(ra_ != nullptr);
 1806   return MachNode::size(ra_);
 1807 }
 1808 
 1809 // REQUIRED EMIT CODE
 1810 
 1811 //=============================================================================
 1812 
 1813 // Emit exception handler code.
 1814 int HandlerImpl::emit_exception_handler(C2_MacroAssembler* masm)
 1815 {
 1816   // auipc t1, #exception_blob_entry_point
 1817   // jr (offset)t1
 1818   // Note that the code buffer's insts_mark is always relative to insts.
 1819   // That's why we must use the macroassembler to generate a handler.
 1820   address base = __ start_a_stub(size_exception_handler());
 1821   if (base == nullptr) {
 1822     ciEnv::current()->record_failure("CodeCache is full");
 1823     return 0;  // CodeBuffer::expand failed
 1824   }
 1825   int offset = __ offset();
 1826   __ far_jump(RuntimeAddress(OptoRuntime::exception_blob()->entry_point()));
 1827   assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
 1828   __ end_a_stub();
 1829   return offset;
 1830 }
 1831 
 1832 // Emit deopt handler code.
 1833 int HandlerImpl::emit_deopt_handler(C2_MacroAssembler* masm)
 1834 {
 1835   address base = __ start_a_stub(size_deopt_handler());
 1836   if (base == nullptr) {
 1837     ciEnv::current()->record_failure("CodeCache is full");
 1838     return 0;  // CodeBuffer::expand failed
 1839   }
 1840   int offset = __ offset();
 1841 
 1842   __ auipc(ra, 0);
 1843   __ far_jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
 1844 
 1845   assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
 1846   __ end_a_stub();
 1847   return offset;
 1848 
 1849 }
 1850 // REQUIRED MATCHER CODE
 1851 
 1852 //=============================================================================
 1853 
 1854 bool Matcher::match_rule_supported(int opcode) {
 1855   if (!has_match_rule(opcode)) {
 1856     return false;
 1857   }
 1858 
 1859   switch (opcode) {
 1860     case Op_OnSpinWait:
 1861       return VM_Version::supports_on_spin_wait();
 1862     case Op_CacheWB:           // fall through
 1863     case Op_CacheWBPreSync:    // fall through
 1864     case Op_CacheWBPostSync:
 1865       if (!VM_Version::supports_data_cache_line_flush()) {
 1866         return false;
 1867       }
 1868       break;
 1869 
 1870     case Op_StrCompressedCopy: // fall through
 1871     case Op_StrInflatedCopy:   // fall through
 1872     case Op_CountPositives:    // fall through
 1873     case Op_EncodeISOArray:
 1874       return UseRVV;
 1875 
 1876     case Op_PopCountI:
 1877     case Op_PopCountL:
 1878       return UsePopCountInstruction;
 1879 
 1880     case Op_ReverseI:
 1881     case Op_ReverseL:
 1882       return UseZbkb;
 1883 
 1884     case Op_ReverseBytesI:
 1885     case Op_ReverseBytesL:
 1886     case Op_ReverseBytesS:
 1887     case Op_ReverseBytesUS:
 1888     case Op_RotateRight:
 1889     case Op_RotateLeft:
 1890     case Op_CountLeadingZerosI:
 1891     case Op_CountLeadingZerosL:
 1892     case Op_CountTrailingZerosI:
 1893     case Op_CountTrailingZerosL:
 1894       return UseZbb;
 1895 
 1896     case Op_FmaF:
 1897     case Op_FmaD:
 1898       return UseFMA;
 1899 
 1900     case Op_ConvHF2F:
 1901     case Op_ConvF2HF:
 1902       return VM_Version::supports_float16_float_conversion();
 1903     case Op_ReinterpretS2HF:
 1904     case Op_ReinterpretHF2S:
 1905       return UseZfh || UseZfhmin;
 1906     case Op_AddHF:
 1907     case Op_DivHF:
 1908     case Op_FmaHF:
 1909     case Op_MaxHF:
 1910     case Op_MinHF:
 1911     case Op_MulHF:
 1912     case Op_SqrtHF:
 1913     case Op_SubHF:
 1914       return UseZfh;
 1915 
 1916     case Op_CMoveF:
 1917     case Op_CMoveD:
 1918     case Op_CMoveP:
 1919     case Op_CMoveN:
 1920       return false;
 1921   }
 1922 
 1923   return true; // Per default match rules are supported.
 1924 }
 1925 
 1926 const RegMask* Matcher::predicate_reg_mask(void) {
 1927   return &_VMASK_REG_mask;
 1928 }
 1929 
 1930 // Vector calling convention not yet implemented.
 1931 bool Matcher::supports_vector_calling_convention(void) {
 1932   return EnableVectorSupport;
 1933 }
 1934 
 1935 OptoRegPair Matcher::vector_return_value(uint ideal_reg) {
 1936   assert(EnableVectorSupport, "sanity");
 1937   assert(ideal_reg == Op_VecA, "sanity");
 1938   // check more info at https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-cc.adoc
 1939   int lo = V8_num;
 1940   int hi = V8_K_num;
 1941   return OptoRegPair(hi, lo);
 1942 }
 1943 
 1944 // Is this branch offset short enough that a short branch can be used?
 1945 //
 1946 // NOTE: If the platform does not provide any short branch variants, then
 1947 //       this method should return false for offset 0.
 1948 // |---label(L1)-----|
 1949 // |-----------------|
 1950 // |-----------------|----------eq: float-------------------
 1951 // |-----------------| // far_cmpD_branch   |   cmpD_branch
 1952 // |------- ---------|    feq;              |      feq;
 1953 // |-far_cmpD_branch-|    beqz done;        |      bnez L;
 1954 // |-----------------|    j L;              |
 1955 // |-----------------|    bind(done);       |
 1956 // |-----------------|--------------------------------------
 1957 // |-----------------| // so shortBrSize = br_size - 4;
 1958 // |-----------------| // so offs = offset - shortBrSize + 4;
 1959 // |---label(L2)-----|
 1960 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
 1961   // The passed offset is relative to address of the branch.
 1962   int shortBrSize = br_size - 4;
 1963   int offs = offset - shortBrSize + 4;
 1964   return (-4096 <= offs && offs < 4096);
 1965 }
 1966 
 1967 // Vector width in bytes.
 1968 int Matcher::vector_width_in_bytes(BasicType bt) {
 1969   if (UseRVV) {
 1970     // The MaxVectorSize should have been set by detecting RVV max vector register size when check UseRVV.
 1971     // MaxVectorSize == VM_Version::_initial_vector_length
 1972     int size = MaxVectorSize;
 1973     // Minimum 2 values in vector
 1974     if (size < 2 * type2aelembytes(bt)) size = 0;
 1975     // But never < 4
 1976     if (size < 4) size = 0;
 1977     return size;
 1978   }
 1979   return 0;
 1980 }
 1981 
 1982 // Limits on vector size (number of elements) loaded into vector.
 1983 int Matcher::max_vector_size(const BasicType bt) {
 1984   return vector_width_in_bytes(bt) / type2aelembytes(bt);
 1985 }
 1986 
 1987 int Matcher::min_vector_size(const BasicType bt) {
 1988   int size;
 1989   switch(bt) {
 1990     case T_BOOLEAN:
 1991       // Load/store a vector mask with only 2 elements for vector types
 1992       // such as "2I/2F/2L/2D".
 1993       size = 2;
 1994       break;
 1995     case T_BYTE:
 1996       // Generate a "4B" vector, to support vector cast between "8B/16B"
 1997       // and "4S/4I/4L/4F/4D".
 1998       size = 4;
 1999       break;
 2000     case T_SHORT:
 2001       // Generate a "2S" vector, to support vector cast between "4S/8S"
 2002       // and "2I/2L/2F/2D".
 2003       size = 2;
 2004       break;
 2005     default:
 2006       // Limit the min vector length to 64-bit.
 2007       size = 8 / type2aelembytes(bt);
 2008       // The number of elements in a vector should be at least 2.
 2009       size = MAX2(size, 2);
 2010   }
 2011 
 2012   int max_size = max_vector_size(bt);
 2013   return MIN2(size, max_size);
 2014 }
 2015 
 2016 int Matcher::max_vector_size_auto_vectorization(const BasicType bt) {
 2017   return Matcher::max_vector_size(bt);
 2018 }
 2019 
 2020 // Vector ideal reg.
 2021 uint Matcher::vector_ideal_reg(int len) {
 2022   assert(MaxVectorSize >= len, "");
 2023   if (UseRVV) {
 2024     return Op_VecA;
 2025   }
 2026 
 2027   ShouldNotReachHere();
 2028   return 0;
 2029 }
 2030 
 2031 int Matcher::scalable_vector_reg_size(const BasicType bt) {
 2032   return Matcher::max_vector_size(bt);
 2033 }
 2034 
 2035 MachOper* Matcher::pd_specialize_generic_vector_operand(MachOper* original_opnd, uint ideal_reg, bool is_temp) {
 2036   ShouldNotReachHere(); // generic vector operands not supported
 2037   return nullptr;
 2038 }
 2039 
 2040 bool Matcher::is_reg2reg_move(MachNode* m) {
 2041   ShouldNotReachHere(); // generic vector operands not supported
 2042   return false;
 2043 }
 2044 
 2045 bool Matcher::is_generic_vector(MachOper* opnd) {
 2046   ShouldNotReachHere(); // generic vector operands not supported
 2047   return false;
 2048 }
 2049 
 2050 // Return whether or not this register is ever used as an argument.
 2051 // This function is used on startup to build the trampoline stubs in
 2052 // generateOptoStub.  Registers not mentioned will be killed by the VM
 2053 // call in the trampoline, and arguments in those registers not be
 2054 // available to the callee.
 2055 bool Matcher::can_be_java_arg(int reg)
 2056 {
 2057   return
 2058     reg ==  R10_num || reg == R10_H_num ||
 2059     reg ==  R11_num || reg == R11_H_num ||
 2060     reg ==  R12_num || reg == R12_H_num ||
 2061     reg ==  R13_num || reg == R13_H_num ||
 2062     reg ==  R14_num || reg == R14_H_num ||
 2063     reg ==  R15_num || reg == R15_H_num ||
 2064     reg ==  R16_num || reg == R16_H_num ||
 2065     reg ==  R17_num || reg == R17_H_num ||
 2066     reg ==  F10_num || reg == F10_H_num ||
 2067     reg ==  F11_num || reg == F11_H_num ||
 2068     reg ==  F12_num || reg == F12_H_num ||
 2069     reg ==  F13_num || reg == F13_H_num ||
 2070     reg ==  F14_num || reg == F14_H_num ||
 2071     reg ==  F15_num || reg == F15_H_num ||
 2072     reg ==  F16_num || reg == F16_H_num ||
 2073     reg ==  F17_num || reg == F17_H_num;
 2074 }
 2075 
 2076 bool Matcher::is_spillable_arg(int reg)
 2077 {
 2078   return can_be_java_arg(reg);
 2079 }
 2080 
 2081 uint Matcher::int_pressure_limit()
 2082 {
 2083   // A derived pointer is live at CallNode and then is flagged by RA
 2084   // as a spilled LRG. Spilling heuristics(Spill-USE) explicitly skip
 2085   // derived pointers and lastly fail to spill after reaching maximum
 2086   // number of iterations. Lowering the default pressure threshold to
 2087   // (_NO_SPECIAL_REG32_mask.Size() minus 1) forces CallNode to become
 2088   // a high register pressure area of the code so that split_DEF can
 2089   // generate DefinitionSpillCopy for the derived pointer.
 2090   uint default_int_pressure_threshold = _NO_SPECIAL_REG32_mask.Size() - 1;
 2091   if (!PreserveFramePointer) {
 2092     // When PreserveFramePointer is off, frame pointer is allocatable,
 2093     // but different from other SOC registers, it is excluded from
 2094     // fatproj's mask because its save type is No-Save. Decrease 1 to
 2095     // ensure high pressure at fatproj when PreserveFramePointer is off.
 2096     // See check_pressure_at_fatproj().
 2097     default_int_pressure_threshold--;
 2098   }
 2099   return (INTPRESSURE == -1) ? default_int_pressure_threshold : INTPRESSURE;
 2100 }
 2101 
 2102 uint Matcher::float_pressure_limit()
 2103 {
 2104   // _FLOAT_REG_mask is generated by adlc from the float_reg register class.
 2105   return (FLOATPRESSURE == -1) ? _FLOAT_REG_mask.Size() : FLOATPRESSURE;
 2106 }
 2107 
 2108 bool Matcher::use_asm_for_ldiv_by_con(jlong divisor) {
 2109   return false;
 2110 }
 2111 
 2112 RegMask Matcher::divI_proj_mask() {
 2113   ShouldNotReachHere();
 2114   return RegMask();
 2115 }
 2116 
 2117 // Register for MODI projection of divmodI.
 2118 RegMask Matcher::modI_proj_mask() {
 2119   ShouldNotReachHere();
 2120   return RegMask();
 2121 }
 2122 
 2123 // Register for DIVL projection of divmodL.
 2124 RegMask Matcher::divL_proj_mask() {
 2125   ShouldNotReachHere();
 2126   return RegMask();
 2127 }
 2128 
 2129 // Register for MODL projection of divmodL.
 2130 RegMask Matcher::modL_proj_mask() {
 2131   ShouldNotReachHere();
 2132   return RegMask();
 2133 }
 2134 
 2135 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
 2136   return FP_REG_mask();
 2137 }
 2138 
 2139 bool size_fits_all_mem_uses(AddPNode* addp, int shift) {
 2140   assert_cond(addp != nullptr);
 2141   for (DUIterator_Fast imax, i = addp->fast_outs(imax); i < imax; i++) {
 2142     Node* u = addp->fast_out(i);
 2143     if (u != nullptr && u->is_Mem()) {
 2144       int opsize = u->as_Mem()->memory_size();
 2145       assert(opsize > 0, "unexpected memory operand size");
 2146       if (u->as_Mem()->memory_size() != (1 << shift)) {
 2147         return false;
 2148       }
 2149     }
 2150   }
 2151   return true;
 2152 }
 2153 
 2154 // Binary src (Replicate scalar/immediate)
 2155 static bool is_vector_scalar_bitwise_pattern(Node* n, Node* m) {
 2156   if (n == nullptr || m == nullptr) {
 2157     return false;
 2158   }
 2159 
 2160   if (m->Opcode() != Op_Replicate) {
 2161     return false;
 2162   }
 2163 
 2164   switch (n->Opcode()) {
 2165     case Op_AndV:
 2166     case Op_OrV:
 2167     case Op_XorV:
 2168     case Op_AddVB:
 2169     case Op_AddVS:
 2170     case Op_AddVI:
 2171     case Op_AddVL:
 2172     case Op_SubVB:
 2173     case Op_SubVS:
 2174     case Op_SubVI:
 2175     case Op_SubVL:
 2176     case Op_MulVB:
 2177     case Op_MulVS:
 2178     case Op_MulVI:
 2179     case Op_MulVL: {
 2180       return true;
 2181     }
 2182     default:
 2183       return false;
 2184   }
 2185 }
 2186 
 2187 // (XorV src (Replicate m1))
 2188 // (XorVMask src (MaskAll m1))
 2189 static bool is_vector_bitwise_not_pattern(Node* n, Node* m) {
 2190   if (n != nullptr && m != nullptr) {
 2191     return (n->Opcode() == Op_XorV || n->Opcode() == Op_XorVMask) &&
 2192            VectorNode::is_all_ones_vector(m);
 2193   }
 2194   return false;
 2195 }
 2196 
 2197 // Should the Matcher clone input 'm' of node 'n'?
 2198 bool Matcher::pd_clone_node(Node* n, Node* m, Matcher::MStack& mstack) {
 2199   assert_cond(m != nullptr);
 2200   if (is_vshift_con_pattern(n, m) || // ShiftV src (ShiftCntV con)
 2201       is_vector_bitwise_not_pattern(n, m) ||
 2202       is_vector_scalar_bitwise_pattern(n, m) ||
 2203       is_encode_and_store_pattern(n, m)) {
 2204     mstack.push(m, Visit);
 2205     return true;
 2206   }
 2207   return false;
 2208 }
 2209 
 2210 // Should the Matcher clone shifts on addressing modes, expecting them
 2211 // to be subsumed into complex addressing expressions or compute them
 2212 // into registers?
 2213 bool Matcher::pd_clone_address_expressions(AddPNode* m, Matcher::MStack& mstack, VectorSet& address_visited) {
 2214   return clone_base_plus_offset_address(m, mstack, address_visited);
 2215 }
 2216 
 2217 %}
 2218 
 2219 
 2220 
 2221 //----------ENCODING BLOCK-----------------------------------------------------
 2222 // This block specifies the encoding classes used by the compiler to
 2223 // output byte streams.  Encoding classes are parameterized macros
 2224 // used by Machine Instruction Nodes in order to generate the bit
 2225 // encoding of the instruction.  Operands specify their base encoding
 2226 // interface with the interface keyword.  There are currently
 2227 // supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, &
 2228 // COND_INTER.  REG_INTER causes an operand to generate a function
 2229 // which returns its register number when queried.  CONST_INTER causes
 2230 // an operand to generate a function which returns the value of the
 2231 // constant when queried.  MEMORY_INTER causes an operand to generate
 2232 // four functions which return the Base Register, the Index Register,
 2233 // the Scale Value, and the Offset Value of the operand when queried.
 2234 // COND_INTER causes an operand to generate six functions which return
 2235 // the encoding code (ie - encoding bits for the instruction)
 2236 // associated with each basic boolean condition for a conditional
 2237 // instruction.
 2238 //
 2239 // Instructions specify two basic values for encoding.  Again, a
 2240 // function is available to check if the constant displacement is an
 2241 // oop. They use the ins_encode keyword to specify their encoding
 2242 // classes (which must be a sequence of enc_class names, and their
 2243 // parameters, specified in the encoding block), and they use the
 2244 // opcode keyword to specify, in order, their primary, secondary, and
 2245 // tertiary opcode.  Only the opcode sections which a particular
 2246 // instruction needs for encoding need to be specified.
 2247 encode %{
 2248   // BEGIN Non-volatile memory access
 2249 
 2250   enc_class riscv_enc_mov_imm(iRegIorL dst, immIorL src) %{
 2251     int64_t con = (int64_t)$src$$constant;
 2252     Register dst_reg = as_Register($dst$$reg);
 2253     __ mv(dst_reg, con);
 2254   %}
 2255 
 2256   enc_class riscv_enc_mov_p(iRegP dst, immP src) %{
 2257     Register dst_reg = as_Register($dst$$reg);
 2258     address con = (address)$src$$constant;
 2259     if (con == nullptr || con == (address)1) {
 2260       ShouldNotReachHere();
 2261     } else {
 2262       relocInfo::relocType rtype = $src->constant_reloc();
 2263       if (rtype == relocInfo::oop_type) {
 2264         __ movoop(dst_reg, (jobject)con);
 2265       } else if (rtype == relocInfo::metadata_type) {
 2266         __ mov_metadata(dst_reg, (Metadata*)con);
 2267       } else {
 2268         assert(rtype == relocInfo::none, "unexpected reloc type");
 2269         __ mv(dst_reg, $src$$constant);
 2270       }
 2271     }
 2272   %}
 2273 
 2274   enc_class riscv_enc_mov_p1(iRegP dst) %{
 2275     Register dst_reg = as_Register($dst$$reg);
 2276     __ mv(dst_reg, 1);
 2277   %}
 2278 
 2279   enc_class riscv_enc_mov_byte_map_base(iRegP dst) %{
 2280     __ load_byte_map_base($dst$$Register);
 2281   %}
 2282 
 2283   enc_class riscv_enc_mov_n(iRegN dst, immN src) %{
 2284     Register dst_reg = as_Register($dst$$reg);
 2285     address con = (address)$src$$constant;
 2286     if (con == nullptr) {
 2287       ShouldNotReachHere();
 2288     } else {
 2289       relocInfo::relocType rtype = $src->constant_reloc();
 2290       assert(rtype == relocInfo::oop_type, "unexpected reloc type");
 2291       __ set_narrow_oop(dst_reg, (jobject)con);
 2292     }
 2293   %}
 2294 
 2295   enc_class riscv_enc_mov_zero(iRegNorP dst) %{
 2296     Register dst_reg = as_Register($dst$$reg);
 2297     __ mv(dst_reg, zr);
 2298   %}
 2299 
 2300   enc_class riscv_enc_mov_nk(iRegN dst, immNKlass src) %{
 2301     Register dst_reg = as_Register($dst$$reg);
 2302     address con = (address)$src$$constant;
 2303     if (con == nullptr) {
 2304       ShouldNotReachHere();
 2305     } else {
 2306       relocInfo::relocType rtype = $src->constant_reloc();
 2307       assert(rtype == relocInfo::metadata_type, "unexpected reloc type");
 2308       __ set_narrow_klass(dst_reg, (Klass *)con);
 2309     }
 2310   %}
 2311 
 2312   // compare and branch instruction encodings
 2313 
 2314   enc_class riscv_enc_j(label lbl) %{
 2315     Label* L = $lbl$$label;
 2316     __ j(*L);
 2317   %}
 2318 
 2319   enc_class riscv_enc_far_cmpULtGe_imm0_branch(cmpOpULtGe cmp, iRegIorL op1, label lbl) %{
 2320     Label* L = $lbl$$label;
 2321     switch ($cmp$$cmpcode) {
 2322       case(BoolTest::ge):
 2323         __ j(*L);
 2324         break;
 2325       case(BoolTest::lt):
 2326         break;
 2327       default:
 2328         Unimplemented();
 2329     }
 2330   %}
 2331 
 2332   // call instruction encodings
 2333 
 2334   enc_class riscv_enc_partial_subtype_check(iRegP sub, iRegP super, iRegP temp, iRegP result) %{
 2335     Register sub_reg = as_Register($sub$$reg);
 2336     Register super_reg = as_Register($super$$reg);
 2337     Register temp_reg = as_Register($temp$$reg);
 2338     Register result_reg = as_Register($result$$reg);
 2339     Register cr_reg = t1;
 2340 
 2341     Label miss;
 2342     Label done;
 2343     __ check_klass_subtype_slow_path(sub_reg, super_reg, temp_reg, result_reg,
 2344                                      nullptr, &miss, /*set_cond_codes*/ true);
 2345     if ($primary) {
 2346       __ mv(result_reg, zr);
 2347     } else {
 2348       __ mv(cr_reg, zr);
 2349       __ j(done);
 2350     }
 2351 
 2352     __ bind(miss);
 2353     if (!$primary) {
 2354       __ mv(cr_reg, 1);
 2355     }
 2356 
 2357     __ bind(done);
 2358   %}
 2359 
 2360   enc_class riscv_enc_java_static_call(method meth) %{
 2361     Assembler::IncompressibleScope scope(masm); // Fixed length: see ret_addr_offset
 2362 
 2363     address addr = (address)$meth$$method;
 2364     address call = nullptr;
 2365     assert_cond(addr != nullptr);
 2366     if (!_method) {
 2367       // A call to a runtime wrapper, e.g. new, new_typeArray_Java, uncommon_trap.
 2368       call = __ reloc_call(Address(addr, relocInfo::runtime_call_type));
 2369       if (call == nullptr) {
 2370         ciEnv::current()->record_failure("CodeCache is full");
 2371         return;
 2372       }
 2373     } else if (_method->intrinsic_id() == vmIntrinsicID::_ensureMaterializedForStackWalk) {
 2374       // The NOP here is purely to ensure that eliding a call to
 2375       // JVM_EnsureMaterializedForStackWalk doesn't change the code size.
 2376       __ nop();
 2377       __ nop();
 2378       __ nop();
 2379       __ block_comment("call JVM_EnsureMaterializedForStackWalk (elided)");
 2380     } else {
 2381       int method_index = resolved_method_index(masm);
 2382       RelocationHolder rspec = _optimized_virtual ? opt_virtual_call_Relocation::spec(method_index)
 2383                                                   : static_call_Relocation::spec(method_index);
 2384       call = __ reloc_call(Address(addr, rspec));
 2385       if (call == nullptr) {
 2386         ciEnv::current()->record_failure("CodeCache is full");
 2387         return;
 2388       }
 2389 
 2390       if (CodeBuffer::supports_shared_stubs() && _method->can_be_statically_bound()) {
 2391         // Calls of the same statically bound method can share
 2392         // a stub to the interpreter.
 2393         __ code()->shared_stub_to_interp_for(_method, call - (__ begin()));
 2394       } else {
 2395         // Emit stub for static call
 2396         address stub = CompiledDirectCall::emit_to_interp_stub(masm, call);
 2397         if (stub == nullptr) {
 2398           ciEnv::current()->record_failure("CodeCache is full");
 2399           return;
 2400         }
 2401       }
 2402     }
 2403 
 2404     __ post_call_nop();
 2405   %}
 2406 
 2407   enc_class riscv_enc_java_dynamic_call(method meth) %{
 2408     Assembler::IncompressibleScope scope(masm); // Fixed length: see ret_addr_offset
 2409     int method_index = resolved_method_index(masm);
 2410     address call = __ ic_call((address)$meth$$method, method_index);
 2411     if (call == nullptr) {
 2412       ciEnv::current()->record_failure("CodeCache is full");
 2413       return;
 2414     }
 2415 
 2416     __ post_call_nop();
 2417   %}
 2418 
 2419   enc_class riscv_enc_call_epilog() %{
 2420     if (VerifyStackAtCalls) {
 2421       // Check that stack depth is unchanged: find majik cookie on stack
 2422       __ call_Unimplemented();
 2423     }
 2424   %}
 2425 
 2426   enc_class riscv_enc_java_to_runtime(method meth) %{
 2427     Assembler::IncompressibleScope scope(masm); // Fixed length: see ret_addr_offset
 2428 
 2429     // Some calls to generated routines (arraycopy code) are scheduled by C2
 2430     // as runtime calls. if so we can call them using a far call (they will be
 2431     // in the code cache, thus in a reachable segment) otherwise we have to use
 2432     // a movptr+jalr pair which loads the absolute address into a register.
 2433     address entry = (address)$meth$$method;
 2434     if (CodeCache::contains(entry)) {
 2435       __ far_call(Address(entry, relocInfo::runtime_call_type));
 2436       __ post_call_nop();
 2437     } else {
 2438       Label retaddr;
 2439       // Make the anchor frame walkable
 2440       __ la(t0, retaddr);
 2441       __ sd(t0, Address(xthread, JavaThread::last_Java_pc_offset()));
 2442       int32_t offset = 0;
 2443       // No relocation needed
 2444       __ movptr(t1, entry, offset, t0); // lui + lui + slli + add
 2445       __ jalr(t1, offset);
 2446       __ bind(retaddr);
 2447       __ post_call_nop();
 2448     }
 2449   %}
 2450 
 2451   enc_class riscv_enc_tail_call(iRegP jump_target) %{
 2452     Register target_reg = as_Register($jump_target$$reg);
 2453     __ jr(target_reg);
 2454   %}
 2455 
 2456   enc_class riscv_enc_tail_jmp(iRegP jump_target) %{
 2457     Register target_reg = as_Register($jump_target$$reg);
 2458     // exception oop should be in x10
 2459     // ret addr has been popped into ra
 2460     // callee expects it in x13
 2461     __ mv(x13, ra);
 2462     __ jr(target_reg);
 2463   %}
 2464 
 2465   enc_class riscv_enc_rethrow() %{
 2466     __ far_jump(RuntimeAddress(OptoRuntime::rethrow_stub()));
 2467   %}
 2468 
 2469   enc_class riscv_enc_ret() %{
 2470     __ ret();
 2471   %}
 2472 
 2473 %}
 2474 
 2475 //----------FRAME--------------------------------------------------------------
 2476 // Definition of frame structure and management information.
 2477 //
 2478 //  S T A C K   L A Y O U T    Allocators stack-slot number
 2479 //                             |   (to get allocators register number
 2480 //  G  Owned by    |        |  v    add OptoReg::stack0())
 2481 //  r   CALLER     |        |
 2482 //  o     |        +--------+      pad to even-align allocators stack-slot
 2483 //  w     V        |  pad0  |        numbers; owned by CALLER
 2484 //  t   -----------+--------+----> Matcher::_in_arg_limit, unaligned
 2485 //  h     ^        |   in   |  5
 2486 //        |        |  args  |  4   Holes in incoming args owned by SELF
 2487 //  |     |        |        |  3
 2488 //  |     |        +--------+
 2489 //  V     |        | old out|      Empty on Intel, window on Sparc
 2490 //        |    old |preserve|      Must be even aligned.
 2491 //        |     SP-+--------+----> Matcher::_old_SP, even aligned
 2492 //        |        |   in   |  3   area for Intel ret address
 2493 //     Owned by    |preserve|      Empty on Sparc.
 2494 //       SELF      +--------+
 2495 //        |        |  pad2  |  2   pad to align old SP
 2496 //        |        +--------+  1
 2497 //        |        | locks  |  0
 2498 //        |        +--------+----> OptoReg::stack0(), even aligned
 2499 //        |        |  pad1  | 11   pad to align new SP
 2500 //        |        +--------+
 2501 //        |        |        | 10
 2502 //        |        | spills |  9   spills
 2503 //        V        |        |  8   (pad0 slot for callee)
 2504 //      -----------+--------+----> Matcher::_out_arg_limit, unaligned
 2505 //        ^        |  out   |  7
 2506 //        |        |  args  |  6   Holes in outgoing args owned by CALLEE
 2507 //     Owned by    +--------+
 2508 //      CALLEE     | new out|  6   Empty on Intel, window on Sparc
 2509 //        |    new |preserve|      Must be even-aligned.
 2510 //        |     SP-+--------+----> Matcher::_new_SP, even aligned
 2511 //        |        |        |
 2512 //
 2513 // Note 1: Only region 8-11 is determined by the allocator.  Region 0-5 is
 2514 //         known from SELF's arguments and the Java calling convention.
 2515 //         Region 6-7 is determined per call site.
 2516 // Note 2: If the calling convention leaves holes in the incoming argument
 2517 //         area, those holes are owned by SELF.  Holes in the outgoing area
 2518 //         are owned by the CALLEE.  Holes should not be necessary in the
 2519 //         incoming area, as the Java calling convention is completely under
 2520 //         the control of the AD file.  Doubles can be sorted and packed to
 2521 //         avoid holes.  Holes in the outgoing arguments may be necessary for
 2522 //         varargs C calling conventions.
 2523 // Note 3: Region 0-3 is even aligned, with pad2 as needed.  Region 3-5 is
 2524 //         even aligned with pad0 as needed.
 2525 //         Region 6 is even aligned.  Region 6-7 is NOT even aligned;
 2526 //           (the latter is true on Intel but is it false on RISCV?)
 2527 //         region 6-11 is even aligned; it may be padded out more so that
 2528 //         the region from SP to FP meets the minimum stack alignment.
 2529 // Note 4: For I2C adapters, the incoming FP may not meet the minimum stack
 2530 //         alignment.  Region 11, pad1, may be dynamically extended so that
 2531 //         SP meets the minimum alignment.
 2532 
 2533 frame %{
 2534   // These three registers define part of the calling convention
 2535   // between compiled code and the interpreter.
 2536 
 2537   // Inline Cache Register or methodOop for I2C.
 2538   inline_cache_reg(R31);
 2539 
 2540   // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
 2541   cisc_spilling_operand_name(indOffset);
 2542 
 2543   // Number of stack slots consumed by locking an object
 2544   // generate Compile::sync_stack_slots
 2545   // VMRegImpl::slots_per_word = wordSize / stack_slot_size = 8 / 4 = 2
 2546   sync_stack_slots(1 * VMRegImpl::slots_per_word);
 2547 
 2548   // Compiled code's Frame Pointer
 2549   frame_pointer(R2);
 2550 
 2551   // Interpreter stores its frame pointer in a register which is
 2552   // stored to the stack by I2CAdaptors.
 2553   // I2CAdaptors convert from interpreted java to compiled java.
 2554   interpreter_frame_pointer(R8);
 2555 
 2556   // Stack alignment requirement
 2557   stack_alignment(StackAlignmentInBytes); // Alignment size in bytes (128-bit -> 16 bytes)
 2558 
 2559   // Number of outgoing stack slots killed above the out_preserve_stack_slots
 2560   // for calls to C.  Supports the var-args backing area for register parms.
 2561   varargs_C_out_slots_killed(frame::arg_reg_save_area_bytes / BytesPerInt);
 2562 
 2563   // The after-PROLOG location of the return address.  Location of
 2564   // return address specifies a type (REG or STACK) and a number
 2565   // representing the register number (i.e. - use a register name) or
 2566   // stack slot.
 2567   // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
 2568   // Otherwise, it is above the locks and verification slot and alignment word
 2569   // TODO this may well be correct but need to check why that - 2 is there
 2570   // ppc port uses 0 but we definitely need to allow for fixed_slots
 2571   // which folds in the space used for monitors
 2572   return_addr(STACK - 2 +
 2573               align_up((Compile::current()->in_preserve_stack_slots() +
 2574                         Compile::current()->fixed_slots()),
 2575                        stack_alignment_in_slots()));
 2576 
 2577   // Location of compiled Java return values.  Same as C for now.
 2578   return_value
 2579   %{
 2580     assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL,
 2581            "only return normal values");
 2582 
 2583     static const int lo[Op_RegL + 1] = { // enum name
 2584       0,                                 // Op_Node
 2585       0,                                 // Op_Set
 2586       R10_num,                           // Op_RegN
 2587       R10_num,                           // Op_RegI
 2588       R10_num,                           // Op_RegP
 2589       F10_num,                           // Op_RegF
 2590       F10_num,                           // Op_RegD
 2591       R10_num                            // Op_RegL
 2592     };
 2593 
 2594     static const int hi[Op_RegL + 1] = { // enum name
 2595       0,                                 // Op_Node
 2596       0,                                 // Op_Set
 2597       OptoReg::Bad,                      // Op_RegN
 2598       OptoReg::Bad,                      // Op_RegI
 2599       R10_H_num,                         // Op_RegP
 2600       OptoReg::Bad,                      // Op_RegF
 2601       F10_H_num,                         // Op_RegD
 2602       R10_H_num                          // Op_RegL
 2603     };
 2604 
 2605     return OptoRegPair(hi[ideal_reg], lo[ideal_reg]);
 2606   %}
 2607 %}
 2608 
 2609 //----------ATTRIBUTES---------------------------------------------------------
 2610 //----------Operand Attributes-------------------------------------------------
 2611 op_attrib op_cost(1);        // Required cost attribute
 2612 
 2613 //----------Instruction Attributes---------------------------------------------
 2614 ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute
 2615 ins_attrib ins_size(32);        // Required size attribute (in bits)
 2616 ins_attrib ins_short_branch(0); // Required flag: is this instruction
 2617                                 // a non-matching short branch variant
 2618                                 // of some long branch?
 2619 ins_attrib ins_alignment(4);    // Required alignment attribute (must
 2620                                 // be a power of 2) specifies the
 2621                                 // alignment that some part of the
 2622                                 // instruction (not necessarily the
 2623                                 // start) requires.  If > 1, a
 2624                                 // compute_padding() function must be
 2625                                 // provided for the instruction
 2626 
 2627 // Whether this node is expanded during code emission into a sequence of
 2628 // instructions and the first instruction can perform an implicit null check.
 2629 ins_attrib ins_is_late_expanded_null_check_candidate(false);
 2630 
 2631 //----------OPERANDS-----------------------------------------------------------
 2632 // Operand definitions must precede instruction definitions for correct parsing
 2633 // in the ADLC because operands constitute user defined types which are used in
 2634 // instruction definitions.
 2635 
 2636 //----------Simple Operands----------------------------------------------------
 2637 
 2638 // Integer operands 32 bit
 2639 // 32 bit immediate
 2640 operand immI()
 2641 %{
 2642   match(ConI);
 2643 
 2644   op_cost(0);
 2645   format %{ %}
 2646   interface(CONST_INTER);
 2647 %}
 2648 
 2649 // 32 bit zero
 2650 operand immI0()
 2651 %{
 2652   predicate(n->get_int() == 0);
 2653   match(ConI);
 2654 
 2655   op_cost(0);
 2656   format %{ %}
 2657   interface(CONST_INTER);
 2658 %}
 2659 
 2660 // 32 bit unit increment
 2661 operand immI_1()
 2662 %{
 2663   predicate(n->get_int() == 1);
 2664   match(ConI);
 2665 
 2666   op_cost(0);
 2667   format %{ %}
 2668   interface(CONST_INTER);
 2669 %}
 2670 
 2671 // 32 bit unit decrement
 2672 operand immI_M1()
 2673 %{
 2674   predicate(n->get_int() == -1);
 2675   match(ConI);
 2676 
 2677   op_cost(0);
 2678   format %{ %}
 2679   interface(CONST_INTER);
 2680 %}
 2681 
 2682 // Unsigned Integer Immediate:  6-bit int, greater than 32
 2683 operand uimmI6_ge32() %{
 2684   predicate(((unsigned int)(n->get_int()) < 64) && (n->get_int() >= 32));
 2685   match(ConI);
 2686   op_cost(0);
 2687   format %{ %}
 2688   interface(CONST_INTER);
 2689 %}
 2690 
 2691 operand immI_le_4()
 2692 %{
 2693   predicate(n->get_int() <= 4);
 2694   match(ConI);
 2695 
 2696   op_cost(0);
 2697   format %{ %}
 2698   interface(CONST_INTER);
 2699 %}
 2700 
 2701 operand immI_16()
 2702 %{
 2703   predicate(n->get_int() == 16);
 2704   match(ConI);
 2705   op_cost(0);
 2706   format %{ %}
 2707   interface(CONST_INTER);
 2708 %}
 2709 
 2710 operand immI_24()
 2711 %{
 2712   predicate(n->get_int() == 24);
 2713   match(ConI);
 2714   op_cost(0);
 2715   format %{ %}
 2716   interface(CONST_INTER);
 2717 %}
 2718 
 2719 operand immI_31()
 2720 %{
 2721   predicate(n->get_int() == 31);
 2722   match(ConI);
 2723 
 2724   op_cost(0);
 2725   format %{ %}
 2726   interface(CONST_INTER);
 2727 %}
 2728 
 2729 operand immI_63()
 2730 %{
 2731   predicate(n->get_int() == 63);
 2732   match(ConI);
 2733 
 2734   op_cost(0);
 2735   format %{ %}
 2736   interface(CONST_INTER);
 2737 %}
 2738 
 2739 // 32 bit integer valid for add immediate
 2740 operand immIAdd()
 2741 %{
 2742   predicate(Assembler::is_simm12((int64_t)n->get_int()));
 2743   match(ConI);
 2744   op_cost(0);
 2745   format %{ %}
 2746   interface(CONST_INTER);
 2747 %}
 2748 
 2749 // 32 bit integer valid for sub immediate
 2750 operand immISub()
 2751 %{
 2752   predicate(Assembler::is_simm12(-(int64_t)n->get_int()));
 2753   match(ConI);
 2754   op_cost(0);
 2755   format %{ %}
 2756   interface(CONST_INTER);
 2757 %}
 2758 
 2759 // 5 bit signed value.
 2760 operand immI5()
 2761 %{
 2762   predicate(n->get_int() <= 15 && n->get_int() >= -16);
 2763   match(ConI);
 2764 
 2765   op_cost(0);
 2766   format %{ %}
 2767   interface(CONST_INTER);
 2768 %}
 2769 
 2770 // 5 bit signed value (simm5)
 2771 operand immL5()
 2772 %{
 2773   predicate(n->get_long() <= 15 && n->get_long() >= -16);
 2774   match(ConL);
 2775 
 2776   op_cost(0);
 2777   format %{ %}
 2778   interface(CONST_INTER);
 2779 %}
 2780 
 2781 // Integer operands 64 bit
 2782 // 64 bit immediate
 2783 operand immL()
 2784 %{
 2785   match(ConL);
 2786 
 2787   op_cost(0);
 2788   format %{ %}
 2789   interface(CONST_INTER);
 2790 %}
 2791 
 2792 // 64 bit zero
 2793 operand immL0()
 2794 %{
 2795   predicate(n->get_long() == 0);
 2796   match(ConL);
 2797 
 2798   op_cost(0);
 2799   format %{ %}
 2800   interface(CONST_INTER);
 2801 %}
 2802 
 2803 // Pointer operands
 2804 // Pointer Immediate
 2805 operand immP()
 2806 %{
 2807   match(ConP);
 2808 
 2809   op_cost(0);
 2810   format %{ %}
 2811   interface(CONST_INTER);
 2812 %}
 2813 
 2814 // Null Pointer Immediate
 2815 operand immP0()
 2816 %{
 2817   predicate(n->get_ptr() == 0);
 2818   match(ConP);
 2819 
 2820   op_cost(0);
 2821   format %{ %}
 2822   interface(CONST_INTER);
 2823 %}
 2824 
 2825 // Pointer Immediate One
 2826 // this is used in object initialization (initial object header)
 2827 operand immP_1()
 2828 %{
 2829   predicate(n->get_ptr() == 1);
 2830   match(ConP);
 2831 
 2832   op_cost(0);
 2833   format %{ %}
 2834   interface(CONST_INTER);
 2835 %}
 2836 
 2837 // Card Table Byte Map Base
 2838 operand immByteMapBase()
 2839 %{
 2840   // Get base of card map
 2841   predicate(BarrierSet::barrier_set()->is_a(BarrierSet::CardTableBarrierSet) &&
 2842             SHENANDOAHGC_ONLY(!BarrierSet::barrier_set()->is_a(BarrierSet::ShenandoahBarrierSet) &&)
 2843             (CardTable::CardValue*)n->get_ptr() ==
 2844              ((CardTableBarrierSet*)(BarrierSet::barrier_set()))->card_table()->byte_map_base());
 2845   match(ConP);
 2846 
 2847   op_cost(0);
 2848   format %{ %}
 2849   interface(CONST_INTER);
 2850 %}
 2851 
 2852 // Int Immediate: low 16-bit mask
 2853 operand immI_16bits()
 2854 %{
 2855   predicate(n->get_int() == 0xFFFF);
 2856   match(ConI);
 2857   op_cost(0);
 2858   format %{ %}
 2859   interface(CONST_INTER);
 2860 %}
 2861 
 2862 operand immIpowerOf2() %{
 2863   predicate(is_power_of_2((juint)(n->get_int())));
 2864   match(ConI);
 2865   op_cost(0);
 2866   format %{ %}
 2867   interface(CONST_INTER);
 2868 %}
 2869 
 2870 // Long Immediate: low 32-bit mask
 2871 operand immL_32bits()
 2872 %{
 2873   predicate(n->get_long() == 0xFFFFFFFFL);
 2874   match(ConL);
 2875   op_cost(0);
 2876   format %{ %}
 2877   interface(CONST_INTER);
 2878 %}
 2879 
 2880 // 64 bit unit decrement
 2881 operand immL_M1()
 2882 %{
 2883   predicate(n->get_long() == -1);
 2884   match(ConL);
 2885 
 2886   op_cost(0);
 2887   format %{ %}
 2888   interface(CONST_INTER);
 2889 %}
 2890 
 2891 
 2892 // 64 bit integer valid for add immediate
 2893 operand immLAdd()
 2894 %{
 2895   predicate(Assembler::is_simm12(n->get_long()));
 2896   match(ConL);
 2897   op_cost(0);
 2898   format %{ %}
 2899   interface(CONST_INTER);
 2900 %}
 2901 
 2902 // 64 bit integer valid for sub immediate
 2903 operand immLSub()
 2904 %{
 2905   predicate(Assembler::is_simm12(-(n->get_long())));
 2906   match(ConL);
 2907   op_cost(0);
 2908   format %{ %}
 2909   interface(CONST_INTER);
 2910 %}
 2911 
 2912 // Narrow pointer operands
 2913 // Narrow Pointer Immediate
 2914 operand immN()
 2915 %{
 2916   match(ConN);
 2917 
 2918   op_cost(0);
 2919   format %{ %}
 2920   interface(CONST_INTER);
 2921 %}
 2922 
 2923 // Narrow Null Pointer Immediate
 2924 operand immN0()
 2925 %{
 2926   predicate(n->get_narrowcon() == 0);
 2927   match(ConN);
 2928 
 2929   op_cost(0);
 2930   format %{ %}
 2931   interface(CONST_INTER);
 2932 %}
 2933 
 2934 operand immNKlass()
 2935 %{
 2936   match(ConNKlass);
 2937 
 2938   op_cost(0);
 2939   format %{ %}
 2940   interface(CONST_INTER);
 2941 %}
 2942 
 2943 // Float and Double operands
 2944 // Double Immediate
 2945 operand immD()
 2946 %{
 2947   match(ConD);
 2948   op_cost(0);
 2949   format %{ %}
 2950   interface(CONST_INTER);
 2951 %}
 2952 
 2953 // Double Immediate: +0.0d
 2954 operand immD0()
 2955 %{
 2956   predicate(jlong_cast(n->getd()) == 0);
 2957   match(ConD);
 2958 
 2959   op_cost(0);
 2960   format %{ %}
 2961   interface(CONST_INTER);
 2962 %}
 2963 
 2964 // Float Immediate
 2965 operand immF()
 2966 %{
 2967   match(ConF);
 2968   op_cost(0);
 2969   format %{ %}
 2970   interface(CONST_INTER);
 2971 %}
 2972 
 2973 // Float Immediate: +0.0f.
 2974 operand immF0()
 2975 %{
 2976   predicate(jint_cast(n->getf()) == 0);
 2977   match(ConF);
 2978 
 2979   op_cost(0);
 2980   format %{ %}
 2981   interface(CONST_INTER);
 2982 %}
 2983 
 2984 // Half Float Immediate
 2985 operand immH()
 2986 %{
 2987   match(ConH);
 2988 
 2989   op_cost(0);
 2990   format %{ %}
 2991   interface(CONST_INTER);
 2992 %}
 2993 
 2994 // Half Float Immediate: +0.0f.
 2995 operand immH0()
 2996 %{
 2997   predicate(jint_cast(n->geth()) == 0);
 2998   match(ConH);
 2999 
 3000   op_cost(0);
 3001   format %{ %}
 3002   interface(CONST_INTER);
 3003 %}
 3004 
 3005 operand immIOffset()
 3006 %{
 3007   predicate(Assembler::is_simm12(n->get_int()));
 3008   match(ConI);
 3009   op_cost(0);
 3010   format %{ %}
 3011   interface(CONST_INTER);
 3012 %}
 3013 
 3014 operand immLOffset()
 3015 %{
 3016   predicate(Assembler::is_simm12(n->get_long()));
 3017   match(ConL);
 3018   op_cost(0);
 3019   format %{ %}
 3020   interface(CONST_INTER);
 3021 %}
 3022 
 3023 // Scale values
 3024 operand immIScale()
 3025 %{
 3026   predicate(1 <= n->get_int() && (n->get_int() <= 3));
 3027   match(ConI);
 3028 
 3029   op_cost(0);
 3030   format %{ %}
 3031   interface(CONST_INTER);
 3032 %}
 3033 
 3034 // Integer 32 bit Register Operands
 3035 operand iRegI()
 3036 %{
 3037   constraint(ALLOC_IN_RC(any_reg32));
 3038   match(RegI);
 3039   match(iRegINoSp);
 3040   op_cost(0);
 3041   format %{ %}
 3042   interface(REG_INTER);
 3043 %}
 3044 
 3045 // Integer 32 bit Register not Special
 3046 operand iRegINoSp()
 3047 %{
 3048   constraint(ALLOC_IN_RC(no_special_reg32));
 3049   match(RegI);
 3050   op_cost(0);
 3051   format %{ %}
 3052   interface(REG_INTER);
 3053 %}
 3054 
 3055 // Register R10 only
 3056 operand iRegI_R10()
 3057 %{
 3058   constraint(ALLOC_IN_RC(int_r10_reg));
 3059   match(RegI);
 3060   match(iRegINoSp);
 3061   op_cost(0);
 3062   format %{ %}
 3063   interface(REG_INTER);
 3064 %}
 3065 
 3066 // Register R12 only
 3067 operand iRegI_R12()
 3068 %{
 3069   constraint(ALLOC_IN_RC(int_r12_reg));
 3070   match(RegI);
 3071   match(iRegINoSp);
 3072   op_cost(0);
 3073   format %{ %}
 3074   interface(REG_INTER);
 3075 %}
 3076 
 3077 // Register R13 only
 3078 operand iRegI_R13()
 3079 %{
 3080   constraint(ALLOC_IN_RC(int_r13_reg));
 3081   match(RegI);
 3082   match(iRegINoSp);
 3083   op_cost(0);
 3084   format %{ %}
 3085   interface(REG_INTER);
 3086 %}
 3087 
 3088 // Register R14 only
 3089 operand iRegI_R14()
 3090 %{
 3091   constraint(ALLOC_IN_RC(int_r14_reg));
 3092   match(RegI);
 3093   match(iRegINoSp);
 3094   op_cost(0);
 3095   format %{ %}
 3096   interface(REG_INTER);
 3097 %}
 3098 
 3099 // Integer 64 bit Register Operands
 3100 operand iRegL()
 3101 %{
 3102   constraint(ALLOC_IN_RC(any_reg));
 3103   match(RegL);
 3104   match(iRegLNoSp);
 3105   op_cost(0);
 3106   format %{ %}
 3107   interface(REG_INTER);
 3108 %}
 3109 
 3110 // Integer 64 bit Register not Special
 3111 operand iRegLNoSp()
 3112 %{
 3113   constraint(ALLOC_IN_RC(no_special_reg));
 3114   match(RegL);
 3115   match(iRegL_R10);
 3116   format %{ %}
 3117   interface(REG_INTER);
 3118 %}
 3119 
 3120 // Long 64 bit Register R29 only
 3121 operand iRegL_R29()
 3122 %{
 3123   constraint(ALLOC_IN_RC(r29_reg));
 3124   match(RegL);
 3125   match(iRegLNoSp);
 3126   op_cost(0);
 3127   format %{ %}
 3128   interface(REG_INTER);
 3129 %}
 3130 
 3131 // Long 64 bit Register R30 only
 3132 operand iRegL_R30()
 3133 %{
 3134   constraint(ALLOC_IN_RC(r30_reg));
 3135   match(RegL);
 3136   match(iRegLNoSp);
 3137   op_cost(0);
 3138   format %{ %}
 3139   interface(REG_INTER);
 3140 %}
 3141 
 3142 // Pointer Register Operands
 3143 // Pointer Register
 3144 operand iRegP()
 3145 %{
 3146   constraint(ALLOC_IN_RC(ptr_reg));
 3147   match(RegP);
 3148   match(iRegPNoSp);
 3149   match(iRegP_R10);
 3150   match(iRegP_R15);
 3151   match(javaThread_RegP);
 3152   op_cost(0);
 3153   format %{ %}
 3154   interface(REG_INTER);
 3155 %}
 3156 
 3157 // Pointer 64 bit Register not Special
 3158 operand iRegPNoSp()
 3159 %{
 3160   constraint(ALLOC_IN_RC(no_special_ptr_reg));
 3161   match(RegP);
 3162   op_cost(0);
 3163   format %{ %}
 3164   interface(REG_INTER);
 3165 %}
 3166 
 3167 // This operand is not allowed to use fp even if
 3168 // fp is not used to hold the frame pointer.
 3169 operand iRegPNoSpNoFp()
 3170 %{
 3171   constraint(ALLOC_IN_RC(no_special_no_fp_ptr_reg));
 3172   match(RegP);
 3173   match(iRegPNoSp);
 3174   op_cost(0);
 3175   format %{ %}
 3176   interface(REG_INTER);
 3177 %}
 3178 
 3179 operand iRegP_R10()
 3180 %{
 3181   constraint(ALLOC_IN_RC(r10_reg));
 3182   match(RegP);
 3183   // match(iRegP);
 3184   match(iRegPNoSp);
 3185   op_cost(0);
 3186   format %{ %}
 3187   interface(REG_INTER);
 3188 %}
 3189 
 3190 // Pointer 64 bit Register R11 only
 3191 operand iRegP_R11()
 3192 %{
 3193   constraint(ALLOC_IN_RC(r11_reg));
 3194   match(RegP);
 3195   match(iRegPNoSp);
 3196   op_cost(0);
 3197   format %{ %}
 3198   interface(REG_INTER);
 3199 %}
 3200 
 3201 operand iRegP_R12()
 3202 %{
 3203   constraint(ALLOC_IN_RC(r12_reg));
 3204   match(RegP);
 3205   // match(iRegP);
 3206   match(iRegPNoSp);
 3207   op_cost(0);
 3208   format %{ %}
 3209   interface(REG_INTER);
 3210 %}
 3211 
 3212 // Pointer 64 bit Register R13 only
 3213 operand iRegP_R13()
 3214 %{
 3215   constraint(ALLOC_IN_RC(r13_reg));
 3216   match(RegP);
 3217   match(iRegPNoSp);
 3218   op_cost(0);
 3219   format %{ %}
 3220   interface(REG_INTER);
 3221 %}
 3222 
 3223 operand iRegP_R14()
 3224 %{
 3225   constraint(ALLOC_IN_RC(r14_reg));
 3226   match(RegP);
 3227   // match(iRegP);
 3228   match(iRegPNoSp);
 3229   op_cost(0);
 3230   format %{ %}
 3231   interface(REG_INTER);
 3232 %}
 3233 
 3234 operand iRegP_R15()
 3235 %{
 3236   constraint(ALLOC_IN_RC(r15_reg));
 3237   match(RegP);
 3238   // match(iRegP);
 3239   match(iRegPNoSp);
 3240   op_cost(0);
 3241   format %{ %}
 3242   interface(REG_INTER);
 3243 %}
 3244 
 3245 operand iRegP_R16()
 3246 %{
 3247   constraint(ALLOC_IN_RC(r16_reg));
 3248   match(RegP);
 3249   match(iRegPNoSp);
 3250   op_cost(0);
 3251   format %{ %}
 3252   interface(REG_INTER);
 3253 %}
 3254 
 3255 // Pointer 64 bit Register R28 only
 3256 operand iRegP_R28()
 3257 %{
 3258   constraint(ALLOC_IN_RC(r28_reg));
 3259   match(RegP);
 3260   match(iRegPNoSp);
 3261   op_cost(0);
 3262   format %{ %}
 3263   interface(REG_INTER);
 3264 %}
 3265 
 3266 // Pointer 64 bit Register R30 only
 3267 operand iRegP_R30()
 3268 %{
 3269   constraint(ALLOC_IN_RC(r30_reg));
 3270   match(RegP);
 3271   match(iRegPNoSp);
 3272   op_cost(0);
 3273   format %{ %}
 3274   interface(REG_INTER);
 3275 %}
 3276 
 3277 // Pointer 64 bit Register R31 only
 3278 operand iRegP_R31()
 3279 %{
 3280   constraint(ALLOC_IN_RC(r31_reg));
 3281   match(RegP);
 3282   match(iRegPNoSp);
 3283   op_cost(0);
 3284   format %{ %}
 3285   interface(REG_INTER);
 3286 %}
 3287 
 3288 // Pointer Register Operands
 3289 // Narrow Pointer Register
 3290 operand iRegN()
 3291 %{
 3292   constraint(ALLOC_IN_RC(any_reg32));
 3293   match(RegN);
 3294   match(iRegNNoSp);
 3295   op_cost(0);
 3296   format %{ %}
 3297   interface(REG_INTER);
 3298 %}
 3299 
 3300 // Integer 64 bit Register not Special
 3301 operand iRegNNoSp()
 3302 %{
 3303   constraint(ALLOC_IN_RC(no_special_reg32));
 3304   match(RegN);
 3305   op_cost(0);
 3306   format %{ %}
 3307   interface(REG_INTER);
 3308 %}
 3309 
 3310 // Long 64 bit Register R10 only
 3311 operand iRegL_R10()
 3312 %{
 3313   constraint(ALLOC_IN_RC(r10_reg));
 3314   match(RegL);
 3315   match(iRegLNoSp);
 3316   op_cost(0);
 3317   format %{ %}
 3318   interface(REG_INTER);
 3319 %}
 3320 
 3321 // Float Register
 3322 // Float register operands
 3323 operand fRegF()
 3324 %{
 3325   constraint(ALLOC_IN_RC(float_reg));
 3326   match(RegF);
 3327 
 3328   op_cost(0);
 3329   format %{ %}
 3330   interface(REG_INTER);
 3331 %}
 3332 
 3333 // Double Register
 3334 // Double register operands
 3335 operand fRegD()
 3336 %{
 3337   constraint(ALLOC_IN_RC(double_reg));
 3338   match(RegD);
 3339 
 3340   op_cost(0);
 3341   format %{ %}
 3342   interface(REG_INTER);
 3343 %}
 3344 
 3345 // Generic vector class. This will be used for
 3346 // all vector operands.
 3347 operand vReg()
 3348 %{
 3349   constraint(ALLOC_IN_RC(vectora_reg));
 3350   match(VecA);
 3351   op_cost(0);
 3352   format %{ %}
 3353   interface(REG_INTER);
 3354 %}
 3355 
 3356 operand vReg_V1()
 3357 %{
 3358   constraint(ALLOC_IN_RC(v1_reg));
 3359   match(VecA);
 3360   match(vReg);
 3361   op_cost(0);
 3362   format %{ %}
 3363   interface(REG_INTER);
 3364 %}
 3365 
 3366 operand vReg_V2()
 3367 %{
 3368   constraint(ALLOC_IN_RC(v2_reg));
 3369   match(VecA);
 3370   match(vReg);
 3371   op_cost(0);
 3372   format %{ %}
 3373   interface(REG_INTER);
 3374 %}
 3375 
 3376 operand vReg_V3()
 3377 %{
 3378   constraint(ALLOC_IN_RC(v3_reg));
 3379   match(VecA);
 3380   match(vReg);
 3381   op_cost(0);
 3382   format %{ %}
 3383   interface(REG_INTER);
 3384 %}
 3385 
 3386 operand vReg_V4()
 3387 %{
 3388   constraint(ALLOC_IN_RC(v4_reg));
 3389   match(VecA);
 3390   match(vReg);
 3391   op_cost(0);
 3392   format %{ %}
 3393   interface(REG_INTER);
 3394 %}
 3395 
 3396 operand vReg_V5()
 3397 %{
 3398   constraint(ALLOC_IN_RC(v5_reg));
 3399   match(VecA);
 3400   match(vReg);
 3401   op_cost(0);
 3402   format %{ %}
 3403   interface(REG_INTER);
 3404 %}
 3405 
 3406 operand vReg_V6()
 3407 %{
 3408   constraint(ALLOC_IN_RC(v6_reg));
 3409   match(VecA);
 3410   match(vReg);
 3411   op_cost(0);
 3412   format %{ %}
 3413   interface(REG_INTER);
 3414 %}
 3415 
 3416 operand vReg_V7()
 3417 %{
 3418   constraint(ALLOC_IN_RC(v7_reg));
 3419   match(VecA);
 3420   match(vReg);
 3421   op_cost(0);
 3422   format %{ %}
 3423   interface(REG_INTER);
 3424 %}
 3425 
 3426 operand vReg_V8()
 3427 %{
 3428   constraint(ALLOC_IN_RC(v8_reg));
 3429   match(VecA);
 3430   match(vReg);
 3431   op_cost(0);
 3432   format %{ %}
 3433   interface(REG_INTER);
 3434 %}
 3435 
 3436 operand vReg_V9()
 3437 %{
 3438   constraint(ALLOC_IN_RC(v9_reg));
 3439   match(VecA);
 3440   match(vReg);
 3441   op_cost(0);
 3442   format %{ %}
 3443   interface(REG_INTER);
 3444 %}
 3445 
 3446 operand vReg_V10()
 3447 %{
 3448   constraint(ALLOC_IN_RC(v10_reg));
 3449   match(VecA);
 3450   match(vReg);
 3451   op_cost(0);
 3452   format %{ %}
 3453   interface(REG_INTER);
 3454 %}
 3455 
 3456 operand vReg_V11()
 3457 %{
 3458   constraint(ALLOC_IN_RC(v11_reg));
 3459   match(VecA);
 3460   match(vReg);
 3461   op_cost(0);
 3462   format %{ %}
 3463   interface(REG_INTER);
 3464 %}
 3465 
 3466 operand vRegMask()
 3467 %{
 3468   constraint(ALLOC_IN_RC(vmask_reg));
 3469   match(RegVectMask);
 3470   match(vRegMask_V0);
 3471   op_cost(0);
 3472   format %{ %}
 3473   interface(REG_INTER);
 3474 %}
 3475 
 3476 // The mask value used to control execution of a masked
 3477 // vector instruction is always supplied by vector register v0.
 3478 operand vRegMask_V0()
 3479 %{
 3480   constraint(ALLOC_IN_RC(vmask_reg_v0));
 3481   match(RegVectMask);
 3482   match(vRegMask);
 3483   op_cost(0);
 3484   format %{ %}
 3485   interface(REG_INTER);
 3486 %}
 3487 
 3488 // Java Thread Register
 3489 operand javaThread_RegP(iRegP reg)
 3490 %{
 3491   constraint(ALLOC_IN_RC(java_thread_reg)); // java_thread_reg
 3492   match(reg);
 3493   op_cost(0);
 3494   format %{ %}
 3495   interface(REG_INTER);
 3496 %}
 3497 
 3498 //----------Memory Operands----------------------------------------------------
 3499 // RISCV has only base_plus_offset and literal address mode, so no need to use
 3500 // index and scale. Here set index as 0xffffffff and scale as 0x0.
 3501 operand indirect(iRegP reg)
 3502 %{
 3503   constraint(ALLOC_IN_RC(ptr_reg));
 3504   match(reg);
 3505   op_cost(0);
 3506   format %{ "[$reg]" %}
 3507   interface(MEMORY_INTER) %{
 3508     base($reg);
 3509     index(0xffffffff);
 3510     scale(0x0);
 3511     disp(0x0);
 3512   %}
 3513 %}
 3514 
 3515 operand indOffI(iRegP reg, immIOffset off)
 3516 %{
 3517   constraint(ALLOC_IN_RC(ptr_reg));
 3518   match(AddP reg off);
 3519   op_cost(0);
 3520   format %{ "[$reg, $off]" %}
 3521   interface(MEMORY_INTER) %{
 3522     base($reg);
 3523     index(0xffffffff);
 3524     scale(0x0);
 3525     disp($off);
 3526   %}
 3527 %}
 3528 
 3529 operand indOffL(iRegP reg, immLOffset off)
 3530 %{
 3531   constraint(ALLOC_IN_RC(ptr_reg));
 3532   match(AddP reg off);
 3533   op_cost(0);
 3534   format %{ "[$reg, $off]" %}
 3535   interface(MEMORY_INTER) %{
 3536     base($reg);
 3537     index(0xffffffff);
 3538     scale(0x0);
 3539     disp($off);
 3540   %}
 3541 %}
 3542 
 3543 operand indirectN(iRegN reg)
 3544 %{
 3545   predicate(CompressedOops::shift() == 0);
 3546   constraint(ALLOC_IN_RC(ptr_reg));
 3547   match(DecodeN reg);
 3548   op_cost(0);
 3549   format %{ "[$reg]\t# narrow" %}
 3550   interface(MEMORY_INTER) %{
 3551     base($reg);
 3552     index(0xffffffff);
 3553     scale(0x0);
 3554     disp(0x0);
 3555   %}
 3556 %}
 3557 
 3558 operand indOffIN(iRegN reg, immIOffset off)
 3559 %{
 3560   predicate(CompressedOops::shift() == 0);
 3561   constraint(ALLOC_IN_RC(ptr_reg));
 3562   match(AddP (DecodeN reg) off);
 3563   op_cost(0);
 3564   format %{ "[$reg, $off]\t# narrow" %}
 3565   interface(MEMORY_INTER) %{
 3566     base($reg);
 3567     index(0xffffffff);
 3568     scale(0x0);
 3569     disp($off);
 3570   %}
 3571 %}
 3572 
 3573 operand indOffLN(iRegN reg, immLOffset off)
 3574 %{
 3575   predicate(CompressedOops::shift() == 0);
 3576   constraint(ALLOC_IN_RC(ptr_reg));
 3577   match(AddP (DecodeN reg) off);
 3578   op_cost(0);
 3579   format %{ "[$reg, $off]\t# narrow" %}
 3580   interface(MEMORY_INTER) %{
 3581     base($reg);
 3582     index(0xffffffff);
 3583     scale(0x0);
 3584     disp($off);
 3585   %}
 3586 %}
 3587 
 3588 //----------Special Memory Operands--------------------------------------------
 3589 // Stack Slot Operand - This operand is used for loading and storing temporary
 3590 //                      values on the stack where a match requires a value to
 3591 //                      flow through memory.
 3592 operand stackSlotI(sRegI reg)
 3593 %{
 3594   constraint(ALLOC_IN_RC(stack_slots));
 3595   // No match rule because this operand is only generated in matching
 3596   // match(RegI);
 3597   format %{ "[$reg]" %}
 3598   interface(MEMORY_INTER) %{
 3599     base(0x02);  // RSP
 3600     index(0xffffffff);  // No Index
 3601     scale(0x0);  // No Scale
 3602     disp($reg);  // Stack Offset
 3603   %}
 3604 %}
 3605 
 3606 operand stackSlotF(sRegF reg)
 3607 %{
 3608   constraint(ALLOC_IN_RC(stack_slots));
 3609   // No match rule because this operand is only generated in matching
 3610   // match(RegF);
 3611   format %{ "[$reg]" %}
 3612   interface(MEMORY_INTER) %{
 3613     base(0x02);  // RSP
 3614     index(0xffffffff);  // No Index
 3615     scale(0x0);  // No Scale
 3616     disp($reg);  // Stack Offset
 3617   %}
 3618 %}
 3619 
 3620 operand stackSlotD(sRegD reg)
 3621 %{
 3622   constraint(ALLOC_IN_RC(stack_slots));
 3623   // No match rule because this operand is only generated in matching
 3624   // match(RegD);
 3625   format %{ "[$reg]" %}
 3626   interface(MEMORY_INTER) %{
 3627     base(0x02);  // RSP
 3628     index(0xffffffff);  // No Index
 3629     scale(0x0);  // No Scale
 3630     disp($reg);  // Stack Offset
 3631   %}
 3632 %}
 3633 
 3634 operand stackSlotL(sRegL reg)
 3635 %{
 3636   constraint(ALLOC_IN_RC(stack_slots));
 3637   // No match rule because this operand is only generated in matching
 3638   // match(RegL);
 3639   format %{ "[$reg]" %}
 3640   interface(MEMORY_INTER) %{
 3641     base(0x02);  // RSP
 3642     index(0xffffffff);  // No Index
 3643     scale(0x0);  // No Scale
 3644     disp($reg);  // Stack Offset
 3645   %}
 3646 %}
 3647 
 3648 // Special operand allowing long args to int ops to be truncated for free
 3649 
 3650 operand iRegL2I(iRegL reg) %{
 3651 
 3652   op_cost(0);
 3653 
 3654   match(ConvL2I reg);
 3655 
 3656   format %{ "l2i($reg)" %}
 3657 
 3658   interface(REG_INTER)
 3659 %}
 3660 
 3661 
 3662 // Comparison Operands
 3663 // NOTE: Label is a predefined operand which should not be redefined in
 3664 //       the AD file. It is generically handled within the ADLC.
 3665 
 3666 //----------Conditional Branch Operands----------------------------------------
 3667 // Comparison Op  - This is the operation of the comparison, and is limited to
 3668 //                  the following set of codes:
 3669 //                  L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
 3670 //
 3671 // Other attributes of the comparison, such as unsignedness, are specified
 3672 // by the comparison instruction that sets a condition code flags register.
 3673 // That result is represented by a flags operand whose subtype is appropriate
 3674 // to the unsignedness (etc.) of the comparison.
 3675 //
 3676 // Later, the instruction which matches both the Comparison Op (a Bool) and
 3677 // the flags (produced by the Cmp) specifies the coding of the comparison op
 3678 // by matching a specific subtype of Bool operand below, such as cmpOpU.
 3679 
 3680 
 3681 // used for signed integral comparisons and fp comparisons
 3682 operand cmpOp()
 3683 %{
 3684   match(Bool);
 3685 
 3686   format %{ "" %}
 3687 
 3688   // the values in interface derives from struct BoolTest::mask
 3689   interface(COND_INTER) %{
 3690     equal(0x0, "eq");
 3691     greater(0x1, "gt");
 3692     overflow(0x2, "overflow");
 3693     less(0x3, "lt");
 3694     not_equal(0x4, "ne");
 3695     less_equal(0x5, "le");
 3696     no_overflow(0x6, "no_overflow");
 3697     greater_equal(0x7, "ge");
 3698   %}
 3699 %}
 3700 
 3701 // used for unsigned integral comparisons
 3702 operand cmpOpU()
 3703 %{
 3704   match(Bool);
 3705 
 3706   format %{ "" %}
 3707   // the values in interface derives from struct BoolTest::mask
 3708   interface(COND_INTER) %{
 3709     equal(0x0, "eq");
 3710     greater(0x1, "gtu");
 3711     overflow(0x2, "overflow");
 3712     less(0x3, "ltu");
 3713     not_equal(0x4, "ne");
 3714     less_equal(0x5, "leu");
 3715     no_overflow(0x6, "no_overflow");
 3716     greater_equal(0x7, "geu");
 3717   %}
 3718 %}
 3719 
 3720 // used for certain integral comparisons which can be
 3721 // converted to bxx instructions
 3722 operand cmpOpEqNe()
 3723 %{
 3724   match(Bool);
 3725   op_cost(0);
 3726   predicate(n->as_Bool()->_test._test == BoolTest::ne ||
 3727             n->as_Bool()->_test._test == BoolTest::eq);
 3728 
 3729   format %{ "" %}
 3730   interface(COND_INTER) %{
 3731     equal(0x0, "eq");
 3732     greater(0x1, "gt");
 3733     overflow(0x2, "overflow");
 3734     less(0x3, "lt");
 3735     not_equal(0x4, "ne");
 3736     less_equal(0x5, "le");
 3737     no_overflow(0x6, "no_overflow");
 3738     greater_equal(0x7, "ge");
 3739   %}
 3740 %}
 3741 
 3742 operand cmpOpULtGe()
 3743 %{
 3744   match(Bool);
 3745   op_cost(0);
 3746   predicate(n->as_Bool()->_test._test == BoolTest::lt ||
 3747             n->as_Bool()->_test._test == BoolTest::ge);
 3748 
 3749   format %{ "" %}
 3750   interface(COND_INTER) %{
 3751     equal(0x0, "eq");
 3752     greater(0x1, "gtu");
 3753     overflow(0x2, "overflow");
 3754     less(0x3, "ltu");
 3755     not_equal(0x4, "ne");
 3756     less_equal(0x5, "leu");
 3757     no_overflow(0x6, "no_overflow");
 3758     greater_equal(0x7, "geu");
 3759   %}
 3760 %}
 3761 
 3762 operand cmpOpUEqNeLeGt()
 3763 %{
 3764   match(Bool);
 3765   op_cost(0);
 3766   predicate(n->as_Bool()->_test._test == BoolTest::ne ||
 3767             n->as_Bool()->_test._test == BoolTest::eq ||
 3768             n->as_Bool()->_test._test == BoolTest::le ||
 3769             n->as_Bool()->_test._test == BoolTest::gt);
 3770 
 3771   format %{ "" %}
 3772   interface(COND_INTER) %{
 3773     equal(0x0, "eq");
 3774     greater(0x1, "gtu");
 3775     overflow(0x2, "overflow");
 3776     less(0x3, "ltu");
 3777     not_equal(0x4, "ne");
 3778     less_equal(0x5, "leu");
 3779     no_overflow(0x6, "no_overflow");
 3780     greater_equal(0x7, "geu");
 3781   %}
 3782 %}
 3783 
 3784 
 3785 // Flags register, used as output of compare logic
 3786 operand rFlagsReg()
 3787 %{
 3788   constraint(ALLOC_IN_RC(reg_flags));
 3789   match(RegFlags);
 3790 
 3791   op_cost(0);
 3792   format %{ "RFLAGS" %}
 3793   interface(REG_INTER);
 3794 %}
 3795 
 3796 // Special Registers
 3797 
 3798 // Method Register
 3799 operand inline_cache_RegP(iRegP reg)
 3800 %{
 3801   constraint(ALLOC_IN_RC(method_reg)); // inline_cache_reg
 3802   match(reg);
 3803   match(iRegPNoSp);
 3804   op_cost(0);
 3805   format %{ %}
 3806   interface(REG_INTER);
 3807 %}
 3808 
 3809 //----------OPERAND CLASSES----------------------------------------------------
 3810 // Operand Classes are groups of operands that are used as to simplify
 3811 // instruction definitions by not requiring the AD writer to specify
 3812 // separate instructions for every form of operand when the
 3813 // instruction accepts multiple operand types with the same basic
 3814 // encoding and format. The classic case of this is memory operands.
 3815 
 3816 // memory is used to define read/write location for load/store
 3817 // instruction defs. we can turn a memory op into an Address
 3818 
 3819 opclass memory(indirect, indOffI, indOffL, indirectN, indOffIN, indOffLN);
 3820 
 3821 // iRegIorL2I is used for src inputs in rules for 32 bit int (I)
 3822 // operations. it allows the src to be either an iRegI or a (ConvL2I
 3823 // iRegL). in the latter case the l2i normally planted for a ConvL2I
 3824 // can be elided because the 32-bit instruction will just employ the
 3825 // lower 32 bits anyway.
 3826 //
 3827 // n.b. this does not elide all L2I conversions. if the truncated
 3828 // value is consumed by more than one operation then the ConvL2I
 3829 // cannot be bundled into the consuming nodes so an l2i gets planted
 3830 // (actually an addiw $dst, $src, 0) and the downstream instructions
 3831 // consume the result of the L2I as an iRegI input. That's a shame since
 3832 // the addiw is actually redundant but its not too costly.
 3833 
 3834 opclass iRegIorL2I(iRegI, iRegL2I);
 3835 opclass iRegIorL(iRegI, iRegL);
 3836 opclass iRegNorP(iRegN, iRegP);
 3837 opclass iRegILNP(iRegI, iRegL, iRegN, iRegP);
 3838 opclass iRegILNPNoSp(iRegINoSp, iRegLNoSp, iRegNNoSp, iRegPNoSp);
 3839 opclass immIorL(immI, immL);
 3840 
 3841 //----------PIPELINE-----------------------------------------------------------
 3842 // Rules which define the behavior of the target architectures pipeline.
 3843 
 3844 // For specific pipelines, e.g. generic RISC-V, define the stages of that pipeline
 3845 //pipe_desc(ID, EX, MEM, WR);
 3846 #define ID   S0
 3847 #define EX   S1
 3848 #define MEM  S2
 3849 #define WR   S3
 3850 
 3851 // Integer ALU reg operation
 3852 pipeline %{
 3853 
 3854 attributes %{
 3855   // RISC-V instructions are of fixed length
 3856   fixed_size_instructions;           // Fixed size instructions TODO does
 3857   max_instructions_per_bundle = 2;   // Generic RISC-V 1, Sifive Series 7 2
 3858   // RISC-V instructions come in 32-bit word units
 3859   instruction_unit_size = 4;         // An instruction is 4 bytes long
 3860   instruction_fetch_unit_size = 64;  // The processor fetches one line
 3861   instruction_fetch_units = 1;       // of 64 bytes
 3862 
 3863   // List of nop instructions
 3864   nops( MachNop );
 3865 %}
 3866 
 3867 // We don't use an actual pipeline model so don't care about resources
 3868 // or description. we do use pipeline classes to introduce fixed
 3869 // latencies
 3870 
 3871 //----------RESOURCES----------------------------------------------------------
 3872 // Resources are the functional units available to the machine
 3873 
 3874 // Generic RISC-V pipeline
 3875 // 1 decoder
 3876 // 1 instruction decoded per cycle
 3877 // 1 load/store ops per cycle, 1 branch, 1 FPU
 3878 // 1 mul, 1 div
 3879 
 3880 resources ( DECODE,
 3881             ALU,
 3882             MUL,
 3883             DIV,
 3884             BRANCH,
 3885             LDST,
 3886             FPU);
 3887 
 3888 //----------PIPELINE DESCRIPTION-----------------------------------------------
 3889 // Pipeline Description specifies the stages in the machine's pipeline
 3890 
 3891 // Define the pipeline as a generic 6 stage pipeline
 3892 pipe_desc(S0, S1, S2, S3, S4, S5);
 3893 
 3894 //----------PIPELINE CLASSES---------------------------------------------------
 3895 // Pipeline Classes describe the stages in which input and output are
 3896 // referenced by the hardware pipeline.
 3897 
 3898 pipe_class fp_dop_reg_reg_s(fRegF dst, fRegF src1, fRegF src2)
 3899 %{
 3900   single_instruction;
 3901   src1   : S1(read);
 3902   src2   : S2(read);
 3903   dst    : S5(write);
 3904   DECODE : ID;
 3905   FPU    : S5;
 3906 %}
 3907 
 3908 pipe_class fp_dop_reg_reg_d(fRegD dst, fRegD src1, fRegD src2)
 3909 %{
 3910   src1   : S1(read);
 3911   src2   : S2(read);
 3912   dst    : S5(write);
 3913   DECODE : ID;
 3914   FPU    : S5;
 3915 %}
 3916 
 3917 pipe_class fp_uop_s(fRegF dst, fRegF src)
 3918 %{
 3919   single_instruction;
 3920   src    : S1(read);
 3921   dst    : S5(write);
 3922   DECODE : ID;
 3923   FPU    : S5;
 3924 %}
 3925 
 3926 pipe_class fp_uop_d(fRegD dst, fRegD src)
 3927 %{
 3928   single_instruction;
 3929   src    : S1(read);
 3930   dst    : S5(write);
 3931   DECODE : ID;
 3932   FPU    : S5;
 3933 %}
 3934 
 3935 pipe_class fp_d2f(fRegF dst, fRegD src)
 3936 %{
 3937   single_instruction;
 3938   src    : S1(read);
 3939   dst    : S5(write);
 3940   DECODE : ID;
 3941   FPU    : S5;
 3942 %}
 3943 
 3944 pipe_class fp_f2d(fRegD dst, fRegF src)
 3945 %{
 3946   single_instruction;
 3947   src    : S1(read);
 3948   dst    : S5(write);
 3949   DECODE : ID;
 3950   FPU    : S5;
 3951 %}
 3952 
 3953 pipe_class fp_f2i(iRegINoSp dst, fRegF src)
 3954 %{
 3955   single_instruction;
 3956   src    : S1(read);
 3957   dst    : S5(write);
 3958   DECODE : ID;
 3959   FPU    : S5;
 3960 %}
 3961 
 3962 pipe_class fp_f2l(iRegLNoSp dst, fRegF src)
 3963 %{
 3964   single_instruction;
 3965   src    : S1(read);
 3966   dst    : S5(write);
 3967   DECODE : ID;
 3968   FPU    : S5;
 3969 %}
 3970 
 3971 pipe_class fp_i2f(fRegF dst, iRegIorL2I src)
 3972 %{
 3973   single_instruction;
 3974   src    : S1(read);
 3975   dst    : S5(write);
 3976   DECODE : ID;
 3977   FPU    : S5;
 3978 %}
 3979 
 3980 pipe_class fp_l2f(fRegF dst, iRegL src)
 3981 %{
 3982   single_instruction;
 3983   src    : S1(read);
 3984   dst    : S5(write);
 3985   DECODE : ID;
 3986   FPU    : S5;
 3987 %}
 3988 
 3989 pipe_class fp_d2i(iRegINoSp dst, fRegD src)
 3990 %{
 3991   single_instruction;
 3992   src    : S1(read);
 3993   dst    : S5(write);
 3994   DECODE : ID;
 3995   FPU    : S5;
 3996 %}
 3997 
 3998 pipe_class fp_d2l(iRegLNoSp dst, fRegD src)
 3999 %{
 4000   single_instruction;
 4001   src    : S1(read);
 4002   dst    : S5(write);
 4003   DECODE : ID;
 4004   FPU    : S5;
 4005 %}
 4006 
 4007 pipe_class fp_i2d(fRegD dst, iRegIorL2I src)
 4008 %{
 4009   single_instruction;
 4010   src    : S1(read);
 4011   dst    : S5(write);
 4012   DECODE : ID;
 4013   FPU    : S5;
 4014 %}
 4015 
 4016 pipe_class fp_l2d(fRegD dst, iRegIorL2I src)
 4017 %{
 4018   single_instruction;
 4019   src    : S1(read);
 4020   dst    : S5(write);
 4021   DECODE : ID;
 4022   FPU    : S5;
 4023 %}
 4024 
 4025 pipe_class fp_div_s(fRegF dst, fRegF src1, fRegF src2)
 4026 %{
 4027   single_instruction;
 4028   src1   : S1(read);
 4029   src2   : S2(read);
 4030   dst    : S5(write);
 4031   DECODE : ID;
 4032   FPU    : S5;
 4033 %}
 4034 
 4035 pipe_class fp_div_d(fRegD dst, fRegD src1, fRegD src2)
 4036 %{
 4037   single_instruction;
 4038   src1   : S1(read);
 4039   src2   : S2(read);
 4040   dst    : S5(write);
 4041   DECODE : ID;
 4042   FPU    : S5;
 4043 %}
 4044 
 4045 pipe_class fp_sqrt_s(fRegF dst, fRegF src)
 4046 %{
 4047   single_instruction;
 4048   src    : S1(read);
 4049   dst    : S5(write);
 4050   DECODE : ID;
 4051   FPU    : S5;
 4052 %}
 4053 
 4054 pipe_class fp_sqrt_d(fRegD dst, fRegD src)
 4055 %{
 4056   single_instruction;
 4057   src    : S1(read);
 4058   dst    : S5(write);
 4059   DECODE : ID;
 4060   FPU    : S5;
 4061 %}
 4062 
 4063 pipe_class fp_load_constant_s(fRegF dst)
 4064 %{
 4065   single_instruction;
 4066   dst    : S5(write);
 4067   DECODE : ID;
 4068   FPU    : S5;
 4069 %}
 4070 
 4071 pipe_class fp_load_constant_d(fRegD dst)
 4072 %{
 4073   single_instruction;
 4074   dst    : S5(write);
 4075   DECODE : ID;
 4076   FPU    : S5;
 4077 %}
 4078 
 4079 pipe_class fp_load_mem_s(fRegF dst, memory mem)
 4080 %{
 4081   single_instruction;
 4082   mem    : S1(read);
 4083   dst    : S5(write);
 4084   DECODE : ID;
 4085   LDST   : MEM;
 4086 %}
 4087 
 4088 pipe_class fp_load_mem_d(fRegD dst, memory mem)
 4089 %{
 4090   single_instruction;
 4091   mem    : S1(read);
 4092   dst    : S5(write);
 4093   DECODE : ID;
 4094   LDST   : MEM;
 4095 %}
 4096 
 4097 pipe_class fp_store_reg_s(fRegF src, memory mem)
 4098 %{
 4099   single_instruction;
 4100   src    : S1(read);
 4101   mem    : S5(write);
 4102   DECODE : ID;
 4103   LDST   : MEM;
 4104 %}
 4105 
 4106 pipe_class fp_store_reg_d(fRegD src, memory mem)
 4107 %{
 4108   single_instruction;
 4109   src    : S1(read);
 4110   mem    : S5(write);
 4111   DECODE : ID;
 4112   LDST   : MEM;
 4113 %}
 4114 
 4115 //------- Integer ALU operations --------------------------
 4116 
 4117 // Integer ALU reg-reg operation
 4118 // Operands needs in ID, result generated in EX
 4119 // E.g.  ADD   Rd, Rs1, Rs2
 4120 pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2)
 4121 %{
 4122   single_instruction;
 4123   dst    : EX(write);
 4124   src1   : ID(read);
 4125   src2   : ID(read);
 4126   DECODE : ID;
 4127   ALU    : EX;
 4128 %}
 4129 
 4130 // Integer ALU reg operation with constant shift
 4131 // E.g. SLLI    Rd, Rs1, #shift
 4132 pipe_class ialu_reg_shift(iRegI dst, iRegI src1)
 4133 %{
 4134   single_instruction;
 4135   dst    : EX(write);
 4136   src1   : ID(read);
 4137   DECODE : ID;
 4138   ALU    : EX;
 4139 %}
 4140 
 4141 // Integer ALU reg-reg operation with variable shift
 4142 // both operands must be available in ID
 4143 // E.g. SLL   Rd, Rs1, Rs2
 4144 pipe_class ialu_reg_reg_vshift(iRegI dst, iRegI src1, iRegI src2)
 4145 %{
 4146   single_instruction;
 4147   dst    : EX(write);
 4148   src1   : ID(read);
 4149   src2   : ID(read);
 4150   DECODE : ID;
 4151   ALU    : EX;
 4152 %}
 4153 
 4154 // Integer ALU reg operation
 4155 // E.g. NEG   Rd, Rs2
 4156 pipe_class ialu_reg(iRegI dst, iRegI src)
 4157 %{
 4158   single_instruction;
 4159   dst    : EX(write);
 4160   src    : ID(read);
 4161   DECODE : ID;
 4162   ALU    : EX;
 4163 %}
 4164 
 4165 // Integer ALU reg immediate operation
 4166 // E.g. ADDI   Rd, Rs1, #imm
 4167 pipe_class ialu_reg_imm(iRegI dst, iRegI src1)
 4168 %{
 4169   single_instruction;
 4170   dst    : EX(write);
 4171   src1   : ID(read);
 4172   DECODE : ID;
 4173   ALU    : EX;
 4174 %}
 4175 
 4176 // Integer ALU immediate operation (no source operands)
 4177 // E.g. LI    Rd, #imm
 4178 pipe_class ialu_imm(iRegI dst)
 4179 %{
 4180   single_instruction;
 4181   dst    : EX(write);
 4182   DECODE : ID;
 4183   ALU    : EX;
 4184 %}
 4185 
 4186 //------- Multiply pipeline operations --------------------
 4187 
 4188 // Multiply reg-reg
 4189 // E.g. MULW   Rd, Rs1, Rs2
 4190 pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2)
 4191 %{
 4192   single_instruction;
 4193   dst    : WR(write);
 4194   src1   : ID(read);
 4195   src2   : ID(read);
 4196   DECODE : ID;
 4197   MUL    : WR;
 4198 %}
 4199 
 4200 // E.g. MUL   RD, Rs1, Rs2
 4201 pipe_class lmul_reg_reg(iRegL dst, iRegL src1, iRegL src2)
 4202 %{
 4203   single_instruction;
 4204   fixed_latency(3); // Maximum latency for 64 bit mul
 4205   dst    : WR(write);
 4206   src1   : ID(read);
 4207   src2   : ID(read);
 4208   DECODE : ID;
 4209   MUL    : WR;
 4210 %}
 4211 
 4212 //------- Divide pipeline operations --------------------
 4213 
 4214 // E.g. DIVW   Rd, Rs1, Rs2
 4215 pipe_class idiv_reg_reg(iRegI dst, iRegI src1, iRegI src2)
 4216 %{
 4217   single_instruction;
 4218   fixed_latency(8); // Maximum latency for 32 bit divide
 4219   dst    : WR(write);
 4220   src1   : ID(read);
 4221   src2   : ID(read);
 4222   DECODE : ID;
 4223   DIV    : WR;
 4224 %}
 4225 
 4226 // E.g. DIV   RD, Rs1, Rs2
 4227 pipe_class ldiv_reg_reg(iRegL dst, iRegL src1, iRegL src2)
 4228 %{
 4229   single_instruction;
 4230   fixed_latency(16); // Maximum latency for 64 bit divide
 4231   dst    : WR(write);
 4232   src1   : ID(read);
 4233   src2   : ID(read);
 4234   DECODE : ID;
 4235   DIV    : WR;
 4236 %}
 4237 
 4238 //------- Load pipeline operations ------------------------
 4239 
 4240 // Load - prefetch
 4241 // Eg.  PREFETCH_W  mem
 4242 pipe_class iload_prefetch(memory mem)
 4243 %{
 4244   single_instruction;
 4245   mem    : ID(read);
 4246   DECODE : ID;
 4247   LDST   : MEM;
 4248 %}
 4249 
 4250 // Load - reg, mem
 4251 // E.g. LA    Rd, mem
 4252 pipe_class iload_reg_mem(iRegI dst, memory mem)
 4253 %{
 4254   single_instruction;
 4255   dst    : WR(write);
 4256   mem    : ID(read);
 4257   DECODE : ID;
 4258   LDST   : MEM;
 4259 %}
 4260 
 4261 // Load - reg, reg
 4262 // E.g. LD    Rd, Rs
 4263 pipe_class iload_reg_reg(iRegI dst, iRegI src)
 4264 %{
 4265   single_instruction;
 4266   dst    : WR(write);
 4267   src    : ID(read);
 4268   DECODE : ID;
 4269   LDST   : MEM;
 4270 %}
 4271 
 4272 //------- Store pipeline operations -----------------------
 4273 
 4274 // Store - zr, mem
 4275 // E.g. SD    zr, mem
 4276 pipe_class istore_mem(memory mem)
 4277 %{
 4278   single_instruction;
 4279   mem    : ID(read);
 4280   DECODE : ID;
 4281   LDST   : MEM;
 4282 %}
 4283 
 4284 // Store - reg, mem
 4285 // E.g. SD    Rs, mem
 4286 pipe_class istore_reg_mem(iRegI src, memory mem)
 4287 %{
 4288   single_instruction;
 4289   mem    : ID(read);
 4290   src    : EX(read);
 4291   DECODE : ID;
 4292   LDST   : MEM;
 4293 %}
 4294 
 4295 // Store - reg, reg
 4296 // E.g. SD    Rs2, Rs1
 4297 pipe_class istore_reg_reg(iRegI dst, iRegI src)
 4298 %{
 4299   single_instruction;
 4300   dst    : ID(read);
 4301   src    : EX(read);
 4302   DECODE : ID;
 4303   LDST   : MEM;
 4304 %}
 4305 
 4306 //------- Control transfer pipeline operations ------------
 4307 
 4308 // Branch
 4309 pipe_class pipe_branch()
 4310 %{
 4311   single_instruction;
 4312   DECODE : ID;
 4313   BRANCH : EX;
 4314 %}
 4315 
 4316 // Branch
 4317 pipe_class pipe_branch_reg(iRegI src)
 4318 %{
 4319   single_instruction;
 4320   src    : ID(read);
 4321   DECODE : ID;
 4322   BRANCH : EX;
 4323 %}
 4324 
 4325 // Compare & Branch
 4326 // E.g. BEQ   Rs1, Rs2, L
 4327 pipe_class pipe_cmp_branch(iRegI src1, iRegI src2)
 4328 %{
 4329   single_instruction;
 4330   src1   : ID(read);
 4331   src2   : ID(read);
 4332   DECODE : ID;
 4333   BRANCH : EX;
 4334 %}
 4335 
 4336 // E.g. BEQZ Rs, L
 4337 pipe_class pipe_cmpz_branch(iRegI src)
 4338 %{
 4339   single_instruction;
 4340   src    : ID(read);
 4341   DECODE : ID;
 4342   BRANCH : EX;
 4343 %}
 4344 
 4345 //------- Synchronisation operations ----------------------
 4346 // Any operation requiring serialization
 4347 // E.g. FENCE/Atomic Ops/Load Acquire/Store Release
 4348 pipe_class pipe_serial()
 4349 %{
 4350   single_instruction;
 4351   force_serialization;
 4352   fixed_latency(16);
 4353   DECODE : ID;
 4354   LDST   : MEM;
 4355 %}
 4356 
 4357 pipe_class pipe_slow()
 4358 %{
 4359   instruction_count(10);
 4360   multiple_bundles;
 4361   force_serialization;
 4362   fixed_latency(16);
 4363   DECODE : ID;
 4364   LDST   : MEM;
 4365 %}
 4366 
 4367 // The real do-nothing guy
 4368 pipe_class real_empty()
 4369 %{
 4370     instruction_count(0);
 4371 %}
 4372 
 4373 // Empty pipeline class
 4374 pipe_class pipe_class_empty()
 4375 %{
 4376   single_instruction;
 4377   fixed_latency(0);
 4378 %}
 4379 
 4380 // Default pipeline class.
 4381 pipe_class pipe_class_default()
 4382 %{
 4383   single_instruction;
 4384   fixed_latency(2);
 4385 %}
 4386 
 4387 // Pipeline class for compares.
 4388 pipe_class pipe_class_compare()
 4389 %{
 4390   single_instruction;
 4391   fixed_latency(16);
 4392 %}
 4393 
 4394 // Pipeline class for memory operations.
 4395 pipe_class pipe_class_memory()
 4396 %{
 4397   single_instruction;
 4398   fixed_latency(16);
 4399 %}
 4400 
 4401 // Pipeline class for call.
 4402 pipe_class pipe_class_call()
 4403 %{
 4404   single_instruction;
 4405   fixed_latency(100);
 4406 %}
 4407 
 4408 // Define the class for the Nop node.
 4409 define %{
 4410    MachNop = pipe_class_empty;
 4411 %}
 4412 %}
 4413 //----------INSTRUCTIONS-------------------------------------------------------
 4414 //
 4415 // match      -- States which machine-independent subtree may be replaced
 4416 //               by this instruction.
 4417 // ins_cost   -- The estimated cost of this instruction is used by instruction
 4418 //               selection to identify a minimum cost tree of machine
 4419 //               instructions that matches a tree of machine-independent
 4420 //               instructions.
 4421 // format     -- A string providing the disassembly for this instruction.
 4422 //               The value of an instruction's operand may be inserted
 4423 //               by referring to it with a '$' prefix.
 4424 // opcode     -- Three instruction opcodes may be provided.  These are referred
 4425 //               to within an encode class as $primary, $secondary, and $tertiary
 4426 //               rrspectively.  The primary opcode is commonly used to
 4427 //               indicate the type of machine instruction, while secondary
 4428 //               and tertiary are often used for prefix options or addressing
 4429 //               modes.
 4430 // ins_encode -- A list of encode classes with parameters. The encode class
 4431 //               name must have been defined in an 'enc_class' specification
 4432 //               in the encode section of the architecture description.
 4433 
 4434 // ============================================================================
 4435 // Memory (Load/Store) Instructions
 4436 
 4437 // Load Instructions
 4438 
 4439 // Load Byte (8 bit signed)
 4440 instruct loadB(iRegINoSp dst, memory mem)
 4441 %{
 4442   match(Set dst (LoadB mem));
 4443 
 4444   ins_cost(LOAD_COST);
 4445   format %{ "lb  $dst, $mem\t# byte, #@loadB" %}
 4446 
 4447   ins_encode %{
 4448     __ lb(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4449   %}
 4450 
 4451   ins_pipe(iload_reg_mem);
 4452 %}
 4453 
 4454 // Load Byte (8 bit signed) into long
 4455 instruct loadB2L(iRegLNoSp dst, memory mem)
 4456 %{
 4457   match(Set dst (ConvI2L (LoadB mem)));
 4458 
 4459   ins_cost(LOAD_COST);
 4460   format %{ "lb  $dst, $mem\t# byte, #@loadB2L" %}
 4461 
 4462   ins_encode %{
 4463     __ lb(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4464   %}
 4465 
 4466   ins_pipe(iload_reg_mem);
 4467 %}
 4468 
 4469 // Load Byte (8 bit unsigned)
 4470 instruct loadUB(iRegINoSp dst, memory mem)
 4471 %{
 4472   match(Set dst (LoadUB mem));
 4473 
 4474   ins_cost(LOAD_COST);
 4475   format %{ "lbu  $dst, $mem\t# byte, #@loadUB" %}
 4476 
 4477   ins_encode %{
 4478     __ lbu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4479   %}
 4480 
 4481   ins_pipe(iload_reg_mem);
 4482 %}
 4483 
 4484 // Load Byte (8 bit unsigned) into long
 4485 instruct loadUB2L(iRegLNoSp dst, memory mem)
 4486 %{
 4487   match(Set dst (ConvI2L (LoadUB mem)));
 4488 
 4489   ins_cost(LOAD_COST);
 4490   format %{ "lbu  $dst, $mem\t# byte, #@loadUB2L" %}
 4491 
 4492   ins_encode %{
 4493     __ lbu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4494   %}
 4495 
 4496   ins_pipe(iload_reg_mem);
 4497 %}
 4498 
 4499 // Load Short (16 bit signed)
 4500 instruct loadS(iRegINoSp dst, memory mem)
 4501 %{
 4502   match(Set dst (LoadS mem));
 4503 
 4504   ins_cost(LOAD_COST);
 4505   format %{ "lh  $dst, $mem\t# short, #@loadS" %}
 4506 
 4507   ins_encode %{
 4508     __ lh(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4509   %}
 4510 
 4511   ins_pipe(iload_reg_mem);
 4512 %}
 4513 
 4514 // Load Short (16 bit signed) into long
 4515 instruct loadS2L(iRegLNoSp dst, memory mem)
 4516 %{
 4517   match(Set dst (ConvI2L (LoadS mem)));
 4518 
 4519   ins_cost(LOAD_COST);
 4520   format %{ "lh  $dst, $mem\t# short, #@loadS2L" %}
 4521 
 4522   ins_encode %{
 4523     __ lh(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4524   %}
 4525 
 4526   ins_pipe(iload_reg_mem);
 4527 %}
 4528 
 4529 // Load Char (16 bit unsigned)
 4530 instruct loadUS(iRegINoSp dst, memory mem)
 4531 %{
 4532   match(Set dst (LoadUS mem));
 4533 
 4534   ins_cost(LOAD_COST);
 4535   format %{ "lhu  $dst, $mem\t# short, #@loadUS" %}
 4536 
 4537   ins_encode %{
 4538     __ lhu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4539   %}
 4540 
 4541   ins_pipe(iload_reg_mem);
 4542 %}
 4543 
 4544 // Load Short/Char (16 bit unsigned) into long
 4545 instruct loadUS2L(iRegLNoSp dst, memory mem)
 4546 %{
 4547   match(Set dst (ConvI2L (LoadUS mem)));
 4548 
 4549   ins_cost(LOAD_COST);
 4550   format %{ "lhu  $dst, $mem\t# short, #@loadUS2L" %}
 4551 
 4552   ins_encode %{
 4553     __ lhu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4554   %}
 4555 
 4556   ins_pipe(iload_reg_mem);
 4557 %}
 4558 
 4559 // Load Integer (32 bit signed)
 4560 instruct loadI(iRegINoSp dst, memory mem)
 4561 %{
 4562   match(Set dst (LoadI mem));
 4563 
 4564   ins_cost(LOAD_COST);
 4565   format %{ "lw  $dst, $mem\t# int, #@loadI" %}
 4566 
 4567   ins_encode %{
 4568     __ lw(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4569   %}
 4570 
 4571   ins_pipe(iload_reg_mem);
 4572 %}
 4573 
 4574 // Load Integer (32 bit signed) into long
 4575 instruct loadI2L(iRegLNoSp dst, memory mem)
 4576 %{
 4577   match(Set dst (ConvI2L (LoadI mem)));
 4578 
 4579   ins_cost(LOAD_COST);
 4580   format %{ "lw  $dst, $mem\t# int, #@loadI2L" %}
 4581 
 4582   ins_encode %{
 4583     __ lw(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4584   %}
 4585 
 4586   ins_pipe(iload_reg_mem);
 4587 %}
 4588 
 4589 // Load Integer (32 bit unsigned) into long
 4590 instruct loadUI2L(iRegLNoSp dst, memory mem, immL_32bits mask)
 4591 %{
 4592   match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
 4593 
 4594   ins_cost(LOAD_COST);
 4595   format %{ "lwu  $dst, $mem\t# int, #@loadUI2L" %}
 4596 
 4597   ins_encode %{
 4598     __ lwu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4599   %}
 4600 
 4601   ins_pipe(iload_reg_mem);
 4602 %}
 4603 
 4604 // Load Long (64 bit signed)
 4605 instruct loadL(iRegLNoSp dst, memory mem)
 4606 %{
 4607   match(Set dst (LoadL mem));
 4608 
 4609   ins_cost(LOAD_COST);
 4610   format %{ "ld  $dst, $mem\t# int, #@loadL" %}
 4611 
 4612   ins_encode %{
 4613     __ ld(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4614   %}
 4615 
 4616   ins_pipe(iload_reg_mem);
 4617 %}
 4618 
 4619 // Load Range
 4620 instruct loadRange(iRegINoSp dst, memory mem)
 4621 %{
 4622   match(Set dst (LoadRange mem));
 4623 
 4624   ins_cost(LOAD_COST);
 4625   format %{ "lwu  $dst, $mem\t# range, #@loadRange" %}
 4626 
 4627   ins_encode %{
 4628     __ lwu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4629   %}
 4630 
 4631   ins_pipe(iload_reg_mem);
 4632 %}
 4633 
 4634 // Load Pointer
 4635 instruct loadP(iRegPNoSp dst, memory mem)
 4636 %{
 4637   match(Set dst (LoadP mem));
 4638   predicate(n->as_Load()->barrier_data() == 0);
 4639 
 4640   ins_cost(LOAD_COST);
 4641   format %{ "ld  $dst, $mem\t# ptr, #@loadP" %}
 4642 
 4643   ins_encode %{
 4644     __ ld(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4645   %}
 4646 
 4647   ins_pipe(iload_reg_mem);
 4648 %}
 4649 
 4650 // Load Compressed Pointer
 4651 instruct loadN(iRegNNoSp dst, memory mem)
 4652 %{
 4653   predicate(n->as_Load()->barrier_data() == 0);
 4654   match(Set dst (LoadN mem));
 4655 
 4656   ins_cost(LOAD_COST);
 4657   format %{ "lwu  $dst, $mem\t# compressed ptr, #@loadN" %}
 4658 
 4659   ins_encode %{
 4660     __ lwu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4661   %}
 4662 
 4663   ins_pipe(iload_reg_mem);
 4664 %}
 4665 
 4666 // Load Klass Pointer
 4667 instruct loadKlass(iRegPNoSp dst, memory mem)
 4668 %{
 4669   match(Set dst (LoadKlass mem));
 4670 
 4671   ins_cost(LOAD_COST);
 4672   format %{ "ld  $dst, $mem\t# class, #@loadKlass" %}
 4673 
 4674   ins_encode %{
 4675     __ ld(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4676   %}
 4677 
 4678   ins_pipe(iload_reg_mem);
 4679 %}
 4680 
 4681 // Load Narrow Klass Pointer
 4682 instruct loadNKlass(iRegNNoSp dst, memory mem)
 4683 %{
 4684   predicate(!UseCompactObjectHeaders);
 4685   match(Set dst (LoadNKlass mem));
 4686 
 4687   ins_cost(LOAD_COST);
 4688   format %{ "lwu  $dst, $mem\t# compressed class ptr, #@loadNKlass" %}
 4689 
 4690   ins_encode %{
 4691     __ lwu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4692   %}
 4693 
 4694   ins_pipe(iload_reg_mem);
 4695 %}
 4696 
 4697 instruct loadNKlassCompactHeaders(iRegNNoSp dst, memory mem)
 4698 %{
 4699   predicate(UseCompactObjectHeaders);
 4700   match(Set dst (LoadNKlass mem));
 4701 
 4702   ins_cost(LOAD_COST);
 4703   format %{
 4704     "lwu  $dst, $mem\t# compressed klass ptr, shifted\n\t"
 4705     "srli $dst, $dst, markWord::klass_shift_at_offset"
 4706   %}
 4707 
 4708   ins_encode %{
 4709     Unimplemented();
 4710     // __ lwu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4711     // __ srli(as_Register($dst$$reg), as_Register($dst$$reg), (unsigned) markWord::klass_shift_at_offset);
 4712   %}
 4713 
 4714   ins_pipe(iload_reg_mem);
 4715 %}
 4716 
 4717 // Load Float
 4718 instruct loadF(fRegF dst, memory mem)
 4719 %{
 4720   match(Set dst (LoadF mem));
 4721 
 4722   ins_cost(LOAD_COST);
 4723   format %{ "flw  $dst, $mem\t# float, #@loadF" %}
 4724 
 4725   ins_encode %{
 4726     __ flw(as_FloatRegister($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4727   %}
 4728 
 4729   ins_pipe(fp_load_mem_s);
 4730 %}
 4731 
 4732 // Load Double
 4733 instruct loadD(fRegD dst, memory mem)
 4734 %{
 4735   match(Set dst (LoadD mem));
 4736 
 4737   ins_cost(LOAD_COST);
 4738   format %{ "fld  $dst, $mem\t# double, #@loadD" %}
 4739 
 4740   ins_encode %{
 4741     __ fld(as_FloatRegister($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4742   %}
 4743 
 4744   ins_pipe(fp_load_mem_d);
 4745 %}
 4746 
 4747 // Load Int Constant
 4748 instruct loadConI(iRegINoSp dst, immI src)
 4749 %{
 4750   match(Set dst src);
 4751 
 4752   ins_cost(ALU_COST);
 4753   format %{ "mv $dst, $src\t# int, #@loadConI" %}
 4754 
 4755   ins_encode(riscv_enc_mov_imm(dst, src));
 4756 
 4757   ins_pipe(ialu_imm);
 4758 %}
 4759 
 4760 // Load Long Constant
 4761 instruct loadConL(iRegLNoSp dst, immL src)
 4762 %{
 4763   match(Set dst src);
 4764 
 4765   ins_cost(ALU_COST);
 4766   format %{ "mv $dst, $src\t# long, #@loadConL" %}
 4767 
 4768   ins_encode(riscv_enc_mov_imm(dst, src));
 4769 
 4770   ins_pipe(ialu_imm);
 4771 %}
 4772 
 4773 // Load Pointer Constant
 4774 instruct loadConP(iRegPNoSp dst, immP con)
 4775 %{
 4776   match(Set dst con);
 4777 
 4778   ins_cost(ALU_COST);
 4779   format %{ "mv  $dst, $con\t# ptr, #@loadConP" %}
 4780 
 4781   ins_encode(riscv_enc_mov_p(dst, con));
 4782 
 4783   ins_pipe(ialu_imm);
 4784 %}
 4785 
 4786 // Load Null Pointer Constant
 4787 instruct loadConP0(iRegPNoSp dst, immP0 con)
 4788 %{
 4789   match(Set dst con);
 4790 
 4791   ins_cost(ALU_COST);
 4792   format %{ "mv  $dst, $con\t# null pointer, #@loadConP0" %}
 4793 
 4794   ins_encode(riscv_enc_mov_zero(dst));
 4795 
 4796   ins_pipe(ialu_imm);
 4797 %}
 4798 
 4799 // Load Pointer Constant One
 4800 instruct loadConP1(iRegPNoSp dst, immP_1 con)
 4801 %{
 4802   match(Set dst con);
 4803 
 4804   ins_cost(ALU_COST);
 4805   format %{ "mv  $dst, $con\t# load ptr constant one, #@loadConP1" %}
 4806 
 4807   ins_encode(riscv_enc_mov_p1(dst));
 4808 
 4809   ins_pipe(ialu_imm);
 4810 %}
 4811 
 4812 // Load Byte Map Base Constant
 4813 instruct loadByteMapBase(iRegPNoSp dst, immByteMapBase con)
 4814 %{
 4815   match(Set dst con);
 4816   ins_cost(ALU_COST);
 4817   format %{ "mv  $dst, $con\t# Byte Map Base, #@loadByteMapBase" %}
 4818 
 4819   ins_encode(riscv_enc_mov_byte_map_base(dst));
 4820 
 4821   ins_pipe(ialu_imm);
 4822 %}
 4823 
 4824 // Load Narrow Pointer Constant
 4825 instruct loadConN(iRegNNoSp dst, immN con)
 4826 %{
 4827   match(Set dst con);
 4828 
 4829   ins_cost(ALU_COST * 4);
 4830   format %{ "mv  $dst, $con\t# compressed ptr, #@loadConN" %}
 4831 
 4832   ins_encode(riscv_enc_mov_n(dst, con));
 4833 
 4834   ins_pipe(ialu_imm);
 4835 %}
 4836 
 4837 // Load Narrow Null Pointer Constant
 4838 instruct loadConN0(iRegNNoSp dst, immN0 con)
 4839 %{
 4840   match(Set dst con);
 4841 
 4842   ins_cost(ALU_COST);
 4843   format %{ "mv  $dst, $con\t# compressed null pointer, #@loadConN0" %}
 4844 
 4845   ins_encode(riscv_enc_mov_zero(dst));
 4846 
 4847   ins_pipe(ialu_imm);
 4848 %}
 4849 
 4850 // Load Narrow Klass Constant
 4851 instruct loadConNKlass(iRegNNoSp dst, immNKlass con)
 4852 %{
 4853   match(Set dst con);
 4854 
 4855   ins_cost(ALU_COST * 6);
 4856   format %{ "mv  $dst, $con\t# compressed klass ptr, #@loadConNKlass" %}
 4857 
 4858   ins_encode(riscv_enc_mov_nk(dst, con));
 4859 
 4860   ins_pipe(ialu_imm);
 4861 %}
 4862 
 4863 // Load Half Float Constant
 4864 instruct loadConH(fRegF dst, immH con) %{
 4865   match(Set dst con);
 4866 
 4867   ins_cost(LOAD_COST);
 4868   format %{
 4869     "flh $dst, [$constantaddress]\t# load from constant table: float=$con, #@loadConH"
 4870   %}
 4871 
 4872   ins_encode %{
 4873     assert(UseZfh || UseZfhmin, "must");
 4874     if (MacroAssembler::can_hf_imm_load($con$$constant)) {
 4875       __ fli_h(as_FloatRegister($dst$$reg), $con$$constant);
 4876     } else {
 4877       __ flh(as_FloatRegister($dst$$reg), $constantaddress($con));
 4878     }
 4879   %}
 4880 
 4881   ins_pipe(fp_load_constant_s);
 4882 %}
 4883 
 4884 instruct loadConH0(fRegF dst, immH0 con) %{
 4885   match(Set dst con);
 4886 
 4887   ins_cost(XFER_COST);
 4888 
 4889   format %{ "fmv.h.x $dst, zr\t# float, #@loadConH0" %}
 4890 
 4891   ins_encode %{
 4892     assert(UseZfh || UseZfhmin, "must");
 4893     __ fmv_h_x(as_FloatRegister($dst$$reg), zr);
 4894   %}
 4895 
 4896   ins_pipe(fp_load_constant_s);
 4897 %}
 4898 
 4899 // Load Float Constant
 4900 instruct loadConF(fRegF dst, immF con) %{
 4901   match(Set dst con);
 4902 
 4903   ins_cost(LOAD_COST);
 4904   format %{
 4905     "flw $dst, [$constantaddress]\t# load from constant table: float=$con, #@loadConF"
 4906   %}
 4907 
 4908   ins_encode %{
 4909     if (MacroAssembler::can_fp_imm_load($con$$constant)) {
 4910       __ fli_s(as_FloatRegister($dst$$reg), $con$$constant);
 4911     } else {
 4912       __ flw(as_FloatRegister($dst$$reg), $constantaddress($con));
 4913     }
 4914   %}
 4915 
 4916   ins_pipe(fp_load_constant_s);
 4917 %}
 4918 
 4919 instruct loadConF0(fRegF dst, immF0 con) %{
 4920   match(Set dst con);
 4921 
 4922   ins_cost(XFER_COST);
 4923 
 4924   format %{ "fmv.w.x $dst, zr\t# float, #@loadConF0" %}
 4925 
 4926   ins_encode %{
 4927     __ fmv_w_x(as_FloatRegister($dst$$reg), zr);
 4928   %}
 4929 
 4930   ins_pipe(fp_load_constant_s);
 4931 %}
 4932 
 4933 // Load Double Constant
 4934 instruct loadConD(fRegD dst, immD con) %{
 4935   match(Set dst con);
 4936 
 4937   ins_cost(LOAD_COST);
 4938   format %{
 4939     "fld $dst, [$constantaddress]\t# load from constant table: double=$con, #@loadConD"
 4940   %}
 4941 
 4942   ins_encode %{
 4943     if (MacroAssembler::can_dp_imm_load($con$$constant)) {
 4944       __ fli_d(as_FloatRegister($dst$$reg), $con$$constant);
 4945     } else {
 4946       __ fld(as_FloatRegister($dst$$reg), $constantaddress($con));
 4947     }
 4948   %}
 4949 
 4950   ins_pipe(fp_load_constant_d);
 4951 %}
 4952 
 4953 instruct loadConD0(fRegD dst, immD0 con) %{
 4954   match(Set dst con);
 4955 
 4956   ins_cost(XFER_COST);
 4957 
 4958   format %{ "fmv.d.x $dst, zr\t# double, #@loadConD0" %}
 4959 
 4960   ins_encode %{
 4961     __ fmv_d_x(as_FloatRegister($dst$$reg), zr);
 4962   %}
 4963 
 4964   ins_pipe(fp_load_constant_d);
 4965 %}
 4966 
 4967 // Store Byte
 4968 instruct storeB(iRegIorL2I src, memory mem)
 4969 %{
 4970   match(Set mem (StoreB mem src));
 4971 
 4972   ins_cost(STORE_COST);
 4973   format %{ "sb  $src, $mem\t# byte, #@storeB" %}
 4974 
 4975   ins_encode %{
 4976     __ sb(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4977   %}
 4978 
 4979   ins_pipe(istore_reg_mem);
 4980 %}
 4981 
 4982 instruct storeimmB0(immI0 zero, memory mem)
 4983 %{
 4984   match(Set mem (StoreB mem zero));
 4985 
 4986   ins_cost(STORE_COST);
 4987   format %{ "sb zr, $mem\t# byte, #@storeimmB0" %}
 4988 
 4989   ins_encode %{
 4990     __ sb(zr, Address(as_Register($mem$$base), $mem$$disp));
 4991   %}
 4992 
 4993   ins_pipe(istore_mem);
 4994 %}
 4995 
 4996 // Store Char/Short
 4997 instruct storeC(iRegIorL2I src, memory mem)
 4998 %{
 4999   match(Set mem (StoreC mem src));
 5000 
 5001   ins_cost(STORE_COST);
 5002   format %{ "sh  $src, $mem\t# short, #@storeC" %}
 5003 
 5004   ins_encode %{
 5005     __ sh(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
 5006   %}
 5007 
 5008   ins_pipe(istore_reg_mem);
 5009 %}
 5010 
 5011 instruct storeimmC0(immI0 zero, memory mem)
 5012 %{
 5013   match(Set mem (StoreC mem zero));
 5014 
 5015   ins_cost(STORE_COST);
 5016   format %{ "sh  zr, $mem\t# short, #@storeimmC0" %}
 5017 
 5018   ins_encode %{
 5019     __ sh(zr, Address(as_Register($mem$$base), $mem$$disp));
 5020   %}
 5021 
 5022   ins_pipe(istore_mem);
 5023 %}
 5024 
 5025 // Store Integer
 5026 instruct storeI(iRegIorL2I src, memory mem)
 5027 %{
 5028   match(Set mem(StoreI mem src));
 5029 
 5030   ins_cost(STORE_COST);
 5031   format %{ "sw  $src, $mem\t# int, #@storeI" %}
 5032 
 5033   ins_encode %{
 5034     __ sw(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
 5035   %}
 5036 
 5037   ins_pipe(istore_reg_mem);
 5038 %}
 5039 
 5040 instruct storeimmI0(immI0 zero, memory mem)
 5041 %{
 5042   match(Set mem(StoreI mem zero));
 5043 
 5044   ins_cost(STORE_COST);
 5045   format %{ "sw  zr, $mem\t# int, #@storeimmI0" %}
 5046 
 5047   ins_encode %{
 5048     __ sw(zr, Address(as_Register($mem$$base), $mem$$disp));
 5049   %}
 5050 
 5051   ins_pipe(istore_mem);
 5052 %}
 5053 
 5054 // Store Long (64 bit signed)
 5055 instruct storeL(iRegL src, memory mem)
 5056 %{
 5057   match(Set mem (StoreL mem src));
 5058 
 5059   ins_cost(STORE_COST);
 5060   format %{ "sd  $src, $mem\t# long, #@storeL" %}
 5061 
 5062   ins_encode %{
 5063     __ sd(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
 5064   %}
 5065 
 5066   ins_pipe(istore_reg_mem);
 5067 %}
 5068 
 5069 // Store Long (64 bit signed)
 5070 instruct storeimmL0(immL0 zero, memory mem)
 5071 %{
 5072   match(Set mem (StoreL mem zero));
 5073 
 5074   ins_cost(STORE_COST);
 5075   format %{ "sd  zr, $mem\t# long, #@storeimmL0" %}
 5076 
 5077   ins_encode %{
 5078     __ sd(zr, Address(as_Register($mem$$base), $mem$$disp));
 5079   %}
 5080 
 5081   ins_pipe(istore_mem);
 5082 %}
 5083 
 5084 // Store Pointer
 5085 instruct storeP(iRegP src, memory mem)
 5086 %{
 5087   match(Set mem (StoreP mem src));
 5088   predicate(n->as_Store()->barrier_data() == 0);
 5089 
 5090   ins_cost(STORE_COST);
 5091   format %{ "sd  $src, $mem\t# ptr, #@storeP" %}
 5092 
 5093   ins_encode %{
 5094     __ sd(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
 5095   %}
 5096 
 5097   ins_pipe(istore_reg_mem);
 5098 %}
 5099 
 5100 // Store Pointer
 5101 instruct storeimmP0(immP0 zero, memory mem)
 5102 %{
 5103   match(Set mem (StoreP mem zero));
 5104   predicate(n->as_Store()->barrier_data() == 0);
 5105 
 5106   ins_cost(STORE_COST);
 5107   format %{ "sd zr, $mem\t# ptr, #@storeimmP0" %}
 5108 
 5109   ins_encode %{
 5110     __ sd(zr, Address(as_Register($mem$$base), $mem$$disp));
 5111   %}
 5112 
 5113   ins_pipe(istore_mem);
 5114 %}
 5115 
 5116 // Store Compressed Pointer
 5117 instruct storeN(iRegN src, memory mem)
 5118 %{
 5119   predicate(n->as_Store()->barrier_data() == 0);
 5120   match(Set mem (StoreN mem src));
 5121 
 5122   ins_cost(STORE_COST);
 5123   format %{ "sw  $src, $mem\t# compressed ptr, #@storeN" %}
 5124 
 5125   ins_encode %{
 5126     __ sw(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
 5127   %}
 5128 
 5129   ins_pipe(istore_reg_mem);
 5130 %}
 5131 
 5132 instruct storeImmN0(immN0 zero, memory mem)
 5133 %{
 5134   predicate(n->as_Store()->barrier_data() == 0);
 5135   match(Set mem (StoreN mem zero));
 5136 
 5137   ins_cost(STORE_COST);
 5138   format %{ "sw  zr, $mem\t# compressed ptr, #@storeImmN0" %}
 5139 
 5140   ins_encode %{
 5141     __ sw(zr, Address(as_Register($mem$$base), $mem$$disp));
 5142   %}
 5143 
 5144   ins_pipe(istore_reg_mem);
 5145 %}
 5146 
 5147 // Store Float
 5148 instruct storeF(fRegF src, memory mem)
 5149 %{
 5150   match(Set mem (StoreF mem src));
 5151 
 5152   ins_cost(STORE_COST);
 5153   format %{ "fsw  $src, $mem\t# float, #@storeF" %}
 5154 
 5155   ins_encode %{
 5156     __ fsw(as_FloatRegister($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
 5157   %}
 5158 
 5159   ins_pipe(fp_store_reg_s);
 5160 %}
 5161 
 5162 // Store Double
 5163 instruct storeD(fRegD src, memory mem)
 5164 %{
 5165   match(Set mem (StoreD mem src));
 5166 
 5167   ins_cost(STORE_COST);
 5168   format %{ "fsd  $src, $mem\t# double, #@storeD" %}
 5169 
 5170   ins_encode %{
 5171     __ fsd(as_FloatRegister($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
 5172   %}
 5173 
 5174   ins_pipe(fp_store_reg_d);
 5175 %}
 5176 
 5177 // Store Compressed Klass Pointer
 5178 instruct storeNKlass(iRegN src, memory mem)
 5179 %{
 5180   match(Set mem (StoreNKlass mem src));
 5181 
 5182   ins_cost(STORE_COST);
 5183   format %{ "sw  $src, $mem\t# compressed klass ptr, #@storeNKlass" %}
 5184 
 5185   ins_encode %{
 5186     __ sw(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
 5187   %}
 5188 
 5189   ins_pipe(istore_reg_mem);
 5190 %}
 5191 
 5192 // ============================================================================
 5193 // Prefetch instructions
 5194 // Must be safe to execute with invalid address (cannot fault).
 5195 
 5196 instruct prefetchalloc( memory mem ) %{
 5197   predicate(UseZicbop);
 5198   match(PrefetchAllocation mem);
 5199 
 5200   ins_cost(ALU_COST * 1);
 5201   format %{ "prefetch_w $mem\t# Prefetch for write" %}
 5202 
 5203   ins_encode %{
 5204     if (Assembler::is_simm12($mem$$disp)) {
 5205       if (($mem$$disp & 0x1f) == 0) {
 5206         __ prefetch_w(as_Register($mem$$base), $mem$$disp);
 5207       } else {
 5208         __ addi(t0, as_Register($mem$$base), $mem$$disp);
 5209         __ prefetch_w(t0, 0);
 5210       }
 5211     } else {
 5212       __ mv(t0, $mem$$disp);
 5213       __ add(t0, as_Register($mem$$base), t0);
 5214       __ prefetch_w(t0, 0);
 5215     }
 5216   %}
 5217 
 5218   ins_pipe(iload_prefetch);
 5219 %}
 5220 
 5221 // ============================================================================
 5222 // Atomic operation instructions
 5223 //
 5224 
 5225 // standard CompareAndSwapX when we are using barriers
 5226 // these have higher priority than the rules selected by a predicate
 5227 instruct compareAndSwapB_narrow(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
 5228                                 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
 5229 %{
 5230   predicate(!UseZabha || !UseZacas);
 5231 
 5232   match(Set res (CompareAndSwapB mem (Binary oldval newval)));
 5233 
 5234   ins_cost(2 * VOLATILE_REF_COST);
 5235 
 5236   effect(TEMP_DEF res, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3, KILL cr);
 5237 
 5238   format %{
 5239     "cmpxchg $mem, $oldval, $newval\t# (byte) if $mem == $oldval then $mem <-- $newval\n\t"
 5240     "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapB_narrow"
 5241   %}
 5242 
 5243   ins_encode %{
 5244     __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
 5245                             Assembler::relaxed /* acquire */, Assembler::rl /* release */, $res$$Register,
 5246                             true /* result as bool */, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
 5247   %}
 5248 
 5249   ins_pipe(pipe_slow);
 5250 %}
 5251 
 5252 instruct compareAndSwapB(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
 5253 %{
 5254   predicate(UseZabha && UseZacas);
 5255 
 5256   match(Set res (CompareAndSwapB mem (Binary oldval newval)));
 5257 
 5258   ins_cost(2 * VOLATILE_REF_COST);
 5259 
 5260   format %{
 5261     "cmpxchg $mem, $oldval, $newval\t# (byte) if $mem == $oldval then $mem <-- $newval\n\t"
 5262     "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapB"
 5263   %}
 5264 
 5265   ins_encode %{
 5266     __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
 5267                Assembler::relaxed /* acquire */, Assembler::rl /* release */, $res$$Register,
 5268                true /* result as bool */);
 5269   %}
 5270 
 5271   ins_pipe(pipe_slow);
 5272 %}
 5273 
 5274 instruct compareAndSwapS_narrow(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
 5275                                 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
 5276 %{
 5277   predicate(!UseZabha || !UseZacas);
 5278 
 5279   match(Set res (CompareAndSwapS mem (Binary oldval newval)));
 5280 
 5281   ins_cost(2 * VOLATILE_REF_COST);
 5282 
 5283   effect(TEMP_DEF res, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3, KILL cr);
 5284 
 5285   format %{
 5286     "cmpxchg $mem, $oldval, $newval\t# (short) if $mem == $oldval then $mem <-- $newval\n\t"
 5287     "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapS_narrow"
 5288   %}
 5289 
 5290   ins_encode %{
 5291     __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
 5292                             Assembler::relaxed /* acquire */, Assembler::rl /* release */, $res$$Register,
 5293                             true /* result as bool */, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
 5294   %}
 5295 
 5296   ins_pipe(pipe_slow);
 5297 %}
 5298 
 5299 instruct compareAndSwapS(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
 5300 %{
 5301   predicate(UseZabha && UseZacas);
 5302 
 5303   match(Set res (CompareAndSwapS mem (Binary oldval newval)));
 5304 
 5305   ins_cost(2 * VOLATILE_REF_COST);
 5306 
 5307   format %{
 5308     "cmpxchg $mem, $oldval, $newval\t# (short) if $mem == $oldval then $mem <-- $newval\n\t"
 5309     "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapS"
 5310   %}
 5311 
 5312   ins_encode %{
 5313     __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
 5314                Assembler::relaxed /* acquire */, Assembler::rl /* release */, $res$$Register,
 5315                true /* result as bool */);
 5316   %}
 5317 
 5318   ins_pipe(pipe_slow);
 5319 %}
 5320 
 5321 instruct compareAndSwapI(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
 5322 %{
 5323   match(Set res (CompareAndSwapI mem (Binary oldval newval)));
 5324 
 5325   ins_cost(2 * VOLATILE_REF_COST);
 5326 
 5327   format %{
 5328     "cmpxchg $mem, $oldval, $newval\t# (int) if $mem == $oldval then $mem <-- $newval\n\t"
 5329     "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapI"
 5330   %}
 5331 
 5332   ins_encode %{
 5333     __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
 5334                /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
 5335                /*result as bool*/ true);
 5336   %}
 5337 
 5338   ins_pipe(pipe_slow);
 5339 %}
 5340 
 5341 instruct compareAndSwapL(iRegINoSp res, indirect mem, iRegL oldval, iRegL newval)
 5342 %{
 5343   match(Set res (CompareAndSwapL mem (Binary oldval newval)));
 5344 
 5345   ins_cost(2 * VOLATILE_REF_COST);
 5346 
 5347   format %{
 5348     "cmpxchg $mem, $oldval, $newval\t# (long) if $mem == $oldval then $mem <-- $newval\n\t"
 5349     "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapL"
 5350   %}
 5351 
 5352   ins_encode %{
 5353     __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
 5354                /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
 5355                /*result as bool*/ true);
 5356   %}
 5357 
 5358   ins_pipe(pipe_slow);
 5359 %}
 5360 
 5361 instruct compareAndSwapP(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval)
 5362 %{
 5363   predicate(n->as_LoadStore()->barrier_data() == 0);
 5364 
 5365   match(Set res (CompareAndSwapP mem (Binary oldval newval)));
 5366 
 5367   ins_cost(2 * VOLATILE_REF_COST);
 5368 
 5369   format %{
 5370     "cmpxchg $mem, $oldval, $newval\t# (ptr) if $mem == $oldval then $mem <-- $newval\n\t"
 5371     "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapP"
 5372   %}
 5373 
 5374   ins_encode %{
 5375     __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
 5376                /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
 5377                /*result as bool*/ true);
 5378   %}
 5379 
 5380   ins_pipe(pipe_slow);
 5381 %}
 5382 
 5383 instruct compareAndSwapN(iRegINoSp res, indirect mem, iRegN oldval, iRegN newval)
 5384 %{
 5385   predicate(n->as_LoadStore()->barrier_data() == 0);
 5386 
 5387   match(Set res (CompareAndSwapN mem (Binary oldval newval)));
 5388 
 5389   ins_cost(2 * VOLATILE_REF_COST);
 5390 
 5391   format %{
 5392     "cmpxchg $mem, $oldval, $newval\t# (narrow oop) if $mem == $oldval then $mem <-- $newval\n\t"
 5393     "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapN"
 5394   %}
 5395 
 5396   ins_encode %{
 5397     __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
 5398                /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
 5399                /*result as bool*/ true);
 5400   %}
 5401 
 5402   ins_pipe(pipe_slow);
 5403 %}
 5404 
 5405 // alternative CompareAndSwapX when we are eliding barriers
 5406 instruct compareAndSwapBAcq_narrow(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
 5407                                    iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
 5408 %{
 5409   predicate((!UseZabha || !UseZacas) && needs_acquiring_load_reserved(n));
 5410 
 5411   match(Set res (CompareAndSwapB mem (Binary oldval newval)));
 5412 
 5413   ins_cost(2 * VOLATILE_REF_COST);
 5414 
 5415   effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
 5416 
 5417   format %{
 5418     "cmpxchg_acq $mem, $oldval, $newval\t# (byte) if $mem == $oldval then $mem <-- $newval\n\t"
 5419     "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapBAcq_narrow"
 5420   %}
 5421 
 5422   ins_encode %{
 5423     __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
 5424                             Assembler::aq /* acquire */, Assembler::rl /* release */, $res$$Register,
 5425                             true /* result as bool */, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
 5426   %}
 5427 
 5428   ins_pipe(pipe_slow);
 5429 %}
 5430 
 5431 instruct compareAndSwapBAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
 5432 %{
 5433   predicate((UseZabha && UseZacas) && needs_acquiring_load_reserved(n));
 5434 
 5435   match(Set res (CompareAndSwapB mem (Binary oldval newval)));
 5436 
 5437   ins_cost(2 * VOLATILE_REF_COST);
 5438 
 5439   format %{
 5440     "cmpxchg $mem, $oldval, $newval\t# (byte) if $mem == $oldval then $mem <-- $newval\n\t"
 5441     "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapBAcq"
 5442   %}
 5443 
 5444   ins_encode %{
 5445     __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
 5446                Assembler::aq /* acquire */, Assembler::rl /* release */, $res$$Register,
 5447                true /* result as bool */);
 5448   %}
 5449 
 5450   ins_pipe(pipe_slow);
 5451 %}
 5452 
 5453 instruct compareAndSwapSAcq_narrow(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
 5454                                    iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
 5455 %{
 5456   predicate((!UseZabha || !UseZacas) && needs_acquiring_load_reserved(n));
 5457 
 5458   match(Set res (CompareAndSwapS mem (Binary oldval newval)));
 5459 
 5460   ins_cost(2 * VOLATILE_REF_COST);
 5461 
 5462   effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
 5463 
 5464   format %{
 5465     "cmpxchg_acq $mem, $oldval, $newval\t# (short) if $mem == $oldval then $mem <-- $newval\n\t"
 5466     "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapSAcq_narrow"
 5467   %}
 5468 
 5469   ins_encode %{
 5470     __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
 5471                             Assembler::aq /* acquire */, Assembler::rl /* release */, $res$$Register,
 5472                             true /* result as bool */, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
 5473   %}
 5474 
 5475   ins_pipe(pipe_slow);
 5476 %}
 5477 
 5478 instruct compareAndSwapSAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
 5479 %{
 5480   predicate((UseZabha && UseZacas) && needs_acquiring_load_reserved(n));
 5481 
 5482   match(Set res (CompareAndSwapS mem (Binary oldval newval)));
 5483 
 5484   ins_cost(2 * VOLATILE_REF_COST);
 5485 
 5486   format %{
 5487     "cmpxchg $mem, $oldval, $newval\t# (short) if $mem == $oldval then $mem <-- $newval\n\t"
 5488     "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapSAcq"
 5489   %}
 5490 
 5491   ins_encode %{
 5492     __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
 5493                Assembler::aq /* acquire */, Assembler::rl /* release */, $res$$Register,
 5494                true /* result as bool */);
 5495   %}
 5496 
 5497   ins_pipe(pipe_slow);
 5498 %}
 5499 
 5500 instruct compareAndSwapIAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
 5501 %{
 5502   predicate(needs_acquiring_load_reserved(n));
 5503 
 5504   match(Set res (CompareAndSwapI mem (Binary oldval newval)));
 5505 
 5506   ins_cost(2 * VOLATILE_REF_COST);
 5507 
 5508   format %{
 5509     "cmpxchg_acq $mem, $oldval, $newval\t# (int) if $mem == $oldval then $mem <-- $newval\n\t"
 5510     "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapIAcq"
 5511   %}
 5512 
 5513   ins_encode %{
 5514     __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
 5515                /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
 5516                /*result as bool*/ true);
 5517   %}
 5518 
 5519   ins_pipe(pipe_slow);
 5520 %}
 5521 
 5522 instruct compareAndSwapLAcq(iRegINoSp res, indirect mem, iRegL oldval, iRegL newval)
 5523 %{
 5524   predicate(needs_acquiring_load_reserved(n));
 5525 
 5526   match(Set res (CompareAndSwapL mem (Binary oldval newval)));
 5527 
 5528   ins_cost(2 * VOLATILE_REF_COST);
 5529 
 5530   format %{
 5531     "cmpxchg_acq $mem, $oldval, $newval\t# (long) if $mem == $oldval then $mem <-- $newval\n\t"
 5532     "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapLAcq"
 5533   %}
 5534 
 5535   ins_encode %{
 5536     __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
 5537                /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
 5538                /*result as bool*/ true);
 5539   %}
 5540 
 5541   ins_pipe(pipe_slow);
 5542 %}
 5543 
 5544 instruct compareAndSwapPAcq(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval)
 5545 %{
 5546   predicate(needs_acquiring_load_reserved(n) && (n->as_LoadStore()->barrier_data() == 0));
 5547 
 5548   match(Set res (CompareAndSwapP mem (Binary oldval newval)));
 5549 
 5550   ins_cost(2 * VOLATILE_REF_COST);
 5551 
 5552   format %{
 5553     "cmpxchg_acq $mem, $oldval, $newval\t# (ptr) if $mem == $oldval then $mem <-- $newval\n\t"
 5554     "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapPAcq"
 5555   %}
 5556 
 5557   ins_encode %{
 5558     __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
 5559                /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
 5560                /*result as bool*/ true);
 5561   %}
 5562 
 5563   ins_pipe(pipe_slow);
 5564 %}
 5565 
 5566 instruct compareAndSwapNAcq(iRegINoSp res, indirect mem, iRegN oldval, iRegN newval)
 5567 %{
 5568   predicate(needs_acquiring_load_reserved(n) && n->as_LoadStore()->barrier_data() == 0);
 5569 
 5570   match(Set res (CompareAndSwapN mem (Binary oldval newval)));
 5571 
 5572   ins_cost(2 * VOLATILE_REF_COST);
 5573 
 5574   format %{
 5575     "cmpxchg_acq $mem, $oldval, $newval\t# (narrow oop) if $mem == $oldval then $mem <-- $newval\n\t"
 5576     "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapNAcq"
 5577   %}
 5578 
 5579   ins_encode %{
 5580     __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
 5581                /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
 5582                /*result as bool*/ true);
 5583   %}
 5584 
 5585   ins_pipe(pipe_slow);
 5586 %}
 5587 
 5588 // Sundry CAS operations.  Note that release is always true,
 5589 // regardless of the memory ordering of the CAS.  This is because we
 5590 // need the volatile case to be sequentially consistent but there is
 5591 // no trailing StoreLoad barrier emitted by C2.  Unfortunately we
 5592 // can't check the type of memory ordering here, so we always emit a
 5593 // sc_d(w) with rl bit set.
 5594 instruct compareAndExchangeB_narrow(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
 5595                                     iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
 5596 %{
 5597   predicate(!UseZabha || !UseZacas);
 5598 
 5599   match(Set res (CompareAndExchangeB mem (Binary oldval newval)));
 5600 
 5601   ins_cost(2 * VOLATILE_REF_COST);
 5602 
 5603   effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
 5604 
 5605   format %{
 5606     "cmpxchg $res = $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeB_narrow"
 5607   %}
 5608 
 5609   ins_encode %{
 5610     __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
 5611                             /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
 5612                             /*result_as_bool*/ false, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
 5613   %}
 5614 
 5615   ins_pipe(pipe_slow);
 5616 %}
 5617 
 5618 instruct compareAndExchangeB(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
 5619 %{
 5620   predicate(UseZabha && UseZacas);
 5621 
 5622   match(Set res (CompareAndExchangeB mem (Binary oldval newval)));
 5623 
 5624   ins_cost(2 * VOLATILE_REF_COST);
 5625 
 5626   format %{
 5627     "cmpxchg $res = $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeB"
 5628   %}
 5629 
 5630   ins_encode %{
 5631     __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
 5632                /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
 5633   %}
 5634 
 5635   ins_pipe(pipe_slow);
 5636 %}
 5637 
 5638 instruct compareAndExchangeS_narrow(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
 5639                                     iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
 5640 %{
 5641   predicate(!UseZabha || !UseZacas);
 5642 
 5643   match(Set res (CompareAndExchangeS mem (Binary oldval newval)));
 5644 
 5645   ins_cost(2 * VOLATILE_REF_COST);
 5646 
 5647   effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
 5648 
 5649   format %{
 5650     "cmpxchg $res = $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeS_narrow"
 5651   %}
 5652 
 5653   ins_encode %{
 5654     __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
 5655                             /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
 5656                             /*result_as_bool*/ false, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
 5657   %}
 5658 
 5659   ins_pipe(pipe_slow);
 5660 %}
 5661 
 5662 instruct compareAndExchangeS(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
 5663 %{
 5664   predicate(UseZabha && UseZacas);
 5665 
 5666   match(Set res (CompareAndExchangeS mem (Binary oldval newval)));
 5667 
 5668   ins_cost(2 * VOLATILE_REF_COST);
 5669 
 5670   format %{
 5671     "cmpxchg $res = $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeS"
 5672   %}
 5673 
 5674   ins_encode %{
 5675     __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
 5676                /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
 5677   %}
 5678 
 5679   ins_pipe(pipe_slow);
 5680 %}
 5681 
 5682 instruct compareAndExchangeI(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
 5683 %{
 5684   match(Set res (CompareAndExchangeI mem (Binary oldval newval)));
 5685 
 5686   ins_cost(2 * VOLATILE_REF_COST);
 5687 
 5688   format %{
 5689     "cmpxchg $res = $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeI"
 5690   %}
 5691 
 5692   ins_encode %{
 5693     __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
 5694                /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
 5695   %}
 5696 
 5697   ins_pipe(pipe_slow);
 5698 %}
 5699 
 5700 instruct compareAndExchangeL(iRegLNoSp res, indirect mem, iRegL oldval, iRegL newval)
 5701 %{
 5702   match(Set res (CompareAndExchangeL mem (Binary oldval newval)));
 5703 
 5704   ins_cost(2 * VOLATILE_REF_COST);
 5705 
 5706   format %{
 5707     "cmpxchg $res = $mem, $oldval, $newval\t# (long, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeL"
 5708   %}
 5709 
 5710   ins_encode %{
 5711     __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
 5712                /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
 5713   %}
 5714 
 5715   ins_pipe(pipe_slow);
 5716 %}
 5717 
 5718 instruct compareAndExchangeN(iRegNNoSp res, indirect mem, iRegN oldval, iRegN newval)
 5719 %{
 5720   predicate(n->as_LoadStore()->barrier_data() == 0);
 5721 
 5722   match(Set res (CompareAndExchangeN mem (Binary oldval newval)));
 5723 
 5724   ins_cost(2 * VOLATILE_REF_COST);
 5725 
 5726   format %{
 5727     "cmpxchg $res = $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeN"
 5728   %}
 5729 
 5730   ins_encode %{
 5731     __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
 5732                /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
 5733   %}
 5734 
 5735   ins_pipe(pipe_slow);
 5736 %}
 5737 
 5738 instruct compareAndExchangeP(iRegPNoSp res, indirect mem, iRegP oldval, iRegP newval)
 5739 %{
 5740   predicate(n->as_LoadStore()->barrier_data() == 0);
 5741 
 5742   match(Set res (CompareAndExchangeP mem (Binary oldval newval)));
 5743 
 5744   ins_cost(2 * VOLATILE_REF_COST);
 5745 
 5746   format %{
 5747     "cmpxchg $res = $mem, $oldval, $newval\t# (ptr, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeP"
 5748   %}
 5749 
 5750   ins_encode %{
 5751     __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
 5752                /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
 5753   %}
 5754 
 5755   ins_pipe(pipe_slow);
 5756 %}
 5757 
 5758 instruct compareAndExchangeBAcq_narrow(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
 5759                                        iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
 5760 %{
 5761   predicate((!UseZabha || !UseZacas) && needs_acquiring_load_reserved(n));
 5762 
 5763   match(Set res (CompareAndExchangeB mem (Binary oldval newval)));
 5764 
 5765   ins_cost(2 * VOLATILE_REF_COST);
 5766 
 5767   effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
 5768 
 5769   format %{
 5770     "cmpxchg_acq $res = $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeBAcq_narrow"
 5771   %}
 5772 
 5773   ins_encode %{
 5774     __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
 5775                             /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
 5776                             /*result_as_bool*/ false, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
 5777   %}
 5778 
 5779   ins_pipe(pipe_slow);
 5780 %}
 5781 
 5782 instruct compareAndExchangeBAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
 5783 %{
 5784   predicate((UseZabha && UseZacas) && needs_acquiring_load_reserved(n));
 5785 
 5786   match(Set res (CompareAndExchangeB mem (Binary oldval newval)));
 5787 
 5788   ins_cost(2 * VOLATILE_REF_COST);
 5789 
 5790   format %{
 5791     "cmpxchg_acq $res = $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeBAcq"
 5792   %}
 5793 
 5794   ins_encode %{
 5795     __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
 5796                /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
 5797   %}
 5798 
 5799   ins_pipe(pipe_slow);
 5800 %}
 5801 
 5802 instruct compareAndExchangeSAcq_narrow(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
 5803                                        iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
 5804 %{
 5805   predicate((!UseZabha || !UseZacas) && needs_acquiring_load_reserved(n));
 5806 
 5807   match(Set res (CompareAndExchangeS mem (Binary oldval newval)));
 5808 
 5809   ins_cost(2 * VOLATILE_REF_COST);
 5810 
 5811   effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
 5812 
 5813   format %{
 5814     "cmpxchg_acq $res = $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeSAcq_narrow"
 5815   %}
 5816 
 5817   ins_encode %{
 5818     __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
 5819                             /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
 5820                             /*result_as_bool*/ false, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
 5821   %}
 5822 
 5823   ins_pipe(pipe_slow);
 5824 %}
 5825 
 5826 instruct compareAndExchangeSAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
 5827 %{
 5828   predicate((UseZabha && UseZacas) && needs_acquiring_load_reserved(n));
 5829 
 5830   match(Set res (CompareAndExchangeS mem (Binary oldval newval)));
 5831 
 5832   ins_cost(2 * VOLATILE_REF_COST);
 5833 
 5834   format %{
 5835     "cmpxchg_acq $res = $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeSAcq"
 5836   %}
 5837 
 5838   ins_encode %{
 5839     __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
 5840                /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
 5841   %}
 5842 
 5843   ins_pipe(pipe_slow);
 5844 %}
 5845 
 5846 instruct compareAndExchangeIAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
 5847 %{
 5848   predicate(needs_acquiring_load_reserved(n));
 5849 
 5850   match(Set res (CompareAndExchangeI mem (Binary oldval newval)));
 5851 
 5852   ins_cost(2 * VOLATILE_REF_COST);
 5853 
 5854   format %{
 5855     "cmpxchg_acq $res = $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeIAcq"
 5856   %}
 5857 
 5858   ins_encode %{
 5859     __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
 5860                /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
 5861   %}
 5862 
 5863   ins_pipe(pipe_slow);
 5864 %}
 5865 
 5866 instruct compareAndExchangeLAcq(iRegLNoSp res, indirect mem, iRegL oldval, iRegL newval)
 5867 %{
 5868   predicate(needs_acquiring_load_reserved(n));
 5869 
 5870   match(Set res (CompareAndExchangeL mem (Binary oldval newval)));
 5871 
 5872   ins_cost(2 * VOLATILE_REF_COST);
 5873 
 5874   format %{
 5875     "cmpxchg_acq $res = $mem, $oldval, $newval\t# (long, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeLAcq"
 5876   %}
 5877 
 5878   ins_encode %{
 5879     __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
 5880                /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
 5881   %}
 5882 
 5883   ins_pipe(pipe_slow);
 5884 %}
 5885 
 5886 instruct compareAndExchangeNAcq(iRegNNoSp res, indirect mem, iRegN oldval, iRegN newval)
 5887 %{
 5888   predicate(needs_acquiring_load_reserved(n) && n->as_LoadStore()->barrier_data() == 0);
 5889 
 5890   match(Set res (CompareAndExchangeN mem (Binary oldval newval)));
 5891 
 5892   ins_cost(2 * VOLATILE_REF_COST);
 5893 
 5894   format %{
 5895     "cmpxchg_acq $res = $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeNAcq"
 5896   %}
 5897 
 5898   ins_encode %{
 5899     __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
 5900                /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
 5901   %}
 5902 
 5903   ins_pipe(pipe_slow);
 5904 %}
 5905 
 5906 instruct compareAndExchangePAcq(iRegPNoSp res, indirect mem, iRegP oldval, iRegP newval)
 5907 %{
 5908   predicate(needs_acquiring_load_reserved(n) && (n->as_LoadStore()->barrier_data() == 0));
 5909 
 5910   match(Set res (CompareAndExchangeP mem (Binary oldval newval)));
 5911 
 5912   ins_cost(2 * VOLATILE_REF_COST);
 5913 
 5914   format %{
 5915     "cmpxchg_acq $res = $mem, $oldval, $newval\t# (ptr, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangePAcq"
 5916   %}
 5917 
 5918   ins_encode %{
 5919     __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
 5920                /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
 5921   %}
 5922 
 5923   ins_pipe(pipe_slow);
 5924 %}
 5925 
 5926 instruct weakCompareAndSwapB_narrow(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
 5927                                     iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
 5928 %{
 5929   predicate(!UseZabha || !UseZacas);
 5930 
 5931   match(Set res (WeakCompareAndSwapB mem (Binary oldval newval)));
 5932 
 5933   ins_cost(2 * VOLATILE_REF_COST);
 5934 
 5935   effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
 5936 
 5937   format %{
 5938     "weak_cmpxchg $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval\n\t"
 5939     "# $res == 1 when success, #@weakCompareAndSwapB_narrow"
 5940   %}
 5941 
 5942   ins_encode %{
 5943     __ weak_cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
 5944                                  /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
 5945                                  $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
 5946   %}
 5947 
 5948   ins_pipe(pipe_slow);
 5949 %}
 5950 
 5951 instruct weakCompareAndSwapB(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
 5952 %{
 5953   predicate(UseZabha && UseZacas);
 5954 
 5955   match(Set res (WeakCompareAndSwapB mem (Binary oldval newval)));
 5956 
 5957   ins_cost(2 * VOLATILE_REF_COST);
 5958 
 5959   format %{
 5960     "weak_cmpxchg $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval\n\t"
 5961     "# $res == 1 when success, #@weakCompareAndSwapB"
 5962   %}
 5963 
 5964   ins_encode %{
 5965     __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
 5966                     /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
 5967   %}
 5968 
 5969   ins_pipe(pipe_slow);
 5970 %}
 5971 
 5972 instruct weakCompareAndSwapS_narrow(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
 5973                                     iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
 5974 %{
 5975   predicate(!UseZabha || !UseZacas);
 5976 
 5977   match(Set res (WeakCompareAndSwapS mem (Binary oldval newval)));
 5978 
 5979   ins_cost(2 * VOLATILE_REF_COST);
 5980 
 5981   effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
 5982 
 5983   format %{
 5984     "weak_cmpxchg $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval\n\t"
 5985     "# $res == 1 when success, #@weakCompareAndSwapS_narrow"
 5986   %}
 5987 
 5988   ins_encode %{
 5989     __ weak_cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
 5990                                  /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
 5991                                  $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
 5992   %}
 5993 
 5994   ins_pipe(pipe_slow);
 5995 %}
 5996 
 5997 instruct weakCompareAndSwapS(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
 5998 %{
 5999   predicate(UseZabha && UseZacas);
 6000 
 6001   match(Set res (WeakCompareAndSwapS mem (Binary oldval newval)));
 6002 
 6003   ins_cost(2 * VOLATILE_REF_COST);
 6004 
 6005   format %{
 6006     "weak_cmpxchg $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval\n\t"
 6007     "# $res == 1 when success, #@weakCompareAndSwapS"
 6008   %}
 6009 
 6010   ins_encode %{
 6011     __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
 6012                     /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
 6013   %}
 6014 
 6015   ins_pipe(pipe_slow);
 6016 %}
 6017 
 6018 instruct weakCompareAndSwapI(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
 6019 %{
 6020   match(Set res (WeakCompareAndSwapI mem (Binary oldval newval)));
 6021 
 6022   ins_cost(2 * VOLATILE_REF_COST);
 6023 
 6024   format %{
 6025     "weak_cmpxchg $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval\n\t"
 6026     "# $res == 1 when success, #@weakCompareAndSwapI"
 6027   %}
 6028 
 6029   ins_encode %{
 6030     __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
 6031                     /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
 6032   %}
 6033 
 6034   ins_pipe(pipe_slow);
 6035 %}
 6036 
 6037 instruct weakCompareAndSwapL(iRegINoSp res, indirect mem, iRegL oldval, iRegL newval)
 6038 %{
 6039   match(Set res (WeakCompareAndSwapL mem (Binary oldval newval)));
 6040 
 6041   ins_cost(2 * VOLATILE_REF_COST);
 6042 
 6043   format %{
 6044     "weak_cmpxchg $mem, $oldval, $newval\t# (long, weak) if $mem == $oldval then $mem <-- $newval\n\t"
 6045     "# $res == 1 when success, #@weakCompareAndSwapL"
 6046   %}
 6047 
 6048   ins_encode %{
 6049     __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
 6050                     /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
 6051   %}
 6052 
 6053   ins_pipe(pipe_slow);
 6054 %}
 6055 
 6056 instruct weakCompareAndSwapN(iRegINoSp res, indirect mem, iRegN oldval, iRegN newval)
 6057 %{
 6058   predicate(n->as_LoadStore()->barrier_data() == 0);
 6059 
 6060   match(Set res (WeakCompareAndSwapN mem (Binary oldval newval)));
 6061 
 6062   ins_cost(2 * VOLATILE_REF_COST);
 6063 
 6064   format %{
 6065     "weak_cmpxchg $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval\n\t"
 6066     "# $res == 1 when success, #@weakCompareAndSwapN"
 6067   %}
 6068 
 6069   ins_encode %{
 6070     __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
 6071                     /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
 6072   %}
 6073 
 6074   ins_pipe(pipe_slow);
 6075 %}
 6076 
 6077 instruct weakCompareAndSwapP(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval)
 6078 %{
 6079   predicate(n->as_LoadStore()->barrier_data() == 0);
 6080 
 6081   match(Set res (WeakCompareAndSwapP mem (Binary oldval newval)));
 6082 
 6083   ins_cost(2 * VOLATILE_REF_COST);
 6084 
 6085   format %{
 6086     "weak_cmpxchg $mem, $oldval, $newval\t# (ptr, weak) if $mem == $oldval then $mem <-- $newval\n\t"
 6087     "# $res == 1 when success, #@weakCompareAndSwapP"
 6088   %}
 6089 
 6090   ins_encode %{
 6091     __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
 6092                     /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
 6093   %}
 6094 
 6095   ins_pipe(pipe_slow);
 6096 %}
 6097 
 6098 instruct weakCompareAndSwapBAcq_narrow(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
 6099                                        iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
 6100 %{
 6101   predicate((!UseZabha || !UseZacas) && needs_acquiring_load_reserved(n));
 6102 
 6103   match(Set res (WeakCompareAndSwapB mem (Binary oldval newval)));
 6104 
 6105   ins_cost(2 * VOLATILE_REF_COST);
 6106 
 6107   effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
 6108 
 6109   format %{
 6110     "weak_cmpxchg_acq $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval\n\t"
 6111     "# $res == 1 when success, #@weakCompareAndSwapBAcq_narrow"
 6112   %}
 6113 
 6114   ins_encode %{
 6115     __ weak_cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
 6116                                  /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
 6117                                  $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
 6118   %}
 6119 
 6120   ins_pipe(pipe_slow);
 6121 %}
 6122 
 6123 instruct weakCompareAndSwapBAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
 6124 %{
 6125   predicate((UseZabha && UseZacas) && needs_acquiring_load_reserved(n));
 6126 
 6127   match(Set res (WeakCompareAndSwapB mem (Binary oldval newval)));
 6128 
 6129   ins_cost(2 * VOLATILE_REF_COST);
 6130 
 6131   format %{
 6132     "weak_cmpxchg_acq $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval\n\t"
 6133     "# $res == 1 when success, #@weakCompareAndSwapBAcq"
 6134   %}
 6135 
 6136   ins_encode %{
 6137     __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
 6138                     /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
 6139   %}
 6140 
 6141   ins_pipe(pipe_slow);
 6142 %}
 6143 
 6144 instruct weakCompareAndSwapSAcq_narrow(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
 6145                                        iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
 6146 %{
 6147   predicate((!UseZabha || !UseZacas) && needs_acquiring_load_reserved(n));
 6148 
 6149   match(Set res (WeakCompareAndSwapS mem (Binary oldval newval)));
 6150 
 6151   ins_cost(2 * VOLATILE_REF_COST);
 6152 
 6153   effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
 6154 
 6155   format %{
 6156     "weak_cmpxchg_acq $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval\n\t"
 6157     "# $res == 1 when success, #@weakCompareAndSwapSAcq_narrow"
 6158   %}
 6159 
 6160   ins_encode %{
 6161     __ weak_cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
 6162                                  /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
 6163                                  $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
 6164   %}
 6165 
 6166   ins_pipe(pipe_slow);
 6167 %}
 6168 
 6169 instruct weakCompareAndSwapSAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
 6170 %{
 6171   predicate((UseZabha && UseZacas) && needs_acquiring_load_reserved(n));
 6172 
 6173   match(Set res (WeakCompareAndSwapS mem (Binary oldval newval)));
 6174 
 6175   ins_cost(2 * VOLATILE_REF_COST);
 6176 
 6177   format %{
 6178     "weak_cmpxchg_acq $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval\n\t"
 6179     "# $res == 1 when success, #@weakCompareAndSwapSAcq"
 6180   %}
 6181 
 6182   ins_encode %{
 6183     __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
 6184                     /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
 6185   %}
 6186 
 6187   ins_pipe(pipe_slow);
 6188 %}
 6189 
 6190 instruct weakCompareAndSwapIAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
 6191 %{
 6192   predicate(needs_acquiring_load_reserved(n));
 6193 
 6194   match(Set res (WeakCompareAndSwapI mem (Binary oldval newval)));
 6195 
 6196   ins_cost(2 * VOLATILE_REF_COST);
 6197 
 6198   format %{
 6199     "weak_cmpxchg_acq $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval\n\t"
 6200     "# $res == 1 when success, #@weakCompareAndSwapIAcq"
 6201   %}
 6202 
 6203   ins_encode %{
 6204     __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
 6205                     /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
 6206   %}
 6207 
 6208   ins_pipe(pipe_slow);
 6209 %}
 6210 
 6211 instruct weakCompareAndSwapLAcq(iRegINoSp res, indirect mem, iRegL oldval, iRegL newval)
 6212 %{
 6213   predicate(needs_acquiring_load_reserved(n));
 6214 
 6215   match(Set res (WeakCompareAndSwapL mem (Binary oldval newval)));
 6216 
 6217   ins_cost(2 * VOLATILE_REF_COST);
 6218 
 6219   format %{
 6220     "weak_cmpxchg_acq $mem, $oldval, $newval\t# (long, weak) if $mem == $oldval then $mem <-- $newval\n\t"
 6221     "# $res == 1 when success, #@weakCompareAndSwapLAcq"
 6222   %}
 6223 
 6224   ins_encode %{
 6225     __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
 6226                     /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
 6227   %}
 6228 
 6229   ins_pipe(pipe_slow);
 6230 %}
 6231 
 6232 instruct weakCompareAndSwapNAcq(iRegINoSp res, indirect mem, iRegN oldval, iRegN newval)
 6233 %{
 6234   predicate(needs_acquiring_load_reserved(n) && n->as_LoadStore()->barrier_data() == 0);
 6235 
 6236   match(Set res (WeakCompareAndSwapN mem (Binary oldval newval)));
 6237 
 6238   ins_cost(2 * VOLATILE_REF_COST);
 6239 
 6240   format %{
 6241     "weak_cmpxchg_acq $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval\n\t"
 6242     "# $res == 1 when success, #@weakCompareAndSwapNAcq"
 6243   %}
 6244 
 6245   ins_encode %{
 6246     __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
 6247                     /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
 6248   %}
 6249 
 6250   ins_pipe(pipe_slow);
 6251 %}
 6252 
 6253 instruct weakCompareAndSwapPAcq(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval)
 6254 %{
 6255   predicate(needs_acquiring_load_reserved(n) && (n->as_LoadStore()->barrier_data() == 0));
 6256 
 6257   match(Set res (WeakCompareAndSwapP mem (Binary oldval newval)));
 6258 
 6259   ins_cost(2 * VOLATILE_REF_COST);
 6260 
 6261   format %{
 6262     "weak_cmpxchg_acq $mem, $oldval, $newval\t# (ptr, weak) if $mem == $oldval then $mem <-- $newval\n\t"
 6263     "\t# $res == 1 when success, #@weakCompareAndSwapPAcq"
 6264   %}
 6265 
 6266   ins_encode %{
 6267     __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
 6268                     /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
 6269   %}
 6270 
 6271   ins_pipe(pipe_slow);
 6272 %}
 6273 
 6274 instruct get_and_setI(indirect mem, iRegI newv, iRegINoSp prev)
 6275 %{
 6276   match(Set prev (GetAndSetI mem newv));
 6277 
 6278   ins_cost(ALU_COST);
 6279 
 6280   format %{ "atomic_xchgw  $prev, $newv, [$mem]\t#@get_and_setI" %}
 6281 
 6282   ins_encode %{
 6283     __ atomic_xchgw($prev$$Register, $newv$$Register, as_Register($mem$$base));
 6284   %}
 6285 
 6286   ins_pipe(pipe_serial);
 6287 %}
 6288 
 6289 instruct get_and_setL(indirect mem, iRegL newv, iRegLNoSp prev)
 6290 %{
 6291   match(Set prev (GetAndSetL mem newv));
 6292 
 6293   ins_cost(ALU_COST);
 6294 
 6295   format %{ "atomic_xchg  $prev, $newv, [$mem]\t#@get_and_setL" %}
 6296 
 6297   ins_encode %{
 6298     __ atomic_xchg($prev$$Register, $newv$$Register, as_Register($mem$$base));
 6299   %}
 6300 
 6301   ins_pipe(pipe_serial);
 6302 %}
 6303 
 6304 instruct get_and_setN(indirect mem, iRegN newv, iRegINoSp prev)
 6305 %{
 6306   predicate(n->as_LoadStore()->barrier_data() == 0);
 6307 
 6308   match(Set prev (GetAndSetN mem newv));
 6309 
 6310   ins_cost(ALU_COST);
 6311 
 6312   format %{ "atomic_xchgwu $prev, $newv, [$mem]\t#@get_and_setN" %}
 6313 
 6314   ins_encode %{
 6315     __ atomic_xchgwu($prev$$Register, $newv$$Register, as_Register($mem$$base));
 6316   %}
 6317 
 6318   ins_pipe(pipe_serial);
 6319 %}
 6320 
 6321 instruct get_and_setP(indirect mem, iRegP newv, iRegPNoSp prev)
 6322 %{
 6323   predicate(n->as_LoadStore()->barrier_data() == 0);
 6324   match(Set prev (GetAndSetP mem newv));
 6325 
 6326   ins_cost(ALU_COST);
 6327 
 6328   format %{ "atomic_xchg  $prev, $newv, [$mem]\t#@get_and_setP" %}
 6329 
 6330   ins_encode %{
 6331     __ atomic_xchg($prev$$Register, $newv$$Register, as_Register($mem$$base));
 6332   %}
 6333 
 6334   ins_pipe(pipe_serial);
 6335 %}
 6336 
 6337 instruct get_and_setIAcq(indirect mem, iRegI newv, iRegINoSp prev)
 6338 %{
 6339   predicate(needs_acquiring_load_reserved(n));
 6340 
 6341   match(Set prev (GetAndSetI mem newv));
 6342 
 6343   ins_cost(ALU_COST);
 6344 
 6345   format %{ "atomic_xchgw_acq  $prev, $newv, [$mem]\t#@get_and_setIAcq" %}
 6346 
 6347   ins_encode %{
 6348     __ atomic_xchgalw($prev$$Register, $newv$$Register, as_Register($mem$$base));
 6349   %}
 6350 
 6351   ins_pipe(pipe_serial);
 6352 %}
 6353 
 6354 instruct get_and_setLAcq(indirect mem, iRegL newv, iRegLNoSp prev)
 6355 %{
 6356   predicate(needs_acquiring_load_reserved(n));
 6357 
 6358   match(Set prev (GetAndSetL mem newv));
 6359 
 6360   ins_cost(ALU_COST);
 6361 
 6362   format %{ "atomic_xchg_acq  $prev, $newv, [$mem]\t#@get_and_setLAcq" %}
 6363 
 6364   ins_encode %{
 6365     __ atomic_xchgal($prev$$Register, $newv$$Register, as_Register($mem$$base));
 6366   %}
 6367 
 6368   ins_pipe(pipe_serial);
 6369 %}
 6370 
 6371 instruct get_and_setNAcq(indirect mem, iRegN newv, iRegINoSp prev)
 6372 %{
 6373   predicate(needs_acquiring_load_reserved(n) && n->as_LoadStore()->barrier_data() == 0);
 6374 
 6375   match(Set prev (GetAndSetN mem newv));
 6376 
 6377   ins_cost(ALU_COST);
 6378 
 6379   format %{ "atomic_xchgwu_acq $prev, $newv, [$mem]\t#@get_and_setNAcq" %}
 6380 
 6381   ins_encode %{
 6382     __ atomic_xchgalwu($prev$$Register, $newv$$Register, as_Register($mem$$base));
 6383   %}
 6384 
 6385   ins_pipe(pipe_serial);
 6386 %}
 6387 
 6388 instruct get_and_setPAcq(indirect mem, iRegP newv, iRegPNoSp prev)
 6389 %{
 6390   predicate(needs_acquiring_load_reserved(n) && (n->as_LoadStore()->barrier_data() == 0));
 6391 
 6392   match(Set prev (GetAndSetP mem newv));
 6393 
 6394   ins_cost(ALU_COST);
 6395 
 6396   format %{ "atomic_xchg_acq  $prev, $newv, [$mem]\t#@get_and_setPAcq" %}
 6397 
 6398   ins_encode %{
 6399     __ atomic_xchgal($prev$$Register, $newv$$Register, as_Register($mem$$base));
 6400   %}
 6401 
 6402   ins_pipe(pipe_serial);
 6403 %}
 6404 
 6405 instruct get_and_addL(indirect mem, iRegLNoSp newval, iRegL incr)
 6406 %{
 6407   match(Set newval (GetAndAddL mem incr));
 6408 
 6409   ins_cost(ALU_COST);
 6410 
 6411   format %{ "get_and_addL $newval, [$mem], $incr\t#@get_and_addL" %}
 6412 
 6413   ins_encode %{
 6414     __ atomic_add($newval$$Register, $incr$$Register, as_Register($mem$$base));
 6415   %}
 6416 
 6417   ins_pipe(pipe_serial);
 6418 %}
 6419 
 6420 instruct get_and_addL_no_res(indirect mem, Universe dummy, iRegL incr)
 6421 %{
 6422   predicate(n->as_LoadStore()->result_not_used());
 6423 
 6424   match(Set dummy (GetAndAddL mem incr));
 6425 
 6426   ins_cost(ALU_COST);
 6427 
 6428   format %{ "get_and_addL [$mem], $incr\t#@get_and_addL_no_res" %}
 6429 
 6430   ins_encode %{
 6431     __ atomic_add(noreg, $incr$$Register, as_Register($mem$$base));
 6432   %}
 6433 
 6434   ins_pipe(pipe_serial);
 6435 %}
 6436 
 6437 instruct get_and_addLi(indirect mem, iRegLNoSp newval, immLAdd incr)
 6438 %{
 6439   match(Set newval (GetAndAddL mem incr));
 6440 
 6441   ins_cost(ALU_COST);
 6442 
 6443   format %{ "get_and_addL $newval, [$mem], $incr\t#@get_and_addLi" %}
 6444 
 6445   ins_encode %{
 6446     __ atomic_add($newval$$Register, $incr$$constant, as_Register($mem$$base));
 6447   %}
 6448 
 6449   ins_pipe(pipe_serial);
 6450 %}
 6451 
 6452 instruct get_and_addLi_no_res(indirect mem, Universe dummy, immLAdd incr)
 6453 %{
 6454   predicate(n->as_LoadStore()->result_not_used());
 6455 
 6456   match(Set dummy (GetAndAddL mem incr));
 6457 
 6458   ins_cost(ALU_COST);
 6459 
 6460   format %{ "get_and_addL [$mem], $incr\t#@get_and_addLi_no_res" %}
 6461 
 6462   ins_encode %{
 6463     __ atomic_add(noreg, $incr$$constant, as_Register($mem$$base));
 6464   %}
 6465 
 6466   ins_pipe(pipe_serial);
 6467 %}
 6468 
 6469 instruct get_and_addI(indirect mem, iRegINoSp newval, iRegIorL2I incr)
 6470 %{
 6471   match(Set newval (GetAndAddI mem incr));
 6472 
 6473   ins_cost(ALU_COST);
 6474 
 6475   format %{ "get_and_addI $newval, [$mem], $incr\t#@get_and_addI" %}
 6476 
 6477   ins_encode %{
 6478     __ atomic_addw($newval$$Register, $incr$$Register, as_Register($mem$$base));
 6479   %}
 6480 
 6481   ins_pipe(pipe_serial);
 6482 %}
 6483 
 6484 instruct get_and_addI_no_res(indirect mem, Universe dummy, iRegIorL2I incr)
 6485 %{
 6486   predicate(n->as_LoadStore()->result_not_used());
 6487 
 6488   match(Set dummy (GetAndAddI mem incr));
 6489 
 6490   ins_cost(ALU_COST);
 6491 
 6492   format %{ "get_and_addI [$mem], $incr\t#@get_and_addI_no_res" %}
 6493 
 6494   ins_encode %{
 6495     __ atomic_addw(noreg, $incr$$Register, as_Register($mem$$base));
 6496   %}
 6497 
 6498   ins_pipe(pipe_serial);
 6499 %}
 6500 
 6501 instruct get_and_addIi(indirect mem, iRegINoSp newval, immIAdd incr)
 6502 %{
 6503   match(Set newval (GetAndAddI mem incr));
 6504 
 6505   ins_cost(ALU_COST);
 6506 
 6507   format %{ "get_and_addI $newval, [$mem], $incr\t#@get_and_addIi" %}
 6508 
 6509   ins_encode %{
 6510     __ atomic_addw($newval$$Register, $incr$$constant, as_Register($mem$$base));
 6511   %}
 6512 
 6513   ins_pipe(pipe_serial);
 6514 %}
 6515 
 6516 instruct get_and_addIi_no_res(indirect mem, Universe dummy, immIAdd incr)
 6517 %{
 6518   predicate(n->as_LoadStore()->result_not_used());
 6519 
 6520   match(Set dummy (GetAndAddI mem incr));
 6521 
 6522   ins_cost(ALU_COST);
 6523 
 6524   format %{ "get_and_addI [$mem], $incr\t#@get_and_addIi_no_res" %}
 6525 
 6526   ins_encode %{
 6527     __ atomic_addw(noreg, $incr$$constant, as_Register($mem$$base));
 6528   %}
 6529 
 6530   ins_pipe(pipe_serial);
 6531 %}
 6532 
 6533 instruct get_and_addLAcq(indirect mem, iRegLNoSp newval, iRegL incr)
 6534 %{
 6535   predicate(needs_acquiring_load_reserved(n));
 6536 
 6537   match(Set newval (GetAndAddL mem incr));
 6538 
 6539   ins_cost(ALU_COST);
 6540 
 6541   format %{ "get_and_addL_acq $newval, [$mem], $incr\t#@get_and_addLAcq" %}
 6542 
 6543   ins_encode %{
 6544     __ atomic_addal($newval$$Register, $incr$$Register, as_Register($mem$$base));
 6545   %}
 6546 
 6547   ins_pipe(pipe_serial);
 6548 %}
 6549 
 6550 instruct get_and_addL_no_resAcq(indirect mem, Universe dummy, iRegL incr) %{
 6551   predicate(n->as_LoadStore()->result_not_used() && needs_acquiring_load_reserved(n));
 6552 
 6553   match(Set dummy (GetAndAddL mem incr));
 6554 
 6555   ins_cost(ALU_COST);
 6556 
 6557   format %{ "get_and_addL_acq [$mem], $incr\t#@get_and_addL_no_resAcq" %}
 6558 
 6559   ins_encode %{
 6560     __ atomic_addal(noreg, $incr$$Register, as_Register($mem$$base));
 6561   %}
 6562 
 6563   ins_pipe(pipe_serial);
 6564 %}
 6565 
 6566 instruct get_and_addLiAcq(indirect mem, iRegLNoSp newval, immLAdd incr)
 6567 %{
 6568   predicate(needs_acquiring_load_reserved(n));
 6569 
 6570   match(Set newval (GetAndAddL mem incr));
 6571 
 6572   ins_cost(ALU_COST);
 6573 
 6574   format %{ "get_and_addL_acq $newval, [$mem], $incr\t#@get_and_addLiAcq" %}
 6575 
 6576   ins_encode %{
 6577     __ atomic_addal($newval$$Register, $incr$$constant, as_Register($mem$$base));
 6578   %}
 6579 
 6580   ins_pipe(pipe_serial);
 6581 %}
 6582 
 6583 instruct get_and_addLi_no_resAcq(indirect mem, Universe dummy, immLAdd incr)
 6584 %{
 6585   predicate(n->as_LoadStore()->result_not_used() && needs_acquiring_load_reserved(n));
 6586 
 6587   match(Set dummy (GetAndAddL mem incr));
 6588 
 6589   ins_cost(ALU_COST);
 6590 
 6591   format %{ "get_and_addL_acq [$mem], $incr\t#@get_and_addLi_no_resAcq" %}
 6592 
 6593   ins_encode %{
 6594     __ atomic_addal(noreg, $incr$$constant, as_Register($mem$$base));
 6595   %}
 6596 
 6597   ins_pipe(pipe_serial);
 6598 %}
 6599 
 6600 instruct get_and_addIAcq(indirect mem, iRegINoSp newval, iRegIorL2I incr)
 6601 %{
 6602   predicate(needs_acquiring_load_reserved(n));
 6603 
 6604   match(Set newval (GetAndAddI mem incr));
 6605 
 6606   ins_cost(ALU_COST);
 6607 
 6608   format %{ "get_and_addI_acq $newval, [$mem], $incr\t#@get_and_addIAcq" %}
 6609 
 6610   ins_encode %{
 6611     __ atomic_addalw($newval$$Register, $incr$$Register, as_Register($mem$$base));
 6612   %}
 6613 
 6614   ins_pipe(pipe_serial);
 6615 %}
 6616 
 6617 instruct get_and_addI_no_resAcq(indirect mem, Universe dummy, iRegIorL2I incr)
 6618 %{
 6619   predicate(n->as_LoadStore()->result_not_used() && needs_acquiring_load_reserved(n));
 6620 
 6621   match(Set dummy (GetAndAddI mem incr));
 6622 
 6623   ins_cost(ALU_COST);
 6624 
 6625   format %{ "get_and_addI_acq [$mem], $incr\t#@get_and_addI_no_resAcq" %}
 6626 
 6627   ins_encode %{
 6628     __ atomic_addalw(noreg, $incr$$Register, as_Register($mem$$base));
 6629   %}
 6630 
 6631   ins_pipe(pipe_serial);
 6632 %}
 6633 
 6634 instruct get_and_addIiAcq(indirect mem, iRegINoSp newval, immIAdd incr)
 6635 %{
 6636   predicate(needs_acquiring_load_reserved(n));
 6637 
 6638   match(Set newval (GetAndAddI mem incr));
 6639 
 6640   ins_cost(ALU_COST);
 6641 
 6642   format %{ "get_and_addI_acq $newval, [$mem], $incr\t#@get_and_addIiAcq" %}
 6643 
 6644   ins_encode %{
 6645     __ atomic_addalw($newval$$Register, $incr$$constant, as_Register($mem$$base));
 6646   %}
 6647 
 6648   ins_pipe(pipe_serial);
 6649 %}
 6650 
 6651 instruct get_and_addIi_no_resAcq(indirect mem, Universe dummy, immIAdd incr)
 6652 %{
 6653   predicate(n->as_LoadStore()->result_not_used() && needs_acquiring_load_reserved(n));
 6654 
 6655   match(Set dummy (GetAndAddI mem incr));
 6656 
 6657   ins_cost(ALU_COST);
 6658 
 6659   format %{ "get_and_addI_acq [$mem], $incr\t#@get_and_addIi_no_resAcq" %}
 6660 
 6661   ins_encode %{
 6662     __ atomic_addalw(noreg, $incr$$constant, as_Register($mem$$base));
 6663   %}
 6664 
 6665   ins_pipe(pipe_serial);
 6666 %}
 6667 
 6668 // ============================================================================
 6669 // Arithmetic Instructions
 6670 //
 6671 
 6672 // Integer Addition
 6673 
 6674 // TODO
 6675 // these currently employ operations which do not set CR and hence are
 6676 // not flagged as killing CR but we would like to isolate the cases
 6677 // where we want to set flags from those where we don't. need to work
 6678 // out how to do that.
 6679 instruct addI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
 6680   match(Set dst (AddI src1 src2));
 6681 
 6682   ins_cost(ALU_COST);
 6683   format %{ "addw  $dst, $src1, $src2\t#@addI_reg_reg" %}
 6684 
 6685   ins_encode %{
 6686     __ addw(as_Register($dst$$reg),
 6687             as_Register($src1$$reg),
 6688             as_Register($src2$$reg));
 6689   %}
 6690 
 6691   ins_pipe(ialu_reg_reg);
 6692 %}
 6693 
 6694 instruct addI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immIAdd src2) %{
 6695   match(Set dst (AddI src1 src2));
 6696 
 6697   ins_cost(ALU_COST);
 6698   format %{ "addiw  $dst, $src1, $src2\t#@addI_reg_imm" %}
 6699 
 6700   ins_encode %{
 6701     __ addiw(as_Register($dst$$reg),
 6702              as_Register($src1$$reg),
 6703              $src2$$constant);
 6704   %}
 6705 
 6706   ins_pipe(ialu_reg_imm);
 6707 %}
 6708 
 6709 instruct addI_reg_imm_l2i(iRegINoSp dst, iRegL src1, immIAdd src2) %{
 6710   match(Set dst (AddI (ConvL2I src1) src2));
 6711 
 6712   ins_cost(ALU_COST);
 6713   format %{ "addiw  $dst, $src1, $src2\t#@addI_reg_imm_l2i" %}
 6714 
 6715   ins_encode %{
 6716     __ addiw(as_Register($dst$$reg),
 6717              as_Register($src1$$reg),
 6718              $src2$$constant);
 6719   %}
 6720 
 6721   ins_pipe(ialu_reg_imm);
 6722 %}
 6723 
 6724 // Pointer Addition
 6725 instruct addP_reg_reg(iRegPNoSp dst, iRegP src1, iRegL src2) %{
 6726   match(Set dst (AddP src1 src2));
 6727 
 6728   ins_cost(ALU_COST);
 6729   format %{ "add $dst, $src1, $src2\t# ptr, #@addP_reg_reg" %}
 6730 
 6731   ins_encode %{
 6732     __ add(as_Register($dst$$reg),
 6733            as_Register($src1$$reg),
 6734            as_Register($src2$$reg));
 6735   %}
 6736 
 6737   ins_pipe(ialu_reg_reg);
 6738 %}
 6739 
 6740 // If we shift more than 32 bits, we need not convert I2L.
 6741 instruct lShiftL_regI_immGE32(iRegLNoSp dst, iRegI src, uimmI6_ge32 scale) %{
 6742   match(Set dst (LShiftL (ConvI2L src) scale));
 6743   ins_cost(ALU_COST);
 6744   format %{ "slli  $dst, $src, $scale & 63\t#@lShiftL_regI_immGE32" %}
 6745 
 6746   ins_encode %{
 6747     __ slli(as_Register($dst$$reg), as_Register($src$$reg), $scale$$constant & 63);
 6748   %}
 6749 
 6750   ins_pipe(ialu_reg_shift);
 6751 %}
 6752 
 6753 // Pointer Immediate Addition
 6754 // n.b. this needs to be more expensive than using an indirect memory
 6755 // operand
 6756 instruct addP_reg_imm(iRegPNoSp dst, iRegP src1, immLAdd src2) %{
 6757   match(Set dst (AddP src1 src2));
 6758   ins_cost(ALU_COST);
 6759   format %{ "addi  $dst, $src1, $src2\t# ptr, #@addP_reg_imm" %}
 6760 
 6761   ins_encode %{
 6762     __ addi(as_Register($dst$$reg),
 6763             as_Register($src1$$reg),
 6764             $src2$$constant);
 6765   %}
 6766 
 6767   ins_pipe(ialu_reg_imm);
 6768 %}
 6769 
 6770 // Long Addition
 6771 instruct addL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
 6772   match(Set dst (AddL src1 src2));
 6773   ins_cost(ALU_COST);
 6774   format %{ "add  $dst, $src1, $src2\t#@addL_reg_reg" %}
 6775 
 6776   ins_encode %{
 6777     __ add(as_Register($dst$$reg),
 6778            as_Register($src1$$reg),
 6779            as_Register($src2$$reg));
 6780   %}
 6781 
 6782   ins_pipe(ialu_reg_reg);
 6783 %}
 6784 
 6785 // No constant pool entries requiredLong Immediate Addition.
 6786 instruct addL_reg_imm(iRegLNoSp dst, iRegL src1, immLAdd src2) %{
 6787   match(Set dst (AddL src1 src2));
 6788   ins_cost(ALU_COST);
 6789   format %{ "addi  $dst, $src1, $src2\t#@addL_reg_imm" %}
 6790 
 6791   ins_encode %{
 6792     // src2 is imm, so actually call the addi
 6793     __ addi(as_Register($dst$$reg),
 6794             as_Register($src1$$reg),
 6795             $src2$$constant);
 6796   %}
 6797 
 6798   ins_pipe(ialu_reg_imm);
 6799 %}
 6800 
 6801 // Integer Subtraction
 6802 instruct subI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
 6803   match(Set dst (SubI src1 src2));
 6804 
 6805   ins_cost(ALU_COST);
 6806   format %{ "subw  $dst, $src1, $src2\t#@subI_reg_reg" %}
 6807 
 6808   ins_encode %{
 6809     __ subw(as_Register($dst$$reg),
 6810             as_Register($src1$$reg),
 6811             as_Register($src2$$reg));
 6812   %}
 6813 
 6814   ins_pipe(ialu_reg_reg);
 6815 %}
 6816 
 6817 // Immediate Subtraction
 6818 instruct subI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immISub src2) %{
 6819   match(Set dst (SubI src1 src2));
 6820 
 6821   ins_cost(ALU_COST);
 6822   format %{ "addiw  $dst, $src1, -$src2\t#@subI_reg_imm" %}
 6823 
 6824   ins_encode %{
 6825     // src2 is imm, so actually call the addiw
 6826     __ subiw(as_Register($dst$$reg),
 6827              as_Register($src1$$reg),
 6828              $src2$$constant);
 6829   %}
 6830 
 6831   ins_pipe(ialu_reg_imm);
 6832 %}
 6833 
 6834 // Long Subtraction
 6835 instruct subL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
 6836   match(Set dst (SubL src1 src2));
 6837   ins_cost(ALU_COST);
 6838   format %{ "sub  $dst, $src1, $src2\t#@subL_reg_reg" %}
 6839 
 6840   ins_encode %{
 6841     __ sub(as_Register($dst$$reg),
 6842            as_Register($src1$$reg),
 6843            as_Register($src2$$reg));
 6844   %}
 6845 
 6846   ins_pipe(ialu_reg_reg);
 6847 %}
 6848 
 6849 // No constant pool entries requiredLong Immediate Subtraction.
 6850 instruct subL_reg_imm(iRegLNoSp dst, iRegL src1, immLSub src2) %{
 6851   match(Set dst (SubL src1 src2));
 6852   ins_cost(ALU_COST);
 6853   format %{ "addi  $dst, $src1, -$src2\t#@subL_reg_imm" %}
 6854 
 6855   ins_encode %{
 6856     // src2 is imm, so actually call the addi
 6857     __ subi(as_Register($dst$$reg),
 6858             as_Register($src1$$reg),
 6859             $src2$$constant);
 6860   %}
 6861 
 6862   ins_pipe(ialu_reg_imm);
 6863 %}
 6864 
 6865 // Integer Negation (special case for sub)
 6866 
 6867 instruct negI_reg(iRegINoSp dst, iRegIorL2I src, immI0 zero) %{
 6868   match(Set dst (SubI zero src));
 6869   ins_cost(ALU_COST);
 6870   format %{ "subw  $dst, x0, $src\t# int, #@negI_reg" %}
 6871 
 6872   ins_encode %{
 6873     // actually call the subw
 6874     __ negw(as_Register($dst$$reg),
 6875             as_Register($src$$reg));
 6876   %}
 6877 
 6878   ins_pipe(ialu_reg);
 6879 %}
 6880 
 6881 // Long Negation
 6882 
 6883 instruct negL_reg(iRegLNoSp dst, iRegL src, immL0 zero) %{
 6884   match(Set dst (SubL zero src));
 6885   ins_cost(ALU_COST);
 6886   format %{ "sub  $dst, x0, $src\t# long, #@negL_reg" %}
 6887 
 6888   ins_encode %{
 6889     // actually call the sub
 6890     __ neg(as_Register($dst$$reg),
 6891            as_Register($src$$reg));
 6892   %}
 6893 
 6894   ins_pipe(ialu_reg);
 6895 %}
 6896 
 6897 // Integer Multiply
 6898 
 6899 instruct mulI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
 6900   match(Set dst (MulI src1 src2));
 6901   ins_cost(IMUL_COST);
 6902   format %{ "mulw  $dst, $src1, $src2\t#@mulI" %}
 6903 
 6904   //this means 2 word multi, and no sign extend to 64 bits
 6905   ins_encode %{
 6906     // riscv64 mulw will sign-extension to high 32 bits in dst reg
 6907     __ mulw(as_Register($dst$$reg),
 6908             as_Register($src1$$reg),
 6909             as_Register($src2$$reg));
 6910   %}
 6911 
 6912   ins_pipe(imul_reg_reg);
 6913 %}
 6914 
 6915 // Long Multiply
 6916 
 6917 instruct mulL(iRegLNoSp dst, iRegL src1, iRegL src2) %{
 6918   match(Set dst (MulL src1 src2));
 6919   ins_cost(IMUL_COST);
 6920   format %{ "mul  $dst, $src1, $src2\t#@mulL" %}
 6921 
 6922   ins_encode %{
 6923     __ mul(as_Register($dst$$reg),
 6924            as_Register($src1$$reg),
 6925            as_Register($src2$$reg));
 6926   %}
 6927 
 6928   ins_pipe(lmul_reg_reg);
 6929 %}
 6930 
 6931 instruct mulHiL_rReg(iRegLNoSp dst, iRegL src1, iRegL src2)
 6932 %{
 6933   match(Set dst (MulHiL src1 src2));
 6934   ins_cost(IMUL_COST);
 6935   format %{ "mulh  $dst, $src1, $src2\t# mulhi, #@mulHiL_rReg" %}
 6936 
 6937   ins_encode %{
 6938     __ mulh(as_Register($dst$$reg),
 6939             as_Register($src1$$reg),
 6940             as_Register($src2$$reg));
 6941   %}
 6942 
 6943   ins_pipe(lmul_reg_reg);
 6944 %}
 6945 
 6946 instruct umulHiL_rReg(iRegLNoSp dst, iRegL src1, iRegL src2)
 6947 %{
 6948   match(Set dst (UMulHiL src1 src2));
 6949   ins_cost(IMUL_COST);
 6950   format %{ "mulhu  $dst, $src1, $src2\t# umulhi, #@umulHiL_rReg" %}
 6951 
 6952   ins_encode %{
 6953     __ mulhu(as_Register($dst$$reg),
 6954              as_Register($src1$$reg),
 6955              as_Register($src2$$reg));
 6956   %}
 6957 
 6958   ins_pipe(lmul_reg_reg);
 6959 %}
 6960 
 6961 // Integer Divide
 6962 
 6963 instruct divI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
 6964   match(Set dst (DivI src1 src2));
 6965   ins_cost(IDIVSI_COST);
 6966   format %{ "divw  $dst, $src1, $src2\t#@divI"%}
 6967 
 6968   ins_encode %{
 6969     __ divw(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg));
 6970   %}
 6971   ins_pipe(idiv_reg_reg);
 6972 %}
 6973 
 6974 instruct UdivI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
 6975   match(Set dst (UDivI src1 src2));
 6976   ins_cost(IDIVSI_COST);
 6977   format %{ "divuw  $dst, $src1, $src2\t#@UdivI"%}
 6978 
 6979   ins_encode %{
 6980     __ divuw(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg));
 6981   %}
 6982   ins_pipe(idiv_reg_reg);
 6983 %}
 6984 
 6985 instruct signExtract(iRegINoSp dst, iRegIorL2I src1, immI_31 div1, immI_31 div2) %{
 6986   match(Set dst (URShiftI (RShiftI src1 div1) div2));
 6987   ins_cost(ALU_COST);
 6988   format %{ "srliw $dst, $src1, $div1\t# int signExtract, #@signExtract" %}
 6989 
 6990   ins_encode %{
 6991     __ srliw(as_Register($dst$$reg), as_Register($src1$$reg), 31);
 6992   %}
 6993   ins_pipe(ialu_reg_shift);
 6994 %}
 6995 
 6996 // Long Divide
 6997 
 6998 instruct divL(iRegLNoSp dst, iRegL src1, iRegL src2) %{
 6999   match(Set dst (DivL src1 src2));
 7000   ins_cost(IDIVDI_COST);
 7001   format %{ "div  $dst, $src1, $src2\t#@divL" %}
 7002 
 7003   ins_encode %{
 7004     __ div(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg));
 7005   %}
 7006   ins_pipe(ldiv_reg_reg);
 7007 %}
 7008 
 7009 instruct UdivL(iRegLNoSp dst, iRegL src1, iRegL src2) %{
 7010   match(Set dst (UDivL src1 src2));
 7011   ins_cost(IDIVDI_COST);
 7012 
 7013   format %{ "divu $dst, $src1, $src2\t#@UdivL" %}
 7014 
 7015   ins_encode %{
 7016     __ divu(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg));
 7017   %}
 7018   ins_pipe(ldiv_reg_reg);
 7019 %}
 7020 
 7021 instruct signExtractL(iRegLNoSp dst, iRegL src1, immI_63 div1, immI_63 div2) %{
 7022   match(Set dst (URShiftL (RShiftL src1 div1) div2));
 7023   ins_cost(ALU_COST);
 7024   format %{ "srli $dst, $src1, $div1\t# long signExtract, #@signExtractL" %}
 7025 
 7026   ins_encode %{
 7027     __ srli(as_Register($dst$$reg), as_Register($src1$$reg), 63);
 7028   %}
 7029   ins_pipe(ialu_reg_shift);
 7030 %}
 7031 
 7032 // Integer Remainder
 7033 
 7034 instruct modI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
 7035   match(Set dst (ModI src1 src2));
 7036   ins_cost(IDIVSI_COST);
 7037   format %{ "remw  $dst, $src1, $src2\t#@modI" %}
 7038 
 7039   ins_encode %{
 7040     __ remw(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg));
 7041   %}
 7042   ins_pipe(ialu_reg_reg);
 7043 %}
 7044 
 7045 instruct UmodI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
 7046   match(Set dst (UModI src1 src2));
 7047   ins_cost(IDIVSI_COST);
 7048   format %{ "remuw  $dst, $src1, $src2\t#@UmodI" %}
 7049 
 7050   ins_encode %{
 7051     __ remuw(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg));
 7052   %}
 7053   ins_pipe(ialu_reg_reg);
 7054 %}
 7055 
 7056 // Long Remainder
 7057 
 7058 instruct modL(iRegLNoSp dst, iRegL src1, iRegL src2) %{
 7059   match(Set dst (ModL src1 src2));
 7060   ins_cost(IDIVDI_COST);
 7061   format %{ "rem  $dst, $src1, $src2\t#@modL" %}
 7062 
 7063   ins_encode %{
 7064     __ rem(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg));
 7065   %}
 7066   ins_pipe(ialu_reg_reg);
 7067 %}
 7068 
 7069 instruct UmodL(iRegLNoSp dst, iRegL src1, iRegL src2) %{
 7070   match(Set dst (UModL src1 src2));
 7071   ins_cost(IDIVDI_COST);
 7072   format %{ "remu  $dst, $src1, $src2\t#@UmodL" %}
 7073 
 7074   ins_encode %{
 7075     __ remu(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg));
 7076   %}
 7077   ins_pipe(ialu_reg_reg);
 7078 %}
 7079 
 7080 // Integer Shifts
 7081 
 7082 // Shift Left Register
 7083 // Only the low 5 bits of src2 are considered for the shift amount, all other bits are ignored.
 7084 instruct lShiftI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
 7085   match(Set dst (LShiftI src1 src2));
 7086   ins_cost(ALU_COST);
 7087   format %{ "sllw  $dst, $src1, $src2\t#@lShiftI_reg_reg" %}
 7088 
 7089   ins_encode %{
 7090     __ sllw(as_Register($dst$$reg),
 7091             as_Register($src1$$reg),
 7092             as_Register($src2$$reg));
 7093   %}
 7094 
 7095   ins_pipe(ialu_reg_reg_vshift);
 7096 %}
 7097 
 7098 // Shift Left Immediate
 7099 instruct lShiftI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immI src2) %{
 7100   match(Set dst (LShiftI src1 src2));
 7101   ins_cost(ALU_COST);
 7102   format %{ "slliw  $dst, $src1, ($src2 & 0x1f)\t#@lShiftI_reg_imm" %}
 7103 
 7104   ins_encode %{
 7105     // the shift amount is encoded in the lower
 7106     // 5 bits of the I-immediate field for RV32I
 7107     __ slliw(as_Register($dst$$reg),
 7108              as_Register($src1$$reg),
 7109              (unsigned) $src2$$constant & 0x1f);
 7110   %}
 7111 
 7112   ins_pipe(ialu_reg_shift);
 7113 %}
 7114 
 7115 // Shift Right Logical Register
 7116 // Only the low 5 bits of src2 are considered for the shift amount, all other bits are ignored.
 7117 instruct urShiftI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
 7118   match(Set dst (URShiftI src1 src2));
 7119   ins_cost(ALU_COST);
 7120   format %{ "srlw  $dst, $src1, $src2\t#@urShiftI_reg_reg" %}
 7121 
 7122   ins_encode %{
 7123     __ srlw(as_Register($dst$$reg),
 7124             as_Register($src1$$reg),
 7125             as_Register($src2$$reg));
 7126   %}
 7127 
 7128   ins_pipe(ialu_reg_reg_vshift);
 7129 %}
 7130 
 7131 // Shift Right Logical Immediate
 7132 instruct urShiftI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immI src2) %{
 7133   match(Set dst (URShiftI src1 src2));
 7134   ins_cost(ALU_COST);
 7135   format %{ "srliw  $dst, $src1, ($src2 & 0x1f)\t#@urShiftI_reg_imm" %}
 7136 
 7137   ins_encode %{
 7138     // the shift amount is encoded in the lower
 7139     // 6 bits of the I-immediate field for RV64I
 7140     __ srliw(as_Register($dst$$reg),
 7141              as_Register($src1$$reg),
 7142              (unsigned) $src2$$constant & 0x1f);
 7143   %}
 7144 
 7145   ins_pipe(ialu_reg_shift);
 7146 %}
 7147 
 7148 // Shift Right Arithmetic Register
 7149 // Only the low 5 bits of src2 are considered for the shift amount, all other bits are ignored.
 7150 instruct rShiftI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
 7151   match(Set dst (RShiftI src1 src2));
 7152   ins_cost(ALU_COST);
 7153   format %{ "sraw  $dst, $src1, $src2\t#@rShiftI_reg_reg" %}
 7154 
 7155   ins_encode %{
 7156     // riscv will sign-ext dst high 32 bits
 7157     __ sraw(as_Register($dst$$reg),
 7158             as_Register($src1$$reg),
 7159             as_Register($src2$$reg));
 7160   %}
 7161 
 7162   ins_pipe(ialu_reg_reg_vshift);
 7163 %}
 7164 
 7165 // Shift Right Arithmetic Immediate
 7166 instruct rShiftI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immI src2) %{
 7167   match(Set dst (RShiftI src1 src2));
 7168   ins_cost(ALU_COST);
 7169   format %{ "sraiw  $dst, $src1, ($src2 & 0x1f)\t#@rShiftI_reg_imm" %}
 7170 
 7171   ins_encode %{
 7172     // riscv will sign-ext dst high 32 bits
 7173     __ sraiw(as_Register($dst$$reg),
 7174              as_Register($src1$$reg),
 7175              (unsigned) $src2$$constant & 0x1f);
 7176   %}
 7177 
 7178   ins_pipe(ialu_reg_shift);
 7179 %}
 7180 
 7181 // Long Shifts
 7182 
 7183 // Shift Left Register
 7184 // Only the low 6 bits of src2 are considered for the shift amount, all other bits are ignored.
 7185 instruct lShiftL_reg_reg(iRegLNoSp dst, iRegL src1, iRegIorL2I src2) %{
 7186   match(Set dst (LShiftL src1 src2));
 7187 
 7188   ins_cost(ALU_COST);
 7189   format %{ "sll  $dst, $src1, $src2\t#@lShiftL_reg_reg" %}
 7190 
 7191   ins_encode %{
 7192     __ sll(as_Register($dst$$reg),
 7193            as_Register($src1$$reg),
 7194            as_Register($src2$$reg));
 7195   %}
 7196 
 7197   ins_pipe(ialu_reg_reg_vshift);
 7198 %}
 7199 
 7200 // Shift Left Immediate
 7201 instruct lShiftL_reg_imm(iRegLNoSp dst, iRegL src1, immI src2) %{
 7202   match(Set dst (LShiftL src1 src2));
 7203 
 7204   ins_cost(ALU_COST);
 7205   format %{ "slli  $dst, $src1, ($src2 & 0x3f)\t#@lShiftL_reg_imm" %}
 7206 
 7207   ins_encode %{
 7208     // the shift amount is encoded in the lower
 7209     // 6 bits of the I-immediate field for RV64I
 7210     __ slli(as_Register($dst$$reg),
 7211             as_Register($src1$$reg),
 7212             (unsigned) $src2$$constant & 0x3f);
 7213   %}
 7214 
 7215   ins_pipe(ialu_reg_shift);
 7216 %}
 7217 
 7218 // Shift Right Logical Register
 7219 // Only the low 6 bits of src2 are considered for the shift amount, all other bits are ignored.
 7220 instruct urShiftL_reg_reg(iRegLNoSp dst, iRegL src1, iRegIorL2I src2) %{
 7221   match(Set dst (URShiftL src1 src2));
 7222 
 7223   ins_cost(ALU_COST);
 7224   format %{ "srl  $dst, $src1, $src2\t#@urShiftL_reg_reg" %}
 7225 
 7226   ins_encode %{
 7227     __ srl(as_Register($dst$$reg),
 7228             as_Register($src1$$reg),
 7229             as_Register($src2$$reg));
 7230   %}
 7231 
 7232   ins_pipe(ialu_reg_reg_vshift);
 7233 %}
 7234 
 7235 // Shift Right Logical Immediate
 7236 instruct urShiftL_reg_imm(iRegLNoSp dst, iRegL src1, immI src2) %{
 7237   match(Set dst (URShiftL src1 src2));
 7238 
 7239   ins_cost(ALU_COST);
 7240   format %{ "srli  $dst, $src1, ($src2 & 0x3f)\t#@urShiftL_reg_imm" %}
 7241 
 7242   ins_encode %{
 7243     // the shift amount is encoded in the lower
 7244     // 6 bits of the I-immediate field for RV64I
 7245     __ srli(as_Register($dst$$reg),
 7246             as_Register($src1$$reg),
 7247             (unsigned) $src2$$constant & 0x3f);
 7248   %}
 7249 
 7250   ins_pipe(ialu_reg_shift);
 7251 %}
 7252 
 7253 // A special-case pattern for card table stores.
 7254 instruct urShiftP_reg_imm(iRegLNoSp dst, iRegP src1, immI src2) %{
 7255   match(Set dst (URShiftL (CastP2X src1) src2));
 7256 
 7257   ins_cost(ALU_COST);
 7258   format %{ "srli  $dst, p2x($src1), ($src2 & 0x3f)\t#@urShiftP_reg_imm" %}
 7259 
 7260   ins_encode %{
 7261     // the shift amount is encoded in the lower
 7262     // 6 bits of the I-immediate field for RV64I
 7263     __ srli(as_Register($dst$$reg),
 7264             as_Register($src1$$reg),
 7265             (unsigned) $src2$$constant & 0x3f);
 7266   %}
 7267 
 7268   ins_pipe(ialu_reg_shift);
 7269 %}
 7270 
 7271 // Shift Right Arithmetic Register
 7272 // Only the low 6 bits of src2 are considered for the shift amount, all other bits are ignored.
 7273 instruct rShiftL_reg_reg(iRegLNoSp dst, iRegL src1, iRegIorL2I src2) %{
 7274   match(Set dst (RShiftL src1 src2));
 7275 
 7276   ins_cost(ALU_COST);
 7277   format %{ "sra  $dst, $src1, $src2\t#@rShiftL_reg_reg" %}
 7278 
 7279   ins_encode %{
 7280     __ sra(as_Register($dst$$reg),
 7281            as_Register($src1$$reg),
 7282            as_Register($src2$$reg));
 7283   %}
 7284 
 7285   ins_pipe(ialu_reg_reg_vshift);
 7286 %}
 7287 
 7288 // Shift Right Arithmetic Immediate
 7289 instruct rShiftL_reg_imm(iRegLNoSp dst, iRegL src1, immI src2) %{
 7290   match(Set dst (RShiftL src1 src2));
 7291 
 7292   ins_cost(ALU_COST);
 7293   format %{ "srai  $dst, $src1, ($src2 & 0x3f)\t#@rShiftL_reg_imm" %}
 7294 
 7295   ins_encode %{
 7296     // the shift amount is encoded in the lower
 7297     // 6 bits of the I-immediate field for RV64I
 7298     __ srai(as_Register($dst$$reg),
 7299             as_Register($src1$$reg),
 7300             (unsigned) $src2$$constant & 0x3f);
 7301   %}
 7302 
 7303   ins_pipe(ialu_reg_shift);
 7304 %}
 7305 
 7306 instruct regI_not_reg(iRegINoSp dst, iRegI src1, immI_M1 m1) %{
 7307   match(Set dst (XorI src1 m1));
 7308   ins_cost(ALU_COST);
 7309   format %{ "xori  $dst, $src1, -1\t#@regI_not_reg" %}
 7310 
 7311   ins_encode %{
 7312     __ xori(as_Register($dst$$reg), as_Register($src1$$reg), -1);
 7313   %}
 7314 
 7315   ins_pipe(ialu_reg_imm);
 7316 %}
 7317 
 7318 instruct regL_not_reg(iRegLNoSp dst, iRegL src1, immL_M1 m1) %{
 7319   match(Set dst (XorL src1 m1));
 7320   ins_cost(ALU_COST);
 7321   format %{ "xori  $dst, $src1, -1\t#@regL_not_reg" %}
 7322 
 7323   ins_encode %{
 7324     __ xori(as_Register($dst$$reg), as_Register($src1$$reg), -1);
 7325   %}
 7326 
 7327   ins_pipe(ialu_reg_imm);
 7328 %}
 7329 
 7330 
 7331 // ============================================================================
 7332 // Floating Point Arithmetic Instructions
 7333 
 7334 instruct addF_reg_reg(fRegF dst, fRegF src1, fRegF src2) %{
 7335   match(Set dst (AddF src1 src2));
 7336 
 7337   ins_cost(DEFAULT_COST * 5);
 7338   format %{ "fadd.s  $dst, $src1, $src2\t#@addF_reg_reg" %}
 7339 
 7340   ins_encode %{
 7341     __ fadd_s(as_FloatRegister($dst$$reg),
 7342               as_FloatRegister($src1$$reg),
 7343               as_FloatRegister($src2$$reg));
 7344   %}
 7345 
 7346   ins_pipe(fp_dop_reg_reg_s);
 7347 %}
 7348 
 7349 instruct addD_reg_reg(fRegD dst, fRegD src1, fRegD src2) %{
 7350   match(Set dst (AddD src1 src2));
 7351 
 7352   ins_cost(DEFAULT_COST * 5);
 7353   format %{ "fadd.d  $dst, $src1, $src2\t#@addD_reg_reg" %}
 7354 
 7355   ins_encode %{
 7356     __ fadd_d(as_FloatRegister($dst$$reg),
 7357               as_FloatRegister($src1$$reg),
 7358               as_FloatRegister($src2$$reg));
 7359   %}
 7360 
 7361   ins_pipe(fp_dop_reg_reg_d);
 7362 %}
 7363 
 7364 instruct subF_reg_reg(fRegF dst, fRegF src1, fRegF src2) %{
 7365   match(Set dst (SubF src1 src2));
 7366 
 7367   ins_cost(DEFAULT_COST * 5);
 7368   format %{ "fsub.s  $dst, $src1, $src2\t#@subF_reg_reg" %}
 7369 
 7370   ins_encode %{
 7371     __ fsub_s(as_FloatRegister($dst$$reg),
 7372               as_FloatRegister($src1$$reg),
 7373               as_FloatRegister($src2$$reg));
 7374   %}
 7375 
 7376   ins_pipe(fp_dop_reg_reg_s);
 7377 %}
 7378 
 7379 instruct subD_reg_reg(fRegD dst, fRegD src1, fRegD src2) %{
 7380   match(Set dst (SubD src1 src2));
 7381 
 7382   ins_cost(DEFAULT_COST * 5);
 7383   format %{ "fsub.d  $dst, $src1, $src2\t#@subD_reg_reg" %}
 7384 
 7385   ins_encode %{
 7386     __ fsub_d(as_FloatRegister($dst$$reg),
 7387               as_FloatRegister($src1$$reg),
 7388               as_FloatRegister($src2$$reg));
 7389   %}
 7390 
 7391   ins_pipe(fp_dop_reg_reg_d);
 7392 %}
 7393 
 7394 instruct mulF_reg_reg(fRegF dst, fRegF src1, fRegF src2) %{
 7395   match(Set dst (MulF src1 src2));
 7396 
 7397   ins_cost(FMUL_SINGLE_COST);
 7398   format %{ "fmul.s  $dst, $src1, $src2\t#@mulF_reg_reg" %}
 7399 
 7400   ins_encode %{
 7401     __ fmul_s(as_FloatRegister($dst$$reg),
 7402               as_FloatRegister($src1$$reg),
 7403               as_FloatRegister($src2$$reg));
 7404   %}
 7405 
 7406   ins_pipe(fp_dop_reg_reg_s);
 7407 %}
 7408 
 7409 instruct mulD_reg_reg(fRegD dst, fRegD src1, fRegD src2) %{
 7410   match(Set dst (MulD src1 src2));
 7411 
 7412   ins_cost(FMUL_DOUBLE_COST);
 7413   format %{ "fmul.d  $dst, $src1, $src2\t#@mulD_reg_reg" %}
 7414 
 7415   ins_encode %{
 7416     __ fmul_d(as_FloatRegister($dst$$reg),
 7417               as_FloatRegister($src1$$reg),
 7418               as_FloatRegister($src2$$reg));
 7419   %}
 7420 
 7421   ins_pipe(fp_dop_reg_reg_d);
 7422 %}
 7423 
 7424 // src1 * src2 + src3
 7425 instruct maddF_reg_reg(fRegF dst, fRegF src1, fRegF src2, fRegF src3) %{
 7426   match(Set dst (FmaF src3 (Binary src1 src2)));
 7427 
 7428   ins_cost(FMUL_SINGLE_COST);
 7429   format %{ "fmadd.s  $dst, $src1, $src2, $src3\t#@maddF_reg_reg" %}
 7430 
 7431   ins_encode %{
 7432     assert(UseFMA, "Needs FMA instructions support.");
 7433     __ fmadd_s(as_FloatRegister($dst$$reg),
 7434                as_FloatRegister($src1$$reg),
 7435                as_FloatRegister($src2$$reg),
 7436                as_FloatRegister($src3$$reg));
 7437   %}
 7438 
 7439   ins_pipe(pipe_class_default);
 7440 %}
 7441 
 7442 // src1 * src2 + src3
 7443 instruct maddD_reg_reg(fRegD dst, fRegD src1, fRegD src2, fRegD src3) %{
 7444   match(Set dst (FmaD src3 (Binary src1 src2)));
 7445 
 7446   ins_cost(FMUL_DOUBLE_COST);
 7447   format %{ "fmadd.d  $dst, $src1, $src2, $src3\t#@maddD_reg_reg" %}
 7448 
 7449   ins_encode %{
 7450     assert(UseFMA, "Needs FMA instructions support.");
 7451     __ fmadd_d(as_FloatRegister($dst$$reg),
 7452                as_FloatRegister($src1$$reg),
 7453                as_FloatRegister($src2$$reg),
 7454                as_FloatRegister($src3$$reg));
 7455   %}
 7456 
 7457   ins_pipe(pipe_class_default);
 7458 %}
 7459 
 7460 // src1 * src2 - src3
 7461 instruct msubF_reg_reg(fRegF dst, fRegF src1, fRegF src2, fRegF src3) %{
 7462   match(Set dst (FmaF (NegF src3) (Binary src1 src2)));
 7463 
 7464   ins_cost(FMUL_SINGLE_COST);
 7465   format %{ "fmsub.s  $dst, $src1, $src2, $src3\t#@msubF_reg_reg" %}
 7466 
 7467   ins_encode %{
 7468     assert(UseFMA, "Needs FMA instructions support.");
 7469     __ fmsub_s(as_FloatRegister($dst$$reg),
 7470                as_FloatRegister($src1$$reg),
 7471                as_FloatRegister($src2$$reg),
 7472                as_FloatRegister($src3$$reg));
 7473   %}
 7474 
 7475   ins_pipe(pipe_class_default);
 7476 %}
 7477 
 7478 // src1 * src2 - src3
 7479 instruct msubD_reg_reg(fRegD dst, fRegD src1, fRegD src2, fRegD src3) %{
 7480   match(Set dst (FmaD (NegD src3) (Binary src1 src2)));
 7481 
 7482   ins_cost(FMUL_DOUBLE_COST);
 7483   format %{ "fmsub.d  $dst, $src1, $src2, $src3\t#@msubD_reg_reg" %}
 7484 
 7485   ins_encode %{
 7486     assert(UseFMA, "Needs FMA instructions support.");
 7487     __ fmsub_d(as_FloatRegister($dst$$reg),
 7488                as_FloatRegister($src1$$reg),
 7489                as_FloatRegister($src2$$reg),
 7490                as_FloatRegister($src3$$reg));
 7491   %}
 7492 
 7493   ins_pipe(pipe_class_default);
 7494 %}
 7495 
 7496 // src1 * (-src2) + src3
 7497 // "(-src1) * src2 + src3" has been idealized to "src2 * (-src1) + src3"
 7498 instruct nmsubF_reg_reg(fRegF dst, fRegF src1, fRegF src2, fRegF src3) %{
 7499   match(Set dst (FmaF src3 (Binary src1 (NegF src2))));
 7500 
 7501   ins_cost(FMUL_SINGLE_COST);
 7502   format %{ "fnmsub.s  $dst, $src1, $src2, $src3\t#@nmsubF_reg_reg" %}
 7503 
 7504   ins_encode %{
 7505     assert(UseFMA, "Needs FMA instructions support.");
 7506     __ fnmsub_s(as_FloatRegister($dst$$reg),
 7507                 as_FloatRegister($src1$$reg),
 7508                 as_FloatRegister($src2$$reg),
 7509                 as_FloatRegister($src3$$reg));
 7510   %}
 7511 
 7512   ins_pipe(pipe_class_default);
 7513 %}
 7514 
 7515 // src1 * (-src2) + src3
 7516 // "(-src1) * src2 + src3" has been idealized to "src2 * (-src1) + src3"
 7517 instruct nmsubD_reg_reg(fRegD dst, fRegD src1, fRegD src2, fRegD src3) %{
 7518   match(Set dst (FmaD src3 (Binary src1 (NegD src2))));
 7519 
 7520   ins_cost(FMUL_DOUBLE_COST);
 7521   format %{ "fnmsub.d  $dst, $src1, $src2, $src3\t#@nmsubD_reg_reg" %}
 7522 
 7523   ins_encode %{
 7524     assert(UseFMA, "Needs FMA instructions support.");
 7525     __ fnmsub_d(as_FloatRegister($dst$$reg),
 7526                 as_FloatRegister($src1$$reg),
 7527                 as_FloatRegister($src2$$reg),
 7528                 as_FloatRegister($src3$$reg));
 7529   %}
 7530 
 7531   ins_pipe(pipe_class_default);
 7532 %}
 7533 
 7534 // src1 * (-src2) - src3
 7535 // "(-src1) * src2 - src3" has been idealized to "src2 * (-src1) - src3"
 7536 instruct nmaddF_reg_reg(fRegF dst, fRegF src1, fRegF src2, fRegF src3) %{
 7537   match(Set dst (FmaF (NegF src3) (Binary src1 (NegF src2))));
 7538 
 7539   ins_cost(FMUL_SINGLE_COST);
 7540   format %{ "fnmadd.s  $dst, $src1, $src2, $src3\t#@nmaddF_reg_reg" %}
 7541 
 7542   ins_encode %{
 7543     assert(UseFMA, "Needs FMA instructions support.");
 7544     __ fnmadd_s(as_FloatRegister($dst$$reg),
 7545                 as_FloatRegister($src1$$reg),
 7546                 as_FloatRegister($src2$$reg),
 7547                 as_FloatRegister($src3$$reg));
 7548   %}
 7549 
 7550   ins_pipe(pipe_class_default);
 7551 %}
 7552 
 7553 // src1 * (-src2) - src3
 7554 // "(-src1) * src2 - src3" has been idealized to "src2 * (-src1) - src3"
 7555 instruct nmaddD_reg_reg(fRegD dst, fRegD src1, fRegD src2, fRegD src3) %{
 7556   match(Set dst (FmaD (NegD src3) (Binary src1 (NegD src2))));
 7557 
 7558   ins_cost(FMUL_DOUBLE_COST);
 7559   format %{ "fnmadd.d  $dst, $src1, $src2, $src3\t#@nmaddD_reg_reg" %}
 7560 
 7561   ins_encode %{
 7562     assert(UseFMA, "Needs FMA instructions support.");
 7563     __ fnmadd_d(as_FloatRegister($dst$$reg),
 7564                 as_FloatRegister($src1$$reg),
 7565                 as_FloatRegister($src2$$reg),
 7566                 as_FloatRegister($src3$$reg));
 7567   %}
 7568 
 7569   ins_pipe(pipe_class_default);
 7570 %}
 7571 
 7572 // Math.max(FF)F
 7573 instruct maxF_reg_reg(fRegF dst, fRegF src1, fRegF src2, rFlagsReg cr) %{
 7574   predicate(!UseZfa);
 7575   match(Set dst (MaxF src1 src2));
 7576   effect(KILL cr);
 7577 
 7578   format %{ "maxF $dst, $src1, $src2" %}
 7579 
 7580   ins_encode %{
 7581     __ minmax_fp(as_FloatRegister($dst$$reg),
 7582                  as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg),
 7583                  __ FLOAT_TYPE::single_precision, false /* is_min */);
 7584   %}
 7585 
 7586   ins_pipe(pipe_class_default);
 7587 %}
 7588 
 7589 instruct maxF_reg_reg_zfa(fRegF dst, fRegF src1, fRegF src2) %{
 7590   predicate(UseZfa);
 7591   match(Set dst (MaxF src1 src2));
 7592 
 7593   format %{ "maxF $dst, $src1, $src2" %}
 7594 
 7595   ins_encode %{
 7596     __ fmaxm_s(as_FloatRegister($dst$$reg),
 7597                as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
 7598   %}
 7599 
 7600   ins_pipe(pipe_class_default);
 7601 %}
 7602 
 7603 // Math.min(FF)F
 7604 instruct minF_reg_reg(fRegF dst, fRegF src1, fRegF src2, rFlagsReg cr) %{
 7605   predicate(!UseZfa);
 7606   match(Set dst (MinF src1 src2));
 7607   effect(KILL cr);
 7608 
 7609   format %{ "minF $dst, $src1, $src2" %}
 7610 
 7611   ins_encode %{
 7612     __ minmax_fp(as_FloatRegister($dst$$reg),
 7613                  as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg),
 7614                  __ FLOAT_TYPE::single_precision, true /* is_min */);
 7615   %}
 7616 
 7617   ins_pipe(pipe_class_default);
 7618 %}
 7619 
 7620 instruct minF_reg_reg_zfa(fRegF dst, fRegF src1, fRegF src2) %{
 7621   predicate(UseZfa);
 7622   match(Set dst (MinF src1 src2));
 7623 
 7624   format %{ "minF $dst, $src1, $src2" %}
 7625 
 7626   ins_encode %{
 7627     __ fminm_s(as_FloatRegister($dst$$reg),
 7628                as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
 7629   %}
 7630 
 7631   ins_pipe(pipe_class_default);
 7632 %}
 7633 
 7634 // Math.max(DD)D
 7635 instruct maxD_reg_reg(fRegD dst, fRegD src1, fRegD src2, rFlagsReg cr) %{
 7636   predicate(!UseZfa);
 7637   match(Set dst (MaxD src1 src2));
 7638   effect(KILL cr);
 7639 
 7640   format %{ "maxD $dst, $src1, $src2" %}
 7641 
 7642   ins_encode %{
 7643     __ minmax_fp(as_FloatRegister($dst$$reg),
 7644                  as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg),
 7645                  __ FLOAT_TYPE::double_precision, false /* is_min */);
 7646   %}
 7647 
 7648   ins_pipe(pipe_class_default);
 7649 %}
 7650 
 7651 instruct maxD_reg_reg_zfa(fRegD dst, fRegD src1, fRegD src2) %{
 7652   predicate(UseZfa);
 7653   match(Set dst (MaxD src1 src2));
 7654 
 7655   format %{ "maxD $dst, $src1, $src2" %}
 7656 
 7657   ins_encode %{
 7658     __ fmaxm_d(as_FloatRegister($dst$$reg),
 7659                as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
 7660   %}
 7661 
 7662   ins_pipe(pipe_class_default);
 7663 %}
 7664 
 7665 // Math.min(DD)D
 7666 instruct minD_reg_reg(fRegD dst, fRegD src1, fRegD src2, rFlagsReg cr) %{
 7667   predicate(!UseZfa);
 7668   match(Set dst (MinD src1 src2));
 7669   effect(KILL cr);
 7670 
 7671   format %{ "minD $dst, $src1, $src2" %}
 7672 
 7673   ins_encode %{
 7674     __ minmax_fp(as_FloatRegister($dst$$reg),
 7675                  as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg),
 7676                  __ FLOAT_TYPE::double_precision, true /* is_min */);
 7677   %}
 7678 
 7679   ins_pipe(pipe_class_default);
 7680 %}
 7681 
 7682 instruct minD_reg_reg_zfa(fRegD dst, fRegD src1, fRegD src2) %{
 7683   predicate(UseZfa);
 7684   match(Set dst (MinD src1 src2));
 7685 
 7686   format %{ "minD $dst, $src1, $src2" %}
 7687 
 7688   ins_encode %{
 7689     __ fminm_d(as_FloatRegister($dst$$reg),
 7690                as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
 7691   %}
 7692 
 7693   ins_pipe(pipe_class_default);
 7694 %}
 7695 
 7696 // Float.isInfinite
 7697 instruct isInfiniteF_reg_reg(iRegINoSp dst, fRegF src)
 7698 %{
 7699   match(Set dst (IsInfiniteF src));
 7700 
 7701   format %{ "isInfinite $dst, $src" %}
 7702   ins_encode %{
 7703     __ fclass_s(as_Register($dst$$reg), as_FloatRegister($src$$reg));
 7704     __ andi(as_Register($dst$$reg), as_Register($dst$$reg), Assembler::FClassBits::inf);
 7705     __ slt(as_Register($dst$$reg), zr, as_Register($dst$$reg));
 7706   %}
 7707 
 7708   ins_pipe(pipe_class_default);
 7709 %}
 7710 
 7711 // Double.isInfinite
 7712 instruct isInfiniteD_reg_reg(iRegINoSp dst, fRegD src)
 7713 %{
 7714   match(Set dst (IsInfiniteD src));
 7715 
 7716   format %{ "isInfinite $dst, $src" %}
 7717   ins_encode %{
 7718     __ fclass_d(as_Register($dst$$reg), as_FloatRegister($src$$reg));
 7719     __ andi(as_Register($dst$$reg), as_Register($dst$$reg), Assembler::FClassBits::inf);
 7720     __ slt(as_Register($dst$$reg), zr, as_Register($dst$$reg));
 7721   %}
 7722 
 7723   ins_pipe(pipe_class_default);
 7724 %}
 7725 
 7726 // Float.isFinite
 7727 instruct isFiniteF_reg_reg(iRegINoSp dst, fRegF src)
 7728 %{
 7729   match(Set dst (IsFiniteF src));
 7730 
 7731   format %{ "isFinite $dst, $src" %}
 7732   ins_encode %{
 7733     __ fclass_s(as_Register($dst$$reg), as_FloatRegister($src$$reg));
 7734     __ andi(as_Register($dst$$reg), as_Register($dst$$reg), Assembler::FClassBits::finite);
 7735     __ slt(as_Register($dst$$reg), zr, as_Register($dst$$reg));
 7736   %}
 7737 
 7738   ins_pipe(pipe_class_default);
 7739 %}
 7740 
 7741 // Double.isFinite
 7742 instruct isFiniteD_reg_reg(iRegINoSp dst, fRegD src)
 7743 %{
 7744   match(Set dst (IsFiniteD src));
 7745 
 7746   format %{ "isFinite $dst, $src" %}
 7747   ins_encode %{
 7748     __ fclass_d(as_Register($dst$$reg), as_FloatRegister($src$$reg));
 7749     __ andi(as_Register($dst$$reg), as_Register($dst$$reg), Assembler::FClassBits::finite);
 7750     __ slt(as_Register($dst$$reg), zr, as_Register($dst$$reg));
 7751   %}
 7752 
 7753   ins_pipe(pipe_class_default);
 7754 %}
 7755 
 7756 instruct divF_reg_reg(fRegF dst, fRegF src1, fRegF src2) %{
 7757   match(Set dst (DivF src1  src2));
 7758 
 7759   ins_cost(FDIV_COST);
 7760   format %{ "fdiv.s  $dst, $src1, $src2\t#@divF_reg_reg" %}
 7761 
 7762   ins_encode %{
 7763     __ fdiv_s(as_FloatRegister($dst$$reg),
 7764               as_FloatRegister($src1$$reg),
 7765               as_FloatRegister($src2$$reg));
 7766   %}
 7767 
 7768   ins_pipe(fp_div_s);
 7769 %}
 7770 
 7771 instruct divD_reg_reg(fRegD dst, fRegD src1, fRegD src2) %{
 7772   match(Set dst (DivD src1  src2));
 7773 
 7774   ins_cost(FDIV_COST);
 7775   format %{ "fdiv.d  $dst, $src1, $src2\t#@divD_reg_reg" %}
 7776 
 7777   ins_encode %{
 7778     __ fdiv_d(as_FloatRegister($dst$$reg),
 7779               as_FloatRegister($src1$$reg),
 7780               as_FloatRegister($src2$$reg));
 7781   %}
 7782 
 7783   ins_pipe(fp_div_d);
 7784 %}
 7785 
 7786 instruct negF_reg_reg(fRegF dst, fRegF src) %{
 7787   match(Set dst (NegF src));
 7788 
 7789   ins_cost(XFER_COST);
 7790   format %{ "fsgnjn.s  $dst, $src, $src\t#@negF_reg_reg" %}
 7791 
 7792   ins_encode %{
 7793     __ fneg_s(as_FloatRegister($dst$$reg),
 7794               as_FloatRegister($src$$reg));
 7795   %}
 7796 
 7797   ins_pipe(fp_uop_s);
 7798 %}
 7799 
 7800 instruct negD_reg_reg(fRegD dst, fRegD src) %{
 7801   match(Set dst (NegD src));
 7802 
 7803   ins_cost(XFER_COST);
 7804   format %{ "fsgnjn.d  $dst, $src, $src\t#@negD_reg_reg" %}
 7805 
 7806   ins_encode %{
 7807     __ fneg_d(as_FloatRegister($dst$$reg),
 7808               as_FloatRegister($src$$reg));
 7809   %}
 7810 
 7811   ins_pipe(fp_uop_d);
 7812 %}
 7813 
 7814 instruct absI_reg(iRegINoSp dst, iRegIorL2I src) %{
 7815   match(Set dst (AbsI src));
 7816 
 7817   ins_cost(ALU_COST * 3);
 7818   format %{
 7819     "sraiw  t0, $src, 0x1f\n\t"
 7820     "addw  $dst, $src, t0\n\t"
 7821     "xorr  $dst, $dst, t0\t#@absI_reg"
 7822   %}
 7823 
 7824   ins_encode %{
 7825     __ sraiw(t0, as_Register($src$$reg), 0x1f);
 7826     __ addw(as_Register($dst$$reg), as_Register($src$$reg), t0);
 7827     __ xorr(as_Register($dst$$reg), as_Register($dst$$reg), t0);
 7828   %}
 7829 
 7830   ins_pipe(pipe_class_default);
 7831 %}
 7832 
 7833 instruct absL_reg(iRegLNoSp dst, iRegL src) %{
 7834   match(Set dst (AbsL src));
 7835 
 7836   ins_cost(ALU_COST * 3);
 7837   format %{
 7838     "srai  t0, $src, 0x3f\n\t"
 7839     "add  $dst, $src, t0\n\t"
 7840     "xorr  $dst, $dst, t0\t#@absL_reg"
 7841   %}
 7842 
 7843   ins_encode %{
 7844     __ srai(t0, as_Register($src$$reg), 0x3f);
 7845     __ add(as_Register($dst$$reg), as_Register($src$$reg), t0);
 7846     __ xorr(as_Register($dst$$reg), as_Register($dst$$reg), t0);
 7847   %}
 7848 
 7849   ins_pipe(pipe_class_default);
 7850 %}
 7851 
 7852 instruct absF_reg(fRegF dst, fRegF src) %{
 7853   match(Set dst (AbsF src));
 7854 
 7855   ins_cost(XFER_COST);
 7856   format %{ "fsgnjx.s  $dst, $src, $src\t#@absF_reg" %}
 7857   ins_encode %{
 7858     __ fabs_s(as_FloatRegister($dst$$reg),
 7859               as_FloatRegister($src$$reg));
 7860   %}
 7861 
 7862   ins_pipe(fp_uop_s);
 7863 %}
 7864 
 7865 instruct absD_reg(fRegD dst, fRegD src) %{
 7866   match(Set dst (AbsD src));
 7867 
 7868   ins_cost(XFER_COST);
 7869   format %{ "fsgnjx.d  $dst, $src, $src\t#@absD_reg" %}
 7870   ins_encode %{
 7871     __ fabs_d(as_FloatRegister($dst$$reg),
 7872               as_FloatRegister($src$$reg));
 7873   %}
 7874 
 7875   ins_pipe(fp_uop_d);
 7876 %}
 7877 
 7878 instruct sqrtF_reg(fRegF dst, fRegF src) %{
 7879   match(Set dst (SqrtF src));
 7880 
 7881   ins_cost(FSQRT_COST);
 7882   format %{ "fsqrt.s  $dst, $src\t#@sqrtF_reg" %}
 7883   ins_encode %{
 7884     __ fsqrt_s(as_FloatRegister($dst$$reg),
 7885                as_FloatRegister($src$$reg));
 7886   %}
 7887 
 7888   ins_pipe(fp_sqrt_s);
 7889 %}
 7890 
 7891 instruct sqrtD_reg(fRegD dst, fRegD src) %{
 7892   match(Set dst (SqrtD src));
 7893 
 7894   ins_cost(FSQRT_COST);
 7895   format %{ "fsqrt.d  $dst, $src\t#@sqrtD_reg" %}
 7896   ins_encode %{
 7897     __ fsqrt_d(as_FloatRegister($dst$$reg),
 7898                as_FloatRegister($src$$reg));
 7899   %}
 7900 
 7901   ins_pipe(fp_sqrt_d);
 7902 %}
 7903 
 7904 // Round Instruction
 7905 instruct roundD_reg(fRegD dst, fRegD src, immI rmode, iRegLNoSp tmp1, iRegLNoSp tmp2, iRegLNoSp tmp3) %{
 7906   match(Set dst (RoundDoubleMode src rmode));
 7907   ins_cost(2 * XFER_COST + BRANCH_COST);
 7908   effect(TEMP_DEF dst, TEMP tmp1, TEMP tmp2, TEMP tmp3);
 7909 
 7910   format %{ "RoundDoubleMode $src, $rmode" %}
 7911   ins_encode %{
 7912     __ round_double_mode(as_FloatRegister($dst$$reg),
 7913                as_FloatRegister($src$$reg), $rmode$$constant, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
 7914   %}
 7915   ins_pipe(pipe_class_default);
 7916 %}
 7917 
 7918 // Copysign and signum intrinsics
 7919 
 7920 instruct copySignD_reg(fRegD dst, fRegD src1, fRegD src2, immD zero) %{
 7921   match(Set dst (CopySignD src1 (Binary src2 zero)));
 7922   format %{ "CopySignD  $dst $src1 $src2" %}
 7923   ins_encode %{
 7924     FloatRegister dst = as_FloatRegister($dst$$reg),
 7925                   src1 = as_FloatRegister($src1$$reg),
 7926                   src2 = as_FloatRegister($src2$$reg);
 7927     __ fsgnj_d(dst, src1, src2);
 7928   %}
 7929   ins_pipe(fp_dop_reg_reg_d);
 7930 %}
 7931 
 7932 instruct copySignF_reg(fRegF dst, fRegF src1, fRegF src2) %{
 7933   match(Set dst (CopySignF src1 src2));
 7934   format %{ "CopySignF  $dst $src1 $src2" %}
 7935   ins_encode %{
 7936     FloatRegister dst = as_FloatRegister($dst$$reg),
 7937                   src1 = as_FloatRegister($src1$$reg),
 7938                   src2 = as_FloatRegister($src2$$reg);
 7939     __ fsgnj_s(dst, src1, src2);
 7940   %}
 7941   ins_pipe(fp_dop_reg_reg_s);
 7942 %}
 7943 
 7944 instruct signumD_reg(fRegD dst, immD zero, fRegD one) %{
 7945   match(Set dst (SignumD dst (Binary zero one)));
 7946   format %{ "signumD  $dst, $dst" %}
 7947   ins_encode %{
 7948     __ signum_fp(as_FloatRegister($dst$$reg), as_FloatRegister($one$$reg), true /* is_double */);
 7949   %}
 7950   ins_pipe(pipe_class_default);
 7951 %}
 7952 
 7953 instruct signumF_reg(fRegF dst, immF zero, fRegF one) %{
 7954   match(Set dst (SignumF dst (Binary zero one)));
 7955   format %{ "signumF  $dst, $dst" %}
 7956   ins_encode %{
 7957     __ signum_fp(as_FloatRegister($dst$$reg), as_FloatRegister($one$$reg), false /* is_double */);
 7958   %}
 7959   ins_pipe(pipe_class_default);
 7960 %}
 7961 
 7962 // Arithmetic Instructions End
 7963 
 7964 // ============================================================================
 7965 // Logical Instructions
 7966 
 7967 // Register And
 7968 instruct andI_reg_reg(iRegINoSp dst, iRegI src1, iRegI src2) %{
 7969   match(Set dst (AndI src1 src2));
 7970 
 7971   format %{ "andr  $dst, $src1, $src2\t#@andI_reg_reg" %}
 7972 
 7973   ins_cost(ALU_COST);
 7974   ins_encode %{
 7975     __ andr(as_Register($dst$$reg),
 7976             as_Register($src1$$reg),
 7977             as_Register($src2$$reg));
 7978   %}
 7979 
 7980   ins_pipe(ialu_reg_reg);
 7981 %}
 7982 
 7983 // Immediate And
 7984 instruct andI_reg_imm(iRegINoSp dst, iRegI src1, immIAdd src2) %{
 7985   match(Set dst (AndI src1 src2));
 7986 
 7987   format %{ "andi  $dst, $src1, $src2\t#@andI_reg_imm" %}
 7988 
 7989   ins_cost(ALU_COST);
 7990   ins_encode %{
 7991     __ andi(as_Register($dst$$reg),
 7992             as_Register($src1$$reg),
 7993             (int32_t)($src2$$constant));
 7994   %}
 7995 
 7996   ins_pipe(ialu_reg_imm);
 7997 %}
 7998 
 7999 // Register Or
 8000 instruct orI_reg_reg(iRegINoSp dst, iRegI src1, iRegI src2) %{
 8001   match(Set dst (OrI src1 src2));
 8002 
 8003   format %{ "orr  $dst, $src1, $src2\t#@orI_reg_reg" %}
 8004 
 8005   ins_cost(ALU_COST);
 8006   ins_encode %{
 8007     __ orr(as_Register($dst$$reg),
 8008            as_Register($src1$$reg),
 8009            as_Register($src2$$reg));
 8010   %}
 8011 
 8012   ins_pipe(ialu_reg_reg);
 8013 %}
 8014 
 8015 // Immediate Or
 8016 instruct orI_reg_imm(iRegINoSp dst, iRegI src1, immIAdd src2) %{
 8017   match(Set dst (OrI src1 src2));
 8018 
 8019   format %{ "ori  $dst, $src1, $src2\t#@orI_reg_imm" %}
 8020 
 8021   ins_cost(ALU_COST);
 8022   ins_encode %{
 8023     __ ori(as_Register($dst$$reg),
 8024            as_Register($src1$$reg),
 8025            (int32_t)($src2$$constant));
 8026   %}
 8027 
 8028   ins_pipe(ialu_reg_imm);
 8029 %}
 8030 
 8031 // Register Xor
 8032 instruct xorI_reg_reg(iRegINoSp dst, iRegI src1, iRegI src2) %{
 8033   match(Set dst (XorI src1 src2));
 8034 
 8035   format %{ "xorr  $dst, $src1, $src2\t#@xorI_reg_reg" %}
 8036 
 8037   ins_cost(ALU_COST);
 8038   ins_encode %{
 8039     __ xorr(as_Register($dst$$reg),
 8040             as_Register($src1$$reg),
 8041             as_Register($src2$$reg));
 8042   %}
 8043 
 8044   ins_pipe(ialu_reg_reg);
 8045 %}
 8046 
 8047 // Immediate Xor
 8048 instruct xorI_reg_imm(iRegINoSp dst, iRegI src1, immIAdd src2) %{
 8049   match(Set dst (XorI src1 src2));
 8050 
 8051   format %{ "xori  $dst, $src1, $src2\t#@xorI_reg_imm" %}
 8052 
 8053   ins_cost(ALU_COST);
 8054   ins_encode %{
 8055     __ xori(as_Register($dst$$reg),
 8056             as_Register($src1$$reg),
 8057             (int32_t)($src2$$constant));
 8058   %}
 8059 
 8060   ins_pipe(ialu_reg_imm);
 8061 %}
 8062 
 8063 // Register And Long
 8064 instruct andL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
 8065   match(Set dst (AndL src1 src2));
 8066 
 8067   format %{ "andr  $dst, $src1, $src2\t#@andL_reg_reg" %}
 8068 
 8069   ins_cost(ALU_COST);
 8070   ins_encode %{
 8071     __ andr(as_Register($dst$$reg),
 8072             as_Register($src1$$reg),
 8073             as_Register($src2$$reg));
 8074   %}
 8075 
 8076   ins_pipe(ialu_reg_reg);
 8077 %}
 8078 
 8079 // Immediate And Long
 8080 instruct andL_reg_imm(iRegLNoSp dst, iRegL src1, immLAdd src2) %{
 8081   match(Set dst (AndL src1 src2));
 8082 
 8083   format %{ "andi  $dst, $src1, $src2\t#@andL_reg_imm" %}
 8084 
 8085   ins_cost(ALU_COST);
 8086   ins_encode %{
 8087     __ andi(as_Register($dst$$reg),
 8088             as_Register($src1$$reg),
 8089             (int32_t)($src2$$constant));
 8090   %}
 8091 
 8092   ins_pipe(ialu_reg_imm);
 8093 %}
 8094 
 8095 // Register Or Long
 8096 instruct orL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
 8097   match(Set dst (OrL src1 src2));
 8098 
 8099   format %{ "orr  $dst, $src1, $src2\t#@orL_reg_reg" %}
 8100 
 8101   ins_cost(ALU_COST);
 8102   ins_encode %{
 8103     __ orr(as_Register($dst$$reg),
 8104            as_Register($src1$$reg),
 8105            as_Register($src2$$reg));
 8106   %}
 8107 
 8108   ins_pipe(ialu_reg_reg);
 8109 %}
 8110 
 8111 // Immediate Or Long
 8112 instruct orL_reg_imm(iRegLNoSp dst, iRegL src1, immLAdd src2) %{
 8113   match(Set dst (OrL src1 src2));
 8114 
 8115   format %{ "ori  $dst, $src1, $src2\t#@orL_reg_imm" %}
 8116 
 8117   ins_cost(ALU_COST);
 8118   ins_encode %{
 8119     __ ori(as_Register($dst$$reg),
 8120            as_Register($src1$$reg),
 8121            (int32_t)($src2$$constant));
 8122   %}
 8123 
 8124   ins_pipe(ialu_reg_imm);
 8125 %}
 8126 
 8127 // Register Xor Long
 8128 instruct xorL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
 8129   match(Set dst (XorL src1 src2));
 8130 
 8131   format %{ "xorr  $dst, $src1, $src2\t#@xorL_reg_reg" %}
 8132 
 8133   ins_cost(ALU_COST);
 8134   ins_encode %{
 8135     __ xorr(as_Register($dst$$reg),
 8136             as_Register($src1$$reg),
 8137             as_Register($src2$$reg));
 8138   %}
 8139 
 8140   ins_pipe(ialu_reg_reg);
 8141 %}
 8142 
 8143 // Immediate Xor Long
 8144 instruct xorL_reg_imm(iRegLNoSp dst, iRegL src1, immLAdd src2) %{
 8145   match(Set dst (XorL src1 src2));
 8146 
 8147   ins_cost(ALU_COST);
 8148   format %{ "xori  $dst, $src1, $src2\t#@xorL_reg_imm" %}
 8149 
 8150   ins_encode %{
 8151     __ xori(as_Register($dst$$reg),
 8152             as_Register($src1$$reg),
 8153             (int32_t)($src2$$constant));
 8154   %}
 8155 
 8156   ins_pipe(ialu_reg_imm);
 8157 %}
 8158 
 8159 // ============================================================================
 8160 // MemBar Instruction
 8161 
 8162 // RVTSO
 8163 
 8164 instruct unnecessary_membar_rvtso() %{
 8165   predicate(UseZtso);
 8166   match(LoadFence);
 8167   match(StoreFence);
 8168   match(StoreStoreFence);
 8169   match(MemBarAcquire);
 8170   match(MemBarRelease);
 8171   match(MemBarStoreStore);
 8172   match(MemBarAcquireLock);
 8173   match(MemBarReleaseLock);
 8174 
 8175   ins_cost(0);
 8176 
 8177   size(0);
 8178 
 8179   format %{ "#@unnecessary_membar_rvtso elided/tso (empty encoding)" %}
 8180   ins_encode %{
 8181     __ block_comment("unnecessary_membar_rvtso");
 8182   %}
 8183   ins_pipe(real_empty);
 8184 %}
 8185 
 8186 instruct membar_volatile_rvtso() %{
 8187   predicate(UseZtso);
 8188   match(MemBarVolatile);
 8189   ins_cost(VOLATILE_REF_COST);
 8190 
 8191   format %{ "#@membar_volatile_rvtso\n\t"
 8192             "fence w, r"%}
 8193 
 8194   ins_encode %{
 8195     __ block_comment("membar_volatile_rvtso");
 8196     __ membar(MacroAssembler::StoreLoad);
 8197   %}
 8198 
 8199   ins_pipe(pipe_slow);
 8200 %}
 8201 
 8202 instruct unnecessary_membar_volatile_rvtso() %{
 8203   predicate(UseZtso && Matcher::post_store_load_barrier(n));
 8204   match(MemBarVolatile);
 8205   ins_cost(0);
 8206 
 8207   size(0);
 8208  
 8209   format %{ "#@unnecessary_membar_volatile_rvtso (unnecessary so empty encoding)" %}
 8210   ins_encode %{
 8211     __ block_comment("unnecessary_membar_volatile_rvtso");
 8212   %}
 8213   ins_pipe(real_empty);
 8214 %}
 8215 
 8216 // RVWMO
 8217 
 8218 instruct membar_aqcuire_rvwmo() %{
 8219   predicate(!UseZtso);
 8220   match(LoadFence);
 8221   match(MemBarAcquire);
 8222   ins_cost(VOLATILE_REF_COST);
 8223 
 8224   format %{ "#@membar_aqcuire_rvwmo\n\t"
 8225             "fence r, rw" %}
 8226 
 8227   ins_encode %{
 8228     __ block_comment("membar_aqcuire_rvwmo");
 8229     __ membar(MacroAssembler::LoadLoad | MacroAssembler::LoadStore);
 8230   %}
 8231   ins_pipe(pipe_serial);
 8232 %}
 8233 
 8234 instruct membar_release_rvwmo() %{
 8235   predicate(!UseZtso);
 8236   match(StoreFence);
 8237   match(MemBarRelease);
 8238   ins_cost(VOLATILE_REF_COST);
 8239 
 8240   format %{ "#@membar_release_rvwmo\n\t"
 8241             "fence rw, w" %}
 8242 
 8243   ins_encode %{
 8244     __ block_comment("membar_release_rvwmo");
 8245     __ membar(MacroAssembler::LoadStore | MacroAssembler::StoreStore);
 8246   %}
 8247   ins_pipe(pipe_serial);
 8248 %}
 8249 
 8250 instruct membar_storestore_rvwmo() %{
 8251   predicate(!UseZtso);
 8252   match(MemBarStoreStore);
 8253   match(StoreStoreFence);
 8254   ins_cost(VOLATILE_REF_COST);
 8255 
 8256   format %{ "#@membar_storestore_rvwmo\n\t"
 8257             "fence w, w" %}
 8258 
 8259   ins_encode %{
 8260     __ membar(MacroAssembler::StoreStore);
 8261   %}
 8262   ins_pipe(pipe_serial);
 8263 %}
 8264 
 8265 instruct membar_volatile_rvwmo() %{
 8266   predicate(!UseZtso);
 8267   match(MemBarVolatile);
 8268   ins_cost(VOLATILE_REF_COST);
 8269 
 8270   format %{ "#@membar_volatile_rvwmo\n\t"
 8271             "fence w, r"%}
 8272 
 8273   ins_encode %{
 8274     __ block_comment("membar_volatile_rvwmo");
 8275     __ membar(MacroAssembler::StoreLoad);
 8276   %}
 8277 
 8278   ins_pipe(pipe_serial);
 8279 %}
 8280 
 8281 instruct membar_lock_rvwmo() %{
 8282   predicate(!UseZtso);
 8283   match(MemBarAcquireLock);
 8284   match(MemBarReleaseLock);
 8285   ins_cost(0);
 8286 
 8287   format %{ "#@membar_lock_rvwmo (elided)" %}
 8288 
 8289   ins_encode %{
 8290     __ block_comment("membar_lock_rvwmo (elided)");
 8291   %}
 8292 
 8293   ins_pipe(pipe_serial);
 8294 %}
 8295 
 8296 instruct unnecessary_membar_volatile_rvwmo() %{
 8297   predicate(!UseZtso && Matcher::post_store_load_barrier(n));
 8298   match(MemBarVolatile);
 8299   ins_cost(0);
 8300 
 8301   size(0);
 8302   format %{ "#@unnecessary_membar_volatile_rvwmo (unnecessary so empty encoding)" %}
 8303   ins_encode %{
 8304     __ block_comment("unnecessary_membar_volatile_rvwmo");
 8305   %}
 8306   ins_pipe(real_empty);
 8307 %}
 8308 
 8309 instruct spin_wait() %{
 8310   predicate(UseZihintpause);
 8311   match(OnSpinWait);
 8312   ins_cost(CACHE_MISS_COST);
 8313 
 8314   format %{ "spin_wait" %}
 8315 
 8316   ins_encode %{
 8317     __ pause();
 8318   %}
 8319 
 8320   ins_pipe(pipe_serial);
 8321 %}
 8322 
 8323 // ============================================================================
 8324 // Cast Instructions (Java-level type cast)
 8325 
 8326 instruct castX2P(iRegPNoSp dst, iRegL src) %{
 8327   match(Set dst (CastX2P src));
 8328 
 8329   ins_cost(ALU_COST);
 8330   format %{ "mv  $dst, $src\t# long -> ptr, #@castX2P" %}
 8331 
 8332   ins_encode %{
 8333     if ($dst$$reg != $src$$reg) {
 8334       __ mv(as_Register($dst$$reg), as_Register($src$$reg));
 8335     }
 8336   %}
 8337 
 8338   ins_pipe(ialu_reg);
 8339 %}
 8340 
 8341 instruct castP2X(iRegLNoSp dst, iRegP src) %{
 8342   match(Set dst (CastP2X src));
 8343 
 8344   ins_cost(ALU_COST);
 8345   format %{ "mv  $dst, $src\t# ptr -> long, #@castP2X" %}
 8346 
 8347   ins_encode %{
 8348     if ($dst$$reg != $src$$reg) {
 8349       __ mv(as_Register($dst$$reg), as_Register($src$$reg));
 8350     }
 8351   %}
 8352 
 8353   ins_pipe(ialu_reg);
 8354 %}
 8355 
 8356 instruct castPP(iRegPNoSp dst)
 8357 %{
 8358   match(Set dst (CastPP dst));
 8359   ins_cost(0);
 8360 
 8361   size(0);
 8362   format %{ "# castPP of $dst, #@castPP" %}
 8363   ins_encode(/* empty encoding */);
 8364   ins_pipe(pipe_class_empty);
 8365 %}
 8366 
 8367 instruct castLL(iRegL dst)
 8368 %{
 8369   match(Set dst (CastLL dst));
 8370 
 8371   size(0);
 8372   format %{ "# castLL of $dst, #@castLL" %}
 8373   ins_encode(/* empty encoding */);
 8374   ins_cost(0);
 8375   ins_pipe(pipe_class_empty);
 8376 %}
 8377 
 8378 instruct castII(iRegI dst)
 8379 %{
 8380   match(Set dst (CastII dst));
 8381 
 8382   size(0);
 8383   format %{ "# castII of $dst, #@castII" %}
 8384   ins_encode(/* empty encoding */);
 8385   ins_cost(0);
 8386   ins_pipe(pipe_class_empty);
 8387 %}
 8388 
 8389 instruct checkCastPP(iRegPNoSp dst)
 8390 %{
 8391   match(Set dst (CheckCastPP dst));
 8392 
 8393   size(0);
 8394   ins_cost(0);
 8395   format %{ "# checkcastPP of $dst, #@checkCastPP" %}
 8396   ins_encode(/* empty encoding */);
 8397   ins_pipe(pipe_class_empty);
 8398 %}
 8399 
 8400 instruct castHH(fRegF dst)
 8401 %{
 8402   match(Set dst (CastHH dst));
 8403 
 8404   size(0);
 8405   format %{ "# castHH of $dst" %}
 8406   ins_encode(/* empty encoding */);
 8407   ins_cost(0);
 8408   ins_pipe(pipe_class_empty);
 8409 %}
 8410 
 8411 instruct castFF(fRegF dst)
 8412 %{
 8413   match(Set dst (CastFF dst));
 8414 
 8415   size(0);
 8416   format %{ "# castFF of $dst" %}
 8417   ins_encode(/* empty encoding */);
 8418   ins_cost(0);
 8419   ins_pipe(pipe_class_empty);
 8420 %}
 8421 
 8422 instruct castDD(fRegD dst)
 8423 %{
 8424   match(Set dst (CastDD dst));
 8425 
 8426   size(0);
 8427   format %{ "# castDD of $dst" %}
 8428   ins_encode(/* empty encoding */);
 8429   ins_cost(0);
 8430   ins_pipe(pipe_class_empty);
 8431 %}
 8432 
 8433 instruct castVV(vReg dst)
 8434 %{
 8435   match(Set dst (CastVV dst));
 8436 
 8437   size(0);
 8438   format %{ "# castVV of $dst" %}
 8439   ins_encode(/* empty encoding */);
 8440   ins_cost(0);
 8441   ins_pipe(pipe_class_empty);
 8442 %}
 8443 
 8444 instruct castVVMask(vRegMask dst)
 8445 %{
 8446   match(Set dst (CastVV dst));
 8447 
 8448   size(0);
 8449   format %{ "# castVV of $dst" %}
 8450   ins_encode(/* empty encoding */);
 8451   ins_cost(0);
 8452   ins_pipe(pipe_class_empty);
 8453 %}
 8454 
 8455 // ============================================================================
 8456 // Convert Instructions
 8457 
 8458 // int to bool
 8459 instruct convI2Bool(iRegINoSp dst, iRegI src)
 8460 %{
 8461   match(Set dst (Conv2B src));
 8462 
 8463   ins_cost(ALU_COST);
 8464   format %{ "snez  $dst, $src\t#@convI2Bool" %}
 8465 
 8466   ins_encode %{
 8467     __ snez(as_Register($dst$$reg), as_Register($src$$reg));
 8468   %}
 8469 
 8470   ins_pipe(ialu_reg);
 8471 %}
 8472 
 8473 // pointer to bool
 8474 instruct convP2Bool(iRegINoSp dst, iRegP src)
 8475 %{
 8476   match(Set dst (Conv2B src));
 8477 
 8478   ins_cost(ALU_COST);
 8479   format %{ "snez  $dst, $src\t#@convP2Bool" %}
 8480 
 8481   ins_encode %{
 8482     __ snez(as_Register($dst$$reg), as_Register($src$$reg));
 8483   %}
 8484 
 8485   ins_pipe(ialu_reg);
 8486 %}
 8487 
 8488 // int <-> long
 8489 
 8490 instruct convI2L_reg_reg(iRegLNoSp dst, iRegIorL2I src)
 8491 %{
 8492   match(Set dst (ConvI2L src));
 8493 
 8494   ins_cost(ALU_COST);
 8495   format %{ "addw  $dst, $src, zr\t#@convI2L_reg_reg" %}
 8496   ins_encode %{
 8497     __ sext(as_Register($dst$$reg), as_Register($src$$reg), 32);
 8498   %}
 8499   ins_pipe(ialu_reg);
 8500 %}
 8501 
 8502 instruct convL2I_reg(iRegINoSp dst, iRegL src) %{
 8503   match(Set dst (ConvL2I src));
 8504 
 8505   ins_cost(ALU_COST);
 8506   format %{ "addw  $dst, $src, zr\t#@convL2I_reg" %}
 8507 
 8508   ins_encode %{
 8509     __ sext(as_Register($dst$$reg), as_Register($src$$reg), 32);
 8510   %}
 8511 
 8512   ins_pipe(ialu_reg);
 8513 %}
 8514 
 8515 // int to unsigned long (Zero-extend)
 8516 instruct convI2UL_reg_reg(iRegLNoSp dst, iRegIorL2I src, immL_32bits mask)
 8517 %{
 8518   match(Set dst (AndL (ConvI2L src) mask));
 8519 
 8520   ins_cost(ALU_COST * 2);
 8521   format %{ "zext $dst, $src, 32\t# i2ul, #@convI2UL_reg_reg" %}
 8522 
 8523   ins_encode %{
 8524     __ zext(as_Register($dst$$reg), as_Register($src$$reg), 32);
 8525   %}
 8526 
 8527   ins_pipe(ialu_reg_shift);
 8528 %}
 8529 
 8530 // float <-> double
 8531 
 8532 instruct convF2D_reg(fRegD dst, fRegF src) %{
 8533   match(Set dst (ConvF2D src));
 8534 
 8535   ins_cost(XFER_COST);
 8536   format %{ "fcvt.d.s  $dst, $src\t#@convF2D_reg" %}
 8537 
 8538   ins_encode %{
 8539     __ fcvt_d_s(as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg));
 8540   %}
 8541 
 8542   ins_pipe(fp_f2d);
 8543 %}
 8544 
 8545 instruct convD2F_reg(fRegF dst, fRegD src) %{
 8546   match(Set dst (ConvD2F src));
 8547 
 8548   ins_cost(XFER_COST);
 8549   format %{ "fcvt.s.d  $dst, $src\t#@convD2F_reg" %}
 8550 
 8551   ins_encode %{
 8552     __ fcvt_s_d(as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg));
 8553   %}
 8554 
 8555   ins_pipe(fp_d2f);
 8556 %}
 8557 
 8558 // single <-> half precision
 8559 
 8560 instruct convHF2F_reg_reg(fRegF dst, iRegINoSp src, iRegINoSp tmp) %{
 8561   match(Set dst (ConvHF2F src));
 8562   effect(TEMP tmp);
 8563   format %{ "fmv.h.x $dst, $src\t# move source from $src to $dst\n\t"
 8564             "fcvt.s.h $dst, $dst\t# convert half to single precision"
 8565   %}
 8566   ins_encode %{
 8567     __ float16_to_float($dst$$FloatRegister, $src$$Register, $tmp$$Register);
 8568   %}
 8569   ins_pipe(pipe_slow);
 8570 %}
 8571 
 8572 instruct convF2HF_reg_reg(iRegINoSp dst, fRegF src, fRegF ftmp, iRegINoSp xtmp) %{
 8573   match(Set dst (ConvF2HF src));
 8574   effect(TEMP_DEF dst, TEMP ftmp, TEMP xtmp);
 8575   format %{ "fcvt.h.s $ftmp, $src\t# convert single precision to half\n\t"
 8576             "fmv.x.h $dst, $ftmp\t# move result from $ftmp to $dst"
 8577   %}
 8578   ins_encode %{
 8579     __ float_to_float16($dst$$Register, $src$$FloatRegister, $ftmp$$FloatRegister, $xtmp$$Register);
 8580   %}
 8581   ins_pipe(pipe_slow);
 8582 %}
 8583 
 8584 // half precision operations
 8585 
 8586 instruct reinterpretS2HF(fRegF dst, iRegI src)
 8587 %{
 8588   match(Set dst (ReinterpretS2HF src));
 8589   format %{ "fmv.h.x $dst, $src" %}
 8590   ins_encode %{
 8591     __ fmv_h_x($dst$$FloatRegister, $src$$Register);
 8592   %}
 8593   ins_pipe(fp_i2f);
 8594 %}
 8595 
 8596 instruct convF2HFAndS2HF(fRegF dst, fRegF src)
 8597 %{
 8598   match(Set dst (ReinterpretS2HF (ConvF2HF src)));
 8599   format %{ "convF2HFAndS2HF $dst, $src" %}
 8600   ins_encode %{
 8601     __ fcvt_h_s($dst$$FloatRegister, $src$$FloatRegister);
 8602   %}
 8603   ins_pipe(fp_uop_s);
 8604 %}
 8605 
 8606 instruct reinterpretHF2S(iRegINoSp dst, fRegF src)
 8607 %{
 8608   match(Set dst (ReinterpretHF2S src));
 8609   format %{ "fmv.x.h $dst, $src" %}
 8610   ins_encode %{
 8611     __ fmv_x_h($dst$$Register, $src$$FloatRegister);
 8612   %}
 8613   ins_pipe(fp_f2i);
 8614 %}
 8615 
 8616 instruct convHF2SAndHF2F(fRegF dst, fRegF src)
 8617 %{
 8618   match(Set dst (ConvHF2F (ReinterpretHF2S src)));
 8619   format %{ "convHF2SAndHF2F $dst, $src" %}
 8620   ins_encode %{
 8621     __ fcvt_s_h($dst$$FloatRegister, $src$$FloatRegister);
 8622   %}
 8623   ins_pipe(fp_uop_s);
 8624 %}
 8625 
 8626 instruct sqrt_HF_reg(fRegF dst, fRegF src)
 8627 %{
 8628   match(Set dst (SqrtHF src));
 8629   format %{ "fsqrt.h $dst, $src" %}
 8630   ins_encode %{
 8631     __ fsqrt_h($dst$$FloatRegister, $src$$FloatRegister);
 8632   %}
 8633   ins_pipe(fp_sqrt_s);
 8634 %}
 8635 
 8636 instruct binOps_HF_reg(fRegF dst, fRegF src1, fRegF src2)
 8637 %{
 8638   match(Set dst (AddHF src1 src2));
 8639   match(Set dst (SubHF src1 src2));
 8640   match(Set dst (MulHF src1 src2));
 8641   match(Set dst (DivHF src1 src2));
 8642   format %{ "binop_hf $dst, $src1, $src2" %}
 8643   ins_encode %{
 8644     int opcode = this->ideal_Opcode();
 8645     switch(opcode) {
 8646       case Op_AddHF: __ fadd_h($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); break;
 8647       case Op_SubHF: __ fsub_h($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); break;
 8648       case Op_MulHF: __ fmul_h($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); break;
 8649       case Op_DivHF: __ fdiv_h($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); break;
 8650       default: assert(false, "%s is not supported here", NodeClassNames[opcode]); break;
 8651     }
 8652   %}
 8653   ins_pipe(fp_dop_reg_reg_s);
 8654 %}
 8655 
 8656 instruct min_HF_reg(fRegF dst, fRegF src1, fRegF src2, rFlagsReg cr)
 8657 %{
 8658   predicate(!UseZfa);
 8659   match(Set dst (MinHF src1 src2));
 8660   effect(KILL cr);
 8661 
 8662   format %{ "min_hf $dst, $src1, $src2" %}
 8663 
 8664   ins_encode %{
 8665     __ minmax_fp($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister,
 8666                  __ FLOAT_TYPE::half_precision, true /* is_min */);
 8667   %}
 8668   ins_pipe(pipe_class_default);
 8669 %}
 8670 
 8671 instruct min_HF_reg_zfa(fRegF dst, fRegF src1, fRegF src2)
 8672 %{
 8673   predicate(UseZfa);
 8674   match(Set dst (MinHF src1 src2));
 8675 
 8676   format %{ "min_hf $dst, $src1, $src2" %}
 8677 
 8678   ins_encode %{
 8679     __ fminm_h(as_FloatRegister($dst$$reg),
 8680                as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
 8681   %}
 8682 
 8683   ins_pipe(pipe_class_default);
 8684 %}
 8685 
 8686 instruct max_HF_reg(fRegF dst, fRegF src1, fRegF src2, rFlagsReg cr)
 8687 %{
 8688   predicate(!UseZfa);
 8689   match(Set dst (MaxHF src1 src2));
 8690   effect(KILL cr);
 8691 
 8692   format %{ "max_hf $dst, $src1, $src2" %}
 8693 
 8694   ins_encode %{
 8695     __ minmax_fp($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister,
 8696                  __ FLOAT_TYPE::half_precision, false /* is_min */);
 8697   %}
 8698   ins_pipe(pipe_class_default);
 8699 %}
 8700 
 8701 instruct max_HF_reg_zfa(fRegF dst, fRegF src1, fRegF src2)
 8702 %{
 8703   predicate(UseZfa);
 8704   match(Set dst (MaxHF src1 src2));
 8705 
 8706   format %{ "max_hf $dst, $src1, $src2" %}
 8707 
 8708   ins_encode %{
 8709     __ fmaxm_h(as_FloatRegister($dst$$reg),
 8710                as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
 8711   %}
 8712 
 8713   ins_pipe(pipe_class_default);
 8714 %}
 8715 
 8716 instruct fma_HF_reg(fRegF dst, fRegF src1, fRegF src2, fRegF src3)
 8717 %{
 8718   match(Set dst (FmaHF src3 (Binary src1 src2)));
 8719   format %{ "fmadd.h $dst, $src1, $src2, $src3\t# $dst = $src1 * $src2 + $src3 fma packedH" %}
 8720   ins_encode %{
 8721     __ fmadd_h($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister, $src3$$FloatRegister);
 8722   %}
 8723   ins_pipe(pipe_class_default);
 8724 %}
 8725 
 8726 // float <-> int
 8727 
 8728 instruct convF2I_reg_reg(iRegINoSp dst, fRegF src) %{
 8729   match(Set dst (ConvF2I src));
 8730 
 8731   ins_cost(XFER_COST);
 8732   format %{ "fcvt.w.s  $dst, $src\t#@convF2I_reg_reg" %}
 8733 
 8734   ins_encode %{
 8735     __ fcvt_w_s_safe($dst$$Register, $src$$FloatRegister);
 8736   %}
 8737 
 8738   ins_pipe(fp_f2i);
 8739 %}
 8740 
 8741 instruct convI2F_reg_reg(fRegF dst, iRegIorL2I src) %{
 8742   match(Set dst (ConvI2F src));
 8743 
 8744   ins_cost(XFER_COST);
 8745   format %{ "fcvt.s.w  $dst, $src\t#@convI2F_reg_reg" %}
 8746 
 8747   ins_encode %{
 8748     __ fcvt_s_w(as_FloatRegister($dst$$reg), as_Register($src$$reg));
 8749   %}
 8750 
 8751   ins_pipe(fp_i2f);
 8752 %}
 8753 
 8754 // float <-> long
 8755 
 8756 instruct convF2L_reg_reg(iRegLNoSp dst, fRegF src) %{
 8757   match(Set dst (ConvF2L src));
 8758 
 8759   ins_cost(XFER_COST);
 8760   format %{ "fcvt.l.s  $dst, $src\t#@convF2L_reg_reg" %}
 8761 
 8762   ins_encode %{
 8763     __ fcvt_l_s_safe($dst$$Register, $src$$FloatRegister);
 8764   %}
 8765 
 8766   ins_pipe(fp_f2l);
 8767 %}
 8768 
 8769 instruct convL2F_reg_reg(fRegF dst, iRegL src) %{
 8770   match(Set dst (ConvL2F src));
 8771 
 8772   ins_cost(XFER_COST);
 8773   format %{ "fcvt.s.l  $dst, $src\t#@convL2F_reg_reg" %}
 8774 
 8775   ins_encode %{
 8776     __ fcvt_s_l(as_FloatRegister($dst$$reg), as_Register($src$$reg));
 8777   %}
 8778 
 8779   ins_pipe(fp_l2f);
 8780 %}
 8781 
 8782 // double <-> int
 8783 
 8784 instruct convD2I_reg_reg(iRegINoSp dst, fRegD src) %{
 8785   match(Set dst (ConvD2I src));
 8786 
 8787   ins_cost(XFER_COST);
 8788   format %{ "fcvt.w.d  $dst, $src\t#@convD2I_reg_reg" %}
 8789 
 8790   ins_encode %{
 8791     __ fcvt_w_d_safe($dst$$Register, $src$$FloatRegister);
 8792   %}
 8793 
 8794   ins_pipe(fp_d2i);
 8795 %}
 8796 
 8797 instruct convI2D_reg_reg(fRegD dst, iRegIorL2I src) %{
 8798   match(Set dst (ConvI2D src));
 8799 
 8800   ins_cost(XFER_COST);
 8801   format %{ "fcvt.d.w  $dst, $src\t#@convI2D_reg_reg" %}
 8802 
 8803   ins_encode %{
 8804     __ fcvt_d_w(as_FloatRegister($dst$$reg), as_Register($src$$reg));
 8805   %}
 8806 
 8807   ins_pipe(fp_i2d);
 8808 %}
 8809 
 8810 // double <-> long
 8811 
 8812 instruct convD2L_reg_reg(iRegLNoSp dst, fRegD src) %{
 8813   match(Set dst (ConvD2L src));
 8814 
 8815   ins_cost(XFER_COST);
 8816   format %{ "fcvt.l.d  $dst, $src\t#@convD2L_reg_reg" %}
 8817 
 8818   ins_encode %{
 8819     __ fcvt_l_d_safe($dst$$Register, $src$$FloatRegister);
 8820   %}
 8821 
 8822   ins_pipe(fp_d2l);
 8823 %}
 8824 
 8825 instruct convL2D_reg_reg(fRegD dst, iRegL src) %{
 8826   match(Set dst (ConvL2D src));
 8827 
 8828   ins_cost(XFER_COST);
 8829   format %{ "fcvt.d.l  $dst, $src\t#@convL2D_reg_reg" %}
 8830 
 8831   ins_encode %{
 8832     __ fcvt_d_l(as_FloatRegister($dst$$reg), as_Register($src$$reg));
 8833   %}
 8834 
 8835   ins_pipe(fp_l2d);
 8836 %}
 8837 
 8838 // Convert oop into int for vectors alignment masking
 8839 instruct convP2I(iRegINoSp dst, iRegP src) %{
 8840   match(Set dst (ConvL2I (CastP2X src)));
 8841 
 8842   ins_cost(ALU_COST * 2);
 8843   format %{ "zext $dst, $src, 32\t# ptr -> int, #@convP2I" %}
 8844 
 8845   ins_encode %{
 8846     __ zext($dst$$Register, $src$$Register, 32);
 8847   %}
 8848 
 8849   ins_pipe(ialu_reg);
 8850 %}
 8851 
 8852 // Convert compressed oop into int for vectors alignment masking
 8853 // in case of 32bit oops (heap < 4Gb).
 8854 instruct convN2I(iRegINoSp dst, iRegN src)
 8855 %{
 8856   predicate(CompressedOops::shift() == 0);
 8857   match(Set dst (ConvL2I (CastP2X (DecodeN src))));
 8858 
 8859   ins_cost(ALU_COST);
 8860   format %{ "mv  $dst, $src\t# compressed ptr -> int, #@convN2I" %}
 8861 
 8862   ins_encode %{
 8863     __ mv($dst$$Register, $src$$Register);
 8864   %}
 8865 
 8866   ins_pipe(ialu_reg);
 8867 %}
 8868 
 8869 instruct round_double_reg(iRegLNoSp dst, fRegD src, fRegD ftmp) %{
 8870   match(Set dst (RoundD src));
 8871 
 8872   ins_cost(XFER_COST + BRANCH_COST);
 8873   effect(TEMP ftmp);
 8874   format %{ "java_round_double $dst, $src\t#@round_double_reg" %}
 8875 
 8876   ins_encode %{
 8877     __ java_round_double($dst$$Register, as_FloatRegister($src$$reg), as_FloatRegister($ftmp$$reg));
 8878   %}
 8879 
 8880   ins_pipe(pipe_slow);
 8881 %}
 8882 
 8883 instruct round_float_reg(iRegINoSp dst, fRegF src, fRegF ftmp) %{
 8884   match(Set dst (RoundF src));
 8885 
 8886   ins_cost(XFER_COST + BRANCH_COST);
 8887   effect(TEMP ftmp);
 8888   format %{ "java_round_float $dst, $src\t#@round_float_reg" %}
 8889 
 8890   ins_encode %{
 8891     __ java_round_float($dst$$Register, as_FloatRegister($src$$reg), as_FloatRegister($ftmp$$reg));
 8892   %}
 8893 
 8894   ins_pipe(pipe_slow);
 8895 %}
 8896 
 8897 // Convert oop pointer into compressed form
 8898 instruct encodeHeapOop(iRegNNoSp dst, iRegP src) %{
 8899   predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
 8900   match(Set dst (EncodeP src));
 8901   ins_cost(ALU_COST);
 8902   format %{ "encode_heap_oop  $dst, $src\t#@encodeHeapOop" %}
 8903   ins_encode %{
 8904     Register s = $src$$Register;
 8905     Register d = $dst$$Register;
 8906     __ encode_heap_oop(d, s);
 8907   %}
 8908   ins_pipe(pipe_class_default);
 8909 %}
 8910 
 8911 instruct encodeHeapOop_not_null(iRegNNoSp dst, iRegP src) %{
 8912   predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
 8913   match(Set dst (EncodeP src));
 8914   ins_cost(ALU_COST);
 8915   format %{ "encode_heap_oop_not_null $dst, $src\t#@encodeHeapOop_not_null" %}
 8916   ins_encode %{
 8917     __ encode_heap_oop_not_null($dst$$Register, $src$$Register);
 8918   %}
 8919   ins_pipe(pipe_class_default);
 8920 %}
 8921 
 8922 instruct decodeHeapOop(iRegPNoSp dst, iRegN src) %{
 8923   predicate(n->bottom_type()->is_ptr()->ptr() != TypePtr::NotNull &&
 8924             n->bottom_type()->is_ptr()->ptr() != TypePtr::Constant);
 8925   match(Set dst (DecodeN src));
 8926 
 8927   ins_cost(0);
 8928   format %{ "decode_heap_oop  $dst, $src\t#@decodeHeapOop" %}
 8929   ins_encode %{
 8930     Register s = $src$$Register;
 8931     Register d = $dst$$Register;
 8932     __ decode_heap_oop(d, s);
 8933   %}
 8934   ins_pipe(pipe_class_default);
 8935 %}
 8936 
 8937 instruct decodeHeapOop_not_null(iRegPNoSp dst, iRegN src) %{
 8938   predicate(n->bottom_type()->is_ptr()->ptr() == TypePtr::NotNull ||
 8939             n->bottom_type()->is_ptr()->ptr() == TypePtr::Constant);
 8940   match(Set dst (DecodeN src));
 8941 
 8942   ins_cost(0);
 8943   format %{ "decode_heap_oop_not_null $dst, $src\t#@decodeHeapOop_not_null" %}
 8944   ins_encode %{
 8945     Register s = $src$$Register;
 8946     Register d = $dst$$Register;
 8947     __ decode_heap_oop_not_null(d, s);
 8948   %}
 8949   ins_pipe(pipe_class_default);
 8950 %}
 8951 
 8952 // Convert klass pointer into compressed form.
 8953 instruct encodeKlass_not_null(iRegNNoSp dst, iRegP src) %{
 8954   match(Set dst (EncodePKlass src));
 8955 
 8956   ins_cost(ALU_COST);
 8957   format %{ "encode_klass_not_null  $dst, $src\t#@encodeKlass_not_null" %}
 8958 
 8959   ins_encode %{
 8960     Register src_reg = as_Register($src$$reg);
 8961     Register dst_reg = as_Register($dst$$reg);
 8962     __ encode_klass_not_null(dst_reg, src_reg, t0);
 8963   %}
 8964 
 8965    ins_pipe(pipe_class_default);
 8966 %}
 8967 
 8968 instruct decodeKlass_not_null(iRegPNoSp dst, iRegN src, iRegPNoSp tmp) %{
 8969   match(Set dst (DecodeNKlass src));
 8970 
 8971   effect(TEMP tmp);
 8972 
 8973   ins_cost(ALU_COST);
 8974   format %{ "decode_klass_not_null  $dst, $src\t#@decodeKlass_not_null" %}
 8975 
 8976   ins_encode %{
 8977     Register src_reg = as_Register($src$$reg);
 8978     Register dst_reg = as_Register($dst$$reg);
 8979     Register tmp_reg = as_Register($tmp$$reg);
 8980     __ decode_klass_not_null(dst_reg, src_reg, tmp_reg);
 8981   %}
 8982 
 8983    ins_pipe(pipe_class_default);
 8984 %}
 8985 
 8986 // stack <-> reg and reg <-> reg shuffles with no conversion
 8987 
 8988 instruct MoveF2I_stack_reg(iRegINoSp dst, stackSlotF src) %{
 8989 
 8990   match(Set dst (MoveF2I src));
 8991 
 8992   effect(DEF dst, USE src);
 8993 
 8994   ins_cost(LOAD_COST);
 8995 
 8996   format %{ "lw  $dst, $src\t#@MoveF2I_stack_reg" %}
 8997 
 8998   ins_encode %{
 8999     __ lw(as_Register($dst$$reg), Address(sp, $src$$disp));
 9000   %}
 9001 
 9002   ins_pipe(iload_reg_reg);
 9003 
 9004 %}
 9005 
 9006 instruct MoveI2F_stack_reg(fRegF dst, stackSlotI src) %{
 9007 
 9008   match(Set dst (MoveI2F src));
 9009 
 9010   effect(DEF dst, USE src);
 9011 
 9012   ins_cost(LOAD_COST);
 9013 
 9014   format %{ "flw  $dst, $src\t#@MoveI2F_stack_reg" %}
 9015 
 9016   ins_encode %{
 9017     __ flw(as_FloatRegister($dst$$reg), Address(sp, $src$$disp));
 9018   %}
 9019 
 9020   ins_pipe(fp_load_mem_s);
 9021 
 9022 %}
 9023 
 9024 instruct MoveD2L_stack_reg(iRegLNoSp dst, stackSlotD src) %{
 9025 
 9026   match(Set dst (MoveD2L src));
 9027 
 9028   effect(DEF dst, USE src);
 9029 
 9030   ins_cost(LOAD_COST);
 9031 
 9032   format %{ "ld  $dst, $src\t#@MoveD2L_stack_reg" %}
 9033 
 9034   ins_encode %{
 9035     __ ld(as_Register($dst$$reg), Address(sp, $src$$disp));
 9036   %}
 9037 
 9038   ins_pipe(iload_reg_reg);
 9039 
 9040 %}
 9041 
 9042 instruct MoveL2D_stack_reg(fRegD dst, stackSlotL src) %{
 9043 
 9044   match(Set dst (MoveL2D src));
 9045 
 9046   effect(DEF dst, USE src);
 9047 
 9048   ins_cost(LOAD_COST);
 9049 
 9050   format %{ "fld  $dst, $src\t#@MoveL2D_stack_reg" %}
 9051 
 9052   ins_encode %{
 9053     __ fld(as_FloatRegister($dst$$reg), Address(sp, $src$$disp));
 9054   %}
 9055 
 9056   ins_pipe(fp_load_mem_d);
 9057 
 9058 %}
 9059 
 9060 instruct MoveF2I_reg_stack(stackSlotI dst, fRegF src) %{
 9061 
 9062   match(Set dst (MoveF2I src));
 9063 
 9064   effect(DEF dst, USE src);
 9065 
 9066   ins_cost(STORE_COST);
 9067 
 9068   format %{ "fsw  $src, $dst\t#@MoveF2I_reg_stack" %}
 9069 
 9070   ins_encode %{
 9071     __ fsw(as_FloatRegister($src$$reg), Address(sp, $dst$$disp));
 9072   %}
 9073 
 9074   ins_pipe(fp_store_reg_s);
 9075 
 9076 %}
 9077 
 9078 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{
 9079 
 9080   match(Set dst (MoveI2F src));
 9081 
 9082   effect(DEF dst, USE src);
 9083 
 9084   ins_cost(STORE_COST);
 9085 
 9086   format %{ "sw  $src, $dst\t#@MoveI2F_reg_stack" %}
 9087 
 9088   ins_encode %{
 9089     __ sw(as_Register($src$$reg), Address(sp, $dst$$disp));
 9090   %}
 9091 
 9092   ins_pipe(istore_reg_reg);
 9093 
 9094 %}
 9095 
 9096 instruct MoveD2L_reg_stack(stackSlotL dst, fRegD src) %{
 9097 
 9098   match(Set dst (MoveD2L src));
 9099 
 9100   effect(DEF dst, USE src);
 9101 
 9102   ins_cost(STORE_COST);
 9103 
 9104   format %{ "fsd  $dst, $src\t#@MoveD2L_reg_stack" %}
 9105 
 9106   ins_encode %{
 9107     __ fsd(as_FloatRegister($src$$reg), Address(sp, $dst$$disp));
 9108   %}
 9109 
 9110   ins_pipe(fp_store_reg_d);
 9111 
 9112 %}
 9113 
 9114 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{
 9115 
 9116   match(Set dst (MoveL2D src));
 9117 
 9118   effect(DEF dst, USE src);
 9119 
 9120   ins_cost(STORE_COST);
 9121 
 9122   format %{ "sd  $src, $dst\t#@MoveL2D_reg_stack" %}
 9123 
 9124   ins_encode %{
 9125     __ sd(as_Register($src$$reg), Address(sp, $dst$$disp));
 9126   %}
 9127 
 9128   ins_pipe(istore_reg_reg);
 9129 
 9130 %}
 9131 
 9132 instruct MoveF2I_reg_reg(iRegINoSp dst, fRegF src) %{
 9133 
 9134   match(Set dst (MoveF2I src));
 9135 
 9136   effect(DEF dst, USE src);
 9137 
 9138   ins_cost(FMVX_COST);
 9139 
 9140   format %{ "fmv.x.w  $dst, $src\t#@MoveF2I_reg_reg" %}
 9141 
 9142   ins_encode %{
 9143     __ fmv_x_w(as_Register($dst$$reg), as_FloatRegister($src$$reg));
 9144   %}
 9145 
 9146   ins_pipe(fp_f2i);
 9147 
 9148 %}
 9149 
 9150 instruct MoveI2F_reg_reg(fRegF dst, iRegI src) %{
 9151 
 9152   match(Set dst (MoveI2F src));
 9153 
 9154   effect(DEF dst, USE src);
 9155 
 9156   ins_cost(FMVX_COST);
 9157 
 9158   format %{ "fmv.w.x  $dst, $src\t#@MoveI2F_reg_reg" %}
 9159 
 9160   ins_encode %{
 9161     __ fmv_w_x(as_FloatRegister($dst$$reg), as_Register($src$$reg));
 9162   %}
 9163 
 9164   ins_pipe(fp_i2f);
 9165 
 9166 %}
 9167 
 9168 instruct MoveD2L_reg_reg(iRegLNoSp dst, fRegD src) %{
 9169 
 9170   match(Set dst (MoveD2L src));
 9171 
 9172   effect(DEF dst, USE src);
 9173 
 9174   ins_cost(FMVX_COST);
 9175 
 9176   format %{ "fmv.x.d $dst, $src\t#@MoveD2L_reg_reg" %}
 9177 
 9178   ins_encode %{
 9179     __ fmv_x_d(as_Register($dst$$reg), as_FloatRegister($src$$reg));
 9180   %}
 9181 
 9182   ins_pipe(fp_d2l);
 9183 
 9184 %}
 9185 
 9186 instruct MoveL2D_reg_reg(fRegD dst, iRegL src) %{
 9187 
 9188   match(Set dst (MoveL2D src));
 9189 
 9190   effect(DEF dst, USE src);
 9191 
 9192   ins_cost(FMVX_COST);
 9193 
 9194   format %{ "fmv.d.x  $dst, $src\t#@MoveL2D_reg_reg" %}
 9195 
 9196   ins_encode %{
 9197     __ fmv_d_x(as_FloatRegister($dst$$reg), as_Register($src$$reg));
 9198   %}
 9199 
 9200   ins_pipe(fp_l2d);
 9201 
 9202 %}
 9203 
 9204 // ============================================================================
 9205 // Compare Instructions which set the result float comparisons in dest register.
 9206 
 9207 instruct cmpF3_reg_reg(iRegINoSp dst, fRegF op1, fRegF op2)
 9208 %{
 9209   match(Set dst (CmpF3 op1 op2));
 9210 
 9211   ins_cost(XFER_COST * 2 + BRANCH_COST + ALU_COST);
 9212   format %{ "flt.s  $dst, $op2, $op1\t#@cmpF3_reg_reg\n\t"
 9213             "bgtz   $dst, done\n\t"
 9214             "feq.s  $dst, $op1, $op2\n\t"
 9215             "addi   $dst, $dst, -1\n\t"
 9216             "done:"
 9217   %}
 9218 
 9219   ins_encode %{
 9220     // we want -1 for unordered or less than, 0 for equal and 1 for greater than.
 9221     __ float_compare(as_Register($dst$$reg), as_FloatRegister($op1$$reg),
 9222                      as_FloatRegister($op2$$reg), -1 /*unordered_result < 0*/);
 9223   %}
 9224 
 9225   ins_pipe(pipe_class_default);
 9226 %}
 9227 
 9228 instruct cmpD3_reg_reg(iRegINoSp dst, fRegD op1, fRegD op2)
 9229 %{
 9230   match(Set dst (CmpD3 op1 op2));
 9231 
 9232   ins_cost(XFER_COST * 2 + BRANCH_COST + ALU_COST);
 9233   format %{ "flt.d  $dst, $op2, $op1\t#@cmpD3_reg_reg\n\t"
 9234             "bgtz   $dst, done\n\t"
 9235             "feq.d  $dst, $op1, $op2\n\t"
 9236             "addi   $dst, $dst, -1\n\t"
 9237             "done:"
 9238   %}
 9239 
 9240   ins_encode %{
 9241     // we want -1 for unordered or less than, 0 for equal and 1 for greater than.
 9242     __ double_compare(as_Register($dst$$reg), as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg), -1 /*unordered_result < 0*/);
 9243   %}
 9244 
 9245   ins_pipe(pipe_class_default);
 9246 %}
 9247 
 9248 instruct cmpL3_reg_reg(iRegINoSp dst, iRegL op1, iRegL op2)
 9249 %{
 9250   match(Set dst (CmpL3 op1 op2));
 9251 
 9252   ins_cost(ALU_COST * 3 + BRANCH_COST);
 9253   format %{ "slt   $dst, $op2, $op1\t#@cmpL3_reg_reg\n\t"
 9254             "bnez  $dst, done\n\t"
 9255             "slt   $dst, $op1, $op2\n\t"
 9256             "neg   $dst, $dst\n\t"
 9257             "done:"
 9258   %}
 9259   ins_encode %{
 9260     __ cmp_l2i(t0, as_Register($op1$$reg), as_Register($op2$$reg));
 9261     __ mv(as_Register($dst$$reg), t0);
 9262   %}
 9263 
 9264   ins_pipe(pipe_class_default);
 9265 %}
 9266 
 9267 instruct cmpUL3_reg_reg(iRegINoSp dst, iRegL op1, iRegL op2)
 9268 %{
 9269   match(Set dst (CmpUL3 op1 op2));
 9270 
 9271   ins_cost(ALU_COST * 3 + BRANCH_COST);
 9272   format %{ "sltu  $dst, $op2, $op1\t#@cmpUL3_reg_reg\n\t"
 9273             "bnez  $dst, done\n\t"
 9274             "sltu  $dst, $op1, $op2\n\t"
 9275             "neg   $dst, $dst\n\t"
 9276             "done:"
 9277   %}
 9278   ins_encode %{
 9279     __ cmp_ul2i(t0, as_Register($op1$$reg), as_Register($op2$$reg));
 9280     __ mv(as_Register($dst$$reg), t0);
 9281   %}
 9282 
 9283   ins_pipe(pipe_class_default);
 9284 %}
 9285 
 9286 instruct cmpU3_reg_reg(iRegINoSp dst, iRegI op1, iRegI op2)
 9287 %{
 9288   match(Set dst (CmpU3 op1 op2));
 9289 
 9290   ins_cost(ALU_COST * 3 + BRANCH_COST);
 9291   format %{ "sltu  $dst, $op2, $op1\t#@cmpU3_reg_reg\n\t"
 9292             "bnez  $dst, done\n\t"
 9293             "sltu  $dst, $op1, $op2\n\t"
 9294             "neg   $dst, $dst\n\t"
 9295             "done:"
 9296   %}
 9297   ins_encode %{
 9298     __ cmp_uw2i(t0, as_Register($op1$$reg), as_Register($op2$$reg));
 9299     __ mv(as_Register($dst$$reg), t0);
 9300   %}
 9301 
 9302   ins_pipe(pipe_class_default);
 9303 %}
 9304 
 9305 instruct cmpLTMask_reg_reg(iRegINoSp dst, iRegI p, iRegI q)
 9306 %{
 9307   match(Set dst (CmpLTMask p q));
 9308 
 9309   ins_cost(2 * ALU_COST);
 9310 
 9311   format %{ "slt $dst, $p, $q\t#@cmpLTMask_reg_reg\n\t"
 9312             "subw $dst, zr, $dst\t#@cmpLTMask_reg_reg"
 9313   %}
 9314 
 9315   ins_encode %{
 9316     __ slt(as_Register($dst$$reg), as_Register($p$$reg), as_Register($q$$reg));
 9317     __ subw(as_Register($dst$$reg), zr, as_Register($dst$$reg));
 9318   %}
 9319 
 9320   ins_pipe(ialu_reg_reg);
 9321 %}
 9322 
 9323 instruct cmpLTMask_reg_zero(iRegINoSp dst, iRegIorL2I op, immI0 zero)
 9324 %{
 9325   match(Set dst (CmpLTMask op zero));
 9326 
 9327   ins_cost(ALU_COST);
 9328 
 9329   format %{ "sraiw $dst, $dst, 31\t#@cmpLTMask_reg_reg" %}
 9330 
 9331   ins_encode %{
 9332     __ sraiw(as_Register($dst$$reg), as_Register($op$$reg), 31);
 9333   %}
 9334 
 9335   ins_pipe(ialu_reg_shift);
 9336 %}
 9337 
 9338 
 9339 // ============================================================================
 9340 // Max and Min
 9341 
 9342 instruct minI_reg_reg(iRegINoSp dst, iRegI src)
 9343 %{
 9344   match(Set dst (MinI dst src));
 9345 
 9346   ins_cost(BRANCH_COST + ALU_COST);
 9347   format %{"minI_reg_reg $dst, $dst, $src\t#@minI_reg_reg\n\t"%}
 9348 
 9349   ins_encode %{
 9350     __ cmov_gt(as_Register($dst$$reg), as_Register($src$$reg),
 9351                as_Register($dst$$reg), as_Register($src$$reg));
 9352   %}
 9353 
 9354   ins_pipe(pipe_class_compare);
 9355 %}
 9356 
 9357 instruct maxI_reg_reg(iRegINoSp dst, iRegI src)
 9358 %{
 9359   match(Set dst (MaxI dst src));
 9360 
 9361   ins_cost(BRANCH_COST + ALU_COST);
 9362   format %{"maxI_reg_reg $dst, $dst, $src\t#@maxI_reg_reg\n\t"%}
 9363 
 9364   ins_encode %{
 9365     __ cmov_lt(as_Register($dst$$reg), as_Register($src$$reg),
 9366                as_Register($dst$$reg), as_Register($src$$reg));
 9367   %}
 9368 
 9369   ins_pipe(pipe_class_compare);
 9370 %}
 9371 
 9372 // special case for comparing with zero
 9373 // n.b. this is selected in preference to the rule above because it
 9374 // avoids loading constant 0 into a source register
 9375 
 9376 instruct minI_reg_zero(iRegINoSp dst, immI0 zero)
 9377 %{
 9378   match(Set dst (MinI dst zero));
 9379   match(Set dst (MinI zero dst));
 9380 
 9381   ins_cost(BRANCH_COST + ALU_COST);
 9382   format %{"minI_reg_zero $dst, $dst, zr\t#@minI_reg_zero\n\t"%}
 9383 
 9384   ins_encode %{
 9385     __ cmov_gt(as_Register($dst$$reg), zr,
 9386                as_Register($dst$$reg), zr);
 9387   %}
 9388 
 9389   ins_pipe(pipe_class_compare);
 9390 %}
 9391 
 9392 instruct maxI_reg_zero(iRegINoSp dst, immI0 zero)
 9393 %{
 9394   match(Set dst (MaxI dst zero));
 9395   match(Set dst (MaxI zero dst));
 9396 
 9397   ins_cost(BRANCH_COST + ALU_COST);
 9398   format %{"maxI_reg_zero $dst, $dst, zr\t#@maxI_reg_zero\n\t"%}
 9399 
 9400   ins_encode %{
 9401     __ cmov_lt(as_Register($dst$$reg), zr,
 9402                as_Register($dst$$reg), zr);
 9403   %}
 9404 
 9405   ins_pipe(pipe_class_compare);
 9406 %}
 9407 
 9408 instruct minI_rReg(iRegINoSp dst, iRegI src1, iRegI src2)
 9409 %{
 9410   match(Set dst (MinI src1 src2));
 9411 
 9412   effect(DEF dst, USE src1, USE src2);
 9413 
 9414   ins_cost(BRANCH_COST + ALU_COST * 2);
 9415   format %{"minI_rReg $dst, $src1, $src2\t#@minI_rReg\n\t"%}
 9416 
 9417   ins_encode %{
 9418     __ mv(as_Register($dst$$reg), as_Register($src1$$reg));
 9419     __ cmov_gt(as_Register($src1$$reg), as_Register($src2$$reg),
 9420                as_Register($dst$$reg), as_Register($src2$$reg));
 9421   %}
 9422 
 9423   ins_pipe(pipe_class_compare);
 9424 %}
 9425 
 9426 instruct maxI_rReg(iRegINoSp dst, iRegI src1, iRegI src2)
 9427 %{
 9428   match(Set dst (MaxI src1 src2));
 9429 
 9430   effect(DEF dst, USE src1, USE src2);
 9431 
 9432   ins_cost(BRANCH_COST + ALU_COST * 2);
 9433   format %{"maxI_rReg $dst, $src1, $src2\t#@maxI_rReg\n\t"%}
 9434 
 9435   ins_encode %{
 9436     __ mv(as_Register($dst$$reg), as_Register($src1$$reg));
 9437     __ cmov_lt(as_Register($src1$$reg), as_Register($src2$$reg),
 9438                as_Register($dst$$reg), as_Register($src2$$reg));
 9439   %}
 9440 
 9441   ins_pipe(pipe_class_compare);
 9442 %}
 9443 
 9444 // ============================================================================
 9445 // Branch Instructions
 9446 // Direct Branch.
 9447 instruct branch(label lbl)
 9448 %{
 9449   match(Goto);
 9450 
 9451   effect(USE lbl);
 9452 
 9453   ins_cost(BRANCH_COST);
 9454   format %{ "j  $lbl\t#@branch" %}
 9455 
 9456   ins_encode(riscv_enc_j(lbl));
 9457 
 9458   ins_pipe(pipe_branch);
 9459 %}
 9460 
 9461 // ============================================================================
 9462 // Compare and Branch Instructions
 9463 
 9464 // Patterns for short (< 12KiB) variants
 9465 
 9466 // Compare flags and branch near instructions.
 9467 instruct cmpFlag_branch(cmpOpEqNe cmp, rFlagsReg cr, label lbl) %{
 9468   match(If cmp cr);
 9469   effect(USE lbl);
 9470 
 9471   ins_cost(BRANCH_COST);
 9472   format %{ "b$cmp  $cr, zr, $lbl\t#@cmpFlag_branch" %}
 9473 
 9474   ins_encode %{
 9475     __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($cr$$reg), *($lbl$$label));
 9476   %}
 9477   ins_pipe(pipe_cmpz_branch);
 9478   ins_short_branch(1);
 9479 %}
 9480 
 9481 // Compare signed int and branch near instructions
 9482 instruct cmpI_branch(cmpOp cmp, iRegI op1, iRegI op2, label lbl)
 9483 %{
 9484   // Same match rule as `far_cmpI_branch'.
 9485   match(If cmp (CmpI op1 op2));
 9486 
 9487   effect(USE lbl);
 9488 
 9489   ins_cost(BRANCH_COST);
 9490 
 9491   format %{ "b$cmp  $op1, $op2, $lbl\t#@cmpI_branch" %}
 9492 
 9493   ins_encode %{
 9494     __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label));
 9495   %}
 9496 
 9497   ins_pipe(pipe_cmp_branch);
 9498   ins_short_branch(1);
 9499 %}
 9500 
 9501 instruct cmpI_loop(cmpOp cmp, iRegI op1, iRegI op2, label lbl)
 9502 %{
 9503   // Same match rule as `far_cmpI_loop'.
 9504   match(CountedLoopEnd cmp (CmpI op1 op2));
 9505 
 9506   effect(USE lbl);
 9507 
 9508   ins_cost(BRANCH_COST);
 9509 
 9510   format %{ "b$cmp  $op1, $op2, $lbl\t#@cmpI_loop" %}
 9511 
 9512   ins_encode %{
 9513     __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label));
 9514   %}
 9515 
 9516   ins_pipe(pipe_cmp_branch);
 9517   ins_short_branch(1);
 9518 %}
 9519 
 9520 // Compare unsigned int and branch near instructions
 9521 instruct cmpU_branch(cmpOpU cmp, iRegI op1, iRegI op2, label lbl)
 9522 %{
 9523   // Same match rule as `far_cmpU_branch'.
 9524   match(If cmp (CmpU op1 op2));
 9525 
 9526   effect(USE lbl);
 9527 
 9528   ins_cost(BRANCH_COST);
 9529 
 9530   format %{ "b$cmp  $op1, $op2, $lbl\t#@cmpU_branch" %}
 9531 
 9532   ins_encode %{
 9533     __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
 9534                   as_Register($op2$$reg), *($lbl$$label));
 9535   %}
 9536 
 9537   ins_pipe(pipe_cmp_branch);
 9538   ins_short_branch(1);
 9539 %}
 9540 
 9541 // Compare signed long and branch near instructions
 9542 instruct cmpL_branch(cmpOp cmp, iRegL op1, iRegL op2, label lbl)
 9543 %{
 9544   // Same match rule as `far_cmpL_branch'.
 9545   match(If cmp (CmpL op1 op2));
 9546 
 9547   effect(USE lbl);
 9548 
 9549   ins_cost(BRANCH_COST);
 9550 
 9551   format %{ "b$cmp  $op1, $op2, $lbl\t#@cmpL_branch" %}
 9552 
 9553   ins_encode %{
 9554     __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label));
 9555   %}
 9556 
 9557   ins_pipe(pipe_cmp_branch);
 9558   ins_short_branch(1);
 9559 %}
 9560 
 9561 instruct cmpL_loop(cmpOp cmp, iRegL op1, iRegL op2, label lbl)
 9562 %{
 9563   // Same match rule as `far_cmpL_loop'.
 9564   match(CountedLoopEnd cmp (CmpL op1 op2));
 9565 
 9566   effect(USE lbl);
 9567 
 9568   ins_cost(BRANCH_COST);
 9569 
 9570   format %{ "b$cmp  $op1, $op2, $lbl\t#@cmpL_loop" %}
 9571 
 9572   ins_encode %{
 9573     __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label));
 9574   %}
 9575 
 9576   ins_pipe(pipe_cmp_branch);
 9577   ins_short_branch(1);
 9578 %}
 9579 
 9580 // Compare unsigned long and branch near instructions
 9581 instruct cmpUL_branch(cmpOpU cmp, iRegL op1, iRegL op2, label lbl)
 9582 %{
 9583   // Same match rule as `far_cmpUL_branch'.
 9584   match(If cmp (CmpUL op1 op2));
 9585 
 9586   effect(USE lbl);
 9587 
 9588   ins_cost(BRANCH_COST);
 9589   format %{ "b$cmp  $op1, $op2, $lbl\t#@cmpUL_branch" %}
 9590 
 9591   ins_encode %{
 9592     __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
 9593                   as_Register($op2$$reg), *($lbl$$label));
 9594   %}
 9595 
 9596   ins_pipe(pipe_cmp_branch);
 9597   ins_short_branch(1);
 9598 %}
 9599 
 9600 // Compare pointer and branch near instructions
 9601 instruct cmpP_branch(cmpOpU cmp, iRegP op1, iRegP op2, label lbl)
 9602 %{
 9603   // Same match rule as `far_cmpP_branch'.
 9604   match(If cmp (CmpP op1 op2));
 9605 
 9606   effect(USE lbl);
 9607 
 9608   ins_cost(BRANCH_COST);
 9609 
 9610   format %{ "b$cmp  $op1, $op2, $lbl\t#@cmpP_branch" %}
 9611 
 9612   ins_encode %{
 9613     __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
 9614                   as_Register($op2$$reg), *($lbl$$label));
 9615   %}
 9616 
 9617   ins_pipe(pipe_cmp_branch);
 9618   ins_short_branch(1);
 9619 %}
 9620 
 9621 // Compare narrow pointer and branch near instructions
 9622 instruct cmpN_branch(cmpOpU cmp, iRegN op1, iRegN op2, label lbl)
 9623 %{
 9624   // Same match rule as `far_cmpN_branch'.
 9625   match(If cmp (CmpN op1 op2));
 9626 
 9627   effect(USE lbl);
 9628 
 9629   ins_cost(BRANCH_COST);
 9630 
 9631   format %{ "b$cmp  $op1, $op2, $lbl\t#@cmpN_branch" %}
 9632 
 9633   ins_encode %{
 9634     __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
 9635                   as_Register($op2$$reg), *($lbl$$label));
 9636   %}
 9637 
 9638   ins_pipe(pipe_cmp_branch);
 9639   ins_short_branch(1);
 9640 %}
 9641 
 9642 // Compare float and branch near instructions
 9643 instruct cmpF_branch(cmpOp cmp, fRegF op1, fRegF op2, label lbl)
 9644 %{
 9645   // Same match rule as `far_cmpF_branch'.
 9646   match(If cmp (CmpF op1 op2));
 9647 
 9648   effect(USE lbl);
 9649 
 9650   ins_cost(XFER_COST + BRANCH_COST);
 9651   format %{ "float_b$cmp $op1, $op2, $lbl \t#@cmpF_branch"%}
 9652 
 9653   ins_encode %{
 9654     __ float_cmp_branch($cmp$$cmpcode, as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg), *($lbl$$label));
 9655   %}
 9656 
 9657   ins_pipe(pipe_class_compare);
 9658   ins_short_branch(1);
 9659 %}
 9660 
 9661 // Compare double and branch near instructions
 9662 instruct cmpD_branch(cmpOp cmp, fRegD op1, fRegD op2, label lbl)
 9663 %{
 9664   // Same match rule as `far_cmpD_branch'.
 9665   match(If cmp (CmpD op1 op2));
 9666   effect(USE lbl);
 9667 
 9668   ins_cost(XFER_COST + BRANCH_COST);
 9669   format %{ "double_b$cmp $op1, $op2, $lbl\t#@cmpD_branch"%}
 9670 
 9671   ins_encode %{
 9672     __ float_cmp_branch($cmp$$cmpcode | C2_MacroAssembler::double_branch_mask, as_FloatRegister($op1$$reg),
 9673                         as_FloatRegister($op2$$reg), *($lbl$$label));
 9674   %}
 9675 
 9676   ins_pipe(pipe_class_compare);
 9677   ins_short_branch(1);
 9678 %}
 9679 
 9680 // Compare signed int with zero and branch near instructions
 9681 instruct cmpI_reg_imm0_branch(cmpOp cmp, iRegI op1, immI0 zero, label lbl)
 9682 %{
 9683   // Same match rule as `far_cmpI_reg_imm0_branch'.
 9684   match(If cmp (CmpI op1 zero));
 9685 
 9686   effect(USE op1, USE lbl);
 9687 
 9688   ins_cost(BRANCH_COST);
 9689   format %{ "b$cmp  $op1, zr, $lbl\t#@cmpI_reg_imm0_branch" %}
 9690 
 9691   ins_encode %{
 9692     __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label));
 9693   %}
 9694 
 9695   ins_pipe(pipe_cmpz_branch);
 9696   ins_short_branch(1);
 9697 %}
 9698 
 9699 instruct cmpI_reg_imm0_loop(cmpOp cmp, iRegI op1, immI0 zero, label lbl)
 9700 %{
 9701   // Same match rule as `far_cmpI_reg_imm0_loop'.
 9702   match(CountedLoopEnd cmp (CmpI op1 zero));
 9703 
 9704   effect(USE op1, USE lbl);
 9705 
 9706   ins_cost(BRANCH_COST);
 9707 
 9708   format %{ "b$cmp  $op1, zr, $lbl\t#@cmpI_reg_imm0_loop" %}
 9709 
 9710   ins_encode %{
 9711     __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label));
 9712   %}
 9713 
 9714   ins_pipe(pipe_cmpz_branch);
 9715   ins_short_branch(1);
 9716 %}
 9717 
 9718 // Compare unsigned int with zero and branch near instructions
 9719 instruct cmpUEqNeLeGt_reg_imm0_branch(cmpOpUEqNeLeGt cmp, iRegI op1, immI0 zero, label lbl)
 9720 %{
 9721   // Same match rule as `far_cmpUEqNeLeGt_reg_imm0_branch'.
 9722   match(If cmp (CmpU op1 zero));
 9723 
 9724   effect(USE op1, USE lbl);
 9725 
 9726   ins_cost(BRANCH_COST);
 9727 
 9728   format %{ "b$cmp  $op1, zr, $lbl\t#@cmpUEqNeLeGt_reg_imm0_branch" %}
 9729 
 9730   ins_encode %{
 9731     __ enc_cmpUEqNeLeGt_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
 9732   %}
 9733 
 9734   ins_pipe(pipe_cmpz_branch);
 9735   ins_short_branch(1);
 9736 %}
 9737 
 9738 // Compare signed long with zero and branch near instructions
 9739 instruct cmpL_reg_imm0_branch(cmpOp cmp, iRegL op1, immL0 zero, label lbl)
 9740 %{
 9741   // Same match rule as `far_cmpL_reg_imm0_branch'.
 9742   match(If cmp (CmpL op1 zero));
 9743 
 9744   effect(USE op1, USE lbl);
 9745 
 9746   ins_cost(BRANCH_COST);
 9747 
 9748   format %{ "b$cmp  $op1, zr, $lbl\t#@cmpL_reg_imm0_branch" %}
 9749 
 9750   ins_encode %{
 9751     __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label));
 9752   %}
 9753 
 9754   ins_pipe(pipe_cmpz_branch);
 9755   ins_short_branch(1);
 9756 %}
 9757 
 9758 instruct cmpL_reg_imm0_loop(cmpOp cmp, iRegL op1, immL0 zero, label lbl)
 9759 %{
 9760   // Same match rule as `far_cmpL_reg_imm0_loop'.
 9761   match(CountedLoopEnd cmp (CmpL op1 zero));
 9762 
 9763   effect(USE op1, USE lbl);
 9764 
 9765   ins_cost(BRANCH_COST);
 9766 
 9767   format %{ "b$cmp  $op1, zr, $lbl\t#@cmpL_reg_imm0_loop" %}
 9768 
 9769   ins_encode %{
 9770     __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label));
 9771   %}
 9772 
 9773   ins_pipe(pipe_cmpz_branch);
 9774   ins_short_branch(1);
 9775 %}
 9776 
 9777 // Compare unsigned long with zero and branch near instructions
 9778 instruct cmpULEqNeLeGt_reg_imm0_branch(cmpOpUEqNeLeGt cmp, iRegL op1, immL0 zero, label lbl)
 9779 %{
 9780   // Same match rule as `far_cmpULEqNeLeGt_reg_imm0_branch'.
 9781   match(If cmp (CmpUL op1 zero));
 9782 
 9783   effect(USE op1, USE lbl);
 9784 
 9785   ins_cost(BRANCH_COST);
 9786 
 9787   format %{ "b$cmp  $op1, zr, $lbl\t#@cmpULEqNeLeGt_reg_imm0_branch" %}
 9788 
 9789   ins_encode %{
 9790     __ enc_cmpUEqNeLeGt_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
 9791   %}
 9792 
 9793   ins_pipe(pipe_cmpz_branch);
 9794   ins_short_branch(1);
 9795 %}
 9796 
 9797 // Compare pointer with zero and branch near instructions
 9798 instruct cmpP_imm0_branch(cmpOpEqNe cmp, iRegP op1, immP0 zero, label lbl) %{
 9799   // Same match rule as `far_cmpP_reg_imm0_branch'.
 9800   match(If cmp (CmpP op1 zero));
 9801   effect(USE lbl);
 9802 
 9803   ins_cost(BRANCH_COST);
 9804   format %{ "b$cmp   $op1, zr, $lbl\t#@cmpP_imm0_branch" %}
 9805 
 9806   ins_encode %{
 9807     __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
 9808   %}
 9809 
 9810   ins_pipe(pipe_cmpz_branch);
 9811   ins_short_branch(1);
 9812 %}
 9813 
 9814 // Compare narrow pointer with zero and branch near instructions
 9815 instruct cmpN_imm0_branch(cmpOpEqNe cmp, iRegN op1, immN0 zero, label lbl) %{
 9816   // Same match rule as `far_cmpN_reg_imm0_branch'.
 9817   match(If cmp (CmpN op1 zero));
 9818   effect(USE lbl);
 9819 
 9820   ins_cost(BRANCH_COST);
 9821 
 9822   format %{ "b$cmp  $op1, zr, $lbl\t#@cmpN_imm0_branch" %}
 9823 
 9824   ins_encode %{
 9825     __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
 9826   %}
 9827 
 9828   ins_pipe(pipe_cmpz_branch);
 9829   ins_short_branch(1);
 9830 %}
 9831 
 9832 // Compare narrow pointer with pointer zero and branch near instructions
 9833 instruct cmpP_narrowOop_imm0_branch(cmpOpEqNe cmp, iRegN op1, immP0 zero, label lbl) %{
 9834   // Same match rule as `far_cmpP_narrowOop_imm0_branch'.
 9835   match(If cmp (CmpP (DecodeN op1) zero));
 9836   effect(USE lbl);
 9837 
 9838   ins_cost(BRANCH_COST);
 9839   format %{ "b$cmp   $op1, zr, $lbl\t#@cmpP_narrowOop_imm0_branch" %}
 9840 
 9841   ins_encode %{
 9842     __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
 9843   %}
 9844 
 9845   ins_pipe(pipe_cmpz_branch);
 9846   ins_short_branch(1);
 9847 %}
 9848 
 9849 // Patterns for far (20KiB) variants
 9850 
 9851 instruct far_cmpFlag_branch(cmpOp cmp, rFlagsReg cr, label lbl) %{
 9852   match(If cmp cr);
 9853   effect(USE lbl);
 9854 
 9855   ins_cost(BRANCH_COST);
 9856   format %{ "far_b$cmp $cr, zr, $lbl\t#@far_cmpFlag_branch"%}
 9857 
 9858   ins_encode %{
 9859     __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($cr$$reg), *($lbl$$label), /* is_far */ true);
 9860   %}
 9861 
 9862   ins_pipe(pipe_cmpz_branch);
 9863 %}
 9864 
 9865 // Compare signed int and branch far instructions
 9866 instruct far_cmpI_branch(cmpOp cmp, iRegI op1, iRegI op2, label lbl) %{
 9867   match(If cmp (CmpI op1 op2));
 9868   effect(USE lbl);
 9869 
 9870   ins_cost(BRANCH_COST * 2);
 9871 
 9872   // the format instruction [far_b$cmp] here is be used as two insructions
 9873   // in macroassembler: b$not_cmp(op1, op2, done), j($lbl), bind(done)
 9874   format %{ "far_b$cmp  $op1, $op2, $lbl\t#@far_cmpI_branch" %}
 9875 
 9876   ins_encode %{
 9877     __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
 9878   %}
 9879 
 9880   ins_pipe(pipe_cmp_branch);
 9881 %}
 9882 
 9883 instruct far_cmpI_loop(cmpOp cmp, iRegI op1, iRegI op2, label lbl) %{
 9884   match(CountedLoopEnd cmp (CmpI op1 op2));
 9885   effect(USE lbl);
 9886 
 9887   ins_cost(BRANCH_COST * 2);
 9888   format %{ "far_b$cmp  $op1, $op2, $lbl\t#@far_cmpI_loop" %}
 9889 
 9890   ins_encode %{
 9891     __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
 9892   %}
 9893 
 9894   ins_pipe(pipe_cmp_branch);
 9895 %}
 9896 
 9897 instruct far_cmpU_branch(cmpOpU cmp, iRegI op1, iRegI op2, label lbl) %{
 9898   match(If cmp (CmpU op1 op2));
 9899   effect(USE lbl);
 9900 
 9901   ins_cost(BRANCH_COST * 2);
 9902   format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpU_branch" %}
 9903 
 9904   ins_encode %{
 9905     __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
 9906                        as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
 9907   %}
 9908 
 9909   ins_pipe(pipe_cmp_branch);
 9910 %}
 9911 
 9912 instruct far_cmpL_branch(cmpOp cmp, iRegL op1, iRegL op2, label lbl) %{
 9913   match(If cmp (CmpL op1 op2));
 9914   effect(USE lbl);
 9915 
 9916   ins_cost(BRANCH_COST * 2);
 9917   format %{ "far_b$cmp  $op1, $op2, $lbl\t#@far_cmpL_branch" %}
 9918 
 9919   ins_encode %{
 9920     __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
 9921   %}
 9922 
 9923   ins_pipe(pipe_cmp_branch);
 9924 %}
 9925 
 9926 instruct far_cmpLloop(cmpOp cmp, iRegL op1, iRegL op2, label lbl) %{
 9927   match(CountedLoopEnd cmp (CmpL op1 op2));
 9928   effect(USE lbl);
 9929 
 9930   ins_cost(BRANCH_COST * 2);
 9931   format %{ "far_b$cmp  $op1, $op2, $lbl\t#@far_cmpL_loop" %}
 9932 
 9933   ins_encode %{
 9934     __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
 9935   %}
 9936 
 9937   ins_pipe(pipe_cmp_branch);
 9938 %}
 9939 
 9940 instruct far_cmpUL_branch(cmpOpU cmp, iRegL op1, iRegL op2, label lbl) %{
 9941   match(If cmp (CmpUL op1 op2));
 9942   effect(USE lbl);
 9943 
 9944   ins_cost(BRANCH_COST * 2);
 9945   format %{ "far_b$cmp  $op1, $op2, $lbl\t#@far_cmpUL_branch" %}
 9946 
 9947   ins_encode %{
 9948     __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
 9949                        as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
 9950   %}
 9951 
 9952   ins_pipe(pipe_cmp_branch);
 9953 %}
 9954 
 9955 instruct far_cmpP_branch(cmpOpU cmp, iRegP op1, iRegP op2, label lbl)
 9956 %{
 9957   match(If cmp (CmpP op1 op2));
 9958 
 9959   effect(USE lbl);
 9960 
 9961   ins_cost(BRANCH_COST * 2);
 9962 
 9963   format %{ "far_b$cmp  $op1, $op2, $lbl\t#@far_cmpP_branch" %}
 9964 
 9965   ins_encode %{
 9966     __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
 9967                        as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
 9968   %}
 9969 
 9970   ins_pipe(pipe_cmp_branch);
 9971 %}
 9972 
 9973 instruct far_cmpN_branch(cmpOpU cmp, iRegN op1, iRegN op2, label lbl)
 9974 %{
 9975   match(If cmp (CmpN op1 op2));
 9976 
 9977   effect(USE lbl);
 9978 
 9979   ins_cost(BRANCH_COST * 2);
 9980 
 9981   format %{ "far_b$cmp  $op1, $op2, $lbl\t#@far_cmpN_branch" %}
 9982 
 9983   ins_encode %{
 9984     __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
 9985                        as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
 9986   %}
 9987 
 9988   ins_pipe(pipe_cmp_branch);
 9989 %}
 9990 
 9991 // Float compare and branch instructions
 9992 instruct far_cmpF_branch(cmpOp cmp, fRegF op1, fRegF op2, label lbl)
 9993 %{
 9994   match(If cmp (CmpF op1 op2));
 9995 
 9996   effect(USE lbl);
 9997 
 9998   ins_cost(XFER_COST + BRANCH_COST * 2);
 9999   format %{ "far_float_b$cmp $op1, $op2, $lbl\t#@far_cmpF_branch"%}
10000 
10001   ins_encode %{
10002     __ float_cmp_branch($cmp$$cmpcode, as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg),
10003                         *($lbl$$label), /* is_far */ true);
10004   %}
10005 
10006   ins_pipe(pipe_class_compare);
10007 %}
10008 
10009 // Double compare and branch instructions
10010 instruct far_cmpD_branch(cmpOp cmp, fRegD op1, fRegD op2, label lbl)
10011 %{
10012   match(If cmp (CmpD op1 op2));
10013   effect(USE lbl);
10014 
10015   ins_cost(XFER_COST + BRANCH_COST * 2);
10016   format %{ "far_double_b$cmp $op1, $op2, $lbl\t#@far_cmpD_branch"%}
10017 
10018   ins_encode %{
10019     __ float_cmp_branch($cmp$$cmpcode | C2_MacroAssembler::double_branch_mask, as_FloatRegister($op1$$reg),
10020                         as_FloatRegister($op2$$reg), *($lbl$$label), /* is_far */ true);
10021   %}
10022 
10023   ins_pipe(pipe_class_compare);
10024 %}
10025 
10026 instruct far_cmpI_reg_imm0_branch(cmpOp cmp, iRegI op1, immI0 zero, label lbl)
10027 %{
10028   match(If cmp (CmpI op1 zero));
10029 
10030   effect(USE op1, USE lbl);
10031 
10032   ins_cost(BRANCH_COST * 2);
10033 
10034   format %{ "far_b$cmp  $op1, zr, $lbl\t#@far_cmpI_reg_imm0_branch" %}
10035 
10036   ins_encode %{
10037     __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label), /* is_far */ true);
10038   %}
10039 
10040   ins_pipe(pipe_cmpz_branch);
10041 %}
10042 
10043 instruct far_cmpI_reg_imm0_loop(cmpOp cmp, iRegI op1, immI0 zero, label lbl)
10044 %{
10045   match(CountedLoopEnd cmp (CmpI op1 zero));
10046 
10047   effect(USE op1, USE lbl);
10048 
10049   ins_cost(BRANCH_COST * 2);
10050 
10051   format %{ "far_b$cmp  $op1, zr, $lbl\t#@far_cmpI_reg_imm0_loop" %}
10052 
10053   ins_encode %{
10054     __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label), /* is_far */ true);
10055   %}
10056 
10057   ins_pipe(pipe_cmpz_branch);
10058 %}
10059 
10060 instruct far_cmpUEqNeLeGt_imm0_branch(cmpOpUEqNeLeGt cmp, iRegI op1, immI0 zero, label lbl)
10061 %{
10062   match(If cmp (CmpU op1 zero));
10063 
10064   effect(USE op1, USE lbl);
10065 
10066   ins_cost(BRANCH_COST * 2);
10067 
10068   format %{ "far_b$cmp  $op1, zr, $lbl\t#@far_cmpUEqNeLeGt_imm0_branch" %}
10069 
10070   ins_encode %{
10071     __ enc_cmpUEqNeLeGt_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
10072   %}
10073 
10074   ins_pipe(pipe_cmpz_branch);
10075 %}
10076 
10077 // compare lt/ge unsigned instructs has no short instruct with same match
10078 instruct far_cmpULtGe_reg_imm0_branch(cmpOpULtGe cmp, iRegI op1, immI0 zero, label lbl)
10079 %{
10080   match(If cmp (CmpU op1 zero));
10081 
10082   effect(USE op1, USE lbl);
10083 
10084   ins_cost(BRANCH_COST);
10085 
10086   format %{ "j  $lbl if $cmp == ge\t#@far_cmpULtGe_reg_imm0_branch" %}
10087 
10088   ins_encode(riscv_enc_far_cmpULtGe_imm0_branch(cmp, op1, lbl));
10089 
10090   ins_pipe(pipe_cmpz_branch);
10091 %}
10092 
10093 instruct far_cmpL_reg_imm0_branch(cmpOp cmp, iRegL op1, immL0 zero, label lbl)
10094 %{
10095   match(If cmp (CmpL op1 zero));
10096 
10097   effect(USE op1, USE lbl);
10098 
10099   ins_cost(BRANCH_COST * 2);
10100 
10101   format %{ "far_b$cmp  $op1, zr, $lbl\t#@far_cmpL_reg_imm0_branch" %}
10102 
10103   ins_encode %{
10104     __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label), /* is_far */ true);
10105   %}
10106 
10107   ins_pipe(pipe_cmpz_branch);
10108 %}
10109 
10110 instruct far_cmpL_reg_imm0_loop(cmpOp cmp, iRegL op1, immL0 zero, label lbl)
10111 %{
10112   match(CountedLoopEnd cmp (CmpL op1 zero));
10113 
10114   effect(USE op1, USE lbl);
10115 
10116   ins_cost(BRANCH_COST * 2);
10117 
10118   format %{ "far_b$cmp  $op1, zr, $lbl\t#@far_cmpL_reg_imm0_loop" %}
10119 
10120   ins_encode %{
10121     __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label), /* is_far */ true);
10122   %}
10123 
10124   ins_pipe(pipe_cmpz_branch);
10125 %}
10126 
10127 instruct far_cmpULEqNeLeGt_reg_imm0_branch(cmpOpUEqNeLeGt cmp, iRegL op1, immL0 zero, label lbl)
10128 %{
10129   match(If cmp (CmpUL op1 zero));
10130 
10131   effect(USE op1, USE lbl);
10132 
10133   ins_cost(BRANCH_COST * 2);
10134 
10135   format %{ "far_b$cmp  $op1, zr, $lbl\t#@far_cmpULEqNeLeGt_reg_imm0_branch" %}
10136 
10137   ins_encode %{
10138     __ enc_cmpUEqNeLeGt_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
10139   %}
10140 
10141   ins_pipe(pipe_cmpz_branch);
10142 %}
10143 
10144 // compare lt/ge unsigned instructs has no short instruct with same match
10145 instruct far_cmpULLtGe_reg_imm0_branch(cmpOpULtGe cmp, iRegL op1, immL0 zero, label lbl)
10146 %{
10147   match(If cmp (CmpUL op1 zero));
10148 
10149   effect(USE op1, USE lbl);
10150 
10151   ins_cost(BRANCH_COST);
10152 
10153   format %{ "j  $lbl if $cmp == ge\t#@far_cmpULLtGe_reg_imm0_branch" %}
10154 
10155   ins_encode(riscv_enc_far_cmpULtGe_imm0_branch(cmp, op1, lbl));
10156 
10157   ins_pipe(pipe_cmpz_branch);
10158 %}
10159 
10160 instruct far_cmpP_imm0_branch(cmpOpEqNe cmp, iRegP op1, immP0 zero, label lbl) %{
10161   match(If cmp (CmpP op1 zero));
10162   effect(USE lbl);
10163 
10164   ins_cost(BRANCH_COST * 2);
10165   format %{ "far_b$cmp   $op1, zr, $lbl\t#@far_cmpP_imm0_branch" %}
10166 
10167   ins_encode %{
10168     __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
10169   %}
10170 
10171   ins_pipe(pipe_cmpz_branch);
10172 %}
10173 
10174 instruct far_cmpN_imm0_branch(cmpOpEqNe cmp, iRegN op1, immN0 zero, label lbl) %{
10175   match(If cmp (CmpN op1 zero));
10176   effect(USE lbl);
10177 
10178   ins_cost(BRANCH_COST * 2);
10179 
10180   format %{ "far_b$cmp  $op1, zr, $lbl\t#@far_cmpN_imm0_branch" %}
10181 
10182   ins_encode %{
10183     __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
10184   %}
10185 
10186   ins_pipe(pipe_cmpz_branch);
10187 %}
10188 
10189 instruct far_cmpP_narrowOop_imm0_branch(cmpOpEqNe cmp, iRegN op1, immP0 zero, label lbl) %{
10190   match(If cmp (CmpP (DecodeN op1) zero));
10191   effect(USE lbl);
10192 
10193   ins_cost(BRANCH_COST * 2);
10194   format %{ "far_b$cmp   $op1, zr, $lbl\t#@far_cmpP_narrowOop_imm0_branch" %}
10195 
10196   ins_encode %{
10197     __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
10198   %}
10199 
10200   ins_pipe(pipe_cmpz_branch);
10201 %}
10202 
10203 // ============================================================================
10204 // Conditional Move Instructions
10205 
10206 // --------- CMoveI ---------
10207 
10208 instruct cmovI_cmpI(iRegINoSp dst, iRegI src, iRegI op1, iRegI op2, cmpOp cop) %{
10209   match(Set dst (CMoveI (Binary cop (CmpI op1 op2)) (Binary dst src)));
10210   ins_cost(ALU_COST + BRANCH_COST);
10211 
10212   format %{
10213     "CMoveI $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpI\n\t"
10214   %}
10215 
10216   ins_encode %{
10217     __ enc_cmove($cop$$cmpcode,
10218                  as_Register($op1$$reg), as_Register($op2$$reg),
10219                  as_Register($dst$$reg), as_Register($src$$reg));
10220   %}
10221 
10222   ins_pipe(pipe_class_compare);
10223 %}
10224 
10225 instruct cmovI_cmpU(iRegINoSp dst, iRegI src, iRegI op1, iRegI op2, cmpOpU cop) %{
10226   match(Set dst (CMoveI (Binary cop (CmpU op1 op2)) (Binary dst src)));
10227   ins_cost(ALU_COST + BRANCH_COST);
10228 
10229   format %{
10230     "CMoveI $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpU\n\t"
10231   %}
10232 
10233   ins_encode %{
10234     __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10235                  as_Register($op1$$reg), as_Register($op2$$reg),
10236                  as_Register($dst$$reg), as_Register($src$$reg));
10237   %}
10238 
10239   ins_pipe(pipe_class_compare);
10240 %}
10241 
10242 instruct cmovI_cmpL(iRegINoSp dst, iRegI src, iRegL op1, iRegL op2, cmpOp cop) %{
10243   match(Set dst (CMoveI (Binary cop (CmpL op1 op2)) (Binary dst src)));
10244   ins_cost(ALU_COST + BRANCH_COST);
10245 
10246   format %{
10247     "CMoveI $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpL\n\t"
10248   %}
10249 
10250   ins_encode %{
10251     __ enc_cmove($cop$$cmpcode,
10252                  as_Register($op1$$reg), as_Register($op2$$reg),
10253                  as_Register($dst$$reg), as_Register($src$$reg));
10254   %}
10255 
10256   ins_pipe(pipe_class_compare);
10257 %}
10258 
10259 instruct cmovI_cmpUL(iRegINoSp dst, iRegI src, iRegL op1, iRegL op2, cmpOpU cop) %{
10260   match(Set dst (CMoveI (Binary cop (CmpUL op1 op2)) (Binary dst src)));
10261   ins_cost(ALU_COST + BRANCH_COST);
10262 
10263   format %{
10264     "CMoveI $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpUL\n\t"
10265   %}
10266 
10267   ins_encode %{
10268     __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10269                  as_Register($op1$$reg), as_Register($op2$$reg),
10270                  as_Register($dst$$reg), as_Register($src$$reg));
10271   %}
10272 
10273   ins_pipe(pipe_class_compare);
10274 %}
10275 
10276 instruct cmovI_cmpF(iRegINoSp dst, iRegI src, fRegF op1, fRegF op2, cmpOp cop) %{
10277   match(Set dst (CMoveI (Binary cop (CmpF op1 op2)) (Binary dst src)));
10278   ins_cost(ALU_COST + BRANCH_COST);
10279 
10280   format %{
10281     "CMoveI $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpF\n\t"
10282   %}
10283 
10284   ins_encode %{
10285     __ enc_cmove_cmp_fp($cop$$cmpcode,
10286                         as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg),
10287                         as_Register($dst$$reg), as_Register($src$$reg), true /* is_single */);
10288   %}
10289 
10290   ins_pipe(pipe_class_compare);
10291 %}
10292 
10293 instruct cmovI_cmpD(iRegINoSp dst, iRegI src, fRegD op1, fRegD op2, cmpOp cop) %{
10294   match(Set dst (CMoveI (Binary cop (CmpD op1 op2)) (Binary dst src)));
10295   ins_cost(ALU_COST + BRANCH_COST);
10296 
10297   format %{
10298     "CMoveI $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpD\n\t"
10299   %}
10300 
10301   ins_encode %{
10302     __ enc_cmove_cmp_fp($cop$$cmpcode | C2_MacroAssembler::double_branch_mask,
10303                         as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg),
10304                         as_Register($dst$$reg), as_Register($src$$reg), false /* is_single */);
10305   %}
10306 
10307   ins_pipe(pipe_class_compare);
10308 %}
10309 
10310 instruct cmovI_cmpN(iRegINoSp dst, iRegI src, iRegN op1, iRegN op2, cmpOpU cop) %{
10311   match(Set dst (CMoveI (Binary cop (CmpN op1 op2)) (Binary dst src)));
10312   ins_cost(ALU_COST + BRANCH_COST);
10313 
10314   format %{
10315     "CMoveI $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpN\n\t"
10316   %}
10317 
10318   ins_encode %{
10319     __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10320                  as_Register($op1$$reg), as_Register($op2$$reg),
10321                  as_Register($dst$$reg), as_Register($src$$reg));
10322   %}
10323 
10324   ins_pipe(pipe_class_compare);
10325 %}
10326 
10327 instruct cmovI_cmpP(iRegINoSp dst, iRegI src, iRegP op1, iRegP op2, cmpOpU cop) %{
10328   match(Set dst (CMoveI (Binary cop (CmpP op1 op2)) (Binary dst src)));
10329   ins_cost(ALU_COST + BRANCH_COST);
10330 
10331   format %{
10332     "CMoveI $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpP\n\t"
10333   %}
10334 
10335   ins_encode %{
10336     __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10337                  as_Register($op1$$reg), as_Register($op2$$reg),
10338                  as_Register($dst$$reg), as_Register($src$$reg));
10339   %}
10340 
10341   ins_pipe(pipe_class_compare);
10342 %}
10343 
10344 // --------- CMoveL ---------
10345 
10346 instruct cmovL_cmpL(iRegLNoSp dst, iRegL src, iRegL op1, iRegL op2, cmpOp cop) %{
10347   match(Set dst (CMoveL (Binary cop (CmpL op1 op2)) (Binary dst src)));
10348   ins_cost(ALU_COST + BRANCH_COST);
10349 
10350   format %{
10351     "CMoveL $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpL\n\t"
10352   %}
10353 
10354   ins_encode %{
10355     __ enc_cmove($cop$$cmpcode,
10356                  as_Register($op1$$reg), as_Register($op2$$reg),
10357                  as_Register($dst$$reg), as_Register($src$$reg));
10358   %}
10359 
10360   ins_pipe(pipe_class_compare);
10361 %}
10362 
10363 instruct cmovL_cmpUL(iRegLNoSp dst, iRegL src, iRegL op1, iRegL op2, cmpOpU cop) %{
10364   match(Set dst (CMoveL (Binary cop (CmpUL op1 op2)) (Binary dst src)));
10365   ins_cost(ALU_COST + BRANCH_COST);
10366 
10367   format %{
10368     "CMoveL $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpUL\n\t"
10369   %}
10370 
10371   ins_encode %{
10372     __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10373                  as_Register($op1$$reg), as_Register($op2$$reg),
10374                  as_Register($dst$$reg), as_Register($src$$reg));
10375   %}
10376 
10377   ins_pipe(pipe_class_compare);
10378 %}
10379 
10380 instruct cmovL_cmpI(iRegLNoSp dst, iRegL src, iRegI op1, iRegI op2, cmpOp cop) %{
10381   match(Set dst (CMoveL (Binary cop (CmpI op1 op2)) (Binary dst src)));
10382   ins_cost(ALU_COST + BRANCH_COST);
10383 
10384   format %{
10385     "CMoveL $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpI\n\t"
10386   %}
10387 
10388   ins_encode %{
10389     __ enc_cmove($cop$$cmpcode,
10390                  as_Register($op1$$reg), as_Register($op2$$reg),
10391                  as_Register($dst$$reg), as_Register($src$$reg));
10392   %}
10393 
10394   ins_pipe(pipe_class_compare);
10395 %}
10396 
10397 instruct cmovL_cmpU(iRegLNoSp dst, iRegL src, iRegI op1, iRegI op2, cmpOpU cop) %{
10398   match(Set dst (CMoveL (Binary cop (CmpU op1 op2)) (Binary dst src)));
10399   ins_cost(ALU_COST + BRANCH_COST);
10400 
10401   format %{
10402     "CMoveL $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpU\n\t"
10403   %}
10404 
10405   ins_encode %{
10406     __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10407                  as_Register($op1$$reg), as_Register($op2$$reg),
10408                  as_Register($dst$$reg), as_Register($src$$reg));
10409   %}
10410 
10411   ins_pipe(pipe_class_compare);
10412 %}
10413 
10414 instruct cmovL_cmpF(iRegLNoSp dst, iRegL src, fRegF op1, fRegF op2, cmpOp cop) %{
10415   match(Set dst (CMoveL (Binary cop (CmpF op1 op2)) (Binary dst src)));
10416   ins_cost(ALU_COST + BRANCH_COST);
10417 
10418   format %{
10419     "CMoveL $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpF\n\t"
10420   %}
10421 
10422   ins_encode %{
10423     __ enc_cmove_cmp_fp($cop$$cmpcode,
10424                         as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg),
10425                         as_Register($dst$$reg), as_Register($src$$reg), true /* is_single */);
10426   %}
10427 
10428   ins_pipe(pipe_class_compare);
10429 %}
10430 
10431 instruct cmovL_cmpD(iRegLNoSp dst, iRegL src, fRegD op1, fRegD op2, cmpOp cop) %{
10432   match(Set dst (CMoveL (Binary cop (CmpD op1 op2)) (Binary dst src)));
10433   ins_cost(ALU_COST + BRANCH_COST);
10434 
10435   format %{
10436     "CMoveL $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpD\n\t"
10437   %}
10438 
10439   ins_encode %{
10440     __ enc_cmove_cmp_fp($cop$$cmpcode | C2_MacroAssembler::double_branch_mask,
10441                         as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg),
10442                         as_Register($dst$$reg), as_Register($src$$reg), false /* is_single */);
10443   %}
10444 
10445   ins_pipe(pipe_class_compare);
10446 %}
10447 
10448 instruct cmovL_cmpN(iRegLNoSp dst, iRegL src, iRegN op1, iRegN op2, cmpOpU cop) %{
10449   match(Set dst (CMoveL (Binary cop (CmpN op1 op2)) (Binary dst src)));
10450   ins_cost(ALU_COST + BRANCH_COST);
10451 
10452   format %{
10453     "CMoveL $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpN\n\t"
10454   %}
10455 
10456   ins_encode %{
10457     __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10458                  as_Register($op1$$reg), as_Register($op2$$reg),
10459                  as_Register($dst$$reg), as_Register($src$$reg));
10460   %}
10461 
10462   ins_pipe(pipe_class_compare);
10463 %}
10464 
10465 instruct cmovL_cmpP(iRegLNoSp dst, iRegL src, iRegP op1, iRegP op2, cmpOpU cop) %{
10466   match(Set dst (CMoveL (Binary cop (CmpP op1 op2)) (Binary dst src)));
10467   ins_cost(ALU_COST + BRANCH_COST);
10468 
10469   format %{
10470     "CMoveL $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpP\n\t"
10471   %}
10472 
10473   ins_encode %{
10474     __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10475                  as_Register($op1$$reg), as_Register($op2$$reg),
10476                  as_Register($dst$$reg), as_Register($src$$reg));
10477   %}
10478 
10479   ins_pipe(pipe_class_compare);
10480 %}
10481 
10482 // ============================================================================
10483 // Procedure Call/Return Instructions
10484 
10485 // Call Java Static Instruction
10486 // Note: If this code changes, the corresponding ret_addr_offset() and
10487 //       compute_padding() functions will have to be adjusted.
10488 instruct CallStaticJavaDirect(method meth)
10489 %{
10490   match(CallStaticJava);
10491 
10492   effect(USE meth);
10493 
10494   ins_cost(BRANCH_COST);
10495 
10496   format %{ "CALL,static $meth\t#@CallStaticJavaDirect" %}
10497 
10498   ins_encode(riscv_enc_java_static_call(meth),
10499              riscv_enc_call_epilog);
10500 
10501   ins_pipe(pipe_class_call);
10502   ins_alignment(4);
10503 %}
10504 
10505 // TO HERE
10506 
10507 // Call Java Dynamic Instruction
10508 // Note: If this code changes, the corresponding ret_addr_offset() and
10509 //       compute_padding() functions will have to be adjusted.
10510 instruct CallDynamicJavaDirect(method meth)
10511 %{
10512   match(CallDynamicJava);
10513 
10514   effect(USE meth);
10515 
10516   ins_cost(BRANCH_COST + ALU_COST * 5);
10517 
10518   format %{ "CALL,dynamic $meth\t#@CallDynamicJavaDirect" %}
10519 
10520   ins_encode(riscv_enc_java_dynamic_call(meth),
10521              riscv_enc_call_epilog);
10522 
10523   ins_pipe(pipe_class_call);
10524   ins_alignment(4);
10525 %}
10526 
10527 // Call Runtime Instruction
10528 
10529 instruct CallRuntimeDirect(method meth)
10530 %{
10531   match(CallRuntime);
10532 
10533   effect(USE meth);
10534 
10535   ins_cost(BRANCH_COST);
10536 
10537   format %{ "CALL, runtime $meth\t#@CallRuntimeDirect" %}
10538 
10539   ins_encode(riscv_enc_java_to_runtime(meth));
10540 
10541   ins_pipe(pipe_class_call);
10542 %}
10543 
10544 // Call Runtime Instruction
10545 
10546 instruct CallLeafDirect(method meth)
10547 %{
10548   match(CallLeaf);
10549 
10550   effect(USE meth);
10551 
10552   ins_cost(BRANCH_COST);
10553 
10554   format %{ "CALL, runtime leaf $meth\t#@CallLeafDirect" %}
10555 
10556   ins_encode(riscv_enc_java_to_runtime(meth));
10557 
10558   ins_pipe(pipe_class_call);
10559 %}
10560 
10561 // Call Runtime Instruction without safepoint and with vector arguments
10562 
10563 instruct CallLeafDirectVector(method meth)
10564 %{
10565   match(CallLeafVector);
10566 
10567   effect(USE meth);
10568 
10569   ins_cost(BRANCH_COST);
10570 
10571   format %{ "CALL, runtime leaf vector $meth" %}
10572 
10573   ins_encode(riscv_enc_java_to_runtime(meth));
10574 
10575   ins_pipe(pipe_class_call);
10576 %}
10577 
10578 // Call Runtime Instruction
10579 
10580 instruct CallLeafNoFPDirect(method meth)
10581 %{
10582   match(CallLeafNoFP);
10583 
10584   effect(USE meth);
10585 
10586   ins_cost(BRANCH_COST);
10587 
10588   format %{ "CALL, runtime leaf nofp $meth\t#@CallLeafNoFPDirect" %}
10589 
10590   ins_encode(riscv_enc_java_to_runtime(meth));
10591 
10592   ins_pipe(pipe_class_call);
10593 %}
10594 
10595 // ============================================================================
10596 // Partial Subtype Check
10597 //
10598 // superklass array for an instance of the superklass.  Set a hidden
10599 // internal cache on a hit (cache is checked with exposed code in
10600 // gen_subtype_check()).  Return zero for a hit.  The encoding
10601 // ALSO sets flags.
10602 
10603 instruct partialSubtypeCheck(iRegP_R15 result, iRegP_R14 sub, iRegP_R10 super, iRegP_R12 tmp, rFlagsReg cr)
10604 %{
10605   predicate(!UseSecondarySupersTable);
10606   match(Set result (PartialSubtypeCheck sub super));
10607   effect(KILL tmp, KILL cr);
10608 
10609   ins_cost(20 * DEFAULT_COST);
10610   format %{ "partialSubtypeCheck $result, $sub, $super\t#@partialSubtypeCheck" %}
10611 
10612   ins_encode(riscv_enc_partial_subtype_check(sub, super, tmp, result));
10613 
10614   opcode(0x1); // Force zero of result reg on hit
10615 
10616   ins_pipe(pipe_class_memory);
10617 %}
10618 
10619 // Two versions of partialSubtypeCheck, both used when we need to
10620 // search for a super class in the secondary supers array. The first
10621 // is used when we don't know _a priori_ the class being searched
10622 // for. The second, far more common, is used when we do know: this is
10623 // used for instanceof, checkcast, and any case where C2 can determine
10624 // it by constant propagation.
10625 
10626 instruct partialSubtypeCheckVarSuper(iRegP_R14 sub, iRegP_R10 super, iRegP_R15 result,
10627                                      iRegP_R11 tmpR11, iRegP_R12 tmpR12, iRegP_R13 tmpR13,
10628                                      iRegP_R16 tmpR16, rFlagsReg cr)
10629 %{
10630   predicate(UseSecondarySupersTable);
10631   match(Set result (PartialSubtypeCheck sub super));
10632   effect(TEMP tmpR11, TEMP tmpR12, TEMP tmpR13, TEMP tmpR16, KILL cr);
10633 
10634   ins_cost(10 * DEFAULT_COST);  // slightly larger than the next version
10635   format %{ "partialSubtypeCheck $result, $sub, $super" %}
10636 
10637   ins_encode %{
10638     __ lookup_secondary_supers_table_var($sub$$Register, $super$$Register, $result$$Register,
10639                                          $tmpR11$$Register, $tmpR12$$Register, $tmpR13$$Register,
10640                                          $tmpR16$$Register, nullptr /*L_success*/);
10641   %}
10642 
10643   ins_pipe(pipe_class_memory);
10644 %}
10645 
10646 instruct partialSubtypeCheckConstSuper(iRegP_R14 sub, iRegP_R10 super_reg, immP super_con, iRegP_R15 result,
10647                                        iRegP_R11 tmpR11, iRegP_R12 tmpR12, iRegP_R13 tmpR13, iRegP_R16 tmpR16, rFlagsReg cr)
10648 %{
10649   predicate(UseSecondarySupersTable);
10650   match(Set result (PartialSubtypeCheck sub (Binary super_reg super_con)));
10651   effect(TEMP tmpR11, TEMP tmpR12, TEMP tmpR13, TEMP tmpR16, KILL cr);
10652 
10653   ins_cost(5 * DEFAULT_COST); // needs to be less than competing nodes
10654   format %{ "partialSubtypeCheck $result, $sub, $super_reg, $super_con" %}
10655 
10656   ins_encode %{
10657     bool success = false;
10658     u1 super_klass_slot = ((Klass*)$super_con$$constant)->hash_slot();
10659     if (InlineSecondarySupersTest) {
10660       success = __ lookup_secondary_supers_table_const($sub$$Register, $super_reg$$Register, $result$$Register,
10661                                                        $tmpR11$$Register, $tmpR12$$Register, $tmpR13$$Register,
10662                                                        $tmpR16$$Register, super_klass_slot);
10663     } else {
10664       address call = __ reloc_call(RuntimeAddress(StubRoutines::lookup_secondary_supers_table_stub(super_klass_slot)));
10665       success = (call != nullptr);
10666     }
10667     if (!success) {
10668       ciEnv::current()->record_failure("CodeCache is full");
10669       return;
10670     }
10671   %}
10672 
10673   ins_pipe(pipe_class_memory);
10674 %}
10675 
10676 instruct string_compareU(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
10677                          iRegI_R10 result, iRegP_R28 tmp1, iRegL_R29 tmp2, iRegL_R30 tmp3, rFlagsReg cr)
10678 %{
10679   predicate(!UseRVV && ((StrCompNode *)n)->encoding() == StrIntrinsicNode::UU);
10680   match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10681   effect(KILL tmp1, KILL tmp2, KILL tmp3, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
10682 
10683   format %{ "String Compare $str1, $cnt1, $str2, $cnt2 -> $result\t#@string_compareU" %}
10684   ins_encode %{
10685     // Count is in 8-bit bytes; non-Compact chars are 16 bits.
10686     __ string_compare($str1$$Register, $str2$$Register,
10687                       $cnt1$$Register, $cnt2$$Register, $result$$Register,
10688                       $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
10689                       StrIntrinsicNode::UU);
10690   %}
10691   ins_pipe(pipe_class_memory);
10692 %}
10693 
10694 instruct string_compareL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
10695                          iRegI_R10 result, iRegP_R28 tmp1, iRegL_R29 tmp2, iRegL_R30 tmp3, rFlagsReg cr)
10696 %{
10697   predicate(!UseRVV && ((StrCompNode *)n)->encoding() == StrIntrinsicNode::LL);
10698   match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10699   effect(KILL tmp1, KILL tmp2, KILL tmp3, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
10700 
10701   format %{ "String Compare $str1, $cnt1, $str2, $cnt2 -> $result\t#@string_compareL" %}
10702   ins_encode %{
10703     __ string_compare($str1$$Register, $str2$$Register,
10704                       $cnt1$$Register, $cnt2$$Register, $result$$Register,
10705                       $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
10706                       StrIntrinsicNode::LL);
10707   %}
10708   ins_pipe(pipe_class_memory);
10709 %}
10710 
10711 instruct string_compareUL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
10712                           iRegI_R10 result, iRegP_R28 tmp1, iRegL_R29 tmp2, iRegL_R30 tmp3, rFlagsReg cr)
10713 %{
10714   predicate(!UseRVV && ((StrCompNode *)n)->encoding() == StrIntrinsicNode::UL);
10715   match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10716   effect(KILL tmp1, KILL tmp2, KILL tmp3, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
10717 
10718   format %{"String Compare $str1, $cnt1, $str2, $cnt2 -> $result\t#@string_compareUL" %}
10719   ins_encode %{
10720     __ string_compare($str1$$Register, $str2$$Register,
10721                       $cnt1$$Register, $cnt2$$Register, $result$$Register,
10722                       $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
10723                       StrIntrinsicNode::UL);
10724   %}
10725   ins_pipe(pipe_class_memory);
10726 %}
10727 
10728 instruct string_compareLU(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
10729                           iRegI_R10 result, iRegP_R28 tmp1, iRegL_R29 tmp2, iRegL_R30 tmp3,
10730                           rFlagsReg cr)
10731 %{
10732   predicate(!UseRVV && ((StrCompNode *)n)->encoding() == StrIntrinsicNode::LU);
10733   match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10734   effect(KILL tmp1, KILL tmp2, KILL tmp3, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
10735 
10736   format %{ "String Compare $str1, $cnt1, $str2, $cnt2 -> $result\t#@string_compareLU" %}
10737   ins_encode %{
10738     __ string_compare($str1$$Register, $str2$$Register,
10739                       $cnt1$$Register, $cnt2$$Register, $result$$Register,
10740                       $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
10741                       StrIntrinsicNode::LU);
10742   %}
10743   ins_pipe(pipe_class_memory);
10744 %}
10745 
10746 instruct string_indexofUU(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
10747                           iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3,
10748                           iRegINoSp tmp4, iRegINoSp tmp5, iRegINoSp tmp6, rFlagsReg cr)
10749 %{
10750   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU);
10751   match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
10752   effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, TEMP_DEF result,
10753          TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, TEMP tmp6, KILL cr);
10754 
10755   format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result (UU)" %}
10756   ins_encode %{
10757     __ string_indexof($str1$$Register, $str2$$Register,
10758                       $cnt1$$Register, $cnt2$$Register,
10759                       $tmp1$$Register, $tmp2$$Register,
10760                       $tmp3$$Register, $tmp4$$Register,
10761                       $tmp5$$Register, $tmp6$$Register,
10762                       $result$$Register, StrIntrinsicNode::UU);
10763   %}
10764   ins_pipe(pipe_class_memory);
10765 %}
10766 
10767 instruct string_indexofLL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
10768                           iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3,
10769                           iRegINoSp tmp4, iRegINoSp tmp5, iRegINoSp tmp6, rFlagsReg cr)
10770 %{
10771   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL);
10772   match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
10773   effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, TEMP_DEF result,
10774          TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, TEMP tmp6, KILL cr);
10775 
10776   format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result (LL)" %}
10777   ins_encode %{
10778     __ string_indexof($str1$$Register, $str2$$Register,
10779                       $cnt1$$Register, $cnt2$$Register,
10780                       $tmp1$$Register, $tmp2$$Register,
10781                       $tmp3$$Register, $tmp4$$Register,
10782                       $tmp5$$Register, $tmp6$$Register,
10783                       $result$$Register, StrIntrinsicNode::LL);
10784   %}
10785   ins_pipe(pipe_class_memory);
10786 %}
10787 
10788 instruct string_indexofUL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
10789                           iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3,
10790                           iRegINoSp tmp4, iRegINoSp tmp5, iRegINoSp tmp6, rFlagsReg cr)
10791 %{
10792   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL);
10793   match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
10794   effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, TEMP_DEF result,
10795          TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, TEMP tmp6, KILL cr);
10796   format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result (UL)" %}
10797 
10798   ins_encode %{
10799     __ string_indexof($str1$$Register, $str2$$Register,
10800                       $cnt1$$Register, $cnt2$$Register,
10801                       $tmp1$$Register, $tmp2$$Register,
10802                       $tmp3$$Register, $tmp4$$Register,
10803                       $tmp5$$Register, $tmp6$$Register,
10804                       $result$$Register, StrIntrinsicNode::UL);
10805   %}
10806   ins_pipe(pipe_class_memory);
10807 %}
10808 
10809 instruct string_indexof_conUU(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2,
10810                               immI_le_4 int_cnt2, iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2,
10811                               iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
10812 %{
10813   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU);
10814   match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
10815   effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, TEMP_DEF result,
10816          TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
10817 
10818   format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result (UU)" %}
10819 
10820   ins_encode %{
10821     int icnt2 = (int)$int_cnt2$$constant;
10822     __ string_indexof_linearscan($str1$$Register, $str2$$Register,
10823                                  $cnt1$$Register, zr,
10824                                  $tmp1$$Register, $tmp2$$Register,
10825                                  $tmp3$$Register, $tmp4$$Register,
10826                                  icnt2, $result$$Register, StrIntrinsicNode::UU);
10827   %}
10828   ins_pipe(pipe_class_memory);
10829 %}
10830 
10831 instruct string_indexof_conLL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2,
10832                               immI_le_4 int_cnt2, iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2,
10833                               iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
10834 %{
10835   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL);
10836   match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
10837   effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, TEMP_DEF result,
10838          TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
10839 
10840   format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result (LL)" %}
10841   ins_encode %{
10842     int icnt2 = (int)$int_cnt2$$constant;
10843     __ string_indexof_linearscan($str1$$Register, $str2$$Register,
10844                                  $cnt1$$Register, zr,
10845                                  $tmp1$$Register, $tmp2$$Register,
10846                                  $tmp3$$Register, $tmp4$$Register,
10847                                  icnt2, $result$$Register, StrIntrinsicNode::LL);
10848   %}
10849   ins_pipe(pipe_class_memory);
10850 %}
10851 
10852 instruct string_indexof_conUL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2,
10853                               immI_1 int_cnt2, iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2,
10854                               iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
10855 %{
10856   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL);
10857   match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
10858   effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, TEMP_DEF result,
10859          TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
10860 
10861   format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result (UL)" %}
10862   ins_encode %{
10863     int icnt2 = (int)$int_cnt2$$constant;
10864     __ string_indexof_linearscan($str1$$Register, $str2$$Register,
10865                                  $cnt1$$Register, zr,
10866                                  $tmp1$$Register, $tmp2$$Register,
10867                                  $tmp3$$Register, $tmp4$$Register,
10868                                  icnt2, $result$$Register, StrIntrinsicNode::UL);
10869   %}
10870   ins_pipe(pipe_class_memory);
10871 %}
10872 
10873 instruct stringU_indexof_char(iRegP_R11 str1, iRegI_R12 cnt1, iRegI_R13 ch,
10874                               iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2,
10875                               iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
10876 %{
10877   match(Set result (StrIndexOfChar (Binary str1 cnt1) ch));
10878   predicate(!UseRVV && (((StrIndexOfCharNode*)n)->encoding() == StrIntrinsicNode::U));
10879   effect(USE_KILL str1, USE_KILL cnt1, USE_KILL ch, TEMP_DEF result,
10880          TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
10881 
10882   format %{ "StringUTF16 IndexOf char[] $str1, $cnt1, $ch -> $result" %}
10883   ins_encode %{
10884     __ string_indexof_char($str1$$Register, $cnt1$$Register, $ch$$Register,
10885                            $result$$Register, $tmp1$$Register, $tmp2$$Register,
10886                            $tmp3$$Register, $tmp4$$Register, false /* isU */);
10887   %}
10888   ins_pipe(pipe_class_memory);
10889 %}
10890 
10891 
10892 instruct stringL_indexof_char(iRegP_R11 str1, iRegI_R12 cnt1, iRegI_R13 ch,
10893                               iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2,
10894                               iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
10895 %{
10896   match(Set result (StrIndexOfChar (Binary str1 cnt1) ch));
10897   predicate(!UseRVV && (((StrIndexOfCharNode*)n)->encoding() == StrIntrinsicNode::L));
10898   effect(USE_KILL str1, USE_KILL cnt1, USE_KILL ch, TEMP_DEF result,
10899          TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
10900 
10901   format %{ "StringLatin1 IndexOf char[] $str1, $cnt1, $ch -> $result" %}
10902   ins_encode %{
10903     __ string_indexof_char($str1$$Register, $cnt1$$Register, $ch$$Register,
10904                            $result$$Register, $tmp1$$Register, $tmp2$$Register,
10905                            $tmp3$$Register, $tmp4$$Register, true /* isL */);
10906   %}
10907   ins_pipe(pipe_class_memory);
10908 %}
10909 
10910 // clearing of an array
10911 instruct clearArray_reg_reg(iRegL_R29 cnt, iRegP_R28 base, iRegP_R30 tmp1,
10912                             iRegP_R31 tmp2, rFlagsReg cr, Universe dummy)
10913 %{
10914   // temp registers must match the one used in StubGenerator::generate_zero_blocks()
10915   predicate(UseBlockZeroing || !UseRVV);
10916   match(Set dummy (ClearArray cnt base));
10917   effect(USE_KILL cnt, USE_KILL base, TEMP tmp1, TEMP tmp2, KILL cr);
10918 
10919   ins_cost(4 * DEFAULT_COST);
10920   format %{ "ClearArray $cnt, $base\t#@clearArray_reg_reg" %}
10921 
10922   ins_encode %{
10923     address tpc = __ zero_words($base$$Register, $cnt$$Register);
10924     if (tpc == nullptr) {
10925       ciEnv::current()->record_failure("CodeCache is full");
10926       return;
10927     }
10928   %}
10929 
10930   ins_pipe(pipe_class_memory);
10931 %}
10932 
10933 instruct clearArray_imm_reg(immL cnt, iRegP_R28 base, Universe dummy, rFlagsReg cr)
10934 %{
10935   predicate(!UseRVV && (uint64_t)n->in(2)->get_long()
10936             < (uint64_t)(BlockZeroingLowLimit >> LogBytesPerWord));
10937   match(Set dummy (ClearArray cnt base));
10938   effect(USE_KILL base, KILL cr);
10939 
10940   ins_cost(4 * DEFAULT_COST);
10941   format %{ "ClearArray $cnt, $base\t#@clearArray_imm_reg" %}
10942 
10943   ins_encode %{
10944     __ zero_words($base$$Register, (uint64_t)$cnt$$constant);
10945   %}
10946 
10947   ins_pipe(pipe_class_memory);
10948 %}
10949 
10950 instruct string_equalsL(iRegP_R11 str1, iRegP_R13 str2, iRegI_R14 cnt,
10951                         iRegI_R10 result, rFlagsReg cr)
10952 %{
10953   predicate(!UseRVV && ((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::LL);
10954   match(Set result (StrEquals (Binary str1 str2) cnt));
10955   effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL cr);
10956 
10957   format %{ "String Equals $str1, $str2, $cnt -> $result\t#@string_equalsL" %}
10958   ins_encode %{
10959     // Count is in 8-bit bytes; non-Compact chars are 16 bits.
10960     __ string_equals($str1$$Register, $str2$$Register,
10961                      $result$$Register, $cnt$$Register);
10962   %}
10963   ins_pipe(pipe_class_memory);
10964 %}
10965 
10966 instruct array_equalsB(iRegP_R11 ary1, iRegP_R12 ary2, iRegI_R10 result,
10967                        iRegP_R13 tmp1, iRegP_R14 tmp2, iRegP_R15 tmp3)
10968 %{
10969   predicate(!UseRVV && ((AryEqNode*)n)->encoding() == StrIntrinsicNode::LL);
10970   match(Set result (AryEq ary1 ary2));
10971   effect(USE_KILL ary1, USE_KILL ary2, TEMP tmp1, TEMP tmp2, TEMP tmp3);
10972 
10973   format %{ "Array Equals $ary1, $ary2 -> $result\t#@array_equalsB // KILL all" %}
10974   ins_encode %{
10975     __ arrays_equals($ary1$$Register, $ary2$$Register,
10976                      $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
10977                      $result$$Register, 1);
10978   %}
10979   ins_pipe(pipe_class_memory);
10980 %}
10981 
10982 instruct array_equalsC(iRegP_R11 ary1, iRegP_R12 ary2, iRegI_R10 result,
10983                        iRegP_R13 tmp1, iRegP_R14 tmp2, iRegP_R15 tmp3)
10984 %{
10985   predicate(!UseRVV && ((AryEqNode*)n)->encoding() == StrIntrinsicNode::UU);
10986   match(Set result (AryEq ary1 ary2));
10987   effect(USE_KILL ary1, USE_KILL ary2, TEMP tmp1, TEMP tmp2, TEMP tmp3);
10988 
10989   format %{ "Array Equals $ary1, $ary2 -> $result\t#@array_equalsC // KILL all" %}
10990   ins_encode %{
10991     __ arrays_equals($ary1$$Register, $ary2$$Register,
10992                      $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
10993                      $result$$Register, 2);
10994   %}
10995   ins_pipe(pipe_class_memory);
10996 %}
10997 
10998 // fast ArraysSupport.vectorizedHashCode
10999 instruct arrays_hashcode(iRegP_R11 ary, iRegI_R12 cnt, iRegI_R10 result, immI basic_type,
11000                          iRegLNoSp tmp1, iRegLNoSp tmp2,
11001                          iRegLNoSp tmp3, iRegLNoSp tmp4,
11002                          iRegLNoSp tmp5, iRegLNoSp tmp6, rFlagsReg cr)
11003 %{
11004   match(Set result (VectorizedHashCode (Binary ary cnt) (Binary result basic_type)));
11005   effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, TEMP tmp6,
11006          USE_KILL ary, USE_KILL cnt, USE basic_type, KILL cr);
11007 
11008   format %{ "Array HashCode array[] $ary,$cnt,$result,$basic_type -> $result   // KILL all" %}
11009   ins_encode %{
11010     __ arrays_hashcode($ary$$Register, $cnt$$Register, $result$$Register,
11011                        $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
11012                        $tmp4$$Register, $tmp5$$Register, $tmp6$$Register,
11013                        (BasicType)$basic_type$$constant);
11014   %}
11015   ins_pipe(pipe_class_memory);
11016 %}
11017 
11018 // ============================================================================
11019 // Safepoint Instructions
11020 
11021 instruct safePoint(iRegP poll)
11022 %{
11023   match(SafePoint poll);
11024 
11025   ins_cost(2 * LOAD_COST);
11026   format %{
11027     "lwu zr, [$poll]\t# Safepoint: poll for GC, #@safePoint"
11028   %}
11029   ins_encode %{
11030     __ read_polling_page(as_Register($poll$$reg), 0, relocInfo::poll_type);
11031   %}
11032   ins_pipe(pipe_serial); // ins_pipe(iload_reg_mem);
11033 %}
11034 
11035 // ============================================================================
11036 // This name is KNOWN by the ADLC and cannot be changed.
11037 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
11038 // for this guy.
11039 instruct tlsLoadP(javaThread_RegP dst)
11040 %{
11041   match(Set dst (ThreadLocal));
11042 
11043   ins_cost(0);
11044 
11045   format %{ " -- \t// $dst=Thread::current(), empty, #@tlsLoadP" %}
11046 
11047   size(0);
11048 
11049   ins_encode( /*empty*/ );
11050 
11051   ins_pipe(pipe_class_empty);
11052 %}
11053 
11054 // inlined locking and unlocking
11055 // using t1 as the 'flag' register to bridge the BoolNode producers and consumers
11056 instruct cmpFastLock(rFlagsReg cr, iRegP object, iRegP box,
11057                      iRegPNoSp tmp1, iRegPNoSp tmp2, iRegPNoSp tmp3, iRegPNoSp tmp4)
11058 %{
11059   predicate(LockingMode != LM_LIGHTWEIGHT);
11060   match(Set cr (FastLock object box));
11061   effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4);
11062 
11063   ins_cost(10 * DEFAULT_COST);
11064   format %{ "fastlock $object,$box\t! kills $tmp1,$tmp2,$tmp3,$tmp4 #@cmpFastLock" %}
11065 
11066   ins_encode %{
11067     __ fast_lock($object$$Register, $box$$Register,
11068                  $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register);
11069   %}
11070 
11071   ins_pipe(pipe_serial);
11072 %}
11073 
11074 // using t1 as the 'flag' register to bridge the BoolNode producers and consumers
11075 instruct cmpFastUnlock(rFlagsReg cr, iRegP object, iRegP box, iRegPNoSp tmp1, iRegPNoSp tmp2)
11076 %{
11077   predicate(LockingMode != LM_LIGHTWEIGHT);
11078   match(Set cr (FastUnlock object box));
11079   effect(TEMP tmp1, TEMP tmp2);
11080 
11081   ins_cost(10 * DEFAULT_COST);
11082   format %{ "fastunlock $object,$box\t! kills $tmp1, $tmp2, #@cmpFastUnlock" %}
11083 
11084   ins_encode %{
11085     __ fast_unlock($object$$Register, $box$$Register, $tmp1$$Register, $tmp2$$Register);
11086   %}
11087 
11088   ins_pipe(pipe_serial);
11089 %}
11090 
11091 instruct cmpFastLockLightweight(rFlagsReg cr, iRegP object, iRegP box,
11092                                 iRegPNoSp tmp1, iRegPNoSp tmp2, iRegPNoSp tmp3, iRegPNoSp tmp4)
11093 %{
11094   predicate(LockingMode == LM_LIGHTWEIGHT);
11095   match(Set cr (FastLock object box));
11096   effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4);
11097 
11098   ins_cost(10 * DEFAULT_COST);
11099   format %{ "fastlock $object,$box\t! kills $tmp1,$tmp2,$tmp3,$tmp4 #@cmpFastLockLightweight" %}
11100 
11101   ins_encode %{
11102     __ fast_lock_lightweight($object$$Register, $box$$Register,
11103                              $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register);
11104   %}
11105 
11106   ins_pipe(pipe_serial);
11107 %}
11108 
11109 instruct cmpFastUnlockLightweight(rFlagsReg cr, iRegP object, iRegP box,
11110                                   iRegPNoSp tmp1, iRegPNoSp tmp2, iRegPNoSp tmp3)
11111 %{
11112   predicate(LockingMode == LM_LIGHTWEIGHT);
11113   match(Set cr (FastUnlock object box));
11114   effect(TEMP tmp1, TEMP tmp2, TEMP tmp3);
11115 
11116   ins_cost(10 * DEFAULT_COST);
11117   format %{ "fastunlock $object,$box\t! kills $tmp1,$tmp2,$tmp3 #@cmpFastUnlockLightweight" %}
11118 
11119   ins_encode %{
11120     __ fast_unlock_lightweight($object$$Register, $box$$Register,
11121                                $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
11122   %}
11123 
11124   ins_pipe(pipe_serial);
11125 %}
11126 
11127 // Tail Call; Jump from runtime stub to Java code.
11128 // Also known as an 'interprocedural jump'.
11129 // Target of jump will eventually return to caller.
11130 // TailJump below removes the return address.
11131 // Don't use fp for 'jump_target' because a MachEpilogNode has already been
11132 // emitted just above the TailCall which has reset fp to the caller state.
11133 instruct TailCalljmpInd(iRegPNoSpNoFp jump_target, inline_cache_RegP method_oop)
11134 %{
11135   match(TailCall jump_target method_oop);
11136 
11137   ins_cost(BRANCH_COST);
11138 
11139   format %{ "jalr $jump_target\t# $method_oop holds method oop, #@TailCalljmpInd." %}
11140 
11141   ins_encode(riscv_enc_tail_call(jump_target));
11142 
11143   ins_pipe(pipe_class_call);
11144 %}
11145 
11146 instruct TailjmpInd(iRegPNoSpNoFp jump_target, iRegP_R10 ex_oop)
11147 %{
11148   match(TailJump jump_target ex_oop);
11149 
11150   ins_cost(ALU_COST + BRANCH_COST);
11151 
11152   format %{ "jalr $jump_target\t# $ex_oop holds exception oop, #@TailjmpInd." %}
11153 
11154   ins_encode(riscv_enc_tail_jmp(jump_target));
11155 
11156   ins_pipe(pipe_class_call);
11157 %}
11158 
11159 // Forward exception.
11160 instruct ForwardExceptionjmp()
11161 %{
11162   match(ForwardException);
11163 
11164   ins_cost(BRANCH_COST);
11165 
11166   format %{ "j forward_exception_stub\t#@ForwardException" %}
11167 
11168   ins_encode %{
11169     __ far_jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
11170   %}
11171 
11172   ins_pipe(pipe_class_call);
11173 %}
11174 
11175 // Create exception oop: created by stack-crawling runtime code.
11176 // Created exception is now available to this handler, and is setup
11177 // just prior to jumping to this handler. No code emitted.
11178 instruct CreateException(iRegP_R10 ex_oop)
11179 %{
11180   match(Set ex_oop (CreateEx));
11181 
11182   ins_cost(0);
11183   format %{ " -- \t// exception oop; no code emitted, #@CreateException" %}
11184 
11185   size(0);
11186 
11187   ins_encode( /*empty*/ );
11188 
11189   ins_pipe(pipe_class_empty);
11190 %}
11191 
11192 // Rethrow exception: The exception oop will come in the first
11193 // argument position. Then JUMP (not call) to the rethrow stub code.
11194 instruct RethrowException()
11195 %{
11196   match(Rethrow);
11197 
11198   ins_cost(BRANCH_COST);
11199 
11200   format %{ "j rethrow_stub\t#@RethrowException" %}
11201 
11202   ins_encode(riscv_enc_rethrow());
11203 
11204   ins_pipe(pipe_class_call);
11205 %}
11206 
11207 // Return Instruction
11208 // epilog node loads ret address into ra as part of frame pop
11209 instruct Ret()
11210 %{
11211   match(Return);
11212 
11213   ins_cost(BRANCH_COST);
11214   format %{ "ret\t// return register, #@Ret" %}
11215 
11216   ins_encode(riscv_enc_ret());
11217 
11218   ins_pipe(pipe_branch);
11219 %}
11220 
11221 // Die now.
11222 instruct ShouldNotReachHere() %{
11223   match(Halt);
11224 
11225   ins_cost(BRANCH_COST);
11226 
11227   format %{ "#@ShouldNotReachHere" %}
11228 
11229   ins_encode %{
11230     if (is_reachable()) {
11231       const char* str = __ code_string(_halt_reason);
11232       __ stop(str);
11233     }
11234   %}
11235 
11236   ins_pipe(pipe_class_default);
11237 %}
11238 
11239 
11240 //----------PEEPHOLE RULES-----------------------------------------------------
11241 // These must follow all instruction definitions as they use the names
11242 // defined in the instructions definitions.
11243 //
11244 // peepmatch ( root_instr_name [preceding_instruction]* );
11245 //
11246 // peepconstraint %{
11247 // (instruction_number.operand_name relational_op instruction_number.operand_name
11248 //  [, ...] );
11249 // // instruction numbers are zero-based using left to right order in peepmatch
11250 //
11251 // peepreplace ( instr_name  ( [instruction_number.operand_name]* ) );
11252 // // provide an instruction_number.operand_name for each operand that appears
11253 // // in the replacement instruction's match rule
11254 //
11255 // ---------VM FLAGS---------------------------------------------------------
11256 //
11257 // All peephole optimizations can be turned off using -XX:-OptoPeephole
11258 //
11259 // Each peephole rule is given an identifying number starting with zero and
11260 // increasing by one in the order seen by the parser.  An individual peephole
11261 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
11262 // on the command-line.
11263 //
11264 // ---------CURRENT LIMITATIONS----------------------------------------------
11265 //
11266 // Only match adjacent instructions in same basic block
11267 // Only equality constraints
11268 // Only constraints between operands, not (0.dest_reg == RAX_enc)
11269 // Only one replacement instruction
11270 //
11271 //----------SMARTSPILL RULES---------------------------------------------------
11272 // These must follow all instruction definitions as they use the names
11273 // defined in the instructions definitions.
11274 
11275 // Local Variables:
11276 // mode: c++
11277 // End: