1 //
2 // Copyright (c) 2003, 2024, Oracle and/or its affiliates. All rights reserved.
3 // Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
4 // Copyright (c) 2020, 2024, Huawei Technologies Co., Ltd. All rights reserved.
5 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
6 //
7 // This code is free software; you can redistribute it and/or modify it
8 // under the terms of the GNU General Public License version 2 only, as
9 // published by the Free Software Foundation.
10 //
11 // This code is distributed in the hope that it will be useful, but WITHOUT
12 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 // version 2 for more details (a copy is included in the LICENSE file that
15 // accompanied this code).
16 //
17 // You should have received a copy of the GNU General Public License version
18 // 2 along with this work; if not, write to the Free Software Foundation,
19 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
20 //
21 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
22 // or visit www.oracle.com if you need additional information or have any
23 // questions.
24 //
25 //
26
27 // RISCV Architecture Description File
28
29 //----------REGISTER DEFINITION BLOCK------------------------------------------
30 // This information is used by the matcher and the register allocator to
31 // describe individual registers and classes of registers within the target
32 // architecture.
33
34 register %{
35 //----------Architecture Description Register Definitions----------------------
36 // General Registers
37 // "reg_def" name ( register save type, C convention save type,
38 // ideal register type, encoding );
39 // Register Save Types:
40 //
41 // NS = No-Save: The register allocator assumes that these registers
42 // can be used without saving upon entry to the method, &
43 // that they do not need to be saved at call sites.
44 //
45 // SOC = Save-On-Call: The register allocator assumes that these registers
46 // can be used without saving upon entry to the method,
47 // but that they must be saved at call sites.
48 //
49 // SOE = Save-On-Entry: The register allocator assumes that these registers
50 // must be saved before using them upon entry to the
51 // method, but they do not need to be saved at call
52 // sites.
53 //
54 // AS = Always-Save: The register allocator assumes that these registers
55 // must be saved before using them upon entry to the
56 // method, & that they must be saved at call sites.
57 //
58 // Ideal Register Type is used to determine how to save & restore a
59 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
60 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
61 //
62 // The encoding number is the actual bit-pattern placed into the opcodes.
63
64 // We must define the 64 bit int registers in two 32 bit halves, the
65 // real lower register and a virtual upper half register. upper halves
66 // are used by the register allocator but are not actually supplied as
67 // operands to memory ops.
68 //
69 // follow the C1 compiler in making registers
70 //
71 // x7, x9-x17, x27-x31 volatile (caller save)
72 // x0-x4, x8, x23 system (no save, no allocate)
73 // x5-x6 non-allocatable (so we can use them as temporary regs)
74
75 //
76 // as regards Java usage. we don't use any callee save registers
77 // because this makes it difficult to de-optimise a frame (see comment
78 // in x86 implementation of Deoptimization::unwind_callee_save_values)
79 //
80
81 // General Registers
82
83 reg_def R0 ( NS, NS, Op_RegI, 0, x0->as_VMReg() ); // zr
84 reg_def R0_H ( NS, NS, Op_RegI, 0, x0->as_VMReg()->next() );
85 reg_def R1 ( NS, SOC, Op_RegI, 1, x1->as_VMReg() ); // ra
86 reg_def R1_H ( NS, SOC, Op_RegI, 1, x1->as_VMReg()->next() );
87 reg_def R2 ( NS, NS, Op_RegI, 2, x2->as_VMReg() ); // sp
88 reg_def R2_H ( NS, NS, Op_RegI, 2, x2->as_VMReg()->next() );
89 reg_def R3 ( NS, NS, Op_RegI, 3, x3->as_VMReg() ); // gp
90 reg_def R3_H ( NS, NS, Op_RegI, 3, x3->as_VMReg()->next() );
91 reg_def R4 ( NS, NS, Op_RegI, 4, x4->as_VMReg() ); // tp
92 reg_def R4_H ( NS, NS, Op_RegI, 4, x4->as_VMReg()->next() );
93 reg_def R7 ( SOC, SOC, Op_RegI, 7, x7->as_VMReg() );
94 reg_def R7_H ( SOC, SOC, Op_RegI, 7, x7->as_VMReg()->next() );
95 reg_def R8 ( NS, SOE, Op_RegI, 8, x8->as_VMReg() ); // fp
96 reg_def R8_H ( NS, SOE, Op_RegI, 8, x8->as_VMReg()->next() );
97 reg_def R9 ( SOC, SOE, Op_RegI, 9, x9->as_VMReg() );
98 reg_def R9_H ( SOC, SOE, Op_RegI, 9, x9->as_VMReg()->next() );
99 reg_def R10 ( SOC, SOC, Op_RegI, 10, x10->as_VMReg() );
100 reg_def R10_H ( SOC, SOC, Op_RegI, 10, x10->as_VMReg()->next());
101 reg_def R11 ( SOC, SOC, Op_RegI, 11, x11->as_VMReg() );
102 reg_def R11_H ( SOC, SOC, Op_RegI, 11, x11->as_VMReg()->next());
103 reg_def R12 ( SOC, SOC, Op_RegI, 12, x12->as_VMReg() );
104 reg_def R12_H ( SOC, SOC, Op_RegI, 12, x12->as_VMReg()->next());
105 reg_def R13 ( SOC, SOC, Op_RegI, 13, x13->as_VMReg() );
106 reg_def R13_H ( SOC, SOC, Op_RegI, 13, x13->as_VMReg()->next());
107 reg_def R14 ( SOC, SOC, Op_RegI, 14, x14->as_VMReg() );
108 reg_def R14_H ( SOC, SOC, Op_RegI, 14, x14->as_VMReg()->next());
109 reg_def R15 ( SOC, SOC, Op_RegI, 15, x15->as_VMReg() );
110 reg_def R15_H ( SOC, SOC, Op_RegI, 15, x15->as_VMReg()->next());
111 reg_def R16 ( SOC, SOC, Op_RegI, 16, x16->as_VMReg() );
112 reg_def R16_H ( SOC, SOC, Op_RegI, 16, x16->as_VMReg()->next());
113 reg_def R17 ( SOC, SOC, Op_RegI, 17, x17->as_VMReg() );
114 reg_def R17_H ( SOC, SOC, Op_RegI, 17, x17->as_VMReg()->next());
115 reg_def R18 ( SOC, SOE, Op_RegI, 18, x18->as_VMReg() );
116 reg_def R18_H ( SOC, SOE, Op_RegI, 18, x18->as_VMReg()->next());
117 reg_def R19 ( SOC, SOE, Op_RegI, 19, x19->as_VMReg() );
118 reg_def R19_H ( SOC, SOE, Op_RegI, 19, x19->as_VMReg()->next());
119 reg_def R20 ( SOC, SOE, Op_RegI, 20, x20->as_VMReg() ); // caller esp
120 reg_def R20_H ( SOC, SOE, Op_RegI, 20, x20->as_VMReg()->next());
121 reg_def R21 ( SOC, SOE, Op_RegI, 21, x21->as_VMReg() );
122 reg_def R21_H ( SOC, SOE, Op_RegI, 21, x21->as_VMReg()->next());
123 reg_def R22 ( SOC, SOE, Op_RegI, 22, x22->as_VMReg() );
124 reg_def R22_H ( SOC, SOE, Op_RegI, 22, x22->as_VMReg()->next());
125 reg_def R23 ( NS, SOE, Op_RegI, 23, x23->as_VMReg() ); // java thread
126 reg_def R23_H ( NS, SOE, Op_RegI, 23, x23->as_VMReg()->next());
127 reg_def R24 ( SOC, SOE, Op_RegI, 24, x24->as_VMReg() );
128 reg_def R24_H ( SOC, SOE, Op_RegI, 24, x24->as_VMReg()->next());
129 reg_def R25 ( SOC, SOE, Op_RegI, 25, x25->as_VMReg() );
130 reg_def R25_H ( SOC, SOE, Op_RegI, 25, x25->as_VMReg()->next());
131 reg_def R26 ( SOC, SOE, Op_RegI, 26, x26->as_VMReg() );
132 reg_def R26_H ( SOC, SOE, Op_RegI, 26, x26->as_VMReg()->next());
133 reg_def R27 ( SOC, SOE, Op_RegI, 27, x27->as_VMReg() ); // heapbase
134 reg_def R27_H ( SOC, SOE, Op_RegI, 27, x27->as_VMReg()->next());
135 reg_def R28 ( SOC, SOC, Op_RegI, 28, x28->as_VMReg() );
136 reg_def R28_H ( SOC, SOC, Op_RegI, 28, x28->as_VMReg()->next());
137 reg_def R29 ( SOC, SOC, Op_RegI, 29, x29->as_VMReg() );
138 reg_def R29_H ( SOC, SOC, Op_RegI, 29, x29->as_VMReg()->next());
139 reg_def R30 ( SOC, SOC, Op_RegI, 30, x30->as_VMReg() );
140 reg_def R30_H ( SOC, SOC, Op_RegI, 30, x30->as_VMReg()->next());
141 reg_def R31 ( SOC, SOC, Op_RegI, 31, x31->as_VMReg() );
142 reg_def R31_H ( SOC, SOC, Op_RegI, 31, x31->as_VMReg()->next());
143
144 // ----------------------------
145 // Float/Double Registers
146 // ----------------------------
147
148 // Double Registers
149
150 // The rules of ADL require that double registers be defined in pairs.
151 // Each pair must be two 32-bit values, but not necessarily a pair of
152 // single float registers. In each pair, ADLC-assigned register numbers
153 // must be adjacent, with the lower number even. Finally, when the
154 // CPU stores such a register pair to memory, the word associated with
155 // the lower ADLC-assigned number must be stored to the lower address.
156
157 // RISCV has 32 floating-point registers. Each can store a single
158 // or double precision floating-point value.
159
160 // for Java use float registers f0-f31 are always save on call whereas
161 // the platform ABI treats f8-f9 and f18-f27 as callee save). Other
162 // float registers are SOC as per the platform spec
163
164 reg_def F0 ( SOC, SOC, Op_RegF, 0, f0->as_VMReg() );
165 reg_def F0_H ( SOC, SOC, Op_RegF, 0, f0->as_VMReg()->next() );
166 reg_def F1 ( SOC, SOC, Op_RegF, 1, f1->as_VMReg() );
167 reg_def F1_H ( SOC, SOC, Op_RegF, 1, f1->as_VMReg()->next() );
168 reg_def F2 ( SOC, SOC, Op_RegF, 2, f2->as_VMReg() );
169 reg_def F2_H ( SOC, SOC, Op_RegF, 2, f2->as_VMReg()->next() );
170 reg_def F3 ( SOC, SOC, Op_RegF, 3, f3->as_VMReg() );
171 reg_def F3_H ( SOC, SOC, Op_RegF, 3, f3->as_VMReg()->next() );
172 reg_def F4 ( SOC, SOC, Op_RegF, 4, f4->as_VMReg() );
173 reg_def F4_H ( SOC, SOC, Op_RegF, 4, f4->as_VMReg()->next() );
174 reg_def F5 ( SOC, SOC, Op_RegF, 5, f5->as_VMReg() );
175 reg_def F5_H ( SOC, SOC, Op_RegF, 5, f5->as_VMReg()->next() );
176 reg_def F6 ( SOC, SOC, Op_RegF, 6, f6->as_VMReg() );
177 reg_def F6_H ( SOC, SOC, Op_RegF, 6, f6->as_VMReg()->next() );
178 reg_def F7 ( SOC, SOC, Op_RegF, 7, f7->as_VMReg() );
179 reg_def F7_H ( SOC, SOC, Op_RegF, 7, f7->as_VMReg()->next() );
180 reg_def F8 ( SOC, SOE, Op_RegF, 8, f8->as_VMReg() );
181 reg_def F8_H ( SOC, SOE, Op_RegF, 8, f8->as_VMReg()->next() );
182 reg_def F9 ( SOC, SOE, Op_RegF, 9, f9->as_VMReg() );
183 reg_def F9_H ( SOC, SOE, Op_RegF, 9, f9->as_VMReg()->next() );
184 reg_def F10 ( SOC, SOC, Op_RegF, 10, f10->as_VMReg() );
185 reg_def F10_H ( SOC, SOC, Op_RegF, 10, f10->as_VMReg()->next() );
186 reg_def F11 ( SOC, SOC, Op_RegF, 11, f11->as_VMReg() );
187 reg_def F11_H ( SOC, SOC, Op_RegF, 11, f11->as_VMReg()->next() );
188 reg_def F12 ( SOC, SOC, Op_RegF, 12, f12->as_VMReg() );
189 reg_def F12_H ( SOC, SOC, Op_RegF, 12, f12->as_VMReg()->next() );
190 reg_def F13 ( SOC, SOC, Op_RegF, 13, f13->as_VMReg() );
191 reg_def F13_H ( SOC, SOC, Op_RegF, 13, f13->as_VMReg()->next() );
192 reg_def F14 ( SOC, SOC, Op_RegF, 14, f14->as_VMReg() );
193 reg_def F14_H ( SOC, SOC, Op_RegF, 14, f14->as_VMReg()->next() );
194 reg_def F15 ( SOC, SOC, Op_RegF, 15, f15->as_VMReg() );
195 reg_def F15_H ( SOC, SOC, Op_RegF, 15, f15->as_VMReg()->next() );
196 reg_def F16 ( SOC, SOC, Op_RegF, 16, f16->as_VMReg() );
197 reg_def F16_H ( SOC, SOC, Op_RegF, 16, f16->as_VMReg()->next() );
198 reg_def F17 ( SOC, SOC, Op_RegF, 17, f17->as_VMReg() );
199 reg_def F17_H ( SOC, SOC, Op_RegF, 17, f17->as_VMReg()->next() );
200 reg_def F18 ( SOC, SOE, Op_RegF, 18, f18->as_VMReg() );
201 reg_def F18_H ( SOC, SOE, Op_RegF, 18, f18->as_VMReg()->next() );
202 reg_def F19 ( SOC, SOE, Op_RegF, 19, f19->as_VMReg() );
203 reg_def F19_H ( SOC, SOE, Op_RegF, 19, f19->as_VMReg()->next() );
204 reg_def F20 ( SOC, SOE, Op_RegF, 20, f20->as_VMReg() );
205 reg_def F20_H ( SOC, SOE, Op_RegF, 20, f20->as_VMReg()->next() );
206 reg_def F21 ( SOC, SOE, Op_RegF, 21, f21->as_VMReg() );
207 reg_def F21_H ( SOC, SOE, Op_RegF, 21, f21->as_VMReg()->next() );
208 reg_def F22 ( SOC, SOE, Op_RegF, 22, f22->as_VMReg() );
209 reg_def F22_H ( SOC, SOE, Op_RegF, 22, f22->as_VMReg()->next() );
210 reg_def F23 ( SOC, SOE, Op_RegF, 23, f23->as_VMReg() );
211 reg_def F23_H ( SOC, SOE, Op_RegF, 23, f23->as_VMReg()->next() );
212 reg_def F24 ( SOC, SOE, Op_RegF, 24, f24->as_VMReg() );
213 reg_def F24_H ( SOC, SOE, Op_RegF, 24, f24->as_VMReg()->next() );
214 reg_def F25 ( SOC, SOE, Op_RegF, 25, f25->as_VMReg() );
215 reg_def F25_H ( SOC, SOE, Op_RegF, 25, f25->as_VMReg()->next() );
216 reg_def F26 ( SOC, SOE, Op_RegF, 26, f26->as_VMReg() );
217 reg_def F26_H ( SOC, SOE, Op_RegF, 26, f26->as_VMReg()->next() );
218 reg_def F27 ( SOC, SOE, Op_RegF, 27, f27->as_VMReg() );
219 reg_def F27_H ( SOC, SOE, Op_RegF, 27, f27->as_VMReg()->next() );
220 reg_def F28 ( SOC, SOC, Op_RegF, 28, f28->as_VMReg() );
221 reg_def F28_H ( SOC, SOC, Op_RegF, 28, f28->as_VMReg()->next() );
222 reg_def F29 ( SOC, SOC, Op_RegF, 29, f29->as_VMReg() );
223 reg_def F29_H ( SOC, SOC, Op_RegF, 29, f29->as_VMReg()->next() );
224 reg_def F30 ( SOC, SOC, Op_RegF, 30, f30->as_VMReg() );
225 reg_def F30_H ( SOC, SOC, Op_RegF, 30, f30->as_VMReg()->next() );
226 reg_def F31 ( SOC, SOC, Op_RegF, 31, f31->as_VMReg() );
227 reg_def F31_H ( SOC, SOC, Op_RegF, 31, f31->as_VMReg()->next() );
228
229 // ----------------------------
230 // Vector Registers
231 // ----------------------------
232
233 // For RVV vector registers, we simply extend vector register size to 4
234 // 'logical' slots. This is nominally 128 bits but it actually covers
235 // all possible 'physical' RVV vector register lengths from 128 ~ 1024
236 // bits. The 'physical' RVV vector register length is detected during
237 // startup, so the register allocator is able to identify the correct
238 // number of bytes needed for an RVV spill/unspill.
239
240 reg_def V0 ( SOC, SOC, Op_VecA, 0, v0->as_VMReg() );
241 reg_def V0_H ( SOC, SOC, Op_VecA, 0, v0->as_VMReg()->next() );
242 reg_def V0_J ( SOC, SOC, Op_VecA, 0, v0->as_VMReg()->next(2) );
243 reg_def V0_K ( SOC, SOC, Op_VecA, 0, v0->as_VMReg()->next(3) );
244
245 reg_def V1 ( SOC, SOC, Op_VecA, 1, v1->as_VMReg() );
246 reg_def V1_H ( SOC, SOC, Op_VecA, 1, v1->as_VMReg()->next() );
247 reg_def V1_J ( SOC, SOC, Op_VecA, 1, v1->as_VMReg()->next(2) );
248 reg_def V1_K ( SOC, SOC, Op_VecA, 1, v1->as_VMReg()->next(3) );
249
250 reg_def V2 ( SOC, SOC, Op_VecA, 2, v2->as_VMReg() );
251 reg_def V2_H ( SOC, SOC, Op_VecA, 2, v2->as_VMReg()->next() );
252 reg_def V2_J ( SOC, SOC, Op_VecA, 2, v2->as_VMReg()->next(2) );
253 reg_def V2_K ( SOC, SOC, Op_VecA, 2, v2->as_VMReg()->next(3) );
254
255 reg_def V3 ( SOC, SOC, Op_VecA, 3, v3->as_VMReg() );
256 reg_def V3_H ( SOC, SOC, Op_VecA, 3, v3->as_VMReg()->next() );
257 reg_def V3_J ( SOC, SOC, Op_VecA, 3, v3->as_VMReg()->next(2) );
258 reg_def V3_K ( SOC, SOC, Op_VecA, 3, v3->as_VMReg()->next(3) );
259
260 reg_def V4 ( SOC, SOC, Op_VecA, 4, v4->as_VMReg() );
261 reg_def V4_H ( SOC, SOC, Op_VecA, 4, v4->as_VMReg()->next() );
262 reg_def V4_J ( SOC, SOC, Op_VecA, 4, v4->as_VMReg()->next(2) );
263 reg_def V4_K ( SOC, SOC, Op_VecA, 4, v4->as_VMReg()->next(3) );
264
265 reg_def V5 ( SOC, SOC, Op_VecA, 5, v5->as_VMReg() );
266 reg_def V5_H ( SOC, SOC, Op_VecA, 5, v5->as_VMReg()->next() );
267 reg_def V5_J ( SOC, SOC, Op_VecA, 5, v5->as_VMReg()->next(2) );
268 reg_def V5_K ( SOC, SOC, Op_VecA, 5, v5->as_VMReg()->next(3) );
269
270 reg_def V6 ( SOC, SOC, Op_VecA, 6, v6->as_VMReg() );
271 reg_def V6_H ( SOC, SOC, Op_VecA, 6, v6->as_VMReg()->next() );
272 reg_def V6_J ( SOC, SOC, Op_VecA, 6, v6->as_VMReg()->next(2) );
273 reg_def V6_K ( SOC, SOC, Op_VecA, 6, v6->as_VMReg()->next(3) );
274
275 reg_def V7 ( SOC, SOC, Op_VecA, 7, v7->as_VMReg() );
276 reg_def V7_H ( SOC, SOC, Op_VecA, 7, v7->as_VMReg()->next() );
277 reg_def V7_J ( SOC, SOC, Op_VecA, 7, v7->as_VMReg()->next(2) );
278 reg_def V7_K ( SOC, SOC, Op_VecA, 7, v7->as_VMReg()->next(3) );
279
280 reg_def V8 ( SOC, SOC, Op_VecA, 8, v8->as_VMReg() );
281 reg_def V8_H ( SOC, SOC, Op_VecA, 8, v8->as_VMReg()->next() );
282 reg_def V8_J ( SOC, SOC, Op_VecA, 8, v8->as_VMReg()->next(2) );
283 reg_def V8_K ( SOC, SOC, Op_VecA, 8, v8->as_VMReg()->next(3) );
284
285 reg_def V9 ( SOC, SOC, Op_VecA, 9, v9->as_VMReg() );
286 reg_def V9_H ( SOC, SOC, Op_VecA, 9, v9->as_VMReg()->next() );
287 reg_def V9_J ( SOC, SOC, Op_VecA, 9, v9->as_VMReg()->next(2) );
288 reg_def V9_K ( SOC, SOC, Op_VecA, 9, v9->as_VMReg()->next(3) );
289
290 reg_def V10 ( SOC, SOC, Op_VecA, 10, v10->as_VMReg() );
291 reg_def V10_H ( SOC, SOC, Op_VecA, 10, v10->as_VMReg()->next() );
292 reg_def V10_J ( SOC, SOC, Op_VecA, 10, v10->as_VMReg()->next(2) );
293 reg_def V10_K ( SOC, SOC, Op_VecA, 10, v10->as_VMReg()->next(3) );
294
295 reg_def V11 ( SOC, SOC, Op_VecA, 11, v11->as_VMReg() );
296 reg_def V11_H ( SOC, SOC, Op_VecA, 11, v11->as_VMReg()->next() );
297 reg_def V11_J ( SOC, SOC, Op_VecA, 11, v11->as_VMReg()->next(2) );
298 reg_def V11_K ( SOC, SOC, Op_VecA, 11, v11->as_VMReg()->next(3) );
299
300 reg_def V12 ( SOC, SOC, Op_VecA, 12, v12->as_VMReg() );
301 reg_def V12_H ( SOC, SOC, Op_VecA, 12, v12->as_VMReg()->next() );
302 reg_def V12_J ( SOC, SOC, Op_VecA, 12, v12->as_VMReg()->next(2) );
303 reg_def V12_K ( SOC, SOC, Op_VecA, 12, v12->as_VMReg()->next(3) );
304
305 reg_def V13 ( SOC, SOC, Op_VecA, 13, v13->as_VMReg() );
306 reg_def V13_H ( SOC, SOC, Op_VecA, 13, v13->as_VMReg()->next() );
307 reg_def V13_J ( SOC, SOC, Op_VecA, 13, v13->as_VMReg()->next(2) );
308 reg_def V13_K ( SOC, SOC, Op_VecA, 13, v13->as_VMReg()->next(3) );
309
310 reg_def V14 ( SOC, SOC, Op_VecA, 14, v14->as_VMReg() );
311 reg_def V14_H ( SOC, SOC, Op_VecA, 14, v14->as_VMReg()->next() );
312 reg_def V14_J ( SOC, SOC, Op_VecA, 14, v14->as_VMReg()->next(2) );
313 reg_def V14_K ( SOC, SOC, Op_VecA, 14, v14->as_VMReg()->next(3) );
314
315 reg_def V15 ( SOC, SOC, Op_VecA, 15, v15->as_VMReg() );
316 reg_def V15_H ( SOC, SOC, Op_VecA, 15, v15->as_VMReg()->next() );
317 reg_def V15_J ( SOC, SOC, Op_VecA, 15, v15->as_VMReg()->next(2) );
318 reg_def V15_K ( SOC, SOC, Op_VecA, 15, v15->as_VMReg()->next(3) );
319
320 reg_def V16 ( SOC, SOC, Op_VecA, 16, v16->as_VMReg() );
321 reg_def V16_H ( SOC, SOC, Op_VecA, 16, v16->as_VMReg()->next() );
322 reg_def V16_J ( SOC, SOC, Op_VecA, 16, v16->as_VMReg()->next(2) );
323 reg_def V16_K ( SOC, SOC, Op_VecA, 16, v16->as_VMReg()->next(3) );
324
325 reg_def V17 ( SOC, SOC, Op_VecA, 17, v17->as_VMReg() );
326 reg_def V17_H ( SOC, SOC, Op_VecA, 17, v17->as_VMReg()->next() );
327 reg_def V17_J ( SOC, SOC, Op_VecA, 17, v17->as_VMReg()->next(2) );
328 reg_def V17_K ( SOC, SOC, Op_VecA, 17, v17->as_VMReg()->next(3) );
329
330 reg_def V18 ( SOC, SOC, Op_VecA, 18, v18->as_VMReg() );
331 reg_def V18_H ( SOC, SOC, Op_VecA, 18, v18->as_VMReg()->next() );
332 reg_def V18_J ( SOC, SOC, Op_VecA, 18, v18->as_VMReg()->next(2) );
333 reg_def V18_K ( SOC, SOC, Op_VecA, 18, v18->as_VMReg()->next(3) );
334
335 reg_def V19 ( SOC, SOC, Op_VecA, 19, v19->as_VMReg() );
336 reg_def V19_H ( SOC, SOC, Op_VecA, 19, v19->as_VMReg()->next() );
337 reg_def V19_J ( SOC, SOC, Op_VecA, 19, v19->as_VMReg()->next(2) );
338 reg_def V19_K ( SOC, SOC, Op_VecA, 19, v19->as_VMReg()->next(3) );
339
340 reg_def V20 ( SOC, SOC, Op_VecA, 20, v20->as_VMReg() );
341 reg_def V20_H ( SOC, SOC, Op_VecA, 20, v20->as_VMReg()->next() );
342 reg_def V20_J ( SOC, SOC, Op_VecA, 20, v20->as_VMReg()->next(2) );
343 reg_def V20_K ( SOC, SOC, Op_VecA, 20, v20->as_VMReg()->next(3) );
344
345 reg_def V21 ( SOC, SOC, Op_VecA, 21, v21->as_VMReg() );
346 reg_def V21_H ( SOC, SOC, Op_VecA, 21, v21->as_VMReg()->next() );
347 reg_def V21_J ( SOC, SOC, Op_VecA, 21, v21->as_VMReg()->next(2) );
348 reg_def V21_K ( SOC, SOC, Op_VecA, 21, v21->as_VMReg()->next(3) );
349
350 reg_def V22 ( SOC, SOC, Op_VecA, 22, v22->as_VMReg() );
351 reg_def V22_H ( SOC, SOC, Op_VecA, 22, v22->as_VMReg()->next() );
352 reg_def V22_J ( SOC, SOC, Op_VecA, 22, v22->as_VMReg()->next(2) );
353 reg_def V22_K ( SOC, SOC, Op_VecA, 22, v22->as_VMReg()->next(3) );
354
355 reg_def V23 ( SOC, SOC, Op_VecA, 23, v23->as_VMReg() );
356 reg_def V23_H ( SOC, SOC, Op_VecA, 23, v23->as_VMReg()->next() );
357 reg_def V23_J ( SOC, SOC, Op_VecA, 23, v23->as_VMReg()->next(2) );
358 reg_def V23_K ( SOC, SOC, Op_VecA, 23, v23->as_VMReg()->next(3) );
359
360 reg_def V24 ( SOC, SOC, Op_VecA, 24, v24->as_VMReg() );
361 reg_def V24_H ( SOC, SOC, Op_VecA, 24, v24->as_VMReg()->next() );
362 reg_def V24_J ( SOC, SOC, Op_VecA, 24, v24->as_VMReg()->next(2) );
363 reg_def V24_K ( SOC, SOC, Op_VecA, 24, v24->as_VMReg()->next(3) );
364
365 reg_def V25 ( SOC, SOC, Op_VecA, 25, v25->as_VMReg() );
366 reg_def V25_H ( SOC, SOC, Op_VecA, 25, v25->as_VMReg()->next() );
367 reg_def V25_J ( SOC, SOC, Op_VecA, 25, v25->as_VMReg()->next(2) );
368 reg_def V25_K ( SOC, SOC, Op_VecA, 25, v25->as_VMReg()->next(3) );
369
370 reg_def V26 ( SOC, SOC, Op_VecA, 26, v26->as_VMReg() );
371 reg_def V26_H ( SOC, SOC, Op_VecA, 26, v26->as_VMReg()->next() );
372 reg_def V26_J ( SOC, SOC, Op_VecA, 26, v26->as_VMReg()->next(2) );
373 reg_def V26_K ( SOC, SOC, Op_VecA, 26, v26->as_VMReg()->next(3) );
374
375 reg_def V27 ( SOC, SOC, Op_VecA, 27, v27->as_VMReg() );
376 reg_def V27_H ( SOC, SOC, Op_VecA, 27, v27->as_VMReg()->next() );
377 reg_def V27_J ( SOC, SOC, Op_VecA, 27, v27->as_VMReg()->next(2) );
378 reg_def V27_K ( SOC, SOC, Op_VecA, 27, v27->as_VMReg()->next(3) );
379
380 reg_def V28 ( SOC, SOC, Op_VecA, 28, v28->as_VMReg() );
381 reg_def V28_H ( SOC, SOC, Op_VecA, 28, v28->as_VMReg()->next() );
382 reg_def V28_J ( SOC, SOC, Op_VecA, 28, v28->as_VMReg()->next(2) );
383 reg_def V28_K ( SOC, SOC, Op_VecA, 28, v28->as_VMReg()->next(3) );
384
385 reg_def V29 ( SOC, SOC, Op_VecA, 29, v29->as_VMReg() );
386 reg_def V29_H ( SOC, SOC, Op_VecA, 29, v29->as_VMReg()->next() );
387 reg_def V29_J ( SOC, SOC, Op_VecA, 29, v29->as_VMReg()->next(2) );
388 reg_def V29_K ( SOC, SOC, Op_VecA, 29, v29->as_VMReg()->next(3) );
389
390 reg_def V30 ( SOC, SOC, Op_VecA, 30, v30->as_VMReg() );
391 reg_def V30_H ( SOC, SOC, Op_VecA, 30, v30->as_VMReg()->next() );
392 reg_def V30_J ( SOC, SOC, Op_VecA, 30, v30->as_VMReg()->next(2) );
393 reg_def V30_K ( SOC, SOC, Op_VecA, 30, v30->as_VMReg()->next(3) );
394
395 reg_def V31 ( SOC, SOC, Op_VecA, 31, v31->as_VMReg() );
396 reg_def V31_H ( SOC, SOC, Op_VecA, 31, v31->as_VMReg()->next() );
397 reg_def V31_J ( SOC, SOC, Op_VecA, 31, v31->as_VMReg()->next(2) );
398 reg_def V31_K ( SOC, SOC, Op_VecA, 31, v31->as_VMReg()->next(3) );
399
400 // ----------------------------
401 // Special Registers
402 // ----------------------------
403
404 // On riscv, the physical flag register is missing, so we use t1 instead,
405 // to bridge the RegFlag semantics in share/opto
406
407 reg_def RFLAGS (SOC, SOC, Op_RegFlags, 6, x6->as_VMReg() );
408
409 // Specify priority of register selection within phases of register
410 // allocation. Highest priority is first. A useful heuristic is to
411 // give registers a low priority when they are required by machine
412 // instructions, like EAX and EDX on I486, and choose no-save registers
413 // before save-on-call, & save-on-call before save-on-entry. Registers
414 // which participate in fixed calling sequences should come last.
415 // Registers which are used as pairs must fall on an even boundary.
416
417 alloc_class chunk0(
418 // volatiles
419 R7, R7_H,
420 R28, R28_H,
421 R29, R29_H,
422 R30, R30_H,
423 R31, R31_H,
424
425 // arg registers
426 R10, R10_H,
427 R11, R11_H,
428 R12, R12_H,
429 R13, R13_H,
430 R14, R14_H,
431 R15, R15_H,
432 R16, R16_H,
433 R17, R17_H,
434
435 // non-volatiles
436 R9, R9_H,
437 R18, R18_H,
438 R19, R19_H,
439 R20, R20_H,
440 R21, R21_H,
441 R22, R22_H,
442 R24, R24_H,
443 R25, R25_H,
444 R26, R26_H,
445
446 // non-allocatable registers
447 R23, R23_H, // java thread
448 R27, R27_H, // heapbase
449 R4, R4_H, // thread
450 R8, R8_H, // fp
451 R0, R0_H, // zero
452 R1, R1_H, // ra
453 R2, R2_H, // sp
454 R3, R3_H, // gp
455 );
456
457 alloc_class chunk1(
458
459 // no save
460 F0, F0_H,
461 F1, F1_H,
462 F2, F2_H,
463 F3, F3_H,
464 F4, F4_H,
465 F5, F5_H,
466 F6, F6_H,
467 F7, F7_H,
468 F28, F28_H,
469 F29, F29_H,
470 F30, F30_H,
471 F31, F31_H,
472
473 // arg registers
474 F10, F10_H,
475 F11, F11_H,
476 F12, F12_H,
477 F13, F13_H,
478 F14, F14_H,
479 F15, F15_H,
480 F16, F16_H,
481 F17, F17_H,
482
483 // non-volatiles
484 F8, F8_H,
485 F9, F9_H,
486 F18, F18_H,
487 F19, F19_H,
488 F20, F20_H,
489 F21, F21_H,
490 F22, F22_H,
491 F23, F23_H,
492 F24, F24_H,
493 F25, F25_H,
494 F26, F26_H,
495 F27, F27_H,
496 );
497
498 alloc_class chunk2(
499 V0, V0_H, V0_J, V0_K,
500 V1, V1_H, V1_J, V1_K,
501 V2, V2_H, V2_J, V2_K,
502 V3, V3_H, V3_J, V3_K,
503 V4, V4_H, V4_J, V4_K,
504 V5, V5_H, V5_J, V5_K,
505 V6, V6_H, V6_J, V6_K,
506 V7, V7_H, V7_J, V7_K,
507 V8, V8_H, V8_J, V8_K,
508 V9, V9_H, V9_J, V9_K,
509 V10, V10_H, V10_J, V10_K,
510 V11, V11_H, V11_J, V11_K,
511 V12, V12_H, V12_J, V12_K,
512 V13, V13_H, V13_J, V13_K,
513 V14, V14_H, V14_J, V14_K,
514 V15, V15_H, V15_J, V15_K,
515 V16, V16_H, V16_J, V16_K,
516 V17, V17_H, V17_J, V17_K,
517 V18, V18_H, V18_J, V18_K,
518 V19, V19_H, V19_J, V19_K,
519 V20, V20_H, V20_J, V20_K,
520 V21, V21_H, V21_J, V21_K,
521 V22, V22_H, V22_J, V22_K,
522 V23, V23_H, V23_J, V23_K,
523 V24, V24_H, V24_J, V24_K,
524 V25, V25_H, V25_J, V25_K,
525 V26, V26_H, V26_J, V26_K,
526 V27, V27_H, V27_J, V27_K,
527 V28, V28_H, V28_J, V28_K,
528 V29, V29_H, V29_J, V29_K,
529 V30, V30_H, V30_J, V30_K,
530 V31, V31_H, V31_J, V31_K,
531 );
532
533 alloc_class chunk3(RFLAGS);
534
535 //----------Architecture Description Register Classes--------------------------
536 // Several register classes are automatically defined based upon information in
537 // this architecture description.
538 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
539 // 2) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
540 //
541
542 // Class for all 32 bit general purpose registers
543 reg_class all_reg32(
544 R0,
545 R1,
546 R2,
547 R3,
548 R4,
549 R7,
550 R8,
551 R9,
552 R10,
553 R11,
554 R12,
555 R13,
556 R14,
557 R15,
558 R16,
559 R17,
560 R18,
561 R19,
562 R20,
563 R21,
564 R22,
565 R23,
566 R24,
567 R25,
568 R26,
569 R27,
570 R28,
571 R29,
572 R30,
573 R31
574 );
575
576 // Class for any 32 bit integer registers (excluding zr)
577 reg_class any_reg32 %{
578 return _ANY_REG32_mask;
579 %}
580
581 // Singleton class for R10 int register
582 reg_class int_r10_reg(R10);
583
584 // Singleton class for R12 int register
585 reg_class int_r12_reg(R12);
586
587 // Singleton class for R13 int register
588 reg_class int_r13_reg(R13);
589
590 // Singleton class for R14 int register
591 reg_class int_r14_reg(R14);
592
593 // Class for all long integer registers
594 reg_class all_reg(
595 R0, R0_H,
596 R1, R1_H,
597 R2, R2_H,
598 R3, R3_H,
599 R4, R4_H,
600 R7, R7_H,
601 R8, R8_H,
602 R9, R9_H,
603 R10, R10_H,
604 R11, R11_H,
605 R12, R12_H,
606 R13, R13_H,
607 R14, R14_H,
608 R15, R15_H,
609 R16, R16_H,
610 R17, R17_H,
611 R18, R18_H,
612 R19, R19_H,
613 R20, R20_H,
614 R21, R21_H,
615 R22, R22_H,
616 R23, R23_H,
617 R24, R24_H,
618 R25, R25_H,
619 R26, R26_H,
620 R27, R27_H,
621 R28, R28_H,
622 R29, R29_H,
623 R30, R30_H,
624 R31, R31_H
625 );
626
627 // Class for all long integer registers (excluding zr)
628 reg_class any_reg %{
629 return _ANY_REG_mask;
630 %}
631
632 // Class for non-allocatable 32 bit registers
633 reg_class non_allocatable_reg32(
634 R0, // zr
635 R1, // ra
636 R2, // sp
637 R3, // gp
638 R4, // tp
639 R23 // java thread
640 );
641
642 // Class for non-allocatable 64 bit registers
643 reg_class non_allocatable_reg(
644 R0, R0_H, // zr
645 R1, R1_H, // ra
646 R2, R2_H, // sp
647 R3, R3_H, // gp
648 R4, R4_H, // tp
649 R23, R23_H // java thread
650 );
651
652 // Class for all non-special integer registers
653 reg_class no_special_reg32 %{
654 return _NO_SPECIAL_REG32_mask;
655 %}
656
657 // Class for all non-special long integer registers
658 reg_class no_special_reg %{
659 return _NO_SPECIAL_REG_mask;
660 %}
661
662 reg_class ptr_reg %{
663 return _PTR_REG_mask;
664 %}
665
666 // Class for all non_special pointer registers
667 reg_class no_special_ptr_reg %{
668 return _NO_SPECIAL_PTR_REG_mask;
669 %}
670
671 // Class for all non_special pointer registers (excluding fp)
672 reg_class no_special_no_fp_ptr_reg %{
673 return _NO_SPECIAL_NO_FP_PTR_REG_mask;
674 %}
675
676 // Class for 64 bit register r10
677 reg_class r10_reg(
678 R10, R10_H
679 );
680
681 // Class for 64 bit register r11
682 reg_class r11_reg(
683 R11, R11_H
684 );
685
686 // Class for 64 bit register r12
687 reg_class r12_reg(
688 R12, R12_H
689 );
690
691 // Class for 64 bit register r13
692 reg_class r13_reg(
693 R13, R13_H
694 );
695
696 // Class for 64 bit register r14
697 reg_class r14_reg(
698 R14, R14_H
699 );
700
701 // Class for 64 bit register r15
702 reg_class r15_reg(
703 R15, R15_H
704 );
705
706 // Class for 64 bit register r16
707 reg_class r16_reg(
708 R16, R16_H
709 );
710
711 // Class for method register
712 reg_class method_reg(
713 R31, R31_H
714 );
715
716 // Class for java thread register
717 reg_class java_thread_reg(
718 R23, R23_H
719 );
720
721 reg_class r28_reg(
722 R28, R28_H
723 );
724
725 reg_class r29_reg(
726 R29, R29_H
727 );
728
729 reg_class r30_reg(
730 R30, R30_H
731 );
732
733 reg_class r31_reg(
734 R31, R31_H
735 );
736
737 // Class for zero registesr
738 reg_class zr_reg(
739 R0, R0_H
740 );
741
742 // Class for thread register
743 reg_class thread_reg(
744 R4, R4_H
745 );
746
747 // Class for frame pointer register
748 reg_class fp_reg(
749 R8, R8_H
750 );
751
752 // Class for link register
753 reg_class ra_reg(
754 R1, R1_H
755 );
756
757 // Class for long sp register
758 reg_class sp_reg(
759 R2, R2_H
760 );
761
762 // Class for all float registers
763 reg_class float_reg(
764 F0,
765 F1,
766 F2,
767 F3,
768 F4,
769 F5,
770 F6,
771 F7,
772 F8,
773 F9,
774 F10,
775 F11,
776 F12,
777 F13,
778 F14,
779 F15,
780 F16,
781 F17,
782 F18,
783 F19,
784 F20,
785 F21,
786 F22,
787 F23,
788 F24,
789 F25,
790 F26,
791 F27,
792 F28,
793 F29,
794 F30,
795 F31
796 );
797
798 // Double precision float registers have virtual `high halves' that
799 // are needed by the allocator.
800 // Class for all double registers
801 reg_class double_reg(
802 F0, F0_H,
803 F1, F1_H,
804 F2, F2_H,
805 F3, F3_H,
806 F4, F4_H,
807 F5, F5_H,
808 F6, F6_H,
809 F7, F7_H,
810 F8, F8_H,
811 F9, F9_H,
812 F10, F10_H,
813 F11, F11_H,
814 F12, F12_H,
815 F13, F13_H,
816 F14, F14_H,
817 F15, F15_H,
818 F16, F16_H,
819 F17, F17_H,
820 F18, F18_H,
821 F19, F19_H,
822 F20, F20_H,
823 F21, F21_H,
824 F22, F22_H,
825 F23, F23_H,
826 F24, F24_H,
827 F25, F25_H,
828 F26, F26_H,
829 F27, F27_H,
830 F28, F28_H,
831 F29, F29_H,
832 F30, F30_H,
833 F31, F31_H
834 );
835
836 // Class for RVV vector registers
837 // Note: v0, v30 and v31 are used as mask registers.
838 reg_class vectora_reg(
839 V1, V1_H, V1_J, V1_K,
840 V2, V2_H, V2_J, V2_K,
841 V3, V3_H, V3_J, V3_K,
842 V4, V4_H, V4_J, V4_K,
843 V5, V5_H, V5_J, V5_K,
844 V6, V6_H, V6_J, V6_K,
845 V7, V7_H, V7_J, V7_K,
846 V8, V8_H, V8_J, V8_K,
847 V9, V9_H, V9_J, V9_K,
848 V10, V10_H, V10_J, V10_K,
849 V11, V11_H, V11_J, V11_K,
850 V12, V12_H, V12_J, V12_K,
851 V13, V13_H, V13_J, V13_K,
852 V14, V14_H, V14_J, V14_K,
853 V15, V15_H, V15_J, V15_K,
854 V16, V16_H, V16_J, V16_K,
855 V17, V17_H, V17_J, V17_K,
856 V18, V18_H, V18_J, V18_K,
857 V19, V19_H, V19_J, V19_K,
858 V20, V20_H, V20_J, V20_K,
859 V21, V21_H, V21_J, V21_K,
860 V22, V22_H, V22_J, V22_K,
861 V23, V23_H, V23_J, V23_K,
862 V24, V24_H, V24_J, V24_K,
863 V25, V25_H, V25_J, V25_K,
864 V26, V26_H, V26_J, V26_K,
865 V27, V27_H, V27_J, V27_K,
866 V28, V28_H, V28_J, V28_K,
867 V29, V29_H, V29_J, V29_K
868 );
869
870 // Class for 64 bit register f0
871 reg_class f0_reg(
872 F0, F0_H
873 );
874
875 // Class for 64 bit register f1
876 reg_class f1_reg(
877 F1, F1_H
878 );
879
880 // Class for 64 bit register f2
881 reg_class f2_reg(
882 F2, F2_H
883 );
884
885 // Class for 64 bit register f3
886 reg_class f3_reg(
887 F3, F3_H
888 );
889
890 // class for vector register v1
891 reg_class v1_reg(
892 V1, V1_H, V1_J, V1_K
893 );
894
895 // class for vector register v2
896 reg_class v2_reg(
897 V2, V2_H, V2_J, V2_K
898 );
899
900 // class for vector register v3
901 reg_class v3_reg(
902 V3, V3_H, V3_J, V3_K
903 );
904
905 // class for vector register v4
906 reg_class v4_reg(
907 V4, V4_H, V4_J, V4_K
908 );
909
910 // class for vector register v5
911 reg_class v5_reg(
912 V5, V5_H, V5_J, V5_K
913 );
914
915 // class for vector register v6
916 reg_class v6_reg(
917 V6, V6_H, V6_J, V6_K
918 );
919
920 // class for vector register v7
921 reg_class v7_reg(
922 V7, V7_H, V7_J, V7_K
923 );
924
925 // class for vector register v8
926 reg_class v8_reg(
927 V8, V8_H, V8_J, V8_K
928 );
929
930 // class for vector register v9
931 reg_class v9_reg(
932 V9, V9_H, V9_J, V9_K
933 );
934
935 // class for vector register v10
936 reg_class v10_reg(
937 V10, V10_H, V10_J, V10_K
938 );
939
940 // class for vector register v11
941 reg_class v11_reg(
942 V11, V11_H, V11_J, V11_K
943 );
944
945 // class for condition codes
946 reg_class reg_flags(RFLAGS);
947
948 // Class for RVV v0 mask register
949 // https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#53-vector-masking
950 // The mask value used to control execution of a masked vector
951 // instruction is always supplied by vector register v0.
952 reg_class vmask_reg_v0 (
953 V0
954 );
955
956 // Class for RVV mask registers
957 // We need two more vmask registers to do the vector mask logical ops,
958 // so define v30, v31 as mask register too.
959 reg_class vmask_reg (
960 V0,
961 V30,
962 V31
963 );
964 %}
965
966 //----------DEFINITION BLOCK---------------------------------------------------
967 // Define name --> value mappings to inform the ADLC of an integer valued name
968 // Current support includes integer values in the range [0, 0x7FFFFFFF]
969 // Format:
970 // int_def <name> ( <int_value>, <expression>);
971 // Generated Code in ad_<arch>.hpp
972 // #define <name> (<expression>)
973 // // value == <int_value>
974 // Generated code in ad_<arch>.cpp adlc_verification()
975 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
976 //
977
978 // we follow the ppc-aix port in using a simple cost model which ranks
979 // register operations as cheap, memory ops as more expensive and
980 // branches as most expensive. the first two have a low as well as a
981 // normal cost. huge cost appears to be a way of saying don't do
982 // something
983
984 definitions %{
985 // The default cost (of a register move instruction).
986 int_def DEFAULT_COST ( 100, 100);
987 int_def ALU_COST ( 100, 1 * DEFAULT_COST); // unknown, const, arith, shift, slt,
988 // multi, auipc, nop, logical, move
989 int_def LOAD_COST ( 300, 3 * DEFAULT_COST); // load, fpload
990 int_def STORE_COST ( 100, 1 * DEFAULT_COST); // store, fpstore
991 int_def XFER_COST ( 300, 3 * DEFAULT_COST); // mfc, mtc, fcvt, fmove, fcmp
992 int_def FMVX_COST ( 100, 1 * DEFAULT_COST); // shuffles with no conversion
993 int_def BRANCH_COST ( 200, 2 * DEFAULT_COST); // branch, jmp, call
994 int_def IMUL_COST ( 1000, 10 * DEFAULT_COST); // imul
995 int_def IDIVSI_COST ( 3400, 34 * DEFAULT_COST); // idivsi
996 int_def IDIVDI_COST ( 6600, 66 * DEFAULT_COST); // idivdi
997 int_def FMUL_SINGLE_COST ( 500, 5 * DEFAULT_COST); // fmul, fmadd
998 int_def FMUL_DOUBLE_COST ( 700, 7 * DEFAULT_COST); // fmul, fmadd
999 int_def FDIV_COST ( 2000, 20 * DEFAULT_COST); // fdiv
1000 int_def FSQRT_COST ( 2500, 25 * DEFAULT_COST); // fsqrt
1001 int_def VOLATILE_REF_COST ( 1000, 10 * DEFAULT_COST);
1002 int_def CACHE_MISS_COST ( 2000, 20 * DEFAULT_COST); // typicall cache miss penalty
1003 %}
1004
1005
1006
1007 //----------SOURCE BLOCK-------------------------------------------------------
1008 // This is a block of C++ code which provides values, functions, and
1009 // definitions necessary in the rest of the architecture description
1010
1011 source_hpp %{
1012
1013 #include "asm/macroAssembler.hpp"
1014 #include "gc/shared/barrierSetAssembler.hpp"
1015 #include "gc/shared/cardTable.hpp"
1016 #include "gc/shared/cardTableBarrierSet.hpp"
1017 #include "gc/shared/collectedHeap.hpp"
1018 #include "opto/addnode.hpp"
1019 #include "opto/convertnode.hpp"
1020 #include "runtime/objectMonitor.hpp"
1021
1022 extern RegMask _ANY_REG32_mask;
1023 extern RegMask _ANY_REG_mask;
1024 extern RegMask _PTR_REG_mask;
1025 extern RegMask _NO_SPECIAL_REG32_mask;
1026 extern RegMask _NO_SPECIAL_REG_mask;
1027 extern RegMask _NO_SPECIAL_PTR_REG_mask;
1028 extern RegMask _NO_SPECIAL_NO_FP_PTR_REG_mask;
1029
1030 class CallStubImpl {
1031
1032 //--------------------------------------------------------------
1033 //---< Used for optimization in Compile::shorten_branches >---
1034 //--------------------------------------------------------------
1035
1036 public:
1037 // Size of call trampoline stub.
1038 static uint size_call_trampoline() {
1039 return 0; // no call trampolines on this platform
1040 }
1041
1042 // number of relocations needed by a call trampoline stub
1043 static uint reloc_call_trampoline() {
1044 return 0; // no call trampolines on this platform
1045 }
1046 };
1047
1048 class HandlerImpl {
1049
1050 public:
1051
1052 static int emit_exception_handler(C2_MacroAssembler *masm);
1053 static int emit_deopt_handler(C2_MacroAssembler* masm);
1054
1055 static uint size_exception_handler() {
1056 return MacroAssembler::far_branch_size();
1057 }
1058
1059 static uint size_deopt_handler() {
1060 // count auipc + far branch
1061 return NativeInstruction::instruction_size + MacroAssembler::far_branch_size();
1062 }
1063 };
1064
1065 class Node::PD {
1066 public:
1067 enum NodeFlags {
1068 _last_flag = Node::_last_flag
1069 };
1070 };
1071
1072 bool is_CAS(int opcode, bool maybe_volatile);
1073
1074 // predicate controlling translation of CompareAndSwapX
1075 bool needs_acquiring_load_reserved(const Node *load);
1076
1077 // predicate controlling addressing modes
1078 bool size_fits_all_mem_uses(AddPNode* addp, int shift);
1079 %}
1080
1081 source %{
1082
1083 // Derived RegMask with conditionally allocatable registers
1084
1085 RegMask _ANY_REG32_mask;
1086 RegMask _ANY_REG_mask;
1087 RegMask _PTR_REG_mask;
1088 RegMask _NO_SPECIAL_REG32_mask;
1089 RegMask _NO_SPECIAL_REG_mask;
1090 RegMask _NO_SPECIAL_PTR_REG_mask;
1091 RegMask _NO_SPECIAL_NO_FP_PTR_REG_mask;
1092
1093 void reg_mask_init() {
1094
1095 _ANY_REG32_mask = _ALL_REG32_mask;
1096 _ANY_REG32_mask.Remove(OptoReg::as_OptoReg(x0->as_VMReg()));
1097
1098 _ANY_REG_mask = _ALL_REG_mask;
1099 _ANY_REG_mask.SUBTRACT(_ZR_REG_mask);
1100
1101 _PTR_REG_mask = _ALL_REG_mask;
1102 _PTR_REG_mask.SUBTRACT(_ZR_REG_mask);
1103
1104 _NO_SPECIAL_REG32_mask = _ALL_REG32_mask;
1105 _NO_SPECIAL_REG32_mask.SUBTRACT(_NON_ALLOCATABLE_REG32_mask);
1106
1107 _NO_SPECIAL_REG_mask = _ALL_REG_mask;
1108 _NO_SPECIAL_REG_mask.SUBTRACT(_NON_ALLOCATABLE_REG_mask);
1109
1110 _NO_SPECIAL_PTR_REG_mask = _ALL_REG_mask;
1111 _NO_SPECIAL_PTR_REG_mask.SUBTRACT(_NON_ALLOCATABLE_REG_mask);
1112
1113 // x27 is not allocatable when compressed oops is on
1114 if (UseCompressedOops) {
1115 _NO_SPECIAL_REG32_mask.Remove(OptoReg::as_OptoReg(x27->as_VMReg()));
1116 _NO_SPECIAL_REG_mask.Remove(OptoReg::as_OptoReg(x27->as_VMReg()));
1117 _NO_SPECIAL_PTR_REG_mask.Remove(OptoReg::as_OptoReg(x27->as_VMReg()));
1118 }
1119
1120 // x8 is not allocatable when PreserveFramePointer is on
1121 if (PreserveFramePointer) {
1122 _NO_SPECIAL_REG32_mask.Remove(OptoReg::as_OptoReg(x8->as_VMReg()));
1123 _NO_SPECIAL_REG_mask.Remove(OptoReg::as_OptoReg(x8->as_VMReg()));
1124 _NO_SPECIAL_PTR_REG_mask.Remove(OptoReg::as_OptoReg(x8->as_VMReg()));
1125 }
1126
1127 _NO_SPECIAL_NO_FP_PTR_REG_mask = _NO_SPECIAL_PTR_REG_mask;
1128 _NO_SPECIAL_NO_FP_PTR_REG_mask.Remove(OptoReg::as_OptoReg(x8->as_VMReg()));
1129 }
1130
1131 void PhaseOutput::pd_perform_mach_node_analysis() {
1132 }
1133
1134 int MachNode::pd_alignment_required() const {
1135 return 1;
1136 }
1137
1138 int MachNode::compute_padding(int current_offset) const {
1139 return 0;
1140 }
1141
1142 // is_CAS(int opcode, bool maybe_volatile)
1143 //
1144 // return true if opcode is one of the possible CompareAndSwapX
1145 // values otherwise false.
1146 bool is_CAS(int opcode, bool maybe_volatile)
1147 {
1148 switch (opcode) {
1149 // We handle these
1150 case Op_CompareAndSwapI:
1151 case Op_CompareAndSwapL:
1152 case Op_CompareAndSwapP:
1153 case Op_CompareAndSwapN:
1154 case Op_ShenandoahCompareAndSwapP:
1155 case Op_ShenandoahCompareAndSwapN:
1156 case Op_CompareAndSwapB:
1157 case Op_CompareAndSwapS:
1158 case Op_GetAndSetI:
1159 case Op_GetAndSetL:
1160 case Op_GetAndSetP:
1161 case Op_GetAndSetN:
1162 case Op_GetAndAddI:
1163 case Op_GetAndAddL:
1164 return true;
1165 case Op_CompareAndExchangeI:
1166 case Op_CompareAndExchangeN:
1167 case Op_CompareAndExchangeB:
1168 case Op_CompareAndExchangeS:
1169 case Op_CompareAndExchangeL:
1170 case Op_CompareAndExchangeP:
1171 case Op_WeakCompareAndSwapB:
1172 case Op_WeakCompareAndSwapS:
1173 case Op_WeakCompareAndSwapI:
1174 case Op_WeakCompareAndSwapL:
1175 case Op_WeakCompareAndSwapP:
1176 case Op_WeakCompareAndSwapN:
1177 case Op_ShenandoahWeakCompareAndSwapP:
1178 case Op_ShenandoahWeakCompareAndSwapN:
1179 case Op_ShenandoahCompareAndExchangeP:
1180 case Op_ShenandoahCompareAndExchangeN:
1181 return maybe_volatile;
1182 default:
1183 return false;
1184 }
1185 }
1186
1187 // predicate controlling translation of CAS
1188 //
1189 // returns true if CAS needs to use an acquiring load otherwise false
1190 bool needs_acquiring_load_reserved(const Node *n)
1191 {
1192 assert(n != nullptr && is_CAS(n->Opcode(), true), "expecting a compare and swap");
1193
1194 LoadStoreNode* ldst = n->as_LoadStore();
1195 if (n != nullptr && is_CAS(n->Opcode(), false)) {
1196 assert(ldst != nullptr && ldst->trailing_membar() != nullptr, "expected trailing membar");
1197 } else {
1198 return ldst != nullptr && ldst->trailing_membar() != nullptr;
1199 }
1200 // so we can just return true here
1201 return true;
1202 }
1203 #define __ masm->
1204
1205 // advance declarations for helper functions to convert register
1206 // indices to register objects
1207
1208 // the ad file has to provide implementations of certain methods
1209 // expected by the generic code
1210 //
1211 // REQUIRED FUNCTIONALITY
1212
1213 //=============================================================================
1214
1215 // !!!!! Special hack to get all types of calls to specify the byte offset
1216 // from the start of the call to the point where the return address
1217 // will point.
1218
1219 int MachCallStaticJavaNode::ret_addr_offset()
1220 {
1221 return 3 * NativeInstruction::instruction_size; // auipc + ld + jalr
1222 }
1223
1224 int MachCallDynamicJavaNode::ret_addr_offset()
1225 {
1226 return NativeMovConstReg::movptr2_instruction_size + (3 * NativeInstruction::instruction_size); // movptr2, auipc + ld + jal
1227 }
1228
1229 int MachCallRuntimeNode::ret_addr_offset() {
1230 // For address inside the code cache the call will be:
1231 // auipc + jalr
1232 // For real runtime callouts it will be 8 instructions
1233 // see riscv_enc_java_to_runtime
1234 // la(t0, retaddr) -> auipc + addi
1235 // sd(t0, Address(xthread, JavaThread::last_Java_pc_offset())) -> sd
1236 // movptr(t1, addr, offset, t0) -> lui + lui + slli + add
1237 // jalr(t1, offset) -> jalr
1238 if (CodeCache::contains(_entry_point)) {
1239 return 2 * NativeInstruction::instruction_size;
1240 } else {
1241 return 8 * NativeInstruction::instruction_size;
1242 }
1243 }
1244
1245 //
1246 // Compute padding required for nodes which need alignment
1247 //
1248
1249 // With RVC a call instruction may get 2-byte aligned.
1250 // The address of the call instruction needs to be 4-byte aligned to
1251 // ensure that it does not span a cache line so that it can be patched.
1252 int CallStaticJavaDirectNode::compute_padding(int current_offset) const
1253 {
1254 // to make sure the address of jal 4-byte aligned.
1255 return align_up(current_offset, alignment_required()) - current_offset;
1256 }
1257
1258 // With RVC a call instruction may get 2-byte aligned.
1259 // The address of the call instruction needs to be 4-byte aligned to
1260 // ensure that it does not span a cache line so that it can be patched.
1261 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const
1262 {
1263 // skip the movptr2 in MacroAssembler::ic_call():
1264 // lui, lui, slli, add, addi
1265 // Though movptr2() has already 4-byte aligned with or without RVC,
1266 // We need to prevent from further changes by explicitly calculating the size.
1267 current_offset += NativeMovConstReg::movptr2_instruction_size;
1268 // to make sure the address of jal 4-byte aligned.
1269 return align_up(current_offset, alignment_required()) - current_offset;
1270 }
1271
1272 //=============================================================================
1273
1274 #ifndef PRODUCT
1275 void MachBreakpointNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1276 assert_cond(st != nullptr);
1277 st->print("BREAKPOINT");
1278 }
1279 #endif
1280
1281 void MachBreakpointNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
1282 __ ebreak();
1283 }
1284
1285 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
1286 return MachNode::size(ra_);
1287 }
1288
1289 //=============================================================================
1290
1291 #ifndef PRODUCT
1292 void MachNopNode::format(PhaseRegAlloc*, outputStream* st) const {
1293 st->print("nop \t# %d bytes pad for loops and calls", _count);
1294 }
1295 #endif
1296
1297 void MachNopNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc*) const {
1298 Assembler::CompressibleScope scope(masm); // nops shall be 2-byte under RVC for alignment purposes.
1299 for (int i = 0; i < _count; i++) {
1300 __ nop();
1301 }
1302 }
1303
1304 uint MachNopNode::size(PhaseRegAlloc*) const {
1305 return _count * (UseRVC ? NativeInstruction::compressed_instruction_size : NativeInstruction::instruction_size);
1306 }
1307
1308 //=============================================================================
1309 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;
1310
1311 int ConstantTable::calculate_table_base_offset() const {
1312 return 0; // absolute addressing, no offset
1313 }
1314
1315 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
1316 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
1317 ShouldNotReachHere();
1318 }
1319
1320 void MachConstantBaseNode::emit(C2_MacroAssembler* masm, PhaseRegAlloc* ra_) const {
1321 // Empty encoding
1322 }
1323
1324 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
1325 return 0;
1326 }
1327
1328 #ifndef PRODUCT
1329 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1330 assert_cond(st != nullptr);
1331 st->print("-- \t// MachConstantBaseNode (empty encoding)");
1332 }
1333 #endif
1334
1335 #ifndef PRODUCT
1336 void MachPrologNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1337 assert_cond(st != nullptr && ra_ != nullptr);
1338 Compile* C = ra_->C;
1339
1340 int framesize = C->output()->frame_slots() << LogBytesPerInt;
1341
1342 if (C->output()->need_stack_bang(framesize)) {
1343 st->print("# stack bang size=%d\n\t", framesize);
1344 }
1345
1346 st->print("sd fp, [sp, #%d]\n\t", - 2 * wordSize);
1347 st->print("sd ra, [sp, #%d]\n\t", - wordSize);
1348 if (PreserveFramePointer) { st->print("sub fp, sp, #%d\n\t", 2 * wordSize); }
1349 st->print("sub sp, sp, #%d\n\t", framesize);
1350
1351 if (C->stub_function() == nullptr) {
1352 st->print("ld t0, [guard]\n\t");
1353 st->print("membar LoadLoad\n\t");
1354 st->print("ld t1, [xthread, #thread_disarmed_guard_value_offset]\n\t");
1355 st->print("beq t0, t1, skip\n\t");
1356 st->print("jalr #nmethod_entry_barrier_stub\n\t");
1357 st->print("j skip\n\t");
1358 st->print("guard: int\n\t");
1359 st->print("skip:\n\t");
1360 }
1361 }
1362 #endif
1363
1364 void MachPrologNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
1365 assert_cond(ra_ != nullptr);
1366 Compile* C = ra_->C;
1367
1368 // n.b. frame size includes space for return pc and fp
1369 const int framesize = C->output()->frame_size_in_bytes();
1370
1371 // insert a nop at the start of the prolog so we can patch in a
1372 // branch if we need to invalidate the method later
1373 {
1374 Assembler::IncompressibleScope scope(masm); // keep the nop as 4 bytes for patching.
1375 MacroAssembler::assert_alignment(__ pc());
1376 __ nop(); // 4 bytes
1377 }
1378
1379 assert_cond(C != nullptr);
1380
1381 if (C->clinit_barrier_on_entry()) {
1382 assert(!C->method()->holder()->is_not_initialized(), "initialization should have been started");
1383
1384 Label L_skip_barrier;
1385
1386 __ mov_metadata(t1, C->method()->holder()->constant_encoding());
1387 __ clinit_barrier(t1, t0, &L_skip_barrier);
1388 __ far_jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub()));
1389 __ bind(L_skip_barrier);
1390 }
1391
1392 int bangsize = C->output()->bang_size_in_bytes();
1393 if (C->output()->need_stack_bang(bangsize)) {
1394 __ generate_stack_overflow_check(bangsize);
1395 }
1396
1397 __ build_frame(framesize);
1398
1399 if (C->stub_function() == nullptr) {
1400 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
1401 // Dummy labels for just measuring the code size
1402 Label dummy_slow_path;
1403 Label dummy_continuation;
1404 Label dummy_guard;
1405 Label* slow_path = &dummy_slow_path;
1406 Label* continuation = &dummy_continuation;
1407 Label* guard = &dummy_guard;
1408 if (!Compile::current()->output()->in_scratch_emit_size()) {
1409 // Use real labels from actual stub when not emitting code for purpose of measuring its size
1410 C2EntryBarrierStub* stub = new (Compile::current()->comp_arena()) C2EntryBarrierStub();
1411 Compile::current()->output()->add_stub(stub);
1412 slow_path = &stub->entry();
1413 continuation = &stub->continuation();
1414 guard = &stub->guard();
1415 }
1416 // In the C2 code, we move the non-hot part of nmethod entry barriers out-of-line to a stub.
1417 bs->nmethod_entry_barrier(masm, slow_path, continuation, guard);
1418 }
1419
1420 if (VerifyStackAtCalls) {
1421 Unimplemented();
1422 }
1423
1424 C->output()->set_frame_complete(__ offset());
1425
1426 if (C->has_mach_constant_base_node()) {
1427 // NOTE: We set the table base offset here because users might be
1428 // emitted before MachConstantBaseNode.
1429 ConstantTable& constant_table = C->output()->constant_table();
1430 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
1431 }
1432 }
1433
1434 uint MachPrologNode::size(PhaseRegAlloc* ra_) const
1435 {
1436 assert_cond(ra_ != nullptr);
1437 return MachNode::size(ra_); // too many variables; just compute it
1438 // the hard way
1439 }
1440
1441 int MachPrologNode::reloc() const
1442 {
1443 return 0;
1444 }
1445
1446 //=============================================================================
1447
1448 #ifndef PRODUCT
1449 void MachEpilogNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1450 assert_cond(st != nullptr && ra_ != nullptr);
1451 Compile* C = ra_->C;
1452 assert_cond(C != nullptr);
1453 int framesize = C->output()->frame_size_in_bytes();
1454
1455 st->print("# pop frame %d\n\t", framesize);
1456
1457 if (framesize == 0) {
1458 st->print("ld ra, [sp,#%d]\n\t", (2 * wordSize));
1459 st->print("ld fp, [sp,#%d]\n\t", (3 * wordSize));
1460 st->print("add sp, sp, #%d\n\t", (2 * wordSize));
1461 } else {
1462 st->print("add sp, sp, #%d\n\t", framesize);
1463 st->print("ld ra, [sp,#%d]\n\t", - 2 * wordSize);
1464 st->print("ld fp, [sp,#%d]\n\t", - wordSize);
1465 }
1466
1467 if (do_polling() && C->is_method_compilation()) {
1468 st->print("# test polling word\n\t");
1469 st->print("ld t0, [xthread,#%d]\n\t", in_bytes(JavaThread::polling_word_offset()));
1470 st->print("bgtu sp, t0, #slow_path");
1471 }
1472 }
1473 #endif
1474
1475 void MachEpilogNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
1476 assert_cond(ra_ != nullptr);
1477 Compile* C = ra_->C;
1478 assert_cond(C != nullptr);
1479 int framesize = C->output()->frame_size_in_bytes();
1480
1481 __ remove_frame(framesize);
1482
1483 if (StackReservedPages > 0 && C->has_reserved_stack_access()) {
1484 __ reserved_stack_check();
1485 }
1486
1487 if (do_polling() && C->is_method_compilation()) {
1488 Label dummy_label;
1489 Label* code_stub = &dummy_label;
1490 if (!C->output()->in_scratch_emit_size()) {
1491 C2SafepointPollStub* stub = new (C->comp_arena()) C2SafepointPollStub(__ offset());
1492 C->output()->add_stub(stub);
1493 code_stub = &stub->entry();
1494 }
1495 __ relocate(relocInfo::poll_return_type);
1496 __ safepoint_poll(*code_stub, true /* at_return */, false /* acquire */, true /* in_nmethod */);
1497 }
1498 }
1499
1500 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
1501 assert_cond(ra_ != nullptr);
1502 // Variable size. Determine dynamically.
1503 return MachNode::size(ra_);
1504 }
1505
1506 int MachEpilogNode::reloc() const {
1507 // Return number of relocatable values contained in this instruction.
1508 return 1; // 1 for polling page.
1509 }
1510 const Pipeline * MachEpilogNode::pipeline() const {
1511 return MachNode::pipeline_class();
1512 }
1513
1514 //=============================================================================
1515
1516 // Figure out which register class each belongs in: rc_int, rc_float or
1517 // rc_stack.
1518 enum RC { rc_bad, rc_int, rc_float, rc_vector, rc_stack };
1519
1520 static enum RC rc_class(OptoReg::Name reg) {
1521
1522 if (reg == OptoReg::Bad) {
1523 return rc_bad;
1524 }
1525
1526 // we have 30 int registers * 2 halves
1527 // (t0 and t1 are omitted)
1528 int slots_of_int_registers = Register::max_slots_per_register * (Register::number_of_registers - 2);
1529 if (reg < slots_of_int_registers) {
1530 return rc_int;
1531 }
1532
1533 // we have 32 float register * 2 halves
1534 int slots_of_float_registers = FloatRegister::max_slots_per_register * FloatRegister::number_of_registers;
1535 if (reg < slots_of_int_registers + slots_of_float_registers) {
1536 return rc_float;
1537 }
1538
1539 // we have 32 vector register * 4 halves
1540 int slots_of_vector_registers = VectorRegister::max_slots_per_register * VectorRegister::number_of_registers;
1541 if (reg < slots_of_int_registers + slots_of_float_registers + slots_of_vector_registers) {
1542 return rc_vector;
1543 }
1544
1545 // Between vector regs & stack is the flags regs.
1546 assert(OptoReg::is_stack(reg), "blow up if spilling flags");
1547
1548 return rc_stack;
1549 }
1550
1551 uint MachSpillCopyNode::implementation(C2_MacroAssembler *masm, PhaseRegAlloc *ra_, bool do_size, outputStream *st) const {
1552 assert_cond(ra_ != nullptr);
1553 Compile* C = ra_->C;
1554
1555 // Get registers to move.
1556 OptoReg::Name src_hi = ra_->get_reg_second(in(1));
1557 OptoReg::Name src_lo = ra_->get_reg_first(in(1));
1558 OptoReg::Name dst_hi = ra_->get_reg_second(this);
1559 OptoReg::Name dst_lo = ra_->get_reg_first(this);
1560
1561 enum RC src_hi_rc = rc_class(src_hi);
1562 enum RC src_lo_rc = rc_class(src_lo);
1563 enum RC dst_hi_rc = rc_class(dst_hi);
1564 enum RC dst_lo_rc = rc_class(dst_lo);
1565
1566 assert(src_lo != OptoReg::Bad && dst_lo != OptoReg::Bad, "must move at least 1 register");
1567
1568 if (src_hi != OptoReg::Bad && !bottom_type()->isa_vectmask()) {
1569 assert((src_lo & 1) == 0 && src_lo + 1 == src_hi &&
1570 (dst_lo & 1) == 0 && dst_lo + 1 == dst_hi,
1571 "expected aligned-adjacent pairs");
1572 }
1573
1574 if (src_lo == dst_lo && src_hi == dst_hi) {
1575 return 0; // Self copy, no move.
1576 }
1577
1578 bool is64 = (src_lo & 1) == 0 && src_lo + 1 == src_hi &&
1579 (dst_lo & 1) == 0 && dst_lo + 1 == dst_hi;
1580 int src_offset = ra_->reg2offset(src_lo);
1581 int dst_offset = ra_->reg2offset(dst_lo);
1582
1583 if (bottom_type()->isa_vect() != nullptr) {
1584 uint ireg = ideal_reg();
1585 if (ireg == Op_VecA && masm) {
1586 int vector_reg_size_in_bytes = Matcher::scalable_vector_reg_size(T_BYTE);
1587 if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
1588 // stack to stack
1589 __ spill_copy_vector_stack_to_stack(src_offset, dst_offset,
1590 vector_reg_size_in_bytes);
1591 } else if (src_lo_rc == rc_vector && dst_lo_rc == rc_stack) {
1592 // vpr to stack
1593 __ spill(as_VectorRegister(Matcher::_regEncode[src_lo]), ra_->reg2offset(dst_lo));
1594 } else if (src_lo_rc == rc_stack && dst_lo_rc == rc_vector) {
1595 // stack to vpr
1596 __ unspill(as_VectorRegister(Matcher::_regEncode[dst_lo]), ra_->reg2offset(src_lo));
1597 } else if (src_lo_rc == rc_vector && dst_lo_rc == rc_vector) {
1598 // vpr to vpr
1599 __ vsetvli_helper(T_BYTE, MaxVectorSize);
1600 __ vmv_v_v(as_VectorRegister(Matcher::_regEncode[dst_lo]), as_VectorRegister(Matcher::_regEncode[src_lo]));
1601 } else {
1602 ShouldNotReachHere();
1603 }
1604 } else if (bottom_type()->isa_vectmask() && masm) {
1605 int vmask_size_in_bytes = Matcher::scalable_predicate_reg_slots() * 32 / 8;
1606 if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
1607 // stack to stack
1608 __ spill_copy_vmask_stack_to_stack(src_offset, dst_offset,
1609 vmask_size_in_bytes);
1610 } else if (src_lo_rc == rc_vector && dst_lo_rc == rc_stack) {
1611 // vmask to stack
1612 __ spill_vmask(as_VectorRegister(Matcher::_regEncode[src_lo]), ra_->reg2offset(dst_lo));
1613 } else if (src_lo_rc == rc_stack && dst_lo_rc == rc_vector) {
1614 // stack to vmask
1615 __ unspill_vmask(as_VectorRegister(Matcher::_regEncode[dst_lo]), ra_->reg2offset(src_lo));
1616 } else if (src_lo_rc == rc_vector && dst_lo_rc == rc_vector) {
1617 // vmask to vmask
1618 __ vsetvli_helper(T_BYTE, MaxVectorSize >> 3);
1619 __ vmv_v_v(as_VectorRegister(Matcher::_regEncode[dst_lo]), as_VectorRegister(Matcher::_regEncode[src_lo]));
1620 } else {
1621 ShouldNotReachHere();
1622 }
1623 }
1624 } else if (masm != nullptr) {
1625 switch (src_lo_rc) {
1626 case rc_int:
1627 if (dst_lo_rc == rc_int) { // gpr --> gpr copy
1628 if (!is64 && this->ideal_reg() != Op_RegI) { // zero extended for narrow oop or klass
1629 __ zext(as_Register(Matcher::_regEncode[dst_lo]), as_Register(Matcher::_regEncode[src_lo]), 32);
1630 } else {
1631 __ mv(as_Register(Matcher::_regEncode[dst_lo]), as_Register(Matcher::_regEncode[src_lo]));
1632 }
1633 } else if (dst_lo_rc == rc_float) { // gpr --> fpr copy
1634 if (is64) {
1635 __ fmv_d_x(as_FloatRegister(Matcher::_regEncode[dst_lo]),
1636 as_Register(Matcher::_regEncode[src_lo]));
1637 } else {
1638 __ fmv_w_x(as_FloatRegister(Matcher::_regEncode[dst_lo]),
1639 as_Register(Matcher::_regEncode[src_lo]));
1640 }
1641 } else { // gpr --> stack spill
1642 assert(dst_lo_rc == rc_stack, "spill to bad register class");
1643 __ spill(as_Register(Matcher::_regEncode[src_lo]), is64, dst_offset);
1644 }
1645 break;
1646 case rc_float:
1647 if (dst_lo_rc == rc_int) { // fpr --> gpr copy
1648 if (is64) {
1649 __ fmv_x_d(as_Register(Matcher::_regEncode[dst_lo]),
1650 as_FloatRegister(Matcher::_regEncode[src_lo]));
1651 } else {
1652 __ fmv_x_w(as_Register(Matcher::_regEncode[dst_lo]),
1653 as_FloatRegister(Matcher::_regEncode[src_lo]));
1654 }
1655 } else if (dst_lo_rc == rc_float) { // fpr --> fpr copy
1656 if (is64) {
1657 __ fmv_d(as_FloatRegister(Matcher::_regEncode[dst_lo]),
1658 as_FloatRegister(Matcher::_regEncode[src_lo]));
1659 } else {
1660 __ fmv_s(as_FloatRegister(Matcher::_regEncode[dst_lo]),
1661 as_FloatRegister(Matcher::_regEncode[src_lo]));
1662 }
1663 } else { // fpr --> stack spill
1664 assert(dst_lo_rc == rc_stack, "spill to bad register class");
1665 __ spill(as_FloatRegister(Matcher::_regEncode[src_lo]),
1666 is64, dst_offset);
1667 }
1668 break;
1669 case rc_stack:
1670 if (dst_lo_rc == rc_int) { // stack --> gpr load
1671 if (this->ideal_reg() == Op_RegI) {
1672 __ unspill(as_Register(Matcher::_regEncode[dst_lo]), is64, src_offset);
1673 } else { // // zero extended for narrow oop or klass
1674 __ unspillu(as_Register(Matcher::_regEncode[dst_lo]), is64, src_offset);
1675 }
1676 } else if (dst_lo_rc == rc_float) { // stack --> fpr load
1677 __ unspill(as_FloatRegister(Matcher::_regEncode[dst_lo]),
1678 is64, src_offset);
1679 } else { // stack --> stack copy
1680 assert(dst_lo_rc == rc_stack, "spill to bad register class");
1681 if (this->ideal_reg() == Op_RegI) {
1682 __ unspill(t0, is64, src_offset);
1683 } else { // zero extended for narrow oop or klass
1684 __ unspillu(t0, is64, src_offset);
1685 }
1686 __ spill(t0, is64, dst_offset);
1687 }
1688 break;
1689 default:
1690 ShouldNotReachHere();
1691 }
1692 }
1693
1694 if (st != nullptr) {
1695 st->print("spill ");
1696 if (src_lo_rc == rc_stack) {
1697 st->print("[sp, #%d] -> ", src_offset);
1698 } else {
1699 st->print("%s -> ", Matcher::regName[src_lo]);
1700 }
1701 if (dst_lo_rc == rc_stack) {
1702 st->print("[sp, #%d]", dst_offset);
1703 } else {
1704 st->print("%s", Matcher::regName[dst_lo]);
1705 }
1706 if (bottom_type()->isa_vect() && !bottom_type()->isa_vectmask()) {
1707 int vsize = 0;
1708 if (ideal_reg() == Op_VecA) {
1709 vsize = Matcher::scalable_vector_reg_size(T_BYTE) * 8;
1710 } else {
1711 ShouldNotReachHere();
1712 }
1713 st->print("\t# vector spill size = %d", vsize);
1714 } else if (ideal_reg() == Op_RegVectMask) {
1715 assert(Matcher::supports_scalable_vector(), "bad register type for spill");
1716 int vsize = Matcher::scalable_predicate_reg_slots() * 32;
1717 st->print("\t# vmask spill size = %d", vsize);
1718 } else {
1719 st->print("\t# spill size = %d", is64 ? 64 : 32);
1720 }
1721 }
1722
1723 return 0;
1724 }
1725
1726 #ifndef PRODUCT
1727 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1728 if (ra_ == nullptr) {
1729 st->print("N%d = SpillCopy(N%d)", _idx, in(1)->_idx);
1730 } else {
1731 implementation(nullptr, ra_, false, st);
1732 }
1733 }
1734 #endif
1735
1736 void MachSpillCopyNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
1737 implementation(masm, ra_, false, nullptr);
1738 }
1739
1740 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1741 return MachNode::size(ra_);
1742 }
1743
1744 //=============================================================================
1745
1746 #ifndef PRODUCT
1747 void BoxLockNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1748 assert_cond(ra_ != nullptr && st != nullptr);
1749 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1750 int reg = ra_->get_reg_first(this);
1751 st->print("add %s, sp, #%d\t# box lock",
1752 Matcher::regName[reg], offset);
1753 }
1754 #endif
1755
1756 void BoxLockNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
1757 Assembler::IncompressibleScope scope(masm); // Fixed length: see BoxLockNode::size()
1758
1759 assert_cond(ra_ != nullptr);
1760 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1761 int reg = ra_->get_encode(this);
1762
1763 if (Assembler::is_simm12(offset)) {
1764 __ addi(as_Register(reg), sp, offset);
1765 } else {
1766 __ li32(t0, offset);
1767 __ add(as_Register(reg), sp, t0);
1768 }
1769 }
1770
1771 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1772 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_).
1773 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1774
1775 if (Assembler::is_simm12(offset)) {
1776 return NativeInstruction::instruction_size;
1777 } else {
1778 return 3 * NativeInstruction::instruction_size; // lui + addiw + add;
1779 }
1780 }
1781
1782 //=============================================================================
1783
1784 #ifndef PRODUCT
1785 void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1786 {
1787 assert_cond(st != nullptr);
1788 st->print_cr("# MachUEPNode");
1789 if (UseCompressedClassPointers) {
1790 st->print_cr("\tlwu t1, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass");
1791 st->print_cr("\tlwu t2, [t0 + CompiledICData::speculated_klass_offset()]\t# compressed klass");
1792 } else {
1793 st->print_cr("\tld t1, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass");
1794 st->print_cr("\tld t2, [t0 + CompiledICData::speculated_klass_offset()]\t# compressed klass");
1795 }
1796 st->print_cr("\tbeq t1, t2, ic_hit");
1797 st->print_cr("\tj, SharedRuntime::_ic_miss_stub\t # Inline cache check");
1798 st->print_cr("\tic_hit:");
1799 }
1800 #endif
1801
1802 void MachUEPNode::emit(C2_MacroAssembler* masm, PhaseRegAlloc* ra_) const
1803 {
1804 // This is the unverified entry point.
1805 __ ic_check(CodeEntryAlignment);
1806
1807 // Verified entry point must be properly 4 bytes aligned for patching by NativeJump::patch_verified_entry().
1808 // ic_check() aligns to CodeEntryAlignment >= InteriorEntryAlignment(min 16) > NativeInstruction::instruction_size(4).
1809 assert(((__ offset()) % CodeEntryAlignment) == 0, "Misaligned verified entry point");
1810 }
1811
1812 uint MachUEPNode::size(PhaseRegAlloc* ra_) const
1813 {
1814 assert_cond(ra_ != nullptr);
1815 return MachNode::size(ra_);
1816 }
1817
1818 // REQUIRED EMIT CODE
1819
1820 //=============================================================================
1821
1822 // Emit exception handler code.
1823 int HandlerImpl::emit_exception_handler(C2_MacroAssembler* masm)
1824 {
1825 // auipc t1, #exception_blob_entry_point
1826 // jr (offset)t1
1827 // Note that the code buffer's insts_mark is always relative to insts.
1828 // That's why we must use the macroassembler to generate a handler.
1829 address base = __ start_a_stub(size_exception_handler());
1830 if (base == nullptr) {
1831 ciEnv::current()->record_failure("CodeCache is full");
1832 return 0; // CodeBuffer::expand failed
1833 }
1834 int offset = __ offset();
1835 __ far_jump(RuntimeAddress(OptoRuntime::exception_blob()->entry_point()));
1836 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1837 __ end_a_stub();
1838 return offset;
1839 }
1840
1841 // Emit deopt handler code.
1842 int HandlerImpl::emit_deopt_handler(C2_MacroAssembler* masm)
1843 {
1844 address base = __ start_a_stub(size_deopt_handler());
1845 if (base == nullptr) {
1846 ciEnv::current()->record_failure("CodeCache is full");
1847 return 0; // CodeBuffer::expand failed
1848 }
1849 int offset = __ offset();
1850
1851 __ auipc(ra, 0);
1852 __ far_jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
1853
1854 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1855 __ end_a_stub();
1856 return offset;
1857
1858 }
1859 // REQUIRED MATCHER CODE
1860
1861 //=============================================================================
1862
1863 bool Matcher::match_rule_supported(int opcode) {
1864 if (!has_match_rule(opcode)) {
1865 return false;
1866 }
1867
1868 switch (opcode) {
1869 case Op_OnSpinWait:
1870 return VM_Version::supports_on_spin_wait();
1871 case Op_CacheWB: // fall through
1872 case Op_CacheWBPreSync: // fall through
1873 case Op_CacheWBPostSync:
1874 if (!VM_Version::supports_data_cache_line_flush()) {
1875 return false;
1876 }
1877 break;
1878
1879 case Op_StrCompressedCopy: // fall through
1880 case Op_StrInflatedCopy: // fall through
1881 case Op_CountPositives: // fall through
1882 case Op_EncodeISOArray:
1883 return UseRVV;
1884
1885 // Current test shows that, it brings performance gain when MaxVectorSize >= 32, but brings
1886 // regression when MaxVectorSize == 16. So only enable the intrinsic when MaxVectorSize >= 32.
1887 case Op_RoundVF:
1888 return UseRVV && MaxVectorSize >= 32;
1889
1890 // For double, current test shows that even with MaxVectorSize == 32, there is still some regression.
1891 // Although there is no hardware to verify it for now, from the trend of performance data on hardwares
1892 // (with vlenb == 16 and 32 respectively), it's promising to bring better performance rather than
1893 // regression for double when MaxVectorSize == 64+. So only enable the intrinsic when MaxVectorSize >= 64.
1894 case Op_RoundVD:
1895 return UseRVV && MaxVectorSize >= 64;
1896
1897 case Op_PopCountI:
1898 case Op_PopCountL:
1899 return UsePopCountInstruction;
1900
1901 case Op_ReverseI:
1902 case Op_ReverseL:
1903 return UseZbkb;
1904
1905 case Op_ReverseBytesI:
1906 case Op_ReverseBytesL:
1907 case Op_ReverseBytesS:
1908 case Op_ReverseBytesUS:
1909 case Op_RotateRight:
1910 case Op_RotateLeft:
1911 case Op_CountLeadingZerosI:
1912 case Op_CountLeadingZerosL:
1913 case Op_CountTrailingZerosI:
1914 case Op_CountTrailingZerosL:
1915 return UseZbb;
1916
1917 case Op_FmaF:
1918 case Op_FmaD:
1919 return UseFMA;
1920 case Op_FmaVF:
1921 case Op_FmaVD:
1922 return UseRVV && UseFMA;
1923
1924 case Op_ConvHF2F:
1925 case Op_ConvF2HF:
1926 return VM_Version::supports_float16_float_conversion();
1927 case Op_ReinterpretS2HF:
1928 case Op_ReinterpretHF2S:
1929 return UseZfh || UseZfhmin;
1930 case Op_AddHF:
1931 case Op_DivHF:
1932 case Op_FmaHF:
1933 case Op_MaxHF:
1934 case Op_MinHF:
1935 case Op_MulHF:
1936 case Op_SubHF:
1937 case Op_SqrtHF:
1938 return UseZfh;
1939
1940 case Op_CMoveF:
1941 case Op_CMoveD:
1942 case Op_CMoveP:
1943 case Op_CMoveN:
1944 return false;
1945 }
1946
1947 return true; // Per default match rules are supported.
1948 }
1949
1950 const RegMask* Matcher::predicate_reg_mask(void) {
1951 return &_VMASK_REG_mask;
1952 }
1953
1954 // Vector calling convention not yet implemented.
1955 bool Matcher::supports_vector_calling_convention(void) {
1956 return EnableVectorSupport;
1957 }
1958
1959 OptoRegPair Matcher::vector_return_value(uint ideal_reg) {
1960 assert(EnableVectorSupport, "sanity");
1961 assert(ideal_reg == Op_VecA, "sanity");
1962 // check more info at https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-cc.adoc
1963 int lo = V8_num;
1964 int hi = V8_K_num;
1965 return OptoRegPair(hi, lo);
1966 }
1967
1968 // Is this branch offset short enough that a short branch can be used?
1969 //
1970 // NOTE: If the platform does not provide any short branch variants, then
1971 // this method should return false for offset 0.
1972 // |---label(L1)-----|
1973 // |-----------------|
1974 // |-----------------|----------eq: float-------------------
1975 // |-----------------| // far_cmpD_branch | cmpD_branch
1976 // |------- ---------| feq; | feq;
1977 // |-far_cmpD_branch-| beqz done; | bnez L;
1978 // |-----------------| j L; |
1979 // |-----------------| bind(done); |
1980 // |-----------------|--------------------------------------
1981 // |-----------------| // so shortBrSize = br_size - 4;
1982 // |-----------------| // so offs = offset - shortBrSize + 4;
1983 // |---label(L2)-----|
1984 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1985 // The passed offset is relative to address of the branch.
1986 int shortBrSize = br_size - 4;
1987 int offs = offset - shortBrSize + 4;
1988 return (-4096 <= offs && offs < 4096);
1989 }
1990
1991 // Vector width in bytes.
1992 int Matcher::vector_width_in_bytes(BasicType bt) {
1993 if (UseRVV) {
1994 // The MaxVectorSize should have been set by detecting RVV max vector register size when check UseRVV.
1995 // MaxVectorSize == VM_Version::_initial_vector_length
1996 int size = MaxVectorSize;
1997 // Minimum 2 values in vector
1998 if (size < 2 * type2aelembytes(bt)) size = 0;
1999 // But never < 4
2000 if (size < 4) size = 0;
2001 return size;
2002 }
2003 return 0;
2004 }
2005
2006 // Limits on vector size (number of elements) loaded into vector.
2007 int Matcher::max_vector_size(const BasicType bt) {
2008 return vector_width_in_bytes(bt) / type2aelembytes(bt);
2009 }
2010
2011 int Matcher::min_vector_size(const BasicType bt) {
2012 int max_size = max_vector_size(bt);
2013 // Limit the min vector size to 8 bytes.
2014 int size = 8 / type2aelembytes(bt);
2015 if (bt == T_BYTE) {
2016 // To support vector api shuffle/rearrange.
2017 size = 4;
2018 } else if (bt == T_BOOLEAN) {
2019 // To support vector api load/store mask.
2020 size = 2;
2021 }
2022 if (size < 2) size = 2;
2023 return MIN2(size, max_size);
2024 }
2025
2026 int Matcher::max_vector_size_auto_vectorization(const BasicType bt) {
2027 return Matcher::max_vector_size(bt);
2028 }
2029
2030 // Vector ideal reg.
2031 uint Matcher::vector_ideal_reg(int len) {
2032 assert(MaxVectorSize >= len, "");
2033 if (UseRVV) {
2034 return Op_VecA;
2035 }
2036
2037 ShouldNotReachHere();
2038 return 0;
2039 }
2040
2041 int Matcher::scalable_vector_reg_size(const BasicType bt) {
2042 return Matcher::max_vector_size(bt);
2043 }
2044
2045 MachOper* Matcher::pd_specialize_generic_vector_operand(MachOper* original_opnd, uint ideal_reg, bool is_temp) {
2046 ShouldNotReachHere(); // generic vector operands not supported
2047 return nullptr;
2048 }
2049
2050 bool Matcher::is_reg2reg_move(MachNode* m) {
2051 ShouldNotReachHere(); // generic vector operands not supported
2052 return false;
2053 }
2054
2055 bool Matcher::is_generic_vector(MachOper* opnd) {
2056 ShouldNotReachHere(); // generic vector operands not supported
2057 return false;
2058 }
2059
2060 // Return whether or not this register is ever used as an argument.
2061 // This function is used on startup to build the trampoline stubs in
2062 // generateOptoStub. Registers not mentioned will be killed by the VM
2063 // call in the trampoline, and arguments in those registers not be
2064 // available to the callee.
2065 bool Matcher::can_be_java_arg(int reg)
2066 {
2067 return
2068 reg == R10_num || reg == R10_H_num ||
2069 reg == R11_num || reg == R11_H_num ||
2070 reg == R12_num || reg == R12_H_num ||
2071 reg == R13_num || reg == R13_H_num ||
2072 reg == R14_num || reg == R14_H_num ||
2073 reg == R15_num || reg == R15_H_num ||
2074 reg == R16_num || reg == R16_H_num ||
2075 reg == R17_num || reg == R17_H_num ||
2076 reg == F10_num || reg == F10_H_num ||
2077 reg == F11_num || reg == F11_H_num ||
2078 reg == F12_num || reg == F12_H_num ||
2079 reg == F13_num || reg == F13_H_num ||
2080 reg == F14_num || reg == F14_H_num ||
2081 reg == F15_num || reg == F15_H_num ||
2082 reg == F16_num || reg == F16_H_num ||
2083 reg == F17_num || reg == F17_H_num;
2084 }
2085
2086 bool Matcher::is_spillable_arg(int reg)
2087 {
2088 return can_be_java_arg(reg);
2089 }
2090
2091 uint Matcher::int_pressure_limit()
2092 {
2093 // A derived pointer is live at CallNode and then is flagged by RA
2094 // as a spilled LRG. Spilling heuristics(Spill-USE) explicitly skip
2095 // derived pointers and lastly fail to spill after reaching maximum
2096 // number of iterations. Lowering the default pressure threshold to
2097 // (_NO_SPECIAL_REG32_mask.Size() minus 1) forces CallNode to become
2098 // a high register pressure area of the code so that split_DEF can
2099 // generate DefinitionSpillCopy for the derived pointer.
2100 uint default_int_pressure_threshold = _NO_SPECIAL_REG32_mask.Size() - 1;
2101 if (!PreserveFramePointer) {
2102 // When PreserveFramePointer is off, frame pointer is allocatable,
2103 // but different from other SOC registers, it is excluded from
2104 // fatproj's mask because its save type is No-Save. Decrease 1 to
2105 // ensure high pressure at fatproj when PreserveFramePointer is off.
2106 // See check_pressure_at_fatproj().
2107 default_int_pressure_threshold--;
2108 }
2109 return (INTPRESSURE == -1) ? default_int_pressure_threshold : INTPRESSURE;
2110 }
2111
2112 uint Matcher::float_pressure_limit()
2113 {
2114 // _FLOAT_REG_mask is generated by adlc from the float_reg register class.
2115 return (FLOATPRESSURE == -1) ? _FLOAT_REG_mask.Size() : FLOATPRESSURE;
2116 }
2117
2118 bool Matcher::use_asm_for_ldiv_by_con(jlong divisor) {
2119 return false;
2120 }
2121
2122 RegMask Matcher::divI_proj_mask() {
2123 ShouldNotReachHere();
2124 return RegMask();
2125 }
2126
2127 // Register for MODI projection of divmodI.
2128 RegMask Matcher::modI_proj_mask() {
2129 ShouldNotReachHere();
2130 return RegMask();
2131 }
2132
2133 // Register for DIVL projection of divmodL.
2134 RegMask Matcher::divL_proj_mask() {
2135 ShouldNotReachHere();
2136 return RegMask();
2137 }
2138
2139 // Register for MODL projection of divmodL.
2140 RegMask Matcher::modL_proj_mask() {
2141 ShouldNotReachHere();
2142 return RegMask();
2143 }
2144
2145 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
2146 return FP_REG_mask();
2147 }
2148
2149 bool size_fits_all_mem_uses(AddPNode* addp, int shift) {
2150 assert_cond(addp != nullptr);
2151 for (DUIterator_Fast imax, i = addp->fast_outs(imax); i < imax; i++) {
2152 Node* u = addp->fast_out(i);
2153 if (u != nullptr && u->is_Mem()) {
2154 int opsize = u->as_Mem()->memory_size();
2155 assert(opsize > 0, "unexpected memory operand size");
2156 if (u->as_Mem()->memory_size() != (1 << shift)) {
2157 return false;
2158 }
2159 }
2160 }
2161 return true;
2162 }
2163
2164 // Binary src (Replicate scalar/immediate)
2165 static bool is_vector_scalar_bitwise_pattern(Node* n, Node* m) {
2166 if (n == nullptr || m == nullptr) {
2167 return false;
2168 }
2169
2170 if (m->Opcode() != Op_Replicate) {
2171 return false;
2172 }
2173
2174 switch (n->Opcode()) {
2175 case Op_AndV:
2176 case Op_OrV:
2177 case Op_XorV:
2178 case Op_AddVB:
2179 case Op_AddVS:
2180 case Op_AddVI:
2181 case Op_AddVL:
2182 case Op_SubVB:
2183 case Op_SubVS:
2184 case Op_SubVI:
2185 case Op_SubVL:
2186 case Op_MulVB:
2187 case Op_MulVS:
2188 case Op_MulVI:
2189 case Op_MulVL: {
2190 return true;
2191 }
2192 default:
2193 return false;
2194 }
2195 }
2196
2197 // (XorV src (Replicate m1))
2198 // (XorVMask src (MaskAll m1))
2199 static bool is_vector_bitwise_not_pattern(Node* n, Node* m) {
2200 if (n != nullptr && m != nullptr) {
2201 return (n->Opcode() == Op_XorV || n->Opcode() == Op_XorVMask) &&
2202 VectorNode::is_all_ones_vector(m);
2203 }
2204 return false;
2205 }
2206
2207 // Should the Matcher clone input 'm' of node 'n'?
2208 bool Matcher::pd_clone_node(Node* n, Node* m, Matcher::MStack& mstack) {
2209 assert_cond(m != nullptr);
2210 if (is_vshift_con_pattern(n, m) || // ShiftV src (ShiftCntV con)
2211 is_vector_bitwise_not_pattern(n, m) ||
2212 is_vector_scalar_bitwise_pattern(n, m) ||
2213 is_encode_and_store_pattern(n, m)) {
2214 mstack.push(m, Visit);
2215 return true;
2216 }
2217 return false;
2218 }
2219
2220 // Should the Matcher clone shifts on addressing modes, expecting them
2221 // to be subsumed into complex addressing expressions or compute them
2222 // into registers?
2223 bool Matcher::pd_clone_address_expressions(AddPNode* m, Matcher::MStack& mstack, VectorSet& address_visited) {
2224 return clone_base_plus_offset_address(m, mstack, address_visited);
2225 }
2226
2227 %}
2228
2229
2230
2231 //----------ENCODING BLOCK-----------------------------------------------------
2232 // This block specifies the encoding classes used by the compiler to
2233 // output byte streams. Encoding classes are parameterized macros
2234 // used by Machine Instruction Nodes in order to generate the bit
2235 // encoding of the instruction. Operands specify their base encoding
2236 // interface with the interface keyword. There are currently
2237 // supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, &
2238 // COND_INTER. REG_INTER causes an operand to generate a function
2239 // which returns its register number when queried. CONST_INTER causes
2240 // an operand to generate a function which returns the value of the
2241 // constant when queried. MEMORY_INTER causes an operand to generate
2242 // four functions which return the Base Register, the Index Register,
2243 // the Scale Value, and the Offset Value of the operand when queried.
2244 // COND_INTER causes an operand to generate six functions which return
2245 // the encoding code (ie - encoding bits for the instruction)
2246 // associated with each basic boolean condition for a conditional
2247 // instruction.
2248 //
2249 // Instructions specify two basic values for encoding. Again, a
2250 // function is available to check if the constant displacement is an
2251 // oop. They use the ins_encode keyword to specify their encoding
2252 // classes (which must be a sequence of enc_class names, and their
2253 // parameters, specified in the encoding block), and they use the
2254 // opcode keyword to specify, in order, their primary, secondary, and
2255 // tertiary opcode. Only the opcode sections which a particular
2256 // instruction needs for encoding need to be specified.
2257 encode %{
2258 // BEGIN Non-volatile memory access
2259
2260 enc_class riscv_enc_mov_imm(iRegIorL dst, immIorL src) %{
2261 int64_t con = (int64_t)$src$$constant;
2262 Register dst_reg = as_Register($dst$$reg);
2263 __ mv(dst_reg, con);
2264 %}
2265
2266 enc_class riscv_enc_mov_p(iRegP dst, immP src) %{
2267 Register dst_reg = as_Register($dst$$reg);
2268 address con = (address)$src$$constant;
2269 if (con == nullptr || con == (address)1) {
2270 ShouldNotReachHere();
2271 } else {
2272 relocInfo::relocType rtype = $src->constant_reloc();
2273 if (rtype == relocInfo::oop_type) {
2274 __ movoop(dst_reg, (jobject)con);
2275 } else if (rtype == relocInfo::metadata_type) {
2276 __ mov_metadata(dst_reg, (Metadata*)con);
2277 } else {
2278 assert(rtype == relocInfo::none, "unexpected reloc type");
2279 __ mv(dst_reg, $src$$constant);
2280 }
2281 }
2282 %}
2283
2284 enc_class riscv_enc_mov_p1(iRegP dst) %{
2285 Register dst_reg = as_Register($dst$$reg);
2286 __ mv(dst_reg, 1);
2287 %}
2288
2289 enc_class riscv_enc_mov_byte_map_base(iRegP dst) %{
2290 __ load_byte_map_base($dst$$Register);
2291 %}
2292
2293 enc_class riscv_enc_mov_n(iRegN dst, immN src) %{
2294 Register dst_reg = as_Register($dst$$reg);
2295 address con = (address)$src$$constant;
2296 if (con == nullptr) {
2297 ShouldNotReachHere();
2298 } else {
2299 relocInfo::relocType rtype = $src->constant_reloc();
2300 assert(rtype == relocInfo::oop_type, "unexpected reloc type");
2301 __ set_narrow_oop(dst_reg, (jobject)con);
2302 }
2303 %}
2304
2305 enc_class riscv_enc_mov_zero(iRegNorP dst) %{
2306 Register dst_reg = as_Register($dst$$reg);
2307 __ mv(dst_reg, zr);
2308 %}
2309
2310 enc_class riscv_enc_mov_nk(iRegN dst, immNKlass src) %{
2311 Register dst_reg = as_Register($dst$$reg);
2312 address con = (address)$src$$constant;
2313 if (con == nullptr) {
2314 ShouldNotReachHere();
2315 } else {
2316 relocInfo::relocType rtype = $src->constant_reloc();
2317 assert(rtype == relocInfo::metadata_type, "unexpected reloc type");
2318 __ set_narrow_klass(dst_reg, (Klass *)con);
2319 }
2320 %}
2321
2322 enc_class riscv_enc_cmpxchgw(iRegINoSp res, memory mem, iRegI oldval, iRegI newval) %{
2323 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
2324 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
2325 /*result as bool*/ true);
2326 %}
2327
2328 enc_class riscv_enc_cmpxchgn(iRegINoSp res, memory mem, iRegI oldval, iRegI newval) %{
2329 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
2330 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
2331 /*result as bool*/ true);
2332 %}
2333
2334 enc_class riscv_enc_cmpxchg(iRegINoSp res, memory mem, iRegL oldval, iRegL newval) %{
2335 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
2336 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
2337 /*result as bool*/ true);
2338 %}
2339
2340 enc_class riscv_enc_cmpxchgw_acq(iRegINoSp res, memory mem, iRegI oldval, iRegI newval) %{
2341 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
2342 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
2343 /*result as bool*/ true);
2344 %}
2345
2346 enc_class riscv_enc_cmpxchgn_acq(iRegINoSp res, memory mem, iRegI oldval, iRegI newval) %{
2347 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
2348 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
2349 /*result as bool*/ true);
2350 %}
2351
2352 enc_class riscv_enc_cmpxchg_acq(iRegINoSp res, memory mem, iRegL oldval, iRegL newval) %{
2353 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
2354 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
2355 /*result as bool*/ true);
2356 %}
2357
2358 // compare and branch instruction encodings
2359
2360 enc_class riscv_enc_j(label lbl) %{
2361 Label* L = $lbl$$label;
2362 __ j(*L);
2363 %}
2364
2365 enc_class riscv_enc_far_cmpULtGe_imm0_branch(cmpOpULtGe cmp, iRegIorL op1, label lbl) %{
2366 Label* L = $lbl$$label;
2367 switch ($cmp$$cmpcode) {
2368 case(BoolTest::ge):
2369 __ j(*L);
2370 break;
2371 case(BoolTest::lt):
2372 break;
2373 default:
2374 Unimplemented();
2375 }
2376 %}
2377
2378 // call instruction encodings
2379
2380 enc_class riscv_enc_partial_subtype_check(iRegP sub, iRegP super, iRegP temp, iRegP result) %{
2381 Register sub_reg = as_Register($sub$$reg);
2382 Register super_reg = as_Register($super$$reg);
2383 Register temp_reg = as_Register($temp$$reg);
2384 Register result_reg = as_Register($result$$reg);
2385 Register cr_reg = t1;
2386
2387 Label miss;
2388 Label done;
2389 __ check_klass_subtype_slow_path(sub_reg, super_reg, temp_reg, result_reg,
2390 nullptr, &miss, /*set_cond_codes*/ true);
2391 if ($primary) {
2392 __ mv(result_reg, zr);
2393 } else {
2394 __ mv(cr_reg, zr);
2395 __ j(done);
2396 }
2397
2398 __ bind(miss);
2399 if (!$primary) {
2400 __ mv(cr_reg, 1);
2401 }
2402
2403 __ bind(done);
2404 %}
2405
2406 enc_class riscv_enc_java_static_call(method meth) %{
2407 Assembler::IncompressibleScope scope(masm); // Fixed length: see ret_addr_offset
2408
2409 address addr = (address)$meth$$method;
2410 address call = nullptr;
2411 assert_cond(addr != nullptr);
2412 if (!_method) {
2413 // A call to a runtime wrapper, e.g. new, new_typeArray_Java, uncommon_trap.
2414 call = __ reloc_call(Address(addr, relocInfo::runtime_call_type));
2415 if (call == nullptr) {
2416 ciEnv::current()->record_failure("CodeCache is full");
2417 return;
2418 }
2419 } else if (_method->intrinsic_id() == vmIntrinsicID::_ensureMaterializedForStackWalk) {
2420 // The NOP here is purely to ensure that eliding a call to
2421 // JVM_EnsureMaterializedForStackWalk doesn't change the code size.
2422 __ nop();
2423 __ nop();
2424 __ nop();
2425 __ block_comment("call JVM_EnsureMaterializedForStackWalk (elided)");
2426 } else {
2427 int method_index = resolved_method_index(masm);
2428 RelocationHolder rspec = _optimized_virtual ? opt_virtual_call_Relocation::spec(method_index)
2429 : static_call_Relocation::spec(method_index);
2430 call = __ reloc_call(Address(addr, rspec));
2431 if (call == nullptr) {
2432 ciEnv::current()->record_failure("CodeCache is full");
2433 return;
2434 }
2435
2436 if (CodeBuffer::supports_shared_stubs() && _method->can_be_statically_bound()) {
2437 // Calls of the same statically bound method can share
2438 // a stub to the interpreter.
2439 __ code()->shared_stub_to_interp_for(_method, call - (__ begin()));
2440 } else {
2441 // Emit stub for static call
2442 address stub = CompiledDirectCall::emit_to_interp_stub(masm, call);
2443 if (stub == nullptr) {
2444 ciEnv::current()->record_failure("CodeCache is full");
2445 return;
2446 }
2447 }
2448 }
2449
2450 __ post_call_nop();
2451 %}
2452
2453 enc_class riscv_enc_java_dynamic_call(method meth) %{
2454 Assembler::IncompressibleScope scope(masm); // Fixed length: see ret_addr_offset
2455 int method_index = resolved_method_index(masm);
2456 address call = __ ic_call((address)$meth$$method, method_index);
2457 if (call == nullptr) {
2458 ciEnv::current()->record_failure("CodeCache is full");
2459 return;
2460 }
2461
2462 __ post_call_nop();
2463 %}
2464
2465 enc_class riscv_enc_call_epilog() %{
2466 if (VerifyStackAtCalls) {
2467 // Check that stack depth is unchanged: find majik cookie on stack
2468 __ call_Unimplemented();
2469 }
2470 %}
2471
2472 enc_class riscv_enc_java_to_runtime(method meth) %{
2473 Assembler::IncompressibleScope scope(masm); // Fixed length: see ret_addr_offset
2474
2475 // Some calls to generated routines (arraycopy code) are scheduled by C2
2476 // as runtime calls. if so we can call them using a far call (they will be
2477 // in the code cache, thus in a reachable segment) otherwise we have to use
2478 // a movptr+jalr pair which loads the absolute address into a register.
2479 address entry = (address)$meth$$method;
2480 if (CodeCache::contains(entry)) {
2481 __ far_call(Address(entry, relocInfo::runtime_call_type));
2482 __ post_call_nop();
2483 } else {
2484 Label retaddr;
2485 // Make the anchor frame walkable
2486 __ la(t0, retaddr);
2487 __ sd(t0, Address(xthread, JavaThread::last_Java_pc_offset()));
2488 int32_t offset = 0;
2489 // No relocation needed
2490 __ movptr(t1, entry, offset, t0); // lui + lui + slli + add
2491 __ jalr(t1, offset);
2492 __ bind(retaddr);
2493 __ post_call_nop();
2494 }
2495 %}
2496
2497 enc_class riscv_enc_tail_call(iRegP jump_target) %{
2498 Register target_reg = as_Register($jump_target$$reg);
2499 __ jr(target_reg);
2500 %}
2501
2502 enc_class riscv_enc_tail_jmp(iRegP jump_target) %{
2503 Register target_reg = as_Register($jump_target$$reg);
2504 // exception oop should be in x10
2505 // ret addr has been popped into ra
2506 // callee expects it in x13
2507 __ mv(x13, ra);
2508 __ jr(target_reg);
2509 %}
2510
2511 enc_class riscv_enc_rethrow() %{
2512 __ far_jump(RuntimeAddress(OptoRuntime::rethrow_stub()));
2513 %}
2514
2515 enc_class riscv_enc_ret() %{
2516 __ ret();
2517 %}
2518
2519 %}
2520
2521 //----------FRAME--------------------------------------------------------------
2522 // Definition of frame structure and management information.
2523 //
2524 // S T A C K L A Y O U T Allocators stack-slot number
2525 // | (to get allocators register number
2526 // G Owned by | | v add OptoReg::stack0())
2527 // r CALLER | |
2528 // o | +--------+ pad to even-align allocators stack-slot
2529 // w V | pad0 | numbers; owned by CALLER
2530 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
2531 // h ^ | in | 5
2532 // | | args | 4 Holes in incoming args owned by SELF
2533 // | | | | 3
2534 // | | +--------+
2535 // V | | old out| Empty on Intel, window on Sparc
2536 // | old |preserve| Must be even aligned.
2537 // | SP-+--------+----> Matcher::_old_SP, even aligned
2538 // | | in | 3 area for Intel ret address
2539 // Owned by |preserve| Empty on Sparc.
2540 // SELF +--------+
2541 // | | pad2 | 2 pad to align old SP
2542 // | +--------+ 1
2543 // | | locks | 0
2544 // | +--------+----> OptoReg::stack0(), even aligned
2545 // | | pad1 | 11 pad to align new SP
2546 // | +--------+
2547 // | | | 10
2548 // | | spills | 9 spills
2549 // V | | 8 (pad0 slot for callee)
2550 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
2551 // ^ | out | 7
2552 // | | args | 6 Holes in outgoing args owned by CALLEE
2553 // Owned by +--------+
2554 // CALLEE | new out| 6 Empty on Intel, window on Sparc
2555 // | new |preserve| Must be even-aligned.
2556 // | SP-+--------+----> Matcher::_new_SP, even aligned
2557 // | | |
2558 //
2559 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
2560 // known from SELF's arguments and the Java calling convention.
2561 // Region 6-7 is determined per call site.
2562 // Note 2: If the calling convention leaves holes in the incoming argument
2563 // area, those holes are owned by SELF. Holes in the outgoing area
2564 // are owned by the CALLEE. Holes should not be necessary in the
2565 // incoming area, as the Java calling convention is completely under
2566 // the control of the AD file. Doubles can be sorted and packed to
2567 // avoid holes. Holes in the outgoing arguments may be necessary for
2568 // varargs C calling conventions.
2569 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
2570 // even aligned with pad0 as needed.
2571 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
2572 // (the latter is true on Intel but is it false on RISCV?)
2573 // region 6-11 is even aligned; it may be padded out more so that
2574 // the region from SP to FP meets the minimum stack alignment.
2575 // Note 4: For I2C adapters, the incoming FP may not meet the minimum stack
2576 // alignment. Region 11, pad1, may be dynamically extended so that
2577 // SP meets the minimum alignment.
2578
2579 frame %{
2580 // These three registers define part of the calling convention
2581 // between compiled code and the interpreter.
2582
2583 // Inline Cache Register or methodOop for I2C.
2584 inline_cache_reg(R31);
2585
2586 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
2587 cisc_spilling_operand_name(indOffset);
2588
2589 // Number of stack slots consumed by locking an object
2590 // generate Compile::sync_stack_slots
2591 // VMRegImpl::slots_per_word = wordSize / stack_slot_size = 8 / 4 = 2
2592 sync_stack_slots(1 * VMRegImpl::slots_per_word);
2593
2594 // Compiled code's Frame Pointer
2595 frame_pointer(R2);
2596
2597 // Interpreter stores its frame pointer in a register which is
2598 // stored to the stack by I2CAdaptors.
2599 // I2CAdaptors convert from interpreted java to compiled java.
2600 interpreter_frame_pointer(R8);
2601
2602 // Stack alignment requirement
2603 stack_alignment(StackAlignmentInBytes); // Alignment size in bytes (128-bit -> 16 bytes)
2604
2605 // Number of outgoing stack slots killed above the out_preserve_stack_slots
2606 // for calls to C. Supports the var-args backing area for register parms.
2607 varargs_C_out_slots_killed(frame::arg_reg_save_area_bytes / BytesPerInt);
2608
2609 // The after-PROLOG location of the return address. Location of
2610 // return address specifies a type (REG or STACK) and a number
2611 // representing the register number (i.e. - use a register name) or
2612 // stack slot.
2613 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
2614 // Otherwise, it is above the locks and verification slot and alignment word
2615 // TODO this may well be correct but need to check why that - 2 is there
2616 // ppc port uses 0 but we definitely need to allow for fixed_slots
2617 // which folds in the space used for monitors
2618 return_addr(STACK - 2 +
2619 align_up((Compile::current()->in_preserve_stack_slots() +
2620 Compile::current()->fixed_slots()),
2621 stack_alignment_in_slots()));
2622
2623 // Location of compiled Java return values. Same as C for now.
2624 return_value
2625 %{
2626 assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL,
2627 "only return normal values");
2628
2629 static const int lo[Op_RegL + 1] = { // enum name
2630 0, // Op_Node
2631 0, // Op_Set
2632 R10_num, // Op_RegN
2633 R10_num, // Op_RegI
2634 R10_num, // Op_RegP
2635 F10_num, // Op_RegF
2636 F10_num, // Op_RegD
2637 R10_num // Op_RegL
2638 };
2639
2640 static const int hi[Op_RegL + 1] = { // enum name
2641 0, // Op_Node
2642 0, // Op_Set
2643 OptoReg::Bad, // Op_RegN
2644 OptoReg::Bad, // Op_RegI
2645 R10_H_num, // Op_RegP
2646 OptoReg::Bad, // Op_RegF
2647 F10_H_num, // Op_RegD
2648 R10_H_num // Op_RegL
2649 };
2650
2651 return OptoRegPair(hi[ideal_reg], lo[ideal_reg]);
2652 %}
2653 %}
2654
2655 //----------ATTRIBUTES---------------------------------------------------------
2656 //----------Operand Attributes-------------------------------------------------
2657 op_attrib op_cost(1); // Required cost attribute
2658
2659 //----------Instruction Attributes---------------------------------------------
2660 ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute
2661 ins_attrib ins_size(32); // Required size attribute (in bits)
2662 ins_attrib ins_short_branch(0); // Required flag: is this instruction
2663 // a non-matching short branch variant
2664 // of some long branch?
2665 ins_attrib ins_alignment(4); // Required alignment attribute (must
2666 // be a power of 2) specifies the
2667 // alignment that some part of the
2668 // instruction (not necessarily the
2669 // start) requires. If > 1, a
2670 // compute_padding() function must be
2671 // provided for the instruction
2672
2673 //----------OPERANDS-----------------------------------------------------------
2674 // Operand definitions must precede instruction definitions for correct parsing
2675 // in the ADLC because operands constitute user defined types which are used in
2676 // instruction definitions.
2677
2678 //----------Simple Operands----------------------------------------------------
2679
2680 // Integer operands 32 bit
2681 // 32 bit immediate
2682 operand immI()
2683 %{
2684 match(ConI);
2685
2686 op_cost(0);
2687 format %{ %}
2688 interface(CONST_INTER);
2689 %}
2690
2691 // 32 bit zero
2692 operand immI0()
2693 %{
2694 predicate(n->get_int() == 0);
2695 match(ConI);
2696
2697 op_cost(0);
2698 format %{ %}
2699 interface(CONST_INTER);
2700 %}
2701
2702 // 32 bit unit increment
2703 operand immI_1()
2704 %{
2705 predicate(n->get_int() == 1);
2706 match(ConI);
2707
2708 op_cost(0);
2709 format %{ %}
2710 interface(CONST_INTER);
2711 %}
2712
2713 // 32 bit unit decrement
2714 operand immI_M1()
2715 %{
2716 predicate(n->get_int() == -1);
2717 match(ConI);
2718
2719 op_cost(0);
2720 format %{ %}
2721 interface(CONST_INTER);
2722 %}
2723
2724 // Unsigned Integer Immediate: 6-bit int, greater than 32
2725 operand uimmI6_ge32() %{
2726 predicate(((unsigned int)(n->get_int()) < 64) && (n->get_int() >= 32));
2727 match(ConI);
2728 op_cost(0);
2729 format %{ %}
2730 interface(CONST_INTER);
2731 %}
2732
2733 operand immI_le_4()
2734 %{
2735 predicate(n->get_int() <= 4);
2736 match(ConI);
2737
2738 op_cost(0);
2739 format %{ %}
2740 interface(CONST_INTER);
2741 %}
2742
2743 operand immI_16()
2744 %{
2745 predicate(n->get_int() == 16);
2746 match(ConI);
2747 op_cost(0);
2748 format %{ %}
2749 interface(CONST_INTER);
2750 %}
2751
2752 operand immI_24()
2753 %{
2754 predicate(n->get_int() == 24);
2755 match(ConI);
2756 op_cost(0);
2757 format %{ %}
2758 interface(CONST_INTER);
2759 %}
2760
2761 operand immI_31()
2762 %{
2763 predicate(n->get_int() == 31);
2764 match(ConI);
2765
2766 op_cost(0);
2767 format %{ %}
2768 interface(CONST_INTER);
2769 %}
2770
2771 operand immI_63()
2772 %{
2773 predicate(n->get_int() == 63);
2774 match(ConI);
2775
2776 op_cost(0);
2777 format %{ %}
2778 interface(CONST_INTER);
2779 %}
2780
2781 // 32 bit integer valid for add immediate
2782 operand immIAdd()
2783 %{
2784 predicate(Assembler::is_simm12((int64_t)n->get_int()));
2785 match(ConI);
2786 op_cost(0);
2787 format %{ %}
2788 interface(CONST_INTER);
2789 %}
2790
2791 // 32 bit integer valid for sub immediate
2792 operand immISub()
2793 %{
2794 predicate(Assembler::is_simm12(-(int64_t)n->get_int()));
2795 match(ConI);
2796 op_cost(0);
2797 format %{ %}
2798 interface(CONST_INTER);
2799 %}
2800
2801 // 5 bit signed value.
2802 operand immI5()
2803 %{
2804 predicate(n->get_int() <= 15 && n->get_int() >= -16);
2805 match(ConI);
2806
2807 op_cost(0);
2808 format %{ %}
2809 interface(CONST_INTER);
2810 %}
2811
2812 // 5 bit signed value (simm5)
2813 operand immL5()
2814 %{
2815 predicate(n->get_long() <= 15 && n->get_long() >= -16);
2816 match(ConL);
2817
2818 op_cost(0);
2819 format %{ %}
2820 interface(CONST_INTER);
2821 %}
2822
2823 // Integer operands 64 bit
2824 // 64 bit immediate
2825 operand immL()
2826 %{
2827 match(ConL);
2828
2829 op_cost(0);
2830 format %{ %}
2831 interface(CONST_INTER);
2832 %}
2833
2834 // 64 bit zero
2835 operand immL0()
2836 %{
2837 predicate(n->get_long() == 0);
2838 match(ConL);
2839
2840 op_cost(0);
2841 format %{ %}
2842 interface(CONST_INTER);
2843 %}
2844
2845 // Pointer operands
2846 // Pointer Immediate
2847 operand immP()
2848 %{
2849 match(ConP);
2850
2851 op_cost(0);
2852 format %{ %}
2853 interface(CONST_INTER);
2854 %}
2855
2856 // Null Pointer Immediate
2857 operand immP0()
2858 %{
2859 predicate(n->get_ptr() == 0);
2860 match(ConP);
2861
2862 op_cost(0);
2863 format %{ %}
2864 interface(CONST_INTER);
2865 %}
2866
2867 // Pointer Immediate One
2868 // this is used in object initialization (initial object header)
2869 operand immP_1()
2870 %{
2871 predicate(n->get_ptr() == 1);
2872 match(ConP);
2873
2874 op_cost(0);
2875 format %{ %}
2876 interface(CONST_INTER);
2877 %}
2878
2879 // Card Table Byte Map Base
2880 operand immByteMapBase()
2881 %{
2882 // Get base of card map
2883 predicate(BarrierSet::barrier_set()->is_a(BarrierSet::CardTableBarrierSet) &&
2884 SHENANDOAHGC_ONLY(!BarrierSet::barrier_set()->is_a(BarrierSet::ShenandoahBarrierSet) &&)
2885 (CardTable::CardValue*)n->get_ptr() ==
2886 ((CardTableBarrierSet*)(BarrierSet::barrier_set()))->card_table()->byte_map_base());
2887 match(ConP);
2888
2889 op_cost(0);
2890 format %{ %}
2891 interface(CONST_INTER);
2892 %}
2893
2894 // Int Immediate: low 16-bit mask
2895 operand immI_16bits()
2896 %{
2897 predicate(n->get_int() == 0xFFFF);
2898 match(ConI);
2899 op_cost(0);
2900 format %{ %}
2901 interface(CONST_INTER);
2902 %}
2903
2904 operand immIpowerOf2() %{
2905 predicate(is_power_of_2((juint)(n->get_int())));
2906 match(ConI);
2907 op_cost(0);
2908 format %{ %}
2909 interface(CONST_INTER);
2910 %}
2911
2912 // Long Immediate: low 32-bit mask
2913 operand immL_32bits()
2914 %{
2915 predicate(n->get_long() == 0xFFFFFFFFL);
2916 match(ConL);
2917 op_cost(0);
2918 format %{ %}
2919 interface(CONST_INTER);
2920 %}
2921
2922 // 64 bit unit decrement
2923 operand immL_M1()
2924 %{
2925 predicate(n->get_long() == -1);
2926 match(ConL);
2927
2928 op_cost(0);
2929 format %{ %}
2930 interface(CONST_INTER);
2931 %}
2932
2933
2934 // 64 bit integer valid for add immediate
2935 operand immLAdd()
2936 %{
2937 predicate(Assembler::is_simm12(n->get_long()));
2938 match(ConL);
2939 op_cost(0);
2940 format %{ %}
2941 interface(CONST_INTER);
2942 %}
2943
2944 // 64 bit integer valid for sub immediate
2945 operand immLSub()
2946 %{
2947 predicate(Assembler::is_simm12(-(n->get_long())));
2948 match(ConL);
2949 op_cost(0);
2950 format %{ %}
2951 interface(CONST_INTER);
2952 %}
2953
2954 // Narrow pointer operands
2955 // Narrow Pointer Immediate
2956 operand immN()
2957 %{
2958 match(ConN);
2959
2960 op_cost(0);
2961 format %{ %}
2962 interface(CONST_INTER);
2963 %}
2964
2965 // Narrow Null Pointer Immediate
2966 operand immN0()
2967 %{
2968 predicate(n->get_narrowcon() == 0);
2969 match(ConN);
2970
2971 op_cost(0);
2972 format %{ %}
2973 interface(CONST_INTER);
2974 %}
2975
2976 operand immNKlass()
2977 %{
2978 match(ConNKlass);
2979
2980 op_cost(0);
2981 format %{ %}
2982 interface(CONST_INTER);
2983 %}
2984
2985 // Float and Double operands
2986 // Double Immediate
2987 operand immD()
2988 %{
2989 match(ConD);
2990 op_cost(0);
2991 format %{ %}
2992 interface(CONST_INTER);
2993 %}
2994
2995 // Double Immediate: +0.0d
2996 operand immD0()
2997 %{
2998 predicate(jlong_cast(n->getd()) == 0);
2999 match(ConD);
3000
3001 op_cost(0);
3002 format %{ %}
3003 interface(CONST_INTER);
3004 %}
3005
3006 // Float Immediate
3007 operand immF()
3008 %{
3009 match(ConF);
3010 op_cost(0);
3011 format %{ %}
3012 interface(CONST_INTER);
3013 %}
3014
3015 // Float Immediate: +0.0f.
3016 operand immF0()
3017 %{
3018 predicate(jint_cast(n->getf()) == 0);
3019 match(ConF);
3020
3021 op_cost(0);
3022 format %{ %}
3023 interface(CONST_INTER);
3024 %}
3025
3026 // Half Float Immediate
3027 operand immH()
3028 %{
3029 match(ConH);
3030
3031 op_cost(0);
3032 format %{ %}
3033 interface(CONST_INTER);
3034 %}
3035
3036 // Half Float Immediate: +0.0f.
3037 operand immH0()
3038 %{
3039 predicate(jint_cast(n->geth()) == 0);
3040 match(ConH);
3041
3042 op_cost(0);
3043 format %{ %}
3044 interface(CONST_INTER);
3045 %}
3046
3047 operand immIOffset()
3048 %{
3049 predicate(Assembler::is_simm12(n->get_int()));
3050 match(ConI);
3051 op_cost(0);
3052 format %{ %}
3053 interface(CONST_INTER);
3054 %}
3055
3056 operand immLOffset()
3057 %{
3058 predicate(Assembler::is_simm12(n->get_long()));
3059 match(ConL);
3060 op_cost(0);
3061 format %{ %}
3062 interface(CONST_INTER);
3063 %}
3064
3065 // Scale values
3066 operand immIScale()
3067 %{
3068 predicate(1 <= n->get_int() && (n->get_int() <= 3));
3069 match(ConI);
3070
3071 op_cost(0);
3072 format %{ %}
3073 interface(CONST_INTER);
3074 %}
3075
3076 // Integer 32 bit Register Operands
3077 operand iRegI()
3078 %{
3079 constraint(ALLOC_IN_RC(any_reg32));
3080 match(RegI);
3081 match(iRegINoSp);
3082 op_cost(0);
3083 format %{ %}
3084 interface(REG_INTER);
3085 %}
3086
3087 // Integer 32 bit Register not Special
3088 operand iRegINoSp()
3089 %{
3090 constraint(ALLOC_IN_RC(no_special_reg32));
3091 match(RegI);
3092 op_cost(0);
3093 format %{ %}
3094 interface(REG_INTER);
3095 %}
3096
3097 // Register R10 only
3098 operand iRegI_R10()
3099 %{
3100 constraint(ALLOC_IN_RC(int_r10_reg));
3101 match(RegI);
3102 match(iRegINoSp);
3103 op_cost(0);
3104 format %{ %}
3105 interface(REG_INTER);
3106 %}
3107
3108 // Register R12 only
3109 operand iRegI_R12()
3110 %{
3111 constraint(ALLOC_IN_RC(int_r12_reg));
3112 match(RegI);
3113 match(iRegINoSp);
3114 op_cost(0);
3115 format %{ %}
3116 interface(REG_INTER);
3117 %}
3118
3119 // Register R13 only
3120 operand iRegI_R13()
3121 %{
3122 constraint(ALLOC_IN_RC(int_r13_reg));
3123 match(RegI);
3124 match(iRegINoSp);
3125 op_cost(0);
3126 format %{ %}
3127 interface(REG_INTER);
3128 %}
3129
3130 // Register R14 only
3131 operand iRegI_R14()
3132 %{
3133 constraint(ALLOC_IN_RC(int_r14_reg));
3134 match(RegI);
3135 match(iRegINoSp);
3136 op_cost(0);
3137 format %{ %}
3138 interface(REG_INTER);
3139 %}
3140
3141 // Integer 64 bit Register Operands
3142 operand iRegL()
3143 %{
3144 constraint(ALLOC_IN_RC(any_reg));
3145 match(RegL);
3146 match(iRegLNoSp);
3147 op_cost(0);
3148 format %{ %}
3149 interface(REG_INTER);
3150 %}
3151
3152 // Integer 64 bit Register not Special
3153 operand iRegLNoSp()
3154 %{
3155 constraint(ALLOC_IN_RC(no_special_reg));
3156 match(RegL);
3157 match(iRegL_R10);
3158 format %{ %}
3159 interface(REG_INTER);
3160 %}
3161
3162 // Long 64 bit Register R29 only
3163 operand iRegL_R29()
3164 %{
3165 constraint(ALLOC_IN_RC(r29_reg));
3166 match(RegL);
3167 match(iRegLNoSp);
3168 op_cost(0);
3169 format %{ %}
3170 interface(REG_INTER);
3171 %}
3172
3173 // Long 64 bit Register R30 only
3174 operand iRegL_R30()
3175 %{
3176 constraint(ALLOC_IN_RC(r30_reg));
3177 match(RegL);
3178 match(iRegLNoSp);
3179 op_cost(0);
3180 format %{ %}
3181 interface(REG_INTER);
3182 %}
3183
3184 // Pointer Register Operands
3185 // Pointer Register
3186 operand iRegP()
3187 %{
3188 constraint(ALLOC_IN_RC(ptr_reg));
3189 match(RegP);
3190 match(iRegPNoSp);
3191 match(iRegP_R10);
3192 match(iRegP_R15);
3193 match(javaThread_RegP);
3194 op_cost(0);
3195 format %{ %}
3196 interface(REG_INTER);
3197 %}
3198
3199 // Pointer 64 bit Register not Special
3200 operand iRegPNoSp()
3201 %{
3202 constraint(ALLOC_IN_RC(no_special_ptr_reg));
3203 match(RegP);
3204 op_cost(0);
3205 format %{ %}
3206 interface(REG_INTER);
3207 %}
3208
3209 // This operand is not allowed to use fp even if
3210 // fp is not used to hold the frame pointer.
3211 operand iRegPNoSpNoFp()
3212 %{
3213 constraint(ALLOC_IN_RC(no_special_no_fp_ptr_reg));
3214 match(RegP);
3215 match(iRegPNoSp);
3216 op_cost(0);
3217 format %{ %}
3218 interface(REG_INTER);
3219 %}
3220
3221 operand iRegP_R10()
3222 %{
3223 constraint(ALLOC_IN_RC(r10_reg));
3224 match(RegP);
3225 // match(iRegP);
3226 match(iRegPNoSp);
3227 op_cost(0);
3228 format %{ %}
3229 interface(REG_INTER);
3230 %}
3231
3232 // Pointer 64 bit Register R11 only
3233 operand iRegP_R11()
3234 %{
3235 constraint(ALLOC_IN_RC(r11_reg));
3236 match(RegP);
3237 match(iRegPNoSp);
3238 op_cost(0);
3239 format %{ %}
3240 interface(REG_INTER);
3241 %}
3242
3243 operand iRegP_R12()
3244 %{
3245 constraint(ALLOC_IN_RC(r12_reg));
3246 match(RegP);
3247 // match(iRegP);
3248 match(iRegPNoSp);
3249 op_cost(0);
3250 format %{ %}
3251 interface(REG_INTER);
3252 %}
3253
3254 // Pointer 64 bit Register R13 only
3255 operand iRegP_R13()
3256 %{
3257 constraint(ALLOC_IN_RC(r13_reg));
3258 match(RegP);
3259 match(iRegPNoSp);
3260 op_cost(0);
3261 format %{ %}
3262 interface(REG_INTER);
3263 %}
3264
3265 operand iRegP_R14()
3266 %{
3267 constraint(ALLOC_IN_RC(r14_reg));
3268 match(RegP);
3269 // match(iRegP);
3270 match(iRegPNoSp);
3271 op_cost(0);
3272 format %{ %}
3273 interface(REG_INTER);
3274 %}
3275
3276 operand iRegP_R15()
3277 %{
3278 constraint(ALLOC_IN_RC(r15_reg));
3279 match(RegP);
3280 // match(iRegP);
3281 match(iRegPNoSp);
3282 op_cost(0);
3283 format %{ %}
3284 interface(REG_INTER);
3285 %}
3286
3287 operand iRegP_R16()
3288 %{
3289 constraint(ALLOC_IN_RC(r16_reg));
3290 match(RegP);
3291 match(iRegPNoSp);
3292 op_cost(0);
3293 format %{ %}
3294 interface(REG_INTER);
3295 %}
3296
3297 // Pointer 64 bit Register R28 only
3298 operand iRegP_R28()
3299 %{
3300 constraint(ALLOC_IN_RC(r28_reg));
3301 match(RegP);
3302 match(iRegPNoSp);
3303 op_cost(0);
3304 format %{ %}
3305 interface(REG_INTER);
3306 %}
3307
3308 // Pointer 64 bit Register R30 only
3309 operand iRegP_R30()
3310 %{
3311 constraint(ALLOC_IN_RC(r30_reg));
3312 match(RegP);
3313 match(iRegPNoSp);
3314 op_cost(0);
3315 format %{ %}
3316 interface(REG_INTER);
3317 %}
3318
3319 // Pointer 64 bit Register R31 only
3320 operand iRegP_R31()
3321 %{
3322 constraint(ALLOC_IN_RC(r31_reg));
3323 match(RegP);
3324 match(iRegPNoSp);
3325 op_cost(0);
3326 format %{ %}
3327 interface(REG_INTER);
3328 %}
3329
3330 // Pointer Register Operands
3331 // Narrow Pointer Register
3332 operand iRegN()
3333 %{
3334 constraint(ALLOC_IN_RC(any_reg32));
3335 match(RegN);
3336 match(iRegNNoSp);
3337 op_cost(0);
3338 format %{ %}
3339 interface(REG_INTER);
3340 %}
3341
3342 // Integer 64 bit Register not Special
3343 operand iRegNNoSp()
3344 %{
3345 constraint(ALLOC_IN_RC(no_special_reg32));
3346 match(RegN);
3347 op_cost(0);
3348 format %{ %}
3349 interface(REG_INTER);
3350 %}
3351
3352 // Long 64 bit Register R10 only
3353 operand iRegL_R10()
3354 %{
3355 constraint(ALLOC_IN_RC(r10_reg));
3356 match(RegL);
3357 match(iRegLNoSp);
3358 op_cost(0);
3359 format %{ %}
3360 interface(REG_INTER);
3361 %}
3362
3363 // Float Register
3364 // Float register operands
3365 operand fRegF()
3366 %{
3367 constraint(ALLOC_IN_RC(float_reg));
3368 match(RegF);
3369
3370 op_cost(0);
3371 format %{ %}
3372 interface(REG_INTER);
3373 %}
3374
3375 // Double Register
3376 // Double register operands
3377 operand fRegD()
3378 %{
3379 constraint(ALLOC_IN_RC(double_reg));
3380 match(RegD);
3381
3382 op_cost(0);
3383 format %{ %}
3384 interface(REG_INTER);
3385 %}
3386
3387 // Generic vector class. This will be used for
3388 // all vector operands.
3389 operand vReg()
3390 %{
3391 constraint(ALLOC_IN_RC(vectora_reg));
3392 match(VecA);
3393 op_cost(0);
3394 format %{ %}
3395 interface(REG_INTER);
3396 %}
3397
3398 operand vReg_V1()
3399 %{
3400 constraint(ALLOC_IN_RC(v1_reg));
3401 match(VecA);
3402 match(vReg);
3403 op_cost(0);
3404 format %{ %}
3405 interface(REG_INTER);
3406 %}
3407
3408 operand vReg_V2()
3409 %{
3410 constraint(ALLOC_IN_RC(v2_reg));
3411 match(VecA);
3412 match(vReg);
3413 op_cost(0);
3414 format %{ %}
3415 interface(REG_INTER);
3416 %}
3417
3418 operand vReg_V3()
3419 %{
3420 constraint(ALLOC_IN_RC(v3_reg));
3421 match(VecA);
3422 match(vReg);
3423 op_cost(0);
3424 format %{ %}
3425 interface(REG_INTER);
3426 %}
3427
3428 operand vReg_V4()
3429 %{
3430 constraint(ALLOC_IN_RC(v4_reg));
3431 match(VecA);
3432 match(vReg);
3433 op_cost(0);
3434 format %{ %}
3435 interface(REG_INTER);
3436 %}
3437
3438 operand vReg_V5()
3439 %{
3440 constraint(ALLOC_IN_RC(v5_reg));
3441 match(VecA);
3442 match(vReg);
3443 op_cost(0);
3444 format %{ %}
3445 interface(REG_INTER);
3446 %}
3447
3448 operand vReg_V6()
3449 %{
3450 constraint(ALLOC_IN_RC(v6_reg));
3451 match(VecA);
3452 match(vReg);
3453 op_cost(0);
3454 format %{ %}
3455 interface(REG_INTER);
3456 %}
3457
3458 operand vReg_V7()
3459 %{
3460 constraint(ALLOC_IN_RC(v7_reg));
3461 match(VecA);
3462 match(vReg);
3463 op_cost(0);
3464 format %{ %}
3465 interface(REG_INTER);
3466 %}
3467
3468 operand vReg_V8()
3469 %{
3470 constraint(ALLOC_IN_RC(v8_reg));
3471 match(VecA);
3472 match(vReg);
3473 op_cost(0);
3474 format %{ %}
3475 interface(REG_INTER);
3476 %}
3477
3478 operand vReg_V9()
3479 %{
3480 constraint(ALLOC_IN_RC(v9_reg));
3481 match(VecA);
3482 match(vReg);
3483 op_cost(0);
3484 format %{ %}
3485 interface(REG_INTER);
3486 %}
3487
3488 operand vReg_V10()
3489 %{
3490 constraint(ALLOC_IN_RC(v10_reg));
3491 match(VecA);
3492 match(vReg);
3493 op_cost(0);
3494 format %{ %}
3495 interface(REG_INTER);
3496 %}
3497
3498 operand vReg_V11()
3499 %{
3500 constraint(ALLOC_IN_RC(v11_reg));
3501 match(VecA);
3502 match(vReg);
3503 op_cost(0);
3504 format %{ %}
3505 interface(REG_INTER);
3506 %}
3507
3508 operand vRegMask()
3509 %{
3510 constraint(ALLOC_IN_RC(vmask_reg));
3511 match(RegVectMask);
3512 match(vRegMask_V0);
3513 op_cost(0);
3514 format %{ %}
3515 interface(REG_INTER);
3516 %}
3517
3518 // The mask value used to control execution of a masked
3519 // vector instruction is always supplied by vector register v0.
3520 operand vRegMask_V0()
3521 %{
3522 constraint(ALLOC_IN_RC(vmask_reg_v0));
3523 match(RegVectMask);
3524 match(vRegMask);
3525 op_cost(0);
3526 format %{ %}
3527 interface(REG_INTER);
3528 %}
3529
3530 // Java Thread Register
3531 operand javaThread_RegP(iRegP reg)
3532 %{
3533 constraint(ALLOC_IN_RC(java_thread_reg)); // java_thread_reg
3534 match(reg);
3535 op_cost(0);
3536 format %{ %}
3537 interface(REG_INTER);
3538 %}
3539
3540 //----------Memory Operands----------------------------------------------------
3541 // RISCV has only base_plus_offset and literal address mode, so no need to use
3542 // index and scale. Here set index as 0xffffffff and scale as 0x0.
3543 operand indirect(iRegP reg)
3544 %{
3545 constraint(ALLOC_IN_RC(ptr_reg));
3546 match(reg);
3547 op_cost(0);
3548 format %{ "[$reg]" %}
3549 interface(MEMORY_INTER) %{
3550 base($reg);
3551 index(0xffffffff);
3552 scale(0x0);
3553 disp(0x0);
3554 %}
3555 %}
3556
3557 operand indOffI(iRegP reg, immIOffset off)
3558 %{
3559 constraint(ALLOC_IN_RC(ptr_reg));
3560 match(AddP reg off);
3561 op_cost(0);
3562 format %{ "[$reg, $off]" %}
3563 interface(MEMORY_INTER) %{
3564 base($reg);
3565 index(0xffffffff);
3566 scale(0x0);
3567 disp($off);
3568 %}
3569 %}
3570
3571 operand indOffL(iRegP reg, immLOffset off)
3572 %{
3573 constraint(ALLOC_IN_RC(ptr_reg));
3574 match(AddP reg off);
3575 op_cost(0);
3576 format %{ "[$reg, $off]" %}
3577 interface(MEMORY_INTER) %{
3578 base($reg);
3579 index(0xffffffff);
3580 scale(0x0);
3581 disp($off);
3582 %}
3583 %}
3584
3585 operand indirectN(iRegN reg)
3586 %{
3587 predicate(CompressedOops::shift() == 0);
3588 constraint(ALLOC_IN_RC(ptr_reg));
3589 match(DecodeN reg);
3590 op_cost(0);
3591 format %{ "[$reg]\t# narrow" %}
3592 interface(MEMORY_INTER) %{
3593 base($reg);
3594 index(0xffffffff);
3595 scale(0x0);
3596 disp(0x0);
3597 %}
3598 %}
3599
3600 operand indOffIN(iRegN reg, immIOffset off)
3601 %{
3602 predicate(CompressedOops::shift() == 0);
3603 constraint(ALLOC_IN_RC(ptr_reg));
3604 match(AddP (DecodeN reg) off);
3605 op_cost(0);
3606 format %{ "[$reg, $off]\t# narrow" %}
3607 interface(MEMORY_INTER) %{
3608 base($reg);
3609 index(0xffffffff);
3610 scale(0x0);
3611 disp($off);
3612 %}
3613 %}
3614
3615 operand indOffLN(iRegN reg, immLOffset off)
3616 %{
3617 predicate(CompressedOops::shift() == 0);
3618 constraint(ALLOC_IN_RC(ptr_reg));
3619 match(AddP (DecodeN reg) off);
3620 op_cost(0);
3621 format %{ "[$reg, $off]\t# narrow" %}
3622 interface(MEMORY_INTER) %{
3623 base($reg);
3624 index(0xffffffff);
3625 scale(0x0);
3626 disp($off);
3627 %}
3628 %}
3629
3630 //----------Special Memory Operands--------------------------------------------
3631 // Stack Slot Operand - This operand is used for loading and storing temporary
3632 // values on the stack where a match requires a value to
3633 // flow through memory.
3634 operand stackSlotI(sRegI reg)
3635 %{
3636 constraint(ALLOC_IN_RC(stack_slots));
3637 // No match rule because this operand is only generated in matching
3638 // match(RegI);
3639 format %{ "[$reg]" %}
3640 interface(MEMORY_INTER) %{
3641 base(0x02); // RSP
3642 index(0xffffffff); // No Index
3643 scale(0x0); // No Scale
3644 disp($reg); // Stack Offset
3645 %}
3646 %}
3647
3648 operand stackSlotF(sRegF reg)
3649 %{
3650 constraint(ALLOC_IN_RC(stack_slots));
3651 // No match rule because this operand is only generated in matching
3652 // match(RegF);
3653 format %{ "[$reg]" %}
3654 interface(MEMORY_INTER) %{
3655 base(0x02); // RSP
3656 index(0xffffffff); // No Index
3657 scale(0x0); // No Scale
3658 disp($reg); // Stack Offset
3659 %}
3660 %}
3661
3662 operand stackSlotD(sRegD reg)
3663 %{
3664 constraint(ALLOC_IN_RC(stack_slots));
3665 // No match rule because this operand is only generated in matching
3666 // match(RegD);
3667 format %{ "[$reg]" %}
3668 interface(MEMORY_INTER) %{
3669 base(0x02); // RSP
3670 index(0xffffffff); // No Index
3671 scale(0x0); // No Scale
3672 disp($reg); // Stack Offset
3673 %}
3674 %}
3675
3676 operand stackSlotL(sRegL reg)
3677 %{
3678 constraint(ALLOC_IN_RC(stack_slots));
3679 // No match rule because this operand is only generated in matching
3680 // match(RegL);
3681 format %{ "[$reg]" %}
3682 interface(MEMORY_INTER) %{
3683 base(0x02); // RSP
3684 index(0xffffffff); // No Index
3685 scale(0x0); // No Scale
3686 disp($reg); // Stack Offset
3687 %}
3688 %}
3689
3690 // Special operand allowing long args to int ops to be truncated for free
3691
3692 operand iRegL2I(iRegL reg) %{
3693
3694 op_cost(0);
3695
3696 match(ConvL2I reg);
3697
3698 format %{ "l2i($reg)" %}
3699
3700 interface(REG_INTER)
3701 %}
3702
3703
3704 // Comparison Operands
3705 // NOTE: Label is a predefined operand which should not be redefined in
3706 // the AD file. It is generically handled within the ADLC.
3707
3708 //----------Conditional Branch Operands----------------------------------------
3709 // Comparison Op - This is the operation of the comparison, and is limited to
3710 // the following set of codes:
3711 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
3712 //
3713 // Other attributes of the comparison, such as unsignedness, are specified
3714 // by the comparison instruction that sets a condition code flags register.
3715 // That result is represented by a flags operand whose subtype is appropriate
3716 // to the unsignedness (etc.) of the comparison.
3717 //
3718 // Later, the instruction which matches both the Comparison Op (a Bool) and
3719 // the flags (produced by the Cmp) specifies the coding of the comparison op
3720 // by matching a specific subtype of Bool operand below, such as cmpOpU.
3721
3722
3723 // used for signed integral comparisons and fp comparisons
3724 operand cmpOp()
3725 %{
3726 match(Bool);
3727
3728 format %{ "" %}
3729
3730 // the values in interface derives from struct BoolTest::mask
3731 interface(COND_INTER) %{
3732 equal(0x0, "eq");
3733 greater(0x1, "gt");
3734 overflow(0x2, "overflow");
3735 less(0x3, "lt");
3736 not_equal(0x4, "ne");
3737 less_equal(0x5, "le");
3738 no_overflow(0x6, "no_overflow");
3739 greater_equal(0x7, "ge");
3740 %}
3741 %}
3742
3743 // used for unsigned integral comparisons
3744 operand cmpOpU()
3745 %{
3746 match(Bool);
3747
3748 format %{ "" %}
3749 // the values in interface derives from struct BoolTest::mask
3750 interface(COND_INTER) %{
3751 equal(0x0, "eq");
3752 greater(0x1, "gtu");
3753 overflow(0x2, "overflow");
3754 less(0x3, "ltu");
3755 not_equal(0x4, "ne");
3756 less_equal(0x5, "leu");
3757 no_overflow(0x6, "no_overflow");
3758 greater_equal(0x7, "geu");
3759 %}
3760 %}
3761
3762 // used for certain integral comparisons which can be
3763 // converted to bxx instructions
3764 operand cmpOpEqNe()
3765 %{
3766 match(Bool);
3767 op_cost(0);
3768 predicate(n->as_Bool()->_test._test == BoolTest::ne ||
3769 n->as_Bool()->_test._test == BoolTest::eq);
3770
3771 format %{ "" %}
3772 interface(COND_INTER) %{
3773 equal(0x0, "eq");
3774 greater(0x1, "gt");
3775 overflow(0x2, "overflow");
3776 less(0x3, "lt");
3777 not_equal(0x4, "ne");
3778 less_equal(0x5, "le");
3779 no_overflow(0x6, "no_overflow");
3780 greater_equal(0x7, "ge");
3781 %}
3782 %}
3783
3784 operand cmpOpULtGe()
3785 %{
3786 match(Bool);
3787 op_cost(0);
3788 predicate(n->as_Bool()->_test._test == BoolTest::lt ||
3789 n->as_Bool()->_test._test == BoolTest::ge);
3790
3791 format %{ "" %}
3792 interface(COND_INTER) %{
3793 equal(0x0, "eq");
3794 greater(0x1, "gtu");
3795 overflow(0x2, "overflow");
3796 less(0x3, "ltu");
3797 not_equal(0x4, "ne");
3798 less_equal(0x5, "leu");
3799 no_overflow(0x6, "no_overflow");
3800 greater_equal(0x7, "geu");
3801 %}
3802 %}
3803
3804 operand cmpOpUEqNeLeGt()
3805 %{
3806 match(Bool);
3807 op_cost(0);
3808 predicate(n->as_Bool()->_test._test == BoolTest::ne ||
3809 n->as_Bool()->_test._test == BoolTest::eq ||
3810 n->as_Bool()->_test._test == BoolTest::le ||
3811 n->as_Bool()->_test._test == BoolTest::gt);
3812
3813 format %{ "" %}
3814 interface(COND_INTER) %{
3815 equal(0x0, "eq");
3816 greater(0x1, "gtu");
3817 overflow(0x2, "overflow");
3818 less(0x3, "ltu");
3819 not_equal(0x4, "ne");
3820 less_equal(0x5, "leu");
3821 no_overflow(0x6, "no_overflow");
3822 greater_equal(0x7, "geu");
3823 %}
3824 %}
3825
3826
3827 // Flags register, used as output of compare logic
3828 operand rFlagsReg()
3829 %{
3830 constraint(ALLOC_IN_RC(reg_flags));
3831 match(RegFlags);
3832
3833 op_cost(0);
3834 format %{ "RFLAGS" %}
3835 interface(REG_INTER);
3836 %}
3837
3838 // Special Registers
3839
3840 // Method Register
3841 operand inline_cache_RegP(iRegP reg)
3842 %{
3843 constraint(ALLOC_IN_RC(method_reg)); // inline_cache_reg
3844 match(reg);
3845 match(iRegPNoSp);
3846 op_cost(0);
3847 format %{ %}
3848 interface(REG_INTER);
3849 %}
3850
3851 //----------OPERAND CLASSES----------------------------------------------------
3852 // Operand Classes are groups of operands that are used as to simplify
3853 // instruction definitions by not requiring the AD writer to specify
3854 // separate instructions for every form of operand when the
3855 // instruction accepts multiple operand types with the same basic
3856 // encoding and format. The classic case of this is memory operands.
3857
3858 // memory is used to define read/write location for load/store
3859 // instruction defs. we can turn a memory op into an Address
3860
3861 opclass memory(indirect, indOffI, indOffL, indirectN, indOffIN, indOffLN);
3862
3863 // iRegIorL2I is used for src inputs in rules for 32 bit int (I)
3864 // operations. it allows the src to be either an iRegI or a (ConvL2I
3865 // iRegL). in the latter case the l2i normally planted for a ConvL2I
3866 // can be elided because the 32-bit instruction will just employ the
3867 // lower 32 bits anyway.
3868 //
3869 // n.b. this does not elide all L2I conversions. if the truncated
3870 // value is consumed by more than one operation then the ConvL2I
3871 // cannot be bundled into the consuming nodes so an l2i gets planted
3872 // (actually an addiw $dst, $src, 0) and the downstream instructions
3873 // consume the result of the L2I as an iRegI input. That's a shame since
3874 // the addiw is actually redundant but its not too costly.
3875
3876 opclass iRegIorL2I(iRegI, iRegL2I);
3877 opclass iRegIorL(iRegI, iRegL);
3878 opclass iRegNorP(iRegN, iRegP);
3879 opclass iRegILNP(iRegI, iRegL, iRegN, iRegP);
3880 opclass iRegILNPNoSp(iRegINoSp, iRegLNoSp, iRegNNoSp, iRegPNoSp);
3881 opclass immIorL(immI, immL);
3882
3883 //----------PIPELINE-----------------------------------------------------------
3884 // Rules which define the behavior of the target architectures pipeline.
3885
3886 // For specific pipelines, e.g. generic RISC-V, define the stages of that pipeline
3887 //pipe_desc(ID, EX, MEM, WR);
3888 #define ID S0
3889 #define EX S1
3890 #define MEM S2
3891 #define WR S3
3892
3893 // Integer ALU reg operation
3894 pipeline %{
3895
3896 attributes %{
3897 // RISC-V instructions are of fixed length
3898 fixed_size_instructions; // Fixed size instructions TODO does
3899 max_instructions_per_bundle = 2; // Generic RISC-V 1, Sifive Series 7 2
3900 // RISC-V instructions come in 32-bit word units
3901 instruction_unit_size = 4; // An instruction is 4 bytes long
3902 instruction_fetch_unit_size = 64; // The processor fetches one line
3903 instruction_fetch_units = 1; // of 64 bytes
3904
3905 // List of nop instructions
3906 nops( MachNop );
3907 %}
3908
3909 // We don't use an actual pipeline model so don't care about resources
3910 // or description. we do use pipeline classes to introduce fixed
3911 // latencies
3912
3913 //----------RESOURCES----------------------------------------------------------
3914 // Resources are the functional units available to the machine
3915
3916 // Generic RISC-V pipeline
3917 // 1 decoder
3918 // 1 instruction decoded per cycle
3919 // 1 load/store ops per cycle, 1 branch, 1 FPU
3920 // 1 mul, 1 div
3921
3922 resources ( DECODE,
3923 ALU,
3924 MUL,
3925 DIV,
3926 BRANCH,
3927 LDST,
3928 FPU);
3929
3930 //----------PIPELINE DESCRIPTION-----------------------------------------------
3931 // Pipeline Description specifies the stages in the machine's pipeline
3932
3933 // Define the pipeline as a generic 6 stage pipeline
3934 pipe_desc(S0, S1, S2, S3, S4, S5);
3935
3936 //----------PIPELINE CLASSES---------------------------------------------------
3937 // Pipeline Classes describe the stages in which input and output are
3938 // referenced by the hardware pipeline.
3939
3940 pipe_class fp_dop_reg_reg_s(fRegF dst, fRegF src1, fRegF src2)
3941 %{
3942 single_instruction;
3943 src1 : S1(read);
3944 src2 : S2(read);
3945 dst : S5(write);
3946 DECODE : ID;
3947 FPU : S5;
3948 %}
3949
3950 pipe_class fp_dop_reg_reg_d(fRegD dst, fRegD src1, fRegD src2)
3951 %{
3952 src1 : S1(read);
3953 src2 : S2(read);
3954 dst : S5(write);
3955 DECODE : ID;
3956 FPU : S5;
3957 %}
3958
3959 pipe_class fp_uop_s(fRegF dst, fRegF src)
3960 %{
3961 single_instruction;
3962 src : S1(read);
3963 dst : S5(write);
3964 DECODE : ID;
3965 FPU : S5;
3966 %}
3967
3968 pipe_class fp_uop_d(fRegD dst, fRegD src)
3969 %{
3970 single_instruction;
3971 src : S1(read);
3972 dst : S5(write);
3973 DECODE : ID;
3974 FPU : S5;
3975 %}
3976
3977 pipe_class fp_d2f(fRegF dst, fRegD src)
3978 %{
3979 single_instruction;
3980 src : S1(read);
3981 dst : S5(write);
3982 DECODE : ID;
3983 FPU : S5;
3984 %}
3985
3986 pipe_class fp_f2d(fRegD dst, fRegF src)
3987 %{
3988 single_instruction;
3989 src : S1(read);
3990 dst : S5(write);
3991 DECODE : ID;
3992 FPU : S5;
3993 %}
3994
3995 pipe_class fp_f2i(iRegINoSp dst, fRegF src)
3996 %{
3997 single_instruction;
3998 src : S1(read);
3999 dst : S5(write);
4000 DECODE : ID;
4001 FPU : S5;
4002 %}
4003
4004 pipe_class fp_f2l(iRegLNoSp dst, fRegF src)
4005 %{
4006 single_instruction;
4007 src : S1(read);
4008 dst : S5(write);
4009 DECODE : ID;
4010 FPU : S5;
4011 %}
4012
4013 pipe_class fp_i2f(fRegF dst, iRegIorL2I src)
4014 %{
4015 single_instruction;
4016 src : S1(read);
4017 dst : S5(write);
4018 DECODE : ID;
4019 FPU : S5;
4020 %}
4021
4022 pipe_class fp_l2f(fRegF dst, iRegL src)
4023 %{
4024 single_instruction;
4025 src : S1(read);
4026 dst : S5(write);
4027 DECODE : ID;
4028 FPU : S5;
4029 %}
4030
4031 pipe_class fp_d2i(iRegINoSp dst, fRegD src)
4032 %{
4033 single_instruction;
4034 src : S1(read);
4035 dst : S5(write);
4036 DECODE : ID;
4037 FPU : S5;
4038 %}
4039
4040 pipe_class fp_d2l(iRegLNoSp dst, fRegD src)
4041 %{
4042 single_instruction;
4043 src : S1(read);
4044 dst : S5(write);
4045 DECODE : ID;
4046 FPU : S5;
4047 %}
4048
4049 pipe_class fp_i2d(fRegD dst, iRegIorL2I src)
4050 %{
4051 single_instruction;
4052 src : S1(read);
4053 dst : S5(write);
4054 DECODE : ID;
4055 FPU : S5;
4056 %}
4057
4058 pipe_class fp_l2d(fRegD dst, iRegIorL2I src)
4059 %{
4060 single_instruction;
4061 src : S1(read);
4062 dst : S5(write);
4063 DECODE : ID;
4064 FPU : S5;
4065 %}
4066
4067 pipe_class fp_div_s(fRegF dst, fRegF src1, fRegF src2)
4068 %{
4069 single_instruction;
4070 src1 : S1(read);
4071 src2 : S2(read);
4072 dst : S5(write);
4073 DECODE : ID;
4074 FPU : S5;
4075 %}
4076
4077 pipe_class fp_div_d(fRegD dst, fRegD src1, fRegD src2)
4078 %{
4079 single_instruction;
4080 src1 : S1(read);
4081 src2 : S2(read);
4082 dst : S5(write);
4083 DECODE : ID;
4084 FPU : S5;
4085 %}
4086
4087 pipe_class fp_sqrt_s(fRegF dst, fRegF src)
4088 %{
4089 single_instruction;
4090 src : S1(read);
4091 dst : S5(write);
4092 DECODE : ID;
4093 FPU : S5;
4094 %}
4095
4096 pipe_class fp_sqrt_d(fRegD dst, fRegD src)
4097 %{
4098 single_instruction;
4099 src : S1(read);
4100 dst : S5(write);
4101 DECODE : ID;
4102 FPU : S5;
4103 %}
4104
4105 pipe_class fp_load_constant_s(fRegF dst)
4106 %{
4107 single_instruction;
4108 dst : S5(write);
4109 DECODE : ID;
4110 FPU : S5;
4111 %}
4112
4113 pipe_class fp_load_constant_d(fRegD dst)
4114 %{
4115 single_instruction;
4116 dst : S5(write);
4117 DECODE : ID;
4118 FPU : S5;
4119 %}
4120
4121 pipe_class fp_load_mem_s(fRegF dst, memory mem)
4122 %{
4123 single_instruction;
4124 mem : S1(read);
4125 dst : S5(write);
4126 DECODE : ID;
4127 LDST : MEM;
4128 %}
4129
4130 pipe_class fp_load_mem_d(fRegD dst, memory mem)
4131 %{
4132 single_instruction;
4133 mem : S1(read);
4134 dst : S5(write);
4135 DECODE : ID;
4136 LDST : MEM;
4137 %}
4138
4139 pipe_class fp_store_reg_s(fRegF src, memory mem)
4140 %{
4141 single_instruction;
4142 src : S1(read);
4143 mem : S5(write);
4144 DECODE : ID;
4145 LDST : MEM;
4146 %}
4147
4148 pipe_class fp_store_reg_d(fRegD src, memory mem)
4149 %{
4150 single_instruction;
4151 src : S1(read);
4152 mem : S5(write);
4153 DECODE : ID;
4154 LDST : MEM;
4155 %}
4156
4157 //------- Integer ALU operations --------------------------
4158
4159 // Integer ALU reg-reg operation
4160 // Operands needs in ID, result generated in EX
4161 // E.g. ADD Rd, Rs1, Rs2
4162 pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2)
4163 %{
4164 single_instruction;
4165 dst : EX(write);
4166 src1 : ID(read);
4167 src2 : ID(read);
4168 DECODE : ID;
4169 ALU : EX;
4170 %}
4171
4172 // Integer ALU reg operation with constant shift
4173 // E.g. SLLI Rd, Rs1, #shift
4174 pipe_class ialu_reg_shift(iRegI dst, iRegI src1)
4175 %{
4176 single_instruction;
4177 dst : EX(write);
4178 src1 : ID(read);
4179 DECODE : ID;
4180 ALU : EX;
4181 %}
4182
4183 // Integer ALU reg-reg operation with variable shift
4184 // both operands must be available in ID
4185 // E.g. SLL Rd, Rs1, Rs2
4186 pipe_class ialu_reg_reg_vshift(iRegI dst, iRegI src1, iRegI src2)
4187 %{
4188 single_instruction;
4189 dst : EX(write);
4190 src1 : ID(read);
4191 src2 : ID(read);
4192 DECODE : ID;
4193 ALU : EX;
4194 %}
4195
4196 // Integer ALU reg operation
4197 // E.g. NEG Rd, Rs2
4198 pipe_class ialu_reg(iRegI dst, iRegI src)
4199 %{
4200 single_instruction;
4201 dst : EX(write);
4202 src : ID(read);
4203 DECODE : ID;
4204 ALU : EX;
4205 %}
4206
4207 // Integer ALU reg immediate operation
4208 // E.g. ADDI Rd, Rs1, #imm
4209 pipe_class ialu_reg_imm(iRegI dst, iRegI src1)
4210 %{
4211 single_instruction;
4212 dst : EX(write);
4213 src1 : ID(read);
4214 DECODE : ID;
4215 ALU : EX;
4216 %}
4217
4218 // Integer ALU immediate operation (no source operands)
4219 // E.g. LI Rd, #imm
4220 pipe_class ialu_imm(iRegI dst)
4221 %{
4222 single_instruction;
4223 dst : EX(write);
4224 DECODE : ID;
4225 ALU : EX;
4226 %}
4227
4228 //------- Multiply pipeline operations --------------------
4229
4230 // Multiply reg-reg
4231 // E.g. MULW Rd, Rs1, Rs2
4232 pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2)
4233 %{
4234 single_instruction;
4235 dst : WR(write);
4236 src1 : ID(read);
4237 src2 : ID(read);
4238 DECODE : ID;
4239 MUL : WR;
4240 %}
4241
4242 // E.g. MUL RD, Rs1, Rs2
4243 pipe_class lmul_reg_reg(iRegL dst, iRegL src1, iRegL src2)
4244 %{
4245 single_instruction;
4246 fixed_latency(3); // Maximum latency for 64 bit mul
4247 dst : WR(write);
4248 src1 : ID(read);
4249 src2 : ID(read);
4250 DECODE : ID;
4251 MUL : WR;
4252 %}
4253
4254 //------- Divide pipeline operations --------------------
4255
4256 // E.g. DIVW Rd, Rs1, Rs2
4257 pipe_class idiv_reg_reg(iRegI dst, iRegI src1, iRegI src2)
4258 %{
4259 single_instruction;
4260 fixed_latency(8); // Maximum latency for 32 bit divide
4261 dst : WR(write);
4262 src1 : ID(read);
4263 src2 : ID(read);
4264 DECODE : ID;
4265 DIV : WR;
4266 %}
4267
4268 // E.g. DIV RD, Rs1, Rs2
4269 pipe_class ldiv_reg_reg(iRegL dst, iRegL src1, iRegL src2)
4270 %{
4271 single_instruction;
4272 fixed_latency(16); // Maximum latency for 64 bit divide
4273 dst : WR(write);
4274 src1 : ID(read);
4275 src2 : ID(read);
4276 DECODE : ID;
4277 DIV : WR;
4278 %}
4279
4280 //------- Load pipeline operations ------------------------
4281
4282 // Load - prefetch
4283 // Eg. PREFETCH_W mem
4284 pipe_class iload_prefetch(memory mem)
4285 %{
4286 single_instruction;
4287 mem : ID(read);
4288 DECODE : ID;
4289 LDST : MEM;
4290 %}
4291
4292 // Load - reg, mem
4293 // E.g. LA Rd, mem
4294 pipe_class iload_reg_mem(iRegI dst, memory mem)
4295 %{
4296 single_instruction;
4297 dst : WR(write);
4298 mem : ID(read);
4299 DECODE : ID;
4300 LDST : MEM;
4301 %}
4302
4303 // Load - reg, reg
4304 // E.g. LD Rd, Rs
4305 pipe_class iload_reg_reg(iRegI dst, iRegI src)
4306 %{
4307 single_instruction;
4308 dst : WR(write);
4309 src : ID(read);
4310 DECODE : ID;
4311 LDST : MEM;
4312 %}
4313
4314 //------- Store pipeline operations -----------------------
4315
4316 // Store - zr, mem
4317 // E.g. SD zr, mem
4318 pipe_class istore_mem(memory mem)
4319 %{
4320 single_instruction;
4321 mem : ID(read);
4322 DECODE : ID;
4323 LDST : MEM;
4324 %}
4325
4326 // Store - reg, mem
4327 // E.g. SD Rs, mem
4328 pipe_class istore_reg_mem(iRegI src, memory mem)
4329 %{
4330 single_instruction;
4331 mem : ID(read);
4332 src : EX(read);
4333 DECODE : ID;
4334 LDST : MEM;
4335 %}
4336
4337 // Store - reg, reg
4338 // E.g. SD Rs2, Rs1
4339 pipe_class istore_reg_reg(iRegI dst, iRegI src)
4340 %{
4341 single_instruction;
4342 dst : ID(read);
4343 src : EX(read);
4344 DECODE : ID;
4345 LDST : MEM;
4346 %}
4347
4348 //------- Control transfer pipeline operations ------------
4349
4350 // Branch
4351 pipe_class pipe_branch()
4352 %{
4353 single_instruction;
4354 DECODE : ID;
4355 BRANCH : EX;
4356 %}
4357
4358 // Branch
4359 pipe_class pipe_branch_reg(iRegI src)
4360 %{
4361 single_instruction;
4362 src : ID(read);
4363 DECODE : ID;
4364 BRANCH : EX;
4365 %}
4366
4367 // Compare & Branch
4368 // E.g. BEQ Rs1, Rs2, L
4369 pipe_class pipe_cmp_branch(iRegI src1, iRegI src2)
4370 %{
4371 single_instruction;
4372 src1 : ID(read);
4373 src2 : ID(read);
4374 DECODE : ID;
4375 BRANCH : EX;
4376 %}
4377
4378 // E.g. BEQZ Rs, L
4379 pipe_class pipe_cmpz_branch(iRegI src)
4380 %{
4381 single_instruction;
4382 src : ID(read);
4383 DECODE : ID;
4384 BRANCH : EX;
4385 %}
4386
4387 //------- Synchronisation operations ----------------------
4388 // Any operation requiring serialization
4389 // E.g. FENCE/Atomic Ops/Load Acquire/Store Release
4390 pipe_class pipe_serial()
4391 %{
4392 single_instruction;
4393 force_serialization;
4394 fixed_latency(16);
4395 DECODE : ID;
4396 LDST : MEM;
4397 %}
4398
4399 pipe_class pipe_slow()
4400 %{
4401 instruction_count(10);
4402 multiple_bundles;
4403 force_serialization;
4404 fixed_latency(16);
4405 DECODE : ID;
4406 LDST : MEM;
4407 %}
4408
4409 // The real do-nothing guy
4410 pipe_class real_empty()
4411 %{
4412 instruction_count(0);
4413 %}
4414
4415 // Empty pipeline class
4416 pipe_class pipe_class_empty()
4417 %{
4418 single_instruction;
4419 fixed_latency(0);
4420 %}
4421
4422 // Default pipeline class.
4423 pipe_class pipe_class_default()
4424 %{
4425 single_instruction;
4426 fixed_latency(2);
4427 %}
4428
4429 // Pipeline class for compares.
4430 pipe_class pipe_class_compare()
4431 %{
4432 single_instruction;
4433 fixed_latency(16);
4434 %}
4435
4436 // Pipeline class for memory operations.
4437 pipe_class pipe_class_memory()
4438 %{
4439 single_instruction;
4440 fixed_latency(16);
4441 %}
4442
4443 // Pipeline class for call.
4444 pipe_class pipe_class_call()
4445 %{
4446 single_instruction;
4447 fixed_latency(100);
4448 %}
4449
4450 // Define the class for the Nop node.
4451 define %{
4452 MachNop = pipe_class_empty;
4453 %}
4454 %}
4455 //----------INSTRUCTIONS-------------------------------------------------------
4456 //
4457 // match -- States which machine-independent subtree may be replaced
4458 // by this instruction.
4459 // ins_cost -- The estimated cost of this instruction is used by instruction
4460 // selection to identify a minimum cost tree of machine
4461 // instructions that matches a tree of machine-independent
4462 // instructions.
4463 // format -- A string providing the disassembly for this instruction.
4464 // The value of an instruction's operand may be inserted
4465 // by referring to it with a '$' prefix.
4466 // opcode -- Three instruction opcodes may be provided. These are referred
4467 // to within an encode class as $primary, $secondary, and $tertiary
4468 // rrspectively. The primary opcode is commonly used to
4469 // indicate the type of machine instruction, while secondary
4470 // and tertiary are often used for prefix options or addressing
4471 // modes.
4472 // ins_encode -- A list of encode classes with parameters. The encode class
4473 // name must have been defined in an 'enc_class' specification
4474 // in the encode section of the architecture description.
4475
4476 // ============================================================================
4477 // Memory (Load/Store) Instructions
4478
4479 // Load Instructions
4480
4481 // Load Byte (8 bit signed)
4482 instruct loadB(iRegINoSp dst, memory mem)
4483 %{
4484 match(Set dst (LoadB mem));
4485
4486 ins_cost(LOAD_COST);
4487 format %{ "lb $dst, $mem\t# byte, #@loadB" %}
4488
4489 ins_encode %{
4490 __ lb(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4491 %}
4492
4493 ins_pipe(iload_reg_mem);
4494 %}
4495
4496 // Load Byte (8 bit signed) into long
4497 instruct loadB2L(iRegLNoSp dst, memory mem)
4498 %{
4499 match(Set dst (ConvI2L (LoadB mem)));
4500
4501 ins_cost(LOAD_COST);
4502 format %{ "lb $dst, $mem\t# byte, #@loadB2L" %}
4503
4504 ins_encode %{
4505 __ lb(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4506 %}
4507
4508 ins_pipe(iload_reg_mem);
4509 %}
4510
4511 // Load Byte (8 bit unsigned)
4512 instruct loadUB(iRegINoSp dst, memory mem)
4513 %{
4514 match(Set dst (LoadUB mem));
4515
4516 ins_cost(LOAD_COST);
4517 format %{ "lbu $dst, $mem\t# byte, #@loadUB" %}
4518
4519 ins_encode %{
4520 __ lbu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4521 %}
4522
4523 ins_pipe(iload_reg_mem);
4524 %}
4525
4526 // Load Byte (8 bit unsigned) into long
4527 instruct loadUB2L(iRegLNoSp dst, memory mem)
4528 %{
4529 match(Set dst (ConvI2L (LoadUB mem)));
4530
4531 ins_cost(LOAD_COST);
4532 format %{ "lbu $dst, $mem\t# byte, #@loadUB2L" %}
4533
4534 ins_encode %{
4535 __ lbu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4536 %}
4537
4538 ins_pipe(iload_reg_mem);
4539 %}
4540
4541 // Load Short (16 bit signed)
4542 instruct loadS(iRegINoSp dst, memory mem)
4543 %{
4544 match(Set dst (LoadS mem));
4545
4546 ins_cost(LOAD_COST);
4547 format %{ "lh $dst, $mem\t# short, #@loadS" %}
4548
4549 ins_encode %{
4550 __ lh(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4551 %}
4552
4553 ins_pipe(iload_reg_mem);
4554 %}
4555
4556 // Load Short (16 bit signed) into long
4557 instruct loadS2L(iRegLNoSp dst, memory mem)
4558 %{
4559 match(Set dst (ConvI2L (LoadS mem)));
4560
4561 ins_cost(LOAD_COST);
4562 format %{ "lh $dst, $mem\t# short, #@loadS2L" %}
4563
4564 ins_encode %{
4565 __ lh(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4566 %}
4567
4568 ins_pipe(iload_reg_mem);
4569 %}
4570
4571 // Load Char (16 bit unsigned)
4572 instruct loadUS(iRegINoSp dst, memory mem)
4573 %{
4574 match(Set dst (LoadUS mem));
4575
4576 ins_cost(LOAD_COST);
4577 format %{ "lhu $dst, $mem\t# short, #@loadUS" %}
4578
4579 ins_encode %{
4580 __ lhu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4581 %}
4582
4583 ins_pipe(iload_reg_mem);
4584 %}
4585
4586 // Load Short/Char (16 bit unsigned) into long
4587 instruct loadUS2L(iRegLNoSp dst, memory mem)
4588 %{
4589 match(Set dst (ConvI2L (LoadUS mem)));
4590
4591 ins_cost(LOAD_COST);
4592 format %{ "lhu $dst, $mem\t# short, #@loadUS2L" %}
4593
4594 ins_encode %{
4595 __ lhu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4596 %}
4597
4598 ins_pipe(iload_reg_mem);
4599 %}
4600
4601 // Load Integer (32 bit signed)
4602 instruct loadI(iRegINoSp dst, memory mem)
4603 %{
4604 match(Set dst (LoadI mem));
4605
4606 ins_cost(LOAD_COST);
4607 format %{ "lw $dst, $mem\t# int, #@loadI" %}
4608
4609 ins_encode %{
4610 __ lw(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4611 %}
4612
4613 ins_pipe(iload_reg_mem);
4614 %}
4615
4616 // Load Integer (32 bit signed) into long
4617 instruct loadI2L(iRegLNoSp dst, memory mem)
4618 %{
4619 match(Set dst (ConvI2L (LoadI mem)));
4620
4621 ins_cost(LOAD_COST);
4622 format %{ "lw $dst, $mem\t# int, #@loadI2L" %}
4623
4624 ins_encode %{
4625 __ lw(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4626 %}
4627
4628 ins_pipe(iload_reg_mem);
4629 %}
4630
4631 // Load Integer (32 bit unsigned) into long
4632 instruct loadUI2L(iRegLNoSp dst, memory mem, immL_32bits mask)
4633 %{
4634 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
4635
4636 ins_cost(LOAD_COST);
4637 format %{ "lwu $dst, $mem\t# int, #@loadUI2L" %}
4638
4639 ins_encode %{
4640 __ lwu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4641 %}
4642
4643 ins_pipe(iload_reg_mem);
4644 %}
4645
4646 // Load Long (64 bit signed)
4647 instruct loadL(iRegLNoSp dst, memory mem)
4648 %{
4649 match(Set dst (LoadL mem));
4650
4651 ins_cost(LOAD_COST);
4652 format %{ "ld $dst, $mem\t# int, #@loadL" %}
4653
4654 ins_encode %{
4655 __ ld(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4656 %}
4657
4658 ins_pipe(iload_reg_mem);
4659 %}
4660
4661 // Load Range
4662 instruct loadRange(iRegINoSp dst, memory mem)
4663 %{
4664 match(Set dst (LoadRange mem));
4665
4666 ins_cost(LOAD_COST);
4667 format %{ "lwu $dst, $mem\t# range, #@loadRange" %}
4668
4669 ins_encode %{
4670 __ lwu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4671 %}
4672
4673 ins_pipe(iload_reg_mem);
4674 %}
4675
4676 // Load Pointer
4677 instruct loadP(iRegPNoSp dst, memory mem)
4678 %{
4679 match(Set dst (LoadP mem));
4680 predicate(n->as_Load()->barrier_data() == 0);
4681
4682 ins_cost(LOAD_COST);
4683 format %{ "ld $dst, $mem\t# ptr, #@loadP" %}
4684
4685 ins_encode %{
4686 __ ld(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4687 %}
4688
4689 ins_pipe(iload_reg_mem);
4690 %}
4691
4692 // Load Compressed Pointer
4693 instruct loadN(iRegNNoSp dst, memory mem)
4694 %{
4695 predicate(n->as_Load()->barrier_data() == 0);
4696 match(Set dst (LoadN mem));
4697
4698 ins_cost(LOAD_COST);
4699 format %{ "lwu $dst, $mem\t# compressed ptr, #@loadN" %}
4700
4701 ins_encode %{
4702 __ lwu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4703 %}
4704
4705 ins_pipe(iload_reg_mem);
4706 %}
4707
4708 // Load Klass Pointer
4709 instruct loadKlass(iRegPNoSp dst, memory mem)
4710 %{
4711 match(Set dst (LoadKlass mem));
4712
4713 ins_cost(LOAD_COST);
4714 format %{ "ld $dst, $mem\t# class, #@loadKlass" %}
4715
4716 ins_encode %{
4717 __ ld(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4718 %}
4719
4720 ins_pipe(iload_reg_mem);
4721 %}
4722
4723 // Load Narrow Klass Pointer
4724 instruct loadNKlass(iRegNNoSp dst, memory mem)
4725 %{
4726 predicate(!UseCompactObjectHeaders);
4727 match(Set dst (LoadNKlass mem));
4728
4729 ins_cost(LOAD_COST);
4730 format %{ "lwu $dst, $mem\t# compressed class ptr, #@loadNKlass" %}
4731
4732 ins_encode %{
4733 __ lwu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4734 %}
4735
4736 ins_pipe(iload_reg_mem);
4737 %}
4738
4739 instruct loadNKlassCompactHeaders(iRegNNoSp dst, memory mem)
4740 %{
4741 predicate(UseCompactObjectHeaders);
4742 match(Set dst (LoadNKlass mem));
4743
4744 ins_cost(LOAD_COST);
4745 format %{
4746 "lwu $dst, $mem\t# compressed klass ptr, shifted\n\t"
4747 "srli $dst, $dst, markWord::klass_shift_at_offset"
4748 %}
4749
4750 ins_encode %{
4751 Unimplemented();
4752 // __ lwu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4753 // __ srli(as_Register($dst$$reg), as_Register($dst$$reg), (unsigned) markWord::klass_shift_at_offset);
4754 %}
4755
4756 ins_pipe(iload_reg_mem);
4757 %}
4758
4759 // Load Float
4760 instruct loadF(fRegF dst, memory mem)
4761 %{
4762 match(Set dst (LoadF mem));
4763
4764 ins_cost(LOAD_COST);
4765 format %{ "flw $dst, $mem\t# float, #@loadF" %}
4766
4767 ins_encode %{
4768 __ flw(as_FloatRegister($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4769 %}
4770
4771 ins_pipe(fp_load_mem_s);
4772 %}
4773
4774 // Load Double
4775 instruct loadD(fRegD dst, memory mem)
4776 %{
4777 match(Set dst (LoadD mem));
4778
4779 ins_cost(LOAD_COST);
4780 format %{ "fld $dst, $mem\t# double, #@loadD" %}
4781
4782 ins_encode %{
4783 __ fld(as_FloatRegister($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4784 %}
4785
4786 ins_pipe(fp_load_mem_d);
4787 %}
4788
4789 // Load Int Constant
4790 instruct loadConI(iRegINoSp dst, immI src)
4791 %{
4792 match(Set dst src);
4793
4794 ins_cost(ALU_COST);
4795 format %{ "mv $dst, $src\t# int, #@loadConI" %}
4796
4797 ins_encode(riscv_enc_mov_imm(dst, src));
4798
4799 ins_pipe(ialu_imm);
4800 %}
4801
4802 // Load Long Constant
4803 instruct loadConL(iRegLNoSp dst, immL src)
4804 %{
4805 match(Set dst src);
4806
4807 ins_cost(ALU_COST);
4808 format %{ "mv $dst, $src\t# long, #@loadConL" %}
4809
4810 ins_encode(riscv_enc_mov_imm(dst, src));
4811
4812 ins_pipe(ialu_imm);
4813 %}
4814
4815 // Load Pointer Constant
4816 instruct loadConP(iRegPNoSp dst, immP con)
4817 %{
4818 match(Set dst con);
4819
4820 ins_cost(ALU_COST);
4821 format %{ "mv $dst, $con\t# ptr, #@loadConP" %}
4822
4823 ins_encode(riscv_enc_mov_p(dst, con));
4824
4825 ins_pipe(ialu_imm);
4826 %}
4827
4828 // Load Null Pointer Constant
4829 instruct loadConP0(iRegPNoSp dst, immP0 con)
4830 %{
4831 match(Set dst con);
4832
4833 ins_cost(ALU_COST);
4834 format %{ "mv $dst, $con\t# null pointer, #@loadConP0" %}
4835
4836 ins_encode(riscv_enc_mov_zero(dst));
4837
4838 ins_pipe(ialu_imm);
4839 %}
4840
4841 // Load Pointer Constant One
4842 instruct loadConP1(iRegPNoSp dst, immP_1 con)
4843 %{
4844 match(Set dst con);
4845
4846 ins_cost(ALU_COST);
4847 format %{ "mv $dst, $con\t# load ptr constant one, #@loadConP1" %}
4848
4849 ins_encode(riscv_enc_mov_p1(dst));
4850
4851 ins_pipe(ialu_imm);
4852 %}
4853
4854 // Load Byte Map Base Constant
4855 instruct loadByteMapBase(iRegPNoSp dst, immByteMapBase con)
4856 %{
4857 match(Set dst con);
4858 ins_cost(ALU_COST);
4859 format %{ "mv $dst, $con\t# Byte Map Base, #@loadByteMapBase" %}
4860
4861 ins_encode(riscv_enc_mov_byte_map_base(dst));
4862
4863 ins_pipe(ialu_imm);
4864 %}
4865
4866 // Load Narrow Pointer Constant
4867 instruct loadConN(iRegNNoSp dst, immN con)
4868 %{
4869 match(Set dst con);
4870
4871 ins_cost(ALU_COST * 4);
4872 format %{ "mv $dst, $con\t# compressed ptr, #@loadConN" %}
4873
4874 ins_encode(riscv_enc_mov_n(dst, con));
4875
4876 ins_pipe(ialu_imm);
4877 %}
4878
4879 // Load Narrow Null Pointer Constant
4880 instruct loadConN0(iRegNNoSp dst, immN0 con)
4881 %{
4882 match(Set dst con);
4883
4884 ins_cost(ALU_COST);
4885 format %{ "mv $dst, $con\t# compressed null pointer, #@loadConN0" %}
4886
4887 ins_encode(riscv_enc_mov_zero(dst));
4888
4889 ins_pipe(ialu_imm);
4890 %}
4891
4892 // Load Narrow Klass Constant
4893 instruct loadConNKlass(iRegNNoSp dst, immNKlass con)
4894 %{
4895 match(Set dst con);
4896
4897 ins_cost(ALU_COST * 6);
4898 format %{ "mv $dst, $con\t# compressed klass ptr, #@loadConNKlass" %}
4899
4900 ins_encode(riscv_enc_mov_nk(dst, con));
4901
4902 ins_pipe(ialu_imm);
4903 %}
4904
4905 // Load Half Float Constant
4906 instruct loadConH(fRegF dst, immH con) %{
4907 match(Set dst con);
4908
4909 ins_cost(LOAD_COST);
4910 format %{
4911 "flh $dst, [$constantaddress]\t# load from constant table: float=$con, #@loadConH"
4912 %}
4913
4914 ins_encode %{
4915 assert(UseZfh || UseZfhmin, "must");
4916 if (MacroAssembler::can_hf_imm_load($con$$constant)) {
4917 __ fli_h(as_FloatRegister($dst$$reg), $con$$constant);
4918 } else {
4919 __ flh(as_FloatRegister($dst$$reg), $constantaddress($con));
4920 }
4921 %}
4922
4923 ins_pipe(fp_load_constant_s);
4924 %}
4925
4926 instruct loadConH0(fRegF dst, immH0 con) %{
4927 match(Set dst con);
4928
4929 ins_cost(XFER_COST);
4930
4931 format %{ "fmv.h.x $dst, zr\t# float, #@loadConH0" %}
4932
4933 ins_encode %{
4934 assert(UseZfh || UseZfhmin, "must");
4935 __ fmv_h_x(as_FloatRegister($dst$$reg), zr);
4936 %}
4937
4938 ins_pipe(fp_load_constant_s);
4939 %}
4940
4941 // Load Float Constant
4942 instruct loadConF(fRegF dst, immF con) %{
4943 match(Set dst con);
4944
4945 ins_cost(LOAD_COST);
4946 format %{
4947 "flw $dst, [$constantaddress]\t# load from constant table: float=$con, #@loadConF"
4948 %}
4949
4950 ins_encode %{
4951 if (MacroAssembler::can_fp_imm_load($con$$constant)) {
4952 __ fli_s(as_FloatRegister($dst$$reg), $con$$constant);
4953 } else {
4954 __ flw(as_FloatRegister($dst$$reg), $constantaddress($con));
4955 }
4956 %}
4957
4958 ins_pipe(fp_load_constant_s);
4959 %}
4960
4961 instruct loadConF0(fRegF dst, immF0 con) %{
4962 match(Set dst con);
4963
4964 ins_cost(XFER_COST);
4965
4966 format %{ "fmv.w.x $dst, zr\t# float, #@loadConF0" %}
4967
4968 ins_encode %{
4969 __ fmv_w_x(as_FloatRegister($dst$$reg), zr);
4970 %}
4971
4972 ins_pipe(fp_load_constant_s);
4973 %}
4974
4975 // Load Double Constant
4976 instruct loadConD(fRegD dst, immD con) %{
4977 match(Set dst con);
4978
4979 ins_cost(LOAD_COST);
4980 format %{
4981 "fld $dst, [$constantaddress]\t# load from constant table: double=$con, #@loadConD"
4982 %}
4983
4984 ins_encode %{
4985 if (MacroAssembler::can_dp_imm_load($con$$constant)) {
4986 __ fli_d(as_FloatRegister($dst$$reg), $con$$constant);
4987 } else {
4988 __ fld(as_FloatRegister($dst$$reg), $constantaddress($con));
4989 }
4990 %}
4991
4992 ins_pipe(fp_load_constant_d);
4993 %}
4994
4995 instruct loadConD0(fRegD dst, immD0 con) %{
4996 match(Set dst con);
4997
4998 ins_cost(XFER_COST);
4999
5000 format %{ "fmv.d.x $dst, zr\t# double, #@loadConD0" %}
5001
5002 ins_encode %{
5003 __ fmv_d_x(as_FloatRegister($dst$$reg), zr);
5004 %}
5005
5006 ins_pipe(fp_load_constant_d);
5007 %}
5008
5009 // Store Byte
5010 instruct storeB(iRegIorL2I src, memory mem)
5011 %{
5012 match(Set mem (StoreB mem src));
5013
5014 ins_cost(STORE_COST);
5015 format %{ "sb $src, $mem\t# byte, #@storeB" %}
5016
5017 ins_encode %{
5018 __ sb(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5019 %}
5020
5021 ins_pipe(istore_reg_mem);
5022 %}
5023
5024 instruct storeimmB0(immI0 zero, memory mem)
5025 %{
5026 match(Set mem (StoreB mem zero));
5027
5028 ins_cost(STORE_COST);
5029 format %{ "sb zr, $mem\t# byte, #@storeimmB0" %}
5030
5031 ins_encode %{
5032 __ sb(zr, Address(as_Register($mem$$base), $mem$$disp));
5033 %}
5034
5035 ins_pipe(istore_mem);
5036 %}
5037
5038 // Store Char/Short
5039 instruct storeC(iRegIorL2I src, memory mem)
5040 %{
5041 match(Set mem (StoreC mem src));
5042
5043 ins_cost(STORE_COST);
5044 format %{ "sh $src, $mem\t# short, #@storeC" %}
5045
5046 ins_encode %{
5047 __ sh(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5048 %}
5049
5050 ins_pipe(istore_reg_mem);
5051 %}
5052
5053 instruct storeimmC0(immI0 zero, memory mem)
5054 %{
5055 match(Set mem (StoreC mem zero));
5056
5057 ins_cost(STORE_COST);
5058 format %{ "sh zr, $mem\t# short, #@storeimmC0" %}
5059
5060 ins_encode %{
5061 __ sh(zr, Address(as_Register($mem$$base), $mem$$disp));
5062 %}
5063
5064 ins_pipe(istore_mem);
5065 %}
5066
5067 // Store Integer
5068 instruct storeI(iRegIorL2I src, memory mem)
5069 %{
5070 match(Set mem(StoreI mem src));
5071
5072 ins_cost(STORE_COST);
5073 format %{ "sw $src, $mem\t# int, #@storeI" %}
5074
5075 ins_encode %{
5076 __ sw(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5077 %}
5078
5079 ins_pipe(istore_reg_mem);
5080 %}
5081
5082 instruct storeimmI0(immI0 zero, memory mem)
5083 %{
5084 match(Set mem(StoreI mem zero));
5085
5086 ins_cost(STORE_COST);
5087 format %{ "sw zr, $mem\t# int, #@storeimmI0" %}
5088
5089 ins_encode %{
5090 __ sw(zr, Address(as_Register($mem$$base), $mem$$disp));
5091 %}
5092
5093 ins_pipe(istore_mem);
5094 %}
5095
5096 // Store Long (64 bit signed)
5097 instruct storeL(iRegL src, memory mem)
5098 %{
5099 match(Set mem (StoreL mem src));
5100
5101 ins_cost(STORE_COST);
5102 format %{ "sd $src, $mem\t# long, #@storeL" %}
5103
5104 ins_encode %{
5105 __ sd(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5106 %}
5107
5108 ins_pipe(istore_reg_mem);
5109 %}
5110
5111 // Store Long (64 bit signed)
5112 instruct storeimmL0(immL0 zero, memory mem)
5113 %{
5114 match(Set mem (StoreL mem zero));
5115
5116 ins_cost(STORE_COST);
5117 format %{ "sd zr, $mem\t# long, #@storeimmL0" %}
5118
5119 ins_encode %{
5120 __ sd(zr, Address(as_Register($mem$$base), $mem$$disp));
5121 %}
5122
5123 ins_pipe(istore_mem);
5124 %}
5125
5126 // Store Pointer
5127 instruct storeP(iRegP src, memory mem)
5128 %{
5129 match(Set mem (StoreP mem src));
5130 predicate(n->as_Store()->barrier_data() == 0);
5131
5132 ins_cost(STORE_COST);
5133 format %{ "sd $src, $mem\t# ptr, #@storeP" %}
5134
5135 ins_encode %{
5136 __ sd(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5137 %}
5138
5139 ins_pipe(istore_reg_mem);
5140 %}
5141
5142 // Store Pointer
5143 instruct storeimmP0(immP0 zero, memory mem)
5144 %{
5145 match(Set mem (StoreP mem zero));
5146 predicate(n->as_Store()->barrier_data() == 0);
5147
5148 ins_cost(STORE_COST);
5149 format %{ "sd zr, $mem\t# ptr, #@storeimmP0" %}
5150
5151 ins_encode %{
5152 __ sd(zr, Address(as_Register($mem$$base), $mem$$disp));
5153 %}
5154
5155 ins_pipe(istore_mem);
5156 %}
5157
5158 // Store Compressed Pointer
5159 instruct storeN(iRegN src, memory mem)
5160 %{
5161 predicate(n->as_Store()->barrier_data() == 0);
5162 match(Set mem (StoreN mem src));
5163
5164 ins_cost(STORE_COST);
5165 format %{ "sw $src, $mem\t# compressed ptr, #@storeN" %}
5166
5167 ins_encode %{
5168 __ sw(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5169 %}
5170
5171 ins_pipe(istore_reg_mem);
5172 %}
5173
5174 instruct storeImmN0(immN0 zero, memory mem)
5175 %{
5176 predicate(n->as_Store()->barrier_data() == 0);
5177 match(Set mem (StoreN mem zero));
5178
5179 ins_cost(STORE_COST);
5180 format %{ "sw zr, $mem\t# compressed ptr, #@storeImmN0" %}
5181
5182 ins_encode %{
5183 __ sw(zr, Address(as_Register($mem$$base), $mem$$disp));
5184 %}
5185
5186 ins_pipe(istore_reg_mem);
5187 %}
5188
5189 // Store Float
5190 instruct storeF(fRegF src, memory mem)
5191 %{
5192 match(Set mem (StoreF mem src));
5193
5194 ins_cost(STORE_COST);
5195 format %{ "fsw $src, $mem\t# float, #@storeF" %}
5196
5197 ins_encode %{
5198 __ fsw(as_FloatRegister($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5199 %}
5200
5201 ins_pipe(fp_store_reg_s);
5202 %}
5203
5204 // Store Double
5205 instruct storeD(fRegD src, memory mem)
5206 %{
5207 match(Set mem (StoreD mem src));
5208
5209 ins_cost(STORE_COST);
5210 format %{ "fsd $src, $mem\t# double, #@storeD" %}
5211
5212 ins_encode %{
5213 __ fsd(as_FloatRegister($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5214 %}
5215
5216 ins_pipe(fp_store_reg_d);
5217 %}
5218
5219 // Store Compressed Klass Pointer
5220 instruct storeNKlass(iRegN src, memory mem)
5221 %{
5222 match(Set mem (StoreNKlass mem src));
5223
5224 ins_cost(STORE_COST);
5225 format %{ "sw $src, $mem\t# compressed klass ptr, #@storeNKlass" %}
5226
5227 ins_encode %{
5228 __ sw(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5229 %}
5230
5231 ins_pipe(istore_reg_mem);
5232 %}
5233
5234 // ============================================================================
5235 // Prefetch instructions
5236 // Must be safe to execute with invalid address (cannot fault).
5237
5238 instruct prefetchalloc( memory mem ) %{
5239 predicate(UseZicbop);
5240 match(PrefetchAllocation mem);
5241
5242 ins_cost(ALU_COST * 1);
5243 format %{ "prefetch_w $mem\t# Prefetch for write" %}
5244
5245 ins_encode %{
5246 if (Assembler::is_simm12($mem$$disp)) {
5247 if (($mem$$disp & 0x1f) == 0) {
5248 __ prefetch_w(as_Register($mem$$base), $mem$$disp);
5249 } else {
5250 __ addi(t0, as_Register($mem$$base), $mem$$disp);
5251 __ prefetch_w(t0, 0);
5252 }
5253 } else {
5254 __ mv(t0, $mem$$disp);
5255 __ add(t0, as_Register($mem$$base), t0);
5256 __ prefetch_w(t0, 0);
5257 }
5258 %}
5259
5260 ins_pipe(iload_prefetch);
5261 %}
5262
5263 // ============================================================================
5264 // Atomic operation instructions
5265 //
5266
5267 // standard CompareAndSwapX when we are using barriers
5268 // these have higher priority than the rules selected by a predicate
5269 instruct compareAndSwapB(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5270 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5271 %{
5272 match(Set res (CompareAndSwapB mem (Binary oldval newval)));
5273
5274 ins_cost(LOAD_COST + STORE_COST + ALU_COST * 10 + BRANCH_COST * 4);
5275
5276 effect(TEMP_DEF res, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3, KILL cr);
5277
5278 format %{
5279 "cmpxchg $mem, $oldval, $newval\t# (byte) if $mem == $oldval then $mem <-- $newval\n\t"
5280 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapB"
5281 %}
5282
5283 ins_encode %{
5284 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5285 Assembler::relaxed /* acquire */, Assembler::rl /* release */, $res$$Register,
5286 true /* result as bool */, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5287 %}
5288
5289 ins_pipe(pipe_slow);
5290 %}
5291
5292 instruct compareAndSwapS(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5293 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5294 %{
5295 match(Set res (CompareAndSwapS mem (Binary oldval newval)));
5296
5297 ins_cost(LOAD_COST + STORE_COST + ALU_COST * 11 + BRANCH_COST * 4);
5298
5299 effect(TEMP_DEF res, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3, KILL cr);
5300
5301 format %{
5302 "cmpxchg $mem, $oldval, $newval\t# (short) if $mem == $oldval then $mem <-- $newval\n\t"
5303 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapS"
5304 %}
5305
5306 ins_encode %{
5307 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5308 Assembler::relaxed /* acquire */, Assembler::rl /* release */, $res$$Register,
5309 true /* result as bool */, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5310 %}
5311
5312 ins_pipe(pipe_slow);
5313 %}
5314
5315 instruct compareAndSwapI(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5316 %{
5317 match(Set res (CompareAndSwapI mem (Binary oldval newval)));
5318
5319 ins_cost(LOAD_COST + STORE_COST + ALU_COST * 6 + BRANCH_COST * 4);
5320
5321 format %{
5322 "cmpxchg $mem, $oldval, $newval\t# (int) if $mem == $oldval then $mem <-- $newval\n\t"
5323 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapI"
5324 %}
5325
5326 ins_encode(riscv_enc_cmpxchgw(res, mem, oldval, newval));
5327
5328 ins_pipe(pipe_slow);
5329 %}
5330
5331 instruct compareAndSwapL(iRegINoSp res, indirect mem, iRegL oldval, iRegL newval)
5332 %{
5333 match(Set res (CompareAndSwapL mem (Binary oldval newval)));
5334
5335 ins_cost(LOAD_COST + STORE_COST + ALU_COST * 6 + BRANCH_COST * 4);
5336
5337 format %{
5338 "cmpxchg $mem, $oldval, $newval\t# (long) if $mem == $oldval then $mem <-- $newval\n\t"
5339 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapL"
5340 %}
5341
5342 ins_encode(riscv_enc_cmpxchg(res, mem, oldval, newval));
5343
5344 ins_pipe(pipe_slow);
5345 %}
5346
5347 instruct compareAndSwapP(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval)
5348 %{
5349 predicate(n->as_LoadStore()->barrier_data() == 0);
5350
5351 match(Set res (CompareAndSwapP mem (Binary oldval newval)));
5352
5353 ins_cost(LOAD_COST + STORE_COST + ALU_COST * 6 + BRANCH_COST * 4);
5354
5355 format %{
5356 "cmpxchg $mem, $oldval, $newval\t# (ptr) if $mem == $oldval then $mem <-- $newval\n\t"
5357 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapP"
5358 %}
5359
5360 ins_encode(riscv_enc_cmpxchg(res, mem, oldval, newval));
5361
5362 ins_pipe(pipe_slow);
5363 %}
5364
5365 instruct compareAndSwapN(iRegINoSp res, indirect mem, iRegN oldval, iRegN newval)
5366 %{
5367 predicate(n->as_LoadStore()->barrier_data() == 0);
5368 match(Set res (CompareAndSwapN mem (Binary oldval newval)));
5369
5370 ins_cost(LOAD_COST + STORE_COST + ALU_COST * 8 + BRANCH_COST * 4);
5371
5372 format %{
5373 "cmpxchg $mem, $oldval, $newval\t# (narrow oop) if $mem == $oldval then $mem <-- $newval\n\t"
5374 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapN"
5375 %}
5376
5377 ins_encode(riscv_enc_cmpxchgn(res, mem, oldval, newval));
5378
5379 ins_pipe(pipe_slow);
5380 %}
5381
5382 // alternative CompareAndSwapX when we are eliding barriers
5383 instruct compareAndSwapBAcq(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5384 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5385 %{
5386 predicate(needs_acquiring_load_reserved(n));
5387
5388 match(Set res (CompareAndSwapB mem (Binary oldval newval)));
5389
5390 ins_cost(LOAD_COST + STORE_COST + ALU_COST * 10 + BRANCH_COST * 4);
5391
5392 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5393
5394 format %{
5395 "cmpxchg_acq $mem, $oldval, $newval\t# (byte) if $mem == $oldval then $mem <-- $newval\n\t"
5396 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapBAcq"
5397 %}
5398
5399 ins_encode %{
5400 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5401 Assembler::aq /* acquire */, Assembler::rl /* release */, $res$$Register,
5402 true /* result as bool */, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5403 %}
5404
5405 ins_pipe(pipe_slow);
5406 %}
5407
5408 instruct compareAndSwapSAcq(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5409 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5410 %{
5411 predicate(needs_acquiring_load_reserved(n));
5412
5413 match(Set res (CompareAndSwapS mem (Binary oldval newval)));
5414
5415 ins_cost(LOAD_COST + STORE_COST + ALU_COST * 11 + BRANCH_COST * 4);
5416
5417 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5418
5419 format %{
5420 "cmpxchg_acq $mem, $oldval, $newval\t# (short) if $mem == $oldval then $mem <-- $newval\n\t"
5421 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapSAcq"
5422 %}
5423
5424 ins_encode %{
5425 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5426 Assembler::aq /* acquire */, Assembler::rl /* release */, $res$$Register,
5427 true /* result as bool */, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5428 %}
5429
5430 ins_pipe(pipe_slow);
5431 %}
5432
5433 instruct compareAndSwapIAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5434 %{
5435 predicate(needs_acquiring_load_reserved(n));
5436
5437 match(Set res (CompareAndSwapI mem (Binary oldval newval)));
5438
5439 ins_cost(LOAD_COST + STORE_COST + ALU_COST * 6 + BRANCH_COST * 4);
5440
5441 format %{
5442 "cmpxchg_acq $mem, $oldval, $newval\t# (int) if $mem == $oldval then $mem <-- $newval\n\t"
5443 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapIAcq"
5444 %}
5445
5446 ins_encode(riscv_enc_cmpxchgw_acq(res, mem, oldval, newval));
5447
5448 ins_pipe(pipe_slow);
5449 %}
5450
5451 instruct compareAndSwapLAcq(iRegINoSp res, indirect mem, iRegL oldval, iRegL newval)
5452 %{
5453 predicate(needs_acquiring_load_reserved(n));
5454
5455 match(Set res (CompareAndSwapL mem (Binary oldval newval)));
5456
5457 ins_cost(LOAD_COST + STORE_COST + ALU_COST * 6 + BRANCH_COST * 4);
5458
5459 format %{
5460 "cmpxchg_acq $mem, $oldval, $newval\t# (long) if $mem == $oldval then $mem <-- $newval\n\t"
5461 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapLAcq"
5462 %}
5463
5464 ins_encode(riscv_enc_cmpxchg_acq(res, mem, oldval, newval));
5465
5466 ins_pipe(pipe_slow);
5467 %}
5468
5469 instruct compareAndSwapPAcq(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval)
5470 %{
5471 predicate(needs_acquiring_load_reserved(n) && (n->as_LoadStore()->barrier_data() == 0));
5472
5473 match(Set res (CompareAndSwapP mem (Binary oldval newval)));
5474
5475 ins_cost(LOAD_COST + STORE_COST + ALU_COST * 6 + BRANCH_COST * 4);
5476
5477 format %{
5478 "cmpxchg_acq $mem, $oldval, $newval\t# (ptr) if $mem == $oldval then $mem <-- $newval\n\t"
5479 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapPAcq"
5480 %}
5481
5482 ins_encode(riscv_enc_cmpxchg_acq(res, mem, oldval, newval));
5483
5484 ins_pipe(pipe_slow);
5485 %}
5486
5487 instruct compareAndSwapNAcq(iRegINoSp res, indirect mem, iRegN oldval, iRegN newval)
5488 %{
5489 predicate(needs_acquiring_load_reserved(n) && n->as_LoadStore()->barrier_data() == 0);
5490
5491 match(Set res (CompareAndSwapN mem (Binary oldval newval)));
5492
5493 ins_cost(LOAD_COST + STORE_COST + ALU_COST * 8 + BRANCH_COST * 4);
5494
5495 format %{
5496 "cmpxchg_acq $mem, $oldval, $newval\t# (narrow oop) if $mem == $oldval then $mem <-- $newval\n\t"
5497 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapNAcq"
5498 %}
5499
5500 ins_encode(riscv_enc_cmpxchgn_acq(res, mem, oldval, newval));
5501
5502 ins_pipe(pipe_slow);
5503 %}
5504
5505 // Sundry CAS operations. Note that release is always true,
5506 // regardless of the memory ordering of the CAS. This is because we
5507 // need the volatile case to be sequentially consistent but there is
5508 // no trailing StoreLoad barrier emitted by C2. Unfortunately we
5509 // can't check the type of memory ordering here, so we always emit a
5510 // sc_d(w) with rl bit set.
5511 instruct compareAndExchangeB(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5512 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5513 %{
5514 match(Set res (CompareAndExchangeB mem (Binary oldval newval)));
5515
5516 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST * 5);
5517
5518 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5519
5520 format %{
5521 "cmpxchg $res = $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeB"
5522 %}
5523
5524 ins_encode %{
5525 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5526 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
5527 /*result_as_bool*/ false, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5528 %}
5529
5530 ins_pipe(pipe_slow);
5531 %}
5532
5533 instruct compareAndExchangeS(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5534 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5535 %{
5536 match(Set res (CompareAndExchangeS mem (Binary oldval newval)));
5537
5538 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST * 6);
5539
5540 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5541
5542 format %{
5543 "cmpxchg $res = $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeS"
5544 %}
5545
5546 ins_encode %{
5547 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5548 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
5549 /*result_as_bool*/ false, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5550 %}
5551
5552 ins_pipe(pipe_slow);
5553 %}
5554
5555 instruct compareAndExchangeI(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5556 %{
5557 match(Set res (CompareAndExchangeI mem (Binary oldval newval)));
5558
5559 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST);
5560
5561 effect(TEMP_DEF res);
5562
5563 format %{
5564 "cmpxchg $res = $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeI"
5565 %}
5566
5567 ins_encode %{
5568 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
5569 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5570 %}
5571
5572 ins_pipe(pipe_slow);
5573 %}
5574
5575 instruct compareAndExchangeL(iRegLNoSp res, indirect mem, iRegL oldval, iRegL newval)
5576 %{
5577 match(Set res (CompareAndExchangeL mem (Binary oldval newval)));
5578
5579 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST);
5580
5581 effect(TEMP_DEF res);
5582
5583 format %{
5584 "cmpxchg $res = $mem, $oldval, $newval\t# (long, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeL"
5585 %}
5586
5587 ins_encode %{
5588 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5589 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5590 %}
5591
5592 ins_pipe(pipe_slow);
5593 %}
5594
5595 instruct compareAndExchangeN(iRegNNoSp res, indirect mem, iRegN oldval, iRegN newval)
5596 %{
5597 predicate(n->as_LoadStore()->barrier_data() == 0);
5598 match(Set res (CompareAndExchangeN mem (Binary oldval newval)));
5599
5600 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST * 3);
5601
5602 effect(TEMP_DEF res);
5603
5604 format %{
5605 "cmpxchg $res = $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeN"
5606 %}
5607
5608 ins_encode %{
5609 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
5610 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5611 %}
5612
5613 ins_pipe(pipe_slow);
5614 %}
5615
5616 instruct compareAndExchangeP(iRegPNoSp res, indirect mem, iRegP oldval, iRegP newval)
5617 %{
5618 predicate(n->as_LoadStore()->barrier_data() == 0);
5619 match(Set res (CompareAndExchangeP mem (Binary oldval newval)));
5620
5621 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST);
5622
5623 effect(TEMP_DEF res);
5624
5625 format %{
5626 "cmpxchg $res = $mem, $oldval, $newval\t# (ptr, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeP"
5627 %}
5628
5629 ins_encode %{
5630 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5631 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5632 %}
5633
5634 ins_pipe(pipe_slow);
5635 %}
5636
5637 instruct compareAndExchangeBAcq(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5638 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5639 %{
5640 predicate(needs_acquiring_load_reserved(n));
5641
5642 match(Set res (CompareAndExchangeB mem (Binary oldval newval)));
5643
5644 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST * 5);
5645
5646 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5647
5648 format %{
5649 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeBAcq"
5650 %}
5651
5652 ins_encode %{
5653 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5654 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
5655 /*result_as_bool*/ false, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5656 %}
5657
5658 ins_pipe(pipe_slow);
5659 %}
5660
5661 instruct compareAndExchangeSAcq(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5662 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5663 %{
5664 predicate(needs_acquiring_load_reserved(n));
5665
5666 match(Set res (CompareAndExchangeS mem (Binary oldval newval)));
5667
5668 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST * 6);
5669
5670 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5671
5672 format %{
5673 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeSAcq"
5674 %}
5675
5676 ins_encode %{
5677 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5678 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
5679 /*result_as_bool*/ false, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5680 %}
5681
5682 ins_pipe(pipe_slow);
5683 %}
5684
5685 instruct compareAndExchangeIAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5686 %{
5687 predicate(needs_acquiring_load_reserved(n));
5688
5689 match(Set res (CompareAndExchangeI mem (Binary oldval newval)));
5690
5691 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST);
5692
5693 effect(TEMP_DEF res);
5694
5695 format %{
5696 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeIAcq"
5697 %}
5698
5699 ins_encode %{
5700 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
5701 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
5702 %}
5703
5704 ins_pipe(pipe_slow);
5705 %}
5706
5707 instruct compareAndExchangeLAcq(iRegLNoSp res, indirect mem, iRegL oldval, iRegL newval)
5708 %{
5709 predicate(needs_acquiring_load_reserved(n));
5710
5711 match(Set res (CompareAndExchangeL mem (Binary oldval newval)));
5712
5713 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST);
5714
5715 effect(TEMP_DEF res);
5716
5717 format %{
5718 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (long, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeLAcq"
5719 %}
5720
5721 ins_encode %{
5722 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5723 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
5724 %}
5725
5726 ins_pipe(pipe_slow);
5727 %}
5728
5729 instruct compareAndExchangeNAcq(iRegNNoSp res, indirect mem, iRegN oldval, iRegN newval)
5730 %{
5731 predicate(needs_acquiring_load_reserved(n) && n->as_LoadStore()->barrier_data() == 0);
5732
5733 match(Set res (CompareAndExchangeN mem (Binary oldval newval)));
5734
5735 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST);
5736
5737 effect(TEMP_DEF res);
5738
5739 format %{
5740 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeNAcq"
5741 %}
5742
5743 ins_encode %{
5744 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
5745 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
5746 %}
5747
5748 ins_pipe(pipe_slow);
5749 %}
5750
5751 instruct compareAndExchangePAcq(iRegPNoSp res, indirect mem, iRegP oldval, iRegP newval)
5752 %{
5753 predicate(needs_acquiring_load_reserved(n) && (n->as_LoadStore()->barrier_data() == 0));
5754
5755 match(Set res (CompareAndExchangeP mem (Binary oldval newval)));
5756
5757 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST);
5758
5759 effect(TEMP_DEF res);
5760
5761 format %{
5762 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (ptr, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangePAcq"
5763 %}
5764
5765 ins_encode %{
5766 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5767 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
5768 %}
5769
5770 ins_pipe(pipe_slow);
5771 %}
5772
5773 instruct weakCompareAndSwapB(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5774 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5775 %{
5776 match(Set res (WeakCompareAndSwapB mem (Binary oldval newval)));
5777
5778 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 6);
5779
5780 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5781
5782 format %{
5783 "weak_cmpxchg $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5784 "# $res == 1 when success, #@weakCompareAndSwapB"
5785 %}
5786
5787 ins_encode %{
5788 __ weak_cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5789 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
5790 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5791 %}
5792
5793 ins_pipe(pipe_slow);
5794 %}
5795
5796 instruct weakCompareAndSwapS(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5797 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5798 %{
5799 match(Set res (WeakCompareAndSwapS mem (Binary oldval newval)));
5800
5801 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 7);
5802
5803 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5804
5805 format %{
5806 "weak_cmpxchg $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5807 "# $res == 1 when success, #@weakCompareAndSwapS"
5808 %}
5809
5810 ins_encode %{
5811 __ weak_cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5812 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
5813 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5814 %}
5815
5816 ins_pipe(pipe_slow);
5817 %}
5818
5819 instruct weakCompareAndSwapI(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5820 %{
5821 match(Set res (WeakCompareAndSwapI mem (Binary oldval newval)));
5822
5823 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 2);
5824
5825 format %{
5826 "weak_cmpxchg $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5827 "# $res == 1 when success, #@weakCompareAndSwapI"
5828 %}
5829
5830 ins_encode %{
5831 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
5832 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5833 %}
5834
5835 ins_pipe(pipe_slow);
5836 %}
5837
5838 instruct weakCompareAndSwapL(iRegINoSp res, indirect mem, iRegL oldval, iRegL newval)
5839 %{
5840 match(Set res (WeakCompareAndSwapL mem (Binary oldval newval)));
5841
5842 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 2);
5843
5844 format %{
5845 "weak_cmpxchg $mem, $oldval, $newval\t# (long, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5846 "# $res == 1 when success, #@weakCompareAndSwapL"
5847 %}
5848
5849 ins_encode %{
5850 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5851 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5852 %}
5853
5854 ins_pipe(pipe_slow);
5855 %}
5856
5857 instruct weakCompareAndSwapN(iRegINoSp res, indirect mem, iRegN oldval, iRegN newval)
5858 %{
5859 predicate(n->as_LoadStore()->barrier_data() == 0);
5860 match(Set res (WeakCompareAndSwapN mem (Binary oldval newval)));
5861
5862 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 4);
5863
5864 format %{
5865 "weak_cmpxchg $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5866 "# $res == 1 when success, #@weakCompareAndSwapN"
5867 %}
5868
5869 ins_encode %{
5870 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
5871 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5872 %}
5873
5874 ins_pipe(pipe_slow);
5875 %}
5876
5877 instruct weakCompareAndSwapP(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval)
5878 %{
5879 predicate(n->as_LoadStore()->barrier_data() == 0);
5880 match(Set res (WeakCompareAndSwapP mem (Binary oldval newval)));
5881
5882 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 2);
5883
5884 format %{
5885 "weak_cmpxchg $mem, $oldval, $newval\t# (ptr, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5886 "# $res == 1 when success, #@weakCompareAndSwapP"
5887 %}
5888
5889 ins_encode %{
5890 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5891 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5892 %}
5893
5894 ins_pipe(pipe_slow);
5895 %}
5896
5897 instruct weakCompareAndSwapBAcq(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5898 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5899 %{
5900 predicate(needs_acquiring_load_reserved(n));
5901
5902 match(Set res (WeakCompareAndSwapB mem (Binary oldval newval)));
5903
5904 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 6);
5905
5906 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5907
5908 format %{
5909 "weak_cmpxchg_acq $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5910 "# $res == 1 when success, #@weakCompareAndSwapBAcq"
5911 %}
5912
5913 ins_encode %{
5914 __ weak_cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5915 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
5916 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5917 %}
5918
5919 ins_pipe(pipe_slow);
5920 %}
5921
5922 instruct weakCompareAndSwapSAcq(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5923 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5924 %{
5925 predicate(needs_acquiring_load_reserved(n));
5926
5927 match(Set res (WeakCompareAndSwapS mem (Binary oldval newval)));
5928
5929 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 7);
5930
5931 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5932
5933 format %{
5934 "weak_cmpxchg_acq $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5935 "# $res == 1 when success, #@weakCompareAndSwapSAcq"
5936 %}
5937
5938 ins_encode %{
5939 __ weak_cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5940 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
5941 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5942 %}
5943
5944 ins_pipe(pipe_slow);
5945 %}
5946
5947 instruct weakCompareAndSwapIAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5948 %{
5949 predicate(needs_acquiring_load_reserved(n));
5950
5951 match(Set res (WeakCompareAndSwapI mem (Binary oldval newval)));
5952
5953 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 2);
5954
5955 format %{
5956 "weak_cmpxchg_acq $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5957 "# $res == 1 when success, #@weakCompareAndSwapIAcq"
5958 %}
5959
5960 ins_encode %{
5961 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
5962 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
5963 %}
5964
5965 ins_pipe(pipe_slow);
5966 %}
5967
5968 instruct weakCompareAndSwapLAcq(iRegINoSp res, indirect mem, iRegL oldval, iRegL newval)
5969 %{
5970 predicate(needs_acquiring_load_reserved(n));
5971
5972 match(Set res (WeakCompareAndSwapL mem (Binary oldval newval)));
5973
5974 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 2);
5975
5976 format %{
5977 "weak_cmpxchg_acq $mem, $oldval, $newval\t# (long, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5978 "# $res == 1 when success, #@weakCompareAndSwapLAcq"
5979 %}
5980
5981 ins_encode %{
5982 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5983 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
5984 %}
5985
5986 ins_pipe(pipe_slow);
5987 %}
5988
5989 instruct weakCompareAndSwapNAcq(iRegINoSp res, indirect mem, iRegN oldval, iRegN newval)
5990 %{
5991 predicate(needs_acquiring_load_reserved(n) && n->as_LoadStore()->barrier_data() == 0);
5992
5993 match(Set res (WeakCompareAndSwapN mem (Binary oldval newval)));
5994
5995 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 4);
5996
5997 format %{
5998 "weak_cmpxchg_acq $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5999 "# $res == 1 when success, #@weakCompareAndSwapNAcq"
6000 %}
6001
6002 ins_encode %{
6003 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
6004 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
6005 %}
6006
6007 ins_pipe(pipe_slow);
6008 %}
6009
6010 instruct weakCompareAndSwapPAcq(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval)
6011 %{
6012 predicate(needs_acquiring_load_reserved(n) && (n->as_LoadStore()->barrier_data() == 0));
6013
6014 match(Set res (WeakCompareAndSwapP mem (Binary oldval newval)));
6015
6016 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 2);
6017
6018 format %{
6019 "weak_cmpxchg_acq $mem, $oldval, $newval\t# (ptr, weak) if $mem == $oldval then $mem <-- $newval\n\t"
6020 "\t# $res == 1 when success, #@weakCompareAndSwapPAcq"
6021 %}
6022
6023 ins_encode %{
6024 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
6025 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
6026 %}
6027
6028 ins_pipe(pipe_slow);
6029 %}
6030
6031 instruct get_and_setI(indirect mem, iRegI newv, iRegINoSp prev)
6032 %{
6033 match(Set prev (GetAndSetI mem newv));
6034
6035 ins_cost(ALU_COST);
6036
6037 format %{ "atomic_xchgw $prev, $newv, [$mem]\t#@get_and_setI" %}
6038
6039 ins_encode %{
6040 __ atomic_xchgw($prev$$Register, $newv$$Register, as_Register($mem$$base));
6041 %}
6042
6043 ins_pipe(pipe_serial);
6044 %}
6045
6046 instruct get_and_setL(indirect mem, iRegL newv, iRegLNoSp prev)
6047 %{
6048 match(Set prev (GetAndSetL mem newv));
6049
6050 ins_cost(ALU_COST);
6051
6052 format %{ "atomic_xchg $prev, $newv, [$mem]\t#@get_and_setL" %}
6053
6054 ins_encode %{
6055 __ atomic_xchg($prev$$Register, $newv$$Register, as_Register($mem$$base));
6056 %}
6057
6058 ins_pipe(pipe_serial);
6059 %}
6060
6061 instruct get_and_setN(indirect mem, iRegN newv, iRegINoSp prev)
6062 %{
6063 predicate(n->as_LoadStore()->barrier_data() == 0);
6064
6065 match(Set prev (GetAndSetN mem newv));
6066
6067 ins_cost(ALU_COST);
6068
6069 format %{ "atomic_xchgwu $prev, $newv, [$mem]\t#@get_and_setN" %}
6070
6071 ins_encode %{
6072 __ atomic_xchgwu($prev$$Register, $newv$$Register, as_Register($mem$$base));
6073 %}
6074
6075 ins_pipe(pipe_serial);
6076 %}
6077
6078 instruct get_and_setP(indirect mem, iRegP newv, iRegPNoSp prev)
6079 %{
6080 predicate(n->as_LoadStore()->barrier_data() == 0);
6081 match(Set prev (GetAndSetP mem newv));
6082
6083 ins_cost(ALU_COST);
6084
6085 format %{ "atomic_xchg $prev, $newv, [$mem]\t#@get_and_setP" %}
6086
6087 ins_encode %{
6088 __ atomic_xchg($prev$$Register, $newv$$Register, as_Register($mem$$base));
6089 %}
6090
6091 ins_pipe(pipe_serial);
6092 %}
6093
6094 instruct get_and_setIAcq(indirect mem, iRegI newv, iRegINoSp prev)
6095 %{
6096 predicate(needs_acquiring_load_reserved(n));
6097
6098 match(Set prev (GetAndSetI mem newv));
6099
6100 ins_cost(ALU_COST);
6101
6102 format %{ "atomic_xchgw_acq $prev, $newv, [$mem]\t#@get_and_setIAcq" %}
6103
6104 ins_encode %{
6105 __ atomic_xchgalw($prev$$Register, $newv$$Register, as_Register($mem$$base));
6106 %}
6107
6108 ins_pipe(pipe_serial);
6109 %}
6110
6111 instruct get_and_setLAcq(indirect mem, iRegL newv, iRegLNoSp prev)
6112 %{
6113 predicate(needs_acquiring_load_reserved(n));
6114
6115 match(Set prev (GetAndSetL mem newv));
6116
6117 ins_cost(ALU_COST);
6118
6119 format %{ "atomic_xchg_acq $prev, $newv, [$mem]\t#@get_and_setLAcq" %}
6120
6121 ins_encode %{
6122 __ atomic_xchgal($prev$$Register, $newv$$Register, as_Register($mem$$base));
6123 %}
6124
6125 ins_pipe(pipe_serial);
6126 %}
6127
6128 instruct get_and_setNAcq(indirect mem, iRegN newv, iRegINoSp prev)
6129 %{
6130 predicate(needs_acquiring_load_reserved(n) && n->as_LoadStore()->barrier_data() == 0);
6131
6132 match(Set prev (GetAndSetN mem newv));
6133
6134 ins_cost(ALU_COST);
6135
6136 format %{ "atomic_xchgwu_acq $prev, $newv, [$mem]\t#@get_and_setNAcq" %}
6137
6138 ins_encode %{
6139 __ atomic_xchgalwu($prev$$Register, $newv$$Register, as_Register($mem$$base));
6140 %}
6141
6142 ins_pipe(pipe_serial);
6143 %}
6144
6145 instruct get_and_setPAcq(indirect mem, iRegP newv, iRegPNoSp prev)
6146 %{
6147 predicate(needs_acquiring_load_reserved(n) && (n->as_LoadStore()->barrier_data() == 0));
6148
6149 match(Set prev (GetAndSetP mem newv));
6150
6151 ins_cost(ALU_COST);
6152
6153 format %{ "atomic_xchg_acq $prev, $newv, [$mem]\t#@get_and_setPAcq" %}
6154
6155 ins_encode %{
6156 __ atomic_xchgal($prev$$Register, $newv$$Register, as_Register($mem$$base));
6157 %}
6158
6159 ins_pipe(pipe_serial);
6160 %}
6161
6162 instruct get_and_addL(indirect mem, iRegLNoSp newval, iRegL incr)
6163 %{
6164 match(Set newval (GetAndAddL mem incr));
6165
6166 ins_cost(ALU_COST);
6167
6168 format %{ "get_and_addL $newval, [$mem], $incr\t#@get_and_addL" %}
6169
6170 ins_encode %{
6171 __ atomic_add($newval$$Register, $incr$$Register, as_Register($mem$$base));
6172 %}
6173
6174 ins_pipe(pipe_serial);
6175 %}
6176
6177 instruct get_and_addL_no_res(indirect mem, Universe dummy, iRegL incr)
6178 %{
6179 predicate(n->as_LoadStore()->result_not_used());
6180
6181 match(Set dummy (GetAndAddL mem incr));
6182
6183 ins_cost(ALU_COST);
6184
6185 format %{ "get_and_addL [$mem], $incr\t#@get_and_addL_no_res" %}
6186
6187 ins_encode %{
6188 __ atomic_add(noreg, $incr$$Register, as_Register($mem$$base));
6189 %}
6190
6191 ins_pipe(pipe_serial);
6192 %}
6193
6194 instruct get_and_addLi(indirect mem, iRegLNoSp newval, immLAdd incr)
6195 %{
6196 match(Set newval (GetAndAddL mem incr));
6197
6198 ins_cost(ALU_COST);
6199
6200 format %{ "get_and_addL $newval, [$mem], $incr\t#@get_and_addLi" %}
6201
6202 ins_encode %{
6203 __ atomic_add($newval$$Register, $incr$$constant, as_Register($mem$$base));
6204 %}
6205
6206 ins_pipe(pipe_serial);
6207 %}
6208
6209 instruct get_and_addLi_no_res(indirect mem, Universe dummy, immLAdd incr)
6210 %{
6211 predicate(n->as_LoadStore()->result_not_used());
6212
6213 match(Set dummy (GetAndAddL mem incr));
6214
6215 ins_cost(ALU_COST);
6216
6217 format %{ "get_and_addL [$mem], $incr\t#@get_and_addLi_no_res" %}
6218
6219 ins_encode %{
6220 __ atomic_add(noreg, $incr$$constant, as_Register($mem$$base));
6221 %}
6222
6223 ins_pipe(pipe_serial);
6224 %}
6225
6226 instruct get_and_addI(indirect mem, iRegINoSp newval, iRegIorL2I incr)
6227 %{
6228 match(Set newval (GetAndAddI mem incr));
6229
6230 ins_cost(ALU_COST);
6231
6232 format %{ "get_and_addI $newval, [$mem], $incr\t#@get_and_addI" %}
6233
6234 ins_encode %{
6235 __ atomic_addw($newval$$Register, $incr$$Register, as_Register($mem$$base));
6236 %}
6237
6238 ins_pipe(pipe_serial);
6239 %}
6240
6241 instruct get_and_addI_no_res(indirect mem, Universe dummy, iRegIorL2I incr)
6242 %{
6243 predicate(n->as_LoadStore()->result_not_used());
6244
6245 match(Set dummy (GetAndAddI mem incr));
6246
6247 ins_cost(ALU_COST);
6248
6249 format %{ "get_and_addI [$mem], $incr\t#@get_and_addI_no_res" %}
6250
6251 ins_encode %{
6252 __ atomic_addw(noreg, $incr$$Register, as_Register($mem$$base));
6253 %}
6254
6255 ins_pipe(pipe_serial);
6256 %}
6257
6258 instruct get_and_addIi(indirect mem, iRegINoSp newval, immIAdd incr)
6259 %{
6260 match(Set newval (GetAndAddI mem incr));
6261
6262 ins_cost(ALU_COST);
6263
6264 format %{ "get_and_addI $newval, [$mem], $incr\t#@get_and_addIi" %}
6265
6266 ins_encode %{
6267 __ atomic_addw($newval$$Register, $incr$$constant, as_Register($mem$$base));
6268 %}
6269
6270 ins_pipe(pipe_serial);
6271 %}
6272
6273 instruct get_and_addIi_no_res(indirect mem, Universe dummy, immIAdd incr)
6274 %{
6275 predicate(n->as_LoadStore()->result_not_used());
6276
6277 match(Set dummy (GetAndAddI mem incr));
6278
6279 ins_cost(ALU_COST);
6280
6281 format %{ "get_and_addI [$mem], $incr\t#@get_and_addIi_no_res" %}
6282
6283 ins_encode %{
6284 __ atomic_addw(noreg, $incr$$constant, as_Register($mem$$base));
6285 %}
6286
6287 ins_pipe(pipe_serial);
6288 %}
6289
6290 instruct get_and_addLAcq(indirect mem, iRegLNoSp newval, iRegL incr)
6291 %{
6292 predicate(needs_acquiring_load_reserved(n));
6293
6294 match(Set newval (GetAndAddL mem incr));
6295
6296 ins_cost(ALU_COST);
6297
6298 format %{ "get_and_addL_acq $newval, [$mem], $incr\t#@get_and_addLAcq" %}
6299
6300 ins_encode %{
6301 __ atomic_addal($newval$$Register, $incr$$Register, as_Register($mem$$base));
6302 %}
6303
6304 ins_pipe(pipe_serial);
6305 %}
6306
6307 instruct get_and_addL_no_resAcq(indirect mem, Universe dummy, iRegL incr) %{
6308 predicate(n->as_LoadStore()->result_not_used() && needs_acquiring_load_reserved(n));
6309
6310 match(Set dummy (GetAndAddL mem incr));
6311
6312 ins_cost(ALU_COST);
6313
6314 format %{ "get_and_addL_acq [$mem], $incr\t#@get_and_addL_no_resAcq" %}
6315
6316 ins_encode %{
6317 __ atomic_addal(noreg, $incr$$Register, as_Register($mem$$base));
6318 %}
6319
6320 ins_pipe(pipe_serial);
6321 %}
6322
6323 instruct get_and_addLiAcq(indirect mem, iRegLNoSp newval, immLAdd incr)
6324 %{
6325 predicate(needs_acquiring_load_reserved(n));
6326
6327 match(Set newval (GetAndAddL mem incr));
6328
6329 ins_cost(ALU_COST);
6330
6331 format %{ "get_and_addL_acq $newval, [$mem], $incr\t#@get_and_addLiAcq" %}
6332
6333 ins_encode %{
6334 __ atomic_addal($newval$$Register, $incr$$constant, as_Register($mem$$base));
6335 %}
6336
6337 ins_pipe(pipe_serial);
6338 %}
6339
6340 instruct get_and_addLi_no_resAcq(indirect mem, Universe dummy, immLAdd incr)
6341 %{
6342 predicate(n->as_LoadStore()->result_not_used() && needs_acquiring_load_reserved(n));
6343
6344 match(Set dummy (GetAndAddL mem incr));
6345
6346 ins_cost(ALU_COST);
6347
6348 format %{ "get_and_addL_acq [$mem], $incr\t#@get_and_addLi_no_resAcq" %}
6349
6350 ins_encode %{
6351 __ atomic_addal(noreg, $incr$$constant, as_Register($mem$$base));
6352 %}
6353
6354 ins_pipe(pipe_serial);
6355 %}
6356
6357 instruct get_and_addIAcq(indirect mem, iRegINoSp newval, iRegIorL2I incr)
6358 %{
6359 predicate(needs_acquiring_load_reserved(n));
6360
6361 match(Set newval (GetAndAddI mem incr));
6362
6363 ins_cost(ALU_COST);
6364
6365 format %{ "get_and_addI_acq $newval, [$mem], $incr\t#@get_and_addIAcq" %}
6366
6367 ins_encode %{
6368 __ atomic_addalw($newval$$Register, $incr$$Register, as_Register($mem$$base));
6369 %}
6370
6371 ins_pipe(pipe_serial);
6372 %}
6373
6374 instruct get_and_addI_no_resAcq(indirect mem, Universe dummy, iRegIorL2I incr)
6375 %{
6376 predicate(n->as_LoadStore()->result_not_used() && needs_acquiring_load_reserved(n));
6377
6378 match(Set dummy (GetAndAddI mem incr));
6379
6380 ins_cost(ALU_COST);
6381
6382 format %{ "get_and_addI_acq [$mem], $incr\t#@get_and_addI_no_resAcq" %}
6383
6384 ins_encode %{
6385 __ atomic_addalw(noreg, $incr$$Register, as_Register($mem$$base));
6386 %}
6387
6388 ins_pipe(pipe_serial);
6389 %}
6390
6391 instruct get_and_addIiAcq(indirect mem, iRegINoSp newval, immIAdd incr)
6392 %{
6393 predicate(needs_acquiring_load_reserved(n));
6394
6395 match(Set newval (GetAndAddI mem incr));
6396
6397 ins_cost(ALU_COST);
6398
6399 format %{ "get_and_addI_acq $newval, [$mem], $incr\t#@get_and_addIiAcq" %}
6400
6401 ins_encode %{
6402 __ atomic_addalw($newval$$Register, $incr$$constant, as_Register($mem$$base));
6403 %}
6404
6405 ins_pipe(pipe_serial);
6406 %}
6407
6408 instruct get_and_addIi_no_resAcq(indirect mem, Universe dummy, immIAdd incr)
6409 %{
6410 predicate(n->as_LoadStore()->result_not_used() && needs_acquiring_load_reserved(n));
6411
6412 match(Set dummy (GetAndAddI mem incr));
6413
6414 ins_cost(ALU_COST);
6415
6416 format %{ "get_and_addI_acq [$mem], $incr\t#@get_and_addIi_no_resAcq" %}
6417
6418 ins_encode %{
6419 __ atomic_addalw(noreg, $incr$$constant, as_Register($mem$$base));
6420 %}
6421
6422 ins_pipe(pipe_serial);
6423 %}
6424
6425 // ============================================================================
6426 // Arithmetic Instructions
6427 //
6428
6429 // Integer Addition
6430
6431 // TODO
6432 // these currently employ operations which do not set CR and hence are
6433 // not flagged as killing CR but we would like to isolate the cases
6434 // where we want to set flags from those where we don't. need to work
6435 // out how to do that.
6436 instruct addI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6437 match(Set dst (AddI src1 src2));
6438
6439 ins_cost(ALU_COST);
6440 format %{ "addw $dst, $src1, $src2\t#@addI_reg_reg" %}
6441
6442 ins_encode %{
6443 __ addw(as_Register($dst$$reg),
6444 as_Register($src1$$reg),
6445 as_Register($src2$$reg));
6446 %}
6447
6448 ins_pipe(ialu_reg_reg);
6449 %}
6450
6451 instruct addI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immIAdd src2) %{
6452 match(Set dst (AddI src1 src2));
6453
6454 ins_cost(ALU_COST);
6455 format %{ "addiw $dst, $src1, $src2\t#@addI_reg_imm" %}
6456
6457 ins_encode %{
6458 __ addiw(as_Register($dst$$reg),
6459 as_Register($src1$$reg),
6460 $src2$$constant);
6461 %}
6462
6463 ins_pipe(ialu_reg_imm);
6464 %}
6465
6466 instruct addI_reg_imm_l2i(iRegINoSp dst, iRegL src1, immIAdd src2) %{
6467 match(Set dst (AddI (ConvL2I src1) src2));
6468
6469 ins_cost(ALU_COST);
6470 format %{ "addiw $dst, $src1, $src2\t#@addI_reg_imm_l2i" %}
6471
6472 ins_encode %{
6473 __ addiw(as_Register($dst$$reg),
6474 as_Register($src1$$reg),
6475 $src2$$constant);
6476 %}
6477
6478 ins_pipe(ialu_reg_imm);
6479 %}
6480
6481 // Pointer Addition
6482 instruct addP_reg_reg(iRegPNoSp dst, iRegP src1, iRegL src2) %{
6483 match(Set dst (AddP src1 src2));
6484
6485 ins_cost(ALU_COST);
6486 format %{ "add $dst, $src1, $src2\t# ptr, #@addP_reg_reg" %}
6487
6488 ins_encode %{
6489 __ add(as_Register($dst$$reg),
6490 as_Register($src1$$reg),
6491 as_Register($src2$$reg));
6492 %}
6493
6494 ins_pipe(ialu_reg_reg);
6495 %}
6496
6497 // If we shift more than 32 bits, we need not convert I2L.
6498 instruct lShiftL_regI_immGE32(iRegLNoSp dst, iRegI src, uimmI6_ge32 scale) %{
6499 match(Set dst (LShiftL (ConvI2L src) scale));
6500 ins_cost(ALU_COST);
6501 format %{ "slli $dst, $src, $scale & 63\t#@lShiftL_regI_immGE32" %}
6502
6503 ins_encode %{
6504 __ slli(as_Register($dst$$reg), as_Register($src$$reg), $scale$$constant & 63);
6505 %}
6506
6507 ins_pipe(ialu_reg_shift);
6508 %}
6509
6510 // Pointer Immediate Addition
6511 // n.b. this needs to be more expensive than using an indirect memory
6512 // operand
6513 instruct addP_reg_imm(iRegPNoSp dst, iRegP src1, immLAdd src2) %{
6514 match(Set dst (AddP src1 src2));
6515 ins_cost(ALU_COST);
6516 format %{ "addi $dst, $src1, $src2\t# ptr, #@addP_reg_imm" %}
6517
6518 ins_encode %{
6519 __ addi(as_Register($dst$$reg),
6520 as_Register($src1$$reg),
6521 $src2$$constant);
6522 %}
6523
6524 ins_pipe(ialu_reg_imm);
6525 %}
6526
6527 // Long Addition
6528 instruct addL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
6529 match(Set dst (AddL src1 src2));
6530 ins_cost(ALU_COST);
6531 format %{ "add $dst, $src1, $src2\t#@addL_reg_reg" %}
6532
6533 ins_encode %{
6534 __ add(as_Register($dst$$reg),
6535 as_Register($src1$$reg),
6536 as_Register($src2$$reg));
6537 %}
6538
6539 ins_pipe(ialu_reg_reg);
6540 %}
6541
6542 // No constant pool entries requiredLong Immediate Addition.
6543 instruct addL_reg_imm(iRegLNoSp dst, iRegL src1, immLAdd src2) %{
6544 match(Set dst (AddL src1 src2));
6545 ins_cost(ALU_COST);
6546 format %{ "addi $dst, $src1, $src2\t#@addL_reg_imm" %}
6547
6548 ins_encode %{
6549 // src2 is imm, so actually call the addi
6550 __ addi(as_Register($dst$$reg),
6551 as_Register($src1$$reg),
6552 $src2$$constant);
6553 %}
6554
6555 ins_pipe(ialu_reg_imm);
6556 %}
6557
6558 // Integer Subtraction
6559 instruct subI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6560 match(Set dst (SubI src1 src2));
6561
6562 ins_cost(ALU_COST);
6563 format %{ "subw $dst, $src1, $src2\t#@subI_reg_reg" %}
6564
6565 ins_encode %{
6566 __ subw(as_Register($dst$$reg),
6567 as_Register($src1$$reg),
6568 as_Register($src2$$reg));
6569 %}
6570
6571 ins_pipe(ialu_reg_reg);
6572 %}
6573
6574 // Immediate Subtraction
6575 instruct subI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immISub src2) %{
6576 match(Set dst (SubI src1 src2));
6577
6578 ins_cost(ALU_COST);
6579 format %{ "addiw $dst, $src1, -$src2\t#@subI_reg_imm" %}
6580
6581 ins_encode %{
6582 // src2 is imm, so actually call the addiw
6583 __ subiw(as_Register($dst$$reg),
6584 as_Register($src1$$reg),
6585 $src2$$constant);
6586 %}
6587
6588 ins_pipe(ialu_reg_imm);
6589 %}
6590
6591 // Long Subtraction
6592 instruct subL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
6593 match(Set dst (SubL src1 src2));
6594 ins_cost(ALU_COST);
6595 format %{ "sub $dst, $src1, $src2\t#@subL_reg_reg" %}
6596
6597 ins_encode %{
6598 __ sub(as_Register($dst$$reg),
6599 as_Register($src1$$reg),
6600 as_Register($src2$$reg));
6601 %}
6602
6603 ins_pipe(ialu_reg_reg);
6604 %}
6605
6606 // No constant pool entries requiredLong Immediate Subtraction.
6607 instruct subL_reg_imm(iRegLNoSp dst, iRegL src1, immLSub src2) %{
6608 match(Set dst (SubL src1 src2));
6609 ins_cost(ALU_COST);
6610 format %{ "addi $dst, $src1, -$src2\t#@subL_reg_imm" %}
6611
6612 ins_encode %{
6613 // src2 is imm, so actually call the addi
6614 __ subi(as_Register($dst$$reg),
6615 as_Register($src1$$reg),
6616 $src2$$constant);
6617 %}
6618
6619 ins_pipe(ialu_reg_imm);
6620 %}
6621
6622 // Integer Negation (special case for sub)
6623
6624 instruct negI_reg(iRegINoSp dst, iRegIorL2I src, immI0 zero) %{
6625 match(Set dst (SubI zero src));
6626 ins_cost(ALU_COST);
6627 format %{ "subw $dst, x0, $src\t# int, #@negI_reg" %}
6628
6629 ins_encode %{
6630 // actually call the subw
6631 __ negw(as_Register($dst$$reg),
6632 as_Register($src$$reg));
6633 %}
6634
6635 ins_pipe(ialu_reg);
6636 %}
6637
6638 // Long Negation
6639
6640 instruct negL_reg(iRegLNoSp dst, iRegL src, immL0 zero) %{
6641 match(Set dst (SubL zero src));
6642 ins_cost(ALU_COST);
6643 format %{ "sub $dst, x0, $src\t# long, #@negL_reg" %}
6644
6645 ins_encode %{
6646 // actually call the sub
6647 __ neg(as_Register($dst$$reg),
6648 as_Register($src$$reg));
6649 %}
6650
6651 ins_pipe(ialu_reg);
6652 %}
6653
6654 // Integer Multiply
6655
6656 instruct mulI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6657 match(Set dst (MulI src1 src2));
6658 ins_cost(IMUL_COST);
6659 format %{ "mulw $dst, $src1, $src2\t#@mulI" %}
6660
6661 //this means 2 word multi, and no sign extend to 64 bits
6662 ins_encode %{
6663 // riscv64 mulw will sign-extension to high 32 bits in dst reg
6664 __ mulw(as_Register($dst$$reg),
6665 as_Register($src1$$reg),
6666 as_Register($src2$$reg));
6667 %}
6668
6669 ins_pipe(imul_reg_reg);
6670 %}
6671
6672 // Long Multiply
6673
6674 instruct mulL(iRegLNoSp dst, iRegL src1, iRegL src2) %{
6675 match(Set dst (MulL src1 src2));
6676 ins_cost(IMUL_COST);
6677 format %{ "mul $dst, $src1, $src2\t#@mulL" %}
6678
6679 ins_encode %{
6680 __ mul(as_Register($dst$$reg),
6681 as_Register($src1$$reg),
6682 as_Register($src2$$reg));
6683 %}
6684
6685 ins_pipe(lmul_reg_reg);
6686 %}
6687
6688 instruct mulHiL_rReg(iRegLNoSp dst, iRegL src1, iRegL src2)
6689 %{
6690 match(Set dst (MulHiL src1 src2));
6691 ins_cost(IMUL_COST);
6692 format %{ "mulh $dst, $src1, $src2\t# mulhi, #@mulHiL_rReg" %}
6693
6694 ins_encode %{
6695 __ mulh(as_Register($dst$$reg),
6696 as_Register($src1$$reg),
6697 as_Register($src2$$reg));
6698 %}
6699
6700 ins_pipe(lmul_reg_reg);
6701 %}
6702
6703 instruct umulHiL_rReg(iRegLNoSp dst, iRegL src1, iRegL src2)
6704 %{
6705 match(Set dst (UMulHiL src1 src2));
6706 ins_cost(IMUL_COST);
6707 format %{ "mulhu $dst, $src1, $src2\t# umulhi, #@umulHiL_rReg" %}
6708
6709 ins_encode %{
6710 __ mulhu(as_Register($dst$$reg),
6711 as_Register($src1$$reg),
6712 as_Register($src2$$reg));
6713 %}
6714
6715 ins_pipe(lmul_reg_reg);
6716 %}
6717
6718 // Integer Divide
6719
6720 instruct divI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6721 match(Set dst (DivI src1 src2));
6722 ins_cost(IDIVSI_COST);
6723 format %{ "divw $dst, $src1, $src2\t#@divI"%}
6724
6725 ins_encode %{
6726 __ divw(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg));
6727 %}
6728 ins_pipe(idiv_reg_reg);
6729 %}
6730
6731 instruct UdivI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6732 match(Set dst (UDivI src1 src2));
6733 ins_cost(IDIVSI_COST);
6734 format %{ "divuw $dst, $src1, $src2\t#@UdivI"%}
6735
6736 ins_encode %{
6737 __ divuw(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg));
6738 %}
6739 ins_pipe(idiv_reg_reg);
6740 %}
6741
6742 instruct signExtract(iRegINoSp dst, iRegIorL2I src1, immI_31 div1, immI_31 div2) %{
6743 match(Set dst (URShiftI (RShiftI src1 div1) div2));
6744 ins_cost(ALU_COST);
6745 format %{ "srliw $dst, $src1, $div1\t# int signExtract, #@signExtract" %}
6746
6747 ins_encode %{
6748 __ srliw(as_Register($dst$$reg), as_Register($src1$$reg), 31);
6749 %}
6750 ins_pipe(ialu_reg_shift);
6751 %}
6752
6753 // Long Divide
6754
6755 instruct divL(iRegLNoSp dst, iRegL src1, iRegL src2) %{
6756 match(Set dst (DivL src1 src2));
6757 ins_cost(IDIVDI_COST);
6758 format %{ "div $dst, $src1, $src2\t#@divL" %}
6759
6760 ins_encode %{
6761 __ div(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg));
6762 %}
6763 ins_pipe(ldiv_reg_reg);
6764 %}
6765
6766 instruct UdivL(iRegLNoSp dst, iRegL src1, iRegL src2) %{
6767 match(Set dst (UDivL src1 src2));
6768 ins_cost(IDIVDI_COST);
6769
6770 format %{ "divu $dst, $src1, $src2\t#@UdivL" %}
6771
6772 ins_encode %{
6773 __ divu(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg));
6774 %}
6775 ins_pipe(ldiv_reg_reg);
6776 %}
6777
6778 instruct signExtractL(iRegLNoSp dst, iRegL src1, immI_63 div1, immI_63 div2) %{
6779 match(Set dst (URShiftL (RShiftL src1 div1) div2));
6780 ins_cost(ALU_COST);
6781 format %{ "srli $dst, $src1, $div1\t# long signExtract, #@signExtractL" %}
6782
6783 ins_encode %{
6784 __ srli(as_Register($dst$$reg), as_Register($src1$$reg), 63);
6785 %}
6786 ins_pipe(ialu_reg_shift);
6787 %}
6788
6789 // Integer Remainder
6790
6791 instruct modI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6792 match(Set dst (ModI src1 src2));
6793 ins_cost(IDIVSI_COST);
6794 format %{ "remw $dst, $src1, $src2\t#@modI" %}
6795
6796 ins_encode %{
6797 __ remw(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg));
6798 %}
6799 ins_pipe(ialu_reg_reg);
6800 %}
6801
6802 instruct UmodI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6803 match(Set dst (UModI src1 src2));
6804 ins_cost(IDIVSI_COST);
6805 format %{ "remuw $dst, $src1, $src2\t#@UmodI" %}
6806
6807 ins_encode %{
6808 __ remuw(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg));
6809 %}
6810 ins_pipe(ialu_reg_reg);
6811 %}
6812
6813 // Long Remainder
6814
6815 instruct modL(iRegLNoSp dst, iRegL src1, iRegL src2) %{
6816 match(Set dst (ModL src1 src2));
6817 ins_cost(IDIVDI_COST);
6818 format %{ "rem $dst, $src1, $src2\t#@modL" %}
6819
6820 ins_encode %{
6821 __ rem(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg));
6822 %}
6823 ins_pipe(ialu_reg_reg);
6824 %}
6825
6826 instruct UmodL(iRegLNoSp dst, iRegL src1, iRegL src2) %{
6827 match(Set dst (UModL src1 src2));
6828 ins_cost(IDIVDI_COST);
6829 format %{ "remu $dst, $src1, $src2\t#@UmodL" %}
6830
6831 ins_encode %{
6832 __ remu(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg));
6833 %}
6834 ins_pipe(ialu_reg_reg);
6835 %}
6836
6837 // Integer Shifts
6838
6839 // Shift Left Register
6840 // Only the low 5 bits of src2 are considered for the shift amount, all other bits are ignored.
6841 instruct lShiftI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6842 match(Set dst (LShiftI src1 src2));
6843 ins_cost(ALU_COST);
6844 format %{ "sllw $dst, $src1, $src2\t#@lShiftI_reg_reg" %}
6845
6846 ins_encode %{
6847 __ sllw(as_Register($dst$$reg),
6848 as_Register($src1$$reg),
6849 as_Register($src2$$reg));
6850 %}
6851
6852 ins_pipe(ialu_reg_reg_vshift);
6853 %}
6854
6855 // Shift Left Immediate
6856 instruct lShiftI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immI src2) %{
6857 match(Set dst (LShiftI src1 src2));
6858 ins_cost(ALU_COST);
6859 format %{ "slliw $dst, $src1, ($src2 & 0x1f)\t#@lShiftI_reg_imm" %}
6860
6861 ins_encode %{
6862 // the shift amount is encoded in the lower
6863 // 5 bits of the I-immediate field for RV32I
6864 __ slliw(as_Register($dst$$reg),
6865 as_Register($src1$$reg),
6866 (unsigned) $src2$$constant & 0x1f);
6867 %}
6868
6869 ins_pipe(ialu_reg_shift);
6870 %}
6871
6872 // Shift Right Logical Register
6873 // Only the low 5 bits of src2 are considered for the shift amount, all other bits are ignored.
6874 instruct urShiftI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6875 match(Set dst (URShiftI src1 src2));
6876 ins_cost(ALU_COST);
6877 format %{ "srlw $dst, $src1, $src2\t#@urShiftI_reg_reg" %}
6878
6879 ins_encode %{
6880 __ srlw(as_Register($dst$$reg),
6881 as_Register($src1$$reg),
6882 as_Register($src2$$reg));
6883 %}
6884
6885 ins_pipe(ialu_reg_reg_vshift);
6886 %}
6887
6888 // Shift Right Logical Immediate
6889 instruct urShiftI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immI src2) %{
6890 match(Set dst (URShiftI src1 src2));
6891 ins_cost(ALU_COST);
6892 format %{ "srliw $dst, $src1, ($src2 & 0x1f)\t#@urShiftI_reg_imm" %}
6893
6894 ins_encode %{
6895 // the shift amount is encoded in the lower
6896 // 6 bits of the I-immediate field for RV64I
6897 __ srliw(as_Register($dst$$reg),
6898 as_Register($src1$$reg),
6899 (unsigned) $src2$$constant & 0x1f);
6900 %}
6901
6902 ins_pipe(ialu_reg_shift);
6903 %}
6904
6905 // Shift Right Arithmetic Register
6906 // Only the low 5 bits of src2 are considered for the shift amount, all other bits are ignored.
6907 instruct rShiftI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6908 match(Set dst (RShiftI src1 src2));
6909 ins_cost(ALU_COST);
6910 format %{ "sraw $dst, $src1, $src2\t#@rShiftI_reg_reg" %}
6911
6912 ins_encode %{
6913 // riscv will sign-ext dst high 32 bits
6914 __ sraw(as_Register($dst$$reg),
6915 as_Register($src1$$reg),
6916 as_Register($src2$$reg));
6917 %}
6918
6919 ins_pipe(ialu_reg_reg_vshift);
6920 %}
6921
6922 // Shift Right Arithmetic Immediate
6923 instruct rShiftI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immI src2) %{
6924 match(Set dst (RShiftI src1 src2));
6925 ins_cost(ALU_COST);
6926 format %{ "sraiw $dst, $src1, ($src2 & 0x1f)\t#@rShiftI_reg_imm" %}
6927
6928 ins_encode %{
6929 // riscv will sign-ext dst high 32 bits
6930 __ sraiw(as_Register($dst$$reg),
6931 as_Register($src1$$reg),
6932 (unsigned) $src2$$constant & 0x1f);
6933 %}
6934
6935 ins_pipe(ialu_reg_shift);
6936 %}
6937
6938 // Long Shifts
6939
6940 // Shift Left Register
6941 // Only the low 6 bits of src2 are considered for the shift amount, all other bits are ignored.
6942 instruct lShiftL_reg_reg(iRegLNoSp dst, iRegL src1, iRegIorL2I src2) %{
6943 match(Set dst (LShiftL src1 src2));
6944
6945 ins_cost(ALU_COST);
6946 format %{ "sll $dst, $src1, $src2\t#@lShiftL_reg_reg" %}
6947
6948 ins_encode %{
6949 __ sll(as_Register($dst$$reg),
6950 as_Register($src1$$reg),
6951 as_Register($src2$$reg));
6952 %}
6953
6954 ins_pipe(ialu_reg_reg_vshift);
6955 %}
6956
6957 // Shift Left Immediate
6958 instruct lShiftL_reg_imm(iRegLNoSp dst, iRegL src1, immI src2) %{
6959 match(Set dst (LShiftL src1 src2));
6960
6961 ins_cost(ALU_COST);
6962 format %{ "slli $dst, $src1, ($src2 & 0x3f)\t#@lShiftL_reg_imm" %}
6963
6964 ins_encode %{
6965 // the shift amount is encoded in the lower
6966 // 6 bits of the I-immediate field for RV64I
6967 __ slli(as_Register($dst$$reg),
6968 as_Register($src1$$reg),
6969 (unsigned) $src2$$constant & 0x3f);
6970 %}
6971
6972 ins_pipe(ialu_reg_shift);
6973 %}
6974
6975 // Shift Right Logical Register
6976 // Only the low 6 bits of src2 are considered for the shift amount, all other bits are ignored.
6977 instruct urShiftL_reg_reg(iRegLNoSp dst, iRegL src1, iRegIorL2I src2) %{
6978 match(Set dst (URShiftL src1 src2));
6979
6980 ins_cost(ALU_COST);
6981 format %{ "srl $dst, $src1, $src2\t#@urShiftL_reg_reg" %}
6982
6983 ins_encode %{
6984 __ srl(as_Register($dst$$reg),
6985 as_Register($src1$$reg),
6986 as_Register($src2$$reg));
6987 %}
6988
6989 ins_pipe(ialu_reg_reg_vshift);
6990 %}
6991
6992 // Shift Right Logical Immediate
6993 instruct urShiftL_reg_imm(iRegLNoSp dst, iRegL src1, immI src2) %{
6994 match(Set dst (URShiftL src1 src2));
6995
6996 ins_cost(ALU_COST);
6997 format %{ "srli $dst, $src1, ($src2 & 0x3f)\t#@urShiftL_reg_imm" %}
6998
6999 ins_encode %{
7000 // the shift amount is encoded in the lower
7001 // 6 bits of the I-immediate field for RV64I
7002 __ srli(as_Register($dst$$reg),
7003 as_Register($src1$$reg),
7004 (unsigned) $src2$$constant & 0x3f);
7005 %}
7006
7007 ins_pipe(ialu_reg_shift);
7008 %}
7009
7010 // A special-case pattern for card table stores.
7011 instruct urShiftP_reg_imm(iRegLNoSp dst, iRegP src1, immI src2) %{
7012 match(Set dst (URShiftL (CastP2X src1) src2));
7013
7014 ins_cost(ALU_COST);
7015 format %{ "srli $dst, p2x($src1), ($src2 & 0x3f)\t#@urShiftP_reg_imm" %}
7016
7017 ins_encode %{
7018 // the shift amount is encoded in the lower
7019 // 6 bits of the I-immediate field for RV64I
7020 __ srli(as_Register($dst$$reg),
7021 as_Register($src1$$reg),
7022 (unsigned) $src2$$constant & 0x3f);
7023 %}
7024
7025 ins_pipe(ialu_reg_shift);
7026 %}
7027
7028 // Shift Right Arithmetic Register
7029 // Only the low 6 bits of src2 are considered for the shift amount, all other bits are ignored.
7030 instruct rShiftL_reg_reg(iRegLNoSp dst, iRegL src1, iRegIorL2I src2) %{
7031 match(Set dst (RShiftL src1 src2));
7032
7033 ins_cost(ALU_COST);
7034 format %{ "sra $dst, $src1, $src2\t#@rShiftL_reg_reg" %}
7035
7036 ins_encode %{
7037 __ sra(as_Register($dst$$reg),
7038 as_Register($src1$$reg),
7039 as_Register($src2$$reg));
7040 %}
7041
7042 ins_pipe(ialu_reg_reg_vshift);
7043 %}
7044
7045 // Shift Right Arithmetic Immediate
7046 instruct rShiftL_reg_imm(iRegLNoSp dst, iRegL src1, immI src2) %{
7047 match(Set dst (RShiftL src1 src2));
7048
7049 ins_cost(ALU_COST);
7050 format %{ "srai $dst, $src1, ($src2 & 0x3f)\t#@rShiftL_reg_imm" %}
7051
7052 ins_encode %{
7053 // the shift amount is encoded in the lower
7054 // 6 bits of the I-immediate field for RV64I
7055 __ srai(as_Register($dst$$reg),
7056 as_Register($src1$$reg),
7057 (unsigned) $src2$$constant & 0x3f);
7058 %}
7059
7060 ins_pipe(ialu_reg_shift);
7061 %}
7062
7063 instruct regI_not_reg(iRegINoSp dst, iRegI src1, immI_M1 m1) %{
7064 match(Set dst (XorI src1 m1));
7065 ins_cost(ALU_COST);
7066 format %{ "xori $dst, $src1, -1\t#@regI_not_reg" %}
7067
7068 ins_encode %{
7069 __ xori(as_Register($dst$$reg), as_Register($src1$$reg), -1);
7070 %}
7071
7072 ins_pipe(ialu_reg_imm);
7073 %}
7074
7075 instruct regL_not_reg(iRegLNoSp dst, iRegL src1, immL_M1 m1) %{
7076 match(Set dst (XorL src1 m1));
7077 ins_cost(ALU_COST);
7078 format %{ "xori $dst, $src1, -1\t#@regL_not_reg" %}
7079
7080 ins_encode %{
7081 __ xori(as_Register($dst$$reg), as_Register($src1$$reg), -1);
7082 %}
7083
7084 ins_pipe(ialu_reg_imm);
7085 %}
7086
7087
7088 // ============================================================================
7089 // Floating Point Arithmetic Instructions
7090
7091 instruct addF_reg_reg(fRegF dst, fRegF src1, fRegF src2) %{
7092 match(Set dst (AddF src1 src2));
7093
7094 ins_cost(DEFAULT_COST * 5);
7095 format %{ "fadd.s $dst, $src1, $src2\t#@addF_reg_reg" %}
7096
7097 ins_encode %{
7098 __ fadd_s(as_FloatRegister($dst$$reg),
7099 as_FloatRegister($src1$$reg),
7100 as_FloatRegister($src2$$reg));
7101 %}
7102
7103 ins_pipe(fp_dop_reg_reg_s);
7104 %}
7105
7106 instruct addD_reg_reg(fRegD dst, fRegD src1, fRegD src2) %{
7107 match(Set dst (AddD src1 src2));
7108
7109 ins_cost(DEFAULT_COST * 5);
7110 format %{ "fadd.d $dst, $src1, $src2\t#@addD_reg_reg" %}
7111
7112 ins_encode %{
7113 __ fadd_d(as_FloatRegister($dst$$reg),
7114 as_FloatRegister($src1$$reg),
7115 as_FloatRegister($src2$$reg));
7116 %}
7117
7118 ins_pipe(fp_dop_reg_reg_d);
7119 %}
7120
7121 instruct subF_reg_reg(fRegF dst, fRegF src1, fRegF src2) %{
7122 match(Set dst (SubF src1 src2));
7123
7124 ins_cost(DEFAULT_COST * 5);
7125 format %{ "fsub.s $dst, $src1, $src2\t#@subF_reg_reg" %}
7126
7127 ins_encode %{
7128 __ fsub_s(as_FloatRegister($dst$$reg),
7129 as_FloatRegister($src1$$reg),
7130 as_FloatRegister($src2$$reg));
7131 %}
7132
7133 ins_pipe(fp_dop_reg_reg_s);
7134 %}
7135
7136 instruct subD_reg_reg(fRegD dst, fRegD src1, fRegD src2) %{
7137 match(Set dst (SubD src1 src2));
7138
7139 ins_cost(DEFAULT_COST * 5);
7140 format %{ "fsub.d $dst, $src1, $src2\t#@subD_reg_reg" %}
7141
7142 ins_encode %{
7143 __ fsub_d(as_FloatRegister($dst$$reg),
7144 as_FloatRegister($src1$$reg),
7145 as_FloatRegister($src2$$reg));
7146 %}
7147
7148 ins_pipe(fp_dop_reg_reg_d);
7149 %}
7150
7151 instruct mulF_reg_reg(fRegF dst, fRegF src1, fRegF src2) %{
7152 match(Set dst (MulF src1 src2));
7153
7154 ins_cost(FMUL_SINGLE_COST);
7155 format %{ "fmul.s $dst, $src1, $src2\t#@mulF_reg_reg" %}
7156
7157 ins_encode %{
7158 __ fmul_s(as_FloatRegister($dst$$reg),
7159 as_FloatRegister($src1$$reg),
7160 as_FloatRegister($src2$$reg));
7161 %}
7162
7163 ins_pipe(fp_dop_reg_reg_s);
7164 %}
7165
7166 instruct mulD_reg_reg(fRegD dst, fRegD src1, fRegD src2) %{
7167 match(Set dst (MulD src1 src2));
7168
7169 ins_cost(FMUL_DOUBLE_COST);
7170 format %{ "fmul.d $dst, $src1, $src2\t#@mulD_reg_reg" %}
7171
7172 ins_encode %{
7173 __ fmul_d(as_FloatRegister($dst$$reg),
7174 as_FloatRegister($src1$$reg),
7175 as_FloatRegister($src2$$reg));
7176 %}
7177
7178 ins_pipe(fp_dop_reg_reg_d);
7179 %}
7180
7181 // src1 * src2 + src3
7182 instruct maddF_reg_reg(fRegF dst, fRegF src1, fRegF src2, fRegF src3) %{
7183 match(Set dst (FmaF src3 (Binary src1 src2)));
7184
7185 ins_cost(FMUL_SINGLE_COST);
7186 format %{ "fmadd.s $dst, $src1, $src2, $src3\t#@maddF_reg_reg" %}
7187
7188 ins_encode %{
7189 assert(UseFMA, "Needs FMA instructions support.");
7190 __ fmadd_s(as_FloatRegister($dst$$reg),
7191 as_FloatRegister($src1$$reg),
7192 as_FloatRegister($src2$$reg),
7193 as_FloatRegister($src3$$reg));
7194 %}
7195
7196 ins_pipe(pipe_class_default);
7197 %}
7198
7199 // src1 * src2 + src3
7200 instruct maddD_reg_reg(fRegD dst, fRegD src1, fRegD src2, fRegD src3) %{
7201 match(Set dst (FmaD src3 (Binary src1 src2)));
7202
7203 ins_cost(FMUL_DOUBLE_COST);
7204 format %{ "fmadd.d $dst, $src1, $src2, $src3\t#@maddD_reg_reg" %}
7205
7206 ins_encode %{
7207 assert(UseFMA, "Needs FMA instructions support.");
7208 __ fmadd_d(as_FloatRegister($dst$$reg),
7209 as_FloatRegister($src1$$reg),
7210 as_FloatRegister($src2$$reg),
7211 as_FloatRegister($src3$$reg));
7212 %}
7213
7214 ins_pipe(pipe_class_default);
7215 %}
7216
7217 // src1 * src2 - src3
7218 instruct msubF_reg_reg(fRegF dst, fRegF src1, fRegF src2, fRegF src3) %{
7219 match(Set dst (FmaF (NegF src3) (Binary src1 src2)));
7220
7221 ins_cost(FMUL_SINGLE_COST);
7222 format %{ "fmsub.s $dst, $src1, $src2, $src3\t#@msubF_reg_reg" %}
7223
7224 ins_encode %{
7225 assert(UseFMA, "Needs FMA instructions support.");
7226 __ fmsub_s(as_FloatRegister($dst$$reg),
7227 as_FloatRegister($src1$$reg),
7228 as_FloatRegister($src2$$reg),
7229 as_FloatRegister($src3$$reg));
7230 %}
7231
7232 ins_pipe(pipe_class_default);
7233 %}
7234
7235 // src1 * src2 - src3
7236 instruct msubD_reg_reg(fRegD dst, fRegD src1, fRegD src2, fRegD src3) %{
7237 match(Set dst (FmaD (NegD src3) (Binary src1 src2)));
7238
7239 ins_cost(FMUL_DOUBLE_COST);
7240 format %{ "fmsub.d $dst, $src1, $src2, $src3\t#@msubD_reg_reg" %}
7241
7242 ins_encode %{
7243 assert(UseFMA, "Needs FMA instructions support.");
7244 __ fmsub_d(as_FloatRegister($dst$$reg),
7245 as_FloatRegister($src1$$reg),
7246 as_FloatRegister($src2$$reg),
7247 as_FloatRegister($src3$$reg));
7248 %}
7249
7250 ins_pipe(pipe_class_default);
7251 %}
7252
7253 // src1 * (-src2) + src3
7254 // "(-src1) * src2 + src3" has been idealized to "src2 * (-src1) + src3"
7255 instruct nmsubF_reg_reg(fRegF dst, fRegF src1, fRegF src2, fRegF src3) %{
7256 match(Set dst (FmaF src3 (Binary src1 (NegF src2))));
7257
7258 ins_cost(FMUL_SINGLE_COST);
7259 format %{ "fnmsub.s $dst, $src1, $src2, $src3\t#@nmsubF_reg_reg" %}
7260
7261 ins_encode %{
7262 assert(UseFMA, "Needs FMA instructions support.");
7263 __ fnmsub_s(as_FloatRegister($dst$$reg),
7264 as_FloatRegister($src1$$reg),
7265 as_FloatRegister($src2$$reg),
7266 as_FloatRegister($src3$$reg));
7267 %}
7268
7269 ins_pipe(pipe_class_default);
7270 %}
7271
7272 // src1 * (-src2) + src3
7273 // "(-src1) * src2 + src3" has been idealized to "src2 * (-src1) + src3"
7274 instruct nmsubD_reg_reg(fRegD dst, fRegD src1, fRegD src2, fRegD src3) %{
7275 match(Set dst (FmaD src3 (Binary src1 (NegD src2))));
7276
7277 ins_cost(FMUL_DOUBLE_COST);
7278 format %{ "fnmsub.d $dst, $src1, $src2, $src3\t#@nmsubD_reg_reg" %}
7279
7280 ins_encode %{
7281 assert(UseFMA, "Needs FMA instructions support.");
7282 __ fnmsub_d(as_FloatRegister($dst$$reg),
7283 as_FloatRegister($src1$$reg),
7284 as_FloatRegister($src2$$reg),
7285 as_FloatRegister($src3$$reg));
7286 %}
7287
7288 ins_pipe(pipe_class_default);
7289 %}
7290
7291 // src1 * (-src2) - src3
7292 // "(-src1) * src2 - src3" has been idealized to "src2 * (-src1) - src3"
7293 instruct nmaddF_reg_reg(fRegF dst, fRegF src1, fRegF src2, fRegF src3) %{
7294 match(Set dst (FmaF (NegF src3) (Binary src1 (NegF src2))));
7295
7296 ins_cost(FMUL_SINGLE_COST);
7297 format %{ "fnmadd.s $dst, $src1, $src2, $src3\t#@nmaddF_reg_reg" %}
7298
7299 ins_encode %{
7300 assert(UseFMA, "Needs FMA instructions support.");
7301 __ fnmadd_s(as_FloatRegister($dst$$reg),
7302 as_FloatRegister($src1$$reg),
7303 as_FloatRegister($src2$$reg),
7304 as_FloatRegister($src3$$reg));
7305 %}
7306
7307 ins_pipe(pipe_class_default);
7308 %}
7309
7310 // src1 * (-src2) - src3
7311 // "(-src1) * src2 - src3" has been idealized to "src2 * (-src1) - src3"
7312 instruct nmaddD_reg_reg(fRegD dst, fRegD src1, fRegD src2, fRegD src3) %{
7313 match(Set dst (FmaD (NegD src3) (Binary src1 (NegD src2))));
7314
7315 ins_cost(FMUL_DOUBLE_COST);
7316 format %{ "fnmadd.d $dst, $src1, $src2, $src3\t#@nmaddD_reg_reg" %}
7317
7318 ins_encode %{
7319 assert(UseFMA, "Needs FMA instructions support.");
7320 __ fnmadd_d(as_FloatRegister($dst$$reg),
7321 as_FloatRegister($src1$$reg),
7322 as_FloatRegister($src2$$reg),
7323 as_FloatRegister($src3$$reg));
7324 %}
7325
7326 ins_pipe(pipe_class_default);
7327 %}
7328
7329 // Math.max(FF)F
7330 instruct maxF_reg_reg(fRegF dst, fRegF src1, fRegF src2, rFlagsReg cr) %{
7331 predicate(!UseZfa);
7332 match(Set dst (MaxF src1 src2));
7333 effect(KILL cr);
7334
7335 format %{ "maxF $dst, $src1, $src2" %}
7336
7337 ins_encode %{
7338 __ minmax_fp(as_FloatRegister($dst$$reg),
7339 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg),
7340 __ FLOAT_TYPE::single_precision, false /* is_min */);
7341 %}
7342
7343 ins_pipe(pipe_class_default);
7344 %}
7345
7346 instruct maxF_reg_reg_zfa(fRegF dst, fRegF src1, fRegF src2) %{
7347 predicate(UseZfa);
7348 match(Set dst (MaxF src1 src2));
7349
7350 format %{ "maxF $dst, $src1, $src2" %}
7351
7352 ins_encode %{
7353 __ fmaxm_s(as_FloatRegister($dst$$reg),
7354 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
7355 %}
7356
7357 ins_pipe(pipe_class_default);
7358 %}
7359
7360 // Math.min(FF)F
7361 instruct minF_reg_reg(fRegF dst, fRegF src1, fRegF src2, rFlagsReg cr) %{
7362 predicate(!UseZfa);
7363 match(Set dst (MinF src1 src2));
7364 effect(KILL cr);
7365
7366 format %{ "minF $dst, $src1, $src2" %}
7367
7368 ins_encode %{
7369 __ minmax_fp(as_FloatRegister($dst$$reg),
7370 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg),
7371 __ FLOAT_TYPE::single_precision, true /* is_min */);
7372 %}
7373
7374 ins_pipe(pipe_class_default);
7375 %}
7376
7377 instruct minF_reg_reg_zfa(fRegF dst, fRegF src1, fRegF src2) %{
7378 predicate(UseZfa);
7379 match(Set dst (MinF src1 src2));
7380
7381 format %{ "minF $dst, $src1, $src2" %}
7382
7383 ins_encode %{
7384 __ fminm_s(as_FloatRegister($dst$$reg),
7385 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
7386 %}
7387
7388 ins_pipe(pipe_class_default);
7389 %}
7390
7391 // Math.max(DD)D
7392 instruct maxD_reg_reg(fRegD dst, fRegD src1, fRegD src2, rFlagsReg cr) %{
7393 predicate(!UseZfa);
7394 match(Set dst (MaxD src1 src2));
7395 effect(KILL cr);
7396
7397 format %{ "maxD $dst, $src1, $src2" %}
7398
7399 ins_encode %{
7400 __ minmax_fp(as_FloatRegister($dst$$reg),
7401 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg),
7402 __ FLOAT_TYPE::double_precision, false /* is_min */);
7403 %}
7404
7405 ins_pipe(pipe_class_default);
7406 %}
7407
7408 instruct maxD_reg_reg_zfa(fRegD dst, fRegD src1, fRegD src2) %{
7409 predicate(UseZfa);
7410 match(Set dst (MaxD src1 src2));
7411
7412 format %{ "maxD $dst, $src1, $src2" %}
7413
7414 ins_encode %{
7415 __ fmaxm_d(as_FloatRegister($dst$$reg),
7416 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
7417 %}
7418
7419 ins_pipe(pipe_class_default);
7420 %}
7421
7422 // Math.min(DD)D
7423 instruct minD_reg_reg(fRegD dst, fRegD src1, fRegD src2, rFlagsReg cr) %{
7424 predicate(!UseZfa);
7425 match(Set dst (MinD src1 src2));
7426 effect(KILL cr);
7427
7428 format %{ "minD $dst, $src1, $src2" %}
7429
7430 ins_encode %{
7431 __ minmax_fp(as_FloatRegister($dst$$reg),
7432 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg),
7433 __ FLOAT_TYPE::double_precision, true /* is_min */);
7434 %}
7435
7436 ins_pipe(pipe_class_default);
7437 %}
7438
7439 instruct minD_reg_reg_zfa(fRegD dst, fRegD src1, fRegD src2) %{
7440 predicate(UseZfa);
7441 match(Set dst (MinD src1 src2));
7442
7443 format %{ "minD $dst, $src1, $src2" %}
7444
7445 ins_encode %{
7446 __ fminm_d(as_FloatRegister($dst$$reg),
7447 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
7448 %}
7449
7450 ins_pipe(pipe_class_default);
7451 %}
7452
7453 // Float.isInfinite
7454 instruct isInfiniteF_reg_reg(iRegINoSp dst, fRegF src)
7455 %{
7456 match(Set dst (IsInfiniteF src));
7457
7458 format %{ "isInfinite $dst, $src" %}
7459 ins_encode %{
7460 __ fclass_s(as_Register($dst$$reg), as_FloatRegister($src$$reg));
7461 __ andi(as_Register($dst$$reg), as_Register($dst$$reg), Assembler::FClassBits::inf);
7462 __ slt(as_Register($dst$$reg), zr, as_Register($dst$$reg));
7463 %}
7464
7465 ins_pipe(pipe_class_default);
7466 %}
7467
7468 // Double.isInfinite
7469 instruct isInfiniteD_reg_reg(iRegINoSp dst, fRegD src)
7470 %{
7471 match(Set dst (IsInfiniteD src));
7472
7473 format %{ "isInfinite $dst, $src" %}
7474 ins_encode %{
7475 __ fclass_d(as_Register($dst$$reg), as_FloatRegister($src$$reg));
7476 __ andi(as_Register($dst$$reg), as_Register($dst$$reg), Assembler::FClassBits::inf);
7477 __ slt(as_Register($dst$$reg), zr, as_Register($dst$$reg));
7478 %}
7479
7480 ins_pipe(pipe_class_default);
7481 %}
7482
7483 // Float.isFinite
7484 instruct isFiniteF_reg_reg(iRegINoSp dst, fRegF src)
7485 %{
7486 match(Set dst (IsFiniteF src));
7487
7488 format %{ "isFinite $dst, $src" %}
7489 ins_encode %{
7490 __ fclass_s(as_Register($dst$$reg), as_FloatRegister($src$$reg));
7491 __ andi(as_Register($dst$$reg), as_Register($dst$$reg), Assembler::FClassBits::finite);
7492 __ slt(as_Register($dst$$reg), zr, as_Register($dst$$reg));
7493 %}
7494
7495 ins_pipe(pipe_class_default);
7496 %}
7497
7498 // Double.isFinite
7499 instruct isFiniteD_reg_reg(iRegINoSp dst, fRegD src)
7500 %{
7501 match(Set dst (IsFiniteD src));
7502
7503 format %{ "isFinite $dst, $src" %}
7504 ins_encode %{
7505 __ fclass_d(as_Register($dst$$reg), as_FloatRegister($src$$reg));
7506 __ andi(as_Register($dst$$reg), as_Register($dst$$reg), Assembler::FClassBits::finite);
7507 __ slt(as_Register($dst$$reg), zr, as_Register($dst$$reg));
7508 %}
7509
7510 ins_pipe(pipe_class_default);
7511 %}
7512
7513 instruct divF_reg_reg(fRegF dst, fRegF src1, fRegF src2) %{
7514 match(Set dst (DivF src1 src2));
7515
7516 ins_cost(FDIV_COST);
7517 format %{ "fdiv.s $dst, $src1, $src2\t#@divF_reg_reg" %}
7518
7519 ins_encode %{
7520 __ fdiv_s(as_FloatRegister($dst$$reg),
7521 as_FloatRegister($src1$$reg),
7522 as_FloatRegister($src2$$reg));
7523 %}
7524
7525 ins_pipe(fp_div_s);
7526 %}
7527
7528 instruct divD_reg_reg(fRegD dst, fRegD src1, fRegD src2) %{
7529 match(Set dst (DivD src1 src2));
7530
7531 ins_cost(FDIV_COST);
7532 format %{ "fdiv.d $dst, $src1, $src2\t#@divD_reg_reg" %}
7533
7534 ins_encode %{
7535 __ fdiv_d(as_FloatRegister($dst$$reg),
7536 as_FloatRegister($src1$$reg),
7537 as_FloatRegister($src2$$reg));
7538 %}
7539
7540 ins_pipe(fp_div_d);
7541 %}
7542
7543 instruct negF_reg_reg(fRegF dst, fRegF src) %{
7544 match(Set dst (NegF src));
7545
7546 ins_cost(XFER_COST);
7547 format %{ "fsgnjn.s $dst, $src, $src\t#@negF_reg_reg" %}
7548
7549 ins_encode %{
7550 __ fneg_s(as_FloatRegister($dst$$reg),
7551 as_FloatRegister($src$$reg));
7552 %}
7553
7554 ins_pipe(fp_uop_s);
7555 %}
7556
7557 instruct negD_reg_reg(fRegD dst, fRegD src) %{
7558 match(Set dst (NegD src));
7559
7560 ins_cost(XFER_COST);
7561 format %{ "fsgnjn.d $dst, $src, $src\t#@negD_reg_reg" %}
7562
7563 ins_encode %{
7564 __ fneg_d(as_FloatRegister($dst$$reg),
7565 as_FloatRegister($src$$reg));
7566 %}
7567
7568 ins_pipe(fp_uop_d);
7569 %}
7570
7571 instruct absI_reg(iRegINoSp dst, iRegIorL2I src) %{
7572 match(Set dst (AbsI src));
7573
7574 ins_cost(ALU_COST * 3);
7575 format %{
7576 "sraiw t0, $src, 0x1f\n\t"
7577 "addw $dst, $src, t0\n\t"
7578 "xorr $dst, $dst, t0\t#@absI_reg"
7579 %}
7580
7581 ins_encode %{
7582 __ sraiw(t0, as_Register($src$$reg), 0x1f);
7583 __ addw(as_Register($dst$$reg), as_Register($src$$reg), t0);
7584 __ xorr(as_Register($dst$$reg), as_Register($dst$$reg), t0);
7585 %}
7586
7587 ins_pipe(pipe_class_default);
7588 %}
7589
7590 instruct absL_reg(iRegLNoSp dst, iRegL src) %{
7591 match(Set dst (AbsL src));
7592
7593 ins_cost(ALU_COST * 3);
7594 format %{
7595 "srai t0, $src, 0x3f\n\t"
7596 "add $dst, $src, t0\n\t"
7597 "xorr $dst, $dst, t0\t#@absL_reg"
7598 %}
7599
7600 ins_encode %{
7601 __ srai(t0, as_Register($src$$reg), 0x3f);
7602 __ add(as_Register($dst$$reg), as_Register($src$$reg), t0);
7603 __ xorr(as_Register($dst$$reg), as_Register($dst$$reg), t0);
7604 %}
7605
7606 ins_pipe(pipe_class_default);
7607 %}
7608
7609 instruct absF_reg(fRegF dst, fRegF src) %{
7610 match(Set dst (AbsF src));
7611
7612 ins_cost(XFER_COST);
7613 format %{ "fsgnjx.s $dst, $src, $src\t#@absF_reg" %}
7614 ins_encode %{
7615 __ fabs_s(as_FloatRegister($dst$$reg),
7616 as_FloatRegister($src$$reg));
7617 %}
7618
7619 ins_pipe(fp_uop_s);
7620 %}
7621
7622 instruct absD_reg(fRegD dst, fRegD src) %{
7623 match(Set dst (AbsD src));
7624
7625 ins_cost(XFER_COST);
7626 format %{ "fsgnjx.d $dst, $src, $src\t#@absD_reg" %}
7627 ins_encode %{
7628 __ fabs_d(as_FloatRegister($dst$$reg),
7629 as_FloatRegister($src$$reg));
7630 %}
7631
7632 ins_pipe(fp_uop_d);
7633 %}
7634
7635 instruct sqrtF_reg(fRegF dst, fRegF src) %{
7636 match(Set dst (SqrtF src));
7637
7638 ins_cost(FSQRT_COST);
7639 format %{ "fsqrt.s $dst, $src\t#@sqrtF_reg" %}
7640 ins_encode %{
7641 __ fsqrt_s(as_FloatRegister($dst$$reg),
7642 as_FloatRegister($src$$reg));
7643 %}
7644
7645 ins_pipe(fp_sqrt_s);
7646 %}
7647
7648 instruct sqrtD_reg(fRegD dst, fRegD src) %{
7649 match(Set dst (SqrtD src));
7650
7651 ins_cost(FSQRT_COST);
7652 format %{ "fsqrt.d $dst, $src\t#@sqrtD_reg" %}
7653 ins_encode %{
7654 __ fsqrt_d(as_FloatRegister($dst$$reg),
7655 as_FloatRegister($src$$reg));
7656 %}
7657
7658 ins_pipe(fp_sqrt_d);
7659 %}
7660
7661 // Round Instruction
7662 instruct roundD_reg(fRegD dst, fRegD src, immI rmode, iRegLNoSp tmp1, iRegLNoSp tmp2, iRegLNoSp tmp3) %{
7663 match(Set dst (RoundDoubleMode src rmode));
7664 ins_cost(2 * XFER_COST + BRANCH_COST);
7665 effect(TEMP_DEF dst, TEMP tmp1, TEMP tmp2, TEMP tmp3);
7666
7667 format %{ "RoundDoubleMode $src, $rmode" %}
7668 ins_encode %{
7669 __ round_double_mode(as_FloatRegister($dst$$reg),
7670 as_FloatRegister($src$$reg), $rmode$$constant, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
7671 %}
7672 ins_pipe(pipe_class_default);
7673 %}
7674
7675 // Copysign and signum intrinsics
7676
7677 instruct copySignD_reg(fRegD dst, fRegD src1, fRegD src2, immD zero) %{
7678 match(Set dst (CopySignD src1 (Binary src2 zero)));
7679 format %{ "CopySignD $dst $src1 $src2" %}
7680 ins_encode %{
7681 FloatRegister dst = as_FloatRegister($dst$$reg),
7682 src1 = as_FloatRegister($src1$$reg),
7683 src2 = as_FloatRegister($src2$$reg);
7684 __ fsgnj_d(dst, src1, src2);
7685 %}
7686 ins_pipe(fp_dop_reg_reg_d);
7687 %}
7688
7689 instruct copySignF_reg(fRegF dst, fRegF src1, fRegF src2) %{
7690 match(Set dst (CopySignF src1 src2));
7691 format %{ "CopySignF $dst $src1 $src2" %}
7692 ins_encode %{
7693 FloatRegister dst = as_FloatRegister($dst$$reg),
7694 src1 = as_FloatRegister($src1$$reg),
7695 src2 = as_FloatRegister($src2$$reg);
7696 __ fsgnj_s(dst, src1, src2);
7697 %}
7698 ins_pipe(fp_dop_reg_reg_s);
7699 %}
7700
7701 instruct signumD_reg(fRegD dst, immD zero, fRegD one) %{
7702 match(Set dst (SignumD dst (Binary zero one)));
7703 format %{ "signumD $dst, $dst" %}
7704 ins_encode %{
7705 __ signum_fp(as_FloatRegister($dst$$reg), as_FloatRegister($one$$reg), true /* is_double */);
7706 %}
7707 ins_pipe(pipe_class_default);
7708 %}
7709
7710 instruct signumF_reg(fRegF dst, immF zero, fRegF one) %{
7711 match(Set dst (SignumF dst (Binary zero one)));
7712 format %{ "signumF $dst, $dst" %}
7713 ins_encode %{
7714 __ signum_fp(as_FloatRegister($dst$$reg), as_FloatRegister($one$$reg), false /* is_double */);
7715 %}
7716 ins_pipe(pipe_class_default);
7717 %}
7718
7719 // Arithmetic Instructions End
7720
7721 // ============================================================================
7722 // Logical Instructions
7723
7724 // Register And
7725 instruct andI_reg_reg(iRegINoSp dst, iRegI src1, iRegI src2) %{
7726 match(Set dst (AndI src1 src2));
7727
7728 format %{ "andr $dst, $src1, $src2\t#@andI_reg_reg" %}
7729
7730 ins_cost(ALU_COST);
7731 ins_encode %{
7732 __ andr(as_Register($dst$$reg),
7733 as_Register($src1$$reg),
7734 as_Register($src2$$reg));
7735 %}
7736
7737 ins_pipe(ialu_reg_reg);
7738 %}
7739
7740 // Immediate And
7741 instruct andI_reg_imm(iRegINoSp dst, iRegI src1, immIAdd src2) %{
7742 match(Set dst (AndI src1 src2));
7743
7744 format %{ "andi $dst, $src1, $src2\t#@andI_reg_imm" %}
7745
7746 ins_cost(ALU_COST);
7747 ins_encode %{
7748 __ andi(as_Register($dst$$reg),
7749 as_Register($src1$$reg),
7750 (int32_t)($src2$$constant));
7751 %}
7752
7753 ins_pipe(ialu_reg_imm);
7754 %}
7755
7756 // Register Or
7757 instruct orI_reg_reg(iRegINoSp dst, iRegI src1, iRegI src2) %{
7758 match(Set dst (OrI src1 src2));
7759
7760 format %{ "orr $dst, $src1, $src2\t#@orI_reg_reg" %}
7761
7762 ins_cost(ALU_COST);
7763 ins_encode %{
7764 __ orr(as_Register($dst$$reg),
7765 as_Register($src1$$reg),
7766 as_Register($src2$$reg));
7767 %}
7768
7769 ins_pipe(ialu_reg_reg);
7770 %}
7771
7772 // Immediate Or
7773 instruct orI_reg_imm(iRegINoSp dst, iRegI src1, immIAdd src2) %{
7774 match(Set dst (OrI src1 src2));
7775
7776 format %{ "ori $dst, $src1, $src2\t#@orI_reg_imm" %}
7777
7778 ins_cost(ALU_COST);
7779 ins_encode %{
7780 __ ori(as_Register($dst$$reg),
7781 as_Register($src1$$reg),
7782 (int32_t)($src2$$constant));
7783 %}
7784
7785 ins_pipe(ialu_reg_imm);
7786 %}
7787
7788 // Register Xor
7789 instruct xorI_reg_reg(iRegINoSp dst, iRegI src1, iRegI src2) %{
7790 match(Set dst (XorI src1 src2));
7791
7792 format %{ "xorr $dst, $src1, $src2\t#@xorI_reg_reg" %}
7793
7794 ins_cost(ALU_COST);
7795 ins_encode %{
7796 __ xorr(as_Register($dst$$reg),
7797 as_Register($src1$$reg),
7798 as_Register($src2$$reg));
7799 %}
7800
7801 ins_pipe(ialu_reg_reg);
7802 %}
7803
7804 // Immediate Xor
7805 instruct xorI_reg_imm(iRegINoSp dst, iRegI src1, immIAdd src2) %{
7806 match(Set dst (XorI src1 src2));
7807
7808 format %{ "xori $dst, $src1, $src2\t#@xorI_reg_imm" %}
7809
7810 ins_cost(ALU_COST);
7811 ins_encode %{
7812 __ xori(as_Register($dst$$reg),
7813 as_Register($src1$$reg),
7814 (int32_t)($src2$$constant));
7815 %}
7816
7817 ins_pipe(ialu_reg_imm);
7818 %}
7819
7820 // Register And Long
7821 instruct andL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
7822 match(Set dst (AndL src1 src2));
7823
7824 format %{ "andr $dst, $src1, $src2\t#@andL_reg_reg" %}
7825
7826 ins_cost(ALU_COST);
7827 ins_encode %{
7828 __ andr(as_Register($dst$$reg),
7829 as_Register($src1$$reg),
7830 as_Register($src2$$reg));
7831 %}
7832
7833 ins_pipe(ialu_reg_reg);
7834 %}
7835
7836 // Immediate And Long
7837 instruct andL_reg_imm(iRegLNoSp dst, iRegL src1, immLAdd src2) %{
7838 match(Set dst (AndL src1 src2));
7839
7840 format %{ "andi $dst, $src1, $src2\t#@andL_reg_imm" %}
7841
7842 ins_cost(ALU_COST);
7843 ins_encode %{
7844 __ andi(as_Register($dst$$reg),
7845 as_Register($src1$$reg),
7846 (int32_t)($src2$$constant));
7847 %}
7848
7849 ins_pipe(ialu_reg_imm);
7850 %}
7851
7852 // Register Or Long
7853 instruct orL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
7854 match(Set dst (OrL src1 src2));
7855
7856 format %{ "orr $dst, $src1, $src2\t#@orL_reg_reg" %}
7857
7858 ins_cost(ALU_COST);
7859 ins_encode %{
7860 __ orr(as_Register($dst$$reg),
7861 as_Register($src1$$reg),
7862 as_Register($src2$$reg));
7863 %}
7864
7865 ins_pipe(ialu_reg_reg);
7866 %}
7867
7868 // Immediate Or Long
7869 instruct orL_reg_imm(iRegLNoSp dst, iRegL src1, immLAdd src2) %{
7870 match(Set dst (OrL src1 src2));
7871
7872 format %{ "ori $dst, $src1, $src2\t#@orL_reg_imm" %}
7873
7874 ins_cost(ALU_COST);
7875 ins_encode %{
7876 __ ori(as_Register($dst$$reg),
7877 as_Register($src1$$reg),
7878 (int32_t)($src2$$constant));
7879 %}
7880
7881 ins_pipe(ialu_reg_imm);
7882 %}
7883
7884 // Register Xor Long
7885 instruct xorL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
7886 match(Set dst (XorL src1 src2));
7887
7888 format %{ "xorr $dst, $src1, $src2\t#@xorL_reg_reg" %}
7889
7890 ins_cost(ALU_COST);
7891 ins_encode %{
7892 __ xorr(as_Register($dst$$reg),
7893 as_Register($src1$$reg),
7894 as_Register($src2$$reg));
7895 %}
7896
7897 ins_pipe(ialu_reg_reg);
7898 %}
7899
7900 // Immediate Xor Long
7901 instruct xorL_reg_imm(iRegLNoSp dst, iRegL src1, immLAdd src2) %{
7902 match(Set dst (XorL src1 src2));
7903
7904 ins_cost(ALU_COST);
7905 format %{ "xori $dst, $src1, $src2\t#@xorL_reg_imm" %}
7906
7907 ins_encode %{
7908 __ xori(as_Register($dst$$reg),
7909 as_Register($src1$$reg),
7910 (int32_t)($src2$$constant));
7911 %}
7912
7913 ins_pipe(ialu_reg_imm);
7914 %}
7915
7916 // ============================================================================
7917 // MemBar Instruction
7918
7919 // RVTSO
7920
7921 instruct unnecessary_membar_rvtso() %{
7922 predicate(UseZtso);
7923 match(LoadFence);
7924 match(StoreFence);
7925 match(StoreStoreFence);
7926 match(MemBarAcquire);
7927 match(MemBarRelease);
7928 match(MemBarStoreStore);
7929 match(MemBarAcquireLock);
7930 match(MemBarReleaseLock);
7931
7932 ins_cost(0);
7933
7934 size(0);
7935
7936 format %{ "#@unnecessary_membar_rvtso elided/tso (empty encoding)" %}
7937 ins_encode %{
7938 __ block_comment("unnecessary_membar_rvtso");
7939 %}
7940 ins_pipe(real_empty);
7941 %}
7942
7943 instruct membar_volatile_rvtso() %{
7944 predicate(UseZtso);
7945 match(MemBarVolatile);
7946 ins_cost(VOLATILE_REF_COST);
7947
7948 format %{ "#@membar_volatile_rvtso\n\t"
7949 "fence w, r"%}
7950
7951 ins_encode %{
7952 __ block_comment("membar_volatile_rvtso");
7953 __ membar(MacroAssembler::StoreLoad);
7954 %}
7955
7956 ins_pipe(pipe_slow);
7957 %}
7958
7959 instruct unnecessary_membar_volatile_rvtso() %{
7960 predicate(UseZtso && Matcher::post_store_load_barrier(n));
7961 match(MemBarVolatile);
7962 ins_cost(0);
7963
7964 size(0);
7965
7966 format %{ "#@unnecessary_membar_volatile_rvtso (unnecessary so empty encoding)" %}
7967 ins_encode %{
7968 __ block_comment("unnecessary_membar_volatile_rvtso");
7969 %}
7970 ins_pipe(real_empty);
7971 %}
7972
7973 // RVWMO
7974
7975 instruct membar_aqcuire_rvwmo() %{
7976 predicate(!UseZtso);
7977 match(LoadFence);
7978 match(MemBarAcquire);
7979 ins_cost(VOLATILE_REF_COST);
7980
7981 format %{ "#@membar_aqcuire_rvwmo\n\t"
7982 "fence r, rw" %}
7983
7984 ins_encode %{
7985 __ block_comment("membar_aqcuire_rvwmo");
7986 __ membar(MacroAssembler::LoadLoad | MacroAssembler::LoadStore);
7987 %}
7988 ins_pipe(pipe_serial);
7989 %}
7990
7991 instruct membar_release_rvwmo() %{
7992 predicate(!UseZtso);
7993 match(StoreFence);
7994 match(MemBarRelease);
7995 ins_cost(VOLATILE_REF_COST);
7996
7997 format %{ "#@membar_release_rvwmo\n\t"
7998 "fence rw, w" %}
7999
8000 ins_encode %{
8001 __ block_comment("membar_release_rvwmo");
8002 __ membar(MacroAssembler::LoadStore | MacroAssembler::StoreStore);
8003 %}
8004 ins_pipe(pipe_serial);
8005 %}
8006
8007 instruct membar_storestore_rvwmo() %{
8008 predicate(!UseZtso);
8009 match(MemBarStoreStore);
8010 match(StoreStoreFence);
8011 ins_cost(VOLATILE_REF_COST);
8012
8013 format %{ "#@membar_storestore_rvwmo\n\t"
8014 "fence w, w" %}
8015
8016 ins_encode %{
8017 __ membar(MacroAssembler::StoreStore);
8018 %}
8019 ins_pipe(pipe_serial);
8020 %}
8021
8022 instruct membar_volatile_rvwmo() %{
8023 predicate(!UseZtso);
8024 match(MemBarVolatile);
8025 ins_cost(VOLATILE_REF_COST);
8026
8027 format %{ "#@membar_volatile_rvwmo\n\t"
8028 "fence w, r"%}
8029
8030 ins_encode %{
8031 __ block_comment("membar_volatile_rvwmo");
8032 __ membar(MacroAssembler::StoreLoad);
8033 %}
8034
8035 ins_pipe(pipe_serial);
8036 %}
8037
8038 instruct membar_lock_rvwmo() %{
8039 predicate(!UseZtso);
8040 match(MemBarAcquireLock);
8041 match(MemBarReleaseLock);
8042 ins_cost(0);
8043
8044 format %{ "#@membar_lock_rvwmo (elided)" %}
8045
8046 ins_encode %{
8047 __ block_comment("membar_lock_rvwmo (elided)");
8048 %}
8049
8050 ins_pipe(pipe_serial);
8051 %}
8052
8053 instruct unnecessary_membar_volatile_rvwmo() %{
8054 predicate(!UseZtso && Matcher::post_store_load_barrier(n));
8055 match(MemBarVolatile);
8056 ins_cost(0);
8057
8058 size(0);
8059 format %{ "#@unnecessary_membar_volatile_rvwmo (unnecessary so empty encoding)" %}
8060 ins_encode %{
8061 __ block_comment("unnecessary_membar_volatile_rvwmo");
8062 %}
8063 ins_pipe(real_empty);
8064 %}
8065
8066 instruct spin_wait() %{
8067 predicate(UseZihintpause);
8068 match(OnSpinWait);
8069 ins_cost(CACHE_MISS_COST);
8070
8071 format %{ "spin_wait" %}
8072
8073 ins_encode %{
8074 __ pause();
8075 %}
8076
8077 ins_pipe(pipe_serial);
8078 %}
8079
8080 // ============================================================================
8081 // Cast Instructions (Java-level type cast)
8082
8083 instruct castX2P(iRegPNoSp dst, iRegL src) %{
8084 match(Set dst (CastX2P src));
8085
8086 ins_cost(ALU_COST);
8087 format %{ "mv $dst, $src\t# long -> ptr, #@castX2P" %}
8088
8089 ins_encode %{
8090 if ($dst$$reg != $src$$reg) {
8091 __ mv(as_Register($dst$$reg), as_Register($src$$reg));
8092 }
8093 %}
8094
8095 ins_pipe(ialu_reg);
8096 %}
8097
8098 instruct castP2X(iRegLNoSp dst, iRegP src) %{
8099 match(Set dst (CastP2X src));
8100
8101 ins_cost(ALU_COST);
8102 format %{ "mv $dst, $src\t# ptr -> long, #@castP2X" %}
8103
8104 ins_encode %{
8105 if ($dst$$reg != $src$$reg) {
8106 __ mv(as_Register($dst$$reg), as_Register($src$$reg));
8107 }
8108 %}
8109
8110 ins_pipe(ialu_reg);
8111 %}
8112
8113 instruct castPP(iRegPNoSp dst)
8114 %{
8115 match(Set dst (CastPP dst));
8116 ins_cost(0);
8117
8118 size(0);
8119 format %{ "# castPP of $dst, #@castPP" %}
8120 ins_encode(/* empty encoding */);
8121 ins_pipe(pipe_class_empty);
8122 %}
8123
8124 instruct castLL(iRegL dst)
8125 %{
8126 match(Set dst (CastLL dst));
8127
8128 size(0);
8129 format %{ "# castLL of $dst, #@castLL" %}
8130 ins_encode(/* empty encoding */);
8131 ins_cost(0);
8132 ins_pipe(pipe_class_empty);
8133 %}
8134
8135 instruct castII(iRegI dst)
8136 %{
8137 match(Set dst (CastII dst));
8138
8139 size(0);
8140 format %{ "# castII of $dst, #@castII" %}
8141 ins_encode(/* empty encoding */);
8142 ins_cost(0);
8143 ins_pipe(pipe_class_empty);
8144 %}
8145
8146 instruct checkCastPP(iRegPNoSp dst)
8147 %{
8148 match(Set dst (CheckCastPP dst));
8149
8150 size(0);
8151 ins_cost(0);
8152 format %{ "# checkcastPP of $dst, #@checkCastPP" %}
8153 ins_encode(/* empty encoding */);
8154 ins_pipe(pipe_class_empty);
8155 %}
8156
8157 instruct castHH(fRegF dst)
8158 %{
8159 match(Set dst (CastHH dst));
8160
8161 size(0);
8162 format %{ "# castHH of $dst" %}
8163 ins_encode(/* empty encoding */);
8164 ins_cost(0);
8165 ins_pipe(pipe_class_empty);
8166 %}
8167
8168 instruct castFF(fRegF dst)
8169 %{
8170 match(Set dst (CastFF dst));
8171
8172 size(0);
8173 format %{ "# castFF of $dst" %}
8174 ins_encode(/* empty encoding */);
8175 ins_cost(0);
8176 ins_pipe(pipe_class_empty);
8177 %}
8178
8179 instruct castDD(fRegD dst)
8180 %{
8181 match(Set dst (CastDD dst));
8182
8183 size(0);
8184 format %{ "# castDD of $dst" %}
8185 ins_encode(/* empty encoding */);
8186 ins_cost(0);
8187 ins_pipe(pipe_class_empty);
8188 %}
8189
8190 instruct castVV(vReg dst)
8191 %{
8192 match(Set dst (CastVV dst));
8193
8194 size(0);
8195 format %{ "# castVV of $dst" %}
8196 ins_encode(/* empty encoding */);
8197 ins_cost(0);
8198 ins_pipe(pipe_class_empty);
8199 %}
8200
8201 // ============================================================================
8202 // Convert Instructions
8203
8204 // int to bool
8205 instruct convI2Bool(iRegINoSp dst, iRegI src)
8206 %{
8207 match(Set dst (Conv2B src));
8208
8209 ins_cost(ALU_COST);
8210 format %{ "snez $dst, $src\t#@convI2Bool" %}
8211
8212 ins_encode %{
8213 __ snez(as_Register($dst$$reg), as_Register($src$$reg));
8214 %}
8215
8216 ins_pipe(ialu_reg);
8217 %}
8218
8219 // pointer to bool
8220 instruct convP2Bool(iRegINoSp dst, iRegP src)
8221 %{
8222 match(Set dst (Conv2B src));
8223
8224 ins_cost(ALU_COST);
8225 format %{ "snez $dst, $src\t#@convP2Bool" %}
8226
8227 ins_encode %{
8228 __ snez(as_Register($dst$$reg), as_Register($src$$reg));
8229 %}
8230
8231 ins_pipe(ialu_reg);
8232 %}
8233
8234 // int <-> long
8235
8236 instruct convI2L_reg_reg(iRegLNoSp dst, iRegIorL2I src)
8237 %{
8238 match(Set dst (ConvI2L src));
8239
8240 ins_cost(ALU_COST);
8241 format %{ "addw $dst, $src, zr\t#@convI2L_reg_reg" %}
8242 ins_encode %{
8243 __ sext(as_Register($dst$$reg), as_Register($src$$reg), 32);
8244 %}
8245 ins_pipe(ialu_reg);
8246 %}
8247
8248 instruct convL2I_reg(iRegINoSp dst, iRegL src) %{
8249 match(Set dst (ConvL2I src));
8250
8251 ins_cost(ALU_COST);
8252 format %{ "addw $dst, $src, zr\t#@convL2I_reg" %}
8253
8254 ins_encode %{
8255 __ sext(as_Register($dst$$reg), as_Register($src$$reg), 32);
8256 %}
8257
8258 ins_pipe(ialu_reg);
8259 %}
8260
8261 // int to unsigned long (Zero-extend)
8262 instruct convI2UL_reg_reg(iRegLNoSp dst, iRegIorL2I src, immL_32bits mask)
8263 %{
8264 match(Set dst (AndL (ConvI2L src) mask));
8265
8266 ins_cost(ALU_COST * 2);
8267 format %{ "zext $dst, $src, 32\t# i2ul, #@convI2UL_reg_reg" %}
8268
8269 ins_encode %{
8270 __ zext(as_Register($dst$$reg), as_Register($src$$reg), 32);
8271 %}
8272
8273 ins_pipe(ialu_reg_shift);
8274 %}
8275
8276 // float <-> double
8277
8278 instruct convF2D_reg(fRegD dst, fRegF src) %{
8279 match(Set dst (ConvF2D src));
8280
8281 ins_cost(XFER_COST);
8282 format %{ "fcvt.d.s $dst, $src\t#@convF2D_reg" %}
8283
8284 ins_encode %{
8285 __ fcvt_d_s(as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg));
8286 %}
8287
8288 ins_pipe(fp_f2d);
8289 %}
8290
8291 instruct convD2F_reg(fRegF dst, fRegD src) %{
8292 match(Set dst (ConvD2F src));
8293
8294 ins_cost(XFER_COST);
8295 format %{ "fcvt.s.d $dst, $src\t#@convD2F_reg" %}
8296
8297 ins_encode %{
8298 __ fcvt_s_d(as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg));
8299 %}
8300
8301 ins_pipe(fp_d2f);
8302 %}
8303
8304 // single <-> half precision
8305
8306 instruct convHF2F_reg_reg(fRegF dst, iRegINoSp src, iRegINoSp tmp) %{
8307 match(Set dst (ConvHF2F src));
8308 effect(TEMP tmp);
8309 format %{ "fmv.h.x $dst, $src\t# move source from $src to $dst\n\t"
8310 "fcvt.s.h $dst, $dst\t# convert half to single precision"
8311 %}
8312 ins_encode %{
8313 __ float16_to_float($dst$$FloatRegister, $src$$Register, $tmp$$Register);
8314 %}
8315 ins_pipe(pipe_slow);
8316 %}
8317
8318 instruct convF2HF_reg_reg(iRegINoSp dst, fRegF src, fRegF ftmp, iRegINoSp xtmp) %{
8319 match(Set dst (ConvF2HF src));
8320 effect(TEMP_DEF dst, TEMP ftmp, TEMP xtmp);
8321 format %{ "fcvt.h.s $ftmp, $src\t# convert single precision to half\n\t"
8322 "fmv.x.h $dst, $ftmp\t# move result from $ftmp to $dst"
8323 %}
8324 ins_encode %{
8325 __ float_to_float16($dst$$Register, $src$$FloatRegister, $ftmp$$FloatRegister, $xtmp$$Register);
8326 %}
8327 ins_pipe(pipe_slow);
8328 %}
8329
8330 // half precision operations
8331
8332 instruct reinterpretS2HF(fRegF dst, iRegI src)
8333 %{
8334 match(Set dst (ReinterpretS2HF src));
8335 format %{ "fmv.h.x $dst, $src" %}
8336 ins_encode %{
8337 __ fmv_h_x($dst$$FloatRegister, $src$$Register);
8338 %}
8339 ins_pipe(fp_i2f);
8340 %}
8341
8342 instruct convF2HFAndS2HF(fRegF dst, fRegF src)
8343 %{
8344 match(Set dst (ReinterpretS2HF (ConvF2HF src)));
8345 format %{ "convF2HFAndS2HF $dst, $src" %}
8346 ins_encode %{
8347 __ fcvt_h_s($dst$$FloatRegister, $src$$FloatRegister);
8348 %}
8349 ins_pipe(fp_uop_s);
8350 %}
8351
8352 instruct reinterpretHF2S(iRegINoSp dst, fRegF src)
8353 %{
8354 match(Set dst (ReinterpretHF2S src));
8355 format %{ "fmv.x.h $dst, $src" %}
8356 ins_encode %{
8357 __ fmv_x_h($dst$$Register, $src$$FloatRegister);
8358 %}
8359 ins_pipe(fp_f2i);
8360 %}
8361
8362 instruct convHF2SAndHF2F(fRegF dst, fRegF src)
8363 %{
8364 match(Set dst (ConvHF2F (ReinterpretHF2S src)));
8365 format %{ "convHF2SAndHF2F $dst, $src" %}
8366 ins_encode %{
8367 __ fcvt_s_h($dst$$FloatRegister, $src$$FloatRegister);
8368 %}
8369 ins_pipe(fp_uop_s);
8370 %}
8371
8372 instruct sqrt_HF_reg(fRegF dst, fRegF src)
8373 %{
8374 match(Set dst (SqrtHF src));
8375 format %{ "fsqrt.h $dst, $src" %}
8376 ins_encode %{
8377 __ fsqrt_h($dst$$FloatRegister, $src$$FloatRegister);
8378 %}
8379 ins_pipe(fp_sqrt_s);
8380 %}
8381
8382 instruct binOps_HF_reg(fRegF dst, fRegF src1, fRegF src2)
8383 %{
8384 match(Set dst (AddHF src1 src2));
8385 match(Set dst (SubHF src1 src2));
8386 match(Set dst (MulHF src1 src2));
8387 match(Set dst (DivHF src1 src2));
8388 format %{ "binop_hf $dst, $src1, $src2" %}
8389 ins_encode %{
8390 int opcode = this->ideal_Opcode();
8391 switch(opcode) {
8392 case Op_AddHF: __ fadd_h($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); break;
8393 case Op_SubHF: __ fsub_h($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); break;
8394 case Op_MulHF: __ fmul_h($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); break;
8395 case Op_DivHF: __ fdiv_h($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); break;
8396 default: assert(false, "%s is not supported here", NodeClassNames[opcode]); break;
8397 }
8398 %}
8399 ins_pipe(fp_dop_reg_reg_s);
8400 %}
8401
8402 instruct min_HF_reg(fRegF dst, fRegF src1, fRegF src2, rFlagsReg cr)
8403 %{
8404 predicate(!UseZfa);
8405 match(Set dst (MinHF src1 src2));
8406 effect(KILL cr);
8407
8408 format %{ "min_hf $dst, $src1, $src2" %}
8409
8410 ins_encode %{
8411 __ minmax_fp($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister,
8412 __ FLOAT_TYPE::half_precision, true /* is_min */);
8413 %}
8414 ins_pipe(pipe_class_default);
8415 %}
8416
8417 instruct min_HF_reg_zfa(fRegF dst, fRegF src1, fRegF src2)
8418 %{
8419 predicate(UseZfa);
8420 match(Set dst (MinHF src1 src2));
8421
8422 format %{ "min_hf $dst, $src1, $src2" %}
8423
8424 ins_encode %{
8425 __ fminm_h(as_FloatRegister($dst$$reg),
8426 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
8427 %}
8428
8429 ins_pipe(pipe_class_default);
8430 %}
8431
8432 instruct max_HF_reg(fRegF dst, fRegF src1, fRegF src2, rFlagsReg cr)
8433 %{
8434 predicate(!UseZfa);
8435 match(Set dst (MaxHF src1 src2));
8436 effect(KILL cr);
8437
8438 format %{ "max_hf $dst, $src1, $src2" %}
8439
8440 ins_encode %{
8441 __ minmax_fp($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister,
8442 __ FLOAT_TYPE::half_precision, false /* is_min */);
8443 %}
8444 ins_pipe(pipe_class_default);
8445 %}
8446
8447 instruct max_HF_reg_zfa(fRegF dst, fRegF src1, fRegF src2)
8448 %{
8449 predicate(UseZfa);
8450 match(Set dst (MaxHF src1 src2));
8451
8452 format %{ "max_hf $dst, $src1, $src2" %}
8453
8454 ins_encode %{
8455 __ fmaxm_h(as_FloatRegister($dst$$reg),
8456 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
8457 %}
8458
8459 ins_pipe(pipe_class_default);
8460 %}
8461
8462 instruct fma_HF_reg(fRegF dst, fRegF src1, fRegF src2, fRegF src3)
8463 %{
8464 match(Set dst (FmaHF src3 (Binary src1 src2)));
8465 format %{ "fmadd.h $dst, $src1, $src2, $src3\t# $dst = $src1 * $src2 + $src3 fma packedH" %}
8466 ins_encode %{
8467 __ fmadd_h($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister, $src3$$FloatRegister);
8468 %}
8469 ins_pipe(pipe_class_default);
8470 %}
8471
8472 // float <-> int
8473
8474 instruct convF2I_reg_reg(iRegINoSp dst, fRegF src) %{
8475 match(Set dst (ConvF2I src));
8476
8477 ins_cost(XFER_COST);
8478 format %{ "fcvt.w.s $dst, $src\t#@convF2I_reg_reg" %}
8479
8480 ins_encode %{
8481 __ fcvt_w_s_safe($dst$$Register, $src$$FloatRegister);
8482 %}
8483
8484 ins_pipe(fp_f2i);
8485 %}
8486
8487 instruct convI2F_reg_reg(fRegF dst, iRegIorL2I src) %{
8488 match(Set dst (ConvI2F src));
8489
8490 ins_cost(XFER_COST);
8491 format %{ "fcvt.s.w $dst, $src\t#@convI2F_reg_reg" %}
8492
8493 ins_encode %{
8494 __ fcvt_s_w(as_FloatRegister($dst$$reg), as_Register($src$$reg));
8495 %}
8496
8497 ins_pipe(fp_i2f);
8498 %}
8499
8500 // float <-> long
8501
8502 instruct convF2L_reg_reg(iRegLNoSp dst, fRegF src) %{
8503 match(Set dst (ConvF2L src));
8504
8505 ins_cost(XFER_COST);
8506 format %{ "fcvt.l.s $dst, $src\t#@convF2L_reg_reg" %}
8507
8508 ins_encode %{
8509 __ fcvt_l_s_safe($dst$$Register, $src$$FloatRegister);
8510 %}
8511
8512 ins_pipe(fp_f2l);
8513 %}
8514
8515 instruct convL2F_reg_reg(fRegF dst, iRegL src) %{
8516 match(Set dst (ConvL2F src));
8517
8518 ins_cost(XFER_COST);
8519 format %{ "fcvt.s.l $dst, $src\t#@convL2F_reg_reg" %}
8520
8521 ins_encode %{
8522 __ fcvt_s_l(as_FloatRegister($dst$$reg), as_Register($src$$reg));
8523 %}
8524
8525 ins_pipe(fp_l2f);
8526 %}
8527
8528 // double <-> int
8529
8530 instruct convD2I_reg_reg(iRegINoSp dst, fRegD src) %{
8531 match(Set dst (ConvD2I src));
8532
8533 ins_cost(XFER_COST);
8534 format %{ "fcvt.w.d $dst, $src\t#@convD2I_reg_reg" %}
8535
8536 ins_encode %{
8537 __ fcvt_w_d_safe($dst$$Register, $src$$FloatRegister);
8538 %}
8539
8540 ins_pipe(fp_d2i);
8541 %}
8542
8543 instruct convI2D_reg_reg(fRegD dst, iRegIorL2I src) %{
8544 match(Set dst (ConvI2D src));
8545
8546 ins_cost(XFER_COST);
8547 format %{ "fcvt.d.w $dst, $src\t#@convI2D_reg_reg" %}
8548
8549 ins_encode %{
8550 __ fcvt_d_w(as_FloatRegister($dst$$reg), as_Register($src$$reg));
8551 %}
8552
8553 ins_pipe(fp_i2d);
8554 %}
8555
8556 // double <-> long
8557
8558 instruct convD2L_reg_reg(iRegLNoSp dst, fRegD src) %{
8559 match(Set dst (ConvD2L src));
8560
8561 ins_cost(XFER_COST);
8562 format %{ "fcvt.l.d $dst, $src\t#@convD2L_reg_reg" %}
8563
8564 ins_encode %{
8565 __ fcvt_l_d_safe($dst$$Register, $src$$FloatRegister);
8566 %}
8567
8568 ins_pipe(fp_d2l);
8569 %}
8570
8571 instruct convL2D_reg_reg(fRegD dst, iRegL src) %{
8572 match(Set dst (ConvL2D src));
8573
8574 ins_cost(XFER_COST);
8575 format %{ "fcvt.d.l $dst, $src\t#@convL2D_reg_reg" %}
8576
8577 ins_encode %{
8578 __ fcvt_d_l(as_FloatRegister($dst$$reg), as_Register($src$$reg));
8579 %}
8580
8581 ins_pipe(fp_l2d);
8582 %}
8583
8584 // Convert oop into int for vectors alignment masking
8585 instruct convP2I(iRegINoSp dst, iRegP src) %{
8586 match(Set dst (ConvL2I (CastP2X src)));
8587
8588 ins_cost(ALU_COST * 2);
8589 format %{ "zext $dst, $src, 32\t# ptr -> int, #@convP2I" %}
8590
8591 ins_encode %{
8592 __ zext($dst$$Register, $src$$Register, 32);
8593 %}
8594
8595 ins_pipe(ialu_reg);
8596 %}
8597
8598 // Convert compressed oop into int for vectors alignment masking
8599 // in case of 32bit oops (heap < 4Gb).
8600 instruct convN2I(iRegINoSp dst, iRegN src)
8601 %{
8602 predicate(CompressedOops::shift() == 0);
8603 match(Set dst (ConvL2I (CastP2X (DecodeN src))));
8604
8605 ins_cost(ALU_COST);
8606 format %{ "mv $dst, $src\t# compressed ptr -> int, #@convN2I" %}
8607
8608 ins_encode %{
8609 __ mv($dst$$Register, $src$$Register);
8610 %}
8611
8612 ins_pipe(ialu_reg);
8613 %}
8614
8615 instruct round_double_reg(iRegLNoSp dst, fRegD src, fRegD ftmp) %{
8616 match(Set dst (RoundD src));
8617
8618 ins_cost(XFER_COST + BRANCH_COST);
8619 effect(TEMP ftmp);
8620 format %{ "java_round_double $dst, $src\t#@round_double_reg" %}
8621
8622 ins_encode %{
8623 __ java_round_double($dst$$Register, as_FloatRegister($src$$reg), as_FloatRegister($ftmp$$reg));
8624 %}
8625
8626 ins_pipe(pipe_slow);
8627 %}
8628
8629 instruct round_float_reg(iRegINoSp dst, fRegF src, fRegF ftmp) %{
8630 match(Set dst (RoundF src));
8631
8632 ins_cost(XFER_COST + BRANCH_COST);
8633 effect(TEMP ftmp);
8634 format %{ "java_round_float $dst, $src\t#@round_float_reg" %}
8635
8636 ins_encode %{
8637 __ java_round_float($dst$$Register, as_FloatRegister($src$$reg), as_FloatRegister($ftmp$$reg));
8638 %}
8639
8640 ins_pipe(pipe_slow);
8641 %}
8642
8643 // Convert oop pointer into compressed form
8644 instruct encodeHeapOop(iRegNNoSp dst, iRegP src) %{
8645 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
8646 match(Set dst (EncodeP src));
8647 ins_cost(ALU_COST);
8648 format %{ "encode_heap_oop $dst, $src\t#@encodeHeapOop" %}
8649 ins_encode %{
8650 Register s = $src$$Register;
8651 Register d = $dst$$Register;
8652 __ encode_heap_oop(d, s);
8653 %}
8654 ins_pipe(pipe_class_default);
8655 %}
8656
8657 instruct encodeHeapOop_not_null(iRegNNoSp dst, iRegP src) %{
8658 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
8659 match(Set dst (EncodeP src));
8660 ins_cost(ALU_COST);
8661 format %{ "encode_heap_oop_not_null $dst, $src\t#@encodeHeapOop_not_null" %}
8662 ins_encode %{
8663 __ encode_heap_oop_not_null($dst$$Register, $src$$Register);
8664 %}
8665 ins_pipe(pipe_class_default);
8666 %}
8667
8668 instruct decodeHeapOop(iRegPNoSp dst, iRegN src) %{
8669 predicate(n->bottom_type()->is_ptr()->ptr() != TypePtr::NotNull &&
8670 n->bottom_type()->is_ptr()->ptr() != TypePtr::Constant);
8671 match(Set dst (DecodeN src));
8672
8673 ins_cost(0);
8674 format %{ "decode_heap_oop $dst, $src\t#@decodeHeapOop" %}
8675 ins_encode %{
8676 Register s = $src$$Register;
8677 Register d = $dst$$Register;
8678 __ decode_heap_oop(d, s);
8679 %}
8680 ins_pipe(pipe_class_default);
8681 %}
8682
8683 instruct decodeHeapOop_not_null(iRegPNoSp dst, iRegN src) %{
8684 predicate(n->bottom_type()->is_ptr()->ptr() == TypePtr::NotNull ||
8685 n->bottom_type()->is_ptr()->ptr() == TypePtr::Constant);
8686 match(Set dst (DecodeN src));
8687
8688 ins_cost(0);
8689 format %{ "decode_heap_oop_not_null $dst, $src\t#@decodeHeapOop_not_null" %}
8690 ins_encode %{
8691 Register s = $src$$Register;
8692 Register d = $dst$$Register;
8693 __ decode_heap_oop_not_null(d, s);
8694 %}
8695 ins_pipe(pipe_class_default);
8696 %}
8697
8698 // Convert klass pointer into compressed form.
8699 instruct encodeKlass_not_null(iRegNNoSp dst, iRegP src) %{
8700 match(Set dst (EncodePKlass src));
8701
8702 ins_cost(ALU_COST);
8703 format %{ "encode_klass_not_null $dst, $src\t#@encodeKlass_not_null" %}
8704
8705 ins_encode %{
8706 Register src_reg = as_Register($src$$reg);
8707 Register dst_reg = as_Register($dst$$reg);
8708 __ encode_klass_not_null(dst_reg, src_reg, t0);
8709 %}
8710
8711 ins_pipe(pipe_class_default);
8712 %}
8713
8714 instruct decodeKlass_not_null(iRegPNoSp dst, iRegN src, iRegPNoSp tmp) %{
8715 match(Set dst (DecodeNKlass src));
8716
8717 effect(TEMP tmp);
8718
8719 ins_cost(ALU_COST);
8720 format %{ "decode_klass_not_null $dst, $src\t#@decodeKlass_not_null" %}
8721
8722 ins_encode %{
8723 Register src_reg = as_Register($src$$reg);
8724 Register dst_reg = as_Register($dst$$reg);
8725 Register tmp_reg = as_Register($tmp$$reg);
8726 __ decode_klass_not_null(dst_reg, src_reg, tmp_reg);
8727 %}
8728
8729 ins_pipe(pipe_class_default);
8730 %}
8731
8732 // stack <-> reg and reg <-> reg shuffles with no conversion
8733
8734 instruct MoveF2I_stack_reg(iRegINoSp dst, stackSlotF src) %{
8735
8736 match(Set dst (MoveF2I src));
8737
8738 effect(DEF dst, USE src);
8739
8740 ins_cost(LOAD_COST);
8741
8742 format %{ "lw $dst, $src\t#@MoveF2I_stack_reg" %}
8743
8744 ins_encode %{
8745 __ lw(as_Register($dst$$reg), Address(sp, $src$$disp));
8746 %}
8747
8748 ins_pipe(iload_reg_reg);
8749
8750 %}
8751
8752 instruct MoveI2F_stack_reg(fRegF dst, stackSlotI src) %{
8753
8754 match(Set dst (MoveI2F src));
8755
8756 effect(DEF dst, USE src);
8757
8758 ins_cost(LOAD_COST);
8759
8760 format %{ "flw $dst, $src\t#@MoveI2F_stack_reg" %}
8761
8762 ins_encode %{
8763 __ flw(as_FloatRegister($dst$$reg), Address(sp, $src$$disp));
8764 %}
8765
8766 ins_pipe(fp_load_mem_s);
8767
8768 %}
8769
8770 instruct MoveD2L_stack_reg(iRegLNoSp dst, stackSlotD src) %{
8771
8772 match(Set dst (MoveD2L src));
8773
8774 effect(DEF dst, USE src);
8775
8776 ins_cost(LOAD_COST);
8777
8778 format %{ "ld $dst, $src\t#@MoveD2L_stack_reg" %}
8779
8780 ins_encode %{
8781 __ ld(as_Register($dst$$reg), Address(sp, $src$$disp));
8782 %}
8783
8784 ins_pipe(iload_reg_reg);
8785
8786 %}
8787
8788 instruct MoveL2D_stack_reg(fRegD dst, stackSlotL src) %{
8789
8790 match(Set dst (MoveL2D src));
8791
8792 effect(DEF dst, USE src);
8793
8794 ins_cost(LOAD_COST);
8795
8796 format %{ "fld $dst, $src\t#@MoveL2D_stack_reg" %}
8797
8798 ins_encode %{
8799 __ fld(as_FloatRegister($dst$$reg), Address(sp, $src$$disp));
8800 %}
8801
8802 ins_pipe(fp_load_mem_d);
8803
8804 %}
8805
8806 instruct MoveF2I_reg_stack(stackSlotI dst, fRegF src) %{
8807
8808 match(Set dst (MoveF2I src));
8809
8810 effect(DEF dst, USE src);
8811
8812 ins_cost(STORE_COST);
8813
8814 format %{ "fsw $src, $dst\t#@MoveF2I_reg_stack" %}
8815
8816 ins_encode %{
8817 __ fsw(as_FloatRegister($src$$reg), Address(sp, $dst$$disp));
8818 %}
8819
8820 ins_pipe(fp_store_reg_s);
8821
8822 %}
8823
8824 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{
8825
8826 match(Set dst (MoveI2F src));
8827
8828 effect(DEF dst, USE src);
8829
8830 ins_cost(STORE_COST);
8831
8832 format %{ "sw $src, $dst\t#@MoveI2F_reg_stack" %}
8833
8834 ins_encode %{
8835 __ sw(as_Register($src$$reg), Address(sp, $dst$$disp));
8836 %}
8837
8838 ins_pipe(istore_reg_reg);
8839
8840 %}
8841
8842 instruct MoveD2L_reg_stack(stackSlotL dst, fRegD src) %{
8843
8844 match(Set dst (MoveD2L src));
8845
8846 effect(DEF dst, USE src);
8847
8848 ins_cost(STORE_COST);
8849
8850 format %{ "fsd $dst, $src\t#@MoveD2L_reg_stack" %}
8851
8852 ins_encode %{
8853 __ fsd(as_FloatRegister($src$$reg), Address(sp, $dst$$disp));
8854 %}
8855
8856 ins_pipe(fp_store_reg_d);
8857
8858 %}
8859
8860 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{
8861
8862 match(Set dst (MoveL2D src));
8863
8864 effect(DEF dst, USE src);
8865
8866 ins_cost(STORE_COST);
8867
8868 format %{ "sd $src, $dst\t#@MoveL2D_reg_stack" %}
8869
8870 ins_encode %{
8871 __ sd(as_Register($src$$reg), Address(sp, $dst$$disp));
8872 %}
8873
8874 ins_pipe(istore_reg_reg);
8875
8876 %}
8877
8878 instruct MoveF2I_reg_reg(iRegINoSp dst, fRegF src) %{
8879
8880 match(Set dst (MoveF2I src));
8881
8882 effect(DEF dst, USE src);
8883
8884 ins_cost(FMVX_COST);
8885
8886 format %{ "fmv.x.w $dst, $src\t#@MoveF2I_reg_reg" %}
8887
8888 ins_encode %{
8889 __ fmv_x_w(as_Register($dst$$reg), as_FloatRegister($src$$reg));
8890 %}
8891
8892 ins_pipe(fp_f2i);
8893
8894 %}
8895
8896 instruct MoveI2F_reg_reg(fRegF dst, iRegI src) %{
8897
8898 match(Set dst (MoveI2F src));
8899
8900 effect(DEF dst, USE src);
8901
8902 ins_cost(FMVX_COST);
8903
8904 format %{ "fmv.w.x $dst, $src\t#@MoveI2F_reg_reg" %}
8905
8906 ins_encode %{
8907 __ fmv_w_x(as_FloatRegister($dst$$reg), as_Register($src$$reg));
8908 %}
8909
8910 ins_pipe(fp_i2f);
8911
8912 %}
8913
8914 instruct MoveD2L_reg_reg(iRegLNoSp dst, fRegD src) %{
8915
8916 match(Set dst (MoveD2L src));
8917
8918 effect(DEF dst, USE src);
8919
8920 ins_cost(FMVX_COST);
8921
8922 format %{ "fmv.x.d $dst, $src\t#@MoveD2L_reg_reg" %}
8923
8924 ins_encode %{
8925 __ fmv_x_d(as_Register($dst$$reg), as_FloatRegister($src$$reg));
8926 %}
8927
8928 ins_pipe(fp_d2l);
8929
8930 %}
8931
8932 instruct MoveL2D_reg_reg(fRegD dst, iRegL src) %{
8933
8934 match(Set dst (MoveL2D src));
8935
8936 effect(DEF dst, USE src);
8937
8938 ins_cost(FMVX_COST);
8939
8940 format %{ "fmv.d.x $dst, $src\t#@MoveL2D_reg_reg" %}
8941
8942 ins_encode %{
8943 __ fmv_d_x(as_FloatRegister($dst$$reg), as_Register($src$$reg));
8944 %}
8945
8946 ins_pipe(fp_l2d);
8947
8948 %}
8949
8950 // ============================================================================
8951 // Compare Instructions which set the result float comparisons in dest register.
8952
8953 instruct cmpF3_reg_reg(iRegINoSp dst, fRegF op1, fRegF op2)
8954 %{
8955 match(Set dst (CmpF3 op1 op2));
8956
8957 ins_cost(XFER_COST * 2 + BRANCH_COST + ALU_COST);
8958 format %{ "flt.s $dst, $op2, $op1\t#@cmpF3_reg_reg\n\t"
8959 "bgtz $dst, done\n\t"
8960 "feq.s $dst, $op1, $op2\n\t"
8961 "addi $dst, $dst, -1\n\t"
8962 "done:"
8963 %}
8964
8965 ins_encode %{
8966 // we want -1 for unordered or less than, 0 for equal and 1 for greater than.
8967 __ float_compare(as_Register($dst$$reg), as_FloatRegister($op1$$reg),
8968 as_FloatRegister($op2$$reg), -1 /*unordered_result < 0*/);
8969 %}
8970
8971 ins_pipe(pipe_class_default);
8972 %}
8973
8974 instruct cmpD3_reg_reg(iRegINoSp dst, fRegD op1, fRegD op2)
8975 %{
8976 match(Set dst (CmpD3 op1 op2));
8977
8978 ins_cost(XFER_COST * 2 + BRANCH_COST + ALU_COST);
8979 format %{ "flt.d $dst, $op2, $op1\t#@cmpD3_reg_reg\n\t"
8980 "bgtz $dst, done\n\t"
8981 "feq.d $dst, $op1, $op2\n\t"
8982 "addi $dst, $dst, -1\n\t"
8983 "done:"
8984 %}
8985
8986 ins_encode %{
8987 // we want -1 for unordered or less than, 0 for equal and 1 for greater than.
8988 __ double_compare(as_Register($dst$$reg), as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg), -1 /*unordered_result < 0*/);
8989 %}
8990
8991 ins_pipe(pipe_class_default);
8992 %}
8993
8994 instruct cmpL3_reg_reg(iRegINoSp dst, iRegL op1, iRegL op2)
8995 %{
8996 match(Set dst (CmpL3 op1 op2));
8997
8998 ins_cost(ALU_COST * 3 + BRANCH_COST);
8999 format %{ "slt $dst, $op2, $op1\t#@cmpL3_reg_reg\n\t"
9000 "bnez $dst, done\n\t"
9001 "slt $dst, $op1, $op2\n\t"
9002 "neg $dst, $dst\n\t"
9003 "done:"
9004 %}
9005 ins_encode %{
9006 __ cmp_l2i(t0, as_Register($op1$$reg), as_Register($op2$$reg));
9007 __ mv(as_Register($dst$$reg), t0);
9008 %}
9009
9010 ins_pipe(pipe_class_default);
9011 %}
9012
9013 instruct cmpUL3_reg_reg(iRegINoSp dst, iRegL op1, iRegL op2)
9014 %{
9015 match(Set dst (CmpUL3 op1 op2));
9016
9017 ins_cost(ALU_COST * 3 + BRANCH_COST);
9018 format %{ "sltu $dst, $op2, $op1\t#@cmpUL3_reg_reg\n\t"
9019 "bnez $dst, done\n\t"
9020 "sltu $dst, $op1, $op2\n\t"
9021 "neg $dst, $dst\n\t"
9022 "done:"
9023 %}
9024 ins_encode %{
9025 __ cmp_ul2i(t0, as_Register($op1$$reg), as_Register($op2$$reg));
9026 __ mv(as_Register($dst$$reg), t0);
9027 %}
9028
9029 ins_pipe(pipe_class_default);
9030 %}
9031
9032 instruct cmpU3_reg_reg(iRegINoSp dst, iRegI op1, iRegI op2)
9033 %{
9034 match(Set dst (CmpU3 op1 op2));
9035
9036 ins_cost(ALU_COST * 3 + BRANCH_COST);
9037 format %{ "sltu $dst, $op2, $op1\t#@cmpU3_reg_reg\n\t"
9038 "bnez $dst, done\n\t"
9039 "sltu $dst, $op1, $op2\n\t"
9040 "neg $dst, $dst\n\t"
9041 "done:"
9042 %}
9043 ins_encode %{
9044 __ cmp_uw2i(t0, as_Register($op1$$reg), as_Register($op2$$reg));
9045 __ mv(as_Register($dst$$reg), t0);
9046 %}
9047
9048 ins_pipe(pipe_class_default);
9049 %}
9050
9051 instruct cmpLTMask_reg_reg(iRegINoSp dst, iRegI p, iRegI q)
9052 %{
9053 match(Set dst (CmpLTMask p q));
9054
9055 ins_cost(2 * ALU_COST);
9056
9057 format %{ "slt $dst, $p, $q\t#@cmpLTMask_reg_reg\n\t"
9058 "subw $dst, zr, $dst\t#@cmpLTMask_reg_reg"
9059 %}
9060
9061 ins_encode %{
9062 __ slt(as_Register($dst$$reg), as_Register($p$$reg), as_Register($q$$reg));
9063 __ subw(as_Register($dst$$reg), zr, as_Register($dst$$reg));
9064 %}
9065
9066 ins_pipe(ialu_reg_reg);
9067 %}
9068
9069 instruct cmpLTMask_reg_zero(iRegINoSp dst, iRegIorL2I op, immI0 zero)
9070 %{
9071 match(Set dst (CmpLTMask op zero));
9072
9073 ins_cost(ALU_COST);
9074
9075 format %{ "sraiw $dst, $dst, 31\t#@cmpLTMask_reg_reg" %}
9076
9077 ins_encode %{
9078 __ sraiw(as_Register($dst$$reg), as_Register($op$$reg), 31);
9079 %}
9080
9081 ins_pipe(ialu_reg_shift);
9082 %}
9083
9084
9085 // ============================================================================
9086 // Max and Min
9087
9088 instruct minI_reg_reg(iRegINoSp dst, iRegI src)
9089 %{
9090 match(Set dst (MinI dst src));
9091
9092 ins_cost(BRANCH_COST + ALU_COST);
9093 format %{"minI_reg_reg $dst, $dst, $src\t#@minI_reg_reg\n\t"%}
9094
9095 ins_encode %{
9096 __ cmov_gt(as_Register($dst$$reg), as_Register($src$$reg),
9097 as_Register($dst$$reg), as_Register($src$$reg));
9098 %}
9099
9100 ins_pipe(pipe_class_compare);
9101 %}
9102
9103 instruct maxI_reg_reg(iRegINoSp dst, iRegI src)
9104 %{
9105 match(Set dst (MaxI dst src));
9106
9107 ins_cost(BRANCH_COST + ALU_COST);
9108 format %{"maxI_reg_reg $dst, $dst, $src\t#@maxI_reg_reg\n\t"%}
9109
9110 ins_encode %{
9111 __ cmov_lt(as_Register($dst$$reg), as_Register($src$$reg),
9112 as_Register($dst$$reg), as_Register($src$$reg));
9113 %}
9114
9115 ins_pipe(pipe_class_compare);
9116 %}
9117
9118 // special case for comparing with zero
9119 // n.b. this is selected in preference to the rule above because it
9120 // avoids loading constant 0 into a source register
9121
9122 instruct minI_reg_zero(iRegINoSp dst, immI0 zero)
9123 %{
9124 match(Set dst (MinI dst zero));
9125 match(Set dst (MinI zero dst));
9126
9127 ins_cost(BRANCH_COST + ALU_COST);
9128 format %{"minI_reg_zero $dst, $dst, zr\t#@minI_reg_zero\n\t"%}
9129
9130 ins_encode %{
9131 __ cmov_gt(as_Register($dst$$reg), zr,
9132 as_Register($dst$$reg), zr);
9133 %}
9134
9135 ins_pipe(pipe_class_compare);
9136 %}
9137
9138 instruct maxI_reg_zero(iRegINoSp dst, immI0 zero)
9139 %{
9140 match(Set dst (MaxI dst zero));
9141 match(Set dst (MaxI zero dst));
9142
9143 ins_cost(BRANCH_COST + ALU_COST);
9144 format %{"maxI_reg_zero $dst, $dst, zr\t#@maxI_reg_zero\n\t"%}
9145
9146 ins_encode %{
9147 __ cmov_lt(as_Register($dst$$reg), zr,
9148 as_Register($dst$$reg), zr);
9149 %}
9150
9151 ins_pipe(pipe_class_compare);
9152 %}
9153
9154 instruct minI_rReg(iRegINoSp dst, iRegI src1, iRegI src2)
9155 %{
9156 match(Set dst (MinI src1 src2));
9157
9158 effect(DEF dst, USE src1, USE src2);
9159
9160 ins_cost(BRANCH_COST + ALU_COST * 2);
9161 format %{"minI_rReg $dst, $src1, $src2\t#@minI_rReg\n\t"%}
9162
9163 ins_encode %{
9164 __ mv(as_Register($dst$$reg), as_Register($src1$$reg));
9165 __ cmov_gt(as_Register($src1$$reg), as_Register($src2$$reg),
9166 as_Register($dst$$reg), as_Register($src2$$reg));
9167 %}
9168
9169 ins_pipe(pipe_class_compare);
9170 %}
9171
9172 instruct maxI_rReg(iRegINoSp dst, iRegI src1, iRegI src2)
9173 %{
9174 match(Set dst (MaxI src1 src2));
9175
9176 effect(DEF dst, USE src1, USE src2);
9177
9178 ins_cost(BRANCH_COST + ALU_COST * 2);
9179 format %{"maxI_rReg $dst, $src1, $src2\t#@maxI_rReg\n\t"%}
9180
9181 ins_encode %{
9182 __ mv(as_Register($dst$$reg), as_Register($src1$$reg));
9183 __ cmov_lt(as_Register($src1$$reg), as_Register($src2$$reg),
9184 as_Register($dst$$reg), as_Register($src2$$reg));
9185 %}
9186
9187 ins_pipe(pipe_class_compare);
9188 %}
9189
9190 // ============================================================================
9191 // Branch Instructions
9192 // Direct Branch.
9193 instruct branch(label lbl)
9194 %{
9195 match(Goto);
9196
9197 effect(USE lbl);
9198
9199 ins_cost(BRANCH_COST);
9200 format %{ "j $lbl\t#@branch" %}
9201
9202 ins_encode(riscv_enc_j(lbl));
9203
9204 ins_pipe(pipe_branch);
9205 %}
9206
9207 // ============================================================================
9208 // Compare and Branch Instructions
9209
9210 // Patterns for short (< 12KiB) variants
9211
9212 // Compare flags and branch near instructions.
9213 instruct cmpFlag_branch(cmpOpEqNe cmp, rFlagsReg cr, label lbl) %{
9214 match(If cmp cr);
9215 effect(USE lbl);
9216
9217 ins_cost(BRANCH_COST);
9218 format %{ "b$cmp $cr, zr, $lbl\t#@cmpFlag_branch" %}
9219
9220 ins_encode %{
9221 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($cr$$reg), *($lbl$$label));
9222 %}
9223 ins_pipe(pipe_cmpz_branch);
9224 ins_short_branch(1);
9225 %}
9226
9227 // Compare signed int and branch near instructions
9228 instruct cmpI_branch(cmpOp cmp, iRegI op1, iRegI op2, label lbl)
9229 %{
9230 // Same match rule as `far_cmpI_branch'.
9231 match(If cmp (CmpI op1 op2));
9232
9233 effect(USE lbl);
9234
9235 ins_cost(BRANCH_COST);
9236
9237 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpI_branch" %}
9238
9239 ins_encode %{
9240 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label));
9241 %}
9242
9243 ins_pipe(pipe_cmp_branch);
9244 ins_short_branch(1);
9245 %}
9246
9247 instruct cmpI_loop(cmpOp cmp, iRegI op1, iRegI op2, label lbl)
9248 %{
9249 // Same match rule as `far_cmpI_loop'.
9250 match(CountedLoopEnd cmp (CmpI op1 op2));
9251
9252 effect(USE lbl);
9253
9254 ins_cost(BRANCH_COST);
9255
9256 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpI_loop" %}
9257
9258 ins_encode %{
9259 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label));
9260 %}
9261
9262 ins_pipe(pipe_cmp_branch);
9263 ins_short_branch(1);
9264 %}
9265
9266 // Compare unsigned int and branch near instructions
9267 instruct cmpU_branch(cmpOpU cmp, iRegI op1, iRegI op2, label lbl)
9268 %{
9269 // Same match rule as `far_cmpU_branch'.
9270 match(If cmp (CmpU op1 op2));
9271
9272 effect(USE lbl);
9273
9274 ins_cost(BRANCH_COST);
9275
9276 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpU_branch" %}
9277
9278 ins_encode %{
9279 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9280 as_Register($op2$$reg), *($lbl$$label));
9281 %}
9282
9283 ins_pipe(pipe_cmp_branch);
9284 ins_short_branch(1);
9285 %}
9286
9287 // Compare signed long and branch near instructions
9288 instruct cmpL_branch(cmpOp cmp, iRegL op1, iRegL op2, label lbl)
9289 %{
9290 // Same match rule as `far_cmpL_branch'.
9291 match(If cmp (CmpL op1 op2));
9292
9293 effect(USE lbl);
9294
9295 ins_cost(BRANCH_COST);
9296
9297 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpL_branch" %}
9298
9299 ins_encode %{
9300 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label));
9301 %}
9302
9303 ins_pipe(pipe_cmp_branch);
9304 ins_short_branch(1);
9305 %}
9306
9307 instruct cmpL_loop(cmpOp cmp, iRegL op1, iRegL op2, label lbl)
9308 %{
9309 // Same match rule as `far_cmpL_loop'.
9310 match(CountedLoopEnd cmp (CmpL op1 op2));
9311
9312 effect(USE lbl);
9313
9314 ins_cost(BRANCH_COST);
9315
9316 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpL_loop" %}
9317
9318 ins_encode %{
9319 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label));
9320 %}
9321
9322 ins_pipe(pipe_cmp_branch);
9323 ins_short_branch(1);
9324 %}
9325
9326 // Compare unsigned long and branch near instructions
9327 instruct cmpUL_branch(cmpOpU cmp, iRegL op1, iRegL op2, label lbl)
9328 %{
9329 // Same match rule as `far_cmpUL_branch'.
9330 match(If cmp (CmpUL op1 op2));
9331
9332 effect(USE lbl);
9333
9334 ins_cost(BRANCH_COST);
9335 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpUL_branch" %}
9336
9337 ins_encode %{
9338 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9339 as_Register($op2$$reg), *($lbl$$label));
9340 %}
9341
9342 ins_pipe(pipe_cmp_branch);
9343 ins_short_branch(1);
9344 %}
9345
9346 // Compare pointer and branch near instructions
9347 instruct cmpP_branch(cmpOpU cmp, iRegP op1, iRegP op2, label lbl)
9348 %{
9349 // Same match rule as `far_cmpP_branch'.
9350 match(If cmp (CmpP op1 op2));
9351
9352 effect(USE lbl);
9353
9354 ins_cost(BRANCH_COST);
9355
9356 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpP_branch" %}
9357
9358 ins_encode %{
9359 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9360 as_Register($op2$$reg), *($lbl$$label));
9361 %}
9362
9363 ins_pipe(pipe_cmp_branch);
9364 ins_short_branch(1);
9365 %}
9366
9367 // Compare narrow pointer and branch near instructions
9368 instruct cmpN_branch(cmpOpU cmp, iRegN op1, iRegN op2, label lbl)
9369 %{
9370 // Same match rule as `far_cmpN_branch'.
9371 match(If cmp (CmpN op1 op2));
9372
9373 effect(USE lbl);
9374
9375 ins_cost(BRANCH_COST);
9376
9377 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpN_branch" %}
9378
9379 ins_encode %{
9380 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9381 as_Register($op2$$reg), *($lbl$$label));
9382 %}
9383
9384 ins_pipe(pipe_cmp_branch);
9385 ins_short_branch(1);
9386 %}
9387
9388 // Compare float and branch near instructions
9389 instruct cmpF_branch(cmpOp cmp, fRegF op1, fRegF op2, label lbl)
9390 %{
9391 // Same match rule as `far_cmpF_branch'.
9392 match(If cmp (CmpF op1 op2));
9393
9394 effect(USE lbl);
9395
9396 ins_cost(XFER_COST + BRANCH_COST);
9397 format %{ "float_b$cmp $op1, $op2, $lbl \t#@cmpF_branch"%}
9398
9399 ins_encode %{
9400 __ float_cmp_branch($cmp$$cmpcode, as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg), *($lbl$$label));
9401 %}
9402
9403 ins_pipe(pipe_class_compare);
9404 ins_short_branch(1);
9405 %}
9406
9407 // Compare double and branch near instructions
9408 instruct cmpD_branch(cmpOp cmp, fRegD op1, fRegD op2, label lbl)
9409 %{
9410 // Same match rule as `far_cmpD_branch'.
9411 match(If cmp (CmpD op1 op2));
9412 effect(USE lbl);
9413
9414 ins_cost(XFER_COST + BRANCH_COST);
9415 format %{ "double_b$cmp $op1, $op2, $lbl\t#@cmpD_branch"%}
9416
9417 ins_encode %{
9418 __ float_cmp_branch($cmp$$cmpcode | C2_MacroAssembler::double_branch_mask, as_FloatRegister($op1$$reg),
9419 as_FloatRegister($op2$$reg), *($lbl$$label));
9420 %}
9421
9422 ins_pipe(pipe_class_compare);
9423 ins_short_branch(1);
9424 %}
9425
9426 // Compare signed int with zero and branch near instructions
9427 instruct cmpI_reg_imm0_branch(cmpOp cmp, iRegI op1, immI0 zero, label lbl)
9428 %{
9429 // Same match rule as `far_cmpI_reg_imm0_branch'.
9430 match(If cmp (CmpI op1 zero));
9431
9432 effect(USE op1, USE lbl);
9433
9434 ins_cost(BRANCH_COST);
9435 format %{ "b$cmp $op1, zr, $lbl\t#@cmpI_reg_imm0_branch" %}
9436
9437 ins_encode %{
9438 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label));
9439 %}
9440
9441 ins_pipe(pipe_cmpz_branch);
9442 ins_short_branch(1);
9443 %}
9444
9445 instruct cmpI_reg_imm0_loop(cmpOp cmp, iRegI op1, immI0 zero, label lbl)
9446 %{
9447 // Same match rule as `far_cmpI_reg_imm0_loop'.
9448 match(CountedLoopEnd cmp (CmpI op1 zero));
9449
9450 effect(USE op1, USE lbl);
9451
9452 ins_cost(BRANCH_COST);
9453
9454 format %{ "b$cmp $op1, zr, $lbl\t#@cmpI_reg_imm0_loop" %}
9455
9456 ins_encode %{
9457 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label));
9458 %}
9459
9460 ins_pipe(pipe_cmpz_branch);
9461 ins_short_branch(1);
9462 %}
9463
9464 // Compare unsigned int with zero and branch near instructions
9465 instruct cmpUEqNeLeGt_reg_imm0_branch(cmpOpUEqNeLeGt cmp, iRegI op1, immI0 zero, label lbl)
9466 %{
9467 // Same match rule as `far_cmpUEqNeLeGt_reg_imm0_branch'.
9468 match(If cmp (CmpU op1 zero));
9469
9470 effect(USE op1, USE lbl);
9471
9472 ins_cost(BRANCH_COST);
9473
9474 format %{ "b$cmp $op1, zr, $lbl\t#@cmpUEqNeLeGt_reg_imm0_branch" %}
9475
9476 ins_encode %{
9477 __ enc_cmpUEqNeLeGt_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
9478 %}
9479
9480 ins_pipe(pipe_cmpz_branch);
9481 ins_short_branch(1);
9482 %}
9483
9484 // Compare signed long with zero and branch near instructions
9485 instruct cmpL_reg_imm0_branch(cmpOp cmp, iRegL op1, immL0 zero, label lbl)
9486 %{
9487 // Same match rule as `far_cmpL_reg_imm0_branch'.
9488 match(If cmp (CmpL op1 zero));
9489
9490 effect(USE op1, USE lbl);
9491
9492 ins_cost(BRANCH_COST);
9493
9494 format %{ "b$cmp $op1, zr, $lbl\t#@cmpL_reg_imm0_branch" %}
9495
9496 ins_encode %{
9497 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label));
9498 %}
9499
9500 ins_pipe(pipe_cmpz_branch);
9501 ins_short_branch(1);
9502 %}
9503
9504 instruct cmpL_reg_imm0_loop(cmpOp cmp, iRegL op1, immL0 zero, label lbl)
9505 %{
9506 // Same match rule as `far_cmpL_reg_imm0_loop'.
9507 match(CountedLoopEnd cmp (CmpL op1 zero));
9508
9509 effect(USE op1, USE lbl);
9510
9511 ins_cost(BRANCH_COST);
9512
9513 format %{ "b$cmp $op1, zr, $lbl\t#@cmpL_reg_imm0_loop" %}
9514
9515 ins_encode %{
9516 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label));
9517 %}
9518
9519 ins_pipe(pipe_cmpz_branch);
9520 ins_short_branch(1);
9521 %}
9522
9523 // Compare unsigned long with zero and branch near instructions
9524 instruct cmpULEqNeLeGt_reg_imm0_branch(cmpOpUEqNeLeGt cmp, iRegL op1, immL0 zero, label lbl)
9525 %{
9526 // Same match rule as `far_cmpULEqNeLeGt_reg_imm0_branch'.
9527 match(If cmp (CmpUL op1 zero));
9528
9529 effect(USE op1, USE lbl);
9530
9531 ins_cost(BRANCH_COST);
9532
9533 format %{ "b$cmp $op1, zr, $lbl\t#@cmpULEqNeLeGt_reg_imm0_branch" %}
9534
9535 ins_encode %{
9536 __ enc_cmpUEqNeLeGt_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
9537 %}
9538
9539 ins_pipe(pipe_cmpz_branch);
9540 ins_short_branch(1);
9541 %}
9542
9543 // Compare pointer with zero and branch near instructions
9544 instruct cmpP_imm0_branch(cmpOpEqNe cmp, iRegP op1, immP0 zero, label lbl) %{
9545 // Same match rule as `far_cmpP_reg_imm0_branch'.
9546 match(If cmp (CmpP op1 zero));
9547 effect(USE lbl);
9548
9549 ins_cost(BRANCH_COST);
9550 format %{ "b$cmp $op1, zr, $lbl\t#@cmpP_imm0_branch" %}
9551
9552 ins_encode %{
9553 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
9554 %}
9555
9556 ins_pipe(pipe_cmpz_branch);
9557 ins_short_branch(1);
9558 %}
9559
9560 // Compare narrow pointer with zero and branch near instructions
9561 instruct cmpN_imm0_branch(cmpOpEqNe cmp, iRegN op1, immN0 zero, label lbl) %{
9562 // Same match rule as `far_cmpN_reg_imm0_branch'.
9563 match(If cmp (CmpN op1 zero));
9564 effect(USE lbl);
9565
9566 ins_cost(BRANCH_COST);
9567
9568 format %{ "b$cmp $op1, zr, $lbl\t#@cmpN_imm0_branch" %}
9569
9570 ins_encode %{
9571 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
9572 %}
9573
9574 ins_pipe(pipe_cmpz_branch);
9575 ins_short_branch(1);
9576 %}
9577
9578 // Compare narrow pointer with pointer zero and branch near instructions
9579 instruct cmpP_narrowOop_imm0_branch(cmpOpEqNe cmp, iRegN op1, immP0 zero, label lbl) %{
9580 // Same match rule as `far_cmpP_narrowOop_imm0_branch'.
9581 match(If cmp (CmpP (DecodeN op1) zero));
9582 effect(USE lbl);
9583
9584 ins_cost(BRANCH_COST);
9585 format %{ "b$cmp $op1, zr, $lbl\t#@cmpP_narrowOop_imm0_branch" %}
9586
9587 ins_encode %{
9588 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
9589 %}
9590
9591 ins_pipe(pipe_cmpz_branch);
9592 ins_short_branch(1);
9593 %}
9594
9595 // Patterns for far (20KiB) variants
9596
9597 instruct far_cmpFlag_branch(cmpOp cmp, rFlagsReg cr, label lbl) %{
9598 match(If cmp cr);
9599 effect(USE lbl);
9600
9601 ins_cost(BRANCH_COST);
9602 format %{ "far_b$cmp $cr, zr, $lbl\t#@far_cmpFlag_branch"%}
9603
9604 ins_encode %{
9605 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($cr$$reg), *($lbl$$label), /* is_far */ true);
9606 %}
9607
9608 ins_pipe(pipe_cmpz_branch);
9609 %}
9610
9611 // Compare signed int and branch far instructions
9612 instruct far_cmpI_branch(cmpOp cmp, iRegI op1, iRegI op2, label lbl) %{
9613 match(If cmp (CmpI op1 op2));
9614 effect(USE lbl);
9615
9616 ins_cost(BRANCH_COST * 2);
9617
9618 // the format instruction [far_b$cmp] here is be used as two insructions
9619 // in macroassembler: b$not_cmp(op1, op2, done), j($lbl), bind(done)
9620 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpI_branch" %}
9621
9622 ins_encode %{
9623 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9624 %}
9625
9626 ins_pipe(pipe_cmp_branch);
9627 %}
9628
9629 instruct far_cmpI_loop(cmpOp cmp, iRegI op1, iRegI op2, label lbl) %{
9630 match(CountedLoopEnd cmp (CmpI op1 op2));
9631 effect(USE lbl);
9632
9633 ins_cost(BRANCH_COST * 2);
9634 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpI_loop" %}
9635
9636 ins_encode %{
9637 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9638 %}
9639
9640 ins_pipe(pipe_cmp_branch);
9641 %}
9642
9643 instruct far_cmpU_branch(cmpOpU cmp, iRegI op1, iRegI op2, label lbl) %{
9644 match(If cmp (CmpU op1 op2));
9645 effect(USE lbl);
9646
9647 ins_cost(BRANCH_COST * 2);
9648 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpU_branch" %}
9649
9650 ins_encode %{
9651 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9652 as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9653 %}
9654
9655 ins_pipe(pipe_cmp_branch);
9656 %}
9657
9658 instruct far_cmpL_branch(cmpOp cmp, iRegL op1, iRegL op2, label lbl) %{
9659 match(If cmp (CmpL op1 op2));
9660 effect(USE lbl);
9661
9662 ins_cost(BRANCH_COST * 2);
9663 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpL_branch" %}
9664
9665 ins_encode %{
9666 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9667 %}
9668
9669 ins_pipe(pipe_cmp_branch);
9670 %}
9671
9672 instruct far_cmpLloop(cmpOp cmp, iRegL op1, iRegL op2, label lbl) %{
9673 match(CountedLoopEnd cmp (CmpL op1 op2));
9674 effect(USE lbl);
9675
9676 ins_cost(BRANCH_COST * 2);
9677 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpL_loop" %}
9678
9679 ins_encode %{
9680 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9681 %}
9682
9683 ins_pipe(pipe_cmp_branch);
9684 %}
9685
9686 instruct far_cmpUL_branch(cmpOpU cmp, iRegL op1, iRegL op2, label lbl) %{
9687 match(If cmp (CmpUL op1 op2));
9688 effect(USE lbl);
9689
9690 ins_cost(BRANCH_COST * 2);
9691 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpUL_branch" %}
9692
9693 ins_encode %{
9694 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9695 as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9696 %}
9697
9698 ins_pipe(pipe_cmp_branch);
9699 %}
9700
9701 instruct far_cmpP_branch(cmpOpU cmp, iRegP op1, iRegP op2, label lbl)
9702 %{
9703 match(If cmp (CmpP op1 op2));
9704
9705 effect(USE lbl);
9706
9707 ins_cost(BRANCH_COST * 2);
9708
9709 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpP_branch" %}
9710
9711 ins_encode %{
9712 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9713 as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9714 %}
9715
9716 ins_pipe(pipe_cmp_branch);
9717 %}
9718
9719 instruct far_cmpN_branch(cmpOpU cmp, iRegN op1, iRegN op2, label lbl)
9720 %{
9721 match(If cmp (CmpN op1 op2));
9722
9723 effect(USE lbl);
9724
9725 ins_cost(BRANCH_COST * 2);
9726
9727 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpN_branch" %}
9728
9729 ins_encode %{
9730 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9731 as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9732 %}
9733
9734 ins_pipe(pipe_cmp_branch);
9735 %}
9736
9737 // Float compare and branch instructions
9738 instruct far_cmpF_branch(cmpOp cmp, fRegF op1, fRegF op2, label lbl)
9739 %{
9740 match(If cmp (CmpF op1 op2));
9741
9742 effect(USE lbl);
9743
9744 ins_cost(XFER_COST + BRANCH_COST * 2);
9745 format %{ "far_float_b$cmp $op1, $op2, $lbl\t#@far_cmpF_branch"%}
9746
9747 ins_encode %{
9748 __ float_cmp_branch($cmp$$cmpcode, as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg),
9749 *($lbl$$label), /* is_far */ true);
9750 %}
9751
9752 ins_pipe(pipe_class_compare);
9753 %}
9754
9755 // Double compare and branch instructions
9756 instruct far_cmpD_branch(cmpOp cmp, fRegD op1, fRegD op2, label lbl)
9757 %{
9758 match(If cmp (CmpD op1 op2));
9759 effect(USE lbl);
9760
9761 ins_cost(XFER_COST + BRANCH_COST * 2);
9762 format %{ "far_double_b$cmp $op1, $op2, $lbl\t#@far_cmpD_branch"%}
9763
9764 ins_encode %{
9765 __ float_cmp_branch($cmp$$cmpcode | C2_MacroAssembler::double_branch_mask, as_FloatRegister($op1$$reg),
9766 as_FloatRegister($op2$$reg), *($lbl$$label), /* is_far */ true);
9767 %}
9768
9769 ins_pipe(pipe_class_compare);
9770 %}
9771
9772 instruct far_cmpI_reg_imm0_branch(cmpOp cmp, iRegI op1, immI0 zero, label lbl)
9773 %{
9774 match(If cmp (CmpI op1 zero));
9775
9776 effect(USE op1, USE lbl);
9777
9778 ins_cost(BRANCH_COST * 2);
9779
9780 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpI_reg_imm0_branch" %}
9781
9782 ins_encode %{
9783 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label), /* is_far */ true);
9784 %}
9785
9786 ins_pipe(pipe_cmpz_branch);
9787 %}
9788
9789 instruct far_cmpI_reg_imm0_loop(cmpOp cmp, iRegI op1, immI0 zero, label lbl)
9790 %{
9791 match(CountedLoopEnd cmp (CmpI op1 zero));
9792
9793 effect(USE op1, USE lbl);
9794
9795 ins_cost(BRANCH_COST * 2);
9796
9797 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpI_reg_imm0_loop" %}
9798
9799 ins_encode %{
9800 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label), /* is_far */ true);
9801 %}
9802
9803 ins_pipe(pipe_cmpz_branch);
9804 %}
9805
9806 instruct far_cmpUEqNeLeGt_imm0_branch(cmpOpUEqNeLeGt cmp, iRegI op1, immI0 zero, label lbl)
9807 %{
9808 match(If cmp (CmpU op1 zero));
9809
9810 effect(USE op1, USE lbl);
9811
9812 ins_cost(BRANCH_COST * 2);
9813
9814 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpUEqNeLeGt_imm0_branch" %}
9815
9816 ins_encode %{
9817 __ enc_cmpUEqNeLeGt_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
9818 %}
9819
9820 ins_pipe(pipe_cmpz_branch);
9821 %}
9822
9823 // compare lt/ge unsigned instructs has no short instruct with same match
9824 instruct far_cmpULtGe_reg_imm0_branch(cmpOpULtGe cmp, iRegI op1, immI0 zero, label lbl)
9825 %{
9826 match(If cmp (CmpU op1 zero));
9827
9828 effect(USE op1, USE lbl);
9829
9830 ins_cost(BRANCH_COST);
9831
9832 format %{ "j $lbl if $cmp == ge\t#@far_cmpULtGe_reg_imm0_branch" %}
9833
9834 ins_encode(riscv_enc_far_cmpULtGe_imm0_branch(cmp, op1, lbl));
9835
9836 ins_pipe(pipe_cmpz_branch);
9837 %}
9838
9839 instruct far_cmpL_reg_imm0_branch(cmpOp cmp, iRegL op1, immL0 zero, label lbl)
9840 %{
9841 match(If cmp (CmpL op1 zero));
9842
9843 effect(USE op1, USE lbl);
9844
9845 ins_cost(BRANCH_COST * 2);
9846
9847 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpL_reg_imm0_branch" %}
9848
9849 ins_encode %{
9850 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label), /* is_far */ true);
9851 %}
9852
9853 ins_pipe(pipe_cmpz_branch);
9854 %}
9855
9856 instruct far_cmpL_reg_imm0_loop(cmpOp cmp, iRegL op1, immL0 zero, label lbl)
9857 %{
9858 match(CountedLoopEnd cmp (CmpL op1 zero));
9859
9860 effect(USE op1, USE lbl);
9861
9862 ins_cost(BRANCH_COST * 2);
9863
9864 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpL_reg_imm0_loop" %}
9865
9866 ins_encode %{
9867 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label), /* is_far */ true);
9868 %}
9869
9870 ins_pipe(pipe_cmpz_branch);
9871 %}
9872
9873 instruct far_cmpULEqNeLeGt_reg_imm0_branch(cmpOpUEqNeLeGt cmp, iRegL op1, immL0 zero, label lbl)
9874 %{
9875 match(If cmp (CmpUL op1 zero));
9876
9877 effect(USE op1, USE lbl);
9878
9879 ins_cost(BRANCH_COST * 2);
9880
9881 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpULEqNeLeGt_reg_imm0_branch" %}
9882
9883 ins_encode %{
9884 __ enc_cmpUEqNeLeGt_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
9885 %}
9886
9887 ins_pipe(pipe_cmpz_branch);
9888 %}
9889
9890 // compare lt/ge unsigned instructs has no short instruct with same match
9891 instruct far_cmpULLtGe_reg_imm0_branch(cmpOpULtGe cmp, iRegL op1, immL0 zero, label lbl)
9892 %{
9893 match(If cmp (CmpUL op1 zero));
9894
9895 effect(USE op1, USE lbl);
9896
9897 ins_cost(BRANCH_COST);
9898
9899 format %{ "j $lbl if $cmp == ge\t#@far_cmpULLtGe_reg_imm0_branch" %}
9900
9901 ins_encode(riscv_enc_far_cmpULtGe_imm0_branch(cmp, op1, lbl));
9902
9903 ins_pipe(pipe_cmpz_branch);
9904 %}
9905
9906 instruct far_cmpP_imm0_branch(cmpOpEqNe cmp, iRegP op1, immP0 zero, label lbl) %{
9907 match(If cmp (CmpP op1 zero));
9908 effect(USE lbl);
9909
9910 ins_cost(BRANCH_COST * 2);
9911 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpP_imm0_branch" %}
9912
9913 ins_encode %{
9914 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
9915 %}
9916
9917 ins_pipe(pipe_cmpz_branch);
9918 %}
9919
9920 instruct far_cmpN_imm0_branch(cmpOpEqNe cmp, iRegN op1, immN0 zero, label lbl) %{
9921 match(If cmp (CmpN op1 zero));
9922 effect(USE lbl);
9923
9924 ins_cost(BRANCH_COST * 2);
9925
9926 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpN_imm0_branch" %}
9927
9928 ins_encode %{
9929 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
9930 %}
9931
9932 ins_pipe(pipe_cmpz_branch);
9933 %}
9934
9935 instruct far_cmpP_narrowOop_imm0_branch(cmpOpEqNe cmp, iRegN op1, immP0 zero, label lbl) %{
9936 match(If cmp (CmpP (DecodeN op1) zero));
9937 effect(USE lbl);
9938
9939 ins_cost(BRANCH_COST * 2);
9940 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpP_narrowOop_imm0_branch" %}
9941
9942 ins_encode %{
9943 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
9944 %}
9945
9946 ins_pipe(pipe_cmpz_branch);
9947 %}
9948
9949 // ============================================================================
9950 // Conditional Move Instructions
9951
9952 // --------- CMoveI ---------
9953
9954 instruct cmovI_cmpI(iRegINoSp dst, iRegI src, iRegI op1, iRegI op2, cmpOp cop) %{
9955 match(Set dst (CMoveI (Binary cop (CmpI op1 op2)) (Binary dst src)));
9956 ins_cost(ALU_COST + BRANCH_COST);
9957
9958 format %{
9959 "CMoveI $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpI\n\t"
9960 %}
9961
9962 ins_encode %{
9963 __ enc_cmove($cop$$cmpcode,
9964 as_Register($op1$$reg), as_Register($op2$$reg),
9965 as_Register($dst$$reg), as_Register($src$$reg));
9966 %}
9967
9968 ins_pipe(pipe_class_compare);
9969 %}
9970
9971 instruct cmovI_cmpU(iRegINoSp dst, iRegI src, iRegI op1, iRegI op2, cmpOpU cop) %{
9972 match(Set dst (CMoveI (Binary cop (CmpU op1 op2)) (Binary dst src)));
9973 ins_cost(ALU_COST + BRANCH_COST);
9974
9975 format %{
9976 "CMoveI $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpU\n\t"
9977 %}
9978
9979 ins_encode %{
9980 __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
9981 as_Register($op1$$reg), as_Register($op2$$reg),
9982 as_Register($dst$$reg), as_Register($src$$reg));
9983 %}
9984
9985 ins_pipe(pipe_class_compare);
9986 %}
9987
9988 instruct cmovI_cmpL(iRegINoSp dst, iRegI src, iRegL op1, iRegL op2, cmpOp cop) %{
9989 match(Set dst (CMoveI (Binary cop (CmpL op1 op2)) (Binary dst src)));
9990 ins_cost(ALU_COST + BRANCH_COST);
9991
9992 format %{
9993 "CMoveI $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpL\n\t"
9994 %}
9995
9996 ins_encode %{
9997 __ enc_cmove($cop$$cmpcode,
9998 as_Register($op1$$reg), as_Register($op2$$reg),
9999 as_Register($dst$$reg), as_Register($src$$reg));
10000 %}
10001
10002 ins_pipe(pipe_class_compare);
10003 %}
10004
10005 instruct cmovI_cmpUL(iRegINoSp dst, iRegI src, iRegL op1, iRegL op2, cmpOpU cop) %{
10006 match(Set dst (CMoveI (Binary cop (CmpUL op1 op2)) (Binary dst src)));
10007 ins_cost(ALU_COST + BRANCH_COST);
10008
10009 format %{
10010 "CMoveI $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpUL\n\t"
10011 %}
10012
10013 ins_encode %{
10014 __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10015 as_Register($op1$$reg), as_Register($op2$$reg),
10016 as_Register($dst$$reg), as_Register($src$$reg));
10017 %}
10018
10019 ins_pipe(pipe_class_compare);
10020 %}
10021
10022 instruct cmovI_cmpF(iRegINoSp dst, iRegI src, fRegF op1, fRegF op2, cmpOp cop) %{
10023 match(Set dst (CMoveI (Binary cop (CmpF op1 op2)) (Binary dst src)));
10024 ins_cost(ALU_COST + BRANCH_COST);
10025
10026 format %{
10027 "CMoveI $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpF\n\t"
10028 %}
10029
10030 ins_encode %{
10031 __ enc_cmove_cmp_fp($cop$$cmpcode,
10032 as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg),
10033 as_Register($dst$$reg), as_Register($src$$reg), true /* is_single */);
10034 %}
10035
10036 ins_pipe(pipe_class_compare);
10037 %}
10038
10039 instruct cmovI_cmpD(iRegINoSp dst, iRegI src, fRegD op1, fRegD op2, cmpOp cop) %{
10040 match(Set dst (CMoveI (Binary cop (CmpD op1 op2)) (Binary dst src)));
10041 ins_cost(ALU_COST + BRANCH_COST);
10042
10043 format %{
10044 "CMoveI $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpD\n\t"
10045 %}
10046
10047 ins_encode %{
10048 __ enc_cmove_cmp_fp($cop$$cmpcode | C2_MacroAssembler::double_branch_mask,
10049 as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg),
10050 as_Register($dst$$reg), as_Register($src$$reg), false /* is_single */);
10051 %}
10052
10053 ins_pipe(pipe_class_compare);
10054 %}
10055
10056 instruct cmovI_cmpN(iRegINoSp dst, iRegI src, iRegN op1, iRegN op2, cmpOpU cop) %{
10057 match(Set dst (CMoveI (Binary cop (CmpN op1 op2)) (Binary dst src)));
10058 ins_cost(ALU_COST + BRANCH_COST);
10059
10060 format %{
10061 "CMoveI $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpN\n\t"
10062 %}
10063
10064 ins_encode %{
10065 __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10066 as_Register($op1$$reg), as_Register($op2$$reg),
10067 as_Register($dst$$reg), as_Register($src$$reg));
10068 %}
10069
10070 ins_pipe(pipe_class_compare);
10071 %}
10072
10073 instruct cmovI_cmpP(iRegINoSp dst, iRegI src, iRegP op1, iRegP op2, cmpOpU cop) %{
10074 match(Set dst (CMoveI (Binary cop (CmpP op1 op2)) (Binary dst src)));
10075 ins_cost(ALU_COST + BRANCH_COST);
10076
10077 format %{
10078 "CMoveI $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpP\n\t"
10079 %}
10080
10081 ins_encode %{
10082 __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10083 as_Register($op1$$reg), as_Register($op2$$reg),
10084 as_Register($dst$$reg), as_Register($src$$reg));
10085 %}
10086
10087 ins_pipe(pipe_class_compare);
10088 %}
10089
10090 // --------- CMoveL ---------
10091
10092 instruct cmovL_cmpL(iRegLNoSp dst, iRegL src, iRegL op1, iRegL op2, cmpOp cop) %{
10093 match(Set dst (CMoveL (Binary cop (CmpL op1 op2)) (Binary dst src)));
10094 ins_cost(ALU_COST + BRANCH_COST);
10095
10096 format %{
10097 "CMoveL $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpL\n\t"
10098 %}
10099
10100 ins_encode %{
10101 __ enc_cmove($cop$$cmpcode,
10102 as_Register($op1$$reg), as_Register($op2$$reg),
10103 as_Register($dst$$reg), as_Register($src$$reg));
10104 %}
10105
10106 ins_pipe(pipe_class_compare);
10107 %}
10108
10109 instruct cmovL_cmpUL(iRegLNoSp dst, iRegL src, iRegL op1, iRegL op2, cmpOpU cop) %{
10110 match(Set dst (CMoveL (Binary cop (CmpUL op1 op2)) (Binary dst src)));
10111 ins_cost(ALU_COST + BRANCH_COST);
10112
10113 format %{
10114 "CMoveL $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpUL\n\t"
10115 %}
10116
10117 ins_encode %{
10118 __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10119 as_Register($op1$$reg), as_Register($op2$$reg),
10120 as_Register($dst$$reg), as_Register($src$$reg));
10121 %}
10122
10123 ins_pipe(pipe_class_compare);
10124 %}
10125
10126 instruct cmovL_cmpI(iRegLNoSp dst, iRegL src, iRegI op1, iRegI op2, cmpOp cop) %{
10127 match(Set dst (CMoveL (Binary cop (CmpI op1 op2)) (Binary dst src)));
10128 ins_cost(ALU_COST + BRANCH_COST);
10129
10130 format %{
10131 "CMoveL $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpI\n\t"
10132 %}
10133
10134 ins_encode %{
10135 __ enc_cmove($cop$$cmpcode,
10136 as_Register($op1$$reg), as_Register($op2$$reg),
10137 as_Register($dst$$reg), as_Register($src$$reg));
10138 %}
10139
10140 ins_pipe(pipe_class_compare);
10141 %}
10142
10143 instruct cmovL_cmpU(iRegLNoSp dst, iRegL src, iRegI op1, iRegI op2, cmpOpU cop) %{
10144 match(Set dst (CMoveL (Binary cop (CmpU op1 op2)) (Binary dst src)));
10145 ins_cost(ALU_COST + BRANCH_COST);
10146
10147 format %{
10148 "CMoveL $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpU\n\t"
10149 %}
10150
10151 ins_encode %{
10152 __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10153 as_Register($op1$$reg), as_Register($op2$$reg),
10154 as_Register($dst$$reg), as_Register($src$$reg));
10155 %}
10156
10157 ins_pipe(pipe_class_compare);
10158 %}
10159
10160 instruct cmovL_cmpF(iRegLNoSp dst, iRegL src, fRegF op1, fRegF op2, cmpOp cop) %{
10161 match(Set dst (CMoveL (Binary cop (CmpF op1 op2)) (Binary dst src)));
10162 ins_cost(ALU_COST + BRANCH_COST);
10163
10164 format %{
10165 "CMoveL $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpF\n\t"
10166 %}
10167
10168 ins_encode %{
10169 __ enc_cmove_cmp_fp($cop$$cmpcode,
10170 as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg),
10171 as_Register($dst$$reg), as_Register($src$$reg), true /* is_single */);
10172 %}
10173
10174 ins_pipe(pipe_class_compare);
10175 %}
10176
10177 instruct cmovL_cmpD(iRegLNoSp dst, iRegL src, fRegD op1, fRegD op2, cmpOp cop) %{
10178 match(Set dst (CMoveL (Binary cop (CmpD op1 op2)) (Binary dst src)));
10179 ins_cost(ALU_COST + BRANCH_COST);
10180
10181 format %{
10182 "CMoveL $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpD\n\t"
10183 %}
10184
10185 ins_encode %{
10186 __ enc_cmove_cmp_fp($cop$$cmpcode | C2_MacroAssembler::double_branch_mask,
10187 as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg),
10188 as_Register($dst$$reg), as_Register($src$$reg), false /* is_single */);
10189 %}
10190
10191 ins_pipe(pipe_class_compare);
10192 %}
10193
10194 instruct cmovL_cmpN(iRegLNoSp dst, iRegL src, iRegN op1, iRegN op2, cmpOpU cop) %{
10195 match(Set dst (CMoveL (Binary cop (CmpN op1 op2)) (Binary dst src)));
10196 ins_cost(ALU_COST + BRANCH_COST);
10197
10198 format %{
10199 "CMoveL $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpN\n\t"
10200 %}
10201
10202 ins_encode %{
10203 __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10204 as_Register($op1$$reg), as_Register($op2$$reg),
10205 as_Register($dst$$reg), as_Register($src$$reg));
10206 %}
10207
10208 ins_pipe(pipe_class_compare);
10209 %}
10210
10211 instruct cmovL_cmpP(iRegLNoSp dst, iRegL src, iRegP op1, iRegP op2, cmpOpU cop) %{
10212 match(Set dst (CMoveL (Binary cop (CmpP op1 op2)) (Binary dst src)));
10213 ins_cost(ALU_COST + BRANCH_COST);
10214
10215 format %{
10216 "CMoveL $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpP\n\t"
10217 %}
10218
10219 ins_encode %{
10220 __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10221 as_Register($op1$$reg), as_Register($op2$$reg),
10222 as_Register($dst$$reg), as_Register($src$$reg));
10223 %}
10224
10225 ins_pipe(pipe_class_compare);
10226 %}
10227
10228 // ============================================================================
10229 // Procedure Call/Return Instructions
10230
10231 // Call Java Static Instruction
10232 // Note: If this code changes, the corresponding ret_addr_offset() and
10233 // compute_padding() functions will have to be adjusted.
10234 instruct CallStaticJavaDirect(method meth)
10235 %{
10236 match(CallStaticJava);
10237
10238 effect(USE meth);
10239
10240 ins_cost(BRANCH_COST);
10241
10242 format %{ "CALL,static $meth\t#@CallStaticJavaDirect" %}
10243
10244 ins_encode(riscv_enc_java_static_call(meth),
10245 riscv_enc_call_epilog);
10246
10247 ins_pipe(pipe_class_call);
10248 ins_alignment(4);
10249 %}
10250
10251 // TO HERE
10252
10253 // Call Java Dynamic Instruction
10254 // Note: If this code changes, the corresponding ret_addr_offset() and
10255 // compute_padding() functions will have to be adjusted.
10256 instruct CallDynamicJavaDirect(method meth)
10257 %{
10258 match(CallDynamicJava);
10259
10260 effect(USE meth);
10261
10262 ins_cost(BRANCH_COST + ALU_COST * 5);
10263
10264 format %{ "CALL,dynamic $meth\t#@CallDynamicJavaDirect" %}
10265
10266 ins_encode(riscv_enc_java_dynamic_call(meth),
10267 riscv_enc_call_epilog);
10268
10269 ins_pipe(pipe_class_call);
10270 ins_alignment(4);
10271 %}
10272
10273 // Call Runtime Instruction
10274
10275 instruct CallRuntimeDirect(method meth)
10276 %{
10277 match(CallRuntime);
10278
10279 effect(USE meth);
10280
10281 ins_cost(BRANCH_COST);
10282
10283 format %{ "CALL, runtime $meth\t#@CallRuntimeDirect" %}
10284
10285 ins_encode(riscv_enc_java_to_runtime(meth));
10286
10287 ins_pipe(pipe_class_call);
10288 %}
10289
10290 // Call Runtime Instruction
10291
10292 instruct CallLeafDirect(method meth)
10293 %{
10294 match(CallLeaf);
10295
10296 effect(USE meth);
10297
10298 ins_cost(BRANCH_COST);
10299
10300 format %{ "CALL, runtime leaf $meth\t#@CallLeafDirect" %}
10301
10302 ins_encode(riscv_enc_java_to_runtime(meth));
10303
10304 ins_pipe(pipe_class_call);
10305 %}
10306
10307 // Call Runtime Instruction without safepoint and with vector arguments
10308
10309 instruct CallLeafDirectVector(method meth)
10310 %{
10311 match(CallLeafVector);
10312
10313 effect(USE meth);
10314
10315 ins_cost(BRANCH_COST);
10316
10317 format %{ "CALL, runtime leaf vector $meth" %}
10318
10319 ins_encode(riscv_enc_java_to_runtime(meth));
10320
10321 ins_pipe(pipe_class_call);
10322 %}
10323
10324 // Call Runtime Instruction
10325
10326 instruct CallLeafNoFPDirect(method meth)
10327 %{
10328 match(CallLeafNoFP);
10329
10330 effect(USE meth);
10331
10332 ins_cost(BRANCH_COST);
10333
10334 format %{ "CALL, runtime leaf nofp $meth\t#@CallLeafNoFPDirect" %}
10335
10336 ins_encode(riscv_enc_java_to_runtime(meth));
10337
10338 ins_pipe(pipe_class_call);
10339 %}
10340
10341 // ============================================================================
10342 // Partial Subtype Check
10343 //
10344 // superklass array for an instance of the superklass. Set a hidden
10345 // internal cache on a hit (cache is checked with exposed code in
10346 // gen_subtype_check()). Return zero for a hit. The encoding
10347 // ALSO sets flags.
10348
10349 instruct partialSubtypeCheck(iRegP_R15 result, iRegP_R14 sub, iRegP_R10 super, iRegP_R12 tmp, rFlagsReg cr)
10350 %{
10351 predicate(!UseSecondarySupersTable);
10352 match(Set result (PartialSubtypeCheck sub super));
10353 effect(KILL tmp, KILL cr);
10354
10355 ins_cost(20 * DEFAULT_COST);
10356 format %{ "partialSubtypeCheck $result, $sub, $super\t#@partialSubtypeCheck" %}
10357
10358 ins_encode(riscv_enc_partial_subtype_check(sub, super, tmp, result));
10359
10360 opcode(0x1); // Force zero of result reg on hit
10361
10362 ins_pipe(pipe_class_memory);
10363 %}
10364
10365 // Two versions of partialSubtypeCheck, both used when we need to
10366 // search for a super class in the secondary supers array. The first
10367 // is used when we don't know _a priori_ the class being searched
10368 // for. The second, far more common, is used when we do know: this is
10369 // used for instanceof, checkcast, and any case where C2 can determine
10370 // it by constant propagation.
10371
10372 instruct partialSubtypeCheckVarSuper(iRegP_R14 sub, iRegP_R10 super, iRegP_R15 result,
10373 iRegP_R11 tmpR11, iRegP_R12 tmpR12, iRegP_R13 tmpR13,
10374 iRegP_R16 tmpR16, rFlagsReg cr)
10375 %{
10376 predicate(UseSecondarySupersTable);
10377 match(Set result (PartialSubtypeCheck sub super));
10378 effect(TEMP tmpR11, TEMP tmpR12, TEMP tmpR13, TEMP tmpR16, KILL cr);
10379
10380 ins_cost(10 * DEFAULT_COST); // slightly larger than the next version
10381 format %{ "partialSubtypeCheck $result, $sub, $super" %}
10382
10383 ins_encode %{
10384 __ lookup_secondary_supers_table_var($sub$$Register, $super$$Register, $result$$Register,
10385 $tmpR11$$Register, $tmpR12$$Register, $tmpR13$$Register,
10386 $tmpR16$$Register, nullptr /*L_success*/);
10387 %}
10388
10389 ins_pipe(pipe_class_memory);
10390 %}
10391
10392 instruct partialSubtypeCheckConstSuper(iRegP_R14 sub, iRegP_R10 super_reg, immP super_con, iRegP_R15 result,
10393 iRegP_R11 tmpR11, iRegP_R12 tmpR12, iRegP_R13 tmpR13, iRegP_R16 tmpR16, rFlagsReg cr)
10394 %{
10395 predicate(UseSecondarySupersTable);
10396 match(Set result (PartialSubtypeCheck sub (Binary super_reg super_con)));
10397 effect(TEMP tmpR11, TEMP tmpR12, TEMP tmpR13, TEMP tmpR16, KILL cr);
10398
10399 ins_cost(5 * DEFAULT_COST); // needs to be less than competing nodes
10400 format %{ "partialSubtypeCheck $result, $sub, $super_reg, $super_con" %}
10401
10402 ins_encode %{
10403 bool success = false;
10404 u1 super_klass_slot = ((Klass*)$super_con$$constant)->hash_slot();
10405 if (InlineSecondarySupersTest) {
10406 success = __ lookup_secondary_supers_table_const($sub$$Register, $super_reg$$Register, $result$$Register,
10407 $tmpR11$$Register, $tmpR12$$Register, $tmpR13$$Register,
10408 $tmpR16$$Register, super_klass_slot);
10409 } else {
10410 address call = __ reloc_call(RuntimeAddress(StubRoutines::lookup_secondary_supers_table_stub(super_klass_slot)));
10411 success = (call != nullptr);
10412 }
10413 if (!success) {
10414 ciEnv::current()->record_failure("CodeCache is full");
10415 return;
10416 }
10417 %}
10418
10419 ins_pipe(pipe_class_memory);
10420 %}
10421
10422 instruct string_compareU(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
10423 iRegI_R10 result, iRegP_R28 tmp1, iRegL_R29 tmp2, iRegL_R30 tmp3, rFlagsReg cr)
10424 %{
10425 predicate(!UseRVV && ((StrCompNode *)n)->encoding() == StrIntrinsicNode::UU);
10426 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10427 effect(KILL tmp1, KILL tmp2, KILL tmp3, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
10428
10429 format %{ "String Compare $str1, $cnt1, $str2, $cnt2 -> $result\t#@string_compareU" %}
10430 ins_encode %{
10431 // Count is in 8-bit bytes; non-Compact chars are 16 bits.
10432 __ string_compare($str1$$Register, $str2$$Register,
10433 $cnt1$$Register, $cnt2$$Register, $result$$Register,
10434 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
10435 StrIntrinsicNode::UU);
10436 %}
10437 ins_pipe(pipe_class_memory);
10438 %}
10439
10440 instruct string_compareL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
10441 iRegI_R10 result, iRegP_R28 tmp1, iRegL_R29 tmp2, iRegL_R30 tmp3, rFlagsReg cr)
10442 %{
10443 predicate(!UseRVV && ((StrCompNode *)n)->encoding() == StrIntrinsicNode::LL);
10444 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10445 effect(KILL tmp1, KILL tmp2, KILL tmp3, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
10446
10447 format %{ "String Compare $str1, $cnt1, $str2, $cnt2 -> $result\t#@string_compareL" %}
10448 ins_encode %{
10449 __ string_compare($str1$$Register, $str2$$Register,
10450 $cnt1$$Register, $cnt2$$Register, $result$$Register,
10451 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
10452 StrIntrinsicNode::LL);
10453 %}
10454 ins_pipe(pipe_class_memory);
10455 %}
10456
10457 instruct string_compareUL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
10458 iRegI_R10 result, iRegP_R28 tmp1, iRegL_R29 tmp2, iRegL_R30 tmp3, rFlagsReg cr)
10459 %{
10460 predicate(!UseRVV && ((StrCompNode *)n)->encoding() == StrIntrinsicNode::UL);
10461 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10462 effect(KILL tmp1, KILL tmp2, KILL tmp3, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
10463
10464 format %{"String Compare $str1, $cnt1, $str2, $cnt2 -> $result\t#@string_compareUL" %}
10465 ins_encode %{
10466 __ string_compare($str1$$Register, $str2$$Register,
10467 $cnt1$$Register, $cnt2$$Register, $result$$Register,
10468 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
10469 StrIntrinsicNode::UL);
10470 %}
10471 ins_pipe(pipe_class_memory);
10472 %}
10473
10474 instruct string_compareLU(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
10475 iRegI_R10 result, iRegP_R28 tmp1, iRegL_R29 tmp2, iRegL_R30 tmp3,
10476 rFlagsReg cr)
10477 %{
10478 predicate(!UseRVV && ((StrCompNode *)n)->encoding() == StrIntrinsicNode::LU);
10479 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10480 effect(KILL tmp1, KILL tmp2, KILL tmp3, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
10481
10482 format %{ "String Compare $str1, $cnt1, $str2, $cnt2 -> $result\t#@string_compareLU" %}
10483 ins_encode %{
10484 __ string_compare($str1$$Register, $str2$$Register,
10485 $cnt1$$Register, $cnt2$$Register, $result$$Register,
10486 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
10487 StrIntrinsicNode::LU);
10488 %}
10489 ins_pipe(pipe_class_memory);
10490 %}
10491
10492 instruct string_indexofUU(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
10493 iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3,
10494 iRegINoSp tmp4, iRegINoSp tmp5, iRegINoSp tmp6, rFlagsReg cr)
10495 %{
10496 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU);
10497 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
10498 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, TEMP_DEF result,
10499 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, TEMP tmp6, KILL cr);
10500
10501 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result (UU)" %}
10502 ins_encode %{
10503 __ string_indexof($str1$$Register, $str2$$Register,
10504 $cnt1$$Register, $cnt2$$Register,
10505 $tmp1$$Register, $tmp2$$Register,
10506 $tmp3$$Register, $tmp4$$Register,
10507 $tmp5$$Register, $tmp6$$Register,
10508 $result$$Register, StrIntrinsicNode::UU);
10509 %}
10510 ins_pipe(pipe_class_memory);
10511 %}
10512
10513 instruct string_indexofLL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
10514 iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3,
10515 iRegINoSp tmp4, iRegINoSp tmp5, iRegINoSp tmp6, rFlagsReg cr)
10516 %{
10517 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL);
10518 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
10519 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, TEMP_DEF result,
10520 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, TEMP tmp6, KILL cr);
10521
10522 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result (LL)" %}
10523 ins_encode %{
10524 __ string_indexof($str1$$Register, $str2$$Register,
10525 $cnt1$$Register, $cnt2$$Register,
10526 $tmp1$$Register, $tmp2$$Register,
10527 $tmp3$$Register, $tmp4$$Register,
10528 $tmp5$$Register, $tmp6$$Register,
10529 $result$$Register, StrIntrinsicNode::LL);
10530 %}
10531 ins_pipe(pipe_class_memory);
10532 %}
10533
10534 instruct string_indexofUL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
10535 iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3,
10536 iRegINoSp tmp4, iRegINoSp tmp5, iRegINoSp tmp6, rFlagsReg cr)
10537 %{
10538 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL);
10539 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
10540 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, TEMP_DEF result,
10541 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, TEMP tmp6, KILL cr);
10542 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result (UL)" %}
10543
10544 ins_encode %{
10545 __ string_indexof($str1$$Register, $str2$$Register,
10546 $cnt1$$Register, $cnt2$$Register,
10547 $tmp1$$Register, $tmp2$$Register,
10548 $tmp3$$Register, $tmp4$$Register,
10549 $tmp5$$Register, $tmp6$$Register,
10550 $result$$Register, StrIntrinsicNode::UL);
10551 %}
10552 ins_pipe(pipe_class_memory);
10553 %}
10554
10555 instruct string_indexof_conUU(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2,
10556 immI_le_4 int_cnt2, iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2,
10557 iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
10558 %{
10559 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU);
10560 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
10561 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, TEMP_DEF result,
10562 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
10563
10564 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result (UU)" %}
10565
10566 ins_encode %{
10567 int icnt2 = (int)$int_cnt2$$constant;
10568 __ string_indexof_linearscan($str1$$Register, $str2$$Register,
10569 $cnt1$$Register, zr,
10570 $tmp1$$Register, $tmp2$$Register,
10571 $tmp3$$Register, $tmp4$$Register,
10572 icnt2, $result$$Register, StrIntrinsicNode::UU);
10573 %}
10574 ins_pipe(pipe_class_memory);
10575 %}
10576
10577 instruct string_indexof_conLL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2,
10578 immI_le_4 int_cnt2, iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2,
10579 iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
10580 %{
10581 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL);
10582 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
10583 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, TEMP_DEF result,
10584 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
10585
10586 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result (LL)" %}
10587 ins_encode %{
10588 int icnt2 = (int)$int_cnt2$$constant;
10589 __ string_indexof_linearscan($str1$$Register, $str2$$Register,
10590 $cnt1$$Register, zr,
10591 $tmp1$$Register, $tmp2$$Register,
10592 $tmp3$$Register, $tmp4$$Register,
10593 icnt2, $result$$Register, StrIntrinsicNode::LL);
10594 %}
10595 ins_pipe(pipe_class_memory);
10596 %}
10597
10598 instruct string_indexof_conUL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2,
10599 immI_1 int_cnt2, iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2,
10600 iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
10601 %{
10602 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL);
10603 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
10604 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, TEMP_DEF result,
10605 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
10606
10607 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result (UL)" %}
10608 ins_encode %{
10609 int icnt2 = (int)$int_cnt2$$constant;
10610 __ string_indexof_linearscan($str1$$Register, $str2$$Register,
10611 $cnt1$$Register, zr,
10612 $tmp1$$Register, $tmp2$$Register,
10613 $tmp3$$Register, $tmp4$$Register,
10614 icnt2, $result$$Register, StrIntrinsicNode::UL);
10615 %}
10616 ins_pipe(pipe_class_memory);
10617 %}
10618
10619 instruct stringU_indexof_char(iRegP_R11 str1, iRegI_R12 cnt1, iRegI_R13 ch,
10620 iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2,
10621 iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
10622 %{
10623 match(Set result (StrIndexOfChar (Binary str1 cnt1) ch));
10624 predicate(!UseRVV && (((StrIndexOfCharNode*)n)->encoding() == StrIntrinsicNode::U));
10625 effect(USE_KILL str1, USE_KILL cnt1, USE_KILL ch, TEMP_DEF result,
10626 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
10627
10628 format %{ "StringUTF16 IndexOf char[] $str1, $cnt1, $ch -> $result" %}
10629 ins_encode %{
10630 __ string_indexof_char($str1$$Register, $cnt1$$Register, $ch$$Register,
10631 $result$$Register, $tmp1$$Register, $tmp2$$Register,
10632 $tmp3$$Register, $tmp4$$Register, false /* isU */);
10633 %}
10634 ins_pipe(pipe_class_memory);
10635 %}
10636
10637
10638 instruct stringL_indexof_char(iRegP_R11 str1, iRegI_R12 cnt1, iRegI_R13 ch,
10639 iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2,
10640 iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
10641 %{
10642 match(Set result (StrIndexOfChar (Binary str1 cnt1) ch));
10643 predicate(!UseRVV && (((StrIndexOfCharNode*)n)->encoding() == StrIntrinsicNode::L));
10644 effect(USE_KILL str1, USE_KILL cnt1, USE_KILL ch, TEMP_DEF result,
10645 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
10646
10647 format %{ "StringLatin1 IndexOf char[] $str1, $cnt1, $ch -> $result" %}
10648 ins_encode %{
10649 __ string_indexof_char($str1$$Register, $cnt1$$Register, $ch$$Register,
10650 $result$$Register, $tmp1$$Register, $tmp2$$Register,
10651 $tmp3$$Register, $tmp4$$Register, true /* isL */);
10652 %}
10653 ins_pipe(pipe_class_memory);
10654 %}
10655
10656 // clearing of an array
10657 instruct clearArray_reg_reg(iRegL_R29 cnt, iRegP_R28 base, iRegP_R30 tmp1,
10658 iRegP_R31 tmp2, rFlagsReg cr, Universe dummy)
10659 %{
10660 // temp registers must match the one used in StubGenerator::generate_zero_blocks()
10661 predicate(UseBlockZeroing || !UseRVV);
10662 match(Set dummy (ClearArray cnt base));
10663 effect(USE_KILL cnt, USE_KILL base, TEMP tmp1, TEMP tmp2, KILL cr);
10664
10665 ins_cost(4 * DEFAULT_COST);
10666 format %{ "ClearArray $cnt, $base\t#@clearArray_reg_reg" %}
10667
10668 ins_encode %{
10669 address tpc = __ zero_words($base$$Register, $cnt$$Register);
10670 if (tpc == nullptr) {
10671 ciEnv::current()->record_failure("CodeCache is full");
10672 return;
10673 }
10674 %}
10675
10676 ins_pipe(pipe_class_memory);
10677 %}
10678
10679 instruct clearArray_imm_reg(immL cnt, iRegP_R28 base, Universe dummy, rFlagsReg cr)
10680 %{
10681 predicate(!UseRVV && (uint64_t)n->in(2)->get_long()
10682 < (uint64_t)(BlockZeroingLowLimit >> LogBytesPerWord));
10683 match(Set dummy (ClearArray cnt base));
10684 effect(USE_KILL base, KILL cr);
10685
10686 ins_cost(4 * DEFAULT_COST);
10687 format %{ "ClearArray $cnt, $base\t#@clearArray_imm_reg" %}
10688
10689 ins_encode %{
10690 __ zero_words($base$$Register, (uint64_t)$cnt$$constant);
10691 %}
10692
10693 ins_pipe(pipe_class_memory);
10694 %}
10695
10696 instruct string_equalsL(iRegP_R11 str1, iRegP_R13 str2, iRegI_R14 cnt,
10697 iRegI_R10 result, rFlagsReg cr)
10698 %{
10699 predicate(!UseRVV && ((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::LL);
10700 match(Set result (StrEquals (Binary str1 str2) cnt));
10701 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL cr);
10702
10703 format %{ "String Equals $str1, $str2, $cnt -> $result\t#@string_equalsL" %}
10704 ins_encode %{
10705 // Count is in 8-bit bytes; non-Compact chars are 16 bits.
10706 __ string_equals($str1$$Register, $str2$$Register,
10707 $result$$Register, $cnt$$Register);
10708 %}
10709 ins_pipe(pipe_class_memory);
10710 %}
10711
10712 instruct array_equalsB(iRegP_R11 ary1, iRegP_R12 ary2, iRegI_R10 result,
10713 iRegP_R13 tmp1, iRegP_R14 tmp2, iRegP_R15 tmp3)
10714 %{
10715 predicate(!UseRVV && ((AryEqNode*)n)->encoding() == StrIntrinsicNode::LL);
10716 match(Set result (AryEq ary1 ary2));
10717 effect(USE_KILL ary1, USE_KILL ary2, TEMP tmp1, TEMP tmp2, TEMP tmp3);
10718
10719 format %{ "Array Equals $ary1, $ary2 -> $result\t#@array_equalsB // KILL all" %}
10720 ins_encode %{
10721 __ arrays_equals($ary1$$Register, $ary2$$Register,
10722 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
10723 $result$$Register, 1);
10724 %}
10725 ins_pipe(pipe_class_memory);
10726 %}
10727
10728 instruct array_equalsC(iRegP_R11 ary1, iRegP_R12 ary2, iRegI_R10 result,
10729 iRegP_R13 tmp1, iRegP_R14 tmp2, iRegP_R15 tmp3)
10730 %{
10731 predicate(!UseRVV && ((AryEqNode*)n)->encoding() == StrIntrinsicNode::UU);
10732 match(Set result (AryEq ary1 ary2));
10733 effect(USE_KILL ary1, USE_KILL ary2, TEMP tmp1, TEMP tmp2, TEMP tmp3);
10734
10735 format %{ "Array Equals $ary1, $ary2 -> $result\t#@array_equalsC // KILL all" %}
10736 ins_encode %{
10737 __ arrays_equals($ary1$$Register, $ary2$$Register,
10738 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
10739 $result$$Register, 2);
10740 %}
10741 ins_pipe(pipe_class_memory);
10742 %}
10743
10744 // fast ArraysSupport.vectorizedHashCode
10745 instruct arrays_hashcode(iRegP_R11 ary, iRegI_R12 cnt, iRegI_R10 result, immI basic_type,
10746 iRegLNoSp tmp1, iRegLNoSp tmp2,
10747 iRegLNoSp tmp3, iRegLNoSp tmp4,
10748 iRegLNoSp tmp5, iRegLNoSp tmp6, rFlagsReg cr)
10749 %{
10750 match(Set result (VectorizedHashCode (Binary ary cnt) (Binary result basic_type)));
10751 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, TEMP tmp6,
10752 USE_KILL ary, USE_KILL cnt, USE basic_type, KILL cr);
10753
10754 format %{ "Array HashCode array[] $ary,$cnt,$result,$basic_type -> $result // KILL all" %}
10755 ins_encode %{
10756 __ arrays_hashcode($ary$$Register, $cnt$$Register, $result$$Register,
10757 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
10758 $tmp4$$Register, $tmp5$$Register, $tmp6$$Register,
10759 (BasicType)$basic_type$$constant);
10760 %}
10761 ins_pipe(pipe_class_memory);
10762 %}
10763
10764 // ============================================================================
10765 // Safepoint Instructions
10766
10767 instruct safePoint(iRegP poll)
10768 %{
10769 match(SafePoint poll);
10770
10771 ins_cost(2 * LOAD_COST);
10772 format %{
10773 "lwu zr, [$poll]\t# Safepoint: poll for GC, #@safePoint"
10774 %}
10775 ins_encode %{
10776 __ read_polling_page(as_Register($poll$$reg), 0, relocInfo::poll_type);
10777 %}
10778 ins_pipe(pipe_serial); // ins_pipe(iload_reg_mem);
10779 %}
10780
10781 // ============================================================================
10782 // This name is KNOWN by the ADLC and cannot be changed.
10783 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
10784 // for this guy.
10785 instruct tlsLoadP(javaThread_RegP dst)
10786 %{
10787 match(Set dst (ThreadLocal));
10788
10789 ins_cost(0);
10790
10791 format %{ " -- \t// $dst=Thread::current(), empty, #@tlsLoadP" %}
10792
10793 size(0);
10794
10795 ins_encode( /*empty*/ );
10796
10797 ins_pipe(pipe_class_empty);
10798 %}
10799
10800 // inlined locking and unlocking
10801 // using t1 as the 'flag' register to bridge the BoolNode producers and consumers
10802 instruct cmpFastLock(rFlagsReg cr, iRegP object, iRegP box,
10803 iRegPNoSp tmp1, iRegPNoSp tmp2, iRegPNoSp tmp3, iRegPNoSp tmp4)
10804 %{
10805 predicate(LockingMode != LM_LIGHTWEIGHT);
10806 match(Set cr (FastLock object box));
10807 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4);
10808
10809 ins_cost(10 * DEFAULT_COST);
10810 format %{ "fastlock $object,$box\t! kills $tmp1,$tmp2,$tmp3,$tmp4 #@cmpFastLock" %}
10811
10812 ins_encode %{
10813 __ fast_lock($object$$Register, $box$$Register,
10814 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register);
10815 %}
10816
10817 ins_pipe(pipe_serial);
10818 %}
10819
10820 // using t1 as the 'flag' register to bridge the BoolNode producers and consumers
10821 instruct cmpFastUnlock(rFlagsReg cr, iRegP object, iRegP box, iRegPNoSp tmp1, iRegPNoSp tmp2)
10822 %{
10823 predicate(LockingMode != LM_LIGHTWEIGHT);
10824 match(Set cr (FastUnlock object box));
10825 effect(TEMP tmp1, TEMP tmp2);
10826
10827 ins_cost(10 * DEFAULT_COST);
10828 format %{ "fastunlock $object,$box\t! kills $tmp1, $tmp2, #@cmpFastUnlock" %}
10829
10830 ins_encode %{
10831 __ fast_unlock($object$$Register, $box$$Register, $tmp1$$Register, $tmp2$$Register);
10832 %}
10833
10834 ins_pipe(pipe_serial);
10835 %}
10836
10837 instruct cmpFastLockLightweight(rFlagsReg cr, iRegP object, iRegP box,
10838 iRegPNoSp tmp1, iRegPNoSp tmp2, iRegPNoSp tmp3, iRegPNoSp tmp4)
10839 %{
10840 predicate(LockingMode == LM_LIGHTWEIGHT);
10841 match(Set cr (FastLock object box));
10842 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4);
10843
10844 ins_cost(10 * DEFAULT_COST);
10845 format %{ "fastlock $object,$box\t! kills $tmp1,$tmp2,$tmp3,$tmp4 #@cmpFastLockLightweight" %}
10846
10847 ins_encode %{
10848 __ fast_lock_lightweight($object$$Register, $box$$Register,
10849 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register);
10850 %}
10851
10852 ins_pipe(pipe_serial);
10853 %}
10854
10855 instruct cmpFastUnlockLightweight(rFlagsReg cr, iRegP object, iRegP box,
10856 iRegPNoSp tmp1, iRegPNoSp tmp2, iRegPNoSp tmp3)
10857 %{
10858 predicate(LockingMode == LM_LIGHTWEIGHT);
10859 match(Set cr (FastUnlock object box));
10860 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3);
10861
10862 ins_cost(10 * DEFAULT_COST);
10863 format %{ "fastunlock $object,$box\t! kills $tmp1,$tmp2,$tmp3 #@cmpFastUnlockLightweight" %}
10864
10865 ins_encode %{
10866 __ fast_unlock_lightweight($object$$Register, $box$$Register,
10867 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
10868 %}
10869
10870 ins_pipe(pipe_serial);
10871 %}
10872
10873 // Tail Call; Jump from runtime stub to Java code.
10874 // Also known as an 'interprocedural jump'.
10875 // Target of jump will eventually return to caller.
10876 // TailJump below removes the return address.
10877 // Don't use fp for 'jump_target' because a MachEpilogNode has already been
10878 // emitted just above the TailCall which has reset fp to the caller state.
10879 instruct TailCalljmpInd(iRegPNoSpNoFp jump_target, inline_cache_RegP method_oop)
10880 %{
10881 match(TailCall jump_target method_oop);
10882
10883 ins_cost(BRANCH_COST);
10884
10885 format %{ "jalr $jump_target\t# $method_oop holds method oop, #@TailCalljmpInd." %}
10886
10887 ins_encode(riscv_enc_tail_call(jump_target));
10888
10889 ins_pipe(pipe_class_call);
10890 %}
10891
10892 instruct TailjmpInd(iRegPNoSpNoFp jump_target, iRegP_R10 ex_oop)
10893 %{
10894 match(TailJump jump_target ex_oop);
10895
10896 ins_cost(ALU_COST + BRANCH_COST);
10897
10898 format %{ "jalr $jump_target\t# $ex_oop holds exception oop, #@TailjmpInd." %}
10899
10900 ins_encode(riscv_enc_tail_jmp(jump_target));
10901
10902 ins_pipe(pipe_class_call);
10903 %}
10904
10905 // Forward exception.
10906 instruct ForwardExceptionjmp()
10907 %{
10908 match(ForwardException);
10909
10910 ins_cost(BRANCH_COST);
10911
10912 format %{ "j forward_exception_stub\t#@ForwardException" %}
10913
10914 ins_encode %{
10915 __ far_jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
10916 %}
10917
10918 ins_pipe(pipe_class_call);
10919 %}
10920
10921 // Create exception oop: created by stack-crawling runtime code.
10922 // Created exception is now available to this handler, and is setup
10923 // just prior to jumping to this handler. No code emitted.
10924 instruct CreateException(iRegP_R10 ex_oop)
10925 %{
10926 match(Set ex_oop (CreateEx));
10927
10928 ins_cost(0);
10929 format %{ " -- \t// exception oop; no code emitted, #@CreateException" %}
10930
10931 size(0);
10932
10933 ins_encode( /*empty*/ );
10934
10935 ins_pipe(pipe_class_empty);
10936 %}
10937
10938 // Rethrow exception: The exception oop will come in the first
10939 // argument position. Then JUMP (not call) to the rethrow stub code.
10940 instruct RethrowException()
10941 %{
10942 match(Rethrow);
10943
10944 ins_cost(BRANCH_COST);
10945
10946 format %{ "j rethrow_stub\t#@RethrowException" %}
10947
10948 ins_encode(riscv_enc_rethrow());
10949
10950 ins_pipe(pipe_class_call);
10951 %}
10952
10953 // Return Instruction
10954 // epilog node loads ret address into ra as part of frame pop
10955 instruct Ret()
10956 %{
10957 match(Return);
10958
10959 ins_cost(BRANCH_COST);
10960 format %{ "ret\t// return register, #@Ret" %}
10961
10962 ins_encode(riscv_enc_ret());
10963
10964 ins_pipe(pipe_branch);
10965 %}
10966
10967 // Die now.
10968 instruct ShouldNotReachHere() %{
10969 match(Halt);
10970
10971 ins_cost(BRANCH_COST);
10972
10973 format %{ "#@ShouldNotReachHere" %}
10974
10975 ins_encode %{
10976 if (is_reachable()) {
10977 const char* str = __ code_string(_halt_reason);
10978 __ stop(str);
10979 }
10980 %}
10981
10982 ins_pipe(pipe_class_default);
10983 %}
10984
10985
10986 //----------PEEPHOLE RULES-----------------------------------------------------
10987 // These must follow all instruction definitions as they use the names
10988 // defined in the instructions definitions.
10989 //
10990 // peepmatch ( root_instr_name [preceding_instruction]* );
10991 //
10992 // peepconstraint %{
10993 // (instruction_number.operand_name relational_op instruction_number.operand_name
10994 // [, ...] );
10995 // // instruction numbers are zero-based using left to right order in peepmatch
10996 //
10997 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
10998 // // provide an instruction_number.operand_name for each operand that appears
10999 // // in the replacement instruction's match rule
11000 //
11001 // ---------VM FLAGS---------------------------------------------------------
11002 //
11003 // All peephole optimizations can be turned off using -XX:-OptoPeephole
11004 //
11005 // Each peephole rule is given an identifying number starting with zero and
11006 // increasing by one in the order seen by the parser. An individual peephole
11007 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
11008 // on the command-line.
11009 //
11010 // ---------CURRENT LIMITATIONS----------------------------------------------
11011 //
11012 // Only match adjacent instructions in same basic block
11013 // Only equality constraints
11014 // Only constraints between operands, not (0.dest_reg == RAX_enc)
11015 // Only one replacement instruction
11016 //
11017 //----------SMARTSPILL RULES---------------------------------------------------
11018 // These must follow all instruction definitions as they use the names
11019 // defined in the instructions definitions.
11020
11021 // Local Variables:
11022 // mode: c++
11023 // End: