1 //
2 // Copyright (c) 2003, 2024, Oracle and/or its affiliates. All rights reserved.
3 // Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
4 // Copyright (c) 2020, 2024, Huawei Technologies Co., Ltd. All rights reserved.
5 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
6 //
7 // This code is free software; you can redistribute it and/or modify it
8 // under the terms of the GNU General Public License version 2 only, as
9 // published by the Free Software Foundation.
10 //
11 // This code is distributed in the hope that it will be useful, but WITHOUT
12 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 // version 2 for more details (a copy is included in the LICENSE file that
15 // accompanied this code).
16 //
17 // You should have received a copy of the GNU General Public License version
18 // 2 along with this work; if not, write to the Free Software Foundation,
19 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
20 //
21 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
22 // or visit www.oracle.com if you need additional information or have any
23 // questions.
24 //
25 //
26
27 // RISCV Architecture Description File
28
29 //----------REGISTER DEFINITION BLOCK------------------------------------------
30 // This information is used by the matcher and the register allocator to
31 // describe individual registers and classes of registers within the target
32 // architecture.
33
34 register %{
35 //----------Architecture Description Register Definitions----------------------
36 // General Registers
37 // "reg_def" name ( register save type, C convention save type,
38 // ideal register type, encoding );
39 // Register Save Types:
40 //
41 // NS = No-Save: The register allocator assumes that these registers
42 // can be used without saving upon entry to the method, &
43 // that they do not need to be saved at call sites.
44 //
45 // SOC = Save-On-Call: The register allocator assumes that these registers
46 // can be used without saving upon entry to the method,
47 // but that they must be saved at call sites.
48 //
49 // SOE = Save-On-Entry: The register allocator assumes that these registers
50 // must be saved before using them upon entry to the
51 // method, but they do not need to be saved at call
52 // sites.
53 //
54 // AS = Always-Save: The register allocator assumes that these registers
55 // must be saved before using them upon entry to the
56 // method, & that they must be saved at call sites.
57 //
58 // Ideal Register Type is used to determine how to save & restore a
59 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
60 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
61 //
62 // The encoding number is the actual bit-pattern placed into the opcodes.
63
64 // We must define the 64 bit int registers in two 32 bit halves, the
65 // real lower register and a virtual upper half register. upper halves
66 // are used by the register allocator but are not actually supplied as
67 // operands to memory ops.
68 //
69 // follow the C1 compiler in making registers
70 //
71 // x7, x9-x17, x27-x31 volatile (caller save)
72 // x0-x4, x8, x23 system (no save, no allocate)
73 // x5-x6 non-allocatable (so we can use them as temporary regs)
74
75 //
76 // as regards Java usage. we don't use any callee save registers
77 // because this makes it difficult to de-optimise a frame (see comment
78 // in x86 implementation of Deoptimization::unwind_callee_save_values)
79 //
80
81 // General Registers
82
83 reg_def R0 ( NS, NS, Op_RegI, 0, x0->as_VMReg() ); // zr
84 reg_def R0_H ( NS, NS, Op_RegI, 0, x0->as_VMReg()->next() );
85 reg_def R1 ( NS, SOC, Op_RegI, 1, x1->as_VMReg() ); // ra
86 reg_def R1_H ( NS, SOC, Op_RegI, 1, x1->as_VMReg()->next() );
87 reg_def R2 ( NS, NS, Op_RegI, 2, x2->as_VMReg() ); // sp
88 reg_def R2_H ( NS, NS, Op_RegI, 2, x2->as_VMReg()->next() );
89 reg_def R3 ( NS, NS, Op_RegI, 3, x3->as_VMReg() ); // gp
90 reg_def R3_H ( NS, NS, Op_RegI, 3, x3->as_VMReg()->next() );
91 reg_def R4 ( NS, NS, Op_RegI, 4, x4->as_VMReg() ); // tp
92 reg_def R4_H ( NS, NS, Op_RegI, 4, x4->as_VMReg()->next() );
93 reg_def R7 ( SOC, SOC, Op_RegI, 7, x7->as_VMReg() );
94 reg_def R7_H ( SOC, SOC, Op_RegI, 7, x7->as_VMReg()->next() );
95 reg_def R8 ( NS, SOE, Op_RegI, 8, x8->as_VMReg() ); // fp
96 reg_def R8_H ( NS, SOE, Op_RegI, 8, x8->as_VMReg()->next() );
97 reg_def R9 ( SOC, SOE, Op_RegI, 9, x9->as_VMReg() );
98 reg_def R9_H ( SOC, SOE, Op_RegI, 9, x9->as_VMReg()->next() );
99 reg_def R10 ( SOC, SOC, Op_RegI, 10, x10->as_VMReg() );
100 reg_def R10_H ( SOC, SOC, Op_RegI, 10, x10->as_VMReg()->next());
101 reg_def R11 ( SOC, SOC, Op_RegI, 11, x11->as_VMReg() );
102 reg_def R11_H ( SOC, SOC, Op_RegI, 11, x11->as_VMReg()->next());
103 reg_def R12 ( SOC, SOC, Op_RegI, 12, x12->as_VMReg() );
104 reg_def R12_H ( SOC, SOC, Op_RegI, 12, x12->as_VMReg()->next());
105 reg_def R13 ( SOC, SOC, Op_RegI, 13, x13->as_VMReg() );
106 reg_def R13_H ( SOC, SOC, Op_RegI, 13, x13->as_VMReg()->next());
107 reg_def R14 ( SOC, SOC, Op_RegI, 14, x14->as_VMReg() );
108 reg_def R14_H ( SOC, SOC, Op_RegI, 14, x14->as_VMReg()->next());
109 reg_def R15 ( SOC, SOC, Op_RegI, 15, x15->as_VMReg() );
110 reg_def R15_H ( SOC, SOC, Op_RegI, 15, x15->as_VMReg()->next());
111 reg_def R16 ( SOC, SOC, Op_RegI, 16, x16->as_VMReg() );
112 reg_def R16_H ( SOC, SOC, Op_RegI, 16, x16->as_VMReg()->next());
113 reg_def R17 ( SOC, SOC, Op_RegI, 17, x17->as_VMReg() );
114 reg_def R17_H ( SOC, SOC, Op_RegI, 17, x17->as_VMReg()->next());
115 reg_def R18 ( SOC, SOE, Op_RegI, 18, x18->as_VMReg() );
116 reg_def R18_H ( SOC, SOE, Op_RegI, 18, x18->as_VMReg()->next());
117 reg_def R19 ( SOC, SOE, Op_RegI, 19, x19->as_VMReg() );
118 reg_def R19_H ( SOC, SOE, Op_RegI, 19, x19->as_VMReg()->next());
119 reg_def R20 ( SOC, SOE, Op_RegI, 20, x20->as_VMReg() ); // caller esp
120 reg_def R20_H ( SOC, SOE, Op_RegI, 20, x20->as_VMReg()->next());
121 reg_def R21 ( SOC, SOE, Op_RegI, 21, x21->as_VMReg() );
122 reg_def R21_H ( SOC, SOE, Op_RegI, 21, x21->as_VMReg()->next());
123 reg_def R22 ( SOC, SOE, Op_RegI, 22, x22->as_VMReg() );
124 reg_def R22_H ( SOC, SOE, Op_RegI, 22, x22->as_VMReg()->next());
125 reg_def R23 ( NS, SOE, Op_RegI, 23, x23->as_VMReg() ); // java thread
126 reg_def R23_H ( NS, SOE, Op_RegI, 23, x23->as_VMReg()->next());
127 reg_def R24 ( SOC, SOE, Op_RegI, 24, x24->as_VMReg() );
128 reg_def R24_H ( SOC, SOE, Op_RegI, 24, x24->as_VMReg()->next());
129 reg_def R25 ( SOC, SOE, Op_RegI, 25, x25->as_VMReg() );
130 reg_def R25_H ( SOC, SOE, Op_RegI, 25, x25->as_VMReg()->next());
131 reg_def R26 ( SOC, SOE, Op_RegI, 26, x26->as_VMReg() );
132 reg_def R26_H ( SOC, SOE, Op_RegI, 26, x26->as_VMReg()->next());
133 reg_def R27 ( SOC, SOE, Op_RegI, 27, x27->as_VMReg() ); // heapbase
134 reg_def R27_H ( SOC, SOE, Op_RegI, 27, x27->as_VMReg()->next());
135 reg_def R28 ( SOC, SOC, Op_RegI, 28, x28->as_VMReg() );
136 reg_def R28_H ( SOC, SOC, Op_RegI, 28, x28->as_VMReg()->next());
137 reg_def R29 ( SOC, SOC, Op_RegI, 29, x29->as_VMReg() );
138 reg_def R29_H ( SOC, SOC, Op_RegI, 29, x29->as_VMReg()->next());
139 reg_def R30 ( SOC, SOC, Op_RegI, 30, x30->as_VMReg() );
140 reg_def R30_H ( SOC, SOC, Op_RegI, 30, x30->as_VMReg()->next());
141 reg_def R31 ( SOC, SOC, Op_RegI, 31, x31->as_VMReg() );
142 reg_def R31_H ( SOC, SOC, Op_RegI, 31, x31->as_VMReg()->next());
143
144 // ----------------------------
145 // Float/Double Registers
146 // ----------------------------
147
148 // Double Registers
149
150 // The rules of ADL require that double registers be defined in pairs.
151 // Each pair must be two 32-bit values, but not necessarily a pair of
152 // single float registers. In each pair, ADLC-assigned register numbers
153 // must be adjacent, with the lower number even. Finally, when the
154 // CPU stores such a register pair to memory, the word associated with
155 // the lower ADLC-assigned number must be stored to the lower address.
156
157 // RISCV has 32 floating-point registers. Each can store a single
158 // or double precision floating-point value.
159
160 // for Java use float registers f0-f31 are always save on call whereas
161 // the platform ABI treats f8-f9 and f18-f27 as callee save). Other
162 // float registers are SOC as per the platform spec
163
164 reg_def F0 ( SOC, SOC, Op_RegF, 0, f0->as_VMReg() );
165 reg_def F0_H ( SOC, SOC, Op_RegF, 0, f0->as_VMReg()->next() );
166 reg_def F1 ( SOC, SOC, Op_RegF, 1, f1->as_VMReg() );
167 reg_def F1_H ( SOC, SOC, Op_RegF, 1, f1->as_VMReg()->next() );
168 reg_def F2 ( SOC, SOC, Op_RegF, 2, f2->as_VMReg() );
169 reg_def F2_H ( SOC, SOC, Op_RegF, 2, f2->as_VMReg()->next() );
170 reg_def F3 ( SOC, SOC, Op_RegF, 3, f3->as_VMReg() );
171 reg_def F3_H ( SOC, SOC, Op_RegF, 3, f3->as_VMReg()->next() );
172 reg_def F4 ( SOC, SOC, Op_RegF, 4, f4->as_VMReg() );
173 reg_def F4_H ( SOC, SOC, Op_RegF, 4, f4->as_VMReg()->next() );
174 reg_def F5 ( SOC, SOC, Op_RegF, 5, f5->as_VMReg() );
175 reg_def F5_H ( SOC, SOC, Op_RegF, 5, f5->as_VMReg()->next() );
176 reg_def F6 ( SOC, SOC, Op_RegF, 6, f6->as_VMReg() );
177 reg_def F6_H ( SOC, SOC, Op_RegF, 6, f6->as_VMReg()->next() );
178 reg_def F7 ( SOC, SOC, Op_RegF, 7, f7->as_VMReg() );
179 reg_def F7_H ( SOC, SOC, Op_RegF, 7, f7->as_VMReg()->next() );
180 reg_def F8 ( SOC, SOE, Op_RegF, 8, f8->as_VMReg() );
181 reg_def F8_H ( SOC, SOE, Op_RegF, 8, f8->as_VMReg()->next() );
182 reg_def F9 ( SOC, SOE, Op_RegF, 9, f9->as_VMReg() );
183 reg_def F9_H ( SOC, SOE, Op_RegF, 9, f9->as_VMReg()->next() );
184 reg_def F10 ( SOC, SOC, Op_RegF, 10, f10->as_VMReg() );
185 reg_def F10_H ( SOC, SOC, Op_RegF, 10, f10->as_VMReg()->next() );
186 reg_def F11 ( SOC, SOC, Op_RegF, 11, f11->as_VMReg() );
187 reg_def F11_H ( SOC, SOC, Op_RegF, 11, f11->as_VMReg()->next() );
188 reg_def F12 ( SOC, SOC, Op_RegF, 12, f12->as_VMReg() );
189 reg_def F12_H ( SOC, SOC, Op_RegF, 12, f12->as_VMReg()->next() );
190 reg_def F13 ( SOC, SOC, Op_RegF, 13, f13->as_VMReg() );
191 reg_def F13_H ( SOC, SOC, Op_RegF, 13, f13->as_VMReg()->next() );
192 reg_def F14 ( SOC, SOC, Op_RegF, 14, f14->as_VMReg() );
193 reg_def F14_H ( SOC, SOC, Op_RegF, 14, f14->as_VMReg()->next() );
194 reg_def F15 ( SOC, SOC, Op_RegF, 15, f15->as_VMReg() );
195 reg_def F15_H ( SOC, SOC, Op_RegF, 15, f15->as_VMReg()->next() );
196 reg_def F16 ( SOC, SOC, Op_RegF, 16, f16->as_VMReg() );
197 reg_def F16_H ( SOC, SOC, Op_RegF, 16, f16->as_VMReg()->next() );
198 reg_def F17 ( SOC, SOC, Op_RegF, 17, f17->as_VMReg() );
199 reg_def F17_H ( SOC, SOC, Op_RegF, 17, f17->as_VMReg()->next() );
200 reg_def F18 ( SOC, SOE, Op_RegF, 18, f18->as_VMReg() );
201 reg_def F18_H ( SOC, SOE, Op_RegF, 18, f18->as_VMReg()->next() );
202 reg_def F19 ( SOC, SOE, Op_RegF, 19, f19->as_VMReg() );
203 reg_def F19_H ( SOC, SOE, Op_RegF, 19, f19->as_VMReg()->next() );
204 reg_def F20 ( SOC, SOE, Op_RegF, 20, f20->as_VMReg() );
205 reg_def F20_H ( SOC, SOE, Op_RegF, 20, f20->as_VMReg()->next() );
206 reg_def F21 ( SOC, SOE, Op_RegF, 21, f21->as_VMReg() );
207 reg_def F21_H ( SOC, SOE, Op_RegF, 21, f21->as_VMReg()->next() );
208 reg_def F22 ( SOC, SOE, Op_RegF, 22, f22->as_VMReg() );
209 reg_def F22_H ( SOC, SOE, Op_RegF, 22, f22->as_VMReg()->next() );
210 reg_def F23 ( SOC, SOE, Op_RegF, 23, f23->as_VMReg() );
211 reg_def F23_H ( SOC, SOE, Op_RegF, 23, f23->as_VMReg()->next() );
212 reg_def F24 ( SOC, SOE, Op_RegF, 24, f24->as_VMReg() );
213 reg_def F24_H ( SOC, SOE, Op_RegF, 24, f24->as_VMReg()->next() );
214 reg_def F25 ( SOC, SOE, Op_RegF, 25, f25->as_VMReg() );
215 reg_def F25_H ( SOC, SOE, Op_RegF, 25, f25->as_VMReg()->next() );
216 reg_def F26 ( SOC, SOE, Op_RegF, 26, f26->as_VMReg() );
217 reg_def F26_H ( SOC, SOE, Op_RegF, 26, f26->as_VMReg()->next() );
218 reg_def F27 ( SOC, SOE, Op_RegF, 27, f27->as_VMReg() );
219 reg_def F27_H ( SOC, SOE, Op_RegF, 27, f27->as_VMReg()->next() );
220 reg_def F28 ( SOC, SOC, Op_RegF, 28, f28->as_VMReg() );
221 reg_def F28_H ( SOC, SOC, Op_RegF, 28, f28->as_VMReg()->next() );
222 reg_def F29 ( SOC, SOC, Op_RegF, 29, f29->as_VMReg() );
223 reg_def F29_H ( SOC, SOC, Op_RegF, 29, f29->as_VMReg()->next() );
224 reg_def F30 ( SOC, SOC, Op_RegF, 30, f30->as_VMReg() );
225 reg_def F30_H ( SOC, SOC, Op_RegF, 30, f30->as_VMReg()->next() );
226 reg_def F31 ( SOC, SOC, Op_RegF, 31, f31->as_VMReg() );
227 reg_def F31_H ( SOC, SOC, Op_RegF, 31, f31->as_VMReg()->next() );
228
229 // ----------------------------
230 // Vector Registers
231 // ----------------------------
232
233 // For RVV vector registers, we simply extend vector register size to 4
234 // 'logical' slots. This is nominally 128 bits but it actually covers
235 // all possible 'physical' RVV vector register lengths from 128 ~ 1024
236 // bits. The 'physical' RVV vector register length is detected during
237 // startup, so the register allocator is able to identify the correct
238 // number of bytes needed for an RVV spill/unspill.
239
240 reg_def V0 ( SOC, SOC, Op_VecA, 0, v0->as_VMReg() );
241 reg_def V0_H ( SOC, SOC, Op_VecA, 0, v0->as_VMReg()->next() );
242 reg_def V0_J ( SOC, SOC, Op_VecA, 0, v0->as_VMReg()->next(2) );
243 reg_def V0_K ( SOC, SOC, Op_VecA, 0, v0->as_VMReg()->next(3) );
244
245 reg_def V1 ( SOC, SOC, Op_VecA, 1, v1->as_VMReg() );
246 reg_def V1_H ( SOC, SOC, Op_VecA, 1, v1->as_VMReg()->next() );
247 reg_def V1_J ( SOC, SOC, Op_VecA, 1, v1->as_VMReg()->next(2) );
248 reg_def V1_K ( SOC, SOC, Op_VecA, 1, v1->as_VMReg()->next(3) );
249
250 reg_def V2 ( SOC, SOC, Op_VecA, 2, v2->as_VMReg() );
251 reg_def V2_H ( SOC, SOC, Op_VecA, 2, v2->as_VMReg()->next() );
252 reg_def V2_J ( SOC, SOC, Op_VecA, 2, v2->as_VMReg()->next(2) );
253 reg_def V2_K ( SOC, SOC, Op_VecA, 2, v2->as_VMReg()->next(3) );
254
255 reg_def V3 ( SOC, SOC, Op_VecA, 3, v3->as_VMReg() );
256 reg_def V3_H ( SOC, SOC, Op_VecA, 3, v3->as_VMReg()->next() );
257 reg_def V3_J ( SOC, SOC, Op_VecA, 3, v3->as_VMReg()->next(2) );
258 reg_def V3_K ( SOC, SOC, Op_VecA, 3, v3->as_VMReg()->next(3) );
259
260 reg_def V4 ( SOC, SOC, Op_VecA, 4, v4->as_VMReg() );
261 reg_def V4_H ( SOC, SOC, Op_VecA, 4, v4->as_VMReg()->next() );
262 reg_def V4_J ( SOC, SOC, Op_VecA, 4, v4->as_VMReg()->next(2) );
263 reg_def V4_K ( SOC, SOC, Op_VecA, 4, v4->as_VMReg()->next(3) );
264
265 reg_def V5 ( SOC, SOC, Op_VecA, 5, v5->as_VMReg() );
266 reg_def V5_H ( SOC, SOC, Op_VecA, 5, v5->as_VMReg()->next() );
267 reg_def V5_J ( SOC, SOC, Op_VecA, 5, v5->as_VMReg()->next(2) );
268 reg_def V5_K ( SOC, SOC, Op_VecA, 5, v5->as_VMReg()->next(3) );
269
270 reg_def V6 ( SOC, SOC, Op_VecA, 6, v6->as_VMReg() );
271 reg_def V6_H ( SOC, SOC, Op_VecA, 6, v6->as_VMReg()->next() );
272 reg_def V6_J ( SOC, SOC, Op_VecA, 6, v6->as_VMReg()->next(2) );
273 reg_def V6_K ( SOC, SOC, Op_VecA, 6, v6->as_VMReg()->next(3) );
274
275 reg_def V7 ( SOC, SOC, Op_VecA, 7, v7->as_VMReg() );
276 reg_def V7_H ( SOC, SOC, Op_VecA, 7, v7->as_VMReg()->next() );
277 reg_def V7_J ( SOC, SOC, Op_VecA, 7, v7->as_VMReg()->next(2) );
278 reg_def V7_K ( SOC, SOC, Op_VecA, 7, v7->as_VMReg()->next(3) );
279
280 reg_def V8 ( SOC, SOC, Op_VecA, 8, v8->as_VMReg() );
281 reg_def V8_H ( SOC, SOC, Op_VecA, 8, v8->as_VMReg()->next() );
282 reg_def V8_J ( SOC, SOC, Op_VecA, 8, v8->as_VMReg()->next(2) );
283 reg_def V8_K ( SOC, SOC, Op_VecA, 8, v8->as_VMReg()->next(3) );
284
285 reg_def V9 ( SOC, SOC, Op_VecA, 9, v9->as_VMReg() );
286 reg_def V9_H ( SOC, SOC, Op_VecA, 9, v9->as_VMReg()->next() );
287 reg_def V9_J ( SOC, SOC, Op_VecA, 9, v9->as_VMReg()->next(2) );
288 reg_def V9_K ( SOC, SOC, Op_VecA, 9, v9->as_VMReg()->next(3) );
289
290 reg_def V10 ( SOC, SOC, Op_VecA, 10, v10->as_VMReg() );
291 reg_def V10_H ( SOC, SOC, Op_VecA, 10, v10->as_VMReg()->next() );
292 reg_def V10_J ( SOC, SOC, Op_VecA, 10, v10->as_VMReg()->next(2) );
293 reg_def V10_K ( SOC, SOC, Op_VecA, 10, v10->as_VMReg()->next(3) );
294
295 reg_def V11 ( SOC, SOC, Op_VecA, 11, v11->as_VMReg() );
296 reg_def V11_H ( SOC, SOC, Op_VecA, 11, v11->as_VMReg()->next() );
297 reg_def V11_J ( SOC, SOC, Op_VecA, 11, v11->as_VMReg()->next(2) );
298 reg_def V11_K ( SOC, SOC, Op_VecA, 11, v11->as_VMReg()->next(3) );
299
300 reg_def V12 ( SOC, SOC, Op_VecA, 12, v12->as_VMReg() );
301 reg_def V12_H ( SOC, SOC, Op_VecA, 12, v12->as_VMReg()->next() );
302 reg_def V12_J ( SOC, SOC, Op_VecA, 12, v12->as_VMReg()->next(2) );
303 reg_def V12_K ( SOC, SOC, Op_VecA, 12, v12->as_VMReg()->next(3) );
304
305 reg_def V13 ( SOC, SOC, Op_VecA, 13, v13->as_VMReg() );
306 reg_def V13_H ( SOC, SOC, Op_VecA, 13, v13->as_VMReg()->next() );
307 reg_def V13_J ( SOC, SOC, Op_VecA, 13, v13->as_VMReg()->next(2) );
308 reg_def V13_K ( SOC, SOC, Op_VecA, 13, v13->as_VMReg()->next(3) );
309
310 reg_def V14 ( SOC, SOC, Op_VecA, 14, v14->as_VMReg() );
311 reg_def V14_H ( SOC, SOC, Op_VecA, 14, v14->as_VMReg()->next() );
312 reg_def V14_J ( SOC, SOC, Op_VecA, 14, v14->as_VMReg()->next(2) );
313 reg_def V14_K ( SOC, SOC, Op_VecA, 14, v14->as_VMReg()->next(3) );
314
315 reg_def V15 ( SOC, SOC, Op_VecA, 15, v15->as_VMReg() );
316 reg_def V15_H ( SOC, SOC, Op_VecA, 15, v15->as_VMReg()->next() );
317 reg_def V15_J ( SOC, SOC, Op_VecA, 15, v15->as_VMReg()->next(2) );
318 reg_def V15_K ( SOC, SOC, Op_VecA, 15, v15->as_VMReg()->next(3) );
319
320 reg_def V16 ( SOC, SOC, Op_VecA, 16, v16->as_VMReg() );
321 reg_def V16_H ( SOC, SOC, Op_VecA, 16, v16->as_VMReg()->next() );
322 reg_def V16_J ( SOC, SOC, Op_VecA, 16, v16->as_VMReg()->next(2) );
323 reg_def V16_K ( SOC, SOC, Op_VecA, 16, v16->as_VMReg()->next(3) );
324
325 reg_def V17 ( SOC, SOC, Op_VecA, 17, v17->as_VMReg() );
326 reg_def V17_H ( SOC, SOC, Op_VecA, 17, v17->as_VMReg()->next() );
327 reg_def V17_J ( SOC, SOC, Op_VecA, 17, v17->as_VMReg()->next(2) );
328 reg_def V17_K ( SOC, SOC, Op_VecA, 17, v17->as_VMReg()->next(3) );
329
330 reg_def V18 ( SOC, SOC, Op_VecA, 18, v18->as_VMReg() );
331 reg_def V18_H ( SOC, SOC, Op_VecA, 18, v18->as_VMReg()->next() );
332 reg_def V18_J ( SOC, SOC, Op_VecA, 18, v18->as_VMReg()->next(2) );
333 reg_def V18_K ( SOC, SOC, Op_VecA, 18, v18->as_VMReg()->next(3) );
334
335 reg_def V19 ( SOC, SOC, Op_VecA, 19, v19->as_VMReg() );
336 reg_def V19_H ( SOC, SOC, Op_VecA, 19, v19->as_VMReg()->next() );
337 reg_def V19_J ( SOC, SOC, Op_VecA, 19, v19->as_VMReg()->next(2) );
338 reg_def V19_K ( SOC, SOC, Op_VecA, 19, v19->as_VMReg()->next(3) );
339
340 reg_def V20 ( SOC, SOC, Op_VecA, 20, v20->as_VMReg() );
341 reg_def V20_H ( SOC, SOC, Op_VecA, 20, v20->as_VMReg()->next() );
342 reg_def V20_J ( SOC, SOC, Op_VecA, 20, v20->as_VMReg()->next(2) );
343 reg_def V20_K ( SOC, SOC, Op_VecA, 20, v20->as_VMReg()->next(3) );
344
345 reg_def V21 ( SOC, SOC, Op_VecA, 21, v21->as_VMReg() );
346 reg_def V21_H ( SOC, SOC, Op_VecA, 21, v21->as_VMReg()->next() );
347 reg_def V21_J ( SOC, SOC, Op_VecA, 21, v21->as_VMReg()->next(2) );
348 reg_def V21_K ( SOC, SOC, Op_VecA, 21, v21->as_VMReg()->next(3) );
349
350 reg_def V22 ( SOC, SOC, Op_VecA, 22, v22->as_VMReg() );
351 reg_def V22_H ( SOC, SOC, Op_VecA, 22, v22->as_VMReg()->next() );
352 reg_def V22_J ( SOC, SOC, Op_VecA, 22, v22->as_VMReg()->next(2) );
353 reg_def V22_K ( SOC, SOC, Op_VecA, 22, v22->as_VMReg()->next(3) );
354
355 reg_def V23 ( SOC, SOC, Op_VecA, 23, v23->as_VMReg() );
356 reg_def V23_H ( SOC, SOC, Op_VecA, 23, v23->as_VMReg()->next() );
357 reg_def V23_J ( SOC, SOC, Op_VecA, 23, v23->as_VMReg()->next(2) );
358 reg_def V23_K ( SOC, SOC, Op_VecA, 23, v23->as_VMReg()->next(3) );
359
360 reg_def V24 ( SOC, SOC, Op_VecA, 24, v24->as_VMReg() );
361 reg_def V24_H ( SOC, SOC, Op_VecA, 24, v24->as_VMReg()->next() );
362 reg_def V24_J ( SOC, SOC, Op_VecA, 24, v24->as_VMReg()->next(2) );
363 reg_def V24_K ( SOC, SOC, Op_VecA, 24, v24->as_VMReg()->next(3) );
364
365 reg_def V25 ( SOC, SOC, Op_VecA, 25, v25->as_VMReg() );
366 reg_def V25_H ( SOC, SOC, Op_VecA, 25, v25->as_VMReg()->next() );
367 reg_def V25_J ( SOC, SOC, Op_VecA, 25, v25->as_VMReg()->next(2) );
368 reg_def V25_K ( SOC, SOC, Op_VecA, 25, v25->as_VMReg()->next(3) );
369
370 reg_def V26 ( SOC, SOC, Op_VecA, 26, v26->as_VMReg() );
371 reg_def V26_H ( SOC, SOC, Op_VecA, 26, v26->as_VMReg()->next() );
372 reg_def V26_J ( SOC, SOC, Op_VecA, 26, v26->as_VMReg()->next(2) );
373 reg_def V26_K ( SOC, SOC, Op_VecA, 26, v26->as_VMReg()->next(3) );
374
375 reg_def V27 ( SOC, SOC, Op_VecA, 27, v27->as_VMReg() );
376 reg_def V27_H ( SOC, SOC, Op_VecA, 27, v27->as_VMReg()->next() );
377 reg_def V27_J ( SOC, SOC, Op_VecA, 27, v27->as_VMReg()->next(2) );
378 reg_def V27_K ( SOC, SOC, Op_VecA, 27, v27->as_VMReg()->next(3) );
379
380 reg_def V28 ( SOC, SOC, Op_VecA, 28, v28->as_VMReg() );
381 reg_def V28_H ( SOC, SOC, Op_VecA, 28, v28->as_VMReg()->next() );
382 reg_def V28_J ( SOC, SOC, Op_VecA, 28, v28->as_VMReg()->next(2) );
383 reg_def V28_K ( SOC, SOC, Op_VecA, 28, v28->as_VMReg()->next(3) );
384
385 reg_def V29 ( SOC, SOC, Op_VecA, 29, v29->as_VMReg() );
386 reg_def V29_H ( SOC, SOC, Op_VecA, 29, v29->as_VMReg()->next() );
387 reg_def V29_J ( SOC, SOC, Op_VecA, 29, v29->as_VMReg()->next(2) );
388 reg_def V29_K ( SOC, SOC, Op_VecA, 29, v29->as_VMReg()->next(3) );
389
390 reg_def V30 ( SOC, SOC, Op_VecA, 30, v30->as_VMReg() );
391 reg_def V30_H ( SOC, SOC, Op_VecA, 30, v30->as_VMReg()->next() );
392 reg_def V30_J ( SOC, SOC, Op_VecA, 30, v30->as_VMReg()->next(2) );
393 reg_def V30_K ( SOC, SOC, Op_VecA, 30, v30->as_VMReg()->next(3) );
394
395 reg_def V31 ( SOC, SOC, Op_VecA, 31, v31->as_VMReg() );
396 reg_def V31_H ( SOC, SOC, Op_VecA, 31, v31->as_VMReg()->next() );
397 reg_def V31_J ( SOC, SOC, Op_VecA, 31, v31->as_VMReg()->next(2) );
398 reg_def V31_K ( SOC, SOC, Op_VecA, 31, v31->as_VMReg()->next(3) );
399
400 // ----------------------------
401 // Special Registers
402 // ----------------------------
403
404 // On riscv, the physical flag register is missing, so we use t1 instead,
405 // to bridge the RegFlag semantics in share/opto
406
407 reg_def RFLAGS (SOC, SOC, Op_RegFlags, 6, x6->as_VMReg() );
408
409 // Specify priority of register selection within phases of register
410 // allocation. Highest priority is first. A useful heuristic is to
411 // give registers a low priority when they are required by machine
412 // instructions, like EAX and EDX on I486, and choose no-save registers
413 // before save-on-call, & save-on-call before save-on-entry. Registers
414 // which participate in fixed calling sequences should come last.
415 // Registers which are used as pairs must fall on an even boundary.
416
417 alloc_class chunk0(
418 // volatiles
419 R7, R7_H,
420 R28, R28_H,
421 R29, R29_H,
422 R30, R30_H,
423 R31, R31_H,
424
425 // arg registers
426 R10, R10_H,
427 R11, R11_H,
428 R12, R12_H,
429 R13, R13_H,
430 R14, R14_H,
431 R15, R15_H,
432 R16, R16_H,
433 R17, R17_H,
434
435 // non-volatiles
436 R9, R9_H,
437 R18, R18_H,
438 R19, R19_H,
439 R20, R20_H,
440 R21, R21_H,
441 R22, R22_H,
442 R24, R24_H,
443 R25, R25_H,
444 R26, R26_H,
445
446 // non-allocatable registers
447 R23, R23_H, // java thread
448 R27, R27_H, // heapbase
449 R4, R4_H, // thread
450 R8, R8_H, // fp
451 R0, R0_H, // zero
452 R1, R1_H, // ra
453 R2, R2_H, // sp
454 R3, R3_H, // gp
455 );
456
457 alloc_class chunk1(
458
459 // no save
460 F0, F0_H,
461 F1, F1_H,
462 F2, F2_H,
463 F3, F3_H,
464 F4, F4_H,
465 F5, F5_H,
466 F6, F6_H,
467 F7, F7_H,
468 F28, F28_H,
469 F29, F29_H,
470 F30, F30_H,
471 F31, F31_H,
472
473 // arg registers
474 F10, F10_H,
475 F11, F11_H,
476 F12, F12_H,
477 F13, F13_H,
478 F14, F14_H,
479 F15, F15_H,
480 F16, F16_H,
481 F17, F17_H,
482
483 // non-volatiles
484 F8, F8_H,
485 F9, F9_H,
486 F18, F18_H,
487 F19, F19_H,
488 F20, F20_H,
489 F21, F21_H,
490 F22, F22_H,
491 F23, F23_H,
492 F24, F24_H,
493 F25, F25_H,
494 F26, F26_H,
495 F27, F27_H,
496 );
497
498 alloc_class chunk2(
499 V0, V0_H, V0_J, V0_K,
500 V1, V1_H, V1_J, V1_K,
501 V2, V2_H, V2_J, V2_K,
502 V3, V3_H, V3_J, V3_K,
503 V4, V4_H, V4_J, V4_K,
504 V5, V5_H, V5_J, V5_K,
505 V6, V6_H, V6_J, V6_K,
506 V7, V7_H, V7_J, V7_K,
507 V8, V8_H, V8_J, V8_K,
508 V9, V9_H, V9_J, V9_K,
509 V10, V10_H, V10_J, V10_K,
510 V11, V11_H, V11_J, V11_K,
511 V12, V12_H, V12_J, V12_K,
512 V13, V13_H, V13_J, V13_K,
513 V14, V14_H, V14_J, V14_K,
514 V15, V15_H, V15_J, V15_K,
515 V16, V16_H, V16_J, V16_K,
516 V17, V17_H, V17_J, V17_K,
517 V18, V18_H, V18_J, V18_K,
518 V19, V19_H, V19_J, V19_K,
519 V20, V20_H, V20_J, V20_K,
520 V21, V21_H, V21_J, V21_K,
521 V22, V22_H, V22_J, V22_K,
522 V23, V23_H, V23_J, V23_K,
523 V24, V24_H, V24_J, V24_K,
524 V25, V25_H, V25_J, V25_K,
525 V26, V26_H, V26_J, V26_K,
526 V27, V27_H, V27_J, V27_K,
527 V28, V28_H, V28_J, V28_K,
528 V29, V29_H, V29_J, V29_K,
529 V30, V30_H, V30_J, V30_K,
530 V31, V31_H, V31_J, V31_K,
531 );
532
533 alloc_class chunk3(RFLAGS);
534
535 //----------Architecture Description Register Classes--------------------------
536 // Several register classes are automatically defined based upon information in
537 // this architecture description.
538 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
539 // 2) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
540 //
541
542 // Class for all 32 bit general purpose registers
543 reg_class all_reg32(
544 R0,
545 R1,
546 R2,
547 R3,
548 R4,
549 R7,
550 R8,
551 R9,
552 R10,
553 R11,
554 R12,
555 R13,
556 R14,
557 R15,
558 R16,
559 R17,
560 R18,
561 R19,
562 R20,
563 R21,
564 R22,
565 R23,
566 R24,
567 R25,
568 R26,
569 R27,
570 R28,
571 R29,
572 R30,
573 R31
574 );
575
576 // Class for any 32 bit integer registers (excluding zr)
577 reg_class any_reg32 %{
578 return _ANY_REG32_mask;
579 %}
580
581 // Singleton class for R10 int register
582 reg_class int_r10_reg(R10);
583
584 // Singleton class for R12 int register
585 reg_class int_r12_reg(R12);
586
587 // Singleton class for R13 int register
588 reg_class int_r13_reg(R13);
589
590 // Singleton class for R14 int register
591 reg_class int_r14_reg(R14);
592
593 // Class for all long integer registers
594 reg_class all_reg(
595 R0, R0_H,
596 R1, R1_H,
597 R2, R2_H,
598 R3, R3_H,
599 R4, R4_H,
600 R7, R7_H,
601 R8, R8_H,
602 R9, R9_H,
603 R10, R10_H,
604 R11, R11_H,
605 R12, R12_H,
606 R13, R13_H,
607 R14, R14_H,
608 R15, R15_H,
609 R16, R16_H,
610 R17, R17_H,
611 R18, R18_H,
612 R19, R19_H,
613 R20, R20_H,
614 R21, R21_H,
615 R22, R22_H,
616 R23, R23_H,
617 R24, R24_H,
618 R25, R25_H,
619 R26, R26_H,
620 R27, R27_H,
621 R28, R28_H,
622 R29, R29_H,
623 R30, R30_H,
624 R31, R31_H
625 );
626
627 // Class for all long integer registers (excluding zr)
628 reg_class any_reg %{
629 return _ANY_REG_mask;
630 %}
631
632 // Class for non-allocatable 32 bit registers
633 reg_class non_allocatable_reg32(
634 R0, // zr
635 R1, // ra
636 R2, // sp
637 R3, // gp
638 R4, // tp
639 R23 // java thread
640 );
641
642 // Class for non-allocatable 64 bit registers
643 reg_class non_allocatable_reg(
644 R0, R0_H, // zr
645 R1, R1_H, // ra
646 R2, R2_H, // sp
647 R3, R3_H, // gp
648 R4, R4_H, // tp
649 R23, R23_H // java thread
650 );
651
652 // Class for all non-special integer registers
653 reg_class no_special_reg32 %{
654 return _NO_SPECIAL_REG32_mask;
655 %}
656
657 // Class for all non-special long integer registers
658 reg_class no_special_reg %{
659 return _NO_SPECIAL_REG_mask;
660 %}
661
662 reg_class ptr_reg %{
663 return _PTR_REG_mask;
664 %}
665
666 // Class for all non_special pointer registers
667 reg_class no_special_ptr_reg %{
668 return _NO_SPECIAL_PTR_REG_mask;
669 %}
670
671 // Class for all non_special pointer registers (excluding fp)
672 reg_class no_special_no_fp_ptr_reg %{
673 return _NO_SPECIAL_NO_FP_PTR_REG_mask;
674 %}
675
676 // Class for 64 bit register r10
677 reg_class r10_reg(
678 R10, R10_H
679 );
680
681 // Class for 64 bit register r11
682 reg_class r11_reg(
683 R11, R11_H
684 );
685
686 // Class for 64 bit register r12
687 reg_class r12_reg(
688 R12, R12_H
689 );
690
691 // Class for 64 bit register r13
692 reg_class r13_reg(
693 R13, R13_H
694 );
695
696 // Class for 64 bit register r14
697 reg_class r14_reg(
698 R14, R14_H
699 );
700
701 // Class for 64 bit register r15
702 reg_class r15_reg(
703 R15, R15_H
704 );
705
706 // Class for 64 bit register r16
707 reg_class r16_reg(
708 R16, R16_H
709 );
710
711 // Class for method register
712 reg_class method_reg(
713 R31, R31_H
714 );
715
716 // Class for java thread register
717 reg_class java_thread_reg(
718 R23, R23_H
719 );
720
721 reg_class r28_reg(
722 R28, R28_H
723 );
724
725 reg_class r29_reg(
726 R29, R29_H
727 );
728
729 reg_class r30_reg(
730 R30, R30_H
731 );
732
733 reg_class r31_reg(
734 R31, R31_H
735 );
736
737 // Class for zero registesr
738 reg_class zr_reg(
739 R0, R0_H
740 );
741
742 // Class for thread register
743 reg_class thread_reg(
744 R4, R4_H
745 );
746
747 // Class for frame pointer register
748 reg_class fp_reg(
749 R8, R8_H
750 );
751
752 // Class for link register
753 reg_class ra_reg(
754 R1, R1_H
755 );
756
757 // Class for long sp register
758 reg_class sp_reg(
759 R2, R2_H
760 );
761
762 // Class for all float registers
763 reg_class float_reg(
764 F0,
765 F1,
766 F2,
767 F3,
768 F4,
769 F5,
770 F6,
771 F7,
772 F8,
773 F9,
774 F10,
775 F11,
776 F12,
777 F13,
778 F14,
779 F15,
780 F16,
781 F17,
782 F18,
783 F19,
784 F20,
785 F21,
786 F22,
787 F23,
788 F24,
789 F25,
790 F26,
791 F27,
792 F28,
793 F29,
794 F30,
795 F31
796 );
797
798 // Double precision float registers have virtual `high halves' that
799 // are needed by the allocator.
800 // Class for all double registers
801 reg_class double_reg(
802 F0, F0_H,
803 F1, F1_H,
804 F2, F2_H,
805 F3, F3_H,
806 F4, F4_H,
807 F5, F5_H,
808 F6, F6_H,
809 F7, F7_H,
810 F8, F8_H,
811 F9, F9_H,
812 F10, F10_H,
813 F11, F11_H,
814 F12, F12_H,
815 F13, F13_H,
816 F14, F14_H,
817 F15, F15_H,
818 F16, F16_H,
819 F17, F17_H,
820 F18, F18_H,
821 F19, F19_H,
822 F20, F20_H,
823 F21, F21_H,
824 F22, F22_H,
825 F23, F23_H,
826 F24, F24_H,
827 F25, F25_H,
828 F26, F26_H,
829 F27, F27_H,
830 F28, F28_H,
831 F29, F29_H,
832 F30, F30_H,
833 F31, F31_H
834 );
835
836 // Class for RVV vector registers
837 // Note: v0, v30 and v31 are used as mask registers.
838 reg_class vectora_reg(
839 V1, V1_H, V1_J, V1_K,
840 V2, V2_H, V2_J, V2_K,
841 V3, V3_H, V3_J, V3_K,
842 V4, V4_H, V4_J, V4_K,
843 V5, V5_H, V5_J, V5_K,
844 V6, V6_H, V6_J, V6_K,
845 V7, V7_H, V7_J, V7_K,
846 V8, V8_H, V8_J, V8_K,
847 V9, V9_H, V9_J, V9_K,
848 V10, V10_H, V10_J, V10_K,
849 V11, V11_H, V11_J, V11_K,
850 V12, V12_H, V12_J, V12_K,
851 V13, V13_H, V13_J, V13_K,
852 V14, V14_H, V14_J, V14_K,
853 V15, V15_H, V15_J, V15_K,
854 V16, V16_H, V16_J, V16_K,
855 V17, V17_H, V17_J, V17_K,
856 V18, V18_H, V18_J, V18_K,
857 V19, V19_H, V19_J, V19_K,
858 V20, V20_H, V20_J, V20_K,
859 V21, V21_H, V21_J, V21_K,
860 V22, V22_H, V22_J, V22_K,
861 V23, V23_H, V23_J, V23_K,
862 V24, V24_H, V24_J, V24_K,
863 V25, V25_H, V25_J, V25_K,
864 V26, V26_H, V26_J, V26_K,
865 V27, V27_H, V27_J, V27_K,
866 V28, V28_H, V28_J, V28_K,
867 V29, V29_H, V29_J, V29_K
868 );
869
870 // Class for 64 bit register f0
871 reg_class f0_reg(
872 F0, F0_H
873 );
874
875 // Class for 64 bit register f1
876 reg_class f1_reg(
877 F1, F1_H
878 );
879
880 // Class for 64 bit register f2
881 reg_class f2_reg(
882 F2, F2_H
883 );
884
885 // Class for 64 bit register f3
886 reg_class f3_reg(
887 F3, F3_H
888 );
889
890 // class for vector register v1
891 reg_class v1_reg(
892 V1, V1_H, V1_J, V1_K
893 );
894
895 // class for vector register v2
896 reg_class v2_reg(
897 V2, V2_H, V2_J, V2_K
898 );
899
900 // class for vector register v3
901 reg_class v3_reg(
902 V3, V3_H, V3_J, V3_K
903 );
904
905 // class for vector register v4
906 reg_class v4_reg(
907 V4, V4_H, V4_J, V4_K
908 );
909
910 // class for vector register v5
911 reg_class v5_reg(
912 V5, V5_H, V5_J, V5_K
913 );
914
915 // class for vector register v6
916 reg_class v6_reg(
917 V6, V6_H, V6_J, V6_K
918 );
919
920 // class for vector register v7
921 reg_class v7_reg(
922 V7, V7_H, V7_J, V7_K
923 );
924
925 // class for vector register v8
926 reg_class v8_reg(
927 V8, V8_H, V8_J, V8_K
928 );
929
930 // class for vector register v9
931 reg_class v9_reg(
932 V9, V9_H, V9_J, V9_K
933 );
934
935 // class for vector register v10
936 reg_class v10_reg(
937 V10, V10_H, V10_J, V10_K
938 );
939
940 // class for vector register v11
941 reg_class v11_reg(
942 V11, V11_H, V11_J, V11_K
943 );
944
945 // class for condition codes
946 reg_class reg_flags(RFLAGS);
947
948 // Class for RVV v0 mask register
949 // https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#53-vector-masking
950 // The mask value used to control execution of a masked vector
951 // instruction is always supplied by vector register v0.
952 reg_class vmask_reg_v0 (
953 V0
954 );
955
956 // Class for RVV mask registers
957 // We need two more vmask registers to do the vector mask logical ops,
958 // so define v30, v31 as mask register too.
959 reg_class vmask_reg (
960 V0,
961 V30,
962 V31
963 );
964 %}
965
966 //----------DEFINITION BLOCK---------------------------------------------------
967 // Define name --> value mappings to inform the ADLC of an integer valued name
968 // Current support includes integer values in the range [0, 0x7FFFFFFF]
969 // Format:
970 // int_def <name> ( <int_value>, <expression>);
971 // Generated Code in ad_<arch>.hpp
972 // #define <name> (<expression>)
973 // // value == <int_value>
974 // Generated code in ad_<arch>.cpp adlc_verification()
975 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
976 //
977
978 // we follow the ppc-aix port in using a simple cost model which ranks
979 // register operations as cheap, memory ops as more expensive and
980 // branches as most expensive. the first two have a low as well as a
981 // normal cost. huge cost appears to be a way of saying don't do
982 // something
983
984 definitions %{
985 // The default cost (of a register move instruction).
986 int_def DEFAULT_COST ( 100, 100);
987 int_def ALU_COST ( 100, 1 * DEFAULT_COST); // unknown, const, arith, shift, slt,
988 // multi, auipc, nop, logical, move
989 int_def LOAD_COST ( 300, 3 * DEFAULT_COST); // load, fpload
990 int_def STORE_COST ( 100, 1 * DEFAULT_COST); // store, fpstore
991 int_def XFER_COST ( 300, 3 * DEFAULT_COST); // mfc, mtc, fcvt, fmove, fcmp
992 int_def FMVX_COST ( 100, 1 * DEFAULT_COST); // shuffles with no conversion
993 int_def BRANCH_COST ( 200, 2 * DEFAULT_COST); // branch, jmp, call
994 int_def IMUL_COST ( 1000, 10 * DEFAULT_COST); // imul
995 int_def IDIVSI_COST ( 3400, 34 * DEFAULT_COST); // idivsi
996 int_def IDIVDI_COST ( 6600, 66 * DEFAULT_COST); // idivdi
997 int_def FMUL_SINGLE_COST ( 500, 5 * DEFAULT_COST); // fmul, fmadd
998 int_def FMUL_DOUBLE_COST ( 700, 7 * DEFAULT_COST); // fmul, fmadd
999 int_def FDIV_COST ( 2000, 20 * DEFAULT_COST); // fdiv
1000 int_def FSQRT_COST ( 2500, 25 * DEFAULT_COST); // fsqrt
1001 int_def VOLATILE_REF_COST ( 1000, 10 * DEFAULT_COST);
1002 int_def CACHE_MISS_COST ( 2000, 20 * DEFAULT_COST); // typicall cache miss penalty
1003 %}
1004
1005
1006
1007 //----------SOURCE BLOCK-------------------------------------------------------
1008 // This is a block of C++ code which provides values, functions, and
1009 // definitions necessary in the rest of the architecture description
1010
1011 source_hpp %{
1012
1013 #include "asm/macroAssembler.hpp"
1014 #include "gc/shared/barrierSetAssembler.hpp"
1015 #include "gc/shared/cardTable.hpp"
1016 #include "gc/shared/cardTableBarrierSet.hpp"
1017 #include "gc/shared/collectedHeap.hpp"
1018 #include "opto/addnode.hpp"
1019 #include "opto/convertnode.hpp"
1020 #include "runtime/objectMonitor.hpp"
1021
1022 extern RegMask _ANY_REG32_mask;
1023 extern RegMask _ANY_REG_mask;
1024 extern RegMask _PTR_REG_mask;
1025 extern RegMask _NO_SPECIAL_REG32_mask;
1026 extern RegMask _NO_SPECIAL_REG_mask;
1027 extern RegMask _NO_SPECIAL_PTR_REG_mask;
1028 extern RegMask _NO_SPECIAL_NO_FP_PTR_REG_mask;
1029
1030 class CallStubImpl {
1031
1032 //--------------------------------------------------------------
1033 //---< Used for optimization in Compile::shorten_branches >---
1034 //--------------------------------------------------------------
1035
1036 public:
1037 // Size of call trampoline stub.
1038 static uint size_call_trampoline() {
1039 return 0; // no call trampolines on this platform
1040 }
1041
1042 // number of relocations needed by a call trampoline stub
1043 static uint reloc_call_trampoline() {
1044 return 0; // no call trampolines on this platform
1045 }
1046 };
1047
1048 class HandlerImpl {
1049
1050 public:
1051
1052 static int emit_exception_handler(C2_MacroAssembler *masm);
1053 static int emit_deopt_handler(C2_MacroAssembler* masm);
1054
1055 static uint size_exception_handler() {
1056 return MacroAssembler::far_branch_size();
1057 }
1058
1059 static uint size_deopt_handler() {
1060 // count auipc + far branch
1061 return NativeInstruction::instruction_size + MacroAssembler::far_branch_size();
1062 }
1063 };
1064
1065 class Node::PD {
1066 public:
1067 enum NodeFlags {
1068 _last_flag = Node::_last_flag
1069 };
1070 };
1071
1072 bool is_CAS(int opcode, bool maybe_volatile);
1073
1074 // predicate controlling translation of CompareAndSwapX
1075 bool needs_acquiring_load_reserved(const Node *load);
1076
1077 // predicate controlling addressing modes
1078 bool size_fits_all_mem_uses(AddPNode* addp, int shift);
1079 %}
1080
1081 source %{
1082
1083 // Derived RegMask with conditionally allocatable registers
1084
1085 RegMask _ANY_REG32_mask;
1086 RegMask _ANY_REG_mask;
1087 RegMask _PTR_REG_mask;
1088 RegMask _NO_SPECIAL_REG32_mask;
1089 RegMask _NO_SPECIAL_REG_mask;
1090 RegMask _NO_SPECIAL_PTR_REG_mask;
1091 RegMask _NO_SPECIAL_NO_FP_PTR_REG_mask;
1092
1093 void reg_mask_init() {
1094
1095 _ANY_REG32_mask = _ALL_REG32_mask;
1096 _ANY_REG32_mask.Remove(OptoReg::as_OptoReg(x0->as_VMReg()));
1097
1098 _ANY_REG_mask = _ALL_REG_mask;
1099 _ANY_REG_mask.SUBTRACT(_ZR_REG_mask);
1100
1101 _PTR_REG_mask = _ALL_REG_mask;
1102 _PTR_REG_mask.SUBTRACT(_ZR_REG_mask);
1103
1104 _NO_SPECIAL_REG32_mask = _ALL_REG32_mask;
1105 _NO_SPECIAL_REG32_mask.SUBTRACT(_NON_ALLOCATABLE_REG32_mask);
1106
1107 _NO_SPECIAL_REG_mask = _ALL_REG_mask;
1108 _NO_SPECIAL_REG_mask.SUBTRACT(_NON_ALLOCATABLE_REG_mask);
1109
1110 _NO_SPECIAL_PTR_REG_mask = _ALL_REG_mask;
1111 _NO_SPECIAL_PTR_REG_mask.SUBTRACT(_NON_ALLOCATABLE_REG_mask);
1112
1113 // x27 is not allocatable when compressed oops is on
1114 if (UseCompressedOops) {
1115 _NO_SPECIAL_REG32_mask.Remove(OptoReg::as_OptoReg(x27->as_VMReg()));
1116 _NO_SPECIAL_REG_mask.Remove(OptoReg::as_OptoReg(x27->as_VMReg()));
1117 _NO_SPECIAL_PTR_REG_mask.Remove(OptoReg::as_OptoReg(x27->as_VMReg()));
1118 }
1119
1120 // x8 is not allocatable when PreserveFramePointer is on
1121 if (PreserveFramePointer) {
1122 _NO_SPECIAL_REG32_mask.Remove(OptoReg::as_OptoReg(x8->as_VMReg()));
1123 _NO_SPECIAL_REG_mask.Remove(OptoReg::as_OptoReg(x8->as_VMReg()));
1124 _NO_SPECIAL_PTR_REG_mask.Remove(OptoReg::as_OptoReg(x8->as_VMReg()));
1125 }
1126
1127 _NO_SPECIAL_NO_FP_PTR_REG_mask = _NO_SPECIAL_PTR_REG_mask;
1128 _NO_SPECIAL_NO_FP_PTR_REG_mask.Remove(OptoReg::as_OptoReg(x8->as_VMReg()));
1129 }
1130
1131 void PhaseOutput::pd_perform_mach_node_analysis() {
1132 }
1133
1134 int MachNode::pd_alignment_required() const {
1135 return 1;
1136 }
1137
1138 int MachNode::compute_padding(int current_offset) const {
1139 return 0;
1140 }
1141
1142 // is_CAS(int opcode, bool maybe_volatile)
1143 //
1144 // return true if opcode is one of the possible CompareAndSwapX
1145 // values otherwise false.
1146 bool is_CAS(int opcode, bool maybe_volatile)
1147 {
1148 switch (opcode) {
1149 // We handle these
1150 case Op_CompareAndSwapI:
1151 case Op_CompareAndSwapL:
1152 case Op_CompareAndSwapP:
1153 case Op_CompareAndSwapN:
1154 case Op_ShenandoahCompareAndSwapP:
1155 case Op_ShenandoahCompareAndSwapN:
1156 case Op_CompareAndSwapB:
1157 case Op_CompareAndSwapS:
1158 case Op_GetAndSetI:
1159 case Op_GetAndSetL:
1160 case Op_GetAndSetP:
1161 case Op_GetAndSetN:
1162 case Op_GetAndAddI:
1163 case Op_GetAndAddL:
1164 return true;
1165 case Op_CompareAndExchangeI:
1166 case Op_CompareAndExchangeN:
1167 case Op_CompareAndExchangeB:
1168 case Op_CompareAndExchangeS:
1169 case Op_CompareAndExchangeL:
1170 case Op_CompareAndExchangeP:
1171 case Op_WeakCompareAndSwapB:
1172 case Op_WeakCompareAndSwapS:
1173 case Op_WeakCompareAndSwapI:
1174 case Op_WeakCompareAndSwapL:
1175 case Op_WeakCompareAndSwapP:
1176 case Op_WeakCompareAndSwapN:
1177 case Op_ShenandoahWeakCompareAndSwapP:
1178 case Op_ShenandoahWeakCompareAndSwapN:
1179 case Op_ShenandoahCompareAndExchangeP:
1180 case Op_ShenandoahCompareAndExchangeN:
1181 return maybe_volatile;
1182 default:
1183 return false;
1184 }
1185 }
1186
1187 // predicate controlling translation of CAS
1188 //
1189 // returns true if CAS needs to use an acquiring load otherwise false
1190 bool needs_acquiring_load_reserved(const Node *n)
1191 {
1192 assert(n != nullptr && is_CAS(n->Opcode(), true), "expecting a compare and swap");
1193
1194 LoadStoreNode* ldst = n->as_LoadStore();
1195 if (n != nullptr && is_CAS(n->Opcode(), false)) {
1196 assert(ldst != nullptr && ldst->trailing_membar() != nullptr, "expected trailing membar");
1197 } else {
1198 return ldst != nullptr && ldst->trailing_membar() != nullptr;
1199 }
1200 // so we can just return true here
1201 return true;
1202 }
1203 #define __ masm->
1204
1205 // advance declarations for helper functions to convert register
1206 // indices to register objects
1207
1208 // the ad file has to provide implementations of certain methods
1209 // expected by the generic code
1210 //
1211 // REQUIRED FUNCTIONALITY
1212
1213 //=============================================================================
1214
1215 // !!!!! Special hack to get all types of calls to specify the byte offset
1216 // from the start of the call to the point where the return address
1217 // will point.
1218
1219 int MachCallStaticJavaNode::ret_addr_offset()
1220 {
1221 return 3 * NativeInstruction::instruction_size; // auipc + ld + jalr
1222 }
1223
1224 int MachCallDynamicJavaNode::ret_addr_offset()
1225 {
1226 return NativeMovConstReg::movptr2_instruction_size + (3 * NativeInstruction::instruction_size); // movptr2, auipc + ld + jal
1227 }
1228
1229 int MachCallRuntimeNode::ret_addr_offset() {
1230 // For address inside the code cache the call will be:
1231 // auipc + jalr
1232 // For real runtime callouts it will be 8 instructions
1233 // see riscv_enc_java_to_runtime
1234 // la(t0, retaddr) -> auipc + addi
1235 // sd(t0, Address(xthread, JavaThread::last_Java_pc_offset())) -> sd
1236 // movptr(t1, addr, offset, t0) -> lui + lui + slli + add
1237 // jalr(t1, offset) -> jalr
1238 if (CodeCache::contains(_entry_point)) {
1239 return 2 * NativeInstruction::instruction_size;
1240 } else {
1241 return 8 * NativeInstruction::instruction_size;
1242 }
1243 }
1244
1245 //
1246 // Compute padding required for nodes which need alignment
1247 //
1248
1249 // With RVC a call instruction may get 2-byte aligned.
1250 // The address of the call instruction needs to be 4-byte aligned to
1251 // ensure that it does not span a cache line so that it can be patched.
1252 int CallStaticJavaDirectNode::compute_padding(int current_offset) const
1253 {
1254 // to make sure the address of jal 4-byte aligned.
1255 return align_up(current_offset, alignment_required()) - current_offset;
1256 }
1257
1258 // With RVC a call instruction may get 2-byte aligned.
1259 // The address of the call instruction needs to be 4-byte aligned to
1260 // ensure that it does not span a cache line so that it can be patched.
1261 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const
1262 {
1263 // skip the movptr2 in MacroAssembler::ic_call():
1264 // lui, lui, slli, add, addi
1265 // Though movptr2() has already 4-byte aligned with or without RVC,
1266 // We need to prevent from further changes by explicitly calculating the size.
1267 current_offset += NativeMovConstReg::movptr2_instruction_size;
1268 // to make sure the address of jal 4-byte aligned.
1269 return align_up(current_offset, alignment_required()) - current_offset;
1270 }
1271
1272 //=============================================================================
1273
1274 #ifndef PRODUCT
1275 void MachBreakpointNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1276 assert_cond(st != nullptr);
1277 st->print("BREAKPOINT");
1278 }
1279 #endif
1280
1281 void MachBreakpointNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
1282 __ ebreak();
1283 }
1284
1285 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
1286 return MachNode::size(ra_);
1287 }
1288
1289 //=============================================================================
1290
1291 #ifndef PRODUCT
1292 void MachNopNode::format(PhaseRegAlloc*, outputStream* st) const {
1293 st->print("nop \t# %d bytes pad for loops and calls", _count);
1294 }
1295 #endif
1296
1297 void MachNopNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc*) const {
1298 Assembler::CompressibleRegion cr(masm); // nops shall be 2-byte under RVC for alignment purposes.
1299 for (int i = 0; i < _count; i++) {
1300 __ nop();
1301 }
1302 }
1303
1304 uint MachNopNode::size(PhaseRegAlloc*) const {
1305 return _count * (UseRVC ? NativeInstruction::compressed_instruction_size : NativeInstruction::instruction_size);
1306 }
1307
1308 //=============================================================================
1309 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;
1310
1311 int ConstantTable::calculate_table_base_offset() const {
1312 return 0; // absolute addressing, no offset
1313 }
1314
1315 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
1316 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
1317 ShouldNotReachHere();
1318 }
1319
1320 void MachConstantBaseNode::emit(C2_MacroAssembler* masm, PhaseRegAlloc* ra_) const {
1321 // Empty encoding
1322 }
1323
1324 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
1325 return 0;
1326 }
1327
1328 #ifndef PRODUCT
1329 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1330 assert_cond(st != nullptr);
1331 st->print("-- \t// MachConstantBaseNode (empty encoding)");
1332 }
1333 #endif
1334
1335 #ifndef PRODUCT
1336 void MachPrologNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1337 assert_cond(st != nullptr && ra_ != nullptr);
1338 Compile* C = ra_->C;
1339
1340 int framesize = C->output()->frame_slots() << LogBytesPerInt;
1341
1342 if (C->output()->need_stack_bang(framesize)) {
1343 st->print("# stack bang size=%d\n\t", framesize);
1344 }
1345
1346 st->print("sd fp, [sp, #%d]\n\t", - 2 * wordSize);
1347 st->print("sd ra, [sp, #%d]\n\t", - wordSize);
1348 if (PreserveFramePointer) { st->print("sub fp, sp, #%d\n\t", 2 * wordSize); }
1349 st->print("sub sp, sp, #%d\n\t", framesize);
1350
1351 if (C->stub_function() == nullptr && BarrierSet::barrier_set()->barrier_set_nmethod() != nullptr) {
1352 st->print("ld t0, [guard]\n\t");
1353 st->print("membar LoadLoad\n\t");
1354 st->print("ld t1, [xthread, #thread_disarmed_guard_value_offset]\n\t");
1355 st->print("beq t0, t1, skip\n\t");
1356 st->print("jalr #nmethod_entry_barrier_stub\n\t");
1357 st->print("j skip\n\t");
1358 st->print("guard: int\n\t");
1359 st->print("skip:\n\t");
1360 }
1361 }
1362 #endif
1363
1364 void MachPrologNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
1365 assert_cond(ra_ != nullptr);
1366 Compile* C = ra_->C;
1367
1368 // n.b. frame size includes space for return pc and fp
1369 const int framesize = C->output()->frame_size_in_bytes();
1370
1371 // insert a nop at the start of the prolog so we can patch in a
1372 // branch if we need to invalidate the method later
1373 {
1374 Assembler::IncompressibleRegion ir(masm); // keep the nop as 4 bytes for patching.
1375 MacroAssembler::assert_alignment(__ pc());
1376 __ nop(); // 4 bytes
1377 }
1378
1379 assert_cond(C != nullptr);
1380
1381 if (C->clinit_barrier_on_entry()) {
1382 assert(!C->method()->holder()->is_not_initialized(), "initialization should have been started");
1383
1384 Label L_skip_barrier;
1385
1386 __ mov_metadata(t1, C->method()->holder()->constant_encoding());
1387 __ clinit_barrier(t1, t0, &L_skip_barrier);
1388 __ far_jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub()));
1389 __ bind(L_skip_barrier);
1390 }
1391
1392 int bangsize = C->output()->bang_size_in_bytes();
1393 if (C->output()->need_stack_bang(bangsize)) {
1394 __ generate_stack_overflow_check(bangsize);
1395 }
1396
1397 __ build_frame(framesize);
1398
1399 if (C->stub_function() == nullptr) {
1400 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
1401 if (BarrierSet::barrier_set()->barrier_set_nmethod() != nullptr) {
1402 // Dummy labels for just measuring the code size
1403 Label dummy_slow_path;
1404 Label dummy_continuation;
1405 Label dummy_guard;
1406 Label* slow_path = &dummy_slow_path;
1407 Label* continuation = &dummy_continuation;
1408 Label* guard = &dummy_guard;
1409 if (!Compile::current()->output()->in_scratch_emit_size()) {
1410 // Use real labels from actual stub when not emitting code for purpose of measuring its size
1411 C2EntryBarrierStub* stub = new (Compile::current()->comp_arena()) C2EntryBarrierStub();
1412 Compile::current()->output()->add_stub(stub);
1413 slow_path = &stub->entry();
1414 continuation = &stub->continuation();
1415 guard = &stub->guard();
1416 }
1417 // In the C2 code, we move the non-hot part of nmethod entry barriers out-of-line to a stub.
1418 bs->nmethod_entry_barrier(masm, slow_path, continuation, guard);
1419 }
1420 }
1421
1422 if (VerifyStackAtCalls) {
1423 Unimplemented();
1424 }
1425
1426 C->output()->set_frame_complete(__ offset());
1427
1428 if (C->has_mach_constant_base_node()) {
1429 // NOTE: We set the table base offset here because users might be
1430 // emitted before MachConstantBaseNode.
1431 ConstantTable& constant_table = C->output()->constant_table();
1432 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
1433 }
1434 }
1435
1436 uint MachPrologNode::size(PhaseRegAlloc* ra_) const
1437 {
1438 assert_cond(ra_ != nullptr);
1439 return MachNode::size(ra_); // too many variables; just compute it
1440 // the hard way
1441 }
1442
1443 int MachPrologNode::reloc() const
1444 {
1445 return 0;
1446 }
1447
1448 //=============================================================================
1449
1450 #ifndef PRODUCT
1451 void MachEpilogNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1452 assert_cond(st != nullptr && ra_ != nullptr);
1453 Compile* C = ra_->C;
1454 assert_cond(C != nullptr);
1455 int framesize = C->output()->frame_size_in_bytes();
1456
1457 st->print("# pop frame %d\n\t", framesize);
1458
1459 if (framesize == 0) {
1460 st->print("ld ra, [sp,#%d]\n\t", (2 * wordSize));
1461 st->print("ld fp, [sp,#%d]\n\t", (3 * wordSize));
1462 st->print("add sp, sp, #%d\n\t", (2 * wordSize));
1463 } else {
1464 st->print("add sp, sp, #%d\n\t", framesize);
1465 st->print("ld ra, [sp,#%d]\n\t", - 2 * wordSize);
1466 st->print("ld fp, [sp,#%d]\n\t", - wordSize);
1467 }
1468
1469 if (do_polling() && C->is_method_compilation()) {
1470 st->print("# test polling word\n\t");
1471 st->print("ld t0, [xthread,#%d]\n\t", in_bytes(JavaThread::polling_word_offset()));
1472 st->print("bgtu sp, t0, #slow_path");
1473 }
1474 }
1475 #endif
1476
1477 void MachEpilogNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
1478 assert_cond(ra_ != nullptr);
1479 Compile* C = ra_->C;
1480 assert_cond(C != nullptr);
1481 int framesize = C->output()->frame_size_in_bytes();
1482
1483 __ remove_frame(framesize);
1484
1485 if (StackReservedPages > 0 && C->has_reserved_stack_access()) {
1486 __ reserved_stack_check();
1487 }
1488
1489 if (do_polling() && C->is_method_compilation()) {
1490 Label dummy_label;
1491 Label* code_stub = &dummy_label;
1492 if (!C->output()->in_scratch_emit_size()) {
1493 C2SafepointPollStub* stub = new (C->comp_arena()) C2SafepointPollStub(__ offset());
1494 C->output()->add_stub(stub);
1495 code_stub = &stub->entry();
1496 }
1497 __ relocate(relocInfo::poll_return_type);
1498 __ safepoint_poll(*code_stub, true /* at_return */, false /* acquire */, true /* in_nmethod */);
1499 }
1500 }
1501
1502 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
1503 assert_cond(ra_ != nullptr);
1504 // Variable size. Determine dynamically.
1505 return MachNode::size(ra_);
1506 }
1507
1508 int MachEpilogNode::reloc() const {
1509 // Return number of relocatable values contained in this instruction.
1510 return 1; // 1 for polling page.
1511 }
1512 const Pipeline * MachEpilogNode::pipeline() const {
1513 return MachNode::pipeline_class();
1514 }
1515
1516 //=============================================================================
1517
1518 // Figure out which register class each belongs in: rc_int, rc_float or
1519 // rc_stack.
1520 enum RC { rc_bad, rc_int, rc_float, rc_vector, rc_stack };
1521
1522 static enum RC rc_class(OptoReg::Name reg) {
1523
1524 if (reg == OptoReg::Bad) {
1525 return rc_bad;
1526 }
1527
1528 // we have 30 int registers * 2 halves
1529 // (t0 and t1 are omitted)
1530 int slots_of_int_registers = Register::max_slots_per_register * (Register::number_of_registers - 2);
1531 if (reg < slots_of_int_registers) {
1532 return rc_int;
1533 }
1534
1535 // we have 32 float register * 2 halves
1536 int slots_of_float_registers = FloatRegister::max_slots_per_register * FloatRegister::number_of_registers;
1537 if (reg < slots_of_int_registers + slots_of_float_registers) {
1538 return rc_float;
1539 }
1540
1541 // we have 32 vector register * 4 halves
1542 int slots_of_vector_registers = VectorRegister::max_slots_per_register * VectorRegister::number_of_registers;
1543 if (reg < slots_of_int_registers + slots_of_float_registers + slots_of_vector_registers) {
1544 return rc_vector;
1545 }
1546
1547 // Between vector regs & stack is the flags regs.
1548 assert(OptoReg::is_stack(reg), "blow up if spilling flags");
1549
1550 return rc_stack;
1551 }
1552
1553 uint MachSpillCopyNode::implementation(C2_MacroAssembler *masm, PhaseRegAlloc *ra_, bool do_size, outputStream *st) const {
1554 assert_cond(ra_ != nullptr);
1555 Compile* C = ra_->C;
1556
1557 // Get registers to move.
1558 OptoReg::Name src_hi = ra_->get_reg_second(in(1));
1559 OptoReg::Name src_lo = ra_->get_reg_first(in(1));
1560 OptoReg::Name dst_hi = ra_->get_reg_second(this);
1561 OptoReg::Name dst_lo = ra_->get_reg_first(this);
1562
1563 enum RC src_hi_rc = rc_class(src_hi);
1564 enum RC src_lo_rc = rc_class(src_lo);
1565 enum RC dst_hi_rc = rc_class(dst_hi);
1566 enum RC dst_lo_rc = rc_class(dst_lo);
1567
1568 assert(src_lo != OptoReg::Bad && dst_lo != OptoReg::Bad, "must move at least 1 register");
1569
1570 if (src_hi != OptoReg::Bad && !bottom_type()->isa_vectmask()) {
1571 assert((src_lo & 1) == 0 && src_lo + 1 == src_hi &&
1572 (dst_lo & 1) == 0 && dst_lo + 1 == dst_hi,
1573 "expected aligned-adjacent pairs");
1574 }
1575
1576 if (src_lo == dst_lo && src_hi == dst_hi) {
1577 return 0; // Self copy, no move.
1578 }
1579
1580 bool is64 = (src_lo & 1) == 0 && src_lo + 1 == src_hi &&
1581 (dst_lo & 1) == 0 && dst_lo + 1 == dst_hi;
1582 int src_offset = ra_->reg2offset(src_lo);
1583 int dst_offset = ra_->reg2offset(dst_lo);
1584
1585 if (bottom_type()->isa_vect() != nullptr) {
1586 uint ireg = ideal_reg();
1587 if (ireg == Op_VecA && masm) {
1588 int vector_reg_size_in_bytes = Matcher::scalable_vector_reg_size(T_BYTE);
1589 if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
1590 // stack to stack
1591 __ spill_copy_vector_stack_to_stack(src_offset, dst_offset,
1592 vector_reg_size_in_bytes);
1593 } else if (src_lo_rc == rc_vector && dst_lo_rc == rc_stack) {
1594 // vpr to stack
1595 __ spill(as_VectorRegister(Matcher::_regEncode[src_lo]), ra_->reg2offset(dst_lo));
1596 } else if (src_lo_rc == rc_stack && dst_lo_rc == rc_vector) {
1597 // stack to vpr
1598 __ unspill(as_VectorRegister(Matcher::_regEncode[dst_lo]), ra_->reg2offset(src_lo));
1599 } else if (src_lo_rc == rc_vector && dst_lo_rc == rc_vector) {
1600 // vpr to vpr
1601 __ vmv1r_v(as_VectorRegister(Matcher::_regEncode[dst_lo]), as_VectorRegister(Matcher::_regEncode[src_lo]));
1602 } else {
1603 ShouldNotReachHere();
1604 }
1605 } else if (bottom_type()->isa_vectmask() && masm) {
1606 int vmask_size_in_bytes = Matcher::scalable_predicate_reg_slots() * 32 / 8;
1607 if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
1608 // stack to stack
1609 __ spill_copy_vmask_stack_to_stack(src_offset, dst_offset,
1610 vmask_size_in_bytes);
1611 } else if (src_lo_rc == rc_vector && dst_lo_rc == rc_stack) {
1612 // vmask to stack
1613 __ spill_vmask(as_VectorRegister(Matcher::_regEncode[src_lo]), ra_->reg2offset(dst_lo));
1614 } else if (src_lo_rc == rc_stack && dst_lo_rc == rc_vector) {
1615 // stack to vmask
1616 __ unspill_vmask(as_VectorRegister(Matcher::_regEncode[dst_lo]), ra_->reg2offset(src_lo));
1617 } else if (src_lo_rc == rc_vector && dst_lo_rc == rc_vector) {
1618 // vmask to vmask
1619 __ vmv1r_v(as_VectorRegister(Matcher::_regEncode[dst_lo]), as_VectorRegister(Matcher::_regEncode[src_lo]));
1620 } else {
1621 ShouldNotReachHere();
1622 }
1623 }
1624 } else if (masm != nullptr) {
1625 switch (src_lo_rc) {
1626 case rc_int:
1627 if (dst_lo_rc == rc_int) { // gpr --> gpr copy
1628 if (!is64 && this->ideal_reg() != Op_RegI) { // zero extended for narrow oop or klass
1629 __ zext(as_Register(Matcher::_regEncode[dst_lo]), as_Register(Matcher::_regEncode[src_lo]), 32);
1630 } else {
1631 __ mv(as_Register(Matcher::_regEncode[dst_lo]), as_Register(Matcher::_regEncode[src_lo]));
1632 }
1633 } else if (dst_lo_rc == rc_float) { // gpr --> fpr copy
1634 if (is64) {
1635 __ fmv_d_x(as_FloatRegister(Matcher::_regEncode[dst_lo]),
1636 as_Register(Matcher::_regEncode[src_lo]));
1637 } else {
1638 __ fmv_w_x(as_FloatRegister(Matcher::_regEncode[dst_lo]),
1639 as_Register(Matcher::_regEncode[src_lo]));
1640 }
1641 } else { // gpr --> stack spill
1642 assert(dst_lo_rc == rc_stack, "spill to bad register class");
1643 __ spill(as_Register(Matcher::_regEncode[src_lo]), is64, dst_offset);
1644 }
1645 break;
1646 case rc_float:
1647 if (dst_lo_rc == rc_int) { // fpr --> gpr copy
1648 if (is64) {
1649 __ fmv_x_d(as_Register(Matcher::_regEncode[dst_lo]),
1650 as_FloatRegister(Matcher::_regEncode[src_lo]));
1651 } else {
1652 __ fmv_x_w(as_Register(Matcher::_regEncode[dst_lo]),
1653 as_FloatRegister(Matcher::_regEncode[src_lo]));
1654 }
1655 } else if (dst_lo_rc == rc_float) { // fpr --> fpr copy
1656 if (is64) {
1657 __ fmv_d(as_FloatRegister(Matcher::_regEncode[dst_lo]),
1658 as_FloatRegister(Matcher::_regEncode[src_lo]));
1659 } else {
1660 __ fmv_s(as_FloatRegister(Matcher::_regEncode[dst_lo]),
1661 as_FloatRegister(Matcher::_regEncode[src_lo]));
1662 }
1663 } else { // fpr --> stack spill
1664 assert(dst_lo_rc == rc_stack, "spill to bad register class");
1665 __ spill(as_FloatRegister(Matcher::_regEncode[src_lo]),
1666 is64, dst_offset);
1667 }
1668 break;
1669 case rc_stack:
1670 if (dst_lo_rc == rc_int) { // stack --> gpr load
1671 if (this->ideal_reg() == Op_RegI) {
1672 __ unspill(as_Register(Matcher::_regEncode[dst_lo]), is64, src_offset);
1673 } else { // // zero extended for narrow oop or klass
1674 __ unspillu(as_Register(Matcher::_regEncode[dst_lo]), is64, src_offset);
1675 }
1676 } else if (dst_lo_rc == rc_float) { // stack --> fpr load
1677 __ unspill(as_FloatRegister(Matcher::_regEncode[dst_lo]),
1678 is64, src_offset);
1679 } else { // stack --> stack copy
1680 assert(dst_lo_rc == rc_stack, "spill to bad register class");
1681 if (this->ideal_reg() == Op_RegI) {
1682 __ unspill(t0, is64, src_offset);
1683 } else { // zero extended for narrow oop or klass
1684 __ unspillu(t0, is64, src_offset);
1685 }
1686 __ spill(t0, is64, dst_offset);
1687 }
1688 break;
1689 default:
1690 ShouldNotReachHere();
1691 }
1692 }
1693
1694 if (st != nullptr) {
1695 st->print("spill ");
1696 if (src_lo_rc == rc_stack) {
1697 st->print("[sp, #%d] -> ", src_offset);
1698 } else {
1699 st->print("%s -> ", Matcher::regName[src_lo]);
1700 }
1701 if (dst_lo_rc == rc_stack) {
1702 st->print("[sp, #%d]", dst_offset);
1703 } else {
1704 st->print("%s", Matcher::regName[dst_lo]);
1705 }
1706 if (bottom_type()->isa_vect() && !bottom_type()->isa_vectmask()) {
1707 int vsize = 0;
1708 if (ideal_reg() == Op_VecA) {
1709 vsize = Matcher::scalable_vector_reg_size(T_BYTE) * 8;
1710 } else {
1711 ShouldNotReachHere();
1712 }
1713 st->print("\t# vector spill size = %d", vsize);
1714 } else if (ideal_reg() == Op_RegVectMask) {
1715 assert(Matcher::supports_scalable_vector(), "bad register type for spill");
1716 int vsize = Matcher::scalable_predicate_reg_slots() * 32;
1717 st->print("\t# vmask spill size = %d", vsize);
1718 } else {
1719 st->print("\t# spill size = %d", is64 ? 64 : 32);
1720 }
1721 }
1722
1723 return 0;
1724 }
1725
1726 #ifndef PRODUCT
1727 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1728 if (ra_ == nullptr) {
1729 st->print("N%d = SpillCopy(N%d)", _idx, in(1)->_idx);
1730 } else {
1731 implementation(nullptr, ra_, false, st);
1732 }
1733 }
1734 #endif
1735
1736 void MachSpillCopyNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
1737 implementation(masm, ra_, false, nullptr);
1738 }
1739
1740 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1741 return MachNode::size(ra_);
1742 }
1743
1744 //=============================================================================
1745
1746 #ifndef PRODUCT
1747 void BoxLockNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1748 assert_cond(ra_ != nullptr && st != nullptr);
1749 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1750 int reg = ra_->get_reg_first(this);
1751 st->print("add %s, sp, #%d\t# box lock",
1752 Matcher::regName[reg], offset);
1753 }
1754 #endif
1755
1756 void BoxLockNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
1757 Assembler::IncompressibleRegion ir(masm); // Fixed length: see BoxLockNode::size()
1758
1759 assert_cond(ra_ != nullptr);
1760 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1761 int reg = ra_->get_encode(this);
1762
1763 if (Assembler::is_simm12(offset)) {
1764 __ addi(as_Register(reg), sp, offset);
1765 } else {
1766 __ li32(t0, offset);
1767 __ add(as_Register(reg), sp, t0);
1768 }
1769 }
1770
1771 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1772 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_).
1773 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1774
1775 if (Assembler::is_simm12(offset)) {
1776 return NativeInstruction::instruction_size;
1777 } else {
1778 return 3 * NativeInstruction::instruction_size; // lui + addiw + add;
1779 }
1780 }
1781
1782 //=============================================================================
1783
1784 #ifndef PRODUCT
1785 void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1786 {
1787 assert_cond(st != nullptr);
1788 st->print_cr("# MachUEPNode");
1789 if (UseCompressedClassPointers) {
1790 st->print_cr("\tlwu t1, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass");
1791 st->print_cr("\tlwu t2, [t0 + CompiledICData::speculated_klass_offset()]\t# compressed klass");
1792 } else {
1793 st->print_cr("\tld t1, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass");
1794 st->print_cr("\tld t2, [t0 + CompiledICData::speculated_klass_offset()]\t# compressed klass");
1795 }
1796 st->print_cr("\tbeq t1, t2, ic_hit");
1797 st->print_cr("\tj, SharedRuntime::_ic_miss_stub\t # Inline cache check");
1798 st->print_cr("\tic_hit:");
1799 }
1800 #endif
1801
1802 void MachUEPNode::emit(C2_MacroAssembler* masm, PhaseRegAlloc* ra_) const
1803 {
1804 // This is the unverified entry point.
1805 __ ic_check(CodeEntryAlignment);
1806
1807 // Verified entry point must be properly 4 bytes aligned for patching by NativeJump::patch_verified_entry().
1808 // ic_check() aligns to CodeEntryAlignment >= InteriorEntryAlignment(min 16) > NativeInstruction::instruction_size(4).
1809 assert(((__ offset()) % CodeEntryAlignment) == 0, "Misaligned verified entry point");
1810 }
1811
1812 uint MachUEPNode::size(PhaseRegAlloc* ra_) const
1813 {
1814 assert_cond(ra_ != nullptr);
1815 return MachNode::size(ra_);
1816 }
1817
1818 // REQUIRED EMIT CODE
1819
1820 //=============================================================================
1821
1822 // Emit exception handler code.
1823 int HandlerImpl::emit_exception_handler(C2_MacroAssembler* masm)
1824 {
1825 // auipc t1, #exception_blob_entry_point
1826 // jr (offset)t1
1827 // Note that the code buffer's insts_mark is always relative to insts.
1828 // That's why we must use the macroassembler to generate a handler.
1829 address base = __ start_a_stub(size_exception_handler());
1830 if (base == nullptr) {
1831 ciEnv::current()->record_failure("CodeCache is full");
1832 return 0; // CodeBuffer::expand failed
1833 }
1834 int offset = __ offset();
1835 __ far_jump(RuntimeAddress(OptoRuntime::exception_blob()->entry_point()));
1836 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1837 __ end_a_stub();
1838 return offset;
1839 }
1840
1841 // Emit deopt handler code.
1842 int HandlerImpl::emit_deopt_handler(C2_MacroAssembler* masm)
1843 {
1844 address base = __ start_a_stub(size_deopt_handler());
1845 if (base == nullptr) {
1846 ciEnv::current()->record_failure("CodeCache is full");
1847 return 0; // CodeBuffer::expand failed
1848 }
1849 int offset = __ offset();
1850
1851 __ auipc(ra, 0);
1852 __ far_jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
1853
1854 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1855 __ end_a_stub();
1856 return offset;
1857
1858 }
1859 // REQUIRED MATCHER CODE
1860
1861 //=============================================================================
1862
1863 bool Matcher::match_rule_supported(int opcode) {
1864 if (!has_match_rule(opcode)) {
1865 return false;
1866 }
1867
1868 switch (opcode) {
1869 case Op_OnSpinWait:
1870 return VM_Version::supports_on_spin_wait();
1871 case Op_CacheWB: // fall through
1872 case Op_CacheWBPreSync: // fall through
1873 case Op_CacheWBPostSync:
1874 if (!VM_Version::supports_data_cache_line_flush()) {
1875 return false;
1876 }
1877 break;
1878
1879 case Op_StrCompressedCopy: // fall through
1880 case Op_StrInflatedCopy: // fall through
1881 case Op_CountPositives: // fall through
1882 case Op_EncodeISOArray:
1883 return UseRVV;
1884
1885 // Current test shows that, it brings performance gain when MaxVectorSize >= 32, but brings
1886 // regression when MaxVectorSize == 16. So only enable the intrinsic when MaxVectorSize >= 32.
1887 case Op_RoundVF:
1888 return UseRVV && MaxVectorSize >= 32;
1889
1890 // For double, current test shows that even with MaxVectorSize == 32, there is still some regression.
1891 // Although there is no hardware to verify it for now, from the trend of performance data on hardwares
1892 // (with vlenb == 16 and 32 respectively), it's promising to bring better performance rather than
1893 // regression for double when MaxVectorSize == 64+. So only enable the intrinsic when MaxVectorSize >= 64.
1894 case Op_RoundVD:
1895 return UseRVV && MaxVectorSize >= 64;
1896
1897 case Op_PopCountI:
1898 case Op_PopCountL:
1899 return UsePopCountInstruction;
1900
1901 case Op_ReverseBytesI:
1902 case Op_ReverseBytesL:
1903 case Op_ReverseBytesS:
1904 case Op_ReverseBytesUS:
1905 case Op_RotateRight:
1906 case Op_RotateLeft:
1907 case Op_CountLeadingZerosI:
1908 case Op_CountLeadingZerosL:
1909 case Op_CountTrailingZerosI:
1910 case Op_CountTrailingZerosL:
1911 return UseZbb;
1912
1913 case Op_FmaF:
1914 case Op_FmaD:
1915 case Op_FmaVF:
1916 case Op_FmaVD:
1917 return UseFMA;
1918
1919 case Op_ConvHF2F:
1920 case Op_ConvF2HF:
1921 return UseZfh || UseZfhmin;
1922 }
1923
1924 return true; // Per default match rules are supported.
1925 }
1926
1927 const RegMask* Matcher::predicate_reg_mask(void) {
1928 return &_VMASK_REG_mask;
1929 }
1930
1931 // Vector calling convention not yet implemented.
1932 bool Matcher::supports_vector_calling_convention(void) {
1933 return EnableVectorSupport && UseVectorStubs;
1934 }
1935
1936 OptoRegPair Matcher::vector_return_value(uint ideal_reg) {
1937 assert(EnableVectorSupport && UseVectorStubs, "sanity");
1938 assert(ideal_reg == Op_VecA, "sanity");
1939 // check more info at https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-cc.adoc
1940 int lo = V8_num;
1941 int hi = V8_K_num;
1942 return OptoRegPair(hi, lo);
1943 }
1944
1945 // Is this branch offset short enough that a short branch can be used?
1946 //
1947 // NOTE: If the platform does not provide any short branch variants, then
1948 // this method should return false for offset 0.
1949 // |---label(L1)-----|
1950 // |-----------------|
1951 // |-----------------|----------eq: float-------------------
1952 // |-----------------| // far_cmpD_branch | cmpD_branch
1953 // |------- ---------| feq; | feq;
1954 // |-far_cmpD_branch-| beqz done; | bnez L;
1955 // |-----------------| j L; |
1956 // |-----------------| bind(done); |
1957 // |-----------------|--------------------------------------
1958 // |-----------------| // so shortBrSize = br_size - 4;
1959 // |-----------------| // so offs = offset - shortBrSize + 4;
1960 // |---label(L2)-----|
1961 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1962 // The passed offset is relative to address of the branch.
1963 int shortBrSize = br_size - 4;
1964 int offs = offset - shortBrSize + 4;
1965 return (-4096 <= offs && offs < 4096);
1966 }
1967
1968 // Vector width in bytes.
1969 int Matcher::vector_width_in_bytes(BasicType bt) {
1970 if (UseRVV) {
1971 // The MaxVectorSize should have been set by detecting RVV max vector register size when check UseRVV.
1972 // MaxVectorSize == VM_Version::_initial_vector_length
1973 int size = MaxVectorSize;
1974 // Minimum 2 values in vector
1975 if (size < 2 * type2aelembytes(bt)) size = 0;
1976 // But never < 4
1977 if (size < 4) size = 0;
1978 return size;
1979 }
1980 return 0;
1981 }
1982
1983 // Limits on vector size (number of elements) loaded into vector.
1984 int Matcher::max_vector_size(const BasicType bt) {
1985 return vector_width_in_bytes(bt) / type2aelembytes(bt);
1986 }
1987
1988 int Matcher::min_vector_size(const BasicType bt) {
1989 int max_size = max_vector_size(bt);
1990 // Limit the min vector size to 8 bytes.
1991 int size = 8 / type2aelembytes(bt);
1992 if (bt == T_BYTE) {
1993 // To support vector api shuffle/rearrange.
1994 size = 4;
1995 } else if (bt == T_BOOLEAN) {
1996 // To support vector api load/store mask.
1997 size = 2;
1998 }
1999 if (size < 2) size = 2;
2000 return MIN2(size, max_size);
2001 }
2002
2003 int Matcher::max_vector_size_auto_vectorization(const BasicType bt) {
2004 return Matcher::max_vector_size(bt);
2005 }
2006
2007 // Vector ideal reg.
2008 uint Matcher::vector_ideal_reg(int len) {
2009 assert(MaxVectorSize >= len, "");
2010 if (UseRVV) {
2011 return Op_VecA;
2012 }
2013
2014 ShouldNotReachHere();
2015 return 0;
2016 }
2017
2018 int Matcher::scalable_vector_reg_size(const BasicType bt) {
2019 return Matcher::max_vector_size(bt);
2020 }
2021
2022 MachOper* Matcher::pd_specialize_generic_vector_operand(MachOper* original_opnd, uint ideal_reg, bool is_temp) {
2023 ShouldNotReachHere(); // generic vector operands not supported
2024 return nullptr;
2025 }
2026
2027 bool Matcher::is_reg2reg_move(MachNode* m) {
2028 ShouldNotReachHere(); // generic vector operands not supported
2029 return false;
2030 }
2031
2032 bool Matcher::is_generic_vector(MachOper* opnd) {
2033 ShouldNotReachHere(); // generic vector operands not supported
2034 return false;
2035 }
2036
2037 // Return whether or not this register is ever used as an argument.
2038 // This function is used on startup to build the trampoline stubs in
2039 // generateOptoStub. Registers not mentioned will be killed by the VM
2040 // call in the trampoline, and arguments in those registers not be
2041 // available to the callee.
2042 bool Matcher::can_be_java_arg(int reg)
2043 {
2044 return
2045 reg == R10_num || reg == R10_H_num ||
2046 reg == R11_num || reg == R11_H_num ||
2047 reg == R12_num || reg == R12_H_num ||
2048 reg == R13_num || reg == R13_H_num ||
2049 reg == R14_num || reg == R14_H_num ||
2050 reg == R15_num || reg == R15_H_num ||
2051 reg == R16_num || reg == R16_H_num ||
2052 reg == R17_num || reg == R17_H_num ||
2053 reg == F10_num || reg == F10_H_num ||
2054 reg == F11_num || reg == F11_H_num ||
2055 reg == F12_num || reg == F12_H_num ||
2056 reg == F13_num || reg == F13_H_num ||
2057 reg == F14_num || reg == F14_H_num ||
2058 reg == F15_num || reg == F15_H_num ||
2059 reg == F16_num || reg == F16_H_num ||
2060 reg == F17_num || reg == F17_H_num;
2061 }
2062
2063 bool Matcher::is_spillable_arg(int reg)
2064 {
2065 return can_be_java_arg(reg);
2066 }
2067
2068 uint Matcher::int_pressure_limit()
2069 {
2070 // A derived pointer is live at CallNode and then is flagged by RA
2071 // as a spilled LRG. Spilling heuristics(Spill-USE) explicitly skip
2072 // derived pointers and lastly fail to spill after reaching maximum
2073 // number of iterations. Lowering the default pressure threshold to
2074 // (_NO_SPECIAL_REG32_mask.Size() minus 1) forces CallNode to become
2075 // a high register pressure area of the code so that split_DEF can
2076 // generate DefinitionSpillCopy for the derived pointer.
2077 uint default_int_pressure_threshold = _NO_SPECIAL_REG32_mask.Size() - 1;
2078 if (!PreserveFramePointer) {
2079 // When PreserveFramePointer is off, frame pointer is allocatable,
2080 // but different from other SOC registers, it is excluded from
2081 // fatproj's mask because its save type is No-Save. Decrease 1 to
2082 // ensure high pressure at fatproj when PreserveFramePointer is off.
2083 // See check_pressure_at_fatproj().
2084 default_int_pressure_threshold--;
2085 }
2086 return (INTPRESSURE == -1) ? default_int_pressure_threshold : INTPRESSURE;
2087 }
2088
2089 uint Matcher::float_pressure_limit()
2090 {
2091 // _FLOAT_REG_mask is generated by adlc from the float_reg register class.
2092 return (FLOATPRESSURE == -1) ? _FLOAT_REG_mask.Size() : FLOATPRESSURE;
2093 }
2094
2095 bool Matcher::use_asm_for_ldiv_by_con(jlong divisor) {
2096 return false;
2097 }
2098
2099 RegMask Matcher::divI_proj_mask() {
2100 ShouldNotReachHere();
2101 return RegMask();
2102 }
2103
2104 // Register for MODI projection of divmodI.
2105 RegMask Matcher::modI_proj_mask() {
2106 ShouldNotReachHere();
2107 return RegMask();
2108 }
2109
2110 // Register for DIVL projection of divmodL.
2111 RegMask Matcher::divL_proj_mask() {
2112 ShouldNotReachHere();
2113 return RegMask();
2114 }
2115
2116 // Register for MODL projection of divmodL.
2117 RegMask Matcher::modL_proj_mask() {
2118 ShouldNotReachHere();
2119 return RegMask();
2120 }
2121
2122 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
2123 return FP_REG_mask();
2124 }
2125
2126 bool size_fits_all_mem_uses(AddPNode* addp, int shift) {
2127 assert_cond(addp != nullptr);
2128 for (DUIterator_Fast imax, i = addp->fast_outs(imax); i < imax; i++) {
2129 Node* u = addp->fast_out(i);
2130 if (u != nullptr && u->is_Mem()) {
2131 int opsize = u->as_Mem()->memory_size();
2132 assert(opsize > 0, "unexpected memory operand size");
2133 if (u->as_Mem()->memory_size() != (1 << shift)) {
2134 return false;
2135 }
2136 }
2137 }
2138 return true;
2139 }
2140
2141 // Binary src (Replicate scalar/immediate)
2142 static bool is_vector_scalar_bitwise_pattern(Node* n, Node* m) {
2143 if (n == nullptr || m == nullptr) {
2144 return false;
2145 }
2146
2147 if (m->Opcode() != Op_Replicate) {
2148 return false;
2149 }
2150
2151 switch (n->Opcode()) {
2152 case Op_AndV:
2153 case Op_OrV:
2154 case Op_XorV:
2155 case Op_AddVB:
2156 case Op_AddVS:
2157 case Op_AddVI:
2158 case Op_AddVL:
2159 case Op_SubVB:
2160 case Op_SubVS:
2161 case Op_SubVI:
2162 case Op_SubVL:
2163 case Op_MulVB:
2164 case Op_MulVS:
2165 case Op_MulVI:
2166 case Op_MulVL: {
2167 return true;
2168 }
2169 default:
2170 return false;
2171 }
2172 }
2173
2174 // (XorV src (Replicate m1))
2175 // (XorVMask src (MaskAll m1))
2176 static bool is_vector_bitwise_not_pattern(Node* n, Node* m) {
2177 if (n != nullptr && m != nullptr) {
2178 return (n->Opcode() == Op_XorV || n->Opcode() == Op_XorVMask) &&
2179 VectorNode::is_all_ones_vector(m);
2180 }
2181 return false;
2182 }
2183
2184 // Should the Matcher clone input 'm' of node 'n'?
2185 bool Matcher::pd_clone_node(Node* n, Node* m, Matcher::MStack& mstack) {
2186 assert_cond(m != nullptr);
2187 if (is_vshift_con_pattern(n, m) || // ShiftV src (ShiftCntV con)
2188 is_vector_bitwise_not_pattern(n, m) ||
2189 is_vector_scalar_bitwise_pattern(n, m) ||
2190 is_encode_and_store_pattern(n, m)) {
2191 mstack.push(m, Visit);
2192 return true;
2193 }
2194 return false;
2195 }
2196
2197 // Should the Matcher clone shifts on addressing modes, expecting them
2198 // to be subsumed into complex addressing expressions or compute them
2199 // into registers?
2200 bool Matcher::pd_clone_address_expressions(AddPNode* m, Matcher::MStack& mstack, VectorSet& address_visited) {
2201 return clone_base_plus_offset_address(m, mstack, address_visited);
2202 }
2203
2204 %}
2205
2206
2207
2208 //----------ENCODING BLOCK-----------------------------------------------------
2209 // This block specifies the encoding classes used by the compiler to
2210 // output byte streams. Encoding classes are parameterized macros
2211 // used by Machine Instruction Nodes in order to generate the bit
2212 // encoding of the instruction. Operands specify their base encoding
2213 // interface with the interface keyword. There are currently
2214 // supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, &
2215 // COND_INTER. REG_INTER causes an operand to generate a function
2216 // which returns its register number when queried. CONST_INTER causes
2217 // an operand to generate a function which returns the value of the
2218 // constant when queried. MEMORY_INTER causes an operand to generate
2219 // four functions which return the Base Register, the Index Register,
2220 // the Scale Value, and the Offset Value of the operand when queried.
2221 // COND_INTER causes an operand to generate six functions which return
2222 // the encoding code (ie - encoding bits for the instruction)
2223 // associated with each basic boolean condition for a conditional
2224 // instruction.
2225 //
2226 // Instructions specify two basic values for encoding. Again, a
2227 // function is available to check if the constant displacement is an
2228 // oop. They use the ins_encode keyword to specify their encoding
2229 // classes (which must be a sequence of enc_class names, and their
2230 // parameters, specified in the encoding block), and they use the
2231 // opcode keyword to specify, in order, their primary, secondary, and
2232 // tertiary opcode. Only the opcode sections which a particular
2233 // instruction needs for encoding need to be specified.
2234 encode %{
2235 // BEGIN Non-volatile memory access
2236
2237 enc_class riscv_enc_mov_imm(iRegIorL dst, immIorL src) %{
2238 int64_t con = (int64_t)$src$$constant;
2239 Register dst_reg = as_Register($dst$$reg);
2240 __ mv(dst_reg, con);
2241 %}
2242
2243 enc_class riscv_enc_mov_p(iRegP dst, immP src) %{
2244 Register dst_reg = as_Register($dst$$reg);
2245 address con = (address)$src$$constant;
2246 if (con == nullptr || con == (address)1) {
2247 ShouldNotReachHere();
2248 } else {
2249 relocInfo::relocType rtype = $src->constant_reloc();
2250 if (rtype == relocInfo::oop_type) {
2251 __ movoop(dst_reg, (jobject)con);
2252 } else if (rtype == relocInfo::metadata_type) {
2253 __ mov_metadata(dst_reg, (Metadata*)con);
2254 } else {
2255 assert(rtype == relocInfo::none, "unexpected reloc type");
2256 __ mv(dst_reg, $src$$constant);
2257 }
2258 }
2259 %}
2260
2261 enc_class riscv_enc_mov_p1(iRegP dst) %{
2262 Register dst_reg = as_Register($dst$$reg);
2263 __ mv(dst_reg, 1);
2264 %}
2265
2266 enc_class riscv_enc_mov_byte_map_base(iRegP dst) %{
2267 __ load_byte_map_base($dst$$Register);
2268 %}
2269
2270 enc_class riscv_enc_mov_n(iRegN dst, immN src) %{
2271 Register dst_reg = as_Register($dst$$reg);
2272 address con = (address)$src$$constant;
2273 if (con == nullptr) {
2274 ShouldNotReachHere();
2275 } else {
2276 relocInfo::relocType rtype = $src->constant_reloc();
2277 assert(rtype == relocInfo::oop_type, "unexpected reloc type");
2278 __ set_narrow_oop(dst_reg, (jobject)con);
2279 }
2280 %}
2281
2282 enc_class riscv_enc_mov_zero(iRegNorP dst) %{
2283 Register dst_reg = as_Register($dst$$reg);
2284 __ mv(dst_reg, zr);
2285 %}
2286
2287 enc_class riscv_enc_mov_nk(iRegN dst, immNKlass src) %{
2288 Register dst_reg = as_Register($dst$$reg);
2289 address con = (address)$src$$constant;
2290 if (con == nullptr) {
2291 ShouldNotReachHere();
2292 } else {
2293 relocInfo::relocType rtype = $src->constant_reloc();
2294 assert(rtype == relocInfo::metadata_type, "unexpected reloc type");
2295 __ set_narrow_klass(dst_reg, (Klass *)con);
2296 }
2297 %}
2298
2299 enc_class riscv_enc_cmpxchgw(iRegINoSp res, memory mem, iRegI oldval, iRegI newval) %{
2300 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
2301 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
2302 /*result as bool*/ true);
2303 %}
2304
2305 enc_class riscv_enc_cmpxchgn(iRegINoSp res, memory mem, iRegI oldval, iRegI newval) %{
2306 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
2307 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
2308 /*result as bool*/ true);
2309 %}
2310
2311 enc_class riscv_enc_cmpxchg(iRegINoSp res, memory mem, iRegL oldval, iRegL newval) %{
2312 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
2313 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
2314 /*result as bool*/ true);
2315 %}
2316
2317 enc_class riscv_enc_cmpxchgw_acq(iRegINoSp res, memory mem, iRegI oldval, iRegI newval) %{
2318 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
2319 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
2320 /*result as bool*/ true);
2321 %}
2322
2323 enc_class riscv_enc_cmpxchgn_acq(iRegINoSp res, memory mem, iRegI oldval, iRegI newval) %{
2324 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
2325 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
2326 /*result as bool*/ true);
2327 %}
2328
2329 enc_class riscv_enc_cmpxchg_acq(iRegINoSp res, memory mem, iRegL oldval, iRegL newval) %{
2330 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
2331 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
2332 /*result as bool*/ true);
2333 %}
2334
2335 // compare and branch instruction encodings
2336
2337 enc_class riscv_enc_j(label lbl) %{
2338 Label* L = $lbl$$label;
2339 __ j(*L);
2340 %}
2341
2342 enc_class riscv_enc_far_cmpULtGe_imm0_branch(cmpOpULtGe cmp, iRegIorL op1, label lbl) %{
2343 Label* L = $lbl$$label;
2344 switch ($cmp$$cmpcode) {
2345 case(BoolTest::ge):
2346 __ j(*L);
2347 break;
2348 case(BoolTest::lt):
2349 break;
2350 default:
2351 Unimplemented();
2352 }
2353 %}
2354
2355 // call instruction encodings
2356
2357 enc_class riscv_enc_partial_subtype_check(iRegP sub, iRegP super, iRegP temp, iRegP result) %{
2358 Register sub_reg = as_Register($sub$$reg);
2359 Register super_reg = as_Register($super$$reg);
2360 Register temp_reg = as_Register($temp$$reg);
2361 Register result_reg = as_Register($result$$reg);
2362 Register cr_reg = t1;
2363
2364 Label miss;
2365 Label done;
2366 __ check_klass_subtype_slow_path(sub_reg, super_reg, temp_reg, result_reg,
2367 nullptr, &miss, /*set_cond_codes*/ true);
2368 if ($primary) {
2369 __ mv(result_reg, zr);
2370 } else {
2371 __ mv(cr_reg, zr);
2372 __ j(done);
2373 }
2374
2375 __ bind(miss);
2376 if (!$primary) {
2377 __ mv(cr_reg, 1);
2378 }
2379
2380 __ bind(done);
2381 %}
2382
2383 enc_class riscv_enc_java_static_call(method meth) %{
2384 Assembler::IncompressibleRegion ir(masm); // Fixed length: see ret_addr_offset
2385
2386 address addr = (address)$meth$$method;
2387 address call = nullptr;
2388 assert_cond(addr != nullptr);
2389 if (!_method) {
2390 // A call to a runtime wrapper, e.g. new, new_typeArray_Java, uncommon_trap.
2391 call = __ reloc_call(Address(addr, relocInfo::runtime_call_type));
2392 if (call == nullptr) {
2393 ciEnv::current()->record_failure("CodeCache is full");
2394 return;
2395 }
2396 } else if (_method->intrinsic_id() == vmIntrinsicID::_ensureMaterializedForStackWalk) {
2397 // The NOP here is purely to ensure that eliding a call to
2398 // JVM_EnsureMaterializedForStackWalk doesn't change the code size.
2399 __ nop();
2400 __ nop();
2401 __ nop();
2402 __ block_comment("call JVM_EnsureMaterializedForStackWalk (elided)");
2403 } else {
2404 int method_index = resolved_method_index(masm);
2405 RelocationHolder rspec = _optimized_virtual ? opt_virtual_call_Relocation::spec(method_index)
2406 : static_call_Relocation::spec(method_index);
2407 call = __ reloc_call(Address(addr, rspec));
2408 if (call == nullptr) {
2409 ciEnv::current()->record_failure("CodeCache is full");
2410 return;
2411 }
2412
2413 if (CodeBuffer::supports_shared_stubs() && _method->can_be_statically_bound()) {
2414 // Calls of the same statically bound method can share
2415 // a stub to the interpreter.
2416 __ code()->shared_stub_to_interp_for(_method, call - (__ begin()));
2417 } else {
2418 // Emit stub for static call
2419 address stub = CompiledDirectCall::emit_to_interp_stub(masm, call);
2420 if (stub == nullptr) {
2421 ciEnv::current()->record_failure("CodeCache is full");
2422 return;
2423 }
2424 }
2425 }
2426
2427 __ post_call_nop();
2428 %}
2429
2430 enc_class riscv_enc_java_dynamic_call(method meth) %{
2431 Assembler::IncompressibleRegion ir(masm); // Fixed length: see ret_addr_offset
2432 int method_index = resolved_method_index(masm);
2433 address call = __ ic_call((address)$meth$$method, method_index);
2434 if (call == nullptr) {
2435 ciEnv::current()->record_failure("CodeCache is full");
2436 return;
2437 }
2438
2439 __ post_call_nop();
2440 %}
2441
2442 enc_class riscv_enc_call_epilog() %{
2443 if (VerifyStackAtCalls) {
2444 // Check that stack depth is unchanged: find majik cookie on stack
2445 __ call_Unimplemented();
2446 }
2447 %}
2448
2449 enc_class riscv_enc_java_to_runtime(method meth) %{
2450 Assembler::IncompressibleRegion ir(masm); // Fixed length: see ret_addr_offset
2451
2452 // Some calls to generated routines (arraycopy code) are scheduled by C2
2453 // as runtime calls. if so we can call them using a far call (they will be
2454 // in the code cache, thus in a reachable segment) otherwise we have to use
2455 // a movptr+jalr pair which loads the absolute address into a register.
2456 address entry = (address)$meth$$method;
2457 if (CodeCache::contains(entry)) {
2458 __ far_call(Address(entry, relocInfo::runtime_call_type));
2459 __ post_call_nop();
2460 } else {
2461 Label retaddr;
2462 // Make the anchor frame walkable
2463 __ la(t0, retaddr);
2464 __ sd(t0, Address(xthread, JavaThread::last_Java_pc_offset()));
2465 int32_t offset = 0;
2466 // No relocation needed
2467 __ movptr(t1, entry, offset, t0); // lui + lui + slli + add
2468 __ jalr(t1, offset);
2469 __ bind(retaddr);
2470 __ post_call_nop();
2471 }
2472 %}
2473
2474 // arithmetic encodings
2475
2476 enc_class riscv_enc_divw(iRegI dst, iRegI src1, iRegI src2) %{
2477 Register dst_reg = as_Register($dst$$reg);
2478 Register src1_reg = as_Register($src1$$reg);
2479 Register src2_reg = as_Register($src2$$reg);
2480 __ corrected_idivl(dst_reg, src1_reg, src2_reg, /* want_remainder */ false, /* is_signed */ true);
2481 %}
2482
2483 enc_class riscv_enc_divuw(iRegI dst, iRegI src1, iRegI src2) %{
2484 Register dst_reg = as_Register($dst$$reg);
2485 Register src1_reg = as_Register($src1$$reg);
2486 Register src2_reg = as_Register($src2$$reg);
2487 __ corrected_idivl(dst_reg, src1_reg, src2_reg, /* want_remainder */ false, /* is_signed */ false);
2488 %}
2489
2490 enc_class riscv_enc_div(iRegI dst, iRegI src1, iRegI src2) %{
2491 Register dst_reg = as_Register($dst$$reg);
2492 Register src1_reg = as_Register($src1$$reg);
2493 Register src2_reg = as_Register($src2$$reg);
2494 __ corrected_idivq(dst_reg, src1_reg, src2_reg, /* want_remainder */ false, /* is_signed */ true);
2495 %}
2496
2497 enc_class riscv_enc_divu(iRegI dst, iRegI src1, iRegI src2) %{
2498 Register dst_reg = as_Register($dst$$reg);
2499 Register src1_reg = as_Register($src1$$reg);
2500 Register src2_reg = as_Register($src2$$reg);
2501 __ corrected_idivq(dst_reg, src1_reg, src2_reg, /* want_remainder */ false, /* is_signed */ false);
2502 %}
2503
2504 enc_class riscv_enc_modw(iRegI dst, iRegI src1, iRegI src2) %{
2505 Register dst_reg = as_Register($dst$$reg);
2506 Register src1_reg = as_Register($src1$$reg);
2507 Register src2_reg = as_Register($src2$$reg);
2508 __ corrected_idivl(dst_reg, src1_reg, src2_reg, /* want_remainder */ true, /* is_signed */ true);
2509 %}
2510
2511 enc_class riscv_enc_moduw(iRegI dst, iRegI src1, iRegI src2) %{
2512 Register dst_reg = as_Register($dst$$reg);
2513 Register src1_reg = as_Register($src1$$reg);
2514 Register src2_reg = as_Register($src2$$reg);
2515 __ corrected_idivl(dst_reg, src1_reg, src2_reg, /* want_remainder */ true, /* is_signed */ false);
2516 %}
2517
2518 enc_class riscv_enc_mod(iRegI dst, iRegI src1, iRegI src2) %{
2519 Register dst_reg = as_Register($dst$$reg);
2520 Register src1_reg = as_Register($src1$$reg);
2521 Register src2_reg = as_Register($src2$$reg);
2522 __ corrected_idivq(dst_reg, src1_reg, src2_reg, /* want_remainder */ true, /* is_signed */ true);
2523 %}
2524
2525 enc_class riscv_enc_modu(iRegI dst, iRegI src1, iRegI src2) %{
2526 Register dst_reg = as_Register($dst$$reg);
2527 Register src1_reg = as_Register($src1$$reg);
2528 Register src2_reg = as_Register($src2$$reg);
2529 __ corrected_idivq(dst_reg, src1_reg, src2_reg, /* want_remainder */ true, /* is_signed */ false);
2530 %}
2531
2532 enc_class riscv_enc_tail_call(iRegP jump_target) %{
2533 Register target_reg = as_Register($jump_target$$reg);
2534 __ jr(target_reg);
2535 %}
2536
2537 enc_class riscv_enc_tail_jmp(iRegP jump_target) %{
2538 Register target_reg = as_Register($jump_target$$reg);
2539 // exception oop should be in x10
2540 // ret addr has been popped into ra
2541 // callee expects it in x13
2542 __ mv(x13, ra);
2543 __ jr(target_reg);
2544 %}
2545
2546 enc_class riscv_enc_rethrow() %{
2547 __ far_jump(RuntimeAddress(OptoRuntime::rethrow_stub()));
2548 %}
2549
2550 enc_class riscv_enc_ret() %{
2551 __ ret();
2552 %}
2553
2554 %}
2555
2556 //----------FRAME--------------------------------------------------------------
2557 // Definition of frame structure and management information.
2558 //
2559 // S T A C K L A Y O U T Allocators stack-slot number
2560 // | (to get allocators register number
2561 // G Owned by | | v add OptoReg::stack0())
2562 // r CALLER | |
2563 // o | +--------+ pad to even-align allocators stack-slot
2564 // w V | pad0 | numbers; owned by CALLER
2565 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
2566 // h ^ | in | 5
2567 // | | args | 4 Holes in incoming args owned by SELF
2568 // | | | | 3
2569 // | | +--------+
2570 // V | | old out| Empty on Intel, window on Sparc
2571 // | old |preserve| Must be even aligned.
2572 // | SP-+--------+----> Matcher::_old_SP, even aligned
2573 // | | in | 3 area for Intel ret address
2574 // Owned by |preserve| Empty on Sparc.
2575 // SELF +--------+
2576 // | | pad2 | 2 pad to align old SP
2577 // | +--------+ 1
2578 // | | locks | 0
2579 // | +--------+----> OptoReg::stack0(), even aligned
2580 // | | pad1 | 11 pad to align new SP
2581 // | +--------+
2582 // | | | 10
2583 // | | spills | 9 spills
2584 // V | | 8 (pad0 slot for callee)
2585 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
2586 // ^ | out | 7
2587 // | | args | 6 Holes in outgoing args owned by CALLEE
2588 // Owned by +--------+
2589 // CALLEE | new out| 6 Empty on Intel, window on Sparc
2590 // | new |preserve| Must be even-aligned.
2591 // | SP-+--------+----> Matcher::_new_SP, even aligned
2592 // | | |
2593 //
2594 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
2595 // known from SELF's arguments and the Java calling convention.
2596 // Region 6-7 is determined per call site.
2597 // Note 2: If the calling convention leaves holes in the incoming argument
2598 // area, those holes are owned by SELF. Holes in the outgoing area
2599 // are owned by the CALLEE. Holes should not be necessary in the
2600 // incoming area, as the Java calling convention is completely under
2601 // the control of the AD file. Doubles can be sorted and packed to
2602 // avoid holes. Holes in the outgoing arguments may be necessary for
2603 // varargs C calling conventions.
2604 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
2605 // even aligned with pad0 as needed.
2606 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
2607 // (the latter is true on Intel but is it false on RISCV?)
2608 // region 6-11 is even aligned; it may be padded out more so that
2609 // the region from SP to FP meets the minimum stack alignment.
2610 // Note 4: For I2C adapters, the incoming FP may not meet the minimum stack
2611 // alignment. Region 11, pad1, may be dynamically extended so that
2612 // SP meets the minimum alignment.
2613
2614 frame %{
2615 // These three registers define part of the calling convention
2616 // between compiled code and the interpreter.
2617
2618 // Inline Cache Register or methodOop for I2C.
2619 inline_cache_reg(R31);
2620
2621 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
2622 cisc_spilling_operand_name(indOffset);
2623
2624 // Number of stack slots consumed by locking an object
2625 // generate Compile::sync_stack_slots
2626 // VMRegImpl::slots_per_word = wordSize / stack_slot_size = 8 / 4 = 2
2627 sync_stack_slots(1 * VMRegImpl::slots_per_word);
2628
2629 // Compiled code's Frame Pointer
2630 frame_pointer(R2);
2631
2632 // Interpreter stores its frame pointer in a register which is
2633 // stored to the stack by I2CAdaptors.
2634 // I2CAdaptors convert from interpreted java to compiled java.
2635 interpreter_frame_pointer(R8);
2636
2637 // Stack alignment requirement
2638 stack_alignment(StackAlignmentInBytes); // Alignment size in bytes (128-bit -> 16 bytes)
2639
2640 // Number of outgoing stack slots killed above the out_preserve_stack_slots
2641 // for calls to C. Supports the var-args backing area for register parms.
2642 varargs_C_out_slots_killed(frame::arg_reg_save_area_bytes / BytesPerInt);
2643
2644 // The after-PROLOG location of the return address. Location of
2645 // return address specifies a type (REG or STACK) and a number
2646 // representing the register number (i.e. - use a register name) or
2647 // stack slot.
2648 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
2649 // Otherwise, it is above the locks and verification slot and alignment word
2650 // TODO this may well be correct but need to check why that - 2 is there
2651 // ppc port uses 0 but we definitely need to allow for fixed_slots
2652 // which folds in the space used for monitors
2653 return_addr(STACK - 2 +
2654 align_up((Compile::current()->in_preserve_stack_slots() +
2655 Compile::current()->fixed_slots()),
2656 stack_alignment_in_slots()));
2657
2658 // Location of compiled Java return values. Same as C for now.
2659 return_value
2660 %{
2661 assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL,
2662 "only return normal values");
2663
2664 static const int lo[Op_RegL + 1] = { // enum name
2665 0, // Op_Node
2666 0, // Op_Set
2667 R10_num, // Op_RegN
2668 R10_num, // Op_RegI
2669 R10_num, // Op_RegP
2670 F10_num, // Op_RegF
2671 F10_num, // Op_RegD
2672 R10_num // Op_RegL
2673 };
2674
2675 static const int hi[Op_RegL + 1] = { // enum name
2676 0, // Op_Node
2677 0, // Op_Set
2678 OptoReg::Bad, // Op_RegN
2679 OptoReg::Bad, // Op_RegI
2680 R10_H_num, // Op_RegP
2681 OptoReg::Bad, // Op_RegF
2682 F10_H_num, // Op_RegD
2683 R10_H_num // Op_RegL
2684 };
2685
2686 return OptoRegPair(hi[ideal_reg], lo[ideal_reg]);
2687 %}
2688 %}
2689
2690 //----------ATTRIBUTES---------------------------------------------------------
2691 //----------Operand Attributes-------------------------------------------------
2692 op_attrib op_cost(1); // Required cost attribute
2693
2694 //----------Instruction Attributes---------------------------------------------
2695 ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute
2696 ins_attrib ins_size(32); // Required size attribute (in bits)
2697 ins_attrib ins_short_branch(0); // Required flag: is this instruction
2698 // a non-matching short branch variant
2699 // of some long branch?
2700 ins_attrib ins_alignment(4); // Required alignment attribute (must
2701 // be a power of 2) specifies the
2702 // alignment that some part of the
2703 // instruction (not necessarily the
2704 // start) requires. If > 1, a
2705 // compute_padding() function must be
2706 // provided for the instruction
2707
2708 //----------OPERANDS-----------------------------------------------------------
2709 // Operand definitions must precede instruction definitions for correct parsing
2710 // in the ADLC because operands constitute user defined types which are used in
2711 // instruction definitions.
2712
2713 //----------Simple Operands----------------------------------------------------
2714
2715 // Integer operands 32 bit
2716 // 32 bit immediate
2717 operand immI()
2718 %{
2719 match(ConI);
2720
2721 op_cost(0);
2722 format %{ %}
2723 interface(CONST_INTER);
2724 %}
2725
2726 // 32 bit zero
2727 operand immI0()
2728 %{
2729 predicate(n->get_int() == 0);
2730 match(ConI);
2731
2732 op_cost(0);
2733 format %{ %}
2734 interface(CONST_INTER);
2735 %}
2736
2737 // 32 bit unit increment
2738 operand immI_1()
2739 %{
2740 predicate(n->get_int() == 1);
2741 match(ConI);
2742
2743 op_cost(0);
2744 format %{ %}
2745 interface(CONST_INTER);
2746 %}
2747
2748 // 32 bit unit decrement
2749 operand immI_M1()
2750 %{
2751 predicate(n->get_int() == -1);
2752 match(ConI);
2753
2754 op_cost(0);
2755 format %{ %}
2756 interface(CONST_INTER);
2757 %}
2758
2759 // Unsigned Integer Immediate: 6-bit int, greater than 32
2760 operand uimmI6_ge32() %{
2761 predicate(((unsigned int)(n->get_int()) < 64) && (n->get_int() >= 32));
2762 match(ConI);
2763 op_cost(0);
2764 format %{ %}
2765 interface(CONST_INTER);
2766 %}
2767
2768 operand immI_le_4()
2769 %{
2770 predicate(n->get_int() <= 4);
2771 match(ConI);
2772
2773 op_cost(0);
2774 format %{ %}
2775 interface(CONST_INTER);
2776 %}
2777
2778 operand immI_16()
2779 %{
2780 predicate(n->get_int() == 16);
2781 match(ConI);
2782 op_cost(0);
2783 format %{ %}
2784 interface(CONST_INTER);
2785 %}
2786
2787 operand immI_24()
2788 %{
2789 predicate(n->get_int() == 24);
2790 match(ConI);
2791 op_cost(0);
2792 format %{ %}
2793 interface(CONST_INTER);
2794 %}
2795
2796 operand immI_31()
2797 %{
2798 predicate(n->get_int() == 31);
2799 match(ConI);
2800
2801 op_cost(0);
2802 format %{ %}
2803 interface(CONST_INTER);
2804 %}
2805
2806 operand immI_63()
2807 %{
2808 predicate(n->get_int() == 63);
2809 match(ConI);
2810
2811 op_cost(0);
2812 format %{ %}
2813 interface(CONST_INTER);
2814 %}
2815
2816 // 32 bit integer valid for add immediate
2817 operand immIAdd()
2818 %{
2819 predicate(Assembler::is_simm12((int64_t)n->get_int()));
2820 match(ConI);
2821 op_cost(0);
2822 format %{ %}
2823 interface(CONST_INTER);
2824 %}
2825
2826 // 32 bit integer valid for sub immediate
2827 operand immISub()
2828 %{
2829 predicate(Assembler::is_simm12(-(int64_t)n->get_int()));
2830 match(ConI);
2831 op_cost(0);
2832 format %{ %}
2833 interface(CONST_INTER);
2834 %}
2835
2836 // 5 bit signed value.
2837 operand immI5()
2838 %{
2839 predicate(n->get_int() <= 15 && n->get_int() >= -16);
2840 match(ConI);
2841
2842 op_cost(0);
2843 format %{ %}
2844 interface(CONST_INTER);
2845 %}
2846
2847 // 5 bit signed value (simm5)
2848 operand immL5()
2849 %{
2850 predicate(n->get_long() <= 15 && n->get_long() >= -16);
2851 match(ConL);
2852
2853 op_cost(0);
2854 format %{ %}
2855 interface(CONST_INTER);
2856 %}
2857
2858 // Integer operands 64 bit
2859 // 64 bit immediate
2860 operand immL()
2861 %{
2862 match(ConL);
2863
2864 op_cost(0);
2865 format %{ %}
2866 interface(CONST_INTER);
2867 %}
2868
2869 // 64 bit zero
2870 operand immL0()
2871 %{
2872 predicate(n->get_long() == 0);
2873 match(ConL);
2874
2875 op_cost(0);
2876 format %{ %}
2877 interface(CONST_INTER);
2878 %}
2879
2880 // Pointer operands
2881 // Pointer Immediate
2882 operand immP()
2883 %{
2884 match(ConP);
2885
2886 op_cost(0);
2887 format %{ %}
2888 interface(CONST_INTER);
2889 %}
2890
2891 // Null Pointer Immediate
2892 operand immP0()
2893 %{
2894 predicate(n->get_ptr() == 0);
2895 match(ConP);
2896
2897 op_cost(0);
2898 format %{ %}
2899 interface(CONST_INTER);
2900 %}
2901
2902 // Pointer Immediate One
2903 // this is used in object initialization (initial object header)
2904 operand immP_1()
2905 %{
2906 predicate(n->get_ptr() == 1);
2907 match(ConP);
2908
2909 op_cost(0);
2910 format %{ %}
2911 interface(CONST_INTER);
2912 %}
2913
2914 // Card Table Byte Map Base
2915 operand immByteMapBase()
2916 %{
2917 // Get base of card map
2918 predicate(BarrierSet::barrier_set()->is_a(BarrierSet::CardTableBarrierSet) &&
2919 (CardTable::CardValue*)n->get_ptr() ==
2920 ((CardTableBarrierSet*)(BarrierSet::barrier_set()))->card_table()->byte_map_base());
2921 match(ConP);
2922
2923 op_cost(0);
2924 format %{ %}
2925 interface(CONST_INTER);
2926 %}
2927
2928 // Int Immediate: low 16-bit mask
2929 operand immI_16bits()
2930 %{
2931 predicate(n->get_int() == 0xFFFF);
2932 match(ConI);
2933 op_cost(0);
2934 format %{ %}
2935 interface(CONST_INTER);
2936 %}
2937
2938 operand immIpowerOf2() %{
2939 predicate(is_power_of_2((juint)(n->get_int())));
2940 match(ConI);
2941 op_cost(0);
2942 format %{ %}
2943 interface(CONST_INTER);
2944 %}
2945
2946 // Long Immediate: low 32-bit mask
2947 operand immL_32bits()
2948 %{
2949 predicate(n->get_long() == 0xFFFFFFFFL);
2950 match(ConL);
2951 op_cost(0);
2952 format %{ %}
2953 interface(CONST_INTER);
2954 %}
2955
2956 // 64 bit unit decrement
2957 operand immL_M1()
2958 %{
2959 predicate(n->get_long() == -1);
2960 match(ConL);
2961
2962 op_cost(0);
2963 format %{ %}
2964 interface(CONST_INTER);
2965 %}
2966
2967
2968 // 64 bit integer valid for add immediate
2969 operand immLAdd()
2970 %{
2971 predicate(Assembler::is_simm12(n->get_long()));
2972 match(ConL);
2973 op_cost(0);
2974 format %{ %}
2975 interface(CONST_INTER);
2976 %}
2977
2978 // 64 bit integer valid for sub immediate
2979 operand immLSub()
2980 %{
2981 predicate(Assembler::is_simm12(-(n->get_long())));
2982 match(ConL);
2983 op_cost(0);
2984 format %{ %}
2985 interface(CONST_INTER);
2986 %}
2987
2988 // Narrow pointer operands
2989 // Narrow Pointer Immediate
2990 operand immN()
2991 %{
2992 match(ConN);
2993
2994 op_cost(0);
2995 format %{ %}
2996 interface(CONST_INTER);
2997 %}
2998
2999 // Narrow Null Pointer Immediate
3000 operand immN0()
3001 %{
3002 predicate(n->get_narrowcon() == 0);
3003 match(ConN);
3004
3005 op_cost(0);
3006 format %{ %}
3007 interface(CONST_INTER);
3008 %}
3009
3010 operand immNKlass()
3011 %{
3012 match(ConNKlass);
3013
3014 op_cost(0);
3015 format %{ %}
3016 interface(CONST_INTER);
3017 %}
3018
3019 // Float and Double operands
3020 // Double Immediate
3021 operand immD()
3022 %{
3023 match(ConD);
3024 op_cost(0);
3025 format %{ %}
3026 interface(CONST_INTER);
3027 %}
3028
3029 // Double Immediate: +0.0d
3030 operand immD0()
3031 %{
3032 predicate(jlong_cast(n->getd()) == 0);
3033 match(ConD);
3034
3035 op_cost(0);
3036 format %{ %}
3037 interface(CONST_INTER);
3038 %}
3039
3040 // Float Immediate
3041 operand immF()
3042 %{
3043 match(ConF);
3044 op_cost(0);
3045 format %{ %}
3046 interface(CONST_INTER);
3047 %}
3048
3049 // Float Immediate: +0.0f.
3050 operand immF0()
3051 %{
3052 predicate(jint_cast(n->getf()) == 0);
3053 match(ConF);
3054
3055 op_cost(0);
3056 format %{ %}
3057 interface(CONST_INTER);
3058 %}
3059
3060 operand immIOffset()
3061 %{
3062 predicate(Assembler::is_simm12(n->get_int()));
3063 match(ConI);
3064 op_cost(0);
3065 format %{ %}
3066 interface(CONST_INTER);
3067 %}
3068
3069 operand immLOffset()
3070 %{
3071 predicate(Assembler::is_simm12(n->get_long()));
3072 match(ConL);
3073 op_cost(0);
3074 format %{ %}
3075 interface(CONST_INTER);
3076 %}
3077
3078 // Scale values
3079 operand immIScale()
3080 %{
3081 predicate(1 <= n->get_int() && (n->get_int() <= 3));
3082 match(ConI);
3083
3084 op_cost(0);
3085 format %{ %}
3086 interface(CONST_INTER);
3087 %}
3088
3089 // Integer 32 bit Register Operands
3090 operand iRegI()
3091 %{
3092 constraint(ALLOC_IN_RC(any_reg32));
3093 match(RegI);
3094 match(iRegINoSp);
3095 op_cost(0);
3096 format %{ %}
3097 interface(REG_INTER);
3098 %}
3099
3100 // Integer 32 bit Register not Special
3101 operand iRegINoSp()
3102 %{
3103 constraint(ALLOC_IN_RC(no_special_reg32));
3104 match(RegI);
3105 op_cost(0);
3106 format %{ %}
3107 interface(REG_INTER);
3108 %}
3109
3110 // Register R10 only
3111 operand iRegI_R10()
3112 %{
3113 constraint(ALLOC_IN_RC(int_r10_reg));
3114 match(RegI);
3115 match(iRegINoSp);
3116 op_cost(0);
3117 format %{ %}
3118 interface(REG_INTER);
3119 %}
3120
3121 // Register R12 only
3122 operand iRegI_R12()
3123 %{
3124 constraint(ALLOC_IN_RC(int_r12_reg));
3125 match(RegI);
3126 match(iRegINoSp);
3127 op_cost(0);
3128 format %{ %}
3129 interface(REG_INTER);
3130 %}
3131
3132 // Register R13 only
3133 operand iRegI_R13()
3134 %{
3135 constraint(ALLOC_IN_RC(int_r13_reg));
3136 match(RegI);
3137 match(iRegINoSp);
3138 op_cost(0);
3139 format %{ %}
3140 interface(REG_INTER);
3141 %}
3142
3143 // Register R14 only
3144 operand iRegI_R14()
3145 %{
3146 constraint(ALLOC_IN_RC(int_r14_reg));
3147 match(RegI);
3148 match(iRegINoSp);
3149 op_cost(0);
3150 format %{ %}
3151 interface(REG_INTER);
3152 %}
3153
3154 // Integer 64 bit Register Operands
3155 operand iRegL()
3156 %{
3157 constraint(ALLOC_IN_RC(any_reg));
3158 match(RegL);
3159 match(iRegLNoSp);
3160 op_cost(0);
3161 format %{ %}
3162 interface(REG_INTER);
3163 %}
3164
3165 // Integer 64 bit Register not Special
3166 operand iRegLNoSp()
3167 %{
3168 constraint(ALLOC_IN_RC(no_special_reg));
3169 match(RegL);
3170 match(iRegL_R10);
3171 format %{ %}
3172 interface(REG_INTER);
3173 %}
3174
3175 // Long 64 bit Register R29 only
3176 operand iRegL_R29()
3177 %{
3178 constraint(ALLOC_IN_RC(r29_reg));
3179 match(RegL);
3180 match(iRegLNoSp);
3181 op_cost(0);
3182 format %{ %}
3183 interface(REG_INTER);
3184 %}
3185
3186 // Long 64 bit Register R30 only
3187 operand iRegL_R30()
3188 %{
3189 constraint(ALLOC_IN_RC(r30_reg));
3190 match(RegL);
3191 match(iRegLNoSp);
3192 op_cost(0);
3193 format %{ %}
3194 interface(REG_INTER);
3195 %}
3196
3197 // Pointer Register Operands
3198 // Pointer Register
3199 operand iRegP()
3200 %{
3201 constraint(ALLOC_IN_RC(ptr_reg));
3202 match(RegP);
3203 match(iRegPNoSp);
3204 match(iRegP_R10);
3205 match(iRegP_R15);
3206 match(javaThread_RegP);
3207 op_cost(0);
3208 format %{ %}
3209 interface(REG_INTER);
3210 %}
3211
3212 // Pointer 64 bit Register not Special
3213 operand iRegPNoSp()
3214 %{
3215 constraint(ALLOC_IN_RC(no_special_ptr_reg));
3216 match(RegP);
3217 op_cost(0);
3218 format %{ %}
3219 interface(REG_INTER);
3220 %}
3221
3222 // This operand is not allowed to use fp even if
3223 // fp is not used to hold the frame pointer.
3224 operand iRegPNoSpNoFp()
3225 %{
3226 constraint(ALLOC_IN_RC(no_special_no_fp_ptr_reg));
3227 match(RegP);
3228 match(iRegPNoSp);
3229 op_cost(0);
3230 format %{ %}
3231 interface(REG_INTER);
3232 %}
3233
3234 operand iRegP_R10()
3235 %{
3236 constraint(ALLOC_IN_RC(r10_reg));
3237 match(RegP);
3238 // match(iRegP);
3239 match(iRegPNoSp);
3240 op_cost(0);
3241 format %{ %}
3242 interface(REG_INTER);
3243 %}
3244
3245 // Pointer 64 bit Register R11 only
3246 operand iRegP_R11()
3247 %{
3248 constraint(ALLOC_IN_RC(r11_reg));
3249 match(RegP);
3250 match(iRegPNoSp);
3251 op_cost(0);
3252 format %{ %}
3253 interface(REG_INTER);
3254 %}
3255
3256 operand iRegP_R12()
3257 %{
3258 constraint(ALLOC_IN_RC(r12_reg));
3259 match(RegP);
3260 // match(iRegP);
3261 match(iRegPNoSp);
3262 op_cost(0);
3263 format %{ %}
3264 interface(REG_INTER);
3265 %}
3266
3267 // Pointer 64 bit Register R13 only
3268 operand iRegP_R13()
3269 %{
3270 constraint(ALLOC_IN_RC(r13_reg));
3271 match(RegP);
3272 match(iRegPNoSp);
3273 op_cost(0);
3274 format %{ %}
3275 interface(REG_INTER);
3276 %}
3277
3278 operand iRegP_R14()
3279 %{
3280 constraint(ALLOC_IN_RC(r14_reg));
3281 match(RegP);
3282 // match(iRegP);
3283 match(iRegPNoSp);
3284 op_cost(0);
3285 format %{ %}
3286 interface(REG_INTER);
3287 %}
3288
3289 operand iRegP_R15()
3290 %{
3291 constraint(ALLOC_IN_RC(r15_reg));
3292 match(RegP);
3293 // match(iRegP);
3294 match(iRegPNoSp);
3295 op_cost(0);
3296 format %{ %}
3297 interface(REG_INTER);
3298 %}
3299
3300 operand iRegP_R16()
3301 %{
3302 constraint(ALLOC_IN_RC(r16_reg));
3303 match(RegP);
3304 match(iRegPNoSp);
3305 op_cost(0);
3306 format %{ %}
3307 interface(REG_INTER);
3308 %}
3309
3310 // Pointer 64 bit Register R28 only
3311 operand iRegP_R28()
3312 %{
3313 constraint(ALLOC_IN_RC(r28_reg));
3314 match(RegP);
3315 match(iRegPNoSp);
3316 op_cost(0);
3317 format %{ %}
3318 interface(REG_INTER);
3319 %}
3320
3321 // Pointer 64 bit Register R30 only
3322 operand iRegP_R30()
3323 %{
3324 constraint(ALLOC_IN_RC(r30_reg));
3325 match(RegP);
3326 match(iRegPNoSp);
3327 op_cost(0);
3328 format %{ %}
3329 interface(REG_INTER);
3330 %}
3331
3332 // Pointer 64 bit Register R31 only
3333 operand iRegP_R31()
3334 %{
3335 constraint(ALLOC_IN_RC(r31_reg));
3336 match(RegP);
3337 match(iRegPNoSp);
3338 op_cost(0);
3339 format %{ %}
3340 interface(REG_INTER);
3341 %}
3342
3343 // Pointer Register Operands
3344 // Narrow Pointer Register
3345 operand iRegN()
3346 %{
3347 constraint(ALLOC_IN_RC(any_reg32));
3348 match(RegN);
3349 match(iRegNNoSp);
3350 op_cost(0);
3351 format %{ %}
3352 interface(REG_INTER);
3353 %}
3354
3355 // Integer 64 bit Register not Special
3356 operand iRegNNoSp()
3357 %{
3358 constraint(ALLOC_IN_RC(no_special_reg32));
3359 match(RegN);
3360 op_cost(0);
3361 format %{ %}
3362 interface(REG_INTER);
3363 %}
3364
3365 // Long 64 bit Register R10 only
3366 operand iRegL_R10()
3367 %{
3368 constraint(ALLOC_IN_RC(r10_reg));
3369 match(RegL);
3370 match(iRegLNoSp);
3371 op_cost(0);
3372 format %{ %}
3373 interface(REG_INTER);
3374 %}
3375
3376 // Float Register
3377 // Float register operands
3378 operand fRegF()
3379 %{
3380 constraint(ALLOC_IN_RC(float_reg));
3381 match(RegF);
3382
3383 op_cost(0);
3384 format %{ %}
3385 interface(REG_INTER);
3386 %}
3387
3388 // Double Register
3389 // Double register operands
3390 operand fRegD()
3391 %{
3392 constraint(ALLOC_IN_RC(double_reg));
3393 match(RegD);
3394
3395 op_cost(0);
3396 format %{ %}
3397 interface(REG_INTER);
3398 %}
3399
3400 // Generic vector class. This will be used for
3401 // all vector operands.
3402 operand vReg()
3403 %{
3404 constraint(ALLOC_IN_RC(vectora_reg));
3405 match(VecA);
3406 op_cost(0);
3407 format %{ %}
3408 interface(REG_INTER);
3409 %}
3410
3411 operand vReg_V1()
3412 %{
3413 constraint(ALLOC_IN_RC(v1_reg));
3414 match(VecA);
3415 match(vReg);
3416 op_cost(0);
3417 format %{ %}
3418 interface(REG_INTER);
3419 %}
3420
3421 operand vReg_V2()
3422 %{
3423 constraint(ALLOC_IN_RC(v2_reg));
3424 match(VecA);
3425 match(vReg);
3426 op_cost(0);
3427 format %{ %}
3428 interface(REG_INTER);
3429 %}
3430
3431 operand vReg_V3()
3432 %{
3433 constraint(ALLOC_IN_RC(v3_reg));
3434 match(VecA);
3435 match(vReg);
3436 op_cost(0);
3437 format %{ %}
3438 interface(REG_INTER);
3439 %}
3440
3441 operand vReg_V4()
3442 %{
3443 constraint(ALLOC_IN_RC(v4_reg));
3444 match(VecA);
3445 match(vReg);
3446 op_cost(0);
3447 format %{ %}
3448 interface(REG_INTER);
3449 %}
3450
3451 operand vReg_V5()
3452 %{
3453 constraint(ALLOC_IN_RC(v5_reg));
3454 match(VecA);
3455 match(vReg);
3456 op_cost(0);
3457 format %{ %}
3458 interface(REG_INTER);
3459 %}
3460
3461 operand vReg_V6()
3462 %{
3463 constraint(ALLOC_IN_RC(v6_reg));
3464 match(VecA);
3465 match(vReg);
3466 op_cost(0);
3467 format %{ %}
3468 interface(REG_INTER);
3469 %}
3470
3471 operand vReg_V7()
3472 %{
3473 constraint(ALLOC_IN_RC(v7_reg));
3474 match(VecA);
3475 match(vReg);
3476 op_cost(0);
3477 format %{ %}
3478 interface(REG_INTER);
3479 %}
3480
3481 operand vReg_V8()
3482 %{
3483 constraint(ALLOC_IN_RC(v8_reg));
3484 match(VecA);
3485 match(vReg);
3486 op_cost(0);
3487 format %{ %}
3488 interface(REG_INTER);
3489 %}
3490
3491 operand vReg_V9()
3492 %{
3493 constraint(ALLOC_IN_RC(v9_reg));
3494 match(VecA);
3495 match(vReg);
3496 op_cost(0);
3497 format %{ %}
3498 interface(REG_INTER);
3499 %}
3500
3501 operand vReg_V10()
3502 %{
3503 constraint(ALLOC_IN_RC(v10_reg));
3504 match(VecA);
3505 match(vReg);
3506 op_cost(0);
3507 format %{ %}
3508 interface(REG_INTER);
3509 %}
3510
3511 operand vReg_V11()
3512 %{
3513 constraint(ALLOC_IN_RC(v11_reg));
3514 match(VecA);
3515 match(vReg);
3516 op_cost(0);
3517 format %{ %}
3518 interface(REG_INTER);
3519 %}
3520
3521 operand vRegMask()
3522 %{
3523 constraint(ALLOC_IN_RC(vmask_reg));
3524 match(RegVectMask);
3525 match(vRegMask_V0);
3526 op_cost(0);
3527 format %{ %}
3528 interface(REG_INTER);
3529 %}
3530
3531 // The mask value used to control execution of a masked
3532 // vector instruction is always supplied by vector register v0.
3533 operand vRegMask_V0()
3534 %{
3535 constraint(ALLOC_IN_RC(vmask_reg_v0));
3536 match(RegVectMask);
3537 match(vRegMask);
3538 op_cost(0);
3539 format %{ %}
3540 interface(REG_INTER);
3541 %}
3542
3543 // Java Thread Register
3544 operand javaThread_RegP(iRegP reg)
3545 %{
3546 constraint(ALLOC_IN_RC(java_thread_reg)); // java_thread_reg
3547 match(reg);
3548 op_cost(0);
3549 format %{ %}
3550 interface(REG_INTER);
3551 %}
3552
3553 //----------Memory Operands----------------------------------------------------
3554 // RISCV has only base_plus_offset and literal address mode, so no need to use
3555 // index and scale. Here set index as 0xffffffff and scale as 0x0.
3556 operand indirect(iRegP reg)
3557 %{
3558 constraint(ALLOC_IN_RC(ptr_reg));
3559 match(reg);
3560 op_cost(0);
3561 format %{ "[$reg]" %}
3562 interface(MEMORY_INTER) %{
3563 base($reg);
3564 index(0xffffffff);
3565 scale(0x0);
3566 disp(0x0);
3567 %}
3568 %}
3569
3570 operand indOffI(iRegP reg, immIOffset off)
3571 %{
3572 constraint(ALLOC_IN_RC(ptr_reg));
3573 match(AddP reg off);
3574 op_cost(0);
3575 format %{ "[$reg, $off]" %}
3576 interface(MEMORY_INTER) %{
3577 base($reg);
3578 index(0xffffffff);
3579 scale(0x0);
3580 disp($off);
3581 %}
3582 %}
3583
3584 operand indOffL(iRegP reg, immLOffset off)
3585 %{
3586 constraint(ALLOC_IN_RC(ptr_reg));
3587 match(AddP reg off);
3588 op_cost(0);
3589 format %{ "[$reg, $off]" %}
3590 interface(MEMORY_INTER) %{
3591 base($reg);
3592 index(0xffffffff);
3593 scale(0x0);
3594 disp($off);
3595 %}
3596 %}
3597
3598 operand indirectN(iRegN reg)
3599 %{
3600 predicate(CompressedOops::shift() == 0);
3601 constraint(ALLOC_IN_RC(ptr_reg));
3602 match(DecodeN reg);
3603 op_cost(0);
3604 format %{ "[$reg]\t# narrow" %}
3605 interface(MEMORY_INTER) %{
3606 base($reg);
3607 index(0xffffffff);
3608 scale(0x0);
3609 disp(0x0);
3610 %}
3611 %}
3612
3613 operand indOffIN(iRegN reg, immIOffset off)
3614 %{
3615 predicate(CompressedOops::shift() == 0);
3616 constraint(ALLOC_IN_RC(ptr_reg));
3617 match(AddP (DecodeN reg) off);
3618 op_cost(0);
3619 format %{ "[$reg, $off]\t# narrow" %}
3620 interface(MEMORY_INTER) %{
3621 base($reg);
3622 index(0xffffffff);
3623 scale(0x0);
3624 disp($off);
3625 %}
3626 %}
3627
3628 operand indOffLN(iRegN reg, immLOffset off)
3629 %{
3630 predicate(CompressedOops::shift() == 0);
3631 constraint(ALLOC_IN_RC(ptr_reg));
3632 match(AddP (DecodeN reg) off);
3633 op_cost(0);
3634 format %{ "[$reg, $off]\t# narrow" %}
3635 interface(MEMORY_INTER) %{
3636 base($reg);
3637 index(0xffffffff);
3638 scale(0x0);
3639 disp($off);
3640 %}
3641 %}
3642
3643 //----------Special Memory Operands--------------------------------------------
3644 // Stack Slot Operand - This operand is used for loading and storing temporary
3645 // values on the stack where a match requires a value to
3646 // flow through memory.
3647 operand stackSlotI(sRegI reg)
3648 %{
3649 constraint(ALLOC_IN_RC(stack_slots));
3650 // No match rule because this operand is only generated in matching
3651 // match(RegI);
3652 format %{ "[$reg]" %}
3653 interface(MEMORY_INTER) %{
3654 base(0x02); // RSP
3655 index(0xffffffff); // No Index
3656 scale(0x0); // No Scale
3657 disp($reg); // Stack Offset
3658 %}
3659 %}
3660
3661 operand stackSlotF(sRegF reg)
3662 %{
3663 constraint(ALLOC_IN_RC(stack_slots));
3664 // No match rule because this operand is only generated in matching
3665 // match(RegF);
3666 format %{ "[$reg]" %}
3667 interface(MEMORY_INTER) %{
3668 base(0x02); // RSP
3669 index(0xffffffff); // No Index
3670 scale(0x0); // No Scale
3671 disp($reg); // Stack Offset
3672 %}
3673 %}
3674
3675 operand stackSlotD(sRegD reg)
3676 %{
3677 constraint(ALLOC_IN_RC(stack_slots));
3678 // No match rule because this operand is only generated in matching
3679 // match(RegD);
3680 format %{ "[$reg]" %}
3681 interface(MEMORY_INTER) %{
3682 base(0x02); // RSP
3683 index(0xffffffff); // No Index
3684 scale(0x0); // No Scale
3685 disp($reg); // Stack Offset
3686 %}
3687 %}
3688
3689 operand stackSlotL(sRegL reg)
3690 %{
3691 constraint(ALLOC_IN_RC(stack_slots));
3692 // No match rule because this operand is only generated in matching
3693 // match(RegL);
3694 format %{ "[$reg]" %}
3695 interface(MEMORY_INTER) %{
3696 base(0x02); // RSP
3697 index(0xffffffff); // No Index
3698 scale(0x0); // No Scale
3699 disp($reg); // Stack Offset
3700 %}
3701 %}
3702
3703 // Special operand allowing long args to int ops to be truncated for free
3704
3705 operand iRegL2I(iRegL reg) %{
3706
3707 op_cost(0);
3708
3709 match(ConvL2I reg);
3710
3711 format %{ "l2i($reg)" %}
3712
3713 interface(REG_INTER)
3714 %}
3715
3716
3717 // Comparison Operands
3718 // NOTE: Label is a predefined operand which should not be redefined in
3719 // the AD file. It is generically handled within the ADLC.
3720
3721 //----------Conditional Branch Operands----------------------------------------
3722 // Comparison Op - This is the operation of the comparison, and is limited to
3723 // the following set of codes:
3724 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
3725 //
3726 // Other attributes of the comparison, such as unsignedness, are specified
3727 // by the comparison instruction that sets a condition code flags register.
3728 // That result is represented by a flags operand whose subtype is appropriate
3729 // to the unsignedness (etc.) of the comparison.
3730 //
3731 // Later, the instruction which matches both the Comparison Op (a Bool) and
3732 // the flags (produced by the Cmp) specifies the coding of the comparison op
3733 // by matching a specific subtype of Bool operand below, such as cmpOpU.
3734
3735
3736 // used for signed integral comparisons and fp comparisons
3737 operand cmpOp()
3738 %{
3739 match(Bool);
3740
3741 format %{ "" %}
3742
3743 // the values in interface derives from struct BoolTest::mask
3744 interface(COND_INTER) %{
3745 equal(0x0, "eq");
3746 greater(0x1, "gt");
3747 overflow(0x2, "overflow");
3748 less(0x3, "lt");
3749 not_equal(0x4, "ne");
3750 less_equal(0x5, "le");
3751 no_overflow(0x6, "no_overflow");
3752 greater_equal(0x7, "ge");
3753 %}
3754 %}
3755
3756 // used for unsigned integral comparisons
3757 operand cmpOpU()
3758 %{
3759 match(Bool);
3760
3761 format %{ "" %}
3762 // the values in interface derives from struct BoolTest::mask
3763 interface(COND_INTER) %{
3764 equal(0x0, "eq");
3765 greater(0x1, "gtu");
3766 overflow(0x2, "overflow");
3767 less(0x3, "ltu");
3768 not_equal(0x4, "ne");
3769 less_equal(0x5, "leu");
3770 no_overflow(0x6, "no_overflow");
3771 greater_equal(0x7, "geu");
3772 %}
3773 %}
3774
3775 // used for certain integral comparisons which can be
3776 // converted to bxx instructions
3777 operand cmpOpEqNe()
3778 %{
3779 match(Bool);
3780 op_cost(0);
3781 predicate(n->as_Bool()->_test._test == BoolTest::ne ||
3782 n->as_Bool()->_test._test == BoolTest::eq);
3783
3784 format %{ "" %}
3785 interface(COND_INTER) %{
3786 equal(0x0, "eq");
3787 greater(0x1, "gt");
3788 overflow(0x2, "overflow");
3789 less(0x3, "lt");
3790 not_equal(0x4, "ne");
3791 less_equal(0x5, "le");
3792 no_overflow(0x6, "no_overflow");
3793 greater_equal(0x7, "ge");
3794 %}
3795 %}
3796
3797 operand cmpOpULtGe()
3798 %{
3799 match(Bool);
3800 op_cost(0);
3801 predicate(n->as_Bool()->_test._test == BoolTest::lt ||
3802 n->as_Bool()->_test._test == BoolTest::ge);
3803
3804 format %{ "" %}
3805 interface(COND_INTER) %{
3806 equal(0x0, "eq");
3807 greater(0x1, "gtu");
3808 overflow(0x2, "overflow");
3809 less(0x3, "ltu");
3810 not_equal(0x4, "ne");
3811 less_equal(0x5, "leu");
3812 no_overflow(0x6, "no_overflow");
3813 greater_equal(0x7, "geu");
3814 %}
3815 %}
3816
3817 operand cmpOpUEqNeLeGt()
3818 %{
3819 match(Bool);
3820 op_cost(0);
3821 predicate(n->as_Bool()->_test._test == BoolTest::ne ||
3822 n->as_Bool()->_test._test == BoolTest::eq ||
3823 n->as_Bool()->_test._test == BoolTest::le ||
3824 n->as_Bool()->_test._test == BoolTest::gt);
3825
3826 format %{ "" %}
3827 interface(COND_INTER) %{
3828 equal(0x0, "eq");
3829 greater(0x1, "gtu");
3830 overflow(0x2, "overflow");
3831 less(0x3, "ltu");
3832 not_equal(0x4, "ne");
3833 less_equal(0x5, "leu");
3834 no_overflow(0x6, "no_overflow");
3835 greater_equal(0x7, "geu");
3836 %}
3837 %}
3838
3839
3840 // Flags register, used as output of compare logic
3841 operand rFlagsReg()
3842 %{
3843 constraint(ALLOC_IN_RC(reg_flags));
3844 match(RegFlags);
3845
3846 op_cost(0);
3847 format %{ "RFLAGS" %}
3848 interface(REG_INTER);
3849 %}
3850
3851 // Special Registers
3852
3853 // Method Register
3854 operand inline_cache_RegP(iRegP reg)
3855 %{
3856 constraint(ALLOC_IN_RC(method_reg)); // inline_cache_reg
3857 match(reg);
3858 match(iRegPNoSp);
3859 op_cost(0);
3860 format %{ %}
3861 interface(REG_INTER);
3862 %}
3863
3864 //----------OPERAND CLASSES----------------------------------------------------
3865 // Operand Classes are groups of operands that are used as to simplify
3866 // instruction definitions by not requiring the AD writer to specify
3867 // separate instructions for every form of operand when the
3868 // instruction accepts multiple operand types with the same basic
3869 // encoding and format. The classic case of this is memory operands.
3870
3871 // memory is used to define read/write location for load/store
3872 // instruction defs. we can turn a memory op into an Address
3873
3874 opclass memory(indirect, indOffI, indOffL, indirectN, indOffIN, indOffLN);
3875
3876 // iRegIorL2I is used for src inputs in rules for 32 bit int (I)
3877 // operations. it allows the src to be either an iRegI or a (ConvL2I
3878 // iRegL). in the latter case the l2i normally planted for a ConvL2I
3879 // can be elided because the 32-bit instruction will just employ the
3880 // lower 32 bits anyway.
3881 //
3882 // n.b. this does not elide all L2I conversions. if the truncated
3883 // value is consumed by more than one operation then the ConvL2I
3884 // cannot be bundled into the consuming nodes so an l2i gets planted
3885 // (actually an addiw $dst, $src, 0) and the downstream instructions
3886 // consume the result of the L2I as an iRegI input. That's a shame since
3887 // the addiw is actually redundant but its not too costly.
3888
3889 opclass iRegIorL2I(iRegI, iRegL2I);
3890 opclass iRegIorL(iRegI, iRegL);
3891 opclass iRegNorP(iRegN, iRegP);
3892 opclass iRegILNP(iRegI, iRegL, iRegN, iRegP);
3893 opclass iRegILNPNoSp(iRegINoSp, iRegLNoSp, iRegNNoSp, iRegPNoSp);
3894 opclass immIorL(immI, immL);
3895
3896 //----------PIPELINE-----------------------------------------------------------
3897 // Rules which define the behavior of the target architectures pipeline.
3898
3899 // For specific pipelines, e.g. generic RISC-V, define the stages of that pipeline
3900 //pipe_desc(ID, EX, MEM, WR);
3901 #define ID S0
3902 #define EX S1
3903 #define MEM S2
3904 #define WR S3
3905
3906 // Integer ALU reg operation
3907 pipeline %{
3908
3909 attributes %{
3910 // RISC-V instructions are of fixed length
3911 fixed_size_instructions; // Fixed size instructions TODO does
3912 max_instructions_per_bundle = 2; // Generic RISC-V 1, Sifive Series 7 2
3913 // RISC-V instructions come in 32-bit word units
3914 instruction_unit_size = 4; // An instruction is 4 bytes long
3915 instruction_fetch_unit_size = 64; // The processor fetches one line
3916 instruction_fetch_units = 1; // of 64 bytes
3917
3918 // List of nop instructions
3919 nops( MachNop );
3920 %}
3921
3922 // We don't use an actual pipeline model so don't care about resources
3923 // or description. we do use pipeline classes to introduce fixed
3924 // latencies
3925
3926 //----------RESOURCES----------------------------------------------------------
3927 // Resources are the functional units available to the machine
3928
3929 // Generic RISC-V pipeline
3930 // 1 decoder
3931 // 1 instruction decoded per cycle
3932 // 1 load/store ops per cycle, 1 branch, 1 FPU
3933 // 1 mul, 1 div
3934
3935 resources ( DECODE,
3936 ALU,
3937 MUL,
3938 DIV,
3939 BRANCH,
3940 LDST,
3941 FPU);
3942
3943 //----------PIPELINE DESCRIPTION-----------------------------------------------
3944 // Pipeline Description specifies the stages in the machine's pipeline
3945
3946 // Define the pipeline as a generic 6 stage pipeline
3947 pipe_desc(S0, S1, S2, S3, S4, S5);
3948
3949 //----------PIPELINE CLASSES---------------------------------------------------
3950 // Pipeline Classes describe the stages in which input and output are
3951 // referenced by the hardware pipeline.
3952
3953 pipe_class fp_dop_reg_reg_s(fRegF dst, fRegF src1, fRegF src2)
3954 %{
3955 single_instruction;
3956 src1 : S1(read);
3957 src2 : S2(read);
3958 dst : S5(write);
3959 DECODE : ID;
3960 FPU : S5;
3961 %}
3962
3963 pipe_class fp_dop_reg_reg_d(fRegD dst, fRegD src1, fRegD src2)
3964 %{
3965 src1 : S1(read);
3966 src2 : S2(read);
3967 dst : S5(write);
3968 DECODE : ID;
3969 FPU : S5;
3970 %}
3971
3972 pipe_class fp_uop_s(fRegF dst, fRegF src)
3973 %{
3974 single_instruction;
3975 src : S1(read);
3976 dst : S5(write);
3977 DECODE : ID;
3978 FPU : S5;
3979 %}
3980
3981 pipe_class fp_uop_d(fRegD dst, fRegD src)
3982 %{
3983 single_instruction;
3984 src : S1(read);
3985 dst : S5(write);
3986 DECODE : ID;
3987 FPU : S5;
3988 %}
3989
3990 pipe_class fp_d2f(fRegF dst, fRegD src)
3991 %{
3992 single_instruction;
3993 src : S1(read);
3994 dst : S5(write);
3995 DECODE : ID;
3996 FPU : S5;
3997 %}
3998
3999 pipe_class fp_f2d(fRegD dst, fRegF src)
4000 %{
4001 single_instruction;
4002 src : S1(read);
4003 dst : S5(write);
4004 DECODE : ID;
4005 FPU : S5;
4006 %}
4007
4008 pipe_class fp_f2i(iRegINoSp dst, fRegF src)
4009 %{
4010 single_instruction;
4011 src : S1(read);
4012 dst : S5(write);
4013 DECODE : ID;
4014 FPU : S5;
4015 %}
4016
4017 pipe_class fp_f2l(iRegLNoSp dst, fRegF src)
4018 %{
4019 single_instruction;
4020 src : S1(read);
4021 dst : S5(write);
4022 DECODE : ID;
4023 FPU : S5;
4024 %}
4025
4026 pipe_class fp_i2f(fRegF dst, iRegIorL2I src)
4027 %{
4028 single_instruction;
4029 src : S1(read);
4030 dst : S5(write);
4031 DECODE : ID;
4032 FPU : S5;
4033 %}
4034
4035 pipe_class fp_l2f(fRegF dst, iRegL src)
4036 %{
4037 single_instruction;
4038 src : S1(read);
4039 dst : S5(write);
4040 DECODE : ID;
4041 FPU : S5;
4042 %}
4043
4044 pipe_class fp_d2i(iRegINoSp dst, fRegD src)
4045 %{
4046 single_instruction;
4047 src : S1(read);
4048 dst : S5(write);
4049 DECODE : ID;
4050 FPU : S5;
4051 %}
4052
4053 pipe_class fp_d2l(iRegLNoSp dst, fRegD src)
4054 %{
4055 single_instruction;
4056 src : S1(read);
4057 dst : S5(write);
4058 DECODE : ID;
4059 FPU : S5;
4060 %}
4061
4062 pipe_class fp_i2d(fRegD dst, iRegIorL2I src)
4063 %{
4064 single_instruction;
4065 src : S1(read);
4066 dst : S5(write);
4067 DECODE : ID;
4068 FPU : S5;
4069 %}
4070
4071 pipe_class fp_l2d(fRegD dst, iRegIorL2I src)
4072 %{
4073 single_instruction;
4074 src : S1(read);
4075 dst : S5(write);
4076 DECODE : ID;
4077 FPU : S5;
4078 %}
4079
4080 pipe_class fp_div_s(fRegF dst, fRegF src1, fRegF src2)
4081 %{
4082 single_instruction;
4083 src1 : S1(read);
4084 src2 : S2(read);
4085 dst : S5(write);
4086 DECODE : ID;
4087 FPU : S5;
4088 %}
4089
4090 pipe_class fp_div_d(fRegD dst, fRegD src1, fRegD src2)
4091 %{
4092 single_instruction;
4093 src1 : S1(read);
4094 src2 : S2(read);
4095 dst : S5(write);
4096 DECODE : ID;
4097 FPU : S5;
4098 %}
4099
4100 pipe_class fp_sqrt_s(fRegF dst, fRegF src1, fRegF src2)
4101 %{
4102 single_instruction;
4103 src1 : S1(read);
4104 src2 : S2(read);
4105 dst : S5(write);
4106 DECODE : ID;
4107 FPU : S5;
4108 %}
4109
4110 pipe_class fp_sqrt_d(fRegD dst, fRegD src1, fRegD src2)
4111 %{
4112 single_instruction;
4113 src1 : S1(read);
4114 src2 : S2(read);
4115 dst : S5(write);
4116 DECODE : ID;
4117 FPU : S5;
4118 %}
4119
4120 pipe_class fp_load_constant_s(fRegF dst)
4121 %{
4122 single_instruction;
4123 dst : S5(write);
4124 DECODE : ID;
4125 FPU : S5;
4126 %}
4127
4128 pipe_class fp_load_constant_d(fRegD dst)
4129 %{
4130 single_instruction;
4131 dst : S5(write);
4132 DECODE : ID;
4133 FPU : S5;
4134 %}
4135
4136 pipe_class fp_load_mem_s(fRegF dst, memory mem)
4137 %{
4138 single_instruction;
4139 mem : S1(read);
4140 dst : S5(write);
4141 DECODE : ID;
4142 LDST : MEM;
4143 %}
4144
4145 pipe_class fp_load_mem_d(fRegD dst, memory mem)
4146 %{
4147 single_instruction;
4148 mem : S1(read);
4149 dst : S5(write);
4150 DECODE : ID;
4151 LDST : MEM;
4152 %}
4153
4154 pipe_class fp_store_reg_s(fRegF src, memory mem)
4155 %{
4156 single_instruction;
4157 src : S1(read);
4158 mem : S5(write);
4159 DECODE : ID;
4160 LDST : MEM;
4161 %}
4162
4163 pipe_class fp_store_reg_d(fRegD src, memory mem)
4164 %{
4165 single_instruction;
4166 src : S1(read);
4167 mem : S5(write);
4168 DECODE : ID;
4169 LDST : MEM;
4170 %}
4171
4172 //------- Integer ALU operations --------------------------
4173
4174 // Integer ALU reg-reg operation
4175 // Operands needs in ID, result generated in EX
4176 // E.g. ADD Rd, Rs1, Rs2
4177 pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2)
4178 %{
4179 single_instruction;
4180 dst : EX(write);
4181 src1 : ID(read);
4182 src2 : ID(read);
4183 DECODE : ID;
4184 ALU : EX;
4185 %}
4186
4187 // Integer ALU reg operation with constant shift
4188 // E.g. SLLI Rd, Rs1, #shift
4189 pipe_class ialu_reg_shift(iRegI dst, iRegI src1)
4190 %{
4191 single_instruction;
4192 dst : EX(write);
4193 src1 : ID(read);
4194 DECODE : ID;
4195 ALU : EX;
4196 %}
4197
4198 // Integer ALU reg-reg operation with variable shift
4199 // both operands must be available in ID
4200 // E.g. SLL Rd, Rs1, Rs2
4201 pipe_class ialu_reg_reg_vshift(iRegI dst, iRegI src1, iRegI src2)
4202 %{
4203 single_instruction;
4204 dst : EX(write);
4205 src1 : ID(read);
4206 src2 : ID(read);
4207 DECODE : ID;
4208 ALU : EX;
4209 %}
4210
4211 // Integer ALU reg operation
4212 // E.g. NEG Rd, Rs2
4213 pipe_class ialu_reg(iRegI dst, iRegI src)
4214 %{
4215 single_instruction;
4216 dst : EX(write);
4217 src : ID(read);
4218 DECODE : ID;
4219 ALU : EX;
4220 %}
4221
4222 // Integer ALU reg immediate operation
4223 // E.g. ADDI Rd, Rs1, #imm
4224 pipe_class ialu_reg_imm(iRegI dst, iRegI src1)
4225 %{
4226 single_instruction;
4227 dst : EX(write);
4228 src1 : ID(read);
4229 DECODE : ID;
4230 ALU : EX;
4231 %}
4232
4233 // Integer ALU immediate operation (no source operands)
4234 // E.g. LI Rd, #imm
4235 pipe_class ialu_imm(iRegI dst)
4236 %{
4237 single_instruction;
4238 dst : EX(write);
4239 DECODE : ID;
4240 ALU : EX;
4241 %}
4242
4243 //------- Multiply pipeline operations --------------------
4244
4245 // Multiply reg-reg
4246 // E.g. MULW Rd, Rs1, Rs2
4247 pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2)
4248 %{
4249 single_instruction;
4250 dst : WR(write);
4251 src1 : ID(read);
4252 src2 : ID(read);
4253 DECODE : ID;
4254 MUL : WR;
4255 %}
4256
4257 // E.g. MUL RD, Rs1, Rs2
4258 pipe_class lmul_reg_reg(iRegL dst, iRegL src1, iRegL src2)
4259 %{
4260 single_instruction;
4261 fixed_latency(3); // Maximum latency for 64 bit mul
4262 dst : WR(write);
4263 src1 : ID(read);
4264 src2 : ID(read);
4265 DECODE : ID;
4266 MUL : WR;
4267 %}
4268
4269 //------- Divide pipeline operations --------------------
4270
4271 // E.g. DIVW Rd, Rs1, Rs2
4272 pipe_class idiv_reg_reg(iRegI dst, iRegI src1, iRegI src2)
4273 %{
4274 single_instruction;
4275 fixed_latency(8); // Maximum latency for 32 bit divide
4276 dst : WR(write);
4277 src1 : ID(read);
4278 src2 : ID(read);
4279 DECODE : ID;
4280 DIV : WR;
4281 %}
4282
4283 // E.g. DIV RD, Rs1, Rs2
4284 pipe_class ldiv_reg_reg(iRegL dst, iRegL src1, iRegL src2)
4285 %{
4286 single_instruction;
4287 fixed_latency(16); // Maximum latency for 64 bit divide
4288 dst : WR(write);
4289 src1 : ID(read);
4290 src2 : ID(read);
4291 DECODE : ID;
4292 DIV : WR;
4293 %}
4294
4295 //------- Load pipeline operations ------------------------
4296
4297 // Load - prefetch
4298 // Eg. PREFETCH_W mem
4299 pipe_class iload_prefetch(memory mem)
4300 %{
4301 single_instruction;
4302 mem : ID(read);
4303 DECODE : ID;
4304 LDST : MEM;
4305 %}
4306
4307 // Load - reg, mem
4308 // E.g. LA Rd, mem
4309 pipe_class iload_reg_mem(iRegI dst, memory mem)
4310 %{
4311 single_instruction;
4312 dst : WR(write);
4313 mem : ID(read);
4314 DECODE : ID;
4315 LDST : MEM;
4316 %}
4317
4318 // Load - reg, reg
4319 // E.g. LD Rd, Rs
4320 pipe_class iload_reg_reg(iRegI dst, iRegI src)
4321 %{
4322 single_instruction;
4323 dst : WR(write);
4324 src : ID(read);
4325 DECODE : ID;
4326 LDST : MEM;
4327 %}
4328
4329 //------- Store pipeline operations -----------------------
4330
4331 // Store - zr, mem
4332 // E.g. SD zr, mem
4333 pipe_class istore_mem(memory mem)
4334 %{
4335 single_instruction;
4336 mem : ID(read);
4337 DECODE : ID;
4338 LDST : MEM;
4339 %}
4340
4341 // Store - reg, mem
4342 // E.g. SD Rs, mem
4343 pipe_class istore_reg_mem(iRegI src, memory mem)
4344 %{
4345 single_instruction;
4346 mem : ID(read);
4347 src : EX(read);
4348 DECODE : ID;
4349 LDST : MEM;
4350 %}
4351
4352 // Store - reg, reg
4353 // E.g. SD Rs2, Rs1
4354 pipe_class istore_reg_reg(iRegI dst, iRegI src)
4355 %{
4356 single_instruction;
4357 dst : ID(read);
4358 src : EX(read);
4359 DECODE : ID;
4360 LDST : MEM;
4361 %}
4362
4363 //------- Control transfer pipeline operations ------------
4364
4365 // Branch
4366 pipe_class pipe_branch()
4367 %{
4368 single_instruction;
4369 DECODE : ID;
4370 BRANCH : EX;
4371 %}
4372
4373 // Branch
4374 pipe_class pipe_branch_reg(iRegI src)
4375 %{
4376 single_instruction;
4377 src : ID(read);
4378 DECODE : ID;
4379 BRANCH : EX;
4380 %}
4381
4382 // Compare & Branch
4383 // E.g. BEQ Rs1, Rs2, L
4384 pipe_class pipe_cmp_branch(iRegI src1, iRegI src2)
4385 %{
4386 single_instruction;
4387 src1 : ID(read);
4388 src2 : ID(read);
4389 DECODE : ID;
4390 BRANCH : EX;
4391 %}
4392
4393 // E.g. BEQZ Rs, L
4394 pipe_class pipe_cmpz_branch(iRegI src)
4395 %{
4396 single_instruction;
4397 src : ID(read);
4398 DECODE : ID;
4399 BRANCH : EX;
4400 %}
4401
4402 //------- Synchronisation operations ----------------------
4403 // Any operation requiring serialization
4404 // E.g. FENCE/Atomic Ops/Load Acquire/Store Release
4405 pipe_class pipe_serial()
4406 %{
4407 single_instruction;
4408 force_serialization;
4409 fixed_latency(16);
4410 DECODE : ID;
4411 LDST : MEM;
4412 %}
4413
4414 pipe_class pipe_slow()
4415 %{
4416 instruction_count(10);
4417 multiple_bundles;
4418 force_serialization;
4419 fixed_latency(16);
4420 DECODE : ID;
4421 LDST : MEM;
4422 %}
4423
4424 // Empty pipeline class
4425 pipe_class pipe_class_empty()
4426 %{
4427 single_instruction;
4428 fixed_latency(0);
4429 %}
4430
4431 // Default pipeline class.
4432 pipe_class pipe_class_default()
4433 %{
4434 single_instruction;
4435 fixed_latency(2);
4436 %}
4437
4438 // Pipeline class for compares.
4439 pipe_class pipe_class_compare()
4440 %{
4441 single_instruction;
4442 fixed_latency(16);
4443 %}
4444
4445 // Pipeline class for memory operations.
4446 pipe_class pipe_class_memory()
4447 %{
4448 single_instruction;
4449 fixed_latency(16);
4450 %}
4451
4452 // Pipeline class for call.
4453 pipe_class pipe_class_call()
4454 %{
4455 single_instruction;
4456 fixed_latency(100);
4457 %}
4458
4459 // Define the class for the Nop node.
4460 define %{
4461 MachNop = pipe_class_empty;
4462 %}
4463 %}
4464 //----------INSTRUCTIONS-------------------------------------------------------
4465 //
4466 // match -- States which machine-independent subtree may be replaced
4467 // by this instruction.
4468 // ins_cost -- The estimated cost of this instruction is used by instruction
4469 // selection to identify a minimum cost tree of machine
4470 // instructions that matches a tree of machine-independent
4471 // instructions.
4472 // format -- A string providing the disassembly for this instruction.
4473 // The value of an instruction's operand may be inserted
4474 // by referring to it with a '$' prefix.
4475 // opcode -- Three instruction opcodes may be provided. These are referred
4476 // to within an encode class as $primary, $secondary, and $tertiary
4477 // rrspectively. The primary opcode is commonly used to
4478 // indicate the type of machine instruction, while secondary
4479 // and tertiary are often used for prefix options or addressing
4480 // modes.
4481 // ins_encode -- A list of encode classes with parameters. The encode class
4482 // name must have been defined in an 'enc_class' specification
4483 // in the encode section of the architecture description.
4484
4485 // ============================================================================
4486 // Memory (Load/Store) Instructions
4487
4488 // Load Instructions
4489
4490 // Load Byte (8 bit signed)
4491 instruct loadB(iRegINoSp dst, memory mem)
4492 %{
4493 match(Set dst (LoadB mem));
4494
4495 ins_cost(LOAD_COST);
4496 format %{ "lb $dst, $mem\t# byte, #@loadB" %}
4497
4498 ins_encode %{
4499 __ lb(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4500 %}
4501
4502 ins_pipe(iload_reg_mem);
4503 %}
4504
4505 // Load Byte (8 bit signed) into long
4506 instruct loadB2L(iRegLNoSp dst, memory mem)
4507 %{
4508 match(Set dst (ConvI2L (LoadB mem)));
4509
4510 ins_cost(LOAD_COST);
4511 format %{ "lb $dst, $mem\t# byte, #@loadB2L" %}
4512
4513 ins_encode %{
4514 __ lb(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4515 %}
4516
4517 ins_pipe(iload_reg_mem);
4518 %}
4519
4520 // Load Byte (8 bit unsigned)
4521 instruct loadUB(iRegINoSp dst, memory mem)
4522 %{
4523 match(Set dst (LoadUB mem));
4524
4525 ins_cost(LOAD_COST);
4526 format %{ "lbu $dst, $mem\t# byte, #@loadUB" %}
4527
4528 ins_encode %{
4529 __ lbu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4530 %}
4531
4532 ins_pipe(iload_reg_mem);
4533 %}
4534
4535 // Load Byte (8 bit unsigned) into long
4536 instruct loadUB2L(iRegLNoSp dst, memory mem)
4537 %{
4538 match(Set dst (ConvI2L (LoadUB mem)));
4539
4540 ins_cost(LOAD_COST);
4541 format %{ "lbu $dst, $mem\t# byte, #@loadUB2L" %}
4542
4543 ins_encode %{
4544 __ lbu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4545 %}
4546
4547 ins_pipe(iload_reg_mem);
4548 %}
4549
4550 // Load Short (16 bit signed)
4551 instruct loadS(iRegINoSp dst, memory mem)
4552 %{
4553 match(Set dst (LoadS mem));
4554
4555 ins_cost(LOAD_COST);
4556 format %{ "lh $dst, $mem\t# short, #@loadS" %}
4557
4558 ins_encode %{
4559 __ lh(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4560 %}
4561
4562 ins_pipe(iload_reg_mem);
4563 %}
4564
4565 // Load Short (16 bit signed) into long
4566 instruct loadS2L(iRegLNoSp dst, memory mem)
4567 %{
4568 match(Set dst (ConvI2L (LoadS mem)));
4569
4570 ins_cost(LOAD_COST);
4571 format %{ "lh $dst, $mem\t# short, #@loadS2L" %}
4572
4573 ins_encode %{
4574 __ lh(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4575 %}
4576
4577 ins_pipe(iload_reg_mem);
4578 %}
4579
4580 // Load Char (16 bit unsigned)
4581 instruct loadUS(iRegINoSp dst, memory mem)
4582 %{
4583 match(Set dst (LoadUS mem));
4584
4585 ins_cost(LOAD_COST);
4586 format %{ "lhu $dst, $mem\t# short, #@loadUS" %}
4587
4588 ins_encode %{
4589 __ lhu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4590 %}
4591
4592 ins_pipe(iload_reg_mem);
4593 %}
4594
4595 // Load Short/Char (16 bit unsigned) into long
4596 instruct loadUS2L(iRegLNoSp dst, memory mem)
4597 %{
4598 match(Set dst (ConvI2L (LoadUS mem)));
4599
4600 ins_cost(LOAD_COST);
4601 format %{ "lhu $dst, $mem\t# short, #@loadUS2L" %}
4602
4603 ins_encode %{
4604 __ lhu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4605 %}
4606
4607 ins_pipe(iload_reg_mem);
4608 %}
4609
4610 // Load Integer (32 bit signed)
4611 instruct loadI(iRegINoSp dst, memory mem)
4612 %{
4613 match(Set dst (LoadI mem));
4614
4615 ins_cost(LOAD_COST);
4616 format %{ "lw $dst, $mem\t# int, #@loadI" %}
4617
4618 ins_encode %{
4619 __ lw(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4620 %}
4621
4622 ins_pipe(iload_reg_mem);
4623 %}
4624
4625 // Load Integer (32 bit signed) into long
4626 instruct loadI2L(iRegLNoSp dst, memory mem)
4627 %{
4628 match(Set dst (ConvI2L (LoadI mem)));
4629
4630 ins_cost(LOAD_COST);
4631 format %{ "lw $dst, $mem\t# int, #@loadI2L" %}
4632
4633 ins_encode %{
4634 __ lw(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4635 %}
4636
4637 ins_pipe(iload_reg_mem);
4638 %}
4639
4640 // Load Integer (32 bit unsigned) into long
4641 instruct loadUI2L(iRegLNoSp dst, memory mem, immL_32bits mask)
4642 %{
4643 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
4644
4645 ins_cost(LOAD_COST);
4646 format %{ "lwu $dst, $mem\t# int, #@loadUI2L" %}
4647
4648 ins_encode %{
4649 __ lwu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4650 %}
4651
4652 ins_pipe(iload_reg_mem);
4653 %}
4654
4655 // Load Long (64 bit signed)
4656 instruct loadL(iRegLNoSp dst, memory mem)
4657 %{
4658 match(Set dst (LoadL mem));
4659
4660 ins_cost(LOAD_COST);
4661 format %{ "ld $dst, $mem\t# int, #@loadL" %}
4662
4663 ins_encode %{
4664 __ ld(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4665 %}
4666
4667 ins_pipe(iload_reg_mem);
4668 %}
4669
4670 // Load Range
4671 instruct loadRange(iRegINoSp dst, memory mem)
4672 %{
4673 match(Set dst (LoadRange mem));
4674
4675 ins_cost(LOAD_COST);
4676 format %{ "lwu $dst, $mem\t# range, #@loadRange" %}
4677
4678 ins_encode %{
4679 __ lwu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4680 %}
4681
4682 ins_pipe(iload_reg_mem);
4683 %}
4684
4685 // Load Pointer
4686 instruct loadP(iRegPNoSp dst, memory mem)
4687 %{
4688 match(Set dst (LoadP mem));
4689 predicate(n->as_Load()->barrier_data() == 0);
4690
4691 ins_cost(LOAD_COST);
4692 format %{ "ld $dst, $mem\t# ptr, #@loadP" %}
4693
4694 ins_encode %{
4695 __ ld(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4696 %}
4697
4698 ins_pipe(iload_reg_mem);
4699 %}
4700
4701 // Load Compressed Pointer
4702 instruct loadN(iRegNNoSp dst, memory mem)
4703 %{
4704 predicate(n->as_Load()->barrier_data() == 0);
4705 match(Set dst (LoadN mem));
4706
4707 ins_cost(LOAD_COST);
4708 format %{ "lwu $dst, $mem\t# compressed ptr, #@loadN" %}
4709
4710 ins_encode %{
4711 __ lwu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4712 %}
4713
4714 ins_pipe(iload_reg_mem);
4715 %}
4716
4717 // Load Klass Pointer
4718 instruct loadKlass(iRegPNoSp dst, memory mem)
4719 %{
4720 match(Set dst (LoadKlass mem));
4721
4722 ins_cost(LOAD_COST);
4723 format %{ "ld $dst, $mem\t# class, #@loadKlass" %}
4724
4725 ins_encode %{
4726 __ ld(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4727 %}
4728
4729 ins_pipe(iload_reg_mem);
4730 %}
4731
4732 // Load Narrow Klass Pointer
4733 instruct loadNKlass(iRegNNoSp dst, memory mem)
4734 %{
4735 predicate(!UseCompactObjectHeaders);
4736 match(Set dst (LoadNKlass mem));
4737
4738 ins_cost(LOAD_COST);
4739 format %{ "lwu $dst, $mem\t# compressed class ptr, #@loadNKlass" %}
4740
4741 ins_encode %{
4742 __ lwu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4743 %}
4744
4745 ins_pipe(iload_reg_mem);
4746 %}
4747
4748 instruct loadNKlassCompactHeaders(iRegNNoSp dst, memory mem)
4749 %{
4750 predicate(UseCompactObjectHeaders);
4751 match(Set dst (LoadNKlass mem));
4752
4753 ins_cost(LOAD_COST);
4754 format %{
4755 "lwu $dst, $mem\t# compressed klass ptr, shifted\n\t"
4756 "srli $dst, $dst, markWord::klass_shift_at_offset"
4757 %}
4758
4759 ins_encode %{
4760 Unimplemented();
4761 // __ lwu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4762 // __ srli(as_Register($dst$$reg), as_Register($dst$$reg), (unsigned) markWord::klass_shift_at_offset);
4763 %}
4764
4765 ins_pipe(iload_reg_mem);
4766 %}
4767
4768 // Load Float
4769 instruct loadF(fRegF dst, memory mem)
4770 %{
4771 match(Set dst (LoadF mem));
4772
4773 ins_cost(LOAD_COST);
4774 format %{ "flw $dst, $mem\t# float, #@loadF" %}
4775
4776 ins_encode %{
4777 __ flw(as_FloatRegister($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4778 %}
4779
4780 ins_pipe(fp_load_mem_s);
4781 %}
4782
4783 // Load Double
4784 instruct loadD(fRegD dst, memory mem)
4785 %{
4786 match(Set dst (LoadD mem));
4787
4788 ins_cost(LOAD_COST);
4789 format %{ "fld $dst, $mem\t# double, #@loadD" %}
4790
4791 ins_encode %{
4792 __ fld(as_FloatRegister($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4793 %}
4794
4795 ins_pipe(fp_load_mem_d);
4796 %}
4797
4798 // Load Int Constant
4799 instruct loadConI(iRegINoSp dst, immI src)
4800 %{
4801 match(Set dst src);
4802
4803 ins_cost(ALU_COST);
4804 format %{ "mv $dst, $src\t# int, #@loadConI" %}
4805
4806 ins_encode(riscv_enc_mov_imm(dst, src));
4807
4808 ins_pipe(ialu_imm);
4809 %}
4810
4811 // Load Long Constant
4812 instruct loadConL(iRegLNoSp dst, immL src)
4813 %{
4814 match(Set dst src);
4815
4816 ins_cost(ALU_COST);
4817 format %{ "mv $dst, $src\t# long, #@loadConL" %}
4818
4819 ins_encode(riscv_enc_mov_imm(dst, src));
4820
4821 ins_pipe(ialu_imm);
4822 %}
4823
4824 // Load Pointer Constant
4825 instruct loadConP(iRegPNoSp dst, immP con)
4826 %{
4827 match(Set dst con);
4828
4829 ins_cost(ALU_COST);
4830 format %{ "mv $dst, $con\t# ptr, #@loadConP" %}
4831
4832 ins_encode(riscv_enc_mov_p(dst, con));
4833
4834 ins_pipe(ialu_imm);
4835 %}
4836
4837 // Load Null Pointer Constant
4838 instruct loadConP0(iRegPNoSp dst, immP0 con)
4839 %{
4840 match(Set dst con);
4841
4842 ins_cost(ALU_COST);
4843 format %{ "mv $dst, $con\t# null pointer, #@loadConP0" %}
4844
4845 ins_encode(riscv_enc_mov_zero(dst));
4846
4847 ins_pipe(ialu_imm);
4848 %}
4849
4850 // Load Pointer Constant One
4851 instruct loadConP1(iRegPNoSp dst, immP_1 con)
4852 %{
4853 match(Set dst con);
4854
4855 ins_cost(ALU_COST);
4856 format %{ "mv $dst, $con\t# load ptr constant one, #@loadConP1" %}
4857
4858 ins_encode(riscv_enc_mov_p1(dst));
4859
4860 ins_pipe(ialu_imm);
4861 %}
4862
4863 // Load Byte Map Base Constant
4864 instruct loadByteMapBase(iRegPNoSp dst, immByteMapBase con)
4865 %{
4866 match(Set dst con);
4867 ins_cost(ALU_COST);
4868 format %{ "mv $dst, $con\t# Byte Map Base, #@loadByteMapBase" %}
4869
4870 ins_encode(riscv_enc_mov_byte_map_base(dst));
4871
4872 ins_pipe(ialu_imm);
4873 %}
4874
4875 // Load Narrow Pointer Constant
4876 instruct loadConN(iRegNNoSp dst, immN con)
4877 %{
4878 match(Set dst con);
4879
4880 ins_cost(ALU_COST * 4);
4881 format %{ "mv $dst, $con\t# compressed ptr, #@loadConN" %}
4882
4883 ins_encode(riscv_enc_mov_n(dst, con));
4884
4885 ins_pipe(ialu_imm);
4886 %}
4887
4888 // Load Narrow Null Pointer Constant
4889 instruct loadConN0(iRegNNoSp dst, immN0 con)
4890 %{
4891 match(Set dst con);
4892
4893 ins_cost(ALU_COST);
4894 format %{ "mv $dst, $con\t# compressed null pointer, #@loadConN0" %}
4895
4896 ins_encode(riscv_enc_mov_zero(dst));
4897
4898 ins_pipe(ialu_imm);
4899 %}
4900
4901 // Load Narrow Klass Constant
4902 instruct loadConNKlass(iRegNNoSp dst, immNKlass con)
4903 %{
4904 match(Set dst con);
4905
4906 ins_cost(ALU_COST * 6);
4907 format %{ "mv $dst, $con\t# compressed klass ptr, #@loadConNKlass" %}
4908
4909 ins_encode(riscv_enc_mov_nk(dst, con));
4910
4911 ins_pipe(ialu_imm);
4912 %}
4913
4914 // Load Float Constant
4915 instruct loadConF(fRegF dst, immF con) %{
4916 match(Set dst con);
4917
4918 ins_cost(LOAD_COST);
4919 format %{
4920 "flw $dst, [$constantaddress]\t# load from constant table: float=$con, #@loadConF"
4921 %}
4922
4923 ins_encode %{
4924 if (MacroAssembler::can_fp_imm_load($con$$constant)) {
4925 __ fli_s(as_FloatRegister($dst$$reg), $con$$constant);
4926 } else {
4927 __ flw(as_FloatRegister($dst$$reg), $constantaddress($con));
4928 }
4929 %}
4930
4931 ins_pipe(fp_load_constant_s);
4932 %}
4933
4934 instruct loadConF0(fRegF dst, immF0 con) %{
4935 match(Set dst con);
4936
4937 ins_cost(XFER_COST);
4938
4939 format %{ "fmv.w.x $dst, zr\t# float, #@loadConF0" %}
4940
4941 ins_encode %{
4942 __ fmv_w_x(as_FloatRegister($dst$$reg), zr);
4943 %}
4944
4945 ins_pipe(fp_load_constant_s);
4946 %}
4947
4948 // Load Double Constant
4949 instruct loadConD(fRegD dst, immD con) %{
4950 match(Set dst con);
4951
4952 ins_cost(LOAD_COST);
4953 format %{
4954 "fld $dst, [$constantaddress]\t# load from constant table: double=$con, #@loadConD"
4955 %}
4956
4957 ins_encode %{
4958 if (MacroAssembler::can_dp_imm_load($con$$constant)) {
4959 __ fli_d(as_FloatRegister($dst$$reg), $con$$constant);
4960 } else {
4961 __ fld(as_FloatRegister($dst$$reg), $constantaddress($con));
4962 }
4963 %}
4964
4965 ins_pipe(fp_load_constant_d);
4966 %}
4967
4968 instruct loadConD0(fRegD dst, immD0 con) %{
4969 match(Set dst con);
4970
4971 ins_cost(XFER_COST);
4972
4973 format %{ "fmv.d.x $dst, zr\t# double, #@loadConD0" %}
4974
4975 ins_encode %{
4976 __ fmv_d_x(as_FloatRegister($dst$$reg), zr);
4977 %}
4978
4979 ins_pipe(fp_load_constant_d);
4980 %}
4981
4982 // Store Byte
4983 instruct storeB(iRegIorL2I src, memory mem)
4984 %{
4985 match(Set mem (StoreB mem src));
4986
4987 ins_cost(STORE_COST);
4988 format %{ "sb $src, $mem\t# byte, #@storeB" %}
4989
4990 ins_encode %{
4991 __ sb(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
4992 %}
4993
4994 ins_pipe(istore_reg_mem);
4995 %}
4996
4997 instruct storeimmB0(immI0 zero, memory mem)
4998 %{
4999 match(Set mem (StoreB mem zero));
5000
5001 ins_cost(STORE_COST);
5002 format %{ "sb zr, $mem\t# byte, #@storeimmB0" %}
5003
5004 ins_encode %{
5005 __ sb(zr, Address(as_Register($mem$$base), $mem$$disp));
5006 %}
5007
5008 ins_pipe(istore_mem);
5009 %}
5010
5011 // Store Char/Short
5012 instruct storeC(iRegIorL2I src, memory mem)
5013 %{
5014 match(Set mem (StoreC mem src));
5015
5016 ins_cost(STORE_COST);
5017 format %{ "sh $src, $mem\t# short, #@storeC" %}
5018
5019 ins_encode %{
5020 __ sh(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5021 %}
5022
5023 ins_pipe(istore_reg_mem);
5024 %}
5025
5026 instruct storeimmC0(immI0 zero, memory mem)
5027 %{
5028 match(Set mem (StoreC mem zero));
5029
5030 ins_cost(STORE_COST);
5031 format %{ "sh zr, $mem\t# short, #@storeimmC0" %}
5032
5033 ins_encode %{
5034 __ sh(zr, Address(as_Register($mem$$base), $mem$$disp));
5035 %}
5036
5037 ins_pipe(istore_mem);
5038 %}
5039
5040 // Store Integer
5041 instruct storeI(iRegIorL2I src, memory mem)
5042 %{
5043 match(Set mem(StoreI mem src));
5044
5045 ins_cost(STORE_COST);
5046 format %{ "sw $src, $mem\t# int, #@storeI" %}
5047
5048 ins_encode %{
5049 __ sw(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5050 %}
5051
5052 ins_pipe(istore_reg_mem);
5053 %}
5054
5055 instruct storeimmI0(immI0 zero, memory mem)
5056 %{
5057 match(Set mem(StoreI mem zero));
5058
5059 ins_cost(STORE_COST);
5060 format %{ "sw zr, $mem\t# int, #@storeimmI0" %}
5061
5062 ins_encode %{
5063 __ sw(zr, Address(as_Register($mem$$base), $mem$$disp));
5064 %}
5065
5066 ins_pipe(istore_mem);
5067 %}
5068
5069 // Store Long (64 bit signed)
5070 instruct storeL(iRegL src, memory mem)
5071 %{
5072 match(Set mem (StoreL mem src));
5073
5074 ins_cost(STORE_COST);
5075 format %{ "sd $src, $mem\t# long, #@storeL" %}
5076
5077 ins_encode %{
5078 __ sd(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5079 %}
5080
5081 ins_pipe(istore_reg_mem);
5082 %}
5083
5084 // Store Long (64 bit signed)
5085 instruct storeimmL0(immL0 zero, memory mem)
5086 %{
5087 match(Set mem (StoreL mem zero));
5088
5089 ins_cost(STORE_COST);
5090 format %{ "sd zr, $mem\t# long, #@storeimmL0" %}
5091
5092 ins_encode %{
5093 __ sd(zr, Address(as_Register($mem$$base), $mem$$disp));
5094 %}
5095
5096 ins_pipe(istore_mem);
5097 %}
5098
5099 // Store Pointer
5100 instruct storeP(iRegP src, memory mem)
5101 %{
5102 match(Set mem (StoreP mem src));
5103 predicate(n->as_Store()->barrier_data() == 0);
5104
5105 ins_cost(STORE_COST);
5106 format %{ "sd $src, $mem\t# ptr, #@storeP" %}
5107
5108 ins_encode %{
5109 __ sd(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5110 %}
5111
5112 ins_pipe(istore_reg_mem);
5113 %}
5114
5115 // Store Pointer
5116 instruct storeimmP0(immP0 zero, memory mem)
5117 %{
5118 match(Set mem (StoreP mem zero));
5119 predicate(n->as_Store()->barrier_data() == 0);
5120
5121 ins_cost(STORE_COST);
5122 format %{ "sd zr, $mem\t# ptr, #@storeimmP0" %}
5123
5124 ins_encode %{
5125 __ sd(zr, Address(as_Register($mem$$base), $mem$$disp));
5126 %}
5127
5128 ins_pipe(istore_mem);
5129 %}
5130
5131 // Store Compressed Pointer
5132 instruct storeN(iRegN src, memory mem)
5133 %{
5134 predicate(n->as_Store()->barrier_data() == 0);
5135 match(Set mem (StoreN mem src));
5136
5137 ins_cost(STORE_COST);
5138 format %{ "sw $src, $mem\t# compressed ptr, #@storeN" %}
5139
5140 ins_encode %{
5141 __ sw(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5142 %}
5143
5144 ins_pipe(istore_reg_mem);
5145 %}
5146
5147 instruct storeImmN0(immN0 zero, memory mem)
5148 %{
5149 predicate(n->as_Store()->barrier_data() == 0);
5150 match(Set mem (StoreN mem zero));
5151
5152 ins_cost(STORE_COST);
5153 format %{ "sw zr, $mem\t# compressed ptr, #@storeImmN0" %}
5154
5155 ins_encode %{
5156 __ sw(zr, Address(as_Register($mem$$base), $mem$$disp));
5157 %}
5158
5159 ins_pipe(istore_reg_mem);
5160 %}
5161
5162 // Store Float
5163 instruct storeF(fRegF src, memory mem)
5164 %{
5165 match(Set mem (StoreF mem src));
5166
5167 ins_cost(STORE_COST);
5168 format %{ "fsw $src, $mem\t# float, #@storeF" %}
5169
5170 ins_encode %{
5171 __ fsw(as_FloatRegister($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5172 %}
5173
5174 ins_pipe(fp_store_reg_s);
5175 %}
5176
5177 // Store Double
5178 instruct storeD(fRegD src, memory mem)
5179 %{
5180 match(Set mem (StoreD mem src));
5181
5182 ins_cost(STORE_COST);
5183 format %{ "fsd $src, $mem\t# double, #@storeD" %}
5184
5185 ins_encode %{
5186 __ fsd(as_FloatRegister($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5187 %}
5188
5189 ins_pipe(fp_store_reg_d);
5190 %}
5191
5192 // Store Compressed Klass Pointer
5193 instruct storeNKlass(iRegN src, memory mem)
5194 %{
5195 match(Set mem (StoreNKlass mem src));
5196
5197 ins_cost(STORE_COST);
5198 format %{ "sw $src, $mem\t# compressed klass ptr, #@storeNKlass" %}
5199
5200 ins_encode %{
5201 __ sw(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5202 %}
5203
5204 ins_pipe(istore_reg_mem);
5205 %}
5206
5207 // ============================================================================
5208 // Prefetch instructions
5209 // Must be safe to execute with invalid address (cannot fault).
5210
5211 instruct prefetchalloc( memory mem ) %{
5212 predicate(UseZicbop);
5213 match(PrefetchAllocation mem);
5214
5215 ins_cost(ALU_COST * 1);
5216 format %{ "prefetch_w $mem\t# Prefetch for write" %}
5217
5218 ins_encode %{
5219 if (Assembler::is_simm12($mem$$disp)) {
5220 if (($mem$$disp & 0x1f) == 0) {
5221 __ prefetch_w(as_Register($mem$$base), $mem$$disp);
5222 } else {
5223 __ addi(t0, as_Register($mem$$base), $mem$$disp);
5224 __ prefetch_w(t0, 0);
5225 }
5226 } else {
5227 __ mv(t0, $mem$$disp);
5228 __ add(t0, as_Register($mem$$base), t0);
5229 __ prefetch_w(t0, 0);
5230 }
5231 %}
5232
5233 ins_pipe(iload_prefetch);
5234 %}
5235
5236 // ============================================================================
5237 // Atomic operation instructions
5238 //
5239
5240 // standard CompareAndSwapX when we are using barriers
5241 // these have higher priority than the rules selected by a predicate
5242 instruct compareAndSwapB(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5243 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5244 %{
5245 match(Set res (CompareAndSwapB mem (Binary oldval newval)));
5246
5247 ins_cost(LOAD_COST + STORE_COST + ALU_COST * 10 + BRANCH_COST * 4);
5248
5249 effect(TEMP_DEF res, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3, KILL cr);
5250
5251 format %{
5252 "cmpxchg $mem, $oldval, $newval\t# (byte) if $mem == $oldval then $mem <-- $newval\n\t"
5253 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapB"
5254 %}
5255
5256 ins_encode %{
5257 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5258 Assembler::relaxed /* acquire */, Assembler::rl /* release */, $res$$Register,
5259 true /* result as bool */, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5260 %}
5261
5262 ins_pipe(pipe_slow);
5263 %}
5264
5265 instruct compareAndSwapS(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5266 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5267 %{
5268 match(Set res (CompareAndSwapS mem (Binary oldval newval)));
5269
5270 ins_cost(LOAD_COST + STORE_COST + ALU_COST * 11 + BRANCH_COST * 4);
5271
5272 effect(TEMP_DEF res, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3, KILL cr);
5273
5274 format %{
5275 "cmpxchg $mem, $oldval, $newval\t# (short) if $mem == $oldval then $mem <-- $newval\n\t"
5276 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapS"
5277 %}
5278
5279 ins_encode %{
5280 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5281 Assembler::relaxed /* acquire */, Assembler::rl /* release */, $res$$Register,
5282 true /* result as bool */, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5283 %}
5284
5285 ins_pipe(pipe_slow);
5286 %}
5287
5288 instruct compareAndSwapI(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5289 %{
5290 match(Set res (CompareAndSwapI mem (Binary oldval newval)));
5291
5292 ins_cost(LOAD_COST + STORE_COST + ALU_COST * 6 + BRANCH_COST * 4);
5293
5294 format %{
5295 "cmpxchg $mem, $oldval, $newval\t# (int) if $mem == $oldval then $mem <-- $newval\n\t"
5296 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapI"
5297 %}
5298
5299 ins_encode(riscv_enc_cmpxchgw(res, mem, oldval, newval));
5300
5301 ins_pipe(pipe_slow);
5302 %}
5303
5304 instruct compareAndSwapL(iRegINoSp res, indirect mem, iRegL oldval, iRegL newval)
5305 %{
5306 match(Set res (CompareAndSwapL mem (Binary oldval newval)));
5307
5308 ins_cost(LOAD_COST + STORE_COST + ALU_COST * 6 + BRANCH_COST * 4);
5309
5310 format %{
5311 "cmpxchg $mem, $oldval, $newval\t# (long) if $mem == $oldval then $mem <-- $newval\n\t"
5312 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapL"
5313 %}
5314
5315 ins_encode(riscv_enc_cmpxchg(res, mem, oldval, newval));
5316
5317 ins_pipe(pipe_slow);
5318 %}
5319
5320 instruct compareAndSwapP(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval)
5321 %{
5322 predicate(n->as_LoadStore()->barrier_data() == 0);
5323
5324 match(Set res (CompareAndSwapP mem (Binary oldval newval)));
5325
5326 ins_cost(LOAD_COST + STORE_COST + ALU_COST * 6 + BRANCH_COST * 4);
5327
5328 format %{
5329 "cmpxchg $mem, $oldval, $newval\t# (ptr) if $mem == $oldval then $mem <-- $newval\n\t"
5330 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapP"
5331 %}
5332
5333 ins_encode(riscv_enc_cmpxchg(res, mem, oldval, newval));
5334
5335 ins_pipe(pipe_slow);
5336 %}
5337
5338 instruct compareAndSwapN(iRegINoSp res, indirect mem, iRegN oldval, iRegN newval)
5339 %{
5340 predicate(n->as_LoadStore()->barrier_data() == 0);
5341 match(Set res (CompareAndSwapN mem (Binary oldval newval)));
5342
5343 ins_cost(LOAD_COST + STORE_COST + ALU_COST * 8 + BRANCH_COST * 4);
5344
5345 format %{
5346 "cmpxchg $mem, $oldval, $newval\t# (narrow oop) if $mem == $oldval then $mem <-- $newval\n\t"
5347 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapN"
5348 %}
5349
5350 ins_encode(riscv_enc_cmpxchgn(res, mem, oldval, newval));
5351
5352 ins_pipe(pipe_slow);
5353 %}
5354
5355 // alternative CompareAndSwapX when we are eliding barriers
5356 instruct compareAndSwapBAcq(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5357 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5358 %{
5359 predicate(needs_acquiring_load_reserved(n));
5360
5361 match(Set res (CompareAndSwapB mem (Binary oldval newval)));
5362
5363 ins_cost(LOAD_COST + STORE_COST + ALU_COST * 10 + BRANCH_COST * 4);
5364
5365 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5366
5367 format %{
5368 "cmpxchg_acq $mem, $oldval, $newval\t# (byte) if $mem == $oldval then $mem <-- $newval\n\t"
5369 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapBAcq"
5370 %}
5371
5372 ins_encode %{
5373 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5374 Assembler::aq /* acquire */, Assembler::rl /* release */, $res$$Register,
5375 true /* result as bool */, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5376 %}
5377
5378 ins_pipe(pipe_slow);
5379 %}
5380
5381 instruct compareAndSwapSAcq(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5382 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5383 %{
5384 predicate(needs_acquiring_load_reserved(n));
5385
5386 match(Set res (CompareAndSwapS mem (Binary oldval newval)));
5387
5388 ins_cost(LOAD_COST + STORE_COST + ALU_COST * 11 + BRANCH_COST * 4);
5389
5390 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5391
5392 format %{
5393 "cmpxchg_acq $mem, $oldval, $newval\t# (short) if $mem == $oldval then $mem <-- $newval\n\t"
5394 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapSAcq"
5395 %}
5396
5397 ins_encode %{
5398 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5399 Assembler::aq /* acquire */, Assembler::rl /* release */, $res$$Register,
5400 true /* result as bool */, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5401 %}
5402
5403 ins_pipe(pipe_slow);
5404 %}
5405
5406 instruct compareAndSwapIAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5407 %{
5408 predicate(needs_acquiring_load_reserved(n));
5409
5410 match(Set res (CompareAndSwapI mem (Binary oldval newval)));
5411
5412 ins_cost(LOAD_COST + STORE_COST + ALU_COST * 6 + BRANCH_COST * 4);
5413
5414 format %{
5415 "cmpxchg_acq $mem, $oldval, $newval\t# (int) if $mem == $oldval then $mem <-- $newval\n\t"
5416 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapIAcq"
5417 %}
5418
5419 ins_encode(riscv_enc_cmpxchgw_acq(res, mem, oldval, newval));
5420
5421 ins_pipe(pipe_slow);
5422 %}
5423
5424 instruct compareAndSwapLAcq(iRegINoSp res, indirect mem, iRegL oldval, iRegL newval)
5425 %{
5426 predicate(needs_acquiring_load_reserved(n));
5427
5428 match(Set res (CompareAndSwapL mem (Binary oldval newval)));
5429
5430 ins_cost(LOAD_COST + STORE_COST + ALU_COST * 6 + BRANCH_COST * 4);
5431
5432 format %{
5433 "cmpxchg_acq $mem, $oldval, $newval\t# (long) if $mem == $oldval then $mem <-- $newval\n\t"
5434 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapLAcq"
5435 %}
5436
5437 ins_encode(riscv_enc_cmpxchg_acq(res, mem, oldval, newval));
5438
5439 ins_pipe(pipe_slow);
5440 %}
5441
5442 instruct compareAndSwapPAcq(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval)
5443 %{
5444 predicate(needs_acquiring_load_reserved(n) && (n->as_LoadStore()->barrier_data() == 0));
5445
5446 match(Set res (CompareAndSwapP mem (Binary oldval newval)));
5447
5448 ins_cost(LOAD_COST + STORE_COST + ALU_COST * 6 + BRANCH_COST * 4);
5449
5450 format %{
5451 "cmpxchg_acq $mem, $oldval, $newval\t# (ptr) if $mem == $oldval then $mem <-- $newval\n\t"
5452 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapPAcq"
5453 %}
5454
5455 ins_encode(riscv_enc_cmpxchg_acq(res, mem, oldval, newval));
5456
5457 ins_pipe(pipe_slow);
5458 %}
5459
5460 instruct compareAndSwapNAcq(iRegINoSp res, indirect mem, iRegN oldval, iRegN newval)
5461 %{
5462 predicate(needs_acquiring_load_reserved(n) && n->as_LoadStore()->barrier_data() == 0);
5463
5464 match(Set res (CompareAndSwapN mem (Binary oldval newval)));
5465
5466 ins_cost(LOAD_COST + STORE_COST + ALU_COST * 8 + BRANCH_COST * 4);
5467
5468 format %{
5469 "cmpxchg_acq $mem, $oldval, $newval\t# (narrow oop) if $mem == $oldval then $mem <-- $newval\n\t"
5470 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapNAcq"
5471 %}
5472
5473 ins_encode(riscv_enc_cmpxchgn_acq(res, mem, oldval, newval));
5474
5475 ins_pipe(pipe_slow);
5476 %}
5477
5478 // Sundry CAS operations. Note that release is always true,
5479 // regardless of the memory ordering of the CAS. This is because we
5480 // need the volatile case to be sequentially consistent but there is
5481 // no trailing StoreLoad barrier emitted by C2. Unfortunately we
5482 // can't check the type of memory ordering here, so we always emit a
5483 // sc_d(w) with rl bit set.
5484 instruct compareAndExchangeB(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5485 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5486 %{
5487 match(Set res (CompareAndExchangeB mem (Binary oldval newval)));
5488
5489 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST * 5);
5490
5491 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5492
5493 format %{
5494 "cmpxchg $res = $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeB"
5495 %}
5496
5497 ins_encode %{
5498 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5499 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
5500 /*result_as_bool*/ false, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5501 %}
5502
5503 ins_pipe(pipe_slow);
5504 %}
5505
5506 instruct compareAndExchangeS(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5507 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5508 %{
5509 match(Set res (CompareAndExchangeS mem (Binary oldval newval)));
5510
5511 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST * 6);
5512
5513 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5514
5515 format %{
5516 "cmpxchg $res = $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeS"
5517 %}
5518
5519 ins_encode %{
5520 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5521 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
5522 /*result_as_bool*/ false, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5523 %}
5524
5525 ins_pipe(pipe_slow);
5526 %}
5527
5528 instruct compareAndExchangeI(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5529 %{
5530 match(Set res (CompareAndExchangeI mem (Binary oldval newval)));
5531
5532 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST);
5533
5534 effect(TEMP_DEF res);
5535
5536 format %{
5537 "cmpxchg $res = $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeI"
5538 %}
5539
5540 ins_encode %{
5541 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
5542 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5543 %}
5544
5545 ins_pipe(pipe_slow);
5546 %}
5547
5548 instruct compareAndExchangeL(iRegLNoSp res, indirect mem, iRegL oldval, iRegL newval)
5549 %{
5550 match(Set res (CompareAndExchangeL mem (Binary oldval newval)));
5551
5552 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST);
5553
5554 effect(TEMP_DEF res);
5555
5556 format %{
5557 "cmpxchg $res = $mem, $oldval, $newval\t# (long, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeL"
5558 %}
5559
5560 ins_encode %{
5561 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5562 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5563 %}
5564
5565 ins_pipe(pipe_slow);
5566 %}
5567
5568 instruct compareAndExchangeN(iRegNNoSp res, indirect mem, iRegN oldval, iRegN newval)
5569 %{
5570 predicate(n->as_LoadStore()->barrier_data() == 0);
5571 match(Set res (CompareAndExchangeN mem (Binary oldval newval)));
5572
5573 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST * 3);
5574
5575 effect(TEMP_DEF res);
5576
5577 format %{
5578 "cmpxchg $res = $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeN"
5579 %}
5580
5581 ins_encode %{
5582 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
5583 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5584 %}
5585
5586 ins_pipe(pipe_slow);
5587 %}
5588
5589 instruct compareAndExchangeP(iRegPNoSp res, indirect mem, iRegP oldval, iRegP newval)
5590 %{
5591 predicate(n->as_LoadStore()->barrier_data() == 0);
5592 match(Set res (CompareAndExchangeP mem (Binary oldval newval)));
5593
5594 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST);
5595
5596 effect(TEMP_DEF res);
5597
5598 format %{
5599 "cmpxchg $res = $mem, $oldval, $newval\t# (ptr, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeP"
5600 %}
5601
5602 ins_encode %{
5603 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5604 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5605 %}
5606
5607 ins_pipe(pipe_slow);
5608 %}
5609
5610 instruct compareAndExchangeBAcq(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5611 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5612 %{
5613 predicate(needs_acquiring_load_reserved(n));
5614
5615 match(Set res (CompareAndExchangeB mem (Binary oldval newval)));
5616
5617 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST * 5);
5618
5619 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5620
5621 format %{
5622 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeBAcq"
5623 %}
5624
5625 ins_encode %{
5626 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5627 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
5628 /*result_as_bool*/ false, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5629 %}
5630
5631 ins_pipe(pipe_slow);
5632 %}
5633
5634 instruct compareAndExchangeSAcq(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5635 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5636 %{
5637 predicate(needs_acquiring_load_reserved(n));
5638
5639 match(Set res (CompareAndExchangeS mem (Binary oldval newval)));
5640
5641 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST * 6);
5642
5643 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5644
5645 format %{
5646 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeSAcq"
5647 %}
5648
5649 ins_encode %{
5650 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5651 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
5652 /*result_as_bool*/ false, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5653 %}
5654
5655 ins_pipe(pipe_slow);
5656 %}
5657
5658 instruct compareAndExchangeIAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5659 %{
5660 predicate(needs_acquiring_load_reserved(n));
5661
5662 match(Set res (CompareAndExchangeI mem (Binary oldval newval)));
5663
5664 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST);
5665
5666 effect(TEMP_DEF res);
5667
5668 format %{
5669 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeIAcq"
5670 %}
5671
5672 ins_encode %{
5673 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
5674 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
5675 %}
5676
5677 ins_pipe(pipe_slow);
5678 %}
5679
5680 instruct compareAndExchangeLAcq(iRegLNoSp res, indirect mem, iRegL oldval, iRegL newval)
5681 %{
5682 predicate(needs_acquiring_load_reserved(n));
5683
5684 match(Set res (CompareAndExchangeL mem (Binary oldval newval)));
5685
5686 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST);
5687
5688 effect(TEMP_DEF res);
5689
5690 format %{
5691 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (long, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeLAcq"
5692 %}
5693
5694 ins_encode %{
5695 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5696 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
5697 %}
5698
5699 ins_pipe(pipe_slow);
5700 %}
5701
5702 instruct compareAndExchangeNAcq(iRegNNoSp res, indirect mem, iRegN oldval, iRegN newval)
5703 %{
5704 predicate(needs_acquiring_load_reserved(n) && n->as_LoadStore()->barrier_data() == 0);
5705
5706 match(Set res (CompareAndExchangeN mem (Binary oldval newval)));
5707
5708 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST);
5709
5710 effect(TEMP_DEF res);
5711
5712 format %{
5713 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeNAcq"
5714 %}
5715
5716 ins_encode %{
5717 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
5718 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
5719 %}
5720
5721 ins_pipe(pipe_slow);
5722 %}
5723
5724 instruct compareAndExchangePAcq(iRegPNoSp res, indirect mem, iRegP oldval, iRegP newval)
5725 %{
5726 predicate(needs_acquiring_load_reserved(n) && (n->as_LoadStore()->barrier_data() == 0));
5727
5728 match(Set res (CompareAndExchangeP mem (Binary oldval newval)));
5729
5730 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST);
5731
5732 effect(TEMP_DEF res);
5733
5734 format %{
5735 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (ptr, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangePAcq"
5736 %}
5737
5738 ins_encode %{
5739 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5740 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
5741 %}
5742
5743 ins_pipe(pipe_slow);
5744 %}
5745
5746 instruct weakCompareAndSwapB(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5747 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5748 %{
5749 match(Set res (WeakCompareAndSwapB mem (Binary oldval newval)));
5750
5751 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 6);
5752
5753 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5754
5755 format %{
5756 "weak_cmpxchg $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5757 "# $res == 1 when success, #@weakCompareAndSwapB"
5758 %}
5759
5760 ins_encode %{
5761 __ weak_cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5762 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
5763 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5764 %}
5765
5766 ins_pipe(pipe_slow);
5767 %}
5768
5769 instruct weakCompareAndSwapS(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5770 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5771 %{
5772 match(Set res (WeakCompareAndSwapS mem (Binary oldval newval)));
5773
5774 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 7);
5775
5776 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5777
5778 format %{
5779 "weak_cmpxchg $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5780 "# $res == 1 when success, #@weakCompareAndSwapS"
5781 %}
5782
5783 ins_encode %{
5784 __ weak_cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5785 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
5786 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5787 %}
5788
5789 ins_pipe(pipe_slow);
5790 %}
5791
5792 instruct weakCompareAndSwapI(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5793 %{
5794 match(Set res (WeakCompareAndSwapI mem (Binary oldval newval)));
5795
5796 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 2);
5797
5798 format %{
5799 "weak_cmpxchg $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5800 "# $res == 1 when success, #@weakCompareAndSwapI"
5801 %}
5802
5803 ins_encode %{
5804 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
5805 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5806 %}
5807
5808 ins_pipe(pipe_slow);
5809 %}
5810
5811 instruct weakCompareAndSwapL(iRegINoSp res, indirect mem, iRegL oldval, iRegL newval)
5812 %{
5813 match(Set res (WeakCompareAndSwapL mem (Binary oldval newval)));
5814
5815 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 2);
5816
5817 format %{
5818 "weak_cmpxchg $mem, $oldval, $newval\t# (long, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5819 "# $res == 1 when success, #@weakCompareAndSwapL"
5820 %}
5821
5822 ins_encode %{
5823 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5824 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5825 %}
5826
5827 ins_pipe(pipe_slow);
5828 %}
5829
5830 instruct weakCompareAndSwapN(iRegINoSp res, indirect mem, iRegN oldval, iRegN newval)
5831 %{
5832 predicate(n->as_LoadStore()->barrier_data() == 0);
5833 match(Set res (WeakCompareAndSwapN mem (Binary oldval newval)));
5834
5835 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 4);
5836
5837 format %{
5838 "weak_cmpxchg $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5839 "# $res == 1 when success, #@weakCompareAndSwapN"
5840 %}
5841
5842 ins_encode %{
5843 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
5844 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5845 %}
5846
5847 ins_pipe(pipe_slow);
5848 %}
5849
5850 instruct weakCompareAndSwapP(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval)
5851 %{
5852 predicate(n->as_LoadStore()->barrier_data() == 0);
5853 match(Set res (WeakCompareAndSwapP mem (Binary oldval newval)));
5854
5855 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 2);
5856
5857 format %{
5858 "weak_cmpxchg $mem, $oldval, $newval\t# (ptr, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5859 "# $res == 1 when success, #@weakCompareAndSwapP"
5860 %}
5861
5862 ins_encode %{
5863 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5864 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5865 %}
5866
5867 ins_pipe(pipe_slow);
5868 %}
5869
5870 instruct weakCompareAndSwapBAcq(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5871 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5872 %{
5873 predicate(needs_acquiring_load_reserved(n));
5874
5875 match(Set res (WeakCompareAndSwapB mem (Binary oldval newval)));
5876
5877 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 6);
5878
5879 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5880
5881 format %{
5882 "weak_cmpxchg_acq $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5883 "# $res == 1 when success, #@weakCompareAndSwapBAcq"
5884 %}
5885
5886 ins_encode %{
5887 __ weak_cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5888 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
5889 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5890 %}
5891
5892 ins_pipe(pipe_slow);
5893 %}
5894
5895 instruct weakCompareAndSwapSAcq(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5896 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5897 %{
5898 predicate(needs_acquiring_load_reserved(n));
5899
5900 match(Set res (WeakCompareAndSwapS mem (Binary oldval newval)));
5901
5902 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 7);
5903
5904 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5905
5906 format %{
5907 "weak_cmpxchg_acq $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5908 "# $res == 1 when success, #@weakCompareAndSwapSAcq"
5909 %}
5910
5911 ins_encode %{
5912 __ weak_cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5913 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
5914 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5915 %}
5916
5917 ins_pipe(pipe_slow);
5918 %}
5919
5920 instruct weakCompareAndSwapIAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5921 %{
5922 predicate(needs_acquiring_load_reserved(n));
5923
5924 match(Set res (WeakCompareAndSwapI mem (Binary oldval newval)));
5925
5926 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 2);
5927
5928 format %{
5929 "weak_cmpxchg_acq $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5930 "# $res == 1 when success, #@weakCompareAndSwapIAcq"
5931 %}
5932
5933 ins_encode %{
5934 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
5935 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
5936 %}
5937
5938 ins_pipe(pipe_slow);
5939 %}
5940
5941 instruct weakCompareAndSwapLAcq(iRegINoSp res, indirect mem, iRegL oldval, iRegL newval)
5942 %{
5943 predicate(needs_acquiring_load_reserved(n));
5944
5945 match(Set res (WeakCompareAndSwapL mem (Binary oldval newval)));
5946
5947 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 2);
5948
5949 format %{
5950 "weak_cmpxchg_acq $mem, $oldval, $newval\t# (long, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5951 "# $res == 1 when success, #@weakCompareAndSwapLAcq"
5952 %}
5953
5954 ins_encode %{
5955 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5956 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
5957 %}
5958
5959 ins_pipe(pipe_slow);
5960 %}
5961
5962 instruct weakCompareAndSwapNAcq(iRegINoSp res, indirect mem, iRegN oldval, iRegN newval)
5963 %{
5964 predicate(needs_acquiring_load_reserved(n) && n->as_LoadStore()->barrier_data() == 0);
5965
5966 match(Set res (WeakCompareAndSwapN mem (Binary oldval newval)));
5967
5968 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 4);
5969
5970 format %{
5971 "weak_cmpxchg_acq $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5972 "# $res == 1 when success, #@weakCompareAndSwapNAcq"
5973 %}
5974
5975 ins_encode %{
5976 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
5977 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
5978 %}
5979
5980 ins_pipe(pipe_slow);
5981 %}
5982
5983 instruct weakCompareAndSwapPAcq(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval)
5984 %{
5985 predicate(needs_acquiring_load_reserved(n) && (n->as_LoadStore()->barrier_data() == 0));
5986
5987 match(Set res (WeakCompareAndSwapP mem (Binary oldval newval)));
5988
5989 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 2);
5990
5991 format %{
5992 "weak_cmpxchg_acq $mem, $oldval, $newval\t# (ptr, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5993 "\t# $res == 1 when success, #@weakCompareAndSwapPAcq"
5994 %}
5995
5996 ins_encode %{
5997 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5998 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
5999 %}
6000
6001 ins_pipe(pipe_slow);
6002 %}
6003
6004 instruct get_and_setI(indirect mem, iRegI newv, iRegINoSp prev)
6005 %{
6006 match(Set prev (GetAndSetI mem newv));
6007
6008 ins_cost(ALU_COST);
6009
6010 format %{ "atomic_xchgw $prev, $newv, [$mem]\t#@get_and_setI" %}
6011
6012 ins_encode %{
6013 __ atomic_xchgw($prev$$Register, $newv$$Register, as_Register($mem$$base));
6014 %}
6015
6016 ins_pipe(pipe_serial);
6017 %}
6018
6019 instruct get_and_setL(indirect mem, iRegL newv, iRegLNoSp prev)
6020 %{
6021 match(Set prev (GetAndSetL mem newv));
6022
6023 ins_cost(ALU_COST);
6024
6025 format %{ "atomic_xchg $prev, $newv, [$mem]\t#@get_and_setL" %}
6026
6027 ins_encode %{
6028 __ atomic_xchg($prev$$Register, $newv$$Register, as_Register($mem$$base));
6029 %}
6030
6031 ins_pipe(pipe_serial);
6032 %}
6033
6034 instruct get_and_setN(indirect mem, iRegN newv, iRegINoSp prev)
6035 %{
6036 predicate(n->as_LoadStore()->barrier_data() == 0);
6037
6038 match(Set prev (GetAndSetN mem newv));
6039
6040 ins_cost(ALU_COST);
6041
6042 format %{ "atomic_xchgwu $prev, $newv, [$mem]\t#@get_and_setN" %}
6043
6044 ins_encode %{
6045 __ atomic_xchgwu($prev$$Register, $newv$$Register, as_Register($mem$$base));
6046 %}
6047
6048 ins_pipe(pipe_serial);
6049 %}
6050
6051 instruct get_and_setP(indirect mem, iRegP newv, iRegPNoSp prev)
6052 %{
6053 predicate(n->as_LoadStore()->barrier_data() == 0);
6054 match(Set prev (GetAndSetP mem newv));
6055
6056 ins_cost(ALU_COST);
6057
6058 format %{ "atomic_xchg $prev, $newv, [$mem]\t#@get_and_setP" %}
6059
6060 ins_encode %{
6061 __ atomic_xchg($prev$$Register, $newv$$Register, as_Register($mem$$base));
6062 %}
6063
6064 ins_pipe(pipe_serial);
6065 %}
6066
6067 instruct get_and_setIAcq(indirect mem, iRegI newv, iRegINoSp prev)
6068 %{
6069 predicate(needs_acquiring_load_reserved(n));
6070
6071 match(Set prev (GetAndSetI mem newv));
6072
6073 ins_cost(ALU_COST);
6074
6075 format %{ "atomic_xchgw_acq $prev, $newv, [$mem]\t#@get_and_setIAcq" %}
6076
6077 ins_encode %{
6078 __ atomic_xchgalw($prev$$Register, $newv$$Register, as_Register($mem$$base));
6079 %}
6080
6081 ins_pipe(pipe_serial);
6082 %}
6083
6084 instruct get_and_setLAcq(indirect mem, iRegL newv, iRegLNoSp prev)
6085 %{
6086 predicate(needs_acquiring_load_reserved(n));
6087
6088 match(Set prev (GetAndSetL mem newv));
6089
6090 ins_cost(ALU_COST);
6091
6092 format %{ "atomic_xchg_acq $prev, $newv, [$mem]\t#@get_and_setLAcq" %}
6093
6094 ins_encode %{
6095 __ atomic_xchgal($prev$$Register, $newv$$Register, as_Register($mem$$base));
6096 %}
6097
6098 ins_pipe(pipe_serial);
6099 %}
6100
6101 instruct get_and_setNAcq(indirect mem, iRegN newv, iRegINoSp prev)
6102 %{
6103 predicate(needs_acquiring_load_reserved(n) && n->as_LoadStore()->barrier_data() == 0);
6104
6105 match(Set prev (GetAndSetN mem newv));
6106
6107 ins_cost(ALU_COST);
6108
6109 format %{ "atomic_xchgwu_acq $prev, $newv, [$mem]\t#@get_and_setNAcq" %}
6110
6111 ins_encode %{
6112 __ atomic_xchgalwu($prev$$Register, $newv$$Register, as_Register($mem$$base));
6113 %}
6114
6115 ins_pipe(pipe_serial);
6116 %}
6117
6118 instruct get_and_setPAcq(indirect mem, iRegP newv, iRegPNoSp prev)
6119 %{
6120 predicate(needs_acquiring_load_reserved(n) && (n->as_LoadStore()->barrier_data() == 0));
6121
6122 match(Set prev (GetAndSetP mem newv));
6123
6124 ins_cost(ALU_COST);
6125
6126 format %{ "atomic_xchg_acq $prev, $newv, [$mem]\t#@get_and_setPAcq" %}
6127
6128 ins_encode %{
6129 __ atomic_xchgal($prev$$Register, $newv$$Register, as_Register($mem$$base));
6130 %}
6131
6132 ins_pipe(pipe_serial);
6133 %}
6134
6135 instruct get_and_addL(indirect mem, iRegLNoSp newval, iRegL incr)
6136 %{
6137 match(Set newval (GetAndAddL mem incr));
6138
6139 ins_cost(ALU_COST);
6140
6141 format %{ "get_and_addL $newval, [$mem], $incr\t#@get_and_addL" %}
6142
6143 ins_encode %{
6144 __ atomic_add($newval$$Register, $incr$$Register, as_Register($mem$$base));
6145 %}
6146
6147 ins_pipe(pipe_serial);
6148 %}
6149
6150 instruct get_and_addL_no_res(indirect mem, Universe dummy, iRegL incr)
6151 %{
6152 predicate(n->as_LoadStore()->result_not_used());
6153
6154 match(Set dummy (GetAndAddL mem incr));
6155
6156 ins_cost(ALU_COST);
6157
6158 format %{ "get_and_addL [$mem], $incr\t#@get_and_addL_no_res" %}
6159
6160 ins_encode %{
6161 __ atomic_add(noreg, $incr$$Register, as_Register($mem$$base));
6162 %}
6163
6164 ins_pipe(pipe_serial);
6165 %}
6166
6167 instruct get_and_addLi(indirect mem, iRegLNoSp newval, immLAdd incr)
6168 %{
6169 match(Set newval (GetAndAddL mem incr));
6170
6171 ins_cost(ALU_COST);
6172
6173 format %{ "get_and_addL $newval, [$mem], $incr\t#@get_and_addLi" %}
6174
6175 ins_encode %{
6176 __ atomic_add($newval$$Register, $incr$$constant, as_Register($mem$$base));
6177 %}
6178
6179 ins_pipe(pipe_serial);
6180 %}
6181
6182 instruct get_and_addLi_no_res(indirect mem, Universe dummy, immLAdd incr)
6183 %{
6184 predicate(n->as_LoadStore()->result_not_used());
6185
6186 match(Set dummy (GetAndAddL mem incr));
6187
6188 ins_cost(ALU_COST);
6189
6190 format %{ "get_and_addL [$mem], $incr\t#@get_and_addLi_no_res" %}
6191
6192 ins_encode %{
6193 __ atomic_add(noreg, $incr$$constant, as_Register($mem$$base));
6194 %}
6195
6196 ins_pipe(pipe_serial);
6197 %}
6198
6199 instruct get_and_addI(indirect mem, iRegINoSp newval, iRegIorL2I incr)
6200 %{
6201 match(Set newval (GetAndAddI mem incr));
6202
6203 ins_cost(ALU_COST);
6204
6205 format %{ "get_and_addI $newval, [$mem], $incr\t#@get_and_addI" %}
6206
6207 ins_encode %{
6208 __ atomic_addw($newval$$Register, $incr$$Register, as_Register($mem$$base));
6209 %}
6210
6211 ins_pipe(pipe_serial);
6212 %}
6213
6214 instruct get_and_addI_no_res(indirect mem, Universe dummy, iRegIorL2I incr)
6215 %{
6216 predicate(n->as_LoadStore()->result_not_used());
6217
6218 match(Set dummy (GetAndAddI mem incr));
6219
6220 ins_cost(ALU_COST);
6221
6222 format %{ "get_and_addI [$mem], $incr\t#@get_and_addI_no_res" %}
6223
6224 ins_encode %{
6225 __ atomic_addw(noreg, $incr$$Register, as_Register($mem$$base));
6226 %}
6227
6228 ins_pipe(pipe_serial);
6229 %}
6230
6231 instruct get_and_addIi(indirect mem, iRegINoSp newval, immIAdd incr)
6232 %{
6233 match(Set newval (GetAndAddI mem incr));
6234
6235 ins_cost(ALU_COST);
6236
6237 format %{ "get_and_addI $newval, [$mem], $incr\t#@get_and_addIi" %}
6238
6239 ins_encode %{
6240 __ atomic_addw($newval$$Register, $incr$$constant, as_Register($mem$$base));
6241 %}
6242
6243 ins_pipe(pipe_serial);
6244 %}
6245
6246 instruct get_and_addIi_no_res(indirect mem, Universe dummy, immIAdd incr)
6247 %{
6248 predicate(n->as_LoadStore()->result_not_used());
6249
6250 match(Set dummy (GetAndAddI mem incr));
6251
6252 ins_cost(ALU_COST);
6253
6254 format %{ "get_and_addI [$mem], $incr\t#@get_and_addIi_no_res" %}
6255
6256 ins_encode %{
6257 __ atomic_addw(noreg, $incr$$constant, as_Register($mem$$base));
6258 %}
6259
6260 ins_pipe(pipe_serial);
6261 %}
6262
6263 instruct get_and_addLAcq(indirect mem, iRegLNoSp newval, iRegL incr)
6264 %{
6265 predicate(needs_acquiring_load_reserved(n));
6266
6267 match(Set newval (GetAndAddL mem incr));
6268
6269 ins_cost(ALU_COST);
6270
6271 format %{ "get_and_addL_acq $newval, [$mem], $incr\t#@get_and_addLAcq" %}
6272
6273 ins_encode %{
6274 __ atomic_addal($newval$$Register, $incr$$Register, as_Register($mem$$base));
6275 %}
6276
6277 ins_pipe(pipe_serial);
6278 %}
6279
6280 instruct get_and_addL_no_resAcq(indirect mem, Universe dummy, iRegL incr) %{
6281 predicate(n->as_LoadStore()->result_not_used() && needs_acquiring_load_reserved(n));
6282
6283 match(Set dummy (GetAndAddL mem incr));
6284
6285 ins_cost(ALU_COST);
6286
6287 format %{ "get_and_addL_acq [$mem], $incr\t#@get_and_addL_no_resAcq" %}
6288
6289 ins_encode %{
6290 __ atomic_addal(noreg, $incr$$Register, as_Register($mem$$base));
6291 %}
6292
6293 ins_pipe(pipe_serial);
6294 %}
6295
6296 instruct get_and_addLiAcq(indirect mem, iRegLNoSp newval, immLAdd incr)
6297 %{
6298 predicate(needs_acquiring_load_reserved(n));
6299
6300 match(Set newval (GetAndAddL mem incr));
6301
6302 ins_cost(ALU_COST);
6303
6304 format %{ "get_and_addL_acq $newval, [$mem], $incr\t#@get_and_addLiAcq" %}
6305
6306 ins_encode %{
6307 __ atomic_addal($newval$$Register, $incr$$constant, as_Register($mem$$base));
6308 %}
6309
6310 ins_pipe(pipe_serial);
6311 %}
6312
6313 instruct get_and_addLi_no_resAcq(indirect mem, Universe dummy, immLAdd incr)
6314 %{
6315 predicate(n->as_LoadStore()->result_not_used() && needs_acquiring_load_reserved(n));
6316
6317 match(Set dummy (GetAndAddL mem incr));
6318
6319 ins_cost(ALU_COST);
6320
6321 format %{ "get_and_addL_acq [$mem], $incr\t#@get_and_addLi_no_resAcq" %}
6322
6323 ins_encode %{
6324 __ atomic_addal(noreg, $incr$$constant, as_Register($mem$$base));
6325 %}
6326
6327 ins_pipe(pipe_serial);
6328 %}
6329
6330 instruct get_and_addIAcq(indirect mem, iRegINoSp newval, iRegIorL2I incr)
6331 %{
6332 predicate(needs_acquiring_load_reserved(n));
6333
6334 match(Set newval (GetAndAddI mem incr));
6335
6336 ins_cost(ALU_COST);
6337
6338 format %{ "get_and_addI_acq $newval, [$mem], $incr\t#@get_and_addIAcq" %}
6339
6340 ins_encode %{
6341 __ atomic_addalw($newval$$Register, $incr$$Register, as_Register($mem$$base));
6342 %}
6343
6344 ins_pipe(pipe_serial);
6345 %}
6346
6347 instruct get_and_addI_no_resAcq(indirect mem, Universe dummy, iRegIorL2I incr)
6348 %{
6349 predicate(n->as_LoadStore()->result_not_used() && needs_acquiring_load_reserved(n));
6350
6351 match(Set dummy (GetAndAddI mem incr));
6352
6353 ins_cost(ALU_COST);
6354
6355 format %{ "get_and_addI_acq [$mem], $incr\t#@get_and_addI_no_resAcq" %}
6356
6357 ins_encode %{
6358 __ atomic_addalw(noreg, $incr$$Register, as_Register($mem$$base));
6359 %}
6360
6361 ins_pipe(pipe_serial);
6362 %}
6363
6364 instruct get_and_addIiAcq(indirect mem, iRegINoSp newval, immIAdd incr)
6365 %{
6366 predicate(needs_acquiring_load_reserved(n));
6367
6368 match(Set newval (GetAndAddI mem incr));
6369
6370 ins_cost(ALU_COST);
6371
6372 format %{ "get_and_addI_acq $newval, [$mem], $incr\t#@get_and_addIiAcq" %}
6373
6374 ins_encode %{
6375 __ atomic_addalw($newval$$Register, $incr$$constant, as_Register($mem$$base));
6376 %}
6377
6378 ins_pipe(pipe_serial);
6379 %}
6380
6381 instruct get_and_addIi_no_resAcq(indirect mem, Universe dummy, immIAdd incr)
6382 %{
6383 predicate(n->as_LoadStore()->result_not_used() && needs_acquiring_load_reserved(n));
6384
6385 match(Set dummy (GetAndAddI mem incr));
6386
6387 ins_cost(ALU_COST);
6388
6389 format %{ "get_and_addI_acq [$mem], $incr\t#@get_and_addIi_no_resAcq" %}
6390
6391 ins_encode %{
6392 __ atomic_addalw(noreg, $incr$$constant, as_Register($mem$$base));
6393 %}
6394
6395 ins_pipe(pipe_serial);
6396 %}
6397
6398 // ============================================================================
6399 // Arithmetic Instructions
6400 //
6401
6402 // Integer Addition
6403
6404 // TODO
6405 // these currently employ operations which do not set CR and hence are
6406 // not flagged as killing CR but we would like to isolate the cases
6407 // where we want to set flags from those where we don't. need to work
6408 // out how to do that.
6409 instruct addI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6410 match(Set dst (AddI src1 src2));
6411
6412 ins_cost(ALU_COST);
6413 format %{ "addw $dst, $src1, $src2\t#@addI_reg_reg" %}
6414
6415 ins_encode %{
6416 __ addw(as_Register($dst$$reg),
6417 as_Register($src1$$reg),
6418 as_Register($src2$$reg));
6419 %}
6420
6421 ins_pipe(ialu_reg_reg);
6422 %}
6423
6424 instruct addI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immIAdd src2) %{
6425 match(Set dst (AddI src1 src2));
6426
6427 ins_cost(ALU_COST);
6428 format %{ "addiw $dst, $src1, $src2\t#@addI_reg_imm" %}
6429
6430 ins_encode %{
6431 int32_t con = (int32_t)$src2$$constant;
6432 __ addiw(as_Register($dst$$reg),
6433 as_Register($src1$$reg),
6434 $src2$$constant);
6435 %}
6436
6437 ins_pipe(ialu_reg_imm);
6438 %}
6439
6440 instruct addI_reg_imm_l2i(iRegINoSp dst, iRegL src1, immIAdd src2) %{
6441 match(Set dst (AddI (ConvL2I src1) src2));
6442
6443 ins_cost(ALU_COST);
6444 format %{ "addiw $dst, $src1, $src2\t#@addI_reg_imm_l2i" %}
6445
6446 ins_encode %{
6447 __ addiw(as_Register($dst$$reg),
6448 as_Register($src1$$reg),
6449 $src2$$constant);
6450 %}
6451
6452 ins_pipe(ialu_reg_imm);
6453 %}
6454
6455 // Pointer Addition
6456 instruct addP_reg_reg(iRegPNoSp dst, iRegP src1, iRegL src2) %{
6457 match(Set dst (AddP src1 src2));
6458
6459 ins_cost(ALU_COST);
6460 format %{ "add $dst, $src1, $src2\t# ptr, #@addP_reg_reg" %}
6461
6462 ins_encode %{
6463 __ add(as_Register($dst$$reg),
6464 as_Register($src1$$reg),
6465 as_Register($src2$$reg));
6466 %}
6467
6468 ins_pipe(ialu_reg_reg);
6469 %}
6470
6471 // If we shift more than 32 bits, we need not convert I2L.
6472 instruct lShiftL_regI_immGE32(iRegLNoSp dst, iRegI src, uimmI6_ge32 scale) %{
6473 match(Set dst (LShiftL (ConvI2L src) scale));
6474 ins_cost(ALU_COST);
6475 format %{ "slli $dst, $src, $scale & 63\t#@lShiftL_regI_immGE32" %}
6476
6477 ins_encode %{
6478 __ slli(as_Register($dst$$reg), as_Register($src$$reg), $scale$$constant & 63);
6479 %}
6480
6481 ins_pipe(ialu_reg_shift);
6482 %}
6483
6484 // Pointer Immediate Addition
6485 // n.b. this needs to be more expensive than using an indirect memory
6486 // operand
6487 instruct addP_reg_imm(iRegPNoSp dst, iRegP src1, immLAdd src2) %{
6488 match(Set dst (AddP src1 src2));
6489 ins_cost(ALU_COST);
6490 format %{ "addi $dst, $src1, $src2\t# ptr, #@addP_reg_imm" %}
6491
6492 ins_encode %{
6493 // src2 is imm, so actually call the addi
6494 __ addi(as_Register($dst$$reg),
6495 as_Register($src1$$reg),
6496 $src2$$constant);
6497 %}
6498
6499 ins_pipe(ialu_reg_imm);
6500 %}
6501
6502 // Long Addition
6503 instruct addL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
6504 match(Set dst (AddL src1 src2));
6505 ins_cost(ALU_COST);
6506 format %{ "add $dst, $src1, $src2\t#@addL_reg_reg" %}
6507
6508 ins_encode %{
6509 __ add(as_Register($dst$$reg),
6510 as_Register($src1$$reg),
6511 as_Register($src2$$reg));
6512 %}
6513
6514 ins_pipe(ialu_reg_reg);
6515 %}
6516
6517 // No constant pool entries requiredLong Immediate Addition.
6518 instruct addL_reg_imm(iRegLNoSp dst, iRegL src1, immLAdd src2) %{
6519 match(Set dst (AddL src1 src2));
6520 ins_cost(ALU_COST);
6521 format %{ "addi $dst, $src1, $src2\t#@addL_reg_imm" %}
6522
6523 ins_encode %{
6524 // src2 is imm, so actually call the addi
6525 __ addi(as_Register($dst$$reg),
6526 as_Register($src1$$reg),
6527 $src2$$constant);
6528 %}
6529
6530 ins_pipe(ialu_reg_imm);
6531 %}
6532
6533 // Integer Subtraction
6534 instruct subI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6535 match(Set dst (SubI src1 src2));
6536
6537 ins_cost(ALU_COST);
6538 format %{ "subw $dst, $src1, $src2\t#@subI_reg_reg" %}
6539
6540 ins_encode %{
6541 __ subw(as_Register($dst$$reg),
6542 as_Register($src1$$reg),
6543 as_Register($src2$$reg));
6544 %}
6545
6546 ins_pipe(ialu_reg_reg);
6547 %}
6548
6549 // Immediate Subtraction
6550 instruct subI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immISub src2) %{
6551 match(Set dst (SubI src1 src2));
6552
6553 ins_cost(ALU_COST);
6554 format %{ "addiw $dst, $src1, -$src2\t#@subI_reg_imm" %}
6555
6556 ins_encode %{
6557 // src2 is imm, so actually call the addiw
6558 __ subiw(as_Register($dst$$reg),
6559 as_Register($src1$$reg),
6560 $src2$$constant);
6561 %}
6562
6563 ins_pipe(ialu_reg_imm);
6564 %}
6565
6566 // Long Subtraction
6567 instruct subL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
6568 match(Set dst (SubL src1 src2));
6569 ins_cost(ALU_COST);
6570 format %{ "sub $dst, $src1, $src2\t#@subL_reg_reg" %}
6571
6572 ins_encode %{
6573 __ sub(as_Register($dst$$reg),
6574 as_Register($src1$$reg),
6575 as_Register($src2$$reg));
6576 %}
6577
6578 ins_pipe(ialu_reg_reg);
6579 %}
6580
6581 // No constant pool entries requiredLong Immediate Subtraction.
6582 instruct subL_reg_imm(iRegLNoSp dst, iRegL src1, immLSub src2) %{
6583 match(Set dst (SubL src1 src2));
6584 ins_cost(ALU_COST);
6585 format %{ "addi $dst, $src1, -$src2\t#@subL_reg_imm" %}
6586
6587 ins_encode %{
6588 // src2 is imm, so actually call the addi
6589 __ subi(as_Register($dst$$reg),
6590 as_Register($src1$$reg),
6591 $src2$$constant);
6592 %}
6593
6594 ins_pipe(ialu_reg_imm);
6595 %}
6596
6597 // Integer Negation (special case for sub)
6598
6599 instruct negI_reg(iRegINoSp dst, iRegIorL2I src, immI0 zero) %{
6600 match(Set dst (SubI zero src));
6601 ins_cost(ALU_COST);
6602 format %{ "subw $dst, x0, $src\t# int, #@negI_reg" %}
6603
6604 ins_encode %{
6605 // actually call the subw
6606 __ negw(as_Register($dst$$reg),
6607 as_Register($src$$reg));
6608 %}
6609
6610 ins_pipe(ialu_reg);
6611 %}
6612
6613 // Long Negation
6614
6615 instruct negL_reg(iRegLNoSp dst, iRegL src, immL0 zero) %{
6616 match(Set dst (SubL zero src));
6617 ins_cost(ALU_COST);
6618 format %{ "sub $dst, x0, $src\t# long, #@negL_reg" %}
6619
6620 ins_encode %{
6621 // actually call the sub
6622 __ neg(as_Register($dst$$reg),
6623 as_Register($src$$reg));
6624 %}
6625
6626 ins_pipe(ialu_reg);
6627 %}
6628
6629 // Integer Multiply
6630
6631 instruct mulI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6632 match(Set dst (MulI src1 src2));
6633 ins_cost(IMUL_COST);
6634 format %{ "mulw $dst, $src1, $src2\t#@mulI" %}
6635
6636 //this means 2 word multi, and no sign extend to 64 bits
6637 ins_encode %{
6638 // riscv64 mulw will sign-extension to high 32 bits in dst reg
6639 __ mulw(as_Register($dst$$reg),
6640 as_Register($src1$$reg),
6641 as_Register($src2$$reg));
6642 %}
6643
6644 ins_pipe(imul_reg_reg);
6645 %}
6646
6647 // Long Multiply
6648
6649 instruct mulL(iRegLNoSp dst, iRegL src1, iRegL src2) %{
6650 match(Set dst (MulL src1 src2));
6651 ins_cost(IMUL_COST);
6652 format %{ "mul $dst, $src1, $src2\t#@mulL" %}
6653
6654 ins_encode %{
6655 __ mul(as_Register($dst$$reg),
6656 as_Register($src1$$reg),
6657 as_Register($src2$$reg));
6658 %}
6659
6660 ins_pipe(lmul_reg_reg);
6661 %}
6662
6663 instruct mulHiL_rReg(iRegLNoSp dst, iRegL src1, iRegL src2)
6664 %{
6665 match(Set dst (MulHiL src1 src2));
6666 ins_cost(IMUL_COST);
6667 format %{ "mulh $dst, $src1, $src2\t# mulhi, #@mulHiL_rReg" %}
6668
6669 ins_encode %{
6670 __ mulh(as_Register($dst$$reg),
6671 as_Register($src1$$reg),
6672 as_Register($src2$$reg));
6673 %}
6674
6675 ins_pipe(lmul_reg_reg);
6676 %}
6677
6678 instruct umulHiL_rReg(iRegLNoSp dst, iRegL src1, iRegL src2)
6679 %{
6680 match(Set dst (UMulHiL src1 src2));
6681 ins_cost(IMUL_COST);
6682 format %{ "mulhu $dst, $src1, $src2\t# umulhi, #@umulHiL_rReg" %}
6683
6684 ins_encode %{
6685 __ mulhu(as_Register($dst$$reg),
6686 as_Register($src1$$reg),
6687 as_Register($src2$$reg));
6688 %}
6689
6690 ins_pipe(lmul_reg_reg);
6691 %}
6692
6693 // Integer Divide
6694
6695 instruct divI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6696 match(Set dst (DivI src1 src2));
6697 ins_cost(IDIVSI_COST);
6698 format %{ "divw $dst, $src1, $src2\t#@divI"%}
6699
6700 ins_encode(riscv_enc_divw(dst, src1, src2));
6701 ins_pipe(idiv_reg_reg);
6702 %}
6703
6704 instruct UdivI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6705 match(Set dst (UDivI src1 src2));
6706 ins_cost(IDIVSI_COST);
6707 format %{ "divuw $dst, $src1, $src2\t#@UdivI"%}
6708
6709 ins_encode(riscv_enc_divuw(dst, src1, src2));
6710 ins_pipe(idiv_reg_reg);
6711 %}
6712
6713 instruct signExtract(iRegINoSp dst, iRegIorL2I src1, immI_31 div1, immI_31 div2) %{
6714 match(Set dst (URShiftI (RShiftI src1 div1) div2));
6715 ins_cost(ALU_COST);
6716 format %{ "srliw $dst, $src1, $div1\t# int signExtract, #@signExtract" %}
6717
6718 ins_encode %{
6719 __ srliw(as_Register($dst$$reg), as_Register($src1$$reg), 31);
6720 %}
6721 ins_pipe(ialu_reg_shift);
6722 %}
6723
6724 // Long Divide
6725
6726 instruct divL(iRegLNoSp dst, iRegL src1, iRegL src2) %{
6727 match(Set dst (DivL src1 src2));
6728 ins_cost(IDIVDI_COST);
6729 format %{ "div $dst, $src1, $src2\t#@divL" %}
6730
6731 ins_encode(riscv_enc_div(dst, src1, src2));
6732 ins_pipe(ldiv_reg_reg);
6733 %}
6734
6735 instruct UdivL(iRegLNoSp dst, iRegL src1, iRegL src2) %{
6736 match(Set dst (UDivL src1 src2));
6737 ins_cost(IDIVDI_COST);
6738
6739 format %{ "divu $dst, $src1, $src2\t#@UdivL" %}
6740
6741 ins_encode(riscv_enc_divu(dst, src1, src2));
6742 ins_pipe(ldiv_reg_reg);
6743 %}
6744
6745 instruct signExtractL(iRegLNoSp dst, iRegL src1, immI_63 div1, immI_63 div2) %{
6746 match(Set dst (URShiftL (RShiftL src1 div1) div2));
6747 ins_cost(ALU_COST);
6748 format %{ "srli $dst, $src1, $div1\t# long signExtract, #@signExtractL" %}
6749
6750 ins_encode %{
6751 __ srli(as_Register($dst$$reg), as_Register($src1$$reg), 63);
6752 %}
6753 ins_pipe(ialu_reg_shift);
6754 %}
6755
6756 // Integer Remainder
6757
6758 instruct modI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6759 match(Set dst (ModI src1 src2));
6760 ins_cost(IDIVSI_COST);
6761 format %{ "remw $dst, $src1, $src2\t#@modI" %}
6762
6763 ins_encode(riscv_enc_modw(dst, src1, src2));
6764 ins_pipe(ialu_reg_reg);
6765 %}
6766
6767 instruct UmodI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6768 match(Set dst (UModI src1 src2));
6769 ins_cost(IDIVSI_COST);
6770 format %{ "remuw $dst, $src1, $src2\t#@UmodI" %}
6771
6772 ins_encode(riscv_enc_moduw(dst, src1, src2));
6773 ins_pipe(ialu_reg_reg);
6774 %}
6775
6776 // Long Remainder
6777
6778 instruct modL(iRegLNoSp dst, iRegL src1, iRegL src2) %{
6779 match(Set dst (ModL src1 src2));
6780 ins_cost(IDIVDI_COST);
6781 format %{ "rem $dst, $src1, $src2\t#@modL" %}
6782
6783 ins_encode(riscv_enc_mod(dst, src1, src2));
6784 ins_pipe(ialu_reg_reg);
6785 %}
6786
6787 instruct UmodL(iRegLNoSp dst, iRegL src1, iRegL src2) %{
6788 match(Set dst (UModL src1 src2));
6789 ins_cost(IDIVDI_COST);
6790 format %{ "remu $dst, $src1, $src2\t#@UmodL" %}
6791
6792 ins_encode(riscv_enc_modu(dst, src1, src2));
6793 ins_pipe(ialu_reg_reg);
6794 %}
6795
6796 // Integer Shifts
6797
6798 // Shift Left Register
6799 // In RV64I, only the low 5 bits of src2 are considered for the shift amount
6800 instruct lShiftI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6801 match(Set dst (LShiftI src1 src2));
6802 ins_cost(ALU_COST);
6803 format %{ "sllw $dst, $src1, $src2\t#@lShiftI_reg_reg" %}
6804
6805 ins_encode %{
6806 __ sllw(as_Register($dst$$reg),
6807 as_Register($src1$$reg),
6808 as_Register($src2$$reg));
6809 %}
6810
6811 ins_pipe(ialu_reg_reg_vshift);
6812 %}
6813
6814 // Shift Left Immediate
6815 instruct lShiftI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immI src2) %{
6816 match(Set dst (LShiftI src1 src2));
6817 ins_cost(ALU_COST);
6818 format %{ "slliw $dst, $src1, ($src2 & 0x1f)\t#@lShiftI_reg_imm" %}
6819
6820 ins_encode %{
6821 // the shift amount is encoded in the lower
6822 // 5 bits of the I-immediate field for RV32I
6823 __ slliw(as_Register($dst$$reg),
6824 as_Register($src1$$reg),
6825 (unsigned) $src2$$constant & 0x1f);
6826 %}
6827
6828 ins_pipe(ialu_reg_shift);
6829 %}
6830
6831 // Shift Right Logical Register
6832 // In RV64I, only the low 5 bits of src2 are considered for the shift amount
6833 instruct urShiftI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6834 match(Set dst (URShiftI src1 src2));
6835 ins_cost(ALU_COST);
6836 format %{ "srlw $dst, $src1, $src2\t#@urShiftI_reg_reg" %}
6837
6838 ins_encode %{
6839 __ srlw(as_Register($dst$$reg),
6840 as_Register($src1$$reg),
6841 as_Register($src2$$reg));
6842 %}
6843
6844 ins_pipe(ialu_reg_reg_vshift);
6845 %}
6846
6847 // Shift Right Logical Immediate
6848 instruct urShiftI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immI src2) %{
6849 match(Set dst (URShiftI src1 src2));
6850 ins_cost(ALU_COST);
6851 format %{ "srliw $dst, $src1, ($src2 & 0x1f)\t#@urShiftI_reg_imm" %}
6852
6853 ins_encode %{
6854 // the shift amount is encoded in the lower
6855 // 6 bits of the I-immediate field for RV64I
6856 __ srliw(as_Register($dst$$reg),
6857 as_Register($src1$$reg),
6858 (unsigned) $src2$$constant & 0x1f);
6859 %}
6860
6861 ins_pipe(ialu_reg_shift);
6862 %}
6863
6864 // Shift Right Arithmetic Register
6865 // In RV64I, only the low 5 bits of src2 are considered for the shift amount
6866 instruct rShiftI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6867 match(Set dst (RShiftI src1 src2));
6868 ins_cost(ALU_COST);
6869 format %{ "sraw $dst, $src1, $src2\t#@rShiftI_reg_reg" %}
6870
6871 ins_encode %{
6872 // riscv will sign-ext dst high 32 bits
6873 __ sraw(as_Register($dst$$reg),
6874 as_Register($src1$$reg),
6875 as_Register($src2$$reg));
6876 %}
6877
6878 ins_pipe(ialu_reg_reg_vshift);
6879 %}
6880
6881 // Shift Right Arithmetic Immediate
6882 instruct rShiftI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immI src2) %{
6883 match(Set dst (RShiftI src1 src2));
6884 ins_cost(ALU_COST);
6885 format %{ "sraiw $dst, $src1, ($src2 & 0x1f)\t#@rShiftI_reg_imm" %}
6886
6887 ins_encode %{
6888 // riscv will sign-ext dst high 32 bits
6889 __ sraiw(as_Register($dst$$reg),
6890 as_Register($src1$$reg),
6891 (unsigned) $src2$$constant & 0x1f);
6892 %}
6893
6894 ins_pipe(ialu_reg_shift);
6895 %}
6896
6897 // Long Shifts
6898
6899 // Shift Left Register
6900 // In RV64I, only the low 6 bits of src2 are considered for the shift amount
6901 instruct lShiftL_reg_reg(iRegLNoSp dst, iRegL src1, iRegIorL2I src2) %{
6902 match(Set dst (LShiftL src1 src2));
6903
6904 ins_cost(ALU_COST);
6905 format %{ "sll $dst, $src1, $src2\t#@lShiftL_reg_reg" %}
6906
6907 ins_encode %{
6908 __ sll(as_Register($dst$$reg),
6909 as_Register($src1$$reg),
6910 as_Register($src2$$reg));
6911 %}
6912
6913 ins_pipe(ialu_reg_reg_vshift);
6914 %}
6915
6916 // Shift Left Immediate
6917 instruct lShiftL_reg_imm(iRegLNoSp dst, iRegL src1, immI src2) %{
6918 match(Set dst (LShiftL src1 src2));
6919
6920 ins_cost(ALU_COST);
6921 format %{ "slli $dst, $src1, ($src2 & 0x3f)\t#@lShiftL_reg_imm" %}
6922
6923 ins_encode %{
6924 // the shift amount is encoded in the lower
6925 // 6 bits of the I-immediate field for RV64I
6926 __ slli(as_Register($dst$$reg),
6927 as_Register($src1$$reg),
6928 (unsigned) $src2$$constant & 0x3f);
6929 %}
6930
6931 ins_pipe(ialu_reg_shift);
6932 %}
6933
6934 // Shift Right Logical Register
6935 // In RV64I, only the low 6 bits of src2 are considered for the shift amount
6936 instruct urShiftL_reg_reg(iRegLNoSp dst, iRegL src1, iRegIorL2I src2) %{
6937 match(Set dst (URShiftL src1 src2));
6938
6939 ins_cost(ALU_COST);
6940 format %{ "srl $dst, $src1, $src2\t#@urShiftL_reg_reg" %}
6941
6942 ins_encode %{
6943 __ srl(as_Register($dst$$reg),
6944 as_Register($src1$$reg),
6945 as_Register($src2$$reg));
6946 %}
6947
6948 ins_pipe(ialu_reg_reg_vshift);
6949 %}
6950
6951 // Shift Right Logical Immediate
6952 instruct urShiftL_reg_imm(iRegLNoSp dst, iRegL src1, immI src2) %{
6953 match(Set dst (URShiftL src1 src2));
6954
6955 ins_cost(ALU_COST);
6956 format %{ "srli $dst, $src1, ($src2 & 0x3f)\t#@urShiftL_reg_imm" %}
6957
6958 ins_encode %{
6959 // the shift amount is encoded in the lower
6960 // 6 bits of the I-immediate field for RV64I
6961 __ srli(as_Register($dst$$reg),
6962 as_Register($src1$$reg),
6963 (unsigned) $src2$$constant & 0x3f);
6964 %}
6965
6966 ins_pipe(ialu_reg_shift);
6967 %}
6968
6969 // A special-case pattern for card table stores.
6970 instruct urShiftP_reg_imm(iRegLNoSp dst, iRegP src1, immI src2) %{
6971 match(Set dst (URShiftL (CastP2X src1) src2));
6972
6973 ins_cost(ALU_COST);
6974 format %{ "srli $dst, p2x($src1), ($src2 & 0x3f)\t#@urShiftP_reg_imm" %}
6975
6976 ins_encode %{
6977 // the shift amount is encoded in the lower
6978 // 6 bits of the I-immediate field for RV64I
6979 __ srli(as_Register($dst$$reg),
6980 as_Register($src1$$reg),
6981 (unsigned) $src2$$constant & 0x3f);
6982 %}
6983
6984 ins_pipe(ialu_reg_shift);
6985 %}
6986
6987 // Shift Right Arithmetic Register
6988 // In RV64I, only the low 6 bits of src2 are considered for the shift amount
6989 instruct rShiftL_reg_reg(iRegLNoSp dst, iRegL src1, iRegIorL2I src2) %{
6990 match(Set dst (RShiftL src1 src2));
6991
6992 ins_cost(ALU_COST);
6993 format %{ "sra $dst, $src1, $src2\t#@rShiftL_reg_reg" %}
6994
6995 ins_encode %{
6996 __ sra(as_Register($dst$$reg),
6997 as_Register($src1$$reg),
6998 as_Register($src2$$reg));
6999 %}
7000
7001 ins_pipe(ialu_reg_reg_vshift);
7002 %}
7003
7004 // Shift Right Arithmetic Immediate
7005 instruct rShiftL_reg_imm(iRegLNoSp dst, iRegL src1, immI src2) %{
7006 match(Set dst (RShiftL src1 src2));
7007
7008 ins_cost(ALU_COST);
7009 format %{ "srai $dst, $src1, ($src2 & 0x3f)\t#@rShiftL_reg_imm" %}
7010
7011 ins_encode %{
7012 // the shift amount is encoded in the lower
7013 // 6 bits of the I-immediate field for RV64I
7014 __ srai(as_Register($dst$$reg),
7015 as_Register($src1$$reg),
7016 (unsigned) $src2$$constant & 0x3f);
7017 %}
7018
7019 ins_pipe(ialu_reg_shift);
7020 %}
7021
7022 instruct regI_not_reg(iRegINoSp dst, iRegI src1, immI_M1 m1) %{
7023 match(Set dst (XorI src1 m1));
7024 ins_cost(ALU_COST);
7025 format %{ "xori $dst, $src1, -1\t#@regI_not_reg" %}
7026
7027 ins_encode %{
7028 __ xori(as_Register($dst$$reg), as_Register($src1$$reg), -1);
7029 %}
7030
7031 ins_pipe(ialu_reg_imm);
7032 %}
7033
7034 instruct regL_not_reg(iRegLNoSp dst, iRegL src1, immL_M1 m1) %{
7035 match(Set dst (XorL src1 m1));
7036 ins_cost(ALU_COST);
7037 format %{ "xori $dst, $src1, -1\t#@regL_not_reg" %}
7038
7039 ins_encode %{
7040 __ xori(as_Register($dst$$reg), as_Register($src1$$reg), -1);
7041 %}
7042
7043 ins_pipe(ialu_reg_imm);
7044 %}
7045
7046
7047 // ============================================================================
7048 // Floating Point Arithmetic Instructions
7049
7050 instruct addF_reg_reg(fRegF dst, fRegF src1, fRegF src2) %{
7051 match(Set dst (AddF src1 src2));
7052
7053 ins_cost(DEFAULT_COST * 5);
7054 format %{ "fadd.s $dst, $src1, $src2\t#@addF_reg_reg" %}
7055
7056 ins_encode %{
7057 __ fadd_s(as_FloatRegister($dst$$reg),
7058 as_FloatRegister($src1$$reg),
7059 as_FloatRegister($src2$$reg));
7060 %}
7061
7062 ins_pipe(fp_dop_reg_reg_s);
7063 %}
7064
7065 instruct addD_reg_reg(fRegD dst, fRegD src1, fRegD src2) %{
7066 match(Set dst (AddD src1 src2));
7067
7068 ins_cost(DEFAULT_COST * 5);
7069 format %{ "fadd.d $dst, $src1, $src2\t#@addD_reg_reg" %}
7070
7071 ins_encode %{
7072 __ fadd_d(as_FloatRegister($dst$$reg),
7073 as_FloatRegister($src1$$reg),
7074 as_FloatRegister($src2$$reg));
7075 %}
7076
7077 ins_pipe(fp_dop_reg_reg_d);
7078 %}
7079
7080 instruct subF_reg_reg(fRegF dst, fRegF src1, fRegF src2) %{
7081 match(Set dst (SubF src1 src2));
7082
7083 ins_cost(DEFAULT_COST * 5);
7084 format %{ "fsub.s $dst, $src1, $src2\t#@subF_reg_reg" %}
7085
7086 ins_encode %{
7087 __ fsub_s(as_FloatRegister($dst$$reg),
7088 as_FloatRegister($src1$$reg),
7089 as_FloatRegister($src2$$reg));
7090 %}
7091
7092 ins_pipe(fp_dop_reg_reg_s);
7093 %}
7094
7095 instruct subD_reg_reg(fRegD dst, fRegD src1, fRegD src2) %{
7096 match(Set dst (SubD src1 src2));
7097
7098 ins_cost(DEFAULT_COST * 5);
7099 format %{ "fsub.d $dst, $src1, $src2\t#@subD_reg_reg" %}
7100
7101 ins_encode %{
7102 __ fsub_d(as_FloatRegister($dst$$reg),
7103 as_FloatRegister($src1$$reg),
7104 as_FloatRegister($src2$$reg));
7105 %}
7106
7107 ins_pipe(fp_dop_reg_reg_d);
7108 %}
7109
7110 instruct mulF_reg_reg(fRegF dst, fRegF src1, fRegF src2) %{
7111 match(Set dst (MulF src1 src2));
7112
7113 ins_cost(FMUL_SINGLE_COST);
7114 format %{ "fmul.s $dst, $src1, $src2\t#@mulF_reg_reg" %}
7115
7116 ins_encode %{
7117 __ fmul_s(as_FloatRegister($dst$$reg),
7118 as_FloatRegister($src1$$reg),
7119 as_FloatRegister($src2$$reg));
7120 %}
7121
7122 ins_pipe(fp_dop_reg_reg_s);
7123 %}
7124
7125 instruct mulD_reg_reg(fRegD dst, fRegD src1, fRegD src2) %{
7126 match(Set dst (MulD src1 src2));
7127
7128 ins_cost(FMUL_DOUBLE_COST);
7129 format %{ "fmul.d $dst, $src1, $src2\t#@mulD_reg_reg" %}
7130
7131 ins_encode %{
7132 __ fmul_d(as_FloatRegister($dst$$reg),
7133 as_FloatRegister($src1$$reg),
7134 as_FloatRegister($src2$$reg));
7135 %}
7136
7137 ins_pipe(fp_dop_reg_reg_d);
7138 %}
7139
7140 // src1 * src2 + src3
7141 instruct maddF_reg_reg(fRegF dst, fRegF src1, fRegF src2, fRegF src3) %{
7142 match(Set dst (FmaF src3 (Binary src1 src2)));
7143
7144 ins_cost(FMUL_SINGLE_COST);
7145 format %{ "fmadd.s $dst, $src1, $src2, $src3\t#@maddF_reg_reg" %}
7146
7147 ins_encode %{
7148 assert(UseFMA, "Needs FMA instructions support.");
7149 __ fmadd_s(as_FloatRegister($dst$$reg),
7150 as_FloatRegister($src1$$reg),
7151 as_FloatRegister($src2$$reg),
7152 as_FloatRegister($src3$$reg));
7153 %}
7154
7155 ins_pipe(pipe_class_default);
7156 %}
7157
7158 // src1 * src2 + src3
7159 instruct maddD_reg_reg(fRegD dst, fRegD src1, fRegD src2, fRegD src3) %{
7160 match(Set dst (FmaD src3 (Binary src1 src2)));
7161
7162 ins_cost(FMUL_DOUBLE_COST);
7163 format %{ "fmadd.d $dst, $src1, $src2, $src3\t#@maddD_reg_reg" %}
7164
7165 ins_encode %{
7166 assert(UseFMA, "Needs FMA instructions support.");
7167 __ fmadd_d(as_FloatRegister($dst$$reg),
7168 as_FloatRegister($src1$$reg),
7169 as_FloatRegister($src2$$reg),
7170 as_FloatRegister($src3$$reg));
7171 %}
7172
7173 ins_pipe(pipe_class_default);
7174 %}
7175
7176 // src1 * src2 - src3
7177 instruct msubF_reg_reg(fRegF dst, fRegF src1, fRegF src2, fRegF src3) %{
7178 match(Set dst (FmaF (NegF src3) (Binary src1 src2)));
7179
7180 ins_cost(FMUL_SINGLE_COST);
7181 format %{ "fmsub.s $dst, $src1, $src2, $src3\t#@msubF_reg_reg" %}
7182
7183 ins_encode %{
7184 assert(UseFMA, "Needs FMA instructions support.");
7185 __ fmsub_s(as_FloatRegister($dst$$reg),
7186 as_FloatRegister($src1$$reg),
7187 as_FloatRegister($src2$$reg),
7188 as_FloatRegister($src3$$reg));
7189 %}
7190
7191 ins_pipe(pipe_class_default);
7192 %}
7193
7194 // src1 * src2 - src3
7195 instruct msubD_reg_reg(fRegD dst, fRegD src1, fRegD src2, fRegD src3) %{
7196 match(Set dst (FmaD (NegD src3) (Binary src1 src2)));
7197
7198 ins_cost(FMUL_DOUBLE_COST);
7199 format %{ "fmsub.d $dst, $src1, $src2, $src3\t#@msubD_reg_reg" %}
7200
7201 ins_encode %{
7202 assert(UseFMA, "Needs FMA instructions support.");
7203 __ fmsub_d(as_FloatRegister($dst$$reg),
7204 as_FloatRegister($src1$$reg),
7205 as_FloatRegister($src2$$reg),
7206 as_FloatRegister($src3$$reg));
7207 %}
7208
7209 ins_pipe(pipe_class_default);
7210 %}
7211
7212 // src1 * (-src2) + src3
7213 // "(-src1) * src2 + src3" has been idealized to "src2 * (-src1) + src3"
7214 instruct nmsubF_reg_reg(fRegF dst, fRegF src1, fRegF src2, fRegF src3) %{
7215 match(Set dst (FmaF src3 (Binary src1 (NegF src2))));
7216
7217 ins_cost(FMUL_SINGLE_COST);
7218 format %{ "fnmsub.s $dst, $src1, $src2, $src3\t#@nmsubF_reg_reg" %}
7219
7220 ins_encode %{
7221 assert(UseFMA, "Needs FMA instructions support.");
7222 __ fnmsub_s(as_FloatRegister($dst$$reg),
7223 as_FloatRegister($src1$$reg),
7224 as_FloatRegister($src2$$reg),
7225 as_FloatRegister($src3$$reg));
7226 %}
7227
7228 ins_pipe(pipe_class_default);
7229 %}
7230
7231 // src1 * (-src2) + src3
7232 // "(-src1) * src2 + src3" has been idealized to "src2 * (-src1) + src3"
7233 instruct nmsubD_reg_reg(fRegD dst, fRegD src1, fRegD src2, fRegD src3) %{
7234 match(Set dst (FmaD src3 (Binary src1 (NegD src2))));
7235
7236 ins_cost(FMUL_DOUBLE_COST);
7237 format %{ "fnmsub.d $dst, $src1, $src2, $src3\t#@nmsubD_reg_reg" %}
7238
7239 ins_encode %{
7240 assert(UseFMA, "Needs FMA instructions support.");
7241 __ fnmsub_d(as_FloatRegister($dst$$reg),
7242 as_FloatRegister($src1$$reg),
7243 as_FloatRegister($src2$$reg),
7244 as_FloatRegister($src3$$reg));
7245 %}
7246
7247 ins_pipe(pipe_class_default);
7248 %}
7249
7250 // src1 * (-src2) - src3
7251 // "(-src1) * src2 - src3" has been idealized to "src2 * (-src1) - src3"
7252 instruct nmaddF_reg_reg(fRegF dst, fRegF src1, fRegF src2, fRegF src3) %{
7253 match(Set dst (FmaF (NegF src3) (Binary src1 (NegF src2))));
7254
7255 ins_cost(FMUL_SINGLE_COST);
7256 format %{ "fnmadd.s $dst, $src1, $src2, $src3\t#@nmaddF_reg_reg" %}
7257
7258 ins_encode %{
7259 assert(UseFMA, "Needs FMA instructions support.");
7260 __ fnmadd_s(as_FloatRegister($dst$$reg),
7261 as_FloatRegister($src1$$reg),
7262 as_FloatRegister($src2$$reg),
7263 as_FloatRegister($src3$$reg));
7264 %}
7265
7266 ins_pipe(pipe_class_default);
7267 %}
7268
7269 // src1 * (-src2) - src3
7270 // "(-src1) * src2 - src3" has been idealized to "src2 * (-src1) - src3"
7271 instruct nmaddD_reg_reg(fRegD dst, fRegD src1, fRegD src2, fRegD src3) %{
7272 match(Set dst (FmaD (NegD src3) (Binary src1 (NegD src2))));
7273
7274 ins_cost(FMUL_DOUBLE_COST);
7275 format %{ "fnmadd.d $dst, $src1, $src2, $src3\t#@nmaddD_reg_reg" %}
7276
7277 ins_encode %{
7278 assert(UseFMA, "Needs FMA instructions support.");
7279 __ fnmadd_d(as_FloatRegister($dst$$reg),
7280 as_FloatRegister($src1$$reg),
7281 as_FloatRegister($src2$$reg),
7282 as_FloatRegister($src3$$reg));
7283 %}
7284
7285 ins_pipe(pipe_class_default);
7286 %}
7287
7288 // Math.max(FF)F
7289 instruct maxF_reg_reg(fRegF dst, fRegF src1, fRegF src2, rFlagsReg cr) %{
7290 match(Set dst (MaxF src1 src2));
7291 effect(TEMP_DEF dst, KILL cr);
7292
7293 format %{ "maxF $dst, $src1, $src2" %}
7294
7295 ins_encode %{
7296 __ minmax_fp(as_FloatRegister($dst$$reg),
7297 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg),
7298 false /* is_double */, false /* is_min */);
7299 %}
7300
7301 ins_pipe(pipe_class_default);
7302 %}
7303
7304 // Math.min(FF)F
7305 instruct minF_reg_reg(fRegF dst, fRegF src1, fRegF src2, rFlagsReg cr) %{
7306 match(Set dst (MinF src1 src2));
7307 effect(TEMP_DEF dst, KILL cr);
7308
7309 format %{ "minF $dst, $src1, $src2" %}
7310
7311 ins_encode %{
7312 __ minmax_fp(as_FloatRegister($dst$$reg),
7313 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg),
7314 false /* is_double */, true /* is_min */);
7315 %}
7316
7317 ins_pipe(pipe_class_default);
7318 %}
7319
7320 // Math.max(DD)D
7321 instruct maxD_reg_reg(fRegD dst, fRegD src1, fRegD src2, rFlagsReg cr) %{
7322 match(Set dst (MaxD src1 src2));
7323 effect(TEMP_DEF dst, KILL cr);
7324
7325 format %{ "maxD $dst, $src1, $src2" %}
7326
7327 ins_encode %{
7328 __ minmax_fp(as_FloatRegister($dst$$reg),
7329 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg),
7330 true /* is_double */, false /* is_min */);
7331 %}
7332
7333 ins_pipe(pipe_class_default);
7334 %}
7335
7336 // Math.min(DD)D
7337 instruct minD_reg_reg(fRegD dst, fRegD src1, fRegD src2, rFlagsReg cr) %{
7338 match(Set dst (MinD src1 src2));
7339 effect(TEMP_DEF dst, KILL cr);
7340
7341 format %{ "minD $dst, $src1, $src2" %}
7342
7343 ins_encode %{
7344 __ minmax_fp(as_FloatRegister($dst$$reg),
7345 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg),
7346 true /* is_double */, true /* is_min */);
7347 %}
7348
7349 ins_pipe(pipe_class_default);
7350 %}
7351
7352 // Float.isInfinite
7353 instruct isInfiniteF_reg_reg(iRegINoSp dst, fRegF src)
7354 %{
7355 match(Set dst (IsInfiniteF src));
7356
7357 format %{ "isInfinite $dst, $src" %}
7358 ins_encode %{
7359 __ fclass_s(as_Register($dst$$reg), as_FloatRegister($src$$reg));
7360 __ andi(as_Register($dst$$reg), as_Register($dst$$reg), Assembler::FClassBits::inf);
7361 __ slt(as_Register($dst$$reg), zr, as_Register($dst$$reg));
7362 %}
7363
7364 ins_pipe(pipe_class_default);
7365 %}
7366
7367 // Double.isInfinite
7368 instruct isInfiniteD_reg_reg(iRegINoSp dst, fRegD src)
7369 %{
7370 match(Set dst (IsInfiniteD src));
7371
7372 format %{ "isInfinite $dst, $src" %}
7373 ins_encode %{
7374 __ fclass_d(as_Register($dst$$reg), as_FloatRegister($src$$reg));
7375 __ andi(as_Register($dst$$reg), as_Register($dst$$reg), Assembler::FClassBits::inf);
7376 __ slt(as_Register($dst$$reg), zr, as_Register($dst$$reg));
7377 %}
7378
7379 ins_pipe(pipe_class_default);
7380 %}
7381
7382 // Float.isFinite
7383 instruct isFiniteF_reg_reg(iRegINoSp dst, fRegF src)
7384 %{
7385 match(Set dst (IsFiniteF src));
7386
7387 format %{ "isFinite $dst, $src" %}
7388 ins_encode %{
7389 __ fclass_s(as_Register($dst$$reg), as_FloatRegister($src$$reg));
7390 __ andi(as_Register($dst$$reg), as_Register($dst$$reg), Assembler::FClassBits::finite);
7391 __ slt(as_Register($dst$$reg), zr, as_Register($dst$$reg));
7392 %}
7393
7394 ins_pipe(pipe_class_default);
7395 %}
7396
7397 // Double.isFinite
7398 instruct isFiniteD_reg_reg(iRegINoSp dst, fRegD src)
7399 %{
7400 match(Set dst (IsFiniteD src));
7401
7402 format %{ "isFinite $dst, $src" %}
7403 ins_encode %{
7404 __ fclass_d(as_Register($dst$$reg), as_FloatRegister($src$$reg));
7405 __ andi(as_Register($dst$$reg), as_Register($dst$$reg), Assembler::FClassBits::finite);
7406 __ slt(as_Register($dst$$reg), zr, as_Register($dst$$reg));
7407 %}
7408
7409 ins_pipe(pipe_class_default);
7410 %}
7411
7412 instruct divF_reg_reg(fRegF dst, fRegF src1, fRegF src2) %{
7413 match(Set dst (DivF src1 src2));
7414
7415 ins_cost(FDIV_COST);
7416 format %{ "fdiv.s $dst, $src1, $src2\t#@divF_reg_reg" %}
7417
7418 ins_encode %{
7419 __ fdiv_s(as_FloatRegister($dst$$reg),
7420 as_FloatRegister($src1$$reg),
7421 as_FloatRegister($src2$$reg));
7422 %}
7423
7424 ins_pipe(fp_div_s);
7425 %}
7426
7427 instruct divD_reg_reg(fRegD dst, fRegD src1, fRegD src2) %{
7428 match(Set dst (DivD src1 src2));
7429
7430 ins_cost(FDIV_COST);
7431 format %{ "fdiv.d $dst, $src1, $src2\t#@divD_reg_reg" %}
7432
7433 ins_encode %{
7434 __ fdiv_d(as_FloatRegister($dst$$reg),
7435 as_FloatRegister($src1$$reg),
7436 as_FloatRegister($src2$$reg));
7437 %}
7438
7439 ins_pipe(fp_div_d);
7440 %}
7441
7442 instruct negF_reg_reg(fRegF dst, fRegF src) %{
7443 match(Set dst (NegF src));
7444
7445 ins_cost(XFER_COST);
7446 format %{ "fsgnjn.s $dst, $src, $src\t#@negF_reg_reg" %}
7447
7448 ins_encode %{
7449 __ fneg_s(as_FloatRegister($dst$$reg),
7450 as_FloatRegister($src$$reg));
7451 %}
7452
7453 ins_pipe(fp_uop_s);
7454 %}
7455
7456 instruct negD_reg_reg(fRegD dst, fRegD src) %{
7457 match(Set dst (NegD src));
7458
7459 ins_cost(XFER_COST);
7460 format %{ "fsgnjn.d $dst, $src, $src\t#@negD_reg_reg" %}
7461
7462 ins_encode %{
7463 __ fneg_d(as_FloatRegister($dst$$reg),
7464 as_FloatRegister($src$$reg));
7465 %}
7466
7467 ins_pipe(fp_uop_d);
7468 %}
7469
7470 instruct absI_reg(iRegINoSp dst, iRegIorL2I src) %{
7471 match(Set dst (AbsI src));
7472
7473 ins_cost(ALU_COST * 3);
7474 format %{
7475 "sraiw t0, $src, 0x1f\n\t"
7476 "addw $dst, $src, t0\n\t"
7477 "xorr $dst, $dst, t0\t#@absI_reg"
7478 %}
7479
7480 ins_encode %{
7481 __ sraiw(t0, as_Register($src$$reg), 0x1f);
7482 __ addw(as_Register($dst$$reg), as_Register($src$$reg), t0);
7483 __ xorr(as_Register($dst$$reg), as_Register($dst$$reg), t0);
7484 %}
7485
7486 ins_pipe(pipe_class_default);
7487 %}
7488
7489 instruct absL_reg(iRegLNoSp dst, iRegL src) %{
7490 match(Set dst (AbsL src));
7491
7492 ins_cost(ALU_COST * 3);
7493 format %{
7494 "srai t0, $src, 0x3f\n\t"
7495 "add $dst, $src, t0\n\t"
7496 "xorr $dst, $dst, t0\t#@absL_reg"
7497 %}
7498
7499 ins_encode %{
7500 __ srai(t0, as_Register($src$$reg), 0x3f);
7501 __ add(as_Register($dst$$reg), as_Register($src$$reg), t0);
7502 __ xorr(as_Register($dst$$reg), as_Register($dst$$reg), t0);
7503 %}
7504
7505 ins_pipe(pipe_class_default);
7506 %}
7507
7508 instruct absF_reg(fRegF dst, fRegF src) %{
7509 match(Set dst (AbsF src));
7510
7511 ins_cost(XFER_COST);
7512 format %{ "fsgnjx.s $dst, $src, $src\t#@absF_reg" %}
7513 ins_encode %{
7514 __ fabs_s(as_FloatRegister($dst$$reg),
7515 as_FloatRegister($src$$reg));
7516 %}
7517
7518 ins_pipe(fp_uop_s);
7519 %}
7520
7521 instruct absD_reg(fRegD dst, fRegD src) %{
7522 match(Set dst (AbsD src));
7523
7524 ins_cost(XFER_COST);
7525 format %{ "fsgnjx.d $dst, $src, $src\t#@absD_reg" %}
7526 ins_encode %{
7527 __ fabs_d(as_FloatRegister($dst$$reg),
7528 as_FloatRegister($src$$reg));
7529 %}
7530
7531 ins_pipe(fp_uop_d);
7532 %}
7533
7534 instruct sqrtF_reg(fRegF dst, fRegF src) %{
7535 match(Set dst (SqrtF src));
7536
7537 ins_cost(FSQRT_COST);
7538 format %{ "fsqrt.s $dst, $src\t#@sqrtF_reg" %}
7539 ins_encode %{
7540 __ fsqrt_s(as_FloatRegister($dst$$reg),
7541 as_FloatRegister($src$$reg));
7542 %}
7543
7544 ins_pipe(fp_sqrt_s);
7545 %}
7546
7547 instruct sqrtD_reg(fRegD dst, fRegD src) %{
7548 match(Set dst (SqrtD src));
7549
7550 ins_cost(FSQRT_COST);
7551 format %{ "fsqrt.d $dst, $src\t#@sqrtD_reg" %}
7552 ins_encode %{
7553 __ fsqrt_d(as_FloatRegister($dst$$reg),
7554 as_FloatRegister($src$$reg));
7555 %}
7556
7557 ins_pipe(fp_sqrt_d);
7558 %}
7559
7560 // Round Instruction
7561 instruct roundD_reg(fRegD dst, fRegD src, immI rmode, iRegLNoSp tmp1, iRegLNoSp tmp2, iRegLNoSp tmp3) %{
7562 match(Set dst (RoundDoubleMode src rmode));
7563 ins_cost(2 * XFER_COST + BRANCH_COST);
7564 effect(TEMP_DEF dst, TEMP tmp1, TEMP tmp2, TEMP tmp3);
7565
7566 format %{ "RoundDoubleMode $src, $rmode" %}
7567 ins_encode %{
7568 __ round_double_mode(as_FloatRegister($dst$$reg),
7569 as_FloatRegister($src$$reg), $rmode$$constant, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
7570 %}
7571 ins_pipe(pipe_class_default);
7572 %}
7573
7574 // Copysign and signum intrinsics
7575
7576 instruct copySignD_reg(fRegD dst, fRegD src1, fRegD src2, immD zero) %{
7577 match(Set dst (CopySignD src1 (Binary src2 zero)));
7578 format %{ "CopySignD $dst $src1 $src2" %}
7579 ins_encode %{
7580 FloatRegister dst = as_FloatRegister($dst$$reg),
7581 src1 = as_FloatRegister($src1$$reg),
7582 src2 = as_FloatRegister($src2$$reg);
7583 __ fsgnj_d(dst, src1, src2);
7584 %}
7585 ins_pipe(fp_dop_reg_reg_d);
7586 %}
7587
7588 instruct copySignF_reg(fRegF dst, fRegF src1, fRegF src2) %{
7589 match(Set dst (CopySignF src1 src2));
7590 format %{ "CopySignF $dst $src1 $src2" %}
7591 ins_encode %{
7592 FloatRegister dst = as_FloatRegister($dst$$reg),
7593 src1 = as_FloatRegister($src1$$reg),
7594 src2 = as_FloatRegister($src2$$reg);
7595 __ fsgnj_s(dst, src1, src2);
7596 %}
7597 ins_pipe(fp_dop_reg_reg_s);
7598 %}
7599
7600 instruct signumD_reg(fRegD dst, immD zero, fRegD one) %{
7601 match(Set dst (SignumD dst (Binary zero one)));
7602 format %{ "signumD $dst, $dst" %}
7603 ins_encode %{
7604 __ signum_fp(as_FloatRegister($dst$$reg), as_FloatRegister($one$$reg), true /* is_double */);
7605 %}
7606 ins_pipe(pipe_class_default);
7607 %}
7608
7609 instruct signumF_reg(fRegF dst, immF zero, fRegF one) %{
7610 match(Set dst (SignumF dst (Binary zero one)));
7611 format %{ "signumF $dst, $dst" %}
7612 ins_encode %{
7613 __ signum_fp(as_FloatRegister($dst$$reg), as_FloatRegister($one$$reg), false /* is_double */);
7614 %}
7615 ins_pipe(pipe_class_default);
7616 %}
7617
7618 // Arithmetic Instructions End
7619
7620 // ============================================================================
7621 // Logical Instructions
7622
7623 // Register And
7624 instruct andI_reg_reg(iRegINoSp dst, iRegI src1, iRegI src2) %{
7625 match(Set dst (AndI src1 src2));
7626
7627 format %{ "andr $dst, $src1, $src2\t#@andI_reg_reg" %}
7628
7629 ins_cost(ALU_COST);
7630 ins_encode %{
7631 __ andr(as_Register($dst$$reg),
7632 as_Register($src1$$reg),
7633 as_Register($src2$$reg));
7634 %}
7635
7636 ins_pipe(ialu_reg_reg);
7637 %}
7638
7639 // Immediate And
7640 instruct andI_reg_imm(iRegINoSp dst, iRegI src1, immIAdd src2) %{
7641 match(Set dst (AndI src1 src2));
7642
7643 format %{ "andi $dst, $src1, $src2\t#@andI_reg_imm" %}
7644
7645 ins_cost(ALU_COST);
7646 ins_encode %{
7647 __ andi(as_Register($dst$$reg),
7648 as_Register($src1$$reg),
7649 (int32_t)($src2$$constant));
7650 %}
7651
7652 ins_pipe(ialu_reg_imm);
7653 %}
7654
7655 // Register Or
7656 instruct orI_reg_reg(iRegINoSp dst, iRegI src1, iRegI src2) %{
7657 match(Set dst (OrI src1 src2));
7658
7659 format %{ "orr $dst, $src1, $src2\t#@orI_reg_reg" %}
7660
7661 ins_cost(ALU_COST);
7662 ins_encode %{
7663 __ orr(as_Register($dst$$reg),
7664 as_Register($src1$$reg),
7665 as_Register($src2$$reg));
7666 %}
7667
7668 ins_pipe(ialu_reg_reg);
7669 %}
7670
7671 // Immediate Or
7672 instruct orI_reg_imm(iRegINoSp dst, iRegI src1, immIAdd src2) %{
7673 match(Set dst (OrI src1 src2));
7674
7675 format %{ "ori $dst, $src1, $src2\t#@orI_reg_imm" %}
7676
7677 ins_cost(ALU_COST);
7678 ins_encode %{
7679 __ ori(as_Register($dst$$reg),
7680 as_Register($src1$$reg),
7681 (int32_t)($src2$$constant));
7682 %}
7683
7684 ins_pipe(ialu_reg_imm);
7685 %}
7686
7687 // Register Xor
7688 instruct xorI_reg_reg(iRegINoSp dst, iRegI src1, iRegI src2) %{
7689 match(Set dst (XorI src1 src2));
7690
7691 format %{ "xorr $dst, $src1, $src2\t#@xorI_reg_reg" %}
7692
7693 ins_cost(ALU_COST);
7694 ins_encode %{
7695 __ xorr(as_Register($dst$$reg),
7696 as_Register($src1$$reg),
7697 as_Register($src2$$reg));
7698 %}
7699
7700 ins_pipe(ialu_reg_reg);
7701 %}
7702
7703 // Immediate Xor
7704 instruct xorI_reg_imm(iRegINoSp dst, iRegI src1, immIAdd src2) %{
7705 match(Set dst (XorI src1 src2));
7706
7707 format %{ "xori $dst, $src1, $src2\t#@xorI_reg_imm" %}
7708
7709 ins_cost(ALU_COST);
7710 ins_encode %{
7711 __ xori(as_Register($dst$$reg),
7712 as_Register($src1$$reg),
7713 (int32_t)($src2$$constant));
7714 %}
7715
7716 ins_pipe(ialu_reg_imm);
7717 %}
7718
7719 // Register And Long
7720 instruct andL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
7721 match(Set dst (AndL src1 src2));
7722
7723 format %{ "andr $dst, $src1, $src2\t#@andL_reg_reg" %}
7724
7725 ins_cost(ALU_COST);
7726 ins_encode %{
7727 __ andr(as_Register($dst$$reg),
7728 as_Register($src1$$reg),
7729 as_Register($src2$$reg));
7730 %}
7731
7732 ins_pipe(ialu_reg_reg);
7733 %}
7734
7735 // Immediate And Long
7736 instruct andL_reg_imm(iRegLNoSp dst, iRegL src1, immLAdd src2) %{
7737 match(Set dst (AndL src1 src2));
7738
7739 format %{ "andi $dst, $src1, $src2\t#@andL_reg_imm" %}
7740
7741 ins_cost(ALU_COST);
7742 ins_encode %{
7743 __ andi(as_Register($dst$$reg),
7744 as_Register($src1$$reg),
7745 (int32_t)($src2$$constant));
7746 %}
7747
7748 ins_pipe(ialu_reg_imm);
7749 %}
7750
7751 // Register Or Long
7752 instruct orL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
7753 match(Set dst (OrL src1 src2));
7754
7755 format %{ "orr $dst, $src1, $src2\t#@orL_reg_reg" %}
7756
7757 ins_cost(ALU_COST);
7758 ins_encode %{
7759 __ orr(as_Register($dst$$reg),
7760 as_Register($src1$$reg),
7761 as_Register($src2$$reg));
7762 %}
7763
7764 ins_pipe(ialu_reg_reg);
7765 %}
7766
7767 // Immediate Or Long
7768 instruct orL_reg_imm(iRegLNoSp dst, iRegL src1, immLAdd src2) %{
7769 match(Set dst (OrL src1 src2));
7770
7771 format %{ "ori $dst, $src1, $src2\t#@orL_reg_imm" %}
7772
7773 ins_cost(ALU_COST);
7774 ins_encode %{
7775 __ ori(as_Register($dst$$reg),
7776 as_Register($src1$$reg),
7777 (int32_t)($src2$$constant));
7778 %}
7779
7780 ins_pipe(ialu_reg_imm);
7781 %}
7782
7783 // Register Xor Long
7784 instruct xorL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
7785 match(Set dst (XorL src1 src2));
7786
7787 format %{ "xorr $dst, $src1, $src2\t#@xorL_reg_reg" %}
7788
7789 ins_cost(ALU_COST);
7790 ins_encode %{
7791 __ xorr(as_Register($dst$$reg),
7792 as_Register($src1$$reg),
7793 as_Register($src2$$reg));
7794 %}
7795
7796 ins_pipe(ialu_reg_reg);
7797 %}
7798
7799 // Immediate Xor Long
7800 instruct xorL_reg_imm(iRegLNoSp dst, iRegL src1, immLAdd src2) %{
7801 match(Set dst (XorL src1 src2));
7802
7803 ins_cost(ALU_COST);
7804 format %{ "xori $dst, $src1, $src2\t#@xorL_reg_imm" %}
7805
7806 ins_encode %{
7807 __ xori(as_Register($dst$$reg),
7808 as_Register($src1$$reg),
7809 (int32_t)($src2$$constant));
7810 %}
7811
7812 ins_pipe(ialu_reg_imm);
7813 %}
7814
7815 // ============================================================================
7816 // MemBar Instruction
7817
7818 instruct load_fence() %{
7819 match(LoadFence);
7820 ins_cost(ALU_COST);
7821
7822 format %{ "#@load_fence" %}
7823
7824 ins_encode %{
7825 __ membar(MacroAssembler::LoadLoad | MacroAssembler::LoadStore);
7826 %}
7827 ins_pipe(pipe_serial);
7828 %}
7829
7830 instruct membar_acquire() %{
7831 match(MemBarAcquire);
7832 ins_cost(ALU_COST);
7833
7834 format %{ "#@membar_acquire\n\t"
7835 "fence ir iorw" %}
7836
7837 ins_encode %{
7838 __ block_comment("membar_acquire");
7839 __ membar(MacroAssembler::LoadLoad | MacroAssembler::LoadStore);
7840 %}
7841
7842 ins_pipe(pipe_serial);
7843 %}
7844
7845 instruct membar_acquire_lock() %{
7846 match(MemBarAcquireLock);
7847 ins_cost(0);
7848
7849 format %{ "#@membar_acquire_lock (elided)" %}
7850
7851 ins_encode %{
7852 __ block_comment("membar_acquire_lock (elided)");
7853 %}
7854
7855 ins_pipe(pipe_serial);
7856 %}
7857
7858 instruct store_fence() %{
7859 match(StoreFence);
7860 ins_cost(ALU_COST);
7861
7862 format %{ "#@store_fence" %}
7863
7864 ins_encode %{
7865 __ membar(MacroAssembler::LoadStore | MacroAssembler::StoreStore);
7866 %}
7867 ins_pipe(pipe_serial);
7868 %}
7869
7870 instruct membar_release() %{
7871 match(MemBarRelease);
7872 ins_cost(ALU_COST);
7873
7874 format %{ "#@membar_release\n\t"
7875 "fence iorw ow" %}
7876
7877 ins_encode %{
7878 __ block_comment("membar_release");
7879 __ membar(MacroAssembler::LoadStore | MacroAssembler::StoreStore);
7880 %}
7881 ins_pipe(pipe_serial);
7882 %}
7883
7884 instruct membar_storestore() %{
7885 match(MemBarStoreStore);
7886 match(StoreStoreFence);
7887 ins_cost(ALU_COST);
7888
7889 format %{ "MEMBAR-store-store\t#@membar_storestore" %}
7890
7891 ins_encode %{
7892 __ membar(MacroAssembler::StoreStore);
7893 %}
7894 ins_pipe(pipe_serial);
7895 %}
7896
7897 instruct membar_release_lock() %{
7898 match(MemBarReleaseLock);
7899 ins_cost(0);
7900
7901 format %{ "#@membar_release_lock (elided)" %}
7902
7903 ins_encode %{
7904 __ block_comment("membar_release_lock (elided)");
7905 %}
7906
7907 ins_pipe(pipe_serial);
7908 %}
7909
7910 instruct membar_volatile() %{
7911 match(MemBarVolatile);
7912 ins_cost(ALU_COST);
7913
7914 format %{ "#@membar_volatile\n\t"
7915 "fence iorw iorw"%}
7916
7917 ins_encode %{
7918 __ block_comment("membar_volatile");
7919 __ membar(MacroAssembler::StoreLoad);
7920 %}
7921
7922 ins_pipe(pipe_serial);
7923 %}
7924
7925 instruct spin_wait() %{
7926 predicate(UseZihintpause);
7927 match(OnSpinWait);
7928 ins_cost(CACHE_MISS_COST);
7929
7930 format %{ "spin_wait" %}
7931
7932 ins_encode %{
7933 __ pause();
7934 %}
7935
7936 ins_pipe(pipe_serial);
7937 %}
7938
7939 // ============================================================================
7940 // Cast Instructions (Java-level type cast)
7941
7942 instruct castX2P(iRegPNoSp dst, iRegL src) %{
7943 match(Set dst (CastX2P src));
7944
7945 ins_cost(ALU_COST);
7946 format %{ "mv $dst, $src\t# long -> ptr, #@castX2P" %}
7947
7948 ins_encode %{
7949 if ($dst$$reg != $src$$reg) {
7950 __ mv(as_Register($dst$$reg), as_Register($src$$reg));
7951 }
7952 %}
7953
7954 ins_pipe(ialu_reg);
7955 %}
7956
7957 instruct castP2X(iRegLNoSp dst, iRegP src) %{
7958 match(Set dst (CastP2X src));
7959
7960 ins_cost(ALU_COST);
7961 format %{ "mv $dst, $src\t# ptr -> long, #@castP2X" %}
7962
7963 ins_encode %{
7964 if ($dst$$reg != $src$$reg) {
7965 __ mv(as_Register($dst$$reg), as_Register($src$$reg));
7966 }
7967 %}
7968
7969 ins_pipe(ialu_reg);
7970 %}
7971
7972 instruct castPP(iRegPNoSp dst)
7973 %{
7974 match(Set dst (CastPP dst));
7975 ins_cost(0);
7976
7977 size(0);
7978 format %{ "# castPP of $dst, #@castPP" %}
7979 ins_encode(/* empty encoding */);
7980 ins_pipe(pipe_class_empty);
7981 %}
7982
7983 instruct castLL(iRegL dst)
7984 %{
7985 match(Set dst (CastLL dst));
7986
7987 size(0);
7988 format %{ "# castLL of $dst, #@castLL" %}
7989 ins_encode(/* empty encoding */);
7990 ins_cost(0);
7991 ins_pipe(pipe_class_empty);
7992 %}
7993
7994 instruct castII(iRegI dst)
7995 %{
7996 match(Set dst (CastII dst));
7997
7998 size(0);
7999 format %{ "# castII of $dst, #@castII" %}
8000 ins_encode(/* empty encoding */);
8001 ins_cost(0);
8002 ins_pipe(pipe_class_empty);
8003 %}
8004
8005 instruct checkCastPP(iRegPNoSp dst)
8006 %{
8007 match(Set dst (CheckCastPP dst));
8008
8009 size(0);
8010 ins_cost(0);
8011 format %{ "# checkcastPP of $dst, #@checkCastPP" %}
8012 ins_encode(/* empty encoding */);
8013 ins_pipe(pipe_class_empty);
8014 %}
8015
8016 instruct castFF(fRegF dst)
8017 %{
8018 match(Set dst (CastFF dst));
8019
8020 size(0);
8021 format %{ "# castFF of $dst" %}
8022 ins_encode(/* empty encoding */);
8023 ins_cost(0);
8024 ins_pipe(pipe_class_empty);
8025 %}
8026
8027 instruct castDD(fRegD dst)
8028 %{
8029 match(Set dst (CastDD dst));
8030
8031 size(0);
8032 format %{ "# castDD of $dst" %}
8033 ins_encode(/* empty encoding */);
8034 ins_cost(0);
8035 ins_pipe(pipe_class_empty);
8036 %}
8037
8038 instruct castVV(vReg dst)
8039 %{
8040 match(Set dst (CastVV dst));
8041
8042 size(0);
8043 format %{ "# castVV of $dst" %}
8044 ins_encode(/* empty encoding */);
8045 ins_cost(0);
8046 ins_pipe(pipe_class_empty);
8047 %}
8048
8049 // ============================================================================
8050 // Convert Instructions
8051
8052 // int to bool
8053 instruct convI2Bool(iRegINoSp dst, iRegI src)
8054 %{
8055 match(Set dst (Conv2B src));
8056
8057 ins_cost(ALU_COST);
8058 format %{ "snez $dst, $src\t#@convI2Bool" %}
8059
8060 ins_encode %{
8061 __ snez(as_Register($dst$$reg), as_Register($src$$reg));
8062 %}
8063
8064 ins_pipe(ialu_reg);
8065 %}
8066
8067 // pointer to bool
8068 instruct convP2Bool(iRegINoSp dst, iRegP src)
8069 %{
8070 match(Set dst (Conv2B src));
8071
8072 ins_cost(ALU_COST);
8073 format %{ "snez $dst, $src\t#@convP2Bool" %}
8074
8075 ins_encode %{
8076 __ snez(as_Register($dst$$reg), as_Register($src$$reg));
8077 %}
8078
8079 ins_pipe(ialu_reg);
8080 %}
8081
8082 // int <-> long
8083
8084 instruct convI2L_reg_reg(iRegLNoSp dst, iRegIorL2I src)
8085 %{
8086 match(Set dst (ConvI2L src));
8087
8088 ins_cost(ALU_COST);
8089 format %{ "addw $dst, $src, zr\t#@convI2L_reg_reg" %}
8090 ins_encode %{
8091 __ sext(as_Register($dst$$reg), as_Register($src$$reg), 32);
8092 %}
8093 ins_pipe(ialu_reg);
8094 %}
8095
8096 instruct convL2I_reg(iRegINoSp dst, iRegL src) %{
8097 match(Set dst (ConvL2I src));
8098
8099 ins_cost(ALU_COST);
8100 format %{ "addw $dst, $src, zr\t#@convL2I_reg" %}
8101
8102 ins_encode %{
8103 __ sext(as_Register($dst$$reg), as_Register($src$$reg), 32);
8104 %}
8105
8106 ins_pipe(ialu_reg);
8107 %}
8108
8109 // int to unsigned long (Zero-extend)
8110 instruct convI2UL_reg_reg(iRegLNoSp dst, iRegIorL2I src, immL_32bits mask)
8111 %{
8112 match(Set dst (AndL (ConvI2L src) mask));
8113
8114 ins_cost(ALU_COST * 2);
8115 format %{ "zext $dst, $src, 32\t# i2ul, #@convI2UL_reg_reg" %}
8116
8117 ins_encode %{
8118 __ zext(as_Register($dst$$reg), as_Register($src$$reg), 32);
8119 %}
8120
8121 ins_pipe(ialu_reg_shift);
8122 %}
8123
8124 // float <-> double
8125
8126 instruct convF2D_reg(fRegD dst, fRegF src) %{
8127 match(Set dst (ConvF2D src));
8128
8129 ins_cost(XFER_COST);
8130 format %{ "fcvt.d.s $dst, $src\t#@convF2D_reg" %}
8131
8132 ins_encode %{
8133 __ fcvt_d_s(as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg));
8134 %}
8135
8136 ins_pipe(fp_f2d);
8137 %}
8138
8139 instruct convD2F_reg(fRegF dst, fRegD src) %{
8140 match(Set dst (ConvD2F src));
8141
8142 ins_cost(XFER_COST);
8143 format %{ "fcvt.s.d $dst, $src\t#@convD2F_reg" %}
8144
8145 ins_encode %{
8146 __ fcvt_s_d(as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg));
8147 %}
8148
8149 ins_pipe(fp_d2f);
8150 %}
8151
8152 // single <-> half precision
8153
8154 instruct convHF2F_reg_reg(fRegF dst, iRegINoSp src, iRegINoSp tmp) %{
8155 match(Set dst (ConvHF2F src));
8156 effect(TEMP tmp);
8157 format %{ "fmv.h.x $dst, $src\t# move source from $src to $dst\n\t"
8158 "fcvt.s.h $dst, $dst\t# convert half to single precision"
8159 %}
8160 ins_encode %{
8161 __ float16_to_float($dst$$FloatRegister, $src$$Register, $tmp$$Register);
8162 %}
8163 ins_pipe(pipe_slow);
8164 %}
8165
8166 instruct convF2HF_reg_reg(iRegINoSp dst, fRegF src, fRegF ftmp, iRegINoSp xtmp) %{
8167 match(Set dst (ConvF2HF src));
8168 effect(TEMP_DEF dst, TEMP ftmp, TEMP xtmp);
8169 format %{ "fcvt.h.s $ftmp, $src\t# convert single precision to half\n\t"
8170 "fmv.x.h $dst, $ftmp\t# move result from $ftmp to $dst"
8171 %}
8172 ins_encode %{
8173 __ float_to_float16($dst$$Register, $src$$FloatRegister, $ftmp$$FloatRegister, $xtmp$$Register);
8174 %}
8175 ins_pipe(pipe_slow);
8176 %}
8177
8178 // float <-> int
8179
8180 instruct convF2I_reg_reg(iRegINoSp dst, fRegF src) %{
8181 match(Set dst (ConvF2I src));
8182
8183 ins_cost(XFER_COST);
8184 format %{ "fcvt.w.s $dst, $src\t#@convF2I_reg_reg" %}
8185
8186 ins_encode %{
8187 __ fcvt_w_s_safe($dst$$Register, $src$$FloatRegister);
8188 %}
8189
8190 ins_pipe(fp_f2i);
8191 %}
8192
8193 instruct convI2F_reg_reg(fRegF dst, iRegIorL2I src) %{
8194 match(Set dst (ConvI2F src));
8195
8196 ins_cost(XFER_COST);
8197 format %{ "fcvt.s.w $dst, $src\t#@convI2F_reg_reg" %}
8198
8199 ins_encode %{
8200 __ fcvt_s_w(as_FloatRegister($dst$$reg), as_Register($src$$reg));
8201 %}
8202
8203 ins_pipe(fp_i2f);
8204 %}
8205
8206 // float <-> long
8207
8208 instruct convF2L_reg_reg(iRegLNoSp dst, fRegF src) %{
8209 match(Set dst (ConvF2L src));
8210
8211 ins_cost(XFER_COST);
8212 format %{ "fcvt.l.s $dst, $src\t#@convF2L_reg_reg" %}
8213
8214 ins_encode %{
8215 __ fcvt_l_s_safe($dst$$Register, $src$$FloatRegister);
8216 %}
8217
8218 ins_pipe(fp_f2l);
8219 %}
8220
8221 instruct convL2F_reg_reg(fRegF dst, iRegL src) %{
8222 match(Set dst (ConvL2F src));
8223
8224 ins_cost(XFER_COST);
8225 format %{ "fcvt.s.l $dst, $src\t#@convL2F_reg_reg" %}
8226
8227 ins_encode %{
8228 __ fcvt_s_l(as_FloatRegister($dst$$reg), as_Register($src$$reg));
8229 %}
8230
8231 ins_pipe(fp_l2f);
8232 %}
8233
8234 // double <-> int
8235
8236 instruct convD2I_reg_reg(iRegINoSp dst, fRegD src) %{
8237 match(Set dst (ConvD2I src));
8238
8239 ins_cost(XFER_COST);
8240 format %{ "fcvt.w.d $dst, $src\t#@convD2I_reg_reg" %}
8241
8242 ins_encode %{
8243 __ fcvt_w_d_safe($dst$$Register, $src$$FloatRegister);
8244 %}
8245
8246 ins_pipe(fp_d2i);
8247 %}
8248
8249 instruct convI2D_reg_reg(fRegD dst, iRegIorL2I src) %{
8250 match(Set dst (ConvI2D src));
8251
8252 ins_cost(XFER_COST);
8253 format %{ "fcvt.d.w $dst, $src\t#@convI2D_reg_reg" %}
8254
8255 ins_encode %{
8256 __ fcvt_d_w(as_FloatRegister($dst$$reg), as_Register($src$$reg));
8257 %}
8258
8259 ins_pipe(fp_i2d);
8260 %}
8261
8262 // double <-> long
8263
8264 instruct convD2L_reg_reg(iRegLNoSp dst, fRegD src) %{
8265 match(Set dst (ConvD2L src));
8266
8267 ins_cost(XFER_COST);
8268 format %{ "fcvt.l.d $dst, $src\t#@convD2L_reg_reg" %}
8269
8270 ins_encode %{
8271 __ fcvt_l_d_safe($dst$$Register, $src$$FloatRegister);
8272 %}
8273
8274 ins_pipe(fp_d2l);
8275 %}
8276
8277 instruct convL2D_reg_reg(fRegD dst, iRegL src) %{
8278 match(Set dst (ConvL2D src));
8279
8280 ins_cost(XFER_COST);
8281 format %{ "fcvt.d.l $dst, $src\t#@convL2D_reg_reg" %}
8282
8283 ins_encode %{
8284 __ fcvt_d_l(as_FloatRegister($dst$$reg), as_Register($src$$reg));
8285 %}
8286
8287 ins_pipe(fp_l2d);
8288 %}
8289
8290 // Convert oop into int for vectors alignment masking
8291 instruct convP2I(iRegINoSp dst, iRegP src) %{
8292 match(Set dst (ConvL2I (CastP2X src)));
8293
8294 ins_cost(ALU_COST * 2);
8295 format %{ "zext $dst, $src, 32\t# ptr -> int, #@convP2I" %}
8296
8297 ins_encode %{
8298 __ zext($dst$$Register, $src$$Register, 32);
8299 %}
8300
8301 ins_pipe(ialu_reg);
8302 %}
8303
8304 // Convert compressed oop into int for vectors alignment masking
8305 // in case of 32bit oops (heap < 4Gb).
8306 instruct convN2I(iRegINoSp dst, iRegN src)
8307 %{
8308 predicate(CompressedOops::shift() == 0);
8309 match(Set dst (ConvL2I (CastP2X (DecodeN src))));
8310
8311 ins_cost(ALU_COST);
8312 format %{ "mv $dst, $src\t# compressed ptr -> int, #@convN2I" %}
8313
8314 ins_encode %{
8315 __ mv($dst$$Register, $src$$Register);
8316 %}
8317
8318 ins_pipe(ialu_reg);
8319 %}
8320
8321 instruct round_double_reg(iRegLNoSp dst, fRegD src, fRegD ftmp) %{
8322 match(Set dst (RoundD src));
8323
8324 ins_cost(XFER_COST + BRANCH_COST);
8325 effect(TEMP ftmp);
8326 format %{ "java_round_double $dst, $src\t#@round_double_reg" %}
8327
8328 ins_encode %{
8329 __ java_round_double($dst$$Register, as_FloatRegister($src$$reg), as_FloatRegister($ftmp$$reg));
8330 %}
8331
8332 ins_pipe(pipe_slow);
8333 %}
8334
8335 instruct round_float_reg(iRegINoSp dst, fRegF src, fRegF ftmp) %{
8336 match(Set dst (RoundF src));
8337
8338 ins_cost(XFER_COST + BRANCH_COST);
8339 effect(TEMP ftmp);
8340 format %{ "java_round_float $dst, $src\t#@round_float_reg" %}
8341
8342 ins_encode %{
8343 __ java_round_float($dst$$Register, as_FloatRegister($src$$reg), as_FloatRegister($ftmp$$reg));
8344 %}
8345
8346 ins_pipe(pipe_slow);
8347 %}
8348
8349 // Convert oop pointer into compressed form
8350 instruct encodeHeapOop(iRegNNoSp dst, iRegP src) %{
8351 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
8352 match(Set dst (EncodeP src));
8353 ins_cost(ALU_COST);
8354 format %{ "encode_heap_oop $dst, $src\t#@encodeHeapOop" %}
8355 ins_encode %{
8356 Register s = $src$$Register;
8357 Register d = $dst$$Register;
8358 __ encode_heap_oop(d, s);
8359 %}
8360 ins_pipe(pipe_class_default);
8361 %}
8362
8363 instruct encodeHeapOop_not_null(iRegNNoSp dst, iRegP src) %{
8364 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
8365 match(Set dst (EncodeP src));
8366 ins_cost(ALU_COST);
8367 format %{ "encode_heap_oop_not_null $dst, $src\t#@encodeHeapOop_not_null" %}
8368 ins_encode %{
8369 __ encode_heap_oop_not_null($dst$$Register, $src$$Register);
8370 %}
8371 ins_pipe(pipe_class_default);
8372 %}
8373
8374 instruct decodeHeapOop(iRegPNoSp dst, iRegN src) %{
8375 predicate(n->bottom_type()->is_ptr()->ptr() != TypePtr::NotNull &&
8376 n->bottom_type()->is_ptr()->ptr() != TypePtr::Constant);
8377 match(Set dst (DecodeN src));
8378
8379 ins_cost(0);
8380 format %{ "decode_heap_oop $dst, $src\t#@decodeHeapOop" %}
8381 ins_encode %{
8382 Register s = $src$$Register;
8383 Register d = $dst$$Register;
8384 __ decode_heap_oop(d, s);
8385 %}
8386 ins_pipe(pipe_class_default);
8387 %}
8388
8389 instruct decodeHeapOop_not_null(iRegPNoSp dst, iRegN src) %{
8390 predicate(n->bottom_type()->is_ptr()->ptr() == TypePtr::NotNull ||
8391 n->bottom_type()->is_ptr()->ptr() == TypePtr::Constant);
8392 match(Set dst (DecodeN src));
8393
8394 ins_cost(0);
8395 format %{ "decode_heap_oop_not_null $dst, $src\t#@decodeHeapOop_not_null" %}
8396 ins_encode %{
8397 Register s = $src$$Register;
8398 Register d = $dst$$Register;
8399 __ decode_heap_oop_not_null(d, s);
8400 %}
8401 ins_pipe(pipe_class_default);
8402 %}
8403
8404 // Convert klass pointer into compressed form.
8405 instruct encodeKlass_not_null(iRegNNoSp dst, iRegP src) %{
8406 match(Set dst (EncodePKlass src));
8407
8408 ins_cost(ALU_COST);
8409 format %{ "encode_klass_not_null $dst, $src\t#@encodeKlass_not_null" %}
8410
8411 ins_encode %{
8412 Register src_reg = as_Register($src$$reg);
8413 Register dst_reg = as_Register($dst$$reg);
8414 __ encode_klass_not_null(dst_reg, src_reg, t0);
8415 %}
8416
8417 ins_pipe(pipe_class_default);
8418 %}
8419
8420 instruct decodeKlass_not_null(iRegPNoSp dst, iRegN src, iRegPNoSp tmp) %{
8421 match(Set dst (DecodeNKlass src));
8422
8423 effect(TEMP tmp);
8424
8425 ins_cost(ALU_COST);
8426 format %{ "decode_klass_not_null $dst, $src\t#@decodeKlass_not_null" %}
8427
8428 ins_encode %{
8429 Register src_reg = as_Register($src$$reg);
8430 Register dst_reg = as_Register($dst$$reg);
8431 Register tmp_reg = as_Register($tmp$$reg);
8432 __ decode_klass_not_null(dst_reg, src_reg, tmp_reg);
8433 %}
8434
8435 ins_pipe(pipe_class_default);
8436 %}
8437
8438 // stack <-> reg and reg <-> reg shuffles with no conversion
8439
8440 instruct MoveF2I_stack_reg(iRegINoSp dst, stackSlotF src) %{
8441
8442 match(Set dst (MoveF2I src));
8443
8444 effect(DEF dst, USE src);
8445
8446 ins_cost(LOAD_COST);
8447
8448 format %{ "lw $dst, $src\t#@MoveF2I_stack_reg" %}
8449
8450 ins_encode %{
8451 __ lw(as_Register($dst$$reg), Address(sp, $src$$disp));
8452 %}
8453
8454 ins_pipe(iload_reg_reg);
8455
8456 %}
8457
8458 instruct MoveI2F_stack_reg(fRegF dst, stackSlotI src) %{
8459
8460 match(Set dst (MoveI2F src));
8461
8462 effect(DEF dst, USE src);
8463
8464 ins_cost(LOAD_COST);
8465
8466 format %{ "flw $dst, $src\t#@MoveI2F_stack_reg" %}
8467
8468 ins_encode %{
8469 __ flw(as_FloatRegister($dst$$reg), Address(sp, $src$$disp));
8470 %}
8471
8472 ins_pipe(fp_load_mem_s);
8473
8474 %}
8475
8476 instruct MoveD2L_stack_reg(iRegLNoSp dst, stackSlotD src) %{
8477
8478 match(Set dst (MoveD2L src));
8479
8480 effect(DEF dst, USE src);
8481
8482 ins_cost(LOAD_COST);
8483
8484 format %{ "ld $dst, $src\t#@MoveD2L_stack_reg" %}
8485
8486 ins_encode %{
8487 __ ld(as_Register($dst$$reg), Address(sp, $src$$disp));
8488 %}
8489
8490 ins_pipe(iload_reg_reg);
8491
8492 %}
8493
8494 instruct MoveL2D_stack_reg(fRegD dst, stackSlotL src) %{
8495
8496 match(Set dst (MoveL2D src));
8497
8498 effect(DEF dst, USE src);
8499
8500 ins_cost(LOAD_COST);
8501
8502 format %{ "fld $dst, $src\t#@MoveL2D_stack_reg" %}
8503
8504 ins_encode %{
8505 __ fld(as_FloatRegister($dst$$reg), Address(sp, $src$$disp));
8506 %}
8507
8508 ins_pipe(fp_load_mem_d);
8509
8510 %}
8511
8512 instruct MoveF2I_reg_stack(stackSlotI dst, fRegF src) %{
8513
8514 match(Set dst (MoveF2I src));
8515
8516 effect(DEF dst, USE src);
8517
8518 ins_cost(STORE_COST);
8519
8520 format %{ "fsw $src, $dst\t#@MoveF2I_reg_stack" %}
8521
8522 ins_encode %{
8523 __ fsw(as_FloatRegister($src$$reg), Address(sp, $dst$$disp));
8524 %}
8525
8526 ins_pipe(fp_store_reg_s);
8527
8528 %}
8529
8530 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{
8531
8532 match(Set dst (MoveI2F src));
8533
8534 effect(DEF dst, USE src);
8535
8536 ins_cost(STORE_COST);
8537
8538 format %{ "sw $src, $dst\t#@MoveI2F_reg_stack" %}
8539
8540 ins_encode %{
8541 __ sw(as_Register($src$$reg), Address(sp, $dst$$disp));
8542 %}
8543
8544 ins_pipe(istore_reg_reg);
8545
8546 %}
8547
8548 instruct MoveD2L_reg_stack(stackSlotL dst, fRegD src) %{
8549
8550 match(Set dst (MoveD2L src));
8551
8552 effect(DEF dst, USE src);
8553
8554 ins_cost(STORE_COST);
8555
8556 format %{ "fsd $dst, $src\t#@MoveD2L_reg_stack" %}
8557
8558 ins_encode %{
8559 __ fsd(as_FloatRegister($src$$reg), Address(sp, $dst$$disp));
8560 %}
8561
8562 ins_pipe(fp_store_reg_d);
8563
8564 %}
8565
8566 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{
8567
8568 match(Set dst (MoveL2D src));
8569
8570 effect(DEF dst, USE src);
8571
8572 ins_cost(STORE_COST);
8573
8574 format %{ "sd $src, $dst\t#@MoveL2D_reg_stack" %}
8575
8576 ins_encode %{
8577 __ sd(as_Register($src$$reg), Address(sp, $dst$$disp));
8578 %}
8579
8580 ins_pipe(istore_reg_reg);
8581
8582 %}
8583
8584 instruct MoveF2I_reg_reg(iRegINoSp dst, fRegF src) %{
8585
8586 match(Set dst (MoveF2I src));
8587
8588 effect(DEF dst, USE src);
8589
8590 ins_cost(FMVX_COST);
8591
8592 format %{ "fmv.x.w $dst, $src\t#@MoveF2I_reg_reg" %}
8593
8594 ins_encode %{
8595 __ fmv_x_w(as_Register($dst$$reg), as_FloatRegister($src$$reg));
8596 %}
8597
8598 ins_pipe(fp_f2i);
8599
8600 %}
8601
8602 instruct MoveI2F_reg_reg(fRegF dst, iRegI src) %{
8603
8604 match(Set dst (MoveI2F src));
8605
8606 effect(DEF dst, USE src);
8607
8608 ins_cost(FMVX_COST);
8609
8610 format %{ "fmv.w.x $dst, $src\t#@MoveI2F_reg_reg" %}
8611
8612 ins_encode %{
8613 __ fmv_w_x(as_FloatRegister($dst$$reg), as_Register($src$$reg));
8614 %}
8615
8616 ins_pipe(fp_i2f);
8617
8618 %}
8619
8620 instruct MoveD2L_reg_reg(iRegLNoSp dst, fRegD src) %{
8621
8622 match(Set dst (MoveD2L src));
8623
8624 effect(DEF dst, USE src);
8625
8626 ins_cost(FMVX_COST);
8627
8628 format %{ "fmv.x.d $dst, $src\t#@MoveD2L_reg_reg" %}
8629
8630 ins_encode %{
8631 __ fmv_x_d(as_Register($dst$$reg), as_FloatRegister($src$$reg));
8632 %}
8633
8634 ins_pipe(fp_d2l);
8635
8636 %}
8637
8638 instruct MoveL2D_reg_reg(fRegD dst, iRegL src) %{
8639
8640 match(Set dst (MoveL2D src));
8641
8642 effect(DEF dst, USE src);
8643
8644 ins_cost(FMVX_COST);
8645
8646 format %{ "fmv.d.x $dst, $src\t#@MoveL2D_reg_reg" %}
8647
8648 ins_encode %{
8649 __ fmv_d_x(as_FloatRegister($dst$$reg), as_Register($src$$reg));
8650 %}
8651
8652 ins_pipe(fp_l2d);
8653
8654 %}
8655
8656 // ============================================================================
8657 // Compare Instructions which set the result float comparisons in dest register.
8658
8659 instruct cmpF3_reg_reg(iRegINoSp dst, fRegF op1, fRegF op2)
8660 %{
8661 match(Set dst (CmpF3 op1 op2));
8662
8663 ins_cost(XFER_COST * 2 + BRANCH_COST + ALU_COST);
8664 format %{ "flt.s $dst, $op2, $op1\t#@cmpF3_reg_reg\n\t"
8665 "bgtz $dst, done\n\t"
8666 "feq.s $dst, $op1, $op2\n\t"
8667 "addi $dst, $dst, -1\n\t"
8668 "done:"
8669 %}
8670
8671 ins_encode %{
8672 // we want -1 for unordered or less than, 0 for equal and 1 for greater than.
8673 __ float_compare(as_Register($dst$$reg), as_FloatRegister($op1$$reg),
8674 as_FloatRegister($op2$$reg), -1 /*unordered_result < 0*/);
8675 %}
8676
8677 ins_pipe(pipe_class_default);
8678 %}
8679
8680 instruct cmpD3_reg_reg(iRegINoSp dst, fRegD op1, fRegD op2)
8681 %{
8682 match(Set dst (CmpD3 op1 op2));
8683
8684 ins_cost(XFER_COST * 2 + BRANCH_COST + ALU_COST);
8685 format %{ "flt.d $dst, $op2, $op1\t#@cmpD3_reg_reg\n\t"
8686 "bgtz $dst, done\n\t"
8687 "feq.d $dst, $op1, $op2\n\t"
8688 "addi $dst, $dst, -1\n\t"
8689 "done:"
8690 %}
8691
8692 ins_encode %{
8693 // we want -1 for unordered or less than, 0 for equal and 1 for greater than.
8694 __ double_compare(as_Register($dst$$reg), as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg), -1 /*unordered_result < 0*/);
8695 %}
8696
8697 ins_pipe(pipe_class_default);
8698 %}
8699
8700 instruct cmpL3_reg_reg(iRegINoSp dst, iRegL op1, iRegL op2)
8701 %{
8702 match(Set dst (CmpL3 op1 op2));
8703
8704 ins_cost(ALU_COST * 3 + BRANCH_COST);
8705 format %{ "slt $dst, $op2, $op1\t#@cmpL3_reg_reg\n\t"
8706 "bnez $dst, done\n\t"
8707 "slt $dst, $op1, $op2\n\t"
8708 "neg $dst, $dst\n\t"
8709 "done:"
8710 %}
8711 ins_encode %{
8712 __ cmp_l2i(t0, as_Register($op1$$reg), as_Register($op2$$reg));
8713 __ mv(as_Register($dst$$reg), t0);
8714 %}
8715
8716 ins_pipe(pipe_class_default);
8717 %}
8718
8719 instruct cmpUL3_reg_reg(iRegINoSp dst, iRegL op1, iRegL op2)
8720 %{
8721 match(Set dst (CmpUL3 op1 op2));
8722
8723 ins_cost(ALU_COST * 3 + BRANCH_COST);
8724 format %{ "sltu $dst, $op2, $op1\t#@cmpUL3_reg_reg\n\t"
8725 "bnez $dst, done\n\t"
8726 "sltu $dst, $op1, $op2\n\t"
8727 "neg $dst, $dst\n\t"
8728 "done:"
8729 %}
8730 ins_encode %{
8731 __ cmp_ul2i(t0, as_Register($op1$$reg), as_Register($op2$$reg));
8732 __ mv(as_Register($dst$$reg), t0);
8733 %}
8734
8735 ins_pipe(pipe_class_default);
8736 %}
8737
8738 instruct cmpU3_reg_reg(iRegINoSp dst, iRegI op1, iRegI op2)
8739 %{
8740 match(Set dst (CmpU3 op1 op2));
8741
8742 ins_cost(ALU_COST * 3 + BRANCH_COST);
8743 format %{ "sltu $dst, $op2, $op1\t#@cmpU3_reg_reg\n\t"
8744 "bnez $dst, done\n\t"
8745 "sltu $dst, $op1, $op2\n\t"
8746 "neg $dst, $dst\n\t"
8747 "done:"
8748 %}
8749 ins_encode %{
8750 __ cmp_uw2i(t0, as_Register($op1$$reg), as_Register($op2$$reg));
8751 __ mv(as_Register($dst$$reg), t0);
8752 %}
8753
8754 ins_pipe(pipe_class_default);
8755 %}
8756
8757 instruct cmpLTMask_reg_reg(iRegINoSp dst, iRegI p, iRegI q)
8758 %{
8759 match(Set dst (CmpLTMask p q));
8760
8761 ins_cost(2 * ALU_COST);
8762
8763 format %{ "slt $dst, $p, $q\t#@cmpLTMask_reg_reg\n\t"
8764 "subw $dst, zr, $dst\t#@cmpLTMask_reg_reg"
8765 %}
8766
8767 ins_encode %{
8768 __ slt(as_Register($dst$$reg), as_Register($p$$reg), as_Register($q$$reg));
8769 __ subw(as_Register($dst$$reg), zr, as_Register($dst$$reg));
8770 %}
8771
8772 ins_pipe(ialu_reg_reg);
8773 %}
8774
8775 instruct cmpLTMask_reg_zero(iRegINoSp dst, iRegIorL2I op, immI0 zero)
8776 %{
8777 match(Set dst (CmpLTMask op zero));
8778
8779 ins_cost(ALU_COST);
8780
8781 format %{ "sraiw $dst, $dst, 31\t#@cmpLTMask_reg_reg" %}
8782
8783 ins_encode %{
8784 __ sraiw(as_Register($dst$$reg), as_Register($op$$reg), 31);
8785 %}
8786
8787 ins_pipe(ialu_reg_shift);
8788 %}
8789
8790
8791 // ============================================================================
8792 // Max and Min
8793
8794 instruct minI_reg_reg(iRegINoSp dst, iRegI src)
8795 %{
8796 match(Set dst (MinI dst src));
8797
8798 ins_cost(BRANCH_COST + ALU_COST);
8799 format %{
8800 "ble $dst, $src, skip\t#@minI_reg_reg\n\t"
8801 "mv $dst, $src\n\t"
8802 "skip:"
8803 %}
8804
8805 ins_encode %{
8806 Label Lskip;
8807 __ ble(as_Register($dst$$reg), as_Register($src$$reg), Lskip);
8808 __ mv(as_Register($dst$$reg), as_Register($src$$reg));
8809 __ bind(Lskip);
8810 %}
8811
8812 ins_pipe(pipe_class_compare);
8813 %}
8814
8815 instruct maxI_reg_reg(iRegINoSp dst, iRegI src)
8816 %{
8817 match(Set dst (MaxI dst src));
8818
8819 ins_cost(BRANCH_COST + ALU_COST);
8820 format %{
8821 "bge $dst, $src, skip\t#@maxI_reg_reg\n\t"
8822 "mv $dst, $src\n\t"
8823 "skip:"
8824 %}
8825
8826 ins_encode %{
8827 Label Lskip;
8828 __ bge(as_Register($dst$$reg), as_Register($src$$reg), Lskip);
8829 __ mv(as_Register($dst$$reg), as_Register($src$$reg));
8830 __ bind(Lskip);
8831 %}
8832
8833 ins_pipe(pipe_class_compare);
8834 %}
8835
8836 // special case for comparing with zero
8837 // n.b. this is selected in preference to the rule above because it
8838 // avoids loading constant 0 into a source register
8839
8840 instruct minI_reg_zero(iRegINoSp dst, immI0 zero)
8841 %{
8842 match(Set dst (MinI dst zero));
8843 match(Set dst (MinI zero dst));
8844
8845 ins_cost(BRANCH_COST + ALU_COST);
8846 format %{
8847 "blez $dst, skip\t#@minI_reg_zero\n\t"
8848 "mv $dst, zr\n\t"
8849 "skip:"
8850 %}
8851
8852 ins_encode %{
8853 Label Lskip;
8854 __ blez(as_Register($dst$$reg), Lskip);
8855 __ mv(as_Register($dst$$reg), zr);
8856 __ bind(Lskip);
8857 %}
8858
8859 ins_pipe(pipe_class_compare);
8860 %}
8861
8862 instruct maxI_reg_zero(iRegINoSp dst, immI0 zero)
8863 %{
8864 match(Set dst (MaxI dst zero));
8865 match(Set dst (MaxI zero dst));
8866
8867 ins_cost(BRANCH_COST + ALU_COST);
8868 format %{
8869 "bgez $dst, skip\t#@maxI_reg_zero\n\t"
8870 "mv $dst, zr\n\t"
8871 "skip:"
8872 %}
8873
8874 ins_encode %{
8875 Label Lskip;
8876 __ bgez(as_Register($dst$$reg), Lskip);
8877 __ mv(as_Register($dst$$reg), zr);
8878 __ bind(Lskip);
8879 %}
8880
8881 ins_pipe(pipe_class_compare);
8882 %}
8883
8884 instruct minI_rReg(iRegINoSp dst, iRegI src1, iRegI src2)
8885 %{
8886 match(Set dst (MinI src1 src2));
8887
8888 effect(DEF dst, USE src1, USE src2);
8889
8890 ins_cost(BRANCH_COST + ALU_COST * 2);
8891 format %{
8892 "ble $src1, $src2, Lsrc1\t#@minI_rReg\n\t"
8893 "mv $dst, $src2\n\t"
8894 "j Ldone\n\t"
8895 "Lsrc1:\n\t"
8896 "mv $dst, $src1\n\t"
8897 "Ldone:"
8898 %}
8899
8900 ins_encode %{
8901 Label Lsrc1, Ldone;
8902 __ ble(as_Register($src1$$reg), as_Register($src2$$reg), Lsrc1);
8903 __ mv(as_Register($dst$$reg), as_Register($src2$$reg));
8904 __ j(Ldone);
8905 __ bind(Lsrc1);
8906 __ mv(as_Register($dst$$reg), as_Register($src1$$reg));
8907 __ bind(Ldone);
8908 %}
8909
8910 ins_pipe(pipe_class_compare);
8911 %}
8912
8913 instruct maxI_rReg(iRegINoSp dst, iRegI src1, iRegI src2)
8914 %{
8915 match(Set dst (MaxI src1 src2));
8916
8917 effect(DEF dst, USE src1, USE src2);
8918
8919 ins_cost(BRANCH_COST + ALU_COST * 2);
8920 format %{
8921 "bge $src1, $src2, Lsrc1\t#@maxI_rReg\n\t"
8922 "mv $dst, $src2\n\t"
8923 "j Ldone\n\t"
8924 "Lsrc1:\n\t"
8925 "mv $dst, $src1\n\t"
8926 "Ldone:"
8927 %}
8928
8929 ins_encode %{
8930 Label Lsrc1, Ldone;
8931 __ bge(as_Register($src1$$reg), as_Register($src2$$reg), Lsrc1);
8932 __ mv(as_Register($dst$$reg), as_Register($src2$$reg));
8933 __ j(Ldone);
8934 __ bind(Lsrc1);
8935 __ mv(as_Register($dst$$reg), as_Register($src1$$reg));
8936 __ bind(Ldone);
8937
8938 %}
8939
8940 ins_pipe(pipe_class_compare);
8941 %}
8942
8943 // ============================================================================
8944 // Branch Instructions
8945 // Direct Branch.
8946 instruct branch(label lbl)
8947 %{
8948 match(Goto);
8949
8950 effect(USE lbl);
8951
8952 ins_cost(BRANCH_COST);
8953 format %{ "j $lbl\t#@branch" %}
8954
8955 ins_encode(riscv_enc_j(lbl));
8956
8957 ins_pipe(pipe_branch);
8958 %}
8959
8960 // ============================================================================
8961 // Compare and Branch Instructions
8962
8963 // Patterns for short (< 12KiB) variants
8964
8965 // Compare flags and branch near instructions.
8966 instruct cmpFlag_branch(cmpOpEqNe cmp, rFlagsReg cr, label lbl) %{
8967 match(If cmp cr);
8968 effect(USE lbl);
8969
8970 ins_cost(BRANCH_COST);
8971 format %{ "b$cmp $cr, zr, $lbl\t#@cmpFlag_branch" %}
8972
8973 ins_encode %{
8974 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($cr$$reg), *($lbl$$label));
8975 %}
8976 ins_pipe(pipe_cmpz_branch);
8977 ins_short_branch(1);
8978 %}
8979
8980 // Compare signed int and branch near instructions
8981 instruct cmpI_branch(cmpOp cmp, iRegI op1, iRegI op2, label lbl)
8982 %{
8983 // Same match rule as `far_cmpI_branch'.
8984 match(If cmp (CmpI op1 op2));
8985
8986 effect(USE lbl);
8987
8988 ins_cost(BRANCH_COST);
8989
8990 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpI_branch" %}
8991
8992 ins_encode %{
8993 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label));
8994 %}
8995
8996 ins_pipe(pipe_cmp_branch);
8997 ins_short_branch(1);
8998 %}
8999
9000 instruct cmpI_loop(cmpOp cmp, iRegI op1, iRegI op2, label lbl)
9001 %{
9002 // Same match rule as `far_cmpI_loop'.
9003 match(CountedLoopEnd cmp (CmpI op1 op2));
9004
9005 effect(USE lbl);
9006
9007 ins_cost(BRANCH_COST);
9008
9009 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpI_loop" %}
9010
9011 ins_encode %{
9012 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label));
9013 %}
9014
9015 ins_pipe(pipe_cmp_branch);
9016 ins_short_branch(1);
9017 %}
9018
9019 // Compare unsigned int and branch near instructions
9020 instruct cmpU_branch(cmpOpU cmp, iRegI op1, iRegI op2, label lbl)
9021 %{
9022 // Same match rule as `far_cmpU_branch'.
9023 match(If cmp (CmpU op1 op2));
9024
9025 effect(USE lbl);
9026
9027 ins_cost(BRANCH_COST);
9028
9029 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpU_branch" %}
9030
9031 ins_encode %{
9032 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9033 as_Register($op2$$reg), *($lbl$$label));
9034 %}
9035
9036 ins_pipe(pipe_cmp_branch);
9037 ins_short_branch(1);
9038 %}
9039
9040 // Compare signed long and branch near instructions
9041 instruct cmpL_branch(cmpOp cmp, iRegL op1, iRegL op2, label lbl)
9042 %{
9043 // Same match rule as `far_cmpL_branch'.
9044 match(If cmp (CmpL op1 op2));
9045
9046 effect(USE lbl);
9047
9048 ins_cost(BRANCH_COST);
9049
9050 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpL_branch" %}
9051
9052 ins_encode %{
9053 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label));
9054 %}
9055
9056 ins_pipe(pipe_cmp_branch);
9057 ins_short_branch(1);
9058 %}
9059
9060 instruct cmpL_loop(cmpOp cmp, iRegL op1, iRegL op2, label lbl)
9061 %{
9062 // Same match rule as `far_cmpL_loop'.
9063 match(CountedLoopEnd cmp (CmpL op1 op2));
9064
9065 effect(USE lbl);
9066
9067 ins_cost(BRANCH_COST);
9068
9069 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpL_loop" %}
9070
9071 ins_encode %{
9072 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label));
9073 %}
9074
9075 ins_pipe(pipe_cmp_branch);
9076 ins_short_branch(1);
9077 %}
9078
9079 // Compare unsigned long and branch near instructions
9080 instruct cmpUL_branch(cmpOpU cmp, iRegL op1, iRegL op2, label lbl)
9081 %{
9082 // Same match rule as `far_cmpUL_branch'.
9083 match(If cmp (CmpUL op1 op2));
9084
9085 effect(USE lbl);
9086
9087 ins_cost(BRANCH_COST);
9088 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpUL_branch" %}
9089
9090 ins_encode %{
9091 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9092 as_Register($op2$$reg), *($lbl$$label));
9093 %}
9094
9095 ins_pipe(pipe_cmp_branch);
9096 ins_short_branch(1);
9097 %}
9098
9099 // Compare pointer and branch near instructions
9100 instruct cmpP_branch(cmpOpU cmp, iRegP op1, iRegP op2, label lbl)
9101 %{
9102 // Same match rule as `far_cmpP_branch'.
9103 match(If cmp (CmpP op1 op2));
9104
9105 effect(USE lbl);
9106
9107 ins_cost(BRANCH_COST);
9108
9109 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpP_branch" %}
9110
9111 ins_encode %{
9112 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9113 as_Register($op2$$reg), *($lbl$$label));
9114 %}
9115
9116 ins_pipe(pipe_cmp_branch);
9117 ins_short_branch(1);
9118 %}
9119
9120 // Compare narrow pointer and branch near instructions
9121 instruct cmpN_branch(cmpOpU cmp, iRegN op1, iRegN op2, label lbl)
9122 %{
9123 // Same match rule as `far_cmpN_branch'.
9124 match(If cmp (CmpN op1 op2));
9125
9126 effect(USE lbl);
9127
9128 ins_cost(BRANCH_COST);
9129
9130 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpN_branch" %}
9131
9132 ins_encode %{
9133 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9134 as_Register($op2$$reg), *($lbl$$label));
9135 %}
9136
9137 ins_pipe(pipe_cmp_branch);
9138 ins_short_branch(1);
9139 %}
9140
9141 // Compare float and branch near instructions
9142 instruct cmpF_branch(cmpOp cmp, fRegF op1, fRegF op2, label lbl)
9143 %{
9144 // Same match rule as `far_cmpF_branch'.
9145 match(If cmp (CmpF op1 op2));
9146
9147 effect(USE lbl);
9148
9149 ins_cost(XFER_COST + BRANCH_COST);
9150 format %{ "float_b$cmp $op1, $op2, $lbl \t#@cmpF_branch"%}
9151
9152 ins_encode %{
9153 __ float_cmp_branch($cmp$$cmpcode, as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg), *($lbl$$label));
9154 %}
9155
9156 ins_pipe(pipe_class_compare);
9157 ins_short_branch(1);
9158 %}
9159
9160 // Compare double and branch near instructions
9161 instruct cmpD_branch(cmpOp cmp, fRegD op1, fRegD op2, label lbl)
9162 %{
9163 // Same match rule as `far_cmpD_branch'.
9164 match(If cmp (CmpD op1 op2));
9165 effect(USE lbl);
9166
9167 ins_cost(XFER_COST + BRANCH_COST);
9168 format %{ "double_b$cmp $op1, $op2, $lbl\t#@cmpD_branch"%}
9169
9170 ins_encode %{
9171 __ float_cmp_branch($cmp$$cmpcode | C2_MacroAssembler::double_branch_mask, as_FloatRegister($op1$$reg),
9172 as_FloatRegister($op2$$reg), *($lbl$$label));
9173 %}
9174
9175 ins_pipe(pipe_class_compare);
9176 ins_short_branch(1);
9177 %}
9178
9179 // Compare signed int with zero and branch near instructions
9180 instruct cmpI_reg_imm0_branch(cmpOp cmp, iRegI op1, immI0 zero, label lbl)
9181 %{
9182 // Same match rule as `far_cmpI_reg_imm0_branch'.
9183 match(If cmp (CmpI op1 zero));
9184
9185 effect(USE op1, USE lbl);
9186
9187 ins_cost(BRANCH_COST);
9188 format %{ "b$cmp $op1, zr, $lbl\t#@cmpI_reg_imm0_branch" %}
9189
9190 ins_encode %{
9191 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label));
9192 %}
9193
9194 ins_pipe(pipe_cmpz_branch);
9195 ins_short_branch(1);
9196 %}
9197
9198 instruct cmpI_reg_imm0_loop(cmpOp cmp, iRegI op1, immI0 zero, label lbl)
9199 %{
9200 // Same match rule as `far_cmpI_reg_imm0_loop'.
9201 match(CountedLoopEnd cmp (CmpI op1 zero));
9202
9203 effect(USE op1, USE lbl);
9204
9205 ins_cost(BRANCH_COST);
9206
9207 format %{ "b$cmp $op1, zr, $lbl\t#@cmpI_reg_imm0_loop" %}
9208
9209 ins_encode %{
9210 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label));
9211 %}
9212
9213 ins_pipe(pipe_cmpz_branch);
9214 ins_short_branch(1);
9215 %}
9216
9217 // Compare unsigned int with zero and branch near instructions
9218 instruct cmpUEqNeLeGt_reg_imm0_branch(cmpOpUEqNeLeGt cmp, iRegI op1, immI0 zero, label lbl)
9219 %{
9220 // Same match rule as `far_cmpUEqNeLeGt_reg_imm0_branch'.
9221 match(If cmp (CmpU op1 zero));
9222
9223 effect(USE op1, USE lbl);
9224
9225 ins_cost(BRANCH_COST);
9226
9227 format %{ "b$cmp $op1, zr, $lbl\t#@cmpUEqNeLeGt_reg_imm0_branch" %}
9228
9229 ins_encode %{
9230 __ enc_cmpUEqNeLeGt_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
9231 %}
9232
9233 ins_pipe(pipe_cmpz_branch);
9234 ins_short_branch(1);
9235 %}
9236
9237 // Compare signed long with zero and branch near instructions
9238 instruct cmpL_reg_imm0_branch(cmpOp cmp, iRegL op1, immL0 zero, label lbl)
9239 %{
9240 // Same match rule as `far_cmpL_reg_imm0_branch'.
9241 match(If cmp (CmpL op1 zero));
9242
9243 effect(USE op1, USE lbl);
9244
9245 ins_cost(BRANCH_COST);
9246
9247 format %{ "b$cmp $op1, zr, $lbl\t#@cmpL_reg_imm0_branch" %}
9248
9249 ins_encode %{
9250 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label));
9251 %}
9252
9253 ins_pipe(pipe_cmpz_branch);
9254 ins_short_branch(1);
9255 %}
9256
9257 instruct cmpL_reg_imm0_loop(cmpOp cmp, iRegL op1, immL0 zero, label lbl)
9258 %{
9259 // Same match rule as `far_cmpL_reg_imm0_loop'.
9260 match(CountedLoopEnd cmp (CmpL op1 zero));
9261
9262 effect(USE op1, USE lbl);
9263
9264 ins_cost(BRANCH_COST);
9265
9266 format %{ "b$cmp $op1, zr, $lbl\t#@cmpL_reg_imm0_loop" %}
9267
9268 ins_encode %{
9269 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label));
9270 %}
9271
9272 ins_pipe(pipe_cmpz_branch);
9273 ins_short_branch(1);
9274 %}
9275
9276 // Compare unsigned long with zero and branch near instructions
9277 instruct cmpULEqNeLeGt_reg_imm0_branch(cmpOpUEqNeLeGt cmp, iRegL op1, immL0 zero, label lbl)
9278 %{
9279 // Same match rule as `far_cmpULEqNeLeGt_reg_imm0_branch'.
9280 match(If cmp (CmpUL op1 zero));
9281
9282 effect(USE op1, USE lbl);
9283
9284 ins_cost(BRANCH_COST);
9285
9286 format %{ "b$cmp $op1, zr, $lbl\t#@cmpULEqNeLeGt_reg_imm0_branch" %}
9287
9288 ins_encode %{
9289 __ enc_cmpUEqNeLeGt_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
9290 %}
9291
9292 ins_pipe(pipe_cmpz_branch);
9293 ins_short_branch(1);
9294 %}
9295
9296 // Compare pointer with zero and branch near instructions
9297 instruct cmpP_imm0_branch(cmpOpEqNe cmp, iRegP op1, immP0 zero, label lbl) %{
9298 // Same match rule as `far_cmpP_reg_imm0_branch'.
9299 match(If cmp (CmpP op1 zero));
9300 effect(USE lbl);
9301
9302 ins_cost(BRANCH_COST);
9303 format %{ "b$cmp $op1, zr, $lbl\t#@cmpP_imm0_branch" %}
9304
9305 ins_encode %{
9306 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
9307 %}
9308
9309 ins_pipe(pipe_cmpz_branch);
9310 ins_short_branch(1);
9311 %}
9312
9313 // Compare narrow pointer with zero and branch near instructions
9314 instruct cmpN_imm0_branch(cmpOpEqNe cmp, iRegN op1, immN0 zero, label lbl) %{
9315 // Same match rule as `far_cmpN_reg_imm0_branch'.
9316 match(If cmp (CmpN op1 zero));
9317 effect(USE lbl);
9318
9319 ins_cost(BRANCH_COST);
9320
9321 format %{ "b$cmp $op1, zr, $lbl\t#@cmpN_imm0_branch" %}
9322
9323 ins_encode %{
9324 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
9325 %}
9326
9327 ins_pipe(pipe_cmpz_branch);
9328 ins_short_branch(1);
9329 %}
9330
9331 // Compare narrow pointer with pointer zero and branch near instructions
9332 instruct cmpP_narrowOop_imm0_branch(cmpOpEqNe cmp, iRegN op1, immP0 zero, label lbl) %{
9333 // Same match rule as `far_cmpP_narrowOop_imm0_branch'.
9334 match(If cmp (CmpP (DecodeN op1) zero));
9335 effect(USE lbl);
9336
9337 ins_cost(BRANCH_COST);
9338 format %{ "b$cmp $op1, zr, $lbl\t#@cmpP_narrowOop_imm0_branch" %}
9339
9340 ins_encode %{
9341 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
9342 %}
9343
9344 ins_pipe(pipe_cmpz_branch);
9345 ins_short_branch(1);
9346 %}
9347
9348 // Patterns for far (20KiB) variants
9349
9350 instruct far_cmpFlag_branch(cmpOp cmp, rFlagsReg cr, label lbl) %{
9351 match(If cmp cr);
9352 effect(USE lbl);
9353
9354 ins_cost(BRANCH_COST);
9355 format %{ "far_b$cmp $cr, zr, $lbl\t#@far_cmpFlag_branch"%}
9356
9357 ins_encode %{
9358 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($cr$$reg), *($lbl$$label), /* is_far */ true);
9359 %}
9360
9361 ins_pipe(pipe_cmpz_branch);
9362 %}
9363
9364 // Compare signed int and branch far instructions
9365 instruct far_cmpI_branch(cmpOp cmp, iRegI op1, iRegI op2, label lbl) %{
9366 match(If cmp (CmpI op1 op2));
9367 effect(USE lbl);
9368
9369 ins_cost(BRANCH_COST * 2);
9370
9371 // the format instruction [far_b$cmp] here is be used as two insructions
9372 // in macroassembler: b$not_cmp(op1, op2, done), j($lbl), bind(done)
9373 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpI_branch" %}
9374
9375 ins_encode %{
9376 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9377 %}
9378
9379 ins_pipe(pipe_cmp_branch);
9380 %}
9381
9382 instruct far_cmpI_loop(cmpOp cmp, iRegI op1, iRegI op2, label lbl) %{
9383 match(CountedLoopEnd cmp (CmpI op1 op2));
9384 effect(USE lbl);
9385
9386 ins_cost(BRANCH_COST * 2);
9387 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpI_loop" %}
9388
9389 ins_encode %{
9390 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9391 %}
9392
9393 ins_pipe(pipe_cmp_branch);
9394 %}
9395
9396 instruct far_cmpU_branch(cmpOpU cmp, iRegI op1, iRegI op2, label lbl) %{
9397 match(If cmp (CmpU op1 op2));
9398 effect(USE lbl);
9399
9400 ins_cost(BRANCH_COST * 2);
9401 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpU_branch" %}
9402
9403 ins_encode %{
9404 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9405 as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9406 %}
9407
9408 ins_pipe(pipe_cmp_branch);
9409 %}
9410
9411 instruct far_cmpL_branch(cmpOp cmp, iRegL op1, iRegL op2, label lbl) %{
9412 match(If cmp (CmpL op1 op2));
9413 effect(USE lbl);
9414
9415 ins_cost(BRANCH_COST * 2);
9416 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpL_branch" %}
9417
9418 ins_encode %{
9419 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9420 %}
9421
9422 ins_pipe(pipe_cmp_branch);
9423 %}
9424
9425 instruct far_cmpLloop(cmpOp cmp, iRegL op1, iRegL op2, label lbl) %{
9426 match(CountedLoopEnd cmp (CmpL op1 op2));
9427 effect(USE lbl);
9428
9429 ins_cost(BRANCH_COST * 2);
9430 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpL_loop" %}
9431
9432 ins_encode %{
9433 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9434 %}
9435
9436 ins_pipe(pipe_cmp_branch);
9437 %}
9438
9439 instruct far_cmpUL_branch(cmpOpU cmp, iRegL op1, iRegL op2, label lbl) %{
9440 match(If cmp (CmpUL op1 op2));
9441 effect(USE lbl);
9442
9443 ins_cost(BRANCH_COST * 2);
9444 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpUL_branch" %}
9445
9446 ins_encode %{
9447 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9448 as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9449 %}
9450
9451 ins_pipe(pipe_cmp_branch);
9452 %}
9453
9454 instruct far_cmpP_branch(cmpOpU cmp, iRegP op1, iRegP op2, label lbl)
9455 %{
9456 match(If cmp (CmpP op1 op2));
9457
9458 effect(USE lbl);
9459
9460 ins_cost(BRANCH_COST * 2);
9461
9462 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpP_branch" %}
9463
9464 ins_encode %{
9465 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9466 as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9467 %}
9468
9469 ins_pipe(pipe_cmp_branch);
9470 %}
9471
9472 instruct far_cmpN_branch(cmpOpU cmp, iRegN op1, iRegN op2, label lbl)
9473 %{
9474 match(If cmp (CmpN op1 op2));
9475
9476 effect(USE lbl);
9477
9478 ins_cost(BRANCH_COST * 2);
9479
9480 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpN_branch" %}
9481
9482 ins_encode %{
9483 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9484 as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9485 %}
9486
9487 ins_pipe(pipe_cmp_branch);
9488 %}
9489
9490 // Float compare and branch instructions
9491 instruct far_cmpF_branch(cmpOp cmp, fRegF op1, fRegF op2, label lbl)
9492 %{
9493 match(If cmp (CmpF op1 op2));
9494
9495 effect(USE lbl);
9496
9497 ins_cost(XFER_COST + BRANCH_COST * 2);
9498 format %{ "far_float_b$cmp $op1, $op2, $lbl\t#@far_cmpF_branch"%}
9499
9500 ins_encode %{
9501 __ float_cmp_branch($cmp$$cmpcode, as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg),
9502 *($lbl$$label), /* is_far */ true);
9503 %}
9504
9505 ins_pipe(pipe_class_compare);
9506 %}
9507
9508 // Double compare and branch instructions
9509 instruct far_cmpD_branch(cmpOp cmp, fRegD op1, fRegD op2, label lbl)
9510 %{
9511 match(If cmp (CmpD op1 op2));
9512 effect(USE lbl);
9513
9514 ins_cost(XFER_COST + BRANCH_COST * 2);
9515 format %{ "far_double_b$cmp $op1, $op2, $lbl\t#@far_cmpD_branch"%}
9516
9517 ins_encode %{
9518 __ float_cmp_branch($cmp$$cmpcode | C2_MacroAssembler::double_branch_mask, as_FloatRegister($op1$$reg),
9519 as_FloatRegister($op2$$reg), *($lbl$$label), /* is_far */ true);
9520 %}
9521
9522 ins_pipe(pipe_class_compare);
9523 %}
9524
9525 instruct far_cmpI_reg_imm0_branch(cmpOp cmp, iRegI op1, immI0 zero, label lbl)
9526 %{
9527 match(If cmp (CmpI op1 zero));
9528
9529 effect(USE op1, USE lbl);
9530
9531 ins_cost(BRANCH_COST * 2);
9532
9533 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpI_reg_imm0_branch" %}
9534
9535 ins_encode %{
9536 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label), /* is_far */ true);
9537 %}
9538
9539 ins_pipe(pipe_cmpz_branch);
9540 %}
9541
9542 instruct far_cmpI_reg_imm0_loop(cmpOp cmp, iRegI op1, immI0 zero, label lbl)
9543 %{
9544 match(CountedLoopEnd cmp (CmpI op1 zero));
9545
9546 effect(USE op1, USE lbl);
9547
9548 ins_cost(BRANCH_COST * 2);
9549
9550 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpI_reg_imm0_loop" %}
9551
9552 ins_encode %{
9553 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label), /* is_far */ true);
9554 %}
9555
9556 ins_pipe(pipe_cmpz_branch);
9557 %}
9558
9559 instruct far_cmpUEqNeLeGt_imm0_branch(cmpOpUEqNeLeGt cmp, iRegI op1, immI0 zero, label lbl)
9560 %{
9561 match(If cmp (CmpU op1 zero));
9562
9563 effect(USE op1, USE lbl);
9564
9565 ins_cost(BRANCH_COST * 2);
9566
9567 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpUEqNeLeGt_imm0_branch" %}
9568
9569 ins_encode %{
9570 __ enc_cmpUEqNeLeGt_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
9571 %}
9572
9573 ins_pipe(pipe_cmpz_branch);
9574 %}
9575
9576 // compare lt/ge unsigned instructs has no short instruct with same match
9577 instruct far_cmpULtGe_reg_imm0_branch(cmpOpULtGe cmp, iRegI op1, immI0 zero, label lbl)
9578 %{
9579 match(If cmp (CmpU op1 zero));
9580
9581 effect(USE op1, USE lbl);
9582
9583 ins_cost(BRANCH_COST);
9584
9585 format %{ "j $lbl if $cmp == ge\t#@far_cmpULtGe_reg_imm0_branch" %}
9586
9587 ins_encode(riscv_enc_far_cmpULtGe_imm0_branch(cmp, op1, lbl));
9588
9589 ins_pipe(pipe_cmpz_branch);
9590 %}
9591
9592 instruct far_cmpL_reg_imm0_branch(cmpOp cmp, iRegL op1, immL0 zero, label lbl)
9593 %{
9594 match(If cmp (CmpL op1 zero));
9595
9596 effect(USE op1, USE lbl);
9597
9598 ins_cost(BRANCH_COST * 2);
9599
9600 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpL_reg_imm0_branch" %}
9601
9602 ins_encode %{
9603 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label), /* is_far */ true);
9604 %}
9605
9606 ins_pipe(pipe_cmpz_branch);
9607 %}
9608
9609 instruct far_cmpL_reg_imm0_loop(cmpOp cmp, iRegL op1, immL0 zero, label lbl)
9610 %{
9611 match(CountedLoopEnd cmp (CmpL op1 zero));
9612
9613 effect(USE op1, USE lbl);
9614
9615 ins_cost(BRANCH_COST * 2);
9616
9617 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpL_reg_imm0_loop" %}
9618
9619 ins_encode %{
9620 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label), /* is_far */ true);
9621 %}
9622
9623 ins_pipe(pipe_cmpz_branch);
9624 %}
9625
9626 instruct far_cmpULEqNeLeGt_reg_imm0_branch(cmpOpUEqNeLeGt cmp, iRegL op1, immL0 zero, label lbl)
9627 %{
9628 match(If cmp (CmpUL op1 zero));
9629
9630 effect(USE op1, USE lbl);
9631
9632 ins_cost(BRANCH_COST * 2);
9633
9634 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpULEqNeLeGt_reg_imm0_branch" %}
9635
9636 ins_encode %{
9637 __ enc_cmpUEqNeLeGt_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
9638 %}
9639
9640 ins_pipe(pipe_cmpz_branch);
9641 %}
9642
9643 // compare lt/ge unsigned instructs has no short instruct with same match
9644 instruct far_cmpULLtGe_reg_imm0_branch(cmpOpULtGe cmp, iRegL op1, immL0 zero, label lbl)
9645 %{
9646 match(If cmp (CmpUL op1 zero));
9647
9648 effect(USE op1, USE lbl);
9649
9650 ins_cost(BRANCH_COST);
9651
9652 format %{ "j $lbl if $cmp == ge\t#@far_cmpULLtGe_reg_imm0_branch" %}
9653
9654 ins_encode(riscv_enc_far_cmpULtGe_imm0_branch(cmp, op1, lbl));
9655
9656 ins_pipe(pipe_cmpz_branch);
9657 %}
9658
9659 instruct far_cmpP_imm0_branch(cmpOpEqNe cmp, iRegP op1, immP0 zero, label lbl) %{
9660 match(If cmp (CmpP op1 zero));
9661 effect(USE lbl);
9662
9663 ins_cost(BRANCH_COST * 2);
9664 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpP_imm0_branch" %}
9665
9666 ins_encode %{
9667 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
9668 %}
9669
9670 ins_pipe(pipe_cmpz_branch);
9671 %}
9672
9673 instruct far_cmpN_imm0_branch(cmpOpEqNe cmp, iRegN op1, immN0 zero, label lbl) %{
9674 match(If cmp (CmpN op1 zero));
9675 effect(USE lbl);
9676
9677 ins_cost(BRANCH_COST * 2);
9678
9679 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpN_imm0_branch" %}
9680
9681 ins_encode %{
9682 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
9683 %}
9684
9685 ins_pipe(pipe_cmpz_branch);
9686 %}
9687
9688 instruct far_cmpP_narrowOop_imm0_branch(cmpOpEqNe cmp, iRegN op1, immP0 zero, label lbl) %{
9689 match(If cmp (CmpP (DecodeN op1) zero));
9690 effect(USE lbl);
9691
9692 ins_cost(BRANCH_COST * 2);
9693 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpP_narrowOop_imm0_branch" %}
9694
9695 ins_encode %{
9696 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
9697 %}
9698
9699 ins_pipe(pipe_cmpz_branch);
9700 %}
9701
9702 // ============================================================================
9703 // Conditional Move Instructions
9704 instruct cmovI_cmpI(iRegINoSp dst, iRegI src, iRegI op1, iRegI op2, cmpOp cop) %{
9705 match(Set dst (CMoveI (Binary cop (CmpI op1 op2)) (Binary dst src)));
9706 ins_cost(ALU_COST + BRANCH_COST);
9707
9708 format %{
9709 "CMove $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpI\n\t"
9710 %}
9711
9712 ins_encode %{
9713 __ enc_cmove($cop$$cmpcode,
9714 as_Register($op1$$reg), as_Register($op2$$reg),
9715 as_Register($dst$$reg), as_Register($src$$reg));
9716 %}
9717
9718 ins_pipe(pipe_class_compare);
9719 %}
9720
9721 instruct cmovI_cmpU(iRegINoSp dst, iRegI src, iRegI op1, iRegI op2, cmpOpU cop) %{
9722 match(Set dst (CMoveI (Binary cop (CmpU op1 op2)) (Binary dst src)));
9723 ins_cost(ALU_COST + BRANCH_COST);
9724
9725 format %{
9726 "CMove $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpU\n\t"
9727 %}
9728
9729 ins_encode %{
9730 __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
9731 as_Register($op1$$reg), as_Register($op2$$reg),
9732 as_Register($dst$$reg), as_Register($src$$reg));
9733 %}
9734
9735 ins_pipe(pipe_class_compare);
9736 %}
9737
9738 instruct cmovI_cmpL(iRegINoSp dst, iRegI src, iRegL op1, iRegL op2, cmpOp cop) %{
9739 match(Set dst (CMoveI (Binary cop (CmpL op1 op2)) (Binary dst src)));
9740 ins_cost(ALU_COST + BRANCH_COST);
9741
9742 format %{
9743 "CMove $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpL\n\t"
9744 %}
9745
9746 ins_encode %{
9747 __ enc_cmove($cop$$cmpcode,
9748 as_Register($op1$$reg), as_Register($op2$$reg),
9749 as_Register($dst$$reg), as_Register($src$$reg));
9750 %}
9751
9752 ins_pipe(pipe_class_compare);
9753 %}
9754
9755 instruct cmovI_cmpUL(iRegINoSp dst, iRegI src, iRegL op1, iRegL op2, cmpOpU cop) %{
9756 match(Set dst (CMoveI (Binary cop (CmpUL op1 op2)) (Binary dst src)));
9757 ins_cost(ALU_COST + BRANCH_COST);
9758
9759 format %{
9760 "CMove $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpUL\n\t"
9761 %}
9762
9763 ins_encode %{
9764 __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
9765 as_Register($op1$$reg), as_Register($op2$$reg),
9766 as_Register($dst$$reg), as_Register($src$$reg));
9767 %}
9768
9769 ins_pipe(pipe_class_compare);
9770 %}
9771
9772 instruct cmovI_cmpN(iRegINoSp dst, iRegI src, iRegN op1, iRegN op2, cmpOpU cop) %{
9773 match(Set dst (CMoveI (Binary cop (CmpN op1 op2)) (Binary dst src)));
9774 ins_cost(ALU_COST + BRANCH_COST);
9775
9776 format %{
9777 "CMove $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpN\n\t"
9778 %}
9779
9780 ins_encode %{
9781 __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
9782 as_Register($op1$$reg), as_Register($op2$$reg),
9783 as_Register($dst$$reg), as_Register($src$$reg));
9784 %}
9785
9786 ins_pipe(pipe_class_compare);
9787 %}
9788
9789 instruct cmovI_cmpP(iRegINoSp dst, iRegI src, iRegP op1, iRegP op2, cmpOpU cop) %{
9790 match(Set dst (CMoveI (Binary cop (CmpP op1 op2)) (Binary dst src)));
9791 ins_cost(ALU_COST + BRANCH_COST);
9792
9793 format %{
9794 "CMove $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpP\n\t"
9795 %}
9796
9797 ins_encode %{
9798 __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
9799 as_Register($op1$$reg), as_Register($op2$$reg),
9800 as_Register($dst$$reg), as_Register($src$$reg));
9801 %}
9802
9803 ins_pipe(pipe_class_compare);
9804 %}
9805
9806 instruct cmovL_cmpL(iRegLNoSp dst, iRegL src, iRegL op1, iRegL op2, cmpOp cop) %{
9807 match(Set dst (CMoveL (Binary cop (CmpL op1 op2)) (Binary dst src)));
9808 ins_cost(ALU_COST + BRANCH_COST);
9809
9810 format %{
9811 "CMove $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpL\n\t"
9812 %}
9813
9814 ins_encode %{
9815 __ enc_cmove($cop$$cmpcode,
9816 as_Register($op1$$reg), as_Register($op2$$reg),
9817 as_Register($dst$$reg), as_Register($src$$reg));
9818 %}
9819
9820 ins_pipe(pipe_class_compare);
9821 %}
9822
9823 instruct cmovL_cmpUL(iRegLNoSp dst, iRegL src, iRegL op1, iRegL op2, cmpOpU cop) %{
9824 match(Set dst (CMoveL (Binary cop (CmpUL op1 op2)) (Binary dst src)));
9825 ins_cost(ALU_COST + BRANCH_COST);
9826
9827 format %{
9828 "CMove $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpUL\n\t"
9829 %}
9830
9831 ins_encode %{
9832 __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
9833 as_Register($op1$$reg), as_Register($op2$$reg),
9834 as_Register($dst$$reg), as_Register($src$$reg));
9835 %}
9836
9837 ins_pipe(pipe_class_compare);
9838 %}
9839
9840 instruct cmovL_cmpI(iRegLNoSp dst, iRegL src, iRegI op1, iRegI op2, cmpOp cop) %{
9841 match(Set dst (CMoveL (Binary cop (CmpI op1 op2)) (Binary dst src)));
9842 ins_cost(ALU_COST + BRANCH_COST);
9843
9844 format %{
9845 "CMove $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpI\n\t"
9846 %}
9847
9848 ins_encode %{
9849 __ enc_cmove($cop$$cmpcode,
9850 as_Register($op1$$reg), as_Register($op2$$reg),
9851 as_Register($dst$$reg), as_Register($src$$reg));
9852 %}
9853
9854 ins_pipe(pipe_class_compare);
9855 %}
9856
9857 instruct cmovL_cmpU(iRegLNoSp dst, iRegL src, iRegI op1, iRegI op2, cmpOpU cop) %{
9858 match(Set dst (CMoveL (Binary cop (CmpU op1 op2)) (Binary dst src)));
9859 ins_cost(ALU_COST + BRANCH_COST);
9860
9861 format %{
9862 "CMove $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpU\n\t"
9863 %}
9864
9865 ins_encode %{
9866 __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
9867 as_Register($op1$$reg), as_Register($op2$$reg),
9868 as_Register($dst$$reg), as_Register($src$$reg));
9869 %}
9870
9871 ins_pipe(pipe_class_compare);
9872 %}
9873
9874 instruct cmovL_cmpN(iRegLNoSp dst, iRegL src, iRegN op1, iRegN op2, cmpOpU cop) %{
9875 match(Set dst (CMoveL (Binary cop (CmpN op1 op2)) (Binary dst src)));
9876 ins_cost(ALU_COST + BRANCH_COST);
9877
9878 format %{
9879 "CMove $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpN\n\t"
9880 %}
9881
9882 ins_encode %{
9883 __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
9884 as_Register($op1$$reg), as_Register($op2$$reg),
9885 as_Register($dst$$reg), as_Register($src$$reg));
9886 %}
9887
9888 ins_pipe(pipe_class_compare);
9889 %}
9890
9891 instruct cmovL_cmpP(iRegLNoSp dst, iRegL src, iRegP op1, iRegP op2, cmpOpU cop) %{
9892 match(Set dst (CMoveL (Binary cop (CmpP op1 op2)) (Binary dst src)));
9893 ins_cost(ALU_COST + BRANCH_COST);
9894
9895 format %{
9896 "CMove $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpP\n\t"
9897 %}
9898
9899 ins_encode %{
9900 __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
9901 as_Register($op1$$reg), as_Register($op2$$reg),
9902 as_Register($dst$$reg), as_Register($src$$reg));
9903 %}
9904
9905 ins_pipe(pipe_class_compare);
9906 %}
9907
9908 // ============================================================================
9909 // Procedure Call/Return Instructions
9910
9911 // Call Java Static Instruction
9912 // Note: If this code changes, the corresponding ret_addr_offset() and
9913 // compute_padding() functions will have to be adjusted.
9914 instruct CallStaticJavaDirect(method meth)
9915 %{
9916 match(CallStaticJava);
9917
9918 effect(USE meth);
9919
9920 ins_cost(BRANCH_COST);
9921
9922 format %{ "CALL,static $meth\t#@CallStaticJavaDirect" %}
9923
9924 ins_encode(riscv_enc_java_static_call(meth),
9925 riscv_enc_call_epilog);
9926
9927 ins_pipe(pipe_class_call);
9928 ins_alignment(4);
9929 %}
9930
9931 // TO HERE
9932
9933 // Call Java Dynamic Instruction
9934 // Note: If this code changes, the corresponding ret_addr_offset() and
9935 // compute_padding() functions will have to be adjusted.
9936 instruct CallDynamicJavaDirect(method meth)
9937 %{
9938 match(CallDynamicJava);
9939
9940 effect(USE meth);
9941
9942 ins_cost(BRANCH_COST + ALU_COST * 5);
9943
9944 format %{ "CALL,dynamic $meth\t#@CallDynamicJavaDirect" %}
9945
9946 ins_encode(riscv_enc_java_dynamic_call(meth),
9947 riscv_enc_call_epilog);
9948
9949 ins_pipe(pipe_class_call);
9950 ins_alignment(4);
9951 %}
9952
9953 // Call Runtime Instruction
9954
9955 instruct CallRuntimeDirect(method meth)
9956 %{
9957 match(CallRuntime);
9958
9959 effect(USE meth);
9960
9961 ins_cost(BRANCH_COST);
9962
9963 format %{ "CALL, runtime $meth\t#@CallRuntimeDirect" %}
9964
9965 ins_encode(riscv_enc_java_to_runtime(meth));
9966
9967 ins_pipe(pipe_class_call);
9968 %}
9969
9970 // Call Runtime Instruction
9971
9972 instruct CallLeafDirect(method meth)
9973 %{
9974 match(CallLeaf);
9975
9976 effect(USE meth);
9977
9978 ins_cost(BRANCH_COST);
9979
9980 format %{ "CALL, runtime leaf $meth\t#@CallLeafDirect" %}
9981
9982 ins_encode(riscv_enc_java_to_runtime(meth));
9983
9984 ins_pipe(pipe_class_call);
9985 %}
9986
9987 // Call Runtime Instruction without safepoint and with vector arguments
9988
9989 instruct CallLeafDirectVector(method meth)
9990 %{
9991 match(CallLeafVector);
9992
9993 effect(USE meth);
9994
9995 ins_cost(BRANCH_COST);
9996
9997 format %{ "CALL, runtime leaf vector $meth" %}
9998
9999 ins_encode(riscv_enc_java_to_runtime(meth));
10000
10001 ins_pipe(pipe_class_call);
10002 %}
10003
10004 // Call Runtime Instruction
10005
10006 instruct CallLeafNoFPDirect(method meth)
10007 %{
10008 match(CallLeafNoFP);
10009
10010 effect(USE meth);
10011
10012 ins_cost(BRANCH_COST);
10013
10014 format %{ "CALL, runtime leaf nofp $meth\t#@CallLeafNoFPDirect" %}
10015
10016 ins_encode(riscv_enc_java_to_runtime(meth));
10017
10018 ins_pipe(pipe_class_call);
10019 %}
10020
10021 // ============================================================================
10022 // Partial Subtype Check
10023 //
10024 // superklass array for an instance of the superklass. Set a hidden
10025 // internal cache on a hit (cache is checked with exposed code in
10026 // gen_subtype_check()). Return zero for a hit. The encoding
10027 // ALSO sets flags.
10028
10029 instruct partialSubtypeCheck(iRegP_R15 result, iRegP_R14 sub, iRegP_R10 super, iRegP_R12 tmp, rFlagsReg cr)
10030 %{
10031 predicate(!UseSecondarySupersTable);
10032 match(Set result (PartialSubtypeCheck sub super));
10033 effect(KILL tmp, KILL cr);
10034
10035 ins_cost(20 * DEFAULT_COST);
10036 format %{ "partialSubtypeCheck $result, $sub, $super\t#@partialSubtypeCheck" %}
10037
10038 ins_encode(riscv_enc_partial_subtype_check(sub, super, tmp, result));
10039
10040 opcode(0x1); // Force zero of result reg on hit
10041
10042 ins_pipe(pipe_class_memory);
10043 %}
10044
10045 // Two versions of partialSubtypeCheck, both used when we need to
10046 // search for a super class in the secondary supers array. The first
10047 // is used when we don't know _a priori_ the class being searched
10048 // for. The second, far more common, is used when we do know: this is
10049 // used for instanceof, checkcast, and any case where C2 can determine
10050 // it by constant propagation.
10051
10052 instruct partialSubtypeCheckVarSuper(iRegP_R14 sub, iRegP_R10 super, iRegP_R15 result,
10053 iRegP_R11 tmpR11, iRegP_R12 tmpR12, iRegP_R13 tmpR13,
10054 iRegP_R16 tmpR16, rFlagsReg cr)
10055 %{
10056 predicate(UseSecondarySupersTable);
10057 match(Set result (PartialSubtypeCheck sub super));
10058 effect(TEMP tmpR11, TEMP tmpR12, TEMP tmpR13, TEMP tmpR16, KILL cr);
10059
10060 ins_cost(10 * DEFAULT_COST); // slightly larger than the next version
10061 format %{ "partialSubtypeCheck $result, $sub, $super" %}
10062
10063 ins_encode %{
10064 __ lookup_secondary_supers_table_var($sub$$Register, $super$$Register, $result$$Register,
10065 $tmpR11$$Register, $tmpR12$$Register, $tmpR13$$Register,
10066 $tmpR16$$Register, nullptr /*L_success*/);
10067 %}
10068
10069 ins_pipe(pipe_class_memory);
10070 %}
10071
10072 instruct partialSubtypeCheckConstSuper(iRegP_R14 sub, iRegP_R10 super_reg, immP super_con, iRegP_R15 result,
10073 iRegP_R11 tmpR11, iRegP_R12 tmpR12, iRegP_R13 tmpR13, iRegP_R16 tmpR16, rFlagsReg cr)
10074 %{
10075 predicate(UseSecondarySupersTable);
10076 match(Set result (PartialSubtypeCheck sub (Binary super_reg super_con)));
10077 effect(TEMP tmpR11, TEMP tmpR12, TEMP tmpR13, TEMP tmpR16, KILL cr);
10078
10079 ins_cost(5 * DEFAULT_COST); // needs to be less than competing nodes
10080 format %{ "partialSubtypeCheck $result, $sub, $super_reg, $super_con" %}
10081
10082 ins_encode %{
10083 bool success = false;
10084 u1 super_klass_slot = ((Klass*)$super_con$$constant)->hash_slot();
10085 if (InlineSecondarySupersTest) {
10086 success = __ lookup_secondary_supers_table_const($sub$$Register, $super_reg$$Register, $result$$Register,
10087 $tmpR11$$Register, $tmpR12$$Register, $tmpR13$$Register,
10088 $tmpR16$$Register, super_klass_slot);
10089 } else {
10090 address call = __ reloc_call(RuntimeAddress(StubRoutines::lookup_secondary_supers_table_stub(super_klass_slot)));
10091 success = (call != nullptr);
10092 }
10093 if (!success) {
10094 ciEnv::current()->record_failure("CodeCache is full");
10095 return;
10096 }
10097 %}
10098
10099 ins_pipe(pipe_class_memory);
10100 %}
10101
10102 instruct string_compareU(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
10103 iRegI_R10 result, iRegP_R28 tmp1, iRegL_R29 tmp2, iRegL_R30 tmp3, rFlagsReg cr)
10104 %{
10105 predicate(!UseRVV && ((StrCompNode *)n)->encoding() == StrIntrinsicNode::UU);
10106 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10107 effect(KILL tmp1, KILL tmp2, KILL tmp3, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
10108
10109 format %{ "String Compare $str1, $cnt1, $str2, $cnt2 -> $result\t#@string_compareU" %}
10110 ins_encode %{
10111 // Count is in 8-bit bytes; non-Compact chars are 16 bits.
10112 __ string_compare($str1$$Register, $str2$$Register,
10113 $cnt1$$Register, $cnt2$$Register, $result$$Register,
10114 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
10115 StrIntrinsicNode::UU);
10116 %}
10117 ins_pipe(pipe_class_memory);
10118 %}
10119
10120 instruct string_compareL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
10121 iRegI_R10 result, iRegP_R28 tmp1, iRegL_R29 tmp2, iRegL_R30 tmp3, rFlagsReg cr)
10122 %{
10123 predicate(!UseRVV && ((StrCompNode *)n)->encoding() == StrIntrinsicNode::LL);
10124 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10125 effect(KILL tmp1, KILL tmp2, KILL tmp3, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
10126
10127 format %{ "String Compare $str1, $cnt1, $str2, $cnt2 -> $result\t#@string_compareL" %}
10128 ins_encode %{
10129 __ string_compare($str1$$Register, $str2$$Register,
10130 $cnt1$$Register, $cnt2$$Register, $result$$Register,
10131 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
10132 StrIntrinsicNode::LL);
10133 %}
10134 ins_pipe(pipe_class_memory);
10135 %}
10136
10137 instruct string_compareUL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
10138 iRegI_R10 result, iRegP_R28 tmp1, iRegL_R29 tmp2, iRegL_R30 tmp3, rFlagsReg cr)
10139 %{
10140 predicate(!UseRVV && ((StrCompNode *)n)->encoding() == StrIntrinsicNode::UL);
10141 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10142 effect(KILL tmp1, KILL tmp2, KILL tmp3, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
10143
10144 format %{"String Compare $str1, $cnt1, $str2, $cnt2 -> $result\t#@string_compareUL" %}
10145 ins_encode %{
10146 __ string_compare($str1$$Register, $str2$$Register,
10147 $cnt1$$Register, $cnt2$$Register, $result$$Register,
10148 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
10149 StrIntrinsicNode::UL);
10150 %}
10151 ins_pipe(pipe_class_memory);
10152 %}
10153
10154 instruct string_compareLU(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
10155 iRegI_R10 result, iRegP_R28 tmp1, iRegL_R29 tmp2, iRegL_R30 tmp3,
10156 rFlagsReg cr)
10157 %{
10158 predicate(!UseRVV && ((StrCompNode *)n)->encoding() == StrIntrinsicNode::LU);
10159 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10160 effect(KILL tmp1, KILL tmp2, KILL tmp3, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
10161
10162 format %{ "String Compare $str1, $cnt1, $str2, $cnt2 -> $result\t#@string_compareLU" %}
10163 ins_encode %{
10164 __ string_compare($str1$$Register, $str2$$Register,
10165 $cnt1$$Register, $cnt2$$Register, $result$$Register,
10166 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
10167 StrIntrinsicNode::LU);
10168 %}
10169 ins_pipe(pipe_class_memory);
10170 %}
10171
10172 instruct string_indexofUU(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
10173 iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3,
10174 iRegINoSp tmp4, iRegINoSp tmp5, iRegINoSp tmp6, rFlagsReg cr)
10175 %{
10176 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU);
10177 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
10178 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, TEMP_DEF result,
10179 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, TEMP tmp6, KILL cr);
10180
10181 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result (UU)" %}
10182 ins_encode %{
10183 __ string_indexof($str1$$Register, $str2$$Register,
10184 $cnt1$$Register, $cnt2$$Register,
10185 $tmp1$$Register, $tmp2$$Register,
10186 $tmp3$$Register, $tmp4$$Register,
10187 $tmp5$$Register, $tmp6$$Register,
10188 $result$$Register, StrIntrinsicNode::UU);
10189 %}
10190 ins_pipe(pipe_class_memory);
10191 %}
10192
10193 instruct string_indexofLL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
10194 iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3,
10195 iRegINoSp tmp4, iRegINoSp tmp5, iRegINoSp tmp6, rFlagsReg cr)
10196 %{
10197 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL);
10198 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
10199 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, TEMP_DEF result,
10200 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, TEMP tmp6, KILL cr);
10201
10202 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result (LL)" %}
10203 ins_encode %{
10204 __ string_indexof($str1$$Register, $str2$$Register,
10205 $cnt1$$Register, $cnt2$$Register,
10206 $tmp1$$Register, $tmp2$$Register,
10207 $tmp3$$Register, $tmp4$$Register,
10208 $tmp5$$Register, $tmp6$$Register,
10209 $result$$Register, StrIntrinsicNode::LL);
10210 %}
10211 ins_pipe(pipe_class_memory);
10212 %}
10213
10214 instruct string_indexofUL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
10215 iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3,
10216 iRegINoSp tmp4, iRegINoSp tmp5, iRegINoSp tmp6, rFlagsReg cr)
10217 %{
10218 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL);
10219 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
10220 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, TEMP_DEF result,
10221 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, TEMP tmp6, KILL cr);
10222 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result (UL)" %}
10223
10224 ins_encode %{
10225 __ string_indexof($str1$$Register, $str2$$Register,
10226 $cnt1$$Register, $cnt2$$Register,
10227 $tmp1$$Register, $tmp2$$Register,
10228 $tmp3$$Register, $tmp4$$Register,
10229 $tmp5$$Register, $tmp6$$Register,
10230 $result$$Register, StrIntrinsicNode::UL);
10231 %}
10232 ins_pipe(pipe_class_memory);
10233 %}
10234
10235 instruct string_indexof_conUU(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2,
10236 immI_le_4 int_cnt2, iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2,
10237 iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
10238 %{
10239 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU);
10240 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
10241 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, TEMP_DEF result,
10242 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
10243
10244 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result (UU)" %}
10245
10246 ins_encode %{
10247 int icnt2 = (int)$int_cnt2$$constant;
10248 __ string_indexof_linearscan($str1$$Register, $str2$$Register,
10249 $cnt1$$Register, zr,
10250 $tmp1$$Register, $tmp2$$Register,
10251 $tmp3$$Register, $tmp4$$Register,
10252 icnt2, $result$$Register, StrIntrinsicNode::UU);
10253 %}
10254 ins_pipe(pipe_class_memory);
10255 %}
10256
10257 instruct string_indexof_conLL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2,
10258 immI_le_4 int_cnt2, iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2,
10259 iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
10260 %{
10261 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL);
10262 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
10263 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, TEMP_DEF result,
10264 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
10265
10266 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result (LL)" %}
10267 ins_encode %{
10268 int icnt2 = (int)$int_cnt2$$constant;
10269 __ string_indexof_linearscan($str1$$Register, $str2$$Register,
10270 $cnt1$$Register, zr,
10271 $tmp1$$Register, $tmp2$$Register,
10272 $tmp3$$Register, $tmp4$$Register,
10273 icnt2, $result$$Register, StrIntrinsicNode::LL);
10274 %}
10275 ins_pipe(pipe_class_memory);
10276 %}
10277
10278 instruct string_indexof_conUL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2,
10279 immI_1 int_cnt2, iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2,
10280 iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
10281 %{
10282 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL);
10283 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
10284 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, TEMP_DEF result,
10285 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
10286
10287 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result (UL)" %}
10288 ins_encode %{
10289 int icnt2 = (int)$int_cnt2$$constant;
10290 __ string_indexof_linearscan($str1$$Register, $str2$$Register,
10291 $cnt1$$Register, zr,
10292 $tmp1$$Register, $tmp2$$Register,
10293 $tmp3$$Register, $tmp4$$Register,
10294 icnt2, $result$$Register, StrIntrinsicNode::UL);
10295 %}
10296 ins_pipe(pipe_class_memory);
10297 %}
10298
10299 instruct stringU_indexof_char(iRegP_R11 str1, iRegI_R12 cnt1, iRegI_R13 ch,
10300 iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2,
10301 iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
10302 %{
10303 match(Set result (StrIndexOfChar (Binary str1 cnt1) ch));
10304 predicate(!UseRVV && (((StrIndexOfCharNode*)n)->encoding() == StrIntrinsicNode::U));
10305 effect(USE_KILL str1, USE_KILL cnt1, USE_KILL ch, TEMP_DEF result,
10306 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
10307
10308 format %{ "StringUTF16 IndexOf char[] $str1, $cnt1, $ch -> $result" %}
10309 ins_encode %{
10310 __ string_indexof_char($str1$$Register, $cnt1$$Register, $ch$$Register,
10311 $result$$Register, $tmp1$$Register, $tmp2$$Register,
10312 $tmp3$$Register, $tmp4$$Register, false /* isU */);
10313 %}
10314 ins_pipe(pipe_class_memory);
10315 %}
10316
10317
10318 instruct stringL_indexof_char(iRegP_R11 str1, iRegI_R12 cnt1, iRegI_R13 ch,
10319 iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2,
10320 iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
10321 %{
10322 match(Set result (StrIndexOfChar (Binary str1 cnt1) ch));
10323 predicate(!UseRVV && (((StrIndexOfCharNode*)n)->encoding() == StrIntrinsicNode::L));
10324 effect(USE_KILL str1, USE_KILL cnt1, USE_KILL ch, TEMP_DEF result,
10325 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
10326
10327 format %{ "StringLatin1 IndexOf char[] $str1, $cnt1, $ch -> $result" %}
10328 ins_encode %{
10329 __ string_indexof_char($str1$$Register, $cnt1$$Register, $ch$$Register,
10330 $result$$Register, $tmp1$$Register, $tmp2$$Register,
10331 $tmp3$$Register, $tmp4$$Register, true /* isL */);
10332 %}
10333 ins_pipe(pipe_class_memory);
10334 %}
10335
10336 // clearing of an array
10337 instruct clearArray_reg_reg(iRegL_R29 cnt, iRegP_R28 base, iRegP_R30 tmp1,
10338 iRegP_R31 tmp2, rFlagsReg cr, Universe dummy)
10339 %{
10340 // temp registers must match the one used in StubGenerator::generate_zero_blocks()
10341 predicate(UseBlockZeroing || !UseRVV);
10342 match(Set dummy (ClearArray cnt base));
10343 effect(USE_KILL cnt, USE_KILL base, TEMP tmp1, TEMP tmp2, KILL cr);
10344
10345 ins_cost(4 * DEFAULT_COST);
10346 format %{ "ClearArray $cnt, $base\t#@clearArray_reg_reg" %}
10347
10348 ins_encode %{
10349 address tpc = __ zero_words($base$$Register, $cnt$$Register);
10350 if (tpc == nullptr) {
10351 ciEnv::current()->record_failure("CodeCache is full");
10352 return;
10353 }
10354 %}
10355
10356 ins_pipe(pipe_class_memory);
10357 %}
10358
10359 instruct clearArray_imm_reg(immL cnt, iRegP_R28 base, Universe dummy, rFlagsReg cr)
10360 %{
10361 predicate(!UseRVV && (uint64_t)n->in(2)->get_long()
10362 < (uint64_t)(BlockZeroingLowLimit >> LogBytesPerWord));
10363 match(Set dummy (ClearArray cnt base));
10364 effect(USE_KILL base, KILL cr);
10365
10366 ins_cost(4 * DEFAULT_COST);
10367 format %{ "ClearArray $cnt, $base\t#@clearArray_imm_reg" %}
10368
10369 ins_encode %{
10370 __ zero_words($base$$Register, (uint64_t)$cnt$$constant);
10371 %}
10372
10373 ins_pipe(pipe_class_memory);
10374 %}
10375
10376 instruct string_equalsL(iRegP_R11 str1, iRegP_R13 str2, iRegI_R14 cnt,
10377 iRegI_R10 result, rFlagsReg cr)
10378 %{
10379 predicate(!UseRVV && ((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::LL);
10380 match(Set result (StrEquals (Binary str1 str2) cnt));
10381 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL cr);
10382
10383 format %{ "String Equals $str1, $str2, $cnt -> $result\t#@string_equalsL" %}
10384 ins_encode %{
10385 // Count is in 8-bit bytes; non-Compact chars are 16 bits.
10386 __ string_equals($str1$$Register, $str2$$Register,
10387 $result$$Register, $cnt$$Register);
10388 %}
10389 ins_pipe(pipe_class_memory);
10390 %}
10391
10392 instruct array_equalsB(iRegP_R11 ary1, iRegP_R12 ary2, iRegI_R10 result,
10393 iRegP_R13 tmp1, iRegP_R14 tmp2, iRegP_R15 tmp3)
10394 %{
10395 predicate(!UseRVV && ((AryEqNode*)n)->encoding() == StrIntrinsicNode::LL);
10396 match(Set result (AryEq ary1 ary2));
10397 effect(USE_KILL ary1, USE_KILL ary2, TEMP tmp1, TEMP tmp2, TEMP tmp3);
10398
10399 format %{ "Array Equals $ary1, $ary2 -> $result\t#@array_equalsB // KILL all" %}
10400 ins_encode %{
10401 __ arrays_equals($ary1$$Register, $ary2$$Register,
10402 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
10403 $result$$Register, 1);
10404 %}
10405 ins_pipe(pipe_class_memory);
10406 %}
10407
10408 instruct array_equalsC(iRegP_R11 ary1, iRegP_R12 ary2, iRegI_R10 result,
10409 iRegP_R13 tmp1, iRegP_R14 tmp2, iRegP_R15 tmp3)
10410 %{
10411 predicate(!UseRVV && ((AryEqNode*)n)->encoding() == StrIntrinsicNode::UU);
10412 match(Set result (AryEq ary1 ary2));
10413 effect(USE_KILL ary1, USE_KILL ary2, TEMP tmp1, TEMP tmp2, TEMP tmp3);
10414
10415 format %{ "Array Equals $ary1, $ary2 -> $result\t#@array_equalsC // KILL all" %}
10416 ins_encode %{
10417 __ arrays_equals($ary1$$Register, $ary2$$Register,
10418 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
10419 $result$$Register, 2);
10420 %}
10421 ins_pipe(pipe_class_memory);
10422 %}
10423
10424 // fast ArraysSupport.vectorizedHashCode
10425 instruct arrays_hashcode(iRegP_R11 ary, iRegI_R12 cnt, iRegI_R10 result, immI basic_type,
10426 iRegLNoSp tmp1, iRegLNoSp tmp2,
10427 iRegLNoSp tmp3, iRegLNoSp tmp4,
10428 iRegLNoSp tmp5, iRegLNoSp tmp6, rFlagsReg cr)
10429 %{
10430 match(Set result (VectorizedHashCode (Binary ary cnt) (Binary result basic_type)));
10431 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, TEMP tmp6,
10432 USE_KILL ary, USE_KILL cnt, USE basic_type, KILL cr);
10433
10434 format %{ "Array HashCode array[] $ary,$cnt,$result,$basic_type -> $result // KILL all" %}
10435 ins_encode %{
10436 __ arrays_hashcode($ary$$Register, $cnt$$Register, $result$$Register,
10437 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
10438 $tmp4$$Register, $tmp5$$Register, $tmp6$$Register,
10439 (BasicType)$basic_type$$constant);
10440 %}
10441 ins_pipe(pipe_class_memory);
10442 %}
10443
10444 // ============================================================================
10445 // Safepoint Instructions
10446
10447 instruct safePoint(iRegP poll)
10448 %{
10449 match(SafePoint poll);
10450
10451 ins_cost(2 * LOAD_COST);
10452 format %{
10453 "lwu zr, [$poll]\t# Safepoint: poll for GC, #@safePoint"
10454 %}
10455 ins_encode %{
10456 __ read_polling_page(as_Register($poll$$reg), 0, relocInfo::poll_type);
10457 %}
10458 ins_pipe(pipe_serial); // ins_pipe(iload_reg_mem);
10459 %}
10460
10461 // ============================================================================
10462 // This name is KNOWN by the ADLC and cannot be changed.
10463 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
10464 // for this guy.
10465 instruct tlsLoadP(javaThread_RegP dst)
10466 %{
10467 match(Set dst (ThreadLocal));
10468
10469 ins_cost(0);
10470
10471 format %{ " -- \t// $dst=Thread::current(), empty, #@tlsLoadP" %}
10472
10473 size(0);
10474
10475 ins_encode( /*empty*/ );
10476
10477 ins_pipe(pipe_class_empty);
10478 %}
10479
10480 // inlined locking and unlocking
10481 // using t1 as the 'flag' register to bridge the BoolNode producers and consumers
10482 instruct cmpFastLock(rFlagsReg cr, iRegP object, iRegP box,
10483 iRegPNoSp tmp1, iRegPNoSp tmp2, iRegPNoSp tmp3, iRegPNoSp tmp4)
10484 %{
10485 predicate(LockingMode != LM_LIGHTWEIGHT);
10486 match(Set cr (FastLock object box));
10487 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4);
10488
10489 ins_cost(10 * DEFAULT_COST);
10490 format %{ "fastlock $object,$box\t! kills $tmp1,$tmp2,$tmp3,$tmp4 #@cmpFastLock" %}
10491
10492 ins_encode %{
10493 __ fast_lock($object$$Register, $box$$Register,
10494 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register);
10495 %}
10496
10497 ins_pipe(pipe_serial);
10498 %}
10499
10500 // using t1 as the 'flag' register to bridge the BoolNode producers and consumers
10501 instruct cmpFastUnlock(rFlagsReg cr, iRegP object, iRegP box, iRegPNoSp tmp1, iRegPNoSp tmp2)
10502 %{
10503 predicate(LockingMode != LM_LIGHTWEIGHT);
10504 match(Set cr (FastUnlock object box));
10505 effect(TEMP tmp1, TEMP tmp2);
10506
10507 ins_cost(10 * DEFAULT_COST);
10508 format %{ "fastunlock $object,$box\t! kills $tmp1, $tmp2, #@cmpFastUnlock" %}
10509
10510 ins_encode %{
10511 __ fast_unlock($object$$Register, $box$$Register, $tmp1$$Register, $tmp2$$Register);
10512 %}
10513
10514 ins_pipe(pipe_serial);
10515 %}
10516
10517 instruct cmpFastLockLightweight(rFlagsReg cr, iRegP object, iRegP box,
10518 iRegPNoSp tmp1, iRegPNoSp tmp2, iRegPNoSp tmp3, iRegPNoSp tmp4)
10519 %{
10520 predicate(LockingMode == LM_LIGHTWEIGHT);
10521 match(Set cr (FastLock object box));
10522 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4);
10523
10524 ins_cost(10 * DEFAULT_COST);
10525 format %{ "fastlock $object,$box\t! kills $tmp1,$tmp2,$tmp3,$tmp4 #@cmpFastLockLightweight" %}
10526
10527 ins_encode %{
10528 __ fast_lock_lightweight($object$$Register, $box$$Register,
10529 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register);
10530 %}
10531
10532 ins_pipe(pipe_serial);
10533 %}
10534
10535 instruct cmpFastUnlockLightweight(rFlagsReg cr, iRegP object, iRegP box,
10536 iRegPNoSp tmp1, iRegPNoSp tmp2, iRegPNoSp tmp3)
10537 %{
10538 predicate(LockingMode == LM_LIGHTWEIGHT);
10539 match(Set cr (FastUnlock object box));
10540 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3);
10541
10542 ins_cost(10 * DEFAULT_COST);
10543 format %{ "fastunlock $object,$box\t! kills $tmp1,$tmp2,$tmp3 #@cmpFastUnlockLightweight" %}
10544
10545 ins_encode %{
10546 __ fast_unlock_lightweight($object$$Register, $box$$Register,
10547 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
10548 %}
10549
10550 ins_pipe(pipe_serial);
10551 %}
10552
10553 // Tail Call; Jump from runtime stub to Java code.
10554 // Also known as an 'interprocedural jump'.
10555 // Target of jump will eventually return to caller.
10556 // TailJump below removes the return address.
10557 // Don't use fp for 'jump_target' because a MachEpilogNode has already been
10558 // emitted just above the TailCall which has reset fp to the caller state.
10559 instruct TailCalljmpInd(iRegPNoSpNoFp jump_target, inline_cache_RegP method_oop)
10560 %{
10561 match(TailCall jump_target method_oop);
10562
10563 ins_cost(BRANCH_COST);
10564
10565 format %{ "jalr $jump_target\t# $method_oop holds method oop, #@TailCalljmpInd." %}
10566
10567 ins_encode(riscv_enc_tail_call(jump_target));
10568
10569 ins_pipe(pipe_class_call);
10570 %}
10571
10572 instruct TailjmpInd(iRegPNoSpNoFp jump_target, iRegP_R10 ex_oop)
10573 %{
10574 match(TailJump jump_target ex_oop);
10575
10576 ins_cost(ALU_COST + BRANCH_COST);
10577
10578 format %{ "jalr $jump_target\t# $ex_oop holds exception oop, #@TailjmpInd." %}
10579
10580 ins_encode(riscv_enc_tail_jmp(jump_target));
10581
10582 ins_pipe(pipe_class_call);
10583 %}
10584
10585 // Forward exception.
10586 instruct ForwardExceptionjmp()
10587 %{
10588 match(ForwardException);
10589
10590 ins_cost(BRANCH_COST);
10591
10592 format %{ "j forward_exception_stub\t#@ForwardException" %}
10593
10594 ins_encode %{
10595 __ far_jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
10596 %}
10597
10598 ins_pipe(pipe_class_call);
10599 %}
10600
10601 // Create exception oop: created by stack-crawling runtime code.
10602 // Created exception is now available to this handler, and is setup
10603 // just prior to jumping to this handler. No code emitted.
10604 instruct CreateException(iRegP_R10 ex_oop)
10605 %{
10606 match(Set ex_oop (CreateEx));
10607
10608 ins_cost(0);
10609 format %{ " -- \t// exception oop; no code emitted, #@CreateException" %}
10610
10611 size(0);
10612
10613 ins_encode( /*empty*/ );
10614
10615 ins_pipe(pipe_class_empty);
10616 %}
10617
10618 // Rethrow exception: The exception oop will come in the first
10619 // argument position. Then JUMP (not call) to the rethrow stub code.
10620 instruct RethrowException()
10621 %{
10622 match(Rethrow);
10623
10624 ins_cost(BRANCH_COST);
10625
10626 format %{ "j rethrow_stub\t#@RethrowException" %}
10627
10628 ins_encode(riscv_enc_rethrow());
10629
10630 ins_pipe(pipe_class_call);
10631 %}
10632
10633 // Return Instruction
10634 // epilog node loads ret address into ra as part of frame pop
10635 instruct Ret()
10636 %{
10637 match(Return);
10638
10639 ins_cost(BRANCH_COST);
10640 format %{ "ret\t// return register, #@Ret" %}
10641
10642 ins_encode(riscv_enc_ret());
10643
10644 ins_pipe(pipe_branch);
10645 %}
10646
10647 // Die now.
10648 instruct ShouldNotReachHere() %{
10649 match(Halt);
10650
10651 ins_cost(BRANCH_COST);
10652
10653 format %{ "#@ShouldNotReachHere" %}
10654
10655 ins_encode %{
10656 if (is_reachable()) {
10657 __ stop(_halt_reason);
10658 }
10659 %}
10660
10661 ins_pipe(pipe_class_default);
10662 %}
10663
10664
10665 //----------PEEPHOLE RULES-----------------------------------------------------
10666 // These must follow all instruction definitions as they use the names
10667 // defined in the instructions definitions.
10668 //
10669 // peepmatch ( root_instr_name [preceding_instruction]* );
10670 //
10671 // peepconstraint %{
10672 // (instruction_number.operand_name relational_op instruction_number.operand_name
10673 // [, ...] );
10674 // // instruction numbers are zero-based using left to right order in peepmatch
10675 //
10676 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
10677 // // provide an instruction_number.operand_name for each operand that appears
10678 // // in the replacement instruction's match rule
10679 //
10680 // ---------VM FLAGS---------------------------------------------------------
10681 //
10682 // All peephole optimizations can be turned off using -XX:-OptoPeephole
10683 //
10684 // Each peephole rule is given an identifying number starting with zero and
10685 // increasing by one in the order seen by the parser. An individual peephole
10686 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
10687 // on the command-line.
10688 //
10689 // ---------CURRENT LIMITATIONS----------------------------------------------
10690 //
10691 // Only match adjacent instructions in same basic block
10692 // Only equality constraints
10693 // Only constraints between operands, not (0.dest_reg == RAX_enc)
10694 // Only one replacement instruction
10695 //
10696 //----------SMARTSPILL RULES---------------------------------------------------
10697 // These must follow all instruction definitions as they use the names
10698 // defined in the instructions definitions.
10699
10700 // Local Variables:
10701 // mode: c++
10702 // End: