1 //
2 // Copyright (c) 2003, 2025, Oracle and/or its affiliates. All rights reserved.
3 // Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
4 // Copyright (c) 2020, 2024, Huawei Technologies Co., Ltd. All rights reserved.
5 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
6 //
7 // This code is free software; you can redistribute it and/or modify it
8 // under the terms of the GNU General Public License version 2 only, as
9 // published by the Free Software Foundation.
10 //
11 // This code is distributed in the hope that it will be useful, but WITHOUT
12 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 // version 2 for more details (a copy is included in the LICENSE file that
15 // accompanied this code).
16 //
17 // You should have received a copy of the GNU General Public License version
18 // 2 along with this work; if not, write to the Free Software Foundation,
19 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
20 //
21 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
22 // or visit www.oracle.com if you need additional information or have any
23 // questions.
24 //
25 //
26
27 // RISCV Architecture Description File
28
29 //----------REGISTER DEFINITION BLOCK------------------------------------------
30 // This information is used by the matcher and the register allocator to
31 // describe individual registers and classes of registers within the target
32 // architecture.
33
34 register %{
35 //----------Architecture Description Register Definitions----------------------
36 // General Registers
37 // "reg_def" name ( register save type, C convention save type,
38 // ideal register type, encoding );
39 // Register Save Types:
40 //
41 // NS = No-Save: The register allocator assumes that these registers
42 // can be used without saving upon entry to the method, &
43 // that they do not need to be saved at call sites.
44 //
45 // SOC = Save-On-Call: The register allocator assumes that these registers
46 // can be used without saving upon entry to the method,
47 // but that they must be saved at call sites.
48 //
49 // SOE = Save-On-Entry: The register allocator assumes that these registers
50 // must be saved before using them upon entry to the
51 // method, but they do not need to be saved at call
52 // sites.
53 //
54 // AS = Always-Save: The register allocator assumes that these registers
55 // must be saved before using them upon entry to the
56 // method, & that they must be saved at call sites.
57 //
58 // Ideal Register Type is used to determine how to save & restore a
59 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
60 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
61 //
62 // The encoding number is the actual bit-pattern placed into the opcodes.
63
64 // We must define the 64 bit int registers in two 32 bit halves, the
65 // real lower register and a virtual upper half register. upper halves
66 // are used by the register allocator but are not actually supplied as
67 // operands to memory ops.
68 //
69 // follow the C1 compiler in making registers
70 //
71 // x7, x9-x17, x27-x31 volatile (caller save)
72 // x0-x4, x8, x23 system (no save, no allocate)
73 // x5-x6 non-allocatable (so we can use them as temporary regs)
74
75 //
76 // as regards Java usage. we don't use any callee save registers
77 // because this makes it difficult to de-optimise a frame (see comment
78 // in x86 implementation of Deoptimization::unwind_callee_save_values)
79 //
80
81 // General Registers
82
83 reg_def R0 ( NS, NS, Op_RegI, 0, x0->as_VMReg() ); // zr
84 reg_def R0_H ( NS, NS, Op_RegI, 0, x0->as_VMReg()->next() );
85 reg_def R1 ( NS, SOC, Op_RegI, 1, x1->as_VMReg() ); // ra
86 reg_def R1_H ( NS, SOC, Op_RegI, 1, x1->as_VMReg()->next() );
87 reg_def R2 ( NS, NS, Op_RegI, 2, x2->as_VMReg() ); // sp
88 reg_def R2_H ( NS, NS, Op_RegI, 2, x2->as_VMReg()->next() );
89 reg_def R3 ( NS, NS, Op_RegI, 3, x3->as_VMReg() ); // gp
90 reg_def R3_H ( NS, NS, Op_RegI, 3, x3->as_VMReg()->next() );
91 reg_def R4 ( NS, NS, Op_RegI, 4, x4->as_VMReg() ); // tp
92 reg_def R4_H ( NS, NS, Op_RegI, 4, x4->as_VMReg()->next() );
93 reg_def R7 ( SOC, SOC, Op_RegI, 7, x7->as_VMReg() );
94 reg_def R7_H ( SOC, SOC, Op_RegI, 7, x7->as_VMReg()->next() );
95 reg_def R8 ( NS, SOE, Op_RegI, 8, x8->as_VMReg() ); // fp
96 reg_def R8_H ( NS, SOE, Op_RegI, 8, x8->as_VMReg()->next() );
97 reg_def R9 ( SOC, SOE, Op_RegI, 9, x9->as_VMReg() );
98 reg_def R9_H ( SOC, SOE, Op_RegI, 9, x9->as_VMReg()->next() );
99 reg_def R10 ( SOC, SOC, Op_RegI, 10, x10->as_VMReg() );
100 reg_def R10_H ( SOC, SOC, Op_RegI, 10, x10->as_VMReg()->next());
101 reg_def R11 ( SOC, SOC, Op_RegI, 11, x11->as_VMReg() );
102 reg_def R11_H ( SOC, SOC, Op_RegI, 11, x11->as_VMReg()->next());
103 reg_def R12 ( SOC, SOC, Op_RegI, 12, x12->as_VMReg() );
104 reg_def R12_H ( SOC, SOC, Op_RegI, 12, x12->as_VMReg()->next());
105 reg_def R13 ( SOC, SOC, Op_RegI, 13, x13->as_VMReg() );
106 reg_def R13_H ( SOC, SOC, Op_RegI, 13, x13->as_VMReg()->next());
107 reg_def R14 ( SOC, SOC, Op_RegI, 14, x14->as_VMReg() );
108 reg_def R14_H ( SOC, SOC, Op_RegI, 14, x14->as_VMReg()->next());
109 reg_def R15 ( SOC, SOC, Op_RegI, 15, x15->as_VMReg() );
110 reg_def R15_H ( SOC, SOC, Op_RegI, 15, x15->as_VMReg()->next());
111 reg_def R16 ( SOC, SOC, Op_RegI, 16, x16->as_VMReg() );
112 reg_def R16_H ( SOC, SOC, Op_RegI, 16, x16->as_VMReg()->next());
113 reg_def R17 ( SOC, SOC, Op_RegI, 17, x17->as_VMReg() );
114 reg_def R17_H ( SOC, SOC, Op_RegI, 17, x17->as_VMReg()->next());
115 reg_def R18 ( SOC, SOE, Op_RegI, 18, x18->as_VMReg() );
116 reg_def R18_H ( SOC, SOE, Op_RegI, 18, x18->as_VMReg()->next());
117 reg_def R19 ( SOC, SOE, Op_RegI, 19, x19->as_VMReg() );
118 reg_def R19_H ( SOC, SOE, Op_RegI, 19, x19->as_VMReg()->next());
119 reg_def R20 ( SOC, SOE, Op_RegI, 20, x20->as_VMReg() ); // caller esp
120 reg_def R20_H ( SOC, SOE, Op_RegI, 20, x20->as_VMReg()->next());
121 reg_def R21 ( SOC, SOE, Op_RegI, 21, x21->as_VMReg() );
122 reg_def R21_H ( SOC, SOE, Op_RegI, 21, x21->as_VMReg()->next());
123 reg_def R22 ( SOC, SOE, Op_RegI, 22, x22->as_VMReg() );
124 reg_def R22_H ( SOC, SOE, Op_RegI, 22, x22->as_VMReg()->next());
125 reg_def R23 ( NS, SOE, Op_RegI, 23, x23->as_VMReg() ); // java thread
126 reg_def R23_H ( NS, SOE, Op_RegI, 23, x23->as_VMReg()->next());
127 reg_def R24 ( SOC, SOE, Op_RegI, 24, x24->as_VMReg() );
128 reg_def R24_H ( SOC, SOE, Op_RegI, 24, x24->as_VMReg()->next());
129 reg_def R25 ( SOC, SOE, Op_RegI, 25, x25->as_VMReg() );
130 reg_def R25_H ( SOC, SOE, Op_RegI, 25, x25->as_VMReg()->next());
131 reg_def R26 ( SOC, SOE, Op_RegI, 26, x26->as_VMReg() );
132 reg_def R26_H ( SOC, SOE, Op_RegI, 26, x26->as_VMReg()->next());
133 reg_def R27 ( SOC, SOE, Op_RegI, 27, x27->as_VMReg() ); // heapbase
134 reg_def R27_H ( SOC, SOE, Op_RegI, 27, x27->as_VMReg()->next());
135 reg_def R28 ( SOC, SOC, Op_RegI, 28, x28->as_VMReg() );
136 reg_def R28_H ( SOC, SOC, Op_RegI, 28, x28->as_VMReg()->next());
137 reg_def R29 ( SOC, SOC, Op_RegI, 29, x29->as_VMReg() );
138 reg_def R29_H ( SOC, SOC, Op_RegI, 29, x29->as_VMReg()->next());
139 reg_def R30 ( SOC, SOC, Op_RegI, 30, x30->as_VMReg() );
140 reg_def R30_H ( SOC, SOC, Op_RegI, 30, x30->as_VMReg()->next());
141 reg_def R31 ( SOC, SOC, Op_RegI, 31, x31->as_VMReg() );
142 reg_def R31_H ( SOC, SOC, Op_RegI, 31, x31->as_VMReg()->next());
143
144 // ----------------------------
145 // Float/Double Registers
146 // ----------------------------
147
148 // Double Registers
149
150 // The rules of ADL require that double registers be defined in pairs.
151 // Each pair must be two 32-bit values, but not necessarily a pair of
152 // single float registers. In each pair, ADLC-assigned register numbers
153 // must be adjacent, with the lower number even. Finally, when the
154 // CPU stores such a register pair to memory, the word associated with
155 // the lower ADLC-assigned number must be stored to the lower address.
156
157 // RISCV has 32 floating-point registers. Each can store a single
158 // or double precision floating-point value.
159
160 // for Java use float registers f0-f31 are always save on call whereas
161 // the platform ABI treats f8-f9 and f18-f27 as callee save). Other
162 // float registers are SOC as per the platform spec
163
164 reg_def F0 ( SOC, SOC, Op_RegF, 0, f0->as_VMReg() );
165 reg_def F0_H ( SOC, SOC, Op_RegF, 0, f0->as_VMReg()->next() );
166 reg_def F1 ( SOC, SOC, Op_RegF, 1, f1->as_VMReg() );
167 reg_def F1_H ( SOC, SOC, Op_RegF, 1, f1->as_VMReg()->next() );
168 reg_def F2 ( SOC, SOC, Op_RegF, 2, f2->as_VMReg() );
169 reg_def F2_H ( SOC, SOC, Op_RegF, 2, f2->as_VMReg()->next() );
170 reg_def F3 ( SOC, SOC, Op_RegF, 3, f3->as_VMReg() );
171 reg_def F3_H ( SOC, SOC, Op_RegF, 3, f3->as_VMReg()->next() );
172 reg_def F4 ( SOC, SOC, Op_RegF, 4, f4->as_VMReg() );
173 reg_def F4_H ( SOC, SOC, Op_RegF, 4, f4->as_VMReg()->next() );
174 reg_def F5 ( SOC, SOC, Op_RegF, 5, f5->as_VMReg() );
175 reg_def F5_H ( SOC, SOC, Op_RegF, 5, f5->as_VMReg()->next() );
176 reg_def F6 ( SOC, SOC, Op_RegF, 6, f6->as_VMReg() );
177 reg_def F6_H ( SOC, SOC, Op_RegF, 6, f6->as_VMReg()->next() );
178 reg_def F7 ( SOC, SOC, Op_RegF, 7, f7->as_VMReg() );
179 reg_def F7_H ( SOC, SOC, Op_RegF, 7, f7->as_VMReg()->next() );
180 reg_def F8 ( SOC, SOE, Op_RegF, 8, f8->as_VMReg() );
181 reg_def F8_H ( SOC, SOE, Op_RegF, 8, f8->as_VMReg()->next() );
182 reg_def F9 ( SOC, SOE, Op_RegF, 9, f9->as_VMReg() );
183 reg_def F9_H ( SOC, SOE, Op_RegF, 9, f9->as_VMReg()->next() );
184 reg_def F10 ( SOC, SOC, Op_RegF, 10, f10->as_VMReg() );
185 reg_def F10_H ( SOC, SOC, Op_RegF, 10, f10->as_VMReg()->next() );
186 reg_def F11 ( SOC, SOC, Op_RegF, 11, f11->as_VMReg() );
187 reg_def F11_H ( SOC, SOC, Op_RegF, 11, f11->as_VMReg()->next() );
188 reg_def F12 ( SOC, SOC, Op_RegF, 12, f12->as_VMReg() );
189 reg_def F12_H ( SOC, SOC, Op_RegF, 12, f12->as_VMReg()->next() );
190 reg_def F13 ( SOC, SOC, Op_RegF, 13, f13->as_VMReg() );
191 reg_def F13_H ( SOC, SOC, Op_RegF, 13, f13->as_VMReg()->next() );
192 reg_def F14 ( SOC, SOC, Op_RegF, 14, f14->as_VMReg() );
193 reg_def F14_H ( SOC, SOC, Op_RegF, 14, f14->as_VMReg()->next() );
194 reg_def F15 ( SOC, SOC, Op_RegF, 15, f15->as_VMReg() );
195 reg_def F15_H ( SOC, SOC, Op_RegF, 15, f15->as_VMReg()->next() );
196 reg_def F16 ( SOC, SOC, Op_RegF, 16, f16->as_VMReg() );
197 reg_def F16_H ( SOC, SOC, Op_RegF, 16, f16->as_VMReg()->next() );
198 reg_def F17 ( SOC, SOC, Op_RegF, 17, f17->as_VMReg() );
199 reg_def F17_H ( SOC, SOC, Op_RegF, 17, f17->as_VMReg()->next() );
200 reg_def F18 ( SOC, SOE, Op_RegF, 18, f18->as_VMReg() );
201 reg_def F18_H ( SOC, SOE, Op_RegF, 18, f18->as_VMReg()->next() );
202 reg_def F19 ( SOC, SOE, Op_RegF, 19, f19->as_VMReg() );
203 reg_def F19_H ( SOC, SOE, Op_RegF, 19, f19->as_VMReg()->next() );
204 reg_def F20 ( SOC, SOE, Op_RegF, 20, f20->as_VMReg() );
205 reg_def F20_H ( SOC, SOE, Op_RegF, 20, f20->as_VMReg()->next() );
206 reg_def F21 ( SOC, SOE, Op_RegF, 21, f21->as_VMReg() );
207 reg_def F21_H ( SOC, SOE, Op_RegF, 21, f21->as_VMReg()->next() );
208 reg_def F22 ( SOC, SOE, Op_RegF, 22, f22->as_VMReg() );
209 reg_def F22_H ( SOC, SOE, Op_RegF, 22, f22->as_VMReg()->next() );
210 reg_def F23 ( SOC, SOE, Op_RegF, 23, f23->as_VMReg() );
211 reg_def F23_H ( SOC, SOE, Op_RegF, 23, f23->as_VMReg()->next() );
212 reg_def F24 ( SOC, SOE, Op_RegF, 24, f24->as_VMReg() );
213 reg_def F24_H ( SOC, SOE, Op_RegF, 24, f24->as_VMReg()->next() );
214 reg_def F25 ( SOC, SOE, Op_RegF, 25, f25->as_VMReg() );
215 reg_def F25_H ( SOC, SOE, Op_RegF, 25, f25->as_VMReg()->next() );
216 reg_def F26 ( SOC, SOE, Op_RegF, 26, f26->as_VMReg() );
217 reg_def F26_H ( SOC, SOE, Op_RegF, 26, f26->as_VMReg()->next() );
218 reg_def F27 ( SOC, SOE, Op_RegF, 27, f27->as_VMReg() );
219 reg_def F27_H ( SOC, SOE, Op_RegF, 27, f27->as_VMReg()->next() );
220 reg_def F28 ( SOC, SOC, Op_RegF, 28, f28->as_VMReg() );
221 reg_def F28_H ( SOC, SOC, Op_RegF, 28, f28->as_VMReg()->next() );
222 reg_def F29 ( SOC, SOC, Op_RegF, 29, f29->as_VMReg() );
223 reg_def F29_H ( SOC, SOC, Op_RegF, 29, f29->as_VMReg()->next() );
224 reg_def F30 ( SOC, SOC, Op_RegF, 30, f30->as_VMReg() );
225 reg_def F30_H ( SOC, SOC, Op_RegF, 30, f30->as_VMReg()->next() );
226 reg_def F31 ( SOC, SOC, Op_RegF, 31, f31->as_VMReg() );
227 reg_def F31_H ( SOC, SOC, Op_RegF, 31, f31->as_VMReg()->next() );
228
229 // ----------------------------
230 // Vector Registers
231 // ----------------------------
232
233 // For RVV vector registers, we simply extend vector register size to 4
234 // 'logical' slots. This is nominally 128 bits but it actually covers
235 // all possible 'physical' RVV vector register lengths from 128 ~ 1024
236 // bits. The 'physical' RVV vector register length is detected during
237 // startup, so the register allocator is able to identify the correct
238 // number of bytes needed for an RVV spill/unspill.
239
240 reg_def V0 ( SOC, SOC, Op_VecA, 0, v0->as_VMReg() );
241 reg_def V0_H ( SOC, SOC, Op_VecA, 0, v0->as_VMReg()->next() );
242 reg_def V0_J ( SOC, SOC, Op_VecA, 0, v0->as_VMReg()->next(2) );
243 reg_def V0_K ( SOC, SOC, Op_VecA, 0, v0->as_VMReg()->next(3) );
244
245 reg_def V1 ( SOC, SOC, Op_VecA, 1, v1->as_VMReg() );
246 reg_def V1_H ( SOC, SOC, Op_VecA, 1, v1->as_VMReg()->next() );
247 reg_def V1_J ( SOC, SOC, Op_VecA, 1, v1->as_VMReg()->next(2) );
248 reg_def V1_K ( SOC, SOC, Op_VecA, 1, v1->as_VMReg()->next(3) );
249
250 reg_def V2 ( SOC, SOC, Op_VecA, 2, v2->as_VMReg() );
251 reg_def V2_H ( SOC, SOC, Op_VecA, 2, v2->as_VMReg()->next() );
252 reg_def V2_J ( SOC, SOC, Op_VecA, 2, v2->as_VMReg()->next(2) );
253 reg_def V2_K ( SOC, SOC, Op_VecA, 2, v2->as_VMReg()->next(3) );
254
255 reg_def V3 ( SOC, SOC, Op_VecA, 3, v3->as_VMReg() );
256 reg_def V3_H ( SOC, SOC, Op_VecA, 3, v3->as_VMReg()->next() );
257 reg_def V3_J ( SOC, SOC, Op_VecA, 3, v3->as_VMReg()->next(2) );
258 reg_def V3_K ( SOC, SOC, Op_VecA, 3, v3->as_VMReg()->next(3) );
259
260 reg_def V4 ( SOC, SOC, Op_VecA, 4, v4->as_VMReg() );
261 reg_def V4_H ( SOC, SOC, Op_VecA, 4, v4->as_VMReg()->next() );
262 reg_def V4_J ( SOC, SOC, Op_VecA, 4, v4->as_VMReg()->next(2) );
263 reg_def V4_K ( SOC, SOC, Op_VecA, 4, v4->as_VMReg()->next(3) );
264
265 reg_def V5 ( SOC, SOC, Op_VecA, 5, v5->as_VMReg() );
266 reg_def V5_H ( SOC, SOC, Op_VecA, 5, v5->as_VMReg()->next() );
267 reg_def V5_J ( SOC, SOC, Op_VecA, 5, v5->as_VMReg()->next(2) );
268 reg_def V5_K ( SOC, SOC, Op_VecA, 5, v5->as_VMReg()->next(3) );
269
270 reg_def V6 ( SOC, SOC, Op_VecA, 6, v6->as_VMReg() );
271 reg_def V6_H ( SOC, SOC, Op_VecA, 6, v6->as_VMReg()->next() );
272 reg_def V6_J ( SOC, SOC, Op_VecA, 6, v6->as_VMReg()->next(2) );
273 reg_def V6_K ( SOC, SOC, Op_VecA, 6, v6->as_VMReg()->next(3) );
274
275 reg_def V7 ( SOC, SOC, Op_VecA, 7, v7->as_VMReg() );
276 reg_def V7_H ( SOC, SOC, Op_VecA, 7, v7->as_VMReg()->next() );
277 reg_def V7_J ( SOC, SOC, Op_VecA, 7, v7->as_VMReg()->next(2) );
278 reg_def V7_K ( SOC, SOC, Op_VecA, 7, v7->as_VMReg()->next(3) );
279
280 reg_def V8 ( SOC, SOC, Op_VecA, 8, v8->as_VMReg() );
281 reg_def V8_H ( SOC, SOC, Op_VecA, 8, v8->as_VMReg()->next() );
282 reg_def V8_J ( SOC, SOC, Op_VecA, 8, v8->as_VMReg()->next(2) );
283 reg_def V8_K ( SOC, SOC, Op_VecA, 8, v8->as_VMReg()->next(3) );
284
285 reg_def V9 ( SOC, SOC, Op_VecA, 9, v9->as_VMReg() );
286 reg_def V9_H ( SOC, SOC, Op_VecA, 9, v9->as_VMReg()->next() );
287 reg_def V9_J ( SOC, SOC, Op_VecA, 9, v9->as_VMReg()->next(2) );
288 reg_def V9_K ( SOC, SOC, Op_VecA, 9, v9->as_VMReg()->next(3) );
289
290 reg_def V10 ( SOC, SOC, Op_VecA, 10, v10->as_VMReg() );
291 reg_def V10_H ( SOC, SOC, Op_VecA, 10, v10->as_VMReg()->next() );
292 reg_def V10_J ( SOC, SOC, Op_VecA, 10, v10->as_VMReg()->next(2) );
293 reg_def V10_K ( SOC, SOC, Op_VecA, 10, v10->as_VMReg()->next(3) );
294
295 reg_def V11 ( SOC, SOC, Op_VecA, 11, v11->as_VMReg() );
296 reg_def V11_H ( SOC, SOC, Op_VecA, 11, v11->as_VMReg()->next() );
297 reg_def V11_J ( SOC, SOC, Op_VecA, 11, v11->as_VMReg()->next(2) );
298 reg_def V11_K ( SOC, SOC, Op_VecA, 11, v11->as_VMReg()->next(3) );
299
300 reg_def V12 ( SOC, SOC, Op_VecA, 12, v12->as_VMReg() );
301 reg_def V12_H ( SOC, SOC, Op_VecA, 12, v12->as_VMReg()->next() );
302 reg_def V12_J ( SOC, SOC, Op_VecA, 12, v12->as_VMReg()->next(2) );
303 reg_def V12_K ( SOC, SOC, Op_VecA, 12, v12->as_VMReg()->next(3) );
304
305 reg_def V13 ( SOC, SOC, Op_VecA, 13, v13->as_VMReg() );
306 reg_def V13_H ( SOC, SOC, Op_VecA, 13, v13->as_VMReg()->next() );
307 reg_def V13_J ( SOC, SOC, Op_VecA, 13, v13->as_VMReg()->next(2) );
308 reg_def V13_K ( SOC, SOC, Op_VecA, 13, v13->as_VMReg()->next(3) );
309
310 reg_def V14 ( SOC, SOC, Op_VecA, 14, v14->as_VMReg() );
311 reg_def V14_H ( SOC, SOC, Op_VecA, 14, v14->as_VMReg()->next() );
312 reg_def V14_J ( SOC, SOC, Op_VecA, 14, v14->as_VMReg()->next(2) );
313 reg_def V14_K ( SOC, SOC, Op_VecA, 14, v14->as_VMReg()->next(3) );
314
315 reg_def V15 ( SOC, SOC, Op_VecA, 15, v15->as_VMReg() );
316 reg_def V15_H ( SOC, SOC, Op_VecA, 15, v15->as_VMReg()->next() );
317 reg_def V15_J ( SOC, SOC, Op_VecA, 15, v15->as_VMReg()->next(2) );
318 reg_def V15_K ( SOC, SOC, Op_VecA, 15, v15->as_VMReg()->next(3) );
319
320 reg_def V16 ( SOC, SOC, Op_VecA, 16, v16->as_VMReg() );
321 reg_def V16_H ( SOC, SOC, Op_VecA, 16, v16->as_VMReg()->next() );
322 reg_def V16_J ( SOC, SOC, Op_VecA, 16, v16->as_VMReg()->next(2) );
323 reg_def V16_K ( SOC, SOC, Op_VecA, 16, v16->as_VMReg()->next(3) );
324
325 reg_def V17 ( SOC, SOC, Op_VecA, 17, v17->as_VMReg() );
326 reg_def V17_H ( SOC, SOC, Op_VecA, 17, v17->as_VMReg()->next() );
327 reg_def V17_J ( SOC, SOC, Op_VecA, 17, v17->as_VMReg()->next(2) );
328 reg_def V17_K ( SOC, SOC, Op_VecA, 17, v17->as_VMReg()->next(3) );
329
330 reg_def V18 ( SOC, SOC, Op_VecA, 18, v18->as_VMReg() );
331 reg_def V18_H ( SOC, SOC, Op_VecA, 18, v18->as_VMReg()->next() );
332 reg_def V18_J ( SOC, SOC, Op_VecA, 18, v18->as_VMReg()->next(2) );
333 reg_def V18_K ( SOC, SOC, Op_VecA, 18, v18->as_VMReg()->next(3) );
334
335 reg_def V19 ( SOC, SOC, Op_VecA, 19, v19->as_VMReg() );
336 reg_def V19_H ( SOC, SOC, Op_VecA, 19, v19->as_VMReg()->next() );
337 reg_def V19_J ( SOC, SOC, Op_VecA, 19, v19->as_VMReg()->next(2) );
338 reg_def V19_K ( SOC, SOC, Op_VecA, 19, v19->as_VMReg()->next(3) );
339
340 reg_def V20 ( SOC, SOC, Op_VecA, 20, v20->as_VMReg() );
341 reg_def V20_H ( SOC, SOC, Op_VecA, 20, v20->as_VMReg()->next() );
342 reg_def V20_J ( SOC, SOC, Op_VecA, 20, v20->as_VMReg()->next(2) );
343 reg_def V20_K ( SOC, SOC, Op_VecA, 20, v20->as_VMReg()->next(3) );
344
345 reg_def V21 ( SOC, SOC, Op_VecA, 21, v21->as_VMReg() );
346 reg_def V21_H ( SOC, SOC, Op_VecA, 21, v21->as_VMReg()->next() );
347 reg_def V21_J ( SOC, SOC, Op_VecA, 21, v21->as_VMReg()->next(2) );
348 reg_def V21_K ( SOC, SOC, Op_VecA, 21, v21->as_VMReg()->next(3) );
349
350 reg_def V22 ( SOC, SOC, Op_VecA, 22, v22->as_VMReg() );
351 reg_def V22_H ( SOC, SOC, Op_VecA, 22, v22->as_VMReg()->next() );
352 reg_def V22_J ( SOC, SOC, Op_VecA, 22, v22->as_VMReg()->next(2) );
353 reg_def V22_K ( SOC, SOC, Op_VecA, 22, v22->as_VMReg()->next(3) );
354
355 reg_def V23 ( SOC, SOC, Op_VecA, 23, v23->as_VMReg() );
356 reg_def V23_H ( SOC, SOC, Op_VecA, 23, v23->as_VMReg()->next() );
357 reg_def V23_J ( SOC, SOC, Op_VecA, 23, v23->as_VMReg()->next(2) );
358 reg_def V23_K ( SOC, SOC, Op_VecA, 23, v23->as_VMReg()->next(3) );
359
360 reg_def V24 ( SOC, SOC, Op_VecA, 24, v24->as_VMReg() );
361 reg_def V24_H ( SOC, SOC, Op_VecA, 24, v24->as_VMReg()->next() );
362 reg_def V24_J ( SOC, SOC, Op_VecA, 24, v24->as_VMReg()->next(2) );
363 reg_def V24_K ( SOC, SOC, Op_VecA, 24, v24->as_VMReg()->next(3) );
364
365 reg_def V25 ( SOC, SOC, Op_VecA, 25, v25->as_VMReg() );
366 reg_def V25_H ( SOC, SOC, Op_VecA, 25, v25->as_VMReg()->next() );
367 reg_def V25_J ( SOC, SOC, Op_VecA, 25, v25->as_VMReg()->next(2) );
368 reg_def V25_K ( SOC, SOC, Op_VecA, 25, v25->as_VMReg()->next(3) );
369
370 reg_def V26 ( SOC, SOC, Op_VecA, 26, v26->as_VMReg() );
371 reg_def V26_H ( SOC, SOC, Op_VecA, 26, v26->as_VMReg()->next() );
372 reg_def V26_J ( SOC, SOC, Op_VecA, 26, v26->as_VMReg()->next(2) );
373 reg_def V26_K ( SOC, SOC, Op_VecA, 26, v26->as_VMReg()->next(3) );
374
375 reg_def V27 ( SOC, SOC, Op_VecA, 27, v27->as_VMReg() );
376 reg_def V27_H ( SOC, SOC, Op_VecA, 27, v27->as_VMReg()->next() );
377 reg_def V27_J ( SOC, SOC, Op_VecA, 27, v27->as_VMReg()->next(2) );
378 reg_def V27_K ( SOC, SOC, Op_VecA, 27, v27->as_VMReg()->next(3) );
379
380 reg_def V28 ( SOC, SOC, Op_VecA, 28, v28->as_VMReg() );
381 reg_def V28_H ( SOC, SOC, Op_VecA, 28, v28->as_VMReg()->next() );
382 reg_def V28_J ( SOC, SOC, Op_VecA, 28, v28->as_VMReg()->next(2) );
383 reg_def V28_K ( SOC, SOC, Op_VecA, 28, v28->as_VMReg()->next(3) );
384
385 reg_def V29 ( SOC, SOC, Op_VecA, 29, v29->as_VMReg() );
386 reg_def V29_H ( SOC, SOC, Op_VecA, 29, v29->as_VMReg()->next() );
387 reg_def V29_J ( SOC, SOC, Op_VecA, 29, v29->as_VMReg()->next(2) );
388 reg_def V29_K ( SOC, SOC, Op_VecA, 29, v29->as_VMReg()->next(3) );
389
390 reg_def V30 ( SOC, SOC, Op_VecA, 30, v30->as_VMReg() );
391 reg_def V30_H ( SOC, SOC, Op_VecA, 30, v30->as_VMReg()->next() );
392 reg_def V30_J ( SOC, SOC, Op_VecA, 30, v30->as_VMReg()->next(2) );
393 reg_def V30_K ( SOC, SOC, Op_VecA, 30, v30->as_VMReg()->next(3) );
394
395 reg_def V31 ( SOC, SOC, Op_VecA, 31, v31->as_VMReg() );
396 reg_def V31_H ( SOC, SOC, Op_VecA, 31, v31->as_VMReg()->next() );
397 reg_def V31_J ( SOC, SOC, Op_VecA, 31, v31->as_VMReg()->next(2) );
398 reg_def V31_K ( SOC, SOC, Op_VecA, 31, v31->as_VMReg()->next(3) );
399
400 // ----------------------------
401 // Special Registers
402 // ----------------------------
403
404 // On riscv, the physical flag register is missing, so we use t1 instead,
405 // to bridge the RegFlag semantics in share/opto
406
407 reg_def RFLAGS (SOC, SOC, Op_RegFlags, 6, x6->as_VMReg() );
408
409 // Specify priority of register selection within phases of register
410 // allocation. Highest priority is first. A useful heuristic is to
411 // give registers a low priority when they are required by machine
412 // instructions, like EAX and EDX on I486, and choose no-save registers
413 // before save-on-call, & save-on-call before save-on-entry. Registers
414 // which participate in fixed calling sequences should come last.
415 // Registers which are used as pairs must fall on an even boundary.
416
417 alloc_class chunk0(
418 // volatiles
419 R7, R7_H,
420 R28, R28_H,
421 R29, R29_H,
422 R30, R30_H,
423 R31, R31_H,
424
425 // arg registers
426 R10, R10_H,
427 R11, R11_H,
428 R12, R12_H,
429 R13, R13_H,
430 R14, R14_H,
431 R15, R15_H,
432 R16, R16_H,
433 R17, R17_H,
434
435 // non-volatiles
436 R9, R9_H,
437 R18, R18_H,
438 R19, R19_H,
439 R20, R20_H,
440 R21, R21_H,
441 R22, R22_H,
442 R24, R24_H,
443 R25, R25_H,
444 R26, R26_H,
445
446 // non-allocatable registers
447 R23, R23_H, // java thread
448 R27, R27_H, // heapbase
449 R4, R4_H, // thread
450 R8, R8_H, // fp
451 R0, R0_H, // zero
452 R1, R1_H, // ra
453 R2, R2_H, // sp
454 R3, R3_H, // gp
455 );
456
457 alloc_class chunk1(
458
459 // no save
460 F0, F0_H,
461 F1, F1_H,
462 F2, F2_H,
463 F3, F3_H,
464 F4, F4_H,
465 F5, F5_H,
466 F6, F6_H,
467 F7, F7_H,
468 F28, F28_H,
469 F29, F29_H,
470 F30, F30_H,
471 F31, F31_H,
472
473 // arg registers
474 F10, F10_H,
475 F11, F11_H,
476 F12, F12_H,
477 F13, F13_H,
478 F14, F14_H,
479 F15, F15_H,
480 F16, F16_H,
481 F17, F17_H,
482
483 // non-volatiles
484 F8, F8_H,
485 F9, F9_H,
486 F18, F18_H,
487 F19, F19_H,
488 F20, F20_H,
489 F21, F21_H,
490 F22, F22_H,
491 F23, F23_H,
492 F24, F24_H,
493 F25, F25_H,
494 F26, F26_H,
495 F27, F27_H,
496 );
497
498 alloc_class chunk2(
499 V0, V0_H, V0_J, V0_K,
500 V1, V1_H, V1_J, V1_K,
501 V2, V2_H, V2_J, V2_K,
502 V3, V3_H, V3_J, V3_K,
503 V4, V4_H, V4_J, V4_K,
504 V5, V5_H, V5_J, V5_K,
505 V6, V6_H, V6_J, V6_K,
506 V7, V7_H, V7_J, V7_K,
507 V8, V8_H, V8_J, V8_K,
508 V9, V9_H, V9_J, V9_K,
509 V10, V10_H, V10_J, V10_K,
510 V11, V11_H, V11_J, V11_K,
511 V12, V12_H, V12_J, V12_K,
512 V13, V13_H, V13_J, V13_K,
513 V14, V14_H, V14_J, V14_K,
514 V15, V15_H, V15_J, V15_K,
515 V16, V16_H, V16_J, V16_K,
516 V17, V17_H, V17_J, V17_K,
517 V18, V18_H, V18_J, V18_K,
518 V19, V19_H, V19_J, V19_K,
519 V20, V20_H, V20_J, V20_K,
520 V21, V21_H, V21_J, V21_K,
521 V22, V22_H, V22_J, V22_K,
522 V23, V23_H, V23_J, V23_K,
523 V24, V24_H, V24_J, V24_K,
524 V25, V25_H, V25_J, V25_K,
525 V26, V26_H, V26_J, V26_K,
526 V27, V27_H, V27_J, V27_K,
527 V28, V28_H, V28_J, V28_K,
528 V29, V29_H, V29_J, V29_K,
529 V30, V30_H, V30_J, V30_K,
530 V31, V31_H, V31_J, V31_K,
531 );
532
533 alloc_class chunk3(RFLAGS);
534
535 //----------Architecture Description Register Classes--------------------------
536 // Several register classes are automatically defined based upon information in
537 // this architecture description.
538 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
539 // 2) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
540 //
541
542 // Class for all 32 bit general purpose registers
543 reg_class all_reg32(
544 R0,
545 R1,
546 R2,
547 R3,
548 R4,
549 R7,
550 R8,
551 R9,
552 R10,
553 R11,
554 R12,
555 R13,
556 R14,
557 R15,
558 R16,
559 R17,
560 R18,
561 R19,
562 R20,
563 R21,
564 R22,
565 R23,
566 R24,
567 R25,
568 R26,
569 R27,
570 R28,
571 R29,
572 R30,
573 R31
574 );
575
576 // Class for any 32 bit integer registers (excluding zr)
577 reg_class any_reg32 %{
578 return _ANY_REG32_mask;
579 %}
580
581 // Singleton class for R10 int register
582 reg_class int_r10_reg(R10);
583
584 // Singleton class for R12 int register
585 reg_class int_r12_reg(R12);
586
587 // Singleton class for R13 int register
588 reg_class int_r13_reg(R13);
589
590 // Singleton class for R14 int register
591 reg_class int_r14_reg(R14);
592
593 // Class for all long integer registers
594 reg_class all_reg(
595 R0, R0_H,
596 R1, R1_H,
597 R2, R2_H,
598 R3, R3_H,
599 R4, R4_H,
600 R7, R7_H,
601 R8, R8_H,
602 R9, R9_H,
603 R10, R10_H,
604 R11, R11_H,
605 R12, R12_H,
606 R13, R13_H,
607 R14, R14_H,
608 R15, R15_H,
609 R16, R16_H,
610 R17, R17_H,
611 R18, R18_H,
612 R19, R19_H,
613 R20, R20_H,
614 R21, R21_H,
615 R22, R22_H,
616 R23, R23_H,
617 R24, R24_H,
618 R25, R25_H,
619 R26, R26_H,
620 R27, R27_H,
621 R28, R28_H,
622 R29, R29_H,
623 R30, R30_H,
624 R31, R31_H
625 );
626
627 // Class for all long integer registers (excluding zr)
628 reg_class any_reg %{
629 return _ANY_REG_mask;
630 %}
631
632 // Class for non-allocatable 32 bit registers
633 reg_class non_allocatable_reg32(
634 R0, // zr
635 R1, // ra
636 R2, // sp
637 R3, // gp
638 R4, // tp
639 R23 // java thread
640 );
641
642 // Class for non-allocatable 64 bit registers
643 reg_class non_allocatable_reg(
644 R0, R0_H, // zr
645 R1, R1_H, // ra
646 R2, R2_H, // sp
647 R3, R3_H, // gp
648 R4, R4_H, // tp
649 R23, R23_H // java thread
650 );
651
652 // Class for all non-special integer registers
653 reg_class no_special_reg32 %{
654 return _NO_SPECIAL_REG32_mask;
655 %}
656
657 // Class for all non-special long integer registers
658 reg_class no_special_reg %{
659 return _NO_SPECIAL_REG_mask;
660 %}
661
662 reg_class ptr_reg %{
663 return _PTR_REG_mask;
664 %}
665
666 // Class for all non_special pointer registers
667 reg_class no_special_ptr_reg %{
668 return _NO_SPECIAL_PTR_REG_mask;
669 %}
670
671 // Class for all non_special pointer registers (excluding fp)
672 reg_class no_special_no_fp_ptr_reg %{
673 return _NO_SPECIAL_NO_FP_PTR_REG_mask;
674 %}
675
676 // Class for 64 bit register r10
677 reg_class r10_reg(
678 R10, R10_H
679 );
680
681 // Class for 64 bit register r11
682 reg_class r11_reg(
683 R11, R11_H
684 );
685
686 // Class for 64 bit register r12
687 reg_class r12_reg(
688 R12, R12_H
689 );
690
691 // Class for 64 bit register r13
692 reg_class r13_reg(
693 R13, R13_H
694 );
695
696 // Class for 64 bit register r14
697 reg_class r14_reg(
698 R14, R14_H
699 );
700
701 // Class for 64 bit register r15
702 reg_class r15_reg(
703 R15, R15_H
704 );
705
706 // Class for 64 bit register r16
707 reg_class r16_reg(
708 R16, R16_H
709 );
710
711 // Class for method register
712 reg_class method_reg(
713 R31, R31_H
714 );
715
716 // Class for java thread register
717 reg_class java_thread_reg(
718 R23, R23_H
719 );
720
721 reg_class r28_reg(
722 R28, R28_H
723 );
724
725 reg_class r29_reg(
726 R29, R29_H
727 );
728
729 reg_class r30_reg(
730 R30, R30_H
731 );
732
733 reg_class r31_reg(
734 R31, R31_H
735 );
736
737 // Class for zero registesr
738 reg_class zr_reg(
739 R0, R0_H
740 );
741
742 // Class for thread register
743 reg_class thread_reg(
744 R4, R4_H
745 );
746
747 // Class for frame pointer register
748 reg_class fp_reg(
749 R8, R8_H
750 );
751
752 // Class for link register
753 reg_class ra_reg(
754 R1, R1_H
755 );
756
757 // Class for long sp register
758 reg_class sp_reg(
759 R2, R2_H
760 );
761
762 // Class for all float registers
763 reg_class float_reg(
764 F0,
765 F1,
766 F2,
767 F3,
768 F4,
769 F5,
770 F6,
771 F7,
772 F8,
773 F9,
774 F10,
775 F11,
776 F12,
777 F13,
778 F14,
779 F15,
780 F16,
781 F17,
782 F18,
783 F19,
784 F20,
785 F21,
786 F22,
787 F23,
788 F24,
789 F25,
790 F26,
791 F27,
792 F28,
793 F29,
794 F30,
795 F31
796 );
797
798 // Double precision float registers have virtual `high halves' that
799 // are needed by the allocator.
800 // Class for all double registers
801 reg_class double_reg(
802 F0, F0_H,
803 F1, F1_H,
804 F2, F2_H,
805 F3, F3_H,
806 F4, F4_H,
807 F5, F5_H,
808 F6, F6_H,
809 F7, F7_H,
810 F8, F8_H,
811 F9, F9_H,
812 F10, F10_H,
813 F11, F11_H,
814 F12, F12_H,
815 F13, F13_H,
816 F14, F14_H,
817 F15, F15_H,
818 F16, F16_H,
819 F17, F17_H,
820 F18, F18_H,
821 F19, F19_H,
822 F20, F20_H,
823 F21, F21_H,
824 F22, F22_H,
825 F23, F23_H,
826 F24, F24_H,
827 F25, F25_H,
828 F26, F26_H,
829 F27, F27_H,
830 F28, F28_H,
831 F29, F29_H,
832 F30, F30_H,
833 F31, F31_H
834 );
835
836 // Class for RVV vector registers
837 // Note: v0, v30 and v31 are used as mask registers.
838 reg_class vectora_reg(
839 V1, V1_H, V1_J, V1_K,
840 V2, V2_H, V2_J, V2_K,
841 V3, V3_H, V3_J, V3_K,
842 V4, V4_H, V4_J, V4_K,
843 V5, V5_H, V5_J, V5_K,
844 V6, V6_H, V6_J, V6_K,
845 V7, V7_H, V7_J, V7_K,
846 V8, V8_H, V8_J, V8_K,
847 V9, V9_H, V9_J, V9_K,
848 V10, V10_H, V10_J, V10_K,
849 V11, V11_H, V11_J, V11_K,
850 V12, V12_H, V12_J, V12_K,
851 V13, V13_H, V13_J, V13_K,
852 V14, V14_H, V14_J, V14_K,
853 V15, V15_H, V15_J, V15_K,
854 V16, V16_H, V16_J, V16_K,
855 V17, V17_H, V17_J, V17_K,
856 V18, V18_H, V18_J, V18_K,
857 V19, V19_H, V19_J, V19_K,
858 V20, V20_H, V20_J, V20_K,
859 V21, V21_H, V21_J, V21_K,
860 V22, V22_H, V22_J, V22_K,
861 V23, V23_H, V23_J, V23_K,
862 V24, V24_H, V24_J, V24_K,
863 V25, V25_H, V25_J, V25_K,
864 V26, V26_H, V26_J, V26_K,
865 V27, V27_H, V27_J, V27_K,
866 V28, V28_H, V28_J, V28_K,
867 V29, V29_H, V29_J, V29_K
868 );
869
870 // Class for 64 bit register f0
871 reg_class f0_reg(
872 F0, F0_H
873 );
874
875 // Class for 64 bit register f1
876 reg_class f1_reg(
877 F1, F1_H
878 );
879
880 // Class for 64 bit register f2
881 reg_class f2_reg(
882 F2, F2_H
883 );
884
885 // Class for 64 bit register f3
886 reg_class f3_reg(
887 F3, F3_H
888 );
889
890 // class for vector register v1
891 reg_class v1_reg(
892 V1, V1_H, V1_J, V1_K
893 );
894
895 // class for vector register v2
896 reg_class v2_reg(
897 V2, V2_H, V2_J, V2_K
898 );
899
900 // class for vector register v3
901 reg_class v3_reg(
902 V3, V3_H, V3_J, V3_K
903 );
904
905 // class for vector register v4
906 reg_class v4_reg(
907 V4, V4_H, V4_J, V4_K
908 );
909
910 // class for vector register v5
911 reg_class v5_reg(
912 V5, V5_H, V5_J, V5_K
913 );
914
915 // class for vector register v6
916 reg_class v6_reg(
917 V6, V6_H, V6_J, V6_K
918 );
919
920 // class for vector register v7
921 reg_class v7_reg(
922 V7, V7_H, V7_J, V7_K
923 );
924
925 // class for vector register v8
926 reg_class v8_reg(
927 V8, V8_H, V8_J, V8_K
928 );
929
930 // class for vector register v9
931 reg_class v9_reg(
932 V9, V9_H, V9_J, V9_K
933 );
934
935 // class for vector register v10
936 reg_class v10_reg(
937 V10, V10_H, V10_J, V10_K
938 );
939
940 // class for vector register v11
941 reg_class v11_reg(
942 V11, V11_H, V11_J, V11_K
943 );
944
945 // class for condition codes
946 reg_class reg_flags(RFLAGS);
947
948 // Class for RVV v0 mask register
949 // https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#53-vector-masking
950 // The mask value used to control execution of a masked vector
951 // instruction is always supplied by vector register v0.
952 reg_class vmask_reg_v0 (
953 V0
954 );
955
956 // Class for RVV mask registers
957 // We need two more vmask registers to do the vector mask logical ops,
958 // so define v30, v31 as mask register too.
959 reg_class vmask_reg (
960 V0,
961 V30,
962 V31
963 );
964 %}
965
966 //----------DEFINITION BLOCK---------------------------------------------------
967 // Define name --> value mappings to inform the ADLC of an integer valued name
968 // Current support includes integer values in the range [0, 0x7FFFFFFF]
969 // Format:
970 // int_def <name> ( <int_value>, <expression>);
971 // Generated Code in ad_<arch>.hpp
972 // #define <name> (<expression>)
973 // // value == <int_value>
974 // Generated code in ad_<arch>.cpp adlc_verification()
975 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
976 //
977
978 // we follow the ppc-aix port in using a simple cost model which ranks
979 // register operations as cheap, memory ops as more expensive and
980 // branches as most expensive. the first two have a low as well as a
981 // normal cost. huge cost appears to be a way of saying don't do
982 // something
983
984 definitions %{
985 // The default cost (of a register move instruction).
986 int_def DEFAULT_COST ( 100, 100);
987 int_def ALU_COST ( 100, 1 * DEFAULT_COST); // unknown, const, arith, shift, slt,
988 // multi, auipc, nop, logical, move
989 int_def LOAD_COST ( 300, 3 * DEFAULT_COST); // load, fpload
990 int_def STORE_COST ( 100, 1 * DEFAULT_COST); // store, fpstore
991 int_def XFER_COST ( 300, 3 * DEFAULT_COST); // mfc, mtc, fcvt, fmove, fcmp
992 int_def FMVX_COST ( 100, 1 * DEFAULT_COST); // shuffles with no conversion
993 int_def BRANCH_COST ( 200, 2 * DEFAULT_COST); // branch, jmp, call
994 int_def IMUL_COST ( 1000, 10 * DEFAULT_COST); // imul
995 int_def IDIVSI_COST ( 3400, 34 * DEFAULT_COST); // idivsi
996 int_def IDIVDI_COST ( 6600, 66 * DEFAULT_COST); // idivdi
997 int_def FMUL_SINGLE_COST ( 500, 5 * DEFAULT_COST); // fmul, fmadd
998 int_def FMUL_DOUBLE_COST ( 700, 7 * DEFAULT_COST); // fmul, fmadd
999 int_def FDIV_COST ( 2000, 20 * DEFAULT_COST); // fdiv
1000 int_def FSQRT_COST ( 2500, 25 * DEFAULT_COST); // fsqrt
1001 int_def VOLATILE_REF_COST ( 1000, 10 * DEFAULT_COST);
1002 int_def CACHE_MISS_COST ( 2000, 20 * DEFAULT_COST); // typicall cache miss penalty
1003 %}
1004
1005
1006
1007 //----------SOURCE BLOCK-------------------------------------------------------
1008 // This is a block of C++ code which provides values, functions, and
1009 // definitions necessary in the rest of the architecture description
1010
1011 source_hpp %{
1012
1013 #include "asm/macroAssembler.hpp"
1014 #include "gc/shared/barrierSetAssembler.hpp"
1015 #include "gc/shared/cardTable.hpp"
1016 #include "gc/shared/cardTableBarrierSet.hpp"
1017 #include "gc/shared/collectedHeap.hpp"
1018 #include "opto/addnode.hpp"
1019 #include "opto/convertnode.hpp"
1020 #include "runtime/objectMonitor.hpp"
1021
1022 extern RegMask _ANY_REG32_mask;
1023 extern RegMask _ANY_REG_mask;
1024 extern RegMask _PTR_REG_mask;
1025 extern RegMask _NO_SPECIAL_REG32_mask;
1026 extern RegMask _NO_SPECIAL_REG_mask;
1027 extern RegMask _NO_SPECIAL_PTR_REG_mask;
1028 extern RegMask _NO_SPECIAL_NO_FP_PTR_REG_mask;
1029
1030 class CallStubImpl {
1031
1032 //--------------------------------------------------------------
1033 //---< Used for optimization in Compile::shorten_branches >---
1034 //--------------------------------------------------------------
1035
1036 public:
1037 // Size of call trampoline stub.
1038 static uint size_call_trampoline() {
1039 return 0; // no call trampolines on this platform
1040 }
1041
1042 // number of relocations needed by a call trampoline stub
1043 static uint reloc_call_trampoline() {
1044 return 0; // no call trampolines on this platform
1045 }
1046 };
1047
1048 class HandlerImpl {
1049
1050 public:
1051
1052 static int emit_deopt_handler(C2_MacroAssembler* masm);
1053
1054 static uint size_deopt_handler() {
1055 // count far call + j
1056 return NativeInstruction::instruction_size + MacroAssembler::far_branch_size();
1057 }
1058 };
1059
1060 class Node::PD {
1061 public:
1062 enum NodeFlags {
1063 _last_flag = Node::_last_flag
1064 };
1065 };
1066
1067 bool is_CAS(int opcode, bool maybe_volatile);
1068
1069 // predicate controlling translation of CompareAndSwapX
1070 bool needs_acquiring_load_reserved(const Node *load);
1071
1072 // predicate controlling addressing modes
1073 bool size_fits_all_mem_uses(AddPNode* addp, int shift);
1074 %}
1075
1076 source %{
1077
1078 // Derived RegMask with conditionally allocatable registers
1079
1080 RegMask _ANY_REG32_mask;
1081 RegMask _ANY_REG_mask;
1082 RegMask _PTR_REG_mask;
1083 RegMask _NO_SPECIAL_REG32_mask;
1084 RegMask _NO_SPECIAL_REG_mask;
1085 RegMask _NO_SPECIAL_PTR_REG_mask;
1086 RegMask _NO_SPECIAL_NO_FP_PTR_REG_mask;
1087
1088 void reg_mask_init() {
1089
1090 _ANY_REG32_mask.assignFrom(_ALL_REG32_mask);
1091 _ANY_REG32_mask.remove(OptoReg::as_OptoReg(x0->as_VMReg()));
1092
1093 _ANY_REG_mask.assignFrom(_ALL_REG_mask);
1094 _ANY_REG_mask.subtract(_ZR_REG_mask);
1095
1096 _PTR_REG_mask.assignFrom(_ALL_REG_mask);
1097 _PTR_REG_mask.subtract(_ZR_REG_mask);
1098
1099 _NO_SPECIAL_REG32_mask.assignFrom(_ALL_REG32_mask);
1100 _NO_SPECIAL_REG32_mask.subtract(_NON_ALLOCATABLE_REG32_mask);
1101
1102 _NO_SPECIAL_REG_mask.assignFrom(_ALL_REG_mask);
1103 _NO_SPECIAL_REG_mask.subtract(_NON_ALLOCATABLE_REG_mask);
1104
1105 _NO_SPECIAL_PTR_REG_mask.assignFrom(_ALL_REG_mask);
1106 _NO_SPECIAL_PTR_REG_mask.subtract(_NON_ALLOCATABLE_REG_mask);
1107
1108 // x27 is not allocatable when compressed oops is on
1109 if (UseCompressedOops) {
1110 _NO_SPECIAL_REG32_mask.remove(OptoReg::as_OptoReg(x27->as_VMReg()));
1111 _NO_SPECIAL_REG_mask.remove(OptoReg::as_OptoReg(x27->as_VMReg()));
1112 _NO_SPECIAL_PTR_REG_mask.remove(OptoReg::as_OptoReg(x27->as_VMReg()));
1113 }
1114
1115 // x8 is not allocatable when PreserveFramePointer is on
1116 if (PreserveFramePointer) {
1117 _NO_SPECIAL_REG32_mask.remove(OptoReg::as_OptoReg(x8->as_VMReg()));
1118 _NO_SPECIAL_REG_mask.remove(OptoReg::as_OptoReg(x8->as_VMReg()));
1119 _NO_SPECIAL_PTR_REG_mask.remove(OptoReg::as_OptoReg(x8->as_VMReg()));
1120 }
1121
1122 _NO_SPECIAL_NO_FP_PTR_REG_mask.assignFrom(_NO_SPECIAL_PTR_REG_mask);
1123 _NO_SPECIAL_NO_FP_PTR_REG_mask.remove(OptoReg::as_OptoReg(x8->as_VMReg()));
1124 }
1125
1126 void PhaseOutput::pd_perform_mach_node_analysis() {
1127 }
1128
1129 int MachNode::pd_alignment_required() const {
1130 return 1;
1131 }
1132
1133 int MachNode::compute_padding(int current_offset) const {
1134 return 0;
1135 }
1136
1137 // is_CAS(int opcode, bool maybe_volatile)
1138 //
1139 // return true if opcode is one of the possible CompareAndSwapX
1140 // values otherwise false.
1141 bool is_CAS(int opcode, bool maybe_volatile)
1142 {
1143 switch (opcode) {
1144 // We handle these
1145 case Op_CompareAndSwapI:
1146 case Op_CompareAndSwapL:
1147 case Op_CompareAndSwapP:
1148 case Op_CompareAndSwapN:
1149 case Op_ShenandoahCompareAndSwapP:
1150 case Op_ShenandoahCompareAndSwapN:
1151 case Op_CompareAndSwapB:
1152 case Op_CompareAndSwapS:
1153 case Op_GetAndSetI:
1154 case Op_GetAndSetL:
1155 case Op_GetAndSetP:
1156 case Op_GetAndSetN:
1157 case Op_GetAndAddI:
1158 case Op_GetAndAddL:
1159 return true;
1160 case Op_CompareAndExchangeI:
1161 case Op_CompareAndExchangeN:
1162 case Op_CompareAndExchangeB:
1163 case Op_CompareAndExchangeS:
1164 case Op_CompareAndExchangeL:
1165 case Op_CompareAndExchangeP:
1166 case Op_WeakCompareAndSwapB:
1167 case Op_WeakCompareAndSwapS:
1168 case Op_WeakCompareAndSwapI:
1169 case Op_WeakCompareAndSwapL:
1170 case Op_WeakCompareAndSwapP:
1171 case Op_WeakCompareAndSwapN:
1172 case Op_ShenandoahWeakCompareAndSwapP:
1173 case Op_ShenandoahWeakCompareAndSwapN:
1174 case Op_ShenandoahCompareAndExchangeP:
1175 case Op_ShenandoahCompareAndExchangeN:
1176 return maybe_volatile;
1177 default:
1178 return false;
1179 }
1180 }
1181
1182 constexpr uint64_t MAJIK_DWORD = 0xabbaabbaabbaabbaull;
1183
1184 // predicate controlling translation of CAS
1185 //
1186 // returns true if CAS needs to use an acquiring load otherwise false
1187 bool needs_acquiring_load_reserved(const Node *n)
1188 {
1189 assert(n != nullptr && is_CAS(n->Opcode(), true), "expecting a compare and swap");
1190
1191 LoadStoreNode* ldst = n->as_LoadStore();
1192 if (n != nullptr && is_CAS(n->Opcode(), false)) {
1193 assert(ldst != nullptr && ldst->trailing_membar() != nullptr, "expected trailing membar");
1194 } else {
1195 return ldst != nullptr && ldst->trailing_membar() != nullptr;
1196 }
1197 // so we can just return true here
1198 return true;
1199 }
1200 #define __ masm->
1201
1202 // advance declarations for helper functions to convert register
1203 // indices to register objects
1204
1205 // the ad file has to provide implementations of certain methods
1206 // expected by the generic code
1207 //
1208 // REQUIRED FUNCTIONALITY
1209
1210 //=============================================================================
1211
1212 // !!!!! Special hack to get all types of calls to specify the byte offset
1213 // from the start of the call to the point where the return address
1214 // will point.
1215
1216 int MachCallStaticJavaNode::ret_addr_offset()
1217 {
1218 return 3 * NativeInstruction::instruction_size; // auipc + ld + jalr
1219 }
1220
1221 int MachCallDynamicJavaNode::ret_addr_offset()
1222 {
1223 return NativeMovConstReg::movptr2_instruction_size + (3 * NativeInstruction::instruction_size); // movptr2, auipc + ld + jal
1224 }
1225
1226 int MachCallRuntimeNode::ret_addr_offset() {
1227 // For address inside the code cache the call will be:
1228 // auipc + jalr
1229 // For real runtime callouts it will be 8 instructions
1230 // see riscv_enc_java_to_runtime
1231 // la(t0, retaddr) -> auipc + addi
1232 // sd(t0, Address(xthread, JavaThread::last_Java_pc_offset())) -> sd
1233 // movptr(t1, addr, offset, t0) -> lui + lui + slli + add
1234 // jalr(t1, offset) -> jalr
1235 if (CodeCache::contains(_entry_point)) {
1236 return 2 * NativeInstruction::instruction_size;
1237 } else {
1238 return 8 * NativeInstruction::instruction_size;
1239 }
1240 }
1241
1242 //
1243 // Compute padding required for nodes which need alignment
1244 //
1245
1246 // With RVC a call instruction may get 2-byte aligned.
1247 // The address of the call instruction needs to be 4-byte aligned to
1248 // ensure that it does not span a cache line so that it can be patched.
1249 int CallStaticJavaDirectNode::compute_padding(int current_offset) const
1250 {
1251 // to make sure the address of jal 4-byte aligned.
1252 return align_up(current_offset, alignment_required()) - current_offset;
1253 }
1254
1255 // With RVC a call instruction may get 2-byte aligned.
1256 // The address of the call instruction needs to be 4-byte aligned to
1257 // ensure that it does not span a cache line so that it can be patched.
1258 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const
1259 {
1260 // skip the movptr2 in MacroAssembler::ic_call():
1261 // lui, lui, slli, add, addi
1262 // Though movptr2() has already 4-byte aligned with or without RVC,
1263 // We need to prevent from further changes by explicitly calculating the size.
1264 current_offset += NativeMovConstReg::movptr2_instruction_size;
1265 // to make sure the address of jal 4-byte aligned.
1266 return align_up(current_offset, alignment_required()) - current_offset;
1267 }
1268
1269 int CallRuntimeDirectNode::compute_padding(int current_offset) const
1270 {
1271 return align_up(current_offset, alignment_required()) - current_offset;
1272 }
1273
1274 int CallLeafDirectNode::compute_padding(int current_offset) const
1275 {
1276 return align_up(current_offset, alignment_required()) - current_offset;
1277 }
1278
1279 int CallLeafDirectVectorNode::compute_padding(int current_offset) const
1280 {
1281 return align_up(current_offset, alignment_required()) - current_offset;
1282 }
1283
1284 int CallLeafNoFPDirectNode::compute_padding(int current_offset) const
1285 {
1286 return align_up(current_offset, alignment_required()) - current_offset;
1287 }
1288
1289 //=============================================================================
1290
1291 #ifndef PRODUCT
1292 void MachBreakpointNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1293 assert_cond(st != nullptr);
1294 st->print("BREAKPOINT");
1295 }
1296 #endif
1297
1298 void MachBreakpointNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
1299 __ ebreak();
1300 }
1301
1302 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
1303 return MachNode::size(ra_);
1304 }
1305
1306 //=============================================================================
1307
1308 #ifndef PRODUCT
1309 void MachNopNode::format(PhaseRegAlloc*, outputStream* st) const {
1310 st->print("nop \t# %d bytes pad for loops and calls", _count);
1311 }
1312 #endif
1313
1314 void MachNopNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc*) const {
1315 Assembler::CompressibleScope scope(masm); // nops shall be 2-byte under RVC for alignment purposes.
1316 for (int i = 0; i < _count; i++) {
1317 __ nop();
1318 }
1319 }
1320
1321 uint MachNopNode::size(PhaseRegAlloc*) const {
1322 return _count * (UseRVC ? NativeInstruction::compressed_instruction_size : NativeInstruction::instruction_size);
1323 }
1324
1325 //=============================================================================
1326 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::EMPTY;
1327
1328 int ConstantTable::calculate_table_base_offset() const {
1329 return 0; // absolute addressing, no offset
1330 }
1331
1332 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
1333 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
1334 ShouldNotReachHere();
1335 }
1336
1337 void MachConstantBaseNode::emit(C2_MacroAssembler* masm, PhaseRegAlloc* ra_) const {
1338 // Empty encoding
1339 }
1340
1341 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
1342 return 0;
1343 }
1344
1345 #ifndef PRODUCT
1346 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1347 assert_cond(st != nullptr);
1348 st->print("-- \t// MachConstantBaseNode (empty encoding)");
1349 }
1350 #endif
1351
1352 #ifndef PRODUCT
1353 void MachPrologNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1354 assert_cond(st != nullptr && ra_ != nullptr);
1355 Compile* C = ra_->C;
1356
1357 int framesize = C->output()->frame_slots() << LogBytesPerInt;
1358
1359 if (C->output()->need_stack_bang(framesize)) {
1360 st->print("# stack bang size=%d\n\t", framesize);
1361 }
1362
1363 st->print("sub sp, sp, #%d\n\t", framesize);
1364 st->print("sd fp, [sp, #%d]\n\t", framesize - 2 * wordSize);
1365 st->print("sd ra, [sp, #%d]\n\t", framesize - wordSize);
1366 if (PreserveFramePointer) { st->print("add fp, sp, #%d\n\t", framesize); }
1367
1368 if (VerifyStackAtCalls) {
1369 st->print("mv t2, %ld\n\t", MAJIK_DWORD);
1370 st->print("sd t2, [sp, #%d]\n\t", framesize - 3 * wordSize);
1371 }
1372
1373 if (C->stub_function() == nullptr) {
1374 st->print("ld t0, [guard]\n\t");
1375 st->print("membar LoadLoad\n\t");
1376 st->print("ld t1, [xthread, #thread_disarmed_guard_value_offset]\n\t");
1377 st->print("beq t0, t1, skip\n\t");
1378 st->print("jalr #nmethod_entry_barrier_stub\n\t");
1379 st->print("j skip\n\t");
1380 st->print("guard: int\n\t");
1381 st->print("skip:\n\t");
1382 }
1383 }
1384 #endif
1385
1386 void MachPrologNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
1387 assert_cond(ra_ != nullptr);
1388 Compile* C = ra_->C;
1389
1390 // n.b. frame size includes space for return pc and fp
1391 const int framesize = C->output()->frame_size_in_bytes();
1392
1393 assert_cond(C != nullptr);
1394
1395 if (C->clinit_barrier_on_entry()) {
1396 assert(!C->method()->holder()->is_not_initialized(), "initialization should have been started");
1397
1398 Label L_skip_barrier;
1399
1400 __ mov_metadata(t1, C->method()->holder()->constant_encoding());
1401 __ clinit_barrier(t1, t0, &L_skip_barrier);
1402 __ far_jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub()));
1403 __ bind(L_skip_barrier);
1404 }
1405
1406 int bangsize = C->output()->bang_size_in_bytes();
1407 if (C->output()->need_stack_bang(bangsize)) {
1408 __ generate_stack_overflow_check(bangsize);
1409 }
1410
1411 __ build_frame(framesize);
1412
1413 if (VerifyStackAtCalls) {
1414 __ mv(t2, MAJIK_DWORD);
1415 __ sd(t2, Address(sp, framesize - 3 * wordSize));
1416 }
1417
1418 if (C->stub_function() == nullptr) {
1419 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
1420 // Dummy labels for just measuring the code size
1421 Label dummy_slow_path;
1422 Label dummy_continuation;
1423 Label dummy_guard;
1424 Label* slow_path = &dummy_slow_path;
1425 Label* continuation = &dummy_continuation;
1426 Label* guard = &dummy_guard;
1427 if (!Compile::current()->output()->in_scratch_emit_size()) {
1428 // Use real labels from actual stub when not emitting code for purpose of measuring its size
1429 C2EntryBarrierStub* stub = new (Compile::current()->comp_arena()) C2EntryBarrierStub();
1430 Compile::current()->output()->add_stub(stub);
1431 slow_path = &stub->entry();
1432 continuation = &stub->continuation();
1433 guard = &stub->guard();
1434 }
1435 // In the C2 code, we move the non-hot part of nmethod entry barriers out-of-line to a stub.
1436 bs->nmethod_entry_barrier(masm, slow_path, continuation, guard);
1437 }
1438
1439 C->output()->set_frame_complete(__ offset());
1440
1441 if (C->has_mach_constant_base_node()) {
1442 // NOTE: We set the table base offset here because users might be
1443 // emitted before MachConstantBaseNode.
1444 ConstantTable& constant_table = C->output()->constant_table();
1445 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
1446 }
1447 }
1448
1449 uint MachPrologNode::size(PhaseRegAlloc* ra_) const
1450 {
1451 assert_cond(ra_ != nullptr);
1452 return MachNode::size(ra_); // too many variables; just compute it
1453 // the hard way
1454 }
1455
1456 int MachPrologNode::reloc() const
1457 {
1458 return 0;
1459 }
1460
1461 //=============================================================================
1462
1463 #ifndef PRODUCT
1464 void MachEpilogNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1465 assert_cond(st != nullptr && ra_ != nullptr);
1466 Compile* C = ra_->C;
1467 assert_cond(C != nullptr);
1468 int framesize = C->output()->frame_size_in_bytes();
1469
1470 st->print("# pop frame %d\n\t", framesize);
1471
1472 if (framesize == 0) {
1473 st->print("ld ra, [sp,#%d]\n\t", (2 * wordSize));
1474 st->print("ld fp, [sp,#%d]\n\t", (3 * wordSize));
1475 st->print("add sp, sp, #%d\n\t", (2 * wordSize));
1476 } else {
1477 st->print("add sp, sp, #%d\n\t", framesize);
1478 st->print("ld ra, [sp,#%d]\n\t", - 2 * wordSize);
1479 st->print("ld fp, [sp,#%d]\n\t", - wordSize);
1480 }
1481
1482 if (do_polling() && C->is_method_compilation()) {
1483 st->print("# test polling word\n\t");
1484 st->print("ld t0, [xthread,#%d]\n\t", in_bytes(JavaThread::polling_word_offset()));
1485 st->print("bgtu sp, t0, #slow_path");
1486 }
1487 }
1488 #endif
1489
1490 void MachEpilogNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
1491 assert_cond(ra_ != nullptr);
1492 Compile* C = ra_->C;
1493 assert_cond(C != nullptr);
1494 int framesize = C->output()->frame_size_in_bytes();
1495
1496 __ remove_frame(framesize);
1497
1498 if (StackReservedPages > 0 && C->has_reserved_stack_access()) {
1499 __ reserved_stack_check();
1500 }
1501
1502 if (do_polling() && C->is_method_compilation()) {
1503 Label dummy_label;
1504 Label* code_stub = &dummy_label;
1505 if (!C->output()->in_scratch_emit_size()) {
1506 C2SafepointPollStub* stub = new (C->comp_arena()) C2SafepointPollStub(__ offset());
1507 C->output()->add_stub(stub);
1508 code_stub = &stub->entry();
1509 }
1510 __ relocate(relocInfo::poll_return_type);
1511 __ safepoint_poll(*code_stub, true /* at_return */, true /* in_nmethod */);
1512 }
1513 }
1514
1515 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
1516 assert_cond(ra_ != nullptr);
1517 // Variable size. Determine dynamically.
1518 return MachNode::size(ra_);
1519 }
1520
1521 int MachEpilogNode::reloc() const {
1522 // Return number of relocatable values contained in this instruction.
1523 return 1; // 1 for polling page.
1524 }
1525 const Pipeline * MachEpilogNode::pipeline() const {
1526 return MachNode::pipeline_class();
1527 }
1528
1529 //=============================================================================
1530
1531 // Figure out which register class each belongs in: rc_int, rc_float or
1532 // rc_stack.
1533 enum RC { rc_bad, rc_int, rc_float, rc_vector, rc_stack };
1534
1535 static enum RC rc_class(OptoReg::Name reg) {
1536
1537 if (reg == OptoReg::Bad) {
1538 return rc_bad;
1539 }
1540
1541 // we have 30 int registers * 2 halves
1542 // (t0 and t1 are omitted)
1543 int slots_of_int_registers = Register::max_slots_per_register * (Register::number_of_registers - 2);
1544 if (reg < slots_of_int_registers) {
1545 return rc_int;
1546 }
1547
1548 // we have 32 float register * 2 halves
1549 int slots_of_float_registers = FloatRegister::max_slots_per_register * FloatRegister::number_of_registers;
1550 if (reg < slots_of_int_registers + slots_of_float_registers) {
1551 return rc_float;
1552 }
1553
1554 // we have 32 vector register * 4 halves
1555 int slots_of_vector_registers = VectorRegister::max_slots_per_register * VectorRegister::number_of_registers;
1556 if (reg < slots_of_int_registers + slots_of_float_registers + slots_of_vector_registers) {
1557 return rc_vector;
1558 }
1559
1560 // Between vector regs & stack is the flags regs.
1561 assert(OptoReg::is_stack(reg), "blow up if spilling flags");
1562
1563 return rc_stack;
1564 }
1565
1566 uint MachSpillCopyNode::implementation(C2_MacroAssembler *masm, PhaseRegAlloc *ra_, bool do_size, outputStream *st) const {
1567 assert_cond(ra_ != nullptr);
1568 Compile* C = ra_->C;
1569
1570 // Get registers to move.
1571 OptoReg::Name src_hi = ra_->get_reg_second(in(1));
1572 OptoReg::Name src_lo = ra_->get_reg_first(in(1));
1573 OptoReg::Name dst_hi = ra_->get_reg_second(this);
1574 OptoReg::Name dst_lo = ra_->get_reg_first(this);
1575
1576 enum RC src_hi_rc = rc_class(src_hi);
1577 enum RC src_lo_rc = rc_class(src_lo);
1578 enum RC dst_hi_rc = rc_class(dst_hi);
1579 enum RC dst_lo_rc = rc_class(dst_lo);
1580
1581 assert(src_lo != OptoReg::Bad && dst_lo != OptoReg::Bad, "must move at least 1 register");
1582
1583 if (src_hi != OptoReg::Bad && !bottom_type()->isa_vectmask()) {
1584 assert((src_lo & 1) == 0 && src_lo + 1 == src_hi &&
1585 (dst_lo & 1) == 0 && dst_lo + 1 == dst_hi,
1586 "expected aligned-adjacent pairs");
1587 }
1588
1589 if (src_lo == dst_lo && src_hi == dst_hi) {
1590 return 0; // Self copy, no move.
1591 }
1592
1593 bool is64 = (src_lo & 1) == 0 && src_lo + 1 == src_hi &&
1594 (dst_lo & 1) == 0 && dst_lo + 1 == dst_hi;
1595 int src_offset = ra_->reg2offset(src_lo);
1596 int dst_offset = ra_->reg2offset(dst_lo);
1597
1598 if (bottom_type()->isa_vect() != nullptr) {
1599 uint ireg = ideal_reg();
1600 if (ireg == Op_VecA && masm) {
1601 int vector_reg_size_in_bytes = Matcher::scalable_vector_reg_size(T_BYTE);
1602 if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
1603 // stack to stack
1604 __ spill_copy_vector_stack_to_stack(src_offset, dst_offset,
1605 vector_reg_size_in_bytes);
1606 } else if (src_lo_rc == rc_vector && dst_lo_rc == rc_stack) {
1607 // vpr to stack
1608 __ spill(as_VectorRegister(Matcher::_regEncode[src_lo]), ra_->reg2offset(dst_lo));
1609 } else if (src_lo_rc == rc_stack && dst_lo_rc == rc_vector) {
1610 // stack to vpr
1611 __ unspill(as_VectorRegister(Matcher::_regEncode[dst_lo]), ra_->reg2offset(src_lo));
1612 } else if (src_lo_rc == rc_vector && dst_lo_rc == rc_vector) {
1613 // vpr to vpr
1614 __ vsetvli_helper(T_BYTE, MaxVectorSize);
1615 __ vmv_v_v(as_VectorRegister(Matcher::_regEncode[dst_lo]), as_VectorRegister(Matcher::_regEncode[src_lo]));
1616 } else {
1617 ShouldNotReachHere();
1618 }
1619 } else if (bottom_type()->isa_vectmask() && masm) {
1620 int vmask_size_in_bytes = Matcher::scalable_predicate_reg_slots() * 32 / 8;
1621 if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
1622 // stack to stack
1623 __ spill_copy_vmask_stack_to_stack(src_offset, dst_offset,
1624 vmask_size_in_bytes);
1625 } else if (src_lo_rc == rc_vector && dst_lo_rc == rc_stack) {
1626 // vmask to stack
1627 __ spill_vmask(as_VectorRegister(Matcher::_regEncode[src_lo]), ra_->reg2offset(dst_lo));
1628 } else if (src_lo_rc == rc_stack && dst_lo_rc == rc_vector) {
1629 // stack to vmask
1630 __ unspill_vmask(as_VectorRegister(Matcher::_regEncode[dst_lo]), ra_->reg2offset(src_lo));
1631 } else if (src_lo_rc == rc_vector && dst_lo_rc == rc_vector) {
1632 // vmask to vmask
1633 __ vsetvli_helper(T_BYTE, MaxVectorSize >> 3);
1634 __ vmv_v_v(as_VectorRegister(Matcher::_regEncode[dst_lo]), as_VectorRegister(Matcher::_regEncode[src_lo]));
1635 } else {
1636 ShouldNotReachHere();
1637 }
1638 }
1639 } else if (masm != nullptr) {
1640 switch (src_lo_rc) {
1641 case rc_int:
1642 if (dst_lo_rc == rc_int) { // gpr --> gpr copy
1643 if (!is64 && this->ideal_reg() != Op_RegI) { // zero extended for narrow oop or klass
1644 __ zext(as_Register(Matcher::_regEncode[dst_lo]), as_Register(Matcher::_regEncode[src_lo]), 32);
1645 } else {
1646 __ mv(as_Register(Matcher::_regEncode[dst_lo]), as_Register(Matcher::_regEncode[src_lo]));
1647 }
1648 } else if (dst_lo_rc == rc_float) { // gpr --> fpr copy
1649 if (is64) {
1650 __ fmv_d_x(as_FloatRegister(Matcher::_regEncode[dst_lo]),
1651 as_Register(Matcher::_regEncode[src_lo]));
1652 } else {
1653 __ fmv_w_x(as_FloatRegister(Matcher::_regEncode[dst_lo]),
1654 as_Register(Matcher::_regEncode[src_lo]));
1655 }
1656 } else { // gpr --> stack spill
1657 assert(dst_lo_rc == rc_stack, "spill to bad register class");
1658 __ spill(as_Register(Matcher::_regEncode[src_lo]), is64, dst_offset);
1659 }
1660 break;
1661 case rc_float:
1662 if (dst_lo_rc == rc_int) { // fpr --> gpr copy
1663 if (is64) {
1664 __ fmv_x_d(as_Register(Matcher::_regEncode[dst_lo]),
1665 as_FloatRegister(Matcher::_regEncode[src_lo]));
1666 } else {
1667 __ fmv_x_w(as_Register(Matcher::_regEncode[dst_lo]),
1668 as_FloatRegister(Matcher::_regEncode[src_lo]));
1669 }
1670 } else if (dst_lo_rc == rc_float) { // fpr --> fpr copy
1671 if (is64) {
1672 __ fmv_d(as_FloatRegister(Matcher::_regEncode[dst_lo]),
1673 as_FloatRegister(Matcher::_regEncode[src_lo]));
1674 } else {
1675 __ fmv_s(as_FloatRegister(Matcher::_regEncode[dst_lo]),
1676 as_FloatRegister(Matcher::_regEncode[src_lo]));
1677 }
1678 } else { // fpr --> stack spill
1679 assert(dst_lo_rc == rc_stack, "spill to bad register class");
1680 __ spill(as_FloatRegister(Matcher::_regEncode[src_lo]),
1681 is64, dst_offset);
1682 }
1683 break;
1684 case rc_stack:
1685 if (dst_lo_rc == rc_int) { // stack --> gpr load
1686 if (this->ideal_reg() == Op_RegI) {
1687 __ unspill(as_Register(Matcher::_regEncode[dst_lo]), is64, src_offset);
1688 } else { // // zero extended for narrow oop or klass
1689 __ unspillu(as_Register(Matcher::_regEncode[dst_lo]), is64, src_offset);
1690 }
1691 } else if (dst_lo_rc == rc_float) { // stack --> fpr load
1692 __ unspill(as_FloatRegister(Matcher::_regEncode[dst_lo]),
1693 is64, src_offset);
1694 } else { // stack --> stack copy
1695 assert(dst_lo_rc == rc_stack, "spill to bad register class");
1696 if (this->ideal_reg() == Op_RegI) {
1697 __ unspill(t0, is64, src_offset);
1698 } else { // zero extended for narrow oop or klass
1699 __ unspillu(t0, is64, src_offset);
1700 }
1701 __ spill(t0, is64, dst_offset);
1702 }
1703 break;
1704 default:
1705 ShouldNotReachHere();
1706 }
1707 }
1708
1709 if (st != nullptr) {
1710 st->print("spill ");
1711 if (src_lo_rc == rc_stack) {
1712 st->print("[sp, #%d] -> ", src_offset);
1713 } else {
1714 st->print("%s -> ", Matcher::regName[src_lo]);
1715 }
1716 if (dst_lo_rc == rc_stack) {
1717 st->print("[sp, #%d]", dst_offset);
1718 } else {
1719 st->print("%s", Matcher::regName[dst_lo]);
1720 }
1721 if (bottom_type()->isa_vect() && !bottom_type()->isa_vectmask()) {
1722 int vsize = 0;
1723 if (ideal_reg() == Op_VecA) {
1724 vsize = Matcher::scalable_vector_reg_size(T_BYTE) * 8;
1725 } else {
1726 ShouldNotReachHere();
1727 }
1728 st->print("\t# vector spill size = %d", vsize);
1729 } else if (ideal_reg() == Op_RegVectMask) {
1730 assert(Matcher::supports_scalable_vector(), "bad register type for spill");
1731 int vsize = Matcher::scalable_predicate_reg_slots() * 32;
1732 st->print("\t# vmask spill size = %d", vsize);
1733 } else {
1734 st->print("\t# spill size = %d", is64 ? 64 : 32);
1735 }
1736 }
1737
1738 return 0;
1739 }
1740
1741 #ifndef PRODUCT
1742 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1743 if (ra_ == nullptr) {
1744 st->print("N%d = SpillCopy(N%d)", _idx, in(1)->_idx);
1745 } else {
1746 implementation(nullptr, ra_, false, st);
1747 }
1748 }
1749 #endif
1750
1751 void MachSpillCopyNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
1752 implementation(masm, ra_, false, nullptr);
1753 }
1754
1755 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1756 return MachNode::size(ra_);
1757 }
1758
1759 //=============================================================================
1760
1761 #ifndef PRODUCT
1762 void BoxLockNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1763 assert_cond(ra_ != nullptr && st != nullptr);
1764 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1765 int reg = ra_->get_reg_first(this);
1766 st->print("add %s, sp, #%d\t# box lock",
1767 Matcher::regName[reg], offset);
1768 }
1769 #endif
1770
1771 void BoxLockNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
1772 Assembler::IncompressibleScope scope(masm); // Fixed length: see BoxLockNode::size()
1773
1774 assert_cond(ra_ != nullptr);
1775 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1776 int reg = ra_->get_encode(this);
1777
1778 if (Assembler::is_simm12(offset)) {
1779 __ addi(as_Register(reg), sp, offset);
1780 } else {
1781 __ li32(t0, offset);
1782 __ add(as_Register(reg), sp, t0);
1783 }
1784 }
1785
1786 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1787 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_).
1788 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1789
1790 if (Assembler::is_simm12(offset)) {
1791 return NativeInstruction::instruction_size;
1792 } else {
1793 return 3 * NativeInstruction::instruction_size; // lui + addiw + add;
1794 }
1795 }
1796
1797 //=============================================================================
1798
1799 #ifndef PRODUCT
1800 void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1801 {
1802 assert_cond(st != nullptr);
1803 st->print_cr("# MachUEPNode");
1804 if (UseCompressedClassPointers) {
1805 st->print_cr("\tlwu t1, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass");
1806 st->print_cr("\tlwu t2, [t0 + CompiledICData::speculated_klass_offset()]\t# compressed klass");
1807 } else {
1808 st->print_cr("\tld t1, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass");
1809 st->print_cr("\tld t2, [t0 + CompiledICData::speculated_klass_offset()]\t# compressed klass");
1810 }
1811 st->print_cr("\tbeq t1, t2, ic_hit");
1812 st->print_cr("\tj, SharedRuntime::_ic_miss_stub\t # Inline cache check");
1813 st->print_cr("\tic_hit:");
1814 }
1815 #endif
1816
1817 void MachUEPNode::emit(C2_MacroAssembler* masm, PhaseRegAlloc* ra_) const
1818 {
1819 // This is the unverified entry point.
1820 __ ic_check(CodeEntryAlignment);
1821
1822 // ic_check() aligns to CodeEntryAlignment >= InteriorEntryAlignment(min 16) > NativeInstruction::instruction_size(4).
1823 assert(((__ offset()) % CodeEntryAlignment) == 0, "Misaligned verified entry point");
1824 }
1825
1826 uint MachUEPNode::size(PhaseRegAlloc* ra_) const
1827 {
1828 assert_cond(ra_ != nullptr);
1829 return MachNode::size(ra_);
1830 }
1831
1832 // REQUIRED EMIT CODE
1833
1834 //=============================================================================
1835
1836 // Emit deopt handler code.
1837 int HandlerImpl::emit_deopt_handler(C2_MacroAssembler* masm)
1838 {
1839 address base = __ start_a_stub(size_deopt_handler());
1840 if (base == nullptr) {
1841 ciEnv::current()->record_failure("CodeCache is full");
1842 return 0; // CodeBuffer::expand failed
1843 }
1844 int offset = __ offset();
1845
1846 Label start;
1847 __ bind(start);
1848
1849 __ far_call(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
1850
1851 int entry_offset = __ offset();
1852 __ j(start);
1853
1854 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1855 assert(__ offset() - entry_offset >= NativePostCallNop::first_check_size,
1856 "out of bounds read in post-call NOP check");
1857 __ end_a_stub();
1858 return entry_offset;
1859
1860 }
1861 // REQUIRED MATCHER CODE
1862
1863 //=============================================================================
1864
1865 bool Matcher::match_rule_supported(int opcode) {
1866 if (!has_match_rule(opcode)) {
1867 return false;
1868 }
1869
1870 switch (opcode) {
1871 case Op_OnSpinWait:
1872 return VM_Version::supports_on_spin_wait();
1873 case Op_CacheWB: // fall through
1874 case Op_CacheWBPreSync: // fall through
1875 case Op_CacheWBPostSync:
1876 if (!VM_Version::supports_data_cache_line_flush()) {
1877 return false;
1878 }
1879 break;
1880
1881 case Op_StrCompressedCopy: // fall through
1882 case Op_StrInflatedCopy: // fall through
1883 case Op_CountPositives: // fall through
1884 case Op_EncodeISOArray:
1885 return UseRVV;
1886
1887 case Op_PopCountI:
1888 case Op_PopCountL:
1889 return UsePopCountInstruction;
1890
1891 case Op_ReverseI:
1892 case Op_ReverseL:
1893 return UseZbkb;
1894
1895 case Op_ReverseBytesI:
1896 case Op_ReverseBytesL:
1897 case Op_ReverseBytesS:
1898 case Op_ReverseBytesUS:
1899 case Op_RotateRight:
1900 case Op_RotateLeft:
1901 case Op_CountLeadingZerosI:
1902 case Op_CountLeadingZerosL:
1903 case Op_CountTrailingZerosI:
1904 case Op_CountTrailingZerosL:
1905 return UseZbb;
1906
1907 case Op_FmaF:
1908 case Op_FmaD:
1909 return UseFMA;
1910
1911 case Op_ConvHF2F:
1912 case Op_ConvF2HF:
1913 return VM_Version::supports_float16_float_conversion();
1914 case Op_ReinterpretS2HF:
1915 case Op_ReinterpretHF2S:
1916 return UseZfh || UseZfhmin;
1917 case Op_AddHF:
1918 case Op_DivHF:
1919 case Op_FmaHF:
1920 case Op_MaxHF:
1921 case Op_MinHF:
1922 case Op_MulHF:
1923 case Op_SqrtHF:
1924 case Op_SubHF:
1925 return UseZfh;
1926
1927 case Op_CMoveF:
1928 case Op_CMoveD:
1929 case Op_CMoveP:
1930 case Op_CMoveN:
1931 return false;
1932 }
1933
1934 return true; // Per default match rules are supported.
1935 }
1936
1937 const RegMask* Matcher::predicate_reg_mask(void) {
1938 return &_VMASK_REG_mask;
1939 }
1940
1941 // Vector calling convention not yet implemented.
1942 bool Matcher::supports_vector_calling_convention(void) {
1943 return EnableVectorSupport;
1944 }
1945
1946 OptoRegPair Matcher::vector_return_value(uint ideal_reg) {
1947 assert(EnableVectorSupport, "sanity");
1948 assert(ideal_reg == Op_VecA, "sanity");
1949 // check more info at https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-cc.adoc
1950 int lo = V8_num;
1951 int hi = V8_K_num;
1952 return OptoRegPair(hi, lo);
1953 }
1954
1955 // Is this branch offset short enough that a short branch can be used?
1956 //
1957 // NOTE: If the platform does not provide any short branch variants, then
1958 // this method should return false for offset 0.
1959 // |---label(L1)-----|
1960 // |-----------------|
1961 // |-----------------|----------eq: float-------------------
1962 // |-----------------| // far_cmpD_branch | cmpD_branch
1963 // |------- ---------| feq; | feq;
1964 // |-far_cmpD_branch-| beqz done; | bnez L;
1965 // |-----------------| j L; |
1966 // |-----------------| bind(done); |
1967 // |-----------------|--------------------------------------
1968 // |-----------------| // so shortBrSize = br_size - 4;
1969 // |-----------------| // so offs = offset - shortBrSize + 4;
1970 // |---label(L2)-----|
1971 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1972 // The passed offset is relative to address of the branch.
1973 int shortBrSize = br_size - 4;
1974 int offs = offset - shortBrSize + 4;
1975 return (-4096 <= offs && offs < 4096);
1976 }
1977
1978 // Vector width in bytes.
1979 int Matcher::vector_width_in_bytes(BasicType bt) {
1980 if (UseRVV) {
1981 // The MaxVectorSize should have been set by detecting RVV max vector register size when check UseRVV.
1982 // MaxVectorSize == VM_Version::_initial_vector_length
1983 int size = MaxVectorSize;
1984 // Minimum 2 values in vector
1985 if (size < 2 * type2aelembytes(bt)) size = 0;
1986 // But never < 4
1987 if (size < 4) size = 0;
1988 return size;
1989 }
1990 return 0;
1991 }
1992
1993 // Limits on vector size (number of elements) loaded into vector.
1994 int Matcher::max_vector_size(const BasicType bt) {
1995 return vector_width_in_bytes(bt) / type2aelembytes(bt);
1996 }
1997
1998 int Matcher::min_vector_size(const BasicType bt) {
1999 int size;
2000 switch(bt) {
2001 case T_BOOLEAN:
2002 // Load/store a vector mask with only 2 elements for vector types
2003 // such as "2I/2F/2L/2D".
2004 size = 2;
2005 break;
2006 case T_BYTE:
2007 // Generate a "4B" vector, to support vector cast between "8B/16B"
2008 // and "4S/4I/4L/4F/4D".
2009 size = 4;
2010 break;
2011 case T_SHORT:
2012 // Generate a "2S" vector, to support vector cast between "4S/8S"
2013 // and "2I/2L/2F/2D".
2014 size = 2;
2015 break;
2016 default:
2017 // Limit the min vector length to 64-bit.
2018 size = 8 / type2aelembytes(bt);
2019 // The number of elements in a vector should be at least 2.
2020 size = MAX2(size, 2);
2021 }
2022
2023 int max_size = max_vector_size(bt);
2024 return MIN2(size, max_size);
2025 }
2026
2027 int Matcher::max_vector_size_auto_vectorization(const BasicType bt) {
2028 return Matcher::max_vector_size(bt);
2029 }
2030
2031 // Vector ideal reg.
2032 uint Matcher::vector_ideal_reg(int len) {
2033 assert(MaxVectorSize >= len, "");
2034 if (UseRVV) {
2035 return Op_VecA;
2036 }
2037
2038 ShouldNotReachHere();
2039 return 0;
2040 }
2041
2042 int Matcher::scalable_vector_reg_size(const BasicType bt) {
2043 return Matcher::max_vector_size(bt);
2044 }
2045
2046 MachOper* Matcher::pd_specialize_generic_vector_operand(MachOper* original_opnd, uint ideal_reg, bool is_temp) {
2047 ShouldNotReachHere(); // generic vector operands not supported
2048 return nullptr;
2049 }
2050
2051 bool Matcher::is_reg2reg_move(MachNode* m) {
2052 ShouldNotReachHere(); // generic vector operands not supported
2053 return false;
2054 }
2055
2056 bool Matcher::is_generic_vector(MachOper* opnd) {
2057 ShouldNotReachHere(); // generic vector operands not supported
2058 return false;
2059 }
2060
2061 // Return whether or not this register is ever used as an argument.
2062 // This function is used on startup to build the trampoline stubs in
2063 // generateOptoStub. Registers not mentioned will be killed by the VM
2064 // call in the trampoline, and arguments in those registers not be
2065 // available to the callee.
2066 bool Matcher::can_be_java_arg(int reg)
2067 {
2068 return
2069 reg == R10_num || reg == R10_H_num ||
2070 reg == R11_num || reg == R11_H_num ||
2071 reg == R12_num || reg == R12_H_num ||
2072 reg == R13_num || reg == R13_H_num ||
2073 reg == R14_num || reg == R14_H_num ||
2074 reg == R15_num || reg == R15_H_num ||
2075 reg == R16_num || reg == R16_H_num ||
2076 reg == R17_num || reg == R17_H_num ||
2077 reg == F10_num || reg == F10_H_num ||
2078 reg == F11_num || reg == F11_H_num ||
2079 reg == F12_num || reg == F12_H_num ||
2080 reg == F13_num || reg == F13_H_num ||
2081 reg == F14_num || reg == F14_H_num ||
2082 reg == F15_num || reg == F15_H_num ||
2083 reg == F16_num || reg == F16_H_num ||
2084 reg == F17_num || reg == F17_H_num;
2085 }
2086
2087 bool Matcher::is_spillable_arg(int reg)
2088 {
2089 return can_be_java_arg(reg);
2090 }
2091
2092 uint Matcher::int_pressure_limit()
2093 {
2094 // A derived pointer is live at CallNode and then is flagged by RA
2095 // as a spilled LRG. Spilling heuristics(Spill-USE) explicitly skip
2096 // derived pointers and lastly fail to spill after reaching maximum
2097 // number of iterations. Lowering the default pressure threshold to
2098 // (_NO_SPECIAL_REG32_mask.size() minus 1) forces CallNode to become
2099 // a high register pressure area of the code so that split_DEF can
2100 // generate DefinitionSpillCopy for the derived pointer.
2101 uint default_int_pressure_threshold = _NO_SPECIAL_REG32_mask.size() - 1;
2102 if (!PreserveFramePointer) {
2103 // When PreserveFramePointer is off, frame pointer is allocatable,
2104 // but different from other SOC registers, it is excluded from
2105 // fatproj's mask because its save type is No-Save. Decrease 1 to
2106 // ensure high pressure at fatproj when PreserveFramePointer is off.
2107 // See check_pressure_at_fatproj().
2108 default_int_pressure_threshold--;
2109 }
2110 return (INTPRESSURE == -1) ? default_int_pressure_threshold : INTPRESSURE;
2111 }
2112
2113 uint Matcher::float_pressure_limit()
2114 {
2115 // _FLOAT_REG_mask is generated by adlc from the float_reg register class.
2116 return (FLOATPRESSURE == -1) ? _FLOAT_REG_mask.size() : FLOATPRESSURE;
2117 }
2118
2119 bool Matcher::use_asm_for_ldiv_by_con(jlong divisor) {
2120 return false;
2121 }
2122
2123 const RegMask& Matcher::divI_proj_mask() {
2124 ShouldNotReachHere();
2125 return RegMask::EMPTY;
2126 }
2127
2128 // Register for MODI projection of divmodI.
2129 const RegMask& Matcher::modI_proj_mask() {
2130 ShouldNotReachHere();
2131 return RegMask::EMPTY;
2132 }
2133
2134 // Register for DIVL projection of divmodL.
2135 const RegMask& Matcher::divL_proj_mask() {
2136 ShouldNotReachHere();
2137 return RegMask::EMPTY;
2138 }
2139
2140 // Register for MODL projection of divmodL.
2141 const RegMask& Matcher::modL_proj_mask() {
2142 ShouldNotReachHere();
2143 return RegMask::EMPTY;
2144 }
2145
2146 bool size_fits_all_mem_uses(AddPNode* addp, int shift) {
2147 assert_cond(addp != nullptr);
2148 for (DUIterator_Fast imax, i = addp->fast_outs(imax); i < imax; i++) {
2149 Node* u = addp->fast_out(i);
2150 if (u != nullptr && u->is_Mem()) {
2151 int opsize = u->as_Mem()->memory_size();
2152 assert(opsize > 0, "unexpected memory operand size");
2153 if (u->as_Mem()->memory_size() != (1 << shift)) {
2154 return false;
2155 }
2156 }
2157 }
2158 return true;
2159 }
2160
2161 // Binary src (Replicate scalar/immediate)
2162 static bool is_vector_scalar_bitwise_pattern(Node* n, Node* m) {
2163 if (n == nullptr || m == nullptr) {
2164 return false;
2165 }
2166
2167 if (m->Opcode() != Op_Replicate) {
2168 return false;
2169 }
2170
2171 switch (n->Opcode()) {
2172 case Op_AndV:
2173 case Op_OrV:
2174 case Op_XorV:
2175 case Op_AddVB:
2176 case Op_AddVS:
2177 case Op_AddVI:
2178 case Op_AddVL:
2179 case Op_SubVB:
2180 case Op_SubVS:
2181 case Op_SubVI:
2182 case Op_SubVL:
2183 case Op_MulVB:
2184 case Op_MulVS:
2185 case Op_MulVI:
2186 case Op_MulVL: {
2187 return true;
2188 }
2189 default:
2190 return false;
2191 }
2192 }
2193
2194 // (XorV src (Replicate m1))
2195 // (XorVMask src (MaskAll m1))
2196 static bool is_vector_bitwise_not_pattern(Node* n, Node* m) {
2197 if (n != nullptr && m != nullptr) {
2198 return (n->Opcode() == Op_XorV || n->Opcode() == Op_XorVMask) &&
2199 VectorNode::is_all_ones_vector(m);
2200 }
2201 return false;
2202 }
2203
2204 // Should the Matcher clone input 'm' of node 'n'?
2205 bool Matcher::pd_clone_node(Node* n, Node* m, Matcher::MStack& mstack) {
2206 assert_cond(m != nullptr);
2207 if (is_vshift_con_pattern(n, m) || // ShiftV src (ShiftCntV con)
2208 is_vector_bitwise_not_pattern(n, m) ||
2209 is_vector_scalar_bitwise_pattern(n, m) ||
2210 is_encode_and_store_pattern(n, m)) {
2211 mstack.push(m, Visit);
2212 return true;
2213 }
2214 return false;
2215 }
2216
2217 // Should the Matcher clone shifts on addressing modes, expecting them
2218 // to be subsumed into complex addressing expressions or compute them
2219 // into registers?
2220 bool Matcher::pd_clone_address_expressions(AddPNode* m, Matcher::MStack& mstack, VectorSet& address_visited) {
2221 return clone_base_plus_offset_address(m, mstack, address_visited);
2222 }
2223
2224 %}
2225
2226
2227
2228 //----------ENCODING BLOCK-----------------------------------------------------
2229 // This block specifies the encoding classes used by the compiler to
2230 // output byte streams. Encoding classes are parameterized macros
2231 // used by Machine Instruction Nodes in order to generate the bit
2232 // encoding of the instruction. Operands specify their base encoding
2233 // interface with the interface keyword. There are currently
2234 // supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, &
2235 // COND_INTER. REG_INTER causes an operand to generate a function
2236 // which returns its register number when queried. CONST_INTER causes
2237 // an operand to generate a function which returns the value of the
2238 // constant when queried. MEMORY_INTER causes an operand to generate
2239 // four functions which return the Base Register, the Index Register,
2240 // the Scale Value, and the Offset Value of the operand when queried.
2241 // COND_INTER causes an operand to generate six functions which return
2242 // the encoding code (ie - encoding bits for the instruction)
2243 // associated with each basic boolean condition for a conditional
2244 // instruction.
2245 //
2246 // Instructions specify two basic values for encoding. Again, a
2247 // function is available to check if the constant displacement is an
2248 // oop. They use the ins_encode keyword to specify their encoding
2249 // classes (which must be a sequence of enc_class names, and their
2250 // parameters, specified in the encoding block), and they use the
2251 // opcode keyword to specify, in order, their primary, secondary, and
2252 // tertiary opcode. Only the opcode sections which a particular
2253 // instruction needs for encoding need to be specified.
2254 encode %{
2255 // BEGIN Non-volatile memory access
2256
2257 enc_class riscv_enc_mov_imm(iRegIorL dst, immIorL src) %{
2258 int64_t con = (int64_t)$src$$constant;
2259 Register dst_reg = as_Register($dst$$reg);
2260 __ mv(dst_reg, con);
2261 %}
2262
2263 enc_class riscv_enc_mov_p(iRegP dst, immP src) %{
2264 Register dst_reg = as_Register($dst$$reg);
2265 address con = (address)$src$$constant;
2266 if (con == nullptr || con == (address)1) {
2267 ShouldNotReachHere();
2268 } else {
2269 relocInfo::relocType rtype = $src->constant_reloc();
2270 if (rtype == relocInfo::oop_type) {
2271 __ movoop(dst_reg, (jobject)con);
2272 } else if (rtype == relocInfo::metadata_type) {
2273 __ mov_metadata(dst_reg, (Metadata*)con);
2274 } else {
2275 assert(rtype == relocInfo::none, "unexpected reloc type");
2276 __ mv(dst_reg, $src$$constant);
2277 }
2278 }
2279 %}
2280
2281 enc_class riscv_enc_mov_p1(iRegP dst) %{
2282 Register dst_reg = as_Register($dst$$reg);
2283 __ mv(dst_reg, 1);
2284 %}
2285
2286 enc_class riscv_enc_mov_n(iRegN dst, immN src) %{
2287 Register dst_reg = as_Register($dst$$reg);
2288 address con = (address)$src$$constant;
2289 if (con == nullptr) {
2290 ShouldNotReachHere();
2291 } else {
2292 relocInfo::relocType rtype = $src->constant_reloc();
2293 assert(rtype == relocInfo::oop_type, "unexpected reloc type");
2294 __ set_narrow_oop(dst_reg, (jobject)con);
2295 }
2296 %}
2297
2298 enc_class riscv_enc_mov_zero(iRegNorP dst) %{
2299 Register dst_reg = as_Register($dst$$reg);
2300 __ mv(dst_reg, zr);
2301 %}
2302
2303 enc_class riscv_enc_mov_nk(iRegN dst, immNKlass src) %{
2304 Register dst_reg = as_Register($dst$$reg);
2305 address con = (address)$src$$constant;
2306 if (con == nullptr) {
2307 ShouldNotReachHere();
2308 } else {
2309 relocInfo::relocType rtype = $src->constant_reloc();
2310 assert(rtype == relocInfo::metadata_type, "unexpected reloc type");
2311 __ set_narrow_klass(dst_reg, (Klass *)con);
2312 }
2313 %}
2314
2315 // compare and branch instruction encodings
2316
2317 enc_class riscv_enc_j(label lbl) %{
2318 Label* L = $lbl$$label;
2319 __ j(*L);
2320 %}
2321
2322 enc_class riscv_enc_far_cmpULtGe_imm0_branch(cmpOpULtGe cmp, iRegIorL op1, label lbl) %{
2323 Label* L = $lbl$$label;
2324 switch ($cmp$$cmpcode) {
2325 case(BoolTest::ge):
2326 __ j(*L);
2327 break;
2328 case(BoolTest::lt):
2329 break;
2330 default:
2331 Unimplemented();
2332 }
2333 %}
2334
2335 // call instruction encodings
2336
2337 enc_class riscv_enc_partial_subtype_check(iRegP sub, iRegP super, iRegP temp, iRegP result) %{
2338 Register sub_reg = as_Register($sub$$reg);
2339 Register super_reg = as_Register($super$$reg);
2340 Register temp_reg = as_Register($temp$$reg);
2341 Register result_reg = as_Register($result$$reg);
2342 Register cr_reg = t1;
2343
2344 Label miss;
2345 Label done;
2346 __ check_klass_subtype_slow_path(sub_reg, super_reg, temp_reg, result_reg,
2347 nullptr, &miss, /*set_cond_codes*/ true);
2348 if ($primary) {
2349 __ mv(result_reg, zr);
2350 } else {
2351 __ mv(cr_reg, zr);
2352 __ j(done);
2353 }
2354
2355 __ bind(miss);
2356 if (!$primary) {
2357 __ mv(cr_reg, 1);
2358 }
2359
2360 __ bind(done);
2361 %}
2362
2363 enc_class riscv_enc_java_static_call(method meth) %{
2364 Assembler::IncompressibleScope scope(masm); // Fixed length: see ret_addr_offset
2365
2366 address addr = (address)$meth$$method;
2367 address call = nullptr;
2368 assert_cond(addr != nullptr);
2369 if (!_method) {
2370 // A call to a runtime wrapper, e.g. new, new_typeArray_Java, uncommon_trap.
2371 call = __ reloc_call(Address(addr, relocInfo::runtime_call_type));
2372 if (call == nullptr) {
2373 ciEnv::current()->record_failure("CodeCache is full");
2374 return;
2375 }
2376 } else if (_method->intrinsic_id() == vmIntrinsicID::_ensureMaterializedForStackWalk) {
2377 // The NOP here is purely to ensure that eliding a call to
2378 // JVM_EnsureMaterializedForStackWalk doesn't change the code size.
2379 __ nop();
2380 __ nop();
2381 __ nop();
2382 __ block_comment("call JVM_EnsureMaterializedForStackWalk (elided)");
2383 } else {
2384 int method_index = resolved_method_index(masm);
2385 RelocationHolder rspec = _optimized_virtual ? opt_virtual_call_Relocation::spec(method_index)
2386 : static_call_Relocation::spec(method_index);
2387 call = __ reloc_call(Address(addr, rspec));
2388 if (call == nullptr) {
2389 ciEnv::current()->record_failure("CodeCache is full");
2390 return;
2391 }
2392
2393 if (CodeBuffer::supports_shared_stubs() && _method->can_be_statically_bound()) {
2394 // Calls of the same statically bound method can share
2395 // a stub to the interpreter.
2396 __ code()->shared_stub_to_interp_for(_method, call - (__ begin()));
2397 } else {
2398 // Emit stub for static call
2399 address stub = CompiledDirectCall::emit_to_interp_stub(masm, call);
2400 if (stub == nullptr) {
2401 ciEnv::current()->record_failure("CodeCache is full");
2402 return;
2403 }
2404 }
2405 }
2406
2407 __ post_call_nop();
2408 %}
2409
2410 enc_class riscv_enc_java_dynamic_call(method meth) %{
2411 Assembler::IncompressibleScope scope(masm); // Fixed length: see ret_addr_offset
2412 int method_index = resolved_method_index(masm);
2413 address call = __ ic_call((address)$meth$$method, method_index);
2414 if (call == nullptr) {
2415 ciEnv::current()->record_failure("CodeCache is full");
2416 return;
2417 }
2418
2419 __ post_call_nop();
2420 %}
2421
2422 enc_class riscv_enc_call_epilog() %{
2423 if (VerifyStackAtCalls) {
2424 // Check that stack depth is unchanged: find majik cookie on stack
2425 int framesize = ra_->reg2offset_unchecked(OptoReg::add(ra_->_matcher._old_SP, -3 * VMRegImpl::slots_per_word));
2426 Label stack_ok;
2427 __ ld(t1, Address(sp, framesize));
2428 __ mv(t2, MAJIK_DWORD);
2429 __ beq(t2, t1, stack_ok);
2430 __ stop("MAJIK_DWORD not found");
2431 __ bind(stack_ok);
2432 }
2433 %}
2434
2435 enc_class riscv_enc_java_to_runtime(method meth) %{
2436 Assembler::IncompressibleScope scope(masm); // Fixed length: see ret_addr_offset
2437
2438 // Some calls to generated routines (arraycopy code) are scheduled by C2
2439 // as runtime calls. if so we can call them using a far call (they will be
2440 // in the code cache, thus in a reachable segment) otherwise we have to use
2441 // a movptr+jalr pair which loads the absolute address into a register.
2442 address entry = (address)$meth$$method;
2443 if (CodeCache::contains(entry)) {
2444 __ far_call(Address(entry, relocInfo::runtime_call_type));
2445 __ post_call_nop();
2446 } else {
2447 Label retaddr;
2448 // Make the anchor frame walkable
2449 __ la(t0, retaddr);
2450 __ sd(t0, Address(xthread, JavaThread::last_Java_pc_offset()));
2451 int32_t offset = 0;
2452 // No relocation needed
2453 __ movptr(t1, entry, offset, t0); // lui + lui + slli + add
2454 __ jalr(t1, offset);
2455 __ bind(retaddr);
2456 __ post_call_nop();
2457 }
2458 %}
2459
2460 enc_class riscv_enc_tail_call(iRegP jump_target) %{
2461 Register target_reg = as_Register($jump_target$$reg);
2462 __ jr(target_reg);
2463 %}
2464
2465 enc_class riscv_enc_tail_jmp(iRegP jump_target) %{
2466 Register target_reg = as_Register($jump_target$$reg);
2467 // exception oop should be in x10
2468 // ret addr has been popped into ra
2469 // callee expects it in x13
2470 __ mv(x13, ra);
2471 __ jr(target_reg);
2472 %}
2473
2474 enc_class riscv_enc_rethrow() %{
2475 __ far_jump(RuntimeAddress(OptoRuntime::rethrow_stub()));
2476 %}
2477
2478 enc_class riscv_enc_ret() %{
2479 __ ret();
2480 %}
2481
2482 %}
2483
2484 //----------FRAME--------------------------------------------------------------
2485 // Definition of frame structure and management information.
2486 //
2487 // S T A C K L A Y O U T Allocators stack-slot number
2488 // | (to get allocators register number
2489 // G Owned by | | v add OptoReg::stack0())
2490 // r CALLER | |
2491 // o | +--------+ pad to even-align allocators stack-slot
2492 // w V | pad0 | numbers; owned by CALLER
2493 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
2494 // h ^ | in | 5
2495 // | | args | 4 Holes in incoming args owned by SELF
2496 // | | | | 3
2497 // | | +--------+
2498 // V | | old out| Empty on Intel, window on Sparc
2499 // | old |preserve| Must be even aligned.
2500 // | SP-+--------+----> Matcher::_old_SP, even aligned
2501 // | | in | 3 area for Intel ret address
2502 // Owned by |preserve| Empty on Sparc.
2503 // SELF +--------+
2504 // | | pad2 | 2 pad to align old SP
2505 // | +--------+ 1
2506 // | | locks | 0
2507 // | +--------+----> OptoReg::stack0(), even aligned
2508 // | | pad1 | 11 pad to align new SP
2509 // | +--------+
2510 // | | | 10
2511 // | | spills | 9 spills
2512 // V | | 8 (pad0 slot for callee)
2513 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
2514 // ^ | out | 7
2515 // | | args | 6 Holes in outgoing args owned by CALLEE
2516 // Owned by +--------+
2517 // CALLEE | new out| 6 Empty on Intel, window on Sparc
2518 // | new |preserve| Must be even-aligned.
2519 // | SP-+--------+----> Matcher::_new_SP, even aligned
2520 // | | |
2521 //
2522 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
2523 // known from SELF's arguments and the Java calling convention.
2524 // Region 6-7 is determined per call site.
2525 // Note 2: If the calling convention leaves holes in the incoming argument
2526 // area, those holes are owned by SELF. Holes in the outgoing area
2527 // are owned by the CALLEE. Holes should not be necessary in the
2528 // incoming area, as the Java calling convention is completely under
2529 // the control of the AD file. Doubles can be sorted and packed to
2530 // avoid holes. Holes in the outgoing arguments may be necessary for
2531 // varargs C calling conventions.
2532 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
2533 // even aligned with pad0 as needed.
2534 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
2535 // (the latter is true on Intel but is it false on RISCV?)
2536 // region 6-11 is even aligned; it may be padded out more so that
2537 // the region from SP to FP meets the minimum stack alignment.
2538 // Note 4: For I2C adapters, the incoming FP may not meet the minimum stack
2539 // alignment. Region 11, pad1, may be dynamically extended so that
2540 // SP meets the minimum alignment.
2541
2542 frame %{
2543 // These three registers define part of the calling convention
2544 // between compiled code and the interpreter.
2545
2546 // Inline Cache Register or methodOop for I2C.
2547 inline_cache_reg(R31);
2548
2549 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
2550 cisc_spilling_operand_name(indOffset);
2551
2552 // Number of stack slots consumed by locking an object
2553 // generate Compile::sync_stack_slots
2554 // VMRegImpl::slots_per_word = wordSize / stack_slot_size = 8 / 4 = 2
2555 sync_stack_slots(1 * VMRegImpl::slots_per_word);
2556
2557 // Compiled code's Frame Pointer
2558 frame_pointer(R2);
2559
2560 // Interpreter stores its frame pointer in a register which is
2561 // stored to the stack by I2CAdaptors.
2562 // I2CAdaptors convert from interpreted java to compiled java.
2563 interpreter_frame_pointer(R8);
2564
2565 // Stack alignment requirement
2566 stack_alignment(StackAlignmentInBytes); // Alignment size in bytes (128-bit -> 16 bytes)
2567
2568 // Number of outgoing stack slots killed above the out_preserve_stack_slots
2569 // for calls to C. Supports the var-args backing area for register parms.
2570 varargs_C_out_slots_killed(frame::arg_reg_save_area_bytes / BytesPerInt);
2571
2572 // The after-PROLOG location of the return address. Location of
2573 // return address specifies a type (REG or STACK) and a number
2574 // representing the register number (i.e. - use a register name) or
2575 // stack slot.
2576 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
2577 // Otherwise, it is above the locks and verification slot and alignment word
2578 // TODO this may well be correct but need to check why that - 2 is there
2579 // ppc port uses 0 but we definitely need to allow for fixed_slots
2580 // which folds in the space used for monitors
2581 return_addr(STACK - 2 +
2582 align_up((Compile::current()->in_preserve_stack_slots() +
2583 Compile::current()->fixed_slots()),
2584 stack_alignment_in_slots()));
2585
2586 // Location of compiled Java return values. Same as C for now.
2587 return_value
2588 %{
2589 assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL,
2590 "only return normal values");
2591
2592 static const int lo[Op_RegL + 1] = { // enum name
2593 0, // Op_Node
2594 0, // Op_Set
2595 R10_num, // Op_RegN
2596 R10_num, // Op_RegI
2597 R10_num, // Op_RegP
2598 F10_num, // Op_RegF
2599 F10_num, // Op_RegD
2600 R10_num // Op_RegL
2601 };
2602
2603 static const int hi[Op_RegL + 1] = { // enum name
2604 0, // Op_Node
2605 0, // Op_Set
2606 OptoReg::Bad, // Op_RegN
2607 OptoReg::Bad, // Op_RegI
2608 R10_H_num, // Op_RegP
2609 OptoReg::Bad, // Op_RegF
2610 F10_H_num, // Op_RegD
2611 R10_H_num // Op_RegL
2612 };
2613
2614 return OptoRegPair(hi[ideal_reg], lo[ideal_reg]);
2615 %}
2616 %}
2617
2618 //----------ATTRIBUTES---------------------------------------------------------
2619 //----------Operand Attributes-------------------------------------------------
2620 op_attrib op_cost(1); // Required cost attribute
2621
2622 //----------Instruction Attributes---------------------------------------------
2623 ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute
2624 ins_attrib ins_size(32); // Required size attribute (in bits)
2625 ins_attrib ins_short_branch(0); // Required flag: is this instruction
2626 // a non-matching short branch variant
2627 // of some long branch?
2628 ins_attrib ins_alignment(4); // Required alignment attribute (must
2629 // be a power of 2) specifies the
2630 // alignment that some part of the
2631 // instruction (not necessarily the
2632 // start) requires. If > 1, a
2633 // compute_padding() function must be
2634 // provided for the instruction
2635
2636 // Whether this node is expanded during code emission into a sequence of
2637 // instructions and the first instruction can perform an implicit null check.
2638 ins_attrib ins_is_late_expanded_null_check_candidate(false);
2639
2640 //----------OPERANDS-----------------------------------------------------------
2641 // Operand definitions must precede instruction definitions for correct parsing
2642 // in the ADLC because operands constitute user defined types which are used in
2643 // instruction definitions.
2644
2645 //----------Simple Operands----------------------------------------------------
2646
2647 // Integer operands 32 bit
2648 // 32 bit immediate
2649 operand immI()
2650 %{
2651 match(ConI);
2652
2653 op_cost(0);
2654 format %{ %}
2655 interface(CONST_INTER);
2656 %}
2657
2658 // 32 bit zero
2659 operand immI0()
2660 %{
2661 predicate(n->get_int() == 0);
2662 match(ConI);
2663
2664 op_cost(0);
2665 format %{ %}
2666 interface(CONST_INTER);
2667 %}
2668
2669 // 32 bit unit increment
2670 operand immI_1()
2671 %{
2672 predicate(n->get_int() == 1);
2673 match(ConI);
2674
2675 op_cost(0);
2676 format %{ %}
2677 interface(CONST_INTER);
2678 %}
2679
2680 // 32 bit unit decrement
2681 operand immI_M1()
2682 %{
2683 predicate(n->get_int() == -1);
2684 match(ConI);
2685
2686 op_cost(0);
2687 format %{ %}
2688 interface(CONST_INTER);
2689 %}
2690
2691 // Unsigned Integer Immediate: 6-bit int, greater than 32
2692 operand uimmI6_ge32() %{
2693 predicate(((unsigned int)(n->get_int()) < 64) && (n->get_int() >= 32));
2694 match(ConI);
2695 op_cost(0);
2696 format %{ %}
2697 interface(CONST_INTER);
2698 %}
2699
2700 operand immI_le_4()
2701 %{
2702 predicate(n->get_int() <= 4);
2703 match(ConI);
2704
2705 op_cost(0);
2706 format %{ %}
2707 interface(CONST_INTER);
2708 %}
2709
2710 operand immI_16()
2711 %{
2712 predicate(n->get_int() == 16);
2713 match(ConI);
2714 op_cost(0);
2715 format %{ %}
2716 interface(CONST_INTER);
2717 %}
2718
2719 operand immI_24()
2720 %{
2721 predicate(n->get_int() == 24);
2722 match(ConI);
2723 op_cost(0);
2724 format %{ %}
2725 interface(CONST_INTER);
2726 %}
2727
2728 operand immI_31()
2729 %{
2730 predicate(n->get_int() == 31);
2731 match(ConI);
2732
2733 op_cost(0);
2734 format %{ %}
2735 interface(CONST_INTER);
2736 %}
2737
2738 operand immI_63()
2739 %{
2740 predicate(n->get_int() == 63);
2741 match(ConI);
2742
2743 op_cost(0);
2744 format %{ %}
2745 interface(CONST_INTER);
2746 %}
2747
2748 // 32 bit integer valid for add immediate
2749 operand immIAdd()
2750 %{
2751 predicate(Assembler::is_simm12((int64_t)n->get_int()));
2752 match(ConI);
2753 op_cost(0);
2754 format %{ %}
2755 interface(CONST_INTER);
2756 %}
2757
2758 // 32 bit integer valid for sub immediate
2759 operand immISub()
2760 %{
2761 predicate(Assembler::is_simm12(-(int64_t)n->get_int()));
2762 match(ConI);
2763 op_cost(0);
2764 format %{ %}
2765 interface(CONST_INTER);
2766 %}
2767
2768 // 5 bit signed value.
2769 operand immI5()
2770 %{
2771 predicate(n->get_int() <= 15 && n->get_int() >= -16);
2772 match(ConI);
2773
2774 op_cost(0);
2775 format %{ %}
2776 interface(CONST_INTER);
2777 %}
2778
2779 // 5 bit signed value (simm5)
2780 operand immL5()
2781 %{
2782 predicate(n->get_long() <= 15 && n->get_long() >= -16);
2783 match(ConL);
2784
2785 op_cost(0);
2786 format %{ %}
2787 interface(CONST_INTER);
2788 %}
2789
2790 // Integer operands 64 bit
2791 // 64 bit immediate
2792 operand immL()
2793 %{
2794 match(ConL);
2795
2796 op_cost(0);
2797 format %{ %}
2798 interface(CONST_INTER);
2799 %}
2800
2801 // 64 bit zero
2802 operand immL0()
2803 %{
2804 predicate(n->get_long() == 0);
2805 match(ConL);
2806
2807 op_cost(0);
2808 format %{ %}
2809 interface(CONST_INTER);
2810 %}
2811
2812 // Pointer operands
2813 // Pointer Immediate
2814 operand immP()
2815 %{
2816 match(ConP);
2817
2818 op_cost(0);
2819 format %{ %}
2820 interface(CONST_INTER);
2821 %}
2822
2823 // Null Pointer Immediate
2824 operand immP0()
2825 %{
2826 predicate(n->get_ptr() == 0);
2827 match(ConP);
2828
2829 op_cost(0);
2830 format %{ %}
2831 interface(CONST_INTER);
2832 %}
2833
2834 // Pointer Immediate One
2835 // this is used in object initialization (initial object header)
2836 operand immP_1()
2837 %{
2838 predicate(n->get_ptr() == 1);
2839 match(ConP);
2840
2841 op_cost(0);
2842 format %{ %}
2843 interface(CONST_INTER);
2844 %}
2845
2846 // Int Immediate: low 16-bit mask
2847 operand immI_16bits()
2848 %{
2849 predicate(n->get_int() == 0xFFFF);
2850 match(ConI);
2851 op_cost(0);
2852 format %{ %}
2853 interface(CONST_INTER);
2854 %}
2855
2856 operand immIpowerOf2() %{
2857 predicate(is_power_of_2((juint)(n->get_int())));
2858 match(ConI);
2859 op_cost(0);
2860 format %{ %}
2861 interface(CONST_INTER);
2862 %}
2863
2864 // Long Immediate: low 32-bit mask
2865 operand immL_32bits()
2866 %{
2867 predicate(n->get_long() == 0xFFFFFFFFL);
2868 match(ConL);
2869 op_cost(0);
2870 format %{ %}
2871 interface(CONST_INTER);
2872 %}
2873
2874 // 64 bit unit decrement
2875 operand immL_M1()
2876 %{
2877 predicate(n->get_long() == -1);
2878 match(ConL);
2879
2880 op_cost(0);
2881 format %{ %}
2882 interface(CONST_INTER);
2883 %}
2884
2885
2886 // 64 bit integer valid for add immediate
2887 operand immLAdd()
2888 %{
2889 predicate(Assembler::is_simm12(n->get_long()));
2890 match(ConL);
2891 op_cost(0);
2892 format %{ %}
2893 interface(CONST_INTER);
2894 %}
2895
2896 // 64 bit integer valid for sub immediate
2897 operand immLSub()
2898 %{
2899 predicate(Assembler::is_simm12(-(n->get_long())));
2900 match(ConL);
2901 op_cost(0);
2902 format %{ %}
2903 interface(CONST_INTER);
2904 %}
2905
2906 // Narrow pointer operands
2907 // Narrow Pointer Immediate
2908 operand immN()
2909 %{
2910 match(ConN);
2911
2912 op_cost(0);
2913 format %{ %}
2914 interface(CONST_INTER);
2915 %}
2916
2917 // Narrow Null Pointer Immediate
2918 operand immN0()
2919 %{
2920 predicate(n->get_narrowcon() == 0);
2921 match(ConN);
2922
2923 op_cost(0);
2924 format %{ %}
2925 interface(CONST_INTER);
2926 %}
2927
2928 operand immNKlass()
2929 %{
2930 match(ConNKlass);
2931
2932 op_cost(0);
2933 format %{ %}
2934 interface(CONST_INTER);
2935 %}
2936
2937 // Float and Double operands
2938 // Double Immediate
2939 operand immD()
2940 %{
2941 match(ConD);
2942 op_cost(0);
2943 format %{ %}
2944 interface(CONST_INTER);
2945 %}
2946
2947 // Double Immediate: +0.0d
2948 operand immD0()
2949 %{
2950 predicate(jlong_cast(n->getd()) == 0);
2951 match(ConD);
2952
2953 op_cost(0);
2954 format %{ %}
2955 interface(CONST_INTER);
2956 %}
2957
2958 // Float Immediate
2959 operand immF()
2960 %{
2961 match(ConF);
2962 op_cost(0);
2963 format %{ %}
2964 interface(CONST_INTER);
2965 %}
2966
2967 // Float Immediate: +0.0f.
2968 operand immF0()
2969 %{
2970 predicate(jint_cast(n->getf()) == 0);
2971 match(ConF);
2972
2973 op_cost(0);
2974 format %{ %}
2975 interface(CONST_INTER);
2976 %}
2977
2978 // Half Float Immediate
2979 operand immH()
2980 %{
2981 match(ConH);
2982
2983 op_cost(0);
2984 format %{ %}
2985 interface(CONST_INTER);
2986 %}
2987
2988 // Half Float Immediate: +0.0f.
2989 operand immH0()
2990 %{
2991 predicate(jint_cast(n->geth()) == 0);
2992 match(ConH);
2993
2994 op_cost(0);
2995 format %{ %}
2996 interface(CONST_INTER);
2997 %}
2998
2999 operand immIOffset()
3000 %{
3001 predicate(Assembler::is_simm12(n->get_int()));
3002 match(ConI);
3003 op_cost(0);
3004 format %{ %}
3005 interface(CONST_INTER);
3006 %}
3007
3008 operand immLOffset()
3009 %{
3010 predicate(Assembler::is_simm12(n->get_long()));
3011 match(ConL);
3012 op_cost(0);
3013 format %{ %}
3014 interface(CONST_INTER);
3015 %}
3016
3017 // Scale values
3018 operand immIScale()
3019 %{
3020 predicate(1 <= n->get_int() && (n->get_int() <= 3));
3021 match(ConI);
3022
3023 op_cost(0);
3024 format %{ %}
3025 interface(CONST_INTER);
3026 %}
3027
3028 // Integer 32 bit Register Operands
3029 operand iRegI()
3030 %{
3031 constraint(ALLOC_IN_RC(any_reg32));
3032 match(RegI);
3033 match(iRegINoSp);
3034 op_cost(0);
3035 format %{ %}
3036 interface(REG_INTER);
3037 %}
3038
3039 // Integer 32 bit Register not Special
3040 operand iRegINoSp()
3041 %{
3042 constraint(ALLOC_IN_RC(no_special_reg32));
3043 match(RegI);
3044 op_cost(0);
3045 format %{ %}
3046 interface(REG_INTER);
3047 %}
3048
3049 // Register R10 only
3050 operand iRegI_R10()
3051 %{
3052 constraint(ALLOC_IN_RC(int_r10_reg));
3053 match(RegI);
3054 match(iRegINoSp);
3055 op_cost(0);
3056 format %{ %}
3057 interface(REG_INTER);
3058 %}
3059
3060 // Register R12 only
3061 operand iRegI_R12()
3062 %{
3063 constraint(ALLOC_IN_RC(int_r12_reg));
3064 match(RegI);
3065 match(iRegINoSp);
3066 op_cost(0);
3067 format %{ %}
3068 interface(REG_INTER);
3069 %}
3070
3071 // Register R13 only
3072 operand iRegI_R13()
3073 %{
3074 constraint(ALLOC_IN_RC(int_r13_reg));
3075 match(RegI);
3076 match(iRegINoSp);
3077 op_cost(0);
3078 format %{ %}
3079 interface(REG_INTER);
3080 %}
3081
3082 // Register R14 only
3083 operand iRegI_R14()
3084 %{
3085 constraint(ALLOC_IN_RC(int_r14_reg));
3086 match(RegI);
3087 match(iRegINoSp);
3088 op_cost(0);
3089 format %{ %}
3090 interface(REG_INTER);
3091 %}
3092
3093 // Integer 64 bit Register Operands
3094 operand iRegL()
3095 %{
3096 constraint(ALLOC_IN_RC(any_reg));
3097 match(RegL);
3098 match(iRegLNoSp);
3099 op_cost(0);
3100 format %{ %}
3101 interface(REG_INTER);
3102 %}
3103
3104 // Integer 64 bit Register not Special
3105 operand iRegLNoSp()
3106 %{
3107 constraint(ALLOC_IN_RC(no_special_reg));
3108 match(RegL);
3109 match(iRegL_R10);
3110 format %{ %}
3111 interface(REG_INTER);
3112 %}
3113
3114 // Long 64 bit Register R29 only
3115 operand iRegL_R29()
3116 %{
3117 constraint(ALLOC_IN_RC(r29_reg));
3118 match(RegL);
3119 match(iRegLNoSp);
3120 op_cost(0);
3121 format %{ %}
3122 interface(REG_INTER);
3123 %}
3124
3125 // Long 64 bit Register R30 only
3126 operand iRegL_R30()
3127 %{
3128 constraint(ALLOC_IN_RC(r30_reg));
3129 match(RegL);
3130 match(iRegLNoSp);
3131 op_cost(0);
3132 format %{ %}
3133 interface(REG_INTER);
3134 %}
3135
3136 // Pointer Register Operands
3137 // Pointer Register
3138 operand iRegP()
3139 %{
3140 constraint(ALLOC_IN_RC(ptr_reg));
3141 match(RegP);
3142 match(iRegPNoSp);
3143 match(iRegP_R10);
3144 match(iRegP_R15);
3145 match(javaThread_RegP);
3146 op_cost(0);
3147 format %{ %}
3148 interface(REG_INTER);
3149 %}
3150
3151 // Pointer 64 bit Register not Special
3152 operand iRegPNoSp()
3153 %{
3154 constraint(ALLOC_IN_RC(no_special_ptr_reg));
3155 match(RegP);
3156 op_cost(0);
3157 format %{ %}
3158 interface(REG_INTER);
3159 %}
3160
3161 // This operand is not allowed to use fp even if
3162 // fp is not used to hold the frame pointer.
3163 operand iRegPNoSpNoFp()
3164 %{
3165 constraint(ALLOC_IN_RC(no_special_no_fp_ptr_reg));
3166 match(RegP);
3167 match(iRegPNoSp);
3168 op_cost(0);
3169 format %{ %}
3170 interface(REG_INTER);
3171 %}
3172
3173 operand iRegP_R10()
3174 %{
3175 constraint(ALLOC_IN_RC(r10_reg));
3176 match(RegP);
3177 // match(iRegP);
3178 match(iRegPNoSp);
3179 op_cost(0);
3180 format %{ %}
3181 interface(REG_INTER);
3182 %}
3183
3184 // Pointer 64 bit Register R11 only
3185 operand iRegP_R11()
3186 %{
3187 constraint(ALLOC_IN_RC(r11_reg));
3188 match(RegP);
3189 match(iRegPNoSp);
3190 op_cost(0);
3191 format %{ %}
3192 interface(REG_INTER);
3193 %}
3194
3195 operand iRegP_R12()
3196 %{
3197 constraint(ALLOC_IN_RC(r12_reg));
3198 match(RegP);
3199 // match(iRegP);
3200 match(iRegPNoSp);
3201 op_cost(0);
3202 format %{ %}
3203 interface(REG_INTER);
3204 %}
3205
3206 // Pointer 64 bit Register R13 only
3207 operand iRegP_R13()
3208 %{
3209 constraint(ALLOC_IN_RC(r13_reg));
3210 match(RegP);
3211 match(iRegPNoSp);
3212 op_cost(0);
3213 format %{ %}
3214 interface(REG_INTER);
3215 %}
3216
3217 operand iRegP_R14()
3218 %{
3219 constraint(ALLOC_IN_RC(r14_reg));
3220 match(RegP);
3221 // match(iRegP);
3222 match(iRegPNoSp);
3223 op_cost(0);
3224 format %{ %}
3225 interface(REG_INTER);
3226 %}
3227
3228 operand iRegP_R15()
3229 %{
3230 constraint(ALLOC_IN_RC(r15_reg));
3231 match(RegP);
3232 // match(iRegP);
3233 match(iRegPNoSp);
3234 op_cost(0);
3235 format %{ %}
3236 interface(REG_INTER);
3237 %}
3238
3239 operand iRegP_R16()
3240 %{
3241 constraint(ALLOC_IN_RC(r16_reg));
3242 match(RegP);
3243 match(iRegPNoSp);
3244 op_cost(0);
3245 format %{ %}
3246 interface(REG_INTER);
3247 %}
3248
3249 // Pointer 64 bit Register R28 only
3250 operand iRegP_R28()
3251 %{
3252 constraint(ALLOC_IN_RC(r28_reg));
3253 match(RegP);
3254 match(iRegPNoSp);
3255 op_cost(0);
3256 format %{ %}
3257 interface(REG_INTER);
3258 %}
3259
3260 // Pointer 64 bit Register R30 only
3261 operand iRegP_R30()
3262 %{
3263 constraint(ALLOC_IN_RC(r30_reg));
3264 match(RegP);
3265 match(iRegPNoSp);
3266 op_cost(0);
3267 format %{ %}
3268 interface(REG_INTER);
3269 %}
3270
3271 // Pointer 64 bit Register R31 only
3272 operand iRegP_R31()
3273 %{
3274 constraint(ALLOC_IN_RC(r31_reg));
3275 match(RegP);
3276 match(iRegPNoSp);
3277 op_cost(0);
3278 format %{ %}
3279 interface(REG_INTER);
3280 %}
3281
3282 // Pointer Register Operands
3283 // Narrow Pointer Register
3284 operand iRegN()
3285 %{
3286 constraint(ALLOC_IN_RC(any_reg32));
3287 match(RegN);
3288 match(iRegNNoSp);
3289 op_cost(0);
3290 format %{ %}
3291 interface(REG_INTER);
3292 %}
3293
3294 // Integer 64 bit Register not Special
3295 operand iRegNNoSp()
3296 %{
3297 constraint(ALLOC_IN_RC(no_special_reg32));
3298 match(RegN);
3299 op_cost(0);
3300 format %{ %}
3301 interface(REG_INTER);
3302 %}
3303
3304 // Long 64 bit Register R10 only
3305 operand iRegL_R10()
3306 %{
3307 constraint(ALLOC_IN_RC(r10_reg));
3308 match(RegL);
3309 match(iRegLNoSp);
3310 op_cost(0);
3311 format %{ %}
3312 interface(REG_INTER);
3313 %}
3314
3315 // Float Register
3316 // Float register operands
3317 operand fRegF()
3318 %{
3319 constraint(ALLOC_IN_RC(float_reg));
3320 match(RegF);
3321
3322 op_cost(0);
3323 format %{ %}
3324 interface(REG_INTER);
3325 %}
3326
3327 // Double Register
3328 // Double register operands
3329 operand fRegD()
3330 %{
3331 constraint(ALLOC_IN_RC(double_reg));
3332 match(RegD);
3333
3334 op_cost(0);
3335 format %{ %}
3336 interface(REG_INTER);
3337 %}
3338
3339 // Generic vector class. This will be used for
3340 // all vector operands.
3341 operand vReg()
3342 %{
3343 constraint(ALLOC_IN_RC(vectora_reg));
3344 match(VecA);
3345 op_cost(0);
3346 format %{ %}
3347 interface(REG_INTER);
3348 %}
3349
3350 operand vReg_V1()
3351 %{
3352 constraint(ALLOC_IN_RC(v1_reg));
3353 match(VecA);
3354 match(vReg);
3355 op_cost(0);
3356 format %{ %}
3357 interface(REG_INTER);
3358 %}
3359
3360 operand vReg_V2()
3361 %{
3362 constraint(ALLOC_IN_RC(v2_reg));
3363 match(VecA);
3364 match(vReg);
3365 op_cost(0);
3366 format %{ %}
3367 interface(REG_INTER);
3368 %}
3369
3370 operand vReg_V3()
3371 %{
3372 constraint(ALLOC_IN_RC(v3_reg));
3373 match(VecA);
3374 match(vReg);
3375 op_cost(0);
3376 format %{ %}
3377 interface(REG_INTER);
3378 %}
3379
3380 operand vReg_V4()
3381 %{
3382 constraint(ALLOC_IN_RC(v4_reg));
3383 match(VecA);
3384 match(vReg);
3385 op_cost(0);
3386 format %{ %}
3387 interface(REG_INTER);
3388 %}
3389
3390 operand vReg_V5()
3391 %{
3392 constraint(ALLOC_IN_RC(v5_reg));
3393 match(VecA);
3394 match(vReg);
3395 op_cost(0);
3396 format %{ %}
3397 interface(REG_INTER);
3398 %}
3399
3400 operand vReg_V6()
3401 %{
3402 constraint(ALLOC_IN_RC(v6_reg));
3403 match(VecA);
3404 match(vReg);
3405 op_cost(0);
3406 format %{ %}
3407 interface(REG_INTER);
3408 %}
3409
3410 operand vReg_V7()
3411 %{
3412 constraint(ALLOC_IN_RC(v7_reg));
3413 match(VecA);
3414 match(vReg);
3415 op_cost(0);
3416 format %{ %}
3417 interface(REG_INTER);
3418 %}
3419
3420 operand vReg_V8()
3421 %{
3422 constraint(ALLOC_IN_RC(v8_reg));
3423 match(VecA);
3424 match(vReg);
3425 op_cost(0);
3426 format %{ %}
3427 interface(REG_INTER);
3428 %}
3429
3430 operand vReg_V9()
3431 %{
3432 constraint(ALLOC_IN_RC(v9_reg));
3433 match(VecA);
3434 match(vReg);
3435 op_cost(0);
3436 format %{ %}
3437 interface(REG_INTER);
3438 %}
3439
3440 operand vReg_V10()
3441 %{
3442 constraint(ALLOC_IN_RC(v10_reg));
3443 match(VecA);
3444 match(vReg);
3445 op_cost(0);
3446 format %{ %}
3447 interface(REG_INTER);
3448 %}
3449
3450 operand vReg_V11()
3451 %{
3452 constraint(ALLOC_IN_RC(v11_reg));
3453 match(VecA);
3454 match(vReg);
3455 op_cost(0);
3456 format %{ %}
3457 interface(REG_INTER);
3458 %}
3459
3460 operand vRegMask()
3461 %{
3462 constraint(ALLOC_IN_RC(vmask_reg));
3463 match(RegVectMask);
3464 match(vRegMask_V0);
3465 op_cost(0);
3466 format %{ %}
3467 interface(REG_INTER);
3468 %}
3469
3470 // The mask value used to control execution of a masked
3471 // vector instruction is always supplied by vector register v0.
3472 operand vRegMask_V0()
3473 %{
3474 constraint(ALLOC_IN_RC(vmask_reg_v0));
3475 match(RegVectMask);
3476 match(vRegMask);
3477 op_cost(0);
3478 format %{ %}
3479 interface(REG_INTER);
3480 %}
3481
3482 // Java Thread Register
3483 operand javaThread_RegP(iRegP reg)
3484 %{
3485 constraint(ALLOC_IN_RC(java_thread_reg)); // java_thread_reg
3486 match(reg);
3487 op_cost(0);
3488 format %{ %}
3489 interface(REG_INTER);
3490 %}
3491
3492 //----------Memory Operands----------------------------------------------------
3493 // RISCV has only base_plus_offset and literal address mode, so no need to use
3494 // index and scale. Here set index as 0xffffffff and scale as 0x0.
3495 operand indirect(iRegP reg)
3496 %{
3497 constraint(ALLOC_IN_RC(ptr_reg));
3498 match(reg);
3499 op_cost(0);
3500 format %{ "[$reg]" %}
3501 interface(MEMORY_INTER) %{
3502 base($reg);
3503 index(0xffffffff);
3504 scale(0x0);
3505 disp(0x0);
3506 %}
3507 %}
3508
3509 operand indOffI(iRegP reg, immIOffset off)
3510 %{
3511 constraint(ALLOC_IN_RC(ptr_reg));
3512 match(AddP reg off);
3513 op_cost(0);
3514 format %{ "[$reg, $off]" %}
3515 interface(MEMORY_INTER) %{
3516 base($reg);
3517 index(0xffffffff);
3518 scale(0x0);
3519 disp($off);
3520 %}
3521 %}
3522
3523 operand indOffL(iRegP reg, immLOffset off)
3524 %{
3525 constraint(ALLOC_IN_RC(ptr_reg));
3526 match(AddP reg off);
3527 op_cost(0);
3528 format %{ "[$reg, $off]" %}
3529 interface(MEMORY_INTER) %{
3530 base($reg);
3531 index(0xffffffff);
3532 scale(0x0);
3533 disp($off);
3534 %}
3535 %}
3536
3537 operand indirectN(iRegN reg)
3538 %{
3539 predicate(CompressedOops::shift() == 0);
3540 constraint(ALLOC_IN_RC(ptr_reg));
3541 match(DecodeN reg);
3542 op_cost(0);
3543 format %{ "[$reg]\t# narrow" %}
3544 interface(MEMORY_INTER) %{
3545 base($reg);
3546 index(0xffffffff);
3547 scale(0x0);
3548 disp(0x0);
3549 %}
3550 %}
3551
3552 operand indOffIN(iRegN reg, immIOffset off)
3553 %{
3554 predicate(CompressedOops::shift() == 0);
3555 constraint(ALLOC_IN_RC(ptr_reg));
3556 match(AddP (DecodeN reg) off);
3557 op_cost(0);
3558 format %{ "[$reg, $off]\t# narrow" %}
3559 interface(MEMORY_INTER) %{
3560 base($reg);
3561 index(0xffffffff);
3562 scale(0x0);
3563 disp($off);
3564 %}
3565 %}
3566
3567 operand indOffLN(iRegN reg, immLOffset off)
3568 %{
3569 predicate(CompressedOops::shift() == 0);
3570 constraint(ALLOC_IN_RC(ptr_reg));
3571 match(AddP (DecodeN reg) off);
3572 op_cost(0);
3573 format %{ "[$reg, $off]\t# narrow" %}
3574 interface(MEMORY_INTER) %{
3575 base($reg);
3576 index(0xffffffff);
3577 scale(0x0);
3578 disp($off);
3579 %}
3580 %}
3581
3582 //----------Special Memory Operands--------------------------------------------
3583 // Stack Slot Operand - This operand is used for loading and storing temporary
3584 // values on the stack where a match requires a value to
3585 // flow through memory.
3586 operand stackSlotI(sRegI reg)
3587 %{
3588 constraint(ALLOC_IN_RC(stack_slots));
3589 // No match rule because this operand is only generated in matching
3590 // match(RegI);
3591 format %{ "[$reg]" %}
3592 interface(MEMORY_INTER) %{
3593 base(0x02); // RSP
3594 index(0xffffffff); // No Index
3595 scale(0x0); // No Scale
3596 disp($reg); // Stack Offset
3597 %}
3598 %}
3599
3600 operand stackSlotF(sRegF reg)
3601 %{
3602 constraint(ALLOC_IN_RC(stack_slots));
3603 // No match rule because this operand is only generated in matching
3604 // match(RegF);
3605 format %{ "[$reg]" %}
3606 interface(MEMORY_INTER) %{
3607 base(0x02); // RSP
3608 index(0xffffffff); // No Index
3609 scale(0x0); // No Scale
3610 disp($reg); // Stack Offset
3611 %}
3612 %}
3613
3614 operand stackSlotD(sRegD reg)
3615 %{
3616 constraint(ALLOC_IN_RC(stack_slots));
3617 // No match rule because this operand is only generated in matching
3618 // match(RegD);
3619 format %{ "[$reg]" %}
3620 interface(MEMORY_INTER) %{
3621 base(0x02); // RSP
3622 index(0xffffffff); // No Index
3623 scale(0x0); // No Scale
3624 disp($reg); // Stack Offset
3625 %}
3626 %}
3627
3628 operand stackSlotL(sRegL reg)
3629 %{
3630 constraint(ALLOC_IN_RC(stack_slots));
3631 // No match rule because this operand is only generated in matching
3632 // match(RegL);
3633 format %{ "[$reg]" %}
3634 interface(MEMORY_INTER) %{
3635 base(0x02); // RSP
3636 index(0xffffffff); // No Index
3637 scale(0x0); // No Scale
3638 disp($reg); // Stack Offset
3639 %}
3640 %}
3641
3642 // Special operand allowing long args to int ops to be truncated for free
3643
3644 operand iRegL2I(iRegL reg) %{
3645
3646 op_cost(0);
3647
3648 match(ConvL2I reg);
3649
3650 format %{ "l2i($reg)" %}
3651
3652 interface(REG_INTER)
3653 %}
3654
3655
3656 // Comparison Operands
3657 // NOTE: Label is a predefined operand which should not be redefined in
3658 // the AD file. It is generically handled within the ADLC.
3659
3660 //----------Conditional Branch Operands----------------------------------------
3661 // Comparison Op - This is the operation of the comparison, and is limited to
3662 // the following set of codes:
3663 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
3664 //
3665 // Other attributes of the comparison, such as unsignedness, are specified
3666 // by the comparison instruction that sets a condition code flags register.
3667 // That result is represented by a flags operand whose subtype is appropriate
3668 // to the unsignedness (etc.) of the comparison.
3669 //
3670 // Later, the instruction which matches both the Comparison Op (a Bool) and
3671 // the flags (produced by the Cmp) specifies the coding of the comparison op
3672 // by matching a specific subtype of Bool operand below, such as cmpOpU.
3673
3674
3675 // used for signed integral comparisons and fp comparisons
3676 operand cmpOp()
3677 %{
3678 match(Bool);
3679
3680 format %{ "" %}
3681
3682 // the values in interface derives from struct BoolTest::mask
3683 interface(COND_INTER) %{
3684 equal(0x0, "eq");
3685 greater(0x1, "gt");
3686 overflow(0x2, "overflow");
3687 less(0x3, "lt");
3688 not_equal(0x4, "ne");
3689 less_equal(0x5, "le");
3690 no_overflow(0x6, "no_overflow");
3691 greater_equal(0x7, "ge");
3692 %}
3693 %}
3694
3695 // used for unsigned integral comparisons
3696 operand cmpOpU()
3697 %{
3698 match(Bool);
3699
3700 format %{ "" %}
3701 // the values in interface derives from struct BoolTest::mask
3702 interface(COND_INTER) %{
3703 equal(0x0, "eq");
3704 greater(0x1, "gtu");
3705 overflow(0x2, "overflow");
3706 less(0x3, "ltu");
3707 not_equal(0x4, "ne");
3708 less_equal(0x5, "leu");
3709 no_overflow(0x6, "no_overflow");
3710 greater_equal(0x7, "geu");
3711 %}
3712 %}
3713
3714 // used for certain integral comparisons which can be
3715 // converted to bxx instructions
3716 operand cmpOpEqNe()
3717 %{
3718 match(Bool);
3719 op_cost(0);
3720 predicate(n->as_Bool()->_test._test == BoolTest::ne ||
3721 n->as_Bool()->_test._test == BoolTest::eq);
3722
3723 format %{ "" %}
3724 interface(COND_INTER) %{
3725 equal(0x0, "eq");
3726 greater(0x1, "gt");
3727 overflow(0x2, "overflow");
3728 less(0x3, "lt");
3729 not_equal(0x4, "ne");
3730 less_equal(0x5, "le");
3731 no_overflow(0x6, "no_overflow");
3732 greater_equal(0x7, "ge");
3733 %}
3734 %}
3735
3736 operand cmpOpULtGe()
3737 %{
3738 match(Bool);
3739 op_cost(0);
3740 predicate(n->as_Bool()->_test._test == BoolTest::lt ||
3741 n->as_Bool()->_test._test == BoolTest::ge);
3742
3743 format %{ "" %}
3744 interface(COND_INTER) %{
3745 equal(0x0, "eq");
3746 greater(0x1, "gtu");
3747 overflow(0x2, "overflow");
3748 less(0x3, "ltu");
3749 not_equal(0x4, "ne");
3750 less_equal(0x5, "leu");
3751 no_overflow(0x6, "no_overflow");
3752 greater_equal(0x7, "geu");
3753 %}
3754 %}
3755
3756 operand cmpOpUEqNeLeGt()
3757 %{
3758 match(Bool);
3759 op_cost(0);
3760 predicate(n->as_Bool()->_test._test == BoolTest::ne ||
3761 n->as_Bool()->_test._test == BoolTest::eq ||
3762 n->as_Bool()->_test._test == BoolTest::le ||
3763 n->as_Bool()->_test._test == BoolTest::gt);
3764
3765 format %{ "" %}
3766 interface(COND_INTER) %{
3767 equal(0x0, "eq");
3768 greater(0x1, "gtu");
3769 overflow(0x2, "overflow");
3770 less(0x3, "ltu");
3771 not_equal(0x4, "ne");
3772 less_equal(0x5, "leu");
3773 no_overflow(0x6, "no_overflow");
3774 greater_equal(0x7, "geu");
3775 %}
3776 %}
3777
3778
3779 // Flags register, used as output of compare logic
3780 operand rFlagsReg()
3781 %{
3782 constraint(ALLOC_IN_RC(reg_flags));
3783 match(RegFlags);
3784
3785 op_cost(0);
3786 format %{ "RFLAGS" %}
3787 interface(REG_INTER);
3788 %}
3789
3790 // Special Registers
3791
3792 // Method Register
3793 operand inline_cache_RegP(iRegP reg)
3794 %{
3795 constraint(ALLOC_IN_RC(method_reg)); // inline_cache_reg
3796 match(reg);
3797 match(iRegPNoSp);
3798 op_cost(0);
3799 format %{ %}
3800 interface(REG_INTER);
3801 %}
3802
3803 //----------OPERAND CLASSES----------------------------------------------------
3804 // Operand Classes are groups of operands that are used as to simplify
3805 // instruction definitions by not requiring the AD writer to specify
3806 // separate instructions for every form of operand when the
3807 // instruction accepts multiple operand types with the same basic
3808 // encoding and format. The classic case of this is memory operands.
3809
3810 // memory is used to define read/write location for load/store
3811 // instruction defs. we can turn a memory op into an Address
3812
3813 opclass memory(indirect, indOffI, indOffL, indirectN, indOffIN, indOffLN);
3814
3815 // iRegIorL2I is used for src inputs in rules for 32 bit int (I)
3816 // operations. it allows the src to be either an iRegI or a (ConvL2I
3817 // iRegL). in the latter case the l2i normally planted for a ConvL2I
3818 // can be elided because the 32-bit instruction will just employ the
3819 // lower 32 bits anyway.
3820 //
3821 // n.b. this does not elide all L2I conversions. if the truncated
3822 // value is consumed by more than one operation then the ConvL2I
3823 // cannot be bundled into the consuming nodes so an l2i gets planted
3824 // (actually an addiw $dst, $src, 0) and the downstream instructions
3825 // consume the result of the L2I as an iRegI input. That's a shame since
3826 // the addiw is actually redundant but its not too costly.
3827
3828 opclass iRegIorL2I(iRegI, iRegL2I);
3829 opclass iRegIorL(iRegI, iRegL);
3830 opclass iRegNorP(iRegN, iRegP);
3831 opclass iRegILNP(iRegI, iRegL, iRegN, iRegP);
3832 opclass iRegILNPNoSp(iRegINoSp, iRegLNoSp, iRegNNoSp, iRegPNoSp);
3833 opclass immIorL(immI, immL);
3834
3835 //----------PIPELINE-----------------------------------------------------------
3836 // Rules which define the behavior of the target architectures pipeline.
3837
3838 // For specific pipelines, e.g. generic RISC-V, define the stages of that pipeline
3839 //pipe_desc(ID, EX, MEM, WR);
3840 #define ID S0
3841 #define EX S1
3842 #define MEM S2
3843 #define WR S3
3844
3845 // Integer ALU reg operation
3846 pipeline %{
3847
3848 attributes %{
3849 // RISC-V instructions are of length 2 or 4 bytes.
3850 variable_size_instructions;
3851 instruction_unit_size = 2;
3852
3853 // Up to 4 instructions per bundle
3854 max_instructions_per_bundle = 4;
3855
3856 // The RISC-V processor fetches 64 bytes...
3857 instruction_fetch_unit_size = 64;
3858
3859 // ...in one line.
3860 instruction_fetch_units = 1;
3861 %}
3862
3863 // We don't use an actual pipeline model so don't care about resources
3864 // or description. we do use pipeline classes to introduce fixed
3865 // latencies
3866
3867 //----------RESOURCES----------------------------------------------------------
3868 // Resources are the functional units available to the machine
3869
3870 // Generic RISC-V pipeline
3871 // 1 decoder
3872 // 1 instruction decoded per cycle
3873 // 1 load/store ops per cycle, 1 branch, 1 FPU
3874 // 1 mul, 1 div
3875
3876 resources ( DECODE,
3877 ALU,
3878 MUL,
3879 DIV,
3880 BRANCH,
3881 LDST,
3882 FPU);
3883
3884 //----------PIPELINE DESCRIPTION-----------------------------------------------
3885 // Pipeline Description specifies the stages in the machine's pipeline
3886
3887 // Define the pipeline as a generic 6 stage pipeline
3888 pipe_desc(S0, S1, S2, S3, S4, S5);
3889
3890 //----------PIPELINE CLASSES---------------------------------------------------
3891 // Pipeline Classes describe the stages in which input and output are
3892 // referenced by the hardware pipeline.
3893
3894 pipe_class fp_dop_reg_reg_s(fRegF dst, fRegF src1, fRegF src2)
3895 %{
3896 single_instruction;
3897 src1 : S1(read);
3898 src2 : S2(read);
3899 dst : S5(write);
3900 DECODE : ID;
3901 FPU : S5;
3902 %}
3903
3904 pipe_class fp_dop_reg_reg_d(fRegD dst, fRegD src1, fRegD src2)
3905 %{
3906 src1 : S1(read);
3907 src2 : S2(read);
3908 dst : S5(write);
3909 DECODE : ID;
3910 FPU : S5;
3911 %}
3912
3913 pipe_class fp_uop_s(fRegF dst, fRegF src)
3914 %{
3915 single_instruction;
3916 src : S1(read);
3917 dst : S5(write);
3918 DECODE : ID;
3919 FPU : S5;
3920 %}
3921
3922 pipe_class fp_uop_d(fRegD dst, fRegD src)
3923 %{
3924 single_instruction;
3925 src : S1(read);
3926 dst : S5(write);
3927 DECODE : ID;
3928 FPU : S5;
3929 %}
3930
3931 pipe_class fp_d2f(fRegF dst, fRegD src)
3932 %{
3933 single_instruction;
3934 src : S1(read);
3935 dst : S5(write);
3936 DECODE : ID;
3937 FPU : S5;
3938 %}
3939
3940 pipe_class fp_f2d(fRegD dst, fRegF src)
3941 %{
3942 single_instruction;
3943 src : S1(read);
3944 dst : S5(write);
3945 DECODE : ID;
3946 FPU : S5;
3947 %}
3948
3949 pipe_class fp_f2i(iRegINoSp dst, fRegF src)
3950 %{
3951 single_instruction;
3952 src : S1(read);
3953 dst : S5(write);
3954 DECODE : ID;
3955 FPU : S5;
3956 %}
3957
3958 pipe_class fp_f2l(iRegLNoSp dst, fRegF src)
3959 %{
3960 single_instruction;
3961 src : S1(read);
3962 dst : S5(write);
3963 DECODE : ID;
3964 FPU : S5;
3965 %}
3966
3967 pipe_class fp_i2f(fRegF dst, iRegIorL2I src)
3968 %{
3969 single_instruction;
3970 src : S1(read);
3971 dst : S5(write);
3972 DECODE : ID;
3973 FPU : S5;
3974 %}
3975
3976 pipe_class fp_l2f(fRegF dst, iRegL src)
3977 %{
3978 single_instruction;
3979 src : S1(read);
3980 dst : S5(write);
3981 DECODE : ID;
3982 FPU : S5;
3983 %}
3984
3985 pipe_class fp_d2i(iRegINoSp dst, fRegD src)
3986 %{
3987 single_instruction;
3988 src : S1(read);
3989 dst : S5(write);
3990 DECODE : ID;
3991 FPU : S5;
3992 %}
3993
3994 pipe_class fp_d2l(iRegLNoSp dst, fRegD src)
3995 %{
3996 single_instruction;
3997 src : S1(read);
3998 dst : S5(write);
3999 DECODE : ID;
4000 FPU : S5;
4001 %}
4002
4003 pipe_class fp_i2d(fRegD dst, iRegIorL2I src)
4004 %{
4005 single_instruction;
4006 src : S1(read);
4007 dst : S5(write);
4008 DECODE : ID;
4009 FPU : S5;
4010 %}
4011
4012 pipe_class fp_l2d(fRegD dst, iRegIorL2I src)
4013 %{
4014 single_instruction;
4015 src : S1(read);
4016 dst : S5(write);
4017 DECODE : ID;
4018 FPU : S5;
4019 %}
4020
4021 pipe_class fp_div_s(fRegF dst, fRegF src1, fRegF src2)
4022 %{
4023 single_instruction;
4024 src1 : S1(read);
4025 src2 : S2(read);
4026 dst : S5(write);
4027 DECODE : ID;
4028 FPU : S5;
4029 %}
4030
4031 pipe_class fp_div_d(fRegD dst, fRegD src1, fRegD src2)
4032 %{
4033 single_instruction;
4034 src1 : S1(read);
4035 src2 : S2(read);
4036 dst : S5(write);
4037 DECODE : ID;
4038 FPU : S5;
4039 %}
4040
4041 pipe_class fp_sqrt_s(fRegF dst, fRegF src)
4042 %{
4043 single_instruction;
4044 src : S1(read);
4045 dst : S5(write);
4046 DECODE : ID;
4047 FPU : S5;
4048 %}
4049
4050 pipe_class fp_sqrt_d(fRegD dst, fRegD src)
4051 %{
4052 single_instruction;
4053 src : S1(read);
4054 dst : S5(write);
4055 DECODE : ID;
4056 FPU : S5;
4057 %}
4058
4059 pipe_class fp_load_constant_s(fRegF dst)
4060 %{
4061 single_instruction;
4062 dst : S5(write);
4063 DECODE : ID;
4064 FPU : S5;
4065 %}
4066
4067 pipe_class fp_load_constant_d(fRegD dst)
4068 %{
4069 single_instruction;
4070 dst : S5(write);
4071 DECODE : ID;
4072 FPU : S5;
4073 %}
4074
4075 pipe_class fp_load_mem_s(fRegF dst, memory mem)
4076 %{
4077 single_instruction;
4078 mem : S1(read);
4079 dst : S5(write);
4080 DECODE : ID;
4081 LDST : MEM;
4082 %}
4083
4084 pipe_class fp_load_mem_d(fRegD dst, memory mem)
4085 %{
4086 single_instruction;
4087 mem : S1(read);
4088 dst : S5(write);
4089 DECODE : ID;
4090 LDST : MEM;
4091 %}
4092
4093 pipe_class fp_store_reg_s(fRegF src, memory mem)
4094 %{
4095 single_instruction;
4096 src : S1(read);
4097 mem : S5(write);
4098 DECODE : ID;
4099 LDST : MEM;
4100 %}
4101
4102 pipe_class fp_store_reg_d(fRegD src, memory mem)
4103 %{
4104 single_instruction;
4105 src : S1(read);
4106 mem : S5(write);
4107 DECODE : ID;
4108 LDST : MEM;
4109 %}
4110
4111 //------- Integer ALU operations --------------------------
4112
4113 // Integer ALU reg-reg operation
4114 // Operands needs in ID, result generated in EX
4115 // E.g. ADD Rd, Rs1, Rs2
4116 pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2)
4117 %{
4118 single_instruction;
4119 dst : EX(write);
4120 src1 : ID(read);
4121 src2 : ID(read);
4122 DECODE : ID;
4123 ALU : EX;
4124 %}
4125
4126 // Integer ALU reg operation with constant shift
4127 // E.g. SLLI Rd, Rs1, #shift
4128 pipe_class ialu_reg_shift(iRegI dst, iRegI src1)
4129 %{
4130 single_instruction;
4131 dst : EX(write);
4132 src1 : ID(read);
4133 DECODE : ID;
4134 ALU : EX;
4135 %}
4136
4137 // Integer ALU reg-reg operation with variable shift
4138 // both operands must be available in ID
4139 // E.g. SLL Rd, Rs1, Rs2
4140 pipe_class ialu_reg_reg_vshift(iRegI dst, iRegI src1, iRegI src2)
4141 %{
4142 single_instruction;
4143 dst : EX(write);
4144 src1 : ID(read);
4145 src2 : ID(read);
4146 DECODE : ID;
4147 ALU : EX;
4148 %}
4149
4150 // Integer ALU reg operation
4151 // E.g. NEG Rd, Rs2
4152 pipe_class ialu_reg(iRegI dst, iRegI src)
4153 %{
4154 single_instruction;
4155 dst : EX(write);
4156 src : ID(read);
4157 DECODE : ID;
4158 ALU : EX;
4159 %}
4160
4161 // Integer ALU reg immediate operation
4162 // E.g. ADDI Rd, Rs1, #imm
4163 pipe_class ialu_reg_imm(iRegI dst, iRegI src1)
4164 %{
4165 single_instruction;
4166 dst : EX(write);
4167 src1 : ID(read);
4168 DECODE : ID;
4169 ALU : EX;
4170 %}
4171
4172 // Integer ALU immediate operation (no source operands)
4173 // E.g. LI Rd, #imm
4174 pipe_class ialu_imm(iRegI dst)
4175 %{
4176 single_instruction;
4177 dst : EX(write);
4178 DECODE : ID;
4179 ALU : EX;
4180 %}
4181
4182 //------- Multiply pipeline operations --------------------
4183
4184 // Multiply reg-reg
4185 // E.g. MULW Rd, Rs1, Rs2
4186 pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2)
4187 %{
4188 single_instruction;
4189 dst : WR(write);
4190 src1 : ID(read);
4191 src2 : ID(read);
4192 DECODE : ID;
4193 MUL : WR;
4194 %}
4195
4196 // E.g. MUL RD, Rs1, Rs2
4197 pipe_class lmul_reg_reg(iRegL dst, iRegL src1, iRegL src2)
4198 %{
4199 single_instruction;
4200 fixed_latency(3); // Maximum latency for 64 bit mul
4201 dst : WR(write);
4202 src1 : ID(read);
4203 src2 : ID(read);
4204 DECODE : ID;
4205 MUL : WR;
4206 %}
4207
4208 //------- Divide pipeline operations --------------------
4209
4210 // E.g. DIVW Rd, Rs1, Rs2
4211 pipe_class idiv_reg_reg(iRegI dst, iRegI src1, iRegI src2)
4212 %{
4213 single_instruction;
4214 fixed_latency(8); // Maximum latency for 32 bit divide
4215 dst : WR(write);
4216 src1 : ID(read);
4217 src2 : ID(read);
4218 DECODE : ID;
4219 DIV : WR;
4220 %}
4221
4222 // E.g. DIV RD, Rs1, Rs2
4223 pipe_class ldiv_reg_reg(iRegL dst, iRegL src1, iRegL src2)
4224 %{
4225 single_instruction;
4226 fixed_latency(16); // Maximum latency for 64 bit divide
4227 dst : WR(write);
4228 src1 : ID(read);
4229 src2 : ID(read);
4230 DECODE : ID;
4231 DIV : WR;
4232 %}
4233
4234 //------- Load pipeline operations ------------------------
4235
4236 // Load - prefetch
4237 // Eg. PREFETCH_W mem
4238 pipe_class iload_prefetch(memory mem)
4239 %{
4240 single_instruction;
4241 mem : ID(read);
4242 DECODE : ID;
4243 LDST : MEM;
4244 %}
4245
4246 // Load - reg, mem
4247 // E.g. LA Rd, mem
4248 pipe_class iload_reg_mem(iRegI dst, memory mem)
4249 %{
4250 single_instruction;
4251 dst : WR(write);
4252 mem : ID(read);
4253 DECODE : ID;
4254 LDST : MEM;
4255 %}
4256
4257 // Load - reg, reg
4258 // E.g. LD Rd, Rs
4259 pipe_class iload_reg_reg(iRegI dst, iRegI src)
4260 %{
4261 single_instruction;
4262 dst : WR(write);
4263 src : ID(read);
4264 DECODE : ID;
4265 LDST : MEM;
4266 %}
4267
4268 //------- Store pipeline operations -----------------------
4269
4270 // Store - zr, mem
4271 // E.g. SD zr, mem
4272 pipe_class istore_mem(memory mem)
4273 %{
4274 single_instruction;
4275 mem : ID(read);
4276 DECODE : ID;
4277 LDST : MEM;
4278 %}
4279
4280 // Store - reg, mem
4281 // E.g. SD Rs, mem
4282 pipe_class istore_reg_mem(iRegI src, memory mem)
4283 %{
4284 single_instruction;
4285 mem : ID(read);
4286 src : EX(read);
4287 DECODE : ID;
4288 LDST : MEM;
4289 %}
4290
4291 // Store - reg, reg
4292 // E.g. SD Rs2, Rs1
4293 pipe_class istore_reg_reg(iRegI dst, iRegI src)
4294 %{
4295 single_instruction;
4296 dst : ID(read);
4297 src : EX(read);
4298 DECODE : ID;
4299 LDST : MEM;
4300 %}
4301
4302 //------- Control transfer pipeline operations ------------
4303
4304 // Branch
4305 pipe_class pipe_branch()
4306 %{
4307 single_instruction;
4308 DECODE : ID;
4309 BRANCH : EX;
4310 %}
4311
4312 // Branch
4313 pipe_class pipe_branch_reg(iRegI src)
4314 %{
4315 single_instruction;
4316 src : ID(read);
4317 DECODE : ID;
4318 BRANCH : EX;
4319 %}
4320
4321 // Compare & Branch
4322 // E.g. BEQ Rs1, Rs2, L
4323 pipe_class pipe_cmp_branch(iRegI src1, iRegI src2)
4324 %{
4325 single_instruction;
4326 src1 : ID(read);
4327 src2 : ID(read);
4328 DECODE : ID;
4329 BRANCH : EX;
4330 %}
4331
4332 // E.g. BEQZ Rs, L
4333 pipe_class pipe_cmpz_branch(iRegI src)
4334 %{
4335 single_instruction;
4336 src : ID(read);
4337 DECODE : ID;
4338 BRANCH : EX;
4339 %}
4340
4341 //------- Synchronisation operations ----------------------
4342 // Any operation requiring serialization
4343 // E.g. FENCE/Atomic Ops/Load Acquire/Store Release
4344 pipe_class pipe_serial()
4345 %{
4346 single_instruction;
4347 force_serialization;
4348 fixed_latency(16);
4349 DECODE : ID;
4350 LDST : MEM;
4351 %}
4352
4353 pipe_class pipe_slow()
4354 %{
4355 instruction_count(10);
4356 multiple_bundles;
4357 force_serialization;
4358 fixed_latency(16);
4359 DECODE : ID;
4360 LDST : MEM;
4361 %}
4362
4363 // The real do-nothing guy
4364 pipe_class real_empty()
4365 %{
4366 instruction_count(0);
4367 %}
4368
4369 // Empty pipeline class
4370 pipe_class pipe_class_empty()
4371 %{
4372 single_instruction;
4373 fixed_latency(0);
4374 %}
4375
4376 // Default pipeline class.
4377 pipe_class pipe_class_default()
4378 %{
4379 single_instruction;
4380 fixed_latency(2);
4381 %}
4382
4383 // Pipeline class for compares.
4384 pipe_class pipe_class_compare()
4385 %{
4386 single_instruction;
4387 fixed_latency(16);
4388 %}
4389
4390 // Pipeline class for memory operations.
4391 pipe_class pipe_class_memory()
4392 %{
4393 single_instruction;
4394 fixed_latency(16);
4395 %}
4396
4397 // Pipeline class for call.
4398 pipe_class pipe_class_call()
4399 %{
4400 single_instruction;
4401 fixed_latency(100);
4402 %}
4403
4404 // Define the class for the Nop node.
4405 define %{
4406 MachNop = pipe_class_empty;
4407 %}
4408 %}
4409 //----------INSTRUCTIONS-------------------------------------------------------
4410 //
4411 // match -- States which machine-independent subtree may be replaced
4412 // by this instruction.
4413 // ins_cost -- The estimated cost of this instruction is used by instruction
4414 // selection to identify a minimum cost tree of machine
4415 // instructions that matches a tree of machine-independent
4416 // instructions.
4417 // format -- A string providing the disassembly for this instruction.
4418 // The value of an instruction's operand may be inserted
4419 // by referring to it with a '$' prefix.
4420 // opcode -- Three instruction opcodes may be provided. These are referred
4421 // to within an encode class as $primary, $secondary, and $tertiary
4422 // rrspectively. The primary opcode is commonly used to
4423 // indicate the type of machine instruction, while secondary
4424 // and tertiary are often used for prefix options or addressing
4425 // modes.
4426 // ins_encode -- A list of encode classes with parameters. The encode class
4427 // name must have been defined in an 'enc_class' specification
4428 // in the encode section of the architecture description.
4429
4430 // ============================================================================
4431 // Memory (Load/Store) Instructions
4432
4433 // Load Instructions
4434
4435 // Load Byte (8 bit signed)
4436 instruct loadB(iRegINoSp dst, memory mem)
4437 %{
4438 match(Set dst (LoadB mem));
4439
4440 ins_cost(LOAD_COST);
4441 format %{ "lb $dst, $mem\t# byte, #@loadB" %}
4442
4443 ins_encode %{
4444 __ lb(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4445 %}
4446
4447 ins_pipe(iload_reg_mem);
4448 %}
4449
4450 // Load Byte (8 bit signed) into long
4451 instruct loadB2L(iRegLNoSp dst, memory mem)
4452 %{
4453 match(Set dst (ConvI2L (LoadB mem)));
4454
4455 ins_cost(LOAD_COST);
4456 format %{ "lb $dst, $mem\t# byte, #@loadB2L" %}
4457
4458 ins_encode %{
4459 __ lb(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4460 %}
4461
4462 ins_pipe(iload_reg_mem);
4463 %}
4464
4465 // Load Byte (8 bit unsigned)
4466 instruct loadUB(iRegINoSp dst, memory mem)
4467 %{
4468 match(Set dst (LoadUB mem));
4469
4470 ins_cost(LOAD_COST);
4471 format %{ "lbu $dst, $mem\t# byte, #@loadUB" %}
4472
4473 ins_encode %{
4474 __ lbu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4475 %}
4476
4477 ins_pipe(iload_reg_mem);
4478 %}
4479
4480 // Load Byte (8 bit unsigned) into long
4481 instruct loadUB2L(iRegLNoSp dst, memory mem)
4482 %{
4483 match(Set dst (ConvI2L (LoadUB mem)));
4484
4485 ins_cost(LOAD_COST);
4486 format %{ "lbu $dst, $mem\t# byte, #@loadUB2L" %}
4487
4488 ins_encode %{
4489 __ lbu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4490 %}
4491
4492 ins_pipe(iload_reg_mem);
4493 %}
4494
4495 // Load Short (16 bit signed)
4496 instruct loadS(iRegINoSp dst, memory mem)
4497 %{
4498 match(Set dst (LoadS mem));
4499
4500 ins_cost(LOAD_COST);
4501 format %{ "lh $dst, $mem\t# short, #@loadS" %}
4502
4503 ins_encode %{
4504 __ lh(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4505 %}
4506
4507 ins_pipe(iload_reg_mem);
4508 %}
4509
4510 // Load Short (16 bit signed) into long
4511 instruct loadS2L(iRegLNoSp dst, memory mem)
4512 %{
4513 match(Set dst (ConvI2L (LoadS mem)));
4514
4515 ins_cost(LOAD_COST);
4516 format %{ "lh $dst, $mem\t# short, #@loadS2L" %}
4517
4518 ins_encode %{
4519 __ lh(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4520 %}
4521
4522 ins_pipe(iload_reg_mem);
4523 %}
4524
4525 // Load Char (16 bit unsigned)
4526 instruct loadUS(iRegINoSp dst, memory mem)
4527 %{
4528 match(Set dst (LoadUS mem));
4529
4530 ins_cost(LOAD_COST);
4531 format %{ "lhu $dst, $mem\t# short, #@loadUS" %}
4532
4533 ins_encode %{
4534 __ lhu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4535 %}
4536
4537 ins_pipe(iload_reg_mem);
4538 %}
4539
4540 // Load Short/Char (16 bit unsigned) into long
4541 instruct loadUS2L(iRegLNoSp dst, memory mem)
4542 %{
4543 match(Set dst (ConvI2L (LoadUS mem)));
4544
4545 ins_cost(LOAD_COST);
4546 format %{ "lhu $dst, $mem\t# short, #@loadUS2L" %}
4547
4548 ins_encode %{
4549 __ lhu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4550 %}
4551
4552 ins_pipe(iload_reg_mem);
4553 %}
4554
4555 // Load Integer (32 bit signed)
4556 instruct loadI(iRegINoSp dst, memory mem)
4557 %{
4558 match(Set dst (LoadI mem));
4559
4560 ins_cost(LOAD_COST);
4561 format %{ "lw $dst, $mem\t# int, #@loadI" %}
4562
4563 ins_encode %{
4564 __ lw(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4565 %}
4566
4567 ins_pipe(iload_reg_mem);
4568 %}
4569
4570 // Load Integer (32 bit signed) into long
4571 instruct loadI2L(iRegLNoSp dst, memory mem)
4572 %{
4573 match(Set dst (ConvI2L (LoadI mem)));
4574
4575 ins_cost(LOAD_COST);
4576 format %{ "lw $dst, $mem\t# int, #@loadI2L" %}
4577
4578 ins_encode %{
4579 __ lw(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4580 %}
4581
4582 ins_pipe(iload_reg_mem);
4583 %}
4584
4585 // Load Integer (32 bit unsigned) into long
4586 instruct loadUI2L(iRegLNoSp dst, memory mem, immL_32bits mask)
4587 %{
4588 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
4589
4590 ins_cost(LOAD_COST);
4591 format %{ "lwu $dst, $mem\t# int, #@loadUI2L" %}
4592
4593 ins_encode %{
4594 __ lwu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4595 %}
4596
4597 ins_pipe(iload_reg_mem);
4598 %}
4599
4600 // Load Long (64 bit signed)
4601 instruct loadL(iRegLNoSp dst, memory mem)
4602 %{
4603 match(Set dst (LoadL mem));
4604
4605 ins_cost(LOAD_COST);
4606 format %{ "ld $dst, $mem\t# int, #@loadL" %}
4607
4608 ins_encode %{
4609 __ ld(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4610 %}
4611
4612 ins_pipe(iload_reg_mem);
4613 %}
4614
4615 // Load Range
4616 instruct loadRange(iRegINoSp dst, memory mem)
4617 %{
4618 match(Set dst (LoadRange mem));
4619
4620 ins_cost(LOAD_COST);
4621 format %{ "lwu $dst, $mem\t# range, #@loadRange" %}
4622
4623 ins_encode %{
4624 __ lwu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4625 %}
4626
4627 ins_pipe(iload_reg_mem);
4628 %}
4629
4630 // Load Pointer
4631 instruct loadP(iRegPNoSp dst, memory mem)
4632 %{
4633 match(Set dst (LoadP mem));
4634 predicate(n->as_Load()->barrier_data() == 0);
4635
4636 ins_cost(LOAD_COST);
4637 format %{ "ld $dst, $mem\t# ptr, #@loadP" %}
4638
4639 ins_encode %{
4640 __ ld(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4641 %}
4642
4643 ins_pipe(iload_reg_mem);
4644 %}
4645
4646 // Load Compressed Pointer
4647 instruct loadN(iRegNNoSp dst, memory mem)
4648 %{
4649 predicate(n->as_Load()->barrier_data() == 0);
4650 match(Set dst (LoadN mem));
4651
4652 ins_cost(LOAD_COST);
4653 format %{ "lwu $dst, $mem\t# compressed ptr, #@loadN" %}
4654
4655 ins_encode %{
4656 __ lwu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4657 %}
4658
4659 ins_pipe(iload_reg_mem);
4660 %}
4661
4662 // Load Klass Pointer
4663 instruct loadKlass(iRegPNoSp dst, memory mem)
4664 %{
4665 match(Set dst (LoadKlass mem));
4666
4667 ins_cost(LOAD_COST);
4668 format %{ "ld $dst, $mem\t# class, #@loadKlass" %}
4669
4670 ins_encode %{
4671 __ ld(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4672 %}
4673
4674 ins_pipe(iload_reg_mem);
4675 %}
4676
4677 // Load Narrow Klass Pointer
4678 instruct loadNKlass(iRegNNoSp dst, memory mem)
4679 %{
4680 predicate(!UseCompactObjectHeaders);
4681 match(Set dst (LoadNKlass mem));
4682
4683 ins_cost(LOAD_COST);
4684 format %{ "lwu $dst, $mem\t# compressed class ptr, #@loadNKlass" %}
4685
4686 ins_encode %{
4687 __ lwu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4688 %}
4689
4690 ins_pipe(iload_reg_mem);
4691 %}
4692
4693 instruct loadNKlassCompactHeaders(iRegNNoSp dst, memory mem)
4694 %{
4695 predicate(UseCompactObjectHeaders);
4696 match(Set dst (LoadNKlass mem));
4697
4698 ins_cost(LOAD_COST);
4699 format %{
4700 "lwu $dst, $mem\t# compressed klass ptr, shifted\n\t"
4701 "srli $dst, $dst, markWord::klass_shift_at_offset"
4702 %}
4703
4704 ins_encode %{
4705 Unimplemented();
4706 // __ lwu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4707 // __ srli(as_Register($dst$$reg), as_Register($dst$$reg), (unsigned) markWord::klass_shift_at_offset);
4708 %}
4709
4710 ins_pipe(iload_reg_mem);
4711 %}
4712
4713 // Load Float
4714 instruct loadF(fRegF dst, memory mem)
4715 %{
4716 match(Set dst (LoadF mem));
4717
4718 ins_cost(LOAD_COST);
4719 format %{ "flw $dst, $mem\t# float, #@loadF" %}
4720
4721 ins_encode %{
4722 __ flw(as_FloatRegister($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4723 %}
4724
4725 ins_pipe(fp_load_mem_s);
4726 %}
4727
4728 // Load Double
4729 instruct loadD(fRegD dst, memory mem)
4730 %{
4731 match(Set dst (LoadD mem));
4732
4733 ins_cost(LOAD_COST);
4734 format %{ "fld $dst, $mem\t# double, #@loadD" %}
4735
4736 ins_encode %{
4737 __ fld(as_FloatRegister($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4738 %}
4739
4740 ins_pipe(fp_load_mem_d);
4741 %}
4742
4743 // Load Int Constant
4744 instruct loadConI(iRegINoSp dst, immI src)
4745 %{
4746 match(Set dst src);
4747
4748 ins_cost(ALU_COST);
4749 format %{ "mv $dst, $src\t# int, #@loadConI" %}
4750
4751 ins_encode(riscv_enc_mov_imm(dst, src));
4752
4753 ins_pipe(ialu_imm);
4754 %}
4755
4756 // Load Long Constant
4757 instruct loadConL(iRegLNoSp dst, immL src)
4758 %{
4759 match(Set dst src);
4760
4761 ins_cost(ALU_COST);
4762 format %{ "mv $dst, $src\t# long, #@loadConL" %}
4763
4764 ins_encode(riscv_enc_mov_imm(dst, src));
4765
4766 ins_pipe(ialu_imm);
4767 %}
4768
4769 // Load Pointer Constant
4770 instruct loadConP(iRegPNoSp dst, immP con)
4771 %{
4772 match(Set dst con);
4773
4774 ins_cost(ALU_COST);
4775 format %{ "mv $dst, $con\t# ptr, #@loadConP" %}
4776
4777 ins_encode(riscv_enc_mov_p(dst, con));
4778
4779 ins_pipe(ialu_imm);
4780 %}
4781
4782 // Load Null Pointer Constant
4783 instruct loadConP0(iRegPNoSp dst, immP0 con)
4784 %{
4785 match(Set dst con);
4786
4787 ins_cost(ALU_COST);
4788 format %{ "mv $dst, $con\t# null pointer, #@loadConP0" %}
4789
4790 ins_encode(riscv_enc_mov_zero(dst));
4791
4792 ins_pipe(ialu_imm);
4793 %}
4794
4795 // Load Pointer Constant One
4796 instruct loadConP1(iRegPNoSp dst, immP_1 con)
4797 %{
4798 match(Set dst con);
4799
4800 ins_cost(ALU_COST);
4801 format %{ "mv $dst, $con\t# load ptr constant one, #@loadConP1" %}
4802
4803 ins_encode(riscv_enc_mov_p1(dst));
4804
4805 ins_pipe(ialu_imm);
4806 %}
4807
4808 // Load Narrow Pointer Constant
4809 instruct loadConN(iRegNNoSp dst, immN con)
4810 %{
4811 match(Set dst con);
4812
4813 ins_cost(ALU_COST * 4);
4814 format %{ "mv $dst, $con\t# compressed ptr, #@loadConN" %}
4815
4816 ins_encode(riscv_enc_mov_n(dst, con));
4817
4818 ins_pipe(ialu_imm);
4819 %}
4820
4821 // Load Narrow Null Pointer Constant
4822 instruct loadConN0(iRegNNoSp dst, immN0 con)
4823 %{
4824 match(Set dst con);
4825
4826 ins_cost(ALU_COST);
4827 format %{ "mv $dst, $con\t# compressed null pointer, #@loadConN0" %}
4828
4829 ins_encode(riscv_enc_mov_zero(dst));
4830
4831 ins_pipe(ialu_imm);
4832 %}
4833
4834 // Load Narrow Klass Constant
4835 instruct loadConNKlass(iRegNNoSp dst, immNKlass con)
4836 %{
4837 match(Set dst con);
4838
4839 ins_cost(ALU_COST * 6);
4840 format %{ "mv $dst, $con\t# compressed klass ptr, #@loadConNKlass" %}
4841
4842 ins_encode(riscv_enc_mov_nk(dst, con));
4843
4844 ins_pipe(ialu_imm);
4845 %}
4846
4847 // Load Half Float Constant
4848 instruct loadConH(fRegF dst, immH con) %{
4849 match(Set dst con);
4850
4851 ins_cost(LOAD_COST);
4852 format %{
4853 "flh $dst, [$constantaddress]\t# load from constant table: float=$con, #@loadConH"
4854 %}
4855
4856 ins_encode %{
4857 assert(UseZfh || UseZfhmin, "must");
4858 if (MacroAssembler::can_hf_imm_load($con$$constant)) {
4859 __ fli_h(as_FloatRegister($dst$$reg), $con$$constant);
4860 } else {
4861 __ flh(as_FloatRegister($dst$$reg), $constantaddress($con));
4862 }
4863 %}
4864
4865 ins_pipe(fp_load_constant_s);
4866 %}
4867
4868 instruct loadConH0(fRegF dst, immH0 con) %{
4869 match(Set dst con);
4870
4871 ins_cost(XFER_COST);
4872
4873 format %{ "fmv.h.x $dst, zr\t# float, #@loadConH0" %}
4874
4875 ins_encode %{
4876 assert(UseZfh || UseZfhmin, "must");
4877 __ fmv_h_x(as_FloatRegister($dst$$reg), zr);
4878 %}
4879
4880 ins_pipe(fp_load_constant_s);
4881 %}
4882
4883 // Load Float Constant
4884 instruct loadConF(fRegF dst, immF con) %{
4885 match(Set dst con);
4886
4887 ins_cost(LOAD_COST);
4888 format %{
4889 "flw $dst, [$constantaddress]\t# load from constant table: float=$con, #@loadConF"
4890 %}
4891
4892 ins_encode %{
4893 if (MacroAssembler::can_fp_imm_load($con$$constant)) {
4894 __ fli_s(as_FloatRegister($dst$$reg), $con$$constant);
4895 } else {
4896 __ flw(as_FloatRegister($dst$$reg), $constantaddress($con));
4897 }
4898 %}
4899
4900 ins_pipe(fp_load_constant_s);
4901 %}
4902
4903 instruct loadConF0(fRegF dst, immF0 con) %{
4904 match(Set dst con);
4905
4906 ins_cost(XFER_COST);
4907
4908 format %{ "fmv.w.x $dst, zr\t# float, #@loadConF0" %}
4909
4910 ins_encode %{
4911 __ fmv_w_x(as_FloatRegister($dst$$reg), zr);
4912 %}
4913
4914 ins_pipe(fp_load_constant_s);
4915 %}
4916
4917 // Load Double Constant
4918 instruct loadConD(fRegD dst, immD con) %{
4919 match(Set dst con);
4920
4921 ins_cost(LOAD_COST);
4922 format %{
4923 "fld $dst, [$constantaddress]\t# load from constant table: double=$con, #@loadConD"
4924 %}
4925
4926 ins_encode %{
4927 if (MacroAssembler::can_dp_imm_load($con$$constant)) {
4928 __ fli_d(as_FloatRegister($dst$$reg), $con$$constant);
4929 } else {
4930 __ fld(as_FloatRegister($dst$$reg), $constantaddress($con));
4931 }
4932 %}
4933
4934 ins_pipe(fp_load_constant_d);
4935 %}
4936
4937 instruct loadConD0(fRegD dst, immD0 con) %{
4938 match(Set dst con);
4939
4940 ins_cost(XFER_COST);
4941
4942 format %{ "fmv.d.x $dst, zr\t# double, #@loadConD0" %}
4943
4944 ins_encode %{
4945 __ fmv_d_x(as_FloatRegister($dst$$reg), zr);
4946 %}
4947
4948 ins_pipe(fp_load_constant_d);
4949 %}
4950
4951 // Store Byte
4952 instruct storeB(iRegIorL2I src, memory mem)
4953 %{
4954 match(Set mem (StoreB mem src));
4955
4956 ins_cost(STORE_COST);
4957 format %{ "sb $src, $mem\t# byte, #@storeB" %}
4958
4959 ins_encode %{
4960 __ sb(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
4961 %}
4962
4963 ins_pipe(istore_reg_mem);
4964 %}
4965
4966 instruct storeimmB0(immI0 zero, memory mem)
4967 %{
4968 match(Set mem (StoreB mem zero));
4969
4970 ins_cost(STORE_COST);
4971 format %{ "sb zr, $mem\t# byte, #@storeimmB0" %}
4972
4973 ins_encode %{
4974 __ sb(zr, Address(as_Register($mem$$base), $mem$$disp));
4975 %}
4976
4977 ins_pipe(istore_mem);
4978 %}
4979
4980 // Store Char/Short
4981 instruct storeC(iRegIorL2I src, memory mem)
4982 %{
4983 match(Set mem (StoreC mem src));
4984
4985 ins_cost(STORE_COST);
4986 format %{ "sh $src, $mem\t# short, #@storeC" %}
4987
4988 ins_encode %{
4989 __ sh(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
4990 %}
4991
4992 ins_pipe(istore_reg_mem);
4993 %}
4994
4995 instruct storeimmC0(immI0 zero, memory mem)
4996 %{
4997 match(Set mem (StoreC mem zero));
4998
4999 ins_cost(STORE_COST);
5000 format %{ "sh zr, $mem\t# short, #@storeimmC0" %}
5001
5002 ins_encode %{
5003 __ sh(zr, Address(as_Register($mem$$base), $mem$$disp));
5004 %}
5005
5006 ins_pipe(istore_mem);
5007 %}
5008
5009 // Store Integer
5010 instruct storeI(iRegIorL2I src, memory mem)
5011 %{
5012 match(Set mem(StoreI mem src));
5013
5014 ins_cost(STORE_COST);
5015 format %{ "sw $src, $mem\t# int, #@storeI" %}
5016
5017 ins_encode %{
5018 __ sw(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5019 %}
5020
5021 ins_pipe(istore_reg_mem);
5022 %}
5023
5024 instruct storeimmI0(immI0 zero, memory mem)
5025 %{
5026 match(Set mem(StoreI mem zero));
5027
5028 ins_cost(STORE_COST);
5029 format %{ "sw zr, $mem\t# int, #@storeimmI0" %}
5030
5031 ins_encode %{
5032 __ sw(zr, Address(as_Register($mem$$base), $mem$$disp));
5033 %}
5034
5035 ins_pipe(istore_mem);
5036 %}
5037
5038 // Store Long (64 bit signed)
5039 instruct storeL(iRegL src, memory mem)
5040 %{
5041 match(Set mem (StoreL mem src));
5042
5043 ins_cost(STORE_COST);
5044 format %{ "sd $src, $mem\t# long, #@storeL" %}
5045
5046 ins_encode %{
5047 __ sd(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5048 %}
5049
5050 ins_pipe(istore_reg_mem);
5051 %}
5052
5053 // Store Long (64 bit signed)
5054 instruct storeimmL0(immL0 zero, memory mem)
5055 %{
5056 match(Set mem (StoreL mem zero));
5057
5058 ins_cost(STORE_COST);
5059 format %{ "sd zr, $mem\t# long, #@storeimmL0" %}
5060
5061 ins_encode %{
5062 __ sd(zr, Address(as_Register($mem$$base), $mem$$disp));
5063 %}
5064
5065 ins_pipe(istore_mem);
5066 %}
5067
5068 // Store Pointer
5069 instruct storeP(iRegP src, memory mem)
5070 %{
5071 match(Set mem (StoreP mem src));
5072 predicate(n->as_Store()->barrier_data() == 0);
5073
5074 ins_cost(STORE_COST);
5075 format %{ "sd $src, $mem\t# ptr, #@storeP" %}
5076
5077 ins_encode %{
5078 __ sd(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5079 %}
5080
5081 ins_pipe(istore_reg_mem);
5082 %}
5083
5084 // Store Pointer
5085 instruct storeimmP0(immP0 zero, memory mem)
5086 %{
5087 match(Set mem (StoreP mem zero));
5088 predicate(n->as_Store()->barrier_data() == 0);
5089
5090 ins_cost(STORE_COST);
5091 format %{ "sd zr, $mem\t# ptr, #@storeimmP0" %}
5092
5093 ins_encode %{
5094 __ sd(zr, Address(as_Register($mem$$base), $mem$$disp));
5095 %}
5096
5097 ins_pipe(istore_mem);
5098 %}
5099
5100 // Store Compressed Pointer
5101 instruct storeN(iRegN src, memory mem)
5102 %{
5103 predicate(n->as_Store()->barrier_data() == 0);
5104 match(Set mem (StoreN mem src));
5105
5106 ins_cost(STORE_COST);
5107 format %{ "sw $src, $mem\t# compressed ptr, #@storeN" %}
5108
5109 ins_encode %{
5110 __ sw(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5111 %}
5112
5113 ins_pipe(istore_reg_mem);
5114 %}
5115
5116 instruct storeImmN0(immN0 zero, memory mem)
5117 %{
5118 predicate(n->as_Store()->barrier_data() == 0);
5119 match(Set mem (StoreN mem zero));
5120
5121 ins_cost(STORE_COST);
5122 format %{ "sw zr, $mem\t# compressed ptr, #@storeImmN0" %}
5123
5124 ins_encode %{
5125 __ sw(zr, Address(as_Register($mem$$base), $mem$$disp));
5126 %}
5127
5128 ins_pipe(istore_reg_mem);
5129 %}
5130
5131 // Store Float
5132 instruct storeF(fRegF src, memory mem)
5133 %{
5134 match(Set mem (StoreF mem src));
5135
5136 ins_cost(STORE_COST);
5137 format %{ "fsw $src, $mem\t# float, #@storeF" %}
5138
5139 ins_encode %{
5140 __ fsw(as_FloatRegister($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5141 %}
5142
5143 ins_pipe(fp_store_reg_s);
5144 %}
5145
5146 // Store Double
5147 instruct storeD(fRegD src, memory mem)
5148 %{
5149 match(Set mem (StoreD mem src));
5150
5151 ins_cost(STORE_COST);
5152 format %{ "fsd $src, $mem\t# double, #@storeD" %}
5153
5154 ins_encode %{
5155 __ fsd(as_FloatRegister($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5156 %}
5157
5158 ins_pipe(fp_store_reg_d);
5159 %}
5160
5161 // Store Compressed Klass Pointer
5162 instruct storeNKlass(iRegN src, memory mem)
5163 %{
5164 match(Set mem (StoreNKlass mem src));
5165
5166 ins_cost(STORE_COST);
5167 format %{ "sw $src, $mem\t# compressed klass ptr, #@storeNKlass" %}
5168
5169 ins_encode %{
5170 __ sw(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5171 %}
5172
5173 ins_pipe(istore_reg_mem);
5174 %}
5175
5176 // ============================================================================
5177 // Prefetch instructions
5178 // Must be safe to execute with invalid address (cannot fault).
5179
5180 instruct prefetchalloc( memory mem ) %{
5181 predicate(UseZicbop);
5182 match(PrefetchAllocation mem);
5183
5184 ins_cost(ALU_COST * 1);
5185 format %{ "prefetch_w $mem\t# Prefetch for write" %}
5186
5187 ins_encode %{
5188 if (Assembler::is_simm12($mem$$disp)) {
5189 if (($mem$$disp & 0x1f) == 0) {
5190 __ prefetch_w(as_Register($mem$$base), $mem$$disp);
5191 } else {
5192 __ addi(t0, as_Register($mem$$base), $mem$$disp);
5193 __ prefetch_w(t0, 0);
5194 }
5195 } else {
5196 __ mv(t0, $mem$$disp);
5197 __ add(t0, as_Register($mem$$base), t0);
5198 __ prefetch_w(t0, 0);
5199 }
5200 %}
5201
5202 ins_pipe(iload_prefetch);
5203 %}
5204
5205 // ============================================================================
5206 // Atomic operation instructions
5207 //
5208
5209 // standard CompareAndSwapX when we are using barriers
5210 // these have higher priority than the rules selected by a predicate
5211 instruct compareAndSwapB_narrow(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5212 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5213 %{
5214 predicate(!UseZabha || !UseZacas);
5215
5216 match(Set res (CompareAndSwapB mem (Binary oldval newval)));
5217
5218 ins_cost(2 * VOLATILE_REF_COST);
5219
5220 effect(TEMP_DEF res, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3, KILL cr);
5221
5222 format %{
5223 "cmpxchg $mem, $oldval, $newval\t# (byte) if $mem == $oldval then $mem <-- $newval\n\t"
5224 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapB_narrow"
5225 %}
5226
5227 ins_encode %{
5228 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5229 Assembler::relaxed /* acquire */, Assembler::rl /* release */, $res$$Register,
5230 true /* result as bool */, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5231 %}
5232
5233 ins_pipe(pipe_slow);
5234 %}
5235
5236 instruct compareAndSwapB(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5237 %{
5238 predicate(UseZabha && UseZacas);
5239
5240 match(Set res (CompareAndSwapB mem (Binary oldval newval)));
5241
5242 ins_cost(2 * VOLATILE_REF_COST);
5243
5244 format %{
5245 "cmpxchg $mem, $oldval, $newval\t# (byte) if $mem == $oldval then $mem <-- $newval\n\t"
5246 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapB"
5247 %}
5248
5249 ins_encode %{
5250 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5251 Assembler::relaxed /* acquire */, Assembler::rl /* release */, $res$$Register,
5252 true /* result as bool */);
5253 %}
5254
5255 ins_pipe(pipe_slow);
5256 %}
5257
5258 instruct compareAndSwapS_narrow(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5259 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5260 %{
5261 predicate(!UseZabha || !UseZacas);
5262
5263 match(Set res (CompareAndSwapS mem (Binary oldval newval)));
5264
5265 ins_cost(2 * VOLATILE_REF_COST);
5266
5267 effect(TEMP_DEF res, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3, KILL cr);
5268
5269 format %{
5270 "cmpxchg $mem, $oldval, $newval\t# (short) if $mem == $oldval then $mem <-- $newval\n\t"
5271 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapS_narrow"
5272 %}
5273
5274 ins_encode %{
5275 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5276 Assembler::relaxed /* acquire */, Assembler::rl /* release */, $res$$Register,
5277 true /* result as bool */, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5278 %}
5279
5280 ins_pipe(pipe_slow);
5281 %}
5282
5283 instruct compareAndSwapS(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5284 %{
5285 predicate(UseZabha && UseZacas);
5286
5287 match(Set res (CompareAndSwapS mem (Binary oldval newval)));
5288
5289 ins_cost(2 * VOLATILE_REF_COST);
5290
5291 format %{
5292 "cmpxchg $mem, $oldval, $newval\t# (short) if $mem == $oldval then $mem <-- $newval\n\t"
5293 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapS"
5294 %}
5295
5296 ins_encode %{
5297 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5298 Assembler::relaxed /* acquire */, Assembler::rl /* release */, $res$$Register,
5299 true /* result as bool */);
5300 %}
5301
5302 ins_pipe(pipe_slow);
5303 %}
5304
5305 instruct compareAndSwapI(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5306 %{
5307 match(Set res (CompareAndSwapI mem (Binary oldval newval)));
5308
5309 ins_cost(2 * VOLATILE_REF_COST);
5310
5311 format %{
5312 "cmpxchg $mem, $oldval, $newval\t# (int) if $mem == $oldval then $mem <-- $newval\n\t"
5313 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapI"
5314 %}
5315
5316 ins_encode %{
5317 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
5318 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
5319 /*result as bool*/ true);
5320 %}
5321
5322 ins_pipe(pipe_slow);
5323 %}
5324
5325 instruct compareAndSwapL(iRegINoSp res, indirect mem, iRegL oldval, iRegL newval)
5326 %{
5327 match(Set res (CompareAndSwapL mem (Binary oldval newval)));
5328
5329 ins_cost(2 * VOLATILE_REF_COST);
5330
5331 format %{
5332 "cmpxchg $mem, $oldval, $newval\t# (long) if $mem == $oldval then $mem <-- $newval\n\t"
5333 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapL"
5334 %}
5335
5336 ins_encode %{
5337 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5338 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
5339 /*result as bool*/ true);
5340 %}
5341
5342 ins_pipe(pipe_slow);
5343 %}
5344
5345 instruct compareAndSwapP(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval)
5346 %{
5347 predicate(n->as_LoadStore()->barrier_data() == 0);
5348
5349 match(Set res (CompareAndSwapP mem (Binary oldval newval)));
5350
5351 ins_cost(2 * VOLATILE_REF_COST);
5352
5353 format %{
5354 "cmpxchg $mem, $oldval, $newval\t# (ptr) if $mem == $oldval then $mem <-- $newval\n\t"
5355 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapP"
5356 %}
5357
5358 ins_encode %{
5359 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5360 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
5361 /*result as bool*/ true);
5362 %}
5363
5364 ins_pipe(pipe_slow);
5365 %}
5366
5367 instruct compareAndSwapN(iRegINoSp res, indirect mem, iRegN oldval, iRegN newval)
5368 %{
5369 predicate(n->as_LoadStore()->barrier_data() == 0);
5370
5371 match(Set res (CompareAndSwapN mem (Binary oldval newval)));
5372
5373 ins_cost(2 * VOLATILE_REF_COST);
5374
5375 format %{
5376 "cmpxchg $mem, $oldval, $newval\t# (narrow oop) if $mem == $oldval then $mem <-- $newval\n\t"
5377 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapN"
5378 %}
5379
5380 ins_encode %{
5381 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
5382 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
5383 /*result as bool*/ true);
5384 %}
5385
5386 ins_pipe(pipe_slow);
5387 %}
5388
5389 // alternative CompareAndSwapX when we are eliding barriers
5390 instruct compareAndSwapBAcq_narrow(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5391 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5392 %{
5393 predicate((!UseZabha || !UseZacas) && needs_acquiring_load_reserved(n));
5394
5395 match(Set res (CompareAndSwapB mem (Binary oldval newval)));
5396
5397 ins_cost(2 * VOLATILE_REF_COST);
5398
5399 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5400
5401 format %{
5402 "cmpxchg_acq $mem, $oldval, $newval\t# (byte) if $mem == $oldval then $mem <-- $newval\n\t"
5403 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapBAcq_narrow"
5404 %}
5405
5406 ins_encode %{
5407 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5408 Assembler::aq /* acquire */, Assembler::rl /* release */, $res$$Register,
5409 true /* result as bool */, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5410 %}
5411
5412 ins_pipe(pipe_slow);
5413 %}
5414
5415 instruct compareAndSwapBAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5416 %{
5417 predicate((UseZabha && UseZacas) && needs_acquiring_load_reserved(n));
5418
5419 match(Set res (CompareAndSwapB mem (Binary oldval newval)));
5420
5421 ins_cost(2 * VOLATILE_REF_COST);
5422
5423 format %{
5424 "cmpxchg $mem, $oldval, $newval\t# (byte) if $mem == $oldval then $mem <-- $newval\n\t"
5425 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapBAcq"
5426 %}
5427
5428 ins_encode %{
5429 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5430 Assembler::aq /* acquire */, Assembler::rl /* release */, $res$$Register,
5431 true /* result as bool */);
5432 %}
5433
5434 ins_pipe(pipe_slow);
5435 %}
5436
5437 instruct compareAndSwapSAcq_narrow(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5438 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5439 %{
5440 predicate((!UseZabha || !UseZacas) && needs_acquiring_load_reserved(n));
5441
5442 match(Set res (CompareAndSwapS mem (Binary oldval newval)));
5443
5444 ins_cost(2 * VOLATILE_REF_COST);
5445
5446 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5447
5448 format %{
5449 "cmpxchg_acq $mem, $oldval, $newval\t# (short) if $mem == $oldval then $mem <-- $newval\n\t"
5450 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapSAcq_narrow"
5451 %}
5452
5453 ins_encode %{
5454 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5455 Assembler::aq /* acquire */, Assembler::rl /* release */, $res$$Register,
5456 true /* result as bool */, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5457 %}
5458
5459 ins_pipe(pipe_slow);
5460 %}
5461
5462 instruct compareAndSwapSAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5463 %{
5464 predicate((UseZabha && UseZacas) && needs_acquiring_load_reserved(n));
5465
5466 match(Set res (CompareAndSwapS mem (Binary oldval newval)));
5467
5468 ins_cost(2 * VOLATILE_REF_COST);
5469
5470 format %{
5471 "cmpxchg $mem, $oldval, $newval\t# (short) if $mem == $oldval then $mem <-- $newval\n\t"
5472 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapSAcq"
5473 %}
5474
5475 ins_encode %{
5476 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5477 Assembler::aq /* acquire */, Assembler::rl /* release */, $res$$Register,
5478 true /* result as bool */);
5479 %}
5480
5481 ins_pipe(pipe_slow);
5482 %}
5483
5484 instruct compareAndSwapIAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5485 %{
5486 predicate(needs_acquiring_load_reserved(n));
5487
5488 match(Set res (CompareAndSwapI mem (Binary oldval newval)));
5489
5490 ins_cost(2 * VOLATILE_REF_COST);
5491
5492 format %{
5493 "cmpxchg_acq $mem, $oldval, $newval\t# (int) if $mem == $oldval then $mem <-- $newval\n\t"
5494 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapIAcq"
5495 %}
5496
5497 ins_encode %{
5498 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
5499 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
5500 /*result as bool*/ true);
5501 %}
5502
5503 ins_pipe(pipe_slow);
5504 %}
5505
5506 instruct compareAndSwapLAcq(iRegINoSp res, indirect mem, iRegL oldval, iRegL newval)
5507 %{
5508 predicate(needs_acquiring_load_reserved(n));
5509
5510 match(Set res (CompareAndSwapL mem (Binary oldval newval)));
5511
5512 ins_cost(2 * VOLATILE_REF_COST);
5513
5514 format %{
5515 "cmpxchg_acq $mem, $oldval, $newval\t# (long) if $mem == $oldval then $mem <-- $newval\n\t"
5516 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapLAcq"
5517 %}
5518
5519 ins_encode %{
5520 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5521 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
5522 /*result as bool*/ true);
5523 %}
5524
5525 ins_pipe(pipe_slow);
5526 %}
5527
5528 instruct compareAndSwapPAcq(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval)
5529 %{
5530 predicate(needs_acquiring_load_reserved(n) && (n->as_LoadStore()->barrier_data() == 0));
5531
5532 match(Set res (CompareAndSwapP mem (Binary oldval newval)));
5533
5534 ins_cost(2 * VOLATILE_REF_COST);
5535
5536 format %{
5537 "cmpxchg_acq $mem, $oldval, $newval\t# (ptr) if $mem == $oldval then $mem <-- $newval\n\t"
5538 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapPAcq"
5539 %}
5540
5541 ins_encode %{
5542 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5543 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
5544 /*result as bool*/ true);
5545 %}
5546
5547 ins_pipe(pipe_slow);
5548 %}
5549
5550 instruct compareAndSwapNAcq(iRegINoSp res, indirect mem, iRegN oldval, iRegN newval)
5551 %{
5552 predicate(needs_acquiring_load_reserved(n) && n->as_LoadStore()->barrier_data() == 0);
5553
5554 match(Set res (CompareAndSwapN mem (Binary oldval newval)));
5555
5556 ins_cost(2 * VOLATILE_REF_COST);
5557
5558 format %{
5559 "cmpxchg_acq $mem, $oldval, $newval\t# (narrow oop) if $mem == $oldval then $mem <-- $newval\n\t"
5560 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapNAcq"
5561 %}
5562
5563 ins_encode %{
5564 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
5565 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
5566 /*result as bool*/ true);
5567 %}
5568
5569 ins_pipe(pipe_slow);
5570 %}
5571
5572 // Sundry CAS operations. Note that release is always true,
5573 // regardless of the memory ordering of the CAS. This is because we
5574 // need the volatile case to be sequentially consistent but there is
5575 // no trailing StoreLoad barrier emitted by C2. Unfortunately we
5576 // can't check the type of memory ordering here, so we always emit a
5577 // sc_d(w) with rl bit set.
5578 instruct compareAndExchangeB_narrow(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5579 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5580 %{
5581 predicate(!UseZabha || !UseZacas);
5582
5583 match(Set res (CompareAndExchangeB mem (Binary oldval newval)));
5584
5585 ins_cost(2 * VOLATILE_REF_COST);
5586
5587 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5588
5589 format %{
5590 "cmpxchg $res = $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeB_narrow"
5591 %}
5592
5593 ins_encode %{
5594 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5595 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
5596 /*result_as_bool*/ false, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5597 %}
5598
5599 ins_pipe(pipe_slow);
5600 %}
5601
5602 instruct compareAndExchangeB(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5603 %{
5604 predicate(UseZabha && UseZacas);
5605
5606 match(Set res (CompareAndExchangeB mem (Binary oldval newval)));
5607
5608 ins_cost(2 * VOLATILE_REF_COST);
5609
5610 format %{
5611 "cmpxchg $res = $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeB"
5612 %}
5613
5614 ins_encode %{
5615 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5616 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5617 %}
5618
5619 ins_pipe(pipe_slow);
5620 %}
5621
5622 instruct compareAndExchangeS_narrow(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5623 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5624 %{
5625 predicate(!UseZabha || !UseZacas);
5626
5627 match(Set res (CompareAndExchangeS mem (Binary oldval newval)));
5628
5629 ins_cost(2 * VOLATILE_REF_COST);
5630
5631 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5632
5633 format %{
5634 "cmpxchg $res = $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeS_narrow"
5635 %}
5636
5637 ins_encode %{
5638 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5639 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
5640 /*result_as_bool*/ false, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5641 %}
5642
5643 ins_pipe(pipe_slow);
5644 %}
5645
5646 instruct compareAndExchangeS(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5647 %{
5648 predicate(UseZabha && UseZacas);
5649
5650 match(Set res (CompareAndExchangeS mem (Binary oldval newval)));
5651
5652 ins_cost(2 * VOLATILE_REF_COST);
5653
5654 format %{
5655 "cmpxchg $res = $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeS"
5656 %}
5657
5658 ins_encode %{
5659 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5660 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5661 %}
5662
5663 ins_pipe(pipe_slow);
5664 %}
5665
5666 instruct compareAndExchangeI(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5667 %{
5668 match(Set res (CompareAndExchangeI mem (Binary oldval newval)));
5669
5670 ins_cost(2 * VOLATILE_REF_COST);
5671
5672 format %{
5673 "cmpxchg $res = $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeI"
5674 %}
5675
5676 ins_encode %{
5677 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
5678 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5679 %}
5680
5681 ins_pipe(pipe_slow);
5682 %}
5683
5684 instruct compareAndExchangeL(iRegLNoSp res, indirect mem, iRegL oldval, iRegL newval)
5685 %{
5686 match(Set res (CompareAndExchangeL mem (Binary oldval newval)));
5687
5688 ins_cost(2 * VOLATILE_REF_COST);
5689
5690 format %{
5691 "cmpxchg $res = $mem, $oldval, $newval\t# (long, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeL"
5692 %}
5693
5694 ins_encode %{
5695 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5696 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5697 %}
5698
5699 ins_pipe(pipe_slow);
5700 %}
5701
5702 instruct compareAndExchangeN(iRegNNoSp res, indirect mem, iRegN oldval, iRegN newval)
5703 %{
5704 predicate(n->as_LoadStore()->barrier_data() == 0);
5705
5706 match(Set res (CompareAndExchangeN mem (Binary oldval newval)));
5707
5708 ins_cost(2 * VOLATILE_REF_COST);
5709
5710 format %{
5711 "cmpxchg $res = $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeN"
5712 %}
5713
5714 ins_encode %{
5715 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
5716 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5717 %}
5718
5719 ins_pipe(pipe_slow);
5720 %}
5721
5722 instruct compareAndExchangeP(iRegPNoSp res, indirect mem, iRegP oldval, iRegP newval)
5723 %{
5724 predicate(n->as_LoadStore()->barrier_data() == 0);
5725
5726 match(Set res (CompareAndExchangeP mem (Binary oldval newval)));
5727
5728 ins_cost(2 * VOLATILE_REF_COST);
5729
5730 format %{
5731 "cmpxchg $res = $mem, $oldval, $newval\t# (ptr, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeP"
5732 %}
5733
5734 ins_encode %{
5735 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5736 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5737 %}
5738
5739 ins_pipe(pipe_slow);
5740 %}
5741
5742 instruct compareAndExchangeBAcq_narrow(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5743 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5744 %{
5745 predicate((!UseZabha || !UseZacas) && needs_acquiring_load_reserved(n));
5746
5747 match(Set res (CompareAndExchangeB mem (Binary oldval newval)));
5748
5749 ins_cost(2 * VOLATILE_REF_COST);
5750
5751 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5752
5753 format %{
5754 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeBAcq_narrow"
5755 %}
5756
5757 ins_encode %{
5758 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5759 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
5760 /*result_as_bool*/ false, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5761 %}
5762
5763 ins_pipe(pipe_slow);
5764 %}
5765
5766 instruct compareAndExchangeBAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5767 %{
5768 predicate((UseZabha && UseZacas) && needs_acquiring_load_reserved(n));
5769
5770 match(Set res (CompareAndExchangeB mem (Binary oldval newval)));
5771
5772 ins_cost(2 * VOLATILE_REF_COST);
5773
5774 format %{
5775 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeBAcq"
5776 %}
5777
5778 ins_encode %{
5779 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5780 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
5781 %}
5782
5783 ins_pipe(pipe_slow);
5784 %}
5785
5786 instruct compareAndExchangeSAcq_narrow(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5787 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5788 %{
5789 predicate((!UseZabha || !UseZacas) && needs_acquiring_load_reserved(n));
5790
5791 match(Set res (CompareAndExchangeS mem (Binary oldval newval)));
5792
5793 ins_cost(2 * VOLATILE_REF_COST);
5794
5795 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5796
5797 format %{
5798 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeSAcq_narrow"
5799 %}
5800
5801 ins_encode %{
5802 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5803 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
5804 /*result_as_bool*/ false, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5805 %}
5806
5807 ins_pipe(pipe_slow);
5808 %}
5809
5810 instruct compareAndExchangeSAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5811 %{
5812 predicate((UseZabha && UseZacas) && needs_acquiring_load_reserved(n));
5813
5814 match(Set res (CompareAndExchangeS mem (Binary oldval newval)));
5815
5816 ins_cost(2 * VOLATILE_REF_COST);
5817
5818 format %{
5819 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeSAcq"
5820 %}
5821
5822 ins_encode %{
5823 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5824 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
5825 %}
5826
5827 ins_pipe(pipe_slow);
5828 %}
5829
5830 instruct compareAndExchangeIAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5831 %{
5832 predicate(needs_acquiring_load_reserved(n));
5833
5834 match(Set res (CompareAndExchangeI mem (Binary oldval newval)));
5835
5836 ins_cost(2 * VOLATILE_REF_COST);
5837
5838 format %{
5839 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeIAcq"
5840 %}
5841
5842 ins_encode %{
5843 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
5844 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
5845 %}
5846
5847 ins_pipe(pipe_slow);
5848 %}
5849
5850 instruct compareAndExchangeLAcq(iRegLNoSp res, indirect mem, iRegL oldval, iRegL newval)
5851 %{
5852 predicate(needs_acquiring_load_reserved(n));
5853
5854 match(Set res (CompareAndExchangeL mem (Binary oldval newval)));
5855
5856 ins_cost(2 * VOLATILE_REF_COST);
5857
5858 format %{
5859 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (long, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeLAcq"
5860 %}
5861
5862 ins_encode %{
5863 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5864 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
5865 %}
5866
5867 ins_pipe(pipe_slow);
5868 %}
5869
5870 instruct compareAndExchangeNAcq(iRegNNoSp res, indirect mem, iRegN oldval, iRegN newval)
5871 %{
5872 predicate(needs_acquiring_load_reserved(n) && n->as_LoadStore()->barrier_data() == 0);
5873
5874 match(Set res (CompareAndExchangeN mem (Binary oldval newval)));
5875
5876 ins_cost(2 * VOLATILE_REF_COST);
5877
5878 format %{
5879 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeNAcq"
5880 %}
5881
5882 ins_encode %{
5883 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
5884 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
5885 %}
5886
5887 ins_pipe(pipe_slow);
5888 %}
5889
5890 instruct compareAndExchangePAcq(iRegPNoSp res, indirect mem, iRegP oldval, iRegP newval)
5891 %{
5892 predicate(needs_acquiring_load_reserved(n) && (n->as_LoadStore()->barrier_data() == 0));
5893
5894 match(Set res (CompareAndExchangeP mem (Binary oldval newval)));
5895
5896 ins_cost(2 * VOLATILE_REF_COST);
5897
5898 format %{
5899 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (ptr, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangePAcq"
5900 %}
5901
5902 ins_encode %{
5903 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5904 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
5905 %}
5906
5907 ins_pipe(pipe_slow);
5908 %}
5909
5910 instruct weakCompareAndSwapB_narrow(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5911 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5912 %{
5913 predicate(!UseZabha || !UseZacas);
5914
5915 match(Set res (WeakCompareAndSwapB mem (Binary oldval newval)));
5916
5917 ins_cost(2 * VOLATILE_REF_COST);
5918
5919 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5920
5921 format %{
5922 "weak_cmpxchg $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5923 "# $res == 1 when success, #@weakCompareAndSwapB_narrow"
5924 %}
5925
5926 ins_encode %{
5927 __ weak_cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5928 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
5929 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5930 %}
5931
5932 ins_pipe(pipe_slow);
5933 %}
5934
5935 instruct weakCompareAndSwapB(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5936 %{
5937 predicate(UseZabha && UseZacas);
5938
5939 match(Set res (WeakCompareAndSwapB mem (Binary oldval newval)));
5940
5941 ins_cost(2 * VOLATILE_REF_COST);
5942
5943 format %{
5944 "weak_cmpxchg $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5945 "# $res == 1 when success, #@weakCompareAndSwapB"
5946 %}
5947
5948 ins_encode %{
5949 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5950 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5951 %}
5952
5953 ins_pipe(pipe_slow);
5954 %}
5955
5956 instruct weakCompareAndSwapS_narrow(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5957 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5958 %{
5959 predicate(!UseZabha || !UseZacas);
5960
5961 match(Set res (WeakCompareAndSwapS mem (Binary oldval newval)));
5962
5963 ins_cost(2 * VOLATILE_REF_COST);
5964
5965 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5966
5967 format %{
5968 "weak_cmpxchg $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5969 "# $res == 1 when success, #@weakCompareAndSwapS_narrow"
5970 %}
5971
5972 ins_encode %{
5973 __ weak_cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5974 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
5975 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5976 %}
5977
5978 ins_pipe(pipe_slow);
5979 %}
5980
5981 instruct weakCompareAndSwapS(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5982 %{
5983 predicate(UseZabha && UseZacas);
5984
5985 match(Set res (WeakCompareAndSwapS mem (Binary oldval newval)));
5986
5987 ins_cost(2 * VOLATILE_REF_COST);
5988
5989 format %{
5990 "weak_cmpxchg $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5991 "# $res == 1 when success, #@weakCompareAndSwapS"
5992 %}
5993
5994 ins_encode %{
5995 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5996 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5997 %}
5998
5999 ins_pipe(pipe_slow);
6000 %}
6001
6002 instruct weakCompareAndSwapI(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
6003 %{
6004 match(Set res (WeakCompareAndSwapI mem (Binary oldval newval)));
6005
6006 ins_cost(2 * VOLATILE_REF_COST);
6007
6008 format %{
6009 "weak_cmpxchg $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval\n\t"
6010 "# $res == 1 when success, #@weakCompareAndSwapI"
6011 %}
6012
6013 ins_encode %{
6014 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
6015 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
6016 %}
6017
6018 ins_pipe(pipe_slow);
6019 %}
6020
6021 instruct weakCompareAndSwapL(iRegINoSp res, indirect mem, iRegL oldval, iRegL newval)
6022 %{
6023 match(Set res (WeakCompareAndSwapL mem (Binary oldval newval)));
6024
6025 ins_cost(2 * VOLATILE_REF_COST);
6026
6027 format %{
6028 "weak_cmpxchg $mem, $oldval, $newval\t# (long, weak) if $mem == $oldval then $mem <-- $newval\n\t"
6029 "# $res == 1 when success, #@weakCompareAndSwapL"
6030 %}
6031
6032 ins_encode %{
6033 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
6034 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
6035 %}
6036
6037 ins_pipe(pipe_slow);
6038 %}
6039
6040 instruct weakCompareAndSwapN(iRegINoSp res, indirect mem, iRegN oldval, iRegN newval)
6041 %{
6042 predicate(n->as_LoadStore()->barrier_data() == 0);
6043
6044 match(Set res (WeakCompareAndSwapN mem (Binary oldval newval)));
6045
6046 ins_cost(2 * VOLATILE_REF_COST);
6047
6048 format %{
6049 "weak_cmpxchg $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval\n\t"
6050 "# $res == 1 when success, #@weakCompareAndSwapN"
6051 %}
6052
6053 ins_encode %{
6054 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
6055 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
6056 %}
6057
6058 ins_pipe(pipe_slow);
6059 %}
6060
6061 instruct weakCompareAndSwapP(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval)
6062 %{
6063 predicate(n->as_LoadStore()->barrier_data() == 0);
6064
6065 match(Set res (WeakCompareAndSwapP mem (Binary oldval newval)));
6066
6067 ins_cost(2 * VOLATILE_REF_COST);
6068
6069 format %{
6070 "weak_cmpxchg $mem, $oldval, $newval\t# (ptr, weak) if $mem == $oldval then $mem <-- $newval\n\t"
6071 "# $res == 1 when success, #@weakCompareAndSwapP"
6072 %}
6073
6074 ins_encode %{
6075 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
6076 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
6077 %}
6078
6079 ins_pipe(pipe_slow);
6080 %}
6081
6082 instruct weakCompareAndSwapBAcq_narrow(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
6083 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
6084 %{
6085 predicate((!UseZabha || !UseZacas) && needs_acquiring_load_reserved(n));
6086
6087 match(Set res (WeakCompareAndSwapB mem (Binary oldval newval)));
6088
6089 ins_cost(2 * VOLATILE_REF_COST);
6090
6091 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
6092
6093 format %{
6094 "weak_cmpxchg_acq $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval\n\t"
6095 "# $res == 1 when success, #@weakCompareAndSwapBAcq_narrow"
6096 %}
6097
6098 ins_encode %{
6099 __ weak_cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
6100 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
6101 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
6102 %}
6103
6104 ins_pipe(pipe_slow);
6105 %}
6106
6107 instruct weakCompareAndSwapBAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
6108 %{
6109 predicate((UseZabha && UseZacas) && needs_acquiring_load_reserved(n));
6110
6111 match(Set res (WeakCompareAndSwapB mem (Binary oldval newval)));
6112
6113 ins_cost(2 * VOLATILE_REF_COST);
6114
6115 format %{
6116 "weak_cmpxchg_acq $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval\n\t"
6117 "# $res == 1 when success, #@weakCompareAndSwapBAcq"
6118 %}
6119
6120 ins_encode %{
6121 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
6122 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
6123 %}
6124
6125 ins_pipe(pipe_slow);
6126 %}
6127
6128 instruct weakCompareAndSwapSAcq_narrow(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
6129 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
6130 %{
6131 predicate((!UseZabha || !UseZacas) && needs_acquiring_load_reserved(n));
6132
6133 match(Set res (WeakCompareAndSwapS mem (Binary oldval newval)));
6134
6135 ins_cost(2 * VOLATILE_REF_COST);
6136
6137 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
6138
6139 format %{
6140 "weak_cmpxchg_acq $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval\n\t"
6141 "# $res == 1 when success, #@weakCompareAndSwapSAcq_narrow"
6142 %}
6143
6144 ins_encode %{
6145 __ weak_cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
6146 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
6147 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
6148 %}
6149
6150 ins_pipe(pipe_slow);
6151 %}
6152
6153 instruct weakCompareAndSwapSAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
6154 %{
6155 predicate((UseZabha && UseZacas) && needs_acquiring_load_reserved(n));
6156
6157 match(Set res (WeakCompareAndSwapS mem (Binary oldval newval)));
6158
6159 ins_cost(2 * VOLATILE_REF_COST);
6160
6161 format %{
6162 "weak_cmpxchg_acq $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval\n\t"
6163 "# $res == 1 when success, #@weakCompareAndSwapSAcq"
6164 %}
6165
6166 ins_encode %{
6167 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
6168 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
6169 %}
6170
6171 ins_pipe(pipe_slow);
6172 %}
6173
6174 instruct weakCompareAndSwapIAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
6175 %{
6176 predicate(needs_acquiring_load_reserved(n));
6177
6178 match(Set res (WeakCompareAndSwapI mem (Binary oldval newval)));
6179
6180 ins_cost(2 * VOLATILE_REF_COST);
6181
6182 format %{
6183 "weak_cmpxchg_acq $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval\n\t"
6184 "# $res == 1 when success, #@weakCompareAndSwapIAcq"
6185 %}
6186
6187 ins_encode %{
6188 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
6189 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
6190 %}
6191
6192 ins_pipe(pipe_slow);
6193 %}
6194
6195 instruct weakCompareAndSwapLAcq(iRegINoSp res, indirect mem, iRegL oldval, iRegL newval)
6196 %{
6197 predicate(needs_acquiring_load_reserved(n));
6198
6199 match(Set res (WeakCompareAndSwapL mem (Binary oldval newval)));
6200
6201 ins_cost(2 * VOLATILE_REF_COST);
6202
6203 format %{
6204 "weak_cmpxchg_acq $mem, $oldval, $newval\t# (long, weak) if $mem == $oldval then $mem <-- $newval\n\t"
6205 "# $res == 1 when success, #@weakCompareAndSwapLAcq"
6206 %}
6207
6208 ins_encode %{
6209 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
6210 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
6211 %}
6212
6213 ins_pipe(pipe_slow);
6214 %}
6215
6216 instruct weakCompareAndSwapNAcq(iRegINoSp res, indirect mem, iRegN oldval, iRegN newval)
6217 %{
6218 predicate(needs_acquiring_load_reserved(n) && n->as_LoadStore()->barrier_data() == 0);
6219
6220 match(Set res (WeakCompareAndSwapN mem (Binary oldval newval)));
6221
6222 ins_cost(2 * VOLATILE_REF_COST);
6223
6224 format %{
6225 "weak_cmpxchg_acq $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval\n\t"
6226 "# $res == 1 when success, #@weakCompareAndSwapNAcq"
6227 %}
6228
6229 ins_encode %{
6230 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
6231 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
6232 %}
6233
6234 ins_pipe(pipe_slow);
6235 %}
6236
6237 instruct weakCompareAndSwapPAcq(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval)
6238 %{
6239 predicate(needs_acquiring_load_reserved(n) && (n->as_LoadStore()->barrier_data() == 0));
6240
6241 match(Set res (WeakCompareAndSwapP mem (Binary oldval newval)));
6242
6243 ins_cost(2 * VOLATILE_REF_COST);
6244
6245 format %{
6246 "weak_cmpxchg_acq $mem, $oldval, $newval\t# (ptr, weak) if $mem == $oldval then $mem <-- $newval\n\t"
6247 "\t# $res == 1 when success, #@weakCompareAndSwapPAcq"
6248 %}
6249
6250 ins_encode %{
6251 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
6252 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
6253 %}
6254
6255 ins_pipe(pipe_slow);
6256 %}
6257
6258 instruct get_and_setI(indirect mem, iRegI newv, iRegINoSp prev)
6259 %{
6260 match(Set prev (GetAndSetI mem newv));
6261
6262 ins_cost(ALU_COST);
6263
6264 format %{ "atomic_xchgw $prev, $newv, [$mem]\t#@get_and_setI" %}
6265
6266 ins_encode %{
6267 __ atomic_xchgw($prev$$Register, $newv$$Register, as_Register($mem$$base));
6268 %}
6269
6270 ins_pipe(pipe_serial);
6271 %}
6272
6273 instruct get_and_setL(indirect mem, iRegL newv, iRegLNoSp prev)
6274 %{
6275 match(Set prev (GetAndSetL mem newv));
6276
6277 ins_cost(ALU_COST);
6278
6279 format %{ "atomic_xchg $prev, $newv, [$mem]\t#@get_and_setL" %}
6280
6281 ins_encode %{
6282 __ atomic_xchg($prev$$Register, $newv$$Register, as_Register($mem$$base));
6283 %}
6284
6285 ins_pipe(pipe_serial);
6286 %}
6287
6288 instruct get_and_setN(indirect mem, iRegN newv, iRegINoSp prev)
6289 %{
6290 predicate(n->as_LoadStore()->barrier_data() == 0);
6291
6292 match(Set prev (GetAndSetN mem newv));
6293
6294 ins_cost(ALU_COST);
6295
6296 format %{ "atomic_xchgwu $prev, $newv, [$mem]\t#@get_and_setN" %}
6297
6298 ins_encode %{
6299 __ atomic_xchgwu($prev$$Register, $newv$$Register, as_Register($mem$$base));
6300 %}
6301
6302 ins_pipe(pipe_serial);
6303 %}
6304
6305 instruct get_and_setP(indirect mem, iRegP newv, iRegPNoSp prev)
6306 %{
6307 predicate(n->as_LoadStore()->barrier_data() == 0);
6308 match(Set prev (GetAndSetP mem newv));
6309
6310 ins_cost(ALU_COST);
6311
6312 format %{ "atomic_xchg $prev, $newv, [$mem]\t#@get_and_setP" %}
6313
6314 ins_encode %{
6315 __ atomic_xchg($prev$$Register, $newv$$Register, as_Register($mem$$base));
6316 %}
6317
6318 ins_pipe(pipe_serial);
6319 %}
6320
6321 instruct get_and_setIAcq(indirect mem, iRegI newv, iRegINoSp prev)
6322 %{
6323 predicate(needs_acquiring_load_reserved(n));
6324
6325 match(Set prev (GetAndSetI mem newv));
6326
6327 ins_cost(ALU_COST);
6328
6329 format %{ "atomic_xchgw_acq $prev, $newv, [$mem]\t#@get_and_setIAcq" %}
6330
6331 ins_encode %{
6332 __ atomic_xchgalw($prev$$Register, $newv$$Register, as_Register($mem$$base));
6333 %}
6334
6335 ins_pipe(pipe_serial);
6336 %}
6337
6338 instruct get_and_setLAcq(indirect mem, iRegL newv, iRegLNoSp prev)
6339 %{
6340 predicate(needs_acquiring_load_reserved(n));
6341
6342 match(Set prev (GetAndSetL mem newv));
6343
6344 ins_cost(ALU_COST);
6345
6346 format %{ "atomic_xchg_acq $prev, $newv, [$mem]\t#@get_and_setLAcq" %}
6347
6348 ins_encode %{
6349 __ atomic_xchgal($prev$$Register, $newv$$Register, as_Register($mem$$base));
6350 %}
6351
6352 ins_pipe(pipe_serial);
6353 %}
6354
6355 instruct get_and_setNAcq(indirect mem, iRegN newv, iRegINoSp prev)
6356 %{
6357 predicate(needs_acquiring_load_reserved(n) && n->as_LoadStore()->barrier_data() == 0);
6358
6359 match(Set prev (GetAndSetN mem newv));
6360
6361 ins_cost(ALU_COST);
6362
6363 format %{ "atomic_xchgwu_acq $prev, $newv, [$mem]\t#@get_and_setNAcq" %}
6364
6365 ins_encode %{
6366 __ atomic_xchgalwu($prev$$Register, $newv$$Register, as_Register($mem$$base));
6367 %}
6368
6369 ins_pipe(pipe_serial);
6370 %}
6371
6372 instruct get_and_setPAcq(indirect mem, iRegP newv, iRegPNoSp prev)
6373 %{
6374 predicate(needs_acquiring_load_reserved(n) && (n->as_LoadStore()->barrier_data() == 0));
6375
6376 match(Set prev (GetAndSetP mem newv));
6377
6378 ins_cost(ALU_COST);
6379
6380 format %{ "atomic_xchg_acq $prev, $newv, [$mem]\t#@get_and_setPAcq" %}
6381
6382 ins_encode %{
6383 __ atomic_xchgal($prev$$Register, $newv$$Register, as_Register($mem$$base));
6384 %}
6385
6386 ins_pipe(pipe_serial);
6387 %}
6388
6389 instruct get_and_addL(indirect mem, iRegLNoSp newval, iRegL incr)
6390 %{
6391 match(Set newval (GetAndAddL mem incr));
6392
6393 ins_cost(ALU_COST);
6394
6395 format %{ "get_and_addL $newval, [$mem], $incr\t#@get_and_addL" %}
6396
6397 ins_encode %{
6398 __ atomic_add($newval$$Register, $incr$$Register, as_Register($mem$$base));
6399 %}
6400
6401 ins_pipe(pipe_serial);
6402 %}
6403
6404 instruct get_and_addL_no_res(indirect mem, Universe dummy, iRegL incr)
6405 %{
6406 predicate(n->as_LoadStore()->result_not_used());
6407
6408 match(Set dummy (GetAndAddL mem incr));
6409
6410 ins_cost(ALU_COST);
6411
6412 format %{ "get_and_addL [$mem], $incr\t#@get_and_addL_no_res" %}
6413
6414 ins_encode %{
6415 __ atomic_add(noreg, $incr$$Register, as_Register($mem$$base));
6416 %}
6417
6418 ins_pipe(pipe_serial);
6419 %}
6420
6421 instruct get_and_addLi(indirect mem, iRegLNoSp newval, immLAdd incr)
6422 %{
6423 match(Set newval (GetAndAddL mem incr));
6424
6425 ins_cost(ALU_COST);
6426
6427 format %{ "get_and_addL $newval, [$mem], $incr\t#@get_and_addLi" %}
6428
6429 ins_encode %{
6430 __ atomic_add($newval$$Register, $incr$$constant, as_Register($mem$$base));
6431 %}
6432
6433 ins_pipe(pipe_serial);
6434 %}
6435
6436 instruct get_and_addLi_no_res(indirect mem, Universe dummy, immLAdd incr)
6437 %{
6438 predicate(n->as_LoadStore()->result_not_used());
6439
6440 match(Set dummy (GetAndAddL mem incr));
6441
6442 ins_cost(ALU_COST);
6443
6444 format %{ "get_and_addL [$mem], $incr\t#@get_and_addLi_no_res" %}
6445
6446 ins_encode %{
6447 __ atomic_add(noreg, $incr$$constant, as_Register($mem$$base));
6448 %}
6449
6450 ins_pipe(pipe_serial);
6451 %}
6452
6453 instruct get_and_addI(indirect mem, iRegINoSp newval, iRegIorL2I incr)
6454 %{
6455 match(Set newval (GetAndAddI mem incr));
6456
6457 ins_cost(ALU_COST);
6458
6459 format %{ "get_and_addI $newval, [$mem], $incr\t#@get_and_addI" %}
6460
6461 ins_encode %{
6462 __ atomic_addw($newval$$Register, $incr$$Register, as_Register($mem$$base));
6463 %}
6464
6465 ins_pipe(pipe_serial);
6466 %}
6467
6468 instruct get_and_addI_no_res(indirect mem, Universe dummy, iRegIorL2I incr)
6469 %{
6470 predicate(n->as_LoadStore()->result_not_used());
6471
6472 match(Set dummy (GetAndAddI mem incr));
6473
6474 ins_cost(ALU_COST);
6475
6476 format %{ "get_and_addI [$mem], $incr\t#@get_and_addI_no_res" %}
6477
6478 ins_encode %{
6479 __ atomic_addw(noreg, $incr$$Register, as_Register($mem$$base));
6480 %}
6481
6482 ins_pipe(pipe_serial);
6483 %}
6484
6485 instruct get_and_addIi(indirect mem, iRegINoSp newval, immIAdd incr)
6486 %{
6487 match(Set newval (GetAndAddI mem incr));
6488
6489 ins_cost(ALU_COST);
6490
6491 format %{ "get_and_addI $newval, [$mem], $incr\t#@get_and_addIi" %}
6492
6493 ins_encode %{
6494 __ atomic_addw($newval$$Register, $incr$$constant, as_Register($mem$$base));
6495 %}
6496
6497 ins_pipe(pipe_serial);
6498 %}
6499
6500 instruct get_and_addIi_no_res(indirect mem, Universe dummy, immIAdd incr)
6501 %{
6502 predicate(n->as_LoadStore()->result_not_used());
6503
6504 match(Set dummy (GetAndAddI mem incr));
6505
6506 ins_cost(ALU_COST);
6507
6508 format %{ "get_and_addI [$mem], $incr\t#@get_and_addIi_no_res" %}
6509
6510 ins_encode %{
6511 __ atomic_addw(noreg, $incr$$constant, as_Register($mem$$base));
6512 %}
6513
6514 ins_pipe(pipe_serial);
6515 %}
6516
6517 instruct get_and_addLAcq(indirect mem, iRegLNoSp newval, iRegL incr)
6518 %{
6519 predicate(needs_acquiring_load_reserved(n));
6520
6521 match(Set newval (GetAndAddL mem incr));
6522
6523 ins_cost(ALU_COST);
6524
6525 format %{ "get_and_addL_acq $newval, [$mem], $incr\t#@get_and_addLAcq" %}
6526
6527 ins_encode %{
6528 __ atomic_addal($newval$$Register, $incr$$Register, as_Register($mem$$base));
6529 %}
6530
6531 ins_pipe(pipe_serial);
6532 %}
6533
6534 instruct get_and_addL_no_resAcq(indirect mem, Universe dummy, iRegL incr) %{
6535 predicate(n->as_LoadStore()->result_not_used() && needs_acquiring_load_reserved(n));
6536
6537 match(Set dummy (GetAndAddL mem incr));
6538
6539 ins_cost(ALU_COST);
6540
6541 format %{ "get_and_addL_acq [$mem], $incr\t#@get_and_addL_no_resAcq" %}
6542
6543 ins_encode %{
6544 __ atomic_addal(noreg, $incr$$Register, as_Register($mem$$base));
6545 %}
6546
6547 ins_pipe(pipe_serial);
6548 %}
6549
6550 instruct get_and_addLiAcq(indirect mem, iRegLNoSp newval, immLAdd incr)
6551 %{
6552 predicate(needs_acquiring_load_reserved(n));
6553
6554 match(Set newval (GetAndAddL mem incr));
6555
6556 ins_cost(ALU_COST);
6557
6558 format %{ "get_and_addL_acq $newval, [$mem], $incr\t#@get_and_addLiAcq" %}
6559
6560 ins_encode %{
6561 __ atomic_addal($newval$$Register, $incr$$constant, as_Register($mem$$base));
6562 %}
6563
6564 ins_pipe(pipe_serial);
6565 %}
6566
6567 instruct get_and_addLi_no_resAcq(indirect mem, Universe dummy, immLAdd incr)
6568 %{
6569 predicate(n->as_LoadStore()->result_not_used() && needs_acquiring_load_reserved(n));
6570
6571 match(Set dummy (GetAndAddL mem incr));
6572
6573 ins_cost(ALU_COST);
6574
6575 format %{ "get_and_addL_acq [$mem], $incr\t#@get_and_addLi_no_resAcq" %}
6576
6577 ins_encode %{
6578 __ atomic_addal(noreg, $incr$$constant, as_Register($mem$$base));
6579 %}
6580
6581 ins_pipe(pipe_serial);
6582 %}
6583
6584 instruct get_and_addIAcq(indirect mem, iRegINoSp newval, iRegIorL2I incr)
6585 %{
6586 predicate(needs_acquiring_load_reserved(n));
6587
6588 match(Set newval (GetAndAddI mem incr));
6589
6590 ins_cost(ALU_COST);
6591
6592 format %{ "get_and_addI_acq $newval, [$mem], $incr\t#@get_and_addIAcq" %}
6593
6594 ins_encode %{
6595 __ atomic_addalw($newval$$Register, $incr$$Register, as_Register($mem$$base));
6596 %}
6597
6598 ins_pipe(pipe_serial);
6599 %}
6600
6601 instruct get_and_addI_no_resAcq(indirect mem, Universe dummy, iRegIorL2I incr)
6602 %{
6603 predicate(n->as_LoadStore()->result_not_used() && needs_acquiring_load_reserved(n));
6604
6605 match(Set dummy (GetAndAddI mem incr));
6606
6607 ins_cost(ALU_COST);
6608
6609 format %{ "get_and_addI_acq [$mem], $incr\t#@get_and_addI_no_resAcq" %}
6610
6611 ins_encode %{
6612 __ atomic_addalw(noreg, $incr$$Register, as_Register($mem$$base));
6613 %}
6614
6615 ins_pipe(pipe_serial);
6616 %}
6617
6618 instruct get_and_addIiAcq(indirect mem, iRegINoSp newval, immIAdd incr)
6619 %{
6620 predicate(needs_acquiring_load_reserved(n));
6621
6622 match(Set newval (GetAndAddI mem incr));
6623
6624 ins_cost(ALU_COST);
6625
6626 format %{ "get_and_addI_acq $newval, [$mem], $incr\t#@get_and_addIiAcq" %}
6627
6628 ins_encode %{
6629 __ atomic_addalw($newval$$Register, $incr$$constant, as_Register($mem$$base));
6630 %}
6631
6632 ins_pipe(pipe_serial);
6633 %}
6634
6635 instruct get_and_addIi_no_resAcq(indirect mem, Universe dummy, immIAdd incr)
6636 %{
6637 predicate(n->as_LoadStore()->result_not_used() && needs_acquiring_load_reserved(n));
6638
6639 match(Set dummy (GetAndAddI mem incr));
6640
6641 ins_cost(ALU_COST);
6642
6643 format %{ "get_and_addI_acq [$mem], $incr\t#@get_and_addIi_no_resAcq" %}
6644
6645 ins_encode %{
6646 __ atomic_addalw(noreg, $incr$$constant, as_Register($mem$$base));
6647 %}
6648
6649 ins_pipe(pipe_serial);
6650 %}
6651
6652 // ============================================================================
6653 // Arithmetic Instructions
6654 //
6655
6656 // Integer Addition
6657
6658 // TODO
6659 // these currently employ operations which do not set CR and hence are
6660 // not flagged as killing CR but we would like to isolate the cases
6661 // where we want to set flags from those where we don't. need to work
6662 // out how to do that.
6663 instruct addI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6664 match(Set dst (AddI src1 src2));
6665
6666 ins_cost(ALU_COST);
6667 format %{ "addw $dst, $src1, $src2\t#@addI_reg_reg" %}
6668
6669 ins_encode %{
6670 __ addw(as_Register($dst$$reg),
6671 as_Register($src1$$reg),
6672 as_Register($src2$$reg));
6673 %}
6674
6675 ins_pipe(ialu_reg_reg);
6676 %}
6677
6678 instruct addI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immIAdd src2) %{
6679 match(Set dst (AddI src1 src2));
6680
6681 ins_cost(ALU_COST);
6682 format %{ "addiw $dst, $src1, $src2\t#@addI_reg_imm" %}
6683
6684 ins_encode %{
6685 __ addiw(as_Register($dst$$reg),
6686 as_Register($src1$$reg),
6687 $src2$$constant);
6688 %}
6689
6690 ins_pipe(ialu_reg_imm);
6691 %}
6692
6693 instruct addI_reg_imm_l2i(iRegINoSp dst, iRegL src1, immIAdd src2) %{
6694 match(Set dst (AddI (ConvL2I src1) src2));
6695
6696 ins_cost(ALU_COST);
6697 format %{ "addiw $dst, $src1, $src2\t#@addI_reg_imm_l2i" %}
6698
6699 ins_encode %{
6700 __ addiw(as_Register($dst$$reg),
6701 as_Register($src1$$reg),
6702 $src2$$constant);
6703 %}
6704
6705 ins_pipe(ialu_reg_imm);
6706 %}
6707
6708 // Pointer Addition
6709 instruct addP_reg_reg(iRegPNoSp dst, iRegP src1, iRegL src2) %{
6710 match(Set dst (AddP src1 src2));
6711
6712 ins_cost(ALU_COST);
6713 format %{ "add $dst, $src1, $src2\t# ptr, #@addP_reg_reg" %}
6714
6715 ins_encode %{
6716 __ add(as_Register($dst$$reg),
6717 as_Register($src1$$reg),
6718 as_Register($src2$$reg));
6719 %}
6720
6721 ins_pipe(ialu_reg_reg);
6722 %}
6723
6724 // If we shift more than 32 bits, we need not convert I2L.
6725 instruct lShiftL_regI_immGE32(iRegLNoSp dst, iRegI src, uimmI6_ge32 scale) %{
6726 match(Set dst (LShiftL (ConvI2L src) scale));
6727 ins_cost(ALU_COST);
6728 format %{ "slli $dst, $src, $scale & 63\t#@lShiftL_regI_immGE32" %}
6729
6730 ins_encode %{
6731 __ slli(as_Register($dst$$reg), as_Register($src$$reg), $scale$$constant & 63);
6732 %}
6733
6734 ins_pipe(ialu_reg_shift);
6735 %}
6736
6737 // Pointer Immediate Addition
6738 // n.b. this needs to be more expensive than using an indirect memory
6739 // operand
6740 instruct addP_reg_imm(iRegPNoSp dst, iRegP src1, immLAdd src2) %{
6741 match(Set dst (AddP src1 src2));
6742 ins_cost(ALU_COST);
6743 format %{ "addi $dst, $src1, $src2\t# ptr, #@addP_reg_imm" %}
6744
6745 ins_encode %{
6746 __ addi(as_Register($dst$$reg),
6747 as_Register($src1$$reg),
6748 $src2$$constant);
6749 %}
6750
6751 ins_pipe(ialu_reg_imm);
6752 %}
6753
6754 // Long Addition
6755 instruct addL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
6756 match(Set dst (AddL src1 src2));
6757 ins_cost(ALU_COST);
6758 format %{ "add $dst, $src1, $src2\t#@addL_reg_reg" %}
6759
6760 ins_encode %{
6761 __ add(as_Register($dst$$reg),
6762 as_Register($src1$$reg),
6763 as_Register($src2$$reg));
6764 %}
6765
6766 ins_pipe(ialu_reg_reg);
6767 %}
6768
6769 // No constant pool entries requiredLong Immediate Addition.
6770 instruct addL_reg_imm(iRegLNoSp dst, iRegL src1, immLAdd src2) %{
6771 match(Set dst (AddL src1 src2));
6772 ins_cost(ALU_COST);
6773 format %{ "addi $dst, $src1, $src2\t#@addL_reg_imm" %}
6774
6775 ins_encode %{
6776 // src2 is imm, so actually call the addi
6777 __ addi(as_Register($dst$$reg),
6778 as_Register($src1$$reg),
6779 $src2$$constant);
6780 %}
6781
6782 ins_pipe(ialu_reg_imm);
6783 %}
6784
6785 // Integer Subtraction
6786 instruct subI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6787 match(Set dst (SubI src1 src2));
6788
6789 ins_cost(ALU_COST);
6790 format %{ "subw $dst, $src1, $src2\t#@subI_reg_reg" %}
6791
6792 ins_encode %{
6793 __ subw(as_Register($dst$$reg),
6794 as_Register($src1$$reg),
6795 as_Register($src2$$reg));
6796 %}
6797
6798 ins_pipe(ialu_reg_reg);
6799 %}
6800
6801 // Immediate Subtraction
6802 instruct subI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immISub src2) %{
6803 match(Set dst (SubI src1 src2));
6804
6805 ins_cost(ALU_COST);
6806 format %{ "addiw $dst, $src1, -$src2\t#@subI_reg_imm" %}
6807
6808 ins_encode %{
6809 // src2 is imm, so actually call the addiw
6810 __ subiw(as_Register($dst$$reg),
6811 as_Register($src1$$reg),
6812 $src2$$constant);
6813 %}
6814
6815 ins_pipe(ialu_reg_imm);
6816 %}
6817
6818 // Long Subtraction
6819 instruct subL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
6820 match(Set dst (SubL src1 src2));
6821 ins_cost(ALU_COST);
6822 format %{ "sub $dst, $src1, $src2\t#@subL_reg_reg" %}
6823
6824 ins_encode %{
6825 __ sub(as_Register($dst$$reg),
6826 as_Register($src1$$reg),
6827 as_Register($src2$$reg));
6828 %}
6829
6830 ins_pipe(ialu_reg_reg);
6831 %}
6832
6833 // No constant pool entries requiredLong Immediate Subtraction.
6834 instruct subL_reg_imm(iRegLNoSp dst, iRegL src1, immLSub src2) %{
6835 match(Set dst (SubL src1 src2));
6836 ins_cost(ALU_COST);
6837 format %{ "addi $dst, $src1, -$src2\t#@subL_reg_imm" %}
6838
6839 ins_encode %{
6840 // src2 is imm, so actually call the addi
6841 __ subi(as_Register($dst$$reg),
6842 as_Register($src1$$reg),
6843 $src2$$constant);
6844 %}
6845
6846 ins_pipe(ialu_reg_imm);
6847 %}
6848
6849 // Integer Negation (special case for sub)
6850
6851 instruct negI_reg(iRegINoSp dst, iRegIorL2I src, immI0 zero) %{
6852 match(Set dst (SubI zero src));
6853 ins_cost(ALU_COST);
6854 format %{ "subw $dst, x0, $src\t# int, #@negI_reg" %}
6855
6856 ins_encode %{
6857 // actually call the subw
6858 __ negw(as_Register($dst$$reg),
6859 as_Register($src$$reg));
6860 %}
6861
6862 ins_pipe(ialu_reg);
6863 %}
6864
6865 // Long Negation
6866
6867 instruct negL_reg(iRegLNoSp dst, iRegL src, immL0 zero) %{
6868 match(Set dst (SubL zero src));
6869 ins_cost(ALU_COST);
6870 format %{ "sub $dst, x0, $src\t# long, #@negL_reg" %}
6871
6872 ins_encode %{
6873 // actually call the sub
6874 __ neg(as_Register($dst$$reg),
6875 as_Register($src$$reg));
6876 %}
6877
6878 ins_pipe(ialu_reg);
6879 %}
6880
6881 // Integer Multiply
6882
6883 instruct mulI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6884 match(Set dst (MulI src1 src2));
6885 ins_cost(IMUL_COST);
6886 format %{ "mulw $dst, $src1, $src2\t#@mulI" %}
6887
6888 //this means 2 word multi, and no sign extend to 64 bits
6889 ins_encode %{
6890 // riscv64 mulw will sign-extension to high 32 bits in dst reg
6891 __ mulw(as_Register($dst$$reg),
6892 as_Register($src1$$reg),
6893 as_Register($src2$$reg));
6894 %}
6895
6896 ins_pipe(imul_reg_reg);
6897 %}
6898
6899 // Long Multiply
6900
6901 instruct mulL(iRegLNoSp dst, iRegL src1, iRegL src2) %{
6902 match(Set dst (MulL src1 src2));
6903 ins_cost(IMUL_COST);
6904 format %{ "mul $dst, $src1, $src2\t#@mulL" %}
6905
6906 ins_encode %{
6907 __ mul(as_Register($dst$$reg),
6908 as_Register($src1$$reg),
6909 as_Register($src2$$reg));
6910 %}
6911
6912 ins_pipe(lmul_reg_reg);
6913 %}
6914
6915 instruct mulHiL_rReg(iRegLNoSp dst, iRegL src1, iRegL src2)
6916 %{
6917 match(Set dst (MulHiL src1 src2));
6918 ins_cost(IMUL_COST);
6919 format %{ "mulh $dst, $src1, $src2\t# mulhi, #@mulHiL_rReg" %}
6920
6921 ins_encode %{
6922 __ mulh(as_Register($dst$$reg),
6923 as_Register($src1$$reg),
6924 as_Register($src2$$reg));
6925 %}
6926
6927 ins_pipe(lmul_reg_reg);
6928 %}
6929
6930 instruct umulHiL_rReg(iRegLNoSp dst, iRegL src1, iRegL src2)
6931 %{
6932 match(Set dst (UMulHiL src1 src2));
6933 ins_cost(IMUL_COST);
6934 format %{ "mulhu $dst, $src1, $src2\t# umulhi, #@umulHiL_rReg" %}
6935
6936 ins_encode %{
6937 __ mulhu(as_Register($dst$$reg),
6938 as_Register($src1$$reg),
6939 as_Register($src2$$reg));
6940 %}
6941
6942 ins_pipe(lmul_reg_reg);
6943 %}
6944
6945 // Integer Divide
6946
6947 instruct divI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6948 match(Set dst (DivI src1 src2));
6949 ins_cost(IDIVSI_COST);
6950 format %{ "divw $dst, $src1, $src2\t#@divI"%}
6951
6952 ins_encode %{
6953 __ divw(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg));
6954 %}
6955 ins_pipe(idiv_reg_reg);
6956 %}
6957
6958 instruct UdivI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6959 match(Set dst (UDivI src1 src2));
6960 ins_cost(IDIVSI_COST);
6961 format %{ "divuw $dst, $src1, $src2\t#@UdivI"%}
6962
6963 ins_encode %{
6964 __ divuw(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg));
6965 %}
6966 ins_pipe(idiv_reg_reg);
6967 %}
6968
6969 instruct signExtract(iRegINoSp dst, iRegIorL2I src1, immI_31 div1, immI_31 div2) %{
6970 match(Set dst (URShiftI (RShiftI src1 div1) div2));
6971 ins_cost(ALU_COST);
6972 format %{ "srliw $dst, $src1, $div1\t# int signExtract, #@signExtract" %}
6973
6974 ins_encode %{
6975 __ srliw(as_Register($dst$$reg), as_Register($src1$$reg), 31);
6976 %}
6977 ins_pipe(ialu_reg_shift);
6978 %}
6979
6980 // Long Divide
6981
6982 instruct divL(iRegLNoSp dst, iRegL src1, iRegL src2) %{
6983 match(Set dst (DivL src1 src2));
6984 ins_cost(IDIVDI_COST);
6985 format %{ "div $dst, $src1, $src2\t#@divL" %}
6986
6987 ins_encode %{
6988 __ div(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg));
6989 %}
6990 ins_pipe(ldiv_reg_reg);
6991 %}
6992
6993 instruct UdivL(iRegLNoSp dst, iRegL src1, iRegL src2) %{
6994 match(Set dst (UDivL src1 src2));
6995 ins_cost(IDIVDI_COST);
6996
6997 format %{ "divu $dst, $src1, $src2\t#@UdivL" %}
6998
6999 ins_encode %{
7000 __ divu(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg));
7001 %}
7002 ins_pipe(ldiv_reg_reg);
7003 %}
7004
7005 instruct signExtractL(iRegLNoSp dst, iRegL src1, immI_63 div1, immI_63 div2) %{
7006 match(Set dst (URShiftL (RShiftL src1 div1) div2));
7007 ins_cost(ALU_COST);
7008 format %{ "srli $dst, $src1, $div1\t# long signExtract, #@signExtractL" %}
7009
7010 ins_encode %{
7011 __ srli(as_Register($dst$$reg), as_Register($src1$$reg), 63);
7012 %}
7013 ins_pipe(ialu_reg_shift);
7014 %}
7015
7016 // Integer Remainder
7017
7018 instruct modI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
7019 match(Set dst (ModI src1 src2));
7020 ins_cost(IDIVSI_COST);
7021 format %{ "remw $dst, $src1, $src2\t#@modI" %}
7022
7023 ins_encode %{
7024 __ remw(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg));
7025 %}
7026 ins_pipe(ialu_reg_reg);
7027 %}
7028
7029 instruct UmodI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
7030 match(Set dst (UModI src1 src2));
7031 ins_cost(IDIVSI_COST);
7032 format %{ "remuw $dst, $src1, $src2\t#@UmodI" %}
7033
7034 ins_encode %{
7035 __ remuw(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg));
7036 %}
7037 ins_pipe(ialu_reg_reg);
7038 %}
7039
7040 // Long Remainder
7041
7042 instruct modL(iRegLNoSp dst, iRegL src1, iRegL src2) %{
7043 match(Set dst (ModL src1 src2));
7044 ins_cost(IDIVDI_COST);
7045 format %{ "rem $dst, $src1, $src2\t#@modL" %}
7046
7047 ins_encode %{
7048 __ rem(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg));
7049 %}
7050 ins_pipe(ialu_reg_reg);
7051 %}
7052
7053 instruct UmodL(iRegLNoSp dst, iRegL src1, iRegL src2) %{
7054 match(Set dst (UModL src1 src2));
7055 ins_cost(IDIVDI_COST);
7056 format %{ "remu $dst, $src1, $src2\t#@UmodL" %}
7057
7058 ins_encode %{
7059 __ remu(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg));
7060 %}
7061 ins_pipe(ialu_reg_reg);
7062 %}
7063
7064 // Integer Shifts
7065
7066 // Shift Left Register
7067 // Only the low 5 bits of src2 are considered for the shift amount, all other bits are ignored.
7068 instruct lShiftI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
7069 match(Set dst (LShiftI src1 src2));
7070 ins_cost(ALU_COST);
7071 format %{ "sllw $dst, $src1, $src2\t#@lShiftI_reg_reg" %}
7072
7073 ins_encode %{
7074 __ sllw(as_Register($dst$$reg),
7075 as_Register($src1$$reg),
7076 as_Register($src2$$reg));
7077 %}
7078
7079 ins_pipe(ialu_reg_reg_vshift);
7080 %}
7081
7082 // Shift Left Immediate
7083 instruct lShiftI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immI src2) %{
7084 match(Set dst (LShiftI src1 src2));
7085 ins_cost(ALU_COST);
7086 format %{ "slliw $dst, $src1, ($src2 & 0x1f)\t#@lShiftI_reg_imm" %}
7087
7088 ins_encode %{
7089 // the shift amount is encoded in the lower
7090 // 5 bits of the I-immediate field for RV32I
7091 __ slliw(as_Register($dst$$reg),
7092 as_Register($src1$$reg),
7093 (unsigned) $src2$$constant & 0x1f);
7094 %}
7095
7096 ins_pipe(ialu_reg_shift);
7097 %}
7098
7099 // Shift Right Logical Register
7100 // Only the low 5 bits of src2 are considered for the shift amount, all other bits are ignored.
7101 instruct urShiftI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
7102 match(Set dst (URShiftI src1 src2));
7103 ins_cost(ALU_COST);
7104 format %{ "srlw $dst, $src1, $src2\t#@urShiftI_reg_reg" %}
7105
7106 ins_encode %{
7107 __ srlw(as_Register($dst$$reg),
7108 as_Register($src1$$reg),
7109 as_Register($src2$$reg));
7110 %}
7111
7112 ins_pipe(ialu_reg_reg_vshift);
7113 %}
7114
7115 // Shift Right Logical Immediate
7116 instruct urShiftI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immI src2) %{
7117 match(Set dst (URShiftI src1 src2));
7118 ins_cost(ALU_COST);
7119 format %{ "srliw $dst, $src1, ($src2 & 0x1f)\t#@urShiftI_reg_imm" %}
7120
7121 ins_encode %{
7122 // the shift amount is encoded in the lower
7123 // 6 bits of the I-immediate field for RV64I
7124 __ srliw(as_Register($dst$$reg),
7125 as_Register($src1$$reg),
7126 (unsigned) $src2$$constant & 0x1f);
7127 %}
7128
7129 ins_pipe(ialu_reg_shift);
7130 %}
7131
7132 // Shift Right Arithmetic Register
7133 // Only the low 5 bits of src2 are considered for the shift amount, all other bits are ignored.
7134 instruct rShiftI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
7135 match(Set dst (RShiftI src1 src2));
7136 ins_cost(ALU_COST);
7137 format %{ "sraw $dst, $src1, $src2\t#@rShiftI_reg_reg" %}
7138
7139 ins_encode %{
7140 // riscv will sign-ext dst high 32 bits
7141 __ sraw(as_Register($dst$$reg),
7142 as_Register($src1$$reg),
7143 as_Register($src2$$reg));
7144 %}
7145
7146 ins_pipe(ialu_reg_reg_vshift);
7147 %}
7148
7149 // Shift Right Arithmetic Immediate
7150 instruct rShiftI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immI src2) %{
7151 match(Set dst (RShiftI src1 src2));
7152 ins_cost(ALU_COST);
7153 format %{ "sraiw $dst, $src1, ($src2 & 0x1f)\t#@rShiftI_reg_imm" %}
7154
7155 ins_encode %{
7156 // riscv will sign-ext dst high 32 bits
7157 __ sraiw(as_Register($dst$$reg),
7158 as_Register($src1$$reg),
7159 (unsigned) $src2$$constant & 0x1f);
7160 %}
7161
7162 ins_pipe(ialu_reg_shift);
7163 %}
7164
7165 // Long Shifts
7166
7167 // Shift Left Register
7168 // Only the low 6 bits of src2 are considered for the shift amount, all other bits are ignored.
7169 instruct lShiftL_reg_reg(iRegLNoSp dst, iRegL src1, iRegIorL2I src2) %{
7170 match(Set dst (LShiftL src1 src2));
7171
7172 ins_cost(ALU_COST);
7173 format %{ "sll $dst, $src1, $src2\t#@lShiftL_reg_reg" %}
7174
7175 ins_encode %{
7176 __ sll(as_Register($dst$$reg),
7177 as_Register($src1$$reg),
7178 as_Register($src2$$reg));
7179 %}
7180
7181 ins_pipe(ialu_reg_reg_vshift);
7182 %}
7183
7184 // Shift Left Immediate
7185 instruct lShiftL_reg_imm(iRegLNoSp dst, iRegL src1, immI src2) %{
7186 match(Set dst (LShiftL src1 src2));
7187
7188 ins_cost(ALU_COST);
7189 format %{ "slli $dst, $src1, ($src2 & 0x3f)\t#@lShiftL_reg_imm" %}
7190
7191 ins_encode %{
7192 // the shift amount is encoded in the lower
7193 // 6 bits of the I-immediate field for RV64I
7194 __ slli(as_Register($dst$$reg),
7195 as_Register($src1$$reg),
7196 (unsigned) $src2$$constant & 0x3f);
7197 %}
7198
7199 ins_pipe(ialu_reg_shift);
7200 %}
7201
7202 // Shift Right Logical Register
7203 // Only the low 6 bits of src2 are considered for the shift amount, all other bits are ignored.
7204 instruct urShiftL_reg_reg(iRegLNoSp dst, iRegL src1, iRegIorL2I src2) %{
7205 match(Set dst (URShiftL src1 src2));
7206
7207 ins_cost(ALU_COST);
7208 format %{ "srl $dst, $src1, $src2\t#@urShiftL_reg_reg" %}
7209
7210 ins_encode %{
7211 __ srl(as_Register($dst$$reg),
7212 as_Register($src1$$reg),
7213 as_Register($src2$$reg));
7214 %}
7215
7216 ins_pipe(ialu_reg_reg_vshift);
7217 %}
7218
7219 // Shift Right Logical Immediate
7220 instruct urShiftL_reg_imm(iRegLNoSp dst, iRegL src1, immI src2) %{
7221 match(Set dst (URShiftL src1 src2));
7222
7223 ins_cost(ALU_COST);
7224 format %{ "srli $dst, $src1, ($src2 & 0x3f)\t#@urShiftL_reg_imm" %}
7225
7226 ins_encode %{
7227 // the shift amount is encoded in the lower
7228 // 6 bits of the I-immediate field for RV64I
7229 __ srli(as_Register($dst$$reg),
7230 as_Register($src1$$reg),
7231 (unsigned) $src2$$constant & 0x3f);
7232 %}
7233
7234 ins_pipe(ialu_reg_shift);
7235 %}
7236
7237 // A special-case pattern for card table stores.
7238 instruct urShiftP_reg_imm(iRegLNoSp dst, iRegP src1, immI src2) %{
7239 match(Set dst (URShiftL (CastP2X src1) src2));
7240
7241 ins_cost(ALU_COST);
7242 format %{ "srli $dst, p2x($src1), ($src2 & 0x3f)\t#@urShiftP_reg_imm" %}
7243
7244 ins_encode %{
7245 // the shift amount is encoded in the lower
7246 // 6 bits of the I-immediate field for RV64I
7247 __ srli(as_Register($dst$$reg),
7248 as_Register($src1$$reg),
7249 (unsigned) $src2$$constant & 0x3f);
7250 %}
7251
7252 ins_pipe(ialu_reg_shift);
7253 %}
7254
7255 // Shift Right Arithmetic Register
7256 // Only the low 6 bits of src2 are considered for the shift amount, all other bits are ignored.
7257 instruct rShiftL_reg_reg(iRegLNoSp dst, iRegL src1, iRegIorL2I src2) %{
7258 match(Set dst (RShiftL src1 src2));
7259
7260 ins_cost(ALU_COST);
7261 format %{ "sra $dst, $src1, $src2\t#@rShiftL_reg_reg" %}
7262
7263 ins_encode %{
7264 __ sra(as_Register($dst$$reg),
7265 as_Register($src1$$reg),
7266 as_Register($src2$$reg));
7267 %}
7268
7269 ins_pipe(ialu_reg_reg_vshift);
7270 %}
7271
7272 // Shift Right Arithmetic Immediate
7273 instruct rShiftL_reg_imm(iRegLNoSp dst, iRegL src1, immI src2) %{
7274 match(Set dst (RShiftL src1 src2));
7275
7276 ins_cost(ALU_COST);
7277 format %{ "srai $dst, $src1, ($src2 & 0x3f)\t#@rShiftL_reg_imm" %}
7278
7279 ins_encode %{
7280 // the shift amount is encoded in the lower
7281 // 6 bits of the I-immediate field for RV64I
7282 __ srai(as_Register($dst$$reg),
7283 as_Register($src1$$reg),
7284 (unsigned) $src2$$constant & 0x3f);
7285 %}
7286
7287 ins_pipe(ialu_reg_shift);
7288 %}
7289
7290 instruct regI_not_reg(iRegINoSp dst, iRegI src1, immI_M1 m1) %{
7291 match(Set dst (XorI src1 m1));
7292 ins_cost(ALU_COST);
7293 format %{ "xori $dst, $src1, -1\t#@regI_not_reg" %}
7294
7295 ins_encode %{
7296 __ xori(as_Register($dst$$reg), as_Register($src1$$reg), -1);
7297 %}
7298
7299 ins_pipe(ialu_reg_imm);
7300 %}
7301
7302 instruct regL_not_reg(iRegLNoSp dst, iRegL src1, immL_M1 m1) %{
7303 match(Set dst (XorL src1 m1));
7304 ins_cost(ALU_COST);
7305 format %{ "xori $dst, $src1, -1\t#@regL_not_reg" %}
7306
7307 ins_encode %{
7308 __ xori(as_Register($dst$$reg), as_Register($src1$$reg), -1);
7309 %}
7310
7311 ins_pipe(ialu_reg_imm);
7312 %}
7313
7314
7315 // ============================================================================
7316 // Floating Point Arithmetic Instructions
7317
7318 instruct addF_reg_reg(fRegF dst, fRegF src1, fRegF src2) %{
7319 match(Set dst (AddF src1 src2));
7320
7321 ins_cost(DEFAULT_COST * 5);
7322 format %{ "fadd.s $dst, $src1, $src2\t#@addF_reg_reg" %}
7323
7324 ins_encode %{
7325 __ fadd_s(as_FloatRegister($dst$$reg),
7326 as_FloatRegister($src1$$reg),
7327 as_FloatRegister($src2$$reg));
7328 %}
7329
7330 ins_pipe(fp_dop_reg_reg_s);
7331 %}
7332
7333 instruct addD_reg_reg(fRegD dst, fRegD src1, fRegD src2) %{
7334 match(Set dst (AddD src1 src2));
7335
7336 ins_cost(DEFAULT_COST * 5);
7337 format %{ "fadd.d $dst, $src1, $src2\t#@addD_reg_reg" %}
7338
7339 ins_encode %{
7340 __ fadd_d(as_FloatRegister($dst$$reg),
7341 as_FloatRegister($src1$$reg),
7342 as_FloatRegister($src2$$reg));
7343 %}
7344
7345 ins_pipe(fp_dop_reg_reg_d);
7346 %}
7347
7348 instruct subF_reg_reg(fRegF dst, fRegF src1, fRegF src2) %{
7349 match(Set dst (SubF src1 src2));
7350
7351 ins_cost(DEFAULT_COST * 5);
7352 format %{ "fsub.s $dst, $src1, $src2\t#@subF_reg_reg" %}
7353
7354 ins_encode %{
7355 __ fsub_s(as_FloatRegister($dst$$reg),
7356 as_FloatRegister($src1$$reg),
7357 as_FloatRegister($src2$$reg));
7358 %}
7359
7360 ins_pipe(fp_dop_reg_reg_s);
7361 %}
7362
7363 instruct subD_reg_reg(fRegD dst, fRegD src1, fRegD src2) %{
7364 match(Set dst (SubD src1 src2));
7365
7366 ins_cost(DEFAULT_COST * 5);
7367 format %{ "fsub.d $dst, $src1, $src2\t#@subD_reg_reg" %}
7368
7369 ins_encode %{
7370 __ fsub_d(as_FloatRegister($dst$$reg),
7371 as_FloatRegister($src1$$reg),
7372 as_FloatRegister($src2$$reg));
7373 %}
7374
7375 ins_pipe(fp_dop_reg_reg_d);
7376 %}
7377
7378 instruct mulF_reg_reg(fRegF dst, fRegF src1, fRegF src2) %{
7379 match(Set dst (MulF src1 src2));
7380
7381 ins_cost(FMUL_SINGLE_COST);
7382 format %{ "fmul.s $dst, $src1, $src2\t#@mulF_reg_reg" %}
7383
7384 ins_encode %{
7385 __ fmul_s(as_FloatRegister($dst$$reg),
7386 as_FloatRegister($src1$$reg),
7387 as_FloatRegister($src2$$reg));
7388 %}
7389
7390 ins_pipe(fp_dop_reg_reg_s);
7391 %}
7392
7393 instruct mulD_reg_reg(fRegD dst, fRegD src1, fRegD src2) %{
7394 match(Set dst (MulD src1 src2));
7395
7396 ins_cost(FMUL_DOUBLE_COST);
7397 format %{ "fmul.d $dst, $src1, $src2\t#@mulD_reg_reg" %}
7398
7399 ins_encode %{
7400 __ fmul_d(as_FloatRegister($dst$$reg),
7401 as_FloatRegister($src1$$reg),
7402 as_FloatRegister($src2$$reg));
7403 %}
7404
7405 ins_pipe(fp_dop_reg_reg_d);
7406 %}
7407
7408 // src1 * src2 + src3
7409 instruct maddF_reg_reg(fRegF dst, fRegF src1, fRegF src2, fRegF src3) %{
7410 match(Set dst (FmaF src3 (Binary src1 src2)));
7411
7412 ins_cost(FMUL_SINGLE_COST);
7413 format %{ "fmadd.s $dst, $src1, $src2, $src3\t#@maddF_reg_reg" %}
7414
7415 ins_encode %{
7416 assert(UseFMA, "Needs FMA instructions support.");
7417 __ fmadd_s(as_FloatRegister($dst$$reg),
7418 as_FloatRegister($src1$$reg),
7419 as_FloatRegister($src2$$reg),
7420 as_FloatRegister($src3$$reg));
7421 %}
7422
7423 ins_pipe(pipe_class_default);
7424 %}
7425
7426 // src1 * src2 + src3
7427 instruct maddD_reg_reg(fRegD dst, fRegD src1, fRegD src2, fRegD src3) %{
7428 match(Set dst (FmaD src3 (Binary src1 src2)));
7429
7430 ins_cost(FMUL_DOUBLE_COST);
7431 format %{ "fmadd.d $dst, $src1, $src2, $src3\t#@maddD_reg_reg" %}
7432
7433 ins_encode %{
7434 assert(UseFMA, "Needs FMA instructions support.");
7435 __ fmadd_d(as_FloatRegister($dst$$reg),
7436 as_FloatRegister($src1$$reg),
7437 as_FloatRegister($src2$$reg),
7438 as_FloatRegister($src3$$reg));
7439 %}
7440
7441 ins_pipe(pipe_class_default);
7442 %}
7443
7444 // src1 * src2 - src3
7445 instruct msubF_reg_reg(fRegF dst, fRegF src1, fRegF src2, fRegF src3) %{
7446 match(Set dst (FmaF (NegF src3) (Binary src1 src2)));
7447
7448 ins_cost(FMUL_SINGLE_COST);
7449 format %{ "fmsub.s $dst, $src1, $src2, $src3\t#@msubF_reg_reg" %}
7450
7451 ins_encode %{
7452 assert(UseFMA, "Needs FMA instructions support.");
7453 __ fmsub_s(as_FloatRegister($dst$$reg),
7454 as_FloatRegister($src1$$reg),
7455 as_FloatRegister($src2$$reg),
7456 as_FloatRegister($src3$$reg));
7457 %}
7458
7459 ins_pipe(pipe_class_default);
7460 %}
7461
7462 // src1 * src2 - src3
7463 instruct msubD_reg_reg(fRegD dst, fRegD src1, fRegD src2, fRegD src3) %{
7464 match(Set dst (FmaD (NegD src3) (Binary src1 src2)));
7465
7466 ins_cost(FMUL_DOUBLE_COST);
7467 format %{ "fmsub.d $dst, $src1, $src2, $src3\t#@msubD_reg_reg" %}
7468
7469 ins_encode %{
7470 assert(UseFMA, "Needs FMA instructions support.");
7471 __ fmsub_d(as_FloatRegister($dst$$reg),
7472 as_FloatRegister($src1$$reg),
7473 as_FloatRegister($src2$$reg),
7474 as_FloatRegister($src3$$reg));
7475 %}
7476
7477 ins_pipe(pipe_class_default);
7478 %}
7479
7480 // src1 * (-src2) + src3
7481 // "(-src1) * src2 + src3" has been idealized to "src2 * (-src1) + src3"
7482 instruct nmsubF_reg_reg(fRegF dst, fRegF src1, fRegF src2, fRegF src3) %{
7483 match(Set dst (FmaF src3 (Binary src1 (NegF src2))));
7484
7485 ins_cost(FMUL_SINGLE_COST);
7486 format %{ "fnmsub.s $dst, $src1, $src2, $src3\t#@nmsubF_reg_reg" %}
7487
7488 ins_encode %{
7489 assert(UseFMA, "Needs FMA instructions support.");
7490 __ fnmsub_s(as_FloatRegister($dst$$reg),
7491 as_FloatRegister($src1$$reg),
7492 as_FloatRegister($src2$$reg),
7493 as_FloatRegister($src3$$reg));
7494 %}
7495
7496 ins_pipe(pipe_class_default);
7497 %}
7498
7499 // src1 * (-src2) + src3
7500 // "(-src1) * src2 + src3" has been idealized to "src2 * (-src1) + src3"
7501 instruct nmsubD_reg_reg(fRegD dst, fRegD src1, fRegD src2, fRegD src3) %{
7502 match(Set dst (FmaD src3 (Binary src1 (NegD src2))));
7503
7504 ins_cost(FMUL_DOUBLE_COST);
7505 format %{ "fnmsub.d $dst, $src1, $src2, $src3\t#@nmsubD_reg_reg" %}
7506
7507 ins_encode %{
7508 assert(UseFMA, "Needs FMA instructions support.");
7509 __ fnmsub_d(as_FloatRegister($dst$$reg),
7510 as_FloatRegister($src1$$reg),
7511 as_FloatRegister($src2$$reg),
7512 as_FloatRegister($src3$$reg));
7513 %}
7514
7515 ins_pipe(pipe_class_default);
7516 %}
7517
7518 // src1 * (-src2) - src3
7519 // "(-src1) * src2 - src3" has been idealized to "src2 * (-src1) - src3"
7520 instruct nmaddF_reg_reg(fRegF dst, fRegF src1, fRegF src2, fRegF src3) %{
7521 match(Set dst (FmaF (NegF src3) (Binary src1 (NegF src2))));
7522
7523 ins_cost(FMUL_SINGLE_COST);
7524 format %{ "fnmadd.s $dst, $src1, $src2, $src3\t#@nmaddF_reg_reg" %}
7525
7526 ins_encode %{
7527 assert(UseFMA, "Needs FMA instructions support.");
7528 __ fnmadd_s(as_FloatRegister($dst$$reg),
7529 as_FloatRegister($src1$$reg),
7530 as_FloatRegister($src2$$reg),
7531 as_FloatRegister($src3$$reg));
7532 %}
7533
7534 ins_pipe(pipe_class_default);
7535 %}
7536
7537 // src1 * (-src2) - src3
7538 // "(-src1) * src2 - src3" has been idealized to "src2 * (-src1) - src3"
7539 instruct nmaddD_reg_reg(fRegD dst, fRegD src1, fRegD src2, fRegD src3) %{
7540 match(Set dst (FmaD (NegD src3) (Binary src1 (NegD src2))));
7541
7542 ins_cost(FMUL_DOUBLE_COST);
7543 format %{ "fnmadd.d $dst, $src1, $src2, $src3\t#@nmaddD_reg_reg" %}
7544
7545 ins_encode %{
7546 assert(UseFMA, "Needs FMA instructions support.");
7547 __ fnmadd_d(as_FloatRegister($dst$$reg),
7548 as_FloatRegister($src1$$reg),
7549 as_FloatRegister($src2$$reg),
7550 as_FloatRegister($src3$$reg));
7551 %}
7552
7553 ins_pipe(pipe_class_default);
7554 %}
7555
7556 // Math.max(FF)F
7557 instruct maxF_reg_reg(fRegF dst, fRegF src1, fRegF src2, rFlagsReg cr) %{
7558 predicate(!UseZfa);
7559 match(Set dst (MaxF src1 src2));
7560 effect(KILL cr);
7561
7562 format %{ "maxF $dst, $src1, $src2" %}
7563
7564 ins_encode %{
7565 __ minmax_fp(as_FloatRegister($dst$$reg),
7566 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg),
7567 __ FLOAT_TYPE::single_precision, false /* is_min */);
7568 %}
7569
7570 ins_pipe(pipe_class_default);
7571 %}
7572
7573 instruct maxF_reg_reg_zfa(fRegF dst, fRegF src1, fRegF src2) %{
7574 predicate(UseZfa);
7575 match(Set dst (MaxF src1 src2));
7576
7577 format %{ "maxF $dst, $src1, $src2" %}
7578
7579 ins_encode %{
7580 __ fmaxm_s(as_FloatRegister($dst$$reg),
7581 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
7582 %}
7583
7584 ins_pipe(pipe_class_default);
7585 %}
7586
7587 // Math.min(FF)F
7588 instruct minF_reg_reg(fRegF dst, fRegF src1, fRegF src2, rFlagsReg cr) %{
7589 predicate(!UseZfa);
7590 match(Set dst (MinF src1 src2));
7591 effect(KILL cr);
7592
7593 format %{ "minF $dst, $src1, $src2" %}
7594
7595 ins_encode %{
7596 __ minmax_fp(as_FloatRegister($dst$$reg),
7597 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg),
7598 __ FLOAT_TYPE::single_precision, true /* is_min */);
7599 %}
7600
7601 ins_pipe(pipe_class_default);
7602 %}
7603
7604 instruct minF_reg_reg_zfa(fRegF dst, fRegF src1, fRegF src2) %{
7605 predicate(UseZfa);
7606 match(Set dst (MinF src1 src2));
7607
7608 format %{ "minF $dst, $src1, $src2" %}
7609
7610 ins_encode %{
7611 __ fminm_s(as_FloatRegister($dst$$reg),
7612 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
7613 %}
7614
7615 ins_pipe(pipe_class_default);
7616 %}
7617
7618 // Math.max(DD)D
7619 instruct maxD_reg_reg(fRegD dst, fRegD src1, fRegD src2, rFlagsReg cr) %{
7620 predicate(!UseZfa);
7621 match(Set dst (MaxD src1 src2));
7622 effect(KILL cr);
7623
7624 format %{ "maxD $dst, $src1, $src2" %}
7625
7626 ins_encode %{
7627 __ minmax_fp(as_FloatRegister($dst$$reg),
7628 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg),
7629 __ FLOAT_TYPE::double_precision, false /* is_min */);
7630 %}
7631
7632 ins_pipe(pipe_class_default);
7633 %}
7634
7635 instruct maxD_reg_reg_zfa(fRegD dst, fRegD src1, fRegD src2) %{
7636 predicate(UseZfa);
7637 match(Set dst (MaxD src1 src2));
7638
7639 format %{ "maxD $dst, $src1, $src2" %}
7640
7641 ins_encode %{
7642 __ fmaxm_d(as_FloatRegister($dst$$reg),
7643 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
7644 %}
7645
7646 ins_pipe(pipe_class_default);
7647 %}
7648
7649 // Math.min(DD)D
7650 instruct minD_reg_reg(fRegD dst, fRegD src1, fRegD src2, rFlagsReg cr) %{
7651 predicate(!UseZfa);
7652 match(Set dst (MinD src1 src2));
7653 effect(KILL cr);
7654
7655 format %{ "minD $dst, $src1, $src2" %}
7656
7657 ins_encode %{
7658 __ minmax_fp(as_FloatRegister($dst$$reg),
7659 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg),
7660 __ FLOAT_TYPE::double_precision, true /* is_min */);
7661 %}
7662
7663 ins_pipe(pipe_class_default);
7664 %}
7665
7666 instruct minD_reg_reg_zfa(fRegD dst, fRegD src1, fRegD src2) %{
7667 predicate(UseZfa);
7668 match(Set dst (MinD src1 src2));
7669
7670 format %{ "minD $dst, $src1, $src2" %}
7671
7672 ins_encode %{
7673 __ fminm_d(as_FloatRegister($dst$$reg),
7674 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
7675 %}
7676
7677 ins_pipe(pipe_class_default);
7678 %}
7679
7680 // Float.isInfinite
7681 instruct isInfiniteF_reg_reg(iRegINoSp dst, fRegF src)
7682 %{
7683 match(Set dst (IsInfiniteF src));
7684
7685 format %{ "isInfinite $dst, $src" %}
7686 ins_encode %{
7687 __ fclass_s(as_Register($dst$$reg), as_FloatRegister($src$$reg));
7688 __ andi(as_Register($dst$$reg), as_Register($dst$$reg), Assembler::FClassBits::inf);
7689 __ slt(as_Register($dst$$reg), zr, as_Register($dst$$reg));
7690 %}
7691
7692 ins_pipe(pipe_class_default);
7693 %}
7694
7695 // Double.isInfinite
7696 instruct isInfiniteD_reg_reg(iRegINoSp dst, fRegD src)
7697 %{
7698 match(Set dst (IsInfiniteD src));
7699
7700 format %{ "isInfinite $dst, $src" %}
7701 ins_encode %{
7702 __ fclass_d(as_Register($dst$$reg), as_FloatRegister($src$$reg));
7703 __ andi(as_Register($dst$$reg), as_Register($dst$$reg), Assembler::FClassBits::inf);
7704 __ slt(as_Register($dst$$reg), zr, as_Register($dst$$reg));
7705 %}
7706
7707 ins_pipe(pipe_class_default);
7708 %}
7709
7710 // Float.isFinite
7711 instruct isFiniteF_reg_reg(iRegINoSp dst, fRegF src)
7712 %{
7713 match(Set dst (IsFiniteF src));
7714
7715 format %{ "isFinite $dst, $src" %}
7716 ins_encode %{
7717 __ fclass_s(as_Register($dst$$reg), as_FloatRegister($src$$reg));
7718 __ andi(as_Register($dst$$reg), as_Register($dst$$reg), Assembler::FClassBits::finite);
7719 __ slt(as_Register($dst$$reg), zr, as_Register($dst$$reg));
7720 %}
7721
7722 ins_pipe(pipe_class_default);
7723 %}
7724
7725 // Double.isFinite
7726 instruct isFiniteD_reg_reg(iRegINoSp dst, fRegD src)
7727 %{
7728 match(Set dst (IsFiniteD src));
7729
7730 format %{ "isFinite $dst, $src" %}
7731 ins_encode %{
7732 __ fclass_d(as_Register($dst$$reg), as_FloatRegister($src$$reg));
7733 __ andi(as_Register($dst$$reg), as_Register($dst$$reg), Assembler::FClassBits::finite);
7734 __ slt(as_Register($dst$$reg), zr, as_Register($dst$$reg));
7735 %}
7736
7737 ins_pipe(pipe_class_default);
7738 %}
7739
7740 instruct divF_reg_reg(fRegF dst, fRegF src1, fRegF src2) %{
7741 match(Set dst (DivF src1 src2));
7742
7743 ins_cost(FDIV_COST);
7744 format %{ "fdiv.s $dst, $src1, $src2\t#@divF_reg_reg" %}
7745
7746 ins_encode %{
7747 __ fdiv_s(as_FloatRegister($dst$$reg),
7748 as_FloatRegister($src1$$reg),
7749 as_FloatRegister($src2$$reg));
7750 %}
7751
7752 ins_pipe(fp_div_s);
7753 %}
7754
7755 instruct divD_reg_reg(fRegD dst, fRegD src1, fRegD src2) %{
7756 match(Set dst (DivD src1 src2));
7757
7758 ins_cost(FDIV_COST);
7759 format %{ "fdiv.d $dst, $src1, $src2\t#@divD_reg_reg" %}
7760
7761 ins_encode %{
7762 __ fdiv_d(as_FloatRegister($dst$$reg),
7763 as_FloatRegister($src1$$reg),
7764 as_FloatRegister($src2$$reg));
7765 %}
7766
7767 ins_pipe(fp_div_d);
7768 %}
7769
7770 instruct negF_reg_reg(fRegF dst, fRegF src) %{
7771 match(Set dst (NegF src));
7772
7773 ins_cost(XFER_COST);
7774 format %{ "fsgnjn.s $dst, $src, $src\t#@negF_reg_reg" %}
7775
7776 ins_encode %{
7777 __ fneg_s(as_FloatRegister($dst$$reg),
7778 as_FloatRegister($src$$reg));
7779 %}
7780
7781 ins_pipe(fp_uop_s);
7782 %}
7783
7784 instruct negD_reg_reg(fRegD dst, fRegD src) %{
7785 match(Set dst (NegD src));
7786
7787 ins_cost(XFER_COST);
7788 format %{ "fsgnjn.d $dst, $src, $src\t#@negD_reg_reg" %}
7789
7790 ins_encode %{
7791 __ fneg_d(as_FloatRegister($dst$$reg),
7792 as_FloatRegister($src$$reg));
7793 %}
7794
7795 ins_pipe(fp_uop_d);
7796 %}
7797
7798 instruct absI_reg(iRegINoSp dst, iRegIorL2I src) %{
7799 match(Set dst (AbsI src));
7800
7801 ins_cost(ALU_COST * 3);
7802 format %{
7803 "sraiw t0, $src, 0x1f\n\t"
7804 "addw $dst, $src, t0\n\t"
7805 "xorr $dst, $dst, t0\t#@absI_reg"
7806 %}
7807
7808 ins_encode %{
7809 __ sraiw(t0, as_Register($src$$reg), 0x1f);
7810 __ addw(as_Register($dst$$reg), as_Register($src$$reg), t0);
7811 __ xorr(as_Register($dst$$reg), as_Register($dst$$reg), t0);
7812 %}
7813
7814 ins_pipe(pipe_class_default);
7815 %}
7816
7817 instruct absL_reg(iRegLNoSp dst, iRegL src) %{
7818 match(Set dst (AbsL src));
7819
7820 ins_cost(ALU_COST * 3);
7821 format %{
7822 "srai t0, $src, 0x3f\n\t"
7823 "add $dst, $src, t0\n\t"
7824 "xorr $dst, $dst, t0\t#@absL_reg"
7825 %}
7826
7827 ins_encode %{
7828 __ srai(t0, as_Register($src$$reg), 0x3f);
7829 __ add(as_Register($dst$$reg), as_Register($src$$reg), t0);
7830 __ xorr(as_Register($dst$$reg), as_Register($dst$$reg), t0);
7831 %}
7832
7833 ins_pipe(pipe_class_default);
7834 %}
7835
7836 instruct absF_reg(fRegF dst, fRegF src) %{
7837 match(Set dst (AbsF src));
7838
7839 ins_cost(XFER_COST);
7840 format %{ "fsgnjx.s $dst, $src, $src\t#@absF_reg" %}
7841 ins_encode %{
7842 __ fabs_s(as_FloatRegister($dst$$reg),
7843 as_FloatRegister($src$$reg));
7844 %}
7845
7846 ins_pipe(fp_uop_s);
7847 %}
7848
7849 instruct absD_reg(fRegD dst, fRegD src) %{
7850 match(Set dst (AbsD src));
7851
7852 ins_cost(XFER_COST);
7853 format %{ "fsgnjx.d $dst, $src, $src\t#@absD_reg" %}
7854 ins_encode %{
7855 __ fabs_d(as_FloatRegister($dst$$reg),
7856 as_FloatRegister($src$$reg));
7857 %}
7858
7859 ins_pipe(fp_uop_d);
7860 %}
7861
7862 instruct sqrtF_reg(fRegF dst, fRegF src) %{
7863 match(Set dst (SqrtF src));
7864
7865 ins_cost(FSQRT_COST);
7866 format %{ "fsqrt.s $dst, $src\t#@sqrtF_reg" %}
7867 ins_encode %{
7868 __ fsqrt_s(as_FloatRegister($dst$$reg),
7869 as_FloatRegister($src$$reg));
7870 %}
7871
7872 ins_pipe(fp_sqrt_s);
7873 %}
7874
7875 instruct sqrtD_reg(fRegD dst, fRegD src) %{
7876 match(Set dst (SqrtD src));
7877
7878 ins_cost(FSQRT_COST);
7879 format %{ "fsqrt.d $dst, $src\t#@sqrtD_reg" %}
7880 ins_encode %{
7881 __ fsqrt_d(as_FloatRegister($dst$$reg),
7882 as_FloatRegister($src$$reg));
7883 %}
7884
7885 ins_pipe(fp_sqrt_d);
7886 %}
7887
7888 // Round Instruction
7889 instruct roundD_reg(fRegD dst, fRegD src, immI rmode, iRegLNoSp tmp1, iRegLNoSp tmp2, iRegLNoSp tmp3) %{
7890 match(Set dst (RoundDoubleMode src rmode));
7891 ins_cost(2 * XFER_COST + BRANCH_COST);
7892 effect(TEMP_DEF dst, TEMP tmp1, TEMP tmp2, TEMP tmp3);
7893
7894 format %{ "RoundDoubleMode $src, $rmode" %}
7895 ins_encode %{
7896 __ round_double_mode(as_FloatRegister($dst$$reg),
7897 as_FloatRegister($src$$reg), $rmode$$constant, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
7898 %}
7899 ins_pipe(pipe_class_default);
7900 %}
7901
7902 // Copysign and signum intrinsics
7903
7904 instruct copySignD_reg(fRegD dst, fRegD src1, fRegD src2, immD zero) %{
7905 match(Set dst (CopySignD src1 (Binary src2 zero)));
7906 format %{ "CopySignD $dst $src1 $src2" %}
7907 ins_encode %{
7908 FloatRegister dst = as_FloatRegister($dst$$reg),
7909 src1 = as_FloatRegister($src1$$reg),
7910 src2 = as_FloatRegister($src2$$reg);
7911 __ fsgnj_d(dst, src1, src2);
7912 %}
7913 ins_pipe(fp_dop_reg_reg_d);
7914 %}
7915
7916 instruct copySignF_reg(fRegF dst, fRegF src1, fRegF src2) %{
7917 match(Set dst (CopySignF src1 src2));
7918 format %{ "CopySignF $dst $src1 $src2" %}
7919 ins_encode %{
7920 FloatRegister dst = as_FloatRegister($dst$$reg),
7921 src1 = as_FloatRegister($src1$$reg),
7922 src2 = as_FloatRegister($src2$$reg);
7923 __ fsgnj_s(dst, src1, src2);
7924 %}
7925 ins_pipe(fp_dop_reg_reg_s);
7926 %}
7927
7928 instruct signumD_reg(fRegD dst, immD zero, fRegD one) %{
7929 match(Set dst (SignumD dst (Binary zero one)));
7930 format %{ "signumD $dst, $dst" %}
7931 ins_encode %{
7932 __ signum_fp(as_FloatRegister($dst$$reg), as_FloatRegister($one$$reg), true /* is_double */);
7933 %}
7934 ins_pipe(pipe_class_default);
7935 %}
7936
7937 instruct signumF_reg(fRegF dst, immF zero, fRegF one) %{
7938 match(Set dst (SignumF dst (Binary zero one)));
7939 format %{ "signumF $dst, $dst" %}
7940 ins_encode %{
7941 __ signum_fp(as_FloatRegister($dst$$reg), as_FloatRegister($one$$reg), false /* is_double */);
7942 %}
7943 ins_pipe(pipe_class_default);
7944 %}
7945
7946 // Arithmetic Instructions End
7947
7948 // ============================================================================
7949 // Logical Instructions
7950
7951 // Register And
7952 instruct andI_reg_reg(iRegINoSp dst, iRegI src1, iRegI src2) %{
7953 match(Set dst (AndI src1 src2));
7954
7955 format %{ "andr $dst, $src1, $src2\t#@andI_reg_reg" %}
7956
7957 ins_cost(ALU_COST);
7958 ins_encode %{
7959 __ andr(as_Register($dst$$reg),
7960 as_Register($src1$$reg),
7961 as_Register($src2$$reg));
7962 %}
7963
7964 ins_pipe(ialu_reg_reg);
7965 %}
7966
7967 // Immediate And
7968 instruct andI_reg_imm(iRegINoSp dst, iRegI src1, immIAdd src2) %{
7969 match(Set dst (AndI src1 src2));
7970
7971 format %{ "andi $dst, $src1, $src2\t#@andI_reg_imm" %}
7972
7973 ins_cost(ALU_COST);
7974 ins_encode %{
7975 __ andi(as_Register($dst$$reg),
7976 as_Register($src1$$reg),
7977 (int32_t)($src2$$constant));
7978 %}
7979
7980 ins_pipe(ialu_reg_imm);
7981 %}
7982
7983 // Register Or
7984 instruct orI_reg_reg(iRegINoSp dst, iRegI src1, iRegI src2) %{
7985 match(Set dst (OrI src1 src2));
7986
7987 format %{ "orr $dst, $src1, $src2\t#@orI_reg_reg" %}
7988
7989 ins_cost(ALU_COST);
7990 ins_encode %{
7991 __ orr(as_Register($dst$$reg),
7992 as_Register($src1$$reg),
7993 as_Register($src2$$reg));
7994 %}
7995
7996 ins_pipe(ialu_reg_reg);
7997 %}
7998
7999 // Immediate Or
8000 instruct orI_reg_imm(iRegINoSp dst, iRegI src1, immIAdd src2) %{
8001 match(Set dst (OrI src1 src2));
8002
8003 format %{ "ori $dst, $src1, $src2\t#@orI_reg_imm" %}
8004
8005 ins_cost(ALU_COST);
8006 ins_encode %{
8007 __ ori(as_Register($dst$$reg),
8008 as_Register($src1$$reg),
8009 (int32_t)($src2$$constant));
8010 %}
8011
8012 ins_pipe(ialu_reg_imm);
8013 %}
8014
8015 // Register Xor
8016 instruct xorI_reg_reg(iRegINoSp dst, iRegI src1, iRegI src2) %{
8017 match(Set dst (XorI src1 src2));
8018
8019 format %{ "xorr $dst, $src1, $src2\t#@xorI_reg_reg" %}
8020
8021 ins_cost(ALU_COST);
8022 ins_encode %{
8023 __ xorr(as_Register($dst$$reg),
8024 as_Register($src1$$reg),
8025 as_Register($src2$$reg));
8026 %}
8027
8028 ins_pipe(ialu_reg_reg);
8029 %}
8030
8031 // Immediate Xor
8032 instruct xorI_reg_imm(iRegINoSp dst, iRegI src1, immIAdd src2) %{
8033 match(Set dst (XorI src1 src2));
8034
8035 format %{ "xori $dst, $src1, $src2\t#@xorI_reg_imm" %}
8036
8037 ins_cost(ALU_COST);
8038 ins_encode %{
8039 __ xori(as_Register($dst$$reg),
8040 as_Register($src1$$reg),
8041 (int32_t)($src2$$constant));
8042 %}
8043
8044 ins_pipe(ialu_reg_imm);
8045 %}
8046
8047 // Register And Long
8048 instruct andL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
8049 match(Set dst (AndL src1 src2));
8050
8051 format %{ "andr $dst, $src1, $src2\t#@andL_reg_reg" %}
8052
8053 ins_cost(ALU_COST);
8054 ins_encode %{
8055 __ andr(as_Register($dst$$reg),
8056 as_Register($src1$$reg),
8057 as_Register($src2$$reg));
8058 %}
8059
8060 ins_pipe(ialu_reg_reg);
8061 %}
8062
8063 // Immediate And Long
8064 instruct andL_reg_imm(iRegLNoSp dst, iRegL src1, immLAdd src2) %{
8065 match(Set dst (AndL src1 src2));
8066
8067 format %{ "andi $dst, $src1, $src2\t#@andL_reg_imm" %}
8068
8069 ins_cost(ALU_COST);
8070 ins_encode %{
8071 __ andi(as_Register($dst$$reg),
8072 as_Register($src1$$reg),
8073 (int32_t)($src2$$constant));
8074 %}
8075
8076 ins_pipe(ialu_reg_imm);
8077 %}
8078
8079 // Register Or Long
8080 instruct orL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
8081 match(Set dst (OrL src1 src2));
8082
8083 format %{ "orr $dst, $src1, $src2\t#@orL_reg_reg" %}
8084
8085 ins_cost(ALU_COST);
8086 ins_encode %{
8087 __ orr(as_Register($dst$$reg),
8088 as_Register($src1$$reg),
8089 as_Register($src2$$reg));
8090 %}
8091
8092 ins_pipe(ialu_reg_reg);
8093 %}
8094
8095 // Immediate Or Long
8096 instruct orL_reg_imm(iRegLNoSp dst, iRegL src1, immLAdd src2) %{
8097 match(Set dst (OrL src1 src2));
8098
8099 format %{ "ori $dst, $src1, $src2\t#@orL_reg_imm" %}
8100
8101 ins_cost(ALU_COST);
8102 ins_encode %{
8103 __ ori(as_Register($dst$$reg),
8104 as_Register($src1$$reg),
8105 (int32_t)($src2$$constant));
8106 %}
8107
8108 ins_pipe(ialu_reg_imm);
8109 %}
8110
8111 // Register Xor Long
8112 instruct xorL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
8113 match(Set dst (XorL src1 src2));
8114
8115 format %{ "xorr $dst, $src1, $src2\t#@xorL_reg_reg" %}
8116
8117 ins_cost(ALU_COST);
8118 ins_encode %{
8119 __ xorr(as_Register($dst$$reg),
8120 as_Register($src1$$reg),
8121 as_Register($src2$$reg));
8122 %}
8123
8124 ins_pipe(ialu_reg_reg);
8125 %}
8126
8127 // Immediate Xor Long
8128 instruct xorL_reg_imm(iRegLNoSp dst, iRegL src1, immLAdd src2) %{
8129 match(Set dst (XorL src1 src2));
8130
8131 ins_cost(ALU_COST);
8132 format %{ "xori $dst, $src1, $src2\t#@xorL_reg_imm" %}
8133
8134 ins_encode %{
8135 __ xori(as_Register($dst$$reg),
8136 as_Register($src1$$reg),
8137 (int32_t)($src2$$constant));
8138 %}
8139
8140 ins_pipe(ialu_reg_imm);
8141 %}
8142
8143 // ============================================================================
8144 // MemBar Instruction
8145
8146 // RVTSO
8147
8148 instruct unnecessary_membar_rvtso() %{
8149 predicate(UseZtso);
8150 match(LoadFence);
8151 match(StoreFence);
8152 match(StoreStoreFence);
8153 match(MemBarAcquire);
8154 match(MemBarRelease);
8155 match(MemBarStoreStore);
8156 match(MemBarAcquireLock);
8157 match(MemBarReleaseLock);
8158
8159 ins_cost(0);
8160
8161 size(0);
8162
8163 format %{ "#@unnecessary_membar_rvtso elided/tso (empty encoding)" %}
8164 ins_encode %{
8165 __ block_comment("unnecessary_membar_rvtso");
8166 %}
8167 ins_pipe(real_empty);
8168 %}
8169
8170 instruct membar_volatile_rvtso() %{
8171 predicate(UseZtso);
8172 match(MemBarVolatile);
8173 ins_cost(VOLATILE_REF_COST);
8174
8175 format %{ "#@membar_volatile_rvtso\n\t"
8176 "fence w, r"%}
8177
8178 ins_encode %{
8179 __ block_comment("membar_volatile_rvtso");
8180 __ membar(MacroAssembler::StoreLoad);
8181 %}
8182
8183 ins_pipe(pipe_slow);
8184 %}
8185
8186 instruct unnecessary_membar_volatile_rvtso() %{
8187 predicate(UseZtso && Matcher::post_store_load_barrier(n));
8188 match(MemBarVolatile);
8189 ins_cost(0);
8190
8191 size(0);
8192
8193 format %{ "#@unnecessary_membar_volatile_rvtso (unnecessary so empty encoding)" %}
8194 ins_encode %{
8195 __ block_comment("unnecessary_membar_volatile_rvtso");
8196 %}
8197 ins_pipe(real_empty);
8198 %}
8199
8200 // RVWMO
8201
8202 instruct membar_aqcuire_rvwmo() %{
8203 predicate(!UseZtso);
8204 match(LoadFence);
8205 match(MemBarAcquire);
8206 ins_cost(VOLATILE_REF_COST);
8207
8208 format %{ "#@membar_aqcuire_rvwmo\n\t"
8209 "fence r, rw" %}
8210
8211 ins_encode %{
8212 __ block_comment("membar_aqcuire_rvwmo");
8213 __ membar(MacroAssembler::LoadLoad | MacroAssembler::LoadStore);
8214 %}
8215 ins_pipe(pipe_serial);
8216 %}
8217
8218 instruct membar_release_rvwmo() %{
8219 predicate(!UseZtso);
8220 match(StoreFence);
8221 match(MemBarRelease);
8222 ins_cost(VOLATILE_REF_COST);
8223
8224 format %{ "#@membar_release_rvwmo\n\t"
8225 "fence rw, w" %}
8226
8227 ins_encode %{
8228 __ block_comment("membar_release_rvwmo");
8229 __ membar(MacroAssembler::LoadStore | MacroAssembler::StoreStore);
8230 %}
8231 ins_pipe(pipe_serial);
8232 %}
8233
8234 instruct membar_storestore_rvwmo() %{
8235 predicate(!UseZtso);
8236 match(MemBarStoreStore);
8237 match(StoreStoreFence);
8238 ins_cost(VOLATILE_REF_COST);
8239
8240 format %{ "#@membar_storestore_rvwmo\n\t"
8241 "fence w, w" %}
8242
8243 ins_encode %{
8244 __ membar(MacroAssembler::StoreStore);
8245 %}
8246 ins_pipe(pipe_serial);
8247 %}
8248
8249 instruct membar_volatile_rvwmo() %{
8250 predicate(!UseZtso);
8251 match(MemBarVolatile);
8252 ins_cost(VOLATILE_REF_COST);
8253
8254 format %{ "#@membar_volatile_rvwmo\n\t"
8255 "fence w, r"%}
8256
8257 ins_encode %{
8258 __ block_comment("membar_volatile_rvwmo");
8259 __ membar(MacroAssembler::StoreLoad);
8260 %}
8261
8262 ins_pipe(pipe_serial);
8263 %}
8264
8265 instruct membar_lock_rvwmo() %{
8266 predicate(!UseZtso);
8267 match(MemBarAcquireLock);
8268 match(MemBarReleaseLock);
8269 ins_cost(0);
8270
8271 format %{ "#@membar_lock_rvwmo (elided)" %}
8272
8273 ins_encode %{
8274 __ block_comment("membar_lock_rvwmo (elided)");
8275 %}
8276
8277 ins_pipe(pipe_serial);
8278 %}
8279
8280 instruct unnecessary_membar_volatile_rvwmo() %{
8281 predicate(!UseZtso && Matcher::post_store_load_barrier(n));
8282 match(MemBarVolatile);
8283 ins_cost(0);
8284
8285 size(0);
8286 format %{ "#@unnecessary_membar_volatile_rvwmo (unnecessary so empty encoding)" %}
8287 ins_encode %{
8288 __ block_comment("unnecessary_membar_volatile_rvwmo");
8289 %}
8290 ins_pipe(real_empty);
8291 %}
8292
8293 instruct spin_wait() %{
8294 predicate(UseZihintpause);
8295 match(OnSpinWait);
8296 ins_cost(CACHE_MISS_COST);
8297
8298 format %{ "spin_wait" %}
8299
8300 ins_encode %{
8301 __ pause();
8302 %}
8303
8304 ins_pipe(pipe_serial);
8305 %}
8306
8307 // ============================================================================
8308 // Cast Instructions (Java-level type cast)
8309
8310 instruct castX2P(iRegPNoSp dst, iRegL src) %{
8311 match(Set dst (CastX2P src));
8312
8313 ins_cost(ALU_COST);
8314 format %{ "mv $dst, $src\t# long -> ptr, #@castX2P" %}
8315
8316 ins_encode %{
8317 if ($dst$$reg != $src$$reg) {
8318 __ mv(as_Register($dst$$reg), as_Register($src$$reg));
8319 }
8320 %}
8321
8322 ins_pipe(ialu_reg);
8323 %}
8324
8325 instruct castP2X(iRegLNoSp dst, iRegP src) %{
8326 match(Set dst (CastP2X src));
8327
8328 ins_cost(ALU_COST);
8329 format %{ "mv $dst, $src\t# ptr -> long, #@castP2X" %}
8330
8331 ins_encode %{
8332 if ($dst$$reg != $src$$reg) {
8333 __ mv(as_Register($dst$$reg), as_Register($src$$reg));
8334 }
8335 %}
8336
8337 ins_pipe(ialu_reg);
8338 %}
8339
8340 instruct castPP(iRegPNoSp dst)
8341 %{
8342 match(Set dst (CastPP dst));
8343 ins_cost(0);
8344
8345 size(0);
8346 format %{ "# castPP of $dst, #@castPP" %}
8347 ins_encode(/* empty encoding */);
8348 ins_pipe(pipe_class_empty);
8349 %}
8350
8351 instruct castLL(iRegL dst)
8352 %{
8353 match(Set dst (CastLL dst));
8354
8355 size(0);
8356 format %{ "# castLL of $dst, #@castLL" %}
8357 ins_encode(/* empty encoding */);
8358 ins_cost(0);
8359 ins_pipe(pipe_class_empty);
8360 %}
8361
8362 instruct castII(iRegI dst)
8363 %{
8364 match(Set dst (CastII dst));
8365
8366 size(0);
8367 format %{ "# castII of $dst, #@castII" %}
8368 ins_encode(/* empty encoding */);
8369 ins_cost(0);
8370 ins_pipe(pipe_class_empty);
8371 %}
8372
8373 instruct checkCastPP(iRegPNoSp dst)
8374 %{
8375 match(Set dst (CheckCastPP dst));
8376
8377 size(0);
8378 ins_cost(0);
8379 format %{ "# checkcastPP of $dst, #@checkCastPP" %}
8380 ins_encode(/* empty encoding */);
8381 ins_pipe(pipe_class_empty);
8382 %}
8383
8384 instruct castHH(fRegF dst)
8385 %{
8386 match(Set dst (CastHH dst));
8387
8388 size(0);
8389 format %{ "# castHH of $dst" %}
8390 ins_encode(/* empty encoding */);
8391 ins_cost(0);
8392 ins_pipe(pipe_class_empty);
8393 %}
8394
8395 instruct castFF(fRegF dst)
8396 %{
8397 match(Set dst (CastFF dst));
8398
8399 size(0);
8400 format %{ "# castFF of $dst" %}
8401 ins_encode(/* empty encoding */);
8402 ins_cost(0);
8403 ins_pipe(pipe_class_empty);
8404 %}
8405
8406 instruct castDD(fRegD dst)
8407 %{
8408 match(Set dst (CastDD dst));
8409
8410 size(0);
8411 format %{ "# castDD of $dst" %}
8412 ins_encode(/* empty encoding */);
8413 ins_cost(0);
8414 ins_pipe(pipe_class_empty);
8415 %}
8416
8417 instruct castVV(vReg dst)
8418 %{
8419 match(Set dst (CastVV dst));
8420
8421 size(0);
8422 format %{ "# castVV of $dst" %}
8423 ins_encode(/* empty encoding */);
8424 ins_cost(0);
8425 ins_pipe(pipe_class_empty);
8426 %}
8427
8428 instruct castVVMask(vRegMask dst)
8429 %{
8430 match(Set dst (CastVV dst));
8431
8432 size(0);
8433 format %{ "# castVV of $dst" %}
8434 ins_encode(/* empty encoding */);
8435 ins_cost(0);
8436 ins_pipe(pipe_class_empty);
8437 %}
8438
8439 // ============================================================================
8440 // Convert Instructions
8441
8442 // int to bool
8443 instruct convI2Bool(iRegINoSp dst, iRegI src)
8444 %{
8445 match(Set dst (Conv2B src));
8446
8447 ins_cost(ALU_COST);
8448 format %{ "snez $dst, $src\t#@convI2Bool" %}
8449
8450 ins_encode %{
8451 __ snez(as_Register($dst$$reg), as_Register($src$$reg));
8452 %}
8453
8454 ins_pipe(ialu_reg);
8455 %}
8456
8457 // pointer to bool
8458 instruct convP2Bool(iRegINoSp dst, iRegP src)
8459 %{
8460 match(Set dst (Conv2B src));
8461
8462 ins_cost(ALU_COST);
8463 format %{ "snez $dst, $src\t#@convP2Bool" %}
8464
8465 ins_encode %{
8466 __ snez(as_Register($dst$$reg), as_Register($src$$reg));
8467 %}
8468
8469 ins_pipe(ialu_reg);
8470 %}
8471
8472 // int <-> long
8473
8474 instruct convI2L_reg_reg(iRegLNoSp dst, iRegIorL2I src)
8475 %{
8476 match(Set dst (ConvI2L src));
8477
8478 ins_cost(ALU_COST);
8479 format %{ "addw $dst, $src, zr\t#@convI2L_reg_reg" %}
8480 ins_encode %{
8481 __ sext(as_Register($dst$$reg), as_Register($src$$reg), 32);
8482 %}
8483 ins_pipe(ialu_reg);
8484 %}
8485
8486 instruct convL2I_reg(iRegINoSp dst, iRegL src) %{
8487 match(Set dst (ConvL2I src));
8488
8489 ins_cost(ALU_COST);
8490 format %{ "addw $dst, $src, zr\t#@convL2I_reg" %}
8491
8492 ins_encode %{
8493 __ sext(as_Register($dst$$reg), as_Register($src$$reg), 32);
8494 %}
8495
8496 ins_pipe(ialu_reg);
8497 %}
8498
8499 // int to unsigned long (Zero-extend)
8500 instruct convI2UL_reg_reg(iRegLNoSp dst, iRegIorL2I src, immL_32bits mask)
8501 %{
8502 match(Set dst (AndL (ConvI2L src) mask));
8503
8504 ins_cost(ALU_COST * 2);
8505 format %{ "zext $dst, $src, 32\t# i2ul, #@convI2UL_reg_reg" %}
8506
8507 ins_encode %{
8508 __ zext(as_Register($dst$$reg), as_Register($src$$reg), 32);
8509 %}
8510
8511 ins_pipe(ialu_reg_shift);
8512 %}
8513
8514 // float <-> double
8515
8516 instruct convF2D_reg(fRegD dst, fRegF src) %{
8517 match(Set dst (ConvF2D src));
8518
8519 ins_cost(XFER_COST);
8520 format %{ "fcvt.d.s $dst, $src\t#@convF2D_reg" %}
8521
8522 ins_encode %{
8523 __ fcvt_d_s(as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg));
8524 %}
8525
8526 ins_pipe(fp_f2d);
8527 %}
8528
8529 instruct convD2F_reg(fRegF dst, fRegD src) %{
8530 match(Set dst (ConvD2F src));
8531
8532 ins_cost(XFER_COST);
8533 format %{ "fcvt.s.d $dst, $src\t#@convD2F_reg" %}
8534
8535 ins_encode %{
8536 __ fcvt_s_d(as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg));
8537 %}
8538
8539 ins_pipe(fp_d2f);
8540 %}
8541
8542 // single <-> half precision
8543
8544 instruct convHF2F_reg_reg(fRegF dst, iRegINoSp src, iRegINoSp tmp) %{
8545 match(Set dst (ConvHF2F src));
8546 effect(TEMP tmp);
8547 format %{ "fmv.h.x $dst, $src\t# move source from $src to $dst\n\t"
8548 "fcvt.s.h $dst, $dst\t# convert half to single precision"
8549 %}
8550 ins_encode %{
8551 __ float16_to_float($dst$$FloatRegister, $src$$Register, $tmp$$Register);
8552 %}
8553 ins_pipe(pipe_slow);
8554 %}
8555
8556 instruct convF2HF_reg_reg(iRegINoSp dst, fRegF src, fRegF ftmp, iRegINoSp xtmp) %{
8557 match(Set dst (ConvF2HF src));
8558 effect(TEMP_DEF dst, TEMP ftmp, TEMP xtmp);
8559 format %{ "fcvt.h.s $ftmp, $src\t# convert single precision to half\n\t"
8560 "fmv.x.h $dst, $ftmp\t# move result from $ftmp to $dst"
8561 %}
8562 ins_encode %{
8563 __ float_to_float16($dst$$Register, $src$$FloatRegister, $ftmp$$FloatRegister, $xtmp$$Register);
8564 %}
8565 ins_pipe(pipe_slow);
8566 %}
8567
8568 // half precision operations
8569
8570 instruct reinterpretS2HF(fRegF dst, iRegI src)
8571 %{
8572 match(Set dst (ReinterpretS2HF src));
8573 format %{ "fmv.h.x $dst, $src\t# reinterpretS2HF" %}
8574 ins_encode %{
8575 __ fmv_h_x($dst$$FloatRegister, $src$$Register);
8576 %}
8577 ins_pipe(fp_i2f);
8578 %}
8579
8580 instruct convF2HFAndS2HF(fRegF dst, fRegF src)
8581 %{
8582 match(Set dst (ReinterpretS2HF (ConvF2HF src)));
8583 format %{ "convF2HFAndS2HF $dst, $src" %}
8584 ins_encode %{
8585 __ fcvt_h_s($dst$$FloatRegister, $src$$FloatRegister);
8586 %}
8587 ins_pipe(fp_uop_s);
8588 %}
8589
8590 instruct reinterpretHF2S(iRegINoSp dst, fRegF src)
8591 %{
8592 match(Set dst (ReinterpretHF2S src));
8593 format %{ "fmv.x.h $dst, $src\t# reinterpretHF2S" %}
8594 ins_encode %{
8595 __ fmv_x_h($dst$$Register, $src$$FloatRegister);
8596 %}
8597 ins_pipe(fp_f2i);
8598 %}
8599
8600 instruct convHF2SAndHF2F(fRegF dst, fRegF src)
8601 %{
8602 match(Set dst (ConvHF2F (ReinterpretHF2S src)));
8603 format %{ "convHF2SAndHF2F $dst, $src" %}
8604 ins_encode %{
8605 __ fcvt_s_h($dst$$FloatRegister, $src$$FloatRegister);
8606 %}
8607 ins_pipe(fp_uop_s);
8608 %}
8609
8610 instruct sqrt_HF_reg(fRegF dst, fRegF src)
8611 %{
8612 match(Set dst (SqrtHF src));
8613 format %{ "fsqrt.h $dst, $src" %}
8614 ins_encode %{
8615 __ fsqrt_h($dst$$FloatRegister, $src$$FloatRegister);
8616 %}
8617 ins_pipe(fp_sqrt_s);
8618 %}
8619
8620 instruct binOps_HF_reg(fRegF dst, fRegF src1, fRegF src2)
8621 %{
8622 match(Set dst (AddHF src1 src2));
8623 match(Set dst (SubHF src1 src2));
8624 match(Set dst (MulHF src1 src2));
8625 match(Set dst (DivHF src1 src2));
8626 format %{ "binop_hf $dst, $src1, $src2" %}
8627 ins_encode %{
8628 int opcode = this->ideal_Opcode();
8629 switch(opcode) {
8630 case Op_AddHF: __ fadd_h($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); break;
8631 case Op_SubHF: __ fsub_h($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); break;
8632 case Op_MulHF: __ fmul_h($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); break;
8633 case Op_DivHF: __ fdiv_h($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); break;
8634 default: assert(false, "%s is not supported here", NodeClassNames[opcode]); break;
8635 }
8636 %}
8637 ins_pipe(fp_dop_reg_reg_s);
8638 %}
8639
8640 instruct min_HF_reg(fRegF dst, fRegF src1, fRegF src2, rFlagsReg cr)
8641 %{
8642 predicate(!UseZfa);
8643 match(Set dst (MinHF src1 src2));
8644 effect(KILL cr);
8645
8646 format %{ "min_hf $dst, $src1, $src2" %}
8647
8648 ins_encode %{
8649 __ minmax_fp($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister,
8650 __ FLOAT_TYPE::half_precision, true /* is_min */);
8651 %}
8652 ins_pipe(pipe_class_default);
8653 %}
8654
8655 instruct min_HF_reg_zfa(fRegF dst, fRegF src1, fRegF src2)
8656 %{
8657 predicate(UseZfa);
8658 match(Set dst (MinHF src1 src2));
8659
8660 format %{ "min_hf $dst, $src1, $src2" %}
8661
8662 ins_encode %{
8663 __ fminm_h(as_FloatRegister($dst$$reg),
8664 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
8665 %}
8666
8667 ins_pipe(pipe_class_default);
8668 %}
8669
8670 instruct max_HF_reg(fRegF dst, fRegF src1, fRegF src2, rFlagsReg cr)
8671 %{
8672 predicate(!UseZfa);
8673 match(Set dst (MaxHF src1 src2));
8674 effect(KILL cr);
8675
8676 format %{ "max_hf $dst, $src1, $src2" %}
8677
8678 ins_encode %{
8679 __ minmax_fp($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister,
8680 __ FLOAT_TYPE::half_precision, false /* is_min */);
8681 %}
8682 ins_pipe(pipe_class_default);
8683 %}
8684
8685 instruct max_HF_reg_zfa(fRegF dst, fRegF src1, fRegF src2)
8686 %{
8687 predicate(UseZfa);
8688 match(Set dst (MaxHF src1 src2));
8689
8690 format %{ "max_hf $dst, $src1, $src2" %}
8691
8692 ins_encode %{
8693 __ fmaxm_h(as_FloatRegister($dst$$reg),
8694 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
8695 %}
8696
8697 ins_pipe(pipe_class_default);
8698 %}
8699
8700 instruct fma_HF_reg(fRegF dst, fRegF src1, fRegF src2, fRegF src3)
8701 %{
8702 match(Set dst (FmaHF src3 (Binary src1 src2)));
8703 format %{ "fmadd.h $dst, $src1, $src2, $src3\t# $dst = $src1 * $src2 + $src3 fma packedH" %}
8704 ins_encode %{
8705 __ fmadd_h($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister, $src3$$FloatRegister);
8706 %}
8707 ins_pipe(pipe_class_default);
8708 %}
8709
8710 // float <-> int
8711
8712 instruct convF2I_reg_reg(iRegINoSp dst, fRegF src) %{
8713 match(Set dst (ConvF2I src));
8714
8715 ins_cost(XFER_COST);
8716 format %{ "fcvt.w.s $dst, $src\t#@convF2I_reg_reg" %}
8717
8718 ins_encode %{
8719 __ fcvt_w_s_safe($dst$$Register, $src$$FloatRegister);
8720 %}
8721
8722 ins_pipe(fp_f2i);
8723 %}
8724
8725 instruct convI2F_reg_reg(fRegF dst, iRegIorL2I src) %{
8726 match(Set dst (ConvI2F src));
8727
8728 ins_cost(XFER_COST);
8729 format %{ "fcvt.s.w $dst, $src\t#@convI2F_reg_reg" %}
8730
8731 ins_encode %{
8732 __ fcvt_s_w(as_FloatRegister($dst$$reg), as_Register($src$$reg));
8733 %}
8734
8735 ins_pipe(fp_i2f);
8736 %}
8737
8738 // float <-> long
8739
8740 instruct convF2L_reg_reg(iRegLNoSp dst, fRegF src) %{
8741 match(Set dst (ConvF2L src));
8742
8743 ins_cost(XFER_COST);
8744 format %{ "fcvt.l.s $dst, $src\t#@convF2L_reg_reg" %}
8745
8746 ins_encode %{
8747 __ fcvt_l_s_safe($dst$$Register, $src$$FloatRegister);
8748 %}
8749
8750 ins_pipe(fp_f2l);
8751 %}
8752
8753 instruct convL2F_reg_reg(fRegF dst, iRegL src) %{
8754 match(Set dst (ConvL2F src));
8755
8756 ins_cost(XFER_COST);
8757 format %{ "fcvt.s.l $dst, $src\t#@convL2F_reg_reg" %}
8758
8759 ins_encode %{
8760 __ fcvt_s_l(as_FloatRegister($dst$$reg), as_Register($src$$reg));
8761 %}
8762
8763 ins_pipe(fp_l2f);
8764 %}
8765
8766 // double <-> int
8767
8768 instruct convD2I_reg_reg(iRegINoSp dst, fRegD src) %{
8769 match(Set dst (ConvD2I src));
8770
8771 ins_cost(XFER_COST);
8772 format %{ "fcvt.w.d $dst, $src\t#@convD2I_reg_reg" %}
8773
8774 ins_encode %{
8775 __ fcvt_w_d_safe($dst$$Register, $src$$FloatRegister);
8776 %}
8777
8778 ins_pipe(fp_d2i);
8779 %}
8780
8781 instruct convI2D_reg_reg(fRegD dst, iRegIorL2I src) %{
8782 match(Set dst (ConvI2D src));
8783
8784 ins_cost(XFER_COST);
8785 format %{ "fcvt.d.w $dst, $src\t#@convI2D_reg_reg" %}
8786
8787 ins_encode %{
8788 __ fcvt_d_w(as_FloatRegister($dst$$reg), as_Register($src$$reg));
8789 %}
8790
8791 ins_pipe(fp_i2d);
8792 %}
8793
8794 // double <-> long
8795
8796 instruct convD2L_reg_reg(iRegLNoSp dst, fRegD src) %{
8797 match(Set dst (ConvD2L src));
8798
8799 ins_cost(XFER_COST);
8800 format %{ "fcvt.l.d $dst, $src\t#@convD2L_reg_reg" %}
8801
8802 ins_encode %{
8803 __ fcvt_l_d_safe($dst$$Register, $src$$FloatRegister);
8804 %}
8805
8806 ins_pipe(fp_d2l);
8807 %}
8808
8809 instruct convL2D_reg_reg(fRegD dst, iRegL src) %{
8810 match(Set dst (ConvL2D src));
8811
8812 ins_cost(XFER_COST);
8813 format %{ "fcvt.d.l $dst, $src\t#@convL2D_reg_reg" %}
8814
8815 ins_encode %{
8816 __ fcvt_d_l(as_FloatRegister($dst$$reg), as_Register($src$$reg));
8817 %}
8818
8819 ins_pipe(fp_l2d);
8820 %}
8821
8822 // Convert oop into int for vectors alignment masking
8823 instruct convP2I(iRegINoSp dst, iRegP src) %{
8824 match(Set dst (ConvL2I (CastP2X src)));
8825
8826 ins_cost(ALU_COST * 2);
8827 format %{ "zext $dst, $src, 32\t# ptr -> int, #@convP2I" %}
8828
8829 ins_encode %{
8830 __ zext($dst$$Register, $src$$Register, 32);
8831 %}
8832
8833 ins_pipe(ialu_reg);
8834 %}
8835
8836 // Convert compressed oop into int for vectors alignment masking
8837 // in case of 32bit oops (heap < 4Gb).
8838 instruct convN2I(iRegINoSp dst, iRegN src)
8839 %{
8840 predicate(CompressedOops::shift() == 0);
8841 match(Set dst (ConvL2I (CastP2X (DecodeN src))));
8842
8843 ins_cost(ALU_COST);
8844 format %{ "mv $dst, $src\t# compressed ptr -> int, #@convN2I" %}
8845
8846 ins_encode %{
8847 __ mv($dst$$Register, $src$$Register);
8848 %}
8849
8850 ins_pipe(ialu_reg);
8851 %}
8852
8853 instruct round_double_reg(iRegLNoSp dst, fRegD src, fRegD ftmp) %{
8854 match(Set dst (RoundD src));
8855
8856 ins_cost(XFER_COST + BRANCH_COST);
8857 effect(TEMP ftmp);
8858 format %{ "java_round_double $dst, $src\t#@round_double_reg" %}
8859
8860 ins_encode %{
8861 __ java_round_double($dst$$Register, as_FloatRegister($src$$reg), as_FloatRegister($ftmp$$reg));
8862 %}
8863
8864 ins_pipe(pipe_slow);
8865 %}
8866
8867 instruct round_float_reg(iRegINoSp dst, fRegF src, fRegF ftmp) %{
8868 match(Set dst (RoundF src));
8869
8870 ins_cost(XFER_COST + BRANCH_COST);
8871 effect(TEMP ftmp);
8872 format %{ "java_round_float $dst, $src\t#@round_float_reg" %}
8873
8874 ins_encode %{
8875 __ java_round_float($dst$$Register, as_FloatRegister($src$$reg), as_FloatRegister($ftmp$$reg));
8876 %}
8877
8878 ins_pipe(pipe_slow);
8879 %}
8880
8881 // Convert oop pointer into compressed form
8882 instruct encodeHeapOop(iRegNNoSp dst, iRegP src) %{
8883 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
8884 match(Set dst (EncodeP src));
8885 ins_cost(ALU_COST);
8886 format %{ "encode_heap_oop $dst, $src\t#@encodeHeapOop" %}
8887 ins_encode %{
8888 Register s = $src$$Register;
8889 Register d = $dst$$Register;
8890 __ encode_heap_oop(d, s);
8891 %}
8892 ins_pipe(pipe_class_default);
8893 %}
8894
8895 instruct encodeHeapOop_not_null(iRegNNoSp dst, iRegP src) %{
8896 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
8897 match(Set dst (EncodeP src));
8898 ins_cost(ALU_COST);
8899 format %{ "encode_heap_oop_not_null $dst, $src\t#@encodeHeapOop_not_null" %}
8900 ins_encode %{
8901 __ encode_heap_oop_not_null($dst$$Register, $src$$Register);
8902 %}
8903 ins_pipe(pipe_class_default);
8904 %}
8905
8906 instruct decodeHeapOop(iRegPNoSp dst, iRegN src) %{
8907 predicate(n->bottom_type()->is_ptr()->ptr() != TypePtr::NotNull &&
8908 n->bottom_type()->is_ptr()->ptr() != TypePtr::Constant);
8909 match(Set dst (DecodeN src));
8910
8911 ins_cost(0);
8912 format %{ "decode_heap_oop $dst, $src\t#@decodeHeapOop" %}
8913 ins_encode %{
8914 Register s = $src$$Register;
8915 Register d = $dst$$Register;
8916 __ decode_heap_oop(d, s);
8917 %}
8918 ins_pipe(pipe_class_default);
8919 %}
8920
8921 instruct decodeHeapOop_not_null(iRegPNoSp dst, iRegN src) %{
8922 predicate(n->bottom_type()->is_ptr()->ptr() == TypePtr::NotNull ||
8923 n->bottom_type()->is_ptr()->ptr() == TypePtr::Constant);
8924 match(Set dst (DecodeN src));
8925
8926 ins_cost(0);
8927 format %{ "decode_heap_oop_not_null $dst, $src\t#@decodeHeapOop_not_null" %}
8928 ins_encode %{
8929 Register s = $src$$Register;
8930 Register d = $dst$$Register;
8931 __ decode_heap_oop_not_null(d, s);
8932 %}
8933 ins_pipe(pipe_class_default);
8934 %}
8935
8936 // Convert klass pointer into compressed form.
8937 instruct encodeKlass_not_null(iRegNNoSp dst, iRegP src) %{
8938 match(Set dst (EncodePKlass src));
8939
8940 ins_cost(ALU_COST);
8941 format %{ "encode_klass_not_null $dst, $src\t#@encodeKlass_not_null" %}
8942
8943 ins_encode %{
8944 Register src_reg = as_Register($src$$reg);
8945 Register dst_reg = as_Register($dst$$reg);
8946 __ encode_klass_not_null(dst_reg, src_reg, t0);
8947 %}
8948
8949 ins_pipe(pipe_class_default);
8950 %}
8951
8952 instruct decodeKlass_not_null(iRegPNoSp dst, iRegN src, iRegPNoSp tmp) %{
8953 match(Set dst (DecodeNKlass src));
8954
8955 effect(TEMP_DEF dst, TEMP tmp);
8956
8957 ins_cost(ALU_COST);
8958 format %{ "decode_klass_not_null $dst, $src\t#@decodeKlass_not_null" %}
8959
8960 ins_encode %{
8961 Register src_reg = as_Register($src$$reg);
8962 Register dst_reg = as_Register($dst$$reg);
8963 Register tmp_reg = as_Register($tmp$$reg);
8964 __ decode_klass_not_null(dst_reg, src_reg, tmp_reg);
8965 %}
8966
8967 ins_pipe(pipe_class_default);
8968 %}
8969
8970 // stack <-> reg and reg <-> reg shuffles with no conversion
8971
8972 instruct MoveF2I_stack_reg(iRegINoSp dst, stackSlotF src) %{
8973
8974 match(Set dst (MoveF2I src));
8975
8976 effect(DEF dst, USE src);
8977
8978 ins_cost(LOAD_COST);
8979
8980 format %{ "lw $dst, $src\t#@MoveF2I_stack_reg" %}
8981
8982 ins_encode %{
8983 __ lw(as_Register($dst$$reg), Address(sp, $src$$disp));
8984 %}
8985
8986 ins_pipe(iload_reg_reg);
8987
8988 %}
8989
8990 instruct MoveI2F_stack_reg(fRegF dst, stackSlotI src) %{
8991
8992 match(Set dst (MoveI2F src));
8993
8994 effect(DEF dst, USE src);
8995
8996 ins_cost(LOAD_COST);
8997
8998 format %{ "flw $dst, $src\t#@MoveI2F_stack_reg" %}
8999
9000 ins_encode %{
9001 __ flw(as_FloatRegister($dst$$reg), Address(sp, $src$$disp));
9002 %}
9003
9004 ins_pipe(fp_load_mem_s);
9005
9006 %}
9007
9008 instruct MoveD2L_stack_reg(iRegLNoSp dst, stackSlotD src) %{
9009
9010 match(Set dst (MoveD2L src));
9011
9012 effect(DEF dst, USE src);
9013
9014 ins_cost(LOAD_COST);
9015
9016 format %{ "ld $dst, $src\t#@MoveD2L_stack_reg" %}
9017
9018 ins_encode %{
9019 __ ld(as_Register($dst$$reg), Address(sp, $src$$disp));
9020 %}
9021
9022 ins_pipe(iload_reg_reg);
9023
9024 %}
9025
9026 instruct MoveL2D_stack_reg(fRegD dst, stackSlotL src) %{
9027
9028 match(Set dst (MoveL2D src));
9029
9030 effect(DEF dst, USE src);
9031
9032 ins_cost(LOAD_COST);
9033
9034 format %{ "fld $dst, $src\t#@MoveL2D_stack_reg" %}
9035
9036 ins_encode %{
9037 __ fld(as_FloatRegister($dst$$reg), Address(sp, $src$$disp));
9038 %}
9039
9040 ins_pipe(fp_load_mem_d);
9041
9042 %}
9043
9044 instruct MoveF2I_reg_stack(stackSlotI dst, fRegF src) %{
9045
9046 match(Set dst (MoveF2I src));
9047
9048 effect(DEF dst, USE src);
9049
9050 ins_cost(STORE_COST);
9051
9052 format %{ "fsw $src, $dst\t#@MoveF2I_reg_stack" %}
9053
9054 ins_encode %{
9055 __ fsw(as_FloatRegister($src$$reg), Address(sp, $dst$$disp));
9056 %}
9057
9058 ins_pipe(fp_store_reg_s);
9059
9060 %}
9061
9062 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{
9063
9064 match(Set dst (MoveI2F src));
9065
9066 effect(DEF dst, USE src);
9067
9068 ins_cost(STORE_COST);
9069
9070 format %{ "sw $src, $dst\t#@MoveI2F_reg_stack" %}
9071
9072 ins_encode %{
9073 __ sw(as_Register($src$$reg), Address(sp, $dst$$disp));
9074 %}
9075
9076 ins_pipe(istore_reg_reg);
9077
9078 %}
9079
9080 instruct MoveD2L_reg_stack(stackSlotL dst, fRegD src) %{
9081
9082 match(Set dst (MoveD2L src));
9083
9084 effect(DEF dst, USE src);
9085
9086 ins_cost(STORE_COST);
9087
9088 format %{ "fsd $dst, $src\t#@MoveD2L_reg_stack" %}
9089
9090 ins_encode %{
9091 __ fsd(as_FloatRegister($src$$reg), Address(sp, $dst$$disp));
9092 %}
9093
9094 ins_pipe(fp_store_reg_d);
9095
9096 %}
9097
9098 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{
9099
9100 match(Set dst (MoveL2D src));
9101
9102 effect(DEF dst, USE src);
9103
9104 ins_cost(STORE_COST);
9105
9106 format %{ "sd $src, $dst\t#@MoveL2D_reg_stack" %}
9107
9108 ins_encode %{
9109 __ sd(as_Register($src$$reg), Address(sp, $dst$$disp));
9110 %}
9111
9112 ins_pipe(istore_reg_reg);
9113
9114 %}
9115
9116 instruct MoveF2I_reg_reg(iRegINoSp dst, fRegF src) %{
9117
9118 match(Set dst (MoveF2I src));
9119
9120 effect(DEF dst, USE src);
9121
9122 ins_cost(FMVX_COST);
9123
9124 format %{ "fmv.x.w $dst, $src\t#@MoveF2I_reg_reg" %}
9125
9126 ins_encode %{
9127 __ fmv_x_w(as_Register($dst$$reg), as_FloatRegister($src$$reg));
9128 %}
9129
9130 ins_pipe(fp_f2i);
9131
9132 %}
9133
9134 instruct MoveI2F_reg_reg(fRegF dst, iRegI src) %{
9135
9136 match(Set dst (MoveI2F src));
9137
9138 effect(DEF dst, USE src);
9139
9140 ins_cost(FMVX_COST);
9141
9142 format %{ "fmv.w.x $dst, $src\t#@MoveI2F_reg_reg" %}
9143
9144 ins_encode %{
9145 __ fmv_w_x(as_FloatRegister($dst$$reg), as_Register($src$$reg));
9146 %}
9147
9148 ins_pipe(fp_i2f);
9149
9150 %}
9151
9152 instruct MoveD2L_reg_reg(iRegLNoSp dst, fRegD src) %{
9153
9154 match(Set dst (MoveD2L src));
9155
9156 effect(DEF dst, USE src);
9157
9158 ins_cost(FMVX_COST);
9159
9160 format %{ "fmv.x.d $dst, $src\t#@MoveD2L_reg_reg" %}
9161
9162 ins_encode %{
9163 __ fmv_x_d(as_Register($dst$$reg), as_FloatRegister($src$$reg));
9164 %}
9165
9166 ins_pipe(fp_d2l);
9167
9168 %}
9169
9170 instruct MoveL2D_reg_reg(fRegD dst, iRegL src) %{
9171
9172 match(Set dst (MoveL2D src));
9173
9174 effect(DEF dst, USE src);
9175
9176 ins_cost(FMVX_COST);
9177
9178 format %{ "fmv.d.x $dst, $src\t#@MoveL2D_reg_reg" %}
9179
9180 ins_encode %{
9181 __ fmv_d_x(as_FloatRegister($dst$$reg), as_Register($src$$reg));
9182 %}
9183
9184 ins_pipe(fp_l2d);
9185
9186 %}
9187
9188 // ============================================================================
9189 // Compare Instructions which set the result float comparisons in dest register.
9190
9191 instruct cmpF3_reg_reg(iRegINoSp dst, fRegF op1, fRegF op2)
9192 %{
9193 match(Set dst (CmpF3 op1 op2));
9194
9195 ins_cost(XFER_COST * 2 + BRANCH_COST + ALU_COST);
9196 format %{ "flt.s $dst, $op2, $op1\t#@cmpF3_reg_reg\n\t"
9197 "bgtz $dst, done\n\t"
9198 "feq.s $dst, $op1, $op2\n\t"
9199 "addi $dst, $dst, -1\n\t"
9200 "done:"
9201 %}
9202
9203 ins_encode %{
9204 // we want -1 for unordered or less than, 0 for equal and 1 for greater than.
9205 __ float_compare(as_Register($dst$$reg), as_FloatRegister($op1$$reg),
9206 as_FloatRegister($op2$$reg), -1 /*unordered_result < 0*/);
9207 %}
9208
9209 ins_pipe(pipe_class_default);
9210 %}
9211
9212 instruct cmpD3_reg_reg(iRegINoSp dst, fRegD op1, fRegD op2)
9213 %{
9214 match(Set dst (CmpD3 op1 op2));
9215
9216 ins_cost(XFER_COST * 2 + BRANCH_COST + ALU_COST);
9217 format %{ "flt.d $dst, $op2, $op1\t#@cmpD3_reg_reg\n\t"
9218 "bgtz $dst, done\n\t"
9219 "feq.d $dst, $op1, $op2\n\t"
9220 "addi $dst, $dst, -1\n\t"
9221 "done:"
9222 %}
9223
9224 ins_encode %{
9225 // we want -1 for unordered or less than, 0 for equal and 1 for greater than.
9226 __ double_compare(as_Register($dst$$reg), as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg), -1 /*unordered_result < 0*/);
9227 %}
9228
9229 ins_pipe(pipe_class_default);
9230 %}
9231
9232 instruct cmpL3_reg_reg(iRegINoSp dst, iRegL op1, iRegL op2)
9233 %{
9234 match(Set dst (CmpL3 op1 op2));
9235
9236 ins_cost(ALU_COST * 3 + BRANCH_COST);
9237 format %{ "slt $dst, $op2, $op1\t#@cmpL3_reg_reg\n\t"
9238 "bnez $dst, done\n\t"
9239 "slt $dst, $op1, $op2\n\t"
9240 "neg $dst, $dst\n\t"
9241 "done:"
9242 %}
9243 ins_encode %{
9244 __ cmp_l2i(t0, as_Register($op1$$reg), as_Register($op2$$reg));
9245 __ mv(as_Register($dst$$reg), t0);
9246 %}
9247
9248 ins_pipe(pipe_class_default);
9249 %}
9250
9251 instruct cmpUL3_reg_reg(iRegINoSp dst, iRegL op1, iRegL op2)
9252 %{
9253 match(Set dst (CmpUL3 op1 op2));
9254
9255 ins_cost(ALU_COST * 3 + BRANCH_COST);
9256 format %{ "sltu $dst, $op2, $op1\t#@cmpUL3_reg_reg\n\t"
9257 "bnez $dst, done\n\t"
9258 "sltu $dst, $op1, $op2\n\t"
9259 "neg $dst, $dst\n\t"
9260 "done:"
9261 %}
9262 ins_encode %{
9263 __ cmp_ul2i(t0, as_Register($op1$$reg), as_Register($op2$$reg));
9264 __ mv(as_Register($dst$$reg), t0);
9265 %}
9266
9267 ins_pipe(pipe_class_default);
9268 %}
9269
9270 instruct cmpU3_reg_reg(iRegINoSp dst, iRegI op1, iRegI op2)
9271 %{
9272 match(Set dst (CmpU3 op1 op2));
9273
9274 ins_cost(ALU_COST * 3 + BRANCH_COST);
9275 format %{ "sltu $dst, $op2, $op1\t#@cmpU3_reg_reg\n\t"
9276 "bnez $dst, done\n\t"
9277 "sltu $dst, $op1, $op2\n\t"
9278 "neg $dst, $dst\n\t"
9279 "done:"
9280 %}
9281 ins_encode %{
9282 __ cmp_uw2i(t0, as_Register($op1$$reg), as_Register($op2$$reg));
9283 __ mv(as_Register($dst$$reg), t0);
9284 %}
9285
9286 ins_pipe(pipe_class_default);
9287 %}
9288
9289 instruct cmpLTMask_reg_reg(iRegINoSp dst, iRegI p, iRegI q)
9290 %{
9291 match(Set dst (CmpLTMask p q));
9292
9293 ins_cost(2 * ALU_COST);
9294
9295 format %{ "slt $dst, $p, $q\t#@cmpLTMask_reg_reg\n\t"
9296 "subw $dst, zr, $dst\t#@cmpLTMask_reg_reg"
9297 %}
9298
9299 ins_encode %{
9300 __ slt(as_Register($dst$$reg), as_Register($p$$reg), as_Register($q$$reg));
9301 __ subw(as_Register($dst$$reg), zr, as_Register($dst$$reg));
9302 %}
9303
9304 ins_pipe(ialu_reg_reg);
9305 %}
9306
9307 instruct cmpLTMask_reg_zero(iRegINoSp dst, iRegIorL2I op, immI0 zero)
9308 %{
9309 match(Set dst (CmpLTMask op zero));
9310
9311 ins_cost(ALU_COST);
9312
9313 format %{ "sraiw $dst, $dst, 31\t#@cmpLTMask_reg_reg" %}
9314
9315 ins_encode %{
9316 __ sraiw(as_Register($dst$$reg), as_Register($op$$reg), 31);
9317 %}
9318
9319 ins_pipe(ialu_reg_shift);
9320 %}
9321
9322
9323 // ============================================================================
9324 // Max and Min
9325
9326 instruct minI_reg_reg(iRegINoSp dst, iRegI src)
9327 %{
9328 match(Set dst (MinI dst src));
9329
9330 ins_cost(BRANCH_COST + ALU_COST);
9331 format %{"minI_reg_reg $dst, $dst, $src\t#@minI_reg_reg\n\t"%}
9332
9333 ins_encode %{
9334 __ cmov_gt(as_Register($dst$$reg), as_Register($src$$reg),
9335 as_Register($dst$$reg), as_Register($src$$reg));
9336 %}
9337
9338 ins_pipe(pipe_class_compare);
9339 %}
9340
9341 instruct maxI_reg_reg(iRegINoSp dst, iRegI src)
9342 %{
9343 match(Set dst (MaxI dst src));
9344
9345 ins_cost(BRANCH_COST + ALU_COST);
9346 format %{"maxI_reg_reg $dst, $dst, $src\t#@maxI_reg_reg\n\t"%}
9347
9348 ins_encode %{
9349 __ cmov_lt(as_Register($dst$$reg), as_Register($src$$reg),
9350 as_Register($dst$$reg), as_Register($src$$reg));
9351 %}
9352
9353 ins_pipe(pipe_class_compare);
9354 %}
9355
9356 // special case for comparing with zero
9357 // n.b. this is selected in preference to the rule above because it
9358 // avoids loading constant 0 into a source register
9359
9360 instruct minI_reg_zero(iRegINoSp dst, immI0 zero)
9361 %{
9362 match(Set dst (MinI dst zero));
9363 match(Set dst (MinI zero dst));
9364
9365 ins_cost(BRANCH_COST + ALU_COST);
9366 format %{"minI_reg_zero $dst, $dst, zr\t#@minI_reg_zero\n\t"%}
9367
9368 ins_encode %{
9369 __ cmov_gt(as_Register($dst$$reg), zr,
9370 as_Register($dst$$reg), zr);
9371 %}
9372
9373 ins_pipe(pipe_class_compare);
9374 %}
9375
9376 instruct maxI_reg_zero(iRegINoSp dst, immI0 zero)
9377 %{
9378 match(Set dst (MaxI dst zero));
9379 match(Set dst (MaxI zero dst));
9380
9381 ins_cost(BRANCH_COST + ALU_COST);
9382 format %{"maxI_reg_zero $dst, $dst, zr\t#@maxI_reg_zero\n\t"%}
9383
9384 ins_encode %{
9385 __ cmov_lt(as_Register($dst$$reg), zr,
9386 as_Register($dst$$reg), zr);
9387 %}
9388
9389 ins_pipe(pipe_class_compare);
9390 %}
9391
9392 instruct minI_rReg(iRegINoSp dst, iRegI src1, iRegI src2)
9393 %{
9394 match(Set dst (MinI src1 src2));
9395
9396 effect(DEF dst, USE src1, USE src2);
9397
9398 ins_cost(BRANCH_COST + ALU_COST * 2);
9399 format %{"minI_rReg $dst, $src1, $src2\t#@minI_rReg\n\t"%}
9400
9401 ins_encode %{
9402 __ mv(as_Register($dst$$reg), as_Register($src1$$reg));
9403 __ cmov_gt(as_Register($src1$$reg), as_Register($src2$$reg),
9404 as_Register($dst$$reg), as_Register($src2$$reg));
9405 %}
9406
9407 ins_pipe(pipe_class_compare);
9408 %}
9409
9410 instruct maxI_rReg(iRegINoSp dst, iRegI src1, iRegI src2)
9411 %{
9412 match(Set dst (MaxI src1 src2));
9413
9414 effect(DEF dst, USE src1, USE src2);
9415
9416 ins_cost(BRANCH_COST + ALU_COST * 2);
9417 format %{"maxI_rReg $dst, $src1, $src2\t#@maxI_rReg\n\t"%}
9418
9419 ins_encode %{
9420 __ mv(as_Register($dst$$reg), as_Register($src1$$reg));
9421 __ cmov_lt(as_Register($src1$$reg), as_Register($src2$$reg),
9422 as_Register($dst$$reg), as_Register($src2$$reg));
9423 %}
9424
9425 ins_pipe(pipe_class_compare);
9426 %}
9427
9428 // ============================================================================
9429 // Branch Instructions
9430 // Direct Branch.
9431 instruct branch(label lbl)
9432 %{
9433 match(Goto);
9434
9435 effect(USE lbl);
9436
9437 ins_cost(BRANCH_COST);
9438 format %{ "j $lbl\t#@branch" %}
9439
9440 ins_encode(riscv_enc_j(lbl));
9441
9442 ins_pipe(pipe_branch);
9443 %}
9444
9445 // ============================================================================
9446 // Compare and Branch Instructions
9447
9448 // Patterns for short (< 12KiB) variants
9449
9450 // Compare flags and branch near instructions.
9451 instruct cmpFlag_branch(cmpOpEqNe cmp, rFlagsReg cr, label lbl) %{
9452 match(If cmp cr);
9453 effect(USE lbl);
9454
9455 ins_cost(BRANCH_COST);
9456 format %{ "b$cmp $cr, zr, $lbl\t#@cmpFlag_branch" %}
9457
9458 ins_encode %{
9459 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($cr$$reg), *($lbl$$label));
9460 %}
9461 ins_pipe(pipe_cmpz_branch);
9462 ins_short_branch(1);
9463 %}
9464
9465 // Compare signed int and branch near instructions
9466 instruct cmpI_branch(cmpOp cmp, iRegI op1, iRegI op2, label lbl)
9467 %{
9468 // Same match rule as `far_cmpI_branch'.
9469 match(If cmp (CmpI op1 op2));
9470
9471 effect(USE lbl);
9472
9473 ins_cost(BRANCH_COST);
9474
9475 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpI_branch" %}
9476
9477 ins_encode %{
9478 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label));
9479 %}
9480
9481 ins_pipe(pipe_cmp_branch);
9482 ins_short_branch(1);
9483 %}
9484
9485 instruct cmpI_loop(cmpOp cmp, iRegI op1, iRegI op2, label lbl)
9486 %{
9487 // Same match rule as `far_cmpI_loop'.
9488 match(CountedLoopEnd cmp (CmpI op1 op2));
9489
9490 effect(USE lbl);
9491
9492 ins_cost(BRANCH_COST);
9493
9494 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpI_loop" %}
9495
9496 ins_encode %{
9497 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label));
9498 %}
9499
9500 ins_pipe(pipe_cmp_branch);
9501 ins_short_branch(1);
9502 %}
9503
9504 // Compare unsigned int and branch near instructions
9505 instruct cmpU_branch(cmpOpU cmp, iRegI op1, iRegI op2, label lbl)
9506 %{
9507 // Same match rule as `far_cmpU_branch'.
9508 match(If cmp (CmpU op1 op2));
9509
9510 effect(USE lbl);
9511
9512 ins_cost(BRANCH_COST);
9513
9514 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpU_branch" %}
9515
9516 ins_encode %{
9517 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9518 as_Register($op2$$reg), *($lbl$$label));
9519 %}
9520
9521 ins_pipe(pipe_cmp_branch);
9522 ins_short_branch(1);
9523 %}
9524
9525 // Compare signed long and branch near instructions
9526 instruct cmpL_branch(cmpOp cmp, iRegL op1, iRegL op2, label lbl)
9527 %{
9528 // Same match rule as `far_cmpL_branch'.
9529 match(If cmp (CmpL op1 op2));
9530
9531 effect(USE lbl);
9532
9533 ins_cost(BRANCH_COST);
9534
9535 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpL_branch" %}
9536
9537 ins_encode %{
9538 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label));
9539 %}
9540
9541 ins_pipe(pipe_cmp_branch);
9542 ins_short_branch(1);
9543 %}
9544
9545 instruct cmpL_loop(cmpOp cmp, iRegL op1, iRegL op2, label lbl)
9546 %{
9547 // Same match rule as `far_cmpL_loop'.
9548 match(CountedLoopEnd cmp (CmpL op1 op2));
9549
9550 effect(USE lbl);
9551
9552 ins_cost(BRANCH_COST);
9553
9554 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpL_loop" %}
9555
9556 ins_encode %{
9557 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label));
9558 %}
9559
9560 ins_pipe(pipe_cmp_branch);
9561 ins_short_branch(1);
9562 %}
9563
9564 // Compare unsigned long and branch near instructions
9565 instruct cmpUL_branch(cmpOpU cmp, iRegL op1, iRegL op2, label lbl)
9566 %{
9567 // Same match rule as `far_cmpUL_branch'.
9568 match(If cmp (CmpUL op1 op2));
9569
9570 effect(USE lbl);
9571
9572 ins_cost(BRANCH_COST);
9573 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpUL_branch" %}
9574
9575 ins_encode %{
9576 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9577 as_Register($op2$$reg), *($lbl$$label));
9578 %}
9579
9580 ins_pipe(pipe_cmp_branch);
9581 ins_short_branch(1);
9582 %}
9583
9584 // Compare pointer and branch near instructions
9585 instruct cmpP_branch(cmpOpU cmp, iRegP op1, iRegP op2, label lbl)
9586 %{
9587 // Same match rule as `far_cmpP_branch'.
9588 match(If cmp (CmpP op1 op2));
9589
9590 effect(USE lbl);
9591
9592 ins_cost(BRANCH_COST);
9593
9594 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpP_branch" %}
9595
9596 ins_encode %{
9597 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9598 as_Register($op2$$reg), *($lbl$$label));
9599 %}
9600
9601 ins_pipe(pipe_cmp_branch);
9602 ins_short_branch(1);
9603 %}
9604
9605 // Compare narrow pointer and branch near instructions
9606 instruct cmpN_branch(cmpOpU cmp, iRegN op1, iRegN op2, label lbl)
9607 %{
9608 // Same match rule as `far_cmpN_branch'.
9609 match(If cmp (CmpN op1 op2));
9610
9611 effect(USE lbl);
9612
9613 ins_cost(BRANCH_COST);
9614
9615 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpN_branch" %}
9616
9617 ins_encode %{
9618 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9619 as_Register($op2$$reg), *($lbl$$label));
9620 %}
9621
9622 ins_pipe(pipe_cmp_branch);
9623 ins_short_branch(1);
9624 %}
9625
9626 // Compare float and branch near instructions
9627 instruct cmpF_branch(cmpOp cmp, fRegF op1, fRegF op2, label lbl)
9628 %{
9629 // Same match rule as `far_cmpF_branch'.
9630 match(If cmp (CmpF op1 op2));
9631
9632 effect(USE lbl);
9633
9634 ins_cost(XFER_COST + BRANCH_COST);
9635 format %{ "float_b$cmp $op1, $op2, $lbl \t#@cmpF_branch"%}
9636
9637 ins_encode %{
9638 __ float_cmp_branch($cmp$$cmpcode, as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg), *($lbl$$label));
9639 %}
9640
9641 ins_pipe(pipe_class_compare);
9642 ins_short_branch(1);
9643 %}
9644
9645 // Compare double and branch near instructions
9646 instruct cmpD_branch(cmpOp cmp, fRegD op1, fRegD op2, label lbl)
9647 %{
9648 // Same match rule as `far_cmpD_branch'.
9649 match(If cmp (CmpD op1 op2));
9650 effect(USE lbl);
9651
9652 ins_cost(XFER_COST + BRANCH_COST);
9653 format %{ "double_b$cmp $op1, $op2, $lbl\t#@cmpD_branch"%}
9654
9655 ins_encode %{
9656 __ float_cmp_branch($cmp$$cmpcode | C2_MacroAssembler::double_branch_mask, as_FloatRegister($op1$$reg),
9657 as_FloatRegister($op2$$reg), *($lbl$$label));
9658 %}
9659
9660 ins_pipe(pipe_class_compare);
9661 ins_short_branch(1);
9662 %}
9663
9664 // Compare signed int with zero and branch near instructions
9665 instruct cmpI_reg_imm0_branch(cmpOp cmp, iRegI op1, immI0 zero, label lbl)
9666 %{
9667 // Same match rule as `far_cmpI_reg_imm0_branch'.
9668 match(If cmp (CmpI op1 zero));
9669
9670 effect(USE op1, USE lbl);
9671
9672 ins_cost(BRANCH_COST);
9673 format %{ "b$cmp $op1, zr, $lbl\t#@cmpI_reg_imm0_branch" %}
9674
9675 ins_encode %{
9676 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label));
9677 %}
9678
9679 ins_pipe(pipe_cmpz_branch);
9680 ins_short_branch(1);
9681 %}
9682
9683 instruct cmpI_reg_imm0_loop(cmpOp cmp, iRegI op1, immI0 zero, label lbl)
9684 %{
9685 // Same match rule as `far_cmpI_reg_imm0_loop'.
9686 match(CountedLoopEnd cmp (CmpI op1 zero));
9687
9688 effect(USE op1, USE lbl);
9689
9690 ins_cost(BRANCH_COST);
9691
9692 format %{ "b$cmp $op1, zr, $lbl\t#@cmpI_reg_imm0_loop" %}
9693
9694 ins_encode %{
9695 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label));
9696 %}
9697
9698 ins_pipe(pipe_cmpz_branch);
9699 ins_short_branch(1);
9700 %}
9701
9702 // Compare unsigned int with zero and branch near instructions
9703 instruct cmpUEqNeLeGt_reg_imm0_branch(cmpOpUEqNeLeGt cmp, iRegI op1, immI0 zero, label lbl)
9704 %{
9705 // Same match rule as `far_cmpUEqNeLeGt_reg_imm0_branch'.
9706 match(If cmp (CmpU op1 zero));
9707
9708 effect(USE op1, USE lbl);
9709
9710 ins_cost(BRANCH_COST);
9711
9712 format %{ "b$cmp $op1, zr, $lbl\t#@cmpUEqNeLeGt_reg_imm0_branch" %}
9713
9714 ins_encode %{
9715 __ enc_cmpUEqNeLeGt_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
9716 %}
9717
9718 ins_pipe(pipe_cmpz_branch);
9719 ins_short_branch(1);
9720 %}
9721
9722 // Compare signed long with zero and branch near instructions
9723 instruct cmpL_reg_imm0_branch(cmpOp cmp, iRegL op1, immL0 zero, label lbl)
9724 %{
9725 // Same match rule as `far_cmpL_reg_imm0_branch'.
9726 match(If cmp (CmpL op1 zero));
9727
9728 effect(USE op1, USE lbl);
9729
9730 ins_cost(BRANCH_COST);
9731
9732 format %{ "b$cmp $op1, zr, $lbl\t#@cmpL_reg_imm0_branch" %}
9733
9734 ins_encode %{
9735 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label));
9736 %}
9737
9738 ins_pipe(pipe_cmpz_branch);
9739 ins_short_branch(1);
9740 %}
9741
9742 instruct cmpL_reg_imm0_loop(cmpOp cmp, iRegL op1, immL0 zero, label lbl)
9743 %{
9744 // Same match rule as `far_cmpL_reg_imm0_loop'.
9745 match(CountedLoopEnd cmp (CmpL op1 zero));
9746
9747 effect(USE op1, USE lbl);
9748
9749 ins_cost(BRANCH_COST);
9750
9751 format %{ "b$cmp $op1, zr, $lbl\t#@cmpL_reg_imm0_loop" %}
9752
9753 ins_encode %{
9754 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label));
9755 %}
9756
9757 ins_pipe(pipe_cmpz_branch);
9758 ins_short_branch(1);
9759 %}
9760
9761 // Compare unsigned long with zero and branch near instructions
9762 instruct cmpULEqNeLeGt_reg_imm0_branch(cmpOpUEqNeLeGt cmp, iRegL op1, immL0 zero, label lbl)
9763 %{
9764 // Same match rule as `far_cmpULEqNeLeGt_reg_imm0_branch'.
9765 match(If cmp (CmpUL op1 zero));
9766
9767 effect(USE op1, USE lbl);
9768
9769 ins_cost(BRANCH_COST);
9770
9771 format %{ "b$cmp $op1, zr, $lbl\t#@cmpULEqNeLeGt_reg_imm0_branch" %}
9772
9773 ins_encode %{
9774 __ enc_cmpUEqNeLeGt_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
9775 %}
9776
9777 ins_pipe(pipe_cmpz_branch);
9778 ins_short_branch(1);
9779 %}
9780
9781 // Compare pointer with zero and branch near instructions
9782 instruct cmpP_imm0_branch(cmpOpEqNe cmp, iRegP op1, immP0 zero, label lbl) %{
9783 // Same match rule as `far_cmpP_reg_imm0_branch'.
9784 match(If cmp (CmpP op1 zero));
9785 effect(USE lbl);
9786
9787 ins_cost(BRANCH_COST);
9788 format %{ "b$cmp $op1, zr, $lbl\t#@cmpP_imm0_branch" %}
9789
9790 ins_encode %{
9791 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
9792 %}
9793
9794 ins_pipe(pipe_cmpz_branch);
9795 ins_short_branch(1);
9796 %}
9797
9798 // Compare narrow pointer with zero and branch near instructions
9799 instruct cmpN_imm0_branch(cmpOpEqNe cmp, iRegN op1, immN0 zero, label lbl) %{
9800 // Same match rule as `far_cmpN_reg_imm0_branch'.
9801 match(If cmp (CmpN op1 zero));
9802 effect(USE lbl);
9803
9804 ins_cost(BRANCH_COST);
9805
9806 format %{ "b$cmp $op1, zr, $lbl\t#@cmpN_imm0_branch" %}
9807
9808 ins_encode %{
9809 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
9810 %}
9811
9812 ins_pipe(pipe_cmpz_branch);
9813 ins_short_branch(1);
9814 %}
9815
9816 // Compare narrow pointer with pointer zero and branch near instructions
9817 instruct cmpP_narrowOop_imm0_branch(cmpOpEqNe cmp, iRegN op1, immP0 zero, label lbl) %{
9818 // Same match rule as `far_cmpP_narrowOop_imm0_branch'.
9819 match(If cmp (CmpP (DecodeN op1) zero));
9820 effect(USE lbl);
9821
9822 ins_cost(BRANCH_COST);
9823 format %{ "b$cmp $op1, zr, $lbl\t#@cmpP_narrowOop_imm0_branch" %}
9824
9825 ins_encode %{
9826 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
9827 %}
9828
9829 ins_pipe(pipe_cmpz_branch);
9830 ins_short_branch(1);
9831 %}
9832
9833 // Patterns for far (20KiB) variants
9834
9835 instruct far_cmpFlag_branch(cmpOp cmp, rFlagsReg cr, label lbl) %{
9836 match(If cmp cr);
9837 effect(USE lbl);
9838
9839 ins_cost(BRANCH_COST);
9840 format %{ "far_b$cmp $cr, zr, $lbl\t#@far_cmpFlag_branch"%}
9841
9842 ins_encode %{
9843 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($cr$$reg), *($lbl$$label), /* is_far */ true);
9844 %}
9845
9846 ins_pipe(pipe_cmpz_branch);
9847 %}
9848
9849 // Compare signed int and branch far instructions
9850 instruct far_cmpI_branch(cmpOp cmp, iRegI op1, iRegI op2, label lbl) %{
9851 match(If cmp (CmpI op1 op2));
9852 effect(USE lbl);
9853
9854 ins_cost(BRANCH_COST * 2);
9855
9856 // the format instruction [far_b$cmp] here is be used as two insructions
9857 // in macroassembler: b$not_cmp(op1, op2, done), j($lbl), bind(done)
9858 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpI_branch" %}
9859
9860 ins_encode %{
9861 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9862 %}
9863
9864 ins_pipe(pipe_cmp_branch);
9865 %}
9866
9867 instruct far_cmpI_loop(cmpOp cmp, iRegI op1, iRegI op2, label lbl) %{
9868 match(CountedLoopEnd cmp (CmpI op1 op2));
9869 effect(USE lbl);
9870
9871 ins_cost(BRANCH_COST * 2);
9872 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpI_loop" %}
9873
9874 ins_encode %{
9875 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9876 %}
9877
9878 ins_pipe(pipe_cmp_branch);
9879 %}
9880
9881 instruct far_cmpU_branch(cmpOpU cmp, iRegI op1, iRegI op2, label lbl) %{
9882 match(If cmp (CmpU op1 op2));
9883 effect(USE lbl);
9884
9885 ins_cost(BRANCH_COST * 2);
9886 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpU_branch" %}
9887
9888 ins_encode %{
9889 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9890 as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9891 %}
9892
9893 ins_pipe(pipe_cmp_branch);
9894 %}
9895
9896 instruct far_cmpL_branch(cmpOp cmp, iRegL op1, iRegL op2, label lbl) %{
9897 match(If cmp (CmpL op1 op2));
9898 effect(USE lbl);
9899
9900 ins_cost(BRANCH_COST * 2);
9901 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpL_branch" %}
9902
9903 ins_encode %{
9904 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9905 %}
9906
9907 ins_pipe(pipe_cmp_branch);
9908 %}
9909
9910 instruct far_cmpLloop(cmpOp cmp, iRegL op1, iRegL op2, label lbl) %{
9911 match(CountedLoopEnd cmp (CmpL op1 op2));
9912 effect(USE lbl);
9913
9914 ins_cost(BRANCH_COST * 2);
9915 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpL_loop" %}
9916
9917 ins_encode %{
9918 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9919 %}
9920
9921 ins_pipe(pipe_cmp_branch);
9922 %}
9923
9924 instruct far_cmpUL_branch(cmpOpU cmp, iRegL op1, iRegL op2, label lbl) %{
9925 match(If cmp (CmpUL op1 op2));
9926 effect(USE lbl);
9927
9928 ins_cost(BRANCH_COST * 2);
9929 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpUL_branch" %}
9930
9931 ins_encode %{
9932 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9933 as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9934 %}
9935
9936 ins_pipe(pipe_cmp_branch);
9937 %}
9938
9939 instruct far_cmpP_branch(cmpOpU cmp, iRegP op1, iRegP op2, label lbl)
9940 %{
9941 match(If cmp (CmpP op1 op2));
9942
9943 effect(USE lbl);
9944
9945 ins_cost(BRANCH_COST * 2);
9946
9947 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpP_branch" %}
9948
9949 ins_encode %{
9950 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9951 as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9952 %}
9953
9954 ins_pipe(pipe_cmp_branch);
9955 %}
9956
9957 instruct far_cmpN_branch(cmpOpU cmp, iRegN op1, iRegN op2, label lbl)
9958 %{
9959 match(If cmp (CmpN op1 op2));
9960
9961 effect(USE lbl);
9962
9963 ins_cost(BRANCH_COST * 2);
9964
9965 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpN_branch" %}
9966
9967 ins_encode %{
9968 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9969 as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9970 %}
9971
9972 ins_pipe(pipe_cmp_branch);
9973 %}
9974
9975 // Float compare and branch instructions
9976 instruct far_cmpF_branch(cmpOp cmp, fRegF op1, fRegF op2, label lbl)
9977 %{
9978 match(If cmp (CmpF op1 op2));
9979
9980 effect(USE lbl);
9981
9982 ins_cost(XFER_COST + BRANCH_COST * 2);
9983 format %{ "far_float_b$cmp $op1, $op2, $lbl\t#@far_cmpF_branch"%}
9984
9985 ins_encode %{
9986 __ float_cmp_branch($cmp$$cmpcode, as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg),
9987 *($lbl$$label), /* is_far */ true);
9988 %}
9989
9990 ins_pipe(pipe_class_compare);
9991 %}
9992
9993 // Double compare and branch instructions
9994 instruct far_cmpD_branch(cmpOp cmp, fRegD op1, fRegD op2, label lbl)
9995 %{
9996 match(If cmp (CmpD op1 op2));
9997 effect(USE lbl);
9998
9999 ins_cost(XFER_COST + BRANCH_COST * 2);
10000 format %{ "far_double_b$cmp $op1, $op2, $lbl\t#@far_cmpD_branch"%}
10001
10002 ins_encode %{
10003 __ float_cmp_branch($cmp$$cmpcode | C2_MacroAssembler::double_branch_mask, as_FloatRegister($op1$$reg),
10004 as_FloatRegister($op2$$reg), *($lbl$$label), /* is_far */ true);
10005 %}
10006
10007 ins_pipe(pipe_class_compare);
10008 %}
10009
10010 instruct far_cmpI_reg_imm0_branch(cmpOp cmp, iRegI op1, immI0 zero, label lbl)
10011 %{
10012 match(If cmp (CmpI op1 zero));
10013
10014 effect(USE op1, USE lbl);
10015
10016 ins_cost(BRANCH_COST * 2);
10017
10018 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpI_reg_imm0_branch" %}
10019
10020 ins_encode %{
10021 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label), /* is_far */ true);
10022 %}
10023
10024 ins_pipe(pipe_cmpz_branch);
10025 %}
10026
10027 instruct far_cmpI_reg_imm0_loop(cmpOp cmp, iRegI op1, immI0 zero, label lbl)
10028 %{
10029 match(CountedLoopEnd cmp (CmpI op1 zero));
10030
10031 effect(USE op1, USE lbl);
10032
10033 ins_cost(BRANCH_COST * 2);
10034
10035 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpI_reg_imm0_loop" %}
10036
10037 ins_encode %{
10038 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label), /* is_far */ true);
10039 %}
10040
10041 ins_pipe(pipe_cmpz_branch);
10042 %}
10043
10044 instruct far_cmpUEqNeLeGt_imm0_branch(cmpOpUEqNeLeGt cmp, iRegI op1, immI0 zero, label lbl)
10045 %{
10046 match(If cmp (CmpU op1 zero));
10047
10048 effect(USE op1, USE lbl);
10049
10050 ins_cost(BRANCH_COST * 2);
10051
10052 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpUEqNeLeGt_imm0_branch" %}
10053
10054 ins_encode %{
10055 __ enc_cmpUEqNeLeGt_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
10056 %}
10057
10058 ins_pipe(pipe_cmpz_branch);
10059 %}
10060
10061 // compare lt/ge unsigned instructs has no short instruct with same match
10062 instruct far_cmpULtGe_reg_imm0_branch(cmpOpULtGe cmp, iRegI op1, immI0 zero, label lbl)
10063 %{
10064 match(If cmp (CmpU op1 zero));
10065
10066 effect(USE op1, USE lbl);
10067
10068 ins_cost(BRANCH_COST);
10069
10070 format %{ "j $lbl if $cmp == ge\t#@far_cmpULtGe_reg_imm0_branch" %}
10071
10072 ins_encode(riscv_enc_far_cmpULtGe_imm0_branch(cmp, op1, lbl));
10073
10074 ins_pipe(pipe_cmpz_branch);
10075 %}
10076
10077 instruct far_cmpL_reg_imm0_branch(cmpOp cmp, iRegL op1, immL0 zero, label lbl)
10078 %{
10079 match(If cmp (CmpL op1 zero));
10080
10081 effect(USE op1, USE lbl);
10082
10083 ins_cost(BRANCH_COST * 2);
10084
10085 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpL_reg_imm0_branch" %}
10086
10087 ins_encode %{
10088 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label), /* is_far */ true);
10089 %}
10090
10091 ins_pipe(pipe_cmpz_branch);
10092 %}
10093
10094 instruct far_cmpL_reg_imm0_loop(cmpOp cmp, iRegL op1, immL0 zero, label lbl)
10095 %{
10096 match(CountedLoopEnd cmp (CmpL op1 zero));
10097
10098 effect(USE op1, USE lbl);
10099
10100 ins_cost(BRANCH_COST * 2);
10101
10102 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpL_reg_imm0_loop" %}
10103
10104 ins_encode %{
10105 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label), /* is_far */ true);
10106 %}
10107
10108 ins_pipe(pipe_cmpz_branch);
10109 %}
10110
10111 instruct far_cmpULEqNeLeGt_reg_imm0_branch(cmpOpUEqNeLeGt cmp, iRegL op1, immL0 zero, label lbl)
10112 %{
10113 match(If cmp (CmpUL op1 zero));
10114
10115 effect(USE op1, USE lbl);
10116
10117 ins_cost(BRANCH_COST * 2);
10118
10119 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpULEqNeLeGt_reg_imm0_branch" %}
10120
10121 ins_encode %{
10122 __ enc_cmpUEqNeLeGt_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
10123 %}
10124
10125 ins_pipe(pipe_cmpz_branch);
10126 %}
10127
10128 // compare lt/ge unsigned instructs has no short instruct with same match
10129 instruct far_cmpULLtGe_reg_imm0_branch(cmpOpULtGe cmp, iRegL op1, immL0 zero, label lbl)
10130 %{
10131 match(If cmp (CmpUL op1 zero));
10132
10133 effect(USE op1, USE lbl);
10134
10135 ins_cost(BRANCH_COST);
10136
10137 format %{ "j $lbl if $cmp == ge\t#@far_cmpULLtGe_reg_imm0_branch" %}
10138
10139 ins_encode(riscv_enc_far_cmpULtGe_imm0_branch(cmp, op1, lbl));
10140
10141 ins_pipe(pipe_cmpz_branch);
10142 %}
10143
10144 instruct far_cmpP_imm0_branch(cmpOpEqNe cmp, iRegP op1, immP0 zero, label lbl) %{
10145 match(If cmp (CmpP op1 zero));
10146 effect(USE lbl);
10147
10148 ins_cost(BRANCH_COST * 2);
10149 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpP_imm0_branch" %}
10150
10151 ins_encode %{
10152 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
10153 %}
10154
10155 ins_pipe(pipe_cmpz_branch);
10156 %}
10157
10158 instruct far_cmpN_imm0_branch(cmpOpEqNe cmp, iRegN op1, immN0 zero, label lbl) %{
10159 match(If cmp (CmpN op1 zero));
10160 effect(USE lbl);
10161
10162 ins_cost(BRANCH_COST * 2);
10163
10164 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpN_imm0_branch" %}
10165
10166 ins_encode %{
10167 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
10168 %}
10169
10170 ins_pipe(pipe_cmpz_branch);
10171 %}
10172
10173 instruct far_cmpP_narrowOop_imm0_branch(cmpOpEqNe cmp, iRegN op1, immP0 zero, label lbl) %{
10174 match(If cmp (CmpP (DecodeN op1) zero));
10175 effect(USE lbl);
10176
10177 ins_cost(BRANCH_COST * 2);
10178 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpP_narrowOop_imm0_branch" %}
10179
10180 ins_encode %{
10181 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
10182 %}
10183
10184 ins_pipe(pipe_cmpz_branch);
10185 %}
10186
10187 // ============================================================================
10188 // Conditional Move Instructions
10189
10190 // --------- CMoveI ---------
10191
10192 instruct cmovI_cmpI(iRegINoSp dst, iRegI src, iRegI op1, iRegI op2, cmpOp cop) %{
10193 match(Set dst (CMoveI (Binary cop (CmpI op1 op2)) (Binary dst src)));
10194 ins_cost(ALU_COST + BRANCH_COST);
10195
10196 format %{
10197 "CMoveI $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpI\n\t"
10198 %}
10199
10200 ins_encode %{
10201 __ enc_cmove($cop$$cmpcode,
10202 as_Register($op1$$reg), as_Register($op2$$reg),
10203 as_Register($dst$$reg), as_Register($src$$reg));
10204 %}
10205
10206 ins_pipe(pipe_class_compare);
10207 %}
10208
10209 instruct cmovI_cmpU(iRegINoSp dst, iRegI src, iRegI op1, iRegI op2, cmpOpU cop) %{
10210 match(Set dst (CMoveI (Binary cop (CmpU op1 op2)) (Binary dst src)));
10211 ins_cost(ALU_COST + BRANCH_COST);
10212
10213 format %{
10214 "CMoveI $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpU\n\t"
10215 %}
10216
10217 ins_encode %{
10218 __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10219 as_Register($op1$$reg), as_Register($op2$$reg),
10220 as_Register($dst$$reg), as_Register($src$$reg));
10221 %}
10222
10223 ins_pipe(pipe_class_compare);
10224 %}
10225
10226 instruct cmovI_cmpL(iRegINoSp dst, iRegI src, iRegL op1, iRegL op2, cmpOp cop) %{
10227 match(Set dst (CMoveI (Binary cop (CmpL op1 op2)) (Binary dst src)));
10228 ins_cost(ALU_COST + BRANCH_COST);
10229
10230 format %{
10231 "CMoveI $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpL\n\t"
10232 %}
10233
10234 ins_encode %{
10235 __ enc_cmove($cop$$cmpcode,
10236 as_Register($op1$$reg), as_Register($op2$$reg),
10237 as_Register($dst$$reg), as_Register($src$$reg));
10238 %}
10239
10240 ins_pipe(pipe_class_compare);
10241 %}
10242
10243 instruct cmovI_cmpUL(iRegINoSp dst, iRegI src, iRegL op1, iRegL op2, cmpOpU cop) %{
10244 match(Set dst (CMoveI (Binary cop (CmpUL op1 op2)) (Binary dst src)));
10245 ins_cost(ALU_COST + BRANCH_COST);
10246
10247 format %{
10248 "CMoveI $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpUL\n\t"
10249 %}
10250
10251 ins_encode %{
10252 __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10253 as_Register($op1$$reg), as_Register($op2$$reg),
10254 as_Register($dst$$reg), as_Register($src$$reg));
10255 %}
10256
10257 ins_pipe(pipe_class_compare);
10258 %}
10259
10260 instruct cmovI_cmpF(iRegINoSp dst, iRegI src, fRegF op1, fRegF op2, cmpOp cop) %{
10261 match(Set dst (CMoveI (Binary cop (CmpF op1 op2)) (Binary dst src)));
10262 ins_cost(ALU_COST + BRANCH_COST);
10263
10264 format %{
10265 "CMoveI $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpF\n\t"
10266 %}
10267
10268 ins_encode %{
10269 __ enc_cmove_cmp_fp($cop$$cmpcode,
10270 as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg),
10271 as_Register($dst$$reg), as_Register($src$$reg), true /* is_single */);
10272 %}
10273
10274 ins_pipe(pipe_class_compare);
10275 %}
10276
10277 instruct cmovI_cmpD(iRegINoSp dst, iRegI src, fRegD op1, fRegD op2, cmpOp cop) %{
10278 match(Set dst (CMoveI (Binary cop (CmpD op1 op2)) (Binary dst src)));
10279 ins_cost(ALU_COST + BRANCH_COST);
10280
10281 format %{
10282 "CMoveI $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpD\n\t"
10283 %}
10284
10285 ins_encode %{
10286 __ enc_cmove_cmp_fp($cop$$cmpcode | C2_MacroAssembler::double_branch_mask,
10287 as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg),
10288 as_Register($dst$$reg), as_Register($src$$reg), false /* is_single */);
10289 %}
10290
10291 ins_pipe(pipe_class_compare);
10292 %}
10293
10294 instruct cmovI_cmpN(iRegINoSp dst, iRegI src, iRegN op1, iRegN op2, cmpOpU cop) %{
10295 match(Set dst (CMoveI (Binary cop (CmpN op1 op2)) (Binary dst src)));
10296 ins_cost(ALU_COST + BRANCH_COST);
10297
10298 format %{
10299 "CMoveI $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpN\n\t"
10300 %}
10301
10302 ins_encode %{
10303 __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10304 as_Register($op1$$reg), as_Register($op2$$reg),
10305 as_Register($dst$$reg), as_Register($src$$reg));
10306 %}
10307
10308 ins_pipe(pipe_class_compare);
10309 %}
10310
10311 instruct cmovI_cmpP(iRegINoSp dst, iRegI src, iRegP op1, iRegP op2, cmpOpU cop) %{
10312 match(Set dst (CMoveI (Binary cop (CmpP op1 op2)) (Binary dst src)));
10313 ins_cost(ALU_COST + BRANCH_COST);
10314
10315 format %{
10316 "CMoveI $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpP\n\t"
10317 %}
10318
10319 ins_encode %{
10320 __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10321 as_Register($op1$$reg), as_Register($op2$$reg),
10322 as_Register($dst$$reg), as_Register($src$$reg));
10323 %}
10324
10325 ins_pipe(pipe_class_compare);
10326 %}
10327
10328 // --------- CMoveL ---------
10329
10330 instruct cmovL_cmpL(iRegLNoSp dst, iRegL src, iRegL op1, iRegL op2, cmpOp cop) %{
10331 match(Set dst (CMoveL (Binary cop (CmpL op1 op2)) (Binary dst src)));
10332 ins_cost(ALU_COST + BRANCH_COST);
10333
10334 format %{
10335 "CMoveL $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpL\n\t"
10336 %}
10337
10338 ins_encode %{
10339 __ enc_cmove($cop$$cmpcode,
10340 as_Register($op1$$reg), as_Register($op2$$reg),
10341 as_Register($dst$$reg), as_Register($src$$reg));
10342 %}
10343
10344 ins_pipe(pipe_class_compare);
10345 %}
10346
10347 instruct cmovL_cmpUL(iRegLNoSp dst, iRegL src, iRegL op1, iRegL op2, cmpOpU cop) %{
10348 match(Set dst (CMoveL (Binary cop (CmpUL op1 op2)) (Binary dst src)));
10349 ins_cost(ALU_COST + BRANCH_COST);
10350
10351 format %{
10352 "CMoveL $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpUL\n\t"
10353 %}
10354
10355 ins_encode %{
10356 __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10357 as_Register($op1$$reg), as_Register($op2$$reg),
10358 as_Register($dst$$reg), as_Register($src$$reg));
10359 %}
10360
10361 ins_pipe(pipe_class_compare);
10362 %}
10363
10364 instruct cmovL_cmpI(iRegLNoSp dst, iRegL src, iRegI op1, iRegI op2, cmpOp cop) %{
10365 match(Set dst (CMoveL (Binary cop (CmpI op1 op2)) (Binary dst src)));
10366 ins_cost(ALU_COST + BRANCH_COST);
10367
10368 format %{
10369 "CMoveL $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpI\n\t"
10370 %}
10371
10372 ins_encode %{
10373 __ enc_cmove($cop$$cmpcode,
10374 as_Register($op1$$reg), as_Register($op2$$reg),
10375 as_Register($dst$$reg), as_Register($src$$reg));
10376 %}
10377
10378 ins_pipe(pipe_class_compare);
10379 %}
10380
10381 instruct cmovL_cmpU(iRegLNoSp dst, iRegL src, iRegI op1, iRegI op2, cmpOpU cop) %{
10382 match(Set dst (CMoveL (Binary cop (CmpU op1 op2)) (Binary dst src)));
10383 ins_cost(ALU_COST + BRANCH_COST);
10384
10385 format %{
10386 "CMoveL $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpU\n\t"
10387 %}
10388
10389 ins_encode %{
10390 __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10391 as_Register($op1$$reg), as_Register($op2$$reg),
10392 as_Register($dst$$reg), as_Register($src$$reg));
10393 %}
10394
10395 ins_pipe(pipe_class_compare);
10396 %}
10397
10398 instruct cmovL_cmpF(iRegLNoSp dst, iRegL src, fRegF op1, fRegF op2, cmpOp cop) %{
10399 match(Set dst (CMoveL (Binary cop (CmpF op1 op2)) (Binary dst src)));
10400 ins_cost(ALU_COST + BRANCH_COST);
10401
10402 format %{
10403 "CMoveL $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpF\n\t"
10404 %}
10405
10406 ins_encode %{
10407 __ enc_cmove_cmp_fp($cop$$cmpcode,
10408 as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg),
10409 as_Register($dst$$reg), as_Register($src$$reg), true /* is_single */);
10410 %}
10411
10412 ins_pipe(pipe_class_compare);
10413 %}
10414
10415 instruct cmovL_cmpD(iRegLNoSp dst, iRegL src, fRegD op1, fRegD op2, cmpOp cop) %{
10416 match(Set dst (CMoveL (Binary cop (CmpD op1 op2)) (Binary dst src)));
10417 ins_cost(ALU_COST + BRANCH_COST);
10418
10419 format %{
10420 "CMoveL $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpD\n\t"
10421 %}
10422
10423 ins_encode %{
10424 __ enc_cmove_cmp_fp($cop$$cmpcode | C2_MacroAssembler::double_branch_mask,
10425 as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg),
10426 as_Register($dst$$reg), as_Register($src$$reg), false /* is_single */);
10427 %}
10428
10429 ins_pipe(pipe_class_compare);
10430 %}
10431
10432 instruct cmovL_cmpN(iRegLNoSp dst, iRegL src, iRegN op1, iRegN op2, cmpOpU cop) %{
10433 match(Set dst (CMoveL (Binary cop (CmpN op1 op2)) (Binary dst src)));
10434 ins_cost(ALU_COST + BRANCH_COST);
10435
10436 format %{
10437 "CMoveL $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpN\n\t"
10438 %}
10439
10440 ins_encode %{
10441 __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10442 as_Register($op1$$reg), as_Register($op2$$reg),
10443 as_Register($dst$$reg), as_Register($src$$reg));
10444 %}
10445
10446 ins_pipe(pipe_class_compare);
10447 %}
10448
10449 instruct cmovL_cmpP(iRegLNoSp dst, iRegL src, iRegP op1, iRegP op2, cmpOpU cop) %{
10450 match(Set dst (CMoveL (Binary cop (CmpP op1 op2)) (Binary dst src)));
10451 ins_cost(ALU_COST + BRANCH_COST);
10452
10453 format %{
10454 "CMoveL $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpP\n\t"
10455 %}
10456
10457 ins_encode %{
10458 __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10459 as_Register($op1$$reg), as_Register($op2$$reg),
10460 as_Register($dst$$reg), as_Register($src$$reg));
10461 %}
10462
10463 ins_pipe(pipe_class_compare);
10464 %}
10465
10466 // ============================================================================
10467 // Procedure Call/Return Instructions
10468
10469 // Call Java Static Instruction
10470 // Note: If this code changes, the corresponding ret_addr_offset() and
10471 // compute_padding() functions will have to be adjusted.
10472 instruct CallStaticJavaDirect(method meth)
10473 %{
10474 match(CallStaticJava);
10475
10476 effect(USE meth);
10477
10478 ins_cost(BRANCH_COST);
10479
10480 format %{ "CALL,static $meth\t#@CallStaticJavaDirect" %}
10481
10482 ins_encode(riscv_enc_java_static_call(meth),
10483 riscv_enc_call_epilog);
10484
10485 ins_pipe(pipe_class_call);
10486 ins_alignment(4);
10487 %}
10488
10489 // TO HERE
10490
10491 // Call Java Dynamic Instruction
10492 // Note: If this code changes, the corresponding ret_addr_offset() and
10493 // compute_padding() functions will have to be adjusted.
10494 instruct CallDynamicJavaDirect(method meth)
10495 %{
10496 match(CallDynamicJava);
10497
10498 effect(USE meth);
10499
10500 ins_cost(BRANCH_COST + ALU_COST * 5);
10501
10502 format %{ "CALL,dynamic $meth\t#@CallDynamicJavaDirect" %}
10503
10504 ins_encode(riscv_enc_java_dynamic_call(meth),
10505 riscv_enc_call_epilog);
10506
10507 ins_pipe(pipe_class_call);
10508 ins_alignment(4);
10509 %}
10510
10511 // Call Runtime Instruction
10512
10513 instruct CallRuntimeDirect(method meth)
10514 %{
10515 match(CallRuntime);
10516
10517 effect(USE meth);
10518
10519 ins_cost(BRANCH_COST);
10520
10521 format %{ "CALL, runtime $meth\t#@CallRuntimeDirect" %}
10522
10523 ins_encode(riscv_enc_java_to_runtime(meth));
10524
10525 ins_pipe(pipe_class_call);
10526 ins_alignment(4);
10527 %}
10528
10529 // Call Runtime Instruction
10530
10531 instruct CallLeafDirect(method meth)
10532 %{
10533 match(CallLeaf);
10534
10535 effect(USE meth);
10536
10537 ins_cost(BRANCH_COST);
10538
10539 format %{ "CALL, runtime leaf $meth\t#@CallLeafDirect" %}
10540
10541 ins_encode(riscv_enc_java_to_runtime(meth));
10542
10543 ins_pipe(pipe_class_call);
10544 ins_alignment(4);
10545 %}
10546
10547 // Call Runtime Instruction without safepoint and with vector arguments
10548
10549 instruct CallLeafDirectVector(method meth)
10550 %{
10551 match(CallLeafVector);
10552
10553 effect(USE meth);
10554
10555 ins_cost(BRANCH_COST);
10556
10557 format %{ "CALL, runtime leaf vector $meth" %}
10558
10559 ins_encode(riscv_enc_java_to_runtime(meth));
10560
10561 ins_pipe(pipe_class_call);
10562 ins_alignment(4);
10563 %}
10564
10565 // Call Runtime Instruction
10566
10567 instruct CallLeafNoFPDirect(method meth)
10568 %{
10569 match(CallLeafNoFP);
10570
10571 effect(USE meth);
10572
10573 ins_cost(BRANCH_COST);
10574
10575 format %{ "CALL, runtime leaf nofp $meth\t#@CallLeafNoFPDirect" %}
10576
10577 ins_encode(riscv_enc_java_to_runtime(meth));
10578
10579 ins_pipe(pipe_class_call);
10580 ins_alignment(4);
10581 %}
10582
10583 // ============================================================================
10584 // Partial Subtype Check
10585 //
10586 // superklass array for an instance of the superklass. Set a hidden
10587 // internal cache on a hit (cache is checked with exposed code in
10588 // gen_subtype_check()). Return zero for a hit. The encoding
10589 // ALSO sets flags.
10590
10591 instruct partialSubtypeCheck(iRegP_R15 result, iRegP_R14 sub, iRegP_R10 super, iRegP_R12 tmp, rFlagsReg cr)
10592 %{
10593 predicate(!UseSecondarySupersTable);
10594 match(Set result (PartialSubtypeCheck sub super));
10595 effect(KILL tmp, KILL cr);
10596
10597 ins_cost(20 * DEFAULT_COST);
10598 format %{ "partialSubtypeCheck $result, $sub, $super\t#@partialSubtypeCheck" %}
10599
10600 ins_encode(riscv_enc_partial_subtype_check(sub, super, tmp, result));
10601
10602 opcode(0x1); // Force zero of result reg on hit
10603
10604 ins_pipe(pipe_class_memory);
10605 %}
10606
10607 // Two versions of partialSubtypeCheck, both used when we need to
10608 // search for a super class in the secondary supers array. The first
10609 // is used when we don't know _a priori_ the class being searched
10610 // for. The second, far more common, is used when we do know: this is
10611 // used for instanceof, checkcast, and any case where C2 can determine
10612 // it by constant propagation.
10613
10614 instruct partialSubtypeCheckVarSuper(iRegP_R14 sub, iRegP_R10 super, iRegP_R15 result,
10615 iRegP_R11 tmpR11, iRegP_R12 tmpR12, iRegP_R13 tmpR13,
10616 iRegP_R16 tmpR16, rFlagsReg cr)
10617 %{
10618 predicate(UseSecondarySupersTable);
10619 match(Set result (PartialSubtypeCheck sub super));
10620 effect(TEMP tmpR11, TEMP tmpR12, TEMP tmpR13, TEMP tmpR16, KILL cr);
10621
10622 ins_cost(10 * DEFAULT_COST); // slightly larger than the next version
10623 format %{ "partialSubtypeCheck $result, $sub, $super" %}
10624
10625 ins_encode %{
10626 __ lookup_secondary_supers_table_var($sub$$Register, $super$$Register, $result$$Register,
10627 $tmpR11$$Register, $tmpR12$$Register, $tmpR13$$Register,
10628 $tmpR16$$Register, nullptr /*L_success*/);
10629 %}
10630
10631 ins_pipe(pipe_class_memory);
10632 %}
10633
10634 instruct partialSubtypeCheckConstSuper(iRegP_R14 sub, iRegP_R10 super_reg, immP super_con, iRegP_R15 result,
10635 iRegP_R11 tmpR11, iRegP_R12 tmpR12, iRegP_R13 tmpR13, iRegP_R16 tmpR16, rFlagsReg cr)
10636 %{
10637 predicate(UseSecondarySupersTable);
10638 match(Set result (PartialSubtypeCheck sub (Binary super_reg super_con)));
10639 effect(TEMP tmpR11, TEMP tmpR12, TEMP tmpR13, TEMP tmpR16, KILL cr);
10640
10641 ins_cost(5 * DEFAULT_COST); // needs to be less than competing nodes
10642 format %{ "partialSubtypeCheck $result, $sub, $super_reg, $super_con" %}
10643
10644 ins_encode %{
10645 bool success = false;
10646 u1 super_klass_slot = ((Klass*)$super_con$$constant)->hash_slot();
10647 if (InlineSecondarySupersTest) {
10648 success = __ lookup_secondary_supers_table_const($sub$$Register, $super_reg$$Register, $result$$Register,
10649 $tmpR11$$Register, $tmpR12$$Register, $tmpR13$$Register,
10650 $tmpR16$$Register, super_klass_slot);
10651 } else {
10652 address call = __ reloc_call(RuntimeAddress(StubRoutines::lookup_secondary_supers_table_stub(super_klass_slot)));
10653 success = (call != nullptr);
10654 }
10655 if (!success) {
10656 ciEnv::current()->record_failure("CodeCache is full");
10657 return;
10658 }
10659 %}
10660
10661 ins_pipe(pipe_class_memory);
10662 %}
10663
10664 instruct string_compareU(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
10665 iRegI_R10 result, iRegP_R28 tmp1, iRegL_R29 tmp2, iRegL_R30 tmp3, rFlagsReg cr)
10666 %{
10667 predicate(!UseRVV && ((StrCompNode *)n)->encoding() == StrIntrinsicNode::UU);
10668 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10669 effect(KILL tmp1, KILL tmp2, KILL tmp3, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
10670
10671 format %{ "String Compare $str1, $cnt1, $str2, $cnt2 -> $result\t#@string_compareU" %}
10672 ins_encode %{
10673 // Count is in 8-bit bytes; non-Compact chars are 16 bits.
10674 __ string_compare($str1$$Register, $str2$$Register,
10675 $cnt1$$Register, $cnt2$$Register, $result$$Register,
10676 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
10677 StrIntrinsicNode::UU);
10678 %}
10679 ins_pipe(pipe_class_memory);
10680 %}
10681
10682 instruct string_compareL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
10683 iRegI_R10 result, iRegP_R28 tmp1, iRegL_R29 tmp2, iRegL_R30 tmp3, rFlagsReg cr)
10684 %{
10685 predicate(!UseRVV && ((StrCompNode *)n)->encoding() == StrIntrinsicNode::LL);
10686 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10687 effect(KILL tmp1, KILL tmp2, KILL tmp3, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
10688
10689 format %{ "String Compare $str1, $cnt1, $str2, $cnt2 -> $result\t#@string_compareL" %}
10690 ins_encode %{
10691 __ string_compare($str1$$Register, $str2$$Register,
10692 $cnt1$$Register, $cnt2$$Register, $result$$Register,
10693 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
10694 StrIntrinsicNode::LL);
10695 %}
10696 ins_pipe(pipe_class_memory);
10697 %}
10698
10699 instruct string_compareUL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
10700 iRegI_R10 result, iRegP_R28 tmp1, iRegL_R29 tmp2, iRegL_R30 tmp3, rFlagsReg cr)
10701 %{
10702 predicate(!UseRVV && ((StrCompNode *)n)->encoding() == StrIntrinsicNode::UL);
10703 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10704 effect(KILL tmp1, KILL tmp2, KILL tmp3, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
10705
10706 format %{"String Compare $str1, $cnt1, $str2, $cnt2 -> $result\t#@string_compareUL" %}
10707 ins_encode %{
10708 __ string_compare($str1$$Register, $str2$$Register,
10709 $cnt1$$Register, $cnt2$$Register, $result$$Register,
10710 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
10711 StrIntrinsicNode::UL);
10712 %}
10713 ins_pipe(pipe_class_memory);
10714 %}
10715
10716 instruct string_compareLU(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
10717 iRegI_R10 result, iRegP_R28 tmp1, iRegL_R29 tmp2, iRegL_R30 tmp3,
10718 rFlagsReg cr)
10719 %{
10720 predicate(!UseRVV && ((StrCompNode *)n)->encoding() == StrIntrinsicNode::LU);
10721 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10722 effect(KILL tmp1, KILL tmp2, KILL tmp3, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
10723
10724 format %{ "String Compare $str1, $cnt1, $str2, $cnt2 -> $result\t#@string_compareLU" %}
10725 ins_encode %{
10726 __ string_compare($str1$$Register, $str2$$Register,
10727 $cnt1$$Register, $cnt2$$Register, $result$$Register,
10728 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
10729 StrIntrinsicNode::LU);
10730 %}
10731 ins_pipe(pipe_class_memory);
10732 %}
10733
10734 instruct string_indexofUU(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
10735 iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3,
10736 iRegINoSp tmp4, iRegINoSp tmp5, iRegINoSp tmp6, rFlagsReg cr)
10737 %{
10738 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU);
10739 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
10740 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, TEMP_DEF result,
10741 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, TEMP tmp6, KILL cr);
10742
10743 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result (UU)" %}
10744 ins_encode %{
10745 __ string_indexof($str1$$Register, $str2$$Register,
10746 $cnt1$$Register, $cnt2$$Register,
10747 $tmp1$$Register, $tmp2$$Register,
10748 $tmp3$$Register, $tmp4$$Register,
10749 $tmp5$$Register, $tmp6$$Register,
10750 $result$$Register, StrIntrinsicNode::UU);
10751 %}
10752 ins_pipe(pipe_class_memory);
10753 %}
10754
10755 instruct string_indexofLL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
10756 iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3,
10757 iRegINoSp tmp4, iRegINoSp tmp5, iRegINoSp tmp6, rFlagsReg cr)
10758 %{
10759 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL);
10760 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
10761 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, TEMP_DEF result,
10762 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, TEMP tmp6, KILL cr);
10763
10764 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result (LL)" %}
10765 ins_encode %{
10766 __ string_indexof($str1$$Register, $str2$$Register,
10767 $cnt1$$Register, $cnt2$$Register,
10768 $tmp1$$Register, $tmp2$$Register,
10769 $tmp3$$Register, $tmp4$$Register,
10770 $tmp5$$Register, $tmp6$$Register,
10771 $result$$Register, StrIntrinsicNode::LL);
10772 %}
10773 ins_pipe(pipe_class_memory);
10774 %}
10775
10776 instruct string_indexofUL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
10777 iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3,
10778 iRegINoSp tmp4, iRegINoSp tmp5, iRegINoSp tmp6, rFlagsReg cr)
10779 %{
10780 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL);
10781 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
10782 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, TEMP_DEF result,
10783 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, TEMP tmp6, KILL cr);
10784 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result (UL)" %}
10785
10786 ins_encode %{
10787 __ string_indexof($str1$$Register, $str2$$Register,
10788 $cnt1$$Register, $cnt2$$Register,
10789 $tmp1$$Register, $tmp2$$Register,
10790 $tmp3$$Register, $tmp4$$Register,
10791 $tmp5$$Register, $tmp6$$Register,
10792 $result$$Register, StrIntrinsicNode::UL);
10793 %}
10794 ins_pipe(pipe_class_memory);
10795 %}
10796
10797 instruct string_indexof_conUU(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2,
10798 immI_le_4 int_cnt2, iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2,
10799 iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
10800 %{
10801 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU);
10802 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
10803 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, TEMP_DEF result,
10804 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
10805
10806 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result (UU)" %}
10807
10808 ins_encode %{
10809 int icnt2 = (int)$int_cnt2$$constant;
10810 __ string_indexof_linearscan($str1$$Register, $str2$$Register,
10811 $cnt1$$Register, zr,
10812 $tmp1$$Register, $tmp2$$Register,
10813 $tmp3$$Register, $tmp4$$Register,
10814 icnt2, $result$$Register, StrIntrinsicNode::UU);
10815 %}
10816 ins_pipe(pipe_class_memory);
10817 %}
10818
10819 instruct string_indexof_conLL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2,
10820 immI_le_4 int_cnt2, iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2,
10821 iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
10822 %{
10823 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL);
10824 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
10825 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, TEMP_DEF result,
10826 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
10827
10828 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result (LL)" %}
10829 ins_encode %{
10830 int icnt2 = (int)$int_cnt2$$constant;
10831 __ string_indexof_linearscan($str1$$Register, $str2$$Register,
10832 $cnt1$$Register, zr,
10833 $tmp1$$Register, $tmp2$$Register,
10834 $tmp3$$Register, $tmp4$$Register,
10835 icnt2, $result$$Register, StrIntrinsicNode::LL);
10836 %}
10837 ins_pipe(pipe_class_memory);
10838 %}
10839
10840 instruct string_indexof_conUL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2,
10841 immI_1 int_cnt2, iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2,
10842 iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
10843 %{
10844 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL);
10845 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
10846 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, TEMP_DEF result,
10847 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
10848
10849 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result (UL)" %}
10850 ins_encode %{
10851 int icnt2 = (int)$int_cnt2$$constant;
10852 __ string_indexof_linearscan($str1$$Register, $str2$$Register,
10853 $cnt1$$Register, zr,
10854 $tmp1$$Register, $tmp2$$Register,
10855 $tmp3$$Register, $tmp4$$Register,
10856 icnt2, $result$$Register, StrIntrinsicNode::UL);
10857 %}
10858 ins_pipe(pipe_class_memory);
10859 %}
10860
10861 instruct stringU_indexof_char(iRegP_R11 str1, iRegI_R12 cnt1, iRegI_R13 ch,
10862 iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2,
10863 iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
10864 %{
10865 match(Set result (StrIndexOfChar (Binary str1 cnt1) ch));
10866 predicate(!UseRVV && (((StrIndexOfCharNode*)n)->encoding() == StrIntrinsicNode::U));
10867 effect(USE_KILL str1, USE_KILL cnt1, USE_KILL ch, TEMP_DEF result,
10868 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
10869
10870 format %{ "StringUTF16 IndexOf char[] $str1, $cnt1, $ch -> $result" %}
10871 ins_encode %{
10872 __ string_indexof_char($str1$$Register, $cnt1$$Register, $ch$$Register,
10873 $result$$Register, $tmp1$$Register, $tmp2$$Register,
10874 $tmp3$$Register, $tmp4$$Register, false /* isU */);
10875 %}
10876 ins_pipe(pipe_class_memory);
10877 %}
10878
10879
10880 instruct stringL_indexof_char(iRegP_R11 str1, iRegI_R12 cnt1, iRegI_R13 ch,
10881 iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2,
10882 iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
10883 %{
10884 match(Set result (StrIndexOfChar (Binary str1 cnt1) ch));
10885 predicate(!UseRVV && (((StrIndexOfCharNode*)n)->encoding() == StrIntrinsicNode::L));
10886 effect(USE_KILL str1, USE_KILL cnt1, USE_KILL ch, TEMP_DEF result,
10887 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
10888
10889 format %{ "StringLatin1 IndexOf char[] $str1, $cnt1, $ch -> $result" %}
10890 ins_encode %{
10891 __ string_indexof_char($str1$$Register, $cnt1$$Register, $ch$$Register,
10892 $result$$Register, $tmp1$$Register, $tmp2$$Register,
10893 $tmp3$$Register, $tmp4$$Register, true /* isL */);
10894 %}
10895 ins_pipe(pipe_class_memory);
10896 %}
10897
10898 // clearing of an array
10899 instruct clearArray_reg_reg(iRegL_R29 cnt, iRegP_R28 base, iRegP_R30 tmp1,
10900 iRegP_R31 tmp2, rFlagsReg cr, Universe dummy)
10901 %{
10902 // temp registers must match the one used in StubGenerator::generate_zero_blocks()
10903 predicate(UseBlockZeroing || !UseRVV);
10904 match(Set dummy (ClearArray cnt base));
10905 effect(USE_KILL cnt, USE_KILL base, TEMP tmp1, TEMP tmp2, KILL cr);
10906
10907 ins_cost(4 * DEFAULT_COST);
10908 format %{ "ClearArray $cnt, $base\t#@clearArray_reg_reg" %}
10909
10910 ins_encode %{
10911 address tpc = __ zero_words($base$$Register, $cnt$$Register);
10912 if (tpc == nullptr) {
10913 ciEnv::current()->record_failure("CodeCache is full");
10914 return;
10915 }
10916 %}
10917
10918 ins_pipe(pipe_class_memory);
10919 %}
10920
10921 instruct clearArray_imm_reg(immL cnt, iRegP_R28 base, Universe dummy, rFlagsReg cr)
10922 %{
10923 predicate(!UseRVV && (uint64_t)n->in(2)->get_long()
10924 < (uint64_t)(BlockZeroingLowLimit >> LogBytesPerWord));
10925 match(Set dummy (ClearArray cnt base));
10926 effect(USE_KILL base, KILL cr);
10927
10928 ins_cost(4 * DEFAULT_COST);
10929 format %{ "ClearArray $cnt, $base\t#@clearArray_imm_reg" %}
10930
10931 ins_encode %{
10932 __ zero_words($base$$Register, (uint64_t)$cnt$$constant);
10933 %}
10934
10935 ins_pipe(pipe_class_memory);
10936 %}
10937
10938 instruct string_equalsL(iRegP_R11 str1, iRegP_R13 str2, iRegI_R14 cnt,
10939 iRegI_R10 result, rFlagsReg cr)
10940 %{
10941 predicate(!UseRVV && ((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::LL);
10942 match(Set result (StrEquals (Binary str1 str2) cnt));
10943 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL cr);
10944
10945 format %{ "String Equals $str1, $str2, $cnt -> $result\t#@string_equalsL" %}
10946 ins_encode %{
10947 // Count is in 8-bit bytes; non-Compact chars are 16 bits.
10948 __ string_equals($str1$$Register, $str2$$Register,
10949 $result$$Register, $cnt$$Register);
10950 %}
10951 ins_pipe(pipe_class_memory);
10952 %}
10953
10954 instruct array_equalsB(iRegP_R11 ary1, iRegP_R12 ary2, iRegI_R10 result,
10955 iRegP_R13 tmp1, iRegP_R14 tmp2, iRegP_R15 tmp3)
10956 %{
10957 predicate(!UseRVV && ((AryEqNode*)n)->encoding() == StrIntrinsicNode::LL);
10958 match(Set result (AryEq ary1 ary2));
10959 effect(USE_KILL ary1, USE_KILL ary2, TEMP tmp1, TEMP tmp2, TEMP tmp3);
10960
10961 format %{ "Array Equals $ary1, $ary2 -> $result\t#@array_equalsB // KILL all" %}
10962 ins_encode %{
10963 __ arrays_equals($ary1$$Register, $ary2$$Register,
10964 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
10965 $result$$Register, 1);
10966 %}
10967 ins_pipe(pipe_class_memory);
10968 %}
10969
10970 instruct array_equalsC(iRegP_R11 ary1, iRegP_R12 ary2, iRegI_R10 result,
10971 iRegP_R13 tmp1, iRegP_R14 tmp2, iRegP_R15 tmp3)
10972 %{
10973 predicate(!UseRVV && ((AryEqNode*)n)->encoding() == StrIntrinsicNode::UU);
10974 match(Set result (AryEq ary1 ary2));
10975 effect(USE_KILL ary1, USE_KILL ary2, TEMP tmp1, TEMP tmp2, TEMP tmp3);
10976
10977 format %{ "Array Equals $ary1, $ary2 -> $result\t#@array_equalsC // KILL all" %}
10978 ins_encode %{
10979 __ arrays_equals($ary1$$Register, $ary2$$Register,
10980 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
10981 $result$$Register, 2);
10982 %}
10983 ins_pipe(pipe_class_memory);
10984 %}
10985
10986 // fast ArraysSupport.vectorizedHashCode
10987 instruct arrays_hashcode(iRegP_R11 ary, iRegI_R12 cnt, iRegI_R10 result, immI basic_type,
10988 iRegLNoSp tmp1, iRegLNoSp tmp2,
10989 iRegLNoSp tmp3, iRegLNoSp tmp4,
10990 iRegLNoSp tmp5, iRegLNoSp tmp6, rFlagsReg cr)
10991 %{
10992 predicate(!UseRVV);
10993 match(Set result (VectorizedHashCode (Binary ary cnt) (Binary result basic_type)));
10994 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, TEMP tmp6,
10995 USE_KILL ary, USE_KILL cnt, USE basic_type, KILL cr);
10996
10997 format %{ "Array HashCode array[] $ary,$cnt,$result,$basic_type -> $result // KILL all" %}
10998 ins_encode %{
10999 __ arrays_hashcode($ary$$Register, $cnt$$Register, $result$$Register,
11000 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
11001 $tmp4$$Register, $tmp5$$Register, $tmp6$$Register,
11002 (BasicType)$basic_type$$constant);
11003 %}
11004 ins_pipe(pipe_class_memory);
11005 %}
11006
11007 // ============================================================================
11008 // Safepoint Instructions
11009
11010 instruct safePoint(iRegP poll)
11011 %{
11012 match(SafePoint poll);
11013
11014 ins_cost(2 * LOAD_COST);
11015 format %{
11016 "lwu zr, [$poll]\t# Safepoint: poll for GC, #@safePoint"
11017 %}
11018 ins_encode %{
11019 __ read_polling_page(as_Register($poll$$reg), 0, relocInfo::poll_type);
11020 %}
11021 ins_pipe(pipe_serial); // ins_pipe(iload_reg_mem);
11022 %}
11023
11024 // ============================================================================
11025 // This name is KNOWN by the ADLC and cannot be changed.
11026 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
11027 // for this guy.
11028 instruct tlsLoadP(javaThread_RegP dst)
11029 %{
11030 match(Set dst (ThreadLocal));
11031
11032 ins_cost(0);
11033
11034 format %{ " -- \t// $dst=Thread::current(), empty, #@tlsLoadP" %}
11035
11036 size(0);
11037
11038 ins_encode( /*empty*/ );
11039
11040 ins_pipe(pipe_class_empty);
11041 %}
11042
11043 // inlined locking and unlocking
11044 // using t1 as the 'flag' register to bridge the BoolNode producers and consumers
11045 instruct cmpFastLock(rFlagsReg cr, iRegP object, iRegP box,
11046 iRegPNoSp tmp1, iRegPNoSp tmp2, iRegPNoSp tmp3, iRegPNoSp tmp4)
11047 %{
11048 match(Set cr (FastLock object box));
11049 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4);
11050
11051 ins_cost(10 * DEFAULT_COST);
11052 format %{ "fastlock $object,$box\t! kills $tmp1,$tmp2,$tmp3,$tmp4 #@cmpFastLock" %}
11053
11054 ins_encode %{
11055 __ fast_lock($object$$Register, $box$$Register,
11056 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register);
11057 %}
11058
11059 ins_pipe(pipe_serial);
11060 %}
11061
11062 // using t1 as the 'flag' register to bridge the BoolNode producers and consumers
11063 instruct cmpFastUnlock(rFlagsReg cr, iRegP object, iRegP box,
11064 iRegPNoSp tmp1, iRegPNoSp tmp2, iRegPNoSp tmp3)
11065 %{
11066 match(Set cr (FastUnlock object box));
11067 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3);
11068
11069 ins_cost(10 * DEFAULT_COST);
11070 format %{ "fastunlock $object,$box\t! kills $tmp1,$tmp2,$tmp3 #@cmpFastUnlock" %}
11071
11072 ins_encode %{
11073 __ fast_unlock($object$$Register, $box$$Register,
11074 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
11075 %}
11076
11077 ins_pipe(pipe_serial);
11078 %}
11079
11080 // Tail Call; Jump from runtime stub to Java code.
11081 // Also known as an 'interprocedural jump'.
11082 // Target of jump will eventually return to caller.
11083 // TailJump below removes the return address.
11084 // Don't use fp for 'jump_target' because a MachEpilogNode has already been
11085 // emitted just above the TailCall which has reset fp to the caller state.
11086 instruct TailCalljmpInd(iRegPNoSpNoFp jump_target, inline_cache_RegP method_oop)
11087 %{
11088 match(TailCall jump_target method_oop);
11089
11090 ins_cost(BRANCH_COST);
11091
11092 format %{ "jalr $jump_target\t# $method_oop holds method oop, #@TailCalljmpInd." %}
11093
11094 ins_encode(riscv_enc_tail_call(jump_target));
11095
11096 ins_pipe(pipe_class_call);
11097 %}
11098
11099 instruct TailjmpInd(iRegPNoSpNoFp jump_target, iRegP_R10 ex_oop)
11100 %{
11101 match(TailJump jump_target ex_oop);
11102
11103 ins_cost(ALU_COST + BRANCH_COST);
11104
11105 format %{ "jalr $jump_target\t# $ex_oop holds exception oop, #@TailjmpInd." %}
11106
11107 ins_encode(riscv_enc_tail_jmp(jump_target));
11108
11109 ins_pipe(pipe_class_call);
11110 %}
11111
11112 // Forward exception.
11113 instruct ForwardExceptionjmp()
11114 %{
11115 match(ForwardException);
11116
11117 ins_cost(BRANCH_COST);
11118
11119 format %{ "j forward_exception_stub\t#@ForwardException" %}
11120
11121 ins_encode %{
11122 __ far_jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
11123 %}
11124
11125 ins_pipe(pipe_class_call);
11126 %}
11127
11128 // Create exception oop: created by stack-crawling runtime code.
11129 // Created exception is now available to this handler, and is setup
11130 // just prior to jumping to this handler. No code emitted.
11131 instruct CreateException(iRegP_R10 ex_oop)
11132 %{
11133 match(Set ex_oop (CreateEx));
11134
11135 ins_cost(0);
11136 format %{ " -- \t// exception oop; no code emitted, #@CreateException" %}
11137
11138 size(0);
11139
11140 ins_encode( /*empty*/ );
11141
11142 ins_pipe(pipe_class_empty);
11143 %}
11144
11145 // Rethrow exception: The exception oop will come in the first
11146 // argument position. Then JUMP (not call) to the rethrow stub code.
11147 instruct RethrowException()
11148 %{
11149 match(Rethrow);
11150
11151 ins_cost(BRANCH_COST);
11152
11153 format %{ "j rethrow_stub\t#@RethrowException" %}
11154
11155 ins_encode(riscv_enc_rethrow());
11156
11157 ins_pipe(pipe_class_call);
11158 %}
11159
11160 // Return Instruction
11161 // epilog node loads ret address into ra as part of frame pop
11162 instruct Ret()
11163 %{
11164 match(Return);
11165
11166 ins_cost(BRANCH_COST);
11167 format %{ "ret\t// return register, #@Ret" %}
11168
11169 ins_encode(riscv_enc_ret());
11170
11171 ins_pipe(pipe_branch);
11172 %}
11173
11174 // Die now.
11175 instruct ShouldNotReachHere() %{
11176 match(Halt);
11177
11178 ins_cost(BRANCH_COST);
11179
11180 format %{ "#@ShouldNotReachHere" %}
11181
11182 ins_encode %{
11183 if (is_reachable()) {
11184 const char* str = __ code_string(_halt_reason);
11185 __ stop(str);
11186 }
11187 %}
11188
11189 ins_pipe(pipe_class_default);
11190 %}
11191
11192
11193 //----------PEEPHOLE RULES-----------------------------------------------------
11194 // These must follow all instruction definitions as they use the names
11195 // defined in the instructions definitions.
11196 //
11197 // peepmatch ( root_instr_name [preceding_instruction]* );
11198 //
11199 // peepconstraint %{
11200 // (instruction_number.operand_name relational_op instruction_number.operand_name
11201 // [, ...] );
11202 // // instruction numbers are zero-based using left to right order in peepmatch
11203 //
11204 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
11205 // // provide an instruction_number.operand_name for each operand that appears
11206 // // in the replacement instruction's match rule
11207 //
11208 // ---------VM FLAGS---------------------------------------------------------
11209 //
11210 // All peephole optimizations can be turned off using -XX:-OptoPeephole
11211 //
11212 // Each peephole rule is given an identifying number starting with zero and
11213 // increasing by one in the order seen by the parser. An individual peephole
11214 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
11215 // on the command-line.
11216 //
11217 // ---------CURRENT LIMITATIONS----------------------------------------------
11218 //
11219 // Only match adjacent instructions in same basic block
11220 // Only equality constraints
11221 // Only constraints between operands, not (0.dest_reg == RAX_enc)
11222 // Only one replacement instruction
11223 //
11224 //----------SMARTSPILL RULES---------------------------------------------------
11225 // These must follow all instruction definitions as they use the names
11226 // defined in the instructions definitions.
11227
11228 // Local Variables:
11229 // mode: c++
11230 // End: