1 //
2 // Copyright (c) 2003, 2024, Oracle and/or its affiliates. All rights reserved.
3 // Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
4 // Copyright (c) 2020, 2024, Huawei Technologies Co., Ltd. All rights reserved.
5 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
6 //
7 // This code is free software; you can redistribute it and/or modify it
8 // under the terms of the GNU General Public License version 2 only, as
9 // published by the Free Software Foundation.
10 //
11 // This code is distributed in the hope that it will be useful, but WITHOUT
12 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 // version 2 for more details (a copy is included in the LICENSE file that
15 // accompanied this code).
16 //
17 // You should have received a copy of the GNU General Public License version
18 // 2 along with this work; if not, write to the Free Software Foundation,
19 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
20 //
21 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
22 // or visit www.oracle.com if you need additional information or have any
23 // questions.
24 //
25 //
26
27 // RISCV Architecture Description File
28
29 //----------REGISTER DEFINITION BLOCK------------------------------------------
30 // This information is used by the matcher and the register allocator to
31 // describe individual registers and classes of registers within the target
32 // architecture.
33
34 register %{
35 //----------Architecture Description Register Definitions----------------------
36 // General Registers
37 // "reg_def" name ( register save type, C convention save type,
38 // ideal register type, encoding );
39 // Register Save Types:
40 //
41 // NS = No-Save: The register allocator assumes that these registers
42 // can be used without saving upon entry to the method, &
43 // that they do not need to be saved at call sites.
44 //
45 // SOC = Save-On-Call: The register allocator assumes that these registers
46 // can be used without saving upon entry to the method,
47 // but that they must be saved at call sites.
48 //
49 // SOE = Save-On-Entry: The register allocator assumes that these registers
50 // must be saved before using them upon entry to the
51 // method, but they do not need to be saved at call
52 // sites.
53 //
54 // AS = Always-Save: The register allocator assumes that these registers
55 // must be saved before using them upon entry to the
56 // method, & that they must be saved at call sites.
57 //
58 // Ideal Register Type is used to determine how to save & restore a
59 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
60 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
61 //
62 // The encoding number is the actual bit-pattern placed into the opcodes.
63
64 // We must define the 64 bit int registers in two 32 bit halves, the
65 // real lower register and a virtual upper half register. upper halves
66 // are used by the register allocator but are not actually supplied as
67 // operands to memory ops.
68 //
69 // follow the C1 compiler in making registers
70 //
71 // x7, x9-x17, x27-x31 volatile (caller save)
72 // x0-x4, x8, x23 system (no save, no allocate)
73 // x5-x6 non-allocatable (so we can use them as temporary regs)
74
75 //
76 // as regards Java usage. we don't use any callee save registers
77 // because this makes it difficult to de-optimise a frame (see comment
78 // in x86 implementation of Deoptimization::unwind_callee_save_values)
79 //
80
81 // General Registers
82
83 reg_def R0 ( NS, NS, Op_RegI, 0, x0->as_VMReg() ); // zr
84 reg_def R0_H ( NS, NS, Op_RegI, 0, x0->as_VMReg()->next() );
85 reg_def R1 ( NS, SOC, Op_RegI, 1, x1->as_VMReg() ); // ra
86 reg_def R1_H ( NS, SOC, Op_RegI, 1, x1->as_VMReg()->next() );
87 reg_def R2 ( NS, NS, Op_RegI, 2, x2->as_VMReg() ); // sp
88 reg_def R2_H ( NS, NS, Op_RegI, 2, x2->as_VMReg()->next() );
89 reg_def R3 ( NS, NS, Op_RegI, 3, x3->as_VMReg() ); // gp
90 reg_def R3_H ( NS, NS, Op_RegI, 3, x3->as_VMReg()->next() );
91 reg_def R4 ( NS, NS, Op_RegI, 4, x4->as_VMReg() ); // tp
92 reg_def R4_H ( NS, NS, Op_RegI, 4, x4->as_VMReg()->next() );
93 reg_def R7 ( SOC, SOC, Op_RegI, 7, x7->as_VMReg() );
94 reg_def R7_H ( SOC, SOC, Op_RegI, 7, x7->as_VMReg()->next() );
95 reg_def R8 ( NS, SOE, Op_RegI, 8, x8->as_VMReg() ); // fp
96 reg_def R8_H ( NS, SOE, Op_RegI, 8, x8->as_VMReg()->next() );
97 reg_def R9 ( SOC, SOE, Op_RegI, 9, x9->as_VMReg() );
98 reg_def R9_H ( SOC, SOE, Op_RegI, 9, x9->as_VMReg()->next() );
99 reg_def R10 ( SOC, SOC, Op_RegI, 10, x10->as_VMReg() );
100 reg_def R10_H ( SOC, SOC, Op_RegI, 10, x10->as_VMReg()->next());
101 reg_def R11 ( SOC, SOC, Op_RegI, 11, x11->as_VMReg() );
102 reg_def R11_H ( SOC, SOC, Op_RegI, 11, x11->as_VMReg()->next());
103 reg_def R12 ( SOC, SOC, Op_RegI, 12, x12->as_VMReg() );
104 reg_def R12_H ( SOC, SOC, Op_RegI, 12, x12->as_VMReg()->next());
105 reg_def R13 ( SOC, SOC, Op_RegI, 13, x13->as_VMReg() );
106 reg_def R13_H ( SOC, SOC, Op_RegI, 13, x13->as_VMReg()->next());
107 reg_def R14 ( SOC, SOC, Op_RegI, 14, x14->as_VMReg() );
108 reg_def R14_H ( SOC, SOC, Op_RegI, 14, x14->as_VMReg()->next());
109 reg_def R15 ( SOC, SOC, Op_RegI, 15, x15->as_VMReg() );
110 reg_def R15_H ( SOC, SOC, Op_RegI, 15, x15->as_VMReg()->next());
111 reg_def R16 ( SOC, SOC, Op_RegI, 16, x16->as_VMReg() );
112 reg_def R16_H ( SOC, SOC, Op_RegI, 16, x16->as_VMReg()->next());
113 reg_def R17 ( SOC, SOC, Op_RegI, 17, x17->as_VMReg() );
114 reg_def R17_H ( SOC, SOC, Op_RegI, 17, x17->as_VMReg()->next());
115 reg_def R18 ( SOC, SOE, Op_RegI, 18, x18->as_VMReg() );
116 reg_def R18_H ( SOC, SOE, Op_RegI, 18, x18->as_VMReg()->next());
117 reg_def R19 ( SOC, SOE, Op_RegI, 19, x19->as_VMReg() );
118 reg_def R19_H ( SOC, SOE, Op_RegI, 19, x19->as_VMReg()->next());
119 reg_def R20 ( SOC, SOE, Op_RegI, 20, x20->as_VMReg() ); // caller esp
120 reg_def R20_H ( SOC, SOE, Op_RegI, 20, x20->as_VMReg()->next());
121 reg_def R21 ( SOC, SOE, Op_RegI, 21, x21->as_VMReg() );
122 reg_def R21_H ( SOC, SOE, Op_RegI, 21, x21->as_VMReg()->next());
123 reg_def R22 ( SOC, SOE, Op_RegI, 22, x22->as_VMReg() );
124 reg_def R22_H ( SOC, SOE, Op_RegI, 22, x22->as_VMReg()->next());
125 reg_def R23 ( NS, SOE, Op_RegI, 23, x23->as_VMReg() ); // java thread
126 reg_def R23_H ( NS, SOE, Op_RegI, 23, x23->as_VMReg()->next());
127 reg_def R24 ( SOC, SOE, Op_RegI, 24, x24->as_VMReg() );
128 reg_def R24_H ( SOC, SOE, Op_RegI, 24, x24->as_VMReg()->next());
129 reg_def R25 ( SOC, SOE, Op_RegI, 25, x25->as_VMReg() );
130 reg_def R25_H ( SOC, SOE, Op_RegI, 25, x25->as_VMReg()->next());
131 reg_def R26 ( SOC, SOE, Op_RegI, 26, x26->as_VMReg() );
132 reg_def R26_H ( SOC, SOE, Op_RegI, 26, x26->as_VMReg()->next());
133 reg_def R27 ( SOC, SOE, Op_RegI, 27, x27->as_VMReg() ); // heapbase
134 reg_def R27_H ( SOC, SOE, Op_RegI, 27, x27->as_VMReg()->next());
135 reg_def R28 ( SOC, SOC, Op_RegI, 28, x28->as_VMReg() );
136 reg_def R28_H ( SOC, SOC, Op_RegI, 28, x28->as_VMReg()->next());
137 reg_def R29 ( SOC, SOC, Op_RegI, 29, x29->as_VMReg() );
138 reg_def R29_H ( SOC, SOC, Op_RegI, 29, x29->as_VMReg()->next());
139 reg_def R30 ( SOC, SOC, Op_RegI, 30, x30->as_VMReg() );
140 reg_def R30_H ( SOC, SOC, Op_RegI, 30, x30->as_VMReg()->next());
141 reg_def R31 ( SOC, SOC, Op_RegI, 31, x31->as_VMReg() );
142 reg_def R31_H ( SOC, SOC, Op_RegI, 31, x31->as_VMReg()->next());
143
144 // ----------------------------
145 // Float/Double Registers
146 // ----------------------------
147
148 // Double Registers
149
150 // The rules of ADL require that double registers be defined in pairs.
151 // Each pair must be two 32-bit values, but not necessarily a pair of
152 // single float registers. In each pair, ADLC-assigned register numbers
153 // must be adjacent, with the lower number even. Finally, when the
154 // CPU stores such a register pair to memory, the word associated with
155 // the lower ADLC-assigned number must be stored to the lower address.
156
157 // RISCV has 32 floating-point registers. Each can store a single
158 // or double precision floating-point value.
159
160 // for Java use float registers f0-f31 are always save on call whereas
161 // the platform ABI treats f8-f9 and f18-f27 as callee save). Other
162 // float registers are SOC as per the platform spec
163
164 reg_def F0 ( SOC, SOC, Op_RegF, 0, f0->as_VMReg() );
165 reg_def F0_H ( SOC, SOC, Op_RegF, 0, f0->as_VMReg()->next() );
166 reg_def F1 ( SOC, SOC, Op_RegF, 1, f1->as_VMReg() );
167 reg_def F1_H ( SOC, SOC, Op_RegF, 1, f1->as_VMReg()->next() );
168 reg_def F2 ( SOC, SOC, Op_RegF, 2, f2->as_VMReg() );
169 reg_def F2_H ( SOC, SOC, Op_RegF, 2, f2->as_VMReg()->next() );
170 reg_def F3 ( SOC, SOC, Op_RegF, 3, f3->as_VMReg() );
171 reg_def F3_H ( SOC, SOC, Op_RegF, 3, f3->as_VMReg()->next() );
172 reg_def F4 ( SOC, SOC, Op_RegF, 4, f4->as_VMReg() );
173 reg_def F4_H ( SOC, SOC, Op_RegF, 4, f4->as_VMReg()->next() );
174 reg_def F5 ( SOC, SOC, Op_RegF, 5, f5->as_VMReg() );
175 reg_def F5_H ( SOC, SOC, Op_RegF, 5, f5->as_VMReg()->next() );
176 reg_def F6 ( SOC, SOC, Op_RegF, 6, f6->as_VMReg() );
177 reg_def F6_H ( SOC, SOC, Op_RegF, 6, f6->as_VMReg()->next() );
178 reg_def F7 ( SOC, SOC, Op_RegF, 7, f7->as_VMReg() );
179 reg_def F7_H ( SOC, SOC, Op_RegF, 7, f7->as_VMReg()->next() );
180 reg_def F8 ( SOC, SOE, Op_RegF, 8, f8->as_VMReg() );
181 reg_def F8_H ( SOC, SOE, Op_RegF, 8, f8->as_VMReg()->next() );
182 reg_def F9 ( SOC, SOE, Op_RegF, 9, f9->as_VMReg() );
183 reg_def F9_H ( SOC, SOE, Op_RegF, 9, f9->as_VMReg()->next() );
184 reg_def F10 ( SOC, SOC, Op_RegF, 10, f10->as_VMReg() );
185 reg_def F10_H ( SOC, SOC, Op_RegF, 10, f10->as_VMReg()->next() );
186 reg_def F11 ( SOC, SOC, Op_RegF, 11, f11->as_VMReg() );
187 reg_def F11_H ( SOC, SOC, Op_RegF, 11, f11->as_VMReg()->next() );
188 reg_def F12 ( SOC, SOC, Op_RegF, 12, f12->as_VMReg() );
189 reg_def F12_H ( SOC, SOC, Op_RegF, 12, f12->as_VMReg()->next() );
190 reg_def F13 ( SOC, SOC, Op_RegF, 13, f13->as_VMReg() );
191 reg_def F13_H ( SOC, SOC, Op_RegF, 13, f13->as_VMReg()->next() );
192 reg_def F14 ( SOC, SOC, Op_RegF, 14, f14->as_VMReg() );
193 reg_def F14_H ( SOC, SOC, Op_RegF, 14, f14->as_VMReg()->next() );
194 reg_def F15 ( SOC, SOC, Op_RegF, 15, f15->as_VMReg() );
195 reg_def F15_H ( SOC, SOC, Op_RegF, 15, f15->as_VMReg()->next() );
196 reg_def F16 ( SOC, SOC, Op_RegF, 16, f16->as_VMReg() );
197 reg_def F16_H ( SOC, SOC, Op_RegF, 16, f16->as_VMReg()->next() );
198 reg_def F17 ( SOC, SOC, Op_RegF, 17, f17->as_VMReg() );
199 reg_def F17_H ( SOC, SOC, Op_RegF, 17, f17->as_VMReg()->next() );
200 reg_def F18 ( SOC, SOE, Op_RegF, 18, f18->as_VMReg() );
201 reg_def F18_H ( SOC, SOE, Op_RegF, 18, f18->as_VMReg()->next() );
202 reg_def F19 ( SOC, SOE, Op_RegF, 19, f19->as_VMReg() );
203 reg_def F19_H ( SOC, SOE, Op_RegF, 19, f19->as_VMReg()->next() );
204 reg_def F20 ( SOC, SOE, Op_RegF, 20, f20->as_VMReg() );
205 reg_def F20_H ( SOC, SOE, Op_RegF, 20, f20->as_VMReg()->next() );
206 reg_def F21 ( SOC, SOE, Op_RegF, 21, f21->as_VMReg() );
207 reg_def F21_H ( SOC, SOE, Op_RegF, 21, f21->as_VMReg()->next() );
208 reg_def F22 ( SOC, SOE, Op_RegF, 22, f22->as_VMReg() );
209 reg_def F22_H ( SOC, SOE, Op_RegF, 22, f22->as_VMReg()->next() );
210 reg_def F23 ( SOC, SOE, Op_RegF, 23, f23->as_VMReg() );
211 reg_def F23_H ( SOC, SOE, Op_RegF, 23, f23->as_VMReg()->next() );
212 reg_def F24 ( SOC, SOE, Op_RegF, 24, f24->as_VMReg() );
213 reg_def F24_H ( SOC, SOE, Op_RegF, 24, f24->as_VMReg()->next() );
214 reg_def F25 ( SOC, SOE, Op_RegF, 25, f25->as_VMReg() );
215 reg_def F25_H ( SOC, SOE, Op_RegF, 25, f25->as_VMReg()->next() );
216 reg_def F26 ( SOC, SOE, Op_RegF, 26, f26->as_VMReg() );
217 reg_def F26_H ( SOC, SOE, Op_RegF, 26, f26->as_VMReg()->next() );
218 reg_def F27 ( SOC, SOE, Op_RegF, 27, f27->as_VMReg() );
219 reg_def F27_H ( SOC, SOE, Op_RegF, 27, f27->as_VMReg()->next() );
220 reg_def F28 ( SOC, SOC, Op_RegF, 28, f28->as_VMReg() );
221 reg_def F28_H ( SOC, SOC, Op_RegF, 28, f28->as_VMReg()->next() );
222 reg_def F29 ( SOC, SOC, Op_RegF, 29, f29->as_VMReg() );
223 reg_def F29_H ( SOC, SOC, Op_RegF, 29, f29->as_VMReg()->next() );
224 reg_def F30 ( SOC, SOC, Op_RegF, 30, f30->as_VMReg() );
225 reg_def F30_H ( SOC, SOC, Op_RegF, 30, f30->as_VMReg()->next() );
226 reg_def F31 ( SOC, SOC, Op_RegF, 31, f31->as_VMReg() );
227 reg_def F31_H ( SOC, SOC, Op_RegF, 31, f31->as_VMReg()->next() );
228
229 // ----------------------------
230 // Vector Registers
231 // ----------------------------
232
233 // For RVV vector registers, we simply extend vector register size to 4
234 // 'logical' slots. This is nominally 128 bits but it actually covers
235 // all possible 'physical' RVV vector register lengths from 128 ~ 1024
236 // bits. The 'physical' RVV vector register length is detected during
237 // startup, so the register allocator is able to identify the correct
238 // number of bytes needed for an RVV spill/unspill.
239
240 reg_def V0 ( SOC, SOC, Op_VecA, 0, v0->as_VMReg() );
241 reg_def V0_H ( SOC, SOC, Op_VecA, 0, v0->as_VMReg()->next() );
242 reg_def V0_J ( SOC, SOC, Op_VecA, 0, v0->as_VMReg()->next(2) );
243 reg_def V0_K ( SOC, SOC, Op_VecA, 0, v0->as_VMReg()->next(3) );
244
245 reg_def V1 ( SOC, SOC, Op_VecA, 1, v1->as_VMReg() );
246 reg_def V1_H ( SOC, SOC, Op_VecA, 1, v1->as_VMReg()->next() );
247 reg_def V1_J ( SOC, SOC, Op_VecA, 1, v1->as_VMReg()->next(2) );
248 reg_def V1_K ( SOC, SOC, Op_VecA, 1, v1->as_VMReg()->next(3) );
249
250 reg_def V2 ( SOC, SOC, Op_VecA, 2, v2->as_VMReg() );
251 reg_def V2_H ( SOC, SOC, Op_VecA, 2, v2->as_VMReg()->next() );
252 reg_def V2_J ( SOC, SOC, Op_VecA, 2, v2->as_VMReg()->next(2) );
253 reg_def V2_K ( SOC, SOC, Op_VecA, 2, v2->as_VMReg()->next(3) );
254
255 reg_def V3 ( SOC, SOC, Op_VecA, 3, v3->as_VMReg() );
256 reg_def V3_H ( SOC, SOC, Op_VecA, 3, v3->as_VMReg()->next() );
257 reg_def V3_J ( SOC, SOC, Op_VecA, 3, v3->as_VMReg()->next(2) );
258 reg_def V3_K ( SOC, SOC, Op_VecA, 3, v3->as_VMReg()->next(3) );
259
260 reg_def V4 ( SOC, SOC, Op_VecA, 4, v4->as_VMReg() );
261 reg_def V4_H ( SOC, SOC, Op_VecA, 4, v4->as_VMReg()->next() );
262 reg_def V4_J ( SOC, SOC, Op_VecA, 4, v4->as_VMReg()->next(2) );
263 reg_def V4_K ( SOC, SOC, Op_VecA, 4, v4->as_VMReg()->next(3) );
264
265 reg_def V5 ( SOC, SOC, Op_VecA, 5, v5->as_VMReg() );
266 reg_def V5_H ( SOC, SOC, Op_VecA, 5, v5->as_VMReg()->next() );
267 reg_def V5_J ( SOC, SOC, Op_VecA, 5, v5->as_VMReg()->next(2) );
268 reg_def V5_K ( SOC, SOC, Op_VecA, 5, v5->as_VMReg()->next(3) );
269
270 reg_def V6 ( SOC, SOC, Op_VecA, 6, v6->as_VMReg() );
271 reg_def V6_H ( SOC, SOC, Op_VecA, 6, v6->as_VMReg()->next() );
272 reg_def V6_J ( SOC, SOC, Op_VecA, 6, v6->as_VMReg()->next(2) );
273 reg_def V6_K ( SOC, SOC, Op_VecA, 6, v6->as_VMReg()->next(3) );
274
275 reg_def V7 ( SOC, SOC, Op_VecA, 7, v7->as_VMReg() );
276 reg_def V7_H ( SOC, SOC, Op_VecA, 7, v7->as_VMReg()->next() );
277 reg_def V7_J ( SOC, SOC, Op_VecA, 7, v7->as_VMReg()->next(2) );
278 reg_def V7_K ( SOC, SOC, Op_VecA, 7, v7->as_VMReg()->next(3) );
279
280 reg_def V8 ( SOC, SOC, Op_VecA, 8, v8->as_VMReg() );
281 reg_def V8_H ( SOC, SOC, Op_VecA, 8, v8->as_VMReg()->next() );
282 reg_def V8_J ( SOC, SOC, Op_VecA, 8, v8->as_VMReg()->next(2) );
283 reg_def V8_K ( SOC, SOC, Op_VecA, 8, v8->as_VMReg()->next(3) );
284
285 reg_def V9 ( SOC, SOC, Op_VecA, 9, v9->as_VMReg() );
286 reg_def V9_H ( SOC, SOC, Op_VecA, 9, v9->as_VMReg()->next() );
287 reg_def V9_J ( SOC, SOC, Op_VecA, 9, v9->as_VMReg()->next(2) );
288 reg_def V9_K ( SOC, SOC, Op_VecA, 9, v9->as_VMReg()->next(3) );
289
290 reg_def V10 ( SOC, SOC, Op_VecA, 10, v10->as_VMReg() );
291 reg_def V10_H ( SOC, SOC, Op_VecA, 10, v10->as_VMReg()->next() );
292 reg_def V10_J ( SOC, SOC, Op_VecA, 10, v10->as_VMReg()->next(2) );
293 reg_def V10_K ( SOC, SOC, Op_VecA, 10, v10->as_VMReg()->next(3) );
294
295 reg_def V11 ( SOC, SOC, Op_VecA, 11, v11->as_VMReg() );
296 reg_def V11_H ( SOC, SOC, Op_VecA, 11, v11->as_VMReg()->next() );
297 reg_def V11_J ( SOC, SOC, Op_VecA, 11, v11->as_VMReg()->next(2) );
298 reg_def V11_K ( SOC, SOC, Op_VecA, 11, v11->as_VMReg()->next(3) );
299
300 reg_def V12 ( SOC, SOC, Op_VecA, 12, v12->as_VMReg() );
301 reg_def V12_H ( SOC, SOC, Op_VecA, 12, v12->as_VMReg()->next() );
302 reg_def V12_J ( SOC, SOC, Op_VecA, 12, v12->as_VMReg()->next(2) );
303 reg_def V12_K ( SOC, SOC, Op_VecA, 12, v12->as_VMReg()->next(3) );
304
305 reg_def V13 ( SOC, SOC, Op_VecA, 13, v13->as_VMReg() );
306 reg_def V13_H ( SOC, SOC, Op_VecA, 13, v13->as_VMReg()->next() );
307 reg_def V13_J ( SOC, SOC, Op_VecA, 13, v13->as_VMReg()->next(2) );
308 reg_def V13_K ( SOC, SOC, Op_VecA, 13, v13->as_VMReg()->next(3) );
309
310 reg_def V14 ( SOC, SOC, Op_VecA, 14, v14->as_VMReg() );
311 reg_def V14_H ( SOC, SOC, Op_VecA, 14, v14->as_VMReg()->next() );
312 reg_def V14_J ( SOC, SOC, Op_VecA, 14, v14->as_VMReg()->next(2) );
313 reg_def V14_K ( SOC, SOC, Op_VecA, 14, v14->as_VMReg()->next(3) );
314
315 reg_def V15 ( SOC, SOC, Op_VecA, 15, v15->as_VMReg() );
316 reg_def V15_H ( SOC, SOC, Op_VecA, 15, v15->as_VMReg()->next() );
317 reg_def V15_J ( SOC, SOC, Op_VecA, 15, v15->as_VMReg()->next(2) );
318 reg_def V15_K ( SOC, SOC, Op_VecA, 15, v15->as_VMReg()->next(3) );
319
320 reg_def V16 ( SOC, SOC, Op_VecA, 16, v16->as_VMReg() );
321 reg_def V16_H ( SOC, SOC, Op_VecA, 16, v16->as_VMReg()->next() );
322 reg_def V16_J ( SOC, SOC, Op_VecA, 16, v16->as_VMReg()->next(2) );
323 reg_def V16_K ( SOC, SOC, Op_VecA, 16, v16->as_VMReg()->next(3) );
324
325 reg_def V17 ( SOC, SOC, Op_VecA, 17, v17->as_VMReg() );
326 reg_def V17_H ( SOC, SOC, Op_VecA, 17, v17->as_VMReg()->next() );
327 reg_def V17_J ( SOC, SOC, Op_VecA, 17, v17->as_VMReg()->next(2) );
328 reg_def V17_K ( SOC, SOC, Op_VecA, 17, v17->as_VMReg()->next(3) );
329
330 reg_def V18 ( SOC, SOC, Op_VecA, 18, v18->as_VMReg() );
331 reg_def V18_H ( SOC, SOC, Op_VecA, 18, v18->as_VMReg()->next() );
332 reg_def V18_J ( SOC, SOC, Op_VecA, 18, v18->as_VMReg()->next(2) );
333 reg_def V18_K ( SOC, SOC, Op_VecA, 18, v18->as_VMReg()->next(3) );
334
335 reg_def V19 ( SOC, SOC, Op_VecA, 19, v19->as_VMReg() );
336 reg_def V19_H ( SOC, SOC, Op_VecA, 19, v19->as_VMReg()->next() );
337 reg_def V19_J ( SOC, SOC, Op_VecA, 19, v19->as_VMReg()->next(2) );
338 reg_def V19_K ( SOC, SOC, Op_VecA, 19, v19->as_VMReg()->next(3) );
339
340 reg_def V20 ( SOC, SOC, Op_VecA, 20, v20->as_VMReg() );
341 reg_def V20_H ( SOC, SOC, Op_VecA, 20, v20->as_VMReg()->next() );
342 reg_def V20_J ( SOC, SOC, Op_VecA, 20, v20->as_VMReg()->next(2) );
343 reg_def V20_K ( SOC, SOC, Op_VecA, 20, v20->as_VMReg()->next(3) );
344
345 reg_def V21 ( SOC, SOC, Op_VecA, 21, v21->as_VMReg() );
346 reg_def V21_H ( SOC, SOC, Op_VecA, 21, v21->as_VMReg()->next() );
347 reg_def V21_J ( SOC, SOC, Op_VecA, 21, v21->as_VMReg()->next(2) );
348 reg_def V21_K ( SOC, SOC, Op_VecA, 21, v21->as_VMReg()->next(3) );
349
350 reg_def V22 ( SOC, SOC, Op_VecA, 22, v22->as_VMReg() );
351 reg_def V22_H ( SOC, SOC, Op_VecA, 22, v22->as_VMReg()->next() );
352 reg_def V22_J ( SOC, SOC, Op_VecA, 22, v22->as_VMReg()->next(2) );
353 reg_def V22_K ( SOC, SOC, Op_VecA, 22, v22->as_VMReg()->next(3) );
354
355 reg_def V23 ( SOC, SOC, Op_VecA, 23, v23->as_VMReg() );
356 reg_def V23_H ( SOC, SOC, Op_VecA, 23, v23->as_VMReg()->next() );
357 reg_def V23_J ( SOC, SOC, Op_VecA, 23, v23->as_VMReg()->next(2) );
358 reg_def V23_K ( SOC, SOC, Op_VecA, 23, v23->as_VMReg()->next(3) );
359
360 reg_def V24 ( SOC, SOC, Op_VecA, 24, v24->as_VMReg() );
361 reg_def V24_H ( SOC, SOC, Op_VecA, 24, v24->as_VMReg()->next() );
362 reg_def V24_J ( SOC, SOC, Op_VecA, 24, v24->as_VMReg()->next(2) );
363 reg_def V24_K ( SOC, SOC, Op_VecA, 24, v24->as_VMReg()->next(3) );
364
365 reg_def V25 ( SOC, SOC, Op_VecA, 25, v25->as_VMReg() );
366 reg_def V25_H ( SOC, SOC, Op_VecA, 25, v25->as_VMReg()->next() );
367 reg_def V25_J ( SOC, SOC, Op_VecA, 25, v25->as_VMReg()->next(2) );
368 reg_def V25_K ( SOC, SOC, Op_VecA, 25, v25->as_VMReg()->next(3) );
369
370 reg_def V26 ( SOC, SOC, Op_VecA, 26, v26->as_VMReg() );
371 reg_def V26_H ( SOC, SOC, Op_VecA, 26, v26->as_VMReg()->next() );
372 reg_def V26_J ( SOC, SOC, Op_VecA, 26, v26->as_VMReg()->next(2) );
373 reg_def V26_K ( SOC, SOC, Op_VecA, 26, v26->as_VMReg()->next(3) );
374
375 reg_def V27 ( SOC, SOC, Op_VecA, 27, v27->as_VMReg() );
376 reg_def V27_H ( SOC, SOC, Op_VecA, 27, v27->as_VMReg()->next() );
377 reg_def V27_J ( SOC, SOC, Op_VecA, 27, v27->as_VMReg()->next(2) );
378 reg_def V27_K ( SOC, SOC, Op_VecA, 27, v27->as_VMReg()->next(3) );
379
380 reg_def V28 ( SOC, SOC, Op_VecA, 28, v28->as_VMReg() );
381 reg_def V28_H ( SOC, SOC, Op_VecA, 28, v28->as_VMReg()->next() );
382 reg_def V28_J ( SOC, SOC, Op_VecA, 28, v28->as_VMReg()->next(2) );
383 reg_def V28_K ( SOC, SOC, Op_VecA, 28, v28->as_VMReg()->next(3) );
384
385 reg_def V29 ( SOC, SOC, Op_VecA, 29, v29->as_VMReg() );
386 reg_def V29_H ( SOC, SOC, Op_VecA, 29, v29->as_VMReg()->next() );
387 reg_def V29_J ( SOC, SOC, Op_VecA, 29, v29->as_VMReg()->next(2) );
388 reg_def V29_K ( SOC, SOC, Op_VecA, 29, v29->as_VMReg()->next(3) );
389
390 reg_def V30 ( SOC, SOC, Op_VecA, 30, v30->as_VMReg() );
391 reg_def V30_H ( SOC, SOC, Op_VecA, 30, v30->as_VMReg()->next() );
392 reg_def V30_J ( SOC, SOC, Op_VecA, 30, v30->as_VMReg()->next(2) );
393 reg_def V30_K ( SOC, SOC, Op_VecA, 30, v30->as_VMReg()->next(3) );
394
395 reg_def V31 ( SOC, SOC, Op_VecA, 31, v31->as_VMReg() );
396 reg_def V31_H ( SOC, SOC, Op_VecA, 31, v31->as_VMReg()->next() );
397 reg_def V31_J ( SOC, SOC, Op_VecA, 31, v31->as_VMReg()->next(2) );
398 reg_def V31_K ( SOC, SOC, Op_VecA, 31, v31->as_VMReg()->next(3) );
399
400 // ----------------------------
401 // Special Registers
402 // ----------------------------
403
404 // On riscv, the physical flag register is missing, so we use t1 instead,
405 // to bridge the RegFlag semantics in share/opto
406
407 reg_def RFLAGS (SOC, SOC, Op_RegFlags, 6, x6->as_VMReg() );
408
409 // Specify priority of register selection within phases of register
410 // allocation. Highest priority is first. A useful heuristic is to
411 // give registers a low priority when they are required by machine
412 // instructions, like EAX and EDX on I486, and choose no-save registers
413 // before save-on-call, & save-on-call before save-on-entry. Registers
414 // which participate in fixed calling sequences should come last.
415 // Registers which are used as pairs must fall on an even boundary.
416
417 alloc_class chunk0(
418 // volatiles
419 R7, R7_H,
420 R28, R28_H,
421 R29, R29_H,
422 R30, R30_H,
423 R31, R31_H,
424
425 // arg registers
426 R10, R10_H,
427 R11, R11_H,
428 R12, R12_H,
429 R13, R13_H,
430 R14, R14_H,
431 R15, R15_H,
432 R16, R16_H,
433 R17, R17_H,
434
435 // non-volatiles
436 R9, R9_H,
437 R18, R18_H,
438 R19, R19_H,
439 R20, R20_H,
440 R21, R21_H,
441 R22, R22_H,
442 R24, R24_H,
443 R25, R25_H,
444 R26, R26_H,
445
446 // non-allocatable registers
447 R23, R23_H, // java thread
448 R27, R27_H, // heapbase
449 R4, R4_H, // thread
450 R8, R8_H, // fp
451 R0, R0_H, // zero
452 R1, R1_H, // ra
453 R2, R2_H, // sp
454 R3, R3_H, // gp
455 );
456
457 alloc_class chunk1(
458
459 // no save
460 F0, F0_H,
461 F1, F1_H,
462 F2, F2_H,
463 F3, F3_H,
464 F4, F4_H,
465 F5, F5_H,
466 F6, F6_H,
467 F7, F7_H,
468 F28, F28_H,
469 F29, F29_H,
470 F30, F30_H,
471 F31, F31_H,
472
473 // arg registers
474 F10, F10_H,
475 F11, F11_H,
476 F12, F12_H,
477 F13, F13_H,
478 F14, F14_H,
479 F15, F15_H,
480 F16, F16_H,
481 F17, F17_H,
482
483 // non-volatiles
484 F8, F8_H,
485 F9, F9_H,
486 F18, F18_H,
487 F19, F19_H,
488 F20, F20_H,
489 F21, F21_H,
490 F22, F22_H,
491 F23, F23_H,
492 F24, F24_H,
493 F25, F25_H,
494 F26, F26_H,
495 F27, F27_H,
496 );
497
498 alloc_class chunk2(
499 V0, V0_H, V0_J, V0_K,
500 V1, V1_H, V1_J, V1_K,
501 V2, V2_H, V2_J, V2_K,
502 V3, V3_H, V3_J, V3_K,
503 V4, V4_H, V4_J, V4_K,
504 V5, V5_H, V5_J, V5_K,
505 V6, V6_H, V6_J, V6_K,
506 V7, V7_H, V7_J, V7_K,
507 V8, V8_H, V8_J, V8_K,
508 V9, V9_H, V9_J, V9_K,
509 V10, V10_H, V10_J, V10_K,
510 V11, V11_H, V11_J, V11_K,
511 V12, V12_H, V12_J, V12_K,
512 V13, V13_H, V13_J, V13_K,
513 V14, V14_H, V14_J, V14_K,
514 V15, V15_H, V15_J, V15_K,
515 V16, V16_H, V16_J, V16_K,
516 V17, V17_H, V17_J, V17_K,
517 V18, V18_H, V18_J, V18_K,
518 V19, V19_H, V19_J, V19_K,
519 V20, V20_H, V20_J, V20_K,
520 V21, V21_H, V21_J, V21_K,
521 V22, V22_H, V22_J, V22_K,
522 V23, V23_H, V23_J, V23_K,
523 V24, V24_H, V24_J, V24_K,
524 V25, V25_H, V25_J, V25_K,
525 V26, V26_H, V26_J, V26_K,
526 V27, V27_H, V27_J, V27_K,
527 V28, V28_H, V28_J, V28_K,
528 V29, V29_H, V29_J, V29_K,
529 V30, V30_H, V30_J, V30_K,
530 V31, V31_H, V31_J, V31_K,
531 );
532
533 alloc_class chunk3(RFLAGS);
534
535 //----------Architecture Description Register Classes--------------------------
536 // Several register classes are automatically defined based upon information in
537 // this architecture description.
538 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
539 // 2) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
540 //
541
542 // Class for all 32 bit general purpose registers
543 reg_class all_reg32(
544 R0,
545 R1,
546 R2,
547 R3,
548 R4,
549 R7,
550 R8,
551 R9,
552 R10,
553 R11,
554 R12,
555 R13,
556 R14,
557 R15,
558 R16,
559 R17,
560 R18,
561 R19,
562 R20,
563 R21,
564 R22,
565 R23,
566 R24,
567 R25,
568 R26,
569 R27,
570 R28,
571 R29,
572 R30,
573 R31
574 );
575
576 // Class for any 32 bit integer registers (excluding zr)
577 reg_class any_reg32 %{
578 return _ANY_REG32_mask;
579 %}
580
581 // Singleton class for R10 int register
582 reg_class int_r10_reg(R10);
583
584 // Singleton class for R12 int register
585 reg_class int_r12_reg(R12);
586
587 // Singleton class for R13 int register
588 reg_class int_r13_reg(R13);
589
590 // Singleton class for R14 int register
591 reg_class int_r14_reg(R14);
592
593 // Class for all long integer registers
594 reg_class all_reg(
595 R0, R0_H,
596 R1, R1_H,
597 R2, R2_H,
598 R3, R3_H,
599 R4, R4_H,
600 R7, R7_H,
601 R8, R8_H,
602 R9, R9_H,
603 R10, R10_H,
604 R11, R11_H,
605 R12, R12_H,
606 R13, R13_H,
607 R14, R14_H,
608 R15, R15_H,
609 R16, R16_H,
610 R17, R17_H,
611 R18, R18_H,
612 R19, R19_H,
613 R20, R20_H,
614 R21, R21_H,
615 R22, R22_H,
616 R23, R23_H,
617 R24, R24_H,
618 R25, R25_H,
619 R26, R26_H,
620 R27, R27_H,
621 R28, R28_H,
622 R29, R29_H,
623 R30, R30_H,
624 R31, R31_H
625 );
626
627 // Class for all long integer registers (excluding zr)
628 reg_class any_reg %{
629 return _ANY_REG_mask;
630 %}
631
632 // Class for non-allocatable 32 bit registers
633 reg_class non_allocatable_reg32(
634 R0, // zr
635 R1, // ra
636 R2, // sp
637 R3, // gp
638 R4, // tp
639 R23 // java thread
640 );
641
642 // Class for non-allocatable 64 bit registers
643 reg_class non_allocatable_reg(
644 R0, R0_H, // zr
645 R1, R1_H, // ra
646 R2, R2_H, // sp
647 R3, R3_H, // gp
648 R4, R4_H, // tp
649 R23, R23_H // java thread
650 );
651
652 // Class for all non-special integer registers
653 reg_class no_special_reg32 %{
654 return _NO_SPECIAL_REG32_mask;
655 %}
656
657 // Class for all non-special long integer registers
658 reg_class no_special_reg %{
659 return _NO_SPECIAL_REG_mask;
660 %}
661
662 reg_class ptr_reg %{
663 return _PTR_REG_mask;
664 %}
665
666 // Class for all non_special pointer registers
667 reg_class no_special_ptr_reg %{
668 return _NO_SPECIAL_PTR_REG_mask;
669 %}
670
671 // Class for all non_special pointer registers (excluding fp)
672 reg_class no_special_no_fp_ptr_reg %{
673 return _NO_SPECIAL_NO_FP_PTR_REG_mask;
674 %}
675
676 // Class for 64 bit register r10
677 reg_class r10_reg(
678 R10, R10_H
679 );
680
681 // Class for 64 bit register r11
682 reg_class r11_reg(
683 R11, R11_H
684 );
685
686 // Class for 64 bit register r12
687 reg_class r12_reg(
688 R12, R12_H
689 );
690
691 // Class for 64 bit register r13
692 reg_class r13_reg(
693 R13, R13_H
694 );
695
696 // Class for 64 bit register r14
697 reg_class r14_reg(
698 R14, R14_H
699 );
700
701 // Class for 64 bit register r15
702 reg_class r15_reg(
703 R15, R15_H
704 );
705
706 // Class for 64 bit register r16
707 reg_class r16_reg(
708 R16, R16_H
709 );
710
711 // Class for method register
712 reg_class method_reg(
713 R31, R31_H
714 );
715
716 // Class for java thread register
717 reg_class java_thread_reg(
718 R23, R23_H
719 );
720
721 reg_class r28_reg(
722 R28, R28_H
723 );
724
725 reg_class r29_reg(
726 R29, R29_H
727 );
728
729 reg_class r30_reg(
730 R30, R30_H
731 );
732
733 reg_class r31_reg(
734 R31, R31_H
735 );
736
737 // Class for zero registesr
738 reg_class zr_reg(
739 R0, R0_H
740 );
741
742 // Class for thread register
743 reg_class thread_reg(
744 R4, R4_H
745 );
746
747 // Class for frame pointer register
748 reg_class fp_reg(
749 R8, R8_H
750 );
751
752 // Class for link register
753 reg_class ra_reg(
754 R1, R1_H
755 );
756
757 // Class for long sp register
758 reg_class sp_reg(
759 R2, R2_H
760 );
761
762 // Class for all float registers
763 reg_class float_reg(
764 F0,
765 F1,
766 F2,
767 F3,
768 F4,
769 F5,
770 F6,
771 F7,
772 F8,
773 F9,
774 F10,
775 F11,
776 F12,
777 F13,
778 F14,
779 F15,
780 F16,
781 F17,
782 F18,
783 F19,
784 F20,
785 F21,
786 F22,
787 F23,
788 F24,
789 F25,
790 F26,
791 F27,
792 F28,
793 F29,
794 F30,
795 F31
796 );
797
798 // Double precision float registers have virtual `high halves' that
799 // are needed by the allocator.
800 // Class for all double registers
801 reg_class double_reg(
802 F0, F0_H,
803 F1, F1_H,
804 F2, F2_H,
805 F3, F3_H,
806 F4, F4_H,
807 F5, F5_H,
808 F6, F6_H,
809 F7, F7_H,
810 F8, F8_H,
811 F9, F9_H,
812 F10, F10_H,
813 F11, F11_H,
814 F12, F12_H,
815 F13, F13_H,
816 F14, F14_H,
817 F15, F15_H,
818 F16, F16_H,
819 F17, F17_H,
820 F18, F18_H,
821 F19, F19_H,
822 F20, F20_H,
823 F21, F21_H,
824 F22, F22_H,
825 F23, F23_H,
826 F24, F24_H,
827 F25, F25_H,
828 F26, F26_H,
829 F27, F27_H,
830 F28, F28_H,
831 F29, F29_H,
832 F30, F30_H,
833 F31, F31_H
834 );
835
836 // Class for RVV vector registers
837 // Note: v0, v30 and v31 are used as mask registers.
838 reg_class vectora_reg(
839 V1, V1_H, V1_J, V1_K,
840 V2, V2_H, V2_J, V2_K,
841 V3, V3_H, V3_J, V3_K,
842 V4, V4_H, V4_J, V4_K,
843 V5, V5_H, V5_J, V5_K,
844 V6, V6_H, V6_J, V6_K,
845 V7, V7_H, V7_J, V7_K,
846 V8, V8_H, V8_J, V8_K,
847 V9, V9_H, V9_J, V9_K,
848 V10, V10_H, V10_J, V10_K,
849 V11, V11_H, V11_J, V11_K,
850 V12, V12_H, V12_J, V12_K,
851 V13, V13_H, V13_J, V13_K,
852 V14, V14_H, V14_J, V14_K,
853 V15, V15_H, V15_J, V15_K,
854 V16, V16_H, V16_J, V16_K,
855 V17, V17_H, V17_J, V17_K,
856 V18, V18_H, V18_J, V18_K,
857 V19, V19_H, V19_J, V19_K,
858 V20, V20_H, V20_J, V20_K,
859 V21, V21_H, V21_J, V21_K,
860 V22, V22_H, V22_J, V22_K,
861 V23, V23_H, V23_J, V23_K,
862 V24, V24_H, V24_J, V24_K,
863 V25, V25_H, V25_J, V25_K,
864 V26, V26_H, V26_J, V26_K,
865 V27, V27_H, V27_J, V27_K,
866 V28, V28_H, V28_J, V28_K,
867 V29, V29_H, V29_J, V29_K
868 );
869
870 // Class for 64 bit register f0
871 reg_class f0_reg(
872 F0, F0_H
873 );
874
875 // Class for 64 bit register f1
876 reg_class f1_reg(
877 F1, F1_H
878 );
879
880 // Class for 64 bit register f2
881 reg_class f2_reg(
882 F2, F2_H
883 );
884
885 // Class for 64 bit register f3
886 reg_class f3_reg(
887 F3, F3_H
888 );
889
890 // class for vector register v1
891 reg_class v1_reg(
892 V1, V1_H, V1_J, V1_K
893 );
894
895 // class for vector register v2
896 reg_class v2_reg(
897 V2, V2_H, V2_J, V2_K
898 );
899
900 // class for vector register v3
901 reg_class v3_reg(
902 V3, V3_H, V3_J, V3_K
903 );
904
905 // class for vector register v4
906 reg_class v4_reg(
907 V4, V4_H, V4_J, V4_K
908 );
909
910 // class for vector register v5
911 reg_class v5_reg(
912 V5, V5_H, V5_J, V5_K
913 );
914
915 // class for vector register v6
916 reg_class v6_reg(
917 V6, V6_H, V6_J, V6_K
918 );
919
920 // class for vector register v7
921 reg_class v7_reg(
922 V7, V7_H, V7_J, V7_K
923 );
924
925 // class for vector register v8
926 reg_class v8_reg(
927 V8, V8_H, V8_J, V8_K
928 );
929
930 // class for vector register v9
931 reg_class v9_reg(
932 V9, V9_H, V9_J, V9_K
933 );
934
935 // class for vector register v10
936 reg_class v10_reg(
937 V10, V10_H, V10_J, V10_K
938 );
939
940 // class for vector register v11
941 reg_class v11_reg(
942 V11, V11_H, V11_J, V11_K
943 );
944
945 // class for condition codes
946 reg_class reg_flags(RFLAGS);
947
948 // Class for RVV v0 mask register
949 // https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#53-vector-masking
950 // The mask value used to control execution of a masked vector
951 // instruction is always supplied by vector register v0.
952 reg_class vmask_reg_v0 (
953 V0
954 );
955
956 // Class for RVV mask registers
957 // We need two more vmask registers to do the vector mask logical ops,
958 // so define v30, v31 as mask register too.
959 reg_class vmask_reg (
960 V0,
961 V30,
962 V31
963 );
964 %}
965
966 //----------DEFINITION BLOCK---------------------------------------------------
967 // Define name --> value mappings to inform the ADLC of an integer valued name
968 // Current support includes integer values in the range [0, 0x7FFFFFFF]
969 // Format:
970 // int_def <name> ( <int_value>, <expression>);
971 // Generated Code in ad_<arch>.hpp
972 // #define <name> (<expression>)
973 // // value == <int_value>
974 // Generated code in ad_<arch>.cpp adlc_verification()
975 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
976 //
977
978 // we follow the ppc-aix port in using a simple cost model which ranks
979 // register operations as cheap, memory ops as more expensive and
980 // branches as most expensive. the first two have a low as well as a
981 // normal cost. huge cost appears to be a way of saying don't do
982 // something
983
984 definitions %{
985 // The default cost (of a register move instruction).
986 int_def DEFAULT_COST ( 100, 100);
987 int_def ALU_COST ( 100, 1 * DEFAULT_COST); // unknown, const, arith, shift, slt,
988 // multi, auipc, nop, logical, move
989 int_def LOAD_COST ( 300, 3 * DEFAULT_COST); // load, fpload
990 int_def STORE_COST ( 100, 1 * DEFAULT_COST); // store, fpstore
991 int_def XFER_COST ( 300, 3 * DEFAULT_COST); // mfc, mtc, fcvt, fmove, fcmp
992 int_def FMVX_COST ( 100, 1 * DEFAULT_COST); // shuffles with no conversion
993 int_def BRANCH_COST ( 200, 2 * DEFAULT_COST); // branch, jmp, call
994 int_def IMUL_COST ( 1000, 10 * DEFAULT_COST); // imul
995 int_def IDIVSI_COST ( 3400, 34 * DEFAULT_COST); // idivsi
996 int_def IDIVDI_COST ( 6600, 66 * DEFAULT_COST); // idivdi
997 int_def FMUL_SINGLE_COST ( 500, 5 * DEFAULT_COST); // fmul, fmadd
998 int_def FMUL_DOUBLE_COST ( 700, 7 * DEFAULT_COST); // fmul, fmadd
999 int_def FDIV_COST ( 2000, 20 * DEFAULT_COST); // fdiv
1000 int_def FSQRT_COST ( 2500, 25 * DEFAULT_COST); // fsqrt
1001 int_def VOLATILE_REF_COST ( 1000, 10 * DEFAULT_COST);
1002 int_def CACHE_MISS_COST ( 2000, 20 * DEFAULT_COST); // typicall cache miss penalty
1003 %}
1004
1005
1006
1007 //----------SOURCE BLOCK-------------------------------------------------------
1008 // This is a block of C++ code which provides values, functions, and
1009 // definitions necessary in the rest of the architecture description
1010
1011 source_hpp %{
1012
1013 #include "asm/macroAssembler.hpp"
1014 #include "gc/shared/barrierSetAssembler.hpp"
1015 #include "gc/shared/cardTable.hpp"
1016 #include "gc/shared/cardTableBarrierSet.hpp"
1017 #include "gc/shared/collectedHeap.hpp"
1018 #include "opto/addnode.hpp"
1019 #include "opto/convertnode.hpp"
1020 #include "runtime/objectMonitor.hpp"
1021
1022 extern RegMask _ANY_REG32_mask;
1023 extern RegMask _ANY_REG_mask;
1024 extern RegMask _PTR_REG_mask;
1025 extern RegMask _NO_SPECIAL_REG32_mask;
1026 extern RegMask _NO_SPECIAL_REG_mask;
1027 extern RegMask _NO_SPECIAL_PTR_REG_mask;
1028 extern RegMask _NO_SPECIAL_NO_FP_PTR_REG_mask;
1029
1030 class CallStubImpl {
1031
1032 //--------------------------------------------------------------
1033 //---< Used for optimization in Compile::shorten_branches >---
1034 //--------------------------------------------------------------
1035
1036 public:
1037 // Size of call trampoline stub.
1038 static uint size_call_trampoline() {
1039 return 0; // no call trampolines on this platform
1040 }
1041
1042 // number of relocations needed by a call trampoline stub
1043 static uint reloc_call_trampoline() {
1044 return 0; // no call trampolines on this platform
1045 }
1046 };
1047
1048 class HandlerImpl {
1049
1050 public:
1051
1052 static int emit_exception_handler(C2_MacroAssembler *masm);
1053 static int emit_deopt_handler(C2_MacroAssembler* masm);
1054
1055 static uint size_exception_handler() {
1056 return MacroAssembler::far_branch_size();
1057 }
1058
1059 static uint size_deopt_handler() {
1060 // count auipc + far branch
1061 return NativeInstruction::instruction_size + MacroAssembler::far_branch_size();
1062 }
1063 };
1064
1065 class Node::PD {
1066 public:
1067 enum NodeFlags {
1068 _last_flag = Node::_last_flag
1069 };
1070 };
1071
1072 bool is_CAS(int opcode, bool maybe_volatile);
1073
1074 // predicate controlling translation of CompareAndSwapX
1075 bool needs_acquiring_load_reserved(const Node *load);
1076
1077 // predicate controlling addressing modes
1078 bool size_fits_all_mem_uses(AddPNode* addp, int shift);
1079 %}
1080
1081 source %{
1082
1083 // Derived RegMask with conditionally allocatable registers
1084
1085 RegMask _ANY_REG32_mask;
1086 RegMask _ANY_REG_mask;
1087 RegMask _PTR_REG_mask;
1088 RegMask _NO_SPECIAL_REG32_mask;
1089 RegMask _NO_SPECIAL_REG_mask;
1090 RegMask _NO_SPECIAL_PTR_REG_mask;
1091 RegMask _NO_SPECIAL_NO_FP_PTR_REG_mask;
1092
1093 void reg_mask_init() {
1094
1095 _ANY_REG32_mask = _ALL_REG32_mask;
1096 _ANY_REG32_mask.Remove(OptoReg::as_OptoReg(x0->as_VMReg()));
1097
1098 _ANY_REG_mask = _ALL_REG_mask;
1099 _ANY_REG_mask.SUBTRACT(_ZR_REG_mask);
1100
1101 _PTR_REG_mask = _ALL_REG_mask;
1102 _PTR_REG_mask.SUBTRACT(_ZR_REG_mask);
1103
1104 _NO_SPECIAL_REG32_mask = _ALL_REG32_mask;
1105 _NO_SPECIAL_REG32_mask.SUBTRACT(_NON_ALLOCATABLE_REG32_mask);
1106
1107 _NO_SPECIAL_REG_mask = _ALL_REG_mask;
1108 _NO_SPECIAL_REG_mask.SUBTRACT(_NON_ALLOCATABLE_REG_mask);
1109
1110 _NO_SPECIAL_PTR_REG_mask = _ALL_REG_mask;
1111 _NO_SPECIAL_PTR_REG_mask.SUBTRACT(_NON_ALLOCATABLE_REG_mask);
1112
1113 // x27 is not allocatable when compressed oops is on
1114 if (UseCompressedOops) {
1115 _NO_SPECIAL_REG32_mask.Remove(OptoReg::as_OptoReg(x27->as_VMReg()));
1116 _NO_SPECIAL_REG_mask.Remove(OptoReg::as_OptoReg(x27->as_VMReg()));
1117 _NO_SPECIAL_PTR_REG_mask.Remove(OptoReg::as_OptoReg(x27->as_VMReg()));
1118 }
1119
1120 // x8 is not allocatable when PreserveFramePointer is on
1121 if (PreserveFramePointer) {
1122 _NO_SPECIAL_REG32_mask.Remove(OptoReg::as_OptoReg(x8->as_VMReg()));
1123 _NO_SPECIAL_REG_mask.Remove(OptoReg::as_OptoReg(x8->as_VMReg()));
1124 _NO_SPECIAL_PTR_REG_mask.Remove(OptoReg::as_OptoReg(x8->as_VMReg()));
1125 }
1126
1127 _NO_SPECIAL_NO_FP_PTR_REG_mask = _NO_SPECIAL_PTR_REG_mask;
1128 _NO_SPECIAL_NO_FP_PTR_REG_mask.Remove(OptoReg::as_OptoReg(x8->as_VMReg()));
1129 }
1130
1131 void PhaseOutput::pd_perform_mach_node_analysis() {
1132 }
1133
1134 int MachNode::pd_alignment_required() const {
1135 return 1;
1136 }
1137
1138 int MachNode::compute_padding(int current_offset) const {
1139 return 0;
1140 }
1141
1142 // is_CAS(int opcode, bool maybe_volatile)
1143 //
1144 // return true if opcode is one of the possible CompareAndSwapX
1145 // values otherwise false.
1146 bool is_CAS(int opcode, bool maybe_volatile)
1147 {
1148 switch (opcode) {
1149 // We handle these
1150 case Op_CompareAndSwapI:
1151 case Op_CompareAndSwapL:
1152 case Op_CompareAndSwapP:
1153 case Op_CompareAndSwapN:
1154 case Op_ShenandoahCompareAndSwapP:
1155 case Op_ShenandoahCompareAndSwapN:
1156 case Op_CompareAndSwapB:
1157 case Op_CompareAndSwapS:
1158 case Op_GetAndSetI:
1159 case Op_GetAndSetL:
1160 case Op_GetAndSetP:
1161 case Op_GetAndSetN:
1162 case Op_GetAndAddI:
1163 case Op_GetAndAddL:
1164 return true;
1165 case Op_CompareAndExchangeI:
1166 case Op_CompareAndExchangeN:
1167 case Op_CompareAndExchangeB:
1168 case Op_CompareAndExchangeS:
1169 case Op_CompareAndExchangeL:
1170 case Op_CompareAndExchangeP:
1171 case Op_WeakCompareAndSwapB:
1172 case Op_WeakCompareAndSwapS:
1173 case Op_WeakCompareAndSwapI:
1174 case Op_WeakCompareAndSwapL:
1175 case Op_WeakCompareAndSwapP:
1176 case Op_WeakCompareAndSwapN:
1177 case Op_ShenandoahWeakCompareAndSwapP:
1178 case Op_ShenandoahWeakCompareAndSwapN:
1179 case Op_ShenandoahCompareAndExchangeP:
1180 case Op_ShenandoahCompareAndExchangeN:
1181 return maybe_volatile;
1182 default:
1183 return false;
1184 }
1185 }
1186
1187 // predicate controlling translation of CAS
1188 //
1189 // returns true if CAS needs to use an acquiring load otherwise false
1190 bool needs_acquiring_load_reserved(const Node *n)
1191 {
1192 assert(n != nullptr && is_CAS(n->Opcode(), true), "expecting a compare and swap");
1193
1194 LoadStoreNode* ldst = n->as_LoadStore();
1195 if (n != nullptr && is_CAS(n->Opcode(), false)) {
1196 assert(ldst != nullptr && ldst->trailing_membar() != nullptr, "expected trailing membar");
1197 } else {
1198 return ldst != nullptr && ldst->trailing_membar() != nullptr;
1199 }
1200 // so we can just return true here
1201 return true;
1202 }
1203 #define __ masm->
1204
1205 // advance declarations for helper functions to convert register
1206 // indices to register objects
1207
1208 // the ad file has to provide implementations of certain methods
1209 // expected by the generic code
1210 //
1211 // REQUIRED FUNCTIONALITY
1212
1213 //=============================================================================
1214
1215 // !!!!! Special hack to get all types of calls to specify the byte offset
1216 // from the start of the call to the point where the return address
1217 // will point.
1218
1219 int MachCallStaticJavaNode::ret_addr_offset()
1220 {
1221 return 3 * NativeInstruction::instruction_size; // auipc + ld + jalr
1222 }
1223
1224 int MachCallDynamicJavaNode::ret_addr_offset()
1225 {
1226 return NativeMovConstReg::movptr2_instruction_size + (3 * NativeInstruction::instruction_size); // movptr2, auipc + ld + jal
1227 }
1228
1229 int MachCallRuntimeNode::ret_addr_offset() {
1230 // For address inside the code cache the call will be:
1231 // auipc + jalr
1232 // For real runtime callouts it will be 8 instructions
1233 // see riscv_enc_java_to_runtime
1234 // la(t0, retaddr) -> auipc + addi
1235 // sd(t0, Address(xthread, JavaThread::last_Java_pc_offset())) -> sd
1236 // movptr(t1, addr, offset, t0) -> lui + lui + slli + add
1237 // jalr(t1, offset) -> jalr
1238 if (CodeCache::contains(_entry_point)) {
1239 return 2 * NativeInstruction::instruction_size;
1240 } else {
1241 return 8 * NativeInstruction::instruction_size;
1242 }
1243 }
1244
1245 //
1246 // Compute padding required for nodes which need alignment
1247 //
1248
1249 // With RVC a call instruction may get 2-byte aligned.
1250 // The address of the call instruction needs to be 4-byte aligned to
1251 // ensure that it does not span a cache line so that it can be patched.
1252 int CallStaticJavaDirectNode::compute_padding(int current_offset) const
1253 {
1254 // to make sure the address of jal 4-byte aligned.
1255 return align_up(current_offset, alignment_required()) - current_offset;
1256 }
1257
1258 // With RVC a call instruction may get 2-byte aligned.
1259 // The address of the call instruction needs to be 4-byte aligned to
1260 // ensure that it does not span a cache line so that it can be patched.
1261 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const
1262 {
1263 // skip the movptr2 in MacroAssembler::ic_call():
1264 // lui, lui, slli, add, addi
1265 // Though movptr2() has already 4-byte aligned with or without RVC,
1266 // We need to prevent from further changes by explicitly calculating the size.
1267 current_offset += NativeMovConstReg::movptr2_instruction_size;
1268 // to make sure the address of jal 4-byte aligned.
1269 return align_up(current_offset, alignment_required()) - current_offset;
1270 }
1271
1272 //=============================================================================
1273
1274 #ifndef PRODUCT
1275 void MachBreakpointNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1276 assert_cond(st != nullptr);
1277 st->print("BREAKPOINT");
1278 }
1279 #endif
1280
1281 void MachBreakpointNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
1282 __ ebreak();
1283 }
1284
1285 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
1286 return MachNode::size(ra_);
1287 }
1288
1289 //=============================================================================
1290
1291 #ifndef PRODUCT
1292 void MachNopNode::format(PhaseRegAlloc*, outputStream* st) const {
1293 st->print("nop \t# %d bytes pad for loops and calls", _count);
1294 }
1295 #endif
1296
1297 void MachNopNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc*) const {
1298 Assembler::CompressibleRegion cr(masm); // nops shall be 2-byte under RVC for alignment purposes.
1299 for (int i = 0; i < _count; i++) {
1300 __ nop();
1301 }
1302 }
1303
1304 uint MachNopNode::size(PhaseRegAlloc*) const {
1305 return _count * (UseRVC ? NativeInstruction::compressed_instruction_size : NativeInstruction::instruction_size);
1306 }
1307
1308 //=============================================================================
1309 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;
1310
1311 int ConstantTable::calculate_table_base_offset() const {
1312 return 0; // absolute addressing, no offset
1313 }
1314
1315 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
1316 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
1317 ShouldNotReachHere();
1318 }
1319
1320 void MachConstantBaseNode::emit(C2_MacroAssembler* masm, PhaseRegAlloc* ra_) const {
1321 // Empty encoding
1322 }
1323
1324 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
1325 return 0;
1326 }
1327
1328 #ifndef PRODUCT
1329 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1330 assert_cond(st != nullptr);
1331 st->print("-- \t// MachConstantBaseNode (empty encoding)");
1332 }
1333 #endif
1334
1335 #ifndef PRODUCT
1336 void MachPrologNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1337 assert_cond(st != nullptr && ra_ != nullptr);
1338 Compile* C = ra_->C;
1339
1340 int framesize = C->output()->frame_slots() << LogBytesPerInt;
1341
1342 if (C->output()->need_stack_bang(framesize)) {
1343 st->print("# stack bang size=%d\n\t", framesize);
1344 }
1345
1346 st->print("sd fp, [sp, #%d]\n\t", - 2 * wordSize);
1347 st->print("sd ra, [sp, #%d]\n\t", - wordSize);
1348 if (PreserveFramePointer) { st->print("sub fp, sp, #%d\n\t", 2 * wordSize); }
1349 st->print("sub sp, sp, #%d\n\t", framesize);
1350
1351 if (C->stub_function() == nullptr) {
1352 st->print("ld t0, [guard]\n\t");
1353 st->print("membar LoadLoad\n\t");
1354 st->print("ld t1, [xthread, #thread_disarmed_guard_value_offset]\n\t");
1355 st->print("beq t0, t1, skip\n\t");
1356 st->print("jalr #nmethod_entry_barrier_stub\n\t");
1357 st->print("j skip\n\t");
1358 st->print("guard: int\n\t");
1359 st->print("skip:\n\t");
1360 }
1361 }
1362 #endif
1363
1364 void MachPrologNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
1365 assert_cond(ra_ != nullptr);
1366 Compile* C = ra_->C;
1367
1368 // n.b. frame size includes space for return pc and fp
1369 const int framesize = C->output()->frame_size_in_bytes();
1370
1371 // insert a nop at the start of the prolog so we can patch in a
1372 // branch if we need to invalidate the method later
1373 {
1374 Assembler::IncompressibleRegion ir(masm); // keep the nop as 4 bytes for patching.
1375 MacroAssembler::assert_alignment(__ pc());
1376 __ nop(); // 4 bytes
1377 }
1378
1379 assert_cond(C != nullptr);
1380
1381 if (C->clinit_barrier_on_entry()) {
1382 assert(!C->method()->holder()->is_not_initialized(), "initialization should have been started");
1383
1384 Label L_skip_barrier;
1385
1386 __ mov_metadata(t1, C->method()->holder()->constant_encoding());
1387 __ clinit_barrier(t1, t0, &L_skip_barrier);
1388 __ far_jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub()));
1389 __ bind(L_skip_barrier);
1390 }
1391
1392 int bangsize = C->output()->bang_size_in_bytes();
1393 if (C->output()->need_stack_bang(bangsize)) {
1394 __ generate_stack_overflow_check(bangsize);
1395 }
1396
1397 __ build_frame(framesize);
1398
1399 if (C->stub_function() == nullptr) {
1400 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
1401 // Dummy labels for just measuring the code size
1402 Label dummy_slow_path;
1403 Label dummy_continuation;
1404 Label dummy_guard;
1405 Label* slow_path = &dummy_slow_path;
1406 Label* continuation = &dummy_continuation;
1407 Label* guard = &dummy_guard;
1408 if (!Compile::current()->output()->in_scratch_emit_size()) {
1409 // Use real labels from actual stub when not emitting code for purpose of measuring its size
1410 C2EntryBarrierStub* stub = new (Compile::current()->comp_arena()) C2EntryBarrierStub();
1411 Compile::current()->output()->add_stub(stub);
1412 slow_path = &stub->entry();
1413 continuation = &stub->continuation();
1414 guard = &stub->guard();
1415 }
1416 // In the C2 code, we move the non-hot part of nmethod entry barriers out-of-line to a stub.
1417 bs->nmethod_entry_barrier(masm, slow_path, continuation, guard);
1418 }
1419
1420 if (VerifyStackAtCalls) {
1421 Unimplemented();
1422 }
1423
1424 C->output()->set_frame_complete(__ offset());
1425
1426 if (C->has_mach_constant_base_node()) {
1427 // NOTE: We set the table base offset here because users might be
1428 // emitted before MachConstantBaseNode.
1429 ConstantTable& constant_table = C->output()->constant_table();
1430 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
1431 }
1432 }
1433
1434 uint MachPrologNode::size(PhaseRegAlloc* ra_) const
1435 {
1436 assert_cond(ra_ != nullptr);
1437 return MachNode::size(ra_); // too many variables; just compute it
1438 // the hard way
1439 }
1440
1441 int MachPrologNode::reloc() const
1442 {
1443 return 0;
1444 }
1445
1446 //=============================================================================
1447
1448 #ifndef PRODUCT
1449 void MachEpilogNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1450 assert_cond(st != nullptr && ra_ != nullptr);
1451 Compile* C = ra_->C;
1452 assert_cond(C != nullptr);
1453 int framesize = C->output()->frame_size_in_bytes();
1454
1455 st->print("# pop frame %d\n\t", framesize);
1456
1457 if (framesize == 0) {
1458 st->print("ld ra, [sp,#%d]\n\t", (2 * wordSize));
1459 st->print("ld fp, [sp,#%d]\n\t", (3 * wordSize));
1460 st->print("add sp, sp, #%d\n\t", (2 * wordSize));
1461 } else {
1462 st->print("add sp, sp, #%d\n\t", framesize);
1463 st->print("ld ra, [sp,#%d]\n\t", - 2 * wordSize);
1464 st->print("ld fp, [sp,#%d]\n\t", - wordSize);
1465 }
1466
1467 if (do_polling() && C->is_method_compilation()) {
1468 st->print("# test polling word\n\t");
1469 st->print("ld t0, [xthread,#%d]\n\t", in_bytes(JavaThread::polling_word_offset()));
1470 st->print("bgtu sp, t0, #slow_path");
1471 }
1472 }
1473 #endif
1474
1475 void MachEpilogNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
1476 assert_cond(ra_ != nullptr);
1477 Compile* C = ra_->C;
1478 assert_cond(C != nullptr);
1479 int framesize = C->output()->frame_size_in_bytes();
1480
1481 __ remove_frame(framesize);
1482
1483 if (StackReservedPages > 0 && C->has_reserved_stack_access()) {
1484 __ reserved_stack_check();
1485 }
1486
1487 if (do_polling() && C->is_method_compilation()) {
1488 Label dummy_label;
1489 Label* code_stub = &dummy_label;
1490 if (!C->output()->in_scratch_emit_size()) {
1491 C2SafepointPollStub* stub = new (C->comp_arena()) C2SafepointPollStub(__ offset());
1492 C->output()->add_stub(stub);
1493 code_stub = &stub->entry();
1494 }
1495 __ relocate(relocInfo::poll_return_type);
1496 __ safepoint_poll(*code_stub, true /* at_return */, false /* acquire */, true /* in_nmethod */);
1497 }
1498 }
1499
1500 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
1501 assert_cond(ra_ != nullptr);
1502 // Variable size. Determine dynamically.
1503 return MachNode::size(ra_);
1504 }
1505
1506 int MachEpilogNode::reloc() const {
1507 // Return number of relocatable values contained in this instruction.
1508 return 1; // 1 for polling page.
1509 }
1510 const Pipeline * MachEpilogNode::pipeline() const {
1511 return MachNode::pipeline_class();
1512 }
1513
1514 //=============================================================================
1515
1516 // Figure out which register class each belongs in: rc_int, rc_float or
1517 // rc_stack.
1518 enum RC { rc_bad, rc_int, rc_float, rc_vector, rc_stack };
1519
1520 static enum RC rc_class(OptoReg::Name reg) {
1521
1522 if (reg == OptoReg::Bad) {
1523 return rc_bad;
1524 }
1525
1526 // we have 30 int registers * 2 halves
1527 // (t0 and t1 are omitted)
1528 int slots_of_int_registers = Register::max_slots_per_register * (Register::number_of_registers - 2);
1529 if (reg < slots_of_int_registers) {
1530 return rc_int;
1531 }
1532
1533 // we have 32 float register * 2 halves
1534 int slots_of_float_registers = FloatRegister::max_slots_per_register * FloatRegister::number_of_registers;
1535 if (reg < slots_of_int_registers + slots_of_float_registers) {
1536 return rc_float;
1537 }
1538
1539 // we have 32 vector register * 4 halves
1540 int slots_of_vector_registers = VectorRegister::max_slots_per_register * VectorRegister::number_of_registers;
1541 if (reg < slots_of_int_registers + slots_of_float_registers + slots_of_vector_registers) {
1542 return rc_vector;
1543 }
1544
1545 // Between vector regs & stack is the flags regs.
1546 assert(OptoReg::is_stack(reg), "blow up if spilling flags");
1547
1548 return rc_stack;
1549 }
1550
1551 uint MachSpillCopyNode::implementation(C2_MacroAssembler *masm, PhaseRegAlloc *ra_, bool do_size, outputStream *st) const {
1552 assert_cond(ra_ != nullptr);
1553 Compile* C = ra_->C;
1554
1555 // Get registers to move.
1556 OptoReg::Name src_hi = ra_->get_reg_second(in(1));
1557 OptoReg::Name src_lo = ra_->get_reg_first(in(1));
1558 OptoReg::Name dst_hi = ra_->get_reg_second(this);
1559 OptoReg::Name dst_lo = ra_->get_reg_first(this);
1560
1561 enum RC src_hi_rc = rc_class(src_hi);
1562 enum RC src_lo_rc = rc_class(src_lo);
1563 enum RC dst_hi_rc = rc_class(dst_hi);
1564 enum RC dst_lo_rc = rc_class(dst_lo);
1565
1566 assert(src_lo != OptoReg::Bad && dst_lo != OptoReg::Bad, "must move at least 1 register");
1567
1568 if (src_hi != OptoReg::Bad && !bottom_type()->isa_vectmask()) {
1569 assert((src_lo & 1) == 0 && src_lo + 1 == src_hi &&
1570 (dst_lo & 1) == 0 && dst_lo + 1 == dst_hi,
1571 "expected aligned-adjacent pairs");
1572 }
1573
1574 if (src_lo == dst_lo && src_hi == dst_hi) {
1575 return 0; // Self copy, no move.
1576 }
1577
1578 bool is64 = (src_lo & 1) == 0 && src_lo + 1 == src_hi &&
1579 (dst_lo & 1) == 0 && dst_lo + 1 == dst_hi;
1580 int src_offset = ra_->reg2offset(src_lo);
1581 int dst_offset = ra_->reg2offset(dst_lo);
1582
1583 if (bottom_type()->isa_vect() != nullptr) {
1584 uint ireg = ideal_reg();
1585 if (ireg == Op_VecA && masm) {
1586 int vector_reg_size_in_bytes = Matcher::scalable_vector_reg_size(T_BYTE);
1587 if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
1588 // stack to stack
1589 __ spill_copy_vector_stack_to_stack(src_offset, dst_offset,
1590 vector_reg_size_in_bytes);
1591 } else if (src_lo_rc == rc_vector && dst_lo_rc == rc_stack) {
1592 // vpr to stack
1593 __ spill(as_VectorRegister(Matcher::_regEncode[src_lo]), ra_->reg2offset(dst_lo));
1594 } else if (src_lo_rc == rc_stack && dst_lo_rc == rc_vector) {
1595 // stack to vpr
1596 __ unspill(as_VectorRegister(Matcher::_regEncode[dst_lo]), ra_->reg2offset(src_lo));
1597 } else if (src_lo_rc == rc_vector && dst_lo_rc == rc_vector) {
1598 // vpr to vpr
1599 __ vsetvli_helper(T_BYTE, MaxVectorSize);
1600 __ vmv_v_v(as_VectorRegister(Matcher::_regEncode[dst_lo]), as_VectorRegister(Matcher::_regEncode[src_lo]));
1601 } else {
1602 ShouldNotReachHere();
1603 }
1604 } else if (bottom_type()->isa_vectmask() && masm) {
1605 int vmask_size_in_bytes = Matcher::scalable_predicate_reg_slots() * 32 / 8;
1606 if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
1607 // stack to stack
1608 __ spill_copy_vmask_stack_to_stack(src_offset, dst_offset,
1609 vmask_size_in_bytes);
1610 } else if (src_lo_rc == rc_vector && dst_lo_rc == rc_stack) {
1611 // vmask to stack
1612 __ spill_vmask(as_VectorRegister(Matcher::_regEncode[src_lo]), ra_->reg2offset(dst_lo));
1613 } else if (src_lo_rc == rc_stack && dst_lo_rc == rc_vector) {
1614 // stack to vmask
1615 __ unspill_vmask(as_VectorRegister(Matcher::_regEncode[dst_lo]), ra_->reg2offset(src_lo));
1616 } else if (src_lo_rc == rc_vector && dst_lo_rc == rc_vector) {
1617 // vmask to vmask
1618 __ vsetvli_helper(T_BYTE, MaxVectorSize >> 3);
1619 __ vmv_v_v(as_VectorRegister(Matcher::_regEncode[dst_lo]), as_VectorRegister(Matcher::_regEncode[src_lo]));
1620 } else {
1621 ShouldNotReachHere();
1622 }
1623 }
1624 } else if (masm != nullptr) {
1625 switch (src_lo_rc) {
1626 case rc_int:
1627 if (dst_lo_rc == rc_int) { // gpr --> gpr copy
1628 if (!is64 && this->ideal_reg() != Op_RegI) { // zero extended for narrow oop or klass
1629 __ zext(as_Register(Matcher::_regEncode[dst_lo]), as_Register(Matcher::_regEncode[src_lo]), 32);
1630 } else {
1631 __ mv(as_Register(Matcher::_regEncode[dst_lo]), as_Register(Matcher::_regEncode[src_lo]));
1632 }
1633 } else if (dst_lo_rc == rc_float) { // gpr --> fpr copy
1634 if (is64) {
1635 __ fmv_d_x(as_FloatRegister(Matcher::_regEncode[dst_lo]),
1636 as_Register(Matcher::_regEncode[src_lo]));
1637 } else {
1638 __ fmv_w_x(as_FloatRegister(Matcher::_regEncode[dst_lo]),
1639 as_Register(Matcher::_regEncode[src_lo]));
1640 }
1641 } else { // gpr --> stack spill
1642 assert(dst_lo_rc == rc_stack, "spill to bad register class");
1643 __ spill(as_Register(Matcher::_regEncode[src_lo]), is64, dst_offset);
1644 }
1645 break;
1646 case rc_float:
1647 if (dst_lo_rc == rc_int) { // fpr --> gpr copy
1648 if (is64) {
1649 __ fmv_x_d(as_Register(Matcher::_regEncode[dst_lo]),
1650 as_FloatRegister(Matcher::_regEncode[src_lo]));
1651 } else {
1652 __ fmv_x_w(as_Register(Matcher::_regEncode[dst_lo]),
1653 as_FloatRegister(Matcher::_regEncode[src_lo]));
1654 }
1655 } else if (dst_lo_rc == rc_float) { // fpr --> fpr copy
1656 if (is64) {
1657 __ fmv_d(as_FloatRegister(Matcher::_regEncode[dst_lo]),
1658 as_FloatRegister(Matcher::_regEncode[src_lo]));
1659 } else {
1660 __ fmv_s(as_FloatRegister(Matcher::_regEncode[dst_lo]),
1661 as_FloatRegister(Matcher::_regEncode[src_lo]));
1662 }
1663 } else { // fpr --> stack spill
1664 assert(dst_lo_rc == rc_stack, "spill to bad register class");
1665 __ spill(as_FloatRegister(Matcher::_regEncode[src_lo]),
1666 is64, dst_offset);
1667 }
1668 break;
1669 case rc_stack:
1670 if (dst_lo_rc == rc_int) { // stack --> gpr load
1671 if (this->ideal_reg() == Op_RegI) {
1672 __ unspill(as_Register(Matcher::_regEncode[dst_lo]), is64, src_offset);
1673 } else { // // zero extended for narrow oop or klass
1674 __ unspillu(as_Register(Matcher::_regEncode[dst_lo]), is64, src_offset);
1675 }
1676 } else if (dst_lo_rc == rc_float) { // stack --> fpr load
1677 __ unspill(as_FloatRegister(Matcher::_regEncode[dst_lo]),
1678 is64, src_offset);
1679 } else { // stack --> stack copy
1680 assert(dst_lo_rc == rc_stack, "spill to bad register class");
1681 if (this->ideal_reg() == Op_RegI) {
1682 __ unspill(t0, is64, src_offset);
1683 } else { // zero extended for narrow oop or klass
1684 __ unspillu(t0, is64, src_offset);
1685 }
1686 __ spill(t0, is64, dst_offset);
1687 }
1688 break;
1689 default:
1690 ShouldNotReachHere();
1691 }
1692 }
1693
1694 if (st != nullptr) {
1695 st->print("spill ");
1696 if (src_lo_rc == rc_stack) {
1697 st->print("[sp, #%d] -> ", src_offset);
1698 } else {
1699 st->print("%s -> ", Matcher::regName[src_lo]);
1700 }
1701 if (dst_lo_rc == rc_stack) {
1702 st->print("[sp, #%d]", dst_offset);
1703 } else {
1704 st->print("%s", Matcher::regName[dst_lo]);
1705 }
1706 if (bottom_type()->isa_vect() && !bottom_type()->isa_vectmask()) {
1707 int vsize = 0;
1708 if (ideal_reg() == Op_VecA) {
1709 vsize = Matcher::scalable_vector_reg_size(T_BYTE) * 8;
1710 } else {
1711 ShouldNotReachHere();
1712 }
1713 st->print("\t# vector spill size = %d", vsize);
1714 } else if (ideal_reg() == Op_RegVectMask) {
1715 assert(Matcher::supports_scalable_vector(), "bad register type for spill");
1716 int vsize = Matcher::scalable_predicate_reg_slots() * 32;
1717 st->print("\t# vmask spill size = %d", vsize);
1718 } else {
1719 st->print("\t# spill size = %d", is64 ? 64 : 32);
1720 }
1721 }
1722
1723 return 0;
1724 }
1725
1726 #ifndef PRODUCT
1727 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1728 if (ra_ == nullptr) {
1729 st->print("N%d = SpillCopy(N%d)", _idx, in(1)->_idx);
1730 } else {
1731 implementation(nullptr, ra_, false, st);
1732 }
1733 }
1734 #endif
1735
1736 void MachSpillCopyNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
1737 implementation(masm, ra_, false, nullptr);
1738 }
1739
1740 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1741 return MachNode::size(ra_);
1742 }
1743
1744 //=============================================================================
1745
1746 #ifndef PRODUCT
1747 void BoxLockNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1748 assert_cond(ra_ != nullptr && st != nullptr);
1749 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1750 int reg = ra_->get_reg_first(this);
1751 st->print("add %s, sp, #%d\t# box lock",
1752 Matcher::regName[reg], offset);
1753 }
1754 #endif
1755
1756 void BoxLockNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
1757 Assembler::IncompressibleRegion ir(masm); // Fixed length: see BoxLockNode::size()
1758
1759 assert_cond(ra_ != nullptr);
1760 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1761 int reg = ra_->get_encode(this);
1762
1763 if (Assembler::is_simm12(offset)) {
1764 __ addi(as_Register(reg), sp, offset);
1765 } else {
1766 __ li32(t0, offset);
1767 __ add(as_Register(reg), sp, t0);
1768 }
1769 }
1770
1771 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1772 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_).
1773 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1774
1775 if (Assembler::is_simm12(offset)) {
1776 return NativeInstruction::instruction_size;
1777 } else {
1778 return 3 * NativeInstruction::instruction_size; // lui + addiw + add;
1779 }
1780 }
1781
1782 //=============================================================================
1783
1784 #ifndef PRODUCT
1785 void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1786 {
1787 assert_cond(st != nullptr);
1788 st->print_cr("# MachUEPNode");
1789 if (UseCompressedClassPointers) {
1790 st->print_cr("\tlwu t1, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass");
1791 st->print_cr("\tlwu t2, [t0 + CompiledICData::speculated_klass_offset()]\t# compressed klass");
1792 } else {
1793 st->print_cr("\tld t1, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass");
1794 st->print_cr("\tld t2, [t0 + CompiledICData::speculated_klass_offset()]\t# compressed klass");
1795 }
1796 st->print_cr("\tbeq t1, t2, ic_hit");
1797 st->print_cr("\tj, SharedRuntime::_ic_miss_stub\t # Inline cache check");
1798 st->print_cr("\tic_hit:");
1799 }
1800 #endif
1801
1802 void MachUEPNode::emit(C2_MacroAssembler* masm, PhaseRegAlloc* ra_) const
1803 {
1804 // This is the unverified entry point.
1805 __ ic_check(CodeEntryAlignment);
1806
1807 // Verified entry point must be properly 4 bytes aligned for patching by NativeJump::patch_verified_entry().
1808 // ic_check() aligns to CodeEntryAlignment >= InteriorEntryAlignment(min 16) > NativeInstruction::instruction_size(4).
1809 assert(((__ offset()) % CodeEntryAlignment) == 0, "Misaligned verified entry point");
1810 }
1811
1812 uint MachUEPNode::size(PhaseRegAlloc* ra_) const
1813 {
1814 assert_cond(ra_ != nullptr);
1815 return MachNode::size(ra_);
1816 }
1817
1818 // REQUIRED EMIT CODE
1819
1820 //=============================================================================
1821
1822 // Emit exception handler code.
1823 int HandlerImpl::emit_exception_handler(C2_MacroAssembler* masm)
1824 {
1825 // auipc t1, #exception_blob_entry_point
1826 // jr (offset)t1
1827 // Note that the code buffer's insts_mark is always relative to insts.
1828 // That's why we must use the macroassembler to generate a handler.
1829 address base = __ start_a_stub(size_exception_handler());
1830 if (base == nullptr) {
1831 ciEnv::current()->record_failure("CodeCache is full");
1832 return 0; // CodeBuffer::expand failed
1833 }
1834 int offset = __ offset();
1835 __ far_jump(RuntimeAddress(OptoRuntime::exception_blob()->entry_point()));
1836 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1837 __ end_a_stub();
1838 return offset;
1839 }
1840
1841 // Emit deopt handler code.
1842 int HandlerImpl::emit_deopt_handler(C2_MacroAssembler* masm)
1843 {
1844 address base = __ start_a_stub(size_deopt_handler());
1845 if (base == nullptr) {
1846 ciEnv::current()->record_failure("CodeCache is full");
1847 return 0; // CodeBuffer::expand failed
1848 }
1849 int offset = __ offset();
1850
1851 __ auipc(ra, 0);
1852 __ far_jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
1853
1854 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1855 __ end_a_stub();
1856 return offset;
1857
1858 }
1859 // REQUIRED MATCHER CODE
1860
1861 //=============================================================================
1862
1863 bool Matcher::match_rule_supported(int opcode) {
1864 if (!has_match_rule(opcode)) {
1865 return false;
1866 }
1867
1868 switch (opcode) {
1869 case Op_OnSpinWait:
1870 return VM_Version::supports_on_spin_wait();
1871 case Op_CacheWB: // fall through
1872 case Op_CacheWBPreSync: // fall through
1873 case Op_CacheWBPostSync:
1874 if (!VM_Version::supports_data_cache_line_flush()) {
1875 return false;
1876 }
1877 break;
1878
1879 case Op_StrCompressedCopy: // fall through
1880 case Op_StrInflatedCopy: // fall through
1881 case Op_CountPositives: // fall through
1882 case Op_EncodeISOArray:
1883 return UseRVV;
1884
1885 // Current test shows that, it brings performance gain when MaxVectorSize >= 32, but brings
1886 // regression when MaxVectorSize == 16. So only enable the intrinsic when MaxVectorSize >= 32.
1887 case Op_RoundVF:
1888 return UseRVV && MaxVectorSize >= 32;
1889
1890 // For double, current test shows that even with MaxVectorSize == 32, there is still some regression.
1891 // Although there is no hardware to verify it for now, from the trend of performance data on hardwares
1892 // (with vlenb == 16 and 32 respectively), it's promising to bring better performance rather than
1893 // regression for double when MaxVectorSize == 64+. So only enable the intrinsic when MaxVectorSize >= 64.
1894 case Op_RoundVD:
1895 return UseRVV && MaxVectorSize >= 64;
1896
1897 case Op_PopCountI:
1898 case Op_PopCountL:
1899 return UsePopCountInstruction;
1900
1901 case Op_ReverseI:
1902 case Op_ReverseL:
1903 return UseZbkb;
1904
1905 case Op_ReverseBytesI:
1906 case Op_ReverseBytesL:
1907 case Op_ReverseBytesS:
1908 case Op_ReverseBytesUS:
1909 case Op_RotateRight:
1910 case Op_RotateLeft:
1911 case Op_CountLeadingZerosI:
1912 case Op_CountLeadingZerosL:
1913 case Op_CountTrailingZerosI:
1914 case Op_CountTrailingZerosL:
1915 return UseZbb;
1916
1917 case Op_FmaF:
1918 case Op_FmaD:
1919 case Op_FmaVF:
1920 case Op_FmaVD:
1921 return UseFMA;
1922
1923 case Op_ConvHF2F:
1924 case Op_ConvF2HF:
1925 return VM_Version::supports_float16_float_conversion();
1926 case Op_ReinterpretS2HF:
1927 case Op_ReinterpretHF2S:
1928 return UseZfh || UseZfhmin;
1929 case Op_AddHF:
1930 case Op_DivHF:
1931 case Op_FmaHF:
1932 case Op_MaxHF:
1933 case Op_MinHF:
1934 case Op_MulHF:
1935 case Op_SubHF:
1936 case Op_SqrtHF:
1937 return UseZfh;
1938
1939 case Op_CMoveF:
1940 case Op_CMoveD:
1941 case Op_CMoveP:
1942 case Op_CMoveN:
1943 return false;
1944 }
1945
1946 return true; // Per default match rules are supported.
1947 }
1948
1949 const RegMask* Matcher::predicate_reg_mask(void) {
1950 return &_VMASK_REG_mask;
1951 }
1952
1953 // Vector calling convention not yet implemented.
1954 bool Matcher::supports_vector_calling_convention(void) {
1955 return EnableVectorSupport;
1956 }
1957
1958 OptoRegPair Matcher::vector_return_value(uint ideal_reg) {
1959 assert(EnableVectorSupport, "sanity");
1960 assert(ideal_reg == Op_VecA, "sanity");
1961 // check more info at https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-cc.adoc
1962 int lo = V8_num;
1963 int hi = V8_K_num;
1964 return OptoRegPair(hi, lo);
1965 }
1966
1967 // Is this branch offset short enough that a short branch can be used?
1968 //
1969 // NOTE: If the platform does not provide any short branch variants, then
1970 // this method should return false for offset 0.
1971 // |---label(L1)-----|
1972 // |-----------------|
1973 // |-----------------|----------eq: float-------------------
1974 // |-----------------| // far_cmpD_branch | cmpD_branch
1975 // |------- ---------| feq; | feq;
1976 // |-far_cmpD_branch-| beqz done; | bnez L;
1977 // |-----------------| j L; |
1978 // |-----------------| bind(done); |
1979 // |-----------------|--------------------------------------
1980 // |-----------------| // so shortBrSize = br_size - 4;
1981 // |-----------------| // so offs = offset - shortBrSize + 4;
1982 // |---label(L2)-----|
1983 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1984 // The passed offset is relative to address of the branch.
1985 int shortBrSize = br_size - 4;
1986 int offs = offset - shortBrSize + 4;
1987 return (-4096 <= offs && offs < 4096);
1988 }
1989
1990 // Vector width in bytes.
1991 int Matcher::vector_width_in_bytes(BasicType bt) {
1992 if (UseRVV) {
1993 // The MaxVectorSize should have been set by detecting RVV max vector register size when check UseRVV.
1994 // MaxVectorSize == VM_Version::_initial_vector_length
1995 int size = MaxVectorSize;
1996 // Minimum 2 values in vector
1997 if (size < 2 * type2aelembytes(bt)) size = 0;
1998 // But never < 4
1999 if (size < 4) size = 0;
2000 return size;
2001 }
2002 return 0;
2003 }
2004
2005 // Limits on vector size (number of elements) loaded into vector.
2006 int Matcher::max_vector_size(const BasicType bt) {
2007 return vector_width_in_bytes(bt) / type2aelembytes(bt);
2008 }
2009
2010 int Matcher::min_vector_size(const BasicType bt) {
2011 int max_size = max_vector_size(bt);
2012 // Limit the min vector size to 8 bytes.
2013 int size = 8 / type2aelembytes(bt);
2014 if (bt == T_BYTE) {
2015 // To support vector api shuffle/rearrange.
2016 size = 4;
2017 } else if (bt == T_BOOLEAN) {
2018 // To support vector api load/store mask.
2019 size = 2;
2020 }
2021 if (size < 2) size = 2;
2022 return MIN2(size, max_size);
2023 }
2024
2025 int Matcher::max_vector_size_auto_vectorization(const BasicType bt) {
2026 return Matcher::max_vector_size(bt);
2027 }
2028
2029 // Vector ideal reg.
2030 uint Matcher::vector_ideal_reg(int len) {
2031 assert(MaxVectorSize >= len, "");
2032 if (UseRVV) {
2033 return Op_VecA;
2034 }
2035
2036 ShouldNotReachHere();
2037 return 0;
2038 }
2039
2040 int Matcher::scalable_vector_reg_size(const BasicType bt) {
2041 return Matcher::max_vector_size(bt);
2042 }
2043
2044 MachOper* Matcher::pd_specialize_generic_vector_operand(MachOper* original_opnd, uint ideal_reg, bool is_temp) {
2045 ShouldNotReachHere(); // generic vector operands not supported
2046 return nullptr;
2047 }
2048
2049 bool Matcher::is_reg2reg_move(MachNode* m) {
2050 ShouldNotReachHere(); // generic vector operands not supported
2051 return false;
2052 }
2053
2054 bool Matcher::is_generic_vector(MachOper* opnd) {
2055 ShouldNotReachHere(); // generic vector operands not supported
2056 return false;
2057 }
2058
2059 // Return whether or not this register is ever used as an argument.
2060 // This function is used on startup to build the trampoline stubs in
2061 // generateOptoStub. Registers not mentioned will be killed by the VM
2062 // call in the trampoline, and arguments in those registers not be
2063 // available to the callee.
2064 bool Matcher::can_be_java_arg(int reg)
2065 {
2066 return
2067 reg == R10_num || reg == R10_H_num ||
2068 reg == R11_num || reg == R11_H_num ||
2069 reg == R12_num || reg == R12_H_num ||
2070 reg == R13_num || reg == R13_H_num ||
2071 reg == R14_num || reg == R14_H_num ||
2072 reg == R15_num || reg == R15_H_num ||
2073 reg == R16_num || reg == R16_H_num ||
2074 reg == R17_num || reg == R17_H_num ||
2075 reg == F10_num || reg == F10_H_num ||
2076 reg == F11_num || reg == F11_H_num ||
2077 reg == F12_num || reg == F12_H_num ||
2078 reg == F13_num || reg == F13_H_num ||
2079 reg == F14_num || reg == F14_H_num ||
2080 reg == F15_num || reg == F15_H_num ||
2081 reg == F16_num || reg == F16_H_num ||
2082 reg == F17_num || reg == F17_H_num;
2083 }
2084
2085 bool Matcher::is_spillable_arg(int reg)
2086 {
2087 return can_be_java_arg(reg);
2088 }
2089
2090 uint Matcher::int_pressure_limit()
2091 {
2092 // A derived pointer is live at CallNode and then is flagged by RA
2093 // as a spilled LRG. Spilling heuristics(Spill-USE) explicitly skip
2094 // derived pointers and lastly fail to spill after reaching maximum
2095 // number of iterations. Lowering the default pressure threshold to
2096 // (_NO_SPECIAL_REG32_mask.Size() minus 1) forces CallNode to become
2097 // a high register pressure area of the code so that split_DEF can
2098 // generate DefinitionSpillCopy for the derived pointer.
2099 uint default_int_pressure_threshold = _NO_SPECIAL_REG32_mask.Size() - 1;
2100 if (!PreserveFramePointer) {
2101 // When PreserveFramePointer is off, frame pointer is allocatable,
2102 // but different from other SOC registers, it is excluded from
2103 // fatproj's mask because its save type is No-Save. Decrease 1 to
2104 // ensure high pressure at fatproj when PreserveFramePointer is off.
2105 // See check_pressure_at_fatproj().
2106 default_int_pressure_threshold--;
2107 }
2108 return (INTPRESSURE == -1) ? default_int_pressure_threshold : INTPRESSURE;
2109 }
2110
2111 uint Matcher::float_pressure_limit()
2112 {
2113 // _FLOAT_REG_mask is generated by adlc from the float_reg register class.
2114 return (FLOATPRESSURE == -1) ? _FLOAT_REG_mask.Size() : FLOATPRESSURE;
2115 }
2116
2117 bool Matcher::use_asm_for_ldiv_by_con(jlong divisor) {
2118 return false;
2119 }
2120
2121 RegMask Matcher::divI_proj_mask() {
2122 ShouldNotReachHere();
2123 return RegMask();
2124 }
2125
2126 // Register for MODI projection of divmodI.
2127 RegMask Matcher::modI_proj_mask() {
2128 ShouldNotReachHere();
2129 return RegMask();
2130 }
2131
2132 // Register for DIVL projection of divmodL.
2133 RegMask Matcher::divL_proj_mask() {
2134 ShouldNotReachHere();
2135 return RegMask();
2136 }
2137
2138 // Register for MODL projection of divmodL.
2139 RegMask Matcher::modL_proj_mask() {
2140 ShouldNotReachHere();
2141 return RegMask();
2142 }
2143
2144 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
2145 return FP_REG_mask();
2146 }
2147
2148 bool size_fits_all_mem_uses(AddPNode* addp, int shift) {
2149 assert_cond(addp != nullptr);
2150 for (DUIterator_Fast imax, i = addp->fast_outs(imax); i < imax; i++) {
2151 Node* u = addp->fast_out(i);
2152 if (u != nullptr && u->is_Mem()) {
2153 int opsize = u->as_Mem()->memory_size();
2154 assert(opsize > 0, "unexpected memory operand size");
2155 if (u->as_Mem()->memory_size() != (1 << shift)) {
2156 return false;
2157 }
2158 }
2159 }
2160 return true;
2161 }
2162
2163 // Binary src (Replicate scalar/immediate)
2164 static bool is_vector_scalar_bitwise_pattern(Node* n, Node* m) {
2165 if (n == nullptr || m == nullptr) {
2166 return false;
2167 }
2168
2169 if (m->Opcode() != Op_Replicate) {
2170 return false;
2171 }
2172
2173 switch (n->Opcode()) {
2174 case Op_AndV:
2175 case Op_OrV:
2176 case Op_XorV:
2177 case Op_AddVB:
2178 case Op_AddVS:
2179 case Op_AddVI:
2180 case Op_AddVL:
2181 case Op_SubVB:
2182 case Op_SubVS:
2183 case Op_SubVI:
2184 case Op_SubVL:
2185 case Op_MulVB:
2186 case Op_MulVS:
2187 case Op_MulVI:
2188 case Op_MulVL: {
2189 return true;
2190 }
2191 default:
2192 return false;
2193 }
2194 }
2195
2196 // (XorV src (Replicate m1))
2197 // (XorVMask src (MaskAll m1))
2198 static bool is_vector_bitwise_not_pattern(Node* n, Node* m) {
2199 if (n != nullptr && m != nullptr) {
2200 return (n->Opcode() == Op_XorV || n->Opcode() == Op_XorVMask) &&
2201 VectorNode::is_all_ones_vector(m);
2202 }
2203 return false;
2204 }
2205
2206 // Should the Matcher clone input 'm' of node 'n'?
2207 bool Matcher::pd_clone_node(Node* n, Node* m, Matcher::MStack& mstack) {
2208 assert_cond(m != nullptr);
2209 if (is_vshift_con_pattern(n, m) || // ShiftV src (ShiftCntV con)
2210 is_vector_bitwise_not_pattern(n, m) ||
2211 is_vector_scalar_bitwise_pattern(n, m) ||
2212 is_encode_and_store_pattern(n, m)) {
2213 mstack.push(m, Visit);
2214 return true;
2215 }
2216 return false;
2217 }
2218
2219 // Should the Matcher clone shifts on addressing modes, expecting them
2220 // to be subsumed into complex addressing expressions or compute them
2221 // into registers?
2222 bool Matcher::pd_clone_address_expressions(AddPNode* m, Matcher::MStack& mstack, VectorSet& address_visited) {
2223 return clone_base_plus_offset_address(m, mstack, address_visited);
2224 }
2225
2226 %}
2227
2228
2229
2230 //----------ENCODING BLOCK-----------------------------------------------------
2231 // This block specifies the encoding classes used by the compiler to
2232 // output byte streams. Encoding classes are parameterized macros
2233 // used by Machine Instruction Nodes in order to generate the bit
2234 // encoding of the instruction. Operands specify their base encoding
2235 // interface with the interface keyword. There are currently
2236 // supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, &
2237 // COND_INTER. REG_INTER causes an operand to generate a function
2238 // which returns its register number when queried. CONST_INTER causes
2239 // an operand to generate a function which returns the value of the
2240 // constant when queried. MEMORY_INTER causes an operand to generate
2241 // four functions which return the Base Register, the Index Register,
2242 // the Scale Value, and the Offset Value of the operand when queried.
2243 // COND_INTER causes an operand to generate six functions which return
2244 // the encoding code (ie - encoding bits for the instruction)
2245 // associated with each basic boolean condition for a conditional
2246 // instruction.
2247 //
2248 // Instructions specify two basic values for encoding. Again, a
2249 // function is available to check if the constant displacement is an
2250 // oop. They use the ins_encode keyword to specify their encoding
2251 // classes (which must be a sequence of enc_class names, and their
2252 // parameters, specified in the encoding block), and they use the
2253 // opcode keyword to specify, in order, their primary, secondary, and
2254 // tertiary opcode. Only the opcode sections which a particular
2255 // instruction needs for encoding need to be specified.
2256 encode %{
2257 // BEGIN Non-volatile memory access
2258
2259 enc_class riscv_enc_mov_imm(iRegIorL dst, immIorL src) %{
2260 int64_t con = (int64_t)$src$$constant;
2261 Register dst_reg = as_Register($dst$$reg);
2262 __ mv(dst_reg, con);
2263 %}
2264
2265 enc_class riscv_enc_mov_p(iRegP dst, immP src) %{
2266 Register dst_reg = as_Register($dst$$reg);
2267 address con = (address)$src$$constant;
2268 if (con == nullptr || con == (address)1) {
2269 ShouldNotReachHere();
2270 } else {
2271 relocInfo::relocType rtype = $src->constant_reloc();
2272 if (rtype == relocInfo::oop_type) {
2273 __ movoop(dst_reg, (jobject)con);
2274 } else if (rtype == relocInfo::metadata_type) {
2275 __ mov_metadata(dst_reg, (Metadata*)con);
2276 } else {
2277 assert(rtype == relocInfo::none, "unexpected reloc type");
2278 __ mv(dst_reg, $src$$constant);
2279 }
2280 }
2281 %}
2282
2283 enc_class riscv_enc_mov_p1(iRegP dst) %{
2284 Register dst_reg = as_Register($dst$$reg);
2285 __ mv(dst_reg, 1);
2286 %}
2287
2288 enc_class riscv_enc_mov_byte_map_base(iRegP dst) %{
2289 __ load_byte_map_base($dst$$Register);
2290 %}
2291
2292 enc_class riscv_enc_mov_n(iRegN dst, immN src) %{
2293 Register dst_reg = as_Register($dst$$reg);
2294 address con = (address)$src$$constant;
2295 if (con == nullptr) {
2296 ShouldNotReachHere();
2297 } else {
2298 relocInfo::relocType rtype = $src->constant_reloc();
2299 assert(rtype == relocInfo::oop_type, "unexpected reloc type");
2300 __ set_narrow_oop(dst_reg, (jobject)con);
2301 }
2302 %}
2303
2304 enc_class riscv_enc_mov_zero(iRegNorP dst) %{
2305 Register dst_reg = as_Register($dst$$reg);
2306 __ mv(dst_reg, zr);
2307 %}
2308
2309 enc_class riscv_enc_mov_nk(iRegN dst, immNKlass src) %{
2310 Register dst_reg = as_Register($dst$$reg);
2311 address con = (address)$src$$constant;
2312 if (con == nullptr) {
2313 ShouldNotReachHere();
2314 } else {
2315 relocInfo::relocType rtype = $src->constant_reloc();
2316 assert(rtype == relocInfo::metadata_type, "unexpected reloc type");
2317 __ set_narrow_klass(dst_reg, (Klass *)con);
2318 }
2319 %}
2320
2321 enc_class riscv_enc_cmpxchgw(iRegINoSp res, memory mem, iRegI oldval, iRegI newval) %{
2322 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
2323 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
2324 /*result as bool*/ true);
2325 %}
2326
2327 enc_class riscv_enc_cmpxchgn(iRegINoSp res, memory mem, iRegI oldval, iRegI newval) %{
2328 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
2329 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
2330 /*result as bool*/ true);
2331 %}
2332
2333 enc_class riscv_enc_cmpxchg(iRegINoSp res, memory mem, iRegL oldval, iRegL newval) %{
2334 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
2335 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
2336 /*result as bool*/ true);
2337 %}
2338
2339 enc_class riscv_enc_cmpxchgw_acq(iRegINoSp res, memory mem, iRegI oldval, iRegI newval) %{
2340 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
2341 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
2342 /*result as bool*/ true);
2343 %}
2344
2345 enc_class riscv_enc_cmpxchgn_acq(iRegINoSp res, memory mem, iRegI oldval, iRegI newval) %{
2346 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
2347 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
2348 /*result as bool*/ true);
2349 %}
2350
2351 enc_class riscv_enc_cmpxchg_acq(iRegINoSp res, memory mem, iRegL oldval, iRegL newval) %{
2352 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
2353 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
2354 /*result as bool*/ true);
2355 %}
2356
2357 // compare and branch instruction encodings
2358
2359 enc_class riscv_enc_j(label lbl) %{
2360 Label* L = $lbl$$label;
2361 __ j(*L);
2362 %}
2363
2364 enc_class riscv_enc_far_cmpULtGe_imm0_branch(cmpOpULtGe cmp, iRegIorL op1, label lbl) %{
2365 Label* L = $lbl$$label;
2366 switch ($cmp$$cmpcode) {
2367 case(BoolTest::ge):
2368 __ j(*L);
2369 break;
2370 case(BoolTest::lt):
2371 break;
2372 default:
2373 Unimplemented();
2374 }
2375 %}
2376
2377 // call instruction encodings
2378
2379 enc_class riscv_enc_partial_subtype_check(iRegP sub, iRegP super, iRegP temp, iRegP result) %{
2380 Register sub_reg = as_Register($sub$$reg);
2381 Register super_reg = as_Register($super$$reg);
2382 Register temp_reg = as_Register($temp$$reg);
2383 Register result_reg = as_Register($result$$reg);
2384 Register cr_reg = t1;
2385
2386 Label miss;
2387 Label done;
2388 __ check_klass_subtype_slow_path(sub_reg, super_reg, temp_reg, result_reg,
2389 nullptr, &miss, /*set_cond_codes*/ true);
2390 if ($primary) {
2391 __ mv(result_reg, zr);
2392 } else {
2393 __ mv(cr_reg, zr);
2394 __ j(done);
2395 }
2396
2397 __ bind(miss);
2398 if (!$primary) {
2399 __ mv(cr_reg, 1);
2400 }
2401
2402 __ bind(done);
2403 %}
2404
2405 enc_class riscv_enc_java_static_call(method meth) %{
2406 Assembler::IncompressibleRegion ir(masm); // Fixed length: see ret_addr_offset
2407
2408 address addr = (address)$meth$$method;
2409 address call = nullptr;
2410 assert_cond(addr != nullptr);
2411 if (!_method) {
2412 // A call to a runtime wrapper, e.g. new, new_typeArray_Java, uncommon_trap.
2413 call = __ reloc_call(Address(addr, relocInfo::runtime_call_type));
2414 if (call == nullptr) {
2415 ciEnv::current()->record_failure("CodeCache is full");
2416 return;
2417 }
2418 } else if (_method->intrinsic_id() == vmIntrinsicID::_ensureMaterializedForStackWalk) {
2419 // The NOP here is purely to ensure that eliding a call to
2420 // JVM_EnsureMaterializedForStackWalk doesn't change the code size.
2421 __ nop();
2422 __ nop();
2423 __ nop();
2424 __ block_comment("call JVM_EnsureMaterializedForStackWalk (elided)");
2425 } else {
2426 int method_index = resolved_method_index(masm);
2427 RelocationHolder rspec = _optimized_virtual ? opt_virtual_call_Relocation::spec(method_index)
2428 : static_call_Relocation::spec(method_index);
2429 call = __ reloc_call(Address(addr, rspec));
2430 if (call == nullptr) {
2431 ciEnv::current()->record_failure("CodeCache is full");
2432 return;
2433 }
2434
2435 if (CodeBuffer::supports_shared_stubs() && _method->can_be_statically_bound()) {
2436 // Calls of the same statically bound method can share
2437 // a stub to the interpreter.
2438 __ code()->shared_stub_to_interp_for(_method, call - (__ begin()));
2439 } else {
2440 // Emit stub for static call
2441 address stub = CompiledDirectCall::emit_to_interp_stub(masm, call);
2442 if (stub == nullptr) {
2443 ciEnv::current()->record_failure("CodeCache is full");
2444 return;
2445 }
2446 }
2447 }
2448
2449 __ post_call_nop();
2450 %}
2451
2452 enc_class riscv_enc_java_dynamic_call(method meth) %{
2453 Assembler::IncompressibleRegion ir(masm); // Fixed length: see ret_addr_offset
2454 int method_index = resolved_method_index(masm);
2455 address call = __ ic_call((address)$meth$$method, method_index);
2456 if (call == nullptr) {
2457 ciEnv::current()->record_failure("CodeCache is full");
2458 return;
2459 }
2460
2461 __ post_call_nop();
2462 %}
2463
2464 enc_class riscv_enc_call_epilog() %{
2465 if (VerifyStackAtCalls) {
2466 // Check that stack depth is unchanged: find majik cookie on stack
2467 __ call_Unimplemented();
2468 }
2469 %}
2470
2471 enc_class riscv_enc_java_to_runtime(method meth) %{
2472 Assembler::IncompressibleRegion ir(masm); // Fixed length: see ret_addr_offset
2473
2474 // Some calls to generated routines (arraycopy code) are scheduled by C2
2475 // as runtime calls. if so we can call them using a far call (they will be
2476 // in the code cache, thus in a reachable segment) otherwise we have to use
2477 // a movptr+jalr pair which loads the absolute address into a register.
2478 address entry = (address)$meth$$method;
2479 if (CodeCache::contains(entry)) {
2480 __ far_call(Address(entry, relocInfo::runtime_call_type));
2481 __ post_call_nop();
2482 } else {
2483 Label retaddr;
2484 // Make the anchor frame walkable
2485 __ la(t0, retaddr);
2486 __ sd(t0, Address(xthread, JavaThread::last_Java_pc_offset()));
2487 int32_t offset = 0;
2488 // No relocation needed
2489 __ movptr(t1, entry, offset, t0); // lui + lui + slli + add
2490 __ jalr(t1, offset);
2491 __ bind(retaddr);
2492 __ post_call_nop();
2493 }
2494 %}
2495
2496 enc_class riscv_enc_tail_call(iRegP jump_target) %{
2497 Register target_reg = as_Register($jump_target$$reg);
2498 __ jr(target_reg);
2499 %}
2500
2501 enc_class riscv_enc_tail_jmp(iRegP jump_target) %{
2502 Register target_reg = as_Register($jump_target$$reg);
2503 // exception oop should be in x10
2504 // ret addr has been popped into ra
2505 // callee expects it in x13
2506 __ mv(x13, ra);
2507 __ jr(target_reg);
2508 %}
2509
2510 enc_class riscv_enc_rethrow() %{
2511 __ far_jump(RuntimeAddress(OptoRuntime::rethrow_stub()));
2512 %}
2513
2514 enc_class riscv_enc_ret() %{
2515 __ ret();
2516 %}
2517
2518 %}
2519
2520 //----------FRAME--------------------------------------------------------------
2521 // Definition of frame structure and management information.
2522 //
2523 // S T A C K L A Y O U T Allocators stack-slot number
2524 // | (to get allocators register number
2525 // G Owned by | | v add OptoReg::stack0())
2526 // r CALLER | |
2527 // o | +--------+ pad to even-align allocators stack-slot
2528 // w V | pad0 | numbers; owned by CALLER
2529 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
2530 // h ^ | in | 5
2531 // | | args | 4 Holes in incoming args owned by SELF
2532 // | | | | 3
2533 // | | +--------+
2534 // V | | old out| Empty on Intel, window on Sparc
2535 // | old |preserve| Must be even aligned.
2536 // | SP-+--------+----> Matcher::_old_SP, even aligned
2537 // | | in | 3 area for Intel ret address
2538 // Owned by |preserve| Empty on Sparc.
2539 // SELF +--------+
2540 // | | pad2 | 2 pad to align old SP
2541 // | +--------+ 1
2542 // | | locks | 0
2543 // | +--------+----> OptoReg::stack0(), even aligned
2544 // | | pad1 | 11 pad to align new SP
2545 // | +--------+
2546 // | | | 10
2547 // | | spills | 9 spills
2548 // V | | 8 (pad0 slot for callee)
2549 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
2550 // ^ | out | 7
2551 // | | args | 6 Holes in outgoing args owned by CALLEE
2552 // Owned by +--------+
2553 // CALLEE | new out| 6 Empty on Intel, window on Sparc
2554 // | new |preserve| Must be even-aligned.
2555 // | SP-+--------+----> Matcher::_new_SP, even aligned
2556 // | | |
2557 //
2558 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
2559 // known from SELF's arguments and the Java calling convention.
2560 // Region 6-7 is determined per call site.
2561 // Note 2: If the calling convention leaves holes in the incoming argument
2562 // area, those holes are owned by SELF. Holes in the outgoing area
2563 // are owned by the CALLEE. Holes should not be necessary in the
2564 // incoming area, as the Java calling convention is completely under
2565 // the control of the AD file. Doubles can be sorted and packed to
2566 // avoid holes. Holes in the outgoing arguments may be necessary for
2567 // varargs C calling conventions.
2568 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
2569 // even aligned with pad0 as needed.
2570 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
2571 // (the latter is true on Intel but is it false on RISCV?)
2572 // region 6-11 is even aligned; it may be padded out more so that
2573 // the region from SP to FP meets the minimum stack alignment.
2574 // Note 4: For I2C adapters, the incoming FP may not meet the minimum stack
2575 // alignment. Region 11, pad1, may be dynamically extended so that
2576 // SP meets the minimum alignment.
2577
2578 frame %{
2579 // These three registers define part of the calling convention
2580 // between compiled code and the interpreter.
2581
2582 // Inline Cache Register or methodOop for I2C.
2583 inline_cache_reg(R31);
2584
2585 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
2586 cisc_spilling_operand_name(indOffset);
2587
2588 // Number of stack slots consumed by locking an object
2589 // generate Compile::sync_stack_slots
2590 // VMRegImpl::slots_per_word = wordSize / stack_slot_size = 8 / 4 = 2
2591 sync_stack_slots(1 * VMRegImpl::slots_per_word);
2592
2593 // Compiled code's Frame Pointer
2594 frame_pointer(R2);
2595
2596 // Interpreter stores its frame pointer in a register which is
2597 // stored to the stack by I2CAdaptors.
2598 // I2CAdaptors convert from interpreted java to compiled java.
2599 interpreter_frame_pointer(R8);
2600
2601 // Stack alignment requirement
2602 stack_alignment(StackAlignmentInBytes); // Alignment size in bytes (128-bit -> 16 bytes)
2603
2604 // Number of outgoing stack slots killed above the out_preserve_stack_slots
2605 // for calls to C. Supports the var-args backing area for register parms.
2606 varargs_C_out_slots_killed(frame::arg_reg_save_area_bytes / BytesPerInt);
2607
2608 // The after-PROLOG location of the return address. Location of
2609 // return address specifies a type (REG or STACK) and a number
2610 // representing the register number (i.e. - use a register name) or
2611 // stack slot.
2612 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
2613 // Otherwise, it is above the locks and verification slot and alignment word
2614 // TODO this may well be correct but need to check why that - 2 is there
2615 // ppc port uses 0 but we definitely need to allow for fixed_slots
2616 // which folds in the space used for monitors
2617 return_addr(STACK - 2 +
2618 align_up((Compile::current()->in_preserve_stack_slots() +
2619 Compile::current()->fixed_slots()),
2620 stack_alignment_in_slots()));
2621
2622 // Location of compiled Java return values. Same as C for now.
2623 return_value
2624 %{
2625 assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL,
2626 "only return normal values");
2627
2628 static const int lo[Op_RegL + 1] = { // enum name
2629 0, // Op_Node
2630 0, // Op_Set
2631 R10_num, // Op_RegN
2632 R10_num, // Op_RegI
2633 R10_num, // Op_RegP
2634 F10_num, // Op_RegF
2635 F10_num, // Op_RegD
2636 R10_num // Op_RegL
2637 };
2638
2639 static const int hi[Op_RegL + 1] = { // enum name
2640 0, // Op_Node
2641 0, // Op_Set
2642 OptoReg::Bad, // Op_RegN
2643 OptoReg::Bad, // Op_RegI
2644 R10_H_num, // Op_RegP
2645 OptoReg::Bad, // Op_RegF
2646 F10_H_num, // Op_RegD
2647 R10_H_num // Op_RegL
2648 };
2649
2650 return OptoRegPair(hi[ideal_reg], lo[ideal_reg]);
2651 %}
2652 %}
2653
2654 //----------ATTRIBUTES---------------------------------------------------------
2655 //----------Operand Attributes-------------------------------------------------
2656 op_attrib op_cost(1); // Required cost attribute
2657
2658 //----------Instruction Attributes---------------------------------------------
2659 ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute
2660 ins_attrib ins_size(32); // Required size attribute (in bits)
2661 ins_attrib ins_short_branch(0); // Required flag: is this instruction
2662 // a non-matching short branch variant
2663 // of some long branch?
2664 ins_attrib ins_alignment(4); // Required alignment attribute (must
2665 // be a power of 2) specifies the
2666 // alignment that some part of the
2667 // instruction (not necessarily the
2668 // start) requires. If > 1, a
2669 // compute_padding() function must be
2670 // provided for the instruction
2671
2672 //----------OPERANDS-----------------------------------------------------------
2673 // Operand definitions must precede instruction definitions for correct parsing
2674 // in the ADLC because operands constitute user defined types which are used in
2675 // instruction definitions.
2676
2677 //----------Simple Operands----------------------------------------------------
2678
2679 // Integer operands 32 bit
2680 // 32 bit immediate
2681 operand immI()
2682 %{
2683 match(ConI);
2684
2685 op_cost(0);
2686 format %{ %}
2687 interface(CONST_INTER);
2688 %}
2689
2690 // 32 bit zero
2691 operand immI0()
2692 %{
2693 predicate(n->get_int() == 0);
2694 match(ConI);
2695
2696 op_cost(0);
2697 format %{ %}
2698 interface(CONST_INTER);
2699 %}
2700
2701 // 32 bit unit increment
2702 operand immI_1()
2703 %{
2704 predicate(n->get_int() == 1);
2705 match(ConI);
2706
2707 op_cost(0);
2708 format %{ %}
2709 interface(CONST_INTER);
2710 %}
2711
2712 // 32 bit unit decrement
2713 operand immI_M1()
2714 %{
2715 predicate(n->get_int() == -1);
2716 match(ConI);
2717
2718 op_cost(0);
2719 format %{ %}
2720 interface(CONST_INTER);
2721 %}
2722
2723 // Unsigned Integer Immediate: 6-bit int, greater than 32
2724 operand uimmI6_ge32() %{
2725 predicate(((unsigned int)(n->get_int()) < 64) && (n->get_int() >= 32));
2726 match(ConI);
2727 op_cost(0);
2728 format %{ %}
2729 interface(CONST_INTER);
2730 %}
2731
2732 operand immI_le_4()
2733 %{
2734 predicate(n->get_int() <= 4);
2735 match(ConI);
2736
2737 op_cost(0);
2738 format %{ %}
2739 interface(CONST_INTER);
2740 %}
2741
2742 operand immI_16()
2743 %{
2744 predicate(n->get_int() == 16);
2745 match(ConI);
2746 op_cost(0);
2747 format %{ %}
2748 interface(CONST_INTER);
2749 %}
2750
2751 operand immI_24()
2752 %{
2753 predicate(n->get_int() == 24);
2754 match(ConI);
2755 op_cost(0);
2756 format %{ %}
2757 interface(CONST_INTER);
2758 %}
2759
2760 operand immI_31()
2761 %{
2762 predicate(n->get_int() == 31);
2763 match(ConI);
2764
2765 op_cost(0);
2766 format %{ %}
2767 interface(CONST_INTER);
2768 %}
2769
2770 operand immI_63()
2771 %{
2772 predicate(n->get_int() == 63);
2773 match(ConI);
2774
2775 op_cost(0);
2776 format %{ %}
2777 interface(CONST_INTER);
2778 %}
2779
2780 // 32 bit integer valid for add immediate
2781 operand immIAdd()
2782 %{
2783 predicate(Assembler::is_simm12((int64_t)n->get_int()));
2784 match(ConI);
2785 op_cost(0);
2786 format %{ %}
2787 interface(CONST_INTER);
2788 %}
2789
2790 // 32 bit integer valid for sub immediate
2791 operand immISub()
2792 %{
2793 predicate(Assembler::is_simm12(-(int64_t)n->get_int()));
2794 match(ConI);
2795 op_cost(0);
2796 format %{ %}
2797 interface(CONST_INTER);
2798 %}
2799
2800 // 5 bit signed value.
2801 operand immI5()
2802 %{
2803 predicate(n->get_int() <= 15 && n->get_int() >= -16);
2804 match(ConI);
2805
2806 op_cost(0);
2807 format %{ %}
2808 interface(CONST_INTER);
2809 %}
2810
2811 // 5 bit signed value (simm5)
2812 operand immL5()
2813 %{
2814 predicate(n->get_long() <= 15 && n->get_long() >= -16);
2815 match(ConL);
2816
2817 op_cost(0);
2818 format %{ %}
2819 interface(CONST_INTER);
2820 %}
2821
2822 // Integer operands 64 bit
2823 // 64 bit immediate
2824 operand immL()
2825 %{
2826 match(ConL);
2827
2828 op_cost(0);
2829 format %{ %}
2830 interface(CONST_INTER);
2831 %}
2832
2833 // 64 bit zero
2834 operand immL0()
2835 %{
2836 predicate(n->get_long() == 0);
2837 match(ConL);
2838
2839 op_cost(0);
2840 format %{ %}
2841 interface(CONST_INTER);
2842 %}
2843
2844 // Pointer operands
2845 // Pointer Immediate
2846 operand immP()
2847 %{
2848 match(ConP);
2849
2850 op_cost(0);
2851 format %{ %}
2852 interface(CONST_INTER);
2853 %}
2854
2855 // Null Pointer Immediate
2856 operand immP0()
2857 %{
2858 predicate(n->get_ptr() == 0);
2859 match(ConP);
2860
2861 op_cost(0);
2862 format %{ %}
2863 interface(CONST_INTER);
2864 %}
2865
2866 // Pointer Immediate One
2867 // this is used in object initialization (initial object header)
2868 operand immP_1()
2869 %{
2870 predicate(n->get_ptr() == 1);
2871 match(ConP);
2872
2873 op_cost(0);
2874 format %{ %}
2875 interface(CONST_INTER);
2876 %}
2877
2878 // Card Table Byte Map Base
2879 operand immByteMapBase()
2880 %{
2881 // Get base of card map
2882 predicate(BarrierSet::barrier_set()->is_a(BarrierSet::CardTableBarrierSet) &&
2883 SHENANDOAHGC_ONLY(!BarrierSet::barrier_set()->is_a(BarrierSet::ShenandoahBarrierSet) &&)
2884 (CardTable::CardValue*)n->get_ptr() ==
2885 ((CardTableBarrierSet*)(BarrierSet::barrier_set()))->card_table()->byte_map_base());
2886 match(ConP);
2887
2888 op_cost(0);
2889 format %{ %}
2890 interface(CONST_INTER);
2891 %}
2892
2893 // Int Immediate: low 16-bit mask
2894 operand immI_16bits()
2895 %{
2896 predicate(n->get_int() == 0xFFFF);
2897 match(ConI);
2898 op_cost(0);
2899 format %{ %}
2900 interface(CONST_INTER);
2901 %}
2902
2903 operand immIpowerOf2() %{
2904 predicate(is_power_of_2((juint)(n->get_int())));
2905 match(ConI);
2906 op_cost(0);
2907 format %{ %}
2908 interface(CONST_INTER);
2909 %}
2910
2911 // Long Immediate: low 32-bit mask
2912 operand immL_32bits()
2913 %{
2914 predicate(n->get_long() == 0xFFFFFFFFL);
2915 match(ConL);
2916 op_cost(0);
2917 format %{ %}
2918 interface(CONST_INTER);
2919 %}
2920
2921 // 64 bit unit decrement
2922 operand immL_M1()
2923 %{
2924 predicate(n->get_long() == -1);
2925 match(ConL);
2926
2927 op_cost(0);
2928 format %{ %}
2929 interface(CONST_INTER);
2930 %}
2931
2932
2933 // 64 bit integer valid for add immediate
2934 operand immLAdd()
2935 %{
2936 predicate(Assembler::is_simm12(n->get_long()));
2937 match(ConL);
2938 op_cost(0);
2939 format %{ %}
2940 interface(CONST_INTER);
2941 %}
2942
2943 // 64 bit integer valid for sub immediate
2944 operand immLSub()
2945 %{
2946 predicate(Assembler::is_simm12(-(n->get_long())));
2947 match(ConL);
2948 op_cost(0);
2949 format %{ %}
2950 interface(CONST_INTER);
2951 %}
2952
2953 // Narrow pointer operands
2954 // Narrow Pointer Immediate
2955 operand immN()
2956 %{
2957 match(ConN);
2958
2959 op_cost(0);
2960 format %{ %}
2961 interface(CONST_INTER);
2962 %}
2963
2964 // Narrow Null Pointer Immediate
2965 operand immN0()
2966 %{
2967 predicate(n->get_narrowcon() == 0);
2968 match(ConN);
2969
2970 op_cost(0);
2971 format %{ %}
2972 interface(CONST_INTER);
2973 %}
2974
2975 operand immNKlass()
2976 %{
2977 match(ConNKlass);
2978
2979 op_cost(0);
2980 format %{ %}
2981 interface(CONST_INTER);
2982 %}
2983
2984 // Float and Double operands
2985 // Double Immediate
2986 operand immD()
2987 %{
2988 match(ConD);
2989 op_cost(0);
2990 format %{ %}
2991 interface(CONST_INTER);
2992 %}
2993
2994 // Double Immediate: +0.0d
2995 operand immD0()
2996 %{
2997 predicate(jlong_cast(n->getd()) == 0);
2998 match(ConD);
2999
3000 op_cost(0);
3001 format %{ %}
3002 interface(CONST_INTER);
3003 %}
3004
3005 // Float Immediate
3006 operand immF()
3007 %{
3008 match(ConF);
3009 op_cost(0);
3010 format %{ %}
3011 interface(CONST_INTER);
3012 %}
3013
3014 // Float Immediate: +0.0f.
3015 operand immF0()
3016 %{
3017 predicate(jint_cast(n->getf()) == 0);
3018 match(ConF);
3019
3020 op_cost(0);
3021 format %{ %}
3022 interface(CONST_INTER);
3023 %}
3024
3025 // Half Float Immediate
3026 operand immH()
3027 %{
3028 match(ConH);
3029
3030 op_cost(0);
3031 format %{ %}
3032 interface(CONST_INTER);
3033 %}
3034
3035 // Half Float Immediate: +0.0f.
3036 operand immH0()
3037 %{
3038 predicate(jint_cast(n->geth()) == 0);
3039 match(ConH);
3040
3041 op_cost(0);
3042 format %{ %}
3043 interface(CONST_INTER);
3044 %}
3045
3046 operand immIOffset()
3047 %{
3048 predicate(Assembler::is_simm12(n->get_int()));
3049 match(ConI);
3050 op_cost(0);
3051 format %{ %}
3052 interface(CONST_INTER);
3053 %}
3054
3055 operand immLOffset()
3056 %{
3057 predicate(Assembler::is_simm12(n->get_long()));
3058 match(ConL);
3059 op_cost(0);
3060 format %{ %}
3061 interface(CONST_INTER);
3062 %}
3063
3064 // Scale values
3065 operand immIScale()
3066 %{
3067 predicate(1 <= n->get_int() && (n->get_int() <= 3));
3068 match(ConI);
3069
3070 op_cost(0);
3071 format %{ %}
3072 interface(CONST_INTER);
3073 %}
3074
3075 // Integer 32 bit Register Operands
3076 operand iRegI()
3077 %{
3078 constraint(ALLOC_IN_RC(any_reg32));
3079 match(RegI);
3080 match(iRegINoSp);
3081 op_cost(0);
3082 format %{ %}
3083 interface(REG_INTER);
3084 %}
3085
3086 // Integer 32 bit Register not Special
3087 operand iRegINoSp()
3088 %{
3089 constraint(ALLOC_IN_RC(no_special_reg32));
3090 match(RegI);
3091 op_cost(0);
3092 format %{ %}
3093 interface(REG_INTER);
3094 %}
3095
3096 // Register R10 only
3097 operand iRegI_R10()
3098 %{
3099 constraint(ALLOC_IN_RC(int_r10_reg));
3100 match(RegI);
3101 match(iRegINoSp);
3102 op_cost(0);
3103 format %{ %}
3104 interface(REG_INTER);
3105 %}
3106
3107 // Register R12 only
3108 operand iRegI_R12()
3109 %{
3110 constraint(ALLOC_IN_RC(int_r12_reg));
3111 match(RegI);
3112 match(iRegINoSp);
3113 op_cost(0);
3114 format %{ %}
3115 interface(REG_INTER);
3116 %}
3117
3118 // Register R13 only
3119 operand iRegI_R13()
3120 %{
3121 constraint(ALLOC_IN_RC(int_r13_reg));
3122 match(RegI);
3123 match(iRegINoSp);
3124 op_cost(0);
3125 format %{ %}
3126 interface(REG_INTER);
3127 %}
3128
3129 // Register R14 only
3130 operand iRegI_R14()
3131 %{
3132 constraint(ALLOC_IN_RC(int_r14_reg));
3133 match(RegI);
3134 match(iRegINoSp);
3135 op_cost(0);
3136 format %{ %}
3137 interface(REG_INTER);
3138 %}
3139
3140 // Integer 64 bit Register Operands
3141 operand iRegL()
3142 %{
3143 constraint(ALLOC_IN_RC(any_reg));
3144 match(RegL);
3145 match(iRegLNoSp);
3146 op_cost(0);
3147 format %{ %}
3148 interface(REG_INTER);
3149 %}
3150
3151 // Integer 64 bit Register not Special
3152 operand iRegLNoSp()
3153 %{
3154 constraint(ALLOC_IN_RC(no_special_reg));
3155 match(RegL);
3156 match(iRegL_R10);
3157 format %{ %}
3158 interface(REG_INTER);
3159 %}
3160
3161 // Long 64 bit Register R29 only
3162 operand iRegL_R29()
3163 %{
3164 constraint(ALLOC_IN_RC(r29_reg));
3165 match(RegL);
3166 match(iRegLNoSp);
3167 op_cost(0);
3168 format %{ %}
3169 interface(REG_INTER);
3170 %}
3171
3172 // Long 64 bit Register R30 only
3173 operand iRegL_R30()
3174 %{
3175 constraint(ALLOC_IN_RC(r30_reg));
3176 match(RegL);
3177 match(iRegLNoSp);
3178 op_cost(0);
3179 format %{ %}
3180 interface(REG_INTER);
3181 %}
3182
3183 // Pointer Register Operands
3184 // Pointer Register
3185 operand iRegP()
3186 %{
3187 constraint(ALLOC_IN_RC(ptr_reg));
3188 match(RegP);
3189 match(iRegPNoSp);
3190 match(iRegP_R10);
3191 match(iRegP_R15);
3192 match(javaThread_RegP);
3193 op_cost(0);
3194 format %{ %}
3195 interface(REG_INTER);
3196 %}
3197
3198 // Pointer 64 bit Register not Special
3199 operand iRegPNoSp()
3200 %{
3201 constraint(ALLOC_IN_RC(no_special_ptr_reg));
3202 match(RegP);
3203 op_cost(0);
3204 format %{ %}
3205 interface(REG_INTER);
3206 %}
3207
3208 // This operand is not allowed to use fp even if
3209 // fp is not used to hold the frame pointer.
3210 operand iRegPNoSpNoFp()
3211 %{
3212 constraint(ALLOC_IN_RC(no_special_no_fp_ptr_reg));
3213 match(RegP);
3214 match(iRegPNoSp);
3215 op_cost(0);
3216 format %{ %}
3217 interface(REG_INTER);
3218 %}
3219
3220 operand iRegP_R10()
3221 %{
3222 constraint(ALLOC_IN_RC(r10_reg));
3223 match(RegP);
3224 // match(iRegP);
3225 match(iRegPNoSp);
3226 op_cost(0);
3227 format %{ %}
3228 interface(REG_INTER);
3229 %}
3230
3231 // Pointer 64 bit Register R11 only
3232 operand iRegP_R11()
3233 %{
3234 constraint(ALLOC_IN_RC(r11_reg));
3235 match(RegP);
3236 match(iRegPNoSp);
3237 op_cost(0);
3238 format %{ %}
3239 interface(REG_INTER);
3240 %}
3241
3242 operand iRegP_R12()
3243 %{
3244 constraint(ALLOC_IN_RC(r12_reg));
3245 match(RegP);
3246 // match(iRegP);
3247 match(iRegPNoSp);
3248 op_cost(0);
3249 format %{ %}
3250 interface(REG_INTER);
3251 %}
3252
3253 // Pointer 64 bit Register R13 only
3254 operand iRegP_R13()
3255 %{
3256 constraint(ALLOC_IN_RC(r13_reg));
3257 match(RegP);
3258 match(iRegPNoSp);
3259 op_cost(0);
3260 format %{ %}
3261 interface(REG_INTER);
3262 %}
3263
3264 operand iRegP_R14()
3265 %{
3266 constraint(ALLOC_IN_RC(r14_reg));
3267 match(RegP);
3268 // match(iRegP);
3269 match(iRegPNoSp);
3270 op_cost(0);
3271 format %{ %}
3272 interface(REG_INTER);
3273 %}
3274
3275 operand iRegP_R15()
3276 %{
3277 constraint(ALLOC_IN_RC(r15_reg));
3278 match(RegP);
3279 // match(iRegP);
3280 match(iRegPNoSp);
3281 op_cost(0);
3282 format %{ %}
3283 interface(REG_INTER);
3284 %}
3285
3286 operand iRegP_R16()
3287 %{
3288 constraint(ALLOC_IN_RC(r16_reg));
3289 match(RegP);
3290 match(iRegPNoSp);
3291 op_cost(0);
3292 format %{ %}
3293 interface(REG_INTER);
3294 %}
3295
3296 // Pointer 64 bit Register R28 only
3297 operand iRegP_R28()
3298 %{
3299 constraint(ALLOC_IN_RC(r28_reg));
3300 match(RegP);
3301 match(iRegPNoSp);
3302 op_cost(0);
3303 format %{ %}
3304 interface(REG_INTER);
3305 %}
3306
3307 // Pointer 64 bit Register R30 only
3308 operand iRegP_R30()
3309 %{
3310 constraint(ALLOC_IN_RC(r30_reg));
3311 match(RegP);
3312 match(iRegPNoSp);
3313 op_cost(0);
3314 format %{ %}
3315 interface(REG_INTER);
3316 %}
3317
3318 // Pointer 64 bit Register R31 only
3319 operand iRegP_R31()
3320 %{
3321 constraint(ALLOC_IN_RC(r31_reg));
3322 match(RegP);
3323 match(iRegPNoSp);
3324 op_cost(0);
3325 format %{ %}
3326 interface(REG_INTER);
3327 %}
3328
3329 // Pointer Register Operands
3330 // Narrow Pointer Register
3331 operand iRegN()
3332 %{
3333 constraint(ALLOC_IN_RC(any_reg32));
3334 match(RegN);
3335 match(iRegNNoSp);
3336 op_cost(0);
3337 format %{ %}
3338 interface(REG_INTER);
3339 %}
3340
3341 // Integer 64 bit Register not Special
3342 operand iRegNNoSp()
3343 %{
3344 constraint(ALLOC_IN_RC(no_special_reg32));
3345 match(RegN);
3346 op_cost(0);
3347 format %{ %}
3348 interface(REG_INTER);
3349 %}
3350
3351 // Long 64 bit Register R10 only
3352 operand iRegL_R10()
3353 %{
3354 constraint(ALLOC_IN_RC(r10_reg));
3355 match(RegL);
3356 match(iRegLNoSp);
3357 op_cost(0);
3358 format %{ %}
3359 interface(REG_INTER);
3360 %}
3361
3362 // Float Register
3363 // Float register operands
3364 operand fRegF()
3365 %{
3366 constraint(ALLOC_IN_RC(float_reg));
3367 match(RegF);
3368
3369 op_cost(0);
3370 format %{ %}
3371 interface(REG_INTER);
3372 %}
3373
3374 // Double Register
3375 // Double register operands
3376 operand fRegD()
3377 %{
3378 constraint(ALLOC_IN_RC(double_reg));
3379 match(RegD);
3380
3381 op_cost(0);
3382 format %{ %}
3383 interface(REG_INTER);
3384 %}
3385
3386 // Generic vector class. This will be used for
3387 // all vector operands.
3388 operand vReg()
3389 %{
3390 constraint(ALLOC_IN_RC(vectora_reg));
3391 match(VecA);
3392 op_cost(0);
3393 format %{ %}
3394 interface(REG_INTER);
3395 %}
3396
3397 operand vReg_V1()
3398 %{
3399 constraint(ALLOC_IN_RC(v1_reg));
3400 match(VecA);
3401 match(vReg);
3402 op_cost(0);
3403 format %{ %}
3404 interface(REG_INTER);
3405 %}
3406
3407 operand vReg_V2()
3408 %{
3409 constraint(ALLOC_IN_RC(v2_reg));
3410 match(VecA);
3411 match(vReg);
3412 op_cost(0);
3413 format %{ %}
3414 interface(REG_INTER);
3415 %}
3416
3417 operand vReg_V3()
3418 %{
3419 constraint(ALLOC_IN_RC(v3_reg));
3420 match(VecA);
3421 match(vReg);
3422 op_cost(0);
3423 format %{ %}
3424 interface(REG_INTER);
3425 %}
3426
3427 operand vReg_V4()
3428 %{
3429 constraint(ALLOC_IN_RC(v4_reg));
3430 match(VecA);
3431 match(vReg);
3432 op_cost(0);
3433 format %{ %}
3434 interface(REG_INTER);
3435 %}
3436
3437 operand vReg_V5()
3438 %{
3439 constraint(ALLOC_IN_RC(v5_reg));
3440 match(VecA);
3441 match(vReg);
3442 op_cost(0);
3443 format %{ %}
3444 interface(REG_INTER);
3445 %}
3446
3447 operand vReg_V6()
3448 %{
3449 constraint(ALLOC_IN_RC(v6_reg));
3450 match(VecA);
3451 match(vReg);
3452 op_cost(0);
3453 format %{ %}
3454 interface(REG_INTER);
3455 %}
3456
3457 operand vReg_V7()
3458 %{
3459 constraint(ALLOC_IN_RC(v7_reg));
3460 match(VecA);
3461 match(vReg);
3462 op_cost(0);
3463 format %{ %}
3464 interface(REG_INTER);
3465 %}
3466
3467 operand vReg_V8()
3468 %{
3469 constraint(ALLOC_IN_RC(v8_reg));
3470 match(VecA);
3471 match(vReg);
3472 op_cost(0);
3473 format %{ %}
3474 interface(REG_INTER);
3475 %}
3476
3477 operand vReg_V9()
3478 %{
3479 constraint(ALLOC_IN_RC(v9_reg));
3480 match(VecA);
3481 match(vReg);
3482 op_cost(0);
3483 format %{ %}
3484 interface(REG_INTER);
3485 %}
3486
3487 operand vReg_V10()
3488 %{
3489 constraint(ALLOC_IN_RC(v10_reg));
3490 match(VecA);
3491 match(vReg);
3492 op_cost(0);
3493 format %{ %}
3494 interface(REG_INTER);
3495 %}
3496
3497 operand vReg_V11()
3498 %{
3499 constraint(ALLOC_IN_RC(v11_reg));
3500 match(VecA);
3501 match(vReg);
3502 op_cost(0);
3503 format %{ %}
3504 interface(REG_INTER);
3505 %}
3506
3507 operand vRegMask()
3508 %{
3509 constraint(ALLOC_IN_RC(vmask_reg));
3510 match(RegVectMask);
3511 match(vRegMask_V0);
3512 op_cost(0);
3513 format %{ %}
3514 interface(REG_INTER);
3515 %}
3516
3517 // The mask value used to control execution of a masked
3518 // vector instruction is always supplied by vector register v0.
3519 operand vRegMask_V0()
3520 %{
3521 constraint(ALLOC_IN_RC(vmask_reg_v0));
3522 match(RegVectMask);
3523 match(vRegMask);
3524 op_cost(0);
3525 format %{ %}
3526 interface(REG_INTER);
3527 %}
3528
3529 // Java Thread Register
3530 operand javaThread_RegP(iRegP reg)
3531 %{
3532 constraint(ALLOC_IN_RC(java_thread_reg)); // java_thread_reg
3533 match(reg);
3534 op_cost(0);
3535 format %{ %}
3536 interface(REG_INTER);
3537 %}
3538
3539 //----------Memory Operands----------------------------------------------------
3540 // RISCV has only base_plus_offset and literal address mode, so no need to use
3541 // index and scale. Here set index as 0xffffffff and scale as 0x0.
3542 operand indirect(iRegP reg)
3543 %{
3544 constraint(ALLOC_IN_RC(ptr_reg));
3545 match(reg);
3546 op_cost(0);
3547 format %{ "[$reg]" %}
3548 interface(MEMORY_INTER) %{
3549 base($reg);
3550 index(0xffffffff);
3551 scale(0x0);
3552 disp(0x0);
3553 %}
3554 %}
3555
3556 operand indOffI(iRegP reg, immIOffset off)
3557 %{
3558 constraint(ALLOC_IN_RC(ptr_reg));
3559 match(AddP reg off);
3560 op_cost(0);
3561 format %{ "[$reg, $off]" %}
3562 interface(MEMORY_INTER) %{
3563 base($reg);
3564 index(0xffffffff);
3565 scale(0x0);
3566 disp($off);
3567 %}
3568 %}
3569
3570 operand indOffL(iRegP reg, immLOffset off)
3571 %{
3572 constraint(ALLOC_IN_RC(ptr_reg));
3573 match(AddP reg off);
3574 op_cost(0);
3575 format %{ "[$reg, $off]" %}
3576 interface(MEMORY_INTER) %{
3577 base($reg);
3578 index(0xffffffff);
3579 scale(0x0);
3580 disp($off);
3581 %}
3582 %}
3583
3584 operand indirectN(iRegN reg)
3585 %{
3586 predicate(CompressedOops::shift() == 0);
3587 constraint(ALLOC_IN_RC(ptr_reg));
3588 match(DecodeN reg);
3589 op_cost(0);
3590 format %{ "[$reg]\t# narrow" %}
3591 interface(MEMORY_INTER) %{
3592 base($reg);
3593 index(0xffffffff);
3594 scale(0x0);
3595 disp(0x0);
3596 %}
3597 %}
3598
3599 operand indOffIN(iRegN reg, immIOffset off)
3600 %{
3601 predicate(CompressedOops::shift() == 0);
3602 constraint(ALLOC_IN_RC(ptr_reg));
3603 match(AddP (DecodeN reg) off);
3604 op_cost(0);
3605 format %{ "[$reg, $off]\t# narrow" %}
3606 interface(MEMORY_INTER) %{
3607 base($reg);
3608 index(0xffffffff);
3609 scale(0x0);
3610 disp($off);
3611 %}
3612 %}
3613
3614 operand indOffLN(iRegN reg, immLOffset off)
3615 %{
3616 predicate(CompressedOops::shift() == 0);
3617 constraint(ALLOC_IN_RC(ptr_reg));
3618 match(AddP (DecodeN reg) off);
3619 op_cost(0);
3620 format %{ "[$reg, $off]\t# narrow" %}
3621 interface(MEMORY_INTER) %{
3622 base($reg);
3623 index(0xffffffff);
3624 scale(0x0);
3625 disp($off);
3626 %}
3627 %}
3628
3629 //----------Special Memory Operands--------------------------------------------
3630 // Stack Slot Operand - This operand is used for loading and storing temporary
3631 // values on the stack where a match requires a value to
3632 // flow through memory.
3633 operand stackSlotI(sRegI reg)
3634 %{
3635 constraint(ALLOC_IN_RC(stack_slots));
3636 // No match rule because this operand is only generated in matching
3637 // match(RegI);
3638 format %{ "[$reg]" %}
3639 interface(MEMORY_INTER) %{
3640 base(0x02); // RSP
3641 index(0xffffffff); // No Index
3642 scale(0x0); // No Scale
3643 disp($reg); // Stack Offset
3644 %}
3645 %}
3646
3647 operand stackSlotF(sRegF reg)
3648 %{
3649 constraint(ALLOC_IN_RC(stack_slots));
3650 // No match rule because this operand is only generated in matching
3651 // match(RegF);
3652 format %{ "[$reg]" %}
3653 interface(MEMORY_INTER) %{
3654 base(0x02); // RSP
3655 index(0xffffffff); // No Index
3656 scale(0x0); // No Scale
3657 disp($reg); // Stack Offset
3658 %}
3659 %}
3660
3661 operand stackSlotD(sRegD reg)
3662 %{
3663 constraint(ALLOC_IN_RC(stack_slots));
3664 // No match rule because this operand is only generated in matching
3665 // match(RegD);
3666 format %{ "[$reg]" %}
3667 interface(MEMORY_INTER) %{
3668 base(0x02); // RSP
3669 index(0xffffffff); // No Index
3670 scale(0x0); // No Scale
3671 disp($reg); // Stack Offset
3672 %}
3673 %}
3674
3675 operand stackSlotL(sRegL reg)
3676 %{
3677 constraint(ALLOC_IN_RC(stack_slots));
3678 // No match rule because this operand is only generated in matching
3679 // match(RegL);
3680 format %{ "[$reg]" %}
3681 interface(MEMORY_INTER) %{
3682 base(0x02); // RSP
3683 index(0xffffffff); // No Index
3684 scale(0x0); // No Scale
3685 disp($reg); // Stack Offset
3686 %}
3687 %}
3688
3689 // Special operand allowing long args to int ops to be truncated for free
3690
3691 operand iRegL2I(iRegL reg) %{
3692
3693 op_cost(0);
3694
3695 match(ConvL2I reg);
3696
3697 format %{ "l2i($reg)" %}
3698
3699 interface(REG_INTER)
3700 %}
3701
3702
3703 // Comparison Operands
3704 // NOTE: Label is a predefined operand which should not be redefined in
3705 // the AD file. It is generically handled within the ADLC.
3706
3707 //----------Conditional Branch Operands----------------------------------------
3708 // Comparison Op - This is the operation of the comparison, and is limited to
3709 // the following set of codes:
3710 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
3711 //
3712 // Other attributes of the comparison, such as unsignedness, are specified
3713 // by the comparison instruction that sets a condition code flags register.
3714 // That result is represented by a flags operand whose subtype is appropriate
3715 // to the unsignedness (etc.) of the comparison.
3716 //
3717 // Later, the instruction which matches both the Comparison Op (a Bool) and
3718 // the flags (produced by the Cmp) specifies the coding of the comparison op
3719 // by matching a specific subtype of Bool operand below, such as cmpOpU.
3720
3721
3722 // used for signed integral comparisons and fp comparisons
3723 operand cmpOp()
3724 %{
3725 match(Bool);
3726
3727 format %{ "" %}
3728
3729 // the values in interface derives from struct BoolTest::mask
3730 interface(COND_INTER) %{
3731 equal(0x0, "eq");
3732 greater(0x1, "gt");
3733 overflow(0x2, "overflow");
3734 less(0x3, "lt");
3735 not_equal(0x4, "ne");
3736 less_equal(0x5, "le");
3737 no_overflow(0x6, "no_overflow");
3738 greater_equal(0x7, "ge");
3739 %}
3740 %}
3741
3742 // used for unsigned integral comparisons
3743 operand cmpOpU()
3744 %{
3745 match(Bool);
3746
3747 format %{ "" %}
3748 // the values in interface derives from struct BoolTest::mask
3749 interface(COND_INTER) %{
3750 equal(0x0, "eq");
3751 greater(0x1, "gtu");
3752 overflow(0x2, "overflow");
3753 less(0x3, "ltu");
3754 not_equal(0x4, "ne");
3755 less_equal(0x5, "leu");
3756 no_overflow(0x6, "no_overflow");
3757 greater_equal(0x7, "geu");
3758 %}
3759 %}
3760
3761 // used for certain integral comparisons which can be
3762 // converted to bxx instructions
3763 operand cmpOpEqNe()
3764 %{
3765 match(Bool);
3766 op_cost(0);
3767 predicate(n->as_Bool()->_test._test == BoolTest::ne ||
3768 n->as_Bool()->_test._test == BoolTest::eq);
3769
3770 format %{ "" %}
3771 interface(COND_INTER) %{
3772 equal(0x0, "eq");
3773 greater(0x1, "gt");
3774 overflow(0x2, "overflow");
3775 less(0x3, "lt");
3776 not_equal(0x4, "ne");
3777 less_equal(0x5, "le");
3778 no_overflow(0x6, "no_overflow");
3779 greater_equal(0x7, "ge");
3780 %}
3781 %}
3782
3783 operand cmpOpULtGe()
3784 %{
3785 match(Bool);
3786 op_cost(0);
3787 predicate(n->as_Bool()->_test._test == BoolTest::lt ||
3788 n->as_Bool()->_test._test == BoolTest::ge);
3789
3790 format %{ "" %}
3791 interface(COND_INTER) %{
3792 equal(0x0, "eq");
3793 greater(0x1, "gtu");
3794 overflow(0x2, "overflow");
3795 less(0x3, "ltu");
3796 not_equal(0x4, "ne");
3797 less_equal(0x5, "leu");
3798 no_overflow(0x6, "no_overflow");
3799 greater_equal(0x7, "geu");
3800 %}
3801 %}
3802
3803 operand cmpOpUEqNeLeGt()
3804 %{
3805 match(Bool);
3806 op_cost(0);
3807 predicate(n->as_Bool()->_test._test == BoolTest::ne ||
3808 n->as_Bool()->_test._test == BoolTest::eq ||
3809 n->as_Bool()->_test._test == BoolTest::le ||
3810 n->as_Bool()->_test._test == BoolTest::gt);
3811
3812 format %{ "" %}
3813 interface(COND_INTER) %{
3814 equal(0x0, "eq");
3815 greater(0x1, "gtu");
3816 overflow(0x2, "overflow");
3817 less(0x3, "ltu");
3818 not_equal(0x4, "ne");
3819 less_equal(0x5, "leu");
3820 no_overflow(0x6, "no_overflow");
3821 greater_equal(0x7, "geu");
3822 %}
3823 %}
3824
3825
3826 // Flags register, used as output of compare logic
3827 operand rFlagsReg()
3828 %{
3829 constraint(ALLOC_IN_RC(reg_flags));
3830 match(RegFlags);
3831
3832 op_cost(0);
3833 format %{ "RFLAGS" %}
3834 interface(REG_INTER);
3835 %}
3836
3837 // Special Registers
3838
3839 // Method Register
3840 operand inline_cache_RegP(iRegP reg)
3841 %{
3842 constraint(ALLOC_IN_RC(method_reg)); // inline_cache_reg
3843 match(reg);
3844 match(iRegPNoSp);
3845 op_cost(0);
3846 format %{ %}
3847 interface(REG_INTER);
3848 %}
3849
3850 //----------OPERAND CLASSES----------------------------------------------------
3851 // Operand Classes are groups of operands that are used as to simplify
3852 // instruction definitions by not requiring the AD writer to specify
3853 // separate instructions for every form of operand when the
3854 // instruction accepts multiple operand types with the same basic
3855 // encoding and format. The classic case of this is memory operands.
3856
3857 // memory is used to define read/write location for load/store
3858 // instruction defs. we can turn a memory op into an Address
3859
3860 opclass memory(indirect, indOffI, indOffL, indirectN, indOffIN, indOffLN);
3861
3862 // iRegIorL2I is used for src inputs in rules for 32 bit int (I)
3863 // operations. it allows the src to be either an iRegI or a (ConvL2I
3864 // iRegL). in the latter case the l2i normally planted for a ConvL2I
3865 // can be elided because the 32-bit instruction will just employ the
3866 // lower 32 bits anyway.
3867 //
3868 // n.b. this does not elide all L2I conversions. if the truncated
3869 // value is consumed by more than one operation then the ConvL2I
3870 // cannot be bundled into the consuming nodes so an l2i gets planted
3871 // (actually an addiw $dst, $src, 0) and the downstream instructions
3872 // consume the result of the L2I as an iRegI input. That's a shame since
3873 // the addiw is actually redundant but its not too costly.
3874
3875 opclass iRegIorL2I(iRegI, iRegL2I);
3876 opclass iRegIorL(iRegI, iRegL);
3877 opclass iRegNorP(iRegN, iRegP);
3878 opclass iRegILNP(iRegI, iRegL, iRegN, iRegP);
3879 opclass iRegILNPNoSp(iRegINoSp, iRegLNoSp, iRegNNoSp, iRegPNoSp);
3880 opclass immIorL(immI, immL);
3881
3882 //----------PIPELINE-----------------------------------------------------------
3883 // Rules which define the behavior of the target architectures pipeline.
3884
3885 // For specific pipelines, e.g. generic RISC-V, define the stages of that pipeline
3886 //pipe_desc(ID, EX, MEM, WR);
3887 #define ID S0
3888 #define EX S1
3889 #define MEM S2
3890 #define WR S3
3891
3892 // Integer ALU reg operation
3893 pipeline %{
3894
3895 attributes %{
3896 // RISC-V instructions are of fixed length
3897 fixed_size_instructions; // Fixed size instructions TODO does
3898 max_instructions_per_bundle = 2; // Generic RISC-V 1, Sifive Series 7 2
3899 // RISC-V instructions come in 32-bit word units
3900 instruction_unit_size = 4; // An instruction is 4 bytes long
3901 instruction_fetch_unit_size = 64; // The processor fetches one line
3902 instruction_fetch_units = 1; // of 64 bytes
3903
3904 // List of nop instructions
3905 nops( MachNop );
3906 %}
3907
3908 // We don't use an actual pipeline model so don't care about resources
3909 // or description. we do use pipeline classes to introduce fixed
3910 // latencies
3911
3912 //----------RESOURCES----------------------------------------------------------
3913 // Resources are the functional units available to the machine
3914
3915 // Generic RISC-V pipeline
3916 // 1 decoder
3917 // 1 instruction decoded per cycle
3918 // 1 load/store ops per cycle, 1 branch, 1 FPU
3919 // 1 mul, 1 div
3920
3921 resources ( DECODE,
3922 ALU,
3923 MUL,
3924 DIV,
3925 BRANCH,
3926 LDST,
3927 FPU);
3928
3929 //----------PIPELINE DESCRIPTION-----------------------------------------------
3930 // Pipeline Description specifies the stages in the machine's pipeline
3931
3932 // Define the pipeline as a generic 6 stage pipeline
3933 pipe_desc(S0, S1, S2, S3, S4, S5);
3934
3935 //----------PIPELINE CLASSES---------------------------------------------------
3936 // Pipeline Classes describe the stages in which input and output are
3937 // referenced by the hardware pipeline.
3938
3939 pipe_class fp_dop_reg_reg_s(fRegF dst, fRegF src1, fRegF src2)
3940 %{
3941 single_instruction;
3942 src1 : S1(read);
3943 src2 : S2(read);
3944 dst : S5(write);
3945 DECODE : ID;
3946 FPU : S5;
3947 %}
3948
3949 pipe_class fp_dop_reg_reg_d(fRegD dst, fRegD src1, fRegD src2)
3950 %{
3951 src1 : S1(read);
3952 src2 : S2(read);
3953 dst : S5(write);
3954 DECODE : ID;
3955 FPU : S5;
3956 %}
3957
3958 pipe_class fp_uop_s(fRegF dst, fRegF src)
3959 %{
3960 single_instruction;
3961 src : S1(read);
3962 dst : S5(write);
3963 DECODE : ID;
3964 FPU : S5;
3965 %}
3966
3967 pipe_class fp_uop_d(fRegD dst, fRegD src)
3968 %{
3969 single_instruction;
3970 src : S1(read);
3971 dst : S5(write);
3972 DECODE : ID;
3973 FPU : S5;
3974 %}
3975
3976 pipe_class fp_d2f(fRegF dst, fRegD src)
3977 %{
3978 single_instruction;
3979 src : S1(read);
3980 dst : S5(write);
3981 DECODE : ID;
3982 FPU : S5;
3983 %}
3984
3985 pipe_class fp_f2d(fRegD dst, fRegF src)
3986 %{
3987 single_instruction;
3988 src : S1(read);
3989 dst : S5(write);
3990 DECODE : ID;
3991 FPU : S5;
3992 %}
3993
3994 pipe_class fp_f2i(iRegINoSp dst, fRegF src)
3995 %{
3996 single_instruction;
3997 src : S1(read);
3998 dst : S5(write);
3999 DECODE : ID;
4000 FPU : S5;
4001 %}
4002
4003 pipe_class fp_f2l(iRegLNoSp dst, fRegF src)
4004 %{
4005 single_instruction;
4006 src : S1(read);
4007 dst : S5(write);
4008 DECODE : ID;
4009 FPU : S5;
4010 %}
4011
4012 pipe_class fp_i2f(fRegF dst, iRegIorL2I src)
4013 %{
4014 single_instruction;
4015 src : S1(read);
4016 dst : S5(write);
4017 DECODE : ID;
4018 FPU : S5;
4019 %}
4020
4021 pipe_class fp_l2f(fRegF dst, iRegL src)
4022 %{
4023 single_instruction;
4024 src : S1(read);
4025 dst : S5(write);
4026 DECODE : ID;
4027 FPU : S5;
4028 %}
4029
4030 pipe_class fp_d2i(iRegINoSp dst, fRegD src)
4031 %{
4032 single_instruction;
4033 src : S1(read);
4034 dst : S5(write);
4035 DECODE : ID;
4036 FPU : S5;
4037 %}
4038
4039 pipe_class fp_d2l(iRegLNoSp dst, fRegD src)
4040 %{
4041 single_instruction;
4042 src : S1(read);
4043 dst : S5(write);
4044 DECODE : ID;
4045 FPU : S5;
4046 %}
4047
4048 pipe_class fp_i2d(fRegD dst, iRegIorL2I src)
4049 %{
4050 single_instruction;
4051 src : S1(read);
4052 dst : S5(write);
4053 DECODE : ID;
4054 FPU : S5;
4055 %}
4056
4057 pipe_class fp_l2d(fRegD dst, iRegIorL2I src)
4058 %{
4059 single_instruction;
4060 src : S1(read);
4061 dst : S5(write);
4062 DECODE : ID;
4063 FPU : S5;
4064 %}
4065
4066 pipe_class fp_div_s(fRegF dst, fRegF src1, fRegF src2)
4067 %{
4068 single_instruction;
4069 src1 : S1(read);
4070 src2 : S2(read);
4071 dst : S5(write);
4072 DECODE : ID;
4073 FPU : S5;
4074 %}
4075
4076 pipe_class fp_div_d(fRegD dst, fRegD src1, fRegD src2)
4077 %{
4078 single_instruction;
4079 src1 : S1(read);
4080 src2 : S2(read);
4081 dst : S5(write);
4082 DECODE : ID;
4083 FPU : S5;
4084 %}
4085
4086 pipe_class fp_sqrt_s(fRegF dst, fRegF src)
4087 %{
4088 single_instruction;
4089 src : S1(read);
4090 dst : S5(write);
4091 DECODE : ID;
4092 FPU : S5;
4093 %}
4094
4095 pipe_class fp_sqrt_d(fRegD dst, fRegD src)
4096 %{
4097 single_instruction;
4098 src : S1(read);
4099 dst : S5(write);
4100 DECODE : ID;
4101 FPU : S5;
4102 %}
4103
4104 pipe_class fp_load_constant_s(fRegF dst)
4105 %{
4106 single_instruction;
4107 dst : S5(write);
4108 DECODE : ID;
4109 FPU : S5;
4110 %}
4111
4112 pipe_class fp_load_constant_d(fRegD dst)
4113 %{
4114 single_instruction;
4115 dst : S5(write);
4116 DECODE : ID;
4117 FPU : S5;
4118 %}
4119
4120 pipe_class fp_load_mem_s(fRegF dst, memory mem)
4121 %{
4122 single_instruction;
4123 mem : S1(read);
4124 dst : S5(write);
4125 DECODE : ID;
4126 LDST : MEM;
4127 %}
4128
4129 pipe_class fp_load_mem_d(fRegD dst, memory mem)
4130 %{
4131 single_instruction;
4132 mem : S1(read);
4133 dst : S5(write);
4134 DECODE : ID;
4135 LDST : MEM;
4136 %}
4137
4138 pipe_class fp_store_reg_s(fRegF src, memory mem)
4139 %{
4140 single_instruction;
4141 src : S1(read);
4142 mem : S5(write);
4143 DECODE : ID;
4144 LDST : MEM;
4145 %}
4146
4147 pipe_class fp_store_reg_d(fRegD src, memory mem)
4148 %{
4149 single_instruction;
4150 src : S1(read);
4151 mem : S5(write);
4152 DECODE : ID;
4153 LDST : MEM;
4154 %}
4155
4156 //------- Integer ALU operations --------------------------
4157
4158 // Integer ALU reg-reg operation
4159 // Operands needs in ID, result generated in EX
4160 // E.g. ADD Rd, Rs1, Rs2
4161 pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2)
4162 %{
4163 single_instruction;
4164 dst : EX(write);
4165 src1 : ID(read);
4166 src2 : ID(read);
4167 DECODE : ID;
4168 ALU : EX;
4169 %}
4170
4171 // Integer ALU reg operation with constant shift
4172 // E.g. SLLI Rd, Rs1, #shift
4173 pipe_class ialu_reg_shift(iRegI dst, iRegI src1)
4174 %{
4175 single_instruction;
4176 dst : EX(write);
4177 src1 : ID(read);
4178 DECODE : ID;
4179 ALU : EX;
4180 %}
4181
4182 // Integer ALU reg-reg operation with variable shift
4183 // both operands must be available in ID
4184 // E.g. SLL Rd, Rs1, Rs2
4185 pipe_class ialu_reg_reg_vshift(iRegI dst, iRegI src1, iRegI src2)
4186 %{
4187 single_instruction;
4188 dst : EX(write);
4189 src1 : ID(read);
4190 src2 : ID(read);
4191 DECODE : ID;
4192 ALU : EX;
4193 %}
4194
4195 // Integer ALU reg operation
4196 // E.g. NEG Rd, Rs2
4197 pipe_class ialu_reg(iRegI dst, iRegI src)
4198 %{
4199 single_instruction;
4200 dst : EX(write);
4201 src : ID(read);
4202 DECODE : ID;
4203 ALU : EX;
4204 %}
4205
4206 // Integer ALU reg immediate operation
4207 // E.g. ADDI Rd, Rs1, #imm
4208 pipe_class ialu_reg_imm(iRegI dst, iRegI src1)
4209 %{
4210 single_instruction;
4211 dst : EX(write);
4212 src1 : ID(read);
4213 DECODE : ID;
4214 ALU : EX;
4215 %}
4216
4217 // Integer ALU immediate operation (no source operands)
4218 // E.g. LI Rd, #imm
4219 pipe_class ialu_imm(iRegI dst)
4220 %{
4221 single_instruction;
4222 dst : EX(write);
4223 DECODE : ID;
4224 ALU : EX;
4225 %}
4226
4227 //------- Multiply pipeline operations --------------------
4228
4229 // Multiply reg-reg
4230 // E.g. MULW Rd, Rs1, Rs2
4231 pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2)
4232 %{
4233 single_instruction;
4234 dst : WR(write);
4235 src1 : ID(read);
4236 src2 : ID(read);
4237 DECODE : ID;
4238 MUL : WR;
4239 %}
4240
4241 // E.g. MUL RD, Rs1, Rs2
4242 pipe_class lmul_reg_reg(iRegL dst, iRegL src1, iRegL src2)
4243 %{
4244 single_instruction;
4245 fixed_latency(3); // Maximum latency for 64 bit mul
4246 dst : WR(write);
4247 src1 : ID(read);
4248 src2 : ID(read);
4249 DECODE : ID;
4250 MUL : WR;
4251 %}
4252
4253 //------- Divide pipeline operations --------------------
4254
4255 // E.g. DIVW Rd, Rs1, Rs2
4256 pipe_class idiv_reg_reg(iRegI dst, iRegI src1, iRegI src2)
4257 %{
4258 single_instruction;
4259 fixed_latency(8); // Maximum latency for 32 bit divide
4260 dst : WR(write);
4261 src1 : ID(read);
4262 src2 : ID(read);
4263 DECODE : ID;
4264 DIV : WR;
4265 %}
4266
4267 // E.g. DIV RD, Rs1, Rs2
4268 pipe_class ldiv_reg_reg(iRegL dst, iRegL src1, iRegL src2)
4269 %{
4270 single_instruction;
4271 fixed_latency(16); // Maximum latency for 64 bit divide
4272 dst : WR(write);
4273 src1 : ID(read);
4274 src2 : ID(read);
4275 DECODE : ID;
4276 DIV : WR;
4277 %}
4278
4279 //------- Load pipeline operations ------------------------
4280
4281 // Load - prefetch
4282 // Eg. PREFETCH_W mem
4283 pipe_class iload_prefetch(memory mem)
4284 %{
4285 single_instruction;
4286 mem : ID(read);
4287 DECODE : ID;
4288 LDST : MEM;
4289 %}
4290
4291 // Load - reg, mem
4292 // E.g. LA Rd, mem
4293 pipe_class iload_reg_mem(iRegI dst, memory mem)
4294 %{
4295 single_instruction;
4296 dst : WR(write);
4297 mem : ID(read);
4298 DECODE : ID;
4299 LDST : MEM;
4300 %}
4301
4302 // Load - reg, reg
4303 // E.g. LD Rd, Rs
4304 pipe_class iload_reg_reg(iRegI dst, iRegI src)
4305 %{
4306 single_instruction;
4307 dst : WR(write);
4308 src : ID(read);
4309 DECODE : ID;
4310 LDST : MEM;
4311 %}
4312
4313 //------- Store pipeline operations -----------------------
4314
4315 // Store - zr, mem
4316 // E.g. SD zr, mem
4317 pipe_class istore_mem(memory mem)
4318 %{
4319 single_instruction;
4320 mem : ID(read);
4321 DECODE : ID;
4322 LDST : MEM;
4323 %}
4324
4325 // Store - reg, mem
4326 // E.g. SD Rs, mem
4327 pipe_class istore_reg_mem(iRegI src, memory mem)
4328 %{
4329 single_instruction;
4330 mem : ID(read);
4331 src : EX(read);
4332 DECODE : ID;
4333 LDST : MEM;
4334 %}
4335
4336 // Store - reg, reg
4337 // E.g. SD Rs2, Rs1
4338 pipe_class istore_reg_reg(iRegI dst, iRegI src)
4339 %{
4340 single_instruction;
4341 dst : ID(read);
4342 src : EX(read);
4343 DECODE : ID;
4344 LDST : MEM;
4345 %}
4346
4347 //------- Control transfer pipeline operations ------------
4348
4349 // Branch
4350 pipe_class pipe_branch()
4351 %{
4352 single_instruction;
4353 DECODE : ID;
4354 BRANCH : EX;
4355 %}
4356
4357 // Branch
4358 pipe_class pipe_branch_reg(iRegI src)
4359 %{
4360 single_instruction;
4361 src : ID(read);
4362 DECODE : ID;
4363 BRANCH : EX;
4364 %}
4365
4366 // Compare & Branch
4367 // E.g. BEQ Rs1, Rs2, L
4368 pipe_class pipe_cmp_branch(iRegI src1, iRegI src2)
4369 %{
4370 single_instruction;
4371 src1 : ID(read);
4372 src2 : ID(read);
4373 DECODE : ID;
4374 BRANCH : EX;
4375 %}
4376
4377 // E.g. BEQZ Rs, L
4378 pipe_class pipe_cmpz_branch(iRegI src)
4379 %{
4380 single_instruction;
4381 src : ID(read);
4382 DECODE : ID;
4383 BRANCH : EX;
4384 %}
4385
4386 //------- Synchronisation operations ----------------------
4387 // Any operation requiring serialization
4388 // E.g. FENCE/Atomic Ops/Load Acquire/Store Release
4389 pipe_class pipe_serial()
4390 %{
4391 single_instruction;
4392 force_serialization;
4393 fixed_latency(16);
4394 DECODE : ID;
4395 LDST : MEM;
4396 %}
4397
4398 pipe_class pipe_slow()
4399 %{
4400 instruction_count(10);
4401 multiple_bundles;
4402 force_serialization;
4403 fixed_latency(16);
4404 DECODE : ID;
4405 LDST : MEM;
4406 %}
4407
4408 // The real do-nothing guy
4409 pipe_class real_empty()
4410 %{
4411 instruction_count(0);
4412 %}
4413
4414 // Empty pipeline class
4415 pipe_class pipe_class_empty()
4416 %{
4417 single_instruction;
4418 fixed_latency(0);
4419 %}
4420
4421 // Default pipeline class.
4422 pipe_class pipe_class_default()
4423 %{
4424 single_instruction;
4425 fixed_latency(2);
4426 %}
4427
4428 // Pipeline class for compares.
4429 pipe_class pipe_class_compare()
4430 %{
4431 single_instruction;
4432 fixed_latency(16);
4433 %}
4434
4435 // Pipeline class for memory operations.
4436 pipe_class pipe_class_memory()
4437 %{
4438 single_instruction;
4439 fixed_latency(16);
4440 %}
4441
4442 // Pipeline class for call.
4443 pipe_class pipe_class_call()
4444 %{
4445 single_instruction;
4446 fixed_latency(100);
4447 %}
4448
4449 // Define the class for the Nop node.
4450 define %{
4451 MachNop = pipe_class_empty;
4452 %}
4453 %}
4454 //----------INSTRUCTIONS-------------------------------------------------------
4455 //
4456 // match -- States which machine-independent subtree may be replaced
4457 // by this instruction.
4458 // ins_cost -- The estimated cost of this instruction is used by instruction
4459 // selection to identify a minimum cost tree of machine
4460 // instructions that matches a tree of machine-independent
4461 // instructions.
4462 // format -- A string providing the disassembly for this instruction.
4463 // The value of an instruction's operand may be inserted
4464 // by referring to it with a '$' prefix.
4465 // opcode -- Three instruction opcodes may be provided. These are referred
4466 // to within an encode class as $primary, $secondary, and $tertiary
4467 // rrspectively. The primary opcode is commonly used to
4468 // indicate the type of machine instruction, while secondary
4469 // and tertiary are often used for prefix options or addressing
4470 // modes.
4471 // ins_encode -- A list of encode classes with parameters. The encode class
4472 // name must have been defined in an 'enc_class' specification
4473 // in the encode section of the architecture description.
4474
4475 // ============================================================================
4476 // Memory (Load/Store) Instructions
4477
4478 // Load Instructions
4479
4480 // Load Byte (8 bit signed)
4481 instruct loadB(iRegINoSp dst, memory mem)
4482 %{
4483 match(Set dst (LoadB mem));
4484
4485 ins_cost(LOAD_COST);
4486 format %{ "lb $dst, $mem\t# byte, #@loadB" %}
4487
4488 ins_encode %{
4489 __ lb(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4490 %}
4491
4492 ins_pipe(iload_reg_mem);
4493 %}
4494
4495 // Load Byte (8 bit signed) into long
4496 instruct loadB2L(iRegLNoSp dst, memory mem)
4497 %{
4498 match(Set dst (ConvI2L (LoadB mem)));
4499
4500 ins_cost(LOAD_COST);
4501 format %{ "lb $dst, $mem\t# byte, #@loadB2L" %}
4502
4503 ins_encode %{
4504 __ lb(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4505 %}
4506
4507 ins_pipe(iload_reg_mem);
4508 %}
4509
4510 // Load Byte (8 bit unsigned)
4511 instruct loadUB(iRegINoSp dst, memory mem)
4512 %{
4513 match(Set dst (LoadUB mem));
4514
4515 ins_cost(LOAD_COST);
4516 format %{ "lbu $dst, $mem\t# byte, #@loadUB" %}
4517
4518 ins_encode %{
4519 __ lbu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4520 %}
4521
4522 ins_pipe(iload_reg_mem);
4523 %}
4524
4525 // Load Byte (8 bit unsigned) into long
4526 instruct loadUB2L(iRegLNoSp dst, memory mem)
4527 %{
4528 match(Set dst (ConvI2L (LoadUB mem)));
4529
4530 ins_cost(LOAD_COST);
4531 format %{ "lbu $dst, $mem\t# byte, #@loadUB2L" %}
4532
4533 ins_encode %{
4534 __ lbu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4535 %}
4536
4537 ins_pipe(iload_reg_mem);
4538 %}
4539
4540 // Load Short (16 bit signed)
4541 instruct loadS(iRegINoSp dst, memory mem)
4542 %{
4543 match(Set dst (LoadS mem));
4544
4545 ins_cost(LOAD_COST);
4546 format %{ "lh $dst, $mem\t# short, #@loadS" %}
4547
4548 ins_encode %{
4549 __ lh(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4550 %}
4551
4552 ins_pipe(iload_reg_mem);
4553 %}
4554
4555 // Load Short (16 bit signed) into long
4556 instruct loadS2L(iRegLNoSp dst, memory mem)
4557 %{
4558 match(Set dst (ConvI2L (LoadS mem)));
4559
4560 ins_cost(LOAD_COST);
4561 format %{ "lh $dst, $mem\t# short, #@loadS2L" %}
4562
4563 ins_encode %{
4564 __ lh(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4565 %}
4566
4567 ins_pipe(iload_reg_mem);
4568 %}
4569
4570 // Load Char (16 bit unsigned)
4571 instruct loadUS(iRegINoSp dst, memory mem)
4572 %{
4573 match(Set dst (LoadUS mem));
4574
4575 ins_cost(LOAD_COST);
4576 format %{ "lhu $dst, $mem\t# short, #@loadUS" %}
4577
4578 ins_encode %{
4579 __ lhu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4580 %}
4581
4582 ins_pipe(iload_reg_mem);
4583 %}
4584
4585 // Load Short/Char (16 bit unsigned) into long
4586 instruct loadUS2L(iRegLNoSp dst, memory mem)
4587 %{
4588 match(Set dst (ConvI2L (LoadUS mem)));
4589
4590 ins_cost(LOAD_COST);
4591 format %{ "lhu $dst, $mem\t# short, #@loadUS2L" %}
4592
4593 ins_encode %{
4594 __ lhu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4595 %}
4596
4597 ins_pipe(iload_reg_mem);
4598 %}
4599
4600 // Load Integer (32 bit signed)
4601 instruct loadI(iRegINoSp dst, memory mem)
4602 %{
4603 match(Set dst (LoadI mem));
4604
4605 ins_cost(LOAD_COST);
4606 format %{ "lw $dst, $mem\t# int, #@loadI" %}
4607
4608 ins_encode %{
4609 __ lw(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4610 %}
4611
4612 ins_pipe(iload_reg_mem);
4613 %}
4614
4615 // Load Integer (32 bit signed) into long
4616 instruct loadI2L(iRegLNoSp dst, memory mem)
4617 %{
4618 match(Set dst (ConvI2L (LoadI mem)));
4619
4620 ins_cost(LOAD_COST);
4621 format %{ "lw $dst, $mem\t# int, #@loadI2L" %}
4622
4623 ins_encode %{
4624 __ lw(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4625 %}
4626
4627 ins_pipe(iload_reg_mem);
4628 %}
4629
4630 // Load Integer (32 bit unsigned) into long
4631 instruct loadUI2L(iRegLNoSp dst, memory mem, immL_32bits mask)
4632 %{
4633 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
4634
4635 ins_cost(LOAD_COST);
4636 format %{ "lwu $dst, $mem\t# int, #@loadUI2L" %}
4637
4638 ins_encode %{
4639 __ lwu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4640 %}
4641
4642 ins_pipe(iload_reg_mem);
4643 %}
4644
4645 // Load Long (64 bit signed)
4646 instruct loadL(iRegLNoSp dst, memory mem)
4647 %{
4648 match(Set dst (LoadL mem));
4649
4650 ins_cost(LOAD_COST);
4651 format %{ "ld $dst, $mem\t# int, #@loadL" %}
4652
4653 ins_encode %{
4654 __ ld(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4655 %}
4656
4657 ins_pipe(iload_reg_mem);
4658 %}
4659
4660 // Load Range
4661 instruct loadRange(iRegINoSp dst, memory mem)
4662 %{
4663 match(Set dst (LoadRange mem));
4664
4665 ins_cost(LOAD_COST);
4666 format %{ "lwu $dst, $mem\t# range, #@loadRange" %}
4667
4668 ins_encode %{
4669 __ lwu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4670 %}
4671
4672 ins_pipe(iload_reg_mem);
4673 %}
4674
4675 // Load Pointer
4676 instruct loadP(iRegPNoSp dst, memory mem)
4677 %{
4678 match(Set dst (LoadP mem));
4679 predicate(n->as_Load()->barrier_data() == 0);
4680
4681 ins_cost(LOAD_COST);
4682 format %{ "ld $dst, $mem\t# ptr, #@loadP" %}
4683
4684 ins_encode %{
4685 __ ld(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4686 %}
4687
4688 ins_pipe(iload_reg_mem);
4689 %}
4690
4691 // Load Compressed Pointer
4692 instruct loadN(iRegNNoSp dst, memory mem)
4693 %{
4694 predicate(n->as_Load()->barrier_data() == 0);
4695 match(Set dst (LoadN mem));
4696
4697 ins_cost(LOAD_COST);
4698 format %{ "lwu $dst, $mem\t# compressed ptr, #@loadN" %}
4699
4700 ins_encode %{
4701 __ lwu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4702 %}
4703
4704 ins_pipe(iload_reg_mem);
4705 %}
4706
4707 // Load Klass Pointer
4708 instruct loadKlass(iRegPNoSp dst, memory mem)
4709 %{
4710 match(Set dst (LoadKlass mem));
4711
4712 ins_cost(LOAD_COST);
4713 format %{ "ld $dst, $mem\t# class, #@loadKlass" %}
4714
4715 ins_encode %{
4716 __ ld(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4717 %}
4718
4719 ins_pipe(iload_reg_mem);
4720 %}
4721
4722 // Load Narrow Klass Pointer
4723 instruct loadNKlass(iRegNNoSp dst, memory mem)
4724 %{
4725 predicate(!UseCompactObjectHeaders);
4726 match(Set dst (LoadNKlass mem));
4727
4728 ins_cost(LOAD_COST);
4729 format %{ "lwu $dst, $mem\t# compressed class ptr, #@loadNKlass" %}
4730
4731 ins_encode %{
4732 __ lwu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4733 %}
4734
4735 ins_pipe(iload_reg_mem);
4736 %}
4737
4738 instruct loadNKlassCompactHeaders(iRegNNoSp dst, memory mem)
4739 %{
4740 predicate(UseCompactObjectHeaders);
4741 match(Set dst (LoadNKlass mem));
4742
4743 ins_cost(LOAD_COST);
4744 format %{
4745 "lwu $dst, $mem\t# compressed klass ptr, shifted\n\t"
4746 "srli $dst, $dst, markWord::klass_shift_at_offset"
4747 %}
4748
4749 ins_encode %{
4750 Unimplemented();
4751 // __ lwu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4752 // __ srli(as_Register($dst$$reg), as_Register($dst$$reg), (unsigned) markWord::klass_shift_at_offset);
4753 %}
4754
4755 ins_pipe(iload_reg_mem);
4756 %}
4757
4758 // Load Float
4759 instruct loadF(fRegF dst, memory mem)
4760 %{
4761 match(Set dst (LoadF mem));
4762
4763 ins_cost(LOAD_COST);
4764 format %{ "flw $dst, $mem\t# float, #@loadF" %}
4765
4766 ins_encode %{
4767 __ flw(as_FloatRegister($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4768 %}
4769
4770 ins_pipe(fp_load_mem_s);
4771 %}
4772
4773 // Load Double
4774 instruct loadD(fRegD dst, memory mem)
4775 %{
4776 match(Set dst (LoadD mem));
4777
4778 ins_cost(LOAD_COST);
4779 format %{ "fld $dst, $mem\t# double, #@loadD" %}
4780
4781 ins_encode %{
4782 __ fld(as_FloatRegister($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4783 %}
4784
4785 ins_pipe(fp_load_mem_d);
4786 %}
4787
4788 // Load Int Constant
4789 instruct loadConI(iRegINoSp dst, immI src)
4790 %{
4791 match(Set dst src);
4792
4793 ins_cost(ALU_COST);
4794 format %{ "mv $dst, $src\t# int, #@loadConI" %}
4795
4796 ins_encode(riscv_enc_mov_imm(dst, src));
4797
4798 ins_pipe(ialu_imm);
4799 %}
4800
4801 // Load Long Constant
4802 instruct loadConL(iRegLNoSp dst, immL src)
4803 %{
4804 match(Set dst src);
4805
4806 ins_cost(ALU_COST);
4807 format %{ "mv $dst, $src\t# long, #@loadConL" %}
4808
4809 ins_encode(riscv_enc_mov_imm(dst, src));
4810
4811 ins_pipe(ialu_imm);
4812 %}
4813
4814 // Load Pointer Constant
4815 instruct loadConP(iRegPNoSp dst, immP con)
4816 %{
4817 match(Set dst con);
4818
4819 ins_cost(ALU_COST);
4820 format %{ "mv $dst, $con\t# ptr, #@loadConP" %}
4821
4822 ins_encode(riscv_enc_mov_p(dst, con));
4823
4824 ins_pipe(ialu_imm);
4825 %}
4826
4827 // Load Null Pointer Constant
4828 instruct loadConP0(iRegPNoSp dst, immP0 con)
4829 %{
4830 match(Set dst con);
4831
4832 ins_cost(ALU_COST);
4833 format %{ "mv $dst, $con\t# null pointer, #@loadConP0" %}
4834
4835 ins_encode(riscv_enc_mov_zero(dst));
4836
4837 ins_pipe(ialu_imm);
4838 %}
4839
4840 // Load Pointer Constant One
4841 instruct loadConP1(iRegPNoSp dst, immP_1 con)
4842 %{
4843 match(Set dst con);
4844
4845 ins_cost(ALU_COST);
4846 format %{ "mv $dst, $con\t# load ptr constant one, #@loadConP1" %}
4847
4848 ins_encode(riscv_enc_mov_p1(dst));
4849
4850 ins_pipe(ialu_imm);
4851 %}
4852
4853 // Load Byte Map Base Constant
4854 instruct loadByteMapBase(iRegPNoSp dst, immByteMapBase con)
4855 %{
4856 match(Set dst con);
4857 ins_cost(ALU_COST);
4858 format %{ "mv $dst, $con\t# Byte Map Base, #@loadByteMapBase" %}
4859
4860 ins_encode(riscv_enc_mov_byte_map_base(dst));
4861
4862 ins_pipe(ialu_imm);
4863 %}
4864
4865 // Load Narrow Pointer Constant
4866 instruct loadConN(iRegNNoSp dst, immN con)
4867 %{
4868 match(Set dst con);
4869
4870 ins_cost(ALU_COST * 4);
4871 format %{ "mv $dst, $con\t# compressed ptr, #@loadConN" %}
4872
4873 ins_encode(riscv_enc_mov_n(dst, con));
4874
4875 ins_pipe(ialu_imm);
4876 %}
4877
4878 // Load Narrow Null Pointer Constant
4879 instruct loadConN0(iRegNNoSp dst, immN0 con)
4880 %{
4881 match(Set dst con);
4882
4883 ins_cost(ALU_COST);
4884 format %{ "mv $dst, $con\t# compressed null pointer, #@loadConN0" %}
4885
4886 ins_encode(riscv_enc_mov_zero(dst));
4887
4888 ins_pipe(ialu_imm);
4889 %}
4890
4891 // Load Narrow Klass Constant
4892 instruct loadConNKlass(iRegNNoSp dst, immNKlass con)
4893 %{
4894 match(Set dst con);
4895
4896 ins_cost(ALU_COST * 6);
4897 format %{ "mv $dst, $con\t# compressed klass ptr, #@loadConNKlass" %}
4898
4899 ins_encode(riscv_enc_mov_nk(dst, con));
4900
4901 ins_pipe(ialu_imm);
4902 %}
4903
4904 // Load Half Float Constant
4905 instruct loadConH(fRegF dst, immH con) %{
4906 match(Set dst con);
4907
4908 ins_cost(LOAD_COST);
4909 format %{
4910 "flh $dst, [$constantaddress]\t# load from constant table: float=$con, #@loadConH"
4911 %}
4912
4913 ins_encode %{
4914 assert(UseZfh || UseZfhmin, "must");
4915 if (MacroAssembler::can_hf_imm_load($con$$constant)) {
4916 __ fli_h(as_FloatRegister($dst$$reg), $con$$constant);
4917 } else {
4918 __ flh(as_FloatRegister($dst$$reg), $constantaddress($con));
4919 }
4920 %}
4921
4922 ins_pipe(fp_load_constant_s);
4923 %}
4924
4925 instruct loadConH0(fRegF dst, immH0 con) %{
4926 match(Set dst con);
4927
4928 ins_cost(XFER_COST);
4929
4930 format %{ "fmv.h.x $dst, zr\t# float, #@loadConH0" %}
4931
4932 ins_encode %{
4933 assert(UseZfh || UseZfhmin, "must");
4934 __ fmv_h_x(as_FloatRegister($dst$$reg), zr);
4935 %}
4936
4937 ins_pipe(fp_load_constant_s);
4938 %}
4939
4940 // Load Float Constant
4941 instruct loadConF(fRegF dst, immF con) %{
4942 match(Set dst con);
4943
4944 ins_cost(LOAD_COST);
4945 format %{
4946 "flw $dst, [$constantaddress]\t# load from constant table: float=$con, #@loadConF"
4947 %}
4948
4949 ins_encode %{
4950 if (MacroAssembler::can_fp_imm_load($con$$constant)) {
4951 __ fli_s(as_FloatRegister($dst$$reg), $con$$constant);
4952 } else {
4953 __ flw(as_FloatRegister($dst$$reg), $constantaddress($con));
4954 }
4955 %}
4956
4957 ins_pipe(fp_load_constant_s);
4958 %}
4959
4960 instruct loadConF0(fRegF dst, immF0 con) %{
4961 match(Set dst con);
4962
4963 ins_cost(XFER_COST);
4964
4965 format %{ "fmv.w.x $dst, zr\t# float, #@loadConF0" %}
4966
4967 ins_encode %{
4968 __ fmv_w_x(as_FloatRegister($dst$$reg), zr);
4969 %}
4970
4971 ins_pipe(fp_load_constant_s);
4972 %}
4973
4974 // Load Double Constant
4975 instruct loadConD(fRegD dst, immD con) %{
4976 match(Set dst con);
4977
4978 ins_cost(LOAD_COST);
4979 format %{
4980 "fld $dst, [$constantaddress]\t# load from constant table: double=$con, #@loadConD"
4981 %}
4982
4983 ins_encode %{
4984 if (MacroAssembler::can_dp_imm_load($con$$constant)) {
4985 __ fli_d(as_FloatRegister($dst$$reg), $con$$constant);
4986 } else {
4987 __ fld(as_FloatRegister($dst$$reg), $constantaddress($con));
4988 }
4989 %}
4990
4991 ins_pipe(fp_load_constant_d);
4992 %}
4993
4994 instruct loadConD0(fRegD dst, immD0 con) %{
4995 match(Set dst con);
4996
4997 ins_cost(XFER_COST);
4998
4999 format %{ "fmv.d.x $dst, zr\t# double, #@loadConD0" %}
5000
5001 ins_encode %{
5002 __ fmv_d_x(as_FloatRegister($dst$$reg), zr);
5003 %}
5004
5005 ins_pipe(fp_load_constant_d);
5006 %}
5007
5008 // Store Byte
5009 instruct storeB(iRegIorL2I src, memory mem)
5010 %{
5011 match(Set mem (StoreB mem src));
5012
5013 ins_cost(STORE_COST);
5014 format %{ "sb $src, $mem\t# byte, #@storeB" %}
5015
5016 ins_encode %{
5017 __ sb(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5018 %}
5019
5020 ins_pipe(istore_reg_mem);
5021 %}
5022
5023 instruct storeimmB0(immI0 zero, memory mem)
5024 %{
5025 match(Set mem (StoreB mem zero));
5026
5027 ins_cost(STORE_COST);
5028 format %{ "sb zr, $mem\t# byte, #@storeimmB0" %}
5029
5030 ins_encode %{
5031 __ sb(zr, Address(as_Register($mem$$base), $mem$$disp));
5032 %}
5033
5034 ins_pipe(istore_mem);
5035 %}
5036
5037 // Store Char/Short
5038 instruct storeC(iRegIorL2I src, memory mem)
5039 %{
5040 match(Set mem (StoreC mem src));
5041
5042 ins_cost(STORE_COST);
5043 format %{ "sh $src, $mem\t# short, #@storeC" %}
5044
5045 ins_encode %{
5046 __ sh(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5047 %}
5048
5049 ins_pipe(istore_reg_mem);
5050 %}
5051
5052 instruct storeimmC0(immI0 zero, memory mem)
5053 %{
5054 match(Set mem (StoreC mem zero));
5055
5056 ins_cost(STORE_COST);
5057 format %{ "sh zr, $mem\t# short, #@storeimmC0" %}
5058
5059 ins_encode %{
5060 __ sh(zr, Address(as_Register($mem$$base), $mem$$disp));
5061 %}
5062
5063 ins_pipe(istore_mem);
5064 %}
5065
5066 // Store Integer
5067 instruct storeI(iRegIorL2I src, memory mem)
5068 %{
5069 match(Set mem(StoreI mem src));
5070
5071 ins_cost(STORE_COST);
5072 format %{ "sw $src, $mem\t# int, #@storeI" %}
5073
5074 ins_encode %{
5075 __ sw(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5076 %}
5077
5078 ins_pipe(istore_reg_mem);
5079 %}
5080
5081 instruct storeimmI0(immI0 zero, memory mem)
5082 %{
5083 match(Set mem(StoreI mem zero));
5084
5085 ins_cost(STORE_COST);
5086 format %{ "sw zr, $mem\t# int, #@storeimmI0" %}
5087
5088 ins_encode %{
5089 __ sw(zr, Address(as_Register($mem$$base), $mem$$disp));
5090 %}
5091
5092 ins_pipe(istore_mem);
5093 %}
5094
5095 // Store Long (64 bit signed)
5096 instruct storeL(iRegL src, memory mem)
5097 %{
5098 match(Set mem (StoreL mem src));
5099
5100 ins_cost(STORE_COST);
5101 format %{ "sd $src, $mem\t# long, #@storeL" %}
5102
5103 ins_encode %{
5104 __ sd(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5105 %}
5106
5107 ins_pipe(istore_reg_mem);
5108 %}
5109
5110 // Store Long (64 bit signed)
5111 instruct storeimmL0(immL0 zero, memory mem)
5112 %{
5113 match(Set mem (StoreL mem zero));
5114
5115 ins_cost(STORE_COST);
5116 format %{ "sd zr, $mem\t# long, #@storeimmL0" %}
5117
5118 ins_encode %{
5119 __ sd(zr, Address(as_Register($mem$$base), $mem$$disp));
5120 %}
5121
5122 ins_pipe(istore_mem);
5123 %}
5124
5125 // Store Pointer
5126 instruct storeP(iRegP src, memory mem)
5127 %{
5128 match(Set mem (StoreP mem src));
5129 predicate(n->as_Store()->barrier_data() == 0);
5130
5131 ins_cost(STORE_COST);
5132 format %{ "sd $src, $mem\t# ptr, #@storeP" %}
5133
5134 ins_encode %{
5135 __ sd(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5136 %}
5137
5138 ins_pipe(istore_reg_mem);
5139 %}
5140
5141 // Store Pointer
5142 instruct storeimmP0(immP0 zero, memory mem)
5143 %{
5144 match(Set mem (StoreP mem zero));
5145 predicate(n->as_Store()->barrier_data() == 0);
5146
5147 ins_cost(STORE_COST);
5148 format %{ "sd zr, $mem\t# ptr, #@storeimmP0" %}
5149
5150 ins_encode %{
5151 __ sd(zr, Address(as_Register($mem$$base), $mem$$disp));
5152 %}
5153
5154 ins_pipe(istore_mem);
5155 %}
5156
5157 // Store Compressed Pointer
5158 instruct storeN(iRegN src, memory mem)
5159 %{
5160 predicate(n->as_Store()->barrier_data() == 0);
5161 match(Set mem (StoreN mem src));
5162
5163 ins_cost(STORE_COST);
5164 format %{ "sw $src, $mem\t# compressed ptr, #@storeN" %}
5165
5166 ins_encode %{
5167 __ sw(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5168 %}
5169
5170 ins_pipe(istore_reg_mem);
5171 %}
5172
5173 instruct storeImmN0(immN0 zero, memory mem)
5174 %{
5175 predicate(n->as_Store()->barrier_data() == 0);
5176 match(Set mem (StoreN mem zero));
5177
5178 ins_cost(STORE_COST);
5179 format %{ "sw zr, $mem\t# compressed ptr, #@storeImmN0" %}
5180
5181 ins_encode %{
5182 __ sw(zr, Address(as_Register($mem$$base), $mem$$disp));
5183 %}
5184
5185 ins_pipe(istore_reg_mem);
5186 %}
5187
5188 // Store Float
5189 instruct storeF(fRegF src, memory mem)
5190 %{
5191 match(Set mem (StoreF mem src));
5192
5193 ins_cost(STORE_COST);
5194 format %{ "fsw $src, $mem\t# float, #@storeF" %}
5195
5196 ins_encode %{
5197 __ fsw(as_FloatRegister($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5198 %}
5199
5200 ins_pipe(fp_store_reg_s);
5201 %}
5202
5203 // Store Double
5204 instruct storeD(fRegD src, memory mem)
5205 %{
5206 match(Set mem (StoreD mem src));
5207
5208 ins_cost(STORE_COST);
5209 format %{ "fsd $src, $mem\t# double, #@storeD" %}
5210
5211 ins_encode %{
5212 __ fsd(as_FloatRegister($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5213 %}
5214
5215 ins_pipe(fp_store_reg_d);
5216 %}
5217
5218 // Store Compressed Klass Pointer
5219 instruct storeNKlass(iRegN src, memory mem)
5220 %{
5221 match(Set mem (StoreNKlass mem src));
5222
5223 ins_cost(STORE_COST);
5224 format %{ "sw $src, $mem\t# compressed klass ptr, #@storeNKlass" %}
5225
5226 ins_encode %{
5227 __ sw(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5228 %}
5229
5230 ins_pipe(istore_reg_mem);
5231 %}
5232
5233 // ============================================================================
5234 // Prefetch instructions
5235 // Must be safe to execute with invalid address (cannot fault).
5236
5237 instruct prefetchalloc( memory mem ) %{
5238 predicate(UseZicbop);
5239 match(PrefetchAllocation mem);
5240
5241 ins_cost(ALU_COST * 1);
5242 format %{ "prefetch_w $mem\t# Prefetch for write" %}
5243
5244 ins_encode %{
5245 if (Assembler::is_simm12($mem$$disp)) {
5246 if (($mem$$disp & 0x1f) == 0) {
5247 __ prefetch_w(as_Register($mem$$base), $mem$$disp);
5248 } else {
5249 __ addi(t0, as_Register($mem$$base), $mem$$disp);
5250 __ prefetch_w(t0, 0);
5251 }
5252 } else {
5253 __ mv(t0, $mem$$disp);
5254 __ add(t0, as_Register($mem$$base), t0);
5255 __ prefetch_w(t0, 0);
5256 }
5257 %}
5258
5259 ins_pipe(iload_prefetch);
5260 %}
5261
5262 // ============================================================================
5263 // Atomic operation instructions
5264 //
5265
5266 // standard CompareAndSwapX when we are using barriers
5267 // these have higher priority than the rules selected by a predicate
5268 instruct compareAndSwapB(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5269 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5270 %{
5271 match(Set res (CompareAndSwapB mem (Binary oldval newval)));
5272
5273 ins_cost(LOAD_COST + STORE_COST + ALU_COST * 10 + BRANCH_COST * 4);
5274
5275 effect(TEMP_DEF res, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3, KILL cr);
5276
5277 format %{
5278 "cmpxchg $mem, $oldval, $newval\t# (byte) if $mem == $oldval then $mem <-- $newval\n\t"
5279 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapB"
5280 %}
5281
5282 ins_encode %{
5283 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5284 Assembler::relaxed /* acquire */, Assembler::rl /* release */, $res$$Register,
5285 true /* result as bool */, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5286 %}
5287
5288 ins_pipe(pipe_slow);
5289 %}
5290
5291 instruct compareAndSwapS(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5292 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5293 %{
5294 match(Set res (CompareAndSwapS mem (Binary oldval newval)));
5295
5296 ins_cost(LOAD_COST + STORE_COST + ALU_COST * 11 + BRANCH_COST * 4);
5297
5298 effect(TEMP_DEF res, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3, KILL cr);
5299
5300 format %{
5301 "cmpxchg $mem, $oldval, $newval\t# (short) if $mem == $oldval then $mem <-- $newval\n\t"
5302 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapS"
5303 %}
5304
5305 ins_encode %{
5306 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5307 Assembler::relaxed /* acquire */, Assembler::rl /* release */, $res$$Register,
5308 true /* result as bool */, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5309 %}
5310
5311 ins_pipe(pipe_slow);
5312 %}
5313
5314 instruct compareAndSwapI(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5315 %{
5316 match(Set res (CompareAndSwapI mem (Binary oldval newval)));
5317
5318 ins_cost(LOAD_COST + STORE_COST + ALU_COST * 6 + BRANCH_COST * 4);
5319
5320 format %{
5321 "cmpxchg $mem, $oldval, $newval\t# (int) if $mem == $oldval then $mem <-- $newval\n\t"
5322 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapI"
5323 %}
5324
5325 ins_encode(riscv_enc_cmpxchgw(res, mem, oldval, newval));
5326
5327 ins_pipe(pipe_slow);
5328 %}
5329
5330 instruct compareAndSwapL(iRegINoSp res, indirect mem, iRegL oldval, iRegL newval)
5331 %{
5332 match(Set res (CompareAndSwapL mem (Binary oldval newval)));
5333
5334 ins_cost(LOAD_COST + STORE_COST + ALU_COST * 6 + BRANCH_COST * 4);
5335
5336 format %{
5337 "cmpxchg $mem, $oldval, $newval\t# (long) if $mem == $oldval then $mem <-- $newval\n\t"
5338 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapL"
5339 %}
5340
5341 ins_encode(riscv_enc_cmpxchg(res, mem, oldval, newval));
5342
5343 ins_pipe(pipe_slow);
5344 %}
5345
5346 instruct compareAndSwapP(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval)
5347 %{
5348 predicate(n->as_LoadStore()->barrier_data() == 0);
5349
5350 match(Set res (CompareAndSwapP mem (Binary oldval newval)));
5351
5352 ins_cost(LOAD_COST + STORE_COST + ALU_COST * 6 + BRANCH_COST * 4);
5353
5354 format %{
5355 "cmpxchg $mem, $oldval, $newval\t# (ptr) if $mem == $oldval then $mem <-- $newval\n\t"
5356 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapP"
5357 %}
5358
5359 ins_encode(riscv_enc_cmpxchg(res, mem, oldval, newval));
5360
5361 ins_pipe(pipe_slow);
5362 %}
5363
5364 instruct compareAndSwapN(iRegINoSp res, indirect mem, iRegN oldval, iRegN newval)
5365 %{
5366 predicate(n->as_LoadStore()->barrier_data() == 0);
5367 match(Set res (CompareAndSwapN mem (Binary oldval newval)));
5368
5369 ins_cost(LOAD_COST + STORE_COST + ALU_COST * 8 + BRANCH_COST * 4);
5370
5371 format %{
5372 "cmpxchg $mem, $oldval, $newval\t# (narrow oop) if $mem == $oldval then $mem <-- $newval\n\t"
5373 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapN"
5374 %}
5375
5376 ins_encode(riscv_enc_cmpxchgn(res, mem, oldval, newval));
5377
5378 ins_pipe(pipe_slow);
5379 %}
5380
5381 // alternative CompareAndSwapX when we are eliding barriers
5382 instruct compareAndSwapBAcq(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5383 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5384 %{
5385 predicate(needs_acquiring_load_reserved(n));
5386
5387 match(Set res (CompareAndSwapB mem (Binary oldval newval)));
5388
5389 ins_cost(LOAD_COST + STORE_COST + ALU_COST * 10 + BRANCH_COST * 4);
5390
5391 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5392
5393 format %{
5394 "cmpxchg_acq $mem, $oldval, $newval\t# (byte) if $mem == $oldval then $mem <-- $newval\n\t"
5395 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapBAcq"
5396 %}
5397
5398 ins_encode %{
5399 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5400 Assembler::aq /* acquire */, Assembler::rl /* release */, $res$$Register,
5401 true /* result as bool */, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5402 %}
5403
5404 ins_pipe(pipe_slow);
5405 %}
5406
5407 instruct compareAndSwapSAcq(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5408 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5409 %{
5410 predicate(needs_acquiring_load_reserved(n));
5411
5412 match(Set res (CompareAndSwapS mem (Binary oldval newval)));
5413
5414 ins_cost(LOAD_COST + STORE_COST + ALU_COST * 11 + BRANCH_COST * 4);
5415
5416 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5417
5418 format %{
5419 "cmpxchg_acq $mem, $oldval, $newval\t# (short) if $mem == $oldval then $mem <-- $newval\n\t"
5420 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapSAcq"
5421 %}
5422
5423 ins_encode %{
5424 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5425 Assembler::aq /* acquire */, Assembler::rl /* release */, $res$$Register,
5426 true /* result as bool */, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5427 %}
5428
5429 ins_pipe(pipe_slow);
5430 %}
5431
5432 instruct compareAndSwapIAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5433 %{
5434 predicate(needs_acquiring_load_reserved(n));
5435
5436 match(Set res (CompareAndSwapI mem (Binary oldval newval)));
5437
5438 ins_cost(LOAD_COST + STORE_COST + ALU_COST * 6 + BRANCH_COST * 4);
5439
5440 format %{
5441 "cmpxchg_acq $mem, $oldval, $newval\t# (int) if $mem == $oldval then $mem <-- $newval\n\t"
5442 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapIAcq"
5443 %}
5444
5445 ins_encode(riscv_enc_cmpxchgw_acq(res, mem, oldval, newval));
5446
5447 ins_pipe(pipe_slow);
5448 %}
5449
5450 instruct compareAndSwapLAcq(iRegINoSp res, indirect mem, iRegL oldval, iRegL newval)
5451 %{
5452 predicate(needs_acquiring_load_reserved(n));
5453
5454 match(Set res (CompareAndSwapL mem (Binary oldval newval)));
5455
5456 ins_cost(LOAD_COST + STORE_COST + ALU_COST * 6 + BRANCH_COST * 4);
5457
5458 format %{
5459 "cmpxchg_acq $mem, $oldval, $newval\t# (long) if $mem == $oldval then $mem <-- $newval\n\t"
5460 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapLAcq"
5461 %}
5462
5463 ins_encode(riscv_enc_cmpxchg_acq(res, mem, oldval, newval));
5464
5465 ins_pipe(pipe_slow);
5466 %}
5467
5468 instruct compareAndSwapPAcq(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval)
5469 %{
5470 predicate(needs_acquiring_load_reserved(n) && (n->as_LoadStore()->barrier_data() == 0));
5471
5472 match(Set res (CompareAndSwapP mem (Binary oldval newval)));
5473
5474 ins_cost(LOAD_COST + STORE_COST + ALU_COST * 6 + BRANCH_COST * 4);
5475
5476 format %{
5477 "cmpxchg_acq $mem, $oldval, $newval\t# (ptr) if $mem == $oldval then $mem <-- $newval\n\t"
5478 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapPAcq"
5479 %}
5480
5481 ins_encode(riscv_enc_cmpxchg_acq(res, mem, oldval, newval));
5482
5483 ins_pipe(pipe_slow);
5484 %}
5485
5486 instruct compareAndSwapNAcq(iRegINoSp res, indirect mem, iRegN oldval, iRegN newval)
5487 %{
5488 predicate(needs_acquiring_load_reserved(n) && n->as_LoadStore()->barrier_data() == 0);
5489
5490 match(Set res (CompareAndSwapN mem (Binary oldval newval)));
5491
5492 ins_cost(LOAD_COST + STORE_COST + ALU_COST * 8 + BRANCH_COST * 4);
5493
5494 format %{
5495 "cmpxchg_acq $mem, $oldval, $newval\t# (narrow oop) if $mem == $oldval then $mem <-- $newval\n\t"
5496 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapNAcq"
5497 %}
5498
5499 ins_encode(riscv_enc_cmpxchgn_acq(res, mem, oldval, newval));
5500
5501 ins_pipe(pipe_slow);
5502 %}
5503
5504 // Sundry CAS operations. Note that release is always true,
5505 // regardless of the memory ordering of the CAS. This is because we
5506 // need the volatile case to be sequentially consistent but there is
5507 // no trailing StoreLoad barrier emitted by C2. Unfortunately we
5508 // can't check the type of memory ordering here, so we always emit a
5509 // sc_d(w) with rl bit set.
5510 instruct compareAndExchangeB(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5511 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5512 %{
5513 match(Set res (CompareAndExchangeB mem (Binary oldval newval)));
5514
5515 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST * 5);
5516
5517 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5518
5519 format %{
5520 "cmpxchg $res = $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeB"
5521 %}
5522
5523 ins_encode %{
5524 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5525 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
5526 /*result_as_bool*/ false, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5527 %}
5528
5529 ins_pipe(pipe_slow);
5530 %}
5531
5532 instruct compareAndExchangeS(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5533 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5534 %{
5535 match(Set res (CompareAndExchangeS mem (Binary oldval newval)));
5536
5537 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST * 6);
5538
5539 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5540
5541 format %{
5542 "cmpxchg $res = $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeS"
5543 %}
5544
5545 ins_encode %{
5546 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5547 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
5548 /*result_as_bool*/ false, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5549 %}
5550
5551 ins_pipe(pipe_slow);
5552 %}
5553
5554 instruct compareAndExchangeI(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5555 %{
5556 match(Set res (CompareAndExchangeI mem (Binary oldval newval)));
5557
5558 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST);
5559
5560 effect(TEMP_DEF res);
5561
5562 format %{
5563 "cmpxchg $res = $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeI"
5564 %}
5565
5566 ins_encode %{
5567 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
5568 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5569 %}
5570
5571 ins_pipe(pipe_slow);
5572 %}
5573
5574 instruct compareAndExchangeL(iRegLNoSp res, indirect mem, iRegL oldval, iRegL newval)
5575 %{
5576 match(Set res (CompareAndExchangeL mem (Binary oldval newval)));
5577
5578 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST);
5579
5580 effect(TEMP_DEF res);
5581
5582 format %{
5583 "cmpxchg $res = $mem, $oldval, $newval\t# (long, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeL"
5584 %}
5585
5586 ins_encode %{
5587 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5588 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5589 %}
5590
5591 ins_pipe(pipe_slow);
5592 %}
5593
5594 instruct compareAndExchangeN(iRegNNoSp res, indirect mem, iRegN oldval, iRegN newval)
5595 %{
5596 predicate(n->as_LoadStore()->barrier_data() == 0);
5597 match(Set res (CompareAndExchangeN mem (Binary oldval newval)));
5598
5599 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST * 3);
5600
5601 effect(TEMP_DEF res);
5602
5603 format %{
5604 "cmpxchg $res = $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeN"
5605 %}
5606
5607 ins_encode %{
5608 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
5609 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5610 %}
5611
5612 ins_pipe(pipe_slow);
5613 %}
5614
5615 instruct compareAndExchangeP(iRegPNoSp res, indirect mem, iRegP oldval, iRegP newval)
5616 %{
5617 predicate(n->as_LoadStore()->barrier_data() == 0);
5618 match(Set res (CompareAndExchangeP mem (Binary oldval newval)));
5619
5620 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST);
5621
5622 effect(TEMP_DEF res);
5623
5624 format %{
5625 "cmpxchg $res = $mem, $oldval, $newval\t# (ptr, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeP"
5626 %}
5627
5628 ins_encode %{
5629 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5630 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5631 %}
5632
5633 ins_pipe(pipe_slow);
5634 %}
5635
5636 instruct compareAndExchangeBAcq(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5637 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5638 %{
5639 predicate(needs_acquiring_load_reserved(n));
5640
5641 match(Set res (CompareAndExchangeB mem (Binary oldval newval)));
5642
5643 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST * 5);
5644
5645 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5646
5647 format %{
5648 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeBAcq"
5649 %}
5650
5651 ins_encode %{
5652 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5653 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
5654 /*result_as_bool*/ false, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5655 %}
5656
5657 ins_pipe(pipe_slow);
5658 %}
5659
5660 instruct compareAndExchangeSAcq(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5661 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5662 %{
5663 predicate(needs_acquiring_load_reserved(n));
5664
5665 match(Set res (CompareAndExchangeS mem (Binary oldval newval)));
5666
5667 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST * 6);
5668
5669 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5670
5671 format %{
5672 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeSAcq"
5673 %}
5674
5675 ins_encode %{
5676 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5677 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
5678 /*result_as_bool*/ false, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5679 %}
5680
5681 ins_pipe(pipe_slow);
5682 %}
5683
5684 instruct compareAndExchangeIAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5685 %{
5686 predicate(needs_acquiring_load_reserved(n));
5687
5688 match(Set res (CompareAndExchangeI mem (Binary oldval newval)));
5689
5690 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST);
5691
5692 effect(TEMP_DEF res);
5693
5694 format %{
5695 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeIAcq"
5696 %}
5697
5698 ins_encode %{
5699 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
5700 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
5701 %}
5702
5703 ins_pipe(pipe_slow);
5704 %}
5705
5706 instruct compareAndExchangeLAcq(iRegLNoSp res, indirect mem, iRegL oldval, iRegL newval)
5707 %{
5708 predicate(needs_acquiring_load_reserved(n));
5709
5710 match(Set res (CompareAndExchangeL mem (Binary oldval newval)));
5711
5712 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST);
5713
5714 effect(TEMP_DEF res);
5715
5716 format %{
5717 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (long, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeLAcq"
5718 %}
5719
5720 ins_encode %{
5721 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5722 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
5723 %}
5724
5725 ins_pipe(pipe_slow);
5726 %}
5727
5728 instruct compareAndExchangeNAcq(iRegNNoSp res, indirect mem, iRegN oldval, iRegN newval)
5729 %{
5730 predicate(needs_acquiring_load_reserved(n) && n->as_LoadStore()->barrier_data() == 0);
5731
5732 match(Set res (CompareAndExchangeN mem (Binary oldval newval)));
5733
5734 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST);
5735
5736 effect(TEMP_DEF res);
5737
5738 format %{
5739 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeNAcq"
5740 %}
5741
5742 ins_encode %{
5743 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
5744 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
5745 %}
5746
5747 ins_pipe(pipe_slow);
5748 %}
5749
5750 instruct compareAndExchangePAcq(iRegPNoSp res, indirect mem, iRegP oldval, iRegP newval)
5751 %{
5752 predicate(needs_acquiring_load_reserved(n) && (n->as_LoadStore()->barrier_data() == 0));
5753
5754 match(Set res (CompareAndExchangeP mem (Binary oldval newval)));
5755
5756 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST);
5757
5758 effect(TEMP_DEF res);
5759
5760 format %{
5761 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (ptr, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangePAcq"
5762 %}
5763
5764 ins_encode %{
5765 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5766 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
5767 %}
5768
5769 ins_pipe(pipe_slow);
5770 %}
5771
5772 instruct weakCompareAndSwapB(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5773 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5774 %{
5775 match(Set res (WeakCompareAndSwapB mem (Binary oldval newval)));
5776
5777 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 6);
5778
5779 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5780
5781 format %{
5782 "weak_cmpxchg $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5783 "# $res == 1 when success, #@weakCompareAndSwapB"
5784 %}
5785
5786 ins_encode %{
5787 __ weak_cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5788 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
5789 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5790 %}
5791
5792 ins_pipe(pipe_slow);
5793 %}
5794
5795 instruct weakCompareAndSwapS(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5796 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5797 %{
5798 match(Set res (WeakCompareAndSwapS mem (Binary oldval newval)));
5799
5800 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 7);
5801
5802 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5803
5804 format %{
5805 "weak_cmpxchg $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5806 "# $res == 1 when success, #@weakCompareAndSwapS"
5807 %}
5808
5809 ins_encode %{
5810 __ weak_cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5811 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
5812 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5813 %}
5814
5815 ins_pipe(pipe_slow);
5816 %}
5817
5818 instruct weakCompareAndSwapI(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5819 %{
5820 match(Set res (WeakCompareAndSwapI mem (Binary oldval newval)));
5821
5822 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 2);
5823
5824 format %{
5825 "weak_cmpxchg $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5826 "# $res == 1 when success, #@weakCompareAndSwapI"
5827 %}
5828
5829 ins_encode %{
5830 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
5831 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5832 %}
5833
5834 ins_pipe(pipe_slow);
5835 %}
5836
5837 instruct weakCompareAndSwapL(iRegINoSp res, indirect mem, iRegL oldval, iRegL newval)
5838 %{
5839 match(Set res (WeakCompareAndSwapL mem (Binary oldval newval)));
5840
5841 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 2);
5842
5843 format %{
5844 "weak_cmpxchg $mem, $oldval, $newval\t# (long, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5845 "# $res == 1 when success, #@weakCompareAndSwapL"
5846 %}
5847
5848 ins_encode %{
5849 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5850 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5851 %}
5852
5853 ins_pipe(pipe_slow);
5854 %}
5855
5856 instruct weakCompareAndSwapN(iRegINoSp res, indirect mem, iRegN oldval, iRegN newval)
5857 %{
5858 predicate(n->as_LoadStore()->barrier_data() == 0);
5859 match(Set res (WeakCompareAndSwapN mem (Binary oldval newval)));
5860
5861 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 4);
5862
5863 format %{
5864 "weak_cmpxchg $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5865 "# $res == 1 when success, #@weakCompareAndSwapN"
5866 %}
5867
5868 ins_encode %{
5869 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
5870 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5871 %}
5872
5873 ins_pipe(pipe_slow);
5874 %}
5875
5876 instruct weakCompareAndSwapP(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval)
5877 %{
5878 predicate(n->as_LoadStore()->barrier_data() == 0);
5879 match(Set res (WeakCompareAndSwapP mem (Binary oldval newval)));
5880
5881 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 2);
5882
5883 format %{
5884 "weak_cmpxchg $mem, $oldval, $newval\t# (ptr, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5885 "# $res == 1 when success, #@weakCompareAndSwapP"
5886 %}
5887
5888 ins_encode %{
5889 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5890 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5891 %}
5892
5893 ins_pipe(pipe_slow);
5894 %}
5895
5896 instruct weakCompareAndSwapBAcq(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5897 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5898 %{
5899 predicate(needs_acquiring_load_reserved(n));
5900
5901 match(Set res (WeakCompareAndSwapB mem (Binary oldval newval)));
5902
5903 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 6);
5904
5905 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5906
5907 format %{
5908 "weak_cmpxchg_acq $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5909 "# $res == 1 when success, #@weakCompareAndSwapBAcq"
5910 %}
5911
5912 ins_encode %{
5913 __ weak_cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5914 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
5915 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5916 %}
5917
5918 ins_pipe(pipe_slow);
5919 %}
5920
5921 instruct weakCompareAndSwapSAcq(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5922 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5923 %{
5924 predicate(needs_acquiring_load_reserved(n));
5925
5926 match(Set res (WeakCompareAndSwapS mem (Binary oldval newval)));
5927
5928 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 7);
5929
5930 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5931
5932 format %{
5933 "weak_cmpxchg_acq $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5934 "# $res == 1 when success, #@weakCompareAndSwapSAcq"
5935 %}
5936
5937 ins_encode %{
5938 __ weak_cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5939 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
5940 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5941 %}
5942
5943 ins_pipe(pipe_slow);
5944 %}
5945
5946 instruct weakCompareAndSwapIAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5947 %{
5948 predicate(needs_acquiring_load_reserved(n));
5949
5950 match(Set res (WeakCompareAndSwapI mem (Binary oldval newval)));
5951
5952 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 2);
5953
5954 format %{
5955 "weak_cmpxchg_acq $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5956 "# $res == 1 when success, #@weakCompareAndSwapIAcq"
5957 %}
5958
5959 ins_encode %{
5960 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
5961 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
5962 %}
5963
5964 ins_pipe(pipe_slow);
5965 %}
5966
5967 instruct weakCompareAndSwapLAcq(iRegINoSp res, indirect mem, iRegL oldval, iRegL newval)
5968 %{
5969 predicate(needs_acquiring_load_reserved(n));
5970
5971 match(Set res (WeakCompareAndSwapL mem (Binary oldval newval)));
5972
5973 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 2);
5974
5975 format %{
5976 "weak_cmpxchg_acq $mem, $oldval, $newval\t# (long, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5977 "# $res == 1 when success, #@weakCompareAndSwapLAcq"
5978 %}
5979
5980 ins_encode %{
5981 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5982 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
5983 %}
5984
5985 ins_pipe(pipe_slow);
5986 %}
5987
5988 instruct weakCompareAndSwapNAcq(iRegINoSp res, indirect mem, iRegN oldval, iRegN newval)
5989 %{
5990 predicate(needs_acquiring_load_reserved(n) && n->as_LoadStore()->barrier_data() == 0);
5991
5992 match(Set res (WeakCompareAndSwapN mem (Binary oldval newval)));
5993
5994 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 4);
5995
5996 format %{
5997 "weak_cmpxchg_acq $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5998 "# $res == 1 when success, #@weakCompareAndSwapNAcq"
5999 %}
6000
6001 ins_encode %{
6002 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
6003 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
6004 %}
6005
6006 ins_pipe(pipe_slow);
6007 %}
6008
6009 instruct weakCompareAndSwapPAcq(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval)
6010 %{
6011 predicate(needs_acquiring_load_reserved(n) && (n->as_LoadStore()->barrier_data() == 0));
6012
6013 match(Set res (WeakCompareAndSwapP mem (Binary oldval newval)));
6014
6015 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 2);
6016
6017 format %{
6018 "weak_cmpxchg_acq $mem, $oldval, $newval\t# (ptr, weak) if $mem == $oldval then $mem <-- $newval\n\t"
6019 "\t# $res == 1 when success, #@weakCompareAndSwapPAcq"
6020 %}
6021
6022 ins_encode %{
6023 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
6024 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
6025 %}
6026
6027 ins_pipe(pipe_slow);
6028 %}
6029
6030 instruct get_and_setI(indirect mem, iRegI newv, iRegINoSp prev)
6031 %{
6032 match(Set prev (GetAndSetI mem newv));
6033
6034 ins_cost(ALU_COST);
6035
6036 format %{ "atomic_xchgw $prev, $newv, [$mem]\t#@get_and_setI" %}
6037
6038 ins_encode %{
6039 __ atomic_xchgw($prev$$Register, $newv$$Register, as_Register($mem$$base));
6040 %}
6041
6042 ins_pipe(pipe_serial);
6043 %}
6044
6045 instruct get_and_setL(indirect mem, iRegL newv, iRegLNoSp prev)
6046 %{
6047 match(Set prev (GetAndSetL mem newv));
6048
6049 ins_cost(ALU_COST);
6050
6051 format %{ "atomic_xchg $prev, $newv, [$mem]\t#@get_and_setL" %}
6052
6053 ins_encode %{
6054 __ atomic_xchg($prev$$Register, $newv$$Register, as_Register($mem$$base));
6055 %}
6056
6057 ins_pipe(pipe_serial);
6058 %}
6059
6060 instruct get_and_setN(indirect mem, iRegN newv, iRegINoSp prev)
6061 %{
6062 predicate(n->as_LoadStore()->barrier_data() == 0);
6063
6064 match(Set prev (GetAndSetN mem newv));
6065
6066 ins_cost(ALU_COST);
6067
6068 format %{ "atomic_xchgwu $prev, $newv, [$mem]\t#@get_and_setN" %}
6069
6070 ins_encode %{
6071 __ atomic_xchgwu($prev$$Register, $newv$$Register, as_Register($mem$$base));
6072 %}
6073
6074 ins_pipe(pipe_serial);
6075 %}
6076
6077 instruct get_and_setP(indirect mem, iRegP newv, iRegPNoSp prev)
6078 %{
6079 predicate(n->as_LoadStore()->barrier_data() == 0);
6080 match(Set prev (GetAndSetP mem newv));
6081
6082 ins_cost(ALU_COST);
6083
6084 format %{ "atomic_xchg $prev, $newv, [$mem]\t#@get_and_setP" %}
6085
6086 ins_encode %{
6087 __ atomic_xchg($prev$$Register, $newv$$Register, as_Register($mem$$base));
6088 %}
6089
6090 ins_pipe(pipe_serial);
6091 %}
6092
6093 instruct get_and_setIAcq(indirect mem, iRegI newv, iRegINoSp prev)
6094 %{
6095 predicate(needs_acquiring_load_reserved(n));
6096
6097 match(Set prev (GetAndSetI mem newv));
6098
6099 ins_cost(ALU_COST);
6100
6101 format %{ "atomic_xchgw_acq $prev, $newv, [$mem]\t#@get_and_setIAcq" %}
6102
6103 ins_encode %{
6104 __ atomic_xchgalw($prev$$Register, $newv$$Register, as_Register($mem$$base));
6105 %}
6106
6107 ins_pipe(pipe_serial);
6108 %}
6109
6110 instruct get_and_setLAcq(indirect mem, iRegL newv, iRegLNoSp prev)
6111 %{
6112 predicate(needs_acquiring_load_reserved(n));
6113
6114 match(Set prev (GetAndSetL mem newv));
6115
6116 ins_cost(ALU_COST);
6117
6118 format %{ "atomic_xchg_acq $prev, $newv, [$mem]\t#@get_and_setLAcq" %}
6119
6120 ins_encode %{
6121 __ atomic_xchgal($prev$$Register, $newv$$Register, as_Register($mem$$base));
6122 %}
6123
6124 ins_pipe(pipe_serial);
6125 %}
6126
6127 instruct get_and_setNAcq(indirect mem, iRegN newv, iRegINoSp prev)
6128 %{
6129 predicate(needs_acquiring_load_reserved(n) && n->as_LoadStore()->barrier_data() == 0);
6130
6131 match(Set prev (GetAndSetN mem newv));
6132
6133 ins_cost(ALU_COST);
6134
6135 format %{ "atomic_xchgwu_acq $prev, $newv, [$mem]\t#@get_and_setNAcq" %}
6136
6137 ins_encode %{
6138 __ atomic_xchgalwu($prev$$Register, $newv$$Register, as_Register($mem$$base));
6139 %}
6140
6141 ins_pipe(pipe_serial);
6142 %}
6143
6144 instruct get_and_setPAcq(indirect mem, iRegP newv, iRegPNoSp prev)
6145 %{
6146 predicate(needs_acquiring_load_reserved(n) && (n->as_LoadStore()->barrier_data() == 0));
6147
6148 match(Set prev (GetAndSetP mem newv));
6149
6150 ins_cost(ALU_COST);
6151
6152 format %{ "atomic_xchg_acq $prev, $newv, [$mem]\t#@get_and_setPAcq" %}
6153
6154 ins_encode %{
6155 __ atomic_xchgal($prev$$Register, $newv$$Register, as_Register($mem$$base));
6156 %}
6157
6158 ins_pipe(pipe_serial);
6159 %}
6160
6161 instruct get_and_addL(indirect mem, iRegLNoSp newval, iRegL incr)
6162 %{
6163 match(Set newval (GetAndAddL mem incr));
6164
6165 ins_cost(ALU_COST);
6166
6167 format %{ "get_and_addL $newval, [$mem], $incr\t#@get_and_addL" %}
6168
6169 ins_encode %{
6170 __ atomic_add($newval$$Register, $incr$$Register, as_Register($mem$$base));
6171 %}
6172
6173 ins_pipe(pipe_serial);
6174 %}
6175
6176 instruct get_and_addL_no_res(indirect mem, Universe dummy, iRegL incr)
6177 %{
6178 predicate(n->as_LoadStore()->result_not_used());
6179
6180 match(Set dummy (GetAndAddL mem incr));
6181
6182 ins_cost(ALU_COST);
6183
6184 format %{ "get_and_addL [$mem], $incr\t#@get_and_addL_no_res" %}
6185
6186 ins_encode %{
6187 __ atomic_add(noreg, $incr$$Register, as_Register($mem$$base));
6188 %}
6189
6190 ins_pipe(pipe_serial);
6191 %}
6192
6193 instruct get_and_addLi(indirect mem, iRegLNoSp newval, immLAdd incr)
6194 %{
6195 match(Set newval (GetAndAddL mem incr));
6196
6197 ins_cost(ALU_COST);
6198
6199 format %{ "get_and_addL $newval, [$mem], $incr\t#@get_and_addLi" %}
6200
6201 ins_encode %{
6202 __ atomic_add($newval$$Register, $incr$$constant, as_Register($mem$$base));
6203 %}
6204
6205 ins_pipe(pipe_serial);
6206 %}
6207
6208 instruct get_and_addLi_no_res(indirect mem, Universe dummy, immLAdd incr)
6209 %{
6210 predicate(n->as_LoadStore()->result_not_used());
6211
6212 match(Set dummy (GetAndAddL mem incr));
6213
6214 ins_cost(ALU_COST);
6215
6216 format %{ "get_and_addL [$mem], $incr\t#@get_and_addLi_no_res" %}
6217
6218 ins_encode %{
6219 __ atomic_add(noreg, $incr$$constant, as_Register($mem$$base));
6220 %}
6221
6222 ins_pipe(pipe_serial);
6223 %}
6224
6225 instruct get_and_addI(indirect mem, iRegINoSp newval, iRegIorL2I incr)
6226 %{
6227 match(Set newval (GetAndAddI mem incr));
6228
6229 ins_cost(ALU_COST);
6230
6231 format %{ "get_and_addI $newval, [$mem], $incr\t#@get_and_addI" %}
6232
6233 ins_encode %{
6234 __ atomic_addw($newval$$Register, $incr$$Register, as_Register($mem$$base));
6235 %}
6236
6237 ins_pipe(pipe_serial);
6238 %}
6239
6240 instruct get_and_addI_no_res(indirect mem, Universe dummy, iRegIorL2I incr)
6241 %{
6242 predicate(n->as_LoadStore()->result_not_used());
6243
6244 match(Set dummy (GetAndAddI mem incr));
6245
6246 ins_cost(ALU_COST);
6247
6248 format %{ "get_and_addI [$mem], $incr\t#@get_and_addI_no_res" %}
6249
6250 ins_encode %{
6251 __ atomic_addw(noreg, $incr$$Register, as_Register($mem$$base));
6252 %}
6253
6254 ins_pipe(pipe_serial);
6255 %}
6256
6257 instruct get_and_addIi(indirect mem, iRegINoSp newval, immIAdd incr)
6258 %{
6259 match(Set newval (GetAndAddI mem incr));
6260
6261 ins_cost(ALU_COST);
6262
6263 format %{ "get_and_addI $newval, [$mem], $incr\t#@get_and_addIi" %}
6264
6265 ins_encode %{
6266 __ atomic_addw($newval$$Register, $incr$$constant, as_Register($mem$$base));
6267 %}
6268
6269 ins_pipe(pipe_serial);
6270 %}
6271
6272 instruct get_and_addIi_no_res(indirect mem, Universe dummy, immIAdd incr)
6273 %{
6274 predicate(n->as_LoadStore()->result_not_used());
6275
6276 match(Set dummy (GetAndAddI mem incr));
6277
6278 ins_cost(ALU_COST);
6279
6280 format %{ "get_and_addI [$mem], $incr\t#@get_and_addIi_no_res" %}
6281
6282 ins_encode %{
6283 __ atomic_addw(noreg, $incr$$constant, as_Register($mem$$base));
6284 %}
6285
6286 ins_pipe(pipe_serial);
6287 %}
6288
6289 instruct get_and_addLAcq(indirect mem, iRegLNoSp newval, iRegL incr)
6290 %{
6291 predicate(needs_acquiring_load_reserved(n));
6292
6293 match(Set newval (GetAndAddL mem incr));
6294
6295 ins_cost(ALU_COST);
6296
6297 format %{ "get_and_addL_acq $newval, [$mem], $incr\t#@get_and_addLAcq" %}
6298
6299 ins_encode %{
6300 __ atomic_addal($newval$$Register, $incr$$Register, as_Register($mem$$base));
6301 %}
6302
6303 ins_pipe(pipe_serial);
6304 %}
6305
6306 instruct get_and_addL_no_resAcq(indirect mem, Universe dummy, iRegL incr) %{
6307 predicate(n->as_LoadStore()->result_not_used() && needs_acquiring_load_reserved(n));
6308
6309 match(Set dummy (GetAndAddL mem incr));
6310
6311 ins_cost(ALU_COST);
6312
6313 format %{ "get_and_addL_acq [$mem], $incr\t#@get_and_addL_no_resAcq" %}
6314
6315 ins_encode %{
6316 __ atomic_addal(noreg, $incr$$Register, as_Register($mem$$base));
6317 %}
6318
6319 ins_pipe(pipe_serial);
6320 %}
6321
6322 instruct get_and_addLiAcq(indirect mem, iRegLNoSp newval, immLAdd incr)
6323 %{
6324 predicate(needs_acquiring_load_reserved(n));
6325
6326 match(Set newval (GetAndAddL mem incr));
6327
6328 ins_cost(ALU_COST);
6329
6330 format %{ "get_and_addL_acq $newval, [$mem], $incr\t#@get_and_addLiAcq" %}
6331
6332 ins_encode %{
6333 __ atomic_addal($newval$$Register, $incr$$constant, as_Register($mem$$base));
6334 %}
6335
6336 ins_pipe(pipe_serial);
6337 %}
6338
6339 instruct get_and_addLi_no_resAcq(indirect mem, Universe dummy, immLAdd incr)
6340 %{
6341 predicate(n->as_LoadStore()->result_not_used() && needs_acquiring_load_reserved(n));
6342
6343 match(Set dummy (GetAndAddL mem incr));
6344
6345 ins_cost(ALU_COST);
6346
6347 format %{ "get_and_addL_acq [$mem], $incr\t#@get_and_addLi_no_resAcq" %}
6348
6349 ins_encode %{
6350 __ atomic_addal(noreg, $incr$$constant, as_Register($mem$$base));
6351 %}
6352
6353 ins_pipe(pipe_serial);
6354 %}
6355
6356 instruct get_and_addIAcq(indirect mem, iRegINoSp newval, iRegIorL2I incr)
6357 %{
6358 predicate(needs_acquiring_load_reserved(n));
6359
6360 match(Set newval (GetAndAddI mem incr));
6361
6362 ins_cost(ALU_COST);
6363
6364 format %{ "get_and_addI_acq $newval, [$mem], $incr\t#@get_and_addIAcq" %}
6365
6366 ins_encode %{
6367 __ atomic_addalw($newval$$Register, $incr$$Register, as_Register($mem$$base));
6368 %}
6369
6370 ins_pipe(pipe_serial);
6371 %}
6372
6373 instruct get_and_addI_no_resAcq(indirect mem, Universe dummy, iRegIorL2I incr)
6374 %{
6375 predicate(n->as_LoadStore()->result_not_used() && needs_acquiring_load_reserved(n));
6376
6377 match(Set dummy (GetAndAddI mem incr));
6378
6379 ins_cost(ALU_COST);
6380
6381 format %{ "get_and_addI_acq [$mem], $incr\t#@get_and_addI_no_resAcq" %}
6382
6383 ins_encode %{
6384 __ atomic_addalw(noreg, $incr$$Register, as_Register($mem$$base));
6385 %}
6386
6387 ins_pipe(pipe_serial);
6388 %}
6389
6390 instruct get_and_addIiAcq(indirect mem, iRegINoSp newval, immIAdd incr)
6391 %{
6392 predicate(needs_acquiring_load_reserved(n));
6393
6394 match(Set newval (GetAndAddI mem incr));
6395
6396 ins_cost(ALU_COST);
6397
6398 format %{ "get_and_addI_acq $newval, [$mem], $incr\t#@get_and_addIiAcq" %}
6399
6400 ins_encode %{
6401 __ atomic_addalw($newval$$Register, $incr$$constant, as_Register($mem$$base));
6402 %}
6403
6404 ins_pipe(pipe_serial);
6405 %}
6406
6407 instruct get_and_addIi_no_resAcq(indirect mem, Universe dummy, immIAdd incr)
6408 %{
6409 predicate(n->as_LoadStore()->result_not_used() && needs_acquiring_load_reserved(n));
6410
6411 match(Set dummy (GetAndAddI mem incr));
6412
6413 ins_cost(ALU_COST);
6414
6415 format %{ "get_and_addI_acq [$mem], $incr\t#@get_and_addIi_no_resAcq" %}
6416
6417 ins_encode %{
6418 __ atomic_addalw(noreg, $incr$$constant, as_Register($mem$$base));
6419 %}
6420
6421 ins_pipe(pipe_serial);
6422 %}
6423
6424 // ============================================================================
6425 // Arithmetic Instructions
6426 //
6427
6428 // Integer Addition
6429
6430 // TODO
6431 // these currently employ operations which do not set CR and hence are
6432 // not flagged as killing CR but we would like to isolate the cases
6433 // where we want to set flags from those where we don't. need to work
6434 // out how to do that.
6435 instruct addI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6436 match(Set dst (AddI src1 src2));
6437
6438 ins_cost(ALU_COST);
6439 format %{ "addw $dst, $src1, $src2\t#@addI_reg_reg" %}
6440
6441 ins_encode %{
6442 __ addw(as_Register($dst$$reg),
6443 as_Register($src1$$reg),
6444 as_Register($src2$$reg));
6445 %}
6446
6447 ins_pipe(ialu_reg_reg);
6448 %}
6449
6450 instruct addI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immIAdd src2) %{
6451 match(Set dst (AddI src1 src2));
6452
6453 ins_cost(ALU_COST);
6454 format %{ "addiw $dst, $src1, $src2\t#@addI_reg_imm" %}
6455
6456 ins_encode %{
6457 __ addiw(as_Register($dst$$reg),
6458 as_Register($src1$$reg),
6459 $src2$$constant);
6460 %}
6461
6462 ins_pipe(ialu_reg_imm);
6463 %}
6464
6465 instruct addI_reg_imm_l2i(iRegINoSp dst, iRegL src1, immIAdd src2) %{
6466 match(Set dst (AddI (ConvL2I src1) src2));
6467
6468 ins_cost(ALU_COST);
6469 format %{ "addiw $dst, $src1, $src2\t#@addI_reg_imm_l2i" %}
6470
6471 ins_encode %{
6472 __ addiw(as_Register($dst$$reg),
6473 as_Register($src1$$reg),
6474 $src2$$constant);
6475 %}
6476
6477 ins_pipe(ialu_reg_imm);
6478 %}
6479
6480 // Pointer Addition
6481 instruct addP_reg_reg(iRegPNoSp dst, iRegP src1, iRegL src2) %{
6482 match(Set dst (AddP src1 src2));
6483
6484 ins_cost(ALU_COST);
6485 format %{ "add $dst, $src1, $src2\t# ptr, #@addP_reg_reg" %}
6486
6487 ins_encode %{
6488 __ add(as_Register($dst$$reg),
6489 as_Register($src1$$reg),
6490 as_Register($src2$$reg));
6491 %}
6492
6493 ins_pipe(ialu_reg_reg);
6494 %}
6495
6496 // If we shift more than 32 bits, we need not convert I2L.
6497 instruct lShiftL_regI_immGE32(iRegLNoSp dst, iRegI src, uimmI6_ge32 scale) %{
6498 match(Set dst (LShiftL (ConvI2L src) scale));
6499 ins_cost(ALU_COST);
6500 format %{ "slli $dst, $src, $scale & 63\t#@lShiftL_regI_immGE32" %}
6501
6502 ins_encode %{
6503 __ slli(as_Register($dst$$reg), as_Register($src$$reg), $scale$$constant & 63);
6504 %}
6505
6506 ins_pipe(ialu_reg_shift);
6507 %}
6508
6509 // Pointer Immediate Addition
6510 // n.b. this needs to be more expensive than using an indirect memory
6511 // operand
6512 instruct addP_reg_imm(iRegPNoSp dst, iRegP src1, immLAdd src2) %{
6513 match(Set dst (AddP src1 src2));
6514 ins_cost(ALU_COST);
6515 format %{ "addi $dst, $src1, $src2\t# ptr, #@addP_reg_imm" %}
6516
6517 ins_encode %{
6518 __ addi(as_Register($dst$$reg),
6519 as_Register($src1$$reg),
6520 $src2$$constant);
6521 %}
6522
6523 ins_pipe(ialu_reg_imm);
6524 %}
6525
6526 // Long Addition
6527 instruct addL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
6528 match(Set dst (AddL src1 src2));
6529 ins_cost(ALU_COST);
6530 format %{ "add $dst, $src1, $src2\t#@addL_reg_reg" %}
6531
6532 ins_encode %{
6533 __ add(as_Register($dst$$reg),
6534 as_Register($src1$$reg),
6535 as_Register($src2$$reg));
6536 %}
6537
6538 ins_pipe(ialu_reg_reg);
6539 %}
6540
6541 // No constant pool entries requiredLong Immediate Addition.
6542 instruct addL_reg_imm(iRegLNoSp dst, iRegL src1, immLAdd src2) %{
6543 match(Set dst (AddL src1 src2));
6544 ins_cost(ALU_COST);
6545 format %{ "addi $dst, $src1, $src2\t#@addL_reg_imm" %}
6546
6547 ins_encode %{
6548 // src2 is imm, so actually call the addi
6549 __ addi(as_Register($dst$$reg),
6550 as_Register($src1$$reg),
6551 $src2$$constant);
6552 %}
6553
6554 ins_pipe(ialu_reg_imm);
6555 %}
6556
6557 // Integer Subtraction
6558 instruct subI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6559 match(Set dst (SubI src1 src2));
6560
6561 ins_cost(ALU_COST);
6562 format %{ "subw $dst, $src1, $src2\t#@subI_reg_reg" %}
6563
6564 ins_encode %{
6565 __ subw(as_Register($dst$$reg),
6566 as_Register($src1$$reg),
6567 as_Register($src2$$reg));
6568 %}
6569
6570 ins_pipe(ialu_reg_reg);
6571 %}
6572
6573 // Immediate Subtraction
6574 instruct subI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immISub src2) %{
6575 match(Set dst (SubI src1 src2));
6576
6577 ins_cost(ALU_COST);
6578 format %{ "addiw $dst, $src1, -$src2\t#@subI_reg_imm" %}
6579
6580 ins_encode %{
6581 // src2 is imm, so actually call the addiw
6582 __ subiw(as_Register($dst$$reg),
6583 as_Register($src1$$reg),
6584 $src2$$constant);
6585 %}
6586
6587 ins_pipe(ialu_reg_imm);
6588 %}
6589
6590 // Long Subtraction
6591 instruct subL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
6592 match(Set dst (SubL src1 src2));
6593 ins_cost(ALU_COST);
6594 format %{ "sub $dst, $src1, $src2\t#@subL_reg_reg" %}
6595
6596 ins_encode %{
6597 __ sub(as_Register($dst$$reg),
6598 as_Register($src1$$reg),
6599 as_Register($src2$$reg));
6600 %}
6601
6602 ins_pipe(ialu_reg_reg);
6603 %}
6604
6605 // No constant pool entries requiredLong Immediate Subtraction.
6606 instruct subL_reg_imm(iRegLNoSp dst, iRegL src1, immLSub src2) %{
6607 match(Set dst (SubL src1 src2));
6608 ins_cost(ALU_COST);
6609 format %{ "addi $dst, $src1, -$src2\t#@subL_reg_imm" %}
6610
6611 ins_encode %{
6612 // src2 is imm, so actually call the addi
6613 __ subi(as_Register($dst$$reg),
6614 as_Register($src1$$reg),
6615 $src2$$constant);
6616 %}
6617
6618 ins_pipe(ialu_reg_imm);
6619 %}
6620
6621 // Integer Negation (special case for sub)
6622
6623 instruct negI_reg(iRegINoSp dst, iRegIorL2I src, immI0 zero) %{
6624 match(Set dst (SubI zero src));
6625 ins_cost(ALU_COST);
6626 format %{ "subw $dst, x0, $src\t# int, #@negI_reg" %}
6627
6628 ins_encode %{
6629 // actually call the subw
6630 __ negw(as_Register($dst$$reg),
6631 as_Register($src$$reg));
6632 %}
6633
6634 ins_pipe(ialu_reg);
6635 %}
6636
6637 // Long Negation
6638
6639 instruct negL_reg(iRegLNoSp dst, iRegL src, immL0 zero) %{
6640 match(Set dst (SubL zero src));
6641 ins_cost(ALU_COST);
6642 format %{ "sub $dst, x0, $src\t# long, #@negL_reg" %}
6643
6644 ins_encode %{
6645 // actually call the sub
6646 __ neg(as_Register($dst$$reg),
6647 as_Register($src$$reg));
6648 %}
6649
6650 ins_pipe(ialu_reg);
6651 %}
6652
6653 // Integer Multiply
6654
6655 instruct mulI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6656 match(Set dst (MulI src1 src2));
6657 ins_cost(IMUL_COST);
6658 format %{ "mulw $dst, $src1, $src2\t#@mulI" %}
6659
6660 //this means 2 word multi, and no sign extend to 64 bits
6661 ins_encode %{
6662 // riscv64 mulw will sign-extension to high 32 bits in dst reg
6663 __ mulw(as_Register($dst$$reg),
6664 as_Register($src1$$reg),
6665 as_Register($src2$$reg));
6666 %}
6667
6668 ins_pipe(imul_reg_reg);
6669 %}
6670
6671 // Long Multiply
6672
6673 instruct mulL(iRegLNoSp dst, iRegL src1, iRegL src2) %{
6674 match(Set dst (MulL src1 src2));
6675 ins_cost(IMUL_COST);
6676 format %{ "mul $dst, $src1, $src2\t#@mulL" %}
6677
6678 ins_encode %{
6679 __ mul(as_Register($dst$$reg),
6680 as_Register($src1$$reg),
6681 as_Register($src2$$reg));
6682 %}
6683
6684 ins_pipe(lmul_reg_reg);
6685 %}
6686
6687 instruct mulHiL_rReg(iRegLNoSp dst, iRegL src1, iRegL src2)
6688 %{
6689 match(Set dst (MulHiL src1 src2));
6690 ins_cost(IMUL_COST);
6691 format %{ "mulh $dst, $src1, $src2\t# mulhi, #@mulHiL_rReg" %}
6692
6693 ins_encode %{
6694 __ mulh(as_Register($dst$$reg),
6695 as_Register($src1$$reg),
6696 as_Register($src2$$reg));
6697 %}
6698
6699 ins_pipe(lmul_reg_reg);
6700 %}
6701
6702 instruct umulHiL_rReg(iRegLNoSp dst, iRegL src1, iRegL src2)
6703 %{
6704 match(Set dst (UMulHiL src1 src2));
6705 ins_cost(IMUL_COST);
6706 format %{ "mulhu $dst, $src1, $src2\t# umulhi, #@umulHiL_rReg" %}
6707
6708 ins_encode %{
6709 __ mulhu(as_Register($dst$$reg),
6710 as_Register($src1$$reg),
6711 as_Register($src2$$reg));
6712 %}
6713
6714 ins_pipe(lmul_reg_reg);
6715 %}
6716
6717 // Integer Divide
6718
6719 instruct divI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6720 match(Set dst (DivI src1 src2));
6721 ins_cost(IDIVSI_COST);
6722 format %{ "divw $dst, $src1, $src2\t#@divI"%}
6723
6724 ins_encode %{
6725 __ divw(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg));
6726 %}
6727 ins_pipe(idiv_reg_reg);
6728 %}
6729
6730 instruct UdivI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6731 match(Set dst (UDivI src1 src2));
6732 ins_cost(IDIVSI_COST);
6733 format %{ "divuw $dst, $src1, $src2\t#@UdivI"%}
6734
6735 ins_encode %{
6736 __ divuw(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg));
6737 %}
6738 ins_pipe(idiv_reg_reg);
6739 %}
6740
6741 instruct signExtract(iRegINoSp dst, iRegIorL2I src1, immI_31 div1, immI_31 div2) %{
6742 match(Set dst (URShiftI (RShiftI src1 div1) div2));
6743 ins_cost(ALU_COST);
6744 format %{ "srliw $dst, $src1, $div1\t# int signExtract, #@signExtract" %}
6745
6746 ins_encode %{
6747 __ srliw(as_Register($dst$$reg), as_Register($src1$$reg), 31);
6748 %}
6749 ins_pipe(ialu_reg_shift);
6750 %}
6751
6752 // Long Divide
6753
6754 instruct divL(iRegLNoSp dst, iRegL src1, iRegL src2) %{
6755 match(Set dst (DivL src1 src2));
6756 ins_cost(IDIVDI_COST);
6757 format %{ "div $dst, $src1, $src2\t#@divL" %}
6758
6759 ins_encode %{
6760 __ div(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg));
6761 %}
6762 ins_pipe(ldiv_reg_reg);
6763 %}
6764
6765 instruct UdivL(iRegLNoSp dst, iRegL src1, iRegL src2) %{
6766 match(Set dst (UDivL src1 src2));
6767 ins_cost(IDIVDI_COST);
6768
6769 format %{ "divu $dst, $src1, $src2\t#@UdivL" %}
6770
6771 ins_encode %{
6772 __ divu(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg));
6773 %}
6774 ins_pipe(ldiv_reg_reg);
6775 %}
6776
6777 instruct signExtractL(iRegLNoSp dst, iRegL src1, immI_63 div1, immI_63 div2) %{
6778 match(Set dst (URShiftL (RShiftL src1 div1) div2));
6779 ins_cost(ALU_COST);
6780 format %{ "srli $dst, $src1, $div1\t# long signExtract, #@signExtractL" %}
6781
6782 ins_encode %{
6783 __ srli(as_Register($dst$$reg), as_Register($src1$$reg), 63);
6784 %}
6785 ins_pipe(ialu_reg_shift);
6786 %}
6787
6788 // Integer Remainder
6789
6790 instruct modI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6791 match(Set dst (ModI src1 src2));
6792 ins_cost(IDIVSI_COST);
6793 format %{ "remw $dst, $src1, $src2\t#@modI" %}
6794
6795 ins_encode %{
6796 __ remw(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg));
6797 %}
6798 ins_pipe(ialu_reg_reg);
6799 %}
6800
6801 instruct UmodI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6802 match(Set dst (UModI src1 src2));
6803 ins_cost(IDIVSI_COST);
6804 format %{ "remuw $dst, $src1, $src2\t#@UmodI" %}
6805
6806 ins_encode %{
6807 __ remuw(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg));
6808 %}
6809 ins_pipe(ialu_reg_reg);
6810 %}
6811
6812 // Long Remainder
6813
6814 instruct modL(iRegLNoSp dst, iRegL src1, iRegL src2) %{
6815 match(Set dst (ModL src1 src2));
6816 ins_cost(IDIVDI_COST);
6817 format %{ "rem $dst, $src1, $src2\t#@modL" %}
6818
6819 ins_encode %{
6820 __ rem(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg));
6821 %}
6822 ins_pipe(ialu_reg_reg);
6823 %}
6824
6825 instruct UmodL(iRegLNoSp dst, iRegL src1, iRegL src2) %{
6826 match(Set dst (UModL src1 src2));
6827 ins_cost(IDIVDI_COST);
6828 format %{ "remu $dst, $src1, $src2\t#@UmodL" %}
6829
6830 ins_encode %{
6831 __ remu(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg));
6832 %}
6833 ins_pipe(ialu_reg_reg);
6834 %}
6835
6836 // Integer Shifts
6837
6838 // Shift Left Register
6839 // Only the low 5 bits of src2 are considered for the shift amount, all other bits are ignored.
6840 instruct lShiftI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6841 match(Set dst (LShiftI src1 src2));
6842 ins_cost(ALU_COST);
6843 format %{ "sllw $dst, $src1, $src2\t#@lShiftI_reg_reg" %}
6844
6845 ins_encode %{
6846 __ sllw(as_Register($dst$$reg),
6847 as_Register($src1$$reg),
6848 as_Register($src2$$reg));
6849 %}
6850
6851 ins_pipe(ialu_reg_reg_vshift);
6852 %}
6853
6854 // Shift Left Immediate
6855 instruct lShiftI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immI src2) %{
6856 match(Set dst (LShiftI src1 src2));
6857 ins_cost(ALU_COST);
6858 format %{ "slliw $dst, $src1, ($src2 & 0x1f)\t#@lShiftI_reg_imm" %}
6859
6860 ins_encode %{
6861 // the shift amount is encoded in the lower
6862 // 5 bits of the I-immediate field for RV32I
6863 __ slliw(as_Register($dst$$reg),
6864 as_Register($src1$$reg),
6865 (unsigned) $src2$$constant & 0x1f);
6866 %}
6867
6868 ins_pipe(ialu_reg_shift);
6869 %}
6870
6871 // Shift Right Logical Register
6872 // Only the low 5 bits of src2 are considered for the shift amount, all other bits are ignored.
6873 instruct urShiftI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6874 match(Set dst (URShiftI src1 src2));
6875 ins_cost(ALU_COST);
6876 format %{ "srlw $dst, $src1, $src2\t#@urShiftI_reg_reg" %}
6877
6878 ins_encode %{
6879 __ srlw(as_Register($dst$$reg),
6880 as_Register($src1$$reg),
6881 as_Register($src2$$reg));
6882 %}
6883
6884 ins_pipe(ialu_reg_reg_vshift);
6885 %}
6886
6887 // Shift Right Logical Immediate
6888 instruct urShiftI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immI src2) %{
6889 match(Set dst (URShiftI src1 src2));
6890 ins_cost(ALU_COST);
6891 format %{ "srliw $dst, $src1, ($src2 & 0x1f)\t#@urShiftI_reg_imm" %}
6892
6893 ins_encode %{
6894 // the shift amount is encoded in the lower
6895 // 6 bits of the I-immediate field for RV64I
6896 __ srliw(as_Register($dst$$reg),
6897 as_Register($src1$$reg),
6898 (unsigned) $src2$$constant & 0x1f);
6899 %}
6900
6901 ins_pipe(ialu_reg_shift);
6902 %}
6903
6904 // Shift Right Arithmetic Register
6905 // Only the low 5 bits of src2 are considered for the shift amount, all other bits are ignored.
6906 instruct rShiftI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6907 match(Set dst (RShiftI src1 src2));
6908 ins_cost(ALU_COST);
6909 format %{ "sraw $dst, $src1, $src2\t#@rShiftI_reg_reg" %}
6910
6911 ins_encode %{
6912 // riscv will sign-ext dst high 32 bits
6913 __ sraw(as_Register($dst$$reg),
6914 as_Register($src1$$reg),
6915 as_Register($src2$$reg));
6916 %}
6917
6918 ins_pipe(ialu_reg_reg_vshift);
6919 %}
6920
6921 // Shift Right Arithmetic Immediate
6922 instruct rShiftI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immI src2) %{
6923 match(Set dst (RShiftI src1 src2));
6924 ins_cost(ALU_COST);
6925 format %{ "sraiw $dst, $src1, ($src2 & 0x1f)\t#@rShiftI_reg_imm" %}
6926
6927 ins_encode %{
6928 // riscv will sign-ext dst high 32 bits
6929 __ sraiw(as_Register($dst$$reg),
6930 as_Register($src1$$reg),
6931 (unsigned) $src2$$constant & 0x1f);
6932 %}
6933
6934 ins_pipe(ialu_reg_shift);
6935 %}
6936
6937 // Long Shifts
6938
6939 // Shift Left Register
6940 // Only the low 6 bits of src2 are considered for the shift amount, all other bits are ignored.
6941 instruct lShiftL_reg_reg(iRegLNoSp dst, iRegL src1, iRegIorL2I src2) %{
6942 match(Set dst (LShiftL src1 src2));
6943
6944 ins_cost(ALU_COST);
6945 format %{ "sll $dst, $src1, $src2\t#@lShiftL_reg_reg" %}
6946
6947 ins_encode %{
6948 __ sll(as_Register($dst$$reg),
6949 as_Register($src1$$reg),
6950 as_Register($src2$$reg));
6951 %}
6952
6953 ins_pipe(ialu_reg_reg_vshift);
6954 %}
6955
6956 // Shift Left Immediate
6957 instruct lShiftL_reg_imm(iRegLNoSp dst, iRegL src1, immI src2) %{
6958 match(Set dst (LShiftL src1 src2));
6959
6960 ins_cost(ALU_COST);
6961 format %{ "slli $dst, $src1, ($src2 & 0x3f)\t#@lShiftL_reg_imm" %}
6962
6963 ins_encode %{
6964 // the shift amount is encoded in the lower
6965 // 6 bits of the I-immediate field for RV64I
6966 __ slli(as_Register($dst$$reg),
6967 as_Register($src1$$reg),
6968 (unsigned) $src2$$constant & 0x3f);
6969 %}
6970
6971 ins_pipe(ialu_reg_shift);
6972 %}
6973
6974 // Shift Right Logical Register
6975 // Only the low 6 bits of src2 are considered for the shift amount, all other bits are ignored.
6976 instruct urShiftL_reg_reg(iRegLNoSp dst, iRegL src1, iRegIorL2I src2) %{
6977 match(Set dst (URShiftL src1 src2));
6978
6979 ins_cost(ALU_COST);
6980 format %{ "srl $dst, $src1, $src2\t#@urShiftL_reg_reg" %}
6981
6982 ins_encode %{
6983 __ srl(as_Register($dst$$reg),
6984 as_Register($src1$$reg),
6985 as_Register($src2$$reg));
6986 %}
6987
6988 ins_pipe(ialu_reg_reg_vshift);
6989 %}
6990
6991 // Shift Right Logical Immediate
6992 instruct urShiftL_reg_imm(iRegLNoSp dst, iRegL src1, immI src2) %{
6993 match(Set dst (URShiftL src1 src2));
6994
6995 ins_cost(ALU_COST);
6996 format %{ "srli $dst, $src1, ($src2 & 0x3f)\t#@urShiftL_reg_imm" %}
6997
6998 ins_encode %{
6999 // the shift amount is encoded in the lower
7000 // 6 bits of the I-immediate field for RV64I
7001 __ srli(as_Register($dst$$reg),
7002 as_Register($src1$$reg),
7003 (unsigned) $src2$$constant & 0x3f);
7004 %}
7005
7006 ins_pipe(ialu_reg_shift);
7007 %}
7008
7009 // A special-case pattern for card table stores.
7010 instruct urShiftP_reg_imm(iRegLNoSp dst, iRegP src1, immI src2) %{
7011 match(Set dst (URShiftL (CastP2X src1) src2));
7012
7013 ins_cost(ALU_COST);
7014 format %{ "srli $dst, p2x($src1), ($src2 & 0x3f)\t#@urShiftP_reg_imm" %}
7015
7016 ins_encode %{
7017 // the shift amount is encoded in the lower
7018 // 6 bits of the I-immediate field for RV64I
7019 __ srli(as_Register($dst$$reg),
7020 as_Register($src1$$reg),
7021 (unsigned) $src2$$constant & 0x3f);
7022 %}
7023
7024 ins_pipe(ialu_reg_shift);
7025 %}
7026
7027 // Shift Right Arithmetic Register
7028 // Only the low 6 bits of src2 are considered for the shift amount, all other bits are ignored.
7029 instruct rShiftL_reg_reg(iRegLNoSp dst, iRegL src1, iRegIorL2I src2) %{
7030 match(Set dst (RShiftL src1 src2));
7031
7032 ins_cost(ALU_COST);
7033 format %{ "sra $dst, $src1, $src2\t#@rShiftL_reg_reg" %}
7034
7035 ins_encode %{
7036 __ sra(as_Register($dst$$reg),
7037 as_Register($src1$$reg),
7038 as_Register($src2$$reg));
7039 %}
7040
7041 ins_pipe(ialu_reg_reg_vshift);
7042 %}
7043
7044 // Shift Right Arithmetic Immediate
7045 instruct rShiftL_reg_imm(iRegLNoSp dst, iRegL src1, immI src2) %{
7046 match(Set dst (RShiftL src1 src2));
7047
7048 ins_cost(ALU_COST);
7049 format %{ "srai $dst, $src1, ($src2 & 0x3f)\t#@rShiftL_reg_imm" %}
7050
7051 ins_encode %{
7052 // the shift amount is encoded in the lower
7053 // 6 bits of the I-immediate field for RV64I
7054 __ srai(as_Register($dst$$reg),
7055 as_Register($src1$$reg),
7056 (unsigned) $src2$$constant & 0x3f);
7057 %}
7058
7059 ins_pipe(ialu_reg_shift);
7060 %}
7061
7062 instruct regI_not_reg(iRegINoSp dst, iRegI src1, immI_M1 m1) %{
7063 match(Set dst (XorI src1 m1));
7064 ins_cost(ALU_COST);
7065 format %{ "xori $dst, $src1, -1\t#@regI_not_reg" %}
7066
7067 ins_encode %{
7068 __ xori(as_Register($dst$$reg), as_Register($src1$$reg), -1);
7069 %}
7070
7071 ins_pipe(ialu_reg_imm);
7072 %}
7073
7074 instruct regL_not_reg(iRegLNoSp dst, iRegL src1, immL_M1 m1) %{
7075 match(Set dst (XorL src1 m1));
7076 ins_cost(ALU_COST);
7077 format %{ "xori $dst, $src1, -1\t#@regL_not_reg" %}
7078
7079 ins_encode %{
7080 __ xori(as_Register($dst$$reg), as_Register($src1$$reg), -1);
7081 %}
7082
7083 ins_pipe(ialu_reg_imm);
7084 %}
7085
7086
7087 // ============================================================================
7088 // Floating Point Arithmetic Instructions
7089
7090 instruct addF_reg_reg(fRegF dst, fRegF src1, fRegF src2) %{
7091 match(Set dst (AddF src1 src2));
7092
7093 ins_cost(DEFAULT_COST * 5);
7094 format %{ "fadd.s $dst, $src1, $src2\t#@addF_reg_reg" %}
7095
7096 ins_encode %{
7097 __ fadd_s(as_FloatRegister($dst$$reg),
7098 as_FloatRegister($src1$$reg),
7099 as_FloatRegister($src2$$reg));
7100 %}
7101
7102 ins_pipe(fp_dop_reg_reg_s);
7103 %}
7104
7105 instruct addD_reg_reg(fRegD dst, fRegD src1, fRegD src2) %{
7106 match(Set dst (AddD src1 src2));
7107
7108 ins_cost(DEFAULT_COST * 5);
7109 format %{ "fadd.d $dst, $src1, $src2\t#@addD_reg_reg" %}
7110
7111 ins_encode %{
7112 __ fadd_d(as_FloatRegister($dst$$reg),
7113 as_FloatRegister($src1$$reg),
7114 as_FloatRegister($src2$$reg));
7115 %}
7116
7117 ins_pipe(fp_dop_reg_reg_d);
7118 %}
7119
7120 instruct subF_reg_reg(fRegF dst, fRegF src1, fRegF src2) %{
7121 match(Set dst (SubF src1 src2));
7122
7123 ins_cost(DEFAULT_COST * 5);
7124 format %{ "fsub.s $dst, $src1, $src2\t#@subF_reg_reg" %}
7125
7126 ins_encode %{
7127 __ fsub_s(as_FloatRegister($dst$$reg),
7128 as_FloatRegister($src1$$reg),
7129 as_FloatRegister($src2$$reg));
7130 %}
7131
7132 ins_pipe(fp_dop_reg_reg_s);
7133 %}
7134
7135 instruct subD_reg_reg(fRegD dst, fRegD src1, fRegD src2) %{
7136 match(Set dst (SubD src1 src2));
7137
7138 ins_cost(DEFAULT_COST * 5);
7139 format %{ "fsub.d $dst, $src1, $src2\t#@subD_reg_reg" %}
7140
7141 ins_encode %{
7142 __ fsub_d(as_FloatRegister($dst$$reg),
7143 as_FloatRegister($src1$$reg),
7144 as_FloatRegister($src2$$reg));
7145 %}
7146
7147 ins_pipe(fp_dop_reg_reg_d);
7148 %}
7149
7150 instruct mulF_reg_reg(fRegF dst, fRegF src1, fRegF src2) %{
7151 match(Set dst (MulF src1 src2));
7152
7153 ins_cost(FMUL_SINGLE_COST);
7154 format %{ "fmul.s $dst, $src1, $src2\t#@mulF_reg_reg" %}
7155
7156 ins_encode %{
7157 __ fmul_s(as_FloatRegister($dst$$reg),
7158 as_FloatRegister($src1$$reg),
7159 as_FloatRegister($src2$$reg));
7160 %}
7161
7162 ins_pipe(fp_dop_reg_reg_s);
7163 %}
7164
7165 instruct mulD_reg_reg(fRegD dst, fRegD src1, fRegD src2) %{
7166 match(Set dst (MulD src1 src2));
7167
7168 ins_cost(FMUL_DOUBLE_COST);
7169 format %{ "fmul.d $dst, $src1, $src2\t#@mulD_reg_reg" %}
7170
7171 ins_encode %{
7172 __ fmul_d(as_FloatRegister($dst$$reg),
7173 as_FloatRegister($src1$$reg),
7174 as_FloatRegister($src2$$reg));
7175 %}
7176
7177 ins_pipe(fp_dop_reg_reg_d);
7178 %}
7179
7180 // src1 * src2 + src3
7181 instruct maddF_reg_reg(fRegF dst, fRegF src1, fRegF src2, fRegF src3) %{
7182 match(Set dst (FmaF src3 (Binary src1 src2)));
7183
7184 ins_cost(FMUL_SINGLE_COST);
7185 format %{ "fmadd.s $dst, $src1, $src2, $src3\t#@maddF_reg_reg" %}
7186
7187 ins_encode %{
7188 assert(UseFMA, "Needs FMA instructions support.");
7189 __ fmadd_s(as_FloatRegister($dst$$reg),
7190 as_FloatRegister($src1$$reg),
7191 as_FloatRegister($src2$$reg),
7192 as_FloatRegister($src3$$reg));
7193 %}
7194
7195 ins_pipe(pipe_class_default);
7196 %}
7197
7198 // src1 * src2 + src3
7199 instruct maddD_reg_reg(fRegD dst, fRegD src1, fRegD src2, fRegD src3) %{
7200 match(Set dst (FmaD src3 (Binary src1 src2)));
7201
7202 ins_cost(FMUL_DOUBLE_COST);
7203 format %{ "fmadd.d $dst, $src1, $src2, $src3\t#@maddD_reg_reg" %}
7204
7205 ins_encode %{
7206 assert(UseFMA, "Needs FMA instructions support.");
7207 __ fmadd_d(as_FloatRegister($dst$$reg),
7208 as_FloatRegister($src1$$reg),
7209 as_FloatRegister($src2$$reg),
7210 as_FloatRegister($src3$$reg));
7211 %}
7212
7213 ins_pipe(pipe_class_default);
7214 %}
7215
7216 // src1 * src2 - src3
7217 instruct msubF_reg_reg(fRegF dst, fRegF src1, fRegF src2, fRegF src3) %{
7218 match(Set dst (FmaF (NegF src3) (Binary src1 src2)));
7219
7220 ins_cost(FMUL_SINGLE_COST);
7221 format %{ "fmsub.s $dst, $src1, $src2, $src3\t#@msubF_reg_reg" %}
7222
7223 ins_encode %{
7224 assert(UseFMA, "Needs FMA instructions support.");
7225 __ fmsub_s(as_FloatRegister($dst$$reg),
7226 as_FloatRegister($src1$$reg),
7227 as_FloatRegister($src2$$reg),
7228 as_FloatRegister($src3$$reg));
7229 %}
7230
7231 ins_pipe(pipe_class_default);
7232 %}
7233
7234 // src1 * src2 - src3
7235 instruct msubD_reg_reg(fRegD dst, fRegD src1, fRegD src2, fRegD src3) %{
7236 match(Set dst (FmaD (NegD src3) (Binary src1 src2)));
7237
7238 ins_cost(FMUL_DOUBLE_COST);
7239 format %{ "fmsub.d $dst, $src1, $src2, $src3\t#@msubD_reg_reg" %}
7240
7241 ins_encode %{
7242 assert(UseFMA, "Needs FMA instructions support.");
7243 __ fmsub_d(as_FloatRegister($dst$$reg),
7244 as_FloatRegister($src1$$reg),
7245 as_FloatRegister($src2$$reg),
7246 as_FloatRegister($src3$$reg));
7247 %}
7248
7249 ins_pipe(pipe_class_default);
7250 %}
7251
7252 // src1 * (-src2) + src3
7253 // "(-src1) * src2 + src3" has been idealized to "src2 * (-src1) + src3"
7254 instruct nmsubF_reg_reg(fRegF dst, fRegF src1, fRegF src2, fRegF src3) %{
7255 match(Set dst (FmaF src3 (Binary src1 (NegF src2))));
7256
7257 ins_cost(FMUL_SINGLE_COST);
7258 format %{ "fnmsub.s $dst, $src1, $src2, $src3\t#@nmsubF_reg_reg" %}
7259
7260 ins_encode %{
7261 assert(UseFMA, "Needs FMA instructions support.");
7262 __ fnmsub_s(as_FloatRegister($dst$$reg),
7263 as_FloatRegister($src1$$reg),
7264 as_FloatRegister($src2$$reg),
7265 as_FloatRegister($src3$$reg));
7266 %}
7267
7268 ins_pipe(pipe_class_default);
7269 %}
7270
7271 // src1 * (-src2) + src3
7272 // "(-src1) * src2 + src3" has been idealized to "src2 * (-src1) + src3"
7273 instruct nmsubD_reg_reg(fRegD dst, fRegD src1, fRegD src2, fRegD src3) %{
7274 match(Set dst (FmaD src3 (Binary src1 (NegD src2))));
7275
7276 ins_cost(FMUL_DOUBLE_COST);
7277 format %{ "fnmsub.d $dst, $src1, $src2, $src3\t#@nmsubD_reg_reg" %}
7278
7279 ins_encode %{
7280 assert(UseFMA, "Needs FMA instructions support.");
7281 __ fnmsub_d(as_FloatRegister($dst$$reg),
7282 as_FloatRegister($src1$$reg),
7283 as_FloatRegister($src2$$reg),
7284 as_FloatRegister($src3$$reg));
7285 %}
7286
7287 ins_pipe(pipe_class_default);
7288 %}
7289
7290 // src1 * (-src2) - src3
7291 // "(-src1) * src2 - src3" has been idealized to "src2 * (-src1) - src3"
7292 instruct nmaddF_reg_reg(fRegF dst, fRegF src1, fRegF src2, fRegF src3) %{
7293 match(Set dst (FmaF (NegF src3) (Binary src1 (NegF src2))));
7294
7295 ins_cost(FMUL_SINGLE_COST);
7296 format %{ "fnmadd.s $dst, $src1, $src2, $src3\t#@nmaddF_reg_reg" %}
7297
7298 ins_encode %{
7299 assert(UseFMA, "Needs FMA instructions support.");
7300 __ fnmadd_s(as_FloatRegister($dst$$reg),
7301 as_FloatRegister($src1$$reg),
7302 as_FloatRegister($src2$$reg),
7303 as_FloatRegister($src3$$reg));
7304 %}
7305
7306 ins_pipe(pipe_class_default);
7307 %}
7308
7309 // src1 * (-src2) - src3
7310 // "(-src1) * src2 - src3" has been idealized to "src2 * (-src1) - src3"
7311 instruct nmaddD_reg_reg(fRegD dst, fRegD src1, fRegD src2, fRegD src3) %{
7312 match(Set dst (FmaD (NegD src3) (Binary src1 (NegD src2))));
7313
7314 ins_cost(FMUL_DOUBLE_COST);
7315 format %{ "fnmadd.d $dst, $src1, $src2, $src3\t#@nmaddD_reg_reg" %}
7316
7317 ins_encode %{
7318 assert(UseFMA, "Needs FMA instructions support.");
7319 __ fnmadd_d(as_FloatRegister($dst$$reg),
7320 as_FloatRegister($src1$$reg),
7321 as_FloatRegister($src2$$reg),
7322 as_FloatRegister($src3$$reg));
7323 %}
7324
7325 ins_pipe(pipe_class_default);
7326 %}
7327
7328 // Math.max(FF)F
7329 instruct maxF_reg_reg(fRegF dst, fRegF src1, fRegF src2, rFlagsReg cr) %{
7330 predicate(!UseZfa);
7331 match(Set dst (MaxF src1 src2));
7332 effect(KILL cr);
7333
7334 format %{ "maxF $dst, $src1, $src2" %}
7335
7336 ins_encode %{
7337 __ minmax_fp(as_FloatRegister($dst$$reg),
7338 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg),
7339 __ FLOAT_TYPE::single_precision, false /* is_min */);
7340 %}
7341
7342 ins_pipe(pipe_class_default);
7343 %}
7344
7345 instruct maxF_reg_reg_zfa(fRegF dst, fRegF src1, fRegF src2) %{
7346 predicate(UseZfa);
7347 match(Set dst (MaxF src1 src2));
7348
7349 format %{ "maxF $dst, $src1, $src2" %}
7350
7351 ins_encode %{
7352 __ fmaxm_s(as_FloatRegister($dst$$reg),
7353 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
7354 %}
7355
7356 ins_pipe(pipe_class_default);
7357 %}
7358
7359 // Math.min(FF)F
7360 instruct minF_reg_reg(fRegF dst, fRegF src1, fRegF src2, rFlagsReg cr) %{
7361 predicate(!UseZfa);
7362 match(Set dst (MinF src1 src2));
7363 effect(KILL cr);
7364
7365 format %{ "minF $dst, $src1, $src2" %}
7366
7367 ins_encode %{
7368 __ minmax_fp(as_FloatRegister($dst$$reg),
7369 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg),
7370 __ FLOAT_TYPE::single_precision, true /* is_min */);
7371 %}
7372
7373 ins_pipe(pipe_class_default);
7374 %}
7375
7376 instruct minF_reg_reg_zfa(fRegF dst, fRegF src1, fRegF src2) %{
7377 predicate(UseZfa);
7378 match(Set dst (MinF src1 src2));
7379
7380 format %{ "minF $dst, $src1, $src2" %}
7381
7382 ins_encode %{
7383 __ fminm_s(as_FloatRegister($dst$$reg),
7384 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
7385 %}
7386
7387 ins_pipe(pipe_class_default);
7388 %}
7389
7390 // Math.max(DD)D
7391 instruct maxD_reg_reg(fRegD dst, fRegD src1, fRegD src2, rFlagsReg cr) %{
7392 predicate(!UseZfa);
7393 match(Set dst (MaxD src1 src2));
7394 effect(KILL cr);
7395
7396 format %{ "maxD $dst, $src1, $src2" %}
7397
7398 ins_encode %{
7399 __ minmax_fp(as_FloatRegister($dst$$reg),
7400 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg),
7401 __ FLOAT_TYPE::double_precision, false /* is_min */);
7402 %}
7403
7404 ins_pipe(pipe_class_default);
7405 %}
7406
7407 instruct maxD_reg_reg_zfa(fRegD dst, fRegD src1, fRegD src2) %{
7408 predicate(UseZfa);
7409 match(Set dst (MaxD src1 src2));
7410
7411 format %{ "maxD $dst, $src1, $src2" %}
7412
7413 ins_encode %{
7414 __ fmaxm_d(as_FloatRegister($dst$$reg),
7415 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
7416 %}
7417
7418 ins_pipe(pipe_class_default);
7419 %}
7420
7421 // Math.min(DD)D
7422 instruct minD_reg_reg(fRegD dst, fRegD src1, fRegD src2, rFlagsReg cr) %{
7423 predicate(!UseZfa);
7424 match(Set dst (MinD src1 src2));
7425 effect(KILL cr);
7426
7427 format %{ "minD $dst, $src1, $src2" %}
7428
7429 ins_encode %{
7430 __ minmax_fp(as_FloatRegister($dst$$reg),
7431 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg),
7432 __ FLOAT_TYPE::double_precision, true /* is_min */);
7433 %}
7434
7435 ins_pipe(pipe_class_default);
7436 %}
7437
7438 instruct minD_reg_reg_zfa(fRegD dst, fRegD src1, fRegD src2) %{
7439 predicate(UseZfa);
7440 match(Set dst (MinD src1 src2));
7441
7442 format %{ "minD $dst, $src1, $src2" %}
7443
7444 ins_encode %{
7445 __ fminm_d(as_FloatRegister($dst$$reg),
7446 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
7447 %}
7448
7449 ins_pipe(pipe_class_default);
7450 %}
7451
7452 // Float.isInfinite
7453 instruct isInfiniteF_reg_reg(iRegINoSp dst, fRegF src)
7454 %{
7455 match(Set dst (IsInfiniteF src));
7456
7457 format %{ "isInfinite $dst, $src" %}
7458 ins_encode %{
7459 __ fclass_s(as_Register($dst$$reg), as_FloatRegister($src$$reg));
7460 __ andi(as_Register($dst$$reg), as_Register($dst$$reg), Assembler::FClassBits::inf);
7461 __ slt(as_Register($dst$$reg), zr, as_Register($dst$$reg));
7462 %}
7463
7464 ins_pipe(pipe_class_default);
7465 %}
7466
7467 // Double.isInfinite
7468 instruct isInfiniteD_reg_reg(iRegINoSp dst, fRegD src)
7469 %{
7470 match(Set dst (IsInfiniteD src));
7471
7472 format %{ "isInfinite $dst, $src" %}
7473 ins_encode %{
7474 __ fclass_d(as_Register($dst$$reg), as_FloatRegister($src$$reg));
7475 __ andi(as_Register($dst$$reg), as_Register($dst$$reg), Assembler::FClassBits::inf);
7476 __ slt(as_Register($dst$$reg), zr, as_Register($dst$$reg));
7477 %}
7478
7479 ins_pipe(pipe_class_default);
7480 %}
7481
7482 // Float.isFinite
7483 instruct isFiniteF_reg_reg(iRegINoSp dst, fRegF src)
7484 %{
7485 match(Set dst (IsFiniteF src));
7486
7487 format %{ "isFinite $dst, $src" %}
7488 ins_encode %{
7489 __ fclass_s(as_Register($dst$$reg), as_FloatRegister($src$$reg));
7490 __ andi(as_Register($dst$$reg), as_Register($dst$$reg), Assembler::FClassBits::finite);
7491 __ slt(as_Register($dst$$reg), zr, as_Register($dst$$reg));
7492 %}
7493
7494 ins_pipe(pipe_class_default);
7495 %}
7496
7497 // Double.isFinite
7498 instruct isFiniteD_reg_reg(iRegINoSp dst, fRegD src)
7499 %{
7500 match(Set dst (IsFiniteD src));
7501
7502 format %{ "isFinite $dst, $src" %}
7503 ins_encode %{
7504 __ fclass_d(as_Register($dst$$reg), as_FloatRegister($src$$reg));
7505 __ andi(as_Register($dst$$reg), as_Register($dst$$reg), Assembler::FClassBits::finite);
7506 __ slt(as_Register($dst$$reg), zr, as_Register($dst$$reg));
7507 %}
7508
7509 ins_pipe(pipe_class_default);
7510 %}
7511
7512 instruct divF_reg_reg(fRegF dst, fRegF src1, fRegF src2) %{
7513 match(Set dst (DivF src1 src2));
7514
7515 ins_cost(FDIV_COST);
7516 format %{ "fdiv.s $dst, $src1, $src2\t#@divF_reg_reg" %}
7517
7518 ins_encode %{
7519 __ fdiv_s(as_FloatRegister($dst$$reg),
7520 as_FloatRegister($src1$$reg),
7521 as_FloatRegister($src2$$reg));
7522 %}
7523
7524 ins_pipe(fp_div_s);
7525 %}
7526
7527 instruct divD_reg_reg(fRegD dst, fRegD src1, fRegD src2) %{
7528 match(Set dst (DivD src1 src2));
7529
7530 ins_cost(FDIV_COST);
7531 format %{ "fdiv.d $dst, $src1, $src2\t#@divD_reg_reg" %}
7532
7533 ins_encode %{
7534 __ fdiv_d(as_FloatRegister($dst$$reg),
7535 as_FloatRegister($src1$$reg),
7536 as_FloatRegister($src2$$reg));
7537 %}
7538
7539 ins_pipe(fp_div_d);
7540 %}
7541
7542 instruct negF_reg_reg(fRegF dst, fRegF src) %{
7543 match(Set dst (NegF src));
7544
7545 ins_cost(XFER_COST);
7546 format %{ "fsgnjn.s $dst, $src, $src\t#@negF_reg_reg" %}
7547
7548 ins_encode %{
7549 __ fneg_s(as_FloatRegister($dst$$reg),
7550 as_FloatRegister($src$$reg));
7551 %}
7552
7553 ins_pipe(fp_uop_s);
7554 %}
7555
7556 instruct negD_reg_reg(fRegD dst, fRegD src) %{
7557 match(Set dst (NegD src));
7558
7559 ins_cost(XFER_COST);
7560 format %{ "fsgnjn.d $dst, $src, $src\t#@negD_reg_reg" %}
7561
7562 ins_encode %{
7563 __ fneg_d(as_FloatRegister($dst$$reg),
7564 as_FloatRegister($src$$reg));
7565 %}
7566
7567 ins_pipe(fp_uop_d);
7568 %}
7569
7570 instruct absI_reg(iRegINoSp dst, iRegIorL2I src) %{
7571 match(Set dst (AbsI src));
7572
7573 ins_cost(ALU_COST * 3);
7574 format %{
7575 "sraiw t0, $src, 0x1f\n\t"
7576 "addw $dst, $src, t0\n\t"
7577 "xorr $dst, $dst, t0\t#@absI_reg"
7578 %}
7579
7580 ins_encode %{
7581 __ sraiw(t0, as_Register($src$$reg), 0x1f);
7582 __ addw(as_Register($dst$$reg), as_Register($src$$reg), t0);
7583 __ xorr(as_Register($dst$$reg), as_Register($dst$$reg), t0);
7584 %}
7585
7586 ins_pipe(pipe_class_default);
7587 %}
7588
7589 instruct absL_reg(iRegLNoSp dst, iRegL src) %{
7590 match(Set dst (AbsL src));
7591
7592 ins_cost(ALU_COST * 3);
7593 format %{
7594 "srai t0, $src, 0x3f\n\t"
7595 "add $dst, $src, t0\n\t"
7596 "xorr $dst, $dst, t0\t#@absL_reg"
7597 %}
7598
7599 ins_encode %{
7600 __ srai(t0, as_Register($src$$reg), 0x3f);
7601 __ add(as_Register($dst$$reg), as_Register($src$$reg), t0);
7602 __ xorr(as_Register($dst$$reg), as_Register($dst$$reg), t0);
7603 %}
7604
7605 ins_pipe(pipe_class_default);
7606 %}
7607
7608 instruct absF_reg(fRegF dst, fRegF src) %{
7609 match(Set dst (AbsF src));
7610
7611 ins_cost(XFER_COST);
7612 format %{ "fsgnjx.s $dst, $src, $src\t#@absF_reg" %}
7613 ins_encode %{
7614 __ fabs_s(as_FloatRegister($dst$$reg),
7615 as_FloatRegister($src$$reg));
7616 %}
7617
7618 ins_pipe(fp_uop_s);
7619 %}
7620
7621 instruct absD_reg(fRegD dst, fRegD src) %{
7622 match(Set dst (AbsD src));
7623
7624 ins_cost(XFER_COST);
7625 format %{ "fsgnjx.d $dst, $src, $src\t#@absD_reg" %}
7626 ins_encode %{
7627 __ fabs_d(as_FloatRegister($dst$$reg),
7628 as_FloatRegister($src$$reg));
7629 %}
7630
7631 ins_pipe(fp_uop_d);
7632 %}
7633
7634 instruct sqrtF_reg(fRegF dst, fRegF src) %{
7635 match(Set dst (SqrtF src));
7636
7637 ins_cost(FSQRT_COST);
7638 format %{ "fsqrt.s $dst, $src\t#@sqrtF_reg" %}
7639 ins_encode %{
7640 __ fsqrt_s(as_FloatRegister($dst$$reg),
7641 as_FloatRegister($src$$reg));
7642 %}
7643
7644 ins_pipe(fp_sqrt_s);
7645 %}
7646
7647 instruct sqrtD_reg(fRegD dst, fRegD src) %{
7648 match(Set dst (SqrtD src));
7649
7650 ins_cost(FSQRT_COST);
7651 format %{ "fsqrt.d $dst, $src\t#@sqrtD_reg" %}
7652 ins_encode %{
7653 __ fsqrt_d(as_FloatRegister($dst$$reg),
7654 as_FloatRegister($src$$reg));
7655 %}
7656
7657 ins_pipe(fp_sqrt_d);
7658 %}
7659
7660 // Round Instruction
7661 instruct roundD_reg(fRegD dst, fRegD src, immI rmode, iRegLNoSp tmp1, iRegLNoSp tmp2, iRegLNoSp tmp3) %{
7662 match(Set dst (RoundDoubleMode src rmode));
7663 ins_cost(2 * XFER_COST + BRANCH_COST);
7664 effect(TEMP_DEF dst, TEMP tmp1, TEMP tmp2, TEMP tmp3);
7665
7666 format %{ "RoundDoubleMode $src, $rmode" %}
7667 ins_encode %{
7668 __ round_double_mode(as_FloatRegister($dst$$reg),
7669 as_FloatRegister($src$$reg), $rmode$$constant, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
7670 %}
7671 ins_pipe(pipe_class_default);
7672 %}
7673
7674 // Copysign and signum intrinsics
7675
7676 instruct copySignD_reg(fRegD dst, fRegD src1, fRegD src2, immD zero) %{
7677 match(Set dst (CopySignD src1 (Binary src2 zero)));
7678 format %{ "CopySignD $dst $src1 $src2" %}
7679 ins_encode %{
7680 FloatRegister dst = as_FloatRegister($dst$$reg),
7681 src1 = as_FloatRegister($src1$$reg),
7682 src2 = as_FloatRegister($src2$$reg);
7683 __ fsgnj_d(dst, src1, src2);
7684 %}
7685 ins_pipe(fp_dop_reg_reg_d);
7686 %}
7687
7688 instruct copySignF_reg(fRegF dst, fRegF src1, fRegF src2) %{
7689 match(Set dst (CopySignF src1 src2));
7690 format %{ "CopySignF $dst $src1 $src2" %}
7691 ins_encode %{
7692 FloatRegister dst = as_FloatRegister($dst$$reg),
7693 src1 = as_FloatRegister($src1$$reg),
7694 src2 = as_FloatRegister($src2$$reg);
7695 __ fsgnj_s(dst, src1, src2);
7696 %}
7697 ins_pipe(fp_dop_reg_reg_s);
7698 %}
7699
7700 instruct signumD_reg(fRegD dst, immD zero, fRegD one) %{
7701 match(Set dst (SignumD dst (Binary zero one)));
7702 format %{ "signumD $dst, $dst" %}
7703 ins_encode %{
7704 __ signum_fp(as_FloatRegister($dst$$reg), as_FloatRegister($one$$reg), true /* is_double */);
7705 %}
7706 ins_pipe(pipe_class_default);
7707 %}
7708
7709 instruct signumF_reg(fRegF dst, immF zero, fRegF one) %{
7710 match(Set dst (SignumF dst (Binary zero one)));
7711 format %{ "signumF $dst, $dst" %}
7712 ins_encode %{
7713 __ signum_fp(as_FloatRegister($dst$$reg), as_FloatRegister($one$$reg), false /* is_double */);
7714 %}
7715 ins_pipe(pipe_class_default);
7716 %}
7717
7718 // Arithmetic Instructions End
7719
7720 // ============================================================================
7721 // Logical Instructions
7722
7723 // Register And
7724 instruct andI_reg_reg(iRegINoSp dst, iRegI src1, iRegI src2) %{
7725 match(Set dst (AndI src1 src2));
7726
7727 format %{ "andr $dst, $src1, $src2\t#@andI_reg_reg" %}
7728
7729 ins_cost(ALU_COST);
7730 ins_encode %{
7731 __ andr(as_Register($dst$$reg),
7732 as_Register($src1$$reg),
7733 as_Register($src2$$reg));
7734 %}
7735
7736 ins_pipe(ialu_reg_reg);
7737 %}
7738
7739 // Immediate And
7740 instruct andI_reg_imm(iRegINoSp dst, iRegI src1, immIAdd src2) %{
7741 match(Set dst (AndI src1 src2));
7742
7743 format %{ "andi $dst, $src1, $src2\t#@andI_reg_imm" %}
7744
7745 ins_cost(ALU_COST);
7746 ins_encode %{
7747 __ andi(as_Register($dst$$reg),
7748 as_Register($src1$$reg),
7749 (int32_t)($src2$$constant));
7750 %}
7751
7752 ins_pipe(ialu_reg_imm);
7753 %}
7754
7755 // Register Or
7756 instruct orI_reg_reg(iRegINoSp dst, iRegI src1, iRegI src2) %{
7757 match(Set dst (OrI src1 src2));
7758
7759 format %{ "orr $dst, $src1, $src2\t#@orI_reg_reg" %}
7760
7761 ins_cost(ALU_COST);
7762 ins_encode %{
7763 __ orr(as_Register($dst$$reg),
7764 as_Register($src1$$reg),
7765 as_Register($src2$$reg));
7766 %}
7767
7768 ins_pipe(ialu_reg_reg);
7769 %}
7770
7771 // Immediate Or
7772 instruct orI_reg_imm(iRegINoSp dst, iRegI src1, immIAdd src2) %{
7773 match(Set dst (OrI src1 src2));
7774
7775 format %{ "ori $dst, $src1, $src2\t#@orI_reg_imm" %}
7776
7777 ins_cost(ALU_COST);
7778 ins_encode %{
7779 __ ori(as_Register($dst$$reg),
7780 as_Register($src1$$reg),
7781 (int32_t)($src2$$constant));
7782 %}
7783
7784 ins_pipe(ialu_reg_imm);
7785 %}
7786
7787 // Register Xor
7788 instruct xorI_reg_reg(iRegINoSp dst, iRegI src1, iRegI src2) %{
7789 match(Set dst (XorI src1 src2));
7790
7791 format %{ "xorr $dst, $src1, $src2\t#@xorI_reg_reg" %}
7792
7793 ins_cost(ALU_COST);
7794 ins_encode %{
7795 __ xorr(as_Register($dst$$reg),
7796 as_Register($src1$$reg),
7797 as_Register($src2$$reg));
7798 %}
7799
7800 ins_pipe(ialu_reg_reg);
7801 %}
7802
7803 // Immediate Xor
7804 instruct xorI_reg_imm(iRegINoSp dst, iRegI src1, immIAdd src2) %{
7805 match(Set dst (XorI src1 src2));
7806
7807 format %{ "xori $dst, $src1, $src2\t#@xorI_reg_imm" %}
7808
7809 ins_cost(ALU_COST);
7810 ins_encode %{
7811 __ xori(as_Register($dst$$reg),
7812 as_Register($src1$$reg),
7813 (int32_t)($src2$$constant));
7814 %}
7815
7816 ins_pipe(ialu_reg_imm);
7817 %}
7818
7819 // Register And Long
7820 instruct andL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
7821 match(Set dst (AndL src1 src2));
7822
7823 format %{ "andr $dst, $src1, $src2\t#@andL_reg_reg" %}
7824
7825 ins_cost(ALU_COST);
7826 ins_encode %{
7827 __ andr(as_Register($dst$$reg),
7828 as_Register($src1$$reg),
7829 as_Register($src2$$reg));
7830 %}
7831
7832 ins_pipe(ialu_reg_reg);
7833 %}
7834
7835 // Immediate And Long
7836 instruct andL_reg_imm(iRegLNoSp dst, iRegL src1, immLAdd src2) %{
7837 match(Set dst (AndL src1 src2));
7838
7839 format %{ "andi $dst, $src1, $src2\t#@andL_reg_imm" %}
7840
7841 ins_cost(ALU_COST);
7842 ins_encode %{
7843 __ andi(as_Register($dst$$reg),
7844 as_Register($src1$$reg),
7845 (int32_t)($src2$$constant));
7846 %}
7847
7848 ins_pipe(ialu_reg_imm);
7849 %}
7850
7851 // Register Or Long
7852 instruct orL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
7853 match(Set dst (OrL src1 src2));
7854
7855 format %{ "orr $dst, $src1, $src2\t#@orL_reg_reg" %}
7856
7857 ins_cost(ALU_COST);
7858 ins_encode %{
7859 __ orr(as_Register($dst$$reg),
7860 as_Register($src1$$reg),
7861 as_Register($src2$$reg));
7862 %}
7863
7864 ins_pipe(ialu_reg_reg);
7865 %}
7866
7867 // Immediate Or Long
7868 instruct orL_reg_imm(iRegLNoSp dst, iRegL src1, immLAdd src2) %{
7869 match(Set dst (OrL src1 src2));
7870
7871 format %{ "ori $dst, $src1, $src2\t#@orL_reg_imm" %}
7872
7873 ins_cost(ALU_COST);
7874 ins_encode %{
7875 __ ori(as_Register($dst$$reg),
7876 as_Register($src1$$reg),
7877 (int32_t)($src2$$constant));
7878 %}
7879
7880 ins_pipe(ialu_reg_imm);
7881 %}
7882
7883 // Register Xor Long
7884 instruct xorL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
7885 match(Set dst (XorL src1 src2));
7886
7887 format %{ "xorr $dst, $src1, $src2\t#@xorL_reg_reg" %}
7888
7889 ins_cost(ALU_COST);
7890 ins_encode %{
7891 __ xorr(as_Register($dst$$reg),
7892 as_Register($src1$$reg),
7893 as_Register($src2$$reg));
7894 %}
7895
7896 ins_pipe(ialu_reg_reg);
7897 %}
7898
7899 // Immediate Xor Long
7900 instruct xorL_reg_imm(iRegLNoSp dst, iRegL src1, immLAdd src2) %{
7901 match(Set dst (XorL src1 src2));
7902
7903 ins_cost(ALU_COST);
7904 format %{ "xori $dst, $src1, $src2\t#@xorL_reg_imm" %}
7905
7906 ins_encode %{
7907 __ xori(as_Register($dst$$reg),
7908 as_Register($src1$$reg),
7909 (int32_t)($src2$$constant));
7910 %}
7911
7912 ins_pipe(ialu_reg_imm);
7913 %}
7914
7915 // ============================================================================
7916 // MemBar Instruction
7917
7918 // RVTSO
7919
7920 instruct unnecessary_membar_rvtso() %{
7921 predicate(UseZtso);
7922 match(LoadFence);
7923 match(StoreFence);
7924 match(StoreStoreFence);
7925 match(MemBarAcquire);
7926 match(MemBarRelease);
7927 match(MemBarStoreStore);
7928 match(MemBarAcquireLock);
7929 match(MemBarReleaseLock);
7930
7931 ins_cost(0);
7932
7933 size(0);
7934
7935 format %{ "#@unnecessary_membar_rvtso elided/tso (empty encoding)" %}
7936 ins_encode %{
7937 __ block_comment("unnecessary_membar_rvtso");
7938 %}
7939 ins_pipe(real_empty);
7940 %}
7941
7942 instruct membar_volatile_rvtso() %{
7943 predicate(UseZtso);
7944 match(MemBarVolatile);
7945 ins_cost(VOLATILE_REF_COST);
7946
7947 format %{ "#@membar_volatile_rvtso\n\t"
7948 "fence w, r"%}
7949
7950 ins_encode %{
7951 __ block_comment("membar_volatile_rvtso");
7952 __ membar(MacroAssembler::StoreLoad);
7953 %}
7954
7955 ins_pipe(pipe_slow);
7956 %}
7957
7958 instruct unnecessary_membar_volatile_rvtso() %{
7959 predicate(UseZtso && Matcher::post_store_load_barrier(n));
7960 match(MemBarVolatile);
7961 ins_cost(0);
7962
7963 size(0);
7964
7965 format %{ "#@unnecessary_membar_volatile_rvtso (unnecessary so empty encoding)" %}
7966 ins_encode %{
7967 __ block_comment("unnecessary_membar_volatile_rvtso");
7968 %}
7969 ins_pipe(real_empty);
7970 %}
7971
7972 // RVWMO
7973
7974 instruct membar_aqcuire_rvwmo() %{
7975 predicate(!UseZtso);
7976 match(LoadFence);
7977 match(MemBarAcquire);
7978 ins_cost(VOLATILE_REF_COST);
7979
7980 format %{ "#@membar_aqcuire_rvwmo\n\t"
7981 "fence r, rw" %}
7982
7983 ins_encode %{
7984 __ block_comment("membar_aqcuire_rvwmo");
7985 __ membar(MacroAssembler::LoadLoad | MacroAssembler::LoadStore);
7986 %}
7987 ins_pipe(pipe_serial);
7988 %}
7989
7990 instruct membar_release_rvwmo() %{
7991 predicate(!UseZtso);
7992 match(StoreFence);
7993 match(MemBarRelease);
7994 ins_cost(VOLATILE_REF_COST);
7995
7996 format %{ "#@membar_release_rvwmo\n\t"
7997 "fence rw, w" %}
7998
7999 ins_encode %{
8000 __ block_comment("membar_release_rvwmo");
8001 __ membar(MacroAssembler::LoadStore | MacroAssembler::StoreStore);
8002 %}
8003 ins_pipe(pipe_serial);
8004 %}
8005
8006 instruct membar_storestore_rvwmo() %{
8007 predicate(!UseZtso);
8008 match(MemBarStoreStore);
8009 match(StoreStoreFence);
8010 ins_cost(VOLATILE_REF_COST);
8011
8012 format %{ "#@membar_storestore_rvwmo\n\t"
8013 "fence w, w" %}
8014
8015 ins_encode %{
8016 __ membar(MacroAssembler::StoreStore);
8017 %}
8018 ins_pipe(pipe_serial);
8019 %}
8020
8021 instruct membar_volatile_rvwmo() %{
8022 predicate(!UseZtso);
8023 match(MemBarVolatile);
8024 ins_cost(VOLATILE_REF_COST);
8025
8026 format %{ "#@membar_volatile_rvwmo\n\t"
8027 "fence w, r"%}
8028
8029 ins_encode %{
8030 __ block_comment("membar_volatile_rvwmo");
8031 __ membar(MacroAssembler::StoreLoad);
8032 %}
8033
8034 ins_pipe(pipe_serial);
8035 %}
8036
8037 instruct membar_lock_rvwmo() %{
8038 predicate(!UseZtso);
8039 match(MemBarAcquireLock);
8040 match(MemBarReleaseLock);
8041 ins_cost(0);
8042
8043 format %{ "#@membar_lock_rvwmo (elided)" %}
8044
8045 ins_encode %{
8046 __ block_comment("membar_lock_rvwmo (elided)");
8047 %}
8048
8049 ins_pipe(pipe_serial);
8050 %}
8051
8052 instruct unnecessary_membar_volatile_rvwmo() %{
8053 predicate(!UseZtso && Matcher::post_store_load_barrier(n));
8054 match(MemBarVolatile);
8055 ins_cost(0);
8056
8057 size(0);
8058 format %{ "#@unnecessary_membar_volatile_rvwmo (unnecessary so empty encoding)" %}
8059 ins_encode %{
8060 __ block_comment("unnecessary_membar_volatile_rvwmo");
8061 %}
8062 ins_pipe(real_empty);
8063 %}
8064
8065 instruct spin_wait() %{
8066 predicate(UseZihintpause);
8067 match(OnSpinWait);
8068 ins_cost(CACHE_MISS_COST);
8069
8070 format %{ "spin_wait" %}
8071
8072 ins_encode %{
8073 __ pause();
8074 %}
8075
8076 ins_pipe(pipe_serial);
8077 %}
8078
8079 // ============================================================================
8080 // Cast Instructions (Java-level type cast)
8081
8082 instruct castX2P(iRegPNoSp dst, iRegL src) %{
8083 match(Set dst (CastX2P src));
8084
8085 ins_cost(ALU_COST);
8086 format %{ "mv $dst, $src\t# long -> ptr, #@castX2P" %}
8087
8088 ins_encode %{
8089 if ($dst$$reg != $src$$reg) {
8090 __ mv(as_Register($dst$$reg), as_Register($src$$reg));
8091 }
8092 %}
8093
8094 ins_pipe(ialu_reg);
8095 %}
8096
8097 instruct castP2X(iRegLNoSp dst, iRegP src) %{
8098 match(Set dst (CastP2X src));
8099
8100 ins_cost(ALU_COST);
8101 format %{ "mv $dst, $src\t# ptr -> long, #@castP2X" %}
8102
8103 ins_encode %{
8104 if ($dst$$reg != $src$$reg) {
8105 __ mv(as_Register($dst$$reg), as_Register($src$$reg));
8106 }
8107 %}
8108
8109 ins_pipe(ialu_reg);
8110 %}
8111
8112 instruct castPP(iRegPNoSp dst)
8113 %{
8114 match(Set dst (CastPP dst));
8115 ins_cost(0);
8116
8117 size(0);
8118 format %{ "# castPP of $dst, #@castPP" %}
8119 ins_encode(/* empty encoding */);
8120 ins_pipe(pipe_class_empty);
8121 %}
8122
8123 instruct castLL(iRegL dst)
8124 %{
8125 match(Set dst (CastLL dst));
8126
8127 size(0);
8128 format %{ "# castLL of $dst, #@castLL" %}
8129 ins_encode(/* empty encoding */);
8130 ins_cost(0);
8131 ins_pipe(pipe_class_empty);
8132 %}
8133
8134 instruct castII(iRegI dst)
8135 %{
8136 match(Set dst (CastII dst));
8137
8138 size(0);
8139 format %{ "# castII of $dst, #@castII" %}
8140 ins_encode(/* empty encoding */);
8141 ins_cost(0);
8142 ins_pipe(pipe_class_empty);
8143 %}
8144
8145 instruct checkCastPP(iRegPNoSp dst)
8146 %{
8147 match(Set dst (CheckCastPP dst));
8148
8149 size(0);
8150 ins_cost(0);
8151 format %{ "# checkcastPP of $dst, #@checkCastPP" %}
8152 ins_encode(/* empty encoding */);
8153 ins_pipe(pipe_class_empty);
8154 %}
8155
8156 instruct castHH(fRegF dst)
8157 %{
8158 match(Set dst (CastHH dst));
8159
8160 size(0);
8161 format %{ "# castHH of $dst" %}
8162 ins_encode(/* empty encoding */);
8163 ins_cost(0);
8164 ins_pipe(pipe_class_empty);
8165 %}
8166
8167 instruct castFF(fRegF dst)
8168 %{
8169 match(Set dst (CastFF dst));
8170
8171 size(0);
8172 format %{ "# castFF of $dst" %}
8173 ins_encode(/* empty encoding */);
8174 ins_cost(0);
8175 ins_pipe(pipe_class_empty);
8176 %}
8177
8178 instruct castDD(fRegD dst)
8179 %{
8180 match(Set dst (CastDD dst));
8181
8182 size(0);
8183 format %{ "# castDD of $dst" %}
8184 ins_encode(/* empty encoding */);
8185 ins_cost(0);
8186 ins_pipe(pipe_class_empty);
8187 %}
8188
8189 instruct castVV(vReg dst)
8190 %{
8191 match(Set dst (CastVV dst));
8192
8193 size(0);
8194 format %{ "# castVV of $dst" %}
8195 ins_encode(/* empty encoding */);
8196 ins_cost(0);
8197 ins_pipe(pipe_class_empty);
8198 %}
8199
8200 // ============================================================================
8201 // Convert Instructions
8202
8203 // int to bool
8204 instruct convI2Bool(iRegINoSp dst, iRegI src)
8205 %{
8206 match(Set dst (Conv2B src));
8207
8208 ins_cost(ALU_COST);
8209 format %{ "snez $dst, $src\t#@convI2Bool" %}
8210
8211 ins_encode %{
8212 __ snez(as_Register($dst$$reg), as_Register($src$$reg));
8213 %}
8214
8215 ins_pipe(ialu_reg);
8216 %}
8217
8218 // pointer to bool
8219 instruct convP2Bool(iRegINoSp dst, iRegP src)
8220 %{
8221 match(Set dst (Conv2B src));
8222
8223 ins_cost(ALU_COST);
8224 format %{ "snez $dst, $src\t#@convP2Bool" %}
8225
8226 ins_encode %{
8227 __ snez(as_Register($dst$$reg), as_Register($src$$reg));
8228 %}
8229
8230 ins_pipe(ialu_reg);
8231 %}
8232
8233 // int <-> long
8234
8235 instruct convI2L_reg_reg(iRegLNoSp dst, iRegIorL2I src)
8236 %{
8237 match(Set dst (ConvI2L src));
8238
8239 ins_cost(ALU_COST);
8240 format %{ "addw $dst, $src, zr\t#@convI2L_reg_reg" %}
8241 ins_encode %{
8242 __ sext(as_Register($dst$$reg), as_Register($src$$reg), 32);
8243 %}
8244 ins_pipe(ialu_reg);
8245 %}
8246
8247 instruct convL2I_reg(iRegINoSp dst, iRegL src) %{
8248 match(Set dst (ConvL2I src));
8249
8250 ins_cost(ALU_COST);
8251 format %{ "addw $dst, $src, zr\t#@convL2I_reg" %}
8252
8253 ins_encode %{
8254 __ sext(as_Register($dst$$reg), as_Register($src$$reg), 32);
8255 %}
8256
8257 ins_pipe(ialu_reg);
8258 %}
8259
8260 // int to unsigned long (Zero-extend)
8261 instruct convI2UL_reg_reg(iRegLNoSp dst, iRegIorL2I src, immL_32bits mask)
8262 %{
8263 match(Set dst (AndL (ConvI2L src) mask));
8264
8265 ins_cost(ALU_COST * 2);
8266 format %{ "zext $dst, $src, 32\t# i2ul, #@convI2UL_reg_reg" %}
8267
8268 ins_encode %{
8269 __ zext(as_Register($dst$$reg), as_Register($src$$reg), 32);
8270 %}
8271
8272 ins_pipe(ialu_reg_shift);
8273 %}
8274
8275 // float <-> double
8276
8277 instruct convF2D_reg(fRegD dst, fRegF src) %{
8278 match(Set dst (ConvF2D src));
8279
8280 ins_cost(XFER_COST);
8281 format %{ "fcvt.d.s $dst, $src\t#@convF2D_reg" %}
8282
8283 ins_encode %{
8284 __ fcvt_d_s(as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg));
8285 %}
8286
8287 ins_pipe(fp_f2d);
8288 %}
8289
8290 instruct convD2F_reg(fRegF dst, fRegD src) %{
8291 match(Set dst (ConvD2F src));
8292
8293 ins_cost(XFER_COST);
8294 format %{ "fcvt.s.d $dst, $src\t#@convD2F_reg" %}
8295
8296 ins_encode %{
8297 __ fcvt_s_d(as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg));
8298 %}
8299
8300 ins_pipe(fp_d2f);
8301 %}
8302
8303 // single <-> half precision
8304
8305 instruct convHF2F_reg_reg(fRegF dst, iRegINoSp src, iRegINoSp tmp) %{
8306 match(Set dst (ConvHF2F src));
8307 effect(TEMP tmp);
8308 format %{ "fmv.h.x $dst, $src\t# move source from $src to $dst\n\t"
8309 "fcvt.s.h $dst, $dst\t# convert half to single precision"
8310 %}
8311 ins_encode %{
8312 __ float16_to_float($dst$$FloatRegister, $src$$Register, $tmp$$Register);
8313 %}
8314 ins_pipe(pipe_slow);
8315 %}
8316
8317 instruct convF2HF_reg_reg(iRegINoSp dst, fRegF src, fRegF ftmp, iRegINoSp xtmp) %{
8318 match(Set dst (ConvF2HF src));
8319 effect(TEMP_DEF dst, TEMP ftmp, TEMP xtmp);
8320 format %{ "fcvt.h.s $ftmp, $src\t# convert single precision to half\n\t"
8321 "fmv.x.h $dst, $ftmp\t# move result from $ftmp to $dst"
8322 %}
8323 ins_encode %{
8324 __ float_to_float16($dst$$Register, $src$$FloatRegister, $ftmp$$FloatRegister, $xtmp$$Register);
8325 %}
8326 ins_pipe(pipe_slow);
8327 %}
8328
8329 // half precision operations
8330
8331 instruct reinterpretS2HF(fRegF dst, iRegI src)
8332 %{
8333 match(Set dst (ReinterpretS2HF src));
8334 format %{ "fmv.h.x $dst, $src" %}
8335 ins_encode %{
8336 __ fmv_h_x($dst$$FloatRegister, $src$$Register);
8337 %}
8338 ins_pipe(fp_i2f);
8339 %}
8340
8341 instruct convF2HFAndS2HF(fRegF dst, fRegF src)
8342 %{
8343 match(Set dst (ReinterpretS2HF (ConvF2HF src)));
8344 format %{ "convF2HFAndS2HF $dst, $src" %}
8345 ins_encode %{
8346 __ fcvt_h_s($dst$$FloatRegister, $src$$FloatRegister);
8347 %}
8348 ins_pipe(fp_uop_s);
8349 %}
8350
8351 instruct reinterpretHF2S(iRegINoSp dst, fRegF src)
8352 %{
8353 match(Set dst (ReinterpretHF2S src));
8354 format %{ "fmv.x.h $dst, $src" %}
8355 ins_encode %{
8356 __ fmv_x_h($dst$$Register, $src$$FloatRegister);
8357 %}
8358 ins_pipe(fp_f2i);
8359 %}
8360
8361 instruct convHF2SAndHF2F(fRegF dst, fRegF src)
8362 %{
8363 match(Set dst (ConvHF2F (ReinterpretHF2S src)));
8364 format %{ "convHF2SAndHF2F $dst, $src" %}
8365 ins_encode %{
8366 __ fcvt_s_h($dst$$FloatRegister, $src$$FloatRegister);
8367 %}
8368 ins_pipe(fp_uop_s);
8369 %}
8370
8371 instruct sqrt_HF_reg(fRegF dst, fRegF src)
8372 %{
8373 match(Set dst (SqrtHF src));
8374 format %{ "fsqrt.h $dst, $src" %}
8375 ins_encode %{
8376 __ fsqrt_h($dst$$FloatRegister, $src$$FloatRegister);
8377 %}
8378 ins_pipe(fp_sqrt_s);
8379 %}
8380
8381 instruct binOps_HF_reg(fRegF dst, fRegF src1, fRegF src2)
8382 %{
8383 match(Set dst (AddHF src1 src2));
8384 match(Set dst (SubHF src1 src2));
8385 match(Set dst (MulHF src1 src2));
8386 match(Set dst (DivHF src1 src2));
8387 format %{ "binop_hf $dst, $src1, $src2" %}
8388 ins_encode %{
8389 int opcode = this->ideal_Opcode();
8390 switch(opcode) {
8391 case Op_AddHF: __ fadd_h($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); break;
8392 case Op_SubHF: __ fsub_h($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); break;
8393 case Op_MulHF: __ fmul_h($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); break;
8394 case Op_DivHF: __ fdiv_h($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); break;
8395 default: assert(false, "%s is not supported here", NodeClassNames[opcode]); break;
8396 }
8397 %}
8398 ins_pipe(fp_dop_reg_reg_s);
8399 %}
8400
8401 instruct min_HF_reg(fRegF dst, fRegF src1, fRegF src2, rFlagsReg cr)
8402 %{
8403 predicate(!UseZfa);
8404 match(Set dst (MinHF src1 src2));
8405 effect(KILL cr);
8406
8407 format %{ "min_hf $dst, $src1, $src2" %}
8408
8409 ins_encode %{
8410 __ minmax_fp($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister,
8411 __ FLOAT_TYPE::half_precision, true /* is_min */);
8412 %}
8413 ins_pipe(pipe_class_default);
8414 %}
8415
8416 instruct min_HF_reg_zfa(fRegF dst, fRegF src1, fRegF src2)
8417 %{
8418 predicate(UseZfa);
8419 match(Set dst (MinHF src1 src2));
8420
8421 format %{ "min_hf $dst, $src1, $src2" %}
8422
8423 ins_encode %{
8424 __ fminm_h(as_FloatRegister($dst$$reg),
8425 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
8426 %}
8427
8428 ins_pipe(pipe_class_default);
8429 %}
8430
8431 instruct max_HF_reg(fRegF dst, fRegF src1, fRegF src2, rFlagsReg cr)
8432 %{
8433 predicate(!UseZfa);
8434 match(Set dst (MaxHF src1 src2));
8435 effect(KILL cr);
8436
8437 format %{ "max_hf $dst, $src1, $src2" %}
8438
8439 ins_encode %{
8440 __ minmax_fp($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister,
8441 __ FLOAT_TYPE::half_precision, false /* is_min */);
8442 %}
8443 ins_pipe(pipe_class_default);
8444 %}
8445
8446 instruct max_HF_reg_zfa(fRegF dst, fRegF src1, fRegF src2)
8447 %{
8448 predicate(UseZfa);
8449 match(Set dst (MaxHF src1 src2));
8450
8451 format %{ "max_hf $dst, $src1, $src2" %}
8452
8453 ins_encode %{
8454 __ fmaxm_h(as_FloatRegister($dst$$reg),
8455 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
8456 %}
8457
8458 ins_pipe(pipe_class_default);
8459 %}
8460
8461 instruct fma_HF_reg(fRegF dst, fRegF src1, fRegF src2, fRegF src3)
8462 %{
8463 match(Set dst (FmaHF src3 (Binary src1 src2)));
8464 format %{ "fmadd.h $dst, $src1, $src2, $src3\t# $dst = $src1 * $src2 + $src3 fma packedH" %}
8465 ins_encode %{
8466 __ fmadd_h($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister, $src3$$FloatRegister);
8467 %}
8468 ins_pipe(pipe_class_default);
8469 %}
8470
8471 // float <-> int
8472
8473 instruct convF2I_reg_reg(iRegINoSp dst, fRegF src) %{
8474 match(Set dst (ConvF2I src));
8475
8476 ins_cost(XFER_COST);
8477 format %{ "fcvt.w.s $dst, $src\t#@convF2I_reg_reg" %}
8478
8479 ins_encode %{
8480 __ fcvt_w_s_safe($dst$$Register, $src$$FloatRegister);
8481 %}
8482
8483 ins_pipe(fp_f2i);
8484 %}
8485
8486 instruct convI2F_reg_reg(fRegF dst, iRegIorL2I src) %{
8487 match(Set dst (ConvI2F src));
8488
8489 ins_cost(XFER_COST);
8490 format %{ "fcvt.s.w $dst, $src\t#@convI2F_reg_reg" %}
8491
8492 ins_encode %{
8493 __ fcvt_s_w(as_FloatRegister($dst$$reg), as_Register($src$$reg));
8494 %}
8495
8496 ins_pipe(fp_i2f);
8497 %}
8498
8499 // float <-> long
8500
8501 instruct convF2L_reg_reg(iRegLNoSp dst, fRegF src) %{
8502 match(Set dst (ConvF2L src));
8503
8504 ins_cost(XFER_COST);
8505 format %{ "fcvt.l.s $dst, $src\t#@convF2L_reg_reg" %}
8506
8507 ins_encode %{
8508 __ fcvt_l_s_safe($dst$$Register, $src$$FloatRegister);
8509 %}
8510
8511 ins_pipe(fp_f2l);
8512 %}
8513
8514 instruct convL2F_reg_reg(fRegF dst, iRegL src) %{
8515 match(Set dst (ConvL2F src));
8516
8517 ins_cost(XFER_COST);
8518 format %{ "fcvt.s.l $dst, $src\t#@convL2F_reg_reg" %}
8519
8520 ins_encode %{
8521 __ fcvt_s_l(as_FloatRegister($dst$$reg), as_Register($src$$reg));
8522 %}
8523
8524 ins_pipe(fp_l2f);
8525 %}
8526
8527 // double <-> int
8528
8529 instruct convD2I_reg_reg(iRegINoSp dst, fRegD src) %{
8530 match(Set dst (ConvD2I src));
8531
8532 ins_cost(XFER_COST);
8533 format %{ "fcvt.w.d $dst, $src\t#@convD2I_reg_reg" %}
8534
8535 ins_encode %{
8536 __ fcvt_w_d_safe($dst$$Register, $src$$FloatRegister);
8537 %}
8538
8539 ins_pipe(fp_d2i);
8540 %}
8541
8542 instruct convI2D_reg_reg(fRegD dst, iRegIorL2I src) %{
8543 match(Set dst (ConvI2D src));
8544
8545 ins_cost(XFER_COST);
8546 format %{ "fcvt.d.w $dst, $src\t#@convI2D_reg_reg" %}
8547
8548 ins_encode %{
8549 __ fcvt_d_w(as_FloatRegister($dst$$reg), as_Register($src$$reg));
8550 %}
8551
8552 ins_pipe(fp_i2d);
8553 %}
8554
8555 // double <-> long
8556
8557 instruct convD2L_reg_reg(iRegLNoSp dst, fRegD src) %{
8558 match(Set dst (ConvD2L src));
8559
8560 ins_cost(XFER_COST);
8561 format %{ "fcvt.l.d $dst, $src\t#@convD2L_reg_reg" %}
8562
8563 ins_encode %{
8564 __ fcvt_l_d_safe($dst$$Register, $src$$FloatRegister);
8565 %}
8566
8567 ins_pipe(fp_d2l);
8568 %}
8569
8570 instruct convL2D_reg_reg(fRegD dst, iRegL src) %{
8571 match(Set dst (ConvL2D src));
8572
8573 ins_cost(XFER_COST);
8574 format %{ "fcvt.d.l $dst, $src\t#@convL2D_reg_reg" %}
8575
8576 ins_encode %{
8577 __ fcvt_d_l(as_FloatRegister($dst$$reg), as_Register($src$$reg));
8578 %}
8579
8580 ins_pipe(fp_l2d);
8581 %}
8582
8583 // Convert oop into int for vectors alignment masking
8584 instruct convP2I(iRegINoSp dst, iRegP src) %{
8585 match(Set dst (ConvL2I (CastP2X src)));
8586
8587 ins_cost(ALU_COST * 2);
8588 format %{ "zext $dst, $src, 32\t# ptr -> int, #@convP2I" %}
8589
8590 ins_encode %{
8591 __ zext($dst$$Register, $src$$Register, 32);
8592 %}
8593
8594 ins_pipe(ialu_reg);
8595 %}
8596
8597 // Convert compressed oop into int for vectors alignment masking
8598 // in case of 32bit oops (heap < 4Gb).
8599 instruct convN2I(iRegINoSp dst, iRegN src)
8600 %{
8601 predicate(CompressedOops::shift() == 0);
8602 match(Set dst (ConvL2I (CastP2X (DecodeN src))));
8603
8604 ins_cost(ALU_COST);
8605 format %{ "mv $dst, $src\t# compressed ptr -> int, #@convN2I" %}
8606
8607 ins_encode %{
8608 __ mv($dst$$Register, $src$$Register);
8609 %}
8610
8611 ins_pipe(ialu_reg);
8612 %}
8613
8614 instruct round_double_reg(iRegLNoSp dst, fRegD src, fRegD ftmp) %{
8615 match(Set dst (RoundD src));
8616
8617 ins_cost(XFER_COST + BRANCH_COST);
8618 effect(TEMP ftmp);
8619 format %{ "java_round_double $dst, $src\t#@round_double_reg" %}
8620
8621 ins_encode %{
8622 __ java_round_double($dst$$Register, as_FloatRegister($src$$reg), as_FloatRegister($ftmp$$reg));
8623 %}
8624
8625 ins_pipe(pipe_slow);
8626 %}
8627
8628 instruct round_float_reg(iRegINoSp dst, fRegF src, fRegF ftmp) %{
8629 match(Set dst (RoundF src));
8630
8631 ins_cost(XFER_COST + BRANCH_COST);
8632 effect(TEMP ftmp);
8633 format %{ "java_round_float $dst, $src\t#@round_float_reg" %}
8634
8635 ins_encode %{
8636 __ java_round_float($dst$$Register, as_FloatRegister($src$$reg), as_FloatRegister($ftmp$$reg));
8637 %}
8638
8639 ins_pipe(pipe_slow);
8640 %}
8641
8642 // Convert oop pointer into compressed form
8643 instruct encodeHeapOop(iRegNNoSp dst, iRegP src) %{
8644 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
8645 match(Set dst (EncodeP src));
8646 ins_cost(ALU_COST);
8647 format %{ "encode_heap_oop $dst, $src\t#@encodeHeapOop" %}
8648 ins_encode %{
8649 Register s = $src$$Register;
8650 Register d = $dst$$Register;
8651 __ encode_heap_oop(d, s);
8652 %}
8653 ins_pipe(pipe_class_default);
8654 %}
8655
8656 instruct encodeHeapOop_not_null(iRegNNoSp dst, iRegP src) %{
8657 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
8658 match(Set dst (EncodeP src));
8659 ins_cost(ALU_COST);
8660 format %{ "encode_heap_oop_not_null $dst, $src\t#@encodeHeapOop_not_null" %}
8661 ins_encode %{
8662 __ encode_heap_oop_not_null($dst$$Register, $src$$Register);
8663 %}
8664 ins_pipe(pipe_class_default);
8665 %}
8666
8667 instruct decodeHeapOop(iRegPNoSp dst, iRegN src) %{
8668 predicate(n->bottom_type()->is_ptr()->ptr() != TypePtr::NotNull &&
8669 n->bottom_type()->is_ptr()->ptr() != TypePtr::Constant);
8670 match(Set dst (DecodeN src));
8671
8672 ins_cost(0);
8673 format %{ "decode_heap_oop $dst, $src\t#@decodeHeapOop" %}
8674 ins_encode %{
8675 Register s = $src$$Register;
8676 Register d = $dst$$Register;
8677 __ decode_heap_oop(d, s);
8678 %}
8679 ins_pipe(pipe_class_default);
8680 %}
8681
8682 instruct decodeHeapOop_not_null(iRegPNoSp dst, iRegN src) %{
8683 predicate(n->bottom_type()->is_ptr()->ptr() == TypePtr::NotNull ||
8684 n->bottom_type()->is_ptr()->ptr() == TypePtr::Constant);
8685 match(Set dst (DecodeN src));
8686
8687 ins_cost(0);
8688 format %{ "decode_heap_oop_not_null $dst, $src\t#@decodeHeapOop_not_null" %}
8689 ins_encode %{
8690 Register s = $src$$Register;
8691 Register d = $dst$$Register;
8692 __ decode_heap_oop_not_null(d, s);
8693 %}
8694 ins_pipe(pipe_class_default);
8695 %}
8696
8697 // Convert klass pointer into compressed form.
8698 instruct encodeKlass_not_null(iRegNNoSp dst, iRegP src) %{
8699 match(Set dst (EncodePKlass src));
8700
8701 ins_cost(ALU_COST);
8702 format %{ "encode_klass_not_null $dst, $src\t#@encodeKlass_not_null" %}
8703
8704 ins_encode %{
8705 Register src_reg = as_Register($src$$reg);
8706 Register dst_reg = as_Register($dst$$reg);
8707 __ encode_klass_not_null(dst_reg, src_reg, t0);
8708 %}
8709
8710 ins_pipe(pipe_class_default);
8711 %}
8712
8713 instruct decodeKlass_not_null(iRegPNoSp dst, iRegN src, iRegPNoSp tmp) %{
8714 match(Set dst (DecodeNKlass src));
8715
8716 effect(TEMP tmp);
8717
8718 ins_cost(ALU_COST);
8719 format %{ "decode_klass_not_null $dst, $src\t#@decodeKlass_not_null" %}
8720
8721 ins_encode %{
8722 Register src_reg = as_Register($src$$reg);
8723 Register dst_reg = as_Register($dst$$reg);
8724 Register tmp_reg = as_Register($tmp$$reg);
8725 __ decode_klass_not_null(dst_reg, src_reg, tmp_reg);
8726 %}
8727
8728 ins_pipe(pipe_class_default);
8729 %}
8730
8731 // stack <-> reg and reg <-> reg shuffles with no conversion
8732
8733 instruct MoveF2I_stack_reg(iRegINoSp dst, stackSlotF src) %{
8734
8735 match(Set dst (MoveF2I src));
8736
8737 effect(DEF dst, USE src);
8738
8739 ins_cost(LOAD_COST);
8740
8741 format %{ "lw $dst, $src\t#@MoveF2I_stack_reg" %}
8742
8743 ins_encode %{
8744 __ lw(as_Register($dst$$reg), Address(sp, $src$$disp));
8745 %}
8746
8747 ins_pipe(iload_reg_reg);
8748
8749 %}
8750
8751 instruct MoveI2F_stack_reg(fRegF dst, stackSlotI src) %{
8752
8753 match(Set dst (MoveI2F src));
8754
8755 effect(DEF dst, USE src);
8756
8757 ins_cost(LOAD_COST);
8758
8759 format %{ "flw $dst, $src\t#@MoveI2F_stack_reg" %}
8760
8761 ins_encode %{
8762 __ flw(as_FloatRegister($dst$$reg), Address(sp, $src$$disp));
8763 %}
8764
8765 ins_pipe(fp_load_mem_s);
8766
8767 %}
8768
8769 instruct MoveD2L_stack_reg(iRegLNoSp dst, stackSlotD src) %{
8770
8771 match(Set dst (MoveD2L src));
8772
8773 effect(DEF dst, USE src);
8774
8775 ins_cost(LOAD_COST);
8776
8777 format %{ "ld $dst, $src\t#@MoveD2L_stack_reg" %}
8778
8779 ins_encode %{
8780 __ ld(as_Register($dst$$reg), Address(sp, $src$$disp));
8781 %}
8782
8783 ins_pipe(iload_reg_reg);
8784
8785 %}
8786
8787 instruct MoveL2D_stack_reg(fRegD dst, stackSlotL src) %{
8788
8789 match(Set dst (MoveL2D src));
8790
8791 effect(DEF dst, USE src);
8792
8793 ins_cost(LOAD_COST);
8794
8795 format %{ "fld $dst, $src\t#@MoveL2D_stack_reg" %}
8796
8797 ins_encode %{
8798 __ fld(as_FloatRegister($dst$$reg), Address(sp, $src$$disp));
8799 %}
8800
8801 ins_pipe(fp_load_mem_d);
8802
8803 %}
8804
8805 instruct MoveF2I_reg_stack(stackSlotI dst, fRegF src) %{
8806
8807 match(Set dst (MoveF2I src));
8808
8809 effect(DEF dst, USE src);
8810
8811 ins_cost(STORE_COST);
8812
8813 format %{ "fsw $src, $dst\t#@MoveF2I_reg_stack" %}
8814
8815 ins_encode %{
8816 __ fsw(as_FloatRegister($src$$reg), Address(sp, $dst$$disp));
8817 %}
8818
8819 ins_pipe(fp_store_reg_s);
8820
8821 %}
8822
8823 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{
8824
8825 match(Set dst (MoveI2F src));
8826
8827 effect(DEF dst, USE src);
8828
8829 ins_cost(STORE_COST);
8830
8831 format %{ "sw $src, $dst\t#@MoveI2F_reg_stack" %}
8832
8833 ins_encode %{
8834 __ sw(as_Register($src$$reg), Address(sp, $dst$$disp));
8835 %}
8836
8837 ins_pipe(istore_reg_reg);
8838
8839 %}
8840
8841 instruct MoveD2L_reg_stack(stackSlotL dst, fRegD src) %{
8842
8843 match(Set dst (MoveD2L src));
8844
8845 effect(DEF dst, USE src);
8846
8847 ins_cost(STORE_COST);
8848
8849 format %{ "fsd $dst, $src\t#@MoveD2L_reg_stack" %}
8850
8851 ins_encode %{
8852 __ fsd(as_FloatRegister($src$$reg), Address(sp, $dst$$disp));
8853 %}
8854
8855 ins_pipe(fp_store_reg_d);
8856
8857 %}
8858
8859 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{
8860
8861 match(Set dst (MoveL2D src));
8862
8863 effect(DEF dst, USE src);
8864
8865 ins_cost(STORE_COST);
8866
8867 format %{ "sd $src, $dst\t#@MoveL2D_reg_stack" %}
8868
8869 ins_encode %{
8870 __ sd(as_Register($src$$reg), Address(sp, $dst$$disp));
8871 %}
8872
8873 ins_pipe(istore_reg_reg);
8874
8875 %}
8876
8877 instruct MoveF2I_reg_reg(iRegINoSp dst, fRegF src) %{
8878
8879 match(Set dst (MoveF2I src));
8880
8881 effect(DEF dst, USE src);
8882
8883 ins_cost(FMVX_COST);
8884
8885 format %{ "fmv.x.w $dst, $src\t#@MoveF2I_reg_reg" %}
8886
8887 ins_encode %{
8888 __ fmv_x_w(as_Register($dst$$reg), as_FloatRegister($src$$reg));
8889 %}
8890
8891 ins_pipe(fp_f2i);
8892
8893 %}
8894
8895 instruct MoveI2F_reg_reg(fRegF dst, iRegI src) %{
8896
8897 match(Set dst (MoveI2F src));
8898
8899 effect(DEF dst, USE src);
8900
8901 ins_cost(FMVX_COST);
8902
8903 format %{ "fmv.w.x $dst, $src\t#@MoveI2F_reg_reg" %}
8904
8905 ins_encode %{
8906 __ fmv_w_x(as_FloatRegister($dst$$reg), as_Register($src$$reg));
8907 %}
8908
8909 ins_pipe(fp_i2f);
8910
8911 %}
8912
8913 instruct MoveD2L_reg_reg(iRegLNoSp dst, fRegD src) %{
8914
8915 match(Set dst (MoveD2L src));
8916
8917 effect(DEF dst, USE src);
8918
8919 ins_cost(FMVX_COST);
8920
8921 format %{ "fmv.x.d $dst, $src\t#@MoveD2L_reg_reg" %}
8922
8923 ins_encode %{
8924 __ fmv_x_d(as_Register($dst$$reg), as_FloatRegister($src$$reg));
8925 %}
8926
8927 ins_pipe(fp_d2l);
8928
8929 %}
8930
8931 instruct MoveL2D_reg_reg(fRegD dst, iRegL src) %{
8932
8933 match(Set dst (MoveL2D src));
8934
8935 effect(DEF dst, USE src);
8936
8937 ins_cost(FMVX_COST);
8938
8939 format %{ "fmv.d.x $dst, $src\t#@MoveL2D_reg_reg" %}
8940
8941 ins_encode %{
8942 __ fmv_d_x(as_FloatRegister($dst$$reg), as_Register($src$$reg));
8943 %}
8944
8945 ins_pipe(fp_l2d);
8946
8947 %}
8948
8949 // ============================================================================
8950 // Compare Instructions which set the result float comparisons in dest register.
8951
8952 instruct cmpF3_reg_reg(iRegINoSp dst, fRegF op1, fRegF op2)
8953 %{
8954 match(Set dst (CmpF3 op1 op2));
8955
8956 ins_cost(XFER_COST * 2 + BRANCH_COST + ALU_COST);
8957 format %{ "flt.s $dst, $op2, $op1\t#@cmpF3_reg_reg\n\t"
8958 "bgtz $dst, done\n\t"
8959 "feq.s $dst, $op1, $op2\n\t"
8960 "addi $dst, $dst, -1\n\t"
8961 "done:"
8962 %}
8963
8964 ins_encode %{
8965 // we want -1 for unordered or less than, 0 for equal and 1 for greater than.
8966 __ float_compare(as_Register($dst$$reg), as_FloatRegister($op1$$reg),
8967 as_FloatRegister($op2$$reg), -1 /*unordered_result < 0*/);
8968 %}
8969
8970 ins_pipe(pipe_class_default);
8971 %}
8972
8973 instruct cmpD3_reg_reg(iRegINoSp dst, fRegD op1, fRegD op2)
8974 %{
8975 match(Set dst (CmpD3 op1 op2));
8976
8977 ins_cost(XFER_COST * 2 + BRANCH_COST + ALU_COST);
8978 format %{ "flt.d $dst, $op2, $op1\t#@cmpD3_reg_reg\n\t"
8979 "bgtz $dst, done\n\t"
8980 "feq.d $dst, $op1, $op2\n\t"
8981 "addi $dst, $dst, -1\n\t"
8982 "done:"
8983 %}
8984
8985 ins_encode %{
8986 // we want -1 for unordered or less than, 0 for equal and 1 for greater than.
8987 __ double_compare(as_Register($dst$$reg), as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg), -1 /*unordered_result < 0*/);
8988 %}
8989
8990 ins_pipe(pipe_class_default);
8991 %}
8992
8993 instruct cmpL3_reg_reg(iRegINoSp dst, iRegL op1, iRegL op2)
8994 %{
8995 match(Set dst (CmpL3 op1 op2));
8996
8997 ins_cost(ALU_COST * 3 + BRANCH_COST);
8998 format %{ "slt $dst, $op2, $op1\t#@cmpL3_reg_reg\n\t"
8999 "bnez $dst, done\n\t"
9000 "slt $dst, $op1, $op2\n\t"
9001 "neg $dst, $dst\n\t"
9002 "done:"
9003 %}
9004 ins_encode %{
9005 __ cmp_l2i(t0, as_Register($op1$$reg), as_Register($op2$$reg));
9006 __ mv(as_Register($dst$$reg), t0);
9007 %}
9008
9009 ins_pipe(pipe_class_default);
9010 %}
9011
9012 instruct cmpUL3_reg_reg(iRegINoSp dst, iRegL op1, iRegL op2)
9013 %{
9014 match(Set dst (CmpUL3 op1 op2));
9015
9016 ins_cost(ALU_COST * 3 + BRANCH_COST);
9017 format %{ "sltu $dst, $op2, $op1\t#@cmpUL3_reg_reg\n\t"
9018 "bnez $dst, done\n\t"
9019 "sltu $dst, $op1, $op2\n\t"
9020 "neg $dst, $dst\n\t"
9021 "done:"
9022 %}
9023 ins_encode %{
9024 __ cmp_ul2i(t0, as_Register($op1$$reg), as_Register($op2$$reg));
9025 __ mv(as_Register($dst$$reg), t0);
9026 %}
9027
9028 ins_pipe(pipe_class_default);
9029 %}
9030
9031 instruct cmpU3_reg_reg(iRegINoSp dst, iRegI op1, iRegI op2)
9032 %{
9033 match(Set dst (CmpU3 op1 op2));
9034
9035 ins_cost(ALU_COST * 3 + BRANCH_COST);
9036 format %{ "sltu $dst, $op2, $op1\t#@cmpU3_reg_reg\n\t"
9037 "bnez $dst, done\n\t"
9038 "sltu $dst, $op1, $op2\n\t"
9039 "neg $dst, $dst\n\t"
9040 "done:"
9041 %}
9042 ins_encode %{
9043 __ cmp_uw2i(t0, as_Register($op1$$reg), as_Register($op2$$reg));
9044 __ mv(as_Register($dst$$reg), t0);
9045 %}
9046
9047 ins_pipe(pipe_class_default);
9048 %}
9049
9050 instruct cmpLTMask_reg_reg(iRegINoSp dst, iRegI p, iRegI q)
9051 %{
9052 match(Set dst (CmpLTMask p q));
9053
9054 ins_cost(2 * ALU_COST);
9055
9056 format %{ "slt $dst, $p, $q\t#@cmpLTMask_reg_reg\n\t"
9057 "subw $dst, zr, $dst\t#@cmpLTMask_reg_reg"
9058 %}
9059
9060 ins_encode %{
9061 __ slt(as_Register($dst$$reg), as_Register($p$$reg), as_Register($q$$reg));
9062 __ subw(as_Register($dst$$reg), zr, as_Register($dst$$reg));
9063 %}
9064
9065 ins_pipe(ialu_reg_reg);
9066 %}
9067
9068 instruct cmpLTMask_reg_zero(iRegINoSp dst, iRegIorL2I op, immI0 zero)
9069 %{
9070 match(Set dst (CmpLTMask op zero));
9071
9072 ins_cost(ALU_COST);
9073
9074 format %{ "sraiw $dst, $dst, 31\t#@cmpLTMask_reg_reg" %}
9075
9076 ins_encode %{
9077 __ sraiw(as_Register($dst$$reg), as_Register($op$$reg), 31);
9078 %}
9079
9080 ins_pipe(ialu_reg_shift);
9081 %}
9082
9083
9084 // ============================================================================
9085 // Max and Min
9086
9087 instruct minI_reg_reg(iRegINoSp dst, iRegI src)
9088 %{
9089 match(Set dst (MinI dst src));
9090
9091 ins_cost(BRANCH_COST + ALU_COST);
9092 format %{"minI_reg_reg $dst, $dst, $src\t#@minI_reg_reg\n\t"%}
9093
9094 ins_encode %{
9095 __ cmov_gt(as_Register($dst$$reg), as_Register($src$$reg),
9096 as_Register($dst$$reg), as_Register($src$$reg));
9097 %}
9098
9099 ins_pipe(pipe_class_compare);
9100 %}
9101
9102 instruct maxI_reg_reg(iRegINoSp dst, iRegI src)
9103 %{
9104 match(Set dst (MaxI dst src));
9105
9106 ins_cost(BRANCH_COST + ALU_COST);
9107 format %{"maxI_reg_reg $dst, $dst, $src\t#@maxI_reg_reg\n\t"%}
9108
9109 ins_encode %{
9110 __ cmov_lt(as_Register($dst$$reg), as_Register($src$$reg),
9111 as_Register($dst$$reg), as_Register($src$$reg));
9112 %}
9113
9114 ins_pipe(pipe_class_compare);
9115 %}
9116
9117 // special case for comparing with zero
9118 // n.b. this is selected in preference to the rule above because it
9119 // avoids loading constant 0 into a source register
9120
9121 instruct minI_reg_zero(iRegINoSp dst, immI0 zero)
9122 %{
9123 match(Set dst (MinI dst zero));
9124 match(Set dst (MinI zero dst));
9125
9126 ins_cost(BRANCH_COST + ALU_COST);
9127 format %{"minI_reg_zero $dst, $dst, zr\t#@minI_reg_zero\n\t"%}
9128
9129 ins_encode %{
9130 __ cmov_gt(as_Register($dst$$reg), zr,
9131 as_Register($dst$$reg), zr);
9132 %}
9133
9134 ins_pipe(pipe_class_compare);
9135 %}
9136
9137 instruct maxI_reg_zero(iRegINoSp dst, immI0 zero)
9138 %{
9139 match(Set dst (MaxI dst zero));
9140 match(Set dst (MaxI zero dst));
9141
9142 ins_cost(BRANCH_COST + ALU_COST);
9143 format %{"maxI_reg_zero $dst, $dst, zr\t#@maxI_reg_zero\n\t"%}
9144
9145 ins_encode %{
9146 __ cmov_lt(as_Register($dst$$reg), zr,
9147 as_Register($dst$$reg), zr);
9148 %}
9149
9150 ins_pipe(pipe_class_compare);
9151 %}
9152
9153 instruct minI_rReg(iRegINoSp dst, iRegI src1, iRegI src2)
9154 %{
9155 match(Set dst (MinI src1 src2));
9156
9157 effect(DEF dst, USE src1, USE src2);
9158
9159 ins_cost(BRANCH_COST + ALU_COST * 2);
9160 format %{"minI_rReg $dst, $src1, $src2\t#@minI_rReg\n\t"%}
9161
9162 ins_encode %{
9163 __ mv(as_Register($dst$$reg), as_Register($src1$$reg));
9164 __ cmov_gt(as_Register($src1$$reg), as_Register($src2$$reg),
9165 as_Register($dst$$reg), as_Register($src2$$reg));
9166 %}
9167
9168 ins_pipe(pipe_class_compare);
9169 %}
9170
9171 instruct maxI_rReg(iRegINoSp dst, iRegI src1, iRegI src2)
9172 %{
9173 match(Set dst (MaxI src1 src2));
9174
9175 effect(DEF dst, USE src1, USE src2);
9176
9177 ins_cost(BRANCH_COST + ALU_COST * 2);
9178 format %{"maxI_rReg $dst, $src1, $src2\t#@maxI_rReg\n\t"%}
9179
9180 ins_encode %{
9181 __ mv(as_Register($dst$$reg), as_Register($src1$$reg));
9182 __ cmov_lt(as_Register($src1$$reg), as_Register($src2$$reg),
9183 as_Register($dst$$reg), as_Register($src2$$reg));
9184 %}
9185
9186 ins_pipe(pipe_class_compare);
9187 %}
9188
9189 // ============================================================================
9190 // Branch Instructions
9191 // Direct Branch.
9192 instruct branch(label lbl)
9193 %{
9194 match(Goto);
9195
9196 effect(USE lbl);
9197
9198 ins_cost(BRANCH_COST);
9199 format %{ "j $lbl\t#@branch" %}
9200
9201 ins_encode(riscv_enc_j(lbl));
9202
9203 ins_pipe(pipe_branch);
9204 %}
9205
9206 // ============================================================================
9207 // Compare and Branch Instructions
9208
9209 // Patterns for short (< 12KiB) variants
9210
9211 // Compare flags and branch near instructions.
9212 instruct cmpFlag_branch(cmpOpEqNe cmp, rFlagsReg cr, label lbl) %{
9213 match(If cmp cr);
9214 effect(USE lbl);
9215
9216 ins_cost(BRANCH_COST);
9217 format %{ "b$cmp $cr, zr, $lbl\t#@cmpFlag_branch" %}
9218
9219 ins_encode %{
9220 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($cr$$reg), *($lbl$$label));
9221 %}
9222 ins_pipe(pipe_cmpz_branch);
9223 ins_short_branch(1);
9224 %}
9225
9226 // Compare signed int and branch near instructions
9227 instruct cmpI_branch(cmpOp cmp, iRegI op1, iRegI op2, label lbl)
9228 %{
9229 // Same match rule as `far_cmpI_branch'.
9230 match(If cmp (CmpI op1 op2));
9231
9232 effect(USE lbl);
9233
9234 ins_cost(BRANCH_COST);
9235
9236 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpI_branch" %}
9237
9238 ins_encode %{
9239 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label));
9240 %}
9241
9242 ins_pipe(pipe_cmp_branch);
9243 ins_short_branch(1);
9244 %}
9245
9246 instruct cmpI_loop(cmpOp cmp, iRegI op1, iRegI op2, label lbl)
9247 %{
9248 // Same match rule as `far_cmpI_loop'.
9249 match(CountedLoopEnd cmp (CmpI op1 op2));
9250
9251 effect(USE lbl);
9252
9253 ins_cost(BRANCH_COST);
9254
9255 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpI_loop" %}
9256
9257 ins_encode %{
9258 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label));
9259 %}
9260
9261 ins_pipe(pipe_cmp_branch);
9262 ins_short_branch(1);
9263 %}
9264
9265 // Compare unsigned int and branch near instructions
9266 instruct cmpU_branch(cmpOpU cmp, iRegI op1, iRegI op2, label lbl)
9267 %{
9268 // Same match rule as `far_cmpU_branch'.
9269 match(If cmp (CmpU op1 op2));
9270
9271 effect(USE lbl);
9272
9273 ins_cost(BRANCH_COST);
9274
9275 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpU_branch" %}
9276
9277 ins_encode %{
9278 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9279 as_Register($op2$$reg), *($lbl$$label));
9280 %}
9281
9282 ins_pipe(pipe_cmp_branch);
9283 ins_short_branch(1);
9284 %}
9285
9286 // Compare signed long and branch near instructions
9287 instruct cmpL_branch(cmpOp cmp, iRegL op1, iRegL op2, label lbl)
9288 %{
9289 // Same match rule as `far_cmpL_branch'.
9290 match(If cmp (CmpL op1 op2));
9291
9292 effect(USE lbl);
9293
9294 ins_cost(BRANCH_COST);
9295
9296 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpL_branch" %}
9297
9298 ins_encode %{
9299 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label));
9300 %}
9301
9302 ins_pipe(pipe_cmp_branch);
9303 ins_short_branch(1);
9304 %}
9305
9306 instruct cmpL_loop(cmpOp cmp, iRegL op1, iRegL op2, label lbl)
9307 %{
9308 // Same match rule as `far_cmpL_loop'.
9309 match(CountedLoopEnd cmp (CmpL op1 op2));
9310
9311 effect(USE lbl);
9312
9313 ins_cost(BRANCH_COST);
9314
9315 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpL_loop" %}
9316
9317 ins_encode %{
9318 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label));
9319 %}
9320
9321 ins_pipe(pipe_cmp_branch);
9322 ins_short_branch(1);
9323 %}
9324
9325 // Compare unsigned long and branch near instructions
9326 instruct cmpUL_branch(cmpOpU cmp, iRegL op1, iRegL op2, label lbl)
9327 %{
9328 // Same match rule as `far_cmpUL_branch'.
9329 match(If cmp (CmpUL op1 op2));
9330
9331 effect(USE lbl);
9332
9333 ins_cost(BRANCH_COST);
9334 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpUL_branch" %}
9335
9336 ins_encode %{
9337 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9338 as_Register($op2$$reg), *($lbl$$label));
9339 %}
9340
9341 ins_pipe(pipe_cmp_branch);
9342 ins_short_branch(1);
9343 %}
9344
9345 // Compare pointer and branch near instructions
9346 instruct cmpP_branch(cmpOpU cmp, iRegP op1, iRegP op2, label lbl)
9347 %{
9348 // Same match rule as `far_cmpP_branch'.
9349 match(If cmp (CmpP op1 op2));
9350
9351 effect(USE lbl);
9352
9353 ins_cost(BRANCH_COST);
9354
9355 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpP_branch" %}
9356
9357 ins_encode %{
9358 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9359 as_Register($op2$$reg), *($lbl$$label));
9360 %}
9361
9362 ins_pipe(pipe_cmp_branch);
9363 ins_short_branch(1);
9364 %}
9365
9366 // Compare narrow pointer and branch near instructions
9367 instruct cmpN_branch(cmpOpU cmp, iRegN op1, iRegN op2, label lbl)
9368 %{
9369 // Same match rule as `far_cmpN_branch'.
9370 match(If cmp (CmpN op1 op2));
9371
9372 effect(USE lbl);
9373
9374 ins_cost(BRANCH_COST);
9375
9376 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpN_branch" %}
9377
9378 ins_encode %{
9379 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9380 as_Register($op2$$reg), *($lbl$$label));
9381 %}
9382
9383 ins_pipe(pipe_cmp_branch);
9384 ins_short_branch(1);
9385 %}
9386
9387 // Compare float and branch near instructions
9388 instruct cmpF_branch(cmpOp cmp, fRegF op1, fRegF op2, label lbl)
9389 %{
9390 // Same match rule as `far_cmpF_branch'.
9391 match(If cmp (CmpF op1 op2));
9392
9393 effect(USE lbl);
9394
9395 ins_cost(XFER_COST + BRANCH_COST);
9396 format %{ "float_b$cmp $op1, $op2, $lbl \t#@cmpF_branch"%}
9397
9398 ins_encode %{
9399 __ float_cmp_branch($cmp$$cmpcode, as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg), *($lbl$$label));
9400 %}
9401
9402 ins_pipe(pipe_class_compare);
9403 ins_short_branch(1);
9404 %}
9405
9406 // Compare double and branch near instructions
9407 instruct cmpD_branch(cmpOp cmp, fRegD op1, fRegD op2, label lbl)
9408 %{
9409 // Same match rule as `far_cmpD_branch'.
9410 match(If cmp (CmpD op1 op2));
9411 effect(USE lbl);
9412
9413 ins_cost(XFER_COST + BRANCH_COST);
9414 format %{ "double_b$cmp $op1, $op2, $lbl\t#@cmpD_branch"%}
9415
9416 ins_encode %{
9417 __ float_cmp_branch($cmp$$cmpcode | C2_MacroAssembler::double_branch_mask, as_FloatRegister($op1$$reg),
9418 as_FloatRegister($op2$$reg), *($lbl$$label));
9419 %}
9420
9421 ins_pipe(pipe_class_compare);
9422 ins_short_branch(1);
9423 %}
9424
9425 // Compare signed int with zero and branch near instructions
9426 instruct cmpI_reg_imm0_branch(cmpOp cmp, iRegI op1, immI0 zero, label lbl)
9427 %{
9428 // Same match rule as `far_cmpI_reg_imm0_branch'.
9429 match(If cmp (CmpI op1 zero));
9430
9431 effect(USE op1, USE lbl);
9432
9433 ins_cost(BRANCH_COST);
9434 format %{ "b$cmp $op1, zr, $lbl\t#@cmpI_reg_imm0_branch" %}
9435
9436 ins_encode %{
9437 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label));
9438 %}
9439
9440 ins_pipe(pipe_cmpz_branch);
9441 ins_short_branch(1);
9442 %}
9443
9444 instruct cmpI_reg_imm0_loop(cmpOp cmp, iRegI op1, immI0 zero, label lbl)
9445 %{
9446 // Same match rule as `far_cmpI_reg_imm0_loop'.
9447 match(CountedLoopEnd cmp (CmpI op1 zero));
9448
9449 effect(USE op1, USE lbl);
9450
9451 ins_cost(BRANCH_COST);
9452
9453 format %{ "b$cmp $op1, zr, $lbl\t#@cmpI_reg_imm0_loop" %}
9454
9455 ins_encode %{
9456 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label));
9457 %}
9458
9459 ins_pipe(pipe_cmpz_branch);
9460 ins_short_branch(1);
9461 %}
9462
9463 // Compare unsigned int with zero and branch near instructions
9464 instruct cmpUEqNeLeGt_reg_imm0_branch(cmpOpUEqNeLeGt cmp, iRegI op1, immI0 zero, label lbl)
9465 %{
9466 // Same match rule as `far_cmpUEqNeLeGt_reg_imm0_branch'.
9467 match(If cmp (CmpU op1 zero));
9468
9469 effect(USE op1, USE lbl);
9470
9471 ins_cost(BRANCH_COST);
9472
9473 format %{ "b$cmp $op1, zr, $lbl\t#@cmpUEqNeLeGt_reg_imm0_branch" %}
9474
9475 ins_encode %{
9476 __ enc_cmpUEqNeLeGt_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
9477 %}
9478
9479 ins_pipe(pipe_cmpz_branch);
9480 ins_short_branch(1);
9481 %}
9482
9483 // Compare signed long with zero and branch near instructions
9484 instruct cmpL_reg_imm0_branch(cmpOp cmp, iRegL op1, immL0 zero, label lbl)
9485 %{
9486 // Same match rule as `far_cmpL_reg_imm0_branch'.
9487 match(If cmp (CmpL op1 zero));
9488
9489 effect(USE op1, USE lbl);
9490
9491 ins_cost(BRANCH_COST);
9492
9493 format %{ "b$cmp $op1, zr, $lbl\t#@cmpL_reg_imm0_branch" %}
9494
9495 ins_encode %{
9496 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label));
9497 %}
9498
9499 ins_pipe(pipe_cmpz_branch);
9500 ins_short_branch(1);
9501 %}
9502
9503 instruct cmpL_reg_imm0_loop(cmpOp cmp, iRegL op1, immL0 zero, label lbl)
9504 %{
9505 // Same match rule as `far_cmpL_reg_imm0_loop'.
9506 match(CountedLoopEnd cmp (CmpL op1 zero));
9507
9508 effect(USE op1, USE lbl);
9509
9510 ins_cost(BRANCH_COST);
9511
9512 format %{ "b$cmp $op1, zr, $lbl\t#@cmpL_reg_imm0_loop" %}
9513
9514 ins_encode %{
9515 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label));
9516 %}
9517
9518 ins_pipe(pipe_cmpz_branch);
9519 ins_short_branch(1);
9520 %}
9521
9522 // Compare unsigned long with zero and branch near instructions
9523 instruct cmpULEqNeLeGt_reg_imm0_branch(cmpOpUEqNeLeGt cmp, iRegL op1, immL0 zero, label lbl)
9524 %{
9525 // Same match rule as `far_cmpULEqNeLeGt_reg_imm0_branch'.
9526 match(If cmp (CmpUL op1 zero));
9527
9528 effect(USE op1, USE lbl);
9529
9530 ins_cost(BRANCH_COST);
9531
9532 format %{ "b$cmp $op1, zr, $lbl\t#@cmpULEqNeLeGt_reg_imm0_branch" %}
9533
9534 ins_encode %{
9535 __ enc_cmpUEqNeLeGt_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
9536 %}
9537
9538 ins_pipe(pipe_cmpz_branch);
9539 ins_short_branch(1);
9540 %}
9541
9542 // Compare pointer with zero and branch near instructions
9543 instruct cmpP_imm0_branch(cmpOpEqNe cmp, iRegP op1, immP0 zero, label lbl) %{
9544 // Same match rule as `far_cmpP_reg_imm0_branch'.
9545 match(If cmp (CmpP op1 zero));
9546 effect(USE lbl);
9547
9548 ins_cost(BRANCH_COST);
9549 format %{ "b$cmp $op1, zr, $lbl\t#@cmpP_imm0_branch" %}
9550
9551 ins_encode %{
9552 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
9553 %}
9554
9555 ins_pipe(pipe_cmpz_branch);
9556 ins_short_branch(1);
9557 %}
9558
9559 // Compare narrow pointer with zero and branch near instructions
9560 instruct cmpN_imm0_branch(cmpOpEqNe cmp, iRegN op1, immN0 zero, label lbl) %{
9561 // Same match rule as `far_cmpN_reg_imm0_branch'.
9562 match(If cmp (CmpN op1 zero));
9563 effect(USE lbl);
9564
9565 ins_cost(BRANCH_COST);
9566
9567 format %{ "b$cmp $op1, zr, $lbl\t#@cmpN_imm0_branch" %}
9568
9569 ins_encode %{
9570 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
9571 %}
9572
9573 ins_pipe(pipe_cmpz_branch);
9574 ins_short_branch(1);
9575 %}
9576
9577 // Compare narrow pointer with pointer zero and branch near instructions
9578 instruct cmpP_narrowOop_imm0_branch(cmpOpEqNe cmp, iRegN op1, immP0 zero, label lbl) %{
9579 // Same match rule as `far_cmpP_narrowOop_imm0_branch'.
9580 match(If cmp (CmpP (DecodeN op1) zero));
9581 effect(USE lbl);
9582
9583 ins_cost(BRANCH_COST);
9584 format %{ "b$cmp $op1, zr, $lbl\t#@cmpP_narrowOop_imm0_branch" %}
9585
9586 ins_encode %{
9587 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
9588 %}
9589
9590 ins_pipe(pipe_cmpz_branch);
9591 ins_short_branch(1);
9592 %}
9593
9594 // Patterns for far (20KiB) variants
9595
9596 instruct far_cmpFlag_branch(cmpOp cmp, rFlagsReg cr, label lbl) %{
9597 match(If cmp cr);
9598 effect(USE lbl);
9599
9600 ins_cost(BRANCH_COST);
9601 format %{ "far_b$cmp $cr, zr, $lbl\t#@far_cmpFlag_branch"%}
9602
9603 ins_encode %{
9604 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($cr$$reg), *($lbl$$label), /* is_far */ true);
9605 %}
9606
9607 ins_pipe(pipe_cmpz_branch);
9608 %}
9609
9610 // Compare signed int and branch far instructions
9611 instruct far_cmpI_branch(cmpOp cmp, iRegI op1, iRegI op2, label lbl) %{
9612 match(If cmp (CmpI op1 op2));
9613 effect(USE lbl);
9614
9615 ins_cost(BRANCH_COST * 2);
9616
9617 // the format instruction [far_b$cmp] here is be used as two insructions
9618 // in macroassembler: b$not_cmp(op1, op2, done), j($lbl), bind(done)
9619 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpI_branch" %}
9620
9621 ins_encode %{
9622 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9623 %}
9624
9625 ins_pipe(pipe_cmp_branch);
9626 %}
9627
9628 instruct far_cmpI_loop(cmpOp cmp, iRegI op1, iRegI op2, label lbl) %{
9629 match(CountedLoopEnd cmp (CmpI op1 op2));
9630 effect(USE lbl);
9631
9632 ins_cost(BRANCH_COST * 2);
9633 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpI_loop" %}
9634
9635 ins_encode %{
9636 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9637 %}
9638
9639 ins_pipe(pipe_cmp_branch);
9640 %}
9641
9642 instruct far_cmpU_branch(cmpOpU cmp, iRegI op1, iRegI op2, label lbl) %{
9643 match(If cmp (CmpU op1 op2));
9644 effect(USE lbl);
9645
9646 ins_cost(BRANCH_COST * 2);
9647 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpU_branch" %}
9648
9649 ins_encode %{
9650 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9651 as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9652 %}
9653
9654 ins_pipe(pipe_cmp_branch);
9655 %}
9656
9657 instruct far_cmpL_branch(cmpOp cmp, iRegL op1, iRegL op2, label lbl) %{
9658 match(If cmp (CmpL op1 op2));
9659 effect(USE lbl);
9660
9661 ins_cost(BRANCH_COST * 2);
9662 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpL_branch" %}
9663
9664 ins_encode %{
9665 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9666 %}
9667
9668 ins_pipe(pipe_cmp_branch);
9669 %}
9670
9671 instruct far_cmpLloop(cmpOp cmp, iRegL op1, iRegL op2, label lbl) %{
9672 match(CountedLoopEnd cmp (CmpL op1 op2));
9673 effect(USE lbl);
9674
9675 ins_cost(BRANCH_COST * 2);
9676 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpL_loop" %}
9677
9678 ins_encode %{
9679 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9680 %}
9681
9682 ins_pipe(pipe_cmp_branch);
9683 %}
9684
9685 instruct far_cmpUL_branch(cmpOpU cmp, iRegL op1, iRegL op2, label lbl) %{
9686 match(If cmp (CmpUL op1 op2));
9687 effect(USE lbl);
9688
9689 ins_cost(BRANCH_COST * 2);
9690 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpUL_branch" %}
9691
9692 ins_encode %{
9693 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9694 as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9695 %}
9696
9697 ins_pipe(pipe_cmp_branch);
9698 %}
9699
9700 instruct far_cmpP_branch(cmpOpU cmp, iRegP op1, iRegP op2, label lbl)
9701 %{
9702 match(If cmp (CmpP op1 op2));
9703
9704 effect(USE lbl);
9705
9706 ins_cost(BRANCH_COST * 2);
9707
9708 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpP_branch" %}
9709
9710 ins_encode %{
9711 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9712 as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9713 %}
9714
9715 ins_pipe(pipe_cmp_branch);
9716 %}
9717
9718 instruct far_cmpN_branch(cmpOpU cmp, iRegN op1, iRegN op2, label lbl)
9719 %{
9720 match(If cmp (CmpN op1 op2));
9721
9722 effect(USE lbl);
9723
9724 ins_cost(BRANCH_COST * 2);
9725
9726 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpN_branch" %}
9727
9728 ins_encode %{
9729 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9730 as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9731 %}
9732
9733 ins_pipe(pipe_cmp_branch);
9734 %}
9735
9736 // Float compare and branch instructions
9737 instruct far_cmpF_branch(cmpOp cmp, fRegF op1, fRegF op2, label lbl)
9738 %{
9739 match(If cmp (CmpF op1 op2));
9740
9741 effect(USE lbl);
9742
9743 ins_cost(XFER_COST + BRANCH_COST * 2);
9744 format %{ "far_float_b$cmp $op1, $op2, $lbl\t#@far_cmpF_branch"%}
9745
9746 ins_encode %{
9747 __ float_cmp_branch($cmp$$cmpcode, as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg),
9748 *($lbl$$label), /* is_far */ true);
9749 %}
9750
9751 ins_pipe(pipe_class_compare);
9752 %}
9753
9754 // Double compare and branch instructions
9755 instruct far_cmpD_branch(cmpOp cmp, fRegD op1, fRegD op2, label lbl)
9756 %{
9757 match(If cmp (CmpD op1 op2));
9758 effect(USE lbl);
9759
9760 ins_cost(XFER_COST + BRANCH_COST * 2);
9761 format %{ "far_double_b$cmp $op1, $op2, $lbl\t#@far_cmpD_branch"%}
9762
9763 ins_encode %{
9764 __ float_cmp_branch($cmp$$cmpcode | C2_MacroAssembler::double_branch_mask, as_FloatRegister($op1$$reg),
9765 as_FloatRegister($op2$$reg), *($lbl$$label), /* is_far */ true);
9766 %}
9767
9768 ins_pipe(pipe_class_compare);
9769 %}
9770
9771 instruct far_cmpI_reg_imm0_branch(cmpOp cmp, iRegI op1, immI0 zero, label lbl)
9772 %{
9773 match(If cmp (CmpI op1 zero));
9774
9775 effect(USE op1, USE lbl);
9776
9777 ins_cost(BRANCH_COST * 2);
9778
9779 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpI_reg_imm0_branch" %}
9780
9781 ins_encode %{
9782 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label), /* is_far */ true);
9783 %}
9784
9785 ins_pipe(pipe_cmpz_branch);
9786 %}
9787
9788 instruct far_cmpI_reg_imm0_loop(cmpOp cmp, iRegI op1, immI0 zero, label lbl)
9789 %{
9790 match(CountedLoopEnd cmp (CmpI op1 zero));
9791
9792 effect(USE op1, USE lbl);
9793
9794 ins_cost(BRANCH_COST * 2);
9795
9796 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpI_reg_imm0_loop" %}
9797
9798 ins_encode %{
9799 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label), /* is_far */ true);
9800 %}
9801
9802 ins_pipe(pipe_cmpz_branch);
9803 %}
9804
9805 instruct far_cmpUEqNeLeGt_imm0_branch(cmpOpUEqNeLeGt cmp, iRegI op1, immI0 zero, label lbl)
9806 %{
9807 match(If cmp (CmpU op1 zero));
9808
9809 effect(USE op1, USE lbl);
9810
9811 ins_cost(BRANCH_COST * 2);
9812
9813 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpUEqNeLeGt_imm0_branch" %}
9814
9815 ins_encode %{
9816 __ enc_cmpUEqNeLeGt_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
9817 %}
9818
9819 ins_pipe(pipe_cmpz_branch);
9820 %}
9821
9822 // compare lt/ge unsigned instructs has no short instruct with same match
9823 instruct far_cmpULtGe_reg_imm0_branch(cmpOpULtGe cmp, iRegI op1, immI0 zero, label lbl)
9824 %{
9825 match(If cmp (CmpU op1 zero));
9826
9827 effect(USE op1, USE lbl);
9828
9829 ins_cost(BRANCH_COST);
9830
9831 format %{ "j $lbl if $cmp == ge\t#@far_cmpULtGe_reg_imm0_branch" %}
9832
9833 ins_encode(riscv_enc_far_cmpULtGe_imm0_branch(cmp, op1, lbl));
9834
9835 ins_pipe(pipe_cmpz_branch);
9836 %}
9837
9838 instruct far_cmpL_reg_imm0_branch(cmpOp cmp, iRegL op1, immL0 zero, label lbl)
9839 %{
9840 match(If cmp (CmpL op1 zero));
9841
9842 effect(USE op1, USE lbl);
9843
9844 ins_cost(BRANCH_COST * 2);
9845
9846 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpL_reg_imm0_branch" %}
9847
9848 ins_encode %{
9849 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label), /* is_far */ true);
9850 %}
9851
9852 ins_pipe(pipe_cmpz_branch);
9853 %}
9854
9855 instruct far_cmpL_reg_imm0_loop(cmpOp cmp, iRegL op1, immL0 zero, label lbl)
9856 %{
9857 match(CountedLoopEnd cmp (CmpL op1 zero));
9858
9859 effect(USE op1, USE lbl);
9860
9861 ins_cost(BRANCH_COST * 2);
9862
9863 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpL_reg_imm0_loop" %}
9864
9865 ins_encode %{
9866 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label), /* is_far */ true);
9867 %}
9868
9869 ins_pipe(pipe_cmpz_branch);
9870 %}
9871
9872 instruct far_cmpULEqNeLeGt_reg_imm0_branch(cmpOpUEqNeLeGt cmp, iRegL op1, immL0 zero, label lbl)
9873 %{
9874 match(If cmp (CmpUL op1 zero));
9875
9876 effect(USE op1, USE lbl);
9877
9878 ins_cost(BRANCH_COST * 2);
9879
9880 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpULEqNeLeGt_reg_imm0_branch" %}
9881
9882 ins_encode %{
9883 __ enc_cmpUEqNeLeGt_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
9884 %}
9885
9886 ins_pipe(pipe_cmpz_branch);
9887 %}
9888
9889 // compare lt/ge unsigned instructs has no short instruct with same match
9890 instruct far_cmpULLtGe_reg_imm0_branch(cmpOpULtGe cmp, iRegL op1, immL0 zero, label lbl)
9891 %{
9892 match(If cmp (CmpUL op1 zero));
9893
9894 effect(USE op1, USE lbl);
9895
9896 ins_cost(BRANCH_COST);
9897
9898 format %{ "j $lbl if $cmp == ge\t#@far_cmpULLtGe_reg_imm0_branch" %}
9899
9900 ins_encode(riscv_enc_far_cmpULtGe_imm0_branch(cmp, op1, lbl));
9901
9902 ins_pipe(pipe_cmpz_branch);
9903 %}
9904
9905 instruct far_cmpP_imm0_branch(cmpOpEqNe cmp, iRegP op1, immP0 zero, label lbl) %{
9906 match(If cmp (CmpP op1 zero));
9907 effect(USE lbl);
9908
9909 ins_cost(BRANCH_COST * 2);
9910 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpP_imm0_branch" %}
9911
9912 ins_encode %{
9913 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
9914 %}
9915
9916 ins_pipe(pipe_cmpz_branch);
9917 %}
9918
9919 instruct far_cmpN_imm0_branch(cmpOpEqNe cmp, iRegN op1, immN0 zero, label lbl) %{
9920 match(If cmp (CmpN op1 zero));
9921 effect(USE lbl);
9922
9923 ins_cost(BRANCH_COST * 2);
9924
9925 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpN_imm0_branch" %}
9926
9927 ins_encode %{
9928 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
9929 %}
9930
9931 ins_pipe(pipe_cmpz_branch);
9932 %}
9933
9934 instruct far_cmpP_narrowOop_imm0_branch(cmpOpEqNe cmp, iRegN op1, immP0 zero, label lbl) %{
9935 match(If cmp (CmpP (DecodeN op1) zero));
9936 effect(USE lbl);
9937
9938 ins_cost(BRANCH_COST * 2);
9939 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpP_narrowOop_imm0_branch" %}
9940
9941 ins_encode %{
9942 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
9943 %}
9944
9945 ins_pipe(pipe_cmpz_branch);
9946 %}
9947
9948 // ============================================================================
9949 // Conditional Move Instructions
9950
9951 // --------- CMoveI ---------
9952
9953 instruct cmovI_cmpI(iRegINoSp dst, iRegI src, iRegI op1, iRegI op2, cmpOp cop) %{
9954 match(Set dst (CMoveI (Binary cop (CmpI op1 op2)) (Binary dst src)));
9955 ins_cost(ALU_COST + BRANCH_COST);
9956
9957 format %{
9958 "CMoveI $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpI\n\t"
9959 %}
9960
9961 ins_encode %{
9962 __ enc_cmove($cop$$cmpcode,
9963 as_Register($op1$$reg), as_Register($op2$$reg),
9964 as_Register($dst$$reg), as_Register($src$$reg));
9965 %}
9966
9967 ins_pipe(pipe_class_compare);
9968 %}
9969
9970 instruct cmovI_cmpU(iRegINoSp dst, iRegI src, iRegI op1, iRegI op2, cmpOpU cop) %{
9971 match(Set dst (CMoveI (Binary cop (CmpU op1 op2)) (Binary dst src)));
9972 ins_cost(ALU_COST + BRANCH_COST);
9973
9974 format %{
9975 "CMoveI $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpU\n\t"
9976 %}
9977
9978 ins_encode %{
9979 __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
9980 as_Register($op1$$reg), as_Register($op2$$reg),
9981 as_Register($dst$$reg), as_Register($src$$reg));
9982 %}
9983
9984 ins_pipe(pipe_class_compare);
9985 %}
9986
9987 instruct cmovI_cmpL(iRegINoSp dst, iRegI src, iRegL op1, iRegL op2, cmpOp cop) %{
9988 match(Set dst (CMoveI (Binary cop (CmpL op1 op2)) (Binary dst src)));
9989 ins_cost(ALU_COST + BRANCH_COST);
9990
9991 format %{
9992 "CMoveI $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpL\n\t"
9993 %}
9994
9995 ins_encode %{
9996 __ enc_cmove($cop$$cmpcode,
9997 as_Register($op1$$reg), as_Register($op2$$reg),
9998 as_Register($dst$$reg), as_Register($src$$reg));
9999 %}
10000
10001 ins_pipe(pipe_class_compare);
10002 %}
10003
10004 instruct cmovI_cmpUL(iRegINoSp dst, iRegI src, iRegL op1, iRegL op2, cmpOpU cop) %{
10005 match(Set dst (CMoveI (Binary cop (CmpUL op1 op2)) (Binary dst src)));
10006 ins_cost(ALU_COST + BRANCH_COST);
10007
10008 format %{
10009 "CMoveI $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpUL\n\t"
10010 %}
10011
10012 ins_encode %{
10013 __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10014 as_Register($op1$$reg), as_Register($op2$$reg),
10015 as_Register($dst$$reg), as_Register($src$$reg));
10016 %}
10017
10018 ins_pipe(pipe_class_compare);
10019 %}
10020
10021 instruct cmovI_cmpF(iRegINoSp dst, iRegI src, fRegF op1, fRegF op2, cmpOp cop) %{
10022 match(Set dst (CMoveI (Binary cop (CmpF op1 op2)) (Binary dst src)));
10023 ins_cost(ALU_COST + BRANCH_COST);
10024
10025 format %{
10026 "CMoveI $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpF\n\t"
10027 %}
10028
10029 ins_encode %{
10030 __ enc_cmove_cmp_fp($cop$$cmpcode,
10031 as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg),
10032 as_Register($dst$$reg), as_Register($src$$reg), true /* is_single */);
10033 %}
10034
10035 ins_pipe(pipe_class_compare);
10036 %}
10037
10038 instruct cmovI_cmpD(iRegINoSp dst, iRegI src, fRegD op1, fRegD op2, cmpOp cop) %{
10039 match(Set dst (CMoveI (Binary cop (CmpD op1 op2)) (Binary dst src)));
10040 ins_cost(ALU_COST + BRANCH_COST);
10041
10042 format %{
10043 "CMoveI $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpD\n\t"
10044 %}
10045
10046 ins_encode %{
10047 __ enc_cmove_cmp_fp($cop$$cmpcode | C2_MacroAssembler::double_branch_mask,
10048 as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg),
10049 as_Register($dst$$reg), as_Register($src$$reg), false /* is_single */);
10050 %}
10051
10052 ins_pipe(pipe_class_compare);
10053 %}
10054
10055 instruct cmovI_cmpN(iRegINoSp dst, iRegI src, iRegN op1, iRegN op2, cmpOpU cop) %{
10056 match(Set dst (CMoveI (Binary cop (CmpN op1 op2)) (Binary dst src)));
10057 ins_cost(ALU_COST + BRANCH_COST);
10058
10059 format %{
10060 "CMoveI $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpN\n\t"
10061 %}
10062
10063 ins_encode %{
10064 __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10065 as_Register($op1$$reg), as_Register($op2$$reg),
10066 as_Register($dst$$reg), as_Register($src$$reg));
10067 %}
10068
10069 ins_pipe(pipe_class_compare);
10070 %}
10071
10072 instruct cmovI_cmpP(iRegINoSp dst, iRegI src, iRegP op1, iRegP op2, cmpOpU cop) %{
10073 match(Set dst (CMoveI (Binary cop (CmpP op1 op2)) (Binary dst src)));
10074 ins_cost(ALU_COST + BRANCH_COST);
10075
10076 format %{
10077 "CMoveI $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpP\n\t"
10078 %}
10079
10080 ins_encode %{
10081 __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10082 as_Register($op1$$reg), as_Register($op2$$reg),
10083 as_Register($dst$$reg), as_Register($src$$reg));
10084 %}
10085
10086 ins_pipe(pipe_class_compare);
10087 %}
10088
10089 // --------- CMoveL ---------
10090
10091 instruct cmovL_cmpL(iRegLNoSp dst, iRegL src, iRegL op1, iRegL op2, cmpOp cop) %{
10092 match(Set dst (CMoveL (Binary cop (CmpL op1 op2)) (Binary dst src)));
10093 ins_cost(ALU_COST + BRANCH_COST);
10094
10095 format %{
10096 "CMoveL $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpL\n\t"
10097 %}
10098
10099 ins_encode %{
10100 __ enc_cmove($cop$$cmpcode,
10101 as_Register($op1$$reg), as_Register($op2$$reg),
10102 as_Register($dst$$reg), as_Register($src$$reg));
10103 %}
10104
10105 ins_pipe(pipe_class_compare);
10106 %}
10107
10108 instruct cmovL_cmpUL(iRegLNoSp dst, iRegL src, iRegL op1, iRegL op2, cmpOpU cop) %{
10109 match(Set dst (CMoveL (Binary cop (CmpUL op1 op2)) (Binary dst src)));
10110 ins_cost(ALU_COST + BRANCH_COST);
10111
10112 format %{
10113 "CMoveL $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpUL\n\t"
10114 %}
10115
10116 ins_encode %{
10117 __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10118 as_Register($op1$$reg), as_Register($op2$$reg),
10119 as_Register($dst$$reg), as_Register($src$$reg));
10120 %}
10121
10122 ins_pipe(pipe_class_compare);
10123 %}
10124
10125 instruct cmovL_cmpI(iRegLNoSp dst, iRegL src, iRegI op1, iRegI op2, cmpOp cop) %{
10126 match(Set dst (CMoveL (Binary cop (CmpI op1 op2)) (Binary dst src)));
10127 ins_cost(ALU_COST + BRANCH_COST);
10128
10129 format %{
10130 "CMoveL $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpI\n\t"
10131 %}
10132
10133 ins_encode %{
10134 __ enc_cmove($cop$$cmpcode,
10135 as_Register($op1$$reg), as_Register($op2$$reg),
10136 as_Register($dst$$reg), as_Register($src$$reg));
10137 %}
10138
10139 ins_pipe(pipe_class_compare);
10140 %}
10141
10142 instruct cmovL_cmpU(iRegLNoSp dst, iRegL src, iRegI op1, iRegI op2, cmpOpU cop) %{
10143 match(Set dst (CMoveL (Binary cop (CmpU op1 op2)) (Binary dst src)));
10144 ins_cost(ALU_COST + BRANCH_COST);
10145
10146 format %{
10147 "CMoveL $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpU\n\t"
10148 %}
10149
10150 ins_encode %{
10151 __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10152 as_Register($op1$$reg), as_Register($op2$$reg),
10153 as_Register($dst$$reg), as_Register($src$$reg));
10154 %}
10155
10156 ins_pipe(pipe_class_compare);
10157 %}
10158
10159 instruct cmovL_cmpF(iRegLNoSp dst, iRegL src, fRegF op1, fRegF op2, cmpOp cop) %{
10160 match(Set dst (CMoveL (Binary cop (CmpF op1 op2)) (Binary dst src)));
10161 ins_cost(ALU_COST + BRANCH_COST);
10162
10163 format %{
10164 "CMoveL $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpF\n\t"
10165 %}
10166
10167 ins_encode %{
10168 __ enc_cmove_cmp_fp($cop$$cmpcode,
10169 as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg),
10170 as_Register($dst$$reg), as_Register($src$$reg), true /* is_single */);
10171 %}
10172
10173 ins_pipe(pipe_class_compare);
10174 %}
10175
10176 instruct cmovL_cmpD(iRegLNoSp dst, iRegL src, fRegD op1, fRegD op2, cmpOp cop) %{
10177 match(Set dst (CMoveL (Binary cop (CmpD op1 op2)) (Binary dst src)));
10178 ins_cost(ALU_COST + BRANCH_COST);
10179
10180 format %{
10181 "CMoveL $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpD\n\t"
10182 %}
10183
10184 ins_encode %{
10185 __ enc_cmove_cmp_fp($cop$$cmpcode | C2_MacroAssembler::double_branch_mask,
10186 as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg),
10187 as_Register($dst$$reg), as_Register($src$$reg), false /* is_single */);
10188 %}
10189
10190 ins_pipe(pipe_class_compare);
10191 %}
10192
10193 instruct cmovL_cmpN(iRegLNoSp dst, iRegL src, iRegN op1, iRegN op2, cmpOpU cop) %{
10194 match(Set dst (CMoveL (Binary cop (CmpN op1 op2)) (Binary dst src)));
10195 ins_cost(ALU_COST + BRANCH_COST);
10196
10197 format %{
10198 "CMoveL $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpN\n\t"
10199 %}
10200
10201 ins_encode %{
10202 __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10203 as_Register($op1$$reg), as_Register($op2$$reg),
10204 as_Register($dst$$reg), as_Register($src$$reg));
10205 %}
10206
10207 ins_pipe(pipe_class_compare);
10208 %}
10209
10210 instruct cmovL_cmpP(iRegLNoSp dst, iRegL src, iRegP op1, iRegP op2, cmpOpU cop) %{
10211 match(Set dst (CMoveL (Binary cop (CmpP op1 op2)) (Binary dst src)));
10212 ins_cost(ALU_COST + BRANCH_COST);
10213
10214 format %{
10215 "CMoveL $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpP\n\t"
10216 %}
10217
10218 ins_encode %{
10219 __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10220 as_Register($op1$$reg), as_Register($op2$$reg),
10221 as_Register($dst$$reg), as_Register($src$$reg));
10222 %}
10223
10224 ins_pipe(pipe_class_compare);
10225 %}
10226
10227 // ============================================================================
10228 // Procedure Call/Return Instructions
10229
10230 // Call Java Static Instruction
10231 // Note: If this code changes, the corresponding ret_addr_offset() and
10232 // compute_padding() functions will have to be adjusted.
10233 instruct CallStaticJavaDirect(method meth)
10234 %{
10235 match(CallStaticJava);
10236
10237 effect(USE meth);
10238
10239 ins_cost(BRANCH_COST);
10240
10241 format %{ "CALL,static $meth\t#@CallStaticJavaDirect" %}
10242
10243 ins_encode(riscv_enc_java_static_call(meth),
10244 riscv_enc_call_epilog);
10245
10246 ins_pipe(pipe_class_call);
10247 ins_alignment(4);
10248 %}
10249
10250 // TO HERE
10251
10252 // Call Java Dynamic Instruction
10253 // Note: If this code changes, the corresponding ret_addr_offset() and
10254 // compute_padding() functions will have to be adjusted.
10255 instruct CallDynamicJavaDirect(method meth)
10256 %{
10257 match(CallDynamicJava);
10258
10259 effect(USE meth);
10260
10261 ins_cost(BRANCH_COST + ALU_COST * 5);
10262
10263 format %{ "CALL,dynamic $meth\t#@CallDynamicJavaDirect" %}
10264
10265 ins_encode(riscv_enc_java_dynamic_call(meth),
10266 riscv_enc_call_epilog);
10267
10268 ins_pipe(pipe_class_call);
10269 ins_alignment(4);
10270 %}
10271
10272 // Call Runtime Instruction
10273
10274 instruct CallRuntimeDirect(method meth)
10275 %{
10276 match(CallRuntime);
10277
10278 effect(USE meth);
10279
10280 ins_cost(BRANCH_COST);
10281
10282 format %{ "CALL, runtime $meth\t#@CallRuntimeDirect" %}
10283
10284 ins_encode(riscv_enc_java_to_runtime(meth));
10285
10286 ins_pipe(pipe_class_call);
10287 %}
10288
10289 // Call Runtime Instruction
10290
10291 instruct CallLeafDirect(method meth)
10292 %{
10293 match(CallLeaf);
10294
10295 effect(USE meth);
10296
10297 ins_cost(BRANCH_COST);
10298
10299 format %{ "CALL, runtime leaf $meth\t#@CallLeafDirect" %}
10300
10301 ins_encode(riscv_enc_java_to_runtime(meth));
10302
10303 ins_pipe(pipe_class_call);
10304 %}
10305
10306 // Call Runtime Instruction without safepoint and with vector arguments
10307
10308 instruct CallLeafDirectVector(method meth)
10309 %{
10310 match(CallLeafVector);
10311
10312 effect(USE meth);
10313
10314 ins_cost(BRANCH_COST);
10315
10316 format %{ "CALL, runtime leaf vector $meth" %}
10317
10318 ins_encode(riscv_enc_java_to_runtime(meth));
10319
10320 ins_pipe(pipe_class_call);
10321 %}
10322
10323 // Call Runtime Instruction
10324
10325 instruct CallLeafNoFPDirect(method meth)
10326 %{
10327 match(CallLeafNoFP);
10328
10329 effect(USE meth);
10330
10331 ins_cost(BRANCH_COST);
10332
10333 format %{ "CALL, runtime leaf nofp $meth\t#@CallLeafNoFPDirect" %}
10334
10335 ins_encode(riscv_enc_java_to_runtime(meth));
10336
10337 ins_pipe(pipe_class_call);
10338 %}
10339
10340 // ============================================================================
10341 // Partial Subtype Check
10342 //
10343 // superklass array for an instance of the superklass. Set a hidden
10344 // internal cache on a hit (cache is checked with exposed code in
10345 // gen_subtype_check()). Return zero for a hit. The encoding
10346 // ALSO sets flags.
10347
10348 instruct partialSubtypeCheck(iRegP_R15 result, iRegP_R14 sub, iRegP_R10 super, iRegP_R12 tmp, rFlagsReg cr)
10349 %{
10350 predicate(!UseSecondarySupersTable);
10351 match(Set result (PartialSubtypeCheck sub super));
10352 effect(KILL tmp, KILL cr);
10353
10354 ins_cost(20 * DEFAULT_COST);
10355 format %{ "partialSubtypeCheck $result, $sub, $super\t#@partialSubtypeCheck" %}
10356
10357 ins_encode(riscv_enc_partial_subtype_check(sub, super, tmp, result));
10358
10359 opcode(0x1); // Force zero of result reg on hit
10360
10361 ins_pipe(pipe_class_memory);
10362 %}
10363
10364 // Two versions of partialSubtypeCheck, both used when we need to
10365 // search for a super class in the secondary supers array. The first
10366 // is used when we don't know _a priori_ the class being searched
10367 // for. The second, far more common, is used when we do know: this is
10368 // used for instanceof, checkcast, and any case where C2 can determine
10369 // it by constant propagation.
10370
10371 instruct partialSubtypeCheckVarSuper(iRegP_R14 sub, iRegP_R10 super, iRegP_R15 result,
10372 iRegP_R11 tmpR11, iRegP_R12 tmpR12, iRegP_R13 tmpR13,
10373 iRegP_R16 tmpR16, rFlagsReg cr)
10374 %{
10375 predicate(UseSecondarySupersTable);
10376 match(Set result (PartialSubtypeCheck sub super));
10377 effect(TEMP tmpR11, TEMP tmpR12, TEMP tmpR13, TEMP tmpR16, KILL cr);
10378
10379 ins_cost(10 * DEFAULT_COST); // slightly larger than the next version
10380 format %{ "partialSubtypeCheck $result, $sub, $super" %}
10381
10382 ins_encode %{
10383 __ lookup_secondary_supers_table_var($sub$$Register, $super$$Register, $result$$Register,
10384 $tmpR11$$Register, $tmpR12$$Register, $tmpR13$$Register,
10385 $tmpR16$$Register, nullptr /*L_success*/);
10386 %}
10387
10388 ins_pipe(pipe_class_memory);
10389 %}
10390
10391 instruct partialSubtypeCheckConstSuper(iRegP_R14 sub, iRegP_R10 super_reg, immP super_con, iRegP_R15 result,
10392 iRegP_R11 tmpR11, iRegP_R12 tmpR12, iRegP_R13 tmpR13, iRegP_R16 tmpR16, rFlagsReg cr)
10393 %{
10394 predicate(UseSecondarySupersTable);
10395 match(Set result (PartialSubtypeCheck sub (Binary super_reg super_con)));
10396 effect(TEMP tmpR11, TEMP tmpR12, TEMP tmpR13, TEMP tmpR16, KILL cr);
10397
10398 ins_cost(5 * DEFAULT_COST); // needs to be less than competing nodes
10399 format %{ "partialSubtypeCheck $result, $sub, $super_reg, $super_con" %}
10400
10401 ins_encode %{
10402 bool success = false;
10403 u1 super_klass_slot = ((Klass*)$super_con$$constant)->hash_slot();
10404 if (InlineSecondarySupersTest) {
10405 success = __ lookup_secondary_supers_table_const($sub$$Register, $super_reg$$Register, $result$$Register,
10406 $tmpR11$$Register, $tmpR12$$Register, $tmpR13$$Register,
10407 $tmpR16$$Register, super_klass_slot);
10408 } else {
10409 address call = __ reloc_call(RuntimeAddress(StubRoutines::lookup_secondary_supers_table_stub(super_klass_slot)));
10410 success = (call != nullptr);
10411 }
10412 if (!success) {
10413 ciEnv::current()->record_failure("CodeCache is full");
10414 return;
10415 }
10416 %}
10417
10418 ins_pipe(pipe_class_memory);
10419 %}
10420
10421 instruct string_compareU(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
10422 iRegI_R10 result, iRegP_R28 tmp1, iRegL_R29 tmp2, iRegL_R30 tmp3, rFlagsReg cr)
10423 %{
10424 predicate(!UseRVV && ((StrCompNode *)n)->encoding() == StrIntrinsicNode::UU);
10425 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10426 effect(KILL tmp1, KILL tmp2, KILL tmp3, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
10427
10428 format %{ "String Compare $str1, $cnt1, $str2, $cnt2 -> $result\t#@string_compareU" %}
10429 ins_encode %{
10430 // Count is in 8-bit bytes; non-Compact chars are 16 bits.
10431 __ string_compare($str1$$Register, $str2$$Register,
10432 $cnt1$$Register, $cnt2$$Register, $result$$Register,
10433 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
10434 StrIntrinsicNode::UU);
10435 %}
10436 ins_pipe(pipe_class_memory);
10437 %}
10438
10439 instruct string_compareL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
10440 iRegI_R10 result, iRegP_R28 tmp1, iRegL_R29 tmp2, iRegL_R30 tmp3, rFlagsReg cr)
10441 %{
10442 predicate(!UseRVV && ((StrCompNode *)n)->encoding() == StrIntrinsicNode::LL);
10443 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10444 effect(KILL tmp1, KILL tmp2, KILL tmp3, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
10445
10446 format %{ "String Compare $str1, $cnt1, $str2, $cnt2 -> $result\t#@string_compareL" %}
10447 ins_encode %{
10448 __ string_compare($str1$$Register, $str2$$Register,
10449 $cnt1$$Register, $cnt2$$Register, $result$$Register,
10450 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
10451 StrIntrinsicNode::LL);
10452 %}
10453 ins_pipe(pipe_class_memory);
10454 %}
10455
10456 instruct string_compareUL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
10457 iRegI_R10 result, iRegP_R28 tmp1, iRegL_R29 tmp2, iRegL_R30 tmp3, rFlagsReg cr)
10458 %{
10459 predicate(!UseRVV && ((StrCompNode *)n)->encoding() == StrIntrinsicNode::UL);
10460 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10461 effect(KILL tmp1, KILL tmp2, KILL tmp3, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
10462
10463 format %{"String Compare $str1, $cnt1, $str2, $cnt2 -> $result\t#@string_compareUL" %}
10464 ins_encode %{
10465 __ string_compare($str1$$Register, $str2$$Register,
10466 $cnt1$$Register, $cnt2$$Register, $result$$Register,
10467 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
10468 StrIntrinsicNode::UL);
10469 %}
10470 ins_pipe(pipe_class_memory);
10471 %}
10472
10473 instruct string_compareLU(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
10474 iRegI_R10 result, iRegP_R28 tmp1, iRegL_R29 tmp2, iRegL_R30 tmp3,
10475 rFlagsReg cr)
10476 %{
10477 predicate(!UseRVV && ((StrCompNode *)n)->encoding() == StrIntrinsicNode::LU);
10478 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10479 effect(KILL tmp1, KILL tmp2, KILL tmp3, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
10480
10481 format %{ "String Compare $str1, $cnt1, $str2, $cnt2 -> $result\t#@string_compareLU" %}
10482 ins_encode %{
10483 __ string_compare($str1$$Register, $str2$$Register,
10484 $cnt1$$Register, $cnt2$$Register, $result$$Register,
10485 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
10486 StrIntrinsicNode::LU);
10487 %}
10488 ins_pipe(pipe_class_memory);
10489 %}
10490
10491 instruct string_indexofUU(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
10492 iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3,
10493 iRegINoSp tmp4, iRegINoSp tmp5, iRegINoSp tmp6, rFlagsReg cr)
10494 %{
10495 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU);
10496 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
10497 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, TEMP_DEF result,
10498 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, TEMP tmp6, KILL cr);
10499
10500 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result (UU)" %}
10501 ins_encode %{
10502 __ string_indexof($str1$$Register, $str2$$Register,
10503 $cnt1$$Register, $cnt2$$Register,
10504 $tmp1$$Register, $tmp2$$Register,
10505 $tmp3$$Register, $tmp4$$Register,
10506 $tmp5$$Register, $tmp6$$Register,
10507 $result$$Register, StrIntrinsicNode::UU);
10508 %}
10509 ins_pipe(pipe_class_memory);
10510 %}
10511
10512 instruct string_indexofLL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
10513 iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3,
10514 iRegINoSp tmp4, iRegINoSp tmp5, iRegINoSp tmp6, rFlagsReg cr)
10515 %{
10516 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL);
10517 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
10518 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, TEMP_DEF result,
10519 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, TEMP tmp6, KILL cr);
10520
10521 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result (LL)" %}
10522 ins_encode %{
10523 __ string_indexof($str1$$Register, $str2$$Register,
10524 $cnt1$$Register, $cnt2$$Register,
10525 $tmp1$$Register, $tmp2$$Register,
10526 $tmp3$$Register, $tmp4$$Register,
10527 $tmp5$$Register, $tmp6$$Register,
10528 $result$$Register, StrIntrinsicNode::LL);
10529 %}
10530 ins_pipe(pipe_class_memory);
10531 %}
10532
10533 instruct string_indexofUL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
10534 iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3,
10535 iRegINoSp tmp4, iRegINoSp tmp5, iRegINoSp tmp6, rFlagsReg cr)
10536 %{
10537 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL);
10538 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
10539 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, TEMP_DEF result,
10540 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, TEMP tmp6, KILL cr);
10541 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result (UL)" %}
10542
10543 ins_encode %{
10544 __ string_indexof($str1$$Register, $str2$$Register,
10545 $cnt1$$Register, $cnt2$$Register,
10546 $tmp1$$Register, $tmp2$$Register,
10547 $tmp3$$Register, $tmp4$$Register,
10548 $tmp5$$Register, $tmp6$$Register,
10549 $result$$Register, StrIntrinsicNode::UL);
10550 %}
10551 ins_pipe(pipe_class_memory);
10552 %}
10553
10554 instruct string_indexof_conUU(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2,
10555 immI_le_4 int_cnt2, iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2,
10556 iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
10557 %{
10558 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU);
10559 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
10560 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, TEMP_DEF result,
10561 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
10562
10563 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result (UU)" %}
10564
10565 ins_encode %{
10566 int icnt2 = (int)$int_cnt2$$constant;
10567 __ string_indexof_linearscan($str1$$Register, $str2$$Register,
10568 $cnt1$$Register, zr,
10569 $tmp1$$Register, $tmp2$$Register,
10570 $tmp3$$Register, $tmp4$$Register,
10571 icnt2, $result$$Register, StrIntrinsicNode::UU);
10572 %}
10573 ins_pipe(pipe_class_memory);
10574 %}
10575
10576 instruct string_indexof_conLL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2,
10577 immI_le_4 int_cnt2, iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2,
10578 iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
10579 %{
10580 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL);
10581 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
10582 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, TEMP_DEF result,
10583 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
10584
10585 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result (LL)" %}
10586 ins_encode %{
10587 int icnt2 = (int)$int_cnt2$$constant;
10588 __ string_indexof_linearscan($str1$$Register, $str2$$Register,
10589 $cnt1$$Register, zr,
10590 $tmp1$$Register, $tmp2$$Register,
10591 $tmp3$$Register, $tmp4$$Register,
10592 icnt2, $result$$Register, StrIntrinsicNode::LL);
10593 %}
10594 ins_pipe(pipe_class_memory);
10595 %}
10596
10597 instruct string_indexof_conUL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2,
10598 immI_1 int_cnt2, iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2,
10599 iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
10600 %{
10601 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL);
10602 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
10603 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, TEMP_DEF result,
10604 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
10605
10606 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result (UL)" %}
10607 ins_encode %{
10608 int icnt2 = (int)$int_cnt2$$constant;
10609 __ string_indexof_linearscan($str1$$Register, $str2$$Register,
10610 $cnt1$$Register, zr,
10611 $tmp1$$Register, $tmp2$$Register,
10612 $tmp3$$Register, $tmp4$$Register,
10613 icnt2, $result$$Register, StrIntrinsicNode::UL);
10614 %}
10615 ins_pipe(pipe_class_memory);
10616 %}
10617
10618 instruct stringU_indexof_char(iRegP_R11 str1, iRegI_R12 cnt1, iRegI_R13 ch,
10619 iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2,
10620 iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
10621 %{
10622 match(Set result (StrIndexOfChar (Binary str1 cnt1) ch));
10623 predicate(!UseRVV && (((StrIndexOfCharNode*)n)->encoding() == StrIntrinsicNode::U));
10624 effect(USE_KILL str1, USE_KILL cnt1, USE_KILL ch, TEMP_DEF result,
10625 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
10626
10627 format %{ "StringUTF16 IndexOf char[] $str1, $cnt1, $ch -> $result" %}
10628 ins_encode %{
10629 __ string_indexof_char($str1$$Register, $cnt1$$Register, $ch$$Register,
10630 $result$$Register, $tmp1$$Register, $tmp2$$Register,
10631 $tmp3$$Register, $tmp4$$Register, false /* isU */);
10632 %}
10633 ins_pipe(pipe_class_memory);
10634 %}
10635
10636
10637 instruct stringL_indexof_char(iRegP_R11 str1, iRegI_R12 cnt1, iRegI_R13 ch,
10638 iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2,
10639 iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
10640 %{
10641 match(Set result (StrIndexOfChar (Binary str1 cnt1) ch));
10642 predicate(!UseRVV && (((StrIndexOfCharNode*)n)->encoding() == StrIntrinsicNode::L));
10643 effect(USE_KILL str1, USE_KILL cnt1, USE_KILL ch, TEMP_DEF result,
10644 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
10645
10646 format %{ "StringLatin1 IndexOf char[] $str1, $cnt1, $ch -> $result" %}
10647 ins_encode %{
10648 __ string_indexof_char($str1$$Register, $cnt1$$Register, $ch$$Register,
10649 $result$$Register, $tmp1$$Register, $tmp2$$Register,
10650 $tmp3$$Register, $tmp4$$Register, true /* isL */);
10651 %}
10652 ins_pipe(pipe_class_memory);
10653 %}
10654
10655 // clearing of an array
10656 instruct clearArray_reg_reg(iRegL_R29 cnt, iRegP_R28 base, iRegP_R30 tmp1,
10657 iRegP_R31 tmp2, rFlagsReg cr, Universe dummy)
10658 %{
10659 // temp registers must match the one used in StubGenerator::generate_zero_blocks()
10660 predicate(UseBlockZeroing || !UseRVV);
10661 match(Set dummy (ClearArray cnt base));
10662 effect(USE_KILL cnt, USE_KILL base, TEMP tmp1, TEMP tmp2, KILL cr);
10663
10664 ins_cost(4 * DEFAULT_COST);
10665 format %{ "ClearArray $cnt, $base\t#@clearArray_reg_reg" %}
10666
10667 ins_encode %{
10668 address tpc = __ zero_words($base$$Register, $cnt$$Register);
10669 if (tpc == nullptr) {
10670 ciEnv::current()->record_failure("CodeCache is full");
10671 return;
10672 }
10673 %}
10674
10675 ins_pipe(pipe_class_memory);
10676 %}
10677
10678 instruct clearArray_imm_reg(immL cnt, iRegP_R28 base, Universe dummy, rFlagsReg cr)
10679 %{
10680 predicate(!UseRVV && (uint64_t)n->in(2)->get_long()
10681 < (uint64_t)(BlockZeroingLowLimit >> LogBytesPerWord));
10682 match(Set dummy (ClearArray cnt base));
10683 effect(USE_KILL base, KILL cr);
10684
10685 ins_cost(4 * DEFAULT_COST);
10686 format %{ "ClearArray $cnt, $base\t#@clearArray_imm_reg" %}
10687
10688 ins_encode %{
10689 __ zero_words($base$$Register, (uint64_t)$cnt$$constant);
10690 %}
10691
10692 ins_pipe(pipe_class_memory);
10693 %}
10694
10695 instruct string_equalsL(iRegP_R11 str1, iRegP_R13 str2, iRegI_R14 cnt,
10696 iRegI_R10 result, rFlagsReg cr)
10697 %{
10698 predicate(!UseRVV && ((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::LL);
10699 match(Set result (StrEquals (Binary str1 str2) cnt));
10700 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL cr);
10701
10702 format %{ "String Equals $str1, $str2, $cnt -> $result\t#@string_equalsL" %}
10703 ins_encode %{
10704 // Count is in 8-bit bytes; non-Compact chars are 16 bits.
10705 __ string_equals($str1$$Register, $str2$$Register,
10706 $result$$Register, $cnt$$Register);
10707 %}
10708 ins_pipe(pipe_class_memory);
10709 %}
10710
10711 instruct array_equalsB(iRegP_R11 ary1, iRegP_R12 ary2, iRegI_R10 result,
10712 iRegP_R13 tmp1, iRegP_R14 tmp2, iRegP_R15 tmp3)
10713 %{
10714 predicate(!UseRVV && ((AryEqNode*)n)->encoding() == StrIntrinsicNode::LL);
10715 match(Set result (AryEq ary1 ary2));
10716 effect(USE_KILL ary1, USE_KILL ary2, TEMP tmp1, TEMP tmp2, TEMP tmp3);
10717
10718 format %{ "Array Equals $ary1, $ary2 -> $result\t#@array_equalsB // KILL all" %}
10719 ins_encode %{
10720 __ arrays_equals($ary1$$Register, $ary2$$Register,
10721 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
10722 $result$$Register, 1);
10723 %}
10724 ins_pipe(pipe_class_memory);
10725 %}
10726
10727 instruct array_equalsC(iRegP_R11 ary1, iRegP_R12 ary2, iRegI_R10 result,
10728 iRegP_R13 tmp1, iRegP_R14 tmp2, iRegP_R15 tmp3)
10729 %{
10730 predicate(!UseRVV && ((AryEqNode*)n)->encoding() == StrIntrinsicNode::UU);
10731 match(Set result (AryEq ary1 ary2));
10732 effect(USE_KILL ary1, USE_KILL ary2, TEMP tmp1, TEMP tmp2, TEMP tmp3);
10733
10734 format %{ "Array Equals $ary1, $ary2 -> $result\t#@array_equalsC // KILL all" %}
10735 ins_encode %{
10736 __ arrays_equals($ary1$$Register, $ary2$$Register,
10737 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
10738 $result$$Register, 2);
10739 %}
10740 ins_pipe(pipe_class_memory);
10741 %}
10742
10743 // fast ArraysSupport.vectorizedHashCode
10744 instruct arrays_hashcode(iRegP_R11 ary, iRegI_R12 cnt, iRegI_R10 result, immI basic_type,
10745 iRegLNoSp tmp1, iRegLNoSp tmp2,
10746 iRegLNoSp tmp3, iRegLNoSp tmp4,
10747 iRegLNoSp tmp5, iRegLNoSp tmp6, rFlagsReg cr)
10748 %{
10749 match(Set result (VectorizedHashCode (Binary ary cnt) (Binary result basic_type)));
10750 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, TEMP tmp6,
10751 USE_KILL ary, USE_KILL cnt, USE basic_type, KILL cr);
10752
10753 format %{ "Array HashCode array[] $ary,$cnt,$result,$basic_type -> $result // KILL all" %}
10754 ins_encode %{
10755 __ arrays_hashcode($ary$$Register, $cnt$$Register, $result$$Register,
10756 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
10757 $tmp4$$Register, $tmp5$$Register, $tmp6$$Register,
10758 (BasicType)$basic_type$$constant);
10759 %}
10760 ins_pipe(pipe_class_memory);
10761 %}
10762
10763 // ============================================================================
10764 // Safepoint Instructions
10765
10766 instruct safePoint(iRegP poll)
10767 %{
10768 match(SafePoint poll);
10769
10770 ins_cost(2 * LOAD_COST);
10771 format %{
10772 "lwu zr, [$poll]\t# Safepoint: poll for GC, #@safePoint"
10773 %}
10774 ins_encode %{
10775 __ read_polling_page(as_Register($poll$$reg), 0, relocInfo::poll_type);
10776 %}
10777 ins_pipe(pipe_serial); // ins_pipe(iload_reg_mem);
10778 %}
10779
10780 // ============================================================================
10781 // This name is KNOWN by the ADLC and cannot be changed.
10782 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
10783 // for this guy.
10784 instruct tlsLoadP(javaThread_RegP dst)
10785 %{
10786 match(Set dst (ThreadLocal));
10787
10788 ins_cost(0);
10789
10790 format %{ " -- \t// $dst=Thread::current(), empty, #@tlsLoadP" %}
10791
10792 size(0);
10793
10794 ins_encode( /*empty*/ );
10795
10796 ins_pipe(pipe_class_empty);
10797 %}
10798
10799 // inlined locking and unlocking
10800 // using t1 as the 'flag' register to bridge the BoolNode producers and consumers
10801 instruct cmpFastLock(rFlagsReg cr, iRegP object, iRegP box,
10802 iRegPNoSp tmp1, iRegPNoSp tmp2, iRegPNoSp tmp3, iRegPNoSp tmp4)
10803 %{
10804 predicate(LockingMode != LM_LIGHTWEIGHT);
10805 match(Set cr (FastLock object box));
10806 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4);
10807
10808 ins_cost(10 * DEFAULT_COST);
10809 format %{ "fastlock $object,$box\t! kills $tmp1,$tmp2,$tmp3,$tmp4 #@cmpFastLock" %}
10810
10811 ins_encode %{
10812 __ fast_lock($object$$Register, $box$$Register,
10813 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register);
10814 %}
10815
10816 ins_pipe(pipe_serial);
10817 %}
10818
10819 // using t1 as the 'flag' register to bridge the BoolNode producers and consumers
10820 instruct cmpFastUnlock(rFlagsReg cr, iRegP object, iRegP box, iRegPNoSp tmp1, iRegPNoSp tmp2)
10821 %{
10822 predicate(LockingMode != LM_LIGHTWEIGHT);
10823 match(Set cr (FastUnlock object box));
10824 effect(TEMP tmp1, TEMP tmp2);
10825
10826 ins_cost(10 * DEFAULT_COST);
10827 format %{ "fastunlock $object,$box\t! kills $tmp1, $tmp2, #@cmpFastUnlock" %}
10828
10829 ins_encode %{
10830 __ fast_unlock($object$$Register, $box$$Register, $tmp1$$Register, $tmp2$$Register);
10831 %}
10832
10833 ins_pipe(pipe_serial);
10834 %}
10835
10836 instruct cmpFastLockLightweight(rFlagsReg cr, iRegP object, iRegP box,
10837 iRegPNoSp tmp1, iRegPNoSp tmp2, iRegPNoSp tmp3, iRegPNoSp tmp4)
10838 %{
10839 predicate(LockingMode == LM_LIGHTWEIGHT);
10840 match(Set cr (FastLock object box));
10841 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4);
10842
10843 ins_cost(10 * DEFAULT_COST);
10844 format %{ "fastlock $object,$box\t! kills $tmp1,$tmp2,$tmp3,$tmp4 #@cmpFastLockLightweight" %}
10845
10846 ins_encode %{
10847 __ fast_lock_lightweight($object$$Register, $box$$Register,
10848 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register);
10849 %}
10850
10851 ins_pipe(pipe_serial);
10852 %}
10853
10854 instruct cmpFastUnlockLightweight(rFlagsReg cr, iRegP object, iRegP box,
10855 iRegPNoSp tmp1, iRegPNoSp tmp2, iRegPNoSp tmp3)
10856 %{
10857 predicate(LockingMode == LM_LIGHTWEIGHT);
10858 match(Set cr (FastUnlock object box));
10859 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3);
10860
10861 ins_cost(10 * DEFAULT_COST);
10862 format %{ "fastunlock $object,$box\t! kills $tmp1,$tmp2,$tmp3 #@cmpFastUnlockLightweight" %}
10863
10864 ins_encode %{
10865 __ fast_unlock_lightweight($object$$Register, $box$$Register,
10866 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
10867 %}
10868
10869 ins_pipe(pipe_serial);
10870 %}
10871
10872 // Tail Call; Jump from runtime stub to Java code.
10873 // Also known as an 'interprocedural jump'.
10874 // Target of jump will eventually return to caller.
10875 // TailJump below removes the return address.
10876 // Don't use fp for 'jump_target' because a MachEpilogNode has already been
10877 // emitted just above the TailCall which has reset fp to the caller state.
10878 instruct TailCalljmpInd(iRegPNoSpNoFp jump_target, inline_cache_RegP method_oop)
10879 %{
10880 match(TailCall jump_target method_oop);
10881
10882 ins_cost(BRANCH_COST);
10883
10884 format %{ "jalr $jump_target\t# $method_oop holds method oop, #@TailCalljmpInd." %}
10885
10886 ins_encode(riscv_enc_tail_call(jump_target));
10887
10888 ins_pipe(pipe_class_call);
10889 %}
10890
10891 instruct TailjmpInd(iRegPNoSpNoFp jump_target, iRegP_R10 ex_oop)
10892 %{
10893 match(TailJump jump_target ex_oop);
10894
10895 ins_cost(ALU_COST + BRANCH_COST);
10896
10897 format %{ "jalr $jump_target\t# $ex_oop holds exception oop, #@TailjmpInd." %}
10898
10899 ins_encode(riscv_enc_tail_jmp(jump_target));
10900
10901 ins_pipe(pipe_class_call);
10902 %}
10903
10904 // Forward exception.
10905 instruct ForwardExceptionjmp()
10906 %{
10907 match(ForwardException);
10908
10909 ins_cost(BRANCH_COST);
10910
10911 format %{ "j forward_exception_stub\t#@ForwardException" %}
10912
10913 ins_encode %{
10914 __ far_jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
10915 %}
10916
10917 ins_pipe(pipe_class_call);
10918 %}
10919
10920 // Create exception oop: created by stack-crawling runtime code.
10921 // Created exception is now available to this handler, and is setup
10922 // just prior to jumping to this handler. No code emitted.
10923 instruct CreateException(iRegP_R10 ex_oop)
10924 %{
10925 match(Set ex_oop (CreateEx));
10926
10927 ins_cost(0);
10928 format %{ " -- \t// exception oop; no code emitted, #@CreateException" %}
10929
10930 size(0);
10931
10932 ins_encode( /*empty*/ );
10933
10934 ins_pipe(pipe_class_empty);
10935 %}
10936
10937 // Rethrow exception: The exception oop will come in the first
10938 // argument position. Then JUMP (not call) to the rethrow stub code.
10939 instruct RethrowException()
10940 %{
10941 match(Rethrow);
10942
10943 ins_cost(BRANCH_COST);
10944
10945 format %{ "j rethrow_stub\t#@RethrowException" %}
10946
10947 ins_encode(riscv_enc_rethrow());
10948
10949 ins_pipe(pipe_class_call);
10950 %}
10951
10952 // Return Instruction
10953 // epilog node loads ret address into ra as part of frame pop
10954 instruct Ret()
10955 %{
10956 match(Return);
10957
10958 ins_cost(BRANCH_COST);
10959 format %{ "ret\t// return register, #@Ret" %}
10960
10961 ins_encode(riscv_enc_ret());
10962
10963 ins_pipe(pipe_branch);
10964 %}
10965
10966 // Die now.
10967 instruct ShouldNotReachHere() %{
10968 match(Halt);
10969
10970 ins_cost(BRANCH_COST);
10971
10972 format %{ "#@ShouldNotReachHere" %}
10973
10974 ins_encode %{
10975 if (is_reachable()) {
10976 const char* str = __ code_string(_halt_reason);
10977 __ stop(str);
10978 }
10979 %}
10980
10981 ins_pipe(pipe_class_default);
10982 %}
10983
10984
10985 //----------PEEPHOLE RULES-----------------------------------------------------
10986 // These must follow all instruction definitions as they use the names
10987 // defined in the instructions definitions.
10988 //
10989 // peepmatch ( root_instr_name [preceding_instruction]* );
10990 //
10991 // peepconstraint %{
10992 // (instruction_number.operand_name relational_op instruction_number.operand_name
10993 // [, ...] );
10994 // // instruction numbers are zero-based using left to right order in peepmatch
10995 //
10996 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
10997 // // provide an instruction_number.operand_name for each operand that appears
10998 // // in the replacement instruction's match rule
10999 //
11000 // ---------VM FLAGS---------------------------------------------------------
11001 //
11002 // All peephole optimizations can be turned off using -XX:-OptoPeephole
11003 //
11004 // Each peephole rule is given an identifying number starting with zero and
11005 // increasing by one in the order seen by the parser. An individual peephole
11006 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
11007 // on the command-line.
11008 //
11009 // ---------CURRENT LIMITATIONS----------------------------------------------
11010 //
11011 // Only match adjacent instructions in same basic block
11012 // Only equality constraints
11013 // Only constraints between operands, not (0.dest_reg == RAX_enc)
11014 // Only one replacement instruction
11015 //
11016 //----------SMARTSPILL RULES---------------------------------------------------
11017 // These must follow all instruction definitions as they use the names
11018 // defined in the instructions definitions.
11019
11020 // Local Variables:
11021 // mode: c++
11022 // End: