1 //
2 // Copyright (c) 2003, 2026, Oracle and/or its affiliates. All rights reserved.
3 // Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
4 // Copyright (c) 2020, 2024, Huawei Technologies Co., Ltd. All rights reserved.
5 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
6 //
7 // This code is free software; you can redistribute it and/or modify it
8 // under the terms of the GNU General Public License version 2 only, as
9 // published by the Free Software Foundation.
10 //
11 // This code is distributed in the hope that it will be useful, but WITHOUT
12 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 // version 2 for more details (a copy is included in the LICENSE file that
15 // accompanied this code).
16 //
17 // You should have received a copy of the GNU General Public License version
18 // 2 along with this work; if not, write to the Free Software Foundation,
19 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
20 //
21 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
22 // or visit www.oracle.com if you need additional information or have any
23 // questions.
24 //
25 //
26
27 // RISCV Architecture Description File
28
29 //----------REGISTER DEFINITION BLOCK------------------------------------------
30 // This information is used by the matcher and the register allocator to
31 // describe individual registers and classes of registers within the target
32 // architecture.
33
34 register %{
35 //----------Architecture Description Register Definitions----------------------
36 // General Registers
37 // "reg_def" name ( register save type, C convention save type,
38 // ideal register type, encoding );
39 // Register Save Types:
40 //
41 // NS = No-Save: The register allocator assumes that these registers
42 // can be used without saving upon entry to the method, &
43 // that they do not need to be saved at call sites.
44 //
45 // SOC = Save-On-Call: The register allocator assumes that these registers
46 // can be used without saving upon entry to the method,
47 // but that they must be saved at call sites.
48 //
49 // SOE = Save-On-Entry: The register allocator assumes that these registers
50 // must be saved before using them upon entry to the
51 // method, but they do not need to be saved at call
52 // sites.
53 //
54 // AS = Always-Save: The register allocator assumes that these registers
55 // must be saved before using them upon entry to the
56 // method, & that they must be saved at call sites.
57 //
58 // Ideal Register Type is used to determine how to save & restore a
59 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
60 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
61 //
62 // The encoding number is the actual bit-pattern placed into the opcodes.
63
64 // We must define the 64 bit int registers in two 32 bit halves, the
65 // real lower register and a virtual upper half register. upper halves
66 // are used by the register allocator but are not actually supplied as
67 // operands to memory ops.
68 //
69 // follow the C1 compiler in making registers
70 //
71 // x7, x9-x17, x27-x31 volatile (caller save)
72 // x0-x4, x8, x23 system (no save, no allocate)
73 // x5-x6 non-allocatable (so we can use them as temporary regs)
74
75 //
76 // as regards Java usage. we don't use any callee save registers
77 // because this makes it difficult to de-optimise a frame (see comment
78 // in x86 implementation of Deoptimization::unwind_callee_save_values)
79 //
80
81 // General Registers
82
83 reg_def R0 ( NS, NS, Op_RegI, 0, x0->as_VMReg() ); // zr
84 reg_def R0_H ( NS, NS, Op_RegI, 0, x0->as_VMReg()->next() );
85 reg_def R1 ( NS, SOC, Op_RegI, 1, x1->as_VMReg() ); // ra
86 reg_def R1_H ( NS, SOC, Op_RegI, 1, x1->as_VMReg()->next() );
87 reg_def R2 ( NS, NS, Op_RegI, 2, x2->as_VMReg() ); // sp
88 reg_def R2_H ( NS, NS, Op_RegI, 2, x2->as_VMReg()->next() );
89 reg_def R3 ( NS, NS, Op_RegI, 3, x3->as_VMReg() ); // gp
90 reg_def R3_H ( NS, NS, Op_RegI, 3, x3->as_VMReg()->next() );
91 reg_def R4 ( NS, NS, Op_RegI, 4, x4->as_VMReg() ); // tp
92 reg_def R4_H ( NS, NS, Op_RegI, 4, x4->as_VMReg()->next() );
93 reg_def R7 ( SOC, SOC, Op_RegI, 7, x7->as_VMReg() );
94 reg_def R7_H ( SOC, SOC, Op_RegI, 7, x7->as_VMReg()->next() );
95 reg_def R8 ( NS, SOE, Op_RegI, 8, x8->as_VMReg() ); // fp
96 reg_def R8_H ( NS, SOE, Op_RegI, 8, x8->as_VMReg()->next() );
97 reg_def R9 ( SOC, SOE, Op_RegI, 9, x9->as_VMReg() );
98 reg_def R9_H ( SOC, SOE, Op_RegI, 9, x9->as_VMReg()->next() );
99 reg_def R10 ( SOC, SOC, Op_RegI, 10, x10->as_VMReg() );
100 reg_def R10_H ( SOC, SOC, Op_RegI, 10, x10->as_VMReg()->next());
101 reg_def R11 ( SOC, SOC, Op_RegI, 11, x11->as_VMReg() );
102 reg_def R11_H ( SOC, SOC, Op_RegI, 11, x11->as_VMReg()->next());
103 reg_def R12 ( SOC, SOC, Op_RegI, 12, x12->as_VMReg() );
104 reg_def R12_H ( SOC, SOC, Op_RegI, 12, x12->as_VMReg()->next());
105 reg_def R13 ( SOC, SOC, Op_RegI, 13, x13->as_VMReg() );
106 reg_def R13_H ( SOC, SOC, Op_RegI, 13, x13->as_VMReg()->next());
107 reg_def R14 ( SOC, SOC, Op_RegI, 14, x14->as_VMReg() );
108 reg_def R14_H ( SOC, SOC, Op_RegI, 14, x14->as_VMReg()->next());
109 reg_def R15 ( SOC, SOC, Op_RegI, 15, x15->as_VMReg() );
110 reg_def R15_H ( SOC, SOC, Op_RegI, 15, x15->as_VMReg()->next());
111 reg_def R16 ( SOC, SOC, Op_RegI, 16, x16->as_VMReg() );
112 reg_def R16_H ( SOC, SOC, Op_RegI, 16, x16->as_VMReg()->next());
113 reg_def R17 ( SOC, SOC, Op_RegI, 17, x17->as_VMReg() );
114 reg_def R17_H ( SOC, SOC, Op_RegI, 17, x17->as_VMReg()->next());
115 reg_def R18 ( SOC, SOE, Op_RegI, 18, x18->as_VMReg() );
116 reg_def R18_H ( SOC, SOE, Op_RegI, 18, x18->as_VMReg()->next());
117 reg_def R19 ( SOC, SOE, Op_RegI, 19, x19->as_VMReg() );
118 reg_def R19_H ( SOC, SOE, Op_RegI, 19, x19->as_VMReg()->next());
119 reg_def R20 ( SOC, SOE, Op_RegI, 20, x20->as_VMReg() ); // caller esp
120 reg_def R20_H ( SOC, SOE, Op_RegI, 20, x20->as_VMReg()->next());
121 reg_def R21 ( SOC, SOE, Op_RegI, 21, x21->as_VMReg() );
122 reg_def R21_H ( SOC, SOE, Op_RegI, 21, x21->as_VMReg()->next());
123 reg_def R22 ( SOC, SOE, Op_RegI, 22, x22->as_VMReg() );
124 reg_def R22_H ( SOC, SOE, Op_RegI, 22, x22->as_VMReg()->next());
125 reg_def R23 ( NS, SOE, Op_RegI, 23, x23->as_VMReg() ); // java thread
126 reg_def R23_H ( NS, SOE, Op_RegI, 23, x23->as_VMReg()->next());
127 reg_def R24 ( SOC, SOE, Op_RegI, 24, x24->as_VMReg() );
128 reg_def R24_H ( SOC, SOE, Op_RegI, 24, x24->as_VMReg()->next());
129 reg_def R25 ( SOC, SOE, Op_RegI, 25, x25->as_VMReg() );
130 reg_def R25_H ( SOC, SOE, Op_RegI, 25, x25->as_VMReg()->next());
131 reg_def R26 ( SOC, SOE, Op_RegI, 26, x26->as_VMReg() );
132 reg_def R26_H ( SOC, SOE, Op_RegI, 26, x26->as_VMReg()->next());
133 reg_def R27 ( SOC, SOE, Op_RegI, 27, x27->as_VMReg() ); // heapbase
134 reg_def R27_H ( SOC, SOE, Op_RegI, 27, x27->as_VMReg()->next());
135 reg_def R28 ( SOC, SOC, Op_RegI, 28, x28->as_VMReg() );
136 reg_def R28_H ( SOC, SOC, Op_RegI, 28, x28->as_VMReg()->next());
137 reg_def R29 ( SOC, SOC, Op_RegI, 29, x29->as_VMReg() );
138 reg_def R29_H ( SOC, SOC, Op_RegI, 29, x29->as_VMReg()->next());
139 reg_def R30 ( SOC, SOC, Op_RegI, 30, x30->as_VMReg() );
140 reg_def R30_H ( SOC, SOC, Op_RegI, 30, x30->as_VMReg()->next());
141 reg_def R31 ( SOC, SOC, Op_RegI, 31, x31->as_VMReg() );
142 reg_def R31_H ( SOC, SOC, Op_RegI, 31, x31->as_VMReg()->next());
143
144 // ----------------------------
145 // Float/Double Registers
146 // ----------------------------
147
148 // Double Registers
149
150 // The rules of ADL require that double registers be defined in pairs.
151 // Each pair must be two 32-bit values, but not necessarily a pair of
152 // single float registers. In each pair, ADLC-assigned register numbers
153 // must be adjacent, with the lower number even. Finally, when the
154 // CPU stores such a register pair to memory, the word associated with
155 // the lower ADLC-assigned number must be stored to the lower address.
156
157 // RISCV has 32 floating-point registers. Each can store a single
158 // or double precision floating-point value.
159
160 // for Java use float registers f0-f31 are always save on call whereas
161 // the platform ABI treats f8-f9 and f18-f27 as callee save). Other
162 // float registers are SOC as per the platform spec
163
164 reg_def F0 ( SOC, SOC, Op_RegF, 0, f0->as_VMReg() );
165 reg_def F0_H ( SOC, SOC, Op_RegF, 0, f0->as_VMReg()->next() );
166 reg_def F1 ( SOC, SOC, Op_RegF, 1, f1->as_VMReg() );
167 reg_def F1_H ( SOC, SOC, Op_RegF, 1, f1->as_VMReg()->next() );
168 reg_def F2 ( SOC, SOC, Op_RegF, 2, f2->as_VMReg() );
169 reg_def F2_H ( SOC, SOC, Op_RegF, 2, f2->as_VMReg()->next() );
170 reg_def F3 ( SOC, SOC, Op_RegF, 3, f3->as_VMReg() );
171 reg_def F3_H ( SOC, SOC, Op_RegF, 3, f3->as_VMReg()->next() );
172 reg_def F4 ( SOC, SOC, Op_RegF, 4, f4->as_VMReg() );
173 reg_def F4_H ( SOC, SOC, Op_RegF, 4, f4->as_VMReg()->next() );
174 reg_def F5 ( SOC, SOC, Op_RegF, 5, f5->as_VMReg() );
175 reg_def F5_H ( SOC, SOC, Op_RegF, 5, f5->as_VMReg()->next() );
176 reg_def F6 ( SOC, SOC, Op_RegF, 6, f6->as_VMReg() );
177 reg_def F6_H ( SOC, SOC, Op_RegF, 6, f6->as_VMReg()->next() );
178 reg_def F7 ( SOC, SOC, Op_RegF, 7, f7->as_VMReg() );
179 reg_def F7_H ( SOC, SOC, Op_RegF, 7, f7->as_VMReg()->next() );
180 reg_def F8 ( SOC, SOE, Op_RegF, 8, f8->as_VMReg() );
181 reg_def F8_H ( SOC, SOE, Op_RegF, 8, f8->as_VMReg()->next() );
182 reg_def F9 ( SOC, SOE, Op_RegF, 9, f9->as_VMReg() );
183 reg_def F9_H ( SOC, SOE, Op_RegF, 9, f9->as_VMReg()->next() );
184 reg_def F10 ( SOC, SOC, Op_RegF, 10, f10->as_VMReg() );
185 reg_def F10_H ( SOC, SOC, Op_RegF, 10, f10->as_VMReg()->next() );
186 reg_def F11 ( SOC, SOC, Op_RegF, 11, f11->as_VMReg() );
187 reg_def F11_H ( SOC, SOC, Op_RegF, 11, f11->as_VMReg()->next() );
188 reg_def F12 ( SOC, SOC, Op_RegF, 12, f12->as_VMReg() );
189 reg_def F12_H ( SOC, SOC, Op_RegF, 12, f12->as_VMReg()->next() );
190 reg_def F13 ( SOC, SOC, Op_RegF, 13, f13->as_VMReg() );
191 reg_def F13_H ( SOC, SOC, Op_RegF, 13, f13->as_VMReg()->next() );
192 reg_def F14 ( SOC, SOC, Op_RegF, 14, f14->as_VMReg() );
193 reg_def F14_H ( SOC, SOC, Op_RegF, 14, f14->as_VMReg()->next() );
194 reg_def F15 ( SOC, SOC, Op_RegF, 15, f15->as_VMReg() );
195 reg_def F15_H ( SOC, SOC, Op_RegF, 15, f15->as_VMReg()->next() );
196 reg_def F16 ( SOC, SOC, Op_RegF, 16, f16->as_VMReg() );
197 reg_def F16_H ( SOC, SOC, Op_RegF, 16, f16->as_VMReg()->next() );
198 reg_def F17 ( SOC, SOC, Op_RegF, 17, f17->as_VMReg() );
199 reg_def F17_H ( SOC, SOC, Op_RegF, 17, f17->as_VMReg()->next() );
200 reg_def F18 ( SOC, SOE, Op_RegF, 18, f18->as_VMReg() );
201 reg_def F18_H ( SOC, SOE, Op_RegF, 18, f18->as_VMReg()->next() );
202 reg_def F19 ( SOC, SOE, Op_RegF, 19, f19->as_VMReg() );
203 reg_def F19_H ( SOC, SOE, Op_RegF, 19, f19->as_VMReg()->next() );
204 reg_def F20 ( SOC, SOE, Op_RegF, 20, f20->as_VMReg() );
205 reg_def F20_H ( SOC, SOE, Op_RegF, 20, f20->as_VMReg()->next() );
206 reg_def F21 ( SOC, SOE, Op_RegF, 21, f21->as_VMReg() );
207 reg_def F21_H ( SOC, SOE, Op_RegF, 21, f21->as_VMReg()->next() );
208 reg_def F22 ( SOC, SOE, Op_RegF, 22, f22->as_VMReg() );
209 reg_def F22_H ( SOC, SOE, Op_RegF, 22, f22->as_VMReg()->next() );
210 reg_def F23 ( SOC, SOE, Op_RegF, 23, f23->as_VMReg() );
211 reg_def F23_H ( SOC, SOE, Op_RegF, 23, f23->as_VMReg()->next() );
212 reg_def F24 ( SOC, SOE, Op_RegF, 24, f24->as_VMReg() );
213 reg_def F24_H ( SOC, SOE, Op_RegF, 24, f24->as_VMReg()->next() );
214 reg_def F25 ( SOC, SOE, Op_RegF, 25, f25->as_VMReg() );
215 reg_def F25_H ( SOC, SOE, Op_RegF, 25, f25->as_VMReg()->next() );
216 reg_def F26 ( SOC, SOE, Op_RegF, 26, f26->as_VMReg() );
217 reg_def F26_H ( SOC, SOE, Op_RegF, 26, f26->as_VMReg()->next() );
218 reg_def F27 ( SOC, SOE, Op_RegF, 27, f27->as_VMReg() );
219 reg_def F27_H ( SOC, SOE, Op_RegF, 27, f27->as_VMReg()->next() );
220 reg_def F28 ( SOC, SOC, Op_RegF, 28, f28->as_VMReg() );
221 reg_def F28_H ( SOC, SOC, Op_RegF, 28, f28->as_VMReg()->next() );
222 reg_def F29 ( SOC, SOC, Op_RegF, 29, f29->as_VMReg() );
223 reg_def F29_H ( SOC, SOC, Op_RegF, 29, f29->as_VMReg()->next() );
224 reg_def F30 ( SOC, SOC, Op_RegF, 30, f30->as_VMReg() );
225 reg_def F30_H ( SOC, SOC, Op_RegF, 30, f30->as_VMReg()->next() );
226 reg_def F31 ( SOC, SOC, Op_RegF, 31, f31->as_VMReg() );
227 reg_def F31_H ( SOC, SOC, Op_RegF, 31, f31->as_VMReg()->next() );
228
229 // ----------------------------
230 // Vector Registers
231 // ----------------------------
232
233 // For RVV vector registers, we simply extend vector register size to 4
234 // 'logical' slots. This is nominally 128 bits but it actually covers
235 // all possible 'physical' RVV vector register lengths from 128 ~ 1024
236 // bits. The 'physical' RVV vector register length is detected during
237 // startup, so the register allocator is able to identify the correct
238 // number of bytes needed for an RVV spill/unspill.
239
240 reg_def V0 ( SOC, SOC, Op_VecA, 0, v0->as_VMReg() );
241 reg_def V0_H ( SOC, SOC, Op_VecA, 0, v0->as_VMReg()->next() );
242 reg_def V0_J ( SOC, SOC, Op_VecA, 0, v0->as_VMReg()->next(2) );
243 reg_def V0_K ( SOC, SOC, Op_VecA, 0, v0->as_VMReg()->next(3) );
244
245 reg_def V1 ( SOC, SOC, Op_VecA, 1, v1->as_VMReg() );
246 reg_def V1_H ( SOC, SOC, Op_VecA, 1, v1->as_VMReg()->next() );
247 reg_def V1_J ( SOC, SOC, Op_VecA, 1, v1->as_VMReg()->next(2) );
248 reg_def V1_K ( SOC, SOC, Op_VecA, 1, v1->as_VMReg()->next(3) );
249
250 reg_def V2 ( SOC, SOC, Op_VecA, 2, v2->as_VMReg() );
251 reg_def V2_H ( SOC, SOC, Op_VecA, 2, v2->as_VMReg()->next() );
252 reg_def V2_J ( SOC, SOC, Op_VecA, 2, v2->as_VMReg()->next(2) );
253 reg_def V2_K ( SOC, SOC, Op_VecA, 2, v2->as_VMReg()->next(3) );
254
255 reg_def V3 ( SOC, SOC, Op_VecA, 3, v3->as_VMReg() );
256 reg_def V3_H ( SOC, SOC, Op_VecA, 3, v3->as_VMReg()->next() );
257 reg_def V3_J ( SOC, SOC, Op_VecA, 3, v3->as_VMReg()->next(2) );
258 reg_def V3_K ( SOC, SOC, Op_VecA, 3, v3->as_VMReg()->next(3) );
259
260 reg_def V4 ( SOC, SOC, Op_VecA, 4, v4->as_VMReg() );
261 reg_def V4_H ( SOC, SOC, Op_VecA, 4, v4->as_VMReg()->next() );
262 reg_def V4_J ( SOC, SOC, Op_VecA, 4, v4->as_VMReg()->next(2) );
263 reg_def V4_K ( SOC, SOC, Op_VecA, 4, v4->as_VMReg()->next(3) );
264
265 reg_def V5 ( SOC, SOC, Op_VecA, 5, v5->as_VMReg() );
266 reg_def V5_H ( SOC, SOC, Op_VecA, 5, v5->as_VMReg()->next() );
267 reg_def V5_J ( SOC, SOC, Op_VecA, 5, v5->as_VMReg()->next(2) );
268 reg_def V5_K ( SOC, SOC, Op_VecA, 5, v5->as_VMReg()->next(3) );
269
270 reg_def V6 ( SOC, SOC, Op_VecA, 6, v6->as_VMReg() );
271 reg_def V6_H ( SOC, SOC, Op_VecA, 6, v6->as_VMReg()->next() );
272 reg_def V6_J ( SOC, SOC, Op_VecA, 6, v6->as_VMReg()->next(2) );
273 reg_def V6_K ( SOC, SOC, Op_VecA, 6, v6->as_VMReg()->next(3) );
274
275 reg_def V7 ( SOC, SOC, Op_VecA, 7, v7->as_VMReg() );
276 reg_def V7_H ( SOC, SOC, Op_VecA, 7, v7->as_VMReg()->next() );
277 reg_def V7_J ( SOC, SOC, Op_VecA, 7, v7->as_VMReg()->next(2) );
278 reg_def V7_K ( SOC, SOC, Op_VecA, 7, v7->as_VMReg()->next(3) );
279
280 reg_def V8 ( SOC, SOC, Op_VecA, 8, v8->as_VMReg() );
281 reg_def V8_H ( SOC, SOC, Op_VecA, 8, v8->as_VMReg()->next() );
282 reg_def V8_J ( SOC, SOC, Op_VecA, 8, v8->as_VMReg()->next(2) );
283 reg_def V8_K ( SOC, SOC, Op_VecA, 8, v8->as_VMReg()->next(3) );
284
285 reg_def V9 ( SOC, SOC, Op_VecA, 9, v9->as_VMReg() );
286 reg_def V9_H ( SOC, SOC, Op_VecA, 9, v9->as_VMReg()->next() );
287 reg_def V9_J ( SOC, SOC, Op_VecA, 9, v9->as_VMReg()->next(2) );
288 reg_def V9_K ( SOC, SOC, Op_VecA, 9, v9->as_VMReg()->next(3) );
289
290 reg_def V10 ( SOC, SOC, Op_VecA, 10, v10->as_VMReg() );
291 reg_def V10_H ( SOC, SOC, Op_VecA, 10, v10->as_VMReg()->next() );
292 reg_def V10_J ( SOC, SOC, Op_VecA, 10, v10->as_VMReg()->next(2) );
293 reg_def V10_K ( SOC, SOC, Op_VecA, 10, v10->as_VMReg()->next(3) );
294
295 reg_def V11 ( SOC, SOC, Op_VecA, 11, v11->as_VMReg() );
296 reg_def V11_H ( SOC, SOC, Op_VecA, 11, v11->as_VMReg()->next() );
297 reg_def V11_J ( SOC, SOC, Op_VecA, 11, v11->as_VMReg()->next(2) );
298 reg_def V11_K ( SOC, SOC, Op_VecA, 11, v11->as_VMReg()->next(3) );
299
300 reg_def V12 ( SOC, SOC, Op_VecA, 12, v12->as_VMReg() );
301 reg_def V12_H ( SOC, SOC, Op_VecA, 12, v12->as_VMReg()->next() );
302 reg_def V12_J ( SOC, SOC, Op_VecA, 12, v12->as_VMReg()->next(2) );
303 reg_def V12_K ( SOC, SOC, Op_VecA, 12, v12->as_VMReg()->next(3) );
304
305 reg_def V13 ( SOC, SOC, Op_VecA, 13, v13->as_VMReg() );
306 reg_def V13_H ( SOC, SOC, Op_VecA, 13, v13->as_VMReg()->next() );
307 reg_def V13_J ( SOC, SOC, Op_VecA, 13, v13->as_VMReg()->next(2) );
308 reg_def V13_K ( SOC, SOC, Op_VecA, 13, v13->as_VMReg()->next(3) );
309
310 reg_def V14 ( SOC, SOC, Op_VecA, 14, v14->as_VMReg() );
311 reg_def V14_H ( SOC, SOC, Op_VecA, 14, v14->as_VMReg()->next() );
312 reg_def V14_J ( SOC, SOC, Op_VecA, 14, v14->as_VMReg()->next(2) );
313 reg_def V14_K ( SOC, SOC, Op_VecA, 14, v14->as_VMReg()->next(3) );
314
315 reg_def V15 ( SOC, SOC, Op_VecA, 15, v15->as_VMReg() );
316 reg_def V15_H ( SOC, SOC, Op_VecA, 15, v15->as_VMReg()->next() );
317 reg_def V15_J ( SOC, SOC, Op_VecA, 15, v15->as_VMReg()->next(2) );
318 reg_def V15_K ( SOC, SOC, Op_VecA, 15, v15->as_VMReg()->next(3) );
319
320 reg_def V16 ( SOC, SOC, Op_VecA, 16, v16->as_VMReg() );
321 reg_def V16_H ( SOC, SOC, Op_VecA, 16, v16->as_VMReg()->next() );
322 reg_def V16_J ( SOC, SOC, Op_VecA, 16, v16->as_VMReg()->next(2) );
323 reg_def V16_K ( SOC, SOC, Op_VecA, 16, v16->as_VMReg()->next(3) );
324
325 reg_def V17 ( SOC, SOC, Op_VecA, 17, v17->as_VMReg() );
326 reg_def V17_H ( SOC, SOC, Op_VecA, 17, v17->as_VMReg()->next() );
327 reg_def V17_J ( SOC, SOC, Op_VecA, 17, v17->as_VMReg()->next(2) );
328 reg_def V17_K ( SOC, SOC, Op_VecA, 17, v17->as_VMReg()->next(3) );
329
330 reg_def V18 ( SOC, SOC, Op_VecA, 18, v18->as_VMReg() );
331 reg_def V18_H ( SOC, SOC, Op_VecA, 18, v18->as_VMReg()->next() );
332 reg_def V18_J ( SOC, SOC, Op_VecA, 18, v18->as_VMReg()->next(2) );
333 reg_def V18_K ( SOC, SOC, Op_VecA, 18, v18->as_VMReg()->next(3) );
334
335 reg_def V19 ( SOC, SOC, Op_VecA, 19, v19->as_VMReg() );
336 reg_def V19_H ( SOC, SOC, Op_VecA, 19, v19->as_VMReg()->next() );
337 reg_def V19_J ( SOC, SOC, Op_VecA, 19, v19->as_VMReg()->next(2) );
338 reg_def V19_K ( SOC, SOC, Op_VecA, 19, v19->as_VMReg()->next(3) );
339
340 reg_def V20 ( SOC, SOC, Op_VecA, 20, v20->as_VMReg() );
341 reg_def V20_H ( SOC, SOC, Op_VecA, 20, v20->as_VMReg()->next() );
342 reg_def V20_J ( SOC, SOC, Op_VecA, 20, v20->as_VMReg()->next(2) );
343 reg_def V20_K ( SOC, SOC, Op_VecA, 20, v20->as_VMReg()->next(3) );
344
345 reg_def V21 ( SOC, SOC, Op_VecA, 21, v21->as_VMReg() );
346 reg_def V21_H ( SOC, SOC, Op_VecA, 21, v21->as_VMReg()->next() );
347 reg_def V21_J ( SOC, SOC, Op_VecA, 21, v21->as_VMReg()->next(2) );
348 reg_def V21_K ( SOC, SOC, Op_VecA, 21, v21->as_VMReg()->next(3) );
349
350 reg_def V22 ( SOC, SOC, Op_VecA, 22, v22->as_VMReg() );
351 reg_def V22_H ( SOC, SOC, Op_VecA, 22, v22->as_VMReg()->next() );
352 reg_def V22_J ( SOC, SOC, Op_VecA, 22, v22->as_VMReg()->next(2) );
353 reg_def V22_K ( SOC, SOC, Op_VecA, 22, v22->as_VMReg()->next(3) );
354
355 reg_def V23 ( SOC, SOC, Op_VecA, 23, v23->as_VMReg() );
356 reg_def V23_H ( SOC, SOC, Op_VecA, 23, v23->as_VMReg()->next() );
357 reg_def V23_J ( SOC, SOC, Op_VecA, 23, v23->as_VMReg()->next(2) );
358 reg_def V23_K ( SOC, SOC, Op_VecA, 23, v23->as_VMReg()->next(3) );
359
360 reg_def V24 ( SOC, SOC, Op_VecA, 24, v24->as_VMReg() );
361 reg_def V24_H ( SOC, SOC, Op_VecA, 24, v24->as_VMReg()->next() );
362 reg_def V24_J ( SOC, SOC, Op_VecA, 24, v24->as_VMReg()->next(2) );
363 reg_def V24_K ( SOC, SOC, Op_VecA, 24, v24->as_VMReg()->next(3) );
364
365 reg_def V25 ( SOC, SOC, Op_VecA, 25, v25->as_VMReg() );
366 reg_def V25_H ( SOC, SOC, Op_VecA, 25, v25->as_VMReg()->next() );
367 reg_def V25_J ( SOC, SOC, Op_VecA, 25, v25->as_VMReg()->next(2) );
368 reg_def V25_K ( SOC, SOC, Op_VecA, 25, v25->as_VMReg()->next(3) );
369
370 reg_def V26 ( SOC, SOC, Op_VecA, 26, v26->as_VMReg() );
371 reg_def V26_H ( SOC, SOC, Op_VecA, 26, v26->as_VMReg()->next() );
372 reg_def V26_J ( SOC, SOC, Op_VecA, 26, v26->as_VMReg()->next(2) );
373 reg_def V26_K ( SOC, SOC, Op_VecA, 26, v26->as_VMReg()->next(3) );
374
375 reg_def V27 ( SOC, SOC, Op_VecA, 27, v27->as_VMReg() );
376 reg_def V27_H ( SOC, SOC, Op_VecA, 27, v27->as_VMReg()->next() );
377 reg_def V27_J ( SOC, SOC, Op_VecA, 27, v27->as_VMReg()->next(2) );
378 reg_def V27_K ( SOC, SOC, Op_VecA, 27, v27->as_VMReg()->next(3) );
379
380 reg_def V28 ( SOC, SOC, Op_VecA, 28, v28->as_VMReg() );
381 reg_def V28_H ( SOC, SOC, Op_VecA, 28, v28->as_VMReg()->next() );
382 reg_def V28_J ( SOC, SOC, Op_VecA, 28, v28->as_VMReg()->next(2) );
383 reg_def V28_K ( SOC, SOC, Op_VecA, 28, v28->as_VMReg()->next(3) );
384
385 reg_def V29 ( SOC, SOC, Op_VecA, 29, v29->as_VMReg() );
386 reg_def V29_H ( SOC, SOC, Op_VecA, 29, v29->as_VMReg()->next() );
387 reg_def V29_J ( SOC, SOC, Op_VecA, 29, v29->as_VMReg()->next(2) );
388 reg_def V29_K ( SOC, SOC, Op_VecA, 29, v29->as_VMReg()->next(3) );
389
390 reg_def V30 ( SOC, SOC, Op_VecA, 30, v30->as_VMReg() );
391 reg_def V30_H ( SOC, SOC, Op_VecA, 30, v30->as_VMReg()->next() );
392 reg_def V30_J ( SOC, SOC, Op_VecA, 30, v30->as_VMReg()->next(2) );
393 reg_def V30_K ( SOC, SOC, Op_VecA, 30, v30->as_VMReg()->next(3) );
394
395 reg_def V31 ( SOC, SOC, Op_VecA, 31, v31->as_VMReg() );
396 reg_def V31_H ( SOC, SOC, Op_VecA, 31, v31->as_VMReg()->next() );
397 reg_def V31_J ( SOC, SOC, Op_VecA, 31, v31->as_VMReg()->next(2) );
398 reg_def V31_K ( SOC, SOC, Op_VecA, 31, v31->as_VMReg()->next(3) );
399
400 // ----------------------------
401 // Special Registers
402 // ----------------------------
403
404 // On riscv, the physical flag register is missing, so we use t1 instead,
405 // to bridge the RegFlag semantics in share/opto
406
407 reg_def RFLAGS (SOC, SOC, Op_RegFlags, 6, x6->as_VMReg() );
408
409 // Specify priority of register selection within phases of register
410 // allocation. Highest priority is first. A useful heuristic is to
411 // give registers a low priority when they are required by machine
412 // instructions, like EAX and EDX on I486, and choose no-save registers
413 // before save-on-call, & save-on-call before save-on-entry. Registers
414 // which participate in fixed calling sequences should come last.
415 // Registers which are used as pairs must fall on an even boundary.
416
417 alloc_class chunk0(
418 // volatiles
419 R7, R7_H,
420 R28, R28_H,
421 R29, R29_H,
422 R30, R30_H,
423 R31, R31_H,
424
425 // arg registers
426 R10, R10_H,
427 R11, R11_H,
428 R12, R12_H,
429 R13, R13_H,
430 R14, R14_H,
431 R15, R15_H,
432 R16, R16_H,
433 R17, R17_H,
434
435 // non-volatiles
436 R9, R9_H,
437 R18, R18_H,
438 R19, R19_H,
439 R20, R20_H,
440 R21, R21_H,
441 R22, R22_H,
442 R24, R24_H,
443 R25, R25_H,
444 R26, R26_H,
445
446 // non-allocatable registers
447 R23, R23_H, // java thread
448 R27, R27_H, // heapbase
449 R4, R4_H, // thread
450 R8, R8_H, // fp
451 R0, R0_H, // zero
452 R1, R1_H, // ra
453 R2, R2_H, // sp
454 R3, R3_H, // gp
455 );
456
457 alloc_class chunk1(
458
459 // no save
460 F0, F0_H,
461 F1, F1_H,
462 F2, F2_H,
463 F3, F3_H,
464 F4, F4_H,
465 F5, F5_H,
466 F6, F6_H,
467 F7, F7_H,
468 F28, F28_H,
469 F29, F29_H,
470 F30, F30_H,
471 F31, F31_H,
472
473 // arg registers
474 F10, F10_H,
475 F11, F11_H,
476 F12, F12_H,
477 F13, F13_H,
478 F14, F14_H,
479 F15, F15_H,
480 F16, F16_H,
481 F17, F17_H,
482
483 // non-volatiles
484 F8, F8_H,
485 F9, F9_H,
486 F18, F18_H,
487 F19, F19_H,
488 F20, F20_H,
489 F21, F21_H,
490 F22, F22_H,
491 F23, F23_H,
492 F24, F24_H,
493 F25, F25_H,
494 F26, F26_H,
495 F27, F27_H,
496 );
497
498 alloc_class chunk2(
499 V0, V0_H, V0_J, V0_K,
500 V1, V1_H, V1_J, V1_K,
501 V2, V2_H, V2_J, V2_K,
502 V3, V3_H, V3_J, V3_K,
503 V4, V4_H, V4_J, V4_K,
504 V5, V5_H, V5_J, V5_K,
505 V6, V6_H, V6_J, V6_K,
506 V7, V7_H, V7_J, V7_K,
507 V8, V8_H, V8_J, V8_K,
508 V9, V9_H, V9_J, V9_K,
509 V10, V10_H, V10_J, V10_K,
510 V11, V11_H, V11_J, V11_K,
511 V12, V12_H, V12_J, V12_K,
512 V13, V13_H, V13_J, V13_K,
513 V14, V14_H, V14_J, V14_K,
514 V15, V15_H, V15_J, V15_K,
515 V16, V16_H, V16_J, V16_K,
516 V17, V17_H, V17_J, V17_K,
517 V18, V18_H, V18_J, V18_K,
518 V19, V19_H, V19_J, V19_K,
519 V20, V20_H, V20_J, V20_K,
520 V21, V21_H, V21_J, V21_K,
521 V22, V22_H, V22_J, V22_K,
522 V23, V23_H, V23_J, V23_K,
523 V24, V24_H, V24_J, V24_K,
524 V25, V25_H, V25_J, V25_K,
525 V26, V26_H, V26_J, V26_K,
526 V27, V27_H, V27_J, V27_K,
527 V28, V28_H, V28_J, V28_K,
528 V29, V29_H, V29_J, V29_K,
529 V30, V30_H, V30_J, V30_K,
530 V31, V31_H, V31_J, V31_K,
531 );
532
533 alloc_class chunk3(RFLAGS);
534
535 //----------Architecture Description Register Classes--------------------------
536 // Several register classes are automatically defined based upon information in
537 // this architecture description.
538 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
539 // 2) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
540 //
541
542 // Class for all 32 bit general purpose registers
543 reg_class all_reg32(
544 R0,
545 R1,
546 R2,
547 R3,
548 R4,
549 R7,
550 R8,
551 R9,
552 R10,
553 R11,
554 R12,
555 R13,
556 R14,
557 R15,
558 R16,
559 R17,
560 R18,
561 R19,
562 R20,
563 R21,
564 R22,
565 R23,
566 R24,
567 R25,
568 R26,
569 R27,
570 R28,
571 R29,
572 R30,
573 R31
574 );
575
576 // Class for any 32 bit integer registers (excluding zr)
577 reg_class any_reg32 %{
578 return _ANY_REG32_mask;
579 %}
580
581 // Singleton class for R10 int register
582 reg_class int_r10_reg(R10);
583
584 // Singleton class for R12 int register
585 reg_class int_r12_reg(R12);
586
587 // Singleton class for R13 int register
588 reg_class int_r13_reg(R13);
589
590 // Singleton class for R14 int register
591 reg_class int_r14_reg(R14);
592
593 // Class for all long integer registers
594 reg_class all_reg(
595 R0, R0_H,
596 R1, R1_H,
597 R2, R2_H,
598 R3, R3_H,
599 R4, R4_H,
600 R7, R7_H,
601 R8, R8_H,
602 R9, R9_H,
603 R10, R10_H,
604 R11, R11_H,
605 R12, R12_H,
606 R13, R13_H,
607 R14, R14_H,
608 R15, R15_H,
609 R16, R16_H,
610 R17, R17_H,
611 R18, R18_H,
612 R19, R19_H,
613 R20, R20_H,
614 R21, R21_H,
615 R22, R22_H,
616 R23, R23_H,
617 R24, R24_H,
618 R25, R25_H,
619 R26, R26_H,
620 R27, R27_H,
621 R28, R28_H,
622 R29, R29_H,
623 R30, R30_H,
624 R31, R31_H
625 );
626
627 // Class for all long integer registers (excluding zr)
628 reg_class any_reg %{
629 return _ANY_REG_mask;
630 %}
631
632 // Class for non-allocatable 32 bit registers
633 reg_class non_allocatable_reg32(
634 R0, // zr
635 R1, // ra
636 R2, // sp
637 R3, // gp
638 R4, // tp
639 R23 // java thread
640 );
641
642 // Class for non-allocatable 64 bit registers
643 reg_class non_allocatable_reg(
644 R0, R0_H, // zr
645 R1, R1_H, // ra
646 R2, R2_H, // sp
647 R3, R3_H, // gp
648 R4, R4_H, // tp
649 R23, R23_H // java thread
650 );
651
652 // Class for all non-special integer registers
653 reg_class no_special_reg32 %{
654 return _NO_SPECIAL_REG32_mask;
655 %}
656
657 // Class for all non-special long integer registers
658 reg_class no_special_reg %{
659 return _NO_SPECIAL_REG_mask;
660 %}
661
662 reg_class ptr_reg %{
663 return _PTR_REG_mask;
664 %}
665
666 // Class for all non_special pointer registers
667 reg_class no_special_ptr_reg %{
668 return _NO_SPECIAL_PTR_REG_mask;
669 %}
670
671 // Class for all non_special pointer registers (excluding fp)
672 reg_class no_special_no_fp_ptr_reg %{
673 return _NO_SPECIAL_NO_FP_PTR_REG_mask;
674 %}
675
676 // Class for 64 bit register r10
677 reg_class r10_reg(
678 R10, R10_H
679 );
680
681 // Class for 64 bit register r11
682 reg_class r11_reg(
683 R11, R11_H
684 );
685
686 // Class for 64 bit register r12
687 reg_class r12_reg(
688 R12, R12_H
689 );
690
691 // Class for 64 bit register r13
692 reg_class r13_reg(
693 R13, R13_H
694 );
695
696 // Class for 64 bit register r14
697 reg_class r14_reg(
698 R14, R14_H
699 );
700
701 // Class for 64 bit register r15
702 reg_class r15_reg(
703 R15, R15_H
704 );
705
706 // Class for 64 bit register r16
707 reg_class r16_reg(
708 R16, R16_H
709 );
710
711 // Class for method register
712 reg_class method_reg(
713 R31, R31_H
714 );
715
716 // Class for java thread register
717 reg_class java_thread_reg(
718 R23, R23_H
719 );
720
721 reg_class r28_reg(
722 R28, R28_H
723 );
724
725 reg_class r29_reg(
726 R29, R29_H
727 );
728
729 reg_class r30_reg(
730 R30, R30_H
731 );
732
733 reg_class r31_reg(
734 R31, R31_H
735 );
736
737 // Class for zero registesr
738 reg_class zr_reg(
739 R0, R0_H
740 );
741
742 // Class for thread register
743 reg_class thread_reg(
744 R4, R4_H
745 );
746
747 // Class for frame pointer register
748 reg_class fp_reg(
749 R8, R8_H
750 );
751
752 // Class for link register
753 reg_class ra_reg(
754 R1, R1_H
755 );
756
757 // Class for long sp register
758 reg_class sp_reg(
759 R2, R2_H
760 );
761
762 // Class for all float registers
763 reg_class float_reg(
764 F0,
765 F1,
766 F2,
767 F3,
768 F4,
769 F5,
770 F6,
771 F7,
772 F8,
773 F9,
774 F10,
775 F11,
776 F12,
777 F13,
778 F14,
779 F15,
780 F16,
781 F17,
782 F18,
783 F19,
784 F20,
785 F21,
786 F22,
787 F23,
788 F24,
789 F25,
790 F26,
791 F27,
792 F28,
793 F29,
794 F30,
795 F31
796 );
797
798 // Double precision float registers have virtual `high halves' that
799 // are needed by the allocator.
800 // Class for all double registers
801 reg_class double_reg(
802 F0, F0_H,
803 F1, F1_H,
804 F2, F2_H,
805 F3, F3_H,
806 F4, F4_H,
807 F5, F5_H,
808 F6, F6_H,
809 F7, F7_H,
810 F8, F8_H,
811 F9, F9_H,
812 F10, F10_H,
813 F11, F11_H,
814 F12, F12_H,
815 F13, F13_H,
816 F14, F14_H,
817 F15, F15_H,
818 F16, F16_H,
819 F17, F17_H,
820 F18, F18_H,
821 F19, F19_H,
822 F20, F20_H,
823 F21, F21_H,
824 F22, F22_H,
825 F23, F23_H,
826 F24, F24_H,
827 F25, F25_H,
828 F26, F26_H,
829 F27, F27_H,
830 F28, F28_H,
831 F29, F29_H,
832 F30, F30_H,
833 F31, F31_H
834 );
835
836 // Class for RVV vector registers
837 // Note: v0, v30 and v31 are used as mask registers.
838 reg_class vectora_reg(
839 V1, V1_H, V1_J, V1_K,
840 V2, V2_H, V2_J, V2_K,
841 V3, V3_H, V3_J, V3_K,
842 V4, V4_H, V4_J, V4_K,
843 V5, V5_H, V5_J, V5_K,
844 V6, V6_H, V6_J, V6_K,
845 V7, V7_H, V7_J, V7_K,
846 V8, V8_H, V8_J, V8_K,
847 V9, V9_H, V9_J, V9_K,
848 V10, V10_H, V10_J, V10_K,
849 V11, V11_H, V11_J, V11_K,
850 V12, V12_H, V12_J, V12_K,
851 V13, V13_H, V13_J, V13_K,
852 V14, V14_H, V14_J, V14_K,
853 V15, V15_H, V15_J, V15_K,
854 V16, V16_H, V16_J, V16_K,
855 V17, V17_H, V17_J, V17_K,
856 V18, V18_H, V18_J, V18_K,
857 V19, V19_H, V19_J, V19_K,
858 V20, V20_H, V20_J, V20_K,
859 V21, V21_H, V21_J, V21_K,
860 V22, V22_H, V22_J, V22_K,
861 V23, V23_H, V23_J, V23_K,
862 V24, V24_H, V24_J, V24_K,
863 V25, V25_H, V25_J, V25_K,
864 V26, V26_H, V26_J, V26_K,
865 V27, V27_H, V27_J, V27_K,
866 V28, V28_H, V28_J, V28_K,
867 V29, V29_H, V29_J, V29_K
868 );
869
870 // Class for 64 bit register f0
871 reg_class f0_reg(
872 F0, F0_H
873 );
874
875 // Class for 64 bit register f1
876 reg_class f1_reg(
877 F1, F1_H
878 );
879
880 // Class for 64 bit register f2
881 reg_class f2_reg(
882 F2, F2_H
883 );
884
885 // Class for 64 bit register f3
886 reg_class f3_reg(
887 F3, F3_H
888 );
889
890 // class for vector register v1
891 reg_class v1_reg(
892 V1, V1_H, V1_J, V1_K
893 );
894
895 // class for vector register v2
896 reg_class v2_reg(
897 V2, V2_H, V2_J, V2_K
898 );
899
900 // class for vector register v3
901 reg_class v3_reg(
902 V3, V3_H, V3_J, V3_K
903 );
904
905 // class for vector register v4
906 reg_class v4_reg(
907 V4, V4_H, V4_J, V4_K
908 );
909
910 // class for vector register v5
911 reg_class v5_reg(
912 V5, V5_H, V5_J, V5_K
913 );
914
915 // class for vector register v6
916 reg_class v6_reg(
917 V6, V6_H, V6_J, V6_K
918 );
919
920 // class for vector register v7
921 reg_class v7_reg(
922 V7, V7_H, V7_J, V7_K
923 );
924
925 // class for vector register v8
926 reg_class v8_reg(
927 V8, V8_H, V8_J, V8_K
928 );
929
930 // class for vector register v9
931 reg_class v9_reg(
932 V9, V9_H, V9_J, V9_K
933 );
934
935 // class for vector register v10
936 reg_class v10_reg(
937 V10, V10_H, V10_J, V10_K
938 );
939
940 // class for vector register v11
941 reg_class v11_reg(
942 V11, V11_H, V11_J, V11_K
943 );
944
945 // class for condition codes
946 reg_class reg_flags(RFLAGS);
947
948 // Class for RVV v0 mask register
949 // https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#53-vector-masking
950 // The mask value used to control execution of a masked vector
951 // instruction is always supplied by vector register v0.
952 reg_class vmask_reg_v0 (
953 V0
954 );
955
956 // Class for RVV mask registers
957 // We need two more vmask registers to do the vector mask logical ops,
958 // so define v30, v31 as mask register too.
959 reg_class vmask_reg (
960 V0,
961 V30,
962 V31
963 );
964 %}
965
966 //----------DEFINITION BLOCK---------------------------------------------------
967 // Define name --> value mappings to inform the ADLC of an integer valued name
968 // Current support includes integer values in the range [0, 0x7FFFFFFF]
969 // Format:
970 // int_def <name> ( <int_value>, <expression>);
971 // Generated Code in ad_<arch>.hpp
972 // #define <name> (<expression>)
973 // // value == <int_value>
974 // Generated code in ad_<arch>.cpp adlc_verification()
975 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
976 //
977
978 // we follow the ppc-aix port in using a simple cost model which ranks
979 // register operations as cheap, memory ops as more expensive and
980 // branches as most expensive. the first two have a low as well as a
981 // normal cost. huge cost appears to be a way of saying don't do
982 // something
983
984 definitions %{
985 // The default cost (of a register move instruction).
986 int_def DEFAULT_COST ( 100, 100);
987 int_def ALU_COST ( 100, 1 * DEFAULT_COST); // unknown, const, arith, shift, slt,
988 // multi, auipc, nop, logical, move
989 int_def LOAD_COST ( 300, 3 * DEFAULT_COST); // load, fpload
990 int_def STORE_COST ( 100, 1 * DEFAULT_COST); // store, fpstore
991 int_def XFER_COST ( 300, 3 * DEFAULT_COST); // mfc, mtc, fcvt, fmove, fcmp
992 int_def FMVX_COST ( 100, 1 * DEFAULT_COST); // shuffles with no conversion
993 int_def BRANCH_COST ( 200, 2 * DEFAULT_COST); // branch, jmp, call
994 int_def IMUL_COST ( 1000, 10 * DEFAULT_COST); // imul
995 int_def IDIVSI_COST ( 3400, 34 * DEFAULT_COST); // idivsi
996 int_def IDIVDI_COST ( 6600, 66 * DEFAULT_COST); // idivdi
997 int_def FMUL_SINGLE_COST ( 500, 5 * DEFAULT_COST); // fmul, fmadd
998 int_def FMUL_DOUBLE_COST ( 700, 7 * DEFAULT_COST); // fmul, fmadd
999 int_def FDIV_COST ( 2000, 20 * DEFAULT_COST); // fdiv
1000 int_def FSQRT_COST ( 2500, 25 * DEFAULT_COST); // fsqrt
1001 int_def VOLATILE_REF_COST ( 1000, 10 * DEFAULT_COST);
1002 int_def CACHE_MISS_COST ( 2000, 20 * DEFAULT_COST); // typicall cache miss penalty
1003 %}
1004
1005
1006
1007 //----------SOURCE BLOCK-------------------------------------------------------
1008 // This is a block of C++ code which provides values, functions, and
1009 // definitions necessary in the rest of the architecture description
1010
1011 source_hpp %{
1012
1013 #include "asm/macroAssembler.hpp"
1014 #include "gc/shared/barrierSetAssembler.hpp"
1015 #include "gc/shared/cardTable.hpp"
1016 #include "gc/shared/cardTableBarrierSet.hpp"
1017 #include "gc/shared/collectedHeap.hpp"
1018 #include "opto/addnode.hpp"
1019 #include "opto/convertnode.hpp"
1020 #include "runtime/objectMonitor.hpp"
1021
1022 extern RegMask _ANY_REG32_mask;
1023 extern RegMask _ANY_REG_mask;
1024 extern RegMask _PTR_REG_mask;
1025 extern RegMask _NO_SPECIAL_REG32_mask;
1026 extern RegMask _NO_SPECIAL_REG_mask;
1027 extern RegMask _NO_SPECIAL_PTR_REG_mask;
1028 extern RegMask _NO_SPECIAL_NO_FP_PTR_REG_mask;
1029
1030 class CallStubImpl {
1031
1032 //--------------------------------------------------------------
1033 //---< Used for optimization in Compile::shorten_branches >---
1034 //--------------------------------------------------------------
1035
1036 public:
1037 // Size of call trampoline stub.
1038 static uint size_call_trampoline() {
1039 return 0; // no call trampolines on this platform
1040 }
1041
1042 // number of relocations needed by a call trampoline stub
1043 static uint reloc_call_trampoline() {
1044 return 0; // no call trampolines on this platform
1045 }
1046 };
1047
1048 class HandlerImpl {
1049
1050 public:
1051
1052 static int emit_deopt_handler(C2_MacroAssembler* masm);
1053
1054 static uint size_deopt_handler() {
1055 // count far call + j
1056 return NativeInstruction::instruction_size + MacroAssembler::far_branch_size();
1057 }
1058 };
1059
1060 class Node::PD {
1061 public:
1062 enum NodeFlags {
1063 _last_flag = Node::_last_flag
1064 };
1065 };
1066
1067 bool is_CAS(int opcode, bool maybe_volatile);
1068
1069 // predicate controlling translation of CompareAndSwapX
1070 bool needs_acquiring_load_reserved(const Node *load);
1071
1072 // predicate controlling addressing modes
1073 bool size_fits_all_mem_uses(AddPNode* addp, int shift);
1074 %}
1075
1076 source %{
1077
1078 // Derived RegMask with conditionally allocatable registers
1079
1080 RegMask _ANY_REG32_mask;
1081 RegMask _ANY_REG_mask;
1082 RegMask _PTR_REG_mask;
1083 RegMask _NO_SPECIAL_REG32_mask;
1084 RegMask _NO_SPECIAL_REG_mask;
1085 RegMask _NO_SPECIAL_PTR_REG_mask;
1086 RegMask _NO_SPECIAL_NO_FP_PTR_REG_mask;
1087
1088 void reg_mask_init() {
1089
1090 _ANY_REG32_mask.assignFrom(_ALL_REG32_mask);
1091 _ANY_REG32_mask.remove(OptoReg::as_OptoReg(x0->as_VMReg()));
1092
1093 _ANY_REG_mask.assignFrom(_ALL_REG_mask);
1094 _ANY_REG_mask.subtract(_ZR_REG_mask);
1095
1096 _PTR_REG_mask.assignFrom(_ALL_REG_mask);
1097 _PTR_REG_mask.subtract(_ZR_REG_mask);
1098
1099 _NO_SPECIAL_REG32_mask.assignFrom(_ALL_REG32_mask);
1100 _NO_SPECIAL_REG32_mask.subtract(_NON_ALLOCATABLE_REG32_mask);
1101
1102 _NO_SPECIAL_REG_mask.assignFrom(_ALL_REG_mask);
1103 _NO_SPECIAL_REG_mask.subtract(_NON_ALLOCATABLE_REG_mask);
1104
1105 _NO_SPECIAL_PTR_REG_mask.assignFrom(_ALL_REG_mask);
1106 _NO_SPECIAL_PTR_REG_mask.subtract(_NON_ALLOCATABLE_REG_mask);
1107
1108 // x27 is not allocatable when compressed oops is on
1109 if (UseCompressedOops) {
1110 _NO_SPECIAL_REG32_mask.remove(OptoReg::as_OptoReg(x27->as_VMReg()));
1111 _NO_SPECIAL_REG_mask.remove(OptoReg::as_OptoReg(x27->as_VMReg()));
1112 _NO_SPECIAL_PTR_REG_mask.remove(OptoReg::as_OptoReg(x27->as_VMReg()));
1113 }
1114
1115 // x8 is not allocatable when PreserveFramePointer is on
1116 if (PreserveFramePointer) {
1117 _NO_SPECIAL_REG32_mask.remove(OptoReg::as_OptoReg(x8->as_VMReg()));
1118 _NO_SPECIAL_REG_mask.remove(OptoReg::as_OptoReg(x8->as_VMReg()));
1119 _NO_SPECIAL_PTR_REG_mask.remove(OptoReg::as_OptoReg(x8->as_VMReg()));
1120 }
1121
1122 _NO_SPECIAL_NO_FP_PTR_REG_mask.assignFrom(_NO_SPECIAL_PTR_REG_mask);
1123 _NO_SPECIAL_NO_FP_PTR_REG_mask.remove(OptoReg::as_OptoReg(x8->as_VMReg()));
1124 }
1125
1126 void PhaseOutput::pd_perform_mach_node_analysis() {
1127 }
1128
1129 int MachNode::pd_alignment_required() const {
1130 return 1;
1131 }
1132
1133 int MachNode::compute_padding(int current_offset) const {
1134 return 0;
1135 }
1136
1137 // is_CAS(int opcode, bool maybe_volatile)
1138 //
1139 // return true if opcode is one of the possible CompareAndSwapX
1140 // values otherwise false.
1141 bool is_CAS(int opcode, bool maybe_volatile)
1142 {
1143 switch (opcode) {
1144 // We handle these
1145 case Op_CompareAndSwapI:
1146 case Op_CompareAndSwapL:
1147 case Op_CompareAndSwapP:
1148 case Op_CompareAndSwapN:
1149 case Op_ShenandoahCompareAndSwapP:
1150 case Op_ShenandoahCompareAndSwapN:
1151 case Op_CompareAndSwapB:
1152 case Op_CompareAndSwapS:
1153 case Op_GetAndSetI:
1154 case Op_GetAndSetL:
1155 case Op_GetAndSetP:
1156 case Op_GetAndSetN:
1157 case Op_GetAndAddI:
1158 case Op_GetAndAddL:
1159 return true;
1160 case Op_CompareAndExchangeI:
1161 case Op_CompareAndExchangeN:
1162 case Op_CompareAndExchangeB:
1163 case Op_CompareAndExchangeS:
1164 case Op_CompareAndExchangeL:
1165 case Op_CompareAndExchangeP:
1166 case Op_WeakCompareAndSwapB:
1167 case Op_WeakCompareAndSwapS:
1168 case Op_WeakCompareAndSwapI:
1169 case Op_WeakCompareAndSwapL:
1170 case Op_WeakCompareAndSwapP:
1171 case Op_WeakCompareAndSwapN:
1172 case Op_ShenandoahWeakCompareAndSwapP:
1173 case Op_ShenandoahWeakCompareAndSwapN:
1174 case Op_ShenandoahCompareAndExchangeP:
1175 case Op_ShenandoahCompareAndExchangeN:
1176 return maybe_volatile;
1177 default:
1178 return false;
1179 }
1180 }
1181
1182 constexpr uint64_t MAJIK_DWORD = 0xabbaabbaabbaabbaull;
1183
1184 // predicate controlling translation of CAS
1185 //
1186 // returns true if CAS needs to use an acquiring load otherwise false
1187 bool needs_acquiring_load_reserved(const Node *n)
1188 {
1189 assert(n != nullptr && is_CAS(n->Opcode(), true), "expecting a compare and swap");
1190
1191 LoadStoreNode* ldst = n->as_LoadStore();
1192 if (n != nullptr && is_CAS(n->Opcode(), false)) {
1193 assert(ldst != nullptr && ldst->trailing_membar() != nullptr, "expected trailing membar");
1194 } else {
1195 return ldst != nullptr && ldst->trailing_membar() != nullptr;
1196 }
1197 // so we can just return true here
1198 return true;
1199 }
1200 #define __ masm->
1201
1202 // advance declarations for helper functions to convert register
1203 // indices to register objects
1204
1205 // the ad file has to provide implementations of certain methods
1206 // expected by the generic code
1207 //
1208 // REQUIRED FUNCTIONALITY
1209
1210 //=============================================================================
1211
1212 // !!!!! Special hack to get all types of calls to specify the byte offset
1213 // from the start of the call to the point where the return address
1214 // will point.
1215
1216 int MachCallStaticJavaNode::ret_addr_offset()
1217 {
1218 return 3 * NativeInstruction::instruction_size; // auipc + ld + jalr
1219 }
1220
1221 int MachCallDynamicJavaNode::ret_addr_offset()
1222 {
1223 return NativeMovConstReg::movptr2_instruction_size + (3 * NativeInstruction::instruction_size); // movptr2, auipc + ld + jal
1224 }
1225
1226 int MachCallRuntimeNode::ret_addr_offset() {
1227 // For address inside the code cache the call will be:
1228 // auipc + jalr
1229 // For real runtime callouts it will be 8 instructions
1230 // see riscv_enc_java_to_runtime
1231 // la(t0, retaddr) -> auipc + addi
1232 // sd(t0, Address(xthread, JavaThread::last_Java_pc_offset())) -> sd
1233 // movptr(t1, addr, offset, t0) -> lui + lui + slli + add
1234 // jalr(t1, offset) -> jalr
1235 if (CodeCache::contains(_entry_point)) {
1236 return 2 * NativeInstruction::instruction_size;
1237 } else {
1238 return 8 * NativeInstruction::instruction_size;
1239 }
1240 }
1241
1242 //
1243 // Compute padding required for nodes which need alignment
1244 //
1245
1246 // With RVC a call instruction may get 2-byte aligned.
1247 // The address of the call instruction needs to be 4-byte aligned to
1248 // ensure that it does not span a cache line so that it can be patched.
1249 int CallStaticJavaDirectNode::compute_padding(int current_offset) const
1250 {
1251 // to make sure the address of jal 4-byte aligned.
1252 return align_up(current_offset, alignment_required()) - current_offset;
1253 }
1254
1255 // With RVC a call instruction may get 2-byte aligned.
1256 // The address of the call instruction needs to be 4-byte aligned to
1257 // ensure that it does not span a cache line so that it can be patched.
1258 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const
1259 {
1260 // skip the movptr2 in MacroAssembler::ic_call():
1261 // lui, lui, slli, add, addi
1262 // Though movptr2() has already 4-byte aligned with or without RVC,
1263 // We need to prevent from further changes by explicitly calculating the size.
1264 current_offset += NativeMovConstReg::movptr2_instruction_size;
1265 // to make sure the address of jal 4-byte aligned.
1266 return align_up(current_offset, alignment_required()) - current_offset;
1267 }
1268
1269 int CallRuntimeDirectNode::compute_padding(int current_offset) const
1270 {
1271 return align_up(current_offset, alignment_required()) - current_offset;
1272 }
1273
1274 int CallLeafDirectNode::compute_padding(int current_offset) const
1275 {
1276 return align_up(current_offset, alignment_required()) - current_offset;
1277 }
1278
1279 int CallLeafDirectVectorNode::compute_padding(int current_offset) const
1280 {
1281 return align_up(current_offset, alignment_required()) - current_offset;
1282 }
1283
1284 int CallLeafNoFPDirectNode::compute_padding(int current_offset) const
1285 {
1286 return align_up(current_offset, alignment_required()) - current_offset;
1287 }
1288
1289 //=============================================================================
1290
1291 #ifndef PRODUCT
1292 void MachBreakpointNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1293 assert_cond(st != nullptr);
1294 st->print("BREAKPOINT");
1295 }
1296 #endif
1297
1298 void MachBreakpointNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
1299 __ ebreak();
1300 }
1301
1302 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
1303 return MachNode::size(ra_);
1304 }
1305
1306 //=============================================================================
1307
1308 #ifndef PRODUCT
1309 void MachNopNode::format(PhaseRegAlloc*, outputStream* st) const {
1310 st->print("nop \t# %d bytes pad for loops and calls", _count);
1311 }
1312 #endif
1313
1314 void MachNopNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc*) const {
1315 Assembler::CompressibleScope scope(masm); // nops shall be 2-byte under RVC for alignment purposes.
1316 for (int i = 0; i < _count; i++) {
1317 __ nop();
1318 }
1319 }
1320
1321 uint MachNopNode::size(PhaseRegAlloc*) const {
1322 return _count * (UseRVC ? NativeInstruction::compressed_instruction_size : NativeInstruction::instruction_size);
1323 }
1324
1325 //=============================================================================
1326 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::EMPTY;
1327
1328 int ConstantTable::calculate_table_base_offset() const {
1329 return 0; // absolute addressing, no offset
1330 }
1331
1332 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
1333 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
1334 ShouldNotReachHere();
1335 }
1336
1337 void MachConstantBaseNode::emit(C2_MacroAssembler* masm, PhaseRegAlloc* ra_) const {
1338 // Empty encoding
1339 }
1340
1341 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
1342 return 0;
1343 }
1344
1345 #ifndef PRODUCT
1346 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1347 assert_cond(st != nullptr);
1348 st->print("-- \t// MachConstantBaseNode (empty encoding)");
1349 }
1350 #endif
1351
1352 #ifndef PRODUCT
1353 void MachPrologNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1354 assert_cond(st != nullptr && ra_ != nullptr);
1355 Compile* C = ra_->C;
1356
1357 int framesize = C->output()->frame_slots() << LogBytesPerInt;
1358
1359 if (C->output()->need_stack_bang(framesize)) {
1360 st->print("# stack bang size=%d\n\t", framesize);
1361 }
1362
1363 st->print("sub sp, sp, #%d\n\t", framesize);
1364 st->print("sd fp, [sp, #%d]\n\t", framesize - 2 * wordSize);
1365 st->print("sd ra, [sp, #%d]\n\t", framesize - wordSize);
1366 if (PreserveFramePointer) { st->print("add fp, sp, #%d\n\t", framesize); }
1367
1368 if (VerifyStackAtCalls) {
1369 st->print("mv t2, %ld\n\t", MAJIK_DWORD);
1370 st->print("sd t2, [sp, #%d]\n\t", framesize - 3 * wordSize);
1371 }
1372
1373 if (C->stub_function() == nullptr) {
1374 st->print("ld t0, [guard]\n\t");
1375 st->print("membar LoadLoad\n\t");
1376 st->print("ld t1, [xthread, #thread_disarmed_guard_value_offset]\n\t");
1377 st->print("beq t0, t1, skip\n\t");
1378 st->print("jalr #nmethod_entry_barrier_stub\n\t");
1379 st->print("j skip\n\t");
1380 st->print("guard: int\n\t");
1381 st->print("skip:\n\t");
1382 }
1383 }
1384 #endif
1385
1386 void MachPrologNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
1387 assert_cond(ra_ != nullptr);
1388 Compile* C = ra_->C;
1389
1390 // n.b. frame size includes space for return pc and fp
1391 const int framesize = C->output()->frame_size_in_bytes();
1392
1393 assert_cond(C != nullptr);
1394
1395 if (C->clinit_barrier_on_entry()) {
1396 assert(!C->method()->holder()->is_not_initialized(), "initialization should have been started");
1397
1398 Label L_skip_barrier;
1399
1400 __ mov_metadata(t1, C->method()->holder()->constant_encoding());
1401 __ clinit_barrier(t1, t0, &L_skip_barrier);
1402 __ far_jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub()));
1403 __ bind(L_skip_barrier);
1404 }
1405
1406 int bangsize = C->output()->bang_size_in_bytes();
1407 if (C->output()->need_stack_bang(bangsize)) {
1408 __ generate_stack_overflow_check(bangsize);
1409 }
1410
1411 __ build_frame(framesize);
1412
1413 if (VerifyStackAtCalls) {
1414 __ mv(t2, MAJIK_DWORD);
1415 __ sd(t2, Address(sp, framesize - 3 * wordSize));
1416 }
1417
1418 if (C->stub_function() == nullptr) {
1419 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
1420 // Dummy labels for just measuring the code size
1421 Label dummy_slow_path;
1422 Label dummy_continuation;
1423 Label dummy_guard;
1424 Label* slow_path = &dummy_slow_path;
1425 Label* continuation = &dummy_continuation;
1426 Label* guard = &dummy_guard;
1427 if (!Compile::current()->output()->in_scratch_emit_size()) {
1428 // Use real labels from actual stub when not emitting code for purpose of measuring its size
1429 C2EntryBarrierStub* stub = new (Compile::current()->comp_arena()) C2EntryBarrierStub();
1430 Compile::current()->output()->add_stub(stub);
1431 slow_path = &stub->entry();
1432 continuation = &stub->continuation();
1433 guard = &stub->guard();
1434 }
1435 // In the C2 code, we move the non-hot part of nmethod entry barriers out-of-line to a stub.
1436 bs->nmethod_entry_barrier(masm, slow_path, continuation, guard);
1437 }
1438
1439 C->output()->set_frame_complete(__ offset());
1440
1441 if (C->has_mach_constant_base_node()) {
1442 // NOTE: We set the table base offset here because users might be
1443 // emitted before MachConstantBaseNode.
1444 ConstantTable& constant_table = C->output()->constant_table();
1445 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
1446 }
1447 }
1448
1449 uint MachPrologNode::size(PhaseRegAlloc* ra_) const
1450 {
1451 assert_cond(ra_ != nullptr);
1452 return MachNode::size(ra_); // too many variables; just compute it
1453 // the hard way
1454 }
1455
1456 int MachPrologNode::reloc() const
1457 {
1458 return 0;
1459 }
1460
1461 //=============================================================================
1462
1463 #ifndef PRODUCT
1464 void MachEpilogNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1465 assert_cond(st != nullptr && ra_ != nullptr);
1466 Compile* C = ra_->C;
1467 assert_cond(C != nullptr);
1468 int framesize = C->output()->frame_size_in_bytes();
1469
1470 st->print("# pop frame %d\n\t", framesize);
1471
1472 if (framesize == 0) {
1473 st->print("ld ra, [sp,#%d]\n\t", (2 * wordSize));
1474 st->print("ld fp, [sp,#%d]\n\t", (3 * wordSize));
1475 st->print("add sp, sp, #%d\n\t", (2 * wordSize));
1476 } else {
1477 st->print("add sp, sp, #%d\n\t", framesize);
1478 st->print("ld ra, [sp,#%d]\n\t", - 2 * wordSize);
1479 st->print("ld fp, [sp,#%d]\n\t", - wordSize);
1480 }
1481
1482 if (do_polling() && C->is_method_compilation()) {
1483 st->print("# test polling word\n\t");
1484 st->print("ld t0, [xthread,#%d]\n\t", in_bytes(JavaThread::polling_word_offset()));
1485 st->print("bgtu sp, t0, #slow_path");
1486 }
1487 }
1488 #endif
1489
1490 void MachEpilogNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
1491 assert_cond(ra_ != nullptr);
1492 Compile* C = ra_->C;
1493 assert_cond(C != nullptr);
1494 int framesize = C->output()->frame_size_in_bytes();
1495
1496 __ remove_frame(framesize);
1497
1498 if (StackReservedPages > 0 && C->has_reserved_stack_access()) {
1499 __ reserved_stack_check();
1500 }
1501
1502 if (do_polling() && C->is_method_compilation()) {
1503 Label dummy_label;
1504 Label* code_stub = &dummy_label;
1505 if (!C->output()->in_scratch_emit_size()) {
1506 C2SafepointPollStub* stub = new (C->comp_arena()) C2SafepointPollStub(__ offset());
1507 C->output()->add_stub(stub);
1508 code_stub = &stub->entry();
1509 }
1510 __ relocate(relocInfo::poll_return_type);
1511 __ safepoint_poll(*code_stub, true /* at_return */, true /* in_nmethod */);
1512 }
1513 }
1514
1515 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
1516 assert_cond(ra_ != nullptr);
1517 // Variable size. Determine dynamically.
1518 return MachNode::size(ra_);
1519 }
1520
1521 int MachEpilogNode::reloc() const {
1522 // Return number of relocatable values contained in this instruction.
1523 return 1; // 1 for polling page.
1524 }
1525 const Pipeline * MachEpilogNode::pipeline() const {
1526 return MachNode::pipeline_class();
1527 }
1528
1529 //=============================================================================
1530
1531 // Figure out which register class each belongs in: rc_int, rc_float or
1532 // rc_stack.
1533 enum RC { rc_bad, rc_int, rc_float, rc_vector, rc_stack };
1534
1535 static enum RC rc_class(OptoReg::Name reg) {
1536
1537 if (reg == OptoReg::Bad) {
1538 return rc_bad;
1539 }
1540
1541 // we have 30 int registers * 2 halves
1542 // (t0 and t1 are omitted)
1543 int slots_of_int_registers = Register::max_slots_per_register * (Register::number_of_registers - 2);
1544 if (reg < slots_of_int_registers) {
1545 return rc_int;
1546 }
1547
1548 // we have 32 float register * 2 halves
1549 int slots_of_float_registers = FloatRegister::max_slots_per_register * FloatRegister::number_of_registers;
1550 if (reg < slots_of_int_registers + slots_of_float_registers) {
1551 return rc_float;
1552 }
1553
1554 // we have 32 vector register * 4 halves
1555 int slots_of_vector_registers = VectorRegister::max_slots_per_register * VectorRegister::number_of_registers;
1556 if (reg < slots_of_int_registers + slots_of_float_registers + slots_of_vector_registers) {
1557 return rc_vector;
1558 }
1559
1560 // Between vector regs & stack is the flags regs.
1561 assert(OptoReg::is_stack(reg), "blow up if spilling flags");
1562
1563 return rc_stack;
1564 }
1565
1566 uint MachSpillCopyNode::implementation(C2_MacroAssembler *masm, PhaseRegAlloc *ra_, bool do_size, outputStream *st) const {
1567 assert_cond(ra_ != nullptr);
1568 Compile* C = ra_->C;
1569
1570 // Get registers to move.
1571 OptoReg::Name src_hi = ra_->get_reg_second(in(1));
1572 OptoReg::Name src_lo = ra_->get_reg_first(in(1));
1573 OptoReg::Name dst_hi = ra_->get_reg_second(this);
1574 OptoReg::Name dst_lo = ra_->get_reg_first(this);
1575
1576 enum RC src_hi_rc = rc_class(src_hi);
1577 enum RC src_lo_rc = rc_class(src_lo);
1578 enum RC dst_hi_rc = rc_class(dst_hi);
1579 enum RC dst_lo_rc = rc_class(dst_lo);
1580
1581 assert(src_lo != OptoReg::Bad && dst_lo != OptoReg::Bad, "must move at least 1 register");
1582
1583 if (src_hi != OptoReg::Bad && !bottom_type()->isa_pvectmask()) {
1584 assert((src_lo & 1) == 0 && src_lo + 1 == src_hi &&
1585 (dst_lo & 1) == 0 && dst_lo + 1 == dst_hi,
1586 "expected aligned-adjacent pairs");
1587 }
1588
1589 if (src_lo == dst_lo && src_hi == dst_hi) {
1590 return 0; // Self copy, no move.
1591 }
1592
1593 bool is64 = (src_lo & 1) == 0 && src_lo + 1 == src_hi &&
1594 (dst_lo & 1) == 0 && dst_lo + 1 == dst_hi;
1595 int src_offset = ra_->reg2offset(src_lo);
1596 int dst_offset = ra_->reg2offset(dst_lo);
1597
1598 if (bottom_type()->isa_vect() != nullptr) {
1599 uint ireg = ideal_reg();
1600 if (ireg == Op_VecA && masm) {
1601 int vector_reg_size_in_bytes = Matcher::scalable_vector_reg_size(T_BYTE);
1602 if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
1603 // stack to stack
1604 __ spill_copy_vector_stack_to_stack(src_offset, dst_offset,
1605 vector_reg_size_in_bytes);
1606 } else if (src_lo_rc == rc_vector && dst_lo_rc == rc_stack) {
1607 // vpr to stack
1608 __ spill(as_VectorRegister(Matcher::_regEncode[src_lo]), ra_->reg2offset(dst_lo));
1609 } else if (src_lo_rc == rc_stack && dst_lo_rc == rc_vector) {
1610 // stack to vpr
1611 __ unspill(as_VectorRegister(Matcher::_regEncode[dst_lo]), ra_->reg2offset(src_lo));
1612 } else if (src_lo_rc == rc_vector && dst_lo_rc == rc_vector) {
1613 // vpr to vpr
1614 __ vsetvli_helper(T_BYTE, MaxVectorSize);
1615 __ vmv_v_v(as_VectorRegister(Matcher::_regEncode[dst_lo]), as_VectorRegister(Matcher::_regEncode[src_lo]));
1616 } else {
1617 ShouldNotReachHere();
1618 }
1619 } else if (bottom_type()->isa_pvectmask() && masm) {
1620 int vmask_size_in_bytes = Matcher::scalable_predicate_reg_slots() * 32 / 8;
1621 if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
1622 // stack to stack
1623 __ spill_copy_vmask_stack_to_stack(src_offset, dst_offset,
1624 vmask_size_in_bytes);
1625 } else if (src_lo_rc == rc_vector && dst_lo_rc == rc_stack) {
1626 // vmask to stack
1627 __ spill_vmask(as_VectorRegister(Matcher::_regEncode[src_lo]), ra_->reg2offset(dst_lo));
1628 } else if (src_lo_rc == rc_stack && dst_lo_rc == rc_vector) {
1629 // stack to vmask
1630 __ unspill_vmask(as_VectorRegister(Matcher::_regEncode[dst_lo]), ra_->reg2offset(src_lo));
1631 } else if (src_lo_rc == rc_vector && dst_lo_rc == rc_vector) {
1632 // vmask to vmask
1633 __ vsetvli_helper(T_BYTE, MaxVectorSize >> 3);
1634 __ vmv_v_v(as_VectorRegister(Matcher::_regEncode[dst_lo]), as_VectorRegister(Matcher::_regEncode[src_lo]));
1635 } else {
1636 ShouldNotReachHere();
1637 }
1638 }
1639 } else if (masm != nullptr) {
1640 switch (src_lo_rc) {
1641 case rc_int:
1642 if (dst_lo_rc == rc_int) { // gpr --> gpr copy
1643 if (!is64 && this->ideal_reg() != Op_RegI) { // zero extended for narrow oop or klass
1644 __ zext(as_Register(Matcher::_regEncode[dst_lo]), as_Register(Matcher::_regEncode[src_lo]), 32);
1645 } else {
1646 __ mv(as_Register(Matcher::_regEncode[dst_lo]), as_Register(Matcher::_regEncode[src_lo]));
1647 }
1648 } else if (dst_lo_rc == rc_float) { // gpr --> fpr copy
1649 if (is64) {
1650 __ fmv_d_x(as_FloatRegister(Matcher::_regEncode[dst_lo]),
1651 as_Register(Matcher::_regEncode[src_lo]));
1652 } else {
1653 __ fmv_w_x(as_FloatRegister(Matcher::_regEncode[dst_lo]),
1654 as_Register(Matcher::_regEncode[src_lo]));
1655 }
1656 } else { // gpr --> stack spill
1657 assert(dst_lo_rc == rc_stack, "spill to bad register class");
1658 __ spill(as_Register(Matcher::_regEncode[src_lo]), is64, dst_offset);
1659 }
1660 break;
1661 case rc_float:
1662 if (dst_lo_rc == rc_int) { // fpr --> gpr copy
1663 if (is64) {
1664 __ fmv_x_d(as_Register(Matcher::_regEncode[dst_lo]),
1665 as_FloatRegister(Matcher::_regEncode[src_lo]));
1666 } else {
1667 __ fmv_x_w(as_Register(Matcher::_regEncode[dst_lo]),
1668 as_FloatRegister(Matcher::_regEncode[src_lo]));
1669 }
1670 } else if (dst_lo_rc == rc_float) { // fpr --> fpr copy
1671 if (is64) {
1672 __ fmv_d(as_FloatRegister(Matcher::_regEncode[dst_lo]),
1673 as_FloatRegister(Matcher::_regEncode[src_lo]));
1674 } else {
1675 __ fmv_s(as_FloatRegister(Matcher::_regEncode[dst_lo]),
1676 as_FloatRegister(Matcher::_regEncode[src_lo]));
1677 }
1678 } else { // fpr --> stack spill
1679 assert(dst_lo_rc == rc_stack, "spill to bad register class");
1680 __ spill(as_FloatRegister(Matcher::_regEncode[src_lo]),
1681 is64, dst_offset);
1682 }
1683 break;
1684 case rc_stack:
1685 if (dst_lo_rc == rc_int) { // stack --> gpr load
1686 if (this->ideal_reg() == Op_RegI) {
1687 __ unspill(as_Register(Matcher::_regEncode[dst_lo]), is64, src_offset);
1688 } else { // // zero extended for narrow oop or klass
1689 __ unspillu(as_Register(Matcher::_regEncode[dst_lo]), is64, src_offset);
1690 }
1691 } else if (dst_lo_rc == rc_float) { // stack --> fpr load
1692 __ unspill(as_FloatRegister(Matcher::_regEncode[dst_lo]),
1693 is64, src_offset);
1694 } else { // stack --> stack copy
1695 assert(dst_lo_rc == rc_stack, "spill to bad register class");
1696 if (this->ideal_reg() == Op_RegI) {
1697 __ unspill(t0, is64, src_offset);
1698 } else { // zero extended for narrow oop or klass
1699 __ unspillu(t0, is64, src_offset);
1700 }
1701 __ spill(t0, is64, dst_offset);
1702 }
1703 break;
1704 default:
1705 ShouldNotReachHere();
1706 }
1707 }
1708
1709 if (st != nullptr) {
1710 st->print("spill ");
1711 if (src_lo_rc == rc_stack) {
1712 st->print("[sp, #%d] -> ", src_offset);
1713 } else {
1714 st->print("%s -> ", Matcher::regName[src_lo]);
1715 }
1716 if (dst_lo_rc == rc_stack) {
1717 st->print("[sp, #%d]", dst_offset);
1718 } else {
1719 st->print("%s", Matcher::regName[dst_lo]);
1720 }
1721 if (bottom_type()->isa_vect() && !bottom_type()->isa_pvectmask()) {
1722 int vsize = 0;
1723 if (ideal_reg() == Op_VecA) {
1724 vsize = Matcher::scalable_vector_reg_size(T_BYTE) * 8;
1725 } else {
1726 ShouldNotReachHere();
1727 }
1728 st->print("\t# vector spill size = %d", vsize);
1729 } else if (ideal_reg() == Op_RegVectMask) {
1730 assert(Matcher::supports_scalable_vector(), "bad register type for spill");
1731 int vsize = Matcher::scalable_predicate_reg_slots() * 32;
1732 st->print("\t# vmask spill size = %d", vsize);
1733 } else {
1734 st->print("\t# spill size = %d", is64 ? 64 : 32);
1735 }
1736 }
1737
1738 return 0;
1739 }
1740
1741 #ifndef PRODUCT
1742 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1743 if (ra_ == nullptr) {
1744 st->print("N%d = SpillCopy(N%d)", _idx, in(1)->_idx);
1745 } else {
1746 implementation(nullptr, ra_, false, st);
1747 }
1748 }
1749 #endif
1750
1751 void MachSpillCopyNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
1752 implementation(masm, ra_, false, nullptr);
1753 }
1754
1755 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1756 return MachNode::size(ra_);
1757 }
1758
1759 //=============================================================================
1760
1761 #ifndef PRODUCT
1762 void BoxLockNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1763 assert_cond(ra_ != nullptr && st != nullptr);
1764 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1765 int reg = ra_->get_reg_first(this);
1766 st->print("add %s, sp, #%d\t# box lock",
1767 Matcher::regName[reg], offset);
1768 }
1769 #endif
1770
1771 void BoxLockNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
1772 Assembler::IncompressibleScope scope(masm); // Fixed length: see BoxLockNode::size()
1773
1774 assert_cond(ra_ != nullptr);
1775 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1776 int reg = ra_->get_encode(this);
1777
1778 if (Assembler::is_simm12(offset)) {
1779 __ addi(as_Register(reg), sp, offset);
1780 } else {
1781 __ li32(t0, offset);
1782 __ add(as_Register(reg), sp, t0);
1783 }
1784 }
1785
1786 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1787 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_).
1788 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1789
1790 if (Assembler::is_simm12(offset)) {
1791 return NativeInstruction::instruction_size;
1792 } else {
1793 return 3 * NativeInstruction::instruction_size; // lui + addiw + add;
1794 }
1795 }
1796
1797 //=============================================================================
1798
1799 #ifndef PRODUCT
1800 void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1801 {
1802 assert_cond(st != nullptr);
1803 st->print_cr("# MachUEPNode");
1804 st->print_cr("\tlwu t1, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass");
1805 st->print_cr("\tlwu t2, [t0 + CompiledICData::speculated_klass_offset()]\t# compressed klass");
1806 st->print_cr("\tbeq t1, t2, ic_hit");
1807 st->print_cr("\tj, SharedRuntime::_ic_miss_stub\t # Inline cache check");
1808 st->print_cr("\tic_hit:");
1809 }
1810 #endif
1811
1812 void MachUEPNode::emit(C2_MacroAssembler* masm, PhaseRegAlloc* ra_) const
1813 {
1814 // This is the unverified entry point.
1815 __ ic_check(CodeEntryAlignment);
1816
1817 // ic_check() aligns to CodeEntryAlignment >= InteriorEntryAlignment(min 16) > NativeInstruction::instruction_size(4).
1818 assert(((__ offset()) % CodeEntryAlignment) == 0, "Misaligned verified entry point");
1819 }
1820
1821 uint MachUEPNode::size(PhaseRegAlloc* ra_) const
1822 {
1823 assert_cond(ra_ != nullptr);
1824 return MachNode::size(ra_);
1825 }
1826
1827 // REQUIRED EMIT CODE
1828
1829 //=============================================================================
1830
1831 // Emit deopt handler code.
1832 int HandlerImpl::emit_deopt_handler(C2_MacroAssembler* masm)
1833 {
1834 address base = __ start_a_stub(size_deopt_handler());
1835 if (base == nullptr) {
1836 ciEnv::current()->record_failure("CodeCache is full");
1837 return 0; // CodeBuffer::expand failed
1838 }
1839 int offset = __ offset();
1840
1841 Label start;
1842 __ bind(start);
1843
1844 __ far_call(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
1845
1846 int entry_offset = __ offset();
1847 __ j(start);
1848
1849 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1850 assert(__ offset() - entry_offset >= NativePostCallNop::first_check_size,
1851 "out of bounds read in post-call NOP check");
1852 __ end_a_stub();
1853 return entry_offset;
1854
1855 }
1856 // REQUIRED MATCHER CODE
1857
1858 //=============================================================================
1859
1860 bool Matcher::match_rule_supported(int opcode) {
1861 if (!has_match_rule(opcode)) {
1862 return false;
1863 }
1864
1865 switch (opcode) {
1866 case Op_OnSpinWait:
1867 return VM_Version::supports_on_spin_wait();
1868 case Op_CacheWB: // fall through
1869 case Op_CacheWBPreSync: // fall through
1870 case Op_CacheWBPostSync:
1871 if (!VM_Version::supports_data_cache_line_flush()) {
1872 return false;
1873 }
1874 break;
1875
1876 case Op_StrCompressedCopy: // fall through
1877 case Op_StrInflatedCopy: // fall through
1878 case Op_CountPositives: // fall through
1879 case Op_EncodeISOArray:
1880 return UseRVV;
1881
1882 case Op_PopCountI:
1883 case Op_PopCountL:
1884 return UsePopCountInstruction;
1885
1886 case Op_ReverseI:
1887 case Op_ReverseL:
1888 return UseZbkb;
1889
1890 case Op_ReverseBytesI:
1891 case Op_ReverseBytesL:
1892 case Op_ReverseBytesS:
1893 case Op_ReverseBytesUS:
1894 case Op_RotateRight:
1895 case Op_RotateLeft:
1896 case Op_CountLeadingZerosI:
1897 case Op_CountLeadingZerosL:
1898 case Op_CountTrailingZerosI:
1899 case Op_CountTrailingZerosL:
1900 return UseZbb;
1901
1902 case Op_FmaF:
1903 case Op_FmaD:
1904 return UseFMA;
1905
1906 case Op_ConvHF2F:
1907 case Op_ConvF2HF:
1908 return VM_Version::supports_float16_float_conversion();
1909 case Op_ReinterpretS2HF:
1910 case Op_ReinterpretHF2S:
1911 return UseZfh || UseZfhmin;
1912 case Op_AddHF:
1913 case Op_DivHF:
1914 case Op_FmaHF:
1915 case Op_MaxHF:
1916 case Op_MinHF:
1917 case Op_MulHF:
1918 case Op_SqrtHF:
1919 case Op_SubHF:
1920 return UseZfh;
1921
1922 case Op_CMoveP:
1923 case Op_CMoveN:
1924 return false;
1925 }
1926
1927 return true; // Per default match rules are supported.
1928 }
1929
1930 const RegMask* Matcher::predicate_reg_mask(void) {
1931 return &_VMASK_REG_mask;
1932 }
1933
1934 // Vector calling convention not yet implemented.
1935 bool Matcher::supports_vector_calling_convention(void) {
1936 return EnableVectorSupport;
1937 }
1938
1939 OptoRegPair Matcher::vector_return_value(uint ideal_reg) {
1940 assert(EnableVectorSupport, "sanity");
1941 assert(ideal_reg == Op_VecA, "sanity");
1942 // check more info at https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-cc.adoc
1943 int lo = V8_num;
1944 int hi = V8_K_num;
1945 return OptoRegPair(hi, lo);
1946 }
1947
1948 // Is this branch offset short enough that a short branch can be used?
1949 //
1950 // NOTE: If the platform does not provide any short branch variants, then
1951 // this method should return false for offset 0.
1952 // |---label(L1)-----|
1953 // |-----------------|
1954 // |-----------------|----------eq: float-------------------
1955 // |-----------------| // far_cmpD_branch | cmpD_branch
1956 // |------- ---------| feq; | feq;
1957 // |-far_cmpD_branch-| beqz done; | bnez L;
1958 // |-----------------| j L; |
1959 // |-----------------| bind(done); |
1960 // |-----------------|--------------------------------------
1961 // |-----------------| // so shortBrSize = br_size - 4;
1962 // |-----------------| // so offs = offset - shortBrSize + 4;
1963 // |---label(L2)-----|
1964 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1965 // The passed offset is relative to address of the branch.
1966 int shortBrSize = br_size - 4;
1967 int offs = offset - shortBrSize + 4;
1968 return (-4096 <= offs && offs < 4096);
1969 }
1970
1971 // Vector width in bytes.
1972 int Matcher::vector_width_in_bytes(BasicType bt) {
1973 if (UseRVV) {
1974 // The MaxVectorSize should have been set by detecting RVV max vector register size when check UseRVV.
1975 // MaxVectorSize == VM_Version::_initial_vector_length
1976 int size = MaxVectorSize;
1977 // Minimum 2 values in vector
1978 if (size < 2 * type2aelembytes(bt)) size = 0;
1979 // But never < 4
1980 if (size < 4) size = 0;
1981 return size;
1982 }
1983 return 0;
1984 }
1985
1986 // Limits on vector size (number of elements) loaded into vector.
1987 int Matcher::max_vector_size(const BasicType bt) {
1988 return vector_width_in_bytes(bt) / type2aelembytes(bt);
1989 }
1990
1991 int Matcher::min_vector_size(const BasicType bt) {
1992 int size;
1993 switch(bt) {
1994 case T_BOOLEAN:
1995 // Load/store a vector mask with only 2 elements for vector types
1996 // such as "2I/2F/2L/2D".
1997 size = 2;
1998 break;
1999 case T_BYTE:
2000 // Generate a "4B" vector, to support vector cast between "8B/16B"
2001 // and "4S/4I/4L/4F/4D".
2002 size = 4;
2003 break;
2004 case T_SHORT:
2005 // Generate a "2S" vector, to support vector cast between "4S/8S"
2006 // and "2I/2L/2F/2D".
2007 size = 2;
2008 break;
2009 default:
2010 // Limit the min vector length to 64-bit.
2011 size = 8 / type2aelembytes(bt);
2012 // The number of elements in a vector should be at least 2.
2013 size = MAX2(size, 2);
2014 }
2015
2016 int max_size = max_vector_size(bt);
2017 return MIN2(size, max_size);
2018 }
2019
2020 int Matcher::max_vector_size_auto_vectorization(const BasicType bt) {
2021 return Matcher::max_vector_size(bt);
2022 }
2023
2024 // Vector ideal reg.
2025 uint Matcher::vector_ideal_reg(int len) {
2026 assert(MaxVectorSize >= len, "");
2027 if (UseRVV) {
2028 return Op_VecA;
2029 }
2030
2031 ShouldNotReachHere();
2032 return 0;
2033 }
2034
2035 int Matcher::scalable_vector_reg_size(const BasicType bt) {
2036 return Matcher::max_vector_size(bt);
2037 }
2038
2039 MachOper* Matcher::pd_specialize_generic_vector_operand(MachOper* original_opnd, uint ideal_reg, bool is_temp) {
2040 ShouldNotReachHere(); // generic vector operands not supported
2041 return nullptr;
2042 }
2043
2044 bool Matcher::is_reg2reg_move(MachNode* m) {
2045 ShouldNotReachHere(); // generic vector operands not supported
2046 return false;
2047 }
2048
2049 bool Matcher::is_register_biasing_candidate(const MachNode* mdef, int oper_index) {
2050 return false;
2051 }
2052
2053 bool Matcher::is_generic_vector(MachOper* opnd) {
2054 ShouldNotReachHere(); // generic vector operands not supported
2055 return false;
2056 }
2057
2058 #ifdef ASSERT
2059 // Return whether or not this register is ever used as an argument.
2060 bool Matcher::can_be_java_arg(int reg)
2061 {
2062 return
2063 reg == R10_num || reg == R10_H_num ||
2064 reg == R11_num || reg == R11_H_num ||
2065 reg == R12_num || reg == R12_H_num ||
2066 reg == R13_num || reg == R13_H_num ||
2067 reg == R14_num || reg == R14_H_num ||
2068 reg == R15_num || reg == R15_H_num ||
2069 reg == R16_num || reg == R16_H_num ||
2070 reg == R17_num || reg == R17_H_num ||
2071 reg == F10_num || reg == F10_H_num ||
2072 reg == F11_num || reg == F11_H_num ||
2073 reg == F12_num || reg == F12_H_num ||
2074 reg == F13_num || reg == F13_H_num ||
2075 reg == F14_num || reg == F14_H_num ||
2076 reg == F15_num || reg == F15_H_num ||
2077 reg == F16_num || reg == F16_H_num ||
2078 reg == F17_num || reg == F17_H_num;
2079 }
2080 #endif
2081
2082 uint Matcher::int_pressure_limit()
2083 {
2084 // A derived pointer is live at CallNode and then is flagged by RA
2085 // as a spilled LRG. Spilling heuristics(Spill-USE) explicitly skip
2086 // derived pointers and lastly fail to spill after reaching maximum
2087 // number of iterations. Lowering the default pressure threshold to
2088 // (_NO_SPECIAL_REG32_mask.size() minus 1) forces CallNode to become
2089 // a high register pressure area of the code so that split_DEF can
2090 // generate DefinitionSpillCopy for the derived pointer.
2091 uint default_int_pressure_threshold = _NO_SPECIAL_REG32_mask.size() - 1;
2092 if (!PreserveFramePointer) {
2093 // When PreserveFramePointer is off, frame pointer is allocatable,
2094 // but different from other SOC registers, it is excluded from
2095 // fatproj's mask because its save type is No-Save. Decrease 1 to
2096 // ensure high pressure at fatproj when PreserveFramePointer is off.
2097 // See check_pressure_at_fatproj().
2098 default_int_pressure_threshold--;
2099 }
2100 return (INTPRESSURE == -1) ? default_int_pressure_threshold : INTPRESSURE;
2101 }
2102
2103 uint Matcher::float_pressure_limit()
2104 {
2105 // _FLOAT_REG_mask is generated by adlc from the float_reg register class.
2106 return (FLOATPRESSURE == -1) ? _FLOAT_REG_mask.size() : FLOATPRESSURE;
2107 }
2108
2109 const RegMask& Matcher::divI_proj_mask() {
2110 ShouldNotReachHere();
2111 return RegMask::EMPTY;
2112 }
2113
2114 // Register for MODI projection of divmodI.
2115 const RegMask& Matcher::modI_proj_mask() {
2116 ShouldNotReachHere();
2117 return RegMask::EMPTY;
2118 }
2119
2120 // Register for DIVL projection of divmodL.
2121 const RegMask& Matcher::divL_proj_mask() {
2122 ShouldNotReachHere();
2123 return RegMask::EMPTY;
2124 }
2125
2126 // Register for MODL projection of divmodL.
2127 const RegMask& Matcher::modL_proj_mask() {
2128 ShouldNotReachHere();
2129 return RegMask::EMPTY;
2130 }
2131
2132 bool size_fits_all_mem_uses(AddPNode* addp, int shift) {
2133 assert_cond(addp != nullptr);
2134 for (DUIterator_Fast imax, i = addp->fast_outs(imax); i < imax; i++) {
2135 Node* u = addp->fast_out(i);
2136 if (u != nullptr && u->is_Mem()) {
2137 int opsize = u->as_Mem()->memory_size();
2138 assert(opsize > 0, "unexpected memory operand size");
2139 if (u->as_Mem()->memory_size() != (1 << shift)) {
2140 return false;
2141 }
2142 }
2143 }
2144 return true;
2145 }
2146
2147 // Binary src (Replicate scalar/immediate)
2148 static bool is_vector_scalar_bitwise_pattern(Node* n, Node* m) {
2149 if (n == nullptr || m == nullptr) {
2150 return false;
2151 }
2152
2153 if (m->Opcode() != Op_Replicate) {
2154 return false;
2155 }
2156
2157 switch (n->Opcode()) {
2158 case Op_AndV:
2159 case Op_OrV:
2160 case Op_XorV:
2161 case Op_AddVB:
2162 case Op_AddVS:
2163 case Op_AddVI:
2164 case Op_AddVL:
2165 case Op_SubVB:
2166 case Op_SubVS:
2167 case Op_SubVI:
2168 case Op_SubVL:
2169 case Op_MulVB:
2170 case Op_MulVS:
2171 case Op_MulVI:
2172 case Op_MulVL: {
2173 return true;
2174 }
2175 default:
2176 return false;
2177 }
2178 }
2179
2180 // (XorV src (Replicate m1))
2181 // (XorVMask src (MaskAll m1))
2182 static bool is_vector_bitwise_not_pattern(Node* n, Node* m) {
2183 if (n != nullptr && m != nullptr) {
2184 return (n->Opcode() == Op_XorV || n->Opcode() == Op_XorVMask) &&
2185 VectorNode::is_all_ones_vector(m);
2186 }
2187 return false;
2188 }
2189
2190 // Should the Matcher clone input 'm' of node 'n'?
2191 bool Matcher::pd_clone_node(Node* n, Node* m, Matcher::MStack& mstack) {
2192 assert_cond(m != nullptr);
2193 if (is_vshift_con_pattern(n, m) || // ShiftV src (ShiftCntV con)
2194 is_vector_bitwise_not_pattern(n, m) ||
2195 is_vector_scalar_bitwise_pattern(n, m) ||
2196 is_encode_and_store_pattern(n, m)) {
2197 mstack.push(m, Visit);
2198 return true;
2199 }
2200 return false;
2201 }
2202
2203 // Should the Matcher clone shifts on addressing modes, expecting them
2204 // to be subsumed into complex addressing expressions or compute them
2205 // into registers?
2206 bool Matcher::pd_clone_address_expressions(AddPNode* m, Matcher::MStack& mstack, VectorSet& address_visited) {
2207 return clone_base_plus_offset_address(m, mstack, address_visited);
2208 }
2209
2210 %}
2211
2212
2213
2214 //----------ENCODING BLOCK-----------------------------------------------------
2215 // This block specifies the encoding classes used by the compiler to
2216 // output byte streams. Encoding classes are parameterized macros
2217 // used by Machine Instruction Nodes in order to generate the bit
2218 // encoding of the instruction. Operands specify their base encoding
2219 // interface with the interface keyword. There are currently
2220 // supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, &
2221 // COND_INTER. REG_INTER causes an operand to generate a function
2222 // which returns its register number when queried. CONST_INTER causes
2223 // an operand to generate a function which returns the value of the
2224 // constant when queried. MEMORY_INTER causes an operand to generate
2225 // four functions which return the Base Register, the Index Register,
2226 // the Scale Value, and the Offset Value of the operand when queried.
2227 // COND_INTER causes an operand to generate six functions which return
2228 // the encoding code (ie - encoding bits for the instruction)
2229 // associated with each basic boolean condition for a conditional
2230 // instruction.
2231 //
2232 // Instructions specify two basic values for encoding. Again, a
2233 // function is available to check if the constant displacement is an
2234 // oop. They use the ins_encode keyword to specify their encoding
2235 // classes (which must be a sequence of enc_class names, and their
2236 // parameters, specified in the encoding block), and they use the
2237 // opcode keyword to specify, in order, their primary, secondary, and
2238 // tertiary opcode. Only the opcode sections which a particular
2239 // instruction needs for encoding need to be specified.
2240 encode %{
2241 // BEGIN Non-volatile memory access
2242
2243 enc_class riscv_enc_mov_imm(iRegIorL dst, immIorL src) %{
2244 int64_t con = (int64_t)$src$$constant;
2245 Register dst_reg = as_Register($dst$$reg);
2246 __ mv(dst_reg, con);
2247 %}
2248
2249 enc_class riscv_enc_mov_p(iRegP dst, immP src) %{
2250 Register dst_reg = as_Register($dst$$reg);
2251 address con = (address)$src$$constant;
2252 if (con == nullptr || con == (address)1) {
2253 ShouldNotReachHere();
2254 } else {
2255 relocInfo::relocType rtype = $src->constant_reloc();
2256 if (rtype == relocInfo::oop_type) {
2257 __ movoop(dst_reg, (jobject)con);
2258 } else if (rtype == relocInfo::metadata_type) {
2259 __ mov_metadata(dst_reg, (Metadata*)con);
2260 } else {
2261 assert(rtype == relocInfo::none || rtype == relocInfo::external_word_type, "unexpected reloc type");
2262 __ mv(dst_reg, $src$$constant);
2263 }
2264 }
2265 %}
2266
2267 enc_class riscv_enc_mov_p1(iRegP dst) %{
2268 Register dst_reg = as_Register($dst$$reg);
2269 __ mv(dst_reg, 1);
2270 %}
2271
2272 enc_class riscv_enc_mov_n(iRegN dst, immN src) %{
2273 Register dst_reg = as_Register($dst$$reg);
2274 address con = (address)$src$$constant;
2275 if (con == nullptr) {
2276 ShouldNotReachHere();
2277 } else {
2278 relocInfo::relocType rtype = $src->constant_reloc();
2279 assert(rtype == relocInfo::oop_type, "unexpected reloc type");
2280 __ set_narrow_oop(dst_reg, (jobject)con);
2281 }
2282 %}
2283
2284 enc_class riscv_enc_mov_zero(iRegNorP dst) %{
2285 Register dst_reg = as_Register($dst$$reg);
2286 __ mv(dst_reg, zr);
2287 %}
2288
2289 enc_class riscv_enc_mov_nk(iRegN dst, immNKlass src) %{
2290 Register dst_reg = as_Register($dst$$reg);
2291 address con = (address)$src$$constant;
2292 if (con == nullptr) {
2293 ShouldNotReachHere();
2294 } else {
2295 relocInfo::relocType rtype = $src->constant_reloc();
2296 assert(rtype == relocInfo::metadata_type, "unexpected reloc type");
2297 __ set_narrow_klass(dst_reg, (Klass *)con);
2298 }
2299 %}
2300
2301 // compare and branch instruction encodings
2302
2303 enc_class riscv_enc_j(label lbl) %{
2304 Label* L = $lbl$$label;
2305 __ j(*L);
2306 %}
2307
2308 enc_class riscv_enc_far_cmpULtGe_imm0_branch(cmpOpULtGe cmp, iRegIorL op1, label lbl) %{
2309 Label* L = $lbl$$label;
2310 switch ($cmp$$cmpcode) {
2311 case(BoolTest::ge):
2312 __ j(*L);
2313 break;
2314 case(BoolTest::lt):
2315 break;
2316 default:
2317 Unimplemented();
2318 }
2319 %}
2320
2321 // call instruction encodings
2322
2323 enc_class riscv_enc_partial_subtype_check(iRegP sub, iRegP super, iRegP temp, iRegP result) %{
2324 Register sub_reg = as_Register($sub$$reg);
2325 Register super_reg = as_Register($super$$reg);
2326 Register temp_reg = as_Register($temp$$reg);
2327 Register result_reg = as_Register($result$$reg);
2328 Register cr_reg = t1;
2329
2330 Label miss;
2331 Label done;
2332 __ check_klass_subtype_slow_path(sub_reg, super_reg, temp_reg, result_reg,
2333 nullptr, &miss, /*set_cond_codes*/ true);
2334 if ($primary) {
2335 __ mv(result_reg, zr);
2336 } else {
2337 __ mv(cr_reg, zr);
2338 __ j(done);
2339 }
2340
2341 __ bind(miss);
2342 if (!$primary) {
2343 __ mv(cr_reg, 1);
2344 }
2345
2346 __ bind(done);
2347 %}
2348
2349 enc_class riscv_enc_java_static_call(method meth) %{
2350 Assembler::IncompressibleScope scope(masm); // Fixed length: see ret_addr_offset
2351
2352 address addr = (address)$meth$$method;
2353 address call = nullptr;
2354 assert_cond(addr != nullptr);
2355 if (!_method) {
2356 // A call to a runtime wrapper, e.g. new, new_typeArray_Java, uncommon_trap.
2357 call = __ reloc_call(Address(addr, relocInfo::runtime_call_type));
2358 if (call == nullptr) {
2359 ciEnv::current()->record_failure("CodeCache is full");
2360 return;
2361 }
2362 } else if (_method->intrinsic_id() == vmIntrinsicID::_ensureMaterializedForStackWalk) {
2363 // The NOP here is purely to ensure that eliding a call to
2364 // JVM_EnsureMaterializedForStackWalk doesn't change the code size.
2365 __ nop();
2366 __ nop();
2367 __ nop();
2368 __ block_comment("call JVM_EnsureMaterializedForStackWalk (elided)");
2369 } else {
2370 int method_index = resolved_method_index(masm);
2371 RelocationHolder rspec = _optimized_virtual ? opt_virtual_call_Relocation::spec(method_index)
2372 : static_call_Relocation::spec(method_index);
2373 call = __ reloc_call(Address(addr, rspec));
2374 if (call == nullptr) {
2375 ciEnv::current()->record_failure("CodeCache is full");
2376 return;
2377 }
2378
2379 if (CodeBuffer::supports_shared_stubs() && _method->can_be_statically_bound()) {
2380 // Calls of the same statically bound method can share
2381 // a stub to the interpreter.
2382 __ code()->shared_stub_to_interp_for(_method, call - (__ begin()));
2383 } else {
2384 // Emit stub for static call
2385 address stub = CompiledDirectCall::emit_to_interp_stub(masm, call);
2386 if (stub == nullptr) {
2387 ciEnv::current()->record_failure("CodeCache is full");
2388 return;
2389 }
2390 }
2391 }
2392
2393 __ post_call_nop();
2394 %}
2395
2396 enc_class riscv_enc_java_dynamic_call(method meth) %{
2397 Assembler::IncompressibleScope scope(masm); // Fixed length: see ret_addr_offset
2398 int method_index = resolved_method_index(masm);
2399 address call = __ ic_call((address)$meth$$method, method_index);
2400 if (call == nullptr) {
2401 ciEnv::current()->record_failure("CodeCache is full");
2402 return;
2403 }
2404
2405 __ post_call_nop();
2406 %}
2407
2408 enc_class riscv_enc_call_epilog() %{
2409 if (VerifyStackAtCalls) {
2410 // Check that stack depth is unchanged: find majik cookie on stack
2411 int framesize = ra_->reg2offset_unchecked(OptoReg::add(ra_->_matcher._old_SP, -3 * VMRegImpl::slots_per_word));
2412 Label stack_ok;
2413 __ ld(t1, Address(sp, framesize));
2414 __ mv(t2, MAJIK_DWORD);
2415 __ beq(t2, t1, stack_ok);
2416 __ stop("MAJIK_DWORD not found");
2417 __ bind(stack_ok);
2418 }
2419 %}
2420
2421 enc_class riscv_enc_java_to_runtime(method meth) %{
2422 Assembler::IncompressibleScope scope(masm); // Fixed length: see ret_addr_offset
2423
2424 // Some calls to generated routines (arraycopy code) are scheduled by C2
2425 // as runtime calls. if so we can call them using a far call (they will be
2426 // in the code cache, thus in a reachable segment) otherwise we have to use
2427 // a movptr+jalr pair which loads the absolute address into a register.
2428 address entry = (address)$meth$$method;
2429 if (CodeCache::contains(entry)) {
2430 __ far_call(Address(entry, relocInfo::runtime_call_type));
2431 __ post_call_nop();
2432 } else {
2433 Label retaddr;
2434 // Make the anchor frame walkable
2435 __ la(t0, retaddr);
2436 __ sd(t0, Address(xthread, JavaThread::last_Java_pc_offset()));
2437 int32_t offset = 0;
2438 // No relocation needed
2439 __ movptr(t1, entry, offset, t0); // lui + lui + slli + add
2440 __ jalr(t1, offset);
2441 __ bind(retaddr);
2442 __ post_call_nop();
2443 }
2444 %}
2445
2446 enc_class riscv_enc_tail_call(iRegP jump_target) %{
2447 Register target_reg = as_Register($jump_target$$reg);
2448 __ jr(target_reg);
2449 %}
2450
2451 enc_class riscv_enc_tail_jmp(iRegP jump_target) %{
2452 Register target_reg = as_Register($jump_target$$reg);
2453 // exception oop should be in x10
2454 // ret addr has been popped into ra
2455 // callee expects it in x13
2456 __ mv(x13, ra);
2457 __ jr(target_reg);
2458 %}
2459
2460 enc_class riscv_enc_rethrow() %{
2461 __ far_jump(RuntimeAddress(OptoRuntime::rethrow_stub()));
2462 %}
2463
2464 enc_class riscv_enc_ret() %{
2465 __ ret();
2466 %}
2467
2468 %}
2469
2470 //----------FRAME--------------------------------------------------------------
2471 // Definition of frame structure and management information.
2472 //
2473 // S T A C K L A Y O U T Allocators stack-slot number
2474 // | (to get allocators register number
2475 // G Owned by | | v add OptoReg::stack0())
2476 // r CALLER | |
2477 // o | +--------+ pad to even-align allocators stack-slot
2478 // w V | pad0 | numbers; owned by CALLER
2479 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
2480 // h ^ | in | 5
2481 // | | args | 4 Holes in incoming args owned by SELF
2482 // | | | | 3
2483 // | | +--------+
2484 // V | | old out| Empty on Intel, window on Sparc
2485 // | old |preserve| Must be even aligned.
2486 // | SP-+--------+----> Matcher::_old_SP, even aligned
2487 // | | in | 3 area for Intel ret address
2488 // Owned by |preserve| Empty on Sparc.
2489 // SELF +--------+
2490 // | | pad2 | 2 pad to align old SP
2491 // | +--------+ 1
2492 // | | locks | 0
2493 // | +--------+----> OptoReg::stack0(), even aligned
2494 // | | pad1 | 11 pad to align new SP
2495 // | +--------+
2496 // | | | 10
2497 // | | spills | 9 spills
2498 // V | | 8 (pad0 slot for callee)
2499 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
2500 // ^ | out | 7
2501 // | | args | 6 Holes in outgoing args owned by CALLEE
2502 // Owned by +--------+
2503 // CALLEE | new out| 6 Empty on Intel, window on Sparc
2504 // | new |preserve| Must be even-aligned.
2505 // | SP-+--------+----> Matcher::_new_SP, even aligned
2506 // | | |
2507 //
2508 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
2509 // known from SELF's arguments and the Java calling convention.
2510 // Region 6-7 is determined per call site.
2511 // Note 2: If the calling convention leaves holes in the incoming argument
2512 // area, those holes are owned by SELF. Holes in the outgoing area
2513 // are owned by the CALLEE. Holes should not be necessary in the
2514 // incoming area, as the Java calling convention is completely under
2515 // the control of the AD file. Doubles can be sorted and packed to
2516 // avoid holes. Holes in the outgoing arguments may be necessary for
2517 // varargs C calling conventions.
2518 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
2519 // even aligned with pad0 as needed.
2520 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
2521 // (the latter is true on Intel but is it false on RISCV?)
2522 // region 6-11 is even aligned; it may be padded out more so that
2523 // the region from SP to FP meets the minimum stack alignment.
2524 // Note 4: For I2C adapters, the incoming FP may not meet the minimum stack
2525 // alignment. Region 11, pad1, may be dynamically extended so that
2526 // SP meets the minimum alignment.
2527
2528 frame %{
2529 // These three registers define part of the calling convention
2530 // between compiled code and the interpreter.
2531
2532 // Inline Cache Register or methodOop for I2C.
2533 inline_cache_reg(R31);
2534
2535 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
2536 cisc_spilling_operand_name(indOffset);
2537
2538 // Number of stack slots consumed by locking an object
2539 // generate Compile::sync_stack_slots
2540 // VMRegImpl::slots_per_word = wordSize / stack_slot_size = 8 / 4 = 2
2541 sync_stack_slots(1 * VMRegImpl::slots_per_word);
2542
2543 // Compiled code's Frame Pointer
2544 frame_pointer(R2);
2545
2546 // Stack alignment requirement
2547 stack_alignment(StackAlignmentInBytes); // Alignment size in bytes (128-bit -> 16 bytes)
2548
2549 // Number of outgoing stack slots killed above the out_preserve_stack_slots
2550 // for calls to C. Supports the var-args backing area for register parms.
2551 varargs_C_out_slots_killed(frame::arg_reg_save_area_bytes / BytesPerInt);
2552
2553 // The after-PROLOG location of the return address. Location of
2554 // return address specifies a type (REG or STACK) and a number
2555 // representing the register number (i.e. - use a register name) or
2556 // stack slot.
2557 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
2558 // Otherwise, it is above the locks and verification slot and alignment word
2559 // TODO this may well be correct but need to check why that - 2 is there
2560 // ppc port uses 0 but we definitely need to allow for fixed_slots
2561 // which folds in the space used for monitors
2562 return_addr(STACK - 2 +
2563 align_up((Compile::current()->in_preserve_stack_slots() +
2564 Compile::current()->fixed_slots()),
2565 stack_alignment_in_slots()));
2566
2567 // Location of compiled Java return values. Same as C for now.
2568 return_value
2569 %{
2570 assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL,
2571 "only return normal values");
2572
2573 static const int lo[Op_RegL + 1] = { // enum name
2574 0, // Op_Node
2575 0, // Op_Set
2576 R10_num, // Op_RegN
2577 R10_num, // Op_RegI
2578 R10_num, // Op_RegP
2579 F10_num, // Op_RegF
2580 F10_num, // Op_RegD
2581 R10_num // Op_RegL
2582 };
2583
2584 static const int hi[Op_RegL + 1] = { // enum name
2585 0, // Op_Node
2586 0, // Op_Set
2587 OptoReg::Bad, // Op_RegN
2588 OptoReg::Bad, // Op_RegI
2589 R10_H_num, // Op_RegP
2590 OptoReg::Bad, // Op_RegF
2591 F10_H_num, // Op_RegD
2592 R10_H_num // Op_RegL
2593 };
2594
2595 return OptoRegPair(hi[ideal_reg], lo[ideal_reg]);
2596 %}
2597 %}
2598
2599 //----------ATTRIBUTES---------------------------------------------------------
2600 //----------Operand Attributes-------------------------------------------------
2601 op_attrib op_cost(1); // Required cost attribute
2602
2603 //----------Instruction Attributes---------------------------------------------
2604 ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute
2605 ins_attrib ins_size(32); // Required size attribute (in bits)
2606 ins_attrib ins_short_branch(0); // Required flag: is this instruction
2607 // a non-matching short branch variant
2608 // of some long branch?
2609 ins_attrib ins_alignment(4); // Required alignment attribute (must
2610 // be a power of 2) specifies the
2611 // alignment that some part of the
2612 // instruction (not necessarily the
2613 // start) requires. If > 1, a
2614 // compute_padding() function must be
2615 // provided for the instruction
2616
2617 // Whether this node is expanded during code emission into a sequence of
2618 // instructions and the first instruction can perform an implicit null check.
2619 ins_attrib ins_is_late_expanded_null_check_candidate(false);
2620
2621 //----------OPERANDS-----------------------------------------------------------
2622 // Operand definitions must precede instruction definitions for correct parsing
2623 // in the ADLC because operands constitute user defined types which are used in
2624 // instruction definitions.
2625
2626 //----------Simple Operands----------------------------------------------------
2627
2628 // Integer operands 32 bit
2629 // 32 bit immediate
2630 operand immI()
2631 %{
2632 match(ConI);
2633
2634 op_cost(0);
2635 format %{ %}
2636 interface(CONST_INTER);
2637 %}
2638
2639 // 32 bit zero
2640 operand immI0()
2641 %{
2642 predicate(n->get_int() == 0);
2643 match(ConI);
2644
2645 op_cost(0);
2646 format %{ %}
2647 interface(CONST_INTER);
2648 %}
2649
2650 // 32 bit unit increment
2651 operand immI_1()
2652 %{
2653 predicate(n->get_int() == 1);
2654 match(ConI);
2655
2656 op_cost(0);
2657 format %{ %}
2658 interface(CONST_INTER);
2659 %}
2660
2661 // 32 bit unit decrement
2662 operand immI_M1()
2663 %{
2664 predicate(n->get_int() == -1);
2665 match(ConI);
2666
2667 op_cost(0);
2668 format %{ %}
2669 interface(CONST_INTER);
2670 %}
2671
2672 // Unsigned Integer Immediate: 6-bit int, greater than 32
2673 operand uimmI6_ge32() %{
2674 predicate(((unsigned int)(n->get_int()) < 64) && (n->get_int() >= 32));
2675 match(ConI);
2676 op_cost(0);
2677 format %{ %}
2678 interface(CONST_INTER);
2679 %}
2680
2681 operand immI_le_4()
2682 %{
2683 predicate(n->get_int() <= 4);
2684 match(ConI);
2685
2686 op_cost(0);
2687 format %{ %}
2688 interface(CONST_INTER);
2689 %}
2690
2691 operand immI_16()
2692 %{
2693 predicate(n->get_int() == 16);
2694 match(ConI);
2695 op_cost(0);
2696 format %{ %}
2697 interface(CONST_INTER);
2698 %}
2699
2700 operand immI_24()
2701 %{
2702 predicate(n->get_int() == 24);
2703 match(ConI);
2704 op_cost(0);
2705 format %{ %}
2706 interface(CONST_INTER);
2707 %}
2708
2709 operand immI_31()
2710 %{
2711 predicate(n->get_int() == 31);
2712 match(ConI);
2713
2714 op_cost(0);
2715 format %{ %}
2716 interface(CONST_INTER);
2717 %}
2718
2719 operand immI_63()
2720 %{
2721 predicate(n->get_int() == 63);
2722 match(ConI);
2723
2724 op_cost(0);
2725 format %{ %}
2726 interface(CONST_INTER);
2727 %}
2728
2729 // 32 bit integer valid for add immediate
2730 operand immIAdd()
2731 %{
2732 predicate(Assembler::is_simm12((int64_t)n->get_int()));
2733 match(ConI);
2734 op_cost(0);
2735 format %{ %}
2736 interface(CONST_INTER);
2737 %}
2738
2739 // 32 bit integer valid for sub immediate
2740 operand immISub()
2741 %{
2742 predicate(Assembler::is_simm12(-(int64_t)n->get_int()));
2743 match(ConI);
2744 op_cost(0);
2745 format %{ %}
2746 interface(CONST_INTER);
2747 %}
2748
2749 // 5 bit signed value.
2750 operand immI5()
2751 %{
2752 predicate(n->get_int() <= 15 && n->get_int() >= -16);
2753 match(ConI);
2754
2755 op_cost(0);
2756 format %{ %}
2757 interface(CONST_INTER);
2758 %}
2759
2760 // 5 bit signed value (simm5)
2761 operand immL5()
2762 %{
2763 predicate(n->get_long() <= 15 && n->get_long() >= -16);
2764 match(ConL);
2765
2766 op_cost(0);
2767 format %{ %}
2768 interface(CONST_INTER);
2769 %}
2770
2771 // Integer operands 64 bit
2772 // 64 bit immediate
2773 operand immL()
2774 %{
2775 match(ConL);
2776
2777 op_cost(0);
2778 format %{ %}
2779 interface(CONST_INTER);
2780 %}
2781
2782 // 64 bit zero
2783 operand immL0()
2784 %{
2785 predicate(n->get_long() == 0);
2786 match(ConL);
2787
2788 op_cost(0);
2789 format %{ %}
2790 interface(CONST_INTER);
2791 %}
2792
2793 // Pointer operands
2794 // Pointer Immediate
2795 operand immP()
2796 %{
2797 match(ConP);
2798
2799 op_cost(0);
2800 format %{ %}
2801 interface(CONST_INTER);
2802 %}
2803
2804 // Null Pointer Immediate
2805 operand immP0()
2806 %{
2807 predicate(n->get_ptr() == 0);
2808 match(ConP);
2809
2810 op_cost(0);
2811 format %{ %}
2812 interface(CONST_INTER);
2813 %}
2814
2815 // Pointer Immediate One
2816 // this is used in object initialization (initial object header)
2817 operand immP_1()
2818 %{
2819 predicate(n->get_ptr() == 1);
2820 match(ConP);
2821
2822 op_cost(0);
2823 format %{ %}
2824 interface(CONST_INTER);
2825 %}
2826
2827 // Int Immediate: low 16-bit mask
2828 operand immI_16bits()
2829 %{
2830 predicate(n->get_int() == 0xFFFF);
2831 match(ConI);
2832 op_cost(0);
2833 format %{ %}
2834 interface(CONST_INTER);
2835 %}
2836
2837 operand immIpowerOf2() %{
2838 predicate(is_power_of_2((juint)(n->get_int())));
2839 match(ConI);
2840 op_cost(0);
2841 format %{ %}
2842 interface(CONST_INTER);
2843 %}
2844
2845 // Long Immediate: low 32-bit mask
2846 operand immL_32bits()
2847 %{
2848 predicate(n->get_long() == 0xFFFFFFFFL);
2849 match(ConL);
2850 op_cost(0);
2851 format %{ %}
2852 interface(CONST_INTER);
2853 %}
2854
2855 // 64 bit unit decrement
2856 operand immL_M1()
2857 %{
2858 predicate(n->get_long() == -1);
2859 match(ConL);
2860
2861 op_cost(0);
2862 format %{ %}
2863 interface(CONST_INTER);
2864 %}
2865
2866
2867 // 64 bit integer valid for add immediate
2868 operand immLAdd()
2869 %{
2870 predicate(Assembler::is_simm12(n->get_long()));
2871 match(ConL);
2872 op_cost(0);
2873 format %{ %}
2874 interface(CONST_INTER);
2875 %}
2876
2877 // 64 bit integer valid for sub immediate
2878 operand immLSub()
2879 %{
2880 predicate(Assembler::is_simm12(-(n->get_long())));
2881 match(ConL);
2882 op_cost(0);
2883 format %{ %}
2884 interface(CONST_INTER);
2885 %}
2886
2887 // Narrow pointer operands
2888 // Narrow Pointer Immediate
2889 operand immN()
2890 %{
2891 match(ConN);
2892
2893 op_cost(0);
2894 format %{ %}
2895 interface(CONST_INTER);
2896 %}
2897
2898 // Narrow Null Pointer Immediate
2899 operand immN0()
2900 %{
2901 predicate(n->get_narrowcon() == 0);
2902 match(ConN);
2903
2904 op_cost(0);
2905 format %{ %}
2906 interface(CONST_INTER);
2907 %}
2908
2909 operand immNKlass()
2910 %{
2911 match(ConNKlass);
2912
2913 op_cost(0);
2914 format %{ %}
2915 interface(CONST_INTER);
2916 %}
2917
2918 // Float and Double operands
2919 // Double Immediate
2920 operand immD()
2921 %{
2922 match(ConD);
2923 op_cost(0);
2924 format %{ %}
2925 interface(CONST_INTER);
2926 %}
2927
2928 // Double Immediate: +0.0d
2929 operand immD0()
2930 %{
2931 predicate(jlong_cast(n->getd()) == 0);
2932 match(ConD);
2933
2934 op_cost(0);
2935 format %{ %}
2936 interface(CONST_INTER);
2937 %}
2938
2939 // Float Immediate
2940 operand immF()
2941 %{
2942 match(ConF);
2943 op_cost(0);
2944 format %{ %}
2945 interface(CONST_INTER);
2946 %}
2947
2948 // Float Immediate: +0.0f.
2949 operand immF0()
2950 %{
2951 predicate(jint_cast(n->getf()) == 0);
2952 match(ConF);
2953
2954 op_cost(0);
2955 format %{ %}
2956 interface(CONST_INTER);
2957 %}
2958
2959 // Half Float Immediate
2960 operand immH()
2961 %{
2962 match(ConH);
2963
2964 op_cost(0);
2965 format %{ %}
2966 interface(CONST_INTER);
2967 %}
2968
2969 // Half Float Immediate: +0.0f.
2970 operand immH0()
2971 %{
2972 predicate(jint_cast(n->geth()) == 0);
2973 match(ConH);
2974
2975 op_cost(0);
2976 format %{ %}
2977 interface(CONST_INTER);
2978 %}
2979
2980 operand immIOffset()
2981 %{
2982 predicate(Assembler::is_simm12(n->get_int()));
2983 match(ConI);
2984 op_cost(0);
2985 format %{ %}
2986 interface(CONST_INTER);
2987 %}
2988
2989 operand immLOffset()
2990 %{
2991 predicate(Assembler::is_simm12(n->get_long()));
2992 match(ConL);
2993 op_cost(0);
2994 format %{ %}
2995 interface(CONST_INTER);
2996 %}
2997
2998 // Scale values
2999 operand immIScale()
3000 %{
3001 predicate(1 <= n->get_int() && (n->get_int() <= 3));
3002 match(ConI);
3003
3004 op_cost(0);
3005 format %{ %}
3006 interface(CONST_INTER);
3007 %}
3008
3009 // Integer 32 bit Register Operands
3010 operand iRegI()
3011 %{
3012 constraint(ALLOC_IN_RC(any_reg32));
3013 match(RegI);
3014 match(iRegINoSp);
3015 op_cost(0);
3016 format %{ %}
3017 interface(REG_INTER);
3018 %}
3019
3020 // Integer 32 bit Register not Special
3021 operand iRegINoSp()
3022 %{
3023 constraint(ALLOC_IN_RC(no_special_reg32));
3024 match(RegI);
3025 op_cost(0);
3026 format %{ %}
3027 interface(REG_INTER);
3028 %}
3029
3030 // Register R10 only
3031 operand iRegI_R10()
3032 %{
3033 constraint(ALLOC_IN_RC(int_r10_reg));
3034 match(RegI);
3035 match(iRegINoSp);
3036 op_cost(0);
3037 format %{ %}
3038 interface(REG_INTER);
3039 %}
3040
3041 // Register R12 only
3042 operand iRegI_R12()
3043 %{
3044 constraint(ALLOC_IN_RC(int_r12_reg));
3045 match(RegI);
3046 match(iRegINoSp);
3047 op_cost(0);
3048 format %{ %}
3049 interface(REG_INTER);
3050 %}
3051
3052 // Register R13 only
3053 operand iRegI_R13()
3054 %{
3055 constraint(ALLOC_IN_RC(int_r13_reg));
3056 match(RegI);
3057 match(iRegINoSp);
3058 op_cost(0);
3059 format %{ %}
3060 interface(REG_INTER);
3061 %}
3062
3063 // Register R14 only
3064 operand iRegI_R14()
3065 %{
3066 constraint(ALLOC_IN_RC(int_r14_reg));
3067 match(RegI);
3068 match(iRegINoSp);
3069 op_cost(0);
3070 format %{ %}
3071 interface(REG_INTER);
3072 %}
3073
3074 // Integer 64 bit Register Operands
3075 operand iRegL()
3076 %{
3077 constraint(ALLOC_IN_RC(any_reg));
3078 match(RegL);
3079 match(iRegLNoSp);
3080 op_cost(0);
3081 format %{ %}
3082 interface(REG_INTER);
3083 %}
3084
3085 // Integer 64 bit Register not Special
3086 operand iRegLNoSp()
3087 %{
3088 constraint(ALLOC_IN_RC(no_special_reg));
3089 match(RegL);
3090 match(iRegL_R10);
3091 format %{ %}
3092 interface(REG_INTER);
3093 %}
3094
3095 // Long 64 bit Register R29 only
3096 operand iRegL_R29()
3097 %{
3098 constraint(ALLOC_IN_RC(r29_reg));
3099 match(RegL);
3100 match(iRegLNoSp);
3101 op_cost(0);
3102 format %{ %}
3103 interface(REG_INTER);
3104 %}
3105
3106 // Long 64 bit Register R30 only
3107 operand iRegL_R30()
3108 %{
3109 constraint(ALLOC_IN_RC(r30_reg));
3110 match(RegL);
3111 match(iRegLNoSp);
3112 op_cost(0);
3113 format %{ %}
3114 interface(REG_INTER);
3115 %}
3116
3117 // Pointer Register Operands
3118 // Pointer Register
3119 operand iRegP()
3120 %{
3121 constraint(ALLOC_IN_RC(ptr_reg));
3122 match(RegP);
3123 match(iRegPNoSp);
3124 match(iRegP_R10);
3125 match(iRegP_R15);
3126 match(javaThread_RegP);
3127 op_cost(0);
3128 format %{ %}
3129 interface(REG_INTER);
3130 %}
3131
3132 // Pointer 64 bit Register not Special
3133 operand iRegPNoSp()
3134 %{
3135 constraint(ALLOC_IN_RC(no_special_ptr_reg));
3136 match(RegP);
3137 op_cost(0);
3138 format %{ %}
3139 interface(REG_INTER);
3140 %}
3141
3142 // This operand is not allowed to use fp even if
3143 // fp is not used to hold the frame pointer.
3144 operand iRegPNoSpNoFp()
3145 %{
3146 constraint(ALLOC_IN_RC(no_special_no_fp_ptr_reg));
3147 match(RegP);
3148 match(iRegPNoSp);
3149 op_cost(0);
3150 format %{ %}
3151 interface(REG_INTER);
3152 %}
3153
3154 operand iRegP_R10()
3155 %{
3156 constraint(ALLOC_IN_RC(r10_reg));
3157 match(RegP);
3158 // match(iRegP);
3159 match(iRegPNoSp);
3160 op_cost(0);
3161 format %{ %}
3162 interface(REG_INTER);
3163 %}
3164
3165 // Pointer 64 bit Register R11 only
3166 operand iRegP_R11()
3167 %{
3168 constraint(ALLOC_IN_RC(r11_reg));
3169 match(RegP);
3170 match(iRegPNoSp);
3171 op_cost(0);
3172 format %{ %}
3173 interface(REG_INTER);
3174 %}
3175
3176 operand iRegP_R12()
3177 %{
3178 constraint(ALLOC_IN_RC(r12_reg));
3179 match(RegP);
3180 // match(iRegP);
3181 match(iRegPNoSp);
3182 op_cost(0);
3183 format %{ %}
3184 interface(REG_INTER);
3185 %}
3186
3187 // Pointer 64 bit Register R13 only
3188 operand iRegP_R13()
3189 %{
3190 constraint(ALLOC_IN_RC(r13_reg));
3191 match(RegP);
3192 match(iRegPNoSp);
3193 op_cost(0);
3194 format %{ %}
3195 interface(REG_INTER);
3196 %}
3197
3198 operand iRegP_R14()
3199 %{
3200 constraint(ALLOC_IN_RC(r14_reg));
3201 match(RegP);
3202 // match(iRegP);
3203 match(iRegPNoSp);
3204 op_cost(0);
3205 format %{ %}
3206 interface(REG_INTER);
3207 %}
3208
3209 operand iRegP_R15()
3210 %{
3211 constraint(ALLOC_IN_RC(r15_reg));
3212 match(RegP);
3213 // match(iRegP);
3214 match(iRegPNoSp);
3215 op_cost(0);
3216 format %{ %}
3217 interface(REG_INTER);
3218 %}
3219
3220 operand iRegP_R16()
3221 %{
3222 constraint(ALLOC_IN_RC(r16_reg));
3223 match(RegP);
3224 match(iRegPNoSp);
3225 op_cost(0);
3226 format %{ %}
3227 interface(REG_INTER);
3228 %}
3229
3230 // Pointer 64 bit Register R28 only
3231 operand iRegP_R28()
3232 %{
3233 constraint(ALLOC_IN_RC(r28_reg));
3234 match(RegP);
3235 match(iRegPNoSp);
3236 op_cost(0);
3237 format %{ %}
3238 interface(REG_INTER);
3239 %}
3240
3241 // Pointer 64 bit Register R30 only
3242 operand iRegP_R30()
3243 %{
3244 constraint(ALLOC_IN_RC(r30_reg));
3245 match(RegP);
3246 match(iRegPNoSp);
3247 op_cost(0);
3248 format %{ %}
3249 interface(REG_INTER);
3250 %}
3251
3252 // Pointer 64 bit Register R31 only
3253 operand iRegP_R31()
3254 %{
3255 constraint(ALLOC_IN_RC(r31_reg));
3256 match(RegP);
3257 match(iRegPNoSp);
3258 op_cost(0);
3259 format %{ %}
3260 interface(REG_INTER);
3261 %}
3262
3263 // Pointer Register Operands
3264 // Narrow Pointer Register
3265 operand iRegN()
3266 %{
3267 constraint(ALLOC_IN_RC(any_reg32));
3268 match(RegN);
3269 match(iRegNNoSp);
3270 op_cost(0);
3271 format %{ %}
3272 interface(REG_INTER);
3273 %}
3274
3275 // Integer 64 bit Register not Special
3276 operand iRegNNoSp()
3277 %{
3278 constraint(ALLOC_IN_RC(no_special_reg32));
3279 match(RegN);
3280 op_cost(0);
3281 format %{ %}
3282 interface(REG_INTER);
3283 %}
3284
3285 // Long 64 bit Register R10 only
3286 operand iRegL_R10()
3287 %{
3288 constraint(ALLOC_IN_RC(r10_reg));
3289 match(RegL);
3290 match(iRegLNoSp);
3291 op_cost(0);
3292 format %{ %}
3293 interface(REG_INTER);
3294 %}
3295
3296 // Float Register
3297 // Float register operands
3298 operand fRegF()
3299 %{
3300 constraint(ALLOC_IN_RC(float_reg));
3301 match(RegF);
3302
3303 op_cost(0);
3304 format %{ %}
3305 interface(REG_INTER);
3306 %}
3307
3308 // Double Register
3309 // Double register operands
3310 operand fRegD()
3311 %{
3312 constraint(ALLOC_IN_RC(double_reg));
3313 match(RegD);
3314
3315 op_cost(0);
3316 format %{ %}
3317 interface(REG_INTER);
3318 %}
3319
3320 // Generic vector class. This will be used for
3321 // all vector operands.
3322 operand vReg()
3323 %{
3324 constraint(ALLOC_IN_RC(vectora_reg));
3325 match(VecA);
3326 op_cost(0);
3327 format %{ %}
3328 interface(REG_INTER);
3329 %}
3330
3331 operand vReg_V1()
3332 %{
3333 constraint(ALLOC_IN_RC(v1_reg));
3334 match(VecA);
3335 match(vReg);
3336 op_cost(0);
3337 format %{ %}
3338 interface(REG_INTER);
3339 %}
3340
3341 operand vReg_V2()
3342 %{
3343 constraint(ALLOC_IN_RC(v2_reg));
3344 match(VecA);
3345 match(vReg);
3346 op_cost(0);
3347 format %{ %}
3348 interface(REG_INTER);
3349 %}
3350
3351 operand vReg_V3()
3352 %{
3353 constraint(ALLOC_IN_RC(v3_reg));
3354 match(VecA);
3355 match(vReg);
3356 op_cost(0);
3357 format %{ %}
3358 interface(REG_INTER);
3359 %}
3360
3361 operand vReg_V4()
3362 %{
3363 constraint(ALLOC_IN_RC(v4_reg));
3364 match(VecA);
3365 match(vReg);
3366 op_cost(0);
3367 format %{ %}
3368 interface(REG_INTER);
3369 %}
3370
3371 operand vReg_V5()
3372 %{
3373 constraint(ALLOC_IN_RC(v5_reg));
3374 match(VecA);
3375 match(vReg);
3376 op_cost(0);
3377 format %{ %}
3378 interface(REG_INTER);
3379 %}
3380
3381 operand vReg_V6()
3382 %{
3383 constraint(ALLOC_IN_RC(v6_reg));
3384 match(VecA);
3385 match(vReg);
3386 op_cost(0);
3387 format %{ %}
3388 interface(REG_INTER);
3389 %}
3390
3391 operand vReg_V7()
3392 %{
3393 constraint(ALLOC_IN_RC(v7_reg));
3394 match(VecA);
3395 match(vReg);
3396 op_cost(0);
3397 format %{ %}
3398 interface(REG_INTER);
3399 %}
3400
3401 operand vReg_V8()
3402 %{
3403 constraint(ALLOC_IN_RC(v8_reg));
3404 match(VecA);
3405 match(vReg);
3406 op_cost(0);
3407 format %{ %}
3408 interface(REG_INTER);
3409 %}
3410
3411 operand vReg_V9()
3412 %{
3413 constraint(ALLOC_IN_RC(v9_reg));
3414 match(VecA);
3415 match(vReg);
3416 op_cost(0);
3417 format %{ %}
3418 interface(REG_INTER);
3419 %}
3420
3421 operand vReg_V10()
3422 %{
3423 constraint(ALLOC_IN_RC(v10_reg));
3424 match(VecA);
3425 match(vReg);
3426 op_cost(0);
3427 format %{ %}
3428 interface(REG_INTER);
3429 %}
3430
3431 operand vReg_V11()
3432 %{
3433 constraint(ALLOC_IN_RC(v11_reg));
3434 match(VecA);
3435 match(vReg);
3436 op_cost(0);
3437 format %{ %}
3438 interface(REG_INTER);
3439 %}
3440
3441 operand vRegMask()
3442 %{
3443 constraint(ALLOC_IN_RC(vmask_reg));
3444 match(RegVectMask);
3445 match(vRegMask_V0);
3446 op_cost(0);
3447 format %{ %}
3448 interface(REG_INTER);
3449 %}
3450
3451 // The mask value used to control execution of a masked
3452 // vector instruction is always supplied by vector register v0.
3453 operand vRegMask_V0()
3454 %{
3455 constraint(ALLOC_IN_RC(vmask_reg_v0));
3456 match(RegVectMask);
3457 match(vRegMask);
3458 op_cost(0);
3459 format %{ %}
3460 interface(REG_INTER);
3461 %}
3462
3463 // Java Thread Register
3464 operand javaThread_RegP(iRegP reg)
3465 %{
3466 constraint(ALLOC_IN_RC(java_thread_reg)); // java_thread_reg
3467 match(reg);
3468 op_cost(0);
3469 format %{ %}
3470 interface(REG_INTER);
3471 %}
3472
3473 //----------Memory Operands----------------------------------------------------
3474 // RISCV has only base_plus_offset and literal address mode, so no need to use
3475 // index and scale. Here set index as 0xffffffff and scale as 0x0.
3476 operand indirect(iRegP reg)
3477 %{
3478 constraint(ALLOC_IN_RC(ptr_reg));
3479 match(reg);
3480 op_cost(0);
3481 format %{ "[$reg]" %}
3482 interface(MEMORY_INTER) %{
3483 base($reg);
3484 index(0xffffffff);
3485 scale(0x0);
3486 disp(0x0);
3487 %}
3488 %}
3489
3490 operand indOffI(iRegP reg, immIOffset off)
3491 %{
3492 constraint(ALLOC_IN_RC(ptr_reg));
3493 match(AddP reg off);
3494 op_cost(0);
3495 format %{ "[$reg, $off]" %}
3496 interface(MEMORY_INTER) %{
3497 base($reg);
3498 index(0xffffffff);
3499 scale(0x0);
3500 disp($off);
3501 %}
3502 %}
3503
3504 operand indOffL(iRegP reg, immLOffset off)
3505 %{
3506 constraint(ALLOC_IN_RC(ptr_reg));
3507 match(AddP reg off);
3508 op_cost(0);
3509 format %{ "[$reg, $off]" %}
3510 interface(MEMORY_INTER) %{
3511 base($reg);
3512 index(0xffffffff);
3513 scale(0x0);
3514 disp($off);
3515 %}
3516 %}
3517
3518 operand indirectN(iRegN reg)
3519 %{
3520 predicate(CompressedOops::shift() == 0);
3521 constraint(ALLOC_IN_RC(ptr_reg));
3522 match(DecodeN reg);
3523 op_cost(0);
3524 format %{ "[$reg]\t# narrow" %}
3525 interface(MEMORY_INTER) %{
3526 base($reg);
3527 index(0xffffffff);
3528 scale(0x0);
3529 disp(0x0);
3530 %}
3531 %}
3532
3533 operand indOffIN(iRegN reg, immIOffset off)
3534 %{
3535 predicate(CompressedOops::shift() == 0);
3536 constraint(ALLOC_IN_RC(ptr_reg));
3537 match(AddP (DecodeN reg) off);
3538 op_cost(0);
3539 format %{ "[$reg, $off]\t# narrow" %}
3540 interface(MEMORY_INTER) %{
3541 base($reg);
3542 index(0xffffffff);
3543 scale(0x0);
3544 disp($off);
3545 %}
3546 %}
3547
3548 operand indOffLN(iRegN reg, immLOffset off)
3549 %{
3550 predicate(CompressedOops::shift() == 0);
3551 constraint(ALLOC_IN_RC(ptr_reg));
3552 match(AddP (DecodeN reg) off);
3553 op_cost(0);
3554 format %{ "[$reg, $off]\t# narrow" %}
3555 interface(MEMORY_INTER) %{
3556 base($reg);
3557 index(0xffffffff);
3558 scale(0x0);
3559 disp($off);
3560 %}
3561 %}
3562
3563 //----------Special Memory Operands--------------------------------------------
3564 // Stack Slot Operand - This operand is used for loading and storing temporary
3565 // values on the stack where a match requires a value to
3566 // flow through memory.
3567 operand stackSlotI(sRegI reg)
3568 %{
3569 constraint(ALLOC_IN_RC(stack_slots));
3570 // No match rule because this operand is only generated in matching
3571 // match(RegI);
3572 format %{ "[$reg]" %}
3573 interface(MEMORY_INTER) %{
3574 base(0x02); // RSP
3575 index(0xffffffff); // No Index
3576 scale(0x0); // No Scale
3577 disp($reg); // Stack Offset
3578 %}
3579 %}
3580
3581 operand stackSlotF(sRegF reg)
3582 %{
3583 constraint(ALLOC_IN_RC(stack_slots));
3584 // No match rule because this operand is only generated in matching
3585 // match(RegF);
3586 format %{ "[$reg]" %}
3587 interface(MEMORY_INTER) %{
3588 base(0x02); // RSP
3589 index(0xffffffff); // No Index
3590 scale(0x0); // No Scale
3591 disp($reg); // Stack Offset
3592 %}
3593 %}
3594
3595 operand stackSlotD(sRegD reg)
3596 %{
3597 constraint(ALLOC_IN_RC(stack_slots));
3598 // No match rule because this operand is only generated in matching
3599 // match(RegD);
3600 format %{ "[$reg]" %}
3601 interface(MEMORY_INTER) %{
3602 base(0x02); // RSP
3603 index(0xffffffff); // No Index
3604 scale(0x0); // No Scale
3605 disp($reg); // Stack Offset
3606 %}
3607 %}
3608
3609 operand stackSlotL(sRegL reg)
3610 %{
3611 constraint(ALLOC_IN_RC(stack_slots));
3612 // No match rule because this operand is only generated in matching
3613 // match(RegL);
3614 format %{ "[$reg]" %}
3615 interface(MEMORY_INTER) %{
3616 base(0x02); // RSP
3617 index(0xffffffff); // No Index
3618 scale(0x0); // No Scale
3619 disp($reg); // Stack Offset
3620 %}
3621 %}
3622
3623 // Special operand allowing long args to int ops to be truncated for free
3624
3625 operand iRegL2I(iRegL reg) %{
3626
3627 op_cost(0);
3628
3629 match(ConvL2I reg);
3630
3631 format %{ "l2i($reg)" %}
3632
3633 interface(REG_INTER)
3634 %}
3635
3636
3637 // Comparison Operands
3638 // NOTE: Label is a predefined operand which should not be redefined in
3639 // the AD file. It is generically handled within the ADLC.
3640
3641 //----------Conditional Branch Operands----------------------------------------
3642 // Comparison Op - This is the operation of the comparison, and is limited to
3643 // the following set of codes:
3644 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
3645 //
3646 // Other attributes of the comparison, such as unsignedness, are specified
3647 // by the comparison instruction that sets a condition code flags register.
3648 // That result is represented by a flags operand whose subtype is appropriate
3649 // to the unsignedness (etc.) of the comparison.
3650 //
3651 // Later, the instruction which matches both the Comparison Op (a Bool) and
3652 // the flags (produced by the Cmp) specifies the coding of the comparison op
3653 // by matching a specific subtype of Bool operand below, such as cmpOpU.
3654
3655
3656 // used for signed integral comparisons and fp comparisons
3657 operand cmpOp()
3658 %{
3659 match(Bool);
3660
3661 format %{ "" %}
3662
3663 // the values in interface derives from struct BoolTest::mask
3664 interface(COND_INTER) %{
3665 equal(0x0, "eq");
3666 greater(0x1, "gt");
3667 overflow(0x2, "overflow");
3668 less(0x3, "lt");
3669 not_equal(0x4, "ne");
3670 less_equal(0x5, "le");
3671 no_overflow(0x6, "no_overflow");
3672 greater_equal(0x7, "ge");
3673 %}
3674 %}
3675
3676 // used for unsigned integral comparisons
3677 operand cmpOpU()
3678 %{
3679 match(Bool);
3680
3681 format %{ "" %}
3682 // the values in interface derives from struct BoolTest::mask
3683 interface(COND_INTER) %{
3684 equal(0x0, "eq");
3685 greater(0x1, "gtu");
3686 overflow(0x2, "overflow");
3687 less(0x3, "ltu");
3688 not_equal(0x4, "ne");
3689 less_equal(0x5, "leu");
3690 no_overflow(0x6, "no_overflow");
3691 greater_equal(0x7, "geu");
3692 %}
3693 %}
3694
3695 // used for certain integral comparisons which can be
3696 // converted to bxx instructions
3697 operand cmpOpEqNe()
3698 %{
3699 match(Bool);
3700 op_cost(0);
3701 predicate(n->as_Bool()->_test._test == BoolTest::ne ||
3702 n->as_Bool()->_test._test == BoolTest::eq);
3703
3704 format %{ "" %}
3705 interface(COND_INTER) %{
3706 equal(0x0, "eq");
3707 greater(0x1, "gt");
3708 overflow(0x2, "overflow");
3709 less(0x3, "lt");
3710 not_equal(0x4, "ne");
3711 less_equal(0x5, "le");
3712 no_overflow(0x6, "no_overflow");
3713 greater_equal(0x7, "ge");
3714 %}
3715 %}
3716
3717 operand cmpOpULtGe()
3718 %{
3719 match(Bool);
3720 op_cost(0);
3721 predicate(n->as_Bool()->_test._test == BoolTest::lt ||
3722 n->as_Bool()->_test._test == BoolTest::ge);
3723
3724 format %{ "" %}
3725 interface(COND_INTER) %{
3726 equal(0x0, "eq");
3727 greater(0x1, "gtu");
3728 overflow(0x2, "overflow");
3729 less(0x3, "ltu");
3730 not_equal(0x4, "ne");
3731 less_equal(0x5, "leu");
3732 no_overflow(0x6, "no_overflow");
3733 greater_equal(0x7, "geu");
3734 %}
3735 %}
3736
3737 operand cmpOpUEqNeLeGt()
3738 %{
3739 match(Bool);
3740 op_cost(0);
3741 predicate(n->as_Bool()->_test._test == BoolTest::ne ||
3742 n->as_Bool()->_test._test == BoolTest::eq ||
3743 n->as_Bool()->_test._test == BoolTest::le ||
3744 n->as_Bool()->_test._test == BoolTest::gt);
3745
3746 format %{ "" %}
3747 interface(COND_INTER) %{
3748 equal(0x0, "eq");
3749 greater(0x1, "gtu");
3750 overflow(0x2, "overflow");
3751 less(0x3, "ltu");
3752 not_equal(0x4, "ne");
3753 less_equal(0x5, "leu");
3754 no_overflow(0x6, "no_overflow");
3755 greater_equal(0x7, "geu");
3756 %}
3757 %}
3758
3759
3760 // Flags register, used as output of compare logic
3761 operand rFlagsReg()
3762 %{
3763 constraint(ALLOC_IN_RC(reg_flags));
3764 match(RegFlags);
3765
3766 op_cost(0);
3767 format %{ "RFLAGS" %}
3768 interface(REG_INTER);
3769 %}
3770
3771 // Special Registers
3772
3773 // Method Register
3774 operand inline_cache_RegP(iRegP reg)
3775 %{
3776 constraint(ALLOC_IN_RC(method_reg)); // inline_cache_reg
3777 match(reg);
3778 match(iRegPNoSp);
3779 op_cost(0);
3780 format %{ %}
3781 interface(REG_INTER);
3782 %}
3783
3784 //----------OPERAND CLASSES----------------------------------------------------
3785 // Operand Classes are groups of operands that are used as to simplify
3786 // instruction definitions by not requiring the AD writer to specify
3787 // separate instructions for every form of operand when the
3788 // instruction accepts multiple operand types with the same basic
3789 // encoding and format. The classic case of this is memory operands.
3790
3791 // memory is used to define read/write location for load/store
3792 // instruction defs. we can turn a memory op into an Address
3793
3794 opclass memory(indirect, indOffI, indOffL, indirectN, indOffIN, indOffLN);
3795
3796 // iRegIorL2I is used for src inputs in rules for 32 bit int (I)
3797 // operations. it allows the src to be either an iRegI or a (ConvL2I
3798 // iRegL). in the latter case the l2i normally planted for a ConvL2I
3799 // can be elided because the 32-bit instruction will just employ the
3800 // lower 32 bits anyway.
3801 //
3802 // n.b. this does not elide all L2I conversions. if the truncated
3803 // value is consumed by more than one operation then the ConvL2I
3804 // cannot be bundled into the consuming nodes so an l2i gets planted
3805 // (actually an addiw $dst, $src, 0) and the downstream instructions
3806 // consume the result of the L2I as an iRegI input. That's a shame since
3807 // the addiw is actually redundant but its not too costly.
3808
3809 opclass iRegIorL2I(iRegI, iRegL2I);
3810 opclass iRegIorL(iRegI, iRegL);
3811 opclass iRegNorP(iRegN, iRegP);
3812 opclass iRegILNP(iRegI, iRegL, iRegN, iRegP);
3813 opclass iRegILNPNoSp(iRegINoSp, iRegLNoSp, iRegNNoSp, iRegPNoSp);
3814 opclass immIorL(immI, immL);
3815
3816 //----------PIPELINE-----------------------------------------------------------
3817 // Rules which define the behavior of the target architectures pipeline.
3818
3819 // For specific pipelines, e.g. generic RISC-V, define the stages of that pipeline
3820 //pipe_desc(ID, EX, MEM, WR);
3821 #define ID S0
3822 #define EX S1
3823 #define MEM S2
3824 #define WR S3
3825
3826 // Integer ALU reg operation
3827 pipeline %{
3828
3829 attributes %{
3830 // RISC-V instructions are of length 2 or 4 bytes.
3831 variable_size_instructions;
3832 instruction_unit_size = 2;
3833
3834 // Up to 4 instructions per bundle
3835 max_instructions_per_bundle = 4;
3836
3837 // The RISC-V processor fetches 64 bytes...
3838 instruction_fetch_unit_size = 64;
3839
3840 // ...in one line.
3841 instruction_fetch_units = 1;
3842 %}
3843
3844 // We don't use an actual pipeline model so don't care about resources
3845 // or description. we do use pipeline classes to introduce fixed
3846 // latencies
3847
3848 //----------RESOURCES----------------------------------------------------------
3849 // Resources are the functional units available to the machine
3850
3851 // Generic RISC-V pipeline
3852 // 1 decoder
3853 // 1 instruction decoded per cycle
3854 // 1 load/store ops per cycle, 1 branch, 1 FPU
3855 // 1 mul, 1 div
3856
3857 resources ( DECODE,
3858 ALU,
3859 MUL,
3860 DIV,
3861 BRANCH,
3862 LDST,
3863 FPU);
3864
3865 //----------PIPELINE DESCRIPTION-----------------------------------------------
3866 // Pipeline Description specifies the stages in the machine's pipeline
3867
3868 // Define the pipeline as a generic 6 stage pipeline
3869 pipe_desc(S0, S1, S2, S3, S4, S5);
3870
3871 //----------PIPELINE CLASSES---------------------------------------------------
3872 // Pipeline Classes describe the stages in which input and output are
3873 // referenced by the hardware pipeline.
3874
3875 pipe_class fp_dop_reg_reg_s(fRegF dst, fRegF src1, fRegF src2)
3876 %{
3877 single_instruction;
3878 src1 : S1(read);
3879 src2 : S2(read);
3880 dst : S5(write);
3881 DECODE : ID;
3882 FPU : S5;
3883 %}
3884
3885 pipe_class fp_dop_reg_reg_d(fRegD dst, fRegD src1, fRegD src2)
3886 %{
3887 src1 : S1(read);
3888 src2 : S2(read);
3889 dst : S5(write);
3890 DECODE : ID;
3891 FPU : S5;
3892 %}
3893
3894 pipe_class fp_uop_s(fRegF dst, fRegF src)
3895 %{
3896 single_instruction;
3897 src : S1(read);
3898 dst : S5(write);
3899 DECODE : ID;
3900 FPU : S5;
3901 %}
3902
3903 pipe_class fp_uop_d(fRegD dst, fRegD src)
3904 %{
3905 single_instruction;
3906 src : S1(read);
3907 dst : S5(write);
3908 DECODE : ID;
3909 FPU : S5;
3910 %}
3911
3912 pipe_class fp_d2f(fRegF dst, fRegD src)
3913 %{
3914 single_instruction;
3915 src : S1(read);
3916 dst : S5(write);
3917 DECODE : ID;
3918 FPU : S5;
3919 %}
3920
3921 pipe_class fp_f2d(fRegD dst, fRegF src)
3922 %{
3923 single_instruction;
3924 src : S1(read);
3925 dst : S5(write);
3926 DECODE : ID;
3927 FPU : S5;
3928 %}
3929
3930 pipe_class fp_f2i(iRegINoSp dst, fRegF src)
3931 %{
3932 single_instruction;
3933 src : S1(read);
3934 dst : S5(write);
3935 DECODE : ID;
3936 FPU : S5;
3937 %}
3938
3939 pipe_class fp_f2l(iRegLNoSp dst, fRegF src)
3940 %{
3941 single_instruction;
3942 src : S1(read);
3943 dst : S5(write);
3944 DECODE : ID;
3945 FPU : S5;
3946 %}
3947
3948 pipe_class fp_i2f(fRegF dst, iRegIorL2I src)
3949 %{
3950 single_instruction;
3951 src : S1(read);
3952 dst : S5(write);
3953 DECODE : ID;
3954 FPU : S5;
3955 %}
3956
3957 pipe_class fp_l2f(fRegF dst, iRegL src)
3958 %{
3959 single_instruction;
3960 src : S1(read);
3961 dst : S5(write);
3962 DECODE : ID;
3963 FPU : S5;
3964 %}
3965
3966 pipe_class fp_d2i(iRegINoSp dst, fRegD src)
3967 %{
3968 single_instruction;
3969 src : S1(read);
3970 dst : S5(write);
3971 DECODE : ID;
3972 FPU : S5;
3973 %}
3974
3975 pipe_class fp_d2l(iRegLNoSp dst, fRegD src)
3976 %{
3977 single_instruction;
3978 src : S1(read);
3979 dst : S5(write);
3980 DECODE : ID;
3981 FPU : S5;
3982 %}
3983
3984 pipe_class fp_i2d(fRegD dst, iRegIorL2I src)
3985 %{
3986 single_instruction;
3987 src : S1(read);
3988 dst : S5(write);
3989 DECODE : ID;
3990 FPU : S5;
3991 %}
3992
3993 pipe_class fp_l2d(fRegD dst, iRegIorL2I src)
3994 %{
3995 single_instruction;
3996 src : S1(read);
3997 dst : S5(write);
3998 DECODE : ID;
3999 FPU : S5;
4000 %}
4001
4002 pipe_class fp_div_s(fRegF dst, fRegF src1, fRegF src2)
4003 %{
4004 single_instruction;
4005 src1 : S1(read);
4006 src2 : S2(read);
4007 dst : S5(write);
4008 DECODE : ID;
4009 FPU : S5;
4010 %}
4011
4012 pipe_class fp_div_d(fRegD dst, fRegD src1, fRegD src2)
4013 %{
4014 single_instruction;
4015 src1 : S1(read);
4016 src2 : S2(read);
4017 dst : S5(write);
4018 DECODE : ID;
4019 FPU : S5;
4020 %}
4021
4022 pipe_class fp_sqrt_s(fRegF dst, fRegF src)
4023 %{
4024 single_instruction;
4025 src : S1(read);
4026 dst : S5(write);
4027 DECODE : ID;
4028 FPU : S5;
4029 %}
4030
4031 pipe_class fp_sqrt_d(fRegD dst, fRegD src)
4032 %{
4033 single_instruction;
4034 src : S1(read);
4035 dst : S5(write);
4036 DECODE : ID;
4037 FPU : S5;
4038 %}
4039
4040 pipe_class fp_load_constant_s(fRegF dst)
4041 %{
4042 single_instruction;
4043 dst : S5(write);
4044 DECODE : ID;
4045 FPU : S5;
4046 %}
4047
4048 pipe_class fp_load_constant_d(fRegD dst)
4049 %{
4050 single_instruction;
4051 dst : S5(write);
4052 DECODE : ID;
4053 FPU : S5;
4054 %}
4055
4056 pipe_class fp_load_mem_s(fRegF dst, memory mem)
4057 %{
4058 single_instruction;
4059 mem : S1(read);
4060 dst : S5(write);
4061 DECODE : ID;
4062 LDST : MEM;
4063 %}
4064
4065 pipe_class fp_load_mem_d(fRegD dst, memory mem)
4066 %{
4067 single_instruction;
4068 mem : S1(read);
4069 dst : S5(write);
4070 DECODE : ID;
4071 LDST : MEM;
4072 %}
4073
4074 pipe_class fp_store_reg_s(fRegF src, memory mem)
4075 %{
4076 single_instruction;
4077 src : S1(read);
4078 mem : S5(write);
4079 DECODE : ID;
4080 LDST : MEM;
4081 %}
4082
4083 pipe_class fp_store_reg_d(fRegD src, memory mem)
4084 %{
4085 single_instruction;
4086 src : S1(read);
4087 mem : S5(write);
4088 DECODE : ID;
4089 LDST : MEM;
4090 %}
4091
4092 //------- Integer ALU operations --------------------------
4093
4094 // Integer ALU reg-reg operation
4095 // Operands needs in ID, result generated in EX
4096 // E.g. ADD Rd, Rs1, Rs2
4097 pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2)
4098 %{
4099 single_instruction;
4100 dst : EX(write);
4101 src1 : ID(read);
4102 src2 : ID(read);
4103 DECODE : ID;
4104 ALU : EX;
4105 %}
4106
4107 // Integer ALU reg operation with constant shift
4108 // E.g. SLLI Rd, Rs1, #shift
4109 pipe_class ialu_reg_shift(iRegI dst, iRegI src1)
4110 %{
4111 single_instruction;
4112 dst : EX(write);
4113 src1 : ID(read);
4114 DECODE : ID;
4115 ALU : EX;
4116 %}
4117
4118 // Integer ALU reg-reg operation with variable shift
4119 // both operands must be available in ID
4120 // E.g. SLL Rd, Rs1, Rs2
4121 pipe_class ialu_reg_reg_vshift(iRegI dst, iRegI src1, iRegI src2)
4122 %{
4123 single_instruction;
4124 dst : EX(write);
4125 src1 : ID(read);
4126 src2 : ID(read);
4127 DECODE : ID;
4128 ALU : EX;
4129 %}
4130
4131 // Integer ALU reg operation
4132 // E.g. NEG Rd, Rs2
4133 pipe_class ialu_reg(iRegI dst, iRegI src)
4134 %{
4135 single_instruction;
4136 dst : EX(write);
4137 src : ID(read);
4138 DECODE : ID;
4139 ALU : EX;
4140 %}
4141
4142 // Integer ALU reg immediate operation
4143 // E.g. ADDI Rd, Rs1, #imm
4144 pipe_class ialu_reg_imm(iRegI dst, iRegI src1)
4145 %{
4146 single_instruction;
4147 dst : EX(write);
4148 src1 : ID(read);
4149 DECODE : ID;
4150 ALU : EX;
4151 %}
4152
4153 // Integer ALU immediate operation (no source operands)
4154 // E.g. LI Rd, #imm
4155 pipe_class ialu_imm(iRegI dst)
4156 %{
4157 single_instruction;
4158 dst : EX(write);
4159 DECODE : ID;
4160 ALU : EX;
4161 %}
4162
4163 //------- Multiply pipeline operations --------------------
4164
4165 // Multiply reg-reg
4166 // E.g. MULW Rd, Rs1, Rs2
4167 pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2)
4168 %{
4169 single_instruction;
4170 dst : WR(write);
4171 src1 : ID(read);
4172 src2 : ID(read);
4173 DECODE : ID;
4174 MUL : WR;
4175 %}
4176
4177 // E.g. MUL RD, Rs1, Rs2
4178 pipe_class lmul_reg_reg(iRegL dst, iRegL src1, iRegL src2)
4179 %{
4180 single_instruction;
4181 fixed_latency(3); // Maximum latency for 64 bit mul
4182 dst : WR(write);
4183 src1 : ID(read);
4184 src2 : ID(read);
4185 DECODE : ID;
4186 MUL : WR;
4187 %}
4188
4189 //------- Divide pipeline operations --------------------
4190
4191 // E.g. DIVW Rd, Rs1, Rs2
4192 pipe_class idiv_reg_reg(iRegI dst, iRegI src1, iRegI src2)
4193 %{
4194 single_instruction;
4195 fixed_latency(8); // Maximum latency for 32 bit divide
4196 dst : WR(write);
4197 src1 : ID(read);
4198 src2 : ID(read);
4199 DECODE : ID;
4200 DIV : WR;
4201 %}
4202
4203 // E.g. DIV RD, Rs1, Rs2
4204 pipe_class ldiv_reg_reg(iRegL dst, iRegL src1, iRegL src2)
4205 %{
4206 single_instruction;
4207 fixed_latency(16); // Maximum latency for 64 bit divide
4208 dst : WR(write);
4209 src1 : ID(read);
4210 src2 : ID(read);
4211 DECODE : ID;
4212 DIV : WR;
4213 %}
4214
4215 //------- Load pipeline operations ------------------------
4216
4217 // Load - prefetch
4218 // Eg. PREFETCH_W mem
4219 pipe_class iload_prefetch(memory mem)
4220 %{
4221 single_instruction;
4222 mem : ID(read);
4223 DECODE : ID;
4224 LDST : MEM;
4225 %}
4226
4227 // Load - reg, mem
4228 // E.g. LA Rd, mem
4229 pipe_class iload_reg_mem(iRegI dst, memory mem)
4230 %{
4231 single_instruction;
4232 dst : WR(write);
4233 mem : ID(read);
4234 DECODE : ID;
4235 LDST : MEM;
4236 %}
4237
4238 // Load - reg, reg
4239 // E.g. LD Rd, Rs
4240 pipe_class iload_reg_reg(iRegI dst, iRegI src)
4241 %{
4242 single_instruction;
4243 dst : WR(write);
4244 src : ID(read);
4245 DECODE : ID;
4246 LDST : MEM;
4247 %}
4248
4249 //------- Store pipeline operations -----------------------
4250
4251 // Store - zr, mem
4252 // E.g. SD zr, mem
4253 pipe_class istore_mem(memory mem)
4254 %{
4255 single_instruction;
4256 mem : ID(read);
4257 DECODE : ID;
4258 LDST : MEM;
4259 %}
4260
4261 // Store - reg, mem
4262 // E.g. SD Rs, mem
4263 pipe_class istore_reg_mem(iRegI src, memory mem)
4264 %{
4265 single_instruction;
4266 mem : ID(read);
4267 src : EX(read);
4268 DECODE : ID;
4269 LDST : MEM;
4270 %}
4271
4272 // Store - reg, reg
4273 // E.g. SD Rs2, Rs1
4274 pipe_class istore_reg_reg(iRegI dst, iRegI src)
4275 %{
4276 single_instruction;
4277 dst : ID(read);
4278 src : EX(read);
4279 DECODE : ID;
4280 LDST : MEM;
4281 %}
4282
4283 //------- Control transfer pipeline operations ------------
4284
4285 // Branch
4286 pipe_class pipe_branch()
4287 %{
4288 single_instruction;
4289 DECODE : ID;
4290 BRANCH : EX;
4291 %}
4292
4293 // Branch
4294 pipe_class pipe_branch_reg(iRegI src)
4295 %{
4296 single_instruction;
4297 src : ID(read);
4298 DECODE : ID;
4299 BRANCH : EX;
4300 %}
4301
4302 // Compare & Branch
4303 // E.g. BEQ Rs1, Rs2, L
4304 pipe_class pipe_cmp_branch(iRegI src1, iRegI src2)
4305 %{
4306 single_instruction;
4307 src1 : ID(read);
4308 src2 : ID(read);
4309 DECODE : ID;
4310 BRANCH : EX;
4311 %}
4312
4313 // E.g. BEQZ Rs, L
4314 pipe_class pipe_cmpz_branch(iRegI src)
4315 %{
4316 single_instruction;
4317 src : ID(read);
4318 DECODE : ID;
4319 BRANCH : EX;
4320 %}
4321
4322 //------- Synchronisation operations ----------------------
4323 // Any operation requiring serialization
4324 // E.g. FENCE/Atomic Ops/Load Acquire/Store Release
4325 pipe_class pipe_serial()
4326 %{
4327 single_instruction;
4328 force_serialization;
4329 fixed_latency(16);
4330 DECODE : ID;
4331 LDST : MEM;
4332 %}
4333
4334 pipe_class pipe_slow()
4335 %{
4336 instruction_count(10);
4337 multiple_bundles;
4338 force_serialization;
4339 fixed_latency(16);
4340 DECODE : ID;
4341 LDST : MEM;
4342 %}
4343
4344 // The real do-nothing guy
4345 pipe_class real_empty()
4346 %{
4347 instruction_count(0);
4348 %}
4349
4350 // Empty pipeline class
4351 pipe_class pipe_class_empty()
4352 %{
4353 single_instruction;
4354 fixed_latency(0);
4355 %}
4356
4357 // Default pipeline class.
4358 pipe_class pipe_class_default()
4359 %{
4360 single_instruction;
4361 fixed_latency(2);
4362 %}
4363
4364 // Pipeline class for compares.
4365 pipe_class pipe_class_compare()
4366 %{
4367 single_instruction;
4368 fixed_latency(16);
4369 %}
4370
4371 // Pipeline class for memory operations.
4372 pipe_class pipe_class_memory()
4373 %{
4374 single_instruction;
4375 fixed_latency(16);
4376 %}
4377
4378 // Pipeline class for call.
4379 pipe_class pipe_class_call()
4380 %{
4381 single_instruction;
4382 fixed_latency(100);
4383 %}
4384
4385 // Define the class for the Nop node.
4386 define %{
4387 MachNop = pipe_class_empty;
4388 %}
4389 %}
4390 //----------INSTRUCTIONS-------------------------------------------------------
4391 //
4392 // match -- States which machine-independent subtree may be replaced
4393 // by this instruction.
4394 // ins_cost -- The estimated cost of this instruction is used by instruction
4395 // selection to identify a minimum cost tree of machine
4396 // instructions that matches a tree of machine-independent
4397 // instructions.
4398 // format -- A string providing the disassembly for this instruction.
4399 // The value of an instruction's operand may be inserted
4400 // by referring to it with a '$' prefix.
4401 // opcode -- Three instruction opcodes may be provided. These are referred
4402 // to within an encode class as $primary, $secondary, and $tertiary
4403 // rrspectively. The primary opcode is commonly used to
4404 // indicate the type of machine instruction, while secondary
4405 // and tertiary are often used for prefix options or addressing
4406 // modes.
4407 // ins_encode -- A list of encode classes with parameters. The encode class
4408 // name must have been defined in an 'enc_class' specification
4409 // in the encode section of the architecture description.
4410
4411 // ============================================================================
4412 // Memory (Load/Store) Instructions
4413
4414 // Load Instructions
4415
4416 // Load Byte (8 bit signed)
4417 instruct loadB(iRegINoSp dst, memory mem)
4418 %{
4419 match(Set dst (LoadB mem));
4420
4421 ins_cost(LOAD_COST);
4422 format %{ "lb $dst, $mem\t# byte, #@loadB" %}
4423
4424 ins_encode %{
4425 __ lb(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4426 %}
4427
4428 ins_pipe(iload_reg_mem);
4429 %}
4430
4431 // Load Byte (8 bit signed) into long
4432 instruct loadB2L(iRegLNoSp dst, memory mem)
4433 %{
4434 match(Set dst (ConvI2L (LoadB mem)));
4435
4436 ins_cost(LOAD_COST);
4437 format %{ "lb $dst, $mem\t# byte, #@loadB2L" %}
4438
4439 ins_encode %{
4440 __ lb(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4441 %}
4442
4443 ins_pipe(iload_reg_mem);
4444 %}
4445
4446 // Load Byte (8 bit unsigned)
4447 instruct loadUB(iRegINoSp dst, memory mem)
4448 %{
4449 match(Set dst (LoadUB mem));
4450
4451 ins_cost(LOAD_COST);
4452 format %{ "lbu $dst, $mem\t# byte, #@loadUB" %}
4453
4454 ins_encode %{
4455 __ lbu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4456 %}
4457
4458 ins_pipe(iload_reg_mem);
4459 %}
4460
4461 // Load Byte (8 bit unsigned) into long
4462 instruct loadUB2L(iRegLNoSp dst, memory mem)
4463 %{
4464 match(Set dst (ConvI2L (LoadUB mem)));
4465
4466 ins_cost(LOAD_COST);
4467 format %{ "lbu $dst, $mem\t# byte, #@loadUB2L" %}
4468
4469 ins_encode %{
4470 __ lbu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4471 %}
4472
4473 ins_pipe(iload_reg_mem);
4474 %}
4475
4476 // Load Short (16 bit signed)
4477 instruct loadS(iRegINoSp dst, memory mem)
4478 %{
4479 match(Set dst (LoadS mem));
4480
4481 ins_cost(LOAD_COST);
4482 format %{ "lh $dst, $mem\t# short, #@loadS" %}
4483
4484 ins_encode %{
4485 __ lh(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4486 %}
4487
4488 ins_pipe(iload_reg_mem);
4489 %}
4490
4491 // Load Short (16 bit signed) into long
4492 instruct loadS2L(iRegLNoSp dst, memory mem)
4493 %{
4494 match(Set dst (ConvI2L (LoadS mem)));
4495
4496 ins_cost(LOAD_COST);
4497 format %{ "lh $dst, $mem\t# short, #@loadS2L" %}
4498
4499 ins_encode %{
4500 __ lh(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4501 %}
4502
4503 ins_pipe(iload_reg_mem);
4504 %}
4505
4506 // Load Char (16 bit unsigned)
4507 instruct loadUS(iRegINoSp dst, memory mem)
4508 %{
4509 match(Set dst (LoadUS mem));
4510
4511 ins_cost(LOAD_COST);
4512 format %{ "lhu $dst, $mem\t# short, #@loadUS" %}
4513
4514 ins_encode %{
4515 __ lhu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4516 %}
4517
4518 ins_pipe(iload_reg_mem);
4519 %}
4520
4521 // Load Short/Char (16 bit unsigned) into long
4522 instruct loadUS2L(iRegLNoSp dst, memory mem)
4523 %{
4524 match(Set dst (ConvI2L (LoadUS mem)));
4525
4526 ins_cost(LOAD_COST);
4527 format %{ "lhu $dst, $mem\t# short, #@loadUS2L" %}
4528
4529 ins_encode %{
4530 __ lhu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4531 %}
4532
4533 ins_pipe(iload_reg_mem);
4534 %}
4535
4536 // Load Integer (32 bit signed)
4537 instruct loadI(iRegINoSp dst, memory mem)
4538 %{
4539 match(Set dst (LoadI mem));
4540
4541 ins_cost(LOAD_COST);
4542 format %{ "lw $dst, $mem\t# int, #@loadI" %}
4543
4544 ins_encode %{
4545 __ lw(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4546 %}
4547
4548 ins_pipe(iload_reg_mem);
4549 %}
4550
4551 // Load Integer (32 bit signed) into long
4552 instruct loadI2L(iRegLNoSp dst, memory mem)
4553 %{
4554 match(Set dst (ConvI2L (LoadI mem)));
4555
4556 ins_cost(LOAD_COST);
4557 format %{ "lw $dst, $mem\t# int, #@loadI2L" %}
4558
4559 ins_encode %{
4560 __ lw(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4561 %}
4562
4563 ins_pipe(iload_reg_mem);
4564 %}
4565
4566 // Load Integer (32 bit unsigned) into long
4567 instruct loadUI2L(iRegLNoSp dst, memory mem, immL_32bits mask)
4568 %{
4569 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
4570
4571 ins_cost(LOAD_COST);
4572 format %{ "lwu $dst, $mem\t# int, #@loadUI2L" %}
4573
4574 ins_encode %{
4575 __ lwu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4576 %}
4577
4578 ins_pipe(iload_reg_mem);
4579 %}
4580
4581 // Load Long (64 bit signed)
4582 instruct loadL(iRegLNoSp dst, memory mem)
4583 %{
4584 match(Set dst (LoadL mem));
4585
4586 ins_cost(LOAD_COST);
4587 format %{ "ld $dst, $mem\t# int, #@loadL" %}
4588
4589 ins_encode %{
4590 __ ld(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4591 %}
4592
4593 ins_pipe(iload_reg_mem);
4594 %}
4595
4596 // Load Range
4597 instruct loadRange(iRegINoSp dst, memory mem)
4598 %{
4599 match(Set dst (LoadRange mem));
4600
4601 ins_cost(LOAD_COST);
4602 format %{ "lwu $dst, $mem\t# range, #@loadRange" %}
4603
4604 ins_encode %{
4605 __ lwu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4606 %}
4607
4608 ins_pipe(iload_reg_mem);
4609 %}
4610
4611 // Load Pointer
4612 instruct loadP(iRegPNoSp dst, memory mem)
4613 %{
4614 match(Set dst (LoadP mem));
4615 predicate(n->as_Load()->barrier_data() == 0);
4616
4617 ins_cost(LOAD_COST);
4618 format %{ "ld $dst, $mem\t# ptr, #@loadP" %}
4619
4620 ins_encode %{
4621 __ ld(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4622 %}
4623
4624 ins_pipe(iload_reg_mem);
4625 %}
4626
4627 // Load Compressed Pointer
4628 instruct loadN(iRegNNoSp dst, memory mem)
4629 %{
4630 predicate(n->as_Load()->barrier_data() == 0);
4631 match(Set dst (LoadN mem));
4632
4633 ins_cost(LOAD_COST);
4634 format %{ "lwu $dst, $mem\t# compressed ptr, #@loadN" %}
4635
4636 ins_encode %{
4637 __ lwu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4638 %}
4639
4640 ins_pipe(iload_reg_mem);
4641 %}
4642
4643 // Load Klass Pointer
4644 instruct loadKlass(iRegPNoSp dst, memory mem)
4645 %{
4646 match(Set dst (LoadKlass mem));
4647
4648 ins_cost(LOAD_COST);
4649 format %{ "ld $dst, $mem\t# class, #@loadKlass" %}
4650
4651 ins_encode %{
4652 __ ld(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4653 %}
4654
4655 ins_pipe(iload_reg_mem);
4656 %}
4657
4658 // Load Narrow Klass Pointer
4659 instruct loadNKlass(iRegNNoSp dst, memory mem)
4660 %{
4661 predicate(!UseCompactObjectHeaders);
4662 match(Set dst (LoadNKlass mem));
4663
4664 ins_cost(LOAD_COST);
4665 format %{ "lwu $dst, $mem\t# compressed class ptr, #@loadNKlass" %}
4666
4667 ins_encode %{
4668 __ lwu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4669 %}
4670
4671 ins_pipe(iload_reg_mem);
4672 %}
4673
4674 instruct loadNKlassCompactHeaders(iRegNNoSp dst, memory mem)
4675 %{
4676 predicate(UseCompactObjectHeaders);
4677 match(Set dst (LoadNKlass mem));
4678
4679 ins_cost(LOAD_COST);
4680 format %{
4681 "lwu $dst, $mem\t# compressed klass ptr, shifted\n\t"
4682 "srli $dst, $dst, markWord::klass_shift_at_offset"
4683 %}
4684
4685 ins_encode %{
4686 Unimplemented();
4687 // __ lwu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4688 // __ srli(as_Register($dst$$reg), as_Register($dst$$reg), (unsigned) markWord::klass_shift_at_offset);
4689 %}
4690
4691 ins_pipe(iload_reg_mem);
4692 %}
4693
4694 // Load Float
4695 instruct loadF(fRegF dst, memory mem)
4696 %{
4697 match(Set dst (LoadF mem));
4698
4699 ins_cost(LOAD_COST);
4700 format %{ "flw $dst, $mem\t# float, #@loadF" %}
4701
4702 ins_encode %{
4703 __ flw(as_FloatRegister($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4704 %}
4705
4706 ins_pipe(fp_load_mem_s);
4707 %}
4708
4709 // Load Double
4710 instruct loadD(fRegD dst, memory mem)
4711 %{
4712 match(Set dst (LoadD mem));
4713
4714 ins_cost(LOAD_COST);
4715 format %{ "fld $dst, $mem\t# double, #@loadD" %}
4716
4717 ins_encode %{
4718 __ fld(as_FloatRegister($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4719 %}
4720
4721 ins_pipe(fp_load_mem_d);
4722 %}
4723
4724 // Load Int Constant
4725 instruct loadConI(iRegINoSp dst, immI src)
4726 %{
4727 match(Set dst src);
4728
4729 ins_cost(ALU_COST);
4730 format %{ "mv $dst, $src\t# int, #@loadConI" %}
4731
4732 ins_encode(riscv_enc_mov_imm(dst, src));
4733
4734 ins_pipe(ialu_imm);
4735 %}
4736
4737 // Load Long Constant
4738 instruct loadConL(iRegLNoSp dst, immL src)
4739 %{
4740 match(Set dst src);
4741
4742 ins_cost(ALU_COST);
4743 format %{ "mv $dst, $src\t# long, #@loadConL" %}
4744
4745 ins_encode(riscv_enc_mov_imm(dst, src));
4746
4747 ins_pipe(ialu_imm);
4748 %}
4749
4750 // Load Pointer Constant
4751 instruct loadConP(iRegPNoSp dst, immP con)
4752 %{
4753 match(Set dst con);
4754
4755 ins_cost(ALU_COST);
4756 format %{ "mv $dst, $con\t# ptr, #@loadConP" %}
4757
4758 ins_encode(riscv_enc_mov_p(dst, con));
4759
4760 ins_pipe(ialu_imm);
4761 %}
4762
4763 // Load Null Pointer Constant
4764 instruct loadConP0(iRegPNoSp dst, immP0 con)
4765 %{
4766 match(Set dst con);
4767
4768 ins_cost(ALU_COST);
4769 format %{ "mv $dst, $con\t# null pointer, #@loadConP0" %}
4770
4771 ins_encode(riscv_enc_mov_zero(dst));
4772
4773 ins_pipe(ialu_imm);
4774 %}
4775
4776 // Load Pointer Constant One
4777 instruct loadConP1(iRegPNoSp dst, immP_1 con)
4778 %{
4779 match(Set dst con);
4780
4781 ins_cost(ALU_COST);
4782 format %{ "mv $dst, $con\t# load ptr constant one, #@loadConP1" %}
4783
4784 ins_encode(riscv_enc_mov_p1(dst));
4785
4786 ins_pipe(ialu_imm);
4787 %}
4788
4789 // Load Narrow Pointer Constant
4790 instruct loadConN(iRegNNoSp dst, immN con)
4791 %{
4792 match(Set dst con);
4793
4794 ins_cost(ALU_COST * 4);
4795 format %{ "mv $dst, $con\t# compressed ptr, #@loadConN" %}
4796
4797 ins_encode(riscv_enc_mov_n(dst, con));
4798
4799 ins_pipe(ialu_imm);
4800 %}
4801
4802 // Load Narrow Null Pointer Constant
4803 instruct loadConN0(iRegNNoSp dst, immN0 con)
4804 %{
4805 match(Set dst con);
4806
4807 ins_cost(ALU_COST);
4808 format %{ "mv $dst, $con\t# compressed null pointer, #@loadConN0" %}
4809
4810 ins_encode(riscv_enc_mov_zero(dst));
4811
4812 ins_pipe(ialu_imm);
4813 %}
4814
4815 // Load Narrow Klass Constant
4816 instruct loadConNKlass(iRegNNoSp dst, immNKlass con)
4817 %{
4818 match(Set dst con);
4819
4820 ins_cost(ALU_COST * 6);
4821 format %{ "mv $dst, $con\t# compressed klass ptr, #@loadConNKlass" %}
4822
4823 ins_encode(riscv_enc_mov_nk(dst, con));
4824
4825 ins_pipe(ialu_imm);
4826 %}
4827
4828 // Load Half Float Constant
4829 instruct loadConH(fRegF dst, immH con) %{
4830 match(Set dst con);
4831
4832 ins_cost(LOAD_COST);
4833 format %{
4834 "flh $dst, [$constantaddress]\t# load from constant table: float=$con, #@loadConH"
4835 %}
4836
4837 ins_encode %{
4838 assert(UseZfh || UseZfhmin, "must");
4839 if (MacroAssembler::can_hf_imm_load($con$$constant)) {
4840 __ fli_h(as_FloatRegister($dst$$reg), $con$$constant);
4841 } else {
4842 __ flh(as_FloatRegister($dst$$reg), $constantaddress($con));
4843 }
4844 %}
4845
4846 ins_pipe(fp_load_constant_s);
4847 %}
4848
4849 instruct loadConH0(fRegF dst, immH0 con) %{
4850 match(Set dst con);
4851
4852 ins_cost(XFER_COST);
4853
4854 format %{ "fmv.h.x $dst, zr\t# float, #@loadConH0" %}
4855
4856 ins_encode %{
4857 assert(UseZfh || UseZfhmin, "must");
4858 __ fmv_h_x(as_FloatRegister($dst$$reg), zr);
4859 %}
4860
4861 ins_pipe(fp_load_constant_s);
4862 %}
4863
4864 // Load Float Constant
4865 instruct loadConF(fRegF dst, immF con) %{
4866 match(Set dst con);
4867
4868 ins_cost(LOAD_COST);
4869 format %{
4870 "flw $dst, [$constantaddress]\t# load from constant table: float=$con, #@loadConF"
4871 %}
4872
4873 ins_encode %{
4874 if (MacroAssembler::can_fp_imm_load($con$$constant)) {
4875 __ fli_s(as_FloatRegister($dst$$reg), $con$$constant);
4876 } else {
4877 __ flw(as_FloatRegister($dst$$reg), $constantaddress($con));
4878 }
4879 %}
4880
4881 ins_pipe(fp_load_constant_s);
4882 %}
4883
4884 instruct loadConF0(fRegF dst, immF0 con) %{
4885 match(Set dst con);
4886
4887 ins_cost(XFER_COST);
4888
4889 format %{ "fmv.w.x $dst, zr\t# float, #@loadConF0" %}
4890
4891 ins_encode %{
4892 __ fmv_w_x(as_FloatRegister($dst$$reg), zr);
4893 %}
4894
4895 ins_pipe(fp_load_constant_s);
4896 %}
4897
4898 // Load Double Constant
4899 instruct loadConD(fRegD dst, immD con) %{
4900 match(Set dst con);
4901
4902 ins_cost(LOAD_COST);
4903 format %{
4904 "fld $dst, [$constantaddress]\t# load from constant table: double=$con, #@loadConD"
4905 %}
4906
4907 ins_encode %{
4908 if (MacroAssembler::can_dp_imm_load($con$$constant)) {
4909 __ fli_d(as_FloatRegister($dst$$reg), $con$$constant);
4910 } else {
4911 __ fld(as_FloatRegister($dst$$reg), $constantaddress($con));
4912 }
4913 %}
4914
4915 ins_pipe(fp_load_constant_d);
4916 %}
4917
4918 instruct loadConD0(fRegD dst, immD0 con) %{
4919 match(Set dst con);
4920
4921 ins_cost(XFER_COST);
4922
4923 format %{ "fmv.d.x $dst, zr\t# double, #@loadConD0" %}
4924
4925 ins_encode %{
4926 __ fmv_d_x(as_FloatRegister($dst$$reg), zr);
4927 %}
4928
4929 ins_pipe(fp_load_constant_d);
4930 %}
4931
4932 // Store Byte
4933 instruct storeB(iRegIorL2I src, memory mem)
4934 %{
4935 match(Set mem (StoreB mem src));
4936
4937 ins_cost(STORE_COST);
4938 format %{ "sb $src, $mem\t# byte, #@storeB" %}
4939
4940 ins_encode %{
4941 __ sb(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
4942 %}
4943
4944 ins_pipe(istore_reg_mem);
4945 %}
4946
4947 instruct storeimmB0(immI0 zero, memory mem)
4948 %{
4949 match(Set mem (StoreB mem zero));
4950
4951 ins_cost(STORE_COST);
4952 format %{ "sb zr, $mem\t# byte, #@storeimmB0" %}
4953
4954 ins_encode %{
4955 __ sb(zr, Address(as_Register($mem$$base), $mem$$disp));
4956 %}
4957
4958 ins_pipe(istore_mem);
4959 %}
4960
4961 // Store Char/Short
4962 instruct storeC(iRegIorL2I src, memory mem)
4963 %{
4964 match(Set mem (StoreC mem src));
4965
4966 ins_cost(STORE_COST);
4967 format %{ "sh $src, $mem\t# short, #@storeC" %}
4968
4969 ins_encode %{
4970 __ sh(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
4971 %}
4972
4973 ins_pipe(istore_reg_mem);
4974 %}
4975
4976 instruct storeimmC0(immI0 zero, memory mem)
4977 %{
4978 match(Set mem (StoreC mem zero));
4979
4980 ins_cost(STORE_COST);
4981 format %{ "sh zr, $mem\t# short, #@storeimmC0" %}
4982
4983 ins_encode %{
4984 __ sh(zr, Address(as_Register($mem$$base), $mem$$disp));
4985 %}
4986
4987 ins_pipe(istore_mem);
4988 %}
4989
4990 // Store Integer
4991 instruct storeI(iRegIorL2I src, memory mem)
4992 %{
4993 match(Set mem(StoreI mem src));
4994
4995 ins_cost(STORE_COST);
4996 format %{ "sw $src, $mem\t# int, #@storeI" %}
4997
4998 ins_encode %{
4999 __ sw(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5000 %}
5001
5002 ins_pipe(istore_reg_mem);
5003 %}
5004
5005 instruct storeimmI0(immI0 zero, memory mem)
5006 %{
5007 match(Set mem(StoreI mem zero));
5008
5009 ins_cost(STORE_COST);
5010 format %{ "sw zr, $mem\t# int, #@storeimmI0" %}
5011
5012 ins_encode %{
5013 __ sw(zr, Address(as_Register($mem$$base), $mem$$disp));
5014 %}
5015
5016 ins_pipe(istore_mem);
5017 %}
5018
5019 // Store Long (64 bit signed)
5020 instruct storeL(iRegL src, memory mem)
5021 %{
5022 match(Set mem (StoreL mem src));
5023
5024 ins_cost(STORE_COST);
5025 format %{ "sd $src, $mem\t# long, #@storeL" %}
5026
5027 ins_encode %{
5028 __ sd(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5029 %}
5030
5031 ins_pipe(istore_reg_mem);
5032 %}
5033
5034 // Store Long (64 bit signed)
5035 instruct storeimmL0(immL0 zero, memory mem)
5036 %{
5037 match(Set mem (StoreL mem zero));
5038
5039 ins_cost(STORE_COST);
5040 format %{ "sd zr, $mem\t# long, #@storeimmL0" %}
5041
5042 ins_encode %{
5043 __ sd(zr, Address(as_Register($mem$$base), $mem$$disp));
5044 %}
5045
5046 ins_pipe(istore_mem);
5047 %}
5048
5049 // Store Pointer
5050 instruct storeP(iRegP src, memory mem)
5051 %{
5052 match(Set mem (StoreP mem src));
5053 predicate(n->as_Store()->barrier_data() == 0);
5054
5055 ins_cost(STORE_COST);
5056 format %{ "sd $src, $mem\t# ptr, #@storeP" %}
5057
5058 ins_encode %{
5059 __ sd(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5060 %}
5061
5062 ins_pipe(istore_reg_mem);
5063 %}
5064
5065 // Store Pointer
5066 instruct storeimmP0(immP0 zero, memory mem)
5067 %{
5068 match(Set mem (StoreP mem zero));
5069 predicate(n->as_Store()->barrier_data() == 0);
5070
5071 ins_cost(STORE_COST);
5072 format %{ "sd zr, $mem\t# ptr, #@storeimmP0" %}
5073
5074 ins_encode %{
5075 __ sd(zr, Address(as_Register($mem$$base), $mem$$disp));
5076 %}
5077
5078 ins_pipe(istore_mem);
5079 %}
5080
5081 // Store Compressed Pointer
5082 instruct storeN(iRegN src, memory mem)
5083 %{
5084 predicate(n->as_Store()->barrier_data() == 0);
5085 match(Set mem (StoreN mem src));
5086
5087 ins_cost(STORE_COST);
5088 format %{ "sw $src, $mem\t# compressed ptr, #@storeN" %}
5089
5090 ins_encode %{
5091 __ sw(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5092 %}
5093
5094 ins_pipe(istore_reg_mem);
5095 %}
5096
5097 instruct storeImmN0(immN0 zero, memory mem)
5098 %{
5099 predicate(n->as_Store()->barrier_data() == 0);
5100 match(Set mem (StoreN mem zero));
5101
5102 ins_cost(STORE_COST);
5103 format %{ "sw zr, $mem\t# compressed ptr, #@storeImmN0" %}
5104
5105 ins_encode %{
5106 __ sw(zr, Address(as_Register($mem$$base), $mem$$disp));
5107 %}
5108
5109 ins_pipe(istore_reg_mem);
5110 %}
5111
5112 // Store Float
5113 instruct storeF(fRegF src, memory mem)
5114 %{
5115 match(Set mem (StoreF mem src));
5116
5117 ins_cost(STORE_COST);
5118 format %{ "fsw $src, $mem\t# float, #@storeF" %}
5119
5120 ins_encode %{
5121 __ fsw(as_FloatRegister($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5122 %}
5123
5124 ins_pipe(fp_store_reg_s);
5125 %}
5126
5127 // Store Double
5128 instruct storeD(fRegD src, memory mem)
5129 %{
5130 match(Set mem (StoreD mem src));
5131
5132 ins_cost(STORE_COST);
5133 format %{ "fsd $src, $mem\t# double, #@storeD" %}
5134
5135 ins_encode %{
5136 __ fsd(as_FloatRegister($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5137 %}
5138
5139 ins_pipe(fp_store_reg_d);
5140 %}
5141
5142 // Store Compressed Klass Pointer
5143 instruct storeNKlass(iRegN src, memory mem)
5144 %{
5145 match(Set mem (StoreNKlass mem src));
5146
5147 ins_cost(STORE_COST);
5148 format %{ "sw $src, $mem\t# compressed klass ptr, #@storeNKlass" %}
5149
5150 ins_encode %{
5151 __ sw(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5152 %}
5153
5154 ins_pipe(istore_reg_mem);
5155 %}
5156
5157 // ============================================================================
5158 // Prefetch instructions
5159 // Must be safe to execute with invalid address (cannot fault).
5160
5161 instruct prefetchalloc( memory mem ) %{
5162 predicate(UseZicbop);
5163 match(PrefetchAllocation mem);
5164
5165 ins_cost(ALU_COST * 1);
5166 format %{ "prefetch_w $mem\t# Prefetch for write" %}
5167
5168 ins_encode %{
5169 if (Assembler::is_simm12($mem$$disp)) {
5170 if (($mem$$disp & 0x1f) == 0) {
5171 __ prefetch_w(as_Register($mem$$base), $mem$$disp);
5172 } else {
5173 __ addi(t0, as_Register($mem$$base), $mem$$disp);
5174 __ prefetch_w(t0, 0);
5175 }
5176 } else {
5177 __ mv(t0, $mem$$disp);
5178 __ add(t0, as_Register($mem$$base), t0);
5179 __ prefetch_w(t0, 0);
5180 }
5181 %}
5182
5183 ins_pipe(iload_prefetch);
5184 %}
5185
5186 // ============================================================================
5187 // Atomic operation instructions
5188 //
5189
5190 // standard CompareAndSwapX when we are using barriers
5191 // these have higher priority than the rules selected by a predicate
5192 instruct compareAndSwapB_narrow(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5193 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5194 %{
5195 predicate(!UseZabha || !UseZacas);
5196
5197 match(Set res (CompareAndSwapB mem (Binary oldval newval)));
5198
5199 ins_cost(2 * VOLATILE_REF_COST);
5200
5201 effect(TEMP_DEF res, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3, KILL cr);
5202
5203 format %{
5204 "cmpxchg $mem, $oldval, $newval\t# (byte) if $mem == $oldval then $mem <-- $newval\n\t"
5205 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapB_narrow"
5206 %}
5207
5208 ins_encode %{
5209 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5210 Assembler::relaxed /* acquire */, Assembler::rl /* release */, $res$$Register,
5211 true /* result as bool */, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5212 %}
5213
5214 ins_pipe(pipe_slow);
5215 %}
5216
5217 instruct compareAndSwapB(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5218 %{
5219 predicate(UseZabha && UseZacas);
5220
5221 match(Set res (CompareAndSwapB mem (Binary oldval newval)));
5222
5223 ins_cost(2 * VOLATILE_REF_COST);
5224
5225 format %{
5226 "cmpxchg $mem, $oldval, $newval\t# (byte) if $mem == $oldval then $mem <-- $newval\n\t"
5227 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapB"
5228 %}
5229
5230 ins_encode %{
5231 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5232 Assembler::relaxed /* acquire */, Assembler::rl /* release */, $res$$Register,
5233 true /* result as bool */);
5234 %}
5235
5236 ins_pipe(pipe_slow);
5237 %}
5238
5239 instruct compareAndSwapS_narrow(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5240 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5241 %{
5242 predicate(!UseZabha || !UseZacas);
5243
5244 match(Set res (CompareAndSwapS mem (Binary oldval newval)));
5245
5246 ins_cost(2 * VOLATILE_REF_COST);
5247
5248 effect(TEMP_DEF res, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3, KILL cr);
5249
5250 format %{
5251 "cmpxchg $mem, $oldval, $newval\t# (short) if $mem == $oldval then $mem <-- $newval\n\t"
5252 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapS_narrow"
5253 %}
5254
5255 ins_encode %{
5256 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5257 Assembler::relaxed /* acquire */, Assembler::rl /* release */, $res$$Register,
5258 true /* result as bool */, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5259 %}
5260
5261 ins_pipe(pipe_slow);
5262 %}
5263
5264 instruct compareAndSwapS(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5265 %{
5266 predicate(UseZabha && UseZacas);
5267
5268 match(Set res (CompareAndSwapS mem (Binary oldval newval)));
5269
5270 ins_cost(2 * VOLATILE_REF_COST);
5271
5272 format %{
5273 "cmpxchg $mem, $oldval, $newval\t# (short) if $mem == $oldval then $mem <-- $newval\n\t"
5274 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapS"
5275 %}
5276
5277 ins_encode %{
5278 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5279 Assembler::relaxed /* acquire */, Assembler::rl /* release */, $res$$Register,
5280 true /* result as bool */);
5281 %}
5282
5283 ins_pipe(pipe_slow);
5284 %}
5285
5286 instruct compareAndSwapI(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5287 %{
5288 match(Set res (CompareAndSwapI mem (Binary oldval newval)));
5289
5290 ins_cost(2 * VOLATILE_REF_COST);
5291
5292 format %{
5293 "cmpxchg $mem, $oldval, $newval\t# (int) if $mem == $oldval then $mem <-- $newval\n\t"
5294 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapI"
5295 %}
5296
5297 ins_encode %{
5298 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
5299 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
5300 /*result as bool*/ true);
5301 %}
5302
5303 ins_pipe(pipe_slow);
5304 %}
5305
5306 instruct compareAndSwapL(iRegINoSp res, indirect mem, iRegL oldval, iRegL newval)
5307 %{
5308 match(Set res (CompareAndSwapL mem (Binary oldval newval)));
5309
5310 ins_cost(2 * VOLATILE_REF_COST);
5311
5312 format %{
5313 "cmpxchg $mem, $oldval, $newval\t# (long) if $mem == $oldval then $mem <-- $newval\n\t"
5314 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapL"
5315 %}
5316
5317 ins_encode %{
5318 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5319 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
5320 /*result as bool*/ true);
5321 %}
5322
5323 ins_pipe(pipe_slow);
5324 %}
5325
5326 instruct compareAndSwapP(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval)
5327 %{
5328 predicate(n->as_LoadStore()->barrier_data() == 0);
5329
5330 match(Set res (CompareAndSwapP mem (Binary oldval newval)));
5331
5332 ins_cost(2 * VOLATILE_REF_COST);
5333
5334 format %{
5335 "cmpxchg $mem, $oldval, $newval\t# (ptr) if $mem == $oldval then $mem <-- $newval\n\t"
5336 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapP"
5337 %}
5338
5339 ins_encode %{
5340 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5341 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
5342 /*result as bool*/ true);
5343 %}
5344
5345 ins_pipe(pipe_slow);
5346 %}
5347
5348 instruct compareAndSwapN(iRegINoSp res, indirect mem, iRegN oldval, iRegN newval)
5349 %{
5350 predicate(n->as_LoadStore()->barrier_data() == 0);
5351
5352 match(Set res (CompareAndSwapN mem (Binary oldval newval)));
5353
5354 ins_cost(2 * VOLATILE_REF_COST);
5355
5356 format %{
5357 "cmpxchg $mem, $oldval, $newval\t# (narrow oop) if $mem == $oldval then $mem <-- $newval\n\t"
5358 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapN"
5359 %}
5360
5361 ins_encode %{
5362 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
5363 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
5364 /*result as bool*/ true);
5365 %}
5366
5367 ins_pipe(pipe_slow);
5368 %}
5369
5370 // alternative CompareAndSwapX when we are eliding barriers
5371 instruct compareAndSwapBAcq_narrow(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5372 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5373 %{
5374 predicate((!UseZabha || !UseZacas) && needs_acquiring_load_reserved(n));
5375
5376 match(Set res (CompareAndSwapB mem (Binary oldval newval)));
5377
5378 ins_cost(2 * VOLATILE_REF_COST);
5379
5380 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5381
5382 format %{
5383 "cmpxchg_acq $mem, $oldval, $newval\t# (byte) if $mem == $oldval then $mem <-- $newval\n\t"
5384 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapBAcq_narrow"
5385 %}
5386
5387 ins_encode %{
5388 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5389 Assembler::aq /* acquire */, Assembler::rl /* release */, $res$$Register,
5390 true /* result as bool */, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5391 %}
5392
5393 ins_pipe(pipe_slow);
5394 %}
5395
5396 instruct compareAndSwapBAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5397 %{
5398 predicate((UseZabha && UseZacas) && needs_acquiring_load_reserved(n));
5399
5400 match(Set res (CompareAndSwapB mem (Binary oldval newval)));
5401
5402 ins_cost(2 * VOLATILE_REF_COST);
5403
5404 format %{
5405 "cmpxchg $mem, $oldval, $newval\t# (byte) if $mem == $oldval then $mem <-- $newval\n\t"
5406 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapBAcq"
5407 %}
5408
5409 ins_encode %{
5410 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5411 Assembler::aq /* acquire */, Assembler::rl /* release */, $res$$Register,
5412 true /* result as bool */);
5413 %}
5414
5415 ins_pipe(pipe_slow);
5416 %}
5417
5418 instruct compareAndSwapSAcq_narrow(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5419 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5420 %{
5421 predicate((!UseZabha || !UseZacas) && needs_acquiring_load_reserved(n));
5422
5423 match(Set res (CompareAndSwapS mem (Binary oldval newval)));
5424
5425 ins_cost(2 * VOLATILE_REF_COST);
5426
5427 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5428
5429 format %{
5430 "cmpxchg_acq $mem, $oldval, $newval\t# (short) if $mem == $oldval then $mem <-- $newval\n\t"
5431 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapSAcq_narrow"
5432 %}
5433
5434 ins_encode %{
5435 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5436 Assembler::aq /* acquire */, Assembler::rl /* release */, $res$$Register,
5437 true /* result as bool */, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5438 %}
5439
5440 ins_pipe(pipe_slow);
5441 %}
5442
5443 instruct compareAndSwapSAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5444 %{
5445 predicate((UseZabha && UseZacas) && needs_acquiring_load_reserved(n));
5446
5447 match(Set res (CompareAndSwapS mem (Binary oldval newval)));
5448
5449 ins_cost(2 * VOLATILE_REF_COST);
5450
5451 format %{
5452 "cmpxchg $mem, $oldval, $newval\t# (short) if $mem == $oldval then $mem <-- $newval\n\t"
5453 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapSAcq"
5454 %}
5455
5456 ins_encode %{
5457 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5458 Assembler::aq /* acquire */, Assembler::rl /* release */, $res$$Register,
5459 true /* result as bool */);
5460 %}
5461
5462 ins_pipe(pipe_slow);
5463 %}
5464
5465 instruct compareAndSwapIAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5466 %{
5467 predicate(needs_acquiring_load_reserved(n));
5468
5469 match(Set res (CompareAndSwapI mem (Binary oldval newval)));
5470
5471 ins_cost(2 * VOLATILE_REF_COST);
5472
5473 format %{
5474 "cmpxchg_acq $mem, $oldval, $newval\t# (int) if $mem == $oldval then $mem <-- $newval\n\t"
5475 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapIAcq"
5476 %}
5477
5478 ins_encode %{
5479 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
5480 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
5481 /*result as bool*/ true);
5482 %}
5483
5484 ins_pipe(pipe_slow);
5485 %}
5486
5487 instruct compareAndSwapLAcq(iRegINoSp res, indirect mem, iRegL oldval, iRegL newval)
5488 %{
5489 predicate(needs_acquiring_load_reserved(n));
5490
5491 match(Set res (CompareAndSwapL mem (Binary oldval newval)));
5492
5493 ins_cost(2 * VOLATILE_REF_COST);
5494
5495 format %{
5496 "cmpxchg_acq $mem, $oldval, $newval\t# (long) if $mem == $oldval then $mem <-- $newval\n\t"
5497 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapLAcq"
5498 %}
5499
5500 ins_encode %{
5501 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5502 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
5503 /*result as bool*/ true);
5504 %}
5505
5506 ins_pipe(pipe_slow);
5507 %}
5508
5509 instruct compareAndSwapPAcq(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval)
5510 %{
5511 predicate(needs_acquiring_load_reserved(n) && (n->as_LoadStore()->barrier_data() == 0));
5512
5513 match(Set res (CompareAndSwapP mem (Binary oldval newval)));
5514
5515 ins_cost(2 * VOLATILE_REF_COST);
5516
5517 format %{
5518 "cmpxchg_acq $mem, $oldval, $newval\t# (ptr) if $mem == $oldval then $mem <-- $newval\n\t"
5519 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapPAcq"
5520 %}
5521
5522 ins_encode %{
5523 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5524 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
5525 /*result as bool*/ true);
5526 %}
5527
5528 ins_pipe(pipe_slow);
5529 %}
5530
5531 instruct compareAndSwapNAcq(iRegINoSp res, indirect mem, iRegN oldval, iRegN newval)
5532 %{
5533 predicate(needs_acquiring_load_reserved(n) && n->as_LoadStore()->barrier_data() == 0);
5534
5535 match(Set res (CompareAndSwapN mem (Binary oldval newval)));
5536
5537 ins_cost(2 * VOLATILE_REF_COST);
5538
5539 format %{
5540 "cmpxchg_acq $mem, $oldval, $newval\t# (narrow oop) if $mem == $oldval then $mem <-- $newval\n\t"
5541 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapNAcq"
5542 %}
5543
5544 ins_encode %{
5545 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
5546 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
5547 /*result as bool*/ true);
5548 %}
5549
5550 ins_pipe(pipe_slow);
5551 %}
5552
5553 // Sundry CAS operations. Note that release is always true,
5554 // regardless of the memory ordering of the CAS. This is because we
5555 // need the volatile case to be sequentially consistent but there is
5556 // no trailing StoreLoad barrier emitted by C2. Unfortunately we
5557 // can't check the type of memory ordering here, so we always emit a
5558 // sc_d(w) with rl bit set.
5559 instruct compareAndExchangeB_narrow(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5560 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5561 %{
5562 predicate(!UseZabha || !UseZacas);
5563
5564 match(Set res (CompareAndExchangeB mem (Binary oldval newval)));
5565
5566 ins_cost(2 * VOLATILE_REF_COST);
5567
5568 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5569
5570 format %{
5571 "cmpxchg $res = $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeB_narrow"
5572 %}
5573
5574 ins_encode %{
5575 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5576 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
5577 /*result_as_bool*/ false, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5578 %}
5579
5580 ins_pipe(pipe_slow);
5581 %}
5582
5583 instruct compareAndExchangeB(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5584 %{
5585 predicate(UseZabha && UseZacas);
5586
5587 match(Set res (CompareAndExchangeB mem (Binary oldval newval)));
5588
5589 ins_cost(2 * VOLATILE_REF_COST);
5590
5591 format %{
5592 "cmpxchg $res = $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeB"
5593 %}
5594
5595 ins_encode %{
5596 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5597 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5598 %}
5599
5600 ins_pipe(pipe_slow);
5601 %}
5602
5603 instruct compareAndExchangeS_narrow(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5604 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5605 %{
5606 predicate(!UseZabha || !UseZacas);
5607
5608 match(Set res (CompareAndExchangeS mem (Binary oldval newval)));
5609
5610 ins_cost(2 * VOLATILE_REF_COST);
5611
5612 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5613
5614 format %{
5615 "cmpxchg $res = $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeS_narrow"
5616 %}
5617
5618 ins_encode %{
5619 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5620 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
5621 /*result_as_bool*/ false, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5622 %}
5623
5624 ins_pipe(pipe_slow);
5625 %}
5626
5627 instruct compareAndExchangeS(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5628 %{
5629 predicate(UseZabha && UseZacas);
5630
5631 match(Set res (CompareAndExchangeS mem (Binary oldval newval)));
5632
5633 ins_cost(2 * VOLATILE_REF_COST);
5634
5635 format %{
5636 "cmpxchg $res = $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeS"
5637 %}
5638
5639 ins_encode %{
5640 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5641 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5642 %}
5643
5644 ins_pipe(pipe_slow);
5645 %}
5646
5647 instruct compareAndExchangeI(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5648 %{
5649 match(Set res (CompareAndExchangeI mem (Binary oldval newval)));
5650
5651 ins_cost(2 * VOLATILE_REF_COST);
5652
5653 format %{
5654 "cmpxchg $res = $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeI"
5655 %}
5656
5657 ins_encode %{
5658 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
5659 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5660 %}
5661
5662 ins_pipe(pipe_slow);
5663 %}
5664
5665 instruct compareAndExchangeL(iRegLNoSp res, indirect mem, iRegL oldval, iRegL newval)
5666 %{
5667 match(Set res (CompareAndExchangeL mem (Binary oldval newval)));
5668
5669 ins_cost(2 * VOLATILE_REF_COST);
5670
5671 format %{
5672 "cmpxchg $res = $mem, $oldval, $newval\t# (long, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeL"
5673 %}
5674
5675 ins_encode %{
5676 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5677 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5678 %}
5679
5680 ins_pipe(pipe_slow);
5681 %}
5682
5683 instruct compareAndExchangeN(iRegNNoSp res, indirect mem, iRegN oldval, iRegN newval)
5684 %{
5685 predicate(n->as_LoadStore()->barrier_data() == 0);
5686
5687 match(Set res (CompareAndExchangeN mem (Binary oldval newval)));
5688
5689 ins_cost(2 * VOLATILE_REF_COST);
5690
5691 format %{
5692 "cmpxchg $res = $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeN"
5693 %}
5694
5695 ins_encode %{
5696 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
5697 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5698 %}
5699
5700 ins_pipe(pipe_slow);
5701 %}
5702
5703 instruct compareAndExchangeP(iRegPNoSp res, indirect mem, iRegP oldval, iRegP newval)
5704 %{
5705 predicate(n->as_LoadStore()->barrier_data() == 0);
5706
5707 match(Set res (CompareAndExchangeP mem (Binary oldval newval)));
5708
5709 ins_cost(2 * VOLATILE_REF_COST);
5710
5711 format %{
5712 "cmpxchg $res = $mem, $oldval, $newval\t# (ptr, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeP"
5713 %}
5714
5715 ins_encode %{
5716 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5717 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5718 %}
5719
5720 ins_pipe(pipe_slow);
5721 %}
5722
5723 instruct compareAndExchangeBAcq_narrow(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5724 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5725 %{
5726 predicate((!UseZabha || !UseZacas) && needs_acquiring_load_reserved(n));
5727
5728 match(Set res (CompareAndExchangeB mem (Binary oldval newval)));
5729
5730 ins_cost(2 * VOLATILE_REF_COST);
5731
5732 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5733
5734 format %{
5735 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeBAcq_narrow"
5736 %}
5737
5738 ins_encode %{
5739 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5740 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
5741 /*result_as_bool*/ false, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5742 %}
5743
5744 ins_pipe(pipe_slow);
5745 %}
5746
5747 instruct compareAndExchangeBAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5748 %{
5749 predicate((UseZabha && UseZacas) && needs_acquiring_load_reserved(n));
5750
5751 match(Set res (CompareAndExchangeB mem (Binary oldval newval)));
5752
5753 ins_cost(2 * VOLATILE_REF_COST);
5754
5755 format %{
5756 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeBAcq"
5757 %}
5758
5759 ins_encode %{
5760 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5761 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
5762 %}
5763
5764 ins_pipe(pipe_slow);
5765 %}
5766
5767 instruct compareAndExchangeSAcq_narrow(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5768 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5769 %{
5770 predicate((!UseZabha || !UseZacas) && needs_acquiring_load_reserved(n));
5771
5772 match(Set res (CompareAndExchangeS mem (Binary oldval newval)));
5773
5774 ins_cost(2 * VOLATILE_REF_COST);
5775
5776 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5777
5778 format %{
5779 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeSAcq_narrow"
5780 %}
5781
5782 ins_encode %{
5783 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5784 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
5785 /*result_as_bool*/ false, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5786 %}
5787
5788 ins_pipe(pipe_slow);
5789 %}
5790
5791 instruct compareAndExchangeSAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5792 %{
5793 predicate((UseZabha && UseZacas) && needs_acquiring_load_reserved(n));
5794
5795 match(Set res (CompareAndExchangeS mem (Binary oldval newval)));
5796
5797 ins_cost(2 * VOLATILE_REF_COST);
5798
5799 format %{
5800 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeSAcq"
5801 %}
5802
5803 ins_encode %{
5804 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5805 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
5806 %}
5807
5808 ins_pipe(pipe_slow);
5809 %}
5810
5811 instruct compareAndExchangeIAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5812 %{
5813 predicate(needs_acquiring_load_reserved(n));
5814
5815 match(Set res (CompareAndExchangeI mem (Binary oldval newval)));
5816
5817 ins_cost(2 * VOLATILE_REF_COST);
5818
5819 format %{
5820 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeIAcq"
5821 %}
5822
5823 ins_encode %{
5824 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
5825 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
5826 %}
5827
5828 ins_pipe(pipe_slow);
5829 %}
5830
5831 instruct compareAndExchangeLAcq(iRegLNoSp res, indirect mem, iRegL oldval, iRegL newval)
5832 %{
5833 predicate(needs_acquiring_load_reserved(n));
5834
5835 match(Set res (CompareAndExchangeL mem (Binary oldval newval)));
5836
5837 ins_cost(2 * VOLATILE_REF_COST);
5838
5839 format %{
5840 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (long, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeLAcq"
5841 %}
5842
5843 ins_encode %{
5844 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5845 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
5846 %}
5847
5848 ins_pipe(pipe_slow);
5849 %}
5850
5851 instruct compareAndExchangeNAcq(iRegNNoSp res, indirect mem, iRegN oldval, iRegN newval)
5852 %{
5853 predicate(needs_acquiring_load_reserved(n) && n->as_LoadStore()->barrier_data() == 0);
5854
5855 match(Set res (CompareAndExchangeN mem (Binary oldval newval)));
5856
5857 ins_cost(2 * VOLATILE_REF_COST);
5858
5859 format %{
5860 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeNAcq"
5861 %}
5862
5863 ins_encode %{
5864 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
5865 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
5866 %}
5867
5868 ins_pipe(pipe_slow);
5869 %}
5870
5871 instruct compareAndExchangePAcq(iRegPNoSp res, indirect mem, iRegP oldval, iRegP newval)
5872 %{
5873 predicate(needs_acquiring_load_reserved(n) && (n->as_LoadStore()->barrier_data() == 0));
5874
5875 match(Set res (CompareAndExchangeP mem (Binary oldval newval)));
5876
5877 ins_cost(2 * VOLATILE_REF_COST);
5878
5879 format %{
5880 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (ptr, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangePAcq"
5881 %}
5882
5883 ins_encode %{
5884 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5885 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
5886 %}
5887
5888 ins_pipe(pipe_slow);
5889 %}
5890
5891 instruct weakCompareAndSwapB_narrow(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5892 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5893 %{
5894 predicate(!UseZabha || !UseZacas);
5895
5896 match(Set res (WeakCompareAndSwapB mem (Binary oldval newval)));
5897
5898 ins_cost(2 * VOLATILE_REF_COST);
5899
5900 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5901
5902 format %{
5903 "weak_cmpxchg $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5904 "# $res == 1 when success, #@weakCompareAndSwapB_narrow"
5905 %}
5906
5907 ins_encode %{
5908 __ weak_cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5909 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
5910 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5911 %}
5912
5913 ins_pipe(pipe_slow);
5914 %}
5915
5916 instruct weakCompareAndSwapB(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5917 %{
5918 predicate(UseZabha && UseZacas);
5919
5920 match(Set res (WeakCompareAndSwapB mem (Binary oldval newval)));
5921
5922 ins_cost(2 * VOLATILE_REF_COST);
5923
5924 format %{
5925 "weak_cmpxchg $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5926 "# $res == 1 when success, #@weakCompareAndSwapB"
5927 %}
5928
5929 ins_encode %{
5930 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5931 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5932 %}
5933
5934 ins_pipe(pipe_slow);
5935 %}
5936
5937 instruct weakCompareAndSwapS_narrow(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5938 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5939 %{
5940 predicate(!UseZabha || !UseZacas);
5941
5942 match(Set res (WeakCompareAndSwapS mem (Binary oldval newval)));
5943
5944 ins_cost(2 * VOLATILE_REF_COST);
5945
5946 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5947
5948 format %{
5949 "weak_cmpxchg $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5950 "# $res == 1 when success, #@weakCompareAndSwapS_narrow"
5951 %}
5952
5953 ins_encode %{
5954 __ weak_cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5955 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
5956 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5957 %}
5958
5959 ins_pipe(pipe_slow);
5960 %}
5961
5962 instruct weakCompareAndSwapS(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5963 %{
5964 predicate(UseZabha && UseZacas);
5965
5966 match(Set res (WeakCompareAndSwapS mem (Binary oldval newval)));
5967
5968 ins_cost(2 * VOLATILE_REF_COST);
5969
5970 format %{
5971 "weak_cmpxchg $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5972 "# $res == 1 when success, #@weakCompareAndSwapS"
5973 %}
5974
5975 ins_encode %{
5976 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5977 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5978 %}
5979
5980 ins_pipe(pipe_slow);
5981 %}
5982
5983 instruct weakCompareAndSwapI(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5984 %{
5985 match(Set res (WeakCompareAndSwapI mem (Binary oldval newval)));
5986
5987 ins_cost(2 * VOLATILE_REF_COST);
5988
5989 format %{
5990 "weak_cmpxchg $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5991 "# $res == 1 when success, #@weakCompareAndSwapI"
5992 %}
5993
5994 ins_encode %{
5995 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
5996 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5997 %}
5998
5999 ins_pipe(pipe_slow);
6000 %}
6001
6002 instruct weakCompareAndSwapL(iRegINoSp res, indirect mem, iRegL oldval, iRegL newval)
6003 %{
6004 match(Set res (WeakCompareAndSwapL mem (Binary oldval newval)));
6005
6006 ins_cost(2 * VOLATILE_REF_COST);
6007
6008 format %{
6009 "weak_cmpxchg $mem, $oldval, $newval\t# (long, weak) if $mem == $oldval then $mem <-- $newval\n\t"
6010 "# $res == 1 when success, #@weakCompareAndSwapL"
6011 %}
6012
6013 ins_encode %{
6014 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
6015 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
6016 %}
6017
6018 ins_pipe(pipe_slow);
6019 %}
6020
6021 instruct weakCompareAndSwapN(iRegINoSp res, indirect mem, iRegN oldval, iRegN newval)
6022 %{
6023 predicate(n->as_LoadStore()->barrier_data() == 0);
6024
6025 match(Set res (WeakCompareAndSwapN mem (Binary oldval newval)));
6026
6027 ins_cost(2 * VOLATILE_REF_COST);
6028
6029 format %{
6030 "weak_cmpxchg $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval\n\t"
6031 "# $res == 1 when success, #@weakCompareAndSwapN"
6032 %}
6033
6034 ins_encode %{
6035 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
6036 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
6037 %}
6038
6039 ins_pipe(pipe_slow);
6040 %}
6041
6042 instruct weakCompareAndSwapP(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval)
6043 %{
6044 predicate(n->as_LoadStore()->barrier_data() == 0);
6045
6046 match(Set res (WeakCompareAndSwapP mem (Binary oldval newval)));
6047
6048 ins_cost(2 * VOLATILE_REF_COST);
6049
6050 format %{
6051 "weak_cmpxchg $mem, $oldval, $newval\t# (ptr, weak) if $mem == $oldval then $mem <-- $newval\n\t"
6052 "# $res == 1 when success, #@weakCompareAndSwapP"
6053 %}
6054
6055 ins_encode %{
6056 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
6057 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
6058 %}
6059
6060 ins_pipe(pipe_slow);
6061 %}
6062
6063 instruct weakCompareAndSwapBAcq_narrow(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
6064 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
6065 %{
6066 predicate((!UseZabha || !UseZacas) && needs_acquiring_load_reserved(n));
6067
6068 match(Set res (WeakCompareAndSwapB mem (Binary oldval newval)));
6069
6070 ins_cost(2 * VOLATILE_REF_COST);
6071
6072 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
6073
6074 format %{
6075 "weak_cmpxchg_acq $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval\n\t"
6076 "# $res == 1 when success, #@weakCompareAndSwapBAcq_narrow"
6077 %}
6078
6079 ins_encode %{
6080 __ weak_cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
6081 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
6082 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
6083 %}
6084
6085 ins_pipe(pipe_slow);
6086 %}
6087
6088 instruct weakCompareAndSwapBAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
6089 %{
6090 predicate((UseZabha && UseZacas) && needs_acquiring_load_reserved(n));
6091
6092 match(Set res (WeakCompareAndSwapB mem (Binary oldval newval)));
6093
6094 ins_cost(2 * VOLATILE_REF_COST);
6095
6096 format %{
6097 "weak_cmpxchg_acq $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval\n\t"
6098 "# $res == 1 when success, #@weakCompareAndSwapBAcq"
6099 %}
6100
6101 ins_encode %{
6102 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
6103 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
6104 %}
6105
6106 ins_pipe(pipe_slow);
6107 %}
6108
6109 instruct weakCompareAndSwapSAcq_narrow(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
6110 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
6111 %{
6112 predicate((!UseZabha || !UseZacas) && needs_acquiring_load_reserved(n));
6113
6114 match(Set res (WeakCompareAndSwapS mem (Binary oldval newval)));
6115
6116 ins_cost(2 * VOLATILE_REF_COST);
6117
6118 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
6119
6120 format %{
6121 "weak_cmpxchg_acq $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval\n\t"
6122 "# $res == 1 when success, #@weakCompareAndSwapSAcq_narrow"
6123 %}
6124
6125 ins_encode %{
6126 __ weak_cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
6127 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
6128 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
6129 %}
6130
6131 ins_pipe(pipe_slow);
6132 %}
6133
6134 instruct weakCompareAndSwapSAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
6135 %{
6136 predicate((UseZabha && UseZacas) && needs_acquiring_load_reserved(n));
6137
6138 match(Set res (WeakCompareAndSwapS mem (Binary oldval newval)));
6139
6140 ins_cost(2 * VOLATILE_REF_COST);
6141
6142 format %{
6143 "weak_cmpxchg_acq $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval\n\t"
6144 "# $res == 1 when success, #@weakCompareAndSwapSAcq"
6145 %}
6146
6147 ins_encode %{
6148 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
6149 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
6150 %}
6151
6152 ins_pipe(pipe_slow);
6153 %}
6154
6155 instruct weakCompareAndSwapIAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
6156 %{
6157 predicate(needs_acquiring_load_reserved(n));
6158
6159 match(Set res (WeakCompareAndSwapI mem (Binary oldval newval)));
6160
6161 ins_cost(2 * VOLATILE_REF_COST);
6162
6163 format %{
6164 "weak_cmpxchg_acq $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval\n\t"
6165 "# $res == 1 when success, #@weakCompareAndSwapIAcq"
6166 %}
6167
6168 ins_encode %{
6169 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
6170 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
6171 %}
6172
6173 ins_pipe(pipe_slow);
6174 %}
6175
6176 instruct weakCompareAndSwapLAcq(iRegINoSp res, indirect mem, iRegL oldval, iRegL newval)
6177 %{
6178 predicate(needs_acquiring_load_reserved(n));
6179
6180 match(Set res (WeakCompareAndSwapL mem (Binary oldval newval)));
6181
6182 ins_cost(2 * VOLATILE_REF_COST);
6183
6184 format %{
6185 "weak_cmpxchg_acq $mem, $oldval, $newval\t# (long, weak) if $mem == $oldval then $mem <-- $newval\n\t"
6186 "# $res == 1 when success, #@weakCompareAndSwapLAcq"
6187 %}
6188
6189 ins_encode %{
6190 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
6191 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
6192 %}
6193
6194 ins_pipe(pipe_slow);
6195 %}
6196
6197 instruct weakCompareAndSwapNAcq(iRegINoSp res, indirect mem, iRegN oldval, iRegN newval)
6198 %{
6199 predicate(needs_acquiring_load_reserved(n) && n->as_LoadStore()->barrier_data() == 0);
6200
6201 match(Set res (WeakCompareAndSwapN mem (Binary oldval newval)));
6202
6203 ins_cost(2 * VOLATILE_REF_COST);
6204
6205 format %{
6206 "weak_cmpxchg_acq $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval\n\t"
6207 "# $res == 1 when success, #@weakCompareAndSwapNAcq"
6208 %}
6209
6210 ins_encode %{
6211 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
6212 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
6213 %}
6214
6215 ins_pipe(pipe_slow);
6216 %}
6217
6218 instruct weakCompareAndSwapPAcq(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval)
6219 %{
6220 predicate(needs_acquiring_load_reserved(n) && (n->as_LoadStore()->barrier_data() == 0));
6221
6222 match(Set res (WeakCompareAndSwapP mem (Binary oldval newval)));
6223
6224 ins_cost(2 * VOLATILE_REF_COST);
6225
6226 format %{
6227 "weak_cmpxchg_acq $mem, $oldval, $newval\t# (ptr, weak) if $mem == $oldval then $mem <-- $newval\n\t"
6228 "\t# $res == 1 when success, #@weakCompareAndSwapPAcq"
6229 %}
6230
6231 ins_encode %{
6232 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
6233 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
6234 %}
6235
6236 ins_pipe(pipe_slow);
6237 %}
6238
6239 instruct get_and_setI(indirect mem, iRegI newv, iRegINoSp prev)
6240 %{
6241 match(Set prev (GetAndSetI mem newv));
6242
6243 ins_cost(ALU_COST);
6244
6245 format %{ "atomic_xchgw $prev, $newv, [$mem]\t#@get_and_setI" %}
6246
6247 ins_encode %{
6248 __ atomic_xchgw($prev$$Register, $newv$$Register, as_Register($mem$$base));
6249 %}
6250
6251 ins_pipe(pipe_serial);
6252 %}
6253
6254 instruct get_and_setL(indirect mem, iRegL newv, iRegLNoSp prev)
6255 %{
6256 match(Set prev (GetAndSetL mem newv));
6257
6258 ins_cost(ALU_COST);
6259
6260 format %{ "atomic_xchg $prev, $newv, [$mem]\t#@get_and_setL" %}
6261
6262 ins_encode %{
6263 __ atomic_xchg($prev$$Register, $newv$$Register, as_Register($mem$$base));
6264 %}
6265
6266 ins_pipe(pipe_serial);
6267 %}
6268
6269 instruct get_and_setN(indirect mem, iRegN newv, iRegINoSp prev)
6270 %{
6271 predicate(n->as_LoadStore()->barrier_data() == 0);
6272
6273 match(Set prev (GetAndSetN mem newv));
6274
6275 ins_cost(ALU_COST);
6276
6277 format %{ "atomic_xchgwu $prev, $newv, [$mem]\t#@get_and_setN" %}
6278
6279 ins_encode %{
6280 __ atomic_xchgwu($prev$$Register, $newv$$Register, as_Register($mem$$base));
6281 %}
6282
6283 ins_pipe(pipe_serial);
6284 %}
6285
6286 instruct get_and_setP(indirect mem, iRegP newv, iRegPNoSp prev)
6287 %{
6288 predicate(n->as_LoadStore()->barrier_data() == 0);
6289 match(Set prev (GetAndSetP mem newv));
6290
6291 ins_cost(ALU_COST);
6292
6293 format %{ "atomic_xchg $prev, $newv, [$mem]\t#@get_and_setP" %}
6294
6295 ins_encode %{
6296 __ atomic_xchg($prev$$Register, $newv$$Register, as_Register($mem$$base));
6297 %}
6298
6299 ins_pipe(pipe_serial);
6300 %}
6301
6302 instruct get_and_setIAcq(indirect mem, iRegI newv, iRegINoSp prev)
6303 %{
6304 predicate(needs_acquiring_load_reserved(n));
6305
6306 match(Set prev (GetAndSetI mem newv));
6307
6308 ins_cost(ALU_COST);
6309
6310 format %{ "atomic_xchgw_acq $prev, $newv, [$mem]\t#@get_and_setIAcq" %}
6311
6312 ins_encode %{
6313 __ atomic_xchgalw($prev$$Register, $newv$$Register, as_Register($mem$$base));
6314 %}
6315
6316 ins_pipe(pipe_serial);
6317 %}
6318
6319 instruct get_and_setLAcq(indirect mem, iRegL newv, iRegLNoSp prev)
6320 %{
6321 predicate(needs_acquiring_load_reserved(n));
6322
6323 match(Set prev (GetAndSetL mem newv));
6324
6325 ins_cost(ALU_COST);
6326
6327 format %{ "atomic_xchg_acq $prev, $newv, [$mem]\t#@get_and_setLAcq" %}
6328
6329 ins_encode %{
6330 __ atomic_xchgal($prev$$Register, $newv$$Register, as_Register($mem$$base));
6331 %}
6332
6333 ins_pipe(pipe_serial);
6334 %}
6335
6336 instruct get_and_setNAcq(indirect mem, iRegN newv, iRegINoSp prev)
6337 %{
6338 predicate(needs_acquiring_load_reserved(n) && n->as_LoadStore()->barrier_data() == 0);
6339
6340 match(Set prev (GetAndSetN mem newv));
6341
6342 ins_cost(ALU_COST);
6343
6344 format %{ "atomic_xchgwu_acq $prev, $newv, [$mem]\t#@get_and_setNAcq" %}
6345
6346 ins_encode %{
6347 __ atomic_xchgalwu($prev$$Register, $newv$$Register, as_Register($mem$$base));
6348 %}
6349
6350 ins_pipe(pipe_serial);
6351 %}
6352
6353 instruct get_and_setPAcq(indirect mem, iRegP newv, iRegPNoSp prev)
6354 %{
6355 predicate(needs_acquiring_load_reserved(n) && (n->as_LoadStore()->barrier_data() == 0));
6356
6357 match(Set prev (GetAndSetP mem newv));
6358
6359 ins_cost(ALU_COST);
6360
6361 format %{ "atomic_xchg_acq $prev, $newv, [$mem]\t#@get_and_setPAcq" %}
6362
6363 ins_encode %{
6364 __ atomic_xchgal($prev$$Register, $newv$$Register, as_Register($mem$$base));
6365 %}
6366
6367 ins_pipe(pipe_serial);
6368 %}
6369
6370 instruct get_and_addL(indirect mem, iRegLNoSp newval, iRegL incr)
6371 %{
6372 match(Set newval (GetAndAddL mem incr));
6373
6374 ins_cost(ALU_COST);
6375
6376 format %{ "get_and_addL $newval, [$mem], $incr\t#@get_and_addL" %}
6377
6378 ins_encode %{
6379 __ atomic_add($newval$$Register, $incr$$Register, as_Register($mem$$base));
6380 %}
6381
6382 ins_pipe(pipe_serial);
6383 %}
6384
6385 instruct get_and_addL_no_res(indirect mem, Universe dummy, iRegL incr)
6386 %{
6387 predicate(n->as_LoadStore()->result_not_used());
6388
6389 match(Set dummy (GetAndAddL mem incr));
6390
6391 ins_cost(ALU_COST);
6392
6393 format %{ "get_and_addL [$mem], $incr\t#@get_and_addL_no_res" %}
6394
6395 ins_encode %{
6396 __ atomic_add(noreg, $incr$$Register, as_Register($mem$$base));
6397 %}
6398
6399 ins_pipe(pipe_serial);
6400 %}
6401
6402 instruct get_and_addLi(indirect mem, iRegLNoSp newval, immLAdd incr)
6403 %{
6404 match(Set newval (GetAndAddL mem incr));
6405
6406 ins_cost(ALU_COST);
6407
6408 format %{ "get_and_addL $newval, [$mem], $incr\t#@get_and_addLi" %}
6409
6410 ins_encode %{
6411 __ atomic_add($newval$$Register, $incr$$constant, as_Register($mem$$base));
6412 %}
6413
6414 ins_pipe(pipe_serial);
6415 %}
6416
6417 instruct get_and_addLi_no_res(indirect mem, Universe dummy, immLAdd incr)
6418 %{
6419 predicate(n->as_LoadStore()->result_not_used());
6420
6421 match(Set dummy (GetAndAddL mem incr));
6422
6423 ins_cost(ALU_COST);
6424
6425 format %{ "get_and_addL [$mem], $incr\t#@get_and_addLi_no_res" %}
6426
6427 ins_encode %{
6428 __ atomic_add(noreg, $incr$$constant, as_Register($mem$$base));
6429 %}
6430
6431 ins_pipe(pipe_serial);
6432 %}
6433
6434 instruct get_and_addI(indirect mem, iRegINoSp newval, iRegIorL2I incr)
6435 %{
6436 match(Set newval (GetAndAddI mem incr));
6437
6438 ins_cost(ALU_COST);
6439
6440 format %{ "get_and_addI $newval, [$mem], $incr\t#@get_and_addI" %}
6441
6442 ins_encode %{
6443 __ atomic_addw($newval$$Register, $incr$$Register, as_Register($mem$$base));
6444 %}
6445
6446 ins_pipe(pipe_serial);
6447 %}
6448
6449 instruct get_and_addI_no_res(indirect mem, Universe dummy, iRegIorL2I incr)
6450 %{
6451 predicate(n->as_LoadStore()->result_not_used());
6452
6453 match(Set dummy (GetAndAddI mem incr));
6454
6455 ins_cost(ALU_COST);
6456
6457 format %{ "get_and_addI [$mem], $incr\t#@get_and_addI_no_res" %}
6458
6459 ins_encode %{
6460 __ atomic_addw(noreg, $incr$$Register, as_Register($mem$$base));
6461 %}
6462
6463 ins_pipe(pipe_serial);
6464 %}
6465
6466 instruct get_and_addIi(indirect mem, iRegINoSp newval, immIAdd incr)
6467 %{
6468 match(Set newval (GetAndAddI mem incr));
6469
6470 ins_cost(ALU_COST);
6471
6472 format %{ "get_and_addI $newval, [$mem], $incr\t#@get_and_addIi" %}
6473
6474 ins_encode %{
6475 __ atomic_addw($newval$$Register, $incr$$constant, as_Register($mem$$base));
6476 %}
6477
6478 ins_pipe(pipe_serial);
6479 %}
6480
6481 instruct get_and_addIi_no_res(indirect mem, Universe dummy, immIAdd incr)
6482 %{
6483 predicate(n->as_LoadStore()->result_not_used());
6484
6485 match(Set dummy (GetAndAddI mem incr));
6486
6487 ins_cost(ALU_COST);
6488
6489 format %{ "get_and_addI [$mem], $incr\t#@get_and_addIi_no_res" %}
6490
6491 ins_encode %{
6492 __ atomic_addw(noreg, $incr$$constant, as_Register($mem$$base));
6493 %}
6494
6495 ins_pipe(pipe_serial);
6496 %}
6497
6498 instruct get_and_addLAcq(indirect mem, iRegLNoSp newval, iRegL incr)
6499 %{
6500 predicate(needs_acquiring_load_reserved(n));
6501
6502 match(Set newval (GetAndAddL mem incr));
6503
6504 ins_cost(ALU_COST);
6505
6506 format %{ "get_and_addL_acq $newval, [$mem], $incr\t#@get_and_addLAcq" %}
6507
6508 ins_encode %{
6509 __ atomic_addal($newval$$Register, $incr$$Register, as_Register($mem$$base));
6510 %}
6511
6512 ins_pipe(pipe_serial);
6513 %}
6514
6515 instruct get_and_addL_no_resAcq(indirect mem, Universe dummy, iRegL incr) %{
6516 predicate(n->as_LoadStore()->result_not_used() && needs_acquiring_load_reserved(n));
6517
6518 match(Set dummy (GetAndAddL mem incr));
6519
6520 ins_cost(ALU_COST);
6521
6522 format %{ "get_and_addL_acq [$mem], $incr\t#@get_and_addL_no_resAcq" %}
6523
6524 ins_encode %{
6525 __ atomic_addal(noreg, $incr$$Register, as_Register($mem$$base));
6526 %}
6527
6528 ins_pipe(pipe_serial);
6529 %}
6530
6531 instruct get_and_addLiAcq(indirect mem, iRegLNoSp newval, immLAdd incr)
6532 %{
6533 predicate(needs_acquiring_load_reserved(n));
6534
6535 match(Set newval (GetAndAddL mem incr));
6536
6537 ins_cost(ALU_COST);
6538
6539 format %{ "get_and_addL_acq $newval, [$mem], $incr\t#@get_and_addLiAcq" %}
6540
6541 ins_encode %{
6542 __ atomic_addal($newval$$Register, $incr$$constant, as_Register($mem$$base));
6543 %}
6544
6545 ins_pipe(pipe_serial);
6546 %}
6547
6548 instruct get_and_addLi_no_resAcq(indirect mem, Universe dummy, immLAdd incr)
6549 %{
6550 predicate(n->as_LoadStore()->result_not_used() && needs_acquiring_load_reserved(n));
6551
6552 match(Set dummy (GetAndAddL mem incr));
6553
6554 ins_cost(ALU_COST);
6555
6556 format %{ "get_and_addL_acq [$mem], $incr\t#@get_and_addLi_no_resAcq" %}
6557
6558 ins_encode %{
6559 __ atomic_addal(noreg, $incr$$constant, as_Register($mem$$base));
6560 %}
6561
6562 ins_pipe(pipe_serial);
6563 %}
6564
6565 instruct get_and_addIAcq(indirect mem, iRegINoSp newval, iRegIorL2I incr)
6566 %{
6567 predicate(needs_acquiring_load_reserved(n));
6568
6569 match(Set newval (GetAndAddI mem incr));
6570
6571 ins_cost(ALU_COST);
6572
6573 format %{ "get_and_addI_acq $newval, [$mem], $incr\t#@get_and_addIAcq" %}
6574
6575 ins_encode %{
6576 __ atomic_addalw($newval$$Register, $incr$$Register, as_Register($mem$$base));
6577 %}
6578
6579 ins_pipe(pipe_serial);
6580 %}
6581
6582 instruct get_and_addI_no_resAcq(indirect mem, Universe dummy, iRegIorL2I incr)
6583 %{
6584 predicate(n->as_LoadStore()->result_not_used() && needs_acquiring_load_reserved(n));
6585
6586 match(Set dummy (GetAndAddI mem incr));
6587
6588 ins_cost(ALU_COST);
6589
6590 format %{ "get_and_addI_acq [$mem], $incr\t#@get_and_addI_no_resAcq" %}
6591
6592 ins_encode %{
6593 __ atomic_addalw(noreg, $incr$$Register, as_Register($mem$$base));
6594 %}
6595
6596 ins_pipe(pipe_serial);
6597 %}
6598
6599 instruct get_and_addIiAcq(indirect mem, iRegINoSp newval, immIAdd incr)
6600 %{
6601 predicate(needs_acquiring_load_reserved(n));
6602
6603 match(Set newval (GetAndAddI mem incr));
6604
6605 ins_cost(ALU_COST);
6606
6607 format %{ "get_and_addI_acq $newval, [$mem], $incr\t#@get_and_addIiAcq" %}
6608
6609 ins_encode %{
6610 __ atomic_addalw($newval$$Register, $incr$$constant, as_Register($mem$$base));
6611 %}
6612
6613 ins_pipe(pipe_serial);
6614 %}
6615
6616 instruct get_and_addIi_no_resAcq(indirect mem, Universe dummy, immIAdd incr)
6617 %{
6618 predicate(n->as_LoadStore()->result_not_used() && needs_acquiring_load_reserved(n));
6619
6620 match(Set dummy (GetAndAddI mem incr));
6621
6622 ins_cost(ALU_COST);
6623
6624 format %{ "get_and_addI_acq [$mem], $incr\t#@get_and_addIi_no_resAcq" %}
6625
6626 ins_encode %{
6627 __ atomic_addalw(noreg, $incr$$constant, as_Register($mem$$base));
6628 %}
6629
6630 ins_pipe(pipe_serial);
6631 %}
6632
6633 // ============================================================================
6634 // Arithmetic Instructions
6635 //
6636
6637 // Integer Addition
6638
6639 // TODO
6640 // these currently employ operations which do not set CR and hence are
6641 // not flagged as killing CR but we would like to isolate the cases
6642 // where we want to set flags from those where we don't. need to work
6643 // out how to do that.
6644 instruct addI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6645 match(Set dst (AddI src1 src2));
6646
6647 ins_cost(ALU_COST);
6648 format %{ "addw $dst, $src1, $src2\t#@addI_reg_reg" %}
6649
6650 ins_encode %{
6651 __ addw(as_Register($dst$$reg),
6652 as_Register($src1$$reg),
6653 as_Register($src2$$reg));
6654 %}
6655
6656 ins_pipe(ialu_reg_reg);
6657 %}
6658
6659 instruct addI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immIAdd src2) %{
6660 match(Set dst (AddI src1 src2));
6661
6662 ins_cost(ALU_COST);
6663 format %{ "addiw $dst, $src1, $src2\t#@addI_reg_imm" %}
6664
6665 ins_encode %{
6666 __ addiw(as_Register($dst$$reg),
6667 as_Register($src1$$reg),
6668 $src2$$constant);
6669 %}
6670
6671 ins_pipe(ialu_reg_imm);
6672 %}
6673
6674 instruct addI_reg_imm_l2i(iRegINoSp dst, iRegL src1, immIAdd src2) %{
6675 match(Set dst (AddI (ConvL2I src1) src2));
6676
6677 ins_cost(ALU_COST);
6678 format %{ "addiw $dst, $src1, $src2\t#@addI_reg_imm_l2i" %}
6679
6680 ins_encode %{
6681 __ addiw(as_Register($dst$$reg),
6682 as_Register($src1$$reg),
6683 $src2$$constant);
6684 %}
6685
6686 ins_pipe(ialu_reg_imm);
6687 %}
6688
6689 // Pointer Addition
6690 instruct addP_reg_reg(iRegPNoSp dst, iRegP src1, iRegL src2) %{
6691 match(Set dst (AddP src1 src2));
6692
6693 ins_cost(ALU_COST);
6694 format %{ "add $dst, $src1, $src2\t# ptr, #@addP_reg_reg" %}
6695
6696 ins_encode %{
6697 __ add(as_Register($dst$$reg),
6698 as_Register($src1$$reg),
6699 as_Register($src2$$reg));
6700 %}
6701
6702 ins_pipe(ialu_reg_reg);
6703 %}
6704
6705 // If we shift more than 32 bits, we need not convert I2L.
6706 instruct lShiftL_regI_immGE32(iRegLNoSp dst, iRegI src, uimmI6_ge32 scale) %{
6707 match(Set dst (LShiftL (ConvI2L src) scale));
6708 ins_cost(ALU_COST);
6709 format %{ "slli $dst, $src, $scale & 63\t#@lShiftL_regI_immGE32" %}
6710
6711 ins_encode %{
6712 __ slli(as_Register($dst$$reg), as_Register($src$$reg), $scale$$constant & 63);
6713 %}
6714
6715 ins_pipe(ialu_reg_shift);
6716 %}
6717
6718 // Pointer Immediate Addition
6719 // n.b. this needs to be more expensive than using an indirect memory
6720 // operand
6721 instruct addP_reg_imm(iRegPNoSp dst, iRegP src1, immLAdd src2) %{
6722 match(Set dst (AddP src1 src2));
6723 ins_cost(ALU_COST);
6724 format %{ "addi $dst, $src1, $src2\t# ptr, #@addP_reg_imm" %}
6725
6726 ins_encode %{
6727 __ addi(as_Register($dst$$reg),
6728 as_Register($src1$$reg),
6729 $src2$$constant);
6730 %}
6731
6732 ins_pipe(ialu_reg_imm);
6733 %}
6734
6735 // Long Addition
6736 instruct addL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
6737 match(Set dst (AddL src1 src2));
6738 ins_cost(ALU_COST);
6739 format %{ "add $dst, $src1, $src2\t#@addL_reg_reg" %}
6740
6741 ins_encode %{
6742 __ add(as_Register($dst$$reg),
6743 as_Register($src1$$reg),
6744 as_Register($src2$$reg));
6745 %}
6746
6747 ins_pipe(ialu_reg_reg);
6748 %}
6749
6750 // No constant pool entries requiredLong Immediate Addition.
6751 instruct addL_reg_imm(iRegLNoSp dst, iRegL src1, immLAdd src2) %{
6752 match(Set dst (AddL src1 src2));
6753 ins_cost(ALU_COST);
6754 format %{ "addi $dst, $src1, $src2\t#@addL_reg_imm" %}
6755
6756 ins_encode %{
6757 // src2 is imm, so actually call the addi
6758 __ addi(as_Register($dst$$reg),
6759 as_Register($src1$$reg),
6760 $src2$$constant);
6761 %}
6762
6763 ins_pipe(ialu_reg_imm);
6764 %}
6765
6766 // Integer Subtraction
6767 instruct subI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6768 match(Set dst (SubI src1 src2));
6769
6770 ins_cost(ALU_COST);
6771 format %{ "subw $dst, $src1, $src2\t#@subI_reg_reg" %}
6772
6773 ins_encode %{
6774 __ subw(as_Register($dst$$reg),
6775 as_Register($src1$$reg),
6776 as_Register($src2$$reg));
6777 %}
6778
6779 ins_pipe(ialu_reg_reg);
6780 %}
6781
6782 // Immediate Subtraction
6783 instruct subI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immISub src2) %{
6784 match(Set dst (SubI src1 src2));
6785
6786 ins_cost(ALU_COST);
6787 format %{ "addiw $dst, $src1, -$src2\t#@subI_reg_imm" %}
6788
6789 ins_encode %{
6790 // src2 is imm, so actually call the addiw
6791 __ subiw(as_Register($dst$$reg),
6792 as_Register($src1$$reg),
6793 $src2$$constant);
6794 %}
6795
6796 ins_pipe(ialu_reg_imm);
6797 %}
6798
6799 // Long Subtraction
6800 instruct subL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
6801 match(Set dst (SubL src1 src2));
6802 ins_cost(ALU_COST);
6803 format %{ "sub $dst, $src1, $src2\t#@subL_reg_reg" %}
6804
6805 ins_encode %{
6806 __ sub(as_Register($dst$$reg),
6807 as_Register($src1$$reg),
6808 as_Register($src2$$reg));
6809 %}
6810
6811 ins_pipe(ialu_reg_reg);
6812 %}
6813
6814 // No constant pool entries requiredLong Immediate Subtraction.
6815 instruct subL_reg_imm(iRegLNoSp dst, iRegL src1, immLSub src2) %{
6816 match(Set dst (SubL src1 src2));
6817 ins_cost(ALU_COST);
6818 format %{ "addi $dst, $src1, -$src2\t#@subL_reg_imm" %}
6819
6820 ins_encode %{
6821 // src2 is imm, so actually call the addi
6822 __ subi(as_Register($dst$$reg),
6823 as_Register($src1$$reg),
6824 $src2$$constant);
6825 %}
6826
6827 ins_pipe(ialu_reg_imm);
6828 %}
6829
6830 // Integer Negation (special case for sub)
6831
6832 instruct negI_reg(iRegINoSp dst, iRegIorL2I src, immI0 zero) %{
6833 match(Set dst (SubI zero src));
6834 ins_cost(ALU_COST);
6835 format %{ "subw $dst, x0, $src\t# int, #@negI_reg" %}
6836
6837 ins_encode %{
6838 // actually call the subw
6839 __ negw(as_Register($dst$$reg),
6840 as_Register($src$$reg));
6841 %}
6842
6843 ins_pipe(ialu_reg);
6844 %}
6845
6846 // Long Negation
6847
6848 instruct negL_reg(iRegLNoSp dst, iRegL src, immL0 zero) %{
6849 match(Set dst (SubL zero src));
6850 ins_cost(ALU_COST);
6851 format %{ "sub $dst, x0, $src\t# long, #@negL_reg" %}
6852
6853 ins_encode %{
6854 // actually call the sub
6855 __ neg(as_Register($dst$$reg),
6856 as_Register($src$$reg));
6857 %}
6858
6859 ins_pipe(ialu_reg);
6860 %}
6861
6862 // Integer Multiply
6863
6864 instruct mulI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6865 match(Set dst (MulI src1 src2));
6866 ins_cost(IMUL_COST);
6867 format %{ "mulw $dst, $src1, $src2\t#@mulI" %}
6868
6869 //this means 2 word multi, and no sign extend to 64 bits
6870 ins_encode %{
6871 // riscv64 mulw will sign-extension to high 32 bits in dst reg
6872 __ mulw(as_Register($dst$$reg),
6873 as_Register($src1$$reg),
6874 as_Register($src2$$reg));
6875 %}
6876
6877 ins_pipe(imul_reg_reg);
6878 %}
6879
6880 // Long Multiply
6881
6882 instruct mulL(iRegLNoSp dst, iRegL src1, iRegL src2) %{
6883 match(Set dst (MulL src1 src2));
6884 ins_cost(IMUL_COST);
6885 format %{ "mul $dst, $src1, $src2\t#@mulL" %}
6886
6887 ins_encode %{
6888 __ mul(as_Register($dst$$reg),
6889 as_Register($src1$$reg),
6890 as_Register($src2$$reg));
6891 %}
6892
6893 ins_pipe(lmul_reg_reg);
6894 %}
6895
6896 instruct mulHiL_rReg(iRegLNoSp dst, iRegL src1, iRegL src2)
6897 %{
6898 match(Set dst (MulHiL src1 src2));
6899 ins_cost(IMUL_COST);
6900 format %{ "mulh $dst, $src1, $src2\t# mulhi, #@mulHiL_rReg" %}
6901
6902 ins_encode %{
6903 __ mulh(as_Register($dst$$reg),
6904 as_Register($src1$$reg),
6905 as_Register($src2$$reg));
6906 %}
6907
6908 ins_pipe(lmul_reg_reg);
6909 %}
6910
6911 instruct umulHiL_rReg(iRegLNoSp dst, iRegL src1, iRegL src2)
6912 %{
6913 match(Set dst (UMulHiL src1 src2));
6914 ins_cost(IMUL_COST);
6915 format %{ "mulhu $dst, $src1, $src2\t# umulhi, #@umulHiL_rReg" %}
6916
6917 ins_encode %{
6918 __ mulhu(as_Register($dst$$reg),
6919 as_Register($src1$$reg),
6920 as_Register($src2$$reg));
6921 %}
6922
6923 ins_pipe(lmul_reg_reg);
6924 %}
6925
6926 // Integer Divide
6927
6928 instruct divI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6929 match(Set dst (DivI src1 src2));
6930 ins_cost(IDIVSI_COST);
6931 format %{ "divw $dst, $src1, $src2\t#@divI"%}
6932
6933 ins_encode %{
6934 __ divw(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg));
6935 %}
6936 ins_pipe(idiv_reg_reg);
6937 %}
6938
6939 instruct UdivI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6940 match(Set dst (UDivI src1 src2));
6941 ins_cost(IDIVSI_COST);
6942 format %{ "divuw $dst, $src1, $src2\t#@UdivI"%}
6943
6944 ins_encode %{
6945 __ divuw(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg));
6946 %}
6947 ins_pipe(idiv_reg_reg);
6948 %}
6949
6950 instruct signExtract(iRegINoSp dst, iRegIorL2I src1, immI_31 div1, immI_31 div2) %{
6951 match(Set dst (URShiftI (RShiftI src1 div1) div2));
6952 ins_cost(ALU_COST);
6953 format %{ "srliw $dst, $src1, $div1\t# int signExtract, #@signExtract" %}
6954
6955 ins_encode %{
6956 __ srliw(as_Register($dst$$reg), as_Register($src1$$reg), 31);
6957 %}
6958 ins_pipe(ialu_reg_shift);
6959 %}
6960
6961 // Long Divide
6962
6963 instruct divL(iRegLNoSp dst, iRegL src1, iRegL src2) %{
6964 match(Set dst (DivL src1 src2));
6965 ins_cost(IDIVDI_COST);
6966 format %{ "div $dst, $src1, $src2\t#@divL" %}
6967
6968 ins_encode %{
6969 __ div(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg));
6970 %}
6971 ins_pipe(ldiv_reg_reg);
6972 %}
6973
6974 instruct UdivL(iRegLNoSp dst, iRegL src1, iRegL src2) %{
6975 match(Set dst (UDivL src1 src2));
6976 ins_cost(IDIVDI_COST);
6977
6978 format %{ "divu $dst, $src1, $src2\t#@UdivL" %}
6979
6980 ins_encode %{
6981 __ divu(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg));
6982 %}
6983 ins_pipe(ldiv_reg_reg);
6984 %}
6985
6986 instruct signExtractL(iRegLNoSp dst, iRegL src1, immI_63 div1, immI_63 div2) %{
6987 match(Set dst (URShiftL (RShiftL src1 div1) div2));
6988 ins_cost(ALU_COST);
6989 format %{ "srli $dst, $src1, $div1\t# long signExtract, #@signExtractL" %}
6990
6991 ins_encode %{
6992 __ srli(as_Register($dst$$reg), as_Register($src1$$reg), 63);
6993 %}
6994 ins_pipe(ialu_reg_shift);
6995 %}
6996
6997 // Integer Remainder
6998
6999 instruct modI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
7000 match(Set dst (ModI src1 src2));
7001 ins_cost(IDIVSI_COST);
7002 format %{ "remw $dst, $src1, $src2\t#@modI" %}
7003
7004 ins_encode %{
7005 __ remw(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg));
7006 %}
7007 ins_pipe(ialu_reg_reg);
7008 %}
7009
7010 instruct UmodI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
7011 match(Set dst (UModI src1 src2));
7012 ins_cost(IDIVSI_COST);
7013 format %{ "remuw $dst, $src1, $src2\t#@UmodI" %}
7014
7015 ins_encode %{
7016 __ remuw(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg));
7017 %}
7018 ins_pipe(ialu_reg_reg);
7019 %}
7020
7021 // Long Remainder
7022
7023 instruct modL(iRegLNoSp dst, iRegL src1, iRegL src2) %{
7024 match(Set dst (ModL src1 src2));
7025 ins_cost(IDIVDI_COST);
7026 format %{ "rem $dst, $src1, $src2\t#@modL" %}
7027
7028 ins_encode %{
7029 __ rem(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg));
7030 %}
7031 ins_pipe(ialu_reg_reg);
7032 %}
7033
7034 instruct UmodL(iRegLNoSp dst, iRegL src1, iRegL src2) %{
7035 match(Set dst (UModL src1 src2));
7036 ins_cost(IDIVDI_COST);
7037 format %{ "remu $dst, $src1, $src2\t#@UmodL" %}
7038
7039 ins_encode %{
7040 __ remu(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg));
7041 %}
7042 ins_pipe(ialu_reg_reg);
7043 %}
7044
7045 // Integer Shifts
7046
7047 // Shift Left Register
7048 // Only the low 5 bits of src2 are considered for the shift amount, all other bits are ignored.
7049 instruct lShiftI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
7050 match(Set dst (LShiftI src1 src2));
7051 ins_cost(ALU_COST);
7052 format %{ "sllw $dst, $src1, $src2\t#@lShiftI_reg_reg" %}
7053
7054 ins_encode %{
7055 __ sllw(as_Register($dst$$reg),
7056 as_Register($src1$$reg),
7057 as_Register($src2$$reg));
7058 %}
7059
7060 ins_pipe(ialu_reg_reg_vshift);
7061 %}
7062
7063 // Shift Left Immediate
7064 instruct lShiftI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immI src2) %{
7065 match(Set dst (LShiftI src1 src2));
7066 ins_cost(ALU_COST);
7067 format %{ "slliw $dst, $src1, ($src2 & 0x1f)\t#@lShiftI_reg_imm" %}
7068
7069 ins_encode %{
7070 // the shift amount is encoded in the lower
7071 // 5 bits of the I-immediate field for RV32I
7072 __ slliw(as_Register($dst$$reg),
7073 as_Register($src1$$reg),
7074 (unsigned) $src2$$constant & 0x1f);
7075 %}
7076
7077 ins_pipe(ialu_reg_shift);
7078 %}
7079
7080 // Shift Right Logical Register
7081 // Only the low 5 bits of src2 are considered for the shift amount, all other bits are ignored.
7082 instruct urShiftI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
7083 match(Set dst (URShiftI src1 src2));
7084 ins_cost(ALU_COST);
7085 format %{ "srlw $dst, $src1, $src2\t#@urShiftI_reg_reg" %}
7086
7087 ins_encode %{
7088 __ srlw(as_Register($dst$$reg),
7089 as_Register($src1$$reg),
7090 as_Register($src2$$reg));
7091 %}
7092
7093 ins_pipe(ialu_reg_reg_vshift);
7094 %}
7095
7096 // Shift Right Logical Immediate
7097 instruct urShiftI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immI src2) %{
7098 match(Set dst (URShiftI src1 src2));
7099 ins_cost(ALU_COST);
7100 format %{ "srliw $dst, $src1, ($src2 & 0x1f)\t#@urShiftI_reg_imm" %}
7101
7102 ins_encode %{
7103 // the shift amount is encoded in the lower
7104 // 6 bits of the I-immediate field for RV64I
7105 __ srliw(as_Register($dst$$reg),
7106 as_Register($src1$$reg),
7107 (unsigned) $src2$$constant & 0x1f);
7108 %}
7109
7110 ins_pipe(ialu_reg_shift);
7111 %}
7112
7113 // Shift Right Arithmetic Register
7114 // Only the low 5 bits of src2 are considered for the shift amount, all other bits are ignored.
7115 instruct rShiftI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
7116 match(Set dst (RShiftI src1 src2));
7117 ins_cost(ALU_COST);
7118 format %{ "sraw $dst, $src1, $src2\t#@rShiftI_reg_reg" %}
7119
7120 ins_encode %{
7121 // riscv will sign-ext dst high 32 bits
7122 __ sraw(as_Register($dst$$reg),
7123 as_Register($src1$$reg),
7124 as_Register($src2$$reg));
7125 %}
7126
7127 ins_pipe(ialu_reg_reg_vshift);
7128 %}
7129
7130 // Shift Right Arithmetic Immediate
7131 instruct rShiftI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immI src2) %{
7132 match(Set dst (RShiftI src1 src2));
7133 ins_cost(ALU_COST);
7134 format %{ "sraiw $dst, $src1, ($src2 & 0x1f)\t#@rShiftI_reg_imm" %}
7135
7136 ins_encode %{
7137 // riscv will sign-ext dst high 32 bits
7138 __ sraiw(as_Register($dst$$reg),
7139 as_Register($src1$$reg),
7140 (unsigned) $src2$$constant & 0x1f);
7141 %}
7142
7143 ins_pipe(ialu_reg_shift);
7144 %}
7145
7146 // Long Shifts
7147
7148 // Shift Left Register
7149 // Only the low 6 bits of src2 are considered for the shift amount, all other bits are ignored.
7150 instruct lShiftL_reg_reg(iRegLNoSp dst, iRegL src1, iRegIorL2I src2) %{
7151 match(Set dst (LShiftL src1 src2));
7152
7153 ins_cost(ALU_COST);
7154 format %{ "sll $dst, $src1, $src2\t#@lShiftL_reg_reg" %}
7155
7156 ins_encode %{
7157 __ sll(as_Register($dst$$reg),
7158 as_Register($src1$$reg),
7159 as_Register($src2$$reg));
7160 %}
7161
7162 ins_pipe(ialu_reg_reg_vshift);
7163 %}
7164
7165 // Shift Left Immediate
7166 instruct lShiftL_reg_imm(iRegLNoSp dst, iRegL src1, immI src2) %{
7167 match(Set dst (LShiftL src1 src2));
7168
7169 ins_cost(ALU_COST);
7170 format %{ "slli $dst, $src1, ($src2 & 0x3f)\t#@lShiftL_reg_imm" %}
7171
7172 ins_encode %{
7173 // the shift amount is encoded in the lower
7174 // 6 bits of the I-immediate field for RV64I
7175 __ slli(as_Register($dst$$reg),
7176 as_Register($src1$$reg),
7177 (unsigned) $src2$$constant & 0x3f);
7178 %}
7179
7180 ins_pipe(ialu_reg_shift);
7181 %}
7182
7183 // Shift Right Logical Register
7184 // Only the low 6 bits of src2 are considered for the shift amount, all other bits are ignored.
7185 instruct urShiftL_reg_reg(iRegLNoSp dst, iRegL src1, iRegIorL2I src2) %{
7186 match(Set dst (URShiftL src1 src2));
7187
7188 ins_cost(ALU_COST);
7189 format %{ "srl $dst, $src1, $src2\t#@urShiftL_reg_reg" %}
7190
7191 ins_encode %{
7192 __ srl(as_Register($dst$$reg),
7193 as_Register($src1$$reg),
7194 as_Register($src2$$reg));
7195 %}
7196
7197 ins_pipe(ialu_reg_reg_vshift);
7198 %}
7199
7200 // Shift Right Logical Immediate
7201 instruct urShiftL_reg_imm(iRegLNoSp dst, iRegL src1, immI src2) %{
7202 match(Set dst (URShiftL src1 src2));
7203
7204 ins_cost(ALU_COST);
7205 format %{ "srli $dst, $src1, ($src2 & 0x3f)\t#@urShiftL_reg_imm" %}
7206
7207 ins_encode %{
7208 // the shift amount is encoded in the lower
7209 // 6 bits of the I-immediate field for RV64I
7210 __ srli(as_Register($dst$$reg),
7211 as_Register($src1$$reg),
7212 (unsigned) $src2$$constant & 0x3f);
7213 %}
7214
7215 ins_pipe(ialu_reg_shift);
7216 %}
7217
7218 // A special-case pattern for card table stores.
7219 instruct urShiftP_reg_imm(iRegLNoSp dst, iRegP src1, immI src2) %{
7220 match(Set dst (URShiftL (CastP2X src1) src2));
7221
7222 ins_cost(ALU_COST);
7223 format %{ "srli $dst, p2x($src1), ($src2 & 0x3f)\t#@urShiftP_reg_imm" %}
7224
7225 ins_encode %{
7226 // the shift amount is encoded in the lower
7227 // 6 bits of the I-immediate field for RV64I
7228 __ srli(as_Register($dst$$reg),
7229 as_Register($src1$$reg),
7230 (unsigned) $src2$$constant & 0x3f);
7231 %}
7232
7233 ins_pipe(ialu_reg_shift);
7234 %}
7235
7236 // Shift Right Arithmetic Register
7237 // Only the low 6 bits of src2 are considered for the shift amount, all other bits are ignored.
7238 instruct rShiftL_reg_reg(iRegLNoSp dst, iRegL src1, iRegIorL2I src2) %{
7239 match(Set dst (RShiftL src1 src2));
7240
7241 ins_cost(ALU_COST);
7242 format %{ "sra $dst, $src1, $src2\t#@rShiftL_reg_reg" %}
7243
7244 ins_encode %{
7245 __ sra(as_Register($dst$$reg),
7246 as_Register($src1$$reg),
7247 as_Register($src2$$reg));
7248 %}
7249
7250 ins_pipe(ialu_reg_reg_vshift);
7251 %}
7252
7253 // Shift Right Arithmetic Immediate
7254 instruct rShiftL_reg_imm(iRegLNoSp dst, iRegL src1, immI src2) %{
7255 match(Set dst (RShiftL src1 src2));
7256
7257 ins_cost(ALU_COST);
7258 format %{ "srai $dst, $src1, ($src2 & 0x3f)\t#@rShiftL_reg_imm" %}
7259
7260 ins_encode %{
7261 // the shift amount is encoded in the lower
7262 // 6 bits of the I-immediate field for RV64I
7263 __ srai(as_Register($dst$$reg),
7264 as_Register($src1$$reg),
7265 (unsigned) $src2$$constant & 0x3f);
7266 %}
7267
7268 ins_pipe(ialu_reg_shift);
7269 %}
7270
7271 instruct regI_not_reg(iRegINoSp dst, iRegI src1, immI_M1 m1) %{
7272 match(Set dst (XorI src1 m1));
7273 ins_cost(ALU_COST);
7274 format %{ "xori $dst, $src1, -1\t#@regI_not_reg" %}
7275
7276 ins_encode %{
7277 __ xori(as_Register($dst$$reg), as_Register($src1$$reg), -1);
7278 %}
7279
7280 ins_pipe(ialu_reg_imm);
7281 %}
7282
7283 instruct regL_not_reg(iRegLNoSp dst, iRegL src1, immL_M1 m1) %{
7284 match(Set dst (XorL src1 m1));
7285 ins_cost(ALU_COST);
7286 format %{ "xori $dst, $src1, -1\t#@regL_not_reg" %}
7287
7288 ins_encode %{
7289 __ xori(as_Register($dst$$reg), as_Register($src1$$reg), -1);
7290 %}
7291
7292 ins_pipe(ialu_reg_imm);
7293 %}
7294
7295
7296 // ============================================================================
7297 // Floating Point Arithmetic Instructions
7298
7299 instruct addF_reg_reg(fRegF dst, fRegF src1, fRegF src2) %{
7300 match(Set dst (AddF src1 src2));
7301
7302 ins_cost(DEFAULT_COST * 5);
7303 format %{ "fadd.s $dst, $src1, $src2\t#@addF_reg_reg" %}
7304
7305 ins_encode %{
7306 __ fadd_s(as_FloatRegister($dst$$reg),
7307 as_FloatRegister($src1$$reg),
7308 as_FloatRegister($src2$$reg));
7309 %}
7310
7311 ins_pipe(fp_dop_reg_reg_s);
7312 %}
7313
7314 instruct addD_reg_reg(fRegD dst, fRegD src1, fRegD src2) %{
7315 match(Set dst (AddD src1 src2));
7316
7317 ins_cost(DEFAULT_COST * 5);
7318 format %{ "fadd.d $dst, $src1, $src2\t#@addD_reg_reg" %}
7319
7320 ins_encode %{
7321 __ fadd_d(as_FloatRegister($dst$$reg),
7322 as_FloatRegister($src1$$reg),
7323 as_FloatRegister($src2$$reg));
7324 %}
7325
7326 ins_pipe(fp_dop_reg_reg_d);
7327 %}
7328
7329 instruct subF_reg_reg(fRegF dst, fRegF src1, fRegF src2) %{
7330 match(Set dst (SubF src1 src2));
7331
7332 ins_cost(DEFAULT_COST * 5);
7333 format %{ "fsub.s $dst, $src1, $src2\t#@subF_reg_reg" %}
7334
7335 ins_encode %{
7336 __ fsub_s(as_FloatRegister($dst$$reg),
7337 as_FloatRegister($src1$$reg),
7338 as_FloatRegister($src2$$reg));
7339 %}
7340
7341 ins_pipe(fp_dop_reg_reg_s);
7342 %}
7343
7344 instruct subD_reg_reg(fRegD dst, fRegD src1, fRegD src2) %{
7345 match(Set dst (SubD src1 src2));
7346
7347 ins_cost(DEFAULT_COST * 5);
7348 format %{ "fsub.d $dst, $src1, $src2\t#@subD_reg_reg" %}
7349
7350 ins_encode %{
7351 __ fsub_d(as_FloatRegister($dst$$reg),
7352 as_FloatRegister($src1$$reg),
7353 as_FloatRegister($src2$$reg));
7354 %}
7355
7356 ins_pipe(fp_dop_reg_reg_d);
7357 %}
7358
7359 instruct mulF_reg_reg(fRegF dst, fRegF src1, fRegF src2) %{
7360 match(Set dst (MulF src1 src2));
7361
7362 ins_cost(FMUL_SINGLE_COST);
7363 format %{ "fmul.s $dst, $src1, $src2\t#@mulF_reg_reg" %}
7364
7365 ins_encode %{
7366 __ fmul_s(as_FloatRegister($dst$$reg),
7367 as_FloatRegister($src1$$reg),
7368 as_FloatRegister($src2$$reg));
7369 %}
7370
7371 ins_pipe(fp_dop_reg_reg_s);
7372 %}
7373
7374 instruct mulD_reg_reg(fRegD dst, fRegD src1, fRegD src2) %{
7375 match(Set dst (MulD src1 src2));
7376
7377 ins_cost(FMUL_DOUBLE_COST);
7378 format %{ "fmul.d $dst, $src1, $src2\t#@mulD_reg_reg" %}
7379
7380 ins_encode %{
7381 __ fmul_d(as_FloatRegister($dst$$reg),
7382 as_FloatRegister($src1$$reg),
7383 as_FloatRegister($src2$$reg));
7384 %}
7385
7386 ins_pipe(fp_dop_reg_reg_d);
7387 %}
7388
7389 // src1 * src2 + src3
7390 instruct maddF_reg_reg(fRegF dst, fRegF src1, fRegF src2, fRegF src3) %{
7391 match(Set dst (FmaF src3 (Binary src1 src2)));
7392
7393 ins_cost(FMUL_SINGLE_COST);
7394 format %{ "fmadd.s $dst, $src1, $src2, $src3\t#@maddF_reg_reg" %}
7395
7396 ins_encode %{
7397 assert(UseFMA, "Needs FMA instructions support.");
7398 __ fmadd_s(as_FloatRegister($dst$$reg),
7399 as_FloatRegister($src1$$reg),
7400 as_FloatRegister($src2$$reg),
7401 as_FloatRegister($src3$$reg));
7402 %}
7403
7404 ins_pipe(pipe_class_default);
7405 %}
7406
7407 // src1 * src2 + src3
7408 instruct maddD_reg_reg(fRegD dst, fRegD src1, fRegD src2, fRegD src3) %{
7409 match(Set dst (FmaD src3 (Binary src1 src2)));
7410
7411 ins_cost(FMUL_DOUBLE_COST);
7412 format %{ "fmadd.d $dst, $src1, $src2, $src3\t#@maddD_reg_reg" %}
7413
7414 ins_encode %{
7415 assert(UseFMA, "Needs FMA instructions support.");
7416 __ fmadd_d(as_FloatRegister($dst$$reg),
7417 as_FloatRegister($src1$$reg),
7418 as_FloatRegister($src2$$reg),
7419 as_FloatRegister($src3$$reg));
7420 %}
7421
7422 ins_pipe(pipe_class_default);
7423 %}
7424
7425 // src1 * src2 - src3
7426 instruct msubF_reg_reg(fRegF dst, fRegF src1, fRegF src2, fRegF src3) %{
7427 match(Set dst (FmaF (NegF src3) (Binary src1 src2)));
7428
7429 ins_cost(FMUL_SINGLE_COST);
7430 format %{ "fmsub.s $dst, $src1, $src2, $src3\t#@msubF_reg_reg" %}
7431
7432 ins_encode %{
7433 assert(UseFMA, "Needs FMA instructions support.");
7434 __ fmsub_s(as_FloatRegister($dst$$reg),
7435 as_FloatRegister($src1$$reg),
7436 as_FloatRegister($src2$$reg),
7437 as_FloatRegister($src3$$reg));
7438 %}
7439
7440 ins_pipe(pipe_class_default);
7441 %}
7442
7443 // src1 * src2 - src3
7444 instruct msubD_reg_reg(fRegD dst, fRegD src1, fRegD src2, fRegD src3) %{
7445 match(Set dst (FmaD (NegD src3) (Binary src1 src2)));
7446
7447 ins_cost(FMUL_DOUBLE_COST);
7448 format %{ "fmsub.d $dst, $src1, $src2, $src3\t#@msubD_reg_reg" %}
7449
7450 ins_encode %{
7451 assert(UseFMA, "Needs FMA instructions support.");
7452 __ fmsub_d(as_FloatRegister($dst$$reg),
7453 as_FloatRegister($src1$$reg),
7454 as_FloatRegister($src2$$reg),
7455 as_FloatRegister($src3$$reg));
7456 %}
7457
7458 ins_pipe(pipe_class_default);
7459 %}
7460
7461 // src1 * (-src2) + src3
7462 // "(-src1) * src2 + src3" has been idealized to "src2 * (-src1) + src3"
7463 instruct nmsubF_reg_reg(fRegF dst, fRegF src1, fRegF src2, fRegF src3) %{
7464 match(Set dst (FmaF src3 (Binary src1 (NegF src2))));
7465
7466 ins_cost(FMUL_SINGLE_COST);
7467 format %{ "fnmsub.s $dst, $src1, $src2, $src3\t#@nmsubF_reg_reg" %}
7468
7469 ins_encode %{
7470 assert(UseFMA, "Needs FMA instructions support.");
7471 __ fnmsub_s(as_FloatRegister($dst$$reg),
7472 as_FloatRegister($src1$$reg),
7473 as_FloatRegister($src2$$reg),
7474 as_FloatRegister($src3$$reg));
7475 %}
7476
7477 ins_pipe(pipe_class_default);
7478 %}
7479
7480 // src1 * (-src2) + src3
7481 // "(-src1) * src2 + src3" has been idealized to "src2 * (-src1) + src3"
7482 instruct nmsubD_reg_reg(fRegD dst, fRegD src1, fRegD src2, fRegD src3) %{
7483 match(Set dst (FmaD src3 (Binary src1 (NegD src2))));
7484
7485 ins_cost(FMUL_DOUBLE_COST);
7486 format %{ "fnmsub.d $dst, $src1, $src2, $src3\t#@nmsubD_reg_reg" %}
7487
7488 ins_encode %{
7489 assert(UseFMA, "Needs FMA instructions support.");
7490 __ fnmsub_d(as_FloatRegister($dst$$reg),
7491 as_FloatRegister($src1$$reg),
7492 as_FloatRegister($src2$$reg),
7493 as_FloatRegister($src3$$reg));
7494 %}
7495
7496 ins_pipe(pipe_class_default);
7497 %}
7498
7499 // src1 * (-src2) - src3
7500 // "(-src1) * src2 - src3" has been idealized to "src2 * (-src1) - src3"
7501 instruct nmaddF_reg_reg(fRegF dst, fRegF src1, fRegF src2, fRegF src3) %{
7502 match(Set dst (FmaF (NegF src3) (Binary src1 (NegF src2))));
7503
7504 ins_cost(FMUL_SINGLE_COST);
7505 format %{ "fnmadd.s $dst, $src1, $src2, $src3\t#@nmaddF_reg_reg" %}
7506
7507 ins_encode %{
7508 assert(UseFMA, "Needs FMA instructions support.");
7509 __ fnmadd_s(as_FloatRegister($dst$$reg),
7510 as_FloatRegister($src1$$reg),
7511 as_FloatRegister($src2$$reg),
7512 as_FloatRegister($src3$$reg));
7513 %}
7514
7515 ins_pipe(pipe_class_default);
7516 %}
7517
7518 // src1 * (-src2) - src3
7519 // "(-src1) * src2 - src3" has been idealized to "src2 * (-src1) - src3"
7520 instruct nmaddD_reg_reg(fRegD dst, fRegD src1, fRegD src2, fRegD src3) %{
7521 match(Set dst (FmaD (NegD src3) (Binary src1 (NegD src2))));
7522
7523 ins_cost(FMUL_DOUBLE_COST);
7524 format %{ "fnmadd.d $dst, $src1, $src2, $src3\t#@nmaddD_reg_reg" %}
7525
7526 ins_encode %{
7527 assert(UseFMA, "Needs FMA instructions support.");
7528 __ fnmadd_d(as_FloatRegister($dst$$reg),
7529 as_FloatRegister($src1$$reg),
7530 as_FloatRegister($src2$$reg),
7531 as_FloatRegister($src3$$reg));
7532 %}
7533
7534 ins_pipe(pipe_class_default);
7535 %}
7536
7537 // Math.max(FF)F
7538 instruct maxF_reg_reg(fRegF dst, fRegF src1, fRegF src2, rFlagsReg cr) %{
7539 predicate(!UseZfa);
7540 match(Set dst (MaxF src1 src2));
7541 effect(KILL cr);
7542
7543 format %{ "maxF $dst, $src1, $src2" %}
7544
7545 ins_encode %{
7546 __ minmax_fp(as_FloatRegister($dst$$reg),
7547 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg),
7548 __ FLOAT_TYPE::single_precision, false /* is_min */);
7549 %}
7550
7551 ins_pipe(pipe_class_default);
7552 %}
7553
7554 instruct maxF_reg_reg_zfa(fRegF dst, fRegF src1, fRegF src2) %{
7555 predicate(UseZfa);
7556 match(Set dst (MaxF src1 src2));
7557
7558 format %{ "maxF $dst, $src1, $src2" %}
7559
7560 ins_encode %{
7561 __ fmaxm_s(as_FloatRegister($dst$$reg),
7562 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
7563 %}
7564
7565 ins_pipe(pipe_class_default);
7566 %}
7567
7568 // Math.min(FF)F
7569 instruct minF_reg_reg(fRegF dst, fRegF src1, fRegF src2, rFlagsReg cr) %{
7570 predicate(!UseZfa);
7571 match(Set dst (MinF src1 src2));
7572 effect(KILL cr);
7573
7574 format %{ "minF $dst, $src1, $src2" %}
7575
7576 ins_encode %{
7577 __ minmax_fp(as_FloatRegister($dst$$reg),
7578 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg),
7579 __ FLOAT_TYPE::single_precision, true /* is_min */);
7580 %}
7581
7582 ins_pipe(pipe_class_default);
7583 %}
7584
7585 instruct minF_reg_reg_zfa(fRegF dst, fRegF src1, fRegF src2) %{
7586 predicate(UseZfa);
7587 match(Set dst (MinF src1 src2));
7588
7589 format %{ "minF $dst, $src1, $src2" %}
7590
7591 ins_encode %{
7592 __ fminm_s(as_FloatRegister($dst$$reg),
7593 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
7594 %}
7595
7596 ins_pipe(pipe_class_default);
7597 %}
7598
7599 // Math.max(DD)D
7600 instruct maxD_reg_reg(fRegD dst, fRegD src1, fRegD src2, rFlagsReg cr) %{
7601 predicate(!UseZfa);
7602 match(Set dst (MaxD src1 src2));
7603 effect(KILL cr);
7604
7605 format %{ "maxD $dst, $src1, $src2" %}
7606
7607 ins_encode %{
7608 __ minmax_fp(as_FloatRegister($dst$$reg),
7609 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg),
7610 __ FLOAT_TYPE::double_precision, false /* is_min */);
7611 %}
7612
7613 ins_pipe(pipe_class_default);
7614 %}
7615
7616 instruct maxD_reg_reg_zfa(fRegD dst, fRegD src1, fRegD src2) %{
7617 predicate(UseZfa);
7618 match(Set dst (MaxD src1 src2));
7619
7620 format %{ "maxD $dst, $src1, $src2" %}
7621
7622 ins_encode %{
7623 __ fmaxm_d(as_FloatRegister($dst$$reg),
7624 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
7625 %}
7626
7627 ins_pipe(pipe_class_default);
7628 %}
7629
7630 // Math.min(DD)D
7631 instruct minD_reg_reg(fRegD dst, fRegD src1, fRegD src2, rFlagsReg cr) %{
7632 predicate(!UseZfa);
7633 match(Set dst (MinD src1 src2));
7634 effect(KILL cr);
7635
7636 format %{ "minD $dst, $src1, $src2" %}
7637
7638 ins_encode %{
7639 __ minmax_fp(as_FloatRegister($dst$$reg),
7640 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg),
7641 __ FLOAT_TYPE::double_precision, true /* is_min */);
7642 %}
7643
7644 ins_pipe(pipe_class_default);
7645 %}
7646
7647 instruct minD_reg_reg_zfa(fRegD dst, fRegD src1, fRegD src2) %{
7648 predicate(UseZfa);
7649 match(Set dst (MinD src1 src2));
7650
7651 format %{ "minD $dst, $src1, $src2" %}
7652
7653 ins_encode %{
7654 __ fminm_d(as_FloatRegister($dst$$reg),
7655 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
7656 %}
7657
7658 ins_pipe(pipe_class_default);
7659 %}
7660
7661 // Float.isInfinite
7662 instruct isInfiniteF_reg_reg(iRegINoSp dst, fRegF src)
7663 %{
7664 match(Set dst (IsInfiniteF src));
7665
7666 format %{ "isInfinite $dst, $src" %}
7667 ins_encode %{
7668 __ fclass_s(as_Register($dst$$reg), as_FloatRegister($src$$reg));
7669 __ andi(as_Register($dst$$reg), as_Register($dst$$reg), Assembler::FClassBits::inf);
7670 __ slt(as_Register($dst$$reg), zr, as_Register($dst$$reg));
7671 %}
7672
7673 ins_pipe(pipe_class_default);
7674 %}
7675
7676 // Double.isInfinite
7677 instruct isInfiniteD_reg_reg(iRegINoSp dst, fRegD src)
7678 %{
7679 match(Set dst (IsInfiniteD src));
7680
7681 format %{ "isInfinite $dst, $src" %}
7682 ins_encode %{
7683 __ fclass_d(as_Register($dst$$reg), as_FloatRegister($src$$reg));
7684 __ andi(as_Register($dst$$reg), as_Register($dst$$reg), Assembler::FClassBits::inf);
7685 __ slt(as_Register($dst$$reg), zr, as_Register($dst$$reg));
7686 %}
7687
7688 ins_pipe(pipe_class_default);
7689 %}
7690
7691 // Float.isFinite
7692 instruct isFiniteF_reg_reg(iRegINoSp dst, fRegF src)
7693 %{
7694 match(Set dst (IsFiniteF src));
7695
7696 format %{ "isFinite $dst, $src" %}
7697 ins_encode %{
7698 __ fclass_s(as_Register($dst$$reg), as_FloatRegister($src$$reg));
7699 __ andi(as_Register($dst$$reg), as_Register($dst$$reg), Assembler::FClassBits::finite);
7700 __ slt(as_Register($dst$$reg), zr, as_Register($dst$$reg));
7701 %}
7702
7703 ins_pipe(pipe_class_default);
7704 %}
7705
7706 // Double.isFinite
7707 instruct isFiniteD_reg_reg(iRegINoSp dst, fRegD src)
7708 %{
7709 match(Set dst (IsFiniteD src));
7710
7711 format %{ "isFinite $dst, $src" %}
7712 ins_encode %{
7713 __ fclass_d(as_Register($dst$$reg), as_FloatRegister($src$$reg));
7714 __ andi(as_Register($dst$$reg), as_Register($dst$$reg), Assembler::FClassBits::finite);
7715 __ slt(as_Register($dst$$reg), zr, as_Register($dst$$reg));
7716 %}
7717
7718 ins_pipe(pipe_class_default);
7719 %}
7720
7721 instruct divF_reg_reg(fRegF dst, fRegF src1, fRegF src2) %{
7722 match(Set dst (DivF src1 src2));
7723
7724 ins_cost(FDIV_COST);
7725 format %{ "fdiv.s $dst, $src1, $src2\t#@divF_reg_reg" %}
7726
7727 ins_encode %{
7728 __ fdiv_s(as_FloatRegister($dst$$reg),
7729 as_FloatRegister($src1$$reg),
7730 as_FloatRegister($src2$$reg));
7731 %}
7732
7733 ins_pipe(fp_div_s);
7734 %}
7735
7736 instruct divD_reg_reg(fRegD dst, fRegD src1, fRegD src2) %{
7737 match(Set dst (DivD src1 src2));
7738
7739 ins_cost(FDIV_COST);
7740 format %{ "fdiv.d $dst, $src1, $src2\t#@divD_reg_reg" %}
7741
7742 ins_encode %{
7743 __ fdiv_d(as_FloatRegister($dst$$reg),
7744 as_FloatRegister($src1$$reg),
7745 as_FloatRegister($src2$$reg));
7746 %}
7747
7748 ins_pipe(fp_div_d);
7749 %}
7750
7751 instruct negF_reg_reg(fRegF dst, fRegF src) %{
7752 match(Set dst (NegF src));
7753
7754 ins_cost(XFER_COST);
7755 format %{ "fsgnjn.s $dst, $src, $src\t#@negF_reg_reg" %}
7756
7757 ins_encode %{
7758 __ fneg_s(as_FloatRegister($dst$$reg),
7759 as_FloatRegister($src$$reg));
7760 %}
7761
7762 ins_pipe(fp_uop_s);
7763 %}
7764
7765 instruct negD_reg_reg(fRegD dst, fRegD src) %{
7766 match(Set dst (NegD src));
7767
7768 ins_cost(XFER_COST);
7769 format %{ "fsgnjn.d $dst, $src, $src\t#@negD_reg_reg" %}
7770
7771 ins_encode %{
7772 __ fneg_d(as_FloatRegister($dst$$reg),
7773 as_FloatRegister($src$$reg));
7774 %}
7775
7776 ins_pipe(fp_uop_d);
7777 %}
7778
7779 instruct absI_reg(iRegINoSp dst, iRegIorL2I src) %{
7780 match(Set dst (AbsI src));
7781
7782 ins_cost(ALU_COST * 3);
7783 format %{
7784 "sraiw t0, $src, 0x1f\n\t"
7785 "addw $dst, $src, t0\n\t"
7786 "xorr $dst, $dst, t0\t#@absI_reg"
7787 %}
7788
7789 ins_encode %{
7790 __ sraiw(t0, as_Register($src$$reg), 0x1f);
7791 __ addw(as_Register($dst$$reg), as_Register($src$$reg), t0);
7792 __ xorr(as_Register($dst$$reg), as_Register($dst$$reg), t0);
7793 %}
7794
7795 ins_pipe(pipe_class_default);
7796 %}
7797
7798 instruct absL_reg(iRegLNoSp dst, iRegL src) %{
7799 match(Set dst (AbsL src));
7800
7801 ins_cost(ALU_COST * 3);
7802 format %{
7803 "srai t0, $src, 0x3f\n\t"
7804 "add $dst, $src, t0\n\t"
7805 "xorr $dst, $dst, t0\t#@absL_reg"
7806 %}
7807
7808 ins_encode %{
7809 __ srai(t0, as_Register($src$$reg), 0x3f);
7810 __ add(as_Register($dst$$reg), as_Register($src$$reg), t0);
7811 __ xorr(as_Register($dst$$reg), as_Register($dst$$reg), t0);
7812 %}
7813
7814 ins_pipe(pipe_class_default);
7815 %}
7816
7817 instruct absF_reg(fRegF dst, fRegF src) %{
7818 match(Set dst (AbsF src));
7819
7820 ins_cost(XFER_COST);
7821 format %{ "fsgnjx.s $dst, $src, $src\t#@absF_reg" %}
7822 ins_encode %{
7823 __ fabs_s(as_FloatRegister($dst$$reg),
7824 as_FloatRegister($src$$reg));
7825 %}
7826
7827 ins_pipe(fp_uop_s);
7828 %}
7829
7830 instruct absD_reg(fRegD dst, fRegD src) %{
7831 match(Set dst (AbsD src));
7832
7833 ins_cost(XFER_COST);
7834 format %{ "fsgnjx.d $dst, $src, $src\t#@absD_reg" %}
7835 ins_encode %{
7836 __ fabs_d(as_FloatRegister($dst$$reg),
7837 as_FloatRegister($src$$reg));
7838 %}
7839
7840 ins_pipe(fp_uop_d);
7841 %}
7842
7843 instruct sqrtF_reg(fRegF dst, fRegF src) %{
7844 match(Set dst (SqrtF src));
7845
7846 ins_cost(FSQRT_COST);
7847 format %{ "fsqrt.s $dst, $src\t#@sqrtF_reg" %}
7848 ins_encode %{
7849 __ fsqrt_s(as_FloatRegister($dst$$reg),
7850 as_FloatRegister($src$$reg));
7851 %}
7852
7853 ins_pipe(fp_sqrt_s);
7854 %}
7855
7856 instruct sqrtD_reg(fRegD dst, fRegD src) %{
7857 match(Set dst (SqrtD src));
7858
7859 ins_cost(FSQRT_COST);
7860 format %{ "fsqrt.d $dst, $src\t#@sqrtD_reg" %}
7861 ins_encode %{
7862 __ fsqrt_d(as_FloatRegister($dst$$reg),
7863 as_FloatRegister($src$$reg));
7864 %}
7865
7866 ins_pipe(fp_sqrt_d);
7867 %}
7868
7869 // Round Instruction
7870 instruct roundD_reg(fRegD dst, fRegD src, immI rmode, iRegLNoSp tmp1, iRegLNoSp tmp2, iRegLNoSp tmp3) %{
7871 match(Set dst (RoundDoubleMode src rmode));
7872 ins_cost(2 * XFER_COST + BRANCH_COST);
7873 effect(TEMP_DEF dst, TEMP tmp1, TEMP tmp2, TEMP tmp3);
7874
7875 format %{ "RoundDoubleMode $src, $rmode" %}
7876 ins_encode %{
7877 __ round_double_mode(as_FloatRegister($dst$$reg),
7878 as_FloatRegister($src$$reg), $rmode$$constant, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
7879 %}
7880 ins_pipe(pipe_class_default);
7881 %}
7882
7883 // Copysign and signum intrinsics
7884
7885 instruct copySignD_reg(fRegD dst, fRegD src1, fRegD src2, immD zero) %{
7886 match(Set dst (CopySignD src1 (Binary src2 zero)));
7887 format %{ "CopySignD $dst $src1 $src2" %}
7888 ins_encode %{
7889 FloatRegister dst = as_FloatRegister($dst$$reg),
7890 src1 = as_FloatRegister($src1$$reg),
7891 src2 = as_FloatRegister($src2$$reg);
7892 __ fsgnj_d(dst, src1, src2);
7893 %}
7894 ins_pipe(fp_dop_reg_reg_d);
7895 %}
7896
7897 instruct copySignF_reg(fRegF dst, fRegF src1, fRegF src2) %{
7898 match(Set dst (CopySignF src1 src2));
7899 format %{ "CopySignF $dst $src1 $src2" %}
7900 ins_encode %{
7901 FloatRegister dst = as_FloatRegister($dst$$reg),
7902 src1 = as_FloatRegister($src1$$reg),
7903 src2 = as_FloatRegister($src2$$reg);
7904 __ fsgnj_s(dst, src1, src2);
7905 %}
7906 ins_pipe(fp_dop_reg_reg_s);
7907 %}
7908
7909 instruct signumD_reg(fRegD dst, immD zero, fRegD one) %{
7910 match(Set dst (SignumD dst (Binary zero one)));
7911 format %{ "signumD $dst, $dst" %}
7912 ins_encode %{
7913 __ signum_fp(as_FloatRegister($dst$$reg), as_FloatRegister($one$$reg), true /* is_double */);
7914 %}
7915 ins_pipe(pipe_class_default);
7916 %}
7917
7918 instruct signumF_reg(fRegF dst, immF zero, fRegF one) %{
7919 match(Set dst (SignumF dst (Binary zero one)));
7920 format %{ "signumF $dst, $dst" %}
7921 ins_encode %{
7922 __ signum_fp(as_FloatRegister($dst$$reg), as_FloatRegister($one$$reg), false /* is_double */);
7923 %}
7924 ins_pipe(pipe_class_default);
7925 %}
7926
7927 // Arithmetic Instructions End
7928
7929 // ============================================================================
7930 // Logical Instructions
7931
7932 // Register And
7933 instruct andI_reg_reg(iRegINoSp dst, iRegI src1, iRegI src2) %{
7934 match(Set dst (AndI src1 src2));
7935
7936 format %{ "andr $dst, $src1, $src2\t#@andI_reg_reg" %}
7937
7938 ins_cost(ALU_COST);
7939 ins_encode %{
7940 __ andr(as_Register($dst$$reg),
7941 as_Register($src1$$reg),
7942 as_Register($src2$$reg));
7943 %}
7944
7945 ins_pipe(ialu_reg_reg);
7946 %}
7947
7948 // Immediate And
7949 instruct andI_reg_imm(iRegINoSp dst, iRegI src1, immIAdd src2) %{
7950 match(Set dst (AndI src1 src2));
7951
7952 format %{ "andi $dst, $src1, $src2\t#@andI_reg_imm" %}
7953
7954 ins_cost(ALU_COST);
7955 ins_encode %{
7956 __ andi(as_Register($dst$$reg),
7957 as_Register($src1$$reg),
7958 (int32_t)($src2$$constant));
7959 %}
7960
7961 ins_pipe(ialu_reg_imm);
7962 %}
7963
7964 // Register Or
7965 instruct orI_reg_reg(iRegINoSp dst, iRegI src1, iRegI src2) %{
7966 match(Set dst (OrI src1 src2));
7967
7968 format %{ "orr $dst, $src1, $src2\t#@orI_reg_reg" %}
7969
7970 ins_cost(ALU_COST);
7971 ins_encode %{
7972 __ orr(as_Register($dst$$reg),
7973 as_Register($src1$$reg),
7974 as_Register($src2$$reg));
7975 %}
7976
7977 ins_pipe(ialu_reg_reg);
7978 %}
7979
7980 // Immediate Or
7981 instruct orI_reg_imm(iRegINoSp dst, iRegI src1, immIAdd src2) %{
7982 match(Set dst (OrI src1 src2));
7983
7984 format %{ "ori $dst, $src1, $src2\t#@orI_reg_imm" %}
7985
7986 ins_cost(ALU_COST);
7987 ins_encode %{
7988 __ ori(as_Register($dst$$reg),
7989 as_Register($src1$$reg),
7990 (int32_t)($src2$$constant));
7991 %}
7992
7993 ins_pipe(ialu_reg_imm);
7994 %}
7995
7996 // Register Xor
7997 instruct xorI_reg_reg(iRegINoSp dst, iRegI src1, iRegI src2) %{
7998 match(Set dst (XorI src1 src2));
7999
8000 format %{ "xorr $dst, $src1, $src2\t#@xorI_reg_reg" %}
8001
8002 ins_cost(ALU_COST);
8003 ins_encode %{
8004 __ xorr(as_Register($dst$$reg),
8005 as_Register($src1$$reg),
8006 as_Register($src2$$reg));
8007 %}
8008
8009 ins_pipe(ialu_reg_reg);
8010 %}
8011
8012 // Immediate Xor
8013 instruct xorI_reg_imm(iRegINoSp dst, iRegI src1, immIAdd src2) %{
8014 match(Set dst (XorI src1 src2));
8015
8016 format %{ "xori $dst, $src1, $src2\t#@xorI_reg_imm" %}
8017
8018 ins_cost(ALU_COST);
8019 ins_encode %{
8020 __ xori(as_Register($dst$$reg),
8021 as_Register($src1$$reg),
8022 (int32_t)($src2$$constant));
8023 %}
8024
8025 ins_pipe(ialu_reg_imm);
8026 %}
8027
8028 // Register And Long
8029 instruct andL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
8030 match(Set dst (AndL src1 src2));
8031
8032 format %{ "andr $dst, $src1, $src2\t#@andL_reg_reg" %}
8033
8034 ins_cost(ALU_COST);
8035 ins_encode %{
8036 __ andr(as_Register($dst$$reg),
8037 as_Register($src1$$reg),
8038 as_Register($src2$$reg));
8039 %}
8040
8041 ins_pipe(ialu_reg_reg);
8042 %}
8043
8044 // Immediate And Long
8045 instruct andL_reg_imm(iRegLNoSp dst, iRegL src1, immLAdd src2) %{
8046 match(Set dst (AndL src1 src2));
8047
8048 format %{ "andi $dst, $src1, $src2\t#@andL_reg_imm" %}
8049
8050 ins_cost(ALU_COST);
8051 ins_encode %{
8052 __ andi(as_Register($dst$$reg),
8053 as_Register($src1$$reg),
8054 (int32_t)($src2$$constant));
8055 %}
8056
8057 ins_pipe(ialu_reg_imm);
8058 %}
8059
8060 // Register Or Long
8061 instruct orL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
8062 match(Set dst (OrL src1 src2));
8063
8064 format %{ "orr $dst, $src1, $src2\t#@orL_reg_reg" %}
8065
8066 ins_cost(ALU_COST);
8067 ins_encode %{
8068 __ orr(as_Register($dst$$reg),
8069 as_Register($src1$$reg),
8070 as_Register($src2$$reg));
8071 %}
8072
8073 ins_pipe(ialu_reg_reg);
8074 %}
8075
8076 // Immediate Or Long
8077 instruct orL_reg_imm(iRegLNoSp dst, iRegL src1, immLAdd src2) %{
8078 match(Set dst (OrL src1 src2));
8079
8080 format %{ "ori $dst, $src1, $src2\t#@orL_reg_imm" %}
8081
8082 ins_cost(ALU_COST);
8083 ins_encode %{
8084 __ ori(as_Register($dst$$reg),
8085 as_Register($src1$$reg),
8086 (int32_t)($src2$$constant));
8087 %}
8088
8089 ins_pipe(ialu_reg_imm);
8090 %}
8091
8092 // Register Xor Long
8093 instruct xorL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
8094 match(Set dst (XorL src1 src2));
8095
8096 format %{ "xorr $dst, $src1, $src2\t#@xorL_reg_reg" %}
8097
8098 ins_cost(ALU_COST);
8099 ins_encode %{
8100 __ xorr(as_Register($dst$$reg),
8101 as_Register($src1$$reg),
8102 as_Register($src2$$reg));
8103 %}
8104
8105 ins_pipe(ialu_reg_reg);
8106 %}
8107
8108 // Immediate Xor Long
8109 instruct xorL_reg_imm(iRegLNoSp dst, iRegL src1, immLAdd src2) %{
8110 match(Set dst (XorL src1 src2));
8111
8112 ins_cost(ALU_COST);
8113 format %{ "xori $dst, $src1, $src2\t#@xorL_reg_imm" %}
8114
8115 ins_encode %{
8116 __ xori(as_Register($dst$$reg),
8117 as_Register($src1$$reg),
8118 (int32_t)($src2$$constant));
8119 %}
8120
8121 ins_pipe(ialu_reg_imm);
8122 %}
8123
8124 // ============================================================================
8125 // MemBar Instruction
8126
8127 // RVTSO
8128
8129 instruct unnecessary_membar_rvtso() %{
8130 predicate(UseZtso);
8131 match(LoadFence);
8132 match(StoreFence);
8133 match(StoreStoreFence);
8134 match(MemBarAcquire);
8135 match(MemBarRelease);
8136 match(MemBarStoreStore);
8137 match(MemBarAcquireLock);
8138 match(MemBarReleaseLock);
8139
8140 ins_cost(0);
8141
8142 size(0);
8143
8144 format %{ "#@unnecessary_membar_rvtso elided/tso (empty encoding)" %}
8145 ins_encode %{
8146 __ block_comment("unnecessary_membar_rvtso");
8147 %}
8148 ins_pipe(real_empty);
8149 %}
8150
8151 instruct membar_storeload_rvtso() %{
8152 predicate(UseZtso);
8153 match(MemBarStoreLoad);
8154 ins_cost(VOLATILE_REF_COST);
8155
8156 format %{ "#@membar_storeload_rvtso\n\t"
8157 "fence w, r"%}
8158
8159 ins_encode %{
8160 __ block_comment("membar_storeload_rvtso");
8161 __ membar(MacroAssembler::StoreLoad);
8162 %}
8163
8164 ins_pipe(pipe_slow);
8165 %}
8166
8167 instruct membar_volatile_rvtso() %{
8168 predicate(UseZtso);
8169 match(MemBarVolatile);
8170 ins_cost(VOLATILE_REF_COST);
8171
8172 format %{ "#@membar_volatile_rvtso\n\t"
8173 "fence w, r"%}
8174
8175 ins_encode %{
8176 __ block_comment("membar_volatile_rvtso");
8177 __ membar(MacroAssembler::StoreLoad);
8178 %}
8179
8180 ins_pipe(pipe_slow);
8181 %}
8182
8183 instruct unnecessary_membar_volatile_rvtso() %{
8184 predicate(UseZtso && Matcher::post_store_load_barrier(n));
8185 match(MemBarVolatile);
8186 ins_cost(0);
8187
8188 size(0);
8189
8190 format %{ "#@unnecessary_membar_volatile_rvtso (unnecessary so empty encoding)" %}
8191 ins_encode %{
8192 __ block_comment("unnecessary_membar_volatile_rvtso");
8193 %}
8194 ins_pipe(real_empty);
8195 %}
8196
8197 instruct membar_full_rvtso() %{
8198 predicate(UseZtso);
8199 match(MemBarFull);
8200 ins_cost(VOLATILE_REF_COST);
8201
8202 format %{ "#@membar_full_rvtso\n\t"
8203 "fence rw, rw" %}
8204
8205 ins_encode %{
8206 __ block_comment("membar_full_rvtso");
8207 __ membar(MacroAssembler::AnyAny);
8208 %}
8209
8210 ins_pipe(pipe_slow);
8211 %}
8212
8213 // RVWMO
8214
8215 instruct membar_aqcuire_rvwmo() %{
8216 predicate(!UseZtso);
8217 match(LoadFence);
8218 match(MemBarAcquire);
8219 ins_cost(VOLATILE_REF_COST);
8220
8221 format %{ "#@membar_aqcuire_rvwmo\n\t"
8222 "fence r, rw" %}
8223
8224 ins_encode %{
8225 __ block_comment("membar_aqcuire_rvwmo");
8226 __ membar(MacroAssembler::LoadLoad | MacroAssembler::LoadStore);
8227 %}
8228 ins_pipe(pipe_serial);
8229 %}
8230
8231 instruct membar_release_rvwmo() %{
8232 predicate(!UseZtso);
8233 match(StoreFence);
8234 match(MemBarRelease);
8235 ins_cost(VOLATILE_REF_COST);
8236
8237 format %{ "#@membar_release_rvwmo\n\t"
8238 "fence rw, w" %}
8239
8240 ins_encode %{
8241 __ block_comment("membar_release_rvwmo");
8242 __ membar(MacroAssembler::LoadStore | MacroAssembler::StoreStore);
8243 %}
8244 ins_pipe(pipe_serial);
8245 %}
8246
8247 instruct membar_storestore_rvwmo() %{
8248 predicate(!UseZtso);
8249 match(MemBarStoreStore);
8250 match(StoreStoreFence);
8251 ins_cost(VOLATILE_REF_COST);
8252
8253 format %{ "#@membar_storestore_rvwmo\n\t"
8254 "fence w, w" %}
8255
8256 ins_encode %{
8257 __ membar(MacroAssembler::StoreStore);
8258 %}
8259 ins_pipe(pipe_serial);
8260 %}
8261
8262 instruct membar_storeload_rvwmo() %{
8263 predicate(!UseZtso);
8264 match(MemBarStoreLoad);
8265 ins_cost(VOLATILE_REF_COST);
8266
8267 format %{ "#@membar_storeload_rvwmo\n\t"
8268 "fence w, r"%}
8269
8270 ins_encode %{
8271 __ block_comment("membar_storeload_rvwmo");
8272 __ membar(MacroAssembler::StoreLoad);
8273 %}
8274
8275 ins_pipe(pipe_serial);
8276 %}
8277
8278 instruct membar_volatile_rvwmo() %{
8279 predicate(!UseZtso);
8280 match(MemBarVolatile);
8281 ins_cost(VOLATILE_REF_COST);
8282
8283 format %{ "#@membar_volatile_rvwmo\n\t"
8284 "fence w, r"%}
8285
8286 ins_encode %{
8287 __ block_comment("membar_volatile_rvwmo");
8288 __ membar(MacroAssembler::StoreLoad);
8289 %}
8290
8291 ins_pipe(pipe_serial);
8292 %}
8293
8294 instruct membar_lock_rvwmo() %{
8295 predicate(!UseZtso);
8296 match(MemBarAcquireLock);
8297 match(MemBarReleaseLock);
8298 ins_cost(0);
8299
8300 format %{ "#@membar_lock_rvwmo (elided)" %}
8301
8302 ins_encode %{
8303 __ block_comment("membar_lock_rvwmo (elided)");
8304 %}
8305
8306 ins_pipe(pipe_serial);
8307 %}
8308
8309 instruct unnecessary_membar_volatile_rvwmo() %{
8310 predicate(!UseZtso && Matcher::post_store_load_barrier(n));
8311 match(MemBarVolatile);
8312 ins_cost(0);
8313
8314 size(0);
8315 format %{ "#@unnecessary_membar_volatile_rvwmo (unnecessary so empty encoding)" %}
8316 ins_encode %{
8317 __ block_comment("unnecessary_membar_volatile_rvwmo");
8318 %}
8319 ins_pipe(real_empty);
8320 %}
8321
8322 instruct membar_full_rvwmo() %{
8323 predicate(!UseZtso);
8324 match(MemBarFull);
8325 ins_cost(VOLATILE_REF_COST);
8326
8327 format %{ "#@membar_full_rvwmo\n\t"
8328 "fence rw, rw" %}
8329
8330 ins_encode %{
8331 __ block_comment("membar_full_rvwmo");
8332 __ membar(MacroAssembler::AnyAny);
8333 %}
8334
8335 ins_pipe(pipe_serial);
8336 %}
8337
8338 instruct spin_wait() %{
8339 predicate(UseZihintpause);
8340 match(OnSpinWait);
8341 ins_cost(CACHE_MISS_COST);
8342
8343 format %{ "spin_wait" %}
8344
8345 ins_encode %{
8346 __ pause();
8347 %}
8348
8349 ins_pipe(pipe_serial);
8350 %}
8351
8352 // ============================================================================
8353 // Cast Instructions (Java-level type cast)
8354
8355 instruct castX2P(iRegPNoSp dst, iRegL src) %{
8356 match(Set dst (CastX2P src));
8357
8358 ins_cost(ALU_COST);
8359 format %{ "mv $dst, $src\t# long -> ptr, #@castX2P" %}
8360
8361 ins_encode %{
8362 if ($dst$$reg != $src$$reg) {
8363 __ mv(as_Register($dst$$reg), as_Register($src$$reg));
8364 }
8365 %}
8366
8367 ins_pipe(ialu_reg);
8368 %}
8369
8370 instruct castP2X(iRegLNoSp dst, iRegP src) %{
8371 match(Set dst (CastP2X src));
8372
8373 ins_cost(ALU_COST);
8374 format %{ "mv $dst, $src\t# ptr -> long, #@castP2X" %}
8375
8376 ins_encode %{
8377 if ($dst$$reg != $src$$reg) {
8378 __ mv(as_Register($dst$$reg), as_Register($src$$reg));
8379 }
8380 %}
8381
8382 ins_pipe(ialu_reg);
8383 %}
8384
8385 instruct castPP(iRegPNoSp dst)
8386 %{
8387 match(Set dst (CastPP dst));
8388 ins_cost(0);
8389
8390 size(0);
8391 format %{ "# castPP of $dst, #@castPP" %}
8392 ins_encode(/* empty encoding */);
8393 ins_pipe(pipe_class_empty);
8394 %}
8395
8396 instruct castLL(iRegL dst)
8397 %{
8398 match(Set dst (CastLL dst));
8399
8400 size(0);
8401 format %{ "# castLL of $dst, #@castLL" %}
8402 ins_encode(/* empty encoding */);
8403 ins_cost(0);
8404 ins_pipe(pipe_class_empty);
8405 %}
8406
8407 instruct castII(iRegI dst)
8408 %{
8409 match(Set dst (CastII dst));
8410
8411 size(0);
8412 format %{ "# castII of $dst, #@castII" %}
8413 ins_encode(/* empty encoding */);
8414 ins_cost(0);
8415 ins_pipe(pipe_class_empty);
8416 %}
8417
8418 instruct checkCastPP(iRegPNoSp dst)
8419 %{
8420 match(Set dst (CheckCastPP dst));
8421
8422 size(0);
8423 ins_cost(0);
8424 format %{ "# checkcastPP of $dst, #@checkCastPP" %}
8425 ins_encode(/* empty encoding */);
8426 ins_pipe(pipe_class_empty);
8427 %}
8428
8429 instruct castHH(fRegF dst)
8430 %{
8431 match(Set dst (CastHH dst));
8432
8433 size(0);
8434 format %{ "# castHH of $dst" %}
8435 ins_encode(/* empty encoding */);
8436 ins_cost(0);
8437 ins_pipe(pipe_class_empty);
8438 %}
8439
8440 instruct castFF(fRegF dst)
8441 %{
8442 match(Set dst (CastFF dst));
8443
8444 size(0);
8445 format %{ "# castFF of $dst" %}
8446 ins_encode(/* empty encoding */);
8447 ins_cost(0);
8448 ins_pipe(pipe_class_empty);
8449 %}
8450
8451 instruct castDD(fRegD dst)
8452 %{
8453 match(Set dst (CastDD dst));
8454
8455 size(0);
8456 format %{ "# castDD of $dst" %}
8457 ins_encode(/* empty encoding */);
8458 ins_cost(0);
8459 ins_pipe(pipe_class_empty);
8460 %}
8461
8462 instruct castVV(vReg dst)
8463 %{
8464 match(Set dst (CastVV dst));
8465
8466 size(0);
8467 format %{ "# castVV of $dst" %}
8468 ins_encode(/* empty encoding */);
8469 ins_cost(0);
8470 ins_pipe(pipe_class_empty);
8471 %}
8472
8473 instruct castVVMask(vRegMask dst)
8474 %{
8475 match(Set dst (CastVV dst));
8476
8477 size(0);
8478 format %{ "# castVV of $dst" %}
8479 ins_encode(/* empty encoding */);
8480 ins_cost(0);
8481 ins_pipe(pipe_class_empty);
8482 %}
8483
8484 // ============================================================================
8485 // Convert Instructions
8486
8487 // int to bool
8488 instruct convI2Bool(iRegINoSp dst, iRegI src)
8489 %{
8490 match(Set dst (Conv2B src));
8491
8492 ins_cost(ALU_COST);
8493 format %{ "snez $dst, $src\t#@convI2Bool" %}
8494
8495 ins_encode %{
8496 __ snez(as_Register($dst$$reg), as_Register($src$$reg));
8497 %}
8498
8499 ins_pipe(ialu_reg);
8500 %}
8501
8502 // pointer to bool
8503 instruct convP2Bool(iRegINoSp dst, iRegP src)
8504 %{
8505 match(Set dst (Conv2B src));
8506
8507 ins_cost(ALU_COST);
8508 format %{ "snez $dst, $src\t#@convP2Bool" %}
8509
8510 ins_encode %{
8511 __ snez(as_Register($dst$$reg), as_Register($src$$reg));
8512 %}
8513
8514 ins_pipe(ialu_reg);
8515 %}
8516
8517 // int <-> long
8518
8519 instruct convI2L_reg_reg(iRegLNoSp dst, iRegIorL2I src)
8520 %{
8521 match(Set dst (ConvI2L src));
8522
8523 ins_cost(ALU_COST);
8524 format %{ "addw $dst, $src, zr\t#@convI2L_reg_reg" %}
8525 ins_encode %{
8526 __ sext(as_Register($dst$$reg), as_Register($src$$reg), 32);
8527 %}
8528 ins_pipe(ialu_reg);
8529 %}
8530
8531 instruct convL2I_reg(iRegINoSp dst, iRegL src) %{
8532 match(Set dst (ConvL2I src));
8533
8534 ins_cost(ALU_COST);
8535 format %{ "addw $dst, $src, zr\t#@convL2I_reg" %}
8536
8537 ins_encode %{
8538 __ sext(as_Register($dst$$reg), as_Register($src$$reg), 32);
8539 %}
8540
8541 ins_pipe(ialu_reg);
8542 %}
8543
8544 // int to unsigned long (Zero-extend)
8545 instruct convI2UL_reg_reg(iRegLNoSp dst, iRegIorL2I src, immL_32bits mask)
8546 %{
8547 match(Set dst (AndL (ConvI2L src) mask));
8548
8549 ins_cost(ALU_COST * 2);
8550 format %{ "zext $dst, $src, 32\t# i2ul, #@convI2UL_reg_reg" %}
8551
8552 ins_encode %{
8553 __ zext(as_Register($dst$$reg), as_Register($src$$reg), 32);
8554 %}
8555
8556 ins_pipe(ialu_reg_shift);
8557 %}
8558
8559 // float <-> double
8560
8561 instruct convF2D_reg(fRegD dst, fRegF src) %{
8562 match(Set dst (ConvF2D src));
8563
8564 ins_cost(XFER_COST);
8565 format %{ "fcvt.d.s $dst, $src\t#@convF2D_reg" %}
8566
8567 ins_encode %{
8568 __ fcvt_d_s(as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg));
8569 %}
8570
8571 ins_pipe(fp_f2d);
8572 %}
8573
8574 instruct convD2F_reg(fRegF dst, fRegD src) %{
8575 match(Set dst (ConvD2F src));
8576
8577 ins_cost(XFER_COST);
8578 format %{ "fcvt.s.d $dst, $src\t#@convD2F_reg" %}
8579
8580 ins_encode %{
8581 __ fcvt_s_d(as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg));
8582 %}
8583
8584 ins_pipe(fp_d2f);
8585 %}
8586
8587 // single <-> half precision
8588
8589 instruct convHF2F_reg_reg(fRegF dst, iRegIorL2I src, iRegINoSp tmp) %{
8590 match(Set dst (ConvHF2F src));
8591 effect(TEMP tmp);
8592 format %{ "fmv.h.x $dst, $src\t# move source from $src to $dst\n\t"
8593 "fcvt.s.h $dst, $dst\t# convert half to single precision"
8594 %}
8595 ins_encode %{
8596 __ float16_to_float($dst$$FloatRegister, $src$$Register, $tmp$$Register);
8597 %}
8598 ins_pipe(pipe_slow);
8599 %}
8600
8601 instruct convF2HF_reg_reg(iRegINoSp dst, fRegF src, fRegF ftmp, iRegINoSp xtmp) %{
8602 match(Set dst (ConvF2HF src));
8603 effect(TEMP_DEF dst, TEMP ftmp, TEMP xtmp);
8604 format %{ "fcvt.h.s $ftmp, $src\t# convert single precision to half\n\t"
8605 "fmv.x.h $dst, $ftmp\t# move result from $ftmp to $dst"
8606 %}
8607 ins_encode %{
8608 __ float_to_float16($dst$$Register, $src$$FloatRegister, $ftmp$$FloatRegister, $xtmp$$Register);
8609 %}
8610 ins_pipe(pipe_slow);
8611 %}
8612
8613 // half precision operations
8614
8615 instruct reinterpretS2HF(fRegF dst, iRegI src)
8616 %{
8617 match(Set dst (ReinterpretS2HF src));
8618 format %{ "fmv.h.x $dst, $src\t# reinterpretS2HF" %}
8619 ins_encode %{
8620 __ fmv_h_x($dst$$FloatRegister, $src$$Register);
8621 %}
8622 ins_pipe(fp_i2f);
8623 %}
8624
8625 instruct convF2HFAndS2HF(fRegF dst, fRegF src)
8626 %{
8627 match(Set dst (ReinterpretS2HF (ConvF2HF src)));
8628 format %{ "convF2HFAndS2HF $dst, $src" %}
8629 ins_encode %{
8630 __ fcvt_h_s($dst$$FloatRegister, $src$$FloatRegister);
8631 %}
8632 ins_pipe(fp_uop_s);
8633 %}
8634
8635 instruct reinterpretHF2S(iRegINoSp dst, fRegF src)
8636 %{
8637 match(Set dst (ReinterpretHF2S src));
8638 format %{ "fmv.x.h $dst, $src\t# reinterpretHF2S" %}
8639 ins_encode %{
8640 __ fmv_x_h($dst$$Register, $src$$FloatRegister);
8641 %}
8642 ins_pipe(fp_f2i);
8643 %}
8644
8645 instruct convHF2SAndHF2F(fRegF dst, fRegF src)
8646 %{
8647 match(Set dst (ConvHF2F (ReinterpretHF2S src)));
8648 format %{ "convHF2SAndHF2F $dst, $src" %}
8649 ins_encode %{
8650 __ fcvt_s_h($dst$$FloatRegister, $src$$FloatRegister);
8651 %}
8652 ins_pipe(fp_uop_s);
8653 %}
8654
8655 instruct sqrt_HF_reg(fRegF dst, fRegF src)
8656 %{
8657 match(Set dst (SqrtHF src));
8658 format %{ "fsqrt.h $dst, $src" %}
8659 ins_encode %{
8660 __ fsqrt_h($dst$$FloatRegister, $src$$FloatRegister);
8661 %}
8662 ins_pipe(fp_sqrt_s);
8663 %}
8664
8665 instruct binOps_HF_reg(fRegF dst, fRegF src1, fRegF src2)
8666 %{
8667 match(Set dst (AddHF src1 src2));
8668 match(Set dst (SubHF src1 src2));
8669 match(Set dst (MulHF src1 src2));
8670 match(Set dst (DivHF src1 src2));
8671 format %{ "binop_hf $dst, $src1, $src2" %}
8672 ins_encode %{
8673 int opcode = this->ideal_Opcode();
8674 switch(opcode) {
8675 case Op_AddHF: __ fadd_h($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); break;
8676 case Op_SubHF: __ fsub_h($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); break;
8677 case Op_MulHF: __ fmul_h($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); break;
8678 case Op_DivHF: __ fdiv_h($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); break;
8679 default: assert(false, "%s is not supported here", NodeClassNames[opcode]); break;
8680 }
8681 %}
8682 ins_pipe(fp_dop_reg_reg_s);
8683 %}
8684
8685 instruct min_HF_reg(fRegF dst, fRegF src1, fRegF src2, rFlagsReg cr)
8686 %{
8687 predicate(!UseZfa);
8688 match(Set dst (MinHF src1 src2));
8689 effect(KILL cr);
8690
8691 format %{ "min_hf $dst, $src1, $src2" %}
8692
8693 ins_encode %{
8694 __ minmax_fp($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister,
8695 __ FLOAT_TYPE::half_precision, true /* is_min */);
8696 %}
8697 ins_pipe(pipe_class_default);
8698 %}
8699
8700 instruct min_HF_reg_zfa(fRegF dst, fRegF src1, fRegF src2)
8701 %{
8702 predicate(UseZfa);
8703 match(Set dst (MinHF src1 src2));
8704
8705 format %{ "min_hf $dst, $src1, $src2" %}
8706
8707 ins_encode %{
8708 __ fminm_h(as_FloatRegister($dst$$reg),
8709 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
8710 %}
8711
8712 ins_pipe(pipe_class_default);
8713 %}
8714
8715 instruct max_HF_reg(fRegF dst, fRegF src1, fRegF src2, rFlagsReg cr)
8716 %{
8717 predicate(!UseZfa);
8718 match(Set dst (MaxHF src1 src2));
8719 effect(KILL cr);
8720
8721 format %{ "max_hf $dst, $src1, $src2" %}
8722
8723 ins_encode %{
8724 __ minmax_fp($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister,
8725 __ FLOAT_TYPE::half_precision, false /* is_min */);
8726 %}
8727 ins_pipe(pipe_class_default);
8728 %}
8729
8730 instruct max_HF_reg_zfa(fRegF dst, fRegF src1, fRegF src2)
8731 %{
8732 predicate(UseZfa);
8733 match(Set dst (MaxHF src1 src2));
8734
8735 format %{ "max_hf $dst, $src1, $src2" %}
8736
8737 ins_encode %{
8738 __ fmaxm_h(as_FloatRegister($dst$$reg),
8739 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
8740 %}
8741
8742 ins_pipe(pipe_class_default);
8743 %}
8744
8745 instruct fma_HF_reg(fRegF dst, fRegF src1, fRegF src2, fRegF src3)
8746 %{
8747 match(Set dst (FmaHF src3 (Binary src1 src2)));
8748 format %{ "fmadd.h $dst, $src1, $src2, $src3\t# $dst = $src1 * $src2 + $src3 fma packedH" %}
8749 ins_encode %{
8750 __ fmadd_h($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister, $src3$$FloatRegister);
8751 %}
8752 ins_pipe(pipe_class_default);
8753 %}
8754
8755 // float <-> int
8756
8757 instruct convF2I_reg_reg(iRegINoSp dst, fRegF src) %{
8758 match(Set dst (ConvF2I src));
8759
8760 ins_cost(XFER_COST);
8761 format %{ "fcvt.w.s $dst, $src\t#@convF2I_reg_reg" %}
8762
8763 ins_encode %{
8764 __ fcvt_w_s_safe($dst$$Register, $src$$FloatRegister);
8765 %}
8766
8767 ins_pipe(fp_f2i);
8768 %}
8769
8770 instruct convI2F_reg_reg(fRegF dst, iRegIorL2I src) %{
8771 match(Set dst (ConvI2F src));
8772
8773 ins_cost(XFER_COST);
8774 format %{ "fcvt.s.w $dst, $src\t#@convI2F_reg_reg" %}
8775
8776 ins_encode %{
8777 __ fcvt_s_w(as_FloatRegister($dst$$reg), as_Register($src$$reg));
8778 %}
8779
8780 ins_pipe(fp_i2f);
8781 %}
8782
8783 // float <-> long
8784
8785 instruct convF2L_reg_reg(iRegLNoSp dst, fRegF src) %{
8786 match(Set dst (ConvF2L src));
8787
8788 ins_cost(XFER_COST);
8789 format %{ "fcvt.l.s $dst, $src\t#@convF2L_reg_reg" %}
8790
8791 ins_encode %{
8792 __ fcvt_l_s_safe($dst$$Register, $src$$FloatRegister);
8793 %}
8794
8795 ins_pipe(fp_f2l);
8796 %}
8797
8798 instruct convL2F_reg_reg(fRegF dst, iRegL src) %{
8799 match(Set dst (ConvL2F src));
8800
8801 ins_cost(XFER_COST);
8802 format %{ "fcvt.s.l $dst, $src\t#@convL2F_reg_reg" %}
8803
8804 ins_encode %{
8805 __ fcvt_s_l(as_FloatRegister($dst$$reg), as_Register($src$$reg));
8806 %}
8807
8808 ins_pipe(fp_l2f);
8809 %}
8810
8811 // double <-> int
8812
8813 instruct convD2I_reg_reg(iRegINoSp dst, fRegD src) %{
8814 match(Set dst (ConvD2I src));
8815
8816 ins_cost(XFER_COST);
8817 format %{ "fcvt.w.d $dst, $src\t#@convD2I_reg_reg" %}
8818
8819 ins_encode %{
8820 __ fcvt_w_d_safe($dst$$Register, $src$$FloatRegister);
8821 %}
8822
8823 ins_pipe(fp_d2i);
8824 %}
8825
8826 instruct convI2D_reg_reg(fRegD dst, iRegIorL2I src) %{
8827 match(Set dst (ConvI2D src));
8828
8829 ins_cost(XFER_COST);
8830 format %{ "fcvt.d.w $dst, $src\t#@convI2D_reg_reg" %}
8831
8832 ins_encode %{
8833 __ fcvt_d_w(as_FloatRegister($dst$$reg), as_Register($src$$reg));
8834 %}
8835
8836 ins_pipe(fp_i2d);
8837 %}
8838
8839 // double <-> long
8840
8841 instruct convD2L_reg_reg(iRegLNoSp dst, fRegD src) %{
8842 match(Set dst (ConvD2L src));
8843
8844 ins_cost(XFER_COST);
8845 format %{ "fcvt.l.d $dst, $src\t#@convD2L_reg_reg" %}
8846
8847 ins_encode %{
8848 __ fcvt_l_d_safe($dst$$Register, $src$$FloatRegister);
8849 %}
8850
8851 ins_pipe(fp_d2l);
8852 %}
8853
8854 instruct convL2D_reg_reg(fRegD dst, iRegL src) %{
8855 match(Set dst (ConvL2D src));
8856
8857 ins_cost(XFER_COST);
8858 format %{ "fcvt.d.l $dst, $src\t#@convL2D_reg_reg" %}
8859
8860 ins_encode %{
8861 __ fcvt_d_l(as_FloatRegister($dst$$reg), as_Register($src$$reg));
8862 %}
8863
8864 ins_pipe(fp_l2d);
8865 %}
8866
8867 // Convert oop into int for vectors alignment masking
8868 instruct convP2I(iRegINoSp dst, iRegP src) %{
8869 match(Set dst (ConvL2I (CastP2X src)));
8870
8871 ins_cost(ALU_COST * 2);
8872 format %{ "zext $dst, $src, 32\t# ptr -> int, #@convP2I" %}
8873
8874 ins_encode %{
8875 __ zext($dst$$Register, $src$$Register, 32);
8876 %}
8877
8878 ins_pipe(ialu_reg);
8879 %}
8880
8881 // Convert compressed oop into int for vectors alignment masking
8882 // in case of 32bit oops (heap < 4Gb).
8883 instruct convN2I(iRegINoSp dst, iRegN src)
8884 %{
8885 predicate(CompressedOops::shift() == 0);
8886 match(Set dst (ConvL2I (CastP2X (DecodeN src))));
8887
8888 ins_cost(ALU_COST);
8889 format %{ "mv $dst, $src\t# compressed ptr -> int, #@convN2I" %}
8890
8891 ins_encode %{
8892 __ mv($dst$$Register, $src$$Register);
8893 %}
8894
8895 ins_pipe(ialu_reg);
8896 %}
8897
8898 instruct round_double_reg(iRegLNoSp dst, fRegD src, fRegD ftmp) %{
8899 match(Set dst (RoundD src));
8900
8901 ins_cost(XFER_COST + BRANCH_COST);
8902 effect(TEMP ftmp);
8903 format %{ "java_round_double $dst, $src\t#@round_double_reg" %}
8904
8905 ins_encode %{
8906 __ java_round_double($dst$$Register, as_FloatRegister($src$$reg), as_FloatRegister($ftmp$$reg));
8907 %}
8908
8909 ins_pipe(pipe_slow);
8910 %}
8911
8912 instruct round_float_reg(iRegINoSp dst, fRegF src, fRegF ftmp) %{
8913 match(Set dst (RoundF src));
8914
8915 ins_cost(XFER_COST + BRANCH_COST);
8916 effect(TEMP ftmp);
8917 format %{ "java_round_float $dst, $src\t#@round_float_reg" %}
8918
8919 ins_encode %{
8920 __ java_round_float($dst$$Register, as_FloatRegister($src$$reg), as_FloatRegister($ftmp$$reg));
8921 %}
8922
8923 ins_pipe(pipe_slow);
8924 %}
8925
8926 // Convert oop pointer into compressed form
8927 instruct encodeHeapOop(iRegNNoSp dst, iRegP src) %{
8928 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
8929 match(Set dst (EncodeP src));
8930 ins_cost(ALU_COST);
8931 format %{ "encode_heap_oop $dst, $src\t#@encodeHeapOop" %}
8932 ins_encode %{
8933 Register s = $src$$Register;
8934 Register d = $dst$$Register;
8935 __ encode_heap_oop(d, s);
8936 %}
8937 ins_pipe(pipe_class_default);
8938 %}
8939
8940 instruct encodeHeapOop_not_null(iRegNNoSp dst, iRegP src) %{
8941 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
8942 match(Set dst (EncodeP src));
8943 ins_cost(ALU_COST);
8944 format %{ "encode_heap_oop_not_null $dst, $src\t#@encodeHeapOop_not_null" %}
8945 ins_encode %{
8946 __ encode_heap_oop_not_null($dst$$Register, $src$$Register);
8947 %}
8948 ins_pipe(pipe_class_default);
8949 %}
8950
8951 instruct decodeHeapOop(iRegPNoSp dst, iRegN src) %{
8952 predicate(n->bottom_type()->is_ptr()->ptr() != TypePtr::NotNull &&
8953 n->bottom_type()->is_ptr()->ptr() != TypePtr::Constant);
8954 match(Set dst (DecodeN src));
8955
8956 ins_cost(0);
8957 format %{ "decode_heap_oop $dst, $src\t#@decodeHeapOop" %}
8958 ins_encode %{
8959 Register s = $src$$Register;
8960 Register d = $dst$$Register;
8961 __ decode_heap_oop(d, s);
8962 %}
8963 ins_pipe(pipe_class_default);
8964 %}
8965
8966 instruct decodeHeapOop_not_null(iRegPNoSp dst, iRegN src) %{
8967 predicate(n->bottom_type()->is_ptr()->ptr() == TypePtr::NotNull ||
8968 n->bottom_type()->is_ptr()->ptr() == TypePtr::Constant);
8969 match(Set dst (DecodeN src));
8970
8971 ins_cost(0);
8972 format %{ "decode_heap_oop_not_null $dst, $src\t#@decodeHeapOop_not_null" %}
8973 ins_encode %{
8974 Register s = $src$$Register;
8975 Register d = $dst$$Register;
8976 __ decode_heap_oop_not_null(d, s);
8977 %}
8978 ins_pipe(pipe_class_default);
8979 %}
8980
8981 // Convert klass pointer into compressed form.
8982 instruct encodeKlass_not_null(iRegNNoSp dst, iRegP src) %{
8983 match(Set dst (EncodePKlass src));
8984
8985 ins_cost(ALU_COST);
8986 format %{ "encode_klass_not_null $dst, $src\t#@encodeKlass_not_null" %}
8987
8988 ins_encode %{
8989 Register src_reg = as_Register($src$$reg);
8990 Register dst_reg = as_Register($dst$$reg);
8991 __ encode_klass_not_null(dst_reg, src_reg, t0);
8992 %}
8993
8994 ins_pipe(pipe_class_default);
8995 %}
8996
8997 instruct decodeKlass_not_null(iRegPNoSp dst, iRegN src, iRegPNoSp tmp) %{
8998 match(Set dst (DecodeNKlass src));
8999
9000 effect(TEMP_DEF dst, TEMP tmp);
9001
9002 ins_cost(ALU_COST);
9003 format %{ "decode_klass_not_null $dst, $src\t#@decodeKlass_not_null" %}
9004
9005 ins_encode %{
9006 Register src_reg = as_Register($src$$reg);
9007 Register dst_reg = as_Register($dst$$reg);
9008 Register tmp_reg = as_Register($tmp$$reg);
9009 __ decode_klass_not_null(dst_reg, src_reg, tmp_reg);
9010 %}
9011
9012 ins_pipe(pipe_class_default);
9013 %}
9014
9015 // stack <-> reg and reg <-> reg shuffles with no conversion
9016
9017 instruct MoveF2I_stack_reg(iRegINoSp dst, stackSlotF src) %{
9018
9019 match(Set dst (MoveF2I src));
9020
9021 effect(DEF dst, USE src);
9022
9023 ins_cost(LOAD_COST);
9024
9025 format %{ "lw $dst, $src\t#@MoveF2I_stack_reg" %}
9026
9027 ins_encode %{
9028 __ lw(as_Register($dst$$reg), Address(sp, $src$$disp));
9029 %}
9030
9031 ins_pipe(iload_reg_reg);
9032
9033 %}
9034
9035 instruct MoveI2F_stack_reg(fRegF dst, stackSlotI src) %{
9036
9037 match(Set dst (MoveI2F src));
9038
9039 effect(DEF dst, USE src);
9040
9041 ins_cost(LOAD_COST);
9042
9043 format %{ "flw $dst, $src\t#@MoveI2F_stack_reg" %}
9044
9045 ins_encode %{
9046 __ flw(as_FloatRegister($dst$$reg), Address(sp, $src$$disp));
9047 %}
9048
9049 ins_pipe(fp_load_mem_s);
9050
9051 %}
9052
9053 instruct MoveD2L_stack_reg(iRegLNoSp dst, stackSlotD src) %{
9054
9055 match(Set dst (MoveD2L src));
9056
9057 effect(DEF dst, USE src);
9058
9059 ins_cost(LOAD_COST);
9060
9061 format %{ "ld $dst, $src\t#@MoveD2L_stack_reg" %}
9062
9063 ins_encode %{
9064 __ ld(as_Register($dst$$reg), Address(sp, $src$$disp));
9065 %}
9066
9067 ins_pipe(iload_reg_reg);
9068
9069 %}
9070
9071 instruct MoveL2D_stack_reg(fRegD dst, stackSlotL src) %{
9072
9073 match(Set dst (MoveL2D src));
9074
9075 effect(DEF dst, USE src);
9076
9077 ins_cost(LOAD_COST);
9078
9079 format %{ "fld $dst, $src\t#@MoveL2D_stack_reg" %}
9080
9081 ins_encode %{
9082 __ fld(as_FloatRegister($dst$$reg), Address(sp, $src$$disp));
9083 %}
9084
9085 ins_pipe(fp_load_mem_d);
9086
9087 %}
9088
9089 instruct MoveF2I_reg_stack(stackSlotI dst, fRegF src) %{
9090
9091 match(Set dst (MoveF2I src));
9092
9093 effect(DEF dst, USE src);
9094
9095 ins_cost(STORE_COST);
9096
9097 format %{ "fsw $src, $dst\t#@MoveF2I_reg_stack" %}
9098
9099 ins_encode %{
9100 __ fsw(as_FloatRegister($src$$reg), Address(sp, $dst$$disp));
9101 %}
9102
9103 ins_pipe(fp_store_reg_s);
9104
9105 %}
9106
9107 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{
9108
9109 match(Set dst (MoveI2F src));
9110
9111 effect(DEF dst, USE src);
9112
9113 ins_cost(STORE_COST);
9114
9115 format %{ "sw $src, $dst\t#@MoveI2F_reg_stack" %}
9116
9117 ins_encode %{
9118 __ sw(as_Register($src$$reg), Address(sp, $dst$$disp));
9119 %}
9120
9121 ins_pipe(istore_reg_reg);
9122
9123 %}
9124
9125 instruct MoveD2L_reg_stack(stackSlotL dst, fRegD src) %{
9126
9127 match(Set dst (MoveD2L src));
9128
9129 effect(DEF dst, USE src);
9130
9131 ins_cost(STORE_COST);
9132
9133 format %{ "fsd $dst, $src\t#@MoveD2L_reg_stack" %}
9134
9135 ins_encode %{
9136 __ fsd(as_FloatRegister($src$$reg), Address(sp, $dst$$disp));
9137 %}
9138
9139 ins_pipe(fp_store_reg_d);
9140
9141 %}
9142
9143 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{
9144
9145 match(Set dst (MoveL2D src));
9146
9147 effect(DEF dst, USE src);
9148
9149 ins_cost(STORE_COST);
9150
9151 format %{ "sd $src, $dst\t#@MoveL2D_reg_stack" %}
9152
9153 ins_encode %{
9154 __ sd(as_Register($src$$reg), Address(sp, $dst$$disp));
9155 %}
9156
9157 ins_pipe(istore_reg_reg);
9158
9159 %}
9160
9161 instruct MoveF2I_reg_reg(iRegINoSp dst, fRegF src) %{
9162
9163 match(Set dst (MoveF2I src));
9164
9165 effect(DEF dst, USE src);
9166
9167 ins_cost(FMVX_COST);
9168
9169 format %{ "fmv.x.w $dst, $src\t#@MoveF2I_reg_reg" %}
9170
9171 ins_encode %{
9172 __ fmv_x_w(as_Register($dst$$reg), as_FloatRegister($src$$reg));
9173 %}
9174
9175 ins_pipe(fp_f2i);
9176
9177 %}
9178
9179 instruct MoveI2F_reg_reg(fRegF dst, iRegI src) %{
9180
9181 match(Set dst (MoveI2F src));
9182
9183 effect(DEF dst, USE src);
9184
9185 ins_cost(FMVX_COST);
9186
9187 format %{ "fmv.w.x $dst, $src\t#@MoveI2F_reg_reg" %}
9188
9189 ins_encode %{
9190 __ fmv_w_x(as_FloatRegister($dst$$reg), as_Register($src$$reg));
9191 %}
9192
9193 ins_pipe(fp_i2f);
9194
9195 %}
9196
9197 instruct MoveD2L_reg_reg(iRegLNoSp dst, fRegD src) %{
9198
9199 match(Set dst (MoveD2L src));
9200
9201 effect(DEF dst, USE src);
9202
9203 ins_cost(FMVX_COST);
9204
9205 format %{ "fmv.x.d $dst, $src\t#@MoveD2L_reg_reg" %}
9206
9207 ins_encode %{
9208 __ fmv_x_d(as_Register($dst$$reg), as_FloatRegister($src$$reg));
9209 %}
9210
9211 ins_pipe(fp_d2l);
9212
9213 %}
9214
9215 instruct MoveL2D_reg_reg(fRegD dst, iRegL src) %{
9216
9217 match(Set dst (MoveL2D src));
9218
9219 effect(DEF dst, USE src);
9220
9221 ins_cost(FMVX_COST);
9222
9223 format %{ "fmv.d.x $dst, $src\t#@MoveL2D_reg_reg" %}
9224
9225 ins_encode %{
9226 __ fmv_d_x(as_FloatRegister($dst$$reg), as_Register($src$$reg));
9227 %}
9228
9229 ins_pipe(fp_l2d);
9230
9231 %}
9232
9233 // ============================================================================
9234 // Compare Instructions which set the result float comparisons in dest register.
9235
9236 instruct cmpF3_reg_reg(iRegINoSp dst, fRegF op1, fRegF op2)
9237 %{
9238 match(Set dst (CmpF3 op1 op2));
9239
9240 ins_cost(XFER_COST * 2 + BRANCH_COST + ALU_COST);
9241 format %{ "flt.s $dst, $op2, $op1\t#@cmpF3_reg_reg\n\t"
9242 "bgtz $dst, done\n\t"
9243 "feq.s $dst, $op1, $op2\n\t"
9244 "addi $dst, $dst, -1\n\t"
9245 "done:"
9246 %}
9247
9248 ins_encode %{
9249 // we want -1 for unordered or less than, 0 for equal and 1 for greater than.
9250 __ float_compare(as_Register($dst$$reg), as_FloatRegister($op1$$reg),
9251 as_FloatRegister($op2$$reg), -1 /*unordered_result < 0*/);
9252 %}
9253
9254 ins_pipe(pipe_class_default);
9255 %}
9256
9257 instruct cmpD3_reg_reg(iRegINoSp dst, fRegD op1, fRegD op2)
9258 %{
9259 match(Set dst (CmpD3 op1 op2));
9260
9261 ins_cost(XFER_COST * 2 + BRANCH_COST + ALU_COST);
9262 format %{ "flt.d $dst, $op2, $op1\t#@cmpD3_reg_reg\n\t"
9263 "bgtz $dst, done\n\t"
9264 "feq.d $dst, $op1, $op2\n\t"
9265 "addi $dst, $dst, -1\n\t"
9266 "done:"
9267 %}
9268
9269 ins_encode %{
9270 // we want -1 for unordered or less than, 0 for equal and 1 for greater than.
9271 __ double_compare(as_Register($dst$$reg), as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg), -1 /*unordered_result < 0*/);
9272 %}
9273
9274 ins_pipe(pipe_class_default);
9275 %}
9276
9277 instruct cmpL3_reg_reg(iRegINoSp dst, iRegL op1, iRegL op2)
9278 %{
9279 match(Set dst (CmpL3 op1 op2));
9280
9281 ins_cost(ALU_COST * 3 + BRANCH_COST);
9282 format %{ "slt $dst, $op2, $op1\t#@cmpL3_reg_reg\n\t"
9283 "bnez $dst, done\n\t"
9284 "slt $dst, $op1, $op2\n\t"
9285 "neg $dst, $dst\n\t"
9286 "done:"
9287 %}
9288 ins_encode %{
9289 __ cmp_l2i(t0, as_Register($op1$$reg), as_Register($op2$$reg));
9290 __ mv(as_Register($dst$$reg), t0);
9291 %}
9292
9293 ins_pipe(pipe_class_default);
9294 %}
9295
9296 instruct cmpUL3_reg_reg(iRegINoSp dst, iRegL op1, iRegL op2)
9297 %{
9298 match(Set dst (CmpUL3 op1 op2));
9299
9300 ins_cost(ALU_COST * 3 + BRANCH_COST);
9301 format %{ "sltu $dst, $op2, $op1\t#@cmpUL3_reg_reg\n\t"
9302 "bnez $dst, done\n\t"
9303 "sltu $dst, $op1, $op2\n\t"
9304 "neg $dst, $dst\n\t"
9305 "done:"
9306 %}
9307 ins_encode %{
9308 __ cmp_ul2i(t0, as_Register($op1$$reg), as_Register($op2$$reg));
9309 __ mv(as_Register($dst$$reg), t0);
9310 %}
9311
9312 ins_pipe(pipe_class_default);
9313 %}
9314
9315 instruct cmpU3_reg_reg(iRegINoSp dst, iRegI op1, iRegI op2)
9316 %{
9317 match(Set dst (CmpU3 op1 op2));
9318
9319 ins_cost(ALU_COST * 3 + BRANCH_COST);
9320 format %{ "sltu $dst, $op2, $op1\t#@cmpU3_reg_reg\n\t"
9321 "bnez $dst, done\n\t"
9322 "sltu $dst, $op1, $op2\n\t"
9323 "neg $dst, $dst\n\t"
9324 "done:"
9325 %}
9326 ins_encode %{
9327 __ cmp_uw2i(t0, as_Register($op1$$reg), as_Register($op2$$reg));
9328 __ mv(as_Register($dst$$reg), t0);
9329 %}
9330
9331 ins_pipe(pipe_class_default);
9332 %}
9333
9334 instruct cmpLTMask_reg_reg(iRegINoSp dst, iRegI p, iRegI q)
9335 %{
9336 match(Set dst (CmpLTMask p q));
9337
9338 ins_cost(2 * ALU_COST);
9339
9340 format %{ "slt $dst, $p, $q\t#@cmpLTMask_reg_reg\n\t"
9341 "subw $dst, zr, $dst\t#@cmpLTMask_reg_reg"
9342 %}
9343
9344 ins_encode %{
9345 __ slt(as_Register($dst$$reg), as_Register($p$$reg), as_Register($q$$reg));
9346 __ subw(as_Register($dst$$reg), zr, as_Register($dst$$reg));
9347 %}
9348
9349 ins_pipe(ialu_reg_reg);
9350 %}
9351
9352 instruct cmpLTMask_reg_zero(iRegINoSp dst, iRegIorL2I op, immI0 zero)
9353 %{
9354 match(Set dst (CmpLTMask op zero));
9355
9356 ins_cost(ALU_COST);
9357
9358 format %{ "sraiw $dst, $dst, 31\t#@cmpLTMask_reg_reg" %}
9359
9360 ins_encode %{
9361 __ sraiw(as_Register($dst$$reg), as_Register($op$$reg), 31);
9362 %}
9363
9364 ins_pipe(ialu_reg_shift);
9365 %}
9366
9367
9368 // ============================================================================
9369 // Max and Min
9370
9371 instruct minI_reg_reg(iRegINoSp dst, iRegI src)
9372 %{
9373 match(Set dst (MinI dst src));
9374
9375 ins_cost(BRANCH_COST + ALU_COST);
9376 format %{"minI_reg_reg $dst, $dst, $src\t#@minI_reg_reg\n\t"%}
9377
9378 ins_encode %{
9379 __ cmov_gt(as_Register($dst$$reg), as_Register($src$$reg),
9380 as_Register($dst$$reg), as_Register($src$$reg));
9381 %}
9382
9383 ins_pipe(pipe_class_compare);
9384 %}
9385
9386 instruct maxI_reg_reg(iRegINoSp dst, iRegI src)
9387 %{
9388 match(Set dst (MaxI dst src));
9389
9390 ins_cost(BRANCH_COST + ALU_COST);
9391 format %{"maxI_reg_reg $dst, $dst, $src\t#@maxI_reg_reg\n\t"%}
9392
9393 ins_encode %{
9394 __ cmov_lt(as_Register($dst$$reg), as_Register($src$$reg),
9395 as_Register($dst$$reg), as_Register($src$$reg));
9396 %}
9397
9398 ins_pipe(pipe_class_compare);
9399 %}
9400
9401 // special case for comparing with zero
9402 // n.b. this is selected in preference to the rule above because it
9403 // avoids loading constant 0 into a source register
9404
9405 instruct minI_reg_zero(iRegINoSp dst, immI0 zero)
9406 %{
9407 match(Set dst (MinI dst zero));
9408 match(Set dst (MinI zero dst));
9409
9410 ins_cost(BRANCH_COST + ALU_COST);
9411 format %{"minI_reg_zero $dst, $dst, zr\t#@minI_reg_zero\n\t"%}
9412
9413 ins_encode %{
9414 __ cmov_gt(as_Register($dst$$reg), zr,
9415 as_Register($dst$$reg), zr);
9416 %}
9417
9418 ins_pipe(pipe_class_compare);
9419 %}
9420
9421 instruct maxI_reg_zero(iRegINoSp dst, immI0 zero)
9422 %{
9423 match(Set dst (MaxI dst zero));
9424 match(Set dst (MaxI zero dst));
9425
9426 ins_cost(BRANCH_COST + ALU_COST);
9427 format %{"maxI_reg_zero $dst, $dst, zr\t#@maxI_reg_zero\n\t"%}
9428
9429 ins_encode %{
9430 __ cmov_lt(as_Register($dst$$reg), zr,
9431 as_Register($dst$$reg), zr);
9432 %}
9433
9434 ins_pipe(pipe_class_compare);
9435 %}
9436
9437 instruct minI_rReg(iRegINoSp dst, iRegI src1, iRegI src2)
9438 %{
9439 match(Set dst (MinI src1 src2));
9440
9441 effect(DEF dst, USE src1, USE src2);
9442
9443 ins_cost(BRANCH_COST + ALU_COST * 2);
9444 format %{"minI_rReg $dst, $src1, $src2\t#@minI_rReg\n\t"%}
9445
9446 ins_encode %{
9447 __ mv(as_Register($dst$$reg), as_Register($src1$$reg));
9448 __ cmov_gt(as_Register($src1$$reg), as_Register($src2$$reg),
9449 as_Register($dst$$reg), as_Register($src2$$reg));
9450 %}
9451
9452 ins_pipe(pipe_class_compare);
9453 %}
9454
9455 instruct maxI_rReg(iRegINoSp dst, iRegI src1, iRegI src2)
9456 %{
9457 match(Set dst (MaxI src1 src2));
9458
9459 effect(DEF dst, USE src1, USE src2);
9460
9461 ins_cost(BRANCH_COST + ALU_COST * 2);
9462 format %{"maxI_rReg $dst, $src1, $src2\t#@maxI_rReg\n\t"%}
9463
9464 ins_encode %{
9465 __ mv(as_Register($dst$$reg), as_Register($src1$$reg));
9466 __ cmov_lt(as_Register($src1$$reg), as_Register($src2$$reg),
9467 as_Register($dst$$reg), as_Register($src2$$reg));
9468 %}
9469
9470 ins_pipe(pipe_class_compare);
9471 %}
9472
9473 // ============================================================================
9474 // Branch Instructions
9475 // Direct Branch.
9476 instruct branch(label lbl)
9477 %{
9478 match(Goto);
9479
9480 effect(USE lbl);
9481
9482 ins_cost(BRANCH_COST);
9483 format %{ "j $lbl\t#@branch" %}
9484
9485 ins_encode(riscv_enc_j(lbl));
9486
9487 ins_pipe(pipe_branch);
9488 %}
9489
9490 // ============================================================================
9491 // Compare and Branch Instructions
9492
9493 // Patterns for short (< 12KiB) variants
9494
9495 // Compare flags and branch near instructions.
9496 instruct cmpFlag_branch(cmpOpEqNe cmp, rFlagsReg cr, label lbl) %{
9497 match(If cmp cr);
9498 effect(USE lbl);
9499
9500 ins_cost(BRANCH_COST);
9501 format %{ "b$cmp $cr, zr, $lbl\t#@cmpFlag_branch" %}
9502
9503 ins_encode %{
9504 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($cr$$reg), *($lbl$$label));
9505 %}
9506 ins_pipe(pipe_cmpz_branch);
9507 ins_short_branch(1);
9508 %}
9509
9510 // Compare signed int and branch near instructions
9511 instruct cmpI_branch(cmpOp cmp, iRegI op1, iRegI op2, label lbl)
9512 %{
9513 // Same match rule as `far_cmpI_branch'.
9514 match(If cmp (CmpI op1 op2));
9515
9516 effect(USE lbl);
9517
9518 ins_cost(BRANCH_COST);
9519
9520 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpI_branch" %}
9521
9522 ins_encode %{
9523 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label));
9524 %}
9525
9526 ins_pipe(pipe_cmp_branch);
9527 ins_short_branch(1);
9528 %}
9529
9530 instruct cmpI_loop(cmpOp cmp, iRegI op1, iRegI op2, label lbl)
9531 %{
9532 // Same match rule as `far_cmpI_loop'.
9533 match(CountedLoopEnd cmp (CmpI op1 op2));
9534
9535 effect(USE lbl);
9536
9537 ins_cost(BRANCH_COST);
9538
9539 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpI_loop" %}
9540
9541 ins_encode %{
9542 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label));
9543 %}
9544
9545 ins_pipe(pipe_cmp_branch);
9546 ins_short_branch(1);
9547 %}
9548
9549 // Compare unsigned int and branch near instructions
9550 instruct cmpU_branch(cmpOpU cmp, iRegI op1, iRegI op2, label lbl)
9551 %{
9552 // Same match rule as `far_cmpU_branch'.
9553 match(If cmp (CmpU op1 op2));
9554
9555 effect(USE lbl);
9556
9557 ins_cost(BRANCH_COST);
9558
9559 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpU_branch" %}
9560
9561 ins_encode %{
9562 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9563 as_Register($op2$$reg), *($lbl$$label));
9564 %}
9565
9566 ins_pipe(pipe_cmp_branch);
9567 ins_short_branch(1);
9568 %}
9569
9570 // Compare signed long and branch near instructions
9571 instruct cmpL_branch(cmpOp cmp, iRegL op1, iRegL op2, label lbl)
9572 %{
9573 // Same match rule as `far_cmpL_branch'.
9574 match(If cmp (CmpL op1 op2));
9575
9576 effect(USE lbl);
9577
9578 ins_cost(BRANCH_COST);
9579
9580 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpL_branch" %}
9581
9582 ins_encode %{
9583 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label));
9584 %}
9585
9586 ins_pipe(pipe_cmp_branch);
9587 ins_short_branch(1);
9588 %}
9589
9590 instruct cmpL_loop(cmpOp cmp, iRegL op1, iRegL op2, label lbl)
9591 %{
9592 // Same match rule as `far_cmpL_loop'.
9593 match(CountedLoopEnd cmp (CmpL op1 op2));
9594
9595 effect(USE lbl);
9596
9597 ins_cost(BRANCH_COST);
9598
9599 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpL_loop" %}
9600
9601 ins_encode %{
9602 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label));
9603 %}
9604
9605 ins_pipe(pipe_cmp_branch);
9606 ins_short_branch(1);
9607 %}
9608
9609 // Compare unsigned long and branch near instructions
9610 instruct cmpUL_branch(cmpOpU cmp, iRegL op1, iRegL op2, label lbl)
9611 %{
9612 // Same match rule as `far_cmpUL_branch'.
9613 match(If cmp (CmpUL op1 op2));
9614
9615 effect(USE lbl);
9616
9617 ins_cost(BRANCH_COST);
9618 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpUL_branch" %}
9619
9620 ins_encode %{
9621 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9622 as_Register($op2$$reg), *($lbl$$label));
9623 %}
9624
9625 ins_pipe(pipe_cmp_branch);
9626 ins_short_branch(1);
9627 %}
9628
9629 // Compare pointer and branch near instructions
9630 instruct cmpP_branch(cmpOpU cmp, iRegP op1, iRegP op2, label lbl)
9631 %{
9632 // Same match rule as `far_cmpP_branch'.
9633 match(If cmp (CmpP op1 op2));
9634
9635 effect(USE lbl);
9636
9637 ins_cost(BRANCH_COST);
9638
9639 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpP_branch" %}
9640
9641 ins_encode %{
9642 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9643 as_Register($op2$$reg), *($lbl$$label));
9644 %}
9645
9646 ins_pipe(pipe_cmp_branch);
9647 ins_short_branch(1);
9648 %}
9649
9650 // Compare narrow pointer and branch near instructions
9651 instruct cmpN_branch(cmpOpU cmp, iRegN op1, iRegN op2, label lbl)
9652 %{
9653 // Same match rule as `far_cmpN_branch'.
9654 match(If cmp (CmpN op1 op2));
9655
9656 effect(USE lbl);
9657
9658 ins_cost(BRANCH_COST);
9659
9660 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpN_branch" %}
9661
9662 ins_encode %{
9663 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9664 as_Register($op2$$reg), *($lbl$$label));
9665 %}
9666
9667 ins_pipe(pipe_cmp_branch);
9668 ins_short_branch(1);
9669 %}
9670
9671 // Compare float and branch near instructions
9672 instruct cmpF_branch(cmpOp cmp, fRegF op1, fRegF op2, label lbl)
9673 %{
9674 // Same match rule as `far_cmpF_branch'.
9675 match(If cmp (CmpF op1 op2));
9676
9677 effect(USE lbl);
9678
9679 ins_cost(XFER_COST + BRANCH_COST);
9680 format %{ "float_b$cmp $op1, $op2, $lbl \t#@cmpF_branch"%}
9681
9682 ins_encode %{
9683 __ float_cmp_branch($cmp$$cmpcode, as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg), *($lbl$$label));
9684 %}
9685
9686 ins_pipe(pipe_class_compare);
9687 ins_short_branch(1);
9688 %}
9689
9690 // Compare double and branch near instructions
9691 instruct cmpD_branch(cmpOp cmp, fRegD op1, fRegD op2, label lbl)
9692 %{
9693 // Same match rule as `far_cmpD_branch'.
9694 match(If cmp (CmpD op1 op2));
9695 effect(USE lbl);
9696
9697 ins_cost(XFER_COST + BRANCH_COST);
9698 format %{ "double_b$cmp $op1, $op2, $lbl\t#@cmpD_branch"%}
9699
9700 ins_encode %{
9701 __ float_cmp_branch($cmp$$cmpcode | C2_MacroAssembler::double_branch_mask, as_FloatRegister($op1$$reg),
9702 as_FloatRegister($op2$$reg), *($lbl$$label));
9703 %}
9704
9705 ins_pipe(pipe_class_compare);
9706 ins_short_branch(1);
9707 %}
9708
9709 // Compare signed int with zero and branch near instructions
9710 instruct cmpI_reg_imm0_branch(cmpOp cmp, iRegI op1, immI0 zero, label lbl)
9711 %{
9712 // Same match rule as `far_cmpI_reg_imm0_branch'.
9713 match(If cmp (CmpI op1 zero));
9714
9715 effect(USE op1, USE lbl);
9716
9717 ins_cost(BRANCH_COST);
9718 format %{ "b$cmp $op1, zr, $lbl\t#@cmpI_reg_imm0_branch" %}
9719
9720 ins_encode %{
9721 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label));
9722 %}
9723
9724 ins_pipe(pipe_cmpz_branch);
9725 ins_short_branch(1);
9726 %}
9727
9728 instruct cmpI_reg_imm0_loop(cmpOp cmp, iRegI op1, immI0 zero, label lbl)
9729 %{
9730 // Same match rule as `far_cmpI_reg_imm0_loop'.
9731 match(CountedLoopEnd cmp (CmpI op1 zero));
9732
9733 effect(USE op1, USE lbl);
9734
9735 ins_cost(BRANCH_COST);
9736
9737 format %{ "b$cmp $op1, zr, $lbl\t#@cmpI_reg_imm0_loop" %}
9738
9739 ins_encode %{
9740 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label));
9741 %}
9742
9743 ins_pipe(pipe_cmpz_branch);
9744 ins_short_branch(1);
9745 %}
9746
9747 // Compare unsigned int with zero and branch near instructions
9748 instruct cmpUEqNeLeGt_reg_imm0_branch(cmpOpUEqNeLeGt cmp, iRegI op1, immI0 zero, label lbl)
9749 %{
9750 // Same match rule as `far_cmpUEqNeLeGt_reg_imm0_branch'.
9751 match(If cmp (CmpU op1 zero));
9752
9753 effect(USE op1, USE lbl);
9754
9755 ins_cost(BRANCH_COST);
9756
9757 format %{ "b$cmp $op1, zr, $lbl\t#@cmpUEqNeLeGt_reg_imm0_branch" %}
9758
9759 ins_encode %{
9760 __ enc_cmpUEqNeLeGt_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
9761 %}
9762
9763 ins_pipe(pipe_cmpz_branch);
9764 ins_short_branch(1);
9765 %}
9766
9767 // Compare signed long with zero and branch near instructions
9768 instruct cmpL_reg_imm0_branch(cmpOp cmp, iRegL op1, immL0 zero, label lbl)
9769 %{
9770 // Same match rule as `far_cmpL_reg_imm0_branch'.
9771 match(If cmp (CmpL op1 zero));
9772
9773 effect(USE op1, USE lbl);
9774
9775 ins_cost(BRANCH_COST);
9776
9777 format %{ "b$cmp $op1, zr, $lbl\t#@cmpL_reg_imm0_branch" %}
9778
9779 ins_encode %{
9780 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label));
9781 %}
9782
9783 ins_pipe(pipe_cmpz_branch);
9784 ins_short_branch(1);
9785 %}
9786
9787 instruct cmpL_reg_imm0_loop(cmpOp cmp, iRegL op1, immL0 zero, label lbl)
9788 %{
9789 // Same match rule as `far_cmpL_reg_imm0_loop'.
9790 match(CountedLoopEnd cmp (CmpL op1 zero));
9791
9792 effect(USE op1, USE lbl);
9793
9794 ins_cost(BRANCH_COST);
9795
9796 format %{ "b$cmp $op1, zr, $lbl\t#@cmpL_reg_imm0_loop" %}
9797
9798 ins_encode %{
9799 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label));
9800 %}
9801
9802 ins_pipe(pipe_cmpz_branch);
9803 ins_short_branch(1);
9804 %}
9805
9806 // Compare unsigned long with zero and branch near instructions
9807 instruct cmpULEqNeLeGt_reg_imm0_branch(cmpOpUEqNeLeGt cmp, iRegL op1, immL0 zero, label lbl)
9808 %{
9809 // Same match rule as `far_cmpULEqNeLeGt_reg_imm0_branch'.
9810 match(If cmp (CmpUL op1 zero));
9811
9812 effect(USE op1, USE lbl);
9813
9814 ins_cost(BRANCH_COST);
9815
9816 format %{ "b$cmp $op1, zr, $lbl\t#@cmpULEqNeLeGt_reg_imm0_branch" %}
9817
9818 ins_encode %{
9819 __ enc_cmpUEqNeLeGt_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
9820 %}
9821
9822 ins_pipe(pipe_cmpz_branch);
9823 ins_short_branch(1);
9824 %}
9825
9826 // Compare pointer with zero and branch near instructions
9827 instruct cmpP_imm0_branch(cmpOpEqNe cmp, iRegP op1, immP0 zero, label lbl) %{
9828 // Same match rule as `far_cmpP_reg_imm0_branch'.
9829 match(If cmp (CmpP op1 zero));
9830 effect(USE lbl);
9831
9832 ins_cost(BRANCH_COST);
9833 format %{ "b$cmp $op1, zr, $lbl\t#@cmpP_imm0_branch" %}
9834
9835 ins_encode %{
9836 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
9837 %}
9838
9839 ins_pipe(pipe_cmpz_branch);
9840 ins_short_branch(1);
9841 %}
9842
9843 // Compare narrow pointer with zero and branch near instructions
9844 instruct cmpN_imm0_branch(cmpOpEqNe cmp, iRegN op1, immN0 zero, label lbl) %{
9845 // Same match rule as `far_cmpN_reg_imm0_branch'.
9846 match(If cmp (CmpN op1 zero));
9847 effect(USE lbl);
9848
9849 ins_cost(BRANCH_COST);
9850
9851 format %{ "b$cmp $op1, zr, $lbl\t#@cmpN_imm0_branch" %}
9852
9853 ins_encode %{
9854 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
9855 %}
9856
9857 ins_pipe(pipe_cmpz_branch);
9858 ins_short_branch(1);
9859 %}
9860
9861 // Compare narrow pointer with pointer zero and branch near instructions
9862 instruct cmpP_narrowOop_imm0_branch(cmpOpEqNe cmp, iRegN op1, immP0 zero, label lbl) %{
9863 // Same match rule as `far_cmpP_narrowOop_imm0_branch'.
9864 match(If cmp (CmpP (DecodeN op1) zero));
9865 effect(USE lbl);
9866
9867 ins_cost(BRANCH_COST);
9868 format %{ "b$cmp $op1, zr, $lbl\t#@cmpP_narrowOop_imm0_branch" %}
9869
9870 ins_encode %{
9871 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
9872 %}
9873
9874 ins_pipe(pipe_cmpz_branch);
9875 ins_short_branch(1);
9876 %}
9877
9878 // Patterns for far (20KiB) variants
9879
9880 instruct far_cmpFlag_branch(cmpOp cmp, rFlagsReg cr, label lbl) %{
9881 match(If cmp cr);
9882 effect(USE lbl);
9883
9884 ins_cost(BRANCH_COST);
9885 format %{ "far_b$cmp $cr, zr, $lbl\t#@far_cmpFlag_branch"%}
9886
9887 ins_encode %{
9888 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($cr$$reg), *($lbl$$label), /* is_far */ true);
9889 %}
9890
9891 ins_pipe(pipe_cmpz_branch);
9892 %}
9893
9894 // Compare signed int and branch far instructions
9895 instruct far_cmpI_branch(cmpOp cmp, iRegI op1, iRegI op2, label lbl) %{
9896 match(If cmp (CmpI op1 op2));
9897 effect(USE lbl);
9898
9899 ins_cost(BRANCH_COST * 2);
9900
9901 // the format instruction [far_b$cmp] here is be used as two insructions
9902 // in macroassembler: b$not_cmp(op1, op2, done), j($lbl), bind(done)
9903 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpI_branch" %}
9904
9905 ins_encode %{
9906 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9907 %}
9908
9909 ins_pipe(pipe_cmp_branch);
9910 %}
9911
9912 instruct far_cmpI_loop(cmpOp cmp, iRegI op1, iRegI op2, label lbl) %{
9913 match(CountedLoopEnd cmp (CmpI op1 op2));
9914 effect(USE lbl);
9915
9916 ins_cost(BRANCH_COST * 2);
9917 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpI_loop" %}
9918
9919 ins_encode %{
9920 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9921 %}
9922
9923 ins_pipe(pipe_cmp_branch);
9924 %}
9925
9926 instruct far_cmpU_branch(cmpOpU cmp, iRegI op1, iRegI op2, label lbl) %{
9927 match(If cmp (CmpU op1 op2));
9928 effect(USE lbl);
9929
9930 ins_cost(BRANCH_COST * 2);
9931 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpU_branch" %}
9932
9933 ins_encode %{
9934 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9935 as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9936 %}
9937
9938 ins_pipe(pipe_cmp_branch);
9939 %}
9940
9941 instruct far_cmpL_branch(cmpOp cmp, iRegL op1, iRegL op2, label lbl) %{
9942 match(If cmp (CmpL op1 op2));
9943 effect(USE lbl);
9944
9945 ins_cost(BRANCH_COST * 2);
9946 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpL_branch" %}
9947
9948 ins_encode %{
9949 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9950 %}
9951
9952 ins_pipe(pipe_cmp_branch);
9953 %}
9954
9955 instruct far_cmpLloop(cmpOp cmp, iRegL op1, iRegL op2, label lbl) %{
9956 match(CountedLoopEnd cmp (CmpL op1 op2));
9957 effect(USE lbl);
9958
9959 ins_cost(BRANCH_COST * 2);
9960 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpL_loop" %}
9961
9962 ins_encode %{
9963 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9964 %}
9965
9966 ins_pipe(pipe_cmp_branch);
9967 %}
9968
9969 instruct far_cmpUL_branch(cmpOpU cmp, iRegL op1, iRegL op2, label lbl) %{
9970 match(If cmp (CmpUL op1 op2));
9971 effect(USE lbl);
9972
9973 ins_cost(BRANCH_COST * 2);
9974 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpUL_branch" %}
9975
9976 ins_encode %{
9977 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9978 as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9979 %}
9980
9981 ins_pipe(pipe_cmp_branch);
9982 %}
9983
9984 instruct far_cmpP_branch(cmpOpU cmp, iRegP op1, iRegP op2, label lbl)
9985 %{
9986 match(If cmp (CmpP op1 op2));
9987
9988 effect(USE lbl);
9989
9990 ins_cost(BRANCH_COST * 2);
9991
9992 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpP_branch" %}
9993
9994 ins_encode %{
9995 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9996 as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9997 %}
9998
9999 ins_pipe(pipe_cmp_branch);
10000 %}
10001
10002 instruct far_cmpN_branch(cmpOpU cmp, iRegN op1, iRegN op2, label lbl)
10003 %{
10004 match(If cmp (CmpN op1 op2));
10005
10006 effect(USE lbl);
10007
10008 ins_cost(BRANCH_COST * 2);
10009
10010 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpN_branch" %}
10011
10012 ins_encode %{
10013 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
10014 as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
10015 %}
10016
10017 ins_pipe(pipe_cmp_branch);
10018 %}
10019
10020 // Float compare and branch instructions
10021 instruct far_cmpF_branch(cmpOp cmp, fRegF op1, fRegF op2, label lbl)
10022 %{
10023 match(If cmp (CmpF op1 op2));
10024
10025 effect(USE lbl);
10026
10027 ins_cost(XFER_COST + BRANCH_COST * 2);
10028 format %{ "far_float_b$cmp $op1, $op2, $lbl\t#@far_cmpF_branch"%}
10029
10030 ins_encode %{
10031 __ float_cmp_branch($cmp$$cmpcode, as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg),
10032 *($lbl$$label), /* is_far */ true);
10033 %}
10034
10035 ins_pipe(pipe_class_compare);
10036 %}
10037
10038 // Double compare and branch instructions
10039 instruct far_cmpD_branch(cmpOp cmp, fRegD op1, fRegD op2, label lbl)
10040 %{
10041 match(If cmp (CmpD op1 op2));
10042 effect(USE lbl);
10043
10044 ins_cost(XFER_COST + BRANCH_COST * 2);
10045 format %{ "far_double_b$cmp $op1, $op2, $lbl\t#@far_cmpD_branch"%}
10046
10047 ins_encode %{
10048 __ float_cmp_branch($cmp$$cmpcode | C2_MacroAssembler::double_branch_mask, as_FloatRegister($op1$$reg),
10049 as_FloatRegister($op2$$reg), *($lbl$$label), /* is_far */ true);
10050 %}
10051
10052 ins_pipe(pipe_class_compare);
10053 %}
10054
10055 instruct far_cmpI_reg_imm0_branch(cmpOp cmp, iRegI op1, immI0 zero, label lbl)
10056 %{
10057 match(If cmp (CmpI op1 zero));
10058
10059 effect(USE op1, USE lbl);
10060
10061 ins_cost(BRANCH_COST * 2);
10062
10063 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpI_reg_imm0_branch" %}
10064
10065 ins_encode %{
10066 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label), /* is_far */ true);
10067 %}
10068
10069 ins_pipe(pipe_cmpz_branch);
10070 %}
10071
10072 instruct far_cmpI_reg_imm0_loop(cmpOp cmp, iRegI op1, immI0 zero, label lbl)
10073 %{
10074 match(CountedLoopEnd cmp (CmpI op1 zero));
10075
10076 effect(USE op1, USE lbl);
10077
10078 ins_cost(BRANCH_COST * 2);
10079
10080 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpI_reg_imm0_loop" %}
10081
10082 ins_encode %{
10083 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label), /* is_far */ true);
10084 %}
10085
10086 ins_pipe(pipe_cmpz_branch);
10087 %}
10088
10089 instruct far_cmpUEqNeLeGt_imm0_branch(cmpOpUEqNeLeGt cmp, iRegI op1, immI0 zero, label lbl)
10090 %{
10091 match(If cmp (CmpU op1 zero));
10092
10093 effect(USE op1, USE lbl);
10094
10095 ins_cost(BRANCH_COST * 2);
10096
10097 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpUEqNeLeGt_imm0_branch" %}
10098
10099 ins_encode %{
10100 __ enc_cmpUEqNeLeGt_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
10101 %}
10102
10103 ins_pipe(pipe_cmpz_branch);
10104 %}
10105
10106 // compare lt/ge unsigned instructs has no short instruct with same match
10107 instruct far_cmpULtGe_reg_imm0_branch(cmpOpULtGe cmp, iRegI op1, immI0 zero, label lbl)
10108 %{
10109 match(If cmp (CmpU op1 zero));
10110
10111 effect(USE op1, USE lbl);
10112
10113 ins_cost(BRANCH_COST);
10114
10115 format %{ "j $lbl if $cmp == ge\t#@far_cmpULtGe_reg_imm0_branch" %}
10116
10117 ins_encode(riscv_enc_far_cmpULtGe_imm0_branch(cmp, op1, lbl));
10118
10119 ins_pipe(pipe_cmpz_branch);
10120 %}
10121
10122 instruct far_cmpL_reg_imm0_branch(cmpOp cmp, iRegL op1, immL0 zero, label lbl)
10123 %{
10124 match(If cmp (CmpL op1 zero));
10125
10126 effect(USE op1, USE lbl);
10127
10128 ins_cost(BRANCH_COST * 2);
10129
10130 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpL_reg_imm0_branch" %}
10131
10132 ins_encode %{
10133 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label), /* is_far */ true);
10134 %}
10135
10136 ins_pipe(pipe_cmpz_branch);
10137 %}
10138
10139 instruct far_cmpL_reg_imm0_loop(cmpOp cmp, iRegL op1, immL0 zero, label lbl)
10140 %{
10141 match(CountedLoopEnd cmp (CmpL op1 zero));
10142
10143 effect(USE op1, USE lbl);
10144
10145 ins_cost(BRANCH_COST * 2);
10146
10147 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpL_reg_imm0_loop" %}
10148
10149 ins_encode %{
10150 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label), /* is_far */ true);
10151 %}
10152
10153 ins_pipe(pipe_cmpz_branch);
10154 %}
10155
10156 instruct far_cmpULEqNeLeGt_reg_imm0_branch(cmpOpUEqNeLeGt cmp, iRegL op1, immL0 zero, label lbl)
10157 %{
10158 match(If cmp (CmpUL op1 zero));
10159
10160 effect(USE op1, USE lbl);
10161
10162 ins_cost(BRANCH_COST * 2);
10163
10164 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpULEqNeLeGt_reg_imm0_branch" %}
10165
10166 ins_encode %{
10167 __ enc_cmpUEqNeLeGt_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
10168 %}
10169
10170 ins_pipe(pipe_cmpz_branch);
10171 %}
10172
10173 // compare lt/ge unsigned instructs has no short instruct with same match
10174 instruct far_cmpULLtGe_reg_imm0_branch(cmpOpULtGe cmp, iRegL op1, immL0 zero, label lbl)
10175 %{
10176 match(If cmp (CmpUL op1 zero));
10177
10178 effect(USE op1, USE lbl);
10179
10180 ins_cost(BRANCH_COST);
10181
10182 format %{ "j $lbl if $cmp == ge\t#@far_cmpULLtGe_reg_imm0_branch" %}
10183
10184 ins_encode(riscv_enc_far_cmpULtGe_imm0_branch(cmp, op1, lbl));
10185
10186 ins_pipe(pipe_cmpz_branch);
10187 %}
10188
10189 instruct far_cmpP_imm0_branch(cmpOpEqNe cmp, iRegP op1, immP0 zero, label lbl) %{
10190 match(If cmp (CmpP op1 zero));
10191 effect(USE lbl);
10192
10193 ins_cost(BRANCH_COST * 2);
10194 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpP_imm0_branch" %}
10195
10196 ins_encode %{
10197 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
10198 %}
10199
10200 ins_pipe(pipe_cmpz_branch);
10201 %}
10202
10203 instruct far_cmpN_imm0_branch(cmpOpEqNe cmp, iRegN op1, immN0 zero, label lbl) %{
10204 match(If cmp (CmpN op1 zero));
10205 effect(USE lbl);
10206
10207 ins_cost(BRANCH_COST * 2);
10208
10209 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpN_imm0_branch" %}
10210
10211 ins_encode %{
10212 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
10213 %}
10214
10215 ins_pipe(pipe_cmpz_branch);
10216 %}
10217
10218 instruct far_cmpP_narrowOop_imm0_branch(cmpOpEqNe cmp, iRegN op1, immP0 zero, label lbl) %{
10219 match(If cmp (CmpP (DecodeN op1) zero));
10220 effect(USE lbl);
10221
10222 ins_cost(BRANCH_COST * 2);
10223 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpP_narrowOop_imm0_branch" %}
10224
10225 ins_encode %{
10226 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
10227 %}
10228
10229 ins_pipe(pipe_cmpz_branch);
10230 %}
10231
10232 // ============================================================================
10233 // Conditional Move Instructions
10234
10235 // --------- CMoveI ---------
10236
10237 instruct cmovI_cmpI(iRegINoSp dst, iRegI src, iRegI op1, iRegI op2, cmpOp cop) %{
10238 match(Set dst (CMoveI (Binary cop (CmpI op1 op2)) (Binary dst src)));
10239 ins_cost(ALU_COST + BRANCH_COST);
10240
10241 format %{
10242 "CMoveI $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpI\n\t"
10243 %}
10244
10245 ins_encode %{
10246 __ enc_cmove($cop$$cmpcode,
10247 as_Register($op1$$reg), as_Register($op2$$reg),
10248 as_Register($dst$$reg), as_Register($src$$reg));
10249 %}
10250
10251 ins_pipe(pipe_class_compare);
10252 %}
10253
10254 instruct cmovI_cmpU(iRegINoSp dst, iRegI src, iRegI op1, iRegI op2, cmpOpU cop) %{
10255 match(Set dst (CMoveI (Binary cop (CmpU op1 op2)) (Binary dst src)));
10256 ins_cost(ALU_COST + BRANCH_COST);
10257
10258 format %{
10259 "CMoveI $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpU\n\t"
10260 %}
10261
10262 ins_encode %{
10263 __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10264 as_Register($op1$$reg), as_Register($op2$$reg),
10265 as_Register($dst$$reg), as_Register($src$$reg));
10266 %}
10267
10268 ins_pipe(pipe_class_compare);
10269 %}
10270
10271 instruct cmovI_cmpL(iRegINoSp dst, iRegI src, iRegL op1, iRegL op2, cmpOp cop) %{
10272 match(Set dst (CMoveI (Binary cop (CmpL op1 op2)) (Binary dst src)));
10273 ins_cost(ALU_COST + BRANCH_COST);
10274
10275 format %{
10276 "CMoveI $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpL\n\t"
10277 %}
10278
10279 ins_encode %{
10280 __ enc_cmove($cop$$cmpcode,
10281 as_Register($op1$$reg), as_Register($op2$$reg),
10282 as_Register($dst$$reg), as_Register($src$$reg));
10283 %}
10284
10285 ins_pipe(pipe_class_compare);
10286 %}
10287
10288 instruct cmovI_cmpUL(iRegINoSp dst, iRegI src, iRegL op1, iRegL op2, cmpOpU cop) %{
10289 match(Set dst (CMoveI (Binary cop (CmpUL op1 op2)) (Binary dst src)));
10290 ins_cost(ALU_COST + BRANCH_COST);
10291
10292 format %{
10293 "CMoveI $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpUL\n\t"
10294 %}
10295
10296 ins_encode %{
10297 __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10298 as_Register($op1$$reg), as_Register($op2$$reg),
10299 as_Register($dst$$reg), as_Register($src$$reg));
10300 %}
10301
10302 ins_pipe(pipe_class_compare);
10303 %}
10304
10305 instruct cmovI_cmpF(iRegINoSp dst, iRegI src, fRegF op1, fRegF op2, cmpOp cop) %{
10306 match(Set dst (CMoveI (Binary cop (CmpF op1 op2)) (Binary dst src)));
10307 ins_cost(ALU_COST + BRANCH_COST);
10308
10309 format %{
10310 "CMoveI $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpF\n\t"
10311 %}
10312
10313 ins_encode %{
10314 __ enc_cmove_cmp_fp($cop$$cmpcode,
10315 as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg),
10316 as_Register($dst$$reg), as_Register($src$$reg), true /* is_single */);
10317 %}
10318
10319 ins_pipe(pipe_class_compare);
10320 %}
10321
10322 instruct cmovI_cmpD(iRegINoSp dst, iRegI src, fRegD op1, fRegD op2, cmpOp cop) %{
10323 match(Set dst (CMoveI (Binary cop (CmpD op1 op2)) (Binary dst src)));
10324 ins_cost(ALU_COST + BRANCH_COST);
10325
10326 format %{
10327 "CMoveI $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpD\n\t"
10328 %}
10329
10330 ins_encode %{
10331 __ enc_cmove_cmp_fp($cop$$cmpcode | C2_MacroAssembler::double_branch_mask,
10332 as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg),
10333 as_Register($dst$$reg), as_Register($src$$reg), false /* is_single */);
10334 %}
10335
10336 ins_pipe(pipe_class_compare);
10337 %}
10338
10339 instruct cmovI_cmpN(iRegINoSp dst, iRegI src, iRegN op1, iRegN op2, cmpOpU cop) %{
10340 match(Set dst (CMoveI (Binary cop (CmpN op1 op2)) (Binary dst src)));
10341 ins_cost(ALU_COST + BRANCH_COST);
10342
10343 format %{
10344 "CMoveI $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpN\n\t"
10345 %}
10346
10347 ins_encode %{
10348 __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10349 as_Register($op1$$reg), as_Register($op2$$reg),
10350 as_Register($dst$$reg), as_Register($src$$reg));
10351 %}
10352
10353 ins_pipe(pipe_class_compare);
10354 %}
10355
10356 instruct cmovI_cmpP(iRegINoSp dst, iRegI src, iRegP op1, iRegP op2, cmpOpU cop) %{
10357 match(Set dst (CMoveI (Binary cop (CmpP op1 op2)) (Binary dst src)));
10358 ins_cost(ALU_COST + BRANCH_COST);
10359
10360 format %{
10361 "CMoveI $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpP\n\t"
10362 %}
10363
10364 ins_encode %{
10365 __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10366 as_Register($op1$$reg), as_Register($op2$$reg),
10367 as_Register($dst$$reg), as_Register($src$$reg));
10368 %}
10369
10370 ins_pipe(pipe_class_compare);
10371 %}
10372
10373 // --------- CMoveL ---------
10374
10375 instruct cmovL_cmpL(iRegLNoSp dst, iRegL src, iRegL op1, iRegL op2, cmpOp cop) %{
10376 match(Set dst (CMoveL (Binary cop (CmpL op1 op2)) (Binary dst src)));
10377 ins_cost(ALU_COST + BRANCH_COST);
10378
10379 format %{
10380 "CMoveL $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpL\n\t"
10381 %}
10382
10383 ins_encode %{
10384 __ enc_cmove($cop$$cmpcode,
10385 as_Register($op1$$reg), as_Register($op2$$reg),
10386 as_Register($dst$$reg), as_Register($src$$reg));
10387 %}
10388
10389 ins_pipe(pipe_class_compare);
10390 %}
10391
10392 instruct cmovL_cmpUL(iRegLNoSp dst, iRegL src, iRegL op1, iRegL op2, cmpOpU cop) %{
10393 match(Set dst (CMoveL (Binary cop (CmpUL op1 op2)) (Binary dst src)));
10394 ins_cost(ALU_COST + BRANCH_COST);
10395
10396 format %{
10397 "CMoveL $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpUL\n\t"
10398 %}
10399
10400 ins_encode %{
10401 __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10402 as_Register($op1$$reg), as_Register($op2$$reg),
10403 as_Register($dst$$reg), as_Register($src$$reg));
10404 %}
10405
10406 ins_pipe(pipe_class_compare);
10407 %}
10408
10409 instruct cmovL_cmpI(iRegLNoSp dst, iRegL src, iRegI op1, iRegI op2, cmpOp cop) %{
10410 match(Set dst (CMoveL (Binary cop (CmpI op1 op2)) (Binary dst src)));
10411 ins_cost(ALU_COST + BRANCH_COST);
10412
10413 format %{
10414 "CMoveL $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpI\n\t"
10415 %}
10416
10417 ins_encode %{
10418 __ enc_cmove($cop$$cmpcode,
10419 as_Register($op1$$reg), as_Register($op2$$reg),
10420 as_Register($dst$$reg), as_Register($src$$reg));
10421 %}
10422
10423 ins_pipe(pipe_class_compare);
10424 %}
10425
10426 instruct cmovL_cmpU(iRegLNoSp dst, iRegL src, iRegI op1, iRegI op2, cmpOpU cop) %{
10427 match(Set dst (CMoveL (Binary cop (CmpU op1 op2)) (Binary dst src)));
10428 ins_cost(ALU_COST + BRANCH_COST);
10429
10430 format %{
10431 "CMoveL $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpU\n\t"
10432 %}
10433
10434 ins_encode %{
10435 __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10436 as_Register($op1$$reg), as_Register($op2$$reg),
10437 as_Register($dst$$reg), as_Register($src$$reg));
10438 %}
10439
10440 ins_pipe(pipe_class_compare);
10441 %}
10442
10443 instruct cmovL_cmpF(iRegLNoSp dst, iRegL src, fRegF op1, fRegF op2, cmpOp cop) %{
10444 match(Set dst (CMoveL (Binary cop (CmpF op1 op2)) (Binary dst src)));
10445 ins_cost(ALU_COST + BRANCH_COST);
10446
10447 format %{
10448 "CMoveL $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpF\n\t"
10449 %}
10450
10451 ins_encode %{
10452 __ enc_cmove_cmp_fp($cop$$cmpcode,
10453 as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg),
10454 as_Register($dst$$reg), as_Register($src$$reg), true /* is_single */);
10455 %}
10456
10457 ins_pipe(pipe_class_compare);
10458 %}
10459
10460 instruct cmovL_cmpD(iRegLNoSp dst, iRegL src, fRegD op1, fRegD op2, cmpOp cop) %{
10461 match(Set dst (CMoveL (Binary cop (CmpD op1 op2)) (Binary dst src)));
10462 ins_cost(ALU_COST + BRANCH_COST);
10463
10464 format %{
10465 "CMoveL $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpD\n\t"
10466 %}
10467
10468 ins_encode %{
10469 __ enc_cmove_cmp_fp($cop$$cmpcode | C2_MacroAssembler::double_branch_mask,
10470 as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg),
10471 as_Register($dst$$reg), as_Register($src$$reg), false /* is_single */);
10472 %}
10473
10474 ins_pipe(pipe_class_compare);
10475 %}
10476
10477 instruct cmovL_cmpN(iRegLNoSp dst, iRegL src, iRegN op1, iRegN op2, cmpOpU cop) %{
10478 match(Set dst (CMoveL (Binary cop (CmpN op1 op2)) (Binary dst src)));
10479 ins_cost(ALU_COST + BRANCH_COST);
10480
10481 format %{
10482 "CMoveL $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpN\n\t"
10483 %}
10484
10485 ins_encode %{
10486 __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10487 as_Register($op1$$reg), as_Register($op2$$reg),
10488 as_Register($dst$$reg), as_Register($src$$reg));
10489 %}
10490
10491 ins_pipe(pipe_class_compare);
10492 %}
10493
10494 instruct cmovL_cmpP(iRegLNoSp dst, iRegL src, iRegP op1, iRegP op2, cmpOpU cop) %{
10495 match(Set dst (CMoveL (Binary cop (CmpP op1 op2)) (Binary dst src)));
10496 ins_cost(ALU_COST + BRANCH_COST);
10497
10498 format %{
10499 "CMoveL $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpP\n\t"
10500 %}
10501
10502 ins_encode %{
10503 __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10504 as_Register($op1$$reg), as_Register($op2$$reg),
10505 as_Register($dst$$reg), as_Register($src$$reg));
10506 %}
10507
10508 ins_pipe(pipe_class_compare);
10509 %}
10510
10511 // --------- CMoveF ---------
10512
10513 instruct cmovF_cmpI(fRegF dst, fRegF src, iRegI op1, iRegI op2, cmpOp cop) %{
10514 match(Set dst (CMoveF (Binary cop (CmpI op1 op2)) (Binary dst src)));
10515 ins_cost(ALU_COST + BRANCH_COST);
10516
10517 format %{
10518 "CMoveF $dst, ($op1 $cop $op2), $dst, $src\t#@cmovF_cmpI\n\t"
10519 %}
10520
10521 ins_encode %{
10522 __ enc_cmove_fp_cmp($cop$$cmpcode,
10523 as_Register($op1$$reg), as_Register($op2$$reg),
10524 as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg), true /* is_single */);
10525 %}
10526
10527 ins_pipe(pipe_class_compare);
10528 %}
10529
10530 instruct cmovF_cmpU(fRegF dst, fRegF src, iRegI op1, iRegI op2, cmpOpU cop) %{
10531 match(Set dst (CMoveF (Binary cop (CmpU op1 op2)) (Binary dst src)));
10532 ins_cost(ALU_COST + BRANCH_COST);
10533
10534 format %{
10535 "CMoveF $dst, ($op1 $cop $op2), $dst, $src\t#@cmovF_cmpU\n\t"
10536 %}
10537
10538 ins_encode %{
10539 __ enc_cmove_fp_cmp($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10540 as_Register($op1$$reg), as_Register($op2$$reg),
10541 as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg), true /* is_single */);
10542 %}
10543
10544 ins_pipe(pipe_class_compare);
10545 %}
10546
10547 instruct cmovF_cmpL(fRegF dst, fRegF src, iRegL op1, iRegL op2, cmpOp cop) %{
10548 match(Set dst (CMoveF (Binary cop (CmpL op1 op2)) (Binary dst src)));
10549 ins_cost(ALU_COST + BRANCH_COST);
10550
10551 format %{
10552 "CMoveF $dst, ($op1 $cop $op2), $dst, $src\t#@cmovF_cmpL\n\t"
10553 %}
10554
10555 ins_encode %{
10556 __ enc_cmove_fp_cmp($cop$$cmpcode,
10557 as_Register($op1$$reg), as_Register($op2$$reg),
10558 as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg), true /* is_single */);
10559 %}
10560
10561 ins_pipe(pipe_class_compare);
10562 %}
10563
10564 instruct cmovF_cmpUL(fRegF dst, fRegF src, iRegL op1, iRegL op2, cmpOpU cop) %{
10565 match(Set dst (CMoveF (Binary cop (CmpUL op1 op2)) (Binary dst src)));
10566 ins_cost(ALU_COST + BRANCH_COST);
10567
10568 format %{
10569 "CMoveF $dst, ($op1 $cop $op2), $dst, $src\t#@cmovF_cmpUL\n\t"
10570 %}
10571
10572 ins_encode %{
10573 __ enc_cmove_fp_cmp($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10574 as_Register($op1$$reg), as_Register($op2$$reg),
10575 as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg), true /* is_single */);
10576 %}
10577
10578 ins_pipe(pipe_class_compare);
10579 %}
10580
10581 instruct cmovF_cmpF(fRegF dst, fRegF src, fRegF op1, fRegF op2, cmpOp cop) %{
10582 match(Set dst (CMoveF (Binary cop (CmpF op1 op2)) (Binary dst src)));
10583 ins_cost(ALU_COST + BRANCH_COST);
10584
10585 format %{
10586 "CMoveF $dst, ($op1 $cop $op2), $dst, $src\t#@cmovF_cmpF\n\t"
10587 %}
10588
10589 ins_encode %{
10590 __ enc_cmove_fp_cmp_fp($cop$$cmpcode,
10591 as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg),
10592 as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg),
10593 true /* cmp_single */, true /* cmov_single */);
10594 %}
10595
10596 ins_pipe(pipe_class_compare);
10597 %}
10598
10599 instruct cmovF_cmpD(fRegF dst, fRegF src, fRegD op1, fRegD op2, cmpOp cop) %{
10600 match(Set dst (CMoveF (Binary cop (CmpD op1 op2)) (Binary dst src)));
10601 ins_cost(ALU_COST + BRANCH_COST);
10602
10603 format %{
10604 "CMoveF $dst, ($op1 $cop $op2), $dst, $src\t#@cmovF_cmpD\n\t"
10605 %}
10606
10607 ins_encode %{
10608 __ enc_cmove_fp_cmp_fp($cop$$cmpcode | C2_MacroAssembler::double_branch_mask,
10609 as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg),
10610 as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg),
10611 false /* cmp_single */, true /* cmov_single */);
10612 %}
10613
10614 ins_pipe(pipe_class_compare);
10615 %}
10616
10617 instruct cmovF_cmpN(fRegF dst, fRegF src, iRegN op1, iRegN op2, cmpOp cop) %{
10618 match(Set dst (CMoveF (Binary cop (CmpN op1 op2)) (Binary dst src)));
10619 ins_cost(ALU_COST + BRANCH_COST);
10620
10621 format %{
10622 "CMoveF $dst, ($op1 $cop $op2), $dst, $src\t#@cmovF_cmpN\n\t"
10623 %}
10624
10625 ins_encode %{
10626 __ enc_cmove_fp_cmp($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10627 as_Register($op1$$reg), as_Register($op2$$reg),
10628 as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg), true /* is_single */);
10629 %}
10630
10631 ins_pipe(pipe_class_compare);
10632 %}
10633
10634 instruct cmovF_cmpP(fRegF dst, fRegF src, iRegP op1, iRegP op2, cmpOp cop) %{
10635 match(Set dst (CMoveF (Binary cop (CmpP op1 op2)) (Binary dst src)));
10636 ins_cost(ALU_COST + BRANCH_COST);
10637
10638 format %{
10639 "CMoveF $dst, ($op1 $cop $op2), $dst, $src\t#@cmovF_cmpP\n\t"
10640 %}
10641
10642 ins_encode %{
10643 __ enc_cmove_fp_cmp($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10644 as_Register($op1$$reg), as_Register($op2$$reg),
10645 as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg), true /* is_single */);
10646 %}
10647
10648 ins_pipe(pipe_class_compare);
10649 %}
10650
10651 // --------- CMoveD ---------
10652
10653 instruct cmovD_cmpI(fRegD dst, fRegD src, iRegI op1, iRegI op2, cmpOp cop) %{
10654 match(Set dst (CMoveD (Binary cop (CmpI op1 op2)) (Binary dst src)));
10655 ins_cost(ALU_COST + BRANCH_COST);
10656
10657 format %{
10658 "CMoveD $dst, ($op1 $cop $op2), $dst, $src\t#@cmovD_cmpI\n\t"
10659 %}
10660
10661 ins_encode %{
10662 __ enc_cmove_fp_cmp($cop$$cmpcode,
10663 as_Register($op1$$reg), as_Register($op2$$reg),
10664 as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg), false /* is_single */);
10665 %}
10666
10667 ins_pipe(pipe_class_compare);
10668 %}
10669
10670 instruct cmovD_cmpU(fRegD dst, fRegD src, iRegI op1, iRegI op2, cmpOpU cop) %{
10671 match(Set dst (CMoveD (Binary cop (CmpU op1 op2)) (Binary dst src)));
10672 ins_cost(ALU_COST + BRANCH_COST);
10673
10674 format %{
10675 "CMoveD $dst, ($op1 $cop $op2), $dst, $src\t#@cmovD_cmpU\n\t"
10676 %}
10677
10678 ins_encode %{
10679 __ enc_cmove_fp_cmp($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10680 as_Register($op1$$reg), as_Register($op2$$reg),
10681 as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg), false /* is_single */);
10682 %}
10683
10684 ins_pipe(pipe_class_compare);
10685 %}
10686
10687 instruct cmovD_cmpL(fRegD dst, fRegD src, iRegL op1, iRegL op2, cmpOp cop) %{
10688 match(Set dst (CMoveD (Binary cop (CmpL op1 op2)) (Binary dst src)));
10689 ins_cost(ALU_COST + BRANCH_COST);
10690
10691 format %{
10692 "CMoveD $dst, ($op1 $cop $op2), $dst, $src\t#@cmovD_cmpL\n\t"
10693 %}
10694
10695 ins_encode %{
10696 __ enc_cmove_fp_cmp($cop$$cmpcode,
10697 as_Register($op1$$reg), as_Register($op2$$reg),
10698 as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg), false /* is_single */);
10699 %}
10700
10701 ins_pipe(pipe_class_compare);
10702 %}
10703
10704 instruct cmovD_cmpUL(fRegD dst, fRegD src, iRegL op1, iRegL op2, cmpOpU cop) %{
10705 match(Set dst (CMoveD (Binary cop (CmpUL op1 op2)) (Binary dst src)));
10706 ins_cost(ALU_COST + BRANCH_COST);
10707
10708 format %{
10709 "CMoveD $dst, ($op1 $cop $op2), $dst, $src\t#@cmovD_cmpUL\n\t"
10710 %}
10711
10712 ins_encode %{
10713 __ enc_cmove_fp_cmp($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10714 as_Register($op1$$reg), as_Register($op2$$reg),
10715 as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg), false /* is_single */);
10716 %}
10717
10718 ins_pipe(pipe_class_compare);
10719 %}
10720
10721 instruct cmovD_cmpF(fRegD dst, fRegD src, fRegF op1, fRegF op2, cmpOp cop) %{
10722 match(Set dst (CMoveD (Binary cop (CmpF op1 op2)) (Binary dst src)));
10723 ins_cost(ALU_COST + BRANCH_COST);
10724
10725 format %{
10726 "CMoveD $dst, ($op1 $cop $op2), $dst, $src\t#@cmovD_cmpF\n\t"
10727 %}
10728
10729 ins_encode %{
10730 __ enc_cmove_fp_cmp_fp($cop$$cmpcode,
10731 as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg),
10732 as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg),
10733 true /* cmp_single */, false /* cmov_single */);
10734 %}
10735
10736 ins_pipe(pipe_class_compare);
10737 %}
10738
10739 instruct cmovD_cmpD(fRegD dst, fRegD src, fRegD op1, fRegD op2, cmpOp cop) %{
10740 match(Set dst (CMoveD (Binary cop (CmpD op1 op2)) (Binary dst src)));
10741 ins_cost(ALU_COST + BRANCH_COST);
10742
10743 format %{
10744 "CMoveD $dst, ($op1 $cop $op2), $dst, $src\t#@cmovD_cmpD\n\t"
10745 %}
10746
10747 ins_encode %{
10748 __ enc_cmove_fp_cmp_fp($cop$$cmpcode | C2_MacroAssembler::double_branch_mask,
10749 as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg),
10750 as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg),
10751 false /* cmp_single */, false /* cmov_single */);
10752 %}
10753
10754 ins_pipe(pipe_class_compare);
10755 %}
10756
10757 instruct cmovD_cmpN(fRegD dst, fRegD src, iRegN op1, iRegN op2, cmpOp cop) %{
10758 match(Set dst (CMoveD (Binary cop (CmpN op1 op2)) (Binary dst src)));
10759 ins_cost(ALU_COST + BRANCH_COST);
10760
10761 format %{
10762 "CMoveD $dst, ($op1 $cop $op2), $dst, $src\t#@cmovD_cmpN\n\t"
10763 %}
10764
10765 ins_encode %{
10766 __ enc_cmove_fp_cmp($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10767 as_Register($op1$$reg), as_Register($op2$$reg),
10768 as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg), false /* is_single */);
10769 %}
10770
10771 ins_pipe(pipe_class_compare);
10772 %}
10773
10774 instruct cmovD_cmpP(fRegD dst, fRegD src, iRegP op1, iRegP op2, cmpOp cop) %{
10775 match(Set dst (CMoveD (Binary cop (CmpP op1 op2)) (Binary dst src)));
10776 ins_cost(ALU_COST + BRANCH_COST);
10777
10778 format %{
10779 "CMoveD $dst, ($op1 $cop $op2), $dst, $src\t#@cmovD_cmpP\n\t"
10780 %}
10781
10782 ins_encode %{
10783 __ enc_cmove_fp_cmp($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10784 as_Register($op1$$reg), as_Register($op2$$reg),
10785 as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg), false /* is_single */);
10786 %}
10787
10788 ins_pipe(pipe_class_compare);
10789 %}
10790
10791 // ============================================================================
10792 // Procedure Call/Return Instructions
10793
10794 // Call Java Static Instruction
10795 // Note: If this code changes, the corresponding ret_addr_offset() and
10796 // compute_padding() functions will have to be adjusted.
10797 instruct CallStaticJavaDirect(method meth)
10798 %{
10799 match(CallStaticJava);
10800
10801 effect(USE meth);
10802
10803 ins_cost(BRANCH_COST);
10804
10805 format %{ "CALL,static $meth\t#@CallStaticJavaDirect" %}
10806
10807 ins_encode(riscv_enc_java_static_call(meth),
10808 riscv_enc_call_epilog);
10809
10810 ins_pipe(pipe_class_call);
10811 ins_alignment(4);
10812 %}
10813
10814 // TO HERE
10815
10816 // Call Java Dynamic Instruction
10817 // Note: If this code changes, the corresponding ret_addr_offset() and
10818 // compute_padding() functions will have to be adjusted.
10819 instruct CallDynamicJavaDirect(method meth)
10820 %{
10821 match(CallDynamicJava);
10822
10823 effect(USE meth);
10824
10825 ins_cost(BRANCH_COST + ALU_COST * 5);
10826
10827 format %{ "CALL,dynamic $meth\t#@CallDynamicJavaDirect" %}
10828
10829 ins_encode(riscv_enc_java_dynamic_call(meth),
10830 riscv_enc_call_epilog);
10831
10832 ins_pipe(pipe_class_call);
10833 ins_alignment(4);
10834 %}
10835
10836 // Call Runtime Instruction
10837
10838 instruct CallRuntimeDirect(method meth)
10839 %{
10840 match(CallRuntime);
10841
10842 effect(USE meth);
10843
10844 ins_cost(BRANCH_COST);
10845
10846 format %{ "CALL, runtime $meth\t#@CallRuntimeDirect" %}
10847
10848 ins_encode(riscv_enc_java_to_runtime(meth));
10849
10850 ins_pipe(pipe_class_call);
10851 ins_alignment(4);
10852 %}
10853
10854 // Call Runtime Instruction
10855
10856 instruct CallLeafDirect(method meth)
10857 %{
10858 match(CallLeaf);
10859
10860 effect(USE meth);
10861
10862 ins_cost(BRANCH_COST);
10863
10864 format %{ "CALL, runtime leaf $meth\t#@CallLeafDirect" %}
10865
10866 ins_encode(riscv_enc_java_to_runtime(meth));
10867
10868 ins_pipe(pipe_class_call);
10869 ins_alignment(4);
10870 %}
10871
10872 // Call Runtime Instruction without safepoint and with vector arguments
10873
10874 instruct CallLeafDirectVector(method meth)
10875 %{
10876 match(CallLeafVector);
10877
10878 effect(USE meth);
10879
10880 ins_cost(BRANCH_COST);
10881
10882 format %{ "CALL, runtime leaf vector $meth" %}
10883
10884 ins_encode(riscv_enc_java_to_runtime(meth));
10885
10886 ins_pipe(pipe_class_call);
10887 ins_alignment(4);
10888 %}
10889
10890 // Call Runtime Instruction
10891
10892 instruct CallLeafNoFPDirect(method meth)
10893 %{
10894 match(CallLeafNoFP);
10895
10896 effect(USE meth);
10897
10898 ins_cost(BRANCH_COST);
10899
10900 format %{ "CALL, runtime leaf nofp $meth\t#@CallLeafNoFPDirect" %}
10901
10902 ins_encode(riscv_enc_java_to_runtime(meth));
10903
10904 ins_pipe(pipe_class_call);
10905 ins_alignment(4);
10906 %}
10907
10908 // ============================================================================
10909 // Partial Subtype Check
10910 //
10911 // superklass array for an instance of the superklass. Set a hidden
10912 // internal cache on a hit (cache is checked with exposed code in
10913 // gen_subtype_check()). Return zero for a hit. The encoding
10914 // ALSO sets flags.
10915
10916 instruct partialSubtypeCheck(iRegP_R15 result, iRegP_R14 sub, iRegP_R10 super, iRegP_R12 tmp, rFlagsReg cr)
10917 %{
10918 predicate(!UseSecondarySupersTable);
10919 match(Set result (PartialSubtypeCheck sub super));
10920 effect(KILL tmp, KILL cr);
10921
10922 ins_cost(20 * DEFAULT_COST);
10923 format %{ "partialSubtypeCheck $result, $sub, $super\t#@partialSubtypeCheck" %}
10924
10925 ins_encode(riscv_enc_partial_subtype_check(sub, super, tmp, result));
10926
10927 opcode(0x1); // Force zero of result reg on hit
10928
10929 ins_pipe(pipe_class_memory);
10930 %}
10931
10932 // Two versions of partialSubtypeCheck, both used when we need to
10933 // search for a super class in the secondary supers array. The first
10934 // is used when we don't know _a priori_ the class being searched
10935 // for. The second, far more common, is used when we do know: this is
10936 // used for instanceof, checkcast, and any case where C2 can determine
10937 // it by constant propagation.
10938
10939 instruct partialSubtypeCheckVarSuper(iRegP_R14 sub, iRegP_R10 super, iRegP_R15 result,
10940 iRegP_R11 tmpR11, iRegP_R12 tmpR12, iRegP_R13 tmpR13,
10941 iRegP_R16 tmpR16, rFlagsReg cr)
10942 %{
10943 predicate(UseSecondarySupersTable);
10944 match(Set result (PartialSubtypeCheck sub super));
10945 effect(TEMP tmpR11, TEMP tmpR12, TEMP tmpR13, TEMP tmpR16, KILL cr);
10946
10947 ins_cost(10 * DEFAULT_COST); // slightly larger than the next version
10948 format %{ "partialSubtypeCheck $result, $sub, $super" %}
10949
10950 ins_encode %{
10951 __ lookup_secondary_supers_table_var($sub$$Register, $super$$Register, $result$$Register,
10952 $tmpR11$$Register, $tmpR12$$Register, $tmpR13$$Register,
10953 $tmpR16$$Register, nullptr /*L_success*/);
10954 %}
10955
10956 ins_pipe(pipe_class_memory);
10957 %}
10958
10959 instruct partialSubtypeCheckConstSuper(iRegP_R14 sub, iRegP_R10 super_reg, immP super_con, iRegP_R15 result,
10960 iRegP_R11 tmpR11, iRegP_R12 tmpR12, iRegP_R13 tmpR13, iRegP_R16 tmpR16, rFlagsReg cr)
10961 %{
10962 predicate(UseSecondarySupersTable);
10963 match(Set result (PartialSubtypeCheck sub (Binary super_reg super_con)));
10964 effect(TEMP tmpR11, TEMP tmpR12, TEMP tmpR13, TEMP tmpR16, KILL cr);
10965
10966 ins_cost(5 * DEFAULT_COST); // needs to be less than competing nodes
10967 format %{ "partialSubtypeCheck $result, $sub, $super_reg, $super_con" %}
10968
10969 ins_encode %{
10970 bool success = false;
10971 u1 super_klass_slot = ((Klass*)$super_con$$constant)->hash_slot();
10972 if (InlineSecondarySupersTest) {
10973 success = __ lookup_secondary_supers_table_const($sub$$Register, $super_reg$$Register, $result$$Register,
10974 $tmpR11$$Register, $tmpR12$$Register, $tmpR13$$Register,
10975 $tmpR16$$Register, super_klass_slot);
10976 } else {
10977 address call = __ reloc_call(RuntimeAddress(StubRoutines::lookup_secondary_supers_table_stub(super_klass_slot)));
10978 success = (call != nullptr);
10979 }
10980 if (!success) {
10981 ciEnv::current()->record_failure("CodeCache is full");
10982 return;
10983 }
10984 %}
10985
10986 ins_pipe(pipe_class_memory);
10987 %}
10988
10989 instruct string_compareU(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
10990 iRegI_R10 result, iRegP_R28 tmp1, iRegL_R29 tmp2, iRegL_R30 tmp3, rFlagsReg cr)
10991 %{
10992 predicate(!UseRVV && ((StrCompNode *)n)->encoding() == StrIntrinsicNode::UU);
10993 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10994 effect(KILL tmp1, KILL tmp2, KILL tmp3, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
10995
10996 format %{ "String Compare $str1, $cnt1, $str2, $cnt2 -> $result\t#@string_compareU" %}
10997 ins_encode %{
10998 // Count is in 8-bit bytes; non-Compact chars are 16 bits.
10999 __ string_compare($str1$$Register, $str2$$Register,
11000 $cnt1$$Register, $cnt2$$Register, $result$$Register,
11001 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
11002 StrIntrinsicNode::UU);
11003 %}
11004 ins_pipe(pipe_class_memory);
11005 %}
11006
11007 instruct string_compareL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
11008 iRegI_R10 result, iRegP_R28 tmp1, iRegL_R29 tmp2, iRegL_R30 tmp3, rFlagsReg cr)
11009 %{
11010 predicate(!UseRVV && ((StrCompNode *)n)->encoding() == StrIntrinsicNode::LL);
11011 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11012 effect(KILL tmp1, KILL tmp2, KILL tmp3, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11013
11014 format %{ "String Compare $str1, $cnt1, $str2, $cnt2 -> $result\t#@string_compareL" %}
11015 ins_encode %{
11016 __ string_compare($str1$$Register, $str2$$Register,
11017 $cnt1$$Register, $cnt2$$Register, $result$$Register,
11018 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
11019 StrIntrinsicNode::LL);
11020 %}
11021 ins_pipe(pipe_class_memory);
11022 %}
11023
11024 instruct string_compareUL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
11025 iRegI_R10 result, iRegP_R28 tmp1, iRegL_R29 tmp2, iRegL_R30 tmp3, rFlagsReg cr)
11026 %{
11027 predicate(!UseRVV && ((StrCompNode *)n)->encoding() == StrIntrinsicNode::UL);
11028 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11029 effect(KILL tmp1, KILL tmp2, KILL tmp3, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11030
11031 format %{"String Compare $str1, $cnt1, $str2, $cnt2 -> $result\t#@string_compareUL" %}
11032 ins_encode %{
11033 __ string_compare($str1$$Register, $str2$$Register,
11034 $cnt1$$Register, $cnt2$$Register, $result$$Register,
11035 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
11036 StrIntrinsicNode::UL);
11037 %}
11038 ins_pipe(pipe_class_memory);
11039 %}
11040
11041 instruct string_compareLU(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
11042 iRegI_R10 result, iRegP_R28 tmp1, iRegL_R29 tmp2, iRegL_R30 tmp3,
11043 rFlagsReg cr)
11044 %{
11045 predicate(!UseRVV && ((StrCompNode *)n)->encoding() == StrIntrinsicNode::LU);
11046 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11047 effect(KILL tmp1, KILL tmp2, KILL tmp3, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11048
11049 format %{ "String Compare $str1, $cnt1, $str2, $cnt2 -> $result\t#@string_compareLU" %}
11050 ins_encode %{
11051 __ string_compare($str1$$Register, $str2$$Register,
11052 $cnt1$$Register, $cnt2$$Register, $result$$Register,
11053 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
11054 StrIntrinsicNode::LU);
11055 %}
11056 ins_pipe(pipe_class_memory);
11057 %}
11058
11059 instruct string_indexofUU(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
11060 iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3,
11061 iRegINoSp tmp4, iRegINoSp tmp5, iRegINoSp tmp6, rFlagsReg cr)
11062 %{
11063 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU);
11064 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
11065 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, TEMP_DEF result,
11066 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, TEMP tmp6, KILL cr);
11067
11068 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result (UU)" %}
11069 ins_encode %{
11070 __ string_indexof($str1$$Register, $str2$$Register,
11071 $cnt1$$Register, $cnt2$$Register,
11072 $tmp1$$Register, $tmp2$$Register,
11073 $tmp3$$Register, $tmp4$$Register,
11074 $tmp5$$Register, $tmp6$$Register,
11075 $result$$Register, StrIntrinsicNode::UU);
11076 %}
11077 ins_pipe(pipe_class_memory);
11078 %}
11079
11080 instruct string_indexofLL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
11081 iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3,
11082 iRegINoSp tmp4, iRegINoSp tmp5, iRegINoSp tmp6, rFlagsReg cr)
11083 %{
11084 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL);
11085 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
11086 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, TEMP_DEF result,
11087 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, TEMP tmp6, KILL cr);
11088
11089 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result (LL)" %}
11090 ins_encode %{
11091 __ string_indexof($str1$$Register, $str2$$Register,
11092 $cnt1$$Register, $cnt2$$Register,
11093 $tmp1$$Register, $tmp2$$Register,
11094 $tmp3$$Register, $tmp4$$Register,
11095 $tmp5$$Register, $tmp6$$Register,
11096 $result$$Register, StrIntrinsicNode::LL);
11097 %}
11098 ins_pipe(pipe_class_memory);
11099 %}
11100
11101 instruct string_indexofUL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
11102 iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3,
11103 iRegINoSp tmp4, iRegINoSp tmp5, iRegINoSp tmp6, rFlagsReg cr)
11104 %{
11105 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL);
11106 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
11107 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, TEMP_DEF result,
11108 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, TEMP tmp6, KILL cr);
11109 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result (UL)" %}
11110
11111 ins_encode %{
11112 __ string_indexof($str1$$Register, $str2$$Register,
11113 $cnt1$$Register, $cnt2$$Register,
11114 $tmp1$$Register, $tmp2$$Register,
11115 $tmp3$$Register, $tmp4$$Register,
11116 $tmp5$$Register, $tmp6$$Register,
11117 $result$$Register, StrIntrinsicNode::UL);
11118 %}
11119 ins_pipe(pipe_class_memory);
11120 %}
11121
11122 instruct string_indexof_conUU(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2,
11123 immI_le_4 int_cnt2, iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2,
11124 iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
11125 %{
11126 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU);
11127 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
11128 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, TEMP_DEF result,
11129 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
11130
11131 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result (UU)" %}
11132
11133 ins_encode %{
11134 int icnt2 = (int)$int_cnt2$$constant;
11135 __ string_indexof_linearscan($str1$$Register, $str2$$Register,
11136 $cnt1$$Register, zr,
11137 $tmp1$$Register, $tmp2$$Register,
11138 $tmp3$$Register, $tmp4$$Register,
11139 icnt2, $result$$Register, StrIntrinsicNode::UU);
11140 %}
11141 ins_pipe(pipe_class_memory);
11142 %}
11143
11144 instruct string_indexof_conLL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2,
11145 immI_le_4 int_cnt2, iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2,
11146 iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
11147 %{
11148 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL);
11149 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
11150 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, TEMP_DEF result,
11151 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
11152
11153 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result (LL)" %}
11154 ins_encode %{
11155 int icnt2 = (int)$int_cnt2$$constant;
11156 __ string_indexof_linearscan($str1$$Register, $str2$$Register,
11157 $cnt1$$Register, zr,
11158 $tmp1$$Register, $tmp2$$Register,
11159 $tmp3$$Register, $tmp4$$Register,
11160 icnt2, $result$$Register, StrIntrinsicNode::LL);
11161 %}
11162 ins_pipe(pipe_class_memory);
11163 %}
11164
11165 instruct string_indexof_conUL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2,
11166 immI_1 int_cnt2, iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2,
11167 iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
11168 %{
11169 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL);
11170 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
11171 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, TEMP_DEF result,
11172 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
11173
11174 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result (UL)" %}
11175 ins_encode %{
11176 int icnt2 = (int)$int_cnt2$$constant;
11177 __ string_indexof_linearscan($str1$$Register, $str2$$Register,
11178 $cnt1$$Register, zr,
11179 $tmp1$$Register, $tmp2$$Register,
11180 $tmp3$$Register, $tmp4$$Register,
11181 icnt2, $result$$Register, StrIntrinsicNode::UL);
11182 %}
11183 ins_pipe(pipe_class_memory);
11184 %}
11185
11186 instruct stringU_indexof_char(iRegP_R11 str1, iRegI_R12 cnt1, iRegI_R13 ch,
11187 iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2,
11188 iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
11189 %{
11190 match(Set result (StrIndexOfChar (Binary str1 cnt1) ch));
11191 predicate(!UseRVV && (((StrIndexOfCharNode*)n)->encoding() == StrIntrinsicNode::U));
11192 effect(USE_KILL str1, USE_KILL cnt1, USE_KILL ch, TEMP_DEF result,
11193 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
11194
11195 format %{ "StringUTF16 IndexOf char[] $str1, $cnt1, $ch -> $result" %}
11196 ins_encode %{
11197 __ string_indexof_char($str1$$Register, $cnt1$$Register, $ch$$Register,
11198 $result$$Register, $tmp1$$Register, $tmp2$$Register,
11199 $tmp3$$Register, $tmp4$$Register, false /* isU */);
11200 %}
11201 ins_pipe(pipe_class_memory);
11202 %}
11203
11204
11205 instruct stringL_indexof_char(iRegP_R11 str1, iRegI_R12 cnt1, iRegI_R13 ch,
11206 iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2,
11207 iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
11208 %{
11209 match(Set result (StrIndexOfChar (Binary str1 cnt1) ch));
11210 predicate(!UseRVV && (((StrIndexOfCharNode*)n)->encoding() == StrIntrinsicNode::L));
11211 effect(USE_KILL str1, USE_KILL cnt1, USE_KILL ch, TEMP_DEF result,
11212 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
11213
11214 format %{ "StringLatin1 IndexOf char[] $str1, $cnt1, $ch -> $result" %}
11215 ins_encode %{
11216 __ string_indexof_char($str1$$Register, $cnt1$$Register, $ch$$Register,
11217 $result$$Register, $tmp1$$Register, $tmp2$$Register,
11218 $tmp3$$Register, $tmp4$$Register, true /* isL */);
11219 %}
11220 ins_pipe(pipe_class_memory);
11221 %}
11222
11223 // clearing of an array
11224 instruct clearArray_reg_reg(iRegL_R29 cnt, iRegP_R28 base, iRegP_R30 tmp1,
11225 iRegP_R31 tmp2, rFlagsReg cr, Universe dummy)
11226 %{
11227 // temp registers must match the one used in StubGenerator::generate_zero_blocks()
11228 predicate(UseBlockZeroing || !UseRVV);
11229 match(Set dummy (ClearArray cnt base));
11230 effect(USE_KILL cnt, USE_KILL base, TEMP tmp1, TEMP tmp2, KILL cr);
11231
11232 ins_cost(4 * DEFAULT_COST);
11233 format %{ "ClearArray $cnt, $base\t#@clearArray_reg_reg" %}
11234
11235 ins_encode %{
11236 address tpc = __ zero_words($base$$Register, $cnt$$Register);
11237 if (tpc == nullptr) {
11238 ciEnv::current()->record_failure("CodeCache is full");
11239 return;
11240 }
11241 %}
11242
11243 ins_pipe(pipe_class_memory);
11244 %}
11245
11246 instruct clearArray_imm_reg(immL cnt, iRegP_R28 base, Universe dummy, rFlagsReg cr)
11247 %{
11248 predicate(!UseRVV && (uint64_t)n->in(2)->get_long()
11249 < (uint64_t)(BlockZeroingLowLimit >> LogBytesPerWord));
11250 match(Set dummy (ClearArray cnt base));
11251 effect(USE_KILL base, KILL cr);
11252
11253 ins_cost(4 * DEFAULT_COST);
11254 format %{ "ClearArray $cnt, $base\t#@clearArray_imm_reg" %}
11255
11256 ins_encode %{
11257 __ zero_words($base$$Register, (uint64_t)$cnt$$constant);
11258 %}
11259
11260 ins_pipe(pipe_class_memory);
11261 %}
11262
11263 instruct string_equalsL(iRegP_R11 str1, iRegP_R13 str2, iRegI_R14 cnt,
11264 iRegI_R10 result, rFlagsReg cr)
11265 %{
11266 predicate(!UseRVV && ((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::LL);
11267 match(Set result (StrEquals (Binary str1 str2) cnt));
11268 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL cr);
11269
11270 format %{ "String Equals $str1, $str2, $cnt -> $result\t#@string_equalsL" %}
11271 ins_encode %{
11272 // Count is in 8-bit bytes; non-Compact chars are 16 bits.
11273 __ string_equals($str1$$Register, $str2$$Register,
11274 $result$$Register, $cnt$$Register);
11275 %}
11276 ins_pipe(pipe_class_memory);
11277 %}
11278
11279 instruct array_equalsB(iRegP_R11 ary1, iRegP_R12 ary2, iRegI_R10 result,
11280 iRegP_R13 tmp1, iRegP_R14 tmp2, iRegP_R15 tmp3)
11281 %{
11282 predicate(!UseRVV && ((AryEqNode*)n)->encoding() == StrIntrinsicNode::LL);
11283 match(Set result (AryEq ary1 ary2));
11284 effect(USE_KILL ary1, USE_KILL ary2, TEMP tmp1, TEMP tmp2, TEMP tmp3);
11285
11286 format %{ "Array Equals $ary1, $ary2 -> $result\t#@array_equalsB // KILL all" %}
11287 ins_encode %{
11288 __ arrays_equals($ary1$$Register, $ary2$$Register,
11289 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
11290 $result$$Register, 1);
11291 %}
11292 ins_pipe(pipe_class_memory);
11293 %}
11294
11295 instruct array_equalsC(iRegP_R11 ary1, iRegP_R12 ary2, iRegI_R10 result,
11296 iRegP_R13 tmp1, iRegP_R14 tmp2, iRegP_R15 tmp3)
11297 %{
11298 predicate(!UseRVV && ((AryEqNode*)n)->encoding() == StrIntrinsicNode::UU);
11299 match(Set result (AryEq ary1 ary2));
11300 effect(USE_KILL ary1, USE_KILL ary2, TEMP tmp1, TEMP tmp2, TEMP tmp3);
11301
11302 format %{ "Array Equals $ary1, $ary2 -> $result\t#@array_equalsC // KILL all" %}
11303 ins_encode %{
11304 __ arrays_equals($ary1$$Register, $ary2$$Register,
11305 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
11306 $result$$Register, 2);
11307 %}
11308 ins_pipe(pipe_class_memory);
11309 %}
11310
11311 // fast ArraysSupport.vectorizedHashCode
11312 instruct arrays_hashcode(iRegP_R11 ary, iRegI_R12 cnt, iRegI_R10 result, immI basic_type,
11313 iRegLNoSp tmp1, iRegLNoSp tmp2,
11314 iRegLNoSp tmp3, iRegLNoSp tmp4,
11315 iRegLNoSp tmp5, iRegLNoSp tmp6, rFlagsReg cr)
11316 %{
11317 predicate(!UseRVV);
11318 match(Set result (VectorizedHashCode (Binary ary cnt) (Binary result basic_type)));
11319 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, TEMP tmp6,
11320 USE_KILL ary, USE_KILL cnt, USE basic_type, KILL cr);
11321
11322 format %{ "Array HashCode array[] $ary,$cnt,$result,$basic_type -> $result // KILL all" %}
11323 ins_encode %{
11324 __ arrays_hashcode($ary$$Register, $cnt$$Register, $result$$Register,
11325 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
11326 $tmp4$$Register, $tmp5$$Register, $tmp6$$Register,
11327 (BasicType)$basic_type$$constant);
11328 %}
11329 ins_pipe(pipe_class_memory);
11330 %}
11331
11332 // ============================================================================
11333 // Safepoint Instructions
11334
11335 instruct safePoint(iRegP poll)
11336 %{
11337 match(SafePoint poll);
11338
11339 ins_cost(2 * LOAD_COST);
11340 format %{
11341 "lwu zr, [$poll]\t# Safepoint: poll for GC, #@safePoint"
11342 %}
11343 ins_encode %{
11344 __ read_polling_page(as_Register($poll$$reg), 0, relocInfo::poll_type);
11345 %}
11346 ins_pipe(pipe_serial); // ins_pipe(iload_reg_mem);
11347 %}
11348
11349 // ============================================================================
11350 // This name is KNOWN by the ADLC and cannot be changed.
11351 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
11352 // for this guy.
11353 instruct tlsLoadP(javaThread_RegP dst)
11354 %{
11355 match(Set dst (ThreadLocal));
11356
11357 ins_cost(0);
11358
11359 format %{ " -- \t// $dst=Thread::current(), empty, #@tlsLoadP" %}
11360
11361 size(0);
11362
11363 ins_encode( /*empty*/ );
11364
11365 ins_pipe(pipe_class_empty);
11366 %}
11367
11368 // inlined locking and unlocking
11369 // using t1 as the 'flag' register to bridge the BoolNode producers and consumers
11370 instruct cmpFastLock(rFlagsReg cr, iRegP object, iRegP box,
11371 iRegPNoSp tmp1, iRegPNoSp tmp2, iRegPNoSp tmp3, iRegPNoSp tmp4)
11372 %{
11373 match(Set cr (FastLock object box));
11374 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4);
11375
11376 ins_cost(10 * DEFAULT_COST);
11377 format %{ "fastlock $object,$box\t! kills $tmp1,$tmp2,$tmp3,$tmp4 #@cmpFastLock" %}
11378
11379 ins_encode %{
11380 __ fast_lock($object$$Register, $box$$Register,
11381 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register);
11382 %}
11383
11384 ins_pipe(pipe_serial);
11385 %}
11386
11387 // using t1 as the 'flag' register to bridge the BoolNode producers and consumers
11388 instruct cmpFastUnlock(rFlagsReg cr, iRegP object, iRegP box,
11389 iRegPNoSp tmp1, iRegPNoSp tmp2, iRegPNoSp tmp3)
11390 %{
11391 match(Set cr (FastUnlock object box));
11392 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3);
11393
11394 ins_cost(10 * DEFAULT_COST);
11395 format %{ "fastunlock $object,$box\t! kills $tmp1,$tmp2,$tmp3 #@cmpFastUnlock" %}
11396
11397 ins_encode %{
11398 __ fast_unlock($object$$Register, $box$$Register,
11399 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
11400 %}
11401
11402 ins_pipe(pipe_serial);
11403 %}
11404
11405 // Tail Call; Jump from runtime stub to Java code.
11406 // Also known as an 'interprocedural jump'.
11407 // Target of jump will eventually return to caller.
11408 // TailJump below removes the return address.
11409 // Don't use fp for 'jump_target' because a MachEpilogNode has already been
11410 // emitted just above the TailCall which has reset fp to the caller state.
11411 instruct TailCalljmpInd(iRegPNoSpNoFp jump_target, inline_cache_RegP method_oop)
11412 %{
11413 match(TailCall jump_target method_oop);
11414
11415 ins_cost(BRANCH_COST);
11416
11417 format %{ "jalr $jump_target\t# $method_oop holds method oop, #@TailCalljmpInd." %}
11418
11419 ins_encode(riscv_enc_tail_call(jump_target));
11420
11421 ins_pipe(pipe_class_call);
11422 %}
11423
11424 instruct TailjmpInd(iRegPNoSpNoFp jump_target, iRegP_R10 ex_oop)
11425 %{
11426 match(TailJump jump_target ex_oop);
11427
11428 ins_cost(ALU_COST + BRANCH_COST);
11429
11430 format %{ "jalr $jump_target\t# $ex_oop holds exception oop, #@TailjmpInd." %}
11431
11432 ins_encode(riscv_enc_tail_jmp(jump_target));
11433
11434 ins_pipe(pipe_class_call);
11435 %}
11436
11437 // Forward exception.
11438 instruct ForwardExceptionjmp()
11439 %{
11440 match(ForwardException);
11441
11442 ins_cost(BRANCH_COST);
11443
11444 format %{ "j forward_exception_stub\t#@ForwardException" %}
11445
11446 ins_encode %{
11447 __ far_jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
11448 %}
11449
11450 ins_pipe(pipe_class_call);
11451 %}
11452
11453 // Create exception oop: created by stack-crawling runtime code.
11454 // Created exception is now available to this handler, and is setup
11455 // just prior to jumping to this handler. No code emitted.
11456 instruct CreateException(iRegP_R10 ex_oop)
11457 %{
11458 match(Set ex_oop (CreateEx));
11459
11460 ins_cost(0);
11461 format %{ " -- \t// exception oop; no code emitted, #@CreateException" %}
11462
11463 size(0);
11464
11465 ins_encode( /*empty*/ );
11466
11467 ins_pipe(pipe_class_empty);
11468 %}
11469
11470 // Rethrow exception: The exception oop will come in the first
11471 // argument position. Then JUMP (not call) to the rethrow stub code.
11472 instruct RethrowException()
11473 %{
11474 match(Rethrow);
11475
11476 ins_cost(BRANCH_COST);
11477
11478 format %{ "j rethrow_stub\t#@RethrowException" %}
11479
11480 ins_encode(riscv_enc_rethrow());
11481
11482 ins_pipe(pipe_class_call);
11483 %}
11484
11485 // Return Instruction
11486 // epilog node loads ret address into ra as part of frame pop
11487 instruct Ret()
11488 %{
11489 match(Return);
11490
11491 ins_cost(BRANCH_COST);
11492 format %{ "ret\t// return register, #@Ret" %}
11493
11494 ins_encode(riscv_enc_ret());
11495
11496 ins_pipe(pipe_branch);
11497 %}
11498
11499 // Die now.
11500 instruct ShouldNotReachHere() %{
11501 match(Halt);
11502
11503 ins_cost(BRANCH_COST);
11504
11505 format %{ "#@ShouldNotReachHere" %}
11506
11507 ins_encode %{
11508 if (is_reachable()) {
11509 const char* str = __ code_string(_halt_reason);
11510 __ stop(str);
11511 }
11512 %}
11513
11514 ins_pipe(pipe_class_default);
11515 %}
11516
11517
11518 //----------PEEPHOLE RULES-----------------------------------------------------
11519 // These must follow all instruction definitions as they use the names
11520 // defined in the instructions definitions.
11521 //
11522 // peepmatch ( root_instr_name [preceding_instruction]* );
11523 //
11524 // peepconstraint %{
11525 // (instruction_number.operand_name relational_op instruction_number.operand_name
11526 // [, ...] );
11527 // // instruction numbers are zero-based using left to right order in peepmatch
11528 //
11529 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
11530 // // provide an instruction_number.operand_name for each operand that appears
11531 // // in the replacement instruction's match rule
11532 //
11533 // ---------VM FLAGS---------------------------------------------------------
11534 //
11535 // All peephole optimizations can be turned off using -XX:-OptoPeephole
11536 //
11537 // Each peephole rule is given an identifying number starting with zero and
11538 // increasing by one in the order seen by the parser. An individual peephole
11539 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
11540 // on the command-line.
11541 //
11542 // ---------CURRENT LIMITATIONS----------------------------------------------
11543 //
11544 // Only match adjacent instructions in same basic block
11545 // Only equality constraints
11546 // Only constraints between operands, not (0.dest_reg == RAX_enc)
11547 // Only one replacement instruction
11548 //
11549 //----------SMARTSPILL RULES---------------------------------------------------
11550 // These must follow all instruction definitions as they use the names
11551 // defined in the instructions definitions.
11552
11553 // Local Variables:
11554 // mode: c++
11555 // End: