1 //
2 // Copyright (c) 2003, 2026, Oracle and/or its affiliates. All rights reserved.
3 // Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
4 // Copyright (c) 2020, 2024, Huawei Technologies Co., Ltd. All rights reserved.
5 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
6 //
7 // This code is free software; you can redistribute it and/or modify it
8 // under the terms of the GNU General Public License version 2 only, as
9 // published by the Free Software Foundation.
10 //
11 // This code is distributed in the hope that it will be useful, but WITHOUT
12 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 // version 2 for more details (a copy is included in the LICENSE file that
15 // accompanied this code).
16 //
17 // You should have received a copy of the GNU General Public License version
18 // 2 along with this work; if not, write to the Free Software Foundation,
19 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
20 //
21 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
22 // or visit www.oracle.com if you need additional information or have any
23 // questions.
24 //
25 //
26
27 // RISCV Architecture Description File
28
29 //----------REGISTER DEFINITION BLOCK------------------------------------------
30 // This information is used by the matcher and the register allocator to
31 // describe individual registers and classes of registers within the target
32 // architecture.
33
34 register %{
35 //----------Architecture Description Register Definitions----------------------
36 // General Registers
37 // "reg_def" name ( register save type, C convention save type,
38 // ideal register type, encoding );
39 // Register Save Types:
40 //
41 // NS = No-Save: The register allocator assumes that these registers
42 // can be used without saving upon entry to the method, &
43 // that they do not need to be saved at call sites.
44 //
45 // SOC = Save-On-Call: The register allocator assumes that these registers
46 // can be used without saving upon entry to the method,
47 // but that they must be saved at call sites.
48 //
49 // SOE = Save-On-Entry: The register allocator assumes that these registers
50 // must be saved before using them upon entry to the
51 // method, but they do not need to be saved at call
52 // sites.
53 //
54 // AS = Always-Save: The register allocator assumes that these registers
55 // must be saved before using them upon entry to the
56 // method, & that they must be saved at call sites.
57 //
58 // Ideal Register Type is used to determine how to save & restore a
59 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
60 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
61 //
62 // The encoding number is the actual bit-pattern placed into the opcodes.
63
64 // We must define the 64 bit int registers in two 32 bit halves, the
65 // real lower register and a virtual upper half register. upper halves
66 // are used by the register allocator but are not actually supplied as
67 // operands to memory ops.
68 //
69 // follow the C1 compiler in making registers
70 //
71 // x7, x9-x17, x27-x31 volatile (caller save)
72 // x0-x4, x8, x23 system (no save, no allocate)
73 // x5-x6 non-allocatable (so we can use them as temporary regs)
74
75 //
76 // as regards Java usage. we don't use any callee save registers
77 // because this makes it difficult to de-optimise a frame (see comment
78 // in x86 implementation of Deoptimization::unwind_callee_save_values)
79 //
80
81 // General Registers
82
83 reg_def R0 ( NS, NS, Op_RegI, 0, x0->as_VMReg() ); // zr
84 reg_def R0_H ( NS, NS, Op_RegI, 0, x0->as_VMReg()->next() );
85 reg_def R1 ( NS, SOC, Op_RegI, 1, x1->as_VMReg() ); // ra
86 reg_def R1_H ( NS, SOC, Op_RegI, 1, x1->as_VMReg()->next() );
87 reg_def R2 ( NS, NS, Op_RegI, 2, x2->as_VMReg() ); // sp
88 reg_def R2_H ( NS, NS, Op_RegI, 2, x2->as_VMReg()->next() );
89 reg_def R3 ( NS, NS, Op_RegI, 3, x3->as_VMReg() ); // gp
90 reg_def R3_H ( NS, NS, Op_RegI, 3, x3->as_VMReg()->next() );
91 reg_def R4 ( NS, NS, Op_RegI, 4, x4->as_VMReg() ); // tp
92 reg_def R4_H ( NS, NS, Op_RegI, 4, x4->as_VMReg()->next() );
93 reg_def R7 ( SOC, SOC, Op_RegI, 7, x7->as_VMReg() );
94 reg_def R7_H ( SOC, SOC, Op_RegI, 7, x7->as_VMReg()->next() );
95 reg_def R8 ( NS, SOE, Op_RegI, 8, x8->as_VMReg() ); // fp
96 reg_def R8_H ( NS, SOE, Op_RegI, 8, x8->as_VMReg()->next() );
97 reg_def R9 ( SOC, SOE, Op_RegI, 9, x9->as_VMReg() );
98 reg_def R9_H ( SOC, SOE, Op_RegI, 9, x9->as_VMReg()->next() );
99 reg_def R10 ( SOC, SOC, Op_RegI, 10, x10->as_VMReg() );
100 reg_def R10_H ( SOC, SOC, Op_RegI, 10, x10->as_VMReg()->next());
101 reg_def R11 ( SOC, SOC, Op_RegI, 11, x11->as_VMReg() );
102 reg_def R11_H ( SOC, SOC, Op_RegI, 11, x11->as_VMReg()->next());
103 reg_def R12 ( SOC, SOC, Op_RegI, 12, x12->as_VMReg() );
104 reg_def R12_H ( SOC, SOC, Op_RegI, 12, x12->as_VMReg()->next());
105 reg_def R13 ( SOC, SOC, Op_RegI, 13, x13->as_VMReg() );
106 reg_def R13_H ( SOC, SOC, Op_RegI, 13, x13->as_VMReg()->next());
107 reg_def R14 ( SOC, SOC, Op_RegI, 14, x14->as_VMReg() );
108 reg_def R14_H ( SOC, SOC, Op_RegI, 14, x14->as_VMReg()->next());
109 reg_def R15 ( SOC, SOC, Op_RegI, 15, x15->as_VMReg() );
110 reg_def R15_H ( SOC, SOC, Op_RegI, 15, x15->as_VMReg()->next());
111 reg_def R16 ( SOC, SOC, Op_RegI, 16, x16->as_VMReg() );
112 reg_def R16_H ( SOC, SOC, Op_RegI, 16, x16->as_VMReg()->next());
113 reg_def R17 ( SOC, SOC, Op_RegI, 17, x17->as_VMReg() );
114 reg_def R17_H ( SOC, SOC, Op_RegI, 17, x17->as_VMReg()->next());
115 reg_def R18 ( SOC, SOE, Op_RegI, 18, x18->as_VMReg() );
116 reg_def R18_H ( SOC, SOE, Op_RegI, 18, x18->as_VMReg()->next());
117 reg_def R19 ( SOC, SOE, Op_RegI, 19, x19->as_VMReg() );
118 reg_def R19_H ( SOC, SOE, Op_RegI, 19, x19->as_VMReg()->next());
119 reg_def R20 ( SOC, SOE, Op_RegI, 20, x20->as_VMReg() ); // caller esp
120 reg_def R20_H ( SOC, SOE, Op_RegI, 20, x20->as_VMReg()->next());
121 reg_def R21 ( SOC, SOE, Op_RegI, 21, x21->as_VMReg() );
122 reg_def R21_H ( SOC, SOE, Op_RegI, 21, x21->as_VMReg()->next());
123 reg_def R22 ( SOC, SOE, Op_RegI, 22, x22->as_VMReg() );
124 reg_def R22_H ( SOC, SOE, Op_RegI, 22, x22->as_VMReg()->next());
125 reg_def R23 ( NS, SOE, Op_RegI, 23, x23->as_VMReg() ); // java thread
126 reg_def R23_H ( NS, SOE, Op_RegI, 23, x23->as_VMReg()->next());
127 reg_def R24 ( SOC, SOE, Op_RegI, 24, x24->as_VMReg() );
128 reg_def R24_H ( SOC, SOE, Op_RegI, 24, x24->as_VMReg()->next());
129 reg_def R25 ( SOC, SOE, Op_RegI, 25, x25->as_VMReg() );
130 reg_def R25_H ( SOC, SOE, Op_RegI, 25, x25->as_VMReg()->next());
131 reg_def R26 ( SOC, SOE, Op_RegI, 26, x26->as_VMReg() );
132 reg_def R26_H ( SOC, SOE, Op_RegI, 26, x26->as_VMReg()->next());
133 reg_def R27 ( SOC, SOE, Op_RegI, 27, x27->as_VMReg() ); // heapbase
134 reg_def R27_H ( SOC, SOE, Op_RegI, 27, x27->as_VMReg()->next());
135 reg_def R28 ( SOC, SOC, Op_RegI, 28, x28->as_VMReg() );
136 reg_def R28_H ( SOC, SOC, Op_RegI, 28, x28->as_VMReg()->next());
137 reg_def R29 ( SOC, SOC, Op_RegI, 29, x29->as_VMReg() );
138 reg_def R29_H ( SOC, SOC, Op_RegI, 29, x29->as_VMReg()->next());
139 reg_def R30 ( SOC, SOC, Op_RegI, 30, x30->as_VMReg() );
140 reg_def R30_H ( SOC, SOC, Op_RegI, 30, x30->as_VMReg()->next());
141 reg_def R31 ( SOC, SOC, Op_RegI, 31, x31->as_VMReg() );
142 reg_def R31_H ( SOC, SOC, Op_RegI, 31, x31->as_VMReg()->next());
143
144 // ----------------------------
145 // Float/Double Registers
146 // ----------------------------
147
148 // Double Registers
149
150 // The rules of ADL require that double registers be defined in pairs.
151 // Each pair must be two 32-bit values, but not necessarily a pair of
152 // single float registers. In each pair, ADLC-assigned register numbers
153 // must be adjacent, with the lower number even. Finally, when the
154 // CPU stores such a register pair to memory, the word associated with
155 // the lower ADLC-assigned number must be stored to the lower address.
156
157 // RISCV has 32 floating-point registers. Each can store a single
158 // or double precision floating-point value.
159
160 // for Java use float registers f0-f31 are always save on call whereas
161 // the platform ABI treats f8-f9 and f18-f27 as callee save). Other
162 // float registers are SOC as per the platform spec
163
164 reg_def F0 ( SOC, SOC, Op_RegF, 0, f0->as_VMReg() );
165 reg_def F0_H ( SOC, SOC, Op_RegF, 0, f0->as_VMReg()->next() );
166 reg_def F1 ( SOC, SOC, Op_RegF, 1, f1->as_VMReg() );
167 reg_def F1_H ( SOC, SOC, Op_RegF, 1, f1->as_VMReg()->next() );
168 reg_def F2 ( SOC, SOC, Op_RegF, 2, f2->as_VMReg() );
169 reg_def F2_H ( SOC, SOC, Op_RegF, 2, f2->as_VMReg()->next() );
170 reg_def F3 ( SOC, SOC, Op_RegF, 3, f3->as_VMReg() );
171 reg_def F3_H ( SOC, SOC, Op_RegF, 3, f3->as_VMReg()->next() );
172 reg_def F4 ( SOC, SOC, Op_RegF, 4, f4->as_VMReg() );
173 reg_def F4_H ( SOC, SOC, Op_RegF, 4, f4->as_VMReg()->next() );
174 reg_def F5 ( SOC, SOC, Op_RegF, 5, f5->as_VMReg() );
175 reg_def F5_H ( SOC, SOC, Op_RegF, 5, f5->as_VMReg()->next() );
176 reg_def F6 ( SOC, SOC, Op_RegF, 6, f6->as_VMReg() );
177 reg_def F6_H ( SOC, SOC, Op_RegF, 6, f6->as_VMReg()->next() );
178 reg_def F7 ( SOC, SOC, Op_RegF, 7, f7->as_VMReg() );
179 reg_def F7_H ( SOC, SOC, Op_RegF, 7, f7->as_VMReg()->next() );
180 reg_def F8 ( SOC, SOE, Op_RegF, 8, f8->as_VMReg() );
181 reg_def F8_H ( SOC, SOE, Op_RegF, 8, f8->as_VMReg()->next() );
182 reg_def F9 ( SOC, SOE, Op_RegF, 9, f9->as_VMReg() );
183 reg_def F9_H ( SOC, SOE, Op_RegF, 9, f9->as_VMReg()->next() );
184 reg_def F10 ( SOC, SOC, Op_RegF, 10, f10->as_VMReg() );
185 reg_def F10_H ( SOC, SOC, Op_RegF, 10, f10->as_VMReg()->next() );
186 reg_def F11 ( SOC, SOC, Op_RegF, 11, f11->as_VMReg() );
187 reg_def F11_H ( SOC, SOC, Op_RegF, 11, f11->as_VMReg()->next() );
188 reg_def F12 ( SOC, SOC, Op_RegF, 12, f12->as_VMReg() );
189 reg_def F12_H ( SOC, SOC, Op_RegF, 12, f12->as_VMReg()->next() );
190 reg_def F13 ( SOC, SOC, Op_RegF, 13, f13->as_VMReg() );
191 reg_def F13_H ( SOC, SOC, Op_RegF, 13, f13->as_VMReg()->next() );
192 reg_def F14 ( SOC, SOC, Op_RegF, 14, f14->as_VMReg() );
193 reg_def F14_H ( SOC, SOC, Op_RegF, 14, f14->as_VMReg()->next() );
194 reg_def F15 ( SOC, SOC, Op_RegF, 15, f15->as_VMReg() );
195 reg_def F15_H ( SOC, SOC, Op_RegF, 15, f15->as_VMReg()->next() );
196 reg_def F16 ( SOC, SOC, Op_RegF, 16, f16->as_VMReg() );
197 reg_def F16_H ( SOC, SOC, Op_RegF, 16, f16->as_VMReg()->next() );
198 reg_def F17 ( SOC, SOC, Op_RegF, 17, f17->as_VMReg() );
199 reg_def F17_H ( SOC, SOC, Op_RegF, 17, f17->as_VMReg()->next() );
200 reg_def F18 ( SOC, SOE, Op_RegF, 18, f18->as_VMReg() );
201 reg_def F18_H ( SOC, SOE, Op_RegF, 18, f18->as_VMReg()->next() );
202 reg_def F19 ( SOC, SOE, Op_RegF, 19, f19->as_VMReg() );
203 reg_def F19_H ( SOC, SOE, Op_RegF, 19, f19->as_VMReg()->next() );
204 reg_def F20 ( SOC, SOE, Op_RegF, 20, f20->as_VMReg() );
205 reg_def F20_H ( SOC, SOE, Op_RegF, 20, f20->as_VMReg()->next() );
206 reg_def F21 ( SOC, SOE, Op_RegF, 21, f21->as_VMReg() );
207 reg_def F21_H ( SOC, SOE, Op_RegF, 21, f21->as_VMReg()->next() );
208 reg_def F22 ( SOC, SOE, Op_RegF, 22, f22->as_VMReg() );
209 reg_def F22_H ( SOC, SOE, Op_RegF, 22, f22->as_VMReg()->next() );
210 reg_def F23 ( SOC, SOE, Op_RegF, 23, f23->as_VMReg() );
211 reg_def F23_H ( SOC, SOE, Op_RegF, 23, f23->as_VMReg()->next() );
212 reg_def F24 ( SOC, SOE, Op_RegF, 24, f24->as_VMReg() );
213 reg_def F24_H ( SOC, SOE, Op_RegF, 24, f24->as_VMReg()->next() );
214 reg_def F25 ( SOC, SOE, Op_RegF, 25, f25->as_VMReg() );
215 reg_def F25_H ( SOC, SOE, Op_RegF, 25, f25->as_VMReg()->next() );
216 reg_def F26 ( SOC, SOE, Op_RegF, 26, f26->as_VMReg() );
217 reg_def F26_H ( SOC, SOE, Op_RegF, 26, f26->as_VMReg()->next() );
218 reg_def F27 ( SOC, SOE, Op_RegF, 27, f27->as_VMReg() );
219 reg_def F27_H ( SOC, SOE, Op_RegF, 27, f27->as_VMReg()->next() );
220 reg_def F28 ( SOC, SOC, Op_RegF, 28, f28->as_VMReg() );
221 reg_def F28_H ( SOC, SOC, Op_RegF, 28, f28->as_VMReg()->next() );
222 reg_def F29 ( SOC, SOC, Op_RegF, 29, f29->as_VMReg() );
223 reg_def F29_H ( SOC, SOC, Op_RegF, 29, f29->as_VMReg()->next() );
224 reg_def F30 ( SOC, SOC, Op_RegF, 30, f30->as_VMReg() );
225 reg_def F30_H ( SOC, SOC, Op_RegF, 30, f30->as_VMReg()->next() );
226 reg_def F31 ( SOC, SOC, Op_RegF, 31, f31->as_VMReg() );
227 reg_def F31_H ( SOC, SOC, Op_RegF, 31, f31->as_VMReg()->next() );
228
229 // ----------------------------
230 // Vector Registers
231 // ----------------------------
232
233 // For RVV vector registers, we simply extend vector register size to 4
234 // 'logical' slots. This is nominally 128 bits but it actually covers
235 // all possible 'physical' RVV vector register lengths from 128 ~ 1024
236 // bits. The 'physical' RVV vector register length is detected during
237 // startup, so the register allocator is able to identify the correct
238 // number of bytes needed for an RVV spill/unspill.
239
240 reg_def V0 ( SOC, SOC, Op_VecA, 0, v0->as_VMReg() );
241 reg_def V0_H ( SOC, SOC, Op_VecA, 0, v0->as_VMReg()->next() );
242 reg_def V0_J ( SOC, SOC, Op_VecA, 0, v0->as_VMReg()->next(2) );
243 reg_def V0_K ( SOC, SOC, Op_VecA, 0, v0->as_VMReg()->next(3) );
244
245 reg_def V1 ( SOC, SOC, Op_VecA, 1, v1->as_VMReg() );
246 reg_def V1_H ( SOC, SOC, Op_VecA, 1, v1->as_VMReg()->next() );
247 reg_def V1_J ( SOC, SOC, Op_VecA, 1, v1->as_VMReg()->next(2) );
248 reg_def V1_K ( SOC, SOC, Op_VecA, 1, v1->as_VMReg()->next(3) );
249
250 reg_def V2 ( SOC, SOC, Op_VecA, 2, v2->as_VMReg() );
251 reg_def V2_H ( SOC, SOC, Op_VecA, 2, v2->as_VMReg()->next() );
252 reg_def V2_J ( SOC, SOC, Op_VecA, 2, v2->as_VMReg()->next(2) );
253 reg_def V2_K ( SOC, SOC, Op_VecA, 2, v2->as_VMReg()->next(3) );
254
255 reg_def V3 ( SOC, SOC, Op_VecA, 3, v3->as_VMReg() );
256 reg_def V3_H ( SOC, SOC, Op_VecA, 3, v3->as_VMReg()->next() );
257 reg_def V3_J ( SOC, SOC, Op_VecA, 3, v3->as_VMReg()->next(2) );
258 reg_def V3_K ( SOC, SOC, Op_VecA, 3, v3->as_VMReg()->next(3) );
259
260 reg_def V4 ( SOC, SOC, Op_VecA, 4, v4->as_VMReg() );
261 reg_def V4_H ( SOC, SOC, Op_VecA, 4, v4->as_VMReg()->next() );
262 reg_def V4_J ( SOC, SOC, Op_VecA, 4, v4->as_VMReg()->next(2) );
263 reg_def V4_K ( SOC, SOC, Op_VecA, 4, v4->as_VMReg()->next(3) );
264
265 reg_def V5 ( SOC, SOC, Op_VecA, 5, v5->as_VMReg() );
266 reg_def V5_H ( SOC, SOC, Op_VecA, 5, v5->as_VMReg()->next() );
267 reg_def V5_J ( SOC, SOC, Op_VecA, 5, v5->as_VMReg()->next(2) );
268 reg_def V5_K ( SOC, SOC, Op_VecA, 5, v5->as_VMReg()->next(3) );
269
270 reg_def V6 ( SOC, SOC, Op_VecA, 6, v6->as_VMReg() );
271 reg_def V6_H ( SOC, SOC, Op_VecA, 6, v6->as_VMReg()->next() );
272 reg_def V6_J ( SOC, SOC, Op_VecA, 6, v6->as_VMReg()->next(2) );
273 reg_def V6_K ( SOC, SOC, Op_VecA, 6, v6->as_VMReg()->next(3) );
274
275 reg_def V7 ( SOC, SOC, Op_VecA, 7, v7->as_VMReg() );
276 reg_def V7_H ( SOC, SOC, Op_VecA, 7, v7->as_VMReg()->next() );
277 reg_def V7_J ( SOC, SOC, Op_VecA, 7, v7->as_VMReg()->next(2) );
278 reg_def V7_K ( SOC, SOC, Op_VecA, 7, v7->as_VMReg()->next(3) );
279
280 reg_def V8 ( SOC, SOC, Op_VecA, 8, v8->as_VMReg() );
281 reg_def V8_H ( SOC, SOC, Op_VecA, 8, v8->as_VMReg()->next() );
282 reg_def V8_J ( SOC, SOC, Op_VecA, 8, v8->as_VMReg()->next(2) );
283 reg_def V8_K ( SOC, SOC, Op_VecA, 8, v8->as_VMReg()->next(3) );
284
285 reg_def V9 ( SOC, SOC, Op_VecA, 9, v9->as_VMReg() );
286 reg_def V9_H ( SOC, SOC, Op_VecA, 9, v9->as_VMReg()->next() );
287 reg_def V9_J ( SOC, SOC, Op_VecA, 9, v9->as_VMReg()->next(2) );
288 reg_def V9_K ( SOC, SOC, Op_VecA, 9, v9->as_VMReg()->next(3) );
289
290 reg_def V10 ( SOC, SOC, Op_VecA, 10, v10->as_VMReg() );
291 reg_def V10_H ( SOC, SOC, Op_VecA, 10, v10->as_VMReg()->next() );
292 reg_def V10_J ( SOC, SOC, Op_VecA, 10, v10->as_VMReg()->next(2) );
293 reg_def V10_K ( SOC, SOC, Op_VecA, 10, v10->as_VMReg()->next(3) );
294
295 reg_def V11 ( SOC, SOC, Op_VecA, 11, v11->as_VMReg() );
296 reg_def V11_H ( SOC, SOC, Op_VecA, 11, v11->as_VMReg()->next() );
297 reg_def V11_J ( SOC, SOC, Op_VecA, 11, v11->as_VMReg()->next(2) );
298 reg_def V11_K ( SOC, SOC, Op_VecA, 11, v11->as_VMReg()->next(3) );
299
300 reg_def V12 ( SOC, SOC, Op_VecA, 12, v12->as_VMReg() );
301 reg_def V12_H ( SOC, SOC, Op_VecA, 12, v12->as_VMReg()->next() );
302 reg_def V12_J ( SOC, SOC, Op_VecA, 12, v12->as_VMReg()->next(2) );
303 reg_def V12_K ( SOC, SOC, Op_VecA, 12, v12->as_VMReg()->next(3) );
304
305 reg_def V13 ( SOC, SOC, Op_VecA, 13, v13->as_VMReg() );
306 reg_def V13_H ( SOC, SOC, Op_VecA, 13, v13->as_VMReg()->next() );
307 reg_def V13_J ( SOC, SOC, Op_VecA, 13, v13->as_VMReg()->next(2) );
308 reg_def V13_K ( SOC, SOC, Op_VecA, 13, v13->as_VMReg()->next(3) );
309
310 reg_def V14 ( SOC, SOC, Op_VecA, 14, v14->as_VMReg() );
311 reg_def V14_H ( SOC, SOC, Op_VecA, 14, v14->as_VMReg()->next() );
312 reg_def V14_J ( SOC, SOC, Op_VecA, 14, v14->as_VMReg()->next(2) );
313 reg_def V14_K ( SOC, SOC, Op_VecA, 14, v14->as_VMReg()->next(3) );
314
315 reg_def V15 ( SOC, SOC, Op_VecA, 15, v15->as_VMReg() );
316 reg_def V15_H ( SOC, SOC, Op_VecA, 15, v15->as_VMReg()->next() );
317 reg_def V15_J ( SOC, SOC, Op_VecA, 15, v15->as_VMReg()->next(2) );
318 reg_def V15_K ( SOC, SOC, Op_VecA, 15, v15->as_VMReg()->next(3) );
319
320 reg_def V16 ( SOC, SOC, Op_VecA, 16, v16->as_VMReg() );
321 reg_def V16_H ( SOC, SOC, Op_VecA, 16, v16->as_VMReg()->next() );
322 reg_def V16_J ( SOC, SOC, Op_VecA, 16, v16->as_VMReg()->next(2) );
323 reg_def V16_K ( SOC, SOC, Op_VecA, 16, v16->as_VMReg()->next(3) );
324
325 reg_def V17 ( SOC, SOC, Op_VecA, 17, v17->as_VMReg() );
326 reg_def V17_H ( SOC, SOC, Op_VecA, 17, v17->as_VMReg()->next() );
327 reg_def V17_J ( SOC, SOC, Op_VecA, 17, v17->as_VMReg()->next(2) );
328 reg_def V17_K ( SOC, SOC, Op_VecA, 17, v17->as_VMReg()->next(3) );
329
330 reg_def V18 ( SOC, SOC, Op_VecA, 18, v18->as_VMReg() );
331 reg_def V18_H ( SOC, SOC, Op_VecA, 18, v18->as_VMReg()->next() );
332 reg_def V18_J ( SOC, SOC, Op_VecA, 18, v18->as_VMReg()->next(2) );
333 reg_def V18_K ( SOC, SOC, Op_VecA, 18, v18->as_VMReg()->next(3) );
334
335 reg_def V19 ( SOC, SOC, Op_VecA, 19, v19->as_VMReg() );
336 reg_def V19_H ( SOC, SOC, Op_VecA, 19, v19->as_VMReg()->next() );
337 reg_def V19_J ( SOC, SOC, Op_VecA, 19, v19->as_VMReg()->next(2) );
338 reg_def V19_K ( SOC, SOC, Op_VecA, 19, v19->as_VMReg()->next(3) );
339
340 reg_def V20 ( SOC, SOC, Op_VecA, 20, v20->as_VMReg() );
341 reg_def V20_H ( SOC, SOC, Op_VecA, 20, v20->as_VMReg()->next() );
342 reg_def V20_J ( SOC, SOC, Op_VecA, 20, v20->as_VMReg()->next(2) );
343 reg_def V20_K ( SOC, SOC, Op_VecA, 20, v20->as_VMReg()->next(3) );
344
345 reg_def V21 ( SOC, SOC, Op_VecA, 21, v21->as_VMReg() );
346 reg_def V21_H ( SOC, SOC, Op_VecA, 21, v21->as_VMReg()->next() );
347 reg_def V21_J ( SOC, SOC, Op_VecA, 21, v21->as_VMReg()->next(2) );
348 reg_def V21_K ( SOC, SOC, Op_VecA, 21, v21->as_VMReg()->next(3) );
349
350 reg_def V22 ( SOC, SOC, Op_VecA, 22, v22->as_VMReg() );
351 reg_def V22_H ( SOC, SOC, Op_VecA, 22, v22->as_VMReg()->next() );
352 reg_def V22_J ( SOC, SOC, Op_VecA, 22, v22->as_VMReg()->next(2) );
353 reg_def V22_K ( SOC, SOC, Op_VecA, 22, v22->as_VMReg()->next(3) );
354
355 reg_def V23 ( SOC, SOC, Op_VecA, 23, v23->as_VMReg() );
356 reg_def V23_H ( SOC, SOC, Op_VecA, 23, v23->as_VMReg()->next() );
357 reg_def V23_J ( SOC, SOC, Op_VecA, 23, v23->as_VMReg()->next(2) );
358 reg_def V23_K ( SOC, SOC, Op_VecA, 23, v23->as_VMReg()->next(3) );
359
360 reg_def V24 ( SOC, SOC, Op_VecA, 24, v24->as_VMReg() );
361 reg_def V24_H ( SOC, SOC, Op_VecA, 24, v24->as_VMReg()->next() );
362 reg_def V24_J ( SOC, SOC, Op_VecA, 24, v24->as_VMReg()->next(2) );
363 reg_def V24_K ( SOC, SOC, Op_VecA, 24, v24->as_VMReg()->next(3) );
364
365 reg_def V25 ( SOC, SOC, Op_VecA, 25, v25->as_VMReg() );
366 reg_def V25_H ( SOC, SOC, Op_VecA, 25, v25->as_VMReg()->next() );
367 reg_def V25_J ( SOC, SOC, Op_VecA, 25, v25->as_VMReg()->next(2) );
368 reg_def V25_K ( SOC, SOC, Op_VecA, 25, v25->as_VMReg()->next(3) );
369
370 reg_def V26 ( SOC, SOC, Op_VecA, 26, v26->as_VMReg() );
371 reg_def V26_H ( SOC, SOC, Op_VecA, 26, v26->as_VMReg()->next() );
372 reg_def V26_J ( SOC, SOC, Op_VecA, 26, v26->as_VMReg()->next(2) );
373 reg_def V26_K ( SOC, SOC, Op_VecA, 26, v26->as_VMReg()->next(3) );
374
375 reg_def V27 ( SOC, SOC, Op_VecA, 27, v27->as_VMReg() );
376 reg_def V27_H ( SOC, SOC, Op_VecA, 27, v27->as_VMReg()->next() );
377 reg_def V27_J ( SOC, SOC, Op_VecA, 27, v27->as_VMReg()->next(2) );
378 reg_def V27_K ( SOC, SOC, Op_VecA, 27, v27->as_VMReg()->next(3) );
379
380 reg_def V28 ( SOC, SOC, Op_VecA, 28, v28->as_VMReg() );
381 reg_def V28_H ( SOC, SOC, Op_VecA, 28, v28->as_VMReg()->next() );
382 reg_def V28_J ( SOC, SOC, Op_VecA, 28, v28->as_VMReg()->next(2) );
383 reg_def V28_K ( SOC, SOC, Op_VecA, 28, v28->as_VMReg()->next(3) );
384
385 reg_def V29 ( SOC, SOC, Op_VecA, 29, v29->as_VMReg() );
386 reg_def V29_H ( SOC, SOC, Op_VecA, 29, v29->as_VMReg()->next() );
387 reg_def V29_J ( SOC, SOC, Op_VecA, 29, v29->as_VMReg()->next(2) );
388 reg_def V29_K ( SOC, SOC, Op_VecA, 29, v29->as_VMReg()->next(3) );
389
390 reg_def V30 ( SOC, SOC, Op_VecA, 30, v30->as_VMReg() );
391 reg_def V30_H ( SOC, SOC, Op_VecA, 30, v30->as_VMReg()->next() );
392 reg_def V30_J ( SOC, SOC, Op_VecA, 30, v30->as_VMReg()->next(2) );
393 reg_def V30_K ( SOC, SOC, Op_VecA, 30, v30->as_VMReg()->next(3) );
394
395 reg_def V31 ( SOC, SOC, Op_VecA, 31, v31->as_VMReg() );
396 reg_def V31_H ( SOC, SOC, Op_VecA, 31, v31->as_VMReg()->next() );
397 reg_def V31_J ( SOC, SOC, Op_VecA, 31, v31->as_VMReg()->next(2) );
398 reg_def V31_K ( SOC, SOC, Op_VecA, 31, v31->as_VMReg()->next(3) );
399
400 // ----------------------------
401 // Special Registers
402 // ----------------------------
403
404 // On riscv, the physical flag register is missing, so we use t1 instead,
405 // to bridge the RegFlag semantics in share/opto
406
407 reg_def RFLAGS (SOC, SOC, Op_RegFlags, 6, x6->as_VMReg() );
408
409 // Specify priority of register selection within phases of register
410 // allocation. Highest priority is first. A useful heuristic is to
411 // give registers a low priority when they are required by machine
412 // instructions, like EAX and EDX on I486, and choose no-save registers
413 // before save-on-call, & save-on-call before save-on-entry. Registers
414 // which participate in fixed calling sequences should come last.
415 // Registers which are used as pairs must fall on an even boundary.
416
417 alloc_class chunk0(
418 // volatiles
419 R7, R7_H,
420 R28, R28_H,
421 R29, R29_H,
422 R30, R30_H,
423 R31, R31_H,
424
425 // arg registers
426 R10, R10_H,
427 R11, R11_H,
428 R12, R12_H,
429 R13, R13_H,
430 R14, R14_H,
431 R15, R15_H,
432 R16, R16_H,
433 R17, R17_H,
434
435 // non-volatiles
436 R9, R9_H,
437 R18, R18_H,
438 R19, R19_H,
439 R20, R20_H,
440 R21, R21_H,
441 R22, R22_H,
442 R24, R24_H,
443 R25, R25_H,
444 R26, R26_H,
445
446 // non-allocatable registers
447 R23, R23_H, // java thread
448 R27, R27_H, // heapbase
449 R4, R4_H, // thread
450 R8, R8_H, // fp
451 R0, R0_H, // zero
452 R1, R1_H, // ra
453 R2, R2_H, // sp
454 R3, R3_H, // gp
455 );
456
457 alloc_class chunk1(
458
459 // no save
460 F0, F0_H,
461 F1, F1_H,
462 F2, F2_H,
463 F3, F3_H,
464 F4, F4_H,
465 F5, F5_H,
466 F6, F6_H,
467 F7, F7_H,
468 F28, F28_H,
469 F29, F29_H,
470 F30, F30_H,
471 F31, F31_H,
472
473 // arg registers
474 F10, F10_H,
475 F11, F11_H,
476 F12, F12_H,
477 F13, F13_H,
478 F14, F14_H,
479 F15, F15_H,
480 F16, F16_H,
481 F17, F17_H,
482
483 // non-volatiles
484 F8, F8_H,
485 F9, F9_H,
486 F18, F18_H,
487 F19, F19_H,
488 F20, F20_H,
489 F21, F21_H,
490 F22, F22_H,
491 F23, F23_H,
492 F24, F24_H,
493 F25, F25_H,
494 F26, F26_H,
495 F27, F27_H,
496 );
497
498 alloc_class chunk2(
499 V0, V0_H, V0_J, V0_K,
500 V1, V1_H, V1_J, V1_K,
501 V2, V2_H, V2_J, V2_K,
502 V3, V3_H, V3_J, V3_K,
503 V4, V4_H, V4_J, V4_K,
504 V5, V5_H, V5_J, V5_K,
505 V6, V6_H, V6_J, V6_K,
506 V7, V7_H, V7_J, V7_K,
507 V8, V8_H, V8_J, V8_K,
508 V9, V9_H, V9_J, V9_K,
509 V10, V10_H, V10_J, V10_K,
510 V11, V11_H, V11_J, V11_K,
511 V12, V12_H, V12_J, V12_K,
512 V13, V13_H, V13_J, V13_K,
513 V14, V14_H, V14_J, V14_K,
514 V15, V15_H, V15_J, V15_K,
515 V16, V16_H, V16_J, V16_K,
516 V17, V17_H, V17_J, V17_K,
517 V18, V18_H, V18_J, V18_K,
518 V19, V19_H, V19_J, V19_K,
519 V20, V20_H, V20_J, V20_K,
520 V21, V21_H, V21_J, V21_K,
521 V22, V22_H, V22_J, V22_K,
522 V23, V23_H, V23_J, V23_K,
523 V24, V24_H, V24_J, V24_K,
524 V25, V25_H, V25_J, V25_K,
525 V26, V26_H, V26_J, V26_K,
526 V27, V27_H, V27_J, V27_K,
527 V28, V28_H, V28_J, V28_K,
528 V29, V29_H, V29_J, V29_K,
529 V30, V30_H, V30_J, V30_K,
530 V31, V31_H, V31_J, V31_K,
531 );
532
533 alloc_class chunk3(RFLAGS);
534
535 //----------Architecture Description Register Classes--------------------------
536 // Several register classes are automatically defined based upon information in
537 // this architecture description.
538 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
539 // 2) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
540 //
541
542 // Class for all 32 bit general purpose registers
543 reg_class all_reg32(
544 R0,
545 R1,
546 R2,
547 R3,
548 R4,
549 R7,
550 R8,
551 R9,
552 R10,
553 R11,
554 R12,
555 R13,
556 R14,
557 R15,
558 R16,
559 R17,
560 R18,
561 R19,
562 R20,
563 R21,
564 R22,
565 R23,
566 R24,
567 R25,
568 R26,
569 R27,
570 R28,
571 R29,
572 R30,
573 R31
574 );
575
576 // Class for any 32 bit integer registers (excluding zr)
577 reg_class any_reg32 %{
578 return _ANY_REG32_mask;
579 %}
580
581 // Singleton class for R10 int register
582 reg_class int_r10_reg(R10);
583
584 // Singleton class for R12 int register
585 reg_class int_r12_reg(R12);
586
587 // Singleton class for R13 int register
588 reg_class int_r13_reg(R13);
589
590 // Singleton class for R14 int register
591 reg_class int_r14_reg(R14);
592
593 // Class for all long integer registers
594 reg_class all_reg(
595 R0, R0_H,
596 R1, R1_H,
597 R2, R2_H,
598 R3, R3_H,
599 R4, R4_H,
600 R7, R7_H,
601 R8, R8_H,
602 R9, R9_H,
603 R10, R10_H,
604 R11, R11_H,
605 R12, R12_H,
606 R13, R13_H,
607 R14, R14_H,
608 R15, R15_H,
609 R16, R16_H,
610 R17, R17_H,
611 R18, R18_H,
612 R19, R19_H,
613 R20, R20_H,
614 R21, R21_H,
615 R22, R22_H,
616 R23, R23_H,
617 R24, R24_H,
618 R25, R25_H,
619 R26, R26_H,
620 R27, R27_H,
621 R28, R28_H,
622 R29, R29_H,
623 R30, R30_H,
624 R31, R31_H
625 );
626
627 // Class for all long integer registers (excluding zr)
628 reg_class any_reg %{
629 return _ANY_REG_mask;
630 %}
631
632 // Class for non-allocatable 32 bit registers
633 reg_class non_allocatable_reg32(
634 R0, // zr
635 R1, // ra
636 R2, // sp
637 R3, // gp
638 R4, // tp
639 R23 // java thread
640 );
641
642 // Class for non-allocatable 64 bit registers
643 reg_class non_allocatable_reg(
644 R0, R0_H, // zr
645 R1, R1_H, // ra
646 R2, R2_H, // sp
647 R3, R3_H, // gp
648 R4, R4_H, // tp
649 R23, R23_H // java thread
650 );
651
652 // Class for all non-special integer registers
653 reg_class no_special_reg32 %{
654 return _NO_SPECIAL_REG32_mask;
655 %}
656
657 // Class for all non-special long integer registers
658 reg_class no_special_reg %{
659 return _NO_SPECIAL_REG_mask;
660 %}
661
662 reg_class ptr_reg %{
663 return _PTR_REG_mask;
664 %}
665
666 // Class for all non_special pointer registers
667 reg_class no_special_ptr_reg %{
668 return _NO_SPECIAL_PTR_REG_mask;
669 %}
670
671 // Class for all non_special pointer registers (excluding fp)
672 reg_class no_special_no_fp_ptr_reg %{
673 return _NO_SPECIAL_NO_FP_PTR_REG_mask;
674 %}
675
676 // Class for 64 bit register r10
677 reg_class r10_reg(
678 R10, R10_H
679 );
680
681 // Class for 64 bit register r11
682 reg_class r11_reg(
683 R11, R11_H
684 );
685
686 // Class for 64 bit register r12
687 reg_class r12_reg(
688 R12, R12_H
689 );
690
691 // Class for 64 bit register r13
692 reg_class r13_reg(
693 R13, R13_H
694 );
695
696 // Class for 64 bit register r14
697 reg_class r14_reg(
698 R14, R14_H
699 );
700
701 // Class for 64 bit register r15
702 reg_class r15_reg(
703 R15, R15_H
704 );
705
706 // Class for 64 bit register r16
707 reg_class r16_reg(
708 R16, R16_H
709 );
710
711 // Class for method register
712 reg_class method_reg(
713 R31, R31_H
714 );
715
716 // Class for java thread register
717 reg_class java_thread_reg(
718 R23, R23_H
719 );
720
721 reg_class r28_reg(
722 R28, R28_H
723 );
724
725 reg_class r29_reg(
726 R29, R29_H
727 );
728
729 reg_class r30_reg(
730 R30, R30_H
731 );
732
733 reg_class r31_reg(
734 R31, R31_H
735 );
736
737 // Class for zero registesr
738 reg_class zr_reg(
739 R0, R0_H
740 );
741
742 // Class for thread register
743 reg_class thread_reg(
744 R4, R4_H
745 );
746
747 // Class for frame pointer register
748 reg_class fp_reg(
749 R8, R8_H
750 );
751
752 // Class for link register
753 reg_class ra_reg(
754 R1, R1_H
755 );
756
757 // Class for long sp register
758 reg_class sp_reg(
759 R2, R2_H
760 );
761
762 // Class for all float registers
763 reg_class float_reg(
764 F0,
765 F1,
766 F2,
767 F3,
768 F4,
769 F5,
770 F6,
771 F7,
772 F8,
773 F9,
774 F10,
775 F11,
776 F12,
777 F13,
778 F14,
779 F15,
780 F16,
781 F17,
782 F18,
783 F19,
784 F20,
785 F21,
786 F22,
787 F23,
788 F24,
789 F25,
790 F26,
791 F27,
792 F28,
793 F29,
794 F30,
795 F31
796 );
797
798 // Double precision float registers have virtual `high halves' that
799 // are needed by the allocator.
800 // Class for all double registers
801 reg_class double_reg(
802 F0, F0_H,
803 F1, F1_H,
804 F2, F2_H,
805 F3, F3_H,
806 F4, F4_H,
807 F5, F5_H,
808 F6, F6_H,
809 F7, F7_H,
810 F8, F8_H,
811 F9, F9_H,
812 F10, F10_H,
813 F11, F11_H,
814 F12, F12_H,
815 F13, F13_H,
816 F14, F14_H,
817 F15, F15_H,
818 F16, F16_H,
819 F17, F17_H,
820 F18, F18_H,
821 F19, F19_H,
822 F20, F20_H,
823 F21, F21_H,
824 F22, F22_H,
825 F23, F23_H,
826 F24, F24_H,
827 F25, F25_H,
828 F26, F26_H,
829 F27, F27_H,
830 F28, F28_H,
831 F29, F29_H,
832 F30, F30_H,
833 F31, F31_H
834 );
835
836 // Class for RVV vector registers
837 // Note: v0, v30 and v31 are used as mask registers.
838 reg_class vectora_reg(
839 V1, V1_H, V1_J, V1_K,
840 V2, V2_H, V2_J, V2_K,
841 V3, V3_H, V3_J, V3_K,
842 V4, V4_H, V4_J, V4_K,
843 V5, V5_H, V5_J, V5_K,
844 V6, V6_H, V6_J, V6_K,
845 V7, V7_H, V7_J, V7_K,
846 V8, V8_H, V8_J, V8_K,
847 V9, V9_H, V9_J, V9_K,
848 V10, V10_H, V10_J, V10_K,
849 V11, V11_H, V11_J, V11_K,
850 V12, V12_H, V12_J, V12_K,
851 V13, V13_H, V13_J, V13_K,
852 V14, V14_H, V14_J, V14_K,
853 V15, V15_H, V15_J, V15_K,
854 V16, V16_H, V16_J, V16_K,
855 V17, V17_H, V17_J, V17_K,
856 V18, V18_H, V18_J, V18_K,
857 V19, V19_H, V19_J, V19_K,
858 V20, V20_H, V20_J, V20_K,
859 V21, V21_H, V21_J, V21_K,
860 V22, V22_H, V22_J, V22_K,
861 V23, V23_H, V23_J, V23_K,
862 V24, V24_H, V24_J, V24_K,
863 V25, V25_H, V25_J, V25_K,
864 V26, V26_H, V26_J, V26_K,
865 V27, V27_H, V27_J, V27_K,
866 V28, V28_H, V28_J, V28_K,
867 V29, V29_H, V29_J, V29_K
868 );
869
870 // Class for 64 bit register f0
871 reg_class f0_reg(
872 F0, F0_H
873 );
874
875 // Class for 64 bit register f1
876 reg_class f1_reg(
877 F1, F1_H
878 );
879
880 // Class for 64 bit register f2
881 reg_class f2_reg(
882 F2, F2_H
883 );
884
885 // Class for 64 bit register f3
886 reg_class f3_reg(
887 F3, F3_H
888 );
889
890 // class for vector register v1
891 reg_class v1_reg(
892 V1, V1_H, V1_J, V1_K
893 );
894
895 // class for vector register v2
896 reg_class v2_reg(
897 V2, V2_H, V2_J, V2_K
898 );
899
900 // class for vector register v3
901 reg_class v3_reg(
902 V3, V3_H, V3_J, V3_K
903 );
904
905 // class for vector register v4
906 reg_class v4_reg(
907 V4, V4_H, V4_J, V4_K
908 );
909
910 // class for vector register v5
911 reg_class v5_reg(
912 V5, V5_H, V5_J, V5_K
913 );
914
915 // class for vector register v6
916 reg_class v6_reg(
917 V6, V6_H, V6_J, V6_K
918 );
919
920 // class for vector register v7
921 reg_class v7_reg(
922 V7, V7_H, V7_J, V7_K
923 );
924
925 // class for vector register v8
926 reg_class v8_reg(
927 V8, V8_H, V8_J, V8_K
928 );
929
930 // class for vector register v9
931 reg_class v9_reg(
932 V9, V9_H, V9_J, V9_K
933 );
934
935 // class for vector register v10
936 reg_class v10_reg(
937 V10, V10_H, V10_J, V10_K
938 );
939
940 // class for vector register v11
941 reg_class v11_reg(
942 V11, V11_H, V11_J, V11_K
943 );
944
945 // class for condition codes
946 reg_class reg_flags(RFLAGS);
947
948 // Class for RVV v0 mask register
949 // https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#53-vector-masking
950 // The mask value used to control execution of a masked vector
951 // instruction is always supplied by vector register v0.
952 reg_class vmask_reg_v0 (
953 V0
954 );
955
956 // Class for RVV mask registers
957 // We need two more vmask registers to do the vector mask logical ops,
958 // so define v30, v31 as mask register too.
959 reg_class vmask_reg (
960 V0,
961 V30,
962 V31
963 );
964 %}
965
966 //----------DEFINITION BLOCK---------------------------------------------------
967 // Define name --> value mappings to inform the ADLC of an integer valued name
968 // Current support includes integer values in the range [0, 0x7FFFFFFF]
969 // Format:
970 // int_def <name> ( <int_value>, <expression>);
971 // Generated Code in ad_<arch>.hpp
972 // #define <name> (<expression>)
973 // // value == <int_value>
974 // Generated code in ad_<arch>.cpp adlc_verification()
975 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
976 //
977
978 // we follow the ppc-aix port in using a simple cost model which ranks
979 // register operations as cheap, memory ops as more expensive and
980 // branches as most expensive. the first two have a low as well as a
981 // normal cost. huge cost appears to be a way of saying don't do
982 // something
983
984 definitions %{
985 // The default cost (of a register move instruction).
986 int_def DEFAULT_COST ( 100, 100);
987 int_def ALU_COST ( 100, 1 * DEFAULT_COST); // unknown, const, arith, shift, slt,
988 // multi, auipc, nop, logical, move
989 int_def LOAD_COST ( 300, 3 * DEFAULT_COST); // load, fpload
990 int_def STORE_COST ( 100, 1 * DEFAULT_COST); // store, fpstore
991 int_def XFER_COST ( 300, 3 * DEFAULT_COST); // mfc, mtc, fcvt, fmove, fcmp
992 int_def FMVX_COST ( 100, 1 * DEFAULT_COST); // shuffles with no conversion
993 int_def BRANCH_COST ( 200, 2 * DEFAULT_COST); // branch, jmp, call
994 int_def IMUL_COST ( 1000, 10 * DEFAULT_COST); // imul
995 int_def IDIVSI_COST ( 3400, 34 * DEFAULT_COST); // idivsi
996 int_def IDIVDI_COST ( 6600, 66 * DEFAULT_COST); // idivdi
997 int_def FMUL_SINGLE_COST ( 500, 5 * DEFAULT_COST); // fmul, fmadd
998 int_def FMUL_DOUBLE_COST ( 700, 7 * DEFAULT_COST); // fmul, fmadd
999 int_def FDIV_COST ( 2000, 20 * DEFAULT_COST); // fdiv
1000 int_def FSQRT_COST ( 2500, 25 * DEFAULT_COST); // fsqrt
1001 int_def VOLATILE_REF_COST ( 1000, 10 * DEFAULT_COST);
1002 int_def CACHE_MISS_COST ( 2000, 20 * DEFAULT_COST); // typicall cache miss penalty
1003 %}
1004
1005
1006
1007 //----------SOURCE BLOCK-------------------------------------------------------
1008 // This is a block of C++ code which provides values, functions, and
1009 // definitions necessary in the rest of the architecture description
1010
1011 source_hpp %{
1012
1013 #include "asm/macroAssembler.hpp"
1014 #include "gc/shared/barrierSetAssembler.hpp"
1015 #include "gc/shared/cardTable.hpp"
1016 #include "gc/shared/cardTableBarrierSet.hpp"
1017 #include "gc/shared/collectedHeap.hpp"
1018 #include "opto/addnode.hpp"
1019 #include "opto/convertnode.hpp"
1020 #include "runtime/objectMonitor.hpp"
1021
1022 extern RegMask _ANY_REG32_mask;
1023 extern RegMask _ANY_REG_mask;
1024 extern RegMask _PTR_REG_mask;
1025 extern RegMask _NO_SPECIAL_REG32_mask;
1026 extern RegMask _NO_SPECIAL_REG_mask;
1027 extern RegMask _NO_SPECIAL_PTR_REG_mask;
1028 extern RegMask _NO_SPECIAL_NO_FP_PTR_REG_mask;
1029
1030 class CallStubImpl {
1031
1032 //--------------------------------------------------------------
1033 //---< Used for optimization in Compile::shorten_branches >---
1034 //--------------------------------------------------------------
1035
1036 public:
1037 // Size of call trampoline stub.
1038 static uint size_call_trampoline() {
1039 return 0; // no call trampolines on this platform
1040 }
1041
1042 // number of relocations needed by a call trampoline stub
1043 static uint reloc_call_trampoline() {
1044 return 0; // no call trampolines on this platform
1045 }
1046 };
1047
1048 class HandlerImpl {
1049
1050 public:
1051
1052 static int emit_deopt_handler(C2_MacroAssembler* masm);
1053
1054 static uint size_deopt_handler() {
1055 // count far call + j
1056 return NativeInstruction::instruction_size + MacroAssembler::far_branch_size();
1057 }
1058 };
1059
1060 class Node::PD {
1061 public:
1062 enum NodeFlags {
1063 _last_flag = Node::_last_flag
1064 };
1065 };
1066
1067 bool is_CAS(int opcode, bool maybe_volatile);
1068
1069 // predicate controlling translation of CompareAndSwapX
1070 bool needs_acquiring_load_reserved(const Node *load);
1071
1072 // predicate controlling addressing modes
1073 bool size_fits_all_mem_uses(AddPNode* addp, int shift);
1074 %}
1075
1076 source %{
1077
1078 // Derived RegMask with conditionally allocatable registers
1079
1080 RegMask _ANY_REG32_mask;
1081 RegMask _ANY_REG_mask;
1082 RegMask _PTR_REG_mask;
1083 RegMask _NO_SPECIAL_REG32_mask;
1084 RegMask _NO_SPECIAL_REG_mask;
1085 RegMask _NO_SPECIAL_PTR_REG_mask;
1086 RegMask _NO_SPECIAL_NO_FP_PTR_REG_mask;
1087
1088 void reg_mask_init() {
1089
1090 _ANY_REG32_mask.assignFrom(_ALL_REG32_mask);
1091 _ANY_REG32_mask.remove(OptoReg::as_OptoReg(x0->as_VMReg()));
1092
1093 _ANY_REG_mask.assignFrom(_ALL_REG_mask);
1094 _ANY_REG_mask.subtract(_ZR_REG_mask);
1095
1096 _PTR_REG_mask.assignFrom(_ALL_REG_mask);
1097 _PTR_REG_mask.subtract(_ZR_REG_mask);
1098
1099 _NO_SPECIAL_REG32_mask.assignFrom(_ALL_REG32_mask);
1100 _NO_SPECIAL_REG32_mask.subtract(_NON_ALLOCATABLE_REG32_mask);
1101
1102 _NO_SPECIAL_REG_mask.assignFrom(_ALL_REG_mask);
1103 _NO_SPECIAL_REG_mask.subtract(_NON_ALLOCATABLE_REG_mask);
1104
1105 _NO_SPECIAL_PTR_REG_mask.assignFrom(_ALL_REG_mask);
1106 _NO_SPECIAL_PTR_REG_mask.subtract(_NON_ALLOCATABLE_REG_mask);
1107
1108 // x27 is not allocatable when compressed oops is on
1109 if (UseCompressedOops) {
1110 _NO_SPECIAL_REG32_mask.remove(OptoReg::as_OptoReg(x27->as_VMReg()));
1111 _NO_SPECIAL_REG_mask.remove(OptoReg::as_OptoReg(x27->as_VMReg()));
1112 _NO_SPECIAL_PTR_REG_mask.remove(OptoReg::as_OptoReg(x27->as_VMReg()));
1113 }
1114
1115 // x8 is not allocatable when PreserveFramePointer is on
1116 if (PreserveFramePointer) {
1117 _NO_SPECIAL_REG32_mask.remove(OptoReg::as_OptoReg(x8->as_VMReg()));
1118 _NO_SPECIAL_REG_mask.remove(OptoReg::as_OptoReg(x8->as_VMReg()));
1119 _NO_SPECIAL_PTR_REG_mask.remove(OptoReg::as_OptoReg(x8->as_VMReg()));
1120 }
1121
1122 _NO_SPECIAL_NO_FP_PTR_REG_mask.assignFrom(_NO_SPECIAL_PTR_REG_mask);
1123 _NO_SPECIAL_NO_FP_PTR_REG_mask.remove(OptoReg::as_OptoReg(x8->as_VMReg()));
1124 }
1125
1126 void PhaseOutput::pd_perform_mach_node_analysis() {
1127 }
1128
1129 int MachNode::pd_alignment_required() const {
1130 return 1;
1131 }
1132
1133 int MachNode::compute_padding(int current_offset) const {
1134 return 0;
1135 }
1136
1137 // is_CAS(int opcode, bool maybe_volatile)
1138 //
1139 // return true if opcode is one of the possible CompareAndSwapX
1140 // values otherwise false.
1141 bool is_CAS(int opcode, bool maybe_volatile)
1142 {
1143 switch (opcode) {
1144 // We handle these
1145 case Op_CompareAndSwapI:
1146 case Op_CompareAndSwapL:
1147 case Op_CompareAndSwapP:
1148 case Op_CompareAndSwapN:
1149 case Op_CompareAndSwapB:
1150 case Op_CompareAndSwapS:
1151 case Op_GetAndSetI:
1152 case Op_GetAndSetL:
1153 case Op_GetAndSetP:
1154 case Op_GetAndSetN:
1155 case Op_GetAndAddI:
1156 case Op_GetAndAddL:
1157 return true;
1158 case Op_CompareAndExchangeI:
1159 case Op_CompareAndExchangeN:
1160 case Op_CompareAndExchangeB:
1161 case Op_CompareAndExchangeS:
1162 case Op_CompareAndExchangeL:
1163 case Op_CompareAndExchangeP:
1164 case Op_WeakCompareAndSwapB:
1165 case Op_WeakCompareAndSwapS:
1166 case Op_WeakCompareAndSwapI:
1167 case Op_WeakCompareAndSwapL:
1168 case Op_WeakCompareAndSwapP:
1169 case Op_WeakCompareAndSwapN:
1170 return maybe_volatile;
1171 default:
1172 return false;
1173 }
1174 }
1175
1176 constexpr uint64_t MAJIK_DWORD = 0xabbaabbaabbaabbaull;
1177
1178 // predicate controlling translation of CAS
1179 //
1180 // returns true if CAS needs to use an acquiring load otherwise false
1181 bool needs_acquiring_load_reserved(const Node *n)
1182 {
1183 assert(n != nullptr && is_CAS(n->Opcode(), true), "expecting a compare and swap");
1184
1185 LoadStoreNode* ldst = n->as_LoadStore();
1186 if (n != nullptr && is_CAS(n->Opcode(), false)) {
1187 assert(ldst != nullptr && ldst->trailing_membar() != nullptr, "expected trailing membar");
1188 } else {
1189 return ldst != nullptr && ldst->trailing_membar() != nullptr;
1190 }
1191 // so we can just return true here
1192 return true;
1193 }
1194 #define __ masm->
1195
1196 // advance declarations for helper functions to convert register
1197 // indices to register objects
1198
1199 // the ad file has to provide implementations of certain methods
1200 // expected by the generic code
1201 //
1202 // REQUIRED FUNCTIONALITY
1203
1204 //=============================================================================
1205
1206 // !!!!! Special hack to get all types of calls to specify the byte offset
1207 // from the start of the call to the point where the return address
1208 // will point.
1209
1210 int MachCallStaticJavaNode::ret_addr_offset()
1211 {
1212 return 3 * NativeInstruction::instruction_size; // auipc + ld + jalr
1213 }
1214
1215 int MachCallDynamicJavaNode::ret_addr_offset()
1216 {
1217 return NativeMovConstReg::movptr2_instruction_size + (3 * NativeInstruction::instruction_size); // movptr2, auipc + ld + jal
1218 }
1219
1220 int MachCallRuntimeNode::ret_addr_offset() {
1221 // For address inside the code cache the call will be:
1222 // auipc + jalr
1223 // For real runtime callouts it will be 8 instructions
1224 // see riscv_enc_java_to_runtime
1225 // la(t0, retaddr) -> auipc + addi
1226 // sd(t0, Address(xthread, JavaThread::last_Java_pc_offset())) -> sd
1227 // movptr(t1, addr, offset, t0) -> lui + lui + slli + add
1228 // jalr(t1, offset) -> jalr
1229 if (CodeCache::contains(_entry_point)) {
1230 return 2 * NativeInstruction::instruction_size;
1231 } else {
1232 return 8 * NativeInstruction::instruction_size;
1233 }
1234 }
1235
1236 //
1237 // Compute padding required for nodes which need alignment
1238 //
1239
1240 // With RVC a call instruction may get 2-byte aligned.
1241 // The address of the call instruction needs to be 4-byte aligned to
1242 // ensure that it does not span a cache line so that it can be patched.
1243 int CallStaticJavaDirectNode::compute_padding(int current_offset) const
1244 {
1245 // to make sure the address of jal 4-byte aligned.
1246 return align_up(current_offset, alignment_required()) - current_offset;
1247 }
1248
1249 // With RVC a call instruction may get 2-byte aligned.
1250 // The address of the call instruction needs to be 4-byte aligned to
1251 // ensure that it does not span a cache line so that it can be patched.
1252 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const
1253 {
1254 // skip the movptr2 in MacroAssembler::ic_call():
1255 // lui, lui, slli, add, addi
1256 // Though movptr2() has already 4-byte aligned with or without RVC,
1257 // We need to prevent from further changes by explicitly calculating the size.
1258 current_offset += NativeMovConstReg::movptr2_instruction_size;
1259 // to make sure the address of jal 4-byte aligned.
1260 return align_up(current_offset, alignment_required()) - current_offset;
1261 }
1262
1263 int CallRuntimeDirectNode::compute_padding(int current_offset) const
1264 {
1265 return align_up(current_offset, alignment_required()) - current_offset;
1266 }
1267
1268 int CallLeafDirectNode::compute_padding(int current_offset) const
1269 {
1270 return align_up(current_offset, alignment_required()) - current_offset;
1271 }
1272
1273 int CallLeafDirectVectorNode::compute_padding(int current_offset) const
1274 {
1275 return align_up(current_offset, alignment_required()) - current_offset;
1276 }
1277
1278 int CallLeafNoFPDirectNode::compute_padding(int current_offset) const
1279 {
1280 return align_up(current_offset, alignment_required()) - current_offset;
1281 }
1282
1283 //=============================================================================
1284
1285 #ifndef PRODUCT
1286 void MachBreakpointNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1287 assert_cond(st != nullptr);
1288 st->print("BREAKPOINT");
1289 }
1290 #endif
1291
1292 void MachBreakpointNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
1293 __ ebreak();
1294 }
1295
1296 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
1297 return MachNode::size(ra_);
1298 }
1299
1300 //=============================================================================
1301
1302 #ifndef PRODUCT
1303 void MachNopNode::format(PhaseRegAlloc*, outputStream* st) const {
1304 st->print("nop \t# %d bytes pad for loops and calls", _count);
1305 }
1306 #endif
1307
1308 void MachNopNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc*) const {
1309 Assembler::CompressibleScope scope(masm); // nops shall be 2-byte under RVC for alignment purposes.
1310 for (int i = 0; i < _count; i++) {
1311 __ nop();
1312 }
1313 }
1314
1315 uint MachNopNode::size(PhaseRegAlloc*) const {
1316 return _count * (UseRVC ? NativeInstruction::compressed_instruction_size : NativeInstruction::instruction_size);
1317 }
1318
1319 //=============================================================================
1320 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::EMPTY;
1321
1322 int ConstantTable::calculate_table_base_offset() const {
1323 return 0; // absolute addressing, no offset
1324 }
1325
1326 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
1327 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
1328 ShouldNotReachHere();
1329 }
1330
1331 void MachConstantBaseNode::emit(C2_MacroAssembler* masm, PhaseRegAlloc* ra_) const {
1332 // Empty encoding
1333 }
1334
1335 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
1336 return 0;
1337 }
1338
1339 #ifndef PRODUCT
1340 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1341 assert_cond(st != nullptr);
1342 st->print("-- \t// MachConstantBaseNode (empty encoding)");
1343 }
1344 #endif
1345
1346 #ifndef PRODUCT
1347 void MachPrologNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1348 assert_cond(st != nullptr && ra_ != nullptr);
1349 Compile* C = ra_->C;
1350
1351 int framesize = C->output()->frame_slots() << LogBytesPerInt;
1352
1353 if (C->output()->need_stack_bang(framesize)) {
1354 st->print("# stack bang size=%d\n\t", framesize);
1355 }
1356
1357 st->print("sub sp, sp, #%d\n\t", framesize);
1358 st->print("sd fp, [sp, #%d]\n\t", framesize - 2 * wordSize);
1359 st->print("sd ra, [sp, #%d]\n\t", framesize - wordSize);
1360 if (PreserveFramePointer) { st->print("add fp, sp, #%d\n\t", framesize); }
1361
1362 if (VerifyStackAtCalls) {
1363 st->print("mv t2, %ld\n\t", MAJIK_DWORD);
1364 st->print("sd t2, [sp, #%d]\n\t", framesize - 3 * wordSize);
1365 }
1366
1367 if (C->stub_function() == nullptr) {
1368 st->print("ld t0, [guard]\n\t");
1369 st->print("membar LoadLoad\n\t");
1370 st->print("ld t1, [xthread, #thread_disarmed_guard_value_offset]\n\t");
1371 st->print("beq t0, t1, skip\n\t");
1372 st->print("jalr #nmethod_entry_barrier_stub\n\t");
1373 st->print("j skip\n\t");
1374 st->print("guard: int\n\t");
1375 st->print("skip:\n\t");
1376 }
1377 }
1378 #endif
1379
1380 void MachPrologNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
1381 assert_cond(ra_ != nullptr);
1382 Compile* C = ra_->C;
1383
1384 // n.b. frame size includes space for return pc and fp
1385 const int framesize = C->output()->frame_size_in_bytes();
1386
1387 assert_cond(C != nullptr);
1388
1389 if (C->clinit_barrier_on_entry()) {
1390 assert(!C->method()->holder()->is_not_initialized(), "initialization should have been started");
1391
1392 Label L_skip_barrier;
1393
1394 __ mov_metadata(t1, C->method()->holder()->constant_encoding());
1395 __ clinit_barrier(t1, t0, &L_skip_barrier);
1396 __ far_jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub()));
1397 __ bind(L_skip_barrier);
1398 }
1399
1400 int bangsize = C->output()->bang_size_in_bytes();
1401 if (C->output()->need_stack_bang(bangsize)) {
1402 __ generate_stack_overflow_check(bangsize);
1403 }
1404
1405 __ build_frame(framesize);
1406
1407 if (VerifyStackAtCalls) {
1408 __ mv(t2, MAJIK_DWORD);
1409 __ sd(t2, Address(sp, framesize - 3 * wordSize));
1410 }
1411
1412 if (C->stub_function() == nullptr) {
1413 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
1414 // Dummy labels for just measuring the code size
1415 Label dummy_slow_path;
1416 Label dummy_continuation;
1417 Label dummy_guard;
1418 Label* slow_path = &dummy_slow_path;
1419 Label* continuation = &dummy_continuation;
1420 Label* guard = &dummy_guard;
1421 if (!Compile::current()->output()->in_scratch_emit_size()) {
1422 // Use real labels from actual stub when not emitting code for purpose of measuring its size
1423 C2EntryBarrierStub* stub = new (Compile::current()->comp_arena()) C2EntryBarrierStub();
1424 Compile::current()->output()->add_stub(stub);
1425 slow_path = &stub->entry();
1426 continuation = &stub->continuation();
1427 guard = &stub->guard();
1428 }
1429 // In the C2 code, we move the non-hot part of nmethod entry barriers out-of-line to a stub.
1430 bs->nmethod_entry_barrier(masm, slow_path, continuation, guard);
1431 }
1432
1433 C->output()->set_frame_complete(__ offset());
1434
1435 if (C->has_mach_constant_base_node()) {
1436 // NOTE: We set the table base offset here because users might be
1437 // emitted before MachConstantBaseNode.
1438 ConstantTable& constant_table = C->output()->constant_table();
1439 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
1440 }
1441 }
1442
1443 uint MachPrologNode::size(PhaseRegAlloc* ra_) const
1444 {
1445 assert_cond(ra_ != nullptr);
1446 return MachNode::size(ra_); // too many variables; just compute it
1447 // the hard way
1448 }
1449
1450 int MachPrologNode::reloc() const
1451 {
1452 return 0;
1453 }
1454
1455 //=============================================================================
1456
1457 #ifndef PRODUCT
1458 void MachEpilogNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1459 assert_cond(st != nullptr && ra_ != nullptr);
1460 Compile* C = ra_->C;
1461 assert_cond(C != nullptr);
1462 int framesize = C->output()->frame_size_in_bytes();
1463
1464 st->print("# pop frame %d\n\t", framesize);
1465
1466 if (framesize == 0) {
1467 st->print("ld ra, [sp,#%d]\n\t", (2 * wordSize));
1468 st->print("ld fp, [sp,#%d]\n\t", (3 * wordSize));
1469 st->print("add sp, sp, #%d\n\t", (2 * wordSize));
1470 } else {
1471 st->print("add sp, sp, #%d\n\t", framesize);
1472 st->print("ld ra, [sp,#%d]\n\t", - 2 * wordSize);
1473 st->print("ld fp, [sp,#%d]\n\t", - wordSize);
1474 }
1475
1476 if (do_polling() && C->is_method_compilation()) {
1477 st->print("# test polling word\n\t");
1478 st->print("ld t0, [xthread,#%d]\n\t", in_bytes(JavaThread::polling_word_offset()));
1479 st->print("bgtu sp, t0, #slow_path");
1480 }
1481 }
1482 #endif
1483
1484 void MachEpilogNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
1485 assert_cond(ra_ != nullptr);
1486 Compile* C = ra_->C;
1487 assert_cond(C != nullptr);
1488 int framesize = C->output()->frame_size_in_bytes();
1489
1490 __ remove_frame(framesize);
1491
1492 if (StackReservedPages > 0 && C->has_reserved_stack_access()) {
1493 __ reserved_stack_check();
1494 }
1495
1496 if (do_polling() && C->is_method_compilation()) {
1497 Label dummy_label;
1498 Label* code_stub = &dummy_label;
1499 if (!C->output()->in_scratch_emit_size()) {
1500 C2SafepointPollStub* stub = new (C->comp_arena()) C2SafepointPollStub(__ offset());
1501 C->output()->add_stub(stub);
1502 code_stub = &stub->entry();
1503 }
1504 __ relocate(relocInfo::poll_return_type);
1505 __ safepoint_poll(*code_stub, true /* at_return */, true /* in_nmethod */);
1506 }
1507 }
1508
1509 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
1510 assert_cond(ra_ != nullptr);
1511 // Variable size. Determine dynamically.
1512 return MachNode::size(ra_);
1513 }
1514
1515 int MachEpilogNode::reloc() const {
1516 // Return number of relocatable values contained in this instruction.
1517 return 1; // 1 for polling page.
1518 }
1519 const Pipeline * MachEpilogNode::pipeline() const {
1520 return MachNode::pipeline_class();
1521 }
1522
1523 //=============================================================================
1524
1525 // Figure out which register class each belongs in: rc_int, rc_float or
1526 // rc_stack.
1527 enum RC { rc_bad, rc_int, rc_float, rc_vector, rc_stack };
1528
1529 static enum RC rc_class(OptoReg::Name reg) {
1530
1531 if (reg == OptoReg::Bad) {
1532 return rc_bad;
1533 }
1534
1535 // we have 30 int registers * 2 halves
1536 // (t0 and t1 are omitted)
1537 int slots_of_int_registers = Register::max_slots_per_register * (Register::number_of_registers - 2);
1538 if (reg < slots_of_int_registers) {
1539 return rc_int;
1540 }
1541
1542 // we have 32 float register * 2 halves
1543 int slots_of_float_registers = FloatRegister::max_slots_per_register * FloatRegister::number_of_registers;
1544 if (reg < slots_of_int_registers + slots_of_float_registers) {
1545 return rc_float;
1546 }
1547
1548 // we have 32 vector register * 4 halves
1549 int slots_of_vector_registers = VectorRegister::max_slots_per_register * VectorRegister::number_of_registers;
1550 if (reg < slots_of_int_registers + slots_of_float_registers + slots_of_vector_registers) {
1551 return rc_vector;
1552 }
1553
1554 // Between vector regs & stack is the flags regs.
1555 assert(OptoReg::is_stack(reg), "blow up if spilling flags");
1556
1557 return rc_stack;
1558 }
1559
1560 uint MachSpillCopyNode::implementation(C2_MacroAssembler *masm, PhaseRegAlloc *ra_, bool do_size, outputStream *st) const {
1561 assert_cond(ra_ != nullptr);
1562 Compile* C = ra_->C;
1563
1564 // Get registers to move.
1565 OptoReg::Name src_hi = ra_->get_reg_second(in(1));
1566 OptoReg::Name src_lo = ra_->get_reg_first(in(1));
1567 OptoReg::Name dst_hi = ra_->get_reg_second(this);
1568 OptoReg::Name dst_lo = ra_->get_reg_first(this);
1569
1570 enum RC src_hi_rc = rc_class(src_hi);
1571 enum RC src_lo_rc = rc_class(src_lo);
1572 enum RC dst_hi_rc = rc_class(dst_hi);
1573 enum RC dst_lo_rc = rc_class(dst_lo);
1574
1575 assert(src_lo != OptoReg::Bad && dst_lo != OptoReg::Bad, "must move at least 1 register");
1576
1577 if (src_hi != OptoReg::Bad && !bottom_type()->isa_pvectmask()) {
1578 assert((src_lo & 1) == 0 && src_lo + 1 == src_hi &&
1579 (dst_lo & 1) == 0 && dst_lo + 1 == dst_hi,
1580 "expected aligned-adjacent pairs");
1581 }
1582
1583 if (src_lo == dst_lo && src_hi == dst_hi) {
1584 return 0; // Self copy, no move.
1585 }
1586
1587 bool is64 = (src_lo & 1) == 0 && src_lo + 1 == src_hi &&
1588 (dst_lo & 1) == 0 && dst_lo + 1 == dst_hi;
1589 int src_offset = ra_->reg2offset(src_lo);
1590 int dst_offset = ra_->reg2offset(dst_lo);
1591
1592 if (bottom_type()->isa_vect() != nullptr) {
1593 uint ireg = ideal_reg();
1594 if (ireg == Op_VecA && masm) {
1595 int vector_reg_size_in_bytes = Matcher::scalable_vector_reg_size(T_BYTE);
1596 if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
1597 // stack to stack
1598 __ spill_copy_vector_stack_to_stack(src_offset, dst_offset,
1599 vector_reg_size_in_bytes);
1600 } else if (src_lo_rc == rc_vector && dst_lo_rc == rc_stack) {
1601 // vpr to stack
1602 __ spill(as_VectorRegister(Matcher::_regEncode[src_lo]), ra_->reg2offset(dst_lo));
1603 } else if (src_lo_rc == rc_stack && dst_lo_rc == rc_vector) {
1604 // stack to vpr
1605 __ unspill(as_VectorRegister(Matcher::_regEncode[dst_lo]), ra_->reg2offset(src_lo));
1606 } else if (src_lo_rc == rc_vector && dst_lo_rc == rc_vector) {
1607 // vpr to vpr
1608 __ vsetvli_helper(T_BYTE, MaxVectorSize);
1609 __ vmv_v_v(as_VectorRegister(Matcher::_regEncode[dst_lo]), as_VectorRegister(Matcher::_regEncode[src_lo]));
1610 } else {
1611 ShouldNotReachHere();
1612 }
1613 } else if (bottom_type()->isa_pvectmask() && masm) {
1614 int vmask_size_in_bytes = Matcher::scalable_predicate_reg_slots() * 32 / 8;
1615 if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
1616 // stack to stack
1617 __ spill_copy_vmask_stack_to_stack(src_offset, dst_offset,
1618 vmask_size_in_bytes);
1619 } else if (src_lo_rc == rc_vector && dst_lo_rc == rc_stack) {
1620 // vmask to stack
1621 __ spill_vmask(as_VectorRegister(Matcher::_regEncode[src_lo]), ra_->reg2offset(dst_lo));
1622 } else if (src_lo_rc == rc_stack && dst_lo_rc == rc_vector) {
1623 // stack to vmask
1624 __ unspill_vmask(as_VectorRegister(Matcher::_regEncode[dst_lo]), ra_->reg2offset(src_lo));
1625 } else if (src_lo_rc == rc_vector && dst_lo_rc == rc_vector) {
1626 // vmask to vmask
1627 __ vsetvli_helper(T_BYTE, MaxVectorSize >> 3);
1628 __ vmv_v_v(as_VectorRegister(Matcher::_regEncode[dst_lo]), as_VectorRegister(Matcher::_regEncode[src_lo]));
1629 } else {
1630 ShouldNotReachHere();
1631 }
1632 }
1633 } else if (masm != nullptr) {
1634 switch (src_lo_rc) {
1635 case rc_int:
1636 if (dst_lo_rc == rc_int) { // gpr --> gpr copy
1637 if (!is64 && this->ideal_reg() != Op_RegI) { // zero extended for narrow oop or klass
1638 __ zext(as_Register(Matcher::_regEncode[dst_lo]), as_Register(Matcher::_regEncode[src_lo]), 32);
1639 } else {
1640 __ mv(as_Register(Matcher::_regEncode[dst_lo]), as_Register(Matcher::_regEncode[src_lo]));
1641 }
1642 } else if (dst_lo_rc == rc_float) { // gpr --> fpr copy
1643 if (is64) {
1644 __ fmv_d_x(as_FloatRegister(Matcher::_regEncode[dst_lo]),
1645 as_Register(Matcher::_regEncode[src_lo]));
1646 } else {
1647 __ fmv_w_x(as_FloatRegister(Matcher::_regEncode[dst_lo]),
1648 as_Register(Matcher::_regEncode[src_lo]));
1649 }
1650 } else { // gpr --> stack spill
1651 assert(dst_lo_rc == rc_stack, "spill to bad register class");
1652 __ spill(as_Register(Matcher::_regEncode[src_lo]), is64, dst_offset);
1653 }
1654 break;
1655 case rc_float:
1656 if (dst_lo_rc == rc_int) { // fpr --> gpr copy
1657 if (is64) {
1658 __ fmv_x_d(as_Register(Matcher::_regEncode[dst_lo]),
1659 as_FloatRegister(Matcher::_regEncode[src_lo]));
1660 } else {
1661 __ fmv_x_w(as_Register(Matcher::_regEncode[dst_lo]),
1662 as_FloatRegister(Matcher::_regEncode[src_lo]));
1663 }
1664 } else if (dst_lo_rc == rc_float) { // fpr --> fpr copy
1665 if (is64) {
1666 __ fmv_d(as_FloatRegister(Matcher::_regEncode[dst_lo]),
1667 as_FloatRegister(Matcher::_regEncode[src_lo]));
1668 } else {
1669 __ fmv_s(as_FloatRegister(Matcher::_regEncode[dst_lo]),
1670 as_FloatRegister(Matcher::_regEncode[src_lo]));
1671 }
1672 } else { // fpr --> stack spill
1673 assert(dst_lo_rc == rc_stack, "spill to bad register class");
1674 __ spill(as_FloatRegister(Matcher::_regEncode[src_lo]),
1675 is64, dst_offset);
1676 }
1677 break;
1678 case rc_stack:
1679 if (dst_lo_rc == rc_int) { // stack --> gpr load
1680 if (this->ideal_reg() == Op_RegI) {
1681 __ unspill(as_Register(Matcher::_regEncode[dst_lo]), is64, src_offset);
1682 } else { // // zero extended for narrow oop or klass
1683 __ unspillu(as_Register(Matcher::_regEncode[dst_lo]), is64, src_offset);
1684 }
1685 } else if (dst_lo_rc == rc_float) { // stack --> fpr load
1686 __ unspill(as_FloatRegister(Matcher::_regEncode[dst_lo]),
1687 is64, src_offset);
1688 } else { // stack --> stack copy
1689 assert(dst_lo_rc == rc_stack, "spill to bad register class");
1690 if (this->ideal_reg() == Op_RegI) {
1691 __ unspill(t0, is64, src_offset);
1692 } else { // zero extended for narrow oop or klass
1693 __ unspillu(t0, is64, src_offset);
1694 }
1695 __ spill(t0, is64, dst_offset);
1696 }
1697 break;
1698 default:
1699 ShouldNotReachHere();
1700 }
1701 }
1702
1703 if (st != nullptr) {
1704 st->print("spill ");
1705 if (src_lo_rc == rc_stack) {
1706 st->print("[sp, #%d] -> ", src_offset);
1707 } else {
1708 st->print("%s -> ", Matcher::regName[src_lo]);
1709 }
1710 if (dst_lo_rc == rc_stack) {
1711 st->print("[sp, #%d]", dst_offset);
1712 } else {
1713 st->print("%s", Matcher::regName[dst_lo]);
1714 }
1715 if (bottom_type()->isa_vect() && !bottom_type()->isa_pvectmask()) {
1716 int vsize = 0;
1717 if (ideal_reg() == Op_VecA) {
1718 vsize = Matcher::scalable_vector_reg_size(T_BYTE) * 8;
1719 } else {
1720 ShouldNotReachHere();
1721 }
1722 st->print("\t# vector spill size = %d", vsize);
1723 } else if (ideal_reg() == Op_RegVectMask) {
1724 assert(Matcher::supports_scalable_vector(), "bad register type for spill");
1725 int vsize = Matcher::scalable_predicate_reg_slots() * 32;
1726 st->print("\t# vmask spill size = %d", vsize);
1727 } else {
1728 st->print("\t# spill size = %d", is64 ? 64 : 32);
1729 }
1730 }
1731
1732 return 0;
1733 }
1734
1735 #ifndef PRODUCT
1736 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1737 if (ra_ == nullptr) {
1738 st->print("N%d = SpillCopy(N%d)", _idx, in(1)->_idx);
1739 } else {
1740 implementation(nullptr, ra_, false, st);
1741 }
1742 }
1743 #endif
1744
1745 void MachSpillCopyNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
1746 implementation(masm, ra_, false, nullptr);
1747 }
1748
1749 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1750 return MachNode::size(ra_);
1751 }
1752
1753 //=============================================================================
1754
1755 #ifndef PRODUCT
1756 void BoxLockNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1757 assert_cond(ra_ != nullptr && st != nullptr);
1758 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1759 int reg = ra_->get_reg_first(this);
1760 st->print("add %s, sp, #%d\t# box lock",
1761 Matcher::regName[reg], offset);
1762 }
1763 #endif
1764
1765 void BoxLockNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
1766 Assembler::IncompressibleScope scope(masm); // Fixed length: see BoxLockNode::size()
1767
1768 assert_cond(ra_ != nullptr);
1769 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1770 int reg = ra_->get_encode(this);
1771
1772 if (Assembler::is_simm12(offset)) {
1773 __ addi(as_Register(reg), sp, offset);
1774 } else {
1775 __ li32(t0, offset);
1776 __ add(as_Register(reg), sp, t0);
1777 }
1778 }
1779
1780 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1781 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_).
1782 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1783
1784 if (Assembler::is_simm12(offset)) {
1785 return NativeInstruction::instruction_size;
1786 } else {
1787 return 3 * NativeInstruction::instruction_size; // lui + addiw + add;
1788 }
1789 }
1790
1791 //=============================================================================
1792
1793 #ifndef PRODUCT
1794 void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1795 {
1796 assert_cond(st != nullptr);
1797 st->print_cr("# MachUEPNode");
1798 st->print_cr("\tlwu t1, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass");
1799 st->print_cr("\tlwu t2, [t0 + CompiledICData::speculated_klass_offset()]\t# compressed klass");
1800 st->print_cr("\tbeq t1, t2, ic_hit");
1801 st->print_cr("\tj, SharedRuntime::_ic_miss_stub\t # Inline cache check");
1802 st->print_cr("\tic_hit:");
1803 }
1804 #endif
1805
1806 void MachUEPNode::emit(C2_MacroAssembler* masm, PhaseRegAlloc* ra_) const
1807 {
1808 // This is the unverified entry point.
1809 __ ic_check(CodeEntryAlignment);
1810
1811 // ic_check() aligns to CodeEntryAlignment >= InteriorEntryAlignment(min 16) > NativeInstruction::instruction_size(4).
1812 assert(((__ offset()) % CodeEntryAlignment) == 0, "Misaligned verified entry point");
1813 }
1814
1815 uint MachUEPNode::size(PhaseRegAlloc* ra_) const
1816 {
1817 assert_cond(ra_ != nullptr);
1818 return MachNode::size(ra_);
1819 }
1820
1821 // REQUIRED EMIT CODE
1822
1823 //=============================================================================
1824
1825 // Emit deopt handler code.
1826 int HandlerImpl::emit_deopt_handler(C2_MacroAssembler* masm)
1827 {
1828 address base = __ start_a_stub(size_deopt_handler());
1829 if (base == nullptr) {
1830 ciEnv::current()->record_failure("CodeCache is full");
1831 return 0; // CodeBuffer::expand failed
1832 }
1833 int offset = __ offset();
1834
1835 Label start;
1836 __ bind(start);
1837
1838 __ far_call(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
1839
1840 int entry_offset = __ offset();
1841 __ j(start);
1842
1843 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1844 assert(__ offset() - entry_offset >= NativePostCallNop::first_check_size,
1845 "out of bounds read in post-call NOP check");
1846 __ end_a_stub();
1847 return entry_offset;
1848
1849 }
1850 // REQUIRED MATCHER CODE
1851
1852 //=============================================================================
1853
1854 bool Matcher::match_rule_supported(int opcode) {
1855 if (!has_match_rule(opcode)) {
1856 return false;
1857 }
1858
1859 switch (opcode) {
1860 case Op_OnSpinWait:
1861 return VM_Version::supports_on_spin_wait();
1862 case Op_CacheWB: // fall through
1863 case Op_CacheWBPreSync: // fall through
1864 case Op_CacheWBPostSync:
1865 if (!VM_Version::supports_data_cache_line_flush()) {
1866 return false;
1867 }
1868 break;
1869
1870 case Op_StrCompressedCopy: // fall through
1871 case Op_StrInflatedCopy: // fall through
1872 case Op_CountPositives: // fall through
1873 case Op_EncodeISOArray:
1874 return UseRVV;
1875
1876 case Op_PopCountI:
1877 case Op_PopCountL:
1878 return UsePopCountInstruction;
1879
1880 case Op_ReverseI:
1881 case Op_ReverseL:
1882 return UseZbkb;
1883
1884 case Op_ReverseBytesI:
1885 case Op_ReverseBytesL:
1886 case Op_ReverseBytesS:
1887 case Op_ReverseBytesUS:
1888 case Op_RotateRight:
1889 case Op_RotateLeft:
1890 case Op_CountLeadingZerosI:
1891 case Op_CountLeadingZerosL:
1892 case Op_CountTrailingZerosI:
1893 case Op_CountTrailingZerosL:
1894 return UseZbb;
1895
1896 case Op_FmaF:
1897 case Op_FmaD:
1898 return UseFMA;
1899
1900 case Op_ConvHF2F:
1901 case Op_ConvF2HF:
1902 return VM_Version::supports_float16_float_conversion();
1903 case Op_ReinterpretS2HF:
1904 case Op_ReinterpretHF2S:
1905 return UseZfh || UseZfhmin;
1906 case Op_AddHF:
1907 case Op_DivHF:
1908 case Op_FmaHF:
1909 case Op_MaxHF:
1910 case Op_MinHF:
1911 case Op_MulHF:
1912 case Op_SqrtHF:
1913 case Op_SubHF:
1914 return UseZfh;
1915
1916 case Op_CMoveP:
1917 case Op_CMoveN:
1918 return false;
1919 }
1920
1921 return true; // Per default match rules are supported.
1922 }
1923
1924 const RegMask* Matcher::predicate_reg_mask(void) {
1925 return &_VMASK_REG_mask;
1926 }
1927
1928 // Vector calling convention not yet implemented.
1929 bool Matcher::supports_vector_calling_convention(void) {
1930 return EnableVectorSupport;
1931 }
1932
1933 OptoRegPair Matcher::vector_return_value(uint ideal_reg) {
1934 assert(EnableVectorSupport, "sanity");
1935 assert(ideal_reg == Op_VecA, "sanity");
1936 // check more info at https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-cc.adoc
1937 int lo = V8_num;
1938 int hi = V8_K_num;
1939 return OptoRegPair(hi, lo);
1940 }
1941
1942 // Is this branch offset short enough that a short branch can be used?
1943 //
1944 // NOTE: If the platform does not provide any short branch variants, then
1945 // this method should return false for offset 0.
1946 // |---label(L1)-----|
1947 // |-----------------|
1948 // |-----------------|----------eq: float-------------------
1949 // |-----------------| // far_cmpD_branch | cmpD_branch
1950 // |------- ---------| feq; | feq;
1951 // |-far_cmpD_branch-| beqz done; | bnez L;
1952 // |-----------------| j L; |
1953 // |-----------------| bind(done); |
1954 // |-----------------|--------------------------------------
1955 // |-----------------| // so shortBrSize = br_size - 4;
1956 // |-----------------| // so offs = offset - shortBrSize + 4;
1957 // |---label(L2)-----|
1958 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1959 // The passed offset is relative to address of the branch.
1960 int shortBrSize = br_size - 4;
1961 int offs = offset - shortBrSize + 4;
1962 return (-4096 <= offs && offs < 4096);
1963 }
1964
1965 // Vector width in bytes.
1966 int Matcher::vector_width_in_bytes(BasicType bt) {
1967 if (UseRVV) {
1968 // The MaxVectorSize should have been set by detecting RVV max vector register size when check UseRVV.
1969 // MaxVectorSize == VM_Version::_initial_vector_length
1970 int size = MaxVectorSize;
1971 // Minimum 2 values in vector
1972 if (size < 2 * type2aelembytes(bt)) size = 0;
1973 // But never < 4
1974 if (size < 4) size = 0;
1975 return size;
1976 }
1977 return 0;
1978 }
1979
1980 // Limits on vector size (number of elements) loaded into vector.
1981 int Matcher::max_vector_size(const BasicType bt) {
1982 return vector_width_in_bytes(bt) / type2aelembytes(bt);
1983 }
1984
1985 int Matcher::min_vector_size(const BasicType bt) {
1986 int size;
1987 switch(bt) {
1988 case T_BOOLEAN:
1989 // Load/store a vector mask with only 2 elements for vector types
1990 // such as "2I/2F/2L/2D".
1991 size = 2;
1992 break;
1993 case T_BYTE:
1994 // Generate a "4B" vector, to support vector cast between "8B/16B"
1995 // and "4S/4I/4L/4F/4D".
1996 size = 4;
1997 break;
1998 case T_SHORT:
1999 // Generate a "2S" vector, to support vector cast between "4S/8S"
2000 // and "2I/2L/2F/2D".
2001 size = 2;
2002 break;
2003 default:
2004 // Limit the min vector length to 64-bit.
2005 size = 8 / type2aelembytes(bt);
2006 // The number of elements in a vector should be at least 2.
2007 size = MAX2(size, 2);
2008 }
2009
2010 int max_size = max_vector_size(bt);
2011 return MIN2(size, max_size);
2012 }
2013
2014 int Matcher::max_vector_size_auto_vectorization(const BasicType bt) {
2015 return Matcher::max_vector_size(bt);
2016 }
2017
2018 // Vector ideal reg.
2019 uint Matcher::vector_ideal_reg(int len) {
2020 assert(MaxVectorSize >= len, "");
2021 if (UseRVV) {
2022 return Op_VecA;
2023 }
2024
2025 ShouldNotReachHere();
2026 return 0;
2027 }
2028
2029 int Matcher::scalable_vector_reg_size(const BasicType bt) {
2030 return Matcher::max_vector_size(bt);
2031 }
2032
2033 MachOper* Matcher::pd_specialize_generic_vector_operand(MachOper* original_opnd, uint ideal_reg, bool is_temp) {
2034 ShouldNotReachHere(); // generic vector operands not supported
2035 return nullptr;
2036 }
2037
2038 bool Matcher::is_reg2reg_move(MachNode* m) {
2039 ShouldNotReachHere(); // generic vector operands not supported
2040 return false;
2041 }
2042
2043 bool Matcher::is_register_biasing_candidate(const MachNode* mdef, int oper_index) {
2044 return false;
2045 }
2046
2047 bool Matcher::is_generic_vector(MachOper* opnd) {
2048 ShouldNotReachHere(); // generic vector operands not supported
2049 return false;
2050 }
2051
2052 #ifdef ASSERT
2053 // Return whether or not this register is ever used as an argument.
2054 bool Matcher::can_be_java_arg(int reg)
2055 {
2056 return
2057 reg == R10_num || reg == R10_H_num ||
2058 reg == R11_num || reg == R11_H_num ||
2059 reg == R12_num || reg == R12_H_num ||
2060 reg == R13_num || reg == R13_H_num ||
2061 reg == R14_num || reg == R14_H_num ||
2062 reg == R15_num || reg == R15_H_num ||
2063 reg == R16_num || reg == R16_H_num ||
2064 reg == R17_num || reg == R17_H_num ||
2065 reg == F10_num || reg == F10_H_num ||
2066 reg == F11_num || reg == F11_H_num ||
2067 reg == F12_num || reg == F12_H_num ||
2068 reg == F13_num || reg == F13_H_num ||
2069 reg == F14_num || reg == F14_H_num ||
2070 reg == F15_num || reg == F15_H_num ||
2071 reg == F16_num || reg == F16_H_num ||
2072 reg == F17_num || reg == F17_H_num;
2073 }
2074 #endif
2075
2076 uint Matcher::int_pressure_limit()
2077 {
2078 // A derived pointer is live at CallNode and then is flagged by RA
2079 // as a spilled LRG. Spilling heuristics(Spill-USE) explicitly skip
2080 // derived pointers and lastly fail to spill after reaching maximum
2081 // number of iterations. Lowering the default pressure threshold to
2082 // (_NO_SPECIAL_REG32_mask.size() minus 1) forces CallNode to become
2083 // a high register pressure area of the code so that split_DEF can
2084 // generate DefinitionSpillCopy for the derived pointer.
2085 uint default_int_pressure_threshold = _NO_SPECIAL_REG32_mask.size() - 1;
2086 if (!PreserveFramePointer) {
2087 // When PreserveFramePointer is off, frame pointer is allocatable,
2088 // but different from other SOC registers, it is excluded from
2089 // fatproj's mask because its save type is No-Save. Decrease 1 to
2090 // ensure high pressure at fatproj when PreserveFramePointer is off.
2091 // See check_pressure_at_fatproj().
2092 default_int_pressure_threshold--;
2093 }
2094 return (INTPRESSURE == -1) ? default_int_pressure_threshold : INTPRESSURE;
2095 }
2096
2097 uint Matcher::float_pressure_limit()
2098 {
2099 // _FLOAT_REG_mask is generated by adlc from the float_reg register class.
2100 return (FLOATPRESSURE == -1) ? _FLOAT_REG_mask.size() : FLOATPRESSURE;
2101 }
2102
2103 const RegMask& Matcher::divI_proj_mask() {
2104 ShouldNotReachHere();
2105 return RegMask::EMPTY;
2106 }
2107
2108 // Register for MODI projection of divmodI.
2109 const RegMask& Matcher::modI_proj_mask() {
2110 ShouldNotReachHere();
2111 return RegMask::EMPTY;
2112 }
2113
2114 // Register for DIVL projection of divmodL.
2115 const RegMask& Matcher::divL_proj_mask() {
2116 ShouldNotReachHere();
2117 return RegMask::EMPTY;
2118 }
2119
2120 // Register for MODL projection of divmodL.
2121 const RegMask& Matcher::modL_proj_mask() {
2122 ShouldNotReachHere();
2123 return RegMask::EMPTY;
2124 }
2125
2126 bool size_fits_all_mem_uses(AddPNode* addp, int shift) {
2127 assert_cond(addp != nullptr);
2128 for (DUIterator_Fast imax, i = addp->fast_outs(imax); i < imax; i++) {
2129 Node* u = addp->fast_out(i);
2130 if (u != nullptr && u->is_Mem()) {
2131 int opsize = u->as_Mem()->memory_size();
2132 assert(opsize > 0, "unexpected memory operand size");
2133 if (u->as_Mem()->memory_size() != (1 << shift)) {
2134 return false;
2135 }
2136 }
2137 }
2138 return true;
2139 }
2140
2141 // Binary src (Replicate scalar/immediate)
2142 static bool is_vector_scalar_bitwise_pattern(Node* n, Node* m) {
2143 if (n == nullptr || m == nullptr) {
2144 return false;
2145 }
2146
2147 if (m->Opcode() != Op_Replicate) {
2148 return false;
2149 }
2150
2151 switch (n->Opcode()) {
2152 case Op_AndV:
2153 case Op_OrV:
2154 case Op_XorV:
2155 case Op_AddVB:
2156 case Op_AddVS:
2157 case Op_AddVI:
2158 case Op_AddVL:
2159 case Op_SubVB:
2160 case Op_SubVS:
2161 case Op_SubVI:
2162 case Op_SubVL:
2163 case Op_MulVB:
2164 case Op_MulVS:
2165 case Op_MulVI:
2166 case Op_MulVL: {
2167 return true;
2168 }
2169 default:
2170 return false;
2171 }
2172 }
2173
2174 // (XorV src (Replicate m1))
2175 // (XorVMask src (MaskAll m1))
2176 static bool is_vector_bitwise_not_pattern(Node* n, Node* m) {
2177 if (n != nullptr && m != nullptr) {
2178 return (n->Opcode() == Op_XorV || n->Opcode() == Op_XorVMask) &&
2179 VectorNode::is_all_ones_vector(m);
2180 }
2181 return false;
2182 }
2183
2184 // Should the Matcher clone input 'm' of node 'n'?
2185 bool Matcher::pd_clone_node(Node* n, Node* m, Matcher::MStack& mstack) {
2186 assert_cond(m != nullptr);
2187 if (is_vshift_con_pattern(n, m) || // ShiftV src (ShiftCntV con)
2188 is_vector_bitwise_not_pattern(n, m) ||
2189 is_vector_scalar_bitwise_pattern(n, m) ||
2190 is_encode_and_store_pattern(n, m)) {
2191 mstack.push(m, Visit);
2192 return true;
2193 }
2194 return false;
2195 }
2196
2197 // Should the Matcher clone shifts on addressing modes, expecting them
2198 // to be subsumed into complex addressing expressions or compute them
2199 // into registers?
2200 bool Matcher::pd_clone_address_expressions(AddPNode* m, Matcher::MStack& mstack, VectorSet& address_visited) {
2201 return clone_base_plus_offset_address(m, mstack, address_visited);
2202 }
2203
2204 %}
2205
2206
2207
2208 //----------ENCODING BLOCK-----------------------------------------------------
2209 // This block specifies the encoding classes used by the compiler to
2210 // output byte streams. Encoding classes are parameterized macros
2211 // used by Machine Instruction Nodes in order to generate the bit
2212 // encoding of the instruction. Operands specify their base encoding
2213 // interface with the interface keyword. There are currently
2214 // supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, &
2215 // COND_INTER. REG_INTER causes an operand to generate a function
2216 // which returns its register number when queried. CONST_INTER causes
2217 // an operand to generate a function which returns the value of the
2218 // constant when queried. MEMORY_INTER causes an operand to generate
2219 // four functions which return the Base Register, the Index Register,
2220 // the Scale Value, and the Offset Value of the operand when queried.
2221 // COND_INTER causes an operand to generate six functions which return
2222 // the encoding code (ie - encoding bits for the instruction)
2223 // associated with each basic boolean condition for a conditional
2224 // instruction.
2225 //
2226 // Instructions specify two basic values for encoding. Again, a
2227 // function is available to check if the constant displacement is an
2228 // oop. They use the ins_encode keyword to specify their encoding
2229 // classes (which must be a sequence of enc_class names, and their
2230 // parameters, specified in the encoding block), and they use the
2231 // opcode keyword to specify, in order, their primary, secondary, and
2232 // tertiary opcode. Only the opcode sections which a particular
2233 // instruction needs for encoding need to be specified.
2234 encode %{
2235 // BEGIN Non-volatile memory access
2236
2237 enc_class riscv_enc_mov_imm(iRegIorL dst, immIorL src) %{
2238 int64_t con = (int64_t)$src$$constant;
2239 Register dst_reg = as_Register($dst$$reg);
2240 __ mv(dst_reg, con);
2241 %}
2242
2243 enc_class riscv_enc_mov_p(iRegP dst, immP src) %{
2244 Register dst_reg = as_Register($dst$$reg);
2245 address con = (address)$src$$constant;
2246 if (con == nullptr || con == (address)1) {
2247 ShouldNotReachHere();
2248 } else {
2249 relocInfo::relocType rtype = $src->constant_reloc();
2250 if (rtype == relocInfo::oop_type) {
2251 __ movoop(dst_reg, (jobject)con);
2252 } else if (rtype == relocInfo::metadata_type) {
2253 __ mov_metadata(dst_reg, (Metadata*)con);
2254 } else {
2255 assert(rtype == relocInfo::none || rtype == relocInfo::external_word_type, "unexpected reloc type");
2256 __ mv(dst_reg, $src$$constant);
2257 }
2258 }
2259 %}
2260
2261 enc_class riscv_enc_mov_p1(iRegP dst) %{
2262 Register dst_reg = as_Register($dst$$reg);
2263 __ mv(dst_reg, 1);
2264 %}
2265
2266 enc_class riscv_enc_mov_n(iRegN dst, immN src) %{
2267 Register dst_reg = as_Register($dst$$reg);
2268 address con = (address)$src$$constant;
2269 if (con == nullptr) {
2270 ShouldNotReachHere();
2271 } else {
2272 relocInfo::relocType rtype = $src->constant_reloc();
2273 assert(rtype == relocInfo::oop_type, "unexpected reloc type");
2274 __ set_narrow_oop(dst_reg, (jobject)con);
2275 }
2276 %}
2277
2278 enc_class riscv_enc_mov_zero(iRegNorP dst) %{
2279 Register dst_reg = as_Register($dst$$reg);
2280 __ mv(dst_reg, zr);
2281 %}
2282
2283 enc_class riscv_enc_mov_nk(iRegN dst, immNKlass src) %{
2284 Register dst_reg = as_Register($dst$$reg);
2285 address con = (address)$src$$constant;
2286 if (con == nullptr) {
2287 ShouldNotReachHere();
2288 } else {
2289 relocInfo::relocType rtype = $src->constant_reloc();
2290 assert(rtype == relocInfo::metadata_type, "unexpected reloc type");
2291 __ set_narrow_klass(dst_reg, (Klass *)con);
2292 }
2293 %}
2294
2295 // compare and branch instruction encodings
2296
2297 enc_class riscv_enc_j(label lbl) %{
2298 Label* L = $lbl$$label;
2299 __ j(*L);
2300 %}
2301
2302 enc_class riscv_enc_far_cmpULtGe_imm0_branch(cmpOpULtGe cmp, iRegIorL op1, label lbl) %{
2303 Label* L = $lbl$$label;
2304 switch ($cmp$$cmpcode) {
2305 case(BoolTest::ge):
2306 __ j(*L);
2307 break;
2308 case(BoolTest::lt):
2309 break;
2310 default:
2311 Unimplemented();
2312 }
2313 %}
2314
2315 // call instruction encodings
2316
2317 enc_class riscv_enc_partial_subtype_check(iRegP sub, iRegP super, iRegP temp, iRegP result) %{
2318 Register sub_reg = as_Register($sub$$reg);
2319 Register super_reg = as_Register($super$$reg);
2320 Register temp_reg = as_Register($temp$$reg);
2321 Register result_reg = as_Register($result$$reg);
2322 Register cr_reg = t1;
2323
2324 Label miss;
2325 Label done;
2326 __ check_klass_subtype_slow_path(sub_reg, super_reg, temp_reg, result_reg,
2327 nullptr, &miss, /*set_cond_codes*/ true);
2328 if ($primary) {
2329 __ mv(result_reg, zr);
2330 } else {
2331 __ mv(cr_reg, zr);
2332 __ j(done);
2333 }
2334
2335 __ bind(miss);
2336 if (!$primary) {
2337 __ mv(cr_reg, 1);
2338 }
2339
2340 __ bind(done);
2341 %}
2342
2343 enc_class riscv_enc_java_static_call(method meth) %{
2344 Assembler::IncompressibleScope scope(masm); // Fixed length: see ret_addr_offset
2345
2346 address addr = (address)$meth$$method;
2347 address call = nullptr;
2348 assert_cond(addr != nullptr);
2349 if (!_method) {
2350 // A call to a runtime wrapper, e.g. new, new_typeArray_Java, uncommon_trap.
2351 call = __ reloc_call(Address(addr, relocInfo::runtime_call_type));
2352 if (call == nullptr) {
2353 ciEnv::current()->record_failure("CodeCache is full");
2354 return;
2355 }
2356 } else if (_method->intrinsic_id() == vmIntrinsicID::_ensureMaterializedForStackWalk) {
2357 // The NOP here is purely to ensure that eliding a call to
2358 // JVM_EnsureMaterializedForStackWalk doesn't change the code size.
2359 __ nop();
2360 __ nop();
2361 __ nop();
2362 __ block_comment("call JVM_EnsureMaterializedForStackWalk (elided)");
2363 } else {
2364 int method_index = resolved_method_index(masm);
2365 RelocationHolder rspec = _optimized_virtual ? opt_virtual_call_Relocation::spec(method_index)
2366 : static_call_Relocation::spec(method_index);
2367 call = __ reloc_call(Address(addr, rspec));
2368 if (call == nullptr) {
2369 ciEnv::current()->record_failure("CodeCache is full");
2370 return;
2371 }
2372
2373 if (CodeBuffer::supports_shared_stubs() && _method->can_be_statically_bound()) {
2374 // Calls of the same statically bound method can share
2375 // a stub to the interpreter.
2376 __ code()->shared_stub_to_interp_for(_method, call - (__ begin()));
2377 } else {
2378 // Emit stub for static call
2379 address stub = CompiledDirectCall::emit_to_interp_stub(masm, call);
2380 if (stub == nullptr) {
2381 ciEnv::current()->record_failure("CodeCache is full");
2382 return;
2383 }
2384 }
2385 }
2386
2387 __ post_call_nop();
2388 %}
2389
2390 enc_class riscv_enc_java_dynamic_call(method meth) %{
2391 Assembler::IncompressibleScope scope(masm); // Fixed length: see ret_addr_offset
2392 int method_index = resolved_method_index(masm);
2393 address call = __ ic_call((address)$meth$$method, method_index);
2394 if (call == nullptr) {
2395 ciEnv::current()->record_failure("CodeCache is full");
2396 return;
2397 }
2398
2399 __ post_call_nop();
2400 %}
2401
2402 enc_class riscv_enc_call_epilog() %{
2403 if (VerifyStackAtCalls) {
2404 // Check that stack depth is unchanged: find majik cookie on stack
2405 int framesize = ra_->reg2offset_unchecked(OptoReg::add(ra_->_matcher._old_SP, -3 * VMRegImpl::slots_per_word));
2406 Label stack_ok;
2407 __ ld(t1, Address(sp, framesize));
2408 __ mv(t2, MAJIK_DWORD);
2409 __ beq(t2, t1, stack_ok);
2410 __ stop("MAJIK_DWORD not found");
2411 __ bind(stack_ok);
2412 }
2413 %}
2414
2415 enc_class riscv_enc_java_to_runtime(method meth) %{
2416 Assembler::IncompressibleScope scope(masm); // Fixed length: see ret_addr_offset
2417
2418 // Some calls to generated routines (arraycopy code) are scheduled by C2
2419 // as runtime calls. if so we can call them using a far call (they will be
2420 // in the code cache, thus in a reachable segment) otherwise we have to use
2421 // a movptr+jalr pair which loads the absolute address into a register.
2422 address entry = (address)$meth$$method;
2423 if (CodeCache::contains(entry)) {
2424 __ far_call(Address(entry, relocInfo::runtime_call_type));
2425 __ post_call_nop();
2426 } else {
2427 Label retaddr;
2428 // Make the anchor frame walkable
2429 __ la(t0, retaddr);
2430 __ sd(t0, Address(xthread, JavaThread::last_Java_pc_offset()));
2431 int32_t offset = 0;
2432 // No relocation needed
2433 __ movptr(t1, entry, offset, t0); // lui + lui + slli + add
2434 __ jalr(t1, offset);
2435 __ bind(retaddr);
2436 __ post_call_nop();
2437 }
2438 %}
2439
2440 enc_class riscv_enc_tail_call(iRegP jump_target) %{
2441 Register target_reg = as_Register($jump_target$$reg);
2442 __ jr(target_reg);
2443 %}
2444
2445 enc_class riscv_enc_tail_jmp(iRegP jump_target) %{
2446 Register target_reg = as_Register($jump_target$$reg);
2447 // exception oop should be in x10
2448 // ret addr has been popped into ra
2449 // callee expects it in x13
2450 __ mv(x13, ra);
2451 __ jr(target_reg);
2452 %}
2453
2454 enc_class riscv_enc_rethrow() %{
2455 __ far_jump(RuntimeAddress(OptoRuntime::rethrow_stub()));
2456 %}
2457
2458 enc_class riscv_enc_ret() %{
2459 __ ret();
2460 %}
2461
2462 %}
2463
2464 //----------FRAME--------------------------------------------------------------
2465 // Definition of frame structure and management information.
2466 //
2467 // S T A C K L A Y O U T Allocators stack-slot number
2468 // | (to get allocators register number
2469 // G Owned by | | v add OptoReg::stack0())
2470 // r CALLER | |
2471 // o | +--------+ pad to even-align allocators stack-slot
2472 // w V | pad0 | numbers; owned by CALLER
2473 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
2474 // h ^ | in | 5
2475 // | | args | 4 Holes in incoming args owned by SELF
2476 // | | | | 3
2477 // | | +--------+
2478 // V | | old out| Empty on Intel, window on Sparc
2479 // | old |preserve| Must be even aligned.
2480 // | SP-+--------+----> Matcher::_old_SP, even aligned
2481 // | | in | 3 area for Intel ret address
2482 // Owned by |preserve| Empty on Sparc.
2483 // SELF +--------+
2484 // | | pad2 | 2 pad to align old SP
2485 // | +--------+ 1
2486 // | | locks | 0
2487 // | +--------+----> OptoReg::stack0(), even aligned
2488 // | | pad1 | 11 pad to align new SP
2489 // | +--------+
2490 // | | | 10
2491 // | | spills | 9 spills
2492 // V | | 8 (pad0 slot for callee)
2493 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
2494 // ^ | out | 7
2495 // | | args | 6 Holes in outgoing args owned by CALLEE
2496 // Owned by +--------+
2497 // CALLEE | new out| 6 Empty on Intel, window on Sparc
2498 // | new |preserve| Must be even-aligned.
2499 // | SP-+--------+----> Matcher::_new_SP, even aligned
2500 // | | |
2501 //
2502 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
2503 // known from SELF's arguments and the Java calling convention.
2504 // Region 6-7 is determined per call site.
2505 // Note 2: If the calling convention leaves holes in the incoming argument
2506 // area, those holes are owned by SELF. Holes in the outgoing area
2507 // are owned by the CALLEE. Holes should not be necessary in the
2508 // incoming area, as the Java calling convention is completely under
2509 // the control of the AD file. Doubles can be sorted and packed to
2510 // avoid holes. Holes in the outgoing arguments may be necessary for
2511 // varargs C calling conventions.
2512 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
2513 // even aligned with pad0 as needed.
2514 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
2515 // (the latter is true on Intel but is it false on RISCV?)
2516 // region 6-11 is even aligned; it may be padded out more so that
2517 // the region from SP to FP meets the minimum stack alignment.
2518 // Note 4: For I2C adapters, the incoming FP may not meet the minimum stack
2519 // alignment. Region 11, pad1, may be dynamically extended so that
2520 // SP meets the minimum alignment.
2521
2522 frame %{
2523 // These three registers define part of the calling convention
2524 // between compiled code and the interpreter.
2525
2526 // Inline Cache Register or methodOop for I2C.
2527 inline_cache_reg(R31);
2528
2529 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
2530 cisc_spilling_operand_name(indOffset);
2531
2532 // Number of stack slots consumed by locking an object
2533 // generate Compile::sync_stack_slots
2534 // VMRegImpl::slots_per_word = wordSize / stack_slot_size = 8 / 4 = 2
2535 sync_stack_slots(1 * VMRegImpl::slots_per_word);
2536
2537 // Compiled code's Frame Pointer
2538 frame_pointer(R2);
2539
2540 // Stack alignment requirement
2541 stack_alignment(StackAlignmentInBytes); // Alignment size in bytes (128-bit -> 16 bytes)
2542
2543 // Number of outgoing stack slots killed above the out_preserve_stack_slots
2544 // for calls to C. Supports the var-args backing area for register parms.
2545 varargs_C_out_slots_killed(frame::arg_reg_save_area_bytes / BytesPerInt);
2546
2547 // The after-PROLOG location of the return address. Location of
2548 // return address specifies a type (REG or STACK) and a number
2549 // representing the register number (i.e. - use a register name) or
2550 // stack slot.
2551 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
2552 // Otherwise, it is above the locks and verification slot and alignment word
2553 // TODO this may well be correct but need to check why that - 2 is there
2554 // ppc port uses 0 but we definitely need to allow for fixed_slots
2555 // which folds in the space used for monitors
2556 return_addr(STACK - 2 +
2557 align_up((Compile::current()->in_preserve_stack_slots() +
2558 Compile::current()->fixed_slots()),
2559 stack_alignment_in_slots()));
2560
2561 // Location of compiled Java return values. Same as C for now.
2562 return_value
2563 %{
2564 assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL,
2565 "only return normal values");
2566
2567 static const int lo[Op_RegL + 1] = { // enum name
2568 0, // Op_Node
2569 0, // Op_Set
2570 R10_num, // Op_RegN
2571 R10_num, // Op_RegI
2572 R10_num, // Op_RegP
2573 F10_num, // Op_RegF
2574 F10_num, // Op_RegD
2575 R10_num // Op_RegL
2576 };
2577
2578 static const int hi[Op_RegL + 1] = { // enum name
2579 0, // Op_Node
2580 0, // Op_Set
2581 OptoReg::Bad, // Op_RegN
2582 OptoReg::Bad, // Op_RegI
2583 R10_H_num, // Op_RegP
2584 OptoReg::Bad, // Op_RegF
2585 F10_H_num, // Op_RegD
2586 R10_H_num // Op_RegL
2587 };
2588
2589 return OptoRegPair(hi[ideal_reg], lo[ideal_reg]);
2590 %}
2591 %}
2592
2593 //----------ATTRIBUTES---------------------------------------------------------
2594 //----------Operand Attributes-------------------------------------------------
2595 op_attrib op_cost(1); // Required cost attribute
2596
2597 //----------Instruction Attributes---------------------------------------------
2598 ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute
2599 ins_attrib ins_size(32); // Required size attribute (in bits)
2600 ins_attrib ins_short_branch(0); // Required flag: is this instruction
2601 // a non-matching short branch variant
2602 // of some long branch?
2603 ins_attrib ins_alignment(4); // Required alignment attribute (must
2604 // be a power of 2) specifies the
2605 // alignment that some part of the
2606 // instruction (not necessarily the
2607 // start) requires. If > 1, a
2608 // compute_padding() function must be
2609 // provided for the instruction
2610
2611 // Whether this node is expanded during code emission into a sequence of
2612 // instructions and the first instruction can perform an implicit null check.
2613 ins_attrib ins_is_late_expanded_null_check_candidate(false);
2614
2615 //----------OPERANDS-----------------------------------------------------------
2616 // Operand definitions must precede instruction definitions for correct parsing
2617 // in the ADLC because operands constitute user defined types which are used in
2618 // instruction definitions.
2619
2620 //----------Simple Operands----------------------------------------------------
2621
2622 // Integer operands 32 bit
2623 // 32 bit immediate
2624 operand immI()
2625 %{
2626 match(ConI);
2627
2628 op_cost(0);
2629 format %{ %}
2630 interface(CONST_INTER);
2631 %}
2632
2633 // 32 bit zero
2634 operand immI0()
2635 %{
2636 predicate(n->get_int() == 0);
2637 match(ConI);
2638
2639 op_cost(0);
2640 format %{ %}
2641 interface(CONST_INTER);
2642 %}
2643
2644 // 32 bit unit increment
2645 operand immI_1()
2646 %{
2647 predicate(n->get_int() == 1);
2648 match(ConI);
2649
2650 op_cost(0);
2651 format %{ %}
2652 interface(CONST_INTER);
2653 %}
2654
2655 // 32 bit unit decrement
2656 operand immI_M1()
2657 %{
2658 predicate(n->get_int() == -1);
2659 match(ConI);
2660
2661 op_cost(0);
2662 format %{ %}
2663 interface(CONST_INTER);
2664 %}
2665
2666 // Unsigned Integer Immediate: 6-bit int, greater than 32
2667 operand uimmI6_ge32() %{
2668 predicate(((unsigned int)(n->get_int()) < 64) && (n->get_int() >= 32));
2669 match(ConI);
2670 op_cost(0);
2671 format %{ %}
2672 interface(CONST_INTER);
2673 %}
2674
2675 operand immI_le_4()
2676 %{
2677 predicate(n->get_int() <= 4);
2678 match(ConI);
2679
2680 op_cost(0);
2681 format %{ %}
2682 interface(CONST_INTER);
2683 %}
2684
2685 operand immI_16()
2686 %{
2687 predicate(n->get_int() == 16);
2688 match(ConI);
2689 op_cost(0);
2690 format %{ %}
2691 interface(CONST_INTER);
2692 %}
2693
2694 operand immI_24()
2695 %{
2696 predicate(n->get_int() == 24);
2697 match(ConI);
2698 op_cost(0);
2699 format %{ %}
2700 interface(CONST_INTER);
2701 %}
2702
2703 operand immI_31()
2704 %{
2705 predicate(n->get_int() == 31);
2706 match(ConI);
2707
2708 op_cost(0);
2709 format %{ %}
2710 interface(CONST_INTER);
2711 %}
2712
2713 operand immI_63()
2714 %{
2715 predicate(n->get_int() == 63);
2716 match(ConI);
2717
2718 op_cost(0);
2719 format %{ %}
2720 interface(CONST_INTER);
2721 %}
2722
2723 // 32 bit integer valid for add immediate
2724 operand immIAdd()
2725 %{
2726 predicate(Assembler::is_simm12((int64_t)n->get_int()));
2727 match(ConI);
2728 op_cost(0);
2729 format %{ %}
2730 interface(CONST_INTER);
2731 %}
2732
2733 // 32 bit integer valid for sub immediate
2734 operand immISub()
2735 %{
2736 predicate(Assembler::is_simm12(-(int64_t)n->get_int()));
2737 match(ConI);
2738 op_cost(0);
2739 format %{ %}
2740 interface(CONST_INTER);
2741 %}
2742
2743 // 5 bit signed value.
2744 operand immI5()
2745 %{
2746 predicate(n->get_int() <= 15 && n->get_int() >= -16);
2747 match(ConI);
2748
2749 op_cost(0);
2750 format %{ %}
2751 interface(CONST_INTER);
2752 %}
2753
2754 // 5 bit signed value (simm5)
2755 operand immL5()
2756 %{
2757 predicate(n->get_long() <= 15 && n->get_long() >= -16);
2758 match(ConL);
2759
2760 op_cost(0);
2761 format %{ %}
2762 interface(CONST_INTER);
2763 %}
2764
2765 // Integer operands 64 bit
2766 // 64 bit immediate
2767 operand immL()
2768 %{
2769 match(ConL);
2770
2771 op_cost(0);
2772 format %{ %}
2773 interface(CONST_INTER);
2774 %}
2775
2776 // 64 bit zero
2777 operand immL0()
2778 %{
2779 predicate(n->get_long() == 0);
2780 match(ConL);
2781
2782 op_cost(0);
2783 format %{ %}
2784 interface(CONST_INTER);
2785 %}
2786
2787 // Pointer operands
2788 // Pointer Immediate
2789 operand immP()
2790 %{
2791 match(ConP);
2792
2793 op_cost(0);
2794 format %{ %}
2795 interface(CONST_INTER);
2796 %}
2797
2798 // Null Pointer Immediate
2799 operand immP0()
2800 %{
2801 predicate(n->get_ptr() == 0);
2802 match(ConP);
2803
2804 op_cost(0);
2805 format %{ %}
2806 interface(CONST_INTER);
2807 %}
2808
2809 // Pointer Immediate One
2810 // this is used in object initialization (initial object header)
2811 operand immP_1()
2812 %{
2813 predicate(n->get_ptr() == 1);
2814 match(ConP);
2815
2816 op_cost(0);
2817 format %{ %}
2818 interface(CONST_INTER);
2819 %}
2820
2821 // Int Immediate: low 16-bit mask
2822 operand immI_16bits()
2823 %{
2824 predicate(n->get_int() == 0xFFFF);
2825 match(ConI);
2826 op_cost(0);
2827 format %{ %}
2828 interface(CONST_INTER);
2829 %}
2830
2831 operand immIpowerOf2() %{
2832 predicate(is_power_of_2((juint)(n->get_int())));
2833 match(ConI);
2834 op_cost(0);
2835 format %{ %}
2836 interface(CONST_INTER);
2837 %}
2838
2839 // Long Immediate: low 32-bit mask
2840 operand immL_32bits()
2841 %{
2842 predicate(n->get_long() == 0xFFFFFFFFL);
2843 match(ConL);
2844 op_cost(0);
2845 format %{ %}
2846 interface(CONST_INTER);
2847 %}
2848
2849 // 64 bit unit decrement
2850 operand immL_M1()
2851 %{
2852 predicate(n->get_long() == -1);
2853 match(ConL);
2854
2855 op_cost(0);
2856 format %{ %}
2857 interface(CONST_INTER);
2858 %}
2859
2860
2861 // 64 bit integer valid for add immediate
2862 operand immLAdd()
2863 %{
2864 predicate(Assembler::is_simm12(n->get_long()));
2865 match(ConL);
2866 op_cost(0);
2867 format %{ %}
2868 interface(CONST_INTER);
2869 %}
2870
2871 // 64 bit integer valid for sub immediate
2872 operand immLSub()
2873 %{
2874 predicate(Assembler::is_simm12(-(n->get_long())));
2875 match(ConL);
2876 op_cost(0);
2877 format %{ %}
2878 interface(CONST_INTER);
2879 %}
2880
2881 // Narrow pointer operands
2882 // Narrow Pointer Immediate
2883 operand immN()
2884 %{
2885 match(ConN);
2886
2887 op_cost(0);
2888 format %{ %}
2889 interface(CONST_INTER);
2890 %}
2891
2892 // Narrow Null Pointer Immediate
2893 operand immN0()
2894 %{
2895 predicate(n->get_narrowcon() == 0);
2896 match(ConN);
2897
2898 op_cost(0);
2899 format %{ %}
2900 interface(CONST_INTER);
2901 %}
2902
2903 operand immNKlass()
2904 %{
2905 match(ConNKlass);
2906
2907 op_cost(0);
2908 format %{ %}
2909 interface(CONST_INTER);
2910 %}
2911
2912 // Float and Double operands
2913 // Double Immediate
2914 operand immD()
2915 %{
2916 match(ConD);
2917 op_cost(0);
2918 format %{ %}
2919 interface(CONST_INTER);
2920 %}
2921
2922 // Double Immediate: +0.0d
2923 operand immD0()
2924 %{
2925 predicate(jlong_cast(n->getd()) == 0);
2926 match(ConD);
2927
2928 op_cost(0);
2929 format %{ %}
2930 interface(CONST_INTER);
2931 %}
2932
2933 // Float Immediate
2934 operand immF()
2935 %{
2936 match(ConF);
2937 op_cost(0);
2938 format %{ %}
2939 interface(CONST_INTER);
2940 %}
2941
2942 // Float Immediate: +0.0f.
2943 operand immF0()
2944 %{
2945 predicate(jint_cast(n->getf()) == 0);
2946 match(ConF);
2947
2948 op_cost(0);
2949 format %{ %}
2950 interface(CONST_INTER);
2951 %}
2952
2953 // Half Float Immediate
2954 operand immH()
2955 %{
2956 match(ConH);
2957
2958 op_cost(0);
2959 format %{ %}
2960 interface(CONST_INTER);
2961 %}
2962
2963 // Half Float Immediate: +0.0f.
2964 operand immH0()
2965 %{
2966 predicate(jint_cast(n->geth()) == 0);
2967 match(ConH);
2968
2969 op_cost(0);
2970 format %{ %}
2971 interface(CONST_INTER);
2972 %}
2973
2974 operand immIOffset()
2975 %{
2976 predicate(Assembler::is_simm12(n->get_int()));
2977 match(ConI);
2978 op_cost(0);
2979 format %{ %}
2980 interface(CONST_INTER);
2981 %}
2982
2983 operand immLOffset()
2984 %{
2985 predicate(Assembler::is_simm12(n->get_long()));
2986 match(ConL);
2987 op_cost(0);
2988 format %{ %}
2989 interface(CONST_INTER);
2990 %}
2991
2992 // Scale values
2993 operand immIScale()
2994 %{
2995 predicate(1 <= n->get_int() && (n->get_int() <= 3));
2996 match(ConI);
2997
2998 op_cost(0);
2999 format %{ %}
3000 interface(CONST_INTER);
3001 %}
3002
3003 // Integer 32 bit Register Operands
3004 operand iRegI()
3005 %{
3006 constraint(ALLOC_IN_RC(any_reg32));
3007 match(RegI);
3008 match(iRegINoSp);
3009 op_cost(0);
3010 format %{ %}
3011 interface(REG_INTER);
3012 %}
3013
3014 // Integer 32 bit Register not Special
3015 operand iRegINoSp()
3016 %{
3017 constraint(ALLOC_IN_RC(no_special_reg32));
3018 match(RegI);
3019 op_cost(0);
3020 format %{ %}
3021 interface(REG_INTER);
3022 %}
3023
3024 // Register R10 only
3025 operand iRegI_R10()
3026 %{
3027 constraint(ALLOC_IN_RC(int_r10_reg));
3028 match(RegI);
3029 match(iRegINoSp);
3030 op_cost(0);
3031 format %{ %}
3032 interface(REG_INTER);
3033 %}
3034
3035 // Register R12 only
3036 operand iRegI_R12()
3037 %{
3038 constraint(ALLOC_IN_RC(int_r12_reg));
3039 match(RegI);
3040 match(iRegINoSp);
3041 op_cost(0);
3042 format %{ %}
3043 interface(REG_INTER);
3044 %}
3045
3046 // Register R13 only
3047 operand iRegI_R13()
3048 %{
3049 constraint(ALLOC_IN_RC(int_r13_reg));
3050 match(RegI);
3051 match(iRegINoSp);
3052 op_cost(0);
3053 format %{ %}
3054 interface(REG_INTER);
3055 %}
3056
3057 // Register R14 only
3058 operand iRegI_R14()
3059 %{
3060 constraint(ALLOC_IN_RC(int_r14_reg));
3061 match(RegI);
3062 match(iRegINoSp);
3063 op_cost(0);
3064 format %{ %}
3065 interface(REG_INTER);
3066 %}
3067
3068 // Integer 64 bit Register Operands
3069 operand iRegL()
3070 %{
3071 constraint(ALLOC_IN_RC(any_reg));
3072 match(RegL);
3073 match(iRegLNoSp);
3074 op_cost(0);
3075 format %{ %}
3076 interface(REG_INTER);
3077 %}
3078
3079 // Integer 64 bit Register not Special
3080 operand iRegLNoSp()
3081 %{
3082 constraint(ALLOC_IN_RC(no_special_reg));
3083 match(RegL);
3084 match(iRegL_R10);
3085 format %{ %}
3086 interface(REG_INTER);
3087 %}
3088
3089 // Long 64 bit Register R29 only
3090 operand iRegL_R29()
3091 %{
3092 constraint(ALLOC_IN_RC(r29_reg));
3093 match(RegL);
3094 match(iRegLNoSp);
3095 op_cost(0);
3096 format %{ %}
3097 interface(REG_INTER);
3098 %}
3099
3100 // Long 64 bit Register R30 only
3101 operand iRegL_R30()
3102 %{
3103 constraint(ALLOC_IN_RC(r30_reg));
3104 match(RegL);
3105 match(iRegLNoSp);
3106 op_cost(0);
3107 format %{ %}
3108 interface(REG_INTER);
3109 %}
3110
3111 // Pointer Register Operands
3112 // Pointer Register
3113 operand iRegP()
3114 %{
3115 constraint(ALLOC_IN_RC(ptr_reg));
3116 match(RegP);
3117 match(iRegPNoSp);
3118 match(iRegP_R10);
3119 match(iRegP_R15);
3120 match(javaThread_RegP);
3121 op_cost(0);
3122 format %{ %}
3123 interface(REG_INTER);
3124 %}
3125
3126 // Pointer 64 bit Register not Special
3127 operand iRegPNoSp()
3128 %{
3129 constraint(ALLOC_IN_RC(no_special_ptr_reg));
3130 match(RegP);
3131 op_cost(0);
3132 format %{ %}
3133 interface(REG_INTER);
3134 %}
3135
3136 // This operand is not allowed to use fp even if
3137 // fp is not used to hold the frame pointer.
3138 operand iRegPNoSpNoFp()
3139 %{
3140 constraint(ALLOC_IN_RC(no_special_no_fp_ptr_reg));
3141 match(RegP);
3142 match(iRegPNoSp);
3143 op_cost(0);
3144 format %{ %}
3145 interface(REG_INTER);
3146 %}
3147
3148 operand iRegP_R10()
3149 %{
3150 constraint(ALLOC_IN_RC(r10_reg));
3151 match(RegP);
3152 // match(iRegP);
3153 match(iRegPNoSp);
3154 op_cost(0);
3155 format %{ %}
3156 interface(REG_INTER);
3157 %}
3158
3159 // Pointer 64 bit Register R11 only
3160 operand iRegP_R11()
3161 %{
3162 constraint(ALLOC_IN_RC(r11_reg));
3163 match(RegP);
3164 match(iRegPNoSp);
3165 op_cost(0);
3166 format %{ %}
3167 interface(REG_INTER);
3168 %}
3169
3170 operand iRegP_R12()
3171 %{
3172 constraint(ALLOC_IN_RC(r12_reg));
3173 match(RegP);
3174 // match(iRegP);
3175 match(iRegPNoSp);
3176 op_cost(0);
3177 format %{ %}
3178 interface(REG_INTER);
3179 %}
3180
3181 // Pointer 64 bit Register R13 only
3182 operand iRegP_R13()
3183 %{
3184 constraint(ALLOC_IN_RC(r13_reg));
3185 match(RegP);
3186 match(iRegPNoSp);
3187 op_cost(0);
3188 format %{ %}
3189 interface(REG_INTER);
3190 %}
3191
3192 operand iRegP_R14()
3193 %{
3194 constraint(ALLOC_IN_RC(r14_reg));
3195 match(RegP);
3196 // match(iRegP);
3197 match(iRegPNoSp);
3198 op_cost(0);
3199 format %{ %}
3200 interface(REG_INTER);
3201 %}
3202
3203 operand iRegP_R15()
3204 %{
3205 constraint(ALLOC_IN_RC(r15_reg));
3206 match(RegP);
3207 // match(iRegP);
3208 match(iRegPNoSp);
3209 op_cost(0);
3210 format %{ %}
3211 interface(REG_INTER);
3212 %}
3213
3214 operand iRegP_R16()
3215 %{
3216 constraint(ALLOC_IN_RC(r16_reg));
3217 match(RegP);
3218 match(iRegPNoSp);
3219 op_cost(0);
3220 format %{ %}
3221 interface(REG_INTER);
3222 %}
3223
3224 // Pointer 64 bit Register R28 only
3225 operand iRegP_R28()
3226 %{
3227 constraint(ALLOC_IN_RC(r28_reg));
3228 match(RegP);
3229 match(iRegPNoSp);
3230 op_cost(0);
3231 format %{ %}
3232 interface(REG_INTER);
3233 %}
3234
3235 // Pointer 64 bit Register R30 only
3236 operand iRegP_R30()
3237 %{
3238 constraint(ALLOC_IN_RC(r30_reg));
3239 match(RegP);
3240 match(iRegPNoSp);
3241 op_cost(0);
3242 format %{ %}
3243 interface(REG_INTER);
3244 %}
3245
3246 // Pointer 64 bit Register R31 only
3247 operand iRegP_R31()
3248 %{
3249 constraint(ALLOC_IN_RC(r31_reg));
3250 match(RegP);
3251 match(iRegPNoSp);
3252 op_cost(0);
3253 format %{ %}
3254 interface(REG_INTER);
3255 %}
3256
3257 // Pointer Register Operands
3258 // Narrow Pointer Register
3259 operand iRegN()
3260 %{
3261 constraint(ALLOC_IN_RC(any_reg32));
3262 match(RegN);
3263 match(iRegNNoSp);
3264 op_cost(0);
3265 format %{ %}
3266 interface(REG_INTER);
3267 %}
3268
3269 // Integer 64 bit Register not Special
3270 operand iRegNNoSp()
3271 %{
3272 constraint(ALLOC_IN_RC(no_special_reg32));
3273 match(RegN);
3274 op_cost(0);
3275 format %{ %}
3276 interface(REG_INTER);
3277 %}
3278
3279 // Long 64 bit Register R10 only
3280 operand iRegL_R10()
3281 %{
3282 constraint(ALLOC_IN_RC(r10_reg));
3283 match(RegL);
3284 match(iRegLNoSp);
3285 op_cost(0);
3286 format %{ %}
3287 interface(REG_INTER);
3288 %}
3289
3290 // Float Register
3291 // Float register operands
3292 operand fRegF()
3293 %{
3294 constraint(ALLOC_IN_RC(float_reg));
3295 match(RegF);
3296
3297 op_cost(0);
3298 format %{ %}
3299 interface(REG_INTER);
3300 %}
3301
3302 // Double Register
3303 // Double register operands
3304 operand fRegD()
3305 %{
3306 constraint(ALLOC_IN_RC(double_reg));
3307 match(RegD);
3308
3309 op_cost(0);
3310 format %{ %}
3311 interface(REG_INTER);
3312 %}
3313
3314 // Generic vector class. This will be used for
3315 // all vector operands.
3316 operand vReg()
3317 %{
3318 constraint(ALLOC_IN_RC(vectora_reg));
3319 match(VecA);
3320 op_cost(0);
3321 format %{ %}
3322 interface(REG_INTER);
3323 %}
3324
3325 operand vReg_V1()
3326 %{
3327 constraint(ALLOC_IN_RC(v1_reg));
3328 match(VecA);
3329 match(vReg);
3330 op_cost(0);
3331 format %{ %}
3332 interface(REG_INTER);
3333 %}
3334
3335 operand vReg_V2()
3336 %{
3337 constraint(ALLOC_IN_RC(v2_reg));
3338 match(VecA);
3339 match(vReg);
3340 op_cost(0);
3341 format %{ %}
3342 interface(REG_INTER);
3343 %}
3344
3345 operand vReg_V3()
3346 %{
3347 constraint(ALLOC_IN_RC(v3_reg));
3348 match(VecA);
3349 match(vReg);
3350 op_cost(0);
3351 format %{ %}
3352 interface(REG_INTER);
3353 %}
3354
3355 operand vReg_V4()
3356 %{
3357 constraint(ALLOC_IN_RC(v4_reg));
3358 match(VecA);
3359 match(vReg);
3360 op_cost(0);
3361 format %{ %}
3362 interface(REG_INTER);
3363 %}
3364
3365 operand vReg_V5()
3366 %{
3367 constraint(ALLOC_IN_RC(v5_reg));
3368 match(VecA);
3369 match(vReg);
3370 op_cost(0);
3371 format %{ %}
3372 interface(REG_INTER);
3373 %}
3374
3375 operand vReg_V6()
3376 %{
3377 constraint(ALLOC_IN_RC(v6_reg));
3378 match(VecA);
3379 match(vReg);
3380 op_cost(0);
3381 format %{ %}
3382 interface(REG_INTER);
3383 %}
3384
3385 operand vReg_V7()
3386 %{
3387 constraint(ALLOC_IN_RC(v7_reg));
3388 match(VecA);
3389 match(vReg);
3390 op_cost(0);
3391 format %{ %}
3392 interface(REG_INTER);
3393 %}
3394
3395 operand vReg_V8()
3396 %{
3397 constraint(ALLOC_IN_RC(v8_reg));
3398 match(VecA);
3399 match(vReg);
3400 op_cost(0);
3401 format %{ %}
3402 interface(REG_INTER);
3403 %}
3404
3405 operand vReg_V9()
3406 %{
3407 constraint(ALLOC_IN_RC(v9_reg));
3408 match(VecA);
3409 match(vReg);
3410 op_cost(0);
3411 format %{ %}
3412 interface(REG_INTER);
3413 %}
3414
3415 operand vReg_V10()
3416 %{
3417 constraint(ALLOC_IN_RC(v10_reg));
3418 match(VecA);
3419 match(vReg);
3420 op_cost(0);
3421 format %{ %}
3422 interface(REG_INTER);
3423 %}
3424
3425 operand vReg_V11()
3426 %{
3427 constraint(ALLOC_IN_RC(v11_reg));
3428 match(VecA);
3429 match(vReg);
3430 op_cost(0);
3431 format %{ %}
3432 interface(REG_INTER);
3433 %}
3434
3435 operand vRegMask()
3436 %{
3437 constraint(ALLOC_IN_RC(vmask_reg));
3438 match(RegVectMask);
3439 match(vRegMask_V0);
3440 op_cost(0);
3441 format %{ %}
3442 interface(REG_INTER);
3443 %}
3444
3445 // The mask value used to control execution of a masked
3446 // vector instruction is always supplied by vector register v0.
3447 operand vRegMask_V0()
3448 %{
3449 constraint(ALLOC_IN_RC(vmask_reg_v0));
3450 match(RegVectMask);
3451 match(vRegMask);
3452 op_cost(0);
3453 format %{ %}
3454 interface(REG_INTER);
3455 %}
3456
3457 // Java Thread Register
3458 operand javaThread_RegP(iRegP reg)
3459 %{
3460 constraint(ALLOC_IN_RC(java_thread_reg)); // java_thread_reg
3461 match(reg);
3462 op_cost(0);
3463 format %{ %}
3464 interface(REG_INTER);
3465 %}
3466
3467 //----------Memory Operands----------------------------------------------------
3468 // RISCV has only base_plus_offset and literal address mode, so no need to use
3469 // index and scale. Here set index as 0xffffffff and scale as 0x0.
3470 operand indirect(iRegP reg)
3471 %{
3472 constraint(ALLOC_IN_RC(ptr_reg));
3473 match(reg);
3474 op_cost(0);
3475 format %{ "[$reg]" %}
3476 interface(MEMORY_INTER) %{
3477 base($reg);
3478 index(0xffffffff);
3479 scale(0x0);
3480 disp(0x0);
3481 %}
3482 %}
3483
3484 operand indOffI(iRegP reg, immIOffset off)
3485 %{
3486 constraint(ALLOC_IN_RC(ptr_reg));
3487 match(AddP reg off);
3488 op_cost(0);
3489 format %{ "[$reg, $off]" %}
3490 interface(MEMORY_INTER) %{
3491 base($reg);
3492 index(0xffffffff);
3493 scale(0x0);
3494 disp($off);
3495 %}
3496 %}
3497
3498 operand indOffL(iRegP reg, immLOffset off)
3499 %{
3500 constraint(ALLOC_IN_RC(ptr_reg));
3501 match(AddP reg off);
3502 op_cost(0);
3503 format %{ "[$reg, $off]" %}
3504 interface(MEMORY_INTER) %{
3505 base($reg);
3506 index(0xffffffff);
3507 scale(0x0);
3508 disp($off);
3509 %}
3510 %}
3511
3512 operand indirectN(iRegN reg)
3513 %{
3514 predicate(CompressedOops::shift() == 0);
3515 constraint(ALLOC_IN_RC(ptr_reg));
3516 match(DecodeN reg);
3517 op_cost(0);
3518 format %{ "[$reg]\t# narrow" %}
3519 interface(MEMORY_INTER) %{
3520 base($reg);
3521 index(0xffffffff);
3522 scale(0x0);
3523 disp(0x0);
3524 %}
3525 %}
3526
3527 operand indOffIN(iRegN reg, immIOffset off)
3528 %{
3529 predicate(CompressedOops::shift() == 0);
3530 constraint(ALLOC_IN_RC(ptr_reg));
3531 match(AddP (DecodeN reg) off);
3532 op_cost(0);
3533 format %{ "[$reg, $off]\t# narrow" %}
3534 interface(MEMORY_INTER) %{
3535 base($reg);
3536 index(0xffffffff);
3537 scale(0x0);
3538 disp($off);
3539 %}
3540 %}
3541
3542 operand indOffLN(iRegN reg, immLOffset off)
3543 %{
3544 predicate(CompressedOops::shift() == 0);
3545 constraint(ALLOC_IN_RC(ptr_reg));
3546 match(AddP (DecodeN reg) off);
3547 op_cost(0);
3548 format %{ "[$reg, $off]\t# narrow" %}
3549 interface(MEMORY_INTER) %{
3550 base($reg);
3551 index(0xffffffff);
3552 scale(0x0);
3553 disp($off);
3554 %}
3555 %}
3556
3557 //----------Special Memory Operands--------------------------------------------
3558 // Stack Slot Operand - This operand is used for loading and storing temporary
3559 // values on the stack where a match requires a value to
3560 // flow through memory.
3561 operand stackSlotI(sRegI reg)
3562 %{
3563 constraint(ALLOC_IN_RC(stack_slots));
3564 // No match rule because this operand is only generated in matching
3565 // match(RegI);
3566 format %{ "[$reg]" %}
3567 interface(MEMORY_INTER) %{
3568 base(0x02); // RSP
3569 index(0xffffffff); // No Index
3570 scale(0x0); // No Scale
3571 disp($reg); // Stack Offset
3572 %}
3573 %}
3574
3575 operand stackSlotF(sRegF reg)
3576 %{
3577 constraint(ALLOC_IN_RC(stack_slots));
3578 // No match rule because this operand is only generated in matching
3579 // match(RegF);
3580 format %{ "[$reg]" %}
3581 interface(MEMORY_INTER) %{
3582 base(0x02); // RSP
3583 index(0xffffffff); // No Index
3584 scale(0x0); // No Scale
3585 disp($reg); // Stack Offset
3586 %}
3587 %}
3588
3589 operand stackSlotD(sRegD reg)
3590 %{
3591 constraint(ALLOC_IN_RC(stack_slots));
3592 // No match rule because this operand is only generated in matching
3593 // match(RegD);
3594 format %{ "[$reg]" %}
3595 interface(MEMORY_INTER) %{
3596 base(0x02); // RSP
3597 index(0xffffffff); // No Index
3598 scale(0x0); // No Scale
3599 disp($reg); // Stack Offset
3600 %}
3601 %}
3602
3603 operand stackSlotL(sRegL reg)
3604 %{
3605 constraint(ALLOC_IN_RC(stack_slots));
3606 // No match rule because this operand is only generated in matching
3607 // match(RegL);
3608 format %{ "[$reg]" %}
3609 interface(MEMORY_INTER) %{
3610 base(0x02); // RSP
3611 index(0xffffffff); // No Index
3612 scale(0x0); // No Scale
3613 disp($reg); // Stack Offset
3614 %}
3615 %}
3616
3617 // Special operand allowing long args to int ops to be truncated for free
3618
3619 operand iRegL2I(iRegL reg) %{
3620
3621 op_cost(0);
3622
3623 match(ConvL2I reg);
3624
3625 format %{ "l2i($reg)" %}
3626
3627 interface(REG_INTER)
3628 %}
3629
3630
3631 // Comparison Operands
3632 // NOTE: Label is a predefined operand which should not be redefined in
3633 // the AD file. It is generically handled within the ADLC.
3634
3635 //----------Conditional Branch Operands----------------------------------------
3636 // Comparison Op - This is the operation of the comparison, and is limited to
3637 // the following set of codes:
3638 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
3639 //
3640 // Other attributes of the comparison, such as unsignedness, are specified
3641 // by the comparison instruction that sets a condition code flags register.
3642 // That result is represented by a flags operand whose subtype is appropriate
3643 // to the unsignedness (etc.) of the comparison.
3644 //
3645 // Later, the instruction which matches both the Comparison Op (a Bool) and
3646 // the flags (produced by the Cmp) specifies the coding of the comparison op
3647 // by matching a specific subtype of Bool operand below, such as cmpOpU.
3648
3649
3650 // used for signed integral comparisons and fp comparisons
3651 operand cmpOp()
3652 %{
3653 match(Bool);
3654
3655 format %{ "" %}
3656
3657 // the values in interface derives from struct BoolTest::mask
3658 interface(COND_INTER) %{
3659 equal(0x0, "eq");
3660 greater(0x1, "gt");
3661 overflow(0x2, "overflow");
3662 less(0x3, "lt");
3663 not_equal(0x4, "ne");
3664 less_equal(0x5, "le");
3665 no_overflow(0x6, "no_overflow");
3666 greater_equal(0x7, "ge");
3667 %}
3668 %}
3669
3670 // used for unsigned integral comparisons
3671 operand cmpOpU()
3672 %{
3673 match(Bool);
3674
3675 format %{ "" %}
3676 // the values in interface derives from struct BoolTest::mask
3677 interface(COND_INTER) %{
3678 equal(0x0, "eq");
3679 greater(0x1, "gtu");
3680 overflow(0x2, "overflow");
3681 less(0x3, "ltu");
3682 not_equal(0x4, "ne");
3683 less_equal(0x5, "leu");
3684 no_overflow(0x6, "no_overflow");
3685 greater_equal(0x7, "geu");
3686 %}
3687 %}
3688
3689 // used for certain integral comparisons which can be
3690 // converted to bxx instructions
3691 operand cmpOpEqNe()
3692 %{
3693 match(Bool);
3694 op_cost(0);
3695 predicate(n->as_Bool()->_test._test == BoolTest::ne ||
3696 n->as_Bool()->_test._test == BoolTest::eq);
3697
3698 format %{ "" %}
3699 interface(COND_INTER) %{
3700 equal(0x0, "eq");
3701 greater(0x1, "gt");
3702 overflow(0x2, "overflow");
3703 less(0x3, "lt");
3704 not_equal(0x4, "ne");
3705 less_equal(0x5, "le");
3706 no_overflow(0x6, "no_overflow");
3707 greater_equal(0x7, "ge");
3708 %}
3709 %}
3710
3711 operand cmpOpULtGe()
3712 %{
3713 match(Bool);
3714 op_cost(0);
3715 predicate(n->as_Bool()->_test._test == BoolTest::lt ||
3716 n->as_Bool()->_test._test == BoolTest::ge);
3717
3718 format %{ "" %}
3719 interface(COND_INTER) %{
3720 equal(0x0, "eq");
3721 greater(0x1, "gtu");
3722 overflow(0x2, "overflow");
3723 less(0x3, "ltu");
3724 not_equal(0x4, "ne");
3725 less_equal(0x5, "leu");
3726 no_overflow(0x6, "no_overflow");
3727 greater_equal(0x7, "geu");
3728 %}
3729 %}
3730
3731 operand cmpOpUEqNeLeGt()
3732 %{
3733 match(Bool);
3734 op_cost(0);
3735 predicate(n->as_Bool()->_test._test == BoolTest::ne ||
3736 n->as_Bool()->_test._test == BoolTest::eq ||
3737 n->as_Bool()->_test._test == BoolTest::le ||
3738 n->as_Bool()->_test._test == BoolTest::gt);
3739
3740 format %{ "" %}
3741 interface(COND_INTER) %{
3742 equal(0x0, "eq");
3743 greater(0x1, "gtu");
3744 overflow(0x2, "overflow");
3745 less(0x3, "ltu");
3746 not_equal(0x4, "ne");
3747 less_equal(0x5, "leu");
3748 no_overflow(0x6, "no_overflow");
3749 greater_equal(0x7, "geu");
3750 %}
3751 %}
3752
3753
3754 // Flags register, used as output of compare logic
3755 operand rFlagsReg()
3756 %{
3757 constraint(ALLOC_IN_RC(reg_flags));
3758 match(RegFlags);
3759
3760 op_cost(0);
3761 format %{ "RFLAGS" %}
3762 interface(REG_INTER);
3763 %}
3764
3765 // Special Registers
3766
3767 // Method Register
3768 operand inline_cache_RegP(iRegP reg)
3769 %{
3770 constraint(ALLOC_IN_RC(method_reg)); // inline_cache_reg
3771 match(reg);
3772 match(iRegPNoSp);
3773 op_cost(0);
3774 format %{ %}
3775 interface(REG_INTER);
3776 %}
3777
3778 //----------OPERAND CLASSES----------------------------------------------------
3779 // Operand Classes are groups of operands that are used as to simplify
3780 // instruction definitions by not requiring the AD writer to specify
3781 // separate instructions for every form of operand when the
3782 // instruction accepts multiple operand types with the same basic
3783 // encoding and format. The classic case of this is memory operands.
3784
3785 // memory is used to define read/write location for load/store
3786 // instruction defs. we can turn a memory op into an Address
3787
3788 opclass memory(indirect, indOffI, indOffL, indirectN, indOffIN, indOffLN);
3789
3790 // iRegIorL2I is used for src inputs in rules for 32 bit int (I)
3791 // operations. it allows the src to be either an iRegI or a (ConvL2I
3792 // iRegL). in the latter case the l2i normally planted for a ConvL2I
3793 // can be elided because the 32-bit instruction will just employ the
3794 // lower 32 bits anyway.
3795 //
3796 // n.b. this does not elide all L2I conversions. if the truncated
3797 // value is consumed by more than one operation then the ConvL2I
3798 // cannot be bundled into the consuming nodes so an l2i gets planted
3799 // (actually an addiw $dst, $src, 0) and the downstream instructions
3800 // consume the result of the L2I as an iRegI input. That's a shame since
3801 // the addiw is actually redundant but its not too costly.
3802
3803 opclass iRegIorL2I(iRegI, iRegL2I);
3804 opclass iRegIorL(iRegI, iRegL);
3805 opclass iRegNorP(iRegN, iRegP);
3806 opclass iRegILNP(iRegI, iRegL, iRegN, iRegP);
3807 opclass iRegILNPNoSp(iRegINoSp, iRegLNoSp, iRegNNoSp, iRegPNoSp);
3808 opclass immIorL(immI, immL);
3809
3810 //----------PIPELINE-----------------------------------------------------------
3811 // Rules which define the behavior of the target architectures pipeline.
3812
3813 // For specific pipelines, e.g. generic RISC-V, define the stages of that pipeline
3814 //pipe_desc(ID, EX, MEM, WR);
3815 #define ID S0
3816 #define EX S1
3817 #define MEM S2
3818 #define WR S3
3819
3820 // Integer ALU reg operation
3821 pipeline %{
3822
3823 attributes %{
3824 // RISC-V instructions are of length 2 or 4 bytes.
3825 variable_size_instructions;
3826 instruction_unit_size = 2;
3827
3828 // Up to 4 instructions per bundle
3829 max_instructions_per_bundle = 4;
3830
3831 // The RISC-V processor fetches 64 bytes...
3832 instruction_fetch_unit_size = 64;
3833
3834 // ...in one line.
3835 instruction_fetch_units = 1;
3836 %}
3837
3838 // We don't use an actual pipeline model so don't care about resources
3839 // or description. we do use pipeline classes to introduce fixed
3840 // latencies
3841
3842 //----------RESOURCES----------------------------------------------------------
3843 // Resources are the functional units available to the machine
3844
3845 // Generic RISC-V pipeline
3846 // 1 decoder
3847 // 1 instruction decoded per cycle
3848 // 1 load/store ops per cycle, 1 branch, 1 FPU
3849 // 1 mul, 1 div
3850
3851 resources ( DECODE,
3852 ALU,
3853 MUL,
3854 DIV,
3855 BRANCH,
3856 LDST,
3857 FPU);
3858
3859 //----------PIPELINE DESCRIPTION-----------------------------------------------
3860 // Pipeline Description specifies the stages in the machine's pipeline
3861
3862 // Define the pipeline as a generic 6 stage pipeline
3863 pipe_desc(S0, S1, S2, S3, S4, S5);
3864
3865 //----------PIPELINE CLASSES---------------------------------------------------
3866 // Pipeline Classes describe the stages in which input and output are
3867 // referenced by the hardware pipeline.
3868
3869 pipe_class fp_dop_reg_reg_s(fRegF dst, fRegF src1, fRegF src2)
3870 %{
3871 single_instruction;
3872 src1 : S1(read);
3873 src2 : S2(read);
3874 dst : S5(write);
3875 DECODE : ID;
3876 FPU : S5;
3877 %}
3878
3879 pipe_class fp_dop_reg_reg_d(fRegD dst, fRegD src1, fRegD src2)
3880 %{
3881 src1 : S1(read);
3882 src2 : S2(read);
3883 dst : S5(write);
3884 DECODE : ID;
3885 FPU : S5;
3886 %}
3887
3888 pipe_class fp_uop_s(fRegF dst, fRegF src)
3889 %{
3890 single_instruction;
3891 src : S1(read);
3892 dst : S5(write);
3893 DECODE : ID;
3894 FPU : S5;
3895 %}
3896
3897 pipe_class fp_uop_d(fRegD dst, fRegD src)
3898 %{
3899 single_instruction;
3900 src : S1(read);
3901 dst : S5(write);
3902 DECODE : ID;
3903 FPU : S5;
3904 %}
3905
3906 pipe_class fp_d2f(fRegF dst, fRegD src)
3907 %{
3908 single_instruction;
3909 src : S1(read);
3910 dst : S5(write);
3911 DECODE : ID;
3912 FPU : S5;
3913 %}
3914
3915 pipe_class fp_f2d(fRegD dst, fRegF src)
3916 %{
3917 single_instruction;
3918 src : S1(read);
3919 dst : S5(write);
3920 DECODE : ID;
3921 FPU : S5;
3922 %}
3923
3924 pipe_class fp_f2i(iRegINoSp dst, fRegF src)
3925 %{
3926 single_instruction;
3927 src : S1(read);
3928 dst : S5(write);
3929 DECODE : ID;
3930 FPU : S5;
3931 %}
3932
3933 pipe_class fp_f2l(iRegLNoSp dst, fRegF src)
3934 %{
3935 single_instruction;
3936 src : S1(read);
3937 dst : S5(write);
3938 DECODE : ID;
3939 FPU : S5;
3940 %}
3941
3942 pipe_class fp_i2f(fRegF dst, iRegIorL2I src)
3943 %{
3944 single_instruction;
3945 src : S1(read);
3946 dst : S5(write);
3947 DECODE : ID;
3948 FPU : S5;
3949 %}
3950
3951 pipe_class fp_l2f(fRegF dst, iRegL src)
3952 %{
3953 single_instruction;
3954 src : S1(read);
3955 dst : S5(write);
3956 DECODE : ID;
3957 FPU : S5;
3958 %}
3959
3960 pipe_class fp_d2i(iRegINoSp dst, fRegD src)
3961 %{
3962 single_instruction;
3963 src : S1(read);
3964 dst : S5(write);
3965 DECODE : ID;
3966 FPU : S5;
3967 %}
3968
3969 pipe_class fp_d2l(iRegLNoSp dst, fRegD src)
3970 %{
3971 single_instruction;
3972 src : S1(read);
3973 dst : S5(write);
3974 DECODE : ID;
3975 FPU : S5;
3976 %}
3977
3978 pipe_class fp_i2d(fRegD dst, iRegIorL2I src)
3979 %{
3980 single_instruction;
3981 src : S1(read);
3982 dst : S5(write);
3983 DECODE : ID;
3984 FPU : S5;
3985 %}
3986
3987 pipe_class fp_l2d(fRegD dst, iRegIorL2I src)
3988 %{
3989 single_instruction;
3990 src : S1(read);
3991 dst : S5(write);
3992 DECODE : ID;
3993 FPU : S5;
3994 %}
3995
3996 pipe_class fp_div_s(fRegF dst, fRegF src1, fRegF src2)
3997 %{
3998 single_instruction;
3999 src1 : S1(read);
4000 src2 : S2(read);
4001 dst : S5(write);
4002 DECODE : ID;
4003 FPU : S5;
4004 %}
4005
4006 pipe_class fp_div_d(fRegD dst, fRegD src1, fRegD src2)
4007 %{
4008 single_instruction;
4009 src1 : S1(read);
4010 src2 : S2(read);
4011 dst : S5(write);
4012 DECODE : ID;
4013 FPU : S5;
4014 %}
4015
4016 pipe_class fp_sqrt_s(fRegF dst, fRegF src)
4017 %{
4018 single_instruction;
4019 src : S1(read);
4020 dst : S5(write);
4021 DECODE : ID;
4022 FPU : S5;
4023 %}
4024
4025 pipe_class fp_sqrt_d(fRegD dst, fRegD src)
4026 %{
4027 single_instruction;
4028 src : S1(read);
4029 dst : S5(write);
4030 DECODE : ID;
4031 FPU : S5;
4032 %}
4033
4034 pipe_class fp_load_constant_s(fRegF dst)
4035 %{
4036 single_instruction;
4037 dst : S5(write);
4038 DECODE : ID;
4039 FPU : S5;
4040 %}
4041
4042 pipe_class fp_load_constant_d(fRegD dst)
4043 %{
4044 single_instruction;
4045 dst : S5(write);
4046 DECODE : ID;
4047 FPU : S5;
4048 %}
4049
4050 pipe_class fp_load_mem_s(fRegF dst, memory mem)
4051 %{
4052 single_instruction;
4053 mem : S1(read);
4054 dst : S5(write);
4055 DECODE : ID;
4056 LDST : MEM;
4057 %}
4058
4059 pipe_class fp_load_mem_d(fRegD dst, memory mem)
4060 %{
4061 single_instruction;
4062 mem : S1(read);
4063 dst : S5(write);
4064 DECODE : ID;
4065 LDST : MEM;
4066 %}
4067
4068 pipe_class fp_store_reg_s(fRegF src, memory mem)
4069 %{
4070 single_instruction;
4071 src : S1(read);
4072 mem : S5(write);
4073 DECODE : ID;
4074 LDST : MEM;
4075 %}
4076
4077 pipe_class fp_store_reg_d(fRegD src, memory mem)
4078 %{
4079 single_instruction;
4080 src : S1(read);
4081 mem : S5(write);
4082 DECODE : ID;
4083 LDST : MEM;
4084 %}
4085
4086 //------- Integer ALU operations --------------------------
4087
4088 // Integer ALU reg-reg operation
4089 // Operands needs in ID, result generated in EX
4090 // E.g. ADD Rd, Rs1, Rs2
4091 pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2)
4092 %{
4093 single_instruction;
4094 dst : EX(write);
4095 src1 : ID(read);
4096 src2 : ID(read);
4097 DECODE : ID;
4098 ALU : EX;
4099 %}
4100
4101 // Integer ALU reg operation with constant shift
4102 // E.g. SLLI Rd, Rs1, #shift
4103 pipe_class ialu_reg_shift(iRegI dst, iRegI src1)
4104 %{
4105 single_instruction;
4106 dst : EX(write);
4107 src1 : ID(read);
4108 DECODE : ID;
4109 ALU : EX;
4110 %}
4111
4112 // Integer ALU reg-reg operation with variable shift
4113 // both operands must be available in ID
4114 // E.g. SLL Rd, Rs1, Rs2
4115 pipe_class ialu_reg_reg_vshift(iRegI dst, iRegI src1, iRegI src2)
4116 %{
4117 single_instruction;
4118 dst : EX(write);
4119 src1 : ID(read);
4120 src2 : ID(read);
4121 DECODE : ID;
4122 ALU : EX;
4123 %}
4124
4125 // Integer ALU reg operation
4126 // E.g. NEG Rd, Rs2
4127 pipe_class ialu_reg(iRegI dst, iRegI src)
4128 %{
4129 single_instruction;
4130 dst : EX(write);
4131 src : ID(read);
4132 DECODE : ID;
4133 ALU : EX;
4134 %}
4135
4136 // Integer ALU reg immediate operation
4137 // E.g. ADDI Rd, Rs1, #imm
4138 pipe_class ialu_reg_imm(iRegI dst, iRegI src1)
4139 %{
4140 single_instruction;
4141 dst : EX(write);
4142 src1 : ID(read);
4143 DECODE : ID;
4144 ALU : EX;
4145 %}
4146
4147 // Integer ALU immediate operation (no source operands)
4148 // E.g. LI Rd, #imm
4149 pipe_class ialu_imm(iRegI dst)
4150 %{
4151 single_instruction;
4152 dst : EX(write);
4153 DECODE : ID;
4154 ALU : EX;
4155 %}
4156
4157 //------- Multiply pipeline operations --------------------
4158
4159 // Multiply reg-reg
4160 // E.g. MULW Rd, Rs1, Rs2
4161 pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2)
4162 %{
4163 single_instruction;
4164 dst : WR(write);
4165 src1 : ID(read);
4166 src2 : ID(read);
4167 DECODE : ID;
4168 MUL : WR;
4169 %}
4170
4171 // E.g. MUL RD, Rs1, Rs2
4172 pipe_class lmul_reg_reg(iRegL dst, iRegL src1, iRegL src2)
4173 %{
4174 single_instruction;
4175 fixed_latency(3); // Maximum latency for 64 bit mul
4176 dst : WR(write);
4177 src1 : ID(read);
4178 src2 : ID(read);
4179 DECODE : ID;
4180 MUL : WR;
4181 %}
4182
4183 //------- Divide pipeline operations --------------------
4184
4185 // E.g. DIVW Rd, Rs1, Rs2
4186 pipe_class idiv_reg_reg(iRegI dst, iRegI src1, iRegI src2)
4187 %{
4188 single_instruction;
4189 fixed_latency(8); // Maximum latency for 32 bit divide
4190 dst : WR(write);
4191 src1 : ID(read);
4192 src2 : ID(read);
4193 DECODE : ID;
4194 DIV : WR;
4195 %}
4196
4197 // E.g. DIV RD, Rs1, Rs2
4198 pipe_class ldiv_reg_reg(iRegL dst, iRegL src1, iRegL src2)
4199 %{
4200 single_instruction;
4201 fixed_latency(16); // Maximum latency for 64 bit divide
4202 dst : WR(write);
4203 src1 : ID(read);
4204 src2 : ID(read);
4205 DECODE : ID;
4206 DIV : WR;
4207 %}
4208
4209 //------- Load pipeline operations ------------------------
4210
4211 // Load - prefetch
4212 // Eg. PREFETCH_W mem
4213 pipe_class iload_prefetch(memory mem)
4214 %{
4215 single_instruction;
4216 mem : ID(read);
4217 DECODE : ID;
4218 LDST : MEM;
4219 %}
4220
4221 // Load - reg, mem
4222 // E.g. LA Rd, mem
4223 pipe_class iload_reg_mem(iRegI dst, memory mem)
4224 %{
4225 single_instruction;
4226 dst : WR(write);
4227 mem : ID(read);
4228 DECODE : ID;
4229 LDST : MEM;
4230 %}
4231
4232 // Load - reg, reg
4233 // E.g. LD Rd, Rs
4234 pipe_class iload_reg_reg(iRegI dst, iRegI src)
4235 %{
4236 single_instruction;
4237 dst : WR(write);
4238 src : ID(read);
4239 DECODE : ID;
4240 LDST : MEM;
4241 %}
4242
4243 //------- Store pipeline operations -----------------------
4244
4245 // Store - zr, mem
4246 // E.g. SD zr, mem
4247 pipe_class istore_mem(memory mem)
4248 %{
4249 single_instruction;
4250 mem : ID(read);
4251 DECODE : ID;
4252 LDST : MEM;
4253 %}
4254
4255 // Store - reg, mem
4256 // E.g. SD Rs, mem
4257 pipe_class istore_reg_mem(iRegI src, memory mem)
4258 %{
4259 single_instruction;
4260 mem : ID(read);
4261 src : EX(read);
4262 DECODE : ID;
4263 LDST : MEM;
4264 %}
4265
4266 // Store - reg, reg
4267 // E.g. SD Rs2, Rs1
4268 pipe_class istore_reg_reg(iRegI dst, iRegI src)
4269 %{
4270 single_instruction;
4271 dst : ID(read);
4272 src : EX(read);
4273 DECODE : ID;
4274 LDST : MEM;
4275 %}
4276
4277 //------- Control transfer pipeline operations ------------
4278
4279 // Branch
4280 pipe_class pipe_branch()
4281 %{
4282 single_instruction;
4283 DECODE : ID;
4284 BRANCH : EX;
4285 %}
4286
4287 // Branch
4288 pipe_class pipe_branch_reg(iRegI src)
4289 %{
4290 single_instruction;
4291 src : ID(read);
4292 DECODE : ID;
4293 BRANCH : EX;
4294 %}
4295
4296 // Compare & Branch
4297 // E.g. BEQ Rs1, Rs2, L
4298 pipe_class pipe_cmp_branch(iRegI src1, iRegI src2)
4299 %{
4300 single_instruction;
4301 src1 : ID(read);
4302 src2 : ID(read);
4303 DECODE : ID;
4304 BRANCH : EX;
4305 %}
4306
4307 // E.g. BEQZ Rs, L
4308 pipe_class pipe_cmpz_branch(iRegI src)
4309 %{
4310 single_instruction;
4311 src : ID(read);
4312 DECODE : ID;
4313 BRANCH : EX;
4314 %}
4315
4316 //------- Synchronisation operations ----------------------
4317 // Any operation requiring serialization
4318 // E.g. FENCE/Atomic Ops/Load Acquire/Store Release
4319 pipe_class pipe_serial()
4320 %{
4321 single_instruction;
4322 force_serialization;
4323 fixed_latency(16);
4324 DECODE : ID;
4325 LDST : MEM;
4326 %}
4327
4328 pipe_class pipe_slow()
4329 %{
4330 instruction_count(10);
4331 multiple_bundles;
4332 force_serialization;
4333 fixed_latency(16);
4334 DECODE : ID;
4335 LDST : MEM;
4336 %}
4337
4338 // The real do-nothing guy
4339 pipe_class real_empty()
4340 %{
4341 instruction_count(0);
4342 %}
4343
4344 // Empty pipeline class
4345 pipe_class pipe_class_empty()
4346 %{
4347 single_instruction;
4348 fixed_latency(0);
4349 %}
4350
4351 // Default pipeline class.
4352 pipe_class pipe_class_default()
4353 %{
4354 single_instruction;
4355 fixed_latency(2);
4356 %}
4357
4358 // Pipeline class for compares.
4359 pipe_class pipe_class_compare()
4360 %{
4361 single_instruction;
4362 fixed_latency(16);
4363 %}
4364
4365 // Pipeline class for memory operations.
4366 pipe_class pipe_class_memory()
4367 %{
4368 single_instruction;
4369 fixed_latency(16);
4370 %}
4371
4372 // Pipeline class for call.
4373 pipe_class pipe_class_call()
4374 %{
4375 single_instruction;
4376 fixed_latency(100);
4377 %}
4378
4379 // Define the class for the Nop node.
4380 define %{
4381 MachNop = pipe_class_empty;
4382 %}
4383 %}
4384 //----------INSTRUCTIONS-------------------------------------------------------
4385 //
4386 // match -- States which machine-independent subtree may be replaced
4387 // by this instruction.
4388 // ins_cost -- The estimated cost of this instruction is used by instruction
4389 // selection to identify a minimum cost tree of machine
4390 // instructions that matches a tree of machine-independent
4391 // instructions.
4392 // format -- A string providing the disassembly for this instruction.
4393 // The value of an instruction's operand may be inserted
4394 // by referring to it with a '$' prefix.
4395 // opcode -- Three instruction opcodes may be provided. These are referred
4396 // to within an encode class as $primary, $secondary, and $tertiary
4397 // rrspectively. The primary opcode is commonly used to
4398 // indicate the type of machine instruction, while secondary
4399 // and tertiary are often used for prefix options or addressing
4400 // modes.
4401 // ins_encode -- A list of encode classes with parameters. The encode class
4402 // name must have been defined in an 'enc_class' specification
4403 // in the encode section of the architecture description.
4404
4405 // ============================================================================
4406 // Memory (Load/Store) Instructions
4407
4408 // Load Instructions
4409
4410 // Load Byte (8 bit signed)
4411 instruct loadB(iRegINoSp dst, memory mem)
4412 %{
4413 match(Set dst (LoadB mem));
4414
4415 ins_cost(LOAD_COST);
4416 format %{ "lb $dst, $mem\t# byte, #@loadB" %}
4417
4418 ins_encode %{
4419 __ lb(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4420 %}
4421
4422 ins_pipe(iload_reg_mem);
4423 %}
4424
4425 // Load Byte (8 bit signed) into long
4426 instruct loadB2L(iRegLNoSp dst, memory mem)
4427 %{
4428 match(Set dst (ConvI2L (LoadB mem)));
4429
4430 ins_cost(LOAD_COST);
4431 format %{ "lb $dst, $mem\t# byte, #@loadB2L" %}
4432
4433 ins_encode %{
4434 __ lb(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4435 %}
4436
4437 ins_pipe(iload_reg_mem);
4438 %}
4439
4440 // Load Byte (8 bit unsigned)
4441 instruct loadUB(iRegINoSp dst, memory mem)
4442 %{
4443 match(Set dst (LoadUB mem));
4444
4445 ins_cost(LOAD_COST);
4446 format %{ "lbu $dst, $mem\t# byte, #@loadUB" %}
4447
4448 ins_encode %{
4449 __ lbu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4450 %}
4451
4452 ins_pipe(iload_reg_mem);
4453 %}
4454
4455 // Load Byte (8 bit unsigned) into long
4456 instruct loadUB2L(iRegLNoSp dst, memory mem)
4457 %{
4458 match(Set dst (ConvI2L (LoadUB mem)));
4459
4460 ins_cost(LOAD_COST);
4461 format %{ "lbu $dst, $mem\t# byte, #@loadUB2L" %}
4462
4463 ins_encode %{
4464 __ lbu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4465 %}
4466
4467 ins_pipe(iload_reg_mem);
4468 %}
4469
4470 // Load Short (16 bit signed)
4471 instruct loadS(iRegINoSp dst, memory mem)
4472 %{
4473 match(Set dst (LoadS mem));
4474
4475 ins_cost(LOAD_COST);
4476 format %{ "lh $dst, $mem\t# short, #@loadS" %}
4477
4478 ins_encode %{
4479 __ lh(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4480 %}
4481
4482 ins_pipe(iload_reg_mem);
4483 %}
4484
4485 // Load Short (16 bit signed) into long
4486 instruct loadS2L(iRegLNoSp dst, memory mem)
4487 %{
4488 match(Set dst (ConvI2L (LoadS mem)));
4489
4490 ins_cost(LOAD_COST);
4491 format %{ "lh $dst, $mem\t# short, #@loadS2L" %}
4492
4493 ins_encode %{
4494 __ lh(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4495 %}
4496
4497 ins_pipe(iload_reg_mem);
4498 %}
4499
4500 // Load Char (16 bit unsigned)
4501 instruct loadUS(iRegINoSp dst, memory mem)
4502 %{
4503 match(Set dst (LoadUS mem));
4504
4505 ins_cost(LOAD_COST);
4506 format %{ "lhu $dst, $mem\t# short, #@loadUS" %}
4507
4508 ins_encode %{
4509 __ lhu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4510 %}
4511
4512 ins_pipe(iload_reg_mem);
4513 %}
4514
4515 // Load Short/Char (16 bit unsigned) into long
4516 instruct loadUS2L(iRegLNoSp dst, memory mem)
4517 %{
4518 match(Set dst (ConvI2L (LoadUS mem)));
4519
4520 ins_cost(LOAD_COST);
4521 format %{ "lhu $dst, $mem\t# short, #@loadUS2L" %}
4522
4523 ins_encode %{
4524 __ lhu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4525 %}
4526
4527 ins_pipe(iload_reg_mem);
4528 %}
4529
4530 // Load Integer (32 bit signed)
4531 instruct loadI(iRegINoSp dst, memory mem)
4532 %{
4533 match(Set dst (LoadI mem));
4534
4535 ins_cost(LOAD_COST);
4536 format %{ "lw $dst, $mem\t# int, #@loadI" %}
4537
4538 ins_encode %{
4539 __ lw(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4540 %}
4541
4542 ins_pipe(iload_reg_mem);
4543 %}
4544
4545 // Load Integer (32 bit signed) into long
4546 instruct loadI2L(iRegLNoSp dst, memory mem)
4547 %{
4548 match(Set dst (ConvI2L (LoadI mem)));
4549
4550 ins_cost(LOAD_COST);
4551 format %{ "lw $dst, $mem\t# int, #@loadI2L" %}
4552
4553 ins_encode %{
4554 __ lw(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4555 %}
4556
4557 ins_pipe(iload_reg_mem);
4558 %}
4559
4560 // Load Integer (32 bit unsigned) into long
4561 instruct loadUI2L(iRegLNoSp dst, memory mem, immL_32bits mask)
4562 %{
4563 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
4564
4565 ins_cost(LOAD_COST);
4566 format %{ "lwu $dst, $mem\t# int, #@loadUI2L" %}
4567
4568 ins_encode %{
4569 __ lwu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4570 %}
4571
4572 ins_pipe(iload_reg_mem);
4573 %}
4574
4575 // Load Long (64 bit signed)
4576 instruct loadL(iRegLNoSp dst, memory mem)
4577 %{
4578 match(Set dst (LoadL mem));
4579
4580 ins_cost(LOAD_COST);
4581 format %{ "ld $dst, $mem\t# int, #@loadL" %}
4582
4583 ins_encode %{
4584 __ ld(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4585 %}
4586
4587 ins_pipe(iload_reg_mem);
4588 %}
4589
4590 // Load Range
4591 instruct loadRange(iRegINoSp dst, memory mem)
4592 %{
4593 match(Set dst (LoadRange mem));
4594
4595 ins_cost(LOAD_COST);
4596 format %{ "lwu $dst, $mem\t# range, #@loadRange" %}
4597
4598 ins_encode %{
4599 __ lwu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4600 %}
4601
4602 ins_pipe(iload_reg_mem);
4603 %}
4604
4605 // Load Pointer
4606 instruct loadP(iRegPNoSp dst, memory mem)
4607 %{
4608 match(Set dst (LoadP mem));
4609 predicate(n->as_Load()->barrier_data() == 0);
4610
4611 ins_cost(LOAD_COST);
4612 format %{ "ld $dst, $mem\t# ptr, #@loadP" %}
4613
4614 ins_encode %{
4615 __ ld(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4616 %}
4617
4618 ins_pipe(iload_reg_mem);
4619 %}
4620
4621 // Load Compressed Pointer
4622 instruct loadN(iRegNNoSp dst, memory mem)
4623 %{
4624 predicate(n->as_Load()->barrier_data() == 0);
4625 match(Set dst (LoadN mem));
4626
4627 ins_cost(LOAD_COST);
4628 format %{ "lwu $dst, $mem\t# compressed ptr, #@loadN" %}
4629
4630 ins_encode %{
4631 __ lwu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4632 %}
4633
4634 ins_pipe(iload_reg_mem);
4635 %}
4636
4637 // Load Klass Pointer
4638 instruct loadKlass(iRegPNoSp dst, memory mem)
4639 %{
4640 match(Set dst (LoadKlass mem));
4641
4642 ins_cost(LOAD_COST);
4643 format %{ "ld $dst, $mem\t# class, #@loadKlass" %}
4644
4645 ins_encode %{
4646 __ ld(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4647 %}
4648
4649 ins_pipe(iload_reg_mem);
4650 %}
4651
4652 // Load Narrow Klass Pointer
4653 instruct loadNKlass(iRegNNoSp dst, memory mem)
4654 %{
4655 predicate(!UseCompactObjectHeaders);
4656 match(Set dst (LoadNKlass mem));
4657
4658 ins_cost(LOAD_COST);
4659 format %{ "lwu $dst, $mem\t# compressed class ptr, #@loadNKlass" %}
4660
4661 ins_encode %{
4662 __ lwu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4663 %}
4664
4665 ins_pipe(iload_reg_mem);
4666 %}
4667
4668 instruct loadNKlassCompactHeaders(iRegNNoSp dst, memory mem)
4669 %{
4670 predicate(UseCompactObjectHeaders);
4671 match(Set dst (LoadNKlass mem));
4672
4673 ins_cost(LOAD_COST);
4674 format %{
4675 "lwu $dst, $mem\t# compressed klass ptr, shifted\n\t"
4676 "srli $dst, $dst, markWord::klass_shift_at_offset"
4677 %}
4678
4679 ins_encode %{
4680 Unimplemented();
4681 // __ lwu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4682 // __ srli(as_Register($dst$$reg), as_Register($dst$$reg), (unsigned) markWord::klass_shift_at_offset);
4683 %}
4684
4685 ins_pipe(iload_reg_mem);
4686 %}
4687
4688 // Load Float
4689 instruct loadF(fRegF dst, memory mem)
4690 %{
4691 match(Set dst (LoadF mem));
4692
4693 ins_cost(LOAD_COST);
4694 format %{ "flw $dst, $mem\t# float, #@loadF" %}
4695
4696 ins_encode %{
4697 __ flw(as_FloatRegister($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4698 %}
4699
4700 ins_pipe(fp_load_mem_s);
4701 %}
4702
4703 // Load Double
4704 instruct loadD(fRegD dst, memory mem)
4705 %{
4706 match(Set dst (LoadD mem));
4707
4708 ins_cost(LOAD_COST);
4709 format %{ "fld $dst, $mem\t# double, #@loadD" %}
4710
4711 ins_encode %{
4712 __ fld(as_FloatRegister($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4713 %}
4714
4715 ins_pipe(fp_load_mem_d);
4716 %}
4717
4718 // Load Int Constant
4719 instruct loadConI(iRegINoSp dst, immI src)
4720 %{
4721 match(Set dst src);
4722
4723 ins_cost(ALU_COST);
4724 format %{ "mv $dst, $src\t# int, #@loadConI" %}
4725
4726 ins_encode(riscv_enc_mov_imm(dst, src));
4727
4728 ins_pipe(ialu_imm);
4729 %}
4730
4731 // Load Long Constant
4732 instruct loadConL(iRegLNoSp dst, immL src)
4733 %{
4734 match(Set dst src);
4735
4736 ins_cost(ALU_COST);
4737 format %{ "mv $dst, $src\t# long, #@loadConL" %}
4738
4739 ins_encode(riscv_enc_mov_imm(dst, src));
4740
4741 ins_pipe(ialu_imm);
4742 %}
4743
4744 // Load Pointer Constant
4745 instruct loadConP(iRegPNoSp dst, immP con)
4746 %{
4747 match(Set dst con);
4748
4749 ins_cost(ALU_COST);
4750 format %{ "mv $dst, $con\t# ptr, #@loadConP" %}
4751
4752 ins_encode(riscv_enc_mov_p(dst, con));
4753
4754 ins_pipe(ialu_imm);
4755 %}
4756
4757 // Load Null Pointer Constant
4758 instruct loadConP0(iRegPNoSp dst, immP0 con)
4759 %{
4760 match(Set dst con);
4761
4762 ins_cost(ALU_COST);
4763 format %{ "mv $dst, $con\t# null pointer, #@loadConP0" %}
4764
4765 ins_encode(riscv_enc_mov_zero(dst));
4766
4767 ins_pipe(ialu_imm);
4768 %}
4769
4770 // Load Pointer Constant One
4771 instruct loadConP1(iRegPNoSp dst, immP_1 con)
4772 %{
4773 match(Set dst con);
4774
4775 ins_cost(ALU_COST);
4776 format %{ "mv $dst, $con\t# load ptr constant one, #@loadConP1" %}
4777
4778 ins_encode(riscv_enc_mov_p1(dst));
4779
4780 ins_pipe(ialu_imm);
4781 %}
4782
4783 // Load Narrow Pointer Constant
4784 instruct loadConN(iRegNNoSp dst, immN con)
4785 %{
4786 match(Set dst con);
4787
4788 ins_cost(ALU_COST * 4);
4789 format %{ "mv $dst, $con\t# compressed ptr, #@loadConN" %}
4790
4791 ins_encode(riscv_enc_mov_n(dst, con));
4792
4793 ins_pipe(ialu_imm);
4794 %}
4795
4796 // Load Narrow Null Pointer Constant
4797 instruct loadConN0(iRegNNoSp dst, immN0 con)
4798 %{
4799 match(Set dst con);
4800
4801 ins_cost(ALU_COST);
4802 format %{ "mv $dst, $con\t# compressed null pointer, #@loadConN0" %}
4803
4804 ins_encode(riscv_enc_mov_zero(dst));
4805
4806 ins_pipe(ialu_imm);
4807 %}
4808
4809 // Load Narrow Klass Constant
4810 instruct loadConNKlass(iRegNNoSp dst, immNKlass con)
4811 %{
4812 match(Set dst con);
4813
4814 ins_cost(ALU_COST * 6);
4815 format %{ "mv $dst, $con\t# compressed klass ptr, #@loadConNKlass" %}
4816
4817 ins_encode(riscv_enc_mov_nk(dst, con));
4818
4819 ins_pipe(ialu_imm);
4820 %}
4821
4822 // Load Half Float Constant
4823 instruct loadConH(fRegF dst, immH con) %{
4824 match(Set dst con);
4825
4826 ins_cost(LOAD_COST);
4827 format %{
4828 "flh $dst, [$constantaddress]\t# load from constant table: float=$con, #@loadConH"
4829 %}
4830
4831 ins_encode %{
4832 assert(UseZfh || UseZfhmin, "must");
4833 if (MacroAssembler::can_hf_imm_load($con$$constant)) {
4834 __ fli_h(as_FloatRegister($dst$$reg), $con$$constant);
4835 } else {
4836 __ flh(as_FloatRegister($dst$$reg), $constantaddress($con));
4837 }
4838 %}
4839
4840 ins_pipe(fp_load_constant_s);
4841 %}
4842
4843 instruct loadConH0(fRegF dst, immH0 con) %{
4844 match(Set dst con);
4845
4846 ins_cost(XFER_COST);
4847
4848 format %{ "fmv.h.x $dst, zr\t# float, #@loadConH0" %}
4849
4850 ins_encode %{
4851 assert(UseZfh || UseZfhmin, "must");
4852 __ fmv_h_x(as_FloatRegister($dst$$reg), zr);
4853 %}
4854
4855 ins_pipe(fp_load_constant_s);
4856 %}
4857
4858 // Load Float Constant
4859 instruct loadConF(fRegF dst, immF con) %{
4860 match(Set dst con);
4861
4862 ins_cost(LOAD_COST);
4863 format %{
4864 "flw $dst, [$constantaddress]\t# load from constant table: float=$con, #@loadConF"
4865 %}
4866
4867 ins_encode %{
4868 if (MacroAssembler::can_fp_imm_load($con$$constant)) {
4869 __ fli_s(as_FloatRegister($dst$$reg), $con$$constant);
4870 } else {
4871 __ flw(as_FloatRegister($dst$$reg), $constantaddress($con));
4872 }
4873 %}
4874
4875 ins_pipe(fp_load_constant_s);
4876 %}
4877
4878 instruct loadConF0(fRegF dst, immF0 con) %{
4879 match(Set dst con);
4880
4881 ins_cost(XFER_COST);
4882
4883 format %{ "fmv.w.x $dst, zr\t# float, #@loadConF0" %}
4884
4885 ins_encode %{
4886 __ fmv_w_x(as_FloatRegister($dst$$reg), zr);
4887 %}
4888
4889 ins_pipe(fp_load_constant_s);
4890 %}
4891
4892 // Load Double Constant
4893 instruct loadConD(fRegD dst, immD con) %{
4894 match(Set dst con);
4895
4896 ins_cost(LOAD_COST);
4897 format %{
4898 "fld $dst, [$constantaddress]\t# load from constant table: double=$con, #@loadConD"
4899 %}
4900
4901 ins_encode %{
4902 if (MacroAssembler::can_dp_imm_load($con$$constant)) {
4903 __ fli_d(as_FloatRegister($dst$$reg), $con$$constant);
4904 } else {
4905 __ fld(as_FloatRegister($dst$$reg), $constantaddress($con));
4906 }
4907 %}
4908
4909 ins_pipe(fp_load_constant_d);
4910 %}
4911
4912 instruct loadConD0(fRegD dst, immD0 con) %{
4913 match(Set dst con);
4914
4915 ins_cost(XFER_COST);
4916
4917 format %{ "fmv.d.x $dst, zr\t# double, #@loadConD0" %}
4918
4919 ins_encode %{
4920 __ fmv_d_x(as_FloatRegister($dst$$reg), zr);
4921 %}
4922
4923 ins_pipe(fp_load_constant_d);
4924 %}
4925
4926 // Store Byte
4927 instruct storeB(iRegIorL2I src, memory mem)
4928 %{
4929 match(Set mem (StoreB mem src));
4930
4931 ins_cost(STORE_COST);
4932 format %{ "sb $src, $mem\t# byte, #@storeB" %}
4933
4934 ins_encode %{
4935 __ sb(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
4936 %}
4937
4938 ins_pipe(istore_reg_mem);
4939 %}
4940
4941 instruct storeimmB0(immI0 zero, memory mem)
4942 %{
4943 match(Set mem (StoreB mem zero));
4944
4945 ins_cost(STORE_COST);
4946 format %{ "sb zr, $mem\t# byte, #@storeimmB0" %}
4947
4948 ins_encode %{
4949 __ sb(zr, Address(as_Register($mem$$base), $mem$$disp));
4950 %}
4951
4952 ins_pipe(istore_mem);
4953 %}
4954
4955 // Store Char/Short
4956 instruct storeC(iRegIorL2I src, memory mem)
4957 %{
4958 match(Set mem (StoreC mem src));
4959
4960 ins_cost(STORE_COST);
4961 format %{ "sh $src, $mem\t# short, #@storeC" %}
4962
4963 ins_encode %{
4964 __ sh(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
4965 %}
4966
4967 ins_pipe(istore_reg_mem);
4968 %}
4969
4970 instruct storeimmC0(immI0 zero, memory mem)
4971 %{
4972 match(Set mem (StoreC mem zero));
4973
4974 ins_cost(STORE_COST);
4975 format %{ "sh zr, $mem\t# short, #@storeimmC0" %}
4976
4977 ins_encode %{
4978 __ sh(zr, Address(as_Register($mem$$base), $mem$$disp));
4979 %}
4980
4981 ins_pipe(istore_mem);
4982 %}
4983
4984 // Store Integer
4985 instruct storeI(iRegIorL2I src, memory mem)
4986 %{
4987 match(Set mem(StoreI mem src));
4988
4989 ins_cost(STORE_COST);
4990 format %{ "sw $src, $mem\t# int, #@storeI" %}
4991
4992 ins_encode %{
4993 __ sw(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
4994 %}
4995
4996 ins_pipe(istore_reg_mem);
4997 %}
4998
4999 instruct storeimmI0(immI0 zero, memory mem)
5000 %{
5001 match(Set mem(StoreI mem zero));
5002
5003 ins_cost(STORE_COST);
5004 format %{ "sw zr, $mem\t# int, #@storeimmI0" %}
5005
5006 ins_encode %{
5007 __ sw(zr, Address(as_Register($mem$$base), $mem$$disp));
5008 %}
5009
5010 ins_pipe(istore_mem);
5011 %}
5012
5013 // Store Long (64 bit signed)
5014 instruct storeL(iRegL src, memory mem)
5015 %{
5016 match(Set mem (StoreL mem src));
5017
5018 ins_cost(STORE_COST);
5019 format %{ "sd $src, $mem\t# long, #@storeL" %}
5020
5021 ins_encode %{
5022 __ sd(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5023 %}
5024
5025 ins_pipe(istore_reg_mem);
5026 %}
5027
5028 // Store Long (64 bit signed)
5029 instruct storeimmL0(immL0 zero, memory mem)
5030 %{
5031 match(Set mem (StoreL mem zero));
5032
5033 ins_cost(STORE_COST);
5034 format %{ "sd zr, $mem\t# long, #@storeimmL0" %}
5035
5036 ins_encode %{
5037 __ sd(zr, Address(as_Register($mem$$base), $mem$$disp));
5038 %}
5039
5040 ins_pipe(istore_mem);
5041 %}
5042
5043 // Store Pointer
5044 instruct storeP(iRegP src, memory mem)
5045 %{
5046 match(Set mem (StoreP mem src));
5047 predicate(n->as_Store()->barrier_data() == 0);
5048
5049 ins_cost(STORE_COST);
5050 format %{ "sd $src, $mem\t# ptr, #@storeP" %}
5051
5052 ins_encode %{
5053 __ sd(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5054 %}
5055
5056 ins_pipe(istore_reg_mem);
5057 %}
5058
5059 // Store Pointer
5060 instruct storeimmP0(immP0 zero, memory mem)
5061 %{
5062 match(Set mem (StoreP mem zero));
5063 predicate(n->as_Store()->barrier_data() == 0);
5064
5065 ins_cost(STORE_COST);
5066 format %{ "sd zr, $mem\t# ptr, #@storeimmP0" %}
5067
5068 ins_encode %{
5069 __ sd(zr, Address(as_Register($mem$$base), $mem$$disp));
5070 %}
5071
5072 ins_pipe(istore_mem);
5073 %}
5074
5075 // Store Compressed Pointer
5076 instruct storeN(iRegN src, memory mem)
5077 %{
5078 predicate(n->as_Store()->barrier_data() == 0);
5079 match(Set mem (StoreN mem src));
5080
5081 ins_cost(STORE_COST);
5082 format %{ "sw $src, $mem\t# compressed ptr, #@storeN" %}
5083
5084 ins_encode %{
5085 __ sw(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5086 %}
5087
5088 ins_pipe(istore_reg_mem);
5089 %}
5090
5091 instruct storeImmN0(immN0 zero, memory mem)
5092 %{
5093 predicate(n->as_Store()->barrier_data() == 0);
5094 match(Set mem (StoreN mem zero));
5095
5096 ins_cost(STORE_COST);
5097 format %{ "sw zr, $mem\t# compressed ptr, #@storeImmN0" %}
5098
5099 ins_encode %{
5100 __ sw(zr, Address(as_Register($mem$$base), $mem$$disp));
5101 %}
5102
5103 ins_pipe(istore_reg_mem);
5104 %}
5105
5106 // Store Float
5107 instruct storeF(fRegF src, memory mem)
5108 %{
5109 match(Set mem (StoreF mem src));
5110
5111 ins_cost(STORE_COST);
5112 format %{ "fsw $src, $mem\t# float, #@storeF" %}
5113
5114 ins_encode %{
5115 __ fsw(as_FloatRegister($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5116 %}
5117
5118 ins_pipe(fp_store_reg_s);
5119 %}
5120
5121 // Store Double
5122 instruct storeD(fRegD src, memory mem)
5123 %{
5124 match(Set mem (StoreD mem src));
5125
5126 ins_cost(STORE_COST);
5127 format %{ "fsd $src, $mem\t# double, #@storeD" %}
5128
5129 ins_encode %{
5130 __ fsd(as_FloatRegister($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5131 %}
5132
5133 ins_pipe(fp_store_reg_d);
5134 %}
5135
5136 // Store Compressed Klass Pointer
5137 instruct storeNKlass(iRegN src, memory mem)
5138 %{
5139 match(Set mem (StoreNKlass mem src));
5140
5141 ins_cost(STORE_COST);
5142 format %{ "sw $src, $mem\t# compressed klass ptr, #@storeNKlass" %}
5143
5144 ins_encode %{
5145 __ sw(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5146 %}
5147
5148 ins_pipe(istore_reg_mem);
5149 %}
5150
5151 // ============================================================================
5152 // Prefetch instructions
5153 // Must be safe to execute with invalid address (cannot fault).
5154
5155 instruct prefetchalloc( memory mem ) %{
5156 predicate(UseZicbop);
5157 match(PrefetchAllocation mem);
5158
5159 ins_cost(ALU_COST * 1);
5160 format %{ "prefetch_w $mem\t# Prefetch for write" %}
5161
5162 ins_encode %{
5163 if (Assembler::is_simm12($mem$$disp)) {
5164 if (($mem$$disp & 0x1f) == 0) {
5165 __ prefetch_w(as_Register($mem$$base), $mem$$disp);
5166 } else {
5167 __ addi(t0, as_Register($mem$$base), $mem$$disp);
5168 __ prefetch_w(t0, 0);
5169 }
5170 } else {
5171 __ mv(t0, $mem$$disp);
5172 __ add(t0, as_Register($mem$$base), t0);
5173 __ prefetch_w(t0, 0);
5174 }
5175 %}
5176
5177 ins_pipe(iload_prefetch);
5178 %}
5179
5180 // ============================================================================
5181 // Atomic operation instructions
5182 //
5183
5184 // standard CompareAndSwapX when we are using barriers
5185 // these have higher priority than the rules selected by a predicate
5186 instruct compareAndSwapB_narrow(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5187 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5188 %{
5189 predicate(!UseZabha || !UseZacas);
5190
5191 match(Set res (CompareAndSwapB mem (Binary oldval newval)));
5192
5193 ins_cost(2 * VOLATILE_REF_COST);
5194
5195 effect(TEMP_DEF res, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3, KILL cr);
5196
5197 format %{
5198 "cmpxchg $mem, $oldval, $newval\t# (byte) if $mem == $oldval then $mem <-- $newval\n\t"
5199 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapB_narrow"
5200 %}
5201
5202 ins_encode %{
5203 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5204 Assembler::relaxed /* acquire */, Assembler::rl /* release */, $res$$Register,
5205 true /* result as bool */, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5206 %}
5207
5208 ins_pipe(pipe_slow);
5209 %}
5210
5211 instruct compareAndSwapB(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5212 %{
5213 predicate(UseZabha && UseZacas);
5214
5215 match(Set res (CompareAndSwapB mem (Binary oldval newval)));
5216
5217 ins_cost(2 * VOLATILE_REF_COST);
5218
5219 format %{
5220 "cmpxchg $mem, $oldval, $newval\t# (byte) if $mem == $oldval then $mem <-- $newval\n\t"
5221 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapB"
5222 %}
5223
5224 ins_encode %{
5225 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5226 Assembler::relaxed /* acquire */, Assembler::rl /* release */, $res$$Register,
5227 true /* result as bool */);
5228 %}
5229
5230 ins_pipe(pipe_slow);
5231 %}
5232
5233 instruct compareAndSwapS_narrow(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5234 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5235 %{
5236 predicate(!UseZabha || !UseZacas);
5237
5238 match(Set res (CompareAndSwapS mem (Binary oldval newval)));
5239
5240 ins_cost(2 * VOLATILE_REF_COST);
5241
5242 effect(TEMP_DEF res, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3, KILL cr);
5243
5244 format %{
5245 "cmpxchg $mem, $oldval, $newval\t# (short) if $mem == $oldval then $mem <-- $newval\n\t"
5246 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapS_narrow"
5247 %}
5248
5249 ins_encode %{
5250 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5251 Assembler::relaxed /* acquire */, Assembler::rl /* release */, $res$$Register,
5252 true /* result as bool */, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5253 %}
5254
5255 ins_pipe(pipe_slow);
5256 %}
5257
5258 instruct compareAndSwapS(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5259 %{
5260 predicate(UseZabha && UseZacas);
5261
5262 match(Set res (CompareAndSwapS mem (Binary oldval newval)));
5263
5264 ins_cost(2 * VOLATILE_REF_COST);
5265
5266 format %{
5267 "cmpxchg $mem, $oldval, $newval\t# (short) if $mem == $oldval then $mem <-- $newval\n\t"
5268 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapS"
5269 %}
5270
5271 ins_encode %{
5272 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5273 Assembler::relaxed /* acquire */, Assembler::rl /* release */, $res$$Register,
5274 true /* result as bool */);
5275 %}
5276
5277 ins_pipe(pipe_slow);
5278 %}
5279
5280 instruct compareAndSwapI(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5281 %{
5282 match(Set res (CompareAndSwapI mem (Binary oldval newval)));
5283
5284 ins_cost(2 * VOLATILE_REF_COST);
5285
5286 format %{
5287 "cmpxchg $mem, $oldval, $newval\t# (int) if $mem == $oldval then $mem <-- $newval\n\t"
5288 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapI"
5289 %}
5290
5291 ins_encode %{
5292 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
5293 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
5294 /*result as bool*/ true);
5295 %}
5296
5297 ins_pipe(pipe_slow);
5298 %}
5299
5300 instruct compareAndSwapL(iRegINoSp res, indirect mem, iRegL oldval, iRegL newval)
5301 %{
5302 match(Set res (CompareAndSwapL mem (Binary oldval newval)));
5303
5304 ins_cost(2 * VOLATILE_REF_COST);
5305
5306 format %{
5307 "cmpxchg $mem, $oldval, $newval\t# (long) if $mem == $oldval then $mem <-- $newval\n\t"
5308 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapL"
5309 %}
5310
5311 ins_encode %{
5312 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5313 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
5314 /*result as bool*/ true);
5315 %}
5316
5317 ins_pipe(pipe_slow);
5318 %}
5319
5320 instruct compareAndSwapP(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval)
5321 %{
5322 predicate(n->as_LoadStore()->barrier_data() == 0);
5323
5324 match(Set res (CompareAndSwapP mem (Binary oldval newval)));
5325
5326 ins_cost(2 * VOLATILE_REF_COST);
5327
5328 format %{
5329 "cmpxchg $mem, $oldval, $newval\t# (ptr) if $mem == $oldval then $mem <-- $newval\n\t"
5330 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapP"
5331 %}
5332
5333 ins_encode %{
5334 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5335 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
5336 /*result as bool*/ true);
5337 %}
5338
5339 ins_pipe(pipe_slow);
5340 %}
5341
5342 instruct compareAndSwapN(iRegINoSp res, indirect mem, iRegN oldval, iRegN newval)
5343 %{
5344 predicate(n->as_LoadStore()->barrier_data() == 0);
5345
5346 match(Set res (CompareAndSwapN mem (Binary oldval newval)));
5347
5348 ins_cost(2 * VOLATILE_REF_COST);
5349
5350 format %{
5351 "cmpxchg $mem, $oldval, $newval\t# (narrow oop) if $mem == $oldval then $mem <-- $newval\n\t"
5352 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapN"
5353 %}
5354
5355 ins_encode %{
5356 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
5357 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
5358 /*result as bool*/ true);
5359 %}
5360
5361 ins_pipe(pipe_slow);
5362 %}
5363
5364 // alternative CompareAndSwapX when we are eliding barriers
5365 instruct compareAndSwapBAcq_narrow(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5366 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5367 %{
5368 predicate((!UseZabha || !UseZacas) && needs_acquiring_load_reserved(n));
5369
5370 match(Set res (CompareAndSwapB mem (Binary oldval newval)));
5371
5372 ins_cost(2 * VOLATILE_REF_COST);
5373
5374 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5375
5376 format %{
5377 "cmpxchg_acq $mem, $oldval, $newval\t# (byte) if $mem == $oldval then $mem <-- $newval\n\t"
5378 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapBAcq_narrow"
5379 %}
5380
5381 ins_encode %{
5382 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5383 Assembler::aq /* acquire */, Assembler::rl /* release */, $res$$Register,
5384 true /* result as bool */, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5385 %}
5386
5387 ins_pipe(pipe_slow);
5388 %}
5389
5390 instruct compareAndSwapBAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5391 %{
5392 predicate((UseZabha && UseZacas) && needs_acquiring_load_reserved(n));
5393
5394 match(Set res (CompareAndSwapB mem (Binary oldval newval)));
5395
5396 ins_cost(2 * VOLATILE_REF_COST);
5397
5398 format %{
5399 "cmpxchg $mem, $oldval, $newval\t# (byte) if $mem == $oldval then $mem <-- $newval\n\t"
5400 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapBAcq"
5401 %}
5402
5403 ins_encode %{
5404 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5405 Assembler::aq /* acquire */, Assembler::rl /* release */, $res$$Register,
5406 true /* result as bool */);
5407 %}
5408
5409 ins_pipe(pipe_slow);
5410 %}
5411
5412 instruct compareAndSwapSAcq_narrow(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5413 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5414 %{
5415 predicate((!UseZabha || !UseZacas) && needs_acquiring_load_reserved(n));
5416
5417 match(Set res (CompareAndSwapS mem (Binary oldval newval)));
5418
5419 ins_cost(2 * VOLATILE_REF_COST);
5420
5421 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5422
5423 format %{
5424 "cmpxchg_acq $mem, $oldval, $newval\t# (short) if $mem == $oldval then $mem <-- $newval\n\t"
5425 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapSAcq_narrow"
5426 %}
5427
5428 ins_encode %{
5429 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5430 Assembler::aq /* acquire */, Assembler::rl /* release */, $res$$Register,
5431 true /* result as bool */, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5432 %}
5433
5434 ins_pipe(pipe_slow);
5435 %}
5436
5437 instruct compareAndSwapSAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5438 %{
5439 predicate((UseZabha && UseZacas) && needs_acquiring_load_reserved(n));
5440
5441 match(Set res (CompareAndSwapS mem (Binary oldval newval)));
5442
5443 ins_cost(2 * VOLATILE_REF_COST);
5444
5445 format %{
5446 "cmpxchg $mem, $oldval, $newval\t# (short) if $mem == $oldval then $mem <-- $newval\n\t"
5447 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapSAcq"
5448 %}
5449
5450 ins_encode %{
5451 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5452 Assembler::aq /* acquire */, Assembler::rl /* release */, $res$$Register,
5453 true /* result as bool */);
5454 %}
5455
5456 ins_pipe(pipe_slow);
5457 %}
5458
5459 instruct compareAndSwapIAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5460 %{
5461 predicate(needs_acquiring_load_reserved(n));
5462
5463 match(Set res (CompareAndSwapI mem (Binary oldval newval)));
5464
5465 ins_cost(2 * VOLATILE_REF_COST);
5466
5467 format %{
5468 "cmpxchg_acq $mem, $oldval, $newval\t# (int) if $mem == $oldval then $mem <-- $newval\n\t"
5469 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapIAcq"
5470 %}
5471
5472 ins_encode %{
5473 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
5474 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
5475 /*result as bool*/ true);
5476 %}
5477
5478 ins_pipe(pipe_slow);
5479 %}
5480
5481 instruct compareAndSwapLAcq(iRegINoSp res, indirect mem, iRegL oldval, iRegL newval)
5482 %{
5483 predicate(needs_acquiring_load_reserved(n));
5484
5485 match(Set res (CompareAndSwapL mem (Binary oldval newval)));
5486
5487 ins_cost(2 * VOLATILE_REF_COST);
5488
5489 format %{
5490 "cmpxchg_acq $mem, $oldval, $newval\t# (long) if $mem == $oldval then $mem <-- $newval\n\t"
5491 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapLAcq"
5492 %}
5493
5494 ins_encode %{
5495 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5496 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
5497 /*result as bool*/ true);
5498 %}
5499
5500 ins_pipe(pipe_slow);
5501 %}
5502
5503 instruct compareAndSwapPAcq(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval)
5504 %{
5505 predicate(needs_acquiring_load_reserved(n) && (n->as_LoadStore()->barrier_data() == 0));
5506
5507 match(Set res (CompareAndSwapP mem (Binary oldval newval)));
5508
5509 ins_cost(2 * VOLATILE_REF_COST);
5510
5511 format %{
5512 "cmpxchg_acq $mem, $oldval, $newval\t# (ptr) if $mem == $oldval then $mem <-- $newval\n\t"
5513 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapPAcq"
5514 %}
5515
5516 ins_encode %{
5517 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5518 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
5519 /*result as bool*/ true);
5520 %}
5521
5522 ins_pipe(pipe_slow);
5523 %}
5524
5525 instruct compareAndSwapNAcq(iRegINoSp res, indirect mem, iRegN oldval, iRegN newval)
5526 %{
5527 predicate(needs_acquiring_load_reserved(n) && n->as_LoadStore()->barrier_data() == 0);
5528
5529 match(Set res (CompareAndSwapN mem (Binary oldval newval)));
5530
5531 ins_cost(2 * VOLATILE_REF_COST);
5532
5533 format %{
5534 "cmpxchg_acq $mem, $oldval, $newval\t# (narrow oop) if $mem == $oldval then $mem <-- $newval\n\t"
5535 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapNAcq"
5536 %}
5537
5538 ins_encode %{
5539 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
5540 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
5541 /*result as bool*/ true);
5542 %}
5543
5544 ins_pipe(pipe_slow);
5545 %}
5546
5547 // Sundry CAS operations. Note that release is always true,
5548 // regardless of the memory ordering of the CAS. This is because we
5549 // need the volatile case to be sequentially consistent but there is
5550 // no trailing StoreLoad barrier emitted by C2. Unfortunately we
5551 // can't check the type of memory ordering here, so we always emit a
5552 // sc_d(w) with rl bit set.
5553 instruct compareAndExchangeB_narrow(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5554 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5555 %{
5556 predicate(!UseZabha || !UseZacas);
5557
5558 match(Set res (CompareAndExchangeB mem (Binary oldval newval)));
5559
5560 ins_cost(2 * VOLATILE_REF_COST);
5561
5562 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5563
5564 format %{
5565 "cmpxchg $res = $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeB_narrow"
5566 %}
5567
5568 ins_encode %{
5569 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5570 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
5571 /*result_as_bool*/ false, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5572 %}
5573
5574 ins_pipe(pipe_slow);
5575 %}
5576
5577 instruct compareAndExchangeB(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5578 %{
5579 predicate(UseZabha && UseZacas);
5580
5581 match(Set res (CompareAndExchangeB mem (Binary oldval newval)));
5582
5583 ins_cost(2 * VOLATILE_REF_COST);
5584
5585 format %{
5586 "cmpxchg $res = $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeB"
5587 %}
5588
5589 ins_encode %{
5590 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5591 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5592 %}
5593
5594 ins_pipe(pipe_slow);
5595 %}
5596
5597 instruct compareAndExchangeS_narrow(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5598 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5599 %{
5600 predicate(!UseZabha || !UseZacas);
5601
5602 match(Set res (CompareAndExchangeS mem (Binary oldval newval)));
5603
5604 ins_cost(2 * VOLATILE_REF_COST);
5605
5606 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5607
5608 format %{
5609 "cmpxchg $res = $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeS_narrow"
5610 %}
5611
5612 ins_encode %{
5613 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5614 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
5615 /*result_as_bool*/ false, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5616 %}
5617
5618 ins_pipe(pipe_slow);
5619 %}
5620
5621 instruct compareAndExchangeS(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5622 %{
5623 predicate(UseZabha && UseZacas);
5624
5625 match(Set res (CompareAndExchangeS mem (Binary oldval newval)));
5626
5627 ins_cost(2 * VOLATILE_REF_COST);
5628
5629 format %{
5630 "cmpxchg $res = $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeS"
5631 %}
5632
5633 ins_encode %{
5634 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5635 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5636 %}
5637
5638 ins_pipe(pipe_slow);
5639 %}
5640
5641 instruct compareAndExchangeI(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5642 %{
5643 match(Set res (CompareAndExchangeI mem (Binary oldval newval)));
5644
5645 ins_cost(2 * VOLATILE_REF_COST);
5646
5647 format %{
5648 "cmpxchg $res = $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeI"
5649 %}
5650
5651 ins_encode %{
5652 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
5653 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5654 %}
5655
5656 ins_pipe(pipe_slow);
5657 %}
5658
5659 instruct compareAndExchangeL(iRegLNoSp res, indirect mem, iRegL oldval, iRegL newval)
5660 %{
5661 match(Set res (CompareAndExchangeL mem (Binary oldval newval)));
5662
5663 ins_cost(2 * VOLATILE_REF_COST);
5664
5665 format %{
5666 "cmpxchg $res = $mem, $oldval, $newval\t# (long, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeL"
5667 %}
5668
5669 ins_encode %{
5670 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5671 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5672 %}
5673
5674 ins_pipe(pipe_slow);
5675 %}
5676
5677 instruct compareAndExchangeN(iRegNNoSp res, indirect mem, iRegN oldval, iRegN newval)
5678 %{
5679 predicate(n->as_LoadStore()->barrier_data() == 0);
5680
5681 match(Set res (CompareAndExchangeN mem (Binary oldval newval)));
5682
5683 ins_cost(2 * VOLATILE_REF_COST);
5684
5685 format %{
5686 "cmpxchg $res = $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeN"
5687 %}
5688
5689 ins_encode %{
5690 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
5691 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5692 %}
5693
5694 ins_pipe(pipe_slow);
5695 %}
5696
5697 instruct compareAndExchangeP(iRegPNoSp res, indirect mem, iRegP oldval, iRegP newval)
5698 %{
5699 predicate(n->as_LoadStore()->barrier_data() == 0);
5700
5701 match(Set res (CompareAndExchangeP mem (Binary oldval newval)));
5702
5703 ins_cost(2 * VOLATILE_REF_COST);
5704
5705 format %{
5706 "cmpxchg $res = $mem, $oldval, $newval\t# (ptr, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeP"
5707 %}
5708
5709 ins_encode %{
5710 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5711 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5712 %}
5713
5714 ins_pipe(pipe_slow);
5715 %}
5716
5717 instruct compareAndExchangeBAcq_narrow(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5718 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5719 %{
5720 predicate((!UseZabha || !UseZacas) && needs_acquiring_load_reserved(n));
5721
5722 match(Set res (CompareAndExchangeB mem (Binary oldval newval)));
5723
5724 ins_cost(2 * VOLATILE_REF_COST);
5725
5726 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5727
5728 format %{
5729 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeBAcq_narrow"
5730 %}
5731
5732 ins_encode %{
5733 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5734 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
5735 /*result_as_bool*/ false, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5736 %}
5737
5738 ins_pipe(pipe_slow);
5739 %}
5740
5741 instruct compareAndExchangeBAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5742 %{
5743 predicate((UseZabha && UseZacas) && needs_acquiring_load_reserved(n));
5744
5745 match(Set res (CompareAndExchangeB mem (Binary oldval newval)));
5746
5747 ins_cost(2 * VOLATILE_REF_COST);
5748
5749 format %{
5750 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeBAcq"
5751 %}
5752
5753 ins_encode %{
5754 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5755 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
5756 %}
5757
5758 ins_pipe(pipe_slow);
5759 %}
5760
5761 instruct compareAndExchangeSAcq_narrow(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5762 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5763 %{
5764 predicate((!UseZabha || !UseZacas) && needs_acquiring_load_reserved(n));
5765
5766 match(Set res (CompareAndExchangeS mem (Binary oldval newval)));
5767
5768 ins_cost(2 * VOLATILE_REF_COST);
5769
5770 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5771
5772 format %{
5773 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeSAcq_narrow"
5774 %}
5775
5776 ins_encode %{
5777 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5778 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
5779 /*result_as_bool*/ false, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5780 %}
5781
5782 ins_pipe(pipe_slow);
5783 %}
5784
5785 instruct compareAndExchangeSAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5786 %{
5787 predicate((UseZabha && UseZacas) && needs_acquiring_load_reserved(n));
5788
5789 match(Set res (CompareAndExchangeS mem (Binary oldval newval)));
5790
5791 ins_cost(2 * VOLATILE_REF_COST);
5792
5793 format %{
5794 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeSAcq"
5795 %}
5796
5797 ins_encode %{
5798 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5799 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
5800 %}
5801
5802 ins_pipe(pipe_slow);
5803 %}
5804
5805 instruct compareAndExchangeIAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5806 %{
5807 predicate(needs_acquiring_load_reserved(n));
5808
5809 match(Set res (CompareAndExchangeI mem (Binary oldval newval)));
5810
5811 ins_cost(2 * VOLATILE_REF_COST);
5812
5813 format %{
5814 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeIAcq"
5815 %}
5816
5817 ins_encode %{
5818 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
5819 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
5820 %}
5821
5822 ins_pipe(pipe_slow);
5823 %}
5824
5825 instruct compareAndExchangeLAcq(iRegLNoSp res, indirect mem, iRegL oldval, iRegL newval)
5826 %{
5827 predicate(needs_acquiring_load_reserved(n));
5828
5829 match(Set res (CompareAndExchangeL mem (Binary oldval newval)));
5830
5831 ins_cost(2 * VOLATILE_REF_COST);
5832
5833 format %{
5834 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (long, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeLAcq"
5835 %}
5836
5837 ins_encode %{
5838 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5839 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
5840 %}
5841
5842 ins_pipe(pipe_slow);
5843 %}
5844
5845 instruct compareAndExchangeNAcq(iRegNNoSp res, indirect mem, iRegN oldval, iRegN newval)
5846 %{
5847 predicate(needs_acquiring_load_reserved(n) && n->as_LoadStore()->barrier_data() == 0);
5848
5849 match(Set res (CompareAndExchangeN mem (Binary oldval newval)));
5850
5851 ins_cost(2 * VOLATILE_REF_COST);
5852
5853 format %{
5854 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeNAcq"
5855 %}
5856
5857 ins_encode %{
5858 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
5859 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
5860 %}
5861
5862 ins_pipe(pipe_slow);
5863 %}
5864
5865 instruct compareAndExchangePAcq(iRegPNoSp res, indirect mem, iRegP oldval, iRegP newval)
5866 %{
5867 predicate(needs_acquiring_load_reserved(n) && (n->as_LoadStore()->barrier_data() == 0));
5868
5869 match(Set res (CompareAndExchangeP mem (Binary oldval newval)));
5870
5871 ins_cost(2 * VOLATILE_REF_COST);
5872
5873 format %{
5874 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (ptr, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangePAcq"
5875 %}
5876
5877 ins_encode %{
5878 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5879 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
5880 %}
5881
5882 ins_pipe(pipe_slow);
5883 %}
5884
5885 instruct weakCompareAndSwapB_narrow(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5886 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5887 %{
5888 predicate(!UseZabha || !UseZacas);
5889
5890 match(Set res (WeakCompareAndSwapB mem (Binary oldval newval)));
5891
5892 ins_cost(2 * VOLATILE_REF_COST);
5893
5894 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5895
5896 format %{
5897 "weak_cmpxchg $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5898 "# $res == 1 when success, #@weakCompareAndSwapB_narrow"
5899 %}
5900
5901 ins_encode %{
5902 __ weak_cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5903 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
5904 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5905 %}
5906
5907 ins_pipe(pipe_slow);
5908 %}
5909
5910 instruct weakCompareAndSwapB(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5911 %{
5912 predicate(UseZabha && UseZacas);
5913
5914 match(Set res (WeakCompareAndSwapB mem (Binary oldval newval)));
5915
5916 ins_cost(2 * VOLATILE_REF_COST);
5917
5918 format %{
5919 "weak_cmpxchg $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5920 "# $res == 1 when success, #@weakCompareAndSwapB"
5921 %}
5922
5923 ins_encode %{
5924 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5925 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5926 %}
5927
5928 ins_pipe(pipe_slow);
5929 %}
5930
5931 instruct weakCompareAndSwapS_narrow(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5932 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5933 %{
5934 predicate(!UseZabha || !UseZacas);
5935
5936 match(Set res (WeakCompareAndSwapS mem (Binary oldval newval)));
5937
5938 ins_cost(2 * VOLATILE_REF_COST);
5939
5940 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5941
5942 format %{
5943 "weak_cmpxchg $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5944 "# $res == 1 when success, #@weakCompareAndSwapS_narrow"
5945 %}
5946
5947 ins_encode %{
5948 __ weak_cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5949 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
5950 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5951 %}
5952
5953 ins_pipe(pipe_slow);
5954 %}
5955
5956 instruct weakCompareAndSwapS(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5957 %{
5958 predicate(UseZabha && UseZacas);
5959
5960 match(Set res (WeakCompareAndSwapS mem (Binary oldval newval)));
5961
5962 ins_cost(2 * VOLATILE_REF_COST);
5963
5964 format %{
5965 "weak_cmpxchg $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5966 "# $res == 1 when success, #@weakCompareAndSwapS"
5967 %}
5968
5969 ins_encode %{
5970 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5971 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5972 %}
5973
5974 ins_pipe(pipe_slow);
5975 %}
5976
5977 instruct weakCompareAndSwapI(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5978 %{
5979 match(Set res (WeakCompareAndSwapI mem (Binary oldval newval)));
5980
5981 ins_cost(2 * VOLATILE_REF_COST);
5982
5983 format %{
5984 "weak_cmpxchg $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5985 "# $res == 1 when success, #@weakCompareAndSwapI"
5986 %}
5987
5988 ins_encode %{
5989 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
5990 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5991 %}
5992
5993 ins_pipe(pipe_slow);
5994 %}
5995
5996 instruct weakCompareAndSwapL(iRegINoSp res, indirect mem, iRegL oldval, iRegL newval)
5997 %{
5998 match(Set res (WeakCompareAndSwapL mem (Binary oldval newval)));
5999
6000 ins_cost(2 * VOLATILE_REF_COST);
6001
6002 format %{
6003 "weak_cmpxchg $mem, $oldval, $newval\t# (long, weak) if $mem == $oldval then $mem <-- $newval\n\t"
6004 "# $res == 1 when success, #@weakCompareAndSwapL"
6005 %}
6006
6007 ins_encode %{
6008 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
6009 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
6010 %}
6011
6012 ins_pipe(pipe_slow);
6013 %}
6014
6015 instruct weakCompareAndSwapN(iRegINoSp res, indirect mem, iRegN oldval, iRegN newval)
6016 %{
6017 predicate(n->as_LoadStore()->barrier_data() == 0);
6018
6019 match(Set res (WeakCompareAndSwapN mem (Binary oldval newval)));
6020
6021 ins_cost(2 * VOLATILE_REF_COST);
6022
6023 format %{
6024 "weak_cmpxchg $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval\n\t"
6025 "# $res == 1 when success, #@weakCompareAndSwapN"
6026 %}
6027
6028 ins_encode %{
6029 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
6030 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
6031 %}
6032
6033 ins_pipe(pipe_slow);
6034 %}
6035
6036 instruct weakCompareAndSwapP(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval)
6037 %{
6038 predicate(n->as_LoadStore()->barrier_data() == 0);
6039
6040 match(Set res (WeakCompareAndSwapP mem (Binary oldval newval)));
6041
6042 ins_cost(2 * VOLATILE_REF_COST);
6043
6044 format %{
6045 "weak_cmpxchg $mem, $oldval, $newval\t# (ptr, weak) if $mem == $oldval then $mem <-- $newval\n\t"
6046 "# $res == 1 when success, #@weakCompareAndSwapP"
6047 %}
6048
6049 ins_encode %{
6050 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
6051 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
6052 %}
6053
6054 ins_pipe(pipe_slow);
6055 %}
6056
6057 instruct weakCompareAndSwapBAcq_narrow(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
6058 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
6059 %{
6060 predicate((!UseZabha || !UseZacas) && needs_acquiring_load_reserved(n));
6061
6062 match(Set res (WeakCompareAndSwapB mem (Binary oldval newval)));
6063
6064 ins_cost(2 * VOLATILE_REF_COST);
6065
6066 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
6067
6068 format %{
6069 "weak_cmpxchg_acq $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval\n\t"
6070 "# $res == 1 when success, #@weakCompareAndSwapBAcq_narrow"
6071 %}
6072
6073 ins_encode %{
6074 __ weak_cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
6075 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
6076 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
6077 %}
6078
6079 ins_pipe(pipe_slow);
6080 %}
6081
6082 instruct weakCompareAndSwapBAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
6083 %{
6084 predicate((UseZabha && UseZacas) && needs_acquiring_load_reserved(n));
6085
6086 match(Set res (WeakCompareAndSwapB mem (Binary oldval newval)));
6087
6088 ins_cost(2 * VOLATILE_REF_COST);
6089
6090 format %{
6091 "weak_cmpxchg_acq $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval\n\t"
6092 "# $res == 1 when success, #@weakCompareAndSwapBAcq"
6093 %}
6094
6095 ins_encode %{
6096 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
6097 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
6098 %}
6099
6100 ins_pipe(pipe_slow);
6101 %}
6102
6103 instruct weakCompareAndSwapSAcq_narrow(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
6104 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
6105 %{
6106 predicate((!UseZabha || !UseZacas) && needs_acquiring_load_reserved(n));
6107
6108 match(Set res (WeakCompareAndSwapS mem (Binary oldval newval)));
6109
6110 ins_cost(2 * VOLATILE_REF_COST);
6111
6112 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
6113
6114 format %{
6115 "weak_cmpxchg_acq $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval\n\t"
6116 "# $res == 1 when success, #@weakCompareAndSwapSAcq_narrow"
6117 %}
6118
6119 ins_encode %{
6120 __ weak_cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
6121 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
6122 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
6123 %}
6124
6125 ins_pipe(pipe_slow);
6126 %}
6127
6128 instruct weakCompareAndSwapSAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
6129 %{
6130 predicate((UseZabha && UseZacas) && needs_acquiring_load_reserved(n));
6131
6132 match(Set res (WeakCompareAndSwapS mem (Binary oldval newval)));
6133
6134 ins_cost(2 * VOLATILE_REF_COST);
6135
6136 format %{
6137 "weak_cmpxchg_acq $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval\n\t"
6138 "# $res == 1 when success, #@weakCompareAndSwapSAcq"
6139 %}
6140
6141 ins_encode %{
6142 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
6143 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
6144 %}
6145
6146 ins_pipe(pipe_slow);
6147 %}
6148
6149 instruct weakCompareAndSwapIAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
6150 %{
6151 predicate(needs_acquiring_load_reserved(n));
6152
6153 match(Set res (WeakCompareAndSwapI mem (Binary oldval newval)));
6154
6155 ins_cost(2 * VOLATILE_REF_COST);
6156
6157 format %{
6158 "weak_cmpxchg_acq $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval\n\t"
6159 "# $res == 1 when success, #@weakCompareAndSwapIAcq"
6160 %}
6161
6162 ins_encode %{
6163 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
6164 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
6165 %}
6166
6167 ins_pipe(pipe_slow);
6168 %}
6169
6170 instruct weakCompareAndSwapLAcq(iRegINoSp res, indirect mem, iRegL oldval, iRegL newval)
6171 %{
6172 predicate(needs_acquiring_load_reserved(n));
6173
6174 match(Set res (WeakCompareAndSwapL mem (Binary oldval newval)));
6175
6176 ins_cost(2 * VOLATILE_REF_COST);
6177
6178 format %{
6179 "weak_cmpxchg_acq $mem, $oldval, $newval\t# (long, weak) if $mem == $oldval then $mem <-- $newval\n\t"
6180 "# $res == 1 when success, #@weakCompareAndSwapLAcq"
6181 %}
6182
6183 ins_encode %{
6184 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
6185 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
6186 %}
6187
6188 ins_pipe(pipe_slow);
6189 %}
6190
6191 instruct weakCompareAndSwapNAcq(iRegINoSp res, indirect mem, iRegN oldval, iRegN newval)
6192 %{
6193 predicate(needs_acquiring_load_reserved(n) && n->as_LoadStore()->barrier_data() == 0);
6194
6195 match(Set res (WeakCompareAndSwapN mem (Binary oldval newval)));
6196
6197 ins_cost(2 * VOLATILE_REF_COST);
6198
6199 format %{
6200 "weak_cmpxchg_acq $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval\n\t"
6201 "# $res == 1 when success, #@weakCompareAndSwapNAcq"
6202 %}
6203
6204 ins_encode %{
6205 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
6206 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
6207 %}
6208
6209 ins_pipe(pipe_slow);
6210 %}
6211
6212 instruct weakCompareAndSwapPAcq(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval)
6213 %{
6214 predicate(needs_acquiring_load_reserved(n) && (n->as_LoadStore()->barrier_data() == 0));
6215
6216 match(Set res (WeakCompareAndSwapP mem (Binary oldval newval)));
6217
6218 ins_cost(2 * VOLATILE_REF_COST);
6219
6220 format %{
6221 "weak_cmpxchg_acq $mem, $oldval, $newval\t# (ptr, weak) if $mem == $oldval then $mem <-- $newval\n\t"
6222 "\t# $res == 1 when success, #@weakCompareAndSwapPAcq"
6223 %}
6224
6225 ins_encode %{
6226 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
6227 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
6228 %}
6229
6230 ins_pipe(pipe_slow);
6231 %}
6232
6233 instruct get_and_setI(indirect mem, iRegI newv, iRegINoSp prev)
6234 %{
6235 match(Set prev (GetAndSetI mem newv));
6236
6237 ins_cost(ALU_COST);
6238
6239 format %{ "atomic_xchgw $prev, $newv, [$mem]\t#@get_and_setI" %}
6240
6241 ins_encode %{
6242 __ atomic_xchgw($prev$$Register, $newv$$Register, as_Register($mem$$base));
6243 %}
6244
6245 ins_pipe(pipe_serial);
6246 %}
6247
6248 instruct get_and_setL(indirect mem, iRegL newv, iRegLNoSp prev)
6249 %{
6250 match(Set prev (GetAndSetL mem newv));
6251
6252 ins_cost(ALU_COST);
6253
6254 format %{ "atomic_xchg $prev, $newv, [$mem]\t#@get_and_setL" %}
6255
6256 ins_encode %{
6257 __ atomic_xchg($prev$$Register, $newv$$Register, as_Register($mem$$base));
6258 %}
6259
6260 ins_pipe(pipe_serial);
6261 %}
6262
6263 instruct get_and_setN(indirect mem, iRegN newv, iRegINoSp prev)
6264 %{
6265 predicate(n->as_LoadStore()->barrier_data() == 0);
6266
6267 match(Set prev (GetAndSetN mem newv));
6268
6269 ins_cost(ALU_COST);
6270
6271 format %{ "atomic_xchgwu $prev, $newv, [$mem]\t#@get_and_setN" %}
6272
6273 ins_encode %{
6274 __ atomic_xchgwu($prev$$Register, $newv$$Register, as_Register($mem$$base));
6275 %}
6276
6277 ins_pipe(pipe_serial);
6278 %}
6279
6280 instruct get_and_setP(indirect mem, iRegP newv, iRegPNoSp prev)
6281 %{
6282 predicate(n->as_LoadStore()->barrier_data() == 0);
6283 match(Set prev (GetAndSetP mem newv));
6284
6285 ins_cost(ALU_COST);
6286
6287 format %{ "atomic_xchg $prev, $newv, [$mem]\t#@get_and_setP" %}
6288
6289 ins_encode %{
6290 __ atomic_xchg($prev$$Register, $newv$$Register, as_Register($mem$$base));
6291 %}
6292
6293 ins_pipe(pipe_serial);
6294 %}
6295
6296 instruct get_and_setIAcq(indirect mem, iRegI newv, iRegINoSp prev)
6297 %{
6298 predicate(needs_acquiring_load_reserved(n));
6299
6300 match(Set prev (GetAndSetI mem newv));
6301
6302 ins_cost(ALU_COST);
6303
6304 format %{ "atomic_xchgw_acq $prev, $newv, [$mem]\t#@get_and_setIAcq" %}
6305
6306 ins_encode %{
6307 __ atomic_xchgalw($prev$$Register, $newv$$Register, as_Register($mem$$base));
6308 %}
6309
6310 ins_pipe(pipe_serial);
6311 %}
6312
6313 instruct get_and_setLAcq(indirect mem, iRegL newv, iRegLNoSp prev)
6314 %{
6315 predicate(needs_acquiring_load_reserved(n));
6316
6317 match(Set prev (GetAndSetL mem newv));
6318
6319 ins_cost(ALU_COST);
6320
6321 format %{ "atomic_xchg_acq $prev, $newv, [$mem]\t#@get_and_setLAcq" %}
6322
6323 ins_encode %{
6324 __ atomic_xchgal($prev$$Register, $newv$$Register, as_Register($mem$$base));
6325 %}
6326
6327 ins_pipe(pipe_serial);
6328 %}
6329
6330 instruct get_and_setNAcq(indirect mem, iRegN newv, iRegINoSp prev)
6331 %{
6332 predicate(needs_acquiring_load_reserved(n) && n->as_LoadStore()->barrier_data() == 0);
6333
6334 match(Set prev (GetAndSetN mem newv));
6335
6336 ins_cost(ALU_COST);
6337
6338 format %{ "atomic_xchgwu_acq $prev, $newv, [$mem]\t#@get_and_setNAcq" %}
6339
6340 ins_encode %{
6341 __ atomic_xchgalwu($prev$$Register, $newv$$Register, as_Register($mem$$base));
6342 %}
6343
6344 ins_pipe(pipe_serial);
6345 %}
6346
6347 instruct get_and_setPAcq(indirect mem, iRegP newv, iRegPNoSp prev)
6348 %{
6349 predicate(needs_acquiring_load_reserved(n) && (n->as_LoadStore()->barrier_data() == 0));
6350
6351 match(Set prev (GetAndSetP mem newv));
6352
6353 ins_cost(ALU_COST);
6354
6355 format %{ "atomic_xchg_acq $prev, $newv, [$mem]\t#@get_and_setPAcq" %}
6356
6357 ins_encode %{
6358 __ atomic_xchgal($prev$$Register, $newv$$Register, as_Register($mem$$base));
6359 %}
6360
6361 ins_pipe(pipe_serial);
6362 %}
6363
6364 instruct get_and_addL(indirect mem, iRegLNoSp newval, iRegL incr)
6365 %{
6366 match(Set newval (GetAndAddL mem incr));
6367
6368 ins_cost(ALU_COST);
6369
6370 format %{ "get_and_addL $newval, [$mem], $incr\t#@get_and_addL" %}
6371
6372 ins_encode %{
6373 __ atomic_add($newval$$Register, $incr$$Register, as_Register($mem$$base));
6374 %}
6375
6376 ins_pipe(pipe_serial);
6377 %}
6378
6379 instruct get_and_addL_no_res(indirect mem, Universe dummy, iRegL incr)
6380 %{
6381 predicate(n->as_LoadStore()->result_not_used());
6382
6383 match(Set dummy (GetAndAddL mem incr));
6384
6385 ins_cost(ALU_COST);
6386
6387 format %{ "get_and_addL [$mem], $incr\t#@get_and_addL_no_res" %}
6388
6389 ins_encode %{
6390 __ atomic_add(noreg, $incr$$Register, as_Register($mem$$base));
6391 %}
6392
6393 ins_pipe(pipe_serial);
6394 %}
6395
6396 instruct get_and_addLi(indirect mem, iRegLNoSp newval, immLAdd incr)
6397 %{
6398 match(Set newval (GetAndAddL mem incr));
6399
6400 ins_cost(ALU_COST);
6401
6402 format %{ "get_and_addL $newval, [$mem], $incr\t#@get_and_addLi" %}
6403
6404 ins_encode %{
6405 __ atomic_add($newval$$Register, $incr$$constant, as_Register($mem$$base));
6406 %}
6407
6408 ins_pipe(pipe_serial);
6409 %}
6410
6411 instruct get_and_addLi_no_res(indirect mem, Universe dummy, immLAdd incr)
6412 %{
6413 predicate(n->as_LoadStore()->result_not_used());
6414
6415 match(Set dummy (GetAndAddL mem incr));
6416
6417 ins_cost(ALU_COST);
6418
6419 format %{ "get_and_addL [$mem], $incr\t#@get_and_addLi_no_res" %}
6420
6421 ins_encode %{
6422 __ atomic_add(noreg, $incr$$constant, as_Register($mem$$base));
6423 %}
6424
6425 ins_pipe(pipe_serial);
6426 %}
6427
6428 instruct get_and_addI(indirect mem, iRegINoSp newval, iRegIorL2I incr)
6429 %{
6430 match(Set newval (GetAndAddI mem incr));
6431
6432 ins_cost(ALU_COST);
6433
6434 format %{ "get_and_addI $newval, [$mem], $incr\t#@get_and_addI" %}
6435
6436 ins_encode %{
6437 __ atomic_addw($newval$$Register, $incr$$Register, as_Register($mem$$base));
6438 %}
6439
6440 ins_pipe(pipe_serial);
6441 %}
6442
6443 instruct get_and_addI_no_res(indirect mem, Universe dummy, iRegIorL2I incr)
6444 %{
6445 predicate(n->as_LoadStore()->result_not_used());
6446
6447 match(Set dummy (GetAndAddI mem incr));
6448
6449 ins_cost(ALU_COST);
6450
6451 format %{ "get_and_addI [$mem], $incr\t#@get_and_addI_no_res" %}
6452
6453 ins_encode %{
6454 __ atomic_addw(noreg, $incr$$Register, as_Register($mem$$base));
6455 %}
6456
6457 ins_pipe(pipe_serial);
6458 %}
6459
6460 instruct get_and_addIi(indirect mem, iRegINoSp newval, immIAdd incr)
6461 %{
6462 match(Set newval (GetAndAddI mem incr));
6463
6464 ins_cost(ALU_COST);
6465
6466 format %{ "get_and_addI $newval, [$mem], $incr\t#@get_and_addIi" %}
6467
6468 ins_encode %{
6469 __ atomic_addw($newval$$Register, $incr$$constant, as_Register($mem$$base));
6470 %}
6471
6472 ins_pipe(pipe_serial);
6473 %}
6474
6475 instruct get_and_addIi_no_res(indirect mem, Universe dummy, immIAdd incr)
6476 %{
6477 predicate(n->as_LoadStore()->result_not_used());
6478
6479 match(Set dummy (GetAndAddI mem incr));
6480
6481 ins_cost(ALU_COST);
6482
6483 format %{ "get_and_addI [$mem], $incr\t#@get_and_addIi_no_res" %}
6484
6485 ins_encode %{
6486 __ atomic_addw(noreg, $incr$$constant, as_Register($mem$$base));
6487 %}
6488
6489 ins_pipe(pipe_serial);
6490 %}
6491
6492 instruct get_and_addLAcq(indirect mem, iRegLNoSp newval, iRegL incr)
6493 %{
6494 predicate(needs_acquiring_load_reserved(n));
6495
6496 match(Set newval (GetAndAddL mem incr));
6497
6498 ins_cost(ALU_COST);
6499
6500 format %{ "get_and_addL_acq $newval, [$mem], $incr\t#@get_and_addLAcq" %}
6501
6502 ins_encode %{
6503 __ atomic_addal($newval$$Register, $incr$$Register, as_Register($mem$$base));
6504 %}
6505
6506 ins_pipe(pipe_serial);
6507 %}
6508
6509 instruct get_and_addL_no_resAcq(indirect mem, Universe dummy, iRegL incr) %{
6510 predicate(n->as_LoadStore()->result_not_used() && needs_acquiring_load_reserved(n));
6511
6512 match(Set dummy (GetAndAddL mem incr));
6513
6514 ins_cost(ALU_COST);
6515
6516 format %{ "get_and_addL_acq [$mem], $incr\t#@get_and_addL_no_resAcq" %}
6517
6518 ins_encode %{
6519 __ atomic_addal(noreg, $incr$$Register, as_Register($mem$$base));
6520 %}
6521
6522 ins_pipe(pipe_serial);
6523 %}
6524
6525 instruct get_and_addLiAcq(indirect mem, iRegLNoSp newval, immLAdd incr)
6526 %{
6527 predicate(needs_acquiring_load_reserved(n));
6528
6529 match(Set newval (GetAndAddL mem incr));
6530
6531 ins_cost(ALU_COST);
6532
6533 format %{ "get_and_addL_acq $newval, [$mem], $incr\t#@get_and_addLiAcq" %}
6534
6535 ins_encode %{
6536 __ atomic_addal($newval$$Register, $incr$$constant, as_Register($mem$$base));
6537 %}
6538
6539 ins_pipe(pipe_serial);
6540 %}
6541
6542 instruct get_and_addLi_no_resAcq(indirect mem, Universe dummy, immLAdd incr)
6543 %{
6544 predicate(n->as_LoadStore()->result_not_used() && needs_acquiring_load_reserved(n));
6545
6546 match(Set dummy (GetAndAddL mem incr));
6547
6548 ins_cost(ALU_COST);
6549
6550 format %{ "get_and_addL_acq [$mem], $incr\t#@get_and_addLi_no_resAcq" %}
6551
6552 ins_encode %{
6553 __ atomic_addal(noreg, $incr$$constant, as_Register($mem$$base));
6554 %}
6555
6556 ins_pipe(pipe_serial);
6557 %}
6558
6559 instruct get_and_addIAcq(indirect mem, iRegINoSp newval, iRegIorL2I incr)
6560 %{
6561 predicate(needs_acquiring_load_reserved(n));
6562
6563 match(Set newval (GetAndAddI mem incr));
6564
6565 ins_cost(ALU_COST);
6566
6567 format %{ "get_and_addI_acq $newval, [$mem], $incr\t#@get_and_addIAcq" %}
6568
6569 ins_encode %{
6570 __ atomic_addalw($newval$$Register, $incr$$Register, as_Register($mem$$base));
6571 %}
6572
6573 ins_pipe(pipe_serial);
6574 %}
6575
6576 instruct get_and_addI_no_resAcq(indirect mem, Universe dummy, iRegIorL2I incr)
6577 %{
6578 predicate(n->as_LoadStore()->result_not_used() && needs_acquiring_load_reserved(n));
6579
6580 match(Set dummy (GetAndAddI mem incr));
6581
6582 ins_cost(ALU_COST);
6583
6584 format %{ "get_and_addI_acq [$mem], $incr\t#@get_and_addI_no_resAcq" %}
6585
6586 ins_encode %{
6587 __ atomic_addalw(noreg, $incr$$Register, as_Register($mem$$base));
6588 %}
6589
6590 ins_pipe(pipe_serial);
6591 %}
6592
6593 instruct get_and_addIiAcq(indirect mem, iRegINoSp newval, immIAdd incr)
6594 %{
6595 predicate(needs_acquiring_load_reserved(n));
6596
6597 match(Set newval (GetAndAddI mem incr));
6598
6599 ins_cost(ALU_COST);
6600
6601 format %{ "get_and_addI_acq $newval, [$mem], $incr\t#@get_and_addIiAcq" %}
6602
6603 ins_encode %{
6604 __ atomic_addalw($newval$$Register, $incr$$constant, as_Register($mem$$base));
6605 %}
6606
6607 ins_pipe(pipe_serial);
6608 %}
6609
6610 instruct get_and_addIi_no_resAcq(indirect mem, Universe dummy, immIAdd incr)
6611 %{
6612 predicate(n->as_LoadStore()->result_not_used() && needs_acquiring_load_reserved(n));
6613
6614 match(Set dummy (GetAndAddI mem incr));
6615
6616 ins_cost(ALU_COST);
6617
6618 format %{ "get_and_addI_acq [$mem], $incr\t#@get_and_addIi_no_resAcq" %}
6619
6620 ins_encode %{
6621 __ atomic_addalw(noreg, $incr$$constant, as_Register($mem$$base));
6622 %}
6623
6624 ins_pipe(pipe_serial);
6625 %}
6626
6627 // ============================================================================
6628 // Arithmetic Instructions
6629 //
6630
6631 // Integer Addition
6632
6633 // TODO
6634 // these currently employ operations which do not set CR and hence are
6635 // not flagged as killing CR but we would like to isolate the cases
6636 // where we want to set flags from those where we don't. need to work
6637 // out how to do that.
6638 instruct addI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6639 match(Set dst (AddI src1 src2));
6640
6641 ins_cost(ALU_COST);
6642 format %{ "addw $dst, $src1, $src2\t#@addI_reg_reg" %}
6643
6644 ins_encode %{
6645 __ addw(as_Register($dst$$reg),
6646 as_Register($src1$$reg),
6647 as_Register($src2$$reg));
6648 %}
6649
6650 ins_pipe(ialu_reg_reg);
6651 %}
6652
6653 instruct addI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immIAdd src2) %{
6654 match(Set dst (AddI src1 src2));
6655
6656 ins_cost(ALU_COST);
6657 format %{ "addiw $dst, $src1, $src2\t#@addI_reg_imm" %}
6658
6659 ins_encode %{
6660 __ addiw(as_Register($dst$$reg),
6661 as_Register($src1$$reg),
6662 $src2$$constant);
6663 %}
6664
6665 ins_pipe(ialu_reg_imm);
6666 %}
6667
6668 instruct addI_reg_imm_l2i(iRegINoSp dst, iRegL src1, immIAdd src2) %{
6669 match(Set dst (AddI (ConvL2I src1) src2));
6670
6671 ins_cost(ALU_COST);
6672 format %{ "addiw $dst, $src1, $src2\t#@addI_reg_imm_l2i" %}
6673
6674 ins_encode %{
6675 __ addiw(as_Register($dst$$reg),
6676 as_Register($src1$$reg),
6677 $src2$$constant);
6678 %}
6679
6680 ins_pipe(ialu_reg_imm);
6681 %}
6682
6683 // Pointer Addition
6684 instruct addP_reg_reg(iRegPNoSp dst, iRegP src1, iRegL src2) %{
6685 match(Set dst (AddP src1 src2));
6686
6687 ins_cost(ALU_COST);
6688 format %{ "add $dst, $src1, $src2\t# ptr, #@addP_reg_reg" %}
6689
6690 ins_encode %{
6691 __ add(as_Register($dst$$reg),
6692 as_Register($src1$$reg),
6693 as_Register($src2$$reg));
6694 %}
6695
6696 ins_pipe(ialu_reg_reg);
6697 %}
6698
6699 // If we shift more than 32 bits, we need not convert I2L.
6700 instruct lShiftL_regI_immGE32(iRegLNoSp dst, iRegI src, uimmI6_ge32 scale) %{
6701 match(Set dst (LShiftL (ConvI2L src) scale));
6702 ins_cost(ALU_COST);
6703 format %{ "slli $dst, $src, $scale & 63\t#@lShiftL_regI_immGE32" %}
6704
6705 ins_encode %{
6706 __ slli(as_Register($dst$$reg), as_Register($src$$reg), $scale$$constant & 63);
6707 %}
6708
6709 ins_pipe(ialu_reg_shift);
6710 %}
6711
6712 // Pointer Immediate Addition
6713 // n.b. this needs to be more expensive than using an indirect memory
6714 // operand
6715 instruct addP_reg_imm(iRegPNoSp dst, iRegP src1, immLAdd src2) %{
6716 match(Set dst (AddP src1 src2));
6717 ins_cost(ALU_COST);
6718 format %{ "addi $dst, $src1, $src2\t# ptr, #@addP_reg_imm" %}
6719
6720 ins_encode %{
6721 __ addi(as_Register($dst$$reg),
6722 as_Register($src1$$reg),
6723 $src2$$constant);
6724 %}
6725
6726 ins_pipe(ialu_reg_imm);
6727 %}
6728
6729 // Long Addition
6730 instruct addL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
6731 match(Set dst (AddL src1 src2));
6732 ins_cost(ALU_COST);
6733 format %{ "add $dst, $src1, $src2\t#@addL_reg_reg" %}
6734
6735 ins_encode %{
6736 __ add(as_Register($dst$$reg),
6737 as_Register($src1$$reg),
6738 as_Register($src2$$reg));
6739 %}
6740
6741 ins_pipe(ialu_reg_reg);
6742 %}
6743
6744 // No constant pool entries requiredLong Immediate Addition.
6745 instruct addL_reg_imm(iRegLNoSp dst, iRegL src1, immLAdd src2) %{
6746 match(Set dst (AddL src1 src2));
6747 ins_cost(ALU_COST);
6748 format %{ "addi $dst, $src1, $src2\t#@addL_reg_imm" %}
6749
6750 ins_encode %{
6751 // src2 is imm, so actually call the addi
6752 __ addi(as_Register($dst$$reg),
6753 as_Register($src1$$reg),
6754 $src2$$constant);
6755 %}
6756
6757 ins_pipe(ialu_reg_imm);
6758 %}
6759
6760 // Integer Subtraction
6761 instruct subI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6762 match(Set dst (SubI src1 src2));
6763
6764 ins_cost(ALU_COST);
6765 format %{ "subw $dst, $src1, $src2\t#@subI_reg_reg" %}
6766
6767 ins_encode %{
6768 __ subw(as_Register($dst$$reg),
6769 as_Register($src1$$reg),
6770 as_Register($src2$$reg));
6771 %}
6772
6773 ins_pipe(ialu_reg_reg);
6774 %}
6775
6776 // Immediate Subtraction
6777 instruct subI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immISub src2) %{
6778 match(Set dst (SubI src1 src2));
6779
6780 ins_cost(ALU_COST);
6781 format %{ "addiw $dst, $src1, -$src2\t#@subI_reg_imm" %}
6782
6783 ins_encode %{
6784 // src2 is imm, so actually call the addiw
6785 __ subiw(as_Register($dst$$reg),
6786 as_Register($src1$$reg),
6787 $src2$$constant);
6788 %}
6789
6790 ins_pipe(ialu_reg_imm);
6791 %}
6792
6793 // Long Subtraction
6794 instruct subL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
6795 match(Set dst (SubL src1 src2));
6796 ins_cost(ALU_COST);
6797 format %{ "sub $dst, $src1, $src2\t#@subL_reg_reg" %}
6798
6799 ins_encode %{
6800 __ sub(as_Register($dst$$reg),
6801 as_Register($src1$$reg),
6802 as_Register($src2$$reg));
6803 %}
6804
6805 ins_pipe(ialu_reg_reg);
6806 %}
6807
6808 // No constant pool entries requiredLong Immediate Subtraction.
6809 instruct subL_reg_imm(iRegLNoSp dst, iRegL src1, immLSub src2) %{
6810 match(Set dst (SubL src1 src2));
6811 ins_cost(ALU_COST);
6812 format %{ "addi $dst, $src1, -$src2\t#@subL_reg_imm" %}
6813
6814 ins_encode %{
6815 // src2 is imm, so actually call the addi
6816 __ subi(as_Register($dst$$reg),
6817 as_Register($src1$$reg),
6818 $src2$$constant);
6819 %}
6820
6821 ins_pipe(ialu_reg_imm);
6822 %}
6823
6824 // Integer Negation (special case for sub)
6825
6826 instruct negI_reg(iRegINoSp dst, iRegIorL2I src, immI0 zero) %{
6827 match(Set dst (SubI zero src));
6828 ins_cost(ALU_COST);
6829 format %{ "subw $dst, x0, $src\t# int, #@negI_reg" %}
6830
6831 ins_encode %{
6832 // actually call the subw
6833 __ negw(as_Register($dst$$reg),
6834 as_Register($src$$reg));
6835 %}
6836
6837 ins_pipe(ialu_reg);
6838 %}
6839
6840 // Long Negation
6841
6842 instruct negL_reg(iRegLNoSp dst, iRegL src, immL0 zero) %{
6843 match(Set dst (SubL zero src));
6844 ins_cost(ALU_COST);
6845 format %{ "sub $dst, x0, $src\t# long, #@negL_reg" %}
6846
6847 ins_encode %{
6848 // actually call the sub
6849 __ neg(as_Register($dst$$reg),
6850 as_Register($src$$reg));
6851 %}
6852
6853 ins_pipe(ialu_reg);
6854 %}
6855
6856 // Integer Multiply
6857
6858 instruct mulI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6859 match(Set dst (MulI src1 src2));
6860 ins_cost(IMUL_COST);
6861 format %{ "mulw $dst, $src1, $src2\t#@mulI" %}
6862
6863 //this means 2 word multi, and no sign extend to 64 bits
6864 ins_encode %{
6865 // riscv64 mulw will sign-extension to high 32 bits in dst reg
6866 __ mulw(as_Register($dst$$reg),
6867 as_Register($src1$$reg),
6868 as_Register($src2$$reg));
6869 %}
6870
6871 ins_pipe(imul_reg_reg);
6872 %}
6873
6874 // Long Multiply
6875
6876 instruct mulL(iRegLNoSp dst, iRegL src1, iRegL src2) %{
6877 match(Set dst (MulL src1 src2));
6878 ins_cost(IMUL_COST);
6879 format %{ "mul $dst, $src1, $src2\t#@mulL" %}
6880
6881 ins_encode %{
6882 __ mul(as_Register($dst$$reg),
6883 as_Register($src1$$reg),
6884 as_Register($src2$$reg));
6885 %}
6886
6887 ins_pipe(lmul_reg_reg);
6888 %}
6889
6890 instruct mulHiL_rReg(iRegLNoSp dst, iRegL src1, iRegL src2)
6891 %{
6892 match(Set dst (MulHiL src1 src2));
6893 ins_cost(IMUL_COST);
6894 format %{ "mulh $dst, $src1, $src2\t# mulhi, #@mulHiL_rReg" %}
6895
6896 ins_encode %{
6897 __ mulh(as_Register($dst$$reg),
6898 as_Register($src1$$reg),
6899 as_Register($src2$$reg));
6900 %}
6901
6902 ins_pipe(lmul_reg_reg);
6903 %}
6904
6905 instruct umulHiL_rReg(iRegLNoSp dst, iRegL src1, iRegL src2)
6906 %{
6907 match(Set dst (UMulHiL src1 src2));
6908 ins_cost(IMUL_COST);
6909 format %{ "mulhu $dst, $src1, $src2\t# umulhi, #@umulHiL_rReg" %}
6910
6911 ins_encode %{
6912 __ mulhu(as_Register($dst$$reg),
6913 as_Register($src1$$reg),
6914 as_Register($src2$$reg));
6915 %}
6916
6917 ins_pipe(lmul_reg_reg);
6918 %}
6919
6920 // Integer Divide
6921
6922 instruct divI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6923 match(Set dst (DivI src1 src2));
6924 ins_cost(IDIVSI_COST);
6925 format %{ "divw $dst, $src1, $src2\t#@divI"%}
6926
6927 ins_encode %{
6928 __ divw(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg));
6929 %}
6930 ins_pipe(idiv_reg_reg);
6931 %}
6932
6933 instruct UdivI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6934 match(Set dst (UDivI src1 src2));
6935 ins_cost(IDIVSI_COST);
6936 format %{ "divuw $dst, $src1, $src2\t#@UdivI"%}
6937
6938 ins_encode %{
6939 __ divuw(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg));
6940 %}
6941 ins_pipe(idiv_reg_reg);
6942 %}
6943
6944 instruct signExtract(iRegINoSp dst, iRegIorL2I src1, immI_31 div1, immI_31 div2) %{
6945 match(Set dst (URShiftI (RShiftI src1 div1) div2));
6946 ins_cost(ALU_COST);
6947 format %{ "srliw $dst, $src1, $div1\t# int signExtract, #@signExtract" %}
6948
6949 ins_encode %{
6950 __ srliw(as_Register($dst$$reg), as_Register($src1$$reg), 31);
6951 %}
6952 ins_pipe(ialu_reg_shift);
6953 %}
6954
6955 // Long Divide
6956
6957 instruct divL(iRegLNoSp dst, iRegL src1, iRegL src2) %{
6958 match(Set dst (DivL src1 src2));
6959 ins_cost(IDIVDI_COST);
6960 format %{ "div $dst, $src1, $src2\t#@divL" %}
6961
6962 ins_encode %{
6963 __ div(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg));
6964 %}
6965 ins_pipe(ldiv_reg_reg);
6966 %}
6967
6968 instruct UdivL(iRegLNoSp dst, iRegL src1, iRegL src2) %{
6969 match(Set dst (UDivL src1 src2));
6970 ins_cost(IDIVDI_COST);
6971
6972 format %{ "divu $dst, $src1, $src2\t#@UdivL" %}
6973
6974 ins_encode %{
6975 __ divu(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg));
6976 %}
6977 ins_pipe(ldiv_reg_reg);
6978 %}
6979
6980 instruct signExtractL(iRegLNoSp dst, iRegL src1, immI_63 div1, immI_63 div2) %{
6981 match(Set dst (URShiftL (RShiftL src1 div1) div2));
6982 ins_cost(ALU_COST);
6983 format %{ "srli $dst, $src1, $div1\t# long signExtract, #@signExtractL" %}
6984
6985 ins_encode %{
6986 __ srli(as_Register($dst$$reg), as_Register($src1$$reg), 63);
6987 %}
6988 ins_pipe(ialu_reg_shift);
6989 %}
6990
6991 // Integer Remainder
6992
6993 instruct modI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6994 match(Set dst (ModI src1 src2));
6995 ins_cost(IDIVSI_COST);
6996 format %{ "remw $dst, $src1, $src2\t#@modI" %}
6997
6998 ins_encode %{
6999 __ remw(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg));
7000 %}
7001 ins_pipe(ialu_reg_reg);
7002 %}
7003
7004 instruct UmodI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
7005 match(Set dst (UModI src1 src2));
7006 ins_cost(IDIVSI_COST);
7007 format %{ "remuw $dst, $src1, $src2\t#@UmodI" %}
7008
7009 ins_encode %{
7010 __ remuw(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg));
7011 %}
7012 ins_pipe(ialu_reg_reg);
7013 %}
7014
7015 // Long Remainder
7016
7017 instruct modL(iRegLNoSp dst, iRegL src1, iRegL src2) %{
7018 match(Set dst (ModL src1 src2));
7019 ins_cost(IDIVDI_COST);
7020 format %{ "rem $dst, $src1, $src2\t#@modL" %}
7021
7022 ins_encode %{
7023 __ rem(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg));
7024 %}
7025 ins_pipe(ialu_reg_reg);
7026 %}
7027
7028 instruct UmodL(iRegLNoSp dst, iRegL src1, iRegL src2) %{
7029 match(Set dst (UModL src1 src2));
7030 ins_cost(IDIVDI_COST);
7031 format %{ "remu $dst, $src1, $src2\t#@UmodL" %}
7032
7033 ins_encode %{
7034 __ remu(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg));
7035 %}
7036 ins_pipe(ialu_reg_reg);
7037 %}
7038
7039 // Integer Shifts
7040
7041 // Shift Left Register
7042 // Only the low 5 bits of src2 are considered for the shift amount, all other bits are ignored.
7043 instruct lShiftI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
7044 match(Set dst (LShiftI src1 src2));
7045 ins_cost(ALU_COST);
7046 format %{ "sllw $dst, $src1, $src2\t#@lShiftI_reg_reg" %}
7047
7048 ins_encode %{
7049 __ sllw(as_Register($dst$$reg),
7050 as_Register($src1$$reg),
7051 as_Register($src2$$reg));
7052 %}
7053
7054 ins_pipe(ialu_reg_reg_vshift);
7055 %}
7056
7057 // Shift Left Immediate
7058 instruct lShiftI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immI src2) %{
7059 match(Set dst (LShiftI src1 src2));
7060 ins_cost(ALU_COST);
7061 format %{ "slliw $dst, $src1, ($src2 & 0x1f)\t#@lShiftI_reg_imm" %}
7062
7063 ins_encode %{
7064 // the shift amount is encoded in the lower
7065 // 5 bits of the I-immediate field for RV32I
7066 __ slliw(as_Register($dst$$reg),
7067 as_Register($src1$$reg),
7068 (unsigned) $src2$$constant & 0x1f);
7069 %}
7070
7071 ins_pipe(ialu_reg_shift);
7072 %}
7073
7074 // Shift Right Logical Register
7075 // Only the low 5 bits of src2 are considered for the shift amount, all other bits are ignored.
7076 instruct urShiftI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
7077 match(Set dst (URShiftI src1 src2));
7078 ins_cost(ALU_COST);
7079 format %{ "srlw $dst, $src1, $src2\t#@urShiftI_reg_reg" %}
7080
7081 ins_encode %{
7082 __ srlw(as_Register($dst$$reg),
7083 as_Register($src1$$reg),
7084 as_Register($src2$$reg));
7085 %}
7086
7087 ins_pipe(ialu_reg_reg_vshift);
7088 %}
7089
7090 // Shift Right Logical Immediate
7091 instruct urShiftI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immI src2) %{
7092 match(Set dst (URShiftI src1 src2));
7093 ins_cost(ALU_COST);
7094 format %{ "srliw $dst, $src1, ($src2 & 0x1f)\t#@urShiftI_reg_imm" %}
7095
7096 ins_encode %{
7097 // the shift amount is encoded in the lower
7098 // 6 bits of the I-immediate field for RV64I
7099 __ srliw(as_Register($dst$$reg),
7100 as_Register($src1$$reg),
7101 (unsigned) $src2$$constant & 0x1f);
7102 %}
7103
7104 ins_pipe(ialu_reg_shift);
7105 %}
7106
7107 // Shift Right Arithmetic Register
7108 // Only the low 5 bits of src2 are considered for the shift amount, all other bits are ignored.
7109 instruct rShiftI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
7110 match(Set dst (RShiftI src1 src2));
7111 ins_cost(ALU_COST);
7112 format %{ "sraw $dst, $src1, $src2\t#@rShiftI_reg_reg" %}
7113
7114 ins_encode %{
7115 // riscv will sign-ext dst high 32 bits
7116 __ sraw(as_Register($dst$$reg),
7117 as_Register($src1$$reg),
7118 as_Register($src2$$reg));
7119 %}
7120
7121 ins_pipe(ialu_reg_reg_vshift);
7122 %}
7123
7124 // Shift Right Arithmetic Immediate
7125 instruct rShiftI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immI src2) %{
7126 match(Set dst (RShiftI src1 src2));
7127 ins_cost(ALU_COST);
7128 format %{ "sraiw $dst, $src1, ($src2 & 0x1f)\t#@rShiftI_reg_imm" %}
7129
7130 ins_encode %{
7131 // riscv will sign-ext dst high 32 bits
7132 __ sraiw(as_Register($dst$$reg),
7133 as_Register($src1$$reg),
7134 (unsigned) $src2$$constant & 0x1f);
7135 %}
7136
7137 ins_pipe(ialu_reg_shift);
7138 %}
7139
7140 // Long Shifts
7141
7142 // Shift Left Register
7143 // Only the low 6 bits of src2 are considered for the shift amount, all other bits are ignored.
7144 instruct lShiftL_reg_reg(iRegLNoSp dst, iRegL src1, iRegIorL2I src2) %{
7145 match(Set dst (LShiftL src1 src2));
7146
7147 ins_cost(ALU_COST);
7148 format %{ "sll $dst, $src1, $src2\t#@lShiftL_reg_reg" %}
7149
7150 ins_encode %{
7151 __ sll(as_Register($dst$$reg),
7152 as_Register($src1$$reg),
7153 as_Register($src2$$reg));
7154 %}
7155
7156 ins_pipe(ialu_reg_reg_vshift);
7157 %}
7158
7159 // Shift Left Immediate
7160 instruct lShiftL_reg_imm(iRegLNoSp dst, iRegL src1, immI src2) %{
7161 match(Set dst (LShiftL src1 src2));
7162
7163 ins_cost(ALU_COST);
7164 format %{ "slli $dst, $src1, ($src2 & 0x3f)\t#@lShiftL_reg_imm" %}
7165
7166 ins_encode %{
7167 // the shift amount is encoded in the lower
7168 // 6 bits of the I-immediate field for RV64I
7169 __ slli(as_Register($dst$$reg),
7170 as_Register($src1$$reg),
7171 (unsigned) $src2$$constant & 0x3f);
7172 %}
7173
7174 ins_pipe(ialu_reg_shift);
7175 %}
7176
7177 // Shift Right Logical Register
7178 // Only the low 6 bits of src2 are considered for the shift amount, all other bits are ignored.
7179 instruct urShiftL_reg_reg(iRegLNoSp dst, iRegL src1, iRegIorL2I src2) %{
7180 match(Set dst (URShiftL src1 src2));
7181
7182 ins_cost(ALU_COST);
7183 format %{ "srl $dst, $src1, $src2\t#@urShiftL_reg_reg" %}
7184
7185 ins_encode %{
7186 __ srl(as_Register($dst$$reg),
7187 as_Register($src1$$reg),
7188 as_Register($src2$$reg));
7189 %}
7190
7191 ins_pipe(ialu_reg_reg_vshift);
7192 %}
7193
7194 // Shift Right Logical Immediate
7195 instruct urShiftL_reg_imm(iRegLNoSp dst, iRegL src1, immI src2) %{
7196 match(Set dst (URShiftL src1 src2));
7197
7198 ins_cost(ALU_COST);
7199 format %{ "srli $dst, $src1, ($src2 & 0x3f)\t#@urShiftL_reg_imm" %}
7200
7201 ins_encode %{
7202 // the shift amount is encoded in the lower
7203 // 6 bits of the I-immediate field for RV64I
7204 __ srli(as_Register($dst$$reg),
7205 as_Register($src1$$reg),
7206 (unsigned) $src2$$constant & 0x3f);
7207 %}
7208
7209 ins_pipe(ialu_reg_shift);
7210 %}
7211
7212 // A special-case pattern for card table stores.
7213 instruct urShiftP_reg_imm(iRegLNoSp dst, iRegP src1, immI src2) %{
7214 match(Set dst (URShiftL (CastP2X src1) src2));
7215
7216 ins_cost(ALU_COST);
7217 format %{ "srli $dst, p2x($src1), ($src2 & 0x3f)\t#@urShiftP_reg_imm" %}
7218
7219 ins_encode %{
7220 // the shift amount is encoded in the lower
7221 // 6 bits of the I-immediate field for RV64I
7222 __ srli(as_Register($dst$$reg),
7223 as_Register($src1$$reg),
7224 (unsigned) $src2$$constant & 0x3f);
7225 %}
7226
7227 ins_pipe(ialu_reg_shift);
7228 %}
7229
7230 // Shift Right Arithmetic Register
7231 // Only the low 6 bits of src2 are considered for the shift amount, all other bits are ignored.
7232 instruct rShiftL_reg_reg(iRegLNoSp dst, iRegL src1, iRegIorL2I src2) %{
7233 match(Set dst (RShiftL src1 src2));
7234
7235 ins_cost(ALU_COST);
7236 format %{ "sra $dst, $src1, $src2\t#@rShiftL_reg_reg" %}
7237
7238 ins_encode %{
7239 __ sra(as_Register($dst$$reg),
7240 as_Register($src1$$reg),
7241 as_Register($src2$$reg));
7242 %}
7243
7244 ins_pipe(ialu_reg_reg_vshift);
7245 %}
7246
7247 // Shift Right Arithmetic Immediate
7248 instruct rShiftL_reg_imm(iRegLNoSp dst, iRegL src1, immI src2) %{
7249 match(Set dst (RShiftL src1 src2));
7250
7251 ins_cost(ALU_COST);
7252 format %{ "srai $dst, $src1, ($src2 & 0x3f)\t#@rShiftL_reg_imm" %}
7253
7254 ins_encode %{
7255 // the shift amount is encoded in the lower
7256 // 6 bits of the I-immediate field for RV64I
7257 __ srai(as_Register($dst$$reg),
7258 as_Register($src1$$reg),
7259 (unsigned) $src2$$constant & 0x3f);
7260 %}
7261
7262 ins_pipe(ialu_reg_shift);
7263 %}
7264
7265 instruct regI_not_reg(iRegINoSp dst, iRegI src1, immI_M1 m1) %{
7266 match(Set dst (XorI src1 m1));
7267 ins_cost(ALU_COST);
7268 format %{ "xori $dst, $src1, -1\t#@regI_not_reg" %}
7269
7270 ins_encode %{
7271 __ xori(as_Register($dst$$reg), as_Register($src1$$reg), -1);
7272 %}
7273
7274 ins_pipe(ialu_reg_imm);
7275 %}
7276
7277 instruct regL_not_reg(iRegLNoSp dst, iRegL src1, immL_M1 m1) %{
7278 match(Set dst (XorL src1 m1));
7279 ins_cost(ALU_COST);
7280 format %{ "xori $dst, $src1, -1\t#@regL_not_reg" %}
7281
7282 ins_encode %{
7283 __ xori(as_Register($dst$$reg), as_Register($src1$$reg), -1);
7284 %}
7285
7286 ins_pipe(ialu_reg_imm);
7287 %}
7288
7289
7290 // ============================================================================
7291 // Floating Point Arithmetic Instructions
7292
7293 instruct addF_reg_reg(fRegF dst, fRegF src1, fRegF src2) %{
7294 match(Set dst (AddF src1 src2));
7295
7296 ins_cost(DEFAULT_COST * 5);
7297 format %{ "fadd.s $dst, $src1, $src2\t#@addF_reg_reg" %}
7298
7299 ins_encode %{
7300 __ fadd_s(as_FloatRegister($dst$$reg),
7301 as_FloatRegister($src1$$reg),
7302 as_FloatRegister($src2$$reg));
7303 %}
7304
7305 ins_pipe(fp_dop_reg_reg_s);
7306 %}
7307
7308 instruct addD_reg_reg(fRegD dst, fRegD src1, fRegD src2) %{
7309 match(Set dst (AddD src1 src2));
7310
7311 ins_cost(DEFAULT_COST * 5);
7312 format %{ "fadd.d $dst, $src1, $src2\t#@addD_reg_reg" %}
7313
7314 ins_encode %{
7315 __ fadd_d(as_FloatRegister($dst$$reg),
7316 as_FloatRegister($src1$$reg),
7317 as_FloatRegister($src2$$reg));
7318 %}
7319
7320 ins_pipe(fp_dop_reg_reg_d);
7321 %}
7322
7323 instruct subF_reg_reg(fRegF dst, fRegF src1, fRegF src2) %{
7324 match(Set dst (SubF src1 src2));
7325
7326 ins_cost(DEFAULT_COST * 5);
7327 format %{ "fsub.s $dst, $src1, $src2\t#@subF_reg_reg" %}
7328
7329 ins_encode %{
7330 __ fsub_s(as_FloatRegister($dst$$reg),
7331 as_FloatRegister($src1$$reg),
7332 as_FloatRegister($src2$$reg));
7333 %}
7334
7335 ins_pipe(fp_dop_reg_reg_s);
7336 %}
7337
7338 instruct subD_reg_reg(fRegD dst, fRegD src1, fRegD src2) %{
7339 match(Set dst (SubD src1 src2));
7340
7341 ins_cost(DEFAULT_COST * 5);
7342 format %{ "fsub.d $dst, $src1, $src2\t#@subD_reg_reg" %}
7343
7344 ins_encode %{
7345 __ fsub_d(as_FloatRegister($dst$$reg),
7346 as_FloatRegister($src1$$reg),
7347 as_FloatRegister($src2$$reg));
7348 %}
7349
7350 ins_pipe(fp_dop_reg_reg_d);
7351 %}
7352
7353 instruct mulF_reg_reg(fRegF dst, fRegF src1, fRegF src2) %{
7354 match(Set dst (MulF src1 src2));
7355
7356 ins_cost(FMUL_SINGLE_COST);
7357 format %{ "fmul.s $dst, $src1, $src2\t#@mulF_reg_reg" %}
7358
7359 ins_encode %{
7360 __ fmul_s(as_FloatRegister($dst$$reg),
7361 as_FloatRegister($src1$$reg),
7362 as_FloatRegister($src2$$reg));
7363 %}
7364
7365 ins_pipe(fp_dop_reg_reg_s);
7366 %}
7367
7368 instruct mulD_reg_reg(fRegD dst, fRegD src1, fRegD src2) %{
7369 match(Set dst (MulD src1 src2));
7370
7371 ins_cost(FMUL_DOUBLE_COST);
7372 format %{ "fmul.d $dst, $src1, $src2\t#@mulD_reg_reg" %}
7373
7374 ins_encode %{
7375 __ fmul_d(as_FloatRegister($dst$$reg),
7376 as_FloatRegister($src1$$reg),
7377 as_FloatRegister($src2$$reg));
7378 %}
7379
7380 ins_pipe(fp_dop_reg_reg_d);
7381 %}
7382
7383 // src1 * src2 + src3
7384 instruct maddF_reg_reg(fRegF dst, fRegF src1, fRegF src2, fRegF src3) %{
7385 match(Set dst (FmaF src3 (Binary src1 src2)));
7386
7387 ins_cost(FMUL_SINGLE_COST);
7388 format %{ "fmadd.s $dst, $src1, $src2, $src3\t#@maddF_reg_reg" %}
7389
7390 ins_encode %{
7391 assert(UseFMA, "Needs FMA instructions support.");
7392 __ fmadd_s(as_FloatRegister($dst$$reg),
7393 as_FloatRegister($src1$$reg),
7394 as_FloatRegister($src2$$reg),
7395 as_FloatRegister($src3$$reg));
7396 %}
7397
7398 ins_pipe(pipe_class_default);
7399 %}
7400
7401 // src1 * src2 + src3
7402 instruct maddD_reg_reg(fRegD dst, fRegD src1, fRegD src2, fRegD src3) %{
7403 match(Set dst (FmaD src3 (Binary src1 src2)));
7404
7405 ins_cost(FMUL_DOUBLE_COST);
7406 format %{ "fmadd.d $dst, $src1, $src2, $src3\t#@maddD_reg_reg" %}
7407
7408 ins_encode %{
7409 assert(UseFMA, "Needs FMA instructions support.");
7410 __ fmadd_d(as_FloatRegister($dst$$reg),
7411 as_FloatRegister($src1$$reg),
7412 as_FloatRegister($src2$$reg),
7413 as_FloatRegister($src3$$reg));
7414 %}
7415
7416 ins_pipe(pipe_class_default);
7417 %}
7418
7419 // src1 * src2 - src3
7420 instruct msubF_reg_reg(fRegF dst, fRegF src1, fRegF src2, fRegF src3) %{
7421 match(Set dst (FmaF (NegF src3) (Binary src1 src2)));
7422
7423 ins_cost(FMUL_SINGLE_COST);
7424 format %{ "fmsub.s $dst, $src1, $src2, $src3\t#@msubF_reg_reg" %}
7425
7426 ins_encode %{
7427 assert(UseFMA, "Needs FMA instructions support.");
7428 __ fmsub_s(as_FloatRegister($dst$$reg),
7429 as_FloatRegister($src1$$reg),
7430 as_FloatRegister($src2$$reg),
7431 as_FloatRegister($src3$$reg));
7432 %}
7433
7434 ins_pipe(pipe_class_default);
7435 %}
7436
7437 // src1 * src2 - src3
7438 instruct msubD_reg_reg(fRegD dst, fRegD src1, fRegD src2, fRegD src3) %{
7439 match(Set dst (FmaD (NegD src3) (Binary src1 src2)));
7440
7441 ins_cost(FMUL_DOUBLE_COST);
7442 format %{ "fmsub.d $dst, $src1, $src2, $src3\t#@msubD_reg_reg" %}
7443
7444 ins_encode %{
7445 assert(UseFMA, "Needs FMA instructions support.");
7446 __ fmsub_d(as_FloatRegister($dst$$reg),
7447 as_FloatRegister($src1$$reg),
7448 as_FloatRegister($src2$$reg),
7449 as_FloatRegister($src3$$reg));
7450 %}
7451
7452 ins_pipe(pipe_class_default);
7453 %}
7454
7455 // src1 * (-src2) + src3
7456 // "(-src1) * src2 + src3" has been idealized to "src2 * (-src1) + src3"
7457 instruct nmsubF_reg_reg(fRegF dst, fRegF src1, fRegF src2, fRegF src3) %{
7458 match(Set dst (FmaF src3 (Binary src1 (NegF src2))));
7459
7460 ins_cost(FMUL_SINGLE_COST);
7461 format %{ "fnmsub.s $dst, $src1, $src2, $src3\t#@nmsubF_reg_reg" %}
7462
7463 ins_encode %{
7464 assert(UseFMA, "Needs FMA instructions support.");
7465 __ fnmsub_s(as_FloatRegister($dst$$reg),
7466 as_FloatRegister($src1$$reg),
7467 as_FloatRegister($src2$$reg),
7468 as_FloatRegister($src3$$reg));
7469 %}
7470
7471 ins_pipe(pipe_class_default);
7472 %}
7473
7474 // src1 * (-src2) + src3
7475 // "(-src1) * src2 + src3" has been idealized to "src2 * (-src1) + src3"
7476 instruct nmsubD_reg_reg(fRegD dst, fRegD src1, fRegD src2, fRegD src3) %{
7477 match(Set dst (FmaD src3 (Binary src1 (NegD src2))));
7478
7479 ins_cost(FMUL_DOUBLE_COST);
7480 format %{ "fnmsub.d $dst, $src1, $src2, $src3\t#@nmsubD_reg_reg" %}
7481
7482 ins_encode %{
7483 assert(UseFMA, "Needs FMA instructions support.");
7484 __ fnmsub_d(as_FloatRegister($dst$$reg),
7485 as_FloatRegister($src1$$reg),
7486 as_FloatRegister($src2$$reg),
7487 as_FloatRegister($src3$$reg));
7488 %}
7489
7490 ins_pipe(pipe_class_default);
7491 %}
7492
7493 // src1 * (-src2) - src3
7494 // "(-src1) * src2 - src3" has been idealized to "src2 * (-src1) - src3"
7495 instruct nmaddF_reg_reg(fRegF dst, fRegF src1, fRegF src2, fRegF src3) %{
7496 match(Set dst (FmaF (NegF src3) (Binary src1 (NegF src2))));
7497
7498 ins_cost(FMUL_SINGLE_COST);
7499 format %{ "fnmadd.s $dst, $src1, $src2, $src3\t#@nmaddF_reg_reg" %}
7500
7501 ins_encode %{
7502 assert(UseFMA, "Needs FMA instructions support.");
7503 __ fnmadd_s(as_FloatRegister($dst$$reg),
7504 as_FloatRegister($src1$$reg),
7505 as_FloatRegister($src2$$reg),
7506 as_FloatRegister($src3$$reg));
7507 %}
7508
7509 ins_pipe(pipe_class_default);
7510 %}
7511
7512 // src1 * (-src2) - src3
7513 // "(-src1) * src2 - src3" has been idealized to "src2 * (-src1) - src3"
7514 instruct nmaddD_reg_reg(fRegD dst, fRegD src1, fRegD src2, fRegD src3) %{
7515 match(Set dst (FmaD (NegD src3) (Binary src1 (NegD src2))));
7516
7517 ins_cost(FMUL_DOUBLE_COST);
7518 format %{ "fnmadd.d $dst, $src1, $src2, $src3\t#@nmaddD_reg_reg" %}
7519
7520 ins_encode %{
7521 assert(UseFMA, "Needs FMA instructions support.");
7522 __ fnmadd_d(as_FloatRegister($dst$$reg),
7523 as_FloatRegister($src1$$reg),
7524 as_FloatRegister($src2$$reg),
7525 as_FloatRegister($src3$$reg));
7526 %}
7527
7528 ins_pipe(pipe_class_default);
7529 %}
7530
7531 // Math.max(FF)F
7532 instruct maxF_reg_reg(fRegF dst, fRegF src1, fRegF src2, rFlagsReg cr) %{
7533 predicate(!UseZfa);
7534 match(Set dst (MaxF src1 src2));
7535 effect(KILL cr);
7536
7537 format %{ "maxF $dst, $src1, $src2" %}
7538
7539 ins_encode %{
7540 __ minmax_fp(as_FloatRegister($dst$$reg),
7541 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg),
7542 __ FLOAT_TYPE::single_precision, false /* is_min */);
7543 %}
7544
7545 ins_pipe(pipe_class_default);
7546 %}
7547
7548 instruct maxF_reg_reg_zfa(fRegF dst, fRegF src1, fRegF src2) %{
7549 predicate(UseZfa);
7550 match(Set dst (MaxF src1 src2));
7551
7552 format %{ "maxF $dst, $src1, $src2" %}
7553
7554 ins_encode %{
7555 __ fmaxm_s(as_FloatRegister($dst$$reg),
7556 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
7557 %}
7558
7559 ins_pipe(pipe_class_default);
7560 %}
7561
7562 // Math.min(FF)F
7563 instruct minF_reg_reg(fRegF dst, fRegF src1, fRegF src2, rFlagsReg cr) %{
7564 predicate(!UseZfa);
7565 match(Set dst (MinF src1 src2));
7566 effect(KILL cr);
7567
7568 format %{ "minF $dst, $src1, $src2" %}
7569
7570 ins_encode %{
7571 __ minmax_fp(as_FloatRegister($dst$$reg),
7572 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg),
7573 __ FLOAT_TYPE::single_precision, true /* is_min */);
7574 %}
7575
7576 ins_pipe(pipe_class_default);
7577 %}
7578
7579 instruct minF_reg_reg_zfa(fRegF dst, fRegF src1, fRegF src2) %{
7580 predicate(UseZfa);
7581 match(Set dst (MinF src1 src2));
7582
7583 format %{ "minF $dst, $src1, $src2" %}
7584
7585 ins_encode %{
7586 __ fminm_s(as_FloatRegister($dst$$reg),
7587 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
7588 %}
7589
7590 ins_pipe(pipe_class_default);
7591 %}
7592
7593 // Math.max(DD)D
7594 instruct maxD_reg_reg(fRegD dst, fRegD src1, fRegD src2, rFlagsReg cr) %{
7595 predicate(!UseZfa);
7596 match(Set dst (MaxD src1 src2));
7597 effect(KILL cr);
7598
7599 format %{ "maxD $dst, $src1, $src2" %}
7600
7601 ins_encode %{
7602 __ minmax_fp(as_FloatRegister($dst$$reg),
7603 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg),
7604 __ FLOAT_TYPE::double_precision, false /* is_min */);
7605 %}
7606
7607 ins_pipe(pipe_class_default);
7608 %}
7609
7610 instruct maxD_reg_reg_zfa(fRegD dst, fRegD src1, fRegD src2) %{
7611 predicate(UseZfa);
7612 match(Set dst (MaxD src1 src2));
7613
7614 format %{ "maxD $dst, $src1, $src2" %}
7615
7616 ins_encode %{
7617 __ fmaxm_d(as_FloatRegister($dst$$reg),
7618 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
7619 %}
7620
7621 ins_pipe(pipe_class_default);
7622 %}
7623
7624 // Math.min(DD)D
7625 instruct minD_reg_reg(fRegD dst, fRegD src1, fRegD src2, rFlagsReg cr) %{
7626 predicate(!UseZfa);
7627 match(Set dst (MinD src1 src2));
7628 effect(KILL cr);
7629
7630 format %{ "minD $dst, $src1, $src2" %}
7631
7632 ins_encode %{
7633 __ minmax_fp(as_FloatRegister($dst$$reg),
7634 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg),
7635 __ FLOAT_TYPE::double_precision, true /* is_min */);
7636 %}
7637
7638 ins_pipe(pipe_class_default);
7639 %}
7640
7641 instruct minD_reg_reg_zfa(fRegD dst, fRegD src1, fRegD src2) %{
7642 predicate(UseZfa);
7643 match(Set dst (MinD src1 src2));
7644
7645 format %{ "minD $dst, $src1, $src2" %}
7646
7647 ins_encode %{
7648 __ fminm_d(as_FloatRegister($dst$$reg),
7649 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
7650 %}
7651
7652 ins_pipe(pipe_class_default);
7653 %}
7654
7655 // Float.isInfinite
7656 instruct isInfiniteF_reg_reg(iRegINoSp dst, fRegF src)
7657 %{
7658 match(Set dst (IsInfiniteF src));
7659
7660 format %{ "isInfinite $dst, $src" %}
7661 ins_encode %{
7662 __ fclass_s(as_Register($dst$$reg), as_FloatRegister($src$$reg));
7663 __ andi(as_Register($dst$$reg), as_Register($dst$$reg), Assembler::FClassBits::inf);
7664 __ slt(as_Register($dst$$reg), zr, as_Register($dst$$reg));
7665 %}
7666
7667 ins_pipe(pipe_class_default);
7668 %}
7669
7670 // Double.isInfinite
7671 instruct isInfiniteD_reg_reg(iRegINoSp dst, fRegD src)
7672 %{
7673 match(Set dst (IsInfiniteD src));
7674
7675 format %{ "isInfinite $dst, $src" %}
7676 ins_encode %{
7677 __ fclass_d(as_Register($dst$$reg), as_FloatRegister($src$$reg));
7678 __ andi(as_Register($dst$$reg), as_Register($dst$$reg), Assembler::FClassBits::inf);
7679 __ slt(as_Register($dst$$reg), zr, as_Register($dst$$reg));
7680 %}
7681
7682 ins_pipe(pipe_class_default);
7683 %}
7684
7685 // Float.isFinite
7686 instruct isFiniteF_reg_reg(iRegINoSp dst, fRegF src)
7687 %{
7688 match(Set dst (IsFiniteF src));
7689
7690 format %{ "isFinite $dst, $src" %}
7691 ins_encode %{
7692 __ fclass_s(as_Register($dst$$reg), as_FloatRegister($src$$reg));
7693 __ andi(as_Register($dst$$reg), as_Register($dst$$reg), Assembler::FClassBits::finite);
7694 __ slt(as_Register($dst$$reg), zr, as_Register($dst$$reg));
7695 %}
7696
7697 ins_pipe(pipe_class_default);
7698 %}
7699
7700 // Double.isFinite
7701 instruct isFiniteD_reg_reg(iRegINoSp dst, fRegD src)
7702 %{
7703 match(Set dst (IsFiniteD src));
7704
7705 format %{ "isFinite $dst, $src" %}
7706 ins_encode %{
7707 __ fclass_d(as_Register($dst$$reg), as_FloatRegister($src$$reg));
7708 __ andi(as_Register($dst$$reg), as_Register($dst$$reg), Assembler::FClassBits::finite);
7709 __ slt(as_Register($dst$$reg), zr, as_Register($dst$$reg));
7710 %}
7711
7712 ins_pipe(pipe_class_default);
7713 %}
7714
7715 instruct divF_reg_reg(fRegF dst, fRegF src1, fRegF src2) %{
7716 match(Set dst (DivF src1 src2));
7717
7718 ins_cost(FDIV_COST);
7719 format %{ "fdiv.s $dst, $src1, $src2\t#@divF_reg_reg" %}
7720
7721 ins_encode %{
7722 __ fdiv_s(as_FloatRegister($dst$$reg),
7723 as_FloatRegister($src1$$reg),
7724 as_FloatRegister($src2$$reg));
7725 %}
7726
7727 ins_pipe(fp_div_s);
7728 %}
7729
7730 instruct divD_reg_reg(fRegD dst, fRegD src1, fRegD src2) %{
7731 match(Set dst (DivD src1 src2));
7732
7733 ins_cost(FDIV_COST);
7734 format %{ "fdiv.d $dst, $src1, $src2\t#@divD_reg_reg" %}
7735
7736 ins_encode %{
7737 __ fdiv_d(as_FloatRegister($dst$$reg),
7738 as_FloatRegister($src1$$reg),
7739 as_FloatRegister($src2$$reg));
7740 %}
7741
7742 ins_pipe(fp_div_d);
7743 %}
7744
7745 instruct negF_reg_reg(fRegF dst, fRegF src) %{
7746 match(Set dst (NegF src));
7747
7748 ins_cost(XFER_COST);
7749 format %{ "fsgnjn.s $dst, $src, $src\t#@negF_reg_reg" %}
7750
7751 ins_encode %{
7752 __ fneg_s(as_FloatRegister($dst$$reg),
7753 as_FloatRegister($src$$reg));
7754 %}
7755
7756 ins_pipe(fp_uop_s);
7757 %}
7758
7759 instruct negD_reg_reg(fRegD dst, fRegD src) %{
7760 match(Set dst (NegD src));
7761
7762 ins_cost(XFER_COST);
7763 format %{ "fsgnjn.d $dst, $src, $src\t#@negD_reg_reg" %}
7764
7765 ins_encode %{
7766 __ fneg_d(as_FloatRegister($dst$$reg),
7767 as_FloatRegister($src$$reg));
7768 %}
7769
7770 ins_pipe(fp_uop_d);
7771 %}
7772
7773 instruct absI_reg(iRegINoSp dst, iRegIorL2I src) %{
7774 match(Set dst (AbsI src));
7775
7776 ins_cost(ALU_COST * 3);
7777 format %{
7778 "sraiw t0, $src, 0x1f\n\t"
7779 "addw $dst, $src, t0\n\t"
7780 "xorr $dst, $dst, t0\t#@absI_reg"
7781 %}
7782
7783 ins_encode %{
7784 __ sraiw(t0, as_Register($src$$reg), 0x1f);
7785 __ addw(as_Register($dst$$reg), as_Register($src$$reg), t0);
7786 __ xorr(as_Register($dst$$reg), as_Register($dst$$reg), t0);
7787 %}
7788
7789 ins_pipe(pipe_class_default);
7790 %}
7791
7792 instruct absL_reg(iRegLNoSp dst, iRegL src) %{
7793 match(Set dst (AbsL src));
7794
7795 ins_cost(ALU_COST * 3);
7796 format %{
7797 "srai t0, $src, 0x3f\n\t"
7798 "add $dst, $src, t0\n\t"
7799 "xorr $dst, $dst, t0\t#@absL_reg"
7800 %}
7801
7802 ins_encode %{
7803 __ srai(t0, as_Register($src$$reg), 0x3f);
7804 __ add(as_Register($dst$$reg), as_Register($src$$reg), t0);
7805 __ xorr(as_Register($dst$$reg), as_Register($dst$$reg), t0);
7806 %}
7807
7808 ins_pipe(pipe_class_default);
7809 %}
7810
7811 instruct absF_reg(fRegF dst, fRegF src) %{
7812 match(Set dst (AbsF src));
7813
7814 ins_cost(XFER_COST);
7815 format %{ "fsgnjx.s $dst, $src, $src\t#@absF_reg" %}
7816 ins_encode %{
7817 __ fabs_s(as_FloatRegister($dst$$reg),
7818 as_FloatRegister($src$$reg));
7819 %}
7820
7821 ins_pipe(fp_uop_s);
7822 %}
7823
7824 instruct absD_reg(fRegD dst, fRegD src) %{
7825 match(Set dst (AbsD src));
7826
7827 ins_cost(XFER_COST);
7828 format %{ "fsgnjx.d $dst, $src, $src\t#@absD_reg" %}
7829 ins_encode %{
7830 __ fabs_d(as_FloatRegister($dst$$reg),
7831 as_FloatRegister($src$$reg));
7832 %}
7833
7834 ins_pipe(fp_uop_d);
7835 %}
7836
7837 instruct sqrtF_reg(fRegF dst, fRegF src) %{
7838 match(Set dst (SqrtF src));
7839
7840 ins_cost(FSQRT_COST);
7841 format %{ "fsqrt.s $dst, $src\t#@sqrtF_reg" %}
7842 ins_encode %{
7843 __ fsqrt_s(as_FloatRegister($dst$$reg),
7844 as_FloatRegister($src$$reg));
7845 %}
7846
7847 ins_pipe(fp_sqrt_s);
7848 %}
7849
7850 instruct sqrtD_reg(fRegD dst, fRegD src) %{
7851 match(Set dst (SqrtD src));
7852
7853 ins_cost(FSQRT_COST);
7854 format %{ "fsqrt.d $dst, $src\t#@sqrtD_reg" %}
7855 ins_encode %{
7856 __ fsqrt_d(as_FloatRegister($dst$$reg),
7857 as_FloatRegister($src$$reg));
7858 %}
7859
7860 ins_pipe(fp_sqrt_d);
7861 %}
7862
7863 // Round Instruction
7864 instruct roundD_reg(fRegD dst, fRegD src, immI rmode, iRegLNoSp tmp1, iRegLNoSp tmp2, iRegLNoSp tmp3) %{
7865 match(Set dst (RoundDoubleMode src rmode));
7866 ins_cost(2 * XFER_COST + BRANCH_COST);
7867 effect(TEMP_DEF dst, TEMP tmp1, TEMP tmp2, TEMP tmp3);
7868
7869 format %{ "RoundDoubleMode $src, $rmode" %}
7870 ins_encode %{
7871 __ round_double_mode(as_FloatRegister($dst$$reg),
7872 as_FloatRegister($src$$reg), $rmode$$constant, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
7873 %}
7874 ins_pipe(pipe_class_default);
7875 %}
7876
7877 // Copysign and signum intrinsics
7878
7879 instruct copySignD_reg(fRegD dst, fRegD src1, fRegD src2, immD zero) %{
7880 match(Set dst (CopySignD src1 (Binary src2 zero)));
7881 format %{ "CopySignD $dst $src1 $src2" %}
7882 ins_encode %{
7883 FloatRegister dst = as_FloatRegister($dst$$reg),
7884 src1 = as_FloatRegister($src1$$reg),
7885 src2 = as_FloatRegister($src2$$reg);
7886 __ fsgnj_d(dst, src1, src2);
7887 %}
7888 ins_pipe(fp_dop_reg_reg_d);
7889 %}
7890
7891 instruct copySignF_reg(fRegF dst, fRegF src1, fRegF src2) %{
7892 match(Set dst (CopySignF src1 src2));
7893 format %{ "CopySignF $dst $src1 $src2" %}
7894 ins_encode %{
7895 FloatRegister dst = as_FloatRegister($dst$$reg),
7896 src1 = as_FloatRegister($src1$$reg),
7897 src2 = as_FloatRegister($src2$$reg);
7898 __ fsgnj_s(dst, src1, src2);
7899 %}
7900 ins_pipe(fp_dop_reg_reg_s);
7901 %}
7902
7903 instruct signumD_reg(fRegD dst, immD zero, fRegD one) %{
7904 match(Set dst (SignumD dst (Binary zero one)));
7905 format %{ "signumD $dst, $dst" %}
7906 ins_encode %{
7907 __ signum_fp(as_FloatRegister($dst$$reg), as_FloatRegister($one$$reg), true /* is_double */);
7908 %}
7909 ins_pipe(pipe_class_default);
7910 %}
7911
7912 instruct signumF_reg(fRegF dst, immF zero, fRegF one) %{
7913 match(Set dst (SignumF dst (Binary zero one)));
7914 format %{ "signumF $dst, $dst" %}
7915 ins_encode %{
7916 __ signum_fp(as_FloatRegister($dst$$reg), as_FloatRegister($one$$reg), false /* is_double */);
7917 %}
7918 ins_pipe(pipe_class_default);
7919 %}
7920
7921 // Arithmetic Instructions End
7922
7923 // ============================================================================
7924 // Logical Instructions
7925
7926 // Register And
7927 instruct andI_reg_reg(iRegINoSp dst, iRegI src1, iRegI src2) %{
7928 match(Set dst (AndI src1 src2));
7929
7930 format %{ "andr $dst, $src1, $src2\t#@andI_reg_reg" %}
7931
7932 ins_cost(ALU_COST);
7933 ins_encode %{
7934 __ andr(as_Register($dst$$reg),
7935 as_Register($src1$$reg),
7936 as_Register($src2$$reg));
7937 %}
7938
7939 ins_pipe(ialu_reg_reg);
7940 %}
7941
7942 // Immediate And
7943 instruct andI_reg_imm(iRegINoSp dst, iRegI src1, immIAdd src2) %{
7944 match(Set dst (AndI src1 src2));
7945
7946 format %{ "andi $dst, $src1, $src2\t#@andI_reg_imm" %}
7947
7948 ins_cost(ALU_COST);
7949 ins_encode %{
7950 __ andi(as_Register($dst$$reg),
7951 as_Register($src1$$reg),
7952 (int32_t)($src2$$constant));
7953 %}
7954
7955 ins_pipe(ialu_reg_imm);
7956 %}
7957
7958 // Register Or
7959 instruct orI_reg_reg(iRegINoSp dst, iRegI src1, iRegI src2) %{
7960 match(Set dst (OrI src1 src2));
7961
7962 format %{ "orr $dst, $src1, $src2\t#@orI_reg_reg" %}
7963
7964 ins_cost(ALU_COST);
7965 ins_encode %{
7966 __ orr(as_Register($dst$$reg),
7967 as_Register($src1$$reg),
7968 as_Register($src2$$reg));
7969 %}
7970
7971 ins_pipe(ialu_reg_reg);
7972 %}
7973
7974 // Immediate Or
7975 instruct orI_reg_imm(iRegINoSp dst, iRegI src1, immIAdd src2) %{
7976 match(Set dst (OrI src1 src2));
7977
7978 format %{ "ori $dst, $src1, $src2\t#@orI_reg_imm" %}
7979
7980 ins_cost(ALU_COST);
7981 ins_encode %{
7982 __ ori(as_Register($dst$$reg),
7983 as_Register($src1$$reg),
7984 (int32_t)($src2$$constant));
7985 %}
7986
7987 ins_pipe(ialu_reg_imm);
7988 %}
7989
7990 // Register Xor
7991 instruct xorI_reg_reg(iRegINoSp dst, iRegI src1, iRegI src2) %{
7992 match(Set dst (XorI src1 src2));
7993
7994 format %{ "xorr $dst, $src1, $src2\t#@xorI_reg_reg" %}
7995
7996 ins_cost(ALU_COST);
7997 ins_encode %{
7998 __ xorr(as_Register($dst$$reg),
7999 as_Register($src1$$reg),
8000 as_Register($src2$$reg));
8001 %}
8002
8003 ins_pipe(ialu_reg_reg);
8004 %}
8005
8006 // Immediate Xor
8007 instruct xorI_reg_imm(iRegINoSp dst, iRegI src1, immIAdd src2) %{
8008 match(Set dst (XorI src1 src2));
8009
8010 format %{ "xori $dst, $src1, $src2\t#@xorI_reg_imm" %}
8011
8012 ins_cost(ALU_COST);
8013 ins_encode %{
8014 __ xori(as_Register($dst$$reg),
8015 as_Register($src1$$reg),
8016 (int32_t)($src2$$constant));
8017 %}
8018
8019 ins_pipe(ialu_reg_imm);
8020 %}
8021
8022 // Register And Long
8023 instruct andL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
8024 match(Set dst (AndL src1 src2));
8025
8026 format %{ "andr $dst, $src1, $src2\t#@andL_reg_reg" %}
8027
8028 ins_cost(ALU_COST);
8029 ins_encode %{
8030 __ andr(as_Register($dst$$reg),
8031 as_Register($src1$$reg),
8032 as_Register($src2$$reg));
8033 %}
8034
8035 ins_pipe(ialu_reg_reg);
8036 %}
8037
8038 // Immediate And Long
8039 instruct andL_reg_imm(iRegLNoSp dst, iRegL src1, immLAdd src2) %{
8040 match(Set dst (AndL src1 src2));
8041
8042 format %{ "andi $dst, $src1, $src2\t#@andL_reg_imm" %}
8043
8044 ins_cost(ALU_COST);
8045 ins_encode %{
8046 __ andi(as_Register($dst$$reg),
8047 as_Register($src1$$reg),
8048 (int32_t)($src2$$constant));
8049 %}
8050
8051 ins_pipe(ialu_reg_imm);
8052 %}
8053
8054 // Register Or Long
8055 instruct orL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
8056 match(Set dst (OrL src1 src2));
8057
8058 format %{ "orr $dst, $src1, $src2\t#@orL_reg_reg" %}
8059
8060 ins_cost(ALU_COST);
8061 ins_encode %{
8062 __ orr(as_Register($dst$$reg),
8063 as_Register($src1$$reg),
8064 as_Register($src2$$reg));
8065 %}
8066
8067 ins_pipe(ialu_reg_reg);
8068 %}
8069
8070 // Immediate Or Long
8071 instruct orL_reg_imm(iRegLNoSp dst, iRegL src1, immLAdd src2) %{
8072 match(Set dst (OrL src1 src2));
8073
8074 format %{ "ori $dst, $src1, $src2\t#@orL_reg_imm" %}
8075
8076 ins_cost(ALU_COST);
8077 ins_encode %{
8078 __ ori(as_Register($dst$$reg),
8079 as_Register($src1$$reg),
8080 (int32_t)($src2$$constant));
8081 %}
8082
8083 ins_pipe(ialu_reg_imm);
8084 %}
8085
8086 // Register Xor Long
8087 instruct xorL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
8088 match(Set dst (XorL src1 src2));
8089
8090 format %{ "xorr $dst, $src1, $src2\t#@xorL_reg_reg" %}
8091
8092 ins_cost(ALU_COST);
8093 ins_encode %{
8094 __ xorr(as_Register($dst$$reg),
8095 as_Register($src1$$reg),
8096 as_Register($src2$$reg));
8097 %}
8098
8099 ins_pipe(ialu_reg_reg);
8100 %}
8101
8102 // Immediate Xor Long
8103 instruct xorL_reg_imm(iRegLNoSp dst, iRegL src1, immLAdd src2) %{
8104 match(Set dst (XorL src1 src2));
8105
8106 ins_cost(ALU_COST);
8107 format %{ "xori $dst, $src1, $src2\t#@xorL_reg_imm" %}
8108
8109 ins_encode %{
8110 __ xori(as_Register($dst$$reg),
8111 as_Register($src1$$reg),
8112 (int32_t)($src2$$constant));
8113 %}
8114
8115 ins_pipe(ialu_reg_imm);
8116 %}
8117
8118 // ============================================================================
8119 // MemBar Instruction
8120
8121 // RVTSO
8122
8123 instruct unnecessary_membar_rvtso() %{
8124 predicate(UseZtso);
8125 match(LoadFence);
8126 match(StoreFence);
8127 match(StoreStoreFence);
8128 match(MemBarAcquire);
8129 match(MemBarRelease);
8130 match(MemBarStoreStore);
8131 match(MemBarAcquireLock);
8132 match(MemBarReleaseLock);
8133
8134 ins_cost(0);
8135
8136 size(0);
8137
8138 format %{ "#@unnecessary_membar_rvtso elided/tso (empty encoding)" %}
8139 ins_encode %{
8140 __ block_comment("unnecessary_membar_rvtso");
8141 %}
8142 ins_pipe(real_empty);
8143 %}
8144
8145 instruct membar_storeload_rvtso() %{
8146 predicate(UseZtso);
8147 match(MemBarStoreLoad);
8148 ins_cost(VOLATILE_REF_COST);
8149
8150 format %{ "#@membar_storeload_rvtso\n\t"
8151 "fence w, r"%}
8152
8153 ins_encode %{
8154 __ block_comment("membar_storeload_rvtso");
8155 __ membar(MacroAssembler::StoreLoad);
8156 %}
8157
8158 ins_pipe(pipe_slow);
8159 %}
8160
8161 instruct membar_volatile_rvtso() %{
8162 predicate(UseZtso);
8163 match(MemBarVolatile);
8164 ins_cost(VOLATILE_REF_COST);
8165
8166 format %{ "#@membar_volatile_rvtso\n\t"
8167 "fence w, r"%}
8168
8169 ins_encode %{
8170 __ block_comment("membar_volatile_rvtso");
8171 __ membar(MacroAssembler::StoreLoad);
8172 %}
8173
8174 ins_pipe(pipe_slow);
8175 %}
8176
8177 instruct unnecessary_membar_volatile_rvtso() %{
8178 predicate(UseZtso && Matcher::post_store_load_barrier(n));
8179 match(MemBarVolatile);
8180 ins_cost(0);
8181
8182 size(0);
8183
8184 format %{ "#@unnecessary_membar_volatile_rvtso (unnecessary so empty encoding)" %}
8185 ins_encode %{
8186 __ block_comment("unnecessary_membar_volatile_rvtso");
8187 %}
8188 ins_pipe(real_empty);
8189 %}
8190
8191 instruct membar_full_rvtso() %{
8192 predicate(UseZtso);
8193 match(MemBarFull);
8194 ins_cost(VOLATILE_REF_COST);
8195
8196 format %{ "#@membar_full_rvtso\n\t"
8197 "fence rw, rw" %}
8198
8199 ins_encode %{
8200 __ block_comment("membar_full_rvtso");
8201 __ membar(MacroAssembler::AnyAny);
8202 %}
8203
8204 ins_pipe(pipe_slow);
8205 %}
8206
8207 // RVWMO
8208
8209 instruct membar_aqcuire_rvwmo() %{
8210 predicate(!UseZtso);
8211 match(LoadFence);
8212 match(MemBarAcquire);
8213 ins_cost(VOLATILE_REF_COST);
8214
8215 format %{ "#@membar_aqcuire_rvwmo\n\t"
8216 "fence r, rw" %}
8217
8218 ins_encode %{
8219 __ block_comment("membar_aqcuire_rvwmo");
8220 __ membar(MacroAssembler::LoadLoad | MacroAssembler::LoadStore);
8221 %}
8222 ins_pipe(pipe_serial);
8223 %}
8224
8225 instruct membar_release_rvwmo() %{
8226 predicate(!UseZtso);
8227 match(StoreFence);
8228 match(MemBarRelease);
8229 ins_cost(VOLATILE_REF_COST);
8230
8231 format %{ "#@membar_release_rvwmo\n\t"
8232 "fence rw, w" %}
8233
8234 ins_encode %{
8235 __ block_comment("membar_release_rvwmo");
8236 __ membar(MacroAssembler::LoadStore | MacroAssembler::StoreStore);
8237 %}
8238 ins_pipe(pipe_serial);
8239 %}
8240
8241 instruct membar_storestore_rvwmo() %{
8242 predicate(!UseZtso);
8243 match(MemBarStoreStore);
8244 match(StoreStoreFence);
8245 ins_cost(VOLATILE_REF_COST);
8246
8247 format %{ "#@membar_storestore_rvwmo\n\t"
8248 "fence w, w" %}
8249
8250 ins_encode %{
8251 __ membar(MacroAssembler::StoreStore);
8252 %}
8253 ins_pipe(pipe_serial);
8254 %}
8255
8256 instruct membar_storeload_rvwmo() %{
8257 predicate(!UseZtso);
8258 match(MemBarStoreLoad);
8259 ins_cost(VOLATILE_REF_COST);
8260
8261 format %{ "#@membar_storeload_rvwmo\n\t"
8262 "fence w, r"%}
8263
8264 ins_encode %{
8265 __ block_comment("membar_storeload_rvwmo");
8266 __ membar(MacroAssembler::StoreLoad);
8267 %}
8268
8269 ins_pipe(pipe_serial);
8270 %}
8271
8272 instruct membar_volatile_rvwmo() %{
8273 predicate(!UseZtso);
8274 match(MemBarVolatile);
8275 ins_cost(VOLATILE_REF_COST);
8276
8277 format %{ "#@membar_volatile_rvwmo\n\t"
8278 "fence w, r"%}
8279
8280 ins_encode %{
8281 __ block_comment("membar_volatile_rvwmo");
8282 __ membar(MacroAssembler::StoreLoad);
8283 %}
8284
8285 ins_pipe(pipe_serial);
8286 %}
8287
8288 instruct membar_lock_rvwmo() %{
8289 predicate(!UseZtso);
8290 match(MemBarAcquireLock);
8291 match(MemBarReleaseLock);
8292 ins_cost(0);
8293
8294 format %{ "#@membar_lock_rvwmo (elided)" %}
8295
8296 ins_encode %{
8297 __ block_comment("membar_lock_rvwmo (elided)");
8298 %}
8299
8300 ins_pipe(pipe_serial);
8301 %}
8302
8303 instruct unnecessary_membar_volatile_rvwmo() %{
8304 predicate(!UseZtso && Matcher::post_store_load_barrier(n));
8305 match(MemBarVolatile);
8306 ins_cost(0);
8307
8308 size(0);
8309 format %{ "#@unnecessary_membar_volatile_rvwmo (unnecessary so empty encoding)" %}
8310 ins_encode %{
8311 __ block_comment("unnecessary_membar_volatile_rvwmo");
8312 %}
8313 ins_pipe(real_empty);
8314 %}
8315
8316 instruct membar_full_rvwmo() %{
8317 predicate(!UseZtso);
8318 match(MemBarFull);
8319 ins_cost(VOLATILE_REF_COST);
8320
8321 format %{ "#@membar_full_rvwmo\n\t"
8322 "fence rw, rw" %}
8323
8324 ins_encode %{
8325 __ block_comment("membar_full_rvwmo");
8326 __ membar(MacroAssembler::AnyAny);
8327 %}
8328
8329 ins_pipe(pipe_serial);
8330 %}
8331
8332 instruct spin_wait() %{
8333 predicate(UseZihintpause);
8334 match(OnSpinWait);
8335 ins_cost(CACHE_MISS_COST);
8336
8337 format %{ "spin_wait" %}
8338
8339 ins_encode %{
8340 __ pause();
8341 %}
8342
8343 ins_pipe(pipe_serial);
8344 %}
8345
8346 // ============================================================================
8347 // Cast Instructions (Java-level type cast)
8348
8349 instruct castX2P(iRegPNoSp dst, iRegL src) %{
8350 match(Set dst (CastX2P src));
8351
8352 ins_cost(ALU_COST);
8353 format %{ "mv $dst, $src\t# long -> ptr, #@castX2P" %}
8354
8355 ins_encode %{
8356 if ($dst$$reg != $src$$reg) {
8357 __ mv(as_Register($dst$$reg), as_Register($src$$reg));
8358 }
8359 %}
8360
8361 ins_pipe(ialu_reg);
8362 %}
8363
8364 instruct castP2X(iRegLNoSp dst, iRegP src) %{
8365 match(Set dst (CastP2X src));
8366
8367 ins_cost(ALU_COST);
8368 format %{ "mv $dst, $src\t# ptr -> long, #@castP2X" %}
8369
8370 ins_encode %{
8371 if ($dst$$reg != $src$$reg) {
8372 __ mv(as_Register($dst$$reg), as_Register($src$$reg));
8373 }
8374 %}
8375
8376 ins_pipe(ialu_reg);
8377 %}
8378
8379 instruct castPP(iRegPNoSp dst)
8380 %{
8381 match(Set dst (CastPP dst));
8382 ins_cost(0);
8383
8384 size(0);
8385 format %{ "# castPP of $dst, #@castPP" %}
8386 ins_encode(/* empty encoding */);
8387 ins_pipe(pipe_class_empty);
8388 %}
8389
8390 instruct castLL(iRegL dst)
8391 %{
8392 match(Set dst (CastLL dst));
8393
8394 size(0);
8395 format %{ "# castLL of $dst, #@castLL" %}
8396 ins_encode(/* empty encoding */);
8397 ins_cost(0);
8398 ins_pipe(pipe_class_empty);
8399 %}
8400
8401 instruct castII(iRegI dst)
8402 %{
8403 match(Set dst (CastII dst));
8404
8405 size(0);
8406 format %{ "# castII of $dst, #@castII" %}
8407 ins_encode(/* empty encoding */);
8408 ins_cost(0);
8409 ins_pipe(pipe_class_empty);
8410 %}
8411
8412 instruct checkCastPP(iRegPNoSp dst)
8413 %{
8414 match(Set dst (CheckCastPP dst));
8415
8416 size(0);
8417 ins_cost(0);
8418 format %{ "# checkcastPP of $dst, #@checkCastPP" %}
8419 ins_encode(/* empty encoding */);
8420 ins_pipe(pipe_class_empty);
8421 %}
8422
8423 instruct castHH(fRegF dst)
8424 %{
8425 match(Set dst (CastHH dst));
8426
8427 size(0);
8428 format %{ "# castHH of $dst" %}
8429 ins_encode(/* empty encoding */);
8430 ins_cost(0);
8431 ins_pipe(pipe_class_empty);
8432 %}
8433
8434 instruct castFF(fRegF dst)
8435 %{
8436 match(Set dst (CastFF dst));
8437
8438 size(0);
8439 format %{ "# castFF of $dst" %}
8440 ins_encode(/* empty encoding */);
8441 ins_cost(0);
8442 ins_pipe(pipe_class_empty);
8443 %}
8444
8445 instruct castDD(fRegD dst)
8446 %{
8447 match(Set dst (CastDD dst));
8448
8449 size(0);
8450 format %{ "# castDD of $dst" %}
8451 ins_encode(/* empty encoding */);
8452 ins_cost(0);
8453 ins_pipe(pipe_class_empty);
8454 %}
8455
8456 instruct castVV(vReg dst)
8457 %{
8458 match(Set dst (CastVV dst));
8459
8460 size(0);
8461 format %{ "# castVV of $dst" %}
8462 ins_encode(/* empty encoding */);
8463 ins_cost(0);
8464 ins_pipe(pipe_class_empty);
8465 %}
8466
8467 instruct castVVMask(vRegMask dst)
8468 %{
8469 match(Set dst (CastVV dst));
8470
8471 size(0);
8472 format %{ "# castVV of $dst" %}
8473 ins_encode(/* empty encoding */);
8474 ins_cost(0);
8475 ins_pipe(pipe_class_empty);
8476 %}
8477
8478 // ============================================================================
8479 // Convert Instructions
8480
8481 // int to bool
8482 instruct convI2Bool(iRegINoSp dst, iRegI src)
8483 %{
8484 match(Set dst (Conv2B src));
8485
8486 ins_cost(ALU_COST);
8487 format %{ "snez $dst, $src\t#@convI2Bool" %}
8488
8489 ins_encode %{
8490 __ snez(as_Register($dst$$reg), as_Register($src$$reg));
8491 %}
8492
8493 ins_pipe(ialu_reg);
8494 %}
8495
8496 // pointer to bool
8497 instruct convP2Bool(iRegINoSp dst, iRegP src)
8498 %{
8499 match(Set dst (Conv2B src));
8500
8501 ins_cost(ALU_COST);
8502 format %{ "snez $dst, $src\t#@convP2Bool" %}
8503
8504 ins_encode %{
8505 __ snez(as_Register($dst$$reg), as_Register($src$$reg));
8506 %}
8507
8508 ins_pipe(ialu_reg);
8509 %}
8510
8511 // int <-> long
8512
8513 instruct convI2L_reg_reg(iRegLNoSp dst, iRegIorL2I src)
8514 %{
8515 match(Set dst (ConvI2L src));
8516
8517 ins_cost(ALU_COST);
8518 format %{ "addw $dst, $src, zr\t#@convI2L_reg_reg" %}
8519 ins_encode %{
8520 __ sext(as_Register($dst$$reg), as_Register($src$$reg), 32);
8521 %}
8522 ins_pipe(ialu_reg);
8523 %}
8524
8525 instruct convL2I_reg(iRegINoSp dst, iRegL src) %{
8526 match(Set dst (ConvL2I src));
8527
8528 ins_cost(ALU_COST);
8529 format %{ "addw $dst, $src, zr\t#@convL2I_reg" %}
8530
8531 ins_encode %{
8532 __ sext(as_Register($dst$$reg), as_Register($src$$reg), 32);
8533 %}
8534
8535 ins_pipe(ialu_reg);
8536 %}
8537
8538 // int to unsigned long (Zero-extend)
8539 instruct convI2UL_reg_reg(iRegLNoSp dst, iRegIorL2I src, immL_32bits mask)
8540 %{
8541 match(Set dst (AndL (ConvI2L src) mask));
8542
8543 ins_cost(ALU_COST * 2);
8544 format %{ "zext $dst, $src, 32\t# i2ul, #@convI2UL_reg_reg" %}
8545
8546 ins_encode %{
8547 __ zext(as_Register($dst$$reg), as_Register($src$$reg), 32);
8548 %}
8549
8550 ins_pipe(ialu_reg_shift);
8551 %}
8552
8553 // float <-> double
8554
8555 instruct convF2D_reg(fRegD dst, fRegF src) %{
8556 match(Set dst (ConvF2D src));
8557
8558 ins_cost(XFER_COST);
8559 format %{ "fcvt.d.s $dst, $src\t#@convF2D_reg" %}
8560
8561 ins_encode %{
8562 __ fcvt_d_s(as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg));
8563 %}
8564
8565 ins_pipe(fp_f2d);
8566 %}
8567
8568 instruct convD2F_reg(fRegF dst, fRegD src) %{
8569 match(Set dst (ConvD2F src));
8570
8571 ins_cost(XFER_COST);
8572 format %{ "fcvt.s.d $dst, $src\t#@convD2F_reg" %}
8573
8574 ins_encode %{
8575 __ fcvt_s_d(as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg));
8576 %}
8577
8578 ins_pipe(fp_d2f);
8579 %}
8580
8581 // single <-> half precision
8582
8583 instruct convHF2F_reg_reg(fRegF dst, iRegIorL2I src, iRegINoSp tmp) %{
8584 match(Set dst (ConvHF2F src));
8585 effect(TEMP tmp);
8586 format %{ "fmv.h.x $dst, $src\t# move source from $src to $dst\n\t"
8587 "fcvt.s.h $dst, $dst\t# convert half to single precision"
8588 %}
8589 ins_encode %{
8590 __ float16_to_float($dst$$FloatRegister, $src$$Register, $tmp$$Register);
8591 %}
8592 ins_pipe(pipe_slow);
8593 %}
8594
8595 instruct convF2HF_reg_reg(iRegINoSp dst, fRegF src, fRegF ftmp, iRegINoSp xtmp) %{
8596 match(Set dst (ConvF2HF src));
8597 effect(TEMP_DEF dst, TEMP ftmp, TEMP xtmp);
8598 format %{ "fcvt.h.s $ftmp, $src\t# convert single precision to half\n\t"
8599 "fmv.x.h $dst, $ftmp\t# move result from $ftmp to $dst"
8600 %}
8601 ins_encode %{
8602 __ float_to_float16($dst$$Register, $src$$FloatRegister, $ftmp$$FloatRegister, $xtmp$$Register);
8603 %}
8604 ins_pipe(pipe_slow);
8605 %}
8606
8607 // half precision operations
8608
8609 instruct reinterpretS2HF(fRegF dst, iRegI src)
8610 %{
8611 match(Set dst (ReinterpretS2HF src));
8612 format %{ "fmv.h.x $dst, $src\t# reinterpretS2HF" %}
8613 ins_encode %{
8614 __ fmv_h_x($dst$$FloatRegister, $src$$Register);
8615 %}
8616 ins_pipe(fp_i2f);
8617 %}
8618
8619 instruct convF2HFAndS2HF(fRegF dst, fRegF src)
8620 %{
8621 match(Set dst (ReinterpretS2HF (ConvF2HF src)));
8622 format %{ "convF2HFAndS2HF $dst, $src" %}
8623 ins_encode %{
8624 __ fcvt_h_s($dst$$FloatRegister, $src$$FloatRegister);
8625 %}
8626 ins_pipe(fp_uop_s);
8627 %}
8628
8629 instruct reinterpretHF2S(iRegINoSp dst, fRegF src)
8630 %{
8631 match(Set dst (ReinterpretHF2S src));
8632 format %{ "fmv.x.h $dst, $src\t# reinterpretHF2S" %}
8633 ins_encode %{
8634 __ fmv_x_h($dst$$Register, $src$$FloatRegister);
8635 %}
8636 ins_pipe(fp_f2i);
8637 %}
8638
8639 instruct convHF2SAndHF2F(fRegF dst, fRegF src)
8640 %{
8641 match(Set dst (ConvHF2F (ReinterpretHF2S src)));
8642 format %{ "convHF2SAndHF2F $dst, $src" %}
8643 ins_encode %{
8644 __ fcvt_s_h($dst$$FloatRegister, $src$$FloatRegister);
8645 %}
8646 ins_pipe(fp_uop_s);
8647 %}
8648
8649 instruct sqrt_HF_reg(fRegF dst, fRegF src)
8650 %{
8651 match(Set dst (SqrtHF src));
8652 format %{ "fsqrt.h $dst, $src" %}
8653 ins_encode %{
8654 __ fsqrt_h($dst$$FloatRegister, $src$$FloatRegister);
8655 %}
8656 ins_pipe(fp_sqrt_s);
8657 %}
8658
8659 instruct binOps_HF_reg(fRegF dst, fRegF src1, fRegF src2)
8660 %{
8661 match(Set dst (AddHF src1 src2));
8662 match(Set dst (SubHF src1 src2));
8663 match(Set dst (MulHF src1 src2));
8664 match(Set dst (DivHF src1 src2));
8665 format %{ "binop_hf $dst, $src1, $src2" %}
8666 ins_encode %{
8667 int opcode = this->ideal_Opcode();
8668 switch(opcode) {
8669 case Op_AddHF: __ fadd_h($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); break;
8670 case Op_SubHF: __ fsub_h($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); break;
8671 case Op_MulHF: __ fmul_h($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); break;
8672 case Op_DivHF: __ fdiv_h($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); break;
8673 default: assert(false, "%s is not supported here", NodeClassNames[opcode]); break;
8674 }
8675 %}
8676 ins_pipe(fp_dop_reg_reg_s);
8677 %}
8678
8679 instruct min_HF_reg(fRegF dst, fRegF src1, fRegF src2, rFlagsReg cr)
8680 %{
8681 predicate(!UseZfa);
8682 match(Set dst (MinHF src1 src2));
8683 effect(KILL cr);
8684
8685 format %{ "min_hf $dst, $src1, $src2" %}
8686
8687 ins_encode %{
8688 __ minmax_fp($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister,
8689 __ FLOAT_TYPE::half_precision, true /* is_min */);
8690 %}
8691 ins_pipe(pipe_class_default);
8692 %}
8693
8694 instruct min_HF_reg_zfa(fRegF dst, fRegF src1, fRegF src2)
8695 %{
8696 predicate(UseZfa);
8697 match(Set dst (MinHF src1 src2));
8698
8699 format %{ "min_hf $dst, $src1, $src2" %}
8700
8701 ins_encode %{
8702 __ fminm_h(as_FloatRegister($dst$$reg),
8703 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
8704 %}
8705
8706 ins_pipe(pipe_class_default);
8707 %}
8708
8709 instruct max_HF_reg(fRegF dst, fRegF src1, fRegF src2, rFlagsReg cr)
8710 %{
8711 predicate(!UseZfa);
8712 match(Set dst (MaxHF src1 src2));
8713 effect(KILL cr);
8714
8715 format %{ "max_hf $dst, $src1, $src2" %}
8716
8717 ins_encode %{
8718 __ minmax_fp($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister,
8719 __ FLOAT_TYPE::half_precision, false /* is_min */);
8720 %}
8721 ins_pipe(pipe_class_default);
8722 %}
8723
8724 instruct max_HF_reg_zfa(fRegF dst, fRegF src1, fRegF src2)
8725 %{
8726 predicate(UseZfa);
8727 match(Set dst (MaxHF src1 src2));
8728
8729 format %{ "max_hf $dst, $src1, $src2" %}
8730
8731 ins_encode %{
8732 __ fmaxm_h(as_FloatRegister($dst$$reg),
8733 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
8734 %}
8735
8736 ins_pipe(pipe_class_default);
8737 %}
8738
8739 instruct fma_HF_reg(fRegF dst, fRegF src1, fRegF src2, fRegF src3)
8740 %{
8741 match(Set dst (FmaHF src3 (Binary src1 src2)));
8742 format %{ "fmadd.h $dst, $src1, $src2, $src3\t# $dst = $src1 * $src2 + $src3 fma packedH" %}
8743 ins_encode %{
8744 __ fmadd_h($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister, $src3$$FloatRegister);
8745 %}
8746 ins_pipe(pipe_class_default);
8747 %}
8748
8749 // float <-> int
8750
8751 instruct convF2I_reg_reg(iRegINoSp dst, fRegF src) %{
8752 match(Set dst (ConvF2I src));
8753
8754 ins_cost(XFER_COST);
8755 format %{ "fcvt.w.s $dst, $src\t#@convF2I_reg_reg" %}
8756
8757 ins_encode %{
8758 __ fcvt_w_s_safe($dst$$Register, $src$$FloatRegister);
8759 %}
8760
8761 ins_pipe(fp_f2i);
8762 %}
8763
8764 instruct convI2F_reg_reg(fRegF dst, iRegIorL2I src) %{
8765 match(Set dst (ConvI2F src));
8766
8767 ins_cost(XFER_COST);
8768 format %{ "fcvt.s.w $dst, $src\t#@convI2F_reg_reg" %}
8769
8770 ins_encode %{
8771 __ fcvt_s_w(as_FloatRegister($dst$$reg), as_Register($src$$reg));
8772 %}
8773
8774 ins_pipe(fp_i2f);
8775 %}
8776
8777 // float <-> long
8778
8779 instruct convF2L_reg_reg(iRegLNoSp dst, fRegF src) %{
8780 match(Set dst (ConvF2L src));
8781
8782 ins_cost(XFER_COST);
8783 format %{ "fcvt.l.s $dst, $src\t#@convF2L_reg_reg" %}
8784
8785 ins_encode %{
8786 __ fcvt_l_s_safe($dst$$Register, $src$$FloatRegister);
8787 %}
8788
8789 ins_pipe(fp_f2l);
8790 %}
8791
8792 instruct convL2F_reg_reg(fRegF dst, iRegL src) %{
8793 match(Set dst (ConvL2F src));
8794
8795 ins_cost(XFER_COST);
8796 format %{ "fcvt.s.l $dst, $src\t#@convL2F_reg_reg" %}
8797
8798 ins_encode %{
8799 __ fcvt_s_l(as_FloatRegister($dst$$reg), as_Register($src$$reg));
8800 %}
8801
8802 ins_pipe(fp_l2f);
8803 %}
8804
8805 // double <-> int
8806
8807 instruct convD2I_reg_reg(iRegINoSp dst, fRegD src) %{
8808 match(Set dst (ConvD2I src));
8809
8810 ins_cost(XFER_COST);
8811 format %{ "fcvt.w.d $dst, $src\t#@convD2I_reg_reg" %}
8812
8813 ins_encode %{
8814 __ fcvt_w_d_safe($dst$$Register, $src$$FloatRegister);
8815 %}
8816
8817 ins_pipe(fp_d2i);
8818 %}
8819
8820 instruct convI2D_reg_reg(fRegD dst, iRegIorL2I src) %{
8821 match(Set dst (ConvI2D src));
8822
8823 ins_cost(XFER_COST);
8824 format %{ "fcvt.d.w $dst, $src\t#@convI2D_reg_reg" %}
8825
8826 ins_encode %{
8827 __ fcvt_d_w(as_FloatRegister($dst$$reg), as_Register($src$$reg));
8828 %}
8829
8830 ins_pipe(fp_i2d);
8831 %}
8832
8833 // double <-> long
8834
8835 instruct convD2L_reg_reg(iRegLNoSp dst, fRegD src) %{
8836 match(Set dst (ConvD2L src));
8837
8838 ins_cost(XFER_COST);
8839 format %{ "fcvt.l.d $dst, $src\t#@convD2L_reg_reg" %}
8840
8841 ins_encode %{
8842 __ fcvt_l_d_safe($dst$$Register, $src$$FloatRegister);
8843 %}
8844
8845 ins_pipe(fp_d2l);
8846 %}
8847
8848 instruct convL2D_reg_reg(fRegD dst, iRegL src) %{
8849 match(Set dst (ConvL2D src));
8850
8851 ins_cost(XFER_COST);
8852 format %{ "fcvt.d.l $dst, $src\t#@convL2D_reg_reg" %}
8853
8854 ins_encode %{
8855 __ fcvt_d_l(as_FloatRegister($dst$$reg), as_Register($src$$reg));
8856 %}
8857
8858 ins_pipe(fp_l2d);
8859 %}
8860
8861 // Convert oop into int for vectors alignment masking
8862 instruct convP2I(iRegINoSp dst, iRegP src) %{
8863 match(Set dst (ConvL2I (CastP2X src)));
8864
8865 ins_cost(ALU_COST * 2);
8866 format %{ "zext $dst, $src, 32\t# ptr -> int, #@convP2I" %}
8867
8868 ins_encode %{
8869 __ zext($dst$$Register, $src$$Register, 32);
8870 %}
8871
8872 ins_pipe(ialu_reg);
8873 %}
8874
8875 // Convert compressed oop into int for vectors alignment masking
8876 // in case of 32bit oops (heap < 4Gb).
8877 instruct convN2I(iRegINoSp dst, iRegN src)
8878 %{
8879 predicate(CompressedOops::shift() == 0);
8880 match(Set dst (ConvL2I (CastP2X (DecodeN src))));
8881
8882 ins_cost(ALU_COST);
8883 format %{ "mv $dst, $src\t# compressed ptr -> int, #@convN2I" %}
8884
8885 ins_encode %{
8886 __ mv($dst$$Register, $src$$Register);
8887 %}
8888
8889 ins_pipe(ialu_reg);
8890 %}
8891
8892 instruct round_double_reg(iRegLNoSp dst, fRegD src, fRegD ftmp) %{
8893 match(Set dst (RoundD src));
8894
8895 ins_cost(XFER_COST + BRANCH_COST);
8896 effect(TEMP ftmp);
8897 format %{ "java_round_double $dst, $src\t#@round_double_reg" %}
8898
8899 ins_encode %{
8900 __ java_round_double($dst$$Register, as_FloatRegister($src$$reg), as_FloatRegister($ftmp$$reg));
8901 %}
8902
8903 ins_pipe(pipe_slow);
8904 %}
8905
8906 instruct round_float_reg(iRegINoSp dst, fRegF src, fRegF ftmp) %{
8907 match(Set dst (RoundF src));
8908
8909 ins_cost(XFER_COST + BRANCH_COST);
8910 effect(TEMP ftmp);
8911 format %{ "java_round_float $dst, $src\t#@round_float_reg" %}
8912
8913 ins_encode %{
8914 __ java_round_float($dst$$Register, as_FloatRegister($src$$reg), as_FloatRegister($ftmp$$reg));
8915 %}
8916
8917 ins_pipe(pipe_slow);
8918 %}
8919
8920 // Convert oop pointer into compressed form
8921 instruct encodeHeapOop(iRegNNoSp dst, iRegP src) %{
8922 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
8923 match(Set dst (EncodeP src));
8924 ins_cost(ALU_COST);
8925 format %{ "encode_heap_oop $dst, $src\t#@encodeHeapOop" %}
8926 ins_encode %{
8927 Register s = $src$$Register;
8928 Register d = $dst$$Register;
8929 __ encode_heap_oop(d, s);
8930 %}
8931 ins_pipe(pipe_class_default);
8932 %}
8933
8934 instruct encodeHeapOop_not_null(iRegNNoSp dst, iRegP src) %{
8935 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
8936 match(Set dst (EncodeP src));
8937 ins_cost(ALU_COST);
8938 format %{ "encode_heap_oop_not_null $dst, $src\t#@encodeHeapOop_not_null" %}
8939 ins_encode %{
8940 __ encode_heap_oop_not_null($dst$$Register, $src$$Register);
8941 %}
8942 ins_pipe(pipe_class_default);
8943 %}
8944
8945 instruct decodeHeapOop(iRegPNoSp dst, iRegN src) %{
8946 predicate(n->bottom_type()->is_ptr()->ptr() != TypePtr::NotNull &&
8947 n->bottom_type()->is_ptr()->ptr() != TypePtr::Constant);
8948 match(Set dst (DecodeN src));
8949
8950 ins_cost(0);
8951 format %{ "decode_heap_oop $dst, $src\t#@decodeHeapOop" %}
8952 ins_encode %{
8953 Register s = $src$$Register;
8954 Register d = $dst$$Register;
8955 __ decode_heap_oop(d, s);
8956 %}
8957 ins_pipe(pipe_class_default);
8958 %}
8959
8960 instruct decodeHeapOop_not_null(iRegPNoSp dst, iRegN src) %{
8961 predicate(n->bottom_type()->is_ptr()->ptr() == TypePtr::NotNull ||
8962 n->bottom_type()->is_ptr()->ptr() == TypePtr::Constant);
8963 match(Set dst (DecodeN src));
8964
8965 ins_cost(0);
8966 format %{ "decode_heap_oop_not_null $dst, $src\t#@decodeHeapOop_not_null" %}
8967 ins_encode %{
8968 Register s = $src$$Register;
8969 Register d = $dst$$Register;
8970 __ decode_heap_oop_not_null(d, s);
8971 %}
8972 ins_pipe(pipe_class_default);
8973 %}
8974
8975 // Convert klass pointer into compressed form.
8976 instruct encodeKlass_not_null(iRegNNoSp dst, iRegP src) %{
8977 match(Set dst (EncodePKlass src));
8978
8979 ins_cost(ALU_COST);
8980 format %{ "encode_klass_not_null $dst, $src\t#@encodeKlass_not_null" %}
8981
8982 ins_encode %{
8983 Register src_reg = as_Register($src$$reg);
8984 Register dst_reg = as_Register($dst$$reg);
8985 __ encode_klass_not_null(dst_reg, src_reg, t0);
8986 %}
8987
8988 ins_pipe(pipe_class_default);
8989 %}
8990
8991 instruct decodeKlass_not_null(iRegPNoSp dst, iRegN src, iRegPNoSp tmp) %{
8992 match(Set dst (DecodeNKlass src));
8993
8994 effect(TEMP_DEF dst, TEMP tmp);
8995
8996 ins_cost(ALU_COST);
8997 format %{ "decode_klass_not_null $dst, $src\t#@decodeKlass_not_null" %}
8998
8999 ins_encode %{
9000 Register src_reg = as_Register($src$$reg);
9001 Register dst_reg = as_Register($dst$$reg);
9002 Register tmp_reg = as_Register($tmp$$reg);
9003 __ decode_klass_not_null(dst_reg, src_reg, tmp_reg);
9004 %}
9005
9006 ins_pipe(pipe_class_default);
9007 %}
9008
9009 // stack <-> reg and reg <-> reg shuffles with no conversion
9010
9011 instruct MoveF2I_stack_reg(iRegINoSp dst, stackSlotF src) %{
9012
9013 match(Set dst (MoveF2I src));
9014
9015 effect(DEF dst, USE src);
9016
9017 ins_cost(LOAD_COST);
9018
9019 format %{ "lw $dst, $src\t#@MoveF2I_stack_reg" %}
9020
9021 ins_encode %{
9022 __ lw(as_Register($dst$$reg), Address(sp, $src$$disp));
9023 %}
9024
9025 ins_pipe(iload_reg_reg);
9026
9027 %}
9028
9029 instruct MoveI2F_stack_reg(fRegF dst, stackSlotI src) %{
9030
9031 match(Set dst (MoveI2F src));
9032
9033 effect(DEF dst, USE src);
9034
9035 ins_cost(LOAD_COST);
9036
9037 format %{ "flw $dst, $src\t#@MoveI2F_stack_reg" %}
9038
9039 ins_encode %{
9040 __ flw(as_FloatRegister($dst$$reg), Address(sp, $src$$disp));
9041 %}
9042
9043 ins_pipe(fp_load_mem_s);
9044
9045 %}
9046
9047 instruct MoveD2L_stack_reg(iRegLNoSp dst, stackSlotD src) %{
9048
9049 match(Set dst (MoveD2L src));
9050
9051 effect(DEF dst, USE src);
9052
9053 ins_cost(LOAD_COST);
9054
9055 format %{ "ld $dst, $src\t#@MoveD2L_stack_reg" %}
9056
9057 ins_encode %{
9058 __ ld(as_Register($dst$$reg), Address(sp, $src$$disp));
9059 %}
9060
9061 ins_pipe(iload_reg_reg);
9062
9063 %}
9064
9065 instruct MoveL2D_stack_reg(fRegD dst, stackSlotL src) %{
9066
9067 match(Set dst (MoveL2D src));
9068
9069 effect(DEF dst, USE src);
9070
9071 ins_cost(LOAD_COST);
9072
9073 format %{ "fld $dst, $src\t#@MoveL2D_stack_reg" %}
9074
9075 ins_encode %{
9076 __ fld(as_FloatRegister($dst$$reg), Address(sp, $src$$disp));
9077 %}
9078
9079 ins_pipe(fp_load_mem_d);
9080
9081 %}
9082
9083 instruct MoveF2I_reg_stack(stackSlotI dst, fRegF src) %{
9084
9085 match(Set dst (MoveF2I src));
9086
9087 effect(DEF dst, USE src);
9088
9089 ins_cost(STORE_COST);
9090
9091 format %{ "fsw $src, $dst\t#@MoveF2I_reg_stack" %}
9092
9093 ins_encode %{
9094 __ fsw(as_FloatRegister($src$$reg), Address(sp, $dst$$disp));
9095 %}
9096
9097 ins_pipe(fp_store_reg_s);
9098
9099 %}
9100
9101 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{
9102
9103 match(Set dst (MoveI2F src));
9104
9105 effect(DEF dst, USE src);
9106
9107 ins_cost(STORE_COST);
9108
9109 format %{ "sw $src, $dst\t#@MoveI2F_reg_stack" %}
9110
9111 ins_encode %{
9112 __ sw(as_Register($src$$reg), Address(sp, $dst$$disp));
9113 %}
9114
9115 ins_pipe(istore_reg_reg);
9116
9117 %}
9118
9119 instruct MoveD2L_reg_stack(stackSlotL dst, fRegD src) %{
9120
9121 match(Set dst (MoveD2L src));
9122
9123 effect(DEF dst, USE src);
9124
9125 ins_cost(STORE_COST);
9126
9127 format %{ "fsd $dst, $src\t#@MoveD2L_reg_stack" %}
9128
9129 ins_encode %{
9130 __ fsd(as_FloatRegister($src$$reg), Address(sp, $dst$$disp));
9131 %}
9132
9133 ins_pipe(fp_store_reg_d);
9134
9135 %}
9136
9137 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{
9138
9139 match(Set dst (MoveL2D src));
9140
9141 effect(DEF dst, USE src);
9142
9143 ins_cost(STORE_COST);
9144
9145 format %{ "sd $src, $dst\t#@MoveL2D_reg_stack" %}
9146
9147 ins_encode %{
9148 __ sd(as_Register($src$$reg), Address(sp, $dst$$disp));
9149 %}
9150
9151 ins_pipe(istore_reg_reg);
9152
9153 %}
9154
9155 instruct MoveF2I_reg_reg(iRegINoSp dst, fRegF src) %{
9156
9157 match(Set dst (MoveF2I src));
9158
9159 effect(DEF dst, USE src);
9160
9161 ins_cost(FMVX_COST);
9162
9163 format %{ "fmv.x.w $dst, $src\t#@MoveF2I_reg_reg" %}
9164
9165 ins_encode %{
9166 __ fmv_x_w(as_Register($dst$$reg), as_FloatRegister($src$$reg));
9167 %}
9168
9169 ins_pipe(fp_f2i);
9170
9171 %}
9172
9173 instruct MoveI2F_reg_reg(fRegF dst, iRegI src) %{
9174
9175 match(Set dst (MoveI2F src));
9176
9177 effect(DEF dst, USE src);
9178
9179 ins_cost(FMVX_COST);
9180
9181 format %{ "fmv.w.x $dst, $src\t#@MoveI2F_reg_reg" %}
9182
9183 ins_encode %{
9184 __ fmv_w_x(as_FloatRegister($dst$$reg), as_Register($src$$reg));
9185 %}
9186
9187 ins_pipe(fp_i2f);
9188
9189 %}
9190
9191 instruct MoveD2L_reg_reg(iRegLNoSp dst, fRegD src) %{
9192
9193 match(Set dst (MoveD2L src));
9194
9195 effect(DEF dst, USE src);
9196
9197 ins_cost(FMVX_COST);
9198
9199 format %{ "fmv.x.d $dst, $src\t#@MoveD2L_reg_reg" %}
9200
9201 ins_encode %{
9202 __ fmv_x_d(as_Register($dst$$reg), as_FloatRegister($src$$reg));
9203 %}
9204
9205 ins_pipe(fp_d2l);
9206
9207 %}
9208
9209 instruct MoveL2D_reg_reg(fRegD dst, iRegL src) %{
9210
9211 match(Set dst (MoveL2D src));
9212
9213 effect(DEF dst, USE src);
9214
9215 ins_cost(FMVX_COST);
9216
9217 format %{ "fmv.d.x $dst, $src\t#@MoveL2D_reg_reg" %}
9218
9219 ins_encode %{
9220 __ fmv_d_x(as_FloatRegister($dst$$reg), as_Register($src$$reg));
9221 %}
9222
9223 ins_pipe(fp_l2d);
9224
9225 %}
9226
9227 // ============================================================================
9228 // Compare Instructions which set the result float comparisons in dest register.
9229
9230 instruct cmpF3_reg_reg(iRegINoSp dst, fRegF op1, fRegF op2)
9231 %{
9232 match(Set dst (CmpF3 op1 op2));
9233
9234 ins_cost(XFER_COST * 2 + BRANCH_COST + ALU_COST);
9235 format %{ "flt.s $dst, $op2, $op1\t#@cmpF3_reg_reg\n\t"
9236 "bgtz $dst, done\n\t"
9237 "feq.s $dst, $op1, $op2\n\t"
9238 "addi $dst, $dst, -1\n\t"
9239 "done:"
9240 %}
9241
9242 ins_encode %{
9243 // we want -1 for unordered or less than, 0 for equal and 1 for greater than.
9244 __ float_compare(as_Register($dst$$reg), as_FloatRegister($op1$$reg),
9245 as_FloatRegister($op2$$reg), -1 /*unordered_result < 0*/);
9246 %}
9247
9248 ins_pipe(pipe_class_default);
9249 %}
9250
9251 instruct cmpD3_reg_reg(iRegINoSp dst, fRegD op1, fRegD op2)
9252 %{
9253 match(Set dst (CmpD3 op1 op2));
9254
9255 ins_cost(XFER_COST * 2 + BRANCH_COST + ALU_COST);
9256 format %{ "flt.d $dst, $op2, $op1\t#@cmpD3_reg_reg\n\t"
9257 "bgtz $dst, done\n\t"
9258 "feq.d $dst, $op1, $op2\n\t"
9259 "addi $dst, $dst, -1\n\t"
9260 "done:"
9261 %}
9262
9263 ins_encode %{
9264 // we want -1 for unordered or less than, 0 for equal and 1 for greater than.
9265 __ double_compare(as_Register($dst$$reg), as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg), -1 /*unordered_result < 0*/);
9266 %}
9267
9268 ins_pipe(pipe_class_default);
9269 %}
9270
9271 instruct cmpL3_reg_reg(iRegINoSp dst, iRegL op1, iRegL op2)
9272 %{
9273 match(Set dst (CmpL3 op1 op2));
9274
9275 ins_cost(ALU_COST * 3 + BRANCH_COST);
9276 format %{ "slt $dst, $op2, $op1\t#@cmpL3_reg_reg\n\t"
9277 "bnez $dst, done\n\t"
9278 "slt $dst, $op1, $op2\n\t"
9279 "neg $dst, $dst\n\t"
9280 "done:"
9281 %}
9282 ins_encode %{
9283 __ cmp_l2i(t0, as_Register($op1$$reg), as_Register($op2$$reg));
9284 __ mv(as_Register($dst$$reg), t0);
9285 %}
9286
9287 ins_pipe(pipe_class_default);
9288 %}
9289
9290 instruct cmpUL3_reg_reg(iRegINoSp dst, iRegL op1, iRegL op2)
9291 %{
9292 match(Set dst (CmpUL3 op1 op2));
9293
9294 ins_cost(ALU_COST * 3 + BRANCH_COST);
9295 format %{ "sltu $dst, $op2, $op1\t#@cmpUL3_reg_reg\n\t"
9296 "bnez $dst, done\n\t"
9297 "sltu $dst, $op1, $op2\n\t"
9298 "neg $dst, $dst\n\t"
9299 "done:"
9300 %}
9301 ins_encode %{
9302 __ cmp_ul2i(t0, as_Register($op1$$reg), as_Register($op2$$reg));
9303 __ mv(as_Register($dst$$reg), t0);
9304 %}
9305
9306 ins_pipe(pipe_class_default);
9307 %}
9308
9309 instruct cmpU3_reg_reg(iRegINoSp dst, iRegI op1, iRegI op2)
9310 %{
9311 match(Set dst (CmpU3 op1 op2));
9312
9313 ins_cost(ALU_COST * 3 + BRANCH_COST);
9314 format %{ "sltu $dst, $op2, $op1\t#@cmpU3_reg_reg\n\t"
9315 "bnez $dst, done\n\t"
9316 "sltu $dst, $op1, $op2\n\t"
9317 "neg $dst, $dst\n\t"
9318 "done:"
9319 %}
9320 ins_encode %{
9321 __ cmp_uw2i(t0, as_Register($op1$$reg), as_Register($op2$$reg));
9322 __ mv(as_Register($dst$$reg), t0);
9323 %}
9324
9325 ins_pipe(pipe_class_default);
9326 %}
9327
9328 instruct cmpLTMask_reg_reg(iRegINoSp dst, iRegI p, iRegI q)
9329 %{
9330 match(Set dst (CmpLTMask p q));
9331
9332 ins_cost(2 * ALU_COST);
9333
9334 format %{ "slt $dst, $p, $q\t#@cmpLTMask_reg_reg\n\t"
9335 "subw $dst, zr, $dst\t#@cmpLTMask_reg_reg"
9336 %}
9337
9338 ins_encode %{
9339 __ slt(as_Register($dst$$reg), as_Register($p$$reg), as_Register($q$$reg));
9340 __ subw(as_Register($dst$$reg), zr, as_Register($dst$$reg));
9341 %}
9342
9343 ins_pipe(ialu_reg_reg);
9344 %}
9345
9346 instruct cmpLTMask_reg_zero(iRegINoSp dst, iRegIorL2I op, immI0 zero)
9347 %{
9348 match(Set dst (CmpLTMask op zero));
9349
9350 ins_cost(ALU_COST);
9351
9352 format %{ "sraiw $dst, $dst, 31\t#@cmpLTMask_reg_reg" %}
9353
9354 ins_encode %{
9355 __ sraiw(as_Register($dst$$reg), as_Register($op$$reg), 31);
9356 %}
9357
9358 ins_pipe(ialu_reg_shift);
9359 %}
9360
9361
9362 // ============================================================================
9363 // Max and Min
9364
9365 instruct minI_reg_reg(iRegINoSp dst, iRegI src)
9366 %{
9367 match(Set dst (MinI dst src));
9368
9369 ins_cost(BRANCH_COST + ALU_COST);
9370 format %{"minI_reg_reg $dst, $dst, $src\t#@minI_reg_reg\n\t"%}
9371
9372 ins_encode %{
9373 __ cmov_gt(as_Register($dst$$reg), as_Register($src$$reg),
9374 as_Register($dst$$reg), as_Register($src$$reg));
9375 %}
9376
9377 ins_pipe(pipe_class_compare);
9378 %}
9379
9380 instruct maxI_reg_reg(iRegINoSp dst, iRegI src)
9381 %{
9382 match(Set dst (MaxI dst src));
9383
9384 ins_cost(BRANCH_COST + ALU_COST);
9385 format %{"maxI_reg_reg $dst, $dst, $src\t#@maxI_reg_reg\n\t"%}
9386
9387 ins_encode %{
9388 __ cmov_lt(as_Register($dst$$reg), as_Register($src$$reg),
9389 as_Register($dst$$reg), as_Register($src$$reg));
9390 %}
9391
9392 ins_pipe(pipe_class_compare);
9393 %}
9394
9395 // special case for comparing with zero
9396 // n.b. this is selected in preference to the rule above because it
9397 // avoids loading constant 0 into a source register
9398
9399 instruct minI_reg_zero(iRegINoSp dst, immI0 zero)
9400 %{
9401 match(Set dst (MinI dst zero));
9402 match(Set dst (MinI zero dst));
9403
9404 ins_cost(BRANCH_COST + ALU_COST);
9405 format %{"minI_reg_zero $dst, $dst, zr\t#@minI_reg_zero\n\t"%}
9406
9407 ins_encode %{
9408 __ cmov_gt(as_Register($dst$$reg), zr,
9409 as_Register($dst$$reg), zr);
9410 %}
9411
9412 ins_pipe(pipe_class_compare);
9413 %}
9414
9415 instruct maxI_reg_zero(iRegINoSp dst, immI0 zero)
9416 %{
9417 match(Set dst (MaxI dst zero));
9418 match(Set dst (MaxI zero dst));
9419
9420 ins_cost(BRANCH_COST + ALU_COST);
9421 format %{"maxI_reg_zero $dst, $dst, zr\t#@maxI_reg_zero\n\t"%}
9422
9423 ins_encode %{
9424 __ cmov_lt(as_Register($dst$$reg), zr,
9425 as_Register($dst$$reg), zr);
9426 %}
9427
9428 ins_pipe(pipe_class_compare);
9429 %}
9430
9431 instruct minI_rReg(iRegINoSp dst, iRegI src1, iRegI src2)
9432 %{
9433 match(Set dst (MinI src1 src2));
9434
9435 effect(DEF dst, USE src1, USE src2);
9436
9437 ins_cost(BRANCH_COST + ALU_COST * 2);
9438 format %{"minI_rReg $dst, $src1, $src2\t#@minI_rReg\n\t"%}
9439
9440 ins_encode %{
9441 __ mv(as_Register($dst$$reg), as_Register($src1$$reg));
9442 __ cmov_gt(as_Register($src1$$reg), as_Register($src2$$reg),
9443 as_Register($dst$$reg), as_Register($src2$$reg));
9444 %}
9445
9446 ins_pipe(pipe_class_compare);
9447 %}
9448
9449 instruct maxI_rReg(iRegINoSp dst, iRegI src1, iRegI src2)
9450 %{
9451 match(Set dst (MaxI src1 src2));
9452
9453 effect(DEF dst, USE src1, USE src2);
9454
9455 ins_cost(BRANCH_COST + ALU_COST * 2);
9456 format %{"maxI_rReg $dst, $src1, $src2\t#@maxI_rReg\n\t"%}
9457
9458 ins_encode %{
9459 __ mv(as_Register($dst$$reg), as_Register($src1$$reg));
9460 __ cmov_lt(as_Register($src1$$reg), as_Register($src2$$reg),
9461 as_Register($dst$$reg), as_Register($src2$$reg));
9462 %}
9463
9464 ins_pipe(pipe_class_compare);
9465 %}
9466
9467 // ============================================================================
9468 // Branch Instructions
9469 // Direct Branch.
9470 instruct branch(label lbl)
9471 %{
9472 match(Goto);
9473
9474 effect(USE lbl);
9475
9476 ins_cost(BRANCH_COST);
9477 format %{ "j $lbl\t#@branch" %}
9478
9479 ins_encode(riscv_enc_j(lbl));
9480
9481 ins_pipe(pipe_branch);
9482 %}
9483
9484 // ============================================================================
9485 // Compare and Branch Instructions
9486
9487 // Patterns for short (< 12KiB) variants
9488
9489 // Compare flags and branch near instructions.
9490 instruct cmpFlag_branch(cmpOpEqNe cmp, rFlagsReg cr, label lbl) %{
9491 match(If cmp cr);
9492 effect(USE lbl);
9493
9494 ins_cost(BRANCH_COST);
9495 format %{ "b$cmp $cr, zr, $lbl\t#@cmpFlag_branch" %}
9496
9497 ins_encode %{
9498 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($cr$$reg), *($lbl$$label));
9499 %}
9500 ins_pipe(pipe_cmpz_branch);
9501 ins_short_branch(1);
9502 %}
9503
9504 // Compare signed int and branch near instructions
9505 instruct cmpI_branch(cmpOp cmp, iRegI op1, iRegI op2, label lbl)
9506 %{
9507 // Same match rule as `far_cmpI_branch'.
9508 match(If cmp (CmpI op1 op2));
9509
9510 effect(USE lbl);
9511
9512 ins_cost(BRANCH_COST);
9513
9514 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpI_branch" %}
9515
9516 ins_encode %{
9517 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label));
9518 %}
9519
9520 ins_pipe(pipe_cmp_branch);
9521 ins_short_branch(1);
9522 %}
9523
9524 instruct cmpI_loop(cmpOp cmp, iRegI op1, iRegI op2, label lbl)
9525 %{
9526 // Same match rule as `far_cmpI_loop'.
9527 match(CountedLoopEnd cmp (CmpI op1 op2));
9528
9529 effect(USE lbl);
9530
9531 ins_cost(BRANCH_COST);
9532
9533 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpI_loop" %}
9534
9535 ins_encode %{
9536 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label));
9537 %}
9538
9539 ins_pipe(pipe_cmp_branch);
9540 ins_short_branch(1);
9541 %}
9542
9543 // Compare unsigned int and branch near instructions
9544 instruct cmpU_branch(cmpOpU cmp, iRegI op1, iRegI op2, label lbl)
9545 %{
9546 // Same match rule as `far_cmpU_branch'.
9547 match(If cmp (CmpU op1 op2));
9548
9549 effect(USE lbl);
9550
9551 ins_cost(BRANCH_COST);
9552
9553 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpU_branch" %}
9554
9555 ins_encode %{
9556 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9557 as_Register($op2$$reg), *($lbl$$label));
9558 %}
9559
9560 ins_pipe(pipe_cmp_branch);
9561 ins_short_branch(1);
9562 %}
9563
9564 // Compare signed long and branch near instructions
9565 instruct cmpL_branch(cmpOp cmp, iRegL op1, iRegL op2, label lbl)
9566 %{
9567 // Same match rule as `far_cmpL_branch'.
9568 match(If cmp (CmpL op1 op2));
9569
9570 effect(USE lbl);
9571
9572 ins_cost(BRANCH_COST);
9573
9574 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpL_branch" %}
9575
9576 ins_encode %{
9577 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label));
9578 %}
9579
9580 ins_pipe(pipe_cmp_branch);
9581 ins_short_branch(1);
9582 %}
9583
9584 instruct cmpL_loop(cmpOp cmp, iRegL op1, iRegL op2, label lbl)
9585 %{
9586 // Same match rule as `far_cmpL_loop'.
9587 match(CountedLoopEnd cmp (CmpL op1 op2));
9588
9589 effect(USE lbl);
9590
9591 ins_cost(BRANCH_COST);
9592
9593 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpL_loop" %}
9594
9595 ins_encode %{
9596 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label));
9597 %}
9598
9599 ins_pipe(pipe_cmp_branch);
9600 ins_short_branch(1);
9601 %}
9602
9603 // Compare unsigned long and branch near instructions
9604 instruct cmpUL_branch(cmpOpU cmp, iRegL op1, iRegL op2, label lbl)
9605 %{
9606 // Same match rule as `far_cmpUL_branch'.
9607 match(If cmp (CmpUL op1 op2));
9608
9609 effect(USE lbl);
9610
9611 ins_cost(BRANCH_COST);
9612 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpUL_branch" %}
9613
9614 ins_encode %{
9615 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9616 as_Register($op2$$reg), *($lbl$$label));
9617 %}
9618
9619 ins_pipe(pipe_cmp_branch);
9620 ins_short_branch(1);
9621 %}
9622
9623 // Compare pointer and branch near instructions
9624 instruct cmpP_branch(cmpOpU cmp, iRegP op1, iRegP op2, label lbl)
9625 %{
9626 // Same match rule as `far_cmpP_branch'.
9627 match(If cmp (CmpP op1 op2));
9628
9629 effect(USE lbl);
9630
9631 ins_cost(BRANCH_COST);
9632
9633 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpP_branch" %}
9634
9635 ins_encode %{
9636 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9637 as_Register($op2$$reg), *($lbl$$label));
9638 %}
9639
9640 ins_pipe(pipe_cmp_branch);
9641 ins_short_branch(1);
9642 %}
9643
9644 // Compare narrow pointer and branch near instructions
9645 instruct cmpN_branch(cmpOpU cmp, iRegN op1, iRegN op2, label lbl)
9646 %{
9647 // Same match rule as `far_cmpN_branch'.
9648 match(If cmp (CmpN op1 op2));
9649
9650 effect(USE lbl);
9651
9652 ins_cost(BRANCH_COST);
9653
9654 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpN_branch" %}
9655
9656 ins_encode %{
9657 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9658 as_Register($op2$$reg), *($lbl$$label));
9659 %}
9660
9661 ins_pipe(pipe_cmp_branch);
9662 ins_short_branch(1);
9663 %}
9664
9665 // Compare float and branch near instructions
9666 instruct cmpF_branch(cmpOp cmp, fRegF op1, fRegF op2, label lbl)
9667 %{
9668 // Same match rule as `far_cmpF_branch'.
9669 match(If cmp (CmpF op1 op2));
9670
9671 effect(USE lbl);
9672
9673 ins_cost(XFER_COST + BRANCH_COST);
9674 format %{ "float_b$cmp $op1, $op2, $lbl \t#@cmpF_branch"%}
9675
9676 ins_encode %{
9677 __ float_cmp_branch($cmp$$cmpcode, as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg), *($lbl$$label));
9678 %}
9679
9680 ins_pipe(pipe_class_compare);
9681 ins_short_branch(1);
9682 %}
9683
9684 // Compare double and branch near instructions
9685 instruct cmpD_branch(cmpOp cmp, fRegD op1, fRegD op2, label lbl)
9686 %{
9687 // Same match rule as `far_cmpD_branch'.
9688 match(If cmp (CmpD op1 op2));
9689 effect(USE lbl);
9690
9691 ins_cost(XFER_COST + BRANCH_COST);
9692 format %{ "double_b$cmp $op1, $op2, $lbl\t#@cmpD_branch"%}
9693
9694 ins_encode %{
9695 __ float_cmp_branch($cmp$$cmpcode | C2_MacroAssembler::double_branch_mask, as_FloatRegister($op1$$reg),
9696 as_FloatRegister($op2$$reg), *($lbl$$label));
9697 %}
9698
9699 ins_pipe(pipe_class_compare);
9700 ins_short_branch(1);
9701 %}
9702
9703 // Compare signed int with zero and branch near instructions
9704 instruct cmpI_reg_imm0_branch(cmpOp cmp, iRegI op1, immI0 zero, label lbl)
9705 %{
9706 // Same match rule as `far_cmpI_reg_imm0_branch'.
9707 match(If cmp (CmpI op1 zero));
9708
9709 effect(USE op1, USE lbl);
9710
9711 ins_cost(BRANCH_COST);
9712 format %{ "b$cmp $op1, zr, $lbl\t#@cmpI_reg_imm0_branch" %}
9713
9714 ins_encode %{
9715 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label));
9716 %}
9717
9718 ins_pipe(pipe_cmpz_branch);
9719 ins_short_branch(1);
9720 %}
9721
9722 instruct cmpI_reg_imm0_loop(cmpOp cmp, iRegI op1, immI0 zero, label lbl)
9723 %{
9724 // Same match rule as `far_cmpI_reg_imm0_loop'.
9725 match(CountedLoopEnd cmp (CmpI op1 zero));
9726
9727 effect(USE op1, USE lbl);
9728
9729 ins_cost(BRANCH_COST);
9730
9731 format %{ "b$cmp $op1, zr, $lbl\t#@cmpI_reg_imm0_loop" %}
9732
9733 ins_encode %{
9734 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label));
9735 %}
9736
9737 ins_pipe(pipe_cmpz_branch);
9738 ins_short_branch(1);
9739 %}
9740
9741 // Compare unsigned int with zero and branch near instructions
9742 instruct cmpUEqNeLeGt_reg_imm0_branch(cmpOpUEqNeLeGt cmp, iRegI op1, immI0 zero, label lbl)
9743 %{
9744 // Same match rule as `far_cmpUEqNeLeGt_reg_imm0_branch'.
9745 match(If cmp (CmpU op1 zero));
9746
9747 effect(USE op1, USE lbl);
9748
9749 ins_cost(BRANCH_COST);
9750
9751 format %{ "b$cmp $op1, zr, $lbl\t#@cmpUEqNeLeGt_reg_imm0_branch" %}
9752
9753 ins_encode %{
9754 __ enc_cmpUEqNeLeGt_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
9755 %}
9756
9757 ins_pipe(pipe_cmpz_branch);
9758 ins_short_branch(1);
9759 %}
9760
9761 // Compare signed long with zero and branch near instructions
9762 instruct cmpL_reg_imm0_branch(cmpOp cmp, iRegL op1, immL0 zero, label lbl)
9763 %{
9764 // Same match rule as `far_cmpL_reg_imm0_branch'.
9765 match(If cmp (CmpL op1 zero));
9766
9767 effect(USE op1, USE lbl);
9768
9769 ins_cost(BRANCH_COST);
9770
9771 format %{ "b$cmp $op1, zr, $lbl\t#@cmpL_reg_imm0_branch" %}
9772
9773 ins_encode %{
9774 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label));
9775 %}
9776
9777 ins_pipe(pipe_cmpz_branch);
9778 ins_short_branch(1);
9779 %}
9780
9781 instruct cmpL_reg_imm0_loop(cmpOp cmp, iRegL op1, immL0 zero, label lbl)
9782 %{
9783 // Same match rule as `far_cmpL_reg_imm0_loop'.
9784 match(CountedLoopEnd cmp (CmpL op1 zero));
9785
9786 effect(USE op1, USE lbl);
9787
9788 ins_cost(BRANCH_COST);
9789
9790 format %{ "b$cmp $op1, zr, $lbl\t#@cmpL_reg_imm0_loop" %}
9791
9792 ins_encode %{
9793 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label));
9794 %}
9795
9796 ins_pipe(pipe_cmpz_branch);
9797 ins_short_branch(1);
9798 %}
9799
9800 // Compare unsigned long with zero and branch near instructions
9801 instruct cmpULEqNeLeGt_reg_imm0_branch(cmpOpUEqNeLeGt cmp, iRegL op1, immL0 zero, label lbl)
9802 %{
9803 // Same match rule as `far_cmpULEqNeLeGt_reg_imm0_branch'.
9804 match(If cmp (CmpUL op1 zero));
9805
9806 effect(USE op1, USE lbl);
9807
9808 ins_cost(BRANCH_COST);
9809
9810 format %{ "b$cmp $op1, zr, $lbl\t#@cmpULEqNeLeGt_reg_imm0_branch" %}
9811
9812 ins_encode %{
9813 __ enc_cmpUEqNeLeGt_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
9814 %}
9815
9816 ins_pipe(pipe_cmpz_branch);
9817 ins_short_branch(1);
9818 %}
9819
9820 // Compare pointer with zero and branch near instructions
9821 instruct cmpP_imm0_branch(cmpOpEqNe cmp, iRegP op1, immP0 zero, label lbl) %{
9822 // Same match rule as `far_cmpP_reg_imm0_branch'.
9823 match(If cmp (CmpP op1 zero));
9824 effect(USE lbl);
9825
9826 ins_cost(BRANCH_COST);
9827 format %{ "b$cmp $op1, zr, $lbl\t#@cmpP_imm0_branch" %}
9828
9829 ins_encode %{
9830 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
9831 %}
9832
9833 ins_pipe(pipe_cmpz_branch);
9834 ins_short_branch(1);
9835 %}
9836
9837 // Compare narrow pointer with zero and branch near instructions
9838 instruct cmpN_imm0_branch(cmpOpEqNe cmp, iRegN op1, immN0 zero, label lbl) %{
9839 // Same match rule as `far_cmpN_reg_imm0_branch'.
9840 match(If cmp (CmpN op1 zero));
9841 effect(USE lbl);
9842
9843 ins_cost(BRANCH_COST);
9844
9845 format %{ "b$cmp $op1, zr, $lbl\t#@cmpN_imm0_branch" %}
9846
9847 ins_encode %{
9848 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
9849 %}
9850
9851 ins_pipe(pipe_cmpz_branch);
9852 ins_short_branch(1);
9853 %}
9854
9855 // Compare narrow pointer with pointer zero and branch near instructions
9856 instruct cmpP_narrowOop_imm0_branch(cmpOpEqNe cmp, iRegN op1, immP0 zero, label lbl) %{
9857 // Same match rule as `far_cmpP_narrowOop_imm0_branch'.
9858 match(If cmp (CmpP (DecodeN op1) zero));
9859 effect(USE lbl);
9860
9861 ins_cost(BRANCH_COST);
9862 format %{ "b$cmp $op1, zr, $lbl\t#@cmpP_narrowOop_imm0_branch" %}
9863
9864 ins_encode %{
9865 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
9866 %}
9867
9868 ins_pipe(pipe_cmpz_branch);
9869 ins_short_branch(1);
9870 %}
9871
9872 // Patterns for far (20KiB) variants
9873
9874 instruct far_cmpFlag_branch(cmpOp cmp, rFlagsReg cr, label lbl) %{
9875 match(If cmp cr);
9876 effect(USE lbl);
9877
9878 ins_cost(BRANCH_COST);
9879 format %{ "far_b$cmp $cr, zr, $lbl\t#@far_cmpFlag_branch"%}
9880
9881 ins_encode %{
9882 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($cr$$reg), *($lbl$$label), /* is_far */ true);
9883 %}
9884
9885 ins_pipe(pipe_cmpz_branch);
9886 %}
9887
9888 // Compare signed int and branch far instructions
9889 instruct far_cmpI_branch(cmpOp cmp, iRegI op1, iRegI op2, label lbl) %{
9890 match(If cmp (CmpI op1 op2));
9891 effect(USE lbl);
9892
9893 ins_cost(BRANCH_COST * 2);
9894
9895 // the format instruction [far_b$cmp] here is be used as two insructions
9896 // in macroassembler: b$not_cmp(op1, op2, done), j($lbl), bind(done)
9897 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpI_branch" %}
9898
9899 ins_encode %{
9900 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9901 %}
9902
9903 ins_pipe(pipe_cmp_branch);
9904 %}
9905
9906 instruct far_cmpI_loop(cmpOp cmp, iRegI op1, iRegI op2, label lbl) %{
9907 match(CountedLoopEnd cmp (CmpI op1 op2));
9908 effect(USE lbl);
9909
9910 ins_cost(BRANCH_COST * 2);
9911 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpI_loop" %}
9912
9913 ins_encode %{
9914 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9915 %}
9916
9917 ins_pipe(pipe_cmp_branch);
9918 %}
9919
9920 instruct far_cmpU_branch(cmpOpU cmp, iRegI op1, iRegI op2, label lbl) %{
9921 match(If cmp (CmpU op1 op2));
9922 effect(USE lbl);
9923
9924 ins_cost(BRANCH_COST * 2);
9925 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpU_branch" %}
9926
9927 ins_encode %{
9928 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9929 as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9930 %}
9931
9932 ins_pipe(pipe_cmp_branch);
9933 %}
9934
9935 instruct far_cmpL_branch(cmpOp cmp, iRegL op1, iRegL op2, label lbl) %{
9936 match(If cmp (CmpL op1 op2));
9937 effect(USE lbl);
9938
9939 ins_cost(BRANCH_COST * 2);
9940 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpL_branch" %}
9941
9942 ins_encode %{
9943 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9944 %}
9945
9946 ins_pipe(pipe_cmp_branch);
9947 %}
9948
9949 instruct far_cmpLloop(cmpOp cmp, iRegL op1, iRegL op2, label lbl) %{
9950 match(CountedLoopEnd cmp (CmpL op1 op2));
9951 effect(USE lbl);
9952
9953 ins_cost(BRANCH_COST * 2);
9954 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpL_loop" %}
9955
9956 ins_encode %{
9957 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9958 %}
9959
9960 ins_pipe(pipe_cmp_branch);
9961 %}
9962
9963 instruct far_cmpUL_branch(cmpOpU cmp, iRegL op1, iRegL op2, label lbl) %{
9964 match(If cmp (CmpUL op1 op2));
9965 effect(USE lbl);
9966
9967 ins_cost(BRANCH_COST * 2);
9968 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpUL_branch" %}
9969
9970 ins_encode %{
9971 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9972 as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9973 %}
9974
9975 ins_pipe(pipe_cmp_branch);
9976 %}
9977
9978 instruct far_cmpP_branch(cmpOpU cmp, iRegP op1, iRegP op2, label lbl)
9979 %{
9980 match(If cmp (CmpP op1 op2));
9981
9982 effect(USE lbl);
9983
9984 ins_cost(BRANCH_COST * 2);
9985
9986 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpP_branch" %}
9987
9988 ins_encode %{
9989 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9990 as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9991 %}
9992
9993 ins_pipe(pipe_cmp_branch);
9994 %}
9995
9996 instruct far_cmpN_branch(cmpOpU cmp, iRegN op1, iRegN op2, label lbl)
9997 %{
9998 match(If cmp (CmpN op1 op2));
9999
10000 effect(USE lbl);
10001
10002 ins_cost(BRANCH_COST * 2);
10003
10004 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpN_branch" %}
10005
10006 ins_encode %{
10007 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
10008 as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
10009 %}
10010
10011 ins_pipe(pipe_cmp_branch);
10012 %}
10013
10014 // Float compare and branch instructions
10015 instruct far_cmpF_branch(cmpOp cmp, fRegF op1, fRegF op2, label lbl)
10016 %{
10017 match(If cmp (CmpF op1 op2));
10018
10019 effect(USE lbl);
10020
10021 ins_cost(XFER_COST + BRANCH_COST * 2);
10022 format %{ "far_float_b$cmp $op1, $op2, $lbl\t#@far_cmpF_branch"%}
10023
10024 ins_encode %{
10025 __ float_cmp_branch($cmp$$cmpcode, as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg),
10026 *($lbl$$label), /* is_far */ true);
10027 %}
10028
10029 ins_pipe(pipe_class_compare);
10030 %}
10031
10032 // Double compare and branch instructions
10033 instruct far_cmpD_branch(cmpOp cmp, fRegD op1, fRegD op2, label lbl)
10034 %{
10035 match(If cmp (CmpD op1 op2));
10036 effect(USE lbl);
10037
10038 ins_cost(XFER_COST + BRANCH_COST * 2);
10039 format %{ "far_double_b$cmp $op1, $op2, $lbl\t#@far_cmpD_branch"%}
10040
10041 ins_encode %{
10042 __ float_cmp_branch($cmp$$cmpcode | C2_MacroAssembler::double_branch_mask, as_FloatRegister($op1$$reg),
10043 as_FloatRegister($op2$$reg), *($lbl$$label), /* is_far */ true);
10044 %}
10045
10046 ins_pipe(pipe_class_compare);
10047 %}
10048
10049 instruct far_cmpI_reg_imm0_branch(cmpOp cmp, iRegI op1, immI0 zero, label lbl)
10050 %{
10051 match(If cmp (CmpI op1 zero));
10052
10053 effect(USE op1, USE lbl);
10054
10055 ins_cost(BRANCH_COST * 2);
10056
10057 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpI_reg_imm0_branch" %}
10058
10059 ins_encode %{
10060 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label), /* is_far */ true);
10061 %}
10062
10063 ins_pipe(pipe_cmpz_branch);
10064 %}
10065
10066 instruct far_cmpI_reg_imm0_loop(cmpOp cmp, iRegI op1, immI0 zero, label lbl)
10067 %{
10068 match(CountedLoopEnd cmp (CmpI op1 zero));
10069
10070 effect(USE op1, USE lbl);
10071
10072 ins_cost(BRANCH_COST * 2);
10073
10074 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpI_reg_imm0_loop" %}
10075
10076 ins_encode %{
10077 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label), /* is_far */ true);
10078 %}
10079
10080 ins_pipe(pipe_cmpz_branch);
10081 %}
10082
10083 instruct far_cmpUEqNeLeGt_imm0_branch(cmpOpUEqNeLeGt cmp, iRegI op1, immI0 zero, label lbl)
10084 %{
10085 match(If cmp (CmpU op1 zero));
10086
10087 effect(USE op1, USE lbl);
10088
10089 ins_cost(BRANCH_COST * 2);
10090
10091 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpUEqNeLeGt_imm0_branch" %}
10092
10093 ins_encode %{
10094 __ enc_cmpUEqNeLeGt_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
10095 %}
10096
10097 ins_pipe(pipe_cmpz_branch);
10098 %}
10099
10100 // compare lt/ge unsigned instructs has no short instruct with same match
10101 instruct far_cmpULtGe_reg_imm0_branch(cmpOpULtGe cmp, iRegI op1, immI0 zero, label lbl)
10102 %{
10103 match(If cmp (CmpU op1 zero));
10104
10105 effect(USE op1, USE lbl);
10106
10107 ins_cost(BRANCH_COST);
10108
10109 format %{ "j $lbl if $cmp == ge\t#@far_cmpULtGe_reg_imm0_branch" %}
10110
10111 ins_encode(riscv_enc_far_cmpULtGe_imm0_branch(cmp, op1, lbl));
10112
10113 ins_pipe(pipe_cmpz_branch);
10114 %}
10115
10116 instruct far_cmpL_reg_imm0_branch(cmpOp cmp, iRegL op1, immL0 zero, label lbl)
10117 %{
10118 match(If cmp (CmpL op1 zero));
10119
10120 effect(USE op1, USE lbl);
10121
10122 ins_cost(BRANCH_COST * 2);
10123
10124 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpL_reg_imm0_branch" %}
10125
10126 ins_encode %{
10127 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label), /* is_far */ true);
10128 %}
10129
10130 ins_pipe(pipe_cmpz_branch);
10131 %}
10132
10133 instruct far_cmpL_reg_imm0_loop(cmpOp cmp, iRegL op1, immL0 zero, label lbl)
10134 %{
10135 match(CountedLoopEnd cmp (CmpL op1 zero));
10136
10137 effect(USE op1, USE lbl);
10138
10139 ins_cost(BRANCH_COST * 2);
10140
10141 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpL_reg_imm0_loop" %}
10142
10143 ins_encode %{
10144 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label), /* is_far */ true);
10145 %}
10146
10147 ins_pipe(pipe_cmpz_branch);
10148 %}
10149
10150 instruct far_cmpULEqNeLeGt_reg_imm0_branch(cmpOpUEqNeLeGt cmp, iRegL op1, immL0 zero, label lbl)
10151 %{
10152 match(If cmp (CmpUL op1 zero));
10153
10154 effect(USE op1, USE lbl);
10155
10156 ins_cost(BRANCH_COST * 2);
10157
10158 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpULEqNeLeGt_reg_imm0_branch" %}
10159
10160 ins_encode %{
10161 __ enc_cmpUEqNeLeGt_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
10162 %}
10163
10164 ins_pipe(pipe_cmpz_branch);
10165 %}
10166
10167 // compare lt/ge unsigned instructs has no short instruct with same match
10168 instruct far_cmpULLtGe_reg_imm0_branch(cmpOpULtGe cmp, iRegL op1, immL0 zero, label lbl)
10169 %{
10170 match(If cmp (CmpUL op1 zero));
10171
10172 effect(USE op1, USE lbl);
10173
10174 ins_cost(BRANCH_COST);
10175
10176 format %{ "j $lbl if $cmp == ge\t#@far_cmpULLtGe_reg_imm0_branch" %}
10177
10178 ins_encode(riscv_enc_far_cmpULtGe_imm0_branch(cmp, op1, lbl));
10179
10180 ins_pipe(pipe_cmpz_branch);
10181 %}
10182
10183 instruct far_cmpP_imm0_branch(cmpOpEqNe cmp, iRegP op1, immP0 zero, label lbl) %{
10184 match(If cmp (CmpP op1 zero));
10185 effect(USE lbl);
10186
10187 ins_cost(BRANCH_COST * 2);
10188 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpP_imm0_branch" %}
10189
10190 ins_encode %{
10191 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
10192 %}
10193
10194 ins_pipe(pipe_cmpz_branch);
10195 %}
10196
10197 instruct far_cmpN_imm0_branch(cmpOpEqNe cmp, iRegN op1, immN0 zero, label lbl) %{
10198 match(If cmp (CmpN op1 zero));
10199 effect(USE lbl);
10200
10201 ins_cost(BRANCH_COST * 2);
10202
10203 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpN_imm0_branch" %}
10204
10205 ins_encode %{
10206 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
10207 %}
10208
10209 ins_pipe(pipe_cmpz_branch);
10210 %}
10211
10212 instruct far_cmpP_narrowOop_imm0_branch(cmpOpEqNe cmp, iRegN op1, immP0 zero, label lbl) %{
10213 match(If cmp (CmpP (DecodeN op1) zero));
10214 effect(USE lbl);
10215
10216 ins_cost(BRANCH_COST * 2);
10217 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpP_narrowOop_imm0_branch" %}
10218
10219 ins_encode %{
10220 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
10221 %}
10222
10223 ins_pipe(pipe_cmpz_branch);
10224 %}
10225
10226 // ============================================================================
10227 // Conditional Move Instructions
10228
10229 // --------- CMoveI ---------
10230
10231 instruct cmovI_cmpI(iRegINoSp dst, iRegI src, iRegI op1, iRegI op2, cmpOp cop) %{
10232 match(Set dst (CMoveI (Binary cop (CmpI op1 op2)) (Binary dst src)));
10233 ins_cost(ALU_COST + BRANCH_COST);
10234
10235 format %{
10236 "CMoveI $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpI\n\t"
10237 %}
10238
10239 ins_encode %{
10240 __ enc_cmove($cop$$cmpcode,
10241 as_Register($op1$$reg), as_Register($op2$$reg),
10242 as_Register($dst$$reg), as_Register($src$$reg));
10243 %}
10244
10245 ins_pipe(pipe_class_compare);
10246 %}
10247
10248 instruct cmovI_cmpU(iRegINoSp dst, iRegI src, iRegI op1, iRegI op2, cmpOpU cop) %{
10249 match(Set dst (CMoveI (Binary cop (CmpU op1 op2)) (Binary dst src)));
10250 ins_cost(ALU_COST + BRANCH_COST);
10251
10252 format %{
10253 "CMoveI $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpU\n\t"
10254 %}
10255
10256 ins_encode %{
10257 __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10258 as_Register($op1$$reg), as_Register($op2$$reg),
10259 as_Register($dst$$reg), as_Register($src$$reg));
10260 %}
10261
10262 ins_pipe(pipe_class_compare);
10263 %}
10264
10265 instruct cmovI_cmpL(iRegINoSp dst, iRegI src, iRegL op1, iRegL op2, cmpOp cop) %{
10266 match(Set dst (CMoveI (Binary cop (CmpL op1 op2)) (Binary dst src)));
10267 ins_cost(ALU_COST + BRANCH_COST);
10268
10269 format %{
10270 "CMoveI $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpL\n\t"
10271 %}
10272
10273 ins_encode %{
10274 __ enc_cmove($cop$$cmpcode,
10275 as_Register($op1$$reg), as_Register($op2$$reg),
10276 as_Register($dst$$reg), as_Register($src$$reg));
10277 %}
10278
10279 ins_pipe(pipe_class_compare);
10280 %}
10281
10282 instruct cmovI_cmpUL(iRegINoSp dst, iRegI src, iRegL op1, iRegL op2, cmpOpU cop) %{
10283 match(Set dst (CMoveI (Binary cop (CmpUL op1 op2)) (Binary dst src)));
10284 ins_cost(ALU_COST + BRANCH_COST);
10285
10286 format %{
10287 "CMoveI $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpUL\n\t"
10288 %}
10289
10290 ins_encode %{
10291 __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10292 as_Register($op1$$reg), as_Register($op2$$reg),
10293 as_Register($dst$$reg), as_Register($src$$reg));
10294 %}
10295
10296 ins_pipe(pipe_class_compare);
10297 %}
10298
10299 instruct cmovI_cmpF(iRegINoSp dst, iRegI src, fRegF op1, fRegF op2, cmpOp cop) %{
10300 match(Set dst (CMoveI (Binary cop (CmpF op1 op2)) (Binary dst src)));
10301 ins_cost(ALU_COST + BRANCH_COST);
10302
10303 format %{
10304 "CMoveI $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpF\n\t"
10305 %}
10306
10307 ins_encode %{
10308 __ enc_cmove_cmp_fp($cop$$cmpcode,
10309 as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg),
10310 as_Register($dst$$reg), as_Register($src$$reg), true /* is_single */);
10311 %}
10312
10313 ins_pipe(pipe_class_compare);
10314 %}
10315
10316 instruct cmovI_cmpD(iRegINoSp dst, iRegI src, fRegD op1, fRegD op2, cmpOp cop) %{
10317 match(Set dst (CMoveI (Binary cop (CmpD op1 op2)) (Binary dst src)));
10318 ins_cost(ALU_COST + BRANCH_COST);
10319
10320 format %{
10321 "CMoveI $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpD\n\t"
10322 %}
10323
10324 ins_encode %{
10325 __ enc_cmove_cmp_fp($cop$$cmpcode | C2_MacroAssembler::double_branch_mask,
10326 as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg),
10327 as_Register($dst$$reg), as_Register($src$$reg), false /* is_single */);
10328 %}
10329
10330 ins_pipe(pipe_class_compare);
10331 %}
10332
10333 instruct cmovI_cmpN(iRegINoSp dst, iRegI src, iRegN op1, iRegN op2, cmpOpU cop) %{
10334 match(Set dst (CMoveI (Binary cop (CmpN op1 op2)) (Binary dst src)));
10335 ins_cost(ALU_COST + BRANCH_COST);
10336
10337 format %{
10338 "CMoveI $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpN\n\t"
10339 %}
10340
10341 ins_encode %{
10342 __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10343 as_Register($op1$$reg), as_Register($op2$$reg),
10344 as_Register($dst$$reg), as_Register($src$$reg));
10345 %}
10346
10347 ins_pipe(pipe_class_compare);
10348 %}
10349
10350 instruct cmovI_cmpP(iRegINoSp dst, iRegI src, iRegP op1, iRegP op2, cmpOpU cop) %{
10351 match(Set dst (CMoveI (Binary cop (CmpP op1 op2)) (Binary dst src)));
10352 ins_cost(ALU_COST + BRANCH_COST);
10353
10354 format %{
10355 "CMoveI $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpP\n\t"
10356 %}
10357
10358 ins_encode %{
10359 __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10360 as_Register($op1$$reg), as_Register($op2$$reg),
10361 as_Register($dst$$reg), as_Register($src$$reg));
10362 %}
10363
10364 ins_pipe(pipe_class_compare);
10365 %}
10366
10367 // --------- CMoveL ---------
10368
10369 instruct cmovL_cmpL(iRegLNoSp dst, iRegL src, iRegL op1, iRegL op2, cmpOp cop) %{
10370 match(Set dst (CMoveL (Binary cop (CmpL op1 op2)) (Binary dst src)));
10371 ins_cost(ALU_COST + BRANCH_COST);
10372
10373 format %{
10374 "CMoveL $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpL\n\t"
10375 %}
10376
10377 ins_encode %{
10378 __ enc_cmove($cop$$cmpcode,
10379 as_Register($op1$$reg), as_Register($op2$$reg),
10380 as_Register($dst$$reg), as_Register($src$$reg));
10381 %}
10382
10383 ins_pipe(pipe_class_compare);
10384 %}
10385
10386 instruct cmovL_cmpUL(iRegLNoSp dst, iRegL src, iRegL op1, iRegL op2, cmpOpU cop) %{
10387 match(Set dst (CMoveL (Binary cop (CmpUL op1 op2)) (Binary dst src)));
10388 ins_cost(ALU_COST + BRANCH_COST);
10389
10390 format %{
10391 "CMoveL $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpUL\n\t"
10392 %}
10393
10394 ins_encode %{
10395 __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10396 as_Register($op1$$reg), as_Register($op2$$reg),
10397 as_Register($dst$$reg), as_Register($src$$reg));
10398 %}
10399
10400 ins_pipe(pipe_class_compare);
10401 %}
10402
10403 instruct cmovL_cmpI(iRegLNoSp dst, iRegL src, iRegI op1, iRegI op2, cmpOp cop) %{
10404 match(Set dst (CMoveL (Binary cop (CmpI op1 op2)) (Binary dst src)));
10405 ins_cost(ALU_COST + BRANCH_COST);
10406
10407 format %{
10408 "CMoveL $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpI\n\t"
10409 %}
10410
10411 ins_encode %{
10412 __ enc_cmove($cop$$cmpcode,
10413 as_Register($op1$$reg), as_Register($op2$$reg),
10414 as_Register($dst$$reg), as_Register($src$$reg));
10415 %}
10416
10417 ins_pipe(pipe_class_compare);
10418 %}
10419
10420 instruct cmovL_cmpU(iRegLNoSp dst, iRegL src, iRegI op1, iRegI op2, cmpOpU cop) %{
10421 match(Set dst (CMoveL (Binary cop (CmpU op1 op2)) (Binary dst src)));
10422 ins_cost(ALU_COST + BRANCH_COST);
10423
10424 format %{
10425 "CMoveL $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpU\n\t"
10426 %}
10427
10428 ins_encode %{
10429 __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10430 as_Register($op1$$reg), as_Register($op2$$reg),
10431 as_Register($dst$$reg), as_Register($src$$reg));
10432 %}
10433
10434 ins_pipe(pipe_class_compare);
10435 %}
10436
10437 instruct cmovL_cmpF(iRegLNoSp dst, iRegL src, fRegF op1, fRegF op2, cmpOp cop) %{
10438 match(Set dst (CMoveL (Binary cop (CmpF op1 op2)) (Binary dst src)));
10439 ins_cost(ALU_COST + BRANCH_COST);
10440
10441 format %{
10442 "CMoveL $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpF\n\t"
10443 %}
10444
10445 ins_encode %{
10446 __ enc_cmove_cmp_fp($cop$$cmpcode,
10447 as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg),
10448 as_Register($dst$$reg), as_Register($src$$reg), true /* is_single */);
10449 %}
10450
10451 ins_pipe(pipe_class_compare);
10452 %}
10453
10454 instruct cmovL_cmpD(iRegLNoSp dst, iRegL src, fRegD op1, fRegD op2, cmpOp cop) %{
10455 match(Set dst (CMoveL (Binary cop (CmpD op1 op2)) (Binary dst src)));
10456 ins_cost(ALU_COST + BRANCH_COST);
10457
10458 format %{
10459 "CMoveL $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpD\n\t"
10460 %}
10461
10462 ins_encode %{
10463 __ enc_cmove_cmp_fp($cop$$cmpcode | C2_MacroAssembler::double_branch_mask,
10464 as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg),
10465 as_Register($dst$$reg), as_Register($src$$reg), false /* is_single */);
10466 %}
10467
10468 ins_pipe(pipe_class_compare);
10469 %}
10470
10471 instruct cmovL_cmpN(iRegLNoSp dst, iRegL src, iRegN op1, iRegN op2, cmpOpU cop) %{
10472 match(Set dst (CMoveL (Binary cop (CmpN op1 op2)) (Binary dst src)));
10473 ins_cost(ALU_COST + BRANCH_COST);
10474
10475 format %{
10476 "CMoveL $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpN\n\t"
10477 %}
10478
10479 ins_encode %{
10480 __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10481 as_Register($op1$$reg), as_Register($op2$$reg),
10482 as_Register($dst$$reg), as_Register($src$$reg));
10483 %}
10484
10485 ins_pipe(pipe_class_compare);
10486 %}
10487
10488 instruct cmovL_cmpP(iRegLNoSp dst, iRegL src, iRegP op1, iRegP op2, cmpOpU cop) %{
10489 match(Set dst (CMoveL (Binary cop (CmpP op1 op2)) (Binary dst src)));
10490 ins_cost(ALU_COST + BRANCH_COST);
10491
10492 format %{
10493 "CMoveL $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpP\n\t"
10494 %}
10495
10496 ins_encode %{
10497 __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10498 as_Register($op1$$reg), as_Register($op2$$reg),
10499 as_Register($dst$$reg), as_Register($src$$reg));
10500 %}
10501
10502 ins_pipe(pipe_class_compare);
10503 %}
10504
10505 // --------- CMoveF ---------
10506
10507 instruct cmovF_cmpI(fRegF dst, fRegF src, iRegI op1, iRegI op2, cmpOp cop) %{
10508 match(Set dst (CMoveF (Binary cop (CmpI op1 op2)) (Binary dst src)));
10509 ins_cost(ALU_COST + BRANCH_COST);
10510
10511 format %{
10512 "CMoveF $dst, ($op1 $cop $op2), $dst, $src\t#@cmovF_cmpI\n\t"
10513 %}
10514
10515 ins_encode %{
10516 __ enc_cmove_fp_cmp($cop$$cmpcode,
10517 as_Register($op1$$reg), as_Register($op2$$reg),
10518 as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg), true /* is_single */);
10519 %}
10520
10521 ins_pipe(pipe_class_compare);
10522 %}
10523
10524 instruct cmovF_cmpU(fRegF dst, fRegF src, iRegI op1, iRegI op2, cmpOpU cop) %{
10525 match(Set dst (CMoveF (Binary cop (CmpU op1 op2)) (Binary dst src)));
10526 ins_cost(ALU_COST + BRANCH_COST);
10527
10528 format %{
10529 "CMoveF $dst, ($op1 $cop $op2), $dst, $src\t#@cmovF_cmpU\n\t"
10530 %}
10531
10532 ins_encode %{
10533 __ enc_cmove_fp_cmp($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10534 as_Register($op1$$reg), as_Register($op2$$reg),
10535 as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg), true /* is_single */);
10536 %}
10537
10538 ins_pipe(pipe_class_compare);
10539 %}
10540
10541 instruct cmovF_cmpL(fRegF dst, fRegF src, iRegL op1, iRegL op2, cmpOp cop) %{
10542 match(Set dst (CMoveF (Binary cop (CmpL op1 op2)) (Binary dst src)));
10543 ins_cost(ALU_COST + BRANCH_COST);
10544
10545 format %{
10546 "CMoveF $dst, ($op1 $cop $op2), $dst, $src\t#@cmovF_cmpL\n\t"
10547 %}
10548
10549 ins_encode %{
10550 __ enc_cmove_fp_cmp($cop$$cmpcode,
10551 as_Register($op1$$reg), as_Register($op2$$reg),
10552 as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg), true /* is_single */);
10553 %}
10554
10555 ins_pipe(pipe_class_compare);
10556 %}
10557
10558 instruct cmovF_cmpUL(fRegF dst, fRegF src, iRegL op1, iRegL op2, cmpOpU cop) %{
10559 match(Set dst (CMoveF (Binary cop (CmpUL op1 op2)) (Binary dst src)));
10560 ins_cost(ALU_COST + BRANCH_COST);
10561
10562 format %{
10563 "CMoveF $dst, ($op1 $cop $op2), $dst, $src\t#@cmovF_cmpUL\n\t"
10564 %}
10565
10566 ins_encode %{
10567 __ enc_cmove_fp_cmp($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10568 as_Register($op1$$reg), as_Register($op2$$reg),
10569 as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg), true /* is_single */);
10570 %}
10571
10572 ins_pipe(pipe_class_compare);
10573 %}
10574
10575 instruct cmovF_cmpF(fRegF dst, fRegF src, fRegF op1, fRegF op2, cmpOp cop) %{
10576 match(Set dst (CMoveF (Binary cop (CmpF op1 op2)) (Binary dst src)));
10577 ins_cost(ALU_COST + BRANCH_COST);
10578
10579 format %{
10580 "CMoveF $dst, ($op1 $cop $op2), $dst, $src\t#@cmovF_cmpF\n\t"
10581 %}
10582
10583 ins_encode %{
10584 __ enc_cmove_fp_cmp_fp($cop$$cmpcode,
10585 as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg),
10586 as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg),
10587 true /* cmp_single */, true /* cmov_single */);
10588 %}
10589
10590 ins_pipe(pipe_class_compare);
10591 %}
10592
10593 instruct cmovF_cmpD(fRegF dst, fRegF src, fRegD op1, fRegD op2, cmpOp cop) %{
10594 match(Set dst (CMoveF (Binary cop (CmpD op1 op2)) (Binary dst src)));
10595 ins_cost(ALU_COST + BRANCH_COST);
10596
10597 format %{
10598 "CMoveF $dst, ($op1 $cop $op2), $dst, $src\t#@cmovF_cmpD\n\t"
10599 %}
10600
10601 ins_encode %{
10602 __ enc_cmove_fp_cmp_fp($cop$$cmpcode | C2_MacroAssembler::double_branch_mask,
10603 as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg),
10604 as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg),
10605 false /* cmp_single */, true /* cmov_single */);
10606 %}
10607
10608 ins_pipe(pipe_class_compare);
10609 %}
10610
10611 instruct cmovF_cmpN(fRegF dst, fRegF src, iRegN op1, iRegN op2, cmpOp cop) %{
10612 match(Set dst (CMoveF (Binary cop (CmpN op1 op2)) (Binary dst src)));
10613 ins_cost(ALU_COST + BRANCH_COST);
10614
10615 format %{
10616 "CMoveF $dst, ($op1 $cop $op2), $dst, $src\t#@cmovF_cmpN\n\t"
10617 %}
10618
10619 ins_encode %{
10620 __ enc_cmove_fp_cmp($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10621 as_Register($op1$$reg), as_Register($op2$$reg),
10622 as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg), true /* is_single */);
10623 %}
10624
10625 ins_pipe(pipe_class_compare);
10626 %}
10627
10628 instruct cmovF_cmpP(fRegF dst, fRegF src, iRegP op1, iRegP op2, cmpOp cop) %{
10629 match(Set dst (CMoveF (Binary cop (CmpP op1 op2)) (Binary dst src)));
10630 ins_cost(ALU_COST + BRANCH_COST);
10631
10632 format %{
10633 "CMoveF $dst, ($op1 $cop $op2), $dst, $src\t#@cmovF_cmpP\n\t"
10634 %}
10635
10636 ins_encode %{
10637 __ enc_cmove_fp_cmp($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10638 as_Register($op1$$reg), as_Register($op2$$reg),
10639 as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg), true /* is_single */);
10640 %}
10641
10642 ins_pipe(pipe_class_compare);
10643 %}
10644
10645 // --------- CMoveD ---------
10646
10647 instruct cmovD_cmpI(fRegD dst, fRegD src, iRegI op1, iRegI op2, cmpOp cop) %{
10648 match(Set dst (CMoveD (Binary cop (CmpI op1 op2)) (Binary dst src)));
10649 ins_cost(ALU_COST + BRANCH_COST);
10650
10651 format %{
10652 "CMoveD $dst, ($op1 $cop $op2), $dst, $src\t#@cmovD_cmpI\n\t"
10653 %}
10654
10655 ins_encode %{
10656 __ enc_cmove_fp_cmp($cop$$cmpcode,
10657 as_Register($op1$$reg), as_Register($op2$$reg),
10658 as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg), false /* is_single */);
10659 %}
10660
10661 ins_pipe(pipe_class_compare);
10662 %}
10663
10664 instruct cmovD_cmpU(fRegD dst, fRegD src, iRegI op1, iRegI op2, cmpOpU cop) %{
10665 match(Set dst (CMoveD (Binary cop (CmpU op1 op2)) (Binary dst src)));
10666 ins_cost(ALU_COST + BRANCH_COST);
10667
10668 format %{
10669 "CMoveD $dst, ($op1 $cop $op2), $dst, $src\t#@cmovD_cmpU\n\t"
10670 %}
10671
10672 ins_encode %{
10673 __ enc_cmove_fp_cmp($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10674 as_Register($op1$$reg), as_Register($op2$$reg),
10675 as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg), false /* is_single */);
10676 %}
10677
10678 ins_pipe(pipe_class_compare);
10679 %}
10680
10681 instruct cmovD_cmpL(fRegD dst, fRegD src, iRegL op1, iRegL op2, cmpOp cop) %{
10682 match(Set dst (CMoveD (Binary cop (CmpL op1 op2)) (Binary dst src)));
10683 ins_cost(ALU_COST + BRANCH_COST);
10684
10685 format %{
10686 "CMoveD $dst, ($op1 $cop $op2), $dst, $src\t#@cmovD_cmpL\n\t"
10687 %}
10688
10689 ins_encode %{
10690 __ enc_cmove_fp_cmp($cop$$cmpcode,
10691 as_Register($op1$$reg), as_Register($op2$$reg),
10692 as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg), false /* is_single */);
10693 %}
10694
10695 ins_pipe(pipe_class_compare);
10696 %}
10697
10698 instruct cmovD_cmpUL(fRegD dst, fRegD src, iRegL op1, iRegL op2, cmpOpU cop) %{
10699 match(Set dst (CMoveD (Binary cop (CmpUL op1 op2)) (Binary dst src)));
10700 ins_cost(ALU_COST + BRANCH_COST);
10701
10702 format %{
10703 "CMoveD $dst, ($op1 $cop $op2), $dst, $src\t#@cmovD_cmpUL\n\t"
10704 %}
10705
10706 ins_encode %{
10707 __ enc_cmove_fp_cmp($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10708 as_Register($op1$$reg), as_Register($op2$$reg),
10709 as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg), false /* is_single */);
10710 %}
10711
10712 ins_pipe(pipe_class_compare);
10713 %}
10714
10715 instruct cmovD_cmpF(fRegD dst, fRegD src, fRegF op1, fRegF op2, cmpOp cop) %{
10716 match(Set dst (CMoveD (Binary cop (CmpF op1 op2)) (Binary dst src)));
10717 ins_cost(ALU_COST + BRANCH_COST);
10718
10719 format %{
10720 "CMoveD $dst, ($op1 $cop $op2), $dst, $src\t#@cmovD_cmpF\n\t"
10721 %}
10722
10723 ins_encode %{
10724 __ enc_cmove_fp_cmp_fp($cop$$cmpcode,
10725 as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg),
10726 as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg),
10727 true /* cmp_single */, false /* cmov_single */);
10728 %}
10729
10730 ins_pipe(pipe_class_compare);
10731 %}
10732
10733 instruct cmovD_cmpD(fRegD dst, fRegD src, fRegD op1, fRegD op2, cmpOp cop) %{
10734 match(Set dst (CMoveD (Binary cop (CmpD op1 op2)) (Binary dst src)));
10735 ins_cost(ALU_COST + BRANCH_COST);
10736
10737 format %{
10738 "CMoveD $dst, ($op1 $cop $op2), $dst, $src\t#@cmovD_cmpD\n\t"
10739 %}
10740
10741 ins_encode %{
10742 __ enc_cmove_fp_cmp_fp($cop$$cmpcode | C2_MacroAssembler::double_branch_mask,
10743 as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg),
10744 as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg),
10745 false /* cmp_single */, false /* cmov_single */);
10746 %}
10747
10748 ins_pipe(pipe_class_compare);
10749 %}
10750
10751 instruct cmovD_cmpN(fRegD dst, fRegD src, iRegN op1, iRegN op2, cmpOp cop) %{
10752 match(Set dst (CMoveD (Binary cop (CmpN op1 op2)) (Binary dst src)));
10753 ins_cost(ALU_COST + BRANCH_COST);
10754
10755 format %{
10756 "CMoveD $dst, ($op1 $cop $op2), $dst, $src\t#@cmovD_cmpN\n\t"
10757 %}
10758
10759 ins_encode %{
10760 __ enc_cmove_fp_cmp($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10761 as_Register($op1$$reg), as_Register($op2$$reg),
10762 as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg), false /* is_single */);
10763 %}
10764
10765 ins_pipe(pipe_class_compare);
10766 %}
10767
10768 instruct cmovD_cmpP(fRegD dst, fRegD src, iRegP op1, iRegP op2, cmpOp cop) %{
10769 match(Set dst (CMoveD (Binary cop (CmpP op1 op2)) (Binary dst src)));
10770 ins_cost(ALU_COST + BRANCH_COST);
10771
10772 format %{
10773 "CMoveD $dst, ($op1 $cop $op2), $dst, $src\t#@cmovD_cmpP\n\t"
10774 %}
10775
10776 ins_encode %{
10777 __ enc_cmove_fp_cmp($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10778 as_Register($op1$$reg), as_Register($op2$$reg),
10779 as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg), false /* is_single */);
10780 %}
10781
10782 ins_pipe(pipe_class_compare);
10783 %}
10784
10785 // ============================================================================
10786 // Procedure Call/Return Instructions
10787
10788 // Call Java Static Instruction
10789 // Note: If this code changes, the corresponding ret_addr_offset() and
10790 // compute_padding() functions will have to be adjusted.
10791 instruct CallStaticJavaDirect(method meth)
10792 %{
10793 match(CallStaticJava);
10794
10795 effect(USE meth);
10796
10797 ins_cost(BRANCH_COST);
10798
10799 format %{ "CALL,static $meth\t#@CallStaticJavaDirect" %}
10800
10801 ins_encode(riscv_enc_java_static_call(meth),
10802 riscv_enc_call_epilog);
10803
10804 ins_pipe(pipe_class_call);
10805 ins_alignment(4);
10806 %}
10807
10808 // TO HERE
10809
10810 // Call Java Dynamic Instruction
10811 // Note: If this code changes, the corresponding ret_addr_offset() and
10812 // compute_padding() functions will have to be adjusted.
10813 instruct CallDynamicJavaDirect(method meth)
10814 %{
10815 match(CallDynamicJava);
10816
10817 effect(USE meth);
10818
10819 ins_cost(BRANCH_COST + ALU_COST * 5);
10820
10821 format %{ "CALL,dynamic $meth\t#@CallDynamicJavaDirect" %}
10822
10823 ins_encode(riscv_enc_java_dynamic_call(meth),
10824 riscv_enc_call_epilog);
10825
10826 ins_pipe(pipe_class_call);
10827 ins_alignment(4);
10828 %}
10829
10830 // Call Runtime Instruction
10831
10832 instruct CallRuntimeDirect(method meth)
10833 %{
10834 match(CallRuntime);
10835
10836 effect(USE meth);
10837
10838 ins_cost(BRANCH_COST);
10839
10840 format %{ "CALL, runtime $meth\t#@CallRuntimeDirect" %}
10841
10842 ins_encode(riscv_enc_java_to_runtime(meth));
10843
10844 ins_pipe(pipe_class_call);
10845 ins_alignment(4);
10846 %}
10847
10848 // Call Runtime Instruction
10849
10850 instruct CallLeafDirect(method meth)
10851 %{
10852 match(CallLeaf);
10853
10854 effect(USE meth);
10855
10856 ins_cost(BRANCH_COST);
10857
10858 format %{ "CALL, runtime leaf $meth\t#@CallLeafDirect" %}
10859
10860 ins_encode(riscv_enc_java_to_runtime(meth));
10861
10862 ins_pipe(pipe_class_call);
10863 ins_alignment(4);
10864 %}
10865
10866 // Call Runtime Instruction without safepoint and with vector arguments
10867
10868 instruct CallLeafDirectVector(method meth)
10869 %{
10870 match(CallLeafVector);
10871
10872 effect(USE meth);
10873
10874 ins_cost(BRANCH_COST);
10875
10876 format %{ "CALL, runtime leaf vector $meth" %}
10877
10878 ins_encode(riscv_enc_java_to_runtime(meth));
10879
10880 ins_pipe(pipe_class_call);
10881 ins_alignment(4);
10882 %}
10883
10884 // Call Runtime Instruction
10885
10886 instruct CallLeafNoFPDirect(method meth)
10887 %{
10888 match(CallLeafNoFP);
10889
10890 effect(USE meth);
10891
10892 ins_cost(BRANCH_COST);
10893
10894 format %{ "CALL, runtime leaf nofp $meth\t#@CallLeafNoFPDirect" %}
10895
10896 ins_encode(riscv_enc_java_to_runtime(meth));
10897
10898 ins_pipe(pipe_class_call);
10899 ins_alignment(4);
10900 %}
10901
10902 // ============================================================================
10903 // Partial Subtype Check
10904 //
10905 // superklass array for an instance of the superklass. Set a hidden
10906 // internal cache on a hit (cache is checked with exposed code in
10907 // gen_subtype_check()). Return zero for a hit. The encoding
10908 // ALSO sets flags.
10909
10910 instruct partialSubtypeCheck(iRegP_R15 result, iRegP_R14 sub, iRegP_R10 super, iRegP_R12 tmp, rFlagsReg cr)
10911 %{
10912 predicate(!UseSecondarySupersTable);
10913 match(Set result (PartialSubtypeCheck sub super));
10914 effect(KILL tmp, KILL cr);
10915
10916 ins_cost(20 * DEFAULT_COST);
10917 format %{ "partialSubtypeCheck $result, $sub, $super\t#@partialSubtypeCheck" %}
10918
10919 ins_encode(riscv_enc_partial_subtype_check(sub, super, tmp, result));
10920
10921 opcode(0x1); // Force zero of result reg on hit
10922
10923 ins_pipe(pipe_class_memory);
10924 %}
10925
10926 // Two versions of partialSubtypeCheck, both used when we need to
10927 // search for a super class in the secondary supers array. The first
10928 // is used when we don't know _a priori_ the class being searched
10929 // for. The second, far more common, is used when we do know: this is
10930 // used for instanceof, checkcast, and any case where C2 can determine
10931 // it by constant propagation.
10932
10933 instruct partialSubtypeCheckVarSuper(iRegP_R14 sub, iRegP_R10 super, iRegP_R15 result,
10934 iRegP_R11 tmpR11, iRegP_R12 tmpR12, iRegP_R13 tmpR13,
10935 iRegP_R16 tmpR16, rFlagsReg cr)
10936 %{
10937 predicate(UseSecondarySupersTable);
10938 match(Set result (PartialSubtypeCheck sub super));
10939 effect(TEMP tmpR11, TEMP tmpR12, TEMP tmpR13, TEMP tmpR16, KILL cr);
10940
10941 ins_cost(10 * DEFAULT_COST); // slightly larger than the next version
10942 format %{ "partialSubtypeCheck $result, $sub, $super" %}
10943
10944 ins_encode %{
10945 __ lookup_secondary_supers_table_var($sub$$Register, $super$$Register, $result$$Register,
10946 $tmpR11$$Register, $tmpR12$$Register, $tmpR13$$Register,
10947 $tmpR16$$Register, nullptr /*L_success*/);
10948 %}
10949
10950 ins_pipe(pipe_class_memory);
10951 %}
10952
10953 instruct partialSubtypeCheckConstSuper(iRegP_R14 sub, iRegP_R10 super_reg, immP super_con, iRegP_R15 result,
10954 iRegP_R11 tmpR11, iRegP_R12 tmpR12, iRegP_R13 tmpR13, iRegP_R16 tmpR16, rFlagsReg cr)
10955 %{
10956 predicate(UseSecondarySupersTable);
10957 match(Set result (PartialSubtypeCheck sub (Binary super_reg super_con)));
10958 effect(TEMP tmpR11, TEMP tmpR12, TEMP tmpR13, TEMP tmpR16, KILL cr);
10959
10960 ins_cost(5 * DEFAULT_COST); // needs to be less than competing nodes
10961 format %{ "partialSubtypeCheck $result, $sub, $super_reg, $super_con" %}
10962
10963 ins_encode %{
10964 bool success = false;
10965 u1 super_klass_slot = ((Klass*)$super_con$$constant)->hash_slot();
10966 if (InlineSecondarySupersTest) {
10967 success = __ lookup_secondary_supers_table_const($sub$$Register, $super_reg$$Register, $result$$Register,
10968 $tmpR11$$Register, $tmpR12$$Register, $tmpR13$$Register,
10969 $tmpR16$$Register, super_klass_slot);
10970 } else {
10971 address call = __ reloc_call(RuntimeAddress(StubRoutines::lookup_secondary_supers_table_stub(super_klass_slot)));
10972 success = (call != nullptr);
10973 }
10974 if (!success) {
10975 ciEnv::current()->record_failure("CodeCache is full");
10976 return;
10977 }
10978 %}
10979
10980 ins_pipe(pipe_class_memory);
10981 %}
10982
10983 instruct string_compareU(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
10984 iRegI_R10 result, iRegP_R28 tmp1, iRegL_R29 tmp2, iRegL_R30 tmp3, rFlagsReg cr)
10985 %{
10986 predicate(!UseRVV && ((StrCompNode *)n)->encoding() == StrIntrinsicNode::UU);
10987 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10988 effect(KILL tmp1, KILL tmp2, KILL tmp3, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
10989
10990 format %{ "String Compare $str1, $cnt1, $str2, $cnt2 -> $result\t#@string_compareU" %}
10991 ins_encode %{
10992 // Count is in 8-bit bytes; non-Compact chars are 16 bits.
10993 __ string_compare($str1$$Register, $str2$$Register,
10994 $cnt1$$Register, $cnt2$$Register, $result$$Register,
10995 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
10996 StrIntrinsicNode::UU);
10997 %}
10998 ins_pipe(pipe_class_memory);
10999 %}
11000
11001 instruct string_compareL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
11002 iRegI_R10 result, iRegP_R28 tmp1, iRegL_R29 tmp2, iRegL_R30 tmp3, rFlagsReg cr)
11003 %{
11004 predicate(!UseRVV && ((StrCompNode *)n)->encoding() == StrIntrinsicNode::LL);
11005 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11006 effect(KILL tmp1, KILL tmp2, KILL tmp3, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11007
11008 format %{ "String Compare $str1, $cnt1, $str2, $cnt2 -> $result\t#@string_compareL" %}
11009 ins_encode %{
11010 __ string_compare($str1$$Register, $str2$$Register,
11011 $cnt1$$Register, $cnt2$$Register, $result$$Register,
11012 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
11013 StrIntrinsicNode::LL);
11014 %}
11015 ins_pipe(pipe_class_memory);
11016 %}
11017
11018 instruct string_compareUL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
11019 iRegI_R10 result, iRegP_R28 tmp1, iRegL_R29 tmp2, iRegL_R30 tmp3, rFlagsReg cr)
11020 %{
11021 predicate(!UseRVV && ((StrCompNode *)n)->encoding() == StrIntrinsicNode::UL);
11022 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11023 effect(KILL tmp1, KILL tmp2, KILL tmp3, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11024
11025 format %{"String Compare $str1, $cnt1, $str2, $cnt2 -> $result\t#@string_compareUL" %}
11026 ins_encode %{
11027 __ string_compare($str1$$Register, $str2$$Register,
11028 $cnt1$$Register, $cnt2$$Register, $result$$Register,
11029 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
11030 StrIntrinsicNode::UL);
11031 %}
11032 ins_pipe(pipe_class_memory);
11033 %}
11034
11035 instruct string_compareLU(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
11036 iRegI_R10 result, iRegP_R28 tmp1, iRegL_R29 tmp2, iRegL_R30 tmp3,
11037 rFlagsReg cr)
11038 %{
11039 predicate(!UseRVV && ((StrCompNode *)n)->encoding() == StrIntrinsicNode::LU);
11040 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11041 effect(KILL tmp1, KILL tmp2, KILL tmp3, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11042
11043 format %{ "String Compare $str1, $cnt1, $str2, $cnt2 -> $result\t#@string_compareLU" %}
11044 ins_encode %{
11045 __ string_compare($str1$$Register, $str2$$Register,
11046 $cnt1$$Register, $cnt2$$Register, $result$$Register,
11047 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
11048 StrIntrinsicNode::LU);
11049 %}
11050 ins_pipe(pipe_class_memory);
11051 %}
11052
11053 instruct string_indexofUU(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
11054 iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3,
11055 iRegINoSp tmp4, iRegINoSp tmp5, iRegINoSp tmp6, rFlagsReg cr)
11056 %{
11057 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU);
11058 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
11059 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, TEMP_DEF result,
11060 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, TEMP tmp6, KILL cr);
11061
11062 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result (UU)" %}
11063 ins_encode %{
11064 __ string_indexof($str1$$Register, $str2$$Register,
11065 $cnt1$$Register, $cnt2$$Register,
11066 $tmp1$$Register, $tmp2$$Register,
11067 $tmp3$$Register, $tmp4$$Register,
11068 $tmp5$$Register, $tmp6$$Register,
11069 $result$$Register, StrIntrinsicNode::UU);
11070 %}
11071 ins_pipe(pipe_class_memory);
11072 %}
11073
11074 instruct string_indexofLL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
11075 iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3,
11076 iRegINoSp tmp4, iRegINoSp tmp5, iRegINoSp tmp6, rFlagsReg cr)
11077 %{
11078 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL);
11079 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
11080 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, TEMP_DEF result,
11081 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, TEMP tmp6, KILL cr);
11082
11083 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result (LL)" %}
11084 ins_encode %{
11085 __ string_indexof($str1$$Register, $str2$$Register,
11086 $cnt1$$Register, $cnt2$$Register,
11087 $tmp1$$Register, $tmp2$$Register,
11088 $tmp3$$Register, $tmp4$$Register,
11089 $tmp5$$Register, $tmp6$$Register,
11090 $result$$Register, StrIntrinsicNode::LL);
11091 %}
11092 ins_pipe(pipe_class_memory);
11093 %}
11094
11095 instruct string_indexofUL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
11096 iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3,
11097 iRegINoSp tmp4, iRegINoSp tmp5, iRegINoSp tmp6, rFlagsReg cr)
11098 %{
11099 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL);
11100 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
11101 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, TEMP_DEF result,
11102 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, TEMP tmp6, KILL cr);
11103 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result (UL)" %}
11104
11105 ins_encode %{
11106 __ string_indexof($str1$$Register, $str2$$Register,
11107 $cnt1$$Register, $cnt2$$Register,
11108 $tmp1$$Register, $tmp2$$Register,
11109 $tmp3$$Register, $tmp4$$Register,
11110 $tmp5$$Register, $tmp6$$Register,
11111 $result$$Register, StrIntrinsicNode::UL);
11112 %}
11113 ins_pipe(pipe_class_memory);
11114 %}
11115
11116 instruct string_indexof_conUU(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2,
11117 immI_le_4 int_cnt2, iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2,
11118 iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
11119 %{
11120 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU);
11121 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
11122 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, TEMP_DEF result,
11123 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
11124
11125 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result (UU)" %}
11126
11127 ins_encode %{
11128 int icnt2 = (int)$int_cnt2$$constant;
11129 __ string_indexof_linearscan($str1$$Register, $str2$$Register,
11130 $cnt1$$Register, zr,
11131 $tmp1$$Register, $tmp2$$Register,
11132 $tmp3$$Register, $tmp4$$Register,
11133 icnt2, $result$$Register, StrIntrinsicNode::UU);
11134 %}
11135 ins_pipe(pipe_class_memory);
11136 %}
11137
11138 instruct string_indexof_conLL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2,
11139 immI_le_4 int_cnt2, iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2,
11140 iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
11141 %{
11142 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL);
11143 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
11144 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, TEMP_DEF result,
11145 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
11146
11147 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result (LL)" %}
11148 ins_encode %{
11149 int icnt2 = (int)$int_cnt2$$constant;
11150 __ string_indexof_linearscan($str1$$Register, $str2$$Register,
11151 $cnt1$$Register, zr,
11152 $tmp1$$Register, $tmp2$$Register,
11153 $tmp3$$Register, $tmp4$$Register,
11154 icnt2, $result$$Register, StrIntrinsicNode::LL);
11155 %}
11156 ins_pipe(pipe_class_memory);
11157 %}
11158
11159 instruct string_indexof_conUL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2,
11160 immI_1 int_cnt2, iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2,
11161 iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
11162 %{
11163 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL);
11164 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
11165 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, TEMP_DEF result,
11166 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
11167
11168 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result (UL)" %}
11169 ins_encode %{
11170 int icnt2 = (int)$int_cnt2$$constant;
11171 __ string_indexof_linearscan($str1$$Register, $str2$$Register,
11172 $cnt1$$Register, zr,
11173 $tmp1$$Register, $tmp2$$Register,
11174 $tmp3$$Register, $tmp4$$Register,
11175 icnt2, $result$$Register, StrIntrinsicNode::UL);
11176 %}
11177 ins_pipe(pipe_class_memory);
11178 %}
11179
11180 instruct stringU_indexof_char(iRegP_R11 str1, iRegI_R12 cnt1, iRegI_R13 ch,
11181 iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2,
11182 iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
11183 %{
11184 match(Set result (StrIndexOfChar (Binary str1 cnt1) ch));
11185 predicate(!UseRVV && (((StrIndexOfCharNode*)n)->encoding() == StrIntrinsicNode::U));
11186 effect(USE_KILL str1, USE_KILL cnt1, USE_KILL ch, TEMP_DEF result,
11187 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
11188
11189 format %{ "StringUTF16 IndexOf char[] $str1, $cnt1, $ch -> $result" %}
11190 ins_encode %{
11191 __ string_indexof_char($str1$$Register, $cnt1$$Register, $ch$$Register,
11192 $result$$Register, $tmp1$$Register, $tmp2$$Register,
11193 $tmp3$$Register, $tmp4$$Register, false /* isU */);
11194 %}
11195 ins_pipe(pipe_class_memory);
11196 %}
11197
11198
11199 instruct stringL_indexof_char(iRegP_R11 str1, iRegI_R12 cnt1, iRegI_R13 ch,
11200 iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2,
11201 iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
11202 %{
11203 match(Set result (StrIndexOfChar (Binary str1 cnt1) ch));
11204 predicate(!UseRVV && (((StrIndexOfCharNode*)n)->encoding() == StrIntrinsicNode::L));
11205 effect(USE_KILL str1, USE_KILL cnt1, USE_KILL ch, TEMP_DEF result,
11206 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
11207
11208 format %{ "StringLatin1 IndexOf char[] $str1, $cnt1, $ch -> $result" %}
11209 ins_encode %{
11210 __ string_indexof_char($str1$$Register, $cnt1$$Register, $ch$$Register,
11211 $result$$Register, $tmp1$$Register, $tmp2$$Register,
11212 $tmp3$$Register, $tmp4$$Register, true /* isL */);
11213 %}
11214 ins_pipe(pipe_class_memory);
11215 %}
11216
11217 // clearing of an array
11218 instruct clearArray_reg_reg(iRegL_R29 cnt, iRegP_R28 base, iRegP_R30 tmp1,
11219 iRegP_R31 tmp2, rFlagsReg cr, Universe dummy)
11220 %{
11221 // temp registers must match the one used in StubGenerator::generate_zero_blocks()
11222 predicate(UseBlockZeroing || !UseRVV);
11223 match(Set dummy (ClearArray cnt base));
11224 effect(USE_KILL cnt, USE_KILL base, TEMP tmp1, TEMP tmp2, KILL cr);
11225
11226 ins_cost(4 * DEFAULT_COST);
11227 format %{ "ClearArray $cnt, $base\t#@clearArray_reg_reg" %}
11228
11229 ins_encode %{
11230 address tpc = __ zero_words($base$$Register, $cnt$$Register);
11231 if (tpc == nullptr) {
11232 ciEnv::current()->record_failure("CodeCache is full");
11233 return;
11234 }
11235 %}
11236
11237 ins_pipe(pipe_class_memory);
11238 %}
11239
11240 instruct clearArray_imm_reg(immL cnt, iRegP_R28 base, Universe dummy, rFlagsReg cr)
11241 %{
11242 predicate(!UseRVV && (uint64_t)n->in(2)->get_long()
11243 < (uint64_t)(BlockZeroingLowLimit >> LogBytesPerWord));
11244 match(Set dummy (ClearArray cnt base));
11245 effect(USE_KILL base, KILL cr);
11246
11247 ins_cost(4 * DEFAULT_COST);
11248 format %{ "ClearArray $cnt, $base\t#@clearArray_imm_reg" %}
11249
11250 ins_encode %{
11251 __ zero_words($base$$Register, (uint64_t)$cnt$$constant);
11252 %}
11253
11254 ins_pipe(pipe_class_memory);
11255 %}
11256
11257 instruct string_equalsL(iRegP_R11 str1, iRegP_R13 str2, iRegI_R14 cnt,
11258 iRegI_R10 result, rFlagsReg cr)
11259 %{
11260 predicate(!UseRVV && ((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::LL);
11261 match(Set result (StrEquals (Binary str1 str2) cnt));
11262 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL cr);
11263
11264 format %{ "String Equals $str1, $str2, $cnt -> $result\t#@string_equalsL" %}
11265 ins_encode %{
11266 // Count is in 8-bit bytes; non-Compact chars are 16 bits.
11267 __ string_equals($str1$$Register, $str2$$Register,
11268 $result$$Register, $cnt$$Register);
11269 %}
11270 ins_pipe(pipe_class_memory);
11271 %}
11272
11273 instruct array_equalsB(iRegP_R11 ary1, iRegP_R12 ary2, iRegI_R10 result,
11274 iRegP_R13 tmp1, iRegP_R14 tmp2, iRegP_R15 tmp3)
11275 %{
11276 predicate(!UseRVV && ((AryEqNode*)n)->encoding() == StrIntrinsicNode::LL);
11277 match(Set result (AryEq ary1 ary2));
11278 effect(USE_KILL ary1, USE_KILL ary2, TEMP tmp1, TEMP tmp2, TEMP tmp3);
11279
11280 format %{ "Array Equals $ary1, $ary2 -> $result\t#@array_equalsB // KILL all" %}
11281 ins_encode %{
11282 __ arrays_equals($ary1$$Register, $ary2$$Register,
11283 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
11284 $result$$Register, 1);
11285 %}
11286 ins_pipe(pipe_class_memory);
11287 %}
11288
11289 instruct array_equalsC(iRegP_R11 ary1, iRegP_R12 ary2, iRegI_R10 result,
11290 iRegP_R13 tmp1, iRegP_R14 tmp2, iRegP_R15 tmp3)
11291 %{
11292 predicate(!UseRVV && ((AryEqNode*)n)->encoding() == StrIntrinsicNode::UU);
11293 match(Set result (AryEq ary1 ary2));
11294 effect(USE_KILL ary1, USE_KILL ary2, TEMP tmp1, TEMP tmp2, TEMP tmp3);
11295
11296 format %{ "Array Equals $ary1, $ary2 -> $result\t#@array_equalsC // KILL all" %}
11297 ins_encode %{
11298 __ arrays_equals($ary1$$Register, $ary2$$Register,
11299 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
11300 $result$$Register, 2);
11301 %}
11302 ins_pipe(pipe_class_memory);
11303 %}
11304
11305 // fast ArraysSupport.vectorizedHashCode
11306 instruct arrays_hashcode(iRegP_R11 ary, iRegI_R12 cnt, iRegI_R10 result, immI basic_type,
11307 iRegLNoSp tmp1, iRegLNoSp tmp2,
11308 iRegLNoSp tmp3, iRegLNoSp tmp4,
11309 iRegLNoSp tmp5, iRegLNoSp tmp6, rFlagsReg cr)
11310 %{
11311 predicate(!UseRVV);
11312 match(Set result (VectorizedHashCode (Binary ary cnt) (Binary result basic_type)));
11313 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, TEMP tmp6,
11314 USE_KILL ary, USE_KILL cnt, USE basic_type, KILL cr);
11315
11316 format %{ "Array HashCode array[] $ary,$cnt,$result,$basic_type -> $result // KILL all" %}
11317 ins_encode %{
11318 __ arrays_hashcode($ary$$Register, $cnt$$Register, $result$$Register,
11319 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
11320 $tmp4$$Register, $tmp5$$Register, $tmp6$$Register,
11321 (BasicType)$basic_type$$constant);
11322 %}
11323 ins_pipe(pipe_class_memory);
11324 %}
11325
11326 // ============================================================================
11327 // Safepoint Instructions
11328
11329 instruct safePoint(iRegP poll)
11330 %{
11331 match(SafePoint poll);
11332
11333 ins_cost(2 * LOAD_COST);
11334 format %{
11335 "lwu zr, [$poll]\t# Safepoint: poll for GC, #@safePoint"
11336 %}
11337 ins_encode %{
11338 __ read_polling_page(as_Register($poll$$reg), 0, relocInfo::poll_type);
11339 %}
11340 ins_pipe(pipe_serial); // ins_pipe(iload_reg_mem);
11341 %}
11342
11343 // ============================================================================
11344 // This name is KNOWN by the ADLC and cannot be changed.
11345 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
11346 // for this guy.
11347 instruct tlsLoadP(javaThread_RegP dst)
11348 %{
11349 match(Set dst (ThreadLocal));
11350
11351 ins_cost(0);
11352
11353 format %{ " -- \t// $dst=Thread::current(), empty, #@tlsLoadP" %}
11354
11355 size(0);
11356
11357 ins_encode( /*empty*/ );
11358
11359 ins_pipe(pipe_class_empty);
11360 %}
11361
11362 // inlined locking and unlocking
11363 // using t1 as the 'flag' register to bridge the BoolNode producers and consumers
11364 instruct cmpFastLock(rFlagsReg cr, iRegP object, iRegP box,
11365 iRegPNoSp tmp1, iRegPNoSp tmp2, iRegPNoSp tmp3, iRegPNoSp tmp4)
11366 %{
11367 match(Set cr (FastLock object box));
11368 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4);
11369
11370 ins_cost(10 * DEFAULT_COST);
11371 format %{ "fastlock $object,$box\t! kills $tmp1,$tmp2,$tmp3,$tmp4 #@cmpFastLock" %}
11372
11373 ins_encode %{
11374 __ fast_lock($object$$Register, $box$$Register,
11375 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register);
11376 %}
11377
11378 ins_pipe(pipe_serial);
11379 %}
11380
11381 // using t1 as the 'flag' register to bridge the BoolNode producers and consumers
11382 instruct cmpFastUnlock(rFlagsReg cr, iRegP object, iRegP box,
11383 iRegPNoSp tmp1, iRegPNoSp tmp2, iRegPNoSp tmp3)
11384 %{
11385 match(Set cr (FastUnlock object box));
11386 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3);
11387
11388 ins_cost(10 * DEFAULT_COST);
11389 format %{ "fastunlock $object,$box\t! kills $tmp1,$tmp2,$tmp3 #@cmpFastUnlock" %}
11390
11391 ins_encode %{
11392 __ fast_unlock($object$$Register, $box$$Register,
11393 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
11394 %}
11395
11396 ins_pipe(pipe_serial);
11397 %}
11398
11399 // Tail Call; Jump from runtime stub to Java code.
11400 // Also known as an 'interprocedural jump'.
11401 // Target of jump will eventually return to caller.
11402 // TailJump below removes the return address.
11403 // Don't use fp for 'jump_target' because a MachEpilogNode has already been
11404 // emitted just above the TailCall which has reset fp to the caller state.
11405 instruct TailCalljmpInd(iRegPNoSpNoFp jump_target, inline_cache_RegP method_oop)
11406 %{
11407 match(TailCall jump_target method_oop);
11408
11409 ins_cost(BRANCH_COST);
11410
11411 format %{ "jalr $jump_target\t# $method_oop holds method oop, #@TailCalljmpInd." %}
11412
11413 ins_encode(riscv_enc_tail_call(jump_target));
11414
11415 ins_pipe(pipe_class_call);
11416 %}
11417
11418 instruct TailjmpInd(iRegPNoSpNoFp jump_target, iRegP_R10 ex_oop)
11419 %{
11420 match(TailJump jump_target ex_oop);
11421
11422 ins_cost(ALU_COST + BRANCH_COST);
11423
11424 format %{ "jalr $jump_target\t# $ex_oop holds exception oop, #@TailjmpInd." %}
11425
11426 ins_encode(riscv_enc_tail_jmp(jump_target));
11427
11428 ins_pipe(pipe_class_call);
11429 %}
11430
11431 // Forward exception.
11432 instruct ForwardExceptionjmp()
11433 %{
11434 match(ForwardException);
11435
11436 ins_cost(BRANCH_COST);
11437
11438 format %{ "j forward_exception_stub\t#@ForwardException" %}
11439
11440 ins_encode %{
11441 __ far_jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
11442 %}
11443
11444 ins_pipe(pipe_class_call);
11445 %}
11446
11447 // Create exception oop: created by stack-crawling runtime code.
11448 // Created exception is now available to this handler, and is setup
11449 // just prior to jumping to this handler. No code emitted.
11450 instruct CreateException(iRegP_R10 ex_oop)
11451 %{
11452 match(Set ex_oop (CreateEx));
11453
11454 ins_cost(0);
11455 format %{ " -- \t// exception oop; no code emitted, #@CreateException" %}
11456
11457 size(0);
11458
11459 ins_encode( /*empty*/ );
11460
11461 ins_pipe(pipe_class_empty);
11462 %}
11463
11464 // Rethrow exception: The exception oop will come in the first
11465 // argument position. Then JUMP (not call) to the rethrow stub code.
11466 instruct RethrowException()
11467 %{
11468 match(Rethrow);
11469
11470 ins_cost(BRANCH_COST);
11471
11472 format %{ "j rethrow_stub\t#@RethrowException" %}
11473
11474 ins_encode(riscv_enc_rethrow());
11475
11476 ins_pipe(pipe_class_call);
11477 %}
11478
11479 // Return Instruction
11480 // epilog node loads ret address into ra as part of frame pop
11481 instruct Ret()
11482 %{
11483 match(Return);
11484
11485 ins_cost(BRANCH_COST);
11486 format %{ "ret\t// return register, #@Ret" %}
11487
11488 ins_encode(riscv_enc_ret());
11489
11490 ins_pipe(pipe_branch);
11491 %}
11492
11493 // Die now.
11494 instruct ShouldNotReachHere() %{
11495 match(Halt);
11496
11497 ins_cost(BRANCH_COST);
11498
11499 format %{ "#@ShouldNotReachHere" %}
11500
11501 ins_encode %{
11502 if (is_reachable()) {
11503 const char* str = __ code_string(_halt_reason);
11504 __ stop(str);
11505 }
11506 %}
11507
11508 ins_pipe(pipe_class_default);
11509 %}
11510
11511
11512 //----------PEEPHOLE RULES-----------------------------------------------------
11513 // These must follow all instruction definitions as they use the names
11514 // defined in the instructions definitions.
11515 //
11516 // peepmatch ( root_instr_name [preceding_instruction]* );
11517 //
11518 // peepconstraint %{
11519 // (instruction_number.operand_name relational_op instruction_number.operand_name
11520 // [, ...] );
11521 // // instruction numbers are zero-based using left to right order in peepmatch
11522 //
11523 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
11524 // // provide an instruction_number.operand_name for each operand that appears
11525 // // in the replacement instruction's match rule
11526 //
11527 // ---------VM FLAGS---------------------------------------------------------
11528 //
11529 // All peephole optimizations can be turned off using -XX:-OptoPeephole
11530 //
11531 // Each peephole rule is given an identifying number starting with zero and
11532 // increasing by one in the order seen by the parser. An individual peephole
11533 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
11534 // on the command-line.
11535 //
11536 // ---------CURRENT LIMITATIONS----------------------------------------------
11537 //
11538 // Only match adjacent instructions in same basic block
11539 // Only equality constraints
11540 // Only constraints between operands, not (0.dest_reg == RAX_enc)
11541 // Only one replacement instruction
11542 //
11543 //----------SMARTSPILL RULES---------------------------------------------------
11544 // These must follow all instruction definitions as they use the names
11545 // defined in the instructions definitions.
11546
11547 // Local Variables:
11548 // mode: c++
11549 // End: