1 /*
2 * Copyright (c) 2000, 2022, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/macroAssembler.hpp"
27 #include "asm/macroAssembler.inline.hpp"
28 #include "c1/c1_CodeStubs.hpp"
29 #include "c1/c1_Compilation.hpp"
30 #include "c1/c1_LIRAssembler.hpp"
31 #include "c1/c1_MacroAssembler.hpp"
32 #include "c1/c1_Runtime1.hpp"
33 #include "c1/c1_ValueStack.hpp"
34 #include "ci/ciArrayKlass.hpp"
35 #include "ci/ciInstance.hpp"
36 #include "compiler/oopMap.hpp"
37 #include "gc/shared/collectedHeap.hpp"
38 #include "gc/shared/gc_globals.hpp"
39 #include "nativeInst_x86.hpp"
40 #include "oops/objArrayKlass.hpp"
41 #include "runtime/frame.inline.hpp"
42 #include "runtime/safepointMechanism.hpp"
43 #include "runtime/sharedRuntime.hpp"
44 #include "runtime/stubRoutines.hpp"
45 #include "utilities/powerOfTwo.hpp"
46 #include "vmreg_x86.inline.hpp"
47
48
49 // These masks are used to provide 128-bit aligned bitmasks to the XMM
50 // instructions, to allow sign-masking or sign-bit flipping. They allow
51 // fast versions of NegF/NegD and AbsF/AbsD.
52
53 // Note: 'double' and 'long long' have 32-bits alignment on x86.
54 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) {
55 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address
56 // of 128-bits operands for SSE instructions.
57 jlong *operand = (jlong*)(((intptr_t)adr) & ((intptr_t)(~0xF)));
58 // Store the value to a 128-bits operand.
59 operand[0] = lo;
60 operand[1] = hi;
61 return operand;
62 }
63
64 // Buffer for 128-bits masks used by SSE instructions.
65 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment)
66
67 // Static initialization during VM startup.
68 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF));
69 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF));
70 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], (jlong)UCONST64(0x8000000080000000), (jlong)UCONST64(0x8000000080000000));
71 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], (jlong)UCONST64(0x8000000000000000), (jlong)UCONST64(0x8000000000000000));
72
73
74 NEEDS_CLEANUP // remove this definitions ?
75 const Register IC_Klass = rax; // where the IC klass is cached
76 const Register SYNC_header = rax; // synchronization header
77 const Register SHIFT_count = rcx; // where count for shift operations must be
78
79 #define __ _masm->
80
81
82 static void select_different_registers(Register preserve,
83 Register extra,
84 Register &tmp1,
85 Register &tmp2) {
86 if (tmp1 == preserve) {
87 assert_different_registers(tmp1, tmp2, extra);
88 tmp1 = extra;
89 } else if (tmp2 == preserve) {
90 assert_different_registers(tmp1, tmp2, extra);
91 tmp2 = extra;
92 }
93 assert_different_registers(preserve, tmp1, tmp2);
94 }
95
96
97
98 static void select_different_registers(Register preserve,
99 Register extra,
100 Register &tmp1,
101 Register &tmp2,
102 Register &tmp3) {
103 if (tmp1 == preserve) {
104 assert_different_registers(tmp1, tmp2, tmp3, extra);
105 tmp1 = extra;
106 } else if (tmp2 == preserve) {
107 assert_different_registers(tmp1, tmp2, tmp3, extra);
108 tmp2 = extra;
109 } else if (tmp3 == preserve) {
110 assert_different_registers(tmp1, tmp2, tmp3, extra);
111 tmp3 = extra;
112 }
113 assert_different_registers(preserve, tmp1, tmp2, tmp3);
114 }
115
116
117
118 bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
119 if (opr->is_constant()) {
120 LIR_Const* constant = opr->as_constant_ptr();
121 switch (constant->type()) {
122 case T_INT: {
123 return true;
124 }
125
126 default:
127 return false;
128 }
129 }
130 return false;
131 }
132
133
134 LIR_Opr LIR_Assembler::receiverOpr() {
135 return FrameMap::receiver_opr;
136 }
137
138 LIR_Opr LIR_Assembler::osrBufferPointer() {
139 return FrameMap::as_pointer_opr(receiverOpr()->as_register());
140 }
141
142 //--------------fpu register translations-----------------------
143
144
145 address LIR_Assembler::float_constant(float f) {
146 address const_addr = __ float_constant(f);
147 if (const_addr == NULL) {
148 bailout("const section overflow");
149 return __ code()->consts()->start();
150 } else {
151 return const_addr;
152 }
153 }
154
155
156 address LIR_Assembler::double_constant(double d) {
157 address const_addr = __ double_constant(d);
158 if (const_addr == NULL) {
159 bailout("const section overflow");
160 return __ code()->consts()->start();
161 } else {
162 return const_addr;
163 }
164 }
165
166 #ifndef _LP64
167 void LIR_Assembler::fpop() {
168 __ fpop();
169 }
170
171 void LIR_Assembler::fxch(int i) {
172 __ fxch(i);
173 }
174
175 void LIR_Assembler::fld(int i) {
176 __ fld_s(i);
177 }
178
179 void LIR_Assembler::ffree(int i) {
180 __ ffree(i);
181 }
182 #endif // !_LP64
183
184 void LIR_Assembler::breakpoint() {
185 __ int3();
186 }
187
188 void LIR_Assembler::push(LIR_Opr opr) {
189 if (opr->is_single_cpu()) {
190 __ push_reg(opr->as_register());
191 } else if (opr->is_double_cpu()) {
192 NOT_LP64(__ push_reg(opr->as_register_hi()));
193 __ push_reg(opr->as_register_lo());
194 } else if (opr->is_stack()) {
195 __ push_addr(frame_map()->address_for_slot(opr->single_stack_ix()));
196 } else if (opr->is_constant()) {
197 LIR_Const* const_opr = opr->as_constant_ptr();
198 if (const_opr->type() == T_OBJECT) {
199 __ push_oop(const_opr->as_jobject(), rscratch1);
200 } else if (const_opr->type() == T_INT) {
201 __ push_jint(const_opr->as_jint());
202 } else {
203 ShouldNotReachHere();
204 }
205
206 } else {
207 ShouldNotReachHere();
208 }
209 }
210
211 void LIR_Assembler::pop(LIR_Opr opr) {
212 if (opr->is_single_cpu()) {
213 __ pop_reg(opr->as_register());
214 } else {
215 ShouldNotReachHere();
216 }
217 }
218
219 bool LIR_Assembler::is_literal_address(LIR_Address* addr) {
220 return addr->base()->is_illegal() && addr->index()->is_illegal();
221 }
222
223 //-------------------------------------------
224
225 Address LIR_Assembler::as_Address(LIR_Address* addr) {
226 return as_Address(addr, rscratch1);
227 }
228
229 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) {
230 if (addr->base()->is_illegal()) {
231 assert(addr->index()->is_illegal(), "must be illegal too");
232 AddressLiteral laddr((address)addr->disp(), relocInfo::none);
233 if (! __ reachable(laddr)) {
234 __ movptr(tmp, laddr.addr());
235 Address res(tmp, 0);
236 return res;
237 } else {
238 return __ as_Address(laddr);
239 }
240 }
241
242 Register base = addr->base()->as_pointer_register();
243
244 if (addr->index()->is_illegal()) {
245 return Address( base, addr->disp());
246 } else if (addr->index()->is_cpu_register()) {
247 Register index = addr->index()->as_pointer_register();
248 return Address(base, index, (Address::ScaleFactor) addr->scale(), addr->disp());
249 } else if (addr->index()->is_constant()) {
250 intptr_t addr_offset = (addr->index()->as_constant_ptr()->as_jint() << addr->scale()) + addr->disp();
251 assert(Assembler::is_simm32(addr_offset), "must be");
252
253 return Address(base, addr_offset);
254 } else {
255 Unimplemented();
256 return Address();
257 }
258 }
259
260
261 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
262 Address base = as_Address(addr);
263 return Address(base._base, base._index, base._scale, base._disp + BytesPerWord);
264 }
265
266
267 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
268 return as_Address(addr);
269 }
270
271
272 void LIR_Assembler::osr_entry() {
273 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
274 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
275 ValueStack* entry_state = osr_entry->state();
276 int number_of_locks = entry_state->locks_size();
277
278 // we jump here if osr happens with the interpreter
279 // state set up to continue at the beginning of the
280 // loop that triggered osr - in particular, we have
281 // the following registers setup:
282 //
283 // rcx: osr buffer
284 //
285
286 // build frame
287 ciMethod* m = compilation()->method();
288 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
289
290 // OSR buffer is
291 //
292 // locals[nlocals-1..0]
293 // monitors[0..number_of_locks]
294 //
295 // locals is a direct copy of the interpreter frame so in the osr buffer
296 // so first slot in the local array is the last local from the interpreter
297 // and last slot is local[0] (receiver) from the interpreter
298 //
299 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
300 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
301 // in the interpreter frame (the method lock if a sync method)
302
303 // Initialize monitors in the compiled activation.
304 // rcx: pointer to osr buffer
305 //
306 // All other registers are dead at this point and the locals will be
307 // copied into place by code emitted in the IR.
308
309 Register OSR_buf = osrBufferPointer()->as_pointer_register();
310 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
311 int monitor_offset = BytesPerWord * method()->max_locals() +
312 (BasicObjectLock::size() * BytesPerWord) * (number_of_locks - 1);
313 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
314 // the OSR buffer using 2 word entries: first the lock and then
315 // the oop.
316 for (int i = 0; i < number_of_locks; i++) {
317 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
318 #ifdef ASSERT
319 // verify the interpreter's monitor has a non-null object
320 {
321 Label L;
322 __ cmpptr(Address(OSR_buf, slot_offset + 1*BytesPerWord), NULL_WORD);
323 __ jcc(Assembler::notZero, L);
324 __ stop("locked object is NULL");
325 __ bind(L);
326 }
327 #endif
328 __ movptr(rbx, Address(OSR_buf, slot_offset + 0));
329 __ movptr(frame_map()->address_for_monitor_lock(i), rbx);
330 __ movptr(rbx, Address(OSR_buf, slot_offset + 1*BytesPerWord));
331 __ movptr(frame_map()->address_for_monitor_object(i), rbx);
332 }
333 }
334 }
335
336
337 // inline cache check; done before the frame is built.
338 int LIR_Assembler::check_icache() {
339 Register receiver = FrameMap::receiver_opr->as_register();
340 Register ic_klass = IC_Klass;
341 const int ic_cmp_size = LP64_ONLY(10) NOT_LP64(9);
342 const bool do_post_padding = VerifyOops || UseCompressedClassPointers;
343 if (!do_post_padding) {
344 // insert some nops so that the verified entry point is aligned on CodeEntryAlignment
345 __ align(CodeEntryAlignment, __ offset() + ic_cmp_size);
346 }
347 int offset = __ offset();
348 __ inline_cache_check(receiver, IC_Klass);
349 assert(__ offset() % CodeEntryAlignment == 0 || do_post_padding, "alignment must be correct");
350 if (do_post_padding) {
351 // force alignment after the cache check.
352 // It's been verified to be aligned if !VerifyOops
353 __ align(CodeEntryAlignment);
354 }
355 return offset;
356 }
357
358 void LIR_Assembler::clinit_barrier(ciMethod* method) {
359 assert(VM_Version::supports_fast_class_init_checks(), "sanity");
360 assert(!method->holder()->is_not_initialized(), "initialization should have been started");
361
362 Label L_skip_barrier;
363 Register klass = rscratch1;
364 Register thread = LP64_ONLY( r15_thread ) NOT_LP64( noreg );
365 assert(thread != noreg, "x86_32 not implemented");
366
367 __ mov_metadata(klass, method->holder()->constant_encoding());
368 __ clinit_barrier(klass, thread, &L_skip_barrier /*L_fast_path*/);
369
370 __ jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub()));
371
372 __ bind(L_skip_barrier);
373 }
374
375 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo* info) {
376 jobject o = NULL;
377 PatchingStub* patch = new PatchingStub(_masm, patching_id(info));
378 __ movoop(reg, o);
379 patching_epilog(patch, lir_patch_normal, reg, info);
380 }
381
382 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) {
383 Metadata* o = NULL;
384 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id);
385 __ mov_metadata(reg, o);
386 patching_epilog(patch, lir_patch_normal, reg, info);
387 }
388
389 // This specifies the rsp decrement needed to build the frame
390 int LIR_Assembler::initial_frame_size_in_bytes() const {
391 // if rounding, must let FrameMap know!
392
393 // The frame_map records size in slots (32bit word)
394
395 // subtract two words to account for return address and link
396 return (frame_map()->framesize() - (2*VMRegImpl::slots_per_word)) * VMRegImpl::stack_slot_size;
397 }
398
399
400 int LIR_Assembler::emit_exception_handler() {
401 // generate code for exception handler
402 address handler_base = __ start_a_stub(exception_handler_size());
403 if (handler_base == NULL) {
404 // not enough space left for the handler
405 bailout("exception handler overflow");
406 return -1;
407 }
408
409 int offset = code_offset();
410
411 // the exception oop and pc are in rax, and rdx
412 // no other registers need to be preserved, so invalidate them
413 __ invalidate_registers(false, true, true, false, true, true);
414
415 // check that there is really an exception
416 __ verify_not_null_oop(rax);
417
418 // search an exception handler (rax: exception oop, rdx: throwing pc)
419 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::handle_exception_from_callee_id)));
420 __ should_not_reach_here();
421 guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
422 __ end_a_stub();
423
424 return offset;
425 }
426
427
428 // Emit the code to remove the frame from the stack in the exception
429 // unwind path.
430 int LIR_Assembler::emit_unwind_handler() {
431 #ifndef PRODUCT
432 if (CommentedAssembly) {
433 _masm->block_comment("Unwind handler");
434 }
435 #endif
436
437 int offset = code_offset();
438
439 // Fetch the exception from TLS and clear out exception related thread state
440 Register thread = NOT_LP64(rsi) LP64_ONLY(r15_thread);
441 NOT_LP64(__ get_thread(thread));
442 __ movptr(rax, Address(thread, JavaThread::exception_oop_offset()));
443 __ movptr(Address(thread, JavaThread::exception_oop_offset()), NULL_WORD);
444 __ movptr(Address(thread, JavaThread::exception_pc_offset()), NULL_WORD);
445
446 __ bind(_unwind_handler_entry);
447 __ verify_not_null_oop(rax);
448 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
449 __ mov(rbx, rax); // Preserve the exception (rbx is always callee-saved)
450 }
451
452 // Perform needed unlocking
453 MonitorExitStub* stub = NULL;
454 if (method()->is_synchronized()) {
455 monitor_address(0, FrameMap::rax_opr);
456 stub = new MonitorExitStub(FrameMap::rax_opr, true, 0);
457 if (UseHeavyMonitors) {
458 __ jmp(*stub->entry());
459 } else {
460 __ unlock_object(rdi, rsi, rax, *stub->entry());
461 }
462 __ bind(*stub->continuation());
463 }
464
465 if (compilation()->env()->dtrace_method_probes()) {
466 #ifdef _LP64
467 __ mov(rdi, r15_thread);
468 __ mov_metadata(rsi, method()->constant_encoding());
469 #else
470 __ get_thread(rax);
471 __ movptr(Address(rsp, 0), rax);
472 __ mov_metadata(Address(rsp, sizeof(void*)), method()->constant_encoding(), noreg);
473 #endif
474 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit)));
475 }
476
477 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
478 __ mov(rax, rbx); // Restore the exception
479 }
480
481 // remove the activation and dispatch to the unwind handler
482 __ remove_frame(initial_frame_size_in_bytes());
483 __ jump(RuntimeAddress(Runtime1::entry_for(Runtime1::unwind_exception_id)));
484
485 // Emit the slow path assembly
486 if (stub != NULL) {
487 stub->emit_code(this);
488 }
489
490 return offset;
491 }
492
493
494 int LIR_Assembler::emit_deopt_handler() {
495 // generate code for exception handler
496 address handler_base = __ start_a_stub(deopt_handler_size());
497 if (handler_base == NULL) {
498 // not enough space left for the handler
499 bailout("deopt handler overflow");
500 return -1;
501 }
502
503 int offset = code_offset();
504 InternalAddress here(__ pc());
505
506 __ pushptr(here.addr(), rscratch1);
507 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
508 guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
509 __ end_a_stub();
510
511 return offset;
512 }
513
514 void LIR_Assembler::return_op(LIR_Opr result, C1SafepointPollStub* code_stub) {
515 assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == rax, "word returns are in rax,");
516 if (!result->is_illegal() && result->is_float_kind() && !result->is_xmm_register()) {
517 assert(result->fpu() == 0, "result must already be on TOS");
518 }
519
520 // Pop the stack before the safepoint code
521 __ remove_frame(initial_frame_size_in_bytes());
522
523 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
524 __ reserved_stack_check();
525 }
526
527 // Note: we do not need to round double result; float result has the right precision
528 // the poll sets the condition code, but no data registers
529
530 #ifdef _LP64
531 const Register thread = r15_thread;
532 #else
533 const Register thread = rbx;
534 __ get_thread(thread);
535 #endif
536 code_stub->set_safepoint_offset(__ offset());
537 __ relocate(relocInfo::poll_return_type);
538 __ safepoint_poll(*code_stub->entry(), thread, true /* at_return */, true /* in_nmethod */);
539 __ ret(0);
540 }
541
542
543 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
544 guarantee(info != NULL, "Shouldn't be NULL");
545 int offset = __ offset();
546 #ifdef _LP64
547 const Register poll_addr = rscratch1;
548 __ movptr(poll_addr, Address(r15_thread, JavaThread::polling_page_offset()));
549 #else
550 assert(tmp->is_cpu_register(), "needed");
551 const Register poll_addr = tmp->as_register();
552 __ get_thread(poll_addr);
553 __ movptr(poll_addr, Address(poll_addr, in_bytes(JavaThread::polling_page_offset())));
554 #endif
555 add_debug_info_for_branch(info);
556 __ relocate(relocInfo::poll_type);
557 address pre_pc = __ pc();
558 __ testl(rax, Address(poll_addr, 0));
559 address post_pc = __ pc();
560 guarantee(pointer_delta(post_pc, pre_pc, 1) == 2 LP64_ONLY(+1), "must be exact length");
561 return offset;
562 }
563
564
565 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
566 if (from_reg != to_reg) __ mov(to_reg, from_reg);
567 }
568
569 void LIR_Assembler::swap_reg(Register a, Register b) {
570 __ xchgptr(a, b);
571 }
572
573
574 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
575 assert(src->is_constant(), "should not call otherwise");
576 assert(dest->is_register(), "should not call otherwise");
577 LIR_Const* c = src->as_constant_ptr();
578
579 switch (c->type()) {
580 case T_INT: {
581 assert(patch_code == lir_patch_none, "no patching handled here");
582 __ movl(dest->as_register(), c->as_jint());
583 break;
584 }
585
586 case T_ADDRESS: {
587 assert(patch_code == lir_patch_none, "no patching handled here");
588 __ movptr(dest->as_register(), c->as_jint());
589 break;
590 }
591
592 case T_LONG: {
593 assert(patch_code == lir_patch_none, "no patching handled here");
594 #ifdef _LP64
595 __ movptr(dest->as_register_lo(), (intptr_t)c->as_jlong());
596 #else
597 __ movptr(dest->as_register_lo(), c->as_jint_lo());
598 __ movptr(dest->as_register_hi(), c->as_jint_hi());
599 #endif // _LP64
600 break;
601 }
602
603 case T_OBJECT: {
604 if (patch_code != lir_patch_none) {
605 jobject2reg_with_patching(dest->as_register(), info);
606 } else {
607 __ movoop(dest->as_register(), c->as_jobject());
608 }
609 break;
610 }
611
612 case T_METADATA: {
613 if (patch_code != lir_patch_none) {
614 klass2reg_with_patching(dest->as_register(), info);
615 } else {
616 __ mov_metadata(dest->as_register(), c->as_metadata());
617 }
618 break;
619 }
620
621 case T_FLOAT: {
622 if (dest->is_single_xmm()) {
623 if (LP64_ONLY(UseAVX <= 2 &&) c->is_zero_float()) {
624 __ xorps(dest->as_xmm_float_reg(), dest->as_xmm_float_reg());
625 } else {
626 __ movflt(dest->as_xmm_float_reg(),
627 InternalAddress(float_constant(c->as_jfloat())));
628 }
629 } else {
630 #ifndef _LP64
631 assert(dest->is_single_fpu(), "must be");
632 assert(dest->fpu_regnr() == 0, "dest must be TOS");
633 if (c->is_zero_float()) {
634 __ fldz();
635 } else if (c->is_one_float()) {
636 __ fld1();
637 } else {
638 __ fld_s (InternalAddress(float_constant(c->as_jfloat())));
639 }
640 #else
641 ShouldNotReachHere();
642 #endif // !_LP64
643 }
644 break;
645 }
646
647 case T_DOUBLE: {
648 if (dest->is_double_xmm()) {
649 if (LP64_ONLY(UseAVX <= 2 &&) c->is_zero_double()) {
650 __ xorpd(dest->as_xmm_double_reg(), dest->as_xmm_double_reg());
651 } else {
652 __ movdbl(dest->as_xmm_double_reg(),
653 InternalAddress(double_constant(c->as_jdouble())));
654 }
655 } else {
656 #ifndef _LP64
657 assert(dest->is_double_fpu(), "must be");
658 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
659 if (c->is_zero_double()) {
660 __ fldz();
661 } else if (c->is_one_double()) {
662 __ fld1();
663 } else {
664 __ fld_d (InternalAddress(double_constant(c->as_jdouble())));
665 }
666 #else
667 ShouldNotReachHere();
668 #endif // !_LP64
669 }
670 break;
671 }
672
673 default:
674 ShouldNotReachHere();
675 }
676 }
677
678 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
679 assert(src->is_constant(), "should not call otherwise");
680 assert(dest->is_stack(), "should not call otherwise");
681 LIR_Const* c = src->as_constant_ptr();
682
683 switch (c->type()) {
684 case T_INT: // fall through
685 case T_FLOAT:
686 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits());
687 break;
688
689 case T_ADDRESS:
690 __ movptr(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits());
691 break;
692
693 case T_OBJECT:
694 __ movoop(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jobject(), rscratch1);
695 break;
696
697 case T_LONG: // fall through
698 case T_DOUBLE:
699 #ifdef _LP64
700 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
701 lo_word_offset_in_bytes),
702 (intptr_t)c->as_jlong_bits(),
703 rscratch1);
704 #else
705 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
706 lo_word_offset_in_bytes), c->as_jint_lo_bits());
707 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
708 hi_word_offset_in_bytes), c->as_jint_hi_bits());
709 #endif // _LP64
710 break;
711
712 default:
713 ShouldNotReachHere();
714 }
715 }
716
717 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
718 assert(src->is_constant(), "should not call otherwise");
719 assert(dest->is_address(), "should not call otherwise");
720 LIR_Const* c = src->as_constant_ptr();
721 LIR_Address* addr = dest->as_address_ptr();
722
723 int null_check_here = code_offset();
724 switch (type) {
725 case T_INT: // fall through
726 case T_FLOAT:
727 __ movl(as_Address(addr), c->as_jint_bits());
728 break;
729
730 case T_ADDRESS:
731 __ movptr(as_Address(addr), c->as_jint_bits());
732 break;
733
734 case T_OBJECT: // fall through
735 case T_ARRAY:
736 if (c->as_jobject() == NULL) {
737 if (UseCompressedOops && !wide) {
738 __ movl(as_Address(addr), NULL_WORD);
739 } else {
740 #ifdef _LP64
741 __ xorptr(rscratch1, rscratch1);
742 null_check_here = code_offset();
743 __ movptr(as_Address(addr), rscratch1);
744 #else
745 __ movptr(as_Address(addr), NULL_WORD);
746 #endif
747 }
748 } else {
749 if (is_literal_address(addr)) {
750 ShouldNotReachHere();
751 __ movoop(as_Address(addr, noreg), c->as_jobject(), rscratch1);
752 } else {
753 #ifdef _LP64
754 __ movoop(rscratch1, c->as_jobject());
755 if (UseCompressedOops && !wide) {
756 __ encode_heap_oop(rscratch1);
757 null_check_here = code_offset();
758 __ movl(as_Address_lo(addr), rscratch1);
759 } else {
760 null_check_here = code_offset();
761 __ movptr(as_Address_lo(addr), rscratch1);
762 }
763 #else
764 __ movoop(as_Address(addr), c->as_jobject(), noreg);
765 #endif
766 }
767 }
768 break;
769
770 case T_LONG: // fall through
771 case T_DOUBLE:
772 #ifdef _LP64
773 if (is_literal_address(addr)) {
774 ShouldNotReachHere();
775 __ movptr(as_Address(addr, r15_thread), (intptr_t)c->as_jlong_bits());
776 } else {
777 __ movptr(r10, (intptr_t)c->as_jlong_bits());
778 null_check_here = code_offset();
779 __ movptr(as_Address_lo(addr), r10);
780 }
781 #else
782 // Always reachable in 32bit so this doesn't produce useless move literal
783 __ movptr(as_Address_hi(addr), c->as_jint_hi_bits());
784 __ movptr(as_Address_lo(addr), c->as_jint_lo_bits());
785 #endif // _LP64
786 break;
787
788 case T_BOOLEAN: // fall through
789 case T_BYTE:
790 __ movb(as_Address(addr), c->as_jint() & 0xFF);
791 break;
792
793 case T_CHAR: // fall through
794 case T_SHORT:
795 __ movw(as_Address(addr), c->as_jint() & 0xFFFF);
796 break;
797
798 default:
799 ShouldNotReachHere();
800 };
801
802 if (info != NULL) {
803 add_debug_info_for_null_check(null_check_here, info);
804 }
805 }
806
807
808 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
809 assert(src->is_register(), "should not call otherwise");
810 assert(dest->is_register(), "should not call otherwise");
811
812 // move between cpu-registers
813 if (dest->is_single_cpu()) {
814 #ifdef _LP64
815 if (src->type() == T_LONG) {
816 // Can do LONG -> OBJECT
817 move_regs(src->as_register_lo(), dest->as_register());
818 return;
819 }
820 #endif
821 assert(src->is_single_cpu(), "must match");
822 if (src->type() == T_OBJECT) {
823 __ verify_oop(src->as_register());
824 }
825 move_regs(src->as_register(), dest->as_register());
826
827 } else if (dest->is_double_cpu()) {
828 #ifdef _LP64
829 if (is_reference_type(src->type())) {
830 // Surprising to me but we can see move of a long to t_object
831 __ verify_oop(src->as_register());
832 move_regs(src->as_register(), dest->as_register_lo());
833 return;
834 }
835 #endif
836 assert(src->is_double_cpu(), "must match");
837 Register f_lo = src->as_register_lo();
838 Register f_hi = src->as_register_hi();
839 Register t_lo = dest->as_register_lo();
840 Register t_hi = dest->as_register_hi();
841 #ifdef _LP64
842 assert(f_hi == f_lo, "must be same");
843 assert(t_hi == t_lo, "must be same");
844 move_regs(f_lo, t_lo);
845 #else
846 assert(f_lo != f_hi && t_lo != t_hi, "invalid register allocation");
847
848
849 if (f_lo == t_hi && f_hi == t_lo) {
850 swap_reg(f_lo, f_hi);
851 } else if (f_hi == t_lo) {
852 assert(f_lo != t_hi, "overwriting register");
853 move_regs(f_hi, t_hi);
854 move_regs(f_lo, t_lo);
855 } else {
856 assert(f_hi != t_lo, "overwriting register");
857 move_regs(f_lo, t_lo);
858 move_regs(f_hi, t_hi);
859 }
860 #endif // LP64
861
862 #ifndef _LP64
863 // special moves from fpu-register to xmm-register
864 // necessary for method results
865 } else if (src->is_single_xmm() && !dest->is_single_xmm()) {
866 __ movflt(Address(rsp, 0), src->as_xmm_float_reg());
867 __ fld_s(Address(rsp, 0));
868 } else if (src->is_double_xmm() && !dest->is_double_xmm()) {
869 __ movdbl(Address(rsp, 0), src->as_xmm_double_reg());
870 __ fld_d(Address(rsp, 0));
871 } else if (dest->is_single_xmm() && !src->is_single_xmm()) {
872 __ fstp_s(Address(rsp, 0));
873 __ movflt(dest->as_xmm_float_reg(), Address(rsp, 0));
874 } else if (dest->is_double_xmm() && !src->is_double_xmm()) {
875 __ fstp_d(Address(rsp, 0));
876 __ movdbl(dest->as_xmm_double_reg(), Address(rsp, 0));
877 #endif // !_LP64
878
879 // move between xmm-registers
880 } else if (dest->is_single_xmm()) {
881 assert(src->is_single_xmm(), "must match");
882 __ movflt(dest->as_xmm_float_reg(), src->as_xmm_float_reg());
883 } else if (dest->is_double_xmm()) {
884 assert(src->is_double_xmm(), "must match");
885 __ movdbl(dest->as_xmm_double_reg(), src->as_xmm_double_reg());
886
887 #ifndef _LP64
888 // move between fpu-registers (no instruction necessary because of fpu-stack)
889 } else if (dest->is_single_fpu() || dest->is_double_fpu()) {
890 assert(src->is_single_fpu() || src->is_double_fpu(), "must match");
891 assert(src->fpu() == dest->fpu(), "currently should be nothing to do");
892 #endif // !_LP64
893
894 } else {
895 ShouldNotReachHere();
896 }
897 }
898
899 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
900 assert(src->is_register(), "should not call otherwise");
901 assert(dest->is_stack(), "should not call otherwise");
902
903 if (src->is_single_cpu()) {
904 Address dst = frame_map()->address_for_slot(dest->single_stack_ix());
905 if (is_reference_type(type)) {
906 __ verify_oop(src->as_register());
907 __ movptr (dst, src->as_register());
908 } else if (type == T_METADATA || type == T_ADDRESS) {
909 __ movptr (dst, src->as_register());
910 } else {
911 __ movl (dst, src->as_register());
912 }
913
914 } else if (src->is_double_cpu()) {
915 Address dstLO = frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes);
916 Address dstHI = frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes);
917 __ movptr (dstLO, src->as_register_lo());
918 NOT_LP64(__ movptr (dstHI, src->as_register_hi()));
919
920 } else if (src->is_single_xmm()) {
921 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
922 __ movflt(dst_addr, src->as_xmm_float_reg());
923
924 } else if (src->is_double_xmm()) {
925 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
926 __ movdbl(dst_addr, src->as_xmm_double_reg());
927
928 #ifndef _LP64
929 } else if (src->is_single_fpu()) {
930 assert(src->fpu_regnr() == 0, "argument must be on TOS");
931 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
932 if (pop_fpu_stack) __ fstp_s (dst_addr);
933 else __ fst_s (dst_addr);
934
935 } else if (src->is_double_fpu()) {
936 assert(src->fpu_regnrLo() == 0, "argument must be on TOS");
937 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
938 if (pop_fpu_stack) __ fstp_d (dst_addr);
939 else __ fst_d (dst_addr);
940 #endif // !_LP64
941
942 } else {
943 ShouldNotReachHere();
944 }
945 }
946
947
948 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool wide) {
949 LIR_Address* to_addr = dest->as_address_ptr();
950 PatchingStub* patch = NULL;
951 Register compressed_src = rscratch1;
952
953 if (is_reference_type(type)) {
954 __ verify_oop(src->as_register());
955 #ifdef _LP64
956 if (UseCompressedOops && !wide) {
957 __ movptr(compressed_src, src->as_register());
958 __ encode_heap_oop(compressed_src);
959 if (patch_code != lir_patch_none) {
960 info->oop_map()->set_narrowoop(compressed_src->as_VMReg());
961 }
962 }
963 #endif
964 }
965
966 if (patch_code != lir_patch_none) {
967 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
968 Address toa = as_Address(to_addr);
969 assert(toa.disp() != 0, "must have");
970 }
971
972 int null_check_here = code_offset();
973 switch (type) {
974 case T_FLOAT: {
975 #ifdef _LP64
976 assert(src->is_single_xmm(), "not a float");
977 __ movflt(as_Address(to_addr), src->as_xmm_float_reg());
978 #else
979 if (src->is_single_xmm()) {
980 __ movflt(as_Address(to_addr), src->as_xmm_float_reg());
981 } else {
982 assert(src->is_single_fpu(), "must be");
983 assert(src->fpu_regnr() == 0, "argument must be on TOS");
984 if (pop_fpu_stack) __ fstp_s(as_Address(to_addr));
985 else __ fst_s (as_Address(to_addr));
986 }
987 #endif // _LP64
988 break;
989 }
990
991 case T_DOUBLE: {
992 #ifdef _LP64
993 assert(src->is_double_xmm(), "not a double");
994 __ movdbl(as_Address(to_addr), src->as_xmm_double_reg());
995 #else
996 if (src->is_double_xmm()) {
997 __ movdbl(as_Address(to_addr), src->as_xmm_double_reg());
998 } else {
999 assert(src->is_double_fpu(), "must be");
1000 assert(src->fpu_regnrLo() == 0, "argument must be on TOS");
1001 if (pop_fpu_stack) __ fstp_d(as_Address(to_addr));
1002 else __ fst_d (as_Address(to_addr));
1003 }
1004 #endif // _LP64
1005 break;
1006 }
1007
1008 case T_ARRAY: // fall through
1009 case T_OBJECT: // fall through
1010 if (UseCompressedOops && !wide) {
1011 __ movl(as_Address(to_addr), compressed_src);
1012 } else {
1013 __ movptr(as_Address(to_addr), src->as_register());
1014 }
1015 break;
1016 case T_METADATA:
1017 // We get here to store a method pointer to the stack to pass to
1018 // a dtrace runtime call. This can't work on 64 bit with
1019 // compressed klass ptrs: T_METADATA can be a compressed klass
1020 // ptr or a 64 bit method pointer.
1021 LP64_ONLY(ShouldNotReachHere());
1022 __ movptr(as_Address(to_addr), src->as_register());
1023 break;
1024 case T_ADDRESS:
1025 __ movptr(as_Address(to_addr), src->as_register());
1026 break;
1027 case T_INT:
1028 __ movl(as_Address(to_addr), src->as_register());
1029 break;
1030
1031 case T_LONG: {
1032 Register from_lo = src->as_register_lo();
1033 Register from_hi = src->as_register_hi();
1034 #ifdef _LP64
1035 __ movptr(as_Address_lo(to_addr), from_lo);
1036 #else
1037 Register base = to_addr->base()->as_register();
1038 Register index = noreg;
1039 if (to_addr->index()->is_register()) {
1040 index = to_addr->index()->as_register();
1041 }
1042 if (base == from_lo || index == from_lo) {
1043 assert(base != from_hi, "can't be");
1044 assert(index == noreg || (index != base && index != from_hi), "can't handle this");
1045 __ movl(as_Address_hi(to_addr), from_hi);
1046 if (patch != NULL) {
1047 patching_epilog(patch, lir_patch_high, base, info);
1048 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1049 patch_code = lir_patch_low;
1050 }
1051 __ movl(as_Address_lo(to_addr), from_lo);
1052 } else {
1053 assert(index == noreg || (index != base && index != from_lo), "can't handle this");
1054 __ movl(as_Address_lo(to_addr), from_lo);
1055 if (patch != NULL) {
1056 patching_epilog(patch, lir_patch_low, base, info);
1057 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1058 patch_code = lir_patch_high;
1059 }
1060 __ movl(as_Address_hi(to_addr), from_hi);
1061 }
1062 #endif // _LP64
1063 break;
1064 }
1065
1066 case T_BYTE: // fall through
1067 case T_BOOLEAN: {
1068 Register src_reg = src->as_register();
1069 Address dst_addr = as_Address(to_addr);
1070 assert(VM_Version::is_P6() || src_reg->has_byte_register(), "must use byte registers if not P6");
1071 __ movb(dst_addr, src_reg);
1072 break;
1073 }
1074
1075 case T_CHAR: // fall through
1076 case T_SHORT:
1077 __ movw(as_Address(to_addr), src->as_register());
1078 break;
1079
1080 default:
1081 ShouldNotReachHere();
1082 }
1083 if (info != NULL) {
1084 add_debug_info_for_null_check(null_check_here, info);
1085 }
1086
1087 if (patch_code != lir_patch_none) {
1088 patching_epilog(patch, patch_code, to_addr->base()->as_register(), info);
1089 }
1090 }
1091
1092
1093 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
1094 assert(src->is_stack(), "should not call otherwise");
1095 assert(dest->is_register(), "should not call otherwise");
1096
1097 if (dest->is_single_cpu()) {
1098 if (is_reference_type(type)) {
1099 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1100 __ verify_oop(dest->as_register());
1101 } else if (type == T_METADATA || type == T_ADDRESS) {
1102 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1103 } else {
1104 __ movl(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1105 }
1106
1107 } else if (dest->is_double_cpu()) {
1108 Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix(), lo_word_offset_in_bytes);
1109 Address src_addr_HI = frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes);
1110 __ movptr(dest->as_register_lo(), src_addr_LO);
1111 NOT_LP64(__ movptr(dest->as_register_hi(), src_addr_HI));
1112
1113 } else if (dest->is_single_xmm()) {
1114 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
1115 __ movflt(dest->as_xmm_float_reg(), src_addr);
1116
1117 } else if (dest->is_double_xmm()) {
1118 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
1119 __ movdbl(dest->as_xmm_double_reg(), src_addr);
1120
1121 #ifndef _LP64
1122 } else if (dest->is_single_fpu()) {
1123 assert(dest->fpu_regnr() == 0, "dest must be TOS");
1124 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
1125 __ fld_s(src_addr);
1126
1127 } else if (dest->is_double_fpu()) {
1128 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
1129 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
1130 __ fld_d(src_addr);
1131 #endif // _LP64
1132
1133 } else {
1134 ShouldNotReachHere();
1135 }
1136 }
1137
1138
1139 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
1140 if (src->is_single_stack()) {
1141 if (is_reference_type(type)) {
1142 __ pushptr(frame_map()->address_for_slot(src ->single_stack_ix()));
1143 __ popptr (frame_map()->address_for_slot(dest->single_stack_ix()));
1144 } else {
1145 #ifndef _LP64
1146 __ pushl(frame_map()->address_for_slot(src ->single_stack_ix()));
1147 __ popl (frame_map()->address_for_slot(dest->single_stack_ix()));
1148 #else
1149 //no pushl on 64bits
1150 __ movl(rscratch1, frame_map()->address_for_slot(src ->single_stack_ix()));
1151 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), rscratch1);
1152 #endif
1153 }
1154
1155 } else if (src->is_double_stack()) {
1156 #ifdef _LP64
1157 __ pushptr(frame_map()->address_for_slot(src ->double_stack_ix()));
1158 __ popptr (frame_map()->address_for_slot(dest->double_stack_ix()));
1159 #else
1160 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 0));
1161 // push and pop the part at src + wordSize, adding wordSize for the previous push
1162 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 2 * wordSize));
1163 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 2 * wordSize));
1164 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 0));
1165 #endif // _LP64
1166
1167 } else {
1168 ShouldNotReachHere();
1169 }
1170 }
1171
1172
1173 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide) {
1174 assert(src->is_address(), "should not call otherwise");
1175 assert(dest->is_register(), "should not call otherwise");
1176
1177 LIR_Address* addr = src->as_address_ptr();
1178 Address from_addr = as_Address(addr);
1179
1180 if (addr->base()->type() == T_OBJECT) {
1181 __ verify_oop(addr->base()->as_pointer_register());
1182 }
1183
1184 switch (type) {
1185 case T_BOOLEAN: // fall through
1186 case T_BYTE: // fall through
1187 case T_CHAR: // fall through
1188 case T_SHORT:
1189 if (!VM_Version::is_P6() && !from_addr.uses(dest->as_register())) {
1190 // on pre P6 processors we may get partial register stalls
1191 // so blow away the value of to_rinfo before loading a
1192 // partial word into it. Do it here so that it precedes
1193 // the potential patch point below.
1194 __ xorptr(dest->as_register(), dest->as_register());
1195 }
1196 break;
1197 default:
1198 break;
1199 }
1200
1201 PatchingStub* patch = NULL;
1202 if (patch_code != lir_patch_none) {
1203 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1204 assert(from_addr.disp() != 0, "must have");
1205 }
1206 if (info != NULL) {
1207 add_debug_info_for_null_check_here(info);
1208 }
1209
1210 switch (type) {
1211 case T_FLOAT: {
1212 if (dest->is_single_xmm()) {
1213 __ movflt(dest->as_xmm_float_reg(), from_addr);
1214 } else {
1215 #ifndef _LP64
1216 assert(dest->is_single_fpu(), "must be");
1217 assert(dest->fpu_regnr() == 0, "dest must be TOS");
1218 __ fld_s(from_addr);
1219 #else
1220 ShouldNotReachHere();
1221 #endif // !LP64
1222 }
1223 break;
1224 }
1225
1226 case T_DOUBLE: {
1227 if (dest->is_double_xmm()) {
1228 __ movdbl(dest->as_xmm_double_reg(), from_addr);
1229 } else {
1230 #ifndef _LP64
1231 assert(dest->is_double_fpu(), "must be");
1232 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
1233 __ fld_d(from_addr);
1234 #else
1235 ShouldNotReachHere();
1236 #endif // !LP64
1237 }
1238 break;
1239 }
1240
1241 case T_OBJECT: // fall through
1242 case T_ARRAY: // fall through
1243 if (UseCompressedOops && !wide) {
1244 __ movl(dest->as_register(), from_addr);
1245 } else {
1246 __ movptr(dest->as_register(), from_addr);
1247 }
1248 break;
1249
1250 case T_ADDRESS:
1251 __ movptr(dest->as_register(), from_addr);
1252 break;
1253 case T_INT:
1254 __ movl(dest->as_register(), from_addr);
1255 break;
1256
1257 case T_LONG: {
1258 Register to_lo = dest->as_register_lo();
1259 Register to_hi = dest->as_register_hi();
1260 #ifdef _LP64
1261 __ movptr(to_lo, as_Address_lo(addr));
1262 #else
1263 Register base = addr->base()->as_register();
1264 Register index = noreg;
1265 if (addr->index()->is_register()) {
1266 index = addr->index()->as_register();
1267 }
1268 if ((base == to_lo && index == to_hi) ||
1269 (base == to_hi && index == to_lo)) {
1270 // addresses with 2 registers are only formed as a result of
1271 // array access so this code will never have to deal with
1272 // patches or null checks.
1273 assert(info == NULL && patch == NULL, "must be");
1274 __ lea(to_hi, as_Address(addr));
1275 __ movl(to_lo, Address(to_hi, 0));
1276 __ movl(to_hi, Address(to_hi, BytesPerWord));
1277 } else if (base == to_lo || index == to_lo) {
1278 assert(base != to_hi, "can't be");
1279 assert(index == noreg || (index != base && index != to_hi), "can't handle this");
1280 __ movl(to_hi, as_Address_hi(addr));
1281 if (patch != NULL) {
1282 patching_epilog(patch, lir_patch_high, base, info);
1283 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1284 patch_code = lir_patch_low;
1285 }
1286 __ movl(to_lo, as_Address_lo(addr));
1287 } else {
1288 assert(index == noreg || (index != base && index != to_lo), "can't handle this");
1289 __ movl(to_lo, as_Address_lo(addr));
1290 if (patch != NULL) {
1291 patching_epilog(patch, lir_patch_low, base, info);
1292 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1293 patch_code = lir_patch_high;
1294 }
1295 __ movl(to_hi, as_Address_hi(addr));
1296 }
1297 #endif // _LP64
1298 break;
1299 }
1300
1301 case T_BOOLEAN: // fall through
1302 case T_BYTE: {
1303 Register dest_reg = dest->as_register();
1304 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
1305 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1306 __ movsbl(dest_reg, from_addr);
1307 } else {
1308 __ movb(dest_reg, from_addr);
1309 __ shll(dest_reg, 24);
1310 __ sarl(dest_reg, 24);
1311 }
1312 break;
1313 }
1314
1315 case T_CHAR: {
1316 Register dest_reg = dest->as_register();
1317 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
1318 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1319 __ movzwl(dest_reg, from_addr);
1320 } else {
1321 __ movw(dest_reg, from_addr);
1322 }
1323 break;
1324 }
1325
1326 case T_SHORT: {
1327 Register dest_reg = dest->as_register();
1328 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1329 __ movswl(dest_reg, from_addr);
1330 } else {
1331 __ movw(dest_reg, from_addr);
1332 __ shll(dest_reg, 16);
1333 __ sarl(dest_reg, 16);
1334 }
1335 break;
1336 }
1337
1338 default:
1339 ShouldNotReachHere();
1340 }
1341
1342 if (patch != NULL) {
1343 patching_epilog(patch, patch_code, addr->base()->as_register(), info);
1344 }
1345
1346 if (is_reference_type(type)) {
1347 #ifdef _LP64
1348 if (UseCompressedOops && !wide) {
1349 __ decode_heap_oop(dest->as_register());
1350 }
1351 #endif
1352
1353 // Load barrier has not yet been applied, so ZGC can't verify the oop here
1354 if (!UseZGC) {
1355 __ verify_oop(dest->as_register());
1356 }
1357 }
1358 }
1359
1360
1361 NEEDS_CLEANUP; // This could be static?
1362 Address::ScaleFactor LIR_Assembler::array_element_size(BasicType type) const {
1363 int elem_size = type2aelembytes(type);
1364 switch (elem_size) {
1365 case 1: return Address::times_1;
1366 case 2: return Address::times_2;
1367 case 4: return Address::times_4;
1368 case 8: return Address::times_8;
1369 }
1370 ShouldNotReachHere();
1371 return Address::no_scale;
1372 }
1373
1374
1375 void LIR_Assembler::emit_op3(LIR_Op3* op) {
1376 switch (op->code()) {
1377 case lir_idiv:
1378 case lir_irem:
1379 arithmetic_idiv(op->code(),
1380 op->in_opr1(),
1381 op->in_opr2(),
1382 op->in_opr3(),
1383 op->result_opr(),
1384 op->info());
1385 break;
1386 case lir_fmad:
1387 __ fmad(op->result_opr()->as_xmm_double_reg(),
1388 op->in_opr1()->as_xmm_double_reg(),
1389 op->in_opr2()->as_xmm_double_reg(),
1390 op->in_opr3()->as_xmm_double_reg());
1391 break;
1392 case lir_fmaf:
1393 __ fmaf(op->result_opr()->as_xmm_float_reg(),
1394 op->in_opr1()->as_xmm_float_reg(),
1395 op->in_opr2()->as_xmm_float_reg(),
1396 op->in_opr3()->as_xmm_float_reg());
1397 break;
1398 default: ShouldNotReachHere(); break;
1399 }
1400 }
1401
1402 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
1403 #ifdef ASSERT
1404 assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label");
1405 if (op->block() != NULL) _branch_target_blocks.append(op->block());
1406 if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock());
1407 #endif
1408
1409 if (op->cond() == lir_cond_always) {
1410 if (op->info() != NULL) add_debug_info_for_branch(op->info());
1411 __ jmp (*(op->label()));
1412 } else {
1413 Assembler::Condition acond = Assembler::zero;
1414 if (op->code() == lir_cond_float_branch) {
1415 assert(op->ublock() != NULL, "must have unordered successor");
1416 __ jcc(Assembler::parity, *(op->ublock()->label()));
1417 switch(op->cond()) {
1418 case lir_cond_equal: acond = Assembler::equal; break;
1419 case lir_cond_notEqual: acond = Assembler::notEqual; break;
1420 case lir_cond_less: acond = Assembler::below; break;
1421 case lir_cond_lessEqual: acond = Assembler::belowEqual; break;
1422 case lir_cond_greaterEqual: acond = Assembler::aboveEqual; break;
1423 case lir_cond_greater: acond = Assembler::above; break;
1424 default: ShouldNotReachHere();
1425 }
1426 } else {
1427 switch (op->cond()) {
1428 case lir_cond_equal: acond = Assembler::equal; break;
1429 case lir_cond_notEqual: acond = Assembler::notEqual; break;
1430 case lir_cond_less: acond = Assembler::less; break;
1431 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
1432 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break;
1433 case lir_cond_greater: acond = Assembler::greater; break;
1434 case lir_cond_belowEqual: acond = Assembler::belowEqual; break;
1435 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break;
1436 default: ShouldNotReachHere();
1437 }
1438 }
1439 __ jcc(acond,*(op->label()));
1440 }
1441 }
1442
1443 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
1444 LIR_Opr src = op->in_opr();
1445 LIR_Opr dest = op->result_opr();
1446
1447 switch (op->bytecode()) {
1448 case Bytecodes::_i2l:
1449 #ifdef _LP64
1450 __ movl2ptr(dest->as_register_lo(), src->as_register());
1451 #else
1452 move_regs(src->as_register(), dest->as_register_lo());
1453 move_regs(src->as_register(), dest->as_register_hi());
1454 __ sarl(dest->as_register_hi(), 31);
1455 #endif // LP64
1456 break;
1457
1458 case Bytecodes::_l2i:
1459 #ifdef _LP64
1460 __ movl(dest->as_register(), src->as_register_lo());
1461 #else
1462 move_regs(src->as_register_lo(), dest->as_register());
1463 #endif
1464 break;
1465
1466 case Bytecodes::_i2b:
1467 move_regs(src->as_register(), dest->as_register());
1468 __ sign_extend_byte(dest->as_register());
1469 break;
1470
1471 case Bytecodes::_i2c:
1472 move_regs(src->as_register(), dest->as_register());
1473 __ andl(dest->as_register(), 0xFFFF);
1474 break;
1475
1476 case Bytecodes::_i2s:
1477 move_regs(src->as_register(), dest->as_register());
1478 __ sign_extend_short(dest->as_register());
1479 break;
1480
1481
1482 #ifdef _LP64
1483 case Bytecodes::_f2d:
1484 __ cvtss2sd(dest->as_xmm_double_reg(), src->as_xmm_float_reg());
1485 break;
1486
1487 case Bytecodes::_d2f:
1488 __ cvtsd2ss(dest->as_xmm_float_reg(), src->as_xmm_double_reg());
1489 break;
1490
1491 case Bytecodes::_i2f:
1492 __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register());
1493 break;
1494
1495 case Bytecodes::_i2d:
1496 __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register());
1497 break;
1498
1499 case Bytecodes::_l2f:
1500 __ cvtsi2ssq(dest->as_xmm_float_reg(), src->as_register_lo());
1501 break;
1502
1503 case Bytecodes::_l2d:
1504 __ cvtsi2sdq(dest->as_xmm_double_reg(), src->as_register_lo());
1505 break;
1506
1507 case Bytecodes::_f2i:
1508 __ convert_f2i(dest->as_register(), src->as_xmm_float_reg());
1509 break;
1510
1511 case Bytecodes::_d2i:
1512 __ convert_d2i(dest->as_register(), src->as_xmm_double_reg());
1513 break;
1514
1515 case Bytecodes::_f2l:
1516 __ convert_f2l(dest->as_register_lo(), src->as_xmm_float_reg());
1517 break;
1518
1519 case Bytecodes::_d2l:
1520 __ convert_d2l(dest->as_register_lo(), src->as_xmm_double_reg());
1521 break;
1522 #else
1523 case Bytecodes::_f2d:
1524 case Bytecodes::_d2f:
1525 if (dest->is_single_xmm()) {
1526 __ cvtsd2ss(dest->as_xmm_float_reg(), src->as_xmm_double_reg());
1527 } else if (dest->is_double_xmm()) {
1528 __ cvtss2sd(dest->as_xmm_double_reg(), src->as_xmm_float_reg());
1529 } else {
1530 assert(src->fpu() == dest->fpu(), "register must be equal");
1531 // do nothing (float result is rounded later through spilling)
1532 }
1533 break;
1534
1535 case Bytecodes::_i2f:
1536 case Bytecodes::_i2d:
1537 if (dest->is_single_xmm()) {
1538 __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register());
1539 } else if (dest->is_double_xmm()) {
1540 __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register());
1541 } else {
1542 assert(dest->fpu() == 0, "result must be on TOS");
1543 __ movl(Address(rsp, 0), src->as_register());
1544 __ fild_s(Address(rsp, 0));
1545 }
1546 break;
1547
1548 case Bytecodes::_l2f:
1549 case Bytecodes::_l2d:
1550 assert(!dest->is_xmm_register(), "result in xmm register not supported (no SSE instruction present)");
1551 assert(dest->fpu() == 0, "result must be on TOS");
1552 __ movptr(Address(rsp, 0), src->as_register_lo());
1553 __ movl(Address(rsp, BytesPerWord), src->as_register_hi());
1554 __ fild_d(Address(rsp, 0));
1555 // float result is rounded later through spilling
1556 break;
1557
1558 case Bytecodes::_f2i:
1559 case Bytecodes::_d2i:
1560 if (src->is_single_xmm()) {
1561 __ cvttss2sil(dest->as_register(), src->as_xmm_float_reg());
1562 } else if (src->is_double_xmm()) {
1563 __ cvttsd2sil(dest->as_register(), src->as_xmm_double_reg());
1564 } else {
1565 assert(src->fpu() == 0, "input must be on TOS");
1566 __ fldcw(ExternalAddress(StubRoutines::x86::addr_fpu_cntrl_wrd_trunc()));
1567 __ fist_s(Address(rsp, 0));
1568 __ movl(dest->as_register(), Address(rsp, 0));
1569 __ fldcw(ExternalAddress(StubRoutines::x86::addr_fpu_cntrl_wrd_std()));
1570 }
1571 // IA32 conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
1572 assert(op->stub() != NULL, "stub required");
1573 __ cmpl(dest->as_register(), 0x80000000);
1574 __ jcc(Assembler::equal, *op->stub()->entry());
1575 __ bind(*op->stub()->continuation());
1576 break;
1577
1578 case Bytecodes::_f2l:
1579 case Bytecodes::_d2l:
1580 assert(!src->is_xmm_register(), "input in xmm register not supported (no SSE instruction present)");
1581 assert(src->fpu() == 0, "input must be on TOS");
1582 assert(dest == FrameMap::long0_opr, "runtime stub places result in these registers");
1583
1584 // instruction sequence too long to inline it here
1585 {
1586 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::fpu2long_stub_id)));
1587 }
1588 break;
1589 #endif // _LP64
1590
1591 default: ShouldNotReachHere();
1592 }
1593 }
1594
1595 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
1596 if (op->init_check()) {
1597 add_debug_info_for_null_check_here(op->stub()->info());
1598 __ cmpb(Address(op->klass()->as_register(),
1599 InstanceKlass::init_state_offset()),
1600 InstanceKlass::fully_initialized);
1601 __ jcc(Assembler::notEqual, *op->stub()->entry());
1602 }
1603 __ allocate_object(op->obj()->as_register(),
1604 op->tmp1()->as_register(),
1605 op->tmp2()->as_register(),
1606 op->header_size(),
1607 op->object_size(),
1608 op->klass()->as_register(),
1609 *op->stub()->entry());
1610 __ bind(*op->stub()->continuation());
1611 }
1612
1613 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
1614 Register len = op->len()->as_register();
1615 LP64_ONLY( __ movslq(len, len); )
1616
1617 if (UseSlowPath ||
1618 (!UseFastNewObjectArray && is_reference_type(op->type())) ||
1619 (!UseFastNewTypeArray && !is_reference_type(op->type()))) {
1620 __ jmp(*op->stub()->entry());
1621 } else {
1622 Register tmp1 = op->tmp1()->as_register();
1623 Register tmp2 = op->tmp2()->as_register();
1624 Register tmp3 = op->tmp3()->as_register();
1625 if (len == tmp1) {
1626 tmp1 = tmp3;
1627 } else if (len == tmp2) {
1628 tmp2 = tmp3;
1629 } else if (len == tmp3) {
1630 // everything is ok
1631 } else {
1632 __ mov(tmp3, len);
1633 }
1634 __ allocate_array(op->obj()->as_register(),
1635 len,
1636 tmp1,
1637 tmp2,
1638 arrayOopDesc::header_size(op->type()),
1639 array_element_size(op->type()),
1640 op->klass()->as_register(),
1641 *op->stub()->entry());
1642 }
1643 __ bind(*op->stub()->continuation());
1644 }
1645
1646 void LIR_Assembler::type_profile_helper(Register mdo,
1647 ciMethodData *md, ciProfileData *data,
1648 Register recv, Label* update_done) {
1649 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1650 Label next_test;
1651 // See if the receiver is receiver[n].
1652 __ cmpptr(recv, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))));
1653 __ jccb(Assembler::notEqual, next_test);
1654 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)));
1655 __ addptr(data_addr, DataLayout::counter_increment);
1656 __ jmp(*update_done);
1657 __ bind(next_test);
1658 }
1659
1660 // Didn't find receiver; find next empty slot and fill it in
1661 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1662 Label next_test;
1663 Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)));
1664 __ cmpptr(recv_addr, NULL_WORD);
1665 __ jccb(Assembler::notEqual, next_test);
1666 __ movptr(recv_addr, recv);
1667 __ movptr(Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))), DataLayout::counter_increment);
1668 __ jmp(*update_done);
1669 __ bind(next_test);
1670 }
1671 }
1672
1673 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
1674 // we always need a stub for the failure case.
1675 CodeStub* stub = op->stub();
1676 Register obj = op->object()->as_register();
1677 Register k_RInfo = op->tmp1()->as_register();
1678 Register klass_RInfo = op->tmp2()->as_register();
1679 Register dst = op->result_opr()->as_register();
1680 ciKlass* k = op->klass();
1681 Register Rtmp1 = noreg;
1682 Register tmp_load_klass = LP64_ONLY(rscratch1) NOT_LP64(noreg);
1683
1684 // check if it needs to be profiled
1685 ciMethodData* md = NULL;
1686 ciProfileData* data = NULL;
1687
1688 if (op->should_profile()) {
1689 ciMethod* method = op->profiled_method();
1690 assert(method != NULL, "Should have method");
1691 int bci = op->profiled_bci();
1692 md = method->method_data_or_null();
1693 assert(md != NULL, "Sanity");
1694 data = md->bci_to_data(bci);
1695 assert(data != NULL, "need data for type check");
1696 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1697 }
1698 Label profile_cast_success, profile_cast_failure;
1699 Label *success_target = op->should_profile() ? &profile_cast_success : success;
1700 Label *failure_target = op->should_profile() ? &profile_cast_failure : failure;
1701
1702 if (obj == k_RInfo) {
1703 k_RInfo = dst;
1704 } else if (obj == klass_RInfo) {
1705 klass_RInfo = dst;
1706 }
1707 if (k->is_loaded() && !UseCompressedClassPointers) {
1708 select_different_registers(obj, dst, k_RInfo, klass_RInfo);
1709 } else {
1710 Rtmp1 = op->tmp3()->as_register();
1711 select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1);
1712 }
1713
1714 assert_different_registers(obj, k_RInfo, klass_RInfo);
1715
1716 __ cmpptr(obj, NULL_WORD);
1717 if (op->should_profile()) {
1718 Label not_null;
1719 __ jccb(Assembler::notEqual, not_null);
1720 // Object is null; update MDO and exit
1721 Register mdo = klass_RInfo;
1722 __ mov_metadata(mdo, md->constant_encoding());
1723 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()));
1724 int header_bits = BitData::null_seen_byte_constant();
1725 __ orb(data_addr, header_bits);
1726 __ jmp(*obj_is_null);
1727 __ bind(not_null);
1728 } else {
1729 __ jcc(Assembler::equal, *obj_is_null);
1730 }
1731
1732 if (!k->is_loaded()) {
1733 klass2reg_with_patching(k_RInfo, op->info_for_patch());
1734 } else {
1735 #ifdef _LP64
1736 __ mov_metadata(k_RInfo, k->constant_encoding());
1737 #endif // _LP64
1738 }
1739 __ verify_oop(obj);
1740
1741 if (op->fast_check()) {
1742 // get object class
1743 // not a safepoint as obj null check happens earlier
1744 #ifdef _LP64
1745 if (UseCompressedClassPointers) {
1746 __ load_klass(Rtmp1, obj, tmp_load_klass);
1747 __ cmpptr(k_RInfo, Rtmp1);
1748 } else {
1749 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1750 }
1751 #else
1752 if (k->is_loaded()) {
1753 __ cmpklass(Address(obj, oopDesc::klass_offset_in_bytes()), k->constant_encoding());
1754 } else {
1755 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1756 }
1757 #endif
1758 __ jcc(Assembler::notEqual, *failure_target);
1759 // successful cast, fall through to profile or jump
1760 } else {
1761 // get object class
1762 // not a safepoint as obj null check happens earlier
1763 __ load_klass(klass_RInfo, obj, tmp_load_klass);
1764 if (k->is_loaded()) {
1765 // See if we get an immediate positive hit
1766 #ifdef _LP64
1767 __ cmpptr(k_RInfo, Address(klass_RInfo, k->super_check_offset()));
1768 #else
1769 __ cmpklass(Address(klass_RInfo, k->super_check_offset()), k->constant_encoding());
1770 #endif // _LP64
1771 if ((juint)in_bytes(Klass::secondary_super_cache_offset()) != k->super_check_offset()) {
1772 __ jcc(Assembler::notEqual, *failure_target);
1773 // successful cast, fall through to profile or jump
1774 } else {
1775 // See if we get an immediate positive hit
1776 __ jcc(Assembler::equal, *success_target);
1777 // check for self
1778 #ifdef _LP64
1779 __ cmpptr(klass_RInfo, k_RInfo);
1780 #else
1781 __ cmpklass(klass_RInfo, k->constant_encoding());
1782 #endif // _LP64
1783 __ jcc(Assembler::equal, *success_target);
1784
1785 __ push(klass_RInfo);
1786 #ifdef _LP64
1787 __ push(k_RInfo);
1788 #else
1789 __ pushklass(k->constant_encoding(), noreg);
1790 #endif // _LP64
1791 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1792 __ pop(klass_RInfo);
1793 __ pop(klass_RInfo);
1794 // result is a boolean
1795 __ cmpl(klass_RInfo, 0);
1796 __ jcc(Assembler::equal, *failure_target);
1797 // successful cast, fall through to profile or jump
1798 }
1799 } else {
1800 // perform the fast part of the checking logic
1801 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL);
1802 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1803 __ push(klass_RInfo);
1804 __ push(k_RInfo);
1805 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1806 __ pop(klass_RInfo);
1807 __ pop(k_RInfo);
1808 // result is a boolean
1809 __ cmpl(k_RInfo, 0);
1810 __ jcc(Assembler::equal, *failure_target);
1811 // successful cast, fall through to profile or jump
1812 }
1813 }
1814 if (op->should_profile()) {
1815 Register mdo = klass_RInfo, recv = k_RInfo;
1816 __ bind(profile_cast_success);
1817 __ mov_metadata(mdo, md->constant_encoding());
1818 __ load_klass(recv, obj, tmp_load_klass);
1819 type_profile_helper(mdo, md, data, recv, success);
1820 __ jmp(*success);
1821
1822 __ bind(profile_cast_failure);
1823 __ mov_metadata(mdo, md->constant_encoding());
1824 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1825 __ subptr(counter_addr, DataLayout::counter_increment);
1826 __ jmp(*failure);
1827 }
1828 __ jmp(*success);
1829 }
1830
1831
1832 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
1833 Register tmp_load_klass = LP64_ONLY(rscratch1) NOT_LP64(noreg);
1834 LIR_Code code = op->code();
1835 if (code == lir_store_check) {
1836 Register value = op->object()->as_register();
1837 Register array = op->array()->as_register();
1838 Register k_RInfo = op->tmp1()->as_register();
1839 Register klass_RInfo = op->tmp2()->as_register();
1840 Register Rtmp1 = op->tmp3()->as_register();
1841
1842 CodeStub* stub = op->stub();
1843
1844 // check if it needs to be profiled
1845 ciMethodData* md = NULL;
1846 ciProfileData* data = NULL;
1847
1848 if (op->should_profile()) {
1849 ciMethod* method = op->profiled_method();
1850 assert(method != NULL, "Should have method");
1851 int bci = op->profiled_bci();
1852 md = method->method_data_or_null();
1853 assert(md != NULL, "Sanity");
1854 data = md->bci_to_data(bci);
1855 assert(data != NULL, "need data for type check");
1856 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1857 }
1858 Label profile_cast_success, profile_cast_failure, done;
1859 Label *success_target = op->should_profile() ? &profile_cast_success : &done;
1860 Label *failure_target = op->should_profile() ? &profile_cast_failure : stub->entry();
1861
1862 __ cmpptr(value, NULL_WORD);
1863 if (op->should_profile()) {
1864 Label not_null;
1865 __ jccb(Assembler::notEqual, not_null);
1866 // Object is null; update MDO and exit
1867 Register mdo = klass_RInfo;
1868 __ mov_metadata(mdo, md->constant_encoding());
1869 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()));
1870 int header_bits = BitData::null_seen_byte_constant();
1871 __ orb(data_addr, header_bits);
1872 __ jmp(done);
1873 __ bind(not_null);
1874 } else {
1875 __ jcc(Assembler::equal, done);
1876 }
1877
1878 add_debug_info_for_null_check_here(op->info_for_exception());
1879 __ load_klass(k_RInfo, array, tmp_load_klass);
1880 __ load_klass(klass_RInfo, value, tmp_load_klass);
1881
1882 // get instance klass (it's already uncompressed)
1883 __ movptr(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset()));
1884 // perform the fast part of the checking logic
1885 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL);
1886 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1887 __ push(klass_RInfo);
1888 __ push(k_RInfo);
1889 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1890 __ pop(klass_RInfo);
1891 __ pop(k_RInfo);
1892 // result is a boolean
1893 __ cmpl(k_RInfo, 0);
1894 __ jcc(Assembler::equal, *failure_target);
1895 // fall through to the success case
1896
1897 if (op->should_profile()) {
1898 Register mdo = klass_RInfo, recv = k_RInfo;
1899 __ bind(profile_cast_success);
1900 __ mov_metadata(mdo, md->constant_encoding());
1901 __ load_klass(recv, value, tmp_load_klass);
1902 type_profile_helper(mdo, md, data, recv, &done);
1903 __ jmpb(done);
1904
1905 __ bind(profile_cast_failure);
1906 __ mov_metadata(mdo, md->constant_encoding());
1907 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1908 __ subptr(counter_addr, DataLayout::counter_increment);
1909 __ jmp(*stub->entry());
1910 }
1911
1912 __ bind(done);
1913 } else
1914 if (code == lir_checkcast) {
1915 Register obj = op->object()->as_register();
1916 Register dst = op->result_opr()->as_register();
1917 Label success;
1918 emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
1919 __ bind(success);
1920 if (dst != obj) {
1921 __ mov(dst, obj);
1922 }
1923 } else
1924 if (code == lir_instanceof) {
1925 Register obj = op->object()->as_register();
1926 Register dst = op->result_opr()->as_register();
1927 Label success, failure, done;
1928 emit_typecheck_helper(op, &success, &failure, &failure);
1929 __ bind(failure);
1930 __ xorptr(dst, dst);
1931 __ jmpb(done);
1932 __ bind(success);
1933 __ movptr(dst, 1);
1934 __ bind(done);
1935 } else {
1936 ShouldNotReachHere();
1937 }
1938
1939 }
1940
1941
1942 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
1943 if (LP64_ONLY(false &&) op->code() == lir_cas_long && VM_Version::supports_cx8()) {
1944 assert(op->cmp_value()->as_register_lo() == rax, "wrong register");
1945 assert(op->cmp_value()->as_register_hi() == rdx, "wrong register");
1946 assert(op->new_value()->as_register_lo() == rbx, "wrong register");
1947 assert(op->new_value()->as_register_hi() == rcx, "wrong register");
1948 Register addr = op->addr()->as_register();
1949 __ lock();
1950 NOT_LP64(__ cmpxchg8(Address(addr, 0)));
1951
1952 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj ) {
1953 NOT_LP64(assert(op->addr()->is_single_cpu(), "must be single");)
1954 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
1955 Register newval = op->new_value()->as_register();
1956 Register cmpval = op->cmp_value()->as_register();
1957 assert(cmpval == rax, "wrong register");
1958 assert(newval != noreg, "new val must be register");
1959 assert(cmpval != newval, "cmp and new values must be in different registers");
1960 assert(cmpval != addr, "cmp and addr must be in different registers");
1961 assert(newval != addr, "new value and addr must be in different registers");
1962
1963 if ( op->code() == lir_cas_obj) {
1964 #ifdef _LP64
1965 if (UseCompressedOops) {
1966 __ encode_heap_oop(cmpval);
1967 __ mov(rscratch1, newval);
1968 __ encode_heap_oop(rscratch1);
1969 __ lock();
1970 // cmpval (rax) is implicitly used by this instruction
1971 __ cmpxchgl(rscratch1, Address(addr, 0));
1972 } else
1973 #endif
1974 {
1975 __ lock();
1976 __ cmpxchgptr(newval, Address(addr, 0));
1977 }
1978 } else {
1979 assert(op->code() == lir_cas_int, "lir_cas_int expected");
1980 __ lock();
1981 __ cmpxchgl(newval, Address(addr, 0));
1982 }
1983 #ifdef _LP64
1984 } else if (op->code() == lir_cas_long) {
1985 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
1986 Register newval = op->new_value()->as_register_lo();
1987 Register cmpval = op->cmp_value()->as_register_lo();
1988 assert(cmpval == rax, "wrong register");
1989 assert(newval != noreg, "new val must be register");
1990 assert(cmpval != newval, "cmp and new values must be in different registers");
1991 assert(cmpval != addr, "cmp and addr must be in different registers");
1992 assert(newval != addr, "new value and addr must be in different registers");
1993 __ lock();
1994 __ cmpxchgq(newval, Address(addr, 0));
1995 #endif // _LP64
1996 } else {
1997 Unimplemented();
1998 }
1999 }
2000
2001 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type,
2002 LIR_Opr cmp_opr1, LIR_Opr cmp_opr2) {
2003 assert(cmp_opr1 == LIR_OprFact::illegalOpr && cmp_opr2 == LIR_OprFact::illegalOpr, "unnecessary cmp oprs on x86");
2004
2005 Assembler::Condition acond, ncond;
2006 switch (condition) {
2007 case lir_cond_equal: acond = Assembler::equal; ncond = Assembler::notEqual; break;
2008 case lir_cond_notEqual: acond = Assembler::notEqual; ncond = Assembler::equal; break;
2009 case lir_cond_less: acond = Assembler::less; ncond = Assembler::greaterEqual; break;
2010 case lir_cond_lessEqual: acond = Assembler::lessEqual; ncond = Assembler::greater; break;
2011 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; ncond = Assembler::less; break;
2012 case lir_cond_greater: acond = Assembler::greater; ncond = Assembler::lessEqual; break;
2013 case lir_cond_belowEqual: acond = Assembler::belowEqual; ncond = Assembler::above; break;
2014 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; ncond = Assembler::below; break;
2015 default: acond = Assembler::equal; ncond = Assembler::notEqual;
2016 ShouldNotReachHere();
2017 }
2018
2019 if (opr1->is_cpu_register()) {
2020 reg2reg(opr1, result);
2021 } else if (opr1->is_stack()) {
2022 stack2reg(opr1, result, result->type());
2023 } else if (opr1->is_constant()) {
2024 const2reg(opr1, result, lir_patch_none, NULL);
2025 } else {
2026 ShouldNotReachHere();
2027 }
2028
2029 if (VM_Version::supports_cmov() && !opr2->is_constant()) {
2030 // optimized version that does not require a branch
2031 if (opr2->is_single_cpu()) {
2032 assert(opr2->cpu_regnr() != result->cpu_regnr(), "opr2 already overwritten by previous move");
2033 __ cmov(ncond, result->as_register(), opr2->as_register());
2034 } else if (opr2->is_double_cpu()) {
2035 assert(opr2->cpu_regnrLo() != result->cpu_regnrLo() && opr2->cpu_regnrLo() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
2036 assert(opr2->cpu_regnrHi() != result->cpu_regnrLo() && opr2->cpu_regnrHi() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
2037 __ cmovptr(ncond, result->as_register_lo(), opr2->as_register_lo());
2038 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), opr2->as_register_hi());)
2039 } else if (opr2->is_single_stack()) {
2040 __ cmovl(ncond, result->as_register(), frame_map()->address_for_slot(opr2->single_stack_ix()));
2041 } else if (opr2->is_double_stack()) {
2042 __ cmovptr(ncond, result->as_register_lo(), frame_map()->address_for_slot(opr2->double_stack_ix(), lo_word_offset_in_bytes));
2043 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), frame_map()->address_for_slot(opr2->double_stack_ix(), hi_word_offset_in_bytes));)
2044 } else {
2045 ShouldNotReachHere();
2046 }
2047
2048 } else {
2049 Label skip;
2050 __ jcc (acond, skip);
2051 if (opr2->is_cpu_register()) {
2052 reg2reg(opr2, result);
2053 } else if (opr2->is_stack()) {
2054 stack2reg(opr2, result, result->type());
2055 } else if (opr2->is_constant()) {
2056 const2reg(opr2, result, lir_patch_none, NULL);
2057 } else {
2058 ShouldNotReachHere();
2059 }
2060 __ bind(skip);
2061 }
2062 }
2063
2064
2065 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) {
2066 assert(info == NULL, "should never be used, idiv/irem and ldiv/lrem not handled by this method");
2067
2068 if (left->is_single_cpu()) {
2069 assert(left == dest, "left and dest must be equal");
2070 Register lreg = left->as_register();
2071
2072 if (right->is_single_cpu()) {
2073 // cpu register - cpu register
2074 Register rreg = right->as_register();
2075 switch (code) {
2076 case lir_add: __ addl (lreg, rreg); break;
2077 case lir_sub: __ subl (lreg, rreg); break;
2078 case lir_mul: __ imull(lreg, rreg); break;
2079 default: ShouldNotReachHere();
2080 }
2081
2082 } else if (right->is_stack()) {
2083 // cpu register - stack
2084 Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
2085 switch (code) {
2086 case lir_add: __ addl(lreg, raddr); break;
2087 case lir_sub: __ subl(lreg, raddr); break;
2088 default: ShouldNotReachHere();
2089 }
2090
2091 } else if (right->is_constant()) {
2092 // cpu register - constant
2093 jint c = right->as_constant_ptr()->as_jint();
2094 switch (code) {
2095 case lir_add: {
2096 __ incrementl(lreg, c);
2097 break;
2098 }
2099 case lir_sub: {
2100 __ decrementl(lreg, c);
2101 break;
2102 }
2103 default: ShouldNotReachHere();
2104 }
2105
2106 } else {
2107 ShouldNotReachHere();
2108 }
2109
2110 } else if (left->is_double_cpu()) {
2111 assert(left == dest, "left and dest must be equal");
2112 Register lreg_lo = left->as_register_lo();
2113 Register lreg_hi = left->as_register_hi();
2114
2115 if (right->is_double_cpu()) {
2116 // cpu register - cpu register
2117 Register rreg_lo = right->as_register_lo();
2118 Register rreg_hi = right->as_register_hi();
2119 NOT_LP64(assert_different_registers(lreg_lo, lreg_hi, rreg_lo, rreg_hi));
2120 LP64_ONLY(assert_different_registers(lreg_lo, rreg_lo));
2121 switch (code) {
2122 case lir_add:
2123 __ addptr(lreg_lo, rreg_lo);
2124 NOT_LP64(__ adcl(lreg_hi, rreg_hi));
2125 break;
2126 case lir_sub:
2127 __ subptr(lreg_lo, rreg_lo);
2128 NOT_LP64(__ sbbl(lreg_hi, rreg_hi));
2129 break;
2130 case lir_mul:
2131 #ifdef _LP64
2132 __ imulq(lreg_lo, rreg_lo);
2133 #else
2134 assert(lreg_lo == rax && lreg_hi == rdx, "must be");
2135 __ imull(lreg_hi, rreg_lo);
2136 __ imull(rreg_hi, lreg_lo);
2137 __ addl (rreg_hi, lreg_hi);
2138 __ mull (rreg_lo);
2139 __ addl (lreg_hi, rreg_hi);
2140 #endif // _LP64
2141 break;
2142 default:
2143 ShouldNotReachHere();
2144 }
2145
2146 } else if (right->is_constant()) {
2147 // cpu register - constant
2148 #ifdef _LP64
2149 jlong c = right->as_constant_ptr()->as_jlong_bits();
2150 __ movptr(r10, (intptr_t) c);
2151 switch (code) {
2152 case lir_add:
2153 __ addptr(lreg_lo, r10);
2154 break;
2155 case lir_sub:
2156 __ subptr(lreg_lo, r10);
2157 break;
2158 default:
2159 ShouldNotReachHere();
2160 }
2161 #else
2162 jint c_lo = right->as_constant_ptr()->as_jint_lo();
2163 jint c_hi = right->as_constant_ptr()->as_jint_hi();
2164 switch (code) {
2165 case lir_add:
2166 __ addptr(lreg_lo, c_lo);
2167 __ adcl(lreg_hi, c_hi);
2168 break;
2169 case lir_sub:
2170 __ subptr(lreg_lo, c_lo);
2171 __ sbbl(lreg_hi, c_hi);
2172 break;
2173 default:
2174 ShouldNotReachHere();
2175 }
2176 #endif // _LP64
2177
2178 } else {
2179 ShouldNotReachHere();
2180 }
2181
2182 } else if (left->is_single_xmm()) {
2183 assert(left == dest, "left and dest must be equal");
2184 XMMRegister lreg = left->as_xmm_float_reg();
2185
2186 if (right->is_single_xmm()) {
2187 XMMRegister rreg = right->as_xmm_float_reg();
2188 switch (code) {
2189 case lir_add: __ addss(lreg, rreg); break;
2190 case lir_sub: __ subss(lreg, rreg); break;
2191 case lir_mul: __ mulss(lreg, rreg); break;
2192 case lir_div: __ divss(lreg, rreg); break;
2193 default: ShouldNotReachHere();
2194 }
2195 } else {
2196 Address raddr;
2197 if (right->is_single_stack()) {
2198 raddr = frame_map()->address_for_slot(right->single_stack_ix());
2199 } else if (right->is_constant()) {
2200 // hack for now
2201 raddr = __ as_Address(InternalAddress(float_constant(right->as_jfloat())));
2202 } else {
2203 ShouldNotReachHere();
2204 }
2205 switch (code) {
2206 case lir_add: __ addss(lreg, raddr); break;
2207 case lir_sub: __ subss(lreg, raddr); break;
2208 case lir_mul: __ mulss(lreg, raddr); break;
2209 case lir_div: __ divss(lreg, raddr); break;
2210 default: ShouldNotReachHere();
2211 }
2212 }
2213
2214 } else if (left->is_double_xmm()) {
2215 assert(left == dest, "left and dest must be equal");
2216
2217 XMMRegister lreg = left->as_xmm_double_reg();
2218 if (right->is_double_xmm()) {
2219 XMMRegister rreg = right->as_xmm_double_reg();
2220 switch (code) {
2221 case lir_add: __ addsd(lreg, rreg); break;
2222 case lir_sub: __ subsd(lreg, rreg); break;
2223 case lir_mul: __ mulsd(lreg, rreg); break;
2224 case lir_div: __ divsd(lreg, rreg); break;
2225 default: ShouldNotReachHere();
2226 }
2227 } else {
2228 Address raddr;
2229 if (right->is_double_stack()) {
2230 raddr = frame_map()->address_for_slot(right->double_stack_ix());
2231 } else if (right->is_constant()) {
2232 // hack for now
2233 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble())));
2234 } else {
2235 ShouldNotReachHere();
2236 }
2237 switch (code) {
2238 case lir_add: __ addsd(lreg, raddr); break;
2239 case lir_sub: __ subsd(lreg, raddr); break;
2240 case lir_mul: __ mulsd(lreg, raddr); break;
2241 case lir_div: __ divsd(lreg, raddr); break;
2242 default: ShouldNotReachHere();
2243 }
2244 }
2245
2246 #ifndef _LP64
2247 } else if (left->is_single_fpu()) {
2248 assert(dest->is_single_fpu(), "fpu stack allocation required");
2249
2250 if (right->is_single_fpu()) {
2251 arith_fpu_implementation(code, left->fpu_regnr(), right->fpu_regnr(), dest->fpu_regnr(), pop_fpu_stack);
2252
2253 } else {
2254 assert(left->fpu_regnr() == 0, "left must be on TOS");
2255 assert(dest->fpu_regnr() == 0, "dest must be on TOS");
2256
2257 Address raddr;
2258 if (right->is_single_stack()) {
2259 raddr = frame_map()->address_for_slot(right->single_stack_ix());
2260 } else if (right->is_constant()) {
2261 address const_addr = float_constant(right->as_jfloat());
2262 assert(const_addr != NULL, "incorrect float/double constant maintenance");
2263 // hack for now
2264 raddr = __ as_Address(InternalAddress(const_addr));
2265 } else {
2266 ShouldNotReachHere();
2267 }
2268
2269 switch (code) {
2270 case lir_add: __ fadd_s(raddr); break;
2271 case lir_sub: __ fsub_s(raddr); break;
2272 case lir_mul: __ fmul_s(raddr); break;
2273 case lir_div: __ fdiv_s(raddr); break;
2274 default: ShouldNotReachHere();
2275 }
2276 }
2277
2278 } else if (left->is_double_fpu()) {
2279 assert(dest->is_double_fpu(), "fpu stack allocation required");
2280
2281 if (code == lir_mul || code == lir_div) {
2282 // Double values require special handling for strictfp mul/div on x86
2283 __ fld_x(ExternalAddress(StubRoutines::x86::addr_fpu_subnormal_bias1()));
2284 __ fmulp(left->fpu_regnrLo() + 1);
2285 }
2286
2287 if (right->is_double_fpu()) {
2288 arith_fpu_implementation(code, left->fpu_regnrLo(), right->fpu_regnrLo(), dest->fpu_regnrLo(), pop_fpu_stack);
2289
2290 } else {
2291 assert(left->fpu_regnrLo() == 0, "left must be on TOS");
2292 assert(dest->fpu_regnrLo() == 0, "dest must be on TOS");
2293
2294 Address raddr;
2295 if (right->is_double_stack()) {
2296 raddr = frame_map()->address_for_slot(right->double_stack_ix());
2297 } else if (right->is_constant()) {
2298 // hack for now
2299 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble())));
2300 } else {
2301 ShouldNotReachHere();
2302 }
2303
2304 switch (code) {
2305 case lir_add: __ fadd_d(raddr); break;
2306 case lir_sub: __ fsub_d(raddr); break;
2307 case lir_mul: __ fmul_d(raddr); break;
2308 case lir_div: __ fdiv_d(raddr); break;
2309 default: ShouldNotReachHere();
2310 }
2311 }
2312
2313 if (code == lir_mul || code == lir_div) {
2314 // Double values require special handling for strictfp mul/div on x86
2315 __ fld_x(ExternalAddress(StubRoutines::x86::addr_fpu_subnormal_bias2()));
2316 __ fmulp(dest->fpu_regnrLo() + 1);
2317 }
2318 #endif // !_LP64
2319
2320 } else if (left->is_single_stack() || left->is_address()) {
2321 assert(left == dest, "left and dest must be equal");
2322
2323 Address laddr;
2324 if (left->is_single_stack()) {
2325 laddr = frame_map()->address_for_slot(left->single_stack_ix());
2326 } else if (left->is_address()) {
2327 laddr = as_Address(left->as_address_ptr());
2328 } else {
2329 ShouldNotReachHere();
2330 }
2331
2332 if (right->is_single_cpu()) {
2333 Register rreg = right->as_register();
2334 switch (code) {
2335 case lir_add: __ addl(laddr, rreg); break;
2336 case lir_sub: __ subl(laddr, rreg); break;
2337 default: ShouldNotReachHere();
2338 }
2339 } else if (right->is_constant()) {
2340 jint c = right->as_constant_ptr()->as_jint();
2341 switch (code) {
2342 case lir_add: {
2343 __ incrementl(laddr, c);
2344 break;
2345 }
2346 case lir_sub: {
2347 __ decrementl(laddr, c);
2348 break;
2349 }
2350 default: ShouldNotReachHere();
2351 }
2352 } else {
2353 ShouldNotReachHere();
2354 }
2355
2356 } else {
2357 ShouldNotReachHere();
2358 }
2359 }
2360
2361 #ifndef _LP64
2362 void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) {
2363 assert(pop_fpu_stack || (left_index == dest_index || right_index == dest_index), "invalid LIR");
2364 assert(!pop_fpu_stack || (left_index - 1 == dest_index || right_index - 1 == dest_index), "invalid LIR");
2365 assert(left_index == 0 || right_index == 0, "either must be on top of stack");
2366
2367 bool left_is_tos = (left_index == 0);
2368 bool dest_is_tos = (dest_index == 0);
2369 int non_tos_index = (left_is_tos ? right_index : left_index);
2370
2371 switch (code) {
2372 case lir_add:
2373 if (pop_fpu_stack) __ faddp(non_tos_index);
2374 else if (dest_is_tos) __ fadd (non_tos_index);
2375 else __ fadda(non_tos_index);
2376 break;
2377
2378 case lir_sub:
2379 if (left_is_tos) {
2380 if (pop_fpu_stack) __ fsubrp(non_tos_index);
2381 else if (dest_is_tos) __ fsub (non_tos_index);
2382 else __ fsubra(non_tos_index);
2383 } else {
2384 if (pop_fpu_stack) __ fsubp (non_tos_index);
2385 else if (dest_is_tos) __ fsubr (non_tos_index);
2386 else __ fsuba (non_tos_index);
2387 }
2388 break;
2389
2390 case lir_mul:
2391 if (pop_fpu_stack) __ fmulp(non_tos_index);
2392 else if (dest_is_tos) __ fmul (non_tos_index);
2393 else __ fmula(non_tos_index);
2394 break;
2395
2396 case lir_div:
2397 if (left_is_tos) {
2398 if (pop_fpu_stack) __ fdivrp(non_tos_index);
2399 else if (dest_is_tos) __ fdiv (non_tos_index);
2400 else __ fdivra(non_tos_index);
2401 } else {
2402 if (pop_fpu_stack) __ fdivp (non_tos_index);
2403 else if (dest_is_tos) __ fdivr (non_tos_index);
2404 else __ fdiva (non_tos_index);
2405 }
2406 break;
2407
2408 case lir_rem:
2409 assert(left_is_tos && dest_is_tos && right_index == 1, "must be guaranteed by FPU stack allocation");
2410 __ fremr(noreg);
2411 break;
2412
2413 default:
2414 ShouldNotReachHere();
2415 }
2416 }
2417 #endif // _LP64
2418
2419
2420 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr tmp, LIR_Opr dest, LIR_Op* op) {
2421 if (value->is_double_xmm()) {
2422 switch(code) {
2423 case lir_abs :
2424 {
2425 #ifdef _LP64
2426 if (UseAVX > 2 && !VM_Version::supports_avx512vl()) {
2427 assert(tmp->is_valid(), "need temporary");
2428 __ vpandn(dest->as_xmm_double_reg(), tmp->as_xmm_double_reg(), value->as_xmm_double_reg(), 2);
2429 } else
2430 #endif
2431 {
2432 if (dest->as_xmm_double_reg() != value->as_xmm_double_reg()) {
2433 __ movdbl(dest->as_xmm_double_reg(), value->as_xmm_double_reg());
2434 }
2435 assert(!tmp->is_valid(), "do not need temporary");
2436 __ andpd(dest->as_xmm_double_reg(),
2437 ExternalAddress((address)double_signmask_pool),
2438 rscratch1);
2439 }
2440 }
2441 break;
2442
2443 case lir_sqrt: __ sqrtsd(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); break;
2444 // all other intrinsics are not available in the SSE instruction set, so FPU is used
2445 default : ShouldNotReachHere();
2446 }
2447
2448 #ifndef _LP64
2449 } else if (value->is_double_fpu()) {
2450 assert(value->fpu_regnrLo() == 0 && dest->fpu_regnrLo() == 0, "both must be on TOS");
2451 switch(code) {
2452 case lir_abs : __ fabs() ; break;
2453 case lir_sqrt : __ fsqrt(); break;
2454 default : ShouldNotReachHere();
2455 }
2456 #endif // !_LP64
2457 } else {
2458 Unimplemented();
2459 }
2460 }
2461
2462 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) {
2463 // assert(left->destroys_register(), "check");
2464 if (left->is_single_cpu()) {
2465 Register reg = left->as_register();
2466 if (right->is_constant()) {
2467 int val = right->as_constant_ptr()->as_jint();
2468 switch (code) {
2469 case lir_logic_and: __ andl (reg, val); break;
2470 case lir_logic_or: __ orl (reg, val); break;
2471 case lir_logic_xor: __ xorl (reg, val); break;
2472 default: ShouldNotReachHere();
2473 }
2474 } else if (right->is_stack()) {
2475 // added support for stack operands
2476 Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
2477 switch (code) {
2478 case lir_logic_and: __ andl (reg, raddr); break;
2479 case lir_logic_or: __ orl (reg, raddr); break;
2480 case lir_logic_xor: __ xorl (reg, raddr); break;
2481 default: ShouldNotReachHere();
2482 }
2483 } else {
2484 Register rright = right->as_register();
2485 switch (code) {
2486 case lir_logic_and: __ andptr (reg, rright); break;
2487 case lir_logic_or : __ orptr (reg, rright); break;
2488 case lir_logic_xor: __ xorptr (reg, rright); break;
2489 default: ShouldNotReachHere();
2490 }
2491 }
2492 move_regs(reg, dst->as_register());
2493 } else {
2494 Register l_lo = left->as_register_lo();
2495 Register l_hi = left->as_register_hi();
2496 if (right->is_constant()) {
2497 #ifdef _LP64
2498 __ mov64(rscratch1, right->as_constant_ptr()->as_jlong());
2499 switch (code) {
2500 case lir_logic_and:
2501 __ andq(l_lo, rscratch1);
2502 break;
2503 case lir_logic_or:
2504 __ orq(l_lo, rscratch1);
2505 break;
2506 case lir_logic_xor:
2507 __ xorq(l_lo, rscratch1);
2508 break;
2509 default: ShouldNotReachHere();
2510 }
2511 #else
2512 int r_lo = right->as_constant_ptr()->as_jint_lo();
2513 int r_hi = right->as_constant_ptr()->as_jint_hi();
2514 switch (code) {
2515 case lir_logic_and:
2516 __ andl(l_lo, r_lo);
2517 __ andl(l_hi, r_hi);
2518 break;
2519 case lir_logic_or:
2520 __ orl(l_lo, r_lo);
2521 __ orl(l_hi, r_hi);
2522 break;
2523 case lir_logic_xor:
2524 __ xorl(l_lo, r_lo);
2525 __ xorl(l_hi, r_hi);
2526 break;
2527 default: ShouldNotReachHere();
2528 }
2529 #endif // _LP64
2530 } else {
2531 #ifdef _LP64
2532 Register r_lo;
2533 if (is_reference_type(right->type())) {
2534 r_lo = right->as_register();
2535 } else {
2536 r_lo = right->as_register_lo();
2537 }
2538 #else
2539 Register r_lo = right->as_register_lo();
2540 Register r_hi = right->as_register_hi();
2541 assert(l_lo != r_hi, "overwriting registers");
2542 #endif
2543 switch (code) {
2544 case lir_logic_and:
2545 __ andptr(l_lo, r_lo);
2546 NOT_LP64(__ andptr(l_hi, r_hi);)
2547 break;
2548 case lir_logic_or:
2549 __ orptr(l_lo, r_lo);
2550 NOT_LP64(__ orptr(l_hi, r_hi);)
2551 break;
2552 case lir_logic_xor:
2553 __ xorptr(l_lo, r_lo);
2554 NOT_LP64(__ xorptr(l_hi, r_hi);)
2555 break;
2556 default: ShouldNotReachHere();
2557 }
2558 }
2559
2560 Register dst_lo = dst->as_register_lo();
2561 Register dst_hi = dst->as_register_hi();
2562
2563 #ifdef _LP64
2564 move_regs(l_lo, dst_lo);
2565 #else
2566 if (dst_lo == l_hi) {
2567 assert(dst_hi != l_lo, "overwriting registers");
2568 move_regs(l_hi, dst_hi);
2569 move_regs(l_lo, dst_lo);
2570 } else {
2571 assert(dst_lo != l_hi, "overwriting registers");
2572 move_regs(l_lo, dst_lo);
2573 move_regs(l_hi, dst_hi);
2574 }
2575 #endif // _LP64
2576 }
2577 }
2578
2579
2580 // we assume that rax, and rdx can be overwritten
2581 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) {
2582
2583 assert(left->is_single_cpu(), "left must be register");
2584 assert(right->is_single_cpu() || right->is_constant(), "right must be register or constant");
2585 assert(result->is_single_cpu(), "result must be register");
2586
2587 // assert(left->destroys_register(), "check");
2588 // assert(right->destroys_register(), "check");
2589
2590 Register lreg = left->as_register();
2591 Register dreg = result->as_register();
2592
2593 if (right->is_constant()) {
2594 jint divisor = right->as_constant_ptr()->as_jint();
2595 assert(divisor > 0 && is_power_of_2(divisor), "must be");
2596 if (code == lir_idiv) {
2597 assert(lreg == rax, "must be rax,");
2598 assert(temp->as_register() == rdx, "tmp register must be rdx");
2599 __ cdql(); // sign extend into rdx:rax
2600 if (divisor == 2) {
2601 __ subl(lreg, rdx);
2602 } else {
2603 __ andl(rdx, divisor - 1);
2604 __ addl(lreg, rdx);
2605 }
2606 __ sarl(lreg, log2i_exact(divisor));
2607 move_regs(lreg, dreg);
2608 } else if (code == lir_irem) {
2609 Label done;
2610 __ mov(dreg, lreg);
2611 __ andl(dreg, 0x80000000 | (divisor - 1));
2612 __ jcc(Assembler::positive, done);
2613 __ decrement(dreg);
2614 __ orl(dreg, ~(divisor - 1));
2615 __ increment(dreg);
2616 __ bind(done);
2617 } else {
2618 ShouldNotReachHere();
2619 }
2620 } else {
2621 Register rreg = right->as_register();
2622 assert(lreg == rax, "left register must be rax,");
2623 assert(rreg != rdx, "right register must not be rdx");
2624 assert(temp->as_register() == rdx, "tmp register must be rdx");
2625
2626 move_regs(lreg, rax);
2627
2628 int idivl_offset = __ corrected_idivl(rreg);
2629 if (ImplicitDiv0Checks) {
2630 add_debug_info_for_div0(idivl_offset, info);
2631 }
2632 if (code == lir_irem) {
2633 move_regs(rdx, dreg); // result is in rdx
2634 } else {
2635 move_regs(rax, dreg);
2636 }
2637 }
2638 }
2639
2640
2641 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
2642 if (opr1->is_single_cpu()) {
2643 Register reg1 = opr1->as_register();
2644 if (opr2->is_single_cpu()) {
2645 // cpu register - cpu register
2646 if (is_reference_type(opr1->type())) {
2647 __ cmpoop(reg1, opr2->as_register());
2648 } else {
2649 assert(!is_reference_type(opr2->type()), "cmp int, oop?");
2650 __ cmpl(reg1, opr2->as_register());
2651 }
2652 } else if (opr2->is_stack()) {
2653 // cpu register - stack
2654 if (is_reference_type(opr1->type())) {
2655 __ cmpoop(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2656 } else {
2657 __ cmpl(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2658 }
2659 } else if (opr2->is_constant()) {
2660 // cpu register - constant
2661 LIR_Const* c = opr2->as_constant_ptr();
2662 if (c->type() == T_INT) {
2663 __ cmpl(reg1, c->as_jint());
2664 } else if (c->type() == T_METADATA) {
2665 // All we need for now is a comparison with NULL for equality.
2666 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "oops");
2667 Metadata* m = c->as_metadata();
2668 if (m == NULL) {
2669 __ cmpptr(reg1, NULL_WORD);
2670 } else {
2671 ShouldNotReachHere();
2672 }
2673 } else if (is_reference_type(c->type())) {
2674 // In 64bit oops are single register
2675 jobject o = c->as_jobject();
2676 if (o == NULL) {
2677 __ cmpptr(reg1, NULL_WORD);
2678 } else {
2679 __ cmpoop(reg1, o, rscratch1);
2680 }
2681 } else {
2682 fatal("unexpected type: %s", basictype_to_str(c->type()));
2683 }
2684 // cpu register - address
2685 } else if (opr2->is_address()) {
2686 if (op->info() != NULL) {
2687 add_debug_info_for_null_check_here(op->info());
2688 }
2689 __ cmpl(reg1, as_Address(opr2->as_address_ptr()));
2690 } else {
2691 ShouldNotReachHere();
2692 }
2693
2694 } else if(opr1->is_double_cpu()) {
2695 Register xlo = opr1->as_register_lo();
2696 Register xhi = opr1->as_register_hi();
2697 if (opr2->is_double_cpu()) {
2698 #ifdef _LP64
2699 __ cmpptr(xlo, opr2->as_register_lo());
2700 #else
2701 // cpu register - cpu register
2702 Register ylo = opr2->as_register_lo();
2703 Register yhi = opr2->as_register_hi();
2704 __ subl(xlo, ylo);
2705 __ sbbl(xhi, yhi);
2706 if (condition == lir_cond_equal || condition == lir_cond_notEqual) {
2707 __ orl(xhi, xlo);
2708 }
2709 #endif // _LP64
2710 } else if (opr2->is_constant()) {
2711 // cpu register - constant 0
2712 assert(opr2->as_jlong() == (jlong)0, "only handles zero");
2713 #ifdef _LP64
2714 __ cmpptr(xlo, (int32_t)opr2->as_jlong());
2715 #else
2716 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles equals case");
2717 __ orl(xhi, xlo);
2718 #endif // _LP64
2719 } else {
2720 ShouldNotReachHere();
2721 }
2722
2723 } else if (opr1->is_single_xmm()) {
2724 XMMRegister reg1 = opr1->as_xmm_float_reg();
2725 if (opr2->is_single_xmm()) {
2726 // xmm register - xmm register
2727 __ ucomiss(reg1, opr2->as_xmm_float_reg());
2728 } else if (opr2->is_stack()) {
2729 // xmm register - stack
2730 __ ucomiss(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2731 } else if (opr2->is_constant()) {
2732 // xmm register - constant
2733 __ ucomiss(reg1, InternalAddress(float_constant(opr2->as_jfloat())));
2734 } else if (opr2->is_address()) {
2735 // xmm register - address
2736 if (op->info() != NULL) {
2737 add_debug_info_for_null_check_here(op->info());
2738 }
2739 __ ucomiss(reg1, as_Address(opr2->as_address_ptr()));
2740 } else {
2741 ShouldNotReachHere();
2742 }
2743
2744 } else if (opr1->is_double_xmm()) {
2745 XMMRegister reg1 = opr1->as_xmm_double_reg();
2746 if (opr2->is_double_xmm()) {
2747 // xmm register - xmm register
2748 __ ucomisd(reg1, opr2->as_xmm_double_reg());
2749 } else if (opr2->is_stack()) {
2750 // xmm register - stack
2751 __ ucomisd(reg1, frame_map()->address_for_slot(opr2->double_stack_ix()));
2752 } else if (opr2->is_constant()) {
2753 // xmm register - constant
2754 __ ucomisd(reg1, InternalAddress(double_constant(opr2->as_jdouble())));
2755 } else if (opr2->is_address()) {
2756 // xmm register - address
2757 if (op->info() != NULL) {
2758 add_debug_info_for_null_check_here(op->info());
2759 }
2760 __ ucomisd(reg1, as_Address(opr2->pointer()->as_address()));
2761 } else {
2762 ShouldNotReachHere();
2763 }
2764
2765 #ifndef _LP64
2766 } else if(opr1->is_single_fpu() || opr1->is_double_fpu()) {
2767 assert(opr1->is_fpu_register() && opr1->fpu() == 0, "currently left-hand side must be on TOS (relax this restriction)");
2768 assert(opr2->is_fpu_register(), "both must be registers");
2769 __ fcmp(noreg, opr2->fpu(), op->fpu_pop_count() > 0, op->fpu_pop_count() > 1);
2770 #endif // LP64
2771
2772 } else if (opr1->is_address() && opr2->is_constant()) {
2773 LIR_Const* c = opr2->as_constant_ptr();
2774 #ifdef _LP64
2775 if (is_reference_type(c->type())) {
2776 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "need to reverse");
2777 __ movoop(rscratch1, c->as_jobject());
2778 }
2779 #endif // LP64
2780 if (op->info() != NULL) {
2781 add_debug_info_for_null_check_here(op->info());
2782 }
2783 // special case: address - constant
2784 LIR_Address* addr = opr1->as_address_ptr();
2785 if (c->type() == T_INT) {
2786 __ cmpl(as_Address(addr), c->as_jint());
2787 } else if (is_reference_type(c->type())) {
2788 #ifdef _LP64
2789 // %%% Make this explode if addr isn't reachable until we figure out a
2790 // better strategy by giving noreg as the temp for as_Address
2791 __ cmpoop(rscratch1, as_Address(addr, noreg));
2792 #else
2793 __ cmpoop(as_Address(addr), c->as_jobject());
2794 #endif // _LP64
2795 } else {
2796 ShouldNotReachHere();
2797 }
2798
2799 } else {
2800 ShouldNotReachHere();
2801 }
2802 }
2803
2804 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op) {
2805 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
2806 if (left->is_single_xmm()) {
2807 assert(right->is_single_xmm(), "must match");
2808 __ cmpss2int(left->as_xmm_float_reg(), right->as_xmm_float_reg(), dst->as_register(), code == lir_ucmp_fd2i);
2809 } else if (left->is_double_xmm()) {
2810 assert(right->is_double_xmm(), "must match");
2811 __ cmpsd2int(left->as_xmm_double_reg(), right->as_xmm_double_reg(), dst->as_register(), code == lir_ucmp_fd2i);
2812
2813 } else {
2814 #ifdef _LP64
2815 ShouldNotReachHere();
2816 #else
2817 assert(left->is_single_fpu() || left->is_double_fpu(), "must be");
2818 assert(right->is_single_fpu() || right->is_double_fpu(), "must match");
2819
2820 assert(left->fpu() == 0, "left must be on TOS");
2821 __ fcmp2int(dst->as_register(), code == lir_ucmp_fd2i, right->fpu(),
2822 op->fpu_pop_count() > 0, op->fpu_pop_count() > 1);
2823 #endif // LP64
2824 }
2825 } else {
2826 assert(code == lir_cmp_l2i, "check");
2827 #ifdef _LP64
2828 Label done;
2829 Register dest = dst->as_register();
2830 __ cmpptr(left->as_register_lo(), right->as_register_lo());
2831 __ movl(dest, -1);
2832 __ jccb(Assembler::less, done);
2833 __ set_byte_if_not_zero(dest);
2834 __ movzbl(dest, dest);
2835 __ bind(done);
2836 #else
2837 __ lcmp2int(left->as_register_hi(),
2838 left->as_register_lo(),
2839 right->as_register_hi(),
2840 right->as_register_lo());
2841 move_regs(left->as_register_hi(), dst->as_register());
2842 #endif // _LP64
2843 }
2844 }
2845
2846
2847 void LIR_Assembler::align_call(LIR_Code code) {
2848 // make sure that the displacement word of the call ends up word aligned
2849 int offset = __ offset();
2850 switch (code) {
2851 case lir_static_call:
2852 case lir_optvirtual_call:
2853 case lir_dynamic_call:
2854 offset += NativeCall::displacement_offset;
2855 break;
2856 case lir_icvirtual_call:
2857 offset += NativeCall::displacement_offset + NativeMovConstReg::instruction_size;
2858 break;
2859 default: ShouldNotReachHere();
2860 }
2861 __ align(BytesPerWord, offset);
2862 }
2863
2864
2865 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
2866 assert((__ offset() + NativeCall::displacement_offset) % BytesPerWord == 0,
2867 "must be aligned");
2868 __ call(AddressLiteral(op->addr(), rtype));
2869 add_call_info(code_offset(), op->info());
2870 __ post_call_nop();
2871 }
2872
2873
2874 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
2875 __ ic_call(op->addr());
2876 add_call_info(code_offset(), op->info());
2877 assert((__ offset() - NativeCall::instruction_size + NativeCall::displacement_offset) % BytesPerWord == 0,
2878 "must be aligned");
2879 __ post_call_nop();
2880 }
2881
2882
2883 void LIR_Assembler::emit_static_call_stub() {
2884 address call_pc = __ pc();
2885 address stub = __ start_a_stub(call_stub_size());
2886 if (stub == NULL) {
2887 bailout("static call stub overflow");
2888 return;
2889 }
2890
2891 int start = __ offset();
2892
2893 // make sure that the displacement word of the call ends up word aligned
2894 __ align(BytesPerWord, __ offset() + NativeMovConstReg::instruction_size + NativeCall::displacement_offset);
2895 __ relocate(static_stub_Relocation::spec(call_pc));
2896 __ mov_metadata(rbx, (Metadata*)NULL);
2897 // must be set to -1 at code generation time
2898 assert(((__ offset() + 1) % BytesPerWord) == 0, "must be aligned");
2899 // On 64bit this will die since it will take a movq & jmp, must be only a jmp
2900 __ jump(RuntimeAddress(__ pc()));
2901
2902 assert(__ offset() - start <= call_stub_size(), "stub too big");
2903 __ end_a_stub();
2904 }
2905
2906
2907 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
2908 assert(exceptionOop->as_register() == rax, "must match");
2909 assert(exceptionPC->as_register() == rdx, "must match");
2910
2911 // exception object is not added to oop map by LinearScan
2912 // (LinearScan assumes that no oops are in fixed registers)
2913 info->add_register_oop(exceptionOop);
2914 Runtime1::StubID unwind_id;
2915
2916 // get current pc information
2917 // pc is only needed if the method has an exception handler, the unwind code does not need it.
2918 int pc_for_athrow_offset = __ offset();
2919 InternalAddress pc_for_athrow(__ pc());
2920 __ lea(exceptionPC->as_register(), pc_for_athrow);
2921 add_call_info(pc_for_athrow_offset, info); // for exception handler
2922
2923 __ verify_not_null_oop(rax);
2924 // search an exception handler (rax: exception oop, rdx: throwing pc)
2925 if (compilation()->has_fpu_code()) {
2926 unwind_id = Runtime1::handle_exception_id;
2927 } else {
2928 unwind_id = Runtime1::handle_exception_nofpu_id;
2929 }
2930 __ call(RuntimeAddress(Runtime1::entry_for(unwind_id)));
2931
2932 // enough room for two byte trap
2933 __ nop();
2934 }
2935
2936
2937 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
2938 assert(exceptionOop->as_register() == rax, "must match");
2939
2940 __ jmp(_unwind_handler_entry);
2941 }
2942
2943
2944 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2945
2946 // optimized version for linear scan:
2947 // * count must be already in ECX (guaranteed by LinearScan)
2948 // * left and dest must be equal
2949 // * tmp must be unused
2950 assert(count->as_register() == SHIFT_count, "count must be in ECX");
2951 assert(left == dest, "left and dest must be equal");
2952 assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2953
2954 if (left->is_single_cpu()) {
2955 Register value = left->as_register();
2956 assert(value != SHIFT_count, "left cannot be ECX");
2957
2958 switch (code) {
2959 case lir_shl: __ shll(value); break;
2960 case lir_shr: __ sarl(value); break;
2961 case lir_ushr: __ shrl(value); break;
2962 default: ShouldNotReachHere();
2963 }
2964 } else if (left->is_double_cpu()) {
2965 Register lo = left->as_register_lo();
2966 Register hi = left->as_register_hi();
2967 assert(lo != SHIFT_count && hi != SHIFT_count, "left cannot be ECX");
2968 #ifdef _LP64
2969 switch (code) {
2970 case lir_shl: __ shlptr(lo); break;
2971 case lir_shr: __ sarptr(lo); break;
2972 case lir_ushr: __ shrptr(lo); break;
2973 default: ShouldNotReachHere();
2974 }
2975 #else
2976
2977 switch (code) {
2978 case lir_shl: __ lshl(hi, lo); break;
2979 case lir_shr: __ lshr(hi, lo, true); break;
2980 case lir_ushr: __ lshr(hi, lo, false); break;
2981 default: ShouldNotReachHere();
2982 }
2983 #endif // LP64
2984 } else {
2985 ShouldNotReachHere();
2986 }
2987 }
2988
2989
2990 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2991 if (dest->is_single_cpu()) {
2992 // first move left into dest so that left is not destroyed by the shift
2993 Register value = dest->as_register();
2994 count = count & 0x1F; // Java spec
2995
2996 move_regs(left->as_register(), value);
2997 switch (code) {
2998 case lir_shl: __ shll(value, count); break;
2999 case lir_shr: __ sarl(value, count); break;
3000 case lir_ushr: __ shrl(value, count); break;
3001 default: ShouldNotReachHere();
3002 }
3003 } else if (dest->is_double_cpu()) {
3004 #ifndef _LP64
3005 Unimplemented();
3006 #else
3007 // first move left into dest so that left is not destroyed by the shift
3008 Register value = dest->as_register_lo();
3009 count = count & 0x1F; // Java spec
3010
3011 move_regs(left->as_register_lo(), value);
3012 switch (code) {
3013 case lir_shl: __ shlptr(value, count); break;
3014 case lir_shr: __ sarptr(value, count); break;
3015 case lir_ushr: __ shrptr(value, count); break;
3016 default: ShouldNotReachHere();
3017 }
3018 #endif // _LP64
3019 } else {
3020 ShouldNotReachHere();
3021 }
3022 }
3023
3024
3025 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) {
3026 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3027 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3028 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3029 __ movptr (Address(rsp, offset_from_rsp_in_bytes), r);
3030 }
3031
3032
3033 void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) {
3034 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3035 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3036 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3037 __ movptr (Address(rsp, offset_from_rsp_in_bytes), c);
3038 }
3039
3040
3041 void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) {
3042 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3043 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3044 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3045 __ movoop(Address(rsp, offset_from_rsp_in_bytes), o, rscratch1);
3046 }
3047
3048
3049 void LIR_Assembler::store_parameter(Metadata* m, int offset_from_rsp_in_words) {
3050 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3051 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3052 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3053 __ mov_metadata(Address(rsp, offset_from_rsp_in_bytes), m, rscratch1);
3054 }
3055
3056
3057 // This code replaces a call to arraycopy; no exception may
3058 // be thrown in this code, they must be thrown in the System.arraycopy
3059 // activation frame; we could save some checks if this would not be the case
3060 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
3061 ciArrayKlass* default_type = op->expected_type();
3062 Register src = op->src()->as_register();
3063 Register dst = op->dst()->as_register();
3064 Register src_pos = op->src_pos()->as_register();
3065 Register dst_pos = op->dst_pos()->as_register();
3066 Register length = op->length()->as_register();
3067 Register tmp = op->tmp()->as_register();
3068 Register tmp_load_klass = LP64_ONLY(rscratch1) NOT_LP64(noreg);
3069
3070 CodeStub* stub = op->stub();
3071 int flags = op->flags();
3072 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL;
3073 if (is_reference_type(basic_type)) basic_type = T_OBJECT;
3074
3075 // if we don't know anything, just go through the generic arraycopy
3076 if (default_type == NULL) {
3077 // save outgoing arguments on stack in case call to System.arraycopy is needed
3078 // HACK ALERT. This code used to push the parameters in a hardwired fashion
3079 // for interpreter calling conventions. Now we have to do it in new style conventions.
3080 // For the moment until C1 gets the new register allocator I just force all the
3081 // args to the right place (except the register args) and then on the back side
3082 // reload the register args properly if we go slow path. Yuck
3083
3084 // These are proper for the calling convention
3085 store_parameter(length, 2);
3086 store_parameter(dst_pos, 1);
3087 store_parameter(dst, 0);
3088
3089 // these are just temporary placements until we need to reload
3090 store_parameter(src_pos, 3);
3091 store_parameter(src, 4);
3092 NOT_LP64(assert(src == rcx && src_pos == rdx, "mismatch in calling convention");)
3093
3094 address copyfunc_addr = StubRoutines::generic_arraycopy();
3095 assert(copyfunc_addr != NULL, "generic arraycopy stub required");
3096
3097 // pass arguments: may push as this is not a safepoint; SP must be fix at each safepoint
3098 #ifdef _LP64
3099 // The arguments are in java calling convention so we can trivially shift them to C
3100 // convention
3101 assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4);
3102 __ mov(c_rarg0, j_rarg0);
3103 assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4);
3104 __ mov(c_rarg1, j_rarg1);
3105 assert_different_registers(c_rarg2, j_rarg3, j_rarg4);
3106 __ mov(c_rarg2, j_rarg2);
3107 assert_different_registers(c_rarg3, j_rarg4);
3108 __ mov(c_rarg3, j_rarg3);
3109 #ifdef _WIN64
3110 // Allocate abi space for args but be sure to keep stack aligned
3111 __ subptr(rsp, 6*wordSize);
3112 store_parameter(j_rarg4, 4);
3113 #ifndef PRODUCT
3114 if (PrintC1Statistics) {
3115 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt), rscratch1);
3116 }
3117 #endif
3118 __ call(RuntimeAddress(copyfunc_addr));
3119 __ addptr(rsp, 6*wordSize);
3120 #else
3121 __ mov(c_rarg4, j_rarg4);
3122 #ifndef PRODUCT
3123 if (PrintC1Statistics) {
3124 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt), rscratch1);
3125 }
3126 #endif
3127 __ call(RuntimeAddress(copyfunc_addr));
3128 #endif // _WIN64
3129 #else
3130 __ push(length);
3131 __ push(dst_pos);
3132 __ push(dst);
3133 __ push(src_pos);
3134 __ push(src);
3135
3136 #ifndef PRODUCT
3137 if (PrintC1Statistics) {
3138 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt), rscratch1);
3139 }
3140 #endif
3141 __ call_VM_leaf(copyfunc_addr, 5); // removes pushed parameter from the stack
3142
3143 #endif // _LP64
3144
3145 __ cmpl(rax, 0);
3146 __ jcc(Assembler::equal, *stub->continuation());
3147
3148 __ mov(tmp, rax);
3149 __ xorl(tmp, -1);
3150
3151 // Reload values from the stack so they are where the stub
3152 // expects them.
3153 __ movptr (dst, Address(rsp, 0*BytesPerWord));
3154 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord));
3155 __ movptr (length, Address(rsp, 2*BytesPerWord));
3156 __ movptr (src_pos, Address(rsp, 3*BytesPerWord));
3157 __ movptr (src, Address(rsp, 4*BytesPerWord));
3158
3159 __ subl(length, tmp);
3160 __ addl(src_pos, tmp);
3161 __ addl(dst_pos, tmp);
3162 __ jmp(*stub->entry());
3163
3164 __ bind(*stub->continuation());
3165 return;
3166 }
3167
3168 assert(default_type != NULL && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
3169
3170 int elem_size = type2aelembytes(basic_type);
3171 Address::ScaleFactor scale;
3172
3173 switch (elem_size) {
3174 case 1 :
3175 scale = Address::times_1;
3176 break;
3177 case 2 :
3178 scale = Address::times_2;
3179 break;
3180 case 4 :
3181 scale = Address::times_4;
3182 break;
3183 case 8 :
3184 scale = Address::times_8;
3185 break;
3186 default:
3187 scale = Address::no_scale;
3188 ShouldNotReachHere();
3189 }
3190
3191 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes());
3192 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes());
3193 Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes());
3194 Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes());
3195
3196 // length and pos's are all sign extended at this point on 64bit
3197
3198 // test for NULL
3199 if (flags & LIR_OpArrayCopy::src_null_check) {
3200 __ testptr(src, src);
3201 __ jcc(Assembler::zero, *stub->entry());
3202 }
3203 if (flags & LIR_OpArrayCopy::dst_null_check) {
3204 __ testptr(dst, dst);
3205 __ jcc(Assembler::zero, *stub->entry());
3206 }
3207
3208 // If the compiler was not able to prove that exact type of the source or the destination
3209 // of the arraycopy is an array type, check at runtime if the source or the destination is
3210 // an instance type.
3211 if (flags & LIR_OpArrayCopy::type_check) {
3212 if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
3213 __ load_klass(tmp, dst, tmp_load_klass);
3214 __ cmpl(Address(tmp, in_bytes(Klass::layout_helper_offset())), Klass::_lh_neutral_value);
3215 __ jcc(Assembler::greaterEqual, *stub->entry());
3216 }
3217
3218 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
3219 __ load_klass(tmp, src, tmp_load_klass);
3220 __ cmpl(Address(tmp, in_bytes(Klass::layout_helper_offset())), Klass::_lh_neutral_value);
3221 __ jcc(Assembler::greaterEqual, *stub->entry());
3222 }
3223 }
3224
3225 // check if negative
3226 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
3227 __ testl(src_pos, src_pos);
3228 __ jcc(Assembler::less, *stub->entry());
3229 }
3230 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
3231 __ testl(dst_pos, dst_pos);
3232 __ jcc(Assembler::less, *stub->entry());
3233 }
3234
3235 if (flags & LIR_OpArrayCopy::src_range_check) {
3236 __ lea(tmp, Address(src_pos, length, Address::times_1, 0));
3237 __ cmpl(tmp, src_length_addr);
3238 __ jcc(Assembler::above, *stub->entry());
3239 }
3240 if (flags & LIR_OpArrayCopy::dst_range_check) {
3241 __ lea(tmp, Address(dst_pos, length, Address::times_1, 0));
3242 __ cmpl(tmp, dst_length_addr);
3243 __ jcc(Assembler::above, *stub->entry());
3244 }
3245
3246 if (flags & LIR_OpArrayCopy::length_positive_check) {
3247 __ testl(length, length);
3248 __ jcc(Assembler::less, *stub->entry());
3249 }
3250
3251 #ifdef _LP64
3252 __ movl2ptr(src_pos, src_pos); //higher 32bits must be null
3253 __ movl2ptr(dst_pos, dst_pos); //higher 32bits must be null
3254 #endif
3255
3256 if (flags & LIR_OpArrayCopy::type_check) {
3257 // We don't know the array types are compatible
3258 if (basic_type != T_OBJECT) {
3259 // Simple test for basic type arrays
3260 if (UseCompressedClassPointers) {
3261 __ movl(tmp, src_klass_addr);
3262 __ cmpl(tmp, dst_klass_addr);
3263 } else {
3264 __ movptr(tmp, src_klass_addr);
3265 __ cmpptr(tmp, dst_klass_addr);
3266 }
3267 __ jcc(Assembler::notEqual, *stub->entry());
3268 } else {
3269 // For object arrays, if src is a sub class of dst then we can
3270 // safely do the copy.
3271 Label cont, slow;
3272
3273 __ push(src);
3274 __ push(dst);
3275
3276 __ load_klass(src, src, tmp_load_klass);
3277 __ load_klass(dst, dst, tmp_load_klass);
3278
3279 __ check_klass_subtype_fast_path(src, dst, tmp, &cont, &slow, NULL);
3280
3281 __ push(src);
3282 __ push(dst);
3283 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
3284 __ pop(dst);
3285 __ pop(src);
3286
3287 __ cmpl(src, 0);
3288 __ jcc(Assembler::notEqual, cont);
3289
3290 __ bind(slow);
3291 __ pop(dst);
3292 __ pop(src);
3293
3294 address copyfunc_addr = StubRoutines::checkcast_arraycopy();
3295 if (copyfunc_addr != NULL) { // use stub if available
3296 // src is not a sub class of dst so we have to do a
3297 // per-element check.
3298
3299 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
3300 if ((flags & mask) != mask) {
3301 // Check that at least both of them object arrays.
3302 assert(flags & mask, "one of the two should be known to be an object array");
3303
3304 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
3305 __ load_klass(tmp, src, tmp_load_klass);
3306 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
3307 __ load_klass(tmp, dst, tmp_load_klass);
3308 }
3309 int lh_offset = in_bytes(Klass::layout_helper_offset());
3310 Address klass_lh_addr(tmp, lh_offset);
3311 jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
3312 __ cmpl(klass_lh_addr, objArray_lh);
3313 __ jcc(Assembler::notEqual, *stub->entry());
3314 }
3315
3316 // Spill because stubs can use any register they like and it's
3317 // easier to restore just those that we care about.
3318 store_parameter(dst, 0);
3319 store_parameter(dst_pos, 1);
3320 store_parameter(length, 2);
3321 store_parameter(src_pos, 3);
3322 store_parameter(src, 4);
3323
3324 #ifndef _LP64
3325 __ movptr(tmp, dst_klass_addr);
3326 __ movptr(tmp, Address(tmp, ObjArrayKlass::element_klass_offset()));
3327 __ push(tmp);
3328 __ movl(tmp, Address(tmp, Klass::super_check_offset_offset()));
3329 __ push(tmp);
3330 __ push(length);
3331 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3332 __ push(tmp);
3333 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3334 __ push(tmp);
3335
3336 __ call_VM_leaf(copyfunc_addr, 5);
3337 #else
3338 __ movl2ptr(length, length); //higher 32bits must be null
3339
3340 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3341 assert_different_registers(c_rarg0, dst, dst_pos, length);
3342 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3343 assert_different_registers(c_rarg1, dst, length);
3344
3345 __ mov(c_rarg2, length);
3346 assert_different_registers(c_rarg2, dst);
3347
3348 #ifdef _WIN64
3349 // Allocate abi space for args but be sure to keep stack aligned
3350 __ subptr(rsp, 6*wordSize);
3351 __ load_klass(c_rarg3, dst, tmp_load_klass);
3352 __ movptr(c_rarg3, Address(c_rarg3, ObjArrayKlass::element_klass_offset()));
3353 store_parameter(c_rarg3, 4);
3354 __ movl(c_rarg3, Address(c_rarg3, Klass::super_check_offset_offset()));
3355 __ call(RuntimeAddress(copyfunc_addr));
3356 __ addptr(rsp, 6*wordSize);
3357 #else
3358 __ load_klass(c_rarg4, dst, tmp_load_klass);
3359 __ movptr(c_rarg4, Address(c_rarg4, ObjArrayKlass::element_klass_offset()));
3360 __ movl(c_rarg3, Address(c_rarg4, Klass::super_check_offset_offset()));
3361 __ call(RuntimeAddress(copyfunc_addr));
3362 #endif
3363
3364 #endif
3365
3366 #ifndef PRODUCT
3367 if (PrintC1Statistics) {
3368 Label failed;
3369 __ testl(rax, rax);
3370 __ jcc(Assembler::notZero, failed);
3371 __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt), rscratch1);
3372 __ bind(failed);
3373 }
3374 #endif
3375
3376 __ testl(rax, rax);
3377 __ jcc(Assembler::zero, *stub->continuation());
3378
3379 #ifndef PRODUCT
3380 if (PrintC1Statistics) {
3381 __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt), rscratch1);
3382 }
3383 #endif
3384
3385 __ mov(tmp, rax);
3386
3387 __ xorl(tmp, -1);
3388
3389 // Restore previously spilled arguments
3390 __ movptr (dst, Address(rsp, 0*BytesPerWord));
3391 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord));
3392 __ movptr (length, Address(rsp, 2*BytesPerWord));
3393 __ movptr (src_pos, Address(rsp, 3*BytesPerWord));
3394 __ movptr (src, Address(rsp, 4*BytesPerWord));
3395
3396
3397 __ subl(length, tmp);
3398 __ addl(src_pos, tmp);
3399 __ addl(dst_pos, tmp);
3400 }
3401
3402 __ jmp(*stub->entry());
3403
3404 __ bind(cont);
3405 __ pop(dst);
3406 __ pop(src);
3407 }
3408 }
3409
3410 #ifdef ASSERT
3411 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
3412 // Sanity check the known type with the incoming class. For the
3413 // primitive case the types must match exactly with src.klass and
3414 // dst.klass each exactly matching the default type. For the
3415 // object array case, if no type check is needed then either the
3416 // dst type is exactly the expected type and the src type is a
3417 // subtype which we can't check or src is the same array as dst
3418 // but not necessarily exactly of type default_type.
3419 Label known_ok, halt;
3420 __ mov_metadata(tmp, default_type->constant_encoding());
3421 #ifdef _LP64
3422 if (UseCompressedClassPointers) {
3423 __ encode_klass_not_null(tmp, rscratch1);
3424 }
3425 #endif
3426
3427 if (basic_type != T_OBJECT) {
3428
3429 if (UseCompressedClassPointers) __ cmpl(tmp, dst_klass_addr);
3430 else __ cmpptr(tmp, dst_klass_addr);
3431 __ jcc(Assembler::notEqual, halt);
3432 if (UseCompressedClassPointers) __ cmpl(tmp, src_klass_addr);
3433 else __ cmpptr(tmp, src_klass_addr);
3434 __ jcc(Assembler::equal, known_ok);
3435 } else {
3436 if (UseCompressedClassPointers) __ cmpl(tmp, dst_klass_addr);
3437 else __ cmpptr(tmp, dst_klass_addr);
3438 __ jcc(Assembler::equal, known_ok);
3439 __ cmpptr(src, dst);
3440 __ jcc(Assembler::equal, known_ok);
3441 }
3442 __ bind(halt);
3443 __ stop("incorrect type information in arraycopy");
3444 __ bind(known_ok);
3445 }
3446 #endif
3447
3448 #ifndef PRODUCT
3449 if (PrintC1Statistics) {
3450 __ incrementl(ExternalAddress(Runtime1::arraycopy_count_address(basic_type)), rscratch1);
3451 }
3452 #endif
3453
3454 #ifdef _LP64
3455 assert_different_registers(c_rarg0, dst, dst_pos, length);
3456 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3457 assert_different_registers(c_rarg1, length);
3458 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3459 __ mov(c_rarg2, length);
3460
3461 #else
3462 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3463 store_parameter(tmp, 0);
3464 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3465 store_parameter(tmp, 1);
3466 store_parameter(length, 2);
3467 #endif // _LP64
3468
3469 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
3470 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
3471 const char *name;
3472 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
3473 __ call_VM_leaf(entry, 0);
3474
3475 __ bind(*stub->continuation());
3476 }
3477
3478 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
3479 assert(op->crc()->is_single_cpu(), "crc must be register");
3480 assert(op->val()->is_single_cpu(), "byte value must be register");
3481 assert(op->result_opr()->is_single_cpu(), "result must be register");
3482 Register crc = op->crc()->as_register();
3483 Register val = op->val()->as_register();
3484 Register res = op->result_opr()->as_register();
3485
3486 assert_different_registers(val, crc, res);
3487
3488 __ lea(res, ExternalAddress(StubRoutines::crc_table_addr()));
3489 __ notl(crc); // ~crc
3490 __ update_byte_crc32(crc, val, res);
3491 __ notl(crc); // ~crc
3492 __ mov(res, crc);
3493 }
3494
3495 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
3496 Register obj = op->obj_opr()->as_register(); // may not be an oop
3497 Register hdr = op->hdr_opr()->as_register();
3498 Register lock = op->lock_opr()->as_register();
3499 if (UseHeavyMonitors) {
3500 if (op->info() != NULL) {
3501 add_debug_info_for_null_check_here(op->info());
3502 __ null_check(obj);
3503 }
3504 __ jmp(*op->stub()->entry());
3505 } else if (op->code() == lir_lock) {
3506 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
3507 // add debug info for NullPointerException only if one is possible
3508 int null_check_offset = __ lock_object(hdr, obj, lock, *op->stub()->entry());
3509 if (op->info() != NULL) {
3510 add_debug_info_for_null_check(null_check_offset, op->info());
3511 }
3512 // done
3513 } else if (op->code() == lir_unlock) {
3514 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
3515 __ unlock_object(hdr, obj, lock, *op->stub()->entry());
3516 } else {
3517 Unimplemented();
3518 }
3519 __ bind(*op->stub()->continuation());
3520 }
3521
3522 void LIR_Assembler::emit_load_klass(LIR_OpLoadKlass* op) {
3523 Register obj = op->obj()->as_pointer_register();
3524 Register result = op->result_opr()->as_pointer_register();
3525
3526 CodeEmitInfo* info = op->info();
3527 if (info != NULL) {
3528 add_debug_info_for_null_check_here(info);
3529 }
3530
3531 #ifdef _LP64
3532 if (UseCompressedClassPointers) {
3533 __ movl(result, Address(obj, oopDesc::klass_offset_in_bytes()));
3534 __ decode_klass_not_null(result, rscratch1);
3535 } else
3536 #endif
3537 __ movptr(result, Address(obj, oopDesc::klass_offset_in_bytes()));
3538 }
3539
3540 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
3541 ciMethod* method = op->profiled_method();
3542 int bci = op->profiled_bci();
3543 ciMethod* callee = op->profiled_callee();
3544 Register tmp_load_klass = LP64_ONLY(rscratch1) NOT_LP64(noreg);
3545
3546 // Update counter for all call types
3547 ciMethodData* md = method->method_data_or_null();
3548 assert(md != NULL, "Sanity");
3549 ciProfileData* data = md->bci_to_data(bci);
3550 assert(data != NULL && data->is_CounterData(), "need CounterData for calls");
3551 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
3552 Register mdo = op->mdo()->as_register();
3553 __ mov_metadata(mdo, md->constant_encoding());
3554 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
3555 // Perform additional virtual call profiling for invokevirtual and
3556 // invokeinterface bytecodes
3557 if (op->should_profile_receiver_type()) {
3558 assert(op->recv()->is_single_cpu(), "recv must be allocated");
3559 Register recv = op->recv()->as_register();
3560 assert_different_registers(mdo, recv);
3561 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
3562 ciKlass* known_klass = op->known_holder();
3563 if (C1OptimizeVirtualCallProfiling && known_klass != NULL) {
3564 // We know the type that will be seen at this call site; we can
3565 // statically update the MethodData* rather than needing to do
3566 // dynamic tests on the receiver type
3567
3568 // NOTE: we should probably put a lock around this search to
3569 // avoid collisions by concurrent compilations
3570 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
3571 uint i;
3572 for (i = 0; i < VirtualCallData::row_limit(); i++) {
3573 ciKlass* receiver = vc_data->receiver(i);
3574 if (known_klass->equals(receiver)) {
3575 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
3576 __ addptr(data_addr, DataLayout::counter_increment);
3577 return;
3578 }
3579 }
3580
3581 // Receiver type not found in profile data; select an empty slot
3582
3583 // Note that this is less efficient than it should be because it
3584 // always does a write to the receiver part of the
3585 // VirtualCallData rather than just the first time
3586 for (i = 0; i < VirtualCallData::row_limit(); i++) {
3587 ciKlass* receiver = vc_data->receiver(i);
3588 if (receiver == NULL) {
3589 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)));
3590 __ mov_metadata(recv_addr, known_klass->constant_encoding(), rscratch1);
3591 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
3592 __ addptr(data_addr, DataLayout::counter_increment);
3593 return;
3594 }
3595 }
3596 } else {
3597 __ load_klass(recv, recv, tmp_load_klass);
3598 Label update_done;
3599 type_profile_helper(mdo, md, data, recv, &update_done);
3600 // Receiver did not match any saved receiver and there is no empty row for it.
3601 // Increment total counter to indicate polymorphic case.
3602 __ addptr(counter_addr, DataLayout::counter_increment);
3603
3604 __ bind(update_done);
3605 }
3606 } else {
3607 // Static call
3608 __ addptr(counter_addr, DataLayout::counter_increment);
3609 }
3610 }
3611
3612 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
3613 Register obj = op->obj()->as_register();
3614 Register tmp = op->tmp()->as_pointer_register();
3615 Register tmp_load_klass = LP64_ONLY(rscratch1) NOT_LP64(noreg);
3616 Address mdo_addr = as_Address(op->mdp()->as_address_ptr());
3617 ciKlass* exact_klass = op->exact_klass();
3618 intptr_t current_klass = op->current_klass();
3619 bool not_null = op->not_null();
3620 bool no_conflict = op->no_conflict();
3621
3622 Label update, next, none;
3623
3624 bool do_null = !not_null;
3625 bool exact_klass_set = exact_klass != NULL && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
3626 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
3627
3628 assert(do_null || do_update, "why are we here?");
3629 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
3630
3631 __ verify_oop(obj);
3632
3633 if (tmp != obj) {
3634 __ mov(tmp, obj);
3635 }
3636 if (do_null) {
3637 __ testptr(tmp, tmp);
3638 __ jccb(Assembler::notZero, update);
3639 if (!TypeEntries::was_null_seen(current_klass)) {
3640 __ orptr(mdo_addr, TypeEntries::null_seen);
3641 }
3642 if (do_update) {
3643 #ifndef ASSERT
3644 __ jmpb(next);
3645 }
3646 #else
3647 __ jmp(next);
3648 }
3649 } else {
3650 __ testptr(tmp, tmp);
3651 __ jcc(Assembler::notZero, update);
3652 __ stop("unexpected null obj");
3653 #endif
3654 }
3655
3656 __ bind(update);
3657
3658 if (do_update) {
3659 #ifdef ASSERT
3660 if (exact_klass != NULL) {
3661 Label ok;
3662 __ load_klass(tmp, tmp, tmp_load_klass);
3663 __ push(tmp);
3664 __ mov_metadata(tmp, exact_klass->constant_encoding());
3665 __ cmpptr(tmp, Address(rsp, 0));
3666 __ jcc(Assembler::equal, ok);
3667 __ stop("exact klass and actual klass differ");
3668 __ bind(ok);
3669 __ pop(tmp);
3670 }
3671 #endif
3672 if (!no_conflict) {
3673 if (exact_klass == NULL || TypeEntries::is_type_none(current_klass)) {
3674 if (exact_klass != NULL) {
3675 __ mov_metadata(tmp, exact_klass->constant_encoding());
3676 } else {
3677 __ load_klass(tmp, tmp, tmp_load_klass);
3678 }
3679
3680 __ xorptr(tmp, mdo_addr);
3681 __ testptr(tmp, TypeEntries::type_klass_mask);
3682 // klass seen before, nothing to do. The unknown bit may have been
3683 // set already but no need to check.
3684 __ jccb(Assembler::zero, next);
3685
3686 __ testptr(tmp, TypeEntries::type_unknown);
3687 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3688
3689 if (TypeEntries::is_type_none(current_klass)) {
3690 __ cmpptr(mdo_addr, 0);
3691 __ jccb(Assembler::equal, none);
3692 __ cmpptr(mdo_addr, TypeEntries::null_seen);
3693 __ jccb(Assembler::equal, none);
3694 // There is a chance that the checks above (re-reading profiling
3695 // data from memory) fail if another thread has just set the
3696 // profiling to this obj's klass
3697 __ xorptr(tmp, mdo_addr);
3698 __ testptr(tmp, TypeEntries::type_klass_mask);
3699 __ jccb(Assembler::zero, next);
3700 }
3701 } else {
3702 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
3703 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
3704
3705 __ movptr(tmp, mdo_addr);
3706 __ testptr(tmp, TypeEntries::type_unknown);
3707 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3708 }
3709
3710 // different than before. Cannot keep accurate profile.
3711 __ orptr(mdo_addr, TypeEntries::type_unknown);
3712
3713 if (TypeEntries::is_type_none(current_klass)) {
3714 __ jmpb(next);
3715
3716 __ bind(none);
3717 // first time here. Set profile type.
3718 __ movptr(mdo_addr, tmp);
3719 }
3720 } else {
3721 // There's a single possible klass at this profile point
3722 assert(exact_klass != NULL, "should be");
3723 if (TypeEntries::is_type_none(current_klass)) {
3724 __ mov_metadata(tmp, exact_klass->constant_encoding());
3725 __ xorptr(tmp, mdo_addr);
3726 __ testptr(tmp, TypeEntries::type_klass_mask);
3727 #ifdef ASSERT
3728 __ jcc(Assembler::zero, next);
3729
3730 {
3731 Label ok;
3732 __ push(tmp);
3733 __ cmpptr(mdo_addr, 0);
3734 __ jcc(Assembler::equal, ok);
3735 __ cmpptr(mdo_addr, TypeEntries::null_seen);
3736 __ jcc(Assembler::equal, ok);
3737 // may have been set by another thread
3738 __ mov_metadata(tmp, exact_klass->constant_encoding());
3739 __ xorptr(tmp, mdo_addr);
3740 __ testptr(tmp, TypeEntries::type_mask);
3741 __ jcc(Assembler::zero, ok);
3742
3743 __ stop("unexpected profiling mismatch");
3744 __ bind(ok);
3745 __ pop(tmp);
3746 }
3747 #else
3748 __ jccb(Assembler::zero, next);
3749 #endif
3750 // first time here. Set profile type.
3751 __ movptr(mdo_addr, tmp);
3752 } else {
3753 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
3754 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
3755
3756 __ movptr(tmp, mdo_addr);
3757 __ testptr(tmp, TypeEntries::type_unknown);
3758 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3759
3760 __ orptr(mdo_addr, TypeEntries::type_unknown);
3761 }
3762 }
3763
3764 __ bind(next);
3765 }
3766 }
3767
3768 void LIR_Assembler::emit_delay(LIR_OpDelay*) {
3769 Unimplemented();
3770 }
3771
3772
3773 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) {
3774 __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no));
3775 }
3776
3777
3778 void LIR_Assembler::align_backward_branch_target() {
3779 __ align(BytesPerWord);
3780 }
3781
3782
3783 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) {
3784 if (left->is_single_cpu()) {
3785 __ negl(left->as_register());
3786 move_regs(left->as_register(), dest->as_register());
3787
3788 } else if (left->is_double_cpu()) {
3789 Register lo = left->as_register_lo();
3790 #ifdef _LP64
3791 Register dst = dest->as_register_lo();
3792 __ movptr(dst, lo);
3793 __ negptr(dst);
3794 #else
3795 Register hi = left->as_register_hi();
3796 __ lneg(hi, lo);
3797 if (dest->as_register_lo() == hi) {
3798 assert(dest->as_register_hi() != lo, "destroying register");
3799 move_regs(hi, dest->as_register_hi());
3800 move_regs(lo, dest->as_register_lo());
3801 } else {
3802 move_regs(lo, dest->as_register_lo());
3803 move_regs(hi, dest->as_register_hi());
3804 }
3805 #endif // _LP64
3806
3807 } else if (dest->is_single_xmm()) {
3808 #ifdef _LP64
3809 if (UseAVX > 2 && !VM_Version::supports_avx512vl()) {
3810 assert(tmp->is_valid(), "need temporary");
3811 assert_different_registers(left->as_xmm_float_reg(), tmp->as_xmm_float_reg());
3812 __ vpxor(dest->as_xmm_float_reg(), tmp->as_xmm_float_reg(), left->as_xmm_float_reg(), 2);
3813 }
3814 else
3815 #endif
3816 {
3817 assert(!tmp->is_valid(), "do not need temporary");
3818 if (left->as_xmm_float_reg() != dest->as_xmm_float_reg()) {
3819 __ movflt(dest->as_xmm_float_reg(), left->as_xmm_float_reg());
3820 }
3821 __ xorps(dest->as_xmm_float_reg(),
3822 ExternalAddress((address)float_signflip_pool),
3823 rscratch1);
3824 }
3825 } else if (dest->is_double_xmm()) {
3826 #ifdef _LP64
3827 if (UseAVX > 2 && !VM_Version::supports_avx512vl()) {
3828 assert(tmp->is_valid(), "need temporary");
3829 assert_different_registers(left->as_xmm_double_reg(), tmp->as_xmm_double_reg());
3830 __ vpxor(dest->as_xmm_double_reg(), tmp->as_xmm_double_reg(), left->as_xmm_double_reg(), 2);
3831 }
3832 else
3833 #endif
3834 {
3835 assert(!tmp->is_valid(), "do not need temporary");
3836 if (left->as_xmm_double_reg() != dest->as_xmm_double_reg()) {
3837 __ movdbl(dest->as_xmm_double_reg(), left->as_xmm_double_reg());
3838 }
3839 __ xorpd(dest->as_xmm_double_reg(),
3840 ExternalAddress((address)double_signflip_pool),
3841 rscratch1);
3842 }
3843 #ifndef _LP64
3844 } else if (left->is_single_fpu() || left->is_double_fpu()) {
3845 assert(left->fpu() == 0, "arg must be on TOS");
3846 assert(dest->fpu() == 0, "dest must be TOS");
3847 __ fchs();
3848 #endif // !_LP64
3849
3850 } else {
3851 ShouldNotReachHere();
3852 }
3853 }
3854
3855
3856 void LIR_Assembler::leal(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
3857 assert(src->is_address(), "must be an address");
3858 assert(dest->is_register(), "must be a register");
3859
3860 PatchingStub* patch = NULL;
3861 if (patch_code != lir_patch_none) {
3862 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
3863 }
3864
3865 Register reg = dest->as_pointer_register();
3866 LIR_Address* addr = src->as_address_ptr();
3867 __ lea(reg, as_Address(addr));
3868
3869 if (patch != NULL) {
3870 patching_epilog(patch, patch_code, addr->base()->as_register(), info);
3871 }
3872 }
3873
3874
3875
3876 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
3877 assert(!tmp->is_valid(), "don't need temporary");
3878 __ call(RuntimeAddress(dest));
3879 if (info != NULL) {
3880 add_call_info_here(info);
3881 }
3882 __ post_call_nop();
3883 }
3884
3885
3886 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
3887 assert(type == T_LONG, "only for volatile long fields");
3888
3889 if (info != NULL) {
3890 add_debug_info_for_null_check_here(info);
3891 }
3892
3893 if (src->is_double_xmm()) {
3894 if (dest->is_double_cpu()) {
3895 #ifdef _LP64
3896 __ movdq(dest->as_register_lo(), src->as_xmm_double_reg());
3897 #else
3898 __ movdl(dest->as_register_lo(), src->as_xmm_double_reg());
3899 __ psrlq(src->as_xmm_double_reg(), 32);
3900 __ movdl(dest->as_register_hi(), src->as_xmm_double_reg());
3901 #endif // _LP64
3902 } else if (dest->is_double_stack()) {
3903 __ movdbl(frame_map()->address_for_slot(dest->double_stack_ix()), src->as_xmm_double_reg());
3904 } else if (dest->is_address()) {
3905 __ movdbl(as_Address(dest->as_address_ptr()), src->as_xmm_double_reg());
3906 } else {
3907 ShouldNotReachHere();
3908 }
3909
3910 } else if (dest->is_double_xmm()) {
3911 if (src->is_double_stack()) {
3912 __ movdbl(dest->as_xmm_double_reg(), frame_map()->address_for_slot(src->double_stack_ix()));
3913 } else if (src->is_address()) {
3914 __ movdbl(dest->as_xmm_double_reg(), as_Address(src->as_address_ptr()));
3915 } else {
3916 ShouldNotReachHere();
3917 }
3918
3919 #ifndef _LP64
3920 } else if (src->is_double_fpu()) {
3921 assert(src->fpu_regnrLo() == 0, "must be TOS");
3922 if (dest->is_double_stack()) {
3923 __ fistp_d(frame_map()->address_for_slot(dest->double_stack_ix()));
3924 } else if (dest->is_address()) {
3925 __ fistp_d(as_Address(dest->as_address_ptr()));
3926 } else {
3927 ShouldNotReachHere();
3928 }
3929
3930 } else if (dest->is_double_fpu()) {
3931 assert(dest->fpu_regnrLo() == 0, "must be TOS");
3932 if (src->is_double_stack()) {
3933 __ fild_d(frame_map()->address_for_slot(src->double_stack_ix()));
3934 } else if (src->is_address()) {
3935 __ fild_d(as_Address(src->as_address_ptr()));
3936 } else {
3937 ShouldNotReachHere();
3938 }
3939 #endif // !_LP64
3940
3941 } else {
3942 ShouldNotReachHere();
3943 }
3944 }
3945
3946 #ifdef ASSERT
3947 // emit run-time assertion
3948 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
3949 assert(op->code() == lir_assert, "must be");
3950
3951 if (op->in_opr1()->is_valid()) {
3952 assert(op->in_opr2()->is_valid(), "both operands must be valid");
3953 comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
3954 } else {
3955 assert(op->in_opr2()->is_illegal(), "both operands must be illegal");
3956 assert(op->condition() == lir_cond_always, "no other conditions allowed");
3957 }
3958
3959 Label ok;
3960 if (op->condition() != lir_cond_always) {
3961 Assembler::Condition acond = Assembler::zero;
3962 switch (op->condition()) {
3963 case lir_cond_equal: acond = Assembler::equal; break;
3964 case lir_cond_notEqual: acond = Assembler::notEqual; break;
3965 case lir_cond_less: acond = Assembler::less; break;
3966 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
3967 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break;
3968 case lir_cond_greater: acond = Assembler::greater; break;
3969 case lir_cond_belowEqual: acond = Assembler::belowEqual; break;
3970 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break;
3971 default: ShouldNotReachHere();
3972 }
3973 __ jcc(acond, ok);
3974 }
3975 if (op->halt()) {
3976 const char* str = __ code_string(op->msg());
3977 __ stop(str);
3978 } else {
3979 breakpoint();
3980 }
3981 __ bind(ok);
3982 }
3983 #endif
3984
3985 void LIR_Assembler::membar() {
3986 // QQQ sparc TSO uses this,
3987 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad));
3988 }
3989
3990 void LIR_Assembler::membar_acquire() {
3991 // No x86 machines currently require load fences
3992 }
3993
3994 void LIR_Assembler::membar_release() {
3995 // No x86 machines currently require store fences
3996 }
3997
3998 void LIR_Assembler::membar_loadload() {
3999 // no-op
4000 //__ membar(Assembler::Membar_mask_bits(Assembler::loadload));
4001 }
4002
4003 void LIR_Assembler::membar_storestore() {
4004 // no-op
4005 //__ membar(Assembler::Membar_mask_bits(Assembler::storestore));
4006 }
4007
4008 void LIR_Assembler::membar_loadstore() {
4009 // no-op
4010 //__ membar(Assembler::Membar_mask_bits(Assembler::loadstore));
4011 }
4012
4013 void LIR_Assembler::membar_storeload() {
4014 __ membar(Assembler::Membar_mask_bits(Assembler::StoreLoad));
4015 }
4016
4017 void LIR_Assembler::on_spin_wait() {
4018 __ pause ();
4019 }
4020
4021 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
4022 assert(result_reg->is_register(), "check");
4023 #ifdef _LP64
4024 // __ get_thread(result_reg->as_register_lo());
4025 __ mov(result_reg->as_register(), r15_thread);
4026 #else
4027 __ get_thread(result_reg->as_register());
4028 #endif // _LP64
4029 }
4030
4031
4032 void LIR_Assembler::peephole(LIR_List*) {
4033 // do nothing for now
4034 }
4035
4036 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) {
4037 assert(data == dest, "xchg/xadd uses only 2 operands");
4038
4039 if (data->type() == T_INT) {
4040 if (code == lir_xadd) {
4041 __ lock();
4042 __ xaddl(as_Address(src->as_address_ptr()), data->as_register());
4043 } else {
4044 __ xchgl(data->as_register(), as_Address(src->as_address_ptr()));
4045 }
4046 } else if (data->is_oop()) {
4047 assert (code == lir_xchg, "xadd for oops");
4048 Register obj = data->as_register();
4049 #ifdef _LP64
4050 if (UseCompressedOops) {
4051 __ encode_heap_oop(obj);
4052 __ xchgl(obj, as_Address(src->as_address_ptr()));
4053 __ decode_heap_oop(obj);
4054 } else {
4055 __ xchgptr(obj, as_Address(src->as_address_ptr()));
4056 }
4057 #else
4058 __ xchgl(obj, as_Address(src->as_address_ptr()));
4059 #endif
4060 } else if (data->type() == T_LONG) {
4061 #ifdef _LP64
4062 assert(data->as_register_lo() == data->as_register_hi(), "should be a single register");
4063 if (code == lir_xadd) {
4064 __ lock();
4065 __ xaddq(as_Address(src->as_address_ptr()), data->as_register_lo());
4066 } else {
4067 __ xchgq(data->as_register_lo(), as_Address(src->as_address_ptr()));
4068 }
4069 #else
4070 ShouldNotReachHere();
4071 #endif
4072 } else {
4073 ShouldNotReachHere();
4074 }
4075 }
4076
4077 #undef __