1 /*
2 * Copyright (c) 2000, 2022, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/macroAssembler.hpp"
27 #include "asm/macroAssembler.inline.hpp"
28 #include "c1/c1_CodeStubs.hpp"
29 #include "c1/c1_Compilation.hpp"
30 #include "c1/c1_LIRAssembler.hpp"
31 #include "c1/c1_MacroAssembler.hpp"
32 #include "c1/c1_Runtime1.hpp"
33 #include "c1/c1_ValueStack.hpp"
34 #include "ci/ciArrayKlass.hpp"
35 #include "ci/ciInstance.hpp"
36 #include "compiler/oopMap.hpp"
37 #include "gc/shared/collectedHeap.hpp"
38 #include "gc/shared/gc_globals.hpp"
39 #include "nativeInst_x86.hpp"
40 #include "oops/objArrayKlass.hpp"
41 #include "runtime/frame.inline.hpp"
42 #include "runtime/safepointMechanism.hpp"
43 #include "runtime/sharedRuntime.hpp"
44 #include "runtime/stubRoutines.hpp"
45 #include "utilities/powerOfTwo.hpp"
46 #include "vmreg_x86.inline.hpp"
47
48
49 // These masks are used to provide 128-bit aligned bitmasks to the XMM
50 // instructions, to allow sign-masking or sign-bit flipping. They allow
51 // fast versions of NegF/NegD and AbsF/AbsD.
52
53 // Note: 'double' and 'long long' have 32-bits alignment on x86.
54 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) {
55 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address
56 // of 128-bits operands for SSE instructions.
57 jlong *operand = (jlong*)(((intptr_t)adr) & ((intptr_t)(~0xF)));
58 // Store the value to a 128-bits operand.
59 operand[0] = lo;
60 operand[1] = hi;
61 return operand;
62 }
63
64 // Buffer for 128-bits masks used by SSE instructions.
65 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment)
66
67 // Static initialization during VM startup.
68 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF));
69 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF));
70 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], (jlong)UCONST64(0x8000000080000000), (jlong)UCONST64(0x8000000080000000));
71 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], (jlong)UCONST64(0x8000000000000000), (jlong)UCONST64(0x8000000000000000));
72
73
74 NEEDS_CLEANUP // remove this definitions ?
75 const Register IC_Klass = rax; // where the IC klass is cached
76 const Register SYNC_header = rax; // synchronization header
77 const Register SHIFT_count = rcx; // where count for shift operations must be
78
79 #define __ _masm->
80
81
82 static void select_different_registers(Register preserve,
83 Register extra,
84 Register &tmp1,
85 Register &tmp2) {
86 if (tmp1 == preserve) {
87 assert_different_registers(tmp1, tmp2, extra);
88 tmp1 = extra;
89 } else if (tmp2 == preserve) {
90 assert_different_registers(tmp1, tmp2, extra);
91 tmp2 = extra;
92 }
93 assert_different_registers(preserve, tmp1, tmp2);
94 }
95
96
97
98 static void select_different_registers(Register preserve,
99 Register extra,
100 Register &tmp1,
101 Register &tmp2,
102 Register &tmp3) {
103 if (tmp1 == preserve) {
104 assert_different_registers(tmp1, tmp2, tmp3, extra);
105 tmp1 = extra;
106 } else if (tmp2 == preserve) {
107 assert_different_registers(tmp1, tmp2, tmp3, extra);
108 tmp2 = extra;
109 } else if (tmp3 == preserve) {
110 assert_different_registers(tmp1, tmp2, tmp3, extra);
111 tmp3 = extra;
112 }
113 assert_different_registers(preserve, tmp1, tmp2, tmp3);
114 }
115
116
117
118 bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
119 if (opr->is_constant()) {
120 LIR_Const* constant = opr->as_constant_ptr();
121 switch (constant->type()) {
122 case T_INT: {
123 return true;
124 }
125
126 default:
127 return false;
128 }
129 }
130 return false;
131 }
132
133
134 LIR_Opr LIR_Assembler::receiverOpr() {
135 return FrameMap::receiver_opr;
136 }
137
138 LIR_Opr LIR_Assembler::osrBufferPointer() {
139 return FrameMap::as_pointer_opr(receiverOpr()->as_register());
140 }
141
142 //--------------fpu register translations-----------------------
143
144
145 address LIR_Assembler::float_constant(float f) {
146 address const_addr = __ float_constant(f);
147 if (const_addr == NULL) {
148 bailout("const section overflow");
149 return __ code()->consts()->start();
150 } else {
151 return const_addr;
152 }
153 }
154
155
156 address LIR_Assembler::double_constant(double d) {
157 address const_addr = __ double_constant(d);
158 if (const_addr == NULL) {
159 bailout("const section overflow");
160 return __ code()->consts()->start();
161 } else {
162 return const_addr;
163 }
164 }
165
166 #ifndef _LP64
167 void LIR_Assembler::fpop() {
168 __ fpop();
169 }
170
171 void LIR_Assembler::fxch(int i) {
172 __ fxch(i);
173 }
174
175 void LIR_Assembler::fld(int i) {
176 __ fld_s(i);
177 }
178
179 void LIR_Assembler::ffree(int i) {
180 __ ffree(i);
181 }
182 #endif // !_LP64
183
184 void LIR_Assembler::breakpoint() {
185 __ int3();
186 }
187
188 void LIR_Assembler::push(LIR_Opr opr) {
189 if (opr->is_single_cpu()) {
190 __ push_reg(opr->as_register());
191 } else if (opr->is_double_cpu()) {
192 NOT_LP64(__ push_reg(opr->as_register_hi()));
193 __ push_reg(opr->as_register_lo());
194 } else if (opr->is_stack()) {
195 __ push_addr(frame_map()->address_for_slot(opr->single_stack_ix()));
196 } else if (opr->is_constant()) {
197 LIR_Const* const_opr = opr->as_constant_ptr();
198 if (const_opr->type() == T_OBJECT) {
199 __ push_oop(const_opr->as_jobject());
200 } else if (const_opr->type() == T_INT) {
201 __ push_jint(const_opr->as_jint());
202 } else {
203 ShouldNotReachHere();
204 }
205
206 } else {
207 ShouldNotReachHere();
208 }
209 }
210
211 void LIR_Assembler::pop(LIR_Opr opr) {
212 if (opr->is_single_cpu()) {
213 __ pop_reg(opr->as_register());
214 } else {
215 ShouldNotReachHere();
216 }
217 }
218
219 bool LIR_Assembler::is_literal_address(LIR_Address* addr) {
220 return addr->base()->is_illegal() && addr->index()->is_illegal();
221 }
222
223 //-------------------------------------------
224
225 Address LIR_Assembler::as_Address(LIR_Address* addr) {
226 return as_Address(addr, rscratch1);
227 }
228
229 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) {
230 if (addr->base()->is_illegal()) {
231 assert(addr->index()->is_illegal(), "must be illegal too");
232 AddressLiteral laddr((address)addr->disp(), relocInfo::none);
233 if (! __ reachable(laddr)) {
234 __ movptr(tmp, laddr.addr());
235 Address res(tmp, 0);
236 return res;
237 } else {
238 return __ as_Address(laddr);
239 }
240 }
241
242 Register base = addr->base()->as_pointer_register();
243
244 if (addr->index()->is_illegal()) {
245 return Address( base, addr->disp());
246 } else if (addr->index()->is_cpu_register()) {
247 Register index = addr->index()->as_pointer_register();
248 return Address(base, index, (Address::ScaleFactor) addr->scale(), addr->disp());
249 } else if (addr->index()->is_constant()) {
250 intptr_t addr_offset = (addr->index()->as_constant_ptr()->as_jint() << addr->scale()) + addr->disp();
251 assert(Assembler::is_simm32(addr_offset), "must be");
252
253 return Address(base, addr_offset);
254 } else {
255 Unimplemented();
256 return Address();
257 }
258 }
259
260
261 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
262 Address base = as_Address(addr);
263 return Address(base._base, base._index, base._scale, base._disp + BytesPerWord);
264 }
265
266
267 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
268 return as_Address(addr);
269 }
270
271
272 void LIR_Assembler::osr_entry() {
273 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
274 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
275 ValueStack* entry_state = osr_entry->state();
276 int number_of_locks = entry_state->locks_size();
277
278 // we jump here if osr happens with the interpreter
279 // state set up to continue at the beginning of the
280 // loop that triggered osr - in particular, we have
281 // the following registers setup:
282 //
283 // rcx: osr buffer
284 //
285
286 // build frame
287 ciMethod* m = compilation()->method();
288 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
289
290 // OSR buffer is
291 //
292 // locals[nlocals-1..0]
293 // monitors[0..number_of_locks]
294 //
295 // locals is a direct copy of the interpreter frame so in the osr buffer
296 // so first slot in the local array is the last local from the interpreter
297 // and last slot is local[0] (receiver) from the interpreter
298 //
299 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
300 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
301 // in the interpreter frame (the method lock if a sync method)
302
303 // Initialize monitors in the compiled activation.
304 // rcx: pointer to osr buffer
305 //
306 // All other registers are dead at this point and the locals will be
307 // copied into place by code emitted in the IR.
308
309 Register OSR_buf = osrBufferPointer()->as_pointer_register();
310 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
311 int monitor_offset = BytesPerWord * method()->max_locals() +
312 (BasicObjectLock::size() * BytesPerWord) * (number_of_locks - 1);
313 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
314 // the OSR buffer using 2 word entries: first the lock and then
315 // the oop.
316 for (int i = 0; i < number_of_locks; i++) {
317 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
318 #ifdef ASSERT
319 // verify the interpreter's monitor has a non-null object
320 {
321 Label L;
322 __ cmpptr(Address(OSR_buf, slot_offset + 1*BytesPerWord), (int32_t)NULL_WORD);
323 __ jcc(Assembler::notZero, L);
324 __ stop("locked object is NULL");
325 __ bind(L);
326 }
327 #endif
328 __ movptr(rbx, Address(OSR_buf, slot_offset + 0));
329 __ movptr(frame_map()->address_for_monitor_lock(i), rbx);
330 __ movptr(rbx, Address(OSR_buf, slot_offset + 1*BytesPerWord));
331 __ movptr(frame_map()->address_for_monitor_object(i), rbx);
332 }
333 }
334 }
335
336
337 // inline cache check; done before the frame is built.
338 int LIR_Assembler::check_icache() {
339 Register receiver = FrameMap::receiver_opr->as_register();
340 Register ic_klass = IC_Klass;
341 const int ic_cmp_size = LP64_ONLY(10) NOT_LP64(9);
342 const bool do_post_padding = VerifyOops || UseCompressedClassPointers;
343 if (!do_post_padding) {
344 // insert some nops so that the verified entry point is aligned on CodeEntryAlignment
345 __ align(CodeEntryAlignment, __ offset() + ic_cmp_size);
346 }
347 int offset = __ offset();
348 __ inline_cache_check(receiver, IC_Klass);
349 assert(__ offset() % CodeEntryAlignment == 0 || do_post_padding, "alignment must be correct");
350 if (do_post_padding) {
351 // force alignment after the cache check.
352 // It's been verified to be aligned if !VerifyOops
353 __ align(CodeEntryAlignment);
354 }
355 return offset;
356 }
357
358 void LIR_Assembler::clinit_barrier(ciMethod* method) {
359 assert(VM_Version::supports_fast_class_init_checks(), "sanity");
360 assert(!method->holder()->is_not_initialized(), "initialization should have been started");
361
362 Label L_skip_barrier;
363 Register klass = rscratch1;
364 Register thread = LP64_ONLY( r15_thread ) NOT_LP64( noreg );
365 assert(thread != noreg, "x86_32 not implemented");
366
367 __ mov_metadata(klass, method->holder()->constant_encoding());
368 __ clinit_barrier(klass, thread, &L_skip_barrier /*L_fast_path*/);
369
370 __ jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub()));
371
372 __ bind(L_skip_barrier);
373 }
374
375 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo* info) {
376 jobject o = NULL;
377 PatchingStub* patch = new PatchingStub(_masm, patching_id(info));
378 __ movoop(reg, o);
379 patching_epilog(patch, lir_patch_normal, reg, info);
380 }
381
382 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) {
383 Metadata* o = NULL;
384 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id);
385 __ mov_metadata(reg, o);
386 patching_epilog(patch, lir_patch_normal, reg, info);
387 }
388
389 // This specifies the rsp decrement needed to build the frame
390 int LIR_Assembler::initial_frame_size_in_bytes() const {
391 // if rounding, must let FrameMap know!
392
393 // The frame_map records size in slots (32bit word)
394
395 // subtract two words to account for return address and link
396 return (frame_map()->framesize() - (2*VMRegImpl::slots_per_word)) * VMRegImpl::stack_slot_size;
397 }
398
399
400 int LIR_Assembler::emit_exception_handler() {
401 // generate code for exception handler
402 address handler_base = __ start_a_stub(exception_handler_size());
403 if (handler_base == NULL) {
404 // not enough space left for the handler
405 bailout("exception handler overflow");
406 return -1;
407 }
408
409 int offset = code_offset();
410
411 // the exception oop and pc are in rax, and rdx
412 // no other registers need to be preserved, so invalidate them
413 __ invalidate_registers(false, true, true, false, true, true);
414
415 // check that there is really an exception
416 __ verify_not_null_oop(rax);
417
418 // search an exception handler (rax: exception oop, rdx: throwing pc)
419 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::handle_exception_from_callee_id)));
420 __ should_not_reach_here();
421 guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
422 __ end_a_stub();
423
424 return offset;
425 }
426
427
428 // Emit the code to remove the frame from the stack in the exception
429 // unwind path.
430 int LIR_Assembler::emit_unwind_handler() {
431 #ifndef PRODUCT
432 if (CommentedAssembly) {
433 _masm->block_comment("Unwind handler");
434 }
435 #endif
436
437 int offset = code_offset();
438
439 // Fetch the exception from TLS and clear out exception related thread state
440 Register thread = NOT_LP64(rsi) LP64_ONLY(r15_thread);
441 NOT_LP64(__ get_thread(thread));
442 __ movptr(rax, Address(thread, JavaThread::exception_oop_offset()));
443 __ movptr(Address(thread, JavaThread::exception_oop_offset()), (intptr_t)NULL_WORD);
444 __ movptr(Address(thread, JavaThread::exception_pc_offset()), (intptr_t)NULL_WORD);
445
446 __ bind(_unwind_handler_entry);
447 __ verify_not_null_oop(rax);
448 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
449 __ mov(rbx, rax); // Preserve the exception (rbx is always callee-saved)
450 }
451
452 // Perform needed unlocking
453 MonitorExitStub* stub = NULL;
454 if (method()->is_synchronized()) {
455 monitor_address(0, FrameMap::rax_opr);
456 stub = new MonitorExitStub(FrameMap::rax_opr, true, 0);
457 if (UseHeavyMonitors) {
458 __ jmp(*stub->entry());
459 } else {
460 __ unlock_object(rdi, rsi, rax, *stub->entry());
461 }
462 __ bind(*stub->continuation());
463 }
464
465 if (compilation()->env()->dtrace_method_probes()) {
466 #ifdef _LP64
467 __ mov(rdi, r15_thread);
468 __ mov_metadata(rsi, method()->constant_encoding());
469 #else
470 __ get_thread(rax);
471 __ movptr(Address(rsp, 0), rax);
472 __ mov_metadata(Address(rsp, sizeof(void*)), method()->constant_encoding());
473 #endif
474 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit)));
475 }
476
477 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
478 __ mov(rax, rbx); // Restore the exception
479 }
480
481 // remove the activation and dispatch to the unwind handler
482 __ remove_frame(initial_frame_size_in_bytes());
483 __ jump(RuntimeAddress(Runtime1::entry_for(Runtime1::unwind_exception_id)));
484
485 // Emit the slow path assembly
486 if (stub != NULL) {
487 stub->emit_code(this);
488 }
489
490 return offset;
491 }
492
493
494 int LIR_Assembler::emit_deopt_handler() {
495 // generate code for exception handler
496 address handler_base = __ start_a_stub(deopt_handler_size());
497 if (handler_base == NULL) {
498 // not enough space left for the handler
499 bailout("deopt handler overflow");
500 return -1;
501 }
502
503 int offset = code_offset();
504 InternalAddress here(__ pc());
505
506 __ pushptr(here.addr());
507 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
508 guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
509 __ end_a_stub();
510
511 return offset;
512 }
513
514 void LIR_Assembler::return_op(LIR_Opr result, C1SafepointPollStub* code_stub) {
515 assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == rax, "word returns are in rax,");
516 if (!result->is_illegal() && result->is_float_kind() && !result->is_xmm_register()) {
517 assert(result->fpu() == 0, "result must already be on TOS");
518 }
519
520 // Pop the stack before the safepoint code
521 __ remove_frame(initial_frame_size_in_bytes());
522
523 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
524 __ reserved_stack_check();
525 }
526
527 // Note: we do not need to round double result; float result has the right precision
528 // the poll sets the condition code, but no data registers
529
530 #ifdef _LP64
531 const Register thread = r15_thread;
532 #else
533 const Register thread = rbx;
534 __ get_thread(thread);
535 #endif
536 code_stub->set_safepoint_offset(__ offset());
537 __ relocate(relocInfo::poll_return_type);
538 __ safepoint_poll(*code_stub->entry(), thread, true /* at_return */, true /* in_nmethod */);
539 __ ret(0);
540 }
541
542
543 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
544 guarantee(info != NULL, "Shouldn't be NULL");
545 int offset = __ offset();
546 #ifdef _LP64
547 const Register poll_addr = rscratch1;
548 __ movptr(poll_addr, Address(r15_thread, JavaThread::polling_page_offset()));
549 #else
550 assert(tmp->is_cpu_register(), "needed");
551 const Register poll_addr = tmp->as_register();
552 __ get_thread(poll_addr);
553 __ movptr(poll_addr, Address(poll_addr, in_bytes(JavaThread::polling_page_offset())));
554 #endif
555 add_debug_info_for_branch(info);
556 __ relocate(relocInfo::poll_type);
557 address pre_pc = __ pc();
558 __ testl(rax, Address(poll_addr, 0));
559 address post_pc = __ pc();
560 guarantee(pointer_delta(post_pc, pre_pc, 1) == 2 LP64_ONLY(+1), "must be exact length");
561 return offset;
562 }
563
564
565 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
566 if (from_reg != to_reg) __ mov(to_reg, from_reg);
567 }
568
569 void LIR_Assembler::swap_reg(Register a, Register b) {
570 __ xchgptr(a, b);
571 }
572
573
574 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
575 assert(src->is_constant(), "should not call otherwise");
576 assert(dest->is_register(), "should not call otherwise");
577 LIR_Const* c = src->as_constant_ptr();
578
579 switch (c->type()) {
580 case T_INT: {
581 assert(patch_code == lir_patch_none, "no patching handled here");
582 __ movl(dest->as_register(), c->as_jint());
583 break;
584 }
585
586 case T_ADDRESS: {
587 assert(patch_code == lir_patch_none, "no patching handled here");
588 __ movptr(dest->as_register(), c->as_jint());
589 break;
590 }
591
592 case T_LONG: {
593 assert(patch_code == lir_patch_none, "no patching handled here");
594 #ifdef _LP64
595 __ movptr(dest->as_register_lo(), (intptr_t)c->as_jlong());
596 #else
597 __ movptr(dest->as_register_lo(), c->as_jint_lo());
598 __ movptr(dest->as_register_hi(), c->as_jint_hi());
599 #endif // _LP64
600 break;
601 }
602
603 case T_OBJECT: {
604 if (patch_code != lir_patch_none) {
605 jobject2reg_with_patching(dest->as_register(), info);
606 } else {
607 __ movoop(dest->as_register(), c->as_jobject());
608 }
609 break;
610 }
611
612 case T_METADATA: {
613 if (patch_code != lir_patch_none) {
614 klass2reg_with_patching(dest->as_register(), info);
615 } else {
616 __ mov_metadata(dest->as_register(), c->as_metadata());
617 }
618 break;
619 }
620
621 case T_FLOAT: {
622 if (dest->is_single_xmm()) {
623 if (LP64_ONLY(UseAVX <= 2 &&) c->is_zero_float()) {
624 __ xorps(dest->as_xmm_float_reg(), dest->as_xmm_float_reg());
625 } else {
626 __ movflt(dest->as_xmm_float_reg(),
627 InternalAddress(float_constant(c->as_jfloat())));
628 }
629 } else {
630 #ifndef _LP64
631 assert(dest->is_single_fpu(), "must be");
632 assert(dest->fpu_regnr() == 0, "dest must be TOS");
633 if (c->is_zero_float()) {
634 __ fldz();
635 } else if (c->is_one_float()) {
636 __ fld1();
637 } else {
638 __ fld_s (InternalAddress(float_constant(c->as_jfloat())));
639 }
640 #else
641 ShouldNotReachHere();
642 #endif // !_LP64
643 }
644 break;
645 }
646
647 case T_DOUBLE: {
648 if (dest->is_double_xmm()) {
649 if (LP64_ONLY(UseAVX <= 2 &&) c->is_zero_double()) {
650 __ xorpd(dest->as_xmm_double_reg(), dest->as_xmm_double_reg());
651 } else {
652 __ movdbl(dest->as_xmm_double_reg(),
653 InternalAddress(double_constant(c->as_jdouble())));
654 }
655 } else {
656 #ifndef _LP64
657 assert(dest->is_double_fpu(), "must be");
658 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
659 if (c->is_zero_double()) {
660 __ fldz();
661 } else if (c->is_one_double()) {
662 __ fld1();
663 } else {
664 __ fld_d (InternalAddress(double_constant(c->as_jdouble())));
665 }
666 #else
667 ShouldNotReachHere();
668 #endif // !_LP64
669 }
670 break;
671 }
672
673 default:
674 ShouldNotReachHere();
675 }
676 }
677
678 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
679 assert(src->is_constant(), "should not call otherwise");
680 assert(dest->is_stack(), "should not call otherwise");
681 LIR_Const* c = src->as_constant_ptr();
682
683 switch (c->type()) {
684 case T_INT: // fall through
685 case T_FLOAT:
686 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits());
687 break;
688
689 case T_ADDRESS:
690 __ movptr(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits());
691 break;
692
693 case T_OBJECT:
694 __ movoop(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jobject());
695 break;
696
697 case T_LONG: // fall through
698 case T_DOUBLE:
699 #ifdef _LP64
700 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
701 lo_word_offset_in_bytes), (intptr_t)c->as_jlong_bits());
702 #else
703 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
704 lo_word_offset_in_bytes), c->as_jint_lo_bits());
705 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
706 hi_word_offset_in_bytes), c->as_jint_hi_bits());
707 #endif // _LP64
708 break;
709
710 default:
711 ShouldNotReachHere();
712 }
713 }
714
715 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
716 assert(src->is_constant(), "should not call otherwise");
717 assert(dest->is_address(), "should not call otherwise");
718 LIR_Const* c = src->as_constant_ptr();
719 LIR_Address* addr = dest->as_address_ptr();
720
721 int null_check_here = code_offset();
722 switch (type) {
723 case T_INT: // fall through
724 case T_FLOAT:
725 __ movl(as_Address(addr), c->as_jint_bits());
726 break;
727
728 case T_ADDRESS:
729 __ movptr(as_Address(addr), c->as_jint_bits());
730 break;
731
732 case T_OBJECT: // fall through
733 case T_ARRAY:
734 if (c->as_jobject() == NULL) {
735 if (UseCompressedOops && !wide) {
736 __ movl(as_Address(addr), (int32_t)NULL_WORD);
737 } else {
738 #ifdef _LP64
739 __ xorptr(rscratch1, rscratch1);
740 null_check_here = code_offset();
741 __ movptr(as_Address(addr), rscratch1);
742 #else
743 __ movptr(as_Address(addr), NULL_WORD);
744 #endif
745 }
746 } else {
747 if (is_literal_address(addr)) {
748 ShouldNotReachHere();
749 __ movoop(as_Address(addr, noreg), c->as_jobject());
750 } else {
751 #ifdef _LP64
752 __ movoop(rscratch1, c->as_jobject());
753 if (UseCompressedOops && !wide) {
754 __ encode_heap_oop(rscratch1);
755 null_check_here = code_offset();
756 __ movl(as_Address_lo(addr), rscratch1);
757 } else {
758 null_check_here = code_offset();
759 __ movptr(as_Address_lo(addr), rscratch1);
760 }
761 #else
762 __ movoop(as_Address(addr), c->as_jobject());
763 #endif
764 }
765 }
766 break;
767
768 case T_LONG: // fall through
769 case T_DOUBLE:
770 #ifdef _LP64
771 if (is_literal_address(addr)) {
772 ShouldNotReachHere();
773 __ movptr(as_Address(addr, r15_thread), (intptr_t)c->as_jlong_bits());
774 } else {
775 __ movptr(r10, (intptr_t)c->as_jlong_bits());
776 null_check_here = code_offset();
777 __ movptr(as_Address_lo(addr), r10);
778 }
779 #else
780 // Always reachable in 32bit so this doesn't produce useless move literal
781 __ movptr(as_Address_hi(addr), c->as_jint_hi_bits());
782 __ movptr(as_Address_lo(addr), c->as_jint_lo_bits());
783 #endif // _LP64
784 break;
785
786 case T_BOOLEAN: // fall through
787 case T_BYTE:
788 __ movb(as_Address(addr), c->as_jint() & 0xFF);
789 break;
790
791 case T_CHAR: // fall through
792 case T_SHORT:
793 __ movw(as_Address(addr), c->as_jint() & 0xFFFF);
794 break;
795
796 default:
797 ShouldNotReachHere();
798 };
799
800 if (info != NULL) {
801 add_debug_info_for_null_check(null_check_here, info);
802 }
803 }
804
805
806 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
807 assert(src->is_register(), "should not call otherwise");
808 assert(dest->is_register(), "should not call otherwise");
809
810 // move between cpu-registers
811 if (dest->is_single_cpu()) {
812 #ifdef _LP64
813 if (src->type() == T_LONG) {
814 // Can do LONG -> OBJECT
815 move_regs(src->as_register_lo(), dest->as_register());
816 return;
817 }
818 #endif
819 assert(src->is_single_cpu(), "must match");
820 if (src->type() == T_OBJECT) {
821 __ verify_oop(src->as_register());
822 }
823 move_regs(src->as_register(), dest->as_register());
824
825 } else if (dest->is_double_cpu()) {
826 #ifdef _LP64
827 if (is_reference_type(src->type())) {
828 // Surprising to me but we can see move of a long to t_object
829 __ verify_oop(src->as_register());
830 move_regs(src->as_register(), dest->as_register_lo());
831 return;
832 }
833 #endif
834 assert(src->is_double_cpu(), "must match");
835 Register f_lo = src->as_register_lo();
836 Register f_hi = src->as_register_hi();
837 Register t_lo = dest->as_register_lo();
838 Register t_hi = dest->as_register_hi();
839 #ifdef _LP64
840 assert(f_hi == f_lo, "must be same");
841 assert(t_hi == t_lo, "must be same");
842 move_regs(f_lo, t_lo);
843 #else
844 assert(f_lo != f_hi && t_lo != t_hi, "invalid register allocation");
845
846
847 if (f_lo == t_hi && f_hi == t_lo) {
848 swap_reg(f_lo, f_hi);
849 } else if (f_hi == t_lo) {
850 assert(f_lo != t_hi, "overwriting register");
851 move_regs(f_hi, t_hi);
852 move_regs(f_lo, t_lo);
853 } else {
854 assert(f_hi != t_lo, "overwriting register");
855 move_regs(f_lo, t_lo);
856 move_regs(f_hi, t_hi);
857 }
858 #endif // LP64
859
860 #ifndef _LP64
861 // special moves from fpu-register to xmm-register
862 // necessary for method results
863 } else if (src->is_single_xmm() && !dest->is_single_xmm()) {
864 __ movflt(Address(rsp, 0), src->as_xmm_float_reg());
865 __ fld_s(Address(rsp, 0));
866 } else if (src->is_double_xmm() && !dest->is_double_xmm()) {
867 __ movdbl(Address(rsp, 0), src->as_xmm_double_reg());
868 __ fld_d(Address(rsp, 0));
869 } else if (dest->is_single_xmm() && !src->is_single_xmm()) {
870 __ fstp_s(Address(rsp, 0));
871 __ movflt(dest->as_xmm_float_reg(), Address(rsp, 0));
872 } else if (dest->is_double_xmm() && !src->is_double_xmm()) {
873 __ fstp_d(Address(rsp, 0));
874 __ movdbl(dest->as_xmm_double_reg(), Address(rsp, 0));
875 #endif // !_LP64
876
877 // move between xmm-registers
878 } else if (dest->is_single_xmm()) {
879 assert(src->is_single_xmm(), "must match");
880 __ movflt(dest->as_xmm_float_reg(), src->as_xmm_float_reg());
881 } else if (dest->is_double_xmm()) {
882 assert(src->is_double_xmm(), "must match");
883 __ movdbl(dest->as_xmm_double_reg(), src->as_xmm_double_reg());
884
885 #ifndef _LP64
886 // move between fpu-registers (no instruction necessary because of fpu-stack)
887 } else if (dest->is_single_fpu() || dest->is_double_fpu()) {
888 assert(src->is_single_fpu() || src->is_double_fpu(), "must match");
889 assert(src->fpu() == dest->fpu(), "currently should be nothing to do");
890 #endif // !_LP64
891
892 } else {
893 ShouldNotReachHere();
894 }
895 }
896
897 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
898 assert(src->is_register(), "should not call otherwise");
899 assert(dest->is_stack(), "should not call otherwise");
900
901 if (src->is_single_cpu()) {
902 Address dst = frame_map()->address_for_slot(dest->single_stack_ix());
903 if (is_reference_type(type)) {
904 __ verify_oop(src->as_register());
905 __ movptr (dst, src->as_register());
906 } else if (type == T_METADATA || type == T_ADDRESS) {
907 __ movptr (dst, src->as_register());
908 } else {
909 __ movl (dst, src->as_register());
910 }
911
912 } else if (src->is_double_cpu()) {
913 Address dstLO = frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes);
914 Address dstHI = frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes);
915 __ movptr (dstLO, src->as_register_lo());
916 NOT_LP64(__ movptr (dstHI, src->as_register_hi()));
917
918 } else if (src->is_single_xmm()) {
919 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
920 __ movflt(dst_addr, src->as_xmm_float_reg());
921
922 } else if (src->is_double_xmm()) {
923 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
924 __ movdbl(dst_addr, src->as_xmm_double_reg());
925
926 #ifndef _LP64
927 } else if (src->is_single_fpu()) {
928 assert(src->fpu_regnr() == 0, "argument must be on TOS");
929 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
930 if (pop_fpu_stack) __ fstp_s (dst_addr);
931 else __ fst_s (dst_addr);
932
933 } else if (src->is_double_fpu()) {
934 assert(src->fpu_regnrLo() == 0, "argument must be on TOS");
935 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
936 if (pop_fpu_stack) __ fstp_d (dst_addr);
937 else __ fst_d (dst_addr);
938 #endif // !_LP64
939
940 } else {
941 ShouldNotReachHere();
942 }
943 }
944
945
946 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool wide) {
947 LIR_Address* to_addr = dest->as_address_ptr();
948 PatchingStub* patch = NULL;
949 Register compressed_src = rscratch1;
950
951 if (is_reference_type(type)) {
952 __ verify_oop(src->as_register());
953 #ifdef _LP64
954 if (UseCompressedOops && !wide) {
955 __ movptr(compressed_src, src->as_register());
956 __ encode_heap_oop(compressed_src);
957 if (patch_code != lir_patch_none) {
958 info->oop_map()->set_narrowoop(compressed_src->as_VMReg());
959 }
960 }
961 #endif
962 }
963
964 if (patch_code != lir_patch_none) {
965 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
966 Address toa = as_Address(to_addr);
967 assert(toa.disp() != 0, "must have");
968 }
969
970 int null_check_here = code_offset();
971 switch (type) {
972 case T_FLOAT: {
973 #ifdef _LP64
974 assert(src->is_single_xmm(), "not a float");
975 __ movflt(as_Address(to_addr), src->as_xmm_float_reg());
976 #else
977 if (src->is_single_xmm()) {
978 __ movflt(as_Address(to_addr), src->as_xmm_float_reg());
979 } else {
980 assert(src->is_single_fpu(), "must be");
981 assert(src->fpu_regnr() == 0, "argument must be on TOS");
982 if (pop_fpu_stack) __ fstp_s(as_Address(to_addr));
983 else __ fst_s (as_Address(to_addr));
984 }
985 #endif // _LP64
986 break;
987 }
988
989 case T_DOUBLE: {
990 #ifdef _LP64
991 assert(src->is_double_xmm(), "not a double");
992 __ movdbl(as_Address(to_addr), src->as_xmm_double_reg());
993 #else
994 if (src->is_double_xmm()) {
995 __ movdbl(as_Address(to_addr), src->as_xmm_double_reg());
996 } else {
997 assert(src->is_double_fpu(), "must be");
998 assert(src->fpu_regnrLo() == 0, "argument must be on TOS");
999 if (pop_fpu_stack) __ fstp_d(as_Address(to_addr));
1000 else __ fst_d (as_Address(to_addr));
1001 }
1002 #endif // _LP64
1003 break;
1004 }
1005
1006 case T_ARRAY: // fall through
1007 case T_OBJECT: // fall through
1008 if (UseCompressedOops && !wide) {
1009 __ movl(as_Address(to_addr), compressed_src);
1010 } else {
1011 __ movptr(as_Address(to_addr), src->as_register());
1012 }
1013 break;
1014 case T_METADATA:
1015 // We get here to store a method pointer to the stack to pass to
1016 // a dtrace runtime call. This can't work on 64 bit with
1017 // compressed klass ptrs: T_METADATA can be a compressed klass
1018 // ptr or a 64 bit method pointer.
1019 LP64_ONLY(ShouldNotReachHere());
1020 __ movptr(as_Address(to_addr), src->as_register());
1021 break;
1022 case T_ADDRESS:
1023 __ movptr(as_Address(to_addr), src->as_register());
1024 break;
1025 case T_INT:
1026 __ movl(as_Address(to_addr), src->as_register());
1027 break;
1028
1029 case T_LONG: {
1030 Register from_lo = src->as_register_lo();
1031 Register from_hi = src->as_register_hi();
1032 #ifdef _LP64
1033 __ movptr(as_Address_lo(to_addr), from_lo);
1034 #else
1035 Register base = to_addr->base()->as_register();
1036 Register index = noreg;
1037 if (to_addr->index()->is_register()) {
1038 index = to_addr->index()->as_register();
1039 }
1040 if (base == from_lo || index == from_lo) {
1041 assert(base != from_hi, "can't be");
1042 assert(index == noreg || (index != base && index != from_hi), "can't handle this");
1043 __ movl(as_Address_hi(to_addr), from_hi);
1044 if (patch != NULL) {
1045 patching_epilog(patch, lir_patch_high, base, info);
1046 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1047 patch_code = lir_patch_low;
1048 }
1049 __ movl(as_Address_lo(to_addr), from_lo);
1050 } else {
1051 assert(index == noreg || (index != base && index != from_lo), "can't handle this");
1052 __ movl(as_Address_lo(to_addr), from_lo);
1053 if (patch != NULL) {
1054 patching_epilog(patch, lir_patch_low, base, info);
1055 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1056 patch_code = lir_patch_high;
1057 }
1058 __ movl(as_Address_hi(to_addr), from_hi);
1059 }
1060 #endif // _LP64
1061 break;
1062 }
1063
1064 case T_BYTE: // fall through
1065 case T_BOOLEAN: {
1066 Register src_reg = src->as_register();
1067 Address dst_addr = as_Address(to_addr);
1068 assert(VM_Version::is_P6() || src_reg->has_byte_register(), "must use byte registers if not P6");
1069 __ movb(dst_addr, src_reg);
1070 break;
1071 }
1072
1073 case T_CHAR: // fall through
1074 case T_SHORT:
1075 __ movw(as_Address(to_addr), src->as_register());
1076 break;
1077
1078 default:
1079 ShouldNotReachHere();
1080 }
1081 if (info != NULL) {
1082 add_debug_info_for_null_check(null_check_here, info);
1083 }
1084
1085 if (patch_code != lir_patch_none) {
1086 patching_epilog(patch, patch_code, to_addr->base()->as_register(), info);
1087 }
1088 }
1089
1090
1091 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
1092 assert(src->is_stack(), "should not call otherwise");
1093 assert(dest->is_register(), "should not call otherwise");
1094
1095 if (dest->is_single_cpu()) {
1096 if (is_reference_type(type)) {
1097 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1098 __ verify_oop(dest->as_register());
1099 } else if (type == T_METADATA || type == T_ADDRESS) {
1100 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1101 } else {
1102 __ movl(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1103 }
1104
1105 } else if (dest->is_double_cpu()) {
1106 Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix(), lo_word_offset_in_bytes);
1107 Address src_addr_HI = frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes);
1108 __ movptr(dest->as_register_lo(), src_addr_LO);
1109 NOT_LP64(__ movptr(dest->as_register_hi(), src_addr_HI));
1110
1111 } else if (dest->is_single_xmm()) {
1112 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
1113 __ movflt(dest->as_xmm_float_reg(), src_addr);
1114
1115 } else if (dest->is_double_xmm()) {
1116 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
1117 __ movdbl(dest->as_xmm_double_reg(), src_addr);
1118
1119 #ifndef _LP64
1120 } else if (dest->is_single_fpu()) {
1121 assert(dest->fpu_regnr() == 0, "dest must be TOS");
1122 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
1123 __ fld_s(src_addr);
1124
1125 } else if (dest->is_double_fpu()) {
1126 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
1127 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
1128 __ fld_d(src_addr);
1129 #endif // _LP64
1130
1131 } else {
1132 ShouldNotReachHere();
1133 }
1134 }
1135
1136
1137 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
1138 if (src->is_single_stack()) {
1139 if (is_reference_type(type)) {
1140 __ pushptr(frame_map()->address_for_slot(src ->single_stack_ix()));
1141 __ popptr (frame_map()->address_for_slot(dest->single_stack_ix()));
1142 } else {
1143 #ifndef _LP64
1144 __ pushl(frame_map()->address_for_slot(src ->single_stack_ix()));
1145 __ popl (frame_map()->address_for_slot(dest->single_stack_ix()));
1146 #else
1147 //no pushl on 64bits
1148 __ movl(rscratch1, frame_map()->address_for_slot(src ->single_stack_ix()));
1149 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), rscratch1);
1150 #endif
1151 }
1152
1153 } else if (src->is_double_stack()) {
1154 #ifdef _LP64
1155 __ pushptr(frame_map()->address_for_slot(src ->double_stack_ix()));
1156 __ popptr (frame_map()->address_for_slot(dest->double_stack_ix()));
1157 #else
1158 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 0));
1159 // push and pop the part at src + wordSize, adding wordSize for the previous push
1160 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 2 * wordSize));
1161 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 2 * wordSize));
1162 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 0));
1163 #endif // _LP64
1164
1165 } else {
1166 ShouldNotReachHere();
1167 }
1168 }
1169
1170
1171 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide) {
1172 assert(src->is_address(), "should not call otherwise");
1173 assert(dest->is_register(), "should not call otherwise");
1174
1175 LIR_Address* addr = src->as_address_ptr();
1176 Address from_addr = as_Address(addr);
1177
1178 if (addr->base()->type() == T_OBJECT) {
1179 __ verify_oop(addr->base()->as_pointer_register());
1180 }
1181
1182 switch (type) {
1183 case T_BOOLEAN: // fall through
1184 case T_BYTE: // fall through
1185 case T_CHAR: // fall through
1186 case T_SHORT:
1187 if (!VM_Version::is_P6() && !from_addr.uses(dest->as_register())) {
1188 // on pre P6 processors we may get partial register stalls
1189 // so blow away the value of to_rinfo before loading a
1190 // partial word into it. Do it here so that it precedes
1191 // the potential patch point below.
1192 __ xorptr(dest->as_register(), dest->as_register());
1193 }
1194 break;
1195 default:
1196 break;
1197 }
1198
1199 PatchingStub* patch = NULL;
1200 if (patch_code != lir_patch_none) {
1201 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1202 assert(from_addr.disp() != 0, "must have");
1203 }
1204 if (info != NULL) {
1205 add_debug_info_for_null_check_here(info);
1206 }
1207
1208 switch (type) {
1209 case T_FLOAT: {
1210 if (dest->is_single_xmm()) {
1211 __ movflt(dest->as_xmm_float_reg(), from_addr);
1212 } else {
1213 #ifndef _LP64
1214 assert(dest->is_single_fpu(), "must be");
1215 assert(dest->fpu_regnr() == 0, "dest must be TOS");
1216 __ fld_s(from_addr);
1217 #else
1218 ShouldNotReachHere();
1219 #endif // !LP64
1220 }
1221 break;
1222 }
1223
1224 case T_DOUBLE: {
1225 if (dest->is_double_xmm()) {
1226 __ movdbl(dest->as_xmm_double_reg(), from_addr);
1227 } else {
1228 #ifndef _LP64
1229 assert(dest->is_double_fpu(), "must be");
1230 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
1231 __ fld_d(from_addr);
1232 #else
1233 ShouldNotReachHere();
1234 #endif // !LP64
1235 }
1236 break;
1237 }
1238
1239 case T_OBJECT: // fall through
1240 case T_ARRAY: // fall through
1241 if (UseCompressedOops && !wide) {
1242 __ movl(dest->as_register(), from_addr);
1243 } else {
1244 __ movptr(dest->as_register(), from_addr);
1245 }
1246 break;
1247
1248 case T_ADDRESS:
1249 __ movptr(dest->as_register(), from_addr);
1250 break;
1251 case T_INT:
1252 __ movl(dest->as_register(), from_addr);
1253 break;
1254
1255 case T_LONG: {
1256 Register to_lo = dest->as_register_lo();
1257 Register to_hi = dest->as_register_hi();
1258 #ifdef _LP64
1259 __ movptr(to_lo, as_Address_lo(addr));
1260 #else
1261 Register base = addr->base()->as_register();
1262 Register index = noreg;
1263 if (addr->index()->is_register()) {
1264 index = addr->index()->as_register();
1265 }
1266 if ((base == to_lo && index == to_hi) ||
1267 (base == to_hi && index == to_lo)) {
1268 // addresses with 2 registers are only formed as a result of
1269 // array access so this code will never have to deal with
1270 // patches or null checks.
1271 assert(info == NULL && patch == NULL, "must be");
1272 __ lea(to_hi, as_Address(addr));
1273 __ movl(to_lo, Address(to_hi, 0));
1274 __ movl(to_hi, Address(to_hi, BytesPerWord));
1275 } else if (base == to_lo || index == to_lo) {
1276 assert(base != to_hi, "can't be");
1277 assert(index == noreg || (index != base && index != to_hi), "can't handle this");
1278 __ movl(to_hi, as_Address_hi(addr));
1279 if (patch != NULL) {
1280 patching_epilog(patch, lir_patch_high, base, info);
1281 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1282 patch_code = lir_patch_low;
1283 }
1284 __ movl(to_lo, as_Address_lo(addr));
1285 } else {
1286 assert(index == noreg || (index != base && index != to_lo), "can't handle this");
1287 __ movl(to_lo, as_Address_lo(addr));
1288 if (patch != NULL) {
1289 patching_epilog(patch, lir_patch_low, base, info);
1290 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1291 patch_code = lir_patch_high;
1292 }
1293 __ movl(to_hi, as_Address_hi(addr));
1294 }
1295 #endif // _LP64
1296 break;
1297 }
1298
1299 case T_BOOLEAN: // fall through
1300 case T_BYTE: {
1301 Register dest_reg = dest->as_register();
1302 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
1303 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1304 __ movsbl(dest_reg, from_addr);
1305 } else {
1306 __ movb(dest_reg, from_addr);
1307 __ shll(dest_reg, 24);
1308 __ sarl(dest_reg, 24);
1309 }
1310 break;
1311 }
1312
1313 case T_CHAR: {
1314 Register dest_reg = dest->as_register();
1315 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
1316 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1317 __ movzwl(dest_reg, from_addr);
1318 } else {
1319 __ movw(dest_reg, from_addr);
1320 }
1321 break;
1322 }
1323
1324 case T_SHORT: {
1325 Register dest_reg = dest->as_register();
1326 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1327 __ movswl(dest_reg, from_addr);
1328 } else {
1329 __ movw(dest_reg, from_addr);
1330 __ shll(dest_reg, 16);
1331 __ sarl(dest_reg, 16);
1332 }
1333 break;
1334 }
1335
1336 default:
1337 ShouldNotReachHere();
1338 }
1339
1340 if (patch != NULL) {
1341 patching_epilog(patch, patch_code, addr->base()->as_register(), info);
1342 }
1343
1344 if (is_reference_type(type)) {
1345 #ifdef _LP64
1346 if (UseCompressedOops && !wide) {
1347 __ decode_heap_oop(dest->as_register());
1348 }
1349 #endif
1350
1351 // Load barrier has not yet been applied, so ZGC can't verify the oop here
1352 if (!UseZGC) {
1353 __ verify_oop(dest->as_register());
1354 }
1355 }
1356 }
1357
1358
1359 NEEDS_CLEANUP; // This could be static?
1360 Address::ScaleFactor LIR_Assembler::array_element_size(BasicType type) const {
1361 int elem_size = type2aelembytes(type);
1362 switch (elem_size) {
1363 case 1: return Address::times_1;
1364 case 2: return Address::times_2;
1365 case 4: return Address::times_4;
1366 case 8: return Address::times_8;
1367 }
1368 ShouldNotReachHere();
1369 return Address::no_scale;
1370 }
1371
1372
1373 void LIR_Assembler::emit_op3(LIR_Op3* op) {
1374 switch (op->code()) {
1375 case lir_idiv:
1376 case lir_irem:
1377 arithmetic_idiv(op->code(),
1378 op->in_opr1(),
1379 op->in_opr2(),
1380 op->in_opr3(),
1381 op->result_opr(),
1382 op->info());
1383 break;
1384 case lir_fmad:
1385 __ fmad(op->result_opr()->as_xmm_double_reg(),
1386 op->in_opr1()->as_xmm_double_reg(),
1387 op->in_opr2()->as_xmm_double_reg(),
1388 op->in_opr3()->as_xmm_double_reg());
1389 break;
1390 case lir_fmaf:
1391 __ fmaf(op->result_opr()->as_xmm_float_reg(),
1392 op->in_opr1()->as_xmm_float_reg(),
1393 op->in_opr2()->as_xmm_float_reg(),
1394 op->in_opr3()->as_xmm_float_reg());
1395 break;
1396 default: ShouldNotReachHere(); break;
1397 }
1398 }
1399
1400 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
1401 #ifdef ASSERT
1402 assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label");
1403 if (op->block() != NULL) _branch_target_blocks.append(op->block());
1404 if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock());
1405 #endif
1406
1407 if (op->cond() == lir_cond_always) {
1408 if (op->info() != NULL) add_debug_info_for_branch(op->info());
1409 __ jmp (*(op->label()));
1410 } else {
1411 Assembler::Condition acond = Assembler::zero;
1412 if (op->code() == lir_cond_float_branch) {
1413 assert(op->ublock() != NULL, "must have unordered successor");
1414 __ jcc(Assembler::parity, *(op->ublock()->label()));
1415 switch(op->cond()) {
1416 case lir_cond_equal: acond = Assembler::equal; break;
1417 case lir_cond_notEqual: acond = Assembler::notEqual; break;
1418 case lir_cond_less: acond = Assembler::below; break;
1419 case lir_cond_lessEqual: acond = Assembler::belowEqual; break;
1420 case lir_cond_greaterEqual: acond = Assembler::aboveEqual; break;
1421 case lir_cond_greater: acond = Assembler::above; break;
1422 default: ShouldNotReachHere();
1423 }
1424 } else {
1425 switch (op->cond()) {
1426 case lir_cond_equal: acond = Assembler::equal; break;
1427 case lir_cond_notEqual: acond = Assembler::notEqual; break;
1428 case lir_cond_less: acond = Assembler::less; break;
1429 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
1430 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break;
1431 case lir_cond_greater: acond = Assembler::greater; break;
1432 case lir_cond_belowEqual: acond = Assembler::belowEqual; break;
1433 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break;
1434 default: ShouldNotReachHere();
1435 }
1436 }
1437 __ jcc(acond,*(op->label()));
1438 }
1439 }
1440
1441 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
1442 LIR_Opr src = op->in_opr();
1443 LIR_Opr dest = op->result_opr();
1444
1445 switch (op->bytecode()) {
1446 case Bytecodes::_i2l:
1447 #ifdef _LP64
1448 __ movl2ptr(dest->as_register_lo(), src->as_register());
1449 #else
1450 move_regs(src->as_register(), dest->as_register_lo());
1451 move_regs(src->as_register(), dest->as_register_hi());
1452 __ sarl(dest->as_register_hi(), 31);
1453 #endif // LP64
1454 break;
1455
1456 case Bytecodes::_l2i:
1457 #ifdef _LP64
1458 __ movl(dest->as_register(), src->as_register_lo());
1459 #else
1460 move_regs(src->as_register_lo(), dest->as_register());
1461 #endif
1462 break;
1463
1464 case Bytecodes::_i2b:
1465 move_regs(src->as_register(), dest->as_register());
1466 __ sign_extend_byte(dest->as_register());
1467 break;
1468
1469 case Bytecodes::_i2c:
1470 move_regs(src->as_register(), dest->as_register());
1471 __ andl(dest->as_register(), 0xFFFF);
1472 break;
1473
1474 case Bytecodes::_i2s:
1475 move_regs(src->as_register(), dest->as_register());
1476 __ sign_extend_short(dest->as_register());
1477 break;
1478
1479
1480 #ifdef _LP64
1481 case Bytecodes::_f2d:
1482 __ cvtss2sd(dest->as_xmm_double_reg(), src->as_xmm_float_reg());
1483 break;
1484
1485 case Bytecodes::_d2f:
1486 __ cvtsd2ss(dest->as_xmm_float_reg(), src->as_xmm_double_reg());
1487 break;
1488
1489 case Bytecodes::_i2f:
1490 __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register());
1491 break;
1492
1493 case Bytecodes::_i2d:
1494 __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register());
1495 break;
1496
1497 case Bytecodes::_l2f:
1498 __ cvtsi2ssq(dest->as_xmm_float_reg(), src->as_register_lo());
1499 break;
1500
1501 case Bytecodes::_l2d:
1502 __ cvtsi2sdq(dest->as_xmm_double_reg(), src->as_register_lo());
1503 break;
1504
1505 case Bytecodes::_f2i:
1506 __ convert_f2i(dest->as_register(), src->as_xmm_float_reg());
1507 break;
1508
1509 case Bytecodes::_d2i:
1510 __ convert_d2i(dest->as_register(), src->as_xmm_double_reg());
1511 break;
1512
1513 case Bytecodes::_f2l:
1514 __ convert_f2l(dest->as_register_lo(), src->as_xmm_float_reg());
1515 break;
1516
1517 case Bytecodes::_d2l:
1518 __ convert_d2l(dest->as_register_lo(), src->as_xmm_double_reg());
1519 break;
1520 #else
1521 case Bytecodes::_f2d:
1522 case Bytecodes::_d2f:
1523 if (dest->is_single_xmm()) {
1524 __ cvtsd2ss(dest->as_xmm_float_reg(), src->as_xmm_double_reg());
1525 } else if (dest->is_double_xmm()) {
1526 __ cvtss2sd(dest->as_xmm_double_reg(), src->as_xmm_float_reg());
1527 } else {
1528 assert(src->fpu() == dest->fpu(), "register must be equal");
1529 // do nothing (float result is rounded later through spilling)
1530 }
1531 break;
1532
1533 case Bytecodes::_i2f:
1534 case Bytecodes::_i2d:
1535 if (dest->is_single_xmm()) {
1536 __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register());
1537 } else if (dest->is_double_xmm()) {
1538 __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register());
1539 } else {
1540 assert(dest->fpu() == 0, "result must be on TOS");
1541 __ movl(Address(rsp, 0), src->as_register());
1542 __ fild_s(Address(rsp, 0));
1543 }
1544 break;
1545
1546 case Bytecodes::_l2f:
1547 case Bytecodes::_l2d:
1548 assert(!dest->is_xmm_register(), "result in xmm register not supported (no SSE instruction present)");
1549 assert(dest->fpu() == 0, "result must be on TOS");
1550 __ movptr(Address(rsp, 0), src->as_register_lo());
1551 __ movl(Address(rsp, BytesPerWord), src->as_register_hi());
1552 __ fild_d(Address(rsp, 0));
1553 // float result is rounded later through spilling
1554 break;
1555
1556 case Bytecodes::_f2i:
1557 case Bytecodes::_d2i:
1558 if (src->is_single_xmm()) {
1559 __ cvttss2sil(dest->as_register(), src->as_xmm_float_reg());
1560 } else if (src->is_double_xmm()) {
1561 __ cvttsd2sil(dest->as_register(), src->as_xmm_double_reg());
1562 } else {
1563 assert(src->fpu() == 0, "input must be on TOS");
1564 __ fldcw(ExternalAddress(StubRoutines::x86::addr_fpu_cntrl_wrd_trunc()));
1565 __ fist_s(Address(rsp, 0));
1566 __ movl(dest->as_register(), Address(rsp, 0));
1567 __ fldcw(ExternalAddress(StubRoutines::x86::addr_fpu_cntrl_wrd_std()));
1568 }
1569 // IA32 conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
1570 assert(op->stub() != NULL, "stub required");
1571 __ cmpl(dest->as_register(), 0x80000000);
1572 __ jcc(Assembler::equal, *op->stub()->entry());
1573 __ bind(*op->stub()->continuation());
1574 break;
1575
1576 case Bytecodes::_f2l:
1577 case Bytecodes::_d2l:
1578 assert(!src->is_xmm_register(), "input in xmm register not supported (no SSE instruction present)");
1579 assert(src->fpu() == 0, "input must be on TOS");
1580 assert(dest == FrameMap::long0_opr, "runtime stub places result in these registers");
1581
1582 // instruction sequence too long to inline it here
1583 {
1584 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::fpu2long_stub_id)));
1585 }
1586 break;
1587 #endif // _LP64
1588
1589 default: ShouldNotReachHere();
1590 }
1591 }
1592
1593 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
1594 if (op->init_check()) {
1595 add_debug_info_for_null_check_here(op->stub()->info());
1596 __ cmpb(Address(op->klass()->as_register(),
1597 InstanceKlass::init_state_offset()),
1598 InstanceKlass::fully_initialized);
1599 __ jcc(Assembler::notEqual, *op->stub()->entry());
1600 }
1601 __ allocate_object(op->obj()->as_register(),
1602 op->tmp1()->as_register(),
1603 op->tmp2()->as_register(),
1604 op->header_size(),
1605 op->object_size(),
1606 op->klass()->as_register(),
1607 *op->stub()->entry());
1608 __ bind(*op->stub()->continuation());
1609 }
1610
1611 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
1612 Register len = op->len()->as_register();
1613 LP64_ONLY( __ movslq(len, len); )
1614
1615 if (UseSlowPath ||
1616 (!UseFastNewObjectArray && is_reference_type(op->type())) ||
1617 (!UseFastNewTypeArray && !is_reference_type(op->type()))) {
1618 __ jmp(*op->stub()->entry());
1619 } else {
1620 Register tmp1 = op->tmp1()->as_register();
1621 Register tmp2 = op->tmp2()->as_register();
1622 Register tmp3 = op->tmp3()->as_register();
1623 if (len == tmp1) {
1624 tmp1 = tmp3;
1625 } else if (len == tmp2) {
1626 tmp2 = tmp3;
1627 } else if (len == tmp3) {
1628 // everything is ok
1629 } else {
1630 __ mov(tmp3, len);
1631 }
1632 __ allocate_array(op->obj()->as_register(),
1633 len,
1634 tmp1,
1635 tmp2,
1636 arrayOopDesc::header_size(op->type()),
1637 array_element_size(op->type()),
1638 op->klass()->as_register(),
1639 *op->stub()->entry());
1640 }
1641 __ bind(*op->stub()->continuation());
1642 }
1643
1644 void LIR_Assembler::type_profile_helper(Register mdo,
1645 ciMethodData *md, ciProfileData *data,
1646 Register recv, Label* update_done) {
1647 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1648 Label next_test;
1649 // See if the receiver is receiver[n].
1650 __ cmpptr(recv, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))));
1651 __ jccb(Assembler::notEqual, next_test);
1652 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)));
1653 __ addptr(data_addr, DataLayout::counter_increment);
1654 __ jmp(*update_done);
1655 __ bind(next_test);
1656 }
1657
1658 // Didn't find receiver; find next empty slot and fill it in
1659 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1660 Label next_test;
1661 Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)));
1662 __ cmpptr(recv_addr, (intptr_t)NULL_WORD);
1663 __ jccb(Assembler::notEqual, next_test);
1664 __ movptr(recv_addr, recv);
1665 __ movptr(Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))), DataLayout::counter_increment);
1666 __ jmp(*update_done);
1667 __ bind(next_test);
1668 }
1669 }
1670
1671 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
1672 // we always need a stub for the failure case.
1673 CodeStub* stub = op->stub();
1674 Register obj = op->object()->as_register();
1675 Register k_RInfo = op->tmp1()->as_register();
1676 Register klass_RInfo = op->tmp2()->as_register();
1677 Register dst = op->result_opr()->as_register();
1678 ciKlass* k = op->klass();
1679 Register Rtmp1 = noreg;
1680 Register tmp_load_klass = LP64_ONLY(rscratch1) NOT_LP64(noreg);
1681
1682 // check if it needs to be profiled
1683 ciMethodData* md = NULL;
1684 ciProfileData* data = NULL;
1685
1686 if (op->should_profile()) {
1687 ciMethod* method = op->profiled_method();
1688 assert(method != NULL, "Should have method");
1689 int bci = op->profiled_bci();
1690 md = method->method_data_or_null();
1691 assert(md != NULL, "Sanity");
1692 data = md->bci_to_data(bci);
1693 assert(data != NULL, "need data for type check");
1694 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1695 }
1696 Label profile_cast_success, profile_cast_failure;
1697 Label *success_target = op->should_profile() ? &profile_cast_success : success;
1698 Label *failure_target = op->should_profile() ? &profile_cast_failure : failure;
1699
1700 if (obj == k_RInfo) {
1701 k_RInfo = dst;
1702 } else if (obj == klass_RInfo) {
1703 klass_RInfo = dst;
1704 }
1705 if (k->is_loaded() && !UseCompressedClassPointers) {
1706 select_different_registers(obj, dst, k_RInfo, klass_RInfo);
1707 } else {
1708 Rtmp1 = op->tmp3()->as_register();
1709 select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1);
1710 }
1711
1712 assert_different_registers(obj, k_RInfo, klass_RInfo);
1713
1714 __ cmpptr(obj, (int32_t)NULL_WORD);
1715 if (op->should_profile()) {
1716 Label not_null;
1717 __ jccb(Assembler::notEqual, not_null);
1718 // Object is null; update MDO and exit
1719 Register mdo = klass_RInfo;
1720 __ mov_metadata(mdo, md->constant_encoding());
1721 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()));
1722 int header_bits = BitData::null_seen_byte_constant();
1723 __ orb(data_addr, header_bits);
1724 __ jmp(*obj_is_null);
1725 __ bind(not_null);
1726 } else {
1727 __ jcc(Assembler::equal, *obj_is_null);
1728 }
1729
1730 if (!k->is_loaded()) {
1731 klass2reg_with_patching(k_RInfo, op->info_for_patch());
1732 } else {
1733 #ifdef _LP64
1734 __ mov_metadata(k_RInfo, k->constant_encoding());
1735 #endif // _LP64
1736 }
1737 __ verify_oop(obj);
1738
1739 if (op->fast_check()) {
1740 // get object class
1741 // not a safepoint as obj null check happens earlier
1742 #ifdef _LP64
1743 if (UseCompressedClassPointers) {
1744 __ load_klass(Rtmp1, obj, tmp_load_klass);
1745 __ cmpptr(k_RInfo, Rtmp1);
1746 } else {
1747 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1748 }
1749 #else
1750 if (k->is_loaded()) {
1751 __ cmpklass(Address(obj, oopDesc::klass_offset_in_bytes()), k->constant_encoding());
1752 } else {
1753 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1754 }
1755 #endif
1756 __ jcc(Assembler::notEqual, *failure_target);
1757 // successful cast, fall through to profile or jump
1758 } else {
1759 // get object class
1760 // not a safepoint as obj null check happens earlier
1761 __ load_klass(klass_RInfo, obj, tmp_load_klass);
1762 if (k->is_loaded()) {
1763 // See if we get an immediate positive hit
1764 #ifdef _LP64
1765 __ cmpptr(k_RInfo, Address(klass_RInfo, k->super_check_offset()));
1766 #else
1767 __ cmpklass(Address(klass_RInfo, k->super_check_offset()), k->constant_encoding());
1768 #endif // _LP64
1769 if ((juint)in_bytes(Klass::secondary_super_cache_offset()) != k->super_check_offset()) {
1770 __ jcc(Assembler::notEqual, *failure_target);
1771 // successful cast, fall through to profile or jump
1772 } else {
1773 // See if we get an immediate positive hit
1774 __ jcc(Assembler::equal, *success_target);
1775 // check for self
1776 #ifdef _LP64
1777 __ cmpptr(klass_RInfo, k_RInfo);
1778 #else
1779 __ cmpklass(klass_RInfo, k->constant_encoding());
1780 #endif // _LP64
1781 __ jcc(Assembler::equal, *success_target);
1782
1783 __ push(klass_RInfo);
1784 #ifdef _LP64
1785 __ push(k_RInfo);
1786 #else
1787 __ pushklass(k->constant_encoding());
1788 #endif // _LP64
1789 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1790 __ pop(klass_RInfo);
1791 __ pop(klass_RInfo);
1792 // result is a boolean
1793 __ cmpl(klass_RInfo, 0);
1794 __ jcc(Assembler::equal, *failure_target);
1795 // successful cast, fall through to profile or jump
1796 }
1797 } else {
1798 // perform the fast part of the checking logic
1799 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL);
1800 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1801 __ push(klass_RInfo);
1802 __ push(k_RInfo);
1803 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1804 __ pop(klass_RInfo);
1805 __ pop(k_RInfo);
1806 // result is a boolean
1807 __ cmpl(k_RInfo, 0);
1808 __ jcc(Assembler::equal, *failure_target);
1809 // successful cast, fall through to profile or jump
1810 }
1811 }
1812 if (op->should_profile()) {
1813 Register mdo = klass_RInfo, recv = k_RInfo;
1814 __ bind(profile_cast_success);
1815 __ mov_metadata(mdo, md->constant_encoding());
1816 __ load_klass(recv, obj, tmp_load_klass);
1817 type_profile_helper(mdo, md, data, recv, success);
1818 __ jmp(*success);
1819
1820 __ bind(profile_cast_failure);
1821 __ mov_metadata(mdo, md->constant_encoding());
1822 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1823 __ subptr(counter_addr, DataLayout::counter_increment);
1824 __ jmp(*failure);
1825 }
1826 __ jmp(*success);
1827 }
1828
1829
1830 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
1831 Register tmp_load_klass = LP64_ONLY(rscratch1) NOT_LP64(noreg);
1832 LIR_Code code = op->code();
1833 if (code == lir_store_check) {
1834 Register value = op->object()->as_register();
1835 Register array = op->array()->as_register();
1836 Register k_RInfo = op->tmp1()->as_register();
1837 Register klass_RInfo = op->tmp2()->as_register();
1838 Register Rtmp1 = op->tmp3()->as_register();
1839
1840 CodeStub* stub = op->stub();
1841
1842 // check if it needs to be profiled
1843 ciMethodData* md = NULL;
1844 ciProfileData* data = NULL;
1845
1846 if (op->should_profile()) {
1847 ciMethod* method = op->profiled_method();
1848 assert(method != NULL, "Should have method");
1849 int bci = op->profiled_bci();
1850 md = method->method_data_or_null();
1851 assert(md != NULL, "Sanity");
1852 data = md->bci_to_data(bci);
1853 assert(data != NULL, "need data for type check");
1854 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1855 }
1856 Label profile_cast_success, profile_cast_failure, done;
1857 Label *success_target = op->should_profile() ? &profile_cast_success : &done;
1858 Label *failure_target = op->should_profile() ? &profile_cast_failure : stub->entry();
1859
1860 __ cmpptr(value, (int32_t)NULL_WORD);
1861 if (op->should_profile()) {
1862 Label not_null;
1863 __ jccb(Assembler::notEqual, not_null);
1864 // Object is null; update MDO and exit
1865 Register mdo = klass_RInfo;
1866 __ mov_metadata(mdo, md->constant_encoding());
1867 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()));
1868 int header_bits = BitData::null_seen_byte_constant();
1869 __ orb(data_addr, header_bits);
1870 __ jmp(done);
1871 __ bind(not_null);
1872 } else {
1873 __ jcc(Assembler::equal, done);
1874 }
1875
1876 add_debug_info_for_null_check_here(op->info_for_exception());
1877 __ load_klass(k_RInfo, array, tmp_load_klass);
1878 __ load_klass(klass_RInfo, value, tmp_load_klass);
1879
1880 // get instance klass (it's already uncompressed)
1881 __ movptr(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset()));
1882 // perform the fast part of the checking logic
1883 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL);
1884 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1885 __ push(klass_RInfo);
1886 __ push(k_RInfo);
1887 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1888 __ pop(klass_RInfo);
1889 __ pop(k_RInfo);
1890 // result is a boolean
1891 __ cmpl(k_RInfo, 0);
1892 __ jcc(Assembler::equal, *failure_target);
1893 // fall through to the success case
1894
1895 if (op->should_profile()) {
1896 Register mdo = klass_RInfo, recv = k_RInfo;
1897 __ bind(profile_cast_success);
1898 __ mov_metadata(mdo, md->constant_encoding());
1899 __ load_klass(recv, value, tmp_load_klass);
1900 type_profile_helper(mdo, md, data, recv, &done);
1901 __ jmpb(done);
1902
1903 __ bind(profile_cast_failure);
1904 __ mov_metadata(mdo, md->constant_encoding());
1905 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1906 __ subptr(counter_addr, DataLayout::counter_increment);
1907 __ jmp(*stub->entry());
1908 }
1909
1910 __ bind(done);
1911 } else
1912 if (code == lir_checkcast) {
1913 Register obj = op->object()->as_register();
1914 Register dst = op->result_opr()->as_register();
1915 Label success;
1916 emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
1917 __ bind(success);
1918 if (dst != obj) {
1919 __ mov(dst, obj);
1920 }
1921 } else
1922 if (code == lir_instanceof) {
1923 Register obj = op->object()->as_register();
1924 Register dst = op->result_opr()->as_register();
1925 Label success, failure, done;
1926 emit_typecheck_helper(op, &success, &failure, &failure);
1927 __ bind(failure);
1928 __ xorptr(dst, dst);
1929 __ jmpb(done);
1930 __ bind(success);
1931 __ movptr(dst, 1);
1932 __ bind(done);
1933 } else {
1934 ShouldNotReachHere();
1935 }
1936
1937 }
1938
1939
1940 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
1941 if (LP64_ONLY(false &&) op->code() == lir_cas_long && VM_Version::supports_cx8()) {
1942 assert(op->cmp_value()->as_register_lo() == rax, "wrong register");
1943 assert(op->cmp_value()->as_register_hi() == rdx, "wrong register");
1944 assert(op->new_value()->as_register_lo() == rbx, "wrong register");
1945 assert(op->new_value()->as_register_hi() == rcx, "wrong register");
1946 Register addr = op->addr()->as_register();
1947 __ lock();
1948 NOT_LP64(__ cmpxchg8(Address(addr, 0)));
1949
1950 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj ) {
1951 NOT_LP64(assert(op->addr()->is_single_cpu(), "must be single");)
1952 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
1953 Register newval = op->new_value()->as_register();
1954 Register cmpval = op->cmp_value()->as_register();
1955 assert(cmpval == rax, "wrong register");
1956 assert(newval != NULL, "new val must be register");
1957 assert(cmpval != newval, "cmp and new values must be in different registers");
1958 assert(cmpval != addr, "cmp and addr must be in different registers");
1959 assert(newval != addr, "new value and addr must be in different registers");
1960
1961 if ( op->code() == lir_cas_obj) {
1962 #ifdef _LP64
1963 if (UseCompressedOops) {
1964 __ encode_heap_oop(cmpval);
1965 __ mov(rscratch1, newval);
1966 __ encode_heap_oop(rscratch1);
1967 __ lock();
1968 // cmpval (rax) is implicitly used by this instruction
1969 __ cmpxchgl(rscratch1, Address(addr, 0));
1970 } else
1971 #endif
1972 {
1973 __ lock();
1974 __ cmpxchgptr(newval, Address(addr, 0));
1975 }
1976 } else {
1977 assert(op->code() == lir_cas_int, "lir_cas_int expected");
1978 __ lock();
1979 __ cmpxchgl(newval, Address(addr, 0));
1980 }
1981 #ifdef _LP64
1982 } else if (op->code() == lir_cas_long) {
1983 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
1984 Register newval = op->new_value()->as_register_lo();
1985 Register cmpval = op->cmp_value()->as_register_lo();
1986 assert(cmpval == rax, "wrong register");
1987 assert(newval != NULL, "new val must be register");
1988 assert(cmpval != newval, "cmp and new values must be in different registers");
1989 assert(cmpval != addr, "cmp and addr must be in different registers");
1990 assert(newval != addr, "new value and addr must be in different registers");
1991 __ lock();
1992 __ cmpxchgq(newval, Address(addr, 0));
1993 #endif // _LP64
1994 } else {
1995 Unimplemented();
1996 }
1997 }
1998
1999 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type,
2000 LIR_Opr cmp_opr1, LIR_Opr cmp_opr2) {
2001 assert(cmp_opr1 == LIR_OprFact::illegalOpr && cmp_opr2 == LIR_OprFact::illegalOpr, "unnecessary cmp oprs on x86");
2002
2003 Assembler::Condition acond, ncond;
2004 switch (condition) {
2005 case lir_cond_equal: acond = Assembler::equal; ncond = Assembler::notEqual; break;
2006 case lir_cond_notEqual: acond = Assembler::notEqual; ncond = Assembler::equal; break;
2007 case lir_cond_less: acond = Assembler::less; ncond = Assembler::greaterEqual; break;
2008 case lir_cond_lessEqual: acond = Assembler::lessEqual; ncond = Assembler::greater; break;
2009 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; ncond = Assembler::less; break;
2010 case lir_cond_greater: acond = Assembler::greater; ncond = Assembler::lessEqual; break;
2011 case lir_cond_belowEqual: acond = Assembler::belowEqual; ncond = Assembler::above; break;
2012 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; ncond = Assembler::below; break;
2013 default: acond = Assembler::equal; ncond = Assembler::notEqual;
2014 ShouldNotReachHere();
2015 }
2016
2017 if (opr1->is_cpu_register()) {
2018 reg2reg(opr1, result);
2019 } else if (opr1->is_stack()) {
2020 stack2reg(opr1, result, result->type());
2021 } else if (opr1->is_constant()) {
2022 const2reg(opr1, result, lir_patch_none, NULL);
2023 } else {
2024 ShouldNotReachHere();
2025 }
2026
2027 if (VM_Version::supports_cmov() && !opr2->is_constant()) {
2028 // optimized version that does not require a branch
2029 if (opr2->is_single_cpu()) {
2030 assert(opr2->cpu_regnr() != result->cpu_regnr(), "opr2 already overwritten by previous move");
2031 __ cmov(ncond, result->as_register(), opr2->as_register());
2032 } else if (opr2->is_double_cpu()) {
2033 assert(opr2->cpu_regnrLo() != result->cpu_regnrLo() && opr2->cpu_regnrLo() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
2034 assert(opr2->cpu_regnrHi() != result->cpu_regnrLo() && opr2->cpu_regnrHi() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
2035 __ cmovptr(ncond, result->as_register_lo(), opr2->as_register_lo());
2036 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), opr2->as_register_hi());)
2037 } else if (opr2->is_single_stack()) {
2038 __ cmovl(ncond, result->as_register(), frame_map()->address_for_slot(opr2->single_stack_ix()));
2039 } else if (opr2->is_double_stack()) {
2040 __ cmovptr(ncond, result->as_register_lo(), frame_map()->address_for_slot(opr2->double_stack_ix(), lo_word_offset_in_bytes));
2041 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), frame_map()->address_for_slot(opr2->double_stack_ix(), hi_word_offset_in_bytes));)
2042 } else {
2043 ShouldNotReachHere();
2044 }
2045
2046 } else {
2047 Label skip;
2048 __ jcc (acond, skip);
2049 if (opr2->is_cpu_register()) {
2050 reg2reg(opr2, result);
2051 } else if (opr2->is_stack()) {
2052 stack2reg(opr2, result, result->type());
2053 } else if (opr2->is_constant()) {
2054 const2reg(opr2, result, lir_patch_none, NULL);
2055 } else {
2056 ShouldNotReachHere();
2057 }
2058 __ bind(skip);
2059 }
2060 }
2061
2062
2063 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) {
2064 assert(info == NULL, "should never be used, idiv/irem and ldiv/lrem not handled by this method");
2065
2066 if (left->is_single_cpu()) {
2067 assert(left == dest, "left and dest must be equal");
2068 Register lreg = left->as_register();
2069
2070 if (right->is_single_cpu()) {
2071 // cpu register - cpu register
2072 Register rreg = right->as_register();
2073 switch (code) {
2074 case lir_add: __ addl (lreg, rreg); break;
2075 case lir_sub: __ subl (lreg, rreg); break;
2076 case lir_mul: __ imull(lreg, rreg); break;
2077 default: ShouldNotReachHere();
2078 }
2079
2080 } else if (right->is_stack()) {
2081 // cpu register - stack
2082 Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
2083 switch (code) {
2084 case lir_add: __ addl(lreg, raddr); break;
2085 case lir_sub: __ subl(lreg, raddr); break;
2086 default: ShouldNotReachHere();
2087 }
2088
2089 } else if (right->is_constant()) {
2090 // cpu register - constant
2091 jint c = right->as_constant_ptr()->as_jint();
2092 switch (code) {
2093 case lir_add: {
2094 __ incrementl(lreg, c);
2095 break;
2096 }
2097 case lir_sub: {
2098 __ decrementl(lreg, c);
2099 break;
2100 }
2101 default: ShouldNotReachHere();
2102 }
2103
2104 } else {
2105 ShouldNotReachHere();
2106 }
2107
2108 } else if (left->is_double_cpu()) {
2109 assert(left == dest, "left and dest must be equal");
2110 Register lreg_lo = left->as_register_lo();
2111 Register lreg_hi = left->as_register_hi();
2112
2113 if (right->is_double_cpu()) {
2114 // cpu register - cpu register
2115 Register rreg_lo = right->as_register_lo();
2116 Register rreg_hi = right->as_register_hi();
2117 NOT_LP64(assert_different_registers(lreg_lo, lreg_hi, rreg_lo, rreg_hi));
2118 LP64_ONLY(assert_different_registers(lreg_lo, rreg_lo));
2119 switch (code) {
2120 case lir_add:
2121 __ addptr(lreg_lo, rreg_lo);
2122 NOT_LP64(__ adcl(lreg_hi, rreg_hi));
2123 break;
2124 case lir_sub:
2125 __ subptr(lreg_lo, rreg_lo);
2126 NOT_LP64(__ sbbl(lreg_hi, rreg_hi));
2127 break;
2128 case lir_mul:
2129 #ifdef _LP64
2130 __ imulq(lreg_lo, rreg_lo);
2131 #else
2132 assert(lreg_lo == rax && lreg_hi == rdx, "must be");
2133 __ imull(lreg_hi, rreg_lo);
2134 __ imull(rreg_hi, lreg_lo);
2135 __ addl (rreg_hi, lreg_hi);
2136 __ mull (rreg_lo);
2137 __ addl (lreg_hi, rreg_hi);
2138 #endif // _LP64
2139 break;
2140 default:
2141 ShouldNotReachHere();
2142 }
2143
2144 } else if (right->is_constant()) {
2145 // cpu register - constant
2146 #ifdef _LP64
2147 jlong c = right->as_constant_ptr()->as_jlong_bits();
2148 __ movptr(r10, (intptr_t) c);
2149 switch (code) {
2150 case lir_add:
2151 __ addptr(lreg_lo, r10);
2152 break;
2153 case lir_sub:
2154 __ subptr(lreg_lo, r10);
2155 break;
2156 default:
2157 ShouldNotReachHere();
2158 }
2159 #else
2160 jint c_lo = right->as_constant_ptr()->as_jint_lo();
2161 jint c_hi = right->as_constant_ptr()->as_jint_hi();
2162 switch (code) {
2163 case lir_add:
2164 __ addptr(lreg_lo, c_lo);
2165 __ adcl(lreg_hi, c_hi);
2166 break;
2167 case lir_sub:
2168 __ subptr(lreg_lo, c_lo);
2169 __ sbbl(lreg_hi, c_hi);
2170 break;
2171 default:
2172 ShouldNotReachHere();
2173 }
2174 #endif // _LP64
2175
2176 } else {
2177 ShouldNotReachHere();
2178 }
2179
2180 } else if (left->is_single_xmm()) {
2181 assert(left == dest, "left and dest must be equal");
2182 XMMRegister lreg = left->as_xmm_float_reg();
2183
2184 if (right->is_single_xmm()) {
2185 XMMRegister rreg = right->as_xmm_float_reg();
2186 switch (code) {
2187 case lir_add: __ addss(lreg, rreg); break;
2188 case lir_sub: __ subss(lreg, rreg); break;
2189 case lir_mul: __ mulss(lreg, rreg); break;
2190 case lir_div: __ divss(lreg, rreg); break;
2191 default: ShouldNotReachHere();
2192 }
2193 } else {
2194 Address raddr;
2195 if (right->is_single_stack()) {
2196 raddr = frame_map()->address_for_slot(right->single_stack_ix());
2197 } else if (right->is_constant()) {
2198 // hack for now
2199 raddr = __ as_Address(InternalAddress(float_constant(right->as_jfloat())));
2200 } else {
2201 ShouldNotReachHere();
2202 }
2203 switch (code) {
2204 case lir_add: __ addss(lreg, raddr); break;
2205 case lir_sub: __ subss(lreg, raddr); break;
2206 case lir_mul: __ mulss(lreg, raddr); break;
2207 case lir_div: __ divss(lreg, raddr); break;
2208 default: ShouldNotReachHere();
2209 }
2210 }
2211
2212 } else if (left->is_double_xmm()) {
2213 assert(left == dest, "left and dest must be equal");
2214
2215 XMMRegister lreg = left->as_xmm_double_reg();
2216 if (right->is_double_xmm()) {
2217 XMMRegister rreg = right->as_xmm_double_reg();
2218 switch (code) {
2219 case lir_add: __ addsd(lreg, rreg); break;
2220 case lir_sub: __ subsd(lreg, rreg); break;
2221 case lir_mul: __ mulsd(lreg, rreg); break;
2222 case lir_div: __ divsd(lreg, rreg); break;
2223 default: ShouldNotReachHere();
2224 }
2225 } else {
2226 Address raddr;
2227 if (right->is_double_stack()) {
2228 raddr = frame_map()->address_for_slot(right->double_stack_ix());
2229 } else if (right->is_constant()) {
2230 // hack for now
2231 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble())));
2232 } else {
2233 ShouldNotReachHere();
2234 }
2235 switch (code) {
2236 case lir_add: __ addsd(lreg, raddr); break;
2237 case lir_sub: __ subsd(lreg, raddr); break;
2238 case lir_mul: __ mulsd(lreg, raddr); break;
2239 case lir_div: __ divsd(lreg, raddr); break;
2240 default: ShouldNotReachHere();
2241 }
2242 }
2243
2244 #ifndef _LP64
2245 } else if (left->is_single_fpu()) {
2246 assert(dest->is_single_fpu(), "fpu stack allocation required");
2247
2248 if (right->is_single_fpu()) {
2249 arith_fpu_implementation(code, left->fpu_regnr(), right->fpu_regnr(), dest->fpu_regnr(), pop_fpu_stack);
2250
2251 } else {
2252 assert(left->fpu_regnr() == 0, "left must be on TOS");
2253 assert(dest->fpu_regnr() == 0, "dest must be on TOS");
2254
2255 Address raddr;
2256 if (right->is_single_stack()) {
2257 raddr = frame_map()->address_for_slot(right->single_stack_ix());
2258 } else if (right->is_constant()) {
2259 address const_addr = float_constant(right->as_jfloat());
2260 assert(const_addr != NULL, "incorrect float/double constant maintenance");
2261 // hack for now
2262 raddr = __ as_Address(InternalAddress(const_addr));
2263 } else {
2264 ShouldNotReachHere();
2265 }
2266
2267 switch (code) {
2268 case lir_add: __ fadd_s(raddr); break;
2269 case lir_sub: __ fsub_s(raddr); break;
2270 case lir_mul: __ fmul_s(raddr); break;
2271 case lir_div: __ fdiv_s(raddr); break;
2272 default: ShouldNotReachHere();
2273 }
2274 }
2275
2276 } else if (left->is_double_fpu()) {
2277 assert(dest->is_double_fpu(), "fpu stack allocation required");
2278
2279 if (code == lir_mul || code == lir_div) {
2280 // Double values require special handling for strictfp mul/div on x86
2281 __ fld_x(ExternalAddress(StubRoutines::x86::addr_fpu_subnormal_bias1()));
2282 __ fmulp(left->fpu_regnrLo() + 1);
2283 }
2284
2285 if (right->is_double_fpu()) {
2286 arith_fpu_implementation(code, left->fpu_regnrLo(), right->fpu_regnrLo(), dest->fpu_regnrLo(), pop_fpu_stack);
2287
2288 } else {
2289 assert(left->fpu_regnrLo() == 0, "left must be on TOS");
2290 assert(dest->fpu_regnrLo() == 0, "dest must be on TOS");
2291
2292 Address raddr;
2293 if (right->is_double_stack()) {
2294 raddr = frame_map()->address_for_slot(right->double_stack_ix());
2295 } else if (right->is_constant()) {
2296 // hack for now
2297 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble())));
2298 } else {
2299 ShouldNotReachHere();
2300 }
2301
2302 switch (code) {
2303 case lir_add: __ fadd_d(raddr); break;
2304 case lir_sub: __ fsub_d(raddr); break;
2305 case lir_mul: __ fmul_d(raddr); break;
2306 case lir_div: __ fdiv_d(raddr); break;
2307 default: ShouldNotReachHere();
2308 }
2309 }
2310
2311 if (code == lir_mul || code == lir_div) {
2312 // Double values require special handling for strictfp mul/div on x86
2313 __ fld_x(ExternalAddress(StubRoutines::x86::addr_fpu_subnormal_bias2()));
2314 __ fmulp(dest->fpu_regnrLo() + 1);
2315 }
2316 #endif // !_LP64
2317
2318 } else if (left->is_single_stack() || left->is_address()) {
2319 assert(left == dest, "left and dest must be equal");
2320
2321 Address laddr;
2322 if (left->is_single_stack()) {
2323 laddr = frame_map()->address_for_slot(left->single_stack_ix());
2324 } else if (left->is_address()) {
2325 laddr = as_Address(left->as_address_ptr());
2326 } else {
2327 ShouldNotReachHere();
2328 }
2329
2330 if (right->is_single_cpu()) {
2331 Register rreg = right->as_register();
2332 switch (code) {
2333 case lir_add: __ addl(laddr, rreg); break;
2334 case lir_sub: __ subl(laddr, rreg); break;
2335 default: ShouldNotReachHere();
2336 }
2337 } else if (right->is_constant()) {
2338 jint c = right->as_constant_ptr()->as_jint();
2339 switch (code) {
2340 case lir_add: {
2341 __ incrementl(laddr, c);
2342 break;
2343 }
2344 case lir_sub: {
2345 __ decrementl(laddr, c);
2346 break;
2347 }
2348 default: ShouldNotReachHere();
2349 }
2350 } else {
2351 ShouldNotReachHere();
2352 }
2353
2354 } else {
2355 ShouldNotReachHere();
2356 }
2357 }
2358
2359 #ifndef _LP64
2360 void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) {
2361 assert(pop_fpu_stack || (left_index == dest_index || right_index == dest_index), "invalid LIR");
2362 assert(!pop_fpu_stack || (left_index - 1 == dest_index || right_index - 1 == dest_index), "invalid LIR");
2363 assert(left_index == 0 || right_index == 0, "either must be on top of stack");
2364
2365 bool left_is_tos = (left_index == 0);
2366 bool dest_is_tos = (dest_index == 0);
2367 int non_tos_index = (left_is_tos ? right_index : left_index);
2368
2369 switch (code) {
2370 case lir_add:
2371 if (pop_fpu_stack) __ faddp(non_tos_index);
2372 else if (dest_is_tos) __ fadd (non_tos_index);
2373 else __ fadda(non_tos_index);
2374 break;
2375
2376 case lir_sub:
2377 if (left_is_tos) {
2378 if (pop_fpu_stack) __ fsubrp(non_tos_index);
2379 else if (dest_is_tos) __ fsub (non_tos_index);
2380 else __ fsubra(non_tos_index);
2381 } else {
2382 if (pop_fpu_stack) __ fsubp (non_tos_index);
2383 else if (dest_is_tos) __ fsubr (non_tos_index);
2384 else __ fsuba (non_tos_index);
2385 }
2386 break;
2387
2388 case lir_mul:
2389 if (pop_fpu_stack) __ fmulp(non_tos_index);
2390 else if (dest_is_tos) __ fmul (non_tos_index);
2391 else __ fmula(non_tos_index);
2392 break;
2393
2394 case lir_div:
2395 if (left_is_tos) {
2396 if (pop_fpu_stack) __ fdivrp(non_tos_index);
2397 else if (dest_is_tos) __ fdiv (non_tos_index);
2398 else __ fdivra(non_tos_index);
2399 } else {
2400 if (pop_fpu_stack) __ fdivp (non_tos_index);
2401 else if (dest_is_tos) __ fdivr (non_tos_index);
2402 else __ fdiva (non_tos_index);
2403 }
2404 break;
2405
2406 case lir_rem:
2407 assert(left_is_tos && dest_is_tos && right_index == 1, "must be guaranteed by FPU stack allocation");
2408 __ fremr(noreg);
2409 break;
2410
2411 default:
2412 ShouldNotReachHere();
2413 }
2414 }
2415 #endif // _LP64
2416
2417
2418 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr tmp, LIR_Opr dest, LIR_Op* op) {
2419 if (value->is_double_xmm()) {
2420 switch(code) {
2421 case lir_abs :
2422 {
2423 #ifdef _LP64
2424 if (UseAVX > 2 && !VM_Version::supports_avx512vl()) {
2425 assert(tmp->is_valid(), "need temporary");
2426 __ vpandn(dest->as_xmm_double_reg(), tmp->as_xmm_double_reg(), value->as_xmm_double_reg(), 2);
2427 } else
2428 #endif
2429 {
2430 if (dest->as_xmm_double_reg() != value->as_xmm_double_reg()) {
2431 __ movdbl(dest->as_xmm_double_reg(), value->as_xmm_double_reg());
2432 }
2433 assert(!tmp->is_valid(), "do not need temporary");
2434 __ andpd(dest->as_xmm_double_reg(),
2435 ExternalAddress((address)double_signmask_pool));
2436 }
2437 }
2438 break;
2439
2440 case lir_sqrt: __ sqrtsd(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); break;
2441 // all other intrinsics are not available in the SSE instruction set, so FPU is used
2442 default : ShouldNotReachHere();
2443 }
2444
2445 #ifndef _LP64
2446 } else if (value->is_double_fpu()) {
2447 assert(value->fpu_regnrLo() == 0 && dest->fpu_regnrLo() == 0, "both must be on TOS");
2448 switch(code) {
2449 case lir_abs : __ fabs() ; break;
2450 case lir_sqrt : __ fsqrt(); break;
2451 default : ShouldNotReachHere();
2452 }
2453 #endif // !_LP64
2454 } else {
2455 Unimplemented();
2456 }
2457 }
2458
2459 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) {
2460 // assert(left->destroys_register(), "check");
2461 if (left->is_single_cpu()) {
2462 Register reg = left->as_register();
2463 if (right->is_constant()) {
2464 int val = right->as_constant_ptr()->as_jint();
2465 switch (code) {
2466 case lir_logic_and: __ andl (reg, val); break;
2467 case lir_logic_or: __ orl (reg, val); break;
2468 case lir_logic_xor: __ xorl (reg, val); break;
2469 default: ShouldNotReachHere();
2470 }
2471 } else if (right->is_stack()) {
2472 // added support for stack operands
2473 Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
2474 switch (code) {
2475 case lir_logic_and: __ andl (reg, raddr); break;
2476 case lir_logic_or: __ orl (reg, raddr); break;
2477 case lir_logic_xor: __ xorl (reg, raddr); break;
2478 default: ShouldNotReachHere();
2479 }
2480 } else {
2481 Register rright = right->as_register();
2482 switch (code) {
2483 case lir_logic_and: __ andptr (reg, rright); break;
2484 case lir_logic_or : __ orptr (reg, rright); break;
2485 case lir_logic_xor: __ xorptr (reg, rright); break;
2486 default: ShouldNotReachHere();
2487 }
2488 }
2489 move_regs(reg, dst->as_register());
2490 } else {
2491 Register l_lo = left->as_register_lo();
2492 Register l_hi = left->as_register_hi();
2493 if (right->is_constant()) {
2494 #ifdef _LP64
2495 __ mov64(rscratch1, right->as_constant_ptr()->as_jlong());
2496 switch (code) {
2497 case lir_logic_and:
2498 __ andq(l_lo, rscratch1);
2499 break;
2500 case lir_logic_or:
2501 __ orq(l_lo, rscratch1);
2502 break;
2503 case lir_logic_xor:
2504 __ xorq(l_lo, rscratch1);
2505 break;
2506 default: ShouldNotReachHere();
2507 }
2508 #else
2509 int r_lo = right->as_constant_ptr()->as_jint_lo();
2510 int r_hi = right->as_constant_ptr()->as_jint_hi();
2511 switch (code) {
2512 case lir_logic_and:
2513 __ andl(l_lo, r_lo);
2514 __ andl(l_hi, r_hi);
2515 break;
2516 case lir_logic_or:
2517 __ orl(l_lo, r_lo);
2518 __ orl(l_hi, r_hi);
2519 break;
2520 case lir_logic_xor:
2521 __ xorl(l_lo, r_lo);
2522 __ xorl(l_hi, r_hi);
2523 break;
2524 default: ShouldNotReachHere();
2525 }
2526 #endif // _LP64
2527 } else {
2528 #ifdef _LP64
2529 Register r_lo;
2530 if (is_reference_type(right->type())) {
2531 r_lo = right->as_register();
2532 } else {
2533 r_lo = right->as_register_lo();
2534 }
2535 #else
2536 Register r_lo = right->as_register_lo();
2537 Register r_hi = right->as_register_hi();
2538 assert(l_lo != r_hi, "overwriting registers");
2539 #endif
2540 switch (code) {
2541 case lir_logic_and:
2542 __ andptr(l_lo, r_lo);
2543 NOT_LP64(__ andptr(l_hi, r_hi);)
2544 break;
2545 case lir_logic_or:
2546 __ orptr(l_lo, r_lo);
2547 NOT_LP64(__ orptr(l_hi, r_hi);)
2548 break;
2549 case lir_logic_xor:
2550 __ xorptr(l_lo, r_lo);
2551 NOT_LP64(__ xorptr(l_hi, r_hi);)
2552 break;
2553 default: ShouldNotReachHere();
2554 }
2555 }
2556
2557 Register dst_lo = dst->as_register_lo();
2558 Register dst_hi = dst->as_register_hi();
2559
2560 #ifdef _LP64
2561 move_regs(l_lo, dst_lo);
2562 #else
2563 if (dst_lo == l_hi) {
2564 assert(dst_hi != l_lo, "overwriting registers");
2565 move_regs(l_hi, dst_hi);
2566 move_regs(l_lo, dst_lo);
2567 } else {
2568 assert(dst_lo != l_hi, "overwriting registers");
2569 move_regs(l_lo, dst_lo);
2570 move_regs(l_hi, dst_hi);
2571 }
2572 #endif // _LP64
2573 }
2574 }
2575
2576
2577 // we assume that rax, and rdx can be overwritten
2578 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) {
2579
2580 assert(left->is_single_cpu(), "left must be register");
2581 assert(right->is_single_cpu() || right->is_constant(), "right must be register or constant");
2582 assert(result->is_single_cpu(), "result must be register");
2583
2584 // assert(left->destroys_register(), "check");
2585 // assert(right->destroys_register(), "check");
2586
2587 Register lreg = left->as_register();
2588 Register dreg = result->as_register();
2589
2590 if (right->is_constant()) {
2591 jint divisor = right->as_constant_ptr()->as_jint();
2592 assert(divisor > 0 && is_power_of_2(divisor), "must be");
2593 if (code == lir_idiv) {
2594 assert(lreg == rax, "must be rax,");
2595 assert(temp->as_register() == rdx, "tmp register must be rdx");
2596 __ cdql(); // sign extend into rdx:rax
2597 if (divisor == 2) {
2598 __ subl(lreg, rdx);
2599 } else {
2600 __ andl(rdx, divisor - 1);
2601 __ addl(lreg, rdx);
2602 }
2603 __ sarl(lreg, log2i_exact(divisor));
2604 move_regs(lreg, dreg);
2605 } else if (code == lir_irem) {
2606 Label done;
2607 __ mov(dreg, lreg);
2608 __ andl(dreg, 0x80000000 | (divisor - 1));
2609 __ jcc(Assembler::positive, done);
2610 __ decrement(dreg);
2611 __ orl(dreg, ~(divisor - 1));
2612 __ increment(dreg);
2613 __ bind(done);
2614 } else {
2615 ShouldNotReachHere();
2616 }
2617 } else {
2618 Register rreg = right->as_register();
2619 assert(lreg == rax, "left register must be rax,");
2620 assert(rreg != rdx, "right register must not be rdx");
2621 assert(temp->as_register() == rdx, "tmp register must be rdx");
2622
2623 move_regs(lreg, rax);
2624
2625 int idivl_offset = __ corrected_idivl(rreg);
2626 if (ImplicitDiv0Checks) {
2627 add_debug_info_for_div0(idivl_offset, info);
2628 }
2629 if (code == lir_irem) {
2630 move_regs(rdx, dreg); // result is in rdx
2631 } else {
2632 move_regs(rax, dreg);
2633 }
2634 }
2635 }
2636
2637
2638 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
2639 if (opr1->is_single_cpu()) {
2640 Register reg1 = opr1->as_register();
2641 if (opr2->is_single_cpu()) {
2642 // cpu register - cpu register
2643 if (is_reference_type(opr1->type())) {
2644 __ cmpoop(reg1, opr2->as_register());
2645 } else {
2646 assert(!is_reference_type(opr2->type()), "cmp int, oop?");
2647 __ cmpl(reg1, opr2->as_register());
2648 }
2649 } else if (opr2->is_stack()) {
2650 // cpu register - stack
2651 if (is_reference_type(opr1->type())) {
2652 __ cmpoop(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2653 } else {
2654 __ cmpl(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2655 }
2656 } else if (opr2->is_constant()) {
2657 // cpu register - constant
2658 LIR_Const* c = opr2->as_constant_ptr();
2659 if (c->type() == T_INT) {
2660 __ cmpl(reg1, c->as_jint());
2661 } else if (c->type() == T_METADATA) {
2662 // All we need for now is a comparison with NULL for equality.
2663 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "oops");
2664 Metadata* m = c->as_metadata();
2665 if (m == NULL) {
2666 __ cmpptr(reg1, (int32_t)0);
2667 } else {
2668 ShouldNotReachHere();
2669 }
2670 } else if (is_reference_type(c->type())) {
2671 // In 64bit oops are single register
2672 jobject o = c->as_jobject();
2673 if (o == NULL) {
2674 __ cmpptr(reg1, (int32_t)NULL_WORD);
2675 } else {
2676 __ cmpoop(reg1, o);
2677 }
2678 } else {
2679 fatal("unexpected type: %s", basictype_to_str(c->type()));
2680 }
2681 // cpu register - address
2682 } else if (opr2->is_address()) {
2683 if (op->info() != NULL) {
2684 add_debug_info_for_null_check_here(op->info());
2685 }
2686 __ cmpl(reg1, as_Address(opr2->as_address_ptr()));
2687 } else {
2688 ShouldNotReachHere();
2689 }
2690
2691 } else if(opr1->is_double_cpu()) {
2692 Register xlo = opr1->as_register_lo();
2693 Register xhi = opr1->as_register_hi();
2694 if (opr2->is_double_cpu()) {
2695 #ifdef _LP64
2696 __ cmpptr(xlo, opr2->as_register_lo());
2697 #else
2698 // cpu register - cpu register
2699 Register ylo = opr2->as_register_lo();
2700 Register yhi = opr2->as_register_hi();
2701 __ subl(xlo, ylo);
2702 __ sbbl(xhi, yhi);
2703 if (condition == lir_cond_equal || condition == lir_cond_notEqual) {
2704 __ orl(xhi, xlo);
2705 }
2706 #endif // _LP64
2707 } else if (opr2->is_constant()) {
2708 // cpu register - constant 0
2709 assert(opr2->as_jlong() == (jlong)0, "only handles zero");
2710 #ifdef _LP64
2711 __ cmpptr(xlo, (int32_t)opr2->as_jlong());
2712 #else
2713 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles equals case");
2714 __ orl(xhi, xlo);
2715 #endif // _LP64
2716 } else {
2717 ShouldNotReachHere();
2718 }
2719
2720 } else if (opr1->is_single_xmm()) {
2721 XMMRegister reg1 = opr1->as_xmm_float_reg();
2722 if (opr2->is_single_xmm()) {
2723 // xmm register - xmm register
2724 __ ucomiss(reg1, opr2->as_xmm_float_reg());
2725 } else if (opr2->is_stack()) {
2726 // xmm register - stack
2727 __ ucomiss(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2728 } else if (opr2->is_constant()) {
2729 // xmm register - constant
2730 __ ucomiss(reg1, InternalAddress(float_constant(opr2->as_jfloat())));
2731 } else if (opr2->is_address()) {
2732 // xmm register - address
2733 if (op->info() != NULL) {
2734 add_debug_info_for_null_check_here(op->info());
2735 }
2736 __ ucomiss(reg1, as_Address(opr2->as_address_ptr()));
2737 } else {
2738 ShouldNotReachHere();
2739 }
2740
2741 } else if (opr1->is_double_xmm()) {
2742 XMMRegister reg1 = opr1->as_xmm_double_reg();
2743 if (opr2->is_double_xmm()) {
2744 // xmm register - xmm register
2745 __ ucomisd(reg1, opr2->as_xmm_double_reg());
2746 } else if (opr2->is_stack()) {
2747 // xmm register - stack
2748 __ ucomisd(reg1, frame_map()->address_for_slot(opr2->double_stack_ix()));
2749 } else if (opr2->is_constant()) {
2750 // xmm register - constant
2751 __ ucomisd(reg1, InternalAddress(double_constant(opr2->as_jdouble())));
2752 } else if (opr2->is_address()) {
2753 // xmm register - address
2754 if (op->info() != NULL) {
2755 add_debug_info_for_null_check_here(op->info());
2756 }
2757 __ ucomisd(reg1, as_Address(opr2->pointer()->as_address()));
2758 } else {
2759 ShouldNotReachHere();
2760 }
2761
2762 #ifndef _LP64
2763 } else if(opr1->is_single_fpu() || opr1->is_double_fpu()) {
2764 assert(opr1->is_fpu_register() && opr1->fpu() == 0, "currently left-hand side must be on TOS (relax this restriction)");
2765 assert(opr2->is_fpu_register(), "both must be registers");
2766 __ fcmp(noreg, opr2->fpu(), op->fpu_pop_count() > 0, op->fpu_pop_count() > 1);
2767 #endif // LP64
2768
2769 } else if (opr1->is_address() && opr2->is_constant()) {
2770 LIR_Const* c = opr2->as_constant_ptr();
2771 #ifdef _LP64
2772 if (is_reference_type(c->type())) {
2773 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "need to reverse");
2774 __ movoop(rscratch1, c->as_jobject());
2775 }
2776 #endif // LP64
2777 if (op->info() != NULL) {
2778 add_debug_info_for_null_check_here(op->info());
2779 }
2780 // special case: address - constant
2781 LIR_Address* addr = opr1->as_address_ptr();
2782 if (c->type() == T_INT) {
2783 __ cmpl(as_Address(addr), c->as_jint());
2784 } else if (is_reference_type(c->type())) {
2785 #ifdef _LP64
2786 // %%% Make this explode if addr isn't reachable until we figure out a
2787 // better strategy by giving noreg as the temp for as_Address
2788 __ cmpoop(rscratch1, as_Address(addr, noreg));
2789 #else
2790 __ cmpoop(as_Address(addr), c->as_jobject());
2791 #endif // _LP64
2792 } else {
2793 ShouldNotReachHere();
2794 }
2795
2796 } else {
2797 ShouldNotReachHere();
2798 }
2799 }
2800
2801 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op) {
2802 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
2803 if (left->is_single_xmm()) {
2804 assert(right->is_single_xmm(), "must match");
2805 __ cmpss2int(left->as_xmm_float_reg(), right->as_xmm_float_reg(), dst->as_register(), code == lir_ucmp_fd2i);
2806 } else if (left->is_double_xmm()) {
2807 assert(right->is_double_xmm(), "must match");
2808 __ cmpsd2int(left->as_xmm_double_reg(), right->as_xmm_double_reg(), dst->as_register(), code == lir_ucmp_fd2i);
2809
2810 } else {
2811 #ifdef _LP64
2812 ShouldNotReachHere();
2813 #else
2814 assert(left->is_single_fpu() || left->is_double_fpu(), "must be");
2815 assert(right->is_single_fpu() || right->is_double_fpu(), "must match");
2816
2817 assert(left->fpu() == 0, "left must be on TOS");
2818 __ fcmp2int(dst->as_register(), code == lir_ucmp_fd2i, right->fpu(),
2819 op->fpu_pop_count() > 0, op->fpu_pop_count() > 1);
2820 #endif // LP64
2821 }
2822 } else {
2823 assert(code == lir_cmp_l2i, "check");
2824 #ifdef _LP64
2825 Label done;
2826 Register dest = dst->as_register();
2827 __ cmpptr(left->as_register_lo(), right->as_register_lo());
2828 __ movl(dest, -1);
2829 __ jccb(Assembler::less, done);
2830 __ set_byte_if_not_zero(dest);
2831 __ movzbl(dest, dest);
2832 __ bind(done);
2833 #else
2834 __ lcmp2int(left->as_register_hi(),
2835 left->as_register_lo(),
2836 right->as_register_hi(),
2837 right->as_register_lo());
2838 move_regs(left->as_register_hi(), dst->as_register());
2839 #endif // _LP64
2840 }
2841 }
2842
2843
2844 void LIR_Assembler::align_call(LIR_Code code) {
2845 // make sure that the displacement word of the call ends up word aligned
2846 int offset = __ offset();
2847 switch (code) {
2848 case lir_static_call:
2849 case lir_optvirtual_call:
2850 case lir_dynamic_call:
2851 offset += NativeCall::displacement_offset;
2852 break;
2853 case lir_icvirtual_call:
2854 offset += NativeCall::displacement_offset + NativeMovConstReg::instruction_size;
2855 break;
2856 default: ShouldNotReachHere();
2857 }
2858 __ align(BytesPerWord, offset);
2859 }
2860
2861
2862 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
2863 assert((__ offset() + NativeCall::displacement_offset) % BytesPerWord == 0,
2864 "must be aligned");
2865 __ call(AddressLiteral(op->addr(), rtype));
2866 add_call_info(code_offset(), op->info());
2867 __ post_call_nop();
2868 }
2869
2870
2871 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
2872 __ ic_call(op->addr());
2873 add_call_info(code_offset(), op->info());
2874 assert((__ offset() - NativeCall::instruction_size + NativeCall::displacement_offset) % BytesPerWord == 0,
2875 "must be aligned");
2876 __ post_call_nop();
2877 }
2878
2879
2880 void LIR_Assembler::emit_static_call_stub() {
2881 address call_pc = __ pc();
2882 address stub = __ start_a_stub(call_stub_size());
2883 if (stub == NULL) {
2884 bailout("static call stub overflow");
2885 return;
2886 }
2887
2888 int start = __ offset();
2889
2890 // make sure that the displacement word of the call ends up word aligned
2891 __ align(BytesPerWord, __ offset() + NativeMovConstReg::instruction_size + NativeCall::displacement_offset);
2892 __ relocate(static_stub_Relocation::spec(call_pc));
2893 __ mov_metadata(rbx, (Metadata*)NULL);
2894 // must be set to -1 at code generation time
2895 assert(((__ offset() + 1) % BytesPerWord) == 0, "must be aligned");
2896 // On 64bit this will die since it will take a movq & jmp, must be only a jmp
2897 __ jump(RuntimeAddress(__ pc()));
2898
2899 assert(__ offset() - start <= call_stub_size(), "stub too big");
2900 __ end_a_stub();
2901 }
2902
2903
2904 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
2905 assert(exceptionOop->as_register() == rax, "must match");
2906 assert(exceptionPC->as_register() == rdx, "must match");
2907
2908 // exception object is not added to oop map by LinearScan
2909 // (LinearScan assumes that no oops are in fixed registers)
2910 info->add_register_oop(exceptionOop);
2911 Runtime1::StubID unwind_id;
2912
2913 // get current pc information
2914 // pc is only needed if the method has an exception handler, the unwind code does not need it.
2915 int pc_for_athrow_offset = __ offset();
2916 InternalAddress pc_for_athrow(__ pc());
2917 __ lea(exceptionPC->as_register(), pc_for_athrow);
2918 add_call_info(pc_for_athrow_offset, info); // for exception handler
2919
2920 __ verify_not_null_oop(rax);
2921 // search an exception handler (rax: exception oop, rdx: throwing pc)
2922 if (compilation()->has_fpu_code()) {
2923 unwind_id = Runtime1::handle_exception_id;
2924 } else {
2925 unwind_id = Runtime1::handle_exception_nofpu_id;
2926 }
2927 __ call(RuntimeAddress(Runtime1::entry_for(unwind_id)));
2928
2929 // enough room for two byte trap
2930 __ nop();
2931 }
2932
2933
2934 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
2935 assert(exceptionOop->as_register() == rax, "must match");
2936
2937 __ jmp(_unwind_handler_entry);
2938 }
2939
2940
2941 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2942
2943 // optimized version for linear scan:
2944 // * count must be already in ECX (guaranteed by LinearScan)
2945 // * left and dest must be equal
2946 // * tmp must be unused
2947 assert(count->as_register() == SHIFT_count, "count must be in ECX");
2948 assert(left == dest, "left and dest must be equal");
2949 assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2950
2951 if (left->is_single_cpu()) {
2952 Register value = left->as_register();
2953 assert(value != SHIFT_count, "left cannot be ECX");
2954
2955 switch (code) {
2956 case lir_shl: __ shll(value); break;
2957 case lir_shr: __ sarl(value); break;
2958 case lir_ushr: __ shrl(value); break;
2959 default: ShouldNotReachHere();
2960 }
2961 } else if (left->is_double_cpu()) {
2962 Register lo = left->as_register_lo();
2963 Register hi = left->as_register_hi();
2964 assert(lo != SHIFT_count && hi != SHIFT_count, "left cannot be ECX");
2965 #ifdef _LP64
2966 switch (code) {
2967 case lir_shl: __ shlptr(lo); break;
2968 case lir_shr: __ sarptr(lo); break;
2969 case lir_ushr: __ shrptr(lo); break;
2970 default: ShouldNotReachHere();
2971 }
2972 #else
2973
2974 switch (code) {
2975 case lir_shl: __ lshl(hi, lo); break;
2976 case lir_shr: __ lshr(hi, lo, true); break;
2977 case lir_ushr: __ lshr(hi, lo, false); break;
2978 default: ShouldNotReachHere();
2979 }
2980 #endif // LP64
2981 } else {
2982 ShouldNotReachHere();
2983 }
2984 }
2985
2986
2987 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2988 if (dest->is_single_cpu()) {
2989 // first move left into dest so that left is not destroyed by the shift
2990 Register value = dest->as_register();
2991 count = count & 0x1F; // Java spec
2992
2993 move_regs(left->as_register(), value);
2994 switch (code) {
2995 case lir_shl: __ shll(value, count); break;
2996 case lir_shr: __ sarl(value, count); break;
2997 case lir_ushr: __ shrl(value, count); break;
2998 default: ShouldNotReachHere();
2999 }
3000 } else if (dest->is_double_cpu()) {
3001 #ifndef _LP64
3002 Unimplemented();
3003 #else
3004 // first move left into dest so that left is not destroyed by the shift
3005 Register value = dest->as_register_lo();
3006 count = count & 0x1F; // Java spec
3007
3008 move_regs(left->as_register_lo(), value);
3009 switch (code) {
3010 case lir_shl: __ shlptr(value, count); break;
3011 case lir_shr: __ sarptr(value, count); break;
3012 case lir_ushr: __ shrptr(value, count); break;
3013 default: ShouldNotReachHere();
3014 }
3015 #endif // _LP64
3016 } else {
3017 ShouldNotReachHere();
3018 }
3019 }
3020
3021
3022 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) {
3023 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3024 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3025 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3026 __ movptr (Address(rsp, offset_from_rsp_in_bytes), r);
3027 }
3028
3029
3030 void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) {
3031 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3032 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3033 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3034 __ movptr (Address(rsp, offset_from_rsp_in_bytes), c);
3035 }
3036
3037
3038 void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) {
3039 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3040 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3041 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3042 __ movoop (Address(rsp, offset_from_rsp_in_bytes), o);
3043 }
3044
3045
3046 void LIR_Assembler::store_parameter(Metadata* m, int offset_from_rsp_in_words) {
3047 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3048 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3049 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3050 __ mov_metadata(Address(rsp, offset_from_rsp_in_bytes), m);
3051 }
3052
3053
3054 // This code replaces a call to arraycopy; no exception may
3055 // be thrown in this code, they must be thrown in the System.arraycopy
3056 // activation frame; we could save some checks if this would not be the case
3057 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
3058 ciArrayKlass* default_type = op->expected_type();
3059 Register src = op->src()->as_register();
3060 Register dst = op->dst()->as_register();
3061 Register src_pos = op->src_pos()->as_register();
3062 Register dst_pos = op->dst_pos()->as_register();
3063 Register length = op->length()->as_register();
3064 Register tmp = op->tmp()->as_register();
3065 Register tmp_load_klass = LP64_ONLY(rscratch1) NOT_LP64(noreg);
3066
3067 CodeStub* stub = op->stub();
3068 int flags = op->flags();
3069 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL;
3070 if (is_reference_type(basic_type)) basic_type = T_OBJECT;
3071
3072 // if we don't know anything, just go through the generic arraycopy
3073 if (default_type == NULL) {
3074 // save outgoing arguments on stack in case call to System.arraycopy is needed
3075 // HACK ALERT. This code used to push the parameters in a hardwired fashion
3076 // for interpreter calling conventions. Now we have to do it in new style conventions.
3077 // For the moment until C1 gets the new register allocator I just force all the
3078 // args to the right place (except the register args) and then on the back side
3079 // reload the register args properly if we go slow path. Yuck
3080
3081 // These are proper for the calling convention
3082 store_parameter(length, 2);
3083 store_parameter(dst_pos, 1);
3084 store_parameter(dst, 0);
3085
3086 // these are just temporary placements until we need to reload
3087 store_parameter(src_pos, 3);
3088 store_parameter(src, 4);
3089 NOT_LP64(assert(src == rcx && src_pos == rdx, "mismatch in calling convention");)
3090
3091 address copyfunc_addr = StubRoutines::generic_arraycopy();
3092 assert(copyfunc_addr != NULL, "generic arraycopy stub required");
3093
3094 // pass arguments: may push as this is not a safepoint; SP must be fix at each safepoint
3095 #ifdef _LP64
3096 // The arguments are in java calling convention so we can trivially shift them to C
3097 // convention
3098 assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4);
3099 __ mov(c_rarg0, j_rarg0);
3100 assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4);
3101 __ mov(c_rarg1, j_rarg1);
3102 assert_different_registers(c_rarg2, j_rarg3, j_rarg4);
3103 __ mov(c_rarg2, j_rarg2);
3104 assert_different_registers(c_rarg3, j_rarg4);
3105 __ mov(c_rarg3, j_rarg3);
3106 #ifdef _WIN64
3107 // Allocate abi space for args but be sure to keep stack aligned
3108 __ subptr(rsp, 6*wordSize);
3109 store_parameter(j_rarg4, 4);
3110 #ifndef PRODUCT
3111 if (PrintC1Statistics) {
3112 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
3113 }
3114 #endif
3115 __ call(RuntimeAddress(copyfunc_addr));
3116 __ addptr(rsp, 6*wordSize);
3117 #else
3118 __ mov(c_rarg4, j_rarg4);
3119 #ifndef PRODUCT
3120 if (PrintC1Statistics) {
3121 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
3122 }
3123 #endif
3124 __ call(RuntimeAddress(copyfunc_addr));
3125 #endif // _WIN64
3126 #else
3127 __ push(length);
3128 __ push(dst_pos);
3129 __ push(dst);
3130 __ push(src_pos);
3131 __ push(src);
3132
3133 #ifndef PRODUCT
3134 if (PrintC1Statistics) {
3135 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
3136 }
3137 #endif
3138 __ call_VM_leaf(copyfunc_addr, 5); // removes pushed parameter from the stack
3139
3140 #endif // _LP64
3141
3142 __ cmpl(rax, 0);
3143 __ jcc(Assembler::equal, *stub->continuation());
3144
3145 __ mov(tmp, rax);
3146 __ xorl(tmp, -1);
3147
3148 // Reload values from the stack so they are where the stub
3149 // expects them.
3150 __ movptr (dst, Address(rsp, 0*BytesPerWord));
3151 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord));
3152 __ movptr (length, Address(rsp, 2*BytesPerWord));
3153 __ movptr (src_pos, Address(rsp, 3*BytesPerWord));
3154 __ movptr (src, Address(rsp, 4*BytesPerWord));
3155
3156 __ subl(length, tmp);
3157 __ addl(src_pos, tmp);
3158 __ addl(dst_pos, tmp);
3159 __ jmp(*stub->entry());
3160
3161 __ bind(*stub->continuation());
3162 return;
3163 }
3164
3165 assert(default_type != NULL && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
3166
3167 int elem_size = type2aelembytes(basic_type);
3168 Address::ScaleFactor scale;
3169
3170 switch (elem_size) {
3171 case 1 :
3172 scale = Address::times_1;
3173 break;
3174 case 2 :
3175 scale = Address::times_2;
3176 break;
3177 case 4 :
3178 scale = Address::times_4;
3179 break;
3180 case 8 :
3181 scale = Address::times_8;
3182 break;
3183 default:
3184 scale = Address::no_scale;
3185 ShouldNotReachHere();
3186 }
3187
3188 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes());
3189 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes());
3190 Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes());
3191 Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes());
3192
3193 // length and pos's are all sign extended at this point on 64bit
3194
3195 // test for NULL
3196 if (flags & LIR_OpArrayCopy::src_null_check) {
3197 __ testptr(src, src);
3198 __ jcc(Assembler::zero, *stub->entry());
3199 }
3200 if (flags & LIR_OpArrayCopy::dst_null_check) {
3201 __ testptr(dst, dst);
3202 __ jcc(Assembler::zero, *stub->entry());
3203 }
3204
3205 // If the compiler was not able to prove that exact type of the source or the destination
3206 // of the arraycopy is an array type, check at runtime if the source or the destination is
3207 // an instance type.
3208 if (flags & LIR_OpArrayCopy::type_check) {
3209 if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
3210 __ load_klass(tmp, dst, tmp_load_klass);
3211 __ cmpl(Address(tmp, in_bytes(Klass::layout_helper_offset())), Klass::_lh_neutral_value);
3212 __ jcc(Assembler::greaterEqual, *stub->entry());
3213 }
3214
3215 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
3216 __ load_klass(tmp, src, tmp_load_klass);
3217 __ cmpl(Address(tmp, in_bytes(Klass::layout_helper_offset())), Klass::_lh_neutral_value);
3218 __ jcc(Assembler::greaterEqual, *stub->entry());
3219 }
3220 }
3221
3222 // check if negative
3223 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
3224 __ testl(src_pos, src_pos);
3225 __ jcc(Assembler::less, *stub->entry());
3226 }
3227 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
3228 __ testl(dst_pos, dst_pos);
3229 __ jcc(Assembler::less, *stub->entry());
3230 }
3231
3232 if (flags & LIR_OpArrayCopy::src_range_check) {
3233 __ lea(tmp, Address(src_pos, length, Address::times_1, 0));
3234 __ cmpl(tmp, src_length_addr);
3235 __ jcc(Assembler::above, *stub->entry());
3236 }
3237 if (flags & LIR_OpArrayCopy::dst_range_check) {
3238 __ lea(tmp, Address(dst_pos, length, Address::times_1, 0));
3239 __ cmpl(tmp, dst_length_addr);
3240 __ jcc(Assembler::above, *stub->entry());
3241 }
3242
3243 if (flags & LIR_OpArrayCopy::length_positive_check) {
3244 __ testl(length, length);
3245 __ jcc(Assembler::less, *stub->entry());
3246 }
3247
3248 #ifdef _LP64
3249 __ movl2ptr(src_pos, src_pos); //higher 32bits must be null
3250 __ movl2ptr(dst_pos, dst_pos); //higher 32bits must be null
3251 #endif
3252
3253 if (flags & LIR_OpArrayCopy::type_check) {
3254 // We don't know the array types are compatible
3255 if (basic_type != T_OBJECT) {
3256 // Simple test for basic type arrays
3257 if (UseCompressedClassPointers) {
3258 __ movl(tmp, src_klass_addr);
3259 __ cmpl(tmp, dst_klass_addr);
3260 } else {
3261 __ movptr(tmp, src_klass_addr);
3262 __ cmpptr(tmp, dst_klass_addr);
3263 }
3264 __ jcc(Assembler::notEqual, *stub->entry());
3265 } else {
3266 // For object arrays, if src is a sub class of dst then we can
3267 // safely do the copy.
3268 Label cont, slow;
3269
3270 __ push(src);
3271 __ push(dst);
3272
3273 __ load_klass(src, src, tmp_load_klass);
3274 __ load_klass(dst, dst, tmp_load_klass);
3275
3276 __ check_klass_subtype_fast_path(src, dst, tmp, &cont, &slow, NULL);
3277
3278 __ push(src);
3279 __ push(dst);
3280 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
3281 __ pop(dst);
3282 __ pop(src);
3283
3284 __ cmpl(src, 0);
3285 __ jcc(Assembler::notEqual, cont);
3286
3287 __ bind(slow);
3288 __ pop(dst);
3289 __ pop(src);
3290
3291 address copyfunc_addr = StubRoutines::checkcast_arraycopy();
3292 if (copyfunc_addr != NULL) { // use stub if available
3293 // src is not a sub class of dst so we have to do a
3294 // per-element check.
3295
3296 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
3297 if ((flags & mask) != mask) {
3298 // Check that at least both of them object arrays.
3299 assert(flags & mask, "one of the two should be known to be an object array");
3300
3301 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
3302 __ load_klass(tmp, src, tmp_load_klass);
3303 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
3304 __ load_klass(tmp, dst, tmp_load_klass);
3305 }
3306 int lh_offset = in_bytes(Klass::layout_helper_offset());
3307 Address klass_lh_addr(tmp, lh_offset);
3308 jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
3309 __ cmpl(klass_lh_addr, objArray_lh);
3310 __ jcc(Assembler::notEqual, *stub->entry());
3311 }
3312
3313 // Spill because stubs can use any register they like and it's
3314 // easier to restore just those that we care about.
3315 store_parameter(dst, 0);
3316 store_parameter(dst_pos, 1);
3317 store_parameter(length, 2);
3318 store_parameter(src_pos, 3);
3319 store_parameter(src, 4);
3320
3321 #ifndef _LP64
3322 __ movptr(tmp, dst_klass_addr);
3323 __ movptr(tmp, Address(tmp, ObjArrayKlass::element_klass_offset()));
3324 __ push(tmp);
3325 __ movl(tmp, Address(tmp, Klass::super_check_offset_offset()));
3326 __ push(tmp);
3327 __ push(length);
3328 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3329 __ push(tmp);
3330 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3331 __ push(tmp);
3332
3333 __ call_VM_leaf(copyfunc_addr, 5);
3334 #else
3335 __ movl2ptr(length, length); //higher 32bits must be null
3336
3337 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3338 assert_different_registers(c_rarg0, dst, dst_pos, length);
3339 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3340 assert_different_registers(c_rarg1, dst, length);
3341
3342 __ mov(c_rarg2, length);
3343 assert_different_registers(c_rarg2, dst);
3344
3345 #ifdef _WIN64
3346 // Allocate abi space for args but be sure to keep stack aligned
3347 __ subptr(rsp, 6*wordSize);
3348 __ load_klass(c_rarg3, dst, tmp_load_klass);
3349 __ movptr(c_rarg3, Address(c_rarg3, ObjArrayKlass::element_klass_offset()));
3350 store_parameter(c_rarg3, 4);
3351 __ movl(c_rarg3, Address(c_rarg3, Klass::super_check_offset_offset()));
3352 __ call(RuntimeAddress(copyfunc_addr));
3353 __ addptr(rsp, 6*wordSize);
3354 #else
3355 __ load_klass(c_rarg4, dst, tmp_load_klass);
3356 __ movptr(c_rarg4, Address(c_rarg4, ObjArrayKlass::element_klass_offset()));
3357 __ movl(c_rarg3, Address(c_rarg4, Klass::super_check_offset_offset()));
3358 __ call(RuntimeAddress(copyfunc_addr));
3359 #endif
3360
3361 #endif
3362
3363 #ifndef PRODUCT
3364 if (PrintC1Statistics) {
3365 Label failed;
3366 __ testl(rax, rax);
3367 __ jcc(Assembler::notZero, failed);
3368 __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt));
3369 __ bind(failed);
3370 }
3371 #endif
3372
3373 __ testl(rax, rax);
3374 __ jcc(Assembler::zero, *stub->continuation());
3375
3376 #ifndef PRODUCT
3377 if (PrintC1Statistics) {
3378 __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt));
3379 }
3380 #endif
3381
3382 __ mov(tmp, rax);
3383
3384 __ xorl(tmp, -1);
3385
3386 // Restore previously spilled arguments
3387 __ movptr (dst, Address(rsp, 0*BytesPerWord));
3388 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord));
3389 __ movptr (length, Address(rsp, 2*BytesPerWord));
3390 __ movptr (src_pos, Address(rsp, 3*BytesPerWord));
3391 __ movptr (src, Address(rsp, 4*BytesPerWord));
3392
3393
3394 __ subl(length, tmp);
3395 __ addl(src_pos, tmp);
3396 __ addl(dst_pos, tmp);
3397 }
3398
3399 __ jmp(*stub->entry());
3400
3401 __ bind(cont);
3402 __ pop(dst);
3403 __ pop(src);
3404 }
3405 }
3406
3407 #ifdef ASSERT
3408 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
3409 // Sanity check the known type with the incoming class. For the
3410 // primitive case the types must match exactly with src.klass and
3411 // dst.klass each exactly matching the default type. For the
3412 // object array case, if no type check is needed then either the
3413 // dst type is exactly the expected type and the src type is a
3414 // subtype which we can't check or src is the same array as dst
3415 // but not necessarily exactly of type default_type.
3416 Label known_ok, halt;
3417 __ mov_metadata(tmp, default_type->constant_encoding());
3418 #ifdef _LP64
3419 if (UseCompressedClassPointers) {
3420 __ encode_klass_not_null(tmp, rscratch1);
3421 }
3422 #endif
3423
3424 if (basic_type != T_OBJECT) {
3425
3426 if (UseCompressedClassPointers) __ cmpl(tmp, dst_klass_addr);
3427 else __ cmpptr(tmp, dst_klass_addr);
3428 __ jcc(Assembler::notEqual, halt);
3429 if (UseCompressedClassPointers) __ cmpl(tmp, src_klass_addr);
3430 else __ cmpptr(tmp, src_klass_addr);
3431 __ jcc(Assembler::equal, known_ok);
3432 } else {
3433 if (UseCompressedClassPointers) __ cmpl(tmp, dst_klass_addr);
3434 else __ cmpptr(tmp, dst_klass_addr);
3435 __ jcc(Assembler::equal, known_ok);
3436 __ cmpptr(src, dst);
3437 __ jcc(Assembler::equal, known_ok);
3438 }
3439 __ bind(halt);
3440 __ stop("incorrect type information in arraycopy");
3441 __ bind(known_ok);
3442 }
3443 #endif
3444
3445 #ifndef PRODUCT
3446 if (PrintC1Statistics) {
3447 __ incrementl(ExternalAddress(Runtime1::arraycopy_count_address(basic_type)));
3448 }
3449 #endif
3450
3451 #ifdef _LP64
3452 assert_different_registers(c_rarg0, dst, dst_pos, length);
3453 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3454 assert_different_registers(c_rarg1, length);
3455 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3456 __ mov(c_rarg2, length);
3457
3458 #else
3459 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3460 store_parameter(tmp, 0);
3461 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3462 store_parameter(tmp, 1);
3463 store_parameter(length, 2);
3464 #endif // _LP64
3465
3466 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
3467 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
3468 const char *name;
3469 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
3470 __ call_VM_leaf(entry, 0);
3471
3472 __ bind(*stub->continuation());
3473 }
3474
3475 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
3476 assert(op->crc()->is_single_cpu(), "crc must be register");
3477 assert(op->val()->is_single_cpu(), "byte value must be register");
3478 assert(op->result_opr()->is_single_cpu(), "result must be register");
3479 Register crc = op->crc()->as_register();
3480 Register val = op->val()->as_register();
3481 Register res = op->result_opr()->as_register();
3482
3483 assert_different_registers(val, crc, res);
3484
3485 __ lea(res, ExternalAddress(StubRoutines::crc_table_addr()));
3486 __ notl(crc); // ~crc
3487 __ update_byte_crc32(crc, val, res);
3488 __ notl(crc); // ~crc
3489 __ mov(res, crc);
3490 }
3491
3492 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
3493 Register obj = op->obj_opr()->as_register(); // may not be an oop
3494 Register hdr = op->hdr_opr()->as_register();
3495 Register lock = op->lock_opr()->as_register();
3496 if (UseHeavyMonitors) {
3497 if (op->info() != NULL) {
3498 add_debug_info_for_null_check_here(op->info());
3499 __ null_check(obj);
3500 }
3501 __ jmp(*op->stub()->entry());
3502 } else if (op->code() == lir_lock) {
3503 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
3504 // add debug info for NullPointerException only if one is possible
3505 int null_check_offset = __ lock_object(hdr, obj, lock, *op->stub()->entry());
3506 if (op->info() != NULL) {
3507 add_debug_info_for_null_check(null_check_offset, op->info());
3508 }
3509 // done
3510 } else if (op->code() == lir_unlock) {
3511 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
3512 __ unlock_object(hdr, obj, lock, *op->stub()->entry());
3513 } else {
3514 Unimplemented();
3515 }
3516 __ bind(*op->stub()->continuation());
3517 }
3518
3519 void LIR_Assembler::emit_load_klass(LIR_OpLoadKlass* op) {
3520 Register obj = op->obj()->as_pointer_register();
3521 Register result = op->result_opr()->as_pointer_register();
3522
3523 CodeEmitInfo* info = op->info();
3524 if (info != NULL) {
3525 add_debug_info_for_null_check_here(info);
3526 }
3527
3528 #ifdef _LP64
3529 if (UseCompressedClassPointers) {
3530 __ movl(result, Address(obj, oopDesc::klass_offset_in_bytes()));
3531 __ decode_klass_not_null(result, rscratch1);
3532 } else
3533 #endif
3534 __ movptr(result, Address(obj, oopDesc::klass_offset_in_bytes()));
3535 }
3536
3537 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
3538 ciMethod* method = op->profiled_method();
3539 int bci = op->profiled_bci();
3540 ciMethod* callee = op->profiled_callee();
3541 Register tmp_load_klass = LP64_ONLY(rscratch1) NOT_LP64(noreg);
3542
3543 // Update counter for all call types
3544 ciMethodData* md = method->method_data_or_null();
3545 assert(md != NULL, "Sanity");
3546 ciProfileData* data = md->bci_to_data(bci);
3547 assert(data != NULL && data->is_CounterData(), "need CounterData for calls");
3548 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
3549 Register mdo = op->mdo()->as_register();
3550 __ mov_metadata(mdo, md->constant_encoding());
3551 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
3552 // Perform additional virtual call profiling for invokevirtual and
3553 // invokeinterface bytecodes
3554 if (op->should_profile_receiver_type()) {
3555 assert(op->recv()->is_single_cpu(), "recv must be allocated");
3556 Register recv = op->recv()->as_register();
3557 assert_different_registers(mdo, recv);
3558 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
3559 ciKlass* known_klass = op->known_holder();
3560 if (C1OptimizeVirtualCallProfiling && known_klass != NULL) {
3561 // We know the type that will be seen at this call site; we can
3562 // statically update the MethodData* rather than needing to do
3563 // dynamic tests on the receiver type
3564
3565 // NOTE: we should probably put a lock around this search to
3566 // avoid collisions by concurrent compilations
3567 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
3568 uint i;
3569 for (i = 0; i < VirtualCallData::row_limit(); i++) {
3570 ciKlass* receiver = vc_data->receiver(i);
3571 if (known_klass->equals(receiver)) {
3572 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
3573 __ addptr(data_addr, DataLayout::counter_increment);
3574 return;
3575 }
3576 }
3577
3578 // Receiver type not found in profile data; select an empty slot
3579
3580 // Note that this is less efficient than it should be because it
3581 // always does a write to the receiver part of the
3582 // VirtualCallData rather than just the first time
3583 for (i = 0; i < VirtualCallData::row_limit(); i++) {
3584 ciKlass* receiver = vc_data->receiver(i);
3585 if (receiver == NULL) {
3586 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)));
3587 __ mov_metadata(recv_addr, known_klass->constant_encoding());
3588 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
3589 __ addptr(data_addr, DataLayout::counter_increment);
3590 return;
3591 }
3592 }
3593 } else {
3594 __ load_klass(recv, recv, tmp_load_klass);
3595 Label update_done;
3596 type_profile_helper(mdo, md, data, recv, &update_done);
3597 // Receiver did not match any saved receiver and there is no empty row for it.
3598 // Increment total counter to indicate polymorphic case.
3599 __ addptr(counter_addr, DataLayout::counter_increment);
3600
3601 __ bind(update_done);
3602 }
3603 } else {
3604 // Static call
3605 __ addptr(counter_addr, DataLayout::counter_increment);
3606 }
3607 }
3608
3609 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
3610 Register obj = op->obj()->as_register();
3611 Register tmp = op->tmp()->as_pointer_register();
3612 Register tmp_load_klass = LP64_ONLY(rscratch1) NOT_LP64(noreg);
3613 Address mdo_addr = as_Address(op->mdp()->as_address_ptr());
3614 ciKlass* exact_klass = op->exact_klass();
3615 intptr_t current_klass = op->current_klass();
3616 bool not_null = op->not_null();
3617 bool no_conflict = op->no_conflict();
3618
3619 Label update, next, none;
3620
3621 bool do_null = !not_null;
3622 bool exact_klass_set = exact_klass != NULL && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
3623 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
3624
3625 assert(do_null || do_update, "why are we here?");
3626 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
3627
3628 __ verify_oop(obj);
3629
3630 if (tmp != obj) {
3631 __ mov(tmp, obj);
3632 }
3633 if (do_null) {
3634 __ testptr(tmp, tmp);
3635 __ jccb(Assembler::notZero, update);
3636 if (!TypeEntries::was_null_seen(current_klass)) {
3637 __ orptr(mdo_addr, TypeEntries::null_seen);
3638 }
3639 if (do_update) {
3640 #ifndef ASSERT
3641 __ jmpb(next);
3642 }
3643 #else
3644 __ jmp(next);
3645 }
3646 } else {
3647 __ testptr(tmp, tmp);
3648 __ jcc(Assembler::notZero, update);
3649 __ stop("unexpected null obj");
3650 #endif
3651 }
3652
3653 __ bind(update);
3654
3655 if (do_update) {
3656 #ifdef ASSERT
3657 if (exact_klass != NULL) {
3658 Label ok;
3659 __ load_klass(tmp, tmp, tmp_load_klass);
3660 __ push(tmp);
3661 __ mov_metadata(tmp, exact_klass->constant_encoding());
3662 __ cmpptr(tmp, Address(rsp, 0));
3663 __ jcc(Assembler::equal, ok);
3664 __ stop("exact klass and actual klass differ");
3665 __ bind(ok);
3666 __ pop(tmp);
3667 }
3668 #endif
3669 if (!no_conflict) {
3670 if (exact_klass == NULL || TypeEntries::is_type_none(current_klass)) {
3671 if (exact_klass != NULL) {
3672 __ mov_metadata(tmp, exact_klass->constant_encoding());
3673 } else {
3674 __ load_klass(tmp, tmp, tmp_load_klass);
3675 }
3676
3677 __ xorptr(tmp, mdo_addr);
3678 __ testptr(tmp, TypeEntries::type_klass_mask);
3679 // klass seen before, nothing to do. The unknown bit may have been
3680 // set already but no need to check.
3681 __ jccb(Assembler::zero, next);
3682
3683 __ testptr(tmp, TypeEntries::type_unknown);
3684 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3685
3686 if (TypeEntries::is_type_none(current_klass)) {
3687 __ cmpptr(mdo_addr, 0);
3688 __ jccb(Assembler::equal, none);
3689 __ cmpptr(mdo_addr, TypeEntries::null_seen);
3690 __ jccb(Assembler::equal, none);
3691 // There is a chance that the checks above (re-reading profiling
3692 // data from memory) fail if another thread has just set the
3693 // profiling to this obj's klass
3694 __ xorptr(tmp, mdo_addr);
3695 __ testptr(tmp, TypeEntries::type_klass_mask);
3696 __ jccb(Assembler::zero, next);
3697 }
3698 } else {
3699 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
3700 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
3701
3702 __ movptr(tmp, mdo_addr);
3703 __ testptr(tmp, TypeEntries::type_unknown);
3704 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3705 }
3706
3707 // different than before. Cannot keep accurate profile.
3708 __ orptr(mdo_addr, TypeEntries::type_unknown);
3709
3710 if (TypeEntries::is_type_none(current_klass)) {
3711 __ jmpb(next);
3712
3713 __ bind(none);
3714 // first time here. Set profile type.
3715 __ movptr(mdo_addr, tmp);
3716 }
3717 } else {
3718 // There's a single possible klass at this profile point
3719 assert(exact_klass != NULL, "should be");
3720 if (TypeEntries::is_type_none(current_klass)) {
3721 __ mov_metadata(tmp, exact_klass->constant_encoding());
3722 __ xorptr(tmp, mdo_addr);
3723 __ testptr(tmp, TypeEntries::type_klass_mask);
3724 #ifdef ASSERT
3725 __ jcc(Assembler::zero, next);
3726
3727 {
3728 Label ok;
3729 __ push(tmp);
3730 __ cmpptr(mdo_addr, 0);
3731 __ jcc(Assembler::equal, ok);
3732 __ cmpptr(mdo_addr, TypeEntries::null_seen);
3733 __ jcc(Assembler::equal, ok);
3734 // may have been set by another thread
3735 __ mov_metadata(tmp, exact_klass->constant_encoding());
3736 __ xorptr(tmp, mdo_addr);
3737 __ testptr(tmp, TypeEntries::type_mask);
3738 __ jcc(Assembler::zero, ok);
3739
3740 __ stop("unexpected profiling mismatch");
3741 __ bind(ok);
3742 __ pop(tmp);
3743 }
3744 #else
3745 __ jccb(Assembler::zero, next);
3746 #endif
3747 // first time here. Set profile type.
3748 __ movptr(mdo_addr, tmp);
3749 } else {
3750 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
3751 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
3752
3753 __ movptr(tmp, mdo_addr);
3754 __ testptr(tmp, TypeEntries::type_unknown);
3755 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3756
3757 __ orptr(mdo_addr, TypeEntries::type_unknown);
3758 }
3759 }
3760
3761 __ bind(next);
3762 }
3763 }
3764
3765 void LIR_Assembler::emit_delay(LIR_OpDelay*) {
3766 Unimplemented();
3767 }
3768
3769
3770 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) {
3771 __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no));
3772 }
3773
3774
3775 void LIR_Assembler::align_backward_branch_target() {
3776 __ align(BytesPerWord);
3777 }
3778
3779
3780 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) {
3781 if (left->is_single_cpu()) {
3782 __ negl(left->as_register());
3783 move_regs(left->as_register(), dest->as_register());
3784
3785 } else if (left->is_double_cpu()) {
3786 Register lo = left->as_register_lo();
3787 #ifdef _LP64
3788 Register dst = dest->as_register_lo();
3789 __ movptr(dst, lo);
3790 __ negptr(dst);
3791 #else
3792 Register hi = left->as_register_hi();
3793 __ lneg(hi, lo);
3794 if (dest->as_register_lo() == hi) {
3795 assert(dest->as_register_hi() != lo, "destroying register");
3796 move_regs(hi, dest->as_register_hi());
3797 move_regs(lo, dest->as_register_lo());
3798 } else {
3799 move_regs(lo, dest->as_register_lo());
3800 move_regs(hi, dest->as_register_hi());
3801 }
3802 #endif // _LP64
3803
3804 } else if (dest->is_single_xmm()) {
3805 #ifdef _LP64
3806 if (UseAVX > 2 && !VM_Version::supports_avx512vl()) {
3807 assert(tmp->is_valid(), "need temporary");
3808 assert_different_registers(left->as_xmm_float_reg(), tmp->as_xmm_float_reg());
3809 __ vpxor(dest->as_xmm_float_reg(), tmp->as_xmm_float_reg(), left->as_xmm_float_reg(), 2);
3810 }
3811 else
3812 #endif
3813 {
3814 assert(!tmp->is_valid(), "do not need temporary");
3815 if (left->as_xmm_float_reg() != dest->as_xmm_float_reg()) {
3816 __ movflt(dest->as_xmm_float_reg(), left->as_xmm_float_reg());
3817 }
3818 __ xorps(dest->as_xmm_float_reg(),
3819 ExternalAddress((address)float_signflip_pool));
3820 }
3821 } else if (dest->is_double_xmm()) {
3822 #ifdef _LP64
3823 if (UseAVX > 2 && !VM_Version::supports_avx512vl()) {
3824 assert(tmp->is_valid(), "need temporary");
3825 assert_different_registers(left->as_xmm_double_reg(), tmp->as_xmm_double_reg());
3826 __ vpxor(dest->as_xmm_double_reg(), tmp->as_xmm_double_reg(), left->as_xmm_double_reg(), 2);
3827 }
3828 else
3829 #endif
3830 {
3831 assert(!tmp->is_valid(), "do not need temporary");
3832 if (left->as_xmm_double_reg() != dest->as_xmm_double_reg()) {
3833 __ movdbl(dest->as_xmm_double_reg(), left->as_xmm_double_reg());
3834 }
3835 __ xorpd(dest->as_xmm_double_reg(),
3836 ExternalAddress((address)double_signflip_pool));
3837 }
3838 #ifndef _LP64
3839 } else if (left->is_single_fpu() || left->is_double_fpu()) {
3840 assert(left->fpu() == 0, "arg must be on TOS");
3841 assert(dest->fpu() == 0, "dest must be TOS");
3842 __ fchs();
3843 #endif // !_LP64
3844
3845 } else {
3846 ShouldNotReachHere();
3847 }
3848 }
3849
3850
3851 void LIR_Assembler::leal(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
3852 assert(src->is_address(), "must be an address");
3853 assert(dest->is_register(), "must be a register");
3854
3855 PatchingStub* patch = NULL;
3856 if (patch_code != lir_patch_none) {
3857 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
3858 }
3859
3860 Register reg = dest->as_pointer_register();
3861 LIR_Address* addr = src->as_address_ptr();
3862 __ lea(reg, as_Address(addr));
3863
3864 if (patch != NULL) {
3865 patching_epilog(patch, patch_code, addr->base()->as_register(), info);
3866 }
3867 }
3868
3869
3870
3871 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
3872 assert(!tmp->is_valid(), "don't need temporary");
3873 __ call(RuntimeAddress(dest));
3874 if (info != NULL) {
3875 add_call_info_here(info);
3876 }
3877 __ post_call_nop();
3878 }
3879
3880
3881 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
3882 assert(type == T_LONG, "only for volatile long fields");
3883
3884 if (info != NULL) {
3885 add_debug_info_for_null_check_here(info);
3886 }
3887
3888 if (src->is_double_xmm()) {
3889 if (dest->is_double_cpu()) {
3890 #ifdef _LP64
3891 __ movdq(dest->as_register_lo(), src->as_xmm_double_reg());
3892 #else
3893 __ movdl(dest->as_register_lo(), src->as_xmm_double_reg());
3894 __ psrlq(src->as_xmm_double_reg(), 32);
3895 __ movdl(dest->as_register_hi(), src->as_xmm_double_reg());
3896 #endif // _LP64
3897 } else if (dest->is_double_stack()) {
3898 __ movdbl(frame_map()->address_for_slot(dest->double_stack_ix()), src->as_xmm_double_reg());
3899 } else if (dest->is_address()) {
3900 __ movdbl(as_Address(dest->as_address_ptr()), src->as_xmm_double_reg());
3901 } else {
3902 ShouldNotReachHere();
3903 }
3904
3905 } else if (dest->is_double_xmm()) {
3906 if (src->is_double_stack()) {
3907 __ movdbl(dest->as_xmm_double_reg(), frame_map()->address_for_slot(src->double_stack_ix()));
3908 } else if (src->is_address()) {
3909 __ movdbl(dest->as_xmm_double_reg(), as_Address(src->as_address_ptr()));
3910 } else {
3911 ShouldNotReachHere();
3912 }
3913
3914 #ifndef _LP64
3915 } else if (src->is_double_fpu()) {
3916 assert(src->fpu_regnrLo() == 0, "must be TOS");
3917 if (dest->is_double_stack()) {
3918 __ fistp_d(frame_map()->address_for_slot(dest->double_stack_ix()));
3919 } else if (dest->is_address()) {
3920 __ fistp_d(as_Address(dest->as_address_ptr()));
3921 } else {
3922 ShouldNotReachHere();
3923 }
3924
3925 } else if (dest->is_double_fpu()) {
3926 assert(dest->fpu_regnrLo() == 0, "must be TOS");
3927 if (src->is_double_stack()) {
3928 __ fild_d(frame_map()->address_for_slot(src->double_stack_ix()));
3929 } else if (src->is_address()) {
3930 __ fild_d(as_Address(src->as_address_ptr()));
3931 } else {
3932 ShouldNotReachHere();
3933 }
3934 #endif // !_LP64
3935
3936 } else {
3937 ShouldNotReachHere();
3938 }
3939 }
3940
3941 #ifdef ASSERT
3942 // emit run-time assertion
3943 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
3944 assert(op->code() == lir_assert, "must be");
3945
3946 if (op->in_opr1()->is_valid()) {
3947 assert(op->in_opr2()->is_valid(), "both operands must be valid");
3948 comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
3949 } else {
3950 assert(op->in_opr2()->is_illegal(), "both operands must be illegal");
3951 assert(op->condition() == lir_cond_always, "no other conditions allowed");
3952 }
3953
3954 Label ok;
3955 if (op->condition() != lir_cond_always) {
3956 Assembler::Condition acond = Assembler::zero;
3957 switch (op->condition()) {
3958 case lir_cond_equal: acond = Assembler::equal; break;
3959 case lir_cond_notEqual: acond = Assembler::notEqual; break;
3960 case lir_cond_less: acond = Assembler::less; break;
3961 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
3962 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break;
3963 case lir_cond_greater: acond = Assembler::greater; break;
3964 case lir_cond_belowEqual: acond = Assembler::belowEqual; break;
3965 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break;
3966 default: ShouldNotReachHere();
3967 }
3968 __ jcc(acond, ok);
3969 }
3970 if (op->halt()) {
3971 const char* str = __ code_string(op->msg());
3972 __ stop(str);
3973 } else {
3974 breakpoint();
3975 }
3976 __ bind(ok);
3977 }
3978 #endif
3979
3980 void LIR_Assembler::membar() {
3981 // QQQ sparc TSO uses this,
3982 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad));
3983 }
3984
3985 void LIR_Assembler::membar_acquire() {
3986 // No x86 machines currently require load fences
3987 }
3988
3989 void LIR_Assembler::membar_release() {
3990 // No x86 machines currently require store fences
3991 }
3992
3993 void LIR_Assembler::membar_loadload() {
3994 // no-op
3995 //__ membar(Assembler::Membar_mask_bits(Assembler::loadload));
3996 }
3997
3998 void LIR_Assembler::membar_storestore() {
3999 // no-op
4000 //__ membar(Assembler::Membar_mask_bits(Assembler::storestore));
4001 }
4002
4003 void LIR_Assembler::membar_loadstore() {
4004 // no-op
4005 //__ membar(Assembler::Membar_mask_bits(Assembler::loadstore));
4006 }
4007
4008 void LIR_Assembler::membar_storeload() {
4009 __ membar(Assembler::Membar_mask_bits(Assembler::StoreLoad));
4010 }
4011
4012 void LIR_Assembler::on_spin_wait() {
4013 __ pause ();
4014 }
4015
4016 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
4017 assert(result_reg->is_register(), "check");
4018 #ifdef _LP64
4019 // __ get_thread(result_reg->as_register_lo());
4020 __ mov(result_reg->as_register(), r15_thread);
4021 #else
4022 __ get_thread(result_reg->as_register());
4023 #endif // _LP64
4024 }
4025
4026
4027 void LIR_Assembler::peephole(LIR_List*) {
4028 // do nothing for now
4029 }
4030
4031 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) {
4032 assert(data == dest, "xchg/xadd uses only 2 operands");
4033
4034 if (data->type() == T_INT) {
4035 if (code == lir_xadd) {
4036 __ lock();
4037 __ xaddl(as_Address(src->as_address_ptr()), data->as_register());
4038 } else {
4039 __ xchgl(data->as_register(), as_Address(src->as_address_ptr()));
4040 }
4041 } else if (data->is_oop()) {
4042 assert (code == lir_xchg, "xadd for oops");
4043 Register obj = data->as_register();
4044 #ifdef _LP64
4045 if (UseCompressedOops) {
4046 __ encode_heap_oop(obj);
4047 __ xchgl(obj, as_Address(src->as_address_ptr()));
4048 __ decode_heap_oop(obj);
4049 } else {
4050 __ xchgptr(obj, as_Address(src->as_address_ptr()));
4051 }
4052 #else
4053 __ xchgl(obj, as_Address(src->as_address_ptr()));
4054 #endif
4055 } else if (data->type() == T_LONG) {
4056 #ifdef _LP64
4057 assert(data->as_register_lo() == data->as_register_hi(), "should be a single register");
4058 if (code == lir_xadd) {
4059 __ lock();
4060 __ xaddq(as_Address(src->as_address_ptr()), data->as_register_lo());
4061 } else {
4062 __ xchgq(data->as_register_lo(), as_Address(src->as_address_ptr()));
4063 }
4064 #else
4065 ShouldNotReachHere();
4066 #endif
4067 } else {
4068 ShouldNotReachHere();
4069 }
4070 }
4071
4072 #undef __