1 /*
2 * Copyright (c) 1999, 2022, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/assembler.hpp"
27 #include "c1/c1_Defs.hpp"
28 #include "c1/c1_FrameMap.hpp"
29 #include "c1/c1_MacroAssembler.hpp"
30 #include "c1/c1_Runtime1.hpp"
31 #include "ci/ciUtilities.hpp"
32 #include "compiler/oopMap.hpp"
33 #include "gc/shared/cardTable.hpp"
34 #include "gc/shared/cardTableBarrierSet.hpp"
35 #include "gc/shared/collectedHeap.hpp"
36 #include "gc/shared/tlab_globals.hpp"
37 #include "interpreter/interpreter.hpp"
38 #include "memory/universe.hpp"
39 #include "nativeInst_x86.hpp"
40 #include "oops/compiledICHolder.hpp"
41 #include "oops/oop.inline.hpp"
42 #include "prims/jvmtiExport.hpp"
43 #include "register_x86.hpp"
44 #include "runtime/sharedRuntime.hpp"
45 #include "runtime/signature.hpp"
46 #include "runtime/stubRoutines.hpp"
47 #include "runtime/vframeArray.hpp"
48 #include "utilities/macros.hpp"
49 #include "vmreg_x86.inline.hpp"
50
51 // Implementation of StubAssembler
52
53 int StubAssembler::call_RT(Register oop_result1, Register metadata_result, address entry, int args_size) {
54 // setup registers
55 const Register thread = NOT_LP64(rdi) LP64_ONLY(r15_thread); // is callee-saved register (Visual C++ calling conventions)
56 assert(!(oop_result1->is_valid() || metadata_result->is_valid()) || oop_result1 != metadata_result, "registers must be different");
57 assert(oop_result1 != thread && metadata_result != thread, "registers must be different");
58 assert(args_size >= 0, "illegal args_size");
59 bool align_stack = false;
60 #ifdef _LP64
61 // At a method handle call, the stack may not be properly aligned
62 // when returning with an exception.
63 align_stack = (stub_id() == Runtime1::handle_exception_from_callee_id);
64 #endif
65
66 #ifdef _LP64
67 mov(c_rarg0, thread);
68 set_num_rt_args(0); // Nothing on stack
69 #else
70 set_num_rt_args(1 + args_size);
71
72 // push java thread (becomes first argument of C function)
73 get_thread(thread);
74 push(thread);
75 #endif // _LP64
76
77 int call_offset = -1;
78 if (!align_stack) {
79 set_last_Java_frame(thread, noreg, rbp, NULL);
80 } else {
81 address the_pc = pc();
82 call_offset = offset();
83 set_last_Java_frame(thread, noreg, rbp, the_pc);
84 andptr(rsp, -(StackAlignmentInBytes)); // Align stack
85 }
86
87 // do the call
88 call(RuntimeAddress(entry));
89 if (!align_stack) {
90 call_offset = offset();
91 }
92 // verify callee-saved register
93 #ifdef ASSERT
94 guarantee(thread != rax, "change this code");
95 push(rax);
96 { Label L;
97 get_thread(rax);
98 cmpptr(thread, rax);
99 jcc(Assembler::equal, L);
100 int3();
101 stop("StubAssembler::call_RT: rdi not callee saved?");
102 bind(L);
103 }
104 pop(rax);
105 #endif
106 reset_last_Java_frame(thread, true);
107
108 // discard thread and arguments
109 NOT_LP64(addptr(rsp, num_rt_args()*BytesPerWord));
110
111 // check for pending exceptions
112 { Label L;
113 cmpptr(Address(thread, Thread::pending_exception_offset()), (int32_t)NULL_WORD);
114 jcc(Assembler::equal, L);
115 // exception pending => remove activation and forward to exception handler
116 movptr(rax, Address(thread, Thread::pending_exception_offset()));
117 // make sure that the vm_results are cleared
118 if (oop_result1->is_valid()) {
119 movptr(Address(thread, JavaThread::vm_result_offset()), NULL_WORD);
120 }
121 if (metadata_result->is_valid()) {
122 movptr(Address(thread, JavaThread::vm_result_2_offset()), NULL_WORD);
123 }
124 if (frame_size() == no_frame_size) {
125 leave();
126 jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
127 } else if (_stub_id == Runtime1::forward_exception_id) {
128 should_not_reach_here();
129 } else {
130 jump(RuntimeAddress(Runtime1::entry_for(Runtime1::forward_exception_id)));
131 }
132 bind(L);
133 }
134 // get oop results if there are any and reset the values in the thread
135 if (oop_result1->is_valid()) {
136 get_vm_result(oop_result1, thread);
137 }
138 if (metadata_result->is_valid()) {
139 get_vm_result_2(metadata_result, thread);
140 }
141
142 assert(call_offset >= 0, "Should be set");
143 return call_offset;
144 }
145
146
147 int StubAssembler::call_RT(Register oop_result1, Register metadata_result, address entry, Register arg1) {
148 #ifdef _LP64
149 mov(c_rarg1, arg1);
150 #else
151 push(arg1);
152 #endif // _LP64
153 return call_RT(oop_result1, metadata_result, entry, 1);
154 }
155
156
157 int StubAssembler::call_RT(Register oop_result1, Register metadata_result, address entry, Register arg1, Register arg2) {
158 #ifdef _LP64
159 if (c_rarg1 == arg2) {
160 if (c_rarg2 == arg1) {
161 xchgq(arg1, arg2);
162 } else {
163 mov(c_rarg2, arg2);
164 mov(c_rarg1, arg1);
165 }
166 } else {
167 mov(c_rarg1, arg1);
168 mov(c_rarg2, arg2);
169 }
170 #else
171 push(arg2);
172 push(arg1);
173 #endif // _LP64
174 return call_RT(oop_result1, metadata_result, entry, 2);
175 }
176
177
178 int StubAssembler::call_RT(Register oop_result1, Register metadata_result, address entry, Register arg1, Register arg2, Register arg3) {
179 #ifdef _LP64
180 // if there is any conflict use the stack
181 if (arg1 == c_rarg2 || arg1 == c_rarg3 ||
182 arg2 == c_rarg1 || arg2 == c_rarg3 ||
183 arg3 == c_rarg1 || arg3 == c_rarg2) {
184 push(arg3);
185 push(arg2);
186 push(arg1);
187 pop(c_rarg1);
188 pop(c_rarg2);
189 pop(c_rarg3);
190 } else {
191 mov(c_rarg1, arg1);
192 mov(c_rarg2, arg2);
193 mov(c_rarg3, arg3);
194 }
195 #else
196 push(arg3);
197 push(arg2);
198 push(arg1);
199 #endif // _LP64
200 return call_RT(oop_result1, metadata_result, entry, 3);
201 }
202
203
204 // Implementation of StubFrame
205
206 class StubFrame: public StackObj {
207 private:
208 StubAssembler* _sasm;
209
210 public:
211 StubFrame(StubAssembler* sasm, const char* name, bool must_gc_arguments);
212 void load_argument(int offset_in_words, Register reg);
213
214 ~StubFrame();
215 };
216
217 void StubAssembler::prologue(const char* name, bool must_gc_arguments) {
218 set_info(name, must_gc_arguments);
219 enter();
220 }
221
222 void StubAssembler::epilogue() {
223 leave();
224 ret(0);
225 }
226
227 #define __ _sasm->
228
229 StubFrame::StubFrame(StubAssembler* sasm, const char* name, bool must_gc_arguments) {
230 _sasm = sasm;
231 __ prologue(name, must_gc_arguments);
232 }
233
234 // load parameters that were stored with LIR_Assembler::store_parameter
235 // Note: offsets for store_parameter and load_argument must match
236 void StubFrame::load_argument(int offset_in_words, Register reg) {
237 __ load_parameter(offset_in_words, reg);
238 }
239
240
241 StubFrame::~StubFrame() {
242 __ epilogue();
243 }
244
245 #undef __
246
247
248 // Implementation of Runtime1
249
250 const int float_regs_as_doubles_size_in_slots = pd_nof_fpu_regs_frame_map * 2;
251 const int xmm_regs_as_doubles_size_in_slots = FrameMap::nof_xmm_regs * 2;
252
253 // Stack layout for saving/restoring all the registers needed during a runtime
254 // call (this includes deoptimization)
255 // Note: note that users of this frame may well have arguments to some runtime
256 // while these values are on the stack. These positions neglect those arguments
257 // but the code in save_live_registers will take the argument count into
258 // account.
259 //
260 #ifdef _LP64
261 #define SLOT2(x) x,
262 #define SLOT_PER_WORD 2
263 #else
264 #define SLOT2(x)
265 #define SLOT_PER_WORD 1
266 #endif // _LP64
267
268 enum reg_save_layout {
269 // 64bit needs to keep stack 16 byte aligned. So we add some alignment dummies to make that
270 // happen and will assert if the stack size we create is misaligned
271 #ifdef _LP64
272 align_dummy_0, align_dummy_1,
273 #endif // _LP64
274 #ifdef _WIN64
275 // Windows always allocates space for it's argument registers (see
276 // frame::arg_reg_save_area_bytes).
277 arg_reg_save_1, arg_reg_save_1H, // 0, 4
278 arg_reg_save_2, arg_reg_save_2H, // 8, 12
279 arg_reg_save_3, arg_reg_save_3H, // 16, 20
280 arg_reg_save_4, arg_reg_save_4H, // 24, 28
281 #endif // _WIN64
282 xmm_regs_as_doubles_off, // 32
283 float_regs_as_doubles_off = xmm_regs_as_doubles_off + xmm_regs_as_doubles_size_in_slots, // 160
284 fpu_state_off = float_regs_as_doubles_off + float_regs_as_doubles_size_in_slots, // 224
285 // fpu_state_end_off is exclusive
286 fpu_state_end_off = fpu_state_off + (FPUStateSizeInWords / SLOT_PER_WORD), // 352
287 marker = fpu_state_end_off, SLOT2(markerH) // 352, 356
288 extra_space_offset, // 360
289 #ifdef _LP64
290 r15_off = extra_space_offset, r15H_off, // 360, 364
291 r14_off, r14H_off, // 368, 372
292 r13_off, r13H_off, // 376, 380
293 r12_off, r12H_off, // 384, 388
294 r11_off, r11H_off, // 392, 396
295 r10_off, r10H_off, // 400, 404
296 r9_off, r9H_off, // 408, 412
297 r8_off, r8H_off, // 416, 420
298 rdi_off, rdiH_off, // 424, 428
299 #else
300 rdi_off = extra_space_offset,
301 #endif // _LP64
302 rsi_off, SLOT2(rsiH_off) // 432, 436
303 rbp_off, SLOT2(rbpH_off) // 440, 444
304 rsp_off, SLOT2(rspH_off) // 448, 452
305 rbx_off, SLOT2(rbxH_off) // 456, 460
306 rdx_off, SLOT2(rdxH_off) // 464, 468
307 rcx_off, SLOT2(rcxH_off) // 472, 476
308 rax_off, SLOT2(raxH_off) // 480, 484
309 saved_rbp_off, SLOT2(saved_rbpH_off) // 488, 492
310 return_off, SLOT2(returnH_off) // 496, 500
311 reg_save_frame_size // As noted: neglects any parameters to runtime // 504
312 };
313
314 // Save off registers which might be killed by calls into the runtime.
315 // Tries to smart of about FP registers. In particular we separate
316 // saving and describing the FPU registers for deoptimization since we
317 // have to save the FPU registers twice if we describe them and on P4
318 // saving FPU registers which don't contain anything appears
319 // expensive. The deopt blob is the only thing which needs to
320 // describe FPU registers. In all other cases it should be sufficient
321 // to simply save their current value.
322 //
323 // Register is a class, but it would be assigned numerical value.
324 // "0" is assigned for rax. Thus we need to ignore -Wnonnull.
325 PRAGMA_DIAG_PUSH
326 PRAGMA_NONNULL_IGNORED
327 static OopMap* generate_oop_map(StubAssembler* sasm, int num_rt_args,
328 bool save_fpu_registers = true) {
329
330 // In 64bit all the args are in regs so there are no additional stack slots
331 LP64_ONLY(num_rt_args = 0);
332 LP64_ONLY(assert((reg_save_frame_size * VMRegImpl::stack_slot_size) % 16 == 0, "must be 16 byte aligned");)
333 int frame_size_in_slots = reg_save_frame_size + num_rt_args; // args + thread
334 sasm->set_frame_size(frame_size_in_slots / VMRegImpl::slots_per_word);
335
336 // record saved value locations in an OopMap
337 // locations are offsets from sp after runtime call; num_rt_args is number of arguments in call, including thread
338 OopMap* map = new OopMap(frame_size_in_slots, 0);
339 map->set_callee_saved(VMRegImpl::stack2reg(rax_off + num_rt_args), rax->as_VMReg());
340 map->set_callee_saved(VMRegImpl::stack2reg(rcx_off + num_rt_args), rcx->as_VMReg());
341 map->set_callee_saved(VMRegImpl::stack2reg(rdx_off + num_rt_args), rdx->as_VMReg());
342 map->set_callee_saved(VMRegImpl::stack2reg(rbx_off + num_rt_args), rbx->as_VMReg());
343 map->set_callee_saved(VMRegImpl::stack2reg(rsi_off + num_rt_args), rsi->as_VMReg());
344 map->set_callee_saved(VMRegImpl::stack2reg(rdi_off + num_rt_args), rdi->as_VMReg());
345 #ifdef _LP64
346 map->set_callee_saved(VMRegImpl::stack2reg(r8_off + num_rt_args), r8->as_VMReg());
347 map->set_callee_saved(VMRegImpl::stack2reg(r9_off + num_rt_args), r9->as_VMReg());
348 map->set_callee_saved(VMRegImpl::stack2reg(r10_off + num_rt_args), r10->as_VMReg());
349 map->set_callee_saved(VMRegImpl::stack2reg(r11_off + num_rt_args), r11->as_VMReg());
350 map->set_callee_saved(VMRegImpl::stack2reg(r12_off + num_rt_args), r12->as_VMReg());
351 map->set_callee_saved(VMRegImpl::stack2reg(r13_off + num_rt_args), r13->as_VMReg());
352 map->set_callee_saved(VMRegImpl::stack2reg(r14_off + num_rt_args), r14->as_VMReg());
353 map->set_callee_saved(VMRegImpl::stack2reg(r15_off + num_rt_args), r15->as_VMReg());
354
355 // This is stupid but needed.
356 map->set_callee_saved(VMRegImpl::stack2reg(raxH_off + num_rt_args), rax->as_VMReg()->next());
357 map->set_callee_saved(VMRegImpl::stack2reg(rcxH_off + num_rt_args), rcx->as_VMReg()->next());
358 map->set_callee_saved(VMRegImpl::stack2reg(rdxH_off + num_rt_args), rdx->as_VMReg()->next());
359 map->set_callee_saved(VMRegImpl::stack2reg(rbxH_off + num_rt_args), rbx->as_VMReg()->next());
360 map->set_callee_saved(VMRegImpl::stack2reg(rsiH_off + num_rt_args), rsi->as_VMReg()->next());
361 map->set_callee_saved(VMRegImpl::stack2reg(rdiH_off + num_rt_args), rdi->as_VMReg()->next());
362
363 map->set_callee_saved(VMRegImpl::stack2reg(r8H_off + num_rt_args), r8->as_VMReg()->next());
364 map->set_callee_saved(VMRegImpl::stack2reg(r9H_off + num_rt_args), r9->as_VMReg()->next());
365 map->set_callee_saved(VMRegImpl::stack2reg(r10H_off + num_rt_args), r10->as_VMReg()->next());
366 map->set_callee_saved(VMRegImpl::stack2reg(r11H_off + num_rt_args), r11->as_VMReg()->next());
367 map->set_callee_saved(VMRegImpl::stack2reg(r12H_off + num_rt_args), r12->as_VMReg()->next());
368 map->set_callee_saved(VMRegImpl::stack2reg(r13H_off + num_rt_args), r13->as_VMReg()->next());
369 map->set_callee_saved(VMRegImpl::stack2reg(r14H_off + num_rt_args), r14->as_VMReg()->next());
370 map->set_callee_saved(VMRegImpl::stack2reg(r15H_off + num_rt_args), r15->as_VMReg()->next());
371 #endif // _LP64
372
373 int xmm_bypass_limit = FrameMap::get_num_caller_save_xmms();
374
375 if (save_fpu_registers) {
376 #ifndef _LP64
377 if (UseSSE < 2) {
378 int fpu_off = float_regs_as_doubles_off;
379 for (int n = 0; n < FrameMap::nof_fpu_regs; n++) {
380 VMReg fpu_name_0 = FrameMap::fpu_regname(n);
381 map->set_callee_saved(VMRegImpl::stack2reg(fpu_off + num_rt_args), fpu_name_0);
382 // %%% This is really a waste but we'll keep things as they were for now
383 if (true) {
384 map->set_callee_saved(VMRegImpl::stack2reg(fpu_off + 1 + num_rt_args), fpu_name_0->next());
385 }
386 fpu_off += 2;
387 }
388 assert(fpu_off == fpu_state_off, "incorrect number of fpu stack slots");
389
390 if (UseSSE == 1) {
391 int xmm_off = xmm_regs_as_doubles_off;
392 for (int n = 0; n < FrameMap::nof_fpu_regs; n++) {
393 VMReg xmm_name_0 = as_XMMRegister(n)->as_VMReg();
394 map->set_callee_saved(VMRegImpl::stack2reg(xmm_off + num_rt_args), xmm_name_0);
395 xmm_off += 2;
396 }
397 assert(xmm_off == float_regs_as_doubles_off, "incorrect number of xmm registers");
398 }
399 }
400 #endif // !LP64
401
402 if (UseSSE >= 2) {
403 int xmm_off = xmm_regs_as_doubles_off;
404 for (int n = 0; n < FrameMap::nof_xmm_regs; n++) {
405 if (n < xmm_bypass_limit) {
406 VMReg xmm_name_0 = as_XMMRegister(n)->as_VMReg();
407 map->set_callee_saved(VMRegImpl::stack2reg(xmm_off + num_rt_args), xmm_name_0);
408 // %%% This is really a waste but we'll keep things as they were for now
409 if (true) {
410 map->set_callee_saved(VMRegImpl::stack2reg(xmm_off + 1 + num_rt_args), xmm_name_0->next());
411 }
412 }
413 xmm_off += 2;
414 }
415 assert(xmm_off == float_regs_as_doubles_off, "incorrect number of xmm registers");
416 }
417 }
418
419 return map;
420 }
421 PRAGMA_DIAG_POP
422
423 #define __ this->
424
425 void C1_MacroAssembler::save_live_registers_no_oop_map(bool save_fpu_registers) {
426 __ block_comment("save_live_registers");
427
428 __ pusha(); // integer registers
429
430 // assert(float_regs_as_doubles_off % 2 == 0, "misaligned offset");
431 // assert(xmm_regs_as_doubles_off % 2 == 0, "misaligned offset");
432
433 __ subptr(rsp, extra_space_offset * VMRegImpl::stack_slot_size);
434
435 #ifdef ASSERT
436 __ movptr(Address(rsp, marker * VMRegImpl::stack_slot_size), (int32_t)0xfeedbeef);
437 #endif
438
439 if (save_fpu_registers) {
440 #ifndef _LP64
441 if (UseSSE < 2) {
442 // save FPU stack
443 __ fnsave(Address(rsp, fpu_state_off * VMRegImpl::stack_slot_size));
444 __ fwait();
445
446 #ifdef ASSERT
447 Label ok;
448 __ cmpw(Address(rsp, fpu_state_off * VMRegImpl::stack_slot_size), StubRoutines::x86::fpu_cntrl_wrd_std());
449 __ jccb(Assembler::equal, ok);
450 __ stop("corrupted control word detected");
451 __ bind(ok);
452 #endif
453
454 // Reset the control word to guard against exceptions being unmasked
455 // since fstp_d can cause FPU stack underflow exceptions. Write it
456 // into the on stack copy and then reload that to make sure that the
457 // current and future values are correct.
458 __ movw(Address(rsp, fpu_state_off * VMRegImpl::stack_slot_size), StubRoutines::x86::fpu_cntrl_wrd_std());
459 __ frstor(Address(rsp, fpu_state_off * VMRegImpl::stack_slot_size));
460
461 // Save the FPU registers in de-opt-able form
462 int offset = 0;
463 for (int n = 0; n < FrameMap::nof_fpu_regs; n++) {
464 __ fstp_d(Address(rsp, float_regs_as_doubles_off * VMRegImpl::stack_slot_size + offset));
465 offset += 8;
466 }
467
468 if (UseSSE == 1) {
469 // save XMM registers as float because double not supported without SSE2(num MMX == num fpu)
470 int offset = 0;
471 for (int n = 0; n < FrameMap::nof_fpu_regs; n++) {
472 XMMRegister xmm_name = as_XMMRegister(n);
473 __ movflt(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + offset), xmm_name);
474 offset += 8;
475 }
476 }
477 }
478 #endif // !_LP64
479
480 if (UseSSE >= 2) {
481 // save XMM registers
482 // XMM registers can contain float or double values, but this is not known here,
483 // so always save them as doubles.
484 // note that float values are _not_ converted automatically, so for float values
485 // the second word contains only garbage data.
486 int xmm_bypass_limit = FrameMap::get_num_caller_save_xmms();
487 int offset = 0;
488 for (int n = 0; n < xmm_bypass_limit; n++) {
489 XMMRegister xmm_name = as_XMMRegister(n);
490 __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + offset), xmm_name);
491 offset += 8;
492 }
493 }
494 }
495
496 // FPU stack must be empty now
497 NOT_LP64( __ verify_FPU(0, "save_live_registers"); )
498 }
499
500 #undef __
501 #define __ sasm->
502
503 static void restore_fpu(C1_MacroAssembler* sasm, bool restore_fpu_registers) {
504 #ifdef _LP64
505 if (restore_fpu_registers) {
506 // restore XMM registers
507 int xmm_bypass_limit = FrameMap::get_num_caller_save_xmms();
508 int offset = 0;
509 for (int n = 0; n < xmm_bypass_limit; n++) {
510 XMMRegister xmm_name = as_XMMRegister(n);
511 __ movdbl(xmm_name, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + offset));
512 offset += 8;
513 }
514 }
515 #else
516 if (restore_fpu_registers) {
517 if (UseSSE >= 2) {
518 // restore XMM registers
519 int xmm_bypass_limit = FrameMap::nof_xmm_regs;
520 int offset = 0;
521 for (int n = 0; n < xmm_bypass_limit; n++) {
522 XMMRegister xmm_name = as_XMMRegister(n);
523 __ movdbl(xmm_name, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + offset));
524 offset += 8;
525 }
526 } else if (UseSSE == 1) {
527 // restore XMM registers(num MMX == num fpu)
528 int offset = 0;
529 for (int n = 0; n < FrameMap::nof_fpu_regs; n++) {
530 XMMRegister xmm_name = as_XMMRegister(n);
531 __ movflt(xmm_name, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + offset));
532 offset += 8;
533 }
534 }
535
536 if (UseSSE < 2) {
537 __ frstor(Address(rsp, fpu_state_off * VMRegImpl::stack_slot_size));
538 } else {
539 // check that FPU stack is really empty
540 __ verify_FPU(0, "restore_live_registers");
541 }
542 } else {
543 // check that FPU stack is really empty
544 __ verify_FPU(0, "restore_live_registers");
545 }
546 #endif // _LP64
547
548 #ifdef ASSERT
549 {
550 Label ok;
551 __ cmpptr(Address(rsp, marker * VMRegImpl::stack_slot_size), (int32_t)0xfeedbeef);
552 __ jcc(Assembler::equal, ok);
553 __ stop("bad offsets in frame");
554 __ bind(ok);
555 }
556 #endif // ASSERT
557
558 __ addptr(rsp, extra_space_offset * VMRegImpl::stack_slot_size);
559 }
560
561 #undef __
562 #define __ this->
563
564 void C1_MacroAssembler::restore_live_registers(bool restore_fpu_registers) {
565 __ block_comment("restore_live_registers");
566
567 restore_fpu(this, restore_fpu_registers);
568 __ popa();
569 }
570
571
572 void C1_MacroAssembler::restore_live_registers_except_rax(bool restore_fpu_registers) {
573 __ block_comment("restore_live_registers_except_rax");
574
575 restore_fpu(this, restore_fpu_registers);
576
577 #ifdef _LP64
578 __ movptr(r15, Address(rsp, 0));
579 __ movptr(r14, Address(rsp, wordSize));
580 __ movptr(r13, Address(rsp, 2 * wordSize));
581 __ movptr(r12, Address(rsp, 3 * wordSize));
582 __ movptr(r11, Address(rsp, 4 * wordSize));
583 __ movptr(r10, Address(rsp, 5 * wordSize));
584 __ movptr(r9, Address(rsp, 6 * wordSize));
585 __ movptr(r8, Address(rsp, 7 * wordSize));
586 __ movptr(rdi, Address(rsp, 8 * wordSize));
587 __ movptr(rsi, Address(rsp, 9 * wordSize));
588 __ movptr(rbp, Address(rsp, 10 * wordSize));
589 // skip rsp
590 __ movptr(rbx, Address(rsp, 12 * wordSize));
591 __ movptr(rdx, Address(rsp, 13 * wordSize));
592 __ movptr(rcx, Address(rsp, 14 * wordSize));
593
594 __ addptr(rsp, 16 * wordSize);
595 #else
596
597 __ pop(rdi);
598 __ pop(rsi);
599 __ pop(rbp);
600 __ pop(rbx); // skip this value
601 __ pop(rbx);
602 __ pop(rdx);
603 __ pop(rcx);
604 __ addptr(rsp, BytesPerWord);
605 #endif // _LP64
606 }
607
608 #undef __
609 #define __ sasm->
610
611 static OopMap* save_live_registers(StubAssembler* sasm, int num_rt_args,
612 bool save_fpu_registers = true) {
613 __ save_live_registers_no_oop_map(save_fpu_registers);
614 return generate_oop_map(sasm, num_rt_args, save_fpu_registers);
615 }
616
617 static void restore_live_registers(StubAssembler* sasm, bool restore_fpu_registers = true) {
618 __ restore_live_registers(restore_fpu_registers);
619 }
620
621 static void restore_live_registers_except_rax(StubAssembler* sasm, bool restore_fpu_registers = true) {
622 sasm->restore_live_registers_except_rax(restore_fpu_registers);
623 }
624
625
626 void Runtime1::initialize_pd() {
627 // nothing to do
628 }
629
630
631 // Target: the entry point of the method that creates and posts the exception oop.
632 // has_argument: true if the exception needs arguments (passed on the stack because
633 // registers must be preserved).
634 OopMapSet* Runtime1::generate_exception_throw(StubAssembler* sasm, address target, bool has_argument) {
635 // Preserve all registers.
636 int num_rt_args = has_argument ? (2 + 1) : 1;
637 OopMap* oop_map = save_live_registers(sasm, num_rt_args);
638
639 // Now all registers are saved and can be used freely.
640 // Verify that no old value is used accidentally.
641 __ invalidate_registers(true, true, true, true, true, true);
642
643 // Registers used by this stub.
644 const Register temp_reg = rbx;
645
646 // Load arguments for exception that are passed as arguments into the stub.
647 if (has_argument) {
648 #ifdef _LP64
649 __ movptr(c_rarg1, Address(rbp, 2*BytesPerWord));
650 __ movptr(c_rarg2, Address(rbp, 3*BytesPerWord));
651 #else
652 __ movptr(temp_reg, Address(rbp, 3*BytesPerWord));
653 __ push(temp_reg);
654 __ movptr(temp_reg, Address(rbp, 2*BytesPerWord));
655 __ push(temp_reg);
656 #endif // _LP64
657 }
658 int call_offset = __ call_RT(noreg, noreg, target, num_rt_args - 1);
659
660 OopMapSet* oop_maps = new OopMapSet();
661 oop_maps->add_gc_map(call_offset, oop_map);
662
663 __ stop("should not reach here");
664
665 return oop_maps;
666 }
667
668
669 OopMapSet* Runtime1::generate_handle_exception(StubID id, StubAssembler *sasm) {
670 __ block_comment("generate_handle_exception");
671
672 // incoming parameters
673 const Register exception_oop = rax;
674 const Register exception_pc = rdx;
675 // other registers used in this stub
676 const Register thread = NOT_LP64(rdi) LP64_ONLY(r15_thread);
677
678 // Save registers, if required.
679 OopMapSet* oop_maps = new OopMapSet();
680 OopMap* oop_map = NULL;
681 switch (id) {
682 case forward_exception_id:
683 // We're handling an exception in the context of a compiled frame.
684 // The registers have been saved in the standard places. Perform
685 // an exception lookup in the caller and dispatch to the handler
686 // if found. Otherwise unwind and dispatch to the callers
687 // exception handler.
688 oop_map = generate_oop_map(sasm, 1 /*thread*/);
689
690 // load and clear pending exception oop into RAX
691 __ movptr(exception_oop, Address(thread, Thread::pending_exception_offset()));
692 __ movptr(Address(thread, Thread::pending_exception_offset()), NULL_WORD);
693
694 // load issuing PC (the return address for this stub) into rdx
695 __ movptr(exception_pc, Address(rbp, 1*BytesPerWord));
696
697 // make sure that the vm_results are cleared (may be unnecessary)
698 __ movptr(Address(thread, JavaThread::vm_result_offset()), NULL_WORD);
699 __ movptr(Address(thread, JavaThread::vm_result_2_offset()), NULL_WORD);
700 break;
701 case handle_exception_nofpu_id:
702 case handle_exception_id:
703 // At this point all registers MAY be live.
704 oop_map = save_live_registers(sasm, 1 /*thread*/, id != handle_exception_nofpu_id);
705 break;
706 case handle_exception_from_callee_id: {
707 // At this point all registers except exception oop (RAX) and
708 // exception pc (RDX) are dead.
709 const int frame_size = 2 /*BP, return address*/ NOT_LP64(+ 1 /*thread*/) WIN64_ONLY(+ frame::arg_reg_save_area_bytes / BytesPerWord);
710 oop_map = new OopMap(frame_size * VMRegImpl::slots_per_word, 0);
711 sasm->set_frame_size(frame_size);
712 WIN64_ONLY(__ subq(rsp, frame::arg_reg_save_area_bytes));
713 break;
714 }
715 default: ShouldNotReachHere();
716 }
717
718 #if !defined(_LP64) && defined(COMPILER2)
719 if (UseSSE < 2 && !CompilerConfig::is_c1_only_no_jvmci()) {
720 // C2 can leave the fpu stack dirty
721 __ empty_FPU_stack();
722 }
723 #endif // !_LP64 && COMPILER2
724
725 // verify that only rax, and rdx is valid at this time
726 __ invalidate_registers(false, true, true, false, true, true);
727 // verify that rax, contains a valid exception
728 __ verify_not_null_oop(exception_oop);
729
730 // load address of JavaThread object for thread-local data
731 NOT_LP64(__ get_thread(thread);)
732
733 #ifdef ASSERT
734 // check that fields in JavaThread for exception oop and issuing pc are
735 // empty before writing to them
736 Label oop_empty;
737 __ cmpptr(Address(thread, JavaThread::exception_oop_offset()), (int32_t) NULL_WORD);
738 __ jcc(Assembler::equal, oop_empty);
739 __ stop("exception oop already set");
740 __ bind(oop_empty);
741
742 Label pc_empty;
743 __ cmpptr(Address(thread, JavaThread::exception_pc_offset()), 0);
744 __ jcc(Assembler::equal, pc_empty);
745 __ stop("exception pc already set");
746 __ bind(pc_empty);
747 #endif
748
749 // save exception oop and issuing pc into JavaThread
750 // (exception handler will load it from here)
751 __ movptr(Address(thread, JavaThread::exception_oop_offset()), exception_oop);
752 __ movptr(Address(thread, JavaThread::exception_pc_offset()), exception_pc);
753
754 // patch throwing pc into return address (has bci & oop map)
755 __ movptr(Address(rbp, 1*BytesPerWord), exception_pc);
756
757 // compute the exception handler.
758 // the exception oop and the throwing pc are read from the fields in JavaThread
759 int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, exception_handler_for_pc));
760 oop_maps->add_gc_map(call_offset, oop_map);
761
762 // rax: handler address
763 // will be the deopt blob if nmethod was deoptimized while we looked up
764 // handler regardless of whether handler existed in the nmethod.
765
766 // only rax, is valid at this time, all other registers have been destroyed by the runtime call
767 __ invalidate_registers(false, true, true, true, true, true);
768
769 // patch the return address, this stub will directly return to the exception handler
770 __ movptr(Address(rbp, 1*BytesPerWord), rax);
771
772 switch (id) {
773 case forward_exception_id:
774 case handle_exception_nofpu_id:
775 case handle_exception_id:
776 // Restore the registers that were saved at the beginning.
777 restore_live_registers(sasm, id != handle_exception_nofpu_id);
778 break;
779 case handle_exception_from_callee_id:
780 // WIN64_ONLY: No need to add frame::arg_reg_save_area_bytes to SP
781 // since we do a leave anyway.
782
783 // Pop the return address.
784 __ leave();
785 __ pop(rcx);
786 __ jmp(rcx); // jump to exception handler
787 break;
788 default: ShouldNotReachHere();
789 }
790
791 return oop_maps;
792 }
793
794
795 void Runtime1::generate_unwind_exception(StubAssembler *sasm) {
796 // incoming parameters
797 const Register exception_oop = rax;
798 // callee-saved copy of exception_oop during runtime call
799 const Register exception_oop_callee_saved = NOT_LP64(rsi) LP64_ONLY(r14);
800 // other registers used in this stub
801 const Register exception_pc = rdx;
802 const Register handler_addr = rbx;
803 const Register thread = NOT_LP64(rdi) LP64_ONLY(r15_thread);
804
805 // verify that only rax, is valid at this time
806 __ invalidate_registers(false, true, true, true, true, true);
807
808 #ifdef ASSERT
809 // check that fields in JavaThread for exception oop and issuing pc are empty
810 NOT_LP64(__ get_thread(thread);)
811 Label oop_empty;
812 __ cmpptr(Address(thread, JavaThread::exception_oop_offset()), 0);
813 __ jcc(Assembler::equal, oop_empty);
814 __ stop("exception oop must be empty");
815 __ bind(oop_empty);
816
817 Label pc_empty;
818 __ cmpptr(Address(thread, JavaThread::exception_pc_offset()), 0);
819 __ jcc(Assembler::equal, pc_empty);
820 __ stop("exception pc must be empty");
821 __ bind(pc_empty);
822 #endif
823
824 // clear the FPU stack in case any FPU results are left behind
825 NOT_LP64( __ empty_FPU_stack(); )
826
827 // save exception_oop in callee-saved register to preserve it during runtime calls
828 __ verify_not_null_oop(exception_oop);
829 __ movptr(exception_oop_callee_saved, exception_oop);
830
831 NOT_LP64(__ get_thread(thread);)
832 // Get return address (is on top of stack after leave).
833 __ movptr(exception_pc, Address(rsp, 0));
834
835 // search the exception handler address of the caller (using the return address)
836 __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::exception_handler_for_return_address), thread, exception_pc);
837 // rax: exception handler address of the caller
838
839 // Only RAX and RSI are valid at this time, all other registers have been destroyed by the call.
840 __ invalidate_registers(false, true, true, true, false, true);
841
842 // move result of call into correct register
843 __ movptr(handler_addr, rax);
844
845 // Restore exception oop to RAX (required convention of exception handler).
846 __ movptr(exception_oop, exception_oop_callee_saved);
847
848 // verify that there is really a valid exception in rax
849 __ verify_not_null_oop(exception_oop);
850
851 // get throwing pc (= return address).
852 // rdx has been destroyed by the call, so it must be set again
853 // the pop is also necessary to simulate the effect of a ret(0)
854 __ pop(exception_pc);
855
856 // continue at exception handler (return address removed)
857 // note: do *not* remove arguments when unwinding the
858 // activation since the caller assumes having
859 // all arguments on the stack when entering the
860 // runtime to determine the exception handler
861 // (GC happens at call site with arguments!)
862 // rax: exception oop
863 // rdx: throwing pc
864 // rbx: exception handler
865 __ jmp(handler_addr);
866 }
867
868
869 OopMapSet* Runtime1::generate_patching(StubAssembler* sasm, address target) {
870 // use the maximum number of runtime-arguments here because it is difficult to
871 // distinguish each RT-Call.
872 // Note: This number affects also the RT-Call in generate_handle_exception because
873 // the oop-map is shared for all calls.
874 const int num_rt_args = 2; // thread + dummy
875
876 DeoptimizationBlob* deopt_blob = SharedRuntime::deopt_blob();
877 assert(deopt_blob != NULL, "deoptimization blob must have been created");
878
879 OopMap* oop_map = save_live_registers(sasm, num_rt_args);
880
881 #ifdef _LP64
882 const Register thread = r15_thread;
883 // No need to worry about dummy
884 __ mov(c_rarg0, thread);
885 #else
886 __ push(rax); // push dummy
887
888 const Register thread = rdi; // is callee-saved register (Visual C++ calling conventions)
889 // push java thread (becomes first argument of C function)
890 __ get_thread(thread);
891 __ push(thread);
892 #endif // _LP64
893 __ set_last_Java_frame(thread, noreg, rbp, NULL);
894 // do the call
895 __ call(RuntimeAddress(target));
896 OopMapSet* oop_maps = new OopMapSet();
897 oop_maps->add_gc_map(__ offset(), oop_map);
898 // verify callee-saved register
899 #ifdef ASSERT
900 guarantee(thread != rax, "change this code");
901 __ push(rax);
902 { Label L;
903 __ get_thread(rax);
904 __ cmpptr(thread, rax);
905 __ jcc(Assembler::equal, L);
906 __ stop("StubAssembler::call_RT: rdi/r15 not callee saved?");
907 __ bind(L);
908 }
909 __ pop(rax);
910 #endif
911 __ reset_last_Java_frame(thread, true);
912 #ifndef _LP64
913 __ pop(rcx); // discard thread arg
914 __ pop(rcx); // discard dummy
915 #endif // _LP64
916
917 // check for pending exceptions
918 { Label L;
919 __ cmpptr(Address(thread, Thread::pending_exception_offset()), (int32_t)NULL_WORD);
920 __ jcc(Assembler::equal, L);
921 // exception pending => remove activation and forward to exception handler
922
923 __ testptr(rax, rax); // have we deoptimized?
924 __ jump_cc(Assembler::equal,
925 RuntimeAddress(Runtime1::entry_for(Runtime1::forward_exception_id)));
926
927 // the deopt blob expects exceptions in the special fields of
928 // JavaThread, so copy and clear pending exception.
929
930 // load and clear pending exception
931 __ movptr(rax, Address(thread, Thread::pending_exception_offset()));
932 __ movptr(Address(thread, Thread::pending_exception_offset()), NULL_WORD);
933
934 // check that there is really a valid exception
935 __ verify_not_null_oop(rax);
936
937 // load throwing pc: this is the return address of the stub
938 __ movptr(rdx, Address(rsp, return_off * VMRegImpl::stack_slot_size));
939
940 #ifdef ASSERT
941 // check that fields in JavaThread for exception oop and issuing pc are empty
942 Label oop_empty;
943 __ cmpptr(Address(thread, JavaThread::exception_oop_offset()), (int32_t)NULL_WORD);
944 __ jcc(Assembler::equal, oop_empty);
945 __ stop("exception oop must be empty");
946 __ bind(oop_empty);
947
948 Label pc_empty;
949 __ cmpptr(Address(thread, JavaThread::exception_pc_offset()), (int32_t)NULL_WORD);
950 __ jcc(Assembler::equal, pc_empty);
951 __ stop("exception pc must be empty");
952 __ bind(pc_empty);
953 #endif
954
955 // store exception oop and throwing pc to JavaThread
956 __ movptr(Address(thread, JavaThread::exception_oop_offset()), rax);
957 __ movptr(Address(thread, JavaThread::exception_pc_offset()), rdx);
958
959 restore_live_registers(sasm);
960
961 __ leave();
962 __ addptr(rsp, BytesPerWord); // remove return address from stack
963
964 // Forward the exception directly to deopt blob. We can blow no
965 // registers and must leave throwing pc on the stack. A patch may
966 // have values live in registers so the entry point with the
967 // exception in tls.
968 __ jump(RuntimeAddress(deopt_blob->unpack_with_exception_in_tls()));
969
970 __ bind(L);
971 }
972
973
974 // Runtime will return true if the nmethod has been deoptimized during
975 // the patching process. In that case we must do a deopt reexecute instead.
976
977 Label cont;
978
979 __ testptr(rax, rax); // have we deoptimized?
980 __ jcc(Assembler::equal, cont); // no
981
982 // Will reexecute. Proper return address is already on the stack we just restore
983 // registers, pop all of our frame but the return address and jump to the deopt blob
984 restore_live_registers(sasm);
985 __ leave();
986 __ jump(RuntimeAddress(deopt_blob->unpack_with_reexecution()));
987
988 __ bind(cont);
989 restore_live_registers(sasm);
990 __ leave();
991 __ ret(0);
992
993 return oop_maps;
994 }
995
996
997 OopMapSet* Runtime1::generate_code_for(StubID id, StubAssembler* sasm) {
998
999 // for better readability
1000 const bool must_gc_arguments = true;
1001 const bool dont_gc_arguments = false;
1002
1003 // default value; overwritten for some optimized stubs that are called from methods that do not use the fpu
1004 bool save_fpu_registers = true;
1005
1006 // stub code & info for the different stubs
1007 OopMapSet* oop_maps = NULL;
1008 switch (id) {
1009 case forward_exception_id:
1010 {
1011 oop_maps = generate_handle_exception(id, sasm);
1012 __ leave();
1013 __ ret(0);
1014 }
1015 break;
1016
1017 case new_instance_id:
1018 case fast_new_instance_id:
1019 case fast_new_instance_init_check_id:
1020 {
1021 Register klass = rdx; // Incoming
1022 Register obj = rax; // Result
1023
1024 if (id == new_instance_id) {
1025 __ set_info("new_instance", dont_gc_arguments);
1026 } else if (id == fast_new_instance_id) {
1027 __ set_info("fast new_instance", dont_gc_arguments);
1028 } else {
1029 assert(id == fast_new_instance_init_check_id, "bad StubID");
1030 __ set_info("fast new_instance init check", dont_gc_arguments);
1031 }
1032
1033 // If TLAB is disabled, see if there is support for inlining contiguous
1034 // allocations.
1035 // Otherwise, just go to the slow path.
1036 if ((id == fast_new_instance_id || id == fast_new_instance_init_check_id) && !UseTLAB
1037 && Universe::heap()->supports_inline_contig_alloc()) {
1038 Label slow_path;
1039 Register obj_size = rcx;
1040 Register t1 = rbx;
1041 Register t2 = rsi;
1042 assert_different_registers(klass, obj, obj_size, t1, t2);
1043
1044 __ push(rdi);
1045 __ push(rbx);
1046
1047 if (id == fast_new_instance_init_check_id) {
1048 // make sure the klass is initialized
1049 __ cmpb(Address(klass, InstanceKlass::init_state_offset()), InstanceKlass::fully_initialized);
1050 __ jcc(Assembler::notEqual, slow_path);
1051 }
1052
1053 #ifdef ASSERT
1054 // assert object can be fast path allocated
1055 {
1056 Label ok, not_ok;
1057 __ movl(obj_size, Address(klass, Klass::layout_helper_offset()));
1058 __ cmpl(obj_size, 0); // make sure it's an instance (LH > 0)
1059 __ jcc(Assembler::lessEqual, not_ok);
1060 __ testl(obj_size, Klass::_lh_instance_slow_path_bit);
1061 __ jcc(Assembler::zero, ok);
1062 __ bind(not_ok);
1063 __ stop("assert(can be fast path allocated)");
1064 __ should_not_reach_here();
1065 __ bind(ok);
1066 }
1067 #endif // ASSERT
1068
1069 const Register thread = NOT_LP64(rdi) LP64_ONLY(r15_thread);
1070 NOT_LP64(__ get_thread(thread));
1071
1072 // get the instance size (size is positive so movl is fine for 64bit)
1073 __ movl(obj_size, Address(klass, Klass::layout_helper_offset()));
1074
1075 __ eden_allocate(thread, obj, obj_size, 0, t1, slow_path);
1076
1077 __ initialize_object(obj, klass, obj_size, 0, t1, t2, /* is_tlab_allocated */ false);
1078 __ verify_oop(obj);
1079 __ pop(rbx);
1080 __ pop(rdi);
1081 __ ret(0);
1082
1083 __ bind(slow_path);
1084 __ pop(rbx);
1085 __ pop(rdi);
1086 }
1087
1088 __ enter();
1089 OopMap* map = save_live_registers(sasm, 2);
1090 int call_offset = __ call_RT(obj, noreg, CAST_FROM_FN_PTR(address, new_instance), klass);
1091 oop_maps = new OopMapSet();
1092 oop_maps->add_gc_map(call_offset, map);
1093 restore_live_registers_except_rax(sasm);
1094 __ verify_oop(obj);
1095 __ leave();
1096 __ ret(0);
1097
1098 // rax,: new instance
1099 }
1100
1101 break;
1102 #ifdef _LP64
1103 case load_klass_id:
1104 {
1105 StubFrame f(sasm, "load_klass", dont_gc_arguments);
1106 sasm->save_live_registers_no_oop_map(true);
1107 f.load_argument(0, c_rarg0); // obj
1108 __ call_VM_leaf(CAST_FROM_FN_PTR(address, oopDesc::load_nklass_runtime), c_rarg0);
1109 sasm->restore_live_registers_except_rax(true);
1110 }
1111 break;
1112 #endif
1113 case counter_overflow_id:
1114 {
1115 Register bci = rax, method = rbx;
1116 __ enter();
1117 OopMap* map = save_live_registers(sasm, 3);
1118 // Retrieve bci
1119 __ movl(bci, Address(rbp, 2*BytesPerWord));
1120 // And a pointer to the Method*
1121 __ movptr(method, Address(rbp, 3*BytesPerWord));
1122 int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, counter_overflow), bci, method);
1123 oop_maps = new OopMapSet();
1124 oop_maps->add_gc_map(call_offset, map);
1125 restore_live_registers(sasm);
1126 __ leave();
1127 __ ret(0);
1128 }
1129 break;
1130
1131 case new_type_array_id:
1132 case new_object_array_id:
1133 {
1134 Register length = rbx; // Incoming
1135 Register klass = rdx; // Incoming
1136 Register obj = rax; // Result
1137
1138 if (id == new_type_array_id) {
1139 __ set_info("new_type_array", dont_gc_arguments);
1140 } else {
1141 __ set_info("new_object_array", dont_gc_arguments);
1142 }
1143
1144 #ifdef ASSERT
1145 // assert object type is really an array of the proper kind
1146 {
1147 Label ok;
1148 Register t0 = obj;
1149 __ movl(t0, Address(klass, Klass::layout_helper_offset()));
1150 __ sarl(t0, Klass::_lh_array_tag_shift);
1151 int tag = ((id == new_type_array_id)
1152 ? Klass::_lh_array_tag_type_value
1153 : Klass::_lh_array_tag_obj_value);
1154 __ cmpl(t0, tag);
1155 __ jcc(Assembler::equal, ok);
1156 __ stop("assert(is an array klass)");
1157 __ should_not_reach_here();
1158 __ bind(ok);
1159 }
1160 #endif // ASSERT
1161
1162 // If TLAB is disabled, see if there is support for inlining contiguous
1163 // allocations.
1164 // Otherwise, just go to the slow path.
1165 if (!UseTLAB && Universe::heap()->supports_inline_contig_alloc()) {
1166 Register arr_size = rsi;
1167 Register t1 = rcx; // must be rcx for use as shift count
1168 Register t2 = rdi;
1169 Label slow_path;
1170
1171 // get the allocation size: round_up(hdr + length << (layout_helper & 0x1F))
1172 // since size is positive movl does right thing on 64bit
1173 __ movl(t1, Address(klass, Klass::layout_helper_offset()));
1174 // since size is positive movl does right thing on 64bit
1175 __ movl(arr_size, length);
1176 assert(t1 == rcx, "fixed register usage");
1177 __ shlptr(arr_size /* by t1=rcx, mod 32 */);
1178 __ shrptr(t1, Klass::_lh_header_size_shift);
1179 __ andptr(t1, Klass::_lh_header_size_mask);
1180 __ addptr(arr_size, t1);
1181 __ addptr(arr_size, MinObjAlignmentInBytesMask); // align up
1182 __ andptr(arr_size, ~MinObjAlignmentInBytesMask);
1183
1184 // Using t2 for non 64-bit.
1185 const Register thread = NOT_LP64(t2) LP64_ONLY(r15_thread);
1186 NOT_LP64(__ get_thread(thread));
1187 __ eden_allocate(thread, obj, arr_size, 0, t1, slow_path); // preserves arr_size
1188
1189 __ initialize_header(obj, klass, length, t1, t2);
1190 __ movb(t1, Address(klass, in_bytes(Klass::layout_helper_offset()) + (Klass::_lh_header_size_shift / BitsPerByte)));
1191 assert(Klass::_lh_header_size_shift % BitsPerByte == 0, "bytewise");
1192 assert(Klass::_lh_header_size_mask <= 0xFF, "bytewise");
1193 __ andptr(t1, Klass::_lh_header_size_mask);
1194 __ subptr(arr_size, t1); // body length
1195 __ addptr(t1, obj); // body start
1196 __ initialize_body(t1, arr_size, 0, t2);
1197 __ verify_oop(obj);
1198 __ ret(0);
1199
1200 __ bind(slow_path);
1201 }
1202
1203 __ enter();
1204 OopMap* map = save_live_registers(sasm, 3);
1205 int call_offset;
1206 if (id == new_type_array_id) {
1207 call_offset = __ call_RT(obj, noreg, CAST_FROM_FN_PTR(address, new_type_array), klass, length);
1208 } else {
1209 call_offset = __ call_RT(obj, noreg, CAST_FROM_FN_PTR(address, new_object_array), klass, length);
1210 }
1211
1212 oop_maps = new OopMapSet();
1213 oop_maps->add_gc_map(call_offset, map);
1214 restore_live_registers_except_rax(sasm);
1215
1216 __ verify_oop(obj);
1217 __ leave();
1218 __ ret(0);
1219
1220 // rax,: new array
1221 }
1222 break;
1223
1224 case new_multi_array_id:
1225 { StubFrame f(sasm, "new_multi_array", dont_gc_arguments);
1226 // rax,: klass
1227 // rbx,: rank
1228 // rcx: address of 1st dimension
1229 OopMap* map = save_live_registers(sasm, 4);
1230 int call_offset = __ call_RT(rax, noreg, CAST_FROM_FN_PTR(address, new_multi_array), rax, rbx, rcx);
1231
1232 oop_maps = new OopMapSet();
1233 oop_maps->add_gc_map(call_offset, map);
1234 restore_live_registers_except_rax(sasm);
1235
1236 // rax,: new multi array
1237 __ verify_oop(rax);
1238 }
1239 break;
1240
1241 case register_finalizer_id:
1242 {
1243 __ set_info("register_finalizer", dont_gc_arguments);
1244
1245 // This is called via call_runtime so the arguments
1246 // will be place in C abi locations
1247
1248 #ifdef _LP64
1249 __ verify_oop(c_rarg0);
1250 __ mov(rax, c_rarg0);
1251 #else
1252 // The object is passed on the stack and we haven't pushed a
1253 // frame yet so it's one work away from top of stack.
1254 __ movptr(rax, Address(rsp, 1 * BytesPerWord));
1255 __ verify_oop(rax);
1256 #endif // _LP64
1257
1258 // load the klass and check the has finalizer flag
1259 Label register_finalizer;
1260 Register tmp_load_klass = LP64_ONLY(rscratch1) NOT_LP64(noreg);
1261 Register t = rsi;
1262 __ load_klass(t, rax, tmp_load_klass);
1263 __ movl(t, Address(t, Klass::access_flags_offset()));
1264 __ testl(t, JVM_ACC_HAS_FINALIZER);
1265 __ jcc(Assembler::notZero, register_finalizer);
1266 __ ret(0);
1267
1268 __ bind(register_finalizer);
1269 __ enter();
1270 OopMap* oop_map = save_live_registers(sasm, 2 /*num_rt_args */);
1271 int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, SharedRuntime::register_finalizer), rax);
1272 oop_maps = new OopMapSet();
1273 oop_maps->add_gc_map(call_offset, oop_map);
1274
1275 // Now restore all the live registers
1276 restore_live_registers(sasm);
1277
1278 __ leave();
1279 __ ret(0);
1280 }
1281 break;
1282
1283 case throw_range_check_failed_id:
1284 { StubFrame f(sasm, "range_check_failed", dont_gc_arguments);
1285 oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_range_check_exception), true);
1286 }
1287 break;
1288
1289 case throw_index_exception_id:
1290 { StubFrame f(sasm, "index_range_check_failed", dont_gc_arguments);
1291 oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_index_exception), true);
1292 }
1293 break;
1294
1295 case throw_div0_exception_id:
1296 { StubFrame f(sasm, "throw_div0_exception", dont_gc_arguments);
1297 oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_div0_exception), false);
1298 }
1299 break;
1300
1301 case throw_null_pointer_exception_id:
1302 { StubFrame f(sasm, "throw_null_pointer_exception", dont_gc_arguments);
1303 oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_null_pointer_exception), false);
1304 }
1305 break;
1306
1307 case handle_exception_nofpu_id:
1308 case handle_exception_id:
1309 { StubFrame f(sasm, "handle_exception", dont_gc_arguments);
1310 oop_maps = generate_handle_exception(id, sasm);
1311 }
1312 break;
1313
1314 case handle_exception_from_callee_id:
1315 { StubFrame f(sasm, "handle_exception_from_callee", dont_gc_arguments);
1316 oop_maps = generate_handle_exception(id, sasm);
1317 }
1318 break;
1319
1320 case unwind_exception_id:
1321 { __ set_info("unwind_exception", dont_gc_arguments);
1322 // note: no stubframe since we are about to leave the current
1323 // activation and we are calling a leaf VM function only.
1324 generate_unwind_exception(sasm);
1325 }
1326 break;
1327
1328 case throw_array_store_exception_id:
1329 { StubFrame f(sasm, "throw_array_store_exception", dont_gc_arguments);
1330 // tos + 0: link
1331 // + 1: return address
1332 oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_array_store_exception), true);
1333 }
1334 break;
1335
1336 case throw_class_cast_exception_id:
1337 { StubFrame f(sasm, "throw_class_cast_exception", dont_gc_arguments);
1338 oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_class_cast_exception), true);
1339 }
1340 break;
1341
1342 case throw_incompatible_class_change_error_id:
1343 { StubFrame f(sasm, "throw_incompatible_class_cast_exception", dont_gc_arguments);
1344 oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_incompatible_class_change_error), false);
1345 }
1346 break;
1347
1348 case slow_subtype_check_id:
1349 {
1350 // Typical calling sequence:
1351 // __ push(klass_RInfo); // object klass or other subclass
1352 // __ push(sup_k_RInfo); // array element klass or other superclass
1353 // __ call(slow_subtype_check);
1354 // Note that the subclass is pushed first, and is therefore deepest.
1355 // Previous versions of this code reversed the names 'sub' and 'super'.
1356 // This was operationally harmless but made the code unreadable.
1357 enum layout {
1358 rax_off, SLOT2(raxH_off)
1359 rcx_off, SLOT2(rcxH_off)
1360 rsi_off, SLOT2(rsiH_off)
1361 rdi_off, SLOT2(rdiH_off)
1362 // saved_rbp_off, SLOT2(saved_rbpH_off)
1363 return_off, SLOT2(returnH_off)
1364 sup_k_off, SLOT2(sup_kH_off)
1365 klass_off, SLOT2(superH_off)
1366 framesize,
1367 result_off = klass_off // deepest argument is also the return value
1368 };
1369
1370 __ set_info("slow_subtype_check", dont_gc_arguments);
1371 __ push(rdi);
1372 __ push(rsi);
1373 __ push(rcx);
1374 __ push(rax);
1375
1376 // This is called by pushing args and not with C abi
1377 __ movptr(rsi, Address(rsp, (klass_off) * VMRegImpl::stack_slot_size)); // subclass
1378 __ movptr(rax, Address(rsp, (sup_k_off) * VMRegImpl::stack_slot_size)); // superclass
1379
1380 Label miss;
1381 __ check_klass_subtype_slow_path(rsi, rax, rcx, rdi, NULL, &miss);
1382
1383 // fallthrough on success:
1384 __ movptr(Address(rsp, (result_off) * VMRegImpl::stack_slot_size), 1); // result
1385 __ pop(rax);
1386 __ pop(rcx);
1387 __ pop(rsi);
1388 __ pop(rdi);
1389 __ ret(0);
1390
1391 __ bind(miss);
1392 __ movptr(Address(rsp, (result_off) * VMRegImpl::stack_slot_size), NULL_WORD); // result
1393 __ pop(rax);
1394 __ pop(rcx);
1395 __ pop(rsi);
1396 __ pop(rdi);
1397 __ ret(0);
1398 }
1399 break;
1400
1401 case monitorenter_nofpu_id:
1402 save_fpu_registers = false;
1403 // fall through
1404 case monitorenter_id:
1405 {
1406 StubFrame f(sasm, "monitorenter", dont_gc_arguments);
1407 OopMap* map = save_live_registers(sasm, 3, save_fpu_registers);
1408
1409 // Called with store_parameter and not C abi
1410
1411 f.load_argument(1, rax); // rax,: object
1412 f.load_argument(0, rbx); // rbx,: lock address
1413
1414 int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, monitorenter), rax, rbx);
1415
1416 oop_maps = new OopMapSet();
1417 oop_maps->add_gc_map(call_offset, map);
1418 restore_live_registers(sasm, save_fpu_registers);
1419 }
1420 break;
1421
1422 case monitorexit_nofpu_id:
1423 save_fpu_registers = false;
1424 // fall through
1425 case monitorexit_id:
1426 {
1427 StubFrame f(sasm, "monitorexit", dont_gc_arguments);
1428 OopMap* map = save_live_registers(sasm, 2, save_fpu_registers);
1429
1430 // Called with store_parameter and not C abi
1431
1432 f.load_argument(0, rax); // rax,: lock address
1433
1434 // note: really a leaf routine but must setup last java sp
1435 // => use call_RT for now (speed can be improved by
1436 // doing last java sp setup manually)
1437 int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, monitorexit), rax);
1438
1439 oop_maps = new OopMapSet();
1440 oop_maps->add_gc_map(call_offset, map);
1441 restore_live_registers(sasm, save_fpu_registers);
1442 }
1443 break;
1444
1445 case deoptimize_id:
1446 {
1447 StubFrame f(sasm, "deoptimize", dont_gc_arguments);
1448 const int num_rt_args = 2; // thread, trap_request
1449 OopMap* oop_map = save_live_registers(sasm, num_rt_args);
1450 f.load_argument(0, rax);
1451 int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, deoptimize), rax);
1452 oop_maps = new OopMapSet();
1453 oop_maps->add_gc_map(call_offset, oop_map);
1454 restore_live_registers(sasm);
1455 DeoptimizationBlob* deopt_blob = SharedRuntime::deopt_blob();
1456 assert(deopt_blob != NULL, "deoptimization blob must have been created");
1457 __ leave();
1458 __ jump(RuntimeAddress(deopt_blob->unpack_with_reexecution()));
1459 }
1460 break;
1461
1462 case access_field_patching_id:
1463 { StubFrame f(sasm, "access_field_patching", dont_gc_arguments);
1464 // we should set up register map
1465 oop_maps = generate_patching(sasm, CAST_FROM_FN_PTR(address, access_field_patching));
1466 }
1467 break;
1468
1469 case load_klass_patching_id:
1470 { StubFrame f(sasm, "load_klass_patching", dont_gc_arguments);
1471 // we should set up register map
1472 oop_maps = generate_patching(sasm, CAST_FROM_FN_PTR(address, move_klass_patching));
1473 }
1474 break;
1475
1476 case load_mirror_patching_id:
1477 { StubFrame f(sasm, "load_mirror_patching", dont_gc_arguments);
1478 // we should set up register map
1479 oop_maps = generate_patching(sasm, CAST_FROM_FN_PTR(address, move_mirror_patching));
1480 }
1481 break;
1482
1483 case load_appendix_patching_id:
1484 { StubFrame f(sasm, "load_appendix_patching", dont_gc_arguments);
1485 // we should set up register map
1486 oop_maps = generate_patching(sasm, CAST_FROM_FN_PTR(address, move_appendix_patching));
1487 }
1488 break;
1489
1490 case dtrace_object_alloc_id:
1491 { // rax,: object
1492 StubFrame f(sasm, "dtrace_object_alloc", dont_gc_arguments);
1493 // we can't gc here so skip the oopmap but make sure that all
1494 // the live registers get saved.
1495 save_live_registers(sasm, 1);
1496
1497 __ NOT_LP64(push(rax)) LP64_ONLY(mov(c_rarg0, rax));
1498 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, static_cast<int (*)(oopDesc*)>(SharedRuntime::dtrace_object_alloc))));
1499 NOT_LP64(__ pop(rax));
1500
1501 restore_live_registers(sasm);
1502 }
1503 break;
1504
1505 case fpu2long_stub_id:
1506 {
1507 #ifdef _LP64
1508 Label done;
1509 __ cvttsd2siq(rax, Address(rsp, wordSize));
1510 __ cmp64(rax, ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
1511 __ jccb(Assembler::notEqual, done);
1512 __ movq(rax, Address(rsp, wordSize));
1513 __ subptr(rsp, 8);
1514 __ movq(Address(rsp, 0), rax);
1515 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2l_fixup())));
1516 __ pop(rax);
1517 __ bind(done);
1518 __ ret(0);
1519 #else
1520 // rax, and rdx are destroyed, but should be free since the result is returned there
1521 // preserve rsi,ecx
1522 __ push(rsi);
1523 __ push(rcx);
1524
1525 // check for NaN
1526 Label return0, do_return, return_min_jlong, do_convert;
1527
1528 Address value_high_word(rsp, wordSize + 4);
1529 Address value_low_word(rsp, wordSize);
1530 Address result_high_word(rsp, 3*wordSize + 4);
1531 Address result_low_word(rsp, 3*wordSize);
1532
1533 __ subptr(rsp, 32); // more than enough on 32bit
1534 __ fst_d(value_low_word);
1535 __ movl(rax, value_high_word);
1536 __ andl(rax, 0x7ff00000);
1537 __ cmpl(rax, 0x7ff00000);
1538 __ jcc(Assembler::notEqual, do_convert);
1539 __ movl(rax, value_high_word);
1540 __ andl(rax, 0xfffff);
1541 __ orl(rax, value_low_word);
1542 __ jcc(Assembler::notZero, return0);
1543
1544 __ bind(do_convert);
1545 __ fnstcw(Address(rsp, 0));
1546 __ movzwl(rax, Address(rsp, 0));
1547 __ orl(rax, 0xc00);
1548 __ movw(Address(rsp, 2), rax);
1549 __ fldcw(Address(rsp, 2));
1550 __ fwait();
1551 __ fistp_d(result_low_word);
1552 __ fldcw(Address(rsp, 0));
1553 __ fwait();
1554 // This gets the entire long in rax on 64bit
1555 __ movptr(rax, result_low_word);
1556 // testing of high bits
1557 __ movl(rdx, result_high_word);
1558 __ mov(rcx, rax);
1559 // What the heck is the point of the next instruction???
1560 __ xorl(rcx, 0x0);
1561 __ movl(rsi, 0x80000000);
1562 __ xorl(rsi, rdx);
1563 __ orl(rcx, rsi);
1564 __ jcc(Assembler::notEqual, do_return);
1565 __ fldz();
1566 __ fcomp_d(value_low_word);
1567 __ fnstsw_ax();
1568 __ sahf();
1569 __ jcc(Assembler::above, return_min_jlong);
1570 // return max_jlong
1571 __ movl(rdx, 0x7fffffff);
1572 __ movl(rax, 0xffffffff);
1573 __ jmp(do_return);
1574
1575 __ bind(return_min_jlong);
1576 __ movl(rdx, 0x80000000);
1577 __ xorl(rax, rax);
1578 __ jmp(do_return);
1579
1580 __ bind(return0);
1581 __ fpop();
1582 __ xorptr(rdx,rdx);
1583 __ xorptr(rax,rax);
1584
1585 __ bind(do_return);
1586 __ addptr(rsp, 32);
1587 __ pop(rcx);
1588 __ pop(rsi);
1589 __ ret(0);
1590 #endif // _LP64
1591 }
1592 break;
1593
1594 case predicate_failed_trap_id:
1595 {
1596 StubFrame f(sasm, "predicate_failed_trap", dont_gc_arguments);
1597
1598 OopMap* map = save_live_registers(sasm, 1);
1599
1600 int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, predicate_failed_trap));
1601 oop_maps = new OopMapSet();
1602 oop_maps->add_gc_map(call_offset, map);
1603 restore_live_registers(sasm);
1604 __ leave();
1605 DeoptimizationBlob* deopt_blob = SharedRuntime::deopt_blob();
1606 assert(deopt_blob != NULL, "deoptimization blob must have been created");
1607
1608 __ jump(RuntimeAddress(deopt_blob->unpack_with_reexecution()));
1609 }
1610 break;
1611
1612 default:
1613 { StubFrame f(sasm, "unimplemented entry", dont_gc_arguments);
1614 __ movptr(rax, (int)id);
1615 __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, unimplemented_entry), rax);
1616 __ should_not_reach_here();
1617 }
1618 break;
1619 }
1620 return oop_maps;
1621 }
1622
1623 #undef __
1624
1625 const char *Runtime1::pd_name_for_address(address entry) {
1626 return "<unknown function>";
1627 }