1 /*
2 * Copyright (c) 1997, 2021, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "jvm.h"
27 #include "asm/assembler.hpp"
28 #include "asm/assembler.inline.hpp"
29 #include "compiler/compiler_globals.hpp"
30 #include "compiler/disassembler.hpp"
31 #include "gc/shared/barrierSet.hpp"
32 #include "gc/shared/barrierSetAssembler.hpp"
33 #include "gc/shared/collectedHeap.inline.hpp"
34 #include "gc/shared/tlab_globals.hpp"
35 #include "interpreter/bytecodeHistogram.hpp"
36 #include "interpreter/interpreter.hpp"
37 #include "memory/resourceArea.hpp"
38 #include "memory/universe.hpp"
39 #include "oops/accessDecorators.hpp"
40 #include "oops/compressedOops.inline.hpp"
41 #include "oops/klass.inline.hpp"
42 #include "prims/methodHandles.hpp"
43 #include "runtime/flags/flagSetting.hpp"
44 #include "runtime/interfaceSupport.inline.hpp"
45 #include "runtime/jniHandles.hpp"
46 #include "runtime/objectMonitor.hpp"
47 #include "runtime/os.hpp"
48 #include "runtime/safepoint.hpp"
49 #include "runtime/safepointMechanism.hpp"
50 #include "runtime/sharedRuntime.hpp"
51 #include "runtime/stubRoutines.hpp"
52 #include "runtime/thread.hpp"
53 #include "utilities/macros.hpp"
54 #include "crc32c.h"
55
56 #ifdef PRODUCT
57 #define BLOCK_COMMENT(str) /* nothing */
58 #define STOP(error) stop(error)
59 #else
60 #define BLOCK_COMMENT(str) block_comment(str)
61 #define STOP(error) block_comment(error); stop(error)
62 #endif
63
64 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
65
66 #ifdef ASSERT
67 bool AbstractAssembler::pd_check_instruction_mark() { return true; }
68 #endif
69
70 static Assembler::Condition reverse[] = {
71 Assembler::noOverflow /* overflow = 0x0 */ ,
72 Assembler::overflow /* noOverflow = 0x1 */ ,
73 Assembler::aboveEqual /* carrySet = 0x2, below = 0x2 */ ,
74 Assembler::below /* aboveEqual = 0x3, carryClear = 0x3 */ ,
75 Assembler::notZero /* zero = 0x4, equal = 0x4 */ ,
76 Assembler::zero /* notZero = 0x5, notEqual = 0x5 */ ,
77 Assembler::above /* belowEqual = 0x6 */ ,
78 Assembler::belowEqual /* above = 0x7 */ ,
79 Assembler::positive /* negative = 0x8 */ ,
80 Assembler::negative /* positive = 0x9 */ ,
81 Assembler::noParity /* parity = 0xa */ ,
82 Assembler::parity /* noParity = 0xb */ ,
83 Assembler::greaterEqual /* less = 0xc */ ,
84 Assembler::less /* greaterEqual = 0xd */ ,
85 Assembler::greater /* lessEqual = 0xe */ ,
86 Assembler::lessEqual /* greater = 0xf, */
87
88 };
89
90
91 // Implementation of MacroAssembler
92
93 // First all the versions that have distinct versions depending on 32/64 bit
94 // Unless the difference is trivial (1 line or so).
95
96 #ifndef _LP64
97
98 // 32bit versions
99
100 Address MacroAssembler::as_Address(AddressLiteral adr) {
101 return Address(adr.target(), adr.rspec());
102 }
103
104 Address MacroAssembler::as_Address(ArrayAddress adr) {
105 return Address::make_array(adr);
106 }
107
108 void MacroAssembler::call_VM_leaf_base(address entry_point,
109 int number_of_arguments) {
110 call(RuntimeAddress(entry_point));
111 increment(rsp, number_of_arguments * wordSize);
112 }
113
114 void MacroAssembler::cmpklass(Address src1, Metadata* obj) {
115 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate());
116 }
117
118
119 void MacroAssembler::cmpklass(Register src1, Metadata* obj) {
120 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate());
121 }
122
123 void MacroAssembler::cmpoop(Address src1, jobject obj) {
124 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
125 }
126
127 void MacroAssembler::cmpoop(Register src1, jobject obj) {
128 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
129 }
130
131 void MacroAssembler::extend_sign(Register hi, Register lo) {
132 // According to Intel Doc. AP-526, "Integer Divide", p.18.
133 if (VM_Version::is_P6() && hi == rdx && lo == rax) {
134 cdql();
135 } else {
136 movl(hi, lo);
137 sarl(hi, 31);
138 }
139 }
140
141 void MacroAssembler::jC2(Register tmp, Label& L) {
142 // set parity bit if FPU flag C2 is set (via rax)
143 save_rax(tmp);
144 fwait(); fnstsw_ax();
145 sahf();
146 restore_rax(tmp);
147 // branch
148 jcc(Assembler::parity, L);
149 }
150
151 void MacroAssembler::jnC2(Register tmp, Label& L) {
152 // set parity bit if FPU flag C2 is set (via rax)
153 save_rax(tmp);
154 fwait(); fnstsw_ax();
155 sahf();
156 restore_rax(tmp);
157 // branch
158 jcc(Assembler::noParity, L);
159 }
160
161 // 32bit can do a case table jump in one instruction but we no longer allow the base
162 // to be installed in the Address class
163 void MacroAssembler::jump(ArrayAddress entry) {
164 jmp(as_Address(entry));
165 }
166
167 // Note: y_lo will be destroyed
168 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
169 // Long compare for Java (semantics as described in JVM spec.)
170 Label high, low, done;
171
172 cmpl(x_hi, y_hi);
173 jcc(Assembler::less, low);
174 jcc(Assembler::greater, high);
175 // x_hi is the return register
176 xorl(x_hi, x_hi);
177 cmpl(x_lo, y_lo);
178 jcc(Assembler::below, low);
179 jcc(Assembler::equal, done);
180
181 bind(high);
182 xorl(x_hi, x_hi);
183 increment(x_hi);
184 jmp(done);
185
186 bind(low);
187 xorl(x_hi, x_hi);
188 decrementl(x_hi);
189
190 bind(done);
191 }
192
193 void MacroAssembler::lea(Register dst, AddressLiteral src) {
194 mov_literal32(dst, (int32_t)src.target(), src.rspec());
195 }
196
197 void MacroAssembler::lea(Address dst, AddressLiteral adr) {
198 // leal(dst, as_Address(adr));
199 // see note in movl as to why we must use a move
200 mov_literal32(dst, (int32_t) adr.target(), adr.rspec());
201 }
202
203 void MacroAssembler::leave() {
204 mov(rsp, rbp);
205 pop(rbp);
206 }
207
208 void MacroAssembler::lmul(int x_rsp_offset, int y_rsp_offset) {
209 // Multiplication of two Java long values stored on the stack
210 // as illustrated below. Result is in rdx:rax.
211 //
212 // rsp ---> [ ?? ] \ \
213 // .... | y_rsp_offset |
214 // [ y_lo ] / (in bytes) | x_rsp_offset
215 // [ y_hi ] | (in bytes)
216 // .... |
217 // [ x_lo ] /
218 // [ x_hi ]
219 // ....
220 //
221 // Basic idea: lo(result) = lo(x_lo * y_lo)
222 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
223 Address x_hi(rsp, x_rsp_offset + wordSize); Address x_lo(rsp, x_rsp_offset);
224 Address y_hi(rsp, y_rsp_offset + wordSize); Address y_lo(rsp, y_rsp_offset);
225 Label quick;
226 // load x_hi, y_hi and check if quick
227 // multiplication is possible
228 movl(rbx, x_hi);
229 movl(rcx, y_hi);
230 movl(rax, rbx);
231 orl(rbx, rcx); // rbx, = 0 <=> x_hi = 0 and y_hi = 0
232 jcc(Assembler::zero, quick); // if rbx, = 0 do quick multiply
233 // do full multiplication
234 // 1st step
235 mull(y_lo); // x_hi * y_lo
236 movl(rbx, rax); // save lo(x_hi * y_lo) in rbx,
237 // 2nd step
238 movl(rax, x_lo);
239 mull(rcx); // x_lo * y_hi
240 addl(rbx, rax); // add lo(x_lo * y_hi) to rbx,
241 // 3rd step
242 bind(quick); // note: rbx, = 0 if quick multiply!
243 movl(rax, x_lo);
244 mull(y_lo); // x_lo * y_lo
245 addl(rdx, rbx); // correct hi(x_lo * y_lo)
246 }
247
248 void MacroAssembler::lneg(Register hi, Register lo) {
249 negl(lo);
250 adcl(hi, 0);
251 negl(hi);
252 }
253
254 void MacroAssembler::lshl(Register hi, Register lo) {
255 // Java shift left long support (semantics as described in JVM spec., p.305)
256 // (basic idea for shift counts s >= n: x << s == (x << n) << (s - n))
257 // shift value is in rcx !
258 assert(hi != rcx, "must not use rcx");
259 assert(lo != rcx, "must not use rcx");
260 const Register s = rcx; // shift count
261 const int n = BitsPerWord;
262 Label L;
263 andl(s, 0x3f); // s := s & 0x3f (s < 0x40)
264 cmpl(s, n); // if (s < n)
265 jcc(Assembler::less, L); // else (s >= n)
266 movl(hi, lo); // x := x << n
267 xorl(lo, lo);
268 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
269 bind(L); // s (mod n) < n
270 shldl(hi, lo); // x := x << s
271 shll(lo);
272 }
273
274
275 void MacroAssembler::lshr(Register hi, Register lo, bool sign_extension) {
276 // Java shift right long support (semantics as described in JVM spec., p.306 & p.310)
277 // (basic idea for shift counts s >= n: x >> s == (x >> n) >> (s - n))
278 assert(hi != rcx, "must not use rcx");
279 assert(lo != rcx, "must not use rcx");
280 const Register s = rcx; // shift count
281 const int n = BitsPerWord;
282 Label L;
283 andl(s, 0x3f); // s := s & 0x3f (s < 0x40)
284 cmpl(s, n); // if (s < n)
285 jcc(Assembler::less, L); // else (s >= n)
286 movl(lo, hi); // x := x >> n
287 if (sign_extension) sarl(hi, 31);
288 else xorl(hi, hi);
289 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
290 bind(L); // s (mod n) < n
291 shrdl(lo, hi); // x := x >> s
292 if (sign_extension) sarl(hi);
293 else shrl(hi);
294 }
295
296 void MacroAssembler::movoop(Register dst, jobject obj) {
297 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
298 }
299
300 void MacroAssembler::movoop(Address dst, jobject obj) {
301 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
302 }
303
304 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
305 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate());
306 }
307
308 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) {
309 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate());
310 }
311
312 void MacroAssembler::movptr(Register dst, AddressLiteral src, Register scratch) {
313 // scratch register is not used,
314 // it is defined to match parameters of 64-bit version of this method.
315 if (src.is_lval()) {
316 mov_literal32(dst, (intptr_t)src.target(), src.rspec());
317 } else {
318 movl(dst, as_Address(src));
319 }
320 }
321
322 void MacroAssembler::movptr(ArrayAddress dst, Register src) {
323 movl(as_Address(dst), src);
324 }
325
326 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
327 movl(dst, as_Address(src));
328 }
329
330 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
331 void MacroAssembler::movptr(Address dst, intptr_t src) {
332 movl(dst, src);
333 }
334
335
336 void MacroAssembler::pop_callee_saved_registers() {
337 pop(rcx);
338 pop(rdx);
339 pop(rdi);
340 pop(rsi);
341 }
342
343 void MacroAssembler::push_callee_saved_registers() {
344 push(rsi);
345 push(rdi);
346 push(rdx);
347 push(rcx);
348 }
349
350 void MacroAssembler::pushoop(jobject obj) {
351 push_literal32((int32_t)obj, oop_Relocation::spec_for_immediate());
352 }
353
354 void MacroAssembler::pushklass(Metadata* obj) {
355 push_literal32((int32_t)obj, metadata_Relocation::spec_for_immediate());
356 }
357
358 void MacroAssembler::pushptr(AddressLiteral src) {
359 if (src.is_lval()) {
360 push_literal32((int32_t)src.target(), src.rspec());
361 } else {
362 pushl(as_Address(src));
363 }
364 }
365
366 static void pass_arg0(MacroAssembler* masm, Register arg) {
367 masm->push(arg);
368 }
369
370 static void pass_arg1(MacroAssembler* masm, Register arg) {
371 masm->push(arg);
372 }
373
374 static void pass_arg2(MacroAssembler* masm, Register arg) {
375 masm->push(arg);
376 }
377
378 static void pass_arg3(MacroAssembler* masm, Register arg) {
379 masm->push(arg);
380 }
381
382 #ifndef PRODUCT
383 extern "C" void findpc(intptr_t x);
384 #endif
385
386 void MacroAssembler::debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg) {
387 // In order to get locks to work, we need to fake a in_VM state
388 JavaThread* thread = JavaThread::current();
389 JavaThreadState saved_state = thread->thread_state();
390 thread->set_thread_state(_thread_in_vm);
391 if (ShowMessageBoxOnError) {
392 JavaThread* thread = JavaThread::current();
393 JavaThreadState saved_state = thread->thread_state();
394 thread->set_thread_state(_thread_in_vm);
395 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
396 ttyLocker ttyl;
397 BytecodeCounter::print();
398 }
399 // To see where a verify_oop failed, get $ebx+40/X for this frame.
400 // This is the value of eip which points to where verify_oop will return.
401 if (os::message_box(msg, "Execution stopped, print registers?")) {
402 print_state32(rdi, rsi, rbp, rsp, rbx, rdx, rcx, rax, eip);
403 BREAKPOINT;
404 }
405 }
406 fatal("DEBUG MESSAGE: %s", msg);
407 }
408
409 void MacroAssembler::print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip) {
410 ttyLocker ttyl;
411 FlagSetting fs(Debugging, true);
412 tty->print_cr("eip = 0x%08x", eip);
413 #ifndef PRODUCT
414 if ((WizardMode || Verbose) && PrintMiscellaneous) {
415 tty->cr();
416 findpc(eip);
417 tty->cr();
418 }
419 #endif
420 #define PRINT_REG(rax) \
421 { tty->print("%s = ", #rax); os::print_location(tty, rax); }
422 PRINT_REG(rax);
423 PRINT_REG(rbx);
424 PRINT_REG(rcx);
425 PRINT_REG(rdx);
426 PRINT_REG(rdi);
427 PRINT_REG(rsi);
428 PRINT_REG(rbp);
429 PRINT_REG(rsp);
430 #undef PRINT_REG
431 // Print some words near top of staack.
432 int* dump_sp = (int*) rsp;
433 for (int col1 = 0; col1 < 8; col1++) {
434 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
435 os::print_location(tty, *dump_sp++);
436 }
437 for (int row = 0; row < 16; row++) {
438 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
439 for (int col = 0; col < 8; col++) {
440 tty->print(" 0x%08x", *dump_sp++);
441 }
442 tty->cr();
443 }
444 // Print some instructions around pc:
445 Disassembler::decode((address)eip-64, (address)eip);
446 tty->print_cr("--------");
447 Disassembler::decode((address)eip, (address)eip+32);
448 }
449
450 void MacroAssembler::stop(const char* msg) {
451 ExternalAddress message((address)msg);
452 // push address of message
453 pushptr(message.addr());
454 { Label L; call(L, relocInfo::none); bind(L); } // push eip
455 pusha(); // push registers
456 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug32)));
457 hlt();
458 }
459
460 void MacroAssembler::warn(const char* msg) {
461 push_CPU_state();
462
463 ExternalAddress message((address) msg);
464 // push address of message
465 pushptr(message.addr());
466
467 call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning)));
468 addl(rsp, wordSize); // discard argument
469 pop_CPU_state();
470 }
471
472 void MacroAssembler::print_state() {
473 { Label L; call(L, relocInfo::none); bind(L); } // push eip
474 pusha(); // push registers
475
476 push_CPU_state();
477 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::print_state32)));
478 pop_CPU_state();
479
480 popa();
481 addl(rsp, wordSize);
482 }
483
484 #else // _LP64
485
486 // 64 bit versions
487
488 Address MacroAssembler::as_Address(AddressLiteral adr) {
489 // amd64 always does this as a pc-rel
490 // we can be absolute or disp based on the instruction type
491 // jmp/call are displacements others are absolute
492 assert(!adr.is_lval(), "must be rval");
493 assert(reachable(adr), "must be");
494 return Address((int32_t)(intptr_t)(adr.target() - pc()), adr.target(), adr.reloc());
495
496 }
497
498 Address MacroAssembler::as_Address(ArrayAddress adr) {
499 AddressLiteral base = adr.base();
500 lea(rscratch1, base);
501 Address index = adr.index();
502 assert(index._disp == 0, "must not have disp"); // maybe it can?
503 Address array(rscratch1, index._index, index._scale, index._disp);
504 return array;
505 }
506
507 void MacroAssembler::call_VM_leaf_base(address entry_point, int num_args) {
508 Label L, E;
509
510 #ifdef _WIN64
511 // Windows always allocates space for it's register args
512 assert(num_args <= 4, "only register arguments supported");
513 subq(rsp, frame::arg_reg_save_area_bytes);
514 #endif
515
516 // Align stack if necessary
517 testl(rsp, 15);
518 jcc(Assembler::zero, L);
519
520 subq(rsp, 8);
521 {
522 call(RuntimeAddress(entry_point));
523 }
524 addq(rsp, 8);
525 jmp(E);
526
527 bind(L);
528 {
529 call(RuntimeAddress(entry_point));
530 }
531
532 bind(E);
533
534 #ifdef _WIN64
535 // restore stack pointer
536 addq(rsp, frame::arg_reg_save_area_bytes);
537 #endif
538
539 }
540
541 void MacroAssembler::cmp64(Register src1, AddressLiteral src2) {
542 assert(!src2.is_lval(), "should use cmpptr");
543
544 if (reachable(src2)) {
545 cmpq(src1, as_Address(src2));
546 } else {
547 lea(rscratch1, src2);
548 Assembler::cmpq(src1, Address(rscratch1, 0));
549 }
550 }
551
552 int MacroAssembler::corrected_idivq(Register reg) {
553 // Full implementation of Java ldiv and lrem; checks for special
554 // case as described in JVM spec., p.243 & p.271. The function
555 // returns the (pc) offset of the idivl instruction - may be needed
556 // for implicit exceptions.
557 //
558 // normal case special case
559 //
560 // input : rax: dividend min_long
561 // reg: divisor (may not be eax/edx) -1
562 //
563 // output: rax: quotient (= rax idiv reg) min_long
564 // rdx: remainder (= rax irem reg) 0
565 assert(reg != rax && reg != rdx, "reg cannot be rax or rdx register");
566 static const int64_t min_long = 0x8000000000000000;
567 Label normal_case, special_case;
568
569 // check for special case
570 cmp64(rax, ExternalAddress((address) &min_long));
571 jcc(Assembler::notEqual, normal_case);
572 xorl(rdx, rdx); // prepare rdx for possible special case (where
573 // remainder = 0)
574 cmpq(reg, -1);
575 jcc(Assembler::equal, special_case);
576
577 // handle normal case
578 bind(normal_case);
579 cdqq();
580 int idivq_offset = offset();
581 idivq(reg);
582
583 // normal and special case exit
584 bind(special_case);
585
586 return idivq_offset;
587 }
588
589 void MacroAssembler::decrementq(Register reg, int value) {
590 if (value == min_jint) { subq(reg, value); return; }
591 if (value < 0) { incrementq(reg, -value); return; }
592 if (value == 0) { ; return; }
593 if (value == 1 && UseIncDec) { decq(reg) ; return; }
594 /* else */ { subq(reg, value) ; return; }
595 }
596
597 void MacroAssembler::decrementq(Address dst, int value) {
598 if (value == min_jint) { subq(dst, value); return; }
599 if (value < 0) { incrementq(dst, -value); return; }
600 if (value == 0) { ; return; }
601 if (value == 1 && UseIncDec) { decq(dst) ; return; }
602 /* else */ { subq(dst, value) ; return; }
603 }
604
605 void MacroAssembler::incrementq(AddressLiteral dst) {
606 if (reachable(dst)) {
607 incrementq(as_Address(dst));
608 } else {
609 lea(rscratch1, dst);
610 incrementq(Address(rscratch1, 0));
611 }
612 }
613
614 void MacroAssembler::incrementq(Register reg, int value) {
615 if (value == min_jint) { addq(reg, value); return; }
616 if (value < 0) { decrementq(reg, -value); return; }
617 if (value == 0) { ; return; }
618 if (value == 1 && UseIncDec) { incq(reg) ; return; }
619 /* else */ { addq(reg, value) ; return; }
620 }
621
622 void MacroAssembler::incrementq(Address dst, int value) {
623 if (value == min_jint) { addq(dst, value); return; }
624 if (value < 0) { decrementq(dst, -value); return; }
625 if (value == 0) { ; return; }
626 if (value == 1 && UseIncDec) { incq(dst) ; return; }
627 /* else */ { addq(dst, value) ; return; }
628 }
629
630 // 32bit can do a case table jump in one instruction but we no longer allow the base
631 // to be installed in the Address class
632 void MacroAssembler::jump(ArrayAddress entry) {
633 lea(rscratch1, entry.base());
634 Address dispatch = entry.index();
635 assert(dispatch._base == noreg, "must be");
636 dispatch._base = rscratch1;
637 jmp(dispatch);
638 }
639
640 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
641 ShouldNotReachHere(); // 64bit doesn't use two regs
642 cmpq(x_lo, y_lo);
643 }
644
645 void MacroAssembler::lea(Register dst, AddressLiteral src) {
646 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
647 }
648
649 void MacroAssembler::lea(Address dst, AddressLiteral adr) {
650 mov_literal64(rscratch1, (intptr_t)adr.target(), adr.rspec());
651 movptr(dst, rscratch1);
652 }
653
654 void MacroAssembler::leave() {
655 // %%% is this really better? Why not on 32bit too?
656 emit_int8((unsigned char)0xC9); // LEAVE
657 }
658
659 void MacroAssembler::lneg(Register hi, Register lo) {
660 ShouldNotReachHere(); // 64bit doesn't use two regs
661 negq(lo);
662 }
663
664 void MacroAssembler::movoop(Register dst, jobject obj) {
665 mov_literal64(dst, (intptr_t)obj, oop_Relocation::spec_for_immediate());
666 }
667
668 void MacroAssembler::movoop(Address dst, jobject obj) {
669 mov_literal64(rscratch1, (intptr_t)obj, oop_Relocation::spec_for_immediate());
670 movq(dst, rscratch1);
671 }
672
673 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
674 mov_literal64(dst, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
675 }
676
677 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) {
678 mov_literal64(rscratch1, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
679 movq(dst, rscratch1);
680 }
681
682 void MacroAssembler::movptr(Register dst, AddressLiteral src, Register scratch) {
683 if (src.is_lval()) {
684 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
685 } else {
686 if (reachable(src)) {
687 movq(dst, as_Address(src));
688 } else {
689 lea(scratch, src);
690 movq(dst, Address(scratch, 0));
691 }
692 }
693 }
694
695 void MacroAssembler::movptr(ArrayAddress dst, Register src) {
696 movq(as_Address(dst), src);
697 }
698
699 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
700 movq(dst, as_Address(src));
701 }
702
703 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
704 void MacroAssembler::movptr(Address dst, intptr_t src) {
705 if (is_simm32(src)) {
706 movptr(dst, checked_cast<int32_t>(src));
707 } else {
708 mov64(rscratch1, src);
709 movq(dst, rscratch1);
710 }
711 }
712
713 // These are mostly for initializing NULL
714 void MacroAssembler::movptr(Address dst, int32_t src) {
715 movslq(dst, src);
716 }
717
718 void MacroAssembler::movptr(Register dst, int32_t src) {
719 mov64(dst, (intptr_t)src);
720 }
721
722 void MacroAssembler::pushoop(jobject obj) {
723 movoop(rscratch1, obj);
724 push(rscratch1);
725 }
726
727 void MacroAssembler::pushklass(Metadata* obj) {
728 mov_metadata(rscratch1, obj);
729 push(rscratch1);
730 }
731
732 void MacroAssembler::pushptr(AddressLiteral src) {
733 lea(rscratch1, src);
734 if (src.is_lval()) {
735 push(rscratch1);
736 } else {
737 pushq(Address(rscratch1, 0));
738 }
739 }
740
741 void MacroAssembler::reset_last_Java_frame(bool clear_fp) {
742 reset_last_Java_frame(r15_thread, clear_fp);
743 }
744
745 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
746 Register last_java_fp,
747 address last_java_pc) {
748 vzeroupper();
749 // determine last_java_sp register
750 if (!last_java_sp->is_valid()) {
751 last_java_sp = rsp;
752 }
753
754 // last_java_fp is optional
755 if (last_java_fp->is_valid()) {
756 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()),
757 last_java_fp);
758 }
759
760 // last_java_pc is optional
761 if (last_java_pc != NULL) {
762 Address java_pc(r15_thread,
763 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset());
764 lea(rscratch1, InternalAddress(last_java_pc));
765 movptr(java_pc, rscratch1);
766 }
767
768 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
769 }
770
771 static void pass_arg0(MacroAssembler* masm, Register arg) {
772 if (c_rarg0 != arg ) {
773 masm->mov(c_rarg0, arg);
774 }
775 }
776
777 static void pass_arg1(MacroAssembler* masm, Register arg) {
778 if (c_rarg1 != arg ) {
779 masm->mov(c_rarg1, arg);
780 }
781 }
782
783 static void pass_arg2(MacroAssembler* masm, Register arg) {
784 if (c_rarg2 != arg ) {
785 masm->mov(c_rarg2, arg);
786 }
787 }
788
789 static void pass_arg3(MacroAssembler* masm, Register arg) {
790 if (c_rarg3 != arg ) {
791 masm->mov(c_rarg3, arg);
792 }
793 }
794
795 void MacroAssembler::stop(const char* msg) {
796 if (ShowMessageBoxOnError) {
797 address rip = pc();
798 pusha(); // get regs on stack
799 lea(c_rarg1, InternalAddress(rip));
800 movq(c_rarg2, rsp); // pass pointer to regs array
801 }
802 lea(c_rarg0, ExternalAddress((address) msg));
803 andq(rsp, -16); // align stack as required by ABI
804 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug64)));
805 hlt();
806 }
807
808 void MacroAssembler::warn(const char* msg) {
809 push(rbp);
810 movq(rbp, rsp);
811 andq(rsp, -16); // align stack as required by push_CPU_state and call
812 push_CPU_state(); // keeps alignment at 16 bytes
813 lea(c_rarg0, ExternalAddress((address) msg));
814 lea(rax, ExternalAddress(CAST_FROM_FN_PTR(address, warning)));
815 call(rax);
816 pop_CPU_state();
817 mov(rsp, rbp);
818 pop(rbp);
819 }
820
821 void MacroAssembler::print_state() {
822 address rip = pc();
823 pusha(); // get regs on stack
824 push(rbp);
825 movq(rbp, rsp);
826 andq(rsp, -16); // align stack as required by push_CPU_state and call
827 push_CPU_state(); // keeps alignment at 16 bytes
828
829 lea(c_rarg0, InternalAddress(rip));
830 lea(c_rarg1, Address(rbp, wordSize)); // pass pointer to regs array
831 call_VM_leaf(CAST_FROM_FN_PTR(address, MacroAssembler::print_state64), c_rarg0, c_rarg1);
832
833 pop_CPU_state();
834 mov(rsp, rbp);
835 pop(rbp);
836 popa();
837 }
838
839 #ifndef PRODUCT
840 extern "C" void findpc(intptr_t x);
841 #endif
842
843 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) {
844 // In order to get locks to work, we need to fake a in_VM state
845 if (ShowMessageBoxOnError) {
846 JavaThread* thread = JavaThread::current();
847 JavaThreadState saved_state = thread->thread_state();
848 thread->set_thread_state(_thread_in_vm);
849 #ifndef PRODUCT
850 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
851 ttyLocker ttyl;
852 BytecodeCounter::print();
853 }
854 #endif
855 // To see where a verify_oop failed, get $ebx+40/X for this frame.
856 // XXX correct this offset for amd64
857 // This is the value of eip which points to where verify_oop will return.
858 if (os::message_box(msg, "Execution stopped, print registers?")) {
859 print_state64(pc, regs);
860 BREAKPOINT;
861 }
862 }
863 fatal("DEBUG MESSAGE: %s", msg);
864 }
865
866 void MacroAssembler::print_state64(int64_t pc, int64_t regs[]) {
867 ttyLocker ttyl;
868 FlagSetting fs(Debugging, true);
869 tty->print_cr("rip = 0x%016lx", (intptr_t)pc);
870 #ifndef PRODUCT
871 tty->cr();
872 findpc(pc);
873 tty->cr();
874 #endif
875 #define PRINT_REG(rax, value) \
876 { tty->print("%s = ", #rax); os::print_location(tty, value); }
877 PRINT_REG(rax, regs[15]);
878 PRINT_REG(rbx, regs[12]);
879 PRINT_REG(rcx, regs[14]);
880 PRINT_REG(rdx, regs[13]);
881 PRINT_REG(rdi, regs[8]);
882 PRINT_REG(rsi, regs[9]);
883 PRINT_REG(rbp, regs[10]);
884 // rsp is actually not stored by pusha(), compute the old rsp from regs (rsp after pusha): regs + 16 = old rsp
885 PRINT_REG(rsp, (intptr_t)(®s[16]));
886 PRINT_REG(r8 , regs[7]);
887 PRINT_REG(r9 , regs[6]);
888 PRINT_REG(r10, regs[5]);
889 PRINT_REG(r11, regs[4]);
890 PRINT_REG(r12, regs[3]);
891 PRINT_REG(r13, regs[2]);
892 PRINT_REG(r14, regs[1]);
893 PRINT_REG(r15, regs[0]);
894 #undef PRINT_REG
895 // Print some words near the top of the stack.
896 int64_t* rsp = ®s[16];
897 int64_t* dump_sp = rsp;
898 for (int col1 = 0; col1 < 8; col1++) {
899 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
900 os::print_location(tty, *dump_sp++);
901 }
902 for (int row = 0; row < 25; row++) {
903 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
904 for (int col = 0; col < 4; col++) {
905 tty->print(" 0x%016lx", (intptr_t)*dump_sp++);
906 }
907 tty->cr();
908 }
909 // Print some instructions around pc:
910 Disassembler::decode((address)pc-64, (address)pc);
911 tty->print_cr("--------");
912 Disassembler::decode((address)pc, (address)pc+32);
913 }
914
915 // The java_calling_convention describes stack locations as ideal slots on
916 // a frame with no abi restrictions. Since we must observe abi restrictions
917 // (like the placement of the register window) the slots must be biased by
918 // the following value.
919 static int reg2offset_in(VMReg r) {
920 // Account for saved rbp and return address
921 // This should really be in_preserve_stack_slots
922 return (r->reg2stack() + 4) * VMRegImpl::stack_slot_size;
923 }
924
925 static int reg2offset_out(VMReg r) {
926 return (r->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size;
927 }
928
929 // A long move
930 void MacroAssembler::long_move(VMRegPair src, VMRegPair dst) {
931
932 // The calling conventions assures us that each VMregpair is either
933 // all really one physical register or adjacent stack slots.
934
935 if (src.is_single_phys_reg() ) {
936 if (dst.is_single_phys_reg()) {
937 if (dst.first() != src.first()) {
938 mov(dst.first()->as_Register(), src.first()->as_Register());
939 }
940 } else {
941 assert(dst.is_single_reg(), "not a stack pair");
942 movq(Address(rsp, reg2offset_out(dst.first())), src.first()->as_Register());
943 }
944 } else if (dst.is_single_phys_reg()) {
945 assert(src.is_single_reg(), "not a stack pair");
946 movq(dst.first()->as_Register(), Address(rbp, reg2offset_out(src.first())));
947 } else {
948 assert(src.is_single_reg() && dst.is_single_reg(), "not stack pairs");
949 movq(rax, Address(rbp, reg2offset_in(src.first())));
950 movq(Address(rsp, reg2offset_out(dst.first())), rax);
951 }
952 }
953
954 // A double move
955 void MacroAssembler::double_move(VMRegPair src, VMRegPair dst) {
956
957 // The calling conventions assures us that each VMregpair is either
958 // all really one physical register or adjacent stack slots.
959
960 if (src.is_single_phys_reg() ) {
961 if (dst.is_single_phys_reg()) {
962 // In theory these overlap but the ordering is such that this is likely a nop
963 if ( src.first() != dst.first()) {
964 movdbl(dst.first()->as_XMMRegister(), src.first()->as_XMMRegister());
965 }
966 } else {
967 assert(dst.is_single_reg(), "not a stack pair");
968 movdbl(Address(rsp, reg2offset_out(dst.first())), src.first()->as_XMMRegister());
969 }
970 } else if (dst.is_single_phys_reg()) {
971 assert(src.is_single_reg(), "not a stack pair");
972 movdbl(dst.first()->as_XMMRegister(), Address(rbp, reg2offset_out(src.first())));
973 } else {
974 assert(src.is_single_reg() && dst.is_single_reg(), "not stack pairs");
975 movq(rax, Address(rbp, reg2offset_in(src.first())));
976 movq(Address(rsp, reg2offset_out(dst.first())), rax);
977 }
978 }
979
980
981 // A float arg may have to do float reg int reg conversion
982 void MacroAssembler::float_move(VMRegPair src, VMRegPair dst) {
983 assert(!src.second()->is_valid() && !dst.second()->is_valid(), "bad float_move");
984
985 // The calling conventions assures us that each VMregpair is either
986 // all really one physical register or adjacent stack slots.
987
988 if (src.first()->is_stack()) {
989 if (dst.first()->is_stack()) {
990 movl(rax, Address(rbp, reg2offset_in(src.first())));
991 movptr(Address(rsp, reg2offset_out(dst.first())), rax);
992 } else {
993 // stack to reg
994 assert(dst.first()->is_XMMRegister(), "only expect xmm registers as parameters");
995 movflt(dst.first()->as_XMMRegister(), Address(rbp, reg2offset_in(src.first())));
996 }
997 } else if (dst.first()->is_stack()) {
998 // reg to stack
999 assert(src.first()->is_XMMRegister(), "only expect xmm registers as parameters");
1000 movflt(Address(rsp, reg2offset_out(dst.first())), src.first()->as_XMMRegister());
1001 } else {
1002 // reg to reg
1003 // In theory these overlap but the ordering is such that this is likely a nop
1004 if ( src.first() != dst.first()) {
1005 movdbl(dst.first()->as_XMMRegister(), src.first()->as_XMMRegister());
1006 }
1007 }
1008 }
1009
1010 // On 64 bit we will store integer like items to the stack as
1011 // 64 bits items (x86_32/64 abi) even though java would only store
1012 // 32bits for a parameter. On 32bit it will simply be 32 bits
1013 // So this routine will do 32->32 on 32bit and 32->64 on 64bit
1014 void MacroAssembler::move32_64(VMRegPair src, VMRegPair dst) {
1015 if (src.first()->is_stack()) {
1016 if (dst.first()->is_stack()) {
1017 // stack to stack
1018 movslq(rax, Address(rbp, reg2offset_in(src.first())));
1019 movq(Address(rsp, reg2offset_out(dst.first())), rax);
1020 } else {
1021 // stack to reg
1022 movslq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first())));
1023 }
1024 } else if (dst.first()->is_stack()) {
1025 // reg to stack
1026 // Do we really have to sign extend???
1027 // __ movslq(src.first()->as_Register(), src.first()->as_Register());
1028 movq(Address(rsp, reg2offset_out(dst.first())), src.first()->as_Register());
1029 } else {
1030 // Do we really have to sign extend???
1031 // __ movslq(dst.first()->as_Register(), src.first()->as_Register());
1032 if (dst.first() != src.first()) {
1033 movq(dst.first()->as_Register(), src.first()->as_Register());
1034 }
1035 }
1036 }
1037
1038 void MacroAssembler::move_ptr(VMRegPair src, VMRegPair dst) {
1039 if (src.first()->is_stack()) {
1040 if (dst.first()->is_stack()) {
1041 // stack to stack
1042 movq(rax, Address(rbp, reg2offset_in(src.first())));
1043 movq(Address(rsp, reg2offset_out(dst.first())), rax);
1044 } else {
1045 // stack to reg
1046 movq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first())));
1047 }
1048 } else if (dst.first()->is_stack()) {
1049 // reg to stack
1050 movq(Address(rsp, reg2offset_out(dst.first())), src.first()->as_Register());
1051 } else {
1052 if (dst.first() != src.first()) {
1053 movq(dst.first()->as_Register(), src.first()->as_Register());
1054 }
1055 }
1056 }
1057
1058 // An oop arg. Must pass a handle not the oop itself
1059 void MacroAssembler::object_move(OopMap* map,
1060 int oop_handle_offset,
1061 int framesize_in_slots,
1062 VMRegPair src,
1063 VMRegPair dst,
1064 bool is_receiver,
1065 int* receiver_offset) {
1066
1067 // must pass a handle. First figure out the location we use as a handle
1068
1069 Register rHandle = dst.first()->is_stack() ? rax : dst.first()->as_Register();
1070
1071 // See if oop is NULL if it is we need no handle
1072
1073 if (src.first()->is_stack()) {
1074
1075 // Oop is already on the stack as an argument
1076 int offset_in_older_frame = src.first()->reg2stack() + SharedRuntime::out_preserve_stack_slots();
1077 map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + framesize_in_slots));
1078 if (is_receiver) {
1079 *receiver_offset = (offset_in_older_frame + framesize_in_slots) * VMRegImpl::stack_slot_size;
1080 }
1081
1082 cmpptr(Address(rbp, reg2offset_in(src.first())), (int32_t)NULL_WORD);
1083 lea(rHandle, Address(rbp, reg2offset_in(src.first())));
1084 // conditionally move a NULL
1085 cmovptr(Assembler::equal, rHandle, Address(rbp, reg2offset_in(src.first())));
1086 } else {
1087
1088 // Oop is in an a register we must store it to the space we reserve
1089 // on the stack for oop_handles and pass a handle if oop is non-NULL
1090
1091 const Register rOop = src.first()->as_Register();
1092 int oop_slot;
1093 if (rOop == j_rarg0)
1094 oop_slot = 0;
1095 else if (rOop == j_rarg1)
1096 oop_slot = 1;
1097 else if (rOop == j_rarg2)
1098 oop_slot = 2;
1099 else if (rOop == j_rarg3)
1100 oop_slot = 3;
1101 else if (rOop == j_rarg4)
1102 oop_slot = 4;
1103 else {
1104 assert(rOop == j_rarg5, "wrong register");
1105 oop_slot = 5;
1106 }
1107
1108 oop_slot = oop_slot * VMRegImpl::slots_per_word + oop_handle_offset;
1109 int offset = oop_slot*VMRegImpl::stack_slot_size;
1110
1111 map->set_oop(VMRegImpl::stack2reg(oop_slot));
1112 // Store oop in handle area, may be NULL
1113 movptr(Address(rsp, offset), rOop);
1114 if (is_receiver) {
1115 *receiver_offset = offset;
1116 }
1117
1118 cmpptr(rOop, (int32_t)NULL_WORD);
1119 lea(rHandle, Address(rsp, offset));
1120 // conditionally move a NULL from the handle area where it was just stored
1121 cmovptr(Assembler::equal, rHandle, Address(rsp, offset));
1122 }
1123
1124 // If arg is on the stack then place it otherwise it is already in correct reg.
1125 if (dst.first()->is_stack()) {
1126 movptr(Address(rsp, reg2offset_out(dst.first())), rHandle);
1127 }
1128 }
1129
1130 #endif // _LP64
1131
1132 // Now versions that are common to 32/64 bit
1133
1134 void MacroAssembler::addptr(Register dst, int32_t imm32) {
1135 LP64_ONLY(addq(dst, imm32)) NOT_LP64(addl(dst, imm32));
1136 }
1137
1138 void MacroAssembler::addptr(Register dst, Register src) {
1139 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
1140 }
1141
1142 void MacroAssembler::addptr(Address dst, Register src) {
1143 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
1144 }
1145
1146 void MacroAssembler::addsd(XMMRegister dst, AddressLiteral src) {
1147 if (reachable(src)) {
1148 Assembler::addsd(dst, as_Address(src));
1149 } else {
1150 lea(rscratch1, src);
1151 Assembler::addsd(dst, Address(rscratch1, 0));
1152 }
1153 }
1154
1155 void MacroAssembler::addss(XMMRegister dst, AddressLiteral src) {
1156 if (reachable(src)) {
1157 addss(dst, as_Address(src));
1158 } else {
1159 lea(rscratch1, src);
1160 addss(dst, Address(rscratch1, 0));
1161 }
1162 }
1163
1164 void MacroAssembler::addpd(XMMRegister dst, AddressLiteral src) {
1165 if (reachable(src)) {
1166 Assembler::addpd(dst, as_Address(src));
1167 } else {
1168 lea(rscratch1, src);
1169 Assembler::addpd(dst, Address(rscratch1, 0));
1170 }
1171 }
1172
1173 // See 8273459. Function for ensuring 64-byte alignment, intended for stubs only.
1174 // Stub code is generated once and never copied.
1175 // NMethods can't use this because they get copied and we can't force alignment > 32 bytes.
1176 void MacroAssembler::align64() {
1177 align(64, (unsigned long long) pc());
1178 }
1179
1180 void MacroAssembler::align32() {
1181 align(32, (unsigned long long) pc());
1182 }
1183
1184 void MacroAssembler::align(int modulus) {
1185 // 8273459: Ensure alignment is possible with current segment alignment
1186 assert(modulus <= CodeEntryAlignment, "Alignment must be <= CodeEntryAlignment");
1187 align(modulus, offset());
1188 }
1189
1190 void MacroAssembler::align(int modulus, int target) {
1191 if (target % modulus != 0) {
1192 nop(modulus - (target % modulus));
1193 }
1194 }
1195
1196 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src, Register scratch_reg) {
1197 // Used in sign-masking with aligned address.
1198 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
1199 if (reachable(src)) {
1200 Assembler::andpd(dst, as_Address(src));
1201 } else {
1202 lea(scratch_reg, src);
1203 Assembler::andpd(dst, Address(scratch_reg, 0));
1204 }
1205 }
1206
1207 void MacroAssembler::andps(XMMRegister dst, AddressLiteral src, Register scratch_reg) {
1208 // Used in sign-masking with aligned address.
1209 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
1210 if (reachable(src)) {
1211 Assembler::andps(dst, as_Address(src));
1212 } else {
1213 lea(scratch_reg, src);
1214 Assembler::andps(dst, Address(scratch_reg, 0));
1215 }
1216 }
1217
1218 void MacroAssembler::andptr(Register dst, int32_t imm32) {
1219 LP64_ONLY(andq(dst, imm32)) NOT_LP64(andl(dst, imm32));
1220 }
1221
1222 void MacroAssembler::atomic_incl(Address counter_addr) {
1223 lock();
1224 incrementl(counter_addr);
1225 }
1226
1227 void MacroAssembler::atomic_incl(AddressLiteral counter_addr, Register scr) {
1228 if (reachable(counter_addr)) {
1229 atomic_incl(as_Address(counter_addr));
1230 } else {
1231 lea(scr, counter_addr);
1232 atomic_incl(Address(scr, 0));
1233 }
1234 }
1235
1236 #ifdef _LP64
1237 void MacroAssembler::atomic_incq(Address counter_addr) {
1238 lock();
1239 incrementq(counter_addr);
1240 }
1241
1242 void MacroAssembler::atomic_incq(AddressLiteral counter_addr, Register scr) {
1243 if (reachable(counter_addr)) {
1244 atomic_incq(as_Address(counter_addr));
1245 } else {
1246 lea(scr, counter_addr);
1247 atomic_incq(Address(scr, 0));
1248 }
1249 }
1250 #endif
1251
1252 // Writes to stack successive pages until offset reached to check for
1253 // stack overflow + shadow pages. This clobbers tmp.
1254 void MacroAssembler::bang_stack_size(Register size, Register tmp) {
1255 movptr(tmp, rsp);
1256 // Bang stack for total size given plus shadow page size.
1257 // Bang one page at a time because large size can bang beyond yellow and
1258 // red zones.
1259 Label loop;
1260 bind(loop);
1261 movl(Address(tmp, (-os::vm_page_size())), size );
1262 subptr(tmp, os::vm_page_size());
1263 subl(size, os::vm_page_size());
1264 jcc(Assembler::greater, loop);
1265
1266 // Bang down shadow pages too.
1267 // At this point, (tmp-0) is the last address touched, so don't
1268 // touch it again. (It was touched as (tmp-pagesize) but then tmp
1269 // was post-decremented.) Skip this address by starting at i=1, and
1270 // touch a few more pages below. N.B. It is important to touch all
1271 // the way down including all pages in the shadow zone.
1272 for (int i = 1; i < ((int)StackOverflow::stack_shadow_zone_size() / os::vm_page_size()); i++) {
1273 // this could be any sized move but this is can be a debugging crumb
1274 // so the bigger the better.
1275 movptr(Address(tmp, (-i*os::vm_page_size())), size );
1276 }
1277 }
1278
1279 void MacroAssembler::reserved_stack_check() {
1280 // testing if reserved zone needs to be enabled
1281 Label no_reserved_zone_enabling;
1282 Register thread = NOT_LP64(rsi) LP64_ONLY(r15_thread);
1283 NOT_LP64(get_thread(rsi);)
1284
1285 cmpptr(rsp, Address(thread, JavaThread::reserved_stack_activation_offset()));
1286 jcc(Assembler::below, no_reserved_zone_enabling);
1287
1288 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::enable_stack_reserved_zone), thread);
1289 jump(RuntimeAddress(StubRoutines::throw_delayed_StackOverflowError_entry()));
1290 should_not_reach_here();
1291
1292 bind(no_reserved_zone_enabling);
1293 }
1294
1295 void MacroAssembler::c2bool(Register x) {
1296 // implements x == 0 ? 0 : 1
1297 // note: must only look at least-significant byte of x
1298 // since C-style booleans are stored in one byte
1299 // only! (was bug)
1300 andl(x, 0xFF);
1301 setb(Assembler::notZero, x);
1302 }
1303
1304 // Wouldn't need if AddressLiteral version had new name
1305 void MacroAssembler::call(Label& L, relocInfo::relocType rtype) {
1306 Assembler::call(L, rtype);
1307 }
1308
1309 void MacroAssembler::call(Register entry) {
1310 Assembler::call(entry);
1311 }
1312
1313 void MacroAssembler::call(AddressLiteral entry) {
1314 if (reachable(entry)) {
1315 Assembler::call_literal(entry.target(), entry.rspec());
1316 } else {
1317 lea(rscratch1, entry);
1318 Assembler::call(rscratch1);
1319 }
1320 }
1321
1322 void MacroAssembler::ic_call(address entry, jint method_index) {
1323 RelocationHolder rh = virtual_call_Relocation::spec(pc(), method_index);
1324 movptr(rax, (intptr_t)Universe::non_oop_word());
1325 call(AddressLiteral(entry, rh));
1326 }
1327
1328 // Implementation of call_VM versions
1329
1330 void MacroAssembler::call_VM(Register oop_result,
1331 address entry_point,
1332 bool check_exceptions) {
1333 Label C, E;
1334 call(C, relocInfo::none);
1335 jmp(E);
1336
1337 bind(C);
1338 call_VM_helper(oop_result, entry_point, 0, check_exceptions);
1339 ret(0);
1340
1341 bind(E);
1342 }
1343
1344 void MacroAssembler::call_VM(Register oop_result,
1345 address entry_point,
1346 Register arg_1,
1347 bool check_exceptions) {
1348 Label C, E;
1349 call(C, relocInfo::none);
1350 jmp(E);
1351
1352 bind(C);
1353 pass_arg1(this, arg_1);
1354 call_VM_helper(oop_result, entry_point, 1, check_exceptions);
1355 ret(0);
1356
1357 bind(E);
1358 }
1359
1360 void MacroAssembler::call_VM(Register oop_result,
1361 address entry_point,
1362 Register arg_1,
1363 Register arg_2,
1364 bool check_exceptions) {
1365 Label C, E;
1366 call(C, relocInfo::none);
1367 jmp(E);
1368
1369 bind(C);
1370
1371 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
1372
1373 pass_arg2(this, arg_2);
1374 pass_arg1(this, arg_1);
1375 call_VM_helper(oop_result, entry_point, 2, check_exceptions);
1376 ret(0);
1377
1378 bind(E);
1379 }
1380
1381 void MacroAssembler::call_VM(Register oop_result,
1382 address entry_point,
1383 Register arg_1,
1384 Register arg_2,
1385 Register arg_3,
1386 bool check_exceptions) {
1387 Label C, E;
1388 call(C, relocInfo::none);
1389 jmp(E);
1390
1391 bind(C);
1392
1393 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
1394 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
1395 pass_arg3(this, arg_3);
1396
1397 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
1398 pass_arg2(this, arg_2);
1399
1400 pass_arg1(this, arg_1);
1401 call_VM_helper(oop_result, entry_point, 3, check_exceptions);
1402 ret(0);
1403
1404 bind(E);
1405 }
1406
1407 void MacroAssembler::call_VM(Register oop_result,
1408 Register last_java_sp,
1409 address entry_point,
1410 int number_of_arguments,
1411 bool check_exceptions) {
1412 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
1413 call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
1414 }
1415
1416 void MacroAssembler::call_VM(Register oop_result,
1417 Register last_java_sp,
1418 address entry_point,
1419 Register arg_1,
1420 bool check_exceptions) {
1421 pass_arg1(this, arg_1);
1422 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
1423 }
1424
1425 void MacroAssembler::call_VM(Register oop_result,
1426 Register last_java_sp,
1427 address entry_point,
1428 Register arg_1,
1429 Register arg_2,
1430 bool check_exceptions) {
1431
1432 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
1433 pass_arg2(this, arg_2);
1434 pass_arg1(this, arg_1);
1435 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
1436 }
1437
1438 void MacroAssembler::call_VM(Register oop_result,
1439 Register last_java_sp,
1440 address entry_point,
1441 Register arg_1,
1442 Register arg_2,
1443 Register arg_3,
1444 bool check_exceptions) {
1445 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
1446 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
1447 pass_arg3(this, arg_3);
1448 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
1449 pass_arg2(this, arg_2);
1450 pass_arg1(this, arg_1);
1451 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
1452 }
1453
1454 void MacroAssembler::super_call_VM(Register oop_result,
1455 Register last_java_sp,
1456 address entry_point,
1457 int number_of_arguments,
1458 bool check_exceptions) {
1459 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
1460 MacroAssembler::call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
1461 }
1462
1463 void MacroAssembler::super_call_VM(Register oop_result,
1464 Register last_java_sp,
1465 address entry_point,
1466 Register arg_1,
1467 bool check_exceptions) {
1468 pass_arg1(this, arg_1);
1469 super_call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
1470 }
1471
1472 void MacroAssembler::super_call_VM(Register oop_result,
1473 Register last_java_sp,
1474 address entry_point,
1475 Register arg_1,
1476 Register arg_2,
1477 bool check_exceptions) {
1478
1479 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
1480 pass_arg2(this, arg_2);
1481 pass_arg1(this, arg_1);
1482 super_call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
1483 }
1484
1485 void MacroAssembler::super_call_VM(Register oop_result,
1486 Register last_java_sp,
1487 address entry_point,
1488 Register arg_1,
1489 Register arg_2,
1490 Register arg_3,
1491 bool check_exceptions) {
1492 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
1493 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
1494 pass_arg3(this, arg_3);
1495 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
1496 pass_arg2(this, arg_2);
1497 pass_arg1(this, arg_1);
1498 super_call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
1499 }
1500
1501 void MacroAssembler::call_VM_base(Register oop_result,
1502 Register java_thread,
1503 Register last_java_sp,
1504 address entry_point,
1505 int number_of_arguments,
1506 bool check_exceptions) {
1507 // determine java_thread register
1508 if (!java_thread->is_valid()) {
1509 #ifdef _LP64
1510 java_thread = r15_thread;
1511 #else
1512 java_thread = rdi;
1513 get_thread(java_thread);
1514 #endif // LP64
1515 }
1516 // determine last_java_sp register
1517 if (!last_java_sp->is_valid()) {
1518 last_java_sp = rsp;
1519 }
1520 // debugging support
1521 assert(number_of_arguments >= 0 , "cannot have negative number of arguments");
1522 LP64_ONLY(assert(java_thread == r15_thread, "unexpected register"));
1523 #ifdef ASSERT
1524 // TraceBytecodes does not use r12 but saves it over the call, so don't verify
1525 // r12 is the heapbase.
1526 LP64_ONLY(if (UseCompressedOops && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?");)
1527 #endif // ASSERT
1528
1529 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result");
1530 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp");
1531
1532 // push java thread (becomes first argument of C function)
1533
1534 NOT_LP64(push(java_thread); number_of_arguments++);
1535 LP64_ONLY(mov(c_rarg0, r15_thread));
1536
1537 // set last Java frame before call
1538 assert(last_java_sp != rbp, "can't use ebp/rbp");
1539
1540 // Only interpreter should have to set fp
1541 set_last_Java_frame(java_thread, last_java_sp, rbp, NULL);
1542
1543 // do the call, remove parameters
1544 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments);
1545
1546 // restore the thread (cannot use the pushed argument since arguments
1547 // may be overwritten by C code generated by an optimizing compiler);
1548 // however can use the register value directly if it is callee saved.
1549 if (LP64_ONLY(true ||) java_thread == rdi || java_thread == rsi) {
1550 // rdi & rsi (also r15) are callee saved -> nothing to do
1551 #ifdef ASSERT
1552 guarantee(java_thread != rax, "change this code");
1553 push(rax);
1554 { Label L;
1555 get_thread(rax);
1556 cmpptr(java_thread, rax);
1557 jcc(Assembler::equal, L);
1558 STOP("MacroAssembler::call_VM_base: rdi not callee saved?");
1559 bind(L);
1560 }
1561 pop(rax);
1562 #endif
1563 } else {
1564 get_thread(java_thread);
1565 }
1566 // reset last Java frame
1567 // Only interpreter should have to clear fp
1568 reset_last_Java_frame(java_thread, true);
1569
1570 // C++ interp handles this in the interpreter
1571 check_and_handle_popframe(java_thread);
1572 check_and_handle_earlyret(java_thread);
1573
1574 if (check_exceptions) {
1575 // check for pending exceptions (java_thread is set upon return)
1576 cmpptr(Address(java_thread, Thread::pending_exception_offset()), (int32_t) NULL_WORD);
1577 #ifndef _LP64
1578 jump_cc(Assembler::notEqual,
1579 RuntimeAddress(StubRoutines::forward_exception_entry()));
1580 #else
1581 // This used to conditionally jump to forward_exception however it is
1582 // possible if we relocate that the branch will not reach. So we must jump
1583 // around so we can always reach
1584
1585 Label ok;
1586 jcc(Assembler::equal, ok);
1587 jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
1588 bind(ok);
1589 #endif // LP64
1590 }
1591
1592 // get oop result if there is one and reset the value in the thread
1593 if (oop_result->is_valid()) {
1594 get_vm_result(oop_result, java_thread);
1595 }
1596 }
1597
1598 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
1599
1600 // Calculate the value for last_Java_sp
1601 // somewhat subtle. call_VM does an intermediate call
1602 // which places a return address on the stack just under the
1603 // stack pointer as the user finsihed with it. This allows
1604 // use to retrieve last_Java_pc from last_Java_sp[-1].
1605 // On 32bit we then have to push additional args on the stack to accomplish
1606 // the actual requested call. On 64bit call_VM only can use register args
1607 // so the only extra space is the return address that call_VM created.
1608 // This hopefully explains the calculations here.
1609
1610 #ifdef _LP64
1611 // We've pushed one address, correct last_Java_sp
1612 lea(rax, Address(rsp, wordSize));
1613 #else
1614 lea(rax, Address(rsp, (1 + number_of_arguments) * wordSize));
1615 #endif // LP64
1616
1617 call_VM_base(oop_result, noreg, rax, entry_point, number_of_arguments, check_exceptions);
1618
1619 }
1620
1621 // Use this method when MacroAssembler version of call_VM_leaf_base() should be called from Interpreter.
1622 void MacroAssembler::call_VM_leaf0(address entry_point) {
1623 MacroAssembler::call_VM_leaf_base(entry_point, 0);
1624 }
1625
1626 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) {
1627 call_VM_leaf_base(entry_point, number_of_arguments);
1628 }
1629
1630 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) {
1631 pass_arg0(this, arg_0);
1632 call_VM_leaf(entry_point, 1);
1633 }
1634
1635 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
1636
1637 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
1638 pass_arg1(this, arg_1);
1639 pass_arg0(this, arg_0);
1640 call_VM_leaf(entry_point, 2);
1641 }
1642
1643 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
1644 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
1645 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
1646 pass_arg2(this, arg_2);
1647 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
1648 pass_arg1(this, arg_1);
1649 pass_arg0(this, arg_0);
1650 call_VM_leaf(entry_point, 3);
1651 }
1652
1653 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) {
1654 pass_arg0(this, arg_0);
1655 MacroAssembler::call_VM_leaf_base(entry_point, 1);
1656 }
1657
1658 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
1659
1660 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
1661 pass_arg1(this, arg_1);
1662 pass_arg0(this, arg_0);
1663 MacroAssembler::call_VM_leaf_base(entry_point, 2);
1664 }
1665
1666 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
1667 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
1668 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
1669 pass_arg2(this, arg_2);
1670 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
1671 pass_arg1(this, arg_1);
1672 pass_arg0(this, arg_0);
1673 MacroAssembler::call_VM_leaf_base(entry_point, 3);
1674 }
1675
1676 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
1677 LP64_ONLY(assert(arg_0 != c_rarg3, "smashed arg"));
1678 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
1679 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
1680 pass_arg3(this, arg_3);
1681 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
1682 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
1683 pass_arg2(this, arg_2);
1684 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
1685 pass_arg1(this, arg_1);
1686 pass_arg0(this, arg_0);
1687 MacroAssembler::call_VM_leaf_base(entry_point, 4);
1688 }
1689
1690 void MacroAssembler::get_vm_result(Register oop_result, Register java_thread) {
1691 movptr(oop_result, Address(java_thread, JavaThread::vm_result_offset()));
1692 movptr(Address(java_thread, JavaThread::vm_result_offset()), NULL_WORD);
1693 verify_oop_msg(oop_result, "broken oop in call_VM_base");
1694 }
1695
1696 void MacroAssembler::get_vm_result_2(Register metadata_result, Register java_thread) {
1697 movptr(metadata_result, Address(java_thread, JavaThread::vm_result_2_offset()));
1698 movptr(Address(java_thread, JavaThread::vm_result_2_offset()), NULL_WORD);
1699 }
1700
1701 void MacroAssembler::check_and_handle_earlyret(Register java_thread) {
1702 }
1703
1704 void MacroAssembler::check_and_handle_popframe(Register java_thread) {
1705 }
1706
1707 void MacroAssembler::cmp32(AddressLiteral src1, int32_t imm) {
1708 if (reachable(src1)) {
1709 cmpl(as_Address(src1), imm);
1710 } else {
1711 lea(rscratch1, src1);
1712 cmpl(Address(rscratch1, 0), imm);
1713 }
1714 }
1715
1716 void MacroAssembler::cmp32(Register src1, AddressLiteral src2) {
1717 assert(!src2.is_lval(), "use cmpptr");
1718 if (reachable(src2)) {
1719 cmpl(src1, as_Address(src2));
1720 } else {
1721 lea(rscratch1, src2);
1722 cmpl(src1, Address(rscratch1, 0));
1723 }
1724 }
1725
1726 void MacroAssembler::cmp32(Register src1, int32_t imm) {
1727 Assembler::cmpl(src1, imm);
1728 }
1729
1730 void MacroAssembler::cmp32(Register src1, Address src2) {
1731 Assembler::cmpl(src1, src2);
1732 }
1733
1734 void MacroAssembler::cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
1735 ucomisd(opr1, opr2);
1736
1737 Label L;
1738 if (unordered_is_less) {
1739 movl(dst, -1);
1740 jcc(Assembler::parity, L);
1741 jcc(Assembler::below , L);
1742 movl(dst, 0);
1743 jcc(Assembler::equal , L);
1744 increment(dst);
1745 } else { // unordered is greater
1746 movl(dst, 1);
1747 jcc(Assembler::parity, L);
1748 jcc(Assembler::above , L);
1749 movl(dst, 0);
1750 jcc(Assembler::equal , L);
1751 decrementl(dst);
1752 }
1753 bind(L);
1754 }
1755
1756 void MacroAssembler::cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
1757 ucomiss(opr1, opr2);
1758
1759 Label L;
1760 if (unordered_is_less) {
1761 movl(dst, -1);
1762 jcc(Assembler::parity, L);
1763 jcc(Assembler::below , L);
1764 movl(dst, 0);
1765 jcc(Assembler::equal , L);
1766 increment(dst);
1767 } else { // unordered is greater
1768 movl(dst, 1);
1769 jcc(Assembler::parity, L);
1770 jcc(Assembler::above , L);
1771 movl(dst, 0);
1772 jcc(Assembler::equal , L);
1773 decrementl(dst);
1774 }
1775 bind(L);
1776 }
1777
1778
1779 void MacroAssembler::cmp8(AddressLiteral src1, int imm) {
1780 if (reachable(src1)) {
1781 cmpb(as_Address(src1), imm);
1782 } else {
1783 lea(rscratch1, src1);
1784 cmpb(Address(rscratch1, 0), imm);
1785 }
1786 }
1787
1788 void MacroAssembler::cmpptr(Register src1, AddressLiteral src2) {
1789 #ifdef _LP64
1790 if (src2.is_lval()) {
1791 movptr(rscratch1, src2);
1792 Assembler::cmpq(src1, rscratch1);
1793 } else if (reachable(src2)) {
1794 cmpq(src1, as_Address(src2));
1795 } else {
1796 lea(rscratch1, src2);
1797 Assembler::cmpq(src1, Address(rscratch1, 0));
1798 }
1799 #else
1800 if (src2.is_lval()) {
1801 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
1802 } else {
1803 cmpl(src1, as_Address(src2));
1804 }
1805 #endif // _LP64
1806 }
1807
1808 void MacroAssembler::cmpptr(Address src1, AddressLiteral src2) {
1809 assert(src2.is_lval(), "not a mem-mem compare");
1810 #ifdef _LP64
1811 // moves src2's literal address
1812 movptr(rscratch1, src2);
1813 Assembler::cmpq(src1, rscratch1);
1814 #else
1815 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
1816 #endif // _LP64
1817 }
1818
1819 void MacroAssembler::cmpoop(Register src1, Register src2) {
1820 cmpptr(src1, src2);
1821 }
1822
1823 void MacroAssembler::cmpoop(Register src1, Address src2) {
1824 cmpptr(src1, src2);
1825 }
1826
1827 #ifdef _LP64
1828 void MacroAssembler::cmpoop(Register src1, jobject src2) {
1829 movoop(rscratch1, src2);
1830 cmpptr(src1, rscratch1);
1831 }
1832 #endif
1833
1834 void MacroAssembler::locked_cmpxchgptr(Register reg, AddressLiteral adr) {
1835 if (reachable(adr)) {
1836 lock();
1837 cmpxchgptr(reg, as_Address(adr));
1838 } else {
1839 lea(rscratch1, adr);
1840 lock();
1841 cmpxchgptr(reg, Address(rscratch1, 0));
1842 }
1843 }
1844
1845 void MacroAssembler::cmpxchgptr(Register reg, Address adr) {
1846 LP64_ONLY(cmpxchgq(reg, adr)) NOT_LP64(cmpxchgl(reg, adr));
1847 }
1848
1849 void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src) {
1850 if (reachable(src)) {
1851 Assembler::comisd(dst, as_Address(src));
1852 } else {
1853 lea(rscratch1, src);
1854 Assembler::comisd(dst, Address(rscratch1, 0));
1855 }
1856 }
1857
1858 void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src) {
1859 if (reachable(src)) {
1860 Assembler::comiss(dst, as_Address(src));
1861 } else {
1862 lea(rscratch1, src);
1863 Assembler::comiss(dst, Address(rscratch1, 0));
1864 }
1865 }
1866
1867
1868 void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr) {
1869 Condition negated_cond = negate_condition(cond);
1870 Label L;
1871 jcc(negated_cond, L);
1872 pushf(); // Preserve flags
1873 atomic_incl(counter_addr);
1874 popf();
1875 bind(L);
1876 }
1877
1878 int MacroAssembler::corrected_idivl(Register reg) {
1879 // Full implementation of Java idiv and irem; checks for
1880 // special case as described in JVM spec., p.243 & p.271.
1881 // The function returns the (pc) offset of the idivl
1882 // instruction - may be needed for implicit exceptions.
1883 //
1884 // normal case special case
1885 //
1886 // input : rax,: dividend min_int
1887 // reg: divisor (may not be rax,/rdx) -1
1888 //
1889 // output: rax,: quotient (= rax, idiv reg) min_int
1890 // rdx: remainder (= rax, irem reg) 0
1891 assert(reg != rax && reg != rdx, "reg cannot be rax, or rdx register");
1892 const int min_int = 0x80000000;
1893 Label normal_case, special_case;
1894
1895 // check for special case
1896 cmpl(rax, min_int);
1897 jcc(Assembler::notEqual, normal_case);
1898 xorl(rdx, rdx); // prepare rdx for possible special case (where remainder = 0)
1899 cmpl(reg, -1);
1900 jcc(Assembler::equal, special_case);
1901
1902 // handle normal case
1903 bind(normal_case);
1904 cdql();
1905 int idivl_offset = offset();
1906 idivl(reg);
1907
1908 // normal and special case exit
1909 bind(special_case);
1910
1911 return idivl_offset;
1912 }
1913
1914
1915
1916 void MacroAssembler::decrementl(Register reg, int value) {
1917 if (value == min_jint) {subl(reg, value) ; return; }
1918 if (value < 0) { incrementl(reg, -value); return; }
1919 if (value == 0) { ; return; }
1920 if (value == 1 && UseIncDec) { decl(reg) ; return; }
1921 /* else */ { subl(reg, value) ; return; }
1922 }
1923
1924 void MacroAssembler::decrementl(Address dst, int value) {
1925 if (value == min_jint) {subl(dst, value) ; return; }
1926 if (value < 0) { incrementl(dst, -value); return; }
1927 if (value == 0) { ; return; }
1928 if (value == 1 && UseIncDec) { decl(dst) ; return; }
1929 /* else */ { subl(dst, value) ; return; }
1930 }
1931
1932 void MacroAssembler::division_with_shift (Register reg, int shift_value) {
1933 assert (shift_value > 0, "illegal shift value");
1934 Label _is_positive;
1935 testl (reg, reg);
1936 jcc (Assembler::positive, _is_positive);
1937 int offset = (1 << shift_value) - 1 ;
1938
1939 if (offset == 1) {
1940 incrementl(reg);
1941 } else {
1942 addl(reg, offset);
1943 }
1944
1945 bind (_is_positive);
1946 sarl(reg, shift_value);
1947 }
1948
1949 void MacroAssembler::divsd(XMMRegister dst, AddressLiteral src) {
1950 if (reachable(src)) {
1951 Assembler::divsd(dst, as_Address(src));
1952 } else {
1953 lea(rscratch1, src);
1954 Assembler::divsd(dst, Address(rscratch1, 0));
1955 }
1956 }
1957
1958 void MacroAssembler::divss(XMMRegister dst, AddressLiteral src) {
1959 if (reachable(src)) {
1960 Assembler::divss(dst, as_Address(src));
1961 } else {
1962 lea(rscratch1, src);
1963 Assembler::divss(dst, Address(rscratch1, 0));
1964 }
1965 }
1966
1967 void MacroAssembler::enter() {
1968 push(rbp);
1969 mov(rbp, rsp);
1970 }
1971
1972 // A 5 byte nop that is safe for patching (see patch_verified_entry)
1973 void MacroAssembler::fat_nop() {
1974 if (UseAddressNop) {
1975 addr_nop_5();
1976 } else {
1977 emit_int8(0x26); // es:
1978 emit_int8(0x2e); // cs:
1979 emit_int8(0x64); // fs:
1980 emit_int8(0x65); // gs:
1981 emit_int8((unsigned char)0x90);
1982 }
1983 }
1984
1985 #ifndef _LP64
1986 void MacroAssembler::fcmp(Register tmp) {
1987 fcmp(tmp, 1, true, true);
1988 }
1989
1990 void MacroAssembler::fcmp(Register tmp, int index, bool pop_left, bool pop_right) {
1991 assert(!pop_right || pop_left, "usage error");
1992 if (VM_Version::supports_cmov()) {
1993 assert(tmp == noreg, "unneeded temp");
1994 if (pop_left) {
1995 fucomip(index);
1996 } else {
1997 fucomi(index);
1998 }
1999 if (pop_right) {
2000 fpop();
2001 }
2002 } else {
2003 assert(tmp != noreg, "need temp");
2004 if (pop_left) {
2005 if (pop_right) {
2006 fcompp();
2007 } else {
2008 fcomp(index);
2009 }
2010 } else {
2011 fcom(index);
2012 }
2013 // convert FPU condition into eflags condition via rax,
2014 save_rax(tmp);
2015 fwait(); fnstsw_ax();
2016 sahf();
2017 restore_rax(tmp);
2018 }
2019 // condition codes set as follows:
2020 //
2021 // CF (corresponds to C0) if x < y
2022 // PF (corresponds to C2) if unordered
2023 // ZF (corresponds to C3) if x = y
2024 }
2025
2026 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less) {
2027 fcmp2int(dst, unordered_is_less, 1, true, true);
2028 }
2029
2030 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right) {
2031 fcmp(VM_Version::supports_cmov() ? noreg : dst, index, pop_left, pop_right);
2032 Label L;
2033 if (unordered_is_less) {
2034 movl(dst, -1);
2035 jcc(Assembler::parity, L);
2036 jcc(Assembler::below , L);
2037 movl(dst, 0);
2038 jcc(Assembler::equal , L);
2039 increment(dst);
2040 } else { // unordered is greater
2041 movl(dst, 1);
2042 jcc(Assembler::parity, L);
2043 jcc(Assembler::above , L);
2044 movl(dst, 0);
2045 jcc(Assembler::equal , L);
2046 decrementl(dst);
2047 }
2048 bind(L);
2049 }
2050
2051 void MacroAssembler::fld_d(AddressLiteral src) {
2052 fld_d(as_Address(src));
2053 }
2054
2055 void MacroAssembler::fld_s(AddressLiteral src) {
2056 fld_s(as_Address(src));
2057 }
2058
2059 void MacroAssembler::fldcw(AddressLiteral src) {
2060 Assembler::fldcw(as_Address(src));
2061 }
2062
2063 void MacroAssembler::fpop() {
2064 ffree();
2065 fincstp();
2066 }
2067
2068 void MacroAssembler::fremr(Register tmp) {
2069 save_rax(tmp);
2070 { Label L;
2071 bind(L);
2072 fprem();
2073 fwait(); fnstsw_ax();
2074 sahf();
2075 jcc(Assembler::parity, L);
2076 }
2077 restore_rax(tmp);
2078 // Result is in ST0.
2079 // Note: fxch & fpop to get rid of ST1
2080 // (otherwise FPU stack could overflow eventually)
2081 fxch(1);
2082 fpop();
2083 }
2084
2085 void MacroAssembler::empty_FPU_stack() {
2086 if (VM_Version::supports_mmx()) {
2087 emms();
2088 } else {
2089 for (int i = 8; i-- > 0; ) ffree(i);
2090 }
2091 }
2092 #endif // !LP64
2093
2094 void MacroAssembler::mulpd(XMMRegister dst, AddressLiteral src) {
2095 if (reachable(src)) {
2096 Assembler::mulpd(dst, as_Address(src));
2097 } else {
2098 lea(rscratch1, src);
2099 Assembler::mulpd(dst, Address(rscratch1, 0));
2100 }
2101 }
2102
2103 void MacroAssembler::load_float(Address src) {
2104 #ifdef _LP64
2105 movflt(xmm0, src);
2106 #else
2107 if (UseSSE >= 1) {
2108 movflt(xmm0, src);
2109 } else {
2110 fld_s(src);
2111 }
2112 #endif // LP64
2113 }
2114
2115 void MacroAssembler::store_float(Address dst) {
2116 #ifdef _LP64
2117 movflt(dst, xmm0);
2118 #else
2119 if (UseSSE >= 1) {
2120 movflt(dst, xmm0);
2121 } else {
2122 fstp_s(dst);
2123 }
2124 #endif // LP64
2125 }
2126
2127 void MacroAssembler::load_double(Address src) {
2128 #ifdef _LP64
2129 movdbl(xmm0, src);
2130 #else
2131 if (UseSSE >= 2) {
2132 movdbl(xmm0, src);
2133 } else {
2134 fld_d(src);
2135 }
2136 #endif // LP64
2137 }
2138
2139 void MacroAssembler::store_double(Address dst) {
2140 #ifdef _LP64
2141 movdbl(dst, xmm0);
2142 #else
2143 if (UseSSE >= 2) {
2144 movdbl(dst, xmm0);
2145 } else {
2146 fstp_d(dst);
2147 }
2148 #endif // LP64
2149 }
2150
2151 // dst = c = a * b + c
2152 void MacroAssembler::fmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) {
2153 Assembler::vfmadd231sd(c, a, b);
2154 if (dst != c) {
2155 movdbl(dst, c);
2156 }
2157 }
2158
2159 // dst = c = a * b + c
2160 void MacroAssembler::fmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) {
2161 Assembler::vfmadd231ss(c, a, b);
2162 if (dst != c) {
2163 movflt(dst, c);
2164 }
2165 }
2166
2167 // dst = c = a * b + c
2168 void MacroAssembler::vfmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len) {
2169 Assembler::vfmadd231pd(c, a, b, vector_len);
2170 if (dst != c) {
2171 vmovdqu(dst, c);
2172 }
2173 }
2174
2175 // dst = c = a * b + c
2176 void MacroAssembler::vfmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len) {
2177 Assembler::vfmadd231ps(c, a, b, vector_len);
2178 if (dst != c) {
2179 vmovdqu(dst, c);
2180 }
2181 }
2182
2183 // dst = c = a * b + c
2184 void MacroAssembler::vfmad(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len) {
2185 Assembler::vfmadd231pd(c, a, b, vector_len);
2186 if (dst != c) {
2187 vmovdqu(dst, c);
2188 }
2189 }
2190
2191 // dst = c = a * b + c
2192 void MacroAssembler::vfmaf(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len) {
2193 Assembler::vfmadd231ps(c, a, b, vector_len);
2194 if (dst != c) {
2195 vmovdqu(dst, c);
2196 }
2197 }
2198
2199 void MacroAssembler::incrementl(AddressLiteral dst) {
2200 if (reachable(dst)) {
2201 incrementl(as_Address(dst));
2202 } else {
2203 lea(rscratch1, dst);
2204 incrementl(Address(rscratch1, 0));
2205 }
2206 }
2207
2208 void MacroAssembler::incrementl(ArrayAddress dst) {
2209 incrementl(as_Address(dst));
2210 }
2211
2212 void MacroAssembler::incrementl(Register reg, int value) {
2213 if (value == min_jint) {addl(reg, value) ; return; }
2214 if (value < 0) { decrementl(reg, -value); return; }
2215 if (value == 0) { ; return; }
2216 if (value == 1 && UseIncDec) { incl(reg) ; return; }
2217 /* else */ { addl(reg, value) ; return; }
2218 }
2219
2220 void MacroAssembler::incrementl(Address dst, int value) {
2221 if (value == min_jint) {addl(dst, value) ; return; }
2222 if (value < 0) { decrementl(dst, -value); return; }
2223 if (value == 0) { ; return; }
2224 if (value == 1 && UseIncDec) { incl(dst) ; return; }
2225 /* else */ { addl(dst, value) ; return; }
2226 }
2227
2228 void MacroAssembler::jump(AddressLiteral dst) {
2229 if (reachable(dst)) {
2230 jmp_literal(dst.target(), dst.rspec());
2231 } else {
2232 lea(rscratch1, dst);
2233 jmp(rscratch1);
2234 }
2235 }
2236
2237 void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst) {
2238 if (reachable(dst)) {
2239 InstructionMark im(this);
2240 relocate(dst.reloc());
2241 const int short_size = 2;
2242 const int long_size = 6;
2243 int offs = (intptr_t)dst.target() - ((intptr_t)pc());
2244 if (dst.reloc() == relocInfo::none && is8bit(offs - short_size)) {
2245 // 0111 tttn #8-bit disp
2246 emit_int8(0x70 | cc);
2247 emit_int8((offs - short_size) & 0xFF);
2248 } else {
2249 // 0000 1111 1000 tttn #32-bit disp
2250 emit_int8(0x0F);
2251 emit_int8((unsigned char)(0x80 | cc));
2252 emit_int32(offs - long_size);
2253 }
2254 } else {
2255 #ifdef ASSERT
2256 warning("reversing conditional branch");
2257 #endif /* ASSERT */
2258 Label skip;
2259 jccb(reverse[cc], skip);
2260 lea(rscratch1, dst);
2261 Assembler::jmp(rscratch1);
2262 bind(skip);
2263 }
2264 }
2265
2266 void MacroAssembler::fld_x(AddressLiteral src) {
2267 Assembler::fld_x(as_Address(src));
2268 }
2269
2270 void MacroAssembler::ldmxcsr(AddressLiteral src) {
2271 if (reachable(src)) {
2272 Assembler::ldmxcsr(as_Address(src));
2273 } else {
2274 lea(rscratch1, src);
2275 Assembler::ldmxcsr(Address(rscratch1, 0));
2276 }
2277 }
2278
2279 int MacroAssembler::load_signed_byte(Register dst, Address src) {
2280 int off;
2281 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
2282 off = offset();
2283 movsbl(dst, src); // movsxb
2284 } else {
2285 off = load_unsigned_byte(dst, src);
2286 shll(dst, 24);
2287 sarl(dst, 24);
2288 }
2289 return off;
2290 }
2291
2292 // Note: load_signed_short used to be called load_signed_word.
2293 // Although the 'w' in x86 opcodes refers to the term "word" in the assembler
2294 // manual, which means 16 bits, that usage is found nowhere in HotSpot code.
2295 // The term "word" in HotSpot means a 32- or 64-bit machine word.
2296 int MacroAssembler::load_signed_short(Register dst, Address src) {
2297 int off;
2298 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
2299 // This is dubious to me since it seems safe to do a signed 16 => 64 bit
2300 // version but this is what 64bit has always done. This seems to imply
2301 // that users are only using 32bits worth.
2302 off = offset();
2303 movswl(dst, src); // movsxw
2304 } else {
2305 off = load_unsigned_short(dst, src);
2306 shll(dst, 16);
2307 sarl(dst, 16);
2308 }
2309 return off;
2310 }
2311
2312 int MacroAssembler::load_unsigned_byte(Register dst, Address src) {
2313 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
2314 // and "3.9 Partial Register Penalties", p. 22).
2315 int off;
2316 if (LP64_ONLY(true || ) VM_Version::is_P6() || src.uses(dst)) {
2317 off = offset();
2318 movzbl(dst, src); // movzxb
2319 } else {
2320 xorl(dst, dst);
2321 off = offset();
2322 movb(dst, src);
2323 }
2324 return off;
2325 }
2326
2327 // Note: load_unsigned_short used to be called load_unsigned_word.
2328 int MacroAssembler::load_unsigned_short(Register dst, Address src) {
2329 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
2330 // and "3.9 Partial Register Penalties", p. 22).
2331 int off;
2332 if (LP64_ONLY(true ||) VM_Version::is_P6() || src.uses(dst)) {
2333 off = offset();
2334 movzwl(dst, src); // movzxw
2335 } else {
2336 xorl(dst, dst);
2337 off = offset();
2338 movw(dst, src);
2339 }
2340 return off;
2341 }
2342
2343 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2) {
2344 switch (size_in_bytes) {
2345 #ifndef _LP64
2346 case 8:
2347 assert(dst2 != noreg, "second dest register required");
2348 movl(dst, src);
2349 movl(dst2, src.plus_disp(BytesPerInt));
2350 break;
2351 #else
2352 case 8: movq(dst, src); break;
2353 #endif
2354 case 4: movl(dst, src); break;
2355 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break;
2356 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break;
2357 default: ShouldNotReachHere();
2358 }
2359 }
2360
2361 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) {
2362 switch (size_in_bytes) {
2363 #ifndef _LP64
2364 case 8:
2365 assert(src2 != noreg, "second source register required");
2366 movl(dst, src);
2367 movl(dst.plus_disp(BytesPerInt), src2);
2368 break;
2369 #else
2370 case 8: movq(dst, src); break;
2371 #endif
2372 case 4: movl(dst, src); break;
2373 case 2: movw(dst, src); break;
2374 case 1: movb(dst, src); break;
2375 default: ShouldNotReachHere();
2376 }
2377 }
2378
2379 void MacroAssembler::mov32(AddressLiteral dst, Register src) {
2380 if (reachable(dst)) {
2381 movl(as_Address(dst), src);
2382 } else {
2383 lea(rscratch1, dst);
2384 movl(Address(rscratch1, 0), src);
2385 }
2386 }
2387
2388 void MacroAssembler::mov32(Register dst, AddressLiteral src) {
2389 if (reachable(src)) {
2390 movl(dst, as_Address(src));
2391 } else {
2392 lea(rscratch1, src);
2393 movl(dst, Address(rscratch1, 0));
2394 }
2395 }
2396
2397 // C++ bool manipulation
2398
2399 void MacroAssembler::movbool(Register dst, Address src) {
2400 if(sizeof(bool) == 1)
2401 movb(dst, src);
2402 else if(sizeof(bool) == 2)
2403 movw(dst, src);
2404 else if(sizeof(bool) == 4)
2405 movl(dst, src);
2406 else
2407 // unsupported
2408 ShouldNotReachHere();
2409 }
2410
2411 void MacroAssembler::movbool(Address dst, bool boolconst) {
2412 if(sizeof(bool) == 1)
2413 movb(dst, (int) boolconst);
2414 else if(sizeof(bool) == 2)
2415 movw(dst, (int) boolconst);
2416 else if(sizeof(bool) == 4)
2417 movl(dst, (int) boolconst);
2418 else
2419 // unsupported
2420 ShouldNotReachHere();
2421 }
2422
2423 void MacroAssembler::movbool(Address dst, Register src) {
2424 if(sizeof(bool) == 1)
2425 movb(dst, src);
2426 else if(sizeof(bool) == 2)
2427 movw(dst, src);
2428 else if(sizeof(bool) == 4)
2429 movl(dst, src);
2430 else
2431 // unsupported
2432 ShouldNotReachHere();
2433 }
2434
2435 void MacroAssembler::movbyte(ArrayAddress dst, int src) {
2436 movb(as_Address(dst), src);
2437 }
2438
2439 void MacroAssembler::movdl(XMMRegister dst, AddressLiteral src) {
2440 if (reachable(src)) {
2441 movdl(dst, as_Address(src));
2442 } else {
2443 lea(rscratch1, src);
2444 movdl(dst, Address(rscratch1, 0));
2445 }
2446 }
2447
2448 void MacroAssembler::movq(XMMRegister dst, AddressLiteral src) {
2449 if (reachable(src)) {
2450 movq(dst, as_Address(src));
2451 } else {
2452 lea(rscratch1, src);
2453 movq(dst, Address(rscratch1, 0));
2454 }
2455 }
2456
2457 void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src) {
2458 if (reachable(src)) {
2459 if (UseXmmLoadAndClearUpper) {
2460 movsd (dst, as_Address(src));
2461 } else {
2462 movlpd(dst, as_Address(src));
2463 }
2464 } else {
2465 lea(rscratch1, src);
2466 if (UseXmmLoadAndClearUpper) {
2467 movsd (dst, Address(rscratch1, 0));
2468 } else {
2469 movlpd(dst, Address(rscratch1, 0));
2470 }
2471 }
2472 }
2473
2474 void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src) {
2475 if (reachable(src)) {
2476 movss(dst, as_Address(src));
2477 } else {
2478 lea(rscratch1, src);
2479 movss(dst, Address(rscratch1, 0));
2480 }
2481 }
2482
2483 void MacroAssembler::movptr(Register dst, Register src) {
2484 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
2485 }
2486
2487 void MacroAssembler::movptr(Register dst, Address src) {
2488 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
2489 }
2490
2491 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
2492 void MacroAssembler::movptr(Register dst, intptr_t src) {
2493 LP64_ONLY(mov64(dst, src)) NOT_LP64(movl(dst, src));
2494 }
2495
2496 void MacroAssembler::movptr(Address dst, Register src) {
2497 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
2498 }
2499
2500 void MacroAssembler::movdqu(Address dst, XMMRegister src) {
2501 assert(((src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2502 Assembler::movdqu(dst, src);
2503 }
2504
2505 void MacroAssembler::movdqu(XMMRegister dst, Address src) {
2506 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2507 Assembler::movdqu(dst, src);
2508 }
2509
2510 void MacroAssembler::movdqu(XMMRegister dst, XMMRegister src) {
2511 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2512 Assembler::movdqu(dst, src);
2513 }
2514
2515 void MacroAssembler::movdqu(XMMRegister dst, AddressLiteral src, Register scratchReg) {
2516 if (reachable(src)) {
2517 movdqu(dst, as_Address(src));
2518 } else {
2519 lea(scratchReg, src);
2520 movdqu(dst, Address(scratchReg, 0));
2521 }
2522 }
2523
2524 void MacroAssembler::vmovdqu(Address dst, XMMRegister src) {
2525 assert(((src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2526 Assembler::vmovdqu(dst, src);
2527 }
2528
2529 void MacroAssembler::vmovdqu(XMMRegister dst, Address src) {
2530 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2531 Assembler::vmovdqu(dst, src);
2532 }
2533
2534 void MacroAssembler::vmovdqu(XMMRegister dst, XMMRegister src) {
2535 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2536 Assembler::vmovdqu(dst, src);
2537 }
2538
2539 void MacroAssembler::vmovdqu(XMMRegister dst, AddressLiteral src, Register scratch_reg) {
2540 if (reachable(src)) {
2541 vmovdqu(dst, as_Address(src));
2542 }
2543 else {
2544 lea(scratch_reg, src);
2545 vmovdqu(dst, Address(scratch_reg, 0));
2546 }
2547 }
2548
2549 void MacroAssembler::kmov(KRegister dst, Address src) {
2550 if (VM_Version::supports_avx512bw()) {
2551 kmovql(dst, src);
2552 } else {
2553 assert(VM_Version::supports_evex(), "");
2554 kmovwl(dst, src);
2555 }
2556 }
2557
2558 void MacroAssembler::kmov(Address dst, KRegister src) {
2559 if (VM_Version::supports_avx512bw()) {
2560 kmovql(dst, src);
2561 } else {
2562 assert(VM_Version::supports_evex(), "");
2563 kmovwl(dst, src);
2564 }
2565 }
2566
2567 void MacroAssembler::kmov(KRegister dst, KRegister src) {
2568 if (VM_Version::supports_avx512bw()) {
2569 kmovql(dst, src);
2570 } else {
2571 assert(VM_Version::supports_evex(), "");
2572 kmovwl(dst, src);
2573 }
2574 }
2575
2576 void MacroAssembler::kmov(Register dst, KRegister src) {
2577 if (VM_Version::supports_avx512bw()) {
2578 kmovql(dst, src);
2579 } else {
2580 assert(VM_Version::supports_evex(), "");
2581 kmovwl(dst, src);
2582 }
2583 }
2584
2585 void MacroAssembler::kmov(KRegister dst, Register src) {
2586 if (VM_Version::supports_avx512bw()) {
2587 kmovql(dst, src);
2588 } else {
2589 assert(VM_Version::supports_evex(), "");
2590 kmovwl(dst, src);
2591 }
2592 }
2593
2594 void MacroAssembler::kmovql(KRegister dst, AddressLiteral src, Register scratch_reg) {
2595 if (reachable(src)) {
2596 kmovql(dst, as_Address(src));
2597 } else {
2598 lea(scratch_reg, src);
2599 kmovql(dst, Address(scratch_reg, 0));
2600 }
2601 }
2602
2603 void MacroAssembler::kmovwl(KRegister dst, AddressLiteral src, Register scratch_reg) {
2604 if (reachable(src)) {
2605 kmovwl(dst, as_Address(src));
2606 } else {
2607 lea(scratch_reg, src);
2608 kmovwl(dst, Address(scratch_reg, 0));
2609 }
2610 }
2611
2612 void MacroAssembler::evmovdqub(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge,
2613 int vector_len, Register scratch_reg) {
2614 if (reachable(src)) {
2615 if (mask == k0) {
2616 Assembler::evmovdqub(dst, as_Address(src), merge, vector_len);
2617 } else {
2618 Assembler::evmovdqub(dst, mask, as_Address(src), merge, vector_len);
2619 }
2620 } else {
2621 lea(scratch_reg, src);
2622 if (mask == k0) {
2623 Assembler::evmovdqub(dst, Address(scratch_reg, 0), merge, vector_len);
2624 } else {
2625 Assembler::evmovdqub(dst, mask, Address(scratch_reg, 0), merge, vector_len);
2626 }
2627 }
2628 }
2629
2630 void MacroAssembler::evmovdquw(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge,
2631 int vector_len, Register scratch_reg) {
2632 if (reachable(src)) {
2633 Assembler::evmovdquw(dst, mask, as_Address(src), merge, vector_len);
2634 } else {
2635 lea(scratch_reg, src);
2636 Assembler::evmovdquw(dst, mask, Address(scratch_reg, 0), merge, vector_len);
2637 }
2638 }
2639
2640 void MacroAssembler::evmovdqul(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge,
2641 int vector_len, Register scratch_reg) {
2642 if (reachable(src)) {
2643 Assembler::evmovdqul(dst, mask, as_Address(src), merge, vector_len);
2644 } else {
2645 lea(scratch_reg, src);
2646 Assembler::evmovdqul(dst, mask, Address(scratch_reg, 0), merge, vector_len);
2647 }
2648 }
2649
2650 void MacroAssembler::evmovdquq(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge,
2651 int vector_len, Register scratch_reg) {
2652 if (reachable(src)) {
2653 Assembler::evmovdquq(dst, mask, as_Address(src), merge, vector_len);
2654 } else {
2655 lea(scratch_reg, src);
2656 Assembler::evmovdquq(dst, mask, Address(scratch_reg, 0), merge, vector_len);
2657 }
2658 }
2659
2660 void MacroAssembler::evmovdquq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2661 if (reachable(src)) {
2662 Assembler::evmovdquq(dst, as_Address(src), vector_len);
2663 } else {
2664 lea(rscratch, src);
2665 Assembler::evmovdquq(dst, Address(rscratch, 0), vector_len);
2666 }
2667 }
2668
2669 void MacroAssembler::movdqa(XMMRegister dst, AddressLiteral src) {
2670 if (reachable(src)) {
2671 Assembler::movdqa(dst, as_Address(src));
2672 } else {
2673 lea(rscratch1, src);
2674 Assembler::movdqa(dst, Address(rscratch1, 0));
2675 }
2676 }
2677
2678 void MacroAssembler::movsd(XMMRegister dst, AddressLiteral src) {
2679 if (reachable(src)) {
2680 Assembler::movsd(dst, as_Address(src));
2681 } else {
2682 lea(rscratch1, src);
2683 Assembler::movsd(dst, Address(rscratch1, 0));
2684 }
2685 }
2686
2687 void MacroAssembler::movss(XMMRegister dst, AddressLiteral src) {
2688 if (reachable(src)) {
2689 Assembler::movss(dst, as_Address(src));
2690 } else {
2691 lea(rscratch1, src);
2692 Assembler::movss(dst, Address(rscratch1, 0));
2693 }
2694 }
2695
2696 void MacroAssembler::mulsd(XMMRegister dst, AddressLiteral src) {
2697 if (reachable(src)) {
2698 Assembler::mulsd(dst, as_Address(src));
2699 } else {
2700 lea(rscratch1, src);
2701 Assembler::mulsd(dst, Address(rscratch1, 0));
2702 }
2703 }
2704
2705 void MacroAssembler::mulss(XMMRegister dst, AddressLiteral src) {
2706 if (reachable(src)) {
2707 Assembler::mulss(dst, as_Address(src));
2708 } else {
2709 lea(rscratch1, src);
2710 Assembler::mulss(dst, Address(rscratch1, 0));
2711 }
2712 }
2713
2714 void MacroAssembler::null_check(Register reg, int offset) {
2715 if (needs_explicit_null_check(offset)) {
2716 // provoke OS NULL exception if reg = NULL by
2717 // accessing M[reg] w/o changing any (non-CC) registers
2718 // NOTE: cmpl is plenty here to provoke a segv
2719 cmpptr(rax, Address(reg, 0));
2720 // Note: should probably use testl(rax, Address(reg, 0));
2721 // may be shorter code (however, this version of
2722 // testl needs to be implemented first)
2723 } else {
2724 // nothing to do, (later) access of M[reg + offset]
2725 // will provoke OS NULL exception if reg = NULL
2726 }
2727 }
2728
2729 void MacroAssembler::os_breakpoint() {
2730 // instead of directly emitting a breakpoint, call os:breakpoint for better debugability
2731 // (e.g., MSVC can't call ps() otherwise)
2732 call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
2733 }
2734
2735 void MacroAssembler::unimplemented(const char* what) {
2736 const char* buf = NULL;
2737 {
2738 ResourceMark rm;
2739 stringStream ss;
2740 ss.print("unimplemented: %s", what);
2741 buf = code_string(ss.as_string());
2742 }
2743 stop(buf);
2744 }
2745
2746 #ifdef _LP64
2747 #define XSTATE_BV 0x200
2748 #endif
2749
2750 void MacroAssembler::pop_CPU_state() {
2751 pop_FPU_state();
2752 pop_IU_state();
2753 }
2754
2755 void MacroAssembler::pop_FPU_state() {
2756 #ifndef _LP64
2757 frstor(Address(rsp, 0));
2758 #else
2759 fxrstor(Address(rsp, 0));
2760 #endif
2761 addptr(rsp, FPUStateSizeInWords * wordSize);
2762 }
2763
2764 void MacroAssembler::pop_IU_state() {
2765 popa();
2766 LP64_ONLY(addq(rsp, 8));
2767 popf();
2768 }
2769
2770 // Save Integer and Float state
2771 // Warning: Stack must be 16 byte aligned (64bit)
2772 void MacroAssembler::push_CPU_state() {
2773 push_IU_state();
2774 push_FPU_state();
2775 }
2776
2777 void MacroAssembler::push_FPU_state() {
2778 subptr(rsp, FPUStateSizeInWords * wordSize);
2779 #ifndef _LP64
2780 fnsave(Address(rsp, 0));
2781 fwait();
2782 #else
2783 fxsave(Address(rsp, 0));
2784 #endif // LP64
2785 }
2786
2787 void MacroAssembler::push_IU_state() {
2788 // Push flags first because pusha kills them
2789 pushf();
2790 // Make sure rsp stays 16-byte aligned
2791 LP64_ONLY(subq(rsp, 8));
2792 pusha();
2793 }
2794
2795 void MacroAssembler::reset_last_Java_frame(Register java_thread, bool clear_fp) { // determine java_thread register
2796 if (!java_thread->is_valid()) {
2797 java_thread = rdi;
2798 get_thread(java_thread);
2799 }
2800 // we must set sp to zero to clear frame
2801 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
2802 // must clear fp, so that compiled frames are not confused; it is
2803 // possible that we need it only for debugging
2804 if (clear_fp) {
2805 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
2806 }
2807 // Always clear the pc because it could have been set by make_walkable()
2808 movptr(Address(java_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
2809 vzeroupper();
2810 }
2811
2812 void MacroAssembler::restore_rax(Register tmp) {
2813 if (tmp == noreg) pop(rax);
2814 else if (tmp != rax) mov(rax, tmp);
2815 }
2816
2817 void MacroAssembler::round_to(Register reg, int modulus) {
2818 addptr(reg, modulus - 1);
2819 andptr(reg, -modulus);
2820 }
2821
2822 void MacroAssembler::save_rax(Register tmp) {
2823 if (tmp == noreg) push(rax);
2824 else if (tmp != rax) mov(tmp, rax);
2825 }
2826
2827 void MacroAssembler::safepoint_poll(Label& slow_path, Register thread_reg, bool at_return, bool in_nmethod) {
2828 if (at_return) {
2829 // Note that when in_nmethod is set, the stack pointer is incremented before the poll. Therefore,
2830 // we may safely use rsp instead to perform the stack watermark check.
2831 cmpptr(in_nmethod ? rsp : rbp, Address(thread_reg, JavaThread::polling_word_offset()));
2832 jcc(Assembler::above, slow_path);
2833 return;
2834 }
2835 testb(Address(thread_reg, JavaThread::polling_word_offset()), SafepointMechanism::poll_bit());
2836 jcc(Assembler::notZero, slow_path); // handshake bit set implies poll
2837 }
2838
2839 // Calls to C land
2840 //
2841 // When entering C land, the rbp, & rsp of the last Java frame have to be recorded
2842 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp
2843 // has to be reset to 0. This is required to allow proper stack traversal.
2844 void MacroAssembler::set_last_Java_frame(Register java_thread,
2845 Register last_java_sp,
2846 Register last_java_fp,
2847 address last_java_pc) {
2848 vzeroupper();
2849 // determine java_thread register
2850 if (!java_thread->is_valid()) {
2851 java_thread = rdi;
2852 get_thread(java_thread);
2853 }
2854 // determine last_java_sp register
2855 if (!last_java_sp->is_valid()) {
2856 last_java_sp = rsp;
2857 }
2858
2859 // last_java_fp is optional
2860
2861 if (last_java_fp->is_valid()) {
2862 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), last_java_fp);
2863 }
2864
2865 // last_java_pc is optional
2866
2867 if (last_java_pc != NULL) {
2868 lea(Address(java_thread,
2869 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()),
2870 InternalAddress(last_java_pc));
2871
2872 }
2873 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
2874 }
2875
2876 void MacroAssembler::shlptr(Register dst, int imm8) {
2877 LP64_ONLY(shlq(dst, imm8)) NOT_LP64(shll(dst, imm8));
2878 }
2879
2880 void MacroAssembler::shrptr(Register dst, int imm8) {
2881 LP64_ONLY(shrq(dst, imm8)) NOT_LP64(shrl(dst, imm8));
2882 }
2883
2884 void MacroAssembler::sign_extend_byte(Register reg) {
2885 if (LP64_ONLY(true ||) (VM_Version::is_P6() && reg->has_byte_register())) {
2886 movsbl(reg, reg); // movsxb
2887 } else {
2888 shll(reg, 24);
2889 sarl(reg, 24);
2890 }
2891 }
2892
2893 void MacroAssembler::sign_extend_short(Register reg) {
2894 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
2895 movswl(reg, reg); // movsxw
2896 } else {
2897 shll(reg, 16);
2898 sarl(reg, 16);
2899 }
2900 }
2901
2902 void MacroAssembler::testl(Register dst, AddressLiteral src) {
2903 assert(reachable(src), "Address should be reachable");
2904 testl(dst, as_Address(src));
2905 }
2906
2907 void MacroAssembler::pcmpeqb(XMMRegister dst, XMMRegister src) {
2908 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2909 Assembler::pcmpeqb(dst, src);
2910 }
2911
2912 void MacroAssembler::pcmpeqw(XMMRegister dst, XMMRegister src) {
2913 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2914 Assembler::pcmpeqw(dst, src);
2915 }
2916
2917 void MacroAssembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
2918 assert((dst->encoding() < 16),"XMM register should be 0-15");
2919 Assembler::pcmpestri(dst, src, imm8);
2920 }
2921
2922 void MacroAssembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
2923 assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
2924 Assembler::pcmpestri(dst, src, imm8);
2925 }
2926
2927 void MacroAssembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
2928 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2929 Assembler::pmovzxbw(dst, src);
2930 }
2931
2932 void MacroAssembler::pmovzxbw(XMMRegister dst, Address src) {
2933 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2934 Assembler::pmovzxbw(dst, src);
2935 }
2936
2937 void MacroAssembler::pmovmskb(Register dst, XMMRegister src) {
2938 assert((src->encoding() < 16),"XMM register should be 0-15");
2939 Assembler::pmovmskb(dst, src);
2940 }
2941
2942 void MacroAssembler::ptest(XMMRegister dst, XMMRegister src) {
2943 assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
2944 Assembler::ptest(dst, src);
2945 }
2946
2947 void MacroAssembler::sqrtsd(XMMRegister dst, AddressLiteral src) {
2948 if (reachable(src)) {
2949 Assembler::sqrtsd(dst, as_Address(src));
2950 } else {
2951 lea(rscratch1, src);
2952 Assembler::sqrtsd(dst, Address(rscratch1, 0));
2953 }
2954 }
2955
2956 void MacroAssembler::sqrtss(XMMRegister dst, AddressLiteral src) {
2957 if (reachable(src)) {
2958 Assembler::sqrtss(dst, as_Address(src));
2959 } else {
2960 lea(rscratch1, src);
2961 Assembler::sqrtss(dst, Address(rscratch1, 0));
2962 }
2963 }
2964
2965 void MacroAssembler::subsd(XMMRegister dst, AddressLiteral src) {
2966 if (reachable(src)) {
2967 Assembler::subsd(dst, as_Address(src));
2968 } else {
2969 lea(rscratch1, src);
2970 Assembler::subsd(dst, Address(rscratch1, 0));
2971 }
2972 }
2973
2974 void MacroAssembler::roundsd(XMMRegister dst, AddressLiteral src, int32_t rmode, Register scratch_reg) {
2975 if (reachable(src)) {
2976 Assembler::roundsd(dst, as_Address(src), rmode);
2977 } else {
2978 lea(scratch_reg, src);
2979 Assembler::roundsd(dst, Address(scratch_reg, 0), rmode);
2980 }
2981 }
2982
2983 void MacroAssembler::subss(XMMRegister dst, AddressLiteral src) {
2984 if (reachable(src)) {
2985 Assembler::subss(dst, as_Address(src));
2986 } else {
2987 lea(rscratch1, src);
2988 Assembler::subss(dst, Address(rscratch1, 0));
2989 }
2990 }
2991
2992 void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src) {
2993 if (reachable(src)) {
2994 Assembler::ucomisd(dst, as_Address(src));
2995 } else {
2996 lea(rscratch1, src);
2997 Assembler::ucomisd(dst, Address(rscratch1, 0));
2998 }
2999 }
3000
3001 void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src) {
3002 if (reachable(src)) {
3003 Assembler::ucomiss(dst, as_Address(src));
3004 } else {
3005 lea(rscratch1, src);
3006 Assembler::ucomiss(dst, Address(rscratch1, 0));
3007 }
3008 }
3009
3010 void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src, Register scratch_reg) {
3011 // Used in sign-bit flipping with aligned address.
3012 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
3013 if (reachable(src)) {
3014 Assembler::xorpd(dst, as_Address(src));
3015 } else {
3016 lea(scratch_reg, src);
3017 Assembler::xorpd(dst, Address(scratch_reg, 0));
3018 }
3019 }
3020
3021 void MacroAssembler::xorpd(XMMRegister dst, XMMRegister src) {
3022 if (UseAVX > 2 && !VM_Version::supports_avx512dq() && (dst->encoding() == src->encoding())) {
3023 Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit);
3024 }
3025 else {
3026 Assembler::xorpd(dst, src);
3027 }
3028 }
3029
3030 void MacroAssembler::xorps(XMMRegister dst, XMMRegister src) {
3031 if (UseAVX > 2 && !VM_Version::supports_avx512dq() && (dst->encoding() == src->encoding())) {
3032 Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit);
3033 } else {
3034 Assembler::xorps(dst, src);
3035 }
3036 }
3037
3038 void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src, Register scratch_reg) {
3039 // Used in sign-bit flipping with aligned address.
3040 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
3041 if (reachable(src)) {
3042 Assembler::xorps(dst, as_Address(src));
3043 } else {
3044 lea(scratch_reg, src);
3045 Assembler::xorps(dst, Address(scratch_reg, 0));
3046 }
3047 }
3048
3049 void MacroAssembler::pshufb(XMMRegister dst, AddressLiteral src) {
3050 // Used in sign-bit flipping with aligned address.
3051 bool aligned_adr = (((intptr_t)src.target() & 15) == 0);
3052 assert((UseAVX > 0) || aligned_adr, "SSE mode requires address alignment 16 bytes");
3053 if (reachable(src)) {
3054 Assembler::pshufb(dst, as_Address(src));
3055 } else {
3056 lea(rscratch1, src);
3057 Assembler::pshufb(dst, Address(rscratch1, 0));
3058 }
3059 }
3060
3061 // AVX 3-operands instructions
3062
3063 void MacroAssembler::vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3064 if (reachable(src)) {
3065 vaddsd(dst, nds, as_Address(src));
3066 } else {
3067 lea(rscratch1, src);
3068 vaddsd(dst, nds, Address(rscratch1, 0));
3069 }
3070 }
3071
3072 void MacroAssembler::vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3073 if (reachable(src)) {
3074 vaddss(dst, nds, as_Address(src));
3075 } else {
3076 lea(rscratch1, src);
3077 vaddss(dst, nds, Address(rscratch1, 0));
3078 }
3079 }
3080
3081 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3082 assert(UseAVX > 0, "requires some form of AVX");
3083 if (reachable(src)) {
3084 Assembler::vpaddb(dst, nds, as_Address(src), vector_len);
3085 } else {
3086 lea(rscratch, src);
3087 Assembler::vpaddb(dst, nds, Address(rscratch, 0), vector_len);
3088 }
3089 }
3090
3091 void MacroAssembler::vpaddd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3092 assert(UseAVX > 0, "requires some form of AVX");
3093 if (reachable(src)) {
3094 Assembler::vpaddd(dst, nds, as_Address(src), vector_len);
3095 } else {
3096 lea(rscratch, src);
3097 Assembler::vpaddd(dst, nds, Address(rscratch, 0), vector_len);
3098 }
3099 }
3100
3101 void MacroAssembler::vabsss(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len) {
3102 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
3103 vandps(dst, nds, negate_field, vector_len);
3104 }
3105
3106 void MacroAssembler::vabssd(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len) {
3107 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
3108 vandpd(dst, nds, negate_field, vector_len);
3109 }
3110
3111 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3112 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3113 Assembler::vpaddb(dst, nds, src, vector_len);
3114 }
3115
3116 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3117 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3118 Assembler::vpaddb(dst, nds, src, vector_len);
3119 }
3120
3121 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3122 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3123 Assembler::vpaddw(dst, nds, src, vector_len);
3124 }
3125
3126 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3127 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3128 Assembler::vpaddw(dst, nds, src, vector_len);
3129 }
3130
3131 void MacroAssembler::vpand(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg) {
3132 if (reachable(src)) {
3133 Assembler::vpand(dst, nds, as_Address(src), vector_len);
3134 } else {
3135 lea(scratch_reg, src);
3136 Assembler::vpand(dst, nds, Address(scratch_reg, 0), vector_len);
3137 }
3138 }
3139
3140 void MacroAssembler::vpbroadcastw(XMMRegister dst, XMMRegister src, int vector_len) {
3141 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3142 Assembler::vpbroadcastw(dst, src, vector_len);
3143 }
3144
3145 void MacroAssembler::vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3146 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3147 Assembler::vpcmpeqb(dst, nds, src, vector_len);
3148 }
3149
3150 void MacroAssembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3151 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3152 Assembler::vpcmpeqw(dst, nds, src, vector_len);
3153 }
3154
3155 void MacroAssembler::evpcmpeqd(KRegister kdst, KRegister mask, XMMRegister nds,
3156 AddressLiteral src, int vector_len, Register scratch_reg) {
3157 if (reachable(src)) {
3158 Assembler::evpcmpeqd(kdst, mask, nds, as_Address(src), vector_len);
3159 } else {
3160 lea(scratch_reg, src);
3161 Assembler::evpcmpeqd(kdst, mask, nds, Address(scratch_reg, 0), vector_len);
3162 }
3163 }
3164
3165 void MacroAssembler::evpcmpd(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3166 int comparison, bool is_signed, int vector_len, Register scratch_reg) {
3167 if (reachable(src)) {
3168 Assembler::evpcmpd(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3169 } else {
3170 lea(scratch_reg, src);
3171 Assembler::evpcmpd(kdst, mask, nds, Address(scratch_reg, 0), comparison, is_signed, vector_len);
3172 }
3173 }
3174
3175 void MacroAssembler::evpcmpq(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3176 int comparison, bool is_signed, int vector_len, Register scratch_reg) {
3177 if (reachable(src)) {
3178 Assembler::evpcmpq(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3179 } else {
3180 lea(scratch_reg, src);
3181 Assembler::evpcmpq(kdst, mask, nds, Address(scratch_reg, 0), comparison, is_signed, vector_len);
3182 }
3183 }
3184
3185 void MacroAssembler::evpcmpb(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3186 int comparison, bool is_signed, int vector_len, Register scratch_reg) {
3187 if (reachable(src)) {
3188 Assembler::evpcmpb(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3189 } else {
3190 lea(scratch_reg, src);
3191 Assembler::evpcmpb(kdst, mask, nds, Address(scratch_reg, 0), comparison, is_signed, vector_len);
3192 }
3193 }
3194
3195 void MacroAssembler::evpcmpw(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3196 int comparison, bool is_signed, int vector_len, Register scratch_reg) {
3197 if (reachable(src)) {
3198 Assembler::evpcmpw(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3199 } else {
3200 lea(scratch_reg, src);
3201 Assembler::evpcmpw(kdst, mask, nds, Address(scratch_reg, 0), comparison, is_signed, vector_len);
3202 }
3203 }
3204
3205 void MacroAssembler::vpcmpCC(XMMRegister dst, XMMRegister nds, XMMRegister src, int cond_encoding, Width width, int vector_len) {
3206 if (width == Assembler::Q) {
3207 Assembler::vpcmpCCq(dst, nds, src, cond_encoding, vector_len);
3208 } else {
3209 Assembler::vpcmpCCbwd(dst, nds, src, cond_encoding, vector_len);
3210 }
3211 }
3212
3213 void MacroAssembler::vpcmpCCW(XMMRegister dst, XMMRegister nds, XMMRegister src, ComparisonPredicate cond, Width width, int vector_len, Register scratch_reg) {
3214 int eq_cond_enc = 0x29;
3215 int gt_cond_enc = 0x37;
3216 if (width != Assembler::Q) {
3217 eq_cond_enc = 0x74 + width;
3218 gt_cond_enc = 0x64 + width;
3219 }
3220 switch (cond) {
3221 case eq:
3222 vpcmpCC(dst, nds, src, eq_cond_enc, width, vector_len);
3223 break;
3224 case neq:
3225 vpcmpCC(dst, nds, src, eq_cond_enc, width, vector_len);
3226 vpxor(dst, dst, ExternalAddress(StubRoutines::x86::vector_all_bits_set()), vector_len, scratch_reg);
3227 break;
3228 case le:
3229 vpcmpCC(dst, nds, src, gt_cond_enc, width, vector_len);
3230 vpxor(dst, dst, ExternalAddress(StubRoutines::x86::vector_all_bits_set()), vector_len, scratch_reg);
3231 break;
3232 case nlt:
3233 vpcmpCC(dst, src, nds, gt_cond_enc, width, vector_len);
3234 vpxor(dst, dst, ExternalAddress(StubRoutines::x86::vector_all_bits_set()), vector_len, scratch_reg);
3235 break;
3236 case lt:
3237 vpcmpCC(dst, src, nds, gt_cond_enc, width, vector_len);
3238 break;
3239 case nle:
3240 vpcmpCC(dst, nds, src, gt_cond_enc, width, vector_len);
3241 break;
3242 default:
3243 assert(false, "Should not reach here");
3244 }
3245 }
3246
3247 void MacroAssembler::vpmovzxbw(XMMRegister dst, Address src, int vector_len) {
3248 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3249 Assembler::vpmovzxbw(dst, src, vector_len);
3250 }
3251
3252 void MacroAssembler::vpmovmskb(Register dst, XMMRegister src, int vector_len) {
3253 assert((src->encoding() < 16),"XMM register should be 0-15");
3254 Assembler::vpmovmskb(dst, src, vector_len);
3255 }
3256
3257 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3258 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3259 Assembler::vpmullw(dst, nds, src, vector_len);
3260 }
3261
3262 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3263 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3264 Assembler::vpmullw(dst, nds, src, vector_len);
3265 }
3266
3267 void MacroAssembler::vpmulld(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg) {
3268 assert((UseAVX > 0), "AVX support is needed");
3269 if (reachable(src)) {
3270 Assembler::vpmulld(dst, nds, as_Address(src), vector_len);
3271 } else {
3272 lea(scratch_reg, src);
3273 Assembler::vpmulld(dst, nds, Address(scratch_reg, 0), vector_len);
3274 }
3275 }
3276
3277 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3278 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3279 Assembler::vpsubb(dst, nds, src, vector_len);
3280 }
3281
3282 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3283 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3284 Assembler::vpsubb(dst, nds, src, vector_len);
3285 }
3286
3287 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3288 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3289 Assembler::vpsubw(dst, nds, src, vector_len);
3290 }
3291
3292 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3293 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3294 Assembler::vpsubw(dst, nds, src, vector_len);
3295 }
3296
3297 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3298 assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3299 Assembler::vpsraw(dst, nds, shift, vector_len);
3300 }
3301
3302 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3303 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3304 Assembler::vpsraw(dst, nds, shift, vector_len);
3305 }
3306
3307 void MacroAssembler::evpsraq(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3308 assert(UseAVX > 2,"");
3309 if (!VM_Version::supports_avx512vl() && vector_len < 2) {
3310 vector_len = 2;
3311 }
3312 Assembler::evpsraq(dst, nds, shift, vector_len);
3313 }
3314
3315 void MacroAssembler::evpsraq(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3316 assert(UseAVX > 2,"");
3317 if (!VM_Version::supports_avx512vl() && vector_len < 2) {
3318 vector_len = 2;
3319 }
3320 Assembler::evpsraq(dst, nds, shift, vector_len);
3321 }
3322
3323 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3324 assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3325 Assembler::vpsrlw(dst, nds, shift, vector_len);
3326 }
3327
3328 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3329 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3330 Assembler::vpsrlw(dst, nds, shift, vector_len);
3331 }
3332
3333 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3334 assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3335 Assembler::vpsllw(dst, nds, shift, vector_len);
3336 }
3337
3338 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3339 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3340 Assembler::vpsllw(dst, nds, shift, vector_len);
3341 }
3342
3343 void MacroAssembler::vptest(XMMRegister dst, XMMRegister src) {
3344 assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
3345 Assembler::vptest(dst, src);
3346 }
3347
3348 void MacroAssembler::punpcklbw(XMMRegister dst, XMMRegister src) {
3349 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3350 Assembler::punpcklbw(dst, src);
3351 }
3352
3353 void MacroAssembler::pshufd(XMMRegister dst, Address src, int mode) {
3354 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
3355 Assembler::pshufd(dst, src, mode);
3356 }
3357
3358 void MacroAssembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
3359 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3360 Assembler::pshuflw(dst, src, mode);
3361 }
3362
3363 void MacroAssembler::vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg) {
3364 if (reachable(src)) {
3365 vandpd(dst, nds, as_Address(src), vector_len);
3366 } else {
3367 lea(scratch_reg, src);
3368 vandpd(dst, nds, Address(scratch_reg, 0), vector_len);
3369 }
3370 }
3371
3372 void MacroAssembler::vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg) {
3373 if (reachable(src)) {
3374 vandps(dst, nds, as_Address(src), vector_len);
3375 } else {
3376 lea(scratch_reg, src);
3377 vandps(dst, nds, Address(scratch_reg, 0), vector_len);
3378 }
3379 }
3380
3381 void MacroAssembler::evpord(XMMRegister dst, KRegister mask, XMMRegister nds, AddressLiteral src,
3382 bool merge, int vector_len, Register scratch_reg) {
3383 if (reachable(src)) {
3384 Assembler::evpord(dst, mask, nds, as_Address(src), merge, vector_len);
3385 } else {
3386 lea(scratch_reg, src);
3387 Assembler::evpord(dst, mask, nds, Address(scratch_reg, 0), merge, vector_len);
3388 }
3389 }
3390
3391 void MacroAssembler::vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3392 if (reachable(src)) {
3393 vdivsd(dst, nds, as_Address(src));
3394 } else {
3395 lea(rscratch1, src);
3396 vdivsd(dst, nds, Address(rscratch1, 0));
3397 }
3398 }
3399
3400 void MacroAssembler::vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3401 if (reachable(src)) {
3402 vdivss(dst, nds, as_Address(src));
3403 } else {
3404 lea(rscratch1, src);
3405 vdivss(dst, nds, Address(rscratch1, 0));
3406 }
3407 }
3408
3409 void MacroAssembler::vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3410 if (reachable(src)) {
3411 vmulsd(dst, nds, as_Address(src));
3412 } else {
3413 lea(rscratch1, src);
3414 vmulsd(dst, nds, Address(rscratch1, 0));
3415 }
3416 }
3417
3418 void MacroAssembler::vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3419 if (reachable(src)) {
3420 vmulss(dst, nds, as_Address(src));
3421 } else {
3422 lea(rscratch1, src);
3423 vmulss(dst, nds, Address(rscratch1, 0));
3424 }
3425 }
3426
3427 void MacroAssembler::vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3428 if (reachable(src)) {
3429 vsubsd(dst, nds, as_Address(src));
3430 } else {
3431 lea(rscratch1, src);
3432 vsubsd(dst, nds, Address(rscratch1, 0));
3433 }
3434 }
3435
3436 void MacroAssembler::vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3437 if (reachable(src)) {
3438 vsubss(dst, nds, as_Address(src));
3439 } else {
3440 lea(rscratch1, src);
3441 vsubss(dst, nds, Address(rscratch1, 0));
3442 }
3443 }
3444
3445 void MacroAssembler::vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3446 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
3447 vxorps(dst, nds, src, Assembler::AVX_128bit);
3448 }
3449
3450 void MacroAssembler::vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3451 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
3452 vxorpd(dst, nds, src, Assembler::AVX_128bit);
3453 }
3454
3455 void MacroAssembler::vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg) {
3456 if (reachable(src)) {
3457 vxorpd(dst, nds, as_Address(src), vector_len);
3458 } else {
3459 lea(scratch_reg, src);
3460 vxorpd(dst, nds, Address(scratch_reg, 0), vector_len);
3461 }
3462 }
3463
3464 void MacroAssembler::vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg) {
3465 if (reachable(src)) {
3466 vxorps(dst, nds, as_Address(src), vector_len);
3467 } else {
3468 lea(scratch_reg, src);
3469 vxorps(dst, nds, Address(scratch_reg, 0), vector_len);
3470 }
3471 }
3472
3473 void MacroAssembler::vpxor(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg) {
3474 if (UseAVX > 1 || (vector_len < 1)) {
3475 if (reachable(src)) {
3476 Assembler::vpxor(dst, nds, as_Address(src), vector_len);
3477 } else {
3478 lea(scratch_reg, src);
3479 Assembler::vpxor(dst, nds, Address(scratch_reg, 0), vector_len);
3480 }
3481 }
3482 else {
3483 MacroAssembler::vxorpd(dst, nds, src, vector_len, scratch_reg);
3484 }
3485 }
3486
3487 void MacroAssembler::vpermd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg) {
3488 if (reachable(src)) {
3489 Assembler::vpermd(dst, nds, as_Address(src), vector_len);
3490 } else {
3491 lea(scratch_reg, src);
3492 Assembler::vpermd(dst, nds, Address(scratch_reg, 0), vector_len);
3493 }
3494 }
3495
3496 void MacroAssembler::clear_jweak_tag(Register possibly_jweak) {
3497 const int32_t inverted_jweak_mask = ~static_cast<int32_t>(JNIHandles::weak_tag_mask);
3498 STATIC_ASSERT(inverted_jweak_mask == -2); // otherwise check this code
3499 // The inverted mask is sign-extended
3500 andptr(possibly_jweak, inverted_jweak_mask);
3501 }
3502
3503 void MacroAssembler::resolve_jobject(Register value,
3504 Register thread,
3505 Register tmp) {
3506 assert_different_registers(value, thread, tmp);
3507 Label done, not_weak;
3508 testptr(value, value);
3509 jcc(Assembler::zero, done); // Use NULL as-is.
3510 testptr(value, JNIHandles::weak_tag_mask); // Test for jweak tag.
3511 jcc(Assembler::zero, not_weak);
3512 // Resolve jweak.
3513 access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF,
3514 value, Address(value, -JNIHandles::weak_tag_value), tmp, thread);
3515 verify_oop(value);
3516 jmp(done);
3517 bind(not_weak);
3518 // Resolve (untagged) jobject.
3519 access_load_at(T_OBJECT, IN_NATIVE, value, Address(value, 0), tmp, thread);
3520 verify_oop(value);
3521 bind(done);
3522 }
3523
3524 void MacroAssembler::subptr(Register dst, int32_t imm32) {
3525 LP64_ONLY(subq(dst, imm32)) NOT_LP64(subl(dst, imm32));
3526 }
3527
3528 // Force generation of a 4 byte immediate value even if it fits into 8bit
3529 void MacroAssembler::subptr_imm32(Register dst, int32_t imm32) {
3530 LP64_ONLY(subq_imm32(dst, imm32)) NOT_LP64(subl_imm32(dst, imm32));
3531 }
3532
3533 void MacroAssembler::subptr(Register dst, Register src) {
3534 LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src));
3535 }
3536
3537 // C++ bool manipulation
3538 void MacroAssembler::testbool(Register dst) {
3539 if(sizeof(bool) == 1)
3540 testb(dst, 0xff);
3541 else if(sizeof(bool) == 2) {
3542 // testw implementation needed for two byte bools
3543 ShouldNotReachHere();
3544 } else if(sizeof(bool) == 4)
3545 testl(dst, dst);
3546 else
3547 // unsupported
3548 ShouldNotReachHere();
3549 }
3550
3551 void MacroAssembler::testptr(Register dst, Register src) {
3552 LP64_ONLY(testq(dst, src)) NOT_LP64(testl(dst, src));
3553 }
3554
3555 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
3556 void MacroAssembler::tlab_allocate(Register thread, Register obj,
3557 Register var_size_in_bytes,
3558 int con_size_in_bytes,
3559 Register t1,
3560 Register t2,
3561 Label& slow_case) {
3562 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
3563 bs->tlab_allocate(this, thread, obj, var_size_in_bytes, con_size_in_bytes, t1, t2, slow_case);
3564 }
3565
3566 // Defines obj, preserves var_size_in_bytes
3567 void MacroAssembler::eden_allocate(Register thread, Register obj,
3568 Register var_size_in_bytes,
3569 int con_size_in_bytes,
3570 Register t1,
3571 Label& slow_case) {
3572 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
3573 bs->eden_allocate(this, thread, obj, var_size_in_bytes, con_size_in_bytes, t1, slow_case);
3574 }
3575
3576 // Preserves the contents of address, destroys the contents length_in_bytes and temp.
3577 void MacroAssembler::zero_memory(Register address, Register length_in_bytes, int offset_in_bytes, Register temp) {
3578 assert(address != length_in_bytes && address != temp && temp != length_in_bytes, "registers must be different");
3579 assert((offset_in_bytes & (BytesPerWord - 1)) == 0, "offset must be a multiple of BytesPerWord");
3580 Label done;
3581
3582 testptr(length_in_bytes, length_in_bytes);
3583 jcc(Assembler::zero, done);
3584
3585 // initialize topmost word, divide index by 2, check if odd and test if zero
3586 // note: for the remaining code to work, index must be a multiple of BytesPerWord
3587 #ifdef ASSERT
3588 {
3589 Label L;
3590 testptr(length_in_bytes, BytesPerWord - 1);
3591 jcc(Assembler::zero, L);
3592 stop("length must be a multiple of BytesPerWord");
3593 bind(L);
3594 }
3595 #endif
3596 Register index = length_in_bytes;
3597 xorptr(temp, temp); // use _zero reg to clear memory (shorter code)
3598 if (UseIncDec) {
3599 shrptr(index, 3); // divide by 8/16 and set carry flag if bit 2 was set
3600 } else {
3601 shrptr(index, 2); // use 2 instructions to avoid partial flag stall
3602 shrptr(index, 1);
3603 }
3604 #ifndef _LP64
3605 // index could have not been a multiple of 8 (i.e., bit 2 was set)
3606 {
3607 Label even;
3608 // note: if index was a multiple of 8, then it cannot
3609 // be 0 now otherwise it must have been 0 before
3610 // => if it is even, we don't need to check for 0 again
3611 jcc(Assembler::carryClear, even);
3612 // clear topmost word (no jump would be needed if conditional assignment worked here)
3613 movptr(Address(address, index, Address::times_8, offset_in_bytes - 0*BytesPerWord), temp);
3614 // index could be 0 now, must check again
3615 jcc(Assembler::zero, done);
3616 bind(even);
3617 }
3618 #endif // !_LP64
3619 // initialize remaining object fields: index is a multiple of 2 now
3620 {
3621 Label loop;
3622 bind(loop);
3623 movptr(Address(address, index, Address::times_8, offset_in_bytes - 1*BytesPerWord), temp);
3624 NOT_LP64(movptr(Address(address, index, Address::times_8, offset_in_bytes - 2*BytesPerWord), temp);)
3625 decrement(index);
3626 jcc(Assembler::notZero, loop);
3627 }
3628
3629 bind(done);
3630 }
3631
3632 // Look up the method for a megamorphic invokeinterface call.
3633 // The target method is determined by <intf_klass, itable_index>.
3634 // The receiver klass is in recv_klass.
3635 // On success, the result will be in method_result, and execution falls through.
3636 // On failure, execution transfers to the given label.
3637 void MacroAssembler::lookup_interface_method(Register recv_klass,
3638 Register intf_klass,
3639 RegisterOrConstant itable_index,
3640 Register method_result,
3641 Register scan_temp,
3642 Label& L_no_such_interface,
3643 bool return_method) {
3644 assert_different_registers(recv_klass, intf_klass, scan_temp);
3645 assert_different_registers(method_result, intf_klass, scan_temp);
3646 assert(recv_klass != method_result || !return_method,
3647 "recv_klass can be destroyed when method isn't needed");
3648
3649 assert(itable_index.is_constant() || itable_index.as_register() == method_result,
3650 "caller must use same register for non-constant itable index as for method");
3651
3652 // Compute start of first itableOffsetEntry (which is at the end of the vtable)
3653 int vtable_base = in_bytes(Klass::vtable_start_offset());
3654 int itentry_off = itableMethodEntry::method_offset_in_bytes();
3655 int scan_step = itableOffsetEntry::size() * wordSize;
3656 int vte_size = vtableEntry::size_in_bytes();
3657 Address::ScaleFactor times_vte_scale = Address::times_ptr;
3658 assert(vte_size == wordSize, "else adjust times_vte_scale");
3659
3660 movl(scan_temp, Address(recv_klass, Klass::vtable_length_offset()));
3661
3662 // %%% Could store the aligned, prescaled offset in the klassoop.
3663 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base));
3664
3665 if (return_method) {
3666 // Adjust recv_klass by scaled itable_index, so we can free itable_index.
3667 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
3668 lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off));
3669 }
3670
3671 // for (scan = klass->itable(); scan->interface() != NULL; scan += scan_step) {
3672 // if (scan->interface() == intf) {
3673 // result = (klass + scan->offset() + itable_index);
3674 // }
3675 // }
3676 Label search, found_method;
3677
3678 for (int peel = 1; peel >= 0; peel--) {
3679 movptr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset_in_bytes()));
3680 cmpptr(intf_klass, method_result);
3681
3682 if (peel) {
3683 jccb(Assembler::equal, found_method);
3684 } else {
3685 jccb(Assembler::notEqual, search);
3686 // (invert the test to fall through to found_method...)
3687 }
3688
3689 if (!peel) break;
3690
3691 bind(search);
3692
3693 // Check that the previous entry is non-null. A null entry means that
3694 // the receiver class doesn't implement the interface, and wasn't the
3695 // same as when the caller was compiled.
3696 testptr(method_result, method_result);
3697 jcc(Assembler::zero, L_no_such_interface);
3698 addptr(scan_temp, scan_step);
3699 }
3700
3701 bind(found_method);
3702
3703 if (return_method) {
3704 // Got a hit.
3705 movl(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset_in_bytes()));
3706 movptr(method_result, Address(recv_klass, scan_temp, Address::times_1));
3707 }
3708 }
3709
3710
3711 // virtual method calling
3712 void MacroAssembler::lookup_virtual_method(Register recv_klass,
3713 RegisterOrConstant vtable_index,
3714 Register method_result) {
3715 const int base = in_bytes(Klass::vtable_start_offset());
3716 assert(vtableEntry::size() * wordSize == wordSize, "else adjust the scaling in the code below");
3717 Address vtable_entry_addr(recv_klass,
3718 vtable_index, Address::times_ptr,
3719 base + vtableEntry::method_offset_in_bytes());
3720 movptr(method_result, vtable_entry_addr);
3721 }
3722
3723
3724 void MacroAssembler::check_klass_subtype(Register sub_klass,
3725 Register super_klass,
3726 Register temp_reg,
3727 Label& L_success) {
3728 Label L_failure;
3729 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, NULL);
3730 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, NULL);
3731 bind(L_failure);
3732 }
3733
3734
3735 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
3736 Register super_klass,
3737 Register temp_reg,
3738 Label* L_success,
3739 Label* L_failure,
3740 Label* L_slow_path,
3741 RegisterOrConstant super_check_offset) {
3742 assert_different_registers(sub_klass, super_klass, temp_reg);
3743 bool must_load_sco = (super_check_offset.constant_or_zero() == -1);
3744 if (super_check_offset.is_register()) {
3745 assert_different_registers(sub_klass, super_klass,
3746 super_check_offset.as_register());
3747 } else if (must_load_sco) {
3748 assert(temp_reg != noreg, "supply either a temp or a register offset");
3749 }
3750
3751 Label L_fallthrough;
3752 int label_nulls = 0;
3753 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
3754 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
3755 if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; }
3756 assert(label_nulls <= 1, "at most one NULL in the batch");
3757
3758 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
3759 int sco_offset = in_bytes(Klass::super_check_offset_offset());
3760 Address super_check_offset_addr(super_klass, sco_offset);
3761
3762 // Hacked jcc, which "knows" that L_fallthrough, at least, is in
3763 // range of a jccb. If this routine grows larger, reconsider at
3764 // least some of these.
3765 #define local_jcc(assembler_cond, label) \
3766 if (&(label) == &L_fallthrough) jccb(assembler_cond, label); \
3767 else jcc( assembler_cond, label) /*omit semi*/
3768
3769 // Hacked jmp, which may only be used just before L_fallthrough.
3770 #define final_jmp(label) \
3771 if (&(label) == &L_fallthrough) { /*do nothing*/ } \
3772 else jmp(label) /*omit semi*/
3773
3774 // If the pointers are equal, we are done (e.g., String[] elements).
3775 // This self-check enables sharing of secondary supertype arrays among
3776 // non-primary types such as array-of-interface. Otherwise, each such
3777 // type would need its own customized SSA.
3778 // We move this check to the front of the fast path because many
3779 // type checks are in fact trivially successful in this manner,
3780 // so we get a nicely predicted branch right at the start of the check.
3781 cmpptr(sub_klass, super_klass);
3782 local_jcc(Assembler::equal, *L_success);
3783
3784 // Check the supertype display:
3785 if (must_load_sco) {
3786 // Positive movl does right thing on LP64.
3787 movl(temp_reg, super_check_offset_addr);
3788 super_check_offset = RegisterOrConstant(temp_reg);
3789 }
3790 Address super_check_addr(sub_klass, super_check_offset, Address::times_1, 0);
3791 cmpptr(super_klass, super_check_addr); // load displayed supertype
3792
3793 // This check has worked decisively for primary supers.
3794 // Secondary supers are sought in the super_cache ('super_cache_addr').
3795 // (Secondary supers are interfaces and very deeply nested subtypes.)
3796 // This works in the same check above because of a tricky aliasing
3797 // between the super_cache and the primary super display elements.
3798 // (The 'super_check_addr' can address either, as the case requires.)
3799 // Note that the cache is updated below if it does not help us find
3800 // what we need immediately.
3801 // So if it was a primary super, we can just fail immediately.
3802 // Otherwise, it's the slow path for us (no success at this point).
3803
3804 if (super_check_offset.is_register()) {
3805 local_jcc(Assembler::equal, *L_success);
3806 cmpl(super_check_offset.as_register(), sc_offset);
3807 if (L_failure == &L_fallthrough) {
3808 local_jcc(Assembler::equal, *L_slow_path);
3809 } else {
3810 local_jcc(Assembler::notEqual, *L_failure);
3811 final_jmp(*L_slow_path);
3812 }
3813 } else if (super_check_offset.as_constant() == sc_offset) {
3814 // Need a slow path; fast failure is impossible.
3815 if (L_slow_path == &L_fallthrough) {
3816 local_jcc(Assembler::equal, *L_success);
3817 } else {
3818 local_jcc(Assembler::notEqual, *L_slow_path);
3819 final_jmp(*L_success);
3820 }
3821 } else {
3822 // No slow path; it's a fast decision.
3823 if (L_failure == &L_fallthrough) {
3824 local_jcc(Assembler::equal, *L_success);
3825 } else {
3826 local_jcc(Assembler::notEqual, *L_failure);
3827 final_jmp(*L_success);
3828 }
3829 }
3830
3831 bind(L_fallthrough);
3832
3833 #undef local_jcc
3834 #undef final_jmp
3835 }
3836
3837
3838 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
3839 Register super_klass,
3840 Register temp_reg,
3841 Register temp2_reg,
3842 Label* L_success,
3843 Label* L_failure,
3844 bool set_cond_codes) {
3845 assert_different_registers(sub_klass, super_klass, temp_reg);
3846 if (temp2_reg != noreg)
3847 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg);
3848 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg)
3849
3850 Label L_fallthrough;
3851 int label_nulls = 0;
3852 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
3853 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
3854 assert(label_nulls <= 1, "at most one NULL in the batch");
3855
3856 // a couple of useful fields in sub_klass:
3857 int ss_offset = in_bytes(Klass::secondary_supers_offset());
3858 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
3859 Address secondary_supers_addr(sub_klass, ss_offset);
3860 Address super_cache_addr( sub_klass, sc_offset);
3861
3862 // Do a linear scan of the secondary super-klass chain.
3863 // This code is rarely used, so simplicity is a virtue here.
3864 // The repne_scan instruction uses fixed registers, which we must spill.
3865 // Don't worry too much about pre-existing connections with the input regs.
3866
3867 assert(sub_klass != rax, "killed reg"); // killed by mov(rax, super)
3868 assert(sub_klass != rcx, "killed reg"); // killed by lea(rcx, &pst_counter)
3869
3870 // Get super_klass value into rax (even if it was in rdi or rcx).
3871 bool pushed_rax = false, pushed_rcx = false, pushed_rdi = false;
3872 if (super_klass != rax || UseCompressedOops) {
3873 if (!IS_A_TEMP(rax)) { push(rax); pushed_rax = true; }
3874 mov(rax, super_klass);
3875 }
3876 if (!IS_A_TEMP(rcx)) { push(rcx); pushed_rcx = true; }
3877 if (!IS_A_TEMP(rdi)) { push(rdi); pushed_rdi = true; }
3878
3879 #ifndef PRODUCT
3880 int* pst_counter = &SharedRuntime::_partial_subtype_ctr;
3881 ExternalAddress pst_counter_addr((address) pst_counter);
3882 NOT_LP64( incrementl(pst_counter_addr) );
3883 LP64_ONLY( lea(rcx, pst_counter_addr) );
3884 LP64_ONLY( incrementl(Address(rcx, 0)) );
3885 #endif //PRODUCT
3886
3887 // We will consult the secondary-super array.
3888 movptr(rdi, secondary_supers_addr);
3889 // Load the array length. (Positive movl does right thing on LP64.)
3890 movl(rcx, Address(rdi, Array<Klass*>::length_offset_in_bytes()));
3891 // Skip to start of data.
3892 addptr(rdi, Array<Klass*>::base_offset_in_bytes());
3893
3894 // Scan RCX words at [RDI] for an occurrence of RAX.
3895 // Set NZ/Z based on last compare.
3896 // Z flag value will not be set by 'repne' if RCX == 0 since 'repne' does
3897 // not change flags (only scas instruction which is repeated sets flags).
3898 // Set Z = 0 (not equal) before 'repne' to indicate that class was not found.
3899
3900 testptr(rax,rax); // Set Z = 0
3901 repne_scan();
3902
3903 // Unspill the temp. registers:
3904 if (pushed_rdi) pop(rdi);
3905 if (pushed_rcx) pop(rcx);
3906 if (pushed_rax) pop(rax);
3907
3908 if (set_cond_codes) {
3909 // Special hack for the AD files: rdi is guaranteed non-zero.
3910 assert(!pushed_rdi, "rdi must be left non-NULL");
3911 // Also, the condition codes are properly set Z/NZ on succeed/failure.
3912 }
3913
3914 if (L_failure == &L_fallthrough)
3915 jccb(Assembler::notEqual, *L_failure);
3916 else jcc(Assembler::notEqual, *L_failure);
3917
3918 // Success. Cache the super we found and proceed in triumph.
3919 movptr(super_cache_addr, super_klass);
3920
3921 if (L_success != &L_fallthrough) {
3922 jmp(*L_success);
3923 }
3924
3925 #undef IS_A_TEMP
3926
3927 bind(L_fallthrough);
3928 }
3929
3930 void MacroAssembler::clinit_barrier(Register klass, Register thread, Label* L_fast_path, Label* L_slow_path) {
3931 assert(L_fast_path != NULL || L_slow_path != NULL, "at least one is required");
3932
3933 Label L_fallthrough;
3934 if (L_fast_path == NULL) {
3935 L_fast_path = &L_fallthrough;
3936 } else if (L_slow_path == NULL) {
3937 L_slow_path = &L_fallthrough;
3938 }
3939
3940 // Fast path check: class is fully initialized
3941 cmpb(Address(klass, InstanceKlass::init_state_offset()), InstanceKlass::fully_initialized);
3942 jcc(Assembler::equal, *L_fast_path);
3943
3944 // Fast path check: current thread is initializer thread
3945 cmpptr(thread, Address(klass, InstanceKlass::init_thread_offset()));
3946 if (L_slow_path == &L_fallthrough) {
3947 jcc(Assembler::equal, *L_fast_path);
3948 bind(*L_slow_path);
3949 } else if (L_fast_path == &L_fallthrough) {
3950 jcc(Assembler::notEqual, *L_slow_path);
3951 bind(*L_fast_path);
3952 } else {
3953 Unimplemented();
3954 }
3955 }
3956
3957 void MacroAssembler::cmov32(Condition cc, Register dst, Address src) {
3958 if (VM_Version::supports_cmov()) {
3959 cmovl(cc, dst, src);
3960 } else {
3961 Label L;
3962 jccb(negate_condition(cc), L);
3963 movl(dst, src);
3964 bind(L);
3965 }
3966 }
3967
3968 void MacroAssembler::cmov32(Condition cc, Register dst, Register src) {
3969 if (VM_Version::supports_cmov()) {
3970 cmovl(cc, dst, src);
3971 } else {
3972 Label L;
3973 jccb(negate_condition(cc), L);
3974 movl(dst, src);
3975 bind(L);
3976 }
3977 }
3978
3979 void MacroAssembler::_verify_oop(Register reg, const char* s, const char* file, int line) {
3980 if (!VerifyOops) return;
3981
3982 // Pass register number to verify_oop_subroutine
3983 const char* b = NULL;
3984 {
3985 ResourceMark rm;
3986 stringStream ss;
3987 ss.print("verify_oop: %s: %s (%s:%d)", reg->name(), s, file, line);
3988 b = code_string(ss.as_string());
3989 }
3990 BLOCK_COMMENT("verify_oop {");
3991 #ifdef _LP64
3992 push(rscratch1); // save r10, trashed by movptr()
3993 #endif
3994 push(rax); // save rax,
3995 push(reg); // pass register argument
3996 ExternalAddress buffer((address) b);
3997 // avoid using pushptr, as it modifies scratch registers
3998 // and our contract is not to modify anything
3999 movptr(rax, buffer.addr());
4000 push(rax);
4001 // call indirectly to solve generation ordering problem
4002 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
4003 call(rax);
4004 // Caller pops the arguments (oop, message) and restores rax, r10
4005 BLOCK_COMMENT("} verify_oop");
4006 }
4007
4008 void MacroAssembler::vallones(XMMRegister dst, int vector_len) {
4009 if (UseAVX > 2 && (vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl())) {
4010 vpternlogd(dst, 0xFF, dst, dst, vector_len);
4011 } else {
4012 assert(UseAVX > 0, "");
4013 vpcmpeqb(dst, dst, dst, vector_len);
4014 }
4015 }
4016
4017 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot,
4018 int extra_slot_offset) {
4019 // cf. TemplateTable::prepare_invoke(), if (load_receiver).
4020 int stackElementSize = Interpreter::stackElementSize;
4021 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0);
4022 #ifdef ASSERT
4023 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1);
4024 assert(offset1 - offset == stackElementSize, "correct arithmetic");
4025 #endif
4026 Register scale_reg = noreg;
4027 Address::ScaleFactor scale_factor = Address::no_scale;
4028 if (arg_slot.is_constant()) {
4029 offset += arg_slot.as_constant() * stackElementSize;
4030 } else {
4031 scale_reg = arg_slot.as_register();
4032 scale_factor = Address::times(stackElementSize);
4033 }
4034 offset += wordSize; // return PC is on stack
4035 return Address(rsp, scale_reg, scale_factor, offset);
4036 }
4037
4038 void MacroAssembler::_verify_oop_addr(Address addr, const char* s, const char* file, int line) {
4039 if (!VerifyOops) return;
4040
4041 // Address adjust(addr.base(), addr.index(), addr.scale(), addr.disp() + BytesPerWord);
4042 // Pass register number to verify_oop_subroutine
4043 const char* b = NULL;
4044 {
4045 ResourceMark rm;
4046 stringStream ss;
4047 ss.print("verify_oop_addr: %s (%s:%d)", s, file, line);
4048 b = code_string(ss.as_string());
4049 }
4050 #ifdef _LP64
4051 push(rscratch1); // save r10, trashed by movptr()
4052 #endif
4053 push(rax); // save rax,
4054 // addr may contain rsp so we will have to adjust it based on the push
4055 // we just did (and on 64 bit we do two pushes)
4056 // NOTE: 64bit seemed to have had a bug in that it did movq(addr, rax); which
4057 // stores rax into addr which is backwards of what was intended.
4058 if (addr.uses(rsp)) {
4059 lea(rax, addr);
4060 pushptr(Address(rax, LP64_ONLY(2 *) BytesPerWord));
4061 } else {
4062 pushptr(addr);
4063 }
4064
4065 ExternalAddress buffer((address) b);
4066 // pass msg argument
4067 // avoid using pushptr, as it modifies scratch registers
4068 // and our contract is not to modify anything
4069 movptr(rax, buffer.addr());
4070 push(rax);
4071
4072 // call indirectly to solve generation ordering problem
4073 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
4074 call(rax);
4075 // Caller pops the arguments (addr, message) and restores rax, r10.
4076 }
4077
4078 void MacroAssembler::verify_tlab() {
4079 #ifdef ASSERT
4080 if (UseTLAB && VerifyOops) {
4081 Label next, ok;
4082 Register t1 = rsi;
4083 Register thread_reg = NOT_LP64(rbx) LP64_ONLY(r15_thread);
4084
4085 push(t1);
4086 NOT_LP64(push(thread_reg));
4087 NOT_LP64(get_thread(thread_reg));
4088
4089 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
4090 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())));
4091 jcc(Assembler::aboveEqual, next);
4092 STOP("assert(top >= start)");
4093 should_not_reach_here();
4094
4095 bind(next);
4096 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())));
4097 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
4098 jcc(Assembler::aboveEqual, ok);
4099 STOP("assert(top <= end)");
4100 should_not_reach_here();
4101
4102 bind(ok);
4103 NOT_LP64(pop(thread_reg));
4104 pop(t1);
4105 }
4106 #endif
4107 }
4108
4109 class ControlWord {
4110 public:
4111 int32_t _value;
4112
4113 int rounding_control() const { return (_value >> 10) & 3 ; }
4114 int precision_control() const { return (_value >> 8) & 3 ; }
4115 bool precision() const { return ((_value >> 5) & 1) != 0; }
4116 bool underflow() const { return ((_value >> 4) & 1) != 0; }
4117 bool overflow() const { return ((_value >> 3) & 1) != 0; }
4118 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
4119 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
4120 bool invalid() const { return ((_value >> 0) & 1) != 0; }
4121
4122 void print() const {
4123 // rounding control
4124 const char* rc;
4125 switch (rounding_control()) {
4126 case 0: rc = "round near"; break;
4127 case 1: rc = "round down"; break;
4128 case 2: rc = "round up "; break;
4129 case 3: rc = "chop "; break;
4130 default:
4131 rc = NULL; // silence compiler warnings
4132 fatal("Unknown rounding control: %d", rounding_control());
4133 };
4134 // precision control
4135 const char* pc;
4136 switch (precision_control()) {
4137 case 0: pc = "24 bits "; break;
4138 case 1: pc = "reserved"; break;
4139 case 2: pc = "53 bits "; break;
4140 case 3: pc = "64 bits "; break;
4141 default:
4142 pc = NULL; // silence compiler warnings
4143 fatal("Unknown precision control: %d", precision_control());
4144 };
4145 // flags
4146 char f[9];
4147 f[0] = ' ';
4148 f[1] = ' ';
4149 f[2] = (precision ()) ? 'P' : 'p';
4150 f[3] = (underflow ()) ? 'U' : 'u';
4151 f[4] = (overflow ()) ? 'O' : 'o';
4152 f[5] = (zero_divide ()) ? 'Z' : 'z';
4153 f[6] = (denormalized()) ? 'D' : 'd';
4154 f[7] = (invalid ()) ? 'I' : 'i';
4155 f[8] = '\x0';
4156 // output
4157 printf("%04x masks = %s, %s, %s", _value & 0xFFFF, f, rc, pc);
4158 }
4159
4160 };
4161
4162 class StatusWord {
4163 public:
4164 int32_t _value;
4165
4166 bool busy() const { return ((_value >> 15) & 1) != 0; }
4167 bool C3() const { return ((_value >> 14) & 1) != 0; }
4168 bool C2() const { return ((_value >> 10) & 1) != 0; }
4169 bool C1() const { return ((_value >> 9) & 1) != 0; }
4170 bool C0() const { return ((_value >> 8) & 1) != 0; }
4171 int top() const { return (_value >> 11) & 7 ; }
4172 bool error_status() const { return ((_value >> 7) & 1) != 0; }
4173 bool stack_fault() const { return ((_value >> 6) & 1) != 0; }
4174 bool precision() const { return ((_value >> 5) & 1) != 0; }
4175 bool underflow() const { return ((_value >> 4) & 1) != 0; }
4176 bool overflow() const { return ((_value >> 3) & 1) != 0; }
4177 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
4178 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
4179 bool invalid() const { return ((_value >> 0) & 1) != 0; }
4180
4181 void print() const {
4182 // condition codes
4183 char c[5];
4184 c[0] = (C3()) ? '3' : '-';
4185 c[1] = (C2()) ? '2' : '-';
4186 c[2] = (C1()) ? '1' : '-';
4187 c[3] = (C0()) ? '0' : '-';
4188 c[4] = '\x0';
4189 // flags
4190 char f[9];
4191 f[0] = (error_status()) ? 'E' : '-';
4192 f[1] = (stack_fault ()) ? 'S' : '-';
4193 f[2] = (precision ()) ? 'P' : '-';
4194 f[3] = (underflow ()) ? 'U' : '-';
4195 f[4] = (overflow ()) ? 'O' : '-';
4196 f[5] = (zero_divide ()) ? 'Z' : '-';
4197 f[6] = (denormalized()) ? 'D' : '-';
4198 f[7] = (invalid ()) ? 'I' : '-';
4199 f[8] = '\x0';
4200 // output
4201 printf("%04x flags = %s, cc = %s, top = %d", _value & 0xFFFF, f, c, top());
4202 }
4203
4204 };
4205
4206 class TagWord {
4207 public:
4208 int32_t _value;
4209
4210 int tag_at(int i) const { return (_value >> (i*2)) & 3; }
4211
4212 void print() const {
4213 printf("%04x", _value & 0xFFFF);
4214 }
4215
4216 };
4217
4218 class FPU_Register {
4219 public:
4220 int32_t _m0;
4221 int32_t _m1;
4222 int16_t _ex;
4223
4224 bool is_indefinite() const {
4225 return _ex == -1 && _m1 == (int32_t)0xC0000000 && _m0 == 0;
4226 }
4227
4228 void print() const {
4229 char sign = (_ex < 0) ? '-' : '+';
4230 const char* kind = (_ex == 0x7FFF || _ex == (int16_t)-1) ? "NaN" : " ";
4231 printf("%c%04hx.%08x%08x %s", sign, _ex, _m1, _m0, kind);
4232 };
4233
4234 };
4235
4236 class FPU_State {
4237 public:
4238 enum {
4239 register_size = 10,
4240 number_of_registers = 8,
4241 register_mask = 7
4242 };
4243
4244 ControlWord _control_word;
4245 StatusWord _status_word;
4246 TagWord _tag_word;
4247 int32_t _error_offset;
4248 int32_t _error_selector;
4249 int32_t _data_offset;
4250 int32_t _data_selector;
4251 int8_t _register[register_size * number_of_registers];
4252
4253 int tag_for_st(int i) const { return _tag_word.tag_at((_status_word.top() + i) & register_mask); }
4254 FPU_Register* st(int i) const { return (FPU_Register*)&_register[register_size * i]; }
4255
4256 const char* tag_as_string(int tag) const {
4257 switch (tag) {
4258 case 0: return "valid";
4259 case 1: return "zero";
4260 case 2: return "special";
4261 case 3: return "empty";
4262 }
4263 ShouldNotReachHere();
4264 return NULL;
4265 }
4266
4267 void print() const {
4268 // print computation registers
4269 { int t = _status_word.top();
4270 for (int i = 0; i < number_of_registers; i++) {
4271 int j = (i - t) & register_mask;
4272 printf("%c r%d = ST%d = ", (j == 0 ? '*' : ' '), i, j);
4273 st(j)->print();
4274 printf(" %s\n", tag_as_string(_tag_word.tag_at(i)));
4275 }
4276 }
4277 printf("\n");
4278 // print control registers
4279 printf("ctrl = "); _control_word.print(); printf("\n");
4280 printf("stat = "); _status_word .print(); printf("\n");
4281 printf("tags = "); _tag_word .print(); printf("\n");
4282 }
4283
4284 };
4285
4286 class Flag_Register {
4287 public:
4288 int32_t _value;
4289
4290 bool overflow() const { return ((_value >> 11) & 1) != 0; }
4291 bool direction() const { return ((_value >> 10) & 1) != 0; }
4292 bool sign() const { return ((_value >> 7) & 1) != 0; }
4293 bool zero() const { return ((_value >> 6) & 1) != 0; }
4294 bool auxiliary_carry() const { return ((_value >> 4) & 1) != 0; }
4295 bool parity() const { return ((_value >> 2) & 1) != 0; }
4296 bool carry() const { return ((_value >> 0) & 1) != 0; }
4297
4298 void print() const {
4299 // flags
4300 char f[8];
4301 f[0] = (overflow ()) ? 'O' : '-';
4302 f[1] = (direction ()) ? 'D' : '-';
4303 f[2] = (sign ()) ? 'S' : '-';
4304 f[3] = (zero ()) ? 'Z' : '-';
4305 f[4] = (auxiliary_carry()) ? 'A' : '-';
4306 f[5] = (parity ()) ? 'P' : '-';
4307 f[6] = (carry ()) ? 'C' : '-';
4308 f[7] = '\x0';
4309 // output
4310 printf("%08x flags = %s", _value, f);
4311 }
4312
4313 };
4314
4315 class IU_Register {
4316 public:
4317 int32_t _value;
4318
4319 void print() const {
4320 printf("%08x %11d", _value, _value);
4321 }
4322
4323 };
4324
4325 class IU_State {
4326 public:
4327 Flag_Register _eflags;
4328 IU_Register _rdi;
4329 IU_Register _rsi;
4330 IU_Register _rbp;
4331 IU_Register _rsp;
4332 IU_Register _rbx;
4333 IU_Register _rdx;
4334 IU_Register _rcx;
4335 IU_Register _rax;
4336
4337 void print() const {
4338 // computation registers
4339 printf("rax, = "); _rax.print(); printf("\n");
4340 printf("rbx, = "); _rbx.print(); printf("\n");
4341 printf("rcx = "); _rcx.print(); printf("\n");
4342 printf("rdx = "); _rdx.print(); printf("\n");
4343 printf("rdi = "); _rdi.print(); printf("\n");
4344 printf("rsi = "); _rsi.print(); printf("\n");
4345 printf("rbp, = "); _rbp.print(); printf("\n");
4346 printf("rsp = "); _rsp.print(); printf("\n");
4347 printf("\n");
4348 // control registers
4349 printf("flgs = "); _eflags.print(); printf("\n");
4350 }
4351 };
4352
4353
4354 class CPU_State {
4355 public:
4356 FPU_State _fpu_state;
4357 IU_State _iu_state;
4358
4359 void print() const {
4360 printf("--------------------------------------------------\n");
4361 _iu_state .print();
4362 printf("\n");
4363 _fpu_state.print();
4364 printf("--------------------------------------------------\n");
4365 }
4366
4367 };
4368
4369
4370 static void _print_CPU_state(CPU_State* state) {
4371 state->print();
4372 };
4373
4374
4375 void MacroAssembler::print_CPU_state() {
4376 push_CPU_state();
4377 push(rsp); // pass CPU state
4378 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _print_CPU_state)));
4379 addptr(rsp, wordSize); // discard argument
4380 pop_CPU_state();
4381 }
4382
4383
4384 #ifndef _LP64
4385 static bool _verify_FPU(int stack_depth, char* s, CPU_State* state) {
4386 static int counter = 0;
4387 FPU_State* fs = &state->_fpu_state;
4388 counter++;
4389 // For leaf calls, only verify that the top few elements remain empty.
4390 // We only need 1 empty at the top for C2 code.
4391 if( stack_depth < 0 ) {
4392 if( fs->tag_for_st(7) != 3 ) {
4393 printf("FPR7 not empty\n");
4394 state->print();
4395 assert(false, "error");
4396 return false;
4397 }
4398 return true; // All other stack states do not matter
4399 }
4400
4401 assert((fs->_control_word._value & 0xffff) == StubRoutines::x86::fpu_cntrl_wrd_std(),
4402 "bad FPU control word");
4403
4404 // compute stack depth
4405 int i = 0;
4406 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) < 3) i++;
4407 int d = i;
4408 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) == 3) i++;
4409 // verify findings
4410 if (i != FPU_State::number_of_registers) {
4411 // stack not contiguous
4412 printf("%s: stack not contiguous at ST%d\n", s, i);
4413 state->print();
4414 assert(false, "error");
4415 return false;
4416 }
4417 // check if computed stack depth corresponds to expected stack depth
4418 if (stack_depth < 0) {
4419 // expected stack depth is -stack_depth or less
4420 if (d > -stack_depth) {
4421 // too many elements on the stack
4422 printf("%s: <= %d stack elements expected but found %d\n", s, -stack_depth, d);
4423 state->print();
4424 assert(false, "error");
4425 return false;
4426 }
4427 } else {
4428 // expected stack depth is stack_depth
4429 if (d != stack_depth) {
4430 // wrong stack depth
4431 printf("%s: %d stack elements expected but found %d\n", s, stack_depth, d);
4432 state->print();
4433 assert(false, "error");
4434 return false;
4435 }
4436 }
4437 // everything is cool
4438 return true;
4439 }
4440
4441 void MacroAssembler::verify_FPU(int stack_depth, const char* s) {
4442 if (!VerifyFPU) return;
4443 push_CPU_state();
4444 push(rsp); // pass CPU state
4445 ExternalAddress msg((address) s);
4446 // pass message string s
4447 pushptr(msg.addr());
4448 push(stack_depth); // pass stack depth
4449 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _verify_FPU)));
4450 addptr(rsp, 3 * wordSize); // discard arguments
4451 // check for error
4452 { Label L;
4453 testl(rax, rax);
4454 jcc(Assembler::notZero, L);
4455 int3(); // break if error condition
4456 bind(L);
4457 }
4458 pop_CPU_state();
4459 }
4460 #endif // _LP64
4461
4462 void MacroAssembler::restore_cpu_control_state_after_jni() {
4463 // Either restore the MXCSR register after returning from the JNI Call
4464 // or verify that it wasn't changed (with -Xcheck:jni flag).
4465 if (VM_Version::supports_sse()) {
4466 if (RestoreMXCSROnJNICalls) {
4467 ldmxcsr(ExternalAddress(StubRoutines::x86::addr_mxcsr_std()));
4468 } else if (CheckJNICalls) {
4469 call(RuntimeAddress(StubRoutines::x86::verify_mxcsr_entry()));
4470 }
4471 }
4472 // Clear upper bits of YMM registers to avoid SSE <-> AVX transition penalty.
4473 vzeroupper();
4474 // Reset k1 to 0xffff.
4475
4476 #ifdef COMPILER2
4477 if (PostLoopMultiversioning && VM_Version::supports_evex()) {
4478 push(rcx);
4479 movl(rcx, 0xffff);
4480 kmovwl(k1, rcx);
4481 pop(rcx);
4482 }
4483 #endif // COMPILER2
4484
4485 #ifndef _LP64
4486 // Either restore the x87 floating pointer control word after returning
4487 // from the JNI call or verify that it wasn't changed.
4488 if (CheckJNICalls) {
4489 call(RuntimeAddress(StubRoutines::x86::verify_fpu_cntrl_wrd_entry()));
4490 }
4491 #endif // _LP64
4492 }
4493
4494 // ((OopHandle)result).resolve();
4495 void MacroAssembler::resolve_oop_handle(Register result, Register tmp) {
4496 assert_different_registers(result, tmp);
4497
4498 // Only 64 bit platforms support GCs that require a tmp register
4499 // Only IN_HEAP loads require a thread_tmp register
4500 // OopHandle::resolve is an indirection like jobject.
4501 access_load_at(T_OBJECT, IN_NATIVE,
4502 result, Address(result, 0), tmp, /*tmp_thread*/noreg);
4503 }
4504
4505 // ((WeakHandle)result).resolve();
4506 void MacroAssembler::resolve_weak_handle(Register rresult, Register rtmp) {
4507 assert_different_registers(rresult, rtmp);
4508 Label resolved;
4509
4510 // A null weak handle resolves to null.
4511 cmpptr(rresult, 0);
4512 jcc(Assembler::equal, resolved);
4513
4514 // Only 64 bit platforms support GCs that require a tmp register
4515 // Only IN_HEAP loads require a thread_tmp register
4516 // WeakHandle::resolve is an indirection like jweak.
4517 access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF,
4518 rresult, Address(rresult, 0), rtmp, /*tmp_thread*/noreg);
4519 bind(resolved);
4520 }
4521
4522 void MacroAssembler::load_mirror(Register mirror, Register method, Register tmp) {
4523 // get mirror
4524 const int mirror_offset = in_bytes(Klass::java_mirror_offset());
4525 load_method_holder(mirror, method);
4526 movptr(mirror, Address(mirror, mirror_offset));
4527 resolve_oop_handle(mirror, tmp);
4528 }
4529
4530 void MacroAssembler::load_method_holder_cld(Register rresult, Register rmethod) {
4531 load_method_holder(rresult, rmethod);
4532 movptr(rresult, Address(rresult, InstanceKlass::class_loader_data_offset()));
4533 }
4534
4535 void MacroAssembler::load_method_holder(Register holder, Register method) {
4536 movptr(holder, Address(method, Method::const_offset())); // ConstMethod*
4537 movptr(holder, Address(holder, ConstMethod::constants_offset())); // ConstantPool*
4538 movptr(holder, Address(holder, ConstantPool::pool_holder_offset_in_bytes())); // InstanceKlass*
4539 }
4540
4541 void MacroAssembler::load_klass(Register dst, Register src, Register tmp) {
4542 assert_different_registers(src, tmp);
4543 assert_different_registers(dst, tmp);
4544 #ifdef _LP64
4545 if (UseCompressedClassPointers) {
4546 movl(dst, Address(src, oopDesc::klass_offset_in_bytes()));
4547 decode_klass_not_null(dst, tmp);
4548 } else
4549 #endif
4550 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
4551 }
4552
4553 void MacroAssembler::store_klass(Register dst, Register src, Register tmp) {
4554 assert_different_registers(src, tmp);
4555 assert_different_registers(dst, tmp);
4556 #ifdef _LP64
4557 if (UseCompressedClassPointers) {
4558 encode_klass_not_null(src, tmp);
4559 movl(Address(dst, oopDesc::klass_offset_in_bytes()), src);
4560 } else
4561 #endif
4562 movptr(Address(dst, oopDesc::klass_offset_in_bytes()), src);
4563 }
4564
4565 void MacroAssembler::access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
4566 Register tmp1, Register thread_tmp) {
4567 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
4568 decorators = AccessInternal::decorator_fixup(decorators);
4569 bool as_raw = (decorators & AS_RAW) != 0;
4570 if (as_raw) {
4571 bs->BarrierSetAssembler::load_at(this, decorators, type, dst, src, tmp1, thread_tmp);
4572 } else {
4573 bs->load_at(this, decorators, type, dst, src, tmp1, thread_tmp);
4574 }
4575 }
4576
4577 void MacroAssembler::access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register src,
4578 Register tmp1, Register tmp2) {
4579 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
4580 decorators = AccessInternal::decorator_fixup(decorators);
4581 bool as_raw = (decorators & AS_RAW) != 0;
4582 if (as_raw) {
4583 bs->BarrierSetAssembler::store_at(this, decorators, type, dst, src, tmp1, tmp2);
4584 } else {
4585 bs->store_at(this, decorators, type, dst, src, tmp1, tmp2);
4586 }
4587 }
4588
4589 void MacroAssembler::load_heap_oop(Register dst, Address src, Register tmp1,
4590 Register thread_tmp, DecoratorSet decorators) {
4591 access_load_at(T_OBJECT, IN_HEAP | decorators, dst, src, tmp1, thread_tmp);
4592 }
4593
4594 // Doesn't do verfication, generates fixed size code
4595 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src, Register tmp1,
4596 Register thread_tmp, DecoratorSet decorators) {
4597 access_load_at(T_OBJECT, IN_HEAP | IS_NOT_NULL | decorators, dst, src, tmp1, thread_tmp);
4598 }
4599
4600 void MacroAssembler::store_heap_oop(Address dst, Register src, Register tmp1,
4601 Register tmp2, DecoratorSet decorators) {
4602 access_store_at(T_OBJECT, IN_HEAP | decorators, dst, src, tmp1, tmp2);
4603 }
4604
4605 // Used for storing NULLs.
4606 void MacroAssembler::store_heap_oop_null(Address dst) {
4607 access_store_at(T_OBJECT, IN_HEAP, dst, noreg, noreg, noreg);
4608 }
4609
4610 #ifdef _LP64
4611 void MacroAssembler::store_klass_gap(Register dst, Register src) {
4612 if (UseCompressedClassPointers) {
4613 // Store to klass gap in destination
4614 movl(Address(dst, oopDesc::klass_gap_offset_in_bytes()), src);
4615 }
4616 }
4617
4618 #ifdef ASSERT
4619 void MacroAssembler::verify_heapbase(const char* msg) {
4620 assert (UseCompressedOops, "should be compressed");
4621 assert (Universe::heap() != NULL, "java heap should be initialized");
4622 if (CheckCompressedOops) {
4623 Label ok;
4624 push(rscratch1); // cmpptr trashes rscratch1
4625 cmpptr(r12_heapbase, ExternalAddress((address)CompressedOops::ptrs_base_addr()));
4626 jcc(Assembler::equal, ok);
4627 STOP(msg);
4628 bind(ok);
4629 pop(rscratch1);
4630 }
4631 }
4632 #endif
4633
4634 // Algorithm must match oop.inline.hpp encode_heap_oop.
4635 void MacroAssembler::encode_heap_oop(Register r) {
4636 #ifdef ASSERT
4637 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?");
4638 #endif
4639 verify_oop_msg(r, "broken oop in encode_heap_oop");
4640 if (CompressedOops::base() == NULL) {
4641 if (CompressedOops::shift() != 0) {
4642 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
4643 shrq(r, LogMinObjAlignmentInBytes);
4644 }
4645 return;
4646 }
4647 testq(r, r);
4648 cmovq(Assembler::equal, r, r12_heapbase);
4649 subq(r, r12_heapbase);
4650 shrq(r, LogMinObjAlignmentInBytes);
4651 }
4652
4653 void MacroAssembler::encode_heap_oop_not_null(Register r) {
4654 #ifdef ASSERT
4655 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?");
4656 if (CheckCompressedOops) {
4657 Label ok;
4658 testq(r, r);
4659 jcc(Assembler::notEqual, ok);
4660 STOP("null oop passed to encode_heap_oop_not_null");
4661 bind(ok);
4662 }
4663 #endif
4664 verify_oop_msg(r, "broken oop in encode_heap_oop_not_null");
4665 if (CompressedOops::base() != NULL) {
4666 subq(r, r12_heapbase);
4667 }
4668 if (CompressedOops::shift() != 0) {
4669 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
4670 shrq(r, LogMinObjAlignmentInBytes);
4671 }
4672 }
4673
4674 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) {
4675 #ifdef ASSERT
4676 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?");
4677 if (CheckCompressedOops) {
4678 Label ok;
4679 testq(src, src);
4680 jcc(Assembler::notEqual, ok);
4681 STOP("null oop passed to encode_heap_oop_not_null2");
4682 bind(ok);
4683 }
4684 #endif
4685 verify_oop_msg(src, "broken oop in encode_heap_oop_not_null2");
4686 if (dst != src) {
4687 movq(dst, src);
4688 }
4689 if (CompressedOops::base() != NULL) {
4690 subq(dst, r12_heapbase);
4691 }
4692 if (CompressedOops::shift() != 0) {
4693 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
4694 shrq(dst, LogMinObjAlignmentInBytes);
4695 }
4696 }
4697
4698 void MacroAssembler::decode_heap_oop(Register r) {
4699 #ifdef ASSERT
4700 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?");
4701 #endif
4702 if (CompressedOops::base() == NULL) {
4703 if (CompressedOops::shift() != 0) {
4704 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
4705 shlq(r, LogMinObjAlignmentInBytes);
4706 }
4707 } else {
4708 Label done;
4709 shlq(r, LogMinObjAlignmentInBytes);
4710 jccb(Assembler::equal, done);
4711 addq(r, r12_heapbase);
4712 bind(done);
4713 }
4714 verify_oop_msg(r, "broken oop in decode_heap_oop");
4715 }
4716
4717 void MacroAssembler::decode_heap_oop_not_null(Register r) {
4718 // Note: it will change flags
4719 assert (UseCompressedOops, "should only be used for compressed headers");
4720 assert (Universe::heap() != NULL, "java heap should be initialized");
4721 // Cannot assert, unverified entry point counts instructions (see .ad file)
4722 // vtableStubs also counts instructions in pd_code_size_limit.
4723 // Also do not verify_oop as this is called by verify_oop.
4724 if (CompressedOops::shift() != 0) {
4725 assert(LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
4726 shlq(r, LogMinObjAlignmentInBytes);
4727 if (CompressedOops::base() != NULL) {
4728 addq(r, r12_heapbase);
4729 }
4730 } else {
4731 assert (CompressedOops::base() == NULL, "sanity");
4732 }
4733 }
4734
4735 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) {
4736 // Note: it will change flags
4737 assert (UseCompressedOops, "should only be used for compressed headers");
4738 assert (Universe::heap() != NULL, "java heap should be initialized");
4739 // Cannot assert, unverified entry point counts instructions (see .ad file)
4740 // vtableStubs also counts instructions in pd_code_size_limit.
4741 // Also do not verify_oop as this is called by verify_oop.
4742 if (CompressedOops::shift() != 0) {
4743 assert(LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
4744 if (LogMinObjAlignmentInBytes == Address::times_8) {
4745 leaq(dst, Address(r12_heapbase, src, Address::times_8, 0));
4746 } else {
4747 if (dst != src) {
4748 movq(dst, src);
4749 }
4750 shlq(dst, LogMinObjAlignmentInBytes);
4751 if (CompressedOops::base() != NULL) {
4752 addq(dst, r12_heapbase);
4753 }
4754 }
4755 } else {
4756 assert (CompressedOops::base() == NULL, "sanity");
4757 if (dst != src) {
4758 movq(dst, src);
4759 }
4760 }
4761 }
4762
4763 void MacroAssembler::encode_klass_not_null(Register r, Register tmp) {
4764 assert_different_registers(r, tmp);
4765 if (CompressedKlassPointers::base() != NULL) {
4766 mov64(tmp, (int64_t)CompressedKlassPointers::base());
4767 subq(r, tmp);
4768 }
4769 if (CompressedKlassPointers::shift() != 0) {
4770 assert (LogKlassAlignmentInBytes == CompressedKlassPointers::shift(), "decode alg wrong");
4771 shrq(r, LogKlassAlignmentInBytes);
4772 }
4773 }
4774
4775 void MacroAssembler::encode_and_move_klass_not_null(Register dst, Register src) {
4776 assert_different_registers(src, dst);
4777 if (CompressedKlassPointers::base() != NULL) {
4778 mov64(dst, -(int64_t)CompressedKlassPointers::base());
4779 addq(dst, src);
4780 } else {
4781 movptr(dst, src);
4782 }
4783 if (CompressedKlassPointers::shift() != 0) {
4784 assert (LogKlassAlignmentInBytes == CompressedKlassPointers::shift(), "decode alg wrong");
4785 shrq(dst, LogKlassAlignmentInBytes);
4786 }
4787 }
4788
4789 void MacroAssembler::decode_klass_not_null(Register r, Register tmp) {
4790 assert_different_registers(r, tmp);
4791 // Note: it will change flags
4792 assert(UseCompressedClassPointers, "should only be used for compressed headers");
4793 // Cannot assert, unverified entry point counts instructions (see .ad file)
4794 // vtableStubs also counts instructions in pd_code_size_limit.
4795 // Also do not verify_oop as this is called by verify_oop.
4796 if (CompressedKlassPointers::shift() != 0) {
4797 assert(LogKlassAlignmentInBytes == CompressedKlassPointers::shift(), "decode alg wrong");
4798 shlq(r, LogKlassAlignmentInBytes);
4799 }
4800 if (CompressedKlassPointers::base() != NULL) {
4801 mov64(tmp, (int64_t)CompressedKlassPointers::base());
4802 addq(r, tmp);
4803 }
4804 }
4805
4806 void MacroAssembler::decode_and_move_klass_not_null(Register dst, Register src) {
4807 assert_different_registers(src, dst);
4808 // Note: it will change flags
4809 assert (UseCompressedClassPointers, "should only be used for compressed headers");
4810 // Cannot assert, unverified entry point counts instructions (see .ad file)
4811 // vtableStubs also counts instructions in pd_code_size_limit.
4812 // Also do not verify_oop as this is called by verify_oop.
4813
4814 if (CompressedKlassPointers::base() == NULL &&
4815 CompressedKlassPointers::shift() == 0) {
4816 // The best case scenario is that there is no base or shift. Then it is already
4817 // a pointer that needs nothing but a register rename.
4818 movl(dst, src);
4819 } else {
4820 if (CompressedKlassPointers::base() != NULL) {
4821 mov64(dst, (int64_t)CompressedKlassPointers::base());
4822 } else {
4823 xorq(dst, dst);
4824 }
4825 if (CompressedKlassPointers::shift() != 0) {
4826 assert(LogKlassAlignmentInBytes == CompressedKlassPointers::shift(), "decode alg wrong");
4827 assert(LogKlassAlignmentInBytes == Address::times_8, "klass not aligned on 64bits?");
4828 leaq(dst, Address(dst, src, Address::times_8, 0));
4829 } else {
4830 addq(dst, src);
4831 }
4832 }
4833 }
4834
4835 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) {
4836 assert (UseCompressedOops, "should only be used for compressed headers");
4837 assert (Universe::heap() != NULL, "java heap should be initialized");
4838 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
4839 int oop_index = oop_recorder()->find_index(obj);
4840 RelocationHolder rspec = oop_Relocation::spec(oop_index);
4841 mov_narrow_oop(dst, oop_index, rspec);
4842 }
4843
4844 void MacroAssembler::set_narrow_oop(Address dst, jobject obj) {
4845 assert (UseCompressedOops, "should only be used for compressed headers");
4846 assert (Universe::heap() != NULL, "java heap should be initialized");
4847 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
4848 int oop_index = oop_recorder()->find_index(obj);
4849 RelocationHolder rspec = oop_Relocation::spec(oop_index);
4850 mov_narrow_oop(dst, oop_index, rspec);
4851 }
4852
4853 void MacroAssembler::set_narrow_klass(Register dst, Klass* k) {
4854 assert (UseCompressedClassPointers, "should only be used for compressed headers");
4855 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
4856 int klass_index = oop_recorder()->find_index(k);
4857 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
4858 mov_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
4859 }
4860
4861 void MacroAssembler::set_narrow_klass(Address dst, Klass* k) {
4862 assert (UseCompressedClassPointers, "should only be used for compressed headers");
4863 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
4864 int klass_index = oop_recorder()->find_index(k);
4865 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
4866 mov_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
4867 }
4868
4869 void MacroAssembler::cmp_narrow_oop(Register dst, jobject obj) {
4870 assert (UseCompressedOops, "should only be used for compressed headers");
4871 assert (Universe::heap() != NULL, "java heap should be initialized");
4872 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
4873 int oop_index = oop_recorder()->find_index(obj);
4874 RelocationHolder rspec = oop_Relocation::spec(oop_index);
4875 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
4876 }
4877
4878 void MacroAssembler::cmp_narrow_oop(Address dst, jobject obj) {
4879 assert (UseCompressedOops, "should only be used for compressed headers");
4880 assert (Universe::heap() != NULL, "java heap should be initialized");
4881 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
4882 int oop_index = oop_recorder()->find_index(obj);
4883 RelocationHolder rspec = oop_Relocation::spec(oop_index);
4884 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
4885 }
4886
4887 void MacroAssembler::cmp_narrow_klass(Register dst, Klass* k) {
4888 assert (UseCompressedClassPointers, "should only be used for compressed headers");
4889 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
4890 int klass_index = oop_recorder()->find_index(k);
4891 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
4892 Assembler::cmp_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
4893 }
4894
4895 void MacroAssembler::cmp_narrow_klass(Address dst, Klass* k) {
4896 assert (UseCompressedClassPointers, "should only be used for compressed headers");
4897 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
4898 int klass_index = oop_recorder()->find_index(k);
4899 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
4900 Assembler::cmp_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
4901 }
4902
4903 void MacroAssembler::reinit_heapbase() {
4904 if (UseCompressedOops) {
4905 if (Universe::heap() != NULL) {
4906 if (CompressedOops::base() == NULL) {
4907 MacroAssembler::xorptr(r12_heapbase, r12_heapbase);
4908 } else {
4909 mov64(r12_heapbase, (int64_t)CompressedOops::ptrs_base());
4910 }
4911 } else {
4912 movptr(r12_heapbase, ExternalAddress((address)CompressedOops::ptrs_base_addr()));
4913 }
4914 }
4915 }
4916
4917 #endif // _LP64
4918
4919 // C2 compiled method's prolog code.
4920 void MacroAssembler::verified_entry(int framesize, int stack_bang_size, bool fp_mode_24b, bool is_stub) {
4921
4922 // WARNING: Initial instruction MUST be 5 bytes or longer so that
4923 // NativeJump::patch_verified_entry will be able to patch out the entry
4924 // code safely. The push to verify stack depth is ok at 5 bytes,
4925 // the frame allocation can be either 3 or 6 bytes. So if we don't do
4926 // stack bang then we must use the 6 byte frame allocation even if
4927 // we have no frame. :-(
4928 assert(stack_bang_size >= framesize || stack_bang_size <= 0, "stack bang size incorrect");
4929
4930 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
4931 // Remove word for return addr
4932 framesize -= wordSize;
4933 stack_bang_size -= wordSize;
4934
4935 // Calls to C2R adapters often do not accept exceptional returns.
4936 // We require that their callers must bang for them. But be careful, because
4937 // some VM calls (such as call site linkage) can use several kilobytes of
4938 // stack. But the stack safety zone should account for that.
4939 // See bugs 4446381, 4468289, 4497237.
4940 if (stack_bang_size > 0) {
4941 generate_stack_overflow_check(stack_bang_size);
4942
4943 // We always push rbp, so that on return to interpreter rbp, will be
4944 // restored correctly and we can correct the stack.
4945 push(rbp);
4946 // Save caller's stack pointer into RBP if the frame pointer is preserved.
4947 if (PreserveFramePointer) {
4948 mov(rbp, rsp);
4949 }
4950 // Remove word for ebp
4951 framesize -= wordSize;
4952
4953 // Create frame
4954 if (framesize) {
4955 subptr(rsp, framesize);
4956 }
4957 } else {
4958 // Create frame (force generation of a 4 byte immediate value)
4959 subptr_imm32(rsp, framesize);
4960
4961 // Save RBP register now.
4962 framesize -= wordSize;
4963 movptr(Address(rsp, framesize), rbp);
4964 // Save caller's stack pointer into RBP if the frame pointer is preserved.
4965 if (PreserveFramePointer) {
4966 movptr(rbp, rsp);
4967 if (framesize > 0) {
4968 addptr(rbp, framesize);
4969 }
4970 }
4971 }
4972
4973 if (VerifyStackAtCalls) { // Majik cookie to verify stack depth
4974 framesize -= wordSize;
4975 movptr(Address(rsp, framesize), (int32_t)0xbadb100d);
4976 }
4977
4978 #ifndef _LP64
4979 // If method sets FPU control word do it now
4980 if (fp_mode_24b) {
4981 fldcw(ExternalAddress(StubRoutines::x86::addr_fpu_cntrl_wrd_24()));
4982 }
4983 if (UseSSE >= 2 && VerifyFPU) {
4984 verify_FPU(0, "FPU stack must be clean on entry");
4985 }
4986 #endif
4987
4988 #ifdef ASSERT
4989 if (VerifyStackAtCalls) {
4990 Label L;
4991 push(rax);
4992 mov(rax, rsp);
4993 andptr(rax, StackAlignmentInBytes-1);
4994 cmpptr(rax, StackAlignmentInBytes-wordSize);
4995 pop(rax);
4996 jcc(Assembler::equal, L);
4997 STOP("Stack is not properly aligned!");
4998 bind(L);
4999 }
5000 #endif
5001
5002 if (!is_stub) {
5003 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
5004 bs->nmethod_entry_barrier(this);
5005 }
5006 }
5007
5008 #if COMPILER2_OR_JVMCI
5009
5010 // clear memory of size 'cnt' qwords, starting at 'base' using XMM/YMM/ZMM registers
5011 void MacroAssembler::xmm_clear_mem(Register base, Register cnt, Register rtmp, XMMRegister xtmp, KRegister mask) {
5012 // cnt - number of qwords (8-byte words).
5013 // base - start address, qword aligned.
5014 Label L_zero_64_bytes, L_loop, L_sloop, L_tail, L_end;
5015 bool use64byteVector = MaxVectorSize == 64 && AVX3Threshold == 0;
5016 if (use64byteVector) {
5017 vpxor(xtmp, xtmp, xtmp, AVX_512bit);
5018 } else if (MaxVectorSize >= 32) {
5019 vpxor(xtmp, xtmp, xtmp, AVX_256bit);
5020 } else {
5021 pxor(xtmp, xtmp);
5022 }
5023 jmp(L_zero_64_bytes);
5024
5025 BIND(L_loop);
5026 if (MaxVectorSize >= 32) {
5027 fill64(base, 0, xtmp, use64byteVector);
5028 } else {
5029 movdqu(Address(base, 0), xtmp);
5030 movdqu(Address(base, 16), xtmp);
5031 movdqu(Address(base, 32), xtmp);
5032 movdqu(Address(base, 48), xtmp);
5033 }
5034 addptr(base, 64);
5035
5036 BIND(L_zero_64_bytes);
5037 subptr(cnt, 8);
5038 jccb(Assembler::greaterEqual, L_loop);
5039
5040 // Copy trailing 64 bytes
5041 if (use64byteVector) {
5042 addptr(cnt, 8);
5043 jccb(Assembler::equal, L_end);
5044 fill64_masked(3, base, 0, xtmp, mask, cnt, rtmp, true);
5045 jmp(L_end);
5046 } else {
5047 addptr(cnt, 4);
5048 jccb(Assembler::less, L_tail);
5049 if (MaxVectorSize >= 32) {
5050 vmovdqu(Address(base, 0), xtmp);
5051 } else {
5052 movdqu(Address(base, 0), xtmp);
5053 movdqu(Address(base, 16), xtmp);
5054 }
5055 }
5056 addptr(base, 32);
5057 subptr(cnt, 4);
5058
5059 BIND(L_tail);
5060 addptr(cnt, 4);
5061 jccb(Assembler::lessEqual, L_end);
5062 if (UseAVX > 2 && MaxVectorSize >= 32 && VM_Version::supports_avx512vl()) {
5063 fill32_masked(3, base, 0, xtmp, mask, cnt, rtmp);
5064 } else {
5065 decrement(cnt);
5066
5067 BIND(L_sloop);
5068 movq(Address(base, 0), xtmp);
5069 addptr(base, 8);
5070 decrement(cnt);
5071 jccb(Assembler::greaterEqual, L_sloop);
5072 }
5073 BIND(L_end);
5074 }
5075
5076 // Clearing constant sized memory using YMM/ZMM registers.
5077 void MacroAssembler::clear_mem(Register base, int cnt, Register rtmp, XMMRegister xtmp, KRegister mask) {
5078 assert(UseAVX > 2 && VM_Version::supports_avx512vlbw(), "");
5079 bool use64byteVector = MaxVectorSize > 32 && AVX3Threshold == 0;
5080
5081 int vector64_count = (cnt & (~0x7)) >> 3;
5082 cnt = cnt & 0x7;
5083
5084 // 64 byte initialization loop.
5085 vpxor(xtmp, xtmp, xtmp, use64byteVector ? AVX_512bit : AVX_256bit);
5086 for (int i = 0; i < vector64_count; i++) {
5087 fill64(base, i * 64, xtmp, use64byteVector);
5088 }
5089
5090 // Clear remaining 64 byte tail.
5091 int disp = vector64_count * 64;
5092 if (cnt) {
5093 switch (cnt) {
5094 case 1:
5095 movq(Address(base, disp), xtmp);
5096 break;
5097 case 2:
5098 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, Assembler::AVX_128bit);
5099 break;
5100 case 3:
5101 movl(rtmp, 0x7);
5102 kmovwl(mask, rtmp);
5103 evmovdqu(T_LONG, mask, Address(base, disp), xtmp, Assembler::AVX_256bit);
5104 break;
5105 case 4:
5106 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, Assembler::AVX_256bit);
5107 break;
5108 case 5:
5109 if (use64byteVector) {
5110 movl(rtmp, 0x1F);
5111 kmovwl(mask, rtmp);
5112 evmovdqu(T_LONG, mask, Address(base, disp), xtmp, Assembler::AVX_512bit);
5113 } else {
5114 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, Assembler::AVX_256bit);
5115 movq(Address(base, disp + 32), xtmp);
5116 }
5117 break;
5118 case 6:
5119 if (use64byteVector) {
5120 movl(rtmp, 0x3F);
5121 kmovwl(mask, rtmp);
5122 evmovdqu(T_LONG, mask, Address(base, disp), xtmp, Assembler::AVX_512bit);
5123 } else {
5124 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, Assembler::AVX_256bit);
5125 evmovdqu(T_LONG, k0, Address(base, disp + 32), xtmp, Assembler::AVX_128bit);
5126 }
5127 break;
5128 case 7:
5129 if (use64byteVector) {
5130 movl(rtmp, 0x7F);
5131 kmovwl(mask, rtmp);
5132 evmovdqu(T_LONG, mask, Address(base, disp), xtmp, Assembler::AVX_512bit);
5133 } else {
5134 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, Assembler::AVX_256bit);
5135 movl(rtmp, 0x7);
5136 kmovwl(mask, rtmp);
5137 evmovdqu(T_LONG, mask, Address(base, disp + 32), xtmp, Assembler::AVX_256bit);
5138 }
5139 break;
5140 default:
5141 fatal("Unexpected length : %d\n",cnt);
5142 break;
5143 }
5144 }
5145 }
5146
5147 void MacroAssembler::clear_mem(Register base, Register cnt, Register tmp, XMMRegister xtmp,
5148 bool is_large, KRegister mask) {
5149 // cnt - number of qwords (8-byte words).
5150 // base - start address, qword aligned.
5151 // is_large - if optimizers know cnt is larger than InitArrayShortSize
5152 assert(base==rdi, "base register must be edi for rep stos");
5153 assert(tmp==rax, "tmp register must be eax for rep stos");
5154 assert(cnt==rcx, "cnt register must be ecx for rep stos");
5155 assert(InitArrayShortSize % BytesPerLong == 0,
5156 "InitArrayShortSize should be the multiple of BytesPerLong");
5157
5158 Label DONE;
5159 if (!is_large || !UseXMMForObjInit) {
5160 xorptr(tmp, tmp);
5161 }
5162
5163 if (!is_large) {
5164 Label LOOP, LONG;
5165 cmpptr(cnt, InitArrayShortSize/BytesPerLong);
5166 jccb(Assembler::greater, LONG);
5167
5168 NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM
5169
5170 decrement(cnt);
5171 jccb(Assembler::negative, DONE); // Zero length
5172
5173 // Use individual pointer-sized stores for small counts:
5174 BIND(LOOP);
5175 movptr(Address(base, cnt, Address::times_ptr), tmp);
5176 decrement(cnt);
5177 jccb(Assembler::greaterEqual, LOOP);
5178 jmpb(DONE);
5179
5180 BIND(LONG);
5181 }
5182
5183 // Use longer rep-prefixed ops for non-small counts:
5184 if (UseFastStosb) {
5185 shlptr(cnt, 3); // convert to number of bytes
5186 rep_stosb();
5187 } else if (UseXMMForObjInit) {
5188 xmm_clear_mem(base, cnt, tmp, xtmp, mask);
5189 } else {
5190 NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM
5191 rep_stos();
5192 }
5193
5194 BIND(DONE);
5195 }
5196
5197 #endif //COMPILER2_OR_JVMCI
5198
5199
5200 void MacroAssembler::generate_fill(BasicType t, bool aligned,
5201 Register to, Register value, Register count,
5202 Register rtmp, XMMRegister xtmp) {
5203 ShortBranchVerifier sbv(this);
5204 assert_different_registers(to, value, count, rtmp);
5205 Label L_exit;
5206 Label L_fill_2_bytes, L_fill_4_bytes;
5207
5208 #if defined(COMPILER2) && defined(_LP64)
5209 if(MaxVectorSize >=32 &&
5210 VM_Version::supports_avx512vlbw() &&
5211 VM_Version::supports_bmi2()) {
5212 generate_fill_avx3(t, to, value, count, rtmp, xtmp);
5213 return;
5214 }
5215 #endif
5216
5217 int shift = -1;
5218 switch (t) {
5219 case T_BYTE:
5220 shift = 2;
5221 break;
5222 case T_SHORT:
5223 shift = 1;
5224 break;
5225 case T_INT:
5226 shift = 0;
5227 break;
5228 default: ShouldNotReachHere();
5229 }
5230
5231 if (t == T_BYTE) {
5232 andl(value, 0xff);
5233 movl(rtmp, value);
5234 shll(rtmp, 8);
5235 orl(value, rtmp);
5236 }
5237 if (t == T_SHORT) {
5238 andl(value, 0xffff);
5239 }
5240 if (t == T_BYTE || t == T_SHORT) {
5241 movl(rtmp, value);
5242 shll(rtmp, 16);
5243 orl(value, rtmp);
5244 }
5245
5246 cmpl(count, 2<<shift); // Short arrays (< 8 bytes) fill by element
5247 jcc(Assembler::below, L_fill_4_bytes); // use unsigned cmp
5248 if (!UseUnalignedLoadStores && !aligned && (t == T_BYTE || t == T_SHORT)) {
5249 Label L_skip_align2;
5250 // align source address at 4 bytes address boundary
5251 if (t == T_BYTE) {
5252 Label L_skip_align1;
5253 // One byte misalignment happens only for byte arrays
5254 testptr(to, 1);
5255 jccb(Assembler::zero, L_skip_align1);
5256 movb(Address(to, 0), value);
5257 increment(to);
5258 decrement(count);
5259 BIND(L_skip_align1);
5260 }
5261 // Two bytes misalignment happens only for byte and short (char) arrays
5262 testptr(to, 2);
5263 jccb(Assembler::zero, L_skip_align2);
5264 movw(Address(to, 0), value);
5265 addptr(to, 2);
5266 subl(count, 1<<(shift-1));
5267 BIND(L_skip_align2);
5268 }
5269 if (UseSSE < 2) {
5270 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
5271 // Fill 32-byte chunks
5272 subl(count, 8 << shift);
5273 jcc(Assembler::less, L_check_fill_8_bytes);
5274 align(16);
5275
5276 BIND(L_fill_32_bytes_loop);
5277
5278 for (int i = 0; i < 32; i += 4) {
5279 movl(Address(to, i), value);
5280 }
5281
5282 addptr(to, 32);
5283 subl(count, 8 << shift);
5284 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
5285 BIND(L_check_fill_8_bytes);
5286 addl(count, 8 << shift);
5287 jccb(Assembler::zero, L_exit);
5288 jmpb(L_fill_8_bytes);
5289
5290 //
5291 // length is too short, just fill qwords
5292 //
5293 BIND(L_fill_8_bytes_loop);
5294 movl(Address(to, 0), value);
5295 movl(Address(to, 4), value);
5296 addptr(to, 8);
5297 BIND(L_fill_8_bytes);
5298 subl(count, 1 << (shift + 1));
5299 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
5300 // fall through to fill 4 bytes
5301 } else {
5302 Label L_fill_32_bytes;
5303 if (!UseUnalignedLoadStores) {
5304 // align to 8 bytes, we know we are 4 byte aligned to start
5305 testptr(to, 4);
5306 jccb(Assembler::zero, L_fill_32_bytes);
5307 movl(Address(to, 0), value);
5308 addptr(to, 4);
5309 subl(count, 1<<shift);
5310 }
5311 BIND(L_fill_32_bytes);
5312 {
5313 assert( UseSSE >= 2, "supported cpu only" );
5314 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
5315 movdl(xtmp, value);
5316 if (UseAVX >= 2 && UseUnalignedLoadStores) {
5317 Label L_check_fill_32_bytes;
5318 if (UseAVX > 2) {
5319 // Fill 64-byte chunks
5320 Label L_fill_64_bytes_loop_avx3, L_check_fill_64_bytes_avx2;
5321
5322 // If number of bytes to fill < AVX3Threshold, perform fill using AVX2
5323 cmpl(count, AVX3Threshold);
5324 jccb(Assembler::below, L_check_fill_64_bytes_avx2);
5325
5326 vpbroadcastd(xtmp, xtmp, Assembler::AVX_512bit);
5327
5328 subl(count, 16 << shift);
5329 jccb(Assembler::less, L_check_fill_32_bytes);
5330 align(16);
5331
5332 BIND(L_fill_64_bytes_loop_avx3);
5333 evmovdqul(Address(to, 0), xtmp, Assembler::AVX_512bit);
5334 addptr(to, 64);
5335 subl(count, 16 << shift);
5336 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop_avx3);
5337 jmpb(L_check_fill_32_bytes);
5338
5339 BIND(L_check_fill_64_bytes_avx2);
5340 }
5341 // Fill 64-byte chunks
5342 Label L_fill_64_bytes_loop;
5343 vpbroadcastd(xtmp, xtmp, Assembler::AVX_256bit);
5344
5345 subl(count, 16 << shift);
5346 jcc(Assembler::less, L_check_fill_32_bytes);
5347 align(16);
5348
5349 BIND(L_fill_64_bytes_loop);
5350 vmovdqu(Address(to, 0), xtmp);
5351 vmovdqu(Address(to, 32), xtmp);
5352 addptr(to, 64);
5353 subl(count, 16 << shift);
5354 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop);
5355
5356 BIND(L_check_fill_32_bytes);
5357 addl(count, 8 << shift);
5358 jccb(Assembler::less, L_check_fill_8_bytes);
5359 vmovdqu(Address(to, 0), xtmp);
5360 addptr(to, 32);
5361 subl(count, 8 << shift);
5362
5363 BIND(L_check_fill_8_bytes);
5364 // clean upper bits of YMM registers
5365 movdl(xtmp, value);
5366 pshufd(xtmp, xtmp, 0);
5367 } else {
5368 // Fill 32-byte chunks
5369 pshufd(xtmp, xtmp, 0);
5370
5371 subl(count, 8 << shift);
5372 jcc(Assembler::less, L_check_fill_8_bytes);
5373 align(16);
5374
5375 BIND(L_fill_32_bytes_loop);
5376
5377 if (UseUnalignedLoadStores) {
5378 movdqu(Address(to, 0), xtmp);
5379 movdqu(Address(to, 16), xtmp);
5380 } else {
5381 movq(Address(to, 0), xtmp);
5382 movq(Address(to, 8), xtmp);
5383 movq(Address(to, 16), xtmp);
5384 movq(Address(to, 24), xtmp);
5385 }
5386
5387 addptr(to, 32);
5388 subl(count, 8 << shift);
5389 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
5390
5391 BIND(L_check_fill_8_bytes);
5392 }
5393 addl(count, 8 << shift);
5394 jccb(Assembler::zero, L_exit);
5395 jmpb(L_fill_8_bytes);
5396
5397 //
5398 // length is too short, just fill qwords
5399 //
5400 BIND(L_fill_8_bytes_loop);
5401 movq(Address(to, 0), xtmp);
5402 addptr(to, 8);
5403 BIND(L_fill_8_bytes);
5404 subl(count, 1 << (shift + 1));
5405 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
5406 }
5407 }
5408 // fill trailing 4 bytes
5409 BIND(L_fill_4_bytes);
5410 testl(count, 1<<shift);
5411 jccb(Assembler::zero, L_fill_2_bytes);
5412 movl(Address(to, 0), value);
5413 if (t == T_BYTE || t == T_SHORT) {
5414 Label L_fill_byte;
5415 addptr(to, 4);
5416 BIND(L_fill_2_bytes);
5417 // fill trailing 2 bytes
5418 testl(count, 1<<(shift-1));
5419 jccb(Assembler::zero, L_fill_byte);
5420 movw(Address(to, 0), value);
5421 if (t == T_BYTE) {
5422 addptr(to, 2);
5423 BIND(L_fill_byte);
5424 // fill trailing byte
5425 testl(count, 1);
5426 jccb(Assembler::zero, L_exit);
5427 movb(Address(to, 0), value);
5428 } else {
5429 BIND(L_fill_byte);
5430 }
5431 } else {
5432 BIND(L_fill_2_bytes);
5433 }
5434 BIND(L_exit);
5435 }
5436
5437 void MacroAssembler::evpbroadcast(BasicType type, XMMRegister dst, Register src, int vector_len) {
5438 switch(type) {
5439 case T_BYTE:
5440 case T_BOOLEAN:
5441 evpbroadcastb(dst, src, vector_len);
5442 break;
5443 case T_SHORT:
5444 case T_CHAR:
5445 evpbroadcastw(dst, src, vector_len);
5446 break;
5447 case T_INT:
5448 case T_FLOAT:
5449 evpbroadcastd(dst, src, vector_len);
5450 break;
5451 case T_LONG:
5452 case T_DOUBLE:
5453 evpbroadcastq(dst, src, vector_len);
5454 break;
5455 default:
5456 fatal("Unhandled type : %s", type2name(type));
5457 break;
5458 }
5459 }
5460
5461 // encode char[] to byte[] in ISO_8859_1 or ASCII
5462 //@IntrinsicCandidate
5463 //private static int implEncodeISOArray(byte[] sa, int sp,
5464 //byte[] da, int dp, int len) {
5465 // int i = 0;
5466 // for (; i < len; i++) {
5467 // char c = StringUTF16.getChar(sa, sp++);
5468 // if (c > '\u00FF')
5469 // break;
5470 // da[dp++] = (byte)c;
5471 // }
5472 // return i;
5473 //}
5474 //
5475 //@IntrinsicCandidate
5476 //private static int implEncodeAsciiArray(char[] sa, int sp,
5477 // byte[] da, int dp, int len) {
5478 // int i = 0;
5479 // for (; i < len; i++) {
5480 // char c = sa[sp++];
5481 // if (c >= '\u0080')
5482 // break;
5483 // da[dp++] = (byte)c;
5484 // }
5485 // return i;
5486 //}
5487 void MacroAssembler::encode_iso_array(Register src, Register dst, Register len,
5488 XMMRegister tmp1Reg, XMMRegister tmp2Reg,
5489 XMMRegister tmp3Reg, XMMRegister tmp4Reg,
5490 Register tmp5, Register result, bool ascii) {
5491
5492 // rsi: src
5493 // rdi: dst
5494 // rdx: len
5495 // rcx: tmp5
5496 // rax: result
5497 ShortBranchVerifier sbv(this);
5498 assert_different_registers(src, dst, len, tmp5, result);
5499 Label L_done, L_copy_1_char, L_copy_1_char_exit;
5500
5501 int mask = ascii ? 0xff80ff80 : 0xff00ff00;
5502 int short_mask = ascii ? 0xff80 : 0xff00;
5503
5504 // set result
5505 xorl(result, result);
5506 // check for zero length
5507 testl(len, len);
5508 jcc(Assembler::zero, L_done);
5509
5510 movl(result, len);
5511
5512 // Setup pointers
5513 lea(src, Address(src, len, Address::times_2)); // char[]
5514 lea(dst, Address(dst, len, Address::times_1)); // byte[]
5515 negptr(len);
5516
5517 if (UseSSE42Intrinsics || UseAVX >= 2) {
5518 Label L_copy_8_chars, L_copy_8_chars_exit;
5519 Label L_chars_16_check, L_copy_16_chars, L_copy_16_chars_exit;
5520
5521 if (UseAVX >= 2) {
5522 Label L_chars_32_check, L_copy_32_chars, L_copy_32_chars_exit;
5523 movl(tmp5, mask); // create mask to test for Unicode or non-ASCII chars in vector
5524 movdl(tmp1Reg, tmp5);
5525 vpbroadcastd(tmp1Reg, tmp1Reg, Assembler::AVX_256bit);
5526 jmp(L_chars_32_check);
5527
5528 bind(L_copy_32_chars);
5529 vmovdqu(tmp3Reg, Address(src, len, Address::times_2, -64));
5530 vmovdqu(tmp4Reg, Address(src, len, Address::times_2, -32));
5531 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
5532 vptest(tmp2Reg, tmp1Reg); // check for Unicode or non-ASCII chars in vector
5533 jccb(Assembler::notZero, L_copy_32_chars_exit);
5534 vpackuswb(tmp3Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
5535 vpermq(tmp4Reg, tmp3Reg, 0xD8, /* vector_len */ 1);
5536 vmovdqu(Address(dst, len, Address::times_1, -32), tmp4Reg);
5537
5538 bind(L_chars_32_check);
5539 addptr(len, 32);
5540 jcc(Assembler::lessEqual, L_copy_32_chars);
5541
5542 bind(L_copy_32_chars_exit);
5543 subptr(len, 16);
5544 jccb(Assembler::greater, L_copy_16_chars_exit);
5545
5546 } else if (UseSSE42Intrinsics) {
5547 movl(tmp5, mask); // create mask to test for Unicode or non-ASCII chars in vector
5548 movdl(tmp1Reg, tmp5);
5549 pshufd(tmp1Reg, tmp1Reg, 0);
5550 jmpb(L_chars_16_check);
5551 }
5552
5553 bind(L_copy_16_chars);
5554 if (UseAVX >= 2) {
5555 vmovdqu(tmp2Reg, Address(src, len, Address::times_2, -32));
5556 vptest(tmp2Reg, tmp1Reg);
5557 jcc(Assembler::notZero, L_copy_16_chars_exit);
5558 vpackuswb(tmp2Reg, tmp2Reg, tmp1Reg, /* vector_len */ 1);
5559 vpermq(tmp3Reg, tmp2Reg, 0xD8, /* vector_len */ 1);
5560 } else {
5561 if (UseAVX > 0) {
5562 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
5563 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
5564 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 0);
5565 } else {
5566 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
5567 por(tmp2Reg, tmp3Reg);
5568 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
5569 por(tmp2Reg, tmp4Reg);
5570 }
5571 ptest(tmp2Reg, tmp1Reg); // check for Unicode or non-ASCII chars in vector
5572 jccb(Assembler::notZero, L_copy_16_chars_exit);
5573 packuswb(tmp3Reg, tmp4Reg);
5574 }
5575 movdqu(Address(dst, len, Address::times_1, -16), tmp3Reg);
5576
5577 bind(L_chars_16_check);
5578 addptr(len, 16);
5579 jcc(Assembler::lessEqual, L_copy_16_chars);
5580
5581 bind(L_copy_16_chars_exit);
5582 if (UseAVX >= 2) {
5583 // clean upper bits of YMM registers
5584 vpxor(tmp2Reg, tmp2Reg);
5585 vpxor(tmp3Reg, tmp3Reg);
5586 vpxor(tmp4Reg, tmp4Reg);
5587 movdl(tmp1Reg, tmp5);
5588 pshufd(tmp1Reg, tmp1Reg, 0);
5589 }
5590 subptr(len, 8);
5591 jccb(Assembler::greater, L_copy_8_chars_exit);
5592
5593 bind(L_copy_8_chars);
5594 movdqu(tmp3Reg, Address(src, len, Address::times_2, -16));
5595 ptest(tmp3Reg, tmp1Reg);
5596 jccb(Assembler::notZero, L_copy_8_chars_exit);
5597 packuswb(tmp3Reg, tmp1Reg);
5598 movq(Address(dst, len, Address::times_1, -8), tmp3Reg);
5599 addptr(len, 8);
5600 jccb(Assembler::lessEqual, L_copy_8_chars);
5601
5602 bind(L_copy_8_chars_exit);
5603 subptr(len, 8);
5604 jccb(Assembler::zero, L_done);
5605 }
5606
5607 bind(L_copy_1_char);
5608 load_unsigned_short(tmp5, Address(src, len, Address::times_2, 0));
5609 testl(tmp5, short_mask); // check if Unicode or non-ASCII char
5610 jccb(Assembler::notZero, L_copy_1_char_exit);
5611 movb(Address(dst, len, Address::times_1, 0), tmp5);
5612 addptr(len, 1);
5613 jccb(Assembler::less, L_copy_1_char);
5614
5615 bind(L_copy_1_char_exit);
5616 addptr(result, len); // len is negative count of not processed elements
5617
5618 bind(L_done);
5619 }
5620
5621 #ifdef _LP64
5622 /**
5623 * Helper for multiply_to_len().
5624 */
5625 void MacroAssembler::add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
5626 addq(dest_lo, src1);
5627 adcq(dest_hi, 0);
5628 addq(dest_lo, src2);
5629 adcq(dest_hi, 0);
5630 }
5631
5632 /**
5633 * Multiply 64 bit by 64 bit first loop.
5634 */
5635 void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
5636 Register y, Register y_idx, Register z,
5637 Register carry, Register product,
5638 Register idx, Register kdx) {
5639 //
5640 // jlong carry, x[], y[], z[];
5641 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
5642 // huge_128 product = y[idx] * x[xstart] + carry;
5643 // z[kdx] = (jlong)product;
5644 // carry = (jlong)(product >>> 64);
5645 // }
5646 // z[xstart] = carry;
5647 //
5648
5649 Label L_first_loop, L_first_loop_exit;
5650 Label L_one_x, L_one_y, L_multiply;
5651
5652 decrementl(xstart);
5653 jcc(Assembler::negative, L_one_x);
5654
5655 movq(x_xstart, Address(x, xstart, Address::times_4, 0));
5656 rorq(x_xstart, 32); // convert big-endian to little-endian
5657
5658 bind(L_first_loop);
5659 decrementl(idx);
5660 jcc(Assembler::negative, L_first_loop_exit);
5661 decrementl(idx);
5662 jcc(Assembler::negative, L_one_y);
5663 movq(y_idx, Address(y, idx, Address::times_4, 0));
5664 rorq(y_idx, 32); // convert big-endian to little-endian
5665 bind(L_multiply);
5666 movq(product, x_xstart);
5667 mulq(y_idx); // product(rax) * y_idx -> rdx:rax
5668 addq(product, carry);
5669 adcq(rdx, 0);
5670 subl(kdx, 2);
5671 movl(Address(z, kdx, Address::times_4, 4), product);
5672 shrq(product, 32);
5673 movl(Address(z, kdx, Address::times_4, 0), product);
5674 movq(carry, rdx);
5675 jmp(L_first_loop);
5676
5677 bind(L_one_y);
5678 movl(y_idx, Address(y, 0));
5679 jmp(L_multiply);
5680
5681 bind(L_one_x);
5682 movl(x_xstart, Address(x, 0));
5683 jmp(L_first_loop);
5684
5685 bind(L_first_loop_exit);
5686 }
5687
5688 /**
5689 * Multiply 64 bit by 64 bit and add 128 bit.
5690 */
5691 void MacroAssembler::multiply_add_128_x_128(Register x_xstart, Register y, Register z,
5692 Register yz_idx, Register idx,
5693 Register carry, Register product, int offset) {
5694 // huge_128 product = (y[idx] * x_xstart) + z[kdx] + carry;
5695 // z[kdx] = (jlong)product;
5696
5697 movq(yz_idx, Address(y, idx, Address::times_4, offset));
5698 rorq(yz_idx, 32); // convert big-endian to little-endian
5699 movq(product, x_xstart);
5700 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
5701 movq(yz_idx, Address(z, idx, Address::times_4, offset));
5702 rorq(yz_idx, 32); // convert big-endian to little-endian
5703
5704 add2_with_carry(rdx, product, carry, yz_idx);
5705
5706 movl(Address(z, idx, Address::times_4, offset+4), product);
5707 shrq(product, 32);
5708 movl(Address(z, idx, Address::times_4, offset), product);
5709
5710 }
5711
5712 /**
5713 * Multiply 128 bit by 128 bit. Unrolled inner loop.
5714 */
5715 void MacroAssembler::multiply_128_x_128_loop(Register x_xstart, Register y, Register z,
5716 Register yz_idx, Register idx, Register jdx,
5717 Register carry, Register product,
5718 Register carry2) {
5719 // jlong carry, x[], y[], z[];
5720 // int kdx = ystart+1;
5721 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
5722 // huge_128 product = (y[idx+1] * x_xstart) + z[kdx+idx+1] + carry;
5723 // z[kdx+idx+1] = (jlong)product;
5724 // jlong carry2 = (jlong)(product >>> 64);
5725 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry2;
5726 // z[kdx+idx] = (jlong)product;
5727 // carry = (jlong)(product >>> 64);
5728 // }
5729 // idx += 2;
5730 // if (idx > 0) {
5731 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry;
5732 // z[kdx+idx] = (jlong)product;
5733 // carry = (jlong)(product >>> 64);
5734 // }
5735 //
5736
5737 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
5738
5739 movl(jdx, idx);
5740 andl(jdx, 0xFFFFFFFC);
5741 shrl(jdx, 2);
5742
5743 bind(L_third_loop);
5744 subl(jdx, 1);
5745 jcc(Assembler::negative, L_third_loop_exit);
5746 subl(idx, 4);
5747
5748 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 8);
5749 movq(carry2, rdx);
5750
5751 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry2, product, 0);
5752 movq(carry, rdx);
5753 jmp(L_third_loop);
5754
5755 bind (L_third_loop_exit);
5756
5757 andl (idx, 0x3);
5758 jcc(Assembler::zero, L_post_third_loop_done);
5759
5760 Label L_check_1;
5761 subl(idx, 2);
5762 jcc(Assembler::negative, L_check_1);
5763
5764 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 0);
5765 movq(carry, rdx);
5766
5767 bind (L_check_1);
5768 addl (idx, 0x2);
5769 andl (idx, 0x1);
5770 subl(idx, 1);
5771 jcc(Assembler::negative, L_post_third_loop_done);
5772
5773 movl(yz_idx, Address(y, idx, Address::times_4, 0));
5774 movq(product, x_xstart);
5775 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
5776 movl(yz_idx, Address(z, idx, Address::times_4, 0));
5777
5778 add2_with_carry(rdx, product, yz_idx, carry);
5779
5780 movl(Address(z, idx, Address::times_4, 0), product);
5781 shrq(product, 32);
5782
5783 shlq(rdx, 32);
5784 orq(product, rdx);
5785 movq(carry, product);
5786
5787 bind(L_post_third_loop_done);
5788 }
5789
5790 /**
5791 * Multiply 128 bit by 128 bit using BMI2. Unrolled inner loop.
5792 *
5793 */
5794 void MacroAssembler::multiply_128_x_128_bmi2_loop(Register y, Register z,
5795 Register carry, Register carry2,
5796 Register idx, Register jdx,
5797 Register yz_idx1, Register yz_idx2,
5798 Register tmp, Register tmp3, Register tmp4) {
5799 assert(UseBMI2Instructions, "should be used only when BMI2 is available");
5800
5801 // jlong carry, x[], y[], z[];
5802 // int kdx = ystart+1;
5803 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
5804 // huge_128 tmp3 = (y[idx+1] * rdx) + z[kdx+idx+1] + carry;
5805 // jlong carry2 = (jlong)(tmp3 >>> 64);
5806 // huge_128 tmp4 = (y[idx] * rdx) + z[kdx+idx] + carry2;
5807 // carry = (jlong)(tmp4 >>> 64);
5808 // z[kdx+idx+1] = (jlong)tmp3;
5809 // z[kdx+idx] = (jlong)tmp4;
5810 // }
5811 // idx += 2;
5812 // if (idx > 0) {
5813 // yz_idx1 = (y[idx] * rdx) + z[kdx+idx] + carry;
5814 // z[kdx+idx] = (jlong)yz_idx1;
5815 // carry = (jlong)(yz_idx1 >>> 64);
5816 // }
5817 //
5818
5819 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
5820
5821 movl(jdx, idx);
5822 andl(jdx, 0xFFFFFFFC);
5823 shrl(jdx, 2);
5824
5825 bind(L_third_loop);
5826 subl(jdx, 1);
5827 jcc(Assembler::negative, L_third_loop_exit);
5828 subl(idx, 4);
5829
5830 movq(yz_idx1, Address(y, idx, Address::times_4, 8));
5831 rorxq(yz_idx1, yz_idx1, 32); // convert big-endian to little-endian
5832 movq(yz_idx2, Address(y, idx, Address::times_4, 0));
5833 rorxq(yz_idx2, yz_idx2, 32);
5834
5835 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3
5836 mulxq(carry2, tmp, yz_idx2); // yz_idx2 * rdx -> carry2:tmp
5837
5838 movq(yz_idx1, Address(z, idx, Address::times_4, 8));
5839 rorxq(yz_idx1, yz_idx1, 32);
5840 movq(yz_idx2, Address(z, idx, Address::times_4, 0));
5841 rorxq(yz_idx2, yz_idx2, 32);
5842
5843 if (VM_Version::supports_adx()) {
5844 adcxq(tmp3, carry);
5845 adoxq(tmp3, yz_idx1);
5846
5847 adcxq(tmp4, tmp);
5848 adoxq(tmp4, yz_idx2);
5849
5850 movl(carry, 0); // does not affect flags
5851 adcxq(carry2, carry);
5852 adoxq(carry2, carry);
5853 } else {
5854 add2_with_carry(tmp4, tmp3, carry, yz_idx1);
5855 add2_with_carry(carry2, tmp4, tmp, yz_idx2);
5856 }
5857 movq(carry, carry2);
5858
5859 movl(Address(z, idx, Address::times_4, 12), tmp3);
5860 shrq(tmp3, 32);
5861 movl(Address(z, idx, Address::times_4, 8), tmp3);
5862
5863 movl(Address(z, idx, Address::times_4, 4), tmp4);
5864 shrq(tmp4, 32);
5865 movl(Address(z, idx, Address::times_4, 0), tmp4);
5866
5867 jmp(L_third_loop);
5868
5869 bind (L_third_loop_exit);
5870
5871 andl (idx, 0x3);
5872 jcc(Assembler::zero, L_post_third_loop_done);
5873
5874 Label L_check_1;
5875 subl(idx, 2);
5876 jcc(Assembler::negative, L_check_1);
5877
5878 movq(yz_idx1, Address(y, idx, Address::times_4, 0));
5879 rorxq(yz_idx1, yz_idx1, 32);
5880 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3
5881 movq(yz_idx2, Address(z, idx, Address::times_4, 0));
5882 rorxq(yz_idx2, yz_idx2, 32);
5883
5884 add2_with_carry(tmp4, tmp3, carry, yz_idx2);
5885
5886 movl(Address(z, idx, Address::times_4, 4), tmp3);
5887 shrq(tmp3, 32);
5888 movl(Address(z, idx, Address::times_4, 0), tmp3);
5889 movq(carry, tmp4);
5890
5891 bind (L_check_1);
5892 addl (idx, 0x2);
5893 andl (idx, 0x1);
5894 subl(idx, 1);
5895 jcc(Assembler::negative, L_post_third_loop_done);
5896 movl(tmp4, Address(y, idx, Address::times_4, 0));
5897 mulxq(carry2, tmp3, tmp4); // tmp4 * rdx -> carry2:tmp3
5898 movl(tmp4, Address(z, idx, Address::times_4, 0));
5899
5900 add2_with_carry(carry2, tmp3, tmp4, carry);
5901
5902 movl(Address(z, idx, Address::times_4, 0), tmp3);
5903 shrq(tmp3, 32);
5904
5905 shlq(carry2, 32);
5906 orq(tmp3, carry2);
5907 movq(carry, tmp3);
5908
5909 bind(L_post_third_loop_done);
5910 }
5911
5912 /**
5913 * Code for BigInteger::multiplyToLen() instrinsic.
5914 *
5915 * rdi: x
5916 * rax: xlen
5917 * rsi: y
5918 * rcx: ylen
5919 * r8: z
5920 * r11: zlen
5921 * r12: tmp1
5922 * r13: tmp2
5923 * r14: tmp3
5924 * r15: tmp4
5925 * rbx: tmp5
5926 *
5927 */
5928 void MacroAssembler::multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register zlen,
5929 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5) {
5930 ShortBranchVerifier sbv(this);
5931 assert_different_registers(x, xlen, y, ylen, z, zlen, tmp1, tmp2, tmp3, tmp4, tmp5, rdx);
5932
5933 push(tmp1);
5934 push(tmp2);
5935 push(tmp3);
5936 push(tmp4);
5937 push(tmp5);
5938
5939 push(xlen);
5940 push(zlen);
5941
5942 const Register idx = tmp1;
5943 const Register kdx = tmp2;
5944 const Register xstart = tmp3;
5945
5946 const Register y_idx = tmp4;
5947 const Register carry = tmp5;
5948 const Register product = xlen;
5949 const Register x_xstart = zlen; // reuse register
5950
5951 // First Loop.
5952 //
5953 // final static long LONG_MASK = 0xffffffffL;
5954 // int xstart = xlen - 1;
5955 // int ystart = ylen - 1;
5956 // long carry = 0;
5957 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
5958 // long product = (y[idx] & LONG_MASK) * (x[xstart] & LONG_MASK) + carry;
5959 // z[kdx] = (int)product;
5960 // carry = product >>> 32;
5961 // }
5962 // z[xstart] = (int)carry;
5963 //
5964
5965 movl(idx, ylen); // idx = ylen;
5966 movl(kdx, zlen); // kdx = xlen+ylen;
5967 xorq(carry, carry); // carry = 0;
5968
5969 Label L_done;
5970
5971 movl(xstart, xlen);
5972 decrementl(xstart);
5973 jcc(Assembler::negative, L_done);
5974
5975 multiply_64_x_64_loop(x, xstart, x_xstart, y, y_idx, z, carry, product, idx, kdx);
5976
5977 Label L_second_loop;
5978 testl(kdx, kdx);
5979 jcc(Assembler::zero, L_second_loop);
5980
5981 Label L_carry;
5982 subl(kdx, 1);
5983 jcc(Assembler::zero, L_carry);
5984
5985 movl(Address(z, kdx, Address::times_4, 0), carry);
5986 shrq(carry, 32);
5987 subl(kdx, 1);
5988
5989 bind(L_carry);
5990 movl(Address(z, kdx, Address::times_4, 0), carry);
5991
5992 // Second and third (nested) loops.
5993 //
5994 // for (int i = xstart-1; i >= 0; i--) { // Second loop
5995 // carry = 0;
5996 // for (int jdx=ystart, k=ystart+1+i; jdx >= 0; jdx--, k--) { // Third loop
5997 // long product = (y[jdx] & LONG_MASK) * (x[i] & LONG_MASK) +
5998 // (z[k] & LONG_MASK) + carry;
5999 // z[k] = (int)product;
6000 // carry = product >>> 32;
6001 // }
6002 // z[i] = (int)carry;
6003 // }
6004 //
6005 // i = xlen, j = tmp1, k = tmp2, carry = tmp5, x[i] = rdx
6006
6007 const Register jdx = tmp1;
6008
6009 bind(L_second_loop);
6010 xorl(carry, carry); // carry = 0;
6011 movl(jdx, ylen); // j = ystart+1
6012
6013 subl(xstart, 1); // i = xstart-1;
6014 jcc(Assembler::negative, L_done);
6015
6016 push (z);
6017
6018 Label L_last_x;
6019 lea(z, Address(z, xstart, Address::times_4, 4)); // z = z + k - j
6020 subl(xstart, 1); // i = xstart-1;
6021 jcc(Assembler::negative, L_last_x);
6022
6023 if (UseBMI2Instructions) {
6024 movq(rdx, Address(x, xstart, Address::times_4, 0));
6025 rorxq(rdx, rdx, 32); // convert big-endian to little-endian
6026 } else {
6027 movq(x_xstart, Address(x, xstart, Address::times_4, 0));
6028 rorq(x_xstart, 32); // convert big-endian to little-endian
6029 }
6030
6031 Label L_third_loop_prologue;
6032 bind(L_third_loop_prologue);
6033
6034 push (x);
6035 push (xstart);
6036 push (ylen);
6037
6038
6039 if (UseBMI2Instructions) {
6040 multiply_128_x_128_bmi2_loop(y, z, carry, x, jdx, ylen, product, tmp2, x_xstart, tmp3, tmp4);
6041 } else { // !UseBMI2Instructions
6042 multiply_128_x_128_loop(x_xstart, y, z, y_idx, jdx, ylen, carry, product, x);
6043 }
6044
6045 pop(ylen);
6046 pop(xlen);
6047 pop(x);
6048 pop(z);
6049
6050 movl(tmp3, xlen);
6051 addl(tmp3, 1);
6052 movl(Address(z, tmp3, Address::times_4, 0), carry);
6053 subl(tmp3, 1);
6054 jccb(Assembler::negative, L_done);
6055
6056 shrq(carry, 32);
6057 movl(Address(z, tmp3, Address::times_4, 0), carry);
6058 jmp(L_second_loop);
6059
6060 // Next infrequent code is moved outside loops.
6061 bind(L_last_x);
6062 if (UseBMI2Instructions) {
6063 movl(rdx, Address(x, 0));
6064 } else {
6065 movl(x_xstart, Address(x, 0));
6066 }
6067 jmp(L_third_loop_prologue);
6068
6069 bind(L_done);
6070
6071 pop(zlen);
6072 pop(xlen);
6073
6074 pop(tmp5);
6075 pop(tmp4);
6076 pop(tmp3);
6077 pop(tmp2);
6078 pop(tmp1);
6079 }
6080
6081 void MacroAssembler::vectorized_mismatch(Register obja, Register objb, Register length, Register log2_array_indxscale,
6082 Register result, Register tmp1, Register tmp2, XMMRegister rymm0, XMMRegister rymm1, XMMRegister rymm2){
6083 assert(UseSSE42Intrinsics, "SSE4.2 must be enabled.");
6084 Label VECTOR16_LOOP, VECTOR8_LOOP, VECTOR4_LOOP;
6085 Label VECTOR8_TAIL, VECTOR4_TAIL;
6086 Label VECTOR32_NOT_EQUAL, VECTOR16_NOT_EQUAL, VECTOR8_NOT_EQUAL, VECTOR4_NOT_EQUAL;
6087 Label SAME_TILL_END, DONE;
6088 Label BYTES_LOOP, BYTES_TAIL, BYTES_NOT_EQUAL;
6089
6090 //scale is in rcx in both Win64 and Unix
6091 ShortBranchVerifier sbv(this);
6092
6093 shlq(length);
6094 xorq(result, result);
6095
6096 if ((AVX3Threshold == 0) && (UseAVX > 2) &&
6097 VM_Version::supports_avx512vlbw()) {
6098 Label VECTOR64_LOOP, VECTOR64_NOT_EQUAL, VECTOR32_TAIL;
6099
6100 cmpq(length, 64);
6101 jcc(Assembler::less, VECTOR32_TAIL);
6102
6103 movq(tmp1, length);
6104 andq(tmp1, 0x3F); // tail count
6105 andq(length, ~(0x3F)); //vector count
6106
6107 bind(VECTOR64_LOOP);
6108 // AVX512 code to compare 64 byte vectors.
6109 evmovdqub(rymm0, Address(obja, result), false, Assembler::AVX_512bit);
6110 evpcmpeqb(k7, rymm0, Address(objb, result), Assembler::AVX_512bit);
6111 kortestql(k7, k7);
6112 jcc(Assembler::aboveEqual, VECTOR64_NOT_EQUAL); // mismatch
6113 addq(result, 64);
6114 subq(length, 64);
6115 jccb(Assembler::notZero, VECTOR64_LOOP);
6116
6117 //bind(VECTOR64_TAIL);
6118 testq(tmp1, tmp1);
6119 jcc(Assembler::zero, SAME_TILL_END);
6120
6121 //bind(VECTOR64_TAIL);
6122 // AVX512 code to compare upto 63 byte vectors.
6123 mov64(tmp2, 0xFFFFFFFFFFFFFFFF);
6124 shlxq(tmp2, tmp2, tmp1);
6125 notq(tmp2);
6126 kmovql(k3, tmp2);
6127
6128 evmovdqub(rymm0, k3, Address(obja, result), false, Assembler::AVX_512bit);
6129 evpcmpeqb(k7, k3, rymm0, Address(objb, result), Assembler::AVX_512bit);
6130
6131 ktestql(k7, k3);
6132 jcc(Assembler::below, SAME_TILL_END); // not mismatch
6133
6134 bind(VECTOR64_NOT_EQUAL);
6135 kmovql(tmp1, k7);
6136 notq(tmp1);
6137 tzcntq(tmp1, tmp1);
6138 addq(result, tmp1);
6139 shrq(result);
6140 jmp(DONE);
6141 bind(VECTOR32_TAIL);
6142 }
6143
6144 cmpq(length, 8);
6145 jcc(Assembler::equal, VECTOR8_LOOP);
6146 jcc(Assembler::less, VECTOR4_TAIL);
6147
6148 if (UseAVX >= 2) {
6149 Label VECTOR16_TAIL, VECTOR32_LOOP;
6150
6151 cmpq(length, 16);
6152 jcc(Assembler::equal, VECTOR16_LOOP);
6153 jcc(Assembler::less, VECTOR8_LOOP);
6154
6155 cmpq(length, 32);
6156 jccb(Assembler::less, VECTOR16_TAIL);
6157
6158 subq(length, 32);
6159 bind(VECTOR32_LOOP);
6160 vmovdqu(rymm0, Address(obja, result));
6161 vmovdqu(rymm1, Address(objb, result));
6162 vpxor(rymm2, rymm0, rymm1, Assembler::AVX_256bit);
6163 vptest(rymm2, rymm2);
6164 jcc(Assembler::notZero, VECTOR32_NOT_EQUAL);//mismatch found
6165 addq(result, 32);
6166 subq(length, 32);
6167 jcc(Assembler::greaterEqual, VECTOR32_LOOP);
6168 addq(length, 32);
6169 jcc(Assembler::equal, SAME_TILL_END);
6170 //falling through if less than 32 bytes left //close the branch here.
6171
6172 bind(VECTOR16_TAIL);
6173 cmpq(length, 16);
6174 jccb(Assembler::less, VECTOR8_TAIL);
6175 bind(VECTOR16_LOOP);
6176 movdqu(rymm0, Address(obja, result));
6177 movdqu(rymm1, Address(objb, result));
6178 vpxor(rymm2, rymm0, rymm1, Assembler::AVX_128bit);
6179 ptest(rymm2, rymm2);
6180 jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found
6181 addq(result, 16);
6182 subq(length, 16);
6183 jcc(Assembler::equal, SAME_TILL_END);
6184 //falling through if less than 16 bytes left
6185 } else {//regular intrinsics
6186
6187 cmpq(length, 16);
6188 jccb(Assembler::less, VECTOR8_TAIL);
6189
6190 subq(length, 16);
6191 bind(VECTOR16_LOOP);
6192 movdqu(rymm0, Address(obja, result));
6193 movdqu(rymm1, Address(objb, result));
6194 pxor(rymm0, rymm1);
6195 ptest(rymm0, rymm0);
6196 jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found
6197 addq(result, 16);
6198 subq(length, 16);
6199 jccb(Assembler::greaterEqual, VECTOR16_LOOP);
6200 addq(length, 16);
6201 jcc(Assembler::equal, SAME_TILL_END);
6202 //falling through if less than 16 bytes left
6203 }
6204
6205 bind(VECTOR8_TAIL);
6206 cmpq(length, 8);
6207 jccb(Assembler::less, VECTOR4_TAIL);
6208 bind(VECTOR8_LOOP);
6209 movq(tmp1, Address(obja, result));
6210 movq(tmp2, Address(objb, result));
6211 xorq(tmp1, tmp2);
6212 testq(tmp1, tmp1);
6213 jcc(Assembler::notZero, VECTOR8_NOT_EQUAL);//mismatch found
6214 addq(result, 8);
6215 subq(length, 8);
6216 jcc(Assembler::equal, SAME_TILL_END);
6217 //falling through if less than 8 bytes left
6218
6219 bind(VECTOR4_TAIL);
6220 cmpq(length, 4);
6221 jccb(Assembler::less, BYTES_TAIL);
6222 bind(VECTOR4_LOOP);
6223 movl(tmp1, Address(obja, result));
6224 xorl(tmp1, Address(objb, result));
6225 testl(tmp1, tmp1);
6226 jcc(Assembler::notZero, VECTOR4_NOT_EQUAL);//mismatch found
6227 addq(result, 4);
6228 subq(length, 4);
6229 jcc(Assembler::equal, SAME_TILL_END);
6230 //falling through if less than 4 bytes left
6231
6232 bind(BYTES_TAIL);
6233 bind(BYTES_LOOP);
6234 load_unsigned_byte(tmp1, Address(obja, result));
6235 load_unsigned_byte(tmp2, Address(objb, result));
6236 xorl(tmp1, tmp2);
6237 testl(tmp1, tmp1);
6238 jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
6239 decq(length);
6240 jcc(Assembler::zero, SAME_TILL_END);
6241 incq(result);
6242 load_unsigned_byte(tmp1, Address(obja, result));
6243 load_unsigned_byte(tmp2, Address(objb, result));
6244 xorl(tmp1, tmp2);
6245 testl(tmp1, tmp1);
6246 jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
6247 decq(length);
6248 jcc(Assembler::zero, SAME_TILL_END);
6249 incq(result);
6250 load_unsigned_byte(tmp1, Address(obja, result));
6251 load_unsigned_byte(tmp2, Address(objb, result));
6252 xorl(tmp1, tmp2);
6253 testl(tmp1, tmp1);
6254 jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
6255 jmp(SAME_TILL_END);
6256
6257 if (UseAVX >= 2) {
6258 bind(VECTOR32_NOT_EQUAL);
6259 vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_256bit);
6260 vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_256bit);
6261 vpxor(rymm0, rymm0, rymm2, Assembler::AVX_256bit);
6262 vpmovmskb(tmp1, rymm0);
6263 bsfq(tmp1, tmp1);
6264 addq(result, tmp1);
6265 shrq(result);
6266 jmp(DONE);
6267 }
6268
6269 bind(VECTOR16_NOT_EQUAL);
6270 if (UseAVX >= 2) {
6271 vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_128bit);
6272 vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_128bit);
6273 pxor(rymm0, rymm2);
6274 } else {
6275 pcmpeqb(rymm2, rymm2);
6276 pxor(rymm0, rymm1);
6277 pcmpeqb(rymm0, rymm1);
6278 pxor(rymm0, rymm2);
6279 }
6280 pmovmskb(tmp1, rymm0);
6281 bsfq(tmp1, tmp1);
6282 addq(result, tmp1);
6283 shrq(result);
6284 jmpb(DONE);
6285
6286 bind(VECTOR8_NOT_EQUAL);
6287 bind(VECTOR4_NOT_EQUAL);
6288 bsfq(tmp1, tmp1);
6289 shrq(tmp1, 3);
6290 addq(result, tmp1);
6291 bind(BYTES_NOT_EQUAL);
6292 shrq(result);
6293 jmpb(DONE);
6294
6295 bind(SAME_TILL_END);
6296 mov64(result, -1);
6297
6298 bind(DONE);
6299 }
6300
6301 //Helper functions for square_to_len()
6302
6303 /**
6304 * Store the squares of x[], right shifted one bit (divided by 2) into z[]
6305 * Preserves x and z and modifies rest of the registers.
6306 */
6307 void MacroAssembler::square_rshift(Register x, Register xlen, Register z, Register tmp1, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
6308 // Perform square and right shift by 1
6309 // Handle odd xlen case first, then for even xlen do the following
6310 // jlong carry = 0;
6311 // for (int j=0, i=0; j < xlen; j+=2, i+=4) {
6312 // huge_128 product = x[j:j+1] * x[j:j+1];
6313 // z[i:i+1] = (carry << 63) | (jlong)(product >>> 65);
6314 // z[i+2:i+3] = (jlong)(product >>> 1);
6315 // carry = (jlong)product;
6316 // }
6317
6318 xorq(tmp5, tmp5); // carry
6319 xorq(rdxReg, rdxReg);
6320 xorl(tmp1, tmp1); // index for x
6321 xorl(tmp4, tmp4); // index for z
6322
6323 Label L_first_loop, L_first_loop_exit;
6324
6325 testl(xlen, 1);
6326 jccb(Assembler::zero, L_first_loop); //jump if xlen is even
6327
6328 // Square and right shift by 1 the odd element using 32 bit multiply
6329 movl(raxReg, Address(x, tmp1, Address::times_4, 0));
6330 imulq(raxReg, raxReg);
6331 shrq(raxReg, 1);
6332 adcq(tmp5, 0);
6333 movq(Address(z, tmp4, Address::times_4, 0), raxReg);
6334 incrementl(tmp1);
6335 addl(tmp4, 2);
6336
6337 // Square and right shift by 1 the rest using 64 bit multiply
6338 bind(L_first_loop);
6339 cmpptr(tmp1, xlen);
6340 jccb(Assembler::equal, L_first_loop_exit);
6341
6342 // Square
6343 movq(raxReg, Address(x, tmp1, Address::times_4, 0));
6344 rorq(raxReg, 32); // convert big-endian to little-endian
6345 mulq(raxReg); // 64-bit multiply rax * rax -> rdx:rax
6346
6347 // Right shift by 1 and save carry
6348 shrq(tmp5, 1); // rdx:rax:tmp5 = (tmp5:rdx:rax) >>> 1
6349 rcrq(rdxReg, 1);
6350 rcrq(raxReg, 1);
6351 adcq(tmp5, 0);
6352
6353 // Store result in z
6354 movq(Address(z, tmp4, Address::times_4, 0), rdxReg);
6355 movq(Address(z, tmp4, Address::times_4, 8), raxReg);
6356
6357 // Update indices for x and z
6358 addl(tmp1, 2);
6359 addl(tmp4, 4);
6360 jmp(L_first_loop);
6361
6362 bind(L_first_loop_exit);
6363 }
6364
6365
6366 /**
6367 * Perform the following multiply add operation using BMI2 instructions
6368 * carry:sum = sum + op1*op2 + carry
6369 * op2 should be in rdx
6370 * op2 is preserved, all other registers are modified
6371 */
6372 void MacroAssembler::multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry, Register tmp2) {
6373 // assert op2 is rdx
6374 mulxq(tmp2, op1, op1); // op1 * op2 -> tmp2:op1
6375 addq(sum, carry);
6376 adcq(tmp2, 0);
6377 addq(sum, op1);
6378 adcq(tmp2, 0);
6379 movq(carry, tmp2);
6380 }
6381
6382 /**
6383 * Perform the following multiply add operation:
6384 * carry:sum = sum + op1*op2 + carry
6385 * Preserves op1, op2 and modifies rest of registers
6386 */
6387 void MacroAssembler::multiply_add_64(Register sum, Register op1, Register op2, Register carry, Register rdxReg, Register raxReg) {
6388 // rdx:rax = op1 * op2
6389 movq(raxReg, op2);
6390 mulq(op1);
6391
6392 // rdx:rax = sum + carry + rdx:rax
6393 addq(sum, carry);
6394 adcq(rdxReg, 0);
6395 addq(sum, raxReg);
6396 adcq(rdxReg, 0);
6397
6398 // carry:sum = rdx:sum
6399 movq(carry, rdxReg);
6400 }
6401
6402 /**
6403 * Add 64 bit long carry into z[] with carry propogation.
6404 * Preserves z and carry register values and modifies rest of registers.
6405 *
6406 */
6407 void MacroAssembler::add_one_64(Register z, Register zlen, Register carry, Register tmp1) {
6408 Label L_fourth_loop, L_fourth_loop_exit;
6409
6410 movl(tmp1, 1);
6411 subl(zlen, 2);
6412 addq(Address(z, zlen, Address::times_4, 0), carry);
6413
6414 bind(L_fourth_loop);
6415 jccb(Assembler::carryClear, L_fourth_loop_exit);
6416 subl(zlen, 2);
6417 jccb(Assembler::negative, L_fourth_loop_exit);
6418 addq(Address(z, zlen, Address::times_4, 0), tmp1);
6419 jmp(L_fourth_loop);
6420 bind(L_fourth_loop_exit);
6421 }
6422
6423 /**
6424 * Shift z[] left by 1 bit.
6425 * Preserves x, len, z and zlen registers and modifies rest of the registers.
6426 *
6427 */
6428 void MacroAssembler::lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4) {
6429
6430 Label L_fifth_loop, L_fifth_loop_exit;
6431
6432 // Fifth loop
6433 // Perform primitiveLeftShift(z, zlen, 1)
6434
6435 const Register prev_carry = tmp1;
6436 const Register new_carry = tmp4;
6437 const Register value = tmp2;
6438 const Register zidx = tmp3;
6439
6440 // int zidx, carry;
6441 // long value;
6442 // carry = 0;
6443 // for (zidx = zlen-2; zidx >=0; zidx -= 2) {
6444 // (carry:value) = (z[i] << 1) | carry ;
6445 // z[i] = value;
6446 // }
6447
6448 movl(zidx, zlen);
6449 xorl(prev_carry, prev_carry); // clear carry flag and prev_carry register
6450
6451 bind(L_fifth_loop);
6452 decl(zidx); // Use decl to preserve carry flag
6453 decl(zidx);
6454 jccb(Assembler::negative, L_fifth_loop_exit);
6455
6456 if (UseBMI2Instructions) {
6457 movq(value, Address(z, zidx, Address::times_4, 0));
6458 rclq(value, 1);
6459 rorxq(value, value, 32);
6460 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form
6461 }
6462 else {
6463 // clear new_carry
6464 xorl(new_carry, new_carry);
6465
6466 // Shift z[i] by 1, or in previous carry and save new carry
6467 movq(value, Address(z, zidx, Address::times_4, 0));
6468 shlq(value, 1);
6469 adcl(new_carry, 0);
6470
6471 orq(value, prev_carry);
6472 rorq(value, 0x20);
6473 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form
6474
6475 // Set previous carry = new carry
6476 movl(prev_carry, new_carry);
6477 }
6478 jmp(L_fifth_loop);
6479
6480 bind(L_fifth_loop_exit);
6481 }
6482
6483
6484 /**
6485 * Code for BigInteger::squareToLen() intrinsic
6486 *
6487 * rdi: x
6488 * rsi: len
6489 * r8: z
6490 * rcx: zlen
6491 * r12: tmp1
6492 * r13: tmp2
6493 * r14: tmp3
6494 * r15: tmp4
6495 * rbx: tmp5
6496 *
6497 */
6498 void MacroAssembler::square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
6499
6500 Label L_second_loop, L_second_loop_exit, L_third_loop, L_third_loop_exit, L_last_x, L_multiply;
6501 push(tmp1);
6502 push(tmp2);
6503 push(tmp3);
6504 push(tmp4);
6505 push(tmp5);
6506
6507 // First loop
6508 // Store the squares, right shifted one bit (i.e., divided by 2).
6509 square_rshift(x, len, z, tmp1, tmp3, tmp4, tmp5, rdxReg, raxReg);
6510
6511 // Add in off-diagonal sums.
6512 //
6513 // Second, third (nested) and fourth loops.
6514 // zlen +=2;
6515 // for (int xidx=len-2,zidx=zlen-4; xidx > 0; xidx-=2,zidx-=4) {
6516 // carry = 0;
6517 // long op2 = x[xidx:xidx+1];
6518 // for (int j=xidx-2,k=zidx; j >= 0; j-=2) {
6519 // k -= 2;
6520 // long op1 = x[j:j+1];
6521 // long sum = z[k:k+1];
6522 // carry:sum = multiply_add_64(sum, op1, op2, carry, tmp_regs);
6523 // z[k:k+1] = sum;
6524 // }
6525 // add_one_64(z, k, carry, tmp_regs);
6526 // }
6527
6528 const Register carry = tmp5;
6529 const Register sum = tmp3;
6530 const Register op1 = tmp4;
6531 Register op2 = tmp2;
6532
6533 push(zlen);
6534 push(len);
6535 addl(zlen,2);
6536 bind(L_second_loop);
6537 xorq(carry, carry);
6538 subl(zlen, 4);
6539 subl(len, 2);
6540 push(zlen);
6541 push(len);
6542 cmpl(len, 0);
6543 jccb(Assembler::lessEqual, L_second_loop_exit);
6544
6545 // Multiply an array by one 64 bit long.
6546 if (UseBMI2Instructions) {
6547 op2 = rdxReg;
6548 movq(op2, Address(x, len, Address::times_4, 0));
6549 rorxq(op2, op2, 32);
6550 }
6551 else {
6552 movq(op2, Address(x, len, Address::times_4, 0));
6553 rorq(op2, 32);
6554 }
6555
6556 bind(L_third_loop);
6557 decrementl(len);
6558 jccb(Assembler::negative, L_third_loop_exit);
6559 decrementl(len);
6560 jccb(Assembler::negative, L_last_x);
6561
6562 movq(op1, Address(x, len, Address::times_4, 0));
6563 rorq(op1, 32);
6564
6565 bind(L_multiply);
6566 subl(zlen, 2);
6567 movq(sum, Address(z, zlen, Address::times_4, 0));
6568
6569 // Multiply 64 bit by 64 bit and add 64 bits lower half and upper 64 bits as carry.
6570 if (UseBMI2Instructions) {
6571 multiply_add_64_bmi2(sum, op1, op2, carry, tmp2);
6572 }
6573 else {
6574 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
6575 }
6576
6577 movq(Address(z, zlen, Address::times_4, 0), sum);
6578
6579 jmp(L_third_loop);
6580 bind(L_third_loop_exit);
6581
6582 // Fourth loop
6583 // Add 64 bit long carry into z with carry propogation.
6584 // Uses offsetted zlen.
6585 add_one_64(z, zlen, carry, tmp1);
6586
6587 pop(len);
6588 pop(zlen);
6589 jmp(L_second_loop);
6590
6591 // Next infrequent code is moved outside loops.
6592 bind(L_last_x);
6593 movl(op1, Address(x, 0));
6594 jmp(L_multiply);
6595
6596 bind(L_second_loop_exit);
6597 pop(len);
6598 pop(zlen);
6599 pop(len);
6600 pop(zlen);
6601
6602 // Fifth loop
6603 // Shift z left 1 bit.
6604 lshift_by_1(x, len, z, zlen, tmp1, tmp2, tmp3, tmp4);
6605
6606 // z[zlen-1] |= x[len-1] & 1;
6607 movl(tmp3, Address(x, len, Address::times_4, -4));
6608 andl(tmp3, 1);
6609 orl(Address(z, zlen, Address::times_4, -4), tmp3);
6610
6611 pop(tmp5);
6612 pop(tmp4);
6613 pop(tmp3);
6614 pop(tmp2);
6615 pop(tmp1);
6616 }
6617
6618 /**
6619 * Helper function for mul_add()
6620 * Multiply the in[] by int k and add to out[] starting at offset offs using
6621 * 128 bit by 32 bit multiply and return the carry in tmp5.
6622 * Only quad int aligned length of in[] is operated on in this function.
6623 * k is in rdxReg for BMI2Instructions, for others it is in tmp2.
6624 * This function preserves out, in and k registers.
6625 * len and offset point to the appropriate index in "in" & "out" correspondingly
6626 * tmp5 has the carry.
6627 * other registers are temporary and are modified.
6628 *
6629 */
6630 void MacroAssembler::mul_add_128_x_32_loop(Register out, Register in,
6631 Register offset, Register len, Register tmp1, Register tmp2, Register tmp3,
6632 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
6633
6634 Label L_first_loop, L_first_loop_exit;
6635
6636 movl(tmp1, len);
6637 shrl(tmp1, 2);
6638
6639 bind(L_first_loop);
6640 subl(tmp1, 1);
6641 jccb(Assembler::negative, L_first_loop_exit);
6642
6643 subl(len, 4);
6644 subl(offset, 4);
6645
6646 Register op2 = tmp2;
6647 const Register sum = tmp3;
6648 const Register op1 = tmp4;
6649 const Register carry = tmp5;
6650
6651 if (UseBMI2Instructions) {
6652 op2 = rdxReg;
6653 }
6654
6655 movq(op1, Address(in, len, Address::times_4, 8));
6656 rorq(op1, 32);
6657 movq(sum, Address(out, offset, Address::times_4, 8));
6658 rorq(sum, 32);
6659 if (UseBMI2Instructions) {
6660 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
6661 }
6662 else {
6663 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
6664 }
6665 // Store back in big endian from little endian
6666 rorq(sum, 0x20);
6667 movq(Address(out, offset, Address::times_4, 8), sum);
6668
6669 movq(op1, Address(in, len, Address::times_4, 0));
6670 rorq(op1, 32);
6671 movq(sum, Address(out, offset, Address::times_4, 0));
6672 rorq(sum, 32);
6673 if (UseBMI2Instructions) {
6674 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
6675 }
6676 else {
6677 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
6678 }
6679 // Store back in big endian from little endian
6680 rorq(sum, 0x20);
6681 movq(Address(out, offset, Address::times_4, 0), sum);
6682
6683 jmp(L_first_loop);
6684 bind(L_first_loop_exit);
6685 }
6686
6687 /**
6688 * Code for BigInteger::mulAdd() intrinsic
6689 *
6690 * rdi: out
6691 * rsi: in
6692 * r11: offs (out.length - offset)
6693 * rcx: len
6694 * r8: k
6695 * r12: tmp1
6696 * r13: tmp2
6697 * r14: tmp3
6698 * r15: tmp4
6699 * rbx: tmp5
6700 * Multiply the in[] by word k and add to out[], return the carry in rax
6701 */
6702 void MacroAssembler::mul_add(Register out, Register in, Register offs,
6703 Register len, Register k, Register tmp1, Register tmp2, Register tmp3,
6704 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
6705
6706 Label L_carry, L_last_in, L_done;
6707
6708 // carry = 0;
6709 // for (int j=len-1; j >= 0; j--) {
6710 // long product = (in[j] & LONG_MASK) * kLong +
6711 // (out[offs] & LONG_MASK) + carry;
6712 // out[offs--] = (int)product;
6713 // carry = product >>> 32;
6714 // }
6715 //
6716 push(tmp1);
6717 push(tmp2);
6718 push(tmp3);
6719 push(tmp4);
6720 push(tmp5);
6721
6722 Register op2 = tmp2;
6723 const Register sum = tmp3;
6724 const Register op1 = tmp4;
6725 const Register carry = tmp5;
6726
6727 if (UseBMI2Instructions) {
6728 op2 = rdxReg;
6729 movl(op2, k);
6730 }
6731 else {
6732 movl(op2, k);
6733 }
6734
6735 xorq(carry, carry);
6736
6737 //First loop
6738
6739 //Multiply in[] by k in a 4 way unrolled loop using 128 bit by 32 bit multiply
6740 //The carry is in tmp5
6741 mul_add_128_x_32_loop(out, in, offs, len, tmp1, tmp2, tmp3, tmp4, tmp5, rdxReg, raxReg);
6742
6743 //Multiply the trailing in[] entry using 64 bit by 32 bit, if any
6744 decrementl(len);
6745 jccb(Assembler::negative, L_carry);
6746 decrementl(len);
6747 jccb(Assembler::negative, L_last_in);
6748
6749 movq(op1, Address(in, len, Address::times_4, 0));
6750 rorq(op1, 32);
6751
6752 subl(offs, 2);
6753 movq(sum, Address(out, offs, Address::times_4, 0));
6754 rorq(sum, 32);
6755
6756 if (UseBMI2Instructions) {
6757 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
6758 }
6759 else {
6760 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
6761 }
6762
6763 // Store back in big endian from little endian
6764 rorq(sum, 0x20);
6765 movq(Address(out, offs, Address::times_4, 0), sum);
6766
6767 testl(len, len);
6768 jccb(Assembler::zero, L_carry);
6769
6770 //Multiply the last in[] entry, if any
6771 bind(L_last_in);
6772 movl(op1, Address(in, 0));
6773 movl(sum, Address(out, offs, Address::times_4, -4));
6774
6775 movl(raxReg, k);
6776 mull(op1); //tmp4 * eax -> edx:eax
6777 addl(sum, carry);
6778 adcl(rdxReg, 0);
6779 addl(sum, raxReg);
6780 adcl(rdxReg, 0);
6781 movl(carry, rdxReg);
6782
6783 movl(Address(out, offs, Address::times_4, -4), sum);
6784
6785 bind(L_carry);
6786 //return tmp5/carry as carry in rax
6787 movl(rax, carry);
6788
6789 bind(L_done);
6790 pop(tmp5);
6791 pop(tmp4);
6792 pop(tmp3);
6793 pop(tmp2);
6794 pop(tmp1);
6795 }
6796 #endif
6797
6798 /**
6799 * Emits code to update CRC-32 with a byte value according to constants in table
6800 *
6801 * @param [in,out]crc Register containing the crc.
6802 * @param [in]val Register containing the byte to fold into the CRC.
6803 * @param [in]table Register containing the table of crc constants.
6804 *
6805 * uint32_t crc;
6806 * val = crc_table[(val ^ crc) & 0xFF];
6807 * crc = val ^ (crc >> 8);
6808 *
6809 */
6810 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) {
6811 xorl(val, crc);
6812 andl(val, 0xFF);
6813 shrl(crc, 8); // unsigned shift
6814 xorl(crc, Address(table, val, Address::times_4, 0));
6815 }
6816
6817 /**
6818 * Fold 128-bit data chunk
6819 */
6820 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset) {
6821 if (UseAVX > 0) {
6822 vpclmulhdq(xtmp, xK, xcrc); // [123:64]
6823 vpclmulldq(xcrc, xK, xcrc); // [63:0]
6824 vpxor(xcrc, xcrc, Address(buf, offset), 0 /* vector_len */);
6825 pxor(xcrc, xtmp);
6826 } else {
6827 movdqa(xtmp, xcrc);
6828 pclmulhdq(xtmp, xK); // [123:64]
6829 pclmulldq(xcrc, xK); // [63:0]
6830 pxor(xcrc, xtmp);
6831 movdqu(xtmp, Address(buf, offset));
6832 pxor(xcrc, xtmp);
6833 }
6834 }
6835
6836 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf) {
6837 if (UseAVX > 0) {
6838 vpclmulhdq(xtmp, xK, xcrc);
6839 vpclmulldq(xcrc, xK, xcrc);
6840 pxor(xcrc, xbuf);
6841 pxor(xcrc, xtmp);
6842 } else {
6843 movdqa(xtmp, xcrc);
6844 pclmulhdq(xtmp, xK);
6845 pclmulldq(xcrc, xK);
6846 pxor(xcrc, xbuf);
6847 pxor(xcrc, xtmp);
6848 }
6849 }
6850
6851 /**
6852 * 8-bit folds to compute 32-bit CRC
6853 *
6854 * uint64_t xcrc;
6855 * timesXtoThe32[xcrc & 0xFF] ^ (xcrc >> 8);
6856 */
6857 void MacroAssembler::fold_8bit_crc32(XMMRegister xcrc, Register table, XMMRegister xtmp, Register tmp) {
6858 movdl(tmp, xcrc);
6859 andl(tmp, 0xFF);
6860 movdl(xtmp, Address(table, tmp, Address::times_4, 0));
6861 psrldq(xcrc, 1); // unsigned shift one byte
6862 pxor(xcrc, xtmp);
6863 }
6864
6865 /**
6866 * uint32_t crc;
6867 * timesXtoThe32[crc & 0xFF] ^ (crc >> 8);
6868 */
6869 void MacroAssembler::fold_8bit_crc32(Register crc, Register table, Register tmp) {
6870 movl(tmp, crc);
6871 andl(tmp, 0xFF);
6872 shrl(crc, 8);
6873 xorl(crc, Address(table, tmp, Address::times_4, 0));
6874 }
6875
6876 /**
6877 * @param crc register containing existing CRC (32-bit)
6878 * @param buf register pointing to input byte buffer (byte*)
6879 * @param len register containing number of bytes
6880 * @param table register that will contain address of CRC table
6881 * @param tmp scratch register
6882 */
6883 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp) {
6884 assert_different_registers(crc, buf, len, table, tmp, rax);
6885
6886 Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned;
6887 Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop;
6888
6889 // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge
6890 // context for the registers used, where all instructions below are using 128-bit mode
6891 // On EVEX without VL and BW, these instructions will all be AVX.
6892 lea(table, ExternalAddress(StubRoutines::crc_table_addr()));
6893 notl(crc); // ~crc
6894 cmpl(len, 16);
6895 jcc(Assembler::less, L_tail);
6896
6897 // Align buffer to 16 bytes
6898 movl(tmp, buf);
6899 andl(tmp, 0xF);
6900 jccb(Assembler::zero, L_aligned);
6901 subl(tmp, 16);
6902 addl(len, tmp);
6903
6904 align(4);
6905 BIND(L_align_loop);
6906 movsbl(rax, Address(buf, 0)); // load byte with sign extension
6907 update_byte_crc32(crc, rax, table);
6908 increment(buf);
6909 incrementl(tmp);
6910 jccb(Assembler::less, L_align_loop);
6911
6912 BIND(L_aligned);
6913 movl(tmp, len); // save
6914 shrl(len, 4);
6915 jcc(Assembler::zero, L_tail_restore);
6916
6917 // Fold crc into first bytes of vector
6918 movdqa(xmm1, Address(buf, 0));
6919 movdl(rax, xmm1);
6920 xorl(crc, rax);
6921 if (VM_Version::supports_sse4_1()) {
6922 pinsrd(xmm1, crc, 0);
6923 } else {
6924 pinsrw(xmm1, crc, 0);
6925 shrl(crc, 16);
6926 pinsrw(xmm1, crc, 1);
6927 }
6928 addptr(buf, 16);
6929 subl(len, 4); // len > 0
6930 jcc(Assembler::less, L_fold_tail);
6931
6932 movdqa(xmm2, Address(buf, 0));
6933 movdqa(xmm3, Address(buf, 16));
6934 movdqa(xmm4, Address(buf, 32));
6935 addptr(buf, 48);
6936 subl(len, 3);
6937 jcc(Assembler::lessEqual, L_fold_512b);
6938
6939 // Fold total 512 bits of polynomial on each iteration,
6940 // 128 bits per each of 4 parallel streams.
6941 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 32));
6942
6943 align32();
6944 BIND(L_fold_512b_loop);
6945 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0);
6946 fold_128bit_crc32(xmm2, xmm0, xmm5, buf, 16);
6947 fold_128bit_crc32(xmm3, xmm0, xmm5, buf, 32);
6948 fold_128bit_crc32(xmm4, xmm0, xmm5, buf, 48);
6949 addptr(buf, 64);
6950 subl(len, 4);
6951 jcc(Assembler::greater, L_fold_512b_loop);
6952
6953 // Fold 512 bits to 128 bits.
6954 BIND(L_fold_512b);
6955 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16));
6956 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm2);
6957 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm3);
6958 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm4);
6959
6960 // Fold the rest of 128 bits data chunks
6961 BIND(L_fold_tail);
6962 addl(len, 3);
6963 jccb(Assembler::lessEqual, L_fold_128b);
6964 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16));
6965
6966 BIND(L_fold_tail_loop);
6967 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0);
6968 addptr(buf, 16);
6969 decrementl(len);
6970 jccb(Assembler::greater, L_fold_tail_loop);
6971
6972 // Fold 128 bits in xmm1 down into 32 bits in crc register.
6973 BIND(L_fold_128b);
6974 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr()));
6975 if (UseAVX > 0) {
6976 vpclmulqdq(xmm2, xmm0, xmm1, 0x1);
6977 vpand(xmm3, xmm0, xmm2, 0 /* vector_len */);
6978 vpclmulqdq(xmm0, xmm0, xmm3, 0x1);
6979 } else {
6980 movdqa(xmm2, xmm0);
6981 pclmulqdq(xmm2, xmm1, 0x1);
6982 movdqa(xmm3, xmm0);
6983 pand(xmm3, xmm2);
6984 pclmulqdq(xmm0, xmm3, 0x1);
6985 }
6986 psrldq(xmm1, 8);
6987 psrldq(xmm2, 4);
6988 pxor(xmm0, xmm1);
6989 pxor(xmm0, xmm2);
6990
6991 // 8 8-bit folds to compute 32-bit CRC.
6992 for (int j = 0; j < 4; j++) {
6993 fold_8bit_crc32(xmm0, table, xmm1, rax);
6994 }
6995 movdl(crc, xmm0); // mov 32 bits to general register
6996 for (int j = 0; j < 4; j++) {
6997 fold_8bit_crc32(crc, table, rax);
6998 }
6999
7000 BIND(L_tail_restore);
7001 movl(len, tmp); // restore
7002 BIND(L_tail);
7003 andl(len, 0xf);
7004 jccb(Assembler::zero, L_exit);
7005
7006 // Fold the rest of bytes
7007 align(4);
7008 BIND(L_tail_loop);
7009 movsbl(rax, Address(buf, 0)); // load byte with sign extension
7010 update_byte_crc32(crc, rax, table);
7011 increment(buf);
7012 decrementl(len);
7013 jccb(Assembler::greater, L_tail_loop);
7014
7015 BIND(L_exit);
7016 notl(crc); // ~c
7017 }
7018
7019 #ifdef _LP64
7020 // Helper function for AVX 512 CRC32
7021 // Fold 512-bit data chunks
7022 void MacroAssembler::fold512bit_crc32_avx512(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf,
7023 Register pos, int offset) {
7024 evmovdquq(xmm3, Address(buf, pos, Address::times_1, offset), Assembler::AVX_512bit);
7025 evpclmulqdq(xtmp, xcrc, xK, 0x10, Assembler::AVX_512bit); // [123:64]
7026 evpclmulqdq(xmm2, xcrc, xK, 0x01, Assembler::AVX_512bit); // [63:0]
7027 evpxorq(xcrc, xtmp, xmm2, Assembler::AVX_512bit /* vector_len */);
7028 evpxorq(xcrc, xcrc, xmm3, Assembler::AVX_512bit /* vector_len */);
7029 }
7030
7031 // Helper function for AVX 512 CRC32
7032 // Compute CRC32 for < 256B buffers
7033 void MacroAssembler::kernel_crc32_avx512_256B(Register crc, Register buf, Register len, Register key, Register pos,
7034 Register tmp1, Register tmp2, Label& L_barrett, Label& L_16B_reduction_loop,
7035 Label& L_get_last_two_xmms, Label& L_128_done, Label& L_cleanup) {
7036
7037 Label L_less_than_32, L_exact_16_left, L_less_than_16_left;
7038 Label L_less_than_8_left, L_less_than_4_left, L_less_than_2_left, L_zero_left;
7039 Label L_only_less_than_4, L_only_less_than_3, L_only_less_than_2;
7040
7041 // check if there is enough buffer to be able to fold 16B at a time
7042 cmpl(len, 32);
7043 jcc(Assembler::less, L_less_than_32);
7044
7045 // if there is, load the constants
7046 movdqu(xmm10, Address(key, 1 * 16)); //rk1 and rk2 in xmm10
7047 movdl(xmm0, crc); // get the initial crc value
7048 movdqu(xmm7, Address(buf, pos, Address::times_1, 0 * 16)); //load the plaintext
7049 pxor(xmm7, xmm0);
7050
7051 // update the buffer pointer
7052 addl(pos, 16);
7053 //update the counter.subtract 32 instead of 16 to save one instruction from the loop
7054 subl(len, 32);
7055 jmp(L_16B_reduction_loop);
7056
7057 bind(L_less_than_32);
7058 //mov initial crc to the return value. this is necessary for zero - length buffers.
7059 movl(rax, crc);
7060 testl(len, len);
7061 jcc(Assembler::equal, L_cleanup);
7062
7063 movdl(xmm0, crc); //get the initial crc value
7064
7065 cmpl(len, 16);
7066 jcc(Assembler::equal, L_exact_16_left);
7067 jcc(Assembler::less, L_less_than_16_left);
7068
7069 movdqu(xmm7, Address(buf, pos, Address::times_1, 0 * 16)); //load the plaintext
7070 pxor(xmm7, xmm0); //xor the initial crc value
7071 addl(pos, 16);
7072 subl(len, 16);
7073 movdqu(xmm10, Address(key, 1 * 16)); // rk1 and rk2 in xmm10
7074 jmp(L_get_last_two_xmms);
7075
7076 bind(L_less_than_16_left);
7077 //use stack space to load data less than 16 bytes, zero - out the 16B in memory first.
7078 pxor(xmm1, xmm1);
7079 movptr(tmp1, rsp);
7080 movdqu(Address(tmp1, 0 * 16), xmm1);
7081
7082 cmpl(len, 4);
7083 jcc(Assembler::less, L_only_less_than_4);
7084
7085 //backup the counter value
7086 movl(tmp2, len);
7087 cmpl(len, 8);
7088 jcc(Assembler::less, L_less_than_8_left);
7089
7090 //load 8 Bytes
7091 movq(rax, Address(buf, pos, Address::times_1, 0 * 16));
7092 movq(Address(tmp1, 0 * 16), rax);
7093 addptr(tmp1, 8);
7094 subl(len, 8);
7095 addl(pos, 8);
7096
7097 bind(L_less_than_8_left);
7098 cmpl(len, 4);
7099 jcc(Assembler::less, L_less_than_4_left);
7100
7101 //load 4 Bytes
7102 movl(rax, Address(buf, pos, Address::times_1, 0));
7103 movl(Address(tmp1, 0 * 16), rax);
7104 addptr(tmp1, 4);
7105 subl(len, 4);
7106 addl(pos, 4);
7107
7108 bind(L_less_than_4_left);
7109 cmpl(len, 2);
7110 jcc(Assembler::less, L_less_than_2_left);
7111
7112 // load 2 Bytes
7113 movw(rax, Address(buf, pos, Address::times_1, 0));
7114 movl(Address(tmp1, 0 * 16), rax);
7115 addptr(tmp1, 2);
7116 subl(len, 2);
7117 addl(pos, 2);
7118
7119 bind(L_less_than_2_left);
7120 cmpl(len, 1);
7121 jcc(Assembler::less, L_zero_left);
7122
7123 // load 1 Byte
7124 movb(rax, Address(buf, pos, Address::times_1, 0));
7125 movb(Address(tmp1, 0 * 16), rax);
7126
7127 bind(L_zero_left);
7128 movdqu(xmm7, Address(rsp, 0));
7129 pxor(xmm7, xmm0); //xor the initial crc value
7130
7131 lea(rax, ExternalAddress(StubRoutines::x86::shuf_table_crc32_avx512_addr()));
7132 movdqu(xmm0, Address(rax, tmp2));
7133 pshufb(xmm7, xmm0);
7134 jmp(L_128_done);
7135
7136 bind(L_exact_16_left);
7137 movdqu(xmm7, Address(buf, pos, Address::times_1, 0));
7138 pxor(xmm7, xmm0); //xor the initial crc value
7139 jmp(L_128_done);
7140
7141 bind(L_only_less_than_4);
7142 cmpl(len, 3);
7143 jcc(Assembler::less, L_only_less_than_3);
7144
7145 // load 3 Bytes
7146 movb(rax, Address(buf, pos, Address::times_1, 0));
7147 movb(Address(tmp1, 0), rax);
7148
7149 movb(rax, Address(buf, pos, Address::times_1, 1));
7150 movb(Address(tmp1, 1), rax);
7151
7152 movb(rax, Address(buf, pos, Address::times_1, 2));
7153 movb(Address(tmp1, 2), rax);
7154
7155 movdqu(xmm7, Address(rsp, 0));
7156 pxor(xmm7, xmm0); //xor the initial crc value
7157
7158 pslldq(xmm7, 0x5);
7159 jmp(L_barrett);
7160 bind(L_only_less_than_3);
7161 cmpl(len, 2);
7162 jcc(Assembler::less, L_only_less_than_2);
7163
7164 // load 2 Bytes
7165 movb(rax, Address(buf, pos, Address::times_1, 0));
7166 movb(Address(tmp1, 0), rax);
7167
7168 movb(rax, Address(buf, pos, Address::times_1, 1));
7169 movb(Address(tmp1, 1), rax);
7170
7171 movdqu(xmm7, Address(rsp, 0));
7172 pxor(xmm7, xmm0); //xor the initial crc value
7173
7174 pslldq(xmm7, 0x6);
7175 jmp(L_barrett);
7176
7177 bind(L_only_less_than_2);
7178 //load 1 Byte
7179 movb(rax, Address(buf, pos, Address::times_1, 0));
7180 movb(Address(tmp1, 0), rax);
7181
7182 movdqu(xmm7, Address(rsp, 0));
7183 pxor(xmm7, xmm0); //xor the initial crc value
7184
7185 pslldq(xmm7, 0x7);
7186 }
7187
7188 /**
7189 * Compute CRC32 using AVX512 instructions
7190 * param crc register containing existing CRC (32-bit)
7191 * param buf register pointing to input byte buffer (byte*)
7192 * param len register containing number of bytes
7193 * param tmp1 scratch register
7194 * param tmp2 scratch register
7195 * return rax result register
7196 */
7197 void MacroAssembler::kernel_crc32_avx512(Register crc, Register buf, Register len, Register key, Register tmp1, Register tmp2) {
7198 assert_different_registers(crc, buf, len, key, tmp1, tmp2, rax);
7199
7200 Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned;
7201 Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop;
7202 Label L_less_than_256, L_fold_128_B_loop, L_fold_256_B_loop;
7203 Label L_fold_128_B_register, L_final_reduction_for_128, L_16B_reduction_loop;
7204 Label L_128_done, L_get_last_two_xmms, L_barrett, L_cleanup;
7205
7206 const Register pos = r12;
7207 push(r12);
7208 subptr(rsp, 16 * 2 + 8);
7209
7210 // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge
7211 // context for the registers used, where all instructions below are using 128-bit mode
7212 // On EVEX without VL and BW, these instructions will all be AVX.
7213 lea(key, ExternalAddress(StubRoutines::x86::crc_table_avx512_addr()));
7214 notl(crc);
7215 movl(pos, 0);
7216
7217 // check if smaller than 256B
7218 cmpl(len, 256);
7219 jcc(Assembler::less, L_less_than_256);
7220
7221 // load the initial crc value
7222 movdl(xmm10, crc);
7223
7224 // receive the initial 64B data, xor the initial crc value
7225 evmovdquq(xmm0, Address(buf, pos, Address::times_1, 0 * 64), Assembler::AVX_512bit);
7226 evmovdquq(xmm4, Address(buf, pos, Address::times_1, 1 * 64), Assembler::AVX_512bit);
7227 evpxorq(xmm0, xmm0, xmm10, Assembler::AVX_512bit);
7228 evbroadcasti32x4(xmm10, Address(key, 2 * 16), Assembler::AVX_512bit); //zmm10 has rk3 and rk4
7229
7230 subl(len, 256);
7231 cmpl(len, 256);
7232 jcc(Assembler::less, L_fold_128_B_loop);
7233
7234 evmovdquq(xmm7, Address(buf, pos, Address::times_1, 2 * 64), Assembler::AVX_512bit);
7235 evmovdquq(xmm8, Address(buf, pos, Address::times_1, 3 * 64), Assembler::AVX_512bit);
7236 evbroadcasti32x4(xmm16, Address(key, 0 * 16), Assembler::AVX_512bit); //zmm16 has rk-1 and rk-2
7237 subl(len, 256);
7238
7239 bind(L_fold_256_B_loop);
7240 addl(pos, 256);
7241 fold512bit_crc32_avx512(xmm0, xmm16, xmm1, buf, pos, 0 * 64);
7242 fold512bit_crc32_avx512(xmm4, xmm16, xmm1, buf, pos, 1 * 64);
7243 fold512bit_crc32_avx512(xmm7, xmm16, xmm1, buf, pos, 2 * 64);
7244 fold512bit_crc32_avx512(xmm8, xmm16, xmm1, buf, pos, 3 * 64);
7245
7246 subl(len, 256);
7247 jcc(Assembler::greaterEqual, L_fold_256_B_loop);
7248
7249 // Fold 256 into 128
7250 addl(pos, 256);
7251 evpclmulqdq(xmm1, xmm0, xmm10, 0x01, Assembler::AVX_512bit);
7252 evpclmulqdq(xmm2, xmm0, xmm10, 0x10, Assembler::AVX_512bit);
7253 vpternlogq(xmm7, 0x96, xmm1, xmm2, Assembler::AVX_512bit); // xor ABC
7254
7255 evpclmulqdq(xmm5, xmm4, xmm10, 0x01, Assembler::AVX_512bit);
7256 evpclmulqdq(xmm6, xmm4, xmm10, 0x10, Assembler::AVX_512bit);
7257 vpternlogq(xmm8, 0x96, xmm5, xmm6, Assembler::AVX_512bit); // xor ABC
7258
7259 evmovdquq(xmm0, xmm7, Assembler::AVX_512bit);
7260 evmovdquq(xmm4, xmm8, Assembler::AVX_512bit);
7261
7262 addl(len, 128);
7263 jmp(L_fold_128_B_register);
7264
7265 // at this section of the code, there is 128 * x + y(0 <= y<128) bytes of buffer.The fold_128_B_loop
7266 // loop will fold 128B at a time until we have 128 + y Bytes of buffer
7267
7268 // fold 128B at a time.This section of the code folds 8 xmm registers in parallel
7269 bind(L_fold_128_B_loop);
7270 addl(pos, 128);
7271 fold512bit_crc32_avx512(xmm0, xmm10, xmm1, buf, pos, 0 * 64);
7272 fold512bit_crc32_avx512(xmm4, xmm10, xmm1, buf, pos, 1 * 64);
7273
7274 subl(len, 128);
7275 jcc(Assembler::greaterEqual, L_fold_128_B_loop);
7276
7277 addl(pos, 128);
7278
7279 // at this point, the buffer pointer is pointing at the last y Bytes of the buffer, where 0 <= y < 128
7280 // the 128B of folded data is in 8 of the xmm registers : xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7
7281 bind(L_fold_128_B_register);
7282 evmovdquq(xmm16, Address(key, 5 * 16), Assembler::AVX_512bit); // multiply by rk9-rk16
7283 evmovdquq(xmm11, Address(key, 9 * 16), Assembler::AVX_512bit); // multiply by rk17-rk20, rk1,rk2, 0,0
7284 evpclmulqdq(xmm1, xmm0, xmm16, 0x01, Assembler::AVX_512bit);
7285 evpclmulqdq(xmm2, xmm0, xmm16, 0x10, Assembler::AVX_512bit);
7286 // save last that has no multiplicand
7287 vextracti64x2(xmm7, xmm4, 3);
7288
7289 evpclmulqdq(xmm5, xmm4, xmm11, 0x01, Assembler::AVX_512bit);
7290 evpclmulqdq(xmm6, xmm4, xmm11, 0x10, Assembler::AVX_512bit);
7291 // Needed later in reduction loop
7292 movdqu(xmm10, Address(key, 1 * 16));
7293 vpternlogq(xmm1, 0x96, xmm2, xmm5, Assembler::AVX_512bit); // xor ABC
7294 vpternlogq(xmm1, 0x96, xmm6, xmm7, Assembler::AVX_512bit); // xor ABC
7295
7296 // Swap 1,0,3,2 - 01 00 11 10
7297 evshufi64x2(xmm8, xmm1, xmm1, 0x4e, Assembler::AVX_512bit);
7298 evpxorq(xmm8, xmm8, xmm1, Assembler::AVX_256bit);
7299 vextracti128(xmm5, xmm8, 1);
7300 evpxorq(xmm7, xmm5, xmm8, Assembler::AVX_128bit);
7301
7302 // instead of 128, we add 128 - 16 to the loop counter to save 1 instruction from the loop
7303 // instead of a cmp instruction, we use the negative flag with the jl instruction
7304 addl(len, 128 - 16);
7305 jcc(Assembler::less, L_final_reduction_for_128);
7306
7307 bind(L_16B_reduction_loop);
7308 vpclmulqdq(xmm8, xmm7, xmm10, 0x1);
7309 vpclmulqdq(xmm7, xmm7, xmm10, 0x10);
7310 vpxor(xmm7, xmm7, xmm8, Assembler::AVX_128bit);
7311 movdqu(xmm0, Address(buf, pos, Address::times_1, 0 * 16));
7312 vpxor(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
7313 addl(pos, 16);
7314 subl(len, 16);
7315 jcc(Assembler::greaterEqual, L_16B_reduction_loop);
7316
7317 bind(L_final_reduction_for_128);
7318 addl(len, 16);
7319 jcc(Assembler::equal, L_128_done);
7320
7321 bind(L_get_last_two_xmms);
7322 movdqu(xmm2, xmm7);
7323 addl(pos, len);
7324 movdqu(xmm1, Address(buf, pos, Address::times_1, -16));
7325 subl(pos, len);
7326
7327 // get rid of the extra data that was loaded before
7328 // load the shift constant
7329 lea(rax, ExternalAddress(StubRoutines::x86::shuf_table_crc32_avx512_addr()));
7330 movdqu(xmm0, Address(rax, len));
7331 addl(rax, len);
7332
7333 vpshufb(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
7334 //Change mask to 512
7335 vpxor(xmm0, xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_avx512_addr() + 2 * 16), Assembler::AVX_128bit, tmp2);
7336 vpshufb(xmm2, xmm2, xmm0, Assembler::AVX_128bit);
7337
7338 blendvpb(xmm2, xmm2, xmm1, xmm0, Assembler::AVX_128bit);
7339 vpclmulqdq(xmm8, xmm7, xmm10, 0x1);
7340 vpclmulqdq(xmm7, xmm7, xmm10, 0x10);
7341 vpxor(xmm7, xmm7, xmm8, Assembler::AVX_128bit);
7342 vpxor(xmm7, xmm7, xmm2, Assembler::AVX_128bit);
7343
7344 bind(L_128_done);
7345 // compute crc of a 128-bit value
7346 movdqu(xmm10, Address(key, 3 * 16));
7347 movdqu(xmm0, xmm7);
7348
7349 // 64b fold
7350 vpclmulqdq(xmm7, xmm7, xmm10, 0x0);
7351 vpsrldq(xmm0, xmm0, 0x8, Assembler::AVX_128bit);
7352 vpxor(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
7353
7354 // 32b fold
7355 movdqu(xmm0, xmm7);
7356 vpslldq(xmm7, xmm7, 0x4, Assembler::AVX_128bit);
7357 vpclmulqdq(xmm7, xmm7, xmm10, 0x10);
7358 vpxor(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
7359 jmp(L_barrett);
7360
7361 bind(L_less_than_256);
7362 kernel_crc32_avx512_256B(crc, buf, len, key, pos, tmp1, tmp2, L_barrett, L_16B_reduction_loop, L_get_last_two_xmms, L_128_done, L_cleanup);
7363
7364 //barrett reduction
7365 bind(L_barrett);
7366 vpand(xmm7, xmm7, ExternalAddress(StubRoutines::x86::crc_by128_masks_avx512_addr() + 1 * 16), Assembler::AVX_128bit, tmp2);
7367 movdqu(xmm1, xmm7);
7368 movdqu(xmm2, xmm7);
7369 movdqu(xmm10, Address(key, 4 * 16));
7370
7371 pclmulqdq(xmm7, xmm10, 0x0);
7372 pxor(xmm7, xmm2);
7373 vpand(xmm7, xmm7, ExternalAddress(StubRoutines::x86::crc_by128_masks_avx512_addr()), Assembler::AVX_128bit, tmp2);
7374 movdqu(xmm2, xmm7);
7375 pclmulqdq(xmm7, xmm10, 0x10);
7376 pxor(xmm7, xmm2);
7377 pxor(xmm7, xmm1);
7378 pextrd(crc, xmm7, 2);
7379
7380 bind(L_cleanup);
7381 notl(crc); // ~c
7382 addptr(rsp, 16 * 2 + 8);
7383 pop(r12);
7384 }
7385
7386 // S. Gueron / Information Processing Letters 112 (2012) 184
7387 // Algorithm 4: Computing carry-less multiplication using a precomputed lookup table.
7388 // Input: A 32 bit value B = [byte3, byte2, byte1, byte0].
7389 // Output: the 64-bit carry-less product of B * CONST
7390 void MacroAssembler::crc32c_ipl_alg4(Register in, uint32_t n,
7391 Register tmp1, Register tmp2, Register tmp3) {
7392 lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr()));
7393 if (n > 0) {
7394 addq(tmp3, n * 256 * 8);
7395 }
7396 // Q1 = TABLEExt[n][B & 0xFF];
7397 movl(tmp1, in);
7398 andl(tmp1, 0x000000FF);
7399 shll(tmp1, 3);
7400 addq(tmp1, tmp3);
7401 movq(tmp1, Address(tmp1, 0));
7402
7403 // Q2 = TABLEExt[n][B >> 8 & 0xFF];
7404 movl(tmp2, in);
7405 shrl(tmp2, 8);
7406 andl(tmp2, 0x000000FF);
7407 shll(tmp2, 3);
7408 addq(tmp2, tmp3);
7409 movq(tmp2, Address(tmp2, 0));
7410
7411 shlq(tmp2, 8);
7412 xorq(tmp1, tmp2);
7413
7414 // Q3 = TABLEExt[n][B >> 16 & 0xFF];
7415 movl(tmp2, in);
7416 shrl(tmp2, 16);
7417 andl(tmp2, 0x000000FF);
7418 shll(tmp2, 3);
7419 addq(tmp2, tmp3);
7420 movq(tmp2, Address(tmp2, 0));
7421
7422 shlq(tmp2, 16);
7423 xorq(tmp1, tmp2);
7424
7425 // Q4 = TABLEExt[n][B >> 24 & 0xFF];
7426 shrl(in, 24);
7427 andl(in, 0x000000FF);
7428 shll(in, 3);
7429 addq(in, tmp3);
7430 movq(in, Address(in, 0));
7431
7432 shlq(in, 24);
7433 xorq(in, tmp1);
7434 // return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24;
7435 }
7436
7437 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1,
7438 Register in_out,
7439 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
7440 XMMRegister w_xtmp2,
7441 Register tmp1,
7442 Register n_tmp2, Register n_tmp3) {
7443 if (is_pclmulqdq_supported) {
7444 movdl(w_xtmp1, in_out); // modified blindly
7445
7446 movl(tmp1, const_or_pre_comp_const_index);
7447 movdl(w_xtmp2, tmp1);
7448 pclmulqdq(w_xtmp1, w_xtmp2, 0);
7449
7450 movdq(in_out, w_xtmp1);
7451 } else {
7452 crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3);
7453 }
7454 }
7455
7456 // Recombination Alternative 2: No bit-reflections
7457 // T1 = (CRC_A * U1) << 1
7458 // T2 = (CRC_B * U2) << 1
7459 // C1 = T1 >> 32
7460 // C2 = T2 >> 32
7461 // T1 = T1 & 0xFFFFFFFF
7462 // T2 = T2 & 0xFFFFFFFF
7463 // T1 = CRC32(0, T1)
7464 // T2 = CRC32(0, T2)
7465 // C1 = C1 ^ T1
7466 // C2 = C2 ^ T2
7467 // CRC = C1 ^ C2 ^ CRC_C
7468 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
7469 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
7470 Register tmp1, Register tmp2,
7471 Register n_tmp3) {
7472 crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
7473 crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
7474 shlq(in_out, 1);
7475 movl(tmp1, in_out);
7476 shrq(in_out, 32);
7477 xorl(tmp2, tmp2);
7478 crc32(tmp2, tmp1, 4);
7479 xorl(in_out, tmp2); // we don't care about upper 32 bit contents here
7480 shlq(in1, 1);
7481 movl(tmp1, in1);
7482 shrq(in1, 32);
7483 xorl(tmp2, tmp2);
7484 crc32(tmp2, tmp1, 4);
7485 xorl(in1, tmp2);
7486 xorl(in_out, in1);
7487 xorl(in_out, in2);
7488 }
7489
7490 // Set N to predefined value
7491 // Subtract from a lenght of a buffer
7492 // execute in a loop:
7493 // CRC_A = 0xFFFFFFFF, CRC_B = 0, CRC_C = 0
7494 // for i = 1 to N do
7495 // CRC_A = CRC32(CRC_A, A[i])
7496 // CRC_B = CRC32(CRC_B, B[i])
7497 // CRC_C = CRC32(CRC_C, C[i])
7498 // end for
7499 // Recombine
7500 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
7501 Register in_out1, Register in_out2, Register in_out3,
7502 Register tmp1, Register tmp2, Register tmp3,
7503 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
7504 Register tmp4, Register tmp5,
7505 Register n_tmp6) {
7506 Label L_processPartitions;
7507 Label L_processPartition;
7508 Label L_exit;
7509
7510 bind(L_processPartitions);
7511 cmpl(in_out1, 3 * size);
7512 jcc(Assembler::less, L_exit);
7513 xorl(tmp1, tmp1);
7514 xorl(tmp2, tmp2);
7515 movq(tmp3, in_out2);
7516 addq(tmp3, size);
7517
7518 bind(L_processPartition);
7519 crc32(in_out3, Address(in_out2, 0), 8);
7520 crc32(tmp1, Address(in_out2, size), 8);
7521 crc32(tmp2, Address(in_out2, size * 2), 8);
7522 addq(in_out2, 8);
7523 cmpq(in_out2, tmp3);
7524 jcc(Assembler::less, L_processPartition);
7525 crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2,
7526 w_xtmp1, w_xtmp2, w_xtmp3,
7527 tmp4, tmp5,
7528 n_tmp6);
7529 addq(in_out2, 2 * size);
7530 subl(in_out1, 3 * size);
7531 jmp(L_processPartitions);
7532
7533 bind(L_exit);
7534 }
7535 #else
7536 void MacroAssembler::crc32c_ipl_alg4(Register in_out, uint32_t n,
7537 Register tmp1, Register tmp2, Register tmp3,
7538 XMMRegister xtmp1, XMMRegister xtmp2) {
7539 lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr()));
7540 if (n > 0) {
7541 addl(tmp3, n * 256 * 8);
7542 }
7543 // Q1 = TABLEExt[n][B & 0xFF];
7544 movl(tmp1, in_out);
7545 andl(tmp1, 0x000000FF);
7546 shll(tmp1, 3);
7547 addl(tmp1, tmp3);
7548 movq(xtmp1, Address(tmp1, 0));
7549
7550 // Q2 = TABLEExt[n][B >> 8 & 0xFF];
7551 movl(tmp2, in_out);
7552 shrl(tmp2, 8);
7553 andl(tmp2, 0x000000FF);
7554 shll(tmp2, 3);
7555 addl(tmp2, tmp3);
7556 movq(xtmp2, Address(tmp2, 0));
7557
7558 psllq(xtmp2, 8);
7559 pxor(xtmp1, xtmp2);
7560
7561 // Q3 = TABLEExt[n][B >> 16 & 0xFF];
7562 movl(tmp2, in_out);
7563 shrl(tmp2, 16);
7564 andl(tmp2, 0x000000FF);
7565 shll(tmp2, 3);
7566 addl(tmp2, tmp3);
7567 movq(xtmp2, Address(tmp2, 0));
7568
7569 psllq(xtmp2, 16);
7570 pxor(xtmp1, xtmp2);
7571
7572 // Q4 = TABLEExt[n][B >> 24 & 0xFF];
7573 shrl(in_out, 24);
7574 andl(in_out, 0x000000FF);
7575 shll(in_out, 3);
7576 addl(in_out, tmp3);
7577 movq(xtmp2, Address(in_out, 0));
7578
7579 psllq(xtmp2, 24);
7580 pxor(xtmp1, xtmp2); // Result in CXMM
7581 // return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24;
7582 }
7583
7584 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1,
7585 Register in_out,
7586 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
7587 XMMRegister w_xtmp2,
7588 Register tmp1,
7589 Register n_tmp2, Register n_tmp3) {
7590 if (is_pclmulqdq_supported) {
7591 movdl(w_xtmp1, in_out);
7592
7593 movl(tmp1, const_or_pre_comp_const_index);
7594 movdl(w_xtmp2, tmp1);
7595 pclmulqdq(w_xtmp1, w_xtmp2, 0);
7596 // Keep result in XMM since GPR is 32 bit in length
7597 } else {
7598 crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3, w_xtmp1, w_xtmp2);
7599 }
7600 }
7601
7602 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
7603 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
7604 Register tmp1, Register tmp2,
7605 Register n_tmp3) {
7606 crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
7607 crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
7608
7609 psllq(w_xtmp1, 1);
7610 movdl(tmp1, w_xtmp1);
7611 psrlq(w_xtmp1, 32);
7612 movdl(in_out, w_xtmp1);
7613
7614 xorl(tmp2, tmp2);
7615 crc32(tmp2, tmp1, 4);
7616 xorl(in_out, tmp2);
7617
7618 psllq(w_xtmp2, 1);
7619 movdl(tmp1, w_xtmp2);
7620 psrlq(w_xtmp2, 32);
7621 movdl(in1, w_xtmp2);
7622
7623 xorl(tmp2, tmp2);
7624 crc32(tmp2, tmp1, 4);
7625 xorl(in1, tmp2);
7626 xorl(in_out, in1);
7627 xorl(in_out, in2);
7628 }
7629
7630 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
7631 Register in_out1, Register in_out2, Register in_out3,
7632 Register tmp1, Register tmp2, Register tmp3,
7633 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
7634 Register tmp4, Register tmp5,
7635 Register n_tmp6) {
7636 Label L_processPartitions;
7637 Label L_processPartition;
7638 Label L_exit;
7639
7640 bind(L_processPartitions);
7641 cmpl(in_out1, 3 * size);
7642 jcc(Assembler::less, L_exit);
7643 xorl(tmp1, tmp1);
7644 xorl(tmp2, tmp2);
7645 movl(tmp3, in_out2);
7646 addl(tmp3, size);
7647
7648 bind(L_processPartition);
7649 crc32(in_out3, Address(in_out2, 0), 4);
7650 crc32(tmp1, Address(in_out2, size), 4);
7651 crc32(tmp2, Address(in_out2, size*2), 4);
7652 crc32(in_out3, Address(in_out2, 0+4), 4);
7653 crc32(tmp1, Address(in_out2, size+4), 4);
7654 crc32(tmp2, Address(in_out2, size*2+4), 4);
7655 addl(in_out2, 8);
7656 cmpl(in_out2, tmp3);
7657 jcc(Assembler::less, L_processPartition);
7658
7659 push(tmp3);
7660 push(in_out1);
7661 push(in_out2);
7662 tmp4 = tmp3;
7663 tmp5 = in_out1;
7664 n_tmp6 = in_out2;
7665
7666 crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2,
7667 w_xtmp1, w_xtmp2, w_xtmp3,
7668 tmp4, tmp5,
7669 n_tmp6);
7670
7671 pop(in_out2);
7672 pop(in_out1);
7673 pop(tmp3);
7674
7675 addl(in_out2, 2 * size);
7676 subl(in_out1, 3 * size);
7677 jmp(L_processPartitions);
7678
7679 bind(L_exit);
7680 }
7681 #endif //LP64
7682
7683 #ifdef _LP64
7684 // Algorithm 2: Pipelined usage of the CRC32 instruction.
7685 // Input: A buffer I of L bytes.
7686 // Output: the CRC32C value of the buffer.
7687 // Notations:
7688 // Write L = 24N + r, with N = floor (L/24).
7689 // r = L mod 24 (0 <= r < 24).
7690 // Consider I as the concatenation of A|B|C|R, where A, B, C, each,
7691 // N quadwords, and R consists of r bytes.
7692 // A[j] = I [8j+7:8j], j= 0, 1, ..., N-1
7693 // B[j] = I [N + 8j+7:N + 8j], j= 0, 1, ..., N-1
7694 // C[j] = I [2N + 8j+7:2N + 8j], j= 0, 1, ..., N-1
7695 // if r > 0 R[j] = I [3N +j], j= 0, 1, ...,r-1
7696 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
7697 Register tmp1, Register tmp2, Register tmp3,
7698 Register tmp4, Register tmp5, Register tmp6,
7699 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
7700 bool is_pclmulqdq_supported) {
7701 uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS];
7702 Label L_wordByWord;
7703 Label L_byteByByteProlog;
7704 Label L_byteByByte;
7705 Label L_exit;
7706
7707 if (is_pclmulqdq_supported ) {
7708 const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::_crc32c_table_addr;
7709 const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::_crc32c_table_addr+1);
7710
7711 const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 2);
7712 const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 3);
7713
7714 const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 4);
7715 const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 5);
7716 assert((CRC32C_NUM_PRECOMPUTED_CONSTANTS - 1 ) == 5, "Checking whether you declared all of the constants based on the number of \"chunks\"");
7717 } else {
7718 const_or_pre_comp_const_index[0] = 1;
7719 const_or_pre_comp_const_index[1] = 0;
7720
7721 const_or_pre_comp_const_index[2] = 3;
7722 const_or_pre_comp_const_index[3] = 2;
7723
7724 const_or_pre_comp_const_index[4] = 5;
7725 const_or_pre_comp_const_index[5] = 4;
7726 }
7727 crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported,
7728 in2, in1, in_out,
7729 tmp1, tmp2, tmp3,
7730 w_xtmp1, w_xtmp2, w_xtmp3,
7731 tmp4, tmp5,
7732 tmp6);
7733 crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported,
7734 in2, in1, in_out,
7735 tmp1, tmp2, tmp3,
7736 w_xtmp1, w_xtmp2, w_xtmp3,
7737 tmp4, tmp5,
7738 tmp6);
7739 crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported,
7740 in2, in1, in_out,
7741 tmp1, tmp2, tmp3,
7742 w_xtmp1, w_xtmp2, w_xtmp3,
7743 tmp4, tmp5,
7744 tmp6);
7745 movl(tmp1, in2);
7746 andl(tmp1, 0x00000007);
7747 negl(tmp1);
7748 addl(tmp1, in2);
7749 addq(tmp1, in1);
7750
7751 BIND(L_wordByWord);
7752 cmpq(in1, tmp1);
7753 jcc(Assembler::greaterEqual, L_byteByByteProlog);
7754 crc32(in_out, Address(in1, 0), 4);
7755 addq(in1, 4);
7756 jmp(L_wordByWord);
7757
7758 BIND(L_byteByByteProlog);
7759 andl(in2, 0x00000007);
7760 movl(tmp2, 1);
7761
7762 BIND(L_byteByByte);
7763 cmpl(tmp2, in2);
7764 jccb(Assembler::greater, L_exit);
7765 crc32(in_out, Address(in1, 0), 1);
7766 incq(in1);
7767 incl(tmp2);
7768 jmp(L_byteByByte);
7769
7770 BIND(L_exit);
7771 }
7772 #else
7773 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
7774 Register tmp1, Register tmp2, Register tmp3,
7775 Register tmp4, Register tmp5, Register tmp6,
7776 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
7777 bool is_pclmulqdq_supported) {
7778 uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS];
7779 Label L_wordByWord;
7780 Label L_byteByByteProlog;
7781 Label L_byteByByte;
7782 Label L_exit;
7783
7784 if (is_pclmulqdq_supported) {
7785 const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::_crc32c_table_addr;
7786 const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 1);
7787
7788 const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 2);
7789 const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 3);
7790
7791 const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 4);
7792 const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 5);
7793 } else {
7794 const_or_pre_comp_const_index[0] = 1;
7795 const_or_pre_comp_const_index[1] = 0;
7796
7797 const_or_pre_comp_const_index[2] = 3;
7798 const_or_pre_comp_const_index[3] = 2;
7799
7800 const_or_pre_comp_const_index[4] = 5;
7801 const_or_pre_comp_const_index[5] = 4;
7802 }
7803 crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported,
7804 in2, in1, in_out,
7805 tmp1, tmp2, tmp3,
7806 w_xtmp1, w_xtmp2, w_xtmp3,
7807 tmp4, tmp5,
7808 tmp6);
7809 crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported,
7810 in2, in1, in_out,
7811 tmp1, tmp2, tmp3,
7812 w_xtmp1, w_xtmp2, w_xtmp3,
7813 tmp4, tmp5,
7814 tmp6);
7815 crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported,
7816 in2, in1, in_out,
7817 tmp1, tmp2, tmp3,
7818 w_xtmp1, w_xtmp2, w_xtmp3,
7819 tmp4, tmp5,
7820 tmp6);
7821 movl(tmp1, in2);
7822 andl(tmp1, 0x00000007);
7823 negl(tmp1);
7824 addl(tmp1, in2);
7825 addl(tmp1, in1);
7826
7827 BIND(L_wordByWord);
7828 cmpl(in1, tmp1);
7829 jcc(Assembler::greaterEqual, L_byteByByteProlog);
7830 crc32(in_out, Address(in1,0), 4);
7831 addl(in1, 4);
7832 jmp(L_wordByWord);
7833
7834 BIND(L_byteByByteProlog);
7835 andl(in2, 0x00000007);
7836 movl(tmp2, 1);
7837
7838 BIND(L_byteByByte);
7839 cmpl(tmp2, in2);
7840 jccb(Assembler::greater, L_exit);
7841 movb(tmp1, Address(in1, 0));
7842 crc32(in_out, tmp1, 1);
7843 incl(in1);
7844 incl(tmp2);
7845 jmp(L_byteByByte);
7846
7847 BIND(L_exit);
7848 }
7849 #endif // LP64
7850 #undef BIND
7851 #undef BLOCK_COMMENT
7852
7853 // Compress char[] array to byte[].
7854 // ..\jdk\src\java.base\share\classes\java\lang\StringUTF16.java
7855 // @IntrinsicCandidate
7856 // private static int compress(char[] src, int srcOff, byte[] dst, int dstOff, int len) {
7857 // for (int i = 0; i < len; i++) {
7858 // int c = src[srcOff++];
7859 // if (c >>> 8 != 0) {
7860 // return 0;
7861 // }
7862 // dst[dstOff++] = (byte)c;
7863 // }
7864 // return len;
7865 // }
7866 void MacroAssembler::char_array_compress(Register src, Register dst, Register len,
7867 XMMRegister tmp1Reg, XMMRegister tmp2Reg,
7868 XMMRegister tmp3Reg, XMMRegister tmp4Reg,
7869 Register tmp5, Register result, KRegister mask1, KRegister mask2) {
7870 Label copy_chars_loop, return_length, return_zero, done;
7871
7872 // rsi: src
7873 // rdi: dst
7874 // rdx: len
7875 // rcx: tmp5
7876 // rax: result
7877
7878 // rsi holds start addr of source char[] to be compressed
7879 // rdi holds start addr of destination byte[]
7880 // rdx holds length
7881
7882 assert(len != result, "");
7883
7884 // save length for return
7885 push(len);
7886
7887 if ((AVX3Threshold == 0) && (UseAVX > 2) && // AVX512
7888 VM_Version::supports_avx512vlbw() &&
7889 VM_Version::supports_bmi2()) {
7890
7891 Label copy_32_loop, copy_loop_tail, below_threshold;
7892
7893 // alignment
7894 Label post_alignment;
7895
7896 // if length of the string is less than 16, handle it in an old fashioned way
7897 testl(len, -32);
7898 jcc(Assembler::zero, below_threshold);
7899
7900 // First check whether a character is compressable ( <= 0xFF).
7901 // Create mask to test for Unicode chars inside zmm vector
7902 movl(result, 0x00FF);
7903 evpbroadcastw(tmp2Reg, result, Assembler::AVX_512bit);
7904
7905 testl(len, -64);
7906 jcc(Assembler::zero, post_alignment);
7907
7908 movl(tmp5, dst);
7909 andl(tmp5, (32 - 1));
7910 negl(tmp5);
7911 andl(tmp5, (32 - 1));
7912
7913 // bail out when there is nothing to be done
7914 testl(tmp5, 0xFFFFFFFF);
7915 jcc(Assembler::zero, post_alignment);
7916
7917 // ~(~0 << len), where len is the # of remaining elements to process
7918 movl(result, 0xFFFFFFFF);
7919 shlxl(result, result, tmp5);
7920 notl(result);
7921 kmovdl(mask2, result);
7922
7923 evmovdquw(tmp1Reg, mask2, Address(src, 0), /*merge*/ false, Assembler::AVX_512bit);
7924 evpcmpw(mask1, mask2, tmp1Reg, tmp2Reg, Assembler::le, /*signed*/ false, Assembler::AVX_512bit);
7925 ktestd(mask1, mask2);
7926 jcc(Assembler::carryClear, return_zero);
7927
7928 evpmovwb(Address(dst, 0), mask2, tmp1Reg, Assembler::AVX_512bit);
7929
7930 addptr(src, tmp5);
7931 addptr(src, tmp5);
7932 addptr(dst, tmp5);
7933 subl(len, tmp5);
7934
7935 bind(post_alignment);
7936 // end of alignment
7937
7938 movl(tmp5, len);
7939 andl(tmp5, (32 - 1)); // tail count (in chars)
7940 andl(len, ~(32 - 1)); // vector count (in chars)
7941 jcc(Assembler::zero, copy_loop_tail);
7942
7943 lea(src, Address(src, len, Address::times_2));
7944 lea(dst, Address(dst, len, Address::times_1));
7945 negptr(len);
7946
7947 bind(copy_32_loop);
7948 evmovdquw(tmp1Reg, Address(src, len, Address::times_2), /*merge*/ false, Assembler::AVX_512bit);
7949 evpcmpuw(mask1, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit);
7950 kortestdl(mask1, mask1);
7951 jcc(Assembler::carryClear, return_zero);
7952
7953 // All elements in current processed chunk are valid candidates for
7954 // compression. Write a truncated byte elements to the memory.
7955 evpmovwb(Address(dst, len, Address::times_1), tmp1Reg, Assembler::AVX_512bit);
7956 addptr(len, 32);
7957 jcc(Assembler::notZero, copy_32_loop);
7958
7959 bind(copy_loop_tail);
7960 // bail out when there is nothing to be done
7961 testl(tmp5, 0xFFFFFFFF);
7962 jcc(Assembler::zero, return_length);
7963
7964 movl(len, tmp5);
7965
7966 // ~(~0 << len), where len is the # of remaining elements to process
7967 movl(result, 0xFFFFFFFF);
7968 shlxl(result, result, len);
7969 notl(result);
7970
7971 kmovdl(mask2, result);
7972
7973 evmovdquw(tmp1Reg, mask2, Address(src, 0), /*merge*/ false, Assembler::AVX_512bit);
7974 evpcmpw(mask1, mask2, tmp1Reg, tmp2Reg, Assembler::le, /*signed*/ false, Assembler::AVX_512bit);
7975 ktestd(mask1, mask2);
7976 jcc(Assembler::carryClear, return_zero);
7977
7978 evpmovwb(Address(dst, 0), mask2, tmp1Reg, Assembler::AVX_512bit);
7979 jmp(return_length);
7980
7981 bind(below_threshold);
7982 }
7983
7984 if (UseSSE42Intrinsics) {
7985 Label copy_32_loop, copy_16, copy_tail;
7986
7987 movl(result, len);
7988
7989 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vectors
7990
7991 // vectored compression
7992 andl(len, 0xfffffff0); // vector count (in chars)
7993 andl(result, 0x0000000f); // tail count (in chars)
7994 testl(len, len);
7995 jcc(Assembler::zero, copy_16);
7996
7997 // compress 16 chars per iter
7998 movdl(tmp1Reg, tmp5);
7999 pshufd(tmp1Reg, tmp1Reg, 0); // store Unicode mask in tmp1Reg
8000 pxor(tmp4Reg, tmp4Reg);
8001
8002 lea(src, Address(src, len, Address::times_2));
8003 lea(dst, Address(dst, len, Address::times_1));
8004 negptr(len);
8005
8006 bind(copy_32_loop);
8007 movdqu(tmp2Reg, Address(src, len, Address::times_2)); // load 1st 8 characters
8008 por(tmp4Reg, tmp2Reg);
8009 movdqu(tmp3Reg, Address(src, len, Address::times_2, 16)); // load next 8 characters
8010 por(tmp4Reg, tmp3Reg);
8011 ptest(tmp4Reg, tmp1Reg); // check for Unicode chars in next vector
8012 jcc(Assembler::notZero, return_zero);
8013 packuswb(tmp2Reg, tmp3Reg); // only ASCII chars; compress each to 1 byte
8014 movdqu(Address(dst, len, Address::times_1), tmp2Reg);
8015 addptr(len, 16);
8016 jcc(Assembler::notZero, copy_32_loop);
8017
8018 // compress next vector of 8 chars (if any)
8019 bind(copy_16);
8020 movl(len, result);
8021 andl(len, 0xfffffff8); // vector count (in chars)
8022 andl(result, 0x00000007); // tail count (in chars)
8023 testl(len, len);
8024 jccb(Assembler::zero, copy_tail);
8025
8026 movdl(tmp1Reg, tmp5);
8027 pshufd(tmp1Reg, tmp1Reg, 0); // store Unicode mask in tmp1Reg
8028 pxor(tmp3Reg, tmp3Reg);
8029
8030 movdqu(tmp2Reg, Address(src, 0));
8031 ptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector
8032 jccb(Assembler::notZero, return_zero);
8033 packuswb(tmp2Reg, tmp3Reg); // only LATIN1 chars; compress each to 1 byte
8034 movq(Address(dst, 0), tmp2Reg);
8035 addptr(src, 16);
8036 addptr(dst, 8);
8037
8038 bind(copy_tail);
8039 movl(len, result);
8040 }
8041 // compress 1 char per iter
8042 testl(len, len);
8043 jccb(Assembler::zero, return_length);
8044 lea(src, Address(src, len, Address::times_2));
8045 lea(dst, Address(dst, len, Address::times_1));
8046 negptr(len);
8047
8048 bind(copy_chars_loop);
8049 load_unsigned_short(result, Address(src, len, Address::times_2));
8050 testl(result, 0xff00); // check if Unicode char
8051 jccb(Assembler::notZero, return_zero);
8052 movb(Address(dst, len, Address::times_1), result); // ASCII char; compress to 1 byte
8053 increment(len);
8054 jcc(Assembler::notZero, copy_chars_loop);
8055
8056 // if compression succeeded, return length
8057 bind(return_length);
8058 pop(result);
8059 jmpb(done);
8060
8061 // if compression failed, return 0
8062 bind(return_zero);
8063 xorl(result, result);
8064 addptr(rsp, wordSize);
8065
8066 bind(done);
8067 }
8068
8069 // Inflate byte[] array to char[].
8070 // ..\jdk\src\java.base\share\classes\java\lang\StringLatin1.java
8071 // @IntrinsicCandidate
8072 // private static void inflate(byte[] src, int srcOff, char[] dst, int dstOff, int len) {
8073 // for (int i = 0; i < len; i++) {
8074 // dst[dstOff++] = (char)(src[srcOff++] & 0xff);
8075 // }
8076 // }
8077 void MacroAssembler::byte_array_inflate(Register src, Register dst, Register len,
8078 XMMRegister tmp1, Register tmp2, KRegister mask) {
8079 Label copy_chars_loop, done, below_threshold, avx3_threshold;
8080 // rsi: src
8081 // rdi: dst
8082 // rdx: len
8083 // rcx: tmp2
8084
8085 // rsi holds start addr of source byte[] to be inflated
8086 // rdi holds start addr of destination char[]
8087 // rdx holds length
8088 assert_different_registers(src, dst, len, tmp2);
8089 movl(tmp2, len);
8090 if ((UseAVX > 2) && // AVX512
8091 VM_Version::supports_avx512vlbw() &&
8092 VM_Version::supports_bmi2()) {
8093
8094 Label copy_32_loop, copy_tail;
8095 Register tmp3_aliased = len;
8096
8097 // if length of the string is less than 16, handle it in an old fashioned way
8098 testl(len, -16);
8099 jcc(Assembler::zero, below_threshold);
8100
8101 testl(len, -1 * AVX3Threshold);
8102 jcc(Assembler::zero, avx3_threshold);
8103
8104 // In order to use only one arithmetic operation for the main loop we use
8105 // this pre-calculation
8106 andl(tmp2, (32 - 1)); // tail count (in chars), 32 element wide loop
8107 andl(len, -32); // vector count
8108 jccb(Assembler::zero, copy_tail);
8109
8110 lea(src, Address(src, len, Address::times_1));
8111 lea(dst, Address(dst, len, Address::times_2));
8112 negptr(len);
8113
8114
8115 // inflate 32 chars per iter
8116 bind(copy_32_loop);
8117 vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_512bit);
8118 evmovdquw(Address(dst, len, Address::times_2), tmp1, /*merge*/ false, Assembler::AVX_512bit);
8119 addptr(len, 32);
8120 jcc(Assembler::notZero, copy_32_loop);
8121
8122 bind(copy_tail);
8123 // bail out when there is nothing to be done
8124 testl(tmp2, -1); // we don't destroy the contents of tmp2 here
8125 jcc(Assembler::zero, done);
8126
8127 // ~(~0 << length), where length is the # of remaining elements to process
8128 movl(tmp3_aliased, -1);
8129 shlxl(tmp3_aliased, tmp3_aliased, tmp2);
8130 notl(tmp3_aliased);
8131 kmovdl(mask, tmp3_aliased);
8132 evpmovzxbw(tmp1, mask, Address(src, 0), Assembler::AVX_512bit);
8133 evmovdquw(Address(dst, 0), mask, tmp1, /*merge*/ true, Assembler::AVX_512bit);
8134
8135 jmp(done);
8136 bind(avx3_threshold);
8137 }
8138 if (UseSSE42Intrinsics) {
8139 Label copy_16_loop, copy_8_loop, copy_bytes, copy_new_tail, copy_tail;
8140
8141 if (UseAVX > 1) {
8142 andl(tmp2, (16 - 1));
8143 andl(len, -16);
8144 jccb(Assembler::zero, copy_new_tail);
8145 } else {
8146 andl(tmp2, 0x00000007); // tail count (in chars)
8147 andl(len, 0xfffffff8); // vector count (in chars)
8148 jccb(Assembler::zero, copy_tail);
8149 }
8150
8151 // vectored inflation
8152 lea(src, Address(src, len, Address::times_1));
8153 lea(dst, Address(dst, len, Address::times_2));
8154 negptr(len);
8155
8156 if (UseAVX > 1) {
8157 bind(copy_16_loop);
8158 vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_256bit);
8159 vmovdqu(Address(dst, len, Address::times_2), tmp1);
8160 addptr(len, 16);
8161 jcc(Assembler::notZero, copy_16_loop);
8162
8163 bind(below_threshold);
8164 bind(copy_new_tail);
8165 movl(len, tmp2);
8166 andl(tmp2, 0x00000007);
8167 andl(len, 0xFFFFFFF8);
8168 jccb(Assembler::zero, copy_tail);
8169
8170 pmovzxbw(tmp1, Address(src, 0));
8171 movdqu(Address(dst, 0), tmp1);
8172 addptr(src, 8);
8173 addptr(dst, 2 * 8);
8174
8175 jmp(copy_tail, true);
8176 }
8177
8178 // inflate 8 chars per iter
8179 bind(copy_8_loop);
8180 pmovzxbw(tmp1, Address(src, len, Address::times_1)); // unpack to 8 words
8181 movdqu(Address(dst, len, Address::times_2), tmp1);
8182 addptr(len, 8);
8183 jcc(Assembler::notZero, copy_8_loop);
8184
8185 bind(copy_tail);
8186 movl(len, tmp2);
8187
8188 cmpl(len, 4);
8189 jccb(Assembler::less, copy_bytes);
8190
8191 movdl(tmp1, Address(src, 0)); // load 4 byte chars
8192 pmovzxbw(tmp1, tmp1);
8193 movq(Address(dst, 0), tmp1);
8194 subptr(len, 4);
8195 addptr(src, 4);
8196 addptr(dst, 8);
8197
8198 bind(copy_bytes);
8199 } else {
8200 bind(below_threshold);
8201 }
8202
8203 testl(len, len);
8204 jccb(Assembler::zero, done);
8205 lea(src, Address(src, len, Address::times_1));
8206 lea(dst, Address(dst, len, Address::times_2));
8207 negptr(len);
8208
8209 // inflate 1 char per iter
8210 bind(copy_chars_loop);
8211 load_unsigned_byte(tmp2, Address(src, len, Address::times_1)); // load byte char
8212 movw(Address(dst, len, Address::times_2), tmp2); // inflate byte char to word
8213 increment(len);
8214 jcc(Assembler::notZero, copy_chars_loop);
8215
8216 bind(done);
8217 }
8218
8219
8220 void MacroAssembler::evmovdqu(BasicType type, KRegister kmask, XMMRegister dst, Address src, int vector_len) {
8221 switch(type) {
8222 case T_BYTE:
8223 case T_BOOLEAN:
8224 evmovdqub(dst, kmask, src, false, vector_len);
8225 break;
8226 case T_CHAR:
8227 case T_SHORT:
8228 evmovdquw(dst, kmask, src, false, vector_len);
8229 break;
8230 case T_INT:
8231 case T_FLOAT:
8232 evmovdqul(dst, kmask, src, false, vector_len);
8233 break;
8234 case T_LONG:
8235 case T_DOUBLE:
8236 evmovdquq(dst, kmask, src, false, vector_len);
8237 break;
8238 default:
8239 fatal("Unexpected type argument %s", type2name(type));
8240 break;
8241 }
8242 }
8243
8244 void MacroAssembler::evmovdqu(BasicType type, KRegister kmask, Address dst, XMMRegister src, int vector_len) {
8245 switch(type) {
8246 case T_BYTE:
8247 case T_BOOLEAN:
8248 evmovdqub(dst, kmask, src, true, vector_len);
8249 break;
8250 case T_CHAR:
8251 case T_SHORT:
8252 evmovdquw(dst, kmask, src, true, vector_len);
8253 break;
8254 case T_INT:
8255 case T_FLOAT:
8256 evmovdqul(dst, kmask, src, true, vector_len);
8257 break;
8258 case T_LONG:
8259 case T_DOUBLE:
8260 evmovdquq(dst, kmask, src, true, vector_len);
8261 break;
8262 default:
8263 fatal("Unexpected type argument %s", type2name(type));
8264 break;
8265 }
8266 }
8267
8268 void MacroAssembler::knot(uint masklen, KRegister dst, KRegister src, KRegister ktmp, Register rtmp) {
8269 switch(masklen) {
8270 case 2:
8271 knotbl(dst, src);
8272 movl(rtmp, 3);
8273 kmovbl(ktmp, rtmp);
8274 kandbl(dst, ktmp, dst);
8275 break;
8276 case 4:
8277 knotbl(dst, src);
8278 movl(rtmp, 15);
8279 kmovbl(ktmp, rtmp);
8280 kandbl(dst, ktmp, dst);
8281 break;
8282 case 8:
8283 knotbl(dst, src);
8284 break;
8285 case 16:
8286 knotwl(dst, src);
8287 break;
8288 case 32:
8289 knotdl(dst, src);
8290 break;
8291 case 64:
8292 knotql(dst, src);
8293 break;
8294 default:
8295 fatal("Unexpected vector length %d", masklen);
8296 break;
8297 }
8298 }
8299
8300 void MacroAssembler::kand(BasicType type, KRegister dst, KRegister src1, KRegister src2) {
8301 switch(type) {
8302 case T_BOOLEAN:
8303 case T_BYTE:
8304 kandbl(dst, src1, src2);
8305 break;
8306 case T_CHAR:
8307 case T_SHORT:
8308 kandwl(dst, src1, src2);
8309 break;
8310 case T_INT:
8311 case T_FLOAT:
8312 kanddl(dst, src1, src2);
8313 break;
8314 case T_LONG:
8315 case T_DOUBLE:
8316 kandql(dst, src1, src2);
8317 break;
8318 default:
8319 fatal("Unexpected type argument %s", type2name(type));
8320 break;
8321 }
8322 }
8323
8324 void MacroAssembler::kor(BasicType type, KRegister dst, KRegister src1, KRegister src2) {
8325 switch(type) {
8326 case T_BOOLEAN:
8327 case T_BYTE:
8328 korbl(dst, src1, src2);
8329 break;
8330 case T_CHAR:
8331 case T_SHORT:
8332 korwl(dst, src1, src2);
8333 break;
8334 case T_INT:
8335 case T_FLOAT:
8336 kordl(dst, src1, src2);
8337 break;
8338 case T_LONG:
8339 case T_DOUBLE:
8340 korql(dst, src1, src2);
8341 break;
8342 default:
8343 fatal("Unexpected type argument %s", type2name(type));
8344 break;
8345 }
8346 }
8347
8348 void MacroAssembler::kxor(BasicType type, KRegister dst, KRegister src1, KRegister src2) {
8349 switch(type) {
8350 case T_BOOLEAN:
8351 case T_BYTE:
8352 kxorbl(dst, src1, src2);
8353 break;
8354 case T_CHAR:
8355 case T_SHORT:
8356 kxorwl(dst, src1, src2);
8357 break;
8358 case T_INT:
8359 case T_FLOAT:
8360 kxordl(dst, src1, src2);
8361 break;
8362 case T_LONG:
8363 case T_DOUBLE:
8364 kxorql(dst, src1, src2);
8365 break;
8366 default:
8367 fatal("Unexpected type argument %s", type2name(type));
8368 break;
8369 }
8370 }
8371
8372 void MacroAssembler::evperm(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
8373 switch(type) {
8374 case T_BOOLEAN:
8375 case T_BYTE:
8376 evpermb(dst, mask, nds, src, merge, vector_len); break;
8377 case T_CHAR:
8378 case T_SHORT:
8379 evpermw(dst, mask, nds, src, merge, vector_len); break;
8380 case T_INT:
8381 case T_FLOAT:
8382 evpermd(dst, mask, nds, src, merge, vector_len); break;
8383 case T_LONG:
8384 case T_DOUBLE:
8385 evpermq(dst, mask, nds, src, merge, vector_len); break;
8386 default:
8387 fatal("Unexpected type argument %s", type2name(type)); break;
8388 }
8389 }
8390
8391 void MacroAssembler::evperm(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
8392 switch(type) {
8393 case T_BOOLEAN:
8394 case T_BYTE:
8395 evpermb(dst, mask, nds, src, merge, vector_len); break;
8396 case T_CHAR:
8397 case T_SHORT:
8398 evpermw(dst, mask, nds, src, merge, vector_len); break;
8399 case T_INT:
8400 case T_FLOAT:
8401 evpermd(dst, mask, nds, src, merge, vector_len); break;
8402 case T_LONG:
8403 case T_DOUBLE:
8404 evpermq(dst, mask, nds, src, merge, vector_len); break;
8405 default:
8406 fatal("Unexpected type argument %s", type2name(type)); break;
8407 }
8408 }
8409
8410 void MacroAssembler::evpmins(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
8411 switch(type) {
8412 case T_BYTE:
8413 evpminsb(dst, mask, nds, src, merge, vector_len); break;
8414 case T_SHORT:
8415 evpminsw(dst, mask, nds, src, merge, vector_len); break;
8416 case T_INT:
8417 evpminsd(dst, mask, nds, src, merge, vector_len); break;
8418 case T_LONG:
8419 evpminsq(dst, mask, nds, src, merge, vector_len); break;
8420 default:
8421 fatal("Unexpected type argument %s", type2name(type)); break;
8422 }
8423 }
8424
8425 void MacroAssembler::evpmaxs(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
8426 switch(type) {
8427 case T_BYTE:
8428 evpmaxsb(dst, mask, nds, src, merge, vector_len); break;
8429 case T_SHORT:
8430 evpmaxsw(dst, mask, nds, src, merge, vector_len); break;
8431 case T_INT:
8432 evpmaxsd(dst, mask, nds, src, merge, vector_len); break;
8433 case T_LONG:
8434 evpmaxsq(dst, mask, nds, src, merge, vector_len); break;
8435 default:
8436 fatal("Unexpected type argument %s", type2name(type)); break;
8437 }
8438 }
8439
8440 void MacroAssembler::evpmins(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
8441 switch(type) {
8442 case T_BYTE:
8443 evpminsb(dst, mask, nds, src, merge, vector_len); break;
8444 case T_SHORT:
8445 evpminsw(dst, mask, nds, src, merge, vector_len); break;
8446 case T_INT:
8447 evpminsd(dst, mask, nds, src, merge, vector_len); break;
8448 case T_LONG:
8449 evpminsq(dst, mask, nds, src, merge, vector_len); break;
8450 default:
8451 fatal("Unexpected type argument %s", type2name(type)); break;
8452 }
8453 }
8454
8455 void MacroAssembler::evpmaxs(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
8456 switch(type) {
8457 case T_BYTE:
8458 evpmaxsb(dst, mask, nds, src, merge, vector_len); break;
8459 case T_SHORT:
8460 evpmaxsw(dst, mask, nds, src, merge, vector_len); break;
8461 case T_INT:
8462 evpmaxsd(dst, mask, nds, src, merge, vector_len); break;
8463 case T_LONG:
8464 evpmaxsq(dst, mask, nds, src, merge, vector_len); break;
8465 default:
8466 fatal("Unexpected type argument %s", type2name(type)); break;
8467 }
8468 }
8469
8470 void MacroAssembler::evxor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
8471 switch(type) {
8472 case T_INT:
8473 evpxord(dst, mask, nds, src, merge, vector_len); break;
8474 case T_LONG:
8475 evpxorq(dst, mask, nds, src, merge, vector_len); break;
8476 default:
8477 fatal("Unexpected type argument %s", type2name(type)); break;
8478 }
8479 }
8480
8481 void MacroAssembler::evxor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
8482 switch(type) {
8483 case T_INT:
8484 evpxord(dst, mask, nds, src, merge, vector_len); break;
8485 case T_LONG:
8486 evpxorq(dst, mask, nds, src, merge, vector_len); break;
8487 default:
8488 fatal("Unexpected type argument %s", type2name(type)); break;
8489 }
8490 }
8491
8492 void MacroAssembler::evor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
8493 switch(type) {
8494 case T_INT:
8495 Assembler::evpord(dst, mask, nds, src, merge, vector_len); break;
8496 case T_LONG:
8497 evporq(dst, mask, nds, src, merge, vector_len); break;
8498 default:
8499 fatal("Unexpected type argument %s", type2name(type)); break;
8500 }
8501 }
8502
8503 void MacroAssembler::evor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
8504 switch(type) {
8505 case T_INT:
8506 Assembler::evpord(dst, mask, nds, src, merge, vector_len); break;
8507 case T_LONG:
8508 evporq(dst, mask, nds, src, merge, vector_len); break;
8509 default:
8510 fatal("Unexpected type argument %s", type2name(type)); break;
8511 }
8512 }
8513
8514 void MacroAssembler::evand(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
8515 switch(type) {
8516 case T_INT:
8517 evpandd(dst, mask, nds, src, merge, vector_len); break;
8518 case T_LONG:
8519 evpandq(dst, mask, nds, src, merge, vector_len); break;
8520 default:
8521 fatal("Unexpected type argument %s", type2name(type)); break;
8522 }
8523 }
8524
8525 void MacroAssembler::evand(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
8526 switch(type) {
8527 case T_INT:
8528 evpandd(dst, mask, nds, src, merge, vector_len); break;
8529 case T_LONG:
8530 evpandq(dst, mask, nds, src, merge, vector_len); break;
8531 default:
8532 fatal("Unexpected type argument %s", type2name(type)); break;
8533 }
8534 }
8535
8536 void MacroAssembler::anytrue(Register dst, uint masklen, KRegister src1, KRegister src2) {
8537 masklen = masklen < 8 ? 8 : masklen;
8538 ktest(masklen, src1, src2);
8539 setb(Assembler::notZero, dst);
8540 movzbl(dst, dst);
8541 }
8542
8543 void MacroAssembler::alltrue(Register dst, uint masklen, KRegister src1, KRegister src2, KRegister kscratch) {
8544 if (masklen < 8) {
8545 knotbl(kscratch, src2);
8546 kortestbl(src1, kscratch);
8547 setb(Assembler::carrySet, dst);
8548 movzbl(dst, dst);
8549 } else {
8550 ktest(masklen, src1, src2);
8551 setb(Assembler::carrySet, dst);
8552 movzbl(dst, dst);
8553 }
8554 }
8555
8556 void MacroAssembler::kortest(uint masklen, KRegister src1, KRegister src2) {
8557 switch(masklen) {
8558 case 8:
8559 kortestbl(src1, src2);
8560 break;
8561 case 16:
8562 kortestwl(src1, src2);
8563 break;
8564 case 32:
8565 kortestdl(src1, src2);
8566 break;
8567 case 64:
8568 kortestql(src1, src2);
8569 break;
8570 default:
8571 fatal("Unexpected mask length %d", masklen);
8572 break;
8573 }
8574 }
8575
8576
8577 void MacroAssembler::ktest(uint masklen, KRegister src1, KRegister src2) {
8578 switch(masklen) {
8579 case 8:
8580 ktestbl(src1, src2);
8581 break;
8582 case 16:
8583 ktestwl(src1, src2);
8584 break;
8585 case 32:
8586 ktestdl(src1, src2);
8587 break;
8588 case 64:
8589 ktestql(src1, src2);
8590 break;
8591 default:
8592 fatal("Unexpected mask length %d", masklen);
8593 break;
8594 }
8595 }
8596
8597 void MacroAssembler::evrold(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vlen_enc) {
8598 switch(type) {
8599 case T_INT:
8600 evprold(dst, mask, src, shift, merge, vlen_enc); break;
8601 case T_LONG:
8602 evprolq(dst, mask, src, shift, merge, vlen_enc); break;
8603 default:
8604 fatal("Unexpected type argument %s", type2name(type)); break;
8605 break;
8606 }
8607 }
8608
8609 void MacroAssembler::evrord(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vlen_enc) {
8610 switch(type) {
8611 case T_INT:
8612 evprord(dst, mask, src, shift, merge, vlen_enc); break;
8613 case T_LONG:
8614 evprorq(dst, mask, src, shift, merge, vlen_enc); break;
8615 default:
8616 fatal("Unexpected type argument %s", type2name(type)); break;
8617 }
8618 }
8619
8620 void MacroAssembler::evrold(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src1, XMMRegister src2, bool merge, int vlen_enc) {
8621 switch(type) {
8622 case T_INT:
8623 evprolvd(dst, mask, src1, src2, merge, vlen_enc); break;
8624 case T_LONG:
8625 evprolvq(dst, mask, src1, src2, merge, vlen_enc); break;
8626 default:
8627 fatal("Unexpected type argument %s", type2name(type)); break;
8628 }
8629 }
8630
8631 void MacroAssembler::evrord(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src1, XMMRegister src2, bool merge, int vlen_enc) {
8632 switch(type) {
8633 case T_INT:
8634 evprorvd(dst, mask, src1, src2, merge, vlen_enc); break;
8635 case T_LONG:
8636 evprorvq(dst, mask, src1, src2, merge, vlen_enc); break;
8637 default:
8638 fatal("Unexpected type argument %s", type2name(type)); break;
8639 }
8640 }
8641 #if COMPILER2_OR_JVMCI
8642
8643 void MacroAssembler::fill_masked(BasicType bt, Address dst, XMMRegister xmm, KRegister mask,
8644 Register length, Register temp, int vec_enc) {
8645 // Computing mask for predicated vector store.
8646 movptr(temp, -1);
8647 bzhiq(temp, temp, length);
8648 kmov(mask, temp);
8649 evmovdqu(bt, mask, dst, xmm, vec_enc);
8650 }
8651
8652 // Set memory operation for length "less than" 64 bytes.
8653 void MacroAssembler::fill64_masked(uint shift, Register dst, int disp,
8654 XMMRegister xmm, KRegister mask, Register length,
8655 Register temp, bool use64byteVector) {
8656 assert(MaxVectorSize >= 32, "vector length should be >= 32");
8657 BasicType type[] = { T_BYTE, T_SHORT, T_INT, T_LONG};
8658 if (!use64byteVector) {
8659 fill32(dst, disp, xmm);
8660 subptr(length, 32 >> shift);
8661 fill32_masked(shift, dst, disp + 32, xmm, mask, length, temp);
8662 } else {
8663 assert(MaxVectorSize == 64, "vector length != 64");
8664 fill_masked(type[shift], Address(dst, disp), xmm, mask, length, temp, Assembler::AVX_512bit);
8665 }
8666 }
8667
8668
8669 void MacroAssembler::fill32_masked(uint shift, Register dst, int disp,
8670 XMMRegister xmm, KRegister mask, Register length,
8671 Register temp) {
8672 assert(MaxVectorSize >= 32, "vector length should be >= 32");
8673 BasicType type[] = { T_BYTE, T_SHORT, T_INT, T_LONG};
8674 fill_masked(type[shift], Address(dst, disp), xmm, mask, length, temp, Assembler::AVX_256bit);
8675 }
8676
8677
8678 void MacroAssembler::fill32(Register dst, int disp, XMMRegister xmm) {
8679 assert(MaxVectorSize >= 32, "vector length should be >= 32");
8680 vmovdqu(Address(dst, disp), xmm);
8681 }
8682
8683 void MacroAssembler::fill64(Register dst, int disp, XMMRegister xmm, bool use64byteVector) {
8684 assert(MaxVectorSize >= 32, "vector length should be >= 32");
8685 BasicType type[] = {T_BYTE, T_SHORT, T_INT, T_LONG};
8686 if (!use64byteVector) {
8687 fill32(dst, disp, xmm);
8688 fill32(dst, disp + 32, xmm);
8689 } else {
8690 evmovdquq(Address(dst, disp), xmm, Assembler::AVX_512bit);
8691 }
8692 }
8693
8694 #ifdef _LP64
8695 void MacroAssembler::generate_fill_avx3(BasicType type, Register to, Register value,
8696 Register count, Register rtmp, XMMRegister xtmp) {
8697 Label L_exit;
8698 Label L_fill_start;
8699 Label L_fill_64_bytes;
8700 Label L_fill_96_bytes;
8701 Label L_fill_128_bytes;
8702 Label L_fill_128_bytes_loop;
8703 Label L_fill_128_loop_header;
8704 Label L_fill_128_bytes_loop_header;
8705 Label L_fill_128_bytes_loop_pre_header;
8706 Label L_fill_zmm_sequence;
8707
8708 int shift = -1;
8709 switch(type) {
8710 case T_BYTE: shift = 0;
8711 break;
8712 case T_SHORT: shift = 1;
8713 break;
8714 case T_INT: shift = 2;
8715 break;
8716 /* Uncomment when LONG fill stubs are supported.
8717 case T_LONG: shift = 3;
8718 break;
8719 */
8720 default:
8721 fatal("Unhandled type: %s\n", type2name(type));
8722 }
8723
8724 if (AVX3Threshold != 0 || MaxVectorSize == 32) {
8725
8726 if (MaxVectorSize == 64) {
8727 cmpq(count, AVX3Threshold >> shift);
8728 jcc(Assembler::greater, L_fill_zmm_sequence);
8729 }
8730
8731 evpbroadcast(type, xtmp, value, Assembler::AVX_256bit);
8732
8733 bind(L_fill_start);
8734
8735 cmpq(count, 32 >> shift);
8736 jccb(Assembler::greater, L_fill_64_bytes);
8737 fill32_masked(shift, to, 0, xtmp, k2, count, rtmp);
8738 jmp(L_exit);
8739
8740 bind(L_fill_64_bytes);
8741 cmpq(count, 64 >> shift);
8742 jccb(Assembler::greater, L_fill_96_bytes);
8743 fill64_masked(shift, to, 0, xtmp, k2, count, rtmp);
8744 jmp(L_exit);
8745
8746 bind(L_fill_96_bytes);
8747 cmpq(count, 96 >> shift);
8748 jccb(Assembler::greater, L_fill_128_bytes);
8749 fill64(to, 0, xtmp);
8750 subq(count, 64 >> shift);
8751 fill32_masked(shift, to, 64, xtmp, k2, count, rtmp);
8752 jmp(L_exit);
8753
8754 bind(L_fill_128_bytes);
8755 cmpq(count, 128 >> shift);
8756 jccb(Assembler::greater, L_fill_128_bytes_loop_pre_header);
8757 fill64(to, 0, xtmp);
8758 fill32(to, 64, xtmp);
8759 subq(count, 96 >> shift);
8760 fill32_masked(shift, to, 96, xtmp, k2, count, rtmp);
8761 jmp(L_exit);
8762
8763 bind(L_fill_128_bytes_loop_pre_header);
8764 {
8765 mov(rtmp, to);
8766 andq(rtmp, 31);
8767 jccb(Assembler::zero, L_fill_128_bytes_loop_header);
8768 negq(rtmp);
8769 addq(rtmp, 32);
8770 mov64(r8, -1L);
8771 bzhiq(r8, r8, rtmp);
8772 kmovql(k2, r8);
8773 evmovdqu(T_BYTE, k2, Address(to, 0), xtmp, Assembler::AVX_256bit);
8774 addq(to, rtmp);
8775 shrq(rtmp, shift);
8776 subq(count, rtmp);
8777 }
8778
8779 cmpq(count, 128 >> shift);
8780 jcc(Assembler::less, L_fill_start);
8781
8782 bind(L_fill_128_bytes_loop_header);
8783 subq(count, 128 >> shift);
8784
8785 align32();
8786 bind(L_fill_128_bytes_loop);
8787 fill64(to, 0, xtmp);
8788 fill64(to, 64, xtmp);
8789 addq(to, 128);
8790 subq(count, 128 >> shift);
8791 jccb(Assembler::greaterEqual, L_fill_128_bytes_loop);
8792
8793 addq(count, 128 >> shift);
8794 jcc(Assembler::zero, L_exit);
8795 jmp(L_fill_start);
8796 }
8797
8798 if (MaxVectorSize == 64) {
8799 // Sequence using 64 byte ZMM register.
8800 Label L_fill_128_bytes_zmm;
8801 Label L_fill_192_bytes_zmm;
8802 Label L_fill_192_bytes_loop_zmm;
8803 Label L_fill_192_bytes_loop_header_zmm;
8804 Label L_fill_192_bytes_loop_pre_header_zmm;
8805 Label L_fill_start_zmm_sequence;
8806
8807 bind(L_fill_zmm_sequence);
8808 evpbroadcast(type, xtmp, value, Assembler::AVX_512bit);
8809
8810 bind(L_fill_start_zmm_sequence);
8811 cmpq(count, 64 >> shift);
8812 jccb(Assembler::greater, L_fill_128_bytes_zmm);
8813 fill64_masked(shift, to, 0, xtmp, k2, count, rtmp, true);
8814 jmp(L_exit);
8815
8816 bind(L_fill_128_bytes_zmm);
8817 cmpq(count, 128 >> shift);
8818 jccb(Assembler::greater, L_fill_192_bytes_zmm);
8819 fill64(to, 0, xtmp, true);
8820 subq(count, 64 >> shift);
8821 fill64_masked(shift, to, 64, xtmp, k2, count, rtmp, true);
8822 jmp(L_exit);
8823
8824 bind(L_fill_192_bytes_zmm);
8825 cmpq(count, 192 >> shift);
8826 jccb(Assembler::greater, L_fill_192_bytes_loop_pre_header_zmm);
8827 fill64(to, 0, xtmp, true);
8828 fill64(to, 64, xtmp, true);
8829 subq(count, 128 >> shift);
8830 fill64_masked(shift, to, 128, xtmp, k2, count, rtmp, true);
8831 jmp(L_exit);
8832
8833 bind(L_fill_192_bytes_loop_pre_header_zmm);
8834 {
8835 movq(rtmp, to);
8836 andq(rtmp, 63);
8837 jccb(Assembler::zero, L_fill_192_bytes_loop_header_zmm);
8838 negq(rtmp);
8839 addq(rtmp, 64);
8840 mov64(r8, -1L);
8841 bzhiq(r8, r8, rtmp);
8842 kmovql(k2, r8);
8843 evmovdqu(T_BYTE, k2, Address(to, 0), xtmp, Assembler::AVX_512bit);
8844 addq(to, rtmp);
8845 shrq(rtmp, shift);
8846 subq(count, rtmp);
8847 }
8848
8849 cmpq(count, 192 >> shift);
8850 jcc(Assembler::less, L_fill_start_zmm_sequence);
8851
8852 bind(L_fill_192_bytes_loop_header_zmm);
8853 subq(count, 192 >> shift);
8854
8855 align32();
8856 bind(L_fill_192_bytes_loop_zmm);
8857 fill64(to, 0, xtmp, true);
8858 fill64(to, 64, xtmp, true);
8859 fill64(to, 128, xtmp, true);
8860 addq(to, 192);
8861 subq(count, 192 >> shift);
8862 jccb(Assembler::greaterEqual, L_fill_192_bytes_loop_zmm);
8863
8864 addq(count, 192 >> shift);
8865 jcc(Assembler::zero, L_exit);
8866 jmp(L_fill_start_zmm_sequence);
8867 }
8868 bind(L_exit);
8869 }
8870 #endif
8871 #endif //COMPILER2_OR_JVMCI
8872
8873
8874 #ifdef _LP64
8875 void MacroAssembler::convert_f2i(Register dst, XMMRegister src) {
8876 Label done;
8877 cvttss2sil(dst, src);
8878 // Conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
8879 cmpl(dst, 0x80000000); // float_sign_flip
8880 jccb(Assembler::notEqual, done);
8881 subptr(rsp, 8);
8882 movflt(Address(rsp, 0), src);
8883 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2i_fixup())));
8884 pop(dst);
8885 bind(done);
8886 }
8887
8888 void MacroAssembler::convert_d2i(Register dst, XMMRegister src) {
8889 Label done;
8890 cvttsd2sil(dst, src);
8891 // Conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
8892 cmpl(dst, 0x80000000); // float_sign_flip
8893 jccb(Assembler::notEqual, done);
8894 subptr(rsp, 8);
8895 movdbl(Address(rsp, 0), src);
8896 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2i_fixup())));
8897 pop(dst);
8898 bind(done);
8899 }
8900
8901 void MacroAssembler::convert_f2l(Register dst, XMMRegister src) {
8902 Label done;
8903 cvttss2siq(dst, src);
8904 cmp64(dst, ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
8905 jccb(Assembler::notEqual, done);
8906 subptr(rsp, 8);
8907 movflt(Address(rsp, 0), src);
8908 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2l_fixup())));
8909 pop(dst);
8910 bind(done);
8911 }
8912
8913 void MacroAssembler::convert_d2l(Register dst, XMMRegister src) {
8914 Label done;
8915 cvttsd2siq(dst, src);
8916 cmp64(dst, ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
8917 jccb(Assembler::notEqual, done);
8918 subptr(rsp, 8);
8919 movdbl(Address(rsp, 0), src);
8920 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2l_fixup())));
8921 pop(dst);
8922 bind(done);
8923 }
8924
8925 void MacroAssembler::cache_wb(Address line)
8926 {
8927 // 64 bit cpus always support clflush
8928 assert(VM_Version::supports_clflush(), "clflush should be available");
8929 bool optimized = VM_Version::supports_clflushopt();
8930 bool no_evict = VM_Version::supports_clwb();
8931
8932 // prefer clwb (writeback without evict) otherwise
8933 // prefer clflushopt (potentially parallel writeback with evict)
8934 // otherwise fallback on clflush (serial writeback with evict)
8935
8936 if (optimized) {
8937 if (no_evict) {
8938 clwb(line);
8939 } else {
8940 clflushopt(line);
8941 }
8942 } else {
8943 // no need for fence when using CLFLUSH
8944 clflush(line);
8945 }
8946 }
8947
8948 void MacroAssembler::cache_wbsync(bool is_pre)
8949 {
8950 assert(VM_Version::supports_clflush(), "clflush should be available");
8951 bool optimized = VM_Version::supports_clflushopt();
8952 bool no_evict = VM_Version::supports_clwb();
8953
8954 // pick the correct implementation
8955
8956 if (!is_pre && (optimized || no_evict)) {
8957 // need an sfence for post flush when using clflushopt or clwb
8958 // otherwise no no need for any synchroniaztion
8959
8960 sfence();
8961 }
8962 }
8963
8964 #endif // _LP64
8965
8966 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) {
8967 switch (cond) {
8968 // Note some conditions are synonyms for others
8969 case Assembler::zero: return Assembler::notZero;
8970 case Assembler::notZero: return Assembler::zero;
8971 case Assembler::less: return Assembler::greaterEqual;
8972 case Assembler::lessEqual: return Assembler::greater;
8973 case Assembler::greater: return Assembler::lessEqual;
8974 case Assembler::greaterEqual: return Assembler::less;
8975 case Assembler::below: return Assembler::aboveEqual;
8976 case Assembler::belowEqual: return Assembler::above;
8977 case Assembler::above: return Assembler::belowEqual;
8978 case Assembler::aboveEqual: return Assembler::below;
8979 case Assembler::overflow: return Assembler::noOverflow;
8980 case Assembler::noOverflow: return Assembler::overflow;
8981 case Assembler::negative: return Assembler::positive;
8982 case Assembler::positive: return Assembler::negative;
8983 case Assembler::parity: return Assembler::noParity;
8984 case Assembler::noParity: return Assembler::parity;
8985 }
8986 ShouldNotReachHere(); return Assembler::overflow;
8987 }
8988
8989 SkipIfEqual::SkipIfEqual(
8990 MacroAssembler* masm, const bool* flag_addr, bool value) {
8991 _masm = masm;
8992 _masm->cmp8(ExternalAddress((address)flag_addr), value);
8993 _masm->jcc(Assembler::equal, _label);
8994 }
8995
8996 SkipIfEqual::~SkipIfEqual() {
8997 _masm->bind(_label);
8998 }
8999
9000 // 32-bit Windows has its own fast-path implementation
9001 // of get_thread
9002 #if !defined(WIN32) || defined(_LP64)
9003
9004 // This is simply a call to Thread::current()
9005 void MacroAssembler::get_thread(Register thread) {
9006 if (thread != rax) {
9007 push(rax);
9008 }
9009 LP64_ONLY(push(rdi);)
9010 LP64_ONLY(push(rsi);)
9011 push(rdx);
9012 push(rcx);
9013 #ifdef _LP64
9014 push(r8);
9015 push(r9);
9016 push(r10);
9017 push(r11);
9018 #endif
9019
9020 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, Thread::current), 0);
9021
9022 #ifdef _LP64
9023 pop(r11);
9024 pop(r10);
9025 pop(r9);
9026 pop(r8);
9027 #endif
9028 pop(rcx);
9029 pop(rdx);
9030 LP64_ONLY(pop(rsi);)
9031 LP64_ONLY(pop(rdi);)
9032 if (thread != rax) {
9033 mov(thread, rax);
9034 pop(rax);
9035 }
9036 }
9037
9038 #endif // !WIN32 || _LP64